[ { "path": ".clang-format", "content": "# https://clang.llvm.org/docs/ClangFormat.html\n# https://clang.llvm.org/docs/ClangFormatStyleOptions.html\n---\nLanguage: Cpp\nAlignAfterOpenBracket: Align\nAlignConsecutiveAssignments: false\nAlignConsecutiveDeclarations: false\nAlignEscapedNewlinesLeft: true\nAlignOperands: true\nAlignTrailingComments: false # churn\nAllowShortBlocksOnASingleLine: false\nAllowShortCaseLabelsOnASingleLine: false\nAllowShortFunctionsOnASingleLine: None\nAllowShortIfStatementsOnASingleLine: false\nAllowShortLoopsOnASingleLine: false\nAlwaysBreakAfterReturnType: None\nAlwaysBreakBeforeMultilineStrings: false\nBinPackArguments: false\nBinPackParameters: false\nAllowAllParametersOfDeclarationOnNextLine: false\nAllowAllArgumentsOnNextLine: true\nBraceWrapping:\n AfterControlStatement: false\n AfterEnum: false\n AfterFunction: true\n AfterStruct: false\n AfterUnion: false\n BeforeElse: false\n IndentBraces: false\nBreakBeforeBinaryOperators: None\nBreakBeforeBraces: Custom\nBreakBeforeTernaryOperators: false\nBreakStringLiterals: true\nColumnLimit: 120\nContinuationIndentWidth: 4\nCpp11BracedListStyle: false\nDerivePointerAlignment: false\nDisableFormat: false\nIncludeIsMainRegex: '$'\nIndentCaseLabels: false\nIndentWidth: 4\nAccessModifierOffset: -4\nIndentWrappedFunctionNames: false\nKeepEmptyLinesAtTheStartOfBlocks: false\nMacroBlockBegin: '.*_BEGIN$' # only PREC_BEGIN ?\nMacroBlockEnd: '.*_END$'\nMaxEmptyLinesToKeep: 2\nPointerAlignment: Right\nReflowComments: true\nSortIncludes: true\nSpaceAfterCStyleCast: false\nSpaceBeforeAssignmentOperators: true\nSpaceBeforeParens: ControlStatements\nSpaceInEmptyParentheses: false\nSpacesBeforeTrailingComments: 1\nSpacesInContainerLiterals: true\nSpacesInParentheses: false\nSpacesInSquareBrackets: false\nStandard: Auto\nUseTab: Never\n...\n" }, { "path": ".github/ISSUE_TEMPLATE/bug-report.yml", "content": "name: Report a bug\ndescription: Report a bug in pypcode\nlabels: [bug,needs-triage]\nbody:\n - type: markdown\n attributes:\n value: |\n Thank you for taking the time to submit this bug report!\n\n Before submitting this bug report, please check the following, which may resolve your issue:\n * Have you checked that you are running the latest versions of angr and its components? angr is rapidly-evolving!\n * Have you [searched existing issues](https://github.com/angr/pypcode/issues?q=is%3Aopen+is%3Aissue+label%3Abug) to see if this bug has been reported before?\n * Have you checked the [documentation](https://docs.angr.io/)?\n * Have you checked the [FAQ](https://docs.angr.io/introductory-errata/faq)?\n\n **Important:** If this bug is a security vulnerability, please submit it privately. See our [security policy](https://github.com/angr/angr/blob/master/SECURITY.md) for more details.\n\n Please note: The angr suite is maintained by a small team. While we cannot guarantee any timeliness for fixes and enhancements, we will do our best. For more real-time help with angr, from us and the community, join our [Slack](https://angr.io/invite/).\n\n - type: textarea\n attributes:\n label: Description\n description: Brief description of the bug, with any relevant log messages.\n validations:\n required: true\n\n - type: textarea\n attributes:\n label: Steps to reproduce the bug\n description: |\n If appropriate, include both a **script to reproduce the bug**, and if possible **attach the binary used**.\n\n **Tip:** You can attach files to the issue by first clicking on the textarea to select it, then dragging & dropping the file onto the textarea.\n - type: textarea\n attributes:\n label: Environment\n description: Many common issues are caused by problems with the local Python environment. Before submitting, double-check that your versions of all modules in the angr suite (angr, cle, pyvex, ...) are up to date and include the output of `python -m angr.misc.bug_report` here.\n\n - type: textarea\n attributes:\n label: Additional context\n description: Any additional context about the problem.\n" }, { "path": ".github/ISSUE_TEMPLATE/config.yml", "content": "blank_issues_enabled: false\ncontact_links:\n - name: Join our Slack community\n url: https://angr.io/invite/\n about: For questions and help with angr, you are invited to join the angr Slack community\n" }, { "path": ".github/ISSUE_TEMPLATE/feature-request.yml", "content": "name: Request a feature\ndescription: Request a new feature for pypcode\nlabels: [enhancement,needs-triage]\nbody:\n - type: markdown\n attributes:\n value: |\n Thank you for taking the time to submit this feature request!\n\n Before submitting this feature request, please check the following:\n * Have you checked that you are running the latest versions of angr and its components? angr is rapidly-evolving!\n * Have you checked the [documentation](https://docs.angr.io/) to see if this feature exists already?\n * Have you [searched existing issues](https://github.com/angr/pypcode/issues?q=is%3Aissue+label%3Aenhancement+) to see if this feature has been requested before?\n\n Please note: The angr suite is maintained by a small team. While we cannot guarantee any timeliness for fixes and enhancements, we will do our best. For more real-time help with angr, from us and the community, join our [Slack](https://angr.io/invite/).\n\n - type: textarea\n attributes:\n label: Description\n description: |\n Brief description of the desired feature. If the feature is intended to solve some problem, please clearly describe the problem, including any relevant binaries, etc.\n\n **Tip:** You can attach files to the issue by first clicking on the textarea to select it, then dragging & dropping the file onto the textarea.\n validations:\n required: true\n\n - type: textarea\n attributes:\n label: Alternatives\n description: Possible alternative solutions or features that you have considered.\n\n - type: textarea\n attributes:\n label: Additional context\n description: Any other context or screenshots about the feature request.\n" }, { "path": ".github/ISSUE_TEMPLATE/question.yml", "content": "name: Ask a question\ndescription: Ask a question about pypcode\nlabels: [question,needs-triage]\nbody:\n - type: markdown\n attributes:\n value: |\n If you have a question about pypcode, that is not a bug report or a feature request, you can ask it here. For more real-time help with pypcode, from us and the community, join our [Slack](https://angr.io/invite/).\n\n Before submitting this question, please check the following, which may answer your question:\n * Have you checked the [documentation](https://docs.angr.io/)?\n * Have you checked the [FAQ](https://docs.angr.io/introductory-errata/faq)?\n * Have you checked our library of [examples](https://github.com/angr/angr-doc/tree/master/examples)?\n * Have you [searched existing issues](https://github.com/angr/pypcode/issues?q=is%3Aissue+label%3Aquestion) to see if this question has been answered before?\n * Have you checked that you are running the latest versions of angr and its components. angr is rapidly-evolving!\n\n Please note: The angr suite is maintained by a small team. While we cannot guarantee any timeliness for fixes and enhancements, we will do our best.\n\n - type: textarea\n attributes:\n label: Question\n description:\n validations:\n required: true\n" }, { "path": ".github/dependabot.yml", "content": "version: 2\nupdates:\n - package-ecosystem: \"github-actions\"\n directory: \"/\"\n schedule:\n interval: \"weekly\"\n commit-message:\n prefix: \"ci\"\n" }, { "path": ".github/workflows/build.yml", "content": "name: Build\n\non: [push, pull_request]\n\nconcurrency:\n group: ${{ github.workflow }}-${{ github.ref }}\n cancel-in-progress: true\n\npermissions:\n contents: read\n\njobs:\n lint:\n name: Lint\n runs-on: ubuntu-latest\n steps:\n - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2\n - uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0\n with:\n python-version: '3.12'\n - run: |\n python -m pip install setuptools pylint\n python -m pip install -e .\n - uses: pre-commit/action@2c7b3805fd2a0fd8c1884dcaebf91fc102a13ecd # v3.0.1\n with:\n extra_args: pylint --all-files\n\n build_sdist:\n name: Build source distribution\n runs-on: ubuntu-latest\n steps:\n - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2\n - uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0\n with:\n python-version: '3.12'\n - name: Build sdist\n run: |\n python -m pip install --user build\n python -m build --sdist\n - uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1\n with:\n name: source\n path: dist/*.tar.gz\n\n build_wheels:\n needs: build_sdist\n name: Build wheel ${{ matrix.py }}-${{ matrix.platform.wheel_tag }} on ${{ matrix.platform.os }}\n runs-on: ${{ matrix.platform.os }}\n strategy:\n matrix:\n py: [cp312, cp313, cp314]\n platform:\n - { arch: x86_64, os: windows-latest, wheel_tag: win_amd64 }\n - { arch: x86_64, os: macos-15-intel, wheel_tag: macosx_x86_64 }\n - { arch: arm64, os: macos-latest, wheel_tag: macosx_arm64 }\n - { arch: x86_64, os: ubuntu-latest, wheel_tag: manylinux_x86_64 }\n - { arch: aarch64, os: ubuntu-24.04-arm, wheel_tag: manylinux_aarch64 }\n steps:\n - name: Download source distribution\n uses: actions/download-artifact@3e5f45b2cfb9172054b4087a40e8e0b5a5461e7c # v8.0.1\n with:\n name: source\n - name: Unpack source distribution\n shell: bash\n run: tar --strip-components 1 -xvf *.tar.gz\n - name: Build wheel\n uses: pypa/cibuildwheel@8d2b08b68458a16aeb24b64e68a09ab1c8e82084 # v3.4.1\n with:\n output-dir: wheelhouse\n env:\n CIBW_ARCHS_MACOS: ${{ matrix.platform.arch }}\n CIBW_BUILD: ${{ matrix.py }}-${{ matrix.platform.wheel_tag }}\n CIBW_TEST_COMMAND: python -m unittest discover -v -s {package}/tests\n CIBW_BUILD_VERBOSITY: 1\n MACOSX_DEPLOYMENT_TARGET: ${{ matrix.platform.arch == 'arm64' && '11' || '10.14' }}\n - uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1\n with:\n name: ${{ matrix.py }}-${{ matrix.platform.wheel_tag }}\n path: ./wheelhouse/*.whl\n\n build_docs:\n name: Build docs\n runs-on: ubuntu-latest\n steps:\n - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2\n - uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0\n with:\n python-version: '3.12'\n - run: |\n pip install -e .[docs]\n cd docs && make html coverage\n\n test_coverage:\n name: Test with coverage\n runs-on: ubuntu-latest\n steps:\n - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2\n - uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0\n with:\n python-version: '3.13'\n - name: Run tests\n run: |\n pip install setuptools nanobind cmake\n COVERAGE=1 pip install --no-build-isolation -e .[testing]\n pytest -vv \\\n --junitxml=junit.xml -o junit_family=legacy \\\n --cov-report=xml \\\n || [[ $? -lt 2 ]] # Accept success and test failures, fail on infrastructure problems (exit codes >1)\n gcovr -r . \\\n --print-summary \\\n --xml-pretty \\\n -o coverage-native.xml \\\n --gcov-filter 'pypcode_native.cpp'\n [[ -e ./junit.xml && -e coverage.xml && -e ./coverage-native.xml ]]\n - name: Upload test results\n uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1\n with:\n name: results\n include-hidden-files: true\n if-no-files-found: error\n path: |\n ./junit.xml\n ./coverage.xml\n ./coverage-native.xml\n\n upload_coverage:\n name: Upload test results to Codecov\n needs: [test_coverage]\n runs-on: ubuntu-latest\n permissions:\n id-token: write\n steps:\n - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2\n - uses: actions/download-artifact@3e5f45b2cfb9172054b4087a40e8e0b5a5461e7c # v8.0.1\n with:\n name: results\n - name: Upload test coverage to Codecov\n uses: codecov/codecov-action@v6\n with:\n use_oidc: true\n fail_ci_if_error: true\n verbose: true\n files: ./coverage.xml ./coverage-native.xml\n - name: Upload test results to Codecov\n uses: codecov/codecov-action@v6\n with:\n use_oidc: true\n fail_ci_if_error: true\n verbose: true\n files: ./junit.xml\n report_type: test_results\n\n upload_pypi:\n name: Upload wheels to PyPI\n needs: [lint, build_docs, build_sdist, build_wheels, upload_coverage]\n environment:\n name: pypi\n url: https://pypi.org/p/pypcode\n permissions:\n id-token: write\n runs-on: ubuntu-latest\n # Upload to PyPI on every tag starting with 'v'\n if: github.event_name == 'push' && startsWith(github.event.ref, 'refs/tags/v')\n steps:\n - uses: actions/download-artifact@3e5f45b2cfb9172054b4087a40e8e0b5a5461e7c # v8.0.1\n with:\n path: artifacts\n - run: |\n mkdir dist\n find artifacts -type f \\( -name '*.whl' -o -name '*.tar.gz' \\) -exec mv {} dist \\;\n - uses: pypa/gh-action-pypi-publish@cef221092ed1bacb1cc03d23a2d87d1d172e277b # v1.14.0\n" }, { "path": ".gitignore", "content": "*.egg-info/\n__pycache__/\nbuild/\ndist/\npypcode/bin/\ndocs/_build/\n*.so\n*.sla\n*.manifest\n*.gradle\n*.java\n.coverage\ncoverage.xml\ncoverage-native.xml\n" }, { "path": ".pre-commit-config.yaml", "content": "ci:\n skip: [pylint]\n\nexclude: ^pypcode/sleigh|^pypcode/processors\nrepos:\n\n#\n# Fail fast\n#\n\n- repo: https://github.com/abravalheri/validate-pyproject\n rev: v0.25\n hooks:\n - id: validate-pyproject\n fail_fast: true\n\n- repo: https://github.com/pre-commit/pre-commit-hooks\n rev: v6.0.0\n hooks:\n # General\n - id: check-merge-conflict\n fail_fast: true\n - id: check-case-conflict\n fail_fast: true\n - id: destroyed-symlinks\n fail_fast: true\n - id: check-symlinks\n fail_fast: true\n - id: check-added-large-files\n fail_fast: true\n # Syntax\n - id: check-toml\n fail_fast: true\n - id: check-json\n fail_fast: true\n - id: check-yaml\n fail_fast: true\n\n- repo: https://github.com/pre-commit/pre-commit-hooks\n rev: v6.0.0\n hooks:\n - id: check-ast\n fail_fast: true\n\n#\n# Modifiers\n#\n\n- repo: https://github.com/pre-commit/pre-commit-hooks\n rev: v6.0.0\n hooks:\n - id: mixed-line-ending\n - id: trailing-whitespace\n\n- repo: https://github.com/dannysepler/rm_unneeded_f_str\n rev: v0.2.0\n hooks:\n - id: rm-unneeded-f-str\n\n- repo: https://github.com/asottile/pyupgrade\n rev: v3.21.2\n hooks:\n - id: pyupgrade\n args: [--py312-plus]\n\n# Last modifier: Coding Standard\n- repo: https://github.com/psf/black-pre-commit-mirror\n rev: 26.3.1\n hooks:\n - id: black\n\n- repo: https://github.com/pre-commit/mirrors-clang-format\n rev: v22.1.4\n hooks:\n - id: clang-format\n files: pypcode/pypcode_native.cpp\n\n\n#\n# Static Checks\n#\n\n- repo: https://github.com/pre-commit/pygrep-hooks\n rev: v1.10.0\n hooks:\n # Python\n - id: python-use-type-annotations\n - id: python-no-log-warn\n # Documentation\n - id: rst-backticks\n - id: rst-directive-colons\n - id: rst-inline-touching-normal\n\n- repo: https://github.com/pre-commit/pre-commit-hooks\n rev: v6.0.0\n hooks:\n - id: debug-statements\n - id: check-builtin-literals\n - id: check-docstring-first\n\n- repo: https://github.com/astral-sh/ruff-pre-commit\n rev: v0.15.12\n hooks:\n - id: ruff\n\n- repo: https://github.com/pre-commit/mirrors-mypy\n rev: v1.20.2\n hooks:\n - id: mypy\n\n- repo: local\n hooks:\n - id: pylint\n name: pylint\n entry: pylint\n language: system\n types: [python]\n args:\n [\n \"-rn\", # Only display messages\n \"-sn\", # Don't display the score\n ]\n" }, { "path": ".pylintrc", "content": "[MASTER]\n\n# Specify a configuration file.\n#rcfile=\n\n# Python code to execute, usually for sys.path manipulation such as\n# pygtk.require().\n#init-hook=\n\n# Add files or directories to the blacklist. They should be base names, not\n# paths.\nignore=CVS\n\n# Pickle collected data for later comparisons.\npersistent=yes\n\n# List of plugins (as comma separated values of python modules names) to load,\n# usually to register additional checkers.\nload-plugins=pylint.extensions.no_self_use,pylint.extensions.bad_builtin\n\n\n[MESSAGES CONTROL]\n\n# Enable the message, report, category or checker with the given id(s). You can\n# either give multiple identifier separated by comma (,) or put this option\n# multiple time.\n#enable=\n\n# Disable the message, report, category or checker with the given id(s). You\n# can either give multiple identifier separated by comma (,) or put this option\n# multiple time (only on the command line, not in the configuration file where\n# it should appear only once).\n\ndisable=\n abstract-method,\n fixme,\n invalid-name,\n len-as-condition,\n locally-disabled,\n missing-function-docstring,\n missing-module-docstring,\n no-else-return,\n protected-access,\n too-few-public-methods,\n too-many-ancestors,\n too-many-arguments,\n too-many-branches,\n too-many-instance-attributes,\n too-many-lines,\n too-many-locals,\n too-many-nested-blocks,\n too-many-public-methods,\n too-many-return-statements,\n too-many-statements,\n unidiomatic-typecheck,\n consider-using-f-string,\n attribute-defined-outside-init\n\n\n[REPORTS]\n\n# Set the output format. Available formats are text, parseable, colorized, msvs\n# (visual studio) and html\noutput-format=text\n\n# Tells whether to display a full report or only the messages\nreports=yes\n\n# Python expression which should return a note less than 10 (10 is the highest\n# note). You have access to the variables errors warning, statement which\n# respectively contain the number of errors / warnings messages and the total\n# number of statements analyzed. This is used by the global evaluation report\n# (RP0004).\nevaluation=10.0 - ((float(5 * error + warning + refactor + convention) / statement) * 10)\n\n\n[TYPECHECK]\n\n# Tells whether missing members accessed in mixin class should be ignored. A\n# mixin class is detected if its name ends with \"mixin\" (case insensitive).\nignore-mixin-members=yes\n\n# List of classes names for which member attributes should not be checked\n# (useful for classes with attributes dynamically set).\nignored-classes=SQLObject,nose.tools,nose.tools.trivial,sympy\n\n# List of members which are set dynamically and missed by pylint inference\n# system, and so shouldn't trigger E0201 when accessed. Python regular\n# expressions are accepted.\ngenerated-members=REQUEST,acl_users,aq_parent\n\nignored-modules=sh,PySide2,PySide2.QtTest,PySide2.QtCore,PySide2.QtWidgets,PySide2.QtGui\n\n[FORMAT]\n\n# Maximum number of characters on a single line.\nmax-line-length=120\n\n# Maximum number of lines in a module\nmax-module-lines=1000\n\n# String used as indentation unit. This is usually \" \" (4 spaces) or \"\\t\" (1\n# tab).\nindent-string=' '\n\n\n[BASIC]\n\n# List of builtins function names that should not be used, separated by a comma\nbad-functions=map,filter,apply,input\n\n# Regular expression which should only match correct module names\nmodule-rgx=(([a-z_][a-z0-9_]*)|([A-Z][a-zA-Z0-9]+))$\n\n# Regular expression which should only match correct module level names\nconst-rgx=(([A-Z_][A-Z0-9_]*)|(__.*__))$\n\n# Regular expression which should only match correct class names\nclass-rgx=[A-Z_][a-zA-Z0-9]+$\n\n# Regular expression which should only match correct function names\nfunction-rgx=[a-z_][a-z0-9_]{2,30}$\n\n# Regular expression which should only match correct method names\nmethod-rgx=[a-z_][a-z0-9_]{2,30}$\n\n# Regular expression which should only match correct instance attribute names\nattr-rgx=[a-z_][a-z0-9_]{2,30}$\n\n# Regular expression which should only match correct argument names\nargument-rgx=[a-z_][a-z0-9_]{2,30}$\n\n# Regular expression which should only match correct variable names\nvariable-rgx=[a-z_][a-z0-9_]{2,30}$\n\n# Regular expression which should only match correct list comprehension /\n# generator expression variable names\ninlinevar-rgx=[A-Za-z_][A-Za-z0-9_]*$\n\n# Good variable names which should always be accepted, separated by a comma\ngood-names=i,j,k,ex,Run,_,l\n\n# Bad variable names which should always be refused, separated by a comma\nbad-names=\n\n# Regular expression which should only match functions or classes name which do\n# not require a docstring\nno-docstring-rgx=__.*__\n\n\n[VARIABLES]\n\n# Tells whether we should check for unused import in __init__ files.\ninit-import=no\n\n# A regular expression matching the beginning of the name of dummy variables\n# (i.e. not used).\ndummy-variables-rgx=_|dummy\n\n# List of additional names supposed to be defined in builtins. Remember that\n# you should avoid to define new builtins when possible.\nadditional-builtins=\n\n\n[MISCELLANEOUS]\n\n# List of note tags to take in consideration, separated by a comma.\nnotes=FIXME,XXX,TODO\n\n\n[SIMILARITIES]\n\n# Minimum lines number of a similarity.\nmin-similarity-lines=4\n\n# Ignore comments when computing similarities.\nignore-comments=yes\n\n# Ignore docstrings when computing similarities.\nignore-docstrings=yes\n\n\n[DESIGN]\n\n# Maximum number of arguments for function / method\nmax-args=5\n\n# Argument names that match this expression will be ignored. Default to name\n# with leading underscore\nignored-argument-names=_.*\n\n# Maximum number of locals for function / method body\nmax-locals=15\n\n# Maximum number of return / yield for function / method body\nmax-returns=6\n\n# Maximum number of branch for function / method body\nmax-branches=12\n\n# Maximum number of statements in function / method body\nmax-statements=50\n\n# Maximum number of parents for a class (see R0901).\nmax-parents=7\n\n# Maximum number of attributes for a class (see R0902).\nmax-attributes=7\n\n# Minimum number of public methods for a class (see R0903).\nmin-public-methods=2\n\n# Maximum number of public methods for a class (see R0904).\nmax-public-methods=20\n\n\n[IMPORTS]\n\n# Deprecated modules which should not be used, separated by a comma\ndeprecated-modules=regsub,TERMIOS,Bastion,rexec\n\n# Create a graph of every (i.e. internal and external) dependencies in the\n# given file (report RP0402 must not be disabled)\nimport-graph=\n\n# Create a graph of external dependencies in the given file (report RP0402 must\n# not be disabled)\next-import-graph=\n\n# Create a graph of internal dependencies in the given file (report RP0402 must\n# not be disabled)\nint-import-graph=\n\n\n[CLASSES]\n\n# List of method names used to declare (i.e. assign) instance attributes.\ndefining-attr-methods=__init__,__new__,setUp\n\n# List of valid names for the first argument in a class method.\nvalid-classmethod-first-arg=cls\n\n\n[EXCEPTIONS]\n\n# Exceptions that will emit a warning when being caught. Defaults to\n# \"Exception\"\novergeneral-exceptions=builtins.Exception\n" }, { "path": ".readthedocs.yml", "content": "# Read the Docs configuration file\n# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details\n\nversion: 2\nbuild:\n os: ubuntu-22.04\n tools:\n python: \"3.12\"\n\npython:\n install:\n - method: pip\n path: .\n extra_requirements:\n - docs\n\nsphinx:\n configuration: docs/conf.py\n" }, { "path": "CMakeLists.txt", "content": "cmake_minimum_required(VERSION 3.18...3.22)\nproject(pypcode)\nfind_package(Python COMPONENTS Interpreter Development.Module REQUIRED)\n\nset(CMAKE_CXX_STANDARD 17)\nset(CMAKE_OSX_DEPLOYMENT_TARGET 10.14)\n\nif(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)\n set(CMAKE_BUILD_TYPE Release CACHE STRING \"Choose the type of build.\" FORCE)\n set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS \"Debug\" \"Release\" \"MinSizeRel\" \"RelWithDebInfo\")\nendif()\n\n# Detect the installed nanobind package and import it into CMake\nexecute_process(\n COMMAND \"${Python_EXECUTABLE}\" -c \"import nanobind; print(nanobind.cmake_dir())\"\n OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE NB_DIR)\nlist(APPEND CMAKE_PREFIX_PATH \"${NB_DIR}\")\nfind_package(nanobind CONFIG REQUIRED)\n\nif(MSVC)\n add_compile_options(/O2 /D_HAS_STD_BYTE=0 /DLOCAL_ZLIB=1 /DNO_GZIP=1)\nelse()\n add_compile_options(-O3 -Wall -Wno-sign-compare -D__TERMINAL__ -DLOCAL_ZLIB=1 -DNO_GZIP=1)\nendif()\n\ninclude_directories(pypcode/thirdparty)\n\nset(ZLIB\n pypcode/zlib/adler32.c\n pypcode/zlib/deflate.c\n pypcode/zlib/inffast.c\n pypcode/zlib/inflate.c\n pypcode/zlib/inftrees.c\n pypcode/zlib/trees.c\n pypcode/zlib/zutil.c\n )\n\nset(SLEIGH_COMMON\n pypcode/sleigh/address.cc\n pypcode/sleigh/compression.cc\n pypcode/sleigh/context.cc\n pypcode/sleigh/float.cc\n pypcode/sleigh/globalcontext.cc\n pypcode/sleigh/marshal.cc\n pypcode/sleigh/opcodes.cc\n pypcode/sleigh/pcodecompile.cc\n pypcode/sleigh/pcodeparse.cc\n pypcode/sleigh/pcoderaw.cc\n pypcode/sleigh/semantics.cc\n pypcode/sleigh/slaformat.cc\n pypcode/sleigh/sleigh.cc\n pypcode/sleigh/sleighbase.cc\n pypcode/sleigh/slghpatexpress.cc\n pypcode/sleigh/slghpattern.cc\n pypcode/sleigh/slghsymbol.cc\n pypcode/sleigh/space.cc\n pypcode/sleigh/translate.cc\n pypcode/sleigh/xml.cc\n )\n\nadd_executable(sleigh\n pypcode/sleigh/filemanage.cc\n pypcode/sleigh/slgh_compile.cc\n pypcode/sleigh/slghparse.cc\n pypcode/sleigh/slghscan.cc\n ${SLEIGH_COMMON}\n ${ZLIB}\n )\ninstall(TARGETS sleigh DESTINATION bin)\n\nnanobind_add_module(pypcode_native\n pypcode/pypcode_native.cpp\n ${SLEIGH_COMMON}\n ${ZLIB}\n )\n\nif(DEFINED ENV{COVERAGE} AND NOT \"$ENV{COVERAGE}\" STREQUAL \"\")\n if(CMAKE_CXX_COMPILER_ID MATCHES \"GNU|Clang\")\n target_compile_options(pypcode_native PRIVATE --coverage -O0 -g)\n target_link_options(pypcode_native PRIVATE --coverage -O0 -g)\n endif()\nendif()\n\ninstall(TARGETS pypcode_native DESTINATION .)\n" }, { "path": "LICENSE.txt", "content": "pypcode is a library built around the SLEIGH library.\n\nSLEIGH and the processor definition files under the pypcode/processors directory\noriginate from the Ghidra project (https://ghidra-sre.org/). SLEIGH is released\nunder the terms of the Apache 2 license as defined in docs/ghidra/LICENSE. See\nNOTICE file in docs/ghidra/NOTICE.\n\nThe remaining code of pypcode, unless stated otherwise, is licensed under the\nterms of the 2-clause BSD license below.\n\n================================================================================\n\nCopyright (c) 2021, Arizona Board of Regents\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.\n2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n" }, { "path": "MANIFEST.in", "content": "graft pypcode\nprune pypcode/bin\ninclude CMakeLists.txt\ninclude LICENSE.txt\ngraft tests\nglobal-exclude *.so\nglobal-exclude *.gitignore\n" }, { "path": "README.md", "content": "pypcode\n=======\n[![pypi](https://img.shields.io/pypi/v/pypcode)](https://pypi.org/project/pypcode/)\n[![codecov](https://codecov.io/gh/angr/pypcode/graph/badge.svg?token=JCV27I1SPZ)](https://codecov.io/gh/angr/pypcode)\n\nMachine code disassembly and IR translation library for Python using the\nexcellent SLEIGH library from the [Ghidra](https://ghidra-sre.org/) framework.\n\nThis library was created primarily for use with [angr](http://angr.io), which\nprovides analyses and symbolic execution of p-code.\n\nDocumentation covering how to install and use pypcode is\n[available here](https://api.angr.io/projects/pypcode/en/latest/).\n" }, { "path": "docs/Makefile", "content": "# Minimal makefile for Sphinx documentation\n#\n\n# You can set these variables from the command line, and also\n# from the environment for the first two.\nSPHINXOPTS ?=\nSPHINXBUILD ?= sphinx-build\nSOURCEDIR = .\nBUILDDIR = _build\n\n# Put it first so that \"make\" without argument is like \"make help\".\nhelp:\n\t@$(SPHINXBUILD) -M help \"$(SOURCEDIR)\" \"$(BUILDDIR)\" $(SPHINXOPTS) $(O)\n\n.PHONY: help Makefile\n\n# Catch-all target: route all unknown targets to Sphinx using the new\n# \"make mode\" option. $(O) is meant as a shortcut for $(SPHINXOPTS).\n%: Makefile\n\t@$(SPHINXBUILD) -M $@ \"$(SOURCEDIR)\" \"$(BUILDDIR)\" $(SPHINXOPTS) $(O)\n" }, { "path": "docs/api.rst", "content": ":mod:`pypcode`\n=========================================\n\n.. automodule:: pypcode\n" }, { "path": "docs/conf.py", "content": "# Configuration file for the Sphinx documentation builder.\n#\n# For the full list of built-in configuration values, see the documentation:\n# https://www.sphinx-doc.org/en/master/usage/configuration.html\n\nimport datetime\n\n# -- Project information -----------------------------------------------------\n# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information\n\nproject = \"pypcode\"\nproject_copyright = f\"{datetime.datetime.now().year}, The angr Project contributors\"\nauthor = \"The angr Project\"\n\n# -- General configuration ---------------------------------------------------\n# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration\n\nextensions = [\n \"sphinx.ext.autodoc\",\n \"sphinx.ext.autosummary\",\n \"IPython.sphinxext.ipython_console_highlighting\",\n \"IPython.sphinxext.ipython_directive\",\n \"sphinx.ext.coverage\",\n \"sphinx.ext.napoleon\",\n \"sphinx.ext.todo\",\n \"sphinx.ext.viewcode\",\n \"sphinx_autodoc_typehints\",\n \"myst_parser\",\n]\n\ntemplates_path = [\"_templates\"]\nexclude_patterns = [\"_build\", \"Thumbs.db\", \".DS_Store\"]\n\n# -- Options for autodoc -----------------------------------------------------\n# https://www.sphinx-doc.org/en/master/usage/extensions/autodoc.html#configuration\nautoclass_content = \"class\"\nautodoc_default_options = {\n \"members\": True,\n \"member-order\": \"bysource\",\n \"inherited-members\": True,\n \"show-inheritance\": True,\n \"undoc-members\": True,\n}\nautodoc_inherit_docstrings = True\nautodoc_typehints = \"both\"\n\n# -- Options for coverage ----------------------------------------------------\n# https://www.sphinx-doc.org/en/master/usage/extensions/coverage.html\ncoverage_write_headline = False\n\n# -- Options for HTML output -------------------------------------------------\n# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output\n\nhtml_theme = \"furo\"\nhtml_static_path = [\"_static\"]\n" }, { "path": "docs/guide.rst", "content": "Guide\n=====\n\nInstallation\n------------\nThis package can be installed on Linux, macOS, and Windows platforms for recent (3.8+) versions of both CPython and\nPyPy. Wheels are provided for several configurations. The latest release can be installed from PyPI using ``pip``:\n\n.. code:: bash\n\n pip install pypcode\n\nThe very latest development version can be installed from GitHub via:\n\n.. code:: bash\n\n pip install --user https://github.com/angr/pypcode/archive/refs/heads/master.zip\n\nUsage Example\n-------------\n\nDisassemble with :meth:`pypcode.Context.disassemble`:\n\n.. ipython::\n\n In [0]: from pypcode import Context\n ...: ctx = Context(\"x86:LE:64:default\")\n ...: dx = ctx.disassemble(bytes.fromhex(\"483578563412c3\"))\n ...: print(dx)\n\nWork with :class:`pypcode.Disassembly` and :class:`pypcode.Instruction`:\n\n.. ipython::\n\n In [0]: (dx.instructions[0].mnem, dx.instructions[0].body)\n\nTranslate to P-Code with :meth:`pypcode.Context.translate`:\n\n.. ipython::\n\n In [0]: from pypcode import Context\n ...: ctx = Context(\"x86:LE:64:default\")\n ...: tx = ctx.translate(bytes.fromhex(\"483578563412c3\"))\n ...: print(tx)\n\nWork with :class:`pypcode.Translation` and :class:`pypcode.PcodeOp`:\n\n.. ipython::\n\n In [0]: tx.ops[3].opcode\n\n In [0]: tx.ops[3].inputs[0].space.name\n\n In [0]: tx.ops[3].inputs[0].getRegisterName()\n\n\nCommand Line Usage Example\n--------------------------\nThe ``pypcode`` module can be invoked from command line to disassemble and translate supported machine code to P-code\nfrom command line. Run ``python -m pypcode --help`` for usage information.\n\n::\n\n $ python -m pypcode -b x86:LE:64:default test-x64.bin\n --------------------------------------------------------------------------------\n 00000000/2: XOR EAX,EAX\n --------------------------------------------------------------------------------\n 0: CF = 0x0\n 1: OF = 0x0\n 2: EAX = EAX ^ EAX\n 3: RAX = zext(EAX)\n 4: SF = EAX s< 0x0\n 5: ZF = EAX == 0x0\n 6: unique[0x2580:4] = EAX & 0xff\n 7: unique[0x2590:1] = popcount(unique[0x2580:4])\n 8: unique[0x25a0:1] = unique[0x2590:1] & 0x1\n 9: PF = unique[0x25a0:1] == 0x0\n\n --------------------------------------------------------------------------------\n 00000002/2: CMP ESI,EAX\n --------------------------------------------------------------------------------\n 0: CF = ESI < EAX\n 1: OF = sborrow(ESI, EAX)\n 2: unique[0x5180:4] = ESI - EAX\n 3: SF = unique[0x5180:4] s< 0x0\n 4: ZF = unique[0x5180:4] == 0x0\n 5: unique[0x2580:4] = unique[0x5180:4] & 0xff\n 6: unique[0x2590:1] = popcount(unique[0x2580:4])\n 7: unique[0x25a0:1] = unique[0x2590:1] & 0x1\n 8: PF = unique[0x25a0:1] == 0x0\n\n --------------------------------------------------------------------------------\n 00000004/2: JBE 0x17\n --------------------------------------------------------------------------------\n 0: unique[0x18f0:1] = CF || ZF\n 1: if (unique[0x18f0:1]) goto ram[0x17:8]\n\nSLEIGH & P-Code References\n--------------------------\nExtensive documentation covering SLEIGH and P-Code is available online:\n\n* `SLEIGH, P-Code Introduction `_\n* `P-Code Reference Manual `_" }, { "path": "docs/index.rst", "content": "pypcode documentation\n=====================\npypcode is a machine code disassembly and IR translation library for Python using the\nexcellent `SLEIGH `__ library from the `Ghidra `__ framework (version 12.0.2).\n\nThis library was created primarily for use with `angr `__, which provides analyses and symbolic\nexecution of p-code.\n\nTable of Contents\n-----------------\n\n.. toctree::\n :maxdepth: 2\n\n Guide \n Architecture Support \n API Reference \n\nIndices and Tables\n------------------\n\n* :ref:`genindex`\n* :ref:`modindex`\n* :ref:`search`\n" }, { "path": "docs/languages.rst", "content": "Architecture Support\n====================\n\n.. ipython::\n\n In [0]: for arch in pypcode.Arch.enumerate():\n ...: for lang in arch.languages:\n ...: print(f'{lang.id:32} - {lang.description}')\n" }, { "path": "docs/make.bat", "content": "@ECHO OFF\n\npushd %~dp0\n\nREM Command file for Sphinx documentation\n\nif \"%SPHINXBUILD%\" == \"\" (\n\tset SPHINXBUILD=sphinx-build\n)\nset SOURCEDIR=.\nset BUILDDIR=_build\n\n%SPHINXBUILD% >NUL 2>NUL\nif errorlevel 9009 (\n\techo.\n\techo.The 'sphinx-build' command was not found. Make sure you have Sphinx\n\techo.installed, then set the SPHINXBUILD environment variable to point\n\techo.to the full path of the 'sphinx-build' executable. Alternatively you\n\techo.may add the Sphinx directory to PATH.\n\techo.\n\techo.If you don't have Sphinx installed, grab it from\n\techo.https://www.sphinx-doc.org/\n\texit /b 1\n)\n\nif \"%1\" == \"\" goto help\n\n%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%\ngoto end\n\n:help\n%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%\n\n:end\npopd\n" }, { "path": "pypcode/__init__.py", "content": "\"\"\"\nPythonic interface to SLEIGH\n\"\"\"\n\nfrom __future__ import annotations\nimport os.path\nimport xml.etree.ElementTree as ET\nfrom enum import IntEnum\nfrom typing import cast\nfrom collections.abc import Generator, Sequence, Mapping\n\nfrom .__version__ import __version__\n\nfrom .pypcode_native import __version__ as __pypcode_native_version__ # pylint:disable=no-name-in-module\n\nassert __version__ == __pypcode_native_version__\n\nfrom .pypcode_native import ( # pylint:disable=no-name-in-module\n Address,\n AddrSpace,\n BadDataError,\n DecoderError,\n Disassembly,\n Instruction,\n LowlevelError,\n OpCode,\n PcodeOp,\n TRANSLATE_FLAGS_BB_TERMINATING,\n Translation,\n UnimplError,\n Varnode,\n)\nfrom .pypcode_native import Context as _Context # pylint:disable=no-name-in-module\n\nfrom .printing import (\n OpFormat,\n OpFormatBinary,\n OpFormatFunc,\n OpFormatSpecial,\n OpFormatUnary,\n PcodePrettyPrinter,\n)\n\n__all__ = [\n \"Address\",\n \"AddrSpace\",\n \"Arch\",\n \"ArchLanguage\",\n \"BadDataError\",\n \"Context\",\n \"DecoderError\",\n \"Disassembly\",\n \"Instruction\",\n \"LowlevelError\",\n \"OpCode\",\n \"OpFormat\",\n \"OpFormatBinary\",\n \"OpFormatFunc\",\n \"OpFormatSpecial\",\n \"OpFormatUnary\",\n \"PcodeOp\",\n \"PcodePrettyPrinter\",\n \"TranslateFlags\",\n \"Translation\",\n \"UnimplError\",\n \"Varnode\",\n]\n\n\nclass TranslateFlags(IntEnum):\n \"\"\"\n Flags that can be passed to Context::translate\n \"\"\"\n\n BB_TERMINATING = TRANSLATE_FLAGS_BB_TERMINATING\n\n\nPKG_SRC_DIR = os.path.abspath(os.path.dirname(__file__))\nSPECFILES_DIR = os.path.join(PKG_SRC_DIR, \"processors\")\n\n\nclass ArchLanguage:\n \"\"\"\n A specific language for an architecture. Provides access to language, pspec, and cspecs.\n \"\"\"\n\n __slots__ = (\n \"archdir\",\n \"ldef\",\n \"_pspec\",\n \"_cspecs\",\n )\n\n archdir: str\n ldef: ET.Element\n\n def __init__(self, archdir: str, ldef: ET.Element):\n self.archdir = archdir\n self.ldef = ldef\n self._pspec: ET.Element | None = None\n self._cspecs: dict[tuple[str, str], ET.Element] | None = None\n\n @property\n def pspec_path(self) -> str:\n return os.path.join(self.archdir, self.processorspec)\n\n @property\n def slafile_path(self) -> str:\n return os.path.join(self.archdir, self.slafile)\n\n @property\n def description(self) -> str:\n elem = self.ldef.find(\"description\")\n if elem is not None:\n return elem.text or \"\"\n return \"\"\n\n def __getattr__(self, key):\n if key in self.ldef.attrib:\n return self.ldef.attrib[key]\n raise AttributeError(key)\n\n @property\n def pspec(self) -> ET.Element | None:\n if self._pspec is None:\n self._pspec = ET.parse(self.pspec_path).getroot()\n return self._pspec\n\n @property\n def cspecs(self) -> Mapping[tuple[str, str], ET.Element]:\n if self._cspecs is None:\n self._cspecs = {}\n for e in self.ldef.findall(\"compiler\"):\n path = os.path.join(self.archdir, e.attrib[\"spec\"])\n cspec = ET.parse(path).getroot()\n self._cspecs[(e.attrib[\"id\"], e.attrib[\"name\"])] = cspec\n return self._cspecs\n\n def init_context_from_pspec(self, ctx: Context) -> None:\n if self.pspec is None:\n return\n cd = self.pspec.find(\"context_data\")\n if cd is None:\n return\n cs = cd.find(\"context_set\")\n if cs is None:\n return\n for e in cs:\n assert e.tag == \"set\"\n ctx.setVariableDefault(e.attrib[\"name\"], int(e.attrib[\"val\"]))\n\n @classmethod\n def from_id(cls, langid: str) -> ArchLanguage | None:\n \"\"\"\n Return language with given id, or None if the language could not be found.\n \"\"\"\n for arch in Arch.enumerate():\n for lang in arch.languages:\n if lang.id == langid:\n return lang\n return None\n\n\nclass Arch:\n \"\"\"\n Main class representing an architecture describing available languages.\n \"\"\"\n\n __slots__ = (\n \"archpath\",\n \"archname\",\n \"ldefpath\",\n \"ldef\",\n \"languages\",\n )\n\n archpath: str\n archname: str\n ldefpath: str\n ldef: ET.ElementTree[ET.Element[str]]\n languages: Sequence[ArchLanguage]\n\n def __init__(self, name: str, ldefpath: str):\n \"\"\"\n Initialize the Arch.\n\n :param name: The name of the architecture\n :param ldefpath: Path to language definition files (.ldefs)\n \"\"\"\n self.archpath = os.path.dirname(ldefpath)\n self.archname = name\n self.ldefpath = ldefpath\n self.ldef = ET.parse(ldefpath)\n self.languages = [ArchLanguage(self.archpath, e) for e in self.ldef.getroot()]\n\n @classmethod\n def enumerate(cls) -> Generator[Arch]:\n \"\"\"\n Enumerate all available architectures and languages.\n\n Language definitions are sourced from definitions shipped with pypcode and\n can be found in processors//data/languages/.ldefs\n \"\"\"\n for archname in os.listdir(SPECFILES_DIR):\n langdir = os.path.join(SPECFILES_DIR, archname, \"data\", \"languages\")\n if not (os.path.exists(langdir) and os.path.isdir(langdir)):\n continue\n for langname in os.listdir(langdir):\n if not langname.endswith(\".ldefs\"):\n continue\n ldefpath = os.path.join(langdir, langname)\n yield Arch(archname, ldefpath)\n\n\nclass Context(_Context):\n \"\"\"\n Context for translation.\n \"\"\"\n\n __slots__ = (\n \"language\",\n \"registers\",\n )\n\n language: ArchLanguage\n registers: dict[str, Varnode]\n\n def __init__(self, language: ArchLanguage | str):\n \"\"\"\n Initialize a context for translation or disassembly.\n\n :param language: The ``ArchLanguage`` to initialize the context with, or a language id ``str``\n \"\"\"\n if isinstance(language, ArchLanguage):\n self.language = language\n elif isinstance(language, str):\n _l = ArchLanguage.from_id(cast(str, language))\n assert _l is not None\n self.language = _l\n else:\n raise TypeError(\"Context must be initialized with a language or language id\")\n super().__init__(f\"{self.language.slafile_path}\")\n self.language.init_context_from_pspec(self)\n self.registers = {n: v for v, n in self.getAllRegisters().items()}\n" }, { "path": "pypcode/__main__.py", "content": "#!/usr/bin/env python\n\"\"\"\nRuns when invoking pypcode module from command line. Lists supported\narchitectures, and handles basic disassembly and translation to P-code of\nsupported binaries. Does not parse object files, the binary files must be plain\nmachine code bytes in a file.\n\"\"\"\n\nimport argparse\nimport logging\nimport sys\nfrom difflib import SequenceMatcher\n\nfrom pypcode import Arch, BadDataError, Context, OpCode, TranslateFlags, UnimplError\n\nlog = logging.getLogger(__name__)\nlogging.basicConfig(level=logging.DEBUG, format=\"[%(name)s:%(levelname)s] %(message)s\")\n\n\ndef main():\n ap = argparse.ArgumentParser(\n prog=\"pypcode\",\n description=\"Disassemble and translate machine code to P-code using SLEIGH\",\n )\n ap.add_argument(\n \"-l\",\n \"--list\",\n action=\"store_true\",\n help=\"list supported architecture languages\",\n )\n ap.add_argument(\"langid\", help=\"architecture language id\")\n ap.add_argument(\"binary\", help=\"path to flat binary code\")\n ap.add_argument(\"base\", default=\"0\", nargs=\"?\", help=\"base address to load at\")\n ap.add_argument(\"-o\", \"--offset\", default=\"0\", help=\"offset in binary file to load from\")\n ap.add_argument(\"-s\", \"--length\", default=None, help=\"length of code in bytes to load\")\n ap.add_argument(\n \"-i\",\n \"--max-instructions\",\n default=0,\n type=int,\n help=\"maximum number of instructions to translate\",\n )\n ap.add_argument(\n \"-b\",\n \"--basic-block\",\n action=\"store_true\",\n default=False,\n help=\"stop translation at end of basic block\",\n )\n\n # List supported languages\n langs = {lang.id: lang for arch in Arch.enumerate() for lang in arch.languages}\n if (\"-l\" in sys.argv) or (\"--list\" in sys.argv):\n for langid in sorted(langs):\n print(\"%-35s - %s\" % (langid, langs[langid].description))\n return\n\n args = ap.parse_args()\n\n # Get requested language\n if args.langid not in langs:\n print(f'Language \"{args.langid}\" not found.')\n t = args.langid.upper()\n suggestions = [langid for langid in langs if SequenceMatcher(None, t, langid.split()[0].upper()).ratio() > 0.25]\n if len(suggestions):\n print(\"\\nSuggestions:\")\n for langid in sorted(suggestions):\n print(\" %-35s - %s\" % (langid, langs[langid].description))\n print(\"\")\n print(\"Try `--list` for full list of architectures.\")\n sys.exit(1)\n\n # Load target binary code\n base = int(args.base, 0)\n with open(args.binary, \"rb\") as f:\n f.seek(int(args.offset, 0))\n code = f.read(int(args.length, 0)) if args.length else f.read()\n\n # Translate\n ctx = Context(langs[args.langid])\n\n try:\n flags = TranslateFlags.BB_TERMINATING if args.basic_block else 0\n res = ctx.translate(code, base, max_instructions=args.max_instructions, flags=flags)\n\n last_imark_idx = 0\n for i, op in enumerate(res.ops):\n if op.opcode == OpCode.IMARK:\n last_imark_idx = i\n disas_addr = op.inputs[0].offset\n disas_offset = disas_addr - base\n disas_len = sum(vn.size for vn in op.inputs)\n disas_slice = code[disas_offset : disas_offset + disas_len]\n print(ctx.disassemble(disas_slice, disas_addr))\n else:\n print(f\" {i - last_imark_idx - 1:3d}: {op}\")\n print(\"\")\n except (BadDataError, UnimplError) as e:\n print(f\"An error occurred during translation: {e}\")\n sys.exit(1)\n\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": "pypcode/__version__.py", "content": "__version__ = \"3.3.4.dev0\"\n" }, { "path": "pypcode/docs/ghidra/DISCLAIMER.md", "content": "# Disclaimer of Warranty\n\nThis Work is provided \"AS IS.\"\nAny express or implied warranties, including but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed.\nIn no event shall the United States Government be liable for any direct, indirect, incidental, special, exemplary or consequential damages (including, but not limited to, procurement of substitute goods or services, loss of use, data or profits, or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this Work, even if advised of the possibility of such damage.\n\nThe User of this Work agrees to hold harmless and indemnify the United States Government, its agents and employees from every claim or liability (whether in tort or in contract), including attorney's fees, court costs, and expenses, arising in direct consequence of Recipient's use of the item, including, but not limited to, claims or liabilities made for injury to or death of personnel of User or third parties, damage to or destruction of property of User or third parties, and infringement or other violations of intellectual property or technical data rights.\n\n# Disclaimer of Endorsement\n\nNothing in this Work is intended to constitute an endorsement, explicit or implied, by the United States Government of any particular manufacturer's product or service.\n\nReference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, in this Work does not constitute an endorsement, recommendation, or favoring by the United States Government and shall not be used for advertising or product endorsement purposes.\n" }, { "path": "pypcode/docs/ghidra/LICENSE", "content": " Apache License\n Version 2.0, January 2004\n http://www.apache.org/licenses/\n\n TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n 1. Definitions.\n\n \"License\" shall mean the terms and conditions for use, reproduction,\n and distribution as defined by Sections 1 through 9 of this document.\n\n \"Licensor\" shall mean the copyright owner or entity authorized by\n the copyright owner that is granting the License.\n\n \"Legal Entity\" shall mean the union of the acting entity and all\n other entities that control, are controlled by, or are under common\n control with that entity. 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We also recommend that a\n file or class name and description of purpose be included on the\n same \"printed page\" as the copyright notice for easier\n identification within third-party archives.\n\n Copyright [yyyy] [name of copyright owner]\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n" }, { "path": "pypcode/docs/ghidra/NOTICE", "content": "Ghidra\n\nThis product includes software developed at National Security Agency\n(https://www.nsa.gov)\n\nPortions of this product were created by the U.S. Government and not subject to\nU.S. copyright protections under 17 U.S.C.\n\nThe remaining portions are copyright their respective authors and have been\ncontributed under the terms of one or more open source licenses, and made\navailable to you under the terms of those licenses. (See LICENSE)\n\n\n\nLicensing Intent\n\nThe intent is that this software and documentation (\"Project\") should be treated\nas if it is licensed under the license associated with the Project (\"License\")\nin the LICENSE file. However, because we are part of the United States (U.S.)\nFederal Government, it is not that simple.\n\nThe portions of this Project written by U.S. Federal Government employees within\nthe scope of their federal employment are ineligible for copyright protection in\nthe U.S.; this is generally understood to mean that these portions of the\nProject are placed in the public domain.\n\nIn countries where copyright protection is available (which does not include the\nU.S.), contributions made by U.S. Federal Government employees are released\nunder the License. Merged contributions from private contributors are released\nunder the License.\n\nThe Ghidra software is released under the Apache License, Version 2.0\n(\"Apache 2.0\").\n\nIn addition, each module may contain numerous 3rd party components (libraries,\nicons, etc.) that each have their own license which is compatible with Apache\n2.0. Each module has a LICENSE.txt file that lists each license used in that\nmodule and the 3rd party files that fall under that license. The license files\nfor each license used by Ghidra can be found in the licenses directory at the\ninstallation root.\n\nAlso, in the GPL directory, there are several stand-alone support programs that\nare released using the GPL 3 license. Ghidra executes these programs as needed\nand parses the output to get the desired results. There is a licenses directory\nunder the GPL directory that has the GPL license files.\n\nConsistent with the inbound=outbound model, contributions to any module must be\nmade available, by the contributor, under the applicable license(s). Please read\nthe Legal section of the CONTRIBUTING.md guide.\n" }, { "path": "pypcode/printing.py", "content": "from __future__ import annotations\n\nfrom .pypcode_native import ( # pylint:disable=no-name-in-module\n Disassembly,\n Instruction,\n OpCode,\n PcodeOp,\n Translation,\n Varnode,\n)\n\n\nclass OpFormat:\n \"\"\"\n General op pretty-printer.\n \"\"\"\n\n @staticmethod\n def fmt_vn(vn: Varnode) -> str:\n if vn.space.name == \"const\":\n return \"%#x\" % vn.offset\n elif vn.space.name == \"register\":\n name = vn.getRegisterName()\n if name:\n return name\n return f\"{vn.space.name}[{vn.offset:x}:{vn.size:d}]\"\n\n def fmt(self, op: PcodeOp) -> str:\n return f'{op.opcode.__name__} {\", \".join(self.fmt_vn(i) for i in op.inputs)}'\n\n\nclass OpFormatUnary(OpFormat):\n \"\"\"\n General unary op pretty-printer.\n \"\"\"\n\n __slots__ = (\"operator\",)\n\n def __init__(self, operator: str):\n super().__init__()\n self.operator = operator\n\n def fmt(self, op: PcodeOp) -> str:\n return f\"{self.operator}{self.fmt_vn(op.inputs[0])}\"\n\n\nclass OpFormatBinary(OpFormat):\n \"\"\"\n General binary op pretty-printer.\n \"\"\"\n\n __slots__ = (\"operator\",)\n\n def __init__(self, operator: str):\n super().__init__()\n self.operator = operator\n\n def fmt(self, op: PcodeOp) -> str:\n return f\"{self.fmt_vn(op.inputs[0])} {self.operator} {self.fmt_vn(op.inputs[1])}\"\n\n\nclass OpFormatFunc(OpFormat):\n \"\"\"\n Function-call style op pretty-printer.\n \"\"\"\n\n __slots__ = (\"operator\",)\n\n def __init__(self, operator: str):\n super().__init__()\n self.operator = operator\n\n def fmt(self, op: PcodeOp) -> str:\n return f'{self.operator}({\", \".join(self.fmt_vn(i) for i in op.inputs)})'\n\n\nclass OpFormatSpecial(OpFormat):\n \"\"\"\n Specialized op pretty-printers.\n \"\"\"\n\n def fmt_BRANCH(self, op: PcodeOp) -> str:\n return f\"goto {self.fmt_vn(op.inputs[0])}\"\n\n def fmt_BRANCHIND(self, op: PcodeOp) -> str:\n return f\"goto [{self.fmt_vn(op.inputs[0])}]\"\n\n def fmt_CALL(self, op: PcodeOp) -> str:\n return f\"call {self.fmt_vn(op.inputs[0])}\"\n\n def fmt_CALLIND(self, op: PcodeOp) -> str:\n return f\"call [{self.fmt_vn(op.inputs[0])}]\"\n\n def fmt_CALLOTHER(self, op: PcodeOp) -> str:\n return f'{op.inputs[0].getUserDefinedOpName()}({\", \".join(self.fmt_vn(i) for i in op.inputs[1:])})'\n\n def fmt_CBRANCH(self, op: PcodeOp) -> str:\n return f\"if ({self.fmt_vn(op.inputs[1])}) goto {self.fmt_vn(op.inputs[0])}\"\n\n def fmt_LOAD(self, op: PcodeOp) -> str:\n return f\"*[{op.inputs[0].getSpaceFromConst().name}]{self.fmt_vn(op.inputs[1])}\"\n\n def fmt_RETURN(self, op: PcodeOp) -> str:\n return f\"return {self.fmt_vn(op.inputs[0])}\"\n\n def fmt_STORE(self, op: PcodeOp) -> str:\n return f\"*[{op.inputs[0].getSpaceFromConst().name}]{self.fmt_vn(op.inputs[1])} = {self.fmt_vn(op.inputs[2])}\"\n\n def fmt(self, op: PcodeOp) -> str:\n return {\n OpCode.BRANCH: self.fmt_BRANCH,\n OpCode.BRANCHIND: self.fmt_BRANCHIND,\n OpCode.CALL: self.fmt_CALL,\n OpCode.CALLIND: self.fmt_CALLIND,\n OpCode.CALLOTHER: self.fmt_CALLOTHER,\n OpCode.CBRANCH: self.fmt_CBRANCH,\n OpCode.LOAD: self.fmt_LOAD,\n OpCode.RETURN: self.fmt_RETURN,\n OpCode.STORE: self.fmt_STORE,\n }.get(op.opcode, super().fmt)(op)\n\n\nclass PcodePrettyPrinter:\n \"\"\"\n P-code pretty-printer.\n \"\"\"\n\n DEFAULT_OP_FORMAT = OpFormat()\n\n OP_FORMATS = {\n OpCode.BOOL_AND: OpFormatBinary(\"&&\"),\n OpCode.BOOL_NEGATE: OpFormatUnary(\"!\"),\n OpCode.BOOL_OR: OpFormatBinary(\"||\"),\n OpCode.BOOL_XOR: OpFormatBinary(\"^^\"),\n OpCode.BRANCH: OpFormatSpecial(),\n OpCode.BRANCHIND: OpFormatSpecial(),\n OpCode.CALL: OpFormatSpecial(),\n OpCode.CALLIND: OpFormatSpecial(),\n OpCode.CALLOTHER: OpFormatSpecial(),\n OpCode.CBRANCH: OpFormatSpecial(),\n OpCode.COPY: OpFormatUnary(\"\"),\n OpCode.CPOOLREF: OpFormatFunc(\"cpool\"),\n OpCode.FLOAT_ABS: OpFormatFunc(\"abs\"),\n OpCode.FLOAT_ADD: OpFormatBinary(\"f+\"),\n OpCode.FLOAT_CEIL: OpFormatFunc(\"ceil\"),\n OpCode.FLOAT_DIV: OpFormatBinary(\"f/\"),\n OpCode.FLOAT_EQUAL: OpFormatBinary(\"f==\"),\n OpCode.FLOAT_FLOAT2FLOAT: OpFormatFunc(\"float2float\"),\n OpCode.FLOAT_FLOOR: OpFormatFunc(\"floor\"),\n OpCode.FLOAT_INT2FLOAT: OpFormatFunc(\"int2float\"),\n OpCode.FLOAT_LESS: OpFormatBinary(\"f<\"),\n OpCode.FLOAT_LESSEQUAL: OpFormatBinary(\"f<=\"),\n OpCode.FLOAT_MULT: OpFormatBinary(\"f*\"),\n OpCode.FLOAT_NAN: OpFormatFunc(\"nan\"),\n OpCode.FLOAT_NEG: OpFormatUnary(\"f- \"),\n OpCode.FLOAT_NOTEQUAL: OpFormatBinary(\"f!=\"),\n OpCode.FLOAT_ROUND: OpFormatFunc(\"round\"),\n OpCode.FLOAT_SQRT: OpFormatFunc(\"sqrt\"),\n OpCode.FLOAT_SUB: OpFormatBinary(\"f-\"),\n OpCode.FLOAT_TRUNC: OpFormatFunc(\"trunc\"),\n OpCode.INT_2COMP: OpFormatUnary(\"-\"),\n OpCode.INT_ADD: OpFormatBinary(\"+\"),\n OpCode.INT_AND: OpFormatBinary(\"&\"),\n OpCode.INT_CARRY: OpFormatFunc(\"carry\"),\n OpCode.INT_DIV: OpFormatBinary(\"/\"),\n OpCode.INT_EQUAL: OpFormatBinary(\"==\"),\n OpCode.INT_LEFT: OpFormatBinary(\"<<\"),\n OpCode.INT_LESS: OpFormatBinary(\"<\"),\n OpCode.INT_LESSEQUAL: OpFormatBinary(\"<=\"),\n OpCode.INT_MULT: OpFormatBinary(\"*\"),\n OpCode.INT_NEGATE: OpFormatUnary(\"~\"),\n OpCode.INT_NOTEQUAL: OpFormatBinary(\"!=\"),\n OpCode.INT_OR: OpFormatBinary(\"|\"),\n OpCode.INT_REM: OpFormatBinary(\"%\"),\n OpCode.INT_RIGHT: OpFormatBinary(\">>\"),\n OpCode.INT_SBORROW: OpFormatFunc(\"sborrow\"),\n OpCode.INT_SCARRY: OpFormatFunc(\"scarry\"),\n OpCode.INT_SDIV: OpFormatBinary(\"s/\"),\n OpCode.INT_SEXT: OpFormatFunc(\"sext\"),\n OpCode.INT_SLESS: OpFormatBinary(\"s<\"),\n OpCode.INT_SLESSEQUAL: OpFormatBinary(\"s<=\"),\n OpCode.INT_SREM: OpFormatBinary(\"s%\"),\n OpCode.INT_SRIGHT: OpFormatBinary(\"s>>\"),\n OpCode.INT_SUB: OpFormatBinary(\"-\"),\n OpCode.INT_XOR: OpFormatBinary(\"^\"),\n OpCode.INT_ZEXT: OpFormatFunc(\"zext\"),\n OpCode.LOAD: OpFormatSpecial(),\n OpCode.NEW: OpFormatFunc(\"newobject\"),\n OpCode.POPCOUNT: OpFormatFunc(\"popcount\"),\n OpCode.LZCOUNT: OpFormatFunc(\"lzcount\"),\n OpCode.RETURN: OpFormatSpecial(),\n OpCode.STORE: OpFormatSpecial(),\n }\n\n @staticmethod\n def fmt_op(op: PcodeOp) -> str:\n fmt = PcodePrettyPrinter.OP_FORMATS.get(op.opcode, PcodePrettyPrinter.DEFAULT_OP_FORMAT)\n return (f\"{fmt.fmt_vn(op.output)} = \" if op.output else \"\") + fmt.fmt(op)\n\n @staticmethod\n def fmt_translation(tx: Translation) -> str:\n return \"\\n\".join(PcodePrettyPrinter.fmt_op(op) for op in tx.ops)\n\n\ndef fmt_instruction(insn: Instruction) -> str:\n return f\"{insn.addr.offset:#x}/{insn.length}: {insn.mnem} {insn.body}\"\n\n\ndef fmt_disassembly(dx: Disassembly) -> str:\n return \"\\n\".join(fmt_instruction(insn) for insn in dx.instructions)\n\n\n# Monkey patch print handlers\nDisassembly.__str__ = fmt_disassembly # type: ignore[assignment,method-assign]\nInstruction.__str__ = fmt_instruction # type: ignore[assignment,method-assign]\nPcodeOp.__str__ = PcodePrettyPrinter.fmt_op # type: ignore[assignment,method-assign]\nTranslation.__str__ = PcodePrettyPrinter.fmt_translation # type: ignore[assignment,method-assign]\nVarnode.__str__ = OpFormat.fmt_vn # type: ignore[assignment,method-assign]\n" }, { "path": "pypcode/processors/6502/data/languages/6502.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/6502/data/languages/6502.ldefs", "content": "\n\n\n \n \n 6502 Microcontroller Family\n \n \n \n\n \n 65C02 Microcontroller Family\n \n\t\n \n \n\n" }, { "path": "pypcode/processors/6502/data/languages/6502.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/6502/data/languages/6502.slaspec", "content": "# sleigh specification file for MOS 6502\n\ndefine endian=little;\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=2 default;\ndefine space register type=register_space size=1;\n\ndefine register offset=0x00 size=1 [ A X Y P ];\ndefine register offset=0x20 size=2 [ PC SP ];\ndefine register offset=0x20 size=1 [ PCL PCH S SH ];\ndefine register offset=0x30 size=1 [ N V B D I Z C ];\t# status bits\n\n#TOKENS\n\ndefine token opbyte (8)\n op = (0,7)\n \n aaa = (5,7)\n bbb = (2,4)\n cc = (0,1)\n;\n\ndefine token data8 (8)\n imm8\t\t= (0,7)\n rel\t\t= (0,7) signed\n;\n\ndefine token data (16)\n\timm16 = (0,15)\n;\n\nmacro popSR() {\n\tSP = SP + 1;\n\tlocal ccr = *:1 SP;\n\tN = ccr[7,1];\n\tV = ccr[6,1];\n\tB = ccr[4,1];\n\tD = ccr[3,1];\n\tI = ccr[2,1];\n\tZ = ccr[1,1];\n\tC = ccr[0,1];\n}\n\nmacro pushSR() {\n\tlocal ccr:1 = 0xff;\n\tccr[7,1] = N;\n\tccr[6,1] = V;\n\tccr[4,1] = B;\n\tccr[3,1] = D;\n\tccr[2,1] = I;\n\tccr[1,1] = Z;\n\tccr[0,1] = C;\n\t*:1 (SP) = ccr;\n\tSP = SP -1;\n}\n\nmacro resultFlags(value) {\n\tZ = (value == 0);\n\tN = (value s< 0);\n}\n\nmacro subtraction_flags1(register, operand, result) {\n\tlocal complement_register = ~register;\n\t\n\tV = ( ((register & ~operand & ~result) | (complement_register & operand & result)) & 0b10000000 ) != 0;\n\tN = (result s< 0);\n\tZ = (result == 0);\n\tC = ( ((complement_register & operand) | (operand & result) | (result & complement_register)) & 0b10000000 ) != 0;\n}\n\n\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop readIRQ;\n\n################################################################\nREL: reloc\t\tis rel\t[ reloc = inst_next + rel; ] { export *:2 reloc; } \n\n# Immediate\nOP1: \"#\"imm8 is bbb=2; imm8\t\t\t{ tmp:1 = imm8; export tmp; }\n# Zero Page\nOP1: imm8 is bbb=1; imm8\t\t\t{ export *:1 imm8; }\n# Zero Page Indexed X\nOP1: imm8,X is bbb=5 & X; imm8\t\t{ tmp:2 = zext(imm8 + X); export *:1 tmp; }\n# Absolute\nOP1: imm16 is bbb=3; imm16\t\t\t{ export *:1 imm16; }\n# Absolute Indexed X\nOP1: imm16,X is bbb=7 & X; imm16\t\t{ tmp:2 = imm16 + zext(X); export *:1 tmp; }\n# Absolute Indexed Y\nOP1: imm16,Y is bbb=6 & Y; imm16\t\t{ tmp:2 = imm16 + zext(Y); export *:1 tmp; }\n# Indirect X\nOP1: (imm8,X) is bbb=0 & X; imm8\t\t{ addr:2 = zext(imm8 + X); tmp:2 = *:2 addr; export *:1 tmp; }\n# Indirect Y\nOP1: (imm8),Y is bbb=4 & Y; imm8\t\t{ addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }\n\n# Immediate\nOP2: \"#\"imm8 is bbb=0; imm8\t\t\t{ tmp:1 = imm8; export tmp; }\n# Zero Page\nOP2: imm8 is bbb=1; imm8\t\t\t{ export *:1 imm8; }\nOP2: A is bbb=2 & A { export A; }\n# Absolute\nOP2: imm16 is bbb=3; imm16\t\t\t{ export *:1 imm16; }\n# Zero Page Indexed X\nOP2: imm8,X is bbb=5 & X; imm8\t\t{ tmp:2 = zext(imm8 + X); export *:1 tmp; }\n# Absolute Indexed X\nOP2: imm16,X is bbb=7 & X; imm16\t\t{ tmp:2 = imm16 + zext(X); export *:1 tmp; }\n\nOP2ST: OP2 is OP2 { export OP2; }\nOP2ST: imm8,Y is bbb=5 & Y; imm8\t\t{ tmp:2 = zext(imm8 + Y); export *:1 tmp; }\n\nOP2LD: OP2 is OP2 { export OP2; }\nOP2LD: imm8,Y is bbb=5 & Y; imm8\t\t{ tmp:2 = zext(imm8 + Y); export *:1 tmp; }\nOP2LD: imm16,Y is bbb=7 & Y; imm16\t\t{ tmp:2 = imm16 + zext(Y); export *:1 tmp; }\n\n\nADDR8: imm8 is imm8\t\t{ export *:1 imm8; }\nADDR16: imm16 is imm16 \t{ export *:1 imm16; }\nADDRI: (imm16) is imm16 { tmp:2 = imm16; export *:2 tmp; }\n\n\n# Instructions\n\n\n:ADC OP1 is (cc=1 & aaa=3) ... & OP1\n{\n\tlocal op1 = OP1;\n\tlocal tmpC = C;\n\t\n\tC = carry(A, op1);\n\t\n\tA = A + op1 + tmpC;\n\n\tresultFlags(A);\n\tV = C;\n}\n\n:AND OP1 is (cc=1 & aaa=1) ... & OP1\n{ \n\tA = A & OP1; \n\tresultFlags(A);\n}\n\n:ASL OP2 is (op=0x06 | op=0x0A | op=0x0E | op=0x16 | op=0x1E) ... & OP2\n{\n\tlocal tmp = OP2;\n\tC = tmp >> 7;\n\ttmp = tmp << 1;\n\tOP2 = tmp;\n\tresultFlags(tmp);\t\n}\n\n:BCC REL\t\t\tis op=0x90; REL\n{\n\tif (C == 0) goto REL;\n}\n\n:BCS REL\t\t\tis op=0xB0; REL\n{\n\tif (C) goto REL;\n}\n\n:BEQ REL\t\t\tis op=0xF0; REL\n{\n\tif (Z) goto REL;\n}\n\n:BIT OP2 is (op=0x24 | op=0x2C) ... & OP2\n{\n\tN = (OP2 & 0x80) == 0x80;\n\tV = (OP2 & 0x40) == 0x40;\n\tlocal value = A & OP2;\n\tZ = (value == 0);\n}\n\n:BMI REL\t\t\tis op=0x30; REL\n{\n\tif (N) goto REL;\n}\n\n:BNE REL\t\t\tis op=0xD0; REL\n{\n\tif (Z == 0) goto REL;\n}\n\n:BPL REL\t\t\tis op=0x10; REL\n{\n\tif (N == 0) goto REL;\n}\n\n:BRK is op=0x00\n{\n\t*:2 (SP - 1) = inst_next;\n\tSP = SP - 2;\n\tB = 1;\n\tpushSR();\n\tI = 1;\n\tlocal target:2 = 0xFFFE;\n\tgoto [*:2 target];\n}\n\n:BVC REL\t\t\tis op=0x50; REL\n{\n\tif (V == 0) goto REL;\n}\n\n:BVS REL\t\t\tis op=0x70; REL\n{\n\tif (V) goto REL;\n}\n\n:CLC is op=0x18\n{\n\tC = 0;\n}\n\n:CLD is op=0xD8\n{\n\tD = 0;\n}\n\n:CLI is op=0x58\n{\n\tI = 0;\n}\n\n:CLV is op=0xB8\n{\n\tV = 0;\n}\n\n:CMP OP1 is (cc=1 & aaa=6) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tlocal tmp = A - op1;\n\tresultFlags(tmp);\n\tC = (A >= op1);\n}\n\n:CPX OP2 is (op=0xE0 | op=0xE4 | op=0xEC) ... & OP2\n{\n\tlocal op1 = OP2;\n\tlocal tmp = X - op1;\n\tresultFlags(tmp);\n\tC = (X >= op1);\n}\n\n:CPY OP2 is (op=0xC0 | op=0xC4 | op=0xCC) ... & OP2\n{\n\tlocal op1 = OP2;\n\tlocal tmp = Y - op1;\n\tresultFlags(tmp);\n\tC = (Y >= op1);\n}\n\n:DEC OP2 is (op=0xC6 | op=0xCE | op=0xD6 | op=0xDE) ... & OP2\n{\n\tlocal tmp = OP2 - 1;\n\tOP2 = tmp;\n\tresultFlags(tmp);\n}\n\n:DEX is op=0xCA\n{\n\tX = X - 1;\n\tresultFlags(X);\n}\n\n\n:DEY is op=0x88\n{\n\tY = Y -1;\n\tresultFlags(Y);\n}\n\n:EOR OP1 is (cc=1 & aaa=2) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tA = A ^ op1;\n\tresultFlags(A);\n}\n\n:INC OP2 is (op=0xE6 | op=0xEE | op=0xF6 | op=0xFE) ... & OP2\n{\n\tlocal tmp = OP2 + 1;\n\tOP2 = tmp;\n\tresultFlags(tmp);\n}\n\n:INY is op=0xC8\n{\n\tY = Y + 1;\n\tresultFlags(Y);\n}\n\n:INX is op=0xE8\n{\n\tX = X + 1;\n\tresultFlags(X);\n}\n\n:JMP ADDR16 is (op=0x4C); ADDR16\n{\n\tgoto ADDR16;\n}\n\n:JMP ADDRI is (op=0x6c); ADDRI\n{\n\tgoto [ADDRI];\n}\n\n:JSR ADDR16 is op=0x20; ADDR16\n{\n\t*:2 (SP-1) = inst_next;\n\tSP=SP-2; \n\tcall ADDR16;\n}\n\n:LDA OP1 is (cc=1 & aaa=5) ... & OP1\n{\n\tA = OP1;\n\tresultFlags(A);\n}\n\n:LDY OP2 is (op=0xA0 | op=0xA4 | op=0xAC | op=0xB4 | op=0xBC) ... & OP2\n{\n\tY = OP2;\n\tresultFlags(Y);\n}\n\n:LDX OP2LD is (op=0xA2 | op=0xA6 | op=0xAE | op=0xB6 | op=0xBE) ... & OP2LD\n{\n\tX = OP2LD;\n\tresultFlags(X);\n}\n\n:LSR OP2 is (op=0x46 | op=0x4A | op=0x4E | op=0x56 | op=0x5E) ... & OP2\n{\n\tlocal tmp = OP2;\n\tC = tmp & 1;\n\ttmp = tmp >> 1;\n\tOP2 = tmp;\n\tZ = (tmp == 0);\n\tN = 0;\t\n}\n\n:NOP is op=0xEA\n{\n}\n\n:ORA OP1 is (cc=1 & aaa=0) ... & OP1\n{\n\tA = A | OP1; \n\tresultFlags(A);\n}\n\n:PHP is op=0x8\n{\n\tpushSR();\n}\n\n:PLP is op=0x28\n{\n\tpopSR();\n}\n\n:PHA is op=0x48\n{\n\t*:1 (SP) = A;\n\tSP = SP - 1;\n}\n\n:PLA is op=0x68\n{\n\tSP = SP + 1;\n\tA = *:1 (SP);\n\tresultFlags(A);\n}\n\n:ROL OP2 is (op=0x26 | op=0x2A | op=0x2E | op=0x36 | op=0x3E) ... & OP2\n{\n\tlocal tmpC = C;\n\tlocal op2 = OP2;\n\tC = op2 >> 7;\n\tlocal result = op2 << 1;\n\tresult = result | tmpC;\n\tOP2 = result;\n\tresultFlags(result);\t\n}\n\n:ROR OP2 is (op=0x66 | op=0x6A | op=0x6E | op=0x76 | op=0x7E) ... & OP2\n{\n\tlocal tmpC = C << 7;\n\tlocal tmp = OP2;\n\tC = tmp & 1;\n\ttmp = tmp >> 1;\n\ttmp = tmp | tmpC;\n\tOP2 = tmp;\n\tresultFlags(tmp);\t\n}\n\n:RTI is op=0x40\n{\n\tpopSR();\n\t\n SP = SP+1;\n\ttmp:2 = *:2 SP;\n\tSP = SP+1;\n\t\n\treturn [tmp];\n}\n\n:RTS is op=0x60\n{\n\tSP = SP+1;\n\ttmp:2 = *:2 SP;\n\tSP = SP+1;\n\t\n\treturn [tmp];\n}\n\n:SBC OP1 is (cc=1 & aaa=7) ... & OP1\n{\n\tlocal op1 = OP1;\n\tlocal result = A - op1 - !C;\n\t\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\t\n\t\n\t# resultFlags(tmp);\n\t# C = ((A <= op1) * C) | (A < op1);\n\t# A = tmp;\n}\n\n:SEC is op=0x38\n{\n\tC = 1;\n}\n\n:SED is op=0xF8\n{\n\tD = 1;\t\n}\n\n:SEI is op=0x78\n{\n\tI = 1;\n}\n\n:STA OP1 is (cc=1 & aaa=4) ... & OP1\n{\n\tOP1 = A;\n}\n\n:STX OP2ST is (op=0x86 | op=0x8E | op=0x96) ... & OP2ST\n{\n\tOP2ST = X;\n}\n\n:STY OP2 is (op=0x84 | op=0x8C | op=0x94) ... & OP2\n{\n\tOP2 = Y;\n}\n\n:TAX is op=0xAA\n{\n\tX = A;\n\tresultFlags(X);\n}\n\n:TAY is op=0xA8\n{\n\tY = A;\n\tresultFlags(Y);\n}\n\n:TSX is op=0xBA\n{\n\tX = S;\n resultFlags(X);\t\n}\n\n:TXA is op=0x8A\n{\n\tA = X;\n\tresultFlags(A);\n}\n\n:TXS is op=0x9A\n{\n\tS = X;\n}\n\n:TYA is op=0x98\n{\n\tA = Y;\n\tresultFlags(A);\n}\n" }, { "path": "pypcode/processors/6502/data/languages/65c02.slaspec", "content": "@include \"6502.slaspec\"\n\ndefine token bitopbyte (8)\n bitop = (0,7)\n\n action = (7,7)\n bitindex = (4,6) dec\n optype = (0,3)\n;\n\ndefine token testopbyte (8)\n top = (0, 7)\n taaa = (5, 7)\n td = (4, 4)\n tbb = (2, 3)\n tcc = (0, 1)\n;\n\n################################################################\n\n# Zero Page Indirect\nZIOP: (imm8) is bbb=4; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; export *:1 tmp; }\n\nOPTB: imm8 is tbb=1; imm8 { export *:1 imm8; }\nOPTB: imm16 is tbb=3; imm16 { export *:1 imm16; }\n\n# Absolute Indexed Indirect\nADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr; export tmp; }\n\n# Instructions\n\n:ADC ZIOP is (cc=2 & aaa=3) ... & ZIOP\n{\n local op1 = ZIOP;\n local tmpC = C;\n\n C = carry(A, op1);\n A = A + op1 + tmpC;\n resultFlags(A);\n V = C;\n}\n\n:AND ZIOP is (cc=2 & aaa=1) ... & ZIOP\n{\n A = A & ZIOP;\n resultFlags(A);\n}\n\n:BBR \"#\"bitindex, imm8, REL is (action=0 & optype=0xF) & bitindex ; imm8 ; REL {\n local ptr:2 = imm8;\n local value:1 = *:1 ptr;\n local jump = (value & (1 << bitindex)) == 0;\n if (jump) goto REL;\n}\n\n:BBS \"#\"bitindex, imm8, REL is (action=1 & optype=0xF) & bitindex ; imm8 ; REL {\n local ptr:2 = imm8;\n local value:1 = *:1 ptr;\n local jump = (value & (1 << bitindex)) != 0;\n if (jump) goto REL;\n}\n\n:BIT \"#\"imm8 is op=0x89; imm8\n{\n local value:1 = imm8;\n N = (value & 0x80) == 0x80;\n V = (value & 0x40) == 0x40;\n value = A & value;\n Z = (value == 0);\n}\n\n:BIT OP2 is (op=0x34 | op=0x3C) ... & OP2\n{\n N = (OP2 & 0x80) == 0x80;\n V = (OP2 & 0x40) == 0x40;\n local value = A & OP2;\n Z = (value == 0);\n}\n\n:BRA REL is op=0x80; REL\n{\n goto REL;\n}\n\n:CMP ZIOP is (cc=2 & aaa=6) ... & ZIOP\n{\n local op1 = ZIOP;\n local tmp = A - op1;\n resultFlags(tmp);\n C = (A >= op1);\n}\n\n:DEC A is op=0x3A & A\n{\n local tmp = A - 1;\n A = tmp;\n resultFlags(tmp);\n}\n\n:EOR ZIOP is (cc=2 & aaa=2) ... & ZIOP\n{\n local op1 = ZIOP;\n A = A ^ op1;\n resultFlags(A);\n}\n\n:INC A is op=0x1A & A\n{\n A = A + 1;\n resultFlags(A);\n}\n\n:JMP ADDRIX is (op=0x7C); ADDRIX\n{\n goto [ADDRIX];\n}\n\n:LDA ZIOP is (cc=2 & aaa=5) ... & ZIOP\n{\n A = ZIOP;\n resultFlags(A);\n}\n\n:ORA ZIOP is (cc=2 & aaa=0) ... & ZIOP\n{\n A = A | ZIOP;\n resultFlags(A);\n}\n\n:PHX is op=0xDA\n{\n *:1 (SP) = X;\n SP = SP - 1;\n}\n\n:PLX is op=0xFA\n{\n SP = SP + 1;\n X = *:1 (SP);\n resultFlags(X);\n}\n\n:PHY is op=0x5A\n{\n *:1 (SP) = Y;\n SP = SP - 1;\n}\n\n:PLY is op=0x7A\n{\n SP = SP + 1;\n Y = *:1 (SP);\n resultFlags(Y);\n}\n\n:RMB \"#\"bitindex, imm8 is (action=0 & optype=7) & bitindex ; imm8 {\n local ptr:2 = imm8;\n local value:1 = *:1 ptr;\n value = value & ~(1 << bitindex);\n *:1 ptr = value;\n}\n\n:SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP\n{\n local op1 = ZIOP;\n local result = A - op1 - !C;\n\n subtraction_flags1(A, op1, result);\n A = result;\n}\n\n:SMB \"#\"bitindex, imm8 is (action=1 & optype=7) & bitindex ; imm8 {\n local ptr:2 = imm8;\n local value:1 = *:1 ptr;\n value = value | (1 << bitindex);\n *:1 ptr = value;\n}\n\n:STA ZIOP is (cc=2 & aaa=4) ... & ZIOP\n{\n ZIOP = A;\n}\n\n:STZ imm8 is op=0x64 ; imm8\n{\n local tmp:2 = imm8;\n *:1 tmp = 0;\n}\n\n:STZ imm8,X is op=0x74 & X ; imm8\n{\n local tmp:2 = zext(imm8 + X);\n *:1 tmp = 0;\n}\n\n:STZ imm16 is op=0x9C ; imm16\n{\n local tmp:2 = imm16;\n *:1 tmp = 0;\n}\n\n:STZ imm16,X is op=0x9E & X ; imm16\n{\n local tmp:2 = imm16 + zext(X);\n *:1 tmp = 0;\n}\n\n:TRB OPTB is (tcc=0 & taaa=0 & td=1) ... & OPTB\n{\n local op1 = OPTB;\n local result = (~A) & op1;\n OPTB = result;\n Z = result == 0;\n}\n\n:TSB OPTB is (tcc=0 & taaa=0 & td=0) ... & OPTB\n{\n local op1 = OPTB;\n local result = A | op1;\n OPTB = result;\n Z = result == 0;\n}\n" }, { "path": "pypcode/processors/6502/data/manuals/6502.idx", "content": "@mcs6500_family_programming_manual.pdf [MCS 6500 Microcomputer Family Programming Manual, January 1976]\nADC, 205\nAND, 205\nASL, 206\nBCC, 206\nBCS, 207\nBEQ, 207\nBIT, 208\nBMI, 208\nBNE, 209\nBPL, 209\nBRK, 210\nBVC, 210\nBVS, 211\nCLC, 211\nCLD, 212\nCLI, 212\nCLV, 213\nCMP, 213\nCPX, 214\nCPY, 214\nDEC, 215\nDEX, 215\nDEY, 216\nEOR, 216\nINC, 217\nINX, 217\nINY, 218\nJMP, 218\nJSR, 219\nLDA, 219\nLDX, 220\nLDY, 220\nLSR, 221\nNOP, 221\nORA, 222\nPHA, 222\nPHP, 223\nPLA, 223\nPLP, 224\nROL, 224\nROR, 225\nRTI, 225\nRTS, 225\nSBC, 226\nSEC, 226\nSED, 227\nSEI, 227\nSTA, 228\nSTX, 228\nSTY, 229\nTAX, 229\nTAY, 230\nTSX, 231\nTXA, 231\nTXS, 231\nTYA, 230\n" }, { "path": "pypcode/processors/6502/data/manuals/65c02.idx", "content": "@wdc_65816_programming_manual.pdf [Programming the 65816 - Including the 6502, 65C02 and 65802, 2007]\nADC, 327\nAND, 328\nASL, 329\nBBR, 457\nBBS, 458\nBCC, 330\nBCS, 331\nBEQ, 332\nBIT, 333\nBMI, 334\nBNE, 335\nBPL, 336\nBRA, 337\nBRK, 338\nBVC, 341\nBVS, 342\nCLC, 343\nCLD, 344\nCLI, 345\nCLV, 346\nCMP, 347\nCPX, 350\nCPY, 351\nDEC, 352\nDEX, 353\nDEY, 354\nEOR, 355\nINC, 357\nINX, 358\nINY, 359\nJMP, 360\nJSR, 362\nLDA, 363\nLDX, 364\nLDY, 365\nLSR, 366\nNOP, 369\nORA, 370\nPHA, 375\nPHP, 379\nPHX, 380\nPHY, 381\nPLA, 382\nPLP, 385\nPLX, 386\nPLY, 387\nRMB, 459\nROL, 389\nROR, 390\nRTI, 391\nRTS, 393\nSBC, 395\nSEC, 397\nSED, 398\nSEI, 399\nSMB, 460\nSTA, 401\nSTX, 403\nSTY, 404\nSTZ, 405\nTAX, 406\nTAY, 407\nTRB, 411\nTSB, 412\nTSX, 414\nTXA, 415\nTXS, 416\nTYA, 418\n" }, { "path": "pypcode/processors/68000/data/languages/68000.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t \n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/68000/data/languages/68000.dwarf", "content": "\n\t\n\t\t \n\n\t\t \n\t\t\n\n\t\t \n\t\n\n" }, { "path": "pypcode/processors/68000/data/languages/68000.ldefs", "content": "\n\n\n \n Motorola 32-bit 68040\n \n \n \n \n \n \n \n \n \n \n Motorola 32-bit 68030\n \n \n \n \n \n \n \n \n Motorola 32-bit 68020\n \n \n \n \n \n \n \n \n \n \n Motorola 32-bit Coldfire\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/68000/data/languages/68000.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/68000/data/languages/68000.pspec", "content": "\n\n\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/68000/data/languages/68000.sinc", "content": "# SLA specification for Motorola 68000 series\n\ndefine endian=big;\ndefine alignment=2;\n\ndefine space ram type=ram_space size=4 default;\ndefine space register type=register_space size=4;\n\ndefine register offset=0 size=4 [ D0 D1 D2 D3 D4 D5 D6 D7 ]; # Data registers\ndefine register offset=0 size=2 [ D0u D0w D1u D1w D2u D2w D3u D3w D4u D4w D5u D5w D6u D6w D7u D7w];\ndefine register offset=0 size=1 [ _ _ _ D0b _ _ _ D1b _ _ _ D2b _ _ _ D3b _ _ _ D4b _ _ _ D5b _ _ _ D6b _ _ _ D7b ];\ndefine register offset=0x20 size=4 [ A0 A1 A2 A3 A4 A5 A6 SP ]; # Address registers\ndefine register offset=0x20 size=2 [ A0u A0w A1u A1w A2u A2w A3u A3w A4u A4w A5u A5w A6u A6w A7u A7w];\ndefine register offset=0x20 size=1 [ _ _ _ A0b _ _ _ A1b _ _ _ A2b _ _ _ A3b _ _ _ A4b _ _ _ A5b _ _ _ A6b _ _ _ A7b ];\ndefine register offset=0x40 size=1 [ TF SVF IPL XF NF ZF VF CF ];\t # Condition flags\ndefine register offset=0x50 size=4 PC;\t\t\t # Program counter register\n\ndefine register offset=0xb0 size=4 [ FPCR FPSR FPIAR ];\ndefine register offset=0xe0 size=8 [ CRP ];\ndefine register offset=0x100 size=4 [ ISP MSP VBR CACR CAAR AC0 AC1 USP TT0 TT1 ];\ndefine register offset=0x140 size=4 [ SFC DFC TC ITT0 ITT1 DTT0 DTT1 MMUSR URP SRP PCR CAC ];\ndefine register offset=0x180 size=4 [ BUSCR MBB RAMBAR0 RAMBAR1 ];\ndefine register offset=0x200 size=2 [ SR ACUSR ];\n# NOTE that SR overlaps XF, ZF, VF, CF\n# NOTE that A7 refers to USP, ISP, or MSP depending on privilege level\n\ndefine register offset=0x300 size=4 [ glbdenom movemptr ];\ndefine register offset=0x400 size=4 [ contextreg ];\n\n@ifdef COLDFIRE\n# TODO: add a pure MAC variant, for now, just do EMAC\ndefine register offset=0x500 size=4 [ MACSR MASK ];\ndefine register offset=0x600 size=4 [ EMACSR ACC0 ACC1 ACC2 ACC3 ACCext01 ACCext23 EMASK ];\n@endif\n\n# Floating point registers are 80 bits internally, but are 96 bits to/from memory.\n# Note that 12-byte float needed to be added to FloatFormat.java\n# Also note that the 96 bit format is not really IEEE, because it gets mapped to 80 bits.\ndefine register offset=0x700 size=10 [ FP0 ];\ndefine register offset=0x70a size=10 [ FP1 ];\ndefine register offset=0x714 size=10 [ FP2 ];\ndefine register offset=0x71e size=10 [ FP3 ];\ndefine register offset=0x728 size=10 [ FP4 ];\ndefine register offset=0x732 size=10 [ FP5 ];\ndefine register offset=0x73c size=10 [ FP6 ];\ndefine register offset=0x746 size=10 [ FP7 ];\n\n#TODO: These mode constraints do not constrain the various mode=7 sub-modes identified by regan bits\n@define MEM_ALTER_ADDR_MODES \"(op4=1 | op5=1)\"\t\t\t# Memory alterable addressing modes (All modes except mode=1 and mode=0)\n@define DAT_ALTER_ADDR_MODES \"(mode=0 | op4=1 | op5=1)\" # Data alterable addressing modes (All modes except mode=1)\n@define DAT_DIR_CTL_ADDR_MODES \"(mode=0 | mode=2 | mode=5 | mode=6 | mode=7)\" # Data direct and control addressing modes\n@define CTL_ADDR_MODES \"(mode=2 | mode=5 | mode=6 | mode=7)\" # Control addressing modes\n@define POSTINC_CTL_ADDR_MODES \"(mode=2 | mode=3 | mode=5 | mode=6 | mode=7)\" # Control addressing modes\n@define PREDEC_CTL_ADDR_MODES \"(mode=2 | mode=4 | mode=5 | mode=6 | mode=7)\" # Control addressing modes\n\n#TODO: These mode constraints do not constrain the various mode=7 sub-modes identified by regan bits\n@define MEM_ALTER_ADDR_MODES2 \"(op7=1 | op8=1)\"\t\t\t# Memory alterable addressing modes (All modes except mode=1 and mode=0)\n@define DAT_ALTER_ADDR_MODES2 \"(mode2=0 | op7=1 | op8=1)\" # Data alterable addressing modes (All modes except mode=1)\n@define DAT_DIR_CTL_ADDR_MODES2 \"(mode2=0 | mode2=2 | mode2=5 | mode2=6 | mode=7)\" # Data direct and control addressing modes\n@define CTL_ADDR_MODES2 \"(mode2=2 | mode2=5 | mode2=6 | mode2=7)\" # Control addressing modes\n\n# Floating-point condition code bits within FPSR\n@define N_FP\t\t\t\t\"FPSR[27,1]\"\n@define Z_FP\t\t\t\t\"FPSR[26,1]\"\n@define I_FP\t\t\t\t\"FPSR[25,1]\"\n@define NAN_FP\t\t\t\t\"FPSR[24,1]\"\n\ndefine token instr (16)\n mode = (3,5)\n mode2 = (6,8)\n regdn = (0,2)\n regdnw = (0,2)\n regdnb = (0,2)\n regan = (0,2)\n reganw = (0,2)\n reganb = (0,2)\n rmbit = (3,3)\n reg9dn = (9,11)\n reg9dnw = (9,11)\n reg9dnb = (9,11)\n reg9an = (9,11)\n copid = (9,11)\n op = (12,15)\n opbig = (8,15)\n op01 = (0,1)\n op02 = (0,2)\n op03 = (0,3)\n op08 = (0,8)\n op015 = (0,15)\n op34 = (3,4)\n op35 = (3,5)\n op37 = (3,7)\n op38 = (3,8)\n op45 = (4,5)\n op48 = (4,8)\n op69 = (6,9)\n op68 = (6,8)\n op67 = (6,7)\n op1315 = (13,15)\n op4 = (4,4)\n op5 = (5,5)\n op7 = (7,7)\n op8 = (8,8)\n op10 = (10,10)\n op11 = (11,11)\n quick = (9,11)\n op811 = (8,11)\n copcc1 = (0,5)\n d8base = (0,7) signed\n@ifdef COLDFIRE\n reg03y = (0,3)\n reg03ywu = (0,3)\n reg03ywl = (0,3)\n op47 = (4,7)\n op611 = (6,11)\n op6 = (6,6)\n op0910 = (9,10)\n acclsb = (7,7)\n d911 = (9,11)\n reg315 = (3, 15)\n reg9dnu = (9,11)\n reg9dnl = (9,11)\n reg9anu = (9,11)\n reg9anl = (9,11)\n@endif\n;\n\ndefine token extword (16)\n opx015 = (0,15)\n opx1315= (13,15)\n opx515 = (5,15)\n da = (15,15)\n regda = (12,15)\n regxdn = (12,14)\n regxdnw = (12,14)\n regxan = (12,14)\n regxanw = (12,14)\n wl = (11,11)\n mregn = (10,12)\n rwx = (9,9)\n scale = (9,10)\n ext_911 = (9,11)\n bigopx = (8,15)\n fbit = (8,8)\n regdu = (6,8)\n regduw = (6,8)\n regdub = (6,8)\n fcmask = (5,7)\n aregx = (5,7)\n ext_35 = (3,5)\n regdc = (0,2)\n regdcw = (0,2)\n regdcb = (0,2)\n d8 = (0,7) signed\n bs = (7,7)\n IS = (6,6)\n bdsize = (4,5)\n iis = (0,2)\n odsize = (0,1)\n copcc2 = (0,5)\n fc4 = (4,4)\n fc3 = (3,3)\n fc03 = (0,3)\n fc02 = (0,2)\n ctl = (0,11)\n@ifdef COLDFIRE\n sfact = (9,10)\n accmsb = (4,4)\n reg03yu = (0,3)\n reg03yl = (0,3)\n ereg03y = (0,3)\n accw = (2,3)\n reg12x = (12,15)\n reg12xwu = (12,15)\n reg12xwl = (12,15)\n@endif \n;\n\ndefine token extword2 (16)\n regda2 = (12,15)\n ext2_911 = (9,11)\n ext2_35 = (3,5)\n regdu2 = (6,8)\n regdu2w = (6,8)\n regdc2 = (0,2)\n regdc2w = (0,2)\n;\n\ndefine token fpword (16)\n fop = (12,15)\n fcopid = (9,11)\n fword = (0,15)\n fcnt = (0,2)\n f1515 = (15,15)\n f1415 = (14,15)\n f1315 = (13,15)\n f1015 = (10,15)\n f0009 = (0,9)\n f0008 = (0,8)\n f0808 = (8,8)\n f0810 = (8,10)\n f0707 = (7,7)\n f0609 = (6,9)\n f0608 = (6,8)\n f0615 = (6,15)\n f0308 = (3,8)\n f0306 = (3,6)\n fmode = (0,2)\n frm = (14,14)\n f1313 = (13,13)\n fsrc = (10,12) # attached to FP registers\n f1012 = (10,12)\n f10 = (10,10)\n f11 = (11,11)\n f12 = (12,12)\n fdcos = (0,2) # attached to FP registers\n fdsin = (7,9) # attached to FP registers\n ffmt = (10,12)\n fdst = (7,9) # attached to FP registers\n fdr = (13,13)\n fsize = (6,6)\n fcode = (0,5)\n fopmode = (0,6)\n fkfactor = (0,6)\n fkfacreg = (4,6)\n fromoffset = (0,6)\n flmode_t = (11,11)\n flmode_m = (12,12)\n fldynreg = (4,6)\n freglist = (0,7)\n frlist0 = (0,0)\n frlist1 = (1,1)\n frlist2 = (2,2)\n frlist3 = (3,3)\n frlist4 = (4,4)\n frlist5 = (5,5)\n frlist6 = (6,6)\n frlist7 = (7,7)\n;\n\ndefine token disp16 (16) d16 = (0,15) signed;\ndefine token disp32 (32) d32 = (0,31) signed;\ndefine token disp64 (64) \n signD = (63,63)\n exponentD = (52,62)\n mantissaD = (0,51)\n d64 = (0,63) signed\n;\ndefine token disp96X_1 (32) \n signX = (31,31)\n exponentX = (16,30)\n;\ndefine token disp96X_2 (64) \n expintbitX = (63,63)\n mantissaX = (0,62)\n;\ndefine token bdisp16 (16) bd16 = (0,15) signed;\ndefine token bdisp32 (32) bd32 = (0,31) signed;\ndefine token odisp16 (16) od16 = (0,15) signed;\ndefine token odisp32 (32) od32 = (0,31) signed;\ndefine token fldparm (16)\n fldpar=(0,15)\n flddo=(11,11)\n fldoffdat=(6,10)\n fldoffreg=(6,8)\n flddw=(5,5)\n fldwddat=(0,4)\n fldwdreg=(0,2)\n f_reg=(12,14)\n regdr=(0,2)\n regdq=(12,14)\n divsgn=(11,11)\n divsz=(10,10)\n mvm0 = (0,0)\t\t\t\t# Bits in the register list mask for movem\n mvm1 = (1,1)\n mvm2 = (2,2)\n mvm3 = (3,3)\n mvm4 = (4,4)\n mvm5 = (5,5)\n mvm6 = (6,6)\n mvm7 = (7,7)\n mvm8 = (8,8)\n mvm9 = (9,9)\n mvm10 = (10,10)\n mvm11 = (11,11)\n mvm12 = (12,12)\n mvm13 = (13,13)\n mvm14 = (14,14)\n mvm15 = (15,15)\n;\n\n# Context bits for getting base register bits into the addressing mode\ndefine context contextreg\n eanum = (0,0)\t\t\t# Which effective address is this (the regf's or the regs's)\n pcmode = (1,1)\t\t\t# is this a PC relative mode\n regfan = (2,4)\t\t\t# saved base register for first effective address\n regtfan = (2,4)\n savmod1 = (5,7)\n savmod2 = (8,10)\t\t\t# Mode for the second effective address\n regsdn = (11,13)\n regsdnw = (11,13)\n regsdnb = (11,13)\n regsan = (11,13)\n regtsan = (11,13)\n regsanw = (11,13)\n regsanb = (11,13)\n extGUARD = (14,14) # guard for saving off modes before starting instructions\n;\n\nattach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];\nattach variables [ fldoffreg fldwdreg f_reg fcnt fkfacreg fldynreg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];\nattach variables [ regdnw regxdnw reg9dnw regsdnw regduw regdcw regdu2w regdc2w ] [ D0w D1w D2w D3w D4w D5w D6w D7w ];\nattach variables [ regdnb reg9dnb regsdnb regdub regdcb ] [ D0b D1b D2b D3b D4b D5b D6b D7b ];\nattach variables [ regda regda2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ];\nattach variables [ regan regxan reg9an regfan regsan aregx ] [ A0 A1 A2 A3 A4 A5 A6 SP ];\nattach variables [ reganw regxanw regsanw ] [ A0w A1w A2w A3w A4w A5w A6w A7w ];\nattach variables [ reganb regsanb ] [ A0b A1b A2b A3b A4b A5b A6b A7b ];\n\nattach variables [ fsrc fdst fdcos fdsin ] [ FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 ];\n\n@ifdef COLDFIRE\nattach variables [ reg03y ereg03y reg12x ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ];\nattach variables [reg03ywu reg12xwu reg03yu ] [ D0u D1u D2u D3u D4u D5u D6u D7u A0u A1u A2u A3u A4u A5u A6u A7u ];\nattach variables [reg03ywl reg12xwl reg03yl ] [ D0w D1w D2w D3w D4w D5w D6w D7w A0w A1w A2w A3w A4w A5w A6w A7w ];\nattach variables [reg9dnu] [ D0u D1u D2u D3u D4u D5u D6u D7u ];\nattach variables [reg9dnl] [ D0w D1w D2w D3w D4w D5w D6w D7w ];\nattach variables [reg9anu] [ A0u A1u A2u A3u A4u A5u A6u A7u ];\nattach variables [reg9anl] [ A0w A1w A2w A3w A4w A5w A6w A7w ];\nattach variables [accw] [ACC0 ACC1 ACC2 ACC3];\n\nattach values d911 [ -1 1 2 3 4 5 6 7 ];\n@endif\n\nattach values scale [ 1 2 4 8 ];\nattach values quick [ 8 1 2 3 4 5 6 7 ];\n\ndefine pcodeop kfactor;\ndefine pcodeop ftrap;\ndefine pcodeop __m68k_trap;\ndefine pcodeop __m68k_trapv;\ndefine pcodeop reset;\ndefine pcodeop saveFPUStateFrame;\ndefine pcodeop restoreFPUStateFrame;\ndefine pcodeop invalidateCacheLines;\ndefine pcodeop pushInvalidateCaches;\n\ndefine pcodeop fetox;\ndefine pcodeop fetoxm1;\ndefine pcodeop fgetexp;\ndefine pcodeop fgetman;\ndefine pcodeop fint;\ndefine pcodeop flog10;\ndefine pcodeop flog2;\ndefine pcodeop flogn;\ndefine pcodeop flognp1;\ndefine pcodeop fmod;\ndefine pcodeop frem;\ndefine pcodeop fscale;\ndefine pcodeop fsgldiv;\ndefine pcodeop ftentox;\ndefine pcodeop ftwotox;\n\ndefine pcodeop bcdAdjust;\n\ndefine pcodeop sin;\ndefine pcodeop cos;\ndefine pcodeop tan;\ndefine pcodeop asin;\ndefine pcodeop acos;\ndefine pcodeop atan;\ndefine pcodeop sinh;\ndefine pcodeop cosh;\ndefine pcodeop tanh;\n\nea_index: regxan*scale\tis da=1 & wl=1 & regxan & scale\t\t{ tmp:4 = regxan*scale; export tmp; }\nea_index: regxanw*scale is da=1 & wl=0 & regxanw & scale \t{ tmp:4 = sext(regxanw)*scale; export tmp; }\nea_index: regxdn*scale\tis da=0 & wl=1 & regxdn & scale\t\t{ tmp:4 = regxdn*scale; export tmp; }\nea_index: regxdnw*scale\tis da=0 & wl=0 & regxdnw & scale\t{ tmp:4 = sext(regxdnw)*scale; export tmp; }\n\n\nbreg: regfan\t\t\tis eanum=0 & regfan\t\t{ export regfan; }\nbreg: regsan\t\t\tis eanum=1 & regsan\t\t{ export regsan; }\n#breg: PC is pcmode=1 & eanum & PC { tmp:4 = inst_start; }\n\nfl_breg: \"-\"\t\t\tis bs=1\t\t\t\t{ export 0:4; }\nfl_breg: \"ZPC\"\t\t\tis bs=1 & pcmode=1\t\t{ export 0:4; }\nfl_breg: breg\t\t\tis bs=0 & pcmode=0 & breg\t{ export breg; }\nfl_breg: PC\t\t\tis PC & bs=0 & pcmode=1 \t{ tmp:4 = inst_start + 2; export tmp; }\n\n# shift amount parameter\ncntreg: reg9dn\t\t\tis reg9dn & op5=1\t\t{ local tmp = reg9dn & 63; export tmp; }\ncntreg: \"#\"^quick\t\t\tis quick & op5=0\t\t{ export *[const]:4 quick; }\n\n# Extension word forms of the effective address\n # 8-bit displacement (brief extension)\nextw: d8,breg,ea_index is breg; ea_index & d8 & fbit=0\t\t\t\t\t\t\t{ local tmp = breg+d8+ea_index; export tmp; }\nextw: rela,PC,ea_index is pcmode=1 & PC; ea_index & d8 & fbit=0\n [ rela = inst_start+d8+2; ]\n\t\t\t\t\t { tmp:4 = rela; tmp = tmp+ea_index; export tmp; }\n # Base displacement (indexed)\nextw: fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=0\t\t\t\t\t{ local tmp = fl_breg+ea_index; export tmp; }\nextw: bd16,fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=0; bd16\t\t\t{ local tmp = fl_breg+ea_index+bd16; export tmp; }\nextw: bd32,fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=0; bd32\t\t\t{ local tmp = fl_breg+ea_index+bd32; export tmp; }\n # Memory Indirect Postindexed Mode\nextw: [fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=1\t\t\t\t{ local tmp = *:4 fl_breg + ea_index; export tmp; }\nextw: [bd16,fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=1; bd16\t\t\t{ local tmp = *:4 (fl_breg+bd16) + ea_index; export tmp; }\nextw: [bd32,fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=1; bd32\t\t\t{ local tmp = *:4 (fl_breg+bd32) + ea_index; export tmp; }\nextw: [fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=2; od16\t\t\t{ local tmp = *:4 fl_breg + ea_index + od16; export tmp; }\nextw: [bd16,fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=2; bd16; od16\t\t{ local tmp = *:4 (fl_breg+bd16) + ea_index + od16; export tmp; }\nextw: [bd32,fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=2; bd32; od16\t\t{ local tmp = *:4 (fl_breg+bd32) + ea_index + od16; export tmp; }\nextw: [fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=3; od32\t\t\t{ local tmp = *:4 fl_breg + ea_index + od32; export tmp; }\nextw: [bd16,fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=3; bd16; od32\t\t{ local tmp = *:4 (fl_breg+bd16) + ea_index + od32; export tmp; }\nextw: [bd32,fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=3; bd32; od32\t\t{ local tmp = *:4 (fl_breg+bd32) + ea_index + od32; export tmp; }\n # Memory Indirect Preindexed Mode\nextw: [fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=5\t\t\t\t{ local tmp = *:4 (fl_breg+ea_index); export tmp; }\nextw: [bd16,fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=5; bd16\t\t\t{ local tmp = *:4 (fl_breg+ea_index+bd16); export tmp; }\nextw: [bd32,fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=5; bd32\t\t\t{ local tmp = *:4 (fl_breg+ea_index+bd32); export tmp; }\nextw: [fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=6; od16\t\t\t{ local tmp = *:4 (fl_breg+ea_index) + od16; export tmp; }\nextw: [bd16,fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=6; bd16; od16\t\t{ local tmp = *:4 (fl_breg+ea_index+bd16) + od16; export tmp; }\nextw: [bd32,fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=6; bd32; od16\t\t{ local tmp = *:4 (fl_breg+ea_index+bd32) + od16; export tmp; }\nextw: [fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=7; od32\t\t\t{ local tmp = *:4 (fl_breg+ea_index) + od32; export tmp; }\nextw: [bd16,fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=7; bd16; od32\t\t{ local tmp = *:4 (fl_breg+ea_index+bd16) + od32; export tmp; }\nextw: [bd32,fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=7; bd32; od32\t\t{ local tmp = *:4 (fl_breg+ea_index+bd32) + od32; export tmp; }\n # Base displacement\nextw: fl_breg is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=0\t\t\t\t\t\t\t{ export fl_breg; }\nextw: bd16,fl_breg is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=0; bd16\t\t\t\t\t\t{ local tmp = fl_breg+bd16; export tmp; }\nextw: bd32,fl_breg is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=0; bd32\t\t\t\t\t\t{ local tmp = fl_breg+bd32; export tmp; }\n # Memory Indirect\nextw: [fl_breg] is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=1\t\t\t\t\t\t\t{ local tmp = *:4 fl_breg; export tmp; }\nextw: [bd16,fl_breg] is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=1; bd16\t\t\t\t\t{ local tmp = *:4 (fl_breg+bd16); export tmp; }\nextw: [bd32,fl_breg] is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=1; bd32\t\t\t\t\t{ local tmp = *:4 (fl_breg+bd32); export tmp; }\nextw: [fl_breg],od16 is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=2; od16\t\t\t\t\t{ local tmp = *:4 fl_breg + od16; export tmp; }\nextw: [bd16,fl_breg],od16 is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=2; bd16; od16\t\t\t\t{ local tmp = *:4 (fl_breg+bd16) + od16; export tmp; }\nextw: [bd32,fl_breg],od16 is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=2; bd32; od16\t\t\t\t{ local tmp = *:4 (fl_breg+bd32) + od16; export tmp; }\nextw: [fl_breg],od32 is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=3; od32\t\t\t\t\t{ local tmp = *:4 fl_breg + od32; export tmp; }\nextw: [bd16,fl_breg],od32 is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=3; bd16; od32\t\t\t\t{ local tmp = *:4 (fl_breg+bd16) + od32; export tmp; }\nextw: [bd32,fl_breg],od32 is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=3; bd32; od32\t\t\t\t{ local tmp = *:4 (fl_breg+bd32) + od32; export tmp; }\n\n\n# The main effective address table\n # size=long\neal: regdn is mode=0 & regdn\t\t\t{ export regdn; }\neal: regan is mode=1 & regan\t\t\t{ export regan; }\neal: (regan) is mode=2 & regan\t\t\t{ export *:4 regan; }\neal: (regan)+ is mode=3 & regan\t\t\t{ local tmp = regan; regan = regan + 4; export *:4 tmp; }\neal: -(regan) is mode=4 & regan\t\t\t{ regan = regan - 4; export *:4 regan; }\neal: (d16,regan) is mode=5 & regan; d16\t\t{ local tmp = regan + d16; export *:4 tmp; }\neal: (extw) is mode=6 & regan; extw\t\t[ regtfan = regan; pcmode = 0; ] { build extw; export *:4 extw; }\neal: (d16,PC) is PC & mode=7 & regan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:4 tmp; }\neal: (extw) is mode=7 & regan=3; extw\t\t[ pcmode=1; ] { build extw; export *:4 extw; }\neal: (d16)\".w\" is mode=7 & regan=0; d16\t\t{ export *:4 d16; }\neal: (d32)\".l\" is mode=7 & regan=1; d32\t\t{ export *:4 d32; }\neal: \"#\"^d32 is mode=7 & regan=4; d32\t\t{ export *[const]:4 d32; }\n # size=word\neaw: regdnw is mode=0 & regdnw\t\t\t{ export regdnw; }\neaw: reganw is mode=1 & reganw\t\t\t{ export reganw; }\neaw: (regan) is mode=2 & regan\t\t\t{ export *:2 regan; }\neaw: (regan)+ is mode=3 & regan\t\t\t{ local tmp = regan; regan = regan + 2; export *:2 tmp; }\neaw: -(regan) is mode=4 & regan\t\t\t{ regan = regan - 2; export *:2 regan; }\neaw: (d16,regan) is mode=5 & regan; d16\t\t{ local tmp = regan + d16; export *:2 tmp; }\neaw: (extw) is mode=6 & regan; extw\t\t[ pcmode=0; regtfan=regan; ] { build extw; export *:2 extw; }\neaw: (d16,PC) is PC & mode=7 & regan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:2 tmp; }\neaw: (extw) is mode=7 & regan=3; extw\t\t[ pcmode=1; ] { build extw; export *:2 extw; }\neaw: (d16)\".w\" is mode=7 & regan=0; d16\t\t{ export *:2 d16; }\neaw: (d32)\".l\" is mode=7 & regan=1; d32\t\t{ export *:2 d32; }\neaw: \"#\"^d16 is mode=7 & regan=4; d16\t\t{ export *[const]:2 d16; }\n # size=byte\neab: regdnb is mode=0 & regdnb\t\t\t{ export regdnb; }\neab: reganb is mode=1 & reganb\t\t\t{ export reganb; }\neab: (regan) is mode=2 & regan\t\t\t{ export *:1 regan; }\neab: (regan)+ is mode=3 & regan & regan=7\t{ local tmp = regan; regan = regan + 2; export *:1 tmp; }\neab: (regan)+ is mode=3 & regan\t\t\t{ local tmp = regan; regan = regan + 1; export *:1 tmp; }\neab: -(regan) is mode=4 & regan & regan=7\t{ regan = regan - 2; export *:1 regan; }\neab: -(regan) is mode=4 & regan\t\t\t{ regan = regan - 1; export *:1 regan; }\neab: (d16,regan) is mode=5 & regan; d16\t\t{ local tmp = regan + d16; export *:1 tmp; }\neab: (extw) is mode=6 & regan; extw\t\t[ pcmode=0; regtfan=regan; ] { build extw; export *:1 extw; }\neab: (d16,PC) is PC & mode=7 & regan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:1 tmp; }\neab: (extw) is mode=7 & regan=3; extw\t\t[ pcmode=1; ] { build extw; export *:1 extw; }\neab: (d16)\".w\" is mode=7 & regan=0; d16\t\t{ export *:1 d16; }\neab: (d32)\".l\" is mode=7 & regan=1; d32\t\t{ export *:1 d32; }\neab: \"#\"^d8 is mode=7 & regan=4; d8\t\t{ export *[const]:1 d8; }\n\n# Second effective address calculation for mov\n\n# NB- Extended-precsion are 12 bytes, so we need to increment or decrement the reg by 12 not 4\n#\n # size=extend | packed (96-bit)\n # The fmovem.x insn needs the movemptr to be set here\ne2x: (regsan) is savmod2=2 & regsan { movemptr = regsan; export *:12 regsan; }\ne2x: (regsan)+ is savmod2=3 & regsan { movemptr = regsan; local tmp = regsan; regsan = regsan + 12; export *:12 tmp; }\ne2x: -(regsan) is savmod2=4 & regsan { movemptr = regsan; regsan = regsan - 12; export *:12 regsan; }\ne2x: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; movemptr = tmp; export *:12 tmp; }\ne2x: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; movemptr = extw; export *:12 extw; }\ne2x: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; movemptr = tmp; export *:12 tmp; }\ne2x: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; movemptr = extw; export *:12 extw; }\ne2x: (d16)\".w\" is savmod2=7 & regsan=0; d16 { movemptr = d16; export *:12 d16; }\ne2x: (d32)\".l\" is savmod2=7 & regsan=1; d32 { movemptr = d32; export *:12 d32; }\ne2x: \"#( -1E\"^signX^\" * 2E\"^exp^\"*1.\"^mantissaX)\tis savmod1=7 & regtfan=4; signX & exponentX; expintbitX & mantissaX\n\t\t[exp=exponentX-0x3FFF;]\n\t\t{ movemptr = mantissaX; export *[const]:12 mantissaX; } # bug: doesn't construct a real, only exports the 64-bit mantissa\n # size=quad (limited mode)\n\n# NB- Doubles are 8 bytes, so we need to increment or decrement the reg by 8 not 4\n#\ne2d: (regsan)\t\tis savmod2=2 & regsan\t\t{ export *:8 regsan; }\ne2d: (regsan)+\t\tis savmod2=3 & regsan\t\t{ local tmp = regsan; regsan = regsan + 8; export *:8 tmp; }\ne2d: -(regsan)\t\tis savmod2=4 & regsan\t\t{ regsan = regsan - 8; export *:8 regsan; }\ne2d: (d16,regsan)\tis savmod2=5 & regsan; d16\t{ local tmp = regsan + d16; export *:8 tmp; }\ne2d: (extw)\t\t\tis savmod2=6; extw\t\t\t[ pcmode=0; eanum=1; ] { build extw; export *:8 extw; }\ne2d: (d16,PC)\t\tis PC & savmod2=7 & regsan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:8 tmp; }\ne2d: (extw)\t\t\tis savmod2=7 & regsan=3; extw\t[ pcmode=1; ] { build extw; export *:8 extw; }\ne2d: (d16)\".w\"\t\tis savmod2=7 & regsan=0; d16\t{ export *:8 d16; }\ne2d: (d32)\".l\"\t\tis savmod2=7 & regsan=1; d32\t{ export *:8 d32; }\ne2d: \"#\"^d64\t\t\tis savmod2=7 & regsan=4; d64\t{ export *[const]:8 d64; }\n\n # size=long\ne2l: regsdn\t\t\tis savmod2=0 & regsdn\t\t{ export regsdn; }\ne2l: regsan\t\t\tis savmod2=1 & regsan\t\t{ export regsan; }\ne2l: (regsan)\t\tis savmod2=2 & regsan\t\t{ export *:4 regsan; }\ne2l: (regsan)+\t\tis savmod2=3 & regsan\t\t{ local tmp = regsan; regsan = regsan + 4; export *:4 tmp; }\ne2l: -(regsan)\t\tis savmod2=4 & regsan\t\t{ regsan = regsan - 4; export *:4 regsan; }\ne2l: (d16,regsan)\tis savmod2=5 & regsan; d16\t{ local tmp = regsan + d16; export *:4 tmp; }\ne2l: (extw)\t\t\tis savmod2=6; extw\t\t\t[ pcmode=0; eanum=1; ] { build extw; export *:4 extw; }\ne2l: (d16,PC)\t\tis PC & savmod2=7 & regsan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:4 tmp; }\ne2l: (extw)\t\t\tis savmod2=7 & regsan=3; extw\t[ pcmode=1; ] { build extw; export *:4 extw; }\ne2l: (d16)\".w\"\t\tis savmod2=7 & regsan=0; d16\t{ export *:4 d16; }\ne2l: (d32)\".l\"\t\tis savmod2=7 & regsan=1; d32\t{ export *:4 d32; }\ne2l: \"#\"^d32\t\t\tis savmod2=7 & regsan=4; d32\t{ export *[const]:4 d32; }\n # size=word\ne2w: regsdnw is savmod2=0 & regsdnw\t\t{ export regsdnw; }\ne2w: regsanw is savmod2=1 & regsanw\t\t{ export regsanw; }\ne2w: (regsan) is savmod2=2 & regsan\t\t{ export *:2 regsan; }\ne2w: (regsan)+ is savmod2=3 & regsan\t\t{ local tmp = regsan; regsan = regsan + 2; export *:2 tmp; }\ne2w: -(regsan) is savmod2=4 & regsan\t\t{ regsan = regsan - 2; export *:2 regsan; }\ne2w: (d16,regsan) is savmod2=5 & regsan; d16\t{ local tmp = regsan + d16; export *:2 tmp; }\ne2w: (extw) is savmod2=6; extw\t\t\t[ pcmode=0; eanum=1; ] { build extw; export *:2 extw; }\ne2w: (d16,PC) is PC & savmod2=7 & regsan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:2 tmp; }\ne2w: (extw) is savmod2=7 & regsan=3; extw\t[ pcmode=1; ] { build extw; export *:2 extw; }\ne2w: (d16)\".w\" is savmod2=7 & regsan=0; d16\t{ export *:2 d16; }\ne2w: (d32)\".l\" is savmod2=7 & regsan=1; d32\t{ export *:2 d32; }\ne2w: \"#\"^d16 is savmod2=7 & regsan=4; d16\t\t{ export *[const]:2 d16; }\n\n # size=byte\n # NB- Manual says that if in predecrement or postincrement mode and the res is the SP, then must inc/dec by 2, not by 1\ne2b: regsdnb is savmod2=0 & regsdnb\t\t{ export regsdnb; }\ne2b: regsanb is savmod2=1 & regsanb\t\t{ export regsanb; }\ne2b: (regsan) is savmod2=2 & regsan\t\t{ export *:1 regsan; }\ne2b: (regsan)+ is savmod2=3 & regsan & regsan=7\t{ local tmp = regsan; regsan = regsan + 2; export *:1 tmp; }\ne2b: (regsan)+ is savmod2=3 & regsan\t\t{ local tmp = regsan; regsan = regsan + 1; export *:1 tmp; }\ne2b: -(regsan) is savmod2=4 & regsan & regsan=7\t{ regsan = regsan - 2; export *:1 regsan; }\ne2b: -(regsan) is savmod2=4 & regsan\t\t{ regsan = regsan - 1; export *:1 regsan; }\ne2b: (d16,regsan) is savmod2=5 & regsan; d16\t{ local tmp = regsan + d16; export *:1 tmp; }\ne2b: (extw) is savmod2=6; extw\t\t\t[ pcmode=0; eanum=1; ] { build extw; export *:1 extw; }\ne2b: (d16,PC) is PC & savmod2=7 & regsan=2; d16\t{ tmp:4 = inst_start + 2 + d16; export *:1 tmp; }\ne2b: (extw) is savmod2=7 & regsan=3; extw\t[ pcmode=1; ] { build extw; export *:1 extw; }\ne2b: (d16)\".w\" is savmod2=7 & regsan=0; d16\t{ export *:1 d16; }\ne2b: (d32)\".l\" is savmod2=7 & regsan=1; d32\t{ export *:1 d32; }\ne2b: \"#\"^d8 is savmod2=7 & regsan=4; d8\t\t{ export *[const]:1 d8; }\n\n# For instructions like lea and pea that manipulative the effective address\n# itself rather than the data the address is pointing at\neaptr: (regan)\t\t\tis mode=2 & regan\t\t\t\t\t{ export regan; }\neaptr: (d16,regan)\t\tis mode=5 & regan; d16\t\t\t\t\t{ local tmp = regan+d16; export tmp; }\neaptr: (extw)\t\t\tis mode=6 & regan; extw\t\t\t\t\t[ pcmode=0; regtfan=regan; ] { export extw; }\neaptr: (d16,PC)\t\t\tis mode=7 & regan=2; d16 & PC\t\t\t\t{ tmp:4 = inst_start+2+d16; export tmp; }\neaptr: (extw)\t\t\tis mode=7 & regan=3; extw\t\t\t\t[ pcmode=1; ] { export extw; }\neaptr: (d16)\".w\"\t\tis mode=7 & regan=0; d16\t\t\t\t{ export *[const]:4 d16; }\neaptr: (d32)\".l\"\t\tis mode=7 & regan=1; d32\t\t\t\t{ export *[const]:4 d32; }\n\n# Data register or predecrement addressing\nTy: -(regan)\tis rmbit=1 & regan\t\t{ regan = regan-4; export *:4 regan; }\nTy: regdn\tis rmbit=0 & regdn\t\t{ export regdn; }\nTx: -(reg9an)\tis rmbit=1 & reg9an\t\t{ reg9an = reg9an-4; export *:4 reg9an; }\nTx: reg9dn\tis rmbit=0 & reg9dn\t\t{ export reg9dn; }\nTyw: -(regan)\tis rmbit=1 & regan\t\t{ regan = regan-2; export *:2 regan; }\nTyw: regdnw\tis rmbit=0 & regdnw\t\t{ export regdnw; }\nTxw: -(reg9an)\tis rmbit=1 & reg9an\t\t{ reg9an = reg9an-2; export *:2 reg9an; }\nTxw: reg9dnw\tis rmbit=0 & reg9dnw\t\t{ export reg9dnw; }\nTyb: -(regan)\tis rmbit=1 & regan\t\t{ regan = regan-1; export *:1 regan; }\nTyb: regdnb\tis rmbit=0 & regdnb\t\t{ export regdnb; }\nTxb: -(reg9an)\tis rmbit=1 & reg9an\t\t{ reg9an = reg9an-1; export *:1 reg9an; }\nTxb: reg9dnb\tis rmbit=0 & reg9dnb\t\t{ export reg9dnb; }\n\n# Bit field parameters\nf_off: fldoffdat\tis flddo=0 & fldoffdat\t{ export *[const]:4 fldoffdat; }\nf_off: fldoffreg\tis flddo=1 & fldoffreg\t{ export fldoffreg; }\nf_wd: fldwddat\t\tis flddw=0 & fldwddat\t{ export *[const]:4 fldwddat; }\nf_wd: fldwdreg\t\tis flddw=1 & fldwdreg\t{ export fldwdreg; }\n\nrreg: regxdn\t\tis da=0 & regxdn\t{ export regxdn; }\nrreg: regxan\t\tis da=1 & regxan\t{ export regxan; }\n\nregPlus: (regan)+ is regan { export regan; }\nregxPlus: (regxan)+ is regxan { export regxan; }\nreg9Plus: (reg9an)+ is reg9an { export reg9an; }\nregParen: (regan) is regan { export regan; }\nd32l: (d32)\".l\" is d32 { export *[const]:4 d32; }\n\n# Condition codes\n\ncc: \"t\"\t\tis op811=0\t\t\t{ export 1:1; }\ncc: \"f\"\t\tis op811=1\t\t\t{ export 0:1; }\ncc: \"hi\"\tis op811=2\t\t\t{ tmp:1 = !(CF || ZF); export tmp; }\ncc: \"ls\"\tis op811=3\t\t\t{ tmp:1 = CF || ZF; export tmp; }\ncc: \"cc\"\tis op811=4\t\t\t{ tmp:1 = !CF; export tmp; }\ncc: \"cs\"\tis op811=5\t\t\t{ export CF; }\ncc: \"ne\"\tis op811=6\t\t\t{ tmp:1 = !ZF; export tmp; }\ncc: \"eq\"\tis op811=7\t\t\t{ export ZF; }\ncc: \"vc\"\tis op811=8\t\t\t{ tmp:1 = !VF; export tmp; }\ncc: \"vs\"\tis op811=9\t\t\t{ export VF; }\ncc: \"pl\"\tis op811=10\t\t\t{ tmp:1 = !NF; export tmp; }\ncc: \"mi\"\tis op811=11\t\t\t{ export NF; }\ncc: \"ge\"\tis op811=12\t\t\t{ tmp:1 = (VF==NF); export tmp; }\ncc: \"lt\"\tis op811=13\t\t\t{ tmp:1 = (VF!=NF); export tmp; }\ncc: \"gt\"\tis op811=14\t\t\t{ tmp:1 = !ZF && (VF==NF); export tmp; }\ncc: \"le\"\tis op811=15\t\t\t{ tmp:1 = ZF || (VF!=NF); export tmp; }\n\nconst8: \"#\"^d8 is d8\t\t{ export *[const]:1 d8; }\nconst16: \"#\"^d16 is d16\t\t{ export *[const]:2 d16; }\nconst32: \"#\"^d32 is d32\t\t{ export *[const]:4 d32; }\n\nctlreg: SFC is SFC & ctl=0x000 { export SFC; }\nctlreg: DFC is DFC & ctl=0x001 { export DFC; }\nctlreg: USP is USP & ctl=0x800 { export USP; }\nctlreg: VBR is VBR & ctl=0x801 { export VBR; }\nctlreg: CACR is CACR & ctl=0x002 { export CACR; }\nctlreg: CAAR is CAAR & ctl=0x802 { export CAAR; }\nctlreg: MSP is MSP & ctl=0x803 { export MSP; }\nctlreg: ISP is ISP & ctl=0x804 { export ISP; }\nctlreg: TC is TC & ctl=0x003 { export TC; }\nctlreg: ITT0 is ITT0 & ctl=0x004 { export ITT0; }\nctlreg: ITT1 is ITT1 & ctl=0x005 { export ITT1; }\nctlreg: DTT0 is DTT0 & ctl=0x006 { export DTT0; }\nctlreg: DTT1 is DTT1 & ctl=0x007 { export DTT1; }\nctlreg: SRP is SRP & ctl=0x008 { export BUSCR; }\nctlreg: MMUSR is MMUSR & ctl=0x805 { export MMUSR; }\nctlreg: URP is URP & ctl=0x806 { export URP; }\nctlreg: SRP is SRP & ctl=0x807 { export SRP; }\nctlreg: PCR is PCR & ctl=0x808 { export PCR; }\nctlreg: RAMBAR0 is RAMBAR0 & ctl=0xc04 { export RAMBAR0; }\nctlreg: RAMBAR1 is RAMBAR1 & ctl=0xc05 { export RAMBAR1; }\n# ctlreg: PCR is PCR & ctl=0x808 { export PCR; }\nctlreg: CAC is CAC & ctl=0xffe { export CAC; }\nctlreg: MBB is MBB & ctl=0xfff { export MBB; }\nctlreg: \"UNK_CTL_\"^ctl is ctl { tmp:4 = 0xffffffff; export tmp; } \n\n\n# Relative jump destinations\naddr8: reloc is d8base [ reloc=inst_start+2+d8base; ]\t{ export *[ram]:4 reloc; }\naddr16: reloc\tis d16 [ reloc=inst_start+2+d16; ]\t\t{ export *[ram]:4 reloc; }\naddr32: reloc\tis d32 [ reloc=inst_start+2+d32; ]\t\t{ export *[ram]:4 reloc; }\n# Jump locations for coprocessor instructions\n#caddr16: reloc is d16\t[ reloc=inst_next-2+d16; ]\t\t{ export *[ram]:4 reloc; }\n#caddr32: reloc is d32\t[ reloc=inst_next-4+d32; ]\t\t{ export *[ram]:4 reloc; }\n\n# Macros for flags etc\n\n\nmacro resflags(result) {\n NF = result s< 0;\n ZF = result == 0;\n}\n\nmacro logflags() {\n VF=0;\n CF=0;\n}\n\nmacro addflags(op1,op2) {\n CF = carry(op1,op2);\n VF = scarry(op1,op2);\n XF = CF;\n}\n\nmacro addxflags(op1, op2) {\n\tlocal opSum = op1 + op2;\n\tCF = carry(op1, op2) || carry(opSum, zext(XF));\n\tVF = scarry(op1, op2) ^^ scarry(opSum, zext(XF));\n}\n\nmacro add(op1, op2res) {\n\tlocal var1 = op1;\n\tlocal var2 = op2res;\n\taddflags(var1, var2);\n\tlocal result = var1 + var2;\n\top2res = result;\n\tresflags(result);\n}\n\nmacro and(op1,op2res) {\n\tlogflags();\n\tlocal result = op1 & op2res;\n\top2res = result;\n\tresflags(result);\n}\n\nmacro eor(op1,op2res) {\n\tlogflags();\n\tlocal result = op1 ^ op2res;\n\top2res = result;\n\tresflags(result);\n}\n\nmacro or(op1,op2res) {\n\tlogflags();\n\tlocal result = op1 | op2res;\n\top2res = result;\n\tresflags(result);\n}\n\nmacro subflags(op1,op2) {\n CF = op1 < op2;\n VF = sborrow(op1,op2);\n XF = CF;\n}\n\nmacro sub(op1,op2res) {\n\tlocal var1 = op1;\n\tlocal var2 = op2res;\n\tsubflags(var2, var1);\n\tlocal result = var2 - var1;\n\top2res = result;\n\tresflags(result);\n}\n\n# This macro needs to consider the XF flag when finding the CF carry flag value: op1=op1-op2-XF\n# original was: CF = op1 < op2;\nmacro subxflags(op1,op2) {\n CF = (op1 < op2) || ( (XF == 1) && (op1 == op2) );\n VF = sborrow(op1,op2);\n XF = CF;\n}\n\nmacro negxsubflags(op1) {\n CF = 0 s< op1;\n VF = sborrow(0,op1);\n XF = CF;\n}\n\nmacro resflags_fp(result) {\n $(I_FP) = 0;\n $(NAN_FP) = 0;\n $(N_FP) = result f< 0;\n $(Z_FP) = result == 0;\n}\n\nmacro clearflags_fp() {\n $(N_FP) = 0;\n $(Z_FP) = 0;\n $(NAN_FP) = 0;\n}\n\nmacro bcdflags(result) {\n XF = CF;\n ZF = (result == 0) * ZF + (result != 0);\n}\n\nmacro getbit(res,in,bitnum) {\n res = ((in >> bitnum) & 1) != 0;\n}\n\nmacro bitmask(res, width) {\n res = (1 << width) - 1;\n}\n\nmacro bfmask (res, off, width) {\n res = ((1 << width) - 1) << (32 - off - width);\n}\n\nmacro getbitfield(res, off, width) {\n res = (res << off) >> (32 - width);\n}\n\nmacro resbitflags(result, bitnum) {\n NF = ((result >> bitnum) & 1) != 0;\n ZF = result == 0;\n}\n\nmacro packflags(res) {\n res = zext((TF<<15)|(SVF<<13)|(IPL<<8)|(XF<<4)|(NF<<3)|(ZF<<2)|(VF<<1)|CF);\n}\n\nmacro unpackflags(in) {\n TF = (in & 0x8000)!=0;\n SVF = (in & 0x2000)!=0;\n IPL = in[8,3];\n XF = (in & 0x10)!=0;\n NF = (in & 8)!=0;\n ZF = (in & 4)!=0;\n VF = (in & 2)!=0;\n CF = (in & 1)!=0;\n}\n\n# This macro sets the NF and ZF flags for extended arithmetic insns- addx, negx, and subx\nmacro extendedResultFlags(result) {\n NF = result s< 0;\n ZF = (result == 0) && (ZF == 1);\n}\n\nmacro arithmeticShiftLeft(count, register, width) {\n\tlocal modcount = count & 63;\n\tlocal lbit:1 = ((register >> (width - modcount) & 1) != 0);\n\tlocal msbBefore:4 = zext(register s< 0);\n\tregister = register << modcount;\n\tresflags(register);\n\tlocal msbAfter:4 = zext(register s< 0);\n\tVF = (msbBefore ^ msbAfter) != 0;\n\tCF = (modcount != 0) * lbit;\n\tXF = ((modcount == 0) * XF) + ((modcount != 0) * CF);\n}\n\nmacro arithmeticShiftRight(count, register, width) {\n\tlocal modcount = count & 63;\n\tlocal lbit:1 = ((register >> (modcount-1) & 1) != 0);\n\tlocal msbBefore:4 = zext(register s< 0);\n\tregister = register s>> modcount;\n\tresflags(register);\n\tlocal msbAfter:4 = zext(register s< 0);\n\tVF = (msbBefore ^ msbAfter) != 0;\n\tCF = (modcount != 0) * lbit;\n\tXF = ((modcount == 0) * XF) + ((modcount != 0) * CF);\n}\n\nmacro logicalShiftLeft(count, register, width) {\n\tlocal modcount = count & 63;\n\tlocal lbit:1 = ((register >> (width - modcount) & 1) != 0);\n\tlocal msbBefore:4 = zext(register s< 0);\n\tregister = register << modcount;\n\tresflags(register);\n\tlocal msbAfter:4 = zext(register s< 0);\n\tVF = (msbBefore ^ msbAfter) != 0;\n\tCF = (modcount != 0) * lbit;\n\tXF = ((modcount == 0) * XF) + ((modcount != 0) * CF);\n}\n\nmacro logicalShiftRight(count, register, width) {\n\tlocal modcount = count & 63;\n\tlocal lbit:1 = ((register >> (modcount-1) & 1) != 0);\n\tlocal msbBefore:4 = zext(register s< 0);\n\tregister = register >> modcount;\n\tresflags(register);\n\tlocal msbAfter:4 = zext(register s< 0);\n\tVF = (msbBefore ^ msbAfter) != 0;\n\tCF = (modcount != 0) * lbit;\n\tXF = ((modcount == 0) * XF) + ((modcount != 0) * CF);\n}\n\nmacro rotateLeft(count, register, width) {\n\tlocal modcount = count & 63;\n\tregister = (register << modcount) | (register >> (width - modcount));\n\tresflags(register);\n\tCF = (register & 1) != 0;\n\tVF = 0;\n}\n\nmacro rotateRight(count, register, width) {\n\tlocal modcount = count & 63;\n\tregister = (register << (width - modcount)) | (register >> modcount);\n\tresflags(register);\n\tCF = zext(register s< 0);\n\tVF = 0;\n}\n\nmacro rotateLeftExtended(count, register, width) {\n\tlocal modcount = count & 63;\n\tlocal xflag = (register & (1 << (width - modcount))) != 0;\n\tlocal result = (register << modcount) | (zext(XF) << (modcount - 1)) | (register >> (width - modcount + 1));\n\tregister = (zext(modcount != 0) * result) + (zext(modcount == 0) * register);\n\tresflags(register);\n\tXF = (zext(modcount != 0) * xflag) + (zext(modcount == 0) * XF);\n\tCF = XF;\n\tVF = 0;\n}\n\nmacro rotateRightExtended(count, register, width) {\n\tlocal modcount = count & 63;\n\tlocal xflag = (register & (1 << (modcount - 1))) != 0;\n\tlocal result = (zext(XF) << (width - modcount)) | (register >> modcount) | (register << (width - modcount + 1));\n\tregister = (zext(modcount != 0) * result) + (zext(modcount == 0) * register);\n\tresflags(register);\n\tXF = (zext(modcount != 0) * xflag) + (zext(modcount == 0) * XF);\n\tCF = XF;\n\tVF = 0;\n}\n\n:^instruction\tis extGUARD=0 & mode2 & reg9an & mode & regan & instruction\n\t\t\t\t[ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ]\t{}\n\n# Here are the instructions\n\nwith : extGUARD=1 {\n\n:abcd Tyb,Txb\t\t\tis op=12 & op48=16 & Tyb & Txb {\n\tCF = carry(Txb,carry(Tyb,XF));\n\tTxb = Txb + Tyb + XF;\n\tXF = bcdAdjust(Txb);\n\tbcdflags(Txb);\n}\n\n:add.b eab,reg9dnb\t\t\tis (op=13 & reg9dnb & op68=0)... & eab\t\t\t\t{ add(eab, reg9dnb); }\n:add.w eaw,reg9dnw\t\t\tis (op=13 & reg9dnw & op68=1)... & eaw\t\t\t\t{ add(eaw,reg9dnw); }\n:add.l eal,reg9dn\t\t\tis (op=13 & reg9dn & op68=2)... & eal\t\t\t\t{ add(eal,reg9dn); }\n:add.b reg9dnb,eab\t\t\tis (op=13 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab\t{ add( reg9dnb, eab); }\n:add.w reg9dnw,eaw\t\t\tis (op=13 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw\t{ add(reg9dnw,eaw); }\n:add.l reg9dn,eal\t\t\tis (op=13 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal\t{ add(reg9dn,eal); }\n\n:adda.w eaw,reg9an\t\t\tis (op=13 & reg9an & op68=3)... & eaw\t\t\t\t{ reg9an = sext(eaw) + reg9an; }\n:adda.l eal,reg9an\t\t\tis (op=13 & reg9an & op68=7)... & eal\t\t\t\t{ reg9an = eal + reg9an; }\n\n:addi.b const8,e2b\t\t\tis opbig=6 & op67=0 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const8; e2b\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ add(const8, e2b); }\n:addi.w const16,e2w\t\t\tis opbig=6 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const16; e2w\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ add(const16,e2w); }\n:addi.l const32,e2l\t\t\tis opbig=6 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const32; e2l\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ add(const32,e2l); }\n\n:addq.b \"#\"^quick,eab\t\tis (op=5 & quick & op68=0)... & eab\t\t\t\t{ add(quick, eab); }\n:addq.w \"#\"^quick,eaw\t\tis (op=5 & quick & op68=1)... & eaw\t\t\t\t{ add(quick, eaw); }\n:addq.l \"#\"^quick,eal\t\tis (op=5 & quick & op68=2)... & eal\t\t\t\t{ add(quick, eal); }\n# special case for address register destination\n:addq.w \"#\"^quick,regan\t\tis op=5 & quick & op68=1 & mode=1 & regan\t\t{ regan = regan + quick; }\n:addq.l \"#\"^quick,regan\t\tis op=5 & quick & op68=2 & mode=1 & regan\t\t{ regan = regan + quick; }\n\n\n:addx.b Tyb,Txb\t\t\tis op=13 & op8=1 & op67=0 & op45=0 & Tyb & Txb\n\t\t\t\t\t{ addxflags(Tyb,Txb); Txb=Tyb+Txb+zext(XF); extendedResultFlags(Txb); }\n:addx.w Tyw,Txw\t\t\tis op=13 & op8=1 & op67=1 & op45=0 & Tyw & Txw\n\t\t\t\t\t{ addxflags(Tyw,Txw); Txw=Tyw+Txw+zext(XF); extendedResultFlags(Txw); }\n:addx.l Ty,Tx\t\t\tis op=13 & op8=1 & op67=2 & op45=0 & Ty & Tx\n\t\t\t\t\t{ addxflags(Ty,Tx); Tx=Ty+Tx+zext(XF); extendedResultFlags(Tx); }\n\n:and.b eab,reg9dnb\t\tis (op=12 & reg9dnb & op68=0 & $(DAT_ALTER_ADDR_MODES))... & eab\t{ and(eab, reg9dnb); }\n:and.w eaw,reg9dnw\t\tis (op=12 & reg9dnw & op68=1 & $(DAT_ALTER_ADDR_MODES))... & eaw\t{ and(eaw, reg9dnw); }\n:and.l eal,reg9dn\t\tis (op=12 & reg9dn & op68=2 & $(DAT_ALTER_ADDR_MODES))... & eal\t\t{ and(eal, reg9dn); }\n:and.b reg9dnb,eab\t\tis (op=12 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab\t{ and(reg9dnb, eab); }\n:and.w reg9dnw,eaw\t\tis (op=12 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw\t{ and(reg9dnw, eaw); }\n:and.l reg9dn,eal\t\tis (op=12 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal\t\t{ and(reg9dn, eal); }\n\n:andi.b const8,e2b\t\tis opbig=2 & op67=0 & $(DAT_ALTER_ADDR_MODES); const8; e2b\t\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ and(const8, e2b); }\n:andi.w const16,e2w\t\tis opbig=2 & op67=1 & $(DAT_ALTER_ADDR_MODES); const16; e2w\t\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ and(const16, e2w); }\n:andi.l const32,e2l\t\tis opbig=2 & op67=2 & $(DAT_ALTER_ADDR_MODES); const32; e2l\t\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ and(const32, e2l); }\n\n:andi const8,\"CCR\"\t\t\tis d16=0x23c; const8\t\t\t\t\t\t\t\t\t{ packflags(SR); SR = SR & zext(const8); unpackflags(SR); }\n:andi const16,SR\t\t\tis opbig=0x2 & d8base=0x7c; const16 & SR\t\t\t\t{ packflags(SR); SR = SR & const16; unpackflags(SR); }\n\n:asl.b cntreg,regdnb\t\tis op=14 & cntreg & op8=1 & op67=0 & op34=0 & regdnb\t{\n\tlocal cnt = cntreg;\n\tlocal result = regdnb;\n\tarithmeticShiftLeft(cnt, result, 8);\n\tregdnb = result;\n}\n\n:asl.w cntreg,regdnw\t\tis op=14 & cntreg & op8=1 & op67=1 & op34=0 & regdnw\t{\n\tlocal cnt = cntreg;\n\tlocal result = regdnw;\n\tarithmeticShiftLeft(cnt, result, 16);\n\tregdnw = result;\n}\n\n:asl.l cntreg,regdn\t\tis op=14 & cntreg & op8=1 & op67=2 & op34=0 & regdn\t\t\t{\n\tlocal cnt = cntreg;\n\tlocal result = regdn;\n\tarithmeticShiftLeft(cnt, result, 32);\n\tregdn = result;\n}\n\n:asl eaw\t\t\tis (opbig=0xe1 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tlocal msbBefore = value & 0x8000;\n\tgetbit(CF, value, 15);\n\tvalue = value << 1;\n\tresflags(value);\n\tlocal msbAfter = value & 0x8000;\n\tVF = (msbBefore ^ msbAfter) != 0;\n\teaw = value;\n\tXF = CF;\n}\n\n:asr.b cntreg,regdnb\t\tis op=14 & cntreg & op8=0 & op67=0 & op34=0 & regdnb\t{\n\tlocal cnt = cntreg;\n\tlocal result = regdnb;\n\tarithmeticShiftRight(cnt, result, 8);\n\tregdnb = result;\n}\n\n:asr.w cntreg,regdnw\t\tis op=14 & cntreg & op8=0 & op67=1 & op34=0 & regdnw\t{\n\tlocal cnt = cntreg;\n\tlocal result = regdnw;\n\tarithmeticShiftRight(cntreg, result, 16);\n\tregdnw = result;\n}\n\n:asr.l cntreg,regdn\t\tis op=14 & cntreg & op8=0 & op67=2 & op34=0 & regdn\t\t\t{\n\tlocal cnt = cntreg;\n\tlocal result = regdn;\n\tarithmeticShiftRight(cntreg, result, 32);\n\tregdn = result;\n}\n\n:asr eaw\t\t\tis (opbig=0xe0 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tlocal msbBefore = value & 0x8000;\n\tgetbit(CF, value, 0);\n\tvalue = value s>> 1;\n\tresflags(value);\n\tlocal msbAfter = value & 0x8000;\n\tVF = (msbBefore ^ msbAfter) != 0;\n\teaw = value;\n\tXF = CF;\n}\t\n\n:b^cc^\".b\" addr8\t\tis op=6 & cc & addr8\t\t\t\t\t\t{ if (cc) goto addr8; }\n:b^cc^\".w\" addr16\t\tis op=6 & cc & d8base=0; addr16\t\t\t\t\t{ if (cc) goto addr16; }\n:b^cc^\".l\": addr32\t\tis op=6 & cc & d8base=255; addr32\t\t\t\t{ if (cc) goto addr32; }\n\n:bchg.b reg9dn,eab is (op=0 & reg9dn & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eab {\n\tlocal source = eab;\n\tlocal mask:1 = 1 << (reg9dn & 7);\n\tZF = (source & mask) == 0;\n\teab = source ^ mask;\n}\n\n:bchg.b const8,e2b\t\tis opbig=8 & op67=1 & $(MEM_ALTER_ADDR_MODES); const8; e2b\n\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal source = e2b;\n\tlocal mask:1 = 1 << (const8 & 7); # target is a byte in memory, so the bit number in the byte is modulo 8\n\tZF = (source & mask) == 0;\n\te2b = source ^ mask;\n}\n\n:bchg.l reg9dn,regdn\tis op=0 & reg9dn & op68=5 & mode=0 & regdn {\n\tlocal source = regdn;\n\tlocal mask:4 = 1 << (reg9dn & 31);\n\tZF = (source & mask) == 0;\n\tregdn = source ^ mask;\n}\n:bchg.l const8,regdn\tis opbig=8 & op67=1 & mode=0 & regdn; const8 {\n\tlocal source = regdn;\n\tlocal mask:4 = 1 << (const8 & 31);\n\tZF = (source & mask) == 0;\n\tregdn = source ^ mask;\n}\n\n:bclr.b reg9dn,eab\t\tis (op=0 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eab {\n\tlocal source = eab; mask:1 = 1 << (reg9dn & 7); ZF = (source & mask) == 0; eab = source & (~mask);\n}\n:bclr.b const8,e2b\t\tis opbig=8 & op67=2 & savmod1 & regtfan & $(MEM_ALTER_ADDR_MODES); const8; e2b [ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal source = e2b; mask:1 = 1 << (const8 & 7); ZF = (source & mask) == 0; e2b = source & (~mask);\n}\n:bclr.l reg9dn,regdn\tis op=0 & reg9dn & op68=6 & mode=0 & regdn {\n\tlocal source = regdn; mask:4 = 1 << (reg9dn & 31); ZF = (source & mask) == 0; regdn = source & (~mask);\n}\n:bclr.l const8,regdn\tis opbig=8 & op67=2 & mode=0 & regdn; const8 {\n\tlocal source = regdn; mask:4 = 1 << (const8 & 31); ZF = (source & mask) == 0; regdn = source & (~mask);\n}\n\nbfOffWd: {f_off:f_wd} is f_off & f_wd { }\n:bfchg e2l^bfOffWd\t\tis opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\ttmp:4 = e2l;\n\tgetbitfield(tmp, f_off, f_wd);\n\tresbitflags(tmp, f_wd-1);\n\tmask:4 = 0;\n\tbfmask(mask, f_off, f_wd);\n\te2l = (tmp & ~mask) | (~(tmp & mask) & mask);\n}\n\n:bfclr e2l^bfOffWd\t\tis opbig=0xec & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\ttmp:4 = e2l;\n\tgetbitfield(tmp, f_off, f_wd);\n\tresbitflags(tmp, f_wd-1);\n\tmask:4 = 0;\n\tbfmask(mask, f_off, f_wd);\n\te2l = tmp & ~mask;\n}\n\n:bfexts e2l^bfOffWd,f_reg\tis opbig=0xeb & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\ttmp:4 = e2l;\n\ttmp = tmp << f_off;\n\ttmp = tmp s>> (32 - f_wd);\n\tf_reg = tmp; tmp2:4 = e2l;\n\tgetbitfield(tmp2, f_off, f_wd);\n\tresbitflags(tmp2, f_wd-1);\n}\n\n:bfextu e2l^bfOffWd,f_reg\tis opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\ttmp:4 = e2l;\n\tgetbitfield(tmp, f_off, f_wd);\n\tf_reg = tmp;\n\tresbitflags(tmp, f_wd-1);\n}\n\n:bfffo e2l^bfOffWd,f_reg\tis opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l\n\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\t# \"Find First One in Bit Field\" pronounced \"boo-foe\"\n\t# Set the destination f_reg with the position of the first 1 bit in the source e2l.\n\t# f_off and f_wd specify the offset and width of the field of the source to consider.\n\t# If f_off=0 and f_wd=0 then this means the full 32-bit source is examined (implemented here).\n\t#\n\tlocal tmp:4 = e2l;\n\tNF = (tmp & 0x80000000) != 0;\n\tZF = (tmp == 0);\n\tVF = 0;\n\tCF = 0;\n\tf_reg = zext(tmp != 0) * lzcount(tmp);\n}\n\n:bfffo e2l^bfOffWd,f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg ; e2l [ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal tmp:4 = e2l;\n\ttmp = (tmp << f_off) >> (32 - f_wd);\n\ttmp = (tmp << (32 - f_wd));\n\tlocal offw = f_off + f_wd;\n\tNF = (tmp & 0x80000000) != 0;\n\tZF = (tmp == 0);\n\tVF = 0;\n\tCF = 0;\n\tf_reg = (zext(tmp != 0) * lzcount(tmp)) + (zext(tmp == 0) * zext(offw));\n}\n\n\n:bfins f_reg,e2l^bfOffWd\tis opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\tmask:4 = 0;\n\tbitmask(mask, f_wd);\n\ttmp:4 = f_reg & mask;\n\tresbitflags(tmp, f_wd-1);\n\tbfmask(mask,f_off,f_wd);\n\te2l = (e2l & ~mask) | (tmp << (32 - f_off - f_wd));\n}\n\n:bfset e2l^bfOffWd\t\tis opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\ttmp:4 = e2l;\n\tgetbitfield(tmp, f_off, f_wd);\n\tresbitflags(tmp, f_wd-1);\n\tmask:4 = 0;\n\tbfmask(mask,f_off,f_wd);\n\te2l = e2l & ~mask;\n}\n\n:bftst e2l^bfOffWd\t\tis opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlogflags();\n\ttmp:4 = e2l;\n\tgetbitfield(tmp, f_off, f_wd);\n\tresbitflags(tmp, f_wd-1);\n}\n\ndefine pcodeop breakpoint;\n:bkpt \"#\"op02\t\t\tis opbig=0x48 & op67=1 & op5=0 & op34=1 & op02\t\t\t{ breakpoint(); }\n\n:bra.b addr8\t\t\tis opbig=0x60 & addr8\t\t\t\t\t\t{ goto addr8; }\n:bra.w addr16\t\t\tis opbig=0x60 & d8base=0; addr16\t\t\t\t{ goto addr16; }\n:bra.l addr32\t\t\tis opbig=0x60 & d8base=255; addr32\t\t\t\t{ goto addr32; }\n\n:bset.b reg9dn,eab\t\tis (op=0 & reg9dn & op68=7 & $(MEM_ALTER_ADDR_MODES))... & eab\t{\n\tlocal tmp = eab;\n\tmask:1 = 1 << (reg9dn & 7);\n\tZF = (tmp & mask) == 0;\n\teab = tmp | mask;\n}\n:bset.b const8,e2b\t\tis opbig=8 & op67=3 & $(MEM_ALTER_ADDR_MODES); const8; e2b\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal tmp = e2b;\n\tmask:1 = 1 << (const8 & 7);\n\tZF = (tmp & mask) == 0;\n\te2b = tmp | mask;\n}\n:bset.l reg9dn,regdn\tis op=0 & reg9dn & op68=7 & mode=0 & regdn\t{\n\tlocal tmp = regdn;\n\tmask:4 = 1 << (reg9dn & 31);\n\tZF = (tmp & mask) == 0;\n\tregdn = tmp | mask;\n}\n\n:bset.l const8,regdn\tis opbig=8 & op67=3 & mode=0 & regdn; const8\t{\n\tlocal tmp = regdn;\n\tmask:4 = 1 << (const8 & 31);\n\tZF = (tmp & mask) == 0;\n\tregdn = tmp | mask;\n}\n\n:bsr.b addr8\t\t\tis opbig=0x61 & addr8\t\t\t\t\t\t\t{ SP=SP-4; *:4 SP = inst_next; call addr8; }\n:bsr.w addr16\t\t\tis opbig=0x61 & d8base=0; addr16\t\t\t\t{ SP=SP-4; *:4 SP = inst_next; call addr16; }\n:bsr.l addr32\t\t\tis opbig=0x61 & d8base=255; addr32\t\t\t\t{ SP=SP-4; *:4 SP = inst_next; call addr32; }\n\n:btst.b reg9dn,eab\t\tis (op=0 & reg9dn & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab\t{ mask:1 = 1 << (reg9dn & 7); ZF = (eab & mask) == 0; }\n:btst.b const8,e2b\t\tis opbig=8 & op67=0 & regan & $(MEM_ALTER_ADDR_MODES); const8; e2b\t[ savmod2=savmod1; regtsan=regtfan; ] { mask:1 = 1 << (const8 & 7); ZF = (e2b & mask) == 0; }\n:btst.l reg9dn,regdn\tis op=0 & reg9dn & op68=4 & mode=0 & regdn\t\t\t\t\t\t{ mask:4 = 1 << (reg9dn & 31); ZF = (regdn & mask) == 0; }\n:btst.l const8,regdn\tis opbig=8 & op67=0 & mode=0 & regdn; const8\t\t\t\t\t{ mask:4 = 1 << (const8 & 31); ZF = (regdn & mask) == 0; }\n\n@ifdef COLDFIRE\n\n:bitrev regdn is reg315=0x18 & regdn {\n\tlocal dword = regdn;\n\tlocal v = regdn;\n\tv = ((v & 0xffff0000) >> 16) | ((v & 0x0000ffff) << 16);\n\tv = ((v & 0xff00ff00) >> 8) | ((v & 0x00ff00ff) << 8);\n\tv = ((v & 0xf0f0f0f0) >> 4) | ((v & 0x0f0f0f0f) << 4);\n\tv = ((v & 0xcccccccc) >> 2) | ((v & 0x33333333) << 2);\n\tv = ((v & 0xaaaaaaaa) >> 1) | ((v & 0x55555555) << 1);\n\tregdn = v;\n}\n\n:byterev regdn is reg315=0x58 & regdn {\n\tregdn = ((regdn & 0x000000FF) << 24) | ((regdn & 0x0000FF00) << 8) | ((regdn & 0x00FF0000) >> 8) | ((regdn & 0xFF000000) >> 24);\n}\n\n@endif # COLDFIRE\n# TODO: Determine layout of a module descriptor \ndefine pcodeop callm;\n:callm const8,e2l\t\t\tis opbig=6 & op67=3 & $(CTL_ADDR_MODES); const8; e2l \t\t\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tPC = callm(const8, e2l);\n\tcall [PC];\n}\n\n#TODO: should constrain CAS to ignore mode=7 & regan=4 (place CAS2 before CAS to avoid problem)\n:cas2.w regdcw:regdc2w,regduw:regdu2w,(regda):(regda2)\tis op015=0x0cfc; regda & ext_911=0 & regduw & ext_35=0 & regdcw; regda2 & ext2_911=0 & regdu2w & ext2_35=0 & regdc2w {\n\tdc1:4 = zext(regdcw);\n\tdc2:4 = zext(regdc2w);\n\tif(dc1!=regda) goto ;\n\tif(dc2!=regda2) goto ;\n\tregda = zext(regduw);\n\tregda2 = zext(regdu2w);\n\tZF = 1;\n\tNF = 0;\n\tgoto inst_next;\n\t\n\tregdcw = regda(2);\n\tregdc2w = regda2(2);\n\tZF = 0;\n\tNF = 1;\n}\n\n:cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2)\tis op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 {\n\tif(regdc!=regda) goto ;\n\tif(regdc2!=regda2) goto ;\n\tregda = regdu;\n\tregda2 = regdu2;\n\tZF = 1;\n\tNF = 0;\n\tgoto inst_next;\n\t\n\tregdc = regda;\n\tregdc2 = regda2;\n\tZF = 0;\n\tNF = 1;\n}\n\n:cas.b regdcb,regdub,e2b\tis opbig=0x0a & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdub & ext_35=0 & regdcb; e2b\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal tmp = e2b;\n\tif(tmp==regdcb) goto ;\n\tregdcb = tmp;\n\tZF = 0;\n\tNF = 1;\n\tgoto inst_next;\n\t\n\te2b = regdub;\n\tZF = 1;\n\tNF = 0;\n}\n\n:cas.w regdcw,regduw,e2w\tis opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal tmp = e2w;\n\tif(tmp==regdcw) goto ;\n\tregdcw = tmp;\n\tZF = 0;\n\tNF = 1;\n\tgoto inst_next;\n\t\n\te2w = regduw;\n\tZF = 1;\n\tNF = 0;\n}\n\n:cas.l regdc,regdu,e2l\t\tis opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] {\n\tlocal tmp = e2l;\n\tif(tmp==regdc) goto ;\n\tregdc = tmp;\n\tZF = 0;\n\tNF = 1;\n\tgoto inst_next;\n\t\n\te2l = regdu;\n\tZF = 1;\n\tNF = 0;\n}\n\n:chk.w eaw,reg9dnw\t\tis (op=4 & reg9dnw & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eaw {\n\tbuild eaw;\n\tlocal address:4 = zext(eaw);\n\tlocal bound:2 = *:2 address;\n\tlocal signed_bound:4 = sext(bound);\n\tlocal signed_register:4 = sext(reg9dnw);\n\n\tif ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next;\n\tNF = signed_register s< 0;\n\t__m68k_trap(6:1);\n}\n\n:chk.l eal,reg9dn\t\tis (op=4 & reg9dn & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eal {\n\tbuild eal;\n\tlocal address:4 = zext(eal);\n\tlocal bound:4 = *:4 address;\n\tlocal signed_bound:4 = sext(bound);\n\tlocal signed_register:4 = sext(reg9dn);\n\n\tif ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next;\n\tNF = signed_register s< 0;\n\t__m68k_trap(6:1);\n}\n\n:chk2.b e2b,rreg\t\tis opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2b [ savmod2=savmod1; regtsan=regtfan; ] {\n\tbuild e2b;\n\tlocal address:4 = zext(e2b);\n\tlocal lower:1 = *:1 address;\n\tlocal upper:1 = *:1 (address + 1);\n\tlocal signed_lower:4 = sext(lower);\n\tlocal signed_upper:4 = sext(upper);\n\tlocal signed_register:4 = sext(rreg);\n\n\tZF = ((signed_register == signed_lower) || (signed_register == signed_upper));\n\tCF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));\n\tif (!CF) goto inst_next;\n\t__m68k_trap(6:1);\n}\n\n:chk2.w e2w,rreg\t\tis opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2w [ savmod2=savmod1; regtsan=regtfan; ] {\n\tbuild e2w;\n\tlocal address:4 = zext(e2w);\n\tlocal lower:2 = *:2 address;\n\tlocal upper:2 = *:2 (address + 2);\n\tlocal signed_lower:4 = sext(lower);\n\tlocal signed_upper:4 = sext(upper);\n\tlocal signed_register:4 = sext(rreg);\n\n\tZF = ((signed_register == signed_lower) || (signed_register == signed_upper));\n\tCF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));\n\tif (!CF) goto inst_next;\n\t__m68k_trap(6:1);\n}\n\n:chk2.l e2l,rreg\t\tis opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] {\n\tbuild e2l;\n\tlocal address:4 = zext(e2l);\n\tlocal lower:4 = *:4 address;\n\tlocal upper:4 = *:4 (address + 4);\n\tlocal signed_lower:4 = sext(lower);\n\tlocal signed_upper:4 = sext(upper);\n\tlocal signed_register:4 = sext(rreg);\n\n\tZF = ((signed_register == signed_lower) || (signed_register == signed_upper));\n\tCF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));\n\tif (!CF) goto inst_next;\n\t__m68k_trap(6:1);\n}\n\n:cmp2.b e2b,rreg\t\tis opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2b [ savmod2=savmod1; regtsan=regtfan; ] {\n\tbuild e2b;\n\tlocal address:4 = zext(e2b);\n\tlocal lower:1 = *:1 address;\n\tlocal upper:1 = *:1 (address + 1);\n\tlocal signed_lower:4 = sext(lower);\n\tlocal signed_upper:4 = sext(upper);\n\tlocal signed_register:4 = sext(rreg);\n\n\tZF = ((signed_register == signed_lower) || (signed_register == signed_upper));\n\tCF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));\n}\n\n:cmp2.w e2w,rreg\t\tis opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] {\n\tbuild e2w;\n\tlocal address:4 = zext(e2w);\n\tlocal lower:2 = *:2 address;\n\tlocal upper:2 = *:2 (address + 2);\n\tlocal signed_lower:4 = sext(lower);\n\tlocal signed_upper:4 = sext(upper);\n\tlocal signed_register:4 = sext(rreg);\n\n\tZF = ((signed_register == signed_lower) || (signed_register == signed_upper));\n\tCF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));\n}\n\n:cmp2.l e2l,rreg\t\tis opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] {\n\tbuild e2l;\n\tlocal address:4 = zext(e2l);\n\tlocal lower:4 = *:4 address;\n\tlocal upper:4 = *:4 (address + 4);\n\tlocal signed_lower:4 = sext(lower);\n\tlocal signed_upper:4 = sext(upper);\n\tlocal signed_register:4 = sext(rreg);\n\n\tZF = ((signed_register == signed_lower) || (signed_register == signed_upper));\n\tCF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));\n}\n\n@ifdef MC68040\n\ncachetype: \"none\"\t\tis op67=0\t\t\t\t\t\t\t{ export 0:4; }\ncachetype: \"data\"\t\tis op67=1\t\t\t\t\t\t\t{ export 1:4; }\ncachetype: \"instr\"\t\tis op67=2\t\t\t\t\t\t\t{ export 2:4; }\ncachetype: \"both\"\t\tis op67=3\t\t\t\t\t\t\t{ export 3:4; }\n:cinvl cachetype,(regan)\tis opbig=0xf4 & cachetype & op5=0 & op34=1 & regan\t\t{ invalidateCacheLines(cachetype, regan); }\n:cinvp cachetype,(regan)\tis opbig=0xf4 & cachetype & op5=0 & op34=2 & regan\t\t{ invalidateCacheLines(cachetype, regan); }\n:cinva cachetype\t\t\tis opbig=0xf4 & cachetype & op5=0 & op34=3\t\t\t{ invalidateCacheLines(cachetype); }\n\n@endif # MC68040\n\n\n@ifdef MC68040\n\n:cpushl cachetype,(regan)\tis opbig=0xf4 & cachetype & op5=1 & op34=1 & regan\t\t{pushInvalidateCaches(cachetype, regan);}\n:cpushp cachetype,(regan)\tis opbig=0xf4 & cachetype & op5=1 & op34=2 & regan\t\t{pushInvalidateCaches(cachetype, regan);}\n:cpusha cachetype\t\t\tis opbig=0xf4 & cachetype & op5=1 & op34=3\t\t\t{pushInvalidateCaches(cachetype);}\n\n@endif # MC68040\n\n:clr.b eab\t\t\tis (opbig=0x42 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab\t\t{ eab = 0; NF=0; ZF=1; VF=0; CF=0; }\n:clr.w eaw\t\t\tis (opbig=0x42 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t{ eaw = 0; NF=0; ZF=1; VF=0; CF=0; }\n:clr.l eal\t\t\tis (opbig=0x42 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal\t\t{ eal=0; NF=0; ZF=1; VF=0; CF=0; }\n\n:cmp.b eab,reg9dnb\t\tis (op=11 & reg9dnb & op68=0)... & eab\t\t\t\t{ o2:1=eab; subflags(reg9dnb,o2); local tmp =reg9dnb-o2; resflags(tmp); }\n:cmp.w eaw,reg9dnw\t\tis (op=11 & reg9dnw & op68=1)... & eaw\t\t\t\t{ o2:2=eaw; subflags(reg9dnw,o2); local tmp =reg9dnw-o2; resflags(tmp); }\n:cmp.l eal,reg9dn\t\tis (op=11 & reg9dn & op68=2)... & eal\t\t\t\t{ o2:4=eal; subflags(reg9dn,o2); local tmp =reg9dn-o2; resflags(tmp); }\n\n:cmpa.w eaw,reg9an\t\tis (op=11 & reg9an & op68=3)... & eaw\t\t\t\t{ tmp1:4 = sext(eaw); subflags(reg9an,tmp1); local tmp =reg9an-tmp1; resflags(tmp); }\n:cmpa.l eal,reg9an\t\tis (op=11 & reg9an & op68=7)... & eal\t\t\t\t{ o2:4=eal; subflags(reg9an,o2); local tmp =reg9an-o2; resflags(tmp); }\n\n\n:cmpi.b const8,e2b\t\tis opbig=12 & op67=0 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const8; e2b\t\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ o2:1=e2b; subflags(o2,const8); local tmp =o2-const8; resflags(tmp); }\n:cmpi.w const16,e2w\t\tis opbig=12 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const16; e2w\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ o2:2=e2w; subflags(o2,const16); local tmp =o2-const16; resflags(tmp);}\n:cmpi.l const32,e2l\t\tis opbig=12 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const32; e2l\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ o2:4=e2l; subflags(o2,const32); local tmp =o2-const32; resflags(tmp);}\n\n:cmpm.b regPlus,reg9Plus\tis op=11 & reg9Plus & op8=1 & op67=0 & op5=0 & op34=1 & regPlus\t{ local tmp1=*:1 regPlus; regPlus=regPlus+1; local tmp2=*:1 reg9Plus; reg9Plus=reg9Plus+1;\n\t\t\t\t\t\t\t\tsubflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }\n:cmpm.w regPlus,reg9Plus\tis op=11 & reg9Plus & op8=1 & op67=1 & op5=0 & op34=1 & regPlus\t{ local tmp1=*:2 regPlus; regPlus=regPlus+2; local tmp2=*:2 reg9Plus; reg9Plus=reg9Plus+2;\n\t\t\t\t\t\t\t\tsubflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }\n:cmpm.l regPlus,reg9Plus\tis op=11 & reg9Plus & op8=1 & op67=2 & op5=0 & op34=1 & regPlus { local tmp1=*:4 regPlus; regPlus=regPlus+4; local tmp2=*:4 reg9Plus; reg9Plus=reg9Plus+4;\n\t\t\t\t\t\t\t\t subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }\n# cpBcc # need to know specific copressors use copcc1\n# cpDBcc # use copcc2\n# cpGEN\n# cpScc\t # use copcc2\n# cpTRAPcc # use copcc2\n\n:db^cc regdnw,addr16\t\tis op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16\n{\n\tif (cc) goto inst_next;\n\tregdnw=regdnw-1;\n\tif (regdnw!=-1) goto addr16;\n}\n\n:divs.w eaw,reg9dn\t\tis (op=8 & reg9dn & op68=7)... & eaw\t{\n\tlocal denom = sext(eaw);\n\tlocal divis = reg9dn;\n\tlocal div = divis s/ denom;\n\tlocal rem = divis s% denom;\n\tCF=0;\n\tresflags(div);\n\treg9dn = (rem << 16) | (div & 0xffff);\n}\n\n:divu.w eaw,reg9dn\t\tis (op=8 & reg9dn & op68=3)... & eaw\n{\n\tlocal denom = zext(eaw);\n\tlocal divis = reg9dn;\n\tlocal div = divis / denom;\n\tlocal rem = divis % denom;\n\tCF=0;\n\tresflags(div);\n\treg9dn = (rem << 16) | (div & 0xffff);\n\t}\n\n#remyes: \"s\"\t\t\tis regdq & (regdr=regdq) & divsgn=1\t\t\t\t{ }\nremyes: \"sl\"\t\t\tis divsgn=1\t\t\t\t\t\t\t{ }\n#remyes: \"u\"\t\t\tis regdq & (regdr=regdq) & divsgn=0\t\t\t\t{ }\nremyes: \"ul\"\t\t\tis divsgn=0\t\t\t\t\t\t\t{ }\n\n#subdiv: regdq\t\t\tis regdq & regdr=regdq & divsz=0 & divsgn=0\t\t\t{ regdq = regdq/glbdenom; export regdq; }\n\n# NB- Need to be very careful with div to not clobber when regdr and regdq refer to the same reg.\n# When this happens it seems the destination reg should get the quotient, not the remainder.\n#\nsubdiv: regdr:regdq\t\tis regdq & regdr & divsz=0 & divsgn=0 {\n\tlocal divis = regdq;\n\tlocal denom = glbdenom;\n\tlocal rem = divis % denom;\n\tlocal quot = divis / denom;\n\tregdr = rem;\n\tregdq = quot;\n\texport regdq;\n}\n\nsubdiv: regdr:regdq\t\tis regdq & regdr & divsz=1 & divsgn=0 {\n\tdivi:8 = (zext(regdr) << 32) | zext(regdq);\n\tdenom:8 = zext(glbdenom);\n\tlocal quot = divi / denom;\n\tlocal rem = divi % denom;\n\tregdr = rem:4;\n\tregdq = quot:4;\n\texport regdq;\n}\n\n#subdiv: regdq\t\t\tis regdq & regdr=regdq & divsz=0 & divsgn=1\t\t\t{ regdq = regdq s/ glbdenom; export regdq; }\n\nsubdiv: regdr:regdq\t\tis regdq & regdr & divsz=0 & divsgn=1 {\n\tlocal divis = regdq;\n\tlocal denom = glbdenom;\n\tlocal rem = divis s% denom;\n\tlocal quot = divis s/ denom;\n\tregdr = rem;\n\tregdq = quot;\n\texport regdq;\n}\n\nsubdiv: regdr:regdq\t\tis regdq & regdr & divsz=1 & divsgn=1 {\n\tdivi:8 = (sext(regdr)<<32)|sext(regdq);\n\tdenom:8=sext(glbdenom);\n\tlocal quot=divi s/ denom;\n\tlocal rem=divi s% denom;\n\tregdr=rem:4;\n\tregdq=quot:4;\n\texport regdq;\n}\n\n# when divsgn=0\n# divu.l is regdq / e2l -> regdq\n# divu.l (when divsz = 1) is regdr concat regdq / el2 - > regdr and regdq\n# divul.l (when divsz = 0) is regdq / el2 -> regdr and regdq\n#\n:div^remyes^\".l\" e2l,subdiv\tis opbig=0x4c & op67=1 & $(DAT_ALTER_ADDR_MODES); subdiv & remyes; e2l [ savmod2=savmod1; regtsan=regtfan;] { glbdenom=e2l; build subdiv; CF=0; resflags(subdiv);}\n\n:eor.b reg9dnb,eab\t\tis (op=11 & reg9dnb & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eab\t\t\t{ eor(reg9dnb, eab); }\n:eor.w reg9dnw,eaw\t\tis (op=11 & reg9dnw & op68=5 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t{ eor(reg9dnw, eaw); }\n:eor.l reg9dn,eal\t\tis (op=11 & reg9dn & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eal\t\t\t\t{ eor(reg9dn, eal); }\n\n:eori.b const8,e2b\t\tis opbig=10 & op67=0 & $(DAT_ALTER_ADDR_MODES); const8; e2b\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { eor(const8, e2b); }\n:eori.w const16,e2w\t\tis opbig=10 & op67=1 & $(DAT_ALTER_ADDR_MODES); const16; e2w\t\t[ savmod2=savmod1; regtsan=regtfan; ] { eor(const16, e2w); }\n:eori.l const32,e2l\t\tis opbig=10 & op67=2 & $(DAT_ALTER_ADDR_MODES); const32; e2l\t\t[ savmod2=savmod1; regtsan=regtfan; ] { eor(const32, e2l); }\n\n:eori const8,\"CCR\"\t\tis d16=0xa3c; const8\t\t\t\t\t\t{ packflags(SR); SR = SR ^ zext(const8); unpackflags(SR); }\n:eori const16,SR\t\tis opbig=0x0a & d8base=0x7c; const16 & SR\t{ packflags(SR); SR = SR ^ const16; unpackflags(SR); }\n\n\n:exg reg9dn,regdn\t\tis op=12 & reg9dn & op8=1 & op37=8 & regdn\t\t\t{ local tmp = reg9dn; reg9dn=regdn; regdn=tmp; }\n:exg reg9an,regan\t\tis op=12 & reg9an & op8=1 & op37=9 & regan\t\t\t{ local tmp = reg9an; reg9an=regan; regan=tmp; }\n:exg reg9dn,regan\t\tis op=12 & reg9dn & op8=1 & op37=17 & regan\t\t\t{ local tmp = reg9dn; reg9dn=regan; regan=tmp; }\n\n:ext.w regdnw\t\t\tis op=4 & reg9dn=4 & op68=2 & op35=0 & regdnw\t\t{ local tmp = regdnw:1; regdnw = sext(tmp); resflags(regdnw); logflags(); }\n:ext.l regdn\t\t\tis op=4 & reg9dn=4 & op68=3 & op35=0 & regdn\t\t{ local tmp = regdn:2; regdn = sext(tmp); resflags(regdn); logflags(); }\n:extb.l regdn\t\t\tis op=4 & reg9dn=4 & op68=7 & op35=0 & regdn\t\t{ local tmp = regdn:1; regdn = sext(tmp); resflags(regdn); logflags(); }\n\n@ifdef COLDFIRE\n:halt\t\t\t\tis d16=0x4ac8\t\tunimpl\n@endif\n\n:illegal\t\t\tis d16=0x4afc\t\tunimpl\n\n# jump addresses derived from effective address calculation\naddrpc16: reloc\t\t\tis d16 [ reloc = inst_start+2+d16; ]\t{ export *[ram]:4 reloc; }\naddrd16: d16\".w\"\t\tis d16\t\t\t\t\t\t\t\t\t{ export *[ram]:4 d16; }\naddrd32: d32\".l\"\t\tis d32\t\t\t\t\t\t\t\t\t{ export *[ram]:4 d32; }\naddrReg: (regan)\t\tis regan\t\t\t\t\t\t\t\t{ export regan; }\naddrRegD16: (d16,regan)\tis regan; d16\t\t\t\t\t\t\t{local tmp = regan + d16; export *[ram]:4 tmp; }\naddrextw: (extw)\t\tis extw\t\t\t\t\t\t\t\t\t{ export extw; }\n\n:jmp addrReg \t\t\tis opbig=0x4e & op67=3 & mode=2 & addrReg\t\t\t\t{ goto [addrReg]; }\n:jmp addrRegD16\t\t\tis (opbig=0x4e & op67=3 & mode=5) ... & addrRegD16\t\t{ goto [addrRegD16]; }\n:jmp addrextw\t\t\tis opbig=0x4e & op67=3 & mode=6 & regan; addrextw\t[ pcmode=0; regtfan=regan; ] { goto [addrextw]; }\n:jmp addrpc16\t\t\tis opbig=0x4e & op67=3 & mode=7 & regan=2; addrpc16\t\t{ goto addrpc16; }\n:jmp addrextw\t\t\tis opbig=0x4e & op67=3 & mode=7 & regan=3; addrextw\t[ pcmode=1; ] { goto [addrextw]; }\n:jmp addrd16\t\t\tis opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16\t\t{ goto addrd16; }\n:jmp addrd32\t\t\tis opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32\t\t{ goto addrd32; }\n\n:jsr addrReg \t\t\tis opbig=0x4e & op67=2 & mode=2 & addrReg\t\t\t\t{ SP=SP-4; *:4 SP = inst_next; call [addrReg]; }\n:jsr addrRegD16\t\t\tis (opbig=0x4e & op67=2 & mode=5) ... & addrRegD16\t\t{ SP=SP-4; *:4 SP = inst_next; call [addrRegD16]; }\n:jsr addrextw\t\t\tis opbig=0x4e & op67=2 & mode=6 & regan; addrextw\t[ pcmode=0; regtfan=regan;] { build addrextw; SP=SP-4; *:4 SP=inst_next; call [addrextw];}\n:jsr addrpc16\t\t\tis opbig=0x4e & op67=2 & mode=7 & regan=2; addrpc16\t\t{ SP=SP-4; *:4 SP = inst_next; call addrpc16; }\n:jsr addrextw\t\t\tis opbig=0x4e & op67=2 & mode=7 & regan=3; addrextw\t[ pcmode=1; ] { build addrextw; SP=SP-4; *:4 SP = inst_next; call [addrextw]; }\n:jsr addrd16\t\t\tis opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16\t\t{ SP=SP-4; *:4 SP = inst_next; call addrd16; }\n:jsr addrd32\t\t\tis opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32\t\t{ SP=SP-4; *:4 SP = inst_next; call addrd32; }\n\n:lea eaptr,reg9an\t\tis (op=4 & reg9an & op68=7)... & eaptr\t\t\t\t{ reg9an = eaptr; }\n\n:link.w regan,d16\t\tis opbig=0x4e & op37=10 & regan; d16\t\t\t\t{ SP=SP-4; *:4 SP = regan; regan=SP; SP = SP + d16; }\n:link.l regan,d32\t\tis opbig=0x48 & op37=1 & regan; d32\t\t\t\t{ SP=SP-4; *:4 SP = regan; regan=SP; SP = SP + d32; }\n\nmacro shiftCXFlags(cntreg) {\n\t\tCF = CF * (cntreg != 0);\n\t\tXF = CF * (cntreg != 0) + XF * (cntreg == 0);\n}\n\n:lsl.b cntreg,regdnb\tis op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb\t\t{ logicalShiftLeft(cntreg, regdnb, 8); }\n:lsl.w cntreg,regdnw\tis op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw\t\t{ logicalShiftLeft(cntreg, regdnw, 16); }\n:lsl.l cntreg,regdn\t\tis op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn\t\t{ logicalShiftLeft(cntreg, regdn, 32); }\n:lsl eaw\t\t\t\tis (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tgetbit(CF, value, 15);\n\tvalue = value << 1;\n\tresflags(value);\n\teaw = value;\n\tVF = 0;\n\tXF = CF;\n}\n\n:lsr.b cntreg,regdnb\t\tis op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb\t\t{ logicalShiftRight(cntreg, regdnb, 8); }\n:lsr.w cntreg,regdnw\t\tis op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw\t\t{ logicalShiftRight(cntreg, regdnw, 16); }\n:lsr.l cntreg,regdn\t\t\tis op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn\t\t{ logicalShiftRight(cntreg, regdn, 32); }\n:lsr eaw\t\t\t\t\tis (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tgetbit(CF, value, 0);\n\tvalue = value >> 1;\n\tresflags(value);\n\teaw = value;\n\tVF = 0;\n\tXF = CF;\n}\n\n:move.b eab,e2b\t\t\tis (op=1 & $(DAT_ALTER_ADDR_MODES2))... & eab ; e2b\t{ build eab; local tmp = eab; build e2b; e2b = tmp; resflags(tmp); logflags(); }\n:move.w eaw,e2w\t\t\tis (op=3 & $(DAT_ALTER_ADDR_MODES2))... & eaw ; e2w\t{ build eaw; local tmp = eaw; build e2w; e2w = tmp; resflags(tmp); logflags(); }\n:move.l eal,e2l\t\t\tis (op=2 & $(DAT_ALTER_ADDR_MODES2))... & eal ; e2l\t{ build eal; local tmp = eal; build e2l; e2l = tmp; resflags(tmp); logflags(); }\n\n:move \"CCR\",eaw\t\t\tis (opbig=0x42 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t\t{ packflags(SR); eaw = SR; }\n:move eaw,\"CCR\"\t\t\tis (opbig=0x44 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t\t{ unpackflags(eaw); }\n:move SR,eaw\t\t\tis SR; (opbig=0x40 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t\t{ packflags(SR); eaw = SR; }\n:move eaw,SR\t\t\tis SR; (opbig=0x46 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t\t{ SR = eaw; unpackflags(SR); }\n:move USP,regan\t\t\tis opbig=0x4e & op37=13 & regan & USP\t\t\t{ regan = USP; }\n:move regan,USP\t\t\tis opbig=0x4e & op37=12 & regan & USP\t\t\t{ USP = regan; }\n \n:movea.w eaw,reg9an\t\tis (op=3 & reg9an & mode2=1)... & eaw\t\t\t\t{ reg9an = sext(eaw); }\n:movea.l eal,reg9an\t\tis (op=2 & reg9an & mode2=1)... & eal\t\t\t\t{ reg9an = eal; }\n\n:movec ctlreg,rreg\t\tis d16=0x4e7a; rreg & ctlreg\t\t\t\t\t{ rreg = ctlreg; }\n:movec rreg,ctlreg\t\tis d16=0x4e7b; rreg & ctlreg\t\t\t\t\t{ ctlreg = rreg; }\n\n@ifdef MC68040\n\nmacro move16(src, dst)\n{\n\t*:4 dst= *:4 src;\n\tsrc=src+4;\n\tdst=dst+4;\n\t*:4 dst= *:4 src;\n\tsrc=src+4;\n\tdst=dst+4;\n\t *:4 dst= *:4 src;\n\t src=src+4;\n\t dst=dst+4;\n\t *:4 dst= *:4 src;\n}\n\n:move16 regPlus,regxPlus\tis opbig=0xf6 & op37=4 & regan & regPlus; regxan & regxPlus & da=1 {\n\tlocal src=regan&0xfffffff0;\n\tlocal dst=regxan&0xfffffff0;\n\tregan=regan+16;\n\tregxan=regxan+16;\n\tmove16(src, dst);\n}\n:move16 regPlus,d32l\tis opbig=0xf6 & op37=0 & regan & regPlus; d32 & d32l {\n\tlocal src=regan&0xfffffff0;\n\tlocal dst:4=d32&0xfffffff0;\n\tregan=regan+16;\n\tmove16(src, dst);\n}\n\n:move16 d32l,regPlus\tis opbig=0xf6 & op37=1 & regan & regPlus; d32 & d32l {\n\tlocal dst=regan&0xfffffff0;\n\tlocal src:4=d32&0xfffffff0;\n\tregan=regan+16;\n\tmove16(src, dst);\n}\n:move16 regParen,d32l\tis opbig=0xf6 & op37=2 & regan & regParen; d32 & d32l {\n\tlocal src=regan&0xfffffff0;\n\tlocal dst:4=d32&0xfffffff0;\n\tmove16(src, dst);\n}\n:move16 d32l,regParen\tis opbig=0xf6 & op37=3 & regan & regParen; d32 & d32l {\n\tlocal dst=regan&0xfffffff0;\n\tlocal src:4=d32&0xfffffff0;\n\tmove16(src, dst);\n}\n@endif # MC68040\n\n@ifdef COLDFIRE\n\n:mvs.b: eab, reg9dn\t\tis (op=0x7 & op68=4 & reg9dn )... & eab\t\t{ reg9dn = sext(eab); }\n:mvs.w: eaw, reg9dn\t\tis (op=0x7 & op68=5 & reg9dn )... & eaw\t\t{ reg9dn = sext(eaw); }\n:mvz.b: eab, reg9dn\t\tis (op=0x7 & op68=6 & reg9dn )... & eab\t\t{ reg9dn = zext(eab); }\n:mvz.w: eaw, reg9dn\t\tis (op=0x7 & op68=7 & reg9dn )... & eaw\t\t{ reg9dn = zext(eaw); }\n\n:mov3q \"#\"^d911, eal\tis (op=0xa & op68=5 & d911 ) ... & eal\t\t{ eal = d911; }\n\n:sats.l regdn\t\t\tis opbig=0x4c & op37=0x10 & regdn\t{ if (VF == 0) goto inst_next; regdn = (zext(regdn == 0 ) * 0x80000000) + (zext(regdn != 0) * 0x7fffffff); VF=0; CF=0; }\n\nskip_addr: skipAddr\t\tis op02=2 [skipAddr = inst_next + 2;] { export *[ram]:4 skipAddr; }\nskip_addr: skipAddr\t\tis op02=3 [skipAddr = inst_next + 4;] { export *[ram]:4 skipAddr; }\n\n# TPF.w/l is occassionally used as a branch over a valid instruction.\n:tpf\t\t\tis opbig=0x51 & op37=0x1f & op02=4\t{ } # nop\n:tpf.w\t\t\tis opbig=0x51 & op37=0x1f & op02=2 & skip_addr\t{ goto skip_addr; } # nop + 1 word\n:tpf.l\t\t\tis opbig=0x51 & op37=0x1f & op02=3 & skip_addr\t{ goto skip_addr; } # nop + 2 word\n@endif # COLDFIRE\n\n# Tables for register lists, for the movem instruction\n # Register to mememory, forward direction, via word\nr2mfwf: D0w\t\t\t\tis D0w & mvm0=1\t\t\t\t{ *movemptr = D0w; movemptr = movemptr + 2; }\nr2mfwf:\t\t\t\t\tis mvm0=0\t\t\t\t\t{ }\nr2mfwe: r2mfwf\" \"D1w\tis D1w & mvm1=1 & r2mfwf\t{ *movemptr = D1w; movemptr = movemptr + 2; }\nr2mfwe: r2mfwf\t\t\tis mvm1=0 & r2mfwf\t\t\t{ }\nr2mfwd: r2mfwe\" \"D2w\tis D2w & mvm2=1 & r2mfwe\t{ *movemptr = D2w; movemptr = movemptr + 2; }\nr2mfwd: r2mfwe\t\t\tis mvm2=0 & r2mfwe\t\t\t{ }\nr2mfwc: r2mfwd\" \"D3w\tis D3w & mvm3=1 & r2mfwd\t{ *movemptr = D3w; movemptr = movemptr + 2; }\nr2mfwc: r2mfwd\t\t\tis mvm3=0 & r2mfwd\t\t\t{ }\nr2mfwb: r2mfwc\" \"D4w\tis D4w & mvm4=1 & r2mfwc\t{ *movemptr = D4w; movemptr = movemptr + 2; }\nr2mfwb: r2mfwc\t\t\tis mvm4=0 & r2mfwc\t\t\t{ }\nr2mfwa: r2mfwb\" \"D5w\tis D5w & mvm5=1 & r2mfwb\t{ *movemptr = D5w; movemptr = movemptr + 2; }\nr2mfwa: r2mfwb\t\t\tis mvm5=0 & r2mfwb\t\t\t{ }\nr2mfw9: r2mfwa\" \"D6w\tis D6w & mvm6=1 & r2mfwa\t{ *movemptr = D6w; movemptr = movemptr + 2; }\nr2mfw9: r2mfwa\t\t\tis mvm6=0 & r2mfwa\t\t\t{ }\nr2mfw8: r2mfw9\" \"D7w\tis D7w & mvm7=1 & r2mfw9\t{ *movemptr = D7w; movemptr = movemptr + 2; }\nr2mfw8: r2mfw9\t\t\tis mvm7=0 & r2mfw9\t\t\t{ }\nr2mfw7: r2mfw8\" \"A0w\tis A0w & mvm8=1\t& r2mfw8\t{ *movemptr = A0w; movemptr = movemptr + 2; }\nr2mfw7:\tr2mfw8\t\t\tis mvm8=0 & r2mfw8\t\t\t{ }\nr2mfw6: r2mfw7\" \"A1w\tis A1w & mvm9=1 & r2mfw7\t{ *movemptr = A1w; movemptr = movemptr + 2; }\nr2mfw6: r2mfw7\t\t\tis mvm9=0 & r2mfw7\t\t\t{ }\nr2mfw5: r2mfw6\" \"A2w\tis A2w & mvm10=1 & r2mfw6\t{ *movemptr = A2w; movemptr = movemptr + 2; }\nr2mfw5: r2mfw6\t\t\tis mvm10=0 & r2mfw6\t\t\t{ }\nr2mfw4: r2mfw5\" \"A3w\tis A3w & mvm11=1 & r2mfw5\t{ *movemptr = A3w; movemptr = movemptr + 2; }\nr2mfw4: r2mfw5\t\t\tis mvm11=0 & r2mfw5\t\t\t{ }\nr2mfw3: r2mfw4\" \"A4w\tis A4w & mvm12=1 & r2mfw4\t{ *movemptr = A4w; movemptr = movemptr + 2; }\nr2mfw3: r2mfw4\t\t\tis mvm12=0 & r2mfw4\t\t\t{ }\nr2mfw2: r2mfw3\" \"A5w\tis A5w & mvm13=1 & r2mfw3\t{ *movemptr = A5w; movemptr = movemptr + 2; }\nr2mfw2: r2mfw3\t\t\tis mvm13=0 & r2mfw3\t\t\t{ }\nr2mfw1: r2mfw2\" \"A6w\tis A6w & mvm14=1 & r2mfw2\t{ *movemptr = A6w; movemptr = movemptr + 2; }\nr2mfw1: r2mfw2\t\t\tis mvm14=0 & r2mfw2\t\t\t{ }\nr2mfw0: { r2mfw1\" \"A7w}\tis A7w & mvm15=1 & r2mfw1\t{ *movemptr = A7w; movemptr = movemptr + 2; }\nr2mfw0: { r2mfw1}\t\tis mvm15=0 & r2mfw1\t\t\t{ }\n\n\n # Register to memory, forward direction, via long\nr2mflf: D0\t\t\t\tis D0 & mvm0=1\t\t\t\t{ *movemptr = D0; movemptr = movemptr + 4; }\nr2mflf:\t\t\t\t\tis mvm0=0\t\t\t\t\t{ }\nr2mfle: r2mflf\" \"D1\t\tis D1 & mvm1=1 & r2mflf\t\t{ *movemptr = D1; movemptr = movemptr + 4; }\nr2mfle: r2mflf\t\t\tis mvm1=0 & r2mflf\t\t\t{ }\nr2mfld: r2mfle\" \"D2\t\tis D2 & mvm2=1 & r2mfle\t\t{ *movemptr = D2; movemptr = movemptr + 4; }\nr2mfld: r2mfle\t\t\tis mvm2=0 & r2mfle\t\t\t{ }\nr2mflc: r2mfld\" \"D3\t\tis D3 & mvm3=1 & r2mfld\t\t{ *movemptr = D3; movemptr = movemptr + 4; }\nr2mflc: r2mfld\t\t\tis mvm3=0 & r2mfld\t\t\t{ }\nr2mflb: r2mflc\" \"D4\t\tis D4 & mvm4=1 & r2mflc\t\t{ *movemptr = D4; movemptr = movemptr + 4; }\nr2mflb: r2mflc\t\t\tis mvm4=0 & r2mflc\t\t\t{ }\nr2mfla: r2mflb\" \"D5\t\tis D5 & mvm5=1 & r2mflb\t\t{ *movemptr = D5; movemptr = movemptr + 4; }\nr2mfla: r2mflb\t\t\tis mvm5=0 & r2mflb\t\t\t{ }\nr2mfl9: r2mfla\" \"D6\t\tis D6 & mvm6=1 & r2mfla\t\t{ *movemptr = D6; movemptr = movemptr + 4; }\nr2mfl9: r2mfla\t\t\tis mvm6=0 & r2mfla\t\t\t{ }\nr2mfl8: r2mfl9\" \"D7\t\tis D7 & mvm7=1 & r2mfl9\t\t{ *movemptr = D7; movemptr = movemptr + 4; }\nr2mfl8: r2mfl9\t\t\tis mvm7=0 & r2mfl9\t\t\t{ }\nr2mfl7: r2mfl8\" \"A0\t\tis A0 & mvm8=1\t& r2mfl8\t{ *movemptr = A0; movemptr = movemptr + 4; }\nr2mfl7:\tr2mfl8\t\t\tis mvm8=0 & r2mfl8\t\t\t{ }\nr2mfl6: r2mfl7\" \"A1\t\tis A1 & mvm9=1 & r2mfl7\t\t{ *movemptr = A1; movemptr = movemptr + 4; }\nr2mfl6: r2mfl7\t\t\tis mvm9=0 & r2mfl7\t\t\t{ }\nr2mfl5: r2mfl6\" \"A2\t\tis A2 & mvm10=1 & r2mfl6\t{ *movemptr = A2; movemptr = movemptr + 4; }\nr2mfl5: r2mfl6\t\t\tis mvm10=0 & r2mfl6\t\t\t{ }\nr2mfl4: r2mfl5\" \"A3\t\tis A3 & mvm11=1 & r2mfl5\t{ *movemptr = A3; movemptr = movemptr + 4; }\nr2mfl4: r2mfl5\t\t\tis mvm11=0 & r2mfl5\t\t\t{ }\nr2mfl3: r2mfl4\" \"A4\t\tis A4 & mvm12=1 & r2mfl4\t{ *movemptr = A4; movemptr = movemptr + 4; }\nr2mfl3: r2mfl4\t\t\tis mvm12=0 & r2mfl4\t\t\t{ }\nr2mfl2: r2mfl3\" \"A5\t\tis A5 & mvm13=1 & r2mfl3\t{ *movemptr = A5; movemptr = movemptr + 4; }\nr2mfl2: r2mfl3\t\t\tis mvm13=0 & r2mfl3\t\t\t{ }\nr2mfl1: r2mfl2\" \"A6\t\tis A6 & mvm14=1 & r2mfl2\t{ *movemptr = A6; movemptr = movemptr + 4; }\nr2mfl1: r2mfl2\t\t\tis mvm14=0 & r2mfl2\t\t\t{ }\nr2mfl0: { r2mfl1\" \"SP}\tis SP & mvm15=1 & r2mfl1\t{ *movemptr = SP; movemptr = movemptr + 4; }\nr2mfl0: { r2mfl1}\t\tis mvm15=0 & r2mfl1\t\t\t{ }\n\n\n # Register to memory, backward direction, via word\nr2mbwf: A7w\t\t\t\tis A7w & mvm0=1\t\t\t\t{ movemptr = movemptr - 4; *movemptr = A7w; }\nr2mbwf:\t\t\t\t\tis mvm0=0\t\t\t\t\t{ }\nr2mbwe: r2mbwf\" \"A6w\tis A6w & mvm1=1 & r2mbwf\t{ movemptr = movemptr - 4; *movemptr = A6w; }\nr2mbwe: r2mbwf\t\t\tis mvm1=0 & r2mbwf\t\t\t{ }\nr2mbwd: r2mbwe\" \"A5w\tis A5w & mvm2=1 & r2mbwe\t{ movemptr = movemptr - 4; *movemptr = A5w; }\nr2mbwd: r2mbwe\t\t\tis mvm2=0 & r2mbwe\t\t\t{ }\nr2mbwc: r2mbwd\" \"A4w\tis A4w & mvm3=1 & r2mbwd\t{ movemptr = movemptr - 4; *movemptr = A4w; }\nr2mbwc: r2mbwd\t\t\tis mvm3=0 & r2mbwd\t\t\t{ }\nr2mbwb: r2mbwc\" \"A3w\tis A3w & mvm4=1 & r2mbwc\t{ movemptr = movemptr - 4; *movemptr = A3w; }\nr2mbwb: r2mbwc\t\t\tis mvm4=0 & r2mbwc\t\t\t{ }\nr2mbwa: r2mbwb\" \"A2w\tis A2w & mvm5=1 & r2mbwb\t{ movemptr = movemptr - 4; *movemptr = A2w; }\nr2mbwa: r2mbwb\t\t\tis mvm5=0 & r2mbwb\t\t\t{ }\nr2mbw9: r2mbwa\" \"A1w\tis A1w & mvm6=1 & r2mbwa\t{ movemptr = movemptr - 4; *movemptr = A1w; }\nr2mbw9: r2mbwa\t\t\tis mvm6=0 & r2mbwa\t\t\t{ }\nr2mbw8: r2mbw9\" \"A0w\tis A0w & mvm7=1 & r2mbw9\t{ movemptr = movemptr - 4; *movemptr = A0w; }\nr2mbw8: r2mbw9\t\t\tis mvm7=0 & r2mbw9\t\t\t{ }\nr2mbw7: r2mbw8\" \"D7w\tis D7w & mvm8=1\t& r2mbw8\t{ movemptr = movemptr - 4; *movemptr = D7w; }\nr2mbw7:\tr2mbw8\t\t\tis mvm8=0 & r2mbw8\t\t\t{ }\nr2mbw6: r2mbw7\" \"D6w\tis D6w & mvm9=1 & r2mbw7\t{ movemptr = movemptr - 4; *movemptr = D6w; }\nr2mbw6: r2mbw7\t\t\tis mvm9=0 & r2mbw7\t\t\t{ }\nr2mbw5: r2mbw6\" \"D5w\tis D5w & mvm10=1 & r2mbw6\t{ movemptr = movemptr - 4; *movemptr = D5w; }\nr2mbw5: r2mbw6\t\t\tis mvm10=0 & r2mbw6\t\t\t{ }\nr2mbw4: r2mbw5\" \"D4w\tis D4w & mvm11=1 & r2mbw5\t{ movemptr = movemptr - 4; *movemptr = D4w; }\nr2mbw4: r2mbw5\t\t\tis mvm11=0 & r2mbw5\t\t\t{ }\nr2mbw3: r2mbw4\" \"D3w\tis D3w & mvm12=1 & r2mbw4\t{ movemptr = movemptr - 4; *movemptr = D3w; }\nr2mbw3: r2mbw4\t\t\tis mvm12=0 & r2mbw4\t\t\t{ }\nr2mbw2: r2mbw3\" \"D2w\tis D2w & mvm13=1 & r2mbw3\t{ movemptr = movemptr - 4; *movemptr = D2w; }\nr2mbw2: r2mbw3\t\t\tis mvm13=0 & r2mbw3\t\t\t{ }\nr2mbw1: r2mbw2\" \"D1w\tis D1w & mvm14=1 & r2mbw2\t{ movemptr = movemptr - 4; *movemptr = D1w; }\nr2mbw1: r2mbw2\t\t\tis mvm14=0 & r2mbw2\t\t\t{ }\nr2mbw0: { r2mbw1\" \"D0w}\tis D0w & mvm15=1 & r2mbw1\t{ movemptr = movemptr - 4; *movemptr = D0w; }\nr2mbw0: { r2mbw1}\t\tis mvm15=0 & r2mbw1\t\t\t{ }\n\n\n # Register to memory, backward direction, via long\nr2mblf: SP\t\t\t\tis SP & mvm0=1\t\t\t\t{ movemptr = movemptr - 4; *movemptr = SP; }\nr2mblf:\t\t\t\t\tis mvm0=0\t\t\t\t\t{ }\nr2mble: r2mblf\" \"A6\t\tis A6 & mvm1=1 & r2mblf\t\t{ movemptr = movemptr - 4; *movemptr = A6; }\nr2mble: r2mblf\t\t\tis mvm1=0 & r2mblf\t\t\t{ }\nr2mbld: r2mble\" \"A5\t\tis A5 & mvm2=1 & r2mble\t\t{ movemptr = movemptr - 4; *movemptr = A5; }\nr2mbld: r2mble\t\t\tis mvm2=0 & r2mble\t\t\t{ }\nr2mblc: r2mbld\" \"A4\t\tis A4 & mvm3=1 & r2mbld\t\t{ movemptr = movemptr - 4; *movemptr = A4; }\nr2mblc: r2mbld\t\t\tis mvm3=0 & r2mbld\t\t\t{ }\nr2mblb: r2mblc\" \"A3\t\tis A3 & mvm4=1 & r2mblc\t\t{ movemptr = movemptr - 4; *movemptr = A3; }\nr2mblb: r2mblc\t\t\tis mvm4=0 & r2mblc\t\t\t{ }\nr2mbla: r2mblb\" \"A2\t\tis A2 & mvm5=1 & r2mblb\t\t{ movemptr = movemptr - 4; *movemptr = A2; }\nr2mbla: r2mblb\t\t\tis mvm5=0 & r2mblb\t\t\t{ }\nr2mbl9: r2mbla\" \"A1\t\tis A1 & mvm6=1 & r2mbla\t\t{ movemptr = movemptr - 4; *movemptr = A1; }\nr2mbl9: r2mbla\t\t\tis mvm6=0 & r2mbla\t\t\t{ }\nr2mbl8: r2mbl9\" \"A0\t\tis A0 & mvm7=1 & r2mbl9\t\t{ movemptr = movemptr - 4; *movemptr = A0; }\nr2mbl8: r2mbl9\t\t\tis mvm7=0 & r2mbl9\t\t\t{ }\nr2mbl7: r2mbl8\" \"D7\t\tis D7 & mvm8=1\t& r2mbl8\t{ movemptr = movemptr - 4; *movemptr = D7; }\nr2mbl7:\tr2mbl8\t\t\tis mvm8=0 & r2mbl8\t\t\t{ }\nr2mbl6: r2mbl7\" \"D6\t\tis D6 & mvm9=1 & r2mbl7\t\t{ movemptr = movemptr - 4; *movemptr = D6; }\nr2mbl6: r2mbl7\t\t\tis mvm9=0 & r2mbl7\t\t\t{ }\nr2mbl5: r2mbl6\" \"D5\t\tis D5 & mvm10=1 & r2mbl6\t{ movemptr = movemptr - 4; *movemptr = D5; }\nr2mbl5: r2mbl6\t\t\tis mvm10=0 & r2mbl6\t\t\t{ }\nr2mbl4: r2mbl5\" \"D4\t\tis D4 & mvm11=1 & r2mbl5\t{ movemptr = movemptr - 4; *movemptr = D4; }\nr2mbl4: r2mbl5\t\t\tis mvm11=0 & r2mbl5\t\t\t{ }\nr2mbl3: r2mbl4\" \"D3\t\tis D3 & mvm12=1 & r2mbl4\t{ movemptr = movemptr - 4; *movemptr = D3; }\nr2mbl3: r2mbl4\t\t\tis mvm12=0 & r2mbl4\t\t\t{ }\nr2mbl2: r2mbl3\" \"D2\t\tis D2 & mvm13=1 & r2mbl3\t{ movemptr = movemptr - 4; *movemptr = D2; }\nr2mbl2: r2mbl3\t\t\tis mvm13=0 & r2mbl3\t\t\t{ }\nr2mbl1: r2mbl2\" \"D1\t\tis D1 & mvm14=1 & r2mbl2\t{ movemptr = movemptr - 4; *movemptr = D1; }\nr2mbl1: r2mbl2\t\t\tis mvm14=0 & r2mbl2\t\t\t{ }\nr2mbl0: { r2mbl1\" \"D0}\tis D0 & mvm15=1 & r2mbl1\t{ movemptr = movemptr - 4; *movemptr = D0; }\nr2mbl0: { r2mbl1}\t\tis mvm15=0 & r2mbl1\t\t\t{ }\n\n\n # Memory to register, forward direction, via word\nm2rfwf: D0\t\t\t\tis D0 & mvm0=1\t\t\t\t{ D0 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfwf:\t\t\t\t\tis mvm0=0\t\t\t\t\t{ }\nm2rfwe: m2rfwf\" \"D1\t\tis D1 & mvm1=1 & m2rfwf\t\t{ D1 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfwe: m2rfwf\t\t\tis mvm1=0 & m2rfwf\t\t\t{ }\nm2rfwd: m2rfwe\" \"D2\t\tis D2 & mvm2=1 & m2rfwe\t\t{ D2 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfwd: m2rfwe\t\t\tis mvm2=0 & m2rfwe\t\t\t{ }\nm2rfwc: m2rfwd\" \"D3\t\tis D3 & mvm3=1 & m2rfwd\t\t{ D3 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfwc: m2rfwd\t\t\tis mvm3=0 & m2rfwd\t\t\t{ }\nm2rfwb: m2rfwc\" \"D4\t\tis D4 & mvm4=1 & m2rfwc\t\t{ D4 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfwb: m2rfwc\t\t\tis mvm4=0 & m2rfwc\t\t\t{ }\nm2rfwa: m2rfwb\" \"D5\t\tis D5 & mvm5=1 & m2rfwb\t\t{ D5 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfwa: m2rfwb\t\t\tis mvm5=0 & m2rfwb\t\t\t{ }\nm2rfw9: m2rfwa\" \"D6\t\tis D6 & mvm6=1 & m2rfwa\t\t{ D6 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw9: m2rfwa\t\t\tis mvm6=0 & m2rfwa\t\t\t{ }\nm2rfw8: m2rfw9\" \"D7\t\tis D7 & mvm7=1 & m2rfw9\t\t{ D7 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw8: m2rfw9\t\t\tis mvm7=0 & m2rfw9\t\t\t{ }\nm2rfw7: m2rfw8\" \"A0\t\tis A0 & mvm8=1\t& m2rfw8\t{ A0 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw7:\tm2rfw8\t\t\tis mvm8=0 & m2rfw8\t\t\t{ }\nm2rfw6: m2rfw7\" \"A1\t\tis A1 & mvm9=1 & m2rfw7\t\t{ A1 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw6: m2rfw7\t\t\tis mvm9=0 & m2rfw7\t\t\t{ }\nm2rfw5: m2rfw6\" \"A2\t\tis A2 & mvm10=1 & m2rfw6\t{ A2 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw5: m2rfw6\t\t\tis mvm10=0 & m2rfw6\t\t\t{ }\nm2rfw4: m2rfw5\" \"A3\t\tis A3 & mvm11=1 & m2rfw5\t{ A3 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw4: m2rfw5\t\t\tis mvm11=0 & m2rfw5\t\t\t{ }\nm2rfw3: m2rfw4\" \"A4\t\tis A4 & mvm12=1 & m2rfw4\t{ A4 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw3: m2rfw4\t\t\tis mvm12=0 & m2rfw4\t\t\t{ }\nm2rfw2: m2rfw3\" \"A5\t\tis A5 & mvm13=1 & m2rfw3\t{ A5 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw2: m2rfw3\t\t\tis mvm13=0 & m2rfw3\t\t\t{ }\nm2rfw1: m2rfw2\" \"A6\t\tis A6 & mvm14=1 & m2rfw2\t{ A6 = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw1: m2rfw2\t\t\tis mvm14=0 & m2rfw2\t\t\t{ }\nm2rfw0: { m2rfw1\" \"SP}\tis SP & mvm15=1 & m2rfw1\t{ SP = sext(*:2 movemptr); movemptr = movemptr + 2; }\nm2rfw0: { m2rfw1}\t\tis mvm15=0 & m2rfw1\t\t\t{ }\n\n\n\n # Memory to register, forward direction, via long\nm2rflf: D0\t\t\t\tis D0 & mvm0=1\t\t\t\t{ D0 = *movemptr; movemptr = movemptr + 4; }\nm2rflf:\t\t\t\t\tis mvm0=0\t\t\t\t\t{ }\nm2rfle: m2rflf\" \"D1\t\tis D1 & mvm1=1 & m2rflf\t\t{ D1 = *movemptr; movemptr = movemptr + 4; }\nm2rfle: m2rflf\t\t\tis mvm1=0 & m2rflf\t\t\t{ }\nm2rfld: m2rfle\" \"D2\t\tis D2 & mvm2=1 & m2rfle\t\t{ D2 = *movemptr; movemptr = movemptr + 4; }\nm2rfld: m2rfle\t\t\tis mvm2=0 & m2rfle\t\t\t{ }\nm2rflc: m2rfld\" \"D3\t\tis D3 & mvm3=1 & m2rfld\t\t{ D3 = *movemptr; movemptr = movemptr + 4; }\nm2rflc: m2rfld\t\t\tis mvm3=0 & m2rfld\t\t\t{ }\nm2rflb: m2rflc\" \"D4\t\tis D4 & mvm4=1 & m2rflc\t\t{ D4 = *movemptr; movemptr = movemptr + 4; }\nm2rflb: m2rflc\t\t\tis mvm4=0 & m2rflc\t\t\t{ }\nm2rfla: m2rflb\" \"D5\t\tis D5 & mvm5=1 & m2rflb\t\t{ D5 = *movemptr; movemptr = movemptr + 4; }\nm2rfla: m2rflb\t\t\tis mvm5=0 & m2rflb\t\t\t{ }\nm2rfl9: m2rfla\" \"D6\t\tis D6 & mvm6=1 & m2rfla\t\t{ D6 = *movemptr; movemptr = movemptr + 4; }\nm2rfl9: m2rfla\t\t\tis mvm6=0 & m2rfla\t\t\t{ }\nm2rfl8: m2rfl9\" \"D7\t\tis D7 & mvm7=1 & m2rfl9\t\t{ D7 = *movemptr; movemptr = movemptr + 4; }\nm2rfl8: m2rfl9\t\t\tis mvm7=0 & m2rfl9\t\t\t{ }\nm2rfl7: m2rfl8\" \"A0\t\tis A0 & mvm8=1\t& m2rfl8\t{ A0 = *movemptr; movemptr = movemptr + 4; }\nm2rfl7:\tm2rfl8\t\t\tis mvm8=0 & m2rfl8\t\t\t{ }\nm2rfl6: m2rfl7\" \"A1\t\tis A1 & mvm9=1 & m2rfl7\t\t{ A1 = *movemptr; movemptr = movemptr + 4; }\nm2rfl6: m2rfl7\t\t\tis mvm9=0 & m2rfl7\t\t\t{ }\nm2rfl5: m2rfl6\" \"A2\t\tis A2 & mvm10=1 & m2rfl6\t{ A2 = *movemptr; movemptr = movemptr + 4; }\nm2rfl5: m2rfl6\t\t\tis mvm10=0 & m2rfl6\t\t\t{ }\nm2rfl4: m2rfl5\" \"A3\t\tis A3 & mvm11=1 & m2rfl5\t{ A3 = *movemptr; movemptr = movemptr + 4; }\nm2rfl4: m2rfl5\t\t\tis mvm11=0 & m2rfl5\t\t\t{ }\nm2rfl3: m2rfl4\" \"A4\t\tis A4 & mvm12=1 & m2rfl4\t{ A4 = *movemptr; movemptr = movemptr + 4; }\nm2rfl3: m2rfl4\t\t\tis mvm12=0 & m2rfl4\t\t\t{ }\nm2rfl2: m2rfl3\" \"A5\t\tis A5 & mvm13=1 & m2rfl3\t{ A5 = *movemptr; movemptr = movemptr + 4; }\nm2rfl2: m2rfl3\t\t\tis mvm13=0 & m2rfl3\t\t\t{ }\nm2rfl1: m2rfl2\" \"A6\t\tis A6 & mvm14=1 & m2rfl2\t{ A6 = *movemptr; movemptr = movemptr + 4; }\nm2rfl1: m2rfl2\t\t\tis mvm14=0 & m2rfl2\t\t\t{ }\nm2rfl0: { m2rfl1\" \"SP}\tis SP & mvm15=1 & m2rfl1\t{ SP = *movemptr; movemptr = movemptr + 4; }\nm2rfl0: { m2rfl1}\t\tis mvm15=0 & m2rfl1\t\t\t{ }\n\n\nmovemOp: (regan)\t\tis mode=2 & regan { export regan; }\nmovemOp: (regan)+\t\tis mode=3 & regan { export regan; }\nmovemOp: -(regan)\t\tis mode=4 & regan { export regan; }\nmovemOp: (d16, regan)\tis mode=5 & regan; fldpar ; d16 { local tmp = regan + d16; export tmp; }\nmovemOp: (extw)\t\t\tis mode=6 & regan; fldpar ; extw [ pcmode=0; regtfan=regan; ] {build extw; export extw; }\nmovemOp: (d16)\".w\"\t\tis mode=7 & regan=0; fldpar; d16 { local tmp:4 = d16; export tmp; }\nmovemOp: (d32)\".l\"\t\tis mode=7 & regan=1; fldpar; d32 { local tmp:4 = d32; export tmp; }\nmovemOp: (d16,PC)\t\tis op10=1 & mode=7 & regan=2; fldpar; d16 & PC { local tmp = inst_start + 4 + d16:4; export tmp; }\nmovemOp: (extw)\t\t\tis op10=1 & mode=7 & regan=3; fldpar; extw [ pcmode=1; ] { build extw; export extw; }\n\nmovemWrt:\t\t\t\tis (mode=3 | mode=4) & regan { regan = movemptr; }\nmovemWrt:\t\t\t\tis mode { }\n\n:movem.w r2mfw0, movemOp\t\tis (opbig=0x48 & op67=2; r2mfw0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mfw0; }\n:movem.w r2mbw0, movemOp\t\tis (opbig=0x48 & op67=2 & mode=4 & movemWrt; r2mbw0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mbw0; build movemWrt; }\n\n:movem.l r2mfl0, movemOp\t\tis (opbig=0x48 & op67=3; r2mfl0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mfl0; }\n:movem.l r2mbl0, movemOp\t\tis (opbig=0x48 & op67=3 & mode=4 & movemWrt; r2mbl0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mbl0; build movemWrt; }\n\n:movem.w movemOp, m2rfw0\t\tis (opbig=0x4c & op67=2 & movemWrt; m2rfw0) ... & movemOp { build movemOp; movemptr = movemOp; build m2rfw0; build movemWrt; }\n:movem.l movemOp, m2rfl0\t\tis (opbig=0x4c & op67=3 & movemWrt; m2rfl0) ... & movemOp { build movemOp; movemptr = movemOp; build m2rfl0; build movemWrt; }\n\n\nepw: (d16, regan) is regan; d16 { local tmp = regan + d16; export tmp; }\n:movep.w epw,reg9dnw\tis (op=0 & reg9dnw & op68=4 & op35=1) ... & epw\t\t{ src:4 = epw; ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); }\t\n:movep.l epw,reg9dn\t\tis (op=0 & reg9dn & op68=5 & op35=1) ... & epw\t\t{ src:4 = epw; ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); }\n:movep.w reg9dnw,epw\tis (op=0 & reg9dnw & op68=6 & op35=1) ... & epw\t\t{ src:4 = epw; local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; }\n:movep.l reg9dn,epw\t is (op=0 & reg9dn & op68=7 & op35=1)... & epw\t\t{ src:4 = epw; local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; }\n\n:moveq d8base,reg9dn\t\tis op=7 & reg9dn & op8=0 & d8base\t\t\t\t{ reg9dn = d8base; resflags(reg9dn); logflags(); }\n\n:moves.b rreg,e2b\t\tis opbig=0x0e & op67=0 & mode & regan; rreg & wl=1; e2b\t [ regtsan=regan; savmod2=mode; ] { e2b = rreg:1; }\n:moves.w rreg,e2w\t\tis opbig=0x0e & op67=1 & mode & regan; rreg & wl=1; e2w [ regtsan=regan; savmod2=mode; ] { e2w = rreg:2; }\n:moves.l rreg,e2l\t\tis opbig=0x0e & op67=2 & mode & regan; rreg & wl=1; e2l [ regtsan=regan; savmod2=mode; ] { e2l = rreg; }\n:moves.b e2b,rreg\t\tis opbig=0x0e & op67=0 & mode & regan; da=0 & rreg & wl=0; e2b\t[ regtsan=regan; savmod2=mode; ] { rreg = (rreg & 0xffffff00) | zext(e2b); }\n:moves.w e2w,rreg\t\tis opbig=0x0e & op67=1 & mode & regan; da=0 & rreg & wl=0; e2w [ regtsan=regan; savmod2=mode; ] { rreg = (rreg & 0xffff0000) | zext(e2w); }\n:moves.b e2b,rreg\t\tis opbig=0x0e & op67=0 & mode & regan; da=1 & rreg & wl=0; e2b\t[ regtsan=regan; savmod2=mode; ] { rreg = sext(e2b); }\n:moves.w e2w,rreg\t\tis opbig=0x0e & op67=1 & mode & regan; da=1 & rreg & wl=0; e2w [ regtsan=regan; savmod2=mode; ] { rreg = sext(e2w); }\n:moves.l e2l,rreg\t\tis opbig=0x0e & op67=2 & mode & regan; rreg & wl=0; e2l [ regtsan=regan; savmod2=mode; ] { rreg = e2l; }\n\n:muls.w eaw,reg9dn\t\tis (op=12 & reg9dn & op68=7)... & eaw {\n\ttmp1:4 = sext( reg9dn:2 );\n\ttmp2:4 = sext(eaw);\n\treg9dn = tmp1 * tmp2;\n\tresflags(reg9dn); CF=0; VF=0;}\n\n:mulu.w eaw,reg9dn\t\tis (op=12 & reg9dn & op68=3)... & eaw {\n\ttmp1:4 = zext( reg9dn:2 );\n\ttmp2:4 = zext(eaw);\n\treg9dn = tmp1 * tmp2;\n\tresflags(reg9dn);\n\tCF=0; VF=0;\n}\n\nmulsize: \"s.l\"\t\t\tis divsgn=1\t\t\t\t\t\t{ }\nmulsize: \"u.l\"\t\t\tis divsgn=0\t\t\t\t\t\t{ }\n\nsubmul: regdq\t\t\tis regdq & divsgn=1 & divsz=0\t\t\t{ regdq = glbdenom * regdq; resflags(regdq); CF=0; }\nsubmul: regdr-regdq\t\tis regdq & divsgn=1 & divsz=1 & regdr\t{\n\ttmp1:8 = sext(glbdenom);\n\ttmp2:8 = sext(regdq);\n\tlocal res = tmp1 * tmp2;\n\tregdq = res:4;\n\tregdr = res(4);\n\tresflags(res);\n\tCF=0;\n\tVF=0;\n}\nsubmul: regdq\t\t\tis regdq & divsgn=0 & divsz=0\t\t\t{ regdq = glbdenom * regdq; resflags(regdq); CF=0; }\nsubmul: regdr-regdq\t\tis regdq & divsgn=0 & divsz=1 & regdr\t{\n\ttmp1:8 = zext(glbdenom);\n\ttmp2:8 = zext(regdq);\n\tlocal res = tmp1 * tmp2;\n\tregdq = res:4;\n\tregdr = res(4);\n\tresflags(res);\n\tCF=0;\n\tVF=0;\n\n}\n:mul^mulsize e2l,submul\t\tis opbig=0x4c & op67=0 & $(DAT_ALTER_ADDR_MODES); submul & mulsize; e2l [ savmod2=savmod1; regtsan=regtfan; ] { glbdenom=e2l; build submul; }\n\n:nbcd eab\tis (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab {\n\tlocal tmp = eab;\n\tCF = (tmp != 0) || (XF == 1);\n\ttmp = 0 - tmp - XF;\n\teab = bcdAdjust(tmp);\n\tbcdflags(tmp);\n}\n\n# NB: For the neg insn the CF carry flag is not set like other insns, from the manual:\n# XF - Set the same as the carry bit.\n# NF - Set if the result is negative; cleared otherwise.\n# ZF - Set if the result is zero; cleared otherwise.\n# VF - Set if an overflow occurs; cleared otherwise.\n# CF - Cleared if the result is zero; set otherwise.\n\nmacro negFlags(op1) {\n VF = sborrow(0, op1);\n}\n\nmacro negResFlags(result) {\n NF = result s< 0;\n CF = result != 0;\n XF = CF;\n ZF = result == 0;\n}\n\n:neg.b eab\t\tis (opbig=0x44 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab\n\t\t\t\t\t{ o2:1=eab; negFlags(o2); o2 = -o2; eab=o2; negResFlags(o2); }\n:neg.w eaw\t\tis (opbig=0x44 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw\n\t\t\t\t\t{ o2:2=eaw; negFlags(o2); o2 = -o2; eaw=o2; negResFlags(o2); }\n:neg.l eal\t\tis (opbig=0x44 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal\n\t\t\t\t\t{ o2:4=eal; negFlags(o2); o2 = -o2; eal=o2; negResFlags(o2); }\n\n# NB: For the negx insn the CF and ZF flags are not set like other insns, from the manual:\n# XF - Set the same as the carry bit.\n# NF - Set if the result is negative; cleared otherwise.\n# ZF - Cleared if the result is nonzero; unchanged otherwise.\n# VF - Set if an overflow occurs; cleared otherwise.\n# CF - Set if borrow occurs; otherwise.\n\n:negx.b eab\t\tis (opbig=0x40 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab\n\t\t\t\t\t{ local tmp = eab + XF; negxsubflags(tmp); tmp = -tmp; eab=tmp; extendedResultFlags(tmp); }\n:negx.w eaw\t\tis (opbig=0x40 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw\n\t\t\t\t\t{ local tmp = eaw + zext(XF); negxsubflags(tmp); tmp = -tmp; eaw=tmp; extendedResultFlags(tmp); }\n:negx.l eal\t\tis (opbig=0x40 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal\n\t\t\t\t\t{ local tmp = eal + zext(XF); negxsubflags(tmp); tmp = -tmp; eal=tmp; extendedResultFlags(tmp); }\n\n:nop\t\t\t\tis opbig=0x4e & op37=14 & op02=1\t\t\t{ }\n\n:not.b eab\t\t\tis (opbig=0x46 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab\t\t\t{ local tmp = eab; logflags(); tmp = ~tmp; eab = tmp; resflags(tmp); }\n:not.w eaw\t\t\tis (opbig=0x46 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t{ local tmp = eaw; logflags(); tmp = ~tmp; eaw = tmp; resflags(tmp); }\n:not.l eal\t\t\tis (opbig=0x46 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal\t\t\t{ local tmp = eal; logflags(); tmp = ~tmp; eal = tmp; resflags(tmp); }\n\n:or.b eab,reg9dnb\t\tis (op=8 & reg9dnb & op68=0 & $(DAT_ALTER_ADDR_MODES))... & eab\t\t\t{ or(eab, reg9dnb); }\n:or.w eaw,reg9dnw\t\tis (op=8 & reg9dnw & op68=1 & $(DAT_ALTER_ADDR_MODES))... & eaw\t\t\t{ or(eaw, reg9dnw); }\n:or.l eal,reg9dn\t\tis (op=8 & reg9dn & op68=2 & $(DAT_ALTER_ADDR_MODES))... & eal\t\t\t{ or(eal, reg9dn); }\n\n:or.b reg9dnb,eab\t\tis (op=8 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab\t\t\t{ or(reg9dnb, eab); }\n:or.w reg9dnw,eaw\t\tis (op=8 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw\t\t\t{ or(reg9dnw, eaw); }\n:or.l reg9dn,eal\t\tis (op=8 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal\t\t\t{ or(reg9dn, eal); }\n\n:ori.b const8,e2b\t\t\tis opbig=0 & op67=0 & $(DAT_ALTER_ADDR_MODES); const8; e2b\t\t[ savmod2=savmod1; regtsan=regtfan; ] { or(const8, e2b); }\n:ori.w const16,e2w\t\t\tis opbig=0 & op67=1 & $(DAT_ALTER_ADDR_MODES); const16; e2w\t\t[ savmod2=savmod1; regtsan=regtfan; ] { or(const16, e2w); }\n:ori.l const32,e2l\t\t\tis opbig=0 & op67=2 & $(DAT_ALTER_ADDR_MODES); const32; e2l\t\t[ savmod2=savmod1; regtsan=regtfan; ] { or(const32, e2l); }\n:ori const8,\"CCR\"\t\t\tis opbig=0 & op37=7 & op02=4; const8\t\t\t{ packflags(SR); SR=SR|zext(const8); unpackflags(SR); }\n:ori const16,SR\t\t\t\tis SR; opbig=0x00 & d8base=0x7c; const16\t\t\t{ packflags(SR); SR=SR|const16; unpackflags(SR); }\n\n:pack Tyw,Txw,const16\t\tis op=8 & op48=20 & Txw & Tyw & rmbit=0; const16 {\n\tlocal value = (Tyw & 0x0F0F) + const16;\n\tTxw = (Txw & 0xFF00) | ((value & 0x0F00) >> 4) | (value & 0x000F);\n}\n\n:pack Tyw,Txb,const16\t\tis op=8 & op48=20 & Tyw & Txb & rmbit=1; const16 {\n\tlocal value = (Tyw & 0x0F0F) + const16;\n\tlocal result:2 = ((value & 0x0F00) >> 4) | (value & 0x000F);\n\tTxb = result:1;\n}\n\n:pea eaptr\t\t\tis (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr\t\t\t{ value:4 = eaptr; SP = SP-4; *SP = value; }\n\n@ifdef MC68040\n\n:pflushn regPlus\tis opbig=0xf5 & op67=0 & op5=0 & op34=0 & regPlus\tunimpl\n:pflush regPlus\t\tis opbig=0xf5 & op67=0 & op5=0 & op34=1 & regPlus\tunimpl\n:pflushan\t\t\tis opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0\tunimpl\n:pflusha\t\t\tis opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0\tunimpl\n\n@endif # MC68040\n\n@ifdef MC68030\n\n:pflusha\t\tis opbig=0xf0 & op67=0 & mode=0 & regan=0; opx015=0x2400\tunimpl\n\nFC: SFC\t\t\tis fc4=0 & fc3=0 & fc02=0 & SFC\t\t{ export SFC; }\nFC: DFC\t\t\tis fc4=0 & fc3=0 & fc02=1 & DFC \t{ export DFC; }\nFC: regdc\t\tis fc4=0 & fc3=1 & regdc \t\t\t{ export regdc; }\nFC: \"#\"^fc03\tis fc4=1 & fc3=0 & fc03 \t\t\t{ export *[const]:4 fc03; }\n\nFCmask: \"#\"^fcmask\tis fcmask\t{ export *[const]:1 fcmask; }\n\n:pflush FC,FCmask\t\tis opbig=0xf0 & op67=0 & mode=0 & regan=0; bigopx=0x30 & FCmask & FC unimpl\n\n:pflush FC,FCmask,e2l\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); bigopx=0x38 & FCmask & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:ploadr FC,e2l\t\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx515=0x110 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl \n\n:ploadw FC,e2l\t\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx515=0x100 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl \n\n:pmove.l TC,e2l\t\tis TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmove.l e2l,TC\t\tis TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmovefd.l e2l,TC\tis TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=1 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:pmove.d SRP,e2d\tis SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2d\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmove.d e2d,SRP\tis SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2d\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmovefd.d e2d,SRP\tis SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=1 & d8=0; e2d\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:pmove.d CRP,e2d\tis CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=1 & fbit=0 & d8=0; e2d\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmove.d e2d,CRP\tis CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=0 & fbit=0 & d8=0; e2d\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmovefd.d e2d,CRP\tis CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=0 & fbit=1 & d8=0; e2d\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:pmove.w MMUSR,e2w\tis MMUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2w\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmove.w e2w,MMUSR\tis MMUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2w\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:pmove.l TT0,e2l\tis TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmove.l e2l,TT0\tis TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmovefd.l e2l,TT0\tis TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=0 & fbit=1 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:pmove.l TT1,e2l\tis TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=1 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmove.l e2l,TT1\tis TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=0 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:pmovefd.l e2l,TT1\tis TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=0 & fbit=1 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n#TODO: MC68EC030 only - conflicts with MMUSR form above\n#:pmove.w ACUSR,e2w\tis ACUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2w\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n#:pmove.w e2w,ACUSR\tis ACUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2w\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n#TODO: MC68EC030 only - - conflicts with TTx form above\n#:pmove.l ACx,e2l\tis ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=1 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n#:pmove.l e2l,ACx\tis ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=0 & fbit=0 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n#:pmovefd.l e2l,ACx\tis ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=0 & fbit=1 & d8=0; e2l\t[ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n@endif # MC68030\n\n#TODO: PMOVE PMMU Register - MC68851 only\n\n#TODO: PRESTORE PMMU Register - MC68851 only\n\n#TODO: PSAVE PMMU Register - MC68851 only\n\n#TODO: PScc PMMU Register - MC68851 only\n\n@ifdef MC68030\n\nptestLevel: \"#\"^mregn\tis mregn { export *[const]:1 mregn; }\n\n:ptestr FC,e2l,ptestLevel\t\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=1 & fbit=0 & aregx=0 & FC; e2l\t [ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:ptestr FC,e2l,ptestLevel,aregx\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=1 & fbit=1 & aregx & FC; e2l\t [ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n:ptestw FC,e2l,ptestLevel\t\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=0 & fbit=0 & aregx=0 & FC; e2l\t [ savmod2=savmod1; regtsan=regtfan; ] unimpl\n:ptestw FC,e2l,ptestLevel,aregx\tis opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=0 & fbit=1 & aregx & FC; e2l\t [ savmod2=savmod1; regtsan=regtfan; ] unimpl\n\n@endif # MC68030\n\n#TODO: PTEST FC, - MC68EX030 only\n\n#TODO: PTEST FC,,#level,(An) - MC68851 only\n\n@ifdef MC68040\n\n:ptestr regPlus\tis opbig=0xf5 & op67=1 & op35=5 & regPlus\t\tunimpl\n:ptestw regPlus\tis opbig=0xf5 & op67=1 & op35=1 & regPlus\t\tunimpl\n\n@endif # MC68040\n\n#TODO: PTRAPcc - MC68851 only\n\n#TODO: PVALID - MC68851 only\n\n:reset\tis d16=0x4e70\t{ reset(); }\n\n:rol.b cntreg,regdnb\t\tis op=14 & cntreg & op8=1 & op67=0 & op34=3 & regdnb\t{ rotateLeft(cntreg, regdnb, 8); }\n:rol.w cntreg,regdnw\t\tis op=14 & cntreg & op8=1 & op67=1 & op34=3 & regdnw\t{ rotateLeft(cntreg, regdnw, 16); }\n:rol.l cntreg,regdn\t\t\tis op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn\t\t\t{ rotateLeft(cntreg, regdn, 32); }\n:rol eaw\t\t\t\t\tis (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tvalue = (value << 1) | (value >> 15);\n\tgetbit(CF, value, 0);\n\tresflags(value);\n\teaw = value;\n\tVF = 0;\n}\n\n:ror.b cntreg,regdnb\t\tis op=14 & cntreg & op8=0 & op67=0 & op34=3 & regdnb\t{ rotateRight(cntreg, regdnb, 8); }\n:ror.w cntreg,regdnw\t\tis op=14 & cntreg & op8=0 & op67=1 & op34=3 & regdnw\t{ rotateRight(cntreg, regdnw, 16); }\n:ror.l cntreg,regdn\t\t\tis op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn \t\t{ rotateRight(cntreg, regdn, 32); }\n:ror eaw\t\t\t\t\tis (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tvalue = (value << 15) | (value >> 1);\n\tgetbit(CF, value, 15);\n\tresflags(value);\n\teaw = value;\n\tVF = 0;\n}\n\n:roxl.b cntreg,regdnb\t\tis op=14 & cntreg & op8=1 & op67=0 & op34=2 & regdnb\t{ rotateLeftExtended(cntreg, regdnb, 8); }\n:roxl.w cntreg,regdnw\t\tis op=14 & cntreg & op8=1 & op67=1 & op34=2 & regdnw\t{ rotateLeftExtended(cntreg, regdnw, 16); }\n:roxl.l cntreg,regdn\t\tis op=14 & cntreg & op8=1 & op67=2 & op34=2 & regdn\t\t{ rotateLeftExtended(cntreg, regdn, 32); }\n:roxl eaw\t\t\t\t\tis (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tlocal xflag = (value & 0x8000) != 0;\n\tvalue = (value << 1) | zext(XF);\n\tresflags(value);\n\teaw = value;\n\tVF = 0;\n\tXF = xflag;\n\tCF = XF;\n}\n\n:roxr.b cntreg,regdnb\t\tis op=14 & cntreg & op8=0 & op67=0 & op34=2 & regdnb\t{ rotateRightExtended(cntreg, regdnb, 8); }\n:roxr.w cntreg,regdnw\t\tis op=14 & cntreg & op8=0 & op67=1 & op34=2 & regdnw\t{ rotateRightExtended(cntreg, regdnw, 16); }\n:roxr.l cntreg,regdn\t\tis op=14 & cntreg & op8=0 & op67=2 & op34=2 & regdn\t\t{ rotateRightExtended(cntreg, regdn, 32); }\n:roxr eaw\t\t\t\t\tis (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw\t{\n\tlocal value:2 = eaw;\n\tlocal xflag = (value & 0x0001) != 0;\n\tvalue = (zext(XF) << 15) | (value >> 1);\n\tresflags(value);\n\teaw = value;\n\tVF = 0;\n\tXF = xflag;\n\tCF = XF;\n}\n\n:rtd const16\t\tis opbig=0x4e & op37=14 & op02=4; const16\t{ PC = *SP; SP = SP + 4 + zext(const16); return [PC]; }\n:rte\t\t\t\tis d16=0x4e73\t\t\t\t\t\t\t{ tmp:4 = 0; return [tmp]; }\n\ndefine pcodeop rtm;\n:rtm regdn\t\t\tis opbig=0x06 & op37=24 & regdn\t\t\t{ PC = rtm(regdn); return [PC]; }\n:rtm regan\t\t\tis opbig=0x06 & op37=25 & regan\t\t\t{ PC = rtm(regan); return [PC];}\n\n:rtr\t\t\t\tis opbig=0x4e & op37=14 & op02=7\t\t{ SR = *SP; SP = SP+2; PC = *SP; SP = SP+4; unpackflags(SR); return [PC]; }\n\n:rts\t\t\t\tis opbig=0x4e & op37=14 & op02=5\t\t{ PC = *SP; SP = SP+4; return [PC]; }\n\n:sbcd Tyb,Txb\t\tis op=8 & op48=16 & Txb & Tyb {\n\tCF = (Txb < Tyb) || ( (XF == 1) && (Txb == Tyb) );\n\tTxb = Txb - Tyb - XF;\n\tTxb = bcdAdjust(Txb);\n\tbcdflags(Txb);\n}\n\n:s^cc eab\t\t\tis (op=5 & cc & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab\t\t\t\t{ eab = -cc; }\n\ndefine pcodeop stop;\n:stop const16\t\tis opbig=0x4e & d8base=0x72; const16\t{\n\tSR = const16; unpackflags(SR);\n\tstop();\n}\n\n:sub.b eab,reg9dnb\t\tis (op=9 & reg9dnb & op68=0)... & eab\t{ sub(eab, reg9dnb); }\n:sub.w eaw,reg9dnw\t\tis (op=9 & reg9dnw & op68=1)... & eaw\t{ sub(eaw, reg9dnw); }\n:sub.l eal,reg9dn\t\tis (op=9 & reg9dn & op68=2)... & eal\t{ sub(eal, reg9dn); }\n:sub.b reg9dnb,eab\t\tis (op=9 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab\t\t{ sub(reg9dnb, eab); }\n:sub.w reg9dnw,eaw\t\tis (op=9 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw\t\t{ sub(reg9dnw, eaw); }\n:sub.l reg9dn,eal\t\tis (op=9 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal\t\t{ sub(reg9dn, eal); }\n\n:suba.w eaw,reg9an\t\tis (op=9 & reg9an & op68=3)... & eaw\t{ reg9an = reg9an - sext(eaw); }\n:suba.l eal,reg9an\t\tis (op=9 & reg9an & op68=7)... & eal\t{ reg9an = reg9an - eal; }\n\n:subi.b const8,e2b\t\tis opbig=4 & op67=0 & $(DAT_ALTER_ADDR_MODES); const8; e2b\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ sub(const8, e2b); }\n:subi.w const16,e2w\t\tis opbig=4 & op67=1 & $(DAT_ALTER_ADDR_MODES); const16; e2w\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ sub(const16, e2w); }\n:subi.l const32,e2l\t\tis opbig=4 & op67=2 & $(DAT_ALTER_ADDR_MODES); const32; e2l\t[ savmod2=savmod1; regtsan=regtfan; ]\t{ sub(const32, e2l); }\n\n:subq.b \"#\"^quick,eab\t\tis (op=5 & quick & op68=4)... & eab\t\t{ sub(quick, eab); }\n:subq.w \"#\"^quick,eaw\t\tis (op=5 & quick & op68=5)... & eaw\t\t{ sub(quick, eaw); }\n:subq.l \"#\"^quick,eal\t\tis (op=5 & quick & op68=6)... & eal\t\t{ sub(quick, eal); }\n\n# special case for address register destination: condition codes not affected\n:subq.w \"#\"^quick,regan\t\tis op=5 & quick & op68=5 & mode=1 & regan\t\t\t{ regan = regan - quick; }\n:subq.l \"#\"^quick,regan\t\tis op=5 & quick & op68=6 & mode=1 & regan\t\t\t{ regan = regan - quick; }\n\n\n\n:subx.b Tyb,Txb\t\t\tis op=9 & op8=1 & op67=0 & op45=0 & Tyb & Txb\n { tmp0:1 = zext(XF); subxflags(Txb, Tyb); local tmp =tmp0+Tyb; Txb=Txb-tmp; extendedResultFlags(Txb); }\n\n:subx.w Tyw,Txw\t\t\tis op=9 & op8=1 & op67=1 & op45=0 & Tyw & Txw\n { tmp0:2 = zext(XF); subxflags(Txw, Tyw); local tmp =tmp0+Tyw; Txw=Txw-tmp; extendedResultFlags(Txw); }\n\n:subx.l Ty,Tx\t\t\tis op=9 & op8=1 & op67=2 & op45=0 & Ty & Tx\n { tmp0:4 = zext(XF); subxflags(Tx, Ty); local tmp =tmp0+Ty; Tx=Tx-tmp; extendedResultFlags(Tx); }\n\n\n:swap regdn\t\t\t\tis opbig=0x48 & op37=8 & regdn\t\t\t\t\t{ logflags(); regdn = (regdn << 16) | (regdn>>16); resflags(regdn); }\n\n@ifndef COLDFIRE\n:tas eab\t\t\t\tis (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab\t\t\t\t{ logflags(); resflags(eab); eab = eab | 0x80; }\n@endif # COLDFIRE\n\n:trap \"#\"^op03\t\t\tis opbig=0x4e & op67=1 & op45=0 & op03\t\t{ vector:1 = op03; __m68k_trap(vector); }\n:trap^cc\t\t\t\tis op=5 & cc & op37=31 & op02=4\t\t\t\t{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = inst_next; vector:1 = 7; __m68k_trap(vector); }\n:trap^cc^\".w\" const16\tis op=5 & cc & op37=31 & op02=2; const16\t{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = inst_next; __m68k_trapv(); }\n:trap^cc^\".l\" const32\tis op=5 & cc & op37=31 & op02=3; const32\t{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = inst_next; __m68k_trapv(); }\n:trapv\t\t\t\t\tis opbig=0x4e & op37=14 & op02=6\t\t\t{ if (!VF) goto inst_next; __m68k_trapv(); }\n\n:tst.b eab\t\t\t\tis (opbig=0x4a & op67=0)... & eab\t\t\t\t{ logflags(); resflags(eab); }\n:tst.w eaw\t\t\t\tis (opbig=0x4a & op67=1)... & eaw\t\t\t\t{ logflags(); resflags(eaw); }\n:tst.l eal\t\t\t\tis (opbig=0x4a & op67=2)... & eal\t\t\t\t{ logflags(); resflags(eal); }\n\n@ifdef COLDFIRE\n:tas eab\t\t\t\tis (opbig=0x4a & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eab\t\t\t\t{ logflags(); resflags(eab); eab = eab | 0x80; }\n@endif # COLDFIRE\n\n:unlk regan\t\t\t\tis opbig=0x4e & op37=11 & regan\t\t\t\t\t{ SP = regan; regan = *SP; SP = SP+4; }\n\n:unpk Tyw,Txw,const16\tis op=8 & Txw & op48=24 & Tyw & rmbit=0; const16 {\n\tTxw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + const16);\n}\n\n:unpk Tyb,Txw,const16\tis op=8 & Tyb & op48=24 & Txw & rmbit=1; const16 {\n\tlocal source:2 = zext(Tyb);\n\tsource = (((source & 0x00F0) << 4) | (source & 0x000F)) + const16;\n\tTxw = (Txw & 0xF0F0) | source;\n}\n\n# Floating Point Instructions\n\n# 68040 directly implements Floating Point instructions but requires Coprocessor ID be 001\n@ifdef MC68040\n@define FP_COP \"copid=1\"\n@define FP_FCOP \"fcopid=1\"\n@else\n@define FP_COP \"epsilon\"\n@define FP_FCOP \"epsilon\"\n@endif\n\n# Condition codes\nfcc: \"eq\"\tis fcode=0x01\t\t\t{ tmp:1 = $(Z_FP); clearflags_fp(); export tmp; }\nfcc: \"ne\"\tis fcode=0x0e\t\t\t{ tmp:1 = !($(Z_FP)); clearflags_fp(); export tmp; } # note this is wrong in the manual\nfcc: \"gt\"\tis fcode=0x12\t\t\t{ tmp:1 = !($(NAN_FP) || $(Z_FP) || $(N_FP)); clearflags_fp(); export tmp; }\nfcc: \"ngt\"\tis fcode=0x1d\t\t\t{ tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; }\nfcc: \"ge\"\tis fcode=0x13\t\t\t{ tmp:1 = $(Z_FP) || !($(NAN_FP) || $(N_FP)); clearflags_fp(); export tmp; }\nfcc: \"nge\"\tis fcode=0x1c\t\t\t{ tmp:1 = $(NAN_FP) || ($(N_FP) && !$(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"lt\"\tis fcode=0x14\t\t\t{ tmp:1 = $(N_FP) && !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"nlt\"\tis fcode=0x1b\t\t\t{ tmp:1 = $(NAN_FP) || ($(Z_FP) || !$(N_FP)); clearflags_fp(); export tmp; }\nfcc: \"le\"\tis fcode=0x15\t\t\t{ tmp:1 = $(Z_FP) || ($(N_FP) && !$(NAN_FP)); clearflags_fp(); export tmp; }\nfcc: \"nle\"\tis fcode=0x1a\t\t\t{ tmp:1 = $(NAN_FP) || !($(N_FP) || $(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"gl\"\tis fcode=0x16\t\t\t{ tmp:1 = !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"ngl\"\tis fcode=0x19\t\t\t{ tmp:1 = $(NAN_FP) || $(Z_FP); clearflags_fp(); export tmp; }\nfcc: \"gle\"\tis fcode=0x17\t\t\t{ tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }\nfcc: \"ngle\"\tis fcode=0x18\t\t\t{ tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }\n\nfcc: \"ogt\"\tis fcode=0x02\t\t\t{ tmp:1 = !($(NAN_FP) || $(Z_FP) || $(N_FP)); clearflags_fp(); export tmp; }\nfcc: \"ule\"\tis fcode=0x0d\t\t\t{ tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; }\nfcc: \"oge\"\tis fcode=0x03\t\t\t{ tmp:1 = $(Z_FP) || !($(NAN_FP) || $(N_FP)); clearflags_fp(); export tmp; }\nfcc: \"ult\"\tis fcode=0x0c\t\t\t{ tmp:1 = $(NAN_FP) || ($(N_FP) && !$(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"olt\"\tis fcode=0x04\t\t\t{ tmp:1 = $(N_FP) && !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"uge\"\tis fcode=0x0b\t\t\t{ tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; }\nfcc: \"ole\"\tis fcode=0x05\t\t\t{ tmp:1 = $(Z_FP) || ($(N_FP) && !$(NAN_FP)); clearflags_fp(); export tmp; }\nfcc: \"ugt\"\tis fcode=0x0a\t\t\t{ tmp:1 = !$(NAN_FP) || !($(N_FP) || $(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"ogl\"\tis fcode=0x06\t\t\t{ tmp:1 = !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }\nfcc: \"ueq\"\tis fcode=0x09\t\t\t{ tmp:1 = $(NAN_FP) || $(Z_FP); clearflags_fp(); export tmp; }\nfcc: \"or\"\tis fcode=0x07\t\t\t{ tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }\nfcc: \"un\"\tis fcode=0x08\t\t\t{ tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }\n\nfcc: \"f\"\tis fcode=0x00\t\t\t{ export 0:1; }\nfcc: \"t\"\tis fcode=0x0f\t\t\t{ export 1:1; }\nfcc: \"sf\"\tis fcode=0x10\t\t\t{ export 0:1; }\nfcc: \"st\"\tis fcode=0x1f\t\t\t{ export 1:1; }\nfcc: \"seq\"\tis fcode=0x11\t\t\t{ tmp:1 = $(Z_FP); clearflags_fp(); export tmp; }\nfcc: \"sne\"\tis fcode=0x1e\t\t\t{ tmp:1 = $(Z_FP); clearflags_fp(); export tmp; }\n\n@define FormatByteWordLongSimple \"( ffmt=0 | ffmt=1 | ffmt=4 | ffmt=6 )\"\n\n# The following constraint should be used when using fprec\n@define FPREC_BWL \"fprec & ( ffmt=0 | ffmt=4 | ffmt=6 )\" # Byte,Word,Long only\n@define FPREC_S \"fprec & ffmt=1\" # Single only\n@define FPREC_BWLS \"fprec & ( ffmt=0 | ffmt=1 | ffmt=4 | ffmt=6 )\" # Byte,Word,Long,Single only\n@define FPREC_DXP \"fprec & ( ffmt=2 | ffmt=3 | ffmt=5)\" # Double,Extended,Packed only\n@define FPREC_XP \"fprec & ( ffmt=2 | ffmt=3)\" # Extended,Packed only\n@define FPREC_DX \"fprec & ( ffmt=2 | ffmt=5)\" # Double,Extended only\n@define FPREC_X \"fprec & ffmt=2\" # Extended only\n@define FPREC_D \"fprec & ffmt=5\" # Double only\n@define FPREC_P \"fprec & ffmt=3\" # Packed only\n@define FPREC_Pd \"fprec & ffmt=7\" # Packed-dynamic only\n\nfprec: \"l\" is ffmt=0 {}\nfprec: \"s\" is ffmt=1 {}\nfprec: \"x\" is ffmt=2 {}\nfprec: \"p\" is ffmt=3 {}\nfprec: \"w\" is ffmt=4 {}\nfprec: \"d\" is ffmt=5 {}\nfprec: \"b\" is ffmt=6 {}\nfprec: \"p\" is ffmt=7 {}\n\n\n# 0 = long\n# 4 = word\n# 6 = byte\n# 1 = Single precision\n# 2 = Extended-Precision real\n# 3 = Packed-decimal real\n# 5 = Double-Precision real\nf_mem: e2l is ffmt=0; e2l { val:4 = e2l; tmp:10 = int2float(val); export tmp; }\nf_mem: e2w is ffmt=4; e2w { val:2 = e2w; tmp:10 = int2float(val); export tmp; }\nf_mem: e2b is ffmt=6; e2b { val:1 = e2b; tmp:10 = int2float(val); export tmp; }\nf_mem: e2l is ffmt=1; e2l { tmp:10 = float2float(e2l); export tmp; }\nf_mem: e2x is ffmt=2; e2x { tmp:10 = float2float(e2x); export tmp; }\nf_mem: e2x is ffmt=3; e2x { tmp:10 = float2float(e2x); export tmp; }\nf_mem: e2d is ffmt=5; e2d { tmp:10 = float2float(e2d); export tmp; }\n\n:fabs.^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x18) ... & f_mem\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); } \n\n:fabs fsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x18\t{ fdst = abs(fsrc); } \n\n@ifdef MC68040\n\nfabsrnd: \"s\" is fdst & fopmode=0x58 { tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfabsrnd: \"d\" is fdst & fopmode=0x5c { tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fabsrnd^\"abs.\"^fprec f_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & fprec & (fopmode=0x58 | fopmode=0x5c)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); build fabsrnd; } \n:f^fabsrnd^\"abs\" fsrc, fdst\t\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fabsrnd\t& (fopmode=0x58 | fopmode=0x5c)\t{ fdst = abs(fsrc); build fabsrnd; }\n\n@endif # MC68040\n\n:facos.^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1c) ... & f_mem\n\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = acos(f_mem);}\n:facos fsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1c\t\t{ fdst = acos(fsrc); }\n\n\n:fadd.^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x22) ... & f_mem\n\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f+ f_mem; }\n:fadd fsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x22\t{ fdst = fdst f+ fsrc; }\n\n@ifdef MC68040\n\nfaddrnd: \"s\"\tis fdst & fopmode=0x62\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfaddrnd: \"d\"\tis fdst & fopmode=0x66\t{ tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^faddrnd^\"add.\"^fprec f_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & fprec & (fopmode=0x62 | fopmode=0x66)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f+ f_mem; build faddrnd; }\n:f^faddrnd^\"add\" fsrc, fdst\t\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & faddrnd & (fopmode=0x62 | fopmode=0x66)\t{ fdst = fdst f+ fsrc; build faddrnd; }\n\n@endif # MC68040\n\n:fasin.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0c) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = asin(f_mem);}\n:fasin\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0c\t\t{ fdst = asin(fsrc);}\n\n:fatan.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0a) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = atan(f_mem);}\n:fatan\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0a\t\t{ fdst = atan(fsrc);}\n\n:fatanh.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0d) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = tanh(f_mem);}\n:fatanh\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0d\t\t{ fdst = tanh(fsrc);}\n\n:fb^fcc^\".w\" addr16\t\t\tis fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=0 & fcc; addr16\t{ if (fcc) goto addr16; }\n:fb^fcc^\".l\" addr32 \t\t\tis fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=1 & fcc; addr32\t{ if (fcc) goto addr32; }\n\n:fcmp.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x38) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { local result = fdst f- f_mem; resflags_fp(result); }\n:fcmp\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x38\t{ local result=fdst f- fsrc; resflags_fp(result); }\n\n:fcos.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1d) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = cos(f_mem);}\n:fcos\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1d\t{ fdst = cos(fsrc);}\n\n:fcosh.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x19) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = cosh(f_mem);}\n:fcosh\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x19\t{ fdst = cos(fsrc);}\n\n:fdb^fcc fcnt, addr16\t\tis fop=15 & $(FP_FCOP) & f0308=9 & fcnt; f0615=0 & fcc; addr16\n { if (fcc) goto inst_next;\n fcnt = fcnt - 1;\n local tst = (fcnt == -1);\n if (!tst) goto addr16;\n }\n\n:fdiv.^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x20) ... & f_mem\n\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f/ f_mem;}\n:fdiv fsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x20\t{ fdst = fdst f/ fsrc;}\n\n@ifdef MC68040\n\nfdivrnd: \"s\"\tis fdst & fopmode=0x60\t\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfdivrnd: \"d\"\tis fdst & fopmode=0x64\t\t{ tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fdivrnd^\"div.\"^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & fprec & (fopmode=0x60 | fopmode=0x64)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f/ f_mem; build fdivrnd; }\n:f^fdivrnd^\"div\" fsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fdivrnd & (fopmode=0x60 | fopmode=0x64)\t{ fdst = fdst f/ fsrc; build fdivrnd; }\n\n@endif # MC68040\n\n\n:fetox.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec& fopmode=0x10) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fetox(f_mem); }\n:fetox\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x10\t\t{ fdst = fetox(fsrc); }\n\n:fetoxm1.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x08) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fetoxm1(f_mem); }\n:fetoxm1\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x08\t\t{ fdst = fetoxm1(fsrc); }\n\n:fgetexp.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst &fprec & fopmode=0x1e) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fgetexp(f_mem); }\n:fgetexp\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1e\t\t{ fdst = fgetexp(fsrc); }\n\n:fgetman.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1f) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fgetman(f_mem); }\n:fgetman\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f\t\t{ fdst = fgetman(fsrc); }\n\n:fint.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x01) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fint(f_mem, FPCR); }\n:fint\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01\t\t{ fdst = fint(fsrc); }\n\n:fintrz.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x03) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(f_mem); fdst = int2float(tmp); }\n:fintrz\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03\t{ tmp:8 = trunc(fsrc); fdst = int2float(tmp); }\n\n:flog10.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x15) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = flog10(f_mem); }\n:flog10\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x15\t\t{ fdst = flog10(fsrc); }\n\n:flog2.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x16) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = flog2(f_mem); }\n:flog2\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x16\t\t{ fdst = flog2(fsrc); }\n\n:flogn.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x14) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = flogn(f_mem); }\n:flogn\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x14\t\t{ fdst = flogn(fsrc); }\n\n:flognp1.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x06) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = flognp1(f_mem); }\n:flognp1\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x06\t\t{ fdst = flognp1(fsrc); }\n\n:fmod.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0& fdst & fprec & fopmode=0x21) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fmod(f_mem); }\n:fmod\t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21\t\t{ fdst = fmod(fsrc); }\n\n:fmove.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x00) ... & f_mem\n\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = f_mem; resflags_fp(fdst); }\n\n:fmove\t\tfsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x00\n\t\t\t\t\t\t\t\t\t{ fdst = fsrc; resflags_fp(fdst); }\n\n@ifdef MC68040\n\nfmovernd: \"s\" is fdst & fopmode=0x40 { tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfmovernd: \"d\" is fdst & fopmode=0x44 { tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fmovernd^\"move.\"^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & fprec & (fopmode=0x40 | fopmode=0x44)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = f_mem; build fmovernd; }\n:f^fmovernd^\"move\" \t\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fmovernd & (fopmode=0x40 | fopmode=0x44)\n\t\t\t\t\t\t\t\t\t\t{ fdst = fsrc; build fmovernd; }\n\n@endif # MC68040\n\n#TODO: Documented decoding (w/ coprocess id in bits 10-12) conflicts with ASL instruction and differs from Instruction Format Summary\n# Convert float in fdst to an int and then move to byte\n:fmove.b fdst, e2b\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=6; e2b\n [ savmod2=savmod1; regtsan=regtfan; ] { e2b = trunc(fdst); }\n\n# Convert float in fdst to an int and then move to word 16-bits\n:fmove.w fdst, e2w\t\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=4; e2w\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2w = trunc(fdst); }\n\n# Convert float in fdst to an int and then move to long 32-bits\n:fmove.l fdst, e2l\t\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=0; e2l\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2l = trunc(fdst); }\n\n# destination is single float (32-bits)\n:fmove.s fdst, e2l\t\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=1; e2l\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2l = float2float(fdst); resflags_fp(e2l); }\n\n:fmove.^fprec fdst, e2x\t\tis op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_X); e2x\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2x = float2float(fdst); resflags_fp(e2x); }\n\n# Double float (64-bits)\n:fmove.^fprec fdst, e2d\t\tis op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); }\n\nkfact: {\"#\"fkfactor}\tis fkfactor & $(FPREC_P) { local tmp:4 = fkfactor; export *[const]:4 tmp; }\nkfact: {fkfacreg}\tis fkfacreg & $(FPREC_Pd) { export fkfacreg; }\n\n:fmove.p fdst, e2l kfact\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & kfact & $(FPREC_P); e2l\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, kfact); }\n\n:fmove.p fdst, e2l kfact\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & kfact & $(FPREC_Pd); e2l\n\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, kfact); }\n\n#Special case for FMOVEM.L and must occur before it within this file\n:fmove.l\te2l, FPCR\tis op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=0 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPCR = e2l; }\n:fmove.l\tFPCR, e2l\tis op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=1 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPCR; }\n:fmove.l\te2l, FPSR\tis op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPSR; f1415=2 & fdr=0 & f1012=2 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPSR = e2l; }\n:fmove.l\tFPSR, e2l\tis op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPSR; f1415=2 & fdr=1 & f1012=2 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPSR; }\n:fmove.l\te2l, FPIAR\tis op=15 & $(FP_COP) & op68=0 & FPIAR; f1415=2 & fdr=0 & f1012=1 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPIAR = e2l; }\n:fmove.l\tFPIAR, e2l\tis op=15 & $(FP_COP) & op68=0 & FPIAR; f1415=2 & fdr=1 & f1012=1 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPIAR; }\n\n#\n# TODO: this table should contain all the rom constants\nromconst: is fromoffset=0x00\t{ tmp1:8 = 0x400921FB4D12D84A:8; tmp:10 = float2float(tmp1); export tmp; } # pi=3.14...\nromconst: is fromoffset=0x0f\t{ tmp1:8 = 0x0:8; tmp:10 = int2float(tmp1); export tmp; }\nromconst: is fromoffset=0x32 { tmp1:8 = 0x01:8; tmp:10 = int2float(tmp1); export tmp; }\nromconst: is fromoffset=0x33 { tmp1:8 = 10:8; tmp:10 = int2float(tmp1); export tmp; }\nromconst: is fromoffset=0x34 { tmp1:8 = 100:8; tmp:10 = int2float(tmp1); export tmp; }\nromconst: is fromoffset=0x35 { tmp1:8 = 10000:8; tmp:10 = int2float(tmp1); export tmp; }\nromconst: is fromoffset=0x36 { tmp1:8 = 100000000:8; tmp:10 = int2float(tmp1); export tmp; }\nromconst: is fromoffset\t{ tmp1:8 = 0x0:8; tmp:10 = int2float(tmp1); export tmp; }\n\n:fmovecr.x \"#\"^fromoffset, fdst is op=15 & $(FP_COP) & op08=0; f1015=0x17 & fdst & fromoffset & romconst { fdst = romconst; }\n\n# Memory to Floating point register, forward direction\nm2fpF7: FP0\t\t\t\tis FP0 & frlist7=1\t\t\t{ FP0 = *movemptr; movemptr = movemptr + 12; }\nm2fpF7:\t\t\t\t\t\tis frlist7=0\t\t\t\t{ }\nm2fpF6: m2fpF7\" \"FP1\t\tis FP1 & frlist6=1 & m2fpF7\t{ FP1 = *movemptr; movemptr = movemptr + 12; }\nm2fpF6: m2fpF7\t\t\tis frlist6=0 & m2fpF7\t\t{ }\nm2fpF5: m2fpF6\" \"FP2\t\tis FP2 & frlist5=1 & m2fpF6\t{ FP2 = *movemptr; movemptr = movemptr + 12; }\nm2fpF5: m2fpF6\t\t\tis frlist5=0 & m2fpF6\t\t{ }\nm2fpF4: m2fpF5\" \"FP3\t\tis FP3 & frlist4=1 & m2fpF5\t{ FP3 = *movemptr; movemptr = movemptr + 12; }\nm2fpF4: m2fpF5\t\t\tis frlist4=0 & m2fpF5\t\t{ }\nm2fpF3: m2fpF4\" \"FP4\t\tis FP4 & frlist3=1 & m2fpF4\t{ FP4 = *movemptr; movemptr = movemptr + 12; }\nm2fpF3: m2fpF4\t\t\tis frlist3=0 & m2fpF4\t\t{ }\nm2fpF2: m2fpF3\" \"FP5\t\tis FP5 & frlist2=1 & m2fpF3\t{ FP5 = *movemptr; movemptr = movemptr + 12; }\nm2fpF2: m2fpF3\t\t\tis frlist2=0 & m2fpF3\t\t{ }\nm2fpF1: m2fpF2\" \"FP6\t\tis FP6 & frlist1=1 & m2fpF2\t{ FP6 = *movemptr; movemptr = movemptr + 12; }\nm2fpF1: m2fpF2\t\t\tis frlist1=0 & m2fpF2\t\t{ }\nm2fpF0: { m2fpF1\" \"FP7 }\tis FP7 & frlist0=1 & m2fpF1\t{ FP7 = *movemptr; movemptr = movemptr + 12; }\nm2fpF0: { m2fpF1 }\t\t\tis frlist0=0 & m2fpF1\t\t{ }\n\n# Memory to Floating point register, reverse direction\nm2fpR7: FP7\t\t\t\tis FP7 & frlist7=1\t\t\t{ movemptr = movemptr - 12; FP7 = *movemptr; }\nm2fpR7:\t\t\t\t\t\tis frlist7=0\t\t\t\t{ }\nm2fpR6: m2fpR7\" \"FP6\t\tis FP6 & frlist6=1 & m2fpR7\t{ movemptr = movemptr - 12; FP6 = *movemptr; }\nm2fpR6: m2fpR7\t\t\tis frlist6=0 & m2fpR7\t\t{ }\nm2fpR5: m2fpR6\" \"FP5\t\tis FP5 & frlist5=1 & m2fpR6\t{ movemptr = movemptr - 12; FP5 = *movemptr; }\nm2fpR5: m2fpR6\t\t\tis frlist5=0 & m2fpR6\t\t{ }\nm2fpR4: m2fpR5\" \"FP4\t\tis FP4 & frlist4=1 & m2fpR5\t{ movemptr = movemptr - 12; FP4 = *movemptr; }\nm2fpR4: m2fpR5\t\t\tis frlist4=0 & m2fpR5\t\t{ }\nm2fpR3: m2fpR4\" \"FP3\t\tis FP3 & frlist3=1 & m2fpR4\t{ movemptr = movemptr - 12; FP3 = *movemptr; }\nm2fpR3: m2fpR4\t\t\tis frlist3=0 & m2fpR4\t\t{ }\nm2fpR2: m2fpR3\" \"FP2\t\tis FP2 & frlist2=1 & m2fpR3\t{ movemptr = movemptr - 12; FP2 = *movemptr; }\nm2fpR2: m2fpR3\t\t\tis frlist2=0 & m2fpR3\t\t{ }\nm2fpR1: m2fpR2\" \"FP1\t\tis FP1 & frlist1=1 & m2fpR2\t{ movemptr = movemptr - 12; FP1 = *movemptr; }\nm2fpR1: m2fpR2\t\t\tis frlist1=0 & m2fpR2\t\t{ }\nm2fpR0: { m2fpR1\" \"FP0 }\tis FP0 & frlist0=1 & m2fpR1\t{ movemptr = movemptr - 12; FP0 = *movemptr; }\nm2fpR0: { m2fpR1 }\t\t\tis frlist0=0 & m2fpR1\t\t{ }\n\n\n# Floating point register to Memory, forward direction\nfp2mF7: FP0\t\t\t\tis FP0 & frlist7=1\t\t\t{ *movemptr = FP0; movemptr = movemptr + 12; }\nfp2mF7:\t\t\t\t\t\tis frlist7=0\t\t\t\t{ }\nfp2mF6: fp2mF7\" \"FP1\t\tis FP1 & frlist6=1 & fp2mF7\t{ *movemptr = FP1; movemptr = movemptr + 12; }\nfp2mF6: fp2mF7\t\t\tis frlist6=0 & fp2mF7\t\t{ }\nfp2mF5: fp2mF6\" \"FP2\t\tis FP2 & frlist5=1 & fp2mF6\t{ *movemptr = FP2; movemptr = movemptr + 12; }\nfp2mF5: fp2mF6\t\t\tis frlist5=0 & fp2mF6\t\t{ }\nfp2mF4: fp2mF5\" \"FP3\t\tis FP3 & frlist4=1 & fp2mF5\t{ *movemptr = FP3; movemptr = movemptr + 12; }\nfp2mF4: fp2mF5\t\t\tis frlist4=0 & fp2mF5\t\t{ }\nfp2mF3: fp2mF4\" \"FP4\t\tis FP4 & frlist3=1 & fp2mF4\t{ *movemptr = FP4; movemptr = movemptr + 12; }\nfp2mF3: fp2mF4\t\t\tis frlist3=0 & fp2mF4\t\t{ }\nfp2mF2: fp2mF3\" \"FP5\t\tis FP5 & frlist2=1 & fp2mF3\t{ *movemptr = FP5; movemptr = movemptr + 12; }\nfp2mF2: fp2mF3\t\t\tis frlist2=0 & fp2mF3\t\t{ }\nfp2mF1: fp2mF2\" \"FP6\t\tis FP6 & frlist1=1 & fp2mF2\t{ *movemptr = FP6; movemptr = movemptr + 12; }\nfp2mF1: fp2mF2\t\t\tis frlist1=0 & fp2mF2\t\t{ }\nfp2mF0: { fp2mF1\" \"FP7 }\tis FP7 & frlist0=1 & fp2mF1\t{ *movemptr = FP7; movemptr = movemptr + 12; }\nfp2mF0: { fp2mF1 }\t\t\tis frlist0=0 & fp2mF1\t\t{ }\n\n# Floating point register to Memory, reverse direction\nfp2mR7: FP7\t\t\t\tis FP7 & frlist7=1\t\t\t{ movemptr = movemptr - 12; *movemptr = FP7; }\nfp2mR7:\t\t\t\t\t\tis frlist7=0\t\t\t\t{ }\nfp2mR6: fp2mR7\" \"FP6\t\tis FP6 & frlist6=1 & fp2mR7\t{ movemptr = movemptr - 12; *movemptr = FP6; }\nfp2mR6: fp2mR7\t\t\tis frlist6=0 & fp2mR7\t\t{ }\nfp2mR5: fp2mR6\" \"FP5\t\tis FP5 & frlist5=1 & fp2mR6\t{ movemptr = movemptr - 12; *movemptr = FP5; }\nfp2mR5: fp2mR6\t\t\tis frlist5=0 & fp2mR6\t\t{ }\nfp2mR4: fp2mR5\" \"FP4\t\tis FP4 & frlist4=1 & fp2mR5\t{ movemptr = movemptr - 12; *movemptr = FP4; }\nfp2mR4: fp2mR5\t\t\tis frlist4=0 & fp2mR5\t\t{ }\nfp2mR3: fp2mR4\" \"FP3\t\tis FP3 & frlist3=1 & fp2mR4\t{ movemptr = movemptr - 12; *movemptr = FP3; }\nfp2mR3: fp2mR4\t\t\tis frlist3=0 & fp2mR4\t\t{ }\nfp2mR2: fp2mR3\" \"FP2\t\tis FP2 & frlist2=1 & fp2mR3\t{ movemptr = movemptr - 12; *movemptr = FP2; }\nfp2mR2: fp2mR3\t\t\tis frlist2=0 & fp2mR3\t\t{ }\nfp2mR1: fp2mR2\" \"FP1\t\tis FP1 & frlist1=1 & fp2mR2\t{ movemptr = movemptr - 12; *movemptr = FP1; }\nfp2mR1: fp2mR2\t\t\tis frlist1=0 & fp2mR2\t\t{ }\nfp2mR0: { fp2mR1\" \"FP0 }\tis FP0 & frlist0=1 & fp2mR1\t{ movemptr = movemptr - 12; *movemptr = FP0; }\nfp2mR0: { fp2mR1 }\t\t\tis frlist0=0 & fp2mR1\t\t{ }\n\n\n# NB- when doing preincrement or postincrement modes, the movemptr that is set in e2x is used as the starting address for the move.\n# Then at completion of the move, the reg is set to the movemptr.\n# Note that movem (non-floating point) does this slightly differently)\n#\n# Not a predecrement or postincrement\n:fmovem.x fp2mF0, e2x is op=15 & $(FP_COP) & op68=0 & (mode=2 | mode=5 | mode=6 | mode=7);\n\t\t\t\t\t\t\t\tf1415=3 & fdr=1 & f0810=0 & fp2mF0 & flmode_t=0 & flmode_m=1; e2x\n [ savmod2=savmod1; regtsan=regtfan; ]\n { build fp2mF0; }\n\n# When mode=3 it's a postincrement\n:fmovem.x fp2mF0, e2x is regan & op=15 & $(FP_COP) & op68=0 & mode=3; f1415=3 & fdr=1 & f0810=0 & fp2mF0 & flmode_t=0 & flmode_m=1; e2x\n [ savmod2=savmod1; regtsan=regtfan; ]\n { build fp2mF0; regan = movemptr; }\n\n# When mode=4 it's a predecrement, and also must update the address register with the new address\n:fmovem.x fp2mR0, e2x is regan & op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=1 & f0810=0 & fp2mR0 & flmode_t=0 & flmode_m=0; e2x\n [ savmod2=savmod1; regtsan=regtfan; ]\n { build fp2mR0; regan = movemptr; }\n\n# Not a predecrement or postincrement\n:fmovem.x e2x, m2fpF0 is op=15 & $(FP_COP) & op68=0 & (mode=2 | mode=5 | mode=6 | mode=7);\n\t\t\t\t\t\tf1415=3 & fdr=0 & f0810=0 & m2fpF0 & flmode_t=0 & flmode_m=1; e2x\n [ savmod2=savmod1; regtsan=regtfan; ]\n { build m2fpF0; }\n\n# When mode=3 it's a postincrement\n:fmovem.x e2x, m2fpF0 is regan & op=15 & $(FP_COP) & op68=0 & mode=3;\n f1415=3 & fdr=0 & f0810=0 & m2fpF0 & flmode_t=0 & flmode_m=1; e2x\n [ savmod2=savmod1; regtsan=regtfan; ]\n { build m2fpF0; regan = movemptr; }\n\n# When mode=4 it's a predecrement, and also must update the address register with the new address\n:fmovem.x e2x, m2fpR0 is regan & op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=0 & f0810=0 & m2fpR0 & flmode_t=0 & flmode_m=0; e2x\n [ savmod2=savmod1; regtsan=regtfan; ]\n { build m2fpR0; regan = movemptr; }\n\ndefine pcodeop fmovem;\n# TODO: Pcode for dynamic register mask is PITA\n:fmovem.x fldynreg, e2l\tis op=15 & $(FP_COP) & op68=0 & $(POSTINC_CTL_ADDR_MODES); f1415=3 & fdr=1 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] { fmovem(e2l,fldynreg); }\n:fmovem.x fldynreg, e2l\tis op=15 & $(FP_COP) & op68=0 & $(PREDEC_CTL_ADDR_MODES); f1415=3 & fdr=1 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { fmovem(e2l,fldynreg); }\n\n:fmovem.x e2l, fldynreg\tis op=15 & $(FP_COP) & op68=0 & $(POSTINC_CTL_ADDR_MODES); f1415=3 & fdr=0 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] { fmovem(e2l,fldynreg); }\n:fmovem.x e2l, fldynreg\tis op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=0 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { fmovem(e2l,fldynreg); }\n\n# Memory to Floating point control register\nm2fpC2: FPCR\t\t\t\tis FPCR & f12=1\t\t\t\t{ FPCR = *movemptr; movemptr = movemptr + 12; }\nm2fpC2: \t\t\t\t\tis f12=0\t\t\t\t\t{ }\nm2fpC1: m2fpC2\" \"FPSR\t\tis FPSR & f11=1 & m2fpC2\t{ FPSR = *movemptr; movemptr = movemptr + 12; }\nm2fpC1: m2fpC2\t\t\tis f11=0 & m2fpC2\t\t\t{ }\nm2fpC0: { m2fpC1\" \"FPIAR }\tis FPIAR & f10=1 & m2fpC1\t{ FPIAR = *movemptr; movemptr = movemptr + 12; }\nm2fpC0: { m2fpC1 }\t\t\tis f10=0 & m2fpC1\t\t\t{ }\n\n# Floating point control register to Memory\nfp2mC2: FPCR\t\t\t\tis FPCR & f12=1\t\t\t\t{ *movemptr = FPCR; movemptr = movemptr + 12; }\nfp2mC2: \t\t\t\t\tis f12=0\t\t\t\t\t{ }\nfp2mC1: fp2mC2\" \"FPSR\t\tis FPSR & f11=1 & fp2mC2\t{ *movemptr = FPSR; movemptr = movemptr + 12; }\nfp2mC1: fp2mC2\t\t\tis f11=0 & fp2mC2\t\t\t{ }\nfp2mC0: { fp2mC1\" \"FPIAR }\tis FPIAR & f10=1 & fp2mC1\t{ *movemptr = FPIAR; movemptr = movemptr + 12; }\nfp2mC0: { fp2mC1 }\t\t\tis f10=0 & fp2mC1\t\t\t{ }\n\n:fmovem.l fp2mC0, e2l\t\tis op=15 & $(FP_COP) & $(MEM_ALTER_ADDR_MODES) & op68=0; f1315=5 & f0009=0 & fp2mC0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { movemptr = e2l; build fp2mC0; }\n:fmovem.l e2l, m2fpC0\t\tis op=15 & $(FP_COP) & $(MEM_ALTER_ADDR_MODES) & op68=0; f1315=4 & f0009=0 & m2fpC0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { movemptr = e2l; build m2fpC0; }\n\n:fmul.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x23) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* f_mem; }\n:fmul fsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x23\n\t\t\t\t\t\t\t\t\t\t{fdst = fdst f* fsrc; }\n@ifdef MC68040\n\nfmulrnd: \"s\"\tis fdst & fopmode=0x63\t\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfmulrnd: \"d\"\tis fdst & fopmode=0x67\t\t{ tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fmulrnd^\"mul.\"^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fmulrnd & (fopmode=0x63 | fopmode=0x67)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* f_mem; build fmulrnd; }\n\n:f^fmulrnd^\"mul\" fsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fmulrnd & (fopmode=0x63 | fopmode=0x67)\n\t\t\t\t\t\t\t\t\t\t{fdst = fdst f* fsrc; build fmulrnd; }\n@endif # MC68040\n\n:fneg.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1a) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = f- f_mem; }\n:fneg\t\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1a\n\t\t\t\t\t\t\t\t\t\t{ fdst = f- fsrc; }\n@ifdef MC68040\n\nfnegrnd: \"s\"\tis fdst & fopmode=0x5a\t\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfnegrnd: \"d\"\tis fdst & fopmode=0x5e\t\t{ tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fnegrnd^\"neg.\"^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fnegrnd & (fopmode=0x5a | fopmode=0x5e)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = f- f_mem; build fnegrnd; }\n:f^fnegrnd^\"neg\"\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fnegrnd & (fopmode=0x5a | fopmode=0x5e)\n\t\t\t\t\t\t\t\t\t\t{ fdst = f- fsrc; build fnegrnd; }\n@endif # MC68040\n\n:fnop\t\t\t\t\t\t\tis fop=15 & $(FP_FCOP) & f0008=0x080; fword=0 { }\n\n:frem.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x25) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = frem(f_mem); }\n:frem\t\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x25\n\t\t\t\t\t\t\t\t\t\t{ fdst = frem(fsrc); }\n\n:frestore\t\teal\t\t\tis (op=15 & $(FP_COP) & op68=5 & $(POSTINC_CTL_ADDR_MODES))... & eal { restoreFPUStateFrame(eal); }\n\n:fsave\t\t\teal\t\t\tis (op=15 & $(FP_COP) & op68=4 & $(PREDEC_CTL_ADDR_MODES))... & eal { saveFPUStateFrame(eal); }\n\n:fscale.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x26) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fscale(f_mem); }\n:fscale\t\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x26\n\t\t\t\t\t\t\t\t\t\t{ fdst = fscale(fsrc); }\n\n# Need to set the destination to all 1s if the condition is true, else set to 0\n#\n:fs^fcc e2b\t\tis op=15 & $(FP_COP) & op68=1 & $(DAT_ALTER_ADDR_MODES); f0615=0 & fcc; e2b\n\t[ savmod2=savmod1; regtsan=regtfan; ]\n\t{ e2b = fcc * 0xff; }\n\n:fsgldiv.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x24) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { tmp:4 = float2float(fdst f/ f_mem); fdst = float2float(tmp); }\n:fsgldiv\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x24\n\t\t\t\t\t\t\t\t\t\t{ tmp:4 = float2float(fdst f/ fsrc); fdst = float2float(tmp); }\n\n# Floating point single precision multiply\n# TODO: set condition flags\n:fsglmul.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x27) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] {tmp:4 = float2float(fdst f* f_mem); fdst = float2float(tmp); }\n:fsglmul\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x27\n\t\t\t\t\t\t\t\t\t\t{tmp:4 = float2float(fdst f* fsrc); fdst = float2float(tmp); }\n\n:fsin.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0e) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = sin(f_mem); }\n:fsin\t\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0e\n\t\t\t\t\t\t\t\t\t\t{ fdst = sin(fsrc); }\n\n:fsincos.^fprec\tf_mem, fdcos, fdsin\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & fprec & f0306=6) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { tmp:10 = f_mem; fdsin = sin(tmp); fdcos = cos(tmp); }\n:fsincos.x\t\tfsrc, fdcos, fdsin\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdcos & fdsin & f0306=6\n\t\t\t\t\t\t\t\t\t\t{ tmp:10 = fsrc; fdsin = sin(tmp); fdcos = cos(tmp); }\n\n:fsinh.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x02) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = sinh(f_mem); }\n:fsinh\t\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x02\n\t\t\t\t\t\t\t\t\t\t{ fdst = sinh(fsrc); }\n\n:fsqrt.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x04) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = sqrt(f_mem); }\n:fsqrt.x fsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x04\n\t\t\t\t\t\t\t\t\t\t{ fdst = sqrt(fsrc); }\n@ifdef MC68040\n\nfsqrtrnd: \"s\"\tis fdst & fopmode=0x41\t\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfsqrtrnd: \"d\"\tis fdst & fopmode=0x45\t\t{ tmp:8 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fsqrtrnd^\"sqrt.\"^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fsqrtrnd & (fopmode=0x41 | fopmode=0x45)) ... & f_mem \n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = sqrt(f_mem); build fsqrtrnd; }\n:f^fsqrtrnd^\"sqrt.x\"\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fsqrtrnd & (fopmode=0x41 | fopmode=0x45)\n\t\t\t\t\t\t\t\t\t\t{ fdst = sqrt(fsrc); build fsqrtrnd; }\n@endif # MC68040\n\n:fsub.^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x28) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f- f_mem; }\n:fsub.x fsrc, fdst\t\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x28\n\t\t\t\t\t\t\t\t\t\t{ fdst = fdst f- fsrc; }\n\n@ifdef MC68040\n\nfsubrnd: \"s\"\tis fdst & fopmode=0x68\t\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\nfsubrnd: \"d\"\tis fdst & fopmode=0x6c\t\t{ tmp:4 = float2float(fdst); fdst = float2float(tmp); }\n\n:f^fsubrnd^\"sub.\"^fprec f_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & fprec & (fopmode=0x68 | fopmode=0x6c)) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f- f_mem; build fsubrnd; }\n:f^fsubrnd^\"sub.x\" fsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fsubrnd & (fopmode=0x68 | fopmode=0x6c)\n\t\t\t\t\t\t\t\t\t\t{ fdst = fdst f- fsrc; build fsubrnd; }\n\n@endif # MC68040\n\n:ftan.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0f) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = tan(f_mem); }\n:ftan.x\t\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0f\n\t\t\t\t\t\t\t\t\t\t{ fdst = tan(fsrc); }\n\n:ftanh.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x09) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = tanh(f_mem); }\n:ftanh.x\t\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x09\n\t\t\t\t\t\t\t\t\t\t{ fdst = tanh(fsrc); }\n\n:ftentox.^fprec\tf_mem, fdst\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x12) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = ftentox(f_mem); }\n:ftentox.x\tfsrc, fdst\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x12\n\t\t\t\t\t\t\t\t\t\t { fdst = ftentox(fsrc); }\n\n:ftrap^fcc const16\t\tis fop=15 & $(FP_FCOP) & f0308=0xf & fmode=2; f0615=0 & fcc; const16\t{ if (!fcc) goto inst_next; ftrap(const16); }\n:ftrap^fcc\tconst32\t\tis fop=15 & $(FP_FCOP) & f0308=0xf & fmode=3; f0615=0 & fcc; const32\t{ if (!fcc) goto inst_next; ftrap(const32); }\n:ftrap^fcc \t\t\tis fop=15 & $(FP_FCOP) & f0308=0xf & fmode=4; f0615=0 & fcc\t\t\t\t{ if (!fcc) goto inst_next; ftrap(); }\n\n:ftst.^fprec\tf_mem\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x3a) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { tmp:10 = f_mem; resflags_fp(tmp); }\n:ftst.x\t\t\tfsrc\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x3a\n\t\t\t\t\t\t\t\t\t\t{ tmp:10 = fsrc; resflags_fp(tmp); }\n\n:ftwotox.^fprec\tf_mem, fdst\t\tis op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x11) ... & f_mem\n\t\t\t\t\t\t\t\t\t\t[ savmod2=savmod1; regtsan=regtfan; ] { fdst = ftwotox(f_mem); }\n:ftwotox.x\t\tfsrc, fdst\t\tis op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x11\n\t\t\t\t\t\t\t\t\t\t{ fdst = ftwotox(fsrc); }\n\n\n@ifdef COLDFIRE\n\nmacregy: reg03ywl\tis reg03ywl; IS=0\t{ export reg03ywl; }\nmacregy: reg03ywu\tis reg03ywu; IS=1\t{ export reg03ywu; }\nmacregx: reg9dnl\tis reg9dnl & op6=0; bs=0\t{ export reg9dnl; }\nmacregx: reg9dnu\tis reg9dnu & op6=0; bs=1\t{ export reg9dnu; }\nmacregx: reg9anl\tis reg9anl & op6=1; bs=0\t{ export reg9anl; }\nmacregx: reg9anu\tis reg9anu & op6=1; bs=1\t{ export reg9anu; }\nmacrw: reg9dn\t\tis reg9dn & op6=0 { export reg9dn; }\nmacrw: reg9an\t\tis reg9an & op6=1 { export reg9an; }\n\nmacregy_e: ereg03y\tis ereg03y\t{ export ereg03y; }\nmacregyl: reg03yl\tis reg03yl & IS=0\t{ export reg03yl; }\nmacregyl: reg03yu\tis reg03yu & IS=1\t{ export reg03yu; }\nmacregxl: reg12xwl\tis reg12xwl & bs=0\t{ export reg12xwl; }\nmacregxl: reg12xwu\tis reg12xwu & bs=1\t{ export reg12xwu; }\n\n\nscalefactor: \"\"\t\t\tis sfact=0\t{ export 0:1; }\nscalefactor: \"<<1\"\t\tis sfact=1\t{ export 1:1; }\nscalefactor: \">>1\"\t\tis sfact=3\t{ export 2:1; }\n\naccreg: ACC0\tis ACC0 & acclsb=0 ; accmsb=0 \t\t{ export ACC0; }\naccreg: ACC1\tis ACC1 & acclsb=1 ; accmsb=0 \t\t{ export ACC1; }\naccreg: ACC2\tis ACC2 & acclsb=0 ; accmsb=1 \t\t{ export ACC2; }\naccreg: ACC3\tis ACC3 & acclsb=1 ; accmsb=1 \t\t{ export ACC3; }\n\n\n:ff1 regdn\t\t\t\t\t\t\tis reg315=0x98 & regdn {\n\tregdn = lzcount(regdn);\n\tVF = 0;\n\tCF = 0;\n\tresflags(regdn);\n}\n\n# MAC effective address table\n # size=long\nm_eal: (regan) is mode=2 & regan\t\t\t{ export *:4 regan; }\nm_eal: (regan)+ is mode=3 & regan\t\t\t{ local tmp = regan; regan = regan + 4; export *:4 tmp; }\nm_eal: -(regan) is mode=4 & regan\t\t\t{ regan = regan - 4; export *:4 regan; }\nm_eal: (d16,regan) is mode=5 & regan; d16\t\t{ local tmp = regan + d16; export *:4 tmp; }\n\n:maaac.l reg03y, reg9dn^scalefactor, accreg, accw\tis (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...\n{\n local tmp = reg03y * reg9dn;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n accw = accw + tmp;\n}\n:maaac.l reg03y, reg9an^scalefactor, accreg, accw\tis (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...\n{\n local tmp = reg03y * reg9an;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n accw = accw + tmp;\n}\n\n:maaac.w macregy, macregx^scalefactor, accreg, accw\tis (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ...\n{\n local tmp = macregy * macregx;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + sext(tmp);\n accw = accw + sext(tmp);\n}\n\n:mac.l reg03y, reg9dn^scalefactor, accreg\tis (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ...\n{\n local tmp = reg03y * reg9dn;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n}\n:mac.l reg03y, reg9an^scalefactor, accreg\tis (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ...\n{\n local tmp = reg03y * reg9an;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n}\n\n:mac.w macregy, macregx^scalefactor, accreg\tis (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ...\n{\n local tmp = macregy * macregx;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + sext(tmp);\n}\n\n#mac with load\n:mac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg\tis ((op=10 & macrw & op8=0 ; macregxl & fbit=0 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal\n{\n local tmp = macregyl * macregxl;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + sext(tmp);\n macrw = m_eal;\n}\n\n:mac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg\tis ((op=10 & macrw & op6=0 & op8=0 ; reg12x & fbit=0 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal\n{\n local tmp = macregy_e * reg12x;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n macrw = m_eal;\n}\n\n:masac.l reg03y, reg9dn^scalefactor, accreg, accw\tis (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...\n{\n local tmp = reg03y * reg9dn;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n accw = accw - tmp;\n}\n:masac.l reg03y, reg9an^scalefactor, accreg, accw\tis (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...\n{\n local tmp = reg03y * reg9an;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + tmp;\n accw = accw - tmp;\n}\n\n:masac.w macregy, macregx^scalefactor, accreg, accw\tis (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ...\n{\n local tmp = macregy * macregx;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg + sext(tmp);\n accw = accw - sext(tmp);\n}\n\nmoveaccreg: ACC0 is ACC0 & op0910=0 { export ACC0; }\nmoveaccreg: ACC1 is ACC1 & op0910=1 { export ACC1; }\nmoveaccreg: ACC2 is ACC2 & op0910=2 { export ACC2; }\nmoveaccreg: ACC3 is ACC3 & op0910=3 { export ACC3; }\n\nmoveaccreg2: ACC0 is ACC0 & op01=0 { export ACC0; }\nmoveaccreg2: ACC1 is ACC1 & op01=1 { export ACC1; }\nmoveaccreg2: ACC2 is ACC2 & op01=2 { export ACC2; }\nmoveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; }\n\n:move.l moveaccreg, reg03y is op=0b1010 & op11=0 & moveaccreg & op8=1 & op47=0b1000 & reg03y { reg03y = moveaccreg; }\n\n:move.l ACCext01, eal is (op=0b1010 & op811=0b1011 & op67=0 & ACCext01 & (mode=0 | mode=1 | mode=7)) ... & eal { ACCext01 = eal; }\n:move.l ACCext23, eal is (op=0b1010 & op811=0b1111 & op67=0 & ACCext23 & (mode=0 | mode=1 | mode=7)) ... & eal { ACCext23 = eal; }\n\n:move.l moveaccreg, eal is (op=0b1010 & op11=0 & moveaccreg & op8=1 & op67=0 & (mode=0 | mode=1 | mode=7)) ... & eal { moveaccreg = eal; }\n\n:move.l moveaccreg, moveaccreg2 is op=0b1010 & op11=0 & moveaccreg & op8=1 & op47=1 & moveaccreg2 { moveaccreg2 = moveaccreg; }\n\n:move.l MACSR, reg03y\t\tis op=0b1010 & op811=0b1001 & op47=0b1000 & MACSR & reg03y\t{ reg03y = MACSR; }\n:move.l ACCext01, reg03y\tis op=0b1010 & op811=0b1011 & op47=0b1000 & ACCext01 & reg03y\t{ reg03y = ACCext01; }\n:move.l ACCext23, reg03y\tis op=0b1010 & op811=0b1111 & op47=0b1000 & ACCext23 & reg03y\t{ reg03y = ACCext23; }\n\n:move.l MASK, reg03y\t\tis op=10 & op811=13 & op47=8 & MASK & reg03y\t{ reg03y = MASK; }\n\n:move.l MACSR, \"CCR\"\t\tis op=10 & op811=9 & op47=12 & MACSR\t\t\t{ unpackflags(MACSR); }\n\n:move.l eal, MACSR\t\t\tis (op=10 & op611=36 & MACSR & (mode=0 | mode=1 | mode=7)) ... & eal\t\t{ MACSR = eal; }\n\n:move.l eal, MASK\t\t\tis (op=10 & op611=52 & MASK & (mode=0 | mode=1 | mode=7)) ... & eal\t\t\t{ MASK = eal; }\n\n\n:msaac.l reg03y, reg9dn^scalefactor, accreg, accw\tis (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...\n{\n local tmp = reg03y * reg9dn;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n accw = accw + tmp;\n}\n\n:msaac.l reg03y, reg9an^scalefactor, accreg, accw\tis (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...\n{\n local tmp = reg03y * reg9an;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n accw = accw + tmp;\n}\n\n:msaac.w macregy, macregx^scalefactor, accreg, accw\tis (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ...\n{\n local tmp = macregy * macregx;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - sext(tmp);\n accw = accw + sext(tmp);\n}\n\n:msac.l reg03y, reg9dn^scalefactor, accreg\tis (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ...\n{\n local tmp = reg03y * reg9dn;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n}\n:msac.l reg03y, reg9an^scalefactor, accreg\tis (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ...\n{\n local tmp = reg03y * reg9an;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n}\n\n:msac.w macregy, macregx^scalefactor, accreg\tis (op=10 & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ...\n{\n local tmp = macregy * macregx;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - sext(tmp);\n}\n\n\n# MSAC with load\n\n:msac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg\tis ((op=10 & macrw & op8=0 ; macregxl & fbit=1 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal\n{\n local tmp = macregyl * macregxl;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - sext(tmp);\n macrw = m_eal;\n}\n\n:msac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg\tis ((op=10 & macrw & op8=0 ; reg12x & fbit=1 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal\n{\n local tmp = macregy_e * reg12x;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n macrw = m_eal;\n}\n\n:msaac.l reg03y, reg9dn^scalefactor, accreg, accw\tis (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...\n{\n local tmp = reg03y * reg9dn;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n accw = accw - tmp;\n}\n:mssac.l reg03y, reg9an^scalefactor, accreg, accw\tis (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...\n{\n local tmp = reg03y * reg9an;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - tmp;\n accw = accw - tmp;\n}\n\n:mssac.w macregy, macregx^scalefactor, accreg, accw\tis (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ...\n{\n local tmp = macregy * macregx;\n tmp = tmp << (scalefactor == 1);\n tmp = tmp >> (scalefactor == 2);\n accreg = accreg - sext(tmp);\n accw = accw - sext(tmp);\n}\n\n@endif\n\n} # end with : extGUARD=1\n" }, { "path": "pypcode/processors/68000/data/languages/68000_register.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t \n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/68000/data/languages/68020.slaspec", "content": "@include \"68000.sinc\"\n" }, { "path": "pypcode/processors/68000/data/languages/68030.slaspec", "content": "@define MC68030 \"\"\n@include \"68000.sinc\"\n" }, { "path": "pypcode/processors/68000/data/languages/68040.slaspec", "content": "@define MC68040 \"\"\n@include \"68000.sinc\"\n" }, { "path": "pypcode/processors/68000/data/languages/coldfire.slaspec", "content": "# Motorola's Coldfire processor\n\n@define COLDFIRE \"\"\n@define MC68040 \"\"\n\n@include \"68000.sinc\"\n" }, { "path": "pypcode/processors/68000/data/manuals/68000.idx", "content": "@M68000PRM.pdf [M68000 FAMILY Programmer's Reference Manual, 1992 (M68000PRM/AD REV.1)]\nABCD, 106\nADD, 108\nADDA, 111\nADDI, 113\nADDQ, 115\nADDX, 117\nAND, 119\nANDI, 122\nASL, 125\nASR, 126\nB, 129\nBCHG, 131\nBCLR, 134\nBFCHG, 137\nBFCLR, 139\nBFEXTS, 141\nBFEXTU, 144\nBFFFO, 147\nBFINS, 150\nBFSET, 153\nBFTST, 155\nBGND, 544\nBKPT, 157\nBRA, 159\nBSET, 160\nBSR, 163\nBTST, 165\nCALLM, 168\nCAS, 170\nCAS2, 171\nCHK, 172\nCHK2, 175\nCINV, 457\nCLR, 177\nCMP, 179\nCMPA, 181\nCMPI, 183\nCMPM, 185\nCMP2, 186\ncpB, 188\ncpDB, 189\ncpGEN, 190\ncpRESTORE, 459\ncpSAVE, 461\ncpS, 191\ncpTRAPcc, 193\nCPUSH, 462\nDB, 194\nDIVS, 196\nDIVSL, 197\nDIVU, 200\nDIVUL, 200\nEOR, 204\nEORI, 206\nEXG, 207\nEXT, 210\nEXTB, 210\nFABS, 307\nFACOS, 310\nFADD, 313\nFASIN, 316\nFATAN, 319\nFATANH, 322\nFB, 325\nFCMP, 327\nFCOS, 330\nFCOSH, 333\nFDB, 336\nFDIV, 338\nFETOX, 342\nFETOXM1, 345\nFGETEXP, 348\nFGETMAN, 351\nFINT, 354\nFINTRZ, 357\nFLOG10, 360\nFLOG2, 363\nFLOGN, 366\nFLOGNP1, 369\nFMOD, 372\nFMOVE, 375\nFMOVECR, 385\nFMOVEM, 387\nFMUL, 396\nFNEG, 400\nFNOP, 404\nFREM, 406\nFRESTORE, 465\nFSAVE, 468\nFSCALE, 409\nFS, 412\nFSGLDIV, 414\nFSGLMUL, 417\nFSIN, 420\nFSINCOS, 423\nFSINH, 427\nFSQRT, 430\nFSUB, 434\nFTAN, 438\nFTANH, 441\nFTENTOX, 444\nFTRAP, 447\nFTST, 449\nFTWOTOX, 452\nILLEGAL, 211\nJMP, 211\nJSR, 212\nLEA, 213\nLINK, 215\nLPSTOP, 545\nLSL, 217\nLSR, 217\nMOVE, 220\nMOVEA, 223\nMOVE USP, 475\nMOVE16, 230\nMOVEC, 476\nMOVEM, 232\nMOVEP, 235\nMOVEQ, 238\nMOVES, 478\nMULS, 239\nMULU, 242\nNBCD, 245\nNEG, 247\nNEGX, 249\nNOP, 251\nNOT, 252\nOR, 254\nORI, 257\nPACK, 260\nPB, 482\nPDB, 484\nPEA, 263\nPFLUSH, 486\nPFLUSHA, 492\nPFLUSHR, 495\nPFLUSHS, 492\nPLOAD, 497\nPMOVE, 501\nPRESTORE, 511\nPSAVE, 513\nPScc, 515\nPTEST, 517\nPTRAPcc, 532\nPVALID, 534\nRESET, 537\nROL, 264\nROR, 264\nROXL, 267\nROXR, 267\nRTD, 270\nRTE, 538\nRTM, 271\nRTR, 272\nRTS, 273\nSBCD, 274\nS, 276\nSTOP, 539\nSUB, 278\nSUBA, 281\nSUBI, 283\nSUBQ, 285\nSUBX, 287\nSWAP, 289\nTAS, 290\nTBLS, 546\nTBLSN, 546\nTBLU, 551\nTBLUN, 551\nTRAP, 292\nTRAPcc, 293\nTRAPV, 295\nTST, 296\nUNLK, 298\nUNPK, 299\n@CFPRM.pdf [ColdFire Family Programmer's Reference Manual, 03/2005 (CFPRM, REV.3)]\nBITREV, 95\nBYTEREV, 102\nCPUSHL, 262\nFF1, 114\nHALT, 267\nINTOUCH, 268\nMAAAC, 182\nMAC, 166\nMASAC, 188\nMOV3Q, 122\nMOVCLR, 190\nMSAAC, 207\nMSAC, 177\nMSSAC, 213\nMVS, 135\nMVZ, 136\nPULSE, 145\nREMS, 146\nREMU, 147\nSATS, 149\nSTRLDSR, 276\nTPF, 159\nWDDATA, 163\nWDEBUG, 278\n" }, { "path": "pypcode/processors/68000/data/patterns/68000_patterns.xml", "content": "\n\n \n \n \n 0x4e 0x75 \n 0x4e 0x75 0x4e 0x71 \n 0x4e 0x75 0x00 0x00 \n 0x4e 0x5e 0x4e 0x75 \n 0x4e 0x5e 0x4e 0x75 0x4e 0x71 \n 0x4e 0x5e 0x4e 0x75 0x00 0x00 \n \n \n 01001111 11101111 1111.... .......0 \n 0x4e 0x56 0x00 0x00 \n 0x4e 0x56 1111.... .......0 \n 0101...1 10001111 01001000 11010111 ........ ........ \n 0010...0 0.101111 0000.... .......0 \n 0x48 0xe7 ........ ........ \n 0x2f 0x02 \n 0x2f 0x03 \n 0x2f 0x0a \n 0x2f 0x0b \n \n \n \n \n \n \n \n 0x60 0x00 ........ ........ \n \n \n 01001111 11101111 1111.... .......0 \n 0x4e 0x56 0x00 0x00 \n 0x4e 0x56 1111.... .......0 \n \n \n \n \n \n" }, { "path": "pypcode/processors/68000/data/patterns/patternconstraints.xml", "content": "\n \n 68000_patterns.xml\n \n\n" }, { "path": "pypcode/processors/8048/data/languages/8048.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8048/data/languages/8048.ldefs", "content": "\n\n\n \n \n 8048 Microcontroller Family\n \n \n \n\n" }, { "path": "pypcode/processors/8048/data/languages/8048.pspec", "content": "\n\n\n\n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n\t \n\t \t \t\n\t \n\t \n\t \n\t \t \t\n\t \n \n \n\n" }, { "path": "pypcode/processors/8048/data/languages/8048.slaspec", "content": "# sleigh specification file for Intel 8048\n#\n# The MCS-48 family can only handle a 4kB (12 bits) address space.\n# However, some applications use a custom method to access multiple\n# banks of 4kB, such as an IO pin driving extra address lines on an\n# external ROM IC.\n#\n# To be able to parse those non-standard >4kB ROMs, this implementation\n# keeps track of 16-bit addresses by simply preserving the upper 4 bits\n# (see Addr8 and Addr12 constructors).\n#\n# To redirect the flow to a different 4kB bank, it is necessary to manually\n# set a flow override (with Fallthrough->Set) on the specific instruction.\n#\n# That cannot really be automated at this level because there is no \"standard\"\n# mechanism for external bank control.\n\n\n\n# Do not take BS into account when decompiling\n@define SINGLE_REGISTER_BANK \"\"\n\n# Treat R0-R7 as not memory mapped (implies SINGLE_REGISTER_BANK)\n@define INTERNAL_REGISTERS \"\"\n\n\n@ifdef INTERNAL_REGISTERS\n@define SINGLE_REGISTER_BANK \"\"\n@endif\n\n\ndefine endian=little;\ndefine alignment=1;\n\ndefine space CODE type=ram_space size=2 default;\ndefine space INTMEM type=ram_space size=1;\ndefine space EXTMEM type=ram_space size=1;\ndefine space PORT type=ram_space size=1;\n\ndefine space register type=register_space size=1;\n\ndefine register offset=0x00 size=1 [ A SP ];\n@ifdef INTERNAL_REGISTERS\ndefine register offset=0x10 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ];\n@endif\ndefine register offset=0x20 size=2 [ PC ];\ndefine register offset=0x30 size=1 [ C AC F0 F1 BS ]; # single bit\n\ndefine register offset=0x80 size=4 bankreg;\ndefine context bankreg\n DBF=(0,0)\n;\n\n################################################################\n# Tokens\n################################################################\n\ndefine token opbyte (8)\n opfull = (0,7)\n oplo = (0,3)\n ophi = (4,7)\n rn = (0,2) dec\n rnfill = (3,3)\n ri = (0,0) dec\n rifill = (1,3)\n opaddr = (5,7)\n addrfill = (4,4)\n pp = (0,1) dec\n xpp = (0,1) dec\n ppfill = (2,3)\n abit = (5,7) dec\n abfill = (4,4)\n dbf = (4,4)\n bs = (4,4)\n;\n\ndefine token aopword (16)\n aoplo = (0,3)\n aaddrfill = (4,4)\n aopaddr = (5,7)\n adata = (8,15)\n;\n\ndefine token ImmedByte (8) data=(0,7);\ndefine token AddrOne (8) addr8=(0,7);\n\n@ifdef INTERNAL_REGISTERS\nattach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];\nattach variables ri [ R0 R1 ];\n@else\nattach names rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];\nattach names ri [ R0 R1 ];\n@endif\n\nattach names abit [\"0\" \"1\" \"2\" \"3\" \"4\" \"5\" \"6\" \"7\"];\nattach names dbf [ MB0 MB1 ];\nattach names bs [ RB0 RB1 ];\nattach names pp [ BUS P1 P2 _ ];\nattach names xpp [ P4 P5 P6 P7 ];\n\n\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop nop;\ndefine pcodeop enableExtInt;\ndefine pcodeop enableTCntInt;\ndefine pcodeop enableClockOutput;\ndefine pcodeop disableExtInt;\ndefine pcodeop disableTCntInt;\ndefine pcodeop startTimer;\ndefine pcodeop startEventCounter;\ndefine pcodeop stopTimerAndEventCounter;\ndefine pcodeop setTmr;\ndefine pcodeop getTmr;\ndefine pcodeop getT0;\ndefine pcodeop getT1;\ndefine pcodeop getTF;\ndefine pcodeop getExtInt;\ndefine pcodeop readPort;\ndefine pcodeop writePort;\ndefine pcodeop setBank;\n\n\n################################################################\n# Macros\n################################################################\n\nmacro getPSW(reg) {\n local tmp:1 = 0;\n tmp[7,1] = C;\n tmp[6,1] = AC;\n tmp[5,1] = F0;\n tmp[4,1] = BS;\n tmp[3,1] = 1;\n tmp[0,3] = (SP>>1)&7;\n reg = tmp;\n}\n\nmacro setPSW(reg) {\n local tmp:1 = reg;\n C = tmp[7,1];\n AC = tmp[6,1];\n F0 = tmp[5,1];\n BS = tmp[4,1];\n SP = 2*tmp[0,3] + 8;\n}\n\nmacro savePSWtoPC(pc) {\n pc[15,1] = C;\n pc[14,1] = AC;\n pc[13,1] = F0;\n pc[12,1] = BS;\n}\n\nmacro restorePSWfromPC(pc) {\n C = pc[15,1];\n AC = pc[14,1];\n F0 = pc[13,1];\n BS = pc[12,1];\n}\n\nmacro push(v) {\n *[INTMEM]:2 SP = v;\n SP = SP + 2;\n}\n\nmacro pop(v) {\n SP = SP - 2;\n v = *[INTMEM]:2 SP;\n}\n\nmacro popPC(pc) {\n pop(pc);\n pc = pc & 0xfff;\n}\n\nmacro popPCandPSW(pc) {\n pop(pc);\n restorePSWfromPC(pc);\n pc = pc & 0xfff;\n}\n\nmacro funcall(target) {\n ret:2 = inst_next; \n savePSWtoPC(ret);\n push(ret);\n call target;\n}\n\nmacro add(dest, op1, op2, cy_in) {\n local result:1 = op1 + op2 + cy_in;\n local half_result:1 = (op1 & 0xf) + (op2 & 0xf) + cy_in;\n C = carry(op1, op2) || carry(op1+op2, cy_in);\n AC = (half_result > 0xf);\n dest = result;\n}\n\nmacro da(reg) {\n local tmp:1 = reg;\n local low:1 = 6*(AC || (tmp&0xf) > 9);\n local cy1:1 = C || carry(tmp, low);\n tmp = tmp + low;\n local high:1 = 0x60*(cy1 || tmp > 0x99);\n C = C || carry(tmp, high);\n tmp = tmp + high;\n reg = tmp;\n}\n\nmacro rotc(cy, acc) {\n local tmp:1 = cy;\n A = acc;\n C = tmp;\n}\n\nmacro xch(node1, node2) {\n local tmp:1 = node1;\n node1 = node2;\n node2 = tmp;\n}\n\n@ifdef SINGLE_REGISTER_BANK\nmacro regbank(r) { r = r; }\nmacro setbank(bs) {\n BS = bs;\n local tmp:1 = bs;\n setBank(tmp);\n}\n@else\nmacro regbank(r) {\n r = r + BS*0x18;\n}\nmacro setbank(bs) {\n BS = bs;\n}\n@endif\n\n\n################################################################\n\nPsw: \"PSW\" is epsilon { }\nExtInt: \"I\" is epsilon { }\nTCntInt: \"TCNTI\" is epsilon { }\nClk: \"CLK\" is epsilon { }\nTmr: \"T\" is epsilon { }\nCnt: \"CNT\" is epsilon { }\nTmrCnt: \"TCNT\" is epsilon { }\n\n@ifdef INTERNAL_REGISTERS\nRn: rn is rn & rnfill=1 {\n export rn;\n}\nRind: @ri is ri & rifill=0 {\n export ri;\n}\n@else\nRn: rn is rn & rnfill=1 {\n local ptr:1 = rn; regbank(ptr); export *[INTMEM]:1 ptr;\n}\nRind: @ri is ri & rifill=0 {\n local ptr:1 = ri; regbank(ptr); export *[INTMEM]:1 ptr;\n}\n@endif\nRi: Rind is Rind {\n export *[INTMEM]:1 Rind;\n}\nRiX: Rind is Rind {\n export *[EXTMEM]:1 Rind;\n}\nPData: @A is A {\n local addr:2 = inst_next; addr[0,8] = A; export *[CODE]:1 addr;\n}\nP3Data: @A is A {\n local addr:2 = 0x300; addr[0,8] = A; export *[CODE]:1 addr;\n}\nAddrInd: PData is PData {\n local addr:2 = inst_next; addr[0,8] = PData; export addr;\n}\nAb: abit is abit {\n local bit:1 = (A>>abit)&1; export bit;\n}\nData: \"#\"^data is data {\n export *[const]:1 data;\n}\nImm: Data is oplo=3; Data {\n export Data;\n}\nAddr8: addr is addr8 [ addr = (inst_next $and 0xff00)+addr8; ] {\n export *[CODE]:1 addr;\n}\nAddr12: addr is aopaddr & adata [ addr = (inst_next & 0xf000) + (DBF*0x800) + (aopaddr*256)+adata; ] {\n export *[CODE]:1 addr;\n}\nBus: \"BUS\" is epsilon {\n local tmp:1 = 0; export *[PORT]:1 tmp;\n}\nPp: pp is pp & ppfill=2 {\n export *[PORT]:1 pp;\n}\nXpp: xpp is xpp & ppfill=3 {\n local tmp:1 = xpp+4; export *[PORT]:1 tmp;\n}\n\nCc: \"C\" is ophi=15 {\n export C;\n}\nCc: \"F0\" is ophi=11 {\n export F0;\n}\nCc: \"F1\" is ophi=7 {\n export F1;\n}\nCc: \"NC\" is ophi=14 {\n tmp:1 = !C; export tmp;\n}\nCc: \"NI\" is ophi=8 {\n tmp:1 = getExtInt(); tmp = !tmp; export tmp;\n}\nCc: \"NT0\" is ophi=2 {\n tmp:1 = getT0(); tmp = !tmp; export tmp;\n}\nCc: \"NT1\" is ophi=4 {\n tmp:1 = getT1(); tmp = !tmp; export tmp;\n}\nCc: \"NZ\" is ophi=9 {\n tmp:1 = A!=0; export tmp;\n}\nCc: \"TF\" is ophi=1 {\n tmp:1 = getTF(); export tmp;\n}\nCc: \"T0\" is ophi=3 {\n tmp:1 = getT0(); export tmp;\n}\nCc: \"T1\" is ophi=5 {\n tmp:1 = getT1(); export tmp;\n}\nCc: \"Z\" is ophi=12 {\n tmp:1 = A==0; export tmp;\n}\n\n\n# Conventience tables for opcodes taking both Rn and Ri (and Imm)\nRni: Rn is Rn {\n export Rn;\n}\nRni: Ri is Ri {\n export Ri;\n}\nRniI: Rni is Rni {\n export Rni;\n}\nRniI: Imm is Imm {\n export Imm;\n}\n\n\n:ADD A,Rni is ophi=6 & (rnfill=1 | rifill=0) & A & Rni {\n add(A,A,Rni,0);\n}\n:ADD A,Imm is (ophi=0 & A)... & Imm {\n add(A,A,Imm,0);\n}\n:ADDC A,Rni is ophi=7 & A & (rnfill=1 | rifill=0) & Rni {\n add(A,A,Rni,C);\n}\n:ADDC A,Imm is (ophi=1 & A)... & Imm {\n add(A,A,Imm,C);\n}\n:ANL A,RniI is (ophi=5 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI {\n A = A & RniI;\n}\n:ANL Pp,Data is ophi=9 & ppfill=2 & Pp; Data {\n Pp = Pp & Data;\n}\n:ANLD Xpp,A is ophi=9 & ppfill=3 & Xpp & A {\n Xpp = Xpp & (A & 0xf);\n}\n:CALL Addr12 is aopaddr & aaddrfill=1 & aoplo=4 & Addr12 {\n funcall(Addr12);\n}\n:CLR A is ophi=2 & oplo=7 & A {\n A = 0;\n}\n:CLR C is ophi=9 & oplo=7 & C {\n C = 0;\n}\n:CLR F0 is ophi=8 & oplo=5 & F0 {\n F0 = 0;\n}\n:CLR F1 is ophi=10 & oplo=5 & F1 {\n F1 = 0;\n}\n:CPL A is ophi=3 & oplo=7 & A {\n A = ~A;\n}\n:CPL C is ophi=10 & oplo=7 & C {\n C = !C;\n}\n:CPL F0 is ophi=9 & oplo=5 & F0 {\n F0 = !F0;\n}\n:CPL F1 is ophi=11 & oplo=5 & F1 {\n F1 = !F1;\n}\n:DA A is ophi=5 & oplo=7 & A {\n da(A);\n}\n:DEC A is ophi=0 & oplo=7 & A {\n A = A - 1;\n}\n:DEC Rn is ophi=12 & Rn {\n Rn = Rn - 1;\n}\n:DIS ExtInt is ophi=1 & oplo=5 & ExtInt {\n disableExtInt();\n}\n:DIS TCntInt is ophi=3 & oplo=5 & TCntInt {\n disableTCntInt();\n}\n:DJNZ Rn,Addr8 is ophi=14 & Rn; Addr8 {\n Rn = Rn - 1; if(Rn != 0) goto Addr8;\n}\n:EN ExtInt is ophi=0 & oplo=5 & ExtInt {\n enableExtInt();\n}\n:EN TCntInt is ophi=2 & oplo=5 & TCntInt {\n enableTCntInt();\n}\n:ENT0 Clk is ophi=7 & oplo=5 & Clk {\n enableClockOutput();\n}\n:IN A,Pp is ophi=0 & pp!=0 & A & Pp {\n A = Pp;\n}\n:INC A is ophi=1 & oplo=7 & A {\n A = A + 1;\n}\n:INC Rni is ophi=1 & (rnfill=1 | rifill=0) & Rni {\n Rni = Rni + 1;\n}\n:INS A,Bus is ophi=0 & oplo=8 & A & Bus {\n A = Bus;\n}\n:JB^Ab Addr8 is oplo=2 & opaddr & abfill=1 & Ab; Addr8 {\n if(Ab) goto Addr8;\n}\n:J^Cc Addr8 is ophi & oplo=6 & Cc; Addr8 {\n if(Cc) goto Addr8;\n}\n:JMP Addr12 is aopaddr & aaddrfill=0 & aoplo=4 & Addr12 {\n goto Addr12;\n}\n:JMPP AddrInd is ophi=11 & oplo=3 & AddrInd {\n goto [AddrInd];\n}\n:MOV A,Imm is (ophi=2 & A)... & Imm {\n A = Imm;\n}\n:MOV A,Psw is ophi=12 & oplo=7 & A & Psw {\n getPSW(A);\n}\n:MOV A,Rni is ophi=15 & A & (rnfill=1 | rifill=0) & Rni {\n A = Rni;\n}\n:MOV A,Tmr is ophi=4 & oplo=2 & A & Tmr {\n A = getTmr();\n}\n:MOV Psw,A is ophi=13 & oplo=7 & Psw & A {\n setPSW(A);\n}\n:MOV Rni,A is ophi=10 & (rnfill=1 | rifill=0) & Rni & A {\n Rni = A;\n}\n:MOV Rni,Data\tis ophi=11 & (rnfill=1 | rifill=0) & Rni; Data {\n Rni = Data;\n}\n:MOV Tmr,A is ophi=6 & oplo=2 & Tmr & A {\n setTmr(A);\n}\n:MOVD A,Xpp is ophi=0 & Xpp & A {\n A = (Xpp & 0xf);\n}\n:MOVD Xpp,A is ophi=3 & Xpp & A {\n Xpp = (A & 0xf);\n}\n:MOVP A,PData is ophi=10 & oplo=3 & A & PData {\n A = PData;\n}\n:MOVP3 A,P3Data is ophi=14 & oplo=3 & A & P3Data {\n A = P3Data;\n}\n:MOVX A,RiX is ophi=8 & A & RiX {\n A = RiX;\n}\n:MOVX RiX,A is ophi=9 & RiX & A {\n RiX = A;\n}\n:NOP is ophi=0 & oplo=0 {\n nop();\n}\n:ORL A,RniI is (ophi=4 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI {\n A = A | RniI;\n}\n:ORL Pp,Data is ophi=8 & Pp; Data {\n Pp = Pp | Data;\n}\n:ORLD Xpp,A is ophi=8 & Xpp & A {\n Xpp = Xpp | (A & 0xf);\n}\n:OUTL Bus,A is ophi=0 & oplo=2 & Bus & A {\n Bus = A;\n}\n:OUTL Pp,A is ophi=3 & pp!=0 & Pp & A {\n Pp = A;\n}\n:RET is ophi=8 & oplo=3 {\n pc:2 = 0; popPC(pc); return[pc];\n}\n:RETR is ophi=9 & oplo=3 {\n pc:2 = 0; popPCandPSW(pc); return[pc];\n}\n:RL A is ophi=14 & oplo=7 & A {\n A = (A<<1) | (A>>7);\n}\n:RLC A is ophi=15 & oplo=7 & A {\n rotc((A&0x80)>>7, (A<<1)|C);\n}\n:RR A is ophi=7 & oplo=7 & A {\n A = (A>>1) | (A<<7);\n}\n:RRC A is ophi=6 & oplo=7 & A {\n rotc(A&1, (A>>1)|(C<<7));\n}\n:SEL dbf is (ophi=14 | ophi=15) & oplo=5 & dbf\n\t[ DBF=dbf; globalset(inst_next,DBF); ]\n{}\n:SEL bs is (ophi=12 | ophi=13) & oplo=5 & bs {\n setbank(bs);\n}\n:STOP TmrCnt is ophi=6 & oplo=5 & TmrCnt {\n stopTimerAndEventCounter();\n}\n:STRT Cnt is ophi=4 & oplo=5 & Cnt {\n startEventCounter();\n}\n:STRT Tmr is ophi=5 & oplo=5 & Tmr {\n startTimer();\n}\n:SWAP A is ophi=4 & oplo=7 & A {\n A = (A<<4)|(A>>4);\n}\n:XCH A,Rni is ophi=2 & (rnfill=1 | rifill=0) & A & Rni {\n xch(A, Rni);\n}\n:XCHD A,Ri is ophi=3 & A & Ri {\n xch(A[0,4], Ri[0,4]);\n}\n:XRL A,RniI is (ophi=13 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI {\n A = A ^ RniI;\n}\n" }, { "path": "pypcode/processors/8048/data/manuals/8048.idx", "content": "@8048.pdf [MCS-48 Microcomputer User's Manual, February 1978]\nADD, 63\nADDC, 63\nANL, 64\nANLD, 65\nCALL, 66\nCLR, 67\nCPL, 67\nDA, 68\nDEC, 68\nDIS, 69\nDJNZ, 69\nEN, 70\nENT0, 70\nIN, 70\nINC, 71\nINS, 72\nJB, 72\nJC, 72\nJF0, 72\nJF1, 73\nJMP, 73\nJMPP, 73\nJNC, 73\nJNI, 74\nJNT0, 74\nJNT1, 74\nJNZ, 74\nJTF, 75\nJT0, 75\nJT1, 75\nJZ, 75\nMOV, 76\nMOVD, 79\nMOVP, 79\nMOVP3, 80\nMOVX, 80\nNOP, 81\nORL, 81\nORLD, 82\nOUTL, 82\nRET, 83\nRETR, 83\nRL, 83\nRLC, 84\nRR, 84\nRRC, 84\nSEL, 85\nSTOP, 86\nSTRT, 87\nSWAP, 87\nXCH, 88\nXCHD, 88\nXRL, 89\n" }, { "path": "pypcode/processors/8051/data/languages/80251.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/80251.pspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n\t\t \n\t\t \n\t\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/80251.sinc", "content": "# 80251 Instructions\n\n# NOTE! 80251 implementation is preliminary and has not tested !!\n\ndefine token srcDestByte (8)\n rm47 = (4,7)\n rm47_d1 = (4,7)\n rm47_d2 = (4,7)\n rm03 = (0,3)\n wrj47 = (4,7)\n wrj47_d1 = (4,7)\n wrj47_d2 = (4,7)\n wrj03 = (0,3)\n drk47 = (4,7)\n drk03 = (0,3)\n # constraint bits\n d7 = (7,7)\n d57 = (5,7)\n d47 = (4,7)\n s3 = (3,3)\n s23 = (2,3)\n s13 = (1,3)\n s03 = (0,3)\n s1 = (1,1)\n s0 = (0,0)\n short01 = (0,1)\n bit02 = (0,2)\n;\n\ndefine token srcDestByte2 (8)\n rm47_ = (4,7)\n rm03_ = (0,3)\n wrj47_ = (4,7)\n wrj03_ = (0,3)\n drk47_ = (4,7)\n drk03_ = (0,3)\n # constraint bits\n d7_ = (7,7)\n d57_ = (5,7)\n s3_ = (3,3)\n s13_ = (1,3)\n s03_ = (0,3)\n;\n\ndefine token AddrThree (24)\n addr24 = (0,23)\n;\n\ndefine token ImmedThree (24)\n\tdata24 = (0,23)\n;\n\nattach values short01 [ 1 2 4 _ ];\n\nattach variables [ rm47 rm03 rm47_ rm03_ ] [ \n\tR0 R1 R2 R3 R4 R5 R6 R7 \n\tR8 R9 B ACC R12 R13 R14 R15 \n];\n\nattach variables [ rm47_d1 ] [ \n\tR0 R0 R2 R2 R4 R3 R6 R6 \n\tR8 R8 B B R12 R12 R14 R14 \n];\n\nattach variables [ rm47_d2 ] [ \n\tR1 R1 R3 R3 R5 R5 R7 R7 \n\tR9 R9 ACC ACC R13 R13 R15 R15 \n];\n\nattach variables [ wrj47 wrj03 wrj47_ wrj03_ ] [ \n\tWR0 WR2 WR4 WR6 WR8 AB WR12 WR14\n WR16 WR18 WR20 WR22 WR24 WR26 WR28 WR30\n];\n\nattach variables [ wrj47_d1 ] [ \n\tWR0 WR0 WR4 WR4 WR8 WR8 WR12 WR12\n WR16 WR16 WR20 WR20 WR24 WR24 WR28 WR28\n];\n\nattach variables [ wrj47_d2 ] [ \n\tWR2 WR2 WR6 WR6 AB AB WR14 WR14\n WR18 WR18 WR22 WR22 WR26 WR26 WR30 WR30\n];\n\n# NOTE: must use constraints DRK, DRKD and DRKS\nattach variables [ drk47 drk03 drk47_ drk03_ ] [\n\tDR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28\n\tDPX SPX _ _ _ _ _ _\n];\n\n@define DRK47 \"drk47 & (d7=0 | d57=4)\" # constraint for using drk47\n@define DRK03 \"drk03 & (s3=0 | s13=4)\" # constraint for using drk03\n@define DRK47_ \"drk47_ & (d7_=0 | d57_=4)\" # constraint for using drk47_\n \nAtWRjb: \"@\"^wrj47\tis wrj47 { ptr:3 = zext(wrj47); export *:1 ptr; }\nAtWRjw: \"@\"^wrj47\tis wrj47 { ptr:3 = zext(wrj47); export *:2 ptr; }\n\n# NOTE: be sure to use the ATDRK constraint on the constructor\nAtDRkb: \"@\"^drk47\tis drk47 { ptr:3 = drk47:3; export *:1 ptr; }\nAtDRkw: \"@\"^drk47\tis drk47 { ptr:3 = drk47:3; export *:2 ptr; }\nAtDRkt: \"@\"^drk47\tis drk47 { ptr:3 = drk47:3; export *:3 ptr; }\n\n@define ATDRK \"(d7=0 | d57=4)\"\n\nAtWRj47Dis16b: \"@\"^wrj47^\"+\"^data16 is wrj47; data16 { ptr:3 = zext(wrj47) + data16; export *:1 ptr; }\nAtWRj47Dis16w: \"@\"^wrj47^\"+\"^data16 is wrj47; data16 { ptr:3 = zext(wrj47) + data16; export *:2 ptr; }\n\nAtWRj03Dis16b: \"@\"^wrj03^\"+\"^data16 is wrj03; data16 { ptr:3 = zext(wrj03) + data16; export *:1 ptr; }\nAtWRj03Dis16w: \"@\"^wrj03^\"+\"^data16 is wrj03; data16 { ptr:3 = zext(wrj03) + data16; export *:2 ptr; }\n\nAtDRk47Dis24b: \"@\"^drk47^\"+\"^data24 is drk47; data24 { ptr:3 = drk47:3 + data24; export *:1 ptr; }\nAtDRk47Dis24w: \"@\"^drk47^\"+\"^data24 is drk47; data24 { ptr:3 = drk47:3 + data24; export *:2 ptr; }\n\nAtDRk03Dis24b: \"@\"^drk03^\"+\"^data24 is drk03; data24 { ptr:3 = drk03:3 + data24; export *:1 ptr; }\nAtDRk03Dis24w: \"@\"^drk03^\"+\"^data24 is drk03; data24 { ptr:3 = drk03:3 + data24; export *:2 ptr; }\n\n# TODO: Verify dir8 access restriction for word/dword accesses !!\nDirect8w: mainreg is bank=0 & mainreg\t{ export *:2 mainreg; }\nDirect8w: Direct is bank=1 & Direct \t{ tmp:2 = zext(Direct); export tmp; }\n\n# TODO: The dir16 mode does not map into the SFR's - is this correct ??\nDirect16b: addr16 is addr16 { export *:1 addr16; }\nDirect16w: addr16 is addr16 { export *:2 addr16; }\nDirect16d: addr16 is addr16 { export *:4 addr16; }\n\nData16x0: \"#\"data16 is data16 { export *[const]:4 data16; }\nData16x1: \"#\"val is data16 [ val = 0xffff0000 + data16; ] { export *[const]:4 val; }\n\nAddr24: addr24 is addr24 { export *:1 addr24; }\n\n# NOTE: use SHORT constraint\nShort: \"#\"^short01 is short01\t\t{ export *[const]:1 short01; }\n@define SHORT \"Short & (s0=0 | s1=0)\"\n\n#TODO: Figure out new bit addressing for 251 ...\n\nxBitByteAddr:\tis bitaddr8 { export *:1 bitaddr8; }\n\nxBitAddr: bitaddr^\".\"^bit02 \t\tis bit02; bitaddr8 [ bitaddr = (bitaddr8 << 3) + bit02; ] { export *[BITS]:1 bitaddr; }\nxBitAddr2: \"/\"^bitaddr^\".\"^bit02 \tis bit02; bitaddr8 [ bitaddr = (bitaddr8 << 3) + bit02; ] { export *[BITS]:1 bitaddr; }\n\n\nmacro push24(val) { \n al:1 = val:1;\n ah:1 = val(1);\n ax:1 = val(2);\n \n ptr:3 = SPX:3;\n \n ptr = ptr + 1; \n *[RAM]:1 ptr = al;\n ptr = ptr + 1; \n *[RAM]:1 ptr = ah;\n ptr = ptr + 1; \n *[RAM]:1 ptr = ax;\n \n SPX = SPX + 3;\n}\n\nmacro pop24(val) {\n \n SPX = SPX - 2;\n \n ptr:3 = SPX:3;\n al:1 = *[RAM]:1 ptr;\n ah:1 = *[RAM]:1 (ptr+1);\n ax:1 = *[RAM]:1 (ptr+2);\n \n SPX = SPX - 1;\n \n val = (zext(ax) << 16) | (zext(ah) << 8) | zext(al);\n}\n\n\n# s s s s Binary representation of m or md\n# S S S S Binary representation of ms\n# t t t t Binary representation of j or jd\n# T T T T Binary representation of js\n# u u u u Binary representation of k or kd\n# U U U U Binary representation of ks\n\n# NOTE: >>>> Find MCS251 instructions by searching for \"Binary Mode = [A5][Encoding]\" in PDF manual <<<<\n# NOTE: All instructions should include the $(GROUP3) pattern prefix\n\n# ADD Rmd,Rms\n:ADD rm47,rm03\tis $(GROUP3) & ophi=2 & oplo=12; rm47 & rm03 { addflags(rm47,rm03); rm47 = rm47 + rm03; resultflags(rm47); }\n\n# ADD WRjd,WRjs\n:ADD wrj47,wrj03\tis $(GROUP3) & ophi=2 & oplo=13; wrj47 & wrj03 { addflags(wrj47,wrj03); wrj47 = wrj47 + wrj03; resultflags(wrj47); }\n\n# ADD DRkd,DRks\n:ADD drk47,drk03 is $(GROUP3) & ophi=2 & oplo=15; $(DRK47) & $(DRK03) { addflags(drk47,drk03); drk47 = drk47 + drk03; resultflags(drk47); }\n\n# ADD Rm,#data\n:ADD rm47,Data\tis $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=0; Data { addflags(rm47,Data); rm47 = rm47 + Data; resultflags(rm47); }\n\n# ADD WRj,#data16\n:ADD wrj47,Data16\tis $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=4; Data16 { addflags(wrj47,Data16); wrj47 = wrj47 + Data16; resultflags(wrj47); }\n\n# ADD DRk,#0data16\n:ADD drk47,Data16x0\tis $(GROUP3) & ophi=2 & oplo=14; $(DRK47) & s03=8; Data16x0 { addflags(drk47,Data16x0); drk47 = drk47 + Data16x0; resultflags(drk47); }\n\n# ADD Rm,dir8\n:ADD rm47,Direct\tis $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=1; Direct { addflags(rm47,Direct); rm47 = rm47 + Direct; resultflags(rm47); }\n\n# ADD WRj,dir8\n:ADD wrj47,Direct8w\tis $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=5; Direct8w { addflags(wrj47,Direct8w); wrj47 = wrj47 + Direct8w; resultflags(wrj47); }\n\n# ADD Rm,dir16\n:ADD rm47,Direct16b\tis $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=3; Direct16b { addflags(rm47,Direct16b); rm47 = rm47 + Direct16b; resultflags(rm47); }\n\n# ADD WRj,dir16\n:ADD wrj47,Direct16w\tis $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=7; Direct16w { addflags(wrj47,Direct16w); wrj47 = wrj47 + Direct16w; resultflags(wrj47); }\n\n# ADD Rm,@WRj\n:ADD rm47_,AtWRjb\tis $(GROUP3) & ophi=2 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { addflags(rm47_,AtWRjb); rm47_ = rm47_ + AtWRjb; resultflags(rm47_); }\n\n# ADD Rm,@DRk\n:ADD rm47_,AtDRkb\tis $(GROUP3) & ophi=2 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { addflags(rm47_,AtDRkb); rm47_ = rm47_ + AtDRkb; resultflags(rm47_); }\n\n# ANL Rmd,Rms\n:ANL rm47,rm03\tis $(GROUP3) & ophi=5 & oplo=12; rm47 & rm03 { rm47 = rm47 & rm03; resultflags(rm47); }\n\n# ANL WRjd,WRjs\n:ANL wrj47,wrj03\tis $(GROUP3) & ophi=5 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 & wrj03; resultflags(wrj47); }\n\n# ANL Rm,#data\n:ANL rm47,Data\tis $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 & Data; resultflags(rm47); }\n\n# ANL WRj,#data16\n:ANL wrj47,Data16\tis $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 & Data16; resultflags(wrj47); }\n\n# ANL Rm,dir8\n:ANL rm47,Direct\tis $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 & Direct; resultflags(rm47); }\n\n# ANL WRj,dir8\n:ANL wrj47,Direct8w\tis $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = wrj47 & Direct8w; resultflags(wrj47); }\n\n# ANL Rm,dir16\n:ANL rm47,Direct16b\tis $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 & Direct16b; resultflags(rm47); }\n\n# ANL WRj,dir16\n:ANL wrj47,Direct16w\tis $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 & Direct16w; resultflags(wrj47); }\n\n# ANL Rm,@WRj\n:ANL rm47_,AtWRjb\tis $(GROUP3) & ophi=5 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ & AtWRjb; resultflags(rm47_); }\n\n# ANL Rm,@DRk\n:ANL rm47_,AtDRkb\tis $(GROUP3) & ophi=5 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ & AtDRkb; resultflags(rm47_); }\n\n# ANL C,bit\n:ANL \"CY\",xBitAddr\tis $(GROUP3) & ophi=10 & oplo=9; (d47=8 & s3=0 & bit02; xBitByteAddr) & xBitAddr { $(CY)=$(CY)& ((xBitByteAddr>>bit02)&1); resultflags(xBitByteAddr); }\n\n# ANL C,/bit\n:ANL \"CY\",xBitAddr2\tis $(GROUP3) & ophi=10 & oplo=9; (d47=15 & s3=0 & bit02; xBitByteAddr) & xBitAddr2 { $(CY)=$(CY)& (~((xBitByteAddr>>bit02)&1)); resultflags(xBitByteAddr); }\n\n# CLR bit\n:CLR xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=12 & s3=0 & bit02; xBitByteAddr) & xBitAddr { tmp:1 = ~(1<>bit02)&1) == 1:1) goto Rel8; }\n\n# JBC bit,rel\n:JBC xBitAddr,Rel8\tis $(GROUP3) & ophi=10 & oplo=9; (d47=1 & s3=0 & bit02; xBitByteAddr) & xBitAddr; Rel8\t{ tmp:1 = 1<>bit02)&1)==0:1) goto Rel8; }\n\n# JNE rel\n:JNE Rel8\tis $(GROUP3) & ophi=7 & oplo=8; Rel8\t\t{ if ($(Z)==0) goto Rel8; }\n\n# JSG rel\n:JSG Rel8\tis $(GROUP3) & ophi=1 & oplo=8; Rel8\t\t{ if ($(Z)==0 && $(N)==$(OV)) goto Rel8; }\n\n# JSGE rel\n:JSGE Rel8\tis $(GROUP3) & ophi=5 & oplo=8; Rel8\t\t{ if ($(N)==$(OV)) goto Rel8; }\n\n# JSL rel\n:JSL Rel8\tis $(GROUP3) & ophi=4 & oplo=8; Rel8\t\t{ if ($(N)!=$(OV)) goto Rel8; }\n\n# JSLE rel\n:JSLE Rel8\tis $(GROUP3) & ophi=0 & oplo=8; Rel8\t\t{ if ($(Z)==1 || $(N)!=$(OV)) goto Rel8; }\n\n# LCALL @WRj\n:LCALL AtWRjw\t\tis $(GROUP3) & ophi=9 & oplo=9; AtWRjw & s03=4\t{ ptr:3 = inst_next; push16(ptr:2); pc:3 = (ptr & 0xff0000) + zext(AtWRjw); call [pc]; }\n\n# LJMP @WRj\n:LJMP AtWRjw\t\tis $(GROUP3) & ophi=8 & oplo=9; AtWRjw & s03=4\t{ ptr:3 = inst_next; pc:3 = (ptr & 0xff0000) + zext(AtWRjw); goto [pc]; }\n\n# MOV Rmd,Rms\n:MOV rm47,rm03\t\tis $(GROUP3) & ophi=7 & oplo=12; rm47 & rm03 { rm47 = rm03; }\n\n# MOV WRjd,WRjs\n:MOV wrj47,wrj03\tis $(GROUP3) & ophi=7 & oplo=13; wrj47 & wrj03 { wrj47 = wrj03; }\n\n# MOV DRkd,DRks\n:MOV drk47,drk03\tis $(GROUP3) & ophi=7 & oplo=15; drk47 & drk03 { drk47 = drk03; }\n\n# MOV Rm,#data\n:MOV rm47,Data\t\tis $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=0; Data\t{ rm47 = Data; }\n\n# MOV WRj,#data16\n:MOV wrj47,Data16\tis $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=4; Data16\t{ wrj47 = Data16; }\n\n# MOV DRk,#0data16\n:MOV drk47,Data16x0\tis $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=8; Data16x0\t{ drk47 = Data16x0; }\n\n# MOV DRk,#1data16\n:MOV drk47,Data16x1\tis $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=12; Data16x1\t{ drk47 = Data16x1; }\n\n# MOV Rm,dir8\n:MOV rm47,Direct\tis $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=1; Direct\t{ rm47 = Direct; }\n\n# MOV WRj,dir8\n:MOV wrj47,Direct8w\tis $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=5; Direct8w\t{ wrj47 = Direct8w; }\n\n# MOV DRk,dir8\n:MOV drk47,Direct8w\tis $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=13; Direct8w\t{ drk47 = zext(Direct8w); }\n\n# MOV Rm,dir16\n:MOV rm47,Direct16b\t\tis $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=3; Direct16b\t{ rm47 = Direct16b; }\n\n# MOV WRj,dir16\n:MOV wrj47,Direct16w\tis $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=7; Direct16w\t{ wrj47 = Direct16w; }\n\n# MOV DRk,dir16\n:MOV drk47,Direct16d\tis $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=15; Direct16d\t{ drk47 = Direct16d; }\n\n# MOV Rm,@WRj\n:MOV rm47_,AtWRjb\tis $(GROUP3) & ophi=7 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = AtWRjb; }\n\n# MOV Rm,@DRk\n:MOV rm47_,AtDRkb\tis $(GROUP3) & ophi=7 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = AtDRkb; }\n\n# MOV WRjd,@WRjs\n:MOV wrj47_,AtWRjw\tis $(GROUP3) & ophi=0 & oplo=11; AtWRjw & s03=8; wrj47_ & s03_=0 { wrj47_ = AtWRjw; }\n\n# MOV WRj,@DRk\n:MOV wrj47_,AtDRkw\tis $(GROUP3) & ophi=0 & oplo=11; $(ATDRK) & AtDRkw & s03=10; wrj47_ & s03_=0 { wrj47_ = AtDRkw; }\n\n# MOV dir8,Rm\n:MOV Direct,rm47\tis $(GROUP3) & ophi=7 & oplo=10; rm47 & s03=1; Direct\t{ Direct = rm47; }\n\n# MOV dir8,WRj\n# TODO: !! Verify direct byte write restriction to SFR registers\n:MOV Direct8w,wrj47\tis $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=5; bank=0 & Direct8w\t{ Direct8w = wrj47; }\n:MOV Direct,wrj47\tis $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=5; bank=1 & Direct\t{ Direct = wrj47:1; }\n\n# MOV dir8,DRk\n# TODO: !! Verify byte/word write restriction to internal memory (00-7f)\n# TODO: !! Verify byte write restriction to SFR registers\n:MOV Direct8w,drk47\tis $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=13; bank=0 & Direct8w\t{ Direct8w = drk47:2; }\n:MOV Direct,drk47\tis $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=13; bank=1 & Direct\t{ Direct = drk47:1; }\n\n# MOV dir16,Rm\n:MOV Direct16b,rm47\tis $(GROUP3) & ophi=7 & oplo=10; rm47 & s03=3; Direct16b\t{ Direct16b = rm47; }\n\n# MOV dir16,WRj\n:MOV Direct16w,wrj47\tis $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=7; Direct16w\t{ Direct16w = wrj47; }\n\n# MOV dir16,DRk\n:MOV Direct16d,drk47\tis $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=15; Direct16d\t{ Direct16d = drk47; }\n\n# MOV @WRj,Rm\n:MOV AtWRjb,rm47_\tis $(GROUP3) & ophi=7 & oplo=10; AtWRjb & s03=9; rm47_ & s03_=0 { AtWRjb = rm47_; }\n\n# MOV @DRk,Rm\n:MOV AtDRkb,rm47_\tis $(GROUP3) & ophi=7 & oplo=10; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { AtDRkb = rm47_; }\n\n# MOV @WRjd,WRjs\n:MOV AtWRjw,wrj47_\tis $(GROUP3) & ophi=1 & oplo=11; AtWRjw & s03=8; wrj47_ & s03_=0 { AtWRjw = wrj47_; }\n\n# MOV @DRk,WRj\n:MOV AtDRkw,wrj47_\tis $(GROUP3) & ophi=1 & oplo=11; $(ATDRK) & AtDRkw & s03=10; wrj47_ & s03_=0 { AtDRkw = wrj47_; }\n\n# MOV Rm,@WRj+dis16\n:MOV rm47,AtWRj03Dis16b\t is $(GROUP3) & ophi=0 & oplo=9; rm47 ... & AtWRj03Dis16b { AtWRj03Dis16b = rm47; }\n\n# MOV WRj,@WRj+dis16\n:MOV wrj47,AtWRj03Dis16w is $(GROUP3) & ophi=4 & oplo=9; wrj47 ... & AtWRj03Dis16w { AtWRj03Dis16w = wrj47; }\n\n# MOV Rm,@DRk+dis24\n:MOV rm47,AtDRk03Dis24b\t is $(GROUP3) & ophi=2 & oplo=9; (rm47 & $(DRK03)) ... & AtDRk03Dis24b { AtDRk03Dis24b = rm47; }\n\n# MOV WRj,@DRk+dis24\n:MOV wrj47,AtDRk03Dis24w is $(GROUP3) & ophi=6 & oplo=9; (wrj47 & $(DRK03)) ... & AtDRk03Dis24w { AtDRk03Dis24w = wrj47; }\n\n# MOV @WRj+dis16,Rm\n:MOV AtWRj47Dis16b,rm03\t is $(GROUP3) & ophi=1 & oplo=9; rm03 ... & AtWRj47Dis16b { AtWRj47Dis16b = rm03; }\n\n# MOV @WRj+dis16,WRj\n:MOV AtWRj47Dis16w,wrj03 is $(GROUP3) & ophi=5 & oplo=9; wrj03 ... & AtWRj47Dis16w { AtWRj47Dis16w = wrj03; }\n\n# MOV @DRk+dis24,Rm\n:MOV AtDRk47Dis24b,rm03 is $(GROUP3) & ophi=3 & oplo=9; (rm03 & $(DRK47)) ... & AtDRk47Dis24b { AtDRk47Dis24b = rm03; }\n\n# MOV @DRk+dis24,WRj\n:MOV AtDRk47Dis24w,wrj03 is $(GROUP3) & ophi=7 & oplo=9; (wrj03 & $(DRK47)) ... & AtDRk47Dis24w { AtDRk47Dis24w = wrj03; }\n\n# MOV bit,C\n:MOV xBitAddr,\"CY\"\tis $(GROUP3) & ophi=10 & oplo=9; (d47=9 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1<>bit02)&1); }\n\n\n# MOVH DRk,#data16\n:MOVH drk47,Data16x0\tis $(GROUP3) & ophi=7 & oplo=14; $(DRK47) & s03=12; Data16x0 { drk47 = (drk47 & 0xffff0000) | (Data16x0 << 16); }\n\n# MOVS WRj,Rm\n:MOVZ wrj47,rm03 is $(GROUP3) & ophi=1 & oplo=10; wrj47 & rm03 { wrj47 = sext(rm03); }\n\n# MOVZ WRj,Rm\n:MOVZ wrj47,rm03 is $(GROUP3) & ophi=0 & oplo=10; wrj47 & rm03 { wrj47 = zext(rm03); }\n\n# MUL Rmd,Rms\n:MUL rm47,rm03\tis $(GROUP3) & ophi=10 & oplo=12; rm47 & rm03 & rm47_d1 & rm47_d2 { result:2 = zext(rm47) * zext(rm03); tmp:2 = result>>8; rm47_d1 = tmp:1; rm47_d2 = result:1; }\n\n# MUL WRjd,WRjs\n:MUL wrj47,wrj03\tis $(GROUP3) & ophi=10 & oplo=13; wrj47 & wrj03 & wrj47_d1 & wrj47_d2 { result:4 = zext(wrj47) * zext(wrj03); tmp:4 = result>>16; wrj47_d1 = tmp:2; wrj47_d2 = result:2; }\n\n# ORL Rmd,Rms\n:ORL rm47,rm03\tis $(GROUP3) & ophi=4 & oplo=12; rm47 & rm03 { rm47 = rm47 | rm03; resultflags(rm47); }\n\n# ORL WRjd,WRjs\n:ORL wrj47,wrj03\tis $(GROUP3) & ophi=4 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 | wrj03; resultflags(wrj47); }\n\n# ORL Rm,#data\n:ORL rm47,Data\tis $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 | Data; resultflags(rm47); }\n\n# ORL WRj,#data16\n:ORL wrj47,Data16\tis $(GROUP3) & ophi=4 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 | Data16; resultflags(wrj47); }\n\n# ORL Rm,dir8\n:ORL rm47,Direct\tis $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 | Direct; resultflags(rm47); }\n\n# ORL WRj,dir8\n:ORL wrj47,Direct8w\tis $(GROUP3) & ophi=4 & oplo=15; wrj47 & s03=5; Direct8w { wrj47 = wrj47 | Direct8w; resultflags(wrj47); }\n\n# ORL Rm,dir16\n:ORL rm47,Direct16b\tis $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 | Direct16b; resultflags(rm47); }\n\n# ORL WRj,dir16\n:ORL wrj47,Direct16w\tis $(GROUP3) & ophi=4 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 | Direct16w; resultflags(wrj47); }\n\n# ORL Rm,@WRj\n:ORL rm47_,AtWRjb\tis $(GROUP3) & ophi=4 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ | AtWRjb; resultflags(rm47_); }\n\n# ORL Rm,@DRk\n:ORL rm47_,AtDRkb\tis $(GROUP3) & ophi=4 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ | AtDRkb; resultflags(rm47_); }\n\n# ORL C,bit\n:ORL \"CY\",xBitAddr\tis $(GROUP3) & ophi=10 & oplo=9; (d47=7 & s3=0 & bit02; xBitByteAddr) & xBitAddr { $(CY) = ((xBitByteAddr>>bit02)&1) | $(CY); }\n\n# ORL bit,C\n:ORL \"CY\",xBitAddr2\tis $(GROUP3) & ophi=10 & oplo=9; (d47=14 & s3=0 & bit02; xBitByteAddr) & xBitAddr2 { $(CY) = ((xBitByteAddr>>bit02)&1) | ($(CY) == 0); }\n\n# POP Rm\n:POP rm47\tis $(GROUP3) & ophi=13 & oplo=10; rm47 & s03=8 { pop8(rm47); }\n\n# POP WRj\n:POP wrj47\tis $(GROUP3) & ophi=13 & oplo=10; wrj47 & s03=9 { pop16(wrj47); }\n\n# POP DRk\n:POP drk47\tis $(GROUP3) & ophi=13 & oplo=10; $(DRK47) & s03=11 { pop16(drk47); }\n\n# PUSH #data\n# TODO: manual did not specify A5 prefix, but would otherwise conflict with the XCH A,Rn instruction (8051)\n:PUSH Data\t is $(GROUP3) & ophi=12 & oplo=10; d47=0 & s03=2; Data { push8(Data); }\n\n# PUSH #data16\n:PUSH Data16\tis $(GROUP3) & ophi=12 & oplo=10; d47=0 & s03=6; Data16 { push16(Data16); }\n\n# PUSH Rm\n:PUSH rm47\tis $(GROUP3) & ophi=12 & oplo=10; rm47 & s03=8 { push8(rm47); }\n\n# PUSH WRj\n:PUSH wrj47\tis $(GROUP3) & ophi=12 & oplo=10; wrj47 & s03=9 { push16(wrj47); }\n\n# PUSH DRk\n:PUSH drk47\tis $(GROUP3) & ophi=12 & oplo=10; $(DRK47) & s03=11 { push16(drk47); }\n\n# SETB bit\n:SETB xBitAddr^\".\"^xBitByteAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=13 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1 << bit02); }\n\n# SLL Rm\n:SLL rm47\tis $(GROUP3) & ophi=3 & oplo=14; rm47 & s03=0 { $(CY) = ((rm47>>7) & 1); rm47 = rm47 << 1; resultflags(rm47); }\n\n# SLL WRj\n:SLL wrj47\tis $(GROUP3) & ophi=3 & oplo=14; wrj47 & s03=4 { $(CY) = ((wrj47>>15) & 1) == 1; wrj47 = wrj47 << 1; resultflags(wrj47); }\n\n# SRA Rm\n:SRA rm47\tis $(GROUP3) & ophi=0 & oplo=14; rm47 & s03=0 { $(CY) = rm47 & 1; rm47 = rm47 s>> 1; resultflags(rm47); }\n\n# SRA WRj\n:SRA wrj47\tis $(GROUP3) & ophi=0 & oplo=14; wrj47 & s03=4 { $(CY) = (wrj47 & 1) == 1; wrj47 = wrj47 s>> 1; resultflags(wrj47); }\n\n# SRL Rm\n:SRL rm47\tis $(GROUP3) & ophi=1 & oplo=14; rm47 & s03=0 { $(CY) = rm47 & 1; rm47 = rm47 >> 1; resultflags(rm47); }\n\n# SRL WRj\n:SRL wrj47\tis $(GROUP3) & ophi=1 & oplo=14; wrj47 & s03=4 { $(CY) = (wrj47 & 1) == 1; wrj47 = wrj47 >> 1; resultflags(wrj47); }\n\n\n# SUB Rmd,Rms\n:SUB rm47,rm03\tis $(GROUP3) & ophi=9 & oplo=12; rm47 & rm03 { subflags(rm47,rm03); rm47 = rm47 - rm03; resultflags(rm47); }\n\n# SUB WRjd,WRjs\n:SUB wrj47,wrj03\tis $(GROUP3) & ophi=9 & oplo=13; wrj47 & wrj03 { subflags(wrj47,wrj03); wrj47 = wrj47 - wrj03; resultflags(wrj47); }\n\n# SUB DRkd,DRks\n:SUB drk47,drk03 is $(GROUP3) & ophi=9 & oplo=15; $(DRK47) & $(DRK03) { subflags(drk47,drk03); drk47 = drk47 - drk03; resultflags(drk47);}\n\n# SUB Rm,#data\n:SUB rm47,Data\tis $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=0; Data { subflags(rm47,Data); rm47 = rm47 - Data; resultflags(rm47);}\n\n# SUB WRj,#data16\n:SUB wrj47,Data16\tis $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=4; Data16 { subflags(wrj47,Data16); wrj47 = wrj47 - Data16; resultflags(wrj47);}\n\n# SUB DRk,#data16\n:SUB drk47,Data16x0\tis $(GROUP3) & ophi=9 & oplo=14; $(DRK47) & s03=8; Data16x0 { subflags(drk47,Data16x0); drk47 = drk47 - Data16x0; resultflags(drk47);}\n\n# SUB Rm,dir8\n:SUB rm47,Direct\tis $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=1; Direct { subflags(rm47,Direct); rm47 = rm47 - Direct; resultflags(rm47);}\n\n# SUB WRj,dir8\n:SUB wrj47,Direct8w\tis $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=5; Direct8w { subflags(wrj47,Direct8w); wrj47 = wrj47 - Direct8w; resultflags(wrj47);}\n\n# SUB Rm,dir16\n:SUB rm47,Direct16b\tis $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=3; Direct16b { subflags(rm47,Direct16b); rm47 = rm47 - Direct16b; resultflags(rm47);}\n\n# SUB WRj,dir16\n:SUB wrj47,Direct16w\tis $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=7; Direct16w { subflags(wrj47,Direct16w); wrj47 = wrj47 - Direct16w; resultflags(wrj47);}\n\n# SUB Rm,@WRj\n:SUB rm47_,AtWRjb\tis $(GROUP3) & ophi=9 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { subflags(rm47_,AtWRjb); rm47_ = rm47_ - AtWRjb; resultflags(rm47_);}\n\n# SUB Rm,@DRk\n:SUB rm47_,AtDRkb\tis $(GROUP3) & ophi=9 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { subflags(rm47_,AtDRkb); rm47_ = rm47_ - AtDRkb; resultflags(rm47_);}\n\n\n# XRL Rmd,Rms\n:XRL rm47,rm03\tis $(GROUP3) & ophi=6 & oplo=12; rm47 & rm03 { rm47 = rm47 ^ rm03; resultflags(rm47); }\n\n# XRL WRjd,WRjs\n:XRL wrj47,wrj03\tis $(GROUP3) & ophi=6 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 ^ wrj03; resultflags(wrj47); }\n\n# XRL Rm,#data\n:XRL rm47,Data\tis $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 ^ Data; resultflags(rm47); }\n\n# XRL WRj,#data16\n:XRL wrj47,Data16\tis $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 ^ Data16; resultflags(wrj47); }\n\n# XRL Rm,dir8\n:XRL rm47,Direct\tis $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 ^ Direct; resultflags(rm47); }\n\n# XRL WRj,dir8\n:XRL wrj47,Direct8w\tis $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = wrj47 ^ Direct8w; resultflags(wrj47); }\n\n# XRL Rm,dir16\n:XRL rm47,Direct16b\tis $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 ^ Direct16b; resultflags(rm47); }\n\n# XRL WRj,dir16\n:XRL wrj47,Direct16w\tis $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 ^ Direct16w; resultflags(wrj47); }\n\n# XRL Rm,@Wrj\n:XRL rm47_,AtWRjb\tis $(GROUP3) & ophi=6 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ ^ AtWRjb; resultflags(rm47_); }\n\n# XRL Rm,@Drk\n:XRL rm47_,AtDRkb\tis $(GROUP3) & ophi=6 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ ^ AtDRkb; resultflags(rm47_); }\n" }, { "path": "pypcode/processors/8051/data/languages/80251.slaspec", "content": "@define MCS251 \"\"\n\n@include \"8051_main.sinc\"\n\n@include \"80251.sinc\"\n" }, { "path": "pypcode/processors/8051/data/languages/80390.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/80390.slaspec", "content": "@define MCS80390 \"\"\n\n@include \"8051_main.sinc\"\n" }, { "path": "pypcode/processors/8051/data/languages/8051.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/8051.ldefs", "content": "\n\n\n \n 8051 Microcontroller Family\n \n \n \n \n \n 80251 Microcontroller Family\n \n \n \n 80390 in flat mode\n \n \n \n NXP/Phillips MX51\n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/8051.opinion", "content": "\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/8051.pspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n\t\t \n\t\t \n\t\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/8051.slaspec", "content": "@define MCS51 \"\"\n\n@include \"8051_main.sinc\"\n" }, { "path": "pypcode/processors/8051/data/languages/8051_archimedes.cspec", "content": "\n\n\n\t\n\t\t\n \t\t\n \t\n \t\n \t\n\t\n \n \n\t \n \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t \n\t\t \t\t\n\t \n\t\t\n\t\t \n\t\t \n\t\t \t\t\n\t\t \n\t\t \n\t\t\t\n\t\t\t \t\n\t\t\t\n\t\t \n\t\t\t\n\t\t \n\t\t\t\n\t \n \n\n \n \n \n\t \t\t\n \n \n\t \t\t\n \n \n\t \t\t\n \n \n\t \t\t\n \n \n\t \t\t\n \n \n\t \t\t\n \n \n\t \t\t\n \n \n\t \t\t\n \n\t\n \n \n\t \t\t\n \n \n\t\t\n \t \t\n\t\t\n \n\t\t\n\t \n\t\t\n\t\n\t\n\n\n" }, { "path": "pypcode/processors/8051/data/languages/8051_main.sinc", "content": "# sleigh specification file for Intel 8051\n\n#@define BIT_OPS \"PCODEOPS\"\n#@define BIT_OPS \"SHIFTS\" \n@define BIT_OPS \"BIT_ADDRS\"\n\n# It's sometimes clearer for decompilation to omit the pushing and\n# restoring of the return value for function calls.\n#@define OMIT_RETADDR\n\n# TODO !!! need to fully employ resultflags macro after resolving the use of the above BIT_OPS !!!\n# TODO !!! Need to reconcile use of PSW vs. PSW1 for MCS251 !!!\n# TODO !!! Need to fill-out SFR bits in 80251.pspec !!!\n\n@if defined(ENDIAN)\ndefine endian=$(ENDIAN);\n@else\ndefine endian=big;\n@endif\n\ndefine alignment=1;\n\n@if defined(MCS251)\n\n@define PTRSIZE 3\n@define SP_SIZE 3\n\ndefine space RAM type=ram_space size=3 default;\ndefine space SFR type=ram_space size=2;\ndefine space BITS type=ram_space size=2;\n\n# 8051 spaces map to the following regions of the 80251 RAM space:\n# CODE - 0xff0000-0xffffff\n# EXTERNAL - 0x010000-0x01ffff\n# INTERNAL - 0x000000-0x0000ff\n\n@elif defined(MCS51)\n\n@if defined(PTRSIZE)\n@else\n@define PTRSIZE 2\n@endif\n\n# SP stack pointer should be set to the size of the space it is used in, to avoid \"issues\"\n# This is a minor inconsistency with the model and the actual processor in some cases\n# If pristine SP sizing is required for rollover and such, the model should be changed\n#\n@define SP_SIZE 1\n\ndefine space CODE type=ram_space size=$(PTRSIZE) default;\ndefine space INTMEM type=ram_space size=1;\ndefine space EXTMEM type=ram_space size=2;\ndefine space SFR type=ram_space size=1;\ndefine space BITS type=ram_space size=1;\n\n@elif defined(MCS80390)\n\n@define PTRSIZE 3\n@define SP_SIZE 1\n\ndefine space CODE type=ram_space size=3 default;\ndefine space INTMEM type=ram_space size=1;\ndefine space EXTMEM type=ram_space size=3;\ndefine space SFR type=ram_space size=1;\ndefine space BITS type=ram_space size=1;\n\n@elif defined(MX51)\n\n@define PTRSIZE 3\n@define SP_SIZE 3\n\n# The right thing for decompilation is to represent these\n# as part of one uniform space, similar to the 80251.\n# Remember to load code at 800000\n#\n# xdata 0 (EXTMEM)\n# data 7f0000 (INTMEM)\n# code 800000\n\ndefine space RAM type=ram_space size=3 default;\ndefine space SFR type=ram_space size=1;\ndefine space ESFR type=ram_space size=1;\ndefine space BITS type=ram_space size=1;\ndefine space EBITS type=ram_space size=1;\n\n# Unsure where stack really is, but probably don't want it on normal\n# registers\n#@define STACKBASE 0x7f0100\n@define STACKBASE 0\n\n@else\n# \"error Unknown processor\"\n@endif\n\n\n\ndefine space register type=register_space size=1;\n\n# Register File\ndefine register offset=0x00 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ];\n\n# for future jump table fixup\ndefine register offset=0x70 size=1 [ jumpTableGuard1 jumpTableGuard2 ];\n\n@if defined(MCS251)\n\ndefine register offset=0x08 size=1 [ R8 R9 B ACC R12 R13 R14 R15\n R16 R17 R18 R19 R20 R21 R22 R23\n R24 R25 R26 R27 R28 R29 R30 R31\n];\ndefine register offset=0x0 size=2 [ WR0 WR2 WR4 WR6 WR8 AB WR12 WR14\n WR16 WR18 WR20 WR22 WR24 WR26 WR28 WR30\n];\ndefine register offset=0x0 size=4 [ DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28 ];\n\ndefine register offset=0x38 size=1 [ R56 DPXL DPH DPL R60 R61 SPH ];\ndefine register offset=0x3A size=2 [ DPTR ]; \ndefine register offset=0x38 size=4 [ DPX SPX ];\n\n@elif defined(MCS51) || defined(MCS80390) || defined(MX51)\n\ndefine register offset=0x00 size=4 [ R0R1R2R3 ];\ndefine register offset=0x01 size=3 [ R1R2R3 ]; # Used as R3R2R1 \ndefine register offset=0x01 size=2 [ R2R1 ];\ndefine register offset=0x00 size=2 [ R0R1 R2R3 R4R5 R6R7 ];\ndefine register offset=0x04 size=4 [ R4R5R6R7 ];\ndefine register offset=0x05 size=3 [ R5R6R7 ];\n\ndefine register offset=0x0A size=1 [ B ACC ]; # relocated to facilitate AB 16-bit access\ndefine register offset=0x0A size=2 [ AB ];\n\n@if defined(MCS51) || defined(MX51)\ndefine register offset=0x82 size=2 [ DPTR ];\ndefine register offset=0x82 size=1 [ DPH DPL ]; # relocated to facilitate DPTR 16-bit access\n@elif defined(MCS80390)\n\n# Following existing example, relocated DPX, DPH, and DPL for DPTR\n# access. Rework some direct moves to compensate. Not clear that all\n# cases are covered, thus might be problematic hack in the long term.\ndefine register offset=0x82 size=3 [ DPTR ];\ndefine register offset=0x82 size=1 [ DPX DPH DPL ]; \n@endif\n\n@else\n# \"error Unknown processor\"\n@endif\n\n\ndefine register offset=0x40 size=$(SP_SIZE) [ SP ];\ndefine register offset=0x44 size=$(PTRSIZE) [ PC ];\ndefine register offset=0x48 size=1 [ PSW ];\n@if defined(DUAL_DPTR)\n# Dual DPTR\n# Rather than model it as context, we're just going\n# to special case the INC and DEC instructions\n# to swap the register values\ndefine register offset=0x4a size=2 [ DPTR2 ];\ndefine register offset=$(DPS_REG_NUM) size=1 [ AUXR1 ]; # Bit 0 is DPS\n@endif\n\n@define CY \t\t\"PSW[7,1]\"\n@define AC \t\"PSW[6,1]\"\n@define N \t\"PSW[5,1]\"\n@define RS1 \t\"PSW[4,1]\"\n@define RS0 \t\"PSW[3,1]\"\n@define OV\t\t\"PSW[2,1]\"\n@define Z \t\t\"PSW[1,1]\"\n\n@if defined(MX51)\n# remap these into the normal register file for decompiler use.\n# Really belong on ESFR @0xfc - 0xfe with order EPL EPM EPH\ndefine register offset=0xc0 size=1 [ EPH EPM EPL ];\ndefine register offset=0xc0 size=3 [ EPTR ];\n@endif\n\n@if defined(MCS251)\n\ndefine register offset=0x50 size=4 contextReg;\n\ndefine context contextReg\n\tphase = (0,0)\n\tsrcMode = (1,1) # (reflects UCONFIG0.0) 1: source mode, 0: binary mode\n\tA5Prefix = (2,2) # reflects presence of A5 prefix\n;\n\n# GROUP1 - MCS51 instructions in 0x00-0x5F range\n@define GROUP1 \"epsilon\"\n\n# GROUP2 - MCS51 instructions in 0x60-0xff range\n@define GROUP2 \"((srcMode=0 & A5Prefix=0) | (srcMode=1 & A5Prefix=1))\"\n\n# GROUP3 - MCS251 instructions in 0x60-0xff range\n@define GROUP3 \"((srcMode=0 & A5Prefix=1) | (srcMode=1 & A5Prefix=0))\"\n\n@elif defined(MCS51) || defined(MCS80390) || defined(MX51)\n\n@define GROUP1 \"epsilon\"\n@define GROUP2 \"epsilon\"\n@define GROUP3 \"epsilon\"\n\n@endif\n\ndefine pcodeop decimal_adjust;\ndefine pcodeop nop;\n\n@if BIT_OPS == \"PCODEOPS\"\ndefine pcodeop get;\ndefine pcodeop set;\ndefine pcodeop set_bit_value;\ndefine pcodeop clr;\n@endif\n\n\n#TOKENS\n\ndefine token opbyte (8)\n opfull = (0,7)\n oplo = (0,3)\n ophi = (4,7)\n rn = (0,2)\n rnfill = (3,3)\n ri = (0,0)\n rifill = (1,3)\n opaddr = (5,7)\n addrfill = (4,4)\n \n b_0000 = (0,0)\n b_0001 = (0,1)\n b_0002 = (0,2)\n b_0005 = (0,5)\n b_0101 = (1,1)\n b_0107 = (1,7)\n b_0207 = (2,7)\n b_0307 = (3,7)\n b_0607 = (6,7)\n@if defined(MX51)\n PRi_sel = (2,2)\n PRi_revend = (2,2) # reverse endian\n emov_delta = (0,1)\n@endif\n;\ndefine token AddrByte (8)\n direct = (0,7)\n bank = (7,7)\n sfr = (0,6)\n sfr6 = (6,6)\n sfrlo = (0,3)\n mainreg = (0,6)\n direct17 = (1,7)\n;\ndefine token AddrByte2 (8)\n direct2 = (0,7)\n bank2 = (7,7)\n sfr2 = (0,6)\n sfr26 = (6,6)\n sfr2lo = (0,3)\n mainreg2 = (0,6)\n;\ndefine token BitByte (8)\n bitaddr8 = (0,7)\n bitaddr27 = (2,7)\n bitbank = (7,7)\n sfrbyte = (3,7)\n bitaddr57 = (5,7)\n sfrbit6 = (6,6)\n sfrbit3 = (3,3)\n sfrbit = (0,2) dec\n lowbyte = (3,6)\n bitaddr0 = (0,0)\n;\ndefine token AddrTwo (16)\n addr16 = (0,15)\n;\n@if defined(MCS80390)\n# todo: deconflict with 80251 version\ndefine token AddrThree (24)\n addr24 = (0,23)\n;\n@endif\n\ndefine token RelByte (8) rel8=(0,7) signed;\ndefine token ImmedByte (8) data=(0,7);\ndefine token ImmedTwo (16)\n data16 = (0,15)\n rel16 = (0,15) signed\n;\n@if defined(MCS80390)\ndefine token ImmedThree (24)\n data24 = (0,23)\n;\n@endif\n\n@if defined(MCS80390)\ndefine token aopword (24)\n aoplo = (16,19)\n aopaddr = (21,23)\n aaddrfill = (20,20)\n adata = (0,15)\n;\n@else\ndefine token aopword (16)\n aoplo = (8,11)\n aopaddr = (13,15)\n aaddrfill = (12,12)\n adata = (0,7)\n;\n@endif\n\nattach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];\nattach variables ri [ R0 R1 ];\n\n# flags macros\n\n#macro addflags(op1, op2) { # Flags set by add instructions\n# PSW = PSW & 0x7b;\n# PSW = PSW | (carry(op1,op2)<<7) # Check for carry\n# | (scarry(op1,op2)<<2); # Check for signed carry\n#}\n\n#macro subflags(op1, op2) { # Flags set by sub instructions\n# PSW = PSW & 0x7b;\n# PSW = PSW | ((op1>sfrbit)&1); resultflags(tmp); }\n:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {tmp:1 = BitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); }\n@if BIT_OPS == \"BIT_ADDRS\"\n:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& BitAddr; }\n:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& ~BitAddr2; }\n@elif BIT_OPS == \"PCODEOPS\"\n:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& get(BitAddr, BitByteAddr); }\n:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& (get(BitAddr2, BitByteAddr)^1); }\n@elif BIT_OPS == \"SHIFTS\"\n:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit\t& BitByteAddr {$(CY)=$(CY)& ((BitByteAddr>>sfrbit)&1); }\n:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit\t& BitByteAddr {$(CY)=$(CY)& (~((BitByteAddr>>sfrbit)&1)); }\n@endif\n\n:CJNE Areg,Direct,Rel8 is $(GROUP1) & ophi=11 & oplo=5 & Areg; Direct; Rel8\t { compflags(ACC,Direct); if (ACC!=Direct) goto Rel8; }\n:CJNE Areg,Data,Rel8 is $(GROUP1) & ophi=11 & oplo=4 & Areg; Data; Rel8\t { compflags(ACC,Data); if (ACC!=Data) goto Rel8; }\n:CJNE rn,Data,Rel8 is $(GROUP2) & ophi=11 & rnfill=1 & rn; Data; Rel8\t\t\t\t { compflags(rn,Data); if (rn!=Data) goto Rel8; }\n:CJNE Ri,Data,Rel8 is $(GROUP2) & ophi=11 & rifill=3 & Ri; Data; Rel8\t\t\t\t { compflags(Ri,Data); if (Ri!=Data) goto Rel8; }\n\n:CLR Areg is $(GROUP1) & ophi=14 & oplo=4 & Areg \t\t\t { ACC = 0; }\n:CLR CY is $(GROUP1) & CY & ophi=12 & oplo=3\t\t\t\t {$(CY)= 0; }\n\n:CLR BitAddr is $(GROUP1) & ophi=12 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { local tmp = ~(1<>sfrbit)&1) == 1:1) goto Rel8; }\n:JBC BitAddr,Rel8 is $(GROUP1) & ophi=1 & oplo=0; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr; Rel8\t { tmp:1 = 1<>sfrbit)&1) == 1:1) goto Rel8; }\n:JBC BitAddr,Rel8 is $(GROUP1) & ophi=1 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8\t { tmp:1 = 1<>sfrbit)&1)==0:1) goto Rel8; }\n@if BIT_OPS == \"BIT_ADDRS\"\n:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (BitAddr == 0:1) goto Rel8; }\n@elif BIT_OPS == \"PCODEOPS\"\n:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (get(BitAddr, BitByteAddr)==0:1) goto Rel8; }\n@elif BIT_OPS == \"SHIFTS\"\n:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (((BitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }\n@endif\n\n:JNC Rel8 is $(GROUP1) & ophi=5 & oplo=0; Rel8\t\t\t\t\t { if ($(CY) == 0) goto Rel8; }\n:JNZ Rel8 is $(GROUP1) & ophi=7 & oplo=0; Rel8\t\t\t\t\t { if (ACC != 0) goto Rel8; }\n:JZ Rel8 is $(GROUP1) & ophi=6 & oplo=0; Rel8\t\t\t\t\t { if (ACC == 0) goto Rel8; }\n\n@if defined(MCS80390)\n:LCALL Addr24 is $(GROUP1) & ophi=1 & oplo=2; Addr24\t{ ret:$(PTRSIZE) = inst_next; push24(ret); call Addr24; }\n:LJMP Addr24 is $(GROUP1) & ophi=0 & oplo=2; Addr24\t{ goto Addr24; }\n@elif defined(MX51)\n:LCALL Addr16 is $(GROUP1) & ophi=1 & oplo=2; Addr16\t{ ret:2 = inst_next; push16(ret); call Addr16; }\n:LJMP Addr16 is $(GROUP1) & ophi=0 & oplo=2; Addr16\t{ goto Addr16; }\n@else\n:LCALL Addr16 is $(GROUP1) & ophi=1 & oplo=2; Addr16\t{ ret:$(PTRSIZE) = inst_next; push16(ret); call Addr16; }\n:LJMP Addr16 is $(GROUP1) & ophi=0 & oplo=2; Addr16\t{ goto Addr16; }\n@endif\n\n:MOV Areg,rn is $(GROUP2) & ophi=14 & rnfill=1 & rn & Areg\t\t\t\t\t { ACC = rn; }\n:MOV Areg,Direct is $(GROUP1) & ophi=14 & oplo=5 & Areg; Direct\t\t { ACC = Direct; }\n:MOV Areg,Ri is $(GROUP2) & ophi=14 & Areg & rifill=3 & Ri\t\t\t\t\t { ACC = Ri; }\n:MOV Areg,Data is $(GROUP1) & ophi=7 & oplo=4 & Areg; Data\t { ACC = Data; }\n:MOV rn,Areg is $(GROUP2) & ophi=15 & rnfill=1 & rn & Areg\t\t\t\t\t { rn = ACC; }\n:MOV rn,Direct is $(GROUP2) & ophi=10 & rnfill=1 & rn; Direct\t\t\t\t { rn = Direct; }\n:MOV rn,Data is $(GROUP2) & ophi=7 & rnfill=1 & rn; Data\t\t\t\t { rn = Data; }\n:MOV Direct,Areg is $(GROUP1) & ophi=15 & oplo=5 & Areg; Direct\t\t { Direct = ACC; }\n:MOV Direct,rn is $(GROUP2) & ophi=8 & rnfill=1 & rn; Direct\t\t\t\t\t { Direct = rn; }\n:MOV Direct2,Direct is $(GROUP1) & ophi=8 & oplo=5; Direct; Direct2\t { Direct2 = Direct; }\n:MOV Direct,Ri is $(GROUP2) & ophi=8 & rifill=3 & Ri; Direct\t\t\t\t\t { Direct = Ri; }\n:MOV Direct,Data is $(GROUP1) & ophi=7 & oplo=5; Direct; Data\t\t { Direct = Data; }\n:MOV Ri,Areg is $(GROUP2) & ophi=15 & rifill=3 & Ri & Areg\t\t\t\t\t { Ri = ACC; }\n:MOV Ri,Direct is $(GROUP2) & ophi=10 & rifill=3 & Ri; Direct\t\t\t\t { Ri = Direct; }\n:MOV Ri,Data is $(GROUP2) & ophi=7 & rifill=3 & Ri; Data\t\t\t\t\t { Ri = Data; }\n@if defined(MCS80390)\n:MOV DPTRreg,Data24 is $(GROUP1) & ophi=9 & oplo=0 & DPTRreg; Data24\t { DPTR = Data24; }\n@else\n:MOV DPTRreg,Data16 is $(GROUP1) & ophi=9 & oplo=0 & DPTRreg; Data16\t { DPTR = Data16; }\n@endif\n\n:MOV CY,BitAddr is $(GROUP1) & CY & ophi=10 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {$(CY)= (BitByteAddr>>sfrbit)&1; }\n:MOV BitAddr,CY is $(GROUP1) & CY & ophi=9 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr & (~(1<>sfrbit)&1; }\n:MOV BitAddr,CY is $(GROUP1) & CY & ophi=9 & oplo=2; BitAddr & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr & (~(1<>sfrbit)&1); }\n:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {$(CY)=$(CY)| (((BitByteAddr>>sfrbit)&1)^1); }\n@if BIT_OPS == \"BIT_ADDRS\"\n:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| BitAddr; }\n:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (BitAddr2^1); }\n@elif BIT_OPS == \"PCODEOPS\"\n:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| get(BitAddr, BitByteAddr); }\n:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (get(BitAddr2, BitByteAddr)^1); }\n@elif BIT_OPS == \"SHIFTS\"\n:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| ((BitByteAddr>>sfrbit)&1); }\n:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (((BitByteAddr>>sfrbit)&1)^1); }\n@endif\n\n:POP Direct is $(GROUP1) & ophi=13 & oplo=0; Direct\t{ pop8(Direct); }\n\n:PUSH Direct is $(GROUP1) & ophi=12 & oplo=0; Direct\t{ push8(Direct); }\n\n:RET is $(GROUP1) & ophi=2 & oplo=2\t{ \n@if defined(MCS251) || defined(MX51)\npc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; \n@elif defined(MCS51)\npc:2 = 0; pop16(pc); return[pc]; \n@elif defined(MCS80390)\npc:3 = 0; pop24(pc); return[pc]; \n@endif\n}\n\n:RETI is $(GROUP1) & ophi=3 & oplo=2\t{ \n@if defined(MCS251) || defined(MX51)\npc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; \n@elif defined(MCS51)\npc:2 = 0; pop16(pc); return[pc]; \n@elif defined(MCS80390)\npc:3 = 0; pop24(pc); return[pc]; \n@endif\n}\n\n:RL Areg is $(GROUP1) & ophi=2 & oplo=3 & Areg\t { ACC = (ACC<<1) | (ACC>>7); }\n:RLC Areg is $(GROUP1) & ophi=3 & oplo=3 & Areg\t { tmp : 1 = (ACC&0x80)>>7; ACC = (ACC<<1) | $(CY);$(CY)= tmp; }\n:RR Areg is $(GROUP1) & ophi=0 & oplo=3 & Areg\t { ACC = (ACC>>1) | (ACC<<7); }\n:RRC Areg is $(GROUP1) & ophi=1 & oplo=3 & Areg\t { tmp : 1 = ACC&1; ACC = (ACC>>1) | ($(CY)<<7);$(CY)= tmp; }\n\n:SETB CY is $(GROUP1) & CY & ophi=13 & oplo=3\t\t\t\t\t { $(CY)=1; }\n\n:SETB BitAddr is $(GROUP1) & ophi=13 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr | (1<>4) | (ACC<<4); }\n\n:XCH Areg,rn is $(GROUP2) & ophi=12 & rnfill=1 & rn & Areg\t\t\t { tmp : 1 = ACC; ACC = rn; rn = tmp; }\n:XCH Areg,Direct is $(GROUP1) & ophi=12 & oplo=5 & Areg; Direct { tmp : 1 = ACC; ACC = Direct; Direct = tmp; }\n:XCH Areg,Ri is $(GROUP2) & ophi=12 & rifill=3 & Ri & Areg\t\t\t { tmp : 1 = ACC; ACC = Ri; Ri = tmp; }\n\n# TODO: This instruction appears to be in both GROUP2 & GROUP3 (always available)\n:XCHD Areg,Ri is ophi=13 & Areg & rifill=3 & Ri\t\t\t\t{ tmp : 1 = ACC & 0xf; ACC = (ACC&0xf0) | (Ri&0xf); Ri = (Ri&0xf0) | tmp; }\n\n:XRL Areg,rn is $(GROUP2) & ophi=6 & rnfill=1 & rn & Areg\t\t\t\t{ ACC = ACC ^ rn; }\n:XRL Areg,Direct is $(GROUP1) & ophi=6 & oplo=5 & Areg; Direct\t{ ACC = ACC ^ Direct; }\n:XRL Areg,Ri is $(GROUP2) & ophi=6 & rifill=3 & Ri & Areg\t\t\t\t{ ACC = ACC ^ Ri; }\n:XRL Areg,Data is $(GROUP1) & ophi=6 & oplo=4 & Areg; Data\t{ ACC = ACC ^ Data; }\n:XRL Direct,Areg is $(GROUP1) & ophi=6 & oplo=2 & Areg; Direct\t{ Direct = Direct ^ ACC; }\n:XRL Direct,Data is $(GROUP1) & ophi=6 & oplo=3; Direct; Data\t{ Direct = Direct ^ Data; }\n\n" }, { "path": "pypcode/processors/8051/data/languages/mx51.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/mx51.pspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8051/data/languages/mx51.sinc", "content": "# Extended mx51 instructions live here, so as to avoid further\n# complicating the main 8051 file.\n\n# All have 0xa5 as prefix, so subtract one\ndefine token TwoByteOp (8)\n b2op = (0,7)\n;\ndefine token ThreeByteOp (16)\n b3op = (8,15)\n;\ndefine token FourByteOp (24)\n b4op = (16,23)\n;\n\ndefine token EcallDispTok (24)\n imm24 = (0,23)\n;\n\n####################\n\n# Note that PRi is used in little endian format, as R3 is the MSB\nattach variables PRi_revend [ R1R2R3 R5R6R7 ];\n@define ENDIANSWAPFUNC \"\"\n@if defined(ENDIANSWAPFUNC)\ndefine pcodeop endian_swap;\nPRi: PRi_revend is PRi_revend { tmp:3 = endian_swap(PRi_revend); export tmp; }\n@else\nPRi: PRi_revend is PRi_sel=0 & PRi_revend { tmp:3 = (zext(R3) << 16) | (zext(R2) << 8) | zext(R1); export tmp; }\nPRi: PRi_revend is PRi_sel=1 & PRi_revend { tmp:3 = (zext(R7) << 16) | (zext(R6) << 8) | zext(R5); export tmp; }\n@endif\n####################\n\n@ifdef OMIT_RETADDR\nmacro push24(val) { val = val; }\nmacro pop24(val) { val = val; }\n\n@else\n# stack grows up.\nmacro push24(val) {\n ptr:3 = zext(SP) + 1 + $(STACKBASE);\n *[RAM]:3 ptr = val;\n SP = SP + 2;\n}\nmacro pop24(val) {\n ptr:3 = zext(SP - 2) + $(STACKBASE);\n val = *[RAM]:3 ptr;\n SP = SP - 3;\n}\n@endif\n\n####################\n\neptrReg: EPTR is EPTR { export EPTR; }\nAPlusEptr: \"@\"Areg\"+\"eptrReg is Areg & eptrReg\t{ tmp:3 = EPTR + zext(ACC); export tmp; }\necallImmAddr: imm24 is imm24 { export *:1 imm24; }\nadd_with_pr_const: emov_delta is emov_delta { tmp:1 = emov_delta; export tmp; }\nadd_with_pr_const: \"4\" is emov_delta = 0 { tmp:1 = 4; export tmp; }\n\nEDirect: mainreg is bank=0 & mainreg\t{ tmp:3 = mainreg + 0x7f0000; export *[RAM]:1 tmp; }\nEDirect: direct is bank=1 & direct \t{ export *[ESFR]:1 direct; }\nEDirect: EPL is bank=1 & direct=0xfc & EPL \t{ export EPL; }\nEDirect: EPM is bank=1 & direct=0xfd & EPM \t{ export EPM; }\nEDirect: EPH is bank=1 & direct=0xfe & EPH \t{ export EPH; }\n\nEDirect2: mainreg2 is bank2=0 & mainreg2\t{ tmp:3 = mainreg2 + 0x7f0000; export *[RAM]:1 tmp; }\nEDirect2: direct2 is bank2=1 & direct2 \t{ export *[ESFR]:1 direct2; }\nEDirect2: EPL is bank2=1 & direct2=0xfc & EPL \t{ export EPL; }\nEDirect2: EPM is bank2=1 & direct2=0xfd & EPM \t{ export EPM; }\nEDirect2: EPH is bank2=1 & direct2=0xfe & EPH \t{ export EPH; }\n\n# Continuing with pattern via copying from stock 8051 sleighspec. \n# Note that there is a known bug with the Bit addressing of the SFR.\nEBitAddr: bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }\nEBitAddr: bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }\nEBitAddr2: \"/\"bitaddr is bitbank=1 & sfrbyte & sfrbit\t [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }\nEBitAddr2: \"/\"bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }\n\nEBitByteAddr: byteaddr \tis bitbank=1 & sfrbyte & sfrbit [ byteaddr =(sfrbyte << 3); ] { export *[ESFR]:1 byteaddr; }\nEBitByteAddr: byteaddr \tis bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { tmp:3 = byteaddr + 0x7f0000; export *[RAM]:1 tmp; }\n\n\n####################\n\n:inc EDirect is opfull=0xa5; ophi=0 & oplo=5; EDirect { \n EDirect = EDirect + 1; \n}\n:dec EDirect is opfull=0xa5; opfull=0x15; EDirect { \n EDirect = EDirect - 1;\n}\n:add Areg,EDirect is opfull=0xa5; opfull=0x25 & Areg; EDirect { \n addflags(ACC,EDirect); ACC = ACC + EDirect; resultflags(ACC);\n}\n:addc Areg,EDirect is opfull=0xa5; opfull=0x35 & Areg; EDirect { \n tmp:1 =$(CY)+ EDirect; addflags(ACC,tmp); ACC = ACC + tmp; resultflags(ACC);\n}\n:orl Areg,EDirect is opfull=0xa5; opfull=0x45 & Areg; EDirect { \n ACC = ACC | EDirect;\n}\n:anl Areg,EDirect is opfull=0xa5; opfull=0x55 & Areg; EDirect { \n ACC = ACC & EDirect; resultflags(ACC); \n}\n:xrl Areg,EDirect is opfull=0xa5; opfull=0x65 & Areg; EDirect { \n ACC = ACC ^ EDirect;\n}\n:subb Areg,EDirect is opfull=0xa5; opfull=0x95 & Areg; EDirect { \n tmp:1 = EDirect+$(CY); subflags(ACC,tmp); ACC = ACC - tmp;\n}\n:xch Areg,EDirect is opfull=0xa5; opfull=0xc5 & Areg; EDirect { \n tmp:1 = ACC; ACC = EDirect; EDirect = tmp;\n}\n:mov Areg,EDirect is opfull=0xa5; opfull=0xe5 & Areg; EDirect { \n ACC = EDirect;\n}\n:mov EDirect,Areg is opfull=0xa5; opfull=0xf5 & Areg; EDirect { \n EDirect = ACC;\n}\n:mov EDirect,rn is opfull=0xa5; ophi=0x8 & rnfill=1 & rn; EDirect {\n EDirect = rn;\n}\n:mov rn,EDirect is opfull=0xa5; ophi=0xa & rnfill=1 & rn; EDirect {\n rn = EDirect;\n}\n:mov EDirect2,EDirect is opfull=0xa5; ophi=8 & oplo=5; EDirect; EDirect2 { \n EDirect2 = EDirect; \n}\n:mov EDirect,Data is opfull=0xa5; ophi=7 & oplo=5; EDirect; Data { \n EDirect = Data; \n}\n:mov EDirect,Ri is opfull=0xa5; ophi=8 & rifill=3 & Ri; EDirect { \n EDirect = Ri; \n}\n:mov Ri,EDirect is opfull=0xa5; ophi=10 & rifill=3 & Ri; EDirect { \n Ri = EDirect; \n}\n:orl EDirect,Areg is opfull=0xa5; ophi=4 & oplo=2 & Areg; EDirect { \n EDirect = EDirect | ACC; \n}\n:anl EDirect,Areg is opfull=0xa5; ophi=5 & oplo=2 & Areg; EDirect { \n tmp:1 = EDirect & ACC; EDirect = tmp; resultflags(tmp); \n}\n:xrl EDirect,Areg is opfull=0xa5; ophi=6 & oplo=2 & Areg; EDirect { \n EDirect = EDirect ^ ACC; \n}\n:xrl EDirect,Data is opfull=0xa5; ophi=6 & oplo=3; EDirect; Data { \n EDirect = EDirect ^ Data; \n}\n:anl EDirect,Data is opfull=0xa5; ophi=5 & oplo=3; EDirect; Data { \n tmp:1 = EDirect & Data; EDirect = tmp; resultflags(tmp); \n}\n:orl EDirect,Data is opfull=0xa5; ophi=4 & oplo=3 & Areg; EDirect; Data { \n EDirect = EDirect | Data; \n}\n:push EDirect is opfull=0xa5; opfull=0xc0; EDirect { \n push8(EDirect);\n}\n:pop EDirect is opfull=0xa5; opfull=0xd0; EDirect { \n pop8(EDirect);\n}\n:cjne Areg,EDirect,Rel8 is opfull=0xa5; ophi=11 & oplo=5 & Areg; EDirect; Rel8\t { \n compflags(ACC,EDirect); if (ACC!=EDirect) goto Rel8; \n}\n:djnz EDirect,Rel8 is opfull=0xa5; ophi=13 & oplo=5; EDirect; Rel8 { \n EDirect = EDirect - 1; \n if (EDirect!=0) goto Rel8; \n}\n\n\n# EPTR operations\n:ejmp ecallImmAddr is opfull=0xa5; opfull=0x02; ecallImmAddr { \n goto ecallImmAddr;\n}\n:ecall ecallImmAddr is opfull=0xa5; opfull=0x12; ecallImmAddr { \n ret:3 = inst_next; push24(ret); call ecallImmAddr;\n}\n:mov eptrReg,ecallImmAddr is opfull=0xa5; opfull=0x90; ecallImmAddr & eptrReg & imm24 { \n EPTR = imm24;\n}\n:eret is opfull=0xa5; opfull=0x22 { \n pc:3 = 0; pop24(pc); return[pc]; \n}\n:jmp APlusEptr is opfull=0xa5; opfull=0x73 & APlusEptr { \n # this is correct, but causes disassembler problems\n # goto APlusEptr; \n # added additional indirection to stop disassembler problems.\n goto [APlusEptr]; \n}\n:movx Areg\",@\"eptrReg is opfull=0xa5; opfull=0xe0 & Areg & eptrReg { \n ACC = *:1 EPTR;\n}\n:movx \"@\"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg { \n *:1 EPTR = ACC;\n}\n:movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr { \n ACC = *:1 APlusEptr;\n}\n:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR { \n EPTR = EPTR + 1;\n}\n\n# PRi operations\n:emov Areg\",@\"PRi\"+\"emov_delta is opfull=0xa5; ophi=4 & PRi & emov_delta & Areg { \n tmp:3 = zext(PRi) + emov_delta;\n ACC = *:1 tmp;\n}\n:emov \"@\"PRi\"+\"emov_delta,Areg is opfull=0xa5; ophi=5 & PRi & emov_delta & Areg { \n tmp:3 = PRi + emov_delta;\n *:1 tmp = ACC;\n}\n:add PRi_revend,add_with_pr_const is opfull=0xa5; ophi=6 & PRi_revend & PRi & add_with_pr_const { \n x:3 = zext(add_with_pr_const);\n tmp:3 = PRi + x;\n@if defined(ENDIANSWAPFUNC)\n y:3 = endian_swap(tmp);\n@else\n y:3 = (tmp << 16) | (tmp & 0x00ff00) | zext(tmp >> 16);\n@endif\n PRi_revend = y;\n}\n\n# bit operations\n:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& ((tmp>>sfrbit)&1); resultflags(tmp); }\n:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); }\n@if BIT_OPS == \"BIT_ADDRS\"\n:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& EBitAddr; }\n:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& ~EBitAddr2; }\n@elif BIT_OPS == \"PCODEOPS\"\n:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& get(EBitAddr, EBitByteAddr); }\n:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (get(EBitAddr2, EBitByteAddr)^1); }\n@elif BIT_OPS == \"SHIFTS\"\n:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit\t& EBitByteAddr {$(CY)=$(CY)& ((EBitByteAddr>>sfrbit)&1); }\n:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit\t& EBitByteAddr {$(CY)=$(CY)& (~((EBitByteAddr>>sfrbit)&1)); }\n@endif\n\n:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = ~(1<>sfrbit)&1) == 1:1) goto Rel8; }\n:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8\t { tmp:1 = 1<>sfrbit)&1) == 1:1) goto Rel8; }\n:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8\t { tmp:1 = 1<>sfrbit)&1)==0:1) goto Rel8; }\n@if BIT_OPS == \"BIT_ADDRS\"\n:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto Rel8; }\n@elif BIT_OPS == \"PCODEOPS\"\n:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==0:1) goto Rel8; }\n@elif BIT_OPS == \"SHIFTS\"\n:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }\n@endif\n\n:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)= (EBitByteAddr>>sfrbit)&1; }\n:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<>sfrbit)&1; }\n:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<>sfrbit)&1); }\n:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }\n@if BIT_OPS == \"BIT_ADDRS\"\n:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| EBitAddr; }\n:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (EBitAddr2^1); }\n@elif BIT_OPS == \"PCODEOPS\"\n:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| get(EBitAddr, EBitByteAddr); }\n:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (get(EBitAddr2, EBitByteAddr)^1); }\n@elif BIT_OPS == \"SHIFTS\"\n:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); }\n:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }\n@endif\n\n:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1<\n\n \n 8051:BE:16:default\n 8051\n default\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/8051/data/languages/old/8051v1.trans", "content": "\n\n 8051:BE:16:default\n 8051:BE:16:default\n \n \n\n\n" }, { "path": "pypcode/processors/8051/data/manuals/8051.idx", "content": "@8xc251sx_um.pdf [8XC251SA, 8XC251SB,8XC251SP, 8XC251SQ Embedded Microcontroller User�s Manual, May 1996]\nACALL, 278\nADD, 279\nADDC, 284\nAJMP, 286\nANL, 286\nCJNE, 294\nCLR, 295\nCMP, 295\nCPL, 301\nDA, 303\nDEC, 304\nDIV, 307\nDJNZ, 309\nECALL, 311\nEJMP, 312\nERET, 313\nINC, 313\nJB, 317\nJBC, 318\nJC, 319\nJE, 320\nJG, 320\nJLE, 321\nJMP, 322\nJNB, 322\nJNC, 324\nJNE, 324\nJNZ, 325\nJSG, 326\nJSGE, 326\nJSL, 327\nJSLE, 328\nJZ, 328\nLCALL, 329\nLJMP, 330\nMOV, 331\nMOVC, 348\nMOVH, 349\nMOVS, 349\nMOVX, 350\nMOVZ, 352\nMUL, 353\nNOP, 355\nORL, 355\nPOP, 362\nPUSH, 364\nRET, 366\nRETI, 367\nRL, 368\nRLC, 368\nRR, 369\nRRC, 370\nSETB, 370\nSJMP, 371\nSLL, 372\nSRA, 373\nSRL, 374\nSUB, 374\nSUBB, 379\nSWAP, 381\nTRAP, 381\nXCH, 382\nXCHD, 383\nXRL, 384\n" }, { "path": "pypcode/processors/8085/data/languages/8085.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8085/data/languages/8085.ldefs", "content": "\n\n\n \n Intel 8085\n \n \n\n" }, { "path": "pypcode/processors/8085/data/languages/8085.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/8085/data/languages/8085.slaspec", "content": "# sleigh specification file for Intel 8085\n\ndefine endian=little;\ndefine alignment=1;\n\ndefine space ram type=ram_space size=2 default;\ndefine space io type=ram_space size=1;\ndefine space register type=register_space size=1;\n\ndefine register offset=0x00 size=1 [ F A C B E D L H ];\ndefine register offset=0x00 size=2 [ AF BC DE HL ];\ndefine register offset=0x10 size=1 [ A_ F_ B_ C_ D_ E_ H_ L_ ]; # Alternate registers\ndefine register offset=0x10 size=2 [ AF_ BC_ DE_ HL_ ]; # Alternate registers\ndefine register offset=0x20 size=2 [ PC SP ];\n\n# Flag bits\n# CY: Carry\n# P: Parity/Overflow\n# AC: Half Carry (Auxiliary flag)\n# Z: Zero\n# S: Sign\ndefine register offset=0x30 size=1 [ S_flag Z_flag AC_flag P_flag CY_flag ];\n\ndefine token opbyte (8)\n op0_8 = (0,7)\n op6_2 = (6,7)\n \n dRegPair4_2 = (4,5)\n pRegPair4_2 = (4,5)\n sRegPair4_2 = (4,5)\n qRegPair4_2 = (4,5)\n rRegPair4_2 = (4,5)\n\n reg3_3 = (3,5)\n bits3_3 = (3,5)\n \n bits0_4 = (0,3)\n \n reg0_3 = (0,2)\n bits0_3 = (0,2)\n;\n\ndefine token data8 (8)\n imm8\t\t= (0,7)\n sign8\t= (7,7)\n simm8\t= (0,7) signed\n;\n\ndefine token data16 (16)\n imm16 = (0,15)\n sign16\t\t= (15,15)\n simm16\t\t= (0,15) signed\n;\n\nattach variables [ reg0_3 reg3_3 ] [ B C D E H L _ A ];\n\nattach variables [ sRegPair4_2 dRegPair4_2 ] [ BC DE HL SP ];\nattach variables [ qRegPair4_2 ] [ BC DE HL AF ];\n\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop BCDadjust;\ndefine pcodeop hasEvenParity;\ndefine pcodeop disableMaskableInterrupts;\ndefine pcodeop enableMaskableInterrupts;\ndefine pcodeop readInterruptMask;\ndefine pcodeop setInterruptMask;\n\n################################################################\n# Macros\n################################################################\n\nmacro setResultFlags(result) {\n\tZ_flag = (result == 0);\n\tS_flag = (result s< 0);\n}\n\nmacro setAddCarryFlags(op1,op2) {\n\tCY_flag = (carry(op1,zext(CY_flag)) || carry(op2,op1 + zext(CY_flag)));\n#\tP_flag = (scarry(op1,CY_flag) || scarry(op2,op1 + CY_flag));\n# AC_flag = ??\n}\n\nmacro setAddFlags(op1,op2) {\n\tCY_flag = carry(op1,op2);\n#\tP_flag = scarry(op1,op2);\n# AC_flag = ??\n}\n\nmacro setSubtractCarryFlags(op1,op2) {\n\tlocal notC = ~CY_flag;\n\tCY_flag = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC))));\n}\n\nmacro setSubtractFlags(op1,op2) {\n\tCY_flag = (op1 < op2);\n}\n\nmacro push16(val16) {\n\tSP = SP - 2;\n\t*:2 SP = val16; \n}\n\nmacro pop16(ret16) {\n\tret16 = *:2 SP;\n\tSP = SP + 2; \n}\n\n################################################################\n\nMem8: (imm16)\t\tis imm16\t\t\t\t\t\t\t\t\t{ export *:1 imm16; }\nMem16: (imm16)\t\tis imm16\t\t\t\t\t\t\t\t\t{ export *:2 imm16; }\n\nAddr16: imm16\t\tis imm16\t\t\t\t\t\t\t\t\t{ export *:1 imm16; }\n\nRstAddr: loc\t\tis bits3_3 [ loc = bits3_3 << 3; ]\t\t\t{ export *:1 loc; }\n\nIOAddr8: (imm8)\tis imm8\t\t\t\t\t\t\t\t\t\t\t{ export *[io]:1 imm8; }\n\ncc: \"NZ\" is bits3_3=0x0 { c:1 = (Z_flag == 0); export c; }\ncc: \"Z\" is bits3_3=0x1 { export Z_flag; }\ncc: \"NC\" is bits3_3=0x2 { c:1 = (CY_flag == 0); export c; }\ncc: \"C\" is bits3_3=0x3 { export CY_flag; }\ncc: \"PO\" is bits3_3=0x4 { c:1 = (P_flag == 0); export c; }\ncc: \"PE\" is bits3_3=0x5 { export P_flag; }\ncc: \"P\" is bits3_3=0x6 { c:1 = (S_flag == 0); export c; }\ncc: \"M\" is bits3_3=0x7 { export S_flag; }\n\n################################################################\n\n:MOV reg3_3,reg0_3 is op6_2=0x1 & reg3_3 & reg0_3 {\n\treg3_3 = reg0_3;\n}\n\n:MVI reg3_3,imm8 is op6_2=0x0 & reg3_3 & bits0_3=0x6; imm8 {\n\treg3_3 = imm8;\n}\n\n:MOV reg3_3,(HL) is op6_2=0x1 & reg3_3 & bits0_3=0x6 & HL {\n\tptr:2 = HL;\n\treg3_3 = *:1 ptr; \n}\n\n:MOV (HL),reg0_3 is op6_2=0x1 & bits3_3=0x6 & reg0_3 & HL {\n\tptr:2 = HL;\n\t*:1 ptr = reg0_3; \n}\n\n:MVI (HL),imm8 is op0_8=0x36 & HL; imm8 {\n\tptr:2 = HL;\n\t*:1 ptr = imm8; \n}\n\n:LDAX (BC) is op0_8=0x0a & BC {\n\tptr:2 = BC;\n\tA = *:1 ptr;\n}\n\n:LDAX (DE) is op0_8=0x1a & DE {\n\tptr:2 = DE;\n\tA = *:1 ptr;\n}\n\n:LDA Mem8 is op0_8=0x3a; Mem8 {\n\tA = Mem8;\n}\n\n:STAX (BC) is op0_8=0x2 & BC {\n\tptr:2 = BC;\n\t*:1 ptr = A;\n}\n\n:STAX (DE) is op0_8=0x12 & DE {\n\tptr:2 = DE;\n\t*:1 ptr = A;\n}\n\n:STA Mem8 is op0_8=0x32; Mem8 {\n\tMem8 = A;\n}\n\n:LXI dRegPair4_2,imm16 is op6_2=0x0 & dRegPair4_2 & bits0_4=0x1; imm16 {\n\tdRegPair4_2 = imm16;\n}\n\n:LHLD Mem16 is op0_8=0x2a; Mem16 {\n\tHL = Mem16;\n}\n\n:SHLD Mem16 is op0_8=0x22; Mem16 {\n\tMem16 = HL;\n}\n\n:SPHL is op0_8=0xf9 {\n\tSP = HL;\n}\n\n:PUSH qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x5 {\n\tpush16(qRegPair4_2);\n}\n\n:POP qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x1 {\n\tpop16(qRegPair4_2);\n}\n\n:XCHG is op0_8=0xeb {\n\ttmp:2 = DE;\n\tDE = HL;\n\tHL = tmp;\t\n}\n\n:XTHL is op0_8=0xe3 {\n\ttmp:2 = *:2 SP;\n\t*:2 SP = HL;\n\tHL = tmp;\n}\n\n:ADD reg0_3 is op6_2=0x2 & bits3_3=0x0 & reg0_3 {\n\tsetAddFlags(A,reg0_3);\n\tA = A + reg0_3;\n\tsetResultFlags(A);\n}\n\n:ADI imm8 is op0_8=0xc6; imm8 {\n\tsetAddFlags(A,imm8);\n\tA = A + imm8;\n\tsetResultFlags(A);\n}\n\n:ADD (HL) is op0_8=0x86 & HL {\n\tval:1 = *:1 HL;\n\tsetAddFlags(A,val);\n\tA = A + val;\n\tsetResultFlags(A);\n}\n\n:ADC reg0_3 is op6_2=0x2 & bits3_3=0x1 & reg0_3 {\n\tsetAddCarryFlags(A,reg0_3);\n\tA = A + reg0_3 + CY_flag;\n\tsetResultFlags(A);\n}\n\n:ACI imm8 is op0_8=0xce; imm8 {\n\tsetAddCarryFlags(A,imm8);\n\tA = A + imm8 + CY_flag;\n\tsetResultFlags(A);\n}\n\n:ADC (HL) is op0_8=0x8e & HL {\n\tval:1 = *:1 HL;\n\tsetAddCarryFlags(A,val);\n\tA = A + val + CY_flag;\n\tsetResultFlags(A);\n}\n\n:SUB reg0_3 is op6_2=0x2 & bits3_3=0x2 & reg0_3 {\n\tsetSubtractFlags(A,reg0_3);\n\tA = A - reg0_3;\n\tsetResultFlags(A);\n}\n\n:SUI imm8 is op0_8=0xd6; imm8 {\n\tsetSubtractFlags(A,imm8);\n\tA = A - imm8;\n\tsetResultFlags(A);\n}\n\n:SUB (HL) is op0_8=0x96 & HL {\n\tval:1 = *:1 HL;\n\tsetSubtractFlags(A,val);\n\tA = A - val;\n\tsetResultFlags(A);\n}\n\n:SBB reg0_3 is op6_2=0x2 & bits3_3=0x3 & reg0_3 {\n\tsetSubtractCarryFlags(A,reg0_3);\n\tA = A - reg0_3 - CY_flag;\n\tsetResultFlags(A);\n}\n\n:SBI imm8 is op0_8=0xde; imm8 {\n\tsetSubtractCarryFlags(A,imm8);\n\tA = A - imm8 - CY_flag;\n\tsetResultFlags(A);\n}\n\n:SBB (HL) is op0_8=0x9e & HL {\n\tval:1 = *:1 HL;\n\tsetSubtractCarryFlags(A,val);\n\tA = A - val - CY_flag;\n\tsetResultFlags(A);\n}\n\n:ANA reg0_3 is op6_2=0x2 & bits3_3=0x4 & reg0_3 {\n\tAC_flag = 1;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A & reg0_3;\n\tsetResultFlags(A);\n}\n\n:ANI imm8 is op0_8=0xe6; imm8 {\n\tAC_flag = 1;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A & imm8;\n\tsetResultFlags(A);\n}\n\n:ANA (HL) is op0_8=0xa6 & HL {\n\tAC_flag = 1;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A & *:1 HL;\n\tsetResultFlags(A);\n}\n\n:ORA reg0_3 is op6_2=0x2 & bits3_3=0x6 & reg0_3 {\n\tAC_flag = 0;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A | reg0_3;\n\tsetResultFlags(A);\n}\n\n:ORI imm8 is op0_8=0xf6; imm8 {\n\tAC_flag = 0;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A | imm8;\n\tsetResultFlags(A);\n}\n\n:ORA (HL) is op0_8=0xb6 & HL {\n\tAC_flag = 0;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A | *:1 HL;\n\tsetResultFlags(A);\n}\n\n:XRA reg0_3 is op6_2=0x2 & bits3_3=0x5 & reg0_3 {\n\tAC_flag = 0;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A ^ reg0_3;\n\tsetResultFlags(A);\n}\n\n:XRA (HL) is op0_8=0xae & HL {\n\tAC_flag = 0;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A ^ *:1 HL;\n\tsetResultFlags(A);\n}\n\n:XRI imm8 is op0_8=0xee; imm8 {\n\tAC_flag = 0;\n\tCY_flag = 0;\n\tP_flag = 0;\n\tA = A ^ imm8;\n\tsetResultFlags(A);\n}\n\n:CMP reg0_3 is op6_2=0x2 & bits3_3=0x7 & reg0_3 {\n\tsetSubtractFlags(A,reg0_3);\n\tcmp:1 = A - reg0_3;\n\tsetResultFlags(cmp);\n}\n\n:CPI imm8 is op0_8=0xfe; imm8 {\n\tsetSubtractFlags(A,imm8);\n\tcmp:1 = A - imm8;\n\tsetResultFlags(cmp);\n}\n\n:CMP (HL) is op0_8=0xbe & HL {\n\tval:1 = *:1 HL;\n\tsetSubtractFlags(A,val);\n\tcmp:1 = A - val;\n\tsetResultFlags(cmp);\n}\n\n:INR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 {\n\tP_flag = (reg3_3 == 0x7f);\n\treg3_3 = reg3_3 + 1;\n\tsetResultFlags(reg3_3);\n}\n\n:INR (HL) is op0_8=0x34 & HL {\n\tval:1 = *:1 HL;\n\tP_flag = (val == 0x7f);\n\tval = val + 1;\n\t*:1 HL = val;\n\tsetResultFlags(val);\n}\n\n:DCR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x5 {\n\tP_flag = (reg3_3 == 0x80);\n\treg3_3 = reg3_3 - 1;\n\tsetResultFlags(reg3_3);\n}\n\n:DCR (HL) is op0_8=0x35 & HL {\n\tval:1 = *:1 HL;\n\tP_flag = (val == 0x80);\n\tval = val - 1;\n\t*:1 HL = val;\n\tsetResultFlags(val);\n}\n\n:DAA is op0_8=0x27 {\n\tA = BCDadjust(A);\n\tsetResultFlags(A);\n\tP_flag = hasEvenParity(A);\n}\n\n:CMA is op0_8=0x2f {\n\tA = ~A;\t\n}\n\n:CMC is op0_8=0x3f {\n\tCY_flag = !CY_flag;\n}\n\n:STC is op0_8=0x37 {\n\tCY_flag = 1;\n\tAC_flag = 0;\n}\n\n:NOP is op0_8=0x0 {\n}\n\n:HALT is op0_8=0x76 {\n\tgoto inst_start;\n}\n\n:DI is op0_8=0xf3 {\n#\tIFF1 = 0;\n#\tIFF2 = 0;\n\tdisableMaskableInterrupts();\n}\n\n:EI is op0_8=0xfb {\n#\tIFF1 = 1;\n#\tIFF2 = 1;\n\tenableMaskableInterrupts();\n}\n\n:RIM is op0_8=0x20 {\n\tA = readInterruptMask();\n}\n\n:SIM is op0_8=0x30 {\n\tsetInterruptMask(A);\n}\n\n:DAD HL,sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x9 & HL {\n\tsetAddFlags(HL,sRegPair4_2);\n\tHL = HL + sRegPair4_2;\n}\n\n:INX sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x3 {\n\tsRegPair4_2 = sRegPair4_2 + 1;\n}\n\n:DCX sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0xb {\n\tsRegPair4_2 = sRegPair4_2 - 1;\n}\n\n:RLC is op0_8=0x07 {\n\tCY_flag = (A >> 7);\n\tA = (A << 1) | CY_flag;\n\tAC_flag = 0;\n}\n\n:RAL is op0_8=0x17 {\n\tnextC:1 = (A >> 7);\n\tA = (A << 1) | CY_flag;\n\tCY_flag = nextC;\n\tAC_flag = 0;\n}\n\n:RRC is op0_8=0x0f {\n\tCY_flag = (A & 1);\n\tA = (A >> 1) | (CY_flag << 7);\n\tAC_flag = 0;\n}\n\n:RAR is op0_8=0x1f {\n\tnextC:1 = (A & 1);\n\tA = (A >> 1) | (CY_flag << 7);\n\tCY_flag = nextC;\n\tAC_flag = 0;\n}\n\n:JMP Addr16 is op0_8=0xc3; Addr16 {\n\tgoto Addr16;\t\n}\n\n:J^cc Addr16 is op6_2=0x3 & cc & bits0_3=0x2; Addr16 {\n\tif (cc) goto Addr16;\n}\n\n:PCHL is op0_8=0xe9 {\n\tgoto [HL];\n}\n\n:CALL Addr16 is op0_8=0xcd; Addr16 {\n\ttmp:2 = inst_next;\n\tpush16(tmp);\n\tcall Addr16;\n}\n\n:C^cc Addr16 is op6_2=0x3 & cc & bits0_3=0x4; Addr16 {\n\tif (!cc) goto inst_next;\n\ttmp:2 = inst_next;\n\tpush16(tmp);\n\tcall Addr16;\n}\n\n:RET is op0_8=0xc9 {\n\ttmp:2 = 0;\n\tpop16(tmp);\n\treturn [tmp];\n}\n\n:R^cc is op6_2=0x3 & cc & bits0_3=0x0 {\n\tif (!cc) goto inst_next;\n\ttmp:2 = 0;\n\tpop16(tmp);\n\treturn [tmp];\n}\t\n\n:RST RstAddr is op6_2=0x3 & RstAddr & bits0_3=0x7 {\n\ttmp:2 = inst_next;\n\tpush16(tmp);\n\tcall RstAddr;\n}\n\n:IN IOAddr8 is op0_8=0xdb; IOAddr8 {\n\tA = IOAddr8;\n}\n\n:OUT IOAddr8 is op0_8=0xd3; IOAddr8 {\n\tIOAddr8 = A;\n}\n\n" }, { "path": "pypcode/processors/AARCH64/data/aarch64-pltThunks.xml", "content": "\n \n \n \n \t...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 8\n \t0x11 ......10 01...... 0xf9 # ldr x17, [x16, PLTGOT + n * 8]\n \t0x10 ......10 00...... 0x91 # add x16, x16, :lo12:PLTGOT + n * 8\n \t0x20 0x02 0x1f 0xd6 # br x17\n \n \n \n \n \t...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 4\n \t0x11 ......10 01...... 0xb9 # ldr x17, [x16, PLTGOT + n * 4]\n \t0x10 ......10 00...... 0x11 # add x16, x16, :lo12:PLTGOT + n * 4\n \t0x20 0x02 0x1f 0xd6 # br x17\n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64.dwarf", "content": "\n\t\n\t\t \n\t\t\n\t\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64.ldefs", "content": "\n\n \n Generic ARM64 v8.5-A LE instructions, LE data, missing some 8.5 vector\n \n \n \n \n \n \n \n \n \n \n Generic ARM64 v8.5-A LE instructions, BE data, missing some 8.5 vector\n \n \n \n \n \n \n \n \n \n Generic ARM64 v8.5-A LE instructions, LE data, ilp32\n \n \n \n \n \n \n \n \n \n Generic ARM64 v8.5-A LE instructions, BE data, ilp32\n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n\n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64.slaspec", "content": "\n@define DATA_ENDIAN \"little\"\n\n@include \"AARCH64instructions.sinc\"\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64BE.slaspec", "content": "\n@define DATA_ENDIAN \"big\"\n\n@include \"AARCH64instructions.sinc\"\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_AMXext.sinc", "content": "#\n# Apple AARCH64 extended matrix instructions\n# Contents based on evolving information published on Web\n#\n#\n\ndefine pcodeop __amx_ldx;\ndefine pcodeop __amx_ldy;\ndefine pcodeop __amx_stx;\ndefine pcodeop __amx_sty;\ndefine pcodeop __amx_ldz;\ndefine pcodeop __amx_stz;\ndefine pcodeop __amx_ldzi;\ndefine pcodeop __amx_stzi;\ndefine pcodeop __amx_extrx;\ndefine pcodeop __amx_extry;\ndefine pcodeop __amx_fma64;\ndefine pcodeop __amx_fms64;\ndefine pcodeop __amx_fma32;\ndefine pcodeop __amx_fms32;\ndefine pcodeop __amx_mac16;\ndefine pcodeop __amx_fma16;\ndefine pcodeop __amx_fms16;\ndefine pcodeop __amx_enable;\ndefine pcodeop __amx_disable;\ndefine pcodeop __amx_vecint;\ndefine pcodeop __amx_vecfp;\ndefine pcodeop __amx_matint;\ndefine pcodeop __amx_matfp;\ndefine pcodeop __amx_genlut;\n\n\nwith : ImmS_ImmR_TestSet=1 {\n\nAMXAddr: is Rd_GPR64 {\n addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;\n export addr;\n}\n\nAMXRegOff: is Rd_GPR64 {\n registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;\n export registerOff;\n}\n\nAMXSize: is Rd_GPR64 {\n local size = ((Rd_GPR64 >> 62) & 1);\n size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;\n export size;\n}\n\n:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_ldx(Rd_GPR64);\n}\n\n:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_ldy(Rd_GPR64);\n}\n\n:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_stx(Rd_GPR64);\n}\n\n:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_sty(Rd_GPR64);\n}\n\n:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_ldz(Rd_GPR64);\n}\n\n:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_stz(Rd_GPR64);\n}\n\n:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_ldzi(Rd_GPR64);\n}\n\n:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64\n{\n __amx_stzi(Rd_GPR64);\n}\n\n:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64\n{\n __amx_extrx(Rd_GPR64);\n}\n\n:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64\n{\n __amx_extry(Rd_GPR64);\n}\n\n:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64\n{\n __amx_fma64(Rd_GPR64);\n}\n\n:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64\n{\n __amx_fms64(Rd_GPR64);\n}\n\n:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64\n{\n __amx_fma32(Rd_GPR64);\n}\n\n:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64\n{\n __amx_fms32(Rd_GPR64);\n}\n\n:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64\n{\n __amx_mac16(Rd_GPR64);\n}\n\n:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64\n{\n __amx_fma16(Rd_GPR64);\n}\n\n:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64\n{\n __amx_fms16(Rd_GPR64);\n}\n\n:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1\n{\n __amx_disable();\n}\n\n:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0\n{\n __amx_enable();\n}\n\n:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64\n{\n __amx_vecint(Rd_GPR64);\n}\n\n:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64\n{\n __amx_vecfp(Rd_GPR64);\n}\n\n:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64\n{\n __amx_matint(Rd_GPR64);\n}\n\n:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64\n{\n __amx_matfp(Rd_GPR64);\n}\n\n:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64\n{\n __amx_genlut(Rd_GPR64);\n}\n\n}" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec", "content": "\n@define DATA_ENDIAN \"little\"\n\n@include \"AARCH64instructions.sinc\"\n@include \"AARCH64_AMXext.sinc\"\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_apple.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc", "content": "autda__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, Rn_GPR64xsp); }\nautda__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDA(Rd_GPR64, Rn_GPR64xsp); }\nautda__PACpart: \"hide\" is ShowPAC=0 { }\n\nautdza__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, xzr); }\nautdza__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDA(Rd_GPR64, xzr); }\nautdza__PACpart: \"hide\" is ShowPAC=0 { }\n\nautdb__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, Rn_GPR64xsp); }\nautdb__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDB(Rd_GPR64, Rn_GPR64xsp); }\nautdb__PACpart: \"hide\" is ShowPAC=0 { }\n\nautdzb__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, xzr); }\nautdzb__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDB(Rd_GPR64, xzr); }\nautdzb__PACpart: \"hide\" is ShowPAC=0 { }\n\nautia__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, Rn_GPR64xsp); }\nautia__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIA(Rd_GPR64, Rn_GPR64xsp); }\nautia__PACpart: \"hide\" is ShowPAC=0 { }\n\nautiza__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, xzr); }\nautiza__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIA(Rd_GPR64, xzr); }\nautiza__PACpart: \"hide\" is ShowPAC=0 { }\n\nautia1716__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIA(x17, x16); }\nautia1716__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x17, x16); }\nautia1716__PACpart: \"hide\" is ShowPAC=0 { }\n\nautiasp__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, sp); }\nautiasp__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }\nautiasp__PACpart: \"hide\" is ShowPAC=0 { }\n\nautiaz__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, xzr); }\nautiaz__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, xzr); }\nautiaz__PACpart: \"hide\" is ShowPAC=0 { }\n\nautib__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, Rn_GPR64xsp); }\nautib__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIB(Rd_GPR64, Rn_GPR64xsp); }\nautib__PACpart: \"hide\" is ShowPAC=0 { }\n\nautizb__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, xzr); }\nautizb__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIB(Rd_GPR64, xzr); }\nautizb__PACpart: \"hide\" is ShowPAC=0 { }\n\nautib1716__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIB(x17, x16); }\nautib1716__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x17, x16); }\nautib1716__PACpart: \"hide\" is ShowPAC=0 { }\n\nautibsp__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, sp); }\nautibsp__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }\nautibsp__PACpart: \"hide\" is ShowPAC=0 { }\n\nautibz__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, xzr); }\nautibz__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, xzr); }\nautibz__PACpart: \"hide\" is ShowPAC=0 { }\n\nb_blinkop__raaz___PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }\nb_blinkop__raaz___PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }\nb_blinkop__raaz___PACpart: \"hide\" is ShowPAC=0 { }\n\nb_blinkop__raa___PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }\nb_blinkop__raa___PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }\nb_blinkop__raa___PACpart: \"hide\" is ShowPAC=0 { }\n\nb_blinkop__rabz___PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }\nb_blinkop__rabz___PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }\nb_blinkop__rabz___PACpart: \"hide\" is ShowPAC=0 { }\n\nb_blinkop__rab___PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }\nb_blinkop__rab___PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }\nb_blinkop__rab___PACpart: \"hide\" is ShowPAC=0 { }\n\neretaa__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { AuthIA(pc, sp); }\neretaa__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIA(pc, sp); }\neretaa__PACpart: \"hide\" is ShowPAC=0 { }\n\neretab__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { AuthIB(pc, sp); }\neretab__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIB(pc, sp); }\neretab__PACpart: \"hide\" is ShowPAC=0 { }\n\nldraa__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }\nldraa__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }\nldraa__PACpart: \"hide\" is ShowPAC=0 { }\n\nldrab__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }\nldrab__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }\nldrab__PACpart: \"hide\" is ShowPAC=0 { }\n\npacda__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacda(Rd_GPR64, Rn_GPR64xsp); }\npacda__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacda(Rd_GPR64, Rn_GPR64xsp); }\npacda__PACpart: \"hide\" is ShowPAC=0 { }\n\npacdza__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdza(Rd_GPR64); }\npacdza__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdza(Rd_GPR64); }\npacdza__PACpart: \"hide\" is ShowPAC=0 { }\n\npacdb__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacdb(Rd_GPR64, Rn_GPR64xsp); }\npacdb__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacdb(Rd_GPR64, Rn_GPR64xsp); }\npacdb__PACpart: \"hide\" is ShowPAC=0 { }\n\npacdzb__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdzb(Rd_GPR64); }\npacdzb__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdzb(Rd_GPR64); }\npacdzb__PACpart: \"hide\" is ShowPAC=0 { }\n\npacia__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacia(Rd_GPR64, Rn_GPR64xsp); }\npacia__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacia(Rd_GPR64, Rn_GPR64xsp); }\npacia__PACpart: \"hide\" is ShowPAC=0 { }\n\npaciza__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = paciza(Rd_GPR64); }\npaciza__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { paciza(Rd_GPR64); }\npaciza__PACpart: \"hide\" is ShowPAC=0 { }\n\npacia1716__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x17 = pacia(x17, x16); }\npacia1716__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { pacia(x17, x16); }\npacia1716__PACpart: \"hide\" is ShowPAC=0 { }\n\npaciasp__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = pacia(x30, sp); }\npaciasp__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { pacia(x30, sp); }\npaciasp__PACpart: \"hide\" is ShowPAC=0 { }\n\npaciaz__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = paciza(x30); }\npaciaz__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { paciza(x30); }\npaciaz__PACpart: \"hide\" is ShowPAC=0 { }\n\npacib__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacib(Rd_GPR64, Rn_GPR64xsp); }\npacib__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacib(Rd_GPR64, Rn_GPR64xsp); }\npacib__PACpart: \"hide\" is ShowPAC=0 { }\n\npacizb__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacizb(Rd_GPR64); }\npacizb__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacizb(Rd_GPR64); }\npacizb__PACpart: \"hide\" is ShowPAC=0 { }\n\npacib1716__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x17 = pacib(x17, x16); }\npacib1716__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { pacib(x17, x16); }\npacib1716__PACpart: \"hide\" is ShowPAC=0 { }\n\npacibsp__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = pacib(x30, sp); }\npacibsp__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { pacib(x30, sp); }\npacibsp__PACpart: \"hide\" is ShowPAC=0 { }\n\npacibz__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = pacizb(x30); }\npacibz__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { pacizb(x30); }\npacibz__PACpart: \"hide\" is ShowPAC=0 { }\n\nretaa__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { AuthIA(x30, sp); }\nretaa__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }\nretaa__PACpart: \"hide\" is ShowPAC=0 { }\n\nretab__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { AuthIB(x30, sp); }\nretab__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }\nretab__PACpart: \"hide\" is ShowPAC=0 { }\n\nxpacd__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 1:1); }\nxpacd__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 1:1); }\nxpacd__PACpart: \"hide\" is ShowPAC=0 { }\n\nxpaci__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 0:1); }\nxpaci__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 0:1); }\nxpaci__PACpart: \"hide\" is ShowPAC=0 { }\n\nxpaclri__PACpart: \"show_and_clobber\" is ShowPAC=1 & PAC_clobber=1 { x30 = xpac(x30, 0:1); }\nxpaclri__PACpart: \"show_noclobber\" is ShowPAC=1 & PAC_clobber=0 { xpac(x30, 0:1); }\nxpaclri__PACpart: \"hide\" is ShowPAC=0 { }\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_golang.cspec", "content": "\n\n\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\n\t\n\n\t\n\t\t\n\t\n \n\t\n\t\n\n \n \n \n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t \n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n \n\t\t\t\t\t\n\t\t\t\t\n\t\t \n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t \n\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t \n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t \n\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n \n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n \n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\t\n\t\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\t\n\t\t\n\n\t" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_golang.register.info", "content": "\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_ilp32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_swift.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64_win.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\n\t\t \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64base.sinc", "content": "# C6.2.1 ADC page C6-1144 line 67905 MATCH x1a000000/mask=x7fe0fc00\n# C6.2.2 ADCS page C6-1146 line 67991 MATCH x3a000000/mask=x7fe0fc00\n# CONSTRUCT x1a000000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1a000000/mask=xdfe0fc00 --status pass --comment \"flags\"\n\n:adc^SBIT_CZNO Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_30=0 & S & SBIT_CZNO & b_2428=0x1a & b_2123=0 & Rm_GPR32 & b_1015=0 & Rd_GPR32 & Rd_GPR64 & Rn_GPR32\n{\n\tadd_with_carry_flags(Rn_GPR32, Rm_GPR32);\n\ttmp:4 = Rm_GPR32 + Rn_GPR32 + zext(CY);\n\tRd_GPR64 = zext(tmp);\n\tresultflags(tmp);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.1 ADC page C6-1144 line 67905 MATCH x1a000000/mask=x7fe0fc00\n# C6.2.2 ADCS page C6-1146 line 67991 MATCH x3a000000/mask=x7fe0fc00\n# CONSTRUCT x9a000000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9a000000/mask=xdfe0fc00 --status pass --comment \"flags\"\n\n:adc^SBIT_CZNO Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_30=0 & S & SBIT_CZNO & b_2428=0x1a & b_2123=0 & Rm_GPR64 & b_1015=0 & Rd_GPR64 & Rn_GPR64\n{\n\tadd_with_carry_flags(Rn_GPR64, Rm_GPR64);\n\tRd_GPR64 = Rn_GPR64 + Rm_GPR64 + zext(CY);\n\tresultflags(Rd_GPR64);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.3 ADD (extended register) page C6-1148 line 68081 MATCH x0b200000/mask=x7fe00000\n# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000\n# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f\n# CONSTRUCT x0b200000/mask=xdfe00000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x0b200000/mask=xdfe00000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, ExtendRegShift32\nis sf=0 & op=0 & S & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_2:4 = ExtendRegShift32;\n\taddflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64xsp = zext(tmp_1);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.3 ADD (extended register) page C6-1148 line 68081 MATCH x0b200000/mask=x7fe00000\n# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000\n# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f\n# CONSTRUCT x8b200000/mask=xdfe00000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x8b200000/mask=xdfe00000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ExtendRegShift64\nis sf=1 & op=0 & S & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp_2:8 = ExtendRegShift64;\n\taddflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64xsp = tmp_1;\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00\n# CONSTRUCT x11000000/mask=xdf000000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x11000000/mask=xdf000000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR32xsp, Rn_GPR32xsp, ImmShift32\nis sf=0 & b_30=0 & S & SBIT_CZNO & b_2428=0x011 & ImmShift32 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp\n{\n\taddflags(Rn_GPR32xsp, ImmShift32);\n\ttmp:4 = Rn_GPR32xsp + ImmShift32;\n\tresultflags(tmp);\n\tbuild SBIT_CZNO;\n\tRd_GPR64xsp = zext(tmp);\n}\n\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00\n# CONSTRUCT x91000000/mask=xdf000000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x91000000/mask=xdf000000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ImmShift64\nis sf=1 & b_30=0 & S & SBIT_CZNO & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\taddflags(Rn_GPR64xsp, ImmShift64);\n\tRd_GPR64xsp = Rn_GPR64xsp + ImmShift64;\n\tresultflags(Rd_GPR64xsp);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00\n# CONSTRUCT x11000000/mask=xdfc00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x11000000/mask=xdfc00000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl0\nis sf=0 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_posimm_lsl0 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_posimm_lsl0;\n\taddflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64xsp = zext(tmp_1);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# CONSTRUCT x11400000/mask=xdfc00000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x11400000/mask=xdfc00000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl12\nis sf=0 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_posimm_lsl12 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_posimm_lsl12;\n\taddflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64xsp = zext(tmp_1);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00\n# CONSTRUCT x91000000/mask=xdfc00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x91000000/mask=xdfc00000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl0\nis sf=1 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_posimm_lsl0 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_posimm_lsl0;\n\taddflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64xsp = tmp_1;\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# CONSTRUCT x91400000/mask=xdfc00000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x91400000/mask=xdfc00000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl12\nis sf=1 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_posimm_lsl12 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_posimm_lsl12;\n\taddflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64xsp = tmp_1;\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.5 ADD (shifted register) page C6-1153 line 68340 MATCH x0b000000/mask=x7f200000\n# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000\n# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f\n# CONSTRUCT x0b000000/mask=xdf208000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x0b000000/mask=xdf208000 --status pass --comment \"flags\"\n# if shift == '11' then ReservedValue();\n\n:add^SBIT_CZNO Rd_GPR32, Rn_GPR32, RegShift32\nis sf=0 & op=0 & S & SBIT_CZNO & b_2428=0xb & b_2121=0 & b_15=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32;\n\taddflags(Rn_GPR32, tmp_2);\n\ttmp_1:4 = Rn_GPR32 + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.5 ADD (shifted register) page C6-1153 line 68340 MATCH x0b000000/mask=x7f200000\n# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000\n# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f\n# CONSTRUCT x8b000000/mask=xdf200000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x8b000000/mask=xdf200000 --status pass --comment \"flags\"\n\n:add^SBIT_CZNO Rd_GPR64, Rn_GPR64, RegShift64\nis sf=1 & op=0 & S & SBIT_CZNO & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64;\n\taddflags(Rn_GPR64, tmp_2);\n\ttmp_1:8 = Rn_GPR64 + tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.10 ADR page C6-1163 line 68896 MATCH x10000000/mask=x9f000000\n# CONSTRUCT x10000000/mask=x9f000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x10000000/mask=x9f000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:adr Rd_GPR64, AdrReloff\nis b_31=0 & AdrReloff & b_2428=0x10 & Rd_GPR64\n{\n\tRd_GPR64 = &AdrReloff;\n}\n\n# C6.2.11 ADRP page C6-1164 line 68943 MATCH x90000000/mask=x9f000000\n# CONSTRUCT x90000000/mask=x9f000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x90000000/mask=x9f000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:adrp Rd_GPR64, AdrReloff\nis b_31=1 & AdrReloff & b_2428=0x10 & Rd_GPR64\n{\n\tRd_GPR64 = &AdrReloff;\n}\n\n# C6.2.12 AND (immediate) page C6-1165 line 68992 MATCH x12000000/mask=x7f800000\n# CONSTRUCT x12000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x12000000/mask=xff800000 --status pass\n\n:and Rd_GPR32wsp, Rn_GPR32, DecodeWMask32\nis sf=0 & opc=0 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_1:4 = Rn_GPR32 & DecodeWMask32;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.12 AND (immediate) page C6-1165 line 68992 MATCH x12000000/mask=x7f800000\n# CONSTRUCT x92000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x92000000/mask=xff800000 --status pass\n\n:and Rd_GPR64xsp, Rn_GPR64, DecodeWMask64\nis sf=1 & opc=0 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp\n{\n\ttmp_1:8 = Rn_GPR64 & DecodeWMask64;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.13 AND (shifted register) page C6-1167 line 69083 MATCH x0a000000/mask=x7f200000\n# CONSTRUCT x0a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x0a000000/mask=xff200000 --status pass\n\n:and Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=0 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32Log;\n\ttmp_1:4 = Rn_GPR32 & tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.13 AND (shifted register) page C6-1167 line 69083 MATCH x0a000000/mask=x7f200000\n# CONSTRUCT x8a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x8a000000/mask=xff200000 --status pass\n\n:and Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=0 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64Log;\n\ttmp_1:8 = Rn_GPR64 & tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000\n# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f\n# CONSTRUCT x72000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x72000000/mask=xff800000 --status pass --comment \"flags\"\n\n:ands Rd_GPR32, Rn_GPR32, DecodeWMask32\nis sf=0 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_1:4 = Rn_GPR32 & DecodeWMask32;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000\n# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f\n# CONSTRUCT xf2000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf2000000/mask=xff800000 --status pass --comment \"flags\"\n\n:ands Rd_GPR64, Rn_GPR64, DecodeWMask64\nis sf=1 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_1:8 = Rn_GPR64 & DecodeWMask64;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectLflags();\n}\n\n# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000\n# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f\n# CONSTRUCT x6a000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x6a000000/mask=xff200000 --status pass --comment \"flags\"\n\n:ands Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=3 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32Log;\n\ttmp_1:4 = Rn_GPR32 & tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000\n# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f\n# CONSTRUCT xea000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xea000000/mask=xff200000 --status pass --comment \"flags\"\n\n:ands Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=3 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64Log;\n\ttmp_1:8 = Rn_GPR64 & tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectLflags();\n}\n\n# C6.2.16 ASR (register) page C6-1173 line 69404 MATCH x1ac02800/mask=x7fe0fc00\n# C6.2.18 ASRV page C6-1177 line 69588 MATCH x1ac02800/mask=x7fe0fc00\n# CONSTRUCT x1ac02800/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac02800/mask=xffe0fc00 --status pass\n\n:asr Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0xa & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Rm_GPR32 & 0x1f;\n\ttmp_1:4 = Rn_GPR32 s>> tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.16 ASR (register) page C6-1173 line 69404 MATCH x1ac02800/mask=x7fe0fc00\n# C6.2.18 ASRV page C6-1177 line 69588 MATCH x1ac02800/mask=x7fe0fc00\n# CONSTRUCT x9ac02800/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ac02800/mask=xffe0fc00 --status pass\n\n:asr Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0xa & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = Rm_GPR64 & 0x3f;\n\ttmp_1:8 = Rn_GPR64 s>> tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x13007c00/mask=xffe0fc02 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x13007c00/mask=xffe0fc02 --status pass\n# Alias for sbfm when imms == '011111'\n# imms is MAX_INT5, so it will never be less than immr. Note that immr is limited to [0,31]\n# Ha! Two explicit cases passes -l\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:asr Rd_GPR32, Rn_GPR32, ImmRConst32\nis ImmS=0x1f & ImmS_LT_ImmR=0 & (ImmS_EQ_ImmR=0 | ImmS_EQ_ImmR=1) & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = ImmRConst32;\n\ttmp_1:4 = Rn_GPR32 s>> tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x9340fc00/mask=xffc0fc02 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x9340fc00/mask=xffc0fc02 --status pass\n# Alias for sbfm when imms == '111111'\n# imms is MAX_INT6, so it will never be less than immr (6-bit field)\n# Ha! Two explicit cases passes -l\n\n:asr Rd_GPR64, Rn_GPR64, ImmRConst64\nis ImmS=0x3f & ImmS_LT_ImmR=0 & (ImmS_EQ_ImmR=0 | ImmS_EQ_ImmR=1) & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = ImmRConst64;\n\ttmp_1:8 = Rn_GPR64 s>> tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd5087800/mask=xffffffe0 --status noqemu\n\n:at \"S1E1R\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64\n{ par_el1 = AT_S1E1R(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c7800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50c7800/mask=xffffffe0 --status noqemu\n\n:at \"S1E2R\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64\n{ par_el1 = AT_S1E2R(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e7800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50e7800/mask=xffffffe0 --status noqemu\n\n:at \"S1E3R\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64\n{ par_el1 = AT_S1E3R(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd5087820/mask=xffffffe0 --status noqemu\n\n:at \"S1E1W\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64\n{ par_el1 = AT_S1E1W(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c7820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50c7820/mask=xffffffe0 --status noqemu\n\n:at \"S1E2W\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64\n{ par_el1 = AT_S1E2W(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e7820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50e7820/mask=xffffffe0 --status noqemu\n\n:at \"S1E3W\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64\n{ par_el1 = AT_S1E3W(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087840/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd5087840/mask=xffffffe0 --status noqemu\n\n:at \"S1E0R\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b010 & Rt_GPR64\n{ par_el1 = AT_S1E0R(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087860/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd5087860/mask=xffffffe0 --status noqemu\n\n:at \"S1E0W\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b011 & Rt_GPR64\n{ par_el1 = AT_S1E0W(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c7880/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50c7880/mask=xffffffe0 --status noqemu\n\n:at \"S12E1R\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b100 & Rt_GPR64\n{ par_el1 = AT_S12E1R(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c78a0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50c78a0/mask=xffffffe0 --status noqemu\n\n:at \"S12E1W\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b101 & Rt_GPR64\n{ par_el1 = AT_S12E1W(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c78c0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50c78c0/mask=xffffffe0 --status noqemu\n\n:at \"S12E0R\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b110 & Rt_GPR64\n{ par_el1 = AT_S12E0R(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c78e0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd50c78e0/mask=xffffffe0 --status noqemu\n\n:at \"S12E0W\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b111 & Rt_GPR64\n{ par_el1 = AT_S12E0W(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087900/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd5087900/mask=xffffffe0 --status noqemu\n\n:at \"S1E1RP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1001 & b_0507=0b000 & Rt_GPR64\n{ par_el1 = AT_S1E1RP(Rt_GPR64); }\n\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087920/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xd5087920/mask=xffffffe0 --status noqemu\n\n:at \"S1E1WP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1001 & b_0507=0b001 & Rt_GPR64\n{ par_el1 = AT_S1E1WP(Rt_GPR64); }\n\n# C6.2.20 AUTDA, AUTDZA page C6-1181 line 69758 MATCH xdac11800/mask=xffffdc00\n# CONSTRUCT xdac11800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac11800/mask=xfffffc00 --status noqemu\n\n:autda Rd_GPR64, Rn_GPR64xsp\nis autda__PACpart & b_1431=0b110110101100000100 & b_1012=0b110 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild autda__PACpart;\n}\n\n# C6.2.20 AUTDA, AUTDZA page C6-1181 line 69758 MATCH xdac11800/mask=xffffdc00\n# CONSTRUCT xdac13be0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac13be0/mask=xffffffe0 --status noqemu\n\n:autdza Rd_GPR64\nis autdza__PACpart & b_1431=0b110110101100000100 & b_1012=0b110 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild autdza__PACpart;\n}\n\n# C6.2.21 AUTDB, AUTDZB page C6-1182 line 69833 MATCH xdac11c00/mask=xffffdc00\n# CONSTRUCT xdac11c00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac11c00/mask=xfffffc00 --status noqemu\n\n:autdb Rd_GPR64, Rn_GPR64xsp\nis autdb__PACpart & b_1431=0b110110101100000100 & b_1012=0b111 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild autdb__PACpart;\n}\n\n# C6.2.21 AUTDB, AUTDZB page C6-1182 line 69833 MATCH xdac11c00/mask=xffffdc00\n# CONSTRUCT xdac13fe0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac13fe0/mask=xffffffe0 --status noqemu\n\n:autdzb Rd_GPR64\nis autdzb__PACpart & b_1431=0b110110101100000100 & b_1012=0b111 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild autdzb__PACpart;\n}\n\n# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xdac11000/mask=xffffdc00\n# CONSTRUCT xdac11000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac11000/mask=xfffffc00 --status noqemu\n\n:autia Rd_GPR64, Rn_GPR64xsp\nis autia__PACpart & b_1431=0b110110101100000100 & b_1012=0b100 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild autia__PACpart;\n}\n\n# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xdac11000/mask=xffffdc00\n# CONSTRUCT xdac133e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac133e0/mask=xffffffe0 --status noqemu\n\n:autiza Rd_GPR64\nis autiza__PACpart & b_1431=0b110110101100000100 & b_1012=0b100 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild autiza__PACpart;\n}\n\n# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503219f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503219f/mask=xffffffff --status nodest\n\n:autia1716\nis autia1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b100 & b_0004=0b11111\n{\n\tbuild autia1716__PACpart;\n}\n\n# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd50323bf/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50323bf/mask=xffffffff --status nodest\n\n:autiasp\nis autiasp__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b101 & b_0004=0b11111\n{\n\tbuild autiasp__PACpart;\n}\n\n# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503239f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503239f/mask=xffffffff --status nodest\n\n:autiaz\nis autiaz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b100 & b_0004=0b11111\n{\n\tbuild autiaz__PACpart;\n}\n\n# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xdac11400/mask=xffffdc00\n# CONSTRUCT xdac11400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac11400/mask=xfffffc00 --status noqemu\n\n:autib Rd_GPR64, Rn_GPR64xsp\nis autib__PACpart & b_1431=0b110110101100000100 & b_1012=0b101 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild autib__PACpart;\n}\n\n# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xdac11400/mask=xffffdc00\n# CONSTRUCT xdac137e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac137e0/mask=xffffffe0 --status noqemu\n\n:autizb Rd_GPR64\nis autizb__PACpart & b_1431=0b110110101100000100 & b_1012=0b101 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild autizb__PACpart;\n}\n\n# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd50321df/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50321df/mask=xffffffff --status nodest\n\n:autib1716\nis autib1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b110 & b_0004=0b11111\n{\n\tbuild autib1716__PACpart;\n}\n\n# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd50323ff/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50323ff/mask=xffffffff --status nodest\n\n:autibsp\nis autibsp__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b111 & b_0004=0b11111\n{\n\tbuild autibsp__PACpart;\n}\n\n# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd50323df/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50323df/mask=xffffffff --status nodest\n\n:autibz\nis autibz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b110 & b_0004=0b11111\n{\n\tbuild autibz__PACpart;\n}\n\n# C6.2.26 B.cond page C6-1191 line 70305 MATCH x54000000/mask=xff000010\n# CONSTRUCT x5400000f/mask=xff00001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x5400000f/mask=xff00001f --status nodest --comment \"noflags qemuerr(illegal addresses cause qemu exit)\"\n\n:b^\".\"^BranchCondOp Addr19\nis b_2531=0x2a & o1=0 & Addr19 & o0=0 & br_cond_op=15 & BranchCondOp\n{\n\tgoto Addr19;\n}\n\n# C6.2.26 B.cond page C6-1191 line 70305 MATCH x54000000/mask=xff000010\n# CONSTRUCT x54000000/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x54000000/mask=xff000010 --status nodest --comment \"flags qemuerr(illegal addresses cause qemu exit)\"\n\n:b^\".\"^BranchCondOp Addr19\nis b_2531=0x2a & o1=0 & Addr19 & o0=0 & br_cond_op & BranchCondOp\n{\n\tif (BranchCondOp) goto Addr19;\n}\n\n# C6.2.25 B page C6-1190 line 70265 MATCH x14000000/mask=xfc000000\n# CONSTRUCT x14000000/mask=xfc000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x14000000/mask=xfc000000 --status nodest --comment \"flags qemuerr(illegal addresses cause qemu exit)\"\n\n:b Addr26\nis b_31=0 & b_2630=0x05 & Addr26\n{\n\tgoto Addr26;\n}\n\n# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010\n# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES\n# b_0031=01010100...................1....\n\n:bc^\".\"^BranchCondOp Addr19\nis b_2531=0x2a & o1=0 & Addr19 & o0=1 & br_cond_op=15 & BranchCondOp\n{\n\tgoto Addr19;\n}\n\n:bc^\".\"^BranchCondOp Addr19\nis b_2531=0x2a & o1=0 & Addr19 & o0=1 & BranchCondOp\n{\n\tif (BranchCondOp) goto Addr19;\n}\n\n\n# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000\n# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0\n# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000\n# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000\n# CONSTRUCT x33000000/mask=xffe08000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x33000000/mask=xffe08000 --status pass\n# if sf == '0' && (N != '0' || immr<5> (b_21) != '0' || imms<5> (b_15) != '0') then ReservedValue();\n\n:bfm Rd_GPR32, Rn_GPR32, ImmR_bitfield32_imm, ImmS_bitfield32_imm\nis sf=0 & opc=1 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmR_bitfield32_imm & ImmS_bitfield32_imm & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32\n{\n\tlocal wmask:4 = DecodeWMask32;\n\tlocal tmask:4 = DecodeTMask32;\n\tlocal dst:4 = Rd_GPR32;\n\tlocal src:4 = Rn_GPR32;\n\tlocal bot:4 = (dst & ~(wmask)) | (((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask);\n\tRd_GPR64 = zext((dst & ~(tmask)) | (bot & tmask));\n}\n\n# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000\n# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0\n# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000\n# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000\n# CONSTRUCT xb3400002/mask=xffc00002 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xb3400002/mask=xffc00002 --status pass\n\n:bfm Rd_GPR64, Rn_GPR64, ImmR_bitfield64_imm, ImmS_bitfield64_imm\nis ImmS_LT_ImmR=1 & sf=1 & opc=1 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmRConst64 & ImmS_bitfield64_imm & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64\n{\n\tlocal wmask:8 = DecodeWMask64;\n\tlocal tmask:8 = DecodeTMask64;\n\tlocal dst:8 = Rd_GPR64;\n\tlocal src:8 = Rn_GPR64;\n\tlocal bot:8 = (dst & ~(wmask)) | (((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask);\n\tRd_GPR64 = (dst & ~(tmask)) | (bot & tmask);\n}\n\n# C6.2.28 BFXIL page C6-567 line 33333 KEEPWITH\n\nBFextractWidth32: \"#\"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:4 imm; }\nBFextractWidth64: \"#\"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:8 imm; }\n\n# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000\n# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0\n# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000\n# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000\n# CONSTRUCT x33000000/mask=xffe08002 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x33000000/mask=xffe08002 --status pass\n\n# Alias for bfm where UInt(imms) >= UInt(immr)\n\n:bfxil Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32\nis ImmS_LT_ImmR=0 & sf=0 & opc=1 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tdst:4 = Rd_GPR32;\n\tsrc:4 = Rn_GPR32;\n\tmask:4 = (0xffffffff >> (32 - BFextractWidth32));\n\ttmp:4 = (src >> ImmRConst32) & mask;\n\tRd_GPR64 = zext((dst & ~(mask)) | tmp);\n}\n\n# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000\n# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0\n# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000\n# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000\n# CONSTRUCT xb3400000/mask=xffc00002 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xb3400000/mask=xffc00002 --status pass\n\n# Alias for bfm where UInt(imms) >= UInt(immr)\n\n:bfxil Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64\nis ImmS_LT_ImmR=0 & sf=1 & opc=1 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & BFextractWidth64 & Rn_GPR64 & Rd_GPR64\n{\n\tdst:8 = Rd_GPR64;\n\tsrc:8 = Rn_GPR64;\n\tmask:8 = (0xffffffffffffffff >> (64 - BFextractWidth64));\n\ttmp:8 = (src >> ImmRConst64) & mask;\n\tRd_GPR64 = ((dst & ~(mask)) | tmp);\n}\n\n# C6.2.32 BIC (shifted register) page C6-1201 line 70793 MATCH x0a200000/mask=x7f200000\n# CONSTRUCT x0a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x0a200000/mask=xff200000 --status pass\n\n:bic Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=0 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_3:4 = RegShift32Log;\n\ttmp_2:4 = tmp_3 ^ -1:4;\n\ttmp_1:4 = Rn_GPR32 & tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.32 BIC (shifted register) page C6-1201 line 70793 MATCH x0a200000/mask=x7f200000\n# CONSTRUCT x8a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x8a200000/mask=xff200000 --status pass\n\n:bic Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=0 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_3:8= RegShift64Log;\n\ttmp_2:8 = tmp_3 ^ -1:8;\n\ttmp_1:8 = Rn_GPR64 & tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.33 BICS (shifted register) page C6-1203 line 70897 MATCH x6a200000/mask=x7f200000\n# CONSTRUCT x6a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x6a200000/mask=xff200000 --status pass --comment \"flags\"\n\n:bics Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=3 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_3:4 = RegShift32Log;\n\ttmp_2:4 = tmp_3 ^ -1:4;\n\ttmp_1:4 = Rn_GPR32 & tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.33 BICS (shifted register) page C6-1203 line 70897 MATCH x6a200000/mask=x7f200000\n# CONSTRUCT xea200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xea200000/mask=xff200000 --status pass --comment \"flags\"\n\n:bics Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=3 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_3:8= RegShift64Log;\n\ttmp_2:8 = tmp_3 ^ -1:8;\n\ttmp_1:8 = Rn_GPR64 & tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectLflags();\n}\n\n# C6.2.34 BL page C6-1205 line 71008 MATCH x94000000/mask=xfc000000\n# CONSTRUCT x94000000/mask=xfc000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x94000000/mask=xfc000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:bl Addr26\nis b_31=1 & b_2630=0x05 & Addr26\n{\n\tx30 = inst_start + 4;\n\tcall Addr26;\n}\n\n# C6.2.35 BLR page C6-1206 line 71050 MATCH xd63f0000/mask=xfffffc1f\n# CONSTRUCT xd63f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd63f0000/mask=xfffffc1f --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:blr Rn_GPR64\nis b_2531=0x6b & b_2324=0 & b_2122=1 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0\n{\n\tpc = Rn_GPR64;\n\tx30 = inst_start + 4;\n\tcall [pc];\n}\n\n# C6.2.33 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-574 line 33668 KEEPWITH\n\n# Z == 0 && M == 0 && Rm = 11111 Key A, zero modifier variant\n\nblinkop: \"l\" is b_2122=0b01 { x30 = inst_start + 4; call [pc]; }\nblinkop: \"\" is b_2122=0b00 { goto[pc]; }\n\n# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800\n# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800\n# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff\n# CONSTRUCT xd61f081f/mask=xff9ffc1f MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd61f081f/mask=xff9ffc1f --status nodest\n\n:b^blinkop^\"raaz\" Rn_GPR64\nis b_blinkop__raaz___PACpart & b_2531=0b1101011 & b_24=0 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=0 & b_0004=0b11111 & Rn_GPR64\n{\n\tbuild b_blinkop__raaz___PACpart;\n\tpc = Rn_GPR64;\n\tbuild blinkop;\n}\n\n# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800\n# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800\n# CONSTRUCT xd71f0800/mask=xff9ffc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd71f0800/mask=xff9ffc00 --status nodest\n# Z == 1 && M == 0 Key A, register modifier variant\n\n:b^blinkop^\"raa\" Rn_GPR64, Rd_GPR64xsp\nis b_blinkop__raa___PACpart & b_2531=0b1101011 & b_24=1 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=0 & Rd_GPR64xsp & Rn_GPR64\n{\n\tbuild b_blinkop__raa___PACpart;\n\tpc = Rn_GPR64;\n\tbuild blinkop;\n}\n\n# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800\n# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800\n# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff\n# CONSTRUCT xd61f0c1f/mask=xff9ffc1f MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd61f0c1f/mask=xff9ffc1f --status nodest\n# Z == 0 && M == 1 && Rm = 11111 Key B, zero modifier variant\n\n:b^blinkop^\"rabz\" Rn_GPR64\nis b_blinkop__rabz___PACpart & b_2531=0b1101011 & b_24=0 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=1 & b_0004=0b11111 & Rn_GPR64\n{\n\tbuild b_blinkop__rabz___PACpart;\n\tpc = Rn_GPR64;\n\tbuild blinkop;\n}\n\n# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800\n# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800\n# CONSTRUCT xd71f0c00/mask=xff9ffc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd71f0c00/mask=xff9ffc00 --status nodest\n# Z == 1 && M == 1 Key B, register modifier variant\n\n:b^blinkop^\"rab\" Rn_GPR64, Rd_GPR64xsp\nis b_blinkop__rab___PACpart & b_2531=0b1101011 & b_24=1 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=1 & Rd_GPR64xsp & Rn_GPR64\n{\n\tbuild b_blinkop__rab___PACpart;\n\tpc = Rn_GPR64;\n\tbuild blinkop;\n}\n\n# C6.2.37 BR page C6-1209 line 71202 MATCH xd61f0000/mask=xfffffc1f\n# CONSTRUCT xd61f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd61f0000/mask=xfffffc1f --status nodest\n\n:br Rn_GPR64\nis b_2531=0x6b & b_2324=0 & b_2122=0 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0\n{\n\tpc = Rn_GPR64;\n\tgoto [pc];\n}\n\n# C6.2.40 BRK page C6-1213 line 71415 MATCH xd4200000/mask=xffe0001f\n# CONSTRUCT xd4200000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4200000/mask=xffe0001f --status nodest\n\n:brk \"#\"^imm16\nis ALL_BTITARGETS & b_2431=0xd4 & b_2123=1 & imm16 & b_0204=0 & b_0001=0\n{\n\ttmp:2 = imm16;\n\tpreferred_exception_return:8 = inst_next;\n\tpc = SoftwareBreakpoint(tmp, preferred_exception_return);\n\tgoto [pc];\n}\n\n# C6.2.37 CASB, CASAB, CASALB, CASLB page C6-580 line 33952 KEEPWITH\n\ncas_var: \"a\" is b_22=1 & b_15=0 { }\ncas_var: \"al\" is b_22=1 & b_15=1 { }\ncas_var: \"\" is b_22=0 & b_15=0 { }\ncas_var: \"l\" is b_22=0 & b_15=1 { }\n\n# C6.2.42 CASB, CASAB, CASALB, CASLB page C6-1216 line 71570 MATCH x08a07c00/mask=xffa07c00\n# CONSTRUCT x08a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08a07c00/mask=xffa07c00 --status nomem\n\n# CAS{,A,AL,L}B size=0b10 (b_3031)\n\n:cas^cas_var^\"b\" aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws\n{\n\tcomparevalue:1 = aa_Ws:1;\n\tnewvalue:1 = aa_Wt:1;\n\tdata:1 = *:1 Rn_GPR64xsp;\n\tif (data != comparevalue) goto ;\n\t*:1 Rn_GPR64xsp = newvalue;\n\n\taa_Ws = zext(data);\n}\n\n# C6.2.43 CASH, CASAH, CASALH, CASLH page C6-1218 line 71692 MATCH x48a07c00/mask=xffa07c00\n# CONSTRUCT x48a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48a07c00/mask=xffa07c00 --status nomem\n\n# CAS{,A,AL,L}H size=0b10 (b_3031)\n\n:cas^cas_var^\"h\" aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws\n{\n\tcomparevalue:2 = aa_Ws:2;\n\tnewvalue:2 = aa_Wt:2;\n\tdata:2 = *:2 Rn_GPR64xsp;\n\tif (data != comparevalue) goto ;\n\t*:2 Rn_GPR64xsp = newvalue;\n\n\taa_Ws = zext(data);\n}\n\n# C6.2.44 CASP, CASPA, CASPAL, CASPL page C6-1220 line 71814 MATCH x08207c00/mask=xbfa07c00\n# CONSTRUCT x08207c00/mask=xffa17c01 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08207c00/mask=xffa17c01 --status nomem\n\n# CASP{,A,AL,L} size=0b00 (b_3031)\n\n:casp^cas_var aa_Ws, aa_Wss, aa_Wt, aa_Wtt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2329=0b0010000 & b_21=1 & b_1014=0b11111 & b_16=0 & b_00=0 & cas_var & aa_Ws & aa_Wss & aa_Wt & aa_Wtt & Rn_GPR64xsp\n{\n@if DATA_ENDIAN == \"big\"\n\tcomparevalue:8 = (zext(aa_Ws) << 32) | zext(aa_Wss);\n\tnewvalue:8 = (zext(aa_Wt) << 32) | zext(aa_Wtt);\n@else\n\tcomparevalue:8 = (zext(aa_Wss) << 32) | zext(aa_Ws);\n\tnewvalue:8 = (zext(aa_Wtt) << 32) | zext(aa_Wt);\n@endif\n\tdata:8 = *:8 Rn_GPR64xsp;\n\tif (data != comparevalue) goto ;\n\t*:8 Rn_GPR64xsp = newvalue;\n\n@if DATA_ENDIAN == \"big\"\n\taa_Ws = data(4);\n\taa_Wss = data:4;\n@else\n\taa_Ws = data:4;\n\taa_Wss = data(4);\n@endif\n}\n\n# C6.2.44 CASP, CASPA, CASPAL, CASPL page C6-1220 line 71814 MATCH x08207c00/mask=xbfa07c00\n# CONSTRUCT x48207c00/mask=xffa17c01 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48207c00/mask=xffa17c01 --status nomem\n\n# CASP{,A,AL,L} size=0b01 (b_3031)\n\n:casp^cas_var aa_Xs, aa_Xss, aa_Xt, aa_Xtt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2329=0b0010000 & b_21=1 & b_1014=0b11111 & b_16=0 & b_00=0 & cas_var & aa_Xs & aa_Xss & aa_Xt & aa_Xtt & Rn_GPR64xsp\n{\n\tlocal tmp_s:8 = aa_Xs;\n\tlocal tmp_ss:8 = aa_Xss;\n\tlocal tmp_t:8 = aa_Xt;\n\tlocal tmp_tt:8 = aa_Xtt;\n\n@if DATA_ENDIAN == \"little\"\n\t# for little endian, swap Xss/Xs and Xtt/Xt\n\ttmp_s = aa_Xss;\n\ttmp_ss = aa_Xs;\n\ttmp_t = aa_Xtt;\n\ttmp_tt = aa_Xt;\n@endif\n\n\tlocal tmp_addr:8 = Rn_GPR64xsp;\n\tlocal tmp_d:8 = *:8 tmp_addr;\n\ttmp_addr = tmp_addr + 8;\n\tlocal tmp_dd:8 = *:8 tmp_addr;\n\n\tif (tmp_d != tmp_s) goto ;\n\tif (tmp_dd != tmp_ss) goto ;\n\n\ttmp_addr = Rn_GPR64xsp;\n\t*:8 tmp_addr = tmp_t;\n\ttmp_addr = tmp_addr + 8;\n\t*:8 tmp_addr = tmp_tt;\n\n\taa_Xs = tmp_d;\n\taa_Xss = tmp_dd;\n}\n\n# C6.2.45 CAS, CASA, CASAL, CASL page C6-1223 line 71996 MATCH x88a07c00/mask=xbfa07c00\n# CONSTRUCT x88a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88a07c00/mask=xffa07c00 --status nomem\n# CAS{,A,AL,L} size=0b10 (b_3031)\n\n:cas^cas_var aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws\n{\n\tcomparevalue:4 = aa_Ws;\n\tnewvalue:4 = aa_Wt;\n\tdata:4 = *:4 Rn_GPR64xsp;\n\tif (data != comparevalue) goto ;\n\t*:4 Rn_GPR64xsp = newvalue;\n\n\taa_Ws = data;\n}\n\n# C6.2.45 CAS, CASA, CASAL, CASL page C6-1223 line 71996 MATCH x88a07c00/mask=xbfa07c00\n# CONSTRUCT xc8a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8a07c00/mask=xffa07c00 --status nomem\n\n# CAS{,A,AL,L} size=0b11 (b_3031)\n\n:cas^cas_var aa_Xs, aa_Xt, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Xt & Rn_GPR64xsp & aa_Xs\n{\n\tcomparevalue:8 = aa_Xs;\n\tnewvalue:8 = aa_Xt;\n\tdata:8 = *:8 Rn_GPR64xsp;\n\tif (data != comparevalue) goto ;\n\t*:8 Rn_GPR64xsp = newvalue;\n\n\taa_Xs = data;\n}\n\n# C6.2.41 CBNZ page C6-589 line 34530 KEEPWITH\n\nZeroOp: \"z\" is cmpr_op=0 { export 1:1; }\nZeroOp: \"nz\" is cmpr_op=1 { export 0:1; }\n\nBitPos: \"#\"^bitpos is sf=1 & b_31 & b_1923 & Rt_GPR64 [ bitpos = b_31 << 5 | b_1923; ]\n{\n\ttmp:1 = ((Rt_GPR64 >> bitpos) & 1) == 0;\n\texport tmp;\n}\n\nBitPos: \"#\"^bitpos is sf=0 & b_31 & b_1923 & Rt_GPR32 [ bitpos = b_31 << 5 | b_1923; ]\n{\n\ttmp:1 = ((Rt_GPR32 >> bitpos) & 1) == 0;\n\texport tmp;\n}\n\n# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000\n# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000\n# CONSTRUCT xb4000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb4000000/mask=xfe000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:cb^ZeroOp Rd_GPR64, Addr19\nis sf=1 & b_2530=0x1a & ZeroOp & Addr19 & Rd_GPR64\n{\n\ttmp:1 = Rd_GPR64 == 0;\n\tif (tmp == ZeroOp) goto Addr19;\n}\n\n# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000\n# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000\n# CONSTRUCT x34000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x34000000/mask=xfe000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:cb^ZeroOp Rd_GPR32, Addr19\nis sf=0 & b_2530=0x1a & ZeroOp & Addr19 & Rd_GPR32\n{\n\ttmp:1 = Rd_GPR32 == 0;\n\tif (tmp == ZeroOp) goto Addr19;\n}\n\n# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000\n# CONSTRUCT x35000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x35000000/mask=xff000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:cbnz Rt_GPR32, Addr19\nis sf=0 & b_2530=0x1a & cmpr_op=1 & Addr19 & Rt_GPR32\n{\n\tif (Rt_GPR32 != 0) goto Addr19;\n}\n\n# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000\n# CONSTRUCT xb5000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb5000000/mask=xff000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:cbnz Rt_GPR64, Addr19\nis sf=1 & b_2530=0x1a & cmpr_op=1 & Addr19 & Rt_GPR64\n{\n\tif (Rt_GPR64 != 0) goto Addr19;\n}\n\n# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000\n# CONSTRUCT x34000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x34000000/mask=xff000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:cbz Rt_GPR32, Addr19\nis sf=0 & b_2530=0x1a & cmpr_op=0 & Addr19 & Rt_GPR32\n{\n\tif (Rt_GPR32 == 0) goto Addr19;\n}\n\n# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000\n# CONSTRUCT xb4000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb4000000/mask=xff000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:cbz Rt_GPR64, Addr19\nis sf=1 & b_2530=0x1a & cmpr_op=0 & Addr19 & Rt_GPR64\n{\n\tif (Rt_GPR64 == 0) goto Addr19;\n}\n\n# C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10\n# CONSTRUCT x3a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x3a400800/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmn Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp\nis sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\ttmp:4 = UImm5;\n\taddflags(Rn_GPR32, tmp);\n\tresult:4 = Rn_GPR32 + tmp;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10\n# CONSTRUCT xba400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xba400800/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmn Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp\nis sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\ttmp:8 = zext(UImm5);\n\taddflags(Rn_GPR64, tmp);\n\tresult:8 = Rn_GPR64 + tmp;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10\n# CONSTRUCT x3a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x3a400000/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmn Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp\nis sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\ttmp:4 = Rm_GPR32;\n\taddflags(Rn_GPR32, tmp);\n\tresult:4 = Rn_GPR32 + tmp;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10\n# CONSTRUCT xba400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xba400000/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmn Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp\nis sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\ttmp:8 = Rm_GPR64;\n\taddflags(Rn_GPR64, tmp);\n\tresult:8 = Rn_GPR64 + tmp;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10\n# CONSTRUCT x7a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x7a400800/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmp Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp\nis sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\tsubflags(Rn_GPR32, UImm5);\n\ttmp:4 = Rn_GPR32 - UImm5;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10\n# CONSTRUCT xfa400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xfa400800/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmp Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp\nis sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\ttmp:8 = zext(UImm5);\n\tsubflags(Rn_GPR64, tmp);\n\ttmp = Rn_GPR64 - tmp;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10\n# CONSTRUCT x7a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x7a400000/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmp Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp\nis sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\tsubflags(Rn_GPR32, Rm_GPR32);\n\ttmp:4 = Rn_GPR32 - Rm_GPR32;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10\n# CONSTRUCT xfa400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xfa400000/mask=xffe00c10 --status pass --comment \"flags\"\n\n:ccmp Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp\nis sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4\n{\n\tcondition:1 = CondOp;\n\tcondMask:1 = NZCVImm_uimm4;\n\tsetCC_NZCV(condMask);\n\tif (!condition) goto inst_next;\n\tsubflags(Rn_GPR64, Rm_GPR64);\n\ttmp:8 = Rn_GPR64 - Rm_GPR64;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.52 CFINV page C6-1236 line 72619 MATCH xd500401f/mask=xfffff0ff\n# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f\n# CONSTRUCT xd500401f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES\n# xd500401f/mask=xfffff0ff NOT MATCHED BY ANY CONSTRUCTOR\n\n:cfinv\nis b_1231=0b11010101000000000100 & b_0811 & b_0007=0b00011111\n{\n\tCY = !CY;\n}\n\n# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00\n# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0\n# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00\n# CONSTRUCT x1a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x1a800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:cinc Rd_GPR32, Rn_GPR32, InvCondOp\nis sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=1 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:4 = Rn_GPR32;\n\tif (!condition) goto ;\n\ttmp = Rn_GPR32 + 1;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00\n# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0\n# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00\n# CONSTRUCT x9a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x9a800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:cinc Rd_GPR64, Rn_GPR64, InvCondOp\nis sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:8 = Rn_GPR64;\n\tif (!condition) goto ;\n\ttmp = Rn_GPR64 + 1;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00\n# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0\n# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00\n# CONSTRUCT x5a800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x5a800000/mask=xffe00c00 --status pass --comment \"flags\"\n\n:cinv Rd_GPR32, Rn_GPR32, InvCondOp\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=0 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:4 = Rn_GPR32;\n\tif (!condition) goto ;\n\ttmp = ~Rn_GPR32;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00\n# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0\n# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00\n# CONSTRUCT xda800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xda800000/mask=xffe00c00 --status pass --comment \"flags\"\n\n:cinv Rd_GPR64, Rn_GPR64, InvCondOp\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=0 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:8 = Rn_GPR64;\n\tif (!condition) goto ;\n\ttmp = ~Rn_GPR64;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.56 CLREX page C6-1242 line 72899 MATCH xd503305f/mask=xfffff0ff\n# CONSTRUCT xd503305f/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd503305f/mask=xfffff0ff --status nodest\n\n:clrex CRm_uimm4_def15\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_uimm4_def15 & Op2=2 & Rt=0x1f\n{\n\tClearExclusiveLocal();\n}\n\n# C6.2.57 CLS page C6-1243 line 72939 MATCH x5ac01400/mask=x7ffffc00\n# CONSTRUCT x5ac01400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x5ac01400/mask=xfffffc00 --status pass\n\n:cls Rd_GPR32, Rn_GPR32\nis sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x5 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp:4 = (Rn_GPR32 ^ (Rn_GPR32<<1))|0x1;\n\t\n\tRd_GPR64 = lzcount(tmp);\n}\n\n# C6.2.57 CLS page C6-1243 line 72939 MATCH x5ac01400/mask=x7ffffc00\n# CONSTRUCT xdac01400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac01400/mask=xfffffc00 --status pass\n\n:cls Rd_GPR64, Rn_GPR64\nis sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x5 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp:8 = (Rn_GPR64 ^ (Rn_GPR64<<1))|0x1;\n\n\tRd_GPR64 = lzcount(tmp);\n}\n\n# C6.2.58 CLZ page C6-1245 line 73022 MATCH x5ac01000/mask=x7ffffc00\n# CONSTRUCT x5ac01000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x5ac01000/mask=xfffffc00 --status pass\n\n:clz Rd_GPR32, Rn_GPR32\nis sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x4 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp:4 = Rn_GPR32;\n\tRd_GPR64 = lzcount(tmp);\n}\n\n# C6.2.58 CLZ page C6-1245 line 73022 MATCH x5ac01000/mask=x7ffffc00\n# CONSTRUCT xdac01000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac01000/mask=xfffffc00 --status pass\n\n:clz Rd_GPR64, Rn_GPR64\nis sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x4 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp:8 = Rn_GPR64;\n\n\tRd_GPR64 = lzcount(tmp);\n}\n\n# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f\n# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000\n# CONSTRUCT x2b20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x2b20001f/mask=xffe0001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR32wsp, ExtendRegShift32\nis sf=0 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd=0x1f\n{\n\ttmp_1:4 = ExtendRegShift32;\n\taddflags(Rn_GPR32wsp, tmp_1);\n\tresult:4 = Rn_GPR32wsp + tmp_1;\n\tresultflags(result);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f\n# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000\n# CONSTRUCT xab20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xab20001f/mask=xffe0001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR64xsp, ExtendRegShift64\nis sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=1 & opt=0 & ExtendRegShift64 & Rn_GPR64xsp & Rd=0x1f\n{\n\ttmp_1:8 = ExtendRegShift64;\n\taddflags(Rn_GPR64xsp, tmp_1);\n\tresult:8 = Rn_GPR64xsp + tmp_1;\n\tresultflags(result);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# CONSTRUCT x3100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x3100001f/mask=xff00001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR32xsp, ImmShift32\nis sf=0 & b_30=0 & b_29=1 & aa_Xd=31 & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp\n{\n\taddflags(Rn_GPR32xsp, ImmShift32);\n\ttmp:4 = Rn_GPR32xsp + ImmShift32;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# CONSTRUCT xb100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb100001f/mask=xff00001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR64xsp, ImmShift64\nis sf=1 & b_30=0 & b_29=1 & aa_Xd=31 & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp\n{\n\taddflags(Rn_GPR64xsp, ImmShift64);\n\ttmp:8 = Rn_GPR64xsp + ImmShift64;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# CONSTRUCT x3100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x3100001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl0\nis sf=0 & op=0 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_posimm_lsl0 & Rn_GPR32wsp & Rd=0x1f\n{\n\ttmp_1:4 = Imm12_addsubimm_operand_i32_posimm_lsl0;\n\taddflags(Rn_GPR32wsp, tmp_1);\n\tresult:4 = Rn_GPR32wsp + tmp_1;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# CONSTRUCT x3140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x3140001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl12\nis sf=0 & op=0 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_posimm_lsl12 & Rn_GPR32wsp & Rd=0x1f\n{\n\ttmp_1:4 = Imm12_addsubimm_operand_i32_posimm_lsl12;\n\taddflags(Rn_GPR32wsp, tmp_1);\n\tresult:4 = Rn_GPR32wsp + tmp_1;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# CONSTRUCT xb100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb100001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl0\nis sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_posimm_lsl0 & Rn_GPR64xsp & Rd=0x1f\n{\n\ttmp_1:8 = Imm12_addsubimm_operand_i64_posimm_lsl0;\n\taddflags(Rn_GPR64xsp, tmp_1);\n\tresult:8 = Rn_GPR64xsp + tmp_1;\n\tresultflags(result);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f\n# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000\n# CONSTRUCT xb140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb140001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl12\nis sf=1 & op=0 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_posimm_lsl12 & Rn_GPR64xsp & Rd=0x1f\n{\n\ttmp_1:8 = Imm12_addsubimm_operand_i64_posimm_lsl12;\n\taddflags(Rn_GPR64xsp, tmp_1);\n\tresult:8 = Rn_GPR64xsp + tmp_1;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f\n# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000\n# CONSTRUCT x2b00001f/mask=xff20801f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x2b00001f/mask=xff20801f --status pass --comment \"flags\"\n# if shift == '11' then ReservedValue();\n\n:cmn Rn_GPR32, RegShift32\nis sf=0 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=0 & b_15=0 & RegShift32 & Rn_GPR32 & Rd=0x1f\n{\n\ttmp_1:4 = RegShift32;\n\taddflags(Rn_GPR32, tmp_1);\n\tresult:4 = Rn_GPR32 + tmp_1;\n\tresultflags(result);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f\n# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000\n# CONSTRUCT xab00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xab00001f/mask=xff20001f --status pass --comment \"flags\"\n\n:cmn Rn_GPR64, RegShift64\nis sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd=0x1f\n{\n\ttmp_1:8 = RegShift64;\n\taddflags(Rn_GPR64, tmp_1);\n\tresult:8 = Rn_GPR64 + tmp_1;\n\tresultflags(result);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f\n# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000\n# CONSTRUCT x6b20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x6b20001f/mask=xffe0001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR32wsp, ExtendRegShift32\nis sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd=0x1f\n{\n\tsubflags(Rn_GPR32wsp, ExtendRegShift32);\n\ttmp:4 = Rn_GPR32wsp - ExtendRegShift32;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f\n# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000\n# CONSTRUCT xeb20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xeb20001f/mask=xffe0001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR64xsp, ExtendRegShift64\nis sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd=0x1f\n{\n\tsubflags(Rn_GPR64xsp, ExtendRegShift64);\n\ttmp:8 = Rn_GPR64xsp - ExtendRegShift64;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# CONSTRUCT x7100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x7100001f/mask=xff00001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR32xsp, ImmShift32\nis sf=0 & b_30=1 & b_29=1 & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp & aa_Wd=31\n{\n\tsubflags(Rn_GPR32xsp, ImmShift32);\n\ttmp:4 = Rn_GPR32xsp - ImmShift32;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# CONSTRUCT xf100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf100001f/mask=xff00001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR64xsp, ImmShift64\nis sf=1 & b_30=1 & b_29=1 & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & aa_Wd=31\n{\n\tsubflags(Rn_GPR64xsp, ImmShift64);\n\ttmp:8 = Rn_GPR64xsp - ImmShift64;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# CONSTRUCT x7100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x7100001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0\nis sf=0 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd=0x1f\n{\n\ttmp_1:4 = Imm12_addsubimm_operand_i32_negimm_lsl0;\n\tsubflags(Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0);\n\tresult:4 = Rn_GPR32wsp - tmp_1;\n\tresultflags(result);\n\taffectflags();\n}\n\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# CONSTRUCT x7140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x7140001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12\nis sf=0 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd=0x1f\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12;\n\tsubflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tresultflags(tmp_1);\n\taffectflags();\n}\n\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# CONSTRUCT xf100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf100001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0\nis sf=1 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd=0x1f\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0;\n\tsubflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tresultflags(tmp_1);\n\taffectflags();\n}\n\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# CONSTRUCT xf140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf140001f/mask=xffc0001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12\nis sf=1 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd=0x1f\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12;\n\tsubflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tresultflags(tmp_1);\n\taffectflags();\n}\n\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# CONSTRUCT x6b00001f/mask=xff20001f MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x6b00001f/mask=xff20001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR32, RegShift32\nis sf=0 & op=1 & S=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn!=0x1f & Rn_GPR32 & Rd=0x1f\n{\n\tsubflags(Rn_GPR32, RegShift32);\n\ttmp:4 = Rn_GPR32 - RegShift32;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# CONSTRUCT xeb00001f/mask=xff20001f MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xeb00001f/mask=xff20001f --status pass --comment \"flags\"\n\n:cmp Rn_GPR64, RegShift64\nis sf=1 & op=1 & S=1 & b_2428=0xb & b_2121=0 & Rm_GPR64 & RegShift64 & Rn!=0x1f & Rn_GPR64 & Rd=0x1f\n{\n\tsubflags(Rn_GPR64, RegShift64);\n\ttmp:8 = Rn_GPR64 - RegShift64;\n\tresultflags(tmp);\n\taffectflags();\n}\n\n# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00\n# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00\n# CONSTRUCT x5a800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x5a800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:cneg Rd_GPR32, Rn_GPR32, InvCondOp\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=1 & Rn=Rm & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:4 = -Rn_GPR32;\n\tif (condition) goto ;\n\ttmp = Rn_GPR32;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00\n# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00\n# CONSTRUCT xda800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xda800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:cneg Rd_GPR64, Rn_GPR64, InvCondOp\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 & Rn=Rm & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:8 = -Rn_GPR64;\n\tif (condition) goto ;\n\ttmp = Rn_GPR64;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00\n# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00\n# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00\n# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00\n# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES\n\ncpyPhase:\"p\" is opt=0 {export 0:1;}\ncpyPhase:\"m\" is opt=1 {export 1:1;}\ncpyPhase:\"e\" is opt=2 {export 2:1;}\n\ncpyType: \"\"\t\tis b_1015=0x01 {export 0x01:1; }\ncpyType: \"n\"\tis b_1015=0x31 {export 0x31:1; }\ncpyType: \"rn\"\tis b_1015=0x21 {export 0x21:1; }\ncpyType: \"wn\"\tis b_1015=0x11 {export 0x11:1; }\n\ncpyType: \"rt\"\tis b_1015=0x09 {export 0x09:1; }\ncpyType: \"rtn\"\tis b_1015=0x39 {export 0x39:1; }\ncpyType: \"rtrn\"\tis b_1015=0x29 {export 0x29:1; }\ncpyType: \"rtwn\"\tis b_1015=0x19 {export 0x19:1; }\n\ncpyType: \"t\"\tis b_1015=0x0d {export 0x0d:1; }\ncpyType: \"tn\"\tis b_1015=0x3d {export 0x3d:1; }\ncpyType: \"trn\"\tis b_1015=0x2d {export 0x2d:1; }\ncpyType: \"twn\"\tis b_1015=0x1d {export 0x1d:1; }\n\ncpyType: \"wt\"\tis b_1015=0x03 {export 0x03:1; }\ncpyType: \"wtn\"\tis b_1015=0x33 {export 0x33:1; }\ncpyType: \"wtrn\"\tis b_1015=0x23 {export 0x23:1; }\ncpyType: \"wtwn\"\tis b_1015=0x13 {export 0x13:1; }\n\n\ndefine pcodeop MemoryCopyForward;\n# Memory Copy Forward-only\n:cpyf^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^\"!\"\nis size.ldstr & b_2429=0x19 & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64\n{\n\tMemoryCopyForward(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase);\n}\ndefine pcodeop MemoryCopy;\n:cpy^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^\"!\"\nis size.ldstr & b_2429=0x1d & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64\n{\n\tMemoryCopy(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase);\n}\n\n# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH\n# sf == 0 && sz = 00 CRC32CB variant\n\ncrcpoly: \"\" is b_12=0 {tmp:4 = 0x04C11DB7; export *[const]:4 tmp; }\ncrcpoly: \"c\" is b_12=1 { tmp:4 = 0x1EDC6F41; export *[const]:4 tmp; }\n\n# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000\n# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000\n# CONSTRUCT x1ac04000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac04000/mask=xffe0ec00 --status noqemu\n\n:crc32^crcpoly^\"b\" Rd_GPR32, Rn_GPR32, Rm_GPR32\nis b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b00 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp_Rd:4 = crc32b(Rn_GPR32, Rm_GPR32, crcpoly);\n\tRd_GPR64 = zext(tmp_Rd);\n}\n\n# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000\n# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000\n# CONSTRUCT x1ac04400/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac04400/mask=xffe0ec00 --status noqemu\n# sf == 0 && sz = 01 CRC32CH variant\n\n:crc32^crcpoly^\"h\" Rd_GPR32, Rn_GPR32, Rm_GPR32\nis b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b01 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp_Rd:4 = crc32h(Rn_GPR32, Rm_GPR32, crcpoly);\n\tRd_GPR64 = zext(tmp_Rd);\n}\n\n# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000\n# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000\n# CONSTRUCT x1ac04800/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac04800/mask=xffe0ec00 --status noqemu\n# sf == 0 && sz = 10 CRC32CW variant\n\n:crc32^crcpoly^\"w\" Rd_GPR32, Rn_GPR32, Rm_GPR32\nis b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b10 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp_Rd:4 = crc32w(Rn_GPR32, Rm_GPR32, crcpoly);\n\tRd_GPR64 = zext(tmp_Rd);\n}\n\n# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000\n# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000\n# CONSTRUCT x9ac04c00/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ac04c00/mask=xffe0ec00 --status noqemu\n# sf == 1 && sz = 11 CRC32CX variant\n\n:crc32^crcpoly^\"x\" Rd_GPR32, Rn_GPR32, Rm_GPR64\nis b_31=1 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b11 & crcpoly & Rm_GPR64 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp_Rd:4 = crc32x(Rn_GPR32, Rm_GPR64, crcpoly);\n\tRd_GPR64 = zext(tmp_Rd);\n}\n\n# C6.2.103 CSEL page C6-1443 line 86120 MATCH x1a800000/mask=x7fe00c00\n# CONSTRUCT x1a800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x1a800000/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csel Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp\nis sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:4 = Rn_GPR32;\n\tif (condition) goto ;\n\ttmp = Rm_GPR32;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.103 CSEL page C6-1443 line 86120 MATCH x1a800000/mask=x7fe00c00\n# CONSTRUCT x9a800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9a800000/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csel Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp\nis sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=0 & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:8 = Rn_GPR64;\n\tif (condition) goto ;\n\ttmp = Rm_GPR64;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0\n# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00\n# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00\n# CONSTRUCT x1a9f07e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x1a9f07e0/mask=xffff0fe0 --status pass --comment \"flags\"\n\n:cset Rd_GPR32, InvCondOp\nis sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & InvCondOp & b_1011=1 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\tRd_GPR64 = zext(condition);\n}\n\n# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0\n# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00\n# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00\n# CONSTRUCT x9a9f07e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x9a9f07e0/mask=xffff0fe0 --status pass --comment \"flags\"\n\n:cset Rd_GPR64, InvCondOp\nis sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & InvCondOp & b_1011=1 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\tRd_GPR64 = zext(condition);\n}\n\n# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0\n# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00\n# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00\n# CONSTRUCT x5a9f03e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x5a9f03e0/mask=xffff0fe0 --status pass --comment \"flags\"\n\n:csetm Rd_GPR32, InvCondOp\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=0 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\ttmp:4 = zext(condition) * -1;\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0\n# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00\n# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00\n# CONSTRUCT xda9f03e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xda9f03e0/mask=xffff0fe0 --status pass --comment \"flags\"\n\n:csetm Rd_GPR64, InvCondOp\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=0 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = InvCondOp;\n\tRd_GPR64 = zext(condition) * -1;\n}\n\n# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00\n# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00\n# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0\n# CONSTRUCT x1a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x1a800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csinc Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp\nis sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=1 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:4 = Rn_GPR32;\n\tif (condition) goto ;\n\ttmp = Rm_GPR32 + 1;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00\n# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00\n# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0\n# CONSTRUCT x9a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x9a800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csinc Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp\nis sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=1 & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:8 = Rn_GPR64;\n\tif (condition) goto ;\n\ttmp = Rm_GPR64 + 1;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00\n# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00\n# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0\n# CONSTRUCT x5a800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x5a800000/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csinv Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:4 = Rn_GPR32;\n\tif (condition) goto ;\n\ttmp = ~Rm_GPR32;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00\n# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00\n# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0\n# CONSTRUCT xda800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xda800000/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csinv Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=0 & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:8 = Rn_GPR64;\n\tif (condition) goto ;\n\ttmp = ~Rm_GPR64;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00\n# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00\n# CONSTRUCT x5a800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x5a800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csneg Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=1 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:4 = Rn_GPR32;\n\tif (condition) goto ;\n\ttmp = -Rm_GPR32;\n\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00\n# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00\n# CONSTRUCT xda800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xda800400/mask=xffe00c00 --status pass --comment \"flags\"\n\n:csneg Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=1 & Rn_GPR64 & Rd_GPR64\n{\n\tcondition:1 = CondOp;\n\ttmp:8 = Rn_GPR64;\n\tif (condition) goto ;\n\ttmp = -Rm_GPR64;\n\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7420/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd50b7420/mask=xffffffe0 --status nodest\n\n:dc \"ZVA\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b001 & Rt_GPR64\n{ DC_ZVA(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087620/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5087620/mask=xffffffe0 --status nodest\n\n:dc \"IVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b001 & Rt_GPR64\n{ DC_IVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087640/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5087640/mask=xffffffe0 --status nodest\n\n:dc \"ISW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b010 & Rt_GPR64\n{ DC_ISW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7a20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd50b7a20/mask=xffffffe0 --status nopcodeop\n\n:dc \"CVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b001 & Rt_GPR64\n{ DC_CVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087a40/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5087a40/mask=xffffffe0 --status nodest\n\n:dc \"CSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b010 & Rt_GPR64\n{ DC_CSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7b20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd50b7b20/mask=xffffffe0 --status nodest\n\n:dc \"CVAU\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1011 & b_0507=0b001 & Rt_GPR64\n{ DC_CVAU(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7e20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd50b7e20/mask=xffffffe0 --status nodest\n\n:dc \"CIVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b001 & Rt_GPR64\n{ DC_CIVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087e40/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5087e40/mask=xffffffe0 --status nodest\n\n:dc \"CISW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b010 & Rt_GPR64\n{ DC_CISW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7c20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd50b7c20/mask=xffffffe0 --status nodest\n\n:dc \"CVAP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b001 & Rt_GPR64\n{ DC_CVAP(Rt_GPR64); }\n\n# C6.2.110 DCPS1 page C6-1457 line 86790 MATCH xd4a00001/mask=xffe0001f\n# CONSTRUCT xd4a00001/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4a00001/mask=xffe0001f --status nodest\n\n:dcps1 imm16\nis b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=1\n{\n\tDCPSInstruction(1:2, imm16:2);\n}\n\n# C6.2.111 DCPS2 page C6-1458 line 86856 MATCH xd4a00002/mask=xffe0001f\n# CONSTRUCT xd4a00002/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4a00002/mask=xffe0001f --status nodest\n\n:dcps2 imm16\nis b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=2\n{\n\tDCPSInstruction(2:2, imm16:2);\n}\n\n# C6.2.112 DCPS3 page C6-1459 line 86927 MATCH xd4a00003/mask=xffe0001f\n# CONSTRUCT xd4a00003/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4a00003/mask=xffe0001f --status nodest\n\n:dcps3 imm16\nis b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=3\n{\n\tDCPSInstruction(3:2, imm16:2);\n}\n\n# C6.2.114 DMB page C6-1461 line 87029 MATCH xd50330bf/mask=xfffff0ff\n# CONSTRUCT xd50330bf/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd50330bf/mask=xfffff3ff --status nodest\n\n:dmb CRm_CRx\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_CRx & CRm_32 & CRm_10=0 & Op2=5 & Rt=0x1f\n{\n\ttypes:1 = 0x0;\n\tdomain:1 = CRm_32;\n\tDataMemoryBarrier(domain, types);\n}\n\n# C6.2.114 DMB page C6-1461 line 87029 MATCH xd50330bf/mask=xfffff0ff\n# CONSTRUCT xd50330bf/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd50330bf/mask=xfffff0ff --status nodest\n\n:dmb CRm_dbarrier_op\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=5 & Rt=0x1f\n{\n\ttypes:1 = CRm_10;\n\tdomain:1 = CRm_32;\n\tDataMemoryBarrier(domain, types);\n}\n\n# C6.2.115 DRPS page C6-1463 line 87125 MATCH xd6bf03e0/mask=xffffffff\n# CONSTRUCT xd6bf03e0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd6bf03e0/mask=xffffffff --status nodest\n\n:drps\nis b_2531=0x6b & b_2324=1 & b_2122=1 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_0004=0\n{\n\tpc = DRPSInstruction();\n\treturn [pc];\n}\n\n# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503309f/mask=xfffff0ff\n# C6.2.252 PSSBB page C6-1727 line 101951 MATCH xd503349f/mask=xffffffff\n# C6.2.290 SSBB page C6-1810 line 106930 MATCH xd503309f/mask=xffffffff\n# CONSTRUCT xd503309f/mask=xfffff3ff MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd503309f/mask=xfffff3ff --status nodest\n\n:dsb CRm_dbarrier_op\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f\n{\n\ttypes:1 = CRm_10;\n\tdomain:1 = CRm_32;\n\tnXS:1 = 0;\n\tDataSynchronizationBarrier(domain, types, nXS);\n}\n\n:ssbb\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_CRx=0 & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f\n{\n\ttypes:1 = CRm_10;\n\tdomain:1 = CRm_32;\n\tnXS:1 = 0;\n\tDataSynchronizationBarrier(domain, types, nXS);\n}\n\n:pssbb\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_CRx=4 & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f\n{\n\ttypes:1 = CRm_10;\n\tdomain:1 = CRm_32;\n\tnXS:1 = 0;\n\tDataSynchronizationBarrier(domain, types, nXS);\n}\n\n# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff\n# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES\n# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=11010101000000110011..1000111111\n\n:dsb CRm_32\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_32 & CRm_10=2 & Op2=1 & Rt=0x1f\n{\n\ttypes:1 = 0x3; # MBReqTypes_All\n\tdomain:1 = CRm_32;\n\tnXS:1 = 1;\n\tDataSynchronizationBarrier(domain, types, nXS);\n}\n\n# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000\n# CONSTRUCT x4a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x4a200000/mask=xff200000 --status pass\n\n:eon Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=2 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_3:4 = RegShift32Log;\n\ttmp_2:4 = tmp_3 ^ -1:4;\n\ttmp_1:4 = Rn_GPR32 ^ tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000\n# CONSTRUCT xca200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xca200000/mask=xff200000 --status pass\n\n:eon Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=2 & b_2428=0xa & N=1 & Rm_GPR64 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_3:8= RegShift64Log;\n\ttmp_2:8 = tmp_3 ^ -1:8;\n\ttmp_1:8 = Rn_GPR64 ^ tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.119 EOR (immediate) page C6-1470 line 87512 MATCH x52000000/mask=x7f800000\n# CONSTRUCT x52000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x52000000/mask=xff800000 --status pass\n\n:eor Rd_GPR32wsp, Rn_GPR32, DecodeWMask32\nis sf=0 & opc=2 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_1:4 = Rn_GPR32 ^ DecodeWMask32;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.119 EOR (immediate) page C6-1470 line 87512 MATCH x52000000/mask=x7f800000\n# CONSTRUCT xd2000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd2000000/mask=xff800000 --status pass\n\n:eor Rd_GPR64xsp, Rn_GPR64, DecodeWMask64\nis sf=1 & opc=2 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp\n{\n\ttmp_1:8 = Rn_GPR64 ^ DecodeWMask64;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.120 EOR (shifted register) page C6-1472 line 87604 MATCH x4a000000/mask=x7f200000\n# CONSTRUCT x4a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x4a000000/mask=xff200000 --status pass\n\n:eor Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=2 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32Log;\n\ttmp_1:4 = Rn_GPR32 ^ tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.120 EOR (shifted register) page C6-1472 line 87604 MATCH x4a000000/mask=x7f200000\n# CONSTRUCT xca000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xca000000/mask=xff200000 --status pass\n\n:eor Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=2 & b_2428=0xa & N=0 & Rm_GPR64 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64Log;\n\ttmp_1:8 = Rn_GPR64 ^ tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.121 ERET page C6-1474 line 87707 MATCH xd69f03e0/mask=xffffffff\n# CONSTRUCT xd69f03e0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd69f03e0/mask=xffffffff --status nodest\n\n:eret\nis b_2531=0x6b & b_2324=1 & b_2122=0 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_0004=0\n{\n\tpc = ExceptionReturn();\n\treturn [pc];\n}\n\n# C6.2.122 ERETAA, ERETAB page C6-1475 line 87749 MATCH xd69f0bff/mask=xfffffbff\n# CONSTRUCT xd69f0bff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd69f0bff/mask=xffffffff --status nodest\n\n:eretaa\nis eretaa__PACpart & b_0031=0xd69f0bff\n{\n\tpc = ExceptionReturn();\n\tbuild eretaa__PACpart;\n\treturn [pc];\n}\n\n# C6.2.122 ERETAA, ERETAB page C6-1475 line 87749 MATCH xd69f0bff/mask=xfffffbff\n# CONSTRUCT xd69f0fff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd69f0fff/mask=xffffffff --status nodest\n\n:eretab\nis eretab__PACpart & b_0031=0xd69f0fff\n{\n\tpc = ExceptionReturn();\n\tbuild eretab__PACpart;\n\treturn [pc];\n}\n\n# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000\n# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000\n# CONSTRUCT x13800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x13800000/mask=xffe00000 --status pass\n\n:extr Rd_GPR32, Rn_GPR32, Rm_GPR32, LSB_bitfield32_imm\nis sf=0 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=0 & b_21=0 & Rm_GPR32 & LSB_bitfield32_imm & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlsb:8 = LSB_bitfield32_imm;\n\tresult:8 = (zext(Rn_GPR32) << 32) | zext(Rm_GPR32);\n\tresult = (result >> lsb);\n\tRd_GPR64 = zext(result:4);\n}\n\n# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000\n# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000\n# CONSTRUCT x93c00000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x93c00000/mask=xffe00000 --status pass\n\n:extr Rd_GPR64, Rn_GPR64, Rm_GPR64, LSB_bitfield64_imm\nis sf=1 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=1 & b_21=0 & Rm_GPR64 & LSB_bitfield64_imm & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp:8 = (Rm_GPR64 >> LSB_bitfield64_imm:1);\n\tRd_GPR64 = tmp | (Rn_GPR64 << (64:1 - LSB_bitfield64_imm:1));\n}\n\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf\n# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf\n# C6.2.102 CSDB page C6-1442 line 86066 MATCH xd503229f/mask=xffffffff\n# C6.2.113 DGH page C6-1460 line 86992 MATCH xd50320df/mask=xffffffff\n# C6.2.123 ESB page C6-1476 line 87816 MATCH xd503221f/mask=xffffffff\n# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf\n# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf\n# C6.2.251 PSB CSYNC page C6-1726 line 101911 MATCH xd503223f/mask=xffffffff\n# C6.2.381 TSB CSYNC page C6-1982 line 116218 MATCH xd503225f/mask=xffffffff\n# CONSTRUCT xd503201f/mask=xfffff01f MATCHED 10 DOCUMENTED OPCODES\n# AUNIT --inst xd503201f/mask=xfffff01f --status nodest\n\n:hint imm7Low\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low & Rt=0x1f {}\n\n# C6.2.127 HLT page C6-1482 line 88176 MATCH xd4400000/mask=xffe0001f\n# CONSTRUCT xd4400000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4400000/mask=xffe0001f --status nodest\n\n:hlt imm16\nis ALL_BTITARGETS & b_2431=0xd4 & excCode=2 & imm16 & excCode2=0 & ll=0\n{\n\tHaltBreakPoint();\n}\n\n# C6.2.128 HVC page C6-1483 line 88218 MATCH xd4000002/mask=xffe0001f\n# CONSTRUCT xd4000002/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4000002/mask=xffe0001f --status nodest\n\n:hvc imm16\nis b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=2\n{\n\tCallHyperVisor(imm16:2);\n}\n\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087100/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5087100/mask=xffffffe0 --status nodest\n\n:ic \"IALLUIS\"\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0001 & b_0507=0b000\n{ IC_IALLUIS(); }\n\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087500/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5087500/mask=xffffffe0 --status nodest\n\n:ic \"IALLU\"\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0101 & b_0507=0b000\n{ IC_IALLU(); }\n\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7520/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd50b7520/mask=xffffffe0 --status nopcodeop\n\n:ic \"IVAU\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0101 & b_0507=0b001 & Rt_GPR64\n{ IC_IVAU(Rt_GPR64); }\n\n# C6.2.85 ISB page C6-647 line 37682 KEEPWITH\n\nIsbOption: \"#\"^CRm_isb_op is CRm_isb_op { export *[const]:4 CRm_isb_op; }\nIsbOption: \"\" is CRm_isb_op=0xf { tmp:4 = 0xf; export tmp; }\n\n# C6.2.131 ISB page C6-1487 line 88428 MATCH xd50330df/mask=xfffff0ff\n# CONSTRUCT xd50330df/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd50330df/mask=xfffff0ff --status nodest\n\n:isb IsbOption\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & IsbOption & Op2=6 & Rt=0x1f\n{\n\tInstructionSynchronizationBarrier();\n}\n\n# C6.2.86 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-648 line 37726 KEEPWITH\n\n# variants, a=acquire, al=acquire+release, l=release\n# build ls_loa to acquire and ls_lor to release\n\nls_loa: \"a\" is b_23=1 & b_22=0 { LOAcquire(); }\nls_loa: \"al\" is b_23=1 & b_22=1 { LOAcquire(); }\nls_loa: \"\" is b_23=0 & b_22=0 { }\nls_loa: \"l\" is b_23=0 & b_22=1 { }\n\nls_lor: \"a\" is b_23=1 & b_22=0 { }\nls_lor: \"al\" is b_23=1 & b_22=1 { LORelease(); }\nls_lor: \"\" is b_23=0 & b_22=0 { }\nls_lor: \"l\" is b_23=0 & b_22=1 { LORelease(); }\n\nls_data1: is b_3031=0b00 & Rn_GPR64xsp { tmp_ldWn = zext(*:1 Rn_GPR64xsp); }\nls_data2: is b_3031=0b01 & Rn_GPR64xsp { tmp_ldWn = zext(*:2 Rn_GPR64xsp); }\nls_data4: is b_3031=0b10 & Rn_GPR64xsp { tmp_ldWn = *:4 Rn_GPR64xsp; }\nls_data8: is b_3031=0b11 & Rn_GPR64xsp { tmp_ldXn = *:8 Rn_GPR64xsp; }\n\nls_mem1: is Rn_GPR64xsp { *:1 Rn_GPR64xsp = tmp_stWn:1; }\nls_mem2: is Rn_GPR64xsp { *:2 Rn_GPR64xsp = tmp_stWn:2; }\nls_mem4: is Rn_GPR64xsp { *:4 Rn_GPR64xsp = tmp_stWn; }\nls_mem8: is Rn_GPR64xsp { *:8 Rn_GPR64xsp = tmp_stXn; }\n\nmacro ls_opc_add (data, value, dest) { dest = data + value; }\nmacro ls_opc_clr (data, value, dest) { dest = data & (~ value); }\nmacro ls_opc_eor (data, value, dest) { dest = data ^ value; }\nmacro ls_opc_set (data, value, dest) { dest = data | value; }\nmacro ls_opc_smax(data, value, dest) { dest = zext(data s> value) * data + zext(data s<= value) * value; }\nmacro ls_opc_smin(data, value, dest) { dest = zext(data s> value) * value + zext(data s<= value) * data; }\nmacro ls_opc_umax(data, value, dest) { dest = zext(data > value) * data + zext(data <= value) * value; }\nmacro ls_opc_umin(data, value, dest) { dest = zext(data > value) * value + zext(data <= value) * data; }\nmacro ls_opc_swp (data, value, dest) { dest = value; }\n\nls_opc1: \"add\" is b_3031=0b00 & b_1215=0b0000 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"add\" is b_3031=0b01 & b_1215=0b0000 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"add\" is b_3031=0b10 & b_1215=0b0000 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"add\" is b_3031=0b11 & b_1215=0b0000 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_add(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"clr\" is b_3031=0b00 & b_1215=0b0001 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"clr\" is b_3031=0b01 & b_1215=0b0001 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"clr\" is b_3031=0b10 & b_1215=0b0001 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"clr\" is b_3031=0b11 & b_1215=0b0001 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_clr(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"eor\" is b_3031=0b00 & b_1215=0b0010 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"eor\" is b_3031=0b01 & b_1215=0b0010 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"eor\" is b_3031=0b10 & b_1215=0b0010 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"eor\" is b_3031=0b11 & b_1215=0b0010 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_eor(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"set\" is b_3031=0b00 & b_1215=0b0011 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"set\" is b_3031=0b01 & b_1215=0b0011 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"set\" is b_3031=0b10 & b_1215=0b0011 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"set\" is b_3031=0b11 & b_1215=0b0011 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_set(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"smax\" is b_3031=0b00 & b_1215=0b0100 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"smax\" is b_3031=0b01 & b_1215=0b0100 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"smax\" is b_3031=0b10 & b_1215=0b0100 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"smax\" is b_3031=0b11 & b_1215=0b0100 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_smax(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"smin\" is b_3031=0b00 & b_1215=0b0101 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"smin\" is b_3031=0b01 & b_1215=0b0101 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"smin\" is b_3031=0b10 & b_1215=0b0101 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"smin\" is b_3031=0b11 & b_1215=0b0101 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_smin(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"umax\" is b_3031=0b00 & b_1215=0b0110 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"umax\" is b_3031=0b01 & b_1215=0b0110 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"umax\" is b_3031=0b10 & b_1215=0b0110 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"umax\" is b_3031=0b11 & b_1215=0b0110 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_umax(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\nls_opc1: \"umin\" is b_3031=0b00 & b_1215=0b0111 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }\nls_opc2: \"umin\" is b_3031=0b01 & b_1215=0b0111 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }\nls_opc4: \"umin\" is b_3031=0b10 & b_1215=0b0111 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }\nls_opc8: \"umin\" is b_3031=0b11 & b_1215=0b0111 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_umin(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }\n\n# Nearly all of these instructions have the same \"operation\" in the\n# manual, the differences being load vs store, the operation (o3:opc),\n# the data size, and the load store semantics of the atomic load and\n# store types (AccType). The opcode mnemonic varies, however. And to\n# facilitate reading, the LD/ST/SWP variants have been separated out.\n\n# C6.2.133 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-1489 line 88545 MATCH x38200000/mask=xff20fc00\n# C6.2.152 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB page C6-1524 line 90495 MATCH x38201000/mask=xff20fc00\n# C6.2.155 LDEORB, LDEORAB, LDEORALB, LDEORLB page C6-1531 line 90916 MATCH x38202000/mask=xff20fc00\n# C6.2.181 LDSETB, LDSETAB, LDSETALB, LDSETLB page C6-1590 line 94403 MATCH x38203000/mask=xff20fc00\n# C6.2.184 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB page C6-1597 line 94824 MATCH x38204000/mask=xff20fc00\n# C6.2.187 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB page C6-1604 line 95245 MATCH x38205000/mask=xff20fc00\n# C6.2.196 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB page C6-1623 line 96362 MATCH x38206000/mask=xff20fc00\n# C6.2.199 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB page C6-1630 line 96783 MATCH x38207000/mask=xff20fc00\n# CONSTRUCT x38200000/mask=xff208c00 MATCHED 8 DOCUMENTED OPCODES\n# AUNIT --inst x38200000/mask=xff208c00 --status nomem\n\n# size=0b00 (3031)\n\n:ld^ls_opc1^ls_lor^\"b\" aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc1 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp\n{ build ls_loa; build ls_opc1; aa_Wt = tmp_ldWn; build ls_lor; }\n\n# C6.2.134 LDADDH, LDADDAH, LDADDALH, LDADDLH page C6-1491 line 88670 MATCH x78200000/mask=xff20fc00\n# C6.2.153 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH page C6-1526 line 90621 MATCH x78201000/mask=xff20fc00\n# C6.2.156 LDEORH, LDEORAH, LDEORALH, LDEORLH page C6-1533 line 91042 MATCH x78202000/mask=xff20fc00\n# C6.2.182 LDSETH, LDSETAH, LDSETALH, LDSETLH page C6-1592 line 94529 MATCH x78203000/mask=xff20fc00\n# C6.2.185 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH page C6-1599 line 94950 MATCH x78204000/mask=xff20fc00\n# C6.2.188 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH page C6-1606 line 95371 MATCH x78205000/mask=xff20fc00\n# C6.2.197 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH page C6-1625 line 96488 MATCH x78206000/mask=xff20fc00\n# C6.2.200 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH page C6-1632 line 96909 MATCH x78207000/mask=xff20fc00\n# CONSTRUCT x78200000/mask=xff208c00 MATCHED 8 DOCUMENTED OPCODES\n# AUNIT --inst x78200000/mask=xff208c00 --status nomem\n\n# size=0b01 (3031)\n\n:ld^ls_opc2^ls_lor^\"h\" aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc2 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp\n{ build ls_loa; build ls_opc2; aa_Wt = tmp_ldWn; build ls_lor; }\n\n# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00\n# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00\n# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00\n# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00\n# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00\n# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00\n# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00\n# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00\n# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f\n# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f\n# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f\n# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f\n# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f\n# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f\n# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f\n# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f\n# CONSTRUCT xb8200000/mask=xff208c00 MATCHED 16 DOCUMENTED OPCODES\n# AUNIT --inst xb8200000/mask=xff208c00 --status nomem\n\n# size=0b10 (3031)\n\n:ld^ls_opc4^ls_lor aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc4 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp\n{ build ls_loa; build ls_opc4; aa_Wt = tmp_ldWn; build ls_lor; }\n\n# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00\n# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00\n# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00\n# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00\n# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00\n# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00\n# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00\n# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00\n# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f\n# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f\n# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f\n# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f\n# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f\n# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f\n# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f\n# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f\n# CONSTRUCT xf8200000/mask=xff208c00 MATCHED 16 DOCUMENTED OPCODES\n# AUNIT --inst xf8200000/mask=xff208c00 --status nomem\n\n# size=0b11 (3031)\n\n:ld^ls_opc8^ls_lor aa_Xs, aa_Xt, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc8 & ls_loa & ls_lor & aa_Xt & aa_Xs & Rn_GPR64xsp\n{ build ls_loa; build ls_opc8; aa_Xt = tmp_ldXn; build ls_lor; }\n\n# C6.2.136 LDAPR page C6-1496 line 88965 MATCH xb8a0c000/mask=xbfe0fc00\n# CONSTRUCT xb8a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb8a0c000/mask=xffe0fc00 --status nomem\n# TODO unsure of load/release semantics for this instruction\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n# size == 10 32-bit variant\n\n:ldapr aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data4\n{\n\taa_Wt = tmp_ldWn;\n}\n\n# C6.2.136 LDAPR page C6-1496 line 88965 MATCH xb8a0c000/mask=xbfe0fc00\n# CONSTRUCT xf8a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8a0c000/mask=xffe0fc00 --status nomem\n# TODO unsure of load/release semantics for this instruction\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n# size == 11 64-bit variant\n\n:ldapr aa_Xt, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Xt & ls_data8\n{\n\taa_Xt = tmp_ldXn;\n}\n\n# C6.2.137 LDAPRB page C6-1498 line 89064 MATCH x38a0c000/mask=xffe0fc00\n# CONSTRUCT x38a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x38a0c000/mask=xffe0fc00 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n# TODO unsure of load/release semantics for this instruction\n\n:ldaprb aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data1\n{\n\taa_Wt = tmp_ldWn;\n}\n\n# C6.2.138 LDAPRH page C6-1500 line 89148 MATCH x78a0c000/mask=xffe0fc00\n# CONSTRUCT x78a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x78a0c000/mask=xffe0fc00 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n\n:ldaprh aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data2\n{\n\taa_Wt = tmp_ldWn;\n}\n\n\n# C6.2.139 LDAPUR page C6-1502 line 89232 MATCH x99400000/mask=xbfe00c00\n# CONSTRUCT x99400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# The following commands are not yet implemented.\n\n\n# x99400000/mask=xbfe00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:ldapur aa_Wt, addr_SIMM9\nis b_3031=0b10 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt\n{\n\taa_Xt = zext(*:4 addr_SIMM9);\n}\n\n# C6.2.139 LDAPUR page C6-1502 line 89232 MATCH x99400000/mask=xbfe00c00\n# CONSTRUCT xd9400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldapur aa_Xt, addr_SIMM9\nis b_3031=0b11 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Xt\n{\n\taa_Xt = *addr_SIMM9;\n}\n\n# C6.2.140 LDAPURB page C6-1504 line 89343 MATCH x19400000/mask=xffe00c00\n# CONSTRUCT x19400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x19400000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:ldapurb aa_Wt, addr_SIMM9\nis b_3031=0b00 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt\n{\n\taa_Xt = zext(*:1 addr_SIMM9);\n}\n\n# C6.2.141 LDAPURH page C6-1506 line 89439 MATCH x59400000/mask=xffe00c00\n# CONSTRUCT x59400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x59400000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:ldapurh aa_Wt, addr_SIMM9\nis b_3031=0b01 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt\n{\n\taa_Xt = zext(*:2 addr_SIMM9);\n}\n\n\n# C6.2.142 LDAPURSB page C6-1508 line 89535 MATCH x19800000/mask=xffa00c00\n# CONSTRUCT x19c00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x19800000/mask=xffa00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:ldapursb aa_Wt, addr_SIMM9\nis b_3031=0b00 & b_2329=0b0110011 & b_22=1 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt\n{\n\taa_Xt = 0;\n\taa_Wt = sext(*:1 addr_SIMM9);\n}\n\n# C6.2.142 LDAPURSB page C6-1508 line 89535 MATCH x19800000/mask=xffa00c00\n# CONSTRUCT x19800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldapursb aa_Xt, addr_SIMM9\nis b_3031=0b00 & b_2329=0b0110011 & b_22=0 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Xt\n{\n\taa_Xt = sext(*:1 addr_SIMM9);\n}\n\n# C6.2.143 LDAPURSH page C6-1510 line 89667 MATCH x59800000/mask=xffa00c00\n# CONSTRUCT x59c00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x59800000/mask=xffa00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:ldapursh aa_Wt, addr_SIMM9\nis b_3031=0b01 & b_2329=0b0110011 & b_22=1 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt\n{\n\taa_Xt = 0;\n\taa_Wt = sext(*:2 addr_SIMM9);\n}\n\n# C6.2.143 LDAPURSH page C6-1510 line 89667 MATCH x59800000/mask=xffa00c00\n# CONSTRUCT x59800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldapursh aa_Xt, addr_SIMM9\nis b_3031=0b01 & b_2329=0b0110011 & b_22=0 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Xt\n{\n\taa_Xt = sext(*:2 addr_SIMM9);\n}\n\n# C6.2.144 LDAPURSW page C6-1512 line 89799 MATCH x99800000/mask=xffe00c00\n# CONSTRUCT x99800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x99800000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:ldapursw aa_Xt, addr_SIMM9\nis b_3031=0b10 & b_2129=0b011001100 & b_1011=0b00 & addr_SIMM9 & aa_Xt\n{\n\taa_Xt = sext(*:4 addr_SIMM9);\n}\n\n# C6.2.145 LDAR page C6-1514 line 89895 MATCH x88c08000/mask=xbfe08000\n# CONSTRUCT xc8c08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8c08000/mask=xffe08000 --status nomem\n# The manual states that Rs and Rt2 should be all ones, which is\n# optionally enforced.\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldar Rt_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR64\n{\n\tRt_GPR64 = *addrReg;\n}\n\n# C6.2.145 LDAR page C6-1514 line 89895 MATCH x88c08000/mask=xbfe08000\n# CONSTRUCT x88dffc00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88dffc00/mask=xfffffc00 --status nomem\n# Enforce SHOULD BE ONE fields b_1620 & b_1014\n\n:ldar Rt_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = *addrReg;\n}\n\n# C6.2.146 LDARB page C6-1516 line 89986 MATCH x08c08000/mask=xffe08000\n# CONSTRUCT x08c08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08c08000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldarb Rt_GPR32, addrReg\nis size.ldstr=0 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrReg);\n}\n\n# C6.2.147 LDARH page C6-1517 line 90054 MATCH x48c08000/mask=xffe08000\n# CONSTRUCT x48dffc00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48dffc00/mask=xfffffc00 --status nomem\n# Enforce SHOULD BE ONE fields b_1620 & b_1014\n\n:ldarh Rt_GPR32, addrReg\nis size.ldstr=1 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:2 addrReg);\n}\n\n# C6.2.148 LDAXP page C6-1518 line 90122 MATCH x88608000/mask=xbfe08000\n# CONSTRUCT xc8608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8608000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n\n:ldaxp Rt_GPR64, Rt2_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=1 & Rt2_GPR64 & addrReg & Rt_GPR64\n{\n\tlocal addrval1:8 = *(addrReg);\n\tlocal addrval2:8 = *(addrReg+8);\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.148 LDAXP page C6-1518 line 90122 MATCH x88608000/mask=xbfe08000\n# CONSTRUCT x88608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88608000/mask=xffe08000 --status nomem\n\n:ldaxp Rt_GPR32, Rt2_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_1620 & b_15=1 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64\n{\n\tlocal addrval1:8 = zext(*:4(addrReg));\n\tlocal addrval2:8 = zext(*:4(addrReg+4));\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.149 LDAXR page C6-1520 line 90256 MATCH x88408000/mask=xbfe08000\n# CONSTRUCT xc8408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8408000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldaxr Rt_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR64\n{\n\tRt_GPR64 = *addrReg;\n}\n\n# C6.2.149 LDAXR page C6-1520 line 90256 MATCH x88408000/mask=xbfe08000\n# CONSTRUCT x88408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88408000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldaxr Rt_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\ttmp:4 = *addrReg;\n\tRt_GPR64 = zext(tmp);\n}\n\n# C6.2.150 LDAXRB page C6-1522 line 90351 MATCH x08408000/mask=xffe08000\n# CONSTRUCT x08408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08408000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldaxrb Rt_GPR32, addrReg\nis size.ldstr=0 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\ttmp:1 = *addrReg;\n\tRt_GPR64 = zext(tmp);\n}\n\n# C6.2.151 LDAXRH page C6-1523 line 90423 MATCH x48408000/mask=xffe08000\n# CONSTRUCT x48408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48408000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldaxrh Rt_GPR32, addrReg\nis size.ldstr=1 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\ttmp:2 = *addrReg;\n\tRt_GPR64 = zext(tmp);\n}\n\n# C6.2.160 LDLARB page C6-1540 line 91472 MATCH x08c00000/mask=xffe08000\n# CONSTRUCT x08c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08c00000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b00 (3031)\n\n:ldlarb aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp\n{ LOAcquire(); aa_Wt = zext(*:1 Rn_GPR64xsp); }\n\n# C6.2.161 LDLARH page C6-1541 line 91541 MATCH x48c00000/mask=xffe08000\n# CONSTRUCT x48c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48c00000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b01 (3031)\n\n:ldlarh aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp\n{ LOAcquire(); aa_Wt = zext(*:2 Rn_GPR64xsp); }\n\n# C6.2.162 LDLAR page C6-1542 line 91610 MATCH x88c00000/mask=xbfe08000\n# CONSTRUCT x88c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88c00000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b10 (3031)\n\n:ldlar aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp\n{ LOAcquire(); aa_Wt = *:4 Rn_GPR64xsp; }\n\n# C6.2.162 LDLAR page C6-1542 line 91610 MATCH x88c00000/mask=xbfe08000\n# CONSTRUCT xc8c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8c00000/mask=xffe08000 --status nomem\n# size=0b11 (3031)\n\n:ldlar aa_Xt, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Xt & Rn_GPR64xsp\n{ LOAcquire(); aa_Xt = *:8 Rn_GPR64xsp; }\n\n# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000\n# CONSTRUCT x28400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x28400000/mask=xffc00000 --status nomem\n\n:ldnp Rt_GPR32, Rt2_GPR32, addrPairIndexed\nis b_3031=0b00 & b_2229=0b10100001 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64\n{\n\tlocal addrval1:8 = zext(*:4 addrPairIndexed);\n\tlocal addrval2:8 = zext(*:4 (addrPairIndexed + 4));\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000\n# CONSTRUCT xa8400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xa8400000/mask=xffc00000 --status nomem\n\n:ldnp Rt_GPR64, Rt2_GPR64, addrPairIndexed\nis b_3031=0b10 & b_2229=0b10100001 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64\n{\n\tlocal addrval1:8 = *addrPairIndexed;\n\tlocal addrval2:8 = *(addrPairIndexed + 8);\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.164 LDP page C6-1546 line 91841 MATCH x28c00000/mask=x7fc00000\n# C6.2.164 LDP page C6-1546 line 91841 MATCH x29c00000/mask=x7fc00000\n# C6.2.164 LDP page C6-1546 line 91841 MATCH x29400000/mask=x7fc00000\n# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000\n# CONSTRUCT x28400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x28400000/mask=xfe400000 --status nomem\n# opc == 00 post-index, pre-index, and signed 32-bit variant\n\n:ldp Rt_GPR32, Rt2_GPR32, addrPairIndexed\nis b_3031=0b00 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64\n{\n\tlocal addrval1:8 = zext(*:4 addrPairIndexed);\n\tlocal addrval2:8 = zext(*:4 (addrPairIndexed + 4));\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.164 LDP page C6-1546 line 91841 MATCH x28c00000/mask=x7fc00000\n# C6.2.164 LDP page C6-1546 line 91841 MATCH x29c00000/mask=x7fc00000\n# C6.2.164 LDP page C6-1546 line 91841 MATCH x29400000/mask=x7fc00000\n# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000\n# CONSTRUCT xa8400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xa8400000/mask=xfe400000 --status nomem\n# opc == 10 post-index, pre-index, and signed 64-bit variant\n\n:ldp Rt_GPR64, Rt2_GPR64, addrPairIndexed\nis b_3031=0b10 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64\n{\n\tlocal addrval1:8 = *addrPairIndexed;\n\tlocal addrval2:8 = *(addrPairIndexed + 8);\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x68c00000/mask=xffc00000\n# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x69c00000/mask=xffc00000\n# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x69400000/mask=xffc00000\n# CONSTRUCT x68400000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x68400000/mask=xfe400000 --status nomem\n\n:ldpsw Rt_GPR64, Rt2_GPR64, addrPairIndexed\nis b_2531=0b0110100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64\n{\n\tlocal addrval1:8 = sext(*:4 addrPairIndexed);\n\tlocal addrval2:8 = sext(*:4 (addrPairIndexed + 8));\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb9400000/mask=xbfc00000\n# CONSTRUCT xb9400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb9400000/mask=xffc00000 --status nomem\n\n:ldr Rt_GPR32, addrUIMM\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:4 addrUIMM);\n}\n\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00\n# C6.2.190 LDTR page C6-1611 line 95666 MATCH xb8400800/mask=xbfe00c00\n# C6.2.202 LDUR page C6-1637 line 97204 MATCH xb8400000/mask=xbfe00c00\n# CONSTRUCT xb8400000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xb8400000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"r\" Rt_GPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:4 addrIndexed);\n}\n\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00\n# CONSTRUCT xb8400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb8400400/mask=xffe00400 --status nomem\n\n:ldr Rt_GPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:4 addrIndexed);\n}\n\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb9400000/mask=xbfc00000\n# CONSTRUCT xf9400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf9400000/mask=xffc00000 --status nomem\n\n:ldr Rt_GPR64, addrUIMM\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR64\n{\n\tRt_GPR64 = *addrUIMM;\n}\n\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00\n# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00\n# CONSTRUCT xf8400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf8400400/mask=xffe00400 --status nomem\n\n:ldr Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = *addrIndexed;\n}\n\n# C6.2.167 LDR (literal) page C6-1556 line 92457 MATCH x18000000/mask=xbf000000\n# CONSTRUCT x18000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x18000000/mask=xff000000 --status nomem\n\n:ldr Rt_GPR32, AddrLoc19\nis size.ldstr=0 & b_2729=3 & v=0 & b_2425=0 & AddrLoc19 & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:4 AddrLoc19);\n}\n\n# C6.2.167 LDR (literal) page C6-1556 line 92457 MATCH x18000000/mask=xbf000000\n# CONSTRUCT x58000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x58000000/mask=xff000000 --status nomem\n\n:ldr Rt_GPR64, AddrLoc19\nis size.ldstr=1 & b_2729=3 & v=0 & b_2425=0 & AddrLoc19 & Rt_GPR64\n{\n\tRt_GPR64 = *:4 AddrLoc19;\n}\n\n# C6.2.168 LDR (register) page C6-1558 line 92557 MATCH xb8600800/mask=xbfe00c00\n# CONSTRUCT xb8600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb8600800/mask=xffe00c00 --status nomem\n\n:ldr Rt_GPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:4 addrIndexed);\n}\n\n# C6.2.168 LDR (register) page C6-1558 line 92557 MATCH xb8600800/mask=xbfe00c00\n# CONSTRUCT xf8600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8600800/mask=xffe00c00 --status nomem\n\n:ldr Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = *addrIndexed;\n}\n\n\n# C6.2.169 LDRAA, LDRAB page C6-1560 line 92679 MATCH xf8200400/mask=xff200400\n# CONSTRUCT xf8200400/mask=xffa00400 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8200400/mask=xffa00400 --status nomem\n# M == 0 && W == 0 key A, offset variant\n# M == 0 && W == 1 key A, offset variant\n\n:ldraa Rt_GPR64, addrIndexed\nis ldraa__PACpart & b_2431=0b11111000 & b_23=0 & b_21=1 & b_10=1 & addrIndexed & Rn_GPR64xsp & Rt_GPR64\n{\n\tbuild ldraa__PACpart;\n\tbuild addrIndexed;\n\t# Note: if writeback is used, the writeback'd value doesn't have a PAC code! It's the output of AuthDA.\n\tRt_GPR64 = *:8 addrIndexed;\n}\n\n# C6.2.169 LDRAA, LDRAB page C6-1560 line 92679 MATCH xf8200400/mask=xff200400\n# CONSTRUCT xf8a00400/mask=xffa00400 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8a00400/mask=xffa00400 --status nomem\n# M == 1 && W == 0 key B, offset variant\n# M == 1 && W == 1 key B, offset variant\n\n:ldrab Rt_GPR64, addrIndexed\nis ldrab__PACpart & b_2431=0b11111000 & b_23=1 & b_21=1 & b_10=1 & addrIndexed & Rn_GPR64xsp & Rt_GPR64\n{\n\tbuild ldrab__PACpart;\n\tbuild addrIndexed;\n\t# Note: if writeback is used, the writeback'd value doesn't have a PAC code! It's the output of AuthDB.\n\tRt_GPR64 = *:8 addrIndexed;\n}\n\n# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x38400400/mask=xffe00c00\n# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x38400c00/mask=xffe00c00\n# CONSTRUCT x38400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x38400400/mask=xffe00400 --status nomem\n# post-index and pre-index variants\n\n:ldrb Rt_GPR32, addrIndexed\nis b_2131=0b00111000010 & b_10=1 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrIndexed);\n}\n\n# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x39400000/mask=xffc00000\n# CONSTRUCT x39400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x39400000/mask=xffc00000 --status nomem\n# unsigned offset variant\n\n:ldrb Rt_GPR32, addrIndexed\nis b_2231=0b0011100101 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrIndexed);\n}\n\n# C6.2.171 LDRB (register) page C6-1565 line 92976 MATCH x38600800/mask=xffe00c00\n# CONSTRUCT x38600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x38600800/mask=xffe00c00 --status nomem\n# extended register and shifted register variant\n# determined in addrIndexed subtable\n\n:ldrb Rt_GPR32, addrIndexed\nis b_2131=0b00111000011 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrIndexed);\n}\n\n# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x79400000/mask=xffc00000\n# CONSTRUCT x79400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x79400000/mask=xffc00000 --status nomem\n\n:ldrh Rt_GPR32, addrUIMM\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:2 addrUIMM);\n}\n\n# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x78400400/mask=xffe00c00\n# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x78400c00/mask=xffe00c00\n# CONSTRUCT x78400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x78400400/mask=xffe00400 --status nomem\n\n:ldrh Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:2 addrIndexed);\n}\n\n# C6.2.173 LDRH (register) page C6-1570 line 93238 MATCH x78600800/mask=xffe00c00\n# CONSTRUCT x78600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x78600800/mask=xffe00c00 --status nomem\n\n:ldrh Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:2 addrIndexed);\n}\n\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x39800000/mask=xff800000\n# CONSTRUCT x39c00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x39c00000/mask=xffc00000 --status nomem\n\n:ldrsb Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_2223=3 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00\n# C6.2.193 LDTRSB page C6-1617 line 95984 MATCH x38800800/mask=xffa00c00\n# C6.2.205 LDURSB page C6-1641 line 97443 MATCH x38800000/mask=xffa00c00\n# CONSTRUCT x38c00000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x38c00000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rsb\" Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrIndexed);\n}\n\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00\n# CONSTRUCT x38c00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x38c00400/mask=xffe00400 --status nomem\n\n:ldrsb Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x39800000/mask=xff800000\n# CONSTRUCT x39800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x39800000/mask=xffc00000 --status nomem\n\n:ldrsb Rt_GPR64, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00\n# C6.2.193 LDTRSB page C6-1617 line 95984 MATCH x38800800/mask=xffa00c00\n# C6.2.205 LDURSB page C6-1641 line 97443 MATCH x38800000/mask=xffa00c00\n# CONSTRUCT x38800000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x38800000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rsb\" Rt_GPR64, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00\n# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00\n# CONSTRUCT x38800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x38800400/mask=xffe00400 --status nomem\n\n:ldrsb Rt_GPR64, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.175 LDRSB (register) page C6-1576 line 93573 MATCH x38a00800/mask=xffa00c00\n# CONSTRUCT x38e00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x38e00800/mask=xffe00c00 --status nomem\n\n:ldrsb Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.175 LDRSB (register) page C6-1576 line 93573 MATCH x38a00800/mask=xffa00c00\n# CONSTRUCT x38a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x38a00800/mask=xffe00c00 --status nomem\n\n:ldrsb Rt_GPR64, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:1 addrIndexed);\n}\n\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x79800000/mask=xff800000\n# CONSTRUCT x79c00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x79c00000/mask=xffc00000 --status nomem\n\n:ldrsh Rt_GPR32, addrUIMM\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_2223=3 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrUIMM);\n}\n\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00\n# C6.2.194 LDTRSH page C6-1619 line 96122 MATCH x78800800/mask=xffa00c00\n# C6.2.206 LDURSH page C6-1643 line 97560 MATCH x78800000/mask=xffa00c00\n# CONSTRUCT x78c00000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x78c00000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rsh\" Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrIndexed);\n}\n\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00\n# CONSTRUCT x78c00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x78c00400/mask=xffe00400 --status nomem\n\n:ldrsh Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrIndexed);\n}\n\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x79800000/mask=xff800000\n# CONSTRUCT x79800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x79800000/mask=xffc00000 --status nomem\n\n:ldrsh Rt_GPR64, addrUIMM\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrUIMM & Rn_GPR64xsp & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrUIMM);\n}\n\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00\n# C6.2.194 LDTRSH page C6-1619 line 96122 MATCH x78800800/mask=xffa00c00\n# C6.2.206 LDURSH page C6-1643 line 97560 MATCH x78800000/mask=xffa00c00\n# CONSTRUCT x78800000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x78800000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rsh\" Rt_GPR64, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrIndexed);\n}\n\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00\n# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00\n# CONSTRUCT x78800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x78800400/mask=xffe00400 --status nomem\n\n:ldrsh Rt_GPR64, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrIndexed);\n}\n\n# C6.2.177 LDRSH (register) page C6-1582 line 93951 MATCH x78a00800/mask=xffa00c00\n# CONSTRUCT x78e00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x78e00800/mask=xffe00c00 --status nomem\n\n:ldrsh Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrIndexed);\n}\n\n# C6.2.177 LDRSH (register) page C6-1582 line 93951 MATCH x78a00800/mask=xffa00c00\n# CONSTRUCT x78a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x78a00800/mask=xffe00c00 --status nomem\n\n:ldrsh Rt_GPR64, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:2 addrIndexed);\n}\n\n# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb8800400/mask=xffe00c00\n# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb8800c00/mask=xffe00c00\n# CONSTRUCT xb8800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb8800400/mask=xffe00400 --status nomem\n\n:ldrsw Rt_GPR64, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:4 addrIndexed);\n}\n\n# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb9800000/mask=xffc00000\n# CONSTRUCT xb9800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb9800000/mask=xffc00000 --status nomem\n\n:ldrsw Rt_GPR64, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:4 addrIndexed);\n}\n\n# C6.2.179 LDRSW (literal) page C6-1587 line 94246 MATCH x98000000/mask=xff000000\n# CONSTRUCT x98000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x98000000/mask=xff000000 --status nomem\n\n:ldrsw Rt_GPR64, AddrLoc19\nis b_2431=0b10011000 & AddrLoc19 & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:4 AddrLoc19);\n}\n\n# C6.2.180 LDRSW (register) page C6-1588 line 94304 MATCH xb8a00800/mask=xffe00c00\n# CONSTRUCT xb8a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb8a00800/mask=xffe00c00 --status nomem\n\n:ldrsw Rt_GPR64, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:4 addrIndexed);\n}\n\n# C6.2.190 LDTR page C6-1611 line 95666 MATCH xb8400800/mask=xbfe00c00\n# CONSTRUCT xf8400800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8400800/mask=xffe00c00 --status nomem\n\n:ld^UnscPriv^\"r\" Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=1 & b_2121=0 & b_1011=2 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = *addrIndexed;\n}\n\n# C6.2.191 LDTRB page C6-1613 line 95782 MATCH x38400800/mask=xffe00c00\n# C6.2.203 LDURB page C6-1639 line 97301 MATCH x38400000/mask=xffe00c00\n# CONSTRUCT x38400000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x38400000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rb\" Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrIndexed);\n}\n\n# C6.2.192 LDTRH page C6-1615 line 95883 MATCH x78400800/mask=xffe00c00\n# C6.2.204 LDURH page C6-1640 line 97372 MATCH x78400000/mask=xffe00c00\n# CONSTRUCT x78400000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x78400000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rh\" Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:2 addrIndexed);\n}\n\n# C6.2.195 LDTRSW page C6-1621 line 96261 MATCH xb8800800/mask=xffe00c00\n# C6.2.207 LDURSW page C6-1645 line 97677 MATCH xb8800000/mask=xffe00c00\n# CONSTRUCT xb8800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb8800000/mask=xffe00000 --status nomem\n\n:ld^UnscPriv^\"rsw\" Rt_GPR64, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = sext(*:4 addrIndexed);\n}\n\n# C6.2.202 LDUR page C6-1637 line 97204 MATCH xb8400000/mask=xbfe00c00\n# CONSTRUCT xf8400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8400000/mask=xffe00c00 --status nomem\n\n:ld^UnscPriv^\"r\" Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2122=2 & b_1011=0 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tRt_GPR64 = *addrIndexed;\n}\n\n# C6.2.208 LDXP page C6-1646 line 97748 MATCH x88600000/mask=xbfe08000\n# CONSTRUCT xc8600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8600000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n\n:ldxp Rt_GPR64, Rt2_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=0 & Rt2_GPR64 & addrReg & Rt_GPR64\n{\n\tlocal addrval1:8 = *addrReg;\n\tlocal addrval2:8 = *(addrReg + 8);\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.208 LDXP page C6-1646 line 97748 MATCH x88600000/mask=xbfe08000\n# CONSTRUCT x88600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88600000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111\n\n:ldxp Rt_GPR32, Rt2_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=0 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64\n{\n\tlocal addrval1:8 = zext(*:4 addrReg);\n\tlocal addrval2:8 = zext(*:4 (addrReg + 4));\n\tRt_GPR64 = addrval1;\n\tRt2_GPR64 = addrval2;\n}\n\n# C6.2.209 LDXR page C6-1648 line 97882 MATCH x88400000/mask=xbfe08000\n# CONSTRUCT xc8400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8400000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldxr Rt_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR64\n{\n\tRt_GPR64 = *addrReg;\n}\n\n# C6.2.209 LDXR page C6-1648 line 97882 MATCH x88400000/mask=xbfe08000\n# CONSTRUCT x88400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88400000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldxr Rt_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:4 addrReg);\n}\n\n# C6.2.210 LDXRB page C6-1650 line 97976 MATCH x08400000/mask=xffe08000\n# CONSTRUCT x08400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08400000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldxrb Rt_GPR32, addrReg\nis size.ldstr=0 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:1 addrReg);\n}\n\n# C6.2.211 LDXRH page C6-1651 line 98048 MATCH x48400000/mask=xffe08000\n# CONSTRUCT x48400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48400000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:ldxrh Rt_GPR32, addrReg\nis size.ldstr=1 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64\n{\n\tRt_GPR64 = zext(*:2 addrReg);\n}\n\n# C6.2.212 LSL (register) page C6-1652 line 98120 MATCH x1ac02000/mask=x7fe0fc00\n# C6.2.214 LSLV page C6-1656 line 98305 MATCH x1ac02000/mask=x7fe0fc00\n# CONSTRUCT x1ac02000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac02000/mask=xffe0fc00 --status pass\n\n:lsl Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x8 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tshiftval:8 = zext(Rm_GPR32 & 0x1f);\n\ttmp_1:4 = Rn_GPR32 << shiftval;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.212 LSL (register) page C6-1652 line 98120 MATCH x1ac02000/mask=x7fe0fc00\n# C6.2.214 LSLV page C6-1656 line 98305 MATCH x1ac02000/mask=x7fe0fc00\n# CONSTRUCT x9ac02000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ac02000/mask=xffe0fc00 --status pass\n\n:lsl Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x8 & Rn_GPR64 & Rd_GPR64\n{\n\tshiftval:8 = (Rm_GPR64 & 0x3f);\n\ttmp_1:8 = Rn_GPR64 << shiftval;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.158 LSL (immediate) page C6-784 line 45779 KEEPWITH\n\nubfiz_lsb: \"#\"^imm is ImmR [ imm = 32 - ImmR; ] { export *[const]:4 imm; }\nubfiz_width: \"#\"^imm is ImmS [ imm = ImmS + 1; ] { export *[const]:4 imm; }\nubfiz_lsb64: \"#\"^imm is ImmR [ imm = 64 - ImmR; ] { export *[const]:4 imm; }\nubfx_width: \"#\"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:4 imm; }\n\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00\n# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00\n# CONSTRUCT x53000012/mask=xffe0801e MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x53000012/mask=xffe0801e --status pass\n# Alias for ubfm where imms+1=immr and imms != '011111'\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:lsl Rd_GPR32, Rn_GPR32, LSB_bitfield32_imm_shift\nis ImmR=ImmS+1 & ImmS_ne_1f=1 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=1 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & LSB_bitfield32_imm_shift & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp:4 = Rn_GPR32 << LSB_bitfield32_imm_shift;\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT xd3400022/mask=xffc0002e MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst xd3400022/mask=xffc0002e --status pass\n# Alias for ubfm where imms+1=immr and imms != '111111'\n\n:lsl Rd_GPR64, Rn_GPR64, LSB_bitfield64_imm_shift\nis ImmR=ImmS+1 & ImmS_ne_3f=1 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=1 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & LSB_bitfield64_imm_shift & Rn_GPR64 & Rd_GPR64\n{\n\tRd_GPR64 = Rn_GPR64 << LSB_bitfield64_imm_shift;\n}\n\n# C6.2.215 LSR (register) page C6-1658 line 98396 MATCH x1ac02400/mask=x7fe0fc00\n# C6.2.217 LSRV page C6-1662 line 98580 MATCH x1ac02400/mask=x7fe0fc00\n# CONSTRUCT x1ac02400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac02400/mask=xffe0fc00 --status pass\n\n:lsr Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x9 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tshiftval:8 = zext(Rm_GPR32 & 0x1f);\n\ttmp_1:4 = Rn_GPR32 >> shiftval;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.215 LSR (register) page C6-1658 line 98396 MATCH x1ac02400/mask=x7fe0fc00\n# C6.2.217 LSRV page C6-1662 line 98580 MATCH x1ac02400/mask=x7fe0fc00\n# CONSTRUCT x9ac02400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ac02400/mask=xffe0fc00 --status pass\n\n:lsr Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x9 & Rn_GPR64 & Rd_GPR64\n{\n\tshiftval:8 = Rm_GPR64 & 0x3f;\n\ttmp_1:8 = Rn_GPR64 >> shiftval;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT x53007c00/mask=xffe0fc1a MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst x53007c00/mask=xffe0fc1a --status pass\n# Alias for ubfm where imms=='011111'\n# imms is MAX_INT5, so it will never be less than immr. Note that immr is limited to [0,31]\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:lsr Rd_GPR32, Rn_GPR32, ImmRConst32\nis ImmS=0x1f & ImmS_ne_1f=0 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = ImmRConst32;\n\ttmp_1:4 = Rn_GPR32 >> tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT xd340fc00/mask=xffc0fc2a MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst xd340fc00/mask=xffc0fc2a --status pass\n# Alias for ubfm where imms=='111111'\n# imms is MAX_INT6, so it will never be less than immr.\n\n:lsr Rd_GPR64, Rn_GPR64, ImmRConst64\nis ImmS=0x3f & ImmS_ne_3f=0 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = ImmRConst64;\n\ttmp_1:8 = Rn_GPR64 >> tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000\n# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00\n# CONSTRUCT x1b000000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1b000000/mask=xffe08000 --status pass\n\n:madd Rd_GPR32, Rn_GPR32, Rm_GPR32, Ra_GPR32\nis sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Rn_GPR32 * Rm_GPR32;\n\taddflags(Ra_GPR32, tmp_2);\n\ttmp_1:4 = Ra_GPR32 + tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000\n# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00\n# CONSTRUCT x9b000000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9b000000/mask=xffe08000 --status pass\n\n:madd Rd_GPR64, Rn_GPR64, Rm_GPR64, Ra_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = Rn_GPR64 * Rm_GPR64;\n\ttmp_1:8 = Ra_GPR64 + tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00\n# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000\n# CONSTRUCT x9b00fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9b00fc00/mask=xffe0fc00 --status pass\n\n:mneg Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = Rn_GPR64 * Rm_GPR64;\n\ttmp_1:8 = -tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00\n# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000\n# CONSTRUCT x1b00fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1b00fc00/mask=xffe0fc00 --status pass\n\n:mneg Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Rn_GPR32 * Rm_GPR32;\n\ttmp_1:4 = -tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# CONSTRUCT x11000000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x11000000/mask=xfffffc00 --status pass\n\n:mov Rd_GPR32xsp, Rn_GPR32xsp\nis sf=0 & b_30=0 & S=0 & b_2428=0x011 & (aa_Xn=31 | aa_Xd=31) & shift=0 & imm12=0 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp\n{\n\tRd_GPR64xsp = zext(Rn_GPR32xsp);\n}\n\n# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00\n# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000\n# CONSTRUCT x91000000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x91000000/mask=xfffffc00 --status pass\n\n:mov Rd_GPR64xsp, Rn_GPR64xsp\nis sf=1 & b_30=0 & S=0 & b_2428=0x11 & (aa_Xn=31 | aa_Xd=31) & shift=0 & imm12=0 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\tRd_GPR64xsp = Rn_GPR64xsp;\n}\n\n# C6.2.166 MOV (inverted wide immediate) page C6-793 line 46366 KEEPWITH\n\nFullImm_movz32_imm: \"#\"^val is imm16 & aa_hw=0 [ val = (imm16 << 0) & 0xffffffff; ] { export *[const]:8 val; }\nFullImm_movz32_imm: \"#\"^val is imm16 & aa_hw=1 [ val = (imm16 << 16) & 0xffffffff; ] { export *[const]:8 val; }\n\nFullImm_movz64_imm: \"#\"^val is imm16 & aa_hw [ val = imm16 << (aa_hw * 16); ] { export *[const]:8 val; }\n\nFullImm_movn32_imm: \"#\"^val is imm16 & aa_hw=0 [ val = ~(imm16 << 0) & 0xffffffff; ] { export *[const]:8 val; }\nFullImm_movn32_imm: \"#\"^val is imm16 & aa_hw=1 [ val = ~(imm16 << 16) & 0xffffffff; ] { export *[const]:8 val; }\n\nFullImm_movn64_imm: \"#\"^val is imm16 & aa_hw [ val = ~(imm16 << (aa_hw * 16)); ] { export *[const]:8 val; }\n\nFullImm_movk32_mask: mask is aa_hw [ mask = (~(0xffff << (aa_hw * 16))) & 0xffffffff; ] { export *[const]:4 mask; }\nFullImm_movk32_shift: tmp is imm16 & aa_hw [ tmp = (imm16 << (aa_hw * 16)) & 0xffffffff; ] { export *[const]:4 tmp; }\nFullImm_movk32_imm: \"#\"^imm16 is imm16 & aa_hw=0 { export *[const]:4 imm16; }\nFullImm_movk32_imm: \"#\"^imm16, \"LSL #16\" is imm16 & aa_hw=1 & FullImm_movk32_shift { export FullImm_movk32_shift; }\n\nFullImm_movk64_mask: mask is aa_hw [ mask = ~(0xffff << (aa_hw * 16)); ] { export *[const]:8 mask; }\nFullImm_movk64_shift: tmp is imm16 & aa_hw [ tmp = (imm16 << (aa_hw * 16)); ] { export *[const]:8 tmp; }\nFullImm_movk64_imm: \"#\"^imm16 is imm16 & aa_hw=0 { export *[const]:8 imm16; }\nFullImm_movk64_imm: \"#\"^imm16, \"LSL #16\" is imm16 & aa_hw=1 & FullImm_movk64_shift { export FullImm_movk64_shift; }\nFullImm_movk64_imm: \"#\"^imm16, \"LSL #32\" is imm16 & aa_hw=2 & FullImm_movk64_shift { export FullImm_movk64_shift; }\nFullImm_movk64_imm: \"#\"^imm16, \"LSL #48\" is imm16 & aa_hw=3 & FullImm_movk64_shift { export FullImm_movk64_shift; }\n\n# C6.2.221 MOV (inverted wide immediate) page C6-1669 line 98943 MATCH x12800000/mask=x7f800000\n# C6.2.226 MOVN page C6-1679 line 99388 MATCH x12800000/mask=x7f800000\n# CONSTRUCT x12800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x12800000/mask=xff800000 --status pass\n\n:mov Rd_GPR32, FullImm_movn32_imm\nis sf=0 & opc=0 & b_2428=0x12 & b_2323=1 & FullImm_movn32_imm & Rd_GPR32 & Rd_GPR64\n{\n\t# Special case MOVN\n\tRd_GPR64 = FullImm_movn32_imm;\n}\n\n# C6.2.221 MOV (inverted wide immediate) page C6-1669 line 98943 MATCH x12800000/mask=x7f800000\n# C6.2.226 MOVN page C6-1679 line 99388 MATCH x12800000/mask=x7f800000\n# CONSTRUCT x92800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x92800000/mask=xff800000 --status pass\n\n:mov Rd_GPR64, FullImm_movn64_imm\nis sf=1 & opc=0 & b_2428=0x12 & b_2323=1 & FullImm_movn64_imm & Rd_GPR64\n{\n\t# Special case MOVN\n\tRd_GPR64 = FullImm_movn64_imm;\n}\n\n# C6.2.222 MOV (wide immediate) page C6-1671 line 99035 MATCH x52800000/mask=x7f800000\n# C6.2.227 MOVZ page C6-1681 line 99489 MATCH x52800000/mask=x7f800000\n# CONSTRUCT x52800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x52800000/mask=xff800000 --status pass\n\n:mov Rd_GPR32, FullImm_movz32_imm\nis sf=0 & opc=2 & b_2428=0x12 & b_2323=1 & FullImm_movz32_imm & Rd_GPR32 & Rd_GPR64\n{\n\tRd_GPR64 = FullImm_movz32_imm;\n}\n\n# C6.2.222 MOV (wide immediate) page C6-1671 line 99035 MATCH x52800000/mask=x7f800000\n# C6.2.227 MOVZ page C6-1681 line 99489 MATCH x52800000/mask=x7f800000\n# CONSTRUCT xd2800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd2800000/mask=xff800000 --status pass\n\n:mov Rd_GPR64, FullImm_movz64_imm\nis sf=1 & opc=2 & b_2428=0x12 & b_2323=1 & FullImm_movz64_imm & Rd_GPR64\n{\n\tRd_GPR64 = FullImm_movz64_imm;\n}\n\n# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0\n# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000\n# CONSTRUCT x320003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x320003e0/mask=xffe0ffe0 --status pass\n\n:mov Rd_GPR32wsp, DecodeWMask32\nis sf=0 & opc=1 & b_2428=0x12 & b_2223=0 & N=0 & imm6=0 & DecodeWMask32 & aa_Xn=31 & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\t# special case ORR\n\ttmp_1:4 = DecodeWMask32;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0\n# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000\n# CONSTRUCT xb20003e0/mask=xffc0ffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb20003e0/mask=xffc0ffe0 --status pass\n\n:mov Rd_GPR64xsp, DecodeWMask64\nis sf=1 & opc=1 & b_2428=0x12 & b_2223=0 & imm6=0 & DecodeWMask64 & aa_Xn=31 & Rd_GPR64xsp\n{\n\t# special case of ORR\n\ttmp_1:8 = DecodeWMask64;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0\n# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000\n# CONSTRUCT x2a0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x2a0003e0/mask=xff2003e0 --status pass\n\n:mov Rd_GPR32, RegShift32Log\nis b_31=0 & b_2430=0b0101010 & b_21=0 & b_0509=0b11111 & RegShift32Log & Rd_GPR32 & Rd_GPR64\n{\n\t# special case ORR\n\ttmp_1:4 = RegShift32Log;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0\n# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000\n# CONSTRUCT xaa0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xaa0003e0/mask=xff2003e0 --status pass\n\n:mov Rd_GPR64, RegShift64Log\nis b_31=1 & b_2430=0b0101010 & b_21=0 & b_0509=0b11111 & RegShift64Log & Rd_GPR64\n{\n\t# special case of ORR\n\ttmp_1:8 = RegShift64Log;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.225 MOVK page C6-1677 line 99301 MATCH x72800000/mask=x7f800000\n# CONSTRUCT x72800000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x72800000/mask=xff800000 --status pass\n\n:movk Rd_GPR32, FullImm_movk32_imm\nis sf=0 & opc=3 & b_2428=0x12 & b_2323=1 & FullImm_movk32_imm & Rd_GPR32 & Rd_GPR64 & FullImm_movk32_mask\n{\n\tlocal tmp:4 = Rd_GPR32 & FullImm_movk32_mask;\n\ttmp = tmp | FullImm_movk32_imm;\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.225 MOVK page C6-1677 line 99301 MATCH x72800000/mask=x7f800000\n# CONSTRUCT xf2800000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf2800000/mask=xff800000 --status pass\n\n:movk Rd_GPR64, FullImm_movk64_imm\nis sf=1 & opc=3 & b_2428=0x12 & b_2323=1 & FullImm_movk64_imm & Rd_GPR64 & FullImm_movk64_mask\n{\n\tRd_GPR64 = Rd_GPR64 & FullImm_movk64_mask;\n\tRd_GPR64 = Rd_GPR64 | FullImm_movk64_imm;\n}\n\n# C6.2.173 MRS page C6-802 line 46877 MATCH KEEPWITH\n\nwith : (l=0 | l=1) {\nCopReg: spsr_el1 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el1 { export spsr_el1; }\nCopReg: elr_el1 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el1 { export elr_el1; }\nCopReg: sp_el0 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el0 { export sp_el0; }\nCopReg: spsel is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=2 & Op2_uimm3=0 & spsel { export spsel; }\nCopReg: daif is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=1 & daif { export daif; }\nCopReg: currentel is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=2 & Op2_uimm3=2 & currentel { export currentel; }\nCopReg: nzcv is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=0 & nzcv { export nzcv; }\nCopReg: fpcr is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=4 & Op2_uimm3=0 & fpcr { export fpcr; }\nCopReg: fpsr is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=4 & Op2_uimm3=1 & fpsr { export fpsr; }\nCopReg: dspsr_el0 is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=5 & Op2_uimm3=0 & dspsr_el0 { export dspsr_el0; }\nCopReg: dlr_el0 is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=5 & Op2_uimm3=1 & dlr_el0 { export dlr_el0; }\nCopReg: spsr_el2 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el2 { export spsr_el2; }\nCopReg: elr_el2 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el2 { export elr_el2; }\nCopReg: sp_el1 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el1 { export sp_el1; }\nCopReg: spsr_irq is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=0 & spsr_irq { export spsr_irq; }\nCopReg: spsr_abt is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=1 & spsr_abt { export spsr_abt; }\nCopReg: spsr_und is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=2 & spsr_und { export spsr_und; }\nCopReg: spsr_fiq is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=3 & spsr_fiq { export spsr_fiq; }\nCopReg: spsr_el3 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el3 { export spsr_el3; }\nCopReg: elr_el3 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el3 { export elr_el3; }\nCopReg: sp_el2 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el2 { export sp_el2; }\n# CopReg: spsr_svc is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_svc { export spsr_svc; }\n# CopReg: spsr_hyp is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_hyp { export spsr_hyp; }\n\nCopReg: midr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=0 & midr_el1 { export midr_el1; }\nCopReg: mpidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=5 & mpidr_el1 { export mpidr_el1; }\nCopReg: revidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=6 & revidr_el1 { export revidr_el1; }\nCopReg: id_dfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=2 & id_dfr0_el1 { export id_dfr0_el1; }\nCopReg: id_pfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=0 & id_pfr0_el1 { export id_pfr0_el1; }\nCopReg: id_pfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=1 & id_pfr1_el1 { export id_pfr1_el1; }\nCopReg: id_afr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=3 & id_afr0_el1 { export id_afr0_el1; }\nCopReg: id_mmfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=4 & id_mmfr0_el1 { export id_mmfr0_el1; }\nCopReg: id_mmfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=5 & id_mmfr1_el1 { export id_mmfr1_el1; }\nCopReg: id_mmfr2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=6 & id_mmfr2_el1 { export id_mmfr2_el1; }\nCopReg: id_mmfr3_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=7 & id_mmfr3_el1 { export id_mmfr3_el1; }\nCopReg: id_isar0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=0 & id_isar0_el1 { export id_isar0_el1; }\nCopReg: id_isar1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=1 & id_isar1_el1 { export id_isar1_el1; }\nCopReg: id_isar2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=2 & id_isar2_el1 { export id_isar2_el1; }\nCopReg: id_isar3_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=3 & id_isar3_el1 { export id_isar3_el1; }\nCopReg: id_isar4_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=4 & id_isar4_el1 { export id_isar4_el1; }\nCopReg: id_isar5_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=5 & id_isar5_el1 { export id_isar5_el1; }\nCopReg: mvfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=0 & mvfr0_el1 { export mvfr0_el1; }\nCopReg: mvfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=1 & mvfr1_el1 { export mvfr1_el1; }\nCopReg: mvfr2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=2 & mvfr2_el1 { export mvfr2_el1; }\nCopReg: ccsidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=0 & ccsidr_el1 { export ccsidr_el1; }\nCopReg: id_aa64pfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=0 & id_aa64pfr0_el1 { export id_aa64pfr0_el1; }\nCopReg: id_aa64pfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=1 & id_aa64pfr1_el1 { export id_aa64pfr1_el1; }\nCopReg: id_aa64dfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=0 & id_aa64dfr0_el1 { export id_aa64dfr0_el1; }\nCopReg: id_aa64dfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=1 & id_aa64dfr1_el1 { export id_aa64dfr1_el1; }\nCopReg: id_aa64isar0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=0 & id_aa64isar0_el1 { export id_aa64isar0_el1; }\nCopReg: id_aa64isar1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=1 & id_aa64isar1_el1 { export id_aa64isar1_el1; }\nCopReg: id_aa64mmfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=0 & id_aa64mmfr0_el1 { export id_aa64mmfr0_el1; }\nCopReg: id_aa64mmfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=1 & id_aa64mmfr1_el1 { export id_aa64mmfr1_el1; }\nCopReg: id_aa64afr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=4 & id_aa64afr0_el1 { export id_aa64afr0_el1; }\nCopReg: id_aa64afr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=5 & id_aa64afr1_el1 { export id_aa64afr1_el1; }\nCopReg: clidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=1 & clidr_el1 { export clidr_el1; }\nCopReg: aidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=7 & aidr_el1 { export aidr_el1; }\nCopReg: csselr_el1 is Op0=3 & Op1_uimm3=2 & CRn=0 & CRm=0 & Op2_uimm3=0 & csselr_el1 { export csselr_el1; }\nCopReg: ctr_el0 is Op0=3 & Op1_uimm3=3 & CRn=0 & CRm=0 & Op2_uimm3=1 & ctr_el0 { export ctr_el0; }\nCopReg: dczid_el0 is Op0=3 & Op1_uimm3=3 & CRn=0 & CRm=0 & Op2_uimm3=7 & dczid_el0 { export dczid_el0; }\nCopReg: vpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=0 & CRm=0 & Op2_uimm3=0 & vpidr_el2 { export vpidr_el2; }\nCopReg: vmpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=0 & CRm=0 & Op2_uimm3=5 & vmpidr_el2 { export vmpidr_el2; }\nCopReg: sctlr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el1 { export sctlr_el1; }\nCopReg: actlr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el1 { export actlr_el1; }\nCopReg: cpacr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=2 & cpacr_el1 { export cpacr_el1; }\nCopReg: sctlr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el2 { export sctlr_el2; }\nCopReg: actlr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el2 { export actlr_el2; }\nCopReg: hcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=0 & hcr_el2 { export hcr_el2; }\nCopReg: mdcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=1 & mdcr_el2 { export mdcr_el2; }\nCopReg: cptr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=2 & cptr_el2 { export cptr_el2; }\nCopReg: hstr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=3 & hstr_el2 { export hstr_el2; }\nCopReg: hacr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=7 & hacr_el2 { export hacr_el2; }\nCopReg: sctlr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el3 { export sctlr_el3; }\nCopReg: actlr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el3 { export actlr_el3; }\nCopReg: scr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=0 & scr_el3 { export scr_el3; }\nCopReg: cptr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=2 & cptr_el3 { export cptr_el3; }\nCopReg: mdcr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=3 & Op2_uimm3=1 & mdcr_el3 { export mdcr_el3; }\nCopReg: ttbr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el1 { export ttbr0_el1; }\nCopReg: ttbr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=1 & ttbr1_el1 { export ttbr1_el1; }\nCopReg: ttbr0_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el2 { export ttbr0_el2; }\nCopReg: ttbr0_el3 is Op0=3 & Op1_uimm3=6 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el3 { export ttbr0_el3; }\nCopReg: vttbr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=1 & Op2_uimm3=0 & vttbr_el2 { export vttbr_el2; }\nCopReg: tcr_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el1 { export tcr_el1; }\nCopReg: tcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el2 { export tcr_el2; }\nCopReg: tcr_el3 is Op0=3 & Op1_uimm3=6 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el3 { export tcr_el3; }\nCopReg: vtcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=1 & Op2_uimm3=2 & vtcr_el2 { export vtcr_el2; }\nCopReg: afsr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el1 { export afsr0_el1; }\nCopReg: afsr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el1 { export afsr1_el1; }\nCopReg: afsr0_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el2 { export afsr0_el2; }\nCopReg: afsr1_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el2 { export afsr1_el2; }\nCopReg: afsr0_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el3 { export afsr0_el3; }\nCopReg: afsr1_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el3 { export afsr1_el3; }\nCopReg: esr_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el1 { export esr_el1; }\nCopReg: esr_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el2 { export esr_el2; }\nCopReg: esr_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el3 { export esr_el3; }\nCopReg: fpexc32_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=3 & Op2_uimm3=0 & fpexc32_el2 { export fpexc32_el2; }\nCopReg: far_el1 is Op0=3 & Op1_uimm3=0 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el1 { export far_el1; }\nCopReg: far_el2 is Op0=3 & Op1_uimm3=4 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el2 { export far_el2; }\nCopReg: far_el3 is Op0=3 & Op1_uimm3=6 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el3 { export far_el3; }\nCopReg: hpfar_el2 is Op0=3 & Op1_uimm3=4 & CRn=6 & CRm=0 & Op2_uimm3=4 & hpfar_el2 { export hpfar_el2; }\nCopReg: par_el1 is Op0=3 & Op1_uimm3=0 & CRn=7 & CRm=4 & Op2_uimm3=0 & par_el1 { export par_el1; }\nCopReg: pmintenset_el1 is Op0=3 & Op1_uimm3=0 & CRn=9 & CRm=14 & Op2_uimm3=1 & pmintenset_el1 { export pmintenset_el1; }\nCopReg: pmintenclr_el1 is Op0=3 & Op1_uimm3=0 & CRn=9 & CRm=14 & Op2_uimm3=2 & pmintenclr_el1 { export pmintenclr_el1; }\nCopReg: pmcr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=0 & pmcr_el0 { export pmcr_el0; }\nCopReg: pmcntenset_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=1 & pmcntenset_el0 { export pmcntenset_el0; }\nCopReg: pmcntenclr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=2 & pmcntenclr_el0 { export pmcntenclr_el0; }\nCopReg: pmovsclr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=3 & pmovsclr_el0 { export pmovsclr_el0; }\nCopReg: pmswinc_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=4 & pmswinc_el0 { export pmswinc_el0; }\nCopReg: pmselr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=5 & pmselr_el0 { export pmselr_el0; }\nCopReg: pmceid0_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=6 & pmceid0_el0 { export pmceid0_el0; }\nCopReg: pmceid1_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=7 & pmceid1_el0 { export pmceid1_el0; }\nCopReg: pmccntr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=0 & pmccntr_el0 { export pmccntr_el0; }\nCopReg: pmxevtyper_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=1 & pmxevtyper_el0 { export pmxevtyper_el0; }\nCopReg: pmxevcntr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=2 & pmxevcntr_el0 { export pmxevcntr_el0; }\nCopReg: pmuserenr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=14 & Op2_uimm3=0 & pmuserenr_el0 { export pmuserenr_el0; }\nCopReg: pmovsset_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=14 & Op2_uimm3=3 & pmovsset_el0 { export pmovsset_el0; }\nCopReg: pmevcntr0_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=0 & pmevcntr0_el0 { export pmevcntr0_el0; }\nCopReg: pmevcntr1_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=1 & pmevcntr1_el0 { export pmevcntr1_el0; }\nCopReg: pmevcntr2_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=2 & pmevcntr2_el0 { export pmevcntr2_el0; }\nCopReg: pmevcntr3_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=3 & pmevcntr3_el0 { export pmevcntr3_el0; }\nCopReg: pmevcntr4_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=4 & pmevcntr4_el0 { export pmevcntr4_el0; }\nCopReg: pmevcntr5_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=5 & pmevcntr5_el0 { export pmevcntr5_el0; }\nCopReg: pmevcntr6_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=6 & pmevcntr6_el0 { export pmevcntr6_el0; }\nCopReg: pmevcntr7_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=7 & pmevcntr7_el0 { export pmevcntr7_el0; }\nCopReg: pmevcntr8_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=0 & pmevcntr8_el0 { export pmevcntr8_el0; }\nCopReg: pmevcntr9_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=1 & pmevcntr9_el0 { export pmevcntr9_el0; }\nCopReg: pmevcntr10_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=2 & pmevcntr10_el0 { export pmevcntr10_el0; }\nCopReg: pmevcntr11_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=3 & pmevcntr11_el0 { export pmevcntr11_el0; }\nCopReg: pmevcntr12_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=4 & pmevcntr12_el0 { export pmevcntr12_el0; }\nCopReg: pmevcntr13_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=5 & pmevcntr13_el0 { export pmevcntr13_el0; }\nCopReg: pmevcntr14_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=6 & pmevcntr14_el0 { export pmevcntr14_el0; }\nCopReg: pmevcntr15_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=7 & pmevcntr15_el0 { export pmevcntr15_el0; }\nCopReg: pmevcntr16_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=0 & pmevcntr16_el0 { export pmevcntr16_el0; }\nCopReg: pmevcntr17_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=1 & pmevcntr17_el0 { export pmevcntr17_el0; }\nCopReg: pmevcntr18_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=2 & pmevcntr18_el0 { export pmevcntr18_el0; }\nCopReg: pmevcntr19_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=3 & pmevcntr19_el0 { export pmevcntr19_el0; }\nCopReg: pmevcntr20_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=4 & pmevcntr20_el0 { export pmevcntr20_el0; }\nCopReg: pmevcntr21_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=5 & pmevcntr21_el0 { export pmevcntr21_el0; }\nCopReg: pmevcntr22_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=6 & pmevcntr22_el0 { export pmevcntr22_el0; }\nCopReg: pmevcntr23_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=7 & pmevcntr23_el0 { export pmevcntr23_el0; }\nCopReg: pmevcntr24_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=0 & pmevcntr24_el0 { export pmevcntr24_el0; }\nCopReg: pmevcntr25_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=1 & pmevcntr25_el0 { export pmevcntr25_el0; }\nCopReg: pmevcntr26_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=2 & pmevcntr26_el0 { export pmevcntr26_el0; }\nCopReg: pmevcntr27_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=3 & pmevcntr27_el0 { export pmevcntr27_el0; }\nCopReg: pmevcntr28_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=4 & pmevcntr28_el0 { export pmevcntr28_el0; }\nCopReg: pmevcntr29_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=5 & pmevcntr29_el0 { export pmevcntr29_el0; }\nCopReg: pmevcntr30_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=6 & pmevcntr30_el0 { export pmevcntr30_el0; }\nCopReg: pmevtyper0_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=0 & pmevtyper0_el0 { export pmevtyper0_el0; }\nCopReg: pmevtyper1_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=1 & pmevtyper1_el0 { export pmevtyper1_el0; }\nCopReg: pmevtyper2_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=2 & pmevtyper2_el0 { export pmevtyper2_el0; }\nCopReg: pmevtyper3_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=3 & pmevtyper3_el0 { export pmevtyper3_el0; }\nCopReg: pmevtyper4_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=4 & pmevtyper4_el0 { export pmevtyper4_el0; }\nCopReg: pmevtyper5_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=5 & pmevtyper5_el0 { export pmevtyper5_el0; }\nCopReg: pmevtyper6_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=6 & pmevtyper6_el0 { export pmevtyper6_el0; }\nCopReg: pmevtyper7_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=7 & pmevtyper7_el0 { export pmevtyper7_el0; }\nCopReg: pmevtyper8_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=0 & pmevtyper8_el0 { export pmevtyper8_el0; }\nCopReg: pmevtyper9_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=1 & pmevtyper9_el0 { export pmevtyper9_el0; }\nCopReg: pmevtyper10_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=2 & pmevtyper10_el0 { export pmevtyper10_el0; }\nCopReg: pmevtyper11_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=3 & pmevtyper11_el0 { export pmevtyper11_el0; }\nCopReg: pmevtyper12_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=4 & pmevtyper12_el0 { export pmevtyper12_el0; }\nCopReg: pmevtyper13_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=5 & pmevtyper13_el0 { export pmevtyper13_el0; }\nCopReg: pmevtyper14_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=6 & pmevtyper14_el0 { export pmevtyper14_el0; }\nCopReg: pmevtyper15_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=7 & pmevtyper15_el0 { export pmevtyper15_el0; }\nCopReg: pmevtyper16_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=0 & pmevtyper16_el0 { export pmevtyper16_el0; }\nCopReg: pmevtyper17_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=1 & pmevtyper17_el0 { export pmevtyper17_el0; }\nCopReg: pmevtyper18_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=2 & pmevtyper18_el0 { export pmevtyper18_el0; }\nCopReg: pmevtyper19_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=3 & pmevtyper19_el0 { export pmevtyper19_el0; }\nCopReg: pmevtyper20_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=4 & pmevtyper20_el0 { export pmevtyper20_el0; }\nCopReg: pmevtyper21_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=5 & pmevtyper21_el0 { export pmevtyper21_el0; }\nCopReg: pmevtyper22_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=6 & pmevtyper22_el0 { export pmevtyper22_el0; }\nCopReg: pmevtyper23_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=7 & pmevtyper23_el0 { export pmevtyper23_el0; }\nCopReg: pmevtyper24_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=0 & pmevtyper24_el0 { export pmevtyper24_el0; }\nCopReg: pmevtyper25_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=1 & pmevtyper25_el0 { export pmevtyper25_el0; }\nCopReg: pmevtyper26_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=2 & pmevtyper26_el0 { export pmevtyper26_el0; }\nCopReg: pmevtyper27_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=3 & pmevtyper27_el0 { export pmevtyper27_el0; }\nCopReg: pmevtyper28_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=4 & pmevtyper28_el0 { export pmevtyper28_el0; }\nCopReg: pmevtyper29_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=5 & pmevtyper29_el0 { export pmevtyper29_el0; }\nCopReg: pmevtyper30_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=6 & pmevtyper30_el0 { export pmevtyper30_el0; }\nCopReg: pmccfiltr_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=7 & pmccfiltr_el0 { export pmccfiltr_el0; }\nCopReg: mair_el1 is Op0=3 & Op1_uimm3=0 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el1 { export mair_el1; }\nCopReg: mair_el2 is Op0=3 & Op1_uimm3=4 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el2 { export mair_el2; }\nCopReg: mair_el3 is Op0=3 & Op1_uimm3=6 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el3 { export mair_el3; }\nCopReg: amair_el1 is Op0=3 & Op1_uimm3=0 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el1 { export amair_el1; }\nCopReg: amair_el2 is Op0=3 & Op1_uimm3=4 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el2 { export amair_el2; }\nCopReg: amair_el3 is Op0=3 & Op1_uimm3=6 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el3 { export amair_el3; }\nCopReg: vbar_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el1 { export vbar_el1; }\nCopReg: vbar_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el2 { export vbar_el2; }\nCopReg: vbar_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el3 { export vbar_el3; }\nCopReg: rvbar_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el1 { export rvbar_el1; }\nCopReg: rvbar_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el2 { export rvbar_el2; }\nCopReg: rvbar_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el3 { export rvbar_el3; }\nCopReg: rmr_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el1 { export rmr_el1; }\nCopReg: rmr_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el2 { export rmr_el2; }\nCopReg: rmr_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el3 { export rmr_el3; }\nCopReg: isr_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=1 & Op2_uimm3=0 & isr_el1 { export isr_el1; }\nCopReg: contextidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=13 & CRm=0 & Op2_uimm3=1 & contextidr_el1 { export contextidr_el1; }\nCopReg: tpidr_el0 is Op0=3 & Op1_uimm3=3 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el0 { export tpidr_el0; }\nCopReg: tpidrro_el0 is Op0=3 & Op1_uimm3=3 & CRn=13 & CRm=0 & Op2_uimm3=3 & tpidrro_el0 { export tpidrro_el0; }\nCopReg: tpidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=13 & CRm=0 & Op2_uimm3=4 & tpidr_el1 { export tpidr_el1; }\nCopReg: tpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el2 { export tpidr_el2; }\nCopReg: tpidr_el3 is Op0=3 & Op1_uimm3=6 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el3 { export tpidr_el3; }\nCopReg: teecr32_el1 is Op0=2 & Op1_uimm3=2 & CRn=0 & CRm=0 & Op2_uimm3=0 & teecr32_el1 { export teecr32_el1; }\nCopReg: cntfrq_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=0 & cntfrq_el0 { export cntfrq_el0; }\nCopReg: cntpct_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=1 & cntpct_el0 { export cntpct_el0; }\nCopReg: cntvct_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=2 & cntvct_el0 { export cntvct_el0; }\nCopReg: cntvoff_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=0 & Op2_uimm3=3 & cntvoff_el2 { export cntvoff_el2; }\nCopReg: cntkctl_el1 is Op0=3 & Op1_uimm3=0 & CRn=14 & CRm=1 & Op2_uimm3=0 & cntkctl_el1 { export cntkctl_el1; }\nCopReg: cnthctl_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=1 & Op2_uimm3=0 & cnthctl_el2 { export cnthctl_el2; }\nCopReg: cntp_tval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=0 & cntp_tval_el0 { export cntp_tval_el0; }\nCopReg: cntp_ctl_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=1 & cntp_ctl_el0 { export cntp_ctl_el0; }\nCopReg: cntp_cval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=2 & cntp_cval_el0 { export cntp_cval_el0; }\nCopReg: cntv_tval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=0 & cntv_tval_el0 { export cntv_tval_el0; }\nCopReg: cntv_ctl_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=1 & cntv_ctl_el0 { export cntv_ctl_el0; }\nCopReg: cntv_cval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=2 & cntv_cval_el0 { export cntv_cval_el0; }\nCopReg: cnthp_tval_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=0 & cnthp_tval_el2 { export cnthp_tval_el2; }\nCopReg: cnthp_ctl_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=1 & cnthp_ctl_el2 { export cnthp_ctl_el2; }\nCopReg: cnthp_cval_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=2 & cnthp_cval_el2 { export cnthp_cval_el2; }\nCopReg: cntps_tval_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=0 & cntps_tval_el1 { export cntps_tval_el1; }\nCopReg: cntps_ctl_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=1 & cntps_ctl_el1 { export cntps_ctl_el1; }\nCopReg: cntps_cval_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=2 & cntps_cval_el1 { export cntps_cval_el1; }\nCopReg: dacr32_el2 is Op0=3 & Op1_uimm3=4 & CRn=3 & CRm=0 & Op2_uimm3=0 & dacr32_el2 { export dacr32_el2; }\nCopReg: ifsr32_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=0 & Op2_uimm3=1 & ifsr32_el2 { export ifsr32_el2; }\nCopReg: teehbr32_el1 is Op0=2 & Op1_uimm3=2 & CRn=1 & CRm=0 & Op2_uimm3=0 & teehbr32_el1 { export teehbr32_el1; }\nCopReg: sder32_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=1 & sder32_el3 { export sder32_el3; }\nCopReg: osdtrrx_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=2 & osdtrrx_el1 { export osdtrrx_el1; }\n\nCopReg: mdccint_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=0 & mdccint_el1 { export mdccint_el1; }\nCopReg: mdscr_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=2 & mdscr_el1 { export mdscr_el1; }\nCopReg: osdtrtx_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=2 & osdtrtx_el1 { export osdtrtx_el1; }\nCopReg: oseccr_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=2 & oseccr_el1 { export oseccr_el1; }\nCopReg: dbgbvr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=4 & dbgbvr0_el1 { export dbgbvr0_el1; }\nCopReg: dbgbvr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=4 & dbgbvr1_el1 { export dbgbvr1_el1; }\nCopReg: dbgbvr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=4 & dbgbvr2_el1 { export dbgbvr2_el1; }\nCopReg: dbgbvr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=4 & dbgbvr3_el1 { export dbgbvr3_el1; }\nCopReg: dbgbvr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=4 & dbgbvr4_el1 { export dbgbvr4_el1; }\nCopReg: dbgbvr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=4 & dbgbvr5_el1 { export dbgbvr5_el1; }\nCopReg: dbgbvr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=4 & dbgbvr6_el1 { export dbgbvr6_el1; }\nCopReg: dbgbvr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=4 & dbgbvr7_el1 { export dbgbvr7_el1; }\nCopReg: dbgbvr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=4 & dbgbvr8_el1 { export dbgbvr8_el1; }\nCopReg: dbgbvr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=4 & dbgbvr9_el1 { export dbgbvr9_el1; }\nCopReg: dbgbvr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=4 & dbgbvr10_el1 { export dbgbvr10_el1; }\nCopReg: dbgbvr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=4 & dbgbvr11_el1 { export dbgbvr11_el1; }\nCopReg: dbgbvr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=4 & dbgbvr12_el1 { export dbgbvr12_el1; }\nCopReg: dbgbvr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=4 & dbgbvr13_el1 { export dbgbvr13_el1; }\nCopReg: dbgbvr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=4 & dbgbvr14_el1 { export dbgbvr14_el1; }\nCopReg: dbgbvr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=4 & dbgbvr15_el1 { export dbgbvr15_el1; }\nCopReg: dbgbcr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=5 & dbgbcr0_el1 { export dbgbcr0_el1; }\nCopReg: dbgbcr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=5 & dbgbcr1_el1 { export dbgbcr1_el1; }\nCopReg: dbgbcr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=5 & dbgbcr2_el1 { export dbgbcr2_el1; }\nCopReg: dbgbcr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=5 & dbgbcr3_el1 { export dbgbcr3_el1; }\nCopReg: dbgbcr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=5 & dbgbcr4_el1 { export dbgbcr4_el1; }\nCopReg: dbgbcr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=5 & dbgbcr5_el1 { export dbgbcr5_el1; }\nCopReg: dbgbcr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=5 & dbgbcr6_el1 { export dbgbcr6_el1; }\nCopReg: dbgbcr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=5 & dbgbcr7_el1 { export dbgbcr7_el1; }\nCopReg: dbgbcr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=5 & dbgbcr8_el1 { export dbgbcr8_el1; }\nCopReg: dbgbcr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=5 & dbgbcr9_el1 { export dbgbcr9_el1; }\nCopReg: dbgbcr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=5 & dbgbcr10_el1 { export dbgbcr10_el1; }\nCopReg: dbgbcr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=5 & dbgbcr11_el1 { export dbgbcr11_el1; }\nCopReg: dbgbcr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=5 & dbgbcr12_el1 { export dbgbcr12_el1; }\nCopReg: dbgbcr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=5 & dbgbcr13_el1 { export dbgbcr13_el1; }\nCopReg: dbgbcr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=5 & dbgbcr14_el1 { export dbgbcr14_el1; }\nCopReg: dbgbcr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=5 & dbgbcr15_el1 { export dbgbcr15_el1; }\nCopReg: dbgwvr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=6 & dbgwvr0_el1 { export dbgwvr0_el1; }\nCopReg: dbgwvr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=6 & dbgwvr1_el1 { export dbgwvr1_el1; }\nCopReg: dbgwvr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=6 & dbgwvr2_el1 { export dbgwvr2_el1; }\nCopReg: dbgwvr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=6 & dbgwvr3_el1 { export dbgwvr3_el1; }\nCopReg: dbgwvr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=6 & dbgwvr4_el1 { export dbgwvr4_el1; }\nCopReg: dbgwvr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=6 & dbgwvr5_el1 { export dbgwvr5_el1; }\nCopReg: dbgwvr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=6 & dbgwvr6_el1 { export dbgwvr6_el1; }\nCopReg: dbgwvr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=6 & dbgwvr7_el1 { export dbgwvr7_el1; }\nCopReg: dbgwvr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=6 & dbgwvr8_el1 { export dbgwvr8_el1; }\nCopReg: dbgwvr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=6 & dbgwvr9_el1 { export dbgwvr9_el1; }\nCopReg: dbgwvr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=6 & dbgwvr10_el1 { export dbgwvr10_el1; }\nCopReg: dbgwvr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=6 & dbgwvr11_el1 { export dbgwvr11_el1; }\nCopReg: dbgwvr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=6 & dbgwvr12_el1 { export dbgwvr12_el1; }\nCopReg: dbgwvr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=6 & dbgwvr13_el1 { export dbgwvr13_el1; }\nCopReg: dbgwvr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=6 & dbgwvr14_el1 { export dbgwvr14_el1; }\nCopReg: dbgwvr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=6 & dbgwvr15_el1 { export dbgwvr15_el1; }\nCopReg: dbgwcr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=7 & dbgwcr0_el1 { export dbgwcr0_el1; }\nCopReg: dbgwcr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=7 & dbgwcr1_el1 { export dbgwcr1_el1; }\nCopReg: dbgwcr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=7 & dbgwcr2_el1 { export dbgwcr2_el1; }\nCopReg: dbgwcr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=7 & dbgwcr3_el1 { export dbgwcr3_el1; }\nCopReg: dbgwcr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=7 & dbgwcr4_el1 { export dbgwcr4_el1; }\nCopReg: dbgwcr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=7 & dbgwcr5_el1 { export dbgwcr5_el1; }\nCopReg: dbgwcr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=7 & dbgwcr6_el1 { export dbgwcr6_el1; }\nCopReg: dbgwcr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=7 & dbgwcr7_el1 { export dbgwcr7_el1; }\nCopReg: dbgwcr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=7 & dbgwcr8_el1 { export dbgwcr8_el1; }\nCopReg: dbgwcr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=7 & dbgwcr9_el1 { export dbgwcr9_el1; }\nCopReg: dbgwcr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=7 & dbgwcr10_el1 { export dbgwcr10_el1; }\nCopReg: dbgwcr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=7 & dbgwcr11_el1 { export dbgwcr11_el1; }\nCopReg: dbgwcr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=7 & dbgwcr12_el1 { export dbgwcr12_el1; }\nCopReg: dbgwcr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=7 & dbgwcr13_el1 { export dbgwcr13_el1; }\nCopReg: dbgwcr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=7 & dbgwcr14_el1 { export dbgwcr14_el1; }\nCopReg: dbgwcr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=7 & dbgwcr15_el1 { export dbgwcr15_el1; }\nCopReg: mdrar_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=0 & mdrar_el1 { export mdrar_el1; }\nCopReg: oslar_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=4 & oslar_el1 { export oslar_el1; }\nCopReg: oslsr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=1 & Op2_uimm3=4 & oslsr_el1 { export oslsr_el1; }\nCopReg: osdlr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=3 & Op2_uimm3=4 & osdlr_el1 { export osdlr_el1; }\nCopReg: dbgprcr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=4 & Op2_uimm3=4 & dbgprcr_el1 { export dbgprcr_el1; }\nCopReg: dbgclaimset_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=8 & Op2_uimm3=6 & dbgclaimset_el1 { export dbgclaimset_el1; }\nCopReg: dbgclaimclr_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=9 & Op2_uimm3=6 & dbgclaimclr_el1 { export dbgclaimclr_el1; }\nCopReg: dbgauthstatus_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=14 & Op2_uimm3=6 & dbgauthstatus_el1 { export dbgauthstatus_el1; }\nCopReg: mdccsr_el0 is Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=1 & Op2_uimm3=0 & mdccsr_el0 { export mdccsr_el0; }\nCopReg: dbgdtr_el0 is Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=4 & Op2_uimm3=0 & dbgdtr_el0 { export dbgdtr_el0; }\nCopReg: dbgvcr32_el2 is Op0=2 & Op1_uimm3=4 & CRn=0 & CRm=7 & Op2_uimm3=0 & dbgvcr32_el2 { export dbgvcr32_el2; }\n# The SysReg document implies that GMID_EL1 can only be read - the doc only provides pseudocode for read access.\n# However, the register is in this block (without a required value for 'l') because that might not be fully accurate.\nCopReg: gmid_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=4 & gmid_el1 { export gmid_el1; }\nCopReg: ssbs is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=6 & ssbs { export ssbs; }\n} # with : (l=0 | l=1) {\n\nCopReg: dbgdtrrx_el0 is l=0 & Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=5 & Op2_uimm3=0 & dbgdtrrx_el0 { export dbgdtrrx_el0; }\nCopReg: dbgdtrtx_el0 is l=1 & Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=5 & Op2_uimm3=0 & dbgdtrtx_el0 { export dbgdtrtx_el0; }\n\nCopReg: \"sreg(\"^Op0^\", \"^Op1_uimm3^\", c\"^CRn^\", c\"^CRm^\", \"^Op2_uimm3^\")\" is l=1 & Op0 & Op1_uimm3 & CRn & CRm & Op2_uimm3 { tmp:8 = UnkSytemRegRead(Op0:1, Op1_uimm3:1, CRn:1, CRm:1, Op2_uimm3:1); export tmp; }\nCopReg: \"sreg(\"^Op0^\", \"^Op1_uimm3^\", c\"^CRn^\", c\"^CRm^\", \"^Op2_uimm3^\")\" is l=0 & Op0 & Op1_uimm3 & CRn & CRm & Op2_uimm3 & Rt_GPR64 { tmp:8 = UnkSytemRegWrite(Op0:1, Op1_uimm3:1, CRn:1, CRm:1, Op2_uimm3:1, Rt_GPR64); export tmp; }\n\nPState_pstate_op: \"DAIFSet\" is Op1_uimm3=3 & Op2_uimm3=6 & CRm { daif = (CRm << 6) | daif; }\nPState_pstate_op: \"DAIFClr\" is Op1_uimm3=3 & Op2_uimm3=7 & CRm { tmp:8 = CRm; daif = (~(tmp << 6)) & daif; }\nPState_pstate_op: \"PState.UAO\" is Op1_uimm3=0 & Op2_uimm3=3 & CRm { tmp:8 = CRm; uao = tmp & 1; }\nPState_pstate_op: \"PState.PAN\" is Op1_uimm3=0 & Op2_uimm3=4 & CRm { tmp:8 = CRm; pan = tmp & 1; }\nPState_pstate_op: \"PState.SP\" is Op1_uimm3=0 & Op2_uimm3=5 & CRm { tmp:8 = CRm; spsel = tmp & 1; }\nPState_pstate_op: \"PState.TCO\" is Op1_uimm3=3 & Op2_uimm3=4 & CRm { tmp:8 = CRm; tco = tmp & 1; }\nPState_pstate_op: \"PState.ALLINT\" is Op1_uimm3=1 & Op2_uimm3=0 & b_0911=0 & CRm { tmp:8 = CRm; allint = tmp & 1; }\nPState_pstate_op: \"PState.DIT\" is Op1_uimm3=3 & Op2_uimm3=2 & CRm { tmp:8 = CRm; dit = tmp & 1; }\n#PState_pstate_op: \"PState.SVCRSM\" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=1 & b_08 { tmp:8 = b_08; svcrsm = tmp & 1; } # see SMSTART/SMSTOP\n#PState_pstate_op: \"PState.SVCRZA\" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=2 & b_08 { tmp:8 = b_08; svcrza = tmp & 1; } # see SMSTART/SMSTOP\n#PState_pstate_op: \"PState.SVZRMZA\" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=3 & b_08 { tmp:8 = b_08; svcrsmza = tmp & 1; } # see SMSTART/SMSTOP\nPState_pstate_op: \"PState.SSBS\" is Op1_uimm3=3 & Op2_uimm3=1 & CRm { tmp:8 = CRm; ssbs = tmp & 1; }\n\n\n\n# C6.2.228 MRS page C6-1683 line 99588 MATCH xd5300000/mask=xfff00000\n# C6.2.379 TSTART page C6-1979 line 116075 MATCH xd5233060/mask=xffffffe0\n# C6.2.380 TTEST page C6-1981 line 116175 MATCH xd5233160/mask=xffffffe0\n# CONSTRUCT xd5200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd5200000/mask=xffe00000 --status noqemu\n\n:mrs Rt_GPR64, CopReg\nis b_2431=0xd5 & b_2223=0 & l=1 & CopReg & Rt_GPR64\n{\n\tRt_GPR64 = CopReg;\n}\n\n# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f\n# CONSTRUCT xd500401f/mask=xfff8f01f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd500401f/mask=xfff8f01f --status nodest\n\n:msr PState_pstate_op, CRm_uimm4\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & PState_pstate_op & CRn=0x4 & CRm_uimm4 & Rt=0x1f\n{\n}\n\n# CONSTRUCT xd5000000/mask=xffe00000 DID NOT MATCH ANY DOCUMENTED OPCODE\n# AUNIT --inst xd5000000/mask=xffe00000 --status noqemu\n\n:msr CopReg, Rt_GPR64\nis b_2431=0xd5 & b_2223=0 & l=0 & CopReg & Rt_GPR64\n{\n\tCopReg = Rt_GPR64;\n}\n\n# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000\n# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00\n# CONSTRUCT x1b008000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1b008000/mask=xffe08000 --status pass\n\n:msub Rd_GPR32, Rn_GPR32, Rm_GPR32, Ra_GPR32\nis sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Rn_GPR32 * Rm_GPR32;\n\ttmp_1:4 = Ra_GPR32 - tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000\n# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00\n# CONSTRUCT x9b008000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9b008000/mask=xffe08000 --status pass\n\n:msub Rd_GPR64, Rn_GPR64, Rm_GPR64, Ra_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = Rn_GPR64 * Rm_GPR64;\n\ttmp_1:8 = Ra_GPR64 - tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00\n# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000\n# CONSTRUCT x1b007c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1b007c00/mask=xffe0fc00 --status pass\n\n:mul Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Rn_GPR32 * Rm_GPR32;\n\tRd_GPR64 = zext(tmp_2);\n}\n\n# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00\n# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000\n# CONSTRUCT x9b007c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9b007c00/mask=xffe0fc00 --status pass\n\n:mul Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = Rn_GPR64 * Rm_GPR64;\n\tRd_GPR64 = tmp_2;\n}\n\n# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0\n# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000\n# CONSTRUCT x2a2003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x2a2003e0/mask=xff2003e0 --status pass\n\n:mvn Rd_GPR32, RegShift32Log\nis sf=0 & opc=1 & b_2428=0xa & N=1 & RegShift32Log & Rn=0x1f & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_1:4 = ~RegShift32Log;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0\n# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000\n# CONSTRUCT xaa2003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xaa2003e0/mask=xff2003e0 --status pass\n\n:mvn Rd_GPR64, RegShift64Log\nis sf=1 & opc=1 & b_2428=0xa & N=1 & Rm_GPR64 & RegShift64Log & Rn=0x1f & Rd_GPR64\n{\n\ttmp_1:8 = ~RegShift64Log;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0\n# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000\n# CONSTRUCT x4b0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x4b0003e0/mask=xff2003e0 --status pass\n\n:neg Rd_GPR32, RegShift32\nis sf=0 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift32 & Rn=0x1f & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32;\n\ttmp_1:4 = - tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0\n# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000\n# CONSTRUCT xcb0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xcb0003e0/mask=xff2003e0 --status pass\n\n:neg Rd_GPR64, RegShift64\nis sf=1 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift64 & Rn=0x1f & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64;\n\ttmp_1:8 = - tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# CONSTRUCT x6b0003e0/mask=xff2003e0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x6b0003e0/mask=xff2003e0 --status pass --comment \"flags\"\n\n:negs Rd_GPR32, RegShift32\nis sf=0 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn=0x1f & Rd_GPR32 & Rd & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32;\n\tsubflags0(tmp_2);\n\ttmp_1:4 = 0:4 - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectflags();\n}\n\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# CONSTRUCT xeb0003e0/mask=xff2003e0 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xeb0003e0/mask=xff2003e0 --status pass --comment \"flags\"\n\n:negs Rd_GPR64, RegShift64\nis sf=1 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift64 & Rn=0x1f & Rd_GPR64 & Rd\n{\n\ttmp_2:8 = RegShift64;\n\tsubflags0(tmp_2);\n\ttmp_1:8 = 0:8 - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectflags();\n}\n\n# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0\n# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00\n# CONSTRUCT x5a0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x5a0003e0/mask=xffe0ffe0 --status pass --comment \"flags\"\n\n:ngc Rd_GPR32, Rm_GPR32\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn=0x1f & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rm_GPR32 + zext(!CY);\n\tRd_GPR64 = zext(-tmp);\n}\n\n# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0\n# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00\n# CONSTRUCT xda0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xda0003e0/mask=xffe0ffe0 --status pass --comment \"flags\"\n\n:ngc Rd_GPR64, Rm_GPR64\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn=0x1f & Rd_GPR64\n{\n\ttmp:8 = Rm_GPR64 + zext(!CY);\n\tRd_GPR64 = -tmp;\n}\n\n# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0\n# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00\n# CONSTRUCT x7a0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x7a0003e0/mask=xffe0ffe0 --status pass --comment \"flags\"\n\n:ngcs Rd_GPR32, Rm_GPR32\nis sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rn=0x1f & opcode2=0x0 & Rm_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rm_GPR32 + zext(!CY);\n\tadd_with_carry_flags(0,~tmp);\n\tRd_GPR64 = zext(-tmp);\n\tresultflags(Rd_GPR32);\n\taffectflags();\n}\n\n# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0\n# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00\n# CONSTRUCT xfa0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xfa0003e0/mask=xffe0ffe0 --status pass --comment \"flags\"\n\n:ngcs Rd_GPR64, Rm_GPR64\nis sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rn=0x1f & opcode2=0x0 & Rm_GPR64 & Rd_GPR64\n{\n\ttmp:8 = Rm_GPR64 + zext(!CY);\n\tadd_with_carry_flags(0,~tmp);\n\tRd_GPR64 = -tmp;\n\tresultflags(Rd_GPR64);\n\taffectflags();\n}\n\n# C6.2.238 NOP page C6-1702 line 100611 MATCH xd503201f/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503201f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503201f/mask=xffffffff --status nodest\n\n:nop\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=0 & Rt=0x1f\n{\n}\n\n# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000\n# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0\n# CONSTRUCT x2a200000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x2a200000/mask=xff200000 --status pass\n\n:orn Rd_GPR32, Rn_GPR32, RegShift32Log\nis sf=0 & opc=1 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_3:4 = RegShift32Log;\n\ttmp_2:4 = tmp_3 ^ -1:4;\n\ttmp_1:4 = Rn_GPR32 | tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000\n# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0\n# CONSTRUCT xaa200000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xaa200000/mask=xff200000 --status pass\n\n:orn Rd_GPR64, Rn_GPR64, RegShift64Log\nis sf=1 & opc=1 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_3:8= RegShift64Log;\n\ttmp_2:8 = tmp_3 ^ -1:8;\n\ttmp_1:8 = Rn_GPR64 | tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000\n# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0\n# CONSTRUCT x32000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x32000000/mask=xff800000 --status pass\n\n:orr Rd_GPR32wsp, Rn_GPR32, DecodeWMask32\nis sf=0 & opc=1 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_1:4 = Rn_GPR32 | DecodeWMask32;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000\n# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0\n# CONSTRUCT xb2000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb2000000/mask=xff800000 --status pass\n\n:orr Rd_GPR64xsp, Rn_GPR64, DecodeWMask64\nis sf=1 & opc=1 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp\n{\n\ttmp_1:8 = Rn_GPR64 | DecodeWMask64;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000\n# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0\n# CONSTRUCT x2a000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x2a000000/mask=xff200000 --status pass\n\n:orr Rd_GPR32, Rn_GPR32, RegShift32Log\nis b_31=0 & b_2430=0b0101010 & b_21=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32Log;\n\ttmp_1:4 = Rn_GPR32 | tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000\n# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0\n# CONSTRUCT xaa000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xaa000000/mask=xff200000 --status pass\n\n:orr Rd_GPR64, Rn_GPR64, RegShift64Log\nis b_31=1 & b_2430=0b0101010 & b_21=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64Log;\n\ttmp_1:8 = Rn_GPR64 | tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.242 PACDA, PACDZA page C6-1709 line 100996 MATCH xdac10800/mask=xffffdc00\n# CONSTRUCT xdac10800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac10800/mask=xfffffc00 --status noqemu\n# z == 0 pacda variant\n\n:pacda Rd_GPR64, Rn_GPR64xsp\nis pacda__PACpart & b_1431=0b110110101100000100 & b_1012=0b010 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild pacda__PACpart;\n}\n\n# C6.2.242 PACDA, PACDZA page C6-1709 line 100996 MATCH xdac10800/mask=xffffdc00\n# CONSTRUCT xdac12be0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac12be0/mask=xffffffe0 --status noqemu\n# z == 1 pacdza variant\n\n:pacdza Rd_GPR64\nis pacdza__PACpart & b_1431=0b110110101100000100 & b_1012=0b010 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild pacdza__PACpart;\n}\n\n# C6.2.243 PACDB, PACDZB page C6-1710 line 101067 MATCH xdac10c00/mask=xffffdc00\n# CONSTRUCT xdac10c00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac10c00/mask=xfffffc00 --status noqemu\n# z == 0 pacdb variant\n\n:pacdb Rd_GPR64, Rn_GPR64xsp\nis pacdb__PACpart & b_1431=0b110110101100000100 & b_1012=0b011 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild pacdb__PACpart;\n}\n\n# C6.2.243 PACDB, PACDZB page C6-1710 line 101067 MATCH xdac10c00/mask=xffffdc00\n# CONSTRUCT xdac12fe0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac12fe0/mask=xffffffe0 --status noqemu\n# z == 1 pacdzb variant\n\n:pacdzb Rd_GPR64\nis pacdzb__PACpart & b_1431=0b110110101100000100 & b_1012=0b011 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild pacdzb__PACpart;\n}\n\n# C6.2.244 PACGA page C6-1711 line 101138 MATCH x9ac03000/mask=xffe0fc00\n# CONSTRUCT x9ac03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9ac03000/mask=xffe0fc00 --status noqemu\n\n:pacga Rd_GPR64, Rn_GPR64, Rm_GPR64xsp\nis b_2131=0b10011010110 & b_1015=0b001100 & Rm_GPR64xsp & Rn_GPR64 & Rd_GPR64\n{\n\t# This operation, unlike all other PAC operations, does not put its output in\n\t# the same register as its first input. This means that putting a \"noclobber\"\n\t# variant on this operation would violate the definition of PACGA.\n\tRd_GPR64 = pacga(Rn_GPR64, Rm_GPR64xsp);\n}\n\n# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xdac10000/mask=xffffdc00\n# CONSTRUCT xdac10000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac10000/mask=xfffffc00 --status noqemu\n# Z == 0 PACIA variant\n\n:pacia Rd_GPR64, Rn_GPR64xsp\nis pacia__PACpart & b_1431=0b110110101100000100 & b_1012=0b000 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild pacia__PACpart;\n}\n\n# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xdac10000/mask=xffffdc00\n# CONSTRUCT xdac123e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac123e0/mask=xffffffe0 --status noqemu\n# Z == 1 && Rn == 11111 PACIZA variant\n\n:paciza Rd_GPR64\nis paciza__PACpart & b_1431=0b110110101100000100 & b_1012=0b000 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild paciza__PACpart;\n}\n\n# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503211f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503211f/mask=xffffffff --status nodest\n# CRm == 0001 && op2 == 000 PICIA1716 variant\n\n:pacia1716\nis pacia1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b000 & b_0004=0b11111\n{\n\tbuild pacia1716__PACpart;\n}\n\n# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503233f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503233f/mask=xffffffff --status nodest\n# CRm == 0011 && op2 == 001 PACIASP variant\n\n:paciasp\nis paciasp__PACpart & PACIXSP_BTITARGETS & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b001 & b_0004=0b11111\n{\n\tbuild paciasp__PACpart;\n}\n\n# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503231f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503231f/mask=xffffffff --status nodest\n# CRm == 0011 && op2 == 000 PACIAZ variant\n\n:paciaz\nis paciaz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b000 & b_0004=0b11111\n{\n\tbuild paciaz__PACpart;\n}\n\n# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xdac10400/mask=xffffdc00\n# CONSTRUCT xdac10400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac10400/mask=xfffffc00 --status noqemu\n# Z == 0 PACIB variant\n\n:pacib Rd_GPR64, Rn_GPR64xsp\nis pacib__PACpart & b_1431=0b110110101100000100 & b_1012=0b001 & b_13=0 & Rn_GPR64xsp & Rd_GPR64\n{\n\tbuild pacib__PACpart;\n}\n\n# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xdac10400/mask=xffffdc00\n# CONSTRUCT xdac127e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac127e0/mask=xffffffe0 --status noqemu\n# Z == 1 && Rn = 11111 PACIZB variant\n\n:pacizb Rd_GPR64\nis pacizb__PACpart & b_1431=0b110110101100000100 & b_1012=0b001 & b_13=1 & b_0509=0b11111 & Rd_GPR64\n{\n\tbuild pacizb__PACpart;\n}\n\n# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503215f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503215f/mask=xffffffff --status nodest\n# CRm == 0001 && op2 == 010 PACIB1716 variant\n\n:pacib1716\nis pacib1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b010 & b_0004=0b11111\n{\n\tbuild pacib1716__PACpart;\n}\n\n# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503237f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503237f/mask=xffffffff --status nodest\n# CRm == 0011 && op2 == 011 PACIBSP variant\n\n:pacibsp\nis pacibsp__PACpart & PACIXSP_BTITARGETS & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b011 & b_0004=0b11111\n{\n\tbuild pacibsp__PACpart;\n}\n\n# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503235f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503235f/mask=xffffffff --status nodest\n# CRm == 0011 && op2 == 010 PACIBZ variant\n\n:pacibz\nis pacibz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b010 & b_0004=0b11111\n{\n\tbuild pacibz__PACpart;\n}\n\n# C6.2.247 PRFM (immediate) page C6-1718 line 101520 MATCH xf9800000/mask=xffc00000\n# CONSTRUCT xf9800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf9800000/mask=xffc00000 --status nomem\n\n:prfm aa_prefetch, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & b_0304 & b_0102 & b_00 & aa_prefetch\n{\n\taddr:8 = addrIndexed;\n\thint:1 = b_0304;\n\ttarget:1 = b_0102;\n\tstream:1 = b_00;\n\tHint_Prefetch(addr, hint, target, stream);\n}\n\n# C6.2.248 PRFM (literal) page C6-1720 line 101616 MATCH xd8000000/mask=xff000000\n# CONSTRUCT xd8000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd8000000/mask=xff000000 --status nodest --comment \"qemuerr(illegal addresses cause qemu exit)\"\n\n:prfm aa_prefetch, Addr19\nis size.ldstr=3 & b_2729=3 & v=0 & b_2425=0 & Addr19 & b_0304 & b_0102 & b_00 & aa_prefetch\n{\n\taddr:8 = &Addr19;\n\thint:1 = b_0304;\n\ttarget:1 = b_0102;\n\tstream:1 = b_00;\n\tHint_Prefetch(addr, hint, target, stream);\n}\n\n# C6.2.249 PRFM (register) page C6-1722 line 101700 MATCH xf8a04800/mask=xffe04c00\n# CONSTRUCT xf8a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8a00800/mask=xffe00c00 --status nomem\n\n:prfm aa_prefetch, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & addrIndexed & b_1011=2 & b_0304 & b_0102 & b_00 & aa_prefetch\n{\n\taddr:8 = addrIndexed;\n\thint:1 = b_0304;\n\ttarget:1 = b_0102;\n\tstream:1 = b_00;\n\tHint_Prefetch(addr, hint, target, stream);\n}\n\n# C6.2.250 PRFUM page C6-1724 line 101815 MATCH xf8800000/mask=xffe00c00\n# CONSTRUCT xf8800000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8800000/mask=xfffffc00 --status nomem\n\n:prfum aa_prefetch, addr_SIMM9\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & addr_SIMM9 & simm9=0 & b_1011=0 & b_0304 & b_0102 & b_00 & aa_prefetch\n{\n\taddr:8 = addr_SIMM9;\n\thint:1 = b_0304;\n\ttarget:1 = b_0102;\n\tstream:1 = b_00;\n\tHint_Prefetch(addr, hint, target, stream);\n}\n\n# C6.2.250 PRFUM page C6-1724 line 101815 MATCH xf8800000/mask=xffe00c00\n# CONSTRUCT xf8800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8800000/mask=xffe00c00 --status nomem\n\n:prfum aa_prefetch, addr_SIMM9\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & addr_SIMM9 & b_1011=0 & b_0304 & b_0102 & b_00 & aa_prefetch\n{\n\taddr:8 = addr_SIMM9;\n\thint:1 = b_0304;\n\ttarget:1 = b_0102;\n\tstream:1 = b_00;\n\tHint_Prefetch(addr, hint, target, stream);\n}\n\n# C6.2.253 RBIT page C6-1728 line 102006 MATCH x5ac00000/mask=x7ffffc00\n# CONSTRUCT x5ac00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x5ac00000/mask=xfffffc00 --status pass\n\n:rbit Rd_GPR32, Rn_GPR32\nis sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\t# The algorithm swaps 1, 2, 4, 8 bits, ect\n\tlocal tmp:4 = Rn_GPR32;\n\ttmp = (((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1));\n\ttmp = (((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2));\n\ttmp = (((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4));\n\ttmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8));\n\ttmp = ((tmp >> 16) | (tmp << 16));\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.253 RBIT page C6-1728 line 102006 MATCH x5ac00000/mask=x7ffffc00\n# CONSTRUCT xdac00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac00000/mask=xfffffc00 --status pass\n\n:rbit Rd_GPR64, Rn_GPR64\nis sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x0 & Rn_GPR64 & Rd_GPR64\n{\n\t# The algorithm swaps 1, 2, 4, 8 bits, ect\n\tlocal tmp:8 = Rn_GPR64;\n\ttmp = (((tmp & 0xaaaaaaaaaaaaaaaa) >> 1) | ((tmp & 0x5555555555555555) << 1));\n\ttmp = (((tmp & 0xcccccccccccccccc) >> 2) | ((tmp & 0x3333333333333333) << 2));\n\ttmp = (((tmp & 0xf0f0f0f0f0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f0f0f0f0f) << 4));\n\ttmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));\n\ttmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16));\n\tRd_GPR64 = ((tmp >> 32) | (tmp << 32));\n}\n\n# C6.2.254 RET page C6-1730 line 102090 MATCH xd65f0000/mask=xfffffc1f\n# CONSTRUCT xd65f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd65f0000/mask=xfffffc1f --status nodest\n\n:ret Rn_GPR64\nis b_2531=0x6b & b_2324=0 & b_2122=2 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0\n{\n\tpc = Rn_GPR64;\n\treturn [pc];\n}\n\n# C6.2.254 RET page C6-1730 line 102090 MATCH xd65f0000/mask=xfffffc1f\n# CONSTRUCT xd65f03c0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd65f03c0/mask=xffffffff --status nodest\n\n:ret\nis b_2531=0x6b & b_2324=0 & b_2122=2 & b_1620=0x1f & b_1015=0 & aa_Xn=30 & b_0004=0\n{\n\tpc = x30;\n\treturn [pc];\n}\n\n# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff\n# CONSTRUCT xd65f0bff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd65f0bff/mask=xffffffff --status nodest\n# M == 0 RETAA variant\n\n:retaa\nis retaa__PACpart & b_1131=0b110101100101111100001 & b_0009=0b1111111111 & b_10=0\n{\n\tbuild retaa__PACpart;\n\tpc = x30;\n\treturn [pc];\n}\n\n# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff\n# CONSTRUCT xd65f0fff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd65f0fff/mask=xffffffff --status nodest\n# M == 1 RETAB variant\n\n:retab\nis retab__PACpart & b_1131=0b110101100101111100001 & b_0009=0b1111111111 & b_10=1\n{\n\tbuild retab__PACpart;\n\tpc = x30;\n\treturn [pc];\n}\n\n# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800\n# CONSTRUCT x5ac00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x5ac00800/mask=xfffffc00 --status pass\n# sf == 0 && opc == 10 32-bit variant (3210 -> 0123)\n\n:rev Rd_GPR32, Rn_GPR32\nis b_1230=0b1011010110000000000 & b_31=0 & b_1011=0b10 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp:4 = Rn_GPR32;\n\ttmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8));\n\ttmp = ((tmp >> 16) | (tmp << 16));\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800\n# C6.2.259 REV64 page C6-1738 line 102502 MATCH xdac00c00/mask=xfffffc00\n# CONSTRUCT xdac00c00/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xdac00c00/mask=xfffffc00 --status pass\n# sf == 1 && opc == 11 64-bit variant (76543210 -> 01234567)\n# NB equivalent to REV64, which is never the preferred disassembly\n\n:rev Rd_GPR64, Rn_GPR64\nis b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b11 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp:8 = Rn_GPR64;\n\ttmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));\n\ttmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16));\n\tRd_GPR64 = ((tmp >> 32) | (tmp << 32));\n}\n\n# C6.2.257 REV16 page C6-1734 line 102308 MATCH x5ac00400/mask=x7ffffc00\n# CONSTRUCT x5ac00400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x5ac00400/mask=xfffffc00 --status pass\n# sf == 0 (and opc == 01) 32-bit variant (3210 -> 2301)\n\n:rev16 Rd_GPR32, Rn_GPR32\nis b_1230=0b1011010110000000000 & b_31=0 & b_1011=0b01 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp:4 = Rn_GPR32;\n\ttmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8));\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.257 REV16 page C6-1734 line 102308 MATCH x5ac00400/mask=x7ffffc00\n# CONSTRUCT xdac00400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac00400/mask=xfffffc00 --status pass\n# sf == 1 (and opc=01) 64-bit variant (76543210 -> 67452301)\n\n:rev16 Rd_GPR64, Rn_GPR64\nis b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b01 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp:8 = Rn_GPR64;\n\tRd_GPR64 = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));\n}\n\n# C6.2.258 REV32 page C6-1736 line 102412 MATCH xdac00800/mask=xfffffc00\n# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800\n# CONSTRUCT xdac00800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xdac00800/mask=xfffffc00 --status pass\n# sf == 1 (and opc == 10) 64-bit variant (76543210 -> 45670123)\n\n:rev32 Rd_GPR64, Rn_GPR64\nis b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b10 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp:8 = Rn_GPR64;\n\ttmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));\n\tRd_GPR64 = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16));\n}\n\n# C6.2.260 RMIF page C6-1739 line 102566 MATCH xba000400/mask=xffe07c10\n# CONSTRUCT xba000400/mask=xffe07c10 MATCHED 1 DOCUMENTED OPCODES\n\n:rmif Rn_GPR64, UImm6, NZCVImm_uimm4\nis b_2131=0b10111010000 & b_1014=0b00001 & b_04=0b0 & Rn_GPR64 & UImm6 & NZCVImm_uimm4\n{\n\ttmp:8 = Rn_GPR64 >> UImm6;\n\tcondMask:1 = NZCVImm_uimm4;\n\tset_NZCV(tmp,condMask);\n}\n\n# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000\n# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000\n# CONSTRUCT x13800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x13800000/mask=xffe00000 --status pass\n\n:ror Rd_GPR32, Rn_GPR32, LSB_bitfield32_imm\nis sf=0 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=0 & b_21=0 & Rn=Rm & Rm_GPR32 & LSB_bitfield32_imm & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tresult:4 = (Rn_GPR32 >> LSB_bitfield32_imm) | (Rn_GPR32 << (32 - LSB_bitfield32_imm));\n\tRd_GPR64 = zext(result);\n}\n\n# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000\n# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000\n# CONSTRUCT x93c00000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x93c00000/mask=xffe00000 --status pass\n\n:ror Rd_GPR64, Rn_GPR64, LSB_bitfield64_imm\nis sf=1 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=1 & b_21=0 & Rn=Rm & Rm_GPR64 & LSB_bitfield64_imm & Rn_GPR64 & Rd_GPR64\n{\n\tresult:8 = (Rn_GPR64 >> LSB_bitfield64_imm) | (Rn_GPR64 << (64 - LSB_bitfield64_imm));\n\tRd_GPR64 = result;\n}\n\n# C6.2.262 ROR (register) page C6-1742 line 102726 MATCH x1ac02c00/mask=x7fe0fc00\n# C6.2.263 RORV page C6-1744 line 102821 MATCH x1ac02c00/mask=x7fe0fc00\n# CONSTRUCT x1ac02c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x1ac02c00/mask=xffe0fc00 --status pass\n\n:ror Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0xb & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\trval:4 = Rm_GPR32 & 0x1f;\n\ttmp_1:4 = ( Rn_GPR32 >> rval) | ( Rn_GPR32 << ( 32 - rval ) );\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.262 ROR (register) page C6-1742 line 102726 MATCH x1ac02c00/mask=x7fe0fc00\n# C6.2.263 RORV page C6-1744 line 102821 MATCH x1ac02c00/mask=x7fe0fc00\n# CONSTRUCT x9ac02c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ac02c00/mask=xffe0fc00 --status pass\n\n:ror Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0xb & Rn_GPR64 & Rd_GPR64\n{\n\trval:8 = Rm_GPR64 & 0x3f;\n\ttmp_1:8 = ( Rn_GPR64 >> rval ) | ( Rn_GPR64 << ( 64 - rval ) );\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.264 SB page C6-1746 line 102913 MATCH xd50330ff/mask=xfffff0ff\n# CONSTRUCT xd50330ff/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES\n\n:sb\nis b_1231=0xd5033 & b_0007=0xff\n{\n\tSpeculationBarrier();\n}\n\n# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00\n# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0\n# CONSTRUCT x5a000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x5a000000/mask=xffe0fc00 --status pass --comment \"flags\"\n\n:sbc Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rm_GPR32 + zext(!CY);\n\tRd_GPR64 = zext(Rn_GPR32 - tmp);\n}\n\n# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00\n# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0\n# CONSTRUCT xda000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xda000000/mask=xffe0fc00 --status pass --comment \"flags\"\n\n:sbc Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp:8 = Rm_GPR64 + zext(!CY);\n\tRd_GPR64 = Rn_GPR64 - tmp;\n}\n\n# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00\n# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0\n# CONSTRUCT x7a000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x7a000000/mask=xffe0fc00 --status pass --comment \"flags\"\n\n:sbcs Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rm_GPR32 + zext(!CY);\n\tadd_with_carry_flags(Rn_GPR32, ~Rm_GPR32);\n\tRd_GPR64 = zext(Rn_GPR32 - tmp);\n\tresultflags(Rd_GPR32);\n\taffectflags();\n}\n\n# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00\n# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0\n# CONSTRUCT xfa000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xfa000000/mask=xffe0fc00 --status pass --comment \"flags\"\n\n:sbcs Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp:8 = Rm_GPR64 + zext(!CY);\n\tadd_with_carry_flags(Rn_GPR64, ~Rm_GPR64);\n\tRd_GPR64 = Rn_GPR64 - tmp;\n\tresultflags(Rd_GPR64);\n\taffectflags();\n}\n\n# C6.2.209 SBFIZ page C6-856 line 49751 KEEPWITH\n\nsbfiz_lsb: \"#\"^imm is ImmR [ imm = 32 - ImmR; ] { export *[const]:4 imm; }\nsbfiz_width: \"#\"^imm is ImmS [ imm = ImmS + 1; ] { export *[const]:4 imm; }\nsbfiz_lsb64: \"#\"^imm is ImmR [ imm = 64 - ImmR; ] { export *[const]:4 imm; }\n\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# CONSTRUCT x13000002/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES\n# AUNIT --inst x13000002/mask=xffe08006 --status pass\n# Special alias case of sbfm for when ImmS < ImmR-1\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:sbfiz Rd_GPR32, Rn_GPR32, sbfiz_lsb, sbfiz_width\nis sbfiz_lsb & sbfiz_width & ImmS_LT_ImmR=1 & ImmS_EQ_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & DecodeWMask32 & DecodeTMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal wmask:4 = DecodeWMask32;\n\tlocal tmask:4 = DecodeTMask32;\n\tlocal src:4 = Rn_GPR32;\n\tlocal bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;\n\tlocal top:4 = (((src>>ImmSConst32)&0x1)*(-1))&0xffffffff;\n\tRd_GPR64 = zext((top & ~(tmask)) | (bot & tmask));\n}\n\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00\n# CONSTRUCT x93400002/mask=xffc00006 MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x93400002/mask=xffc00006 --status pass\n# Special alias case of sbfm for when ImmS < ImmR-1\n\n:sbfiz Rd_GPR64, Rn_GPR64, sbfiz_lsb64, sbfiz_width\nis sbfiz_lsb64 & sbfiz_width & ImmS_LT_ImmR=1 & ImmS_EQ_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & ImmSConst64 & DecodeWMask64 & DecodeTMask64 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal wmask:8 = DecodeWMask64;\n\tlocal tmask:8 = DecodeTMask64;\n\tlocal src:8 = Rn_GPR64;\n\tlocal bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;\n\tlocal top:8 = ((src>>ImmSConst64)&0x1)*(-1);\n\tRd_GPR64 = (top & ~(tmask)) | (bot & tmask);\n}\n\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# CONSTRUCT x13000000/mask=xffe08000 MATCHED 6 DOCUMENTED OPCODES\n# AUNIT --inst x13000000/mask=xffe08000 --status pass\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:sbfm Rd_GPR32, Rn_GPR32, ImmRConst32, ImmSConst32\nis sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & DecodeWMask32 & DecodeTMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal wmask:4 = DecodeWMask32;\n\tlocal tmask:4 = DecodeTMask32;\n\tlocal src:4 = Rn_GPR32;\n\tlocal bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;\n\tlocal top:4 = (((src>>ImmSConst32)&0x1)*(-1))&0xffffffff;\n\tRd_GPR64 = zext((top & ~(tmask)) | (bot & tmask));\n}\n\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00\n# CONSTRUCT x93400000/mask=xffc00000 MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x93400000/mask=xffc00000 --status pass\n\n:sbfm Rd_GPR64, Rn_GPR64, ImmRConst64, ImmSConst64\nis sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & ImmSConst64 & DecodeWMask64 & DecodeTMask64 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal wmask:8 = DecodeWMask64;\n\tlocal tmask:8 = DecodeTMask64;\n\tlocal src:8 = Rn_GPR64;\n\tlocal bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;\n\tlocal top:8 = ((src>>ImmSConst64)&0x1)*(-1);\n\tRd_GPR64 = (top & ~(tmask)) | (bot & tmask);\n}\n\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# CONSTRUCT x13000004/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES\n# AUNIT --inst x13000004/mask=xffe08006 --status pass\n# Special cases when just getting the 0 bit\n# >> Not sure about the above old comment one, this is actually for getting one bit from Rn\n# SBFX alias of SMFM is used when ImmS >= ImmR\n# We split the '>=' into two separate cases\n# Here ImmS = ImmR (for 32-bit)\n# Alias for sbfm as determined by BFXPreferred()\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:sbfx Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32\nis ImmS_LT_ImmR=0 & ImmS_EQ_ImmR=1 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & ImmSConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = ((Rn_GPR32 >> ImmSConst32) & 0x1) * 0xffffffff;\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00\n# CONSTRUCT x93400004/mask=xffc00006 MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x93400004/mask=xffc00006 --status pass\n# Now, the case where ImmS = ImmR (for 64-bit)\n\n:sbfx Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64\nis ImmS_LT_ImmR=0 & ImmS_EQ_ImmR=1 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & BFextractWidth64 & ImmRConst64 & ImmSConst64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp:8 = ((Rn_GPR64 >> ImmSConst64) & 0x1) * 0xffffffffffffffff;\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# CONSTRUCT x13000000/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES\n# AUNIT --inst x13000000/mask=xffe08006 --status pass\n# Now, the case where ImmS > ImmR (for 32-bit)\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:sbfx Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32\nis ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tsrc:4 = Rn_GPR32;\n\ttmp:4 = src << (31 - (ImmRConst32 + BFextractWidth32 - 1));\n\ttmp = tmp s>> (32 - BFextractWidth32);\n\tRd_GPR64 = zext(tmp);\n}\n\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00\n# CONSTRUCT x93400000/mask=xffc00000 MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x93400000/mask=xffc00000 --status pass\n# Finally, the case where ImmS > ImmR (for 64-bit)\n\n:sbfx Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64\nis sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & BFextractWidth64 & (ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0) & Rn_GPR64 & Rd_GPR64\n{\n\tsrc:8 = Rn_GPR64;\n\ttmp:8 = src << (63 - (ImmRConst64 + BFextractWidth64 - 1));\n\ttmp = tmp s>> (64 - BFextractWidth64);\n\tRd_GPR64 = tmp;\n}\n\n# C6.2.270 SDIV page C6-1758 line 103515 MATCH x1ac00c00/mask=x7fe0fc00\n# CONSTRUCT x1ac00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x1ac00c00/mask=xffe0fc00 --status pass\n\n:sdiv Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x3 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp_1:4 = 0;\n\tif (Rm_GPR32 == 0) goto ;\n\ttmp_1 = Rn_GPR32 s/ Rm_GPR32;\n\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.270 SDIV page C6-1758 line 103515 MATCH x1ac00c00/mask=x7fe0fc00\n# CONSTRUCT x9ac00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9ac00c00/mask=xffe0fc00 --status pass\n\n:sdiv Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x3 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp_1:8 = 0;\n\tif (Rm_GPR64 == 0) goto ;\n\ttmp_1 = Rn_GPR64 s/ Rm_GPR64;\n\n\tRd_GPR64 = tmp_1;\n}\n\n\n# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f\n# CONSTRUCT x3a00080d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES\n\n:setf8 aa_Wn\nis b_1531=0b00111010000000000 & b_14=0 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn\n{\n\tNG = ((aa_Wn:1 >> 7) & 1) == 1;\n\tZR = (aa_Wn:1 == 0);\n\tOV = (((aa_Wn >> 7) & 1) ^ ((aa_Wn >>8) & 1)) == 1;\n}\n\n\n# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f\n# CONSTRUCT x3a00480d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES\n\n:setf16 aa_Wn\nis b_1531=0b00111010000000000 & b_14=1 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn\n{\n\tNG = ((aa_Wn:2 >> 15) & 1) == 1;\n\tZR = (aa_Wn:2 == 0);\n\tOV = (((aa_Wn >> 15) & 1) ^ ((aa_Wn >>16) & 1)) == 1;\n}\n\n\n\n\n# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00\n# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00\n# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES\n\nsetPhase:\"p\" is b_1415=0 {export 0:1;}\nsetPhase:\"m\" is b_1415=1 {export 1:1;}\nsetPhase:\"e\" is b_1415=2 {export 2:1;}\n\nsetType: \"\"\t\tis b_1013=0x1 {export 1:1; }\nsetType: \"n\"\tis b_1013=0x9 {export 9:1; }\nsetType: \"t\"\tis b_1013=0x5 {export 5:1; }\nsetType: \"tn\"\tis b_1013=0xd {export 13:1; }\n\ndefine pcodeop memorySetTag;\n:setg^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64\nis size.ldstr & b_2129=0xee & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 {\n\tmemorySetTag(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType);\n}\n\n\n# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00\n# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES\ndefine pcodeop memorySet;\n:setp^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64\nis size.ldstr & b_2129=0xce & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 {\n\tmemorySet(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType);\n}\n\n\n# C6.2.280 SEV page C6-1796 line 106224 MATCH xd503209f/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503209f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503209f/mask=xffffffff --status nodest\n\n:sev\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=4 & Rt=0x1f\n{\n\tSendEvent();\n}\n\n# C6.2.281 SEVL page C6-1797 line 106259 MATCH xd50320bf/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd50320bf/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50320bf/mask=xffffffff --status nodest\n\n:sevl\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=5 & Rt=0x1f\n{\n\tSendEventLocally();\n}\n\n# C6.2.282 SMADDL page C6-1798 line 106294 MATCH x9b200000/mask=xffe08000\n# CONSTRUCT x9b200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9b200000/mask=xffe08000 --status pass\n\n:smaddl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = sext(Rn_GPR32);\n\ttmp_4:8 = sext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\ttmp_1:8 = Ra_GPR64 + tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.283 SMC page C6-1800 line 106384 MATCH xd4000003/mask=xffe0001f\n# CONSTRUCT xd4000003/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4000003/mask=xffe0001f --status nodest\n\n:smc imm16\nis b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=3\n{\n\tCallSecureMonitor(imm16:2);\n}\n\n# C6.2.284 SMNEGL page C6-1801 line 106433 MATCH x9b20fc00/mask=xffe0fc00\n# C6.2.287 SMSUBL page C6-1806 line 106711 MATCH x9b208000/mask=xffe08000\n# CONSTRUCT x9b20fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9b20fc00/mask=xffe0fc00 --status pass\n\n:smnegl Rd_GPR64, Rn_GPR32, Rm_GPR32\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = sext(Rn_GPR32);\n\ttmp_4:8 = sext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\tsubflags0(tmp_2);\n\ttmp_1:8 = -tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.287 SMSUBL page C6-1806 line 106711 MATCH x9b208000/mask=xffe08000\n# CONSTRUCT x9b208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9b208000/mask=xffe08000 --status pass\n\n:smsubl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = sext(Rn_GPR32);\n\ttmp_4:8 = sext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\ttmp_1:8 = Ra_GPR64 - tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n\n# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff\n# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f\n# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES\n# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=110101010000001101000..101111111\n\ndefine pcodeop sveStreamingModeStart;\ndefine pcodeop sveStreamingModeStop;\n\nSVAmodeOp: \"SM\" is b_0911=0x1 & b_08 { svcr[0,1] = b_08; }\nSVAmodeOp: \"ZA\" is b_0911=0x2 & b_08 { svcr[1,1] = b_08; }\nSVAmodeOp: \"\" is b_0911=0x3 & b_08 { svcr[0,1] = b_08; svcr[1,1] = b_08; }\n\n:smstart \"{\"^SVAmodeOp^\"}\"\nis b_1131=0x1aa068 & SVAmodeOp & b_08=1 & b_0507=0x3 & op4=0x1f {\n\tbuild SVAmodeOp;\n\tsveStreamingModeStart();\n}\n\n\n# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff\n# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f\n# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES\n# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=110101010000001101000..001111111\n\n:smstop \"{\"^SVAmodeOp^\"}\"\nis b_1131=0x1aa068 & SVAmodeOp & b_08=0 & b_0507=0x3 & op4=0x1f {\n\tsveStreamingModeStop();\n}\n\n\n# C6.2.288 SMULH page C6-1808 line 106800 MATCH x9b400000/mask=xffe08000\n# CONSTRUCT x9b400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9b400000/mask=xffe08000 --status pass\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:smulh Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & op.dp3=0 & b_2428=0x1b & op.dp3_op31=2 & Rm_GPR64 & op.dp3_o0=0 & Ra & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmpq:16 = sext(Rn_GPR64) * sext(Rm_GPR64);\n\tRd_GPR64 = tmpq(8);\n}\n\n# C6.2.289 SMULL page C6-1809 line 106867 MATCH x9b207c00/mask=xffe0fc00\n# C6.2.282 SMADDL page C6-1798 line 106294 MATCH x9b200000/mask=xffe08000\n# CONSTRUCT x9b207c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9b207c00/mask=xffe0fc00 --status pass\n\n:smull Rd_GPR64, Rn_GPR32, Rm_GPR32\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = sext(Rn_GPR32);\n\ttmp_4:8 = sext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\ttmp_1:8 = tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.295 STADDB, STADDLB page C6-1818 line 107383 MATCH x3820001f/mask=xffa0fc1f\n# C6.2.298 STCLRB, STCLRLB page C6-1824 line 107670 MATCH x3820101f/mask=xffa0fc1f\n# C6.2.301 STEORB, STEORLB page C6-1830 line 107956 MATCH x3820201f/mask=xffa0fc1f\n# C6.2.328 STSETB, STSETLB page C6-1886 line 111044 MATCH x3820301f/mask=xffa0fc1f\n# C6.2.331 STSMAXB, STSMAXLB page C6-1892 line 111330 MATCH x3820401f/mask=xffa0fc1f\n# C6.2.334 STSMINB, STSMINLB page C6-1898 line 111623 MATCH x3820501f/mask=xffa0fc1f\n# C6.2.340 STUMAXB, STUMAXLB page C6-1910 line 112231 MATCH x3820601f/mask=xffa0fc1f\n# C6.2.343 STUMINB, STUMINLB page C6-1916 line 112525 MATCH x3820701f/mask=xffa0fc1f\n# C6.2.133 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-1489 line 88545 MATCH x38200000/mask=xff20fc00\n# C6.2.152 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB page C6-1524 line 90495 MATCH x38201000/mask=xff20fc00\n# C6.2.155 LDEORB, LDEORAB, LDEORALB, LDEORLB page C6-1531 line 90916 MATCH x38202000/mask=xff20fc00\n# C6.2.181 LDSETB, LDSETAB, LDSETALB, LDSETLB page C6-1590 line 94403 MATCH x38203000/mask=xff20fc00\n# C6.2.184 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB page C6-1597 line 94824 MATCH x38204000/mask=xff20fc00\n# C6.2.187 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB page C6-1604 line 95245 MATCH x38205000/mask=xff20fc00\n# C6.2.196 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB page C6-1623 line 96362 MATCH x38206000/mask=xff20fc00\n# C6.2.199 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB page C6-1630 line 96783 MATCH x38207000/mask=xff20fc00\n# CONSTRUCT x3820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES\n# AUNIT --inst x3820001f/mask=xffa08c1f --status nomem\n\n# size=0b00 (3031)\n\n:st^ls_opc1^ls_lor^\"b\" aa_Ws, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc1 & ls_lor & aa_Ws & Rn_GPR64xsp\n{ build ls_opc1; build ls_lor; }\n\n# C6.2.296 STADDH, STADDLH page C6-1820 line 107469 MATCH x7820001f/mask=xffa0fc1f\n# C6.2.299 STCLRH, STCLRLH page C6-1826 line 107756 MATCH x7820101f/mask=xffa0fc1f\n# C6.2.302 STEORH, STEORLH page C6-1832 line 108042 MATCH x7820201f/mask=xffa0fc1f\n# C6.2.329 STSETH, STSETLH page C6-1888 line 111130 MATCH x7820301f/mask=xffa0fc1f\n# C6.2.332 STSMAXH, STSMAXLH page C6-1894 line 111419 MATCH x7820401f/mask=xffa0fc1f\n# C6.2.335 STSMINH, STSMINLH page C6-1900 line 111712 MATCH x7820501f/mask=xffa0fc1f\n# C6.2.341 STUMAXH, STUMAXLH page C6-1912 line 112320 MATCH x7820601f/mask=xffa0fc1f\n# C6.2.344 STUMINH, STUMINLH page C6-1918 line 112614 MATCH x7820701f/mask=xffa0fc1f\n# C6.2.134 LDADDH, LDADDAH, LDADDALH, LDADDLH page C6-1491 line 88670 MATCH x78200000/mask=xff20fc00\n# C6.2.153 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH page C6-1526 line 90621 MATCH x78201000/mask=xff20fc00\n# C6.2.156 LDEORH, LDEORAH, LDEORALH, LDEORLH page C6-1533 line 91042 MATCH x78202000/mask=xff20fc00\n# C6.2.182 LDSETH, LDSETAH, LDSETALH, LDSETLH page C6-1592 line 94529 MATCH x78203000/mask=xff20fc00\n# C6.2.185 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH page C6-1599 line 94950 MATCH x78204000/mask=xff20fc00\n# C6.2.188 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH page C6-1606 line 95371 MATCH x78205000/mask=xff20fc00\n# C6.2.197 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH page C6-1625 line 96488 MATCH x78206000/mask=xff20fc00\n# C6.2.200 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH page C6-1632 line 96909 MATCH x78207000/mask=xff20fc00\n# CONSTRUCT x7820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES\n# AUNIT --inst x7820001f/mask=xffa08c1f --status nomem\n\n# size=0b01 (3031)\n\n:st^ls_opc2^ls_lor^\"h\" aa_Ws, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc2 & ls_lor & aa_Ws & Rn_GPR64xsp\n{ build ls_opc2; build ls_lor; }\n\n# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f\n# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f\n# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f\n# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f\n# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f\n# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f\n# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f\n# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f\n# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00\n# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00\n# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00\n# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00\n# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00\n# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00\n# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00\n# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00\n# CONSTRUCT xb820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES\n# AUNIT --inst xb820001f/mask=xffa08c1f --status nomem\n\n# size=0b10 (3031)\n\n:st^ls_opc4^ls_lor aa_Ws, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc4 & ls_lor & aa_Ws & Rn_GPR64xsp\n{ build ls_opc4; build ls_lor; }\n\n# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f\n# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f\n# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f\n# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f\n# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f\n# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f\n# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f\n# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f\n# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00\n# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00\n# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00\n# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00\n# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00\n# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00\n# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00\n# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00\n# CONSTRUCT xf820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES\n# AUNIT --inst xf820001f/mask=xffa08c1f --status nomem\n# size=0b11 (3031)\n\n:st^ls_opc8^ls_lor aa_Xs, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc8 & ls_lor & aa_Xs & Rn_GPR64xsp\n{ build ls_opc8; build ls_lor; }\n\n# C6.2.307 STLLRB page C6-1842 line 108609 MATCH x08800000/mask=xffe08000\n# CONSTRUCT x08800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08800000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b00 (3031)\n\n:stllrb aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp\n{ *:1 Rn_GPR64xsp = aa_Wt:1; LORelease(); }\n\n# C6.2.308 STLLRH page C6-1843 line 108673 MATCH x48800000/mask=xffe08000\n# CONSTRUCT x48800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48800000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b01 (3031)\n\n:stllrh aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp\n{ *:2 Rn_GPR64xsp = aa_Wt:2; LORelease(); }\n\n# C6.2.309 STLLR page C6-1844 line 108737 MATCH x88800000/mask=xbfe08000\n# CONSTRUCT x88800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88800000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b10 (3031)\n\n:stllr aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp\n{ *:4 Rn_GPR64xsp = aa_Wt; LORelease(); }\n\n# C6.2.309 STLLR page C6-1844 line 108737 MATCH x88800000/mask=xbfe08000\n# CONSTRUCT xc8800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8800000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n# size=0b11 (3031)\n\n:stllr aa_Xt, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Xt & Rn_GPR64xsp\n{ *:8 Rn_GPR64xsp = aa_Xt; LORelease(); }\n\n# C6.2.310 STLR page C6-1846 line 108821 MATCH x88808000/mask=xbfe08000\n# CONSTRUCT xc8808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8808000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:stlr Rt_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR64\n{\n\t*addrReg = Rt_GPR64;\n}\n\n# C6.2.310 STLR page C6-1846 line 108821 MATCH x88808000/mask=xbfe08000\n# CONSTRUCT x88808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88808000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:stlr Rt_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32\n{\n\t*addrReg = Rt_GPR32;\n}\n\n# C6.2.311 STLRB page C6-1848 line 108904 MATCH x08808000/mask=xffe08000\n# CONSTRUCT x08808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08808000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:stlrb Rt_GPR32, addrReg\nis size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32\n{\n\t*addrReg = Rt_GPR32;\n}\n\n# C6.2.312 STLRH page C6-1849 line 108967 MATCH x48808000/mask=xffe08000\n# CONSTRUCT x48808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48808000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111\n\n:stlrh Rt_GPR32, addrReg\nis size.ldstr=1 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32\n{\n\t*addrReg = Rt_GPR32;\n}\n\n# C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00\n# CONSTRUCT x99000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:stlur aa_Wt, addr_SIMM9\nis b_3031=0b10 & b_2129=0b011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt\n{\n\t*addr_SIMM9 = aa_Wt;\n}\n\n# C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00\n# CONSTRUCT xd9000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:stlur aa_Xt, addr_SIMM9\nis b_3031=0b11 & b_2129=0b011001000 & b_1011=0b00 & addr_SIMM9 & aa_Xt\n{\n\t*addr_SIMM9 = aa_Xt;\n}\n\n# C6.2.314 STLURB page C6-1852 line 109129 MATCH x19000000/mask=xffe00c00\n# CONSTRUCT x19000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x19000000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:stlurb aa_Wt, addr_SIMM9\nis b_2131=0b00011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt\n{\n\t*addr_SIMM9 = aa_Wt:1;\n}\n\n# C6.2.315 STLURH page C6-1854 line 109217 MATCH x59000000/mask=xffe00c00\n# CONSTRUCT x59000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# x59000000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR\n\n:stlurh aa_Wt, addr_SIMM9\nis b_2131=0b01011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt\n{\n\t*addr_SIMM9 = aa_Wt:2;\n}\n\n# C6.2.316 STLXP page C6-1856 line 109305 MATCH x88208000/mask=xbfe08000\n# CONSTRUCT xc8208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8208000/mask=xffe08000 --status nomem\n\n:stlxp Rs_GPR32, Rt_GPR64, Rt2_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=1 & Rt2_GPR64 & addrReg & Rt_GPR64 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR64;\n\t*(addrReg + 4) = Rt2_GPR64;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.316 STLXP page C6-1856 line 109305 MATCH x88208000/mask=xbfe08000\n# CONSTRUCT x88208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88208000/mask=xffe08000 --status nomem\n\n:stlxp Rs_GPR32, Rt_GPR32, Rt2_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=1 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR32;\n\t*(addrReg + 4) = Rt2_GPR32;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.317 STLXR page C6-1859 line 109472 MATCH x88008000/mask=xbfe08000\n# CONSTRUCT xc8008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8008000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stlxr Rs_GPR32, Rt_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR64 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR64;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.317 STLXR page C6-1859 line 109472 MATCH x88008000/mask=xbfe08000\n# CONSTRUCT x88008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88008000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stlxr Rs_GPR32, Rt_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR32;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.318 STLXRB page C6-1862 line 109627 MATCH x08008000/mask=xffe08000\n# CONSTRUCT x08008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08008000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stlxrb Rs_GPR32, Rt_GPR32, addrReg\nis size.ldstr=0 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\tlocal tmp:4 = Rt_GPR32;\n\t*addrReg = tmp:1;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.319 STLXRH page C6-1864 line 109754 MATCH x48008000/mask=xffe08000\n# CONSTRUCT x48008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48008000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stlxrh Rs_GPR32, Rt_GPR32, addrReg\nis size.ldstr=1 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\tlocal tmp:4 = Rt_GPR32;\n\t*addrReg = tmp:2;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000\n# CONSTRUCT x28000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x28000000/mask=xffc00000 --status nomem\n\n:stnp Rt_GPR32, Rt2_GPR32, addrPairIndexed\nis b_3031=0b00 & b_2229=0b10100000 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32\n{\n\tdata1:4 = Rt_GPR32;\n\tdata2:4 = Rt2_GPR32;\n\tbuild addrPairIndexed;\n\t*addrPairIndexed = data1;\n\t*(addrPairIndexed + 4) = data2;\n}\n\n# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000\n# CONSTRUCT xa8000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xa8000000/mask=xffc00000 --status nomem\n\n:stnp Rt_GPR64, Rt2_GPR64, addrPairIndexed\nis b_3031=0b10 & b_2229=0b10100000 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64\n{\n\tdata1:8 = Rt_GPR64;\n\tdata2:8 = Rt2_GPR64;\n\tbuild addrPairIndexed;\n\t*addrPairIndexed = data1;\n\t*(addrPairIndexed + 8) = data2;\n}\n\n# C6.2.321 STP page C6-1868 line 109996 MATCH x28800000/mask=x7fc00000\n# C6.2.321 STP page C6-1868 line 109996 MATCH x29800000/mask=x7fc00000\n# C6.2.321 STP page C6-1868 line 109996 MATCH x29000000/mask=x7fc00000\n# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000\n# CONSTRUCT x28000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x28000000/mask=xfe400000 --status nomem\n\n:stp Rt_GPR32, Rt2_GPR32, addrPairIndexed\nis b_3031=0b00 & b_2529=0b10100 & b_22=0b0 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32\n{\n\tdata1:4 = Rt_GPR32;\n\tdata2:4 = Rt2_GPR32;\n\tbuild addrPairIndexed;\n\t*addrPairIndexed = data1;\n\t*(addrPairIndexed + 4) = data2;\n}\n\n# C6.2.321 STP page C6-1868 line 109996 MATCH x28800000/mask=x7fc00000\n# C6.2.321 STP page C6-1868 line 109996 MATCH x29800000/mask=x7fc00000\n# C6.2.321 STP page C6-1868 line 109996 MATCH x29000000/mask=x7fc00000\n# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000\n# CONSTRUCT xa8000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xa8000000/mask=xfe400000 --status nomem\n\n:stp Rt_GPR64, Rt2_GPR64, addrPairIndexed\nis b_3031=0b10 & b_2529=0b10100 & b_22=0b0 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64\n{\n\tdata1:8 = Rt_GPR64;\n\tdata2:8 = Rt2_GPR64;\n\tbuild addrPairIndexed;\n\t*addrPairIndexed = data1;\n\t*(addrPairIndexed + 8) = data2;\n}\n\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb9000000/mask=xbfc00000\n# CONSTRUCT xb9000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb9000000/mask=xffc00000 --status nomem\n\n:str Rt_GPR32, addrUIMM\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR32\n{\n\t*addrUIMM = Rt_GPR32;\n}\n\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00\n# C6.2.337 STTR page C6-1904 line 111916 MATCH xb8000800/mask=xbfe00c00\n# C6.2.346 STUR page C6-1922 line 112818 MATCH xb8000000/mask=xbfe00c00\n# CONSTRUCT xb8000000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst xb8000000/mask=xffe00000 --status nomem\n\n:st^UnscPriv^\"r\" Rt_GPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32\n{\n\tdata1:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00\n# CONSTRUCT xb8000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb8000400/mask=xffe00400 --status nomem\n\n:str Rt_GPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32\n{\n\tdata1:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb9000000/mask=xbfc00000\n# CONSTRUCT xf9000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf9000000/mask=xffc00000 --status nomem\n\n:str Rt_GPR64, addrUIMM\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR64\n{\n\t*addrUIMM = Rt_GPR64;\n}\n\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00\n# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00\n# CONSTRUCT xf8000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf8000400/mask=xffe00400 --status nomem\n\n:str Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64\n{\n\tdata1:8 = Rt_GPR64;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.323 STR (register) page C6-1874 line 110394 MATCH xb8200800/mask=xbfe00c00\n# CONSTRUCT xb8200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb8200800/mask=xffe00c00 --status nomem\n\n:str Rt_GPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32\n{\n\tdata1:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.323 STR (register) page C6-1874 line 110394 MATCH xb8200800/mask=xbfe00c00\n# CONSTRUCT xf8200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8200800/mask=xffe00c00 --status nomem\n\n:str Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64\n{\n\tdata1:8 = Rt_GPR64;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x39000000/mask=xffc00000\n# CONSTRUCT x39000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x39000000/mask=xffc00000 --status nomem\n\n:strb Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrIndexed & Rt_GPR32\n{\n\ttmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:1;\n}\n\n# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x38000400/mask=xffe00c00\n# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x38000c00/mask=xffe00c00\n# CONSTRUCT x38000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x38000400/mask=xffe00400 --status nomem\n\n:strb Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32\n{\n\ttmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:1;\n}\n\n# C6.2.325 STRB (register) page C6-1879 line 110678 MATCH x38200800/mask=xffe00c00\n# CONSTRUCT x38200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x38200800/mask=xffe00c00 --status nomem\n\n:strb Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32\n{\n\ttmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:1;\n}\n\n# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x79000000/mask=xffc00000\n# CONSTRUCT x79000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x79000000/mask=xffc00000 --status nomem\n\n:strh Rt_GPR32, addrUIMM\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR32\n{\n\ttmp:4 = Rt_GPR32;\n\t*addrUIMM = tmp:2;\n}\n\n# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x78000400/mask=xffe00c00\n# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x78000c00/mask=xffe00c00\n# CONSTRUCT x78000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x78000400/mask=xffe00400 --status nomem\n\n:strh Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32\n{\n\ttmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:2;\n}\n\n# C6.2.327 STRH (register) page C6-1884 line 110943 MATCH x78200800/mask=xffe00c00\n# CONSTRUCT x78200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x78200800/mask=xffe00c00 --status nomem\n\n:strh Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32\n{\n\ttmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:2;\n}\n\n# C6.2.337 STTR page C6-1904 line 111916 MATCH xb8000800/mask=xbfe00c00\n# CONSTRUCT xf8000800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8000800/mask=xffe00c00 --status nomem\n\n:st^UnscPriv^\"r\" Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=0 & b_2121=0 & b_1011=2 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tdata1:8 = Rt_GPR64;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.338 STTRB page C6-1906 line 112029 MATCH x38000800/mask=xffe00c00\n# C6.2.347 STURB page C6-1924 line 112913 MATCH x38000000/mask=xffe00c00\n# CONSTRUCT x38000000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x38000000/mask=xffe00000 --status nomem\n\n:st^UnscPriv^\"rb\" Rt_GPR32, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32\n{\n\tlocal tmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:1;\n}\n\n# C6.2.339 STTRH page C6-1908 line 112130 MATCH x78000800/mask=xffe00c00\n# C6.2.348 STURH page C6-1925 line 112984 MATCH x78000000/mask=xffe00c00\n# CONSTRUCT x78000000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x78000000/mask=xffe00000 --status nomem\n\n:st^UnscPriv^\"rh\" Rt_GPR32, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32\n{\n\tlocal tmp:4 = Rt_GPR32;\n\tbuild addrIndexed;\n\t*addrIndexed = tmp:2;\n}\n\n# C6.2.346 STUR page C6-1922 line 112818 MATCH xb8000000/mask=xbfe00c00\n# CONSTRUCT xf8000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8000000/mask=xffe00c00 --status nomem\n\n:st^UnscPriv^\"r\" Rt_GPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2122=0 & b_1011=0 & UnscPriv & addrIndexed & Rt_GPR64\n{\n\tdata1:8 = Rt_GPR64;\n\tbuild addrIndexed;\n\t*addrIndexed = data1;\n}\n\n# C6.2.349 STXP page C6-1926 line 113055 MATCH x88200000/mask=xbfe08000\n# CONSTRUCT xc8200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8200000/mask=xffe08000 --status nomem\n\n:stxp Rs_GPR32, Rt_GPR64, Rt2_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=0 & Rt2_GPR64 & addrReg & Rt_GPR64 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR64;\n\t*(addrReg + 8) = Rt2_GPR64;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.349 STXP page C6-1926 line 113055 MATCH x88200000/mask=xbfe08000\n# CONSTRUCT x88200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88200000/mask=xffe08000 --status nomem\n\n:stxp Rs_GPR32, Rt_GPR32, Rt2_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=0 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR32;\n\t*(addrReg + 4) = Rt2_GPR32;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.350 STXR page C6-1929 line 113222 MATCH x88000000/mask=xbfe08000\n# CONSTRUCT xc8000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xc8000000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stxr Rs_GPR32, Rt_GPR64, addrReg\nis size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR64 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR64;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.350 STXR page C6-1929 line 113222 MATCH x88000000/mask=xbfe08000\n# CONSTRUCT x88000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x88000000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stxr Rs_GPR32, Rt_GPR32, addrReg\nis size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\t*addrReg = Rt_GPR32;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.351 STXRB page C6-1931 line 113368 MATCH x08000000/mask=xffe08000\n# CONSTRUCT x08000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x08000000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stxrb Rs_GPR32, Rt_GPR32, addrReg\nis size.ldstr=0 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\tlocal tmp:4 = Rt_GPR32;\n\t*addrReg = tmp:1;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.352 STXRH page C6-1933 line 113496 MATCH x48000000/mask=xffe08000\n# CONSTRUCT x48000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x48000000/mask=xffe08000 --status nomem\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:stxrh Rs_GPR32, Rt_GPR32, addrReg\nis size.ldstr=1 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64\n{\n\tstatus:1 = 1;\n\trsize:1 = 16;\n\tcheck:1 = ExclusiveMonitorPass(addrReg, rsize);\n\tif (!check) goto ;\n\tlocal tmp:4 = Rt_GPR32;\n\t*addrReg = tmp:2;\n\tstatus = ExclusiveMonitorsStatus();\n\n\tRs_GPR64 = zext(status);\n}\n\n# C6.2.356 SUB (extended register) page C6-1940 line 113972 MATCH x4b200000/mask=x7fe00000\n# CONSTRUCT x4b200000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x4b200000/mask=xffe00000 --status pass\n\n:sub Rd_GPR32wsp, Rn_GPR32wsp, ExtendRegShift32\nis sf=0 & op=1 & S=0 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_2:4 = ExtendRegShift32;\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.356 SUB (extended register) page C6-1940 line 113972 MATCH x4b200000/mask=x7fe00000\n# CONSTRUCT xcb200000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xcb200000/mask=xffe00000 --status pass\n\n:sub Rd_GPR64xsp, Rn_GPR64xsp, ExtendRegShift64\nis sf=1 & op=1 & S=0 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp_2:8 = ExtendRegShift64;\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# CONSTRUCT x51000000/mask=xdf000000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x51000000/mask=xdf000000 --status pass --comment \"flags\"\n\n:sub^SBIT_CZNO Rd_GPR32xsp, Rn_GPR32xsp, ImmShift32\nis sf=0 & b_30=1 & S & SBIT_CZNO & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp\n{\n\tsubflags(Rn_GPR32xsp, ImmShift32);\n\ttmp:4 = Rn_GPR32xsp - ImmShift32;\n\tresultflags(tmp);\n\tbuild SBIT_CZNO;\n\tRd_GPR64xsp = zext(tmp);\n}\n\n# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# CONSTRUCT xd1000000/mask=xdf000000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xd1000000/mask=xdf000000 --status pass --comment \"flags\"\n\n:sub^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ImmShift64\nis sf=1 & b_30=1 & S & SBIT_CZNO & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\tsubflags(Rn_GPR64xsp, ImmShift64);\n\tRd_GPR64xsp = Rn_GPR64xsp - ImmShift64;\n\tresultflags(Rd_GPR64xsp);\n\tbuild SBIT_CZNO;\n}\n\n# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000\n# CONSTRUCT x51000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x51000000/mask=xffc00000 --status pass\n\n:sub Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0\nis sf=0 & op=1 & S=0 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl0;\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000\n# CONSTRUCT x51400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x51400000/mask=xffc00000 --status pass\n\n:sub Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12\nis sf=0 & op=1 & S=0 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12;\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tRd_GPR64xsp = zext(tmp_1);\n}\n\n# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000\n# CONSTRUCT xd1000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd1000000/mask=xffc00000 --status pass\n\n:sub Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0\nis sf=1 & op=1 & S=0 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0;\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000\n# CONSTRUCT xd1400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd1400000/mask=xffc00000 --status pass\n\n:sub Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12\nis sf=1 & op=1 & S=0 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12;\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tRd_GPR64xsp = tmp_1;\n}\n\n# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000\n# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0\n# CONSTRUCT x4b000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x4b000000/mask=xff200000 --status pass\n\n:sub Rd_GPR32, Rn_GPR32, RegShift32\nis sf=0 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32;\n\ttmp_1:4 = Rn_GPR32 - tmp_2;\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000\n# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0\n# CONSTRUCT xcb000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xcb000000/mask=xff200000 --status pass\n\n:sub Rd_GPR64, Rn_GPR64, RegShift64\nis sf=1 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64\n{\n\ttmp_2:8 = RegShift64;\n\ttmp_1:8 = Rn_GPR64 - tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000\n# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f\n# CONSTRUCT x6b200000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x6b200000/mask=xffe00000 --status pass --comment \"flags\"\n\n:subs Rd_GPR32, Rn_GPR32wsp, ExtendRegShift32\nis sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = ExtendRegShift32;\n\tsubflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectflags();\n}\n\n# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# CONSTRUCT xeb000000/mask=xffc00000 MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst xeb000000/mask=xffc00000 --status pass --comment \"flags\"\n\n:subs Rd_GPR64, Rn_GPR64xsp, ExtendRegShift64\nis sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64\n{\n\ttmp_2:8 = ExtendRegShift64;\n\tsubflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectflags();\n}\n\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# CONSTRUCT x71000000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x71000000/mask=xffc00000 --status pass --comment \"flags\"\n\n:subs Rd_GPR32, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0\nis sf=0 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl0;\n\tsubflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectflags();\n}\n\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# CONSTRUCT x71400000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x71400000/mask=xffc00000 --status pass --comment \"flags\"\n\n:subs Rd_GPR32, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12\nis sf=0 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12;\n\tsubflags(Rn_GPR32wsp, tmp_2);\n\ttmp_1:4 = Rn_GPR32wsp - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectflags();\n}\n\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# CONSTRUCT xf1000000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf1000000/mask=xffc00000 --status pass --comment \"flags\"\n\n:subs Rd_GPR64, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0\nis sf=1 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd_GPR64\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0;\n\tsubflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectflags();\n}\n\n# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000\n# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f\n# CONSTRUCT xf1400000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf1400000/mask=xffc00000 --status pass --comment \"flags\"\n\n:subs Rd_GPR64, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12\nis sf=1 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd_GPR64\n{\n\ttmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12;\n\tsubflags(Rn_GPR64xsp, tmp_2);\n\ttmp_1:8 = Rn_GPR64xsp - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectflags();\n}\n\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# CONSTRUCT x6b000000/mask=xff200000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst x6b000000/mask=xff200000 --status pass\n\n:subs Rd_GPR32, Rn_GPR32, RegShift32\nis sf=0 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp_2:4 = RegShift32;\n\tsubflags(Rn_GPR32, tmp_2);\n\ttmp_1:4 = Rn_GPR32 - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = zext(tmp_1);\n\taffectflags();\n}\n\n# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000\n# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f\n# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0\n# CONSTRUCT xeb000000/mask=xff200000 MATCHED 3 DOCUMENTED OPCODES\n# AUNIT --inst xeb000000/mask=xff200000 --status pass\n\n:subs Rd_GPR64, Rn_GPR64, RegShift64\nis sf=1 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64 & Rd\n{\n\ttmp_2:8 = RegShift64;\n\tsubflags(Rn_GPR64, tmp_2);\n\ttmp_1:8 = Rn_GPR64 - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\taffectflags();\n}\n\n# C6.2.365 SVC page C6-1957 line 114930 MATCH xd4000001/mask=xffe0001f\n# CONSTRUCT xd4000001/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd4000001/mask=xffe0001f --status nodest\n\n:svc imm16\nis b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=1\n{\n\tCallSupervisor(imm16:2);\n}\n\n# C6.2.366 SWPB, SWPAB, SWPALB, SWPLB page C6-1958 line 114973 MATCH x38208000/mask=xff20fc00\n# CONSTRUCT x38208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x38208000/mask=xff20fc00 --status nomem\n\n# size=0b00 (3031)\n\n:swp^ls_lor^\"b\" aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b00 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data1 & ls_mem1 & aa_Ws & Rn_GPR64xsp\n{ build ls_loa; build ls_data1; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; aa_Wt = tmp_ldWn; build ls_lor; }\n\n# C6.2.367 SWPH, SWPAH, SWPALH, SWPLH page C6-1960 line 115079 MATCH x78208000/mask=xff20fc00\n# CONSTRUCT x78208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x78208000/mask=xff20fc00 --status nomem\n\n# size=0b01 (3031)\n\n:swp^ls_lor^\"h\" aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b01 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data2 & ls_mem2 & aa_Ws & Rn_GPR64xsp\n{ build ls_loa; build ls_data2; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; aa_Wt = tmp_ldWn; build ls_lor; }\n\n# C6.2.368 SWP, SWPA, SWPAL, SWPL page C6-1962 line 115186 MATCH xb8208000/mask=xbf20fc00\n# CONSTRUCT xb8208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xb8208000/mask=xff20fc00 --status nomem\n\n# size=0b10 (3031)\n\n:swp^ls_lor aa_Ws, aa_Wt, [Rn_GPR64xsp]\nis b_3031=0b10 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data4 & ls_mem4 & aa_Ws & Rn_GPR64xsp\n{ build ls_loa; build ls_data4; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; aa_Wt = tmp_ldWn; build ls_lor; }\n\n# C6.2.368 SWP, SWPA, SWPAL, SWPL page C6-1962 line 115186 MATCH xb8208000/mask=xbf20fc00\n# CONSTRUCT xf8208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xf8208000/mask=xff20fc00 --status nomem\n\n# size=0b11 (3031)\n\n:swp^ls_lor aa_Xs, aa_Xt, [Rn_GPR64xsp]\nis b_3031=0b11 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Xt & ls_data8 & ls_mem8 & aa_Xs & Rn_GPR64xsp\n{ build ls_loa; build ls_data8; ls_opc_swp(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; aa_Xt = tmp_ldXn; build ls_lor; }\n\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x93401c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x93401c00/mask=xfffffc06 --status pass\n\n# Special case of sbfm where imms='000111' and immr='000000'\n\n:sxtb Rd_GPR64, Rn_GPR32\nis ImmR=0x0 & ImmS=0x7 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\ttmp_byte:1 = tmp:1;\n\tresult:8 = sext(tmp_byte);\n\tRd_GPR64 = result;\n}\n\n# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x13001c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x13001c00/mask=xfffffc06 --status pass\n\n# Special case of sbfm when ImmS=7 and ImmR=0. Note that this implies ImmS > ImmR-1\n# Otherwise, this might appear to conflict with sbfiz\n\n:sxtb Rd_GPR32, Rn_GPR32\nis ImmR=0x0 & ImmS=0x7 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\ttmp_byte:1 = tmp:1;\n\tresult:4 = sext(tmp_byte);\n\tRd_GPR64 = zext(result);\n}\n\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x93403c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x93403c00/mask=xfffffc06 --status pass\n\n# Special case of sbfm where imms='001111' and immr='000000'\n\n:sxth Rd_GPR64, Rn_GPR32\nis ImmR=0x0 & ImmS=0xf & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\ttmp_1:2 = tmp:2;\n\ttmp_2:8 = sext(tmp_1);\n\tRd_GPR64 = tmp_2;\n}\n\n# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x13003c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES\n# AUNIT --inst x13003c00/mask=xfffffc06 --status pass\n\n# Special case of sbfm where imms='001111' and immr='000000'\n\n:sxth Rd_GPR32, Rn_GPR32\nis ImmR=0x0 & ImmS=0xf & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\ttmp_1:2 = tmp:2;\n\ttmp_2:4 = sext(tmp_1);\n\tRd_GPR64 = zext(tmp_2);\n}\n\n# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00\n# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00\n# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000\n# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000\n# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000\n# CONSTRUCT x93407c00/mask=xfffffc06 MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst x93407c00/mask=xfffffc06 --status pass\n\n# Special case of sbfm where imms='011111' and immr='000000'\n\n:sxtw Rd_GPR64, Rn_GPR32\nis ImmR=0x0 & ImmS=0x1f & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\tRd_GPR64 = sext(tmp);\n}\n\n# C6.2.286 SYS page C6-979 line 56782 KEEPWITH\n\nSysArgs: Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3, Rt_GPR64 is Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt & Rt_GPR64 { export Rt_GPR64; }\nSysArgs: Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3 is Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt=31 & Rt_GPR64 { export 0:8; }\n\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00\n# C6.2.39 BRB page C6-1212 line 71361 MATCH xd5097200/mask=xffffff00\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# CONSTRUCT xd5080000/mask=xfff80000 MATCHED 6 DOCUMENTED OPCODES\n# AUNIT --inst xd5080000/mask=xfff80000 --status nodest\n\n:sys SysArgs\nis b_1931=0b1101010100001 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & SysArgs\n{\n\ttmp1:4 = Op1_uimm3;\n\ttmp2:4 = CRn_CRx;\n\ttmp3:4 = CRm_CRx;\n\ttmp4:4 = Op2_uimm3;\n\tSysOp_W(tmp1, tmp2, tmp3, tmp4, SysArgs);\n}\n\n# C6.2.373 SYSL page C6-1971 line 115652 MATCH xd5280000/mask=xfff80000\n# CONSTRUCT xd5280000/mask=xfff80000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd5280000/mask=xfff80000 --status nodest\n\n:sysl Rt_GPR64, Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3\nis b_2431=0xd5 & b_2223=0 & l=1 & Op0=1 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt & Rt_GPR64\n{\n\ttmp1:4 = Op1_uimm3;\n\ttmp2:4 = CRn_CRx;\n\ttmp3:4 = CRm_CRx;\n\ttmp4:4 = Op2_uimm3;\n\tRt_GPR64 = SysOp_R(tmp1, tmp2, tmp3, tmp4);\n}\n\n# C6.2.373 SYSL page C6-1971 line 115652 MATCH xd5280000/mask=xfff80000\n# CONSTRUCT xd528001f/mask=xfff8001f MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xd528001f/mask=xfff8001f --status nodest\n\n:sysl Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3\nis b_2431=0xd5 & b_2223=0 & l=1 & Op0=1 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt=31 & Rt_GPR64\n{\n\ttmp1:4 = Op1_uimm3;\n\ttmp2:4 = CRn_CRx;\n\ttmp3:4 = CRm_CRx;\n\ttmp4:4 = Op2_uimm3;\n\tSysOp_R(tmp1, tmp2, tmp3, tmp4);\n}\n\n# C6.2.374 TBNZ page C6-1972 line 115708 MATCH x37000000/mask=x7f000000\n# C6.2.375 TBZ page C6-1973 line 115766 MATCH x36000000/mask=x7f000000\n# CONSTRUCT xb6000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xb6000000/mask=xfe000000 --status nodest\n\n:tb^ZeroOp Rd_GPR64, BitPos, Addr14\nis sf=1 & b_2530=0x1b & BitPos & ZeroOp & Addr14 & Rd_GPR64\n{\n\ttmp:1 = BitPos;\n\tif (tmp == ZeroOp) goto Addr14;\n}\n\n# C6.2.374 TBNZ page C6-1972 line 115708 MATCH x37000000/mask=x7f000000\n# C6.2.375 TBZ page C6-1973 line 115766 MATCH x36000000/mask=x7f000000\n# CONSTRUCT x36000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x36000000/mask=xfe000000 --status nodest\n\n:tb^ZeroOp Rd_GPR32, BitPos, Addr14\nis sf=0 & b_2530=0x1b & BitPos & ZeroOp & Addr14 & Rd_GPR32\n{\n\ttmp:1 = BitPos;\n\tif (tmp == ZeroOp) goto Addr14;\n}\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8020/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8020/mask=xffffffe0 --status nodest\n\n:tlbi \"IPAS2E1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0000 & b_0507=0b001 & Rt_GPR64\n{ TLBI_IPAS2E1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c80a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c80a0/mask=xffffffe0 --status nodest\n\n:tlbi \"IPAS2LE1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0000 & b_0507=0b101 & Rt_GPR64\n{ TLBI_IPAS2LE1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088300/mask=xffffffe0 --status nodest\n\n:tlbi \"VMALLE1IS\"\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000\n{ TLBI_VMALLE1IS(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8300/mask=xffffffe0 --status nodest\n\n:tlbi \"ALLE2IS\"\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000\n{ TLBI_ALLE2IS(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e8300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50e8300/mask=xffffffe0 --status nodest\n\n:tlbi \"ALLE3IS\"\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000\n{ TLBI_ALLE3IS(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088320/mask=xffffffe0 --status nodest\n\n:tlbi \"VAE1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64\n{ TLBI_VAE1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8320/mask=xffffffe0 --status nodest\n\n:tlbi \"VAE2IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64\n{ TLBI_VAE2IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e8320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50e8320/mask=xffffffe0 --status nodest\n\n:tlbi \"VAE3IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64\n{ TLBI_VAE3IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088340/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088340/mask=xffffffe0 --status nodest\n\n:tlbi \"ASIDE1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b010 & Rt_GPR64\n{ TLBI_ASIDE1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088360/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088360/mask=xffffffe0 --status nodest\n\n:tlbi \"VAAE1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b011 & Rt_GPR64\n{ TLBI_VAAE1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8380/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8380/mask=xffffffe0 --status nodest\n\n:tlbi \"ALLE1IS\"\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b100\n{ TLBI_ALLE1IS(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50883a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50883a0/mask=xffffffe0 --status nodest\n\n:tlbi \"VALE1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64\n{ TLBI_VALE1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c83a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c83a0/mask=xffffffe0 --status nodest\n\n:tlbi \"VALE2IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64\n{ TLBI_VALE2IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e83a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50e83a0/mask=xffffffe0 --status nodest\n\n:tlbi \"VALE3IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64\n{ TLBI_VALE3IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c83c0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c83c0/mask=xffffffe0 --status nodest\n\n:tlbi \"VMALLS12E1IS\"\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b110\n{ TLBI_VMALLS12E1IS(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50883e0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50883e0/mask=xffffffe0 --status nodest\n\n:tlbi \"VAALE1IS\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b111 & Rt_GPR64\n{ TLBI_VAALE1IS(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8420/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8420/mask=xffffffe0 --status nodest\n\n:tlbi \"IPAS2E1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0100 & b_0507=0b001 & Rt_GPR64\n{ TLBI_IPAS2E1(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c84a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c84a0/mask=xffffffe0 --status nodest\n\n:tlbi \"IPAS2LE1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0100 & b_0507=0b101 & Rt_GPR64\n{ TLBI_IPAS2LE1(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088700/mask=xffffffe0 --status nodest\n\n:tlbi \"VMALLE1\"\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000\n{ TLBI_VMALLE1(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8700/mask=xffffffe0 --status nodest\n\n:tlbi \"ALLE2\"\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000\n{ TLBI_ALLE2(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e8700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50e8700/mask=xffffffe0 --status nodest\n\n:tlbi \"ALLE3\"\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000\n{ TLBI_ALLE3(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088720/mask=xffffffe0 --status nodest\n\n:tlbi \"VAE1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64\n{ TLBI_VAE1(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8720/mask=xffffffe0 --status nodest\n\n:tlbi \"VAE2\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64\n{ TLBI_VAE2(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e8720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50e8720/mask=xffffffe0 --status nodest\n\n:tlbi \"VAE3\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64\n{ TLBI_VAE3(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088740/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088740/mask=xffffffe0 --status nodest\n\n:tlbi \"ASIDE1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b010 & Rt_GPR64\n{ TLBI_ASIDE1(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5088760/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd5088760/mask=xffffffe0 --status nodest\n\n:tlbi \"VAAE1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b011 & Rt_GPR64\n{ TLBI_VAAE1(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c8780/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c8780/mask=xffffffe0 --status nodest\n\n:tlbi \"ALLE1\"\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b100\n{ TLBI_ALLE1(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50887a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50887a0/mask=xffffffe0 --status nodest\n\n:tlbi \"VALE1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64\n{ TLBI_VALE1(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c87a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c87a0/mask=xffffffe0 --status nodest\n\n:tlbi \"VALE2\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64\n{ TLBI_VALE2(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50e87a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50e87a0/mask=xffffffe0 --status nodest\n\n:tlbi \"VALE3\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64\n{ TLBI_VALE3(Rt_GPR64); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50c87c0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50c87c0/mask=xffffffe0 --status nodest\n\n:tlbi \"VMALLS12E1\"\nis b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b110\n{ TLBI_VMALLS12E1(); }\n\n# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50887e0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50887e0/mask=xffffffe0 --status nodest\n\n:tlbi \"VAALE1\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b111 & Rt_GPR64\n{ TLBI_VAALE1(Rt_GPR64); }\n\n# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f\n# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000\n# CONSTRUCT x7200001f/mask=xff80001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x7200001f/mask=xff80001f --status pass --comment \"flags\"\n\n:tst Rn_GPR32, DecodeWMask32\nis sf=0 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd=0x1f\n{\n\ttmp_2:4 = DecodeWMask32;\n\ttmp_1:4 = Rn_GPR32 & tmp_2;\n\tresultflags(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f\n# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000\n# CONSTRUCT xf200001f/mask=xff80001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xf200001f/mask=xff80001f --status pass --comment \"flags\"\n\n:tst Rn_GPR64, DecodeWMask64\nis sf=1 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd=0x1f\n{\n\ttmp_2:8 = DecodeWMask64;\n\ttmp_1:8 = Rn_GPR64 & tmp_2;\n\tresultflags(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f\n# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000\n# CONSTRUCT x6a00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x6a00001f/mask=xff20001f --status pass --comment \"flags\"\n\n:tst Rn_GPR32, RegShift32Log\nis sf=0 & opc=3 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd=0x1f\n{\n\ttmp_2:4 = RegShift32Log;\n\ttmp_1:4 = Rn_GPR32 & tmp_2;\n\tresultflags(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f\n# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000\n# CONSTRUCT xea00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xea00001f/mask=xff20001f --status pass --comment \"flags\"\n\n:tst Rn_GPR64, RegShift64Log\nis sf=1 & opc=3 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd=0x1f\n{\n\ttmp_2:8 = RegShift64Log;\n\ttmp_1:8 = Rn_GPR64 & tmp_2;\n\tresultflags(tmp_1);\n\taffectLflags();\n}\n\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00\n# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00\n# CONSTRUCT x53000008/mask=xffe0800c MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x53000008/mask=xffe0800c --status pass\n# Special case of ubfm where UInt(imms) < UInt(immr).\n# Note because LSL is preferred where imms + 1 == immr, we use ImmS_LT_ImmR_minus_1\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:ubfiz Rd_GPR32, Rn_GPR32, ubfiz_lsb, ubfiz_width\nis ImmS_LT_ImmR_minus_1=1 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ubfiz_lsb & ubfiz_width & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32\n{\n\tlocal wmask:4 = DecodeWMask32;\n\tlocal tmask:4 = DecodeTMask32;\n\tlocal src:4 = Rn_GPR32;\n\tlocal bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;\n\tRd_GPR64 = zext(bot & tmask);\n}\n\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT xd340000a/mask=xffc0000a MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst xd340000a/mask=xffc0000a --status pass\n# Special case of ubfm where UInt(imms) < UInt(immr).\n# Note because LSL is preferred where imms + 1 == immr, we use ImmS_LT_ImmR_minus_1\n\n:ubfiz Rd_GPR64, Rn_GPR64, ubfiz_lsb64, ubfiz_width\nis ImmS_LT_ImmR_minus_1=1 & ImmS_LT_ImmR=1 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & ImmRConst64 & ubfiz_lsb64 & ubfiz_width & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64\n{\n\tlocal wmask:8 = DecodeWMask64;\n\tlocal tmask:8 = DecodeTMask64;\n\tlocal src:8 = Rn_GPR64;\n\tlocal bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;\n\tRd_GPR64 = bot & tmask;\n}\n\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00\n# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00\n# CONSTRUCT x53000000/mask=xffe08000 MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x53000000/mask=xffe08000 --status pass\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:ubfm Rd_GPR32, Rn_GPR32, ImmRConst32, ImmSConst32\nis sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32\n{\n\tlocal wmask:4 = DecodeWMask32;\n\tlocal tmask:4 = DecodeTMask32;\n\tlocal src:4 = Rn_GPR32;\n\tlocal bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;\n\tRd_GPR64 = zext(bot & tmask);\n}\n\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT xd3400000/mask=xffc00000 MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst xd3400000/mask=xffc00000 --status pass\n\n:ubfm Rd_GPR64, Rn_GPR64, ImmRConst64, ImmSConst64\nis sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & ImmRConst64 & ImmSConst64 & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64\n{\n\tlocal wmask:8 = DecodeWMask64;\n\tlocal tmask:8 = DecodeTMask64;\n\tlocal src:8 = Rn_GPR64;\n\tlocal bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;\n\tRd_GPR64 = bot & tmask;\n}\n\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00\n# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00\n# CONSTRUCT x53000010/mask=xffe0801a MATCHED 7 DOCUMENTED OPCODES\n# AUNIT --inst x53000010/mask=xffe0801a --status pass\n# Special case of ubfm as determined by BFXPreferred()\n# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();\n\n:ubfx Rd_GPR32, Rn_GPR32, ImmRConst32, ubfx_width\nis ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmRConst32 & ubfx_width & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32\n{\n\tlocal wmask:4 = DecodeWMask32;\n\tlocal tmask:4 = DecodeTMask32;\n\tlocal src:4 = Rn_GPR32;\n\tlocal bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;\n\tRd_GPR64 = zext(bot & tmask);\n}\n\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# CONSTRUCT xd3400020/mask=xffc0002a MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst xd3400020/mask=xffc0002a --status pass\n\n# Special case of ubfm as determined by BFXPreferred()\n\n:ubfx Rd_GPR64, Rn_GPR64, ImmRConst64, ubfx_width\nis ImmS_ne_3f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmRConst64 & ubfx_width & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64\n{\n\tlocal wmask:8 = DecodeWMask64;\n\tlocal tmask:8 = DecodeTMask64;\n\tlocal src:8 = Rn_GPR64;\n\tlocal bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;\n\tRd_GPR64 = bot & tmask;\n}\n\n# C6.2.388 UDIV page C6-1994 line 116786 MATCH x1ac00800/mask=x7fe0fc00\n# CONSTRUCT x1ac00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x1ac00800/mask=xffe0fc00 --status pass\n\n:udiv Rd_GPR32, Rn_GPR32, Rm_GPR32\nis sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x2 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp_1:4 = 0;\n\tif (Rm_GPR32 == 0) goto ;\n\ttmp_1 = Rn_GPR32 / Rm_GPR32;\n\n\tRd_GPR64 = zext(tmp_1);\n}\n\n# C6.2.388 UDIV page C6-1994 line 116786 MATCH x1ac00800/mask=x7fe0fc00\n# CONSTRUCT x9ac00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9ac00800/mask=xffe0fc00 --status pass\n\n:udiv Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x2 & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmp_1:8 = 0;\n\tif (Rm_GPR64 == 0) goto ;\n\ttmp_1 = Rn_GPR64 / Rm_GPR64;\n\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.389 UMADDL page C6-1995 line 116855 MATCH x9ba00000/mask=xffe08000\n# CONSTRUCT x9ba00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9ba00000/mask=xffe08000 --status pass\n\n:umaddl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = zext(Rn_GPR32);\n\ttmp_4:8 = zext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\ttmp_1:8 = Ra_GPR64 + tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.390 UMNEGL page C6-1997 line 116945 MATCH x9ba0fc00/mask=xffe0fc00\n# C6.2.391 UMSUBL page C6-1998 line 117009 MATCH x9ba08000/mask=xffe08000\n# CONSTRUCT x9ba0fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ba0fc00/mask=xffe0fc00 --status pass\n\n:umnegl Rd_GPR64, Rn_GPR32, Rm_GPR32\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = zext(Rn_GPR32);\n\ttmp_4:8 = zext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\ttmp_1:8 = - tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.391 UMSUBL page C6-1998 line 117009 MATCH x9ba08000/mask=xffe08000\n# CONSTRUCT x9ba08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9ba08000/mask=xffe08000 --status pass\n\n:umsubl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = zext(Rn_GPR32);\n\ttmp_4:8 = zext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\ttmp_1:8 = Ra_GPR64 - tmp_2;\n\tRd_GPR64 = tmp_1;\n}\n\n# C6.2.392 UMULH page C6-2000 line 117098 MATCH x9bc00000/mask=xffe08000\n# CONSTRUCT x9bc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst x9bc00000/mask=xffe08000 --status pass\n# To enforce SHOULD BE ONE fields add: b_1014=0b11111\n\n:umulh Rd_GPR64, Rn_GPR64, Rm_GPR64\nis sf=1 & op.dp3=0 & b_2428=0x1b & op.dp3_op31=6 & Rm_GPR64 & op.dp3_o0=0 & Ra & Rn_GPR64 & Rd_GPR64\n{\n\tlocal tmpq:16 = zext(Rn_GPR64) * zext(Rm_GPR64);\n\tRd_GPR64 = tmpq(8);\n}\n\n# C6.2.393 UMULL page C6-2001 line 117165 MATCH x9ba07c00/mask=xffe0fc00\n# C6.2.389 UMADDL page C6-1995 line 116855 MATCH x9ba00000/mask=xffe08000\n# CONSTRUCT x9ba07c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst x9ba07c00/mask=xffe0fc00 --status pass\n\n:umull Rd_GPR64, Rn_GPR32, Rm_GPR32\nis sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR64\n{\n\ttmp_3:8 = zext(Rn_GPR32);\n\ttmp_4:8 = zext(Rm_GPR32);\n\ttmp_2:8 = tmp_3 * tmp_4;\n\tRd_GPR64 = tmp_2;\n}\n\n# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT x53001c10/mask=xfffffc1e MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst x53001c10/mask=xfffffc1e --status pass\n\n# Alias for ubfm where immr=='000000' and imms='000111'\n# These imply things about the inequalities\n\n:uxtb Rd_GPR32, Rn_GPR32\nis ImmR=0x0 & ImmS=0x7 & ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\tRd_GPR64 = zext(tmp:1);\n}\n\n# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00\n# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000\n# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000\n# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000\n# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000\n# CONSTRUCT x53003c10/mask=xfffffc1e MATCHED 5 DOCUMENTED OPCODES\n# AUNIT --inst x53003c10/mask=xfffffc1e --status pass\n\n# Alias for ubfm where immr=='000000' and imms='001111'\n# These imply things about the inequalities\n\n:uxth Rd_GPR32, Rn_GPR32\nis ImmR=0x0 & ImmS=0x0f & ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64\n{\n\ttmp:4 = Rn_GPR32;\n\tRd_GPR64 = zext(tmp:2);\n}\n\n# C6.2.396 WFE page C6-2004 line 117348 MATCH xd503205f/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503205f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503205f/mask=xffffffff --status nodest\n\n:wfe\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=2 & Rt=0x1f\n{\n\tWaitForEvent();\n}\n\n# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0\n# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=110101010000001100010000000.....\n\n:wfet Rd_GPR64\nis b_0531=0x6a81880 & Rd_GPR64\n{\n\tWaitForEvent(Rd_GPR64);\n}\n\n# C6.2.398 WFI page C6-2006 line 117439 MATCH xd503207f/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503207f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503207f/mask=xffffffff --status nodest\n\n:wfi\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=3 & Rt=0x1f\n{\n\tWaitForInterrupt();\n}\n\n# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0\n# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=110101010000001100010000001.....\n\n:wfit Rd_GPR64\nis b_0531=0x6a81881 & Rd_GPR64\n{\n\tWaitForInterrupt(Rd_GPR64);\n}\n\n# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0\n# CONSTRUCT xdac147e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac147e0/mask=xffffffe0 --status noqemu\n# D == 1 XPACD variant\n\n:xpacd Rd_GPR64\nis xpacd__PACpart & b_1131=0b110110101100000101000 & b_0509=0b11111 & b_10=1 & Rd_GPR64\n{\n\tbuild xpacd__PACpart;\n}\n\n# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0\n# CONSTRUCT xdac143e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES\n# AUNIT --inst xdac143e0/mask=xffffffe0 --status noqemu\n# D == 0 XPACI variant\n\n:xpaci Rd_GPR64\nis xpaci__PACpart & b_1131=0b110110101100000101000 & b_0509=0b11111 & b_10=0 & Rd_GPR64\n{\n\tbuild xpaci__PACpart;\n}\n\n# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xd50320ff/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd50320ff/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd50320ff/mask=xffffffff --status nodest\n# System variant\n\n:xpaclri\nis xpaclri__PACpart & b_0031=0b11010101000000110010000011111111\n{\n\tbuild xpaclri__PACpart;\n}\n\n# C6.2.402 YIELD page C6-2011 line 117656 MATCH xd503203f/mask=xffffffff\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503203f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES\n# AUNIT --inst xd503203f/mask=xffffffff --status nodest\n\n:yield\nis b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=1 & Rt=0x1f\n{\n\tYield();\n}\n\n# C6.2.6 ADDG page C6-787 line 46877 MATCH KEEPWITH\n\nwith : ShowMemTag=1 {\n\n# C6.2.6 ADDG page C6-1155 line 68448 MATCH x91800000/mask=xffc00000\n# CONSTRUCT x91800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n\n:addg Rd_GPR64xsp, Rn_GPR64xsp, \"#\"^shifted_imm, \"#\"^b_1013\nis sf=1 & op=0 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp\n# \" & b_1415=0\" is not required by the spec (op3 doesn't have any requirements and is not used)\n[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]\n{\n\t# we don't actually modify the target register, so Ghidra understands the pointer target is still the same.\n\t# pseudo-ops let us do that, but it means that the decompiler can put an unintuitive value in the\n\t# \"CopyPtrTag_AddToPtrTag_Exclude\" argument, e.g. \"param_2 + 0x20\".\n\tuimm4:1 = b_1013;\n\texclude:2 = 0;\n\tOr2BytesWithExcludedTags(exclude);\n\tRd_GPR64xsp = Rn_GPR64xsp + shifted_imm;\n\tCopyPtrTag_AddToPtrTag_Exclude(Rd_GPR64xsp, Rn_GPR64xsp, uimm4, exclude);\n}\n\n}\n\n# C6.2.6 ADDG page C6-787 line 44223 KEEPWITH\nwith : ShowMemTag=0 {\n\n# C6.2.6 ADDG page C6-1155 line 68448 MATCH x91800000/mask=xffc00000\n# CONSTRUCT x91800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n\n:addg Rd_GPR64xsp, Rn_GPR64xsp, \"#\"^shifted_imm, \"#\"^b_1013\nis sf=1 & op=0 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp\n# \" & b_1415=0\" is not required by the spec (op3 doesn't have any requirements and is not used)\n[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]\n{\n\tRd_GPR64xsp = Rn_GPR64xsp + shifted_imm;\n}\n\n}\n\n\n# C6.2.24 AXFLAG page C6-1189 line 70222 MATCH xd500405f/mask=xfffff0ff\n# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f\n# CONSTRUCT xd500405f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES\n# To enforce SHOULD BE ZERO fields add: b_0811=0b0000\n:axflag\nis b_1231=0b11010101000000000100 & b_0007=0b01011111\n{\n\ttmpZR = ZR | OV;\n\ttmpCY = CY & !OV;\n\n\tNG = 0;\n\tZR = tmpZR;\n\tCY = tmpCY;\n\tOV = 0;\n}\n\n# C6.2.41 BTI page C6-1214 line 71457 MATCH xd503241f/mask=xffffff3f\n# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f\n# CONSTRUCT xd503241f/mask=xffffff1f MATCHED 2 DOCUMENTED OPCODES\n\n:bti BTI_BTITARGETS\nis BTI_BTITARGETS & b_1231=0xd5032 & b_0811=4 & b_0004=0x1f\n{\n\t# This instruction is a valid target for jumps, calls, or both; see the BTI_BTITARGETS table.\n}\n\n# C6.2.53 CFP page C6-1237 line 72667 MATCH xd50b7380/mask=xffffffe0\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7380/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n\n:cfp \"RCTX\", Rt_GPR64\nis b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=4 & Rt_GPR64\n{\n\tControlFlowPredictionRestrictionByContext(Rt_GPR64);\n}\n\n\n# C6.2.65 CMPP page C6-1258 line 73720 MATCH xbac0001f/mask=xffe0fc1f\n# C6.2.361 SUBPS page C6-1949 line 114470 MATCH xbac00000/mask=xffe0fc00\n# CONSTRUCT xbac0001f/mask=xffe0fc1f MATCHED 2 DOCUMENTED OPCODES\n# CMPP: Compare Pointers\n# Compare two pointer 56-bit pointer values and set flags\n:cmpp Rn_GPR64xsp, Rm_GPR64xsp\nis sf=1 & b_30=0 & S=1 & b_2128=0b11010110 & Rm_GPR64xsp & b_1015=0b000000 & Rd=0b11111 & Rn_GPR64xsp\n{\n\t# out of a 64-bit value, keep the lowest 56 bits, which is 7 bytes.\n\t# sign-extend a 7-byte value to an 8-byte value. If the boundary weren't byte-aligned,\n\t# sext() wouldn't work so well.\n\ttmp_2:8 = Rm_GPR64xsp;\n\ttmp_2 = sext(tmp_2:7); # if Rm:7 is used here, the decompiler considers the Rm register an int7 for the whole function.\n\ttmp_1:8 = Rn_GPR64xsp;\n\ttmp_1 = sext(tmp_1:7);\n\tsubflags(tmp_1, tmp_2);\n\ttmp_1 = tmp_1 - tmp_2;\n\tresultflags(tmp_1);\n\taffectflags();\n}\n\n\n# C6.2.67 CPP page C6-1261 line 73861 MATCH xd50b73e0/mask=xffffffe0\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b73e0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n\n:cpp \"RCTX\", Rt_GPR64\nis b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=7 & Rt_GPR64\n{\n\tCachePrefetchPredictionRestrictionByContext(Rt_GPR64);\n}\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087660/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n# the new DC instruction types from ARMv8.5\n\n:dc \"IGVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b011 & Rt_GPR64\n{ DC_IGVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087680/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"IGSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b100 & Rt_GPR64\n{ DC_IGSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50876a0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"IGDVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b101 & Rt_GPR64\n{ DC_IGDVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50876c0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"IGDSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b110 & Rt_GPR64\n{ DC_IGDSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087a80/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b100 & Rt_GPR64\n{ DC_CGSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087ac0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGDSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b110 & Rt_GPR64\n{ DC_CGDSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087e80/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CIGSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b100 & Rt_GPR64\n{ DC_CIGSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd5087ec0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CIGDSW\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b110 & Rt_GPR64\n{ DC_CIGDSW(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7460/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"GVA\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b011 & Rt_GPR64\n{ DC_GVA(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7480/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"GZVA\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b100 & Rt_GPR64\n{ DC_GZVA(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7a60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b011 & Rt_GPR64\n{ DC_CGVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7aa0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGDVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b101 & Rt_GPR64\n{ DC_CGDVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7c60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGVAP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b011 & Rt_GPR64\n{ DC_CGVAP(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7ca0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGDVAP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b101 & Rt_GPR64\n{ DC_CGDVAP(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7d60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGVADP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1101 & b_0507=0b011 & Rt_GPR64\n{ DC_CGVADP(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7da0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CGDVADP\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1101 & b_0507=0b101 & Rt_GPR64\n{ DC_CGDVADP(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7e60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CIGVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b011 & Rt_GPR64\n{ DC_CIGVAC(Rt_GPR64); }\n\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b7ea0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES\n\n:dc \"CIGDVAC\", Rt_GPR64\nis b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b101 & Rt_GPR64\n{ DC_CIGDVAC(Rt_GPR64); }\n\n# C6.2.117 DVP page C6-1467 line 87355 MATCH xd50b73a0/mask=xffffffe0\n# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000\n# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000\n# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000\n# CONSTRUCT xd50b73a0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES\n\n:dvp \"RCTX\", Rt_GPR64\nis b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=5 & Rt_GPR64\n{\n\tDataValuePredictionRestrictionByContext(Rt_GPR64);\n}\n\n\n# GMI: Tag Mask Insert\n# Extracts tag from first source register (Xn) and adds as an excluded tag to list of excluded\n# tags in second source register, writing the updated exclusion set to the destination register\n\nwith : ShowMemTag=1 {\n\n# C6.2.125 GMI page C6-1479 line 87976 MATCH x9ac01400/mask=xffe0fc00\n# CONSTRUCT x9ac01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:gmi Rd_GPR64, Rn_GPR64xsp, Rm_GPR64\nis sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & Rm_GPR64 & b_1015=0b000101 & Rn_GPR64xsp & Rd_GPR64\n{\n\t# get tag from address\n\t#tag:8 = (Rn_GPR64xsp >> 56) & 0xf;\n\ttag:8 = 0;\n\tAllocationTagFromAddress(tag, Rn_GPR64xsp);\n\tRd_GPR64 = Rm_GPR64 | (1 << tag);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.125 GMI page C6-1479 line 87976 MATCH x9ac01400/mask=xffe0fc00\n# CONSTRUCT x9ac01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:gmi Rd_GPR64, Rn_GPR64xsp, Rm_GPR64\nis sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & Rm_GPR64 & b_1015=0b000101 & Rn_GPR64xsp & Rd_GPR64\n{\n\t# The only expected use of the output of this instruction is in \"exclude\" arguments, which will be totally ignored\n\t# with ShowMemTag off anyway, so for the sake of more concise code don't set any mask bits at all.\n\tRd_GPR64 = Rm_GPR64;\n}\n\n}\n\n# IRG: Insert Random Tag\n# Generates random tag (honoring excluded tags specified in optional second source register\n# and GCR_EL1.Exclude) into the address from first source register, writing the result to the\n# destination register.\nwith : ShowMemTag=1 {\n\n# C6.2.130 IRG page C6-1485 line 88340 MATCH x9ac01000/mask=xffe0fc00\n# CONSTRUCT x9ac01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:irg Rd_GPR64xsp, Rn_GPR64xsp^OPTIONAL_XM\nis sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & OPTIONAL_XM & b_1015=0b000100 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\ttmp:8 = OPTIONAL_XM;\n\texclude:2 = tmp:2;\n\tOr2BytesWithExcludedTags(exclude);\n\tRd_GPR64xsp = Rn_GPR64xsp;\n\tRandomizePtrTag_Exclude(Rd_GPR64xsp, exclude);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.130 IRG page C6-1485 line 88340 MATCH x9ac01000/mask=xffe0fc00\n# CONSTRUCT x9ac01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:irg Rd_GPR64xsp, Rn_GPR64xsp^OPTIONAL_XM\nis sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & OPTIONAL_XM & b_1015=0b000100 & Rn_GPR64xsp & Rd_GPR64xsp\n{\n\tRd_GPR64xsp = Rn_GPR64xsp;\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.158 LDG page C6-1538 line 91337 MATCH xd9600000/mask=xffe00c00\n# CONSTRUCT xd9600000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldg Rt_GPR64, addr_granuleSIMM\nis b_2131=0b11011001011 & addr_granuleSIMM & b_1011=0b00 & Rt_GPR64\n{\n\ttmp:8 = addr_granuleSIMM;\n\tAlign(tmp, $(TAG_GRANULE));\n\ttag:8 = LoadMemTag(tmp);\n\tSetPtrTag(Rt_GPR64, tag);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.158 LDG page C6-1538 line 91337 MATCH xd9600000/mask=xffe00c00\n# CONSTRUCT xd9600000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldg Rt_GPR64, addr_granuleSIMM\nis b_2131=0b11011001011 & addr_granuleSIMM & b_1011=0b00 & Rt_GPR64\n{\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.159 LDGM page C6-1539 line 91400 MATCH xd9e00000/mask=xfffffc00\n# CONSTRUCT xd9e00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldgm Rt_GPR64, \"[\"^Rn_GPR64xsp^\"]\"\nis b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp\n{\n\tsze:8 = 4 << (gmid_el1 & 0xf); # The value in parentheses (GMID_EL1.BS) varies between 2 and 6.\n\taddress:8 = Rn_GPR64xsp;\n\tAlign(address, sze); # this ensures that address will be granule-aligned, so we don't need to check it\n\tcount:8 = sze >> $(LOG2_TAG_GRANULE);\n\tdata:8 = 0:8; # output value\n\tindex:8 = (address >> $(LOG2_TAG_GRANULE)) & 0xf;\n\t# for tmp = 0 to count-1\n\ttmp:8 = 0;\n\n\ttag:8 = LoadMemTag(address) & 0xf;\n\t\t# The 0xf doesn't do anything to streamline the representation of this\n\t\t# instruction in the decompiler, but it shows the size of a tag.\n\tdata = data | (tag << (index * 4));\n\taddress = address + $(TAG_GRANULE);\n\tindex = index + 1;\n\ttmp = tmp + 1;\n\t# next tmp\n\tif (tmp < count) goto ;\n\tRt_GPR64 = data;\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.159 LDGM page C6-1539 line 91400 MATCH xd9e00000/mask=xfffffc00\n# CONSTRUCT xd9e00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:ldgm Rt_GPR64, \"[\"^Rn_GPR64xsp^\"]\"\nis b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp\n{\n\tdata:8 = 0:8; # output value\n\tRt_GPR64 = data;\n}\n\n}\n\n# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00\n# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=1111100000111111110100..........\n\n# Single-copy Atomic 64-byte Load\n:ld64b Rn_GPR64, [Rt_GPR64xsp]\nis b_1031=0x3e0ff4 & Rn_GPR64 & Rt_GPR64xsp {\n\tRn_GPR64 = *Rt_GPR64xsp;\n}\n\n\n# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00\n# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:st64b Rn_GPR64, [Rt_GPR64xsp]\nis b_1031=0x3e0fe4 & Rn_GPR64 & Rt_GPR64xsp {\n\t*Rt_GPR64xsp = Rn_GPR64;\n}\n\n\n# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00\n# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\ndefine pcodeop store64ByteAtomic;\n:st64bv Rs_GPR64, Rn_GPR64, [Rt_GPR64xsp]\nis b_2131=0x7c1 & Rs_GPR64 & b_1015=0x2c & Rn_GPR64 & Rt_GPR64xsp {\n\t*Rt_GPR64xsp = Rn_GPR64;\n\tRs_GPR64 = store64ByteAtomic(Rn_GPR64, Rt_GPR64xsp);\n}\n\n\n# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00\n# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:st64bv0\nis b_2131=0b11111000001 & Rs_GPR64 & b_1015=0x28 & Rn_GPR64 & Rt_GPR64xsp {\n\tlocal st64bv_addr:8 = (Rt_GPR64xsp & 0xffff0000) | (accdata & 0xffff);\n\t*st64bv_addr = Rn_GPR64;\n\tRs_GPR64 = store64ByteAtomic(Rn_GPR64, st64bv_addr);\n}\n\n\naddrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn=0b11111 & addrGranuleIndexed { export addrGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional\naddrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn & addrGranuleIndexed { tmp:8 = addrGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case\n\naddrPairGranuleIndexed_checkAlignment: addrPairGranuleIndexed is Rn=0b11111 & addrPairGranuleIndexed { export addrPairGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional\naddrPairGranuleIndexed_checkAlignment: addrPairGranuleIndexed is Rn & addrPairGranuleIndexed { tmp:8 = addrPairGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00400/mask=xffe00c00\n# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00c00/mask=xffe00c00\n# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00800/mask=xffe00c00\n# CONSTRUCT xd9a00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:st2g Rt_GPR64xsp, addrGranuleIndexed_checkAlignment\nis b_2131=0b11011001101 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed_checkAlignment\n{\n\t# in case Rt == Rn, get the tag first so any updates in addrGranuleIndexed_checkAlignment don't affect it\n\ttag:8 = 0;\n\tAllocationTagFromAddress(tag, Rt_GPR64xsp);\n\n\tbuild addrGranuleIndexed_checkAlignment;\n\n\t# this instruction throws an alignment fault if address is not granule-aligned\n\taddress:8 = addrGranuleIndexed_checkAlignment;\n\n\tStoreMemTag(address, tag );\n\tStoreMemTag(address + $(TAG_GRANULE), tag );\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00400/mask=xffe00c00\n# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00c00/mask=xffe00c00\n# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00800/mask=xffe00c00\n# CONSTRUCT xd9a00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:st2g Rt_GPR64xsp, addrGranuleIndexed\nis b_2131=0b11011001101 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed\n{\n\t# for the sake of simplified output, omit the alignment check when ShowMemTag is off\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200400/mask=xffe00c00\n# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200c00/mask=xffe00c00\n# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200800/mask=xffe00c00\n# CONSTRUCT xd9200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:stg Rt_GPR64xsp, addrGranuleIndexed_checkAlignment\nis b_2131=0b11011001001 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed_checkAlignment\n{\n\t# in case Rt == Rn, get the tag first so any updates in addrGranuleIndexed_checkAlignment don't affect it\n\ttag:8 = 0;\n\tAllocationTagFromAddress(tag, Rt_GPR64xsp);\n\n\tbuild addrGranuleIndexed_checkAlignment;\n\n\t# this instruction throws an alignment fault if address is not granule-aligned\n\taddress:8 = addrGranuleIndexed_checkAlignment;\n\n\tStoreMemTag(address, tag );\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200400/mask=xffe00c00\n# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200c00/mask=xffe00c00\n# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200800/mask=xffe00c00\n# CONSTRUCT xd9200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:stg Rt_GPR64xsp, addrGranuleIndexed\nis b_2131=0b11011001001 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed\n{\n\t# for the sake of simplified output, omit the alignment check when ShowMemTag is off\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.305 STGM page C6-1838 line 108375 MATCH xd9a00000/mask=xfffffc00\n# CONSTRUCT xd9a00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:stgm Rt_GPR64, \"[\"^Rn_GPR64xsp^\"]\"\nis b_1031=0b1101100110100000000000 & Rt_GPR64 & Rn_GPR64xsp\n{\n\tsze:8 = 4 << (gmid_el1 & 0xf); # The value of GMID_EL1.BS varies between 2 and 6. Can that be asserted somehow?\n\taddress:8 = Rn_GPR64xsp;\n\tAlign(address, sze); # this ensures that address will be granule-aligned, so we don't need to check it\n\tcount:8 = sze >> $(LOG2_TAG_GRANULE);\n\tdata:8 = Rt_GPR64;\n\tindex:8 = (address >> $(LOG2_TAG_GRANULE)) & 0xf;\n\t# for tmp = 0 to count-1\n\ttmp:8 = 0;\n\n\t# This could also be done by leaving index and address constant and adding a tmp-based\n\t# offset to them both, but that crams everything together into the StoreMemTag line in\n\t# the decompiler and makes it harder to assign names and figure out what's going on.\n\t# (Or at least, my opinion is that it's harder that way.)\n\t# Also in favor of this design is that the ARM spec pseudocode describes it this way,\n\t# so it's easier to see that this code matches the pseudocode.\n\ttag:8 = (data >> (index * 4)) & 0xf;\n\tStoreMemTag(address, tag );\n\taddress = address + $(TAG_GRANULE);\n\tindex = index + 1;\n\ttmp = tmp + 1;\n\t# next tmp\n\tif (tmp < count) goto ;\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.305 STGM page C6-1838 line 108375 MATCH xd9a00000/mask=xfffffc00\n# CONSTRUCT xd9a00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:stgm Rt_GPR64, \"[\"^Rn_GPR64xsp^\"]\"\nis b_1031=0b1101100110100000000000 & Rt_GPR64 & Rn_GPR64xsp\n{\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.306 STGP page C6-1839 line 108445 MATCH x68800000/mask=xffc00000\n# C6.2.306 STGP page C6-1839 line 108445 MATCH x69800000/mask=xffc00000\n# C6.2.306 STGP page C6-1839 line 108445 MATCH x69000000/mask=xffc00000\n# CONSTRUCT x68000000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES\n\n:stgp Rt_GPR64, Rt2_GPR64, addrPairGranuleIndexed_checkAlignment\nis b_3031=0b01 & b_2529=0b10100 & (b_23=1 | b_24=1) & b_22=0 & Rt2_GPR64 & addrPairGranuleIndexed_checkAlignment & Rt_GPR64\n{\n\t# Read all registers before addrPairGranuleIndexed_checkAlignment takes effect, or pre-index writeback could modify their values\n\t# (unusually, this instruction does not have unpredictable behavior in that case).\n\tdata1:8 = Rt_GPR64;\n\tdata2:8 = Rt2_GPR64;\n\n\tbuild addrPairGranuleIndexed_checkAlignment;\n\taddress:8 = addrPairGranuleIndexed_checkAlignment; # StoreMemTag requires granule alignment\n\n\ttag:8 = 0;\n\tAllocationTagFromAddress(tag, address);\n\n\t# The decompiler apparently doesn't show changes to [sp+X] unless the new values\n\t# are used in the function. However, the changes really are happening.\n\t*address = data1;\n\t*(address + 8) = data2;\n\tStoreMemTag(address, tag);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.306 STGP page C6-1839 line 108445 MATCH x68800000/mask=xffc00000\n# C6.2.306 STGP page C6-1839 line 108445 MATCH x69800000/mask=xffc00000\n# C6.2.306 STGP page C6-1839 line 108445 MATCH x69000000/mask=xffc00000\n# CONSTRUCT x68000000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES\n\n:stgp Rt_GPR64, Rt2_GPR64, addrPairGranuleIndexed\nis b_3031=0b01 & b_2529=0b10100 & (b_23=1 | b_24=1) & b_22=0 & Rt2_GPR64 & addrPairGranuleIndexed & Rt_GPR64\n{\n\t# Read all registers before addrPairGranuleIndexed takes effect, or pre-index writeback could modify their values\n\t# (unusually, this instruction does not have unpredictable behavior in this case).\n\tdata1:8 = Rt_GPR64;\n\tdata2:8 = Rt2_GPR64;\n\n\t# for the sake of simplified output, omit the alignment check when ShowMemTag is off\n\tbuild addrPairGranuleIndexed;\n\taddress:8 = addrPairGranuleIndexed;\n\n\t# The decompiler apparently doesn't show changes to [sp+X] unless the new values\n\t# are used in the function. However, the changes really are happening.\n\t*address = data1;\n\t*(address + 8) = data2;\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00400/mask=xffe00c00\n# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00c00/mask=xffe00c00\n# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00800/mask=xffe00c00\n# CONSTRUCT xd9e00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:stz2g Rt_GPR64xsp, addrGranuleIndexed_checkAlignment\nis b_2131=0b11011001111 & (b_10=1 | b_11=1) & addrGranuleIndexed_checkAlignment & Rt_GPR64xsp\n{\n\ttag:8 = 0;\n\tAllocationTagFromAddress(tag, Rt_GPR64xsp);\n\n\t# Although the zero-storage is not required to be granule-aligned, the tag-updating is,\n\t# so effectively the entire operation must be at a granule-aligned address.\n\tbuild addrGranuleIndexed_checkAlignment;\n\taddress:8 = addrGranuleIndexed_checkAlignment;\n\n\t# store two granules worth of zeros and tag it from Rt\n\ttmp:8 = 0;\n\taddr:8 = 0;\n\tcount:8 = $(TAG_GRANULE) * 2;\n\n\taddr = address + tmp;\n\t*addr = 0:8;\n\ttmp = tmp + 8;\n\tif (tmp < count) goto ;\n\n\tStoreMemTag(address, tag);\n\tStoreMemTag(address + $(TAG_GRANULE), tag);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00400/mask=xffe00c00\n# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00c00/mask=xffe00c00\n# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00800/mask=xffe00c00\n# CONSTRUCT xd9e00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:stz2g Rt_GPR64xsp, addrGranuleIndexed\nis b_2131=0b11011001111 & (b_10=1 | b_11=1) & addrGranuleIndexed & Rt_GPR64xsp\n{\n\t# for the sake of simplified output, omit the alignment check when ShowMemTag is off\n\tbuild addrGranuleIndexed;\n\taddress:8 = addrGranuleIndexed;\n\n\t# store two granules worth of zeros\n\ttmp:8 = 0;\n\taddr:8 = 0;\n\tcount:8 = $(TAG_GRANULE) * 2;\n\n\taddr = address + tmp;\n\t*addr = 0:8;\n\ttmp = tmp + 8;\n\tif (tmp < count) goto ;\n}\n\n}\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600400/mask=xffe00c00\n# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600c00/mask=xffe00c00\n# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600800/mask=xffe00c00\n# CONSTRUCT xd9600000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:stzg Rt_GPR64xsp, addrGranuleIndexed_checkAlignment\nis b_2131=0b11011001011 & (b_10=1 | b_11=1) & addrGranuleIndexed_checkAlignment & Rt_GPR64xsp\n{\n\ttag:8 = 0;\n\tAllocationTagFromAddress(tag, Rt_GPR64xsp);\n\n\t# Although the zero-storage is not required to be granule-aligned, the tag-updating is,\n\t# so effectively the entire operation must be at a granule-aligned address.\n\tbuild addrGranuleIndexed_checkAlignment;\n\taddress:8 = addrGranuleIndexed_checkAlignment;\n\n\t# store one granule worth of zeros and tag it from Rt\n\ttmp:8 = 0;\n\taddr:8 = 0;\n\tcount:8 = $(TAG_GRANULE);\n\n\taddr = address + tmp;\n\t*addr = 0:8;\n\ttmp = tmp + 8;\n\tif (tmp < count) goto ;\n\n\tStoreMemTag(address, tag);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600400/mask=xffe00c00\n# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600c00/mask=xffe00c00\n# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600800/mask=xffe00c00\n# CONSTRUCT xd9600000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES\n\n:stzg Rt_GPR64xsp, addrGranuleIndexed\nis b_2131=0b11011001011 & (b_10=1 | b_11=1) & addrGranuleIndexed & Rt_GPR64xsp\n{\n\t# for the sake of simplified output, omit the alignment check when ShowMemTag is off\n\tbuild addrGranuleIndexed;\n\taddress:8 = addrGranuleIndexed;\n\n\t# store one granule worth of zeros\n\ttmp:8 = 0;\n\taddr:8 = 0;\n\tcount:8 = $(TAG_GRANULE);\n\n\taddr = address + tmp;\n\t*addr = 0:8;\n\ttmp = tmp + 8;\n\tif (tmp < count) goto ;\n}\n\n}\n\n\n\nwith : ShowMemTag=1 {\n\n# C6.2.355 STZGM page C6-1939 line 113904 MATCH xd9200000/mask=xfffffc00\n# CONSTRUCT xd9200000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:stzgm Rt_GPR64, \"[\"^Rn_GPR64xsp^\"]\"\nis b_1031=0b1101100100100000000000 & Rt_GPR64 & Rn_GPR64xsp\n{\n\tsze:8 = 4 << (dczid_el0 & 0xf); # the last value (DCZID_EL0.BS) can be up to 9 (for a size of 2KB) and seems\n\t # to be hardware-dependent and unwriteable (sysreg spec doesn't show how to write it).\n\t # minimum is probably 2, which would make the size equal to a tag granule\n\taddress:8 = Rn_GPR64xsp;\n\tAlign(address, sze); # based on the educated guess above, address is probably granule-aligned by this, so we won't check it explicitly (compare to LDGM or STGM)\n\tcount:8 = sze >> $(LOG2_TAG_GRANULE);\n\tdata:8 = Rt_GPR64;\n\ttag:8 = data & 0xf;\n\t# for tmp = 0 to count-1\n\ttmp:8 = 0;\n\n\tStoreMemTag(address, tag );\n\n\t# store zeros to the entire granule\n\ttmp_zero:8 = 0;\n\taddr_zero:8 = address;\n\tcount_zero:8 = $(TAG_GRANULE);\n\n\taddr_zero = address + tmp_zero;\n\t*addr_zero = 0:8;\n\ttmp_zero = tmp_zero + 8;\n\tif (tmp_zero < count_zero) goto ;\n\n\taddress = address + $(TAG_GRANULE);\n\t# next tmp\n\ttmp = tmp + 1;\n\tif (tmp < count) goto ;\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.355 STZGM page C6-1939 line 113904 MATCH xd9200000/mask=xfffffc00\n# CONSTRUCT xd9200000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n\n:stzgm Rt_GPR64, \"[\"^Rn_GPR64xsp^\"]\"\nis b_1031=0b1101100100100000000000 & Rt_GPR64 & Rn_GPR64xsp\n{\n\tsze:8 = 4 << (dczid_el0 & 0xf); # the last value (DCZID_EL0.BS) can be up to 9 (for a size of 2KB) and seems\n\t # to be hardware-dependent and unwriteable (sysreg spec doesn't show how to write it).\n\t # minimum is probably 2, which would make the size equal to a tag granule\n\taddress:8 = Rn_GPR64xsp;\n\tAlign(address, sze); # based on the educated guess above, address is probably granule-aligned by this, so we won't check it explicitly (compare to LDGM or STGM)\n\tcount:8 = sze >> $(LOG2_TAG_GRANULE);\n\t# for tmp = 0 to count-1\n\ttmp:8 = 0;\n\n\n\t# store zeros to the entire granule\n\ttmp_zero:8 = 0;\n\taddr_zero:8 = address;\n\tcount_zero:8 = $(TAG_GRANULE);\n\n\taddr_zero = address + tmp_zero;\n\t*addr_zero = 0:8;\n\ttmp_zero = tmp_zero + 8;\n\tif (tmp_zero < count_zero) goto ;\n\n\taddress = address + $(TAG_GRANULE);\n\t# next tmp\n\ttmp = tmp + 1;\n\tif (tmp < count) goto ;\n}\n\n}\n\n\n# To enforce SHOULD BE ZERO fields add: b_1415=0b00\n\nwith : ShowMemTag=1 {\n\n# C6.2.359 SUBG page C6-1947 line 114340 MATCH xd1800000/mask=xffc00000\n# CONSTRUCT xd1800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n\n:subg Rd_GPR64xsp, Rn_GPR64xsp, \"#\"^shifted_imm, \"#\"^b_1013\nis sf=1 & op=1 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp\n# \" & b_1415=0\" is not required by the spec (op3 doesn't have any requirements and is not used)\n[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]\n{\n\t# we don't actually modify the target register, so Ghidra understands the pointer target is still the same.\n\t# pseudo-ops let us do that, but it means that the decompiler can put an unintuitive value in the\n\t# \"CopyPtrTag_AddToPtrTag_Exclude\" argument, e.g. \"param_2 - 0x20\".\n\tuimm4:1 = b_1013;\n\texclude:2 = 0;\n\tOr2BytesWithExcludedTags(exclude);\n\tRd_GPR64xsp = Rn_GPR64xsp - shifted_imm;\n\tCopyPtrTag_AddToPtrTag_Exclude(Rd_GPR64xsp, Rn_GPR64xsp, uimm4, exclude);\n}\n\n}\nwith : ShowMemTag=0 {\n\n# C6.2.359 SUBG page C6-1947 line 114340 MATCH xd1800000/mask=xffc00000\n# CONSTRUCT xd1800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n\n:subg Rd_GPR64xsp, Rn_GPR64xsp, \"#\"^shifted_imm, \"#\"^b_1013\nis sf=1 & op=1 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp\n# \" & b_1415=0\" is not required by the spec (op3 doesn't have any requirements and is not used)\n[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]\n{\n\tRd_GPR64xsp = Rn_GPR64xsp - shifted_imm;\n}\n\n}\n\n\n# Subtract Pointer [setting Flags]:\n# Subtract the 56-bit address held in the second operand from the first and store the result\n# in the destination register. If the destination register is XZR, then just use as a side-\n# effect of being a pointer comparison (CMPP).\n# C6.2.360 SUBP page C6-1948 line 114410 MATCH x9ac00000/mask=xffe0fc00\n# C6.2.361 SUBPS page C6-1949 line 114470 MATCH xbac00000/mask=xffe0fc00\n# CONSTRUCT x9ac00000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES\n\n:subp^SBIT_CZNO Rd_GPR64, Rn_GPR64xsp, Rm_GPR64xsp\nis sf=1 & b_30=0 & S & SBIT_CZNO & b_2128=0b11010110 & b_1015=0b000000 & Rd_GPR64 & Rn_GPR64xsp & Rm_GPR64xsp\n{\n\t# out of a 64-bit value, keep the lowest 56 bits, which is 7 bytes.\n\t# sign-extend a 7-byte value to an 8-byte value. If the boundary weren't byte-aligned,\n\t# sext() wouldn't work so well.\n\ttmp_2:8 = Rm_GPR64xsp;\n\ttmp_2 = sext(tmp_2:7); # if Rm:7 is used here, the decompiler considers the Rm register an int7 for the whole function.\n\ttmp_1:8 = Rn_GPR64xsp;\n\ttmp_1 = sext(tmp_1:7);\n\tsubflags(tmp_1, tmp_2);\n\ttmp_1 = tmp_1 - tmp_2;\n\tresultflags(tmp_1);\n\tRd_GPR64 = tmp_1;\n\tbuild SBIT_CZNO;\n}\n\n\n# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f\n# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES\n\ndefine pcodeop cancelTransaction;\n:tcancel \"#\"^imm16\nis b_2131=0x6a3 & imm16 & b_0519 & b_2020 & b_0004=0x0 {\n\tlocal tmp:2 = imm16;\n\tlocal reason:2 = b_0519;\n\tlocal retry:1 = b_2020;\n\tcancelTransaction(reason, retry);\n}\n\n\n# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff\n# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES\n\ndefine pcodeop commitTransaction;\n:tcommit\nis b_0031=0xd503307f {\n\tcommitTransaction();\n}\n\n\n# C6.2.379 TSTART page C6-1979 line 116075\n\ndefine pcodeop transactionStart;\n:tstart Rd_GPR64\nis b_0531=0x6a9193a & Rd_GPR64 {\n\ttransactionStart(Rd_GPR64);\n}\n\n\n# C6.2.380 TTEST page C6-1981 line 116175\n\ndefine pcodeop transactionDepth;\n:ttest Rd_GPR64\nis b_0531=0x6a9198b & Rd_GPR64 {\n\tRd_GPR64 = transactionDepth();\n}\n\n\n\n# C6.2.387 UDF page C6-1993 line 116744 MATCH x00000000/mask=xffff0000\n# CONSTRUCT x00000000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# Undefined instruction\n:udf b_0015\nis b_1631=0b0000000000000000 & b_0015\n{\n local excaddr:8 = inst_start;\n local id:2 = b_0015;\n\tlocal target:8 = UndefinedInstructionException(id, excaddr);\n\tgoto [target];\n}\n\n\n# C6.2.400 XAFLAG page C6-2008 line 117528 MATCH xd500403f/mask=xfffff0ff\n# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f\n# CONSTRUCT xd500403f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES\n\n:xaflag\nis b_1231=0b11010101000000000100 & b_0007=0b00111111\n{\n\ttmpNG = !CY & !ZR;\n\ttmpZR = ZR & CY;\n\ttmpCY = CY | ZR;\n\ttmpOV = !CY & ZR;\n\n\tNG = tmpNG;\n\tZR = tmpZR;\n\tCY = tmpCY;\n\tOV = tmpOV;\n}\n\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc", "content": "# Specification for the AARCH64 64-bit ARM instruction set\n#\n# See \"ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile\"\n# opcodes are always Little endian, although the data can be Big/Little Endian.\n\n# TODO Collapse SUB/SUBS forms\n# TODO MSR/MRS's need to be specified with special registers, coproc\n# TODO Many special case opcodes for UBFM and BFM, For example BFI\n\n# TODO? Floating point numbers don't display correctly as IEEE floats\n# TODO? Many special case opcodes like\n\n# TODO When writing to 32-bit Rd32, the upper bits of the bigger 64-bit Rd64 are zero'ed\n# Most pcode does this, but this needs to be carefully checked. There may be some\n# that do not zero extend into Rd64, and some that do extend into Rd64 but shouldn't.\n# If it's not done right (or naively) the decompiler gets confused. So\n# the accepted pattern for doing this is:\n#\n# ... calculate and set destination register ...\n# local tmps:SIZE = destination_register;\n# big_register = zext(tmps);\n# destination_register = big_register;\n\n# Note Implemented 2/2016\n#\n# UBFM/SBFM/BFM is implemented\n#\n# When the destination is a 32-bit register, the upper 32 bits of the register must be set to 0.\n# This includes the wsp stack pointer, which might clobber the upper part of an address.\n#\n# And when the destination is a Rd_VPR vector register but the operand size is less than 128 bits,\n# and the destination is not the upper half of the register (ie, bit 30 q=0)\n# then the unused remaining upper bits must be set to 0.\n\n@if DATA_ENDIAN == \"little\"\ndefine endian=little;\n@else\ndefine endian=big;\n@endif\ndefine alignment=4;\n\n# Unlike the above, these are preprocessor macros. Use them with e.g. $(TAG_GRANULE) in SLEIGH statements.\n@define LOG2_TAG_GRANULE \"4\"\n@define TAG_GRANULE \"16\"\n\n# SECTION registers\n\ndefine space ram type=ram_space size=8 default;\ndefine space register type=register_space size=4;\n\n# See \"ABOUT THE ENDIAN IFDEFS\" below for an explanation of the endian\n# ifdefs\n\n@if DATA_ENDIAN == \"little\"\ndefine register offset=0x0000 size=8 [ pc sp ];\ndefine register offset=0x0000 size=4 [ _ _ wsp _ ];\n@else\ndefine register offset=0x0000 size=8 [ pc sp ];\ndefine register offset=0x0000 size=4 [ _ _ _ wsp ];\n@endif\n\ndefine register offset=0x0100 size=1 [ NG ZR CY OV shift_carry tmpCY tmpOV tmpNG tmpZR ];\n\ndefine register offset=0x0200 size=4 [ glob_mask32 ];\ndefine register offset=0x0204 size=8 [ glob_mask64 ];\n\n# address set to load/store a value from memory in/out of vectors\ndefine register offset=0x0300 size=8 [ VecMemAddr VectorSelem ];\n\n# register address to load/store a value from memory in/out of registers\ndefine register offset=0x0310 size=4 [ VecRegAddr ];\n\n# Special Purpose Registers - most of these are really 1 bit and part\n# of a status register, however they all need to be consistent\n\n# 26 registers 0xd0 bytes\n\ndefine register offset=0x1000 size=8\n[\n\tspsr_el1\n\telr_el1\n\tsp_el0\n\tspsel\n\tdaif\n\tcurrentel\n\tnzcv\n\tfpcr\n\tfpsr\n\tdspsr_el0\n\tdlr_el0\n\tspsr_el2\n\telr_el2\n\tsp_el1\n\tspsr_irq\n\tspsr_abt\n\tspsr_und\n\tspsr_fiq\n\tspsr_el3\n\telr_el3\n\tsp_el2\n\tspsr_svc\n\tspsr_hyp\n\tuao\n\tpan\n\ttco\n\taccdata\n];\n\n# System Registers\n\n# 202 registers 0x330 bytes\ndefine register offset=0x1100 size=8\n[\n\tmidr_el1\n\tmpidr_el1\n\trevidr_el1\n\tid_dfr0_el1\n\tid_pfr0_el1\n\tid_pfr1_el1\n\tid_afr0_el1\n\tid_mmfr0_el1\n\tid_mmfr1_el1\n\tid_mmfr2_el1\n\tid_mmfr3_el1\n\tid_isar0_el1\n\tid_isar1_el1\n\tid_isar2_el1\n\tid_isar3_el1\n\tid_isar4_el1\n\tid_isar5_el1\n\tmvfr0_el1\n\tmvfr1_el1\n\tmvfr2_el1\n\tccsidr_el1\n\tid_aa64pfr0_el1\n\tid_aa64pfr1_el1\n\tid_aa64dfr0_el1\n\tid_aa64dfr1_el1\n\tid_aa64isar0_el1\n\tid_aa64isar1_el1\n\tid_aa64mmfr0_el1\n\tid_aa64mmfr1_el1\n\tid_aa64afr0_el1\n\tid_aa64afr1_el1\n\tclidr_el1\n\taidr_el1\n\tcsselr_el1\n\tctr_el0\n\tdczid_el0\n\tvpidr_el2\n\tvmpidr_el2\n\tsctlr_el1\n\tactlr_el1\n\tcpacr_el1\n\tsctlr_el2\n\tactlr_el2\n\thcr_el2\n\tmdcr_el2\n\tcptr_el2\n\thstr_el2\n\thacr_el2\n\tsctlr_el3\n\tactlr_el3\n\tscr_el3\n\tcptr_el3\n\tmdcr_el3\n\tttbr0_el1\n\tttbr1_el1\n\tttbr0_el2\n\tttbr0_el3\n\tvttbr_el2\n\ttcr_el1\n\ttcr_el2\n\ttcr_el3\n\tvtcr_el2\n\tafsr0_el1\n\tafsr1_el1\n\tafsr0_el2\n\tafsr1_el2\n\tafsr0_el3\n\tafsr1_el3\n\tesr_el1\n\tesr_el2\n\tesr_el3\n\tfpexc32_el2\n\tfar_el1\n\tfar_el2\n\tfar_el3\n\thpfar_el2\n\tpar_el1\n\tpmintenset_el1\n\tpmintenclr_el1\n\tpmcr_el0\n\tpmcntenset_el0\n\tpmcntenclr_el0\n\tpmovsclr_el0\n\tpmswinc_el0\n\tpmselr_el0\n\tpmceid0_el0\n\tpmceid1_el0\n\tpmccntr_el0\n\tpmxevtyper_el0\n\tpmxevcntr_el0\n\tpmuserenr_el0\n\tpmovsset_el0\n\tpmevcntr0_el0\n\tpmevcntr1_el0\n\tpmevcntr2_el0\n\tpmevcntr3_el0\n\tpmevcntr4_el0\n\tpmevcntr5_el0\n\tpmevcntr6_el0\n\tpmevcntr7_el0\n\tpmevcntr8_el0\n\tpmevcntr9_el0\n\tpmevcntr10_el0\n\tpmevcntr11_el0\n\tpmevcntr12_el0\n\tpmevcntr13_el0\n\tpmevcntr14_el0\n\tpmevcntr15_el0\n\tpmevcntr16_el0\n\tpmevcntr17_el0\n\tpmevcntr18_el0\n\tpmevcntr19_el0\n\tpmevcntr20_el0\n\tpmevcntr21_el0\n\tpmevcntr22_el0\n\tpmevcntr23_el0\n\tpmevcntr24_el0\n\tpmevcntr25_el0\n\tpmevcntr26_el0\n\tpmevcntr27_el0\n\tpmevcntr28_el0\n\tpmevcntr29_el0\n\tpmevcntr30_el0\n\tpmevtyper0_el0\n\tpmevtyper1_el0\n\tpmevtyper2_el0\n\tpmevtyper3_el0\n\tpmevtyper4_el0\n\tpmevtyper5_el0\n\tpmevtyper6_el0\n\tpmevtyper7_el0\n\tpmevtyper8_el0\n\tpmevtyper9_el0\n\tpmevtyper10_el0\n\tpmevtyper11_el0\n\tpmevtyper12_el0\n\tpmevtyper13_el0\n\tpmevtyper14_el0\n\tpmevtyper15_el0\n\tpmevtyper16_el0\n\tpmevtyper17_el0\n\tpmevtyper18_el0\n\tpmevtyper19_el0\n\tpmevtyper20_el0\n\tpmevtyper21_el0\n\tpmevtyper22_el0\n\tpmevtyper23_el0\n\tpmevtyper24_el0\n\tpmevtyper25_el0\n\tpmevtyper26_el0\n\tpmevtyper27_el0\n\tpmevtyper28_el0\n\tpmevtyper29_el0\n\tpmevtyper30_el0\n\tpmccfiltr_el0\n\tmair_el1\n\tmair_el2\n\tmair_el3\n\tamair_el1\n\tamair_el2\n\tamair_el3\n\tvbar_el1\n\tvbar_el2\n\tvbar_el3\n\trvbar_el1\n\trvbar_el2\n\trvbar_el3\n\trmr_el1\n\trmr_el2\n\trmr_el3\n\tisr_el1\n\tcontextidr_el1\n\ttpidr_el0\n\ttpidrro_el0\n\ttpidr_el1\n\ttpidr_el2\n\ttpidr_el3\n\tteecr32_el1\n\tcntfrq_el0\n\tcntpct_el0\n\tcntvct_el0\n\tcntvoff_el2\n\tcntkctl_el1\n\tcnthctl_el2\n\tcntp_tval_el0\n\tcntp_ctl_el0\n\tcntp_cval_el0\n\tcntv_tval_el0\n\tcntv_ctl_el0\n\tcntv_cval_el0\n\tcnthp_tval_el2\n\tcnthp_ctl_el2\n\tcnthp_cval_el2\n\tcntps_tval_el1\n\tcntps_ctl_el1\n\tcntps_cval_el1\n\tdacr32_el2\n\tifsr32_el2\n\tteehbr32_el1\n\tsder32_el3\n\tgmid_el1\n\tgcr_el1\n\tssbs\n\tallint\n\tdit\n\tsvcr\n];\n\n# bitrange definitions are [,]\n\ndefine bitrange gcr_el1.exclude=gcr_el1[0,16];\n\n# Debug Registers\n# 82 registers 0x290 bytes\n\ndefine register offset=0x1800 size=8\n[\n\tosdtrrx_el1\n\tmdccint_el1\n\tmdscr_el1\n\tosdtrtx_el1\n\toseccr_el1\n\tdbgbvr0_el1\n\tdbgbvr1_el1\n\tdbgbvr2_el1\n\tdbgbvr3_el1\n\tdbgbvr4_el1\n\tdbgbvr5_el1\n\tdbgbvr6_el1\n\tdbgbvr7_el1\n\tdbgbvr8_el1\n\tdbgbvr9_el1\n\tdbgbvr10_el1\n\tdbgbvr11_el1\n\tdbgbvr12_el1\n\tdbgbvr13_el1\n\tdbgbvr14_el1\n\tdbgbvr15_el1\n\tdbgbcr0_el1\n\tdbgbcr1_el1\n\tdbgbcr2_el1\n\tdbgbcr3_el1\n\tdbgbcr4_el1\n\tdbgbcr5_el1\n\tdbgbcr6_el1\n\tdbgbcr7_el1\n\tdbgbcr8_el1\n\tdbgbcr9_el1\n\tdbgbcr10_el1\n\tdbgbcr11_el1\n\tdbgbcr12_el1\n\tdbgbcr13_el1\n\tdbgbcr14_el1\n\tdbgbcr15_el1\n\tdbgwvr0_el1\n\tdbgwvr1_el1\n\tdbgwvr2_el1\n\tdbgwvr3_el1\n\tdbgwvr4_el1\n\tdbgwvr5_el1\n\tdbgwvr6_el1\n\tdbgwvr7_el1\n\tdbgwvr8_el1\n\tdbgwvr9_el1\n\tdbgwvr10_el1\n\tdbgwvr11_el1\n\tdbgwvr12_el1\n\tdbgwvr13_el1\n\tdbgwvr14_el1\n\tdbgwvr15_el1\n\tdbgwcr0_el1\n\tdbgwcr1_el1\n\tdbgwcr2_el1\n\tdbgwcr3_el1\n\tdbgwcr4_el1\n\tdbgwcr5_el1\n\tdbgwcr6_el1\n\tdbgwcr7_el1\n\tdbgwcr8_el1\n\tdbgwcr9_el1\n\tdbgwcr10_el1\n\tdbgwcr11_el1\n\tdbgwcr12_el1\n\tdbgwcr13_el1\n\tdbgwcr14_el1\n\tdbgwcr15_el1\n\tmdrar_el1\n\toslar_el1\n\toslsr_el1\n\tosdlr_el1\n\tdbgprcr_el1\n\tdbgclaimset_el1\n\tdbgclaimclr_el1\n\tdbgauthstatus_el1\n\tmdccsr_el0\n\tdbgdtr_el0\n\tdbgdtrrx_el0\n\tdbgdtrtx_el0\n\tdbgvcr32_el2\n];\n\ndefine register offset=0x3000 size=4 contextreg;\n\n# value loaded from memory to store in register\n# or computed to store in memory\ndefine register offset=0x3100 size=4 tmp_ldWn;\ndefine register offset=0x3104 size=8 tmp_ldXn;\ndefine register offset=0x310c size=4 tmp_stWn;\ndefine register offset=0x3110 size=8 tmp_stXn;\n\n# General purpose and SIMD registers\n#\n# These will start at 0x3800 and there should be no defined registers\n# after this address (this is because the size of the registers is\n# potentially variable).\n#\n# ABOUT THE ENDIAN IFDEFS\n# the *address* of the overlain registers depends on if the underlying\n# memory is in big or little endian order. In little endian order, the\n# LSB is byte 0, so (for example) w0 and x0 have the same address *in\n# register memory*. But in big endian order, the LSB of x0 is byte 7,\n# and so w0 starts at byte 4. All of that just gets at the address in\n# register memory. Any time a value is loaded into a varnode and\n# manipulated in sleigh code, it is always in big endian order. It is\n# only byte reversed when read or written to little endian memory. All\n# that means is that there are endian ifdefs for the overlain\n# registers here, but that can and should be ignored when writing\n# semantics.\n\n# General purpose registers R0-R30 (R31=zero register ZR)\n# They are accessed as\n#\t64-bit register named X0-X30\n#\t32-bit registers named W0-W30\n\ndefine register offset=0x4000 size=8\n[\n\tx0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15\n\tx16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 xzr\n];\n\n@if DATA_ENDIAN == \"little\"\ndefine register offset=0x4000 size=4\n[\n\tw0 _\n\tw1 _\n\tw2 _\n\tw3 _\n\tw4 _\n\tw5 _\n\tw6 _\n\tw7 _\n\tw8 _\n\tw9 _\n\tw10 _\n\tw11 _\n\tw12 _\n\tw13 _\n\tw14 _\n\tw15 _\n\tw16 _\n\tw17 _\n\tw18 _\n\tw19 _\n\tw20 _\n\tw21 _\n\tw22 _\n\tw23 _\n\tw24 _\n\tw25 _\n\tw26 _\n\tw27 _\n\tw28 _\n\tw29 _\n\tw30 _\n\twzr _\n];\n@else\ndefine register offset=0x4000 size=4\n[\n\t_ w0\n\t_ w1\n\t_ w2\n\t_ w3\n\t_ w4\n\t_ w5\n\t_ w6\n\t_ w7\n\t_ w8\n\t_ w9\n\t_ w10\n\t_ w11\n\t_ w12\n\t_ w13\n\t_ w14\n\t_ w15\n\t_ w16\n\t_ w17\n\t_ w18\n\t_ w19\n\t_ w20\n\t_ w21\n\t_ w22\n\t_ w23\n\t_ w24\n\t_ w25\n\t_ w26\n\t_ w27\n\t_ w28\n\t_ w29\n\t_ w30\n\t_ wzr\n];\n@endif\n\n# SIMD&FP registers V0-V31 at 0x5000\n# They are accessed as:\n#\t128-bit registers named Q0-Q31\n#\t64-bit registers named D0-D31\n#\t32-bit registers named S0-S31\n#\t16-bit registers named H0-H31\n#\t8-bit registers named B0-B31\n#\ta 128-bit vector of elements\n#\ta 64-bit vector of elements\n# The packing is endian dependent\n# For SVE, registers Z0-Z31 can be any size that is a multiple of 128\n# up to 2048 bits, and they overlap the V0-V31 registers\n\n# temporary SIMD registers, needed for calculations in SIMD semantics\n\ndefine register offset=0x4800 size=32 [ TMPZ1 TMPZ2 TMPZ3 TMPZ4 TMPZ5 TMPZ6 ];\n\n@if DATA_ENDIAN == \"little\"\n\ndefine register offset=0x4800 size=16\n[\n\tTMPQ1 _\n\tTMPQ2 _\n\tTMPQ3 _\n\tTMPQ4 _\n\tTMPQ5 _\n\tTMPQ6 _\n];\n\ndefine register offset=0x4800 size=8\n[\n\tTMPD1 _ _ _\n\tTMPD2 _ _ _\n\tTMPD3 _ _ _\n\tTMPD4 _ _ _\n\tTMPD5 _ _ _\n\tTMPD6 _ _ _\n];\n\ndefine register offset=0x4800 size=4\n[\n\tTMPS1 _ _ _ _ _ _ _\n\tTMPS2 _ _ _ _ _ _ _\n\tTMPS3 _ _ _ _ _ _ _\n\tTMPS4 _ _ _ _ _ _ _\n\tTMPS5 _ _ _ _ _ _ _\n\tTMPS6 _ _ _ _ _ _ _\n];\n\n@else # this is DATA_ENDIAN == \"big\"\n\ndefine register offset=0x4800 size=16\n[\n\t_ TMPQ1\n\t_ TMPQ2\n\t_ TMPQ3\n\t_ TMPQ4\n\t_ TMPQ5\n\t_ TMPQ6\n];\n\ndefine register offset=0x4800 size=8\n[\n\t_ _ _ TMPD1\n\t_ _ _ TMPD2\n\t_ _ _ TMPD3\n\t_ _ _ TMPD4\n\t_ _ _ TMPD5\n\t_ _ _ TMPD6\n];\n\ndefine register offset=0x4800 size=4\n[\n\t_ _ _ _ _ _ _ TMPS1\n\t_ _ _ _ _ _ _ TMPS2\n\t_ _ _ _ _ _ _ TMPS3\n\t_ _ _ _ _ _ _ TMPS4\n\t_ _ _ _ _ _ _ TMPS5\n\t_ _ _ _ _ _ _ TMPS6\n];\n\n@endif\n\n# The size of the simd (z) register (in bytes) can be any multiple of\n# 16 from 32 to 256 bytes. There are also 16 predicate registers are\n# 1/8 the size of the corresponding simd registers.\n\n@define SIMD_SIZE \"32\"\n@define PRED_SIZE \"4\"\n\n# In order to \"move\" the overlain registers to the right place, use\n# these defines to locate within the z register. The __128 is for an\n# 128-bit vector overlaid in a z-register, etc. For this to work\n# SIMD_SIZE must be at least 32.\n\ndefine register offset=0x5000 size=$(SIMD_SIZE)\n[\n\tz0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31\n];\n\ndefine register offset=0x6000 size=$(PRED_SIZE)\n[\n\tp0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15\n];\n\n# define the overlaid simd registers\n\n@if DATA_ENDIAN == \"little\"\n\ndefine register offset=0x5000 size=16\n[\n\tq0 _\n\tq1 _\n\tq2 _\n\tq3 _\n\tq4 _\n\tq5 _\n\tq6 _\n\tq7 _\n\tq8 _\n\tq9 _\n\tq10 _\n\tq11 _\n\tq12 _\n\tq13 _\n\tq14 _\n\tq15 _\n\tq16 _\n\tq17 _\n\tq18 _\n\tq19 _\n\tq20 _\n\tq21 _\n\tq22 _\n\tq23 _\n\tq24 _\n\tq25 _\n\tq26 _\n\tq27 _\n\tq28 _\n\tq29 _\n\tq30 _\n\tq31 _\n];\n\ndefine register offset=0x5000 size=8\n[\n\td0 _ _ _\n\td1 _ _ _\n\td2 _ _ _\n\td3 _ _ _\n\td4 _ _ _\n\td5 _ _ _\n\td6 _ _ _\n\td7 _ _ _\n\td8 _ _ _\n\td9 _ _ _\n\td10 _ _ _\n\td11 _ _ _\n\td12 _ _ _\n\td13 _ _ _\n\td14 _ _ _\n\td15 _ _ _\n\td16 _ _ _\n\td17 _ _ _\n\td18 _ _ _\n\td19 _ _ _\n\td20 _ _ _\n\td21 _ _ _\n\td22 _ _ _\n\td23 _ _ _\n\td24 _ _ _\n\td25 _ _ _\n\td26 _ _ _\n\td27 _ _ _\n\td28 _ _ _\n\td29 _ _ _\n\td30 _ _ _\n\td31 _ _ _\n];\n\ndefine register offset=0x5000 size=4\n[\n\ts0 _ _ _ _ _ _ _\n\ts1 _ _ _ _ _ _ _\n\ts2 _ _ _ _ _ _ _\n\ts3 _ _ _ _ _ _ _\n\ts4 _ _ _ _ _ _ _\n\ts5 _ _ _ _ _ _ _\n\ts6 _ _ _ _ _ _ _\n\ts7 _ _ _ _ _ _ _\n\ts8 _ _ _ _ _ _ _\n\ts9 _ _ _ _ _ _ _\n\ts10 _ _ _ _ _ _ _\n\ts11 _ _ _ _ _ _ _\n\ts12 _ _ _ _ _ _ _\n\ts13 _ _ _ _ _ _ _\n\ts14 _ _ _ _ _ _ _\n\ts15 _ _ _ _ _ _ _\n\ts16 _ _ _ _ _ _ _\n\ts17 _ _ _ _ _ _ _\n\ts18 _ _ _ _ _ _ _\n\ts19 _ _ _ _ _ _ _\n\ts20 _ _ _ _ _ _ _\n\ts21 _ _ _ _ _ _ _\n\ts22 _ _ _ _ _ _ _\n\ts23 _ _ _ _ _ _ _\n\ts24 _ _ _ _ _ _ _\n\ts25 _ _ _ _ _ _ _\n\ts26 _ _ _ _ _ _ _\n\ts27 _ _ _ _ _ _ _\n\ts28 _ _ _ _ _ _ _\n\ts29 _ _ _ _ _ _ _\n\ts30 _ _ _ _ _ _ _\n\ts31 _ _ _ _ _ _ _\n];\n\ndefine register offset=0x5000 size=2\n[\n\th0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th19 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th23 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th25 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th26 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th27 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th29 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\th31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n];\n\ndefine register offset=0x5000 size=1\n[\n\tb0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb19 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb23 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb25 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb26 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb27 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb29 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tb31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n];\n\n@else # this is DATA_ENDIAN == \"big\"\n\ndefine register offset=0x5000 size=16\n[\n\t_ q0\n\t_ q1\n\t_ q2\n\t_ q3\n\t_ q4\n\t_ q5\n\t_ q6\n\t_ q7\n\t_ q8\n\t_ q9\n\t_ q10\n\t_ q11\n\t_ q12\n\t_ q13\n\t_ q14\n\t_ q15\n\t_ q16\n\t_ q17\n\t_ q18\n\t_ q19\n\t_ q20\n\t_ q21\n\t_ q22\n\t_ q23\n\t_ q24\n\t_ q25\n\t_ q26\n\t_ q27\n\t_ q28\n\t_ q29\n\t_ q30\n\t_ q31\n];\n\ndefine register offset=0x5000 size=8\n[\n\t_ _ _ d0\n\t_ _ _ d1\n\t_ _ _ d2\n\t_ _ _ d3\n\t_ _ _ d4\n\t_ _ _ d5\n\t_ _ _ d6\n\t_ _ _ d7\n\t_ _ _ d8\n\t_ _ _ d9\n\t_ _ _ d10\n\t_ _ _ d11\n\t_ _ _ d12\n\t_ _ _ d13\n\t_ _ _ d14\n\t_ _ _ d15\n\t_ _ _ d16\n\t_ _ _ d17\n\t_ _ _ d18\n\t_ _ _ d19\n\t_ _ _ d20\n\t_ _ _ d21\n\t_ _ _ d22\n\t_ _ _ d23\n\t_ _ _ d24\n\t_ _ _ d25\n\t_ _ _ d26\n\t_ _ _ d27\n\t_ _ _ d28\n\t_ _ _ d29\n\t_ _ _ d30\n\t_ _ _ d31\n];\n\ndefine register offset=0x5000 size=4\n[\n\t_ _ _ _ _ _ _ s0\n\t_ _ _ _ _ _ _ s1\n\t_ _ _ _ _ _ _ s2\n\t_ _ _ _ _ _ _ s3\n\t_ _ _ _ _ _ _ s4\n\t_ _ _ _ _ _ _ s5\n\t_ _ _ _ _ _ _ s6\n\t_ _ _ _ _ _ _ s7\n\t_ _ _ _ _ _ _ s8\n\t_ _ _ _ _ _ _ s9\n\t_ _ _ _ _ _ _ s10\n\t_ _ _ _ _ _ _ s11\n\t_ _ _ _ _ _ _ s12\n\t_ _ _ _ _ _ _ s13\n\t_ _ _ _ _ _ _ s14\n\t_ _ _ _ _ _ _ s15\n\t_ _ _ _ _ _ _ s16\n\t_ _ _ _ _ _ _ s17\n\t_ _ _ _ _ _ _ s18\n\t_ _ _ _ _ _ _ s19\n\t_ _ _ _ _ _ _ s20\n\t_ _ _ _ _ _ _ s21\n\t_ _ _ _ _ _ _ s22\n\t_ _ _ _ _ _ _ s23\n\t_ _ _ _ _ _ _ s24\n\t_ _ _ _ _ _ _ s25\n\t_ _ _ _ _ _ _ s26\n\t_ _ _ _ _ _ _ s27\n\t_ _ _ _ _ _ _ s28\n\t_ _ _ _ _ _ _ s29\n\t_ _ _ _ _ _ _ s30\n\t_ _ _ _ _ _ _ s31\n];\n\ndefine register offset=0x5000 size=2\n[\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h0\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h1\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h2\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h3\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h4\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h5\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h6\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h7\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h8\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h9\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h10\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h11\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h12\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h13\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h14\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h15\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h16\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h17\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h18\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h19\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h20\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h21\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h22\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h23\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h24\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h25\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h26\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h27\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h28\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h29\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h30\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h31\n];\n\ndefine register offset=0x5000 size=1\n[\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b0\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b1\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b2\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b3\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b4\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b5\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b6\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b7\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b8\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b9\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b10\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b11\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b12\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b13\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b14\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b15\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b16\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b17\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b18\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b19\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b20\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b21\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b22\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b23\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b24\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b25\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b26\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b27\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b28\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b29\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b30\n\t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b31\n];\n@endif\n\n# SECTION token fields and context variables\n\n# \"noflow\" limits register changes to a single instruction (or a highlighted region) rather than following control flow.\n# This allows the select-clear-SetRegister-disassemble procedure to be done without affecting\n# any instructions other than those that are selected.\ndefine context contextreg\n\tImmS_ImmR_TestSet = (0,0)\n\tImmS_LT_ImmR = (1,1)\n\tImmS_EQ_ImmR = (2,2)\n\tImmS_LT_ImmR_minus_1 = (3,3)\n\tImmS_ne_1f = (4,4)\n\tImmS_ne_3f = (5,5)\n\tShowPAC = (21,21) noflow\n\tPAC_clobber = (22,22) noflow\n\tShowBTI = (23,23) noflow\n\tShowMemTag = (24,24) noflow\n;\n\ndefine token instrAARCH64 (32) endian = little\n\n\tRm = (16,20)\n\tRn = (5,9)\n\tRd = (0,4)\n\tRt = (0,4)\n\tRa = (10,14)\n\tRt2 = (10,14)\n\n\tRm_FPR8 = (16,20)\n\tRn_FPR8 = (5,9)\n\tRd_FPR8 = (0,4)\n\tRd_FPR8_2 = (0,4)\n\tRt_FPR8 = (0,4)\n\tRm_FPR16 = (16,20)\n\tRn_FPR16 = (5,9)\n\tRd_FPR16 = (0,4)\n\tRd_FPR16_2 = (0,4)\n\tRt_FPR16 = (0,4)\n\tRa_FPR16 = (10,14)\n\tRm_FPR32 = (16,20)\n\tRn_FPR32 = (5,9)\n\tRd_FPR32 = (0,4)\n\tRd_FPR32_2 = (0,4)\n\tRa_FPR32 = (10,14)\n\tRm_FPR64 = (16,20)\n\tRn_FPR64 = (5,9)\n\tRd_FPR64 = (0,4)\n\tRd_FPR64_2 = (0,4)\n\tRt_FPR64 = (0,4)\n\tRt_FPR32 = (0,4)\n\tRa_FPR64 = (10,14)\n\tRt2_FPR128 = (10,14)\n\tRt2_FPR32 = (10,14)\n\tRt2_FPR64 = (10,14)\n\tRa_VPR128 = (10,14)\n\n\tRm_VPR64 = (16,20)\n\tRn_VPR64 = (5,9)\n\tRd_VPR64 = (0,4)\n\n\tRe_VPR128 = (16,20)\n\tRe_VPR128Lo = (16,19)\n\tRm_VPR128 = (16,20)\n\tRm_VPR128Lo = (16,19)\n\tRn_VPR128 = (5,9)\n\tRnn_VPR128 = (5,9)\n\tRnnn_VPR128 = (5,9)\n\tRnnnn_VPR128 = (5,9)\n\tRd_VPR128 = (0,4)\n\tRt_VPR128 = (0,4)\n\tRtt_VPR128 = (0,4)\n\tRttt_VPR128 = (0,4)\n\tRtttt_VPR128 = (0,4)\n\tRt_VPR64 = (0,4)\n\tRtt_VPR64 = (0,4)\n\tRttt_VPR64 = (0,4)\n\tRtttt_VPR64 = (0,4)\n\tRt_FPR128 = (0,4)\n\tvRm_VPR64 = (16,20)\n\tvRm_VPR128Lo = (16,19)\n\tvRe_VPR128 = (16,20)\n\tvRe_VPR128Lo = (16,19)\n\tvRn_VPR64 = (5,9)\n\tvRd_VPR64 = (0,4)\n\tvRm_VPR128 = (16,20)\n\tvRn_VPR128 = (5,9)\n\tvRnn_VPR128 = (5,9)\n\tvRnnn_VPR128 = (5,9)\n\tvRnnnn_VPR128 = (5,9)\n\tvRd_VPR128 = (0,4)\n\tvRa_VPR128 = (10,14)\n\n\tVt = (0,4)\n\tVtt = (0,4)\n\tVttt = (0,4)\n\tVtttt = (0,4)\n\n\tvVt = (0,4)\n\tvVtt = (0,4)\n\tvVttt = (0,4)\n\tvVtttt = (0,4)\n\n\taa_Xm = (16,20)\n\taa_Xn = (5,9)\n\taa_Xd = (0,4)\n\taa_Xs = (16,20)\n\taa_Xss = (16,20)\n\taa_Xt = (0,4)\n\taa_Xtt = (0,4)\n\taa_Xa = (10,14)\n\taa_Wm = (16,20)\n\taa_Wn = (5,9)\n\taa_Wd = (0,4)\n\taa_Ws = (16,20)\n\taa_Wss = (16,20)\n\taa_Wt = (0,4)\n\taa_Wtt = (0,4)\n\taa_Wa = (10,14)\n\taa_Wa2 = (10,14)\n\taa_CRm = (8,11)\n\n\tbr_cond_op = (0,3)\n\tcond_op = (12,15)\n\n\taa_prefetch = (0,4)\n\n\taa_hw = (21,22)\n\n\taa_extreg_imm3 = (10,12)\n\taa_extreg_shift = (22,23)\n\taa_extreg_option = (13,15)\n\n\timm6 = (10,15)\n\taa_imm7 = (15,21)\n\timm12 = (10,21)\n\timm16 = (5,20)\n\n\tsimm7 = (15,21) signed\n\tsimm9 = (12,20) signed\n\tsimm14 = (5,18) signed\n\tsimm19 = (5,23) signed\n\tsimm26 = (0,25) signed\n\n\timmlo = (29,30)\n\timmhi = (5,23) signed\n\n\t# Arbitrary bit fields\n\n\tb_00 = (0,0)\n\tb_01 = (1,1)\n\tb_02 = (2,2)\n\tb_03 = (3,3)\n\tb_04 = (4,4)\n\tb_05 = (5,5)\n\tb_06 = (6,6)\n\tb_07 = (7,7)\n\tb_08 = (8,8)\n\tb_09 = (9,9)\n\tb_10 = (10,10)\n\tb_11 = (11,11)\n\tb_12 = (12,12)\n\tb_13 = (13,13)\n\tb_14 = (14,14)\n\tb_15 = (15,15)\n\tb_16 = (16,16)\n\tb_17 = (17,17)\n\tb_18 = (18,18)\n\tb_19 = (19,19)\n\tb_20 = (20,20)\n\tb_21 = (21,21)\n\tb_22 = (22,22)\n\tb_23 = (23,23)\n\tb_24 = (24,24)\n\tb_25 = (25,25)\n\tb_26 = (26,26)\n\tb_27 = (27,27)\n\tb_28 = (28,28)\n\tb_29 = (29,29)\n\tb_30 = (30,30)\n\tb_31 = (31,31)\n\n\tb_0001 = (0,1)\n\tb_0003 = (0,3)\n\tb_0004 = (0,4)\n\tb_0006 = (0,6)\n\tb_0007 = (0,7)\n\tb_0009 = (0,9)\n\tb_0011 = (0,11)\n\tb_0015 = (0,15)\n\tb_0027 = (0,27)\n\tb_0031 = (0,31)\n\tb_0102 = (1,2)\n\tb_0103 = (1,3)\n\tb_0204 = (2,4)\n\tb_0304 = (3,4)\n\tb_0405 = (4,5)\n\tb_0406 = (4,6)\n\tb_0407 = (4,7)\n\tb_0409 = (4,9)\n\tb_0411 = (4,11)\n\tb_0427 = (4,27)\n\tb_0431 = (4,31)\n\tb_0506 = (5,6)\n\tb_0507 = (5,7)\n\tb_0508 = (5,8)\n\tb_0509 = (5,9)\n\tb_0510 = (5,10)\n\tb_0515 = (5,15)\n\tb_0519 = (5,19)\n\tb_0531 = (5,31)\n\tb_0607 = (6,7)\n\tb_0609 = (6,9)\n\tb_0610 = (6,10)\n\tb_0611 = (6,11)\n\tb_0708 = (7,8)\n\tb_0709 = (7,9)\n\tb_0710 = (7,10)\n\tb_0711 = (7,11)\n\tb_0809 = (8,9)\n\tb_0810 = (8,10)\n\tb_0811 = (8,11)\n\tb_0910 = (9,10)\n\tb_0911 = (9,11)\n\tb_0916 = (9,16)\n\tb_1010 = (10,10)\n\tb_1011 = (10,11)\n\tb_1012 = (10,12)\n\tb_1013 = (10,13)\n\tb_1014 = (10,14)\n\tb_1015 = (10,15)\n\tb_1021 = (10,21)\n\tb_1022 = (10,22)\n\tb_1028 = (10,28)\n\tb_1029 = (10,29)\n\tb_1031 = (10,31)\n\tb_1111 = (11,11)\n\tb_1112 = (11,12)\n\tb_1113 = (11,13)\n\tb_1114 = (11,14)\n\tb_1115 = (11,15)\n\tb_1116 = (11,16)\n\tb_1131 = (11,31)\n\tb_1212 = (12,12)\n\tb_1213 = (12,13)\n\tb_1214 = (12,14)\n\tb_1215 = (12,15)\n\tb_1216 = (12,16)\n\tb_1217 = (12,17)\n\tb_1220 = (12,20)\n\tb_1223 = (12,23)\n\tb_1229 = (12,29)\n\tb_1230 = (12,30)\n\tb_1231 = (12,31)\n\tb_1313 = (13,13)\n\tb_1314 = (13,14)\n\tb_1315 = (13,15)\n\tb_1317 = (13,17)\n\tb_1321 = (13,21)\n\tb_1322 = (13,22)\n\tb_1414 = (14,14)\n\tb_1417 = (14,17)\n\tb_1415 = (14,15)\n\tb_1431 = (14,31)\n\tb_1515 = (15,15)\n\tb_1517 = (15,17)\n\tb_1520 = (15,20)\n\tb_1531 = (15,31)\n\tb_1616 = (16,16)\n\tb_1617 = (16,17)\n\tb_1618 = (16,18)\n\tb_1619 = (16,19)\n\tb_1620 = (16,20)\n\tb_1621 = (16,21)\n\tb_1623 = (16,23)\n\tb_1627 = (16,27)\n\tb_1629 = (16,29)\n\tb_1631 = (16,31)\n\tb_1718 = (17,18)\n\tb_1719 = (17,19)\n\tb_1720 = (17,20)\n\tb_1721 = (17,21)\n\tb_1722 = (17,22)\n\tb_1818 = (18,18)\n\tb_1819 = (18,19)\n\tb_1820 = (18,20)\n\tb_1821 = (18,21)\n\tb_1920 = (19,20)\n\tb_1921 = (19,21)\n\tb_1922 = (19,22)\n\tb_1923 = (19,23)\n\tb_1928 = (19,28)\n\tb_1929 = (19,29)\n\tb_1931 = (19,31)\n\tb_2020 = (20,20)\n\tb_2021 = (20,21)\n\tb_2022 = (20,22)\n\tb_2023 = (20,23)\n\tb_2024 = (20,24)\n\tb_2027 = (20,27)\n\tb_2121 = (21,21)\n\tb_2122 = (21,22)\n\tb_2123 = (21,23)\n\tb_2124 = (21,24)\n\tb_2125 = (21,25)\n\tb_2127 = (21,27)\n\tb_2128 = (21,28)\n\tb_2129 = (21,29)\n\tb_2130 = (21,30)\n\tb_2131 = (21,31)\n\tb_2222 = (22,22)\n\tb_2223 = (22,23)\n\tb_2224 = (22,24)\n\tb_2225 = (22,25)\n\tb_2229 = (22,29)\n\tb_2231 = (22,31)\n\tb_2323 = (23,23)\n\tb_2324 = (23,24)\n\tb_2325 = (23,25)\n\tb_2327 = (23,27)\n\tb_2328 = (23,28)\n\tb_2329 = (23,29)\n\tb_2331 = (23,31)\n\tb_2425 = (24,25)\n\tb_2427 = (24,27)\n\tb_2428 = (24,28)\n\tb_2429 = (24,29)\n\tb_2430 = (24,30)\n\tb_2431 = (24,31)\n\tb_2525 = (25,25)\n\tb_2527 = (25,27)\n\tb_2529 = (25,29)\n\tb_2530 = (25,30)\n\tb_2531 = (25,31)\n\tb_2627 = (26,27)\n\tb_2629 = (26,29)\n\tb_2630 = (26,30)\n\tb_2631 = (26,31)\n\tb_2729 = (27,29)\n\tb_2929 = (29,29)\n\tb_2930 = (29,30)\n\tb_2931 = (29,31)\n\tb_3030 = (30,30)\n\tb_3031 = (30,31)\n\tb_3131 = (31,31)\n\n\tcmpr_op = (24,24)\n\tsf = (31,31)\n\n\timm_neon_uimm1 = (20,20)\n\timm_neon_uimm2 = (19,20)\n\timm_neon_uimm3 = (18,20)\n\timm_neon_uimm4 = (17,20)\n\timmN_neon_uimm1 = (14,14)\n\timmN_neon_uimm2 = (13,14)\n\timmN_neon_uimm3 = (12,14)\n\timmN_neon_uimm4 = (11,14)\n\n\tfpOpcode = (16,18)\n\tfpDpOpcode = (15,20)\n\n\tCRm_CRx = (8,11)\n\tCRm_32 = (10,11)\n\tCRm_10 = (8,9)\n\tCRm_dbarrier_op = (8,11)\n\tCRm_isb_op = (8,11)\n\n\tCRn = (12,15)\n\tCRm = (8,11)\n\tCRn_CRx = (12,15)\n\n\tImm4 = (11,13)\n\n\t# C2.2.3 Modified immediate constants in A64 instructions page C2-158\n\n\tImm8_fmov_sign = (20,20)\t# a\n\tImm8_fmov_exph = (19,19)\t# b\n\tImm8_fmov_expl = (17,18)\t# cd\n\tImm8_fmov_frac = (13,16)\t# efgh\n\n\tImmN = (22,22)\n\tImmR = (16,21)\n\tImmS = (10,15)\n\tImm_imm0_63 = (16,21)\n\n\tn_uimm8L = (5,9)\n\tn_uimm8H = (16,18)\n\n\tImm_uimm3 = (16,18)\n\tImm_uimm4 = (16,19)\n\tImm_uimm5 = (16,20)\n\tImm_uimm5_31 = (31,31)\n\tImm_uimm6 = (31,31)\n\n\tL = (22,22)\n\n\tN = (21,21)\n\n\tOp0 = (19,20)\n\tOp1 = (16,18)\n\tOp1_uimm3 = (16,18)\n\tOp2 = (5,7)\n\tOp2_uimm3 = (5,7)\n\tQ = (30,30)\n\tS = (29,29)\n\n\tScale = (10,15)\n\n\texcCode = (21,23)\n\texcCode2 = (2,4)\n\n\timm7Low = (5,11)\n\n\tcmode = (12,15)\n\timm4 = (11,14)\n\timm5 = (5,9)\n\tl = (21,21)\n\tll = (0,1)\n\tm = (31,31)\n\tmode = (19,20)\n\tn = (22,22)\n\to0 = (4,4)\n\to1 = (24,24)\n\to2 = (10,10)\n\n\to3 = (4,4)\n\top = (30,30)\n\n\tfpccmp.op = (4,4)\n\tfpcmp.op = (14,15)\n\n\top2 = (16,20)\n\n\top3 = (10,15)\n\top4 = (0,4)\n\topc = (29,30)\n\topc.indexmode = (10,11)\n\n\top.dp3 = (29,30)\n\top.dp3_o0 = (15,15)\n\top.dp3_op31 = (21,23)\n\top.dp3_op54 = (29,30)\n\n\topcode2 = (10,15)\n\tdp1.opcode2 = (16,20)\n\tfpcmp.opcode2 = (0,4)\n\topt = (22,23)\n\toption = (13,15)\n\toptionlo = (13,13)\n\tq = (30,30)\n\trmode = (19,20)\n\ts = (29,29)\n\n\tsize.ldstr = (30,31)\n\n\tshift = (22,23)\n\tadvSIMD3.size = (22,23)\n\tsize.neon = (10,11)\n\n\tsize_high = (23,23)\n\tftype = (22,23)\n\tu = (29,29)\n\tv = (26,26)\n\n\t# SVE tokens\n\n\tZd = (0,4)\n\tZt = (0,4)\n\tZtt = (0,4)\n\tZttt = (0,4)\n\tZtttt = (0,4)\n\tZe = (16,20)\n\tZm = (16,20)\n\tZn = (5,9)\n\tZt2 = (10,14)\n\n\tsve_b_00 = (0,0)\n\tsve_b_0001 = (0,1)\n\tsve_b_01 = (1,1)\n\tsve_b_02 = (2,2)\n\tsve_b_03 = (3,3)\n\tsve_b_04 = (4,4)\n\tsve_b_0409 = (4,9)\n\tsve_b_0609 = (6,9)\n\tsve_b_09 = (9,9)\n\tsve_b_10 = (10,10)\n\tsve_b_1015 = (10,15)\n\tsve_b_1019 = (10,19)\n\tsve_b_1021 = (10,21)\n\tsve_b_11 = (11,11)\n\tsve_b_1112 = (11,12)\n\tsve_b_1115 = (11,15)\n\tsve_b_12 = (12,12)\n\tsve_b_1215 = (12,15)\n\tsve_b_13 = (13,13)\n\tsve_b_1315 = (13,15)\n\tsve_b_1321 = (13,21)\n\tsve_b_14 = (14,14)\n\tsve_b_1415 = (14,15)\n\tsve_b_1416 = (14,16)\n\tsve_b_1419 = (14,19)\n\tsve_b_1421 = (14,21)\n\tsve_b_15 = (15,15)\n\tsve_b_16 = (16,16)\n\tsve_b_17 = (17,17)\n\tsve_b_1718 = (17,18)\n\tsve_b_1719 = (17,19)\n\tsve_b_1720 = (17,20)\n\tsve_b_1721 = (17,21)\n\tsve_b_1731 = (17,31)\n\tsve_b_18 = (18,18)\n\tsve_b_1821 = (18,21)\n\tsve_b_1831 = (18,31)\n\tsve_b_1921 = (19,21)\n\tsve_b_20 = (20,20)\n\tsve_b_2021 = (20,21)\n\tsve_b_2022 = (20,22)\n\tsve_b_21 = (21,21)\n\tsve_b_2122 = (21,22)\n\tsve_b_2131 = (21,31)\n\tsve_b_22 = (22,22)\n\tsve_b_2224 = (22,24)\n\tsve_b_2231 = (22,31)\n\tsve_b_23 = (23,23)\n\tsve_b_2331 = (23,31)\n\tsve_b_24 = (24,24)\n\tsve_b_2429 = (24,29)\n\tsve_b_2431 = (24,31)\n\tsve_b_2531 = (25,31)\n\tsve_b_3031 = (30,31)\n\tsve_float_dec = (5,8)\n\tsve_float_exp = (9,11)\n\tsve_i1_05 = (5,5)\n\tsve_i1_20 = (20,20)\n\tsve_i2_1920 = (19,20)\n\tsve_i3h_22 = (22,22)\n\tsve_i3l_1920 = (19,20)\n\tsve_imm13_0517 = (5,17)\n\tsve_imm2_2223 = (22,23)\n\tsve_imm3_0507 = (5,7)\n\tsve_imm3_1618 = (16,18)\n\tsve_imm4_1619 = (16,19)\n\tsve_imm4s_1619 = (16,19) signed\n\tsve_imm5_0509 = (5,9)\n\tsve_imm5s_0509 = (5,9) signed\n\tsve_imm5_1620 = (16,20)\n\tsve_imm5s_1620 = (16,20) signed\n\tsve_imm5b_1620 = (16,20) signed\n\tsve_imm6_0510 = (5,10)\n\tsve_imm6s_0510 = (5,10) signed\n\tsve_imm6_1621 = (16,21)\n\tsve_imm6s_1621 = (16,21) signed\n\tsve_imm7_1420 = (14,20)\n\tsve_imm8_0512 = (5,12)\n\tsve_imm8s_0512 = (5,12) signed\n\tsve_imm8h_1620 = (16,20)\n\tsve_imm8l_1012 = (10,12)\n\tsve_imm9h_1621 = (16,21)\n\tsve_imm9hs_1621 = (16,21) signed\n\tsve_imm9l_1012 = (10,12)\n\tsve_m_04 = (4,4)\n\tsve_m_14 = (14,14)\n\tsve_m_16 = (16,16)\n\tsve_msz_1011 = (10,11)\n\tsve_pattern_0509 = (5,9)\n\tsve_pd_0003 = (0,3)\n\tsve_pdm_0003 = (0,3)\n\tsve_pdn_0003 = (0,3)\n\tsve_pg_0508 = (5,8)\n\tsve_pg_1012 = (10,12)\n\tsve_pg_1013 = (10,13)\n\tsve_pg_1619 = (16,19)\n\tsve_pm_1619 = (16,19)\n\tsve_pn_0508 = (5,8)\n\tsve_prfop_0003 = (0,3)\n\tsve_pt_0003 = (0,3)\n\tsve_rd_0004 = (0,4)\n\tsve_rdn_0004 = (0,4)\n\tsve_rm_0509 = (5,9)\n\tsve_rm_1620 = (16,20)\n\tsve_rn_0509 = (5,9)\n\tsve_rn_1620 = (16,20)\n\tsve_rot_1011 = (10,11)\n\tsve_rot_1314 = (13,14)\n\tsve_rot_16 = (16,16)\n\tsve_s_22 = (22,22)\n\tsve_sf_12 = (12,12)\n\tsve_sh_13 = (13,13)\n\tsve_size_2122 = (21,22)\n\tsve_size_2223 = (22,23)\n\tsve_sz_22 = (22,22)\n\tsve_tsz_1620 = (16,20)\n\tsve_tszh_2223 = (22,23)\n\tsve_tszl_0809 = (8,9)\n\tsve_tszl_1920 = (19,20)\n\tsve_vd_0004 = (0,4)\n\tsve_vdn_0004 = (0,4)\n\tsve_vm_0509 = (5,9)\n\tsve_vn_0509 = (5,9)\n\tsve_xs_14 = (14,14)\n\tsve_xs_22 = (22,22)\n\tsve_za_0509 = (5,9)\n\tsve_za_1620 = (16,20)\n\tsve_zd_0004 = (0,4)\n\tsve_zda_0004 = (0,4)\n\tsve_zdn_0004 = (0,4)\n\tsve_zm_0509 = (5,9)\n\tsve_zm_1618 = (16,18)\n\tsve_zm_1619 = (16,19)\n\tsve_zm_1620 = (16,20)\n\tsve_zn_0509 = (5,9)\n\tsve_zt_0004 = (0,4)\n\tsve_ztt_0004 = (0,4)\n\tsve_zttt_0004 = (0,4)\n\tsve_ztttt_0004 = (0,4)\n;\n\n# SECTION variables and variable names\n\nattach variables [ Zd Ze Zm Zn Zt Zt2 ]\n[\n\tz0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31\n];\n\nattach variables [ Ztt ]\n[\n\tz1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0\n];\n\nattach variables [ Zttt ]\n[\n\tz2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1\n];\n\nattach variables [ Ztttt ]\n[\n\tz3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 z2\n];\n\nattach variables [ aa_Xn aa_Xm aa_Xs aa_Xd aa_Xt aa_Xa ]\n[\n\tx0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15\n\tx16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 xzr\n];\n\nattach variables [ aa_Xss aa_Xtt ]\n[\n\tx1 _ x3 _ x5 _ x7 _ x9 _ x11 _ x13 _ x15\n\t_ x17 _ x19 _ x21 _ x23 _ x25 _ x27 _ x29 _ xzr _\n];\n\nattach variables [ aa_Wn aa_Wm aa_Ws aa_Wd aa_Wt aa_Wa ]\n[\n\tw0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15\n\tw16 w17 w18 w19 w20 w21 w22 w23 w24 w25 w26 w27 w28 w29 w30 wzr\n];\n\nattach variables [ aa_Wss aa_Wtt ]\n[\n\tw1 _ w3 _ w5 _ w7 _ w9 _ w11 _ w13 _ w15\n\t_ w17 _ w19 _ w21 _ w23 _ w25 _ w27 _ w29 _ wzr _\n];\n\nattach variables [ Rm_VPR128 Rn_VPR128 Rd_VPR128 Rt_VPR128 Rt2_FPR128 Re_VPR128 Rt_FPR128 Ra_VPR128 ]\n[\n\tq0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31\n];\n\nattach variables [ Rnn_VPR128 Rtt_VPR128 ]\n[\n\tq1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31\n\tq0\n];\n\nattach variables [ Rnnn_VPR128 Rttt_VPR128 ]\n[\n\tq2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31\n\tq0 q1\n];\n\nattach variables [ Rnnnn_VPR128 Rtttt_VPR128 ]\n[\n\tq3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31\n\tq0 q1 q2\n];\n\nattach names [ vRm_VPR128 vRn_VPR128 vRd_VPR128 vRe_VPR128 vRa_VPR128 ]\n[\n\tv0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31\n];\n\nattach names [ vRnn_VPR128 ]\n[\n\tv1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31\n\tv0\n];\n\nattach names [ vRnnn_VPR128 ]\n[\n\tv2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31\n\tv0 v1\n];\n\nattach names [ vRnnnn_VPR128 ]\n[\n\tv3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31\n\tv0 v1 v2\n];\n\nattach variables [ Rm_VPR128Lo Re_VPR128Lo ] [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ];\n\nattach names [ vRm_VPR128Lo vRe_VPR128Lo ] [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 ];\n\nattach variables [ Rm_VPR64 Rn_VPR64 Rd_VPR64 Rt_VPR64 ]\n[\n\td0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15\n\td16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31\n];\n\nattach variables [ Rtt_VPR64 ]\n[\n\td1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15\n\td16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0\n];\n\nattach variables [ Rttt_VPR64 ]\n[\n\td2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15\n\td16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 d1\n];\n\nattach variables [ Rtttt_VPR64 ]\n[\n\td3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15\n\td16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 d1 d2\n];\n\nattach names [ vRm_VPR64 vRn_VPR64 vRd_VPR64 ]\n[\n\tv0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31\n];\n\nattach variables [ Rm_FPR64 Rn_FPR64 Rd_FPR64 Rd_FPR64_2 Rt2_FPR64 Ra_FPR64 Rt_FPR64 ]\n[\n\td0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15\n\td16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31\n];\n\nattach variables [ Rm_FPR32 Rn_FPR32 Rd_FPR32 Rd_FPR32_2 Rt2_FPR32 Ra_FPR32 Rt_FPR32 ]\n[\n\ts0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15\n\ts16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31\n];\n\nattach variables [ Rm_FPR16 Rn_FPR16 Rd_FPR16 Rd_FPR16_2 Rt_FPR16 Ra_FPR16 ]\n[\n\th0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15\n\th16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31\n];\n\nattach variables [ Rm_FPR8 Rn_FPR8 Rd_FPR8 Rd_FPR8_2 Rt_FPR8 ]\n[\n\tb0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15\n\tb16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31\n];\n\nattach variables [ Vt ]\n[\n\tq0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31\n];\n\nattach variables [ Vtt ]\n[\n\tq1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0\n];\n\nattach variables [ Vttt ]\n[\n\tq2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 q1\n];\n\nattach variables [ Vtttt ]\n[\n\tq3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15\n\tq16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 q1 q2\n];\n\nattach names [ vVt ]\n[\n\tv0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31\n];\n\nattach names [ vVtt ]\n[\n\tv1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0\n];\n\nattach names [ vVttt ]\n[\n\tv2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 v1\n];\n\nattach names [ vVtttt ]\n[\n\tv3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 v1 v2\n];\n\nattach names [ aa_prefetch ]\n[\n\tPLDL1KEEP PLDL1STRM PLDL2KEEP PLDL2STRM PLDL3KEEP PLDL3STRM P_0x06 P_0x07\n\tPLIL1KEEP PLIL1STRM PLIL2KEEP PLIL2STRM PLIL3KEEP PLIL3STRM P_0x0e P_0x0f\n\tPSTL1KEEP PSTL1STRM PSTL2KEEP PSTL2STRM PSTL3KEEP PSTL3STRM\n\tP_0x16 P_0x17 P_0x18 P_0x19 P_0x1a P_0x1b P_0x1c P_0x1d P_0x1e P_0x1f\n];\n\nattach names [ CRm_dbarrier_op ] [ _ OSHLD OSHST OSH _ NSHLD NSHST NSH _ ISHLD ISHST ISH _ LD ST SY ];\n\n# SVE registers and names\n\nattach variables [ sve_zm_1618 ]\n[\n\tz0 z1 z2 z3 z4 z5 z6 z7\n];\n\nattach variables [ sve_zm_1619 ]\n[\n\tz0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n];\n\nattach variables [ sve_za_0509 sve_za_1620 sve_zd_0004 sve_zda_0004 sve_zdn_0004 sve_zm_0509 sve_zm_1620 sve_zn_0509 sve_zt_0004 ]\n[\n\tz0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31\n];\n\nattach variables [ sve_ztt_0004 ]\n[\n\tz1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0\n];\n\nattach variables [ sve_zttt_0004 ]\n[\n\tz2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1\n];\n\nattach variables [ sve_ztttt_0004 ]\n[\n\tz3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15\n\tz16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 z2\n];\n\nattach variables [ sve_pg_1012 ]\n[\n\tp0 p1 p2 p3 p4 p5 p6 p7\n];\n\nattach variables [ sve_pd_0003 sve_pdm_0003 sve_pdn_0003 sve_pg_0508 sve_pg_1013 sve_pg_1619 sve_pm_1619 sve_pn_0508 sve_pt_0003 ]\n[\n\tp0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15\n];\n\nattach names [ sve_sz_22 ] [ b h ];\nattach names [ sve_msz_1011 ] [ \"\" \" #1\" \" #2\" \" #3\" ];\nattach names [ sve_rot_16 ] [ \"#90\" \"#270\" ];\nattach names [ sve_rot_1314 ] [ \"#0\" \"#90\" \"#180\" \"#270\" ];\nattach names [ sve_rot_1011 ] [ \"#0\" \"#90\" \"#180\" \"#270\" ];\n\n# SECTION subtables\n\nRm_GPR32: aa_Wm is aa_Wm { export aa_Wm; }\nRm_GPR32: wzr is aa_Wm=31 & wzr { tmp:4 = 0; export tmp; }\n\nRd_GPR32: aa_Wd is aa_Wd { export aa_Wd; }\nRd_GPR32: wzr is aa_Wd=31 & wzr { tmp:4 = 0; export tmp; }\nRd_GPR32_2: aa_Wd is aa_Wd { export aa_Wd; }\nRd_GPR32_2: wzr is aa_Wd=31 & wzr { tmp:4 = 0; export tmp; }\n\nRd_GPR32xsp: aa_Wd is aa_Wd { export aa_Wd; }\nRd_GPR32xsp: wsp is aa_Wd=31 & wsp { export wsp; }\n\nRd_GPR32wsp: Rd_GPR32xsp is Rd_GPR32xsp { export Rd_GPR32xsp; }\n\nRn_GPR32: aa_Wn is aa_Wn { export aa_Wn; }\nRn_GPR32: wzr is aa_Wn=31 & wzr { tmp:4 = 0; export tmp; }\n\nRa_GPR32: aa_Wa is aa_Wa { export aa_Wa; }\nRa_GPR32: wzr is aa_Wa=31 & wzr { tmp:4 = 0; export tmp; }\n\nRt2_GPR32: aa_Wa is aa_Wa { export aa_Wa; }\nRt2_GPR32: wzr is aa_Wa=31 & wzr { tmp:4 = 0; export tmp; }\n\nRn_GPR32xsp: aa_Wn is aa_Wn { export aa_Wn; }\nRn_GPR32xsp: wsp is aa_Wn=31 & wsp { export wsp; }\n\nRn_GPR32wsp: aa_Wn is aa_Wn { export aa_Wn; }\nRn_GPR32wsp: wsp is aa_Wn=31 & wsp { export wsp; }\n\nRt_GPR32: aa_Wt is aa_Wt { export aa_Wt; }\nRt_GPR32: wzr is aa_Wt=31 & wzr { tmp:4 = 0; export tmp; }\n\nRm_GPR64: aa_Xm is aa_Xm { export aa_Xm; }\nRm_GPR64: xzr is aa_Xm=31 & xzr { export 0:8; }\n\nRd_GPR64: aa_Xd is aa_Xd { export aa_Xd; }\nRd_GPR64: xzr is aa_Xd=31 & xzr { tmp:8 = 0; export tmp; }\nRd_GPR64_2: aa_Xd is aa_Xd { export aa_Xd; }\nRd_GPR64_2: xzr is aa_Xd=31 & xzr { tmp:8 = 0; export tmp; }\n\nRa_GPR64: aa_Xa is aa_Xa { export aa_Xa; }\nRa_GPR64: xzr is aa_Xa=31 & xzr { tmp:8 = 0; export tmp; }\n\nRt2_GPR64: aa_Xa is aa_Xa { export aa_Xa; }\nRt2_GPR64: xzr is aa_Xa=31 & xzr { tmp:8 = 0; export tmp; }\n\nRd_GPR64xsp: aa_Xd is aa_Xd { export aa_Xd; }\nRd_GPR64xsp: sp is aa_Xd=31 & sp { export sp; }\n\nRn_GPR64: aa_Xn is aa_Xn { export aa_Xn; }\nRn_GPR64: xzr is aa_Xn=31 & xzr { tmp:8 = 0; export tmp; }\n\nRt_GPR64: aa_Xt is aa_Xt { export aa_Xt; }\nRt_GPR64: xzr is aa_Xt=31 & xzr { tmp:8 = 0; export tmp; }\n\nRn_GPR64xsp: aa_Xn is aa_Xn { export aa_Xn; }\nRn_GPR64xsp: sp is aa_Xn=31 & sp { export sp; }\n\nRm_GPR64xsp: aa_Xm is aa_Xm { export aa_Xm; }\nRm_GPR64xsp: sp is aa_Xm=31 & sp { export sp; }\n\nRt_GPR64xsp: aa_Xt is aa_Xt { export aa_Xt; }\nRt_GPR64xsp: sp is aa_Xt=31 & sp { export sp; }\n\nRs_GPR32: Rm_GPR32 is Rm_GPR32 { export Rm_GPR32; }\nRs_GPR64: Rm_GPR64 is Rm_GPR64 { export Rm_GPR64; }\n\nRm_fpz16: \"#0.0\" is Rm { tmp:2 = int2float(0:2); export tmp; }\nRm_fpz32: \"#0.0\" is Rm { tmp:4 = int2float(0:4); export tmp; }\nRm_fpz64: \"#0.0\" is Rm { tmp:8 = int2float(0:8); export tmp; }\n\nRd_VPR128.16B: vRd_VPR128^\".16B\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.8H: vRd_VPR128^\".8H\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.4S: vRd_VPR128^\".4S\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.2S: vRd_VPR128^\".2S\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.2D: vRd_VPR128^\".2D\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.1Q: vRd_VPR128^\".1Q\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\n\nRn_VPR128.16B: vRn_VPR128^\".16B\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRnn_VPR128.16B: vRnn_VPR128^\".16B\" is Rnn_VPR128 & vRnn_VPR128 { export Rnn_VPR128; }\nRnnn_VPR128.16B: vRnnn_VPR128^\".16B\" is Rnnn_VPR128 & vRnnn_VPR128 { export Rnnn_VPR128; }\nRnnnn_VPR128.16B: vRnnnn_VPR128^\".16B\" is Rnnnn_VPR128 & vRnnnn_VPR128 { export Rnnnn_VPR128; }\n\nRn_VPR128.8B: vRn_VPR128^\".8B\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.8H: vRn_VPR128^\".8H\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.4S: vRn_VPR128^\".4S\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.4H: vRn_VPR128^\".4H\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.2D: vRn_VPR128^\".2D\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\n\nRm_VPR128.8B: vRm_VPR128^\".8B\" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }\nRm_VPR128.16B: vRm_VPR128^\".16B\" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }\nRm_VPR128.8H: vRm_VPR128^\".8H\" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }\nRm_VPR128.4S: vRm_VPR128^\".4S\" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }\nRm_VPR128.4H: vRm_VPR128^\".4H\" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }\nRm_VPR128.2D: vRm_VPR128^\".2D\" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }\n\nRa_VPR128.16B: vRa_VPR128^\".16B\" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }\n# Ra_VPR128.8H: vRa_VPR128^\".8H\" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }\nRa_VPR128.4S: vRa_VPR128^\".4S\" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }\n# Ra_VPR128.2D: vRa_VPR128^\".2D\" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }\n# Ra_VPR128.1Q: vRa_VPR128^\".1Q\" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }\n\nRd_VPR64.8B: vRd_VPR64^\".8B\" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }\nRd_VPR64.4H: vRd_VPR64^\".4H\" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }\nRd_VPR64.2S: vRd_VPR64^\".2S\" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }\nRd_VPR64.1D: vRd_VPR64^\".1D\" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }\n\nRn_VPR64.8B: vRn_VPR64^\".8B\" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }\nRn_VPR64.4H: vRn_VPR64^\".4H\" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }\nRn_VPR64.2S: vRn_VPR64^\".2S\" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }\nRn_VPR64.1D: vRn_VPR64^\".1D\" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }\n\nRm_VPR64.8B: vRm_VPR64^\".8B\" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }\nRm_VPR64.4H: vRm_VPR64^\".4H\" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }\nRm_VPR64.2S: vRm_VPR64^\".2S\" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }\nRm_VPR64.1D: vRm_VPR64^\".1D\" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }\n\nRd_VPR128.B: vRd_VPR128^\".B\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.H: vRd_VPR128^\".H\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.S: vRd_VPR128^\".S\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\nRd_VPR128.D: vRd_VPR128^\".D\" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }\n\nRn_VPR128.B: vRn_VPR128^\".B\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.H: vRn_VPR128^\".H\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.S: vRn_VPR128^\".S\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\nRn_VPR128.D: vRn_VPR128^\".D\" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }\n\nRe_VPR128.B: vRe_VPR128^\".B\" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }\nRe_VPR128.H: vRe_VPR128^\".H\" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }\nRe_VPR128.S: vRe_VPR128^\".S\" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }\nRe_VPR128.D: vRe_VPR128^\".D\" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }\n\nRe_VPR128Lo.H: vRe_VPR128Lo^\".H\" is Re_VPR128Lo & vRe_VPR128Lo { export Re_VPR128Lo; }\n\nbr_cc_op: \"eq\" is br_cond_op=0 { export ZR; }\nbr_cc_op: \"ne\" is br_cond_op=1 { tmp:1 = !ZR; export tmp; }\nbr_cc_op: \"cs\" is br_cond_op=2 { export CY; }\nbr_cc_op: \"cc\" is br_cond_op=3 { tmp:1 = !CY; export tmp; }\nbr_cc_op: \"mi\" is br_cond_op=4 { export NG; }\nbr_cc_op: \"pl\" is br_cond_op=5 { tmp:1 = !NG; export tmp; }\nbr_cc_op: \"vs\" is br_cond_op=6 { export OV; }\nbr_cc_op: \"vc\" is br_cond_op=7 { tmp:1 = !OV; export tmp; }\nbr_cc_op: \"hi\" is br_cond_op=8 { tmp:1 = CY && (!ZR); export tmp; }\nbr_cc_op: \"ls\" is br_cond_op=9 { tmp:1 = (!CY) || ZR; export tmp; }\nbr_cc_op: \"ge\" is br_cond_op=10 { tmp:1 = (NG==OV); export tmp; }\nbr_cc_op: \"lt\" is br_cond_op=11 { tmp:1 = (NG!=OV); export tmp; }\nbr_cc_op: \"gt\" is br_cond_op=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; }\nbr_cc_op: \"le\" is br_cond_op=13 { tmp:1 = ZR || (NG!=OV); export tmp; }\nbr_cc_op: \"al\" is br_cond_op=14 { export 1:1; }\nbr_cc_op: \"nv\" is br_cond_op=15 { export 1:1; }\n\nBranchCondOp: br_cc_op is br_cc_op { export br_cc_op; }\n\ncc_op: \"eq\" is cond_op=0 { export ZR; }\ncc_op: \"ne\" is cond_op=1 { tmp:1 = !ZR; export tmp; }\ncc_op: \"cs\" is cond_op=2 { export CY; }\ncc_op: \"cc\" is cond_op=3 { tmp:1 = !CY; export tmp; }\ncc_op: \"mi\" is cond_op=4 { export NG; }\ncc_op: \"pl\" is cond_op=5 { tmp:1 = !NG; export tmp; }\ncc_op: \"vs\" is cond_op=6 { export OV; }\ncc_op: \"vc\" is cond_op=7 { tmp:1 = !OV; export tmp; }\ncc_op: \"hi\" is cond_op=8 { tmp:1 = CY && (!ZR); export tmp; }\ncc_op: \"ls\" is cond_op=9 { tmp:1 = (!CY) || ZR; export tmp; }\ncc_op: \"ge\" is cond_op=10 { tmp:1 = (NG==OV); export tmp; }\ncc_op: \"lt\" is cond_op=11 { tmp:1 = (NG!=OV); export tmp; }\ncc_op: \"gt\" is cond_op=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; }\ncc_op: \"le\" is cond_op=13 { tmp:1 = ZR || (NG!=OV); export tmp; }\ncc_op: \"al\" is cond_op=14 { export 1:1; }\ncc_op: \"nv\" is cond_op=15 { export 1:1; }\n\nCondOp: cc_op is cc_op { export cc_op; }\n\ninv_cc_op: \"eq\" is cond_op=1 { export ZR; }\ninv_cc_op: \"ne\" is cond_op=0 { tmp:1 = !ZR; export tmp; }\ninv_cc_op: \"cs\" is cond_op=3 { export CY; }\ninv_cc_op: \"cc\" is cond_op=2 { tmp:1 = !CY; export tmp; }\ninv_cc_op: \"mi\" is cond_op=5 { export NG; }\ninv_cc_op: \"pl\" is cond_op=4 { tmp:1 = !NG; export tmp; }\ninv_cc_op: \"vs\" is cond_op=7 { export OV; }\ninv_cc_op: \"vc\" is cond_op=6 { tmp:1 = !OV; export tmp; }\ninv_cc_op: \"hi\" is cond_op=9 { tmp:1 = CY && (!ZR); export tmp; }\ninv_cc_op: \"ls\" is cond_op=8 { tmp:1 = (!CY) || ZR; export tmp; }\ninv_cc_op: \"ge\" is cond_op=11 { tmp:1 = (NG==OV); export tmp; }\ninv_cc_op: \"lt\" is cond_op=10 { tmp:1 = (NG!=OV); export tmp; }\ninv_cc_op: \"gt\" is cond_op=13 { tmp:1 = (!ZR) && (NG==OV); export tmp; }\ninv_cc_op: \"le\" is cond_op=12 { tmp:1 = ZR || (NG!=OV); export tmp; }\ninv_cc_op: \"al\" is cond_op=15 { export 1:1; }\ninv_cc_op: \"nv\" is cond_op=14 { export 1:1; }\n\nInvCondOp: inv_cc_op is inv_cc_op { export inv_cc_op; }\n\nSBIT_CZNO: is b_29=0 { } # Do nothing to the flag bits\nSBIT_CZNO: \"s\" is b_29=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }\n\nImm_uimm_exact8: \"#\"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; }\nImm_uimm_exact16: \"#\"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; }\nImm_uimm_exact32: \"#\"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; }\n\nImm_shr_imm8: \"#\"^val is b_1922 & b_1618 [ val = (8*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }\nImm_shr_imm16: \"#\"^val is b_1922 & b_1618 [ val = (16*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }\nImm_shr_imm32: \"#\"^val is b_1922 & b_1618 [ val = (32*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }\nImm_shr_imm64: \"#\"^val is b_1922 & b_1618 [ val = (64*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }\n\nNZCVImm_uimm4: \"#\"^b_0003 is b_0003 { export *[const]:1 b_0003; }\nUImm5: \"#\"^b_1620 is b_1620 { export *[const]:4 b_1620; }\nUImm6: \"#\"^b_1520 is b_1520 { export *[const]:4 b_1520; }\n\nCRm_uimm4: \"#\"^b_0811 is b_0811 { export *[const]:1 b_0811; }\n\nCRm_uimm4_def15: \"#\"^b_0811 is b_0811 { export *[const]:1 b_0811; }\nCRm_uimm4_def15: is b_0811=0xf { export 15:1; }\n\nLSB_bitfield32_imm: \"#\"^imm6 is b_1515=0 & imm6 { export *[const]:8 imm6; }\nLSB_bitfield64_imm: \"#\"^imm6 is imm6 { export *[const]:8 imm6; }\n\nLSB_bitfield32_imm_shift: \"#\"^shift is b_1515=0 & imm6 [ shift = 31 - imm6; ] { export *[const]:4 shift; }\nLSB_bitfield64_imm_shift: \"#\"^shift is imm6 [ shift = 63 - imm6; ] { export *[const]:8 shift; }\n\nAddrLoc14: reloc is simm14 [ reloc = inst_start + (4*simm14); ] { export *[const]:8 reloc; }\n\nAddrLoc19: reloc is simm19 [ reloc = inst_start + (4*simm19); ] { export *[const]:8 reloc; }\n\nAddrLoc26: reloc is simm26 [ reloc = inst_start + (4*simm26); ] { export *[const]:8 reloc; }\n\nAddr14: AddrLoc14 is AddrLoc14 { export *:8 AddrLoc14; }\n\nAddr19: AddrLoc19 is AddrLoc19 { export *:8 AddrLoc19; }\n\nAddr26: AddrLoc26 is AddrLoc26 { export *:8 AddrLoc26; }\n\nAdrReloff: reloff is b_31=1 & immlo & immhi [ reloff = ((inst_start) & ~0xfff) + ( ((immhi << 2) | immlo) << 12 ); ] { export *[const]:8 reloff; }\nAdrReloff: reloff is b_31=0 & immlo & immhi [ reloff = (inst_start) + ( ((immhi << 2) | immlo) ); ] { export *[const]:8 reloff; }\n\nImmShift32: \"#\"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:4 imm12; }\nImmShift32: \"#\"^imm12, \"LSL #12\" is aa_extreg_shift=1 & imm12 { tmp:4 = imm12 << 12; export tmp; }\n\nImmShift64: \"#\"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:8 imm12; }\nImmShift64: \"#\"^imm12, \"LSL #12\" is aa_extreg_shift=1 & imm12 { tmp:8 = imm12 << 12; export tmp; }\n\n# TODO some instructions can't do ROR operation on immediate!\n\nRegShift32: Rm_GPR32, \"LSL #\"^imm6 is Rm_GPR32 & aa_extreg_shift = 0 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 << imm6; export tmp; }\nRegShift32: Rm_GPR32 is Rm_GPR32 & aa_extreg_shift = 0 & imm6=0 { export Rm_GPR32; }\nRegShift32: Rm_GPR32, \"LSR #\"^imm6 is Rm_GPR32 & aa_extreg_shift = 1 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 >> imm6; export tmp; }\nRegShift32: Rm_GPR32, \"ASR #\"^imm6 is Rm_GPR32 & aa_extreg_shift = 2 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 s>> imm6; export tmp; }\n\nRegShift32Log: RegShift32 is aa_extreg_shift & RegShift32 { export RegShift32; }\nRegShift32Log: Rm_GPR32, \"ROR #\"^imm6 is aa_extreg_shift=3 & Rm_GPR32 & imm6 & b_1515=0 { tmp:4 = (Rm_GPR32 >> imm6) | (Rm_GPR32 << (32 - imm6)); export tmp; }\n\nRegShift64: Rm_GPR64, \"LSL #\"^imm6 is Rm_GPR64 & aa_extreg_shift = 0 & imm6 { tmp:8 = Rm_GPR64 << imm6; export tmp; }\nRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_shift = 0 & imm6=0 { export Rm_GPR64; }\nRegShift64: Rm_GPR64, \"LSR #\"^imm6 is Rm_GPR64 & aa_extreg_shift = 1 & imm6 { tmp:8 = Rm_GPR64 >> imm6; export tmp; }\nRegShift64: Rm_GPR64, \"ASR #\"^imm6 is Rm_GPR64 & aa_extreg_shift = 2 & imm6 { tmp:8 = Rm_GPR64 s>> imm6; export tmp; }\n\nRegShift64Log: RegShift64 is aa_extreg_shift & RegShift64 & aa_Xn & aa_Xm & imm6 { export RegShift64; }\nRegShift64Log: Rm_GPR64, \"ROR #\"^imm6 is aa_extreg_shift=3 & Rm_GPR64 & aa_Xn & aa_Xm & imm6 { tmp:8 = (Rm_GPR64 >> imm6) | (Rm_GPR64 << (64 - imm6)); export tmp; }\n\nRegShiftVal32: \" #\"^b_1012 is aa_extreg_imm3=1 & b_1012 { export 1:4; }\nRegShiftVal32: \" #\"^b_1012 is aa_extreg_imm3=2 & b_1012 { export 2:4; }\nRegShiftVal32: \" #\"^b_1012 is aa_extreg_imm3=3 & b_1012 { export 3:4; }\nRegShiftVal32: \" #\"^b_1012 is aa_extreg_imm3=4 & b_1012 { export 4:4; }\nRegShiftVal32: \"\" is aa_extreg_imm3=0 { export 0:4; }\n\nLSL_Sp_Special32: Rm_GPR32, \"LSL \" is Rm_GPR32 & aa_extreg_imm3 { export Rm_GPR32; }\nLSL_Sp_Special32: Rm_GPR32 is Rm_GPR32 & aa_extreg_imm3=0 { export Rm_GPR32; }\n\nExtendReg32: Rm_GPR32, \"UXTB \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:4 = zext(tmp0:1); export tmp; }\nExtendReg32: Rm_GPR32, \"UXTH \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:4 = zext(tmp0:2); export tmp; }\nExtendReg32: LSL_Sp_Special32 is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 & b_29=1 & (Rn=0x1f) & LSL_Sp_Special32 { export Rm_GPR32; }\nExtendReg32: LSL_Sp_Special32 is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 & b_29=0 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special32 { export Rm_GPR32; }\nExtendReg32: Rm_GPR32, \"UXTW \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:4 = Rm_GPR32; export tmp; }\nExtendReg32: Rm_GPR32, \"UXTX \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=3 { tmp:4 = Rm_GPR32; export tmp; }\nExtendReg32: Rm_GPR32, \"SXTB \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:4 = sext(tmp0:1); export tmp; }\nExtendReg32: Rm_GPR32, \"SXTH \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:4 = sext(tmp0:2); export tmp; }\n\nExtendReg32: Rm_GPR32, \"SXTW \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:4 = Rm_GPR32; export tmp; }\nExtendReg32: Rm_GPR32, \"SXTX \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=7 { tmp:4 = Rm_GPR32; export tmp; }\n\nExtendRegShift32: ExtendReg32^RegShiftVal32 is aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg32 & RegShiftVal32 { tmp:4 = ExtendReg32; tmp = tmp << RegShiftVal32; export tmp; }\nExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=2 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }\nExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }\nExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=6 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }\nExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }\n\nImm12_addsubimm_operand_i32_negimm_lsl0: ImmShift32 is ImmShift32 { export ImmShift32; }\nImm12_addsubimm_operand_i32_negimm_lsl12: ImmShift32 is ImmShift32 { export ImmShift32; }\nImm12_addsubimm_operand_i32_posimm_lsl0: ImmShift32 is ImmShift32 { export ImmShift32; }\nImm12_addsubimm_operand_i32_posimm_lsl12: ImmShift32 is ImmShift32 { export ImmShift32; }\nImm12_addsubimm_operand_i64_negimm_lsl0: ImmShift64 is ImmShift64 { export ImmShift64; }\nImm12_addsubimm_operand_i64_negimm_lsl12: ImmShift64 is ImmShift64 { export ImmShift64; }\nImm12_addsubimm_operand_i64_posimm_lsl0: ImmShift64 is ImmShift64 { export ImmShift64; }\nImm12_addsubimm_operand_i64_posimm_lsl12: ImmShift64 is ImmShift64 { export ImmShift64; }\n\nRegShiftVal64: \" #\"^b_1012 is aa_extreg_imm3=1 & b_1012 { export 1:8; }\nRegShiftVal64: \" #\"^b_1012 is aa_extreg_imm3=2 & b_1012 { export 2:8; }\nRegShiftVal64: \" #\"^b_1012 is aa_extreg_imm3=3 & b_1012 { export 3:8; }\nRegShiftVal64: \" #\"^b_1012 is aa_extreg_imm3=4 & b_1012 { export 4:8; }\nRegShiftVal64: \"\" is aa_extreg_imm3=0 { export 0:8; }\n\nLSL_Sp_Special64: Rm_GPR64, \"LSL \" is Rm_GPR64 & aa_extreg_imm3 { export Rm_GPR64; }\nLSL_Sp_Special64: Rm_GPR64 is Rm_GPR64 & aa_extreg_imm3=0 { export Rm_GPR64; }\n\nExtendReg64: Rm_GPR32, \"UXTB \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:1); export tmp; }\nExtendReg64: Rm_GPR32, \"UXTH \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:2); export tmp; }\nExtendReg64: Rm_GPR32, \"UXTW \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:8 = zext(Rm_GPR32); export tmp; }\nExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=1 & b_25=1 & (Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; }\nExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=0 & b_25=1 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; }\nExtendReg64: Rm_GPR64, \"LSL \" is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29 & b_25=0 { tmp:8 = Rm_GPR64; export tmp; }\nExtendReg64: Rm_GPR64, \"UXTX \" is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 { tmp:8 = Rm_GPR64; export tmp; }\nExtendReg64: Rm_GPR32, \"SXTB \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:1); export tmp; }\nExtendReg64: Rm_GPR32, \"SXTH \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:2); export tmp; }\nExtendReg64: Rm_GPR32, \"SXTW \" is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:8 = sext(Rm_GPR32); export tmp; }\nExtendReg64: Rm_GPR64, \"SXTX \" is Rm_GPR64 & b_2121=1 & aa_extreg_option=7 { tmp:8 = Rm_GPR64; export tmp; }\n\nExtendRegShift64: ExtendReg64^RegShiftVal64\nis aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg64 & RegShiftVal64\n{\n\tbuild ExtendReg64;\n\tbuild RegShiftVal64;\n\ttmp:8 = ExtendReg64;\n\ttmp = tmp << RegShiftVal64;\n\texport tmp;\n}\n\nExtendRegShift64: ExtendReg64 is Rm_GPR64 & aa_extreg_shift = 0 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg64 & RegShiftVal64 { export Rm_GPR64; }\nExtendRegShift64: ExtendReg64 is Rm_GPR64 & aa_extreg_shift = 0 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg64 & RegShiftVal64 { export Rm_GPR64; }\n\nUnscPriv: \"u\" is b_1011=0 { }\nUnscPriv: \"t\" is b_1011=2 { }\n\n# Simple register load or store\naddrReg: \"[\"^Rn_GPR64xsp^\"]\" is Rn_GPR64xsp { export Rn_GPR64xsp; }\n\n# Scaled Offset\naddrUIMM: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]\" is size.ldstr=0 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 0; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]\" is size.ldstr=1 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 1; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]\" is size.ldstr=2 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 2; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]\" is size.ldstr=3 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 3; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }\n\naddrUIMM: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]\" is size.ldstr=0 & b_2729=7 & v=1 & b_2425=1 & b_2323=1 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 4; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp^\"]\" is size.ldstr=0 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp^\"]\" is size.ldstr=1 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp^\"]\" is size.ldstr=2 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp^\"]\" is size.ldstr=3 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\naddrUIMM: \"[\"^Rn_GPR64xsp^\"]\" is size.ldstr=0 & b_2729=7 & v=1 & b_2425=1 & b_2323=1 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\n\n# Address Reg + signed offset -256 to 255\naddr_SIMM9: \"[\"^Rn_GPR64xsp, \"#\"^simm9^\"]\" is Rn_GPR64xsp & simm9 { tmp:8 = Rn_GPR64xsp + simm9; export tmp; }\naddr_SIMM9: \"[\"^Rn_GPR64xsp^\"]\" is Rn_GPR64xsp & simm9=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\n\naddrRegShift64: \"#\"^val is size.ldstr=0 & v=0 & opt & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; }\naddrRegShift64: \"\" is size.ldstr=0 & v=0 & opt & b_1212=0 { export 0:8; }\n\naddrRegShift64: \"#\"^val is size.ldstr=0 & v=1 & opt=0 & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; }\naddrRegShift64: \"\" is size.ldstr=0 & v=1 & opt=0 & b_1212=0 { export 0:8; }\naddrRegShift64: \"#\"^val is size.ldstr=0 & v=1 & opt=1 & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; }\naddrRegShift64: \"\" is size.ldstr=0 & v=1 & opt=1 & b_1212=0 { export 0:8; }\naddrRegShift64: \"#\"^val is size.ldstr=0 & v=1 & opt=2 & b_1212 [ val = b_1212 * 4; ] { export *[const]:8 val; }\naddrRegShift64: \"#\"^val is size.ldstr=0 & v=1 & opt=3 & b_1212 [ val = b_1212 * 4; ] { export *[const]:8 val; }\n\naddrRegShift64: \"#\"^val is size.ldstr=1 & v=0 & opt & b_1212 [ val = b_1212 * 1; ] { export *[const]:8 val; }\naddrRegShift64: \"#\"^val is size.ldstr=1 & v=1 & opt & b_1212 [ val = b_1212 * 1; ] { export *[const]:8 val; }\n\naddrRegShift64: \"#\"^val is size.ldstr=2 & v=0 & opt & b_1212 [ val = b_1212 * 2; ] { export *[const]:8 val; }\naddrRegShift64: \"#\"^val is size.ldstr=2 & v=1 & opt & b_1212 [ val = b_1212 * 2; ] { export *[const]:8 val; }\n\naddrRegShift64: \"#\"^val is size.ldstr=3 & v=0 & opt & b_1212 [ val = b_1212 * 3; ] { export *[const]:8 val; }\naddrRegShift64: \"#\"^val is size.ldstr=3 & v=1 & opt & b_1212 [ val = b_1212 * 3; ] { export *[const]:8 val; }\n\naddrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=2 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }\naddrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=3 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }\naddrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=6 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }\naddrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=7 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }\naddrExtendRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg64 { export Rm_GPR64; }\naddrExtendRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg64 { export Rm_GPR64; }\n\n# unsigned offset\naddrIndexed: addrUIMM is size.ldstr & b_2729=7 & b_2425=1 & addrUIMM { export addrUIMM; }\n\n# unsinged offset unscaled immediate\naddrIndexed: addr_SIMM9 is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & opc.indexmode=0 & addr_SIMM9 { export addr_SIMM9; }\n\n# register unpriviledged\naddrIndexed: addr_SIMM9 is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & opc.indexmode=2 & addr_SIMM9 { export addr_SIMM9; }\n\n# post indexed wback\naddrIndexed: \"[\"^Rn_GPR64xsp^\"]\", \"#\"^simm9\nis size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & Rn_GPR64xsp & simm9 & opc.indexmode=1\n{\n\ttmp:8 = Rn_GPR64xsp;\n\tRn_GPR64xsp = Rn_GPR64xsp + simm9;\n\texport tmp;\n}\n\n# Register, Register offset extended\naddrIndexed: \"[\"^Rn_GPR64xsp, addrExtendRegShift64^\"]\"\nis size.ldstr & b_2729=7 & b_2425=0 & b_2121=1 & Rn_GPR64xsp & opc.indexmode=2 & addrExtendRegShift64\n{\n\ttmp:8 = Rn_GPR64xsp + addrExtendRegShift64;\n\texport tmp;\n}\n\n# pre indexed wback\naddrIndexed: \"[\"^Rn_GPR64xsp, \"#\"^simm9^\"]!\"\nis size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & Rn_GPR64xsp & simm9 & opc.indexmode=3\n{\n\tRn_GPR64xsp = Rn_GPR64xsp + simm9;\n\texport Rn_GPR64xsp;\n}\n\n# For LDRAA/LDRAB\n\n# no offset (with S)\naddrIndexed: \"[\"^Rn_GPR64xsp^\"]\"\nis size.ldstr & b_2729=7 & b_2425=0 & b_22=0 & b_2121=1 & Rn_GPR64xsp & simm9=0 & opc.indexmode=1\n{\n\texport Rn_GPR64xsp;\n}\n\n# offset (with S)\naddrIndexed: \"[\"^Rn_GPR64xsp, \"#\"^sim^\"]\"\nis size.ldstr & b_2729=7 & b_2425=0 & b_22 & b_2121=1 & Rn_GPR64xsp & simm9 & opc.indexmode=1\n[ sim = (b_22 * (-1<<9) | (simm9 & 0x1ff)) << 3; ]\n{\n\ttmp:8 = Rn_GPR64xsp + sim;\n\texport tmp;\n}\n\n# no offset writeback (with S)\naddrIndexed: \"[\"^Rn_GPR64xsp^\"]!\"\nis size.ldstr & b_2729=7 & b_2425=0 & b_22=0 & b_2121=1 & Rn_GPR64xsp & simm9=0 & opc.indexmode=3\n{\n\texport Rn_GPR64xsp;\n}\n\n# pre indexed wback (with S)\naddrIndexed: \"[\"^Rn_GPR64xsp, \"#\"^sim^\"]!\"\nis size.ldstr & b_2729=7 & b_2425=0 & b_22 & b_2121=1 & Rn_GPR64xsp & simm9 & opc.indexmode=3\n[ sim = (b_22 * (-1<<9) | (simm9 & 0x1ff)) << 3; ]\n{\n\tRn_GPR64xsp = Rn_GPR64xsp + sim;\n\texport Rn_GPR64xsp;\n}\n\naddrPairScale: pimm is b_3031=0 & v=0 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; }\naddrPairScale: pimm is b_3031=0 & v=1 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; }\naddrPairScale: pimm is b_3031=2 & v=0 & simm7 [ pimm = simm7 << 3; ] { export *[const]:8 pimm; }\naddrPairScale: pimm is b_3031=1 & v=0 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; }\naddrPairScale: pimm is b_3031=1 & v=1 & simm7 [ pimm = simm7 << 3; ] { export *[const]:8 pimm; }\naddrPairScale: pimm is b_3031=2 & v=1 & simm7 [ pimm = simm7 << 4; ] { export *[const]:8 pimm; }\n\n# Scaled Offset\naddrPairUIMM: \"[\"^Rn_GPR64xsp, \"#\"^addrPairScale^\"]\"\nis sf & Rn_GPR64xsp & addrPairScale & simm7\n{\n\ttmp:8 = Rn_GPR64xsp + addrPairScale;\n\texport tmp;\n}\n\naddrPairUIMM: \"[\"^Rn_GPR64xsp^\"]\"\nis sf & Rn_GPR64xsp & addrPairScale & simm7=0\n{\n\ttmp:8 = Rn_GPR64xsp;\n\texport tmp;\n}\n\n# unsigned offset\naddrPairIndexed: addrPairUIMM\nis b_2729=0b101 & b_2325=0b010 & addrPairUIMM\n{ export addrPairUIMM; }\n\n# unsigned offset, non-temporal hint\naddrPairIndexed: addrPairUIMM\nis b_2729=0b101 & b_2325=0b000 & addrPairUIMM\n{ export addrPairUIMM; }\n\n# post indexed wback\naddrPairIndexed: \"[\"^Rn_GPR64xsp^\"]\", \"#\"^addrPairScale\nis b_2729=0b101 & b_2325=0b001 & Rn_GPR64xsp & addrPairScale\n{\n\ttmp:8 = Rn_GPR64xsp;\n\tRn_GPR64xsp = Rn_GPR64xsp + addrPairScale;\n\texport tmp;\n}\n\n# pre indexed wback\naddrPairIndexed: \"[\"^Rn_GPR64xsp, \"#\"^addrPairScale^\"]!\"\nis b_2729=0b101 & b_2325=0b011 & Rn_GPR64xsp & addrPairScale\n{\n\tRn_GPR64xsp = Rn_GPR64xsp + addrPairScale;\n\texport Rn_GPR64xsp;\n}\n\n#### Undefined behavior on writeback ####\n#\n# Most instructions with writeback have unpredictable behavior when their address input register Rn\n# is the same register as another input, e.g. Rt. For example, LDR x1, [x1, 0x8]! has unpredictable\n# behavior in the ARM spec. Similarly, STR x5, [x5], 0x28 has unpredictable behavior in the spec\n# (but with slightly different possibilities for what forms that unpredictable behavior might take!).\n#\n# One of the few exceptions is STGP, which has no mention of unpredictable behavior. In such cases,\n# it's important to read all registers before addrGranuleIndexed or addrPairGranuleIndexed takes effect,\n# or pre-index writeback will modify the register values used if Rn is the same register as another R.\n#\n# This is an example of how to code a definition for an instruction with no unpredictable behavior:\n#{\n#\t# save the initial register values\n#\tdata1:8 = Rt_GPR64;\n#\tdata2:8 = Rt2_GPR64;\n#\n#\tbuild addrPairGranuleIndexed; # may modify Rt or Rt2, so use data1/data2 instead afterward\n#\n#\t...etc...\n#}\n\nOPTIONAL_XM: is Rm=0b11111 { export 0:8; } # default to XZR if Xm is absent\nOPTIONAL_XM: ,Rm_GPR64 is Rm_GPR64 { export Rm_GPR64; }\n\naddr_granuleSIMM: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]\" is Rn_GPR64xsp & simm9 [ pimm = simm9 << $(LOG2_TAG_GRANULE); ] { tmp:8 = Rn_GPR64xsp + ( simm9 << $(LOG2_TAG_GRANULE) ); export tmp; }\naddr_granuleSIMM: \"[\"^Rn_GPR64xsp^\"]\" is Rn_GPR64xsp & simm9=0 { tmp:8 = Rn_GPR64xsp; export tmp; }\n\n# signed offset\naddrGranuleIndexed: addr_granuleSIMM is opc.indexmode=2 & addr_granuleSIMM { export addr_granuleSIMM; }\n\n# post indexed wback\naddrGranuleIndexed: \"[\"^Rn_GPR64xsp^\"]\", \"#\"^pimm\nis Rn_GPR64xsp & simm9 & opc.indexmode=1\n[ pimm = simm9 << $(LOG2_TAG_GRANULE); ] \n{\n\ttmp:8 = Rn_GPR64xsp;\n\tRn_GPR64xsp = Rn_GPR64xsp + pimm;\n\texport tmp;\n}\n\n# pre indexed wback\naddrGranuleIndexed: \"[\"^Rn_GPR64xsp, \"#\"^pimm^\"]!\"\nis Rn_GPR64xsp & simm9 & opc.indexmode=3\n[ pimm = simm9 << $(LOG2_TAG_GRANULE); ]\n{\n\tRn_GPR64xsp = Rn_GPR64xsp + pimm;\n\ttmp:8 = Rn_GPR64xsp;\n\texport tmp;\n}\n\naddrPairGranuleScale: pimm is simm7 [ pimm = simm7 << $(LOG2_TAG_GRANULE); ] { export *[const]:8 pimm; }\n\n# Scaled Offset\naddrPairGranuleSIMM: \"[\"^Rn_GPR64xsp, \"#\"^addrPairGranuleScale^\"]\"\nis sf & Rn_GPR64xsp & addrPairGranuleScale & simm7\n{\n\ttmp:8 = Rn_GPR64xsp + addrPairGranuleScale;\n\texport tmp;\n}\n\naddrPairGranuleSIMM: \"[\"^Rn_GPR64xsp^\"]\"\nis sf & Rn_GPR64xsp & addrPairGranuleScale & simm7=0\n{\n\ttmp:8 = Rn_GPR64xsp;\n\texport tmp;\n}\n\n\n# signed offset\naddrPairGranuleIndexed: addrPairGranuleSIMM\nis b_2729=0b101 & b_2325=0b010 & addrPairGranuleSIMM\n{ export addrPairGranuleSIMM; }\n\n# post indexed wback\naddrPairGranuleIndexed: \"[\"^Rn_GPR64xsp^\"]\", \"#\"^addrPairGranuleScale\nis b_2729=0b101 & b_2325=0b001 & Rn_GPR64xsp & addrPairGranuleScale\n{\n\ttmp:8 = Rn_GPR64xsp;\n\tRn_GPR64xsp = Rn_GPR64xsp + addrPairGranuleScale;\n\texport tmp;\n}\n\n# pre indexed wback\naddrPairGranuleIndexed: \"[\"^Rn_GPR64xsp, \"#\"^addrPairGranuleScale^\"]!\"\nis b_2729=0b101 & b_2325=0b011 & Rn_GPR64xsp & addrPairGranuleScale\n{\n\tRn_GPR64xsp = Rn_GPR64xsp + addrPairGranuleScale;\n\texport Rn_GPR64xsp;\n}\n\n# esize=32, len=5, levels=0x1f: 32 bits with b_1014+1 1s; rotate right b_1620; replicate 1 time\nDecodeWMask32: \"#\"^wmask is b_31=0 & b_22=0 & b_15=0 & b_1014 & b_1620\n[ wmask=(((~(-1<<(b_1014+1)))*0x100000001)>>b_1620)&0xffffffff; ]\n{ export * [const]:4 wmask; }\n\n# esize=32, len=5, levels=0x1f: 32 bits with |b_1014-b_1620|+1 1s; replicate 1 time\nDecodeTMask32: \"#\"^tmask is b_31=0 & b_22=0 & b_15=0 & b_1014 & b_1620\n[ tmask=(~(-1<<(((b_1014-b_1620)&0x1f)+1)))&0xffffffff; ]\n{ export * [const]:4 tmask; }\n\n# esize=16, len=4, levels=0xf: 16 bits with b_1013+1 1s; rotate right b_1619; replicate 2 times\nDecodeWMask32: \"#\"^wmask is b_31=0 & b_22=0 & b_1415=0x2 & b_1013 & b_1619\n[ wmask=((((~(-1<<(b_1013+1)))*0x10001)>>b_1619)&0xffff)*0x10001; ]\n{ export * [const]:4 wmask; }\n\n# esize=16, len=4, levels=0xf: 16 bits with |b_1013-b_1619|+1 1s; replicate 2 times\nDecodeTMask32: \"#\"^tmask is b_31=0 & b_22=0 & b_1415=0x2 & b_1013 & b_1619\n[ tmask=((~(-1<<(((b_1013-b_1619)&0xf)+1)))&0xffff)*0x10001; ]\n{ export * [const]:4 tmask; }\n\n# esize=8, len=3, levels=0x7: 8 bits with b_1012+1 1s; rotate right b_1618; replicate 4 times\nDecodeWMask32: \"#\"^wmask is b_31=0 & b_22=0 & b_1315=0x6 & b_1012 & b_1618\n[ wmask=((((~(-1<<(b_1012+1)))*0x101)>>b_1618)&0xff)*0x101*0x10001; ]\n{ export * [const]:4 wmask; }\n\n# esize=8, len=3, levels=0x7: 8 bits with |b_1012-b_1618|+1 1s; replicate 4 times\nDecodeTMask32: \"#\"^tmask is b_31=0 & b_22=0 & b_1315=0x6 & b_1012 & b_1618\n[ tmask=((~(-1<<(((b_1012-b_1618)&0x7)+1)))&0xff)*0x101*0x10001; ]\n{ export * [const]:4 tmask; }\n\n# esize=4, len=2, levels=0x3: 4 bits with b_1011+1 1s; rotate right b_1617; replicate 8 times\nDecodeWMask32: \"#\"^wmask is b_31=0 & b_22=0 & b_1215=0xe & b_1011 & b_1617\n[ wmask=((((~(-1<<(b_1011+1)))*0x11)>>b_1617)&0xf)*0x11*0x101*0x10001; ]\n{ export * [const]:4 wmask; }\n\n# esize=4, len=2, levels=0x3: 4 bits with |b_1011-b_1617|+1 1s; replicate 8 times\nDecodeTMask32: \"#\"^tmask is b_31=0 & b_22=0 & b_1215=0xe & b_1011 & b_1617\n[ tmask=((~(-1<<(((b_1011-b_1617)&0x7)+1)))&0xf)*0x11*0x101*0x10001; ]\n{ export * [const]:4 tmask; }\n\n# esize=2, len=1, levels=0x1: 2 bits with b_1010+1 1s; rotate right b_1616; replicate 16 times\nDecodeWMask32: \"#\"^wmask is b_31=0 & b_22=0 & b_1115=0x1e & b_1010 & b_1616\n[ wmask=((((~(-1<<(b_1010+1)))*0x5)>>b_1616)&0x3)*0x5*0x11*0x101*0x10001; ] \n{ export * [const]:4 wmask; }\n\n# esize=2, len=1, levels=0x1: 2 bits with |b_1010-b_1616|+1 1s; replicate 16 times\nDecodeTMask32: \"#\"^tmask is b_31=0 & b_22=0 & b_1115=0x1e & b_1010 & b_1616\n[ tmask=((~(-1<<(((b_1010-b_1616)&0x1)+1)))&0x3)*0x5*0x11*0x101*0x10001; ] \n{ export * [const]:4 tmask; }\n\n# esize=64, len=6, levels=0x3f: 64 bits with b_1015+1 1s; rotate right b_1621; repeat 1 time\n# can't rotate 64 bits by multiplying, and can't shift by 64 bits all at once\nDecodeWMask64: \"#\"^wmask is b_31=1 & b_22=1 & b_1015 & b_1621\n[ wmask=((~((-1<>b_1621)|((~((-1<>b_1620)&0xffffffff)*0x100000001; ] \n{ export * [const]:8 wmask; }\n\n# esize=32, len=5, levels=0x1f: 32 bits with |b_1014-b_1620|+1 1s; replicate 2 times\nDecodeTMask64: \"#\"^tmask is b_31=1 & b_22=0 & b_15=0 & b_1014 & b_1620\n[ tmask=((~(-1<<(((b_1014-b_1620)&0x1f)+1)))&0xffffffff)*0x100000001; ] \n{ export * [const]:8 tmask; }\n\n# returned 0xffcfffdefcfffcf\n# shouldbe 0xffcfffcfffcfffcf\n# esize=16, len=4, levels=0xf: 16 bits with b_1013+1 1s; rotate right b_1619; replicate 4 times\nDecodeWMask64: \"#\"^wmask is b_31=1 & b_22=0 & b_1415=0x2 & b_1013 & b_1619\n[ wmask=((((~(-1<<(b_1013+1)))*0x10001)>>b_1619)&0xffff)*0x10001*0x100000001; ] \n{ export * [const]:8 wmask; }\n\n# esize=16, len=4, levels=0xf: 16 bits with |b_1013-b_1619|+1 1s; replicate 4 times\nDecodeTMask64: \"#\"^tmask is b_31=1 & b_22=0 & b_1415=0x2 & b_1013 & b_1619\n[ tmask=((~(-1<<(((b_1013-b_1619)&0xf)+1)))&0xffff)*0x10001*0x100000001; ]\n{ export * [const]:8 tmask; }\n\n# esize=8, len=3, levels=0x7: 8 bits with b_1012+1 1s; rotate right b_1618; replicate 8 times\nDecodeWMask64: \"#\"^wmask is b_31=1 & b_22=0 & b_1315=0x6 & b_1012 & b_1618\n[ wmask=((((~(-1<<(b_1012+1)))*0x101)>>b_1618)&0xff)*0x101*0x10001*0x100000001; ]\n{ export * [const]:8 wmask; }\n\n# esize=8, len=3, levels=0x7: 8 bits with |b_1012-b_1618|+1 1s; replicate 8 times\nDecodeTMask64: \"#\"^tmask is b_31=1 & b_22=0 & b_1315=0x6 & b_1012 & b_1618\n[ tmask=((~(-1<<(((b_1012-b_1618)&0x7)+1)))&0xff)*0x101*0x10001*0x100000001; ]\n{ export * [const]:8 tmask; }\n\n# esize=4, len=2, levels=0x3: 4 bits with b_1011+1 1s; rotate right b_1617; replicate 16 times\nDecodeWMask64: \"#\"^wmask is b_31=1 & b_22=0 & b_1215=0xe & b_1011 & b_1617\n[ wmask=((((~(-1<<(b_1011+1)))*0x11)>>b_1617)&0xf)*0x11*0x101*0x10001*0x100000001; ]\n{ export * [const]:8 wmask; }\n\n# esize=4, len=2, levels=0x3: 4 bits with |b_1011-b_1617|+1 1s; replicate 16 times\nDecodeTMask64: \"#\"^tmask is b_31=1 & b_22=0 & b_1215=0xe & b_1011 & b_1617\n[ tmask=((~(-1<<(((b_1011-b_1617)&0x3)+1)))&0xf)*0x11*0x101*0x10001*0x100000001; ]\n{ export * [const]:8 tmask; }\n\n# esize=2, len=1, levels=0x1: 2 bits with b_1010+1 1s; rotate right b_1616; replicate 32 times\nDecodeWMask64: \"#\"^wmask is b_31=1 & b_22=0 & b_1115=0x1e & b_1010 & b_1616\n[ wmask=((((~((-1)<<(b_1010+1)))*0x5)>>b_1616)&0x3)*0x5*0x11*0x101*0x10001*0x100000001; ]\n{ export * [const]:8 wmask; }\n\n# esize=2, len=1, levels=0x1: 2 bits with |b_1010-b_1616|+1 1s; replicate 32 times\nDecodeTMask64: \"#\"^tmask is b_31=1 & b_22=0 & b_1115=0x1e & b_1010 & b_1616\n[ tmask=((~(-1<<(((b_1010-b_1616)&0x1)+1)))&0x3)*0x5*0x11*0x101*0x10001*0x100000001; ]\n{ export * [const]:8 tmask; }\n\nImmRConst32: \"#\"^ImmR is ImmR { export *[const]:4 ImmR; }\nImmRConst64: \"#\"^ImmR is ImmR { export *[const]:8 ImmR; }\n\nImmSConst32: \"#\"^ImmS is ImmS { export *[const]:4 ImmS; }\nImmSConst64: \"#\"^ImmS is ImmS { export *[const]:8 ImmS; }\n\nImmR_bitfield64_imm: \"#\"^ImmR is ImmR & DecodeWMask64 { export DecodeWMask64; }\nImmR_bitfield32_imm: \"#\"^ImmR is ImmR & DecodeWMask32 { export DecodeWMask32; }\n\nImmS_bitfield64_imm: \"#\"^ImmS is ImmS & DecodeTMask64 { export DecodeTMask64; }\nImmS_bitfield32_imm: \"#\"^ImmS is ImmS & DecodeTMask32 { export DecodeTMask32; }\n\nabcdefgh: \"#\"^imm is n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; }\n\nrepl000: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; }\nrepl001: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 8); ] { export *[const]:8 imm; }\nrepl010: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 16); ] { export *[const]:8 imm; }\nrepl011: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 24); ] { export *[const]:8 imm; }\nrepl100: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L) << 16) | ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; }\nrepl101: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 24) | ((n_uimm8H << 5 | n_uimm8L) << 8); ] { export *[const]:8 imm; }\nrepl1100: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((((n_uimm8H << 5 | n_uimm8L) << 8) | 0xff) << 32) | (((n_uimm8H << 5 | n_uimm8L) << 8) | 0xff); ] { export *[const]:8 imm; }\nrepl1101: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((((n_uimm8H << 5 | n_uimm8L) << 16) | 0xffff) << 32) | (((n_uimm8H << 5 | n_uimm8L) << 16) | 0xffff); ] { export *[const]:8 imm; }\nrepl11100: \"#\"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L) << 24) | ((n_uimm8H << 5 | n_uimm8L) << 16) | ((n_uimm8H << 5 | n_uimm8L) << 8) | (n_uimm8H << 5 | n_uimm8L); ] { export *[const]:8 imm; }\nrepl11101: \"#\"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = ((b_18 * 0xff) << 56) | ((b_17 * 0xff) << 48) | ((b_16 * 0xff) << 40) | ((b_09 * 0xff) << 32) | ((b_08 * 0xff) << 24) | ((b_07 * 0xff) << 16) | ((b_06 * 0xff) << 8) | (b_05 * 0xff); ] { export *[const]:8 imm; }\nrepl11110: \"#\"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = (b_18 << 31) | ((b_17 $xor 1) << 30) | ((b_17 * 0x1f) << 25) | (b_16 << 24) | (b_09 << 23) | (b_08 << 22) | (b_07 << 21) | (b_06 << 20) | (b_05 << 19); ] { tmp:8 = imm; tmp = (tmp << 32) | tmp; export tmp; }\nrepl11111: \"#\"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = (b_18 << 63) | ((b_17 $xor 1) << 62) | ((b_17 * 0xff) << 54) | (b_16 << 53) | (b_09 << 52) | (b_08 << 51) | (b_07 << 50) | (b_06 << 49) | (b_05 << 48); ] { tmp:8 = imm; export tmp; }\n\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x0 & b_29=0 & repl000 { export repl000; }\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x1 & b_29=0 & repl000 { export repl000; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #8\" is abcdefgh & cmode=0x2 & b_29=0 & repl001 { export repl001; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #8\" is abcdefgh & cmode=0x3 & b_29=0 & repl001 { export repl001; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #16\" is abcdefgh & cmode=0x4 & b_29=0 & repl010 { export repl010; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #16\" is abcdefgh & cmode=0x5 & b_29=0 & repl010 { export repl010; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #24\" is abcdefgh & cmode=0x6 & b_29=0 & repl011 { export repl011; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #24\" is abcdefgh & cmode=0x7 & b_29=0 & repl011 { export repl011; }\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x8 & b_29=0 & repl100 { export repl100; }\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x9 & b_29=0 & repl100 { export repl100; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #8\" is abcdefgh & cmode=0xa & b_29=0 & repl101 { export repl101; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL #8\" is abcdefgh & cmode=0xb & b_29=0 & repl101 { export repl101; }\nImm_neon_uimm8Shift: abcdefgh^\", MSL #8\" is abcdefgh & cmode=0xc & b_29=0 & repl1100 { export repl1100; }\nImm_neon_uimm8Shift: abcdefgh^\", MSL #16\" is abcdefgh & cmode=0xd & b_29=0 & repl1101 { export repl1101; }\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0xe & b_29=0 & repl11100 { export repl11100; }\nImm_neon_uimm8Shift: repl11101 is abcdefgh & cmode=0xe & b_29=1 & repl11101 { export repl11101; } # MOVI 64\nImm_neon_uimm8Shift: repl11110 is abcdefgh & cmode=0xf & b_29=0 & repl11110 { export repl11110; } # FMOV\nImm_neon_uimm8Shift: repl11111 is abcdefgh & cmode=0xf & b_29=1 & repl11111 { export repl11111; } # FMOV\n\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x1 & b_29=1 & repl000 { export repl000; } # BIC32\nImm_neon_uimm8Shift: abcdefgh^\", LSL 8\" is abcdefgh & cmode=0x3 & b_29=1 & repl001 { export repl001; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL 16\" is abcdefgh & cmode=0x5 & b_29=1 & repl010 { export repl010; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL 24\" is abcdefgh & cmode=0x7 & b_29=1 & repl011 { export repl011; } # BIC16\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x9 & b_29=1 & repl000 { export repl000; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL 8\" is abcdefgh & cmode=0xb & b_29=1 & repl001 { export repl001; }\n\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x0 & b_29=1 & repl000 { export repl000; } # MVNI\nImm_neon_uimm8Shift: abcdefgh^\", LSL 8\" is abcdefgh & cmode=0x2 & b_29=1 & repl001 { export repl001; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL 16\" is abcdefgh & cmode=0x4 & b_29=1 & repl010 { export repl010; }\nImm_neon_uimm8Shift: abcdefgh^\", LSL 24\" is abcdefgh & cmode=0x6 & b_29=1 & repl011 { export repl011; }\nImm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x8 & b_29=1 & repl000 { export repl000; } # MVNI\nImm_neon_uimm8Shift: abcdefgh^\", LSL 8\" is abcdefgh & cmode=0xa & b_29=1 & repl001 { export repl001; }\nImm_neon_uimm8Shift: abcdefgh^\", MSL 8\" is abcdefgh & cmode=0xc & b_29=1 & repl1100 { export repl1100; } # MVNI\nImm_neon_uimm8Shift: abcdefgh^\", MSL 16\" is abcdefgh & cmode=0xd & b_29=1 & repl1101 { export repl1101; }\n\nvIndex: val is b_2222=0 & b_2121 & b_1111 [ val = b_1111 << 1 | b_2121; ] { export *[const]:8 val; }\nvIndex: val is b_2222=1 & b_2121=0 & b_1111 [ val = b_1111 & 0x1; ] { export *[const]:8 val; }\n\nvIndexHLM: val is b_2223=2 & b_2121 & b_1111 [ val = b_1111 << 1 | b_2121; ] { export *[const]:8 val; }\nvIndexHLM: val is b_2223=1 & b_2121 & b_1111 & b_2020 [ val = b_1111 << 2 | b_2121 << 1 | b_2020; ] { export *[const]:8 val; }\nvIndexHLM: val is b_2223=0 & b_2121 & b_1111 & b_2020 [ val = b_1111 << 2 | b_2121 << 1 | b_2020; ] { export *[const]:8 val; }\n\nvIndexHL: val is b_2223=0b01 & b_21 & b_11 [ val = b_11 << 1 | b_21; ] { export *[const]:8 val; }\nvIndexHL: b_11 is b_2223=0b10 & b_11 { export *[const]:8 b_11; }\n\n@if DATA_ENDIAN == \"little\"\nRe_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 2 + b_2121; ] { export *[register]:1 val; }\nRe_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111; ] { export *[register]:1 val; }\nRe_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121) * 4; ] { export *[register]:4 val; }\nRe_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 4; ] { export *[register]:4 val; }\nRe_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121) * 8; ] { export *[register]:8 val; }\nRe_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 8; ] { export *[register]:8 val; }\n@else\nRe_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x501f + 32*Re_VPR128 - b_1111 * 2 - b_2121; ] { export *[register]:1 val; }\nRe_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x501f + 32*Re_VPR128 - b_1111; ] { export *[register]:1 val; }\nRe_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x501c + 32*Re_VPR128 - (b_1111 * 2 + b_2121) * 4; ] { export *[register]:4 val; }\nRe_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x501c + 32*Re_VPR128 - b_1111 * 4; ] { export *[register]:4 val; }\nRe_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5018 + 32*Re_VPR128 - (b_1111 * 2 + b_2121) * 8; ] { export *[register]:8 val; }\nRe_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5018 + 32*Re_VPR128 - b_1111 * 8; ] { export *[register]:8 val; }\n@endif\n\nRe_VPR128.B.vIndex: Re_VPR128.B^\"[\"^vIndex^\"]\" is Re_VPR128.B & vIndex & Re_VPR128.B.sel { export Re_VPR128.B.sel; }\nRe_VPR128.S.vIndex: Re_VPR128.S^\"[\"^vIndex^\"]\" is Re_VPR128.S & vIndex & Re_VPR128.S.sel { export Re_VPR128.S.sel; }\nRe_VPR128.D.vIndex: Re_VPR128.D^\"[\"^vIndex^\"]\" is Re_VPR128.D & vIndex & Re_VPR128.D.sel { export Re_VPR128.D.sel; }\n\n@if DATA_ENDIAN == \"little\"\nRd_VPR128.B.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm4 [ val = 0x5000 + 32*Rd_VPR128 + imm_neon_uimm4; ] { export *[register]:1 val; }\nRd_VPR128.H.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm3 [ val = 0x5000 + 32*Rd_VPR128 + 2*imm_neon_uimm3; ] { export *[register]:2 val; }\nRd_VPR128.S.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm2 [ val = 0x5000 + 32*Rd_VPR128 + 4*imm_neon_uimm2; ] { export *[register]:4 val; }\nRd_VPR128.D.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm1 [ val = 0x5000 + 32*Rd_VPR128 + 8*imm_neon_uimm1; ] { export *[register]:8 val; }\n@else\nRd_VPR128.B.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm4 [ val = 0x501f + 32*Rd_VPR128 - imm_neon_uimm4; ] { export *[register]:1 val; }\nRd_VPR128.H.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm3 [ val = 0x501e + 32*Rd_VPR128 - 2*imm_neon_uimm3; ] { export *[register]:2 val; }\nRd_VPR128.S.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm2 [ val = 0x501c + 32*Rd_VPR128 - 4*imm_neon_uimm2; ] { export *[register]:4 val; }\nRd_VPR128.D.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm1 [ val = 0x5018 + 32*Rd_VPR128 - 8*imm_neon_uimm1; ] { export *[register]:8 val; }\n@endif\nRd_VPR128.B.imm_neon_uimm4: Rd_VPR128.B^\"[\"^imm_neon_uimm4^\"]\" is Rd_VPR128.B & imm_neon_uimm4 & Rd_VPR128.B.sel { export Rd_VPR128.B.sel; }\nRd_VPR128.H.imm_neon_uimm3: Rd_VPR128.H^\"[\"^imm_neon_uimm3^\"]\" is Rd_VPR128.H & imm_neon_uimm3 & Rd_VPR128.H.sel { export Rd_VPR128.H.sel; }\nRd_VPR128.S.imm_neon_uimm2: Rd_VPR128.S^\"[\"^imm_neon_uimm2^\"]\" is Rd_VPR128.S & imm_neon_uimm2 & Rd_VPR128.S.sel { export Rd_VPR128.S.sel; }\nRd_VPR128.D.imm_neon_uimm1: Rd_VPR128.D^\"[\"^imm_neon_uimm1^\"]\" is Rd_VPR128.D & imm_neon_uimm1 & Rd_VPR128.D.sel { export Rd_VPR128.D.sel; }\n\n@if DATA_ENDIAN == \"little\"\nRn_VPR128.B.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm4 [ val = 0x5000 + 32*Rn_VPR128 + immN_neon_uimm4; ] { export *[register]:1 val; }\nRn_VPR128.H.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm3 [ val = 0x5000 + 32*Rn_VPR128 + 2*immN_neon_uimm3; ] { export *[register]:2 val; }\nRn_VPR128.S.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm2 [ val = 0x5000 + 32*Rn_VPR128 + 4*immN_neon_uimm2; ] { export *[register]:4 val; }\nRn_VPR128.D.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm1 [ val = 0x5000 + 32*Rn_VPR128 + 8*immN_neon_uimm1; ] { export *[register]:8 val; }\n@else\nRn_VPR128.B.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm4 [ val = 0x501f + 32*Rn_VPR128 - immN_neon_uimm4; ] { export *[register]:1 val; }\nRn_VPR128.H.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm3 [ val = 0x501e + 32*Rn_VPR128 - 2*immN_neon_uimm3; ] { export *[register]:2 val; }\nRn_VPR128.S.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm2 [ val = 0x501c + 32*Rn_VPR128 - 4*immN_neon_uimm2; ] { export *[register]:4 val; }\nRn_VPR128.D.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm1 [ val = 0x5018 + 32*Rn_VPR128 - 8*immN_neon_uimm1; ] { export *[register]:8 val; }\n@endif\nRn_VPR128.B.immN_neon_uimm4: Rn_VPR128.B^\"[\"^immN_neon_uimm4^\"]\" is Rn_VPR128.B & immN_neon_uimm4 & Rn_VPR128.B.selN { export Rn_VPR128.B.selN; }\nRn_VPR128.H.immN_neon_uimm3: Rn_VPR128.H^\"[\"^immN_neon_uimm3^\"]\" is Rn_VPR128.H & immN_neon_uimm3 & Rn_VPR128.H.selN { export Rn_VPR128.H.selN; }\nRn_VPR128.S.immN_neon_uimm2: Rn_VPR128.S^\"[\"^immN_neon_uimm2^\"]\" is Rn_VPR128.S & immN_neon_uimm2 & Rn_VPR128.S.selN { export Rn_VPR128.S.selN; }\nRn_VPR128.D.immN_neon_uimm1: Rn_VPR128.D^\"[\"^immN_neon_uimm1^\"]\" is Rn_VPR128.D & immN_neon_uimm1 & Rn_VPR128.D.selN { export Rn_VPR128.D.selN; }\n\n@if DATA_ENDIAN == \"little\"\nRn_VPR128.B.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm4 [ val = 0x5000 + 32*Rn_VPR128 + imm_neon_uimm4; ] { export *[register]:1 val; }\nRn_VPR128.H.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm3 [ val = 0x5000 + 32*Rn_VPR128 + 2*imm_neon_uimm3; ] { export *[register]:2 val; }\nRn_VPR128.S.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm2 [ val = 0x5000 + 32*Rn_VPR128 + 4*imm_neon_uimm2; ] { export *[register]:4 val; }\nRn_VPR128.D.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm1 [ val = 0x5000 + 32*Rn_VPR128 + 8*imm_neon_uimm1; ] { export *[register]:8 val; }\n@else\nRn_VPR128.B.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm4 [ val = 0x501f + 32*Rn_VPR128 - imm_neon_uimm4; ] { export *[register]:1 val; }\nRn_VPR128.H.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm3 [ val = 0x501e + 32*Rn_VPR128 - 2*imm_neon_uimm3; ] { export *[register]:2 val; }\nRn_VPR128.S.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm2 [ val = 0x501c + 32*Rn_VPR128 - 4*imm_neon_uimm2; ] { export *[register]:4 val; }\nRn_VPR128.D.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm1 [ val = 0x5018 + 32*Rn_VPR128 - 8*imm_neon_uimm1; ] { export *[register]:8 val; }\n@endif\nRn_VPR128.B.imm_neon_uimm4: Rn_VPR128.B^\"[\"^imm_neon_uimm4^\"]\" is Rn_VPR128.B & imm_neon_uimm4 & Rn_VPR128.B.sel { export Rn_VPR128.B.sel; }\nRn_VPR128.H.imm_neon_uimm3: Rn_VPR128.H^\"[\"^imm_neon_uimm3^\"]\" is Rn_VPR128.H & imm_neon_uimm3 & Rn_VPR128.H.sel { export Rn_VPR128.H.sel; }\nRn_VPR128.S.imm_neon_uimm2: Rn_VPR128.S^\"[\"^imm_neon_uimm2^\"]\" is Rn_VPR128.S & imm_neon_uimm2 & Rn_VPR128.S.sel { export Rn_VPR128.S.sel; }\nRn_VPR128.D.imm_neon_uimm1: Rn_VPR128.D^\"[\"^imm_neon_uimm1^\"]\" is Rn_VPR128.D & imm_neon_uimm1 & Rn_VPR128.D.sel { export Rn_VPR128.D.sel; }\n\nRe_VPR128.H.vIndexHL: Re_VPR128.H^\"[\"^vIndexHL^\"]\" is Re_VPR128.H & vIndexHL { }\n\n@if DATA_ENDIAN == \"little\"\nRe_VPR128Lo.H.sel: Re_VPR128Lo, val is Re_VPR128Lo & b_2223=2 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128Lo + (b_1111 * 2 + b_2121)*2; ] { export *[register]:2 val; }\nRe_VPR128Lo.H.sel: Re_VPR128Lo, val is Re_VPR128Lo & b_2223=1 & b_2121 & b_1111 & b_2020 [ val = 0x5000 + 32*Re_VPR128Lo + (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }\nRe_VPR128Lo.H.sel: Re_VPR128Lo, val is Re_VPR128Lo & b_2223=0 & b_2121 & b_1111 & b_2020 [ val = 0x5000 + 32*Re_VPR128Lo + (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }\n@else\nRe_VPR128Lo.H.sel: Re_VPR128Lo, val is Re_VPR128Lo & b_2223=2 & b_2121 & b_1111 [ val = 0x501e + 32*Re_VPR128Lo - (b_1111 * 2 + b_2121)*2; ] { export *[register]:2 val; }\nRe_VPR128Lo.H.sel: Re_VPR128Lo, val is Re_VPR128Lo & b_2223=1 & b_2121 & b_1111 & b_2020 [ val = 0x501e + 32*Re_VPR128Lo - (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }\nRe_VPR128Lo.H.sel: Re_VPR128Lo, val is Re_VPR128Lo & b_2223=0 & b_2121 & b_1111 & b_2020 [ val = 0x501e + 32*Re_VPR128Lo - (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }\n@endif\nRe_VPR128Lo.H.vIndexHLM: Re_VPR128Lo.H^\"[\"^vIndexHLM^\"]\" is Re_VPR128Lo.H & vIndexHLM & Re_VPR128Lo.H.sel { export Re_VPR128Lo.H.sel; }\n\nFBitsOp: \"#\"^fbits is Scale [ fbits = 64 - Scale; ] { export *[const]:2 fbits; }\n\nFBits64: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:8 = int2float(factor:8); export fval; }\nFBits32: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:4 = int2float(factor:8); export fval; }\nFBits16: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:2 = int2float(factor:8); export fval; }\n\n# float\n\nImm8_fmov16_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=3 [ imm = (Imm8_fmov_sign << 15) | ((Imm8_fmov_exph $xor 1) << 14) | ((Imm8_fmov_exph * 0x3) << 12) | (Imm8_fmov_expl << 10) | (Imm8_fmov_frac << 6); ] { export *[const]:2 imm; }\n\nImm8_fmov32_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=0 [ imm = (Imm8_fmov_sign << 31) | ((Imm8_fmov_exph $xor 1) << 30) | ((Imm8_fmov_exph * 0x1f) << 25) | (Imm8_fmov_expl << 23) | (Imm8_fmov_frac << 19); ] { export *[const]:4 imm; }\n\n# double\nImm8_fmov64_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=1 [ imm = (Imm8_fmov_sign << 63) | ((Imm8_fmov_exph $xor 1) << 62) | ((Imm8_fmov_exph * 0xff) << 54) | (Imm8_fmov_expl << 52) | (Imm8_fmov_frac << 48); ] { export *[const]:8 imm; }\n\n# SVE subtables\n\n# The size qualifer (T) is encoded in several different ways. The\n# majority of encodings are in sve_size_2223\n\n# encoded in \"size\" -- Is the size specifier, size 00 B 01 H 10 S 11 D\n\nT: \"B\" is sve_size_2223=0b00 { export 1:1; }\nT: \"H\" is sve_size_2223=0b01 { export 2:1; }\nT: \"S\" is sve_size_2223=0b10 { export 4:1; }\nT: \"D\" is sve_size_2223=0b11 { export 8:1; }\n\nT_sz: \"S\" is sve_sz_22=0 { export 4:1; }\nT_sz: \"D\" is sve_sz_22=1 { export 8:1; }\n\n# encoded in \"tszh:tszl\" -- Is the size specifier, tszh tszl 00 00 RESERVED 00 01 B 00 1x H 01 xx S 1x xx D \n# Note that tszl is either in b_0809 (if b_21=0) or b_1920 (if b_21=1)\n\nT_tszh: \"B\" is sve_tszh_2223=0b00 & b_21=0 & sve_tszl_0809=0b01 { export 1:1; }\nT_tszh: \"B\" is sve_tszh_2223=0b00 & b_21=1 & sve_tszl_1920=0b01 { export 1:1; }\nT_tszh: \"H\" is sve_tszh_2223=0b00 & b_21=0 & b_09=1 { export 2:1; }\nT_tszh: \"H\" is sve_tszh_2223=0b00 & b_21=1 & b_20=1 { export 2:1; }\nT_tszh: \"S\" is sve_tszh_2223=0b01 { export 4:1; }\nT_tszh: \"D\" is b_23=1 { export 8:1; }\n\n# encoded in \"size\" -- Is the size specifier, size 00 B 01 H 10 S 11 D\n\nT_size_2122: \"B\" is sve_size_2122=0b00 { export 1:1; }\nT_size_2122: \"H\" is sve_size_2122=0b01 { export 2:1; }\nT_size_2122: \"S\" is sve_size_2122=0b10 { export 4:1; }\nT_size_2122: \"D\" is sve_size_2122=0b11 { export 8:1; }\n\n# encoded in \"tsz\" -- Is the size specifier, tsz 00000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D 10000 Q\n\nT_tsz: \"B\" is b_16=1 { export 1:1; }\nT_tsz: \"H\" is b_1617=0b10 { export 2:1; }\nT_tsz: \"S\" is b_1618=0b100 { export 4:1; }\nT_tsz: \"D\" is b_1619=0b1000 { export 8:1; }\nT_tsz: \"Q\" is b_1620=0b10000 { export 16:1; }\nsve_imm2_tsz: tmp is b_16=1 & sve_imm2_2223 & b_1720 [ tmp = sve_imm2_2223 * 16 + b_1720; ] { export *[const]:1 tmp; }\nsve_imm2_tsz: tmp is b_1617=0b10 & sve_imm2_2223 & b_1820 [ tmp = sve_imm2_2223 * 8 + b_1820; ] { export *[const]:1 tmp; }\nsve_imm2_tsz: tmp is b_1618=0b100 & sve_imm2_2223 & b_1920 [ tmp = sve_imm2_2223 * 4 + b_1920; ] { export *[const]:1 tmp; }\nsve_imm2_tsz: tmp is b_1619=0b1000 & sve_imm2_2223 & b_20 [ tmp = sve_imm2_2223 * 2 + b_20; ] { export *[const]:1 tmp; }\nsve_imm2_tsz: tmp is b_1620=0b10000 & sve_imm2_2223 [ tmp = sve_imm2_2223 + 0; ] { export *[const]:1 tmp; }\n\n# encoded in \"imm13<12>:imm13<5:0>\" -- Is the size specifier, imm13<12> imm13<5:0> 0 0xxxxx S 0 10xxxx H 0 110xxx B 0 1110xx B 0 11110x B 0 111110 RESERVED 0 111111 RESERVED 1 xxxxxx D\n\nT_imm13: \"S\" is b_17=0 & b_10=0 { export 4:1; }\nT_imm13: \"H\" is b_17=0 & b_0910=0b10 { export 2:1; }\nT_imm13: \"B\" is b_17=0 & b_0810=0b110 { export 1:1; }\nT_imm13: \"B\" is b_17=0 & b_0710=0b1110 { export 1:1; }\nT_imm13: \"B\" is b_17=0 & b_0610=0b11110 { export 1:1; }\nT_imm13: \"D\" is b_17=1 { export 8:1; }\n\nZd.T: Zd^\".\"^T is Zd & T { export Zd; }\nZd.T_2: Zd^\".\"^T is Zd & T { export Zd; }\nZd.T_tszh: Zd^\".\"^T_tszh is Zd & T_tszh { export Zd; }\nZd.T_tszh_2: Zd^\".\"^T_tszh is Zd & T_tszh { export Zd; }\nZd.T_tsz: Zd^\".\"^T_tsz is Zd & T_tsz { export Zd; }\nZd.T_imm13: Zd^\".\"^T_imm13 is Zd & T_imm13 { export Zd; }\nZd.T_imm13_2: Zd^\".\"^T_imm13 is Zd & T_imm13 { export Zd; }\nZd.T_sz: Zd^\".\"^T_sz is Zd & T_sz { export Zd; }\nZd.T_sz_2: Zd^\".\"^T_sz is Zd & T_sz { export Zd; }\nZd.T_size_2122: Zd^\".\"^T_size_2122 is Zd & T_size_2122 { export Zd; }\n\nZd.B: Zd^\".B\" is Zd { export Zd; }\nZd.B_2: Zd^\".B\" is Zd { export Zd; }\nZd.H: Zd^\".H\" is Zd { export Zd; }\nZd.S: Zd^\".S\" is Zd { export Zd; }\nZd.D: Zd^\".D\" is Zd { export Zd; }\n\nZt.B: sve_zt_0004^\".B\" is sve_zt_0004 { export sve_zt_0004; }\nZtt.B: sve_ztt_0004^\".B\" is sve_ztt_0004 { export sve_ztt_0004; }\nZttt.B: sve_zttt_0004^\".B\" is sve_zttt_0004 { export sve_zttt_0004; }\nZtttt.B: sve_ztttt_0004^\".B\" is sve_ztttt_0004 { export sve_ztttt_0004; }\nZt.H: sve_zt_0004^\".H\" is sve_zt_0004 { export sve_zt_0004; }\nZtt.H: sve_ztt_0004^\".H\" is sve_ztt_0004 { export sve_ztt_0004; }\nZttt.H: sve_zttt_0004^\".H\" is sve_zttt_0004 { export sve_zttt_0004; }\nZtttt.H: sve_ztttt_0004^\".H\" is sve_ztttt_0004 { export sve_ztttt_0004; }\nZt.S: sve_zt_0004^\".S\" is sve_zt_0004 { export sve_zt_0004; }\nZtt.S: sve_ztt_0004^\".S\" is sve_ztt_0004 { export sve_ztt_0004; }\nZttt.S: sve_zttt_0004^\".S\" is sve_zttt_0004 { export sve_zttt_0004; }\nZtttt.S: sve_ztttt_0004^\".S\" is sve_ztttt_0004 { export sve_ztttt_0004; }\nZt.D: sve_zt_0004^\".D\" is sve_zt_0004 { export sve_zt_0004; }\nZtt.D: sve_ztt_0004^\".D\" is sve_ztt_0004 { export sve_ztt_0004; }\nZttt.D: sve_zttt_0004^\".D\" is sve_zttt_0004 { export sve_zttt_0004; }\nZtttt.D: sve_ztttt_0004^\".D\" is sve_ztttt_0004 { export sve_ztttt_0004; }\n\nZn.T: sve_zn_0509^\".\"^T is sve_zn_0509 & T { export sve_zn_0509; }\nZn.T_sz: sve_zn_0509^\".\"^T_sz is sve_zn_0509 & T_sz { export sve_zn_0509; }\nZn.T_tszh: sve_zn_0509^\".\"^T_tszh is sve_zn_0509 & T_tszh { export sve_zn_0509; }\nZn.T_tsz: sve_zn_0509^\".\"^T_tsz is sve_zn_0509 & T_tsz { export sve_zn_0509; }\nZn.Tb_sz: sve_zn_0509^\".B\" is sve_zn_0509 & sve_sz_22=0 { export sve_zn_0509; }\nZn.Tb_sz: sve_zn_0509^\".H\" is sve_zn_0509 & sve_sz_22=1 { export sve_zn_0509; }\nZn.Tb: sve_zn_0509^\".B\" is sve_zn_0509 & sve_size_2223=0b01 { export sve_zn_0509; }\nZn.Tb: sve_zn_0509^\".H\" is sve_zn_0509 & sve_size_2223=0b10 { export sve_zn_0509; }\nZn.Tb: sve_zn_0509^\".S\" is sve_zn_0509 & sve_size_2223=0b11 { export sve_zn_0509; }\n\nZn.B: sve_zn_0509^\".B\" is sve_zn_0509 { export sve_zn_0509; }\nZn.H: sve_zn_0509^\".H\" is sve_zn_0509 { export sve_zn_0509; }\nZn.S: sve_zn_0509^\".S\" is sve_zn_0509 { export sve_zn_0509; }\nZn.D: sve_zn_0509^\".D\" is sve_zn_0509 { export sve_zn_0509; }\n\nZm.T: sve_zm_1620^\".\"^T is sve_zm_1620 & T { export sve_zm_1620; }\nZm.T_sz: sve_zm_1620^\".\"^T_sz is sve_zm_1620 & T_sz { export sve_zm_1620; }\nZm.Tb_sz: sve_zm_1620^\".B\" is sve_zm_1620 & sve_sz_22=0 { export sve_zm_1620; }\nZm.Tb_sz: sve_zm_1620^\".H\" is sve_zm_1620 & sve_sz_22=1 { export sve_zm_1620; }\n# Zm.Tb: sve_zm_1620^\".B\" is sve_zm_1620 & sve_size_2223=0b01 { export sve_zm_1620; }\n# Zm.Tb: sve_zm_1620^\".H\" is sve_zm_1620 & sve_size_2223=0b10 { export sve_zm_1620; }\n# Zm.Tb: sve_zm_1620^\".S\" is sve_zm_1620 & sve_size_2223=0b11 { export sve_zm_1620; }\n\n# Zm.B: sve_zm_1620^\".B\" is sve_zm_1620 { export sve_zm_1620; }\n# Zm.H: sve_zm_1620^\".H\" is sve_zm_1620 { export sve_zm_1620; }\nZm.S: sve_zm_1620^\".S\" is sve_zm_1620 { export sve_zm_1620; }\nZm.D: sve_zm_1620^\".D\" is sve_zm_1620 { export sve_zm_1620; }\n\nZm3.B: sve_zm_1618^\".B\" is sve_zm_1618 { export sve_zm_1618; }\nZm3.H: sve_zm_1618^\".H\" is sve_zm_1618 { export sve_zm_1618; }\nZm3.S: sve_zm_1618^\".S\" is sve_zm_1618 { export sve_zm_1618; }\n# Zm3.D: sve_zm_1618^\".D\" is sve_zm_1618 { export sve_zm_1618; }\n\n# Zm4.B: sve_zm_1619^\".B\" is sve_zm_1619 { export sve_zm_1619; }\nZm4.H: sve_zm_1619^\".H\" is sve_zm_1619 { export sve_zm_1619; }\nZm4.S: sve_zm_1619^\".S\" is sve_zm_1619 { export sve_zm_1619; }\nZm4.D: sve_zm_1619^\".D\" is sve_zm_1619 { export sve_zm_1619; }\n\nPg: sve_pg_1013 is sve_pg_1013 { export sve_pg_1013; }\nPg_z: sve_pg_1013^\"/z\" is sve_pg_1013 { export sve_pg_1013; }\nPg_zm: sve_pg_1013^\"/z\" is sve_pg_1013 & sve_m_04=0 { export sve_pg_1013; }\nPg_zm: sve_pg_1013^\"/m\" is sve_pg_1013 & sve_m_04=1 { export sve_pg_1013; }\nPg3: sve_pg_1012 is sve_pg_1012 { export sve_pg_1012; }\nPg3_m: sve_pg_1012^\"/m\" is sve_pg_1012 { export sve_pg_1012; }\nPg3_z: sve_pg_1012^\"/z\" is sve_pg_1012 { export sve_pg_1012; }\nPg3_zm: sve_pg_1012^\"/z\" is sve_pg_1012 & sve_m_16=0 { export sve_pg_1012; }\nPg3_zm: sve_pg_1012^\"/m\" is sve_pg_1012 & sve_m_16=1 { export sve_pg_1012; }\n\nPd.T: sve_pd_0003^\".\"^T is sve_pd_0003 & T { export sve_pd_0003; }\nPd.T_2: sve_pd_0003^\".\"^T is sve_pd_0003 & T { export sve_pd_0003; }\nPd: sve_pd_0003 is sve_pd_0003 { export sve_pd_0003; }\nPd.B: sve_pd_0003^\".B\" is sve_pd_0003 { export sve_pd_0003; }\nPd.B_2: sve_pd_0003^\".B\" is sve_pd_0003 { export sve_pd_0003; }\nPd.H: sve_pd_0003^\".H\" is sve_pd_0003 { export sve_pd_0003; }\n# Pd.S: sve_pd_0003^\".S\" is sve_pd_0003 { export sve_pd_0003; }\n# Pd.D: sve_pd_0003^\".D\" is sve_pd_0003 { export sve_pd_0003; }\n\nPn: sve_pn_0508 is sve_pn_0508 { export sve_pn_0508; }\nPn_z: sve_pn_0508^\"/z\" is sve_pn_0508 { export sve_pn_0508; }\nPn.T: sve_pn_0508^\".\"^T is sve_pn_0508 & T { export sve_pn_0508; }\nPn.B: sve_pn_0508^\".B\" is sve_pn_0508 { export sve_pn_0508; }\n# Pn.H: sve_pn_0508^\".H\" is sve_pn_0508 { export sve_pn_0508; }\n# Pn.S: sve_pn_0508^\".S\" is sve_pn_0508 { export sve_pn_0508; }\n# Pn.D: sve_pn_0508^\".D\" is sve_pn_0508 { export sve_pn_0508; }\n\nPm_m: sve_pm_1619^\"/m\" is sve_pm_1619 { export sve_pm_1619; }\nPm_zm: sve_pm_1619^\"/z\" is sve_pm_1619 & sve_m_14=0 { export sve_pm_1619; }\nPm_zm: sve_pm_1619^\"/m\" is sve_pm_1619 & sve_m_14=1 { export sve_pm_1619; }\nPm.T: sve_pm_1619^\".\"^T is sve_pm_1619 & T { export sve_pm_1619; }\nPm.B: sve_pm_1619^\".B\" is sve_pm_1619 { export sve_pm_1619; }\n# Pm.H: sve_pm_1619^\".H\" is sve_pm_1619 { export sve_pm_1619; }\n# Pm.S: sve_pm_1619^\".S\" is sve_pm_1619 { export sve_pm_1619; }\n# Pm.D: sve_pm_1619^\".D\" is sve_pm_1619 { export sve_pm_1619; }\n\nsve_i3h_i3l: tmp is sve_i3h_22 & sve_i3l_1920 [ tmp = sve_i3h_22 * 4 + sve_i3l_1920; ] { export *[const]:1 tmp; }\nsve_imm3_1_0to7: sve_imm3_1618 is sve_imm3_1618 { export *[const]:1 sve_imm3_1618; }\nsve_imm4_1_1to16: tmp is sve_imm4_1619 [ tmp = sve_imm4_1619 + 1; ] { export *[const]:1 tmp; }\nsve_imm4_1_m128to112: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 16; ] { export *[const]:1 tmp; }\nsve_opt4_1_m128to112: \"\" is sve_imm4s_1619=0 { export 0:1; }\nsve_opt4_1_m128to112: \", #\"^sve_imm4_1_m128to112 is sve_imm4_1_m128to112 { export sve_imm4_1_m128to112; }\nsve_imm4_1_m16to14: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 2; ] { export *[const]:1 tmp; }\nsve_mul4_1_m16to14: \"\" is sve_imm4s_1619=0 { export 0:1; }\nsve_mul4_1_m16to14: \", #\"^sve_imm4_1_m16to14^\", mul vl\" is sve_imm4_1_m16to14 { export *[const]:1 sve_imm4_1_m16to14; }\nsve_imm4_1_m24to21: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 3; ] { export *[const]:1 tmp; }\nsve_mul4_1_m24to21: \"\" is sve_imm4s_1619=0 { export 0:1; }\nsve_mul4_1_m24to21: \", #\"^sve_imm4_1_m24to21^\", mul vl\" is sve_imm4_1_m24to21 { export *[const]:1 sve_imm4_1_m24to21; }\nsve_imm4_1_m32to28: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 4; ] { export *[const]:1 tmp; }\nsve_mul4_1_m32to28: \"\" is sve_imm4s_1619=0 { export 0:1; }\nsve_mul4_1_m32to28: \", #\"^sve_imm4_1_m32to28^\", mul vl\" is sve_imm4_1_m32to28 { export *[const]:1 sve_imm4_1_m32to28; }\nsve_imm4_1_m8to7: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 1; ] { export *[const]:1 tmp; }\nsve_mul4_1_m8to7: \"\" is sve_imm4s_1619=0 { export 0:1; }\nsve_mul4_1_m8to7: \", #\"^sve_imm4_1_m8to7^\", mul vl\" is sve_imm4_1_m8to7 { export *[const]:1 sve_imm4_1_m8to7; }\nsve_imm5_1_0to124: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 4; ] { export *[const]:1 tmp; }\nsve_opt5_1_0to124: \"\" is sve_imm5_1620=0 { export 0:1; }\nsve_opt5_1_0to124: \", #\"^sve_imm5_1_0to124 is sve_imm5_1_0to124 { export sve_imm5_1_0to124; }\nsve_imm5_1_0to248: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 8; ] { export *[const]:1 tmp; }\nsve_opt5_1_0to248: \"\" is sve_imm5_1620=0 { export 0:1; }\nsve_opt5_1_0to248: \", #\"^sve_imm5_1_0to248 is sve_imm5_1_0to248 { export sve_imm5_1_0to248; }\nsve_imm5_1_0to31: sve_imm5_1620 is sve_imm5_1620 { export *[const]:1 sve_imm5_1620; }\nsve_opt5_1_0to31: \"\" is sve_imm5_1620=0 { export 0:1; }\nsve_opt5_1_0to31: \", #\"^sve_imm5_1_0to31 is sve_imm5_1_0to31 { export sve_imm5_1_0to31; }\nsve_imm5_1_0to62: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 2; ] { export *[const]:1 tmp; }\nsve_opt5_1_0to62: \"\" is sve_imm5_1620=0 { export 0:1; }\nsve_opt5_1_0to62: \", #\"^sve_imm5_1_0to62 is sve_imm5_1_0to62 { export sve_imm5_1_0to62; }\nsve_imm5_1_m16to15: sve_imm5s_1620 is sve_b_1015=0b010001 & sve_imm5s_1620 { export *[const]:1 sve_imm5s_1620; }\nsve_imm5_1_m16to15: sve_imm5s_0509 is sve_b_1015=0b010010 & sve_imm5s_0509 { export *[const]:1 sve_imm5s_0509; }\nsve_imm6_1_0to126: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 2; ] { export *[const]:1 tmp; }\nsve_opt6_1_0to126: \"\" is sve_imm6_1621=0 { export 0:1; }\nsve_opt6_1_0to126: \", #\"^sve_imm6_1_0to126 is sve_imm6_1_0to126 { export sve_imm6_1_0to126; }\nsve_imm6_1_0to252: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 4; ] { export *[const]:1 tmp; }\nsve_opt6_1_0to252: \"\" is sve_imm6_1621=0 { export 0:1; }\nsve_opt6_1_0to252: \", #\"^sve_imm6_1_0to252 is sve_imm6_1_0to252 { export sve_imm6_1_0to252; }\nsve_imm6_1_0to504: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 8; ] { export *[const]:2 tmp; }\nsve_opt6_1_0to504: \"\" is sve_imm6_1621=0 { export 0:2; }\nsve_opt6_1_0to504: \", #\"^sve_imm6_1_0to504 is sve_imm6_1_0to504 { export sve_imm6_1_0to504; }\nsve_imm6_1_0to63: sve_imm6_1621 is sve_imm6_1621 { export *[const]:1 sve_imm6_1621; }\nsve_opt6_1_0to63: \"\" is sve_imm6_1621=0 { export 0:1; }\nsve_opt6_1_0to63: \", #\"^sve_imm6_1_0to63 is sve_imm6_1_0to63 { export sve_imm6_1_0to63; }\nsve_imm6_1_m32to31: sve_imm6s_0510 is sve_imm6s_0510 { export *[const]:1 sve_imm6s_0510; }\nsve_mul6_1_m32to31: \"\" is sve_imm6_1621=0 { export 0:1; }\nsve_mul6_1_m32to31: \", #\"^sve_imm6s_1621^\", mul vl\" is sve_imm6s_1621 { export *[const]:1 sve_imm6s_1621; }\nsve_imm8_1_0to255: sve_imm8_0512 is sve_imm8_0512 { export *[const]:1 sve_imm8_0512; }\nsve_shf8_1_0to255: \"#0, LSL #8\" is sve_imm8_0512=0 & sve_sh_13=1 { export 0:2; }\nsve_shf8_1_0to255: \"#\"^tmp is sve_imm8_0512 & sve_sh_13 [ tmp = sve_imm8_0512 << (8 * sve_sh_13); ] { export *[const]:2 tmp; }\nsve_imm8_1_m128to127: sve_imm8s_0512 is sve_imm8s_0512 { export *[const]:1 sve_imm8s_0512; }\nsve_shf8_1_m128to127: \"#0, LSL #8\" is sve_imm8s_0512=0 & sve_sh_13=1 { export 0:2; }\nsve_shf8_1_m128to127: \"#\"^tmp is sve_imm8s_0512 & sve_sh_13 [ tmp = sve_imm8s_0512 << (8 * sve_sh_13); ] { export *[const]:2 tmp; }\nsve_imm8_2_0to255: tmp is sve_imm8h_1620 & sve_imm8l_1012 [ tmp = sve_imm8h_1620 * 8 + sve_imm8l_1012; ] { export *[const]:1 tmp; }\nsve_imm9_2_m256to255: tmp is sve_imm9hs_1621 & sve_imm9l_1012 [ tmp = sve_imm9hs_1621 * 8 + sve_imm9l_1012; ] { export *[const]:2 tmp; }\nsve_mul9_2_m256to255: \"\" is sve_imm6_1621=0 & sve_imm9l_1012=0 { export 0:2; }\nsve_mul9_2_m256to255: \", #\"^sve_imm9_2_m256to255^\", mul vl\" is sve_imm9_2_m256to255 { export sve_imm9_2_m256to255; }\n\nsve_pattern: \"POW2\" is sve_pattern_0509=0b00000 { export 0b00000:1; }\nsve_pattern: \"VL1\" is sve_pattern_0509=0b00001 { export 0b00001:1; }\nsve_pattern: \"VL2\" is sve_pattern_0509=0b00010 { export 0b00010:1; }\nsve_pattern: \"VL3\" is sve_pattern_0509=0b00011 { export 0b00011:1; }\nsve_pattern: \"VL4\" is sve_pattern_0509=0b00100 { export 0b00100:1; }\nsve_pattern: \"VL5\" is sve_pattern_0509=0b00101 { export 0b00101:1; }\nsve_pattern: \"VL6\" is sve_pattern_0509=0b00110 { export 0b00110:1; }\nsve_pattern: \"VL7\" is sve_pattern_0509=0b00111 { export 0b00111:1; }\nsve_pattern: \"VL8\" is sve_pattern_0509=0b01000 { export 0b01000:1; }\nsve_pattern: \"VL16\" is sve_pattern_0509=0b01001 { export 0b01001:1; }\nsve_pattern: \"VL32\" is sve_pattern_0509=0b01010 { export 0b01010:1; }\nsve_pattern: \"VL64\" is sve_pattern_0509=0b01011 { export 0b01011:1; }\nsve_pattern: \"VL128\" is sve_pattern_0509=0b01100 { export 0b01100:1; }\nsve_pattern: \"VL256\" is sve_pattern_0509=0b01101 { export 0b01101:1; }\nsve_pattern: \"#\"^sve_pattern_0509 is b_0609=0b0111 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }\nsve_pattern: \"#\"^sve_pattern_0509 is b_0709=0b101 & b_05=1 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }\nsve_pattern: \"#\"^sve_pattern_0509 is b_0509=0b10110 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }\nsve_pattern: \"#\"^sve_pattern_0509 is b_09=1 & b_07=0 & b_05=1 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }\nsve_pattern: \"#\"^sve_pattern_0509 is b_09=1 & b_0507=0b010 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }\nsve_pattern: \"#\"^sve_pattern_0509 is b_09=1 & b_0506=0b00 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }\nsve_pattern: \"MUL4\" is sve_pattern_0509=0b11101 { export 0b11101:1; }\nsve_pattern: \"MUL3\" is sve_pattern_0509=0b11110 { export 0b11110:1; }\nsve_pattern: \"ALL\" is sve_pattern_0509=0b11111 { export 0b11111:1; }\n\nsve_opt_pattern: \"\" is sve_pattern_0509=0b11111 { export 0b11111:1; }\nsve_opt_pattern: \", \"^sve_pattern is sve_pattern { export sve_pattern; }\n\nsve_mul_pattern: \"\" is sve_pattern_0509=0b11111 & sve_imm4_1619=0b0000 { export 0b11111:1; }\nsve_mul_pattern: \", \"^sve_pattern is sve_pattern & sve_imm4_1619=0b0000 { export sve_pattern; }\nsve_mul_pattern: \", \"^sve_pattern^\", mul #\"^sve_imm4_1_1to16 is sve_pattern & sve_imm4_1_1to16 { export sve_pattern; }\n\nsve_mod_amount: \"\" is sve_msz_1011=0b00 { export 0:1; }\nsve_mod_amount: \", LSL #1\" is sve_msz_1011=0b01 { export 1:1; }\nsve_mod_amount: \", LSL #2\" is sve_msz_1011=0b10 { export 2:1; }\nsve_mod_amount: \", LSL #3\" is sve_msz_1011=0b11 { export 3:1; }\n\nsve_mod: \"UXTW\" is b_15=1 & b_14=0 { export 2:1; }\nsve_mod: \"SXTW\" is b_15=1 & b_14=1 { export 3:1; }\nsve_mod: \"UXTW\" is b_15=0 & b_22=0 { export 0:1; }\nsve_mod: \"SXTW\" is b_15=0 & b_22=1 { export 1:1; }\n\nsve_prfop: \"PLDL1KEEP\" is sve_prfop_0003=0b0000 { export 0b0000:1; }\nsve_prfop: \"PLDL1STRM\" is sve_prfop_0003=0b0001 { export 0b0001:1; }\nsve_prfop: \"PLDL2KEEP\" is sve_prfop_0003=0b0010 { export 0b0010:1; }\nsve_prfop: \"PLDL2STRM\" is sve_prfop_0003=0b0011 { export 0b0011:1; }\nsve_prfop: \"PLDL3KEEP\" is sve_prfop_0003=0b0100 { export 0b0100:1; }\nsve_prfop: \"PLDL3STRM\" is sve_prfop_0003=0b0101 { export 0b0101:1; }\nsve_prfop: \"#\"^sve_prfop_0003 is b_02 & b_01=1 & sve_prfop_0003 { export *[const]:1 sve_prfop_0003; }\nsve_prfop: \"PSTL1KEEP\" is sve_prfop_0003=0b1000 { export 0b1000:1; }\nsve_prfop: \"PSTL1STRM\" is sve_prfop_0003=0b1001 { export 0b1001:1; }\nsve_prfop: \"PSTL2KEEP\" is sve_prfop_0003=0b1010 { export 0b1010:1; }\nsve_prfop: \"PSTL2STRM\" is sve_prfop_0003=0b1011 { export 0b1011:1; }\nsve_prfop: \"PSTL3KEEP\" is sve_prfop_0003=0b1100 { export 0b1100:1; }\nsve_prfop: \"PSTL3STRM\" is sve_prfop_0003=0b1101 { export 0b1101:1; }\n\nsve_decode_bit_mask: wmask is b_17=0 & b_0510=0b111100 & b_11 [ wmask = (0x5555 >> b_11) & 0xff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b00 & b_1112 [ wmask = (0x1111 >> b_1112) & 0xff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b01 & b_1112 [ wmask = (0x3333 >> b_1112) & 0xff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b10 & b_1112 [ wmask = (0x7777 >> b_1112) & 0xff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=0 & b_0810=0b110 & b_0507 & b_1113 [ wmask = (((~(-1<<(b_0507+1))) | (~(-1<<(b_0507+9)) & 0xff00)) >> b_1113) & 0xff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=0 & b_0910=0b10 & b_0508 & b_1114 [ wmask = (((~(-1<<(b_0508+1))) | (~(-1<<(b_0508+17)) & 0xffff0000)) >> b_1114) & 0xffff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=0 & b_10=0 & b_0509 & b_1115 [ wmask = (((~(-1<<(b_0509+1))) | (~(-1<<(b_0509+33)) & 0xffffffff00000000)) >> b_1115) & 0xffffffff; ] { export *[const]:8 wmask; }\nsve_decode_bit_mask: wmask is b_17=1 & b_0510 & b_1116 [ wmask = ( (((~(-1<<(b_0510+1)))) >> b_1116) | (((~(-1<<(b_0510+1)))) << (64-b_1116))) & 0xffffffffffffffff; ] { export *[const]:8 wmask; }\n\nsve_shift_13: \"\" is sve_sh_13=0 { export 0:1; }\nsve_shift_13: \", LSL #8\" is sve_sh_13=1 { export 8:1; }\n\n# The immediate shift is computed from tszh, tszl, imm8. The formula\n# depends on the instruction, as does the location of tszl and imm8.\n# The conditions b_21=0/1 and b_17/b_11=0/1 were found by inspecting\n# the differences between the instructions.\n\n# Instructions where the immediate shift is 2 * esize - UInt(tsz:imm3)\nsve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b00 & sve_tszl_0809=0b01 & sve_imm3_0507 [ tmp = 16 - ( 8 + sve_imm3_0507); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b00 & b_09=1 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 32 - ( 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b01 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 64 - (32 + 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=0 & b_17=0 & b_23=1 & sve_tszh_2223 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 128 - (32 * sve_tszh_2223 + 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b00 & sve_tszl_1920=0b01 & sve_imm3_1618 [ tmp = 16 - ( 8 + sve_imm3_1618); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b00 & b_20=1 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 32 - ( 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b01 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 64 - (32 + 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=0 & b_23=1 & sve_tszh_2223 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 128 - (32 * sve_tszh_2223 + 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; }\n\n# Instructions where the immediate shift is UInt(tsz:imm3) - esize\nsve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b00 & sve_tszl_0809=0b01 & sve_imm3_0507 [ tmp = ( 8 + sve_imm3_0507) - 8; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b00 & b_09=1 & sve_tszl_0809 & sve_imm3_0507 [ tmp = ( 8 * sve_tszl_0809 + sve_imm3_0507) - 16; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b01 & sve_tszl_0809 & sve_imm3_0507 [ tmp = (32 + 8 * sve_tszl_0809 + sve_imm3_0507) - 32; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=0 & b_17=1 & b_23=1 & sve_tszh_2223 & sve_tszl_0809 & sve_imm3_0507 [ tmp = (32 * sve_tszh_2223 + 8 * sve_tszl_0809 + sve_imm3_0507) - 64; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b00 & sve_tszl_1920=0b01 & sve_imm3_1618 [ tmp = ( 8 + sve_imm3_1618) - 8; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b00 & b_20=1 & sve_tszl_1920 & sve_imm3_1618 [ tmp = ( 8 * sve_tszl_1920 + sve_imm3_1618) - 16; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b01 & sve_tszl_1920 & sve_imm3_1618 [ tmp = (32 + 8 * sve_tszl_1920 + sve_imm3_1618) - 32; ] { export *[const]:1 tmp; }\nsve_imm_shift: tmp is b_21=1 & b_11=1 & b_23=1 & sve_tszh_2223 & sve_tszl_1920 & sve_imm3_1618 [ tmp = (32 * sve_tszh_2223 + 8 * sve_tszl_1920 + sve_imm3_1618) - 64; ] { export *[const]:1 tmp; }\n\nsve_float_0510: \"#0.5\" is sve_i1_05=0 { export 0:1; }\nsve_float_0510: \"#1.0\" is sve_i1_05=1 { export 1:1; }\nsve_float_0520: \"#0.5\" is sve_i1_05=0 { export 0:1; }\nsve_float_0520: \"#2.0\" is sve_i1_05=1 { export 1:1; }\nsve_float_0010: \"#0.0\" is sve_i1_05=0 { export 0:1; }\nsve_float_0010: \"#1.0\" is sve_i1_05=1 { export 1:1; }\n\n# there are no floating point constants in SLEIGH\n# generate equivalent hex floating point constant\n\nattach names [ sve_float_dec ] [ \"0\" \"1\" \"2\" \"3\" \"4\" \"5\" \"6\" \"7\" \"8\" \"9\" \"a\" \"b\" \"c\" \"d\" \"e\" \"f\" ];\nattach names [ sve_float_exp ] [ \"+1\" \"+2\" \"+3\" \"+4\" \"-3\" \"-2\" \"-1\" \"+0\" ];\n\nsve_float_imm8: s^\".\"^sve_float_dec^\"p\"^sve_float_exp is sve_imm8_0512 & sve_float_dec & sve_float_exp & b_12 [ s = (1 - 2 * b_12); ] { export *[const]:1 sve_imm8_0512; }\n\n# SECTION pcodeops\n\n# The following SIMD and MP versions of SLEIGH primitives are\n# implemented in java for AARCH64\n\ndefine pcodeop MP_INT_ABS;\ndefine pcodeop MP_INT_RIGHT;\ndefine pcodeop MP_INT_MULT;\ndefine pcodeop MP_INT_UMULT;\n\n# The following AARCH64 instructions are implemented in java as a\n# pcodeop\n\ndefine pcodeop a64_TBL;\n\n# The following pcode ops are not implemented\n\ndefine pcodeop AT_S12E0R;\ndefine pcodeop AT_S12E0W;\ndefine pcodeop AT_S12E1R;\ndefine pcodeop AT_S12E1W;\ndefine pcodeop AT_S1E0R;\ndefine pcodeop AT_S1E0W;\ndefine pcodeop AT_S1E1R;\ndefine pcodeop AT_S1E1RP;\ndefine pcodeop AT_S1E1W;\ndefine pcodeop AT_S1E1WP;\ndefine pcodeop AT_S1E2R;\ndefine pcodeop AT_S1E2W;\ndefine pcodeop AT_S1E3R;\ndefine pcodeop AT_S1E3W;\ndefine pcodeop AuthIA;\ndefine pcodeop AuthIB;\ndefine pcodeop AuthDA;\ndefine pcodeop AuthDB;\ndefine pcodeop CallHyperVisor;\ndefine pcodeop CallSecureMonitor;\ndefine pcodeop CallSupervisor;\ndefine pcodeop ClearExclusiveLocal;\ndefine pcodeop crc32b; define pcodeop crc32h;\ndefine pcodeop crc32w;\ndefine pcodeop crc32x;\ndefine pcodeop DataMemoryBarrier;\ndefine pcodeop DataSynchronizationBarrier;\ndefine pcodeop DC_CISW;\ndefine pcodeop DC_CIVAC;\ndefine pcodeop DC_CSW;\ndefine pcodeop DC_CVAC;\ndefine pcodeop DC_CVAP;\ndefine pcodeop DC_CVAU;\ndefine pcodeop DC_ISW;\ndefine pcodeop DC_IVAC;\ndefine pcodeop DC_IGVAC;\ndefine pcodeop DC_IGSW;\ndefine pcodeop DC_IGDVAC;\ndefine pcodeop DC_IGDSW;\ndefine pcodeop DC_CGSW;\ndefine pcodeop DC_CGDSW;\ndefine pcodeop DC_CIGSW;\ndefine pcodeop DC_CIGDSW;\ndefine pcodeop DC_GVA;\ndefine pcodeop DC_GZVA;\ndefine pcodeop DC_CGVAC;\ndefine pcodeop DC_CGDVAC;\ndefine pcodeop DC_CGVAP;\ndefine pcodeop DC_CGDVAP;\ndefine pcodeop DC_CGVADP;\ndefine pcodeop DC_CGDVADP;\ndefine pcodeop DC_CIGVAC;\ndefine pcodeop DC_CIGDVAC;\ndefine pcodeop DCPSInstruction;\ndefine pcodeop DC_ZVA;\ndefine pcodeop DRPSInstruction;\ndefine pcodeop ExceptionReturn;\ndefine pcodeop ExclusiveMonitorPass;\ndefine pcodeop ExclusiveMonitorsStatus;\ndefine pcodeop HaltBreakPoint;\ndefine pcodeop Hint_Prefetch;\ndefine pcodeop IC_IALLU;\ndefine pcodeop IC_IALLUIS;\ndefine pcodeop IC_IVAU;\ndefine pcodeop InstructionSynchronizationBarrier;\ndefine pcodeop LOAcquire;\ndefine pcodeop LORelease;\ndefine pcodeop pacda;\ndefine pcodeop pacdb;\ndefine pcodeop pacdza;\ndefine pcodeop pacdzb;\ndefine pcodeop pacga;\ndefine pcodeop pacia;\ndefine pcodeop paciza;\ndefine pcodeop pacib;\ndefine pcodeop pacizb;\ndefine pcodeop SendEvent;\ndefine pcodeop SendEventLocally;\ndefine pcodeop SoftwareBreakpoint;\ndefine pcodeop SpeculationBarrier;\ndefine pcodeop SysOp_R;\ndefine pcodeop SysOp_W;\ndefine pcodeop TLBI_ALLE1;\ndefine pcodeop TLBI_ALLE1IS;\ndefine pcodeop TLBI_ALLE2;\ndefine pcodeop TLBI_ALLE2IS;\ndefine pcodeop TLBI_ALLE3;\ndefine pcodeop TLBI_ALLE3IS;\ndefine pcodeop TLBI_ASIDE1;\ndefine pcodeop TLBI_ASIDE1IS;\ndefine pcodeop TLBI_IPAS2E1;\ndefine pcodeop TLBI_IPAS2E1IS;\ndefine pcodeop TLBI_IPAS2LE1;\ndefine pcodeop TLBI_IPAS2LE1IS;\ndefine pcodeop TLBI_VAAE1;\ndefine pcodeop TLBI_VAALE1;\ndefine pcodeop TLBI_VAAE1IS;\ndefine pcodeop TLBI_VAALE1IS;\ndefine pcodeop TLBI_VAE1;\ndefine pcodeop TLBI_VAE1IS;\ndefine pcodeop TLBI_VAE2;\ndefine pcodeop TLBI_VAE2IS;\ndefine pcodeop TLBI_VAE3;\ndefine pcodeop TLBI_VAE3IS;\ndefine pcodeop TLBI_VALE1;\ndefine pcodeop TLBI_VALE1IS;\ndefine pcodeop TLBI_VALE2;\ndefine pcodeop TLBI_VALE2IS;\ndefine pcodeop TLBI_VALE3;\ndefine pcodeop TLBI_VALE3IS;\ndefine pcodeop TLBI_VMALLE1;\ndefine pcodeop TLBI_VMALLE1IS;\ndefine pcodeop TLBI_VMALLS12E1;\ndefine pcodeop TLBI_VMALLS12E1IS;\ndefine pcodeop UndefinedInstructionException;\ndefine pcodeop UnkSytemRegRead;\ndefine pcodeop UnkSytemRegWrite;\ndefine pcodeop WaitForEvent;\ndefine pcodeop WaitForInterrupt;\ndefine pcodeop xpac;\ndefine pcodeop Yield;\n\n# BTI and MemTag pseudo ops\n\ndefine pcodeop CopyPtrTag_AddToPtrTag_Exclude; # a combination of the ARM spec's ChooseNonExcludedTag and AddressWithAllocationTag\ndefine pcodeop ValidCallTarget;\ndefine pcodeop ValidJumpTarget; # jumps are valid regardless of the register holding the target\ndefine pcodeop ValidJumpTargetWhenDestIsX16OrX17; # jumps are valid if the register holding the target is x16 or x17, e.g. \"br x16\"\ndefine pcodeop ValidJumpTargetIfPermittedBySCTLR; # depending on EL and SCTLR[35,36], jumps using arbitrary registers may or may not be valid.\ndefine pcodeop ControlFlowPredictionRestrictionByContext;\ndefine pcodeop CachePrefetchPredictionRestrictionByContext;\ndefine pcodeop DataValuePredictionRestrictionByContext;\ndefine pcodeop RandomizePtrTag_Exclude;\ndefine pcodeop SetPtrTag; # this could be implemented in pcode, but it would break the data flow of the original ptr value\ndefine pcodeop LoadMemTag;\ndefine pcodeop StoreMemTag;\ndefine pcodeop AlignmentFault;\n\n# BTI show/hide operations, which use pcodeops defined above\n\n# for BTI\nBTI_BTITARGETS: is b_0607=0 { } # Not a valid target for jumps or calls\nBTI_BTITARGETS: \"c\" is ShowBTI=1 & b_0607=1 { ValidCallTarget(); ValidJumpTargetWhenDestIsX16OrX17(); } # BR x16 is valid, BR x5 isn't\nBTI_BTITARGETS: \"j\" is ShowBTI=1 & b_0607=2 { ValidJumpTarget(); }\nBTI_BTITARGETS: \"jc\" is ShowBTI=1 & b_0607=3 { ValidJumpTarget(); ValidCallTarget(); }\n# hidden versions of the above; use to prevent ValidXXXXTarget calls from cluttering decompiled code in switch statements etc.\nBTI_BTITARGETS: \"c\" is ShowBTI=0 & b_0607=1 { }\nBTI_BTITARGETS: \"j\" is ShowBTI=0 & b_0607=2 { }\nBTI_BTITARGETS: \"jc\" is ShowBTI=0 & b_0607=3 { }\n\n# for BRK and HLT\nALL_BTITARGETS: is ShowBTI=1 { ValidJumpTarget(); ValidCallTarget(); }\nALL_BTITARGETS: is ShowBTI=0 { }\n\n# for PACIASP and PACIBSP\nPACIXSP_BTITARGETS: is ShowBTI=1 {\n\tValidCallTarget();\n\tValidJumpTargetWhenDestIsX16OrX17();\n\t# global jump target in the following cases:\n\t# EL == 0 and SCTLR[35] == 0\n\t# EL != 0 and SCTLR[36] == 0\n\tValidJumpTargetIfPermittedBySCTLR(); # this doesn't seem important enough to clutter decompilations with a decision tree\n}\nPACIXSP_BTITARGETS: is ShowBTI=0 { }\n\n\n# These pseudo ops are used in neon\n\ndefine pcodeop SIMD_PIECE;\n\ndefine pcodeop NEON_aesd;\ndefine pcodeop NEON_aese;\ndefine pcodeop NEON_aesimc;\ndefine pcodeop NEON_aesmc;\ndefine pcodeop NEON_bfdot;\ndefine pcodeop NEON_bfmlalb;\ndefine pcodeop NEON_bfmlalt;\ndefine pcodeop NEON_bfmmla;\ndefine pcodeop NEON_cls;\ndefine pcodeop NEON_ext;\ndefine pcodeop NEON_facge;\ndefine pcodeop NEON_facgt;\ndefine pcodeop NEON_fcadd;\ndefine pcodeop NEON_fcmeq;\ndefine pcodeop NEON_fcmge;\ndefine pcodeop NEON_fcmgt;\ndefine pcodeop NEON_fcmla;\ndefine pcodeop NEON_fcmle;\ndefine pcodeop NEON_fcmlt;\ndefine pcodeop NEON_fcvtzs;\ndefine pcodeop NEON_fcvtzu;\ndefine pcodeop NEON_fmax;\ndefine pcodeop NEON_fmaxnm;\ndefine pcodeop NEON_fmaxnmp;\ndefine pcodeop NEON_fmaxnmv;\ndefine pcodeop NEON_fmaxp;\ndefine pcodeop NEON_fmaxv;\ndefine pcodeop NEON_fmin;\ndefine pcodeop NEON_fminnm;\ndefine pcodeop NEON_fminnmp;\ndefine pcodeop NEON_fminnmv;\ndefine pcodeop NEON_fminp;\ndefine pcodeop NEON_fminv;\ndefine pcodeop NEON_fmov;\ndefine pcodeop NEON_fmulx;\ndefine pcodeop NEON_fnmadd;\ndefine pcodeop NEON_fnmsub;\ndefine pcodeop NEON_frecpe;\ndefine pcodeop NEON_frecps;\ndefine pcodeop NEON_frecpx;\ndefine pcodeop NEON_frsqrte;\ndefine pcodeop NEON_frsqrts;\ndefine pcodeop NEON_fsqrt;\ndefine pcodeop NEON_neg;\ndefine pcodeop NEON_pmul;\ndefine pcodeop NEON_pmull;\ndefine pcodeop NEON_pmull2;\ndefine pcodeop NEON_raddhn;\ndefine pcodeop NEON_rbit;\ndefine pcodeop NEON_rev16;\ndefine pcodeop NEON_rev32;\ndefine pcodeop NEON_rev64;\ndefine pcodeop NEON_rshrn;\ndefine pcodeop NEON_rshrn2;\ndefine pcodeop NEON_rsubhn;\ndefine pcodeop NEON_rsubhn2;\ndefine pcodeop NEON_saba;\ndefine pcodeop NEON_sabd;\ndefine pcodeop NEON_saddlv;\ndefine pcodeop NEON_scvtf;\ndefine pcodeop NEON_sdot;\ndefine pcodeop NEON_sha1c;\ndefine pcodeop NEON_sha1m;\ndefine pcodeop NEON_sha1p;\ndefine pcodeop NEON_sha1su0;\ndefine pcodeop NEON_sha1su1;\ndefine pcodeop NEON_sha256h;\ndefine pcodeop NEON_sha256h2;\ndefine pcodeop NEON_sha256su0;\ndefine pcodeop NEON_sha256su1;\ndefine pcodeop NEON_sha512h;\ndefine pcodeop NEON_sha512h2;\ndefine pcodeop NEON_sha512su0;\ndefine pcodeop NEON_sha512su1;\ndefine pcodeop NEON_shadd;\ndefine pcodeop NEON_shl;\ndefine pcodeop NEON_shsub;\ndefine pcodeop NEON_sli;\ndefine pcodeop NEON_sm3partw1;\ndefine pcodeop NEON_sm3partw2;\ndefine pcodeop NEON_sm3ss1;\ndefine pcodeop NEON_sm3tt1a;\ndefine pcodeop NEON_sm3tt1b;\ndefine pcodeop NEON_sm3tt2a;\ndefine pcodeop NEON_sm3tt2b;\ndefine pcodeop NEON_sm4e;\ndefine pcodeop NEON_sm4ekey;\ndefine pcodeop NEON_smax;\ndefine pcodeop NEON_smaxp;\ndefine pcodeop NEON_smaxv;\ndefine pcodeop NEON_smin;\ndefine pcodeop NEON_sminp;\ndefine pcodeop NEON_sminv;\ndefine pcodeop NEON_smmla;\ndefine pcodeop NEON_sqadd;\ndefine pcodeop NEON_sqdmulh;\ndefine pcodeop NEON_sqdmull;\ndefine pcodeop NEON_sqrdml_as_h;\ndefine pcodeop NEON_sqrdmulh;\ndefine pcodeop NEON_sqrshl;\ndefine pcodeop NEON_sqrshrn;\ndefine pcodeop NEON_sqrshrn2;\ndefine pcodeop NEON_sqrshrun;\ndefine pcodeop NEON_sqrshrun2;\ndefine pcodeop NEON_sqshl;\ndefine pcodeop NEON_sqshlu;\ndefine pcodeop NEON_sqshrn;\ndefine pcodeop NEON_sqshrn2;\ndefine pcodeop NEON_sqshrun;\ndefine pcodeop NEON_sqshrun2;\ndefine pcodeop NEON_sqsub;\ndefine pcodeop NEON_sqxtn;\ndefine pcodeop NEON_sqxtn2;\ndefine pcodeop NEON_sqxtun;\ndefine pcodeop NEON_sqxtun2;\ndefine pcodeop NEON_srhadd;\ndefine pcodeop NEON_sri;\ndefine pcodeop NEON_srshl;\ndefine pcodeop NEON_srshr;\ndefine pcodeop NEON_sshl;\ndefine pcodeop NEON_sshr;\ndefine pcodeop NEON_sudot;\ndefine pcodeop NEON_uaba;\ndefine pcodeop NEON_uabd;\ndefine pcodeop NEON_uaddlv;\ndefine pcodeop NEON_ucvtf;\ndefine pcodeop NEON_udot;\ndefine pcodeop NEON_uhadd;\ndefine pcodeop NEON_uhsub;\ndefine pcodeop NEON_umax;\ndefine pcodeop NEON_umaxp;\ndefine pcodeop NEON_umaxv;\ndefine pcodeop NEON_umin;\ndefine pcodeop NEON_uminp;\ndefine pcodeop NEON_uminv;\ndefine pcodeop NEON_ummla;\ndefine pcodeop NEON_umull;\ndefine pcodeop NEON_uqadd;\ndefine pcodeop NEON_uqrshl;\ndefine pcodeop NEON_uqrshrn;\ndefine pcodeop NEON_uqrshrn2;\ndefine pcodeop NEON_uqshl;\ndefine pcodeop NEON_uqshrn;\ndefine pcodeop NEON_uqshrn2;\ndefine pcodeop NEON_uqsub;\ndefine pcodeop NEON_uqxtn;\ndefine pcodeop NEON_uqxtn2;\ndefine pcodeop NEON_urecpe;\ndefine pcodeop NEON_urhadd;\ndefine pcodeop NEON_urshl;\ndefine pcodeop NEON_urshr;\ndefine pcodeop NEON_ursqrte;\ndefine pcodeop NEON_usdot;\ndefine pcodeop NEON_ushl;\ndefine pcodeop NEON_usmmla;\ndefine pcodeop NEON_usqadd;\n\n# These pseudo ops are automatically generated\n\ndefine pcodeop SVE_abs;\ndefine pcodeop SVE_add;\ndefine pcodeop SVE_addpl;\ndefine pcodeop SVE_addvl;\ndefine pcodeop SVE_adr;\ndefine pcodeop SVE_and;\ndefine pcodeop SVE_ands;\ndefine pcodeop SVE_andv;\ndefine pcodeop SVE_asr;\ndefine pcodeop SVE_asrd;\ndefine pcodeop SVE_asrr;\ndefine pcodeop SVE_bic;\ndefine pcodeop SVE_bics;\ndefine pcodeop SVE_brka;\ndefine pcodeop SVE_brkas;\ndefine pcodeop SVE_brkb;\ndefine pcodeop SVE_brkbs;\ndefine pcodeop SVE_brkn;\ndefine pcodeop SVE_brkns;\ndefine pcodeop SVE_brkpa;\ndefine pcodeop SVE_brkpas;\ndefine pcodeop SVE_brkpb;\ndefine pcodeop SVE_brkpbs;\ndefine pcodeop SVE_clasta;\ndefine pcodeop SVE_clastb;\ndefine pcodeop SVE_cls;\ndefine pcodeop SVE_clz;\ndefine pcodeop SVE_cmpeq;\ndefine pcodeop SVE_cmpge;\ndefine pcodeop SVE_cmpgt;\ndefine pcodeop SVE_cmphi;\ndefine pcodeop SVE_cmphs;\ndefine pcodeop SVE_cmple;\ndefine pcodeop SVE_cmplo;\ndefine pcodeop SVE_cmpls;\ndefine pcodeop SVE_cmplt;\ndefine pcodeop SVE_cmpne;\ndefine pcodeop SVE_cnot;\ndefine pcodeop SVE_cnt;\ndefine pcodeop SVE_cntb;\ndefine pcodeop SVE_cntd;\ndefine pcodeop SVE_cnth;\ndefine pcodeop SVE_cntp;\ndefine pcodeop SVE_cntw;\ndefine pcodeop SVE_compact;\ndefine pcodeop SVE_cpy;\ndefine pcodeop SVE_ctermeq;\ndefine pcodeop SVE_ctermne;\ndefine pcodeop SVE_decb;\ndefine pcodeop SVE_decd;\ndefine pcodeop SVE_dech;\ndefine pcodeop SVE_decp;\ndefine pcodeop SVE_decw;\ndefine pcodeop SVE_dup;\ndefine pcodeop SVE_dupm;\ndefine pcodeop SVE_eon;\ndefine pcodeop SVE_eor;\ndefine pcodeop SVE_eors;\ndefine pcodeop SVE_eorv;\ndefine pcodeop SVE_ext;\ndefine pcodeop SVE_fabd;\ndefine pcodeop SVE_fabs;\ndefine pcodeop SVE_facge;\ndefine pcodeop SVE_facgt;\ndefine pcodeop SVE_fadd;\ndefine pcodeop SVE_fadda;\ndefine pcodeop SVE_faddv;\ndefine pcodeop SVE_fcadd;\ndefine pcodeop SVE_fcmeq;\ndefine pcodeop SVE_fcmge;\ndefine pcodeop SVE_fcmgt;\ndefine pcodeop SVE_fcmla;\ndefine pcodeop SVE_fcmle;\ndefine pcodeop SVE_fcmlt;\ndefine pcodeop SVE_fcmne;\ndefine pcodeop SVE_fcmuo;\ndefine pcodeop SVE_fcpy;\ndefine pcodeop SVE_fcvt;\ndefine pcodeop SVE_fcvtzs;\ndefine pcodeop SVE_fcvtzu;\ndefine pcodeop SVE_fdiv;\ndefine pcodeop SVE_fdivr;\ndefine pcodeop SVE_fdup;\ndefine pcodeop SVE_fexpa;\ndefine pcodeop SVE_fmad;\ndefine pcodeop SVE_fmax;\ndefine pcodeop SVE_fmaxnm;\ndefine pcodeop SVE_fmaxnmv;\ndefine pcodeop SVE_fmaxv;\ndefine pcodeop SVE_fmin;\ndefine pcodeop SVE_fminnm;\ndefine pcodeop SVE_fminnmv;\ndefine pcodeop SVE_fminv;\ndefine pcodeop SVE_fmla;\ndefine pcodeop SVE_fmls;\ndefine pcodeop SVE_fmov;\ndefine pcodeop SVE_fmsb;\ndefine pcodeop SVE_fmul;\ndefine pcodeop SVE_fmulx;\ndefine pcodeop SVE_fneg;\ndefine pcodeop SVE_fnmad;\ndefine pcodeop SVE_fnmla;\ndefine pcodeop SVE_fnmls;\ndefine pcodeop SVE_fnmsb;\ndefine pcodeop SVE_frecpe;\ndefine pcodeop SVE_frecps;\ndefine pcodeop SVE_frecpx;\ndefine pcodeop SVE_frinta;\ndefine pcodeop SVE_frinti;\ndefine pcodeop SVE_frintm;\ndefine pcodeop SVE_frintn;\ndefine pcodeop SVE_frintp;\ndefine pcodeop SVE_frintx;\ndefine pcodeop SVE_frintz;\ndefine pcodeop SVE_frsqrte;\ndefine pcodeop SVE_frsqrts;\ndefine pcodeop SVE_fscale;\ndefine pcodeop SVE_fsqrt;\ndefine pcodeop SVE_fsub;\ndefine pcodeop SVE_fsubr;\ndefine pcodeop SVE_ftmad;\ndefine pcodeop SVE_ftsmul;\ndefine pcodeop SVE_ftssel;\ndefine pcodeop SVE_incb;\ndefine pcodeop SVE_incd;\ndefine pcodeop SVE_inch;\ndefine pcodeop SVE_incp;\ndefine pcodeop SVE_incw;\ndefine pcodeop SVE_index;\ndefine pcodeop SVE_insr;\ndefine pcodeop SVE_lasta;\ndefine pcodeop SVE_lastb;\ndefine pcodeop SVE_ld1b;\ndefine pcodeop SVE_ld1d;\ndefine pcodeop SVE_ld1h;\ndefine pcodeop SVE_ld1rb;\ndefine pcodeop SVE_ld1rd;\ndefine pcodeop SVE_ld1rh;\ndefine pcodeop SVE_ld1rqb;\ndefine pcodeop SVE_ld1rqd;\ndefine pcodeop SVE_ld1rqh;\ndefine pcodeop SVE_ld1rqw;\ndefine pcodeop SVE_ld1rsb;\ndefine pcodeop SVE_ld1rsh;\ndefine pcodeop SVE_ld1rsw;\ndefine pcodeop SVE_ld1rw;\ndefine pcodeop SVE_ld1sb;\ndefine pcodeop SVE_ld1sh;\ndefine pcodeop SVE_ld1sw;\ndefine pcodeop SVE_ld1w;\ndefine pcodeop SVE_ld2b;\ndefine pcodeop SVE_ld2d;\ndefine pcodeop SVE_ld2h;\ndefine pcodeop SVE_ld2w;\ndefine pcodeop SVE_ld3b;\ndefine pcodeop SVE_ld3d;\ndefine pcodeop SVE_ld3h;\ndefine pcodeop SVE_ld3w;\ndefine pcodeop SVE_ld4b;\ndefine pcodeop SVE_ld4d;\ndefine pcodeop SVE_ld4h;\ndefine pcodeop SVE_ld4w;\ndefine pcodeop SVE_ldff1b;\ndefine pcodeop SVE_ldff1d;\ndefine pcodeop SVE_ldff1h;\ndefine pcodeop SVE_ldff1sb;\ndefine pcodeop SVE_ldff1sh;\ndefine pcodeop SVE_ldff1sw;\ndefine pcodeop SVE_ldff1w;\ndefine pcodeop SVE_ldnf1b;\ndefine pcodeop SVE_ldnf1d;\ndefine pcodeop SVE_ldnf1h;\ndefine pcodeop SVE_ldnf1sb;\ndefine pcodeop SVE_ldnf1sh;\ndefine pcodeop SVE_ldnf1sw;\ndefine pcodeop SVE_ldnf1w;\ndefine pcodeop SVE_ldnt1b;\ndefine pcodeop SVE_ldnt1d;\ndefine pcodeop SVE_ldnt1h;\ndefine pcodeop SVE_ldnt1w;\ndefine pcodeop SVE_ldr;\ndefine pcodeop SVE_lsl;\ndefine pcodeop SVE_lslr;\ndefine pcodeop SVE_lsr;\ndefine pcodeop SVE_lsrr;\ndefine pcodeop SVE_mad;\ndefine pcodeop SVE_mla;\ndefine pcodeop SVE_mls;\ndefine pcodeop SVE_movprfx;\ndefine pcodeop SVE_msb;\ndefine pcodeop SVE_mul;\ndefine pcodeop SVE_nand;\ndefine pcodeop SVE_nands;\ndefine pcodeop SVE_neg;\ndefine pcodeop SVE_nor;\ndefine pcodeop SVE_nors;\ndefine pcodeop SVE_not;\ndefine pcodeop SVE_orn;\ndefine pcodeop SVE_orns;\ndefine pcodeop SVE_orr;\ndefine pcodeop SVE_orrs;\ndefine pcodeop SVE_orv;\ndefine pcodeop SVE_pfalse;\ndefine pcodeop SVE_pfirst;\ndefine pcodeop SVE_pnext;\ndefine pcodeop SVE_prfb;\ndefine pcodeop SVE_prfd;\ndefine pcodeop SVE_prfh;\ndefine pcodeop SVE_prfw;\ndefine pcodeop SVE_ptest;\ndefine pcodeop SVE_ptrue;\ndefine pcodeop SVE_ptrues;\ndefine pcodeop SVE_punpkhi;\ndefine pcodeop SVE_punpklo;\ndefine pcodeop SVE_rbit;\ndefine pcodeop SVE_rdffr;\ndefine pcodeop SVE_rdffrs;\ndefine pcodeop SVE_rdvl;\ndefine pcodeop SVE_rev;\ndefine pcodeop SVE_revb;\ndefine pcodeop SVE_revh;\ndefine pcodeop SVE_revw;\ndefine pcodeop SVE_sabd;\ndefine pcodeop SVE_saddv;\ndefine pcodeop SVE_scvtf;\ndefine pcodeop SVE_sdiv;\ndefine pcodeop SVE_sdivr;\ndefine pcodeop SVE_sdot;\ndefine pcodeop SVE_sel;\ndefine pcodeop SVE_smax;\ndefine pcodeop SVE_smaxv;\ndefine pcodeop SVE_smin;\ndefine pcodeop SVE_sminv;\ndefine pcodeop SVE_smulh;\ndefine pcodeop SVE_splice;\ndefine pcodeop SVE_sqadd;\ndefine pcodeop SVE_sqdecb;\ndefine pcodeop SVE_sqdecd;\ndefine pcodeop SVE_sqdech;\ndefine pcodeop SVE_sqdecp;\ndefine pcodeop SVE_sqdecw;\ndefine pcodeop SVE_sqincb;\ndefine pcodeop SVE_sqincd;\ndefine pcodeop SVE_sqinch;\ndefine pcodeop SVE_sqincp;\ndefine pcodeop SVE_sqincw;\ndefine pcodeop SVE_sqsub;\ndefine pcodeop SVE_st1b;\ndefine pcodeop SVE_st1d;\ndefine pcodeop SVE_st1h;\ndefine pcodeop SVE_st1w;\ndefine pcodeop SVE_st2b;\ndefine pcodeop SVE_st2d;\ndefine pcodeop SVE_st2h;\ndefine pcodeop SVE_st2w;\ndefine pcodeop SVE_st3b;\ndefine pcodeop SVE_st3d;\ndefine pcodeop SVE_st3h;\ndefine pcodeop SVE_st3w;\ndefine pcodeop SVE_st4b;\ndefine pcodeop SVE_st4d;\ndefine pcodeop SVE_st4h;\ndefine pcodeop SVE_st4w;\ndefine pcodeop SVE_stnt1b;\ndefine pcodeop SVE_stnt1d;\ndefine pcodeop SVE_stnt1h;\ndefine pcodeop SVE_stnt1w;\ndefine pcodeop SVE_str;\ndefine pcodeop SVE_sub;\ndefine pcodeop SVE_subr;\ndefine pcodeop SVE_sunpkhi;\ndefine pcodeop SVE_sunpklo;\ndefine pcodeop SVE_sxtb;\ndefine pcodeop SVE_sxth;\ndefine pcodeop SVE_sxtw;\ndefine pcodeop SVE_tbl;\ndefine pcodeop SVE_trn1;\ndefine pcodeop SVE_trn2;\ndefine pcodeop SVE_uabd;\ndefine pcodeop SVE_uaddv;\ndefine pcodeop SVE_ucvtf;\ndefine pcodeop SVE_udiv;\ndefine pcodeop SVE_udivr;\ndefine pcodeop SVE_udot;\ndefine pcodeop SVE_umax;\ndefine pcodeop SVE_umaxv;\ndefine pcodeop SVE_umin;\ndefine pcodeop SVE_uminv;\ndefine pcodeop SVE_umulh;\ndefine pcodeop SVE_uqadd;\ndefine pcodeop SVE_uqdecb;\ndefine pcodeop SVE_uqdecd;\ndefine pcodeop SVE_uqdech;\ndefine pcodeop SVE_uqdecp;\ndefine pcodeop SVE_uqdecw;\ndefine pcodeop SVE_uqincb;\ndefine pcodeop SVE_uqincd;\ndefine pcodeop SVE_uqinch;\ndefine pcodeop SVE_uqincp;\ndefine pcodeop SVE_uqincw;\ndefine pcodeop SVE_uqsub;\ndefine pcodeop SVE_uunpkhi;\ndefine pcodeop SVE_uunpklo;\ndefine pcodeop SVE_uxtb;\ndefine pcodeop SVE_uxth;\ndefine pcodeop SVE_uxtw;\ndefine pcodeop SVE_uzp1;\ndefine pcodeop SVE_uzp2;\ndefine pcodeop SVE_whilele;\ndefine pcodeop SVE_whilelo;\ndefine pcodeop SVE_whilels;\ndefine pcodeop SVE_whilelt;\ndefine pcodeop SVE_wrffr;\ndefine pcodeop SVE_zip1;\ndefine pcodeop SVE_zip2;\n\n# SECTION macros\n\n# begin macros related to memory-tagging\n\nmacro AllocationTagFromAddress(result, op)\n{\n\t# Summary: Sometimes the decompiler won't show this, but that's usually okay.\n\t#\n\t# A potential downside to actually implementing this, rather than using a pseudo-op,\n\t# is that the whole operation can get optimized out to zero by the decompiler when\n\t# tags are being ignored/non-populated by the user. (This zero-tagging is helped along by\n\t# SetPtrTag being a pseudo-op rather than a macro, which is done to preserve data-flow.)\n\t# The optimization makes it harder to tell that tag-related things are happening;\n\t# however, it's arguably convenient to omit a bunch of tag-related stuff when tags\n\t# are being ignored by the user.\n\n\tresult = (op >> 56) & 0xf;\n\t # decompiler output: return unaff_x30 | 1 << ((ulonglong)register0x00000008 >> 0x38 & 0xf);\n\t# An alternate implementation is the following, which has the downside of adding at least one extra length conversion:\n\t# result = zext(op[56,4]);\n\t # decompiler output: return unaff_x30 | 1 << (ulonglong)((byte)((ulonglong)register0x00000008 >> 0x38) & 0xf);\n}\n\nmacro Align(value, sze)\n{\n\tvalue = value & ~(sze - 1);\n}\n\nmacro RequireGranuleAlignment(addr)\n{\n\tmisalignment:8 = addr & ($(TAG_GRANULE) - 1);\n\tif (misalignment == 0) goto ;\n\tAlignmentFault();\n\n}\n\nmacro Or2BytesWithExcludedTags(tmp)\n{\n\ttmp = (tmp | gcr_el1.exclude) & 0xffff;\n}\n\n# end of memory-tagging macros\n\nmacro addflags(op1, op2)\n{\n\ttmpCY = carry(op1, op2);\n\ttmpOV = scarry(op1, op2);\n}\n\nmacro add_with_carry_flags(op1,op2){\n\tlocal carry_in = zext(CY);\n\tlocal tempResult = op1 + op2;\n\ttmpCY = carry(op1,op2) || carry(tempResult, carry_in);\n tmpOV = scarry(op1,op2) ^^ scarry(tempResult, carry_in);\n}\n\nmacro affectflags()\n{\n\tNG = tmpNG; ZR = tmpZR; CY = tmpCY; OV = tmpOV;\n}\n\nmacro affectLflags()\n{\n\tNG = tmpNG; ZR = tmpZR; CY = 0; OV = 0;\n}\n\n# NOTE unlike x86, carry flag is SET if there is NO borrow\nmacro subflags(op1, op2)\n{\n\ttmpCY = op1 >= op2;\n\ttmpOV = sborrow(op1, op2);\n}\n\n# Special case when the first op of the macro call is 0\nmacro subflags0(op2)\n{\n\ttmpCY = 0 == op2;\n\ttmpOV = sborrow(0, op2);\n}\n\nmacro logicflags()\n{\n\ttmpCY = shift_carry;\n\ttmpOV = OV;\n}\n\nmacro CVunaffected()\n{\n\ttmpCY = CY;\n\ttmpOV = OV;\n}\n\nmacro resultflags(result)\n{\n\ttmpNG = result s< 0;\n\ttmpZR = result == 0;\n}\n\nmacro fcomp(a, b)\n{\n\tNG = a f< b;\n\tZR = a f== b;\n\tCY = a f>= b;\n\tOV = 0;\n}\n\n# this sets NG, ZR, CY, and OV to the values the processor\n# uses to indicate an unordered comparison. If at least \n# one of the inputs is NaN, it skips to the next instruction.\n# A use of this macro should be followed by a use of the\n# fcomp macro, which will set the flags according to an \n# ordered comparison. Basically, set the flags to the \"unordered\"\n# values, check for unordered, and if not set the flags again with\n# fcomp.\nmacro ftestNAN(a, b)\n{\n\tNG = 0;\n\tZR = 0;\n\tCY = 1;\n\tOV = 1;\n\ttst:1 = nan(a) || nan(b);\n\tif (tst) goto inst_next;\n}\n\nmacro ROR32(out, val, rotate)\n{\n\tout = ( val >> rotate) | ( val << ( 32 - rotate ) );\n}\n\nmacro ROR64(out, val, rotate)\n{\n\tout = ( val >> rotate) | ( val << ( 64 - rotate ) );\n}\n\nmacro selectCC(result, val1, val2, condition)\n{\n\tresult = (zext(condition) * val1) + (zext(!condition) * val2);\n}\n\nmacro setCC_NZCV(condMask)\n{\n\tNG = (condMask & 0x8) == 0x8;\n\tZR = (condMask & 0x4) == 0x4;\n\tCY = (condMask & 0x2) == 0x2;\n\tOV = (condMask & 0x1) == 0x1;\n}\n\nmacro set_NZCV(value, condMask)\n{\n setNG:1 = (condMask & 0x8) == 0x8;\n\tNG = ((setNG==0) * NG) | ((setNG==1) * (((value >> 3) & 1) ==1));\n\tsetZR:1 = (condMask & 0x4) == 0x4;\n\tZR = ((setZR==0) * NG) | ((setZR==1) * (((value >> 2) & 1) ==1));\n\tsetCY:1 = (condMask & 0x2) == 0x2;\n\tCY = ((setCY==0) * NG) | ((setCY==1) * (((value >> 1) & 1) == 1));\n\tsetOV:1 = (condMask & 0x1) == 0x1;\n\tOV = ((setOV==0) * NG) | ((setOV==1) * (((value >> 0) & 1) == 1));\n}\n\n# Macro to access simd lanes\n\n# Macros to zero the high bits of the Z or Q registers\n# These are friendlier to the decompiler\n\nmacro zext_zb(reg)\n{\n\treg[8,56] = 0;\n\treg[64,64] = 0;\n\treg[128,64] = 0;\n\treg[192,64] = 0;\n}\n\nmacro zext_zh(reg)\n{\n\treg[16,48] = 0;\n\treg[64,64] = 0;\n\treg[128,64] = 0;\n\treg[192,64] = 0;\n}\n\nmacro zext_zs(reg)\n{\n\treg[32,32] = 0;\n\treg[64,64] = 0;\n\treg[128,64] = 0;\n\treg[192,64] = 0;\n}\n\nmacro zext_zd(reg)\n{\n\treg[64,64] = 0;\n\treg[128,64] = 0;\n\treg[192,64] = 0;\n}\n\nmacro zext_zq(reg)\n{\n\treg[128,64] = 0;\n\treg[192,64] = 0;\n}\n\nmacro zext_rb(reg)\n{\n\treg[8,56] = 0;\n}\n\nmacro zext_rh(reg)\n{\n\treg[16,48] = 0;\n}\n\nmacro zext_rs(reg)\n{\n\treg[32,32] = 0;\n}\n\n# SECTION instructions\n\n:^instruction\nis ImmS_ImmR_TestSet=0 & ImmR & ImmS & instruction\n[\n\tImmS_LT_ImmR = (((ImmS - ImmR) >> 6) $and 1);\n\tImmS_EQ_ImmR = ~((((ImmS - ImmR) >> 6) $and 1) | (((ImmR - ImmS) >> 6) $and 1));\n\t# For ubfm, lsl is the preferred alias when imms + 1 == immr, so we must subtract an extra one\n\t# to determine when ubfiz is the preferred alias.\n\tImmS_LT_ImmR_minus_1 = (((ImmS - (ImmR - 1)) >> 6) & 0x1) & (((ImmS - (ImmR - 1)) >> 7) & 0x1);\n\tImmS_ne_1f = (((ImmS - 0x1f) >> 6) & 0x1) | (((0x1f - ImmS) >> 6) & 0x1);\n\tImmS_ne_3f = (((ImmS - 0x3f) >> 6) & 0x1) | (((0x3f - ImmS) >> 6) & 0x1);\n\tImmS_ImmR_TestSet=1;\n]{}\n\nwith : ImmS_ImmR_TestSet=1 {\n\t\n@include \"AARCH64_base_PACoptions.sinc\"\n\n@include \"AARCH64base.sinc\"\n@include \"AARCH64neon.sinc\"\n@include \"AARCH64ldst.sinc\"\n@include \"AARCH64sve.sinc\"\n\n# TODO These are placeholders until the correction instruction implementations can be found\n\n:NotYetImplemented_UNK1\nis b_0031=0xe7ffdeff\nunimpl\n\n:NotYetImplemented_UNK2\nis b_0031=0x00200820\nunimpl\n\n:NotYetImplemented_UNK3\nis b_0031=0x00200c20\nunimpl\n\n} # end with ImmS_ImmR_TestSet=1\n\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64ldst.sinc", "content": "# C7.2.162 LD1 (multiple structures) page C7-1359 line 78995 KEEPWITH\n# INFO This file automatically generated by andre on Fri Jun 8 10:47:29 2018\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['../../../ProcessorTest/test/andre/scrape/a64ldst.py']\n\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=0 & b_13=0 [ tmp = 1; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=0 [ tmp = 1; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=0 & b_13=0 [ tmp = 2; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=1 & b_13=0 & b_10=0 [ tmp = 2; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 2; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=0 [ tmp = 2; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=0 & b_13=1 [ tmp = 3; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=0 [ tmp = 3; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=0 & b_13=1 [ tmp = 4; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=1 & b_13=0 & b_10=0 [ tmp = 4; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=0 & b_11=0 & b_10=0 [ tmp = 4; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 4; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 4; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=0 [ tmp = 4; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_10=0 [ tmp = 6; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 6; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=1 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=1 & b_13=1 & b_10=0 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=0 & b_11=0 & b_10=0 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=1 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 8; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_11=0 & b_10=0 [ tmp = 12; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 12; ] { }\nldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=1 [ tmp = 16; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 & b_11=0 [ tmp = 16; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 16; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 16; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 16; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=1 & b_11=0 & b_10=0 [ tmp = 16; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=1 [ tmp = 16; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 16; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 & b_11=0 [ tmp = 24; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 24; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 24; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 24; ] { }\nldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 24; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 & b_11=0 [ tmp = 32; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 32; ] { }\nldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 32; ] { }\nldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 [ tmp = 32; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 32; ] { }\nldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 32; ] { }\nldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 [ tmp = 48; ] { }\nldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 [ tmp = 64; ] { }\n\nldst_wback: \"\" is b_23=0 & b_1620=0b00000 { }\nldst_wback: \", #\"^ldst_imm is b_23=1 & b_1620=0b11111 & Rn_GPR64xsp & ldst_imm { Rn_GPR64xsp = tmp_ldXn; }\nldst_wback: \", \"^Rm_GPR64 is b_23=1 & Rn_GPR64xsp & Rm_GPR64 { Rn_GPR64xsp = Rn_GPR64xsp + Rm_GPR64; }\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\", vVtttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\", vVtttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\", vVtttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".1D\", vVtt^\".1D\", vVttt^\".1D\", vVtttt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\", vVtttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\", vVtttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\", vVtttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\", vVtttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c406400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c406c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".1D\", vVtt^\".1D\", vVttt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c406400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c406c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c407400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c407c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.1D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.16B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c407400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c407c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8B\", vVtt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4H\", vVtt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c40a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2S\", vVtt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x0c40ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.1D, Vt2.1D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".1D\", vVtt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR64[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".16B\", vVtt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".8H\", vVtt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c40a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".4S\", vVtt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000\n# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000\n# CONSTRUCT x4c40ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]\n\n:ld1 {vVt^\".2D\", vVtt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[0], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[1], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[2], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[3], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d401000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[4], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d401400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[5], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d401800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[6], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d401c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[7], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[8], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[9], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[10], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[11], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d401000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[12], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d401400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[13], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d401800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[14], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d401c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.B}[15], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[0], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[1], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d405000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[2], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d405800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[3], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[4], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[5], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d405000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[6], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d405800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.H}[7], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.S}[0], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d409000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.S}[1], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.S}[2], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d409000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.S}[3], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.D}[0], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld1 {Vt.D}[1], [Xn|SP] [, wback]\n\n:ld1 {vVt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d40c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.8B}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR64[0,8] = tmpv;\n\tRt_VPR64[8,8] = tmpv;\n\tRt_VPR64[16,8] = tmpv;\n\tRt_VPR64[24,8] = tmpv;\n\tRt_VPR64[32,8] = tmpv;\n\tRt_VPR64[40,8] = tmpv;\n\tRt_VPR64[48,8] = tmpv;\n\tRt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d40c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.4H}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR64[0,16] = tmpv;\n\tRt_VPR64[16,16] = tmpv;\n\tRt_VPR64[32,16] = tmpv;\n\tRt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d40c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.2S}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR64[0,32] = tmpv;\n\tRt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x0d40cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.1D}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d40c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.16B}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR128[0,8] = tmpv;\n\tRt_VPR128[8,8] = tmpv;\n\tRt_VPR128[16,8] = tmpv;\n\tRt_VPR128[24,8] = tmpv;\n\tRt_VPR128[32,8] = tmpv;\n\tRt_VPR128[40,8] = tmpv;\n\tRt_VPR128[48,8] = tmpv;\n\tRt_VPR128[56,8] = tmpv;\n\tRt_VPR128[64,8] = tmpv;\n\tRt_VPR128[72,8] = tmpv;\n\tRt_VPR128[80,8] = tmpv;\n\tRt_VPR128[88,8] = tmpv;\n\tRt_VPR128[96,8] = tmpv;\n\tRt_VPR128[104,8] = tmpv;\n\tRt_VPR128[112,8] = tmpv;\n\tRt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d40c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.8H}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR128[0,16] = tmpv;\n\tRt_VPR128[16,16] = tmpv;\n\tRt_VPR128[32,16] = tmpv;\n\tRt_VPR128[48,16] = tmpv;\n\tRt_VPR128[64,16] = tmpv;\n\tRt_VPR128[80,16] = tmpv;\n\tRt_VPR128[96,16] = tmpv;\n\tRt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d40c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.4S}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR128[0,32] = tmpv;\n\tRt_VPR128[32,32] = tmpv;\n\tRt_VPR128[64,32] = tmpv;\n\tRt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000\n# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000\n# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000\n# CONSTRUCT x4d40cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld1r {Vt.2D}, [Xn|SP] [, wback]\n\n:ld1r {vVt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR128[0,64] = tmpv;\n\tRt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x0c408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".8B\", vVtt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x0c408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".4H\", vVtt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x0c408800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".2S\", vVtt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x4c408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".16B\", vVtt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x4c408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".8H\", vVtt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x4c408800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".4S\", vVtt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000\n# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000\n# CONSTRUCT x4c408c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]\n\n:ld2 {vVt^\".2D\", vVtt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d600000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[0], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d600400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[1], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d600800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[2], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d600c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[3], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d601000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[4], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d601400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[5], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d601800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[6], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d601c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[7], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d600000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[8], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d600400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[9], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d600800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[10], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d600c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[11], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d601000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[12], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d601400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[13], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d601800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[14], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d601c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.B, Vt2.B}[15], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".B\", vVtt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d604000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[0], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d604800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[1], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d605000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[2], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d605800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[3], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d604000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[4], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d604800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[5], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d605000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[6], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d605800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.H, Vt2.H}[7], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".H\", vVtt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d608000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.S, Vt2.S}[0], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".S\", vVtt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d609000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.S, Vt2.S}[1], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".S\", vVtt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d608000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.S, Vt2.S}[2], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".S\", vVtt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d609000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.S, Vt2.S}[3], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".S\", vVtt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d608400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.D, Vt2.D}[0], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".D\", vVtt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d608400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld2 {Vt.D, Vt2.D}[1], [Xn|SP] [, wback]\n\n:ld2 {vVt^\".D\", vVtt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d60c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".8B\", vVtt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR64[0,8] = tmpv;\n\tRt_VPR64[8,8] = tmpv;\n\tRt_VPR64[16,8] = tmpv;\n\tRt_VPR64[24,8] = tmpv;\n\tRt_VPR64[32,8] = tmpv;\n\tRt_VPR64[40,8] = tmpv;\n\tRt_VPR64[48,8] = tmpv;\n\tRt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtt_VPR64[0,8] = tmpv;\n\tRtt_VPR64[8,8] = tmpv;\n\tRtt_VPR64[16,8] = tmpv;\n\tRtt_VPR64[24,8] = tmpv;\n\tRtt_VPR64[32,8] = tmpv;\n\tRtt_VPR64[40,8] = tmpv;\n\tRtt_VPR64[48,8] = tmpv;\n\tRtt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d60c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".4H\", vVtt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR64[0,16] = tmpv;\n\tRt_VPR64[16,16] = tmpv;\n\tRt_VPR64[32,16] = tmpv;\n\tRt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtt_VPR64[0,16] = tmpv;\n\tRtt_VPR64[16,16] = tmpv;\n\tRtt_VPR64[32,16] = tmpv;\n\tRtt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d60c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".2S\", vVtt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR64[0,32] = tmpv;\n\tRt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtt_VPR64[0,32] = tmpv;\n\tRtt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x0d60cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.1D, Vt2.1D}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".1D\", vVtt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d60c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".16B\", vVtt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR128[0,8] = tmpv;\n\tRt_VPR128[8,8] = tmpv;\n\tRt_VPR128[16,8] = tmpv;\n\tRt_VPR128[24,8] = tmpv;\n\tRt_VPR128[32,8] = tmpv;\n\tRt_VPR128[40,8] = tmpv;\n\tRt_VPR128[48,8] = tmpv;\n\tRt_VPR128[56,8] = tmpv;\n\tRt_VPR128[64,8] = tmpv;\n\tRt_VPR128[72,8] = tmpv;\n\tRt_VPR128[80,8] = tmpv;\n\tRt_VPR128[88,8] = tmpv;\n\tRt_VPR128[96,8] = tmpv;\n\tRt_VPR128[104,8] = tmpv;\n\tRt_VPR128[112,8] = tmpv;\n\tRt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtt_VPR128[0,8] = tmpv;\n\tRtt_VPR128[8,8] = tmpv;\n\tRtt_VPR128[16,8] = tmpv;\n\tRtt_VPR128[24,8] = tmpv;\n\tRtt_VPR128[32,8] = tmpv;\n\tRtt_VPR128[40,8] = tmpv;\n\tRtt_VPR128[48,8] = tmpv;\n\tRtt_VPR128[56,8] = tmpv;\n\tRtt_VPR128[64,8] = tmpv;\n\tRtt_VPR128[72,8] = tmpv;\n\tRtt_VPR128[80,8] = tmpv;\n\tRtt_VPR128[88,8] = tmpv;\n\tRtt_VPR128[96,8] = tmpv;\n\tRtt_VPR128[104,8] = tmpv;\n\tRtt_VPR128[112,8] = tmpv;\n\tRtt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d60c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".8H\", vVtt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR128[0,16] = tmpv;\n\tRt_VPR128[16,16] = tmpv;\n\tRt_VPR128[32,16] = tmpv;\n\tRt_VPR128[48,16] = tmpv;\n\tRt_VPR128[64,16] = tmpv;\n\tRt_VPR128[80,16] = tmpv;\n\tRt_VPR128[96,16] = tmpv;\n\tRt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtt_VPR128[0,16] = tmpv;\n\tRtt_VPR128[16,16] = tmpv;\n\tRtt_VPR128[32,16] = tmpv;\n\tRtt_VPR128[48,16] = tmpv;\n\tRtt_VPR128[64,16] = tmpv;\n\tRtt_VPR128[80,16] = tmpv;\n\tRtt_VPR128[96,16] = tmpv;\n\tRtt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d60c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".4S\", vVtt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR128[0,32] = tmpv;\n\tRt_VPR128[32,32] = tmpv;\n\tRt_VPR128[64,32] = tmpv;\n\tRt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtt_VPR128[0,32] = tmpv;\n\tRtt_VPR128[32,32] = tmpv;\n\tRtt_VPR128[64,32] = tmpv;\n\tRtt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000\n# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000\n# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000\n# CONSTRUCT x4d60cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld2r {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]\n\n:ld2r {vVt^\".2D\", vVtt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR128[0,64] = tmpv;\n\tRt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtt_VPR128[0,64] = tmpv;\n\tRtt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x0c404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x0c404400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x0c404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x4c404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x4c404400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x4c404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000\n# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000\n# CONSTRUCT x4c404c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]\n\n:ld3 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[0], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[1], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[2], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[3], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d403000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[4], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d403400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[5], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d403800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[6], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d403c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[7], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[8], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[9], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[10], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[11], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d403000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[12], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d403400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[13], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d403800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[14], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d403c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.B, Vt2.B, Vt3.B}[15], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[0], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[1], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[2], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[3], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[4], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[5], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[6], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.H, Vt2.H, Vt3.H}[7], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.S, Vt2.S, Vt3.S}[0], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.S, Vt2.S, Vt3.S}[1], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.S, Vt2.S, Vt3.S}[2], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.S, Vt2.S, Vt3.S}[3], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.D, Vt2.D, Vt3.D}[0], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld3 {Vt.D, Vt2.D, Vt3.D}[1], [Xn|SP] [, wback]\n\n:ld3 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR64[0,8] = tmpv;\n\tRt_VPR64[8,8] = tmpv;\n\tRt_VPR64[16,8] = tmpv;\n\tRt_VPR64[24,8] = tmpv;\n\tRt_VPR64[32,8] = tmpv;\n\tRt_VPR64[40,8] = tmpv;\n\tRt_VPR64[48,8] = tmpv;\n\tRt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtt_VPR64[0,8] = tmpv;\n\tRtt_VPR64[8,8] = tmpv;\n\tRtt_VPR64[16,8] = tmpv;\n\tRtt_VPR64[24,8] = tmpv;\n\tRtt_VPR64[32,8] = tmpv;\n\tRtt_VPR64[40,8] = tmpv;\n\tRtt_VPR64[48,8] = tmpv;\n\tRtt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRttt_VPR64[0,8] = tmpv;\n\tRttt_VPR64[8,8] = tmpv;\n\tRttt_VPR64[16,8] = tmpv;\n\tRttt_VPR64[24,8] = tmpv;\n\tRttt_VPR64[32,8] = tmpv;\n\tRttt_VPR64[40,8] = tmpv;\n\tRttt_VPR64[48,8] = tmpv;\n\tRttt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR64[0,16] = tmpv;\n\tRt_VPR64[16,16] = tmpv;\n\tRt_VPR64[32,16] = tmpv;\n\tRt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtt_VPR64[0,16] = tmpv;\n\tRtt_VPR64[16,16] = tmpv;\n\tRtt_VPR64[32,16] = tmpv;\n\tRtt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRttt_VPR64[0,16] = tmpv;\n\tRttt_VPR64[16,16] = tmpv;\n\tRttt_VPR64[32,16] = tmpv;\n\tRttt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR64[0,32] = tmpv;\n\tRt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtt_VPR64[0,32] = tmpv;\n\tRtt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRttt_VPR64[0,32] = tmpv;\n\tRttt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x0d40ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".1D\", vVtt^\".1D\", vVttt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRttt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR128[0,8] = tmpv;\n\tRt_VPR128[8,8] = tmpv;\n\tRt_VPR128[16,8] = tmpv;\n\tRt_VPR128[24,8] = tmpv;\n\tRt_VPR128[32,8] = tmpv;\n\tRt_VPR128[40,8] = tmpv;\n\tRt_VPR128[48,8] = tmpv;\n\tRt_VPR128[56,8] = tmpv;\n\tRt_VPR128[64,8] = tmpv;\n\tRt_VPR128[72,8] = tmpv;\n\tRt_VPR128[80,8] = tmpv;\n\tRt_VPR128[88,8] = tmpv;\n\tRt_VPR128[96,8] = tmpv;\n\tRt_VPR128[104,8] = tmpv;\n\tRt_VPR128[112,8] = tmpv;\n\tRt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtt_VPR128[0,8] = tmpv;\n\tRtt_VPR128[8,8] = tmpv;\n\tRtt_VPR128[16,8] = tmpv;\n\tRtt_VPR128[24,8] = tmpv;\n\tRtt_VPR128[32,8] = tmpv;\n\tRtt_VPR128[40,8] = tmpv;\n\tRtt_VPR128[48,8] = tmpv;\n\tRtt_VPR128[56,8] = tmpv;\n\tRtt_VPR128[64,8] = tmpv;\n\tRtt_VPR128[72,8] = tmpv;\n\tRtt_VPR128[80,8] = tmpv;\n\tRtt_VPR128[88,8] = tmpv;\n\tRtt_VPR128[96,8] = tmpv;\n\tRtt_VPR128[104,8] = tmpv;\n\tRtt_VPR128[112,8] = tmpv;\n\tRtt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRttt_VPR128[0,8] = tmpv;\n\tRttt_VPR128[8,8] = tmpv;\n\tRttt_VPR128[16,8] = tmpv;\n\tRttt_VPR128[24,8] = tmpv;\n\tRttt_VPR128[32,8] = tmpv;\n\tRttt_VPR128[40,8] = tmpv;\n\tRttt_VPR128[48,8] = tmpv;\n\tRttt_VPR128[56,8] = tmpv;\n\tRttt_VPR128[64,8] = tmpv;\n\tRttt_VPR128[72,8] = tmpv;\n\tRttt_VPR128[80,8] = tmpv;\n\tRttt_VPR128[88,8] = tmpv;\n\tRttt_VPR128[96,8] = tmpv;\n\tRttt_VPR128[104,8] = tmpv;\n\tRttt_VPR128[112,8] = tmpv;\n\tRttt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR128[0,16] = tmpv;\n\tRt_VPR128[16,16] = tmpv;\n\tRt_VPR128[32,16] = tmpv;\n\tRt_VPR128[48,16] = tmpv;\n\tRt_VPR128[64,16] = tmpv;\n\tRt_VPR128[80,16] = tmpv;\n\tRt_VPR128[96,16] = tmpv;\n\tRt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtt_VPR128[0,16] = tmpv;\n\tRtt_VPR128[16,16] = tmpv;\n\tRtt_VPR128[32,16] = tmpv;\n\tRtt_VPR128[48,16] = tmpv;\n\tRtt_VPR128[64,16] = tmpv;\n\tRtt_VPR128[80,16] = tmpv;\n\tRtt_VPR128[96,16] = tmpv;\n\tRtt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRttt_VPR128[0,16] = tmpv;\n\tRttt_VPR128[16,16] = tmpv;\n\tRttt_VPR128[32,16] = tmpv;\n\tRttt_VPR128[48,16] = tmpv;\n\tRttt_VPR128[64,16] = tmpv;\n\tRttt_VPR128[80,16] = tmpv;\n\tRttt_VPR128[96,16] = tmpv;\n\tRttt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR128[0,32] = tmpv;\n\tRt_VPR128[32,32] = tmpv;\n\tRt_VPR128[64,32] = tmpv;\n\tRt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtt_VPR128[0,32] = tmpv;\n\tRtt_VPR128[32,32] = tmpv;\n\tRtt_VPR128[64,32] = tmpv;\n\tRtt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRttt_VPR128[0,32] = tmpv;\n\tRttt_VPR128[32,32] = tmpv;\n\tRttt_VPR128[64,32] = tmpv;\n\tRttt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000\n# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000\n# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000\n# CONSTRUCT x4d40ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld3r {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]\n\n:ld3r {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR128[0,64] = tmpv;\n\tRt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtt_VPR128[0,64] = tmpv;\n\tRtt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRttt_VPR128[0,64] = tmpv;\n\tRttt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x0c400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\", vVtttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR64[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x0c400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\", vVtttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR64[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x0c400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\", vVtttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR64[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR64[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x4c400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\", vVtttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x4c400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\", vVtttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x4c400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\", vVtttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000\n# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000\n# CONSTRUCT x4c400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]\n\n:ld4 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\", vVtttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d602000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[0], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[0,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d602400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[1], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[8,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d602800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[2], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[16,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d602c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[3], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[24,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d603000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[4], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[32,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d603400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[5], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[40,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d603800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[6], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[48,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d603c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[7], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[56,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d602000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[8], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[64,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d602400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[9], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[72,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d602800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[10], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[80,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d602c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[11], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[88,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d603000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[12], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[96,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d603400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[13], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[104,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d603800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[14], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[112,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d603c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[15], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\tRtttt_VPR128[120,8] = *:1 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d606000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[0], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[0,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d606800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[1], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[16,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d607000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[2], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[32,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d607800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[3], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[48,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d606000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[4], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[64,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d606800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[5], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[80,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d607000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[6], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[96,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d607800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[7], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\tRtttt_VPR128[112,16] = *:2 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[0], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[0,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[1], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[32,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[2], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[64,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[3], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\tRtttt_VPR128[96,32] = *:4 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[0], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\", vVtttt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR128[0,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# ld4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[1], [Xn|SP] [, wback]\n\n:ld4 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\", vVtttt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tRt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\tRtttt_VPR128[64,64] = *:8 tmp_ldXn;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\", vVtttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR64[0,8] = tmpv;\n\tRt_VPR64[8,8] = tmpv;\n\tRt_VPR64[16,8] = tmpv;\n\tRt_VPR64[24,8] = tmpv;\n\tRt_VPR64[32,8] = tmpv;\n\tRt_VPR64[40,8] = tmpv;\n\tRt_VPR64[48,8] = tmpv;\n\tRt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtt_VPR64[0,8] = tmpv;\n\tRtt_VPR64[8,8] = tmpv;\n\tRtt_VPR64[16,8] = tmpv;\n\tRtt_VPR64[24,8] = tmpv;\n\tRtt_VPR64[32,8] = tmpv;\n\tRtt_VPR64[40,8] = tmpv;\n\tRtt_VPR64[48,8] = tmpv;\n\tRtt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRttt_VPR64[0,8] = tmpv;\n\tRttt_VPR64[8,8] = tmpv;\n\tRttt_VPR64[16,8] = tmpv;\n\tRttt_VPR64[24,8] = tmpv;\n\tRttt_VPR64[32,8] = tmpv;\n\tRttt_VPR64[40,8] = tmpv;\n\tRttt_VPR64[48,8] = tmpv;\n\tRttt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtttt_VPR64[0,8] = tmpv;\n\tRtttt_VPR64[8,8] = tmpv;\n\tRtttt_VPR64[16,8] = tmpv;\n\tRtttt_VPR64[24,8] = tmpv;\n\tRtttt_VPR64[32,8] = tmpv;\n\tRtttt_VPR64[40,8] = tmpv;\n\tRtttt_VPR64[48,8] = tmpv;\n\tRtttt_VPR64[56,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\", vVtttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR64[0,16] = tmpv;\n\tRt_VPR64[16,16] = tmpv;\n\tRt_VPR64[32,16] = tmpv;\n\tRt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtt_VPR64[0,16] = tmpv;\n\tRtt_VPR64[16,16] = tmpv;\n\tRtt_VPR64[32,16] = tmpv;\n\tRtt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRttt_VPR64[0,16] = tmpv;\n\tRttt_VPR64[16,16] = tmpv;\n\tRttt_VPR64[32,16] = tmpv;\n\tRttt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtttt_VPR64[0,16] = tmpv;\n\tRtttt_VPR64[16,16] = tmpv;\n\tRtttt_VPR64[32,16] = tmpv;\n\tRtttt_VPR64[48,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\", vVtttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR64[0,32] = tmpv;\n\tRt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtt_VPR64[0,32] = tmpv;\n\tRtt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRttt_VPR64[0,32] = tmpv;\n\tRttt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtttt_VPR64[0,32] = tmpv;\n\tRtttt_VPR64[32,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x0d60ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".1D\", vVtt^\".1D\", vVttt^\".1D\", vVtttt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRttt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtttt_VPR64[0,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\", vVtttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:1 = 0;\n\ttmpv = *:1 tmp_ldXn;\n\tRt_VPR128[0,8] = tmpv;\n\tRt_VPR128[8,8] = tmpv;\n\tRt_VPR128[16,8] = tmpv;\n\tRt_VPR128[24,8] = tmpv;\n\tRt_VPR128[32,8] = tmpv;\n\tRt_VPR128[40,8] = tmpv;\n\tRt_VPR128[48,8] = tmpv;\n\tRt_VPR128[56,8] = tmpv;\n\tRt_VPR128[64,8] = tmpv;\n\tRt_VPR128[72,8] = tmpv;\n\tRt_VPR128[80,8] = tmpv;\n\tRt_VPR128[88,8] = tmpv;\n\tRt_VPR128[96,8] = tmpv;\n\tRt_VPR128[104,8] = tmpv;\n\tRt_VPR128[112,8] = tmpv;\n\tRt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtt_VPR128[0,8] = tmpv;\n\tRtt_VPR128[8,8] = tmpv;\n\tRtt_VPR128[16,8] = tmpv;\n\tRtt_VPR128[24,8] = tmpv;\n\tRtt_VPR128[32,8] = tmpv;\n\tRtt_VPR128[40,8] = tmpv;\n\tRtt_VPR128[48,8] = tmpv;\n\tRtt_VPR128[56,8] = tmpv;\n\tRtt_VPR128[64,8] = tmpv;\n\tRtt_VPR128[72,8] = tmpv;\n\tRtt_VPR128[80,8] = tmpv;\n\tRtt_VPR128[88,8] = tmpv;\n\tRtt_VPR128[96,8] = tmpv;\n\tRtt_VPR128[104,8] = tmpv;\n\tRtt_VPR128[112,8] = tmpv;\n\tRtt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRttt_VPR128[0,8] = tmpv;\n\tRttt_VPR128[8,8] = tmpv;\n\tRttt_VPR128[16,8] = tmpv;\n\tRttt_VPR128[24,8] = tmpv;\n\tRttt_VPR128[32,8] = tmpv;\n\tRttt_VPR128[40,8] = tmpv;\n\tRttt_VPR128[48,8] = tmpv;\n\tRttt_VPR128[56,8] = tmpv;\n\tRttt_VPR128[64,8] = tmpv;\n\tRttt_VPR128[72,8] = tmpv;\n\tRttt_VPR128[80,8] = tmpv;\n\tRttt_VPR128[88,8] = tmpv;\n\tRttt_VPR128[96,8] = tmpv;\n\tRttt_VPR128[104,8] = tmpv;\n\tRttt_VPR128[112,8] = tmpv;\n\tRttt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\ttmpv = *:1 tmp_ldXn;\n\tRtttt_VPR128[0,8] = tmpv;\n\tRtttt_VPR128[8,8] = tmpv;\n\tRtttt_VPR128[16,8] = tmpv;\n\tRtttt_VPR128[24,8] = tmpv;\n\tRtttt_VPR128[32,8] = tmpv;\n\tRtttt_VPR128[40,8] = tmpv;\n\tRtttt_VPR128[48,8] = tmpv;\n\tRtttt_VPR128[56,8] = tmpv;\n\tRtttt_VPR128[64,8] = tmpv;\n\tRtttt_VPR128[72,8] = tmpv;\n\tRtttt_VPR128[80,8] = tmpv;\n\tRtttt_VPR128[88,8] = tmpv;\n\tRtttt_VPR128[96,8] = tmpv;\n\tRtttt_VPR128[104,8] = tmpv;\n\tRtttt_VPR128[112,8] = tmpv;\n\tRtttt_VPR128[120,8] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\", vVtttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:2 = 0;\n\ttmpv = *:2 tmp_ldXn;\n\tRt_VPR128[0,16] = tmpv;\n\tRt_VPR128[16,16] = tmpv;\n\tRt_VPR128[32,16] = tmpv;\n\tRt_VPR128[48,16] = tmpv;\n\tRt_VPR128[64,16] = tmpv;\n\tRt_VPR128[80,16] = tmpv;\n\tRt_VPR128[96,16] = tmpv;\n\tRt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtt_VPR128[0,16] = tmpv;\n\tRtt_VPR128[16,16] = tmpv;\n\tRtt_VPR128[32,16] = tmpv;\n\tRtt_VPR128[48,16] = tmpv;\n\tRtt_VPR128[64,16] = tmpv;\n\tRtt_VPR128[80,16] = tmpv;\n\tRtt_VPR128[96,16] = tmpv;\n\tRtt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRttt_VPR128[0,16] = tmpv;\n\tRttt_VPR128[16,16] = tmpv;\n\tRttt_VPR128[32,16] = tmpv;\n\tRttt_VPR128[48,16] = tmpv;\n\tRttt_VPR128[64,16] = tmpv;\n\tRttt_VPR128[80,16] = tmpv;\n\tRttt_VPR128[96,16] = tmpv;\n\tRttt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\ttmpv = *:2 tmp_ldXn;\n\tRtttt_VPR128[0,16] = tmpv;\n\tRtttt_VPR128[16,16] = tmpv;\n\tRtttt_VPR128[32,16] = tmpv;\n\tRtttt_VPR128[48,16] = tmpv;\n\tRtttt_VPR128[64,16] = tmpv;\n\tRtttt_VPR128[80,16] = tmpv;\n\tRtttt_VPR128[96,16] = tmpv;\n\tRtttt_VPR128[112,16] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\", vVtttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:4 = 0;\n\ttmpv = *:4 tmp_ldXn;\n\tRt_VPR128[0,32] = tmpv;\n\tRt_VPR128[32,32] = tmpv;\n\tRt_VPR128[64,32] = tmpv;\n\tRt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtt_VPR128[0,32] = tmpv;\n\tRtt_VPR128[32,32] = tmpv;\n\tRtt_VPR128[64,32] = tmpv;\n\tRtt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRttt_VPR128[0,32] = tmpv;\n\tRttt_VPR128[32,32] = tmpv;\n\tRttt_VPR128[64,32] = tmpv;\n\tRttt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\ttmpv = *:4 tmp_ldXn;\n\tRtttt_VPR128[0,32] = tmpv;\n\tRtttt_VPR128[32,32] = tmpv;\n\tRtttt_VPR128[64,32] = tmpv;\n\tRtttt_VPR128[96,32] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000\n# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000\n# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000\n# CONSTRUCT x4d60ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES\n# ld4r {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]\n\n:ld4r {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\", vVtttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\tlocal tmpv:8 = 0;\n\ttmpv = *:8 tmp_ldXn;\n\tRt_VPR128[0,64] = tmpv;\n\tRt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtt_VPR128[0,64] = tmpv;\n\tRtt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRttt_VPR128[0,64] = tmpv;\n\tRttt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\ttmpv = *:8 tmp_ldXn;\n\tRtttt_VPR128[0,64] = tmpv;\n\tRtttt_VPR128[64,64] = tmpv;\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\", vVtttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\", vVtttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\", vVtttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".1D\", vVtt^\".1D\", vVttt^\".1D\", vVtttt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\", vVtttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\", vVtttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\", vVtttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\", vVtttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c006400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c006c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".1D\", vVtt^\".1D\", vVttt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c006400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c006c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c007400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c007c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.1D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.16B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c007400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c007c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8B\", vVtt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4H\", vVtt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c00a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2S\", vVtt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x0c00ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.1D, Vt2.1D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".1D\", vVtt^\".1D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR64[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".16B\", vVtt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".8H\", vVtt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c00a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".4S\", vVtt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000\n# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000\n# CONSTRUCT x4c00ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]\n\n:st1 {vVt^\".2D\", vVtt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[0], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[1], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[2], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[3], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d001000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[4], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d001400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[5], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d001800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[6], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d001c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[7], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[8], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[9], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[10], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[11], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d001000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[12], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d001400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[13], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d001800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[14], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d001c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.B}[15], [Xn|SP] [, wback]\n\n:st1 {vVt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[0], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[1], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d005000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[2], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d005800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[3], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[4], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[5], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d005000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[6], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d005800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.H}[7], [Xn|SP] [, wback]\n\n:st1 {vVt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.S}[0], [Xn|SP] [, wback]\n\n:st1 {vVt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d009000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.S}[1], [Xn|SP] [, wback]\n\n:st1 {vVt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.S}[2], [Xn|SP] [, wback]\n\n:st1 {vVt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d009000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.S}[3], [Xn|SP] [, wback]\n\n:st1 {vVt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x0d008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.D}[0], [Xn|SP] [, wback]\n\n:st1 {vVt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000\n# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000\n# CONSTRUCT x4d008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st1 {Vt.D}[1], [Xn|SP] [, wback]\n\n:st1 {vVt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x0c008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".8B\", vVtt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x0c008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".4H\", vVtt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x0c008800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".2S\", vVtt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x4c008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".16B\", vVtt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x4c008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".8H\", vVtt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x4c008800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".4S\", vVtt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000\n# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000\n# CONSTRUCT x4c008c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]\n\n:st2 {vVt^\".2D\", vVtt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d200000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[0], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d200400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[1], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d200800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[2], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d200c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[3], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d201000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[4], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d201400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[5], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d201800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[6], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d201c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[7], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d200000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[8], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d200400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[9], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d200800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[10], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d200c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[11], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d201000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[12], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d201400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[13], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d201800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[14], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d201c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.B, Vt2.B}[15], [Xn|SP] [, wback]\n\n:st2 {vVt^\".B\", vVtt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d204000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[0], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d204800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[1], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d205000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[2], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d205800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[3], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d204000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[4], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d204800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[5], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d205000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[6], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d205800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.H, Vt2.H}[7], [Xn|SP] [, wback]\n\n:st2 {vVt^\".H\", vVtt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d208000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.S, Vt2.S}[0], [Xn|SP] [, wback]\n\n:st2 {vVt^\".S\", vVtt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d209000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.S, Vt2.S}[1], [Xn|SP] [, wback]\n\n:st2 {vVt^\".S\", vVtt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d208000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.S, Vt2.S}[2], [Xn|SP] [, wback]\n\n:st2 {vVt^\".S\", vVtt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d209000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.S, Vt2.S}[3], [Xn|SP] [, wback]\n\n:st2 {vVt^\".S\", vVtt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x0d208400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.D, Vt2.D}[0], [Xn|SP] [, wback]\n\n:st2 {vVt^\".D\", vVtt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000\n# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000\n# CONSTRUCT x4d208400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st2 {Vt.D, Vt2.D}[1], [Xn|SP] [, wback]\n\n:st2 {vVt^\".D\", vVtt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x0c004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x0c004400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x0c004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x4c004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x4c004400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x4c004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000\n# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000\n# CONSTRUCT x4c004c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]\n\n:st3 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[0], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[1], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[2], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[3], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d003000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[4], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d003400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[5], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d003800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[6], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d003c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[7], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[8], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[9], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[10], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[11], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d003000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[12], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d003400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[13], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d003800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[14], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d003c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.B, Vt2.B, Vt3.B}[15], [Xn|SP] [, wback]\n\n:st3 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[0], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[1], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[2], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[3], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[4], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[5], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[6], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.H, Vt2.H, Vt3.H}[7], [Xn|SP] [, wback]\n\n:st3 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.S, Vt2.S, Vt3.S}[0], [Xn|SP] [, wback]\n\n:st3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d00b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.S, Vt2.S, Vt3.S}[1], [Xn|SP] [, wback]\n\n:st3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.S, Vt2.S, Vt3.S}[2], [Xn|SP] [, wback]\n\n:st3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d00b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.S, Vt2.S, Vt3.S}[3], [Xn|SP] [, wback]\n\n:st3 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x0d00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.D, Vt2.D, Vt3.D}[0], [Xn|SP] [, wback]\n\n:st3 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000\n# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000\n# CONSTRUCT x4d00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st3 {Vt.D, Vt2.D, Vt3.D}[1], [Xn|SP] [, wback]\n\n:st3 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x0c000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".8B\", vVtt^\".8B\", vVttt^\".8B\", vVtttt^\".8B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR64[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x0c000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".4H\", vVtt^\".4H\", vVttt^\".4H\", vVtttt^\".4H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR64[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x0c000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".2S\", vVtt^\".2S\", vVttt^\".2S\", vVtttt^\".2S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR64[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR64[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x4c000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".16B\", vVtt^\".16B\", vVttt^\".16B\", vVtttt^\".16B\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x4c000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".8H\", vVtt^\".8H\", vVttt^\".8H\", vVtttt^\".8H\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x4c000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".4S\", vVtt^\".4S\", vVttt^\".4S\", vVtttt^\".4S\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000\n# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000\n# CONSTRUCT x4c000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]\n\n:st4 {vVt^\".2D\", vVtt^\".2D\", vVttt^\".2D\", vVtttt^\".2D\"}, [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d202000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[0], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[0,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d202400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[1], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[8,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d202800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[2], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[16,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d202c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[3], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[24,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d203000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[4], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[32,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d203400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[5], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[40,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d203800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[6], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[48,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d203c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[7], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[56,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d202000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[8], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[8], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[64,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d202400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[9], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[9], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[72,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d202800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[10], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[10], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[80,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d202c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[11], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[11], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[88,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d203000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[12], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[12], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[96,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d203400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[13], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[13], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[104,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d203800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[14], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[14], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[112,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d203c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[15], [Xn|SP] [, wback]\n\n:st4 {vVt^\".B\", vVtt^\".B\", vVttt^\".B\", vVtttt^\".B\"}[15], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:1 tmp_ldXn = Rt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t*:1 tmp_ldXn = Rtttt_VPR128[120,8];\n\ttmp_ldXn = tmp_ldXn + 1;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d206000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[0], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[0,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d206800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[1], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[16,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d207000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[2], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[32,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d207800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[3], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[48,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d206000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[4], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[4], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[64,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d206800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[5], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[5], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[80,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d207000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[6], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[6], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[96,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d207800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[7], [Xn|SP] [, wback]\n\n:st4 {vVt^\".H\", vVtt^\".H\", vVttt^\".H\", vVtttt^\".H\"}[7], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:2 tmp_ldXn = Rt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t*:2 tmp_ldXn = Rtttt_VPR128[112,16];\n\ttmp_ldXn = tmp_ldXn + 2;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d20a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[0], [Xn|SP] [, wback]\n\n:st4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[0,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d20b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[1], [Xn|SP] [, wback]\n\n:st4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[32,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d20a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[2], [Xn|SP] [, wback]\n\n:st4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[2], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[64,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d20b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[3], [Xn|SP] [, wback]\n\n:st4 {vVt^\".S\", vVtt^\".S\", vVttt^\".S\", vVtttt^\".S\"}[3], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:4 tmp_ldXn = Rt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t*:4 tmp_ldXn = Rtttt_VPR128[96,32];\n\ttmp_ldXn = tmp_ldXn + 4;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x0d20a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[0], [Xn|SP] [, wback]\n\n:st4 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\", vVtttt^\".D\"}[0], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR128[0,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000\n# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000\n# CONSTRUCT x4d20a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES\n# st4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[1], [Xn|SP] [, wback]\n\n:st4 {vVt^\".D\", vVtt^\".D\", vVttt^\".D\", vVtttt^\".D\"}[1], [Rn_GPR64xsp]^ldst_wback\nis b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64\n{\n\ttmp_ldXn = Rn_GPR64xsp;\n\t*:8 tmp_ldXn = Rt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t*:8 tmp_ldXn = Rtttt_VPR128[64,64];\n\ttmp_ldXn = tmp_ldXn + 8;\n\t# neglected zexts\n\tbuild ldst_wback;\n}\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc", "content": "# C7.2.1 ABS page C7-1009 line 58362 KEEPWITH\n#\n# The semantics in this file are auto-generated with armit.py script\n# in the andre directory (capture output and replace file):\n#\n# python ../../../ProcessorTest/test/andre/scrape/armit.py --arch a64 --sort --refurb --smacro primitive --sinc languages/AARCH64neon.sinc\n#\n# The AUNIT tests are run using the command line options from the\n# comment with the python script aunit.py in the cunit directory:\n#\n# (cd ../../../ProcessorTest/test/cunit; python aunit.py OPTIONS)\n#\n# (aunit.py may require a local copy of a current andre exhaust).\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x5e20b800/mask=xff3ffc00\n# CONSTRUCT x5ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =abs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1\n# AUNIT --inst x5ee0b800/mask=xfffffc00 --status pass\n# ABS Scalar\n\n:abs Rd_FPR64, Rn_FPR64\nis b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal test = Rn_FPR64 s< 0;\n\tRd_FPR64 = (zext(!test)*Rn_FPR64) + (zext(test)*(-Rn_FPR64));\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x0e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1\n# AUNIT --inst x0e20b800/mask=xfffffc00 --status pass\n# ABS Vector 8B when size = 00 , Q = 0\n\n:abs Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1\n\tRd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]);\n\tRd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]);\n\tRd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]);\n\tRd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]);\n\tRd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]);\n\tRd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]);\n\tRd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]);\n\tRd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x4e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1\n# AUNIT --inst x4e20b800/mask=xfffffc00 --status pass\n# ABS Vector SIMD 16B when size = 00 , Q = 1\n\n:abs Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1\n\tRd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]);\n\tRd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]);\n\tRd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]);\n\tRd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]);\n\tRd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]);\n\tRd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]);\n\tRd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]);\n\tRd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]);\n\tRd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]);\n\tRd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]);\n\tRd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]);\n\tRd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]);\n\tRd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]);\n\tRd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]);\n\tRd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]);\n\tRd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x0e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2\n# AUNIT --inst x0e60b800/mask=xfffffc00 --status pass\n# ABS Vector SIMD 4H when size = 01 , Q = 0\n\n:abs Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x4e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2\n# AUNIT --inst x4e60b800/mask=xfffffc00 --status pass\n# ABS Vector SIMD 8H when size = 01 , Q = 1\n\n:abs Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x0ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4\n# AUNIT --inst x0ea0b800/mask=xfffffc00 --status pass\n# ABS Vector SIMD 2S when size = 10 , Q = 0\n\n:abs Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x4ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4\n# AUNIT --inst x4ea0b800/mask=xfffffc00 --status pass\n# ABS Vector SIMD 4S when size = 10 , Q = 1\n\n:abs Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00\n# CONSTRUCT x4ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@8\n# AUNIT --inst x4ee0b800/mask=xfffffc00 --status pass\n# ABS Vector SIMD 2D when size = 11 , Q = 1\n\n:abs Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x5e208400/mask=xff20fc00\n# CONSTRUCT x5ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2\n# AUNIT --inst x5ee08400/mask=xffe0fc00 --status pass\n\n:add Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64 + Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x4e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1\n# AUNIT --inst x4e208400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B + Rm_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] + Rm_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] + Rm_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] + Rm_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] + Rm_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] + Rm_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] + Rm_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] + Rm_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] + Rm_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] + Rm_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] + Rm_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] + Rm_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] + Rm_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] + Rm_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] + Rm_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] + Rm_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] + Rm_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x4e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2\n# AUNIT --inst x4e608400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x4ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4\n# AUNIT --inst x4ea08400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x4ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@8\n# AUNIT --inst x4ee08400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x0e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1\n# AUNIT --inst x0e208400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B + Rm_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] + Rm_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] + Rm_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] + Rm_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] + Rm_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] + Rm_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] + Rm_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] + Rm_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] + Rm_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x0e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2\n# AUNIT --inst x0e608400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H + Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] + Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] + Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] + Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] + Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00\n# CONSTRUCT x0ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4\n# AUNIT --inst x0ea08400/mask=xffe0fc00 --status pass\n\n:add Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S + Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] + Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] + Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00\n# CONSTRUCT x0ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-0@3-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@8\n# AUNIT --inst x0ea04000/mask=xffe0fc00 --status pass\n\n:addhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];\n\t# simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4\n\tRd_VPR64.2S[0,32] = TMPQ1[32,32];\n\tRd_VPR64.2S[32,32] = TMPQ1[96,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00\n# CONSTRUCT x0e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-0@3-1@5-2@7-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@4\n# AUNIT --inst x0e604000/mask=xffe0fc00 --status pass\n\n:addhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];\n\t# simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2\n\tRd_VPR64.4H[0,16] = TMPQ1[16,16];\n\tRd_VPR64.4H[16,16] = TMPQ1[48,16];\n\tRd_VPR64.4H[32,16] = TMPQ1[80,16];\n\tRd_VPR64.4H[48,16] = TMPQ1[112,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00\n# CONSTRUCT x0e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@2\n# AUNIT --inst x0e204000/mask=xffe0fc00 --status pass\n\n:addhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Rd_VPR128 & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];\n\t# simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1\n\tRd_VPR64.8B[0,8] = TMPQ1[8,8];\n\tRd_VPR64.8B[8,8] = TMPQ1[24,8];\n\tRd_VPR64.8B[16,8] = TMPQ1[40,8];\n\tRd_VPR64.8B[24,8] = TMPQ1[56,8];\n\tRd_VPR64.8B[32,8] = TMPQ1[72,8];\n\tRd_VPR64.8B[40,8] = TMPQ1[88,8];\n\tRd_VPR64.8B[48,8] = TMPQ1[104,8];\n\tRd_VPR64.8B[56,8] = TMPQ1[120,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00\n# CONSTRUCT x4e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@2\n# AUNIT --inst x4e204000/mask=xffe0fc00 --status pass\n\n:addhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Rd_VPR128 & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1\n\tRd_VPR128.16B[64,8] = TMPQ1[8,8];\n\tRd_VPR128.16B[72,8] = TMPQ1[24,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[40,8];\n\tRd_VPR128.16B[88,8] = TMPQ1[56,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[72,8];\n\tRd_VPR128.16B[104,8] = TMPQ1[88,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[104,8];\n\tRd_VPR128.16B[120,8] = TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00\n# CONSTRUCT x4ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-2@3-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@8\n# AUNIT --inst x4ea04000/mask=xffe0fc00 --status pass\n\n:addhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Rd_VPR128 & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4\n\tRd_VPR128.4S[64,32] = TMPQ1[32,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00\n# CONSTRUCT x4e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-4@3-5@5-6@7-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@4\n# AUNIT --inst x4e604000/mask=xffe0fc00 --status pass\n\n:addhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Rd_VPR128 & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2\n\tRd_VPR128.8H[64,16] = TMPQ1[16,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[48,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[80,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.4 ADDP (scalar) page C7-2023 line 118265 MATCH x5e31b800/mask=xff3ffc00\n# CONSTRUCT x5ef1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =#+\n# SMACRO(pseudo) ARG1 ARG2 =NEON_addp/1@8\n# AUNIT --inst x5ef1b800/mask=xfffffc00 --status pass\n\n:addp Rd_FPR64, Rn_VPR128.2D\nis b_3031=1 & u=0 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0x1b & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd\n{\n\t# sipd infix Rd_FPR64 = +(Rn_VPR128.2D) on pairs lane size (8 to 8)\n\tlocal tmp1 = Rn_VPR128.2D[0,64];\n\tlocal tmp2 = Rn_VPR128.2D[64,64];\n\tRd_FPR64 = tmp1 + tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x4e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1\n# AUNIT --inst x4e20bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x17 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.16B,Rm_VPR128.16B) on pairs lane size (1 to 1)\n\tlocal tmp2 = Rn_VPR128.16B[0,8];\n\tlocal tmp3 = Rn_VPR128.16B[8,8];\n\tTMPQ1[0,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[16,8];\n\ttmp3 = Rn_VPR128.16B[24,8];\n\tTMPQ1[8,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[32,8];\n\ttmp3 = Rn_VPR128.16B[40,8];\n\tTMPQ1[16,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[48,8];\n\ttmp3 = Rn_VPR128.16B[56,8];\n\tTMPQ1[24,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[64,8];\n\ttmp3 = Rn_VPR128.16B[72,8];\n\tTMPQ1[32,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[80,8];\n\ttmp3 = Rn_VPR128.16B[88,8];\n\tTMPQ1[40,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[96,8];\n\ttmp3 = Rn_VPR128.16B[104,8];\n\tTMPQ1[48,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.16B[112,8];\n\ttmp3 = Rn_VPR128.16B[120,8];\n\tTMPQ1[56,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[0,8];\n\ttmp3 = Rm_VPR128.16B[8,8];\n\tTMPQ1[64,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[16,8];\n\ttmp3 = Rm_VPR128.16B[24,8];\n\tTMPQ1[72,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[32,8];\n\ttmp3 = Rm_VPR128.16B[40,8];\n\tTMPQ1[80,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[48,8];\n\ttmp3 = Rm_VPR128.16B[56,8];\n\tTMPQ1[88,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[64,8];\n\ttmp3 = Rm_VPR128.16B[72,8];\n\tTMPQ1[96,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[80,8];\n\ttmp3 = Rm_VPR128.16B[88,8];\n\tTMPQ1[104,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[96,8];\n\ttmp3 = Rm_VPR128.16B[104,8];\n\tTMPQ1[112,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.16B[112,8];\n\ttmp3 = Rm_VPR128.16B[120,8];\n\tTMPQ1[120,8] = tmp2 + tmp3;\n\tRd_VPR128.16B = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x4ee0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@8\n# AUNIT --inst x4ee0bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x17 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8)\n\tlocal tmp2 = Rn_VPR128.2D[0,64];\n\tlocal tmp3 = Rn_VPR128.2D[64,64];\n\tTMPQ1[0,64] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.2D[0,64];\n\ttmp3 = Rm_VPR128.2D[64,64];\n\tTMPQ1[64,64] = tmp2 + tmp3;\n\tRd_VPR128.2D = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x0ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4\n# AUNIT --inst x0ea0bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x17 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4)\n\tlocal tmp2 = Rn_VPR64.2S[0,32];\n\tlocal tmp3 = Rn_VPR64.2S[32,32];\n\tTMPD1[0,32] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.2S[0,32];\n\ttmp3 = Rm_VPR64.2S[32,32];\n\tTMPD1[32,32] = tmp2 + tmp3;\n\tRd_VPR64.2S = TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x0e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2\n# AUNIT --inst x0e60bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x17 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.4H,Rm_VPR64.4H) on pairs lane size (2 to 2)\n\tlocal tmp2 = Rn_VPR64.4H[0,16];\n\tlocal tmp3 = Rn_VPR64.4H[16,16];\n\tTMPD1[0,16] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR64.4H[32,16];\n\ttmp3 = Rn_VPR64.4H[48,16];\n\tTMPD1[16,16] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.4H[0,16];\n\ttmp3 = Rm_VPR64.4H[16,16];\n\tTMPD1[32,16] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.4H[32,16];\n\ttmp3 = Rm_VPR64.4H[48,16];\n\tTMPD1[48,16] = tmp2 + tmp3;\n\tRd_VPR64.4H = TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x4ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4\n# AUNIT --inst x4ea0bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x17 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4)\n\tlocal tmp2 = Rn_VPR128.4S[0,32];\n\tlocal tmp3 = Rn_VPR128.4S[32,32];\n\tTMPQ1[0,32] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.4S[64,32];\n\ttmp3 = Rn_VPR128.4S[96,32];\n\tTMPQ1[32,32] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.4S[0,32];\n\ttmp3 = Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.4S[64,32];\n\ttmp3 = Rm_VPR128.4S[96,32];\n\tTMPQ1[96,32] = tmp2 + tmp3;\n\tRd_VPR128.4S = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x0e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1\n# AUNIT --inst x0e20bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x17 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.8B,Rm_VPR64.8B) on pairs lane size (1 to 1)\n\tlocal tmp2 = Rn_VPR64.8B[0,8];\n\tlocal tmp3 = Rn_VPR64.8B[8,8];\n\tTMPD1[0,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR64.8B[16,8];\n\ttmp3 = Rn_VPR64.8B[24,8];\n\tTMPD1[8,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR64.8B[32,8];\n\ttmp3 = Rn_VPR64.8B[40,8];\n\tTMPD1[16,8] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR64.8B[48,8];\n\ttmp3 = Rn_VPR64.8B[56,8];\n\tTMPD1[24,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.8B[0,8];\n\ttmp3 = Rm_VPR64.8B[8,8];\n\tTMPD1[32,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.8B[16,8];\n\ttmp3 = Rm_VPR64.8B[24,8];\n\tTMPD1[40,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.8B[32,8];\n\ttmp3 = Rm_VPR64.8B[40,8];\n\tTMPD1[48,8] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR64.8B[48,8];\n\ttmp3 = Rm_VPR64.8B[56,8];\n\tTMPD1[56,8] = tmp2 + tmp3;\n\tRd_VPR64.8B = TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00\n# CONSTRUCT x4e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2\n# AUNIT --inst x4e60bc00/mask=xffe0fc00 --status pass\n\n:addp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x17 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2)\n\tlocal tmp2 = Rn_VPR128.8H[0,16];\n\tlocal tmp3 = Rn_VPR128.8H[16,16];\n\tTMPQ1[0,16] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.8H[32,16];\n\ttmp3 = Rn_VPR128.8H[48,16];\n\tTMPQ1[16,16] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.8H[64,16];\n\ttmp3 = Rn_VPR128.8H[80,16];\n\tTMPQ1[32,16] = tmp2 + tmp3;\n\ttmp2 = Rn_VPR128.8H[96,16];\n\ttmp3 = Rn_VPR128.8H[112,16];\n\tTMPQ1[48,16] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.8H[0,16];\n\ttmp3 = Rm_VPR128.8H[16,16];\n\tTMPQ1[64,16] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.8H[32,16];\n\ttmp3 = Rm_VPR128.8H[48,16];\n\tTMPQ1[80,16] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.8H[64,16];\n\ttmp3 = Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = tmp2 + tmp3;\n\ttmp2 = Rm_VPR128.8H[96,16];\n\ttmp3 = Rm_VPR128.8H[112,16];\n\tTMPQ1[112,16] = tmp2 + tmp3;\n\tRd_VPR128.8H = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00\n# CONSTRUCT x4e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1\n# AUNIT --inst x4e31b800/mask=xfffffc00 --status nopcodeop\n\n:addv Rd_FPR8, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = Rn_VPR128.16B[0,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[8,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[16,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[24,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[32,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[40,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[48,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[56,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[64,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[72,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[80,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[88,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[96,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[104,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[112,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 31 bytes of Zd\n}\n\n# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00\n# CONSTRUCT x0e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1\n# AUNIT --inst x0e31b800/mask=xfffffc00 --status nopcodeop\n\n:addv Rd_FPR8, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = Rn_VPR64.8B[0,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[8,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[16,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[24,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[32,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[40,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[48,8];\n\tRd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[56,8];\n\tzext_zq(Zd); # zero upper 31 bytes of Zd\n}\n\n# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00\n# CONSTRUCT x0e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2\n# AUNIT --inst x0e71b800/mask=xfffffc00 --status nopcodeop\n\n:addv Rd_FPR16, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_VPR64.4H[0,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR64.4H[16,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR64.4H[32,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR64.4H[48,16];\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00\n# CONSTRUCT x4e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2\n# AUNIT --inst x4e71b800/mask=xfffffc00 --status nopcodeop\n\n:addv Rd_FPR16, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_VPR128.8H[0,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[16,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[32,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[48,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[64,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[80,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[96,16];\n\tRd_FPR16 = Rd_FPR16 + Rn_VPR128.8H[112,16];\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00\n# CONSTRUCT x4eb1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2[0]:4 ARG2[1]:4 + ARG2[2]:4 ARG2[3]:4 + =+\n# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@4\n# AUNIT --inst x4eb1b800/mask=xfffffc00 --status pass\n\n:addv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tlocal tmp1:4 = Rn_VPR128.4S[0,32];\n\tlocal tmp2:4 = Rn_VPR128.4S[32,32];\n\tlocal tmp3:4 = tmp1 + tmp2;\n\tlocal tmp4:4 = Rn_VPR128.4S[64,32];\n\tlocal tmp5:4 = Rn_VPR128.4S[96,32];\n\tlocal tmp6:4 = tmp4 + tmp5;\n\tRd_FPR32 = tmp3 + tmp6;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.7 AESD page C7-2029 line 118544 MATCH x4e285800/mask=xfffffc00\n# CONSTRUCT x4e285800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesd/2\n# AUNIT --inst x4e285800/mask=xfffffc00 --status noqemu\n\n:aesd Rd_VPR128.16B, Rn_VPR128.16B\nis b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_aesd(Rd_VPR128.16B, Rn_VPR128.16B);\n}\n\n# C7.2.8 AESE page C7-2030 line 118606 MATCH x4e284800/mask=xfffffc00\n# CONSTRUCT x4e284800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_aese/2\n# AUNIT --inst x4e284800/mask=xfffffc00 --status noqemu\n\n:aese Rd_VPR128.16B, Rn_VPR128.16B\nis b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=4 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_aese(Rd_VPR128.16B, Rn_VPR128.16B);\n}\n\n# C7.2.9 AESIMC page C7-2031 line 118669 MATCH x4e287800/mask=xfffffc00\n# CONSTRUCT x4e287800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesimc/2\n# AUNIT --inst x4e287800/mask=xfffffc00 --status noqemu\n\n:aesimc Rd_VPR128.16B, Rn_VPR128.16B\nis b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd\n{\n\tRd_VPR128.16B = NEON_aesimc(Rd_VPR128.16B, Rn_VPR128.16B);\n}\n\n# C7.2.10 AESMC page C7-2032 line 118729 MATCH x4e286800/mask=xfffffc00\n# CONSTRUCT x4e286800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesmc/2\n# AUNIT --inst x4e286800/mask=xfffffc00 --status noqemu\n\n:aesmc Rd_VPR128.16B, Rn_VPR128.16B\nis b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd\n{\n\tRd_VPR128.16B = NEON_aesmc(Rd_VPR128.16B, Rn_VPR128.16B);\n}\n\n# C7.2.11 AND (vector) page C7-2033 line 118789 MATCH x0e201c00/mask=xbfe0fc00\n# CONSTRUCT x4e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$&@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1\n# AUNIT --inst x4e201c00/mask=xffe0fc00 --status pass\n\n:and Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B & Rm_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & Rm_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & Rm_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & Rm_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & Rm_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & Rm_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & Rm_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & Rm_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & Rm_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & Rm_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & Rm_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & Rm_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & Rm_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & Rm_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & Rm_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & Rm_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & Rm_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.11 AND (vector) page C7-2033 line 118789 MATCH x0e201c00/mask=xbfe0fc00\n# CONSTRUCT x0e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =&\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1\n# AUNIT --inst x0e201c00/mask=xffe0fc00 --status pass\n\n:and Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = Rn_VPR64.8B & Rm_VPR64.8B;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.12 BCAX page C7-2035 line 118871 MATCH xce200000/mask=xffe08000\n# CONSTRUCT xce200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 ARG4 $~@1 $&@1 =$|@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG3 =NEON_bcax/3@1\n# AUNIT --inst xce200000/mask=xffe08000 --status noqemu\n\n:bcax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B\nis b_2131=0b11001110001 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd\n{\n\t# simd unary TMPQ1 = ~(Ra_VPR128.16B) on lane size 1\n\tTMPQ1[0,8] = ~(Ra_VPR128.16B[0,8]);\n\tTMPQ1[8,8] = ~(Ra_VPR128.16B[8,8]);\n\tTMPQ1[16,8] = ~(Ra_VPR128.16B[16,8]);\n\tTMPQ1[24,8] = ~(Ra_VPR128.16B[24,8]);\n\tTMPQ1[32,8] = ~(Ra_VPR128.16B[32,8]);\n\tTMPQ1[40,8] = ~(Ra_VPR128.16B[40,8]);\n\tTMPQ1[48,8] = ~(Ra_VPR128.16B[48,8]);\n\tTMPQ1[56,8] = ~(Ra_VPR128.16B[56,8]);\n\tTMPQ1[64,8] = ~(Ra_VPR128.16B[64,8]);\n\tTMPQ1[72,8] = ~(Ra_VPR128.16B[72,8]);\n\tTMPQ1[80,8] = ~(Ra_VPR128.16B[80,8]);\n\tTMPQ1[88,8] = ~(Ra_VPR128.16B[88,8]);\n\tTMPQ1[96,8] = ~(Ra_VPR128.16B[96,8]);\n\tTMPQ1[104,8] = ~(Ra_VPR128.16B[104,8]);\n\tTMPQ1[112,8] = ~(Ra_VPR128.16B[112,8]);\n\tTMPQ1[120,8] = ~(Ra_VPR128.16B[120,8]);\n\t# simd infix TMPQ2 = Rm_VPR128.16B & TMPQ1 on lane size 1\n\tTMPQ2[0,8] = Rm_VPR128.16B[0,8] & TMPQ1[0,8];\n\tTMPQ2[8,8] = Rm_VPR128.16B[8,8] & TMPQ1[8,8];\n\tTMPQ2[16,8] = Rm_VPR128.16B[16,8] & TMPQ1[16,8];\n\tTMPQ2[24,8] = Rm_VPR128.16B[24,8] & TMPQ1[24,8];\n\tTMPQ2[32,8] = Rm_VPR128.16B[32,8] & TMPQ1[32,8];\n\tTMPQ2[40,8] = Rm_VPR128.16B[40,8] & TMPQ1[40,8];\n\tTMPQ2[48,8] = Rm_VPR128.16B[48,8] & TMPQ1[48,8];\n\tTMPQ2[56,8] = Rm_VPR128.16B[56,8] & TMPQ1[56,8];\n\tTMPQ2[64,8] = Rm_VPR128.16B[64,8] & TMPQ1[64,8];\n\tTMPQ2[72,8] = Rm_VPR128.16B[72,8] & TMPQ1[72,8];\n\tTMPQ2[80,8] = Rm_VPR128.16B[80,8] & TMPQ1[80,8];\n\tTMPQ2[88,8] = Rm_VPR128.16B[88,8] & TMPQ1[88,8];\n\tTMPQ2[96,8] = Rm_VPR128.16B[96,8] & TMPQ1[96,8];\n\tTMPQ2[104,8] = Rm_VPR128.16B[104,8] & TMPQ1[104,8];\n\tTMPQ2[112,8] = Rm_VPR128.16B[112,8] & TMPQ1[112,8];\n\tTMPQ2[120,8] = Rm_VPR128.16B[120,8] & TMPQ1[120,8];\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ2 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ2[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ2[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ2[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ2[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ2[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ2[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ2[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ2[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ2[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ2[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ2[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ2[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ2[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ2[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ2[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ2[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x2f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$&\n# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4\n# AUNIT --inst x2f001400/mask=xfff89c00 --status pass\n\n:bic Rd_VPR64.2S, abcdefgh\nis b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = ~ Imm_neon_uimm8Shift:4;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S & tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] & tmp1;\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] & tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x2f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$&\n# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2\n# AUNIT --inst x2f009400/mask=xfff8dc00 --status pass\n\n:bic Rd_VPR64.4H, abcdefgh\nis b_3131=0 & q=0 & b_29=1 & b_2428=0xf & abcdefgh & b_1923=0x0 & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.4H & Zd\n{\n\tlocal tmp1:2 = ~ Imm_neon_uimm8Shift:2;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H & tmp1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] & tmp1;\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] & tmp1;\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] & tmp1;\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] & tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x6f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$&\n# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4\n# AUNIT --inst x6f001400/mask=xfff89c00 --status pass\n\n:bic Rd_VPR128.4S, abcdefgh\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = ~ Imm_neon_uimm8Shift:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S & tmp1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] & tmp1;\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] & tmp1;\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] & tmp1;\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] & tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x6f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$&\n# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2\n# AUNIT --inst x6f009400/mask=xfff8dc00 --status pass\n\n:bic Rd_VPR128.8H, abcdefgh\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & abcdefgh & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.8H & Zd\n{\n\tlocal tmp1:2 = ~ Imm_neon_uimm8Shift:2;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H & tmp1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] & tmp1;\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] & tmp1;\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] & tmp1;\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] & tmp1;\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] & tmp1;\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] & tmp1;\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] & tmp1;\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] & tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.21 BIC (vector, register) page C7-2050 line 119707 MATCH x0e601c00/mask=xbfe0fc00\n# CONSTRUCT x4e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1\n# AUNIT --inst x4e601c00/mask=xffe0fc00 --status pass\n\n:bic Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1\n\tTMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]);\n\tTMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]);\n\tTMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]);\n\tTMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]);\n\tTMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]);\n\tTMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]);\n\tTMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]);\n\tTMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]);\n\tTMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]);\n\tTMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]);\n\tTMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]);\n\tTMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]);\n\tTMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]);\n\tTMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]);\n\tTMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]);\n\tTMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]);\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B & TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.21 BIC (vector, register) page C7-2050 line 119707 MATCH x0e601c00/mask=xbfe0fc00\n# CONSTRUCT x0e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1\n# AUNIT --inst x0e601c00/mask=xffe0fc00 --status pass\n\n:bic Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1\n\tTMPD1[0,8] = ~(Rm_VPR64.8B[0,8]);\n\tTMPD1[8,8] = ~(Rm_VPR64.8B[8,8]);\n\tTMPD1[16,8] = ~(Rm_VPR64.8B[16,8]);\n\tTMPD1[24,8] = ~(Rm_VPR64.8B[24,8]);\n\tTMPD1[32,8] = ~(Rm_VPR64.8B[32,8]);\n\tTMPD1[40,8] = ~(Rm_VPR64.8B[40,8]);\n\tTMPD1[48,8] = ~(Rm_VPR64.8B[48,8]);\n\tTMPD1[56,8] = ~(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B & TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] & TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] & TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] & TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] & TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] & TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] & TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] & TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] & TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.22 BIF page C7-2052 line 119791 MATCH x2ee01c00/mask=xbfe0fc00\n# CONSTRUCT x6ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1\n# AUNIT --inst x6ee01c00/mask=xffe0fc00 --status nopcodeop\n\n:bif Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = Rd_VPR128.16B ^ ((Rd_VPR128.16B ^ Rn_VPR128.16B) & ~Rm_VPR128.16B);\n}\n\n# C7.2.22 BIF page C7-2052 line 119791 MATCH x2ee01c00/mask=xbfe0fc00\n# CONSTRUCT x2ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1\n# AUNIT --inst x2ee01c00/mask=xffe0fc00 --status nopcodeop\n\n:bif Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = Rd_VPR64.8B ^ ((Rd_VPR64.8B ^ Rn_VPR64.8B) & ~Rm_VPR64.8B);\n}\n\n# C7.2.23 BIT page C7-2054 line 119875 MATCH x2ea01c00/mask=xbfe0fc00\n# CONSTRUCT x6ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1\n# AUNIT --inst x6ea01c00/mask=xffe0fc00 --status nopcodeop\n\n:bit Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = Rd_VPR128.16B ^ ((Rd_VPR128.16B ^ Rn_VPR128.16B) & Rm_VPR128.16B);\n}\n\n# C7.2.23 BIT page C7-2054 line 119875 MATCH x2ea01c00/mask=xbfe0fc00\n# CONSTRUCT x2ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1\n# AUNIT --inst x2ea01c00/mask=xffe0fc00 --status nopcodeop\n\n:bit Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = Rd_VPR64.8B ^ ((Rd_VPR64.8B ^ Rn_VPR64.8B) & Rm_VPR64.8B);\n}\n\n# C7.2.24 BSL page C7-2056 line 119959 MATCH x2e601c00/mask=xbfe0fc00\n# CONSTRUCT x6e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1\n# AUNIT --inst x6e601c00/mask=xffe0fc00 --status nopcodeop\n\n:bsl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = Rm_VPR128.16B ^ ((Rm_VPR128.16B ^ Rn_VPR128.16B) & Rd_VPR128.16B);\n}\n\n# C7.2.24 BSL page C7-2056 line 119959 MATCH x2e601c00/mask=xbfe0fc00\n# CONSTRUCT x2e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1\n# AUNIT --inst x2e601c00/mask=xffe0fc00 --status nopcodeop\n\n:bsl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = Rm_VPR64.8B ^ ((Rm_VPR64.8B ^ Rn_VPR64.8B) & Rd_VPR64.8B);\n}\n\n# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00\n# CONSTRUCT x0e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1\n# AUNIT --inst x0e204800/mask=xfffffc00 --status nopcodeop\n# CLS (vector) SIMD 8B when size = 00 , Q = 0\n\n:cls Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_cls(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00\n# CONSTRUCT x4e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1\n# AUNIT --inst x4e204800/mask=xfffffc00 --status nopcodeop\n# CLS (vector) SIMD 16B when size = 00 , Q = 1\n\n:cls Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_cls(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00\n# CONSTRUCT x0e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2\n# AUNIT --inst x0e604800/mask=xfffffc00 --status nopcodeop\n# CLS (vector) SIMD 4H when size = 01 , Q = 0\n\n:cls Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_cls(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00\n# CONSTRUCT x4e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2\n# AUNIT --inst x4e604800/mask=xfffffc00 --status nopcodeop\n# CLS (vector) SIMD 8H when size = 01 , Q = 1\n\n:cls Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_cls(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00\n# CONSTRUCT x0ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4\n# AUNIT --inst x0ea04800/mask=xfffffc00 --status nopcodeop\n# CLS (vector) SIMD 2S when size = 10 , Q = 0\n\n:cls Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_cls(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00\n# CONSTRUCT x4ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4\n# AUNIT --inst x4ea04800/mask=xfffffc00 --status nopcodeop\n# CLS (vector) SIMD 4S when size = 10 , Q = 1\n\n:cls Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_cls(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00\n# CONSTRUCT x2e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1\n# AUNIT --inst x2e204800/mask=xfffffc00 --status nopcodeop\n# CLZ (vector) SIMD 8B when size = 00 , Q = 0\n\n:clz Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = lzcount(Rn_VPR64.8B) on lane size 1\n\tRd_VPR64.8B[0,8] = lzcount(Rn_VPR64.8B[0,8]);\n\tRd_VPR64.8B[8,8] = lzcount(Rn_VPR64.8B[8,8]);\n\tRd_VPR64.8B[16,8] = lzcount(Rn_VPR64.8B[16,8]);\n\tRd_VPR64.8B[24,8] = lzcount(Rn_VPR64.8B[24,8]);\n\tRd_VPR64.8B[32,8] = lzcount(Rn_VPR64.8B[32,8]);\n\tRd_VPR64.8B[40,8] = lzcount(Rn_VPR64.8B[40,8]);\n\tRd_VPR64.8B[48,8] = lzcount(Rn_VPR64.8B[48,8]);\n\tRd_VPR64.8B[56,8] = lzcount(Rn_VPR64.8B[56,8]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00\n# CONSTRUCT x6e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1\n# AUNIT --inst x6e204800/mask=xfffffc00 --status nopcodeop\n# CLZ (vector) SIMD 16B when size = 00 , Q = 1\n\n:clz Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = lzcount(Rn_VPR128.16B) on lane size 1\n\tRd_VPR128.16B[0,8] = lzcount(Rn_VPR128.16B[0,8]);\n\tRd_VPR128.16B[8,8] = lzcount(Rn_VPR128.16B[8,8]);\n\tRd_VPR128.16B[16,8] = lzcount(Rn_VPR128.16B[16,8]);\n\tRd_VPR128.16B[24,8] = lzcount(Rn_VPR128.16B[24,8]);\n\tRd_VPR128.16B[32,8] = lzcount(Rn_VPR128.16B[32,8]);\n\tRd_VPR128.16B[40,8] = lzcount(Rn_VPR128.16B[40,8]);\n\tRd_VPR128.16B[48,8] = lzcount(Rn_VPR128.16B[48,8]);\n\tRd_VPR128.16B[56,8] = lzcount(Rn_VPR128.16B[56,8]);\n\tRd_VPR128.16B[64,8] = lzcount(Rn_VPR128.16B[64,8]);\n\tRd_VPR128.16B[72,8] = lzcount(Rn_VPR128.16B[72,8]);\n\tRd_VPR128.16B[80,8] = lzcount(Rn_VPR128.16B[80,8]);\n\tRd_VPR128.16B[88,8] = lzcount(Rn_VPR128.16B[88,8]);\n\tRd_VPR128.16B[96,8] = lzcount(Rn_VPR128.16B[96,8]);\n\tRd_VPR128.16B[104,8] = lzcount(Rn_VPR128.16B[104,8]);\n\tRd_VPR128.16B[112,8] = lzcount(Rn_VPR128.16B[112,8]);\n\tRd_VPR128.16B[120,8] = lzcount(Rn_VPR128.16B[120,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00\n# CONSTRUCT x2e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2\n# AUNIT --inst x2e604800/mask=xfffffc00 --status nopcodeop\n# CLZ (vector) SIMD 4H when size = 01 , Q = 0\n\n:clz Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = lzcount(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = lzcount(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = lzcount(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = lzcount(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = lzcount(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00\n# CONSTRUCT x6e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2\n# AUNIT --inst x6e604800/mask=xfffffc00 --status nopcodeop\n# CLZ (vector) SIMD 8H when size = 01 , Q = 1\n\n:clz Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = lzcount(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = lzcount(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = lzcount(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = lzcount(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = lzcount(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = lzcount(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = lzcount(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = lzcount(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = lzcount(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00\n# CONSTRUCT x2ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4\n# AUNIT --inst x2ea04800/mask=xfffffc00 --status nopcodeop\n# CLZ (vector) SIMD 2S when size = 10 , Q = 0\n\n:clz Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = lzcount(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = lzcount(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = lzcount(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00\n# CONSTRUCT x6ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4\n# AUNIT --inst x6ea04800/mask=xfffffc00 --status nopcodeop\n# CLZ (vector) SIMD 4S when size = 10 , Q = 1\n\n:clz Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = lzcount(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = lzcount(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = lzcount(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = lzcount(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = lzcount(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x7e208c00/mask=xff20fc00\n# CONSTRUCT x7ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 dup dup dup ARG2 ARG3 equal:1 zext:8 0:8 ~ =*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2\n# AUNIT --inst x7ee08c00/mask=xffe0fc00 --status pass\n# CMEQ (register) Scalar\n\n:cmeq Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 == Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x2e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1\n# AUNIT --inst x2e208c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 8B when size = 00 , Q = 0\n\n:cmeq Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR64.8B & Rn_VPR64.8B & Rm_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] == Rm_VPR64.8B[0,8]) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] == Rm_VPR64.8B[8,8]) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] == Rm_VPR64.8B[16,8]) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] == Rm_VPR64.8B[24,8]) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] == Rm_VPR64.8B[32,8]) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] == Rm_VPR64.8B[40,8]) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] == Rm_VPR64.8B[48,8]) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] == Rm_VPR64.8B[56,8]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x6e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1\n# AUNIT --inst x6e208c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 16B when size = 00 , Q = 1\n\n:cmeq Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] == Rm_VPR128.16B[0,8]) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] == Rm_VPR128.16B[8,8]) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] == Rm_VPR128.16B[16,8]) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] == Rm_VPR128.16B[24,8]) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] == Rm_VPR128.16B[32,8]) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] == Rm_VPR128.16B[40,8]) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] == Rm_VPR128.16B[48,8]) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] == Rm_VPR128.16B[56,8]) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] == Rm_VPR128.16B[64,8]) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] == Rm_VPR128.16B[72,8]) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] == Rm_VPR128.16B[80,8]) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] == Rm_VPR128.16B[88,8]) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] == Rm_VPR128.16B[96,8]) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] == Rm_VPR128.16B[104,8]) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] == Rm_VPR128.16B[112,8]) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] == Rm_VPR128.16B[120,8]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x2e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2\n# AUNIT --inst x2e608c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 4H when size = 01 , Q = 0\n\n:cmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] == Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] == Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] == Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] == Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x6e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2\n# AUNIT --inst x6e608c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 8H when size = 01 , Q = 1\n\n:cmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] == Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] == Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] == Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] == Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] == Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] == Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] == Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] == Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x2ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4\n# AUNIT --inst x2ea08c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 2S when size = 10 , Q = 0\n\n:cmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] == Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] == Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x6ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4\n# AUNIT --inst x6ea08c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 4S when size = 10 , Q = 1\n\n:cmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] == Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] == Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] == Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] == Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00\n# CONSTRUCT x6ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@8\n# AUNIT --inst x6ee08c00/mask=xffe0fc00 --status nopcodeop\n# CMEQ (register) SIMD 2D when size = 11 , Q = 1\n\n:cmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] == Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] == Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x5e209800/mask=xff3ffc00\n# CONSTRUCT x5ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2\n# AUNIT --inst x5ee09800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_FPR64, Rn_FPR64, \"#0\"\nis b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 == 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x0e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1\n# AUNIT --inst x0e209800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR64.8B, Rn_VPR64.8B, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] == zero) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] == zero) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] == zero) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] == zero) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] == zero) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] == zero) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] == zero) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] == zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x4e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1\n# AUNIT --inst x4e209800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR128.16B, Rn_VPR128.16B, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] == zero) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] == zero) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] == zero) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] == zero) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] == zero) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] == zero) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] == zero) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] == zero) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] == zero) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] == zero) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] == zero) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] == zero) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] == zero) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] == zero) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] == zero) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] == zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x0e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2\n# AUNIT --inst x0e609800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR64.4H, Rn_VPR64.4H, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] == zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] == zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] == zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] == zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x4e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2\n# AUNIT --inst x4e609800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR128.8H, Rn_VPR128.8H, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] == zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] == zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] == zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] == zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] == zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] == zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] == zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] == zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x0ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@4\n# AUNIT --inst x0ea09800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR64.2S, Rn_VPR64.2S, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] == zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] == zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x4ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@2\n# AUNIT --inst x4ea09800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR128.4S, Rn_VPR128.4S, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] == zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] == zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] == zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] == zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00\n# CONSTRUCT x4ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmeq/2@8\n# AUNIT --inst x4ee09800/mask=xfffffc00 --status nopcodeop\n\n:cmeq Rd_VPR128.2D, Rn_VPR128.2D, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] == zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] == zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x5e203c00/mask=xff20fc00\n# CONSTRUCT x5ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2\n# AUNIT --inst x5ee03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 s>= Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x0e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1\n# AUNIT --inst x0e203c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] s>= Rm_VPR64.8B[0,8]) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] s>= Rm_VPR64.8B[8,8]) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] s>= Rm_VPR64.8B[16,8]) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] s>= Rm_VPR64.8B[24,8]) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] s>= Rm_VPR64.8B[32,8]) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] s>= Rm_VPR64.8B[40,8]) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] s>= Rm_VPR64.8B[48,8]) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] s>= Rm_VPR64.8B[56,8]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x4e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1\n# AUNIT --inst x4e203c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] s>= Rm_VPR128.16B[0,8]) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] s>= Rm_VPR128.16B[8,8]) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] s>= Rm_VPR128.16B[16,8]) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] s>= Rm_VPR128.16B[24,8]) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] s>= Rm_VPR128.16B[32,8]) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] s>= Rm_VPR128.16B[40,8]) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] s>= Rm_VPR128.16B[48,8]) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] s>= Rm_VPR128.16B[56,8]) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] s>= Rm_VPR128.16B[64,8]) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] s>= Rm_VPR128.16B[72,8]) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] s>= Rm_VPR128.16B[80,8]) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] s>= Rm_VPR128.16B[88,8]) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] s>= Rm_VPR128.16B[96,8]) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] s>= Rm_VPR128.16B[104,8]) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] s>= Rm_VPR128.16B[112,8]) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] s>= Rm_VPR128.16B[120,8]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x0e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2\n# AUNIT --inst x0e603c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] s>= Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] s>= Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] s>= Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] s>= Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x4e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2\n# AUNIT --inst x4e603c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] s>= Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] s>= Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] s>= Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] s>= Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] s>= Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] s>= Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] s>= Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] s>= Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x0ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4\n# AUNIT --inst x0ea03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] s>= Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] s>= Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x4ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4\n# AUNIT --inst x4ea03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] s>= Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] s>= Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] s>= Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] s>= Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00\n# CONSTRUCT x4ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@8\n# AUNIT --inst x4ee03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] s>= Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] s>= Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x7e208800/mask=xff3ffc00\n# CONSTRUCT x7ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2\n# AUNIT --inst x7ee08800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_FPR64, Rn_FPR64, \"#0\"\nis b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 s>= 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x2e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1\n# AUNIT --inst x2e208800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR64.8B, Rn_VPR64.8B, \"#0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] s>= zero) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] s>= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x6e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1\n# AUNIT --inst x6e208800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR128.16B, Rn_VPR128.16B, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] s>= zero) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] s>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x2e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2\n# AUNIT --inst x2e608800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR64.4H, Rn_VPR64.4H, \"#0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] s>= zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] s>= zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] s>= zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] s>= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x6e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2\n# AUNIT --inst x6e608800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR128.8H, Rn_VPR128.8H, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] s>= zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] s>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x2ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4\n# AUNIT --inst x2ea08800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR64.2S, Rn_VPR64.2S, \"#0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] s>= zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] s>= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x6ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4\n# AUNIT --inst x6ea08800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR128.4S, Rn_VPR128.4S, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] s>= zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] s>= zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] s>= zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] s>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00\n# CONSTRUCT x6ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmge/2@8\n# AUNIT --inst x6ee08800/mask=xfffffc00 --status nopcodeop\n\n:cmge Rd_VPR128.2D, Rn_VPR128.2D, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] s>= zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] s>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x5e203400/mask=xff20fc00\n# CONSTRUCT x5ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2\n# AUNIT --inst x5ee03400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 s> Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x0e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1\n# AUNIT --inst x0e203400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] s> Rm_VPR64.8B[0,8]) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] s> Rm_VPR64.8B[8,8]) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] s> Rm_VPR64.8B[16,8]) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] s> Rm_VPR64.8B[24,8]) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] s> Rm_VPR64.8B[32,8]) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] s> Rm_VPR64.8B[40,8]) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] s> Rm_VPR64.8B[48,8]) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] s> Rm_VPR64.8B[56,8]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x4e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1\n# AUNIT --inst x4e203400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] s> Rm_VPR128.16B[0,8]) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] s> Rm_VPR128.16B[8,8]) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] s> Rm_VPR128.16B[16,8]) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] s> Rm_VPR128.16B[24,8]) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] s> Rm_VPR128.16B[32,8]) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] s> Rm_VPR128.16B[40,8]) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] s> Rm_VPR128.16B[48,8]) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] s> Rm_VPR128.16B[56,8]) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] s> Rm_VPR128.16B[64,8]) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] s> Rm_VPR128.16B[72,8]) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] s> Rm_VPR128.16B[80,8]) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] s> Rm_VPR128.16B[88,8]) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] s> Rm_VPR128.16B[96,8]) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] s> Rm_VPR128.16B[104,8]) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] s> Rm_VPR128.16B[112,8]) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] s> Rm_VPR128.16B[120,8]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x0e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2\n# AUNIT --inst x0e603400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] s> Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] s> Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] s> Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] s> Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x4e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2\n# AUNIT --inst x4e603400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] s> Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] s> Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] s> Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] s> Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] s> Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] s> Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] s> Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] s> Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x0ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4\n# AUNIT --inst x0ea03400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] s> Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] s> Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x4ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4\n# AUNIT --inst x4ea03400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] s> Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] s> Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] s> Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] s> Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00\n# CONSTRUCT x4ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@8\n# AUNIT --inst x4ee03400/mask=xffe0fc00 --status nopcodeop\n\n:cmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] s> Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] s> Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x5e208800/mask=xff3ffc00\n# CONSTRUCT x5ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2\n# AUNIT --inst x5ee08800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_FPR64, Rn_FPR64, \"#0\"\nis b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 s> 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x0e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1\n# AUNIT --inst x0e208800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR64.8B, Rn_VPR64.8B, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] s> zero) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] s> zero) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] s> zero) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] s> zero) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] s> zero) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] s> zero) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] s> zero) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] s> zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x4e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1\n# AUNIT --inst x4e208800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR128.16B, Rn_VPR128.16B, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] s> zero) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] s> zero) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] s> zero) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] s> zero) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] s> zero) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] s> zero) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] s> zero) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] s> zero) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] s> zero) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] s> zero) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] s> zero) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] s> zero) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] s> zero) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] s> zero) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] s> zero) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] s> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x0e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2\n# AUNIT --inst x0e608800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR64.4H, Rn_VPR64.4H, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] s> zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] s> zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] s> zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] s> zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x4e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2\n# AUNIT --inst x4e608800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR128.8H, Rn_VPR128.8H, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] s> zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] s> zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] s> zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] s> zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] s> zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] s> zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] s> zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] s> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x0ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4\n# AUNIT --inst x0ea08800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR64.2S, Rn_VPR64.2S, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] s> zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] s> zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x4ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4\n# AUNIT --inst x4ea08800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR128.4S, Rn_VPR128.4S, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] s> zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] s> zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] s> zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] s> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00\n# CONSTRUCT x4ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2@8\n# AUNIT --inst x4ee08800/mask=xfffffc00 --status nopcodeop\n\n:cmgt Rd_VPR128.2D, Rn_VPR128.2D, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] s> zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] s> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x7e203400/mask=xff20fc00\n# CONSTRUCT x7ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2\n# AUNIT --inst x7ee03400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 > Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x2e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1\n# AUNIT --inst x2e203400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] > Rm_VPR64.8B[0,8]) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] > Rm_VPR64.8B[8,8]) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] > Rm_VPR64.8B[16,8]) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] > Rm_VPR64.8B[24,8]) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] > Rm_VPR64.8B[32,8]) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] > Rm_VPR64.8B[40,8]) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] > Rm_VPR64.8B[48,8]) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] > Rm_VPR64.8B[56,8]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x6e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1\n# AUNIT --inst x6e203400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] > Rm_VPR128.16B[0,8]) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] > Rm_VPR128.16B[8,8]) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] > Rm_VPR128.16B[16,8]) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] > Rm_VPR128.16B[24,8]) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] > Rm_VPR128.16B[32,8]) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] > Rm_VPR128.16B[40,8]) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] > Rm_VPR128.16B[48,8]) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] > Rm_VPR128.16B[56,8]) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] > Rm_VPR128.16B[64,8]) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] > Rm_VPR128.16B[72,8]) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] > Rm_VPR128.16B[80,8]) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] > Rm_VPR128.16B[88,8]) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] > Rm_VPR128.16B[96,8]) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] > Rm_VPR128.16B[104,8]) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] > Rm_VPR128.16B[112,8]) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] > Rm_VPR128.16B[120,8]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x2e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2\n# AUNIT --inst x2e603400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] > Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] > Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] > Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] > Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x6e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2\n# AUNIT --inst x6e603400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] > Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] > Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] > Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] > Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] > Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] > Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] > Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] > Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x2ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4\n# AUNIT --inst x2ea03400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] > Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] > Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x6ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4\n# AUNIT --inst x6ea03400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] > Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] > Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] > Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] > Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00\n# CONSTRUCT x6ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@8\n# AUNIT --inst x6ee03400/mask=xffe0fc00 --status nopcodeop\n\n:cmhi Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] > Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] > Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x7e203c00/mask=xff20fc00\n# CONSTRUCT x7ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2\n# AUNIT --inst x7ee03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 >= Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x2e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1\n# AUNIT --inst x2e203c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] >= Rm_VPR64.8B[0,8]) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] >= Rm_VPR64.8B[8,8]) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] >= Rm_VPR64.8B[16,8]) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] >= Rm_VPR64.8B[24,8]) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] >= Rm_VPR64.8B[32,8]) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] >= Rm_VPR64.8B[40,8]) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] >= Rm_VPR64.8B[48,8]) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] >= Rm_VPR64.8B[56,8]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x6e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1\n# AUNIT --inst x6e203c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] >= Rm_VPR128.16B[0,8]) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] >= Rm_VPR128.16B[8,8]) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] >= Rm_VPR128.16B[16,8]) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] >= Rm_VPR128.16B[24,8]) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] >= Rm_VPR128.16B[32,8]) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] >= Rm_VPR128.16B[40,8]) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] >= Rm_VPR128.16B[48,8]) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] >= Rm_VPR128.16B[56,8]) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] >= Rm_VPR128.16B[64,8]) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] >= Rm_VPR128.16B[72,8]) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] >= Rm_VPR128.16B[80,8]) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] >= Rm_VPR128.16B[88,8]) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] >= Rm_VPR128.16B[96,8]) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] >= Rm_VPR128.16B[104,8]) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] >= Rm_VPR128.16B[112,8]) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] >= Rm_VPR128.16B[120,8]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x2e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2\n# AUNIT --inst x2e603c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] >= Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] >= Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] >= Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] >= Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x6e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2\n# AUNIT --inst x6e603c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] >= Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] >= Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] >= Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] >= Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] >= Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] >= Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] >= Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] >= Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x2ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4\n# AUNIT --inst x2ea03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] >= Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] >= Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x6ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4\n# AUNIT --inst x6ea03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] >= Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] >= Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] >= Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] >= Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00\n# CONSTRUCT x6ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@8\n# AUNIT --inst x6ee03c00/mask=xffe0fc00 --status nopcodeop\n\n:cmhs Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] >= Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] >= Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x7e209800/mask=xff3ffc00\n# CONSTRUCT x7ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2\n# AUNIT --inst x7ee09800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_FPR64, Rn_FPR64, \"#0\"\nis b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 s<= 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x2e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1\n# AUNIT --inst x2e209800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR64.8B, Rn_VPR64.8B, \"#0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] s<= zero) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] s<= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x6e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1\n# AUNIT --inst x6e209800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR128.16B, Rn_VPR128.16B, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] s<= zero) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] s<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x2e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2\n# AUNIT --inst x2e609800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR64.4H, Rn_VPR64.4H, \"#0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] s<= zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] s<= zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] s<= zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] s<= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x6e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2\n# AUNIT --inst x6e609800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR128.8H, Rn_VPR128.8H, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] s<= zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] s<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x2ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4\n# AUNIT --inst x2ea09800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR64.2S, Rn_VPR64.2S, \"#0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] s<= zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] s<= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x6ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4\n# AUNIT --inst x6ea09800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR128.4S, Rn_VPR128.4S, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] s<= zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] s<= zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] s<= zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] s<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00\n# CONSTRUCT x6ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2@8\n# AUNIT --inst x6ee09800/mask=xfffffc00 --status nopcodeop\n\n:cmle Rd_VPR128.2D, Rn_VPR128.2D, \"#0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] s<= zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] s<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x5e20a800/mask=xff3ffc00\n# CONSTRUCT x5ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2\n# AUNIT --inst x5ee0a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_FPR64, Rn_FPR64, \"#0\"\nis b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101010 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 s< 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x0e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1\n# AUNIT --inst x0e20a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR64.8B, Rn_VPR64.8B, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR64.8B[0,8] = (Rn_VPR64.8B[0,8] s< zero) * eqVal;\n\tRd_VPR64.8B[8,8] = (Rn_VPR64.8B[8,8] s< zero) * eqVal;\n\tRd_VPR64.8B[16,8] = (Rn_VPR64.8B[16,8] s< zero) * eqVal;\n\tRd_VPR64.8B[24,8] = (Rn_VPR64.8B[24,8] s< zero) * eqVal;\n\tRd_VPR64.8B[32,8] = (Rn_VPR64.8B[32,8] s< zero) * eqVal;\n\tRd_VPR64.8B[40,8] = (Rn_VPR64.8B[40,8] s< zero) * eqVal;\n\tRd_VPR64.8B[48,8] = (Rn_VPR64.8B[48,8] s< zero) * eqVal;\n\tRd_VPR64.8B[56,8] = (Rn_VPR64.8B[56,8] s< zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x4e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1\n# AUNIT --inst x4e20a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR128.16B, Rn_VPR128.16B, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tlocal zero:1 = 0;\n\tRd_VPR128.16B[0,8] = (Rn_VPR128.16B[0,8] s< zero) * eqVal;\n\tRd_VPR128.16B[8,8] = (Rn_VPR128.16B[8,8] s< zero) * eqVal;\n\tRd_VPR128.16B[16,8] = (Rn_VPR128.16B[16,8] s< zero) * eqVal;\n\tRd_VPR128.16B[24,8] = (Rn_VPR128.16B[24,8] s< zero) * eqVal;\n\tRd_VPR128.16B[32,8] = (Rn_VPR128.16B[32,8] s< zero) * eqVal;\n\tRd_VPR128.16B[40,8] = (Rn_VPR128.16B[40,8] s< zero) * eqVal;\n\tRd_VPR128.16B[48,8] = (Rn_VPR128.16B[48,8] s< zero) * eqVal;\n\tRd_VPR128.16B[56,8] = (Rn_VPR128.16B[56,8] s< zero) * eqVal;\n\tRd_VPR128.16B[64,8] = (Rn_VPR128.16B[64,8] s< zero) * eqVal;\n\tRd_VPR128.16B[72,8] = (Rn_VPR128.16B[72,8] s< zero) * eqVal;\n\tRd_VPR128.16B[80,8] = (Rn_VPR128.16B[80,8] s< zero) * eqVal;\n\tRd_VPR128.16B[88,8] = (Rn_VPR128.16B[88,8] s< zero) * eqVal;\n\tRd_VPR128.16B[96,8] = (Rn_VPR128.16B[96,8] s< zero) * eqVal;\n\tRd_VPR128.16B[104,8] = (Rn_VPR128.16B[104,8] s< zero) * eqVal;\n\tRd_VPR128.16B[112,8] = (Rn_VPR128.16B[112,8] s< zero) * eqVal;\n\tRd_VPR128.16B[120,8] = (Rn_VPR128.16B[120,8] s< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x0e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2\n# AUNIT --inst x0e60a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR64.4H, Rn_VPR64.4H, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] s< zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] s< zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] s< zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] s< zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x4e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2\n# AUNIT --inst x4e60a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR128.8H, Rn_VPR128.8H, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] s< zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] s< zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] s< zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] s< zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] s< zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] s< zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] s< zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] s< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x0ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4\n# AUNIT --inst x0ea0a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR64.2S, Rn_VPR64.2S, \"#0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] s< zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] s< zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x4ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4\n# AUNIT --inst x4ea0a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR128.4S, Rn_VPR128.4S, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] s< zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] s< zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] s< zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] s< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00\n# CONSTRUCT x4ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2@8\n# AUNIT --inst x4ee0a800/mask=xfffffc00 --status nopcodeop\n\n:cmlt Rd_VPR128.2D, Rn_VPR128.2D, \"#0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] s< zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] s< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x5e208c00/mask=xff20fc00\n# CONSTRUCT x5ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2\n# AUNIT --inst x5ee08c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = (Rn_FPR64 & Rm_FPR64) != 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x0e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1\n# AUNIT --inst x0e208c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x11 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR64.8B[0,8] = ((Rn_VPR64.8B[0,8] & Rm_VPR64.8B[0,8]) != 0) * eqVal;\n\tRd_VPR64.8B[8,8] = ((Rn_VPR64.8B[8,8] & Rm_VPR64.8B[8,8]) != 0) * eqVal;\n\tRd_VPR64.8B[16,8] = ((Rn_VPR64.8B[16,8] & Rm_VPR64.8B[16,8]) != 0) * eqVal;\n\tRd_VPR64.8B[24,8] = ((Rn_VPR64.8B[24,8] & Rm_VPR64.8B[24,8]) != 0) * eqVal;\n\tRd_VPR64.8B[32,8] = ((Rn_VPR64.8B[32,8] & Rm_VPR64.8B[32,8]) != 0) * eqVal;\n\tRd_VPR64.8B[40,8] = ((Rn_VPR64.8B[40,8] & Rm_VPR64.8B[40,8]) != 0) * eqVal;\n\tRd_VPR64.8B[48,8] = ((Rn_VPR64.8B[48,8] & Rm_VPR64.8B[48,8]) != 0) * eqVal;\n\tRd_VPR64.8B[56,8] = ((Rn_VPR64.8B[56,8] & Rm_VPR64.8B[56,8]) != 0) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x4e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1\n# AUNIT --inst x4e208c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x11 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal eqVal:1 = ~ 0;\n\tRd_VPR128.16B[0,8] = ((Rn_VPR128.16B[0,8] & Rm_VPR128.16B[0,8]) != 0) * eqVal;\n\tRd_VPR128.16B[8,8] = ((Rn_VPR128.16B[8,8] & Rm_VPR128.16B[8,8]) != 0) * eqVal;\n\tRd_VPR128.16B[16,8] = ((Rn_VPR128.16B[16,8] & Rm_VPR128.16B[16,8]) != 0) * eqVal;\n\tRd_VPR128.16B[24,8] = ((Rn_VPR128.16B[24,8] & Rm_VPR128.16B[24,8]) != 0) * eqVal;\n\tRd_VPR128.16B[32,8] = ((Rn_VPR128.16B[32,8] & Rm_VPR128.16B[32,8]) != 0) * eqVal;\n\tRd_VPR128.16B[40,8] = ((Rn_VPR128.16B[40,8] & Rm_VPR128.16B[40,8]) != 0) * eqVal;\n\tRd_VPR128.16B[48,8] = ((Rn_VPR128.16B[48,8] & Rm_VPR128.16B[48,8]) != 0) * eqVal;\n\tRd_VPR128.16B[56,8] = ((Rn_VPR128.16B[56,8] & Rm_VPR128.16B[56,8]) != 0) * eqVal;\n\tRd_VPR128.16B[64,8] = ((Rn_VPR128.16B[64,8] & Rm_VPR128.16B[64,8]) != 0) * eqVal;\n\tRd_VPR128.16B[72,8] = ((Rn_VPR128.16B[72,8] & Rm_VPR128.16B[72,8]) != 0) * eqVal;\n\tRd_VPR128.16B[80,8] = ((Rn_VPR128.16B[80,8] & Rm_VPR128.16B[80,8]) != 0) * eqVal;\n\tRd_VPR128.16B[88,8] = ((Rn_VPR128.16B[88,8] & Rm_VPR128.16B[88,8]) != 0) * eqVal;\n\tRd_VPR128.16B[96,8] = ((Rn_VPR128.16B[96,8] & Rm_VPR128.16B[96,8]) != 0) * eqVal;\n\tRd_VPR128.16B[104,8] = ((Rn_VPR128.16B[104,8] & Rm_VPR128.16B[104,8]) != 0) * eqVal;\n\tRd_VPR128.16B[112,8] = ((Rn_VPR128.16B[112,8] & Rm_VPR128.16B[112,8]) != 0) * eqVal;\n\tRd_VPR128.16B[120,8] = ((Rn_VPR128.16B[120,8] & Rm_VPR128.16B[120,8]) != 0) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x0e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2\n# AUNIT --inst x0e608c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x11 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext((Rn_VPR64.4H[0,16] & Rm_VPR64.4H[0,16]) != 0) * eqVal;\n\tRd_VPR64.4H[16,16] = zext((Rn_VPR64.4H[16,16] & Rm_VPR64.4H[16,16]) != 0) * eqVal;\n\tRd_VPR64.4H[32,16] = zext((Rn_VPR64.4H[32,16] & Rm_VPR64.4H[32,16]) != 0) * eqVal;\n\tRd_VPR64.4H[48,16] = zext((Rn_VPR64.4H[48,16] & Rm_VPR64.4H[48,16]) != 0) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x4e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2\n# AUNIT --inst x4e608c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext((Rn_VPR128.8H[0,16] & Rm_VPR128.8H[0,16]) != 0) * eqVal;\n\tRd_VPR128.8H[16,16] = zext((Rn_VPR128.8H[16,16] & Rm_VPR128.8H[16,16]) != 0) * eqVal;\n\tRd_VPR128.8H[32,16] = zext((Rn_VPR128.8H[32,16] & Rm_VPR128.8H[32,16]) != 0) * eqVal;\n\tRd_VPR128.8H[48,16] = zext((Rn_VPR128.8H[48,16] & Rm_VPR128.8H[48,16]) != 0) * eqVal;\n\tRd_VPR128.8H[64,16] = zext((Rn_VPR128.8H[64,16] & Rm_VPR128.8H[64,16]) != 0) * eqVal;\n\tRd_VPR128.8H[80,16] = zext((Rn_VPR128.8H[80,16] & Rm_VPR128.8H[80,16]) != 0) * eqVal;\n\tRd_VPR128.8H[96,16] = zext((Rn_VPR128.8H[96,16] & Rm_VPR128.8H[96,16]) != 0) * eqVal;\n\tRd_VPR128.8H[112,16] = zext((Rn_VPR128.8H[112,16] & Rm_VPR128.8H[112,16]) != 0) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x0ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4\n# AUNIT --inst x0ea08c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x11 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext((Rn_VPR64.2S[0,32] & Rm_VPR64.2S[0,32]) != 0) * eqVal;\n\tRd_VPR64.2S[32,32] = zext((Rn_VPR64.2S[32,32] & Rm_VPR64.2S[32,32]) != 0) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x4ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4\n# AUNIT --inst x4ea08c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext((Rn_VPR128.4S[0,32] & Rm_VPR128.4S[0,32]) != 0) * eqVal;\n\tRd_VPR128.4S[32,32] = zext((Rn_VPR128.4S[32,32] & Rm_VPR128.4S[32,32]) != 0) * eqVal;\n\tRd_VPR128.4S[64,32] = zext((Rn_VPR128.4S[64,32] & Rm_VPR128.4S[64,32]) != 0) * eqVal;\n\tRd_VPR128.4S[96,32] = zext((Rn_VPR128.4S[96,32] & Rm_VPR128.4S[96,32]) != 0) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00\n# CONSTRUCT x4ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@8\n# AUNIT --inst x4ee08c00/mask=xffe0fc00 --status nopcodeop\n\n:cmtst Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext((Rn_VPR128.2D[0,64] & Rm_VPR128.2D[0,64]) != 0) * eqVal;\n\tRd_VPR128.2D[64,64] = zext((Rn_VPR128.2D[64,64] & Rm_VPR128.2D[64,64]) != 0) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.38 CNT page C7-2092 line 121883 MATCH x0e205800/mask=xbf3ffc00\n# CONSTRUCT x0e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1\n# AUNIT --inst x0e205800/mask=xfffffc00 --status nopcodeop\n\n:cnt Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = popcount(Rn_VPR64.8B) on lane size 1\n\tRd_VPR64.8B[0,8] = popcount(Rn_VPR64.8B[0,8]);\n\tRd_VPR64.8B[8,8] = popcount(Rn_VPR64.8B[8,8]);\n\tRd_VPR64.8B[16,8] = popcount(Rn_VPR64.8B[16,8]);\n\tRd_VPR64.8B[24,8] = popcount(Rn_VPR64.8B[24,8]);\n\tRd_VPR64.8B[32,8] = popcount(Rn_VPR64.8B[32,8]);\n\tRd_VPR64.8B[40,8] = popcount(Rn_VPR64.8B[40,8]);\n\tRd_VPR64.8B[48,8] = popcount(Rn_VPR64.8B[48,8]);\n\tRd_VPR64.8B[56,8] = popcount(Rn_VPR64.8B[56,8]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.38 CNT page C7-2092 line 121883 MATCH x0e205800/mask=xbf3ffc00\n# CONSTRUCT x4e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1\n# AUNIT --inst x4e205800/mask=xfffffc00 --status nopcodeop\n\n:cnt Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = popcount(Rn_VPR128.16B) on lane size 1\n\tRd_VPR128.16B[0,8] = popcount(Rn_VPR128.16B[0,8]);\n\tRd_VPR128.16B[8,8] = popcount(Rn_VPR128.16B[8,8]);\n\tRd_VPR128.16B[16,8] = popcount(Rn_VPR128.16B[16,8]);\n\tRd_VPR128.16B[24,8] = popcount(Rn_VPR128.16B[24,8]);\n\tRd_VPR128.16B[32,8] = popcount(Rn_VPR128.16B[32,8]);\n\tRd_VPR128.16B[40,8] = popcount(Rn_VPR128.16B[40,8]);\n\tRd_VPR128.16B[48,8] = popcount(Rn_VPR128.16B[48,8]);\n\tRd_VPR128.16B[56,8] = popcount(Rn_VPR128.16B[56,8]);\n\tRd_VPR128.16B[64,8] = popcount(Rn_VPR128.16B[64,8]);\n\tRd_VPR128.16B[72,8] = popcount(Rn_VPR128.16B[72,8]);\n\tRd_VPR128.16B[80,8] = popcount(Rn_VPR128.16B[80,8]);\n\tRd_VPR128.16B[88,8] = popcount(Rn_VPR128.16B[88,8]);\n\tRd_VPR128.16B[96,8] = popcount(Rn_VPR128.16B[96,8]);\n\tRd_VPR128.16B[104,8] = popcount(Rn_VPR128.16B[104,8]);\n\tRd_VPR128.16B[112,8] = popcount(Rn_VPR128.16B[112,8]);\n\tRd_VPR128.16B[120,8] = popcount(Rn_VPR128.16B[120,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x4e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1\n# AUNIT --inst x4e010400/mask=xffe1fc00 --status pass\n\n:dup Rd_VPR128.16B, Rn_VPR128.B.imm_neon_uimm4\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.16B & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm4] lane size 1\n\tlocal tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;\n\t# simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1)\n\tRd_VPR128.16B[0,8] = tmp1;\n\tRd_VPR128.16B[8,8] = tmp1;\n\tRd_VPR128.16B[16,8] = tmp1;\n\tRd_VPR128.16B[24,8] = tmp1;\n\tRd_VPR128.16B[32,8] = tmp1;\n\tRd_VPR128.16B[40,8] = tmp1;\n\tRd_VPR128.16B[48,8] = tmp1;\n\tRd_VPR128.16B[56,8] = tmp1;\n\tRd_VPR128.16B[64,8] = tmp1;\n\tRd_VPR128.16B[72,8] = tmp1;\n\tRd_VPR128.16B[80,8] = tmp1;\n\tRd_VPR128.16B[88,8] = tmp1;\n\tRd_VPR128.16B[96,8] = tmp1;\n\tRd_VPR128.16B[104,8] = tmp1;\n\tRd_VPR128.16B[112,8] = tmp1;\n\tRd_VPR128.16B[120,8] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x4e080400/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8\n# AUNIT --inst x4e080400/mask=xffeffc00 --status pass\n\n:dup Rd_VPR128.2D, Rn_VPR128.D.imm_neon_uimm1\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.2D & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm1] lane size 8\n\tlocal tmp1:8 = Rn_VPR128.D.imm_neon_uimm1;\n\t# simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8)\n\tRd_VPR128.2D[0,64] = tmp1;\n\tRd_VPR128.2D[64,64] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x0e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4\n# AUNIT --inst x0e040400/mask=xffe7fc00 --status pass\n\n:dup Rd_VPR64.2S, Rn_VPR128.S.imm_neon_uimm2\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.2S & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm2] lane size 4\n\tlocal tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;\n\t# simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)\n\tRd_VPR64.2S[0,32] = tmp1;\n\tRd_VPR64.2S[32,32] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x0e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2\n# AUNIT --inst x0e020400/mask=xffe3fc00 --status pass\n\n:dup Rd_VPR64.4H, Rn_VPR128.H.imm_neon_uimm3\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.4H & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm3] lane size 2\n\tlocal tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;\n\t# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)\n\tRd_VPR64.4H[0,16] = tmp1;\n\tRd_VPR64.4H[16,16] = tmp1;\n\tRd_VPR64.4H[32,16] = tmp1;\n\tRd_VPR64.4H[48,16] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x4e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4\n# AUNIT --inst x4e040400/mask=xffe7fc00 --status pass\n\n:dup Rd_VPR128.4S, Rn_VPR128.S.imm_neon_uimm2\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.4S & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm2] lane size 4\n\tlocal tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;\n\t# simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)\n\tRd_VPR128.4S[0,32] = tmp1;\n\tRd_VPR128.4S[32,32] = tmp1;\n\tRd_VPR128.4S[64,32] = tmp1;\n\tRd_VPR128.4S[96,32] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x0e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1\n# AUNIT --inst x0e010400/mask=xffe1fc00 --status pass\n\n:dup Rd_VPR64.8B, Rn_VPR128.B.imm_neon_uimm4\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.8B & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm4] lane size 1\n\tlocal tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;\n\t# simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1)\n\tRd_VPR64.8B[0,8] = tmp1;\n\tRd_VPR64.8B[8,8] = tmp1;\n\tRd_VPR64.8B[16,8] = tmp1;\n\tRd_VPR64.8B[24,8] = tmp1;\n\tRd_VPR64.8B[32,8] = tmp1;\n\tRd_VPR64.8B[40,8] = tmp1;\n\tRd_VPR64.8B[48,8] = tmp1;\n\tRd_VPR64.8B[56,8] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00\n# CONSTRUCT x4e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2\n# AUNIT --inst x4e020400/mask=xffe3fc00 --status pass\n\n:dup Rd_VPR128.8H, Rn_VPR128.H.imm_neon_uimm3\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.8H & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm3] lane size 2\n\tlocal tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;\n\t# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)\n\tRd_VPR128.8H[0,16] = tmp1;\n\tRd_VPR128.8H[16,16] = tmp1;\n\tRd_VPR128.8H[32,16] = tmp1;\n\tRd_VPR128.8H[48,16] = tmp1;\n\tRd_VPR128.8H[64,16] = tmp1;\n\tRd_VPR128.8H[80,16] = tmp1;\n\tRd_VPR128.8H[96,16] = tmp1;\n\tRd_VPR128.8H[112,16] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00\n# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00\n# CONSTRUCT x5e010400/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 =ARG2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1\n# AUNIT --inst x5e010400/mask=xffe1fc00 --status pass\n\n:dup Rd_FPR8, Rn_VPR128.B.imm_neon_uimm4\nis b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR8 & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm4] lane size 1\n\tRd_FPR8 = Rn_VPR128.B.imm_neon_uimm4;\n\tzext_zb(Zd); # zero upper 31 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00\n# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00\n# CONSTRUCT x5e080400/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 =ARG2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8\n# AUNIT --inst x5e080400/mask=xffeffc00 --status pass\n\n:dup Rd_FPR64, Rn_VPR128.D.imm_neon_uimm1\nis b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR64 & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm1] lane size 8\n\tRd_FPR64 = Rn_VPR128.D.imm_neon_uimm1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00\n# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00\n# CONSTRUCT x5e020400/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 =ARG2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2\n# AUNIT --inst x5e020400/mask=xffe3fc00 --status pass\n\n:dup Rd_FPR16, Rn_VPR128.H.imm_neon_uimm3\nis b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR16 & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm3] lane size 2\n\tRd_FPR16 = Rn_VPR128.H.imm_neon_uimm3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00\n# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00\n# CONSTRUCT x5e040400/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 =ARG2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4\n# AUNIT --inst x5e040400/mask=xffe7fc00 --status pass\n\n:dup Rd_FPR32, Rn_VPR128.S.imm_neon_uimm2\nis b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR32 & Zd\n{\n\t# simd element Rn_VPR128[imm_neon_uimm2] lane size 4\n\tRd_FPR32 = Rn_VPR128.S.imm_neon_uimm2;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x4e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2[0]:1 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1\n# AUNIT --inst x4e010c00/mask=xffe1fc00 --status pass\n\n:dup Rd_VPR128.16B, Rn_GPR32\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.16B & Zd\n{\n\tlocal tmp1:1 = Rn_GPR32[0,8];\n\t# simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1)\n\tRd_VPR128.16B[0,8] = tmp1;\n\tRd_VPR128.16B[8,8] = tmp1;\n\tRd_VPR128.16B[16,8] = tmp1;\n\tRd_VPR128.16B[24,8] = tmp1;\n\tRd_VPR128.16B[32,8] = tmp1;\n\tRd_VPR128.16B[40,8] = tmp1;\n\tRd_VPR128.16B[48,8] = tmp1;\n\tRd_VPR128.16B[56,8] = tmp1;\n\tRd_VPR128.16B[64,8] = tmp1;\n\tRd_VPR128.16B[72,8] = tmp1;\n\tRd_VPR128.16B[80,8] = tmp1;\n\tRd_VPR128.16B[88,8] = tmp1;\n\tRd_VPR128.16B[96,8] = tmp1;\n\tRd_VPR128.16B[104,8] = tmp1;\n\tRd_VPR128.16B[112,8] = tmp1;\n\tRd_VPR128.16B[120,8] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x4e080c00/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8\n# AUNIT --inst x4e080c00/mask=xffeffc00 --status pass\n\n:dup Rd_VPR128.2D, Rn_GPR64\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1619=0b1000 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR64 & Rd_VPR128.2D & Zd\n{\n\t# simd duplicate Rd_VPR128.2D = all elements Rn_GPR64 (lane size 8)\n\tRd_VPR128.2D[0,64] = Rn_GPR64;\n\tRd_VPR128.2D[64,64] = Rn_GPR64;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x0e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4\n# AUNIT --inst x0e040c00/mask=xffe7fc00 --status pass\n\n:dup Rd_VPR64.2S, Rn_GPR32\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.2S & Zd\n{\n\t# simd duplicate Rd_VPR64.2S = all elements Rn_GPR32 (lane size 4)\n\tRd_VPR64.2S[0,32] = Rn_GPR32;\n\tRd_VPR64.2S[32,32] = Rn_GPR32;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x0e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2\n# AUNIT --inst x0e020c00/mask=xffe3fc00 --status pass\n\n:dup Rd_VPR64.4H, Rn_GPR32\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.4H & Zd\n{\n\tlocal tmp1:2 = Rn_GPR32[0,16];\n\t# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)\n\tRd_VPR64.4H[0,16] = tmp1;\n\tRd_VPR64.4H[16,16] = tmp1;\n\tRd_VPR64.4H[32,16] = tmp1;\n\tRd_VPR64.4H[48,16] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x4e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4\n# AUNIT --inst x4e040c00/mask=xffe7fc00 --status pass\n\n:dup Rd_VPR128.4S, Rn_GPR32\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.4S & Zd\n{\n\t# simd duplicate Rd_VPR128.4S = all elements Rn_GPR32 (lane size 4)\n\tRd_VPR128.4S[0,32] = Rn_GPR32;\n\tRd_VPR128.4S[32,32] = Rn_GPR32;\n\tRd_VPR128.4S[64,32] = Rn_GPR32;\n\tRd_VPR128.4S[96,32] = Rn_GPR32;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x0e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:1 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1\n# AUNIT --inst x0e010c00/mask=xffe1fc00 --status pass\n\n:dup Rd_VPR64.8B, Rn_GPR32\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.8B & Zd\n{\n\tlocal tmp1:1 = Rn_GPR32[0,8];\n\t# simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1)\n\tRd_VPR64.8B[0,8] = tmp1;\n\tRd_VPR64.8B[8,8] = tmp1;\n\tRd_VPR64.8B[16,8] = tmp1;\n\tRd_VPR64.8B[24,8] = tmp1;\n\tRd_VPR64.8B[32,8] = tmp1;\n\tRd_VPR64.8B[40,8] = tmp1;\n\tRd_VPR64.8B[48,8] = tmp1;\n\tRd_VPR64.8B[56,8] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00\n# CONSTRUCT x4e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2\n# AUNIT --inst x4e020c00/mask=xffe3fc00 --status pass\n\n:dup Rd_VPR128.8H, Rn_GPR32\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.8H & Zd\n{\n\tlocal tmp1:2 = Rn_GPR32[0,16];\n\t# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)\n\tRd_VPR128.8H[0,16] = tmp1;\n\tRd_VPR128.8H[16,16] = tmp1;\n\tRd_VPR128.8H[32,16] = tmp1;\n\tRd_VPR128.8H[48,16] = tmp1;\n\tRd_VPR128.8H[64,16] = tmp1;\n\tRd_VPR128.8H[80,16] = tmp1;\n\tRd_VPR128.8H[96,16] = tmp1;\n\tRd_VPR128.8H[112,16] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.41 EOR (vector) page C7-2099 line 122248 MATCH x2e201c00/mask=xbfe0fc00\n# CONSTRUCT x6e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$^@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1\n# AUNIT --inst x6e201c00/mask=xffe0fc00 --status pass\n\n:eor Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B ^ Rm_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] ^ Rm_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] ^ Rm_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] ^ Rm_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] ^ Rm_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] ^ Rm_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] ^ Rm_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] ^ Rm_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] ^ Rm_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] ^ Rm_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] ^ Rm_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] ^ Rm_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] ^ Rm_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] ^ Rm_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] ^ Rm_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] ^ Rm_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] ^ Rm_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.41 EOR (vector) page C7-2099 line 122248 MATCH x2e201c00/mask=xbfe0fc00\n# CONSTRUCT x2e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$^@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1\n# AUNIT --inst x2e201c00/mask=xffe0fc00 --status pass\n\n:eor Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B ^ Rm_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] ^ Rm_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] ^ Rm_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] ^ Rm_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] ^ Rm_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] ^ Rm_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] ^ Rm_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] ^ Rm_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] ^ Rm_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.42 EOR3 page C7-2101 line 122332 MATCH xce000000/mask=xffe08000\n# CONSTRUCT xce000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 ARG4 $|@1 =$|@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_eor3/3@1\n# AUNIT --inst xce000000/mask=xffe08000 --status noqemu\n\n:eor3 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B\nis b_2131=0b11001110000 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rm_VPR128.16B | Ra_VPR128.16B on lane size 1\n\tTMPQ1[0,8] = Rm_VPR128.16B[0,8] | Ra_VPR128.16B[0,8];\n\tTMPQ1[8,8] = Rm_VPR128.16B[8,8] | Ra_VPR128.16B[8,8];\n\tTMPQ1[16,8] = Rm_VPR128.16B[16,8] | Ra_VPR128.16B[16,8];\n\tTMPQ1[24,8] = Rm_VPR128.16B[24,8] | Ra_VPR128.16B[24,8];\n\tTMPQ1[32,8] = Rm_VPR128.16B[32,8] | Ra_VPR128.16B[32,8];\n\tTMPQ1[40,8] = Rm_VPR128.16B[40,8] | Ra_VPR128.16B[40,8];\n\tTMPQ1[48,8] = Rm_VPR128.16B[48,8] | Ra_VPR128.16B[48,8];\n\tTMPQ1[56,8] = Rm_VPR128.16B[56,8] | Ra_VPR128.16B[56,8];\n\tTMPQ1[64,8] = Rm_VPR128.16B[64,8] | Ra_VPR128.16B[64,8];\n\tTMPQ1[72,8] = Rm_VPR128.16B[72,8] | Ra_VPR128.16B[72,8];\n\tTMPQ1[80,8] = Rm_VPR128.16B[80,8] | Ra_VPR128.16B[80,8];\n\tTMPQ1[88,8] = Rm_VPR128.16B[88,8] | Ra_VPR128.16B[88,8];\n\tTMPQ1[96,8] = Rm_VPR128.16B[96,8] | Ra_VPR128.16B[96,8];\n\tTMPQ1[104,8] = Rm_VPR128.16B[104,8] | Ra_VPR128.16B[104,8];\n\tTMPQ1[112,8] = Rm_VPR128.16B[112,8] | Ra_VPR128.16B[112,8];\n\tTMPQ1[120,8] = Rm_VPR128.16B[120,8] | Ra_VPR128.16B[120,8];\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.43 EXT page C7-2102 line 122403 MATCH x2e000000/mask=xbfe08400\n# CONSTRUCT x6e000000/mask=xffe08400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1\n# AUNIT --inst x6e000000/mask=xffe08400 --status nopcodeop\n\n:ext Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, imm4\nis b_3131=0 & q=1 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & imm4 & b_1010=0 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_ext(Rn_VPR128.16B, Rm_VPR128.16B, imm4:1, 1:1);\n}\n\n# C7.2.43 EXT page C7-2102 line 122403 MATCH x2e000000/mask=xbfe08400\n# CONSTRUCT x2e000000/mask=xffe0c400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1\n# AUNIT --inst x2e000000/mask=xffe0c400 --status nopcodeop\n\n:ext Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, imm4\nis b_3131=0 & q=0 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR64.8B & b_1415=0 & imm4 & b_1010=0 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_ext(Rn_VPR64.8B, Rm_VPR64.8B, imm4:1, 1:1);\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ec01400/mask=xbfe0fc00\n# CONSTRUCT x2ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2\n# AUNIT --inst x2ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 sz=1 bb=0 cc=00 F=VPR64.4H\n\n:fabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16];\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16];\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16];\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16];\n\t# simd unary Rd_VPR64.4H = abs(TMPD1) on lane size 2\n\tRd_VPR64.4H[0,16] = abs(TMPD1[0,16]);\n\tRd_VPR64.4H[16,16] = abs(TMPD1[16,16]);\n\tRd_VPR64.4H[32,16] = abs(TMPD1[32,16]);\n\tRd_VPR64.4H[48,16] = abs(TMPD1[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ec01400/mask=xbfe0fc00\n# CONSTRUCT x6ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2\n# AUNIT --inst x6ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 sz=1 bb=0 cc=00 F=VPR128.8H\n\n:fabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16];\n\t# simd unary Rd_VPR128.8H = abs(TMPQ1) on lane size 2\n\tRd_VPR128.8H[0,16] = abs(TMPQ1[0,16]);\n\tRd_VPR128.8H[16,16] = abs(TMPQ1[16,16]);\n\tRd_VPR128.8H[32,16] = abs(TMPQ1[32,16]);\n\tRd_VPR128.8H[48,16] = abs(TMPQ1[48,16]);\n\tRd_VPR128.8H[64,16] = abs(TMPQ1[64,16]);\n\tRd_VPR128.8H[80,16] = abs(TMPQ1[80,16]);\n\tRd_VPR128.8H[96,16] = abs(TMPQ1[96,16]);\n\tRd_VPR128.8H[112,16] = abs(TMPQ1[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00\n# CONSTRUCT x2ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4\n# AUNIT --inst x2ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n# Vector half precision variant when Q=0 sz=0 bb=1 cc=11 F=VPR64.2S\n\n:fabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32];\n\t# simd unary Rd_VPR64.2S = abs(TMPD1) on lane size 4\n\tRd_VPR64.2S[0,32] = abs(TMPD1[0,32]);\n\tRd_VPR64.2S[32,32] = abs(TMPD1[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00\n# CONSTRUCT x6ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4\n# AUNIT --inst x6ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n# Vector half precision variant when Q=1 sz=0 bb=1 cc=11 F=VPR128.4S\n\n:fabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32];\n\t# simd unary Rd_VPR128.4S = abs(TMPQ1) on lane size 4\n\tRd_VPR128.4S[0,32] = abs(TMPQ1[0,32]);\n\tRd_VPR128.4S[32,32] = abs(TMPQ1[32,32]);\n\tRd_VPR128.4S[64,32] = abs(TMPQ1[64,32]);\n\tRd_VPR128.4S[96,32] = abs(TMPQ1[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00\n# CONSTRUCT x6ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f-@8 =$fabs@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@8\n# AUNIT --inst x6ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n# Vector half precision variant when Q=1 sz=1 bb=1 cc=11 F=VPR128.2D\n\n:fabd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=1 & b_1015=0b110101 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64];\n\t# simd unary Rd_VPR128.2D = abs(TMPQ1) on lane size 8\n\tRd_VPR128.2D[0,64] = abs(TMPQ1[0,64]);\n\tRd_VPR128.2D[64,64] = abs(TMPQ1[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ec01400/mask=xffe0fc00\n# CONSTRUCT x7ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f- =fabs\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2\n# AUNIT --inst x7ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision variant when sz=1 bb=0 cc=00 F=FPR16\n\n:fabd Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01111110110 & b_1015=0b000101 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:2 = Rn_FPR16 f- Rm_FPR16;\n\tRd_FPR16 = abs(tmp1);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ea0d400/mask=xffa0fc00\n# CONSTRUCT x7ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f- =fabs\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2\n# AUNIT --inst x7ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n# Scalar half precision variant when sz=0 bb=1 cc=11 F=FPR32\n\n:fabd Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_2131=0b01111110101 & b_1015=0b110101 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:4 = Rn_FPR32 f- Rm_FPR32;\n\tRd_FPR32 = abs(tmp1);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ea0d400/mask=xffa0fc00\n# CONSTRUCT x7ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f- =fabs\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2\n# AUNIT --inst x7ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n# Scalar half precision variant when sz=1 bb=1 cc=11 F=FPR64\n\n:fabd Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2131=0b01111110111 & b_1015=0b110101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:8 = Rn_FPR64 f- Rm_FPR64;\n\tRd_FPR64 = abs(tmp1);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00\n# CONSTRUCT x4ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fabs@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@8\n# AUNIT --inst x4ee0f800/mask=xfffffc00 --rand dfp --status pass\n\n:fabs Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = abs(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = abs(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = abs(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00\n# CONSTRUCT x0ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fabs@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4\n# AUNIT --inst x0ea0f800/mask=xfffffc00 --rand sfp --status pass\n\n:fabs Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = abs(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = abs(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = abs(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00\n# CONSTRUCT x4ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fabs@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4\n# AUNIT --inst x4ea0f800/mask=xfffffc00 --rand sfp --status pass\n\n:fabs Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = abs(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = abs(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = abs(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = abs(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = abs(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ef8f800/mask=xbffffc00\n# CONSTRUCT x0ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fabs@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2\n# AUNIT --inst x0ef8f800/mask=xfffffc00 --rand hfp --status noqemu\n# FABS (vector) SIMD 4H when size=0 Q=0\n\n:fabs Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = abs(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = abs(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = abs(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = abs(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = abs(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ef8f800/mask=xbffffc00\n# CONSTRUCT x4ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fabs@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2\n# AUNIT --inst x4ef8f800/mask=xfffffc00 --rand hfp --status noqemu\n# FABS (vector) SIMD 8H when size=0 Q=1\n\n:fabs Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = abs(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = abs(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = abs(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = abs(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = abs(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = abs(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = abs(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = abs(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = abs(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00\n# CONSTRUCT x1ee0c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =fabs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1\n# AUNIT --inst x1ee0c000/mask=xfffffc00 --rand hfp --status noqemu\n\n:fabs Rd_FPR16, Rn_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = abs(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00\n# CONSTRUCT x1e60c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =fabs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1\n# AUNIT --inst x1e60c000/mask=xfffffc00 --rand dfp --status pass\n\n:fabs Rd_FPR64, Rn_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = abs(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00\n# CONSTRUCT x1e20c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =fabs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1\n# AUNIT --inst x1e20c000/mask=xfffffc00 --rand sfp --status pass\n\n:fabs Rd_FPR32, Rn_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = abs(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00\n# CONSTRUCT x6e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@8\n# AUNIT --inst x6e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop\n\n:facge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(abs(Rn_VPR128.2D[0,64]) f>= abs(Rm_VPR128.2D[0,64])) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(abs(Rn_VPR128.2D[64,64]) f>= abs(Rm_VPR128.2D[64,64])) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00\n# CONSTRUCT x2e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4\n# AUNIT --inst x2e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop\n\n:facge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(abs(Rn_VPR64.2S[0,32]) f>= abs(Rm_VPR64.2S[0,32])) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(abs(Rn_VPR64.2S[32,32]) f>= abs(Rm_VPR64.2S[32,32])) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00\n# CONSTRUCT x6e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4\n# AUNIT --inst x6e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop\n\n:facge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(abs(Rn_VPR128.4S[0,32]) f>= abs(Rm_VPR128.4S[0,32])) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(abs(Rn_VPR128.4S[32,32]) f>= abs(Rm_VPR128.4S[32,32])) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(abs(Rn_VPR128.4S[64,32]) f>= abs(Rm_VPR128.4S[64,32])) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(abs(Rn_VPR128.4S[96,32]) f>= abs(Rm_VPR128.4S[96,32])) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e402c00/mask=xffe0fc00\n# CONSTRUCT x7e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2\n# AUNIT --inst x7e402c00/mask=xffe0fc00 --rand hfp --status noqemu\n# Scalar half precision\n\n:facge Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01111110010 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:1 = abs(Rn_FPR16) f>= abs(Rm_FPR16);\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e20ec00/mask=xffa0fc00\n# CONSTRUCT x7e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2\n# AUNIT --inst x7e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop\n# Scalar single-precision and double-precision sz=0\n\n:facge Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:1 = abs(Rn_FPR32) f>= abs(Rm_FPR32);\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e20ec00/mask=xffa0fc00\n# CONSTRUCT x7e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2\n# AUNIT --inst x7e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop\n# Scalar single-precision and double-precision sz=1\n\n:facge Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = abs(Rn_FPR64) f>= abs(Rm_FPR64);\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e402c00/mask=xbfe0fc00\n# CONSTRUCT x2e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2\n# AUNIT --inst x2e402c00/mask=xffe0fc00 --rand hfp --status noqemu\n# FACGE SIMD 4H when size=0 Q=0\n\n:facge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(abs(Rn_VPR64.4H[0,16]) f>= abs(Rm_VPR64.4H[0,16])) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(abs(Rn_VPR64.4H[16,16]) f>= abs(Rm_VPR64.4H[16,16])) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(abs(Rn_VPR64.4H[32,16]) f>= abs(Rm_VPR64.4H[32,16])) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(abs(Rn_VPR64.4H[48,16]) f>= abs(Rm_VPR64.4H[48,16])) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e402c00/mask=xbfe0fc00\n# CONSTRUCT x6e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2\n# AUNIT --inst x6e402c00/mask=xffe0fc00 --rand hfp --status noqemu\n# FACGE SIMD 8H when size=0 Q=1\n\n:facge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(abs(Rn_VPR128.8H[0,16]) f>= abs(Rm_VPR128.8H[0,16])) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(abs(Rn_VPR128.8H[16,16]) f>= abs(Rm_VPR128.8H[16,16])) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(abs(Rn_VPR128.8H[32,16]) f>= abs(Rm_VPR128.8H[32,16])) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(abs(Rn_VPR128.8H[48,16]) f>= abs(Rm_VPR128.8H[48,16])) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(abs(Rn_VPR128.8H[64,16]) f>= abs(Rm_VPR128.8H[64,16])) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(abs(Rn_VPR128.8H[80,16]) f>= abs(Rm_VPR128.8H[80,16])) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(abs(Rn_VPR128.8H[96,16]) f>= abs(Rm_VPR128.8H[96,16])) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(abs(Rn_VPR128.8H[112,16]) f>= abs(Rm_VPR128.8H[112,16])) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00\n# CONSTRUCT x6ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@8\n# AUNIT --inst x6ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop\n\n:facgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(abs(Rn_VPR128.2D[0,64]) f> abs(Rm_VPR128.2D[0,64])) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(abs(Rn_VPR128.2D[64,64]) f> abs(Rm_VPR128.2D[64,64])) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00\n# CONSTRUCT x2ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4\n# AUNIT --inst x2ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop\n\n:facgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(abs(Rn_VPR64.2S[0,32]) f> abs(Rm_VPR64.2S[0,32])) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(abs(Rn_VPR64.2S[32,32]) f> abs(Rm_VPR64.2S[32,32])) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00\n# CONSTRUCT x6ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4\n# AUNIT --inst x6ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop\n\n:facgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(abs(Rn_VPR128.4S[0,32]) f> abs(Rm_VPR128.4S[0,32])) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(abs(Rn_VPR128.4S[32,32]) f> abs(Rm_VPR128.4S[32,32])) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(abs(Rn_VPR128.4S[64,32]) f> abs(Rm_VPR128.4S[64,32])) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(abs(Rn_VPR128.4S[96,32]) f> abs(Rm_VPR128.4S[96,32])) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ec02c00/mask=xffe0fc00\n# CONSTRUCT x7ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2\n# AUNIT --inst x7ec02c00/mask=xffe0fc00 --rand hfp --status noqemu\n# Scalar half precision\n\n:facgt Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01111110110 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:1 = abs(Rn_FPR16) f> abs(Rm_FPR16);\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ea0ec00/mask=xffa0fc00\n# CONSTRUCT x7ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2\n# AUNIT --inst x7ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop\n# Scalar single-precision and double-precision sz=0\n\n:facgt Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:1 = abs(Rn_FPR32) f> abs(Rm_FPR32);\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ea0ec00/mask=xffa0fc00\n# CONSTRUCT x7ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2\n# AUNIT --inst x7ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop\n# Scalar single-precision and double-precision sz=1\n\n:facgt Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = abs(Rn_FPR64) f> abs(Rm_FPR64);\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ec02c00/mask=xbfe0fc00\n# CONSTRUCT x2ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2\n# AUNIT --inst x2ec02c00/mask=xffe0fc00 --rand hfp --status noqemu\n# Vector half-precision SIMD 4H when Q=0\n\n:facgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(abs(Rn_VPR64.4H[0,16]) f> abs(Rm_VPR64.4H[0,16])) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(abs(Rn_VPR64.4H[16,16]) f> abs(Rm_VPR64.4H[16,16])) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(abs(Rn_VPR64.4H[32,16]) f> abs(Rm_VPR64.4H[32,16])) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(abs(Rn_VPR64.4H[48,16]) f> abs(Rm_VPR64.4H[48,16])) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ec02c00/mask=xbfe0fc00\n# CONSTRUCT x6ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2\n# AUNIT --inst x6ec02c00/mask=xffe0fc00 --rand hfp --status noqemu\n# Vector half-precision SIMD 8H when Q=1\n\n:facgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(abs(Rn_VPR128.8H[0,16]) f> abs(Rm_VPR128.8H[0,16])) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(abs(Rn_VPR128.8H[16,16]) f> abs(Rm_VPR128.8H[16,16])) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(abs(Rn_VPR128.8H[32,16]) f> abs(Rm_VPR128.8H[32,16])) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(abs(Rn_VPR128.8H[48,16]) f> abs(Rm_VPR128.8H[48,16])) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(abs(Rn_VPR128.8H[64,16]) f> abs(Rm_VPR128.8H[64,16])) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(abs(Rn_VPR128.8H[80,16]) f> abs(Rm_VPR128.8H[80,16])) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(abs(Rn_VPR128.8H[96,16]) f> abs(Rm_VPR128.8H[96,16])) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(abs(Rn_VPR128.8H[112,16]) f> abs(Rm_VPR128.8H[112,16])) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00\n# CONSTRUCT x4e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@8\n# AUNIT --inst x4e60d400/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D f+ Rm_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f+ Rm_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f+ Rm_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00\n# CONSTRUCT x0e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4\n# AUNIT --inst x0e20d400/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S f+ Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f+ Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f+ Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00\n# CONSTRUCT x4e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4\n# AUNIT --inst x4e20d400/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S f+ Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f+ Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f+ Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f+ Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f+ Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e401400/mask=xbfe0fc00\n# CONSTRUCT x0e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2\n# AUNIT --inst x0e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision SIMD 4H when Q=0\n\n:fadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f+ Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f+ Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f+ Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f+ Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f+ Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e401400/mask=xbfe0fc00\n# CONSTRUCT x4e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2\n# AUNIT --inst x4e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision SIMD 8H when Q=1\n\n:fadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f+ Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f+ Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f+ Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f+ Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f+ Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f+ Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f+ Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f+ Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f+ Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00\n# CONSTRUCT x1e602800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2\n# AUNIT --inst x1e602800/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fadd Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x2 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64 f+ Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00\n# CONSTRUCT x1ee02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2\n# AUNIT --inst x1ee02800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fadd Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x2 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16 f+ Rm_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00\n# CONSTRUCT x1e202800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2\n# AUNIT --inst x1e202800/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fadd Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x2 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32 f+ Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x7e30d800/mask=xffbffc00\n# CONSTRUCT x7e70d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =#f+\n# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@8\n# AUNIT --inst x7e70d800/mask=xfffffc00 --rand dfp --status pass --comment \"nofpround\"\n\n:faddp Rd_FPR64, Rn_VPR128.2D\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd\n{\n\t# sipd infix Rd_FPR64 = f+(Rn_VPR128.2D) on pairs lane size (8 to 8)\n\tlocal tmp1 = Rn_VPR128.2D[0,64];\n\tlocal tmp2 = Rn_VPR128.2D[64,64];\n\tRd_FPR64 = tmp1 f+ tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x7e30d800/mask=xffbffc00\n# CONSTRUCT x7e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =#f+\n# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@4\n# AUNIT --inst x7e30d800/mask=xfffffc00 --rand sfp --status pass --comment \"nofpround\"\n\n:faddp Rd_FPR32, Rn_VPR64.2S\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd\n{\n\t# sipd infix Rd_FPR32 = f+(Rn_VPR64.2S) on pairs lane size (4 to 4)\n\tlocal tmp1 = Rn_VPR64.2S[0,32];\n\tlocal tmp2 = Rn_VPR64.2S[32,32];\n\tRd_FPR32 = tmp1 f+ tmp2;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x5e30d800/mask=xffbffc00\n# CONSTRUCT x5e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_FPR32 =#f+@2\n# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_faddp/1@2\n# AUNIT --inst x5e30d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant\n\n:faddp Rd_FPR16, vRn_VPR128^\".2H\"\nis b_1031=0b0101111000110000110110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd\n{\n\t# sipd infix Rd_FPR16 = f+(Rn_FPR32) on pairs lane size (2 to 2)\n\tlocal tmp1 = Rn_FPR32[0,16];\n\tlocal tmp2 = Rn_FPR32[16,16];\n\tRd_FPR16 = tmp1 f+ tmp2;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00\n# CONSTRUCT x6e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@8\n# AUNIT --inst x6e60d400/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:faddp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = f+(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8)\n\tlocal tmp2 = Rn_VPR128.2D[0,64];\n\tlocal tmp3 = Rn_VPR128.2D[64,64];\n\tTMPQ1[0,64] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.2D[0,64];\n\ttmp3 = Rm_VPR128.2D[64,64];\n\tTMPQ1[64,64] = tmp2 f+ tmp3;\n\tRd_VPR128.2D = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00\n# CONSTRUCT x2e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 ARG3 =#f+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4\n# AUNIT --inst x2e20d400/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:faddp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = f+(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4)\n\tlocal tmp2 = Rn_VPR64.2S[0,32];\n\tlocal tmp3 = Rn_VPR64.2S[32,32];\n\tTMPD1[0,32] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR64.2S[0,32];\n\ttmp3 = Rm_VPR64.2S[32,32];\n\tTMPD1[32,32] = tmp2 f+ tmp3;\n\tRd_VPR64.2S = TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00\n# CONSTRUCT x6e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4\n# AUNIT --inst x6e20d400/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:faddp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = f+(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4)\n\tlocal tmp2 = Rn_VPR128.4S[0,32];\n\tlocal tmp3 = Rn_VPR128.4S[32,32];\n\tTMPQ1[0,32] = tmp2 f+ tmp3;\n\ttmp2 = Rn_VPR128.4S[64,32];\n\ttmp3 = Rn_VPR128.4S[96,32];\n\tTMPQ1[32,32] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.4S[0,32];\n\ttmp3 = Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.4S[64,32];\n\ttmp3 = Rm_VPR128.4S[96,32];\n\tTMPQ1[96,32] = tmp2 f+ tmp3;\n\tRd_VPR128.4S = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e401400/mask=xbfe0fc00\n# CONSTRUCT x2e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG3 ARG2 =#f+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2\n# AUNIT --inst x2e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision SIMD 4H when Q = 0\n\n:faddp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = f+(Rm_VPR64.4H,Rn_VPR64.4H) on pairs lane size (2 to 2)\n\tlocal tmp2 = Rm_VPR64.4H[0,16];\n\tlocal tmp3 = Rm_VPR64.4H[16,16];\n\tTMPD1[0,16] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR64.4H[32,16];\n\ttmp3 = Rm_VPR64.4H[48,16];\n\tTMPD1[16,16] = tmp2 f+ tmp3;\n\ttmp2 = Rn_VPR64.4H[0,16];\n\ttmp3 = Rn_VPR64.4H[16,16];\n\tTMPD1[32,16] = tmp2 f+ tmp3;\n\ttmp2 = Rn_VPR64.4H[32,16];\n\ttmp3 = Rn_VPR64.4H[48,16];\n\tTMPD1[48,16] = tmp2 f+ tmp3;\n\tRd_VPR64.4H = TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e401400/mask=xbfe0fc00\n# CONSTRUCT x6e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2\n# AUNIT --inst x6e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision SIMD 8H when Q = 1\n\n:faddp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = f+(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2)\n\tlocal tmp2 = Rn_VPR128.8H[0,16];\n\tlocal tmp3 = Rn_VPR128.8H[16,16];\n\tTMPQ1[0,16] = tmp2 f+ tmp3;\n\ttmp2 = Rn_VPR128.8H[32,16];\n\ttmp3 = Rn_VPR128.8H[48,16];\n\tTMPQ1[16,16] = tmp2 f+ tmp3;\n\ttmp2 = Rn_VPR128.8H[64,16];\n\ttmp3 = Rn_VPR128.8H[80,16];\n\tTMPQ1[32,16] = tmp2 f+ tmp3;\n\ttmp2 = Rn_VPR128.8H[96,16];\n\ttmp3 = Rn_VPR128.8H[112,16];\n\tTMPQ1[48,16] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.8H[0,16];\n\ttmp3 = Rm_VPR128.8H[16,16];\n\tTMPQ1[64,16] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.8H[32,16];\n\ttmp3 = Rm_VPR128.8H[48,16];\n\tTMPQ1[80,16] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.8H[64,16];\n\ttmp3 = Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = tmp2 f+ tmp3;\n\ttmp2 = Rm_VPR128.8H[96,16];\n\ttmp3 = Rm_VPR128.8H[112,16];\n\tTMPQ1[112,16] = tmp2 f+ tmp3;\n\tRd_VPR128.8H = TMPQ1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.46 FCADD page C7-1090 line 63037 KEEPWITH\n# val is either 90 or 270 depending on the value of bit b_12 (0 or 1)\nfcadd_rotate: \"#\"^val is b_12 [ val = 90 + 180 * b_12; ] { export *[const]:2 val; }\n\n# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00\n# CONSTRUCT x2e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2\n# AUNIT --inst x2e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment \"nofpround\"\n# FCADD SIMD 4H when size = 01 , Q = 0\n\n:fcadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fcadd(Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate, 2:1);\n}\n\n# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00\n# CONSTRUCT x6e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2\n# AUNIT --inst x6e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment \"nofpround\"\n# FCADD SIMD 8H when size = 01 , Q = 1\n\n:fcadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fcadd(Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate, 2:1);\n}\n\n# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00\n# CONSTRUCT x2e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4\n# AUNIT --inst x2e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment \"nofpround\"\n# FCADD SIMD 2S when size = 10 , Q = 0\n\n:fcadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fcadd(Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate, 4:1);\n}\n\n# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00\n# CONSTRUCT x6e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4\n# AUNIT --inst x6e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment \"nofpround\"\n# FCADD SIMD 4S when size = 10 , Q = 1\n\n:fcadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fcadd(Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate, 4:1);\n}\n\n# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00\n# CONSTRUCT x6ec0e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@8\n# AUNIT --inst x6ec0e400/mask=xffe0ec00 --rand dfp --status noqemu --comment \"nofpround\"\n# FCADD SIMD 2D when size = 11 , Q = 1\n\n:fcadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fcadd(Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate, 8:1);\n}\n\n# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10\n# CONSTRUCT x1e600400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4\n# AUNIT --inst x1e600400/mask=xffe00c10 --rand dfp --status nodest --comment \"flags\"\n\n:fccmp Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=0 & NZCVImm_uimm4\n{\n\tlocal tmp1:1 = ! CondOp:1;\n\tsetCC_NZCV(NZCVImm_uimm4:1);\n\tif (tmp1) goto inst_next;\n\tftestNAN(Rn_FPR64, Rm_FPR64);\n\tfcomp(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10\n# CONSTRUCT x1e200400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4\n# AUNIT --inst x1e200400/mask=xffe00c10 --rand sfp --status nodest --comment \"flags\"\n\n:fccmp Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=0 & NZCVImm_uimm4\n{\n\tlocal tmp1:1 = ! CondOp:1;\n\tsetCC_NZCV(NZCVImm_uimm4:1);\n\tif (tmp1) goto inst_next;\n\tftestNAN(Rn_FPR32, Rm_FPR32);\n\tfcomp(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10\n# CONSTRUCT x1ee00400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4\n# AUNIT --inst x1ee00400/mask=xffe00c10 --rand hfp --status nodest --comment \"flags\"\n\n:fccmp Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=0 & NZCVImm_uimm4\n{\n\tlocal tmp1:1 = ! CondOp:1;\n\tsetCC_NZCV(NZCVImm_uimm4:1);\n\tif (tmp1) goto inst_next;\n\tftestNAN(Rn_FPR16, Rm_FPR16);\n\tfcomp(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10\n# CONSTRUCT x1e600410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4\n# AUNIT --inst x1e600410/mask=xffe00c10 --rand dfp --status nodest --comment \"flags\"\n\n:fccmpe Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=1 & NZCVImm_uimm4\n{\n\tlocal tmp1:1 = ! CondOp:1;\n\tsetCC_NZCV(NZCVImm_uimm4:1);\n\tif (tmp1) goto inst_next;\n\tftestNAN(Rn_FPR64, Rm_FPR64);\n\tfcomp(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10\n# CONSTRUCT x1e200410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4\n# AUNIT --inst x1e200410/mask=xffe00c10 --rand sfp --status nodest --comment \"flags\"\n\n:fccmpe Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=1 & NZCVImm_uimm4\n{\n\tlocal tmp1:1 = ! CondOp:1;\n\tsetCC_NZCV(NZCVImm_uimm4:1);\n\tif (tmp1) goto inst_next;\n\tftestNAN(Rn_FPR32, Rm_FPR32);\n\tfcomp(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10\n# CONSTRUCT x1ee00410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4\n# AUNIT --inst x1ee00410/mask=xffe00c10 --rand hfp --status nodest --comment \"flags\"\n\n:fccmpe Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=1 & NZCVImm_uimm4\n{\n\tlocal tmp1:1 = ! CondOp:1;\n\tsetCC_NZCV(NZCVImm_uimm4:1);\n\tif (tmp1) goto inst_next;\n\tftestNAN(Rn_FPR16, Rm_FPR16);\n\tfcomp(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00\n# CONSTRUCT x4e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@8\n# AUNIT --inst x4e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f== Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f== Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00\n# CONSTRUCT x0e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4\n# AUNIT --inst x0e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f== Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f== Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00\n# CONSTRUCT x4e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4\n# AUNIT --inst x4e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f== Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f== Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f== Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f== Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e402400/mask=xffe0fc00\n# CONSTRUCT x5e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2\n# AUNIT --inst x5e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmeq Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01011110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f== Rm_FPR16;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e20e400/mask=xffa0fc00\n# CONSTRUCT x5e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2\n# AUNIT --inst x5e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision variant sz=0\n\n:fcmeq Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_2331=0b010111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f== Rm_FPR32;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e20e400/mask=xffa0fc00\n# CONSTRUCT x5e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2\n# AUNIT --inst x5e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision variant sz=1\n\n:fcmeq Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2331=0b010111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f== Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e402400/mask=xbfe0fc00\n# CONSTRUCT x0e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2\n# AUNIT --inst x0e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q=0\n\n:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f== Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f== Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f== Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f== Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e402400/mask=xbfe0fc00\n# CONSTRUCT x4e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2\n# AUNIT --inst x4e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q=1\n\n:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f== Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f== Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f== Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f== Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f== Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f== Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f== Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] == Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00\n# CONSTRUCT x4ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2@8\n# AUNIT --inst x4ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, \"#0.0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f== zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f== zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00\n# CONSTRUCT x0ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4\n# AUNIT --inst x0ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, \"#0.0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f== zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f== zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00\n# CONSTRUCT x4ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4\n# AUNIT --inst x4ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, \"#0.0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f== zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f== zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f== zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f== zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ef8d800/mask=xfffffc00\n# CONSTRUCT x5ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2\n# AUNIT --inst x5ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmeq Rd_FPR16, Rn_FPR16, \"#0.0\"\nis b_1031=0b0101111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f== 0;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ea0d800/mask=xffbffc00\n# CONSTRUCT x5ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2\n# AUNIT --inst x5ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=0\n\n:fcmeq Rd_FPR32, Rn_FPR32, \"#0.0\"\nis b_2331=0b010111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f== 0;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ea0d800/mask=xffbffc00\n# CONSTRUCT x5ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2\n# AUNIT --inst x5ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=1\n\n:fcmeq Rd_FPR64, Rn_FPR64, \"#0.0\"\nis b_2331=0b010111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f== 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ef8d800/mask=xbffffc00\n# CONSTRUCT x0ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2\n# AUNIT --inst x0ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, \"#0.0\"\nis b_31=0 & b_30=0 & b_1029=0b00111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f== zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f== zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f== zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f== zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ef8d800/mask=xbffffc00\n# CONSTRUCT x4ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2\n# AUNIT --inst x4ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, \"#0.0\"\nis b_31=0 & b_30=1 & b_1029=0b00111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f== zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f== zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f== zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f== zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f== zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f== zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f== zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f== zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00\n# CONSTRUCT x6e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@8\n# AUNIT --inst x6e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f>= Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f>= Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00\n# CONSTRUCT x2e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4\n# AUNIT --inst x2e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f>= Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f>= Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00\n# CONSTRUCT x6e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4\n# AUNIT --inst x6e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f>= Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f>= Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f>= Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f>= Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e402400/mask=xffe0fc00\n# CONSTRUCT x7e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2\n# AUNIT --inst x7e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmge Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01111110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f>= Rm_FPR16;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e20e400/mask=xffa0fc00\n# CONSTRUCT x7e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2\n# AUNIT --inst x7e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision variant sz=0\n\n:fcmge Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f>= Rm_FPR32;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e20e400/mask=xffa0fc00\n# CONSTRUCT x7e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2\n# AUNIT --inst x7e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision variant sz=1\n\n:fcmge Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f>= Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e402400/mask=xbfe0fc00\n# CONSTRUCT x2e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2\n# AUNIT --inst x2e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f>= Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f>= Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f>= Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f>= Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e402400/mask=xbfe0fc00\n# CONSTRUCT x6e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2\n# AUNIT --inst x6e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f>= Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f>= Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f>= Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f>= Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f>= Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f>= Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f>= Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f>= Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00\n# CONSTRUCT x6ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2@8\n# AUNIT --inst x6ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmge Rd_VPR128.2D, Rn_VPR128.2D, \"#0.0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f>= zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00\n# CONSTRUCT x2ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4\n# AUNIT --inst x2ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmge Rd_VPR64.2S, Rn_VPR64.2S, \"#0.0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f>= zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f>= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00\n# CONSTRUCT x6ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4\n# AUNIT --inst x6ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmge Rd_VPR128.4S, Rn_VPR128.4S, \"#0.0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f>= zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f>= zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f>= zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ef8c800/mask=xfffffc00\n# CONSTRUCT x7ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2\n# AUNIT --inst x7ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmge Rd_FPR16, Rn_FPR16, \"#0.0\"\nis b_1031=0b0111111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f>= 0;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ea0c800/mask=xffbffc00\n# CONSTRUCT x7ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2\n# AUNIT --inst x7ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=0\n\n:fcmge Rd_FPR32, Rn_FPR32, \"#0.0\"\nis b_2331=0b011111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f>= 0;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ea0c800/mask=xffbffc00\n# CONSTRUCT x7ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2\n# AUNIT --inst x7ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=1\n\n:fcmge Rd_FPR64, Rn_FPR64, \"#0.0\"\nis b_2331=0b011111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f>= 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ef8c800/mask=xbffffc00\n# CONSTRUCT x2ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2\n# AUNIT --inst x2ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmge Rd_VPR64.4H, Rn_VPR64.4H, \"#0.0\"\nis b_31=0 & b_30=0 & b_1029=0b10111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f>= zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f>= zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f>= zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f>= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ef8c800/mask=xbffffc00\n# CONSTRUCT x6ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2\n# AUNIT --inst x6ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmge Rd_VPR128.8H, Rn_VPR128.8H, \"#0.0\"\nis b_31=0 & b_30=1 & b_1029=0b10111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f>= zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f>= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00\n# CONSTRUCT x6ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@8\n# AUNIT --inst x6ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f> Rm_VPR128.2D[0,64]) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f> Rm_VPR128.2D[64,64]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00\n# CONSTRUCT x2ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4\n# AUNIT --inst x2ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f> Rm_VPR64.2S[0,32]) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f> Rm_VPR64.2S[32,32]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00\n# CONSTRUCT x6ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4\n# AUNIT --inst x6ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f> Rm_VPR128.4S[0,32]) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f> Rm_VPR128.4S[32,32]) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f> Rm_VPR128.4S[64,32]) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f> Rm_VPR128.4S[96,32]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ec02400/mask=xffe0fc00\n# CONSTRUCT x7ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2\n# AUNIT --inst x7ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmgt Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01111110110 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f> Rm_FPR16;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ea0e400/mask=xffa0fc00\n# CONSTRUCT x7ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2\n# AUNIT --inst x7ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision variant sz=0\n\n:fcmgt Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f> Rm_FPR32;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ea0e400/mask=xffa0fc00\n# CONSTRUCT x7ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2\n# AUNIT --inst x7ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision variant sz=1\n\n:fcmgt Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f> Rm_FPR64;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ec02400/mask=xbfe0fc00\n# CONSTRUCT x2ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2\n# AUNIT --inst x2ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f> Rm_VPR64.4H[0,16]) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f> Rm_VPR64.4H[16,16]) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f> Rm_VPR64.4H[32,16]) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f> Rm_VPR64.4H[48,16]) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ec02400/mask=xbfe0fc00\n# CONSTRUCT x6ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2\n# AUNIT --inst x6ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f> Rm_VPR128.8H[0,16]) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f> Rm_VPR128.8H[16,16]) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f> Rm_VPR128.8H[32,16]) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f> Rm_VPR128.8H[48,16]) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f> Rm_VPR128.8H[64,16]) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f> Rm_VPR128.8H[80,16]) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f> Rm_VPR128.8H[96,16]) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f> Rm_VPR128.8H[112,16]) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00\n# CONSTRUCT x4ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2@8\n# AUNIT --inst x4ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, \"#0.0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f> zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00\n# CONSTRUCT x0ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4\n# AUNIT --inst x0ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, \"#0.0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f> zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f> zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00\n# CONSTRUCT x4ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4\n# AUNIT --inst x4ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, \"#0.0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f> zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f> zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f> zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ef8c800/mask=xfffffc00\n# CONSTRUCT x5ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2\n# AUNIT --inst x5ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmgt Rd_FPR16, Rn_FPR16, \"#0.0\"\nis b_1031=0b0101111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f> 0;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ea0c800/mask=xffbffc00\n# CONSTRUCT x5ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2\n# AUNIT --inst x5ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=0\n\n:fcmgt Rd_FPR32, Rn_FPR32, \"#0.0\"\nis b_2331=0b010111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f> 0;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ea0c800/mask=xffbffc00\n# CONSTRUCT x5ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2\n# AUNIT --inst x5ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=1\n\n:fcmgt Rd_FPR64, Rn_FPR64, \"#0.0\"\nis b_2331=0b010111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f> 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ef8c800/mask=xbffffc00\n# CONSTRUCT x0ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2\n# AUNIT --inst x0ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, \"#0.0\"\nis b_31=0 & b_30=0 & b_1029=0b00111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f> zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f> zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f> zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f> zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ef8c800/mask=xbffffc00\n# CONSTRUCT x4ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2\n# AUNIT --inst x4ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, \"#0.0\"\nis b_31=0 & b_30=1 & b_1029=0b00111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f> zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f> zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f> zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f> zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f> zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f> zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f> zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f> zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.55 FCMLA (by element) page C7-1117 line 64749 KEEPWITH\n# Values in set {0,90,180,270} depending on b_1314/1112 values of {0,1,2,3}\nfcmla_rotate: \"#\"^val is b_15=0 & b_1314 [ val = 90 * b_1314; ] { export *[const]:2 val; }\nfcmla_rotate: \"#\"^val is b_15=1 & b_1112 [ val = 90 * b_1112; ] { export *[const]:2 val; }\n\n# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400\n# CONSTRUCT x2f401000/mask=xffc09c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2\n# AUNIT --inst x2f401000/mask=xffc09c00 --rand hfp --status noqemu --comment \"noflags\"\n# The representation of Rm in the documentation as a 4 bit field\n# extended by M actually makes it a standard 5 bit field.\n# 4H variant when size = 01 , Q = 0 T=VPR64.4H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL\n# NOTE: if size == '01' and H == '1' && Q == '0' then ReservedValue();\n\n:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128.H.vIndexHL, fcmla_rotate\nis b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_11=0 & b_10=0 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd\n{\n\tlocal tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1);\n\tRd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, tmp1, fcmla_rotate, 2:1);\n}\n\n# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400\n# CONSTRUCT x6f401000/mask=xffc09400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2\n# AUNIT --inst x6f401000/mask=xffc09400 --rand hfp --status noqemu --comment \"noflags\"\n# 8H variant when size = 01 , Q = 1 T=VPR128.8H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL\n\n:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128.H.vIndexHL, fcmla_rotate\nis b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd\n{\n\tlocal tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1);\n\tRd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, tmp1, fcmla_rotate, 2:1);\n}\n\n# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400\n# CONSTRUCT x6f801000/mask=xffe09400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4\n# AUNIT --inst x6f801000/mask=xffe09400 --rand sfp --status noqemu --comment \"noflags\"\n# 4S variant when size = 10 , Q = 1 T=VPR128.4S imm=Re_VPR128.S.vIndex i1=Re_VPR128.S i2=vIndex\n# NOTE: if size == '10' and (L == '1' || Q == '0') then ReservedValue();\n\n:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex, fcmla_rotate\nis b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_21=0 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);\n\tRd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, tmp1, fcmla_rotate, 4:1);\n}\n\n# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400\n# CONSTRUCT x2e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4\n# AUNIT --inst x2e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment \"noflags\"\n# FCMLA SIMD 4H when size = 01 , Q = 0\n\n:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate, 4:1);\n}\n\n# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400\n# CONSTRUCT x6e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4\n# AUNIT --inst x6e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment \"noflags\"\n# FCMLA SIMD 8H when size = 01 , Q = 1\n\n:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate, 4:1);\n}\n\n# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400\n# CONSTRUCT x2e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4\n# AUNIT --inst x2e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment \"noflags\"\n# FCMLA SIMD 2S when size = 10 , Q = 0\n\n:fcmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fcmla(Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate, 4:1);\n}\n\n# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400\n# CONSTRUCT x6e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4\n# AUNIT --inst x6e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment \"noflags\"\n# FCMLA SIMD 4S when size = 10 , Q = 1\n\n:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate, 4:1);\n}\n\n# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400\n# CONSTRUCT x6ec0c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4\n# AUNIT --inst x6ec0c400/mask=xffe0e400 --rand dfp --status noqemu --comment \"noflags\"\n# FCMLA SIMD 2D when size = 11 , Q = 1\n\n:fcmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fcmla(Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate, 4:1);\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00\n# CONSTRUCT x6ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2@8\n# AUNIT --inst x6ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmle Rd_VPR128.2D, Rn_VPR128.2D, \"#0.0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f<= zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00\n# CONSTRUCT x2ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2\n# AUNIT --inst x2ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmle Rd_VPR64.2S, Rn_VPR64.2S, \"#0.0\"\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f<= zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f<= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00\n# CONSTRUCT x6ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2@4\n# AUNIT --inst x6ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop\n\n:fcmle Rd_VPR128.4S, Rn_VPR128.4S, \"#0.0\"\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f<= zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f<= zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f<= zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ef8d800/mask=xfffffc00\n# CONSTRUCT x7ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2\n# AUNIT --inst x7ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmle Rd_FPR16, Rn_FPR16, \"#0.0\"\nis b_1031=0b0111111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f<= 0;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ea0d800/mask=xffbffc00\n# CONSTRUCT x7ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2\n# AUNIT --inst x7ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=0\n\n:fcmle Rd_FPR32, Rn_FPR32, \"#0.0\"\nis b_2331=0b011111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f<= 0;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ea0d800/mask=xffbffc00\n# CONSTRUCT x7ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2\n# AUNIT --inst x7ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=1\n\n:fcmle Rd_FPR64, Rn_FPR64, \"#0.0\"\nis b_2331=0b011111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f<= 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ef8d800/mask=xbffffc00\n# CONSTRUCT x2ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2\n# AUNIT --inst x2ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmle Rd_VPR64.4H, Rn_VPR64.4H, \"#0.0\"\nis b_31=0 & b_30=0 & b_1029=0b10111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f<= zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f<= zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f<= zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f<= zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ef8d800/mask=xbffffc00\n# CONSTRUCT x6ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2\n# AUNIT --inst x6ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmle Rd_VPR128.8H, Rn_VPR128.8H, \"#0.0\"\nis b_31=0 & b_30=1 & b_1029=0b10111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f<= zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f<= zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00\n# CONSTRUCT x4ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2@8\n# AUNIT --inst x4ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n\n:fcmlt Rd_VPR128.2D, Rn_VPR128.2D, \"#0.0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xe & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal eqVal:8 = ~ 0;\n\tlocal zero:8 = 0;\n\tRd_VPR128.2D[0,64] = zext(Rn_VPR128.2D[0,64] f< zero) * eqVal;\n\tRd_VPR128.2D[64,64] = zext(Rn_VPR128.2D[64,64] f< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00\n# CONSTRUCT x0ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4\n# AUNIT --inst x0ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmlt Rd_VPR64.2S, Rn_VPR64.2S, \"#0.0\"\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR64.2S[0,32] = zext(Rn_VPR64.2S[0,32] f< zero) * eqVal;\n\tRd_VPR64.2S[32,32] = zext(Rn_VPR64.2S[32,32] f< zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00\n# CONSTRUCT x4ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4\n# AUNIT --inst x4ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n\n:fcmlt Rd_VPR128.4S, Rn_VPR128.4S, \"#0.0\"\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal eqVal:4 = ~ 0;\n\tlocal zero:4 = 0;\n\tRd_VPR128.4S[0,32] = zext(Rn_VPR128.4S[0,32] f< zero) * eqVal;\n\tRd_VPR128.4S[32,32] = zext(Rn_VPR128.4S[32,32] f< zero) * eqVal;\n\tRd_VPR128.4S[64,32] = zext(Rn_VPR128.4S[64,32] f< zero) * eqVal;\n\tRd_VPR128.4S[96,32] = zext(Rn_VPR128.4S[96,32] f< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ef8e800/mask=xfffffc00\n# CONSTRUCT x5ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2\n# AUNIT --inst x5ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Scalar half precision variant\n\n:fcmlt Rd_FPR16, Rn_FPR16, \"#0.0\"\nis b_1031=0b0101111011111000111010 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR16 f< 0;\n\tlocal tmp2:2 = zext(tmp1);\n\tlocal tmp3:2 = ~ 0:2;\n\tRd_FPR16 = tmp2 * tmp3;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ea0e800/mask=xffbffc00\n# CONSTRUCT x5ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2\n# AUNIT --inst x5ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=0\n\n:fcmlt Rd_FPR32, Rn_FPR32, \"#0.0\"\nis b_2331=0b010111101 & b_22=0 & b_1021=0b100000111010 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR32 f< 0;\n\tlocal tmp2:4 = zext(tmp1);\n\tlocal tmp3:4 = ~ 0:4;\n\tRd_FPR32 = tmp2 * tmp3;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ea0e800/mask=xffbffc00\n# CONSTRUCT x5ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2\n# AUNIT --inst x5ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"noflags\"\n# Scalar single-precision and double-precision sz=1\n\n:fcmlt Rd_FPR64, Rn_FPR64, \"#0.0\"\nis b_2331=0b010111101 & b_22=1 & b_1021=0b100000111010 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tlocal tmp1:1 = Rn_FPR64 f< 0;\n\tlocal tmp2:8 = zext(tmp1);\n\tlocal tmp3:8 = ~ 0:8;\n\tRd_FPR64 = tmp2 * tmp3;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ef8e800/mask=xbffffc00\n# CONSTRUCT x0ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2\n# AUNIT --inst x0ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 4H when Q = 0\n\n:fcmlt Rd_VPR64.4H, Rn_VPR64.4H, \"#0.0\"\nis b_31=0 & b_30=0 & b_1029=0b00111011111000111010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR64.4H[0,16] = zext(Rn_VPR64.4H[0,16] f< zero) * eqVal;\n\tRd_VPR64.4H[16,16] = zext(Rn_VPR64.4H[16,16] f< zero) * eqVal;\n\tRd_VPR64.4H[32,16] = zext(Rn_VPR64.4H[32,16] f< zero) * eqVal;\n\tRd_VPR64.4H[48,16] = zext(Rn_VPR64.4H[48,16] f< zero) * eqVal;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ef8e800/mask=xbffffc00\n# CONSTRUCT x4ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2\n# AUNIT --inst x4ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment \"noflags\"\n# Vector half precision variant SIMD 8H when Q = 1\n\n:fcmlt Rd_VPR128.8H, Rn_VPR128.8H, \"#0.0\"\nis b_31=0 & b_30=1 & b_1029=0b00111011111000111010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tlocal eqVal:2 = ~ 0;\n\tlocal zero:2 = 0;\n\tRd_VPR128.8H[0,16] = zext(Rn_VPR128.8H[0,16] f< zero) * eqVal;\n\tRd_VPR128.8H[16,16] = zext(Rn_VPR128.8H[16,16] f< zero) * eqVal;\n\tRd_VPR128.8H[32,16] = zext(Rn_VPR128.8H[32,16] f< zero) * eqVal;\n\tRd_VPR128.8H[48,16] = zext(Rn_VPR128.8H[48,16] f< zero) * eqVal;\n\tRd_VPR128.8H[64,16] = zext(Rn_VPR128.8H[64,16] f< zero) * eqVal;\n\tRd_VPR128.8H[80,16] = zext(Rn_VPR128.8H[80,16] f< zero) * eqVal;\n\tRd_VPR128.8H[96,16] = zext(Rn_VPR128.8H[96,16] f< zero) * eqVal;\n\tRd_VPR128.8H[112,16] = zext(Rn_VPR128.8H[112,16] f< zero) * eqVal;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17\n# CONSTRUCT x1e602000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2\n# AUNIT --inst x1e602000/mask=xffe0fc1f --rand dfp --status nodest --comment \"flags\"\n\n:fcmp Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x0\n{\n\tftestNAN(Rn_FPR64, Rm_FPR64);\n\tfcomp(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17\n# CONSTRUCT x1e602008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2\n# AUNIT --inst x1e602008/mask=xffe0fc1f --rand dfp --status nodest --comment \"flags\"\n\n:fcmp Rn_FPR64, Rm_fpz64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x8\n{\n\tftestNAN(Rn_FPR64, Rm_fpz64);\n\tfcomp(Rn_FPR64, Rm_fpz64);\n}\n\n# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17\n# CONSTRUCT x1e202008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2\n# AUNIT --inst x1e202008/mask=xffe0fc1f --rand sfp --status nodest --comment \"flags\"\n\n:fcmp Rn_FPR32, Rm_fpz32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x8\n{\n\tftestNAN(Rn_FPR32, Rm_fpz32);\n\tfcomp(Rn_FPR32, Rm_fpz32);\n}\n\n# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17\n# CONSTRUCT x1e202000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2\n# AUNIT --inst x1e202000/mask=xffe0fc1f --rand sfp --status nodest --comment \"flags\"\n\n:fcmp Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x0\n{\n\tftestNAN(Rn_FPR32, Rm_FPR32);\n\tfcomp(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17\n# CONSTRUCT x1ee02008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2\n# AUNIT --inst x1ee02008/mask=xffe0fc1f --rand hfp --status nodest --comment \"flags\"\n\n:fcmp Rn_FPR16, Rm_fpz16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x8\n{\n\tftestNAN(Rn_FPR16, Rm_fpz16);\n\tfcomp(Rn_FPR16, Rm_fpz16);\n}\n\n# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17\n# CONSTRUCT x1ee02000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2\n# AUNIT --inst x1ee02000/mask=xffe0fc1f --rand hfp --status nodest --comment \"flags\"\n\n:fcmp Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x0\n{\n\tftestNAN(Rn_FPR16, Rm_FPR16);\n\tfcomp(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17\n# CONSTRUCT x1e602010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2\n# AUNIT --inst x1e602010/mask=xffe0fc1f --rand dfp --status nodest --comment \"flags\"\n\n:fcmpe Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x10\n{\n\tftestNAN(Rn_FPR64, Rm_FPR64);\n\tfcomp(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17\n# CONSTRUCT x1e602018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2\n# AUNIT --inst x1e602018/mask=xffe0fc1f --rand dfp --status nodest --comment \"flags\"\n\n:fcmpe Rn_FPR64, Rm_fpz64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x18\n{\n\tftestNAN(Rn_FPR64, Rm_fpz64);\n\tfcomp(Rn_FPR64, Rm_fpz64);\n}\n\n# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17\n# CONSTRUCT x1e202018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2\n# AUNIT --inst x1e202018/mask=xffe0fc1f --rand sfp --status nodest --comment \"flags\"\n\n:fcmpe Rn_FPR32, Rm_fpz32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x18\n{\n\tftestNAN(Rn_FPR32, Rm_fpz32);\n\tfcomp(Rn_FPR32, Rm_fpz32);\n}\n\n# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17\n# CONSTRUCT x1e202010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2\n# AUNIT --inst x1e202010/mask=xffe0fc1f --rand sfp --status nodest --comment \"flags\"\n\n:fcmpe Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x10\n{\n\tftestNAN(Rn_FPR32, Rm_FPR32);\n\tfcomp(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17\n# CONSTRUCT x1ee02018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2\n# AUNIT --inst x1ee02018/mask=xffe0fc1f --rand hfp --status nodest --comment \"flags\"\n\n:fcmpe Rn_FPR16, Rm_fpz16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x18\n{\n\tftestNAN(Rn_FPR16, Rm_fpz16);\n\tfcomp(Rn_FPR16, Rm_fpz16);\n}\n\n# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17\n# CONSTRUCT x1ee02010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES\n# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2\n# AUNIT --inst x1ee02010/mask=xffe0fc1f --rand hfp --status nodest --comment \"flags\"\n\n:fcmpe Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x10\n{\n\tftestNAN(Rn_FPR16, Rm_FPR16);\n\tfcomp(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00\n# CONSTRUCT x1e600c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3\n# AUNIT --inst x1e600c00/mask=xffe00c00 --rand dfp --status pass --comment \"flags\"\n# Rm may be the same register as Rd, so it needs to be saved\n\n:fcsel Rd_FPR64, Rn_FPR64, Rm_FPR64, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=3 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = Rm_FPR64;\n\tRd_FPR64 = Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n\tif (CondOp:1) goto inst_next;\n\tRd_FPR64 = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00\n# CONSTRUCT x1e200c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3\n# AUNIT --inst x1e200c00/mask=xffe00c00 --rand sfp --status pass --comment \"flags\"\n\n:fcsel Rd_FPR32, Rn_FPR32, Rm_FPR32, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=3 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:4 = Rm_FPR32;\n\tRd_FPR32 = Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n\tif (CondOp:1) goto inst_next;\n\tRd_FPR32 = tmp1;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00\n# CONSTRUCT x1ee00c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3\n# AUNIT --inst x1ee00c00/mask=xffe00c00 --rand hfp --status noqemu --comment \"flags\"\n\n:fcsel Rd_FPR16, Rn_FPR16, Rm_FPR16, CondOp\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=3 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:2 = Rm_FPR16;\n\tRd_FPR16 = Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n\tif (CondOp:1) goto inst_next;\n\tRd_FPR16 = tmp1;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1ee2c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1\n# AUNIT --inst x1ee2c000/mask=xfffffc00 --rand hfp --status pass --comment \"nofpround\"\n\n:fcvt Rd_FPR64, Rn_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR16 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = float2float(Rn_FPR16);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1e22c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1\n# AUNIT --inst x1e22c000/mask=xfffffc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fcvt Rd_FPR64, Rn_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR32 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = float2float(Rn_FPR32);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1e63c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1\n# AUNIT --inst x1e63c000/mask=xfffffc00 --rand hfp --status pass --comment \"nofpround\"\n\n:fcvt Rd_FPR16, Rn_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR64 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = float2float(Rn_FPR64);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1e23c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1\n# AUNIT --inst x1e23c000/mask=xfffffc00 --rand hfp --status fail --comment \"nofpround\"\n\n:fcvt Rd_FPR16, Rn_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR32 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = float2float(Rn_FPR32);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1e624000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1\n# AUNIT --inst x1e624000/mask=xfffffc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fcvt Rd_FPR32, Rn_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR64 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = float2float(Rn_FPR64);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1ee24000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1\n# AUNIT --inst x1ee24000/mask=xfffffc00 --rand hfp --status pass --comment \"nofpround\"\n\n:fcvt Rd_FPR32, Rn_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR16 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = float2float(Rn_FPR16);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.63 FCVTAS (vector) page C7-1136 line 65961 KEEPWITH\n\nfcvt_vmnemonic: \"fcvtas\" is b_29=0 & b_23=0 & b_1314=0b10 & b_12=0 { }\nfcvt_vmnemonic: \"fcvtau\" is b_29=1 & b_23=0 & b_1314=0b10 & b_12=0 { }\nfcvt_vmnemonic: \"fcvtms\" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=1 { }\nfcvt_vmnemonic: \"fcvtmu\" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=1 { }\nfcvt_vmnemonic: \"fcvtns\" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=0 { }\nfcvt_vmnemonic: \"fcvtnu\" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=0 { }\nfcvt_vmnemonic: \"fcvtps\" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=0 { }\nfcvt_vmnemonic: \"fcvtpu\" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=0 { }\nfcvt_vmnemonic: \"fcvtzs\" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=1 { }\nfcvt_vmnemonic: \"fcvtzu\" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=1 { }\n\nfcvt_smnemonic: \"fcvtas\" is b_1920=0b00 & b_1618=0b100 { }\nfcvt_smnemonic: \"fcvtau\" is b_1920=0b00 & b_1618=0b101 { }\nfcvt_smnemonic: \"fcvtms\" is b_1920=0b10 & b_1618=0b000 { }\nfcvt_smnemonic: \"fcvtmu\" is b_1920=0b10 & b_1618=0b001 { }\nfcvt_smnemonic: \"fcvtns\" is b_1920=0b00 & b_1618=0b000 { }\nfcvt_smnemonic: \"fcvtnu\" is b_1920=0b00 & b_1618=0b001 { }\nfcvt_smnemonic: \"fcvtps\" is b_1920=0b01 & b_1618=0b000 { }\nfcvt_smnemonic: \"fcvtpu\" is b_1920=0b01 & b_1618=0b001 { }\nfcvt_smnemonic: \"fcvtzs\" is b_1920=0b11 & b_1618=0b000 { }\nfcvt_smnemonic: \"fcvtzu\" is b_1920=0b11 & b_1618=0b001 { }\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e79c800/mask=xfffffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e79c800/mask=xfffffc00\n# CONSTRUCT x5e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x5e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision\n\n:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16\nis b_3031=0b01 & b_1028=0b1111001111001110010 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = trunc(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e21c800/mask=xffbffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e21c800/mask=xffbffc00\n# CONSTRUCT x5e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x5e21c800/mask=xdffffc00 --rand sfp --status fail --comment \"nofpround\"\n# Scalar single-precision and double-precision variant sz=0\n\n:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32\nis b_3031=0b01 & b_2328=0b111100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = trunc(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e21c800/mask=xffbffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e21c800/mask=xffbffc00\n# CONSTRUCT x5e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x5e61c800/mask=xdffffc00 --rand dfp --status fail --comment \"nofpround\"\n# Scalar single-precision and double-precision variant sz=1\n\n:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64\nis b_3031=0b01 & b_2328=0b111100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = trunc(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e79c800/mask=xbffffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e79c800/mask=xbffffc00\n# CONSTRUCT x0e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2\n# AUNIT --inst x0e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant Q=0\n\n:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e79c800/mask=xbffffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e79c800/mask=xbffffc00\n# CONSTRUCT x4e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2\n# AUNIT --inst x4e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant Q=1\n\n:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00\n# CONSTRUCT x0e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4\n# AUNIT --inst x0e21c800/mask=xdffffc00 --rand sfp --status fail --comment \"nofpround\"\n# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0\n\n:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00\n# CONSTRUCT x4e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4\n# AUNIT --inst x4e21c800/mask=xdffffc00 --rand sfp --status fail --comment \"nofpround\"\n# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1\n\n:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00\n# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00\n# CONSTRUCT x4e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8\n# AUNIT --inst x4e61c800/mask=xdffffc00 --rand dfp --status fail --comment \"nofpround\"\n# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1\n\n:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2328=0b011100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00\n# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00\n# CONSTRUCT x1ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x1ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 32-bit variant when sf == 0 && type == 11\n\n:^fcvt_smnemonic Rd_GPR32, Rn_FPR16\nis b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR16);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00\n# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00\n# CONSTRUCT x9ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x9ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 64-bit variant when sf == 1 && type == 11\n\n:^fcvt_smnemonic Rd_GPR64, Rn_FPR16\nis b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16\n{\n\tRd_GPR64 = trunc(Rn_FPR16);\n}\n\n# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00\n# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00\n# CONSTRUCT x1e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x1e240000/mask=xfffefc00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision to 32-bit variant when sf == 0 && type == 00\n\n:^fcvt_smnemonic Rd_GPR32, Rn_FPR32\nis b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR32);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00\n# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00\n# CONSTRUCT x9e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x9e240000/mask=xfffefc00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision to 64-bit variant when sf == 1 && type == 00\n\n:^fcvt_smnemonic Rd_GPR64, Rn_FPR32\nis b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32\n{\n\tRd_GPR64 = trunc(Rn_FPR32);\n}\n\n# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00\n# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00\n# CONSTRUCT x1e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x1e640000/mask=xfffefc00 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision to 32-bit variant when sf == 0 && type == 01\n\n:^fcvt_smnemonic Rd_GPR32, Rn_FPR64\nis b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR64);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00\n# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00\n# CONSTRUCT x9e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x9e640000/mask=xfffefc00 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision to 64-bit variant sf == 1 && type == 01\n\n:^fcvt_smnemonic Rd_GPR64, Rn_FPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64\n{\n\tRd_GPR64 = trunc(Rn_FPR64);\n}\n\n# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00\n# CONSTRUCT x0e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$float2float@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4\n# AUNIT --inst x0e617800/mask=xfffffc00 --rand dfp --status fail --comment \"ext nofpround\"\n\n:fcvtl Rd_VPR128.2D, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8)\n\tRd_VPR128.2D[0,64] = float2float(TMPD1[0,32]);\n\tRd_VPR128.2D[64,64] = float2float(TMPD1[32,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00\n# CONSTRUCT x4e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$float2float@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@8\n# AUNIT --inst x4e617800/mask=xfffffc00 --rand dfp --status fail --comment \"ext nofpround\"\n\n:fcvtl2 Rd_VPR128.2D, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8)\n\tRd_VPR128.2D[0,64] = float2float(TMPD1[0,32]);\n\tRd_VPR128.2D[64,64] = float2float(TMPD1[32,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00\n# CONSTRUCT x0e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$float2float@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4\n# AUNIT --inst x0e217800/mask=xfffffc00 --rand sfp --status fail --comment \"ext nofpround\"\n\n:fcvtl Rd_VPR128.4S, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4)\n\tRd_VPR128.4S[0,32] = float2float(TMPD1[0,16]);\n\tRd_VPR128.4S[32,32] = float2float(TMPD1[16,16]);\n\tRd_VPR128.4S[64,32] = float2float(TMPD1[32,16]);\n\tRd_VPR128.4S[96,32] = float2float(TMPD1[48,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00\n# CONSTRUCT x4e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$float2float@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@2\n# AUNIT --inst x4e217800/mask=xfffffc00 --rand sfp --status fail --comment \"ext nofpround\"\n\n:fcvtl2 Rd_VPR128.4S, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4)\n\tRd_VPR128.4S[0,32] = float2float(TMPD1[0,16]);\n\tRd_VPR128.4S[32,32] = float2float(TMPD1[16,16]);\n\tRd_VPR128.4S[64,32] = float2float(TMPD1[32,16]);\n\tRd_VPR128.4S[96,32] = float2float(TMPD1[48,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e79b800/mask=xfffffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e79b800/mask=xfffffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e79a800/mask=xfffffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e79a800/mask=xfffffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ef9a800/mask=xfffffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ef9a800/mask=xfffffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ef9b800/mask=xfffffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ef9b800/mask=xfffffc00\n# CONSTRUCT x5e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x5e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision\n\n:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16\nis b_3031=0b01 & b_2428=0b11110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = trunc(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e21b800/mask=xffbffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e21b800/mask=xffbffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e21a800/mask=xffbffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e21a800/mask=xffbffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ea1a800/mask=xffbffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ea1a800/mask=xffbffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ea1b800/mask=xffbffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ea1b800/mask=xffbffc00\n# CONSTRUCT x5e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x5e21a800/mask=xdf7fec00 --rand sfp --status fail --comment \"nofpround\"\n# Scalar single-precision and double-precision variant sz=0\n\n:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32\nis b_3031=0b01 & b_2428=0b11110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = trunc(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e21b800/mask=xffbffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e21b800/mask=xffbffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e21a800/mask=xffbffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e21a800/mask=xffbffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ea1a800/mask=xffbffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ea1a800/mask=xffbffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ea1b800/mask=xffbffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ea1b800/mask=xffbffc00\n# CONSTRUCT x5e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x5e61a800/mask=xdf7fec00 --rand dfp --status fail --comment \"nofpround\"\n# Scalar single-precision and double-precision variant sz=1\n\n:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64\nis b_3031=0b01 & b_2428=0b11110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = trunc(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e79b800/mask=xbffffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e79b800/mask=xbffffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e79a800/mask=xbffffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e79a800/mask=xbffffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ef9a800/mask=xbffffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ef9a800/mask=xbffffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ef9b800/mask=xbffffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ef9b800/mask=xbffffc00\n# CONSTRUCT x0e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2\n# AUNIT --inst x0e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant Q=0\n\n:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e79b800/mask=xbffffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e79b800/mask=xbffffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e79a800/mask=xbffffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e79a800/mask=xbffffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ef9a800/mask=xbffffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ef9a800/mask=xbffffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ef9b800/mask=xbffffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ef9b800/mask=xbffffc00\n# CONSTRUCT x4e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2\n# AUNIT --inst x4e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant Q=1\n\n:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00\n# CONSTRUCT x0e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4\n# AUNIT --inst x0e21a800/mask=xdf7fec00 --rand sfp --status fail --comment \"nofpround\"\n# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0\n\n:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00\n# CONSTRUCT x4e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4\n# AUNIT --inst x4e21a800/mask=xdf7fec00 --rand sfp --status fail --comment \"nofpround\"\n# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1\n\n:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00\n# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00\n# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00\n# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00\n# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00\n# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00\n# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00\n# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00\n# CONSTRUCT x4e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8\n# AUNIT --inst x4e61a800/mask=xdf7fec00 --rand dfp --status fail --comment \"nofpround\"\n# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1\n\n:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2428=0b01110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00\n# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00\n# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00\n# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00\n# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00\n# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00\n# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00\n# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00\n# CONSTRUCT x1ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x1ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 32-bit variant when sf == 0 && type == 11\n\n:^fcvt_smnemonic Rd_GPR32, Rn_FPR16\nis b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR16);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00\n# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00\n# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00\n# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00\n# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00\n# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00\n# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00\n# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00\n# CONSTRUCT x9ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x9ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 64-bit variant when sf == 1 && type == 11\n\n:^fcvt_smnemonic Rd_GPR64, Rn_FPR16\nis b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16\n{\n\tRd_GPR64 = trunc(Rn_FPR16);\n}\n\n# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00\n# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00\n# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00\n# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00\n# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00\n# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00\n# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00\n# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00\n# CONSTRUCT x1e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x1e200000/mask=xffe6fc00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision to 32-bit variant when sf == 0 && type == 00\n\n:^fcvt_smnemonic Rd_GPR32, Rn_FPR32\nis b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR32);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00\n# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00\n# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00\n# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00\n# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00\n# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00\n# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00\n# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00\n# CONSTRUCT x9e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x9e200000/mask=xffe6fc00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision to 64-bit variant when sf == 1 && type == 00\n\n:^fcvt_smnemonic Rd_GPR64, Rn_FPR32\nis b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32\n{\n\tRd_GPR64 = trunc(Rn_FPR32);\n}\n\n# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00\n# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00\n# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00\n# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00\n# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00\n# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00\n# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00\n# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00\n# CONSTRUCT x1e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x1e600000/mask=xffe6fc00 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision to 32-bit variant when sf == 0 && type == 01\n\n:^fcvt_smnemonic Rd_GPR32, Rn_FPR64\nis b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR64);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00\n# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00\n# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00\n# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00\n# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00\n# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00\n# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00\n# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00\n# CONSTRUCT x9e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1\n# AUNIT --inst x9e600000/mask=xffe6fc00 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision to 64-bit variant sf == 1 && type == 01\n\n:^fcvt_smnemonic Rd_GPR64, Rn_FPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64\n{\n\tRd_GPR64 = trunc(Rn_FPR64);\n}\n\n# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00\n# CONSTRUCT x0e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$float2float@8:8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@8\n# AUNIT --inst x0e616800/mask=xfffffc00 --rand sfp --status fail --comment \"ext nofpround\"\n\n:fcvtn Rd_VPR64.2S, Rn_VPR128.2D\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd\n{\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4)\n\tRd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]);\n\tRd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00\n# CONSTRUCT x4e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@8\n# AUNIT --inst x4e616800/mask=xfffffc00 --rand sfp --status pass --comment \"ext nofpround\"\n\n:fcvtn2 Rd_VPR128.4S, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4)\n\tTMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]);\n\tTMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]);\n\t# simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8)\n\tRd_VPR128.4S[64,64] = TMPD1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00\n# CONSTRUCT x0e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$float2float@4:8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4\n# AUNIT --inst x0e216800/mask=xfffffc00 --rand hfp --status fail --comment \"ext nofpround\"\n\n:fcvtn Rd_VPR64.4H, Rn_VPR128.4S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd\n{\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd resize Rd_VPR64.4H = float2float(TMPQ1) (lane size 4 to 2)\n\tRd_VPR64.4H[0,16] = float2float(TMPQ1[0,32]);\n\tRd_VPR64.4H[16,16] = float2float(TMPQ1[32,32]);\n\tRd_VPR64.4H[32,16] = float2float(TMPQ1[64,32]);\n\tRd_VPR64.4H[48,16] = float2float(TMPQ1[96,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00\n# CONSTRUCT x4e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $float2float@4:8 1:1 &=$copy\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@4\n# AUNIT --inst x4e216800/mask=xfffffc00 --rand hfp --status fail --comment \"ext nofpround\"\n\n:fcvtn2 Rd_VPR128.8H, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPD1 = float2float(Rn_VPR128.4S) (lane size 4 to 2)\n\tTMPD1[0,16] = float2float(Rn_VPR128.4S[0,32]);\n\tTMPD1[16,16] = float2float(Rn_VPR128.4S[32,32]);\n\tTMPD1[32,16] = float2float(Rn_VPR128.4S[64,32]);\n\tTMPD1[48,16] = float2float(Rn_VPR128.4S[96,32]);\n\t# simd copy Rd_VPR128.8H element 1:1 = TMPD1 (lane size 8)\n\tRd_VPR128.8H[64,64] = TMPD1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x7e216800/mask=xffbffc00\n# CONSTRUCT x7e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2\n# AUNIT --inst x7e616800/mask=xfffffc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fcvtxn Rd_FPR32, Rn_FPR64\nis b_2331=0b011111100 & b_22=1 & b_1021=0b100001011010 & Rd_FPR32 & Rn_FPR64 & Zd\n{\n\tRd_FPR32 = float2float(Rn_FPR64);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x2e216800/mask=xbfbffc00\n# CONSTRUCT x2e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$float2float@8:8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2@8\n# AUNIT --inst x2e616800/mask=xfffffc00 --rand sfp --status fail --comment \"ext nofpround\"\n# Vector Variant\n\n:fcvtxn Rd_VPR64.2S, Rn_VPR128.2D\nis b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR64.2S & Rd_VPR128 & Rn_VPR128.2D & Zd\n{\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4)\n\tRd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]);\n\tRd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x2e216800/mask=xbfbffc00\n# CONSTRUCT x6e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn2/2@8\n# AUNIT --inst x6e616800/mask=xfffffc00 --rand sfp --status fail --comment \"ext nofpround\"\n# Vector Variant\n\n:fcvtxn2 Rd_VPR128.4S, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR128.4S & Rn_VPR128.2D & Rd_VPR128 & Zd\n{\n\t# simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4)\n\tTMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]);\n\tTMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]);\n\t# simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8)\n\tRd_VPR128.4S[64,64] = TMPD1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00\n# CONSTRUCT x5f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2\n# AUNIT --inst x5f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Scalar variant when immh=1xxx\n\n:fcvtzs Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b010111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm64 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tRd_FPR64 = NEON_fcvtzs(Rn_FPR64, tmp1);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00\n# CONSTRUCT x5f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2\n# AUNIT --inst x5f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Scalar variant when immh=01xx\n\n:fcvtzs Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_2331=0b010111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fcvtzs(Rn_FPR32, Imm_shr_imm32:4);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00\n# CONSTRUCT x5f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2\n# AUNIT --inst x5f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar variant when immh=001x\n\n:fcvtzs Rd_FPR16, Rn_FPR16, Imm_shr_imm16\nis b_2331=0b010111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm16 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_fcvtzs(Rn_FPR16, Imm_shr_imm16);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x4f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2@8\n# AUNIT --inst x4f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Vector 2D variant when immh=1xxx Q=1 bb=b_22 cc=1 V=VPR128.2D imm=Imm_shr_imm64\n\n:fcvtzs Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_31=0 & b_30=1 & b_2329=0b0011110 & b_22=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Imm_shr_imm64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tRd_VPR128.2D = NEON_fcvtzs(Rn_VPR128.2D, tmp1, 8:1);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x0f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4\n# AUNIT --inst x0f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Vector 2S variant when immh=01xx Q=0 bb=b_2122 cc=0b01 V=VPR64.2S imm=Imm_shr_imm32\n\n:fcvtzs Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_31=0 & b_30=0 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Imm_shr_imm32 & Zd\n{\n\tRd_VPR64.2S = NEON_fcvtzs(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x4f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4\n# AUNIT --inst x4f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Vector 4S variant when immh=01xx Q=1 bb=b_2122 cc=0b01 V=VPR128.4S imm=Imm_shr_imm32\n\n:fcvtzs Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_31=0 & b_30=1 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Imm_shr_imm32 & Zd\n{\n\tRd_VPR128.4S = NEON_fcvtzs(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x0f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2\n# AUNIT --inst x0f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector 4H variant when immh=001x Q=0 bb=b_2022 cc=0b001 V=VPR64.4H imm=Imm_shr_imm16\n\n:fcvtzs Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_31=0 & b_30=0 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR64.4H & Rn_VPR64.4H & Imm_shr_imm16 & Zd\n{\n\tRd_VPR64.4H = NEON_fcvtzs(Rn_VPR64.4H, Imm_shr_imm16, 2:1);\n}\n\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x4f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2\n# AUNIT --inst x4f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector 8H variant when immh=001x Q=1 bb=b_2022 cc=0b001 V=VPR128.8H imm=Imm_shr_imm16\n\n:fcvtzs Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_31=0 & b_30=1 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR128.8H & Rn_VPR128.8H & Imm_shr_imm16 & Zd\n{\n\tRd_VPR128.8H = NEON_fcvtzs(Rn_VPR128.8H, Imm_shr_imm16, 2:1);\n}\n\n# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000\n# CONSTRUCT x1ed88000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits16 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_fcvtzs/2\n# AUNIT --inst x1ed88000/mask=xffff8000 --rand hfp --status noqemu --comment \"nofpround\"\n# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();\n# Half-precision to 32-bit variant when sf == 0 && type == 11 G=GPR32 V=FPR16 size=2 fbits=FBits16\n\n:fcvtzs Rd_GPR32, Rn_FPR16, FBitsOp\nis b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR16 & FBitsOp & FBits16 & Rd_GPR64\n{\n\tlocal tmp1:2 = Rn_FPR16 f* FBits16;\n\tRd_GPR32 = trunc(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000\n# CONSTRUCT x9ed80000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2\n# AUNIT --inst x9ed80000/mask=xffff0000 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 64-bit variant when sf == 1 && type == 11 G=GPR64 V=FPR16 size=2 fbits=FBits16\n\n:fcvtzs Rd_GPR64, Rn_FPR16, FBitsOp\nis b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR16 & FBitsOp & FBits16\n{\n\tlocal tmp1:2 = Rn_FPR16 f* FBitsOp;\n\tRd_GPR64 = trunc(tmp1);\n}\n\n# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000\n# CONSTRUCT x1e188000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits32 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2\n# AUNIT --inst x1e188000/mask=xffff8000 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision to 32-bit variant when sf == 0 && type == 00 G=GPR32 V=FPR32 size=4 fbits=FBits32\n\n:fcvtzs Rd_GPR32, Rn_FPR32, FBitsOp\nis b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR32 & FBitsOp & FBits32 & Rd_GPR64\n{\n\tlocal tmp1:4 = Rn_FPR32 f* FBits32;\n\tRd_GPR32 = trunc(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000\n# CONSTRUCT x9e180000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits32 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2\n# AUNIT --inst x9e180000/mask=xffff0000 --rand sfp --status pass --comment \"nofpround\"\n# Single-precision to 64-bit variant when sf == 1 && type == 00 G=GPR64 V=FPR32 size=4 fbits=FBits32\n\n:fcvtzs Rd_GPR64, Rn_FPR32, FBitsOp\nis b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR32 & FBitsOp & FBits32\n{\n\tlocal tmp1:4 = Rn_FPR32 f* FBits32;\n\tRd_GPR64 = trunc(tmp1);\n}\n\n# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000\n# CONSTRUCT x1e588000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits64 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2\n# AUNIT --inst x1e588000/mask=xffff8000 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision to 32-bit variant when sf == 0 && type == 01 G=GPR32 V=FPR64 size=8 fbits=FBits64\n\n:fcvtzs Rd_GPR32, Rn_FPR64, FBitsOp\nis b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR64 & FBitsOp & FBits64 & Rd_GPR64\n{\n\tlocal tmp1:8 = Rn_FPR64 f* FBits64;\n\tRd_GPR32 = trunc(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000\n# CONSTRUCT x9e580000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits64 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2\n# AUNIT --inst x9e580000/mask=xffff0000 --rand dfp --status pass --comment \"nofpround\"\n# Double-precision to 64-bit variant when sf == 1 && type == 01 G=GPR64 V=FPR64 size=8 fbits=FBits64\n\n:fcvtzs Rd_GPR64, Rn_FPR64, FBitsOp\nis b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR64 & FBitsOp & FBits64\n{\n\tlocal tmp1:8 = Rn_FPR64 f* FBits64;\n\tRd_GPR64 = trunc(tmp1);\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00\n# CONSTRUCT x6f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzu/2@8\n# AUNIT --inst x6f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fcvtzu Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tRd_VPR128.2D = NEON_fcvtzu(Rn_VPR128.2D, tmp1, 8:1);\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00\n# CONSTRUCT x2f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4\n# AUNIT --inst x2f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fcvtzu Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fcvtzu(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00\n# CONSTRUCT x6f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4\n# AUNIT --inst x6f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fcvtzu Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fcvtzu(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00\n# CONSTRUCT x2f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2\n# AUNIT --inst x2f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fcvtzu Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fcvtzu(Rn_VPR64.4H, Imm_shr_imm16, 2:1);\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00\n# CONSTRUCT x6f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2\n# AUNIT --inst x6f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fcvtzu Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fcvtzu(Rn_VPR128.8H, Imm_shr_imm16, 2:1);\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00\n# CONSTRUCT x7f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 1:2 ARG3 << int2float:2 f* fabs =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2\n# AUNIT --inst x7f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# FCVTZU (vector, fixed-point) Scalar immh=001x\n\n:fcvtzu Rd_FPR16, Rn_FPR16, Imm_shr_imm32\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:2 = 1:2 << Imm_shr_imm32;\n\tlocal tmp2:2 = int2float(tmp1);\n\tlocal tmp3:2 = Rn_FPR16 f* tmp2;\n\tlocal tmp4:2 = abs(tmp3);\n\tRd_FPR16 = trunc(tmp4);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00\n# CONSTRUCT x7f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 1:4 ARG3:4 << int2float:4 f* fabs =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2\n# AUNIT --inst x7f20fc00/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n# FCVTZU (vector, fixed-point) Scalar immh=01xx\n\n:fcvtzu Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:4 = 1:4 << Imm_shr_imm32:4;\n\tlocal tmp2:4 = int2float(tmp1);\n\tlocal tmp3:4 = Rn_FPR32 f* tmp2;\n\tlocal tmp4:4 = abs(tmp3);\n\tRd_FPR32 = trunc(tmp4);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00\n# CONSTRUCT x7f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 1:8 ARG3 zext:8 << int2float:8 f* fabs =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2\n# AUNIT --inst x7f40fc00/mask=xffc0fc00 --rand dfp --status fail --comment \"nofpround\"\n# FCVTZU (vector, fixed-point) Scalar immh=1xxx\n\n:fcvtzu Rd_FPR64, Rn_FPR64, Imm_shr_imm32\nis b_2331=0b011111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm32);\n\tlocal tmp2:8 = 1:8 << tmp1;\n\tlocal tmp3:8 = int2float(tmp2);\n\tlocal tmp4:8 = Rn_FPR64 f* tmp3;\n\tlocal tmp5:8 = abs(tmp4);\n\tRd_FPR64 = trunc(tmp5);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000\n# CONSTRUCT x1ed98000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2\n# AUNIT --inst x1ed98000/mask=xffff8000 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fcvtzu Rd_GPR32, Rn_FPR16, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp1:2 = Rn_FPR16 f* FBitsOp;\n\tRd_GPR32 = trunc(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000\n# CONSTRUCT x9ed90000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2\n# AUNIT --inst x9ed90000/mask=xffff0000 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fcvtzu Rd_GPR64, Rn_FPR16, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR64\n{\n\tlocal tmp1:2 = Rn_FPR16 f* FBitsOp;\n\tRd_GPR64 = trunc(tmp1);\n}\n\n# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000\n# CONSTRUCT x1e598000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits64 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2\n# AUNIT --inst x1e598000/mask=xffff8000 --rand dfp --status fail --comment \"nofpround\"\n\n:fcvtzu Rd_GPR32, Rn_FPR64, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp1:8 = Rn_FPR64 f* FBits64;\n\tRd_GPR32 = trunc(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000\n# CONSTRUCT x1e198000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits32 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2\n# AUNIT --inst x1e198000/mask=xffff8000 --rand sfp --status fail --comment \"nofpround\"\n\n:fcvtzu Rd_GPR32, Rn_FPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR32 & Rd_GPR64\n{\n\tlocal tmp1:4 = Rn_FPR32 f* FBits32;\n\tRd_GPR32 = trunc(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000\n# CONSTRUCT x9e590000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits64 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzu/2\n# AUNIT --inst x9e590000/mask=xffff0000 --rand dfp --status fail --comment \"nofpround\"\n\n:fcvtzu Rd_GPR64, Rn_FPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR64\n{\n\tlocal tmp1:8 = Rn_FPR64 f* FBits64;\n\tRd_GPR64 = trunc(tmp1);\n}\n\n# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000\n# CONSTRUCT x9e190000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 FBits32 f* =trunc\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2\n# AUNIT --inst x9e190000/mask=xffff0000 --rand sfp --status fail --comment \"nofpround\"\n\n:fcvtzu Rd_GPR64, Rn_FPR32, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR64\n{\n\tlocal tmp1:4 = Rn_FPR32 f* FBits32;\n\tRd_GPR64 = trunc(tmp1);\n}\n\n# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00\n# CONSTRUCT x6e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f/@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@8\n# AUNIT --inst x6e60fc00/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fdiv Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D f/ Rm_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f/ Rm_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f/ Rm_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00\n# CONSTRUCT x2e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f/@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4\n# AUNIT --inst x2e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fdiv Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S f/ Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f/ Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f/ Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00\n# CONSTRUCT x6e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f/@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4\n# AUNIT --inst x6e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fdiv Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S f/ Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f/ Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f/ Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f/ Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f/ Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e403c00/mask=xbfe0fc00\n# CONSTRUCT x2e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f/@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2\n# AUNIT --inst x2e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fdiv Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f/ Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f/ Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f/ Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f/ Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f/ Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e403c00/mask=xbfe0fc00\n# CONSTRUCT x6e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f/@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2\n# AUNIT --inst x6e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fdiv Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f/ Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f/ Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f/ Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f/ Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f/ Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f/ Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f/ Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f/ Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f/ Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00\n# CONSTRUCT x1e601800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f/\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2\n# AUNIT --inst x1e601800/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fdiv Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x1 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64 f/ Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00\n# CONSTRUCT x1e201800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f/\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2\n# AUNIT --inst x1e201800/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fdiv Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x1 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32 f/ Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00\n# CONSTRUCT x1ee01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f/\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2\n# AUNIT --inst x1ee01800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fdiv Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x1 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16 f/ Rm_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.99 FJCVTZS page C7-2245 line 131259 MATCH x1e7e0000/mask=xfffffc00\n# CONSTRUCT x1e7e0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fjcvtzs/1\n# AUNIT --inst x1e7e0000/mask=xfffffc00 --rand dfp --status noqemu --comment \"nofpround\"\n\n:fjcvtzs Rd_GPR32, Rn_FPR64\nis b_1031=0b0001111001111110000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64\n{\n\tRd_GPR32 = trunc(Rn_FPR64);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000\n# CONSTRUCT x1f400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3\n# AUNIT --inst x1f400000/mask=xffe08000 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Ra_FPR64 f+ (Rm_FPR64 f* Rn_FPR64); #NEON_fmadd(Rn_FPR64, Rm_FPR64, Ra_FPR64);\n}\n\n# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000\n# CONSTRUCT x1f000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3\n# AUNIT --inst x1f000000/mask=xffe08000 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Ra_FPR32 f+ (Rm_FPR32 f* Rn_FPR32); #NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32);\n}\n\n# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000\n# CONSTRUCT x1fc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3\n# AUNIT --inst x1fc00000/mask=xffe08000 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Ra_FPR16 f+ (Rm_FPR16 f* Rn_FPR16); #NEON_fmadd(Rn_FPR16, Rm_FPR16, Ra_FPR16);\n}\n\n# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00\n# CONSTRUCT x4e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@8\n# AUNIT --inst x4e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmax Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmax(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00\n# CONSTRUCT x0e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4\n# AUNIT --inst x0e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00\n# CONSTRUCT x4e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4\n# AUNIT --inst x4e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e403400/mask=xbfe0fc00\n# CONSTRUCT x0e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2\n# AUNIT --inst x0e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fmax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e403400/mask=xbfe0fc00\n# CONSTRUCT x4e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2\n# AUNIT --inst x4e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fmax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00\n# CONSTRUCT x1e604800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2\n# AUNIT --inst x1e604800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmax Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x4 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR64 f> Rm_FPR64;\n\tif (tmp1) goto inst_next;\n\tRd_FPR64 = Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00\n# CONSTRUCT x1e204800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2\n# AUNIT --inst x1e204800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmax Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x4 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR32 f> Rm_FPR32;\n\tif (tmp1) goto inst_next;\n\tRd_FPR32 = Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00\n# CONSTRUCT x1ee04800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2\n# AUNIT --inst x1ee04800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fmax Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x4 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR16 f> Rm_FPR16;\n\tif (tmp1) goto inst_next;\n\tRd_FPR16 = Rm_FPR16;\n\tzext_zh(Zd);# zero upper 30 bytes of Zd\n}\n\n# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00\n# CONSTRUCT x4e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@8\n# AUNIT --inst x4e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmaxnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00\n# CONSTRUCT x0e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4\n# AUNIT --inst x0e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmaxnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00\n# CONSTRUCT x4e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4\n# AUNIT --inst x4e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmaxnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e400400/mask=xbfe0fc00\n# CONSTRUCT x0e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2\n# AUNIT --inst x0e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision SIMD 4H when Q = 0\n\n:fmaxnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fmaxnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e400400/mask=xbfe0fc00\n# CONSTRUCT x4e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2\n# AUNIT --inst x4e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision SIMD 8H when Q = 1\n\n:fmaxnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fmaxnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00\n# CONSTRUCT x1e606800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2\n# AUNIT --inst x1e606800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnm Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x6 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR64 f> Rm_FPR64;\n\tif (tmp1) goto inst_next;\n\tRd_FPR64 = Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00\n# CONSTRUCT x1e206800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2\n# AUNIT --inst x1e206800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnm Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x6 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR32 f> Rm_FPR32;\n\tif (tmp1) goto inst_next;\n\tRd_FPR32 = Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00\n# CONSTRUCT x1ee06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2\n# AUNIT --inst x1ee06800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fmaxnm Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x6 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR16 f> Rm_FPR16;\n\tif (tmp1) goto inst_next;\n\tRd_FPR16 = Rm_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x7e30c800/mask=xffbffc00\n# CONSTRUCT x7e70c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@8\n# AUNIT --inst x7e70c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnmp Rd_FPR64, Rn_VPR128.2D\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_fmaxnmp(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x7e30c800/mask=xffbffc00\n# CONSTRUCT x7e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@4\n# AUNIT --inst x7e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnmp Rd_FPR32, Rn_VPR64.2S\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fmaxnmp(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x5e30c800/mask=xffbffc00\n# CONSTRUCT x5e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxnmp/1@2\n# AUNIT --inst x5e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant\n\n:fmaxnmp Rd_FPR16, vRn_VPR128^\".2H\"\nis b_1031=0b0101111000110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = NEON_fmaxnmp(Rn_FPR32, 2:1);\n}\n\n# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00\n# CONSTRUCT x6e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@8\n# AUNIT --inst x6e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmaxnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00\n# CONSTRUCT x2e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4\n# AUNIT --inst x2e20c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmaxnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00\n# CONSTRUCT x6e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4\n# AUNIT --inst x6e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmaxnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e400400/mask=xbfe0fc00\n# CONSTRUCT x2e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2\n# AUNIT --inst x2e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmaxnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fmaxnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e400400/mask=xbfe0fc00\n# CONSTRUCT x6e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2\n# AUNIT --inst x6e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmaxnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fmaxnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x2e30c800/mask=xbfbffc00\n# CONSTRUCT x6e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@4\n# AUNIT --inst x6e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxnmv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fmaxnmv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x0e30c800/mask=xbffffc00\n# CONSTRUCT x0e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2\n# AUNIT --inst x0e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmaxnmv Rd_FPR16, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd\n{\n\tRd_FPR16 = NEON_fmaxnmv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x0e30c800/mask=xbffffc00\n# CONSTRUCT x4e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2\n# AUNIT --inst x4e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmaxnmv Rd_FPR16, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd\n{\n\tRd_FPR16 = NEON_fmaxnmv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x7e30f800/mask=xffbffc00\n# CONSTRUCT x7e70f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@8\n# AUNIT --inst x7e70f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxp Rd_FPR64, Rn_VPR128.2D\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_fmaxnmv(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x7e30f800/mask=xffbffc00\n# CONSTRUCT x7e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxp/1@4\n# AUNIT --inst x7e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxp Rd_FPR32, Rn_VPR64.2S\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fmaxp(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x5e30f800/mask=xffbffc00\n# CONSTRUCT x5e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxp/1@2\n# AUNIT --inst x5e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant\n\n:fmaxp Rd_FPR16, vRn_VPR128^\".2H\"\nis b_1031=0b0101111000110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = NEON_fmaxp(Rn_FPR32, 2:1);\n}\n\n# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00\n# CONSTRUCT x6e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@8\n# AUNIT --inst x6e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmaxp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00\n# CONSTRUCT x2e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4\n# AUNIT --inst x2e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00\n# CONSTRUCT x6e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4\n# AUNIT --inst x6e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e403400/mask=xbfe0fc00\n# CONSTRUCT x2e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2\n# AUNIT --inst x2e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fmaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e403400/mask=xbfe0fc00\n# CONSTRUCT x6e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2\n# AUNIT --inst x6e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fmaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x2e30f800/mask=xbfbffc00\n# CONSTRUCT x6e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@4\n# AUNIT --inst x6e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmaxv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fmaxv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x0e30f800/mask=xbffffc00\n# CONSTRUCT x0e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2\n# AUNIT --inst x0e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmaxv Rd_FPR16, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd\n{\n\tRd_FPR16 = NEON_fmaxv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x0e30f800/mask=xbffffc00\n# CONSTRUCT x4e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2\n# AUNIT --inst x4e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmaxv Rd_FPR16, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd\n{\n\tRd_FPR16 = NEON_fmaxv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00\n# CONSTRUCT x4ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@8\n# AUNIT --inst x4ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmin Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmin(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00\n# CONSTRUCT x0ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4\n# AUNIT --inst x0ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00\n# CONSTRUCT x4ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4\n# AUNIT --inst x4ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ec03400/mask=xbfe0fc00\n# CONSTRUCT x0ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2\n# AUNIT --inst x0ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fmin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ec03400/mask=xbfe0fc00\n# CONSTRUCT x4ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2\n# AUNIT --inst x4ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fmin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00\n# CONSTRUCT x1e605800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2\n# AUNIT --inst x1e605800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmin Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x5 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR64 f<= Rm_FPR64;\n\tif (tmp1) goto inst_next;\n\tRd_FPR64 = Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00\n# CONSTRUCT x1e205800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2\n# AUNIT --inst x1e205800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmin Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x5 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR32 f<= Rm_FPR32;\n\tif (tmp1) goto inst_next;\n\tRd_FPR32 = Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00\n# CONSTRUCT x1ee05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2\n# AUNIT --inst x1ee05800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fmin Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x5 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n\tlocal tmp1:1 = Rn_FPR16 f<= Rm_FPR16;\n\tif (tmp1) goto inst_next;\n\tRd_FPR16 = Rm_FPR16;\n\tzext_zh(Zd);# zero upper 30 bytes of Zd\n}\n\n# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00\n# CONSTRUCT x4ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@8\n# AUNIT --inst x4ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fminnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fminnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00\n# CONSTRUCT x0ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4\n# AUNIT --inst x0ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fminnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00\n# CONSTRUCT x4ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4\n# AUNIT --inst x4ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fminnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ec00400/mask=xbfe0fc00\n# CONSTRUCT x0ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2\n# AUNIT --inst x0ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fminnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fminnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ec00400/mask=xbfe0fc00\n# CONSTRUCT x4ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2\n# AUNIT --inst x4ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fminnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fminnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00\n# CONSTRUCT x1e607800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2\n# AUNIT --inst x1e607800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fminnm Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x7 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_fminnm(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00\n# CONSTRUCT x1e207800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2\n# AUNIT --inst x1e207800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnm Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x7 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fminnm(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00\n# CONSTRUCT x1ee07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2\n# AUNIT --inst x1ee07800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fminnm Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x7 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_fminnm(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x7eb0c800/mask=xffbffc00\n# CONSTRUCT x7ef0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@8\n# AUNIT --inst x7ef0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fminnmp Rd_FPR64, Rn_VPR128.2D\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_fminnmp(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x7eb0c800/mask=xffbffc00\n# CONSTRUCT x7eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@4\n# AUNIT --inst x7eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnmp Rd_FPR32, Rn_VPR64.2S\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fminnmp(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x5eb0c800/mask=xffbffc00\n# CONSTRUCT x5eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminnmp/1@2\n# AUNIT --inst x5eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant\n\n:fminnmp Rd_FPR16, vRn_VPR128^\".2H\"\nis b_1031=0b0101111010110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = NEON_fminnmp(Rn_FPR32, 2:1);\n}\n\n# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00\n# CONSTRUCT x6ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@8\n# AUNIT --inst x6ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fminnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fminnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00\n# CONSTRUCT x2ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4\n# AUNIT --inst x2ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fminnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00\n# CONSTRUCT x6ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4\n# AUNIT --inst x6ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fminnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ec00400/mask=xbfe0fc00\n# CONSTRUCT x2ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2\n# AUNIT --inst x2ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fminnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fminnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ec00400/mask=xbfe0fc00\n# CONSTRUCT x6ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2\n# AUNIT --inst x6ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fminnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fminnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x2eb0c800/mask=xbfbffc00\n# CONSTRUCT x6eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@4\n# AUNIT --inst x6eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminnmv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fminnmv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x0eb0c800/mask=xbffffc00\n# CONSTRUCT x0eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2\n# AUNIT --inst x0eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fminnmv Rd_FPR16, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd\n{\n\tRd_FPR16 = NEON_fminnmv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x0eb0c800/mask=xbffffc00\n# CONSTRUCT x4eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2\n# AUNIT --inst x4eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fminnmv Rd_FPR16, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd\n{\n\tRd_FPR16 = NEON_fminnmv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x7eb0f800/mask=xffbffc00\n# CONSTRUCT x7ef0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@8\n# AUNIT --inst x7ef0f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fminp Rd_FPR64, Rn_VPR128.2D\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_fminp(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x7eb0f800/mask=xffbffc00\n# CONSTRUCT x7eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@4\n# AUNIT --inst x7eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminp Rd_FPR32, Rn_VPR64.2S\nis b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fminp(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x5eb0f800/mask=xffbffc00\n# CONSTRUCT x5eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminp/1@2\n# AUNIT --inst x5eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant\n\n:fminp Rd_FPR16, vRn_VPR128^\".2H\"\nis b_1031=0b0101111010110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = NEON_fminp(Rn_FPR32, 2:1);\n}\n\n# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00\n# CONSTRUCT x6ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@8\n# AUNIT --inst x6ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fminp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fminp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00\n# CONSTRUCT x2ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4\n# AUNIT --inst x2ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00\n# CONSTRUCT x6ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4\n# AUNIT --inst x6ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ec03400/mask=xbfe0fc00\n# CONSTRUCT x2ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2\n# AUNIT --inst x2ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_fminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ec03400/mask=xbfe0fc00\n# CONSTRUCT x6ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2\n# AUNIT --inst x6ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_fminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.120 FMINV page C7-2286 line 133697 MATCH x2eb0f800/mask=xbfbffc00\n# CONSTRUCT x6eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@4\n# AUNIT --inst x6eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fminv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fminv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.120 FMINV page C7-2286 line 133697 MATCH x0eb0f800/mask=xbffffc00\n# CONSTRUCT x0eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2\n# AUNIT --inst x0eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fminv Rd_FPR16, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd\n{\n\tRd_FPR16 = NEON_fminv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.120 FMINV page C7-2286 line 133697 MATCH x0eb0f800/mask=xbffffc00\n# CONSTRUCT x4eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2\n# AUNIT --inst x4eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fminv Rd_FPR16, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd\n{\n\tRd_FPR16 = NEON_fminv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400\n# CONSTRUCT x4fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8\n# AUNIT --inst x4fc01000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n\n:fmla Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x1 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\t# simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400\n# CONSTRUCT x0f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4\n# AUNIT --inst x0f801000/mask=xffc0f400 --rand sfp --status pass --comment \"nofpround\"\n\n:fmla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400\n# CONSTRUCT x4f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4\n# AUNIT --inst x4f801000/mask=xffc0f400 --rand sfp --status fail --comment \"nofpround\"\n\n:fmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f001000/mask=xffc0f400\n# CONSTRUCT x5f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* &=f+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2\n# AUNIT --inst x5f001000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half-precision variant\n\n:fmla Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2231=0b0101111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp2:2 = Rn_FPR16 f* tmp1;\n\tRd_FPR16 = Rd_FPR16 f+ tmp2;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f801000/mask=xff80f400\n# CONSTRUCT x5f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* &=f+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4\n# AUNIT --inst x5f801000/mask=xffc0f400 --rand sfp --status pass --comment \"nofpround\"\n# Scalar, single-precision and double-precision variant, sz=0\n\n:fmla Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2331=0b010111111 & b_22=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\tlocal tmp2:4 = Rn_FPR32 f* tmp1;\n\tRd_FPR32 = Rd_FPR32 f+ tmp2;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f801000/mask=xff80f400\n# CONSTRUCT x5fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* &=f+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8\n# AUNIT --inst x5fc01000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n# Scalar, single-precision and double-precision variant, sz=1\n\n:fmla Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex\nis b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\tlocal tmp2:8 = Rn_FPR64 f* tmp1;\n\tRd_FPR64 = Rd_FPR64 f+ tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f001000/mask=xbfc0f400\n# CONSTRUCT x0f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2\n# AUNIT --inst x0f001000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector, half-precision variant SIMD 4H when Q = 0\n\n:fmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f+ TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f+ TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f+ TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f+ TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f001000/mask=xbfc0f400\n# CONSTRUCT x4f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2\n# AUNIT --inst x4f001000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector, half-precision variant SIMD 8H when Q = 1\n\n:fmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f+ TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f+ TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f+ TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f+ TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f+ TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f+ TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f+ TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f+ TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00\n# CONSTRUCT x4e60cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@8 &=$f+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8\n# AUNIT --inst x4e60cc00/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00\n# CONSTRUCT x0e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4\n# AUNIT --inst x0e20cc00/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Re_VPR128 & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00\n# CONSTRUCT x4e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4\n# AUNIT --inst x4e20cc00/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e400c00/mask=xbfe0fc00\n# CONSTRUCT x0e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2\n# AUNIT --inst x0e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32];\n\tTMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32];\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 4\n\tRd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f+ TMPD1[0,32];\n\tRd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f+ TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e400c00/mask=xbfe0fc00\n# CONSTRUCT x4e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2\n# AUNIT --inst x4e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 4\n\tRd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f+ TMPQ1[0,32];\n\tRd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f+ TMPQ1[32,32];\n\tRd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f+ TMPQ1[64,32];\n\tRd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f+ TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x0f800000/mask=xbfc0f400\n# CONSTRUCT x0f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@4\n# AUNIT --inst x0f800000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlal Rd_VPR64.2S, vRn_VPR64^\".2H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPS1 = Rn_VPR64[0,32];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2\n\tTMPS2[0,16] = TMPS1[0,16] f* tmp2;\n\tTMPS2[16,16] = TMPS1[16,16] f* tmp2;\n\t# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)\n\tTMPD3[0,32] = float2float(TMPS2[0,16]);\n\tTMPD3[32,32] = float2float(TMPS2[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x0f800000/mask=xbfc0f400\n# CONSTRUCT x4f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2\n# AUNIT --inst x4f800000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlal Rd_VPR128.4S, vRn_VPR128^\".4H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPD1 = Rn_VPR128[0,64];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2\n\tTMPD2[0,16] = TMPD1[0,16] f* tmp2;\n\tTMPD2[16,16] = TMPD1[16,16] f* tmp2;\n\tTMPD2[32,16] = TMPD1[32,16] f* tmp2;\n\tTMPD2[48,16] = TMPD1[48,16] f* tmp2;\n\t# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)\n\tTMPQ3[0,32] = float2float(TMPD2[0,16]);\n\tTMPQ3[32,32] = float2float(TMPD2[16,16]);\n\tTMPQ3[64,32] = float2float(TMPD2[32,16]);\n\tTMPQ3[96,32] = float2float(TMPD2[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x2f808000/mask=xbfc0f400\n# CONSTRUCT x2f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2\n# AUNIT --inst x2f808000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlal2 Rd_VPR64.2S, vRn_VPR64^\".2H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPS1 = Rn_VPR64[32,32];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2\n\tTMPS2[0,16] = TMPS1[0,16] f* tmp2;\n\tTMPS2[16,16] = TMPS1[16,16] f* tmp2;\n\t# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)\n\tTMPD3[0,32] = float2float(TMPS2[0,16]);\n\tTMPD3[32,32] = float2float(TMPS2[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x2f808000/mask=xbfc0f400\n# CONSTRUCT x6f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2\n# AUNIT --inst x6f808000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlal2 Rd_VPR128.4S, vRn_VPR128^\".4H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPD1 = Rn_VPR128[64,64];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2\n\tTMPD2[0,16] = TMPD1[0,16] f* tmp2;\n\tTMPD2[16,16] = TMPD1[16,16] f* tmp2;\n\tTMPD2[32,16] = TMPD1[32,16] f* tmp2;\n\tTMPD2[48,16] = TMPD1[48,16] f* tmp2;\n\t# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)\n\tTMPQ3[0,32] = float2float(TMPD2[0,16]);\n\tTMPQ3[32,32] = float2float(TMPD2[16,16]);\n\tTMPQ3[64,32] = float2float(TMPD2[32,16]);\n\tTMPQ3[96,32] = float2float(TMPD2[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x0e20ec00/mask=xbfe0fc00\n# CONSTRUCT x0e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2\n# AUNIT --inst x0e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlal Rd_VPR64.2S, vRn_VPR64^\".2H\", vRm_VPR64^\".2H\"\nis b_31=0 & b_30=0 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd\n{\n\tTMPS1 = Rn_VPR64[0,32];\n\tTMPS2 = Rm_VPR64[0,32];\n\t# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2\n\tTMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];\n\tTMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];\n\t# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)\n\tTMPD4[0,32] = float2float(TMPS3[0,16]);\n\tTMPD4[32,32] = float2float(TMPS3[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x0e20ec00/mask=xbfe0fc00\n# CONSTRUCT x4e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2\n# AUNIT --inst x4e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlal Rd_VPR128.4S, vRn_VPR128^\".4H\", Rm_VPR64.4H\nis b_31=0 & b_30=1 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd\n{\n\tTMPD1 = Rn_VPR128[0,64];\n\tTMPD2 = Rm_VPR64.4H[0,64];\n\t# simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2\n\tTMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16];\n\tTMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16];\n\tTMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16];\n\tTMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16];\n\t# simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = float2float(TMPD3[0,16]);\n\tTMPQ4[32,32] = float2float(TMPD3[16,16]);\n\tTMPQ4[64,32] = float2float(TMPD3[32,16]);\n\tTMPQ4[96,32] = float2float(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x2e20cc00/mask=xbfe0fc00\n# CONSTRUCT x2e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2\n# AUNIT --inst x2e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlal2 Rd_VPR64.2S, vRn_VPR64^\".2H\", vRm_VPR128^\".2H\"\nis b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd\n{\n\tTMPS1 = Rn_VPR64[32,32];\n\tTMPS2 = Rm_VPR128[32,32];\n\t# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2\n\tTMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];\n\tTMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];\n\t# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)\n\tTMPD4[0,32] = float2float(TMPS3[0,16]);\n\tTMPD4[32,32] = float2float(TMPS3[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x2e20cc00/mask=xbfe0fc00\n# CONSTRUCT x6e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2\n# AUNIT --inst x6e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlal2 Rd_VPR128.4S, vRn_VPR128^\".4H\", Rm_VPR64.4H\nis b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd\n{\n\tTMPD1 = Rn_VPR128[64,64];\n\t# simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2\n\tTMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16];\n\tTMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16];\n\tTMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16];\n\tTMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16];\n\t# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)\n\tTMPQ3[0,32] = float2float(TMPD2[0,16]);\n\tTMPQ3[32,32] = float2float(TMPD2[16,16]);\n\tTMPQ3[64,32] = float2float(TMPD2[32,16]);\n\tTMPQ3[96,32] = float2float(TMPD2[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400\n# CONSTRUCT x4fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8\n# AUNIT --inst x4fc05000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n\n:fmls Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x5 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\t# simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400\n# CONSTRUCT x0f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4\n# AUNIT --inst x0f805000/mask=xffc0f400 --rand sfp --status pass --comment \"nofpround\"\n\n:fmls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f- TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f- TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400\n# CONSTRUCT x4f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4\n# AUNIT --inst x4f805000/mask=xffc0f400 --rand sfp --status fail --comment \"nofpround\"\n\n:fmls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f005000/mask=xffc0f400\n# CONSTRUCT x5f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* &=f-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2\n# AUNIT --inst x5f005000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half-precision variant\n\n:fmls Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2231=0b0101111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp2:2 = Rn_FPR16 f* tmp1;\n\tRd_FPR16 = Rd_FPR16 f- tmp2;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f805000/mask=xff80f400\n# CONSTRUCT x5f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* &=f-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4\n# AUNIT --inst x5f805000/mask=xffc0f400 --rand sfp --status pass --comment \"nofpround\"\n# Scalar, single-precision and double-precision variant, sz=0\n\n:fmls Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2331=0b010111111 & b_22=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\tlocal tmp2:4 = Rn_FPR32 f* tmp1;\n\tRd_FPR32 = Rd_FPR32 f- tmp2;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f805000/mask=xff80f400\n# CONSTRUCT x5fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* &=f-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8\n# AUNIT --inst x5fc05000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n# Scalar, single-precision and double-precision variant, sz=1\n\n:fmls Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex\nis b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\tlocal tmp2:8 = Rn_FPR64 f* tmp1;\n\tRd_FPR64 = Rd_FPR64 f- tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f005000/mask=xbfc0f400\n# CONSTRUCT x0f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2\n# AUNIT --inst x0f005000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector, half-precision variant SIMD 4H when Q = 0\n\n:fmls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f- TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f- TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f- TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f- TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f005000/mask=xbfc0f400\n# CONSTRUCT x4f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2\n# AUNIT --inst x4f005000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector, half-precision variant SIMD 8H when Q = 1\n\n:fmls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f- TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f- TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f- TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f- TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f- TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f- TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f- TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f- TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00\n# CONSTRUCT x4ee0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG1 $f*@8 &=$f-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8\n# AUNIT --inst x4ee0cc00/mask=xffe0fc00 --rand dfp --status fail --comment \"nofpround\"\n\n:fmls Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D f* Rd_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rd_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rd_VPR128.2D[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00\n# CONSTRUCT x0ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4\n# AUNIT --inst x0ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fmls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];\n\tRd_VPR64.2S = Rd_VPR64.2S f- TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00\n# CONSTRUCT x4ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4\n# AUNIT --inst x4ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fmls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ec00c00/mask=xbfe0fc00\n# CONSTRUCT x0ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2\n# AUNIT --inst x0ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32];\n\tTMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32];\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 4\n\tRd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f- TMPD1[0,32];\n\tRd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f- TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ec00c00/mask=xbfe0fc00\n# CONSTRUCT x4ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2\n# AUNIT --inst x4ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 4\n\tRd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f- TMPQ1[0,32];\n\tRd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f- TMPQ1[32,32];\n\tRd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f- TMPQ1[64,32];\n\tRd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f- TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x0f804000/mask=xbfc0f400\n# CONSTRUCT x0f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2\n# AUNIT --inst x0f804000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlsl Rd_VPR64.2S, vRn_VPR64^\".2H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPS1 = Rn_VPR64[0,32];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2\n\tTMPS2[0,16] = TMPS1[0,16] f* tmp2;\n\tTMPS2[16,16] = TMPS1[16,16] f* tmp2;\n\t# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)\n\tTMPD3[0,32] = float2float(TMPS2[0,16]);\n\tTMPD3[32,32] = float2float(TMPS2[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x0f804000/mask=xbfc0f400\n# CONSTRUCT x4f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2\n# AUNIT --inst x4f804000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlsl Rd_VPR128.4S, vRn_VPR128^\".4H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPD1 = Rn_VPR128[0,64];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2\n\tTMPD2[0,16] = TMPD1[0,16] f* tmp2;\n\tTMPD2[16,16] = TMPD1[16,16] f* tmp2;\n\tTMPD2[32,16] = TMPD1[32,16] f* tmp2;\n\tTMPD2[48,16] = TMPD1[48,16] f* tmp2;\n\t# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)\n\tTMPQ3[0,32] = float2float(TMPD2[0,16]);\n\tTMPQ3[32,32] = float2float(TMPD2[16,16]);\n\tTMPQ3[64,32] = float2float(TMPD2[32,16]);\n\tTMPQ3[96,32] = float2float(TMPD2[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x2f80c000/mask=xbfc0f400\n# CONSTRUCT x2f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2\n# AUNIT --inst x2f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlsl2 Rd_VPR64.2S, vRn_VPR64^\".2H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPS1 = Rn_VPR64[32,32];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2\n\tTMPS2[0,16] = TMPS1[0,16] f* tmp2;\n\tTMPS2[16,16] = TMPS1[16,16] f* tmp2;\n\t# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)\n\tTMPD3[0,32] = float2float(TMPS2[0,16]);\n\tTMPD3[32,32] = float2float(TMPS2[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x2f80c000/mask=xbfc0f400\n# CONSTRUCT x6f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2\n# AUNIT --inst x6f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlsl2 Rd_VPR128.4S, vRn_VPR128^\".4H\", Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\tTMPD1 = Rn_VPR128[64,64];\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2\n\tTMPD2[0,16] = TMPD1[0,16] f* tmp2;\n\tTMPD2[16,16] = TMPD1[16,16] f* tmp2;\n\tTMPD2[32,16] = TMPD1[32,16] f* tmp2;\n\tTMPD2[48,16] = TMPD1[48,16] f* tmp2;\n\t# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)\n\tTMPQ3[0,32] = float2float(TMPD2[0,16]);\n\tTMPQ3[32,32] = float2float(TMPD2[16,16]);\n\tTMPQ3[64,32] = float2float(TMPD2[32,16]);\n\tTMPQ3[96,32] = float2float(TMPD2[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x0ea0ec00/mask=xbfe0fc00\n# CONSTRUCT x0ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2\n# AUNIT --inst x0ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlsl Rd_VPR64.2S, vRn_VPR64^\".2H\", vRm_VPR64^\".2H\"\nis b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd\n{\n\tTMPS1 = Rn_VPR64[0,32];\n\tTMPS2 = Rm_VPR64[0,32];\n\t# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2\n\tTMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];\n\tTMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];\n\t# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)\n\tTMPD4[0,32] = float2float(TMPS3[0,16]);\n\tTMPD4[32,32] = float2float(TMPS3[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x0ea0ec00/mask=xbfe0fc00\n# CONSTRUCT x4ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2\n# AUNIT --inst x4ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlsl Rd_VPR128.4S, vRn_VPR128^\".4H\", Rm_VPR64.4H\nis b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd\n{\n\tTMPD1 = Rn_VPR128[0,64];\n\tTMPD2 = Rm_VPR64.4H[0,64];\n\t# simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2\n\tTMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16];\n\tTMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16];\n\tTMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16];\n\tTMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16];\n\t# simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = float2float(TMPD3[0,16]);\n\tTMPQ4[32,32] = float2float(TMPD3[16,16]);\n\tTMPQ4[64,32] = float2float(TMPD3[32,16]);\n\tTMPQ4[96,32] = float2float(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x2ea0cc00/mask=xbfe0fc00\n# CONSTRUCT x2ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2\n# AUNIT --inst x2ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 2S when Q = 0\n\n:fmlsl2 Rd_VPR64.2S, vRn_VPR64^\".2H\", vRm_VPR128^\".2H\"\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd\n{\n\tTMPS1 = Rn_VPR64[32,32];\n\tTMPS2 = Rm_VPR128[32,32];\n\t# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2\n\tTMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];\n\tTMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];\n\t# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)\n\tTMPD4[0,32] = float2float(TMPS3[0,16]);\n\tTMPD4[32,32] = float2float(TMPS3[16,16]);\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x2ea0cc00/mask=xbfe0fc00\n# CONSTRUCT x6ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2\n# AUNIT --inst x6ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment \"ext nofpround\"\n# SIMD 4S when Q = 1\n\n:fmlsl2 Rd_VPR128.4S, vRn_VPR128^\".4H\", Rm_VPR64.4H\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd\n{\n\tTMPD1 = Rn_VPR128[64,64];\n\t# simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2\n\tTMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16];\n\tTMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16];\n\tTMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16];\n\tTMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16];\n\t# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)\n\tTMPQ3[0,32] = float2float(TMPD2[0,16]);\n\tTMPQ3[32,32] = float2float(TMPD2[16,16]);\n\tTMPQ3[64,32] = float2float(TMPD2[32,16]);\n\tTMPQ3[96,32] = float2float(TMPD2[48,16]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# CONSTRUCT x6f00f400/mask=xfff8fc00 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8\n# AUNIT --inst x6f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop\n\n:fmov Rd_VPR128.2D, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmov(Imm_neon_uimm8Shift, 8:1);\n}\n\n# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# CONSTRUCT x0f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4\n# AUNIT --inst x0f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop\n\n:fmov Rd_VPR64.2S, Imm_neon_uimm8Shift\nis b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1);\n}\n\n# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# CONSTRUCT x4f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4\n# AUNIT --inst x4f00f400/mask=xfff8fc00 --rand sfp --status nopcodeop\n\n:fmov Rd_VPR128.4S, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1);\n}\n\n# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00fc00/mask=xbff8fc00\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x0f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float:2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2\n# AUNIT --inst x0f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 4H when Q = 0\n\n:fmov Rd_VPR64.4H, Imm_neon_uimm8Shift\nis b_31=0 & b_30=0 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR64.4H & Imm_neon_uimm8Shift & Zd\n{\n\tlocal tmp1:2 = int2float(Imm_neon_uimm8Shift);\n\t# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)\n\tRd_VPR64.4H[0,16] = tmp1;\n\tRd_VPR64.4H[16,16] = tmp1;\n\tRd_VPR64.4H[32,16] = tmp1;\n\tRd_VPR64.4H[48,16] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00fc00/mask=xbff8fc00\n# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00\n# CONSTRUCT x4f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float:2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2\n# AUNIT --inst x4f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant SIMD 8H when Q = 1\n\n:fmov Rd_VPR128.8H, Imm_neon_uimm8Shift\nis b_31=0 & b_30=1 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR128.8H & Imm_neon_uimm8Shift & Zd\n{\n\tlocal tmp1:2 = int2float(Imm_neon_uimm8Shift);\n\t# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)\n\tRd_VPR128.8H[0,16] = tmp1;\n\tRd_VPR128.8H[16,16] = tmp1;\n\tRd_VPR128.8H[32,16] = tmp1;\n\tRd_VPR128.8H[48,16] = tmp1;\n\tRd_VPR128.8H[64,16] = tmp1;\n\tRd_VPR128.8H[80,16] = tmp1;\n\tRd_VPR128.8H[96,16] = tmp1;\n\tRd_VPR128.8H[112,16] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00\n# CONSTRUCT x1ee04000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1ee04000/mask=xfffffc00 --rand hfp --status noqemu\n# Half-precision variant when type == 11 arg1=Rd_FPR16 arg2=Rn_FPR16\n\n:fmov Rd_FPR16, Rn_FPR16\nis b_2431=0b00011110 & b_2223=0b11 & b_1021=0b100000010000 & Rd_FPR16 & Rn_FPR16 & Rd_FPR64 & Zd\n{\n\tRd_FPR16 = Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00\n# CONSTRUCT x1e204000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e204000/mask=xfffffc00 --rand sfp --status pass\n# Single-precision variant when type == 00 arg1=Rd_FPR32 arg2=Rn_FPR32\n\n:fmov Rd_FPR32, Rn_FPR32\nis b_2431=0b00011110 & b_2223=0b00 & b_1021=0b100000010000 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00\n# CONSTRUCT x1e604000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e604000/mask=xfffffc00 --rand dfp --status pass\n# Double-precision variant when type == 01 arg1=Rd_FPR64 arg2=Rn_FPR64\n\n:fmov Rd_FPR64, Rn_FPR64\nis b_2431=0b00011110 & b_2223=0b01 & b_1021=0b100000010000 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x1e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e660000/mask=xfffffc00 --rand dfp --status noqemu --comment \"nofpround\"\n# UNDOCUMENTED Double-precision to 32-bit variant when sf == 0 && type == 01 && rmode == 00 && opcode = 110 arg1=Rd_GPR32 arg2=Rn_FPR64\n\n:fmov Rd_GPR32, Rn_FPR64\nis b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64\n{\n\tRd_GPR32 = float2float(Rn_FPR64);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x9e260000/mask=xfffffc00 --rand sfp --status noqemu --comment \"nofpround\"\n# UNDOCUMENTED Single-precision to 64-bit variant when sf == 1 && type == 00 && rmode == 00 && opcode = 110 arg1=Rd_GPR64 arg2=Rn_FPR32\n\n:fmov Rd_GPR64, Rn_FPR32\nis b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR32\n{\n\tRd_GPR64 = float2float(Rn_FPR32);\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x1e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e670000/mask=xfffffc00 --rand dfp --status noqemu --comment \"nofpround\"\n# UNDOCUMENTED 32-bit to Double-precision variant when sf == 0 && type == 01 && rmode == 00 && opcode = 111 arg1=Rd_FPR64 arg2=Rn_GPR32\n\n:fmov Rd_FPR64, Rn_GPR32\nis b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR32 & Zd\n{\n\tRd_FPR64 = float2float(Rn_GPR32);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x9e270000/mask=xfffffc00 --rand sfp --status noqemu --comment \"nofpround\"\n# UNDOCUMENTED 64-bit to single-precision variant when sf == 1 && type == 00 && rmode == 00 && opcode = 111 arg1=Rd_FPR32 arg2=Rn_GPR64\n\n:fmov Rd_FPR32, Rn_GPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR64 & Zd\n{\n\tRd_FPR32 = float2float(Rn_GPR64);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x1ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 32-bit variant when sf == 0 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR16\n\n:fmov Rd_GPR32, Rn_FPR16\nis b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR16 & Rd_GPR64\n{\n\tRd_GPR32 = float2float(Rn_FPR16);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x9ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision to 64-bit variant when sf == 1 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR16\n\n:fmov Rd_GPR64, Rn_FPR16\nis b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR16\n{\n\tRd_GPR64 = float2float(Rn_FPR16);\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x1ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# 32-bit to half-precision variant when sf == 0 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR32\n\n:fmov Rd_FPR16, Rn_GPR32\nis b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR32 & Zd\n{\n\tRd_FPR16 = float2float(Rn_GPR32);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x1e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e270000/mask=xfffffc00 --rand sfp --status pass --comment \"nofpround\"\n# 32-bit to single-precision variant when sf == 0 && type == 00 && rmode == 00 && opcode == 111 arg1=Rd_FPR32 arg2=Rn_GPR32\n\n:fmov Rd_FPR32, Rn_GPR32\nis b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR32 & Zd\n{\n\tRd_FPR32 = Rn_GPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x1e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e260000/mask=xfffffc00 --rand sfp --status pass --comment \"nofpround\"\n# Single-precision to 32-bit variant when sf == 0 && type == 00 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR32\n\n:fmov Rd_GPR32, Rn_FPR32\nis b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR32 & Rd_GPR64\n{\n\tRd_GPR32 = Rn_FPR32;\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =float2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x9ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# 64-bit to half-precision variant when sf == 1 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR64\n\n:fmov Rd_FPR16, Rn_GPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR64 & Zd\n{\n\tRd_FPR16 = float2float(Rn_GPR64);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x9e670000/mask=xfffffc00 --rand dfp --status pass --comment \"nofpround\"\n# 64-bit to double-precision variant when sf == 1 && type == 01 && rmode == 00 && opcode == 111 arg1=Rd_FPR64 arg2=Rn_GPR64\n\n:fmov Rd_FPR64, Rn_GPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR64 & Zd\n{\n\tRd_FPR64 = Rn_GPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9eaf0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 1:1 &=$copy@8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fmov/2\n# AUNIT --inst x9eaf0000/mask=xfffffc00 --rand dfp --status pass --comment \"nofpround\"\n# 64-bit to top half of 128-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 111 arg1=vRd_VPR128^\".D[1]\" arg2=Rn_GPR64\n\n:fmov vRd_VPR128^\".D[1]\", Rn_GPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b111 & b_1015=0b000000 & vRd_VPR128 & Rd_VPR128 & Rn_GPR64 & Zd\n{\n\t# simd copy Rd_VPR128 element 1:1 = Rn_GPR64 (lane size 8)\n\tRd_VPR128[64,64] = Rn_GPR64;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x9e660000/mask=xfffffc00 --rand dfp --status pass --comment \"nofpround\"\n# Double-precision to 64-bit variant when sf == 1 && type == 01 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR64\n\n:fmov Rd_GPR64, Rn_FPR64\nis b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR64\n{\n\tRd_GPR64 = Rn_FPR64;\n}\n\n# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00\n# CONSTRUCT x9eae0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 =ARG2[1]:8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8\n# AUNIT --inst x9eae0000/mask=xfffffc00 --rand dfp --status pass --comment \"nofpround\"\n# Top half of 128-bit to 64-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 110 arg1=Rd_GPR64 arg2=vRd_VPR128^\".D[1]\"\n\n:fmov Rd_GPR64, vRn_VPR128^\".D[1]\"\nis b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & vRn_VPR128 & Rn_VPR128\n{\n\tRd_GPR64 = Rn_VPR128[64,64];\n}\n\n# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0\n# CONSTRUCT x1e601001/mask=xffe01fe1 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e601001/mask=xffe01fe1 --rand dfp --status pass\n\n:fmov Rd_FPR64, Imm8_fmov64_operand\nis ImmS_ImmR_TestSet=1 & m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Imm8_fmov64_operand & b_1012=4 & imm5=0x0 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Imm8_fmov64_operand:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0\n# CONSTRUCT x1e201000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1e201000/mask=xffe01fe0 --rand sfp --status pass\n\n:fmov Rd_FPR32, Imm8_fmov32_operand\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Imm8_fmov32_operand & b_1012=4 & imm5=0x0 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Imm8_fmov32_operand:4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0\n# CONSTRUCT x1ee01000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1\n# AUNIT --inst x1ee01000/mask=xffe01fe0 --rand hfp --status noqemu\n\n:fmov Rd_FPR16, Imm8_fmov16_operand\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Imm8_fmov16_operand & b_1012=4 & imm5=0x0 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Imm8_fmov16_operand:2;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000\n# CONSTRUCT x1f408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3\n# AUNIT --inst x1f408000/mask=xffe08000 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Ra_FPR64 f- (Rm_FPR64 f* Rn_FPR64);\n\n}\n\n# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000\n# CONSTRUCT x1f008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3\n# AUNIT --inst x1f008000/mask=xffe08000 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Ra_FPR32 f- (Rm_FPR32 f* Rn_FPR32);\n}\n\n# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000\n# CONSTRUCT x1fc08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3\n# AUNIT --inst x1fc08000/mask=xffe08000 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Ra_FPR16 f- (Rm_FPR16 f* Rn_FPR16);\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f009000/mask=xffc0f400\n# CONSTRUCT x5f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2\n# AUNIT --inst x5f009000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# FMUL (by element) Scalar, half-precision\n\n:fmul Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2231=0b0101111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\tRd_FPR16 = Rn_FPR16 f* tmp1;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f809000/mask=xff80f400\n# CONSTRUCT x5f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4\n# AUNIT --inst x5f809000/mask=xffc0f400 --rand sfp --status pass --comment \"nofpround\"\n# FMUL (by element) Scalar, single-precision and double-precision sz=0\n\n:fmul Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2331=0b010111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\tRd_FPR32 = Rn_FPR32 f* tmp1;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f809000/mask=xff80f400\n# CONSTRUCT x5fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8\n# AUNIT --inst x5fc09000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n# FMUL (by element) Scalar, single-precision and double-precision sz=1\n\n:fmul Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex\nis b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\tRd_FPR64 = Rn_FPR64 f* tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f009000/mask=xbfc0f400\n# CONSTRUCT x0f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2\n# AUNIT --inst x0f009000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# FMUL (by element) Vector, half-precision, Q=0\n\n:fmul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 &b_30=0 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1;\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1;\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1;\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f009000/mask=xbfc0f400\n# CONSTRUCT x4f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2\n# AUNIT --inst x4f009000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# FMUL (by element) Vector, half-precision, Q=1\n\n:fmul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 &b_30=1 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1;\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1;\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1;\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1;\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1;\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1;\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1;\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400\n# CONSTRUCT x4fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8\n# AUNIT --inst x4fc09000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n# Vector, single-precision and double-precision Q=1 and sz:L=10\n\n:fmul Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex\nis b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D f* tmp1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* tmp1;\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400\n# CONSTRUCT x0f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4\n# AUNIT --inst x0f809000/mask=xffc0f400 --rand sfp --status fail --comment \"nofpround\"\n# Vector, single-precision and double-precision Q=0 and sz:L=0x\n\n:fmul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1;\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400\n# CONSTRUCT x4f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4\n# AUNIT --inst x4f809000/mask=xffc0f400 --rand sfp --status fail --comment \"nofpround\"\n# Vector, single-precision and double-precision Q=1 and sz:L=0x\n\n:fmul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S f* tmp1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* tmp1;\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* tmp1;\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* tmp1;\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00\n# CONSTRUCT x6e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8\n# AUNIT --inst x6e60dc00/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fmul Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00\n# CONSTRUCT x2e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4\n# AUNIT --inst x2e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fmul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00\n# CONSTRUCT x6e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4\n# AUNIT --inst x6e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fmul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e401c00/mask=xbfe0fc00\n# CONSTRUCT x2e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2\n# AUNIT --inst x2e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=0 suf=VPR64.4H\n\n:fmul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e401c00/mask=xbfe0fc00\n# CONSTRUCT x6e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2\n# AUNIT --inst x6e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=1 suf=VPR128.8H\n\n:fmul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00\n# CONSTRUCT x1e600800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2\n# AUNIT --inst x1e600800/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fmul Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x0 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64 f* Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00\n# CONSTRUCT x1e200800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2\n# AUNIT --inst x1e200800/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fmul Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x0 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32 f* Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00\n# CONSTRUCT x1ee00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2\n# AUNIT --inst x1ee00800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fmul Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x0 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16 f* Rm_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400\n# CONSTRUCT x6fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8\n# AUNIT --inst x6fc09000/mask=xffe0f400 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x9 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D f* tmp1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* tmp1;\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400\n# CONSTRUCT x2f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4\n# AUNIT --inst x2f809000/mask=xffc0f400 --rand sfp --status fail --comment \"nofpround\"\n\n:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1;\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400\n# CONSTRUCT x6f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4\n# AUNIT --inst x6f809000/mask=xffc0f400 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* tmp1;\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* tmp1;\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* tmp1;\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f009000/mask=xffc0f400\n# CONSTRUCT x7f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2\n# AUNIT --inst x7f009000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar, half-precision variant\n\n:fmulx Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2231=0b0111111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\tRd_FPR16 = Rn_FPR16 f* tmp1;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f809000/mask=xff80f400\n# CONSTRUCT x7f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4\n# AUNIT --inst x7f809000/mask=xffc0f400 --rand sfp --status pass --comment \"nofpround\"\n# Scalar, single-precision and double-precision variant when sz=0 Ts=S V=32\n\n:fmulx Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2331=0b011111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\tRd_FPR32 = Rn_FPR32 f* tmp1;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f809000/mask=xff80f400\n# CONSTRUCT x7fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8\n# AUNIT --inst x7fc09000/mask=xffe0f400 --rand dfp --status pass --comment \"nofpround\"\n# Scalar, single-precision and double-precision variant when sz=1 Ts=D V=64\n\n:fmulx Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex\nis b_2331=0b011111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Re_VPR128.D & vIndex & Zd\n{\n\t# simd element Re_VPR128.D[vIndex] lane size 8\n\tlocal tmp1:8 = Re_VPR128.D.vIndex;\n\tRd_FPR64 = Rn_FPR64 f* tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f009000/mask=xbfc0f400\n# CONSTRUCT x2f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2\n# AUNIT --inst x2f009000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector, half-precision variant when Q = 0 suf=64.4H\n\n:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1;\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1;\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1;\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f009000/mask=xbfc0f400\n# CONSTRUCT x6f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2\n# AUNIT --inst x6f009000/mask=xffc0f400 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector, half-precision variant when Q = 1 suf=128.8H\n\n:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1;\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1;\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1;\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1;\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1;\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1;\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1;\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e20dc00/mask=xffa0fc00\n# CONSTRUCT x5e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2\n# AUNIT --inst x5e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1b & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_fmulx(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e20dc00/mask=xffa0fc00\n# CONSTRUCT x5e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2\n# AUNIT --inst x5e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1b & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_fmulx(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00\n# CONSTRUCT x4e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8\n# AUNIT --inst x4e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00\n# CONSTRUCT x0e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4\n# AUNIT --inst x0e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_fmulx(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00\n# CONSTRUCT x4e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4\n# AUNIT --inst x4e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e401c00/mask=xffe0fc00\n# CONSTRUCT x5e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2\n# AUNIT --inst x5e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision variant\n\n:fmulx Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01011110010 & b_1015=0b000111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16 f* Rm_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e401c00/mask=xbfe0fc00\n# CONSTRUCT x0e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2\n# AUNIT --inst x0e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 suf=64.4H\n\n:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e401c00/mask=xbfe0fc00\n# CONSTRUCT x4e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2\n# AUNIT --inst x4e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 suf=128.8H\n\n:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00\n# CONSTRUCT x6ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fneg@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@8\n# AUNIT --inst x6ee0f800/mask=xfffffc00 --rand dfp --status pass\n\n:fneg Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = f-(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = f-(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = f-(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00\n# CONSTRUCT x2ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fneg@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4\n# AUNIT --inst x2ea0f800/mask=xfffffc00 --rand sfp --status pass\n\n:fneg Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = f-(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = f-(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = f-(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00\n# CONSTRUCT x6ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fneg@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4\n# AUNIT --inst x6ea0f800/mask=xfffffc00 --rand sfp --status pass\n\n:fneg Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = f-(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = f-(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = f-(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = f-(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = f-(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ef8f800/mask=xbffffc00\n# CONSTRUCT x2ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fneg@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2\n# AUNIT --inst x2ef8f800/mask=xfffffc00 --rand hfp --status noqemu\n# Half-precision variant when Q=0 suf=64.4H\n\n:fneg Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b10111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = f-(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = f-(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = f-(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = f-(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = f-(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ef8f800/mask=xbffffc00\n# CONSTRUCT x6ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$fneg@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2\n# AUNIT --inst x6ef8f800/mask=xfffffc00 --rand hfp --status noqemu\n# Half-precision variant when Q=1 suf=128.8H\n\n:fneg Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b10111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = f-(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = f-(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = f-(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = f-(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = f-(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = f-(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = f-(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = f-(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = f-(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00\n# CONSTRUCT x1e614000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =fneg\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1\n# AUNIT --inst x1e614000/mask=xfffffc00 --rand dfp --status pass\n\n:fneg Rd_FPR64, Rn_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = f- Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00\n# CONSTRUCT x1e214000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =fneg\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1\n# AUNIT --inst x1e214000/mask=xfffffc00 --rand sfp --status pass\n\n:fneg Rd_FPR32, Rn_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = f- Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00\n# CONSTRUCT x1ee14000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =fneg\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1\n# AUNIT --inst x1ee14000/mask=xfffffc00 --rand hfp --status noqemu\n\n:fneg Rd_FPR16, Rn_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = f- Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000\n# CONSTRUCT x1f600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3\n# AUNIT --inst x1f600000/mask=xffe08000 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fnmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = (f-(Rn_FPR64 f* Rm_FPR64)) f- Ra_FPR64;\n\tzext_zd(Zd);\n}\n\n# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000\n# CONSTRUCT x1f200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3\n# AUNIT --inst x1f200000/mask=xffe08000 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fnmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = (f-(Rn_FPR32 f* Rm_FPR32)) f- Ra_FPR32;\n\tzext_zs(Zd);\n}\n\n# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000\n# CONSTRUCT x1fe00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3\n# AUNIT --inst x1fe00000/mask=xffe08000 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fnmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = (f-(Rn_FPR16 f* Rm_FPR16)) f- Ra_FPR16;\n\tzext_zh(Zd);\n}\n\n# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000\n# CONSTRUCT x1f608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3\n# AUNIT --inst x1f608000/mask=xffe08000 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:fnmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = (Rn_FPR64 f* Rm_FPR64) f- Ra_FPR64;\n\tzext_zd(Zd);\n}\n\n# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000\n# CONSTRUCT x1f208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3\n# AUNIT --inst x1f208000/mask=xffe08000 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:fnmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = (Rn_FPR32 f* Rm_FPR32) f- Ra_FPR32;\n\tzext_zs(Zd);\n}\n\n# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000\n# CONSTRUCT x1fe08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3\n# AUNIT --inst x1fe08000/mask=xffe08000 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fnmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = (Rn_FPR16 f* Rm_FPR16) f- Ra_FPR16;\n\tzext_zh(Zd);\n}\n\n# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00\n# CONSTRUCT x1e608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* =fneg\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2\n# AUNIT --inst x1e608800/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fnmul Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x8 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = Rn_FPR64 f* Rm_FPR64;\n\tRd_FPR64 = f- tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00\n# CONSTRUCT x1e208800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* =fneg\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2\n# AUNIT --inst x1e208800/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fnmul Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x8 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:4 = Rn_FPR32 f* Rm_FPR32;\n\tRd_FPR32 = f- tmp1;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00\n# CONSTRUCT x1ee08800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 f* =fneg\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2\n# AUNIT --inst x1ee08800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fnmul Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x8 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:2 = Rn_FPR16 f* Rm_FPR16;\n\tRd_FPR16 = f- tmp1;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00\n# CONSTRUCT x4ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@8\n# AUNIT --inst x4ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:frecpe Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_frecpe(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00\n# CONSTRUCT x0ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4\n# AUNIT --inst x0ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:frecpe Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_frecpe(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00\n# CONSTRUCT x4ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4\n# AUNIT --inst x4ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:frecpe Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_frecpe(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ea1d800/mask=xffbffc00\n# CONSTRUCT x5ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1\n# AUNIT --inst x5ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:frecpe Rd_FPR64, Rn_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_frecpe(Rn_FPR64);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ea1d800/mask=xffbffc00\n# CONSTRUCT x5ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1\n# AUNIT --inst x5ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:frecpe Rd_FPR32, Rn_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_frecpe(Rn_FPR32);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ef9d800/mask=xfffffc00\n# CONSTRUCT x5ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1\n# AUNIT --inst x5ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision variant\n\n:frecpe Rd_FPR16, Rn_FPR16\nis b_1031=0b0101111011111001110110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_frecpe(Rn_FPR16);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ef9d800/mask=xbffffc00\n# CONSTRUCT x0ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2\n# AUNIT --inst x0ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 suf=64.4H\n\n:frecpe Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111011111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_frecpe(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ef9d800/mask=xbffffc00\n# CONSTRUCT x4ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2\n# AUNIT --inst x4ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 suf=128.8H\n\n:frecpe Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111011111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_frecpe(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e20fc00/mask=xffa0fc00\n# CONSTRUCT x5e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2\n# AUNIT --inst x5e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:frecps Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1f & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_frecps(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e20fc00/mask=xffa0fc00\n# CONSTRUCT x5e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2\n# AUNIT --inst x5e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:frecps Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1f & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_frecps(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00\n# CONSTRUCT x4e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@8\n# AUNIT --inst x4e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n\n:frecps Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_frecps(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00\n# CONSTRUCT x0e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4\n# AUNIT --inst x0e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:frecps Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_frecps(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00\n# CONSTRUCT x4e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4\n# AUNIT --inst x4e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n\n:frecps Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_frecps(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e403c00/mask=xffe0fc00\n# CONSTRUCT x5e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2\n# AUNIT --inst x5e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision variant\n\n:frecps Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_2131=0b01011110010 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_frecps(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e403c00/mask=xbfe0fc00\n# CONSTRUCT x0e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2\n# AUNIT --inst x0e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 suf=64.4H\n\n:frecps Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_frecps(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e403c00/mask=xbfe0fc00\n# CONSTRUCT x4e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2\n# AUNIT --inst x4e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 suf=128.8H\n\n:frecps Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_frecps(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ef9f800/mask=xfffffc00\n# CONSTRUCT x5ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1\n# AUNIT --inst x5ef9f800/mask=xfffffc00 --rand hfp --status noqemu\n# Half-precision variant\n\n:frecpx Rd_FPR16, Rn_FPR16\nis b_1031=0b0101111011111001111110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_frecpx(Rn_FPR16);\n}\n\n# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ea1f800/mask=xffbffc00\n# CONSTRUCT x5ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1\n# AUNIT --inst x5ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop\n# Single-precision and double-precision variant when sz=0 suf=32\n\n:frecpx Rd_FPR32, Rn_FPR32\nis b_2331=0b010111101 & b_22=0 & b_1021=0b100001111110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_frecpx(Rn_FPR32);\n}\n\n# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ea1f800/mask=xffbffc00\n# CONSTRUCT x5ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1\n# AUNIT --inst x5ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop\n# Single-precision and double-precision variant when sz=1 suf=64\n\n:frecpx Rd_FPR64, Rn_FPR64\nis b_2331=0b010111101 & b_22=1 & b_1021=0b100001111110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_frecpx(Rn_FPR64);\n}\n\n# C7.2.140 FRINTA (vector) page C7-1313 line 76386 KEEPWITH\n\nfrint_vmode: \"a\" is b_29=1 & b_23=0 & b_12=0 { }\nfrint_vmode: \"i\" is b_29=1 & b_23=1 & b_12=1 { }\nfrint_vmode: \"m\" is b_29=0 & b_23=0 & b_12=1 { }\nfrint_vmode: \"n\" is b_29=0 & b_23=0 & b_12=0 { }\nfrint_vmode: \"p\" is b_29=0 & b_23=1 & b_12=0 { }\nfrint_vmode: \"x\" is b_29=1 & b_23=0 & b_12=1 { }\nfrint_vmode: \"z\" is b_29=0 & b_23=1 & b_12=1 { }\n\n# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e798800/mask=xbffffc00\n# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ef99800/mask=xbffffc00\n# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e799800/mask=xbffffc00\n# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e798800/mask=xbffffc00\n# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ef98800/mask=xbffffc00\n# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e799800/mask=xbffffc00\n# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ef99800/mask=xbffffc00\n# CONSTRUCT x0e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2\n# AUNIT --inst x0e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=0 suf=64.4H\n\n:frint^frint_vmode Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e798800/mask=xbffffc00\n# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ef99800/mask=xbffffc00\n# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e799800/mask=xbffffc00\n# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e798800/mask=xbffffc00\n# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ef98800/mask=xbffffc00\n# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e799800/mask=xbffffc00\n# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ef99800/mask=xbffffc00\n# CONSTRUCT x4e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2\n# AUNIT --inst x4e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=1 suf=128.8H\n\n:frint^frint_vmode Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00\n# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00\n# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00\n# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00\n# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00\n# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00\n# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00\n# CONSTRUCT x0e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4\n# AUNIT --inst x0e218800/mask=xdf7fec00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision and double-precision variant when sz=0 Q=0 suf=64.2S\n\n:frint^frint_vmode Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00\n# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00\n# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00\n# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00\n# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00\n# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00\n# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00\n# CONSTRUCT x4e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4\n# AUNIT --inst x4e218800/mask=xdf7fec00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision and double-precision variant when sz=0 Q=1 suf=128.4S\n\n:frint^frint_vmode Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00\n# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00\n# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00\n# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00\n# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00\n# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00\n# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00\n# CONSTRUCT x4e618800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$trunc@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@8\n# AUNIT --inst x4e618800/mask=xdf7fec00 --rand dfp --status fail --comment \"nofpround\"\n# Single-precision and double-precision variant when sz=1 Q=1 suf=128.2D\n\n:frint^frint_vmode Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b1 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.141 FRINTA (scalar) page C7-1315 line 76515 KEEPWITH\n# FP rounding instruction (not implemented)\n\nfrint_smode: \"a\" is b_1517=0b100 { }\nfrint_smode: \"i\" is b_1517=0b111 { }\nfrint_smode: \"m\" is b_1517=0b010 { }\nfrint_smode: \"n\" is b_1517=0b000 { }\nfrint_smode: \"p\" is b_1517=0b001 { }\nfrint_smode: \"x\" is b_1517=0b110 { }\nfrint_smode: \"z\" is b_1517=0b011 { }\n\n# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00\n# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00\n# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00\n# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00\n# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00\n# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00\n# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00\n# CONSTRUCT x1ee44000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1\n# AUNIT --inst x1ee44000/mask=xfffc7c00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when type = 11 suf=16\n\n:frint^frint_smode Rd_FPR16, Rn_FPR16\nis b_2431=0b00011110 & b_2223=0b11 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = trunc(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00\n# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00\n# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00\n# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00\n# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00\n# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00\n# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00\n# CONSTRUCT x1e244000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1\n# AUNIT --inst x1e244000/mask=xfffc7c00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision variant when type = 00 suf=32\n\n:frint^frint_smode Rd_FPR32, Rn_FPR32\nis b_2431=0b00011110 & b_2223=0b00 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = trunc(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00\n# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00\n# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00\n# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00\n# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00\n# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00\n# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00\n# CONSTRUCT x1e644000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =trunc\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1\n# AUNIT --inst x1e644000/mask=xfffc7c00 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision variant when type = 01 suf=64\n\n:frint^frint_smode Rd_FPR64, Rn_FPR64\nis b_2431=0b00011110 & b_2223=0b01 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = trunc(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ef9d800/mask=xfffffc00\n# CONSTRUCT x7ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1\n# AUNIT --inst x7ef9d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Scalar half precision variant when Q=1 sz=1 ba=11 bb=111 V=FPR16 esize=\n\n:frsqrte Rd_FPR16, Rn_FPR16\nis b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b111001110110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_frsqrte(Rn_FPR16);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ea1d800/mask=xffbffc00\n# CONSTRUCT x7ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1\n# AUNIT --inst x7ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=11 bb=100 V=FPR32 esize=\n\n:frsqrte Rd_FPR32, Rn_FPR32\nis b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=0 & b_1021=0b100001110110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_frsqrte(Rn_FPR32);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ea1d800/mask=xffbffc00\n# CONSTRUCT x7ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1\n# AUNIT --inst x7ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=11 bb=100 V=FPR64 esize=\n\n:frsqrte Rd_FPR64, Rn_FPR64\nis b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b100001110110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_frsqrte(Rn_FPR64);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ef9d800/mask=xbffffc00\n# CONSTRUCT x2ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2\n# AUNIT --inst x2ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 sz=1 ba=10 bb=111 V=VPR64.4H esize=@2\n\n:frsqrte Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_frsqrte(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ef9d800/mask=xbffffc00\n# CONSTRUCT x6ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2\n# AUNIT --inst x6ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 sz=1 ba=10 bb=111 V=VPR128.8H esize=@2\n\n:frsqrte Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_frsqrte(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00\n# CONSTRUCT x2ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4\n# AUNIT --inst x2ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Vector single-precision and double-precision variant when Q=0 sz=0 ba=10 bb=100 V=VPR64.2S esize=@4\n\n:frsqrte Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_frsqrte(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00\n# CONSTRUCT x6ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4\n# AUNIT --inst x6ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Vector single-precision and double-precision variant when Q=1 sz=0 ba=10 bb=100 V=VPR128.4S esize=@4\n\n:frsqrte Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_frsqrte(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00\n# CONSTRUCT x6ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@8\n# AUNIT --inst x6ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Vector single-precision and double-precision variant when Q=1 sz=1 ba=10 bb=100 V=VPR128.2D esize=@8\n\n:frsqrte Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001110110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_frsqrte(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ec03c00/mask=xffe0fc00\n# CONSTRUCT x5ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrts/1\n# AUNIT --inst x5ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Scalar half precision variant when Q=1 sz=1 ba=01 bb=0 bc=00 V=FPR16 esize=\n\n:frsqrts Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_frsqrts(Rn_FPR16);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ea0fc00/mask=xffa0fc00\n# CONSTRUCT x5ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2\n# AUNIT --inst x5ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=01 bb=1 bc=11 V=FPR32 esize=\n\n:frsqrts Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_frsqrts(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ea0fc00/mask=xffa0fc00\n# CONSTRUCT x5ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2\n# AUNIT --inst x5ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=01 bb=1 bc=11 V=FPR64 esize=\n\n:frsqrts Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_frsqrts(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ec03c00/mask=xbfe0fc00\n# CONSTRUCT x0ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2\n# AUNIT --inst x0ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 sz=1 ba=00 bb=0 bc=00 V=VPR64.4H esize=@2\n\n:frsqrts Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_frsqrts(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ec03c00/mask=xbfe0fc00\n# CONSTRUCT x4ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2\n# AUNIT --inst x4ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 sz=1 ba=00 bb=0 bc=00 V=VPR128.8H esize=@2\n\n:frsqrts Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_frsqrts(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00\n# CONSTRUCT x0ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4\n# AUNIT --inst x0ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Vector single-precision and double-precision variant when Q=0 sz=0 ba=00 bb=1 bc=11 V=VPR64.2S esize=@4\n\n:frsqrts Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_frsqrts(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00\n# CONSTRUCT x4ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4\n# AUNIT --inst x4ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Vector single-precision and double-precision variant when Q=1 sz=0 ba=00 bb=1 bc=11 V=VPR128.4S esize=@4\n\n:frsqrts Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_frsqrts(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00\n# CONSTRUCT x4ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@8\n# AUNIT --inst x4ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Vector single-precision and double-precision variant when Q=1 sz=1 ba=00 bb=1 bc=11 V=VPR128.2D esize=@8\n\n:frsqrts Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_frsqrts(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ef9f800/mask=xbffffc00\n# CONSTRUCT x2ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2\n# AUNIT --inst x2ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=0 sz=1 ba=111 esize=2 suf=VPR64.4H\n\n:fsqrt Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = sqrt(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = sqrt(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = sqrt(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = sqrt(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = sqrt(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ef9f800/mask=xbffffc00\n# CONSTRUCT x6ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2\n# AUNIT --inst x6ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=1 sz=1 ba=111 esize=2 suf=VPR128.8H\n\n:fsqrt Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = sqrt(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = sqrt(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = sqrt(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = sqrt(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = sqrt(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = sqrt(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = sqrt(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = sqrt(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = sqrt(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00\n# CONSTRUCT x2ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4\n# AUNIT --inst x2ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Single-precision and double-precision variant when Q=0 sz=0 ba=100 esize=4 suf=VPR64.2S\n\n:fsqrt Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = sqrt(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = sqrt(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = sqrt(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00\n# CONSTRUCT x6ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4\n# AUNIT --inst x6ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment \"nofpround\"\n# Single-precision and double-precision variant when Q=1 sz=0 ba=100 esize=4 suf=VPR128.4S\n\n:fsqrt Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = sqrt(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = sqrt(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = sqrt(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = sqrt(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = sqrt(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00\n# CONSTRUCT x6ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@8\n# AUNIT --inst x6ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment \"nofpround\"\n# Single-precision and double-precision variant when Q=1 sz=1 ba=100 esize=8 suf=VPR128.2D\n\n:fsqrt Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001111110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = sqrt(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = sqrt(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = sqrt(Rn_VPR128.2D[64,64]);\n}\n\n# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00\n# CONSTRUCT x1ee1c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sqrt/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1\n# AUNIT --inst x1ee1c000/mask=xfffffc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant\n\n:fsqrt Rd_FPR16, Rn_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = sqrt(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00\n# CONSTRUCT x1e21c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sqrt/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1\n# AUNIT --inst x1e21c000/mask=xfffffc00 --rand sfp --status fail --comment \"nofpround\"\n# Single-precision variant\n\n:fsqrt Rd_FPR32, Rn_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = sqrt(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00\n# CONSTRUCT x1e61c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sqrt/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1\n# AUNIT --inst x1e61c000/mask=xfffffc00 --rand dfp --status fail --comment \"nofpround\"\n# Double-precision variant\n\n:fsqrt Rd_FPR64, Rn_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = sqrt(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00\n# CONSTRUCT x4ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@8\n# AUNIT --inst x4ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00\n# CONSTRUCT x0ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4\n# AUNIT --inst x0ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00\n# CONSTRUCT x4ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4\n# AUNIT --inst x4ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment \"nofpround\"\n\n:fsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ec01400/mask=xbfe0fc00\n# CONSTRUCT x0ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2\n# AUNIT --inst x0ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=0 suf=VPR64.4H\n\n:fsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ec01400/mask=xbfe0fc00\n# CONSTRUCT x4ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$f-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2\n# AUNIT --inst x4ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n# Half-precision variant when Q=1 suf=VPR128.8H\n\n:fsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00\n# CONSTRUCT x1e603800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2\n# AUNIT --inst x1e603800/mask=xffe0fc00 --rand dfp --status pass --comment \"nofpround\"\n\n:fsub Rd_FPR64, Rn_FPR64, Rm_FPR64\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x3 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64 f- Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00\n# CONSTRUCT x1e203800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2\n# AUNIT --inst x1e203800/mask=xffe0fc00 --rand sfp --status pass --comment \"nofpround\"\n\n:fsub Rd_FPR32, Rn_FPR32, Rm_FPR32\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x3 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32 f- Rm_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00\n# CONSTRUCT x1ee03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =f-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2\n# AUNIT --inst x1ee03800/mask=xffe0fc00 --rand hfp --status noqemu --comment \"nofpround\"\n\n:fsub Rd_FPR16, Rn_FPR16, Rm_FPR16\nis m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x3 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = Rn_FPR16 f- Rm_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000\n# CONSTRUCT x2c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext\n# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1\n# AUNIT --inst x2c400000/mask=xffc00000 --status nomem\n\n:ldnp Rt_FPR32, Rt2_FPR32, addrPairIndexed\nis b_3031=0b00 & b_2229=0b10110001 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2\n{\n\tRt_FPR32 = * addrPairIndexed;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n\tlocal tmp1:8 = addrPairIndexed + 4;\n\tRt2_FPR32 = * tmp1;\n\tzext_zs(Zt2); # zero upper 28 bytes of Zt2\n}\n\n# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000\n# CONSTRUCT x6c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext\n# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1\n# AUNIT --inst x6c400000/mask=xffc00000 --status nomem\n\n:ldnp Rt_FPR64, Rt2_FPR64, addrPairIndexed\nis b_3031=0b01 & b_2229=0b10110001 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2\n{\n\tRt_FPR64 = * addrPairIndexed;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n\tlocal tmp1:8 = addrPairIndexed + 8;\n\tRt2_FPR64 = * tmp1;\n\tzext_zd(Zt2); # zero upper 24 bytes of Zt2\n}\n\n# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000\n# CONSTRUCT xac400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext\n# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1\n# AUNIT --inst xac400000/mask=xffc00000 --status nomem\n\n:ldnp Rt_FPR128, Rt2_FPR128, addrPairIndexed\nis b_3031=0b10 & b_2229=0b10110001 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2\n{\n\tRt_FPR128 = * addrPairIndexed;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n\tlocal tmp1:8 = addrPairIndexed + 16;\n\tRt2_FPR128 = * tmp1;\n\tzext_zq(Zt2); # zero upper 16 bytes of Zt2\n}\n\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000\n# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000\n# CONSTRUCT xac400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext\n# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1\n# AUNIT --inst xac400000/mask=xfe400000 --status nomem\n\n:ldp Rt_FPR128, Rt2_FPR128, addrPairIndexed\nis b_3031=0b10 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2\n{\n\tRt_FPR128 = * addrPairIndexed;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n\tlocal tmp1:8 = addrPairIndexed + 16;\n\tRt2_FPR128 = * tmp1;\n\tzext_zq(Zt2); # zero upper 16 bytes of Zt2\n}\n\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000\n# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000\n# CONSTRUCT x2c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext\n# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1\n# AUNIT --inst x2c400000/mask=xfe400000 --status nomem\n\n:ldp Rt_FPR32, Rt2_FPR32, addrPairIndexed\nis b_3031=0b00 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2\n{\n\tRt_FPR32 = * addrPairIndexed;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n\tlocal tmp1:8 = addrPairIndexed + 4;\n\tRt2_FPR32 = * tmp1;\n\tzext_zs(Zt2); # zero upper 28 bytes of Zt2\n}\n\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000\n# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000\n# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000\n# CONSTRUCT x6c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext\n# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1\n# AUNIT --inst x6c400000/mask=xfe400000 --status nomem\n\n:ldp Rt_FPR64, Rt2_FPR64, addrPairIndexed\nis b_3031=0b01 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2\n{\n\tRt_FPR64 = * addrPairIndexed;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n\tlocal tmp1:8 = addrPairIndexed + 8;\n\tRt2_FPR64 = * tmp1;\n\tzext_zd(Zt2); # zero upper 24 bytes of Zt2\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00\n# CONSTRUCT x3c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x3c400400/mask=xffe00400 --status nomem\n# Post- and Pre-index 8-bit variant when size==00 && opc==01 F=FPR8\n\n:ldr Rt_FPR8, addrIndexed\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt\n{\n\tRt_FPR8 = * addrIndexed;\n\tzext_zb(Zt); # zero upper 31 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00\n# CONSTRUCT x7c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x7c400400/mask=xffe00400 --status nomem\n# Post- and Pre-index 16-bit variant when size==01 && opc==01 F=FPR16\n\n:ldr Rt_FPR16, addrIndexed\nis b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt\n{\n\tRt_FPR16 = * addrIndexed;\n\tzext_zh(Zt); # zero upper 30 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00\n# CONSTRUCT xbc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst xbc400400/mask=xffe00400 --status nomem\n# Post- and Pre-index 32-bit variant when size==10 && opc==01 F=FPR32\n\n:ldr Rt_FPR32, addrIndexed\nis b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt\n{\n\tRt_FPR32 = * addrIndexed;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00\n# CONSTRUCT xfc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst xfc400400/mask=xffe00400 --status nomem\n# Post- and Pre-index 64-bit variant when size==11 && opc==01 F=FPR64\n\n:ldr Rt_FPR64, addrIndexed\nis b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt\n{\n\tRt_FPR64 = * addrIndexed;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00\n# CONSTRUCT x3cc00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x3cc00400/mask=xffe00400 --status nomem\n# Post- and Pre-index 128-bit variant when size==00 && opc==11 F=FPR128\n\n:ldr Rt_FPR128, addrIndexed\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt\n{\n\tRt_FPR128 = * addrIndexed;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000\n# CONSTRUCT x3d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x3d400000/mask=xffc00000 --status nomem\n# Unsigned offset 8-bit variant when size == 00 && opc == 01 F=FPR8\n\n:ldr Rt_FPR8, addrUIMM\nis b_3031=0b00 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR8 & addrUIMM & Zt\n{\n\tRt_FPR8 = * addrUIMM;\n\tzext_zb(Zt); # zero upper 31 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000\n# CONSTRUCT x7d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x7d400000/mask=xffc00000 --status nomem\n# Unsigned offset 16-bit variant when size == 01 && opc == 01 F=FPR16\n\n:ldr Rt_FPR16, addrUIMM\nis b_3031=0b01 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR16 & addrUIMM & Zt\n{\n\tRt_FPR16 = * addrUIMM;\n\tzext_zh(Zt); # zero upper 30 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000\n# CONSTRUCT xbd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst xbd400000/mask=xffc00000 --status nomem\n# Unsigned offset 32-bit variant when size == 10 && opc == 01 F=FPR32\n\n:ldr Rt_FPR32, addrUIMM\nis b_3031=0b10 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR32 & addrUIMM & Zt\n{\n\tRt_FPR32 = * addrUIMM;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000\n# CONSTRUCT xfd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst xfd400000/mask=xffc00000 --status nomem\n# Unsigned offset 64-bit variant when size == 11 && opc == 01 F=FPR64\n\n:ldr Rt_FPR64, addrUIMM\nis b_3031=0b11 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR64 & addrUIMM & Zt\n{\n\tRt_FPR64 = * addrUIMM;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n}\n\n# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000\n# CONSTRUCT x3dc00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x3dc00000/mask=xffc00000 --status nomem\n# Unsigned offset 128-bit variant when size == 00 && opc == 11 F=FPR128\n\n:ldr Rt_FPR128, addrUIMM\nis b_3031=0b00 & b_2429=0b111101 & b_2223=0b11 & Rt_FPR128 & addrUIMM & Zt\n{\n\tRt_FPR128 = * addrUIMM;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n}\n\n# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000\n# CONSTRUCT x5c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load:8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x5c000000/mask=xff000000 --status nomem\n\n:ldr Rt_FPR64, AddrLoc19\nis size.ldstr=1 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR64 & Zt\n{\n\tRt_FPR64 = *:8 AddrLoc19;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n}\n\n# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000\n# CONSTRUCT x9c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x9c000000/mask=xff000000 --status nomem\n\n:ldr Rt_FPR128, AddrLoc19\nis size.ldstr=2 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR128 & Zt\n{\n\tRt_FPR128 = *:16 AddrLoc19;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n}\n\n# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000\n# CONSTRUCT x1c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load:4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1\n# AUNIT --inst x1c000000/mask=xff000000 --status nomem\n\n:ldr Rt_FPR32, AddrLoc19\nis size.ldstr=0 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR32 & Zt\n{\n\tRt_FPR32 = *:4 AddrLoc19;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n}\n\n# C7.2.178 LDR (register, SIMD&FP) page C7-1411 line 82199 KEEPWITH\n\nextend_amount: \"\" is b_3031=0b00 & b_23=0 & b_12=0 { export 0:1; }\nextend_amount: \" #0\" is b_3031=0b00 & b_23=0 & b_12=1 { export 0:1; }\nextend_amount: \"\" is b_3031=0b01 & b_23=0 & b_12=0 { export 0:1; }\nextend_amount: \" #1\" is b_3031=0b01 & b_23=0 & b_12=1 { export 1:1; }\nextend_amount: \"\" is b_3031=0b10 & b_23=0 & b_12=0 { export 0:1; }\nextend_amount: \" #2\" is b_3031=0b10 & b_23=0 & b_12=1 { export 2:1; }\nextend_amount: \"\" is b_3031=0b11 & b_23=0 & b_12=0 { export 0:1; }\nextend_amount: \" #3\" is b_3031=0b11 & b_23=0 & b_12=1 { export 3:1; }\nextend_amount: \"\" is b_3031=0b00 & b_23=1 & b_12=0 { export 0:1; }\nextend_amount: \" #4\" is b_3031=0b00 & b_23=1 & b_12=1 { export 4:1; }\n\nextend_spec: \", uxtw\" is b_1315=0b010 & Rm_GPR32 { local tmp:8 = zext(Rm_GPR32); export tmp; }\nextend_spec: \", sxtw\" is b_1315=0b110 & Rm_GPR32 { local tmp:8 = sext(Rm_GPR32); export tmp; }\nextend_spec: \", sxtx\" is b_1315=0b111 & Rm_GPR64 { export Rm_GPR64; }\nextend_spec: \", lsl\" is b_1315=0b011 & b_12=1 & Rm_GPR64 { export Rm_GPR64; }\t# same as uxtx\nextend_spec: \"\" is b_1315=0b011 & b_12=0 & Rm_GPR64 { export Rm_GPR64; }\t# same as uxtx\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x3c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x3c600800/mask=xffe02c00 --status nomem\n# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32\n\n:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR8 = * tmp2;\n\tzext_zb(Zt); # zero upper 31 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x3c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x3c602800/mask=xffe02c00 --status nomem\n# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64\n\n:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR8 = * tmp2;\n\tzext_zb(Zt); # zero upper 31 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x3c606800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x3c606800/mask=xffe0ec00 --status nomem\n# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64\n\n:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR8 = * tmp2;\n\tzext_zb(Zt); # zero upper 31 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x7c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x7c600800/mask=xffe02c00 --status nomem\n# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=0 F=FPR16 G=GPR32\n\n:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR16 = * tmp2;\n\tzext_zh(Zt); # zero upper 30 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x7c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x7c602800/mask=xffe02c00 --status nomem\n# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=1 F=FPR16 G=GPR64\n\n:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR16 = * tmp2;\n\tzext_zh(Zt); # zero upper 30 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT xbc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst xbc600800/mask=xffe02c00 --status nomem\n# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=0 F=FPR32 G=GPR32\n\n:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR32 = * tmp2;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT xbc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst xbc602800/mask=xffe02c00 --status nomem\n# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=1 F=FPR32 G=GPR64\n\n:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR32 = * tmp2;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT xfc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst xfc600800/mask=xffe02c00 --status nomem\n# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=0 F=FPR64 G=GPR32\n\n:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR64 = * tmp2;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT xfc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst xfc602800/mask=xffe02c00 --status nomem\n# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=1 F=FPR64 G=GPR64\n\n:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR64 = * tmp2;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x3ce00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x3ce00800/mask=xffe02c00 --status nomem\n# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=0 F=FPR128 G=GPR32\n\n:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR128 = * tmp2;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n}\n\n# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00\n# CONSTRUCT x3ce02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load\n# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3\n# AUNIT --inst x3ce02800/mask=xffe02c00 --status nomem\n# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=1 F=FPR128 G=GPR64\n\n:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\tRt_FPR128 = * tmp2;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n}\n\n# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00\n# CONSTRUCT x3cc00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1\n# AUNIT --inst x3cc00000/mask=xffe00c00 --status nomem\n\n:ldur Rt_FPR128, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128 & Zt\n{\n\tRt_FPR128 = * addrIndexed;\n\tzext_zq(Zt); # zero upper 16 bytes of Zt\n}\n\n# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00\n# CONSTRUCT x7c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1\n# AUNIT --inst x7c400000/mask=xffe00c00 --status nomem\n\n:ldur Rt_FPR16, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR16 & Zt\n{\n\tRt_FPR16 = * addrIndexed;\n\tzext_zh(Zt); # zero upper 30 bytes of Zt\n}\n\n# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00\n# CONSTRUCT xbc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1\n# AUNIT --inst xbc400000/mask=xffe00c00 --status nomem\n\n:ldur Rt_FPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32 & Zt\n{\n\tRt_FPR32 = * addrIndexed;\n\tzext_zs(Zt); # zero upper 28 bytes of Zt\n}\n\n# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00\n# CONSTRUCT xfc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1\n# AUNIT --inst xfc400000/mask=xffe00c00 --status nomem\n\n:ldur Rt_FPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64 & Zt\n{\n\tRt_FPR64 = * addrIndexed;\n\tzext_zd(Zt); # zero upper 24 bytes of Zt\n}\n\n# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00\n# CONSTRUCT x3c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =load\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1\n# AUNIT --inst x3c400000/mask=xffe00c00 --status nomem\n\n:ldur Rt_FPR8, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8 & Zt\n{\n\tRt_FPR8 = * addrIndexed;\n\tzext_zb(Zt); # zero upper 31 bytes of Zt\n}\n\n# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400\n# CONSTRUCT x2f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4\n# AUNIT --inst x2f800000/mask=xffc0f400 --status pass\n\n:mla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & vIndex & Re_VPR128.S & b_1215=0x0 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400\n# CONSTRUCT x2f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2\n# AUNIT --inst x2f400000/mask=xffc0f400 --status pass\n\n:mla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400\n# CONSTRUCT x6f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4\n# AUNIT --inst x6f800000/mask=xffc0f400 --status pass\n\n:mla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x0 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400\n# CONSTRUCT x6f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2\n# AUNIT --inst x6f400000/mask=xffc0f400 --status pass\n\n:mla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00\n# CONSTRUCT x4e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1\n# AUNIT --inst x4e209400/mask=xffe0fc00 --status pass\n\n:mla Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00\n# CONSTRUCT x0ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4\n# AUNIT --inst x0ea09400/mask=xffe0fc00 --status pass\n\n:mla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00\n# CONSTRUCT x0e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2\n# AUNIT --inst x0e609400/mask=xffe0fc00 --status pass\n\n:mla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00\n# CONSTRUCT x4ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4\n# AUNIT --inst x4ea09400/mask=xffe0fc00 --status pass\n\n:mla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00\n# CONSTRUCT x0e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1\n# AUNIT --inst x0e209400/mask=xffe0fc00 --status pass\n\n:mla Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00\n# CONSTRUCT x4e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2\n# AUNIT --inst x4e609400/mask=xffe0fc00 --status pass\n\n:mla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400\n# CONSTRUCT x2f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4\n# AUNIT --inst x2f804000/mask=xffc0f400 --status pass\n\n:mls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400\n# CONSTRUCT x2f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2\n# AUNIT --inst x2f404000/mask=xffc0f400 --status pass\n\n:mls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400\n# CONSTRUCT x6f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4\n# AUNIT --inst x6f804000/mask=xffc0f400 --status pass\n\n:mls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400\n# CONSTRUCT x6f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $* &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2\n# AUNIT --inst x6f404000/mask=xffc0f400 --status pass\n\n:mls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00\n# CONSTRUCT x6e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1\n# AUNIT --inst x6e209400/mask=xffe0fc00 --status pass\n\n:mls Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B - TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] - TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] - TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] - TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] - TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] - TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] - TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] - TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] - TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] - TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] - TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] - TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] - TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] - TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] - TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] - TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] - TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00\n# CONSTRUCT x2ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4\n# AUNIT --inst x2ea09400/mask=xffe0fc00 --status pass\n\n:mls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00\n# CONSTRUCT x2e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2\n# AUNIT --inst x2e609400/mask=xffe0fc00 --status pass\n\n:mls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00\n# CONSTRUCT x6ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4\n# AUNIT --inst x6ea09400/mask=xffe0fc00 --status pass\n\n:mls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00\n# CONSTRUCT x2e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1\n# AUNIT --inst x2e209400/mask=xffe0fc00 --status pass\n\n:mls Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B - TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] - TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] - TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] - TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] - TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] - TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] - TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] - TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] - TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00\n# CONSTRUCT x6e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2\n# AUNIT --inst x6e609400/mask=xffe0fc00 --status pass\n\n:mls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400\n# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400\n# CONSTRUCT x6e010400/mask=xffe18400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2 imm_neon_uimm4:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1\n# AUNIT --inst x6e010400/mask=xffe18400 --status pass\n\n:mov Rd_VPR128.B.imm_neon_uimm4, Rn_VPR128.B.immN_neon_uimm4\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & Rn_VPR128.B.immN_neon_uimm4 & immN_neon_uimm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd\n{\n\t# simd element Rn_VPR128[immN_neon_uimm4] lane size 1\n\tlocal tmp1:1 = Rn_VPR128.B.immN_neon_uimm4;\n\t# simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1)\n\tRd_VPR128.B.imm_neon_uimm4 = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400\n# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400\n# CONSTRUCT x6e080400/mask=xffef8400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8\n# AUNIT --inst x6e080400/mask=xffef8400 --status pass\n\n:mov Rd_VPR128.D.imm_neon_uimm1, Rn_VPR128.D.immN_neon_uimm1\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & Rn_VPR128.D.immN_neon_uimm1 & immN_neon_uimm1 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd\n{\n\t# simd element Rn_VPR128[immN_neon_uimm1] lane size 8\n\tlocal tmp1:8 = Rn_VPR128.D.immN_neon_uimm1;\n\t# simd copy Rd_VPR128 element imm_neon_uimm1:1 = tmp1 (lane size 8)\n\tRd_VPR128.D.imm_neon_uimm1 = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400\n# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400\n# CONSTRUCT x6e020400/mask=xffe38400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2 imm_neon_uimm3:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2\n# AUNIT --inst x6e020400/mask=xffe38400 --status pass\n\n:mov Rd_VPR128.H.imm_neon_uimm3, Rn_VPR128.H.immN_neon_uimm3\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & Rn_VPR128.H.immN_neon_uimm3 & immN_neon_uimm3 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd\n{\n\t# simd element Rn_VPR128[immN_neon_uimm3] lane size 2\n\tlocal tmp1:2 = Rn_VPR128.H.immN_neon_uimm3;\n\t# simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2)\n\tRd_VPR128.H.imm_neon_uimm3 = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400\n# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400\n# CONSTRUCT x6e040400/mask=xffe78400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@4\n# AUNIT --inst x6e040400/mask=xffe78400 --status pass\n\n:mov Rd_VPR128.S.imm_neon_uimm2, Rn_VPR128.S.immN_neon_uimm2\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & Rn_VPR128.S.immN_neon_uimm2 & immN_neon_uimm2 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd\n{\n\t# simd element Rn_VPR128[immN_neon_uimm2] lane size 4\n\tlocal tmp1:4 = Rn_VPR128.S.immN_neon_uimm2;\n\t# simd copy Rd_VPR128 element imm_neon_uimm2:1 = tmp1 (lane size 4)\n\tRd_VPR128.S.imm_neon_uimm2 = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00\n# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00\n# CONSTRUCT x4e011c00/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2[0]:1 imm_neon_uimm4:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1\n# AUNIT --inst x4e011c00/mask=xffe1fc00 --status pass\n\n:mov Rd_VPR128.B.imm_neon_uimm4, Rn_GPR32\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd\n{\n\tlocal tmp1:1 = Rn_GPR32[0,8];\n\t# simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1)\n\tRd_VPR128.B.imm_neon_uimm4 = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00\n# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00\n# CONSTRUCT x4e081c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8\n# AUNIT --inst x4e081c00/mask=xffeffc00 --status pass\n\n:mov Rd_VPR128.D.imm_neon_uimm1, Rn_GPR64\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR64 & Rd_VPR128 & Zd\n{\n\t# simd copy Rd_VPR128 element imm_neon_uimm1:1 = Rn_GPR64 (lane size 8)\n\tRd_VPR128.D.imm_neon_uimm1 = Rn_GPR64;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00\n# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00\n# CONSTRUCT x4e021c00/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO Rd_VPR128 ARG2[0]:2 imm_neon_uimm3:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2\n# AUNIT --inst x4e021c00/mask=xffe3fc00 --status pass\n\n:mov Rd_VPR128.H.imm_neon_uimm3, Rn_GPR32\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd\n{\n\tlocal tmp1:2 = Rn_GPR32[0,16];\n\t# simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2)\n\tRd_VPR128.H.imm_neon_uimm3 = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00\n# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00\n# CONSTRUCT x4e041c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO(force-primitive) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy\n# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@2\n# AUNIT --inst x4e041c00/mask=xffe7fc00 --status pass\n\n:mov Rd_VPR128.S.imm_neon_uimm2, Rn_GPR32\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd\n{\n\t# simd copy Rd_VPR128 element imm_neon_uimm2:1 = Rn_GPR32 (lane size 4)\n\tRd_VPR128.S.imm_neon_uimm2 = Rn_GPR32;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00\n# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00\n# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1\n# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass\n\n:mov Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Rn=Rm & Zd\n{\n\tRd_VPR128.16B = Rn_VPR128.16B;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00\n# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00\n# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1\n# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass\n\n:mov Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Rn=Rm & Zd\n{\n\tRd_VPR64.8B = Rn_VPR64.8B;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.203 MOV (to general) page C7-2488 line 145671 MATCH x0e003c00/mask=xbfe3fc00\n# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00\n# CONSTRUCT x0e043c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@4\n# AUNIT --inst x0e043c00/mask=xffe7fc00 --status pass\n\n:mov Rd_GPR32, Rn_VPR128.S.imm_neon_uimm2\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128\n{\n\t# simd element Rn_VPR128[imm_neon_uimm2] lane size 4\n\tlocal tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;\n\tRd_GPR32 = tmp1;\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.203 MOV (to general) page C7-2488 line 145671 MATCH x0e003c00/mask=xbfe3fc00\n# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00\n# CONSTRUCT x4e083c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@8\n# AUNIT --inst x4e083c00/mask=xffeffc00 --status pass\n\n:mov Rd_GPR64, Rn_VPR128.D.imm_neon_uimm1\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm1] lane size 8\n\tlocal tmp1:8 = Rn_VPR128.D.imm_neon_uimm1;\n\tRd_GPR64 = tmp1;\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x2f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1\n# AUNIT --inst x2f00e400/mask=xfff8fc00 --status pass\n# MOVI 64-bit scalar variant when datasize=64 q == 0 && op == 1 && cmode == 1110\n\n:movi Rd_FPR64, Imm_neon_uimm8Shift\nis b_31=0 & b_30=0 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Imm_neon_uimm8Shift:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x4f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:1 &=$dup\n# SMACRO(pseudo) ARG1 ARG2:1 =NEON_movi/1@1\n# AUNIT --inst x4f00e400/mask=xfff8fc00 --status pass\n# MOVI 8-bit variant when datasize=128 q == 1 && op == 0 && cmode == 0b1110\n\n:movi Rd_VPR128.16B, Imm_neon_uimm8Shift\nis b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.16B & Zd\n{\n\t# simd duplicate Rd_VPR128.16B = all elements Imm_neon_uimm8Shift:1 (lane size 1)\n\tRd_VPR128.16B[0,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[8,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[16,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[24,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[32,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[40,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[48,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[56,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[64,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[72,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[80,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[88,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[96,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[104,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[112,8] = Imm_neon_uimm8Shift:1;\n\tRd_VPR128.16B[120,8] = Imm_neon_uimm8Shift:1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x6f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2 =var:8 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@8\n# AUNIT --inst x6f00e400/mask=xfff8fc00 --status pass\n# MOVI 64-bit vector variant when datasize=128 q == 1 && op == 1 && cmode == 1110\n\n:movi Rd_VPR128.2D, Imm_neon_uimm8Shift\nis b_31=0 & b_30=1 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = Imm_neon_uimm8Shift;\n\t# simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8)\n\tRd_VPR128.2D[0,64] = tmp1;\n\tRd_VPR128.2D[64,64] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x0f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@1\n# AUNIT --inst x0f00e400/mask=xfff8fc00 --status pass\n# MOVI 8-bit variant when datasize=64 q == 0 && op == 0 && cmode == 1110\n\n:movi Rd_VPR64.8B, Imm_neon_uimm8Shift\nis b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = Imm_neon_uimm8Shift:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x0f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4\n# AUNIT --inst x0f000400/mask=xfff89c00 --status pass\n# MOVI 32-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 0xx0\n\n:movi Rd_VPR64.2S, Imm_neon_uimm8Shift\nis b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = Imm_neon_uimm8Shift:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x0f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2\n# AUNIT --inst x0f008400/mask=xfff8dc00 --status pass\n# MOVI 16-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 10x0\n\n:movi Rd_VPR64.4H, Imm_neon_uimm8Shift\nis b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = Imm_neon_uimm8Shift:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x4f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2:4 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4\n# AUNIT --inst x4f000400/mask=xfff89c00 --status pass\n# MOVI 32-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 0xx0\n\n:movi Rd_VPR128.4S, Imm_neon_uimm8Shift\nis b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd\n{\n\t# simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4)\n\tRd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x4f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:2 &=$dup\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2\n# AUNIT --inst x4f008400/mask=xfff8dc00 --status pass\n# MOVI 16-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 10x0\n\n:movi Rd_VPR128.8H, Imm_neon_uimm8Shift\nis b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.8H & Zd\n{\n\t# simd duplicate Rd_VPR128.8H = all elements Imm_neon_uimm8Shift:2 (lane size 2)\n\tRd_VPR128.8H[0,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[16,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[32,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[48,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[64,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[80,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[96,16] = Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[112,16] = Imm_neon_uimm8Shift:2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# CONSTRUCT x0f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =\n# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4\n# AUNIT --inst x0f00c400/mask=xfff8ec00 --status pass\n# MOVI 32-bit shifting ones variant when datasize=64 q == 0 && op == 0 && cmode == 110x\n\n:movi Rd_VPR64.2S, Imm_neon_uimm8Shift\nis b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = Imm_neon_uimm8Shift:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# CONSTRUCT x4f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 &=$dup\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_movi/1@4\n# AUNIT --inst x4f00c400/mask=xfff8ec00 --status pass\n# MOVI 32-bit shifting ones variant when datasize=128 q == 1 && op == 0 && cmode == 110x\n\n:movi Rd_VPR128.4S, Imm_neon_uimm8Shift\nis b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd\n{\n\t# simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4)\n\tRd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400\n# CONSTRUCT x0f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4\n# AUNIT --inst x0f808000/mask=xffc0f400 --status pass\n\n:mul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S * tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * tmp1;\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400\n# CONSTRUCT x0f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2\n# AUNIT --inst x0f408000/mask=xffc0f400 --status pass\n\n:mul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H * tmp1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * tmp1;\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * tmp1;\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * tmp1;\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400\n# CONSTRUCT x4f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4\n# AUNIT --inst x4f808000/mask=xffc0f400 --status pass\n\n:mul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp1:4 = Re_VPR128.S.vIndex;\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S * tmp1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * tmp1;\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * tmp1;\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * tmp1;\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400\n# CONSTRUCT x4f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2\n# AUNIT --inst x4f408000/mask=xffc0f400 --status pass\n\n:mul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H * tmp1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * tmp1;\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * tmp1;\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * tmp1;\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * tmp1;\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * tmp1;\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * tmp1;\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * tmp1;\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00\n# CONSTRUCT x4e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1\n# AUNIT --inst x4e209c00/mask=xffe0fc00 --status pass\n\n:mul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00\n# CONSTRUCT x0ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4\n# AUNIT --inst x0ea09c00/mask=xffe0fc00 --status pass\n\n:mul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x13 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00\n# CONSTRUCT x0e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2\n# AUNIT --inst x0e609c00/mask=xffe0fc00 --status pass\n\n:mul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x13 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00\n# CONSTRUCT x4ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4\n# AUNIT --inst x4ea09c00/mask=xffe0fc00 --status pass\n\n:mul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00\n# CONSTRUCT x0e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1\n# AUNIT --inst x0e209c00/mask=xffe0fc00 --status pass\n\n:mul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00\n# CONSTRUCT x4e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2\n# AUNIT --inst x4e609c00/mask=xffe0fc00 --status pass\n\n:mul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.207 MVN page C7-2497 line 146183 MATCH x2e205800/mask=xbffffc00\n# C7.2.210 NOT page C7-2503 line 146536 MATCH x2e205800/mask=xbffffc00\n# CONSTRUCT x6e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$~@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1\n# AUNIT --inst x6e205800/mask=xfffffc00 --status pass\n\n:mvn Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = ~(Rn_VPR128.16B) on lane size 1\n\tRd_VPR128.16B[0,8] = ~(Rn_VPR128.16B[0,8]);\n\tRd_VPR128.16B[8,8] = ~(Rn_VPR128.16B[8,8]);\n\tRd_VPR128.16B[16,8] = ~(Rn_VPR128.16B[16,8]);\n\tRd_VPR128.16B[24,8] = ~(Rn_VPR128.16B[24,8]);\n\tRd_VPR128.16B[32,8] = ~(Rn_VPR128.16B[32,8]);\n\tRd_VPR128.16B[40,8] = ~(Rn_VPR128.16B[40,8]);\n\tRd_VPR128.16B[48,8] = ~(Rn_VPR128.16B[48,8]);\n\tRd_VPR128.16B[56,8] = ~(Rn_VPR128.16B[56,8]);\n\tRd_VPR128.16B[64,8] = ~(Rn_VPR128.16B[64,8]);\n\tRd_VPR128.16B[72,8] = ~(Rn_VPR128.16B[72,8]);\n\tRd_VPR128.16B[80,8] = ~(Rn_VPR128.16B[80,8]);\n\tRd_VPR128.16B[88,8] = ~(Rn_VPR128.16B[88,8]);\n\tRd_VPR128.16B[96,8] = ~(Rn_VPR128.16B[96,8]);\n\tRd_VPR128.16B[104,8] = ~(Rn_VPR128.16B[104,8]);\n\tRd_VPR128.16B[112,8] = ~(Rn_VPR128.16B[112,8]);\n\tRd_VPR128.16B[120,8] = ~(Rn_VPR128.16B[120,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.207 MVN page C7-2497 line 146183 MATCH x2e205800/mask=xbffffc00\n# C7.2.210 NOT page C7-2503 line 146536 MATCH x2e205800/mask=xbffffc00\n# CONSTRUCT x2e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$~@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1\n# AUNIT --inst x2e205800/mask=xfffffc00 --status pass\n\n:mvn Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = ~(Rn_VPR64.8B) on lane size 1\n\tRd_VPR64.8B[0,8] = ~(Rn_VPR64.8B[0,8]);\n\tRd_VPR64.8B[8,8] = ~(Rn_VPR64.8B[8,8]);\n\tRd_VPR64.8B[16,8] = ~(Rn_VPR64.8B[16,8]);\n\tRd_VPR64.8B[24,8] = ~(Rn_VPR64.8B[24,8]);\n\tRd_VPR64.8B[32,8] = ~(Rn_VPR64.8B[32,8]);\n\tRd_VPR64.8B[40,8] = ~(Rn_VPR64.8B[40,8]);\n\tRd_VPR64.8B[48,8] = ~(Rn_VPR64.8B[48,8]);\n\tRd_VPR64.8B[56,8] = ~(Rn_VPR64.8B[56,8]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x2f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 ~ &=$dup\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4\n# AUNIT --inst x2f000400/mask=xfff89c00 --status pass\n\n:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift\nis b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & Imm_neon_uimm8Shift & b_1012=1 & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = ~ Imm_neon_uimm8Shift:4;\n\t# simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)\n\tRd_VPR64.2S[0,32] = tmp1;\n\tRd_VPR64.2S[32,32] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x2f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:2 ~ &=$dup\n# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2\n# AUNIT --inst x2f008400/mask=xfff8dc00 --status pass\n\n:mvni Rd_VPR64.4H, Imm_neon_uimm8Shift\nis b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR64.4H & Zd\n{\n\tlocal tmp1:2 = ~ Imm_neon_uimm8Shift:2;\n\t# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)\n\tRd_VPR64.4H[0,16] = tmp1;\n\tRd_VPR64.4H[16,16] = tmp1;\n\tRd_VPR64.4H[32,16] = tmp1;\n\tRd_VPR64.4H[48,16] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x6f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 ~ &=$dup\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4\n# AUNIT --inst x6f000400/mask=xfff89c00 --status pass\n\n:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=1 & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = ~ Imm_neon_uimm8Shift:4;\n\t# simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)\n\tRd_VPR128.4S[0,32] = tmp1;\n\tRd_VPR128.4S[32,32] = tmp1;\n\tRd_VPR128.4S[64,32] = tmp1;\n\tRd_VPR128.4S[96,32] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x6f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:2 ~ &=$dup\n# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2\n# AUNIT --inst x6f008400/mask=xfff8dc00 --status pass\n\n:mvni Rd_VPR128.8H, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR128.8H & Zd\n{\n\tlocal tmp1:2 = ~ Imm_neon_uimm8Shift:2;\n\t# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)\n\tRd_VPR128.8H[0,16] = tmp1;\n\tRd_VPR128.8H[16,16] = tmp1;\n\tRd_VPR128.8H[32,16] = tmp1;\n\tRd_VPR128.8H[48,16] = tmp1;\n\tRd_VPR128.8H[64,16] = tmp1;\n\tRd_VPR128.8H[80,16] = tmp1;\n\tRd_VPR128.8H[96,16] = tmp1;\n\tRd_VPR128.8H[112,16] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# CONSTRUCT x2f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 ~ &=$dup\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4\n# AUNIT --inst x2f00c400/mask=xfff8ec00 --status pass\n\n:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift\nis b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = ~ Imm_neon_uimm8Shift:4;\n\t# simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)\n\tRd_VPR64.2S[0,32] = tmp1;\n\tRd_VPR64.2S[32,32] = tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00\n# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# CONSTRUCT x6f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 ~ &=$dup\n# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4\n# AUNIT --inst x6f00c400/mask=xfff8ec00 --status pass\n\n:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = ~ Imm_neon_uimm8Shift:4;\n\t# simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)\n\tRd_VPR128.4S[0,32] = tmp1;\n\tRd_VPR128.4S[32,32] = tmp1;\n\tRd_VPR128.4S[64,32] = tmp1;\n\tRd_VPR128.4S[96,32] = tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x7e20b800/mask=xff3ffc00\n# CONSTRUCT x7ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =2comp\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1\n# AUNIT --inst x7ee0b800/mask=xfffffc00 --status pass\n\n:neg Rd_VPR64, Rn_VPR64\nis b_3131=0 & q=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64 & Rd_VPR64 & Zd\n{\n\tRd_VPR64 = - Rn_VPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x2e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1\n# AUNIT --inst x2e20b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = -Rn_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = -Rn_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = -Rn_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = -Rn_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = -Rn_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = -Rn_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = -Rn_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = -Rn_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = -Rn_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x6e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1\n# AUNIT --inst x6e20b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = -Rn_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = -Rn_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = -Rn_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = -Rn_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = -Rn_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = -Rn_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = -Rn_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = -Rn_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = -Rn_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = -Rn_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = -Rn_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = -Rn_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = -Rn_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = -Rn_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = -Rn_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = -Rn_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = -Rn_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x2e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2\n# AUNIT --inst x2e60b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR64.4H, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = -Rn_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = -Rn_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = -Rn_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = -Rn_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = -Rn_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x6e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2\n# AUNIT --inst x6e60b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR128.8H, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = -Rn_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = -Rn_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = -Rn_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = -Rn_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = -Rn_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = -Rn_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = -Rn_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = -Rn_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = -Rn_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x2ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4\n# AUNIT --inst x2ea0b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = -Rn_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = -Rn_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = -Rn_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x6ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4\n# AUNIT --inst x6ea0b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = -Rn_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = -Rn_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = -Rn_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = -Rn_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = -Rn_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00\n# CONSTRUCT x6ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@8\n# AUNIT --inst x6ee0b800/mask=xfffffc00 --status nopcodeop\n\n:neg Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = -Rn_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = -Rn_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = -Rn_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.211 ORN (vector) page C7-2505 line 146624 MATCH x0ee01c00/mask=xbfe0fc00\n# CONSTRUCT x4ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1\n# AUNIT --inst x4ee01c00/mask=xffe0fc00 --status pass\n\n:orn Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1\n\tTMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]);\n\tTMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]);\n\tTMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]);\n\tTMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]);\n\tTMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]);\n\tTMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]);\n\tTMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]);\n\tTMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]);\n\tTMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]);\n\tTMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]);\n\tTMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]);\n\tTMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]);\n\tTMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]);\n\tTMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]);\n\tTMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]);\n\tTMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]);\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.211 ORN (vector) page C7-2505 line 146624 MATCH x0ee01c00/mask=xbfe0fc00\n# CONSTRUCT x0ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1\n# AUNIT --inst x0ee01c00/mask=xffe0fc00 --status pass\n\n:orn Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1\n\tTMPD1[0,8] = ~(Rm_VPR64.8B[0,8]);\n\tTMPD1[8,8] = ~(Rm_VPR64.8B[8,8]);\n\tTMPD1[16,8] = ~(Rm_VPR64.8B[16,8]);\n\tTMPD1[24,8] = ~(Rm_VPR64.8B[24,8]);\n\tTMPD1[32,8] = ~(Rm_VPR64.8B[32,8]);\n\tTMPD1[40,8] = ~(Rm_VPR64.8B[40,8]);\n\tTMPD1[48,8] = ~(Rm_VPR64.8B[48,8]);\n\tTMPD1[56,8] = ~(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B | TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x0f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 &=$|@4\n# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4\n# AUNIT --inst x0f001400/mask=xfff89c00 --status pass\n\n:orr Rd_VPR64.2S, Imm_neon_uimm8Shift\nis b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S | Imm_neon_uimm8Shift:4 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] | Imm_neon_uimm8Shift:4;\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] | Imm_neon_uimm8Shift:4;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x0f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:2 &=$|@2\n# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orn/2@2\n# AUNIT --inst x0f009400/mask=xfff8dc00 --status pass\n\n:orr Rd_VPR64.4H, Imm_neon_uimm8Shift\nis b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H | Imm_neon_uimm8Shift:2 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] | Imm_neon_uimm8Shift:2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x4f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:4 &=$|\n# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4\n# AUNIT --inst x4f001400/mask=xfff89c00 --status pass\n\n:orr Rd_VPR128.4S, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S | Imm_neon_uimm8Shift:4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] | Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] | Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] | Imm_neon_uimm8Shift:4;\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] | Imm_neon_uimm8Shift:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00\n# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x4f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2:2 &=$|\n# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orr/2@2\n# AUNIT --inst x4f009400/mask=xfff8dc00 --status pass\n\n:orr Rd_VPR128.8H, Imm_neon_uimm8Shift\nis b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H | Imm_neon_uimm8Shift:2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] | Imm_neon_uimm8Shift:2;\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] | Imm_neon_uimm8Shift:2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00\n# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00\n# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$|@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1\n# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass\n\n:orr Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B | Rm_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | Rm_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | Rm_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | Rm_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | Rm_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | Rm_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | Rm_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | Rm_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | Rm_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | Rm_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | Rm_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | Rm_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | Rm_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | Rm_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | Rm_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | Rm_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | Rm_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00\n# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00\n# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$|@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1\n# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass\n\n:orr Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B | Rm_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | Rm_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | Rm_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | Rm_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | Rm_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | Rm_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | Rm_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | Rm_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | Rm_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.214 PMUL page C7-2511 line 146928 MATCH x2e209c00/mask=xbf20fc00\n# CONSTRUCT x6e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1\n# AUNIT --inst x6e209c00/mask=xffe0fc00 --status nopcodeop\n\n:pmul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_pmul(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.214 PMUL page C7-2511 line 146928 MATCH x2e209c00/mask=xbf20fc00\n# CONSTRUCT x2e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1\n# AUNIT --inst x2e209c00/mask=xffe0fc00 --status nopcodeop\n\n:pmul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_pmul(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00\n# CONSTRUCT x0ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@8\n# AUNIT --inst x0ee0e000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:pmull Rd_VPR128.1Q, Rn_VPR64.1D, Rm_VPR64.1D\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.1D & b_1215=0xe & b_1011=0 & Rn_VPR64.1D & Rd_VPR128.1Q & Zd\n{\n\tRd_VPR128.1Q = NEON_pmull(Rn_VPR64.1D, Rm_VPR64.1D, 8:1);\n}\n\n# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00\n# CONSTRUCT x0e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@1\n# AUNIT --inst x0e20e000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:pmull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xe & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_pmull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00\n# CONSTRUCT x4ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@8\n# AUNIT --inst x4ee0e000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:pmull2 Rd_VPR128.1Q, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1215=0xe & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.1Q & Zd\n{\n\tRd_VPR128.1Q = NEON_pmull2(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00\n# CONSTRUCT x4e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@1\n# AUNIT --inst x4e20e000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:pmull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xe & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_pmull2(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00\n# CONSTRUCT x6e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@2 0x80:2 &=$+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@2\n# AUNIT --inst x6e204000/mask=xffe0fc00 --status pass --comment \"intround\"\n\n:raddhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];\n\t# simd infix TMPQ1 = TMPQ1 + 0x80:2 on lane size 2\n\tTMPQ1[0,16] = TMPQ1[0,16] + 0x80:2;\n\tTMPQ1[16,16] = TMPQ1[16,16] + 0x80:2;\n\tTMPQ1[32,16] = TMPQ1[32,16] + 0x80:2;\n\tTMPQ1[48,16] = TMPQ1[48,16] + 0x80:2;\n\tTMPQ1[64,16] = TMPQ1[64,16] + 0x80:2;\n\tTMPQ1[80,16] = TMPQ1[80,16] + 0x80:2;\n\tTMPQ1[96,16] = TMPQ1[96,16] + 0x80:2;\n\tTMPQ1[112,16] = TMPQ1[112,16] + 0x80:2;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1\n\tRd_VPR128.16B[64,8] = TMPQ1[8,8];\n\tRd_VPR128.16B[72,8] = TMPQ1[24,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[40,8];\n\tRd_VPR128.16B[88,8] = TMPQ1[56,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[72,8];\n\tRd_VPR128.16B[104,8] = TMPQ1[88,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[104,8];\n\tRd_VPR128.16B[120,8] = TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00\n# CONSTRUCT x6ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@8 0x80000000:8 &=$+@8 &=$shuffle@1-2@3-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@8\n# AUNIT --inst x6ea04000/mask=xffe0fc00 --status pass --comment \"intround\"\n\n:raddhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];\n\t# simd infix TMPQ1 = TMPQ1 + 0x80000000:8 on lane size 8\n\tTMPQ1[0,64] = TMPQ1[0,64] + 0x80000000:8;\n\tTMPQ1[64,64] = TMPQ1[64,64] + 0x80000000:8;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4\n\tRd_VPR128.4S[64,32] = TMPQ1[32,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00\n# CONSTRUCT x6e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $+@4 0x8000:4 &=$+@4 &=$shuffle@1-4@3-5@5-6@7-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@4\n# AUNIT --inst x6e604000/mask=xffe0fc00 --status pass --comment \"intround\"\n\n:raddhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];\n\t# simd infix TMPQ1 = TMPQ1 + 0x8000:4 on lane size 4\n\tTMPQ1[0,32] = TMPQ1[0,32] + 0x8000:4;\n\tTMPQ1[32,32] = TMPQ1[32,32] + 0x8000:4;\n\tTMPQ1[64,32] = TMPQ1[64,32] + 0x8000:4;\n\tTMPQ1[96,32] = TMPQ1[96,32] + 0x8000:4;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2\n\tRd_VPR128.8H[64,16] = TMPQ1[16,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[48,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[80,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00\n# CONSTRUCT x2ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@8\n# AUNIT --inst x2ea04000/mask=xffe0fc00 --status nopcodeop\n\n:raddhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_raddhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00\n# CONSTRUCT x2e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@4\n# AUNIT --inst x2e604000/mask=xffe0fc00 --status nopcodeop\n\n:raddhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_raddhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00\n# CONSTRUCT x2e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@2\n# AUNIT --inst x2e204000/mask=xffe0fc00 --status nopcodeop\n\n:raddhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_raddhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.217 RAX1 page C7-2517 line 147279 MATCH xce608c00/mask=xffe0fc00\n# CONSTRUCT xce608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 1:8 $<<@8 =$|@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_rax1/2@8\n# AUNIT --inst xce608c00/mask=xffe0fc00 --status noqemu\n\n:rax1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_2131=0b11001110011 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\t# simd infix TMPQ1 = Rm_VPR128.2D << 1:8 on lane size 8\n\tTMPQ1[0,64] = Rm_VPR128.2D[0,64] << 1:8;\n\tTMPQ1[64,64] = Rm_VPR128.2D[64,64] << 1:8;\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D | TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] | TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] | TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.218 RBIT (vector) page C7-2518 line 147347 MATCH x2e605800/mask=xbffffc00\n# CONSTRUCT x2e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1\n# AUNIT --inst x2e605800/mask=xfffffc00 --status nopcodeop\n\n:rbit Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_1029=0b10111001100000010110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_rbit(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.218 RBIT (vector) page C7-2518 line 147347 MATCH x2e605800/mask=xbffffc00\n# CONSTRUCT x6e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1\n# AUNIT --inst x6e605800/mask=xfffffc00 --status nopcodeop\n\n:rbit Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_1029=0b10111001100000010110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_rbit(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.219 REV16 (vector) page C7-2520 line 147435 MATCH x0e201800/mask=xbf3ffc00\n# CONSTRUCT x4e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1\n# AUNIT --inst x4e201800/mask=xfffffc00 --status nopcodeop\n\n:rev16 Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_rev16(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.219 REV16 (vector) page C7-2520 line 147435 MATCH x0e201800/mask=xbf3ffc00\n# CONSTRUCT x0e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1\n# AUNIT --inst x0e201800/mask=xfffffc00 --status nopcodeop\n\n:rev16 Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_rev16(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00\n# CONSTRUCT x6e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1\n# AUNIT --inst x6e200800/mask=xfffffc00 --status nopcodeop\n\n:rev32 Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_rev32(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00\n# CONSTRUCT x2e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2\n# AUNIT --inst x2e600800/mask=xfffffc00 --status nopcodeop\n\n:rev32 Rd_VPR64.4H, Rn_VPR64.4H\nis b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_rev32(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00\n# CONSTRUCT x2e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1\n# AUNIT --inst x2e200800/mask=xfffffc00 --status nopcodeop\n\n:rev32 Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_rev32(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00\n# CONSTRUCT x6e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2\n# AUNIT --inst x6e600800/mask=xfffffc00 --status nopcodeop\n\n:rev32 Rd_VPR128.8H, Rn_VPR128.8H\nis b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_rev32(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00\n# CONSTRUCT x4e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1\n# AUNIT --inst x4e200800/mask=xfffffc00 --status nopcodeop\n\n:rev64 Rd_VPR128.16B, Rn_VPR128.16B\nis b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_rev64(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00\n# CONSTRUCT x0ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4\n# AUNIT --inst x0ea00800/mask=xfffffc00 --status nopcodeop\n\n:rev64 Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_rev64(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00\n# CONSTRUCT x0e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2\n# AUNIT --inst x0e600800/mask=xfffffc00 --status nopcodeop\n\n:rev64 Rd_VPR64.4H, Rn_VPR64.4H\nis b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_rev64(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00\n# CONSTRUCT x4ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4\n# AUNIT --inst x4ea00800/mask=xfffffc00 --status nopcodeop\n\n:rev64 Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_rev64(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00\n# CONSTRUCT x0e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1\n# AUNIT --inst x0e200800/mask=xfffffc00 --status nopcodeop\n\n:rev64 Rd_VPR64.8B, Rn_VPR64.8B\nis b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_rev64(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00\n# CONSTRUCT x4e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2\n# AUNIT --inst x4e600800/mask=xfffffc00 --status nopcodeop\n\n:rev64 Rd_VPR128.8H, Rn_VPR128.8H\nis b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_rev64(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00\n# CONSTRUCT x4f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@2\n# AUNIT --inst x4f088c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround\"\n\n:rshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_rshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00\n# CONSTRUCT x0f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@8\n# AUNIT --inst x0f208c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_rshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00\n# CONSTRUCT x0f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@4\n# AUNIT --inst x0f108c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround\"\n\n:rshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_rshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00\n# CONSTRUCT x4f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@8\n# AUNIT --inst x4f208c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_rshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00\n# CONSTRUCT x0f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@2\n# AUNIT --inst x0f088c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround\"\n\n:rshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_rshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00\n# CONSTRUCT x4f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@4\n# AUNIT --inst x4f108c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround\"\n\n:rshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_rshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00\n# CONSTRUCT x6e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@2\n# AUNIT --inst x6e206000/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rsubhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_rsubhn2(Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00\n# CONSTRUCT x6ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@8\n# AUNIT --inst x6ea06000/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rsubhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_rsubhn2(Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00\n# CONSTRUCT x6e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@4\n# AUNIT --inst x6e606000/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rsubhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_rsubhn2(Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00\n# CONSTRUCT x2ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@8\n# AUNIT --inst x2ea06000/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rsubhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_rsubhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00\n# CONSTRUCT x2e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@4\n# AUNIT --inst x2e606000/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rsubhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_rsubhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00\n# CONSTRUCT x2e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@2\n# AUNIT --inst x2e206000/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:rsubhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_rsubhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00\n# CONSTRUCT x4e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1\n# AUNIT --inst x4e207c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:saba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_saba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00\n# CONSTRUCT x0ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4\n# AUNIT --inst x0ea07c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:saba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_saba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00\n# CONSTRUCT x0e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2\n# AUNIT --inst x0e607c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:saba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_saba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00\n# CONSTRUCT x4ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4\n# AUNIT --inst x4ea07c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:saba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_saba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00\n# CONSTRUCT x0e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1\n# AUNIT --inst x0e207c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:saba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_saba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00\n# CONSTRUCT x4e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2\n# AUNIT --inst x4e607c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:saba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_saba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00\n# CONSTRUCT x0ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 $abs@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@4\n# AUNIT --inst x0ea05000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];\n\t# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8\n\tTMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]);\n\tTMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]);\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00\n# CONSTRUCT x0e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 $abs@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@2\n# AUNIT --inst x0e605000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];\n\t# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4\n\tTMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]);\n\tTMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]);\n\tTMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]);\n\tTMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00\n# CONSTRUCT x0e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 $abs@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@1\n# AUNIT --inst x0e205000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];\n\t# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2\n\tTMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]);\n\tTMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]);\n\tTMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]);\n\tTMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]);\n\tTMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]);\n\tTMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]);\n\tTMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]);\n\tTMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]);\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00\n# CONSTRUCT x4ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 $abs@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@4\n# AUNIT --inst x4ea05000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];\n\t# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8\n\tTMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]);\n\tTMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]);\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00\n# CONSTRUCT x4e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 $abs@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@2\n# AUNIT --inst x4e605000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];\n\t# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4\n\tTMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]);\n\tTMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]);\n\tTMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]);\n\tTMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00\n# CONSTRUCT x4e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 $abs@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@1\n# AUNIT --inst x4e205000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];\n\t# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2\n\tTMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]);\n\tTMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]);\n\tTMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]);\n\tTMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]);\n\tTMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]);\n\tTMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]);\n\tTMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]);\n\tTMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]);\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x4ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4\n# AUNIT --inst x4ea07400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x4e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1\n# AUNIT --inst x4e207400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:sabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B- Rm_VPR128.16B on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] - Rm_VPR128.16B[0,8];\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] - Rm_VPR128.16B[8,8];\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] - Rm_VPR128.16B[16,8];\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] - Rm_VPR128.16B[24,8];\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] - Rm_VPR128.16B[32,8];\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] - Rm_VPR128.16B[40,8];\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] - Rm_VPR128.16B[48,8];\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] - Rm_VPR128.16B[56,8];\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] - Rm_VPR128.16B[64,8];\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] - Rm_VPR128.16B[72,8];\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] - Rm_VPR128.16B[80,8];\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] - Rm_VPR128.16B[88,8];\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] - Rm_VPR128.16B[96,8];\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] - Rm_VPR128.16B[104,8];\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] - Rm_VPR128.16B[112,8];\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] - Rm_VPR128.16B[120,8];\n\n\n\t# simd infix TMPQ2 = Rm_VPR128.16B - Rn_VPR128.16B on lane size 1\n\tTMPQ2[0,8] = Rm_VPR128.16B[0,8] - Rn_VPR128.16B[0,8];\n\tTMPQ2[8,8] = Rm_VPR128.16B[8,8] - Rn_VPR128.16B[8,8];\n\tTMPQ2[16,8] = Rm_VPR128.16B[16,8] - Rn_VPR128.16B[16,8];\n\tTMPQ2[24,8] = Rm_VPR128.16B[24,8] - Rn_VPR128.16B[24,8];\n\tTMPQ2[32,8] = Rm_VPR128.16B[32,8] - Rn_VPR128.16B[32,8];\n\tTMPQ2[40,8] = Rm_VPR128.16B[40,8] - Rn_VPR128.16B[40,8];\n\tTMPQ2[48,8] = Rm_VPR128.16B[48,8] - Rn_VPR128.16B[48,8];\n\tTMPQ2[56,8] = Rm_VPR128.16B[56,8] - Rn_VPR128.16B[56,8];\n\tTMPQ2[64,8] = Rm_VPR128.16B[64,8] - Rn_VPR128.16B[64,8];\n\tTMPQ2[72,8] = Rm_VPR128.16B[72,8] - Rn_VPR128.16B[72,8];\n\tTMPQ2[80,8] = Rm_VPR128.16B[80,8] - Rn_VPR128.16B[80,8];\n\tTMPQ2[88,8] = Rm_VPR128.16B[88,8] - Rn_VPR128.16B[88,8];\n\tTMPQ2[96,8] = Rm_VPR128.16B[96,8] - Rn_VPR128.16B[96,8];\n\tTMPQ2[104,8] = Rm_VPR128.16B[104,8] - Rn_VPR128.16B[104,8];\n\tTMPQ2[112,8] = Rm_VPR128.16B[112,8] - Rn_VPR128.16B[112,8];\n\tTMPQ2[120,8] = Rm_VPR128.16B[120,8] - Rn_VPR128.16B[120,8];\n\n\n\t# simd infix TMPQ2 = TMPQ2 * 2:1 on lane size 1\n\tTMPQ2[0,8] = TMPQ2[0,8] * 2:1;\n\tTMPQ2[8,8] = TMPQ2[8,8] * 2:1;\n\tTMPQ2[16,8] = TMPQ2[16,8] * 2:1;\n\tTMPQ2[24,8] = TMPQ2[24,8] * 2:1;\n\tTMPQ2[32,8] = TMPQ2[32,8] * 2:1;\n\tTMPQ2[40,8] = TMPQ2[40,8] * 2:1;\n\tTMPQ2[48,8] = TMPQ2[48,8] * 2:1;\n\tTMPQ2[56,8] = TMPQ2[56,8] * 2:1;\n\tTMPQ2[64,8] = TMPQ2[64,8] * 2:1;\n\tTMPQ2[72,8] = TMPQ2[72,8] * 2:1;\n\tTMPQ2[80,8] = TMPQ2[80,8] * 2:1;\n\tTMPQ2[88,8] = TMPQ2[88,8] * 2:1;\n\tTMPQ2[96,8] = TMPQ2[96,8] * 2:1;\n\tTMPQ2[104,8] = TMPQ2[104,8] * 2:1;\n\tTMPQ2[112,8] = TMPQ2[112,8] * 2:1;\n\tTMPQ2[120,8] = TMPQ2[120,8] * 2:1;\n\n\n\t# simd infix TMPQ3 = Rn_VPR128.16B s< Rm_VPR128.16B on lane size 1\n\tTMPQ3[0,8] = zext(Rn_VPR128.16B[0,8] s< Rm_VPR128.16B[0,8]);\n\tTMPQ3[8,8] = zext(Rn_VPR128.16B[8,8] s< Rm_VPR128.16B[8,8]);\n\tTMPQ3[16,8] = zext(Rn_VPR128.16B[16,8] s< Rm_VPR128.16B[16,8]);\n\tTMPQ3[24,8] = zext(Rn_VPR128.16B[24,8] s< Rm_VPR128.16B[24,8]);\n\tTMPQ3[32,8] = zext(Rn_VPR128.16B[32,8] s< Rm_VPR128.16B[32,8]);\n\tTMPQ3[40,8] = zext(Rn_VPR128.16B[40,8] s< Rm_VPR128.16B[40,8]);\n\tTMPQ3[48,8] = zext(Rn_VPR128.16B[48,8] s< Rm_VPR128.16B[48,8]);\n\tTMPQ3[56,8] = zext(Rn_VPR128.16B[56,8] s< Rm_VPR128.16B[56,8]);\n\tTMPQ3[64,8] = zext(Rn_VPR128.16B[64,8] s< Rm_VPR128.16B[64,8]);\n\tTMPQ3[72,8] = zext(Rn_VPR128.16B[72,8] s< Rm_VPR128.16B[72,8]);\n\tTMPQ3[80,8] = zext(Rn_VPR128.16B[80,8] s< Rm_VPR128.16B[80,8]);\n\tTMPQ3[88,8] = zext(Rn_VPR128.16B[88,8] s< Rm_VPR128.16B[88,8]);\n\tTMPQ3[96,8] = zext(Rn_VPR128.16B[96,8] s< Rm_VPR128.16B[96,8]);\n\tTMPQ3[104,8] = zext(Rn_VPR128.16B[104,8] s< Rm_VPR128.16B[104,8]);\n\tTMPQ3[112,8] = zext(Rn_VPR128.16B[112,8] s< Rm_VPR128.16B[112,8]);\n\tTMPQ3[120,8] = zext(Rn_VPR128.16B[120,8] s< Rm_VPR128.16B[120,8]);\n\n\n\t# simd infix TMPQ2 = TMPQ2 * TMPQ3 on lane size 1\n\tTMPQ2[0,8] = TMPQ2[0,8] * TMPQ3[0,8];\n\tTMPQ2[8,8] = TMPQ2[8,8] * TMPQ3[8,8];\n\tTMPQ2[16,8] = TMPQ2[16,8] * TMPQ3[16,8];\n\tTMPQ2[24,8] = TMPQ2[24,8] * TMPQ3[24,8];\n\tTMPQ2[32,8] = TMPQ2[32,8] * TMPQ3[32,8];\n\tTMPQ2[40,8] = TMPQ2[40,8] * TMPQ3[40,8];\n\tTMPQ2[48,8] = TMPQ2[48,8] * TMPQ3[48,8];\n\tTMPQ2[56,8] = TMPQ2[56,8] * TMPQ3[56,8];\n\tTMPQ2[64,8] = TMPQ2[64,8] * TMPQ3[64,8];\n\tTMPQ2[72,8] = TMPQ2[72,8] * TMPQ3[72,8];\n\tTMPQ2[80,8] = TMPQ2[80,8] * TMPQ3[80,8];\n\tTMPQ2[88,8] = TMPQ2[88,8] * TMPQ3[88,8];\n\tTMPQ2[96,8] = TMPQ2[96,8] * TMPQ3[96,8];\n\tTMPQ2[104,8] = TMPQ2[104,8] * TMPQ3[104,8];\n\tTMPQ2[112,8] = TMPQ2[112,8] * TMPQ3[112,8];\n\tTMPQ2[120,8] = TMPQ2[120,8] * TMPQ3[120,8];\n\n\n\t# simd infix Rd_VPR128.16B = TMPQ1 + TMPQ2 on lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[0,8] + TMPQ2[0,8];\n\tRd_VPR128.16B[8,8] = TMPQ1[8,8] + TMPQ2[8,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[16,8] + TMPQ2[16,8];\n\tRd_VPR128.16B[24,8] = TMPQ1[24,8] + TMPQ2[24,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[32,8] + TMPQ2[32,8];\n\tRd_VPR128.16B[40,8] = TMPQ1[40,8] + TMPQ2[40,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[48,8] + TMPQ2[48,8];\n\tRd_VPR128.16B[56,8] = TMPQ1[56,8] + TMPQ2[56,8];\n\tRd_VPR128.16B[64,8] = TMPQ1[64,8] + TMPQ2[64,8];\n\tRd_VPR128.16B[72,8] = TMPQ1[72,8] + TMPQ2[72,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[80,8] + TMPQ2[80,8];\n\tRd_VPR128.16B[88,8] = TMPQ1[88,8] + TMPQ2[88,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[96,8] + TMPQ2[96,8];\n\tRd_VPR128.16B[104,8] = TMPQ1[104,8] + TMPQ2[104,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[112,8] + TMPQ2[112,8];\n\tRd_VPR128.16B[120,8] = TMPQ1[120,8] + TMPQ2[120,8];\n\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x0ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $sless@4 &=$*@4 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4\n# AUNIT --inst x0ea07400/mask=xffe0fc00 --status pass --comment \"abd\"\n# This abd instruction is implemented correctly to document a correct\n# way to implement the signed absolute difference semantic.\n\n:sabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];\n\n\t# simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4\n\tTMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32];\n\tTMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32];\n\n\t# simd infix TMPD2 = TMPD2 * 2:4 on lane size 4\n\tTMPD2[0,32] = TMPD2[0,32] * 2:4;\n\tTMPD2[32,32] = TMPD2[32,32] * 2:4;\n\n\t# simd infix TMPD3 = Rn_VPR64.2S s< Rm_VPR64.2S on lane size 4\n\tTMPD3[0,32] = zext(Rn_VPR64.2S[0,32] s< Rm_VPR64.2S[0,32]);\n\tTMPD3[32,32] = zext(Rn_VPR64.2S[32,32] s< Rm_VPR64.2S[32,32]);\n\n\t# simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4\n\tTMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32];\n\tTMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32];\n\n\t# simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32];\n\tRd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32];\n\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x0e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2\n# AUNIT --inst x0e607400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:sabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H - Rm_VPR64.4H on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] - Rm_VPR64.4H[0,16];\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] - Rm_VPR64.4H[16,16];\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] - Rm_VPR64.4H[32,16];\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] - Rm_VPR64.4H[48,16];\n\n\t# simd infix TMPD2 = Rm_VPR64.4H - Rn_VPR64.4H on lane size 2\n\tTMPD2[0,16] = Rm_VPR64.4H[0,16] - Rn_VPR64.4H[0,16];\n\tTMPD2[16,16] = Rm_VPR64.4H[16,16] - Rn_VPR64.4H[16,16];\n\tTMPD2[32,16] = Rm_VPR64.4H[32,16] - Rn_VPR64.4H[32,16];\n\tTMPD2[48,16] = Rm_VPR64.4H[48,16] - Rn_VPR64.4H[48,16];\n\n\t# simd infix TMPD2 = TMPD2 * 2:2 on lane size 2\n\tTMPD2[0,16] = TMPD2[0,16] * 2:2;\n\tTMPD2[16,16] = TMPD2[16,16] * 2:2;\n\tTMPD2[32,16] = TMPD2[32,16] * 2:2;\n\tTMPD2[48,16] = TMPD2[48,16] * 2:2;\n\n\t# simd infix TMPD3 = Rn_VPR64.4H s< Rm_VPR64.4H on lane size 2\n\tTMPD3[0,16] = zext(Rn_VPR64.4H[0,16] s< Rm_VPR64.4H[0,16]);\n\tTMPD3[16,16] = zext(Rn_VPR64.4H[16,16] s< Rm_VPR64.4H[16,16]);\n\tTMPD3[32,16] = zext(Rn_VPR64.4H[32,16] s< Rm_VPR64.4H[32,16]);\n\tTMPD3[48,16] = zext(Rn_VPR64.4H[48,16] s< Rm_VPR64.4H[48,16]);\n\n\t# simd infix TMPD2 = TMPD2 * TMPD3 on lane size 2\n\tTMPD2[0,16] = TMPD2[0,16] * TMPD3[0,16];\n\tTMPD2[16,16] = TMPD2[16,16] * TMPD3[16,16];\n\tTMPD2[32,16] = TMPD2[32,16] * TMPD3[32,16];\n\tTMPD2[48,16] = TMPD2[48,16] * TMPD3[48,16];\n\n\t# simd infix Rd_VPR64.4H = TMPD1 + TMPD2 on lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[0,16] + TMPD2[0,16];\n\tRd_VPR64.4H[16,16] = TMPD1[16,16] + TMPD2[16,16];\n\tRd_VPR64.4H[32,16] = TMPD1[32,16] + TMPD2[32,16];\n\tRd_VPR64.4H[48,16] = TMPD1[48,16] + TMPD2[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x4ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4\n# AUNIT --inst x4ea07400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:sabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];\n\n\t# simd infix TMPQ2 = Rm_VPR128.4S - Rn_VPR128.4S on lane size 4\n\tTMPQ2[0,32] = Rm_VPR128.4S[0,32] - Rn_VPR128.4S[0,32];\n\tTMPQ2[32,32] = Rm_VPR128.4S[32,32] - Rn_VPR128.4S[32,32];\n\tTMPQ2[64,32] = Rm_VPR128.4S[64,32] - Rn_VPR128.4S[64,32];\n\tTMPQ2[96,32] = Rm_VPR128.4S[96,32] - Rn_VPR128.4S[96,32];\n\n\t# simd infix TMPQ2 = TMPQ2 * 2:4 on lane size 4\n\tTMPQ2[0,32] = TMPQ2[0,32] * 2:4;\n\tTMPQ2[32,32] = TMPQ2[32,32] * 2:4;\n\tTMPQ2[64,32] = TMPQ2[94,32] * 2:4;\n\tTMPQ2[96,32] = TMPQ2[96,32] * 2:4;\n\n\t# simd infix TMPQ3 = Rn_VPR128.4S s< Rm_VPR128.4S on lane size 4\n\tTMPQ3[0,32] = zext(Rn_VPR128.4S[0,32] s< Rm_VPR128.4S[0,32]);\n\tTMPQ3[32,32] = zext(Rn_VPR128.4S[32,32] s< Rm_VPR128.4S[32,32]);\n\tTMPQ3[64,32] = zext(Rn_VPR128.4S[64,32] s< Rm_VPR128.4S[64,32]);\n\tTMPQ3[96,32] = zext(Rn_VPR128.4S[96,32] s< Rm_VPR128.4S[96,32]);\n\n\t# simd infix TMPQ2 = TMPQ2 * TMPQ3 on lane size 4\n\tTMPQ2[0,32] = TMPQ2[0,32] * TMPQ3[0,32];\n\tTMPQ2[32,32] = TMPQ2[32,32] * TMPQ3[32,32];\n\tTMPQ2[64,32] = TMPQ2[64,32] * TMPQ3[64,32];\n\tTMPQ2[96,32] = TMPQ2[96,32] * TMPQ3[96,32];\n\n\t# simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];\n\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x0e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1\n# AUNIT --inst x0e207400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:sabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B - Rm_VPR64.8B on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] - Rm_VPR64.8B[0,8];\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] - Rm_VPR64.8B[8,8];\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] - Rm_VPR64.8B[16,8];\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] - Rm_VPR64.8B[24,8];\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] - Rm_VPR64.8B[32,8];\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] - Rm_VPR64.8B[40,8];\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] - Rm_VPR64.8B[48,8];\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] - Rm_VPR64.8B[56,8];\n\n\t# simd infix TMPD2 = Rm_VPR64.8B - Rn_VPR64.8B on lane size 1\n\tTMPD2[0,8] = Rm_VPR64.8B[0,8] - Rn_VPR64.8B[0,8];\n\tTMPD2[8,8] = Rm_VPR64.8B[8,8] - Rn_VPR64.8B[8,8];\n\tTMPD2[16,8] = Rm_VPR64.8B[16,8] - Rn_VPR64.8B[16,8];\n\tTMPD2[24,8] = Rm_VPR64.8B[24,8] - Rn_VPR64.8B[24,8];\n\tTMPD2[32,8] = Rm_VPR64.8B[32,8] - Rn_VPR64.8B[32,8];\n\tTMPD2[40,8] = Rm_VPR64.8B[40,8] - Rn_VPR64.8B[40,8];\n\tTMPD2[48,8] = Rm_VPR64.8B[48,8] - Rn_VPR64.8B[48,8];\n\tTMPD2[56,8] = Rm_VPR64.8B[56,8] - Rn_VPR64.8B[56,8];\n\n\t# simd infix TMPD2 = TMPD2 * 2:1 on lane size 1\n\tTMPD2[0,8] = TMPD2[0,8] * 2:1;\n\tTMPD2[8,8] = TMPD2[8,8] * 2:1;\n\tTMPD2[16,8] = TMPD2[16,8] * 2:1;\n\tTMPD2[24,8] = TMPD2[24,8] * 2:1;\n\tTMPD2[32,8] = TMPD2[32,8] * 2:1;\n\tTMPD2[40,8] = TMPD2[40,8] * 2:1;\n\tTMPD2[48,8] = TMPD2[48,8] * 2:1;\n\tTMPD2[56,8] = TMPD2[56,8] * 2:1;\n\n\t# simd infix TMPD3 = Rn_VPR64.8B s< Rm_VPR64.8B on lane size 1\n\tTMPD3[0,8] = zext(Rn_VPR64.8B[0,8] s< Rm_VPR64.8B[0,8]);\n\tTMPD3[8,8] = zext(Rn_VPR64.8B[8,8] s< Rm_VPR64.8B[8,8]);\n\tTMPD3[16,8] = zext(Rn_VPR64.8B[16,8] s< Rm_VPR64.8B[16,8]);\n\tTMPD3[24,8] = zext(Rn_VPR64.8B[24,8] s< Rm_VPR64.8B[24,8]);\n\tTMPD3[32,8] = zext(Rn_VPR64.8B[32,8] s< Rm_VPR64.8B[32,8]);\n\tTMPD3[40,8] = zext(Rn_VPR64.8B[40,8] s< Rm_VPR64.8B[40,8]);\n\tTMPD3[48,8] = zext(Rn_VPR64.8B[48,8] s< Rm_VPR64.8B[48,8]);\n\tTMPD3[56,8] = zext(Rn_VPR64.8B[56,8] s< Rm_VPR64.8B[56,8]);\n\n\t# simd infix TMPD2 = TMPD2 * TMPD3 on lane size 1\n\tTMPD2[0,8] = TMPD2[0,8] * TMPD3[0,8];\n\tTMPD2[8,8] = TMPD2[8,8] * TMPD3[8,8];\n\tTMPD2[16,8] = TMPD2[16,8] * TMPD3[16,8];\n\tTMPD2[24,8] = TMPD2[24,8] * TMPD3[24,8];\n\tTMPD2[32,8] = TMPD2[32,8] * TMPD3[32,8];\n\tTMPD2[40,8] = TMPD2[40,8] * TMPD3[40,8];\n\tTMPD2[48,8] = TMPD2[48,8] * TMPD3[48,8];\n\tTMPD2[56,8] = TMPD2[56,8] * TMPD3[56,8];\n\n\t# simd infix Rd_VPR64.8B = TMPD1 + TMPD2 on lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[0,8] + TMPD2[0,8];\n\tRd_VPR64.8B[8,8] = TMPD1[8,8] + TMPD2[8,8];\n\tRd_VPR64.8B[16,8] = TMPD1[16,8] + TMPD2[16,8];\n\tRd_VPR64.8B[24,8] = TMPD1[24,8] + TMPD2[24,8];\n\tRd_VPR64.8B[32,8] = TMPD1[32,8] + TMPD2[32,8];\n\tRd_VPR64.8B[40,8] = TMPD1[40,8] + TMPD2[40,8];\n\tRd_VPR64.8B[48,8] = TMPD1[48,8] + TMPD2[48,8];\n\tRd_VPR64.8B[56,8] = TMPD1[56,8] + TMPD2[56,8];\n\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00\n# CONSTRUCT x4e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2\n# AUNIT --inst x4e607400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:sabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];\n\n\t# simd infix TMPQ2 = Rm_VPR128.8H - Rn_VPR128.8H on lane size 2\n\tTMPQ2[0,16] = Rm_VPR128.8H[0,16] - Rn_VPR128.8H[0,16];\n\tTMPQ2[16,16] = Rm_VPR128.8H[16,16] - Rn_VPR128.8H[16,16];\n\tTMPQ2[32,16] = Rm_VPR128.8H[32,16] - Rn_VPR128.8H[32,16];\n\tTMPQ2[48,16] = Rm_VPR128.8H[48,16] - Rn_VPR128.8H[48,16];\n\tTMPQ2[64,16] = Rm_VPR128.8H[64,16] - Rn_VPR128.8H[64,16];\n\tTMPQ2[80,16] = Rm_VPR128.8H[80,16] - Rn_VPR128.8H[80,16];\n\tTMPQ2[96,16] = Rm_VPR128.8H[96,16] - Rn_VPR128.8H[96,16];\n\tTMPQ2[112,16] = Rm_VPR128.8H[112,16] - Rn_VPR128.8H[112,16];\n\n\t# simd infix TMPQ2 = TMPQ2 * 2:2 on lane size 2\n\tTMPQ2[0,16] = TMPQ2[0,16] * 2:2;\n\tTMPQ2[16,16] = TMPQ2[16,16] * 2:2;\n\tTMPQ2[32,16] = TMPQ2[32,16] * 2:2;\n\tTMPQ2[48,16] = TMPQ2[48,16] * 2:2;\n\tTMPQ2[64,16] = TMPQ2[64,16] * 2:2;\n\tTMPQ2[80,16] = TMPQ2[80,16] * 2:2;\n\tTMPQ2[96,16] = TMPQ2[96,16] * 2:2;\n\tTMPQ2[112,16] = TMPQ2[112,16] * 2:2;\n\n\t# simd infix TMPQ3 = Rn_VPR128.8H s< Rm_VPR128.8H on lane size 2\n\tTMPQ3[0,16] = zext(Rn_VPR128.8H[0,16] s< Rm_VPR128.8H[0,16]);\n\tTMPQ3[16,16] = zext(Rn_VPR128.8H[16,16] s< Rm_VPR128.8H[16,16]);\n\tTMPQ3[32,16] = zext(Rn_VPR128.8H[32,16] s< Rm_VPR128.8H[32,16]);\n\tTMPQ3[48,16] = zext(Rn_VPR128.8H[48,16] s< Rm_VPR128.8H[48,16]);\n\tTMPQ3[64,16] = zext(Rn_VPR128.8H[64,16] s< Rm_VPR128.8H[64,16]);\n\tTMPQ3[80,16] = zext(Rn_VPR128.8H[80,16] s< Rm_VPR128.8H[80,16]);\n\tTMPQ3[96,16] = zext(Rn_VPR128.8H[96,16] s< Rm_VPR128.8H[96,16]);\n\tTMPQ3[112,16] = zext(Rn_VPR128.8H[112,16] s< Rm_VPR128.8H[112,16]);\n\n\t# simd infix TMPQ2 = TMPQ2 * TMPQ3 on lane size 2\n\tTMPQ2[0,16] = TMPQ2[0,16] * TMPQ3[0,16];\n\tTMPQ2[16,16] = TMPQ2[16,16] * TMPQ3[16,16];\n\tTMPQ2[32,16] = TMPQ2[32,16] * TMPQ3[32,16];\n\tTMPQ2[48,16] = TMPQ2[48,16] * TMPQ3[48,16];\n\tTMPQ2[64,16] = TMPQ2[64,16] * TMPQ3[64,16];\n\tTMPQ2[80,16] = TMPQ2[80,16] * TMPQ3[80,16];\n\tTMPQ2[96,16] = TMPQ2[96,16] * TMPQ3[96,16];\n\tTMPQ2[112,16] = TMPQ2[112,16] * TMPQ3[112,16];\n\n\t# simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];\n\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00\n# CONSTRUCT x0ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 =$abs@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@4\n# AUNIT --inst x0ea07000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];\n\t# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8\n\tRd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]);\n\tRd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00\n# CONSTRUCT x0e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@2\n# AUNIT --inst x0e607000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];\n\t# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4\n\tRd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]);\n\tRd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]);\n\tRd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]);\n\tRd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00\n# CONSTRUCT x0e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@1\n# AUNIT --inst x0e207000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];\n\t# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2\n\tRd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]);\n\tRd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]);\n\tRd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]);\n\tRd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]);\n\tRd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]);\n\tRd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]);\n\tRd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]);\n\tRd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00\n# CONSTRUCT x4ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 =$abs@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@4\n# AUNIT --inst x4ea07000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];\n\t# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8\n\tRd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]);\n\tRd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00\n# CONSTRUCT x4e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@2\n# AUNIT --inst x4e607000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];\n\t# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4\n\tRd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]);\n\tRd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]);\n\tRd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]);\n\tRd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00\n# CONSTRUCT x4e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@1\n# AUNIT --inst x4e207000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:sabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];\n\t# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2\n\tRd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]);\n\tRd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]);\n\tRd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]);\n\tRd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]);\n\tRd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]);\n\tRd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]);\n\tRd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]);\n\tRd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00\n# CONSTRUCT x0e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 =#+ &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1\n# AUNIT --inst x0e206800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when 4H when size = 00 , Q = 0 Ta=VPR64.4H Tb=VPR64.8B e1=1 e2=2 s2=16\n\n:sadalp Rd_VPR64.4H, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2)\n\tlocal tmp2 = Rn_VPR64.8B[0,8];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = Rn_VPR64.8B[8,8];\n\tlocal tmp5 = sext(tmp3);\n\tTMPD1[0,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.8B[16,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR64.8B[24,8];\n\ttmp5 = sext(tmp3);\n\tTMPD1[16,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.8B[32,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR64.8B[40,8];\n\ttmp5 = sext(tmp3);\n\tTMPD1[32,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.8B[48,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR64.8B[56,8];\n\ttmp5 = sext(tmp3);\n\tTMPD1[48,16] = tmp4 + tmp5;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00\n# CONSTRUCT x4e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 =#+ &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1\n# AUNIT --inst x4e206800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when 8H when size = 00 , Q = 1 Ta=VPR128.8H Tb=VPR128.16B e1=1 e2=2 s2=32\n\n:sadalp Rd_VPR128.8H, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2)\n\tlocal tmp2 = Rn_VPR128.16B[0,8];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = Rn_VPR128.16B[8,8];\n\tlocal tmp5 = sext(tmp3);\n\tTMPQ1[0,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[16,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[24,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[16,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[32,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[40,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[32,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[48,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[56,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[48,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[64,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[72,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[64,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[80,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[88,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[80,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[96,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[104,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[96,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[112,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.16B[120,8];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[112,16] = tmp4 + tmp5;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00\n# CONSTRUCT x0e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 =#+ &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2\n# AUNIT --inst x0e606800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when 2S when size = 01 , Q = 0 Ta=VPR64.2S Tb=VPR64.4H e1=2 e2=4 s2=16\n\n:sadalp Rd_VPR64.2S, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4)\n\tlocal tmp2 = Rn_VPR64.4H[0,16];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = Rn_VPR64.4H[16,16];\n\tlocal tmp5 = sext(tmp3);\n\tTMPD1[0,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.4H[32,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR64.4H[48,16];\n\ttmp5 = sext(tmp3);\n\tTMPD1[32,32] = tmp4 + tmp5;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00\n# CONSTRUCT x4e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 =#+ &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2\n# AUNIT --inst x4e606800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when 4S when size = 01 , Q = 1 Ta=VPR128.4S Tb=VPR128.8H e1=2 e2=4 s2=32\n\n:sadalp Rd_VPR128.4S, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4)\n\tlocal tmp2 = Rn_VPR128.8H[0,16];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = Rn_VPR128.8H[16,16];\n\tlocal tmp5 = sext(tmp3);\n\tTMPQ1[0,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.8H[32,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.8H[48,16];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[32,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.8H[64,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.8H[80,16];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[64,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.8H[96,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.8H[112,16];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[96,32] = tmp4 + tmp5;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00\n# CONSTRUCT x0ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 =#+ &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4\n# AUNIT --inst x0ea06800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when 1D when size = 10 , Q = 0 Ta=VPR64.1D Tb=VPR64.2S e1=4 e2=8 s2=16\n\n:sadalp Rd_VPR64.1D, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8)\n\tlocal tmp2 = Rn_VPR64.2S[0,32];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = Rn_VPR64.2S[32,32];\n\tlocal tmp5 = sext(tmp3);\n\tTMPD1 = tmp4 + tmp5;\n\t# simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8\n\tRd_VPR64.1D = Rd_VPR64.1D + TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00\n# CONSTRUCT x4ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 =#+ &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4\n# AUNIT --inst x4ea06800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when 2D when size = 10 , Q = 1 Ta=VPR128.2D Tb=VPR128.4S e1=4 e2=8 s2=32\n\n:sadalp Rd_VPR128.2D, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8)\n\tlocal tmp2 = Rn_VPR128.4S[0,32];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = Rn_VPR128.4S[32,32];\n\tlocal tmp5 = sext(tmp3);\n\tTMPQ1[0,64] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.4S[64,32];\n\ttmp4 = sext(tmp2);\n\ttmp3 = Rn_VPR128.4S[96,32];\n\ttmp5 = sext(tmp3);\n\tTMPQ1[64,64] = tmp4 + tmp5;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00\n# CONSTRUCT x0ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saddl/2@4\n# AUNIT --inst x0ea00000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00\n# CONSTRUCT x0e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@2\n# AUNIT --inst x0e600000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00\n# CONSTRUCT x0e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@1\n# AUNIT --inst x0e200000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00\n# CONSTRUCT x4ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@4\n# AUNIT --inst x4ea00000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00\n# CONSTRUCT x4e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@2\n# AUNIT --inst x4e600000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00\n# CONSTRUCT x4e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@1\n# AUNIT --inst x4e200000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00\n# CONSTRUCT x0ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#+@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4\n# AUNIT --inst x0ea02800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:saddlp Rd_VPR64.1D, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd\n{\n\tTMPD1 = Rn_VPR64.2S;\n\t# sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8)\n\tlocal tmp2 = TMPD1[0,32];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = TMPD1[32,32];\n\tlocal tmp5 = sext(tmp3);\n\tRd_VPR64.1D = tmp4 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00\n# CONSTRUCT x0e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#+@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2\n# AUNIT --inst x0e602800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:saddlp Rd_VPR64.2S, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd\n{\n\tTMPD1 = Rn_VPR64.4H;\n\t# sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4)\n\tlocal tmp2 = TMPD1[0,16];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = TMPD1[16,16];\n\tlocal tmp5 = sext(tmp3);\n\tRd_VPR64.2S[0,32] = tmp4 + tmp5;\n\ttmp2 = TMPD1[32,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPD1[48,16];\n\ttmp5 = sext(tmp3);\n\tRd_VPR64.2S[32,32] = tmp4 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00\n# CONSTRUCT x0e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#+@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1\n# AUNIT --inst x0e202800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:saddlp Rd_VPR64.4H, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd\n{\n\tTMPD1 = Rn_VPR64.8B;\n\t# sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2)\n\tlocal tmp2 = TMPD1[0,8];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = TMPD1[8,8];\n\tlocal tmp5 = sext(tmp3);\n\tRd_VPR64.4H[0,16] = tmp4 + tmp5;\n\ttmp2 = TMPD1[16,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPD1[24,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR64.4H[16,16] = tmp4 + tmp5;\n\ttmp2 = TMPD1[32,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPD1[40,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR64.4H[32,16] = tmp4 + tmp5;\n\ttmp2 = TMPD1[48,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPD1[56,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR64.4H[48,16] = tmp4 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00\n# CONSTRUCT x4ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#+@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4\n# AUNIT --inst x4ea02800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:saddlp Rd_VPR128.2D, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPQ1 = Rn_VPR128.4S;\n\t# sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8)\n\tlocal tmp2 = TMPQ1[0,32];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = TMPQ1[32,32];\n\tlocal tmp5 = sext(tmp3);\n\tRd_VPR128.2D[0,64] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[64,32];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[96,32];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.2D[64,64] = tmp4 + tmp5;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00\n# CONSTRUCT x4e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#+@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2\n# AUNIT --inst x4e602800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:saddlp Rd_VPR128.4S, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPQ1 = Rn_VPR128.8H;\n\t# sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4)\n\tlocal tmp2 = TMPQ1[0,16];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = TMPQ1[16,16];\n\tlocal tmp5 = sext(tmp3);\n\tRd_VPR128.4S[0,32] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[32,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[48,16];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.4S[32,32] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[64,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[80,16];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.4S[64,32] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[96,16];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[112,16];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.4S[96,32] = tmp4 + tmp5;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00\n# CONSTRUCT x4e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#+@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1\n# AUNIT --inst x4e202800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:saddlp Rd_VPR128.8H, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPQ1 = Rn_VPR128.16B;\n\t# sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2)\n\tlocal tmp2 = TMPQ1[0,8];\n\tlocal tmp4 = sext(tmp2);\n\tlocal tmp3 = TMPQ1[8,8];\n\tlocal tmp5 = sext(tmp3);\n\tRd_VPR128.8H[0,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[16,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[24,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[16,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[32,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[40,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[32,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[48,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[56,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[48,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[64,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[72,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[64,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[80,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[88,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[80,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[96,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[104,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[96,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[112,8];\n\ttmp4 = sext(tmp2);\n\ttmp3 = TMPQ1[120,8];\n\ttmp5 = sext(tmp3);\n\tRd_VPR128.8H[112,16] = tmp4 + tmp5;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00\n# CONSTRUCT x4eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@4\n# AUNIT --inst x4eb03800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:saddlv Rd_FPR64, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_saddlv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00\n# CONSTRUCT x4e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1\n# AUNIT --inst x4e303800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:saddlv Rd_FPR16, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_saddlv(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00\n# CONSTRUCT x0e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1\n# AUNIT --inst x0e303800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:saddlv Rd_FPR16, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_saddlv(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00\n# CONSTRUCT x0e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2\n# AUNIT --inst x0e703800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:saddlv Rd_FPR32, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_saddlv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00\n# CONSTRUCT x4e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2\n# AUNIT --inst x4e703800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:saddlv Rd_FPR32, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_saddlv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00\n# CONSTRUCT x0ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@4\n# AUNIT --inst x0ea01000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00\n# CONSTRUCT x0e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@2\n# AUNIT --inst x0e601000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00\n# CONSTRUCT x0e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@1\n# AUNIT --inst x0e201000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00\n# CONSTRUCT x4ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@4\n# AUNIT --inst x4ea01000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00\n# CONSTRUCT x4e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@2\n# AUNIT --inst x4e601000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00\n# CONSTRUCT x4e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@1\n# AUNIT --inst x4e201000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:saddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00\n# CONSTRUCT x5f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2\n# AUNIT --inst x5f40e400/mask=xffc0fc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_scvtf(Rn_FPR64, Imm_shr_imm64:4);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00\n# CONSTRUCT x5f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2\n# AUNIT --inst x5f20e400/mask=xffe0fc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_3031=1 & u=0 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_scvtf(Rn_FPR32, Imm_shr_imm32:4);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00\n# CONSTRUCT x5f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2\n# AUNIT --inst x5f10e400/mask=xfff0fc00 --status noqemu --comment \"nofpround\"\n\n:scvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16\nis b_3031=1 & u=0 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_scvtf(Rn_FPR16, Imm_shr_imm16:4);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x4f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@8\n# AUNIT --inst x4f40e400/mask=xffc0fc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, Imm_shr_imm64:4, 8:1);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x0f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4\n# AUNIT --inst x0f20e400/mask=xffe0fc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x4f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4\n# AUNIT --inst x4f20e400/mask=xffe0fc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x0f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2\n# AUNIT --inst x0f10e400/mask=xfff0fc00 --status noqemu --comment \"nofpround\"\n\n:scvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, Imm_shr_imm32:4, 2:1);\n}\n\n# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00\n# CONSTRUCT x4f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2\n# AUNIT --inst x4f10e400/mask=xfff0fc00 --status noqemu --comment \"nofpround\"\n\n:scvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, Imm_shr_imm32:4, 2:1);\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e21d800/mask=xffbffc00\n# CONSTRUCT x5e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x5e21d800/mask=xfffffc00 --status fail --comment \"nofpround\"\n\n:scvtf Rd_FPR32, Rn_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = int2float(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e21d800/mask=xffbffc00\n# CONSTRUCT x5e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x5e61d800/mask=xfffffc00 --status pass --comment \"nofpround\"\n\n:scvtf Rd_FPR64, Rn_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = int2float(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00\n# CONSTRUCT x4e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@8\n# AUNIT --inst x4e61d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00\n# CONSTRUCT x0e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4\n# AUNIT --inst x0e21d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00\n# CONSTRUCT x4e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4\n# AUNIT --inst x4e21d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:scvtf Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e79d800/mask=xfffffc00\n# CONSTRUCT x5e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x5e79d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Scalar half precision variant\n\n:scvtf Rd_FPR16, Rn_FPR16\nis b_1031=0b0101111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = int2float(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e79d800/mask=xbffffc00\n# CONSTRUCT x0e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2\n# AUNIT --inst x0e79d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 suf=VPR64.4H\n\n:scvtf Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b00111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e79d800/mask=xbffffc00\n# CONSTRUCT x4e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2\n# AUNIT --inst x4e79d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 suf=VPR128.8H\n\n:scvtf Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b00111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000\n# CONSTRUCT x1ec28000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2\n# AUNIT --inst x1ec28000/mask=xffff8000 --status noqemu --comment \"nofpround\"\n# 32-bit to half-precision variant when sf == 0 && type == 11\n\n:scvtf Rd_FPR16, Rn_GPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:2 = int2float(Rn_GPR32);\n\tRd_FPR16 = tmp1 f/ FBits16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000\n# CONSTRUCT x9ec20000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2\n# AUNIT --inst x9ec20000/mask=xffff0000 --status noqemu --comment \"nofpround\"\n# 64-bit to half-precision variant when sf == 1 && type == 11\n\n:scvtf Rd_FPR16, Rn_GPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:2 = int2float(Rn_GPR64);\n\tRd_FPR16 = tmp1 f/ FBits16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000\n# CONSTRUCT x1e428000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float:8 FBits64 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2\n# AUNIT --inst x1e428000/mask=xffff8000 --status pass --comment \"nofpround\"\n\n:scvtf Rd_FPR64, Rn_GPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = int2float(Rn_GPR32);\n\tRd_FPR64 = tmp1 f/ FBits64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000\n# CONSTRUCT x1e028000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float FBits32 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2\n# AUNIT --inst x1e028000/mask=xffff8000 --status fail --comment \"nofpround\"\n\n:scvtf Rd_FPR32, Rn_GPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:4 = int2float(Rn_GPR32);\n\tRd_FPR32 = tmp1 f/ FBits32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000\n# CONSTRUCT x9e420000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float FBits64 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2\n# AUNIT --inst x9e420000/mask=xffff0000 --status fail --comment \"nofpround\"\n\n:scvtf Rd_FPR64, Rn_GPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = int2float(Rn_GPR64);\n\tRd_FPR64 = tmp1 f/ FBits64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000\n# CONSTRUCT x9e020000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 int2float:4 FBits32 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2\n# AUNIT --inst x9e020000/mask=xffff0000 --status fail --comment \"nofpround\"\n\n:scvtf Rd_FPR32, Rn_GPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:4 = int2float(Rn_GPR64);\n\tRd_FPR32 = tmp1 f/ FBits32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00\n# CONSTRUCT x1ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x1ee20000/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n\n:scvtf Rd_FPR16, Rn_GPR32\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = int2float(Rn_GPR32);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00\n# CONSTRUCT x9ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x9ee20000/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n\n:scvtf Rd_FPR16, Rn_GPR64\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = int2float(Rn_GPR64);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00\n# CONSTRUCT x1e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x1e620000/mask=xfffffc00 --status pass --comment \"nofpround\"\n\n:scvtf Rd_FPR64, Rn_GPR32\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = int2float(Rn_GPR32);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00\n# CONSTRUCT x9e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x9e620000/mask=xfffffc00 --status pass --comment \"nofpround\"\n\n:scvtf Rd_FPR64, Rn_GPR64\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = int2float(Rn_GPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00\n# CONSTRUCT x1e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x1e220000/mask=xfffffc00 --status fail --comment \"nofpround\"\n\n:scvtf Rd_FPR32, Rn_GPR32\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = int2float(Rn_GPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00\n# CONSTRUCT x9e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =int2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1\n# AUNIT --inst x9e220000/mask=xfffffc00 --status fail --comment \"nofpround\"\n\n:scvtf Rd_FPR32, Rn_GPR64\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = int2float(Rn_GPR64);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.237 SDOT (by element) page C7-2558 line 149653 MATCH x0f00e000/mask=xbf00f400\n# CONSTRUCT x0f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1\n# AUNIT --inst x0f80e000/mask=xffc0f400 --status noqemu\n# Vector variant when Q=0 Ta=64.2S Tb=64.8B\n\n:sdot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex\nis b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);\n\tRd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, tmp1, 1:1);\n}\n\n# C7.2.237 SDOT (by element) page C7-2558 line 149653 MATCH x0f00e000/mask=xbf00f400\n# CONSTRUCT x4f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1\n# AUNIT --inst x4f80e000/mask=xffc0f400 --status noqemu\n# Vector variant when Q=1 Ta=128.4S Tb=128.16B\n\n:sdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex\nis b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);\n\tRd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, tmp1, 1:1);\n}\n\n# C7.2.238 SDOT (vector) page C7-2560 line 149755 MATCH x0e009400/mask=xbf20fc00\n# CONSTRUCT x0e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1\n# AUNIT --inst x0e809400/mask=xffe0fc00 --status noqemu\n# Three registers of the same type variant when Q=0 Ta=64.2S Tb=64.8B\n\n:sdot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd\n{\n\tRd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.238 SDOT (vector) page C7-2560 line 149755 MATCH x0e009400/mask=xbf20fc00\n# CONSTRUCT x4e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1\n# AUNIT --inst x4e809400/mask=xffe0fc00 --status noqemu\n# Three registers of the same type variant when Q=1 Ta=128.4S Tb=128.16B\n\n:sdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd\n{\n\tRd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.239 SHA1C page C7-2562 line 149854 MATCH x5e000000/mask=xffe0fc00\n# CONSTRUCT x5e000000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1c/3@4\n# AUNIT --inst x5e000000/mask=xffe0fc00 --status noqemu\n\n:sha1c Rd_VPR128, Rn_FPR32, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000000 & Rn_FPR32 & Rd_VPR128 & Zd\n{\n\tRd_VPR128 = NEON_sha1c(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.240 SHA1H page C7-2563 line 149925 MATCH x5e280800/mask=xfffffc00\n# CONSTRUCT x5e280800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 30:1 =<<\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sha1h/1\n# AUNIT --inst x5e280800/mask=xfffffc00 --status noqemu\n\n:sha1h Rd_FPR32, Rn_FPR32\nis b_2431=0b01011110 & b_2223=0b00 & b_1721=0b10100 & b_1216=0b00000 & b_1011=0b10 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = Rn_FPR32 << 30:1;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.241 SHA1M page C7-2564 line 149984 MATCH x5e002000/mask=xffe0fc00\n# CONSTRUCT x5e002000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1m/3@4\n# AUNIT --inst x5e002000/mask=xffe0fc00 --status noqemu\n\n:sha1m Rd_VPR128, Rn_FPR32, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001000 & Rn_FPR32 & Rd_VPR128 & Zd\n{\n\tRd_VPR128 = NEON_sha1m(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.242 SHA1P page C7-2565 line 150055 MATCH x5e001000/mask=xffe0fc00\n# CONSTRUCT x5e001000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1p/3@4\n# AUNIT --inst x5e001000/mask=xffe0fc00 --status noqemu\n\n:sha1p Rd_VPR128, Rn_FPR32, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000100 & Rn_FPR32 & Rd_VPR128 & Zd\n{\n\tRd_VPR128 = NEON_sha1p(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.243 SHA1SU0 page C7-2566 line 150126 MATCH x5e003000/mask=xffe0fc00\n# CONSTRUCT x5e003000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1su0/3@4\n# AUNIT --inst x5e003000/mask=xffe0fc00 --status noqemu\n\n:sha1su0 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001100 & Rn_VPR128.4S & Rd_VPR128.4S & Rd_VPR128 & Zd\n{\n\tRd_VPR128.4S = NEON_sha1su0(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.244 SHA1SU1 page C7-2567 line 150194 MATCH x5e281800/mask=xfffffc00\n# CONSTRUCT x5e281800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha1su1/2@4\n# AUNIT --inst x5e281800/mask=xfffffc00 --status noqemu\n\n:sha1su1 Rd_VPR128.4S, Rn_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b000110 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sha1su1(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.245 SHA256H2 page C7-2568 line 150260 MATCH x5e005000/mask=xffe0fc00\n# CONSTRUCT x5e005000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h2/3@4\n# AUNIT --inst x5e005000/mask=xffe0fc00 --status noqemu\n\n:sha256h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010100 & Rn_VPR128 & Rd_VPR128 & Zd\n{\n\tRd_VPR128 = NEON_sha256h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.246 SHA256H page C7-2569 line 150322 MATCH x5e004000/mask=xffe0fc00\n# CONSTRUCT x5e004000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h/3@4\n# AUNIT --inst x5e004000/mask=xffe0fc00 --status noqemu\n\n:sha256h Rd_VPR128, Rn_VPR128, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010000 & Rn_VPR128 & Rd_VPR128 & Zd\n{\n\tRd_VPR128 = NEON_sha256h(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.247 SHA256SU0 page C7-2570 line 150384 MATCH x5e282800/mask=xfffffc00\n# CONSTRUCT x5e282800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha256su0/2@4\n# AUNIT --inst x5e282800/mask=xfffffc00 --status noqemu\n\n:sha256su0 Rd_VPR128.4S, Rn_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b001010 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sha256su0(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.248 SHA256SU1 page C7-2571 line 150452 MATCH x5e006000/mask=xffe0fc00\n# CONSTRUCT x5e006000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256su1/3@4\n# AUNIT --inst x5e006000/mask=xffe0fc00 --status noqemu\n\n:sha256su1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b011000 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sha256su1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.249 SHA512H page C7-2573 line 150543 MATCH xce608000/mask=xffe0fc00\n# CONSTRUCT xce608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h/3@8\n# AUNIT --inst xce608000/mask=xffe0fc00 --status noqemu\n\n:sha512h Rd_VPR128, Rn_VPR128, Rm_VPR128.2D\nis b_2131=0b11001110011 & b_1015=0b100000 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd\n{\n\tRd_VPR128 = NEON_sha512h(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.250 SHA512H2 page C7-2575 line 150631 MATCH xce608400/mask=xffe0fc00\n# CONSTRUCT xce608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h2/3@8\n# AUNIT --inst xce608400/mask=xffe0fc00 --status noqemu\n\n:sha512h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.2D\nis b_2131=0b11001110011 & b_1015=0b100001 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd\n{\n\tRd_VPR128 = NEON_sha512h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.251 SHA512SU0 page C7-2577 line 150719 MATCH xcec08000/mask=xfffffc00\n# CONSTRUCT xcec08000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha512su0/2@8\n# AUNIT --inst xcec08000/mask=xfffffc00 --status noqemu\n\n:sha512su0 Rd_VPR128.2D, Rn_VPR128.2D\nis b_1031=0b1100111011000000100000 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sha512su0(Rd_VPR128.2D, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.252 SHA512SU1 page C7-2578 line 150789 MATCH xce608800/mask=xffe0fc00\n# CONSTRUCT xce608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512su1/3@8\n# AUNIT --inst xce608800/mask=xffe0fc00 --status noqemu\n\n:sha512su1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_2131=0b11001110011 & b_1015=0b100010 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sha512su1(Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00\n# CONSTRUCT x4e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1\n# AUNIT --inst x4e200400/mask=xffe0fc00 --status nopcodeop\n\n:shadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_shadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00\n# CONSTRUCT x0ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4\n# AUNIT --inst x0ea00400/mask=xffe0fc00 --status nopcodeop\n\n:shadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_shadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00\n# CONSTRUCT x0e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2\n# AUNIT --inst x0e600400/mask=xffe0fc00 --status nopcodeop\n\n:shadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_shadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00\n# CONSTRUCT x4ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4\n# AUNIT --inst x4ea00400/mask=xffe0fc00 --status nopcodeop\n\n:shadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_shadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00\n# CONSTRUCT x0e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1\n# AUNIT --inst x0e200400/mask=xffe0fc00 --status nopcodeop\n\n:shadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_shadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00\n# CONSTRUCT x4e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2\n# AUNIT --inst x4e600400/mask=xffe0fc00 --status nopcodeop\n\n:shadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_shadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x5f005400/mask=xff80fc00\n# CONSTRUCT x5f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2\n# AUNIT --inst x5f405400/mask=xffc0fc00 --status nopcodeop\n\n:shl Rd_FPR64, Rn_FPR64, Imm_imm0_63\nis b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_shl(Rn_FPR64, Imm_imm0_63:1);\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x4f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1\n# AUNIT --inst x4f085400/mask=xfff8fc00 --status pass\n\n:shl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tlocal tmp1:1 = Imm_uimm3;\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B << tmp1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] << tmp1;\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] << tmp1;\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] << tmp1;\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] << tmp1;\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] << tmp1;\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] << tmp1;\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] << tmp1;\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] << tmp1;\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] << tmp1;\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] << tmp1;\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] << tmp1;\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] << tmp1;\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] << tmp1;\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] << tmp1;\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] << tmp1;\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] << tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x4f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@8\n# AUNIT --inst x4f405400/mask=xffc0fc00 --status pass\n\n:shl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = Imm_imm0_63;\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D << tmp1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] << tmp1;\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] << tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x0f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4\n# AUNIT --inst x0f205400/mask=xffe0fc00 --status pass\n\n:shl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = Imm_uimm5;\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S << tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] << tmp1;\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] << tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x0f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2\n# AUNIT --inst x0f105400/mask=xfff0fc00 --status pass\n\n:shl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tlocal tmp1:2 = Imm_uimm4;\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H << tmp1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] << tmp1;\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] << tmp1;\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] << tmp1;\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] << tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x4f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4\n# AUNIT --inst x4f205400/mask=xffe0fc00 --status pass\n\n:shl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = Imm_uimm5;\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S << tmp1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] << tmp1;\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] << tmp1;\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] << tmp1;\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] << tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x0f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1\n# AUNIT --inst x0f085400/mask=xfff8fc00 --status pass\n\n:shl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tlocal tmp1:1 = Imm_uimm3;\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B << tmp1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] << tmp1;\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] << tmp1;\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] << tmp1;\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] << tmp1;\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] << tmp1;\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] << tmp1;\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] << tmp1;\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] << tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00\n# CONSTRUCT x4f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2\n# AUNIT --inst x4f105400/mask=xfff0fc00 --status pass\n\n:shl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tlocal tmp1:2 = Imm_uimm4;\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H << tmp1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] << tmp1;\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] << tmp1;\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] << tmp1;\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] << tmp1;\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] << tmp1;\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] << tmp1;\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] << tmp1;\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] << tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00\n# CONSTRUCT x2ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 zext:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@4\n# AUNIT --inst x2ea13800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:shll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm_exact32\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\tlocal tmp2:8 = zext(Imm_uimm_exact32);\n\t# simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00\n# CONSTRUCT x2e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@2\n# AUNIT --inst x2e613800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:shll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm_exact16\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ1 << Imm_uimm_exact16:4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] << Imm_uimm_exact16:4;\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] << Imm_uimm_exact16:4;\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] << Imm_uimm_exact16:4;\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] << Imm_uimm_exact16:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00\n# CONSTRUCT x2e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@1\n# AUNIT --inst x2e213800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:shll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm_exact8\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ1 << Imm_uimm_exact8:2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] << Imm_uimm_exact8:2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00\n# CONSTRUCT x6ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 zext:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@4\n# AUNIT --inst x6ea13800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:shll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm_exact32\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tlocal tmp3:8 = zext(Imm_uimm_exact32);\n\t# simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00\n# CONSTRUCT x6e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@2\n# AUNIT --inst x6e613800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:shll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm_exact16\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 << Imm_uimm_exact16:4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] << Imm_uimm_exact16:4;\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] << Imm_uimm_exact16:4;\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] << Imm_uimm_exact16:4;\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] << Imm_uimm_exact16:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00\n# CONSTRUCT x6e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@1\n# AUNIT --inst x6e213800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:shll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm_exact8\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 << Imm_uimm_exact8:2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] << Imm_uimm_exact8:2;\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] << Imm_uimm_exact8:2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# CONSTRUCT x0f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 =$zext@8:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@8\n# AUNIT --inst x0f208400/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:shrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm32);\n\t# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;\n\t# simd resize Rd_VPR64.2S = zext(TMPQ1) (lane size 8 to 4)\n\tRd_VPR64.2S[0,32] = TMPQ1[0,32];\n\tRd_VPR64.2S[32,32] = TMPQ1[64,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# CONSTRUCT x0f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:4 $>>@4 =$zext@4:16\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@4\n# AUNIT --inst x0f108400/mask=xfff0fc00 --status pass --comment \"ext\"\n\n:shrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4;\n\t# simd resize Rd_VPR64.4H = zext(TMPQ1) (lane size 4 to 2)\n\tRd_VPR64.4H[0,16] = TMPQ1[0,16];\n\tRd_VPR64.4H[16,16] = TMPQ1[32,16];\n\tRd_VPR64.4H[32,16] = TMPQ1[64,16];\n\tRd_VPR64.4H[48,16] = TMPQ1[96,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# CONSTRUCT x0f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $>>@2 =$zext@2:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@2\n# AUNIT --inst x0f088400/mask=xfff8fc00 --status pass --comment \"ext\"\n\n:shrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2;\n\t# simd resize Rd_VPR64.8B = zext(TMPQ1) (lane size 2 to 1)\n\tRd_VPR64.8B[0,8] = TMPQ1[0,8];\n\tRd_VPR64.8B[8,8] = TMPQ1[16,8];\n\tRd_VPR64.8B[16,8] = TMPQ1[32,8];\n\tRd_VPR64.8B[24,8] = TMPQ1[48,8];\n\tRd_VPR64.8B[32,8] = TMPQ1[64,8];\n\tRd_VPR64.8B[40,8] = TMPQ1[80,8];\n\tRd_VPR64.8B[48,8] = TMPQ1[96,8];\n\tRd_VPR64.8B[56,8] = TMPQ1[112,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# CONSTRUCT x4f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 $zext@8:8 1:1 &=$copy\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@8\n# AUNIT --inst x4f208400/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:shrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm32);\n\t# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;\n\t# simd resize TMPD2 = zext(TMPQ1) (lane size 8 to 4)\n\tTMPD2[0,32] = TMPQ1[0,32];\n\tTMPD2[32,32] = TMPQ1[64,32];\n\t# simd copy Rd_VPR128.4S element 1:1 = TMPD2 (lane size 8)\n\tRd_VPR128.4S[64,64] = TMPD2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# CONSTRUCT x4f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:4 $>>@4 $zext@4:8 1:1 &=$copy\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@4\n# AUNIT --inst x4f108400/mask=xfff0fc00 --status pass --comment \"ext\"\n\n:shrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4;\n\t# simd resize TMPD2 = zext(TMPQ1) (lane size 4 to 2)\n\tTMPD2[0,16] = TMPQ1[0,16];\n\tTMPD2[16,16] = TMPQ1[32,16];\n\tTMPD2[32,16] = TMPQ1[64,16];\n\tTMPD2[48,16] = TMPQ1[96,16];\n\t# simd copy Rd_VPR128.8H element 1:1 = TMPD2 (lane size 8)\n\tRd_VPR128.8H[64,64] = TMPD2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00\n# CONSTRUCT x4f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $>>@2 $zext@2:8 1:1 &=$copy\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@2\n# AUNIT --inst x4f088400/mask=xfff8fc00 --status pass --comment \"ext\"\n\n:shrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2;\n\t# simd resize TMPD2 = zext(TMPQ1) (lane size 2 to 1)\n\tTMPD2[0,8] = TMPQ1[0,8];\n\tTMPD2[8,8] = TMPQ1[16,8];\n\tTMPD2[16,8] = TMPQ1[32,8];\n\tTMPD2[24,8] = TMPQ1[48,8];\n\tTMPD2[32,8] = TMPQ1[64,8];\n\tTMPD2[40,8] = TMPQ1[80,8];\n\tTMPD2[48,8] = TMPQ1[96,8];\n\tTMPD2[56,8] = TMPQ1[112,8];\n\t# simd copy Rd_VPR128.16B element 1:1 = TMPD2 (lane size 8)\n\tRd_VPR128.16B[64,64] = TMPD2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00\n# CONSTRUCT x4e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1\n# AUNIT --inst x4e202400/mask=xffe0fc00 --status nopcodeop\n\n:shsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_shsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00\n# CONSTRUCT x0ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4\n# AUNIT --inst x0ea02400/mask=xffe0fc00 --status nopcodeop\n\n:shsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_shsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00\n# CONSTRUCT x0e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2\n# AUNIT --inst x0e602400/mask=xffe0fc00 --status nopcodeop\n\n:shsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_shsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00\n# CONSTRUCT x4ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4\n# AUNIT --inst x4ea02400/mask=xffe0fc00 --status nopcodeop\n\n:shsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_shsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00\n# CONSTRUCT x0e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1\n# AUNIT --inst x0e202400/mask=xffe0fc00 --status nopcodeop\n\n:shsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_shsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00\n# CONSTRUCT x4e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2\n# AUNIT --inst x4e602400/mask=xffe0fc00 --status nopcodeop\n\n:shsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_shsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x6f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1\n# AUNIT --inst x6f085400/mask=xfff8fc00 --status nopcodeop\n\n:sli Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sli(Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x6f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@8\n# AUNIT --inst x6f405400/mask=xffc0fc00 --status nopcodeop\n\n:sli Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sli(Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63:1, 8:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x2f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4\n# AUNIT --inst x2f205400/mask=xffe0fc00 --status nopcodeop\n\n:sli Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sli(Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x2f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2\n# AUNIT --inst x2f105400/mask=xfff0fc00 --status nopcodeop\n\n:sli Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sli(Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x6f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4\n# AUNIT --inst x6f205400/mask=xffe0fc00 --status nopcodeop\n\n:sli Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sli(Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x2f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1\n# AUNIT --inst x2f085400/mask=xfff8fc00 --status nopcodeop\n\n:sli Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sli(Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00\n# CONSTRUCT x6f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2\n# AUNIT --inst x6f105400/mask=xfff0fc00 --status nopcodeop\n\n:sli Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sli(Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.258 SLI page C7-2591 line 151468 MATCH x7f005400/mask=xff80fc00\n# CONSTRUCT x7f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3\n# AUNIT --inst x7f405400/mask=xffc0fc00 --status nopcodeop\n\n:sli Rd_VPR64, Rn_VPR64, Imm_uimm5\nis b_2331=0b011111110 & b_22=1 & b_1015=0b010101 & Rd_VPR64 & Rn_VPR64 & Imm_uimm5 & Zd\n{\n\tRd_VPR64 = NEON_sli(Rd_VPR64, Rn_VPR64, Imm_uimm5:1);\n}\n\n# C7.2.259 SM3PARTW1 page C7-2594 line 151635 MATCH xce60c000/mask=xffe0fc00\n# CONSTRUCT xce60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw1/3@4\n# AUNIT --inst xce60c000/mask=xffe0fc00 --status noqemu\n\n:sm3partw1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_2131=0b11001110011 & b_1015=0b110000 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sm3partw1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.260 SM3PARTW2 page C7-2596 line 151723 MATCH xce60c400/mask=xffe0fc00\n# CONSTRUCT xce60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw2/3@4\n# AUNIT --inst xce60c400/mask=xffe0fc00 --status noqemu\n\n:sm3partw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_2131=0b11001110011 & b_1015=0b110001 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sm3partw2(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.261 SM3SS1 page C7-2598 line 151808 MATCH xce400000/mask=xffe08000\n# CONSTRUCT xce400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_sm3ss1/3@4\n# AUNIT --inst xce400000/mask=xffe08000 --status noqemu\n\n:sm3ss1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S\nis b_2131=0b11001110010 & b_15=0 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Ra_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sm3ss1(Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S, 4:1);\n}\n\n# C7.2.247 SM3TT1A page C7-1529 line 88534 KEEPWITH\n\nsm3imm2: b_1213 is b_1213 { export *[const]:4 b_1213; }\nRe_VPR128.S.sm3imm2: Re_VPR128.S^\"[\"^sm3imm2^\"]\" is Re_VPR128.S & sm3imm2 { export Re_VPR128.S; }\n\n# C7.2.262 SM3TT1A page C7-2600 line 151893 MATCH xce408000/mask=xffe0cc00\n# CONSTRUCT xce408000/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1a/3@4\n# AUNIT --inst xce408000/mask=xffe0cc00 --status noqemu\n\n:sm3tt1a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2\nis b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b00 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);\n\tRd_VPR128.4S = NEON_sm3tt1a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);\n}\n\n# C7.2.263 SM3TT1B page C7-2602 line 151999 MATCH xce408400/mask=xffe0cc00\n# CONSTRUCT xce408400/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1b/3@4\n# AUNIT --inst xce408400/mask=xffe0cc00 --status noqemu\n\n:sm3tt1b Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2\nis b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b01 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);\n\tRd_VPR128.4S = NEON_sm3tt1b(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);\n}\n\n# C7.2.264 SM3TT2A page C7-2604 line 152105 MATCH xce408800/mask=xffe0cc00\n# CONSTRUCT xce408800/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2a/3@4\n# AUNIT --inst xce408800/mask=xffe0cc00 --status noqemu\n\n:sm3tt2a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2\nis b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b10 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);\n\tRd_VPR128.4S = NEON_sm3tt2a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);\n}\n\n# C7.2.265 SM3TT2B page C7-2606 line 152210 MATCH xce408c00/mask=xffe0cc00\n# CONSTRUCT xce408c00/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2b/3@4\n# AUNIT --inst xce408c00/mask=xffe0cc00 --status noqemu\n\n:sm3tt2b Rd_VPR128.S, Rn_VPR128.S, Re_VPR128.S.sm3imm2\nis b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b11 & Rd_VPR128.S & Rn_VPR128.S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);\n\tRd_VPR128.S = NEON_sm3tt2b(Rd_VPR128.S, Rn_VPR128.S, tmp1, 4:1);\n}\n\n# C7.2.266 SM4E page C7-2608 line 152315 MATCH xcec08400/mask=xfffffc00\n# CONSTRUCT xcec08400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sm4e/2@4\n# AUNIT --inst xcec08400/mask=xfffffc00 --status noqemu\n\n:sm4e Rd_VPR128.4S, Rn_VPR128.4S\nis b_1031=0b1100111011000000100001 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sm4e(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.267 SM4EKEY page C7-2610 line 152409 MATCH xce60c800/mask=xffe0fc00\n# CONSTRUCT xce60c800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm4ekey/3@4\n# AUNIT --inst xce60c800/mask=xffe0fc00 --status noqemu\n\n:sm4ekey Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_2131=0b11001110011 & b_1015=0b110010 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sm4ekey(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00\n# CONSTRUCT x4e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1\n# AUNIT --inst x4e206400/mask=xffe0fc00 --status nopcodeop\n\n:smax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00\n# CONSTRUCT x0ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4\n# AUNIT --inst x0ea06400/mask=xffe0fc00 --status nopcodeop\n\n:smax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_smax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00\n# CONSTRUCT x0e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2\n# AUNIT --inst x0e606400/mask=xffe0fc00 --status nopcodeop\n\n:smax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_smax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00\n# CONSTRUCT x4ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4\n# AUNIT --inst x4ea06400/mask=xffe0fc00 --status nopcodeop\n\n:smax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_smax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00\n# CONSTRUCT x0e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1\n# AUNIT --inst x0e206400/mask=xffe0fc00 --status nopcodeop\n\n:smax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_smax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00\n# CONSTRUCT x4e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2\n# AUNIT --inst x4e606400/mask=xffe0fc00 --status nopcodeop\n\n:smax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_smax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00\n# CONSTRUCT x4e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1\n# AUNIT --inst x4e20a400/mask=xffe0fc00 --status nopcodeop\n\n:smaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00\n# CONSTRUCT x0ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4\n# AUNIT --inst x0ea0a400/mask=xffe0fc00 --status nopcodeop\n\n:smaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_smaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00\n# CONSTRUCT x0e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2\n# AUNIT --inst x0e60a400/mask=xffe0fc00 --status nopcodeop\n\n:smaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_smaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00\n# CONSTRUCT x4ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4\n# AUNIT --inst x4ea0a400/mask=xffe0fc00 --status nopcodeop\n\n:smaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_smaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00\n# CONSTRUCT x0e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@1\n# AUNIT --inst x0e20a400/mask=xffe0fc00 --status nopcodeop\n\n:smaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_smaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00\n# CONSTRUCT x4e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2\n# AUNIT --inst x4e60a400/mask=xffe0fc00 --status nopcodeop\n\n:smaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_smaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00\n# CONSTRUCT x4e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1\n# AUNIT --inst x4e30a800/mask=xfffffc00 --status nopcodeop\n\n:smaxv Rd_FPR8, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_smaxv(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00\n# CONSTRUCT x0e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1\n# AUNIT --inst x0e30a800/mask=xfffffc00 --status nopcodeop\n\n:smaxv Rd_FPR8, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_smaxv(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00\n# CONSTRUCT x0e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2\n# AUNIT --inst x0e70a800/mask=xfffffc00 --status nopcodeop\n\n:smaxv Rd_FPR16, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_smaxv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00\n# CONSTRUCT x4e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2\n# AUNIT --inst x4e70a800/mask=xfffffc00 --status nopcodeop\n\n:smaxv Rd_FPR16, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_smaxv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00\n# CONSTRUCT x4eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@4\n# AUNIT --inst x4eb0a800/mask=xfffffc00 --status nopcodeop\n\n:smaxv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_smaxv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00\n# CONSTRUCT x4e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1\n# AUNIT --inst x4e206c00/mask=xffe0fc00 --status nopcodeop\n\n:smin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_smin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00\n# CONSTRUCT x0ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4\n# AUNIT --inst x0ea06c00/mask=xffe0fc00 --status nopcodeop\n\n:smin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_smin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00\n# CONSTRUCT x0e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2\n# AUNIT --inst x0e606c00/mask=xffe0fc00 --status nopcodeop\n\n:smin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_smin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00\n# CONSTRUCT x4ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4\n# AUNIT --inst x4ea06c00/mask=xffe0fc00 --status nopcodeop\n\n:smin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_smin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00\n# CONSTRUCT x0e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1\n# AUNIT --inst x0e206c00/mask=xffe0fc00 --status nopcodeop\n\n:smin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_smin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00\n# CONSTRUCT x4e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2\n# AUNIT --inst x4e606c00/mask=xffe0fc00 --status nopcodeop\n\n:smin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_smin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00\n# CONSTRUCT x4e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1\n# AUNIT --inst x4e20ac00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:sminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00\n# CONSTRUCT x0ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4\n# AUNIT --inst x0ea0ac00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:sminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00\n# CONSTRUCT x0e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2\n# AUNIT --inst x0e60ac00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:sminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00\n# CONSTRUCT x4ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4\n# AUNIT --inst x4ea0ac00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:sminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00\n# CONSTRUCT x0e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1\n# AUNIT --inst x0e20ac00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:sminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00\n# CONSTRUCT x4e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2\n# AUNIT --inst x4e60ac00/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:sminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00\n# CONSTRUCT x4e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1\n# AUNIT --inst x4e31a800/mask=xfffffc00 --status nopcodeop\n\n:sminv Rd_FPR8, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sminv(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00\n# CONSTRUCT x0e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1\n# AUNIT --inst x0e31a800/mask=xfffffc00 --status nopcodeop\n\n:sminv Rd_FPR8, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sminv(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00\n# CONSTRUCT x0e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2\n# AUNIT --inst x0e71a800/mask=xfffffc00 --status nopcodeop\n\n:sminv Rd_FPR16, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sminv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00\n# CONSTRUCT x4e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2\n# AUNIT --inst x4e71a800/mask=xfffffc00 --status nopcodeop\n\n:sminv Rd_FPR16, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sminv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00\n# CONSTRUCT x4eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@4\n# AUNIT --inst x4eb1a800/mask=xfffffc00 --status nopcodeop\n\n:sminv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sminv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400\n# CONSTRUCT x0f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4\n# AUNIT --inst x0f802000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400\n# CONSTRUCT x0f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2\n# AUNIT --inst x0f402000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400\n# CONSTRUCT x4f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4\n# AUNIT --inst x4f802000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400\n# CONSTRUCT x4f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2\n# AUNIT --inst x4f402000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00\n# CONSTRUCT x0ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4\n# AUNIT --inst x0ea08000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00\n# CONSTRUCT x0e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2\n# AUNIT --inst x0e608000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00\n# CONSTRUCT x0e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@1\n# AUNIT --inst x0e208000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00\n# CONSTRUCT x4ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4\n# AUNIT --inst x4ea08000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00\n# CONSTRUCT x4e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2\n# AUNIT --inst x4e608000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00\n# CONSTRUCT x4e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@1\n# AUNIT --inst x4e208000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400\n# CONSTRUCT x0f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4\n# AUNIT --inst x0f806000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400\n# CONSTRUCT x0f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2\n# AUNIT --inst x0f406000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400\n# CONSTRUCT x4f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4\n# AUNIT --inst x4f806000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400\n# CONSTRUCT x4f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2\n# AUNIT --inst x4f406000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00\n# CONSTRUCT x0ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4\n# AUNIT --inst x0ea0a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00\n# CONSTRUCT x0e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2\n# AUNIT --inst x0e60a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00\n# CONSTRUCT x0e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@1\n# AUNIT --inst x0e20a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00\n# CONSTRUCT x4ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4\n# AUNIT --inst x4ea0a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00\n# CONSTRUCT x4e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2\n# AUNIT --inst x4e60a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00\n# CONSTRUCT x4e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@1\n# AUNIT --inst x4e20a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00\n# CONSTRUCT x0e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sext\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1\n# AUNIT --inst x0e012c00/mask=xffe1fc00 --status pass\n\n:smov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm4] lane size 1\n\tlocal tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;\n\tRd_GPR32 = sext(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00\n# CONSTRUCT x0e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sext\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1\n# AUNIT --inst x0e022c00/mask=xffe3fc00 --status pass\n\n:smov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm3] lane size 2\n\tlocal tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;\n\tRd_GPR32 = sext(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00\n# CONSTRUCT x4e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sext\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1\n# AUNIT --inst x4e012c00/mask=xffe1fc00 --status pass\n\n:smov Rd_GPR64, Rn_VPR128.B.imm_neon_uimm4\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm4] lane size 1\n\tlocal tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;\n\tRd_GPR64 = sext(tmp1);\n}\n\n# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00\n# CONSTRUCT x4e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sext\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1\n# AUNIT --inst x4e022c00/mask=xffe3fc00 --status pass\n\n:smov Rd_GPR64, Rn_VPR128.H.imm_neon_uimm3\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm3] lane size 2\n\tlocal tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;\n\tRd_GPR64 = sext(tmp1);\n}\n\n# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00\n# CONSTRUCT x4e042c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =sext\n# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1\n# AUNIT --inst x4e042c00/mask=xffe7fc00 --status pass\n\n:smov Rd_GPR64, Rn_VPR128.S.imm_neon_uimm2\nis b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm2] lane size 4\n\tlocal tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;\n\tRd_GPR64 = sext(tmp1);\n}\n\n# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400\n# CONSTRUCT x0f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4\n# AUNIT --inst x0f80a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3;\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400\n# CONSTRUCT x0f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2\n# AUNIT --inst x0f40a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3;\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3;\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3;\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400\n# CONSTRUCT x4f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4\n# AUNIT --inst x4f80a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = sext(tmp3);\n\t# simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4;\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400\n# CONSTRUCT x4f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2\n# AUNIT --inst x4f40a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = sext(tmp3);\n\t# simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4;\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4;\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4;\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00\n# CONSTRUCT x0ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$*@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4\n# AUNIT --inst x0ea0c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ1 * TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00\n# CONSTRUCT x0e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2\n# AUNIT --inst x0e60c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ1 * TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00\n# CONSTRUCT x0e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@1\n# AUNIT --inst x0e20c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ1 * TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] * TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] * TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] * TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] * TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] * TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] * TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] * TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] * TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00\n# CONSTRUCT x4ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$*@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4\n# AUNIT --inst x4ea0c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Rm_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00\n# CONSTRUCT x4e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2\n# AUNIT --inst x4e60c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00\n# CONSTRUCT x4e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@1\n# AUNIT --inst x4e20c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:smull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00\n# CONSTRUCT x5e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =abs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1\n# AUNIT --inst x5e207800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size = 00 Q = 1 aa=1 suf=FPR8\n# Note: in some implemented semantics that ignore saturation (where it\n# makes a difference), there is an error in about 50% of the lanes.\n\n:sqabs Rd_FPR8, Rn_FPR8\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd\n{\n\tRd_FPR8 = MP_INT_ABS(Rn_FPR8);\n\tzext_zb(Zd); # zero upper 31 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00\n# CONSTRUCT x5e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =abs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1\n# AUNIT --inst x5e607800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size = 01 Q = 1 aa=1 suf=FPR16\n\n:sqabs Rd_FPR16, Rn_FPR16\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = MP_INT_ABS(Rn_FPR16);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00\n# CONSTRUCT x5ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =abs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1\n# AUNIT --inst x5ea07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size = 10 Q = 1 aa=1 suf=FPR32\n\n:sqabs Rd_FPR32, Rn_FPR32\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = MP_INT_ABS(Rn_FPR32);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00\n# CONSTRUCT x5ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =abs\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1\n# AUNIT --inst x5ee07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size = 11 Q = 1 aa=1 suf=FPR64\n\n:sqabs Rd_FPR64, Rn_FPR64\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = MP_INT_ABS(Rn_FPR64);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x0e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1\n# AUNIT --inst x0e207800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size = 00 Q = 0 aa=0 esize=1 suf=VPR64.8B\n\n:sqabs Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1\n\tRd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]);\n\tRd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]);\n\tRd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]);\n\tRd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]);\n\tRd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]);\n\tRd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]);\n\tRd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]);\n\tRd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x4e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1\n# AUNIT --inst x4e207800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size = 00 Q = 1 aa=0 esize=1 suf=VPR128.16B\n\n:sqabs Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1\n\tRd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]);\n\tRd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]);\n\tRd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]);\n\tRd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]);\n\tRd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]);\n\tRd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]);\n\tRd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]);\n\tRd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]);\n\tRd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]);\n\tRd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]);\n\tRd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]);\n\tRd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]);\n\tRd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]);\n\tRd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]);\n\tRd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]);\n\tRd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x0e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2\n# AUNIT --inst x0e607800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when size = 01 Q = 0 aa=0 esize=2 suf=VPR64.4H\n\n:sqabs Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x4e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2\n# AUNIT --inst x4e607800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when size = 01 Q = 1 aa=0 esize=2 suf=VPR128.8H\n\n:sqabs Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x0ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4\n# AUNIT --inst x0ea07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when size = 10 Q = 0 aa=0 esize=4 suf=VPR64.2S\n\n:sqabs Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x4ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4\n# AUNIT --inst x4ea07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when size = 10 Q = 1 aa=0 esize=4 suf=VPR128.4S\n\n:sqabs Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00\n# CONSTRUCT x4ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$abs@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@8\n# AUNIT --inst x4ee07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when size = 11 Q = 1 aa=0 esize=8 suf=VPR128.2D\n\n:sqabs Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00\n# CONSTRUCT x5e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2\n# AUNIT --inst x5e200c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sqadd(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00\n# CONSTRUCT x5ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2\n# AUNIT --inst x5ee00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_sqadd(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00\n# CONSTRUCT x5e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2\n# AUNIT --inst x5e600c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqadd(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00\n# CONSTRUCT x5ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2\n# AUNIT --inst x5ea00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqadd(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x4e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1\n# AUNIT --inst x4e200c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x4ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@8\n# AUNIT --inst x4ee00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x0ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4\n# AUNIT --inst x0ea00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x0e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2\n# AUNIT --inst x0e600c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x4ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4\n# AUNIT --inst x4ea00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x0e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1\n# AUNIT --inst x0e200c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00\n# CONSTRUCT x4e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2\n# AUNIT --inst x4e600c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x5f003000/mask=xff00f400\n# CONSTRUCT x5f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+/2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3\n# AUNIT --inst x5f803000/mask=xffc0f400 --status fail --comment \"nointsat\"\n# scalar variant, size == 10 (always part == 0)\n\n:sqdmlal Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\tlocal tmp4:8 = tmp1 * tmp3;\n\tlocal tmp5:8 = tmp4 * 2:8;\n\tRd_FPR64 = Rd_FPR64 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x5f003000/mask=xff00f400\n# CONSTRUCT x5f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 sext:4 ARG2 sext:4 * 2:4 * &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3\n# AUNIT --inst x5f403000/mask=xffc0f400 --status fail --comment \"nointsat\"\n# scalar variant, size == 01 (always part == 0)\n\n:sqdmlal Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd\n{\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp1:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp2:4 = sext(tmp1);\n\tlocal tmp3:4 = sext(Rn_FPR16);\n\tlocal tmp4:4 = tmp2 * tmp3;\n\tlocal tmp5:4 = tmp4 * 2:4;\n\tRd_FPR32 = Rd_FPR32 + tmp5;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400\n# CONSTRUCT x0f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4\n# AUNIT --inst x0f803000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q == 0, size == 10\n\n:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * 2:8;\n\tTMPQ3[64,64] = TMPQ2[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400\n# CONSTRUCT x0f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2\n# AUNIT --inst x0f403000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 0, size == 01\n\n:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * 2:4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * 2:4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * 2:4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400\n# CONSTRUCT x4f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4\n# AUNIT --inst x4f803000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 10\n\n:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8\n\tTMPQ4[0,64] = TMPQ3[0,64] * 2:8;\n\tTMPQ4[64,64] = TMPQ3[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400\n# CONSTRUCT x4f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2\n# AUNIT --inst x4f403000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 01\n\n:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4\n\tTMPQ4[0,32] = TMPQ3[0,32] * 2:4;\n\tTMPQ4[32,32] = TMPQ3[32,32] * 2:4;\n\tTMPQ4[64,32] = TMPQ3[64,32] * 2:4;\n\tTMPQ4[96,32] = TMPQ3[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x5e209000/mask=xff20fc00\n# CONSTRUCT x5ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3\n# AUNIT --inst x5ea09000/mask=xffe0fc00 --status fail --comment \"nointsat\"\n# scalar variant, size == 10 (always part == 0)\n\n:sqdmlal Rd_FPR64, Rn_FPR32, Rm_FPR32\nis b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\tlocal tmp2:8 = sext(Rm_FPR32);\n\tlocal tmp3:8 = tmp1 * tmp2;\n\tlocal tmp4:8 = tmp3 * 2:8;\n\tRd_FPR64 = Rd_FPR64 + tmp4;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x5e209000/mask=xff20fc00\n# CONSTRUCT x5e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3\n# AUNIT --inst x5e609000/mask=xffe0fc00 --status fail --comment \"nointsat\"\n# scalar variant, size == 01 (always part == 0)\n\n:sqdmlal Rd_FPR32, Rn_FPR16, Rm_FPR16\nis b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\tlocal tmp2:4 = sext(Rm_FPR16);\n\tlocal tmp3:4 = tmp1 * tmp2;\n\tlocal tmp4:4 = tmp3 * 2:4;\n\tRd_FPR32 = Rd_FPR32 + tmp4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00\n# CONSTRUCT x0ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4\n# AUNIT --inst x0ea09000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q == 0, size == 10\n\n:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\t# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8\n\tTMPQ4[0,64] = TMPQ3[0,64] * 2:8;\n\tTMPQ4[64,64] = TMPQ3[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00\n# CONSTRUCT x0e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2\n# AUNIT --inst x0e609000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 0, size == 01\n\n:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\t# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4\n\tTMPQ4[0,32] = TMPQ3[0,32] * 2:4;\n\tTMPQ4[32,32] = TMPQ3[32,32] * 2:4;\n\tTMPQ4[64,32] = TMPQ3[64,32] * 2:4;\n\tTMPQ4[96,32] = TMPQ3[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00\n# CONSTRUCT x4ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4\n# AUNIT --inst x4ea09000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 10\n\n:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8\n\tTMPQ6[0,64] = TMPQ5[0,64] * 2:8;\n\tTMPQ6[64,64] = TMPQ5[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00\n# CONSTRUCT x4e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2\n# AUNIT --inst x4e609000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 01\n\n:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4\n\tTMPQ6[0,32] = TMPQ5[0,32] * 2:4;\n\tTMPQ6[32,32] = TMPQ5[32,32] * 2:4;\n\tTMPQ6[64,32] = TMPQ5[64,32] * 2:4;\n\tTMPQ6[96,32] = TMPQ5[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x5f007000/mask=xff00f400\n# CONSTRUCT x5f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3\n# AUNIT --inst x5f807000/mask=xffc0f400 --status fail --comment \"nointsat\"\n# scalar variant, size == 10 (always part == 0)\n\n:sqdmlsl Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\tlocal tmp4:8 = tmp1 * tmp3;\n\tlocal tmp5:8 = tmp4 * 2:8;\n\tRd_FPR64 = Rd_FPR64 - tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x5f007000/mask=xff00f400\n# CONSTRUCT x5f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3\n# AUNIT --inst x5f407000/mask=xffc0f400 --status fail --comment \"nointsat\"\n# scalar variant, size == 01 (always part == 0)\n\n:sqdmlsl Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\tlocal tmp4:4 = tmp1 * tmp3;\n\tlocal tmp5:4 = tmp4 * 2:4;\n\tRd_FPR32 = Rd_FPR32 - tmp5;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400\n# CONSTRUCT x0f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4\n# AUNIT --inst x0f807000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q == 0, size == 10\n\n:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * 2:8;\n\tTMPQ3[64,64] = TMPQ2[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400\n# CONSTRUCT x0f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2\n# AUNIT --inst x0f407000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 0, size == 01\n\n:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * 2:4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * 2:4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * 2:4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400\n# CONSTRUCT x4f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4\n# AUNIT --inst x4f807000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 10\n\n:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8\n\tTMPQ4[0,64] = TMPQ3[0,64] * 2:8;\n\tTMPQ4[64,64] = TMPQ3[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400\n# CONSTRUCT x4f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2\n# AUNIT --inst x4f407000/mask=xffc0f400 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 01\n\n:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4\n\tTMPQ4[0,32] = TMPQ3[0,32] * 2:4;\n\tTMPQ4[32,32] = TMPQ3[32,32] * 2:4;\n\tTMPQ4[64,32] = TMPQ3[64,32] * 2:4;\n\tTMPQ4[96,32] = TMPQ3[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x5e20b000/mask=xff20fc00\n# CONSTRUCT x5ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3\n# AUNIT --inst x5ea0b000/mask=xffe0fc00 --status fail --comment \"nointsat\"\n# scalar variant, size == 10 (always part == 0)\n\n:sqdmlsl Rd_FPR64, Rn_FPR32, Rm_FPR32\nis b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\tlocal tmp2:8 = sext(Rm_FPR32);\n\tlocal tmp3:8 = tmp1 * tmp2;\n\tlocal tmp4:8 = tmp3 * 2:8;\n\tRd_FPR64 = Rd_FPR64 - tmp4;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x5e20b000/mask=xff20fc00\n# CONSTRUCT x5e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3\n# AUNIT --inst x5e60b000/mask=xffe0fc00 --status fail --comment \"nointsat\"\n# scalar variant, size == 01 (always part == 0)\n\n:sqdmlsl Rd_FPR32, Rn_FPR16, Rm_FPR16\nis b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\tlocal tmp2:4 = sext(Rm_FPR16);\n\tlocal tmp3:4 = tmp1 * tmp2;\n\tlocal tmp4:4 = tmp3 * 2:4;\n\tRd_FPR32 = Rd_FPR32 - tmp4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00\n# CONSTRUCT x0ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3\n# AUNIT --inst x0ea0b000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q == 0, size == 10\n\n:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\t# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8\n\tTMPQ4[0,64] = TMPQ3[0,64] * 2:8;\n\tTMPQ4[64,64] = TMPQ3[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00\n# CONSTRUCT x0e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2\n# AUNIT --inst x0e60b000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 0, size == 01\n\n:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\t# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4\n\tTMPQ4[0,32] = TMPQ3[0,32] * 2:4;\n\tTMPQ4[32,32] = TMPQ3[32,32] * 2:4;\n\tTMPQ4[64,32] = TMPQ3[64,32] * 2:4;\n\tTMPQ4[96,32] = TMPQ3[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00\n# CONSTRUCT x4ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4\n# AUNIT --inst x4ea0b000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 10\n\n:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8\n\tTMPQ6[0,64] = TMPQ5[0,64] * 2:8;\n\tTMPQ6[64,64] = TMPQ5[64,64] * 2:8;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ6 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ6[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ6[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00\n# CONSTRUCT x4e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2\n# AUNIT --inst x4e60b000/mask=xffe0fc00 --status fail --comment \"ext nointsat\"\n# vector variant, Q = 1, size == 01\n\n:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4\n\tTMPQ6[0,32] = TMPQ5[0,32] * 2:4;\n\tTMPQ6[32,32] = TMPQ5[32,32] * 2:4;\n\tTMPQ6[64,32] = TMPQ5[64,32] * 2:4;\n\tTMPQ6[96,32] = TMPQ5[96,32] * 2:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ6 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ6[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ6[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ6[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ6[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400\n# CONSTRUCT x0f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4\n# AUNIT --inst x0f80c000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * 2:8;\n\tTMPQ3[64,64] = TMPQ2[64,64] * 2:8;\n\t# simd shuffle Rd_VPR64.2S = TMPQ3 (@1-0@3-1) lane size 4\n\tRd_VPR64.2S[0,32] = TMPQ3[32,32];\n\tRd_VPR64.2S[32,32] = TMPQ3[96,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400\n# CONSTRUCT x0f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2\n# AUNIT --inst x0f40c000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * 2:4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * 2:4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * 2:4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * 2:4;\n\t# simd shuffle Rd_VPR64.4H = TMPQ3 (@1-0@3-1@5-2@7-3) lane size 2\n\tRd_VPR64.4H[0,16] = TMPQ3[16,16];\n\tRd_VPR64.4H[16,16] = TMPQ3[48,16];\n\tRd_VPR64.4H[32,16] = TMPQ3[80,16];\n\tRd_VPR64.4H[48,16] = TMPQ3[112,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400\n# CONSTRUCT x4f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:32 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1@5-2@7-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4\n# AUNIT --inst x4f80c000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPZ1 = sext(Rn_VPR128.4S) (lane size 4 to 8)\n\tTMPZ1[0,64] = sext(Rn_VPR128.4S[0,32]);\n\tTMPZ1[64,64] = sext(Rn_VPR128.4S[32,32]);\n\tTMPZ1[128,64] = sext(Rn_VPR128.4S[64,32]);\n\tTMPZ1[192,64] = sext(Rn_VPR128.4S[96,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 8\n\tTMPZ2[0,64] = TMPZ1[0,64] * tmp3;\n\tTMPZ2[64,64] = TMPZ1[64,64] * tmp3;\n\tTMPZ2[128,64] = TMPZ1[128,64] * tmp3;\n\tTMPZ2[192,64] = TMPZ1[192,64] * tmp3;\n\t# simd infix TMPZ3 = TMPZ2 * 2:8 on lane size 8\n\tTMPZ3[0,64] = TMPZ2[0,64] * 2:8;\n\tTMPZ3[64,64] = TMPZ2[64,64] * 2:8;\n\tTMPZ3[128,64] = TMPZ2[128,64] * 2:8;\n\tTMPZ3[192,64] = TMPZ2[192,64] * 2:8;\n\t# simd shuffle Rd_VPR128.4S = TMPZ3 (@1-0@3-1@5-2@7-3) lane size 4\n\tRd_VPR128.4S[0,32] = TMPZ3[32,32];\n\tRd_VPR128.4S[32,32] = TMPZ3[96,32];\n\tRd_VPR128.4S[64,32] = TMPZ3[160,32];\n\tRd_VPR128.4S[96,32] = TMPZ3[224,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400\n# CONSTRUCT x4f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:32 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2\n# AUNIT --inst x4f40c000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPZ1 = sext(Rn_VPR128.8H) (lane size 2 to 4)\n\tTMPZ1[0,32] = sext(Rn_VPR128.8H[0,16]);\n\tTMPZ1[32,32] = sext(Rn_VPR128.8H[16,16]);\n\tTMPZ1[64,32] = sext(Rn_VPR128.8H[32,16]);\n\tTMPZ1[96,32] = sext(Rn_VPR128.8H[48,16]);\n\tTMPZ1[128,32] = sext(Rn_VPR128.8H[64,16]);\n\tTMPZ1[160,32] = sext(Rn_VPR128.8H[80,16]);\n\tTMPZ1[192,32] = sext(Rn_VPR128.8H[96,16]);\n\tTMPZ1[224,32] = sext(Rn_VPR128.8H[112,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 4\n\tTMPZ2[0,32] = TMPZ1[0,32] * tmp3;\n\tTMPZ2[32,32] = TMPZ1[32,32] * tmp3;\n\tTMPZ2[64,32] = TMPZ1[64,32] * tmp3;\n\tTMPZ2[96,32] = TMPZ1[96,32] * tmp3;\n\tTMPZ2[128,32] = TMPZ1[128,32] * tmp3;\n\tTMPZ2[160,32] = TMPZ1[160,32] * tmp3;\n\tTMPZ2[192,32] = TMPZ1[192,32] * tmp3;\n\tTMPZ2[224,32] = TMPZ1[224,32] * tmp3;\n\t# simd infix TMPZ3 = TMPZ2 * 2:4 on lane size 4\n\tTMPZ3[0,32] = TMPZ2[0,32] * 2:4;\n\tTMPZ3[32,32] = TMPZ2[32,32] * 2:4;\n\tTMPZ3[64,32] = TMPZ2[64,32] * 2:4;\n\tTMPZ3[96,32] = TMPZ2[96,32] * 2:4;\n\tTMPZ3[128,32] = TMPZ2[128,32] * 2:4;\n\tTMPZ3[160,32] = TMPZ2[160,32] * 2:4;\n\tTMPZ3[192,32] = TMPZ2[192,32] * 2:4;\n\tTMPZ3[224,32] = TMPZ2[224,32] * 2:4;\n\t# simd shuffle Rd_VPR128.8H = TMPZ3 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 2\n\tRd_VPR128.8H[0,16] = TMPZ3[16,16];\n\tRd_VPR128.8H[16,16] = TMPZ3[48,16];\n\tRd_VPR128.8H[32,16] = TMPZ3[80,16];\n\tRd_VPR128.8H[48,16] = TMPZ3[112,16];\n\tRd_VPR128.8H[64,16] = TMPZ3[144,16];\n\tRd_VPR128.8H[80,16] = TMPZ3[176,16];\n\tRd_VPR128.8H[96,16] = TMPZ3[208,16];\n\tRd_VPR128.8H[112,16] = TMPZ3[240,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x5f00c000/mask=xff00f400\n# CONSTRUCT x5f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * 16:1 >>:4 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2\n# AUNIT --inst x5f40c000/mask=xffc0f400 --status pass --comment \"nointsat\"\n# Scalar variant when size=01 suf=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM\n\n:sqdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1100 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\tlocal tmp4:4 = tmp1 * tmp3;\n\tlocal tmp5:4 = tmp4 * 2:4;\n\tlocal tmp6:4 = tmp5 >> 16:1;\n\tRd_FPR16 = tmp6:2;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x5f00c000/mask=xff00f400\n# CONSTRUCT x5f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:1 >>:8 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2\n# AUNIT --inst x5f80c000/mask=xffc0f400 --status pass --comment \"nointsat\"\n# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex\n\n:sqdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1100 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\tlocal tmp4:8 = tmp1 * tmp3;\n\tlocal tmp5:8 = tmp4 * 2:8;\n\tlocal tmp6:8 = tmp5 >> 32:1;\n\tRd_FPR32 = tmp6:4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x5e20b400/mask=xff20fc00\n# CONSTRUCT x5e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2\n# AUNIT --inst x5e60b400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqdmulh(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x5e20b400/mask=xff20fc00\n# CONSTRUCT x5ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2\n# AUNIT --inst x5ea0b400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqdmulh(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00\n# CONSTRUCT x0ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4\n# AUNIT --inst x0ea0b400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00\n# CONSTRUCT x0e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2\n# AUNIT --inst x0e60b400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00\n# CONSTRUCT x4ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4\n# AUNIT --inst x4ea0b400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00\n# CONSTRUCT x4e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2\n# AUNIT --inst x4e60b400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400\n# CONSTRUCT x0f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4\n# AUNIT --inst x0f80b000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix Rd_VPR128.2D = TMPQ2 * 2:8 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] * 2:8;\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] * 2:8;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400\n# CONSTRUCT x4f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4\n# AUNIT --inst x4f80b000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix Rd_VPR128.2D = TMPQ3 * 2:8 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ3[0,64] * 2:8;\n\tRd_VPR128.2D[64,64] = TMPQ3[64,64] * 2:8;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400\n# CONSTRUCT x0f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2\n# AUNIT --inst x0f40b000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix Rd_VPR128.4S = TMPQ2 * 2:4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] * 2:4;\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] * 2:4;\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] * 2:4;\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] * 2:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400\n# CONSTRUCT x4f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2\n# AUNIT --inst x4f40b000/mask=xffc0f400 --status pass --comment \"ext nointsat\"\n\n:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = sext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix Rd_VPR128.4S = TMPQ3 * 2:4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ3[0,32] * 2:4;\n\tRd_VPR128.4S[32,32] = TMPQ3[32,32] * 2:4;\n\tRd_VPR128.4S[64,32] = TMPQ3[64,32] * 2:4;\n\tRd_VPR128.4S[96,32] = TMPQ3[96,32] * 2:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x5f00b000/mask=xff00f400\n# CONSTRUCT x5f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2\n# AUNIT --inst x5f40b000/mask=xffc0f400 --status pass --comment \"nointsat\"\n# Scalar variant when size=01 Va=FPR32 Vb=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM\n\n:sqdmull Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1011 & b_10=0 & Rd_FPR32 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\tlocal tmp4:4 = tmp1 * tmp3;\n\tRd_FPR32 = tmp4 * 2:4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x5f00b000/mask=xff00f400\n# CONSTRUCT x5f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2\n# AUNIT --inst x5f80b000/mask=xffc0f400 --status pass --comment \"nointsat\"\n# Scalar variant when size=10 Va=FPR64 Vb=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex\n\n:sqdmull Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1011 & b_10=0 & Rd_FPR64 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\tlocal tmp4:8 = tmp1 * tmp3;\n\tRd_FPR64 = tmp4 * 2:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00\n# CONSTRUCT x4ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4\n# AUNIT --inst x4ea0d000/mask=xffe0fc00 --status pass --comment \"ext nointsat\"\n\n:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xd & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix Rd_VPR128.2D = TMPQ5 * 2:8 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ5[0,64] * 2:8;\n\tRd_VPR128.2D[64,64] = TMPQ5[64,64] * 2:8;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00\n# CONSTRUCT x4e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2\n# AUNIT --inst x4e60d000/mask=xffe0fc00 --status pass --comment \"ext nointsat\"\n\n:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xd & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix Rd_VPR128.4S = TMPQ5 * 2:4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ5[0,32] * 2:4;\n\tRd_VPR128.4S[32,32] = TMPQ5[32,32] * 2:4;\n\tRd_VPR128.4S[64,32] = TMPQ5[64,32] * 2:4;\n\tRd_VPR128.4S[96,32] = TMPQ5[96,32] * 2:4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00\n# CONSTRUCT x0ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4\n# AUNIT --inst x0ea0d000/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xd & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqdmull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00\n# CONSTRUCT x0e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@2\n# AUNIT --inst x0e60d000/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xd & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqdmull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x5e20d000/mask=xff20fc00\n# CONSTRUCT x5e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2\n# AUNIT --inst x5e60d000/mask=xffe0fc00 --status pass --comment \"nointsat\"\n# Scalar variant when size=01 Va=FPR32 Vb=FPR16\n\n:sqdmull Rd_FPR32, Rn_FPR16, Rm_FPR16\nis b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b110100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\tlocal tmp2:4 = sext(Rm_FPR16);\n\tlocal tmp3:4 = tmp1 * tmp2;\n\tRd_FPR32 = tmp3 * 2:4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x5e20d000/mask=xff20fc00\n# CONSTRUCT x5ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2\n# AUNIT --inst x5ea0d000/mask=xffe0fc00 --status pass --comment \"nointsat\"\n# Scalar variant when size=10 Va=FPR64 Vb=FPR32\n\n:sqdmull Rd_FPR64, Rn_FPR32, Rm_FPR32\nis b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b110100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\tlocal tmp2:8 = sext(Rm_FPR32);\n\tlocal tmp3:8 = tmp1 * tmp2;\n\tRd_FPR64 = tmp3 * 2:8;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00\n# CONSTRUCT x7e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =2comp\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1\n# AUNIT --inst x7e207800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size=00 Q=1 aa=1 suf=FPR8\n\n:sqneg Rd_FPR8, Rn_FPR8\nis b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd\n{\n\tRd_FPR8 = - Rn_FPR8;\n\tzext_zb(Zd); # zero upper 31 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00\n# CONSTRUCT x7e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =2comp\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1\n# AUNIT --inst x7e607800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size=01 Q=1 aa=1 suf=FPR16\n\n:sqneg Rd_FPR16, Rn_FPR16\nis b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = - Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00\n# CONSTRUCT x7ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =2comp\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1\n# AUNIT --inst x7ea07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size=10 Q=1 aa=1 suf=FPR32\n\n:sqneg Rd_FPR32, Rn_FPR32\nis b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = - Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00\n# CONSTRUCT x7ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =2comp\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1\n# AUNIT --inst x7ee07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Scalar variant when size=11 Q=1 aa=1 suf=FPR64\n\n:sqneg Rd_FPR64, Rn_FPR64\nis b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = - Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x2e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1\n# AUNIT --inst x2e207800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when when size = 00 , Q = 0 aa=0 esize=1 suf=VPR64.8B\n\n:sqneg Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\t# simd unary Rd_VPR64.8B = -(Rn_VPR64.8B) on lane size 1\n\tRd_VPR64.8B[0,8] = -(Rn_VPR64.8B[0,8]);\n\tRd_VPR64.8B[8,8] = -(Rn_VPR64.8B[8,8]);\n\tRd_VPR64.8B[16,8] = -(Rn_VPR64.8B[16,8]);\n\tRd_VPR64.8B[24,8] = -(Rn_VPR64.8B[24,8]);\n\tRd_VPR64.8B[32,8] = -(Rn_VPR64.8B[32,8]);\n\tRd_VPR64.8B[40,8] = -(Rn_VPR64.8B[40,8]);\n\tRd_VPR64.8B[48,8] = -(Rn_VPR64.8B[48,8]);\n\tRd_VPR64.8B[56,8] = -(Rn_VPR64.8B[56,8]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x6e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1\n# AUNIT --inst x6e207800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when when size = 00 , Q = 1 aa=0 esize=1 suf=VPR128.16B\n\n:sqneg Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\t# simd unary Rd_VPR128.16B = -(Rn_VPR128.16B) on lane size 1\n\tRd_VPR128.16B[0,8] = -(Rn_VPR128.16B[0,8]);\n\tRd_VPR128.16B[8,8] = -(Rn_VPR128.16B[8,8]);\n\tRd_VPR128.16B[16,8] = -(Rn_VPR128.16B[16,8]);\n\tRd_VPR128.16B[24,8] = -(Rn_VPR128.16B[24,8]);\n\tRd_VPR128.16B[32,8] = -(Rn_VPR128.16B[32,8]);\n\tRd_VPR128.16B[40,8] = -(Rn_VPR128.16B[40,8]);\n\tRd_VPR128.16B[48,8] = -(Rn_VPR128.16B[48,8]);\n\tRd_VPR128.16B[56,8] = -(Rn_VPR128.16B[56,8]);\n\tRd_VPR128.16B[64,8] = -(Rn_VPR128.16B[64,8]);\n\tRd_VPR128.16B[72,8] = -(Rn_VPR128.16B[72,8]);\n\tRd_VPR128.16B[80,8] = -(Rn_VPR128.16B[80,8]);\n\tRd_VPR128.16B[88,8] = -(Rn_VPR128.16B[88,8]);\n\tRd_VPR128.16B[96,8] = -(Rn_VPR128.16B[96,8]);\n\tRd_VPR128.16B[104,8] = -(Rn_VPR128.16B[104,8]);\n\tRd_VPR128.16B[112,8] = -(Rn_VPR128.16B[112,8]);\n\tRd_VPR128.16B[120,8] = -(Rn_VPR128.16B[120,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x2e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2\n# AUNIT --inst x2e607800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when when size = 01 , Q = 0 aa=0 esize=2 suf=VPR64.4H\n\n:sqneg Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd unary Rd_VPR64.4H = -(Rn_VPR64.4H) on lane size 2\n\tRd_VPR64.4H[0,16] = -(Rn_VPR64.4H[0,16]);\n\tRd_VPR64.4H[16,16] = -(Rn_VPR64.4H[16,16]);\n\tRd_VPR64.4H[32,16] = -(Rn_VPR64.4H[32,16]);\n\tRd_VPR64.4H[48,16] = -(Rn_VPR64.4H[48,16]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x6e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2\n# AUNIT --inst x6e607800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when when size = 01 , Q = 1 aa=0 esize=2 suf=VPR128.8H\n\n:sqneg Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd unary Rd_VPR128.8H = -(Rn_VPR128.8H) on lane size 2\n\tRd_VPR128.8H[0,16] = -(Rn_VPR128.8H[0,16]);\n\tRd_VPR128.8H[16,16] = -(Rn_VPR128.8H[16,16]);\n\tRd_VPR128.8H[32,16] = -(Rn_VPR128.8H[32,16]);\n\tRd_VPR128.8H[48,16] = -(Rn_VPR128.8H[48,16]);\n\tRd_VPR128.8H[64,16] = -(Rn_VPR128.8H[64,16]);\n\tRd_VPR128.8H[80,16] = -(Rn_VPR128.8H[80,16]);\n\tRd_VPR128.8H[96,16] = -(Rn_VPR128.8H[96,16]);\n\tRd_VPR128.8H[112,16] = -(Rn_VPR128.8H[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x2ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4\n# AUNIT --inst x2ea07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when when size = 10 , Q = 0 aa=0 esize=4 suf=VPR64.2S\n\n:sqneg Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd unary Rd_VPR64.2S = -(Rn_VPR64.2S) on lane size 4\n\tRd_VPR64.2S[0,32] = -(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = -(Rn_VPR64.2S[32,32]);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x6ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4\n# AUNIT --inst x6ea07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when when size = 10 , Q = 1 aa=0 esize=4 suf=VPR128.4S\n\n:sqneg Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd unary Rd_VPR128.4S = -(Rn_VPR128.4S) on lane size 4\n\tRd_VPR128.4S[0,32] = -(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = -(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = -(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = -(Rn_VPR128.4S[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00\n# CONSTRUCT x6ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =$2comp@8\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@8\n# AUNIT --inst x6ee07800/mask=xfffffc00 --status pass --comment \"nointsat\"\n# Vector variant when when size = 11 , Q = 1 aa=0 esize=8 suf=VPR128.2D\n\n:sqneg Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd unary Rd_VPR128.2D = -(Rn_VPR128.2D) on lane size 8\n\tRd_VPR128.2D[0,64] = -(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = -(Rn_VPR128.2D[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.277 SQRDMLAH (by element) page C7-1598 line 92254 KEEPWITH\n# Integer saturating instruction (not implemented)\n\nsqrdml_subop: \"ah\" is b_24=0 & b_11=0 { export 0:1; }\nsqrdml_subop: \"ah\" is b_24=1 & b_13=0 { export 0:1; }\nsqrdml_subop: \"sh\" is b_24=0 & b_11=1 { export 1:1; }\nsqrdml_subop: \"sh\" is b_24=1 & b_13=1 { export 1:1; }\n\nsqrdml_esize: \"h\" is b_2223=0b01 { export 16:1; }\nsqrdml_esize: \"s\" is b_2223=0b10 { export 32:1; }\n\nsqrdml_elements: \"4h\" is b_2223=0b01 & b_30=0 { export 4:1; }\nsqrdml_elements: \"8h\" is b_2223=0b01 & b_30=1 { export 8:1; }\nsqrdml_elements: \"2s\" is b_2223=0b10 & b_30=0 { export 2:1; }\nsqrdml_elements: \"4s\" is b_2223=0b10 & b_30=1 { export 4:1; }\n\nsqrdml_index: val is b_2223=0b01 & b_21 & b_20 & b_11 [ val = b_11 * 4 + b_21 * 2 + b_20; ] { export * [const]:1 val; }\nsqrdml_index: val is b_2223=0b10 & b_21 & b_11 [ val = b_11 * 2 + b_21; ] { export * [const]:1 val; }\n\n# We could be more specific about the size of the register, which\n# depends on the variant and Q (b_30). For now, I've just made them\n# all 128 bits.\n\nsqrdml_vd: Rd_FPR16 is b_28=1 & b_2223=0b01 & Rd_FPR16 & Rd_VPR128 { export Rd_VPR128; }\nsqrdml_vd: Rd_FPR32 is b_28=1 & b_2223=0b10 & Rd_FPR32 & Rd_VPR128 { export Rd_VPR128; }\nsqrdml_vd: vRd_VPR128^\".\"^sqrdml_elements is b_28=0 & vRd_VPR128 & Rd_VPR128 & sqrdml_elements { export Rd_VPR128; }\n\nsqrdml_vn: Rn_FPR16 is b_28=1 & b_2223=0b01 & Rn_FPR16 & Rn_VPR128 { export Rn_VPR128; }\nsqrdml_vn: Rn_FPR32 is b_28=1 & b_2223=0b10 & Rn_FPR32 & Rn_VPR128 { export Rn_VPR128; }\nsqrdml_vn: vRn_VPR128^\".\"^sqrdml_elements is b_28=0 & vRn_VPR128 & Rn_VPR128 & sqrdml_elements { export Rn_VPR128; }\n\n# Decode Vm (in some cases) depending on size\n\n# cases 34.1, 36.1\nsqrdml_vm: Rm_FPR16 is b_28=1 & b_24=0 & b_2223=0b01 & Rm_FPR16 & Rm_VPR128 { export Rm_VPR128; }\nsqrdml_vm: Rm_FPR32 is b_28=1 & b_24=0 & b_2223=0b10 & Rm_FPR32 & Rm_VPR128 { export Rm_VPR128; }\n\n# cases 34.2, 36.2\nsqrdml_vm: vRm_VPR128^\".\"^sqrdml_elements is b_28=0 & b_24=0 & vRm_VPR128 & sqrdml_elements & Rm_VPR128 { export Rm_VPR128; }\n\nsqrdml_vmlo: vRm_VPR128Lo is b_2223=0b01 & vRm_VPR128Lo & Rm_VPR128Lo { export Rm_VPR128Lo; }\nsqrdml_vmlo: vRm_VPR128 is b_2223=0b10 & vRm_VPR128 & Rm_VPR128 { export Rm_VPR128; }\n\n# cases 33, 35\nsqrdml_vm: sqrdml_vmlo^\".\"^sqrdml_esize[sqrdml_index] is b_24=1 & sqrdml_vmlo & sqrdml_esize & sqrdml_index { export sqrdml_vmlo; }\n\n# SQRDML(Vd, Vn, Vm, esize, elements, subop[, index])\n#\n# performs the SQRDML operation\n#\n# Vd[e] = SignedSatQ(Vd[e]<>:4 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2\n# AUNIT --inst x5f40d000/mask=xffc0f400 --status fail --comment \"nointround nointsat\"\n# Scalar variant when size=01 suf=FPR16 elem elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM\n\n:sqrdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM\nis b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1101 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd\n{\n\tlocal tmp1:4 = sext(Rn_FPR16);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = sext(tmp2);\n\tlocal tmp4:4 = tmp1 * tmp3;\n\tlocal tmp5:4 = tmp4 * 2:4;\n\tlocal tmp6:4 = tmp5 >> 16:4;\n\tRd_FPR16 = tmp6:2;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.297 SQRDMULH (by element) page C7-2685 line 156680 MATCH x5f00d000/mask=xff00f400\n# CONSTRUCT x5f80d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:8 >>:8 =\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2\n# AUNIT --inst x5f80d000/mask=xffc0f400 --status fail --comment \"nointround nointsat\"\n# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex\n\n:sqrdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex\nis b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1101 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:8 = sext(Rn_FPR32);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = sext(tmp2);\n\tlocal tmp4:8 = tmp1 * tmp3;\n\tlocal tmp5:8 = tmp4 * 2:8;\n\tlocal tmp6:8 = tmp5 >> 32:8;\n\tRd_FPR32 = tmp6:4;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x7e20b400/mask=xff20fc00\n# CONSTRUCT x7e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2\n# AUNIT --inst x7e60b400/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqrdmulh(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x7e20b400/mask=xff20fc00\n# CONSTRUCT x7ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2\n# AUNIT --inst x7ea0b400/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqrdmulh(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00\n# CONSTRUCT x2ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4\n# AUNIT --inst x2ea0b400/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqrdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00\n# CONSTRUCT x2e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2\n# AUNIT --inst x2e60b400/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqrdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00\n# CONSTRUCT x6ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4\n# AUNIT --inst x6ea0b400/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqrdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00\n# CONSTRUCT x6e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2\n# AUNIT --inst x6e60b400/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqrdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00\n# CONSTRUCT x5e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2\n# AUNIT --inst x5e205c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sqrshl(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00\n# CONSTRUCT x5ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2\n# AUNIT --inst x5ee05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_sqrshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00\n# CONSTRUCT x5e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2\n# AUNIT --inst x5e605c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqrshl(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00\n# CONSTRUCT x5ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2\n# AUNIT --inst x5ea05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqrshl(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x4e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1\n# AUNIT --inst x4e205c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x4ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@8\n# AUNIT --inst x4ee05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x0ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4\n# AUNIT --inst x0ea05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x0e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2\n# AUNIT --inst x0e605c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x4ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4\n# AUNIT --inst x4ea05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x0e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1\n# AUNIT --inst x0e205c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00\n# CONSTRUCT x4e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2\n# AUNIT --inst x4e605c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00\n# CONSTRUCT x4f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2\n# AUNIT --inst x4f089c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqrshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00\n# CONSTRUCT x0f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@8\n# AUNIT --inst x0f209c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqrshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00\n# CONSTRUCT x0f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@4\n# AUNIT --inst x0f109c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqrshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00\n# CONSTRUCT x4f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@8\n# AUNIT --inst x4f209c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqrshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00\n# CONSTRUCT x0f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2\n# AUNIT --inst x0f089c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqrshrn2(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00\n# CONSTRUCT x4f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@4\n# AUNIT --inst x4f109c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqrshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00\n# CONSTRUCT x5f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3\n# AUNIT --inst x5f089c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:sqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8\nis b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_sqrshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00\n# CONSTRUCT x5f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3\n# AUNIT --inst x5f109c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:sqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16\nis b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_sqrshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);\n}\n\n# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00\n# CONSTRUCT x5f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3\n# AUNIT --inst x5f209c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:sqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32\nis b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_sqrshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00\n# CONSTRUCT x6f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@2\n# AUNIT --inst x6f088c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqrshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00\n# CONSTRUCT x2f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@8\n# AUNIT --inst x2f208c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqrshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00\n# CONSTRUCT x2f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@4\n# AUNIT --inst x2f108c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqrshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00\n# CONSTRUCT x6f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@8\n# AUNIT --inst x6f208c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqrshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00\n# CONSTRUCT x2f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@2\n# AUNIT --inst x2f088c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqrshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00\n# CONSTRUCT x6f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@4\n# AUNIT --inst x6f108c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:sqrshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqrshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00\n# CONSTRUCT x7f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3\n# AUNIT --inst x7f088c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:sqrshrun Rd_FPR8, Rn_FPR16, Imm_shr_imm8\nis b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100011 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_sqrshrun(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00\n# CONSTRUCT x7f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3\n# AUNIT --inst x7f108c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:sqrshrun Rd_FPR16, Rn_FPR32, Imm_shr_imm16\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100011 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_sqrshrun(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);\n}\n\n# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00\n# CONSTRUCT x7f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3\n# AUNIT --inst x7f208c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:sqrshrun Rd_FPR32, Rn_FPR64, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100011 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_sqrshrun(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x4f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1\n# AUNIT --inst x4f087400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x4f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@8\n# AUNIT --inst x4f407400/mask=xffc0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x0f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4\n# AUNIT --inst x0f207400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x0f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2\n# AUNIT --inst x0f107400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x4f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4\n# AUNIT --inst x4f207400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x0f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1\n# AUNIT --inst x0f087400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00\n# CONSTRUCT x4f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2\n# AUNIT --inst x4f107400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00\n# CONSTRUCT x5f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2\n# AUNIT --inst x5f087400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:sqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8\nis b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_sqshl(Rn_FPR8, Imm_shr_imm8:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00\n# CONSTRUCT x5f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2\n# AUNIT --inst x5f107400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:sqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16\nis b_2331=0b010111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_sqshl(Rn_FPR16, Imm_shr_imm16:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00\n# CONSTRUCT x5f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2\n# AUNIT --inst x5f207400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:sqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_2331=0b010111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_sqshl(Rn_FPR32, Imm_shr_imm32:1);\n}\n\n# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00\n# CONSTRUCT x5f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2\n# AUNIT --inst x5f407400/mask=xffc0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1\n\n:sqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b010111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tRd_FPR64 = NEON_sqshl(Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00\n# CONSTRUCT x5e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2\n# AUNIT --inst x5e204c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sqshl(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00\n# CONSTRUCT x5ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2\n# AUNIT --inst x5ee04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_sqshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00\n# CONSTRUCT x5e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2\n# AUNIT --inst x5e604c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqshl(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00\n# CONSTRUCT x5ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2\n# AUNIT --inst x5ea04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqshl(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x4e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1\n# AUNIT --inst x4e204c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x4ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@8\n# AUNIT --inst x4ee04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x0ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4\n# AUNIT --inst x0ea04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x0e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2\n# AUNIT --inst x0e604c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x4ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4\n# AUNIT --inst x4ea04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x0e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1\n# AUNIT --inst x0e204c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00\n# CONSTRUCT x4e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2\n# AUNIT --inst x4e604c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x6f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1\n# AUNIT --inst x6f086400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqshlu(Rn_VPR128.16B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x6f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@8\n# AUNIT --inst x6f406400/mask=xffc0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xc & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqshlu(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x2f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4\n# AUNIT --inst x2f206400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqshlu(Rn_VPR64.2S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x2f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2\n# AUNIT --inst x2f106400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqshlu(Rn_VPR64.4H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x6f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4\n# AUNIT --inst x6f206400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqshlu(Rn_VPR128.4S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x2f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1\n# AUNIT --inst x2f086400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqshlu(Rn_VPR64.8B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00\n# CONSTRUCT x6f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2\n# AUNIT --inst x6f106400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshlu Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqshlu(Rn_VPR128.8H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00\n# CONSTRUCT x7f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2\n# AUNIT --inst x7f086400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:sqshlu Rd_FPR8, Rn_FPR8, Imm_shr_imm8\nis b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011001 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_sqshlu(Rn_FPR8, Imm_shr_imm8:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00\n# CONSTRUCT x7f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2\n# AUNIT --inst x7f106400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:sqshlu Rd_FPR16, Rn_FPR16, Imm_shr_imm16\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011001 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_sqshlu(Rn_FPR16, Imm_shr_imm16:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00\n# CONSTRUCT x7f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2\n# AUNIT --inst x7f206400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:sqshlu Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011001 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_sqshlu(Rn_FPR32, Imm_shr_imm32:1);\n}\n\n# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00\n# CONSTRUCT x7f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2\n# AUNIT --inst x7f406400/mask=xffc0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1\n\n:sqshlu Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b011111110 & b_22=1 & b_1015=0b011001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tRd_FPR64 = NEON_sqshlu(Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x4f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@2\n# AUNIT --inst x4f089400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x0f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@8\n# AUNIT --inst x0f209400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x0f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@4\n# AUNIT --inst x0f109400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x4f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@8\n# AUNIT --inst x4f209400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x0f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@2\n# AUNIT --inst x0f089400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00\n# CONSTRUCT x4f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@4\n# AUNIT --inst x4f109400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00\n# CONSTRUCT x5f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3\n# AUNIT --inst x5f089400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:sqshrn Rd_FPR8, Rd_FPR16, Imm_shr_imm8\nis b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_sqshrn(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00\n# CONSTRUCT x5f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3\n# AUNIT --inst x5f109400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:sqshrn Rd_FPR16, Rd_FPR32, Imm_shr_imm16\nis b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_sqshrn(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1);\n}\n\n# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00\n# CONSTRUCT x5f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3\n# AUNIT --inst x5f209400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:sqshrn Rd_FPR32, Rd_FPR64, Imm_shr_imm32\nis b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_sqshrn(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# CONSTRUCT x6f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@2\n# AUNIT --inst x6f088400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# CONSTRUCT x2f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@8\n# AUNIT --inst x2f208400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# CONSTRUCT x2f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@4\n# AUNIT --inst x2f108400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# CONSTRUCT x6f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@8\n# AUNIT --inst x6f208400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# CONSTRUCT x2f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@2\n# AUNIT --inst x2f088400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00\n# CONSTRUCT x6f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@4\n# AUNIT --inst x6f108400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00\n# CONSTRUCT x7f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3\n# AUNIT --inst x7f088400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:sqshrun Rd_FPR8, Rd_FPR16, Imm_shr_imm8\nis b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100001 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_sqshrun(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00\n# CONSTRUCT x7f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3\n# AUNIT --inst x7f108400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:sqshrun Rd_FPR16, Rd_FPR32, Imm_shr_imm16\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100001 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_sqshrun(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1);\n}\n\n# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00\n# CONSTRUCT x7f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3\n# AUNIT --inst x7f208400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:sqshrun Rd_FPR32, Rd_FPR64, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100001 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_sqshrun(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00\n# CONSTRUCT x5e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2\n# AUNIT --inst x5e202c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sqsub(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00\n# CONSTRUCT x5ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2\n# AUNIT --inst x5ee02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_sqsub(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00\n# CONSTRUCT x5e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2\n# AUNIT --inst x5e602c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqsub(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00\n# CONSTRUCT x5ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2\n# AUNIT --inst x5ea02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqsub(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x4e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1\n# AUNIT --inst x4e202c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x4ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@8\n# AUNIT --inst x4ee02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x0ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4\n# AUNIT --inst x0ea02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x0e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2\n# AUNIT --inst x0e602c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x4ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4\n# AUNIT --inst x4ea02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x0e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1\n# AUNIT --inst x0e202c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00\n# CONSTRUCT x4e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2\n# AUNIT --inst x4e602c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:sqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00\n# CONSTRUCT x5e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2\n# AUNIT --inst x5e214800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn Rd_FPR8, Rn_FPR16\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR16 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_sqxtn(Rd_FPR8, Rn_FPR16);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00\n# CONSTRUCT x5e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2\n# AUNIT --inst x5e614800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn Rd_FPR16, Rn_FPR32\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR32 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_sqxtn(Rd_FPR16, Rn_FPR32);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00\n# CONSTRUCT x5ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2\n# AUNIT --inst x5ea14800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn Rd_FPR32, Rn_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR64 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_sqxtn(Rd_FPR32, Rn_FPR64);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00\n# CONSTRUCT x4e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@2\n# AUNIT --inst x4e214800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn2 Rd_VPR128.16B, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00\n# CONSTRUCT x4e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@4\n# AUNIT --inst x4e614800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn2 Rd_VPR128.8H, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00\n# CONSTRUCT x4ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@8\n# AUNIT --inst x4ea14800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn2 Rd_VPR128.4S, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00\n# CONSTRUCT x0ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@8\n# AUNIT --inst x0ea14800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn Rd_VPR64.2S, Rn_VPR128.2D\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00\n# CONSTRUCT x0e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@4\n# AUNIT --inst x0e614800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn Rd_VPR64.4H, Rn_VPR128.4S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00\n# CONSTRUCT x0e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@2\n# AUNIT --inst x0e214800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n\n:sqxtn Rd_VPR64.8B, Rn_VPR128.8H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00\n# CONSTRUCT x7e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2\n# AUNIT --inst x7e212800/mask=xfffffc00 --status noqemu --comment \"nointsat\"\n# Scalar variant when size=00 Q=1 bb=1 Ta=FPR16 Tb=FPR8\n\n:sqxtun Rd_FPR8, Rn_FPR16\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_FPR8 & Rn_FPR16 & Zd\n{\n\tRd_FPR8 = NEON_sqxtun(Rd_FPR8, Rn_FPR16);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00\n# CONSTRUCT x7e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2\n# AUNIT --inst x7e612800/mask=xfffffc00 --status noqemu --comment \"nointsat\"\n# Scalar variant when size=01 Q=1 bb=1 Ta=FPR32 Tb=FPR16\n\n:sqxtun Rd_FPR16, Rn_FPR32\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_FPR16 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = NEON_sqxtun(Rd_FPR16, Rn_FPR32);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00\n# CONSTRUCT x7ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2\n# AUNIT --inst x7ea12800/mask=xfffffc00 --status noqemu --comment \"nointsat\"\n# Scalar variant when size=10 Q=1 bb=1 Ta=FPR64 Tb=FPR32\n\n:sqxtun Rd_FPR32, Rn_FPR64\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_FPR32 & Rn_FPR64 & Zd\n{\n\tRd_FPR32 = NEON_sqxtun(Rd_FPR32, Rn_FPR64);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00\n# CONSTRUCT x2e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@2\n# AUNIT --inst x2e212800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=00 Q=0 bb=0 Ta=VPR128.8H Tb=VPR64.8B esize=2\n\n:sqxtun Rd_VPR64.8B, Rn_VPR128.8H\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd\n{\n\tRd_VPR64.8B = NEON_sqxtun(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00\n# CONSTRUCT x6e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@2\n# AUNIT --inst x6e212800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=00 Q=1 bb=0 Ta=VPR128.8H Tb=VPR128.16B esize=2\n\n:sqxtun2 Rd_VPR128.16B, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.16B = NEON_sqxtun2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00\n# CONSTRUCT x2e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@4\n# AUNIT --inst x2e612800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=01 Q=0 bb=0 Ta=VPR128.4S Tb=VPR64.4H esize=4\n\n:sqxtun Rd_VPR64.4H, Rn_VPR128.4S\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd\n{\n\tRd_VPR64.4H = NEON_sqxtun(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00\n# CONSTRUCT x6e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@4\n# AUNIT --inst x6e612800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=01 Q=1 bb=0 Ta=VPR128.4S Tb=VPR128.8H esize=4\n\n:sqxtun2 Rd_VPR128.8H, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.8H = NEON_sqxtun2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00\n# CONSTRUCT x2ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@8\n# AUNIT --inst x2ea12800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=10 Q=0 bb=0 Ta=VPR128.2D Tb=VPR64.2S esize=8\n\n:sqxtun Rd_VPR64.2S, Rn_VPR128.2D\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd\n{\n\tRd_VPR64.2S = NEON_sqxtun(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00\n# CONSTRUCT x6ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@8\n# AUNIT --inst x6ea12800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=10 Q=1 bb=0 Ta=VPR128.2D Tb=VPR128.4S esize=8\n\n:sqxtun2 Rd_VPR128.4S, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd\n{\n\tRd_VPR128.4S = NEON_sqxtun2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00\n# CONSTRUCT x4e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1\n# AUNIT --inst x4e201400/mask=xffe0fc00 --status nopcodeop\n\n:srhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRn_VPR128.16B = NEON_srhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00\n# CONSTRUCT x0ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4\n# AUNIT --inst x0ea01400/mask=xffe0fc00 --status nopcodeop\n\n:srhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRn_VPR64.2S = NEON_srhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00\n# CONSTRUCT x0e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2\n# AUNIT --inst x0e601400/mask=xffe0fc00 --status nopcodeop\n\n:srhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRn_VPR64.4H = NEON_srhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00\n# CONSTRUCT x4ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4\n# AUNIT --inst x4ea01400/mask=xffe0fc00 --status nopcodeop\n\n:srhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRn_VPR128.4S = NEON_srhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00\n# CONSTRUCT x0e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1\n# AUNIT --inst x0e201400/mask=xffe0fc00 --status nopcodeop\n\n:srhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRn_VPR64.8B = NEON_srhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00\n# CONSTRUCT x4e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2\n# AUNIT --inst x4e601400/mask=xffe0fc00 --status nopcodeop\n\n:srhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRn_VPR128.8H = NEON_srhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x6f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1\n# AUNIT --inst x6f084400/mask=xfff8fc00 --status nopcodeop\n\n:sri Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sri(Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8:4, 1:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x6f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@8\n# AUNIT --inst x6f404400/mask=xffc0fc00 --status nopcodeop\n\n:sri Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sri(Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64:4, 8:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x2f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4\n# AUNIT --inst x2f204400/mask=xffe0fc00 --status nopcodeop\n\n:sri Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sri(Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x2f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2\n# AUNIT --inst x2f104400/mask=xfff0fc00 --status nopcodeop\n\n:sri Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sri(Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16:4, 2:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x6f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4\n# AUNIT --inst x6f204400/mask=xffe0fc00 --status nopcodeop\n\n:sri Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sri(Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x2f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1\n# AUNIT --inst x2f084400/mask=xfff8fc00 --status nopcodeop\n\n:sri Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sri(Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8:4, 1:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00\n# CONSTRUCT x6f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2\n# AUNIT --inst x6f104400/mask=xfff0fc00 --status nopcodeop\n\n:sri Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sri(Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16:4, 2:1);\n}\n\n# C7.2.311 SRI page C7-2722 line 158861 MATCH x7f004400/mask=xff80fc00\n# CONSTRUCT x7f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sri/3\n# AUNIT --inst x7f404400/mask=xffc0fc00 --status nopcodeop\n\n:sri Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b011111110 & b_22=1 & b_1015=0b010001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tRd_FPR64 = NEON_sri(Rd_FPR64, Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x5e205400/mask=xff20fc00\n# CONSTRUCT x5ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2\n# AUNIT --inst x5ee05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_srshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x4e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1\n# AUNIT --inst x4e205400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_srshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x4ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@8\n# AUNIT --inst x4ee05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_srshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x0ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4\n# AUNIT --inst x0ea05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_srshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x0e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2\n# AUNIT --inst x0e605400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_srshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x4ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4\n# AUNIT --inst x4ea05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_srshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x0e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1\n# AUNIT --inst x0e205400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_srshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00\n# CONSTRUCT x4e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2\n# AUNIT --inst x4e605400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_srshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x4f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1\n# AUNIT --inst x4f082400/mask=xfff8fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_srshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x4f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@8\n# AUNIT --inst x4f402400/mask=xffc0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_srshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x0f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4\n# AUNIT --inst x0f202400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_srshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x0f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2\n# AUNIT --inst x0f102400/mask=xfff0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_srshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x4f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4\n# AUNIT --inst x4f202400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_srshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x0f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1\n# AUNIT --inst x0f082400/mask=xfff8fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_srshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00\n# CONSTRUCT x4f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2\n# AUNIT --inst x4f102400/mask=xfff0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_srshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1);\n}\n\n# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x5f002400/mask=xff80fc00\n# CONSTRUCT x5f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2\n# AUNIT --inst x5f402400/mask=xffc0fc00 --status nopcodeop --comment \"nointround\"\n\n:srshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b010111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tRd_FPR64 = NEON_srshr(Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x4f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1\n# AUNIT --inst x4f083400/mask=xfff8fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x4f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@8\n# AUNIT --inst x4f403400/mask=xffc0fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\t# simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x0f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4\n# AUNIT --inst x0f203400/mask=xffe0fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S s>> Imm_shr_imm32:4 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] s>> Imm_shr_imm32:4;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] s>> Imm_shr_imm32:4;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x0f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2\n# AUNIT --inst x0f103400/mask=xfff0fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x4f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4\n# AUNIT --inst x4f203400/mask=xffe0fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S s>> Imm_shr_imm32:4 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> Imm_shr_imm32:4;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> Imm_shr_imm32:4;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> Imm_shr_imm32:4;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> Imm_shr_imm32:4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x0f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1\n# AUNIT --inst x0f083400/mask=xfff8fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00\n# CONSTRUCT x4f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2\n# AUNIT --inst x4f103400/mask=xfff0fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x5f003400/mask=xff80fc00\n# CONSTRUCT x5f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3\n# AUNIT --inst x5f403400/mask=xffc0fc00 --status fail --comment \"nointround\"\n\n:srsra Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b010111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tlocal tmp2:8 = Rn_FPR64 s>> tmp1;\n\tRd_FPR64 = Rd_FPR64 + tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x5e204400/mask=xff20fc00\n# CONSTRUCT x5ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2\n# AUNIT --inst x5ee04400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_sshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x4e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1\n# AUNIT --inst x4e204400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_sshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x4ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@8\n# AUNIT --inst x4ee04400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_sshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x0ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4\n# AUNIT --inst x0ea04400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_sshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x0e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2\n# AUNIT --inst x0e604400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_sshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x4ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4\n# AUNIT --inst x4ea04400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_sshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x0e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1\n# AUNIT --inst x0e204400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_sshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00\n# CONSTRUCT x4e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2\n# AUNIT --inst x4e604400/mask=xffe0fc00 --status nopcodeop\n\n:sshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_sshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x4f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3 =var:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@1\n# AUNIT --inst x4f08a400/mask=xfff8fc00 --status pass --comment \"ext\"\n\n:sshll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tlocal tmp3:2 = Imm_uimm3;\n\t# simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3;\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3;\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3;\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3;\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3;\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3;\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3;\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x0f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 =var:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@4\n# AUNIT --inst x0f20a400/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:sshll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\tlocal tmp2:8 = Imm_uimm5;\n\t# simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x0f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 =var:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@2\n# AUNIT --inst x0f10a400/mask=xfff0fc00 --status pass --comment \"ext\"\n\n:sshll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\tlocal tmp2:4 = Imm_uimm4;\n\t# simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2;\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2;\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2;\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x4f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 =var:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@4\n# AUNIT --inst x4f20a400/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:sshll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tlocal tmp3:8 = Imm_uimm5;\n\t# simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x0f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 =var:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@1\n# AUNIT --inst x0f08a400/mask=xfff8fc00 --status pass --comment \"ext\"\n\n:sshll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\tlocal tmp2:2 = Imm_uimm3;\n\t# simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2;\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2;\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2;\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2;\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2;\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2;\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2;\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# CONSTRUCT x4f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 =var:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@2\n# AUNIT --inst x4f10a400/mask=xfff0fc00 --status pass --comment \"ext\"\n\n:sshll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tlocal tmp3:4 = Imm_uimm4;\n\t# simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3;\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3;\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3;\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x5f000400/mask=xff80fc00\n# CONSTRUCT x5f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2\n# AUNIT --inst x5f400400/mask=xffc0fc00 --status nopcodeop\n\n:sshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_sshr(Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x4f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1\n# AUNIT --inst x4f080400/mask=xfff8fc00 --status pass\n\n:sshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x4f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 =$s>>@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@8\n# AUNIT --inst x4f400400/mask=xffc0fc00 --status pass\n\n:sshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D s>> tmp1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x0f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4\n# AUNIT --inst x0f200400/mask=xffe0fc00 --status pass\n\n:sshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S s>> tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] s>> tmp1;\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] s>> tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x0f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2\n# AUNIT --inst x0f100400/mask=xfff0fc00 --status pass\n\n:sshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x4f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4\n# AUNIT --inst x4f200400/mask=xffe0fc00 --status pass\n\n:sshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S s>> tmp1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] s>> tmp1;\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] s>> tmp1;\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] s>> tmp1;\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] s>> tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x0f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1\n# AUNIT --inst x0f080400/mask=xfff8fc00 --status pass\n\n:sshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00\n# CONSTRUCT x4f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2\n# AUNIT --inst x4f100400/mask=xfff0fc00 --status pass\n\n:sshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x4f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1\n# AUNIT --inst x4f081400/mask=xfff8fc00 --status pass\n\n:ssra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x4f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@8\n# AUNIT --inst x4f401400/mask=xffc0fc00 --status pass\n\n:ssra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\t# simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x0f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4\n# AUNIT --inst x0f201400/mask=xffe0fc00 --status pass\n\n:ssra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix TMPD1 = Rn_VPR64.2S s>> tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] s>> tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] s>> tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x0f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2\n# AUNIT --inst x0f101400/mask=xfff0fc00 --status pass\n\n:ssra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x4f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4\n# AUNIT --inst x4f201400/mask=xffe0fc00 --status pass\n\n:ssra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix TMPQ1 = Rn_VPR128.4S s>> tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x0f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1\n# AUNIT --inst x0f081400/mask=xfff8fc00 --status pass\n\n:ssra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00\n# CONSTRUCT x4f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2\n# AUNIT --inst x4f101400/mask=xfff0fc00 --status pass\n\n:ssra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.318 SSRA page C7-2741 line 159921 MATCH x5f001400/mask=xff80fc00\n# CONSTRUCT x5f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3\n# AUNIT --inst x5f401400/mask=xffc0fc00 --status pass\n\n:ssra Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b010111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tlocal tmp2:8 = Rn_FPR64 s>> tmp1;\n\tRd_FPR64 = Rd_FPR64 + tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00\n# CONSTRUCT x4ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@4\n# AUNIT --inst x4ea02000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = sext(TMPD3[0,32]);\n\tTMPQ4[64,64] = sext(TMPD3[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00\n# CONSTRUCT x4e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@2\n# AUNIT --inst x4e602000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = sext(TMPD3[0,16]);\n\tTMPQ4[32,32] = sext(TMPD3[16,16]);\n\tTMPQ4[64,32] = sext(TMPD3[32,16]);\n\tTMPQ4[96,32] = sext(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00\n# CONSTRUCT x4e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@1\n# AUNIT --inst x4e202000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = sext(TMPD3[0,8]);\n\tTMPQ4[16,16] = sext(TMPD3[8,8]);\n\tTMPQ4[32,16] = sext(TMPD3[16,8]);\n\tTMPQ4[48,16] = sext(TMPD3[24,8]);\n\tTMPQ4[64,16] = sext(TMPD3[32,8]);\n\tTMPQ4[80,16] = sext(TMPD3[40,8]);\n\tTMPQ4[96,16] = sext(TMPD3[48,8]);\n\tTMPQ4[112,16] = sext(TMPD3[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00\n# CONSTRUCT x0ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@4\n# AUNIT --inst x0ea02000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00\n# CONSTRUCT x0e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@2\n# AUNIT --inst x0e602000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00\n# CONSTRUCT x0e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@1\n# AUNIT --inst x0e202000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00\n# CONSTRUCT x4ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@4\n# AUNIT --inst x4ea03000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Rm_VPR128 & Zd\n{\n\tTMPD1 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = sext(TMPD1[0,32]);\n\tTMPQ2[64,64] = sext(TMPD1[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00\n# CONSTRUCT x4e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@2\n# AUNIT --inst x4e603000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = sext(TMPD1[0,16]);\n\tTMPQ2[32,32] = sext(TMPD1[16,16]);\n\tTMPQ2[64,32] = sext(TMPD1[32,16]);\n\tTMPQ2[96,32] = sext(TMPD1[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00\n# CONSTRUCT x4e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@1\n# AUNIT --inst x4e203000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = sext(TMPD1[0,8]);\n\tTMPQ2[16,16] = sext(TMPD1[8,8]);\n\tTMPQ2[32,16] = sext(TMPD1[16,8]);\n\tTMPQ2[48,16] = sext(TMPD1[24,8]);\n\tTMPQ2[64,16] = sext(TMPD1[32,8]);\n\tTMPQ2[80,16] = sext(TMPD1[40,8]);\n\tTMPQ2[96,16] = sext(TMPD1[48,8]);\n\tTMPQ2[112,16] = sext(TMPD1[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00\n# CONSTRUCT x0ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@4\n# AUNIT --inst x0ea03000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00\n# CONSTRUCT x0e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@2\n# AUNIT --inst x0e603000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00\n# CONSTRUCT x0e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@1\n# AUNIT --inst x0e203000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ssubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000\n# CONSTRUCT x2c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop\n# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2\n# AUNIT --inst x2c000000/mask=xffc00000 --status nomem\n\n:stnp Rt_FPR32, Rt2_FPR32, addrPairIndexed\nis b_3031=0b00 & b_2229=0b10110000 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32\n{\n\t* addrPairIndexed = Rt_FPR32;\n\tlocal tmp1:8 = addrPairIndexed + 4;\n\t* tmp1 = Rt2_FPR32;\n}\n\n# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000\n# CONSTRUCT x6c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop\n# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2\n# AUNIT --inst x6c000000/mask=xffc00000 --status nomem\n\n:stnp Rt_FPR64, Rt2_FPR64, addrPairIndexed\nis b_3031=0b01 & b_2229=0b10110000 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64\n{\n\t* addrPairIndexed = Rt_FPR64;\n\tlocal tmp1:8 = addrPairIndexed + 8;\n\t* tmp1 = Rt2_FPR64;\n}\n\n# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000\n# CONSTRUCT xac000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop\n# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2\n# AUNIT --inst xac000000/mask=xffc00000 --status nomem\n\n:stnp Rt_FPR128, Rt2_FPR128, addrPairIndexed\nis b_3031=0b10 & b_2229=0b10110000 & Rt2_FPR64 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128\n{\n\t* addrPairIndexed = Rt_FPR128;\n\tlocal tmp1:8 = addrPairIndexed + 16;\n\t* tmp1 = Rt2_FPR128;\n}\n\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000\n# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000\n# CONSTRUCT xac000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop\n# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2\n# AUNIT --inst xac000000/mask=xfe400000 --status nomem\n# 128-bit variant (post-index, pre-index, and signed offset)\n\n:stp Rt_FPR128, Rt2_FPR128, addrPairIndexed\nis b_3031=0b10 & b_2529=0b10110 & b_22=0 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128\n{\n\t* addrPairIndexed = Rt_FPR128;\n\tlocal tmp1:8 = addrPairIndexed + 16;\n\t* tmp1 = Rt2_FPR128;\n}\n\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000\n# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000\n# CONSTRUCT x2c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop\n# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2\n# AUNIT --inst x2c000000/mask=xfe400000 --status nomem\n# 32-bit variant (post-index, pre-index, and signed offset)\n\n:stp Rt_FPR32, Rt2_FPR32, addrPairIndexed\nis b_3031=0b00 & b_2529=0b10110 & b_22=0 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32\n{\n\t* addrPairIndexed = Rt_FPR32;\n\tlocal tmp1:8 = addrPairIndexed + 4;\n\t* tmp1 = Rt2_FPR32;\n}\n\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000\n# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000\n# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000\n# CONSTRUCT x6c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop\n# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2\n# AUNIT --inst x6c000000/mask=xfe400000 --status nomem\n# 64-bit variant (post-index, pre-index, and signed offset)\n\n:stp Rt_FPR64, Rt2_FPR64, addrPairIndexed\nis b_3031=0b01 & b_2529=0b10110 & b_22=0 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64\n{\n\t* addrPairIndexed = Rt_FPR64;\n\tlocal tmp1:8 = addrPairIndexed + 8;\n\t* tmp1 = Rt2_FPR64;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00\n# CONSTRUCT x3c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst x3c000400/mask=xffe00400 --status nomem\n# Post- and Pre-offset 8-bit variant when size == 00 && opc == 00 F=FPR8\n\n:str Rt_FPR8, addrIndexed\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt\n{\n\t* addrIndexed = Rt_FPR8;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00\n# CONSTRUCT x7c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst x7c000400/mask=xffe00400 --status nomem\n# Post- and Pre-offset 16-bit variant when size == 01 && opc == 00 F=FPR16\n\n:str Rt_FPR16, addrIndexed\nis b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt\n{\n\t* addrIndexed = Rt_FPR16;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00\n# CONSTRUCT xbc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst xbc000400/mask=xffe00400 --status nomem\n# Post- and Pre-offset 32-bit variant when size == 10 && opc == 00 F=FPR32\n\n:str Rt_FPR32, addrIndexed\nis b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt\n{\n\t* addrIndexed = Rt_FPR32;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00\n# CONSTRUCT xfc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst xfc000400/mask=xffe00400 --status nomem\n# Post- and Pre-offset 64-bit variant when size == 11 && opc == 00 F=FPR64\n\n:str Rt_FPR64, addrIndexed\nis b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt\n{\n\t* addrIndexed = Rt_FPR64;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00\n# CONSTRUCT x3c800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst x3c800400/mask=xffe00400 --status nomem\n# Post- and Pre-offset 128-bit variant when size == 00 && opc == 10 F=FPR128\n\n:str Rt_FPR128, addrIndexed\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt\n{\n\t* addrIndexed = Rt_FPR128;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000\n# CONSTRUCT x3d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst x3d000000/mask=xffc00000 --status nomem\n# Unsigned offset 8-bit variant when size == 00 && opc == 00 F=FPR8\n\n:str Rt_FPR8, addrUIMM\nis b_3031=0b00 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR8 & addrUIMM & Zt\n{\n\t* addrUIMM = Rt_FPR8;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000\n# CONSTRUCT x7d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst x7d000000/mask=xffc00000 --status nomem\n# Unsigned offset 16-bit variant when size == 01 && opc == 00 F=FPR16\n\n:str Rt_FPR16, addrUIMM\nis b_3031=0b01 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR16 & addrUIMM & Zt\n{\n\t* addrUIMM = Rt_FPR16;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000\n# CONSTRUCT xbd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst xbd000000/mask=xffc00000 --status nomem\n# Unsigned offset 32-bit variant when size == 10 && opc == 00 F=FPR32\n\n:str Rt_FPR32, addrUIMM\nis b_3031=0b10 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR32 & addrUIMM & Zt\n{\n\t* addrUIMM = Rt_FPR32;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000\n# CONSTRUCT xfd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst xfd000000/mask=xffc00000 --status nomem\n# Unsigned offset 64-bit variant when size == 11 && opc == 00 F=FPR64\n\n:str Rt_FPR64, addrUIMM\nis b_3031=0b11 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR64 & addrUIMM & Zt\n{\n\t* addrUIMM = Rt_FPR64;\n}\n\n# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000\n# CONSTRUCT x3d800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2\n# AUNIT --inst x3d800000/mask=xffc00000 --status nomem\n# Unsigned offset 128-bit variant when size == 00 && opc == 10 F=FPR128\n\n:str Rt_FPR128, addrUIMM\nis b_3031=0b00 & b_2429=0b111101 & b_2223=0b10 & Rt_FPR128 & addrUIMM & Zt\n{\n\t* addrUIMM = Rt_FPR128;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x3c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x3c200800/mask=xffe02c00 --status nomem\n# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32\n\n:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR8;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x3c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x3c202800/mask=xffe02c00 --status nomem\n# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64\n\n:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR8;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x3c206800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x3c206800/mask=xffe0ec00 --status nomem\n# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64\n\n:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR8;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x7c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x7c200800/mask=xffe02c00 --status nomem\n# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=0 F=FPR16 G=GPR32\n\n:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR16;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x7c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x7c202800/mask=xffe02c00 --status nomem\n# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=1 F=FPR16 G=GPR64\n\n:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR16;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT xbc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst xbc200800/mask=xffe02c00 --status nomem\n# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=0 F=FPR32 G=GPR32\n\n:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR32;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT xbc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst xbc202800/mask=xffe02c00 --status nomem\n# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=1 F=FPR32 G=GPR64\n\n:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR32;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT xfc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst xfc200800/mask=xffe02c00 --status nomem\n# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=0 F=FPR64 G=GPR32\n\n:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR64;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT xfc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst xfc202800/mask=xffe02c00 --status nomem\n# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=1 F=FPR64 G=GPR64\n\n:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR64;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x3ca00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x3ca00800/mask=xffe02c00 --status nomem\n# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=0 F=FPR128 G=GPR32\n\n:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR128;\n}\n\n# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00\n# CONSTRUCT x3ca02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop\n# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4\n# AUNIT --inst x3ca02800/mask=xffe02c00 --status nomem\n# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=1 F=FPR128 G=GPR64\n\n:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]\nis b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd\n{\n\tlocal tmp1:8 = extend_spec << extend_amount;\n\tlocal tmp2:8 = Rn_GPR64xsp + tmp1;\n\t* tmp2 = Rt_FPR128;\n}\n\n# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00\n# CONSTRUCT x3c800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2\n# AUNIT --inst x3c800000/mask=xffe00c00 --status nomem\n\n:stur Rt_FPR128, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128\n{\n\t* addrIndexed = Rt_FPR128;\n}\n\n# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00\n# CONSTRUCT x7c000000/mask=xffc00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2\n# AUNIT --inst x7c000000/mask=xffc00c00 --status nomem\n\n:stur Rt_FPR16, addrIndexed\nis size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_1011=0 & addrIndexed & Rt_FPR16\n{\n\t* addrIndexed = Rt_FPR16;\n}\n\n# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00\n# CONSTRUCT xbc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2\n# AUNIT --inst xbc000000/mask=xffe00c00 --status nomem\n\n:stur Rt_FPR32, addrIndexed\nis size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32\n{\n\t* addrIndexed = Rt_FPR32;\n}\n\n# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00\n# CONSTRUCT xfc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2\n# AUNIT --inst xfc000000/mask=xffe00c00 --status nomem\n\n:stur Rt_FPR64, addrIndexed\nis size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64\n{\n\t* addrIndexed = Rt_FPR64;\n}\n\n# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00\n# CONSTRUCT x3c000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =store pop\n# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2\n# AUNIT --inst x3c000000/mask=xffe00c00 --status nomem\n\n:stur Rt_FPR8, addrIndexed\nis size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8\n{\n\t* addrIndexed = Rt_FPR8;\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x7e208400/mask=xff20fc00\n# CONSTRUCT x7ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =-\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2\n# AUNIT --inst x7ee08400/mask=xffe0fc00 --status pass\n\n:sub Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = Rn_FPR64 - Rm_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x6e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1\n# AUNIT --inst x6e208400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B - Rm_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] - Rm_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] - Rm_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] - Rm_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] - Rm_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] - Rm_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] - Rm_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] - Rm_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] - Rm_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] - Rm_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] - Rm_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] - Rm_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] - Rm_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] - Rm_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] - Rm_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] - Rm_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] - Rm_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x6ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8\n# AUNIT --inst x6ee08400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x2ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4\n# AUNIT --inst x2ea08400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x2e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2\n# AUNIT --inst x2e608400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H - Rm_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] - Rm_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] - Rm_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] - Rm_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] - Rm_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x6ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4\n# AUNIT --inst x6ea08400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x2e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1\n# AUNIT --inst x2e208400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B - Rm_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] - Rm_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] - Rm_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] - Rm_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] - Rm_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] - Rm_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] - Rm_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] - Rm_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] - Rm_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00\n# CONSTRUCT x6e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2\n# AUNIT --inst x6e608400/mask=xffe0fc00 --status pass\n\n:sub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00\n# CONSTRUCT x4e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2\n# AUNIT --inst x4e206000/mask=xffe0fc00 --status pass\n\n:subhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1\n\tRd_VPR128.16B[64,8] = TMPQ1[8,8];\n\tRd_VPR128.16B[72,8] = TMPQ1[24,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[40,8];\n\tRd_VPR128.16B[88,8] = TMPQ1[56,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[72,8];\n\tRd_VPR128.16B[104,8] = TMPQ1[88,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[104,8];\n\tRd_VPR128.16B[120,8] = TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00\n# CONSTRUCT x4ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-2@3-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8\n# AUNIT --inst x4ea06000/mask=xffe0fc00 --status pass\n\n:subhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4\n\tRd_VPR128.4S[64,32] = TMPQ1[32,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00\n# CONSTRUCT x4e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-4@3-5@5-6@7-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn2/3@4\n# AUNIT --inst x4e606000/mask=xffe0fc00 --status pass\n\n:subhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2\n\tRd_VPR128.8H[64,16] = TMPQ1[16,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[48,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[80,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00\n# CONSTRUCT x0ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-0@3-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@8\n# AUNIT --inst x0ea06000/mask=xffe0fc00 --status pass\n\n:subhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];\n\t# simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4\n\tRd_VPR64.2S[0,32] = TMPQ1[32,32];\n\tRd_VPR64.2S[32,32] = TMPQ1[96,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00\n# CONSTRUCT x0e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-0@3-1@5-2@7-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@4\n# AUNIT --inst x0e606000/mask=xffe0fc00 --status pass\n\n:subhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];\n\t# simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2\n\tRd_VPR64.4H[0,16] = TMPQ1[16,16];\n\tRd_VPR64.4H[16,16] = TMPQ1[48,16];\n\tRd_VPR64.4H[32,16] = TMPQ1[80,16];\n\tRd_VPR64.4H[48,16] = TMPQ1[112,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00\n# CONSTRUCT x0e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@2\n# AUNIT --inst x0e206000/mask=xffe0fc00 --status pass\n\n:subhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];\n\t# simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1\n\tRd_VPR64.8B[0,8] = TMPQ1[8,8];\n\tRd_VPR64.8B[8,8] = TMPQ1[24,8];\n\tRd_VPR64.8B[16,8] = TMPQ1[40,8];\n\tRd_VPR64.8B[24,8] = TMPQ1[56,8];\n\tRd_VPR64.8B[32,8] = TMPQ1[72,8];\n\tRd_VPR64.8B[40,8] = TMPQ1[88,8];\n\tRd_VPR64.8B[48,8] = TMPQ1[104,8];\n\tRd_VPR64.8B[56,8] = TMPQ1[120,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00\n# CONSTRUCT x5e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=+\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2\n# AUNIT --inst x5e203800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Scalar variant when size=00 Q=1 bb=1 V=FPR8 s2=2\n\n:suqadd Rd_FPR8, Rn_FPR8\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd\n{\n\tRd_FPR8 = Rd_FPR8 + Rn_FPR8;\n\tzext_zb(Zd); # zero upper 31 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00\n# CONSTRUCT x5e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=+\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2\n# AUNIT --inst x5e603800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Scalar variant when size=01 Q=1 bb=1 V=FPR16 s2=4\n\n:suqadd Rd_FPR16, Rn_FPR16\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = Rd_FPR16 + Rn_FPR16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00\n# CONSTRUCT x5ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=+\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2\n# AUNIT --inst x5ea03800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Scalar variant when size=10 Q=1 bb=1 V=FPR32 s2=8\n\n:suqadd Rd_FPR32, Rn_FPR32\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = Rd_FPR32 + Rn_FPR32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00\n# CONSTRUCT x5ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=+\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2\n# AUNIT --inst x5ee03800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Scalar variant when size=11 Q=1 bb=1 V=FPR64 s2=16\n\n:suqadd Rd_FPR64, Rn_FPR64\nis b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = Rd_FPR64 + Rn_FPR64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x0e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1\n# AUNIT --inst x0e203800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=00 Q=0 bb=0 V=VPR64.8B e1=1 s2=16\n\n:suqadd Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B + Rn_VPR64.8B on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + Rn_VPR64.8B[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + Rn_VPR64.8B[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + Rn_VPR64.8B[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + Rn_VPR64.8B[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + Rn_VPR64.8B[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + Rn_VPR64.8B[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + Rn_VPR64.8B[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + Rn_VPR64.8B[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x4e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1\n# AUNIT --inst x4e203800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=00 Q=1 bb=0 V=VPR128.16B e1=1 s2=32\n\n:suqadd Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B + Rn_VPR128.16B on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + Rn_VPR128.16B[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + Rn_VPR128.16B[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + Rn_VPR128.16B[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + Rn_VPR128.16B[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + Rn_VPR128.16B[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + Rn_VPR128.16B[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + Rn_VPR128.16B[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + Rn_VPR128.16B[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + Rn_VPR128.16B[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + Rn_VPR128.16B[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + Rn_VPR128.16B[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + Rn_VPR128.16B[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + Rn_VPR128.16B[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + Rn_VPR128.16B[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + Rn_VPR128.16B[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + Rn_VPR128.16B[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x0e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2\n# AUNIT --inst x0e603800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=01 Q=0 bb=0 V=VPR64.4H e1=2 s2=16\n\n:suqadd Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + Rn_VPR64.4H on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + Rn_VPR64.4H[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + Rn_VPR64.4H[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + Rn_VPR64.4H[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + Rn_VPR64.4H[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x4e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2\n# AUNIT --inst x4e603800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=01 Q=1 bb=0 V=VPR128.8H e1=2 s2=32\n\n:suqadd Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + Rn_VPR128.8H on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + Rn_VPR128.8H[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + Rn_VPR128.8H[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + Rn_VPR128.8H[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + Rn_VPR128.8H[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + Rn_VPR128.8H[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + Rn_VPR128.8H[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + Rn_VPR128.8H[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + Rn_VPR128.8H[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x0ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4\n# AUNIT --inst x0ea03800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=10 Q=0 bb=0 V=VPR64.2S e1=4 s2=16\n\n:suqadd Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + Rn_VPR64.2S on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + Rn_VPR64.2S[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + Rn_VPR64.2S[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x4ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4\n# AUNIT --inst x4ea03800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=10 Q=1 bb=0 V=VPR128.4S e1=4 s2=32\n\n:suqadd Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + Rn_VPR128.4S on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + Rn_VPR128.4S[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + Rn_VPR128.4S[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + Rn_VPR128.4S[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + Rn_VPR128.4S[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00\n# CONSTRUCT x4ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@8\n# AUNIT --inst x4ee03800/mask=xfffffc00 --status fail --comment \"nointsat\"\n# Vector variant when size=11 Q=1 bb=0 V=VPR128.2D e1=8 s2=32\n\n:suqadd Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + Rn_VPR128.2D on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + Rn_VPR128.2D[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + Rn_VPR128.2D[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# CONSTRUCT x4f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$sext@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@1\n# AUNIT --inst x4f08a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:sxtl2 Rd_VPR128.8H, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2)\n\tRd_VPR128.8H[0,16] = sext(TMPD1[0,8]);\n\tRd_VPR128.8H[16,16] = sext(TMPD1[8,8]);\n\tRd_VPR128.8H[32,16] = sext(TMPD1[16,8]);\n\tRd_VPR128.8H[48,16] = sext(TMPD1[24,8]);\n\tRd_VPR128.8H[64,16] = sext(TMPD1[32,8]);\n\tRd_VPR128.8H[80,16] = sext(TMPD1[40,8]);\n\tRd_VPR128.8H[96,16] = sext(TMPD1[48,8]);\n\tRd_VPR128.8H[112,16] = sext(TMPD1[56,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# CONSTRUCT x0f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$sext@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@4\n# AUNIT --inst x0f20a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:sxtl Rd_VPR128.2D, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8)\n\tRd_VPR128.2D[0,64] = sext(TMPD1[0,32]);\n\tRd_VPR128.2D[64,64] = sext(TMPD1[32,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# CONSTRUCT x0f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$sext@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@2\n# AUNIT --inst x0f10a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:sxtl Rd_VPR128.4S, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4)\n\tRd_VPR128.4S[0,32] = sext(TMPD1[0,16]);\n\tRd_VPR128.4S[32,32] = sext(TMPD1[16,16]);\n\tRd_VPR128.4S[64,32] = sext(TMPD1[32,16]);\n\tRd_VPR128.4S[96,32] = sext(TMPD1[48,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# CONSTRUCT x4f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$sext@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@4\n# AUNIT --inst x4f20a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:sxtl2 Rd_VPR128.2D, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8)\n\tRd_VPR128.2D[0,64] = sext(TMPD1[0,32]);\n\tRd_VPR128.2D[64,64] = sext(TMPD1[32,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# CONSTRUCT x0f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$sext@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@1\n# AUNIT --inst x0f08a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:sxtl Rd_VPR128.8H, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Zd\n{\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2)\n\tRd_VPR128.8H[0,16] = sext(TMPD1[0,8]);\n\tRd_VPR128.8H[16,16] = sext(TMPD1[8,8]);\n\tRd_VPR128.8H[32,16] = sext(TMPD1[16,8]);\n\tRd_VPR128.8H[48,16] = sext(TMPD1[24,8]);\n\tRd_VPR128.8H[64,16] = sext(TMPD1[32,8]);\n\tRd_VPR128.8H[80,16] = sext(TMPD1[40,8]);\n\tRd_VPR128.8H[96,16] = sext(TMPD1[48,8]);\n\tRd_VPR128.8H[112,16] = sext(TMPD1[56,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00\n# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00\n# CONSTRUCT x4f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$sext@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@2\n# AUNIT --inst x4f10a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:sxtl2 Rd_VPR128.4S, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4)\n\tRd_VPR128.4S[0,32] = sext(TMPD1[0,16]);\n\tRd_VPR128.4S[32,32] = sext(TMPD1[16,16]);\n\tRd_VPR128.4S[64,32] = sext(TMPD1[32,16]);\n\tRd_VPR128.4S[96,32] = sext(TMPD1[48,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.322 TBL page C7-1717 line 99409 KEEPWITH\n\ntblx: \"tbl\" is b_12=0 { local tmp:16 = zext(0:8); export tmp; }\ntblx: \"tbx\" is b_12=1 & Rd_VPR128 { export Rd_VPR128; }\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x0e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1\n# AUNIT --inst x0e000000/mask=xffe0ec00 --status pass\n# Q == 0 && len == 00 8B, Single register table variant\n\n:^tblx Rd_VPR64.8B, \"{\"^Rn_VPR128.16B^\"}\", Rm_VPR64.8B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b00 & Rm_VPR64.8B & Rn_VPR128.16B & Rd_VPR64.8B & tblx & Zd\n{\n\tRd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR64.8B);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x4e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1\n# AUNIT --inst x4e000000/mask=xffe0ec00 --status pass\n# Q == 1 && len == 00 16B, Single register table variant\n\n:^tblx Rd_VPR128.16B, \"{\"^Rn_VPR128.16B^\"}\", Rm_VPR128.16B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b00 & Rm_VPR128.16B & Rn_VPR128.16B & Rd_VPR128.16B & tblx & Zd\n{\n\tRd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR128.16B);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x0e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4\n# AUNIT --inst x0e002000/mask=xffe0ec00 --status pass\n# Q == 0 && len == 01 8B, Two register table variant\n\n:^tblx Rd_VPR64.8B, \"{\"^Rn_VPR128.16B^\", \"^Rnn_VPR128.16B^\"}\", Rm_VPR64.8B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b01 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd\n{\n\tRd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR64.8B);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x4e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4\n# AUNIT --inst x4e002000/mask=xffe0ec00 --status pass\n# Q == 1 && len == 01 16B, Two register table variant\n\n:^tblx Rd_VPR128.16B, \"{\"^Rn_VPR128.16B^\", \"^Rnn_VPR128.16B^\"}\", Rm_VPR128.16B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b01 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd\n{\n\tRd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR128.16B);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x0e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5\n# AUNIT --inst x0e004000/mask=xffe0ec00 --status pass\n# Q == 0 && len == 10 8B, Three register table variant\n\n:^tblx Rd_VPR64.8B, \"{\"^Rn_VPR128.16B^\", \"^Rnn_VPR128.16B^\", \"^Rnnn_VPR128.16B^\"}\", Rm_VPR64.8B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b10 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd\n{\n\tRd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR64.8B);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x4e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5\n# AUNIT --inst x4e004000/mask=xffe0ec00 --status pass\n# Q == 1 && len == 10 16B, Three register table variant\n\n:^tblx Rd_VPR128.16B, \"{\"^Rn_VPR128.16B^\", \"^Rnn_VPR128.16B^\", \"^Rnnn_VPR128.16B^\"}\", Rm_VPR128.16B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b10 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd\n{\n\tRd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR128.16B);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x0e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6\n# AUNIT --inst x0e006000/mask=xffe0ec00 --status pass\n# Q == 0 && len == 11 8B, Four register table variant\n\n:^tblx Rd_VPR64.8B, \"{\"^Rn_VPR128.16B^\", \"^Rnn_VPR128.16B^\", \"^Rnnn_VPR128.16B^\", \"^Rnnnn_VPR128.16B^\"}\", Rm_VPR64.8B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b11 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd\n{\n\tRd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR64.8B);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00\n# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00\n# CONSTRUCT x4e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6\n# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6\n# AUNIT --inst x4e006000/mask=xffe0ec00 --status pass\n# Q == 1 && len == 11 16B, Four register table variant\n\n:^tblx Rd_VPR128.16B, \"{\"^Rn_VPR128.16B^\", \"^Rnn_VPR128.16B^\", \"^Rnnn_VPR128.16B^\", \"^Rnnnn_VPR128.16B^\"}\", Rm_VPR128.16B\nis b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b11 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd\n{\n\tRd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR128.16B);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x4e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14:1 swap &=$shuffle@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1\n# AUNIT --inst x4e002800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ2 = Rm_VPR128.16B;\n\tTMPQ1 = Rn_VPR128.16B;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14) lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[0,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[16,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[32,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[48,8];\n\tRd_VPR128.16B[64,8] = TMPQ1[64,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[80,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[96,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[112,8];\n\t# simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15) lane size 1\n\tRd_VPR128.16B[8,8] = TMPQ2[0,8];\n\tRd_VPR128.16B[24,8] = TMPQ2[16,8];\n\tRd_VPR128.16B[40,8] = TMPQ2[32,8];\n\tRd_VPR128.16B[56,8] = TMPQ2[48,8];\n\tRd_VPR128.16B[72,8] = TMPQ2[64,8];\n\tRd_VPR128.16B[88,8] = TMPQ2[80,8];\n\tRd_VPR128.16B[104,8] = TMPQ2[96,8];\n\tRd_VPR128.16B[120,8] = TMPQ2[112,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x4ec02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@8\n# AUNIT --inst x4ec02800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ2 = Rm_VPR128.2D;\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64];\n\t# simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8\n\tRd_VPR128.2D[64,64] = TMPQ2[0,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x0e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4\n# AUNIT --inst x0e802800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD2 = Rm_VPR64.2S;\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[0,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4\n\tRd_VPR64.2S[32,32] = TMPD2[0,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x0e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:2 swap &=$shuffle@0-1@2-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2\n# AUNIT --inst x0e402800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD2 = Rm_VPR64.4H;\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-2) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[0,16];\n\tRd_VPR64.4H[32,16] = TMPD1[32,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@2-3) lane size 2\n\tRd_VPR64.4H[16,16] = TMPD2[0,16];\n\tRd_VPR64.4H[48,16] = TMPD2[32,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x4e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:4 swap &=$shuffle@0-1@2-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4\n# AUNIT --inst x4e802800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ2 = Rm_VPR128.4S;\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-2) lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32];\n\t# simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@2-3) lane size 4\n\tRd_VPR128.4S[32,32] = TMPQ2[0,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[64,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x0e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:1 swap &=$shuffle@0-1@2-3@4-5@6-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1\n# AUNIT --inst x0e002800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD2 = Rm_VPR64.8B;\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-2@4-4@6-6) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[0,8];\n\tRd_VPR64.8B[16,8] = TMPD1[16,8];\n\tRd_VPR64.8B[32,8] = TMPD1[32,8];\n\tRd_VPR64.8B[48,8] = TMPD1[48,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@2-3@4-5@6-7) lane size 1\n\tRd_VPR64.8B[8,8] = TMPD2[0,8];\n\tRd_VPR64.8B[24,8] = TMPD2[16,8];\n\tRd_VPR64.8B[40,8] = TMPD2[32,8];\n\tRd_VPR64.8B[56,8] = TMPD2[48,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00\n# CONSTRUCT x4e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:2 swap &=$shuffle@0-1@2-3@4-5@6-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2\n# AUNIT --inst x4e402800/mask=xffe0fc00 --status pass\n\n:trn1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ2 = Rm_VPR128.8H;\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-2@4-4@6-6) lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16];\n\t# simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@2-3@4-5@6-7) lane size 2\n\tRd_VPR128.8H[16,16] = TMPQ2[0,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[32,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[64,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[96,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x4e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14:1 swap &=$shuffle@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1\n# AUNIT --inst x4e006800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ2 = Rm_VPR128.16B;\n\tTMPQ1 = Rn_VPR128.16B;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14) lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[120,8];\n\t# simd shuffle Rd_VPR128.16B = TMPQ2 (@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15) lane size 1\n\tRd_VPR128.16B[8,8] = TMPQ2[8,8];\n\tRd_VPR128.16B[24,8] = TMPQ2[24,8];\n\tRd_VPR128.16B[40,8] = TMPQ2[40,8];\n\tRd_VPR128.16B[56,8] = TMPQ2[56,8];\n\tRd_VPR128.16B[72,8] = TMPQ2[72,8];\n\tRd_VPR128.16B[88,8] = TMPQ2[88,8];\n\tRd_VPR128.16B[104,8] = TMPQ2[104,8];\n\tRd_VPR128.16B[120,8] = TMPQ2[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x4ec06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@8\n# AUNIT --inst x4ec06800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ2 = Rm_VPR128.2D;\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[64,64];\n\t# simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x0e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4\n# AUNIT --inst x0e806800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD2 = Rm_VPR64.2S;\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[32,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4\n\tRd_VPR64.2S[32,32] = TMPD2[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x0e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:2 swap &=$shuffle@1-1@3-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2\n# AUNIT --inst x0e406800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD2 = Rm_VPR64.4H;\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-2) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = TMPD1[48,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD2 (@1-1@3-3) lane size 2\n\tRd_VPR64.4H[16,16] = TMPD2[16,16];\n\tRd_VPR64.4H[48,16] = TMPD2[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x4e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:4 swap &=$shuffle@1-1@3-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4\n# AUNIT --inst x4e806800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ2 = Rm_VPR128.4S;\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-2) lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[96,32];\n\t# simd shuffle Rd_VPR128.4S = TMPQ2 (@1-1@3-3) lane size 4\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x0e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:1 swap &=$shuffle@1-1@3-3@5-5@7-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1\n# AUNIT --inst x0e006800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD2 = Rm_VPR64.8B;\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-2@5-4@7-6) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = TMPD1[56,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD2 (@1-1@3-3@5-5@7-7) lane size 1\n\tRd_VPR64.8B[8,8] = TMPD2[8,8];\n\tRd_VPR64.8B[24,8] = TMPD2[24,8];\n\tRd_VPR64.8B[40,8] = TMPD2[40,8];\n\tRd_VPR64.8B[56,8] = TMPD2[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00\n# CONSTRUCT x4e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:2 swap &=$shuffle@1-1@3-3@5-5@7-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2\n# AUNIT --inst x4e406800/mask=xffe0fc00 --status pass\n\n:trn2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ2 = Rm_VPR128.8H;\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-2@5-4@7-6) lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[112,16];\n\t# simd shuffle Rd_VPR128.8H = TMPQ2 (@1-1@3-3@5-5@7-7) lane size 2\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00\n# CONSTRUCT x6e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1\n# AUNIT --inst x6e207c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uaba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uaba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00\n# CONSTRUCT x2ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4\n# AUNIT --inst x2ea07c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uaba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uaba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00\n# CONSTRUCT x2e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2\n# AUNIT --inst x2e607c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uaba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uaba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00\n# CONSTRUCT x6ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4\n# AUNIT --inst x6ea07c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uaba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uaba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00\n# CONSTRUCT x2e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1\n# AUNIT --inst x2e207c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uaba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uaba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00\n# CONSTRUCT x6e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2\n# AUNIT --inst x6e607c00/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uaba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uaba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00\n# CONSTRUCT x6ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 $abs@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@4\n# AUNIT --inst x6ea05000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];\n\t# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8\n\tTMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]);\n\tTMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]);\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00\n# CONSTRUCT x6e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 $abs@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@2\n# AUNIT --inst x6e605000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];\n\t# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4\n\tTMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]);\n\tTMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]);\n\tTMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]);\n\tTMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00\n# CONSTRUCT x6e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 $abs@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@1\n# AUNIT --inst x6e205000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];\n\t# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2\n\tTMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]);\n\tTMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]);\n\tTMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]);\n\tTMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]);\n\tTMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]);\n\tTMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]);\n\tTMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]);\n\tTMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]);\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00\n# CONSTRUCT x2ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 $abs@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@4\n# AUNIT --inst x2ea05000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];\n\t# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8\n\tTMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]);\n\tTMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]);\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00\n# CONSTRUCT x2e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 $abs@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@2\n# AUNIT --inst x2e605000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];\n\t# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4\n\tTMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]);\n\tTMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]);\n\tTMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]);\n\tTMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]);\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00\n# CONSTRUCT x2e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 $abs@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@1\n# AUNIT --inst x2e205000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];\n\t# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2\n\tTMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]);\n\tTMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]);\n\tTMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]);\n\tTMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]);\n\tTMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]);\n\tTMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]);\n\tTMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]);\n\tTMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]);\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00\n# CONSTRUCT x6e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1\n# AUNIT --inst x6e207400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00\n# CONSTRUCT x2ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $less@4 &=$*@4 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4\n# AUNIT --inst x2ea07400/mask=xffe0fc00 --status pass --comment \"abd\"\n# This abd instruction is implemented correctly to document a correct\n# way to implement the unsigned absolute difference semantic.\n\n:uabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];\n\t# simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4\n\tTMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32];\n\tTMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32];\n\t# simd infix TMPD2 = TMPD2 * 2:4 on lane size 4\n\tTMPD2[0,32] = TMPD2[0,32] * 2:4;\n\tTMPD2[32,32] = TMPD2[32,32] * 2:4;\n\t# simd infix TMPD3 = Rn_VPR64.2S < Rm_VPR64.2S on lane size 4\n\tTMPD3[0,32] = zext(Rn_VPR64.2S[0,32] < Rm_VPR64.2S[0,32]);\n\tTMPD3[32,32] = zext(Rn_VPR64.2S[32,32] < Rm_VPR64.2S[32,32]);\n\t# simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4\n\tTMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32];\n\tTMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32];\n\t# simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32];\n\tRd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00\n# CONSTRUCT x2e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2\n# AUNIT --inst x2e607400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00\n# CONSTRUCT x6ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4\n# AUNIT --inst x6ea07400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00\n# CONSTRUCT x2e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1\n# AUNIT --inst x2e207400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00\n# CONSTRUCT x6e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2\n# AUNIT --inst x6e607400/mask=xffe0fc00 --status nopcodeop --comment \"abd\"\n\n:uabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00\n# CONSTRUCT x6ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 =$abs@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@4\n# AUNIT --inst x6ea07000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];\n\t# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8\n\tRd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]);\n\tRd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00\n# CONSTRUCT x6e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@2\n# AUNIT --inst x6e607000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];\n\t# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4\n\tRd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]);\n\tRd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]);\n\tRd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]);\n\tRd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00\n# CONSTRUCT x6e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@1\n# AUNIT --inst x6e207000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];\n\t# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2\n\tRd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]);\n\tRd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]);\n\tRd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]);\n\tRd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]);\n\tRd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]);\n\tRd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]);\n\tRd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]);\n\tRd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00\n# CONSTRUCT x2ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 =$abs@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@4\n# AUNIT --inst x2ea07000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];\n\t# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8\n\tRd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]);\n\tRd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00\n# CONSTRUCT x2e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 =$abs@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@2\n# AUNIT --inst x2e607000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];\n\t# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4\n\tRd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]);\n\tRd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]);\n\tRd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]);\n\tRd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00\n# CONSTRUCT x2e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 =$abs@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@1\n# AUNIT --inst x2e207000/mask=xffe0fc00 --status pass --comment \"ext abd\"\n\n:uabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];\n\t# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2\n\tRd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]);\n\tRd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]);\n\tRd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]);\n\tRd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]);\n\tRd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]);\n\tRd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]);\n\tRd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]);\n\tRd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00\n# CONSTRUCT x6e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1\n# AUNIT --inst x6e206800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uadalp Rd_VPR128.8H, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2)\n\tlocal tmp2 = Rn_VPR128.16B[0,8];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = Rn_VPR128.16B[8,8];\n\tlocal tmp5 = zext(tmp3);\n\tTMPQ1[0,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[16,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[24,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[16,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[32,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[40,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[32,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[48,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[56,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[48,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[64,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[72,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[64,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[80,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[88,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[80,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[96,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[104,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[96,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.16B[112,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.16B[120,8];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[112,16] = tmp4 + tmp5;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00\n# CONSTRUCT x2ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4\n# AUNIT --inst x2ea06800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uadalp Rd_VPR64.1D, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8)\n\tlocal tmp2 = Rn_VPR64.2S[0,32];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = Rn_VPR64.2S[32,32];\n\tlocal tmp5 = zext(tmp3);\n\tTMPD1 = tmp4 + tmp5;\n\t# simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8\n\tRd_VPR64.1D = Rd_VPR64.1D + TMPD1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00\n# CONSTRUCT x2e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2\n# AUNIT --inst x2e606800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uadalp Rd_VPR64.2S, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4)\n\tlocal tmp2 = Rn_VPR64.4H[0,16];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = Rn_VPR64.4H[16,16];\n\tlocal tmp5 = zext(tmp3);\n\tTMPD1[0,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.4H[32,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR64.4H[48,16];\n\ttmp5 = zext(tmp3);\n\tTMPD1[32,32] = tmp4 + tmp5;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00\n# CONSTRUCT x6ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4\n# AUNIT --inst x6ea06800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uadalp Rd_VPR128.2D, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8)\n\tlocal tmp2 = Rn_VPR128.4S[0,32];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = Rn_VPR128.4S[32,32];\n\tlocal tmp5 = zext(tmp3);\n\tTMPQ1[0,64] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.4S[64,32];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.4S[96,32];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[64,64] = tmp4 + tmp5;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00\n# CONSTRUCT x2e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1\n# AUNIT --inst x2e206800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uadalp Rd_VPR64.4H, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd\n{\n\tTMPD1 = 0;\n\t# sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2)\n\tlocal tmp2 = Rn_VPR64.8B[0,8];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = Rn_VPR64.8B[8,8];\n\tlocal tmp5 = zext(tmp3);\n\tTMPD1[0,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.8B[16,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR64.8B[24,8];\n\ttmp5 = zext(tmp3);\n\tTMPD1[16,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.8B[32,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR64.8B[40,8];\n\ttmp5 = zext(tmp3);\n\tTMPD1[32,16] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR64.8B[48,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR64.8B[56,8];\n\ttmp5 = zext(tmp3);\n\tTMPD1[48,16] = tmp4 + tmp5;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00\n# CONSTRUCT x6e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2\n# AUNIT --inst x6e606800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uadalp Rd_VPR128.4S, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPQ1 = 0;\n\t# sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4)\n\tlocal tmp2 = Rn_VPR128.8H[0,16];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = Rn_VPR128.8H[16,16];\n\tlocal tmp5 = zext(tmp3);\n\tTMPQ1[0,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.8H[32,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.8H[48,16];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[32,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.8H[64,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.8H[80,16];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[64,32] = tmp4 + tmp5;\n\ttmp2 = Rn_VPR128.8H[96,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = Rn_VPR128.8H[112,16];\n\ttmp5 = zext(tmp3);\n\tTMPQ1[96,32] = tmp4 + tmp5;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00\n# CONSTRUCT x6ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@4\n# AUNIT --inst x6ea00000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00\n# CONSTRUCT x6e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@2\n# AUNIT --inst x6e600000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00\n# CONSTRUCT x6e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@1\n# AUNIT --inst x6e200000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00\n# CONSTRUCT x2ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@4\n# AUNIT --inst x2ea00000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00\n# CONSTRUCT x2e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@2\n# AUNIT --inst x2e600000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00\n# CONSTRUCT x2e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@1\n# AUNIT --inst x2e200000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00\n# CONSTRUCT x2e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#u+@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1\n# AUNIT --inst x2e202800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when size = 00 , Q = 0 s=16 e1=1 e2=2 Ta=VPR64.4H Tb=VPR64.8B\n\n:uaddlp Rd_VPR64.4H, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd\n{\n\tTMPD1 = Rn_VPR64.8B;\n\t# sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2)\n\tlocal tmp2 = TMPD1[0,8];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = TMPD1[8,8];\n\tlocal tmp5 = zext(tmp3);\n\tRd_VPR64.4H[0,16] = tmp4 + tmp5;\n\ttmp2 = TMPD1[16,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPD1[24,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR64.4H[16,16] = tmp4 + tmp5;\n\ttmp2 = TMPD1[32,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPD1[40,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR64.4H[32,16] = tmp4 + tmp5;\n\ttmp2 = TMPD1[48,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPD1[56,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR64.4H[48,16] = tmp4 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00\n# CONSTRUCT x6e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#u+@1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1\n# AUNIT --inst x6e202800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when size = 00 , Q = 1 s=32 e1=1 e2=2 Ta=VPR128.8H Tb=VPR128.16B\n\n:uaddlp Rd_VPR128.8H, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd\n{\n\tTMPQ1 = Rn_VPR128.16B;\n\t# sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2)\n\tlocal tmp2 = TMPQ1[0,8];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = TMPQ1[8,8];\n\tlocal tmp5 = zext(tmp3);\n\tRd_VPR128.8H[0,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[16,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[24,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[16,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[32,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[40,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[32,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[48,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[56,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[48,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[64,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[72,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[64,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[80,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[88,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[80,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[96,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[104,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[96,16] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[112,8];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[120,8];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.8H[112,16] = tmp4 + tmp5;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00\n# CONSTRUCT x2e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#u+@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2\n# AUNIT --inst x2e602800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when size = 01 , Q = 0 s=16 e1=2 e2=4 Ta=VPR64.2S Tb=VPR64.4H\n\n:uaddlp Rd_VPR64.2S, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd\n{\n\tTMPD1 = Rn_VPR64.4H;\n\t# sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4)\n\tlocal tmp2 = TMPD1[0,16];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = TMPD1[16,16];\n\tlocal tmp5 = zext(tmp3);\n\tRd_VPR64.2S[0,32] = tmp4 + tmp5;\n\ttmp2 = TMPD1[32,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPD1[48,16];\n\ttmp5 = zext(tmp3);\n\tRd_VPR64.2S[32,32] = tmp4 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00\n# CONSTRUCT x6e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#u+@2\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2\n# AUNIT --inst x6e602800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when size = 01 , Q = 1 s=32 e1=2 e2=4 Ta=VPR128.4S Tb=VPR128.8H\n\n:uaddlp Rd_VPR128.4S, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd\n{\n\tTMPQ1 = Rn_VPR128.8H;\n\t# sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4)\n\tlocal tmp2 = TMPQ1[0,16];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = TMPQ1[16,16];\n\tlocal tmp5 = zext(tmp3);\n\tRd_VPR128.4S[0,32] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[32,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[48,16];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.4S[32,32] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[64,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[80,16];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.4S[64,32] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[96,16];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[112,16];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.4S[96,32] = tmp4 + tmp5;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00\n# CONSTRUCT x2ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#u+@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4\n# AUNIT --inst x2ea02800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when size = 10 , Q = 0 s=16 e1=4 e2=8 Ta=VPR64.1D Tb=VPR64.2S\n\n:uaddlp Rd_VPR64.1D, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd\n{\n\tTMPD1 = Rn_VPR64.2S;\n\t# sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8)\n\tlocal tmp2 = TMPD1[0,32];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = TMPD1[32,32];\n\tlocal tmp5 = zext(tmp3);\n\tRd_VPR64.1D = tmp4 + tmp5;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00\n# CONSTRUCT x6ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =#u+@4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4\n# AUNIT --inst x6ea02800/mask=xfffffc00 --status pass --comment \"ext\"\n# Vector variant when size = 10 , Q = 1 s=32 e1=4 e2=8 Ta=VPR128.2D Tb=VPR128.4S\n\n:uaddlp Rd_VPR128.2D, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd\n{\n\tTMPQ1 = Rn_VPR128.4S;\n\t# sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8)\n\tlocal tmp2 = TMPQ1[0,32];\n\tlocal tmp4 = zext(tmp2);\n\tlocal tmp3 = TMPQ1[32,32];\n\tlocal tmp5 = zext(tmp3);\n\tRd_VPR128.2D[0,64] = tmp4 + tmp5;\n\ttmp2 = TMPQ1[64,32];\n\ttmp4 = zext(tmp2);\n\ttmp3 = TMPQ1[96,32];\n\ttmp5 = zext(tmp3);\n\tRd_VPR128.2D[64,64] = tmp4 + tmp5;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00\n# CONSTRUCT x6eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@4\n# AUNIT --inst x6eb03800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:uaddlv Rd_FPR64, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_uaddlv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00\n# CONSTRUCT x6e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1\n# AUNIT --inst x6e303800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:uaddlv Rd_FPR16, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uaddlv(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00\n# CONSTRUCT x2e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1\n# AUNIT --inst x2e303800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:uaddlv Rd_FPR16, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uaddlv(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00\n# CONSTRUCT x2e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2\n# AUNIT --inst x2e703800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:uaddlv Rd_FPR32, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uaddlv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00\n# CONSTRUCT x6e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2\n# AUNIT --inst x6e703800/mask=xfffffc00 --status nopcodeop --comment \"ext\"\n\n:uaddlv Rd_FPR32, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uaddlv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00\n# CONSTRUCT x6ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@4\n# AUNIT --inst x6ea01000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00\n# CONSTRUCT x6e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@2\n# AUNIT --inst x6e601000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00\n# CONSTRUCT x6e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@1\n# AUNIT --inst x6e201000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00\n# CONSTRUCT x2ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@4\n# AUNIT --inst x2ea01000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00\n# CONSTRUCT x2e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@2\n# AUNIT --inst x2e601000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00\n# CONSTRUCT x2e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@1\n# AUNIT --inst x2e201000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:uaddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00\n# CONSTRUCT x7f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2\n# AUNIT --inst x7f40e400/mask=xffc0fc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_3031=1 & u=1 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_ucvtf(Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00\n# CONSTRUCT x7f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2\n# AUNIT --inst x7f20e400/mask=xffe0fc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_3031=1 & u=1 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_ucvtf(Rn_FPR32, Imm_shr_imm32:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00\n# CONSTRUCT x7f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2\n# AUNIT --inst x7f10e400/mask=xfff0fc00 --status noqemu --comment \"nofpround\"\n\n:ucvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16\nis b_3031=1 & u=1 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_ucvtf(Rn_FPR16, Imm_shr_imm16:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x6f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@8\n# AUNIT --inst x6f40e400/mask=xffc0fc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x2f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4\n# AUNIT --inst x2f20e400/mask=xffe0fc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x6f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4\n# AUNIT --inst x6f20e400/mask=xffe0fc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x2f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2\n# AUNIT --inst x2f10e400/mask=xfff0fc00 --status noqemu --comment \"nofpround\"\n\n:ucvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, Imm_shr_imm32:1, 2:1);\n}\n\n# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00\n# CONSTRUCT x6f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2\n# AUNIT --inst x6f10e400/mask=xfff0fc00 --status noqemu --comment \"nofpround\"\n\n:ucvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, Imm_shr_imm32:1, 2:1);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e21d800/mask=xffbffc00\n# CONSTRUCT x7e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x7e21d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_FPR32, Rn_FPR32\nis b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_ucvtf(Rn_FPR32);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e21d800/mask=xffbffc00\n# CONSTRUCT x7e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x7e61d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_FPR64, Rn_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_ucvtf(Rn_FPR64);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00\n# CONSTRUCT x2e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4\n# AUNIT --inst x2e21d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_VPR64.2S, Rn_VPR64.2S\nis sf=0 & q=0 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00\n# CONSTRUCT x6e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4\n# AUNIT --inst x6e21d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_VPR128.4S, Rn_VPR128.4S\nis sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00\n# CONSTRUCT x6e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@8\n# AUNIT --inst x6e61d800/mask=xfffffc00 --status nopcodeop --comment \"nofpround\"\n\n:ucvtf Rd_VPR128.2D, Rn_VPR128.2D\nis sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e79d800/mask=xfffffc00\n# CONSTRUCT x7e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x7e79d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Scalar half precision variant\n\n:ucvtf Rd_FPR16, Rn_FPR16\nis b_1031=0b0111111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_ucvtf(Rn_FPR16);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e79d800/mask=xbffffc00\n# CONSTRUCT x2e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2\n# AUNIT --inst x2e79d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=0 T=VPR64.4H\n\n:ucvtf Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_1029=0b10111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e79d800/mask=xbffffc00\n# CONSTRUCT x6e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2\n# AUNIT --inst x6e79d800/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n# Vector half precision variant when Q=1 T=VPR128.8H\n\n:ucvtf Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_1029=0b10111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000\n# CONSTRUCT x1ec38000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:8 int2float:2 FBits16 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2\n# AUNIT --inst x1ec38000/mask=xffff8000 --status noqemu --comment \"nofpround\"\n# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();\n\n:ucvtf Rd_FPR16, Rn_GPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:8 = zext(Rn_GPR32);\n\tlocal tmp2:2 = int2float(tmp1);\n\tRd_FPR16 = tmp2 f/ FBits16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000\n# CONSTRUCT x9ec30000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:9 int2float:2 FBits16 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2\n# AUNIT --inst x9ec30000/mask=xffff0000 --status noqemu --comment \"nofpround\"\n\n:ucvtf Rd_FPR16, Rn_GPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:9 = zext(Rn_GPR64);\n\tlocal tmp2:2 = int2float(tmp1);\n\tRd_FPR16 = tmp2 f/ FBits16;\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000\n# CONSTRUCT x1e438000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:8 int2float:8 FBits64 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2\n# AUNIT --inst x1e438000/mask=xffff8000 --status pass --comment \"nofpround\"\n# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();\n\n:ucvtf Rd_FPR64, Rn_GPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = zext(Rn_GPR32);\n\tlocal tmp2:8 = int2float(tmp1);\n\tRd_FPR64 = tmp2 f/ FBits64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000\n# CONSTRUCT x9e430000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:9 int2float:8 FBits64 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2\n# AUNIT --inst x9e430000/mask=xffff0000 --status fail --comment \"nofpround\"\n# The zext:9 naively force unsigned int before conversion\n\n:ucvtf Rd_FPR64, Rn_GPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:9 = zext(Rn_GPR64);\n\tlocal tmp2:8 = int2float(tmp1);\n\tRd_FPR64 = tmp2 f/ FBits64;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000\n# CONSTRUCT x1e038000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:8 int2float:4 FBits32 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2\n# AUNIT --inst x1e038000/mask=xffff8000 --status fail --comment \"nofpround\"\n# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();\n\n:ucvtf Rd_FPR32, Rn_GPR32, FBitsOp\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:8 = zext(Rn_GPR32);\n\tlocal tmp2:4 = int2float(tmp1);\n\tRd_FPR32 = tmp2 f/ FBits32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000\n# CONSTRUCT x9e030000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:9 int2float:4 FBits32 =f/\n# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2\n# AUNIT --inst x9e030000/mask=xffff0000 --status fail --comment \"nofpround\"\n\n:ucvtf Rd_FPR32, Rn_GPR64, FBitsOp\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:9 = zext(Rn_GPR64);\n\tlocal tmp2:4 = int2float(tmp1);\n\tRd_FPR32 = tmp2 f/ FBits32;\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00\n# CONSTRUCT x1ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:8 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x1ee30000/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n\n:ucvtf Rd_FPR16, Rn_GPR32\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:8 = zext(Rn_GPR32);\n\tRd_FPR16 = int2float(tmp1);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00\n# CONSTRUCT x9ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:9 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x9ee30000/mask=xfffffc00 --status noqemu --comment \"nofpround\"\n\n:ucvtf Rd_FPR16, Rn_GPR64\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd\n{\n\tlocal tmp1:9 = zext(Rn_GPR64);\n\tRd_FPR16 = int2float(tmp1);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00\n# CONSTRUCT x1e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:8 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x1e630000/mask=xfffffc00 --status pass --comment \"nofpround\"\n\n:ucvtf Rd_FPR64, Rn_GPR32\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:8 = zext(Rn_GPR32);\n\tRd_FPR64 = int2float(tmp1);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00\n# CONSTRUCT x9e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:9 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x9e630000/mask=xfffffc00 --status fail --comment \"nofpround\"\n\n:ucvtf Rd_FPR64, Rn_GPR64\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd\n{\n\tlocal tmp1:9 = zext(Rn_GPR64);\n\tRd_FPR64 = int2float(tmp1);\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00\n# CONSTRUCT x1e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:8 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x1e230000/mask=xfffffc00 --status fail --comment \"nofpround\"\n\n:ucvtf Rd_FPR32, Rn_GPR32\nis sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:8 = zext(Rn_GPR32);\n\tRd_FPR32 = int2float(tmp1);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00\n# CONSTRUCT x9e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 zext:9 =int2float\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1\n# AUNIT --inst x9e230000/mask=xfffffc00 --status fail --comment \"nofpround\"\n\n:ucvtf Rd_FPR32, Rn_GPR64\nis sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd\n{\n\tlocal tmp1:9 = zext(Rn_GPR64);\n\tRd_FPR32 = int2float(tmp1);\n\tzext_zs(Zd); # zero upper 28 bytes of Zd\n}\n\n# C7.2.356 UDOT (by element) page C7-2837 line 165760 MATCH x2f00e000/mask=xbf00f400\n# CONSTRUCT x2f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1\n# AUNIT --inst x2f80e000/mask=xffc0f400 --status noqemu\n# Vector variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B\n\n:udot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex\nis b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);\n\tRd_VPR64.2S = NEON_udot(Rn_VPR64.8B, tmp1, 1:1);\n}\n\n# C7.2.356 UDOT (by element) page C7-2837 line 165760 MATCH x2f00e000/mask=xbf00f400\n# CONSTRUCT x6f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1\n# AUNIT --inst x6f80e000/mask=xffc0f400 --status noqemu\n# Vector variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B\n\n:udot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex\nis b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd\n{\n\tlocal tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);\n\tRd_VPR128.4S = NEON_udot(Rn_VPR128.16B, tmp1, 1:1);\n}\n\n# C7.2.357 UDOT (vector) page C7-2839 line 165862 MATCH x2e009400/mask=xbf20fc00\n# CONSTRUCT x2e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1\n# AUNIT --inst x2e809400/mask=xffe0fc00 --status noqemu\n# Three registers of the same type variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B\n\n:udot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd\n{\n\tRd_VPR64.2S = NEON_udot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.357 UDOT (vector) page C7-2839 line 165862 MATCH x2e009400/mask=xbf20fc00\n# CONSTRUCT x6e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1\n# AUNIT --inst x6e809400/mask=xffe0fc00 --status noqemu\n# Three registers of the same type variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B\n\n:udot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd\n{\n\tRd_VPR128.4S = NEON_udot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00\n# CONSTRUCT x6e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1\n# AUNIT --inst x6e200400/mask=xffe0fc00 --status nopcodeop\n\n:uhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00\n# CONSTRUCT x2ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4\n# AUNIT --inst x2ea00400/mask=xffe0fc00 --status nopcodeop\n\n:uhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00\n# CONSTRUCT x2e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2\n# AUNIT --inst x2e600400/mask=xffe0fc00 --status nopcodeop\n\n:uhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00\n# CONSTRUCT x6ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4\n# AUNIT --inst x6ea00400/mask=xffe0fc00 --status nopcodeop\n\n:uhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00\n# CONSTRUCT x2e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1\n# AUNIT --inst x2e200400/mask=xffe0fc00 --status nopcodeop\n\n:uhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00\n# CONSTRUCT x6e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2\n# AUNIT --inst x6e600400/mask=xffe0fc00 --status nopcodeop\n\n:uhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00\n# CONSTRUCT x6e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1\n# AUNIT --inst x6e202400/mask=xffe0fc00 --status nopcodeop\n\n:uhsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uhsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00\n# CONSTRUCT x2ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4\n# AUNIT --inst x2ea02400/mask=xffe0fc00 --status nopcodeop\n\n:uhsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uhsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00\n# CONSTRUCT x2e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2\n# AUNIT --inst x2e602400/mask=xffe0fc00 --status nopcodeop\n\n:uhsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uhsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00\n# CONSTRUCT x6ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4\n# AUNIT --inst x6ea02400/mask=xffe0fc00 --status nopcodeop\n\n:uhsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uhsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00\n# CONSTRUCT x2e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1\n# AUNIT --inst x2e202400/mask=xffe0fc00 --status nopcodeop\n\n:uhsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uhsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00\n# CONSTRUCT x6e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2\n# AUNIT --inst x6e602400/mask=xffe0fc00 --status nopcodeop\n\n:uhsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uhsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00\n# CONSTRUCT x6e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1\n# AUNIT --inst x6e206400/mask=xffe0fc00 --status nopcodeop\n\n:umax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_umax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00\n# CONSTRUCT x2ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4\n# AUNIT --inst x2ea06400/mask=xffe0fc00 --status nopcodeop\n\n:umax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_umax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00\n# CONSTRUCT x2e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2\n# AUNIT --inst x2e606400/mask=xffe0fc00 --status nopcodeop\n\n:umax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_umax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00\n# CONSTRUCT x6ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4\n# AUNIT --inst x6ea06400/mask=xffe0fc00 --status nopcodeop\n\n:umax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_umax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00\n# CONSTRUCT x2e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1\n# AUNIT --inst x2e206400/mask=xffe0fc00 --status nopcodeop\n\n:umax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_umax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00\n# CONSTRUCT x6e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2\n# AUNIT --inst x6e606400/mask=xffe0fc00 --status nopcodeop\n\n:umax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_umax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00\n# CONSTRUCT x6e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1\n# AUNIT --inst x6e20a400/mask=xffe0fc00 --status nopcodeop\n\n:umaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_umaxp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00\n# CONSTRUCT x2ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4\n# AUNIT --inst x2ea0a400/mask=xffe0fc00 --status nopcodeop\n\n:umaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_umaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00\n# CONSTRUCT x2e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2\n# AUNIT --inst x2e60a400/mask=xffe0fc00 --status nopcodeop\n\n:umaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_umaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00\n# CONSTRUCT x6ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4\n# AUNIT --inst x6ea0a400/mask=xffe0fc00 --status nopcodeop\n\n:umaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_umaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00\n# CONSTRUCT x2e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1\n# AUNIT --inst x2e20a400/mask=xffe0fc00 --status nopcodeop\n\n:umaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_umaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00\n# CONSTRUCT x6e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2\n# AUNIT --inst x6e60a400/mask=xffe0fc00 --status nopcodeop\n\n:umaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_umaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00\n# CONSTRUCT x6e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1\n# AUNIT --inst x6e30a800/mask=xfffffc00 --status nopcodeop\n\n:umaxv Rd_FPR8, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_umaxv(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00\n# CONSTRUCT x2e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1\n# AUNIT --inst x2e30a800/mask=xfffffc00 --status nopcodeop\n\n:umaxv Rd_FPR8, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_umaxv(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00\n# CONSTRUCT x2e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2\n# AUNIT --inst x2e70a800/mask=xfffffc00 --status nopcodeop\n\n:umaxv Rd_FPR16, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_umaxv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00\n# CONSTRUCT x6e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2\n# AUNIT --inst x6e70a800/mask=xfffffc00 --status nopcodeop\n\n:umaxv Rd_FPR16, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_umaxv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00\n# CONSTRUCT x6eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@4\n# AUNIT --inst x6eb0a800/mask=xfffffc00 --status nopcodeop\n\n:umaxv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_umaxv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00\n# CONSTRUCT x6e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1\n# AUNIT --inst x6e206c00/mask=xffe0fc00 --status nopcodeop\n\n:umin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_umin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00\n# CONSTRUCT x2ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4\n# AUNIT --inst x2ea06c00/mask=xffe0fc00 --status nopcodeop\n\n:umin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_umin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00\n# CONSTRUCT x2e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2\n# AUNIT --inst x2e606c00/mask=xffe0fc00 --status nopcodeop\n\n:umin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_umin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00\n# CONSTRUCT x6ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4\n# AUNIT --inst x6ea06c00/mask=xffe0fc00 --status nopcodeop\n\n:umin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_umin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00\n# CONSTRUCT x2e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1\n# AUNIT --inst x2e206c00/mask=xffe0fc00 --status nopcodeop\n\n:umin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_umin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00\n# CONSTRUCT x6e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2\n# AUNIT --inst x6e606c00/mask=xffe0fc00 --status nopcodeop\n\n:umin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_umin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00\n# CONSTRUCT x6e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1\n# AUNIT --inst x6e20ac00/mask=xffe0fc00 --status nopcodeop\n\n:uminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00\n# CONSTRUCT x2ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4\n# AUNIT --inst x2ea0ac00/mask=xffe0fc00 --status nopcodeop\n\n:uminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00\n# CONSTRUCT x2e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2\n# AUNIT --inst x2e60ac00/mask=xffe0fc00 --status nopcodeop\n\n:uminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00\n# CONSTRUCT x6ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4\n# AUNIT --inst x6ea0ac00/mask=xffe0fc00 --status nopcodeop\n\n:uminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00\n# CONSTRUCT x2e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1\n# AUNIT --inst x2e20ac00/mask=xffe0fc00 --status nopcodeop\n\n:uminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00\n# CONSTRUCT x6e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2\n# AUNIT --inst x6e60ac00/mask=xffe0fc00 --status nopcodeop\n\n:uminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00\n# CONSTRUCT x6e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1\n# AUNIT --inst x6e31a800/mask=xfffffc00 --status nopcodeop\n\n:uminv Rd_FPR8, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_uminv(Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00\n# CONSTRUCT x2e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1\n# AUNIT --inst x2e31a800/mask=xfffffc00 --status nopcodeop\n\n:uminv Rd_FPR8, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_uminv(Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00\n# CONSTRUCT x2e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2\n# AUNIT --inst x2e71a800/mask=xfffffc00 --status nopcodeop\n\n:uminv Rd_FPR16, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uminv(Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00\n# CONSTRUCT x6e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2\n# AUNIT --inst x6e71a800/mask=xfffffc00 --status nopcodeop\n\n:uminv Rd_FPR16, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uminv(Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00\n# CONSTRUCT x6eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@4\n# AUNIT --inst x6eb1a800/mask=xfffffc00 --status nopcodeop\n\n:uminv Rd_FPR32, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uminv(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400\n# CONSTRUCT x2f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4\n# AUNIT --inst x2f802000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = zext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400\n# CONSTRUCT x6f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $* &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4\n# AUNIT --inst x6f802000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = zext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400\n# CONSTRUCT x2f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2\n# AUNIT --inst x2f402000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = zext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400\n# CONSTRUCT x6f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $* &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2\n# AUNIT --inst x6f402000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = zext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00\n# CONSTRUCT x6ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@4\n# AUNIT --inst x6ea08000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00\n# CONSTRUCT x6e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2\n# AUNIT --inst x6e608000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00\n# CONSTRUCT x6e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@1\n# AUNIT --inst x6e208000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00\n# CONSTRUCT x2ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4\n# AUNIT --inst x2ea08000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00\n# CONSTRUCT x2e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2\n# AUNIT --inst x2e608000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00\n# CONSTRUCT x2e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@1\n# AUNIT --inst x2e208000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400\n# CONSTRUCT x2f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4\n# AUNIT --inst x2f806000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = zext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8\n\tTMPQ2[0,64] = TMPQ1[0,64] * tmp3;\n\tTMPQ2[64,64] = TMPQ1[64,64] * tmp3;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400\n# CONSTRUCT x6f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4\n# AUNIT --inst x6f806000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = zext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8\n\tTMPQ3[0,64] = TMPQ2[0,64] * tmp4;\n\tTMPQ3[64,64] = TMPQ2[64,64] * tmp4;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400\n# CONSTRUCT x2f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2\n# AUNIT --inst x2f406000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = zext(tmp2);\n\t# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4\n\tTMPQ2[0,32] = TMPQ1[0,32] * tmp3;\n\tTMPQ2[32,32] = TMPQ1[32,32] * tmp3;\n\tTMPQ2[64,32] = TMPQ1[64,32] * tmp3;\n\tTMPQ2[96,32] = TMPQ1[96,32] * tmp3;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400\n# CONSTRUCT x6f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2\n# AUNIT --inst x6f406000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = zext(tmp3);\n\t# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4\n\tTMPQ3[0,32] = TMPQ2[0,32] * tmp4;\n\tTMPQ3[32,32] = TMPQ2[32,32] * tmp4;\n\tTMPQ3[64,32] = TMPQ2[64,32] * tmp4;\n\tTMPQ3[96,32] = TMPQ2[96,32] * tmp4;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00\n# CONSTRUCT x6ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4\n# AUNIT --inst x6ea0a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8\n\tTMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tTMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00\n# CONSTRUCT x6e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2\n# AUNIT --inst x6e60a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4\n\tTMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tTMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tTMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tTMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00\n# CONSTRUCT x6e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@1\n# AUNIT --inst x6e20a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2\n\tTMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];\n\tTMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];\n\tTMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];\n\tTMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];\n\tTMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];\n\tTMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];\n\tTMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];\n\tTMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00\n# CONSTRUCT x2ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4\n# AUNIT --inst x2ea0a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8\n\tTMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];\n\tTMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00\n# CONSTRUCT x2e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2\n# AUNIT --inst x2e60a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rd_VPR128 & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4\n\tTMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];\n\tTMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];\n\tTMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];\n\tTMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00\n# CONSTRUCT x2e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@1\n# AUNIT --inst x2e20a000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rd_VPR128 & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2\n\tTMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];\n\tTMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];\n\tTMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];\n\tTMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];\n\tTMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];\n\tTMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];\n\tTMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];\n\tTMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00\n# CONSTRUCT x0e013c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =zext:4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1\n# AUNIT --inst x0e013c00/mask=xffe1fc00 --status pass\n\n:umov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64\n{\n\t# simd element Rn_VPR128[imm_neon_uimm4] lane size 1\n\tlocal tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;\n\tRd_GPR32 = zext(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00\n# CONSTRUCT x0e023c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =zext:4\n# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1\n# AUNIT --inst x0e023c00/mask=xffe3fc00 --status pass\n\n:umov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3\nis b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128\n{\n\t# simd element Rn_VPR128[imm_neon_uimm3] lane size 2\n\tlocal tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;\n\tRd_GPR32 = zext(tmp1);\n\tzext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64\n}\n\n# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400\n# CONSTRUCT x6f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4\n# AUNIT --inst x6f80a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp3:4 = Re_VPR128.S.vIndex;\n\tlocal tmp4:8 = zext(tmp3);\n\t# simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4;\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400\n# CONSTRUCT x6f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2\n# AUNIT --inst x6f40a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp3:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp4:4 = zext(tmp3);\n\t# simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4;\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4;\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4;\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400\n# CONSTRUCT x2f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4\n# AUNIT --inst x2f80a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd element Re_VPR128.S[vIndex] lane size 4\n\tlocal tmp2:4 = Re_VPR128.S.vIndex;\n\tlocal tmp3:8 = zext(tmp2);\n\t# simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3;\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400\n# CONSTRUCT x2f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 =$*\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2\n# AUNIT --inst x2f40a000/mask=xffc0f400 --status pass --comment \"ext\"\n\n:umull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2\n\tlocal tmp2:2 = Re_VPR128Lo.H.vIndexHLM;\n\tlocal tmp3:4 = zext(tmp2);\n\t# simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3;\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3;\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3;\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00\n# CONSTRUCT x6ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$*@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4\n# AUNIT --inst x6ea0c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00\n# CONSTRUCT x6e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$*@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2\n# AUNIT --inst x6e60c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00\n# CONSTRUCT x6e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$*@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@1\n# AUNIT --inst x6e20c000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:umull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00\n# CONSTRUCT x2ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4\n# AUNIT --inst x2ea0c000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:umull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_umull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00\n# CONSTRUCT x2e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2\n# AUNIT --inst x2e60c000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:umull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_umull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00\n# CONSTRUCT x2e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@1\n# AUNIT --inst x2e20c000/mask=xffe0fc00 --status nopcodeop --comment \"ext\"\n\n:umull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_umull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00\n# CONSTRUCT x7e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2\n# AUNIT --inst x7e200c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_uqadd(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00\n# CONSTRUCT x7ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2\n# AUNIT --inst x7ee00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_uqadd(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00\n# CONSTRUCT x7e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2\n# AUNIT --inst x7e600c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uqadd(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00\n# CONSTRUCT x7ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2\n# AUNIT --inst x7ea00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uqadd(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x6e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1\n# AUNIT --inst x6e200c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x6ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@8\n# AUNIT --inst x6ee00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_uqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x2ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4\n# AUNIT --inst x2ea00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x2e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2\n# AUNIT --inst x2e600c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x6ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4\n# AUNIT --inst x6ea00c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x2e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1\n# AUNIT --inst x2e200c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00\n# CONSTRUCT x6e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2\n# AUNIT --inst x6e600c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00\n# CONSTRUCT x7e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2\n# AUNIT --inst x7e205c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_uqrshl(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00\n# CONSTRUCT x7ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2\n# AUNIT --inst x7ee05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_uqrshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00\n# CONSTRUCT x7e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2\n# AUNIT --inst x7e605c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uqrshl(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00\n# CONSTRUCT x7ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2\n# AUNIT --inst x7ea05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uqrshl(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x6e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1\n# AUNIT --inst x6e205c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x6ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@8\n# AUNIT --inst x6ee05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_uqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x2ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4\n# AUNIT --inst x2ea05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x2e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2\n# AUNIT --inst x2e605c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x6ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4\n# AUNIT --inst x6ea05c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x2e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1\n# AUNIT --inst x2e205c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00\n# CONSTRUCT x6e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2\n# AUNIT --inst x6e605c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00\n# CONSTRUCT x6f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@2\n# AUNIT --inst x6f089c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqrshrn2(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00\n# CONSTRUCT x2f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8\n# AUNIT --inst x2f209c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00\n# CONSTRUCT x2f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@4\n# AUNIT --inst x2f109c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqrshrn(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00\n# CONSTRUCT x6f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8\n# AUNIT --inst x6f209c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00\n# CONSTRUCT x2f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@2\n# AUNIT --inst x2f089c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqrshrn(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00\n# CONSTRUCT x6f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@4\n# AUNIT --inst x6f109c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n\n:uqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqrshrn2(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00\n# CONSTRUCT x7f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2\n# AUNIT --inst x7f089c00/mask=xfff8fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:uqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8\nis b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_uqrshrn(Rn_FPR16, Imm_shr_imm8:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00\n# CONSTRUCT x7f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2\n# AUNIT --inst x7f109c00/mask=xfff0fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:uqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_uqrshrn(Rn_FPR32, Imm_shr_imm16:1);\n}\n\n# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00\n# CONSTRUCT x7f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2\n# AUNIT --inst x7f209c00/mask=xffe0fc00 --status nopcodeop --comment \"nointround nointsat\"\n# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:uqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_uqrshrn(Rn_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x6f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1\n# AUNIT --inst x6f087400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x6f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@8\n# AUNIT --inst x6f407400/mask=xffc0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x2f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4\n# AUNIT --inst x2f207400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x2f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2\n# AUNIT --inst x2f107400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x6f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4\n# AUNIT --inst x6f207400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x2f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1\n# AUNIT --inst x2f087400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00\n# CONSTRUCT x6f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2\n# AUNIT --inst x6f107400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00\n# CONSTRUCT x7f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2\n# AUNIT --inst x7f087400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:uqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8\nis b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_uqshl(Rn_FPR8, Imm_shr_imm8:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00\n# CONSTRUCT x7f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2\n# AUNIT --inst x7f107400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:uqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_uqshl(Rn_FPR16, Imm_shr_imm16:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00\n# CONSTRUCT x7f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2\n# AUNIT --inst x7f207400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:uqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_uqshl(Rn_FPR32, Imm_shr_imm32:1);\n}\n\n# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00\n# CONSTRUCT x7f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2\n# AUNIT --inst x7f407400/mask=xffc0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1\n\n:uqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b011111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tRd_FPR64 = NEON_uqshl(Rn_FPR64, Imm_shr_imm64:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00\n# CONSTRUCT x7e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2\n# AUNIT --inst x7e204c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_uqshl(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00\n# CONSTRUCT x7ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2\n# AUNIT --inst x7ee04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_uqshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00\n# CONSTRUCT x7e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2\n# AUNIT --inst x7e604c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uqshl(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00\n# CONSTRUCT x7ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2\n# AUNIT --inst x7ea04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uqshl(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x6e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1\n# AUNIT --inst x6e204c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x6ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@8\n# AUNIT --inst x6ee04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x2ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4\n# AUNIT --inst x2ea04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x2e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2\n# AUNIT --inst x2e604c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x6ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4\n# AUNIT --inst x6ea04c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x2e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1\n# AUNIT --inst x2e204c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00\n# CONSTRUCT x6e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2\n# AUNIT --inst x6e604c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x6f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@2\n# AUNIT --inst x6f089400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x2f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@8\n# AUNIT --inst x2f209400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x2f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@4\n# AUNIT --inst x2f109400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x6f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@8\n# AUNIT --inst x6f209400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x2f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@2\n# AUNIT --inst x2f089400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00\n# CONSTRUCT x6f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@4\n# AUNIT --inst x6f109400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00\n# CONSTRUCT x7f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3\n# AUNIT --inst x7f089400/mask=xfff8fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001\n\n:uqshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8\nis b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd\n{\n\tRd_FPR8 = NEON_uqshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00\n# CONSTRUCT x7f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3\n# AUNIT --inst x7f109400/mask=xfff0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001\n\n:uqshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16\nis b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd\n{\n\tRd_FPR16 = NEON_uqshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);\n}\n\n# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00\n# CONSTRUCT x7f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3\n# AUNIT --inst x7f209400/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01\n\n:uqshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32\nis b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR32 = NEON_uqshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00\n# CONSTRUCT x7e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2\n# AUNIT --inst x7e202c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_FPR8, Rn_FPR8, Rm_FPR8\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_uqsub(Rn_FPR8, Rm_FPR8);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00\n# CONSTRUCT x7ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2\n# AUNIT --inst x7ee02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_uqsub(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00\n# CONSTRUCT x7e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2\n# AUNIT --inst x7e602c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_FPR16, Rn_FPR16, Rm_FPR16\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_uqsub(Rn_FPR16, Rm_FPR16);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00\n# CONSTRUCT x7ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2\n# AUNIT --inst x7ea02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_FPR32, Rn_FPR32, Rm_FPR32\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_uqsub(Rn_FPR32, Rm_FPR32);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x6e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1\n# AUNIT --inst x6e202c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_uqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x6ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@8\n# AUNIT --inst x6ee02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_uqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x2ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4\n# AUNIT --inst x2ea02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_uqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x2e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2\n# AUNIT --inst x2e602c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_uqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x6ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4\n# AUNIT --inst x6ea02c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_uqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x2e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1\n# AUNIT --inst x2e202c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_uqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00\n# CONSTRUCT x6e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2\n# AUNIT --inst x6e602c00/mask=xffe0fc00 --status nopcodeop --comment \"nointsat\"\n\n:uqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_uqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00\n# CONSTRUCT x7e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2\n# AUNIT --inst x7e214800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=00 Q=1 bb=1 mnemonic=uqxtn Ta=FPR16 Tb=FPR8\n\n:uqxtn Rd_FPR8, Rn_FPR16\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_FPR8 & Rn_FPR16 & Zd\n{\n\tRd_FPR8 = NEON_uqxtn(Rd_FPR8, Rn_FPR16);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00\n# CONSTRUCT x7e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2\n# AUNIT --inst x7e614800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=01 Q=1 bb=1 mnemonic=uqxtn Ta=FPR32 Tb=FPR16\n\n:uqxtn Rd_FPR16, Rn_FPR32\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_FPR16 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = NEON_uqxtn(Rd_FPR16, Rn_FPR32);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00\n# CONSTRUCT x7ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2\n# AUNIT --inst x7ea14800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=10 Q=1 bb=1 mnemonic=uqxtn Ta=FPR64 Tb=FPR32\n\n:uqxtn Rd_FPR32, Rn_FPR64\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_FPR32 & Rn_FPR64 & Zd\n{\n\tRd_FPR32 = NEON_uqxtn(Rd_FPR32, Rn_FPR64);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00\n# CONSTRUCT x2e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@2\n# AUNIT --inst x2e214800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=00 Q=0 bb=0 mnemonic=uqxtn e=2 Ta=VPR128.8H Tb=VPR64.8B\n\n:uqxtn Rd_VPR64.8B, Rn_VPR128.8H\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd\n{\n\tRd_VPR64.8B = NEON_uqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00\n# CONSTRUCT x6e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@2\n# AUNIT --inst x6e214800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=00 Q=1 bb=0 mnemonic=uqxtn2 e=2 Ta=VPR128.8H Tb=VPR128.16B\n\n:uqxtn2 Rd_VPR128.16B, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.16B = NEON_uqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00\n# CONSTRUCT x2e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@4\n# AUNIT --inst x2e614800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=01 Q=0 bb=0 mnemonic=uqxtn e=4 Ta=VPR128.4S Tb=VPR64.4H\n\n:uqxtn Rd_VPR64.4H, Rn_VPR128.4S\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd\n{\n\tRd_VPR64.4H = NEON_uqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00\n# CONSTRUCT x6e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@4\n# AUNIT --inst x6e614800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=01 Q=1 bb=0 mnemonic=uqxtn2 e=4 Ta=VPR128.4S Tb=VPR128.8H\n\n:uqxtn2 Rd_VPR128.8H, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.8H = NEON_uqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00\n# CONSTRUCT x2ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@8\n# AUNIT --inst x2ea14800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=10 Q=0 bb=0 mnemonic=uqxtn e=8 Ta=VPR128.2D Tb=VPR64.2S\n\n:uqxtn Rd_VPR64.2S, Rn_VPR128.2D\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd\n{\n\tRd_VPR64.2S = NEON_uqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00\n# CONSTRUCT x6ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@8\n# AUNIT --inst x6ea14800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=10 Q=1 bb=0 mnemonic=uqxtn2 e=8 Ta=VPR128.2D Tb=VPR128.4S\n\n:uqxtn2 Rd_VPR128.4S, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd\n{\n\tRd_VPR128.4S = NEON_uqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.382 URECPE page C7-2895 line 169051 MATCH x0ea1c800/mask=xbfbffc00\n# CONSTRUCT x0ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4\n# AUNIT --inst x0ea1c800/mask=xfffffc00 --status nopcodeop\n# Vector variant when Q=0 T=VPR64.2S\n\n:urecpe Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_urecpe(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.382 URECPE page C7-2895 line 169051 MATCH x0ea1c800/mask=xbfbffc00\n# CONSTRUCT x4ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4\n# AUNIT --inst x4ea1c800/mask=xfffffc00 --status nopcodeop\n# Vector variant when Q=1 T=VPR128.4S\n\n:urecpe Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_urecpe(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00\n# CONSTRUCT x6e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1\n# AUNIT --inst x6e201400/mask=xffe0fc00 --status nopcodeop\n\n:urhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_urhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00\n# CONSTRUCT x2ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2\n# AUNIT --inst x2ea01400/mask=xffe0fc00 --status nopcodeop\n\n:urhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_urhadd(Rn_VPR64.2S, Rm_VPR64.2S, 2:1);\n}\n\n# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00\n# CONSTRUCT x2e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2\n# AUNIT --inst x2e601400/mask=xffe0fc00 --status nopcodeop\n\n:urhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_urhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00\n# CONSTRUCT x6ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@4\n# AUNIT --inst x6ea01400/mask=xffe0fc00 --status nopcodeop\n\n:urhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_urhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00\n# CONSTRUCT x2e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1\n# AUNIT --inst x2e201400/mask=xffe0fc00 --status nopcodeop\n\n:urhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_urhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00\n# CONSTRUCT x6e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2\n# AUNIT --inst x6e601400/mask=xffe0fc00 --status nopcodeop\n\n:urhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_urhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x7e205400/mask=xff20fc00\n# CONSTRUCT x7ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2\n# AUNIT --inst x7ee05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_urshl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x6e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1\n# AUNIT --inst x6e205400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_urshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x6ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@8\n# AUNIT --inst x6ee05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_urshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x2ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4\n# AUNIT --inst x2ea05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_urshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x2e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2\n# AUNIT --inst x2e605400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_urshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x6ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4\n# AUNIT --inst x6ea05400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_urshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x2e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1\n# AUNIT --inst x2e205400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_urshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00\n# CONSTRUCT x6e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2\n# AUNIT --inst x6e605400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_urshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x6f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1\n# AUNIT --inst x6f082400/mask=xfff8fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_urshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x6f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@8\n# AUNIT --inst x6f402400/mask=xffc0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_urshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x2f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4\n# AUNIT --inst x2f202400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_urshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x2f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2\n# AUNIT --inst x2f102400/mask=xfff0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_urshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x6f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4\n# AUNIT --inst x6f202400/mask=xffe0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_urshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x2f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1\n# AUNIT --inst x2f082400/mask=xfff8fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_urshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00\n# CONSTRUCT x6f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2\n# AUNIT --inst x6f102400/mask=xfff0fc00 --status nopcodeop --comment \"nointround\"\n\n:urshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_urshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1);\n}\n\n# C7.2.385 URSHR page C7-2900 line 169341 MATCH x7f002400/mask=xff80fc00\n# CONSTRUCT x7f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2\n# AUNIT --inst x7f402400/mask=xffc0fc00 --status nopcodeop --comment \"nointround\"\n# Scalar variant\n\n:urshr Rd_FPR64, Rn_FPR64, Imm_shr_imm32\nis b_2331=0b011111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm32 & Zd\n{\n\tRd_FPR64 = NEON_urshr(Rn_FPR64, Imm_shr_imm32:1);\n}\n\n# C7.2.386 URSQRTE page C7-2903 line 169492 MATCH x2ea1c800/mask=xbfbffc00\n# CONSTRUCT x2ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4\n# AUNIT --inst x2ea1c800/mask=xfffffc00 --status nopcodeop\n# Vector variant when Q=0 T=VPR64.2S\n\n:ursqrte Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_ursqrte(Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.386 URSQRTE page C7-2903 line 169492 MATCH x2ea1c800/mask=xbfbffc00\n# CONSTRUCT x6ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4\n# AUNIT --inst x6ea1c800/mask=xfffffc00 --status nopcodeop\n# Vector variant when Q=0 T=VPR128.4S\n\n:ursqrte Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_ursqrte(Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x6f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1\n# AUNIT --inst x6f083400/mask=xfff8fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x6f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@8\n# AUNIT --inst x6f403400/mask=xffc0fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\t# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x2f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4\n# AUNIT --inst x2f203400/mask=xffe0fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x2f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2\n# AUNIT --inst x2f103400/mask=xfff0fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 4\n\tRd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] + TMPD1[0,32];\n\tRd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x6f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4\n# AUNIT --inst x6f203400/mask=xffe0fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x2f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1\n# AUNIT --inst x2f083400/mask=xfff8fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00\n# CONSTRUCT x6f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2\n# AUNIT --inst x6f103400/mask=xfff0fc00 --status fail --comment \"nointround\"\n\n:ursra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.387 URSRA page C7-2904 line 169558 MATCH x7f003400/mask=xff80fc00\n# CONSTRUCT x7f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3\n# AUNIT --inst x7f403400/mask=xffc0fc00 --status fail --comment \"nointround\"\n# Scalar variant when immh=1xxx\n\n:ursra Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b011111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tlocal tmp2:8 = Rn_FPR64 >> tmp1;\n\tRd_FPR64 = Rd_FPR64 + tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x7e204400/mask=xff20fc00\n# CONSTRUCT x7ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2\n# AUNIT --inst x7ee04400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_FPR64, Rn_FPR64, Rm_FPR64\nis b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_ushl(Rn_FPR64, Rm_FPR64);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x6e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1\n# AUNIT --inst x6e204400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_ushl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x6ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@8\n# AUNIT --inst x6ee04400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_ushl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x2ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4\n# AUNIT --inst x2ea04400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_ushl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x2e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2\n# AUNIT --inst x2e604400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_ushl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x6ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4\n# AUNIT --inst x6ea04400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_ushl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x2e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1\n# AUNIT --inst x2e204400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_ushl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);\n}\n\n# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00\n# CONSTRUCT x6e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2\n# AUNIT --inst x6e604400/mask=xffe0fc00 --status nopcodeop\n\n:ushl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_ushl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);\n}\n\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x6f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3 =var:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@1\n# AUNIT --inst x6f08a400/mask=xfff8fc00 --status pass --comment \"ext\"\n\n:ushll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tlocal tmp3:2 = Imm_uimm3;\n\t# simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3;\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3;\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3;\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3;\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3;\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3;\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3;\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x2f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 =var:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@4\n# AUNIT --inst x2f20a400/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ushll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\tlocal tmp2:8 = Imm_uimm5;\n\t# simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x2f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 =var:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@2\n# AUNIT --inst x2f10a400/mask=xfff0fc00 --status pass --comment \"ext\"\n\n:ushll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\tlocal tmp2:4 = Imm_uimm4;\n\t# simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2;\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2;\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2;\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x6f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 =var:8 =$<<@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@4\n# AUNIT --inst x6f20a400/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:ushll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tlocal tmp3:8 = Imm_uimm5;\n\t# simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x2f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 =var:2 =$<<@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@1\n# AUNIT --inst x2f08a400/mask=xfff8fc00 --status pass --comment \"ext\"\n\n:ushll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\tlocal tmp2:2 = Imm_uimm3;\n\t# simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2;\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2;\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2;\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2;\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2;\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2;\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2;\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# CONSTRUCT x6f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 =var:4 =$<<@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@2\n# AUNIT --inst x6f10a400/mask=xfff0fc00 --status pass --comment \"ext\"\n\n:ushll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tlocal tmp3:4 = Imm_uimm4;\n\t# simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3;\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3;\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3;\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x6f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 =$>>@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1\n# AUNIT --inst x6f080400/mask=xfff8fc00 --status pass\n\n:ushr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix Rd_VPR128.16B = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;\n\tRd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x6f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 =$>>@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@8\n# AUNIT --inst x6f400400/mask=xffc0fc00 --status pass\n\n:ushr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D >> tmp1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] >> tmp1;\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] >> tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x2f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4\n# AUNIT --inst x2f200400/mask=xffe0fc00 --status pass\n\n:ushr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix Rd_VPR64.2S = Rn_VPR64.2S >> tmp1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] >> tmp1;\n\tRd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] >> tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x2f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 =$>>@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2\n# AUNIT --inst x2f100400/mask=xfff0fc00 --status pass\n\n:ushr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix Rd_VPR64.4H = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2\n\tRd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;\n\tRd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;\n\tRd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;\n\tRd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x6f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4\n# AUNIT --inst x6f200400/mask=xffe0fc00 --status pass\n\n:ushr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S >> tmp1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] >> tmp1;\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] >> tmp1;\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] >> tmp1;\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] >> tmp1;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x2f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 =$>>@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1\n# AUNIT --inst x2f080400/mask=xfff8fc00 --status pass\n\n:ushr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix Rd_VPR64.8B = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;\n\tRd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00\n# CONSTRUCT x6f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 =$>>@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2\n# AUNIT --inst x6f100400/mask=xfff0fc00 --status pass\n\n:ushr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.392 USHR page C7-2916 line 170174 MATCH x7f000400/mask=xff80fc00\n# CONSTRUCT x7f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 =>>\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2\n# AUNIT --inst x7f400400/mask=xffc0fc00 --status pass\n# Scalar variant when immh=1xxx\n\n:ushr Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b011111110 & b_22=1 & b_1015=0b000001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tRd_FPR64 = Rn_FPR64 >> tmp1;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00\n# CONSTRUCT x7e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2\n# AUNIT --inst x7e203800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=00 Q=1 bb=1 T=FPR8\n\n:usqadd Rd_FPR8, Rn_FPR8\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd\n{\n\tRd_FPR8 = NEON_usqadd(Rd_FPR8, Rn_FPR8);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00\n# CONSTRUCT x7e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2\n# AUNIT --inst x7e603800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=01 Q=1 bb=1 T=FPR16\n\n:usqadd Rd_FPR16, Rn_FPR16\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd\n{\n\tRd_FPR16 = NEON_usqadd(Rd_FPR16, Rn_FPR16);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00\n# CONSTRUCT x7ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2\n# AUNIT --inst x7ea03800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=10 Q=1 bb=1 T=FPR32\n\n:usqadd Rd_FPR32, Rn_FPR32\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd\n{\n\tRd_FPR32 = NEON_usqadd(Rd_FPR32, Rn_FPR32);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00\n# CONSTRUCT x7ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2\n# AUNIT --inst x7ee03800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Scalar variant when size=11 Q=1 bb=1 T=FPR64\n\n:usqadd Rd_FPR64, Rn_FPR64\nis b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd\n{\n\tRd_FPR64 = NEON_usqadd(Rd_FPR64, Rn_FPR64);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x2e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1\n# AUNIT --inst x2e203800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=00 Q=0 bb=0 e=1 T=VPR64.8B\n\n:usqadd Rd_VPR64.8B, Rn_VPR64.8B\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd\n{\n\tRd_VPR64.8B = NEON_usqadd(Rd_VPR64.8B, Rn_VPR64.8B, 1:1);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x6e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1\n# AUNIT --inst x6e203800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=00 Q=1 bb=0 e=1 T=VPR128.16B\n\n:usqadd Rd_VPR128.16B, Rn_VPR128.16B\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd\n{\n\tRd_VPR128.16B = NEON_usqadd(Rd_VPR128.16B, Rn_VPR128.16B, 1:1);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x2e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2\n# AUNIT --inst x2e603800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=01 Q=0 bb=0 e=2 T=VPR64.4H\n\n:usqadd Rd_VPR64.4H, Rn_VPR64.4H\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd\n{\n\tRd_VPR64.4H = NEON_usqadd(Rd_VPR64.4H, Rn_VPR64.4H, 2:1);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x6e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2\n# AUNIT --inst x6e603800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=01 Q=1 bb=0 e=2 T=VPR128.8H\n\n:usqadd Rd_VPR128.8H, Rn_VPR128.8H\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd\n{\n\tRd_VPR128.8H = NEON_usqadd(Rd_VPR128.8H, Rn_VPR128.8H, 2:1);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x2ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4\n# AUNIT --inst x2ea03800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=10 Q=0 bb=0 e=4 T=VPR64.2S\n\n:usqadd Rd_VPR64.2S, Rn_VPR64.2S\nis b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd\n{\n\tRd_VPR64.2S = NEON_usqadd(Rd_VPR64.2S, Rn_VPR64.2S, 4:1);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x6ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4\n# AUNIT --inst x6ea03800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=10 Q=1 bb=0 e=4 T=VPR128.4S\n\n:usqadd Rd_VPR128.4S, Rn_VPR128.4S\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd\n{\n\tRd_VPR128.4S = NEON_usqadd(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);\n}\n\n# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00\n# CONSTRUCT x6ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@8\n# AUNIT --inst x6ee03800/mask=xfffffc00 --status nopcodeop --comment \"nointsat\"\n# Vector variant when size=11 Q=1 bb=0 e=8 T=VPR128.2D\n\n:usqadd Rd_VPR128.2D, Rn_VPR128.2D\nis b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd\n{\n\tRd_VPR128.2D = NEON_usqadd(Rd_VPR128.2D, Rn_VPR128.2D, 8:1);\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x6f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1\n# AUNIT --inst x6f081400/mask=xfff8fc00 --status pass\n\n:usra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1\n\tTMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;\n\tTMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;\n\tTMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;\n\tTMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;\n\tTMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;\n\tTMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;\n\tTMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;\n\tTMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;\n\tTMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;\n\tTMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;\n\tTMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;\n\tTMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;\n\tTMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;\n\tTMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;\n\tTMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;\n\tTMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1\n\tRd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];\n\tRd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];\n\tRd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];\n\tRd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];\n\tRd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];\n\tRd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];\n\tRd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];\n\tRd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];\n\tRd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];\n\tRd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];\n\tRd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];\n\tRd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];\n\tRd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];\n\tRd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];\n\tRd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x6f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@8\n# AUNIT --inst x6f401400/mask=xffc0fc00 --status pass\n\n:usra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\t# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;\n\t# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x2f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4\n# AUNIT --inst x2f201400/mask=xffe0fc00 --status pass\n\n:usra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4\n\tTMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1;\n\tTMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1;\n\t# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4\n\tRd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x2f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2\n# AUNIT --inst x2f101400/mask=xfff0fc00 --status pass\n\n:usra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2\n\tTMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;\n\tTMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;\n\tTMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;\n\tTMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2\n\tRd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x6f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4\n# AUNIT --inst x6f201400/mask=xffe0fc00 --status pass\n\n:usra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tlocal tmp1:4 = Imm_shr_imm32;\n\t# simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4\n\tTMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1;\n\tTMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1;\n\tTMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1;\n\tTMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1;\n\t# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x2f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1\n# AUNIT --inst x2f081400/mask=xfff8fc00 --status pass\n\n:usra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\t# simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1\n\tTMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;\n\tTMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;\n\tTMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;\n\tTMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;\n\tTMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;\n\tTMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;\n\tTMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;\n\tTMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;\n\t# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1\n\tRd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00\n# CONSTRUCT x6f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2\n# AUNIT --inst x6f101400/mask=xfff0fc00 --status pass\n\n:usra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2\n\tTMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;\n\tTMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;\n\tTMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;\n\tTMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;\n\tTMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;\n\tTMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;\n\tTMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;\n\tTMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;\n\t# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.395 USRA page C7-2922 line 170519 MATCH x7f001400/mask=xff80fc00\n# CONSTRUCT x7f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+\n# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3\n# AUNIT --inst x7f401400/mask=xffc0fc00 --status pass\n# Scalar variant when immh=1xxx\n\n:usra Rd_FPR64, Rn_FPR64, Imm_shr_imm64\nis b_2331=0b011111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd\n{\n\tlocal tmp1:8 = zext(Imm_shr_imm64);\n\tlocal tmp2:8 = Rn_FPR64 >> tmp1;\n\tRd_FPR64 = Rd_FPR64 + tmp2;\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00\n# CONSTRUCT x6ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@4\n# AUNIT --inst x6ea02000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\tTMPD3 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)\n\tTMPQ4[0,64] = zext(TMPD3[0,32]);\n\tTMPQ4[64,64] = zext(TMPD3[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00\n# CONSTRUCT x6e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@2\n# AUNIT --inst x6e602000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\tTMPD3 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)\n\tTMPQ4[0,32] = zext(TMPD3[0,16]);\n\tTMPQ4[32,32] = zext(TMPD3[16,16]);\n\tTMPQ4[64,32] = zext(TMPD3[32,16]);\n\tTMPQ4[96,32] = zext(TMPD3[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00\n# CONSTRUCT x6e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@1\n# AUNIT --inst x6e202000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\tTMPD3 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)\n\tTMPQ4[0,16] = zext(TMPD3[0,8]);\n\tTMPQ4[16,16] = zext(TMPD3[8,8]);\n\tTMPQ4[32,16] = zext(TMPD3[16,8]);\n\tTMPQ4[48,16] = zext(TMPD3[24,8]);\n\tTMPQ4[64,16] = zext(TMPD3[32,8]);\n\tTMPQ4[80,16] = zext(TMPD3[40,8]);\n\tTMPQ4[96,16] = zext(TMPD3[48,8]);\n\tTMPQ4[112,16] = zext(TMPD3[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00\n# CONSTRUCT x2ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@4\n# AUNIT --inst x2ea02000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00\n# CONSTRUCT x2e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@2\n# AUNIT --inst x2e602000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00\n# CONSTRUCT x2e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@1\n# AUNIT --inst x2e202000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);\n\t# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00\n# CONSTRUCT x6ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@4\n# AUNIT --inst x6ea03000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rm_VPR128.4S[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)\n\tTMPQ2[0,64] = zext(TMPD1[0,32]);\n\tTMPQ2[64,64] = zext(TMPD1[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00\n# CONSTRUCT x6e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@2\n# AUNIT --inst x6e603000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rm_VPR128.8H[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)\n\tTMPQ2[0,32] = zext(TMPD1[0,16]);\n\tTMPQ2[32,32] = zext(TMPD1[16,16]);\n\tTMPQ2[64,32] = zext(TMPD1[32,16]);\n\tTMPQ2[96,32] = zext(TMPD1[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00\n# CONSTRUCT x6e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@1\n# AUNIT --inst x6e203000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rm_VPR128.16B[64,64];\n\t# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)\n\tTMPQ2[0,16] = zext(TMPD1[0,8]);\n\tTMPQ2[16,16] = zext(TMPD1[8,8]);\n\tTMPQ2[32,16] = zext(TMPD1[16,8]);\n\tTMPQ2[48,16] = zext(TMPD1[24,8]);\n\tTMPQ2[64,16] = zext(TMPD1[32,8]);\n\tTMPQ2[80,16] = zext(TMPD1[40,8]);\n\tTMPQ2[96,16] = zext(TMPD1[48,8]);\n\tTMPQ2[112,16] = zext(TMPD1[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00\n# CONSTRUCT x2ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$-@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@4\n# AUNIT --inst x2ea03000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\t# simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8)\n\tTMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]);\n\tTMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]);\n\t# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8\n\tRd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64];\n\tRd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00\n# CONSTRUCT x2e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$-@4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@2\n# AUNIT --inst x2e603000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4)\n\tTMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]);\n\tTMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]);\n\tTMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]);\n\tTMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]);\n\t# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4\n\tRd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32];\n\tRd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32];\n\tRd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00\n# CONSTRUCT x2e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$-@2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@1\n# AUNIT --inst x2e203000/mask=xffe0fc00 --status pass --comment \"ext\"\n\n:usubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2)\n\tTMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]);\n\tTMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]);\n\tTMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]);\n\tTMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]);\n\tTMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]);\n\tTMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]);\n\tTMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]);\n\tTMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]);\n\t# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2\n\tRd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16];\n\tRd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16];\n\tRd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16];\n\tRd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16];\n\tRd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16];\n\tRd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16];\n\tRd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# CONSTRUCT x6f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$zext@1:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@1\n# AUNIT --inst x6f08a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uxtl2 Rd_VPR128.8H, Rn_VPR128.16B\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR128.16B[64,64];\n\t# simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2)\n\tRd_VPR128.8H[0,16] = zext(TMPD1[0,8]);\n\tRd_VPR128.8H[16,16] = zext(TMPD1[8,8]);\n\tRd_VPR128.8H[32,16] = zext(TMPD1[16,8]);\n\tRd_VPR128.8H[48,16] = zext(TMPD1[24,8]);\n\tRd_VPR128.8H[64,16] = zext(TMPD1[32,8]);\n\tRd_VPR128.8H[80,16] = zext(TMPD1[40,8]);\n\tRd_VPR128.8H[96,16] = zext(TMPD1[48,8]);\n\tRd_VPR128.8H[112,16] = zext(TMPD1[56,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# CONSTRUCT x2f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$zext@4:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@4\n# AUNIT --inst x2f20a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uxtl Rd_VPR128.2D, Rn_VPR64.2S\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8)\n\tRd_VPR128.2D[0,64] = zext(TMPD1[0,32]);\n\tRd_VPR128.2D[64,64] = zext(TMPD1[32,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# CONSTRUCT x2f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$zext@2:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@2\n# AUNIT --inst x2f10a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uxtl Rd_VPR128.4S, Rn_VPR64.4H\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4)\n\tRd_VPR128.4S[0,32] = zext(TMPD1[0,16]);\n\tRd_VPR128.4S[32,32] = zext(TMPD1[16,16]);\n\tRd_VPR128.4S[64,32] = zext(TMPD1[32,16]);\n\tRd_VPR128.4S[96,32] = zext(TMPD1[48,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# CONSTRUCT x6f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$zext@4:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@4\n# AUNIT --inst x6f20a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uxtl2 Rd_VPR128.2D, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd\n{\n\tTMPD1 = Rn_VPR128.4S[64,64];\n\t# simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8)\n\tRd_VPR128.2D[0,64] = zext(TMPD1[0,32]);\n\tRd_VPR128.2D[64,64] = zext(TMPD1[32,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# CONSTRUCT x2f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 =var =$zext@1:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@1\n# AUNIT --inst x2f08a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uxtl Rd_VPR128.8H, Rn_VPR64.8B\nis b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd\n{\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2)\n\tRd_VPR128.8H[0,16] = zext(TMPD1[0,8]);\n\tRd_VPR128.8H[16,16] = zext(TMPD1[8,8]);\n\tRd_VPR128.8H[32,16] = zext(TMPD1[16,8]);\n\tRd_VPR128.8H[48,16] = zext(TMPD1[24,8]);\n\tRd_VPR128.8H[64,16] = zext(TMPD1[32,8]);\n\tRd_VPR128.8H[80,16] = zext(TMPD1[40,8]);\n\tRd_VPR128.8H[96,16] = zext(TMPD1[48,8]);\n\tRd_VPR128.8H[112,16] = zext(TMPD1[56,8]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00\n# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00\n# CONSTRUCT x6f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2[1]:8 =$zext@2:16\n# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@2\n# AUNIT --inst x6f10a400/mask=xfffffc00 --status pass --comment \"ext\"\n\n:uxtl2 Rd_VPR128.4S, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPD1 = Rn_VPR128.8H[64,64];\n\t# simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4)\n\tRd_VPR128.4S[0,32] = zext(TMPD1[0,16]);\n\tRd_VPR128.4S[32,32] = zext(TMPD1[16,16]);\n\tRd_VPR128.4S[64,32] = zext(TMPD1[32,16]);\n\tRd_VPR128.4S[96,32] = zext(TMPD1[48,16]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x4e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7:1 swap &=$shuffle@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1\n# AUNIT --inst x4e001800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ2 = Rm_VPR128.16B;\n\tTMPQ1 = Rn_VPR128.16B;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7) lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[0,8];\n\tRd_VPR128.16B[8,8] = TMPQ1[16,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[32,8];\n\tRd_VPR128.16B[24,8] = TMPQ1[48,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[64,8];\n\tRd_VPR128.16B[40,8] = TMPQ1[80,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[96,8];\n\tRd_VPR128.16B[56,8] = TMPQ1[112,8];\n\t# simd shuffle Rd_VPR128.16B = TMPQ2 (@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15) lane size 1\n\tRd_VPR128.16B[64,8] = TMPQ2[0,8];\n\tRd_VPR128.16B[72,8] = TMPQ2[16,8];\n\tRd_VPR128.16B[80,8] = TMPQ2[32,8];\n\tRd_VPR128.16B[88,8] = TMPQ2[48,8];\n\tRd_VPR128.16B[96,8] = TMPQ2[64,8];\n\tRd_VPR128.16B[104,8] = TMPQ2[80,8];\n\tRd_VPR128.16B[112,8] = TMPQ2[96,8];\n\tRd_VPR128.16B[120,8] = TMPQ2[112,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x4ec01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@8\n# AUNIT --inst x4ec01800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ2 = Rm_VPR128.2D;\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64];\n\t# simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8\n\tRd_VPR128.2D[64,64] = TMPQ2[0,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x0e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4\n# AUNIT --inst x0e801800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD2 = Rm_VPR64.2S;\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[0,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4\n\tRd_VPR64.2S[32,32] = TMPD2[0,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x0e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:2 swap &=$shuffle@0-2@2-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2\n# AUNIT --inst x0e401800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD2 = Rm_VPR64.4H;\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-1) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = TMPD1[32,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD2 (@0-2@2-3) lane size 2\n\tRd_VPR64.4H[32,16] = TMPD2[0,16];\n\tRd_VPR64.4H[48,16] = TMPD2[32,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x4e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:4 swap &=$shuffle@0-2@2-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4\n# AUNIT --inst x4e801800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ2 = Rm_VPR128.4S;\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-1) lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[64,32];\n\t# simd shuffle Rd_VPR128.4S = TMPQ2 (@0-2@2-3) lane size 4\n\tRd_VPR128.4S[64,32] = TMPQ2[0,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[64,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x0e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:1 swap &=$shuffle@0-4@2-5@4-6@6-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1\n# AUNIT --inst x0e001800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD2 = Rm_VPR64.8B;\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-1@4-2@6-3) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = TMPD1[16,8];\n\tRd_VPR64.8B[16,8] = TMPD1[32,8];\n\tRd_VPR64.8B[24,8] = TMPD1[48,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD2 (@0-4@2-5@4-6@6-7) lane size 1\n\tRd_VPR64.8B[32,8] = TMPD2[0,8];\n\tRd_VPR64.8B[40,8] = TMPD2[16,8];\n\tRd_VPR64.8B[48,8] = TMPD2[32,8];\n\tRd_VPR64.8B[56,8] = TMPD2[48,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00\n# CONSTRUCT x4e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:2 swap &=$shuffle@0-4@2-5@4-6@6-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2\n# AUNIT --inst x4e401800/mask=xffe0fc00 --status pass\n\n:uzp1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ2 = Rm_VPR128.8H;\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-1@4-2@6-3) lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[32,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[64,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[96,16];\n\t# simd shuffle Rd_VPR128.8H = TMPQ2 (@0-4@2-5@4-6@6-7) lane size 2\n\tRd_VPR128.8H[64,16] = TMPQ2[0,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[32,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[64,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[96,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x4e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1 swap &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1\n# AUNIT --inst x4e005800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ2 = Rm_VPR128.16B;\n\tTMPQ1 = Rn_VPR128.16B;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[8,8];\n\tRd_VPR128.16B[8,8] = TMPQ1[24,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[40,8];\n\tRd_VPR128.16B[24,8] = TMPQ1[56,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[72,8];\n\tRd_VPR128.16B[40,8] = TMPQ1[88,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[104,8];\n\tRd_VPR128.16B[56,8] = TMPQ1[120,8];\n\t# simd shuffle Rd_VPR128.16B = TMPQ2 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1\n\tRd_VPR128.16B[64,8] = TMPQ2[8,8];\n\tRd_VPR128.16B[72,8] = TMPQ2[24,8];\n\tRd_VPR128.16B[80,8] = TMPQ2[40,8];\n\tRd_VPR128.16B[88,8] = TMPQ2[56,8];\n\tRd_VPR128.16B[96,8] = TMPQ2[72,8];\n\tRd_VPR128.16B[104,8] = TMPQ2[88,8];\n\tRd_VPR128.16B[112,8] = TMPQ2[104,8];\n\tRd_VPR128.16B[120,8] = TMPQ2[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x4ec05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@8\n# AUNIT --inst x4ec05800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ2 = Rm_VPR128.2D;\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[64,64];\n\t# simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x0e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4\n# AUNIT --inst x0e805800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD2 = Rm_VPR64.2S;\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[32,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4\n\tRd_VPR64.2S[32,32] = TMPD2[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x0e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:2 swap &=$shuffle@1-2@3-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2\n# AUNIT --inst x0e405800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD2 = Rm_VPR64.4H;\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-1) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[16,16];\n\tRd_VPR64.4H[16,16] = TMPD1[48,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD2 (@1-2@3-3) lane size 2\n\tRd_VPR64.4H[32,16] = TMPD2[16,16];\n\tRd_VPR64.4H[48,16] = TMPD2[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x4e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:4 swap &=$shuffle@1-2@3-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4\n# AUNIT --inst x4e805800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ2 = Rm_VPR128.4S;\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-1) lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[32,32];\n\tRd_VPR128.4S[32,32] = TMPQ1[96,32];\n\t# simd shuffle Rd_VPR128.4S = TMPQ2 (@1-2@3-3) lane size 4\n\tRd_VPR128.4S[64,32] = TMPQ2[32,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x0e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:1 swap &=$shuffle@1-4@3-5@5-6@7-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1\n# AUNIT --inst x0e005800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD2 = Rm_VPR64.8B;\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-1@5-2@7-3) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[8,8];\n\tRd_VPR64.8B[8,8] = TMPD1[24,8];\n\tRd_VPR64.8B[16,8] = TMPD1[40,8];\n\tRd_VPR64.8B[24,8] = TMPD1[56,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD2 (@1-4@3-5@5-6@7-7) lane size 1\n\tRd_VPR64.8B[32,8] = TMPD2[8,8];\n\tRd_VPR64.8B[40,8] = TMPD2[24,8];\n\tRd_VPR64.8B[48,8] = TMPD2[40,8];\n\tRd_VPR64.8B[56,8] = TMPD2[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00\n# CONSTRUCT x4e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:2 swap &=$shuffle@1-4@3-5@5-6@7-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2\n# AUNIT --inst x4e405800/mask=xffe0fc00 --status pass\n\n:uzp2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ2 = Rm_VPR128.8H;\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[16,16];\n\tRd_VPR128.8H[16,16] = TMPQ1[48,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[80,16];\n\tRd_VPR128.8H[48,16] = TMPQ1[112,16];\n\t# simd shuffle Rd_VPR128.8H = TMPQ2 (@1-4@3-5@5-6@7-7) lane size 2\n\tRd_VPR128.8H[64,16] = TMPQ2[16,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[48,16];\n\tRd_VPR128.8H[96,16] = TMPQ2[80,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.401 XAR page C7-2935 line 171254 MATCH xce800000/mask=xffe00000\n# CONSTRUCT xce800000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 ARG3 $|@8 ARG4 =var:8 =$>>@8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_xar/3@8\n# AUNIT --inst xce800000/mask=xffe00000 --status noqemu\n# Advanced SIMD variant\n\n:xar Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, LSB_bitfield64_imm\nis b_2131=0b11001110100 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & LSB_bitfield64_imm & Zd\n{\n\t# simd infix TMPQ1 = Rn_VPR128.2D | Rm_VPR128.2D on lane size 8\n\tTMPQ1[0,64] = Rn_VPR128.2D[0,64] | Rm_VPR128.2D[0,64];\n\tTMPQ1[64,64] = Rn_VPR128.2D[64,64] | Rm_VPR128.2D[64,64];\n\tlocal tmp2:8 = LSB_bitfield64_imm;\n\t# simd infix Rd_VPR128.2D = TMPQ1 >> tmp2 on lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64] >> tmp2;\n\tRd_VPR128.2D[64,64] = TMPQ1[64,64] >> tmp2;\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00\n# CONSTRUCT x0ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-0@1-1:4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@8\n# AUNIT --inst x0ea12800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:xtn Rd_VPR64.2S, Rn_VPR128.2D\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd\n{\n\t# simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4)\n\tTMPD1[0,32] = Rn_VPR128.2D[0,32];\n\tTMPD1[32,32] = Rn_VPR128.2D[64,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0@1-1) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[0,32];\n\tRd_VPR64.2S[32,32] = TMPD1[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00\n# CONSTRUCT x4ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-2@1-3:4\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@8\n# AUNIT --inst x4ea12800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:xtn2 Rd_VPR128.4S, Rn_VPR128.2D\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd\n{\n\t# simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4)\n\tTMPD1[0,32] = Rn_VPR128.2D[0,32];\n\tTMPD1[32,32] = Rn_VPR128.2D[64,32];\n\t# simd shuffle Rd_VPR128.4S = TMPD1 (@0-2@1-3) lane size 4\n\tRd_VPR128.4S[64,32] = TMPD1[0,32];\n\tRd_VPR128.4S[96,32] = TMPD1[32,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00\n# CONSTRUCT x0e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-0@1-1@2-2@3-3:2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@4\n# AUNIT --inst x0e612800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:xtn Rd_VPR64.4H, Rn_VPR128.4S\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd\n{\n\t# simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2)\n\tTMPD1[0,16] = Rn_VPR128.4S[0,16];\n\tTMPD1[16,16] = Rn_VPR128.4S[32,16];\n\tTMPD1[32,16] = Rn_VPR128.4S[64,16];\n\tTMPD1[48,16] = Rn_VPR128.4S[96,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-1@2-2@3-3) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[0,16];\n\tRd_VPR64.4H[16,16] = TMPD1[16,16];\n\tRd_VPR64.4H[32,16] = TMPD1[32,16];\n\tRd_VPR64.4H[48,16] = TMPD1[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00\n# CONSTRUCT x4e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-4@1-5@2-6@3-7:2\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@4\n# AUNIT --inst x4e612800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:xtn2 Rd_VPR128.8H, Rn_VPR128.4S\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd\n{\n\t# simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2)\n\tTMPD1[0,16] = Rn_VPR128.4S[0,16];\n\tTMPD1[16,16] = Rn_VPR128.4S[32,16];\n\tTMPD1[32,16] = Rn_VPR128.4S[64,16];\n\tTMPD1[48,16] = Rn_VPR128.4S[96,16];\n\t# simd shuffle Rd_VPR128.8H = TMPD1 (@0-4@1-5@2-6@3-7) lane size 2\n\tRd_VPR128.8H[64,16] = TMPD1[0,16];\n\tRd_VPR128.8H[80,16] = TMPD1[16,16];\n\tRd_VPR128.8H[96,16] = TMPD1[32,16];\n\tRd_VPR128.8H[112,16] = TMPD1[48,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00\n# CONSTRUCT x0e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7:1\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@2\n# AUNIT --inst x0e212800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:xtn Rd_VPR64.8B, Rn_VPR128.8H\nis b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd\n{\n\t# simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1)\n\tTMPD1[0,8] = Rn_VPR128.8H[0,8];\n\tTMPD1[8,8] = Rn_VPR128.8H[16,8];\n\tTMPD1[16,8] = Rn_VPR128.8H[32,8];\n\tTMPD1[24,8] = Rn_VPR128.8H[48,8];\n\tTMPD1[32,8] = Rn_VPR128.8H[64,8];\n\tTMPD1[40,8] = Rn_VPR128.8H[80,8];\n\tTMPD1[48,8] = Rn_VPR128.8H[96,8];\n\tTMPD1[56,8] = Rn_VPR128.8H[112,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[0,8];\n\tRd_VPR64.8B[8,8] = TMPD1[8,8];\n\tRd_VPR64.8B[16,8] = TMPD1[16,8];\n\tRd_VPR64.8B[24,8] = TMPD1[24,8];\n\tRd_VPR64.8B[32,8] = TMPD1[32,8];\n\tRd_VPR64.8B[40,8] = TMPD1[40,8];\n\tRd_VPR64.8B[48,8] = TMPD1[48,8];\n\tRd_VPR64.8B[56,8] = TMPD1[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00\n# CONSTRUCT x4e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15:1\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@2\n# AUNIT --inst x4e212800/mask=xfffffc00 --status pass --comment \"ext\"\n\n:xtn2 Rd_VPR128.16B, Rn_VPR128.8H\nis b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd\n{\n\t# simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1)\n\tTMPD1[0,8] = Rn_VPR128.8H[0,8];\n\tTMPD1[8,8] = Rn_VPR128.8H[16,8];\n\tTMPD1[16,8] = Rn_VPR128.8H[32,8];\n\tTMPD1[24,8] = Rn_VPR128.8H[48,8];\n\tTMPD1[32,8] = Rn_VPR128.8H[64,8];\n\tTMPD1[40,8] = Rn_VPR128.8H[80,8];\n\tTMPD1[48,8] = Rn_VPR128.8H[96,8];\n\tTMPD1[56,8] = Rn_VPR128.8H[112,8];\n\t# simd shuffle Rd_VPR128.16B = TMPD1 (@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15) lane size 1\n\tRd_VPR128.16B[64,8] = TMPD1[0,8];\n\tRd_VPR128.16B[72,8] = TMPD1[8,8];\n\tRd_VPR128.16B[80,8] = TMPD1[16,8];\n\tRd_VPR128.16B[88,8] = TMPD1[24,8];\n\tRd_VPR128.16B[96,8] = TMPD1[32,8];\n\tRd_VPR128.16B[104,8] = TMPD1[40,8];\n\tRd_VPR128.16B[112,8] = TMPD1[48,8];\n\tRd_VPR128.16B[120,8] = TMPD1[56,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x4e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14:1 swap &=$shuffle@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1\n# AUNIT --inst x4e003800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ2 = Rm_VPR128.16B;\n\tTMPQ1 = Rn_VPR128.16B;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14) lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[0,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[8,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[16,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[24,8];\n\tRd_VPR128.16B[64,8] = TMPQ1[32,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[40,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[48,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[56,8];\n\t# simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15) lane size 1\n\tRd_VPR128.16B[8,8] = TMPQ2[0,8];\n\tRd_VPR128.16B[24,8] = TMPQ2[8,8];\n\tRd_VPR128.16B[40,8] = TMPQ2[16,8];\n\tRd_VPR128.16B[56,8] = TMPQ2[24,8];\n\tRd_VPR128.16B[72,8] = TMPQ2[32,8];\n\tRd_VPR128.16B[88,8] = TMPQ2[40,8];\n\tRd_VPR128.16B[104,8] = TMPQ2[48,8];\n\tRd_VPR128.16B[120,8] = TMPQ2[56,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x4ec03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@8\n# AUNIT --inst x4ec03800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ2 = Rm_VPR128.2D;\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[0,64];\n\t# simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8\n\tRd_VPR128.2D[64,64] = TMPQ2[0,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x0e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4\n# AUNIT --inst x0e803800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD2 = Rm_VPR64.2S;\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[0,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4\n\tRd_VPR64.2S[32,32] = TMPD2[0,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x0e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:2 swap &=$shuffle@0-1@1-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2\n# AUNIT --inst x0e403800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD2 = Rm_VPR64.4H;\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-2) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[0,16];\n\tRd_VPR64.4H[32,16] = TMPD1[16,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@1-3) lane size 2\n\tRd_VPR64.4H[16,16] = TMPD2[0,16];\n\tRd_VPR64.4H[48,16] = TMPD2[16,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x4e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:4 swap &=$shuffle@0-1@1-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4\n# AUNIT --inst x4e803800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ2 = Rm_VPR128.4S;\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@1-2) lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[0,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[32,32];\n\t# simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@1-3) lane size 4\n\tRd_VPR128.4S[32,32] = TMPQ2[0,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[32,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x0e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:1 swap &=$shuffle@0-1@1-3@2-5@3-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1\n# AUNIT --inst x0e003800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD2 = Rm_VPR64.8B;\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-2@2-4@3-6) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[0,8];\n\tRd_VPR64.8B[16,8] = TMPD1[8,8];\n\tRd_VPR64.8B[32,8] = TMPD1[16,8];\n\tRd_VPR64.8B[48,8] = TMPD1[24,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@1-3@2-5@3-7) lane size 1\n\tRd_VPR64.8B[8,8] = TMPD2[0,8];\n\tRd_VPR64.8B[24,8] = TMPD2[8,8];\n\tRd_VPR64.8B[40,8] = TMPD2[16,8];\n\tRd_VPR64.8B[56,8] = TMPD2[24,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00\n# CONSTRUCT x4e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:2 swap &=$shuffle@0-1@1-3@2-5@3-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2\n# AUNIT --inst x4e403800/mask=xffe0fc00 --status pass\n\n:zip1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ2 = Rm_VPR128.8H;\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@1-2@2-4@3-6) lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[0,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[16,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[32,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[48,16];\n\t# simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@1-3@2-5@3-7) lane size 2\n\tRd_VPR128.8H[16,16] = TMPQ2[0,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[16,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[32,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[48,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x4e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14:1 swap &=$shuffle@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1\n# AUNIT --inst x4e007800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd\n{\n\tTMPQ2 = Rm_VPR128.16B;\n\tTMPQ1 = Rn_VPR128.16B;\n\t# simd shuffle Rd_VPR128.16B = TMPQ1 (@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14) lane size 1\n\tRd_VPR128.16B[0,8] = TMPQ1[64,8];\n\tRd_VPR128.16B[16,8] = TMPQ1[72,8];\n\tRd_VPR128.16B[32,8] = TMPQ1[80,8];\n\tRd_VPR128.16B[48,8] = TMPQ1[88,8];\n\tRd_VPR128.16B[64,8] = TMPQ1[96,8];\n\tRd_VPR128.16B[80,8] = TMPQ1[104,8];\n\tRd_VPR128.16B[96,8] = TMPQ1[112,8];\n\tRd_VPR128.16B[112,8] = TMPQ1[120,8];\n\t# simd shuffle Rd_VPR128.16B = TMPQ2 (@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15) lane size 1\n\tRd_VPR128.16B[8,8] = TMPQ2[64,8];\n\tRd_VPR128.16B[24,8] = TMPQ2[72,8];\n\tRd_VPR128.16B[40,8] = TMPQ2[80,8];\n\tRd_VPR128.16B[56,8] = TMPQ2[88,8];\n\tRd_VPR128.16B[72,8] = TMPQ2[96,8];\n\tRd_VPR128.16B[88,8] = TMPQ2[104,8];\n\tRd_VPR128.16B[104,8] = TMPQ2[112,8];\n\tRd_VPR128.16B[120,8] = TMPQ2[120,8];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x4ec07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@8\n# AUNIT --inst x4ec07800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd\n{\n\tTMPQ2 = Rm_VPR128.2D;\n\tTMPQ1 = Rn_VPR128.2D;\n\t# simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8\n\tRd_VPR128.2D[0,64] = TMPQ1[64,64];\n\t# simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8\n\tRd_VPR128.2D[64,64] = TMPQ2[64,64];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x0e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4\n# AUNIT --inst x0e807800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd\n{\n\tTMPD2 = Rm_VPR64.2S;\n\tTMPD1 = Rn_VPR64.2S;\n\t# simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4\n\tRd_VPR64.2S[0,32] = TMPD1[32,32];\n\t# simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4\n\tRd_VPR64.2S[32,32] = TMPD2[32,32];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x0e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:2 swap &=$shuffle@2-1@3-3:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2\n# AUNIT --inst x0e407800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd\n{\n\tTMPD2 = Rm_VPR64.4H;\n\tTMPD1 = Rn_VPR64.4H;\n\t# simd shuffle Rd_VPR64.4H = TMPD1 (@2-0@3-2) lane size 2\n\tRd_VPR64.4H[0,16] = TMPD1[32,16];\n\tRd_VPR64.4H[32,16] = TMPD1[48,16];\n\t# simd shuffle Rd_VPR64.4H = TMPD2 (@2-1@3-3) lane size 2\n\tRd_VPR64.4H[16,16] = TMPD2[32,16];\n\tRd_VPR64.4H[48,16] = TMPD2[48,16];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x4e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:4 swap &=$shuffle@2-1@3-3:4\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4\n# AUNIT --inst x4e807800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd\n{\n\tTMPQ2 = Rm_VPR128.4S;\n\tTMPQ1 = Rn_VPR128.4S;\n\t# simd shuffle Rd_VPR128.4S = TMPQ1 (@2-0@3-2) lane size 4\n\tRd_VPR128.4S[0,32] = TMPQ1[64,32];\n\tRd_VPR128.4S[64,32] = TMPQ1[96,32];\n\t# simd shuffle Rd_VPR128.4S = TMPQ2 (@2-1@3-3) lane size 4\n\tRd_VPR128.4S[32,32] = TMPQ2[64,32];\n\tRd_VPR128.4S[96,32] = TMPQ2[96,32];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x0e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:1 swap &=$shuffle@4-1@5-3@6-5@7-7:1\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1\n# AUNIT --inst x0e007800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B\nis b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd\n{\n\tTMPD2 = Rm_VPR64.8B;\n\tTMPD1 = Rn_VPR64.8B;\n\t# simd shuffle Rd_VPR64.8B = TMPD1 (@4-0@5-2@6-4@7-6) lane size 1\n\tRd_VPR64.8B[0,8] = TMPD1[32,8];\n\tRd_VPR64.8B[16,8] = TMPD1[40,8];\n\tRd_VPR64.8B[32,8] = TMPD1[48,8];\n\tRd_VPR64.8B[48,8] = TMPD1[56,8];\n\t# simd shuffle Rd_VPR64.8B = TMPD2 (@4-1@5-3@6-5@7-7) lane size 1\n\tRd_VPR64.8B[8,8] = TMPD2[32,8];\n\tRd_VPR64.8B[24,8] = TMPD2[40,8];\n\tRd_VPR64.8B[40,8] = TMPD2[48,8];\n\tRd_VPR64.8B[56,8] = TMPD2[56,8];\n\tzext_zd(Zd); # zero upper 24 bytes of Zd\n}\n\n# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00\n# CONSTRUCT x4e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:2 swap &=$shuffle@4-1@5-3@6-5@7-7:2\n# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2\n# AUNIT --inst x4e407800/mask=xffe0fc00 --status pass\n\n:zip2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd\n{\n\tTMPQ2 = Rm_VPR128.8H;\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd shuffle Rd_VPR128.8H = TMPQ1 (@4-0@5-2@6-4@7-6) lane size 2\n\tRd_VPR128.8H[0,16] = TMPQ1[64,16];\n\tRd_VPR128.8H[32,16] = TMPQ1[80,16];\n\tRd_VPR128.8H[64,16] = TMPQ1[96,16];\n\tRd_VPR128.8H[96,16] = TMPQ1[112,16];\n\t# simd shuffle Rd_VPR128.8H = TMPQ2 (@4-1@5-3@6-5@7-7) lane size 2\n\tRd_VPR128.8H[16,16] = TMPQ2[64,16];\n\tRd_VPR128.8H[48,16] = TMPQ2[80,16];\n\tRd_VPR128.8H[80,16] = TMPQ2[96,16];\n\tRd_VPR128.8H[112,16] = TMPQ2[112,16];\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n\n# C7.2.13 BFCVT page C7-2037 line 118954 MATCH x1e634000/mask=xfffffc00\n# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00\n# CONSTRUCT x1e634000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES\n# x1e634000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# SMACRO ARG1 ARG2 =float2float/1\n# SMACRO(pseudo) ARG1 ARG2 =NEON_bfcvt/1\n# b_0031=0001111001100011010000..........\n:bfcvt Rd_FPR16, Rn_FPR32\nis b_1031=0b0001111001100011010000 & Rd_FPR16 & Rn_FPR32 & Zd\n{\n\tRd_FPR16 = float2float(Rn_FPR32);\n\tzext_zh(Zd); # zero upper 30 bytes of Zd\n}\n\n# C7.2.14 BFCVTN, BFCVTN2 page C7-2038 line 119011 MATCH x0ea16800/mask=xbffffc00\n# CONSTRUCT x0ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# SMACRO ARG1 ARG2 =var =$float2float@4:8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4\n# b_0031=0.00111010100001011010..........\n\n:bfcvtn Rd_VPR128.4S, Rn_VPR128.4H\nis b_3131=0b0 & Q=0 & b_1029=0b00111010100001011010 & Rn_VPR128.4H & Rd_VPR128.4S & Zd\n{\n\tTMPQ1 = Rn_VPR128.4H;\n\t# simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4)\n\tRd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]);\n\tRd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]);\n\tRd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]);\n\tRd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.14 BFCVTN, BFCVTN2 page C7-2038 line 119011 MATCH x0ea16800/mask=xbffffc00\n# CONSTRUCT x4ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES\n# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# SMACRO ARG1 ARG2 =var =$float2float@4:8\n# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4\n\n:bfcvtn2 Rd_VPR128.4S, Rn_VPR128.8H\nis b_3131=0b0 & Q=1 & b_1029=0b00111010100001011010 & Rn_VPR128.8H & Rd_VPR128.4S & Zd\n{\n\tTMPQ1 = Rn_VPR128.8H;\n\t# simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4)\n\tRd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]);\n\tRd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]);\n\tRd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]);\n\tRd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]);\n\tzext_zq(Zd); # zero upper 16 bytes of Zd\n}\n\n# C7.2.15 BFDOT (by element) page C7-2039 line 119080 MATCH x0f40f000/mask=xbfc0f400\n# CONSTRUCT x0f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# x0f40f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.00111101......1111.0..........\n\n:bfdot Rd_VPR128.2S, Rn_VPR128.4H, , Re_VPR128.H.vIndexHL\nis b_3131=0b0 & Q=0 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.4H & Rd_VPR128.2S\n{\n\tRd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Re_VPR128.H.vIndexHL);\n}\n\n# C7.2.15 BFDOT (by element) page C7-2039 line 119080 MATCH x0f40f000/mask=xbfc0f400\n# CONSTRUCT x4f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n\n:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128.H.vIndexHL\nis b_3131=0b0 & Q=1 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Re_VPR128.H.vIndexHL);\n}\n\n# C7.2.16 BFDOT (vector) page C7-2041 line 119201 MATCH x2e40fc00/mask=xbfe0fc00\n# CONSTRUCT x2e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# x2e40fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.101110010.....111111..........\n\n:bfdot Rd_VPR128.2S, Rn_VPR128.4H, Rm_VPR128.4H\nis b_3131=0b0 & Q=0 & b_2129=0b101110010 & Rm_VPR128.4H & b_1015=0b111111 & Rn_VPR128.4H & Rd_VPR128.2S\n{\n\tRd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Rm_VPR128.4H);\n}\n\n# C7.2.16 BFDOT (vector) page C7-2041 line 119201 MATCH x2e40fc00/mask=xbfe0fc00\n# CONSTRUCT x6e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0b0 & Q=1 & b_2129=0b101110010 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Rm_VPR128.8H);\n}\n\n# C7.2.17 BFMLALB, BFMLALT (by element) page C7-2043 line 119316 MATCH x0fc0f000/mask=xbfc0f400\n# CONSTRUCT x0fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# x0fc0f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.00111111......1111.0..........\n\n:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0b0 & Q=0 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM);\n}\n\n# C7.2.17 BFMLALB, BFMLALT (by element) page C7-2043 line 119316 MATCH x0fc0f000/mask=xbfc0f400\n# CONSTRUCT x4fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n\n:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM\nis b_3131=0b0 & Q=1 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM);\n}\n\n# C7.2.18 BFMLALB, BFMLALT (vector) page C7-2045 line 119401 MATCH x2ec0fc00/mask=xbfe0fc00\n# CONSTRUCT x2ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# x2ec0fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.101110110.....111111..........\n\n:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0b0 & Q=0 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);\n}\n\n# C7.2.18 BFMLALB, BFMLALT (vector) page C7-2045 line 119401 MATCH x2ec0fc00/mask=xbfe0fc00\n# CONSTRUCT x6ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_3131=0b0 & Q=1 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);\n}\n\n# C7.2.19 BFMMLA page C7-2046 line 119472 MATCH x6e40ec00/mask=xffe0fc00\n# CONSTRUCT x6e40ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# x6e40ec00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=01101110010.....111011..........\n\n:bfmmla Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H\nis b_2131=0b01101110010 & Rm_VPR128.8H & b_1015=0b111011 & Rn_VPR128.8H & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_bfmmla(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);\n}\n\n# C7.2.147 FRINT32X (vector) page C7-2353 line 137678 MATCH x2e21e800/mask=xbfbffc00\n# CONSTRUCT x2e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x2e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.1011100.100001111010..........\n\n:frint32x Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0b0 & Q=0 & b_2329=0b1011100 & b_22=0 & b_1021=0b100001111010 & Rn_VPR64.2S & Rd_VPR64.2S\n{\n\tRd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);\n}\n\n:frint32x Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0b0 & Q=1 & b_2329=0b1011100 & b_22=0 & b_1021=0b100001111010 & Rn_VPR128.4S & Rd_VPR128.4S\n{\n\tRd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);\n}\n\n:frint32x Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0b0 & Q=1 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001111010 & Rn_VPR128.2D & Rd_VPR128.2D\n{\n\tlocal result:4 = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[0,64] = zext(result);\n\tresult = trunc(Rn_VPR128.2D[64,64]);\n\tRd_VPR128.2D[64,64] = zext(result);\n}\n\n# C7.2.148 FRINT32X (scalar) page C7-2355 line 137767 MATCH x1e28c000/mask=xffbffc00\n# CONSTRUCT x1e28c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x1e28c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=000111100.101000110000..........\n\n:frint32x Rd_FPR32, Rn_FPR32\nis b_2331=0b000111100 & b_22=0 & b_1021=0b101000110000 & Rn_FPR32 & Rd_FPR32\n{\n\tRd_FPR32 = trunc(Rn_FPR32);\n}\n\n:frint32x Rd_FPR64, Rn_FPR64\nis b_2331=0b000111100 & b_22=1 & b_1021=0b101000110000 & Rn_FPR64 & Rd_FPR64\n{\n\tlocal result:4 = trunc(Rn_FPR64);\n\tRd_FPR64 = zext(result);\n}\n\n# C7.2.149 FRINT32Z (vector) page C7-2357 line 137862 MATCH x0e21e800/mask=xbfbffc00\n# CONSTRUCT x0e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x0e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.0011100.100001111010..........\n\n:frint32z Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0b0 & Q=0 & b_2329=0b0011100 & b_22=0 & b_1021=0b100001111010 & Rn_VPR64.2S & Rd_VPR64.2S\n{\n\tRd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);\n}\n\n:frint32z Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0b0 & Q=1 & b_2329=0b0011100 & b_22=0 & b_1021=0b100001111010 & Rn_VPR128.4S & Rd_VPR128.4S\n{\n\tRd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);\n}\n\n:frint32z Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0b0 & Q=1 & b_2329=0b0011100 & b_22=1 & b_1021=0b100001111010 & Rn_VPR128.2D & Rd_VPR128.2D\n{\n\tlocal result:4 = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[0,64] = zext(result);\n\tresult = trunc(Rn_VPR128.2D[64,64]);\n\tRd_VPR128.2D[64,64] = zext(result);\n}\n\n# C7.2.150 FRINT32Z (scalar) page C7-2359 line 137950 MATCH x1e284000/mask=xffbffc00\n# CONSTRUCT x1e284000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x1e284000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=000111100.101000010000..........\n\n:frint32z Rd_FPR32, Rn_FPR32\nis b_2331=0b000111100 & b_22=0 & b_1021=0b101000010000 & Rn_FPR32 & Rd_FPR32\n{\n\tRd_FPR32 = trunc(Rn_FPR32);\n}\n\n:frint32z Rd_FPR64, Rn_FPR64\nis b_2331=0b000111100 & b_22=1 & b_1021=0b101000010000 & Rn_FPR64 & Rd_FPR64\n{\n\tlocal result:4 = trunc(Rn_FPR64);\n\tRd_FPR64 = zext(result);\n}\n\n# C7.2.151 FRINT64X (vector) page C7-2361 line 138043 MATCH x2e21f800/mask=xbfbffc00\n# CONSTRUCT x2e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x2e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.1011100.100001111110..........\n\n:frint64x Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0b0 & Q=0 & b_2329=0b1011100 & b_22=0 & b_1021=0b100001111110 & Rn_VPR64.2S & Rd_VPR64.2S\n{\n\tlocal result:8 = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[0,32] = result[0,32];\n\tresult = trunc(Rn_VPR64.2S[32,32]);\n\tRd_VPR64.2S[32,32] = result[0,32];\n}\n\n:frint64x Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0b0 & Q=1 & b_2329=0b1011100 & b_22=0 & b_1021=0b100001111110 & Rn_VPR128.4S & Rd_VPR128.4S\n{\n\tlocal result:8 = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[0,32] = result[0,32];\n\tresult = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[32,32] = result[0,32];\n\tresult = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[64,32] = result[0,32];\n\tresult = trunc(Rn_VPR128.4S[96,32]);\n\tRd_VPR128.4S[96,32] = result[0,32];\n}\n\n:frint64x Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0b0 & Q=1 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001111110 & Rn_VPR128.2D & Rd_VPR128.2D\n{\n\tRd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);\n}\n\n# C7.2.152 FRINT64X (scalar) page C7-2363 line 138132 MATCH x1e29c000/mask=xffbffc00\n# CONSTRUCT x1e29c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x1e29c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=000111100.101001110000..........\n\n:frint64x Rd_FPR32, Rn_FPR32\nis b_2331=0b000111100 & b_22=0 & b_1021=0b101001110000 & Rn_FPR32 & Rd_FPR32\n{\n\tlocal result:8 = trunc(Rn_FPR32);\n\tRd_FPR32 = result[0,32];\n}\n\n:frint64x Rd_FPR64, Rn_FPR64\nis b_2331=0b000111100 & b_22=1 & b_1021=0b101001110000 & Rn_FPR64 & Rd_FPR64\n{\n\tRd_FPR64 = trunc(Rn_FPR64);\n}\n\n# C7.2.153 FRINT64Z (vector) page C7-2365 line 138227 MATCH x0e21f800/mask=xbfbffc00\n# CONSTRUCT x0e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x0e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.0011100.100001111110..........\n\n:frint64z Rd_VPR64.2S, Rn_VPR64.2S\nis b_3131=0b0 & Q=0 & b_2329=0b0011100 & b_22=0 & b_1021=0b100001111110 & Rn_VPR64.2S & Rd_VPR64.2S\n{\n\tlocal result:8 = trunc(Rn_VPR64.2S[0,32]);\n\tRd_VPR64.2S[0,32] = result[0,32];\n\tresult = trunc(Rn_VPR64.2S[32,32]);\n\tRd_VPR64.2S[32,32] = result[0,32];\n}\n\n:frint64z Rd_VPR128.4S, Rn_VPR128.4S\nis b_3131=0b0 & Q=1 & b_2329=0b0011100 & b_22=0 & b_1021=0b100001111110 & Rn_VPR128.4S & Rd_VPR128.4S\n{\n\tlocal result:8 = trunc(Rn_VPR128.4S[0,32]);\n\tRd_VPR128.4S[0,32] = result[0,32];\n\tresult = trunc(Rn_VPR128.4S[32,32]);\n\tRd_VPR128.4S[32,32] = result[0,32];\n\tresult = trunc(Rn_VPR128.4S[64,32]);\n\tRd_VPR128.4S[64,32] = result[0,32];\n\tresult = trunc(Rn_VPR128.4S[96,32]);\n\tRd_VPR128.4S[96,32] = result[0,32];\n}\n\n:frint64z Rd_VPR128.2D, Rn_VPR128.2D\nis b_3131=0b0 & Q=1 & b_2329=0b0011100 & b_22=1 & b_1021=0b100001111110 & Rn_VPR128.2D & Rd_VPR128.2D\n{\n\tRd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);\n\tRd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);\n}\n\n# C7.2.154 FRINT64Z (scalar) page C7-2367 line 138315 MATCH x1e294000/mask=xffbffc00\n# CONSTRUCT x1e294000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES\n# x1e294000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=000111100.101001010000..........\n\n:frint64z Rd_FPR32, Rn_FPR32\nis b_2331=0b000111100 & b_22=0 & b_1021=0b101001010000 & Rn_FPR32 & Rd_FPR32\n{\n\tlocal result:8 = trunc(Rn_FPR32);\n\tRd_FPR32 = result[0,32];\n}\n\n:frint64z Rd_FPR64, Rn_FPR64\nis b_2331=0b000111100 & b_22=1 & b_1021=0b101001010000 & Rn_FPR64 & Rd_FPR64\n{\n\tRd_FPR64 = trunc(Rn_FPR64);\n}\n\n# C7.2.278 SMMLA (vector) page C7-2634 line 153703 MATCH x4e80a400/mask=xffe0fc00\n# CONSTRUCT x4e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# x4e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=01001110100.....101001..........\n\n:smmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B\nis b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_smmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B);\n}\n\n# C7.2.336 SUDOT (by element) page C7-2795 line 163341 MATCH x0f00f000/mask=xbfc0f400\n# CONSTRUCT x0f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# x0f00f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.00111100......1111.0..........\n\n:sudot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL\nis b_3131=0b0 & Q=0 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S\n{\n\tRd_VPR128.2S = NEON_sudot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL);\n}\n\n# C7.2.336 SUDOT (by element) page C7-2795 line 163341 MATCH x0f00f000/mask=xbfc0f400\n# CONSTRUCT x4f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n\n:sudot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL\nis b_3131=0b0 & Q=1 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_sudot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL);\n}\n\n# C7.2.370 UMMLA (vector) page C7-2867 line 167357 MATCH x6e80a400/mask=xffe0fc00\n# CONSTRUCT x6e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# x6e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_ummla/3@1\n# b_0031=01101110100.....101001..........\n:ummla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B\nis b_2131=0b01101110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_ummla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n\n# C7.2.388 USDOT (vector) page C7-2907 line 169709 MATCH x0e809c00/mask=xbfe0fc00\n# CONSTRUCT x0e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# x0e809c00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.001110100.....100111..........\n\n:usdot Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B\nis b_3131=0b0 & Q=0 & b_2129=0b001110100 & Rm_VPR128.8B & b_1015=0b100111 & Rn_VPR128.8B & Rd_VPR128.2S\n{\n\tRd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B);\n}\n\n# C7.2.388 USDOT (vector) page C7-2907 line 169709 MATCH x0e809c00/mask=xbfe0fc00\n# CONSTRUCT x4e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n\n:usdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B\nis b_3131=0b0 & Q=1 & b_2129=0b001110100 & Rn_VPR128.16B & b_1015=0b100111 & Rm_VPR128.16B & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B);\n}\n\n# C7.2.389 USDOT (by element) page C7-2909 line 169795 MATCH x0f80f000/mask=xbfc0f400\n# CONSTRUCT x0f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n# x0f80f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=0.00111110......1111.0..........\n\n:usdot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL\nis b_3131=0b0 & Q=0 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S\n{\n\tRd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL);\n}\n\n# C7.2.389 USDOT (by element) page C7-2909 line 169795 MATCH x0f80f000/mask=xbfc0f400\n# CONSTRUCT x4f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES\n\n:usdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL\nis b_3131=0b0 & Q=1 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL);\n}\n\n# C7.2.393 USMMLA (vector) page C7-2919 line 170338 MATCH x4e80ac00/mask=xffe0fc00\n# CONSTRUCT x4e80ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES\n# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_usmmla/3@1\n# x4e80ac00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=01001110100.....101011..........\n:usmmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B\nis b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101011 & Rn_VPR128.16B & Rd_VPR128.4S\n{\n\tRd_VPR128.4S = NEON_usmmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);\n}\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AARCH64sve.sinc", "content": "# INFO This file automatically generated by andre on Mon Apr 30 14:51:39 2018\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['../../../ProcessorTest/test/andre/scrape/sveit.py', '--sinc']\n\n# abs_z_p_z.xml: ABS variant SVE\n# PATTERN x0416a000/mask=xff3fe000\n\n:abs Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_abs(Zd.T, Pg3_m, Zn.T);\n}\n\n# add_z_p_zz.xml: ADD (vectors, predicated) variant SVE\n# PATTERN x04000000/mask=xff3fe000\n\n:add Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_add(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# add_z_zi.xml: ADD (immediate) variant SVE\n# PATTERN x2520c000/mask=xff3fc000\n\n:add Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_add(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# add_z_zz.xml: ADD (vectors, unpredicated) variant SVE\n# PATTERN x04200000/mask=xff20fc00\n\n:add Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_add(Zd.T, Zn.T, Zm.T);\n}\n\n# addpl_r_ri.xml: ADDPL variant SVE\n# PATTERN x04605000/mask=xffe0f800\n\n:addpl Rd_GPR64xsp, Rm_GPR64xsp, \"#\"^sve_imm6_1_m32to31\nis sve_b_2331=0b000001000 & sve_b_22=1 & sve_b_21=1 & sve_rn_1620 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & Rd_GPR64xsp & Rm_GPR64xsp & sve_imm6_1_m32to31\n{\n\tRd_GPR64xsp = SVE_addpl(Rd_GPR64xsp, Rm_GPR64xsp, sve_imm6_1_m32to31:1);\n}\n\n# addvl_r_ri.xml: ADDVL variant SVE\n# PATTERN x04205000/mask=xffe0f800\n\n:addvl Rd_GPR64xsp, Rm_GPR64xsp, \"#\"^sve_imm6_1_m32to31\nis sve_b_2331=0b000001000 & sve_b_22=0 & sve_b_21=1 & sve_rn_1620 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & Rd_GPR64xsp & Rm_GPR64xsp & sve_imm6_1_m32to31\n{\n\tRd_GPR64xsp = SVE_addvl(Rd_GPR64xsp, Rm_GPR64xsp, sve_imm6_1_m32to31:1);\n}\n\n# adr_z_az.xml: ADR variant Packed offsets\n# PATTERN x04a0a000/mask=xffa0f000\n\n:adr Zd.T_sz, [Zn.T_sz, Zm.T_sz^sve_mod_amount]\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & sve_mod_amount & Zm.T_sz & Zd.T_sz & Zn.T_sz\n{\n\tZd.T_sz = SVE_adr(Zd.T_sz, Zn.T_sz, Zm.T_sz, sve_mod_amount:1);\n}\n\n# adr_z_az.xml: ADR variant Unpacked 32-bit signed offsets\n# PATTERN x0420a000/mask=xffe0f000\n\n:adr Zd.D, [Zn.D, Zm.D, \"sxtw\"^sve_msz_1011]\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D\n{\n\tZd.D = SVE_adr(Zd.D, Zn.D, Zm.D, sve_msz_1011:1);\n}\n\n# adr_z_az.xml: ADR variant Unpacked 32-bit unsigned offsets\n# PATTERN x0460a000/mask=xffe0f000\n\n:adr Zd.D, [Zn.D, Zm.D, \"uxtw\"^sve_msz_1011]\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D\n{\n\tZd.D = SVE_adr(Zd.D, Zn.D, Zm.D, sve_msz_1011:1);\n}\n\n# and_p_p_pp.xml: AND, ANDS (predicates) variant Flag setting\n# PATTERN x25404000/mask=xfff0c210\n\n:ands Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_s_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_ands(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# and_p_p_pp.xml: AND, ANDS (predicates) variant Not flag setting\n# PATTERN x25004000/mask=xfff0c210\n\n:and Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_s_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_and(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# and_z_p_zz.xml: AND (vectors, predicated) variant SVE\n# PATTERN x041a0000/mask=xff3fe000\n\n:and Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_and(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# and_z_zi.xml: AND (immediate) variant SVE\n# PATTERN x05800000/mask=xfffc0000\n\n:and Zd.T_imm13, Zd.T_imm13_2, \"#\"^sve_decode_bit_mask\nis sve_b_2431=0b00000101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2\n{\n\tZd.T_imm13 = SVE_and(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1);\n}\n\n# and_z_zz.xml: AND (vectors, unpredicated) variant SVE\n# PATTERN x04203000/mask=xffe0fc00\n\n:and Zd.D, Zn.D, Zm.D\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D\n{\n\tZd.D = SVE_and(Zd.D, Zn.D, Zm.D);\n}\n\n# andv_r_p_z.xml: ANDV variant SVE\n# PATTERN x041a2000/mask=xff3fe000\n\n:andv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_andv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# andv_r_p_z.xml: ANDV variant SVE\n# PATTERN x041a2000/mask=xff3fe000\n\n:andv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_andv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# andv_r_p_z.xml: ANDV variant SVE\n# PATTERN x041a2000/mask=xff3fe000\n\n:andv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_andv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# andv_r_p_z.xml: ANDV variant SVE\n# PATTERN x041a2000/mask=xff3fe000\n\n:andv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_andv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# asr_z_p_zi.xml: ASR (immediate, predicated) variant SVE\n# PATTERN x04008000/mask=xff3fe000\n\n:asr Zd.T_tszh, Pg3_m, Zd.T_tszh_2, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m\n{\n\tZd.T_tszh = SVE_asr(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1);\n}\n\n# asr_z_p_zw.xml: ASR (wide elements, predicated) variant SVE\n# PATTERN x04188000/mask=xff3fe000\n\n:asr Zd.T, Pg3_m, Zd.T_2, Zn.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D\n{\n\tZd.T = SVE_asr(Zd.T, Pg3_m, Zd.T_2, Zn.D);\n}\n\n# asr_z_p_zz.xml: ASR (vectors) variant SVE\n# PATTERN x04108000/mask=xff3fe000\n\n:asr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_asr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# asr_z_zi.xml: ASR (immediate, unpredicated) variant SVE\n# PATTERN x04209000/mask=xff20fc00\n\n:asr Zd.T_tszh, Zn.T_tszh, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=0 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh\n{\n\tZd.T_tszh = SVE_asr(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1);\n}\n\n# asr_z_zw.xml: ASR (wide elements, unpredicated) variant SVE\n# PATTERN x04208000/mask=xff20fc00\n\n:asr Zd.T, Zn.T, Zm.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=0 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D\n{\n\tZd.T = SVE_asr(Zd.T, Zn.T, Zm.D);\n}\n\n# asrd_z_p_zi.xml: ASRD variant SVE\n# PATTERN x04048000/mask=xff3fe000\n\n:asrd Zd.T_tszh, Pg3_m, Zd.T_tszh_2, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m\n{\n\tZd.T_tszh = SVE_asrd(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1);\n}\n\n# asrr_z_p_zz.xml: ASRR variant SVE\n# PATTERN x04148000/mask=xff3fe000\n\n:asrr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_asrr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# bic_and_z_zi.xml: BIC (immediate) variant SVE\n# ALIASEDBY AND ., ., #(- - 1) if Never\n# PATTERN x05800000/mask=xfffc0000\n\n# SKIPPING bic_and_z_zi.xml because x05800000/mask=xfffc0000 has already been defined\n\n# bic_p_p_pp.xml: BIC, BICS (predicates) variant Flag setting\n# PATTERN x25404010/mask=xfff0c210\n\n:bics Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_bics(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# bic_p_p_pp.xml: BIC, BICS (predicates) variant Not flag setting\n# PATTERN x25004010/mask=xfff0c210\n\n:bic Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_bic(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# bic_z_p_zz.xml: BIC (vectors, predicated) variant SVE\n# PATTERN x041b0000/mask=xff3fe000\n\n:bic Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_bic(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# bic_z_zz.xml: BIC (vectors, unpredicated) variant SVE\n# PATTERN x04e03000/mask=xffe0fc00\n\n:bic Zd.D, Zn.D, Zm.D\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D\n{\n\tZd.D = SVE_bic(Zd.D, Zn.D, Zm.D);\n}\n\n# brka_p_p_p.xml: BRKA, BRKAS variant Flag setting\n# PATTERN x25504000/mask=xffffc210\n\n:brkas Pd.B, Pg_z, Pn.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B\n{\n\tPd.B = SVE_brkas(Pd.B, Pg_z, Pn.B);\n}\n\n# brka_p_p_p.xml: BRKA, BRKAS variant Not flag setting\n# PATTERN x25104000/mask=xffffc200\n\n:brka Pd.B, Pg_zm, Pn.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_m_04 & sve_pd_0003 & Pg_zm & Pd.B & Pn.B\n{\n\tPd.B = SVE_brka(Pd.B, Pg_zm, Pn.B);\n}\n\n# brkb_p_p_p.xml: BRKB, BRKBS variant Flag setting\n# PATTERN x25d04000/mask=xffffc210\n\n:brkbs Pd.B, Pg_z, Pn.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B\n{\n\tPd.B = SVE_brkbs(Pd.B, Pg_z, Pn.B);\n}\n\n# brkb_p_p_p.xml: BRKB, BRKBS variant Not flag setting\n# PATTERN x25904000/mask=xffffc200\n\n:brkb Pd.B, Pg_zm, Pn.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_m_04 & sve_pd_0003 & Pg_zm & Pd.B & Pn.B\n{\n\tPd.B = SVE_brkb(Pd.B, Pg_zm, Pn.B);\n}\n\n# brkn_p_p_pp.xml: BRKN, BRKNS variant Flag setting\n# PATTERN x25584000/mask=xffffc210\n\n:brkns Pd.B, Pg_z, Pn.B, Pd.B_2\nis sve_b_2331=0b001001010 & sve_b_22=1 & sve_b_1421=0b01100001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pdm_0003 & Pd.B & Pd.B_2 & Pg_z & Pn.B\n{\n\tPd.B = SVE_brkns(Pd.B, Pg_z, Pn.B, Pd.B_2);\n}\n\n# brkn_p_p_pp.xml: BRKN, BRKNS variant Not flag setting\n# PATTERN x25184000/mask=xffffc210\n\n:brkn Pd.B, Pg_z, Pn.B, Pd.B_2\nis sve_b_2331=0b001001010 & sve_b_22=0 & sve_b_1421=0b01100001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pdm_0003 & Pd.B & Pd.B_2 & Pg_z & Pn.B\n{\n\tPd.B = SVE_brkn(Pd.B, Pg_z, Pn.B, Pd.B_2);\n}\n\n# brkpa_p_p_pp.xml: BRKPA, BRKPAS variant Flag setting\n# PATTERN x2540c000/mask=xfff0c210\n\n:brkpas Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_brkpas(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# brkpa_p_p_pp.xml: BRKPA, BRKPAS variant Not flag setting\n# PATTERN x2500c000/mask=xfff0c210\n\n:brkpa Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_brkpa(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# brkpb_p_p_pp.xml: BRKPB, BRKPBS variant Flag setting\n# PATTERN x2540c010/mask=xfff0c210\n\n:brkpbs Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_brkpbs(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# brkpb_p_p_pp.xml: BRKPB, BRKPBS variant Not flag setting\n# PATTERN x2500c010/mask=xfff0c210\n\n:brkpb Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_brkpb(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# clasta_r_p_z.xml: CLASTA (scalar) variant SVE\n# PATTERN x0530a000/mask=xff3fe000\n\n:clasta Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b11000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR64 & Rd_GPR64_2 & Pg3\n{\n\tRd_GPR64 = SVE_clasta(Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T);\n}\n\n# clasta_r_p_z.xml: CLASTA (scalar) variant SVE\n# PATTERN x0530a000/mask=xff3fe000\n\n:clasta Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b11000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR32 & Rd_GPR32_2 & Pg3\n{\n\tRd_GPR32 = SVE_clasta(Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T);\n}\n\n# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE\n# PATTERN x052a8000/mask=xff3fe000\n\n:clasta Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3\n{\n\tRd_FPR8 = SVE_clasta(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T);\n}\n\n# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE\n# PATTERN x052a8000/mask=xff3fe000\n\n:clasta Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3\n{\n\tRd_FPR32 = SVE_clasta(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T);\n}\n\n# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE\n# PATTERN x052a8000/mask=xff3fe000\n\n:clasta Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3\n{\n\tRd_FPR16 = SVE_clasta(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T);\n}\n\n# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE\n# PATTERN x052a8000/mask=xff3fe000\n\n:clasta Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3\n{\n\tRd_FPR64 = SVE_clasta(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T);\n}\n\n# clasta_z_p_zz.xml: CLASTA (vectors) variant SVE\n# PATTERN x05288000/mask=xff3fe000\n\n:clasta Zd.T, Pg3, Zd.T_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1721=0b10100 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3\n{\n\tZd.T = SVE_clasta(Zd.T, Pg3, Zd.T_2, Zn.T);\n}\n\n# clastb_r_p_z.xml: CLASTB (scalar) variant SVE\n# PATTERN x0531a000/mask=xff3fe000\n\n:clastb Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b11000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR64 & Rd_GPR64_2 & Pg3\n{\n\tRd_GPR64 = SVE_clastb(Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T);\n}\n\n# clastb_r_p_z.xml: CLASTB (scalar) variant SVE\n# PATTERN x0531a000/mask=xff3fe000\n\n:clastb Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b11000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR32 & Rd_GPR32_2 & Pg3\n{\n\tRd_GPR32 = SVE_clastb(Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T);\n}\n\n# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE\n# PATTERN x052b8000/mask=xff3fe000\n\n:clastb Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3\n{\n\tRd_FPR8 = SVE_clastb(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T);\n}\n\n# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE\n# PATTERN x052b8000/mask=xff3fe000\n\n:clastb Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3\n{\n\tRd_FPR32 = SVE_clastb(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T);\n}\n\n# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE\n# PATTERN x052b8000/mask=xff3fe000\n\n:clastb Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3\n{\n\tRd_FPR16 = SVE_clastb(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T);\n}\n\n# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE\n# PATTERN x052b8000/mask=xff3fe000\n\n:clastb Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3\n{\n\tRd_FPR64 = SVE_clastb(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T);\n}\n\n# clastb_z_p_zz.xml: CLASTB (vectors) variant SVE\n# PATTERN x05298000/mask=xff3fe000\n\n:clastb Zd.T, Pg3, Zd.T_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1721=0b10100 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3\n{\n\tZd.T = SVE_clastb(Zd.T, Pg3, Zd.T_2, Zn.T);\n}\n\n# cls_z_p_z.xml: CLS variant SVE\n# PATTERN x0418a000/mask=xff3fe000\n\n:cls Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_cls(Zd.T, Pg3_m, Zn.T);\n}\n\n# clz_z_p_z.xml: CLZ variant SVE\n# PATTERN x0419a000/mask=xff3fe000\n\n:clz Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_clz(Zd.T, Pg3_m, Zn.T);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Equal\n# PATTERN x25008000/mask=xff20e010\n\n:cmpeq Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm5s_1620\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620\n{\n\tPd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Greater than\n# PATTERN x25000010/mask=xff20e010\n\n:cmpgt Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm5s_1620\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620\n{\n\tPd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Greater than or equal\n# PATTERN x25000000/mask=xff20e010\n\n:cmpge Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm5s_1620\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620\n{\n\tPd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Higher\n# PATTERN x24200010/mask=xff202010\n\n:cmphi Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm7_1420\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Higher or same\n# PATTERN x24200000/mask=xff202010\n\n:cmphs Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm7_1420\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Less than\n# PATTERN x25002000/mask=xff20e010\n\n:cmplt Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm5s_1620\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620\n{\n\tPd.T = SVE_cmplt(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Less than or equal\n# PATTERN x25002010/mask=xff20e010\n\n:cmple Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm5s_1620\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620\n{\n\tPd.T = SVE_cmple(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Lower\n# PATTERN x24202000/mask=xff202010\n\n:cmplo Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm7_1420\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmplo(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Lower or same\n# PATTERN x24202010/mask=xff202010\n\n:cmpls Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm7_1420\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmpls(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);\n}\n\n# cmpeq_p_p_zi.xml: CMP (immediate) variant Not equal\n# PATTERN x25008010/mask=xff20e010\n\n:cmpne Pd.T, Pg3_z, Zn.T, \"#\"^sve_imm5s_1620\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620\n{\n\tPd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Equal\n# PATTERN x24002000/mask=xff20e010\n\n:cmpeq Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Greater than\n# PATTERN x24004010/mask=xff20e010\n\n:cmpgt Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Greater than or equal\n# PATTERN x24004000/mask=xff20e010\n\n:cmpge Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Higher\n# PATTERN x2400c010/mask=xff20e010\n\n:cmphi Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Higher or same\n# PATTERN x2400c000/mask=xff20e010\n\n:cmphs Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Less than\n# PATTERN x24006000/mask=xff20e010\n\n:cmplt Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmplt(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Less than or equal\n# PATTERN x24006010/mask=xff20e010\n\n:cmple Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmple(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Lower\n# PATTERN x2400e000/mask=xff20e010\n\n:cmplo Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmplo(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Lower or same\n# PATTERN x2400e010/mask=xff20e010\n\n:cmpls Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmpls(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zw.xml: CMP (wide elements) variant Not equal\n# PATTERN x24002010/mask=xff20e010\n\n:cmpne Pd.T, Pg3_z, Zn.T, Zm.D\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D\n{\n\tPd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, Zm.D);\n}\n\n# cmpeq_p_p_zz.xml: CMP (vectors) variant Equal\n# PATTERN x2400a000/mask=xff20e010\n\n:cmpeq Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# cmpeq_p_p_zz.xml: CMP (vectors) variant Greater than\n# PATTERN x24008010/mask=xff20e010\n\n:cmpgt Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# cmpeq_p_p_zz.xml: CMP (vectors) variant Greater than or equal\n# PATTERN x24008000/mask=xff20e010\n\n:cmpge Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# cmpeq_p_p_zz.xml: CMP (vectors) variant Higher\n# PATTERN x24000010/mask=xff20e010\n\n:cmphi Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# cmpeq_p_p_zz.xml: CMP (vectors) variant Higher or same\n# PATTERN x24000000/mask=xff20e010\n\n:cmphs Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# cmpeq_p_p_zz.xml: CMP (vectors) variant Not equal\n# PATTERN x2400a010/mask=xff20e010\n\n:cmpne Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# cmple_cmpeq_p_p_zz.xml: CMPLE (vectors) variant Greater than or equal\n# ALIASEDBY CMPGE ., /Z, ., . if Never\n# PATTERN x24008000/mask=xff20e010\n\n# SKIPPING cmple_cmpeq_p_p_zz.xml because x24008000/mask=xff20e010 has already been defined\n\n# cmplo_cmpeq_p_p_zz.xml: CMPLO (vectors) variant Higher\n# ALIASEDBY CMPHI ., /Z, ., . if Never\n# PATTERN x24000010/mask=xff20e010\n\n# SKIPPING cmplo_cmpeq_p_p_zz.xml because x24000010/mask=xff20e010 has already been defined\n\n# cmpls_cmpeq_p_p_zz.xml: CMPLS (vectors) variant Higher or same\n# ALIASEDBY CMPHS ., /Z, ., . if Never\n# PATTERN x24000000/mask=xff20e010\n\n# SKIPPING cmpls_cmpeq_p_p_zz.xml because x24000000/mask=xff20e010 has already been defined\n\n# cmplt_cmpeq_p_p_zz.xml: CMPLT (vectors) variant Greater than\n# ALIASEDBY CMPGT ., /Z, ., . if Never\n# PATTERN x24008010/mask=xff20e010\n\n# SKIPPING cmplt_cmpeq_p_p_zz.xml because x24008010/mask=xff20e010 has already been defined\n\n# cnot_z_p_z.xml: CNOT variant SVE\n# PATTERN x041ba000/mask=xff3fe000\n\n:cnot Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_cnot(Zd.T, Pg3_m, Zn.T);\n}\n\n# cnt_z_p_z.xml: CNT variant SVE\n# PATTERN x041aa000/mask=xff3fe000\n\n:cnt Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_cnt(Zd.T, Pg3_m, Zn.T);\n}\n\n# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Byte\n# PATTERN x0420e000/mask=xfff0fc00\n\n:cntb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_cntb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Doubleword\n# PATTERN x04e0e000/mask=xfff0fc00\n\n:cntd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_cntd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Halfword\n# PATTERN x0460e000/mask=xfff0fc00\n\n:cnth Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_cnth(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Word\n# PATTERN x04a0e000/mask=xfff0fc00\n\n:cntw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_cntw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# cntp_r_p_p.xml: CNTP variant SVE\n# PATTERN x25208000/mask=xff3fc200\n\n:cntp Rd_GPR64, Pg, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b10 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_rd_0004 & Pn.T & Rd_GPR64 & Pg\n{\n\tRd_GPR64 = SVE_cntp(Rd_GPR64, Pn.T, Pg);\n}\n\n# compact_z_p_z.xml: COMPACT variant SVE\n# PATTERN x05a18000/mask=xffbfe000\n\n:compact Zd.T_sz, Pg3, Zn.T_sz\nis sve_b_2331=0b000001011 & sve_sz_22 & sve_b_1321=0b100001100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T_sz & Zn.T_sz & Pg3\n{\n\tZd.T_sz = SVE_compact(Zd.T_sz, Pg3, Zn.T_sz);\n}\n\n# cpy_z_p_i.xml: CPY (immediate) variant SVE\n# PATTERN x05100000/mask=xff308000\n\n:cpy Zd.T, Pm_zm, sve_shf8_1_m128to127\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_15=0 & sve_m_14 & sve_sh_13 & sve_imm8_0512 & sve_zd_0004 & sve_shift_13 & Pm_zm & Zd.T & sve_imm8_1_m128to127 & sve_shf8_1_m128to127\n{\n\tZd.T = SVE_cpy(Zd.T, Pm_zm, sve_shf8_1_m128to127, sve_shift_13:1);\n}\n\n# cpy_z_p_r.xml: CPY (scalar) variant SVE\n# PATTERN x0528a000/mask=xff3fe000\n\n:cpy Zd.T, Pg3_m, Rn_GPR64xsp\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1321=0b101000101 & sve_pg_1012 & sve_rn_0509 & sve_zd_0004 & Rn_GPR64xsp & Zd.T & Pg3_m\n{\n\tZd.T = SVE_cpy(Zd.T, Pg3_m, Rn_GPR64xsp);\n}\n\n# cpy_z_p_r.xml: CPY (scalar) variant SVE\n# PATTERN x0528a000/mask=xff3fe000\n\n:cpy Zd.T, Pg3_m, Rn_GPR32xsp\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1321=0b101000101 & sve_pg_1012 & sve_rn_0509 & sve_zd_0004 & Rn_GPR32xsp & Zd.T & Pg3_m\n{\n\tZd.T = SVE_cpy(Zd.T, Pg3_m, Rn_GPR32xsp);\n}\n\n# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE\n# PATTERN x05208000/mask=xff3fe000\n\n:cpy Zd.T, Pg3_m, Rn_FPR8\nis sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR8 & Pg3_m\n{\n\tZd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR8);\n}\n\n# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE\n# PATTERN x05208000/mask=xff3fe000\n\n:cpy Zd.T, Pg3_m, Rn_FPR32\nis sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR32 & Pg3_m\n{\n\tZd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR32);\n}\n\n# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE\n# PATTERN x05208000/mask=xff3fe000\n\n:cpy Zd.T, Pg3_m, Rn_FPR16\nis sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR16 & Pg3_m\n{\n\tZd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR16);\n}\n\n# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE\n# PATTERN x05208000/mask=xff3fe000\n\n:cpy Zd.T, Pg3_m, Rn_FPR64\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR64 & Pg3_m\n{\n\tZd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR64);\n}\n\n# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Equal\n# PATTERN x25a02000/mask=xffa0fc1f\n\n:ctermeq Rn_GPR64, Rm_GPR64\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=1 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR64 & Rm_GPR64\n{\n\tSVE_ctermeq(Rn_GPR64, Rm_GPR64);\n}\n\n# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Equal\n# PATTERN x25a02000/mask=xffa0fc1f\n\n:ctermeq Rn_GPR32, Rm_GPR32\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=0 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR32 & Rm_GPR32\n{\n\tSVE_ctermeq(Rn_GPR32, Rm_GPR32);\n}\n\n# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Not equal\n# PATTERN x25a02010/mask=xffa0fc1f\n\n:ctermne Rn_GPR64, Rm_GPR64\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=1 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=1 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR64 & Rm_GPR64\n{\n\tSVE_ctermne(Rn_GPR64, Rm_GPR64);\n}\n\n# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Not equal\n# PATTERN x25a02010/mask=xffa0fc1f\n\n:ctermne Rn_GPR32, Rm_GPR32\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=0 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=1 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR32 & Rm_GPR32\n{\n\tSVE_ctermne(Rn_GPR32, Rm_GPR32);\n}\n\n# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Byte\n# PATTERN x0430e400/mask=xfff0fc00\n\n:decb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_decb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Doubleword\n# PATTERN x04f0e400/mask=xfff0fc00\n\n:decd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_decd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Halfword\n# PATTERN x0470e400/mask=xfff0fc00\n\n:dech Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_dech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Word\n# PATTERN x04b0e400/mask=xfff0fc00\n\n:decw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_decw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Doubleword\n# PATTERN x04f0c400/mask=xfff0fc00\n\n:decd Zd.D^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.D = SVE_decd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Halfword\n# PATTERN x0470c400/mask=xfff0fc00\n\n:dech Zd.H^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.H = SVE_dech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Word\n# PATTERN x04b0c400/mask=xfff0fc00\n\n:decw Zd.S^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.S = SVE_decw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# decp_r_p_r.xml: DECP (scalar) variant SVE\n# PATTERN x252d8800/mask=xff3ffe00\n\n:decp Rd_GPR64, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64\n{\n\tRd_GPR64 = SVE_decp(Rd_GPR64, Pn.T);\n}\n\n# decp_z_p_z.xml: DECP (vector) variant SVE\n# PATTERN x252d8000/mask=xff3ffe00\n\n:decp Zd.T, Pn\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn\n{\n\tZd.T = SVE_decp(Zd.T, Pn);\n}\n\n# dup_z_i.xml: DUP (immediate) variant SVE\n# PATTERN x2538c000/mask=xff3fc000\n\n:dup Zd.T, sve_shf8_1_m128to127\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b011 & sve_sh_13 & sve_imm8_0512 & sve_zd_0004 & sve_shift_13 & Zd.T & sve_imm8_1_m128to127 & sve_shf8_1_m128to127\n{\n\tZd.T = SVE_dup(Zd.T, sve_shf8_1_m128to127, sve_shift_13:1);\n}\n\n# dup_z_r.xml: DUP (scalar) variant SVE\n# PATTERN x05203800/mask=xff3ffc00\n\n:dup Zd.T, Rn_GPR64xsp\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b100000001110 & sve_rn_0509 & sve_zd_0004 & Rn_GPR64xsp & Zd.T\n{\n\tZd.T = SVE_dup(Zd.T, Rn_GPR64xsp);\n}\n\n# dup_z_r.xml: DUP (scalar) variant SVE\n# PATTERN x05203800/mask=xff3ffc00\n\n:dup Zd.T, Rn_GPR32xsp\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1021=0b100000001110 & sve_rn_0509 & sve_zd_0004 & Rn_GPR32xsp & Zd.T\n{\n\tZd.T = SVE_dup(Zd.T, Rn_GPR32xsp);\n}\n\n# dup_z_zi.xml: DUP (indexed) variant SVE\n# PATTERN x05202000/mask=xff20fc00\n\n:dup Zd.T_tsz, Zn.T_tsz[sve_imm2_tsz]\nis sve_b_2431=0b00000101 & sve_imm2_2223 & sve_b_21=1 & sve_tsz_1620 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zd.T_tsz & Zn.T_tsz & sve_imm2_tsz\n{\n\tZd.T_tsz = SVE_dup(Zd.T_tsz, Zn.T_tsz, sve_imm2_tsz:1);\n}\n\n# dupm_z_i.xml: DUPM variant SVE\n# PATTERN x05c00000/mask=xfffc0000\n\n:dupm Zd.T_imm13, \"#\"^sve_decode_bit_mask\nis sve_b_1831=0b00000101110000 & sve_imm13_0517 & sve_zd_0004 & sve_decode_bit_mask & Zd.T_imm13\n{\n\tZd.T_imm13 = SVE_dupm(Zd.T_imm13, sve_decode_bit_mask:1);\n}\n\n# eon_eor_z_zi.xml: EON variant SVE\n# ALIASEDBY EOR ., ., #(- - 1) if Never\n# PATTERN x05400000/mask=xfffc0000\n\n:eon Zd.T_imm13, Zd.T_imm13_2, \"#\"^sve_decode_bit_mask\nis sve_b_2431=0b00000101 & sve_b_23=0 & sve_b_22=1 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2\n{\n\tZd.T_imm13 = SVE_eon(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1);\n}\n\n# eor_p_p_pp.xml: EOR, EORS (predicates) variant Flag setting\n# PATTERN x25404200/mask=xfff0c210\n\n:eors Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_eors(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# eor_p_p_pp.xml: EOR, EORS (predicates) variant Not flag setting\n# PATTERN x25004200/mask=xfff0c210\n\n:eor Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_eor(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# eor_z_p_zz.xml: EOR (vectors, predicated) variant SVE\n# PATTERN x04190000/mask=xff3fe000\n\n:eor Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_eor(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# eor_z_zi.xml: EOR (immediate) variant SVE\n# PATTERN x05400000/mask=xfffc0000\n\n# SKIPPING eor_z_zi.xml because x05400000/mask=xfffc0000 has already been defined\n\n# eor_z_zz.xml: EOR (vectors, unpredicated) variant SVE\n# PATTERN x04a03000/mask=xffe0fc00\n\n:eor Zd.D, Zn.D, Zm.D\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D\n{\n\tZd.D = SVE_eor(Zd.D, Zn.D, Zm.D);\n}\n\n# eorv_r_p_z.xml: EORV variant SVE\n# PATTERN x04192000/mask=xff3fe000\n\n:eorv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_eorv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# eorv_r_p_z.xml: EORV variant SVE\n# PATTERN x04192000/mask=xff3fe000\n\n:eorv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_eorv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# eorv_r_p_z.xml: EORV variant SVE\n# PATTERN x04192000/mask=xff3fe000\n\n:eorv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_eorv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# eorv_r_p_z.xml: EORV variant SVE\n# PATTERN x04192000/mask=xff3fe000\n\n:eorv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_eorv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# ext_z_zi.xml: EXT variant SVE\n# PATTERN x05200000/mask=xffe0e000\n\n:ext Zd.B, Zd.B_2, Zn.B, \"#\"^sve_imm8_2_0to255\nis sve_b_2131=0b00000101001 & sve_imm8h_1620 & sve_b_1315=0b000 & sve_imm8l_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.B & Zd.B_2 & Zn.B & sve_imm8_2_0to255\n{\n\tZd.B = SVE_ext(Zd.B, Zd.B_2, Zn.B, sve_imm8_2_0to255:1);\n}\n\n# fabd_z_p_zz.xml: FABD variant SVE\n# PATTERN x65088000/mask=xff3fe000\n\n:fabd Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b100 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fabd(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fabs_z_p_z.xml: FABS variant SVE\n# PATTERN x041ca000/mask=xff3fe000\n\n:fabs Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fabs(Zd.T, Pg3_m, Zn.T);\n}\n\n# facge_p_p_zz.xml: FAC variant Greater than\n# PATTERN x6500e010/mask=xff20e010\n\n:facgt Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_facgt(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# facge_p_p_zz.xml: FAC variant Greater than or equal\n# PATTERN x6500c010/mask=xff20e010\n\n:facge Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_facge(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# facle_facge_p_p_zz.xml: FACLE variant Greater than or equal\n# ALIASEDBY FACGE ., /Z, ., . if Never\n# PATTERN x6500c010/mask=xff20e010\n\n# SKIPPING facle_facge_p_p_zz.xml because x6500c010/mask=xff20e010 has already been defined\n\n# faclt_facge_p_p_zz.xml: FACLT variant Greater than\n# ALIASEDBY FACGT ., /Z, ., . if Never\n# PATTERN x6500e010/mask=xff20e010\n\n# SKIPPING faclt_facge_p_p_zz.xml because x6500e010/mask=xff20e010 has already been defined\n\n# fadd_z_p_zs.xml: FADD (immediate) variant SVE\n# PATTERN x65188000/mask=xff3fe3c0\n\n:fadd Zd.T, Pg3_m, Zd.T_2, sve_float_0510\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fadd(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1);\n}\n\n# fadd_z_p_zz.xml: FADD (vectors, predicated) variant SVE\n# PATTERN x65008000/mask=xff3fe000\n\n:fadd Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b000 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fadd(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fadd_z_zz.xml: FADD (vectors, unpredicated) variant SVE\n# PATTERN x65000000/mask=xff20fc00\n\n:fadd Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_fadd(Zd.T, Zn.T, Zm.T);\n}\n\n# fadda_v_p_z.xml: FADDA variant SVE\n# PATTERN x65182000/mask=xff3fe000\n\n:fadda Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3\n{\n\tRd_FPR8 = SVE_fadda(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T);\n}\n\n# fadda_v_p_z.xml: FADDA variant SVE\n# PATTERN x65182000/mask=xff3fe000\n\n:fadda Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3\n{\n\tRd_FPR32 = SVE_fadda(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T);\n}\n\n# fadda_v_p_z.xml: FADDA variant SVE\n# PATTERN x65182000/mask=xff3fe000\n\n:fadda Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3\n{\n\tRd_FPR16 = SVE_fadda(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T);\n}\n\n# fadda_v_p_z.xml: FADDA variant SVE\n# PATTERN x65182000/mask=xff3fe000\n\n:fadda Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3\n{\n\tRd_FPR64 = SVE_fadda(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T);\n}\n\n# faddv_v_p_z.xml: FADDV variant SVE\n# PATTERN x65002000/mask=xff3fe000\n\n:faddv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_faddv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# faddv_v_p_z.xml: FADDV variant SVE\n# PATTERN x65002000/mask=xff3fe000\n\n:faddv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_faddv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# faddv_v_p_z.xml: FADDV variant SVE\n# PATTERN x65002000/mask=xff3fe000\n\n:faddv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_faddv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# faddv_v_p_z.xml: FADDV variant SVE\n# PATTERN x65002000/mask=xff3fe000\n\n:faddv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_faddv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# fcadd_z_p_zz.xml: FCADD variant SVE\n# PATTERN x64008000/mask=xff3ee000\n\n:fcadd Zd.T, Pg3_m, Zd.T_2, Zn.T, sve_rot_16\nis sve_b_2431=0b01100100 & sve_size_2223 & sve_b_1721=0b00000 & sve_rot_16 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fcadd(Zd.T, Pg3_m, Zd.T_2, Zn.T, sve_rot_16:1);\n}\n\n# fcmeq_p_p_z0.xml: FCM (zero) variant Equal\n# PATTERN x65122000/mask=xff3fe010\n\n:fcmeq Pd.T, Pg3_z, Zn.T, \"#0.0\"\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmeq(Pd.T, Pg3_z, Zn.T);\n}\n\n# fcmeq_p_p_z0.xml: FCM (zero) variant Greater than\n# PATTERN x65102010/mask=xff3fe010\n\n:fcmgt Pd.T, Pg3_z, Zn.T, \"#0.0\"\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmgt(Pd.T, Pg3_z, Zn.T);\n}\n\n# fcmeq_p_p_z0.xml: FCM (zero) variant Greater than or equal\n# PATTERN x65102000/mask=xff3fe010\n\n:fcmge Pd.T, Pg3_z, Zn.T, \"#0.0\"\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmge(Pd.T, Pg3_z, Zn.T);\n}\n\n# fcmeq_p_p_z0.xml: FCM (zero) variant Less than\n# PATTERN x65112000/mask=xff3fe010\n\n:fcmlt Pd.T, Pg3_z, Zn.T, \"#0.0\"\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmlt(Pd.T, Pg3_z, Zn.T);\n}\n\n# fcmeq_p_p_z0.xml: FCM (zero) variant Less than or equal\n# PATTERN x65112010/mask=xff3fe010\n\n:fcmle Pd.T, Pg3_z, Zn.T, \"#0.0\"\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmle(Pd.T, Pg3_z, Zn.T);\n}\n\n# fcmeq_p_p_z0.xml: FCM (zero) variant Not equal\n# PATTERN x65132000/mask=xff3fe010\n\n:fcmne Pd.T, Pg3_z, Zn.T, \"#0.0\"\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmne(Pd.T, Pg3_z, Zn.T);\n}\n\n# fcmeq_p_p_zz.xml: FCM (vectors) variant Equal\n# PATTERN x65006000/mask=xff20e010\n\n:fcmeq Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmeq(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# fcmeq_p_p_zz.xml: FCM (vectors) variant Greater than\n# PATTERN x65004010/mask=xff20e010\n\n:fcmgt Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmgt(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# fcmeq_p_p_zz.xml: FCM (vectors) variant Greater than or equal\n# PATTERN x65004000/mask=xff20e010\n\n:fcmge Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmge(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# fcmeq_p_p_zz.xml: FCM (vectors) variant Not equal\n# PATTERN x65006010/mask=xff20e010\n\n:fcmne Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmne(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# fcmeq_p_p_zz.xml: FCM (vectors) variant Unordered\n# PATTERN x6500c000/mask=xff20e010\n\n:fcmuo Pd.T, Pg3_z, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z\n{\n\tPd.T = SVE_fcmuo(Pd.T, Pg3_z, Zn.T, Zm.T);\n}\n\n# fcmla_z_p_zzz.xml: FCMLA (vectors) variant SVE\n# PATTERN x64000000/mask=xff208000\n\n:fcmla Zd.T, Pg3_m, Zn.T, Zm.T, sve_rot_1314\nis sve_b_2431=0b01100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_rot_1314 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fcmla(Zd.T, Pg3_m, Zn.T, Zm.T, sve_rot_1314:1);\n}\n\n# fcmla_z_zzzi.xml: FCMLA (indexed) variant Half-precision\n# PATTERN x64a01000/mask=xffe0f000\n\n:fcmla Zd.H, Zn.H, Zm3.H[sve_i2_1920], sve_rot_1011\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1215=0b0001 & sve_rot_1011 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H\n{\n\tZd.H = SVE_fcmla(Zd.H, Zn.H, Zm3.H, sve_i2_1920:1, sve_rot_1011:1);\n}\n\n# fcmla_z_zzzi.xml: FCMLA (indexed) variant Single-precision\n# PATTERN x64e01000/mask=xffe0f000\n\n:fcmla Zd.S, Zn.S, Zm4.S[sve_i1_20], sve_rot_1011\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1215=0b0001 & sve_rot_1011 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm4.S\n{\n\tZd.S = SVE_fcmla(Zd.S, Zn.S, Zm4.S, sve_i1_20:1, sve_rot_1011:1);\n}\n\n# fcmle_fcmeq_p_p_zz.xml: FCMLE (vectors) variant Greater than or equal\n# ALIASEDBY FCMGE ., /Z, ., . if Never\n# PATTERN x65004000/mask=xff20e010\n\n# SKIPPING fcmle_fcmeq_p_p_zz.xml because x65004000/mask=xff20e010 has already been defined\n\n# fcmlt_fcmeq_p_p_zz.xml: FCMLT (vectors) variant Greater than\n# ALIASEDBY FCMGT ., /Z, ., . if Never\n# PATTERN x65004010/mask=xff20e010\n\n# SKIPPING fcmlt_fcmeq_p_p_zz.xml because x65004010/mask=xff20e010 has already been defined\n\n# fcpy_z_p_i.xml: FCPY variant SVE\n# PATTERN x0510c000/mask=xff30e000\n\n:fcpy Zd.T, Pm_m, \"#\"^sve_float_imm8\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_1315=0b110 & sve_imm8_0512 & sve_zd_0004 & sve_float_imm8 & Zd.T & Pm_m\n{\n\tZd.T = SVE_fcpy(Zd.T, Pm_m, sve_float_imm8:1);\n}\n\n# fcvt_z_p_z.xml: FCVT variant Half-precision to single-precision\n# PATTERN x6589a000/mask=xffffe000\n\n:fcvt Zd.S, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvt(Zd.S, Pg3_m, Zn.H);\n}\n\n# fcvt_z_p_z.xml: FCVT variant Half-precision to double-precision\n# PATTERN x65c9a000/mask=xffffe000\n\n:fcvt Zd.D, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvt(Zd.D, Pg3_m, Zn.H);\n}\n\n# fcvt_z_p_z.xml: FCVT variant Single-precision to half-precision\n# PATTERN x6588a000/mask=xffffe000\n\n:fcvt Zd.H, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m\n{\n\tZd.H = SVE_fcvt(Zd.H, Pg3_m, Zn.S);\n}\n\n# fcvt_z_p_z.xml: FCVT variant Single-precision to double-precision\n# PATTERN x65cba000/mask=xffffe000\n\n:fcvt Zd.D, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvt(Zd.D, Pg3_m, Zn.S);\n}\n\n# fcvt_z_p_z.xml: FCVT variant Double-precision to half-precision\n# PATTERN x65c8a000/mask=xffffe000\n\n:fcvt Zd.H, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m\n{\n\tZd.H = SVE_fcvt(Zd.H, Pg3_m, Zn.D);\n}\n\n# fcvt_z_p_z.xml: FCVT variant Double-precision to single-precision\n# PATTERN x65caa000/mask=xffffe000\n\n:fcvt Zd.S, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvt(Zd.S, Pg3_m, Zn.D);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 16-bit\n# PATTERN x655aa000/mask=xffffe000\n\n:fcvtzs Zd.H, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m\n{\n\tZd.H = SVE_fcvtzs(Zd.H, Pg3_m, Zn.H);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 32-bit\n# PATTERN x655ca000/mask=xffffe000\n\n:fcvtzs Zd.S, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.H);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 64-bit\n# PATTERN x655ea000/mask=xffffe000\n\n:fcvtzs Zd.D, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.H);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Single-precision to 32-bit\n# PATTERN x659ca000/mask=xffffe000\n\n:fcvtzs Zd.S, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.S);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Single-precision to 64-bit\n# PATTERN x65dca000/mask=xffffe000\n\n:fcvtzs Zd.D, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.S);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Double-precision to 32-bit\n# PATTERN x65d8a000/mask=xffffe000\n\n:fcvtzs Zd.S, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.D);\n}\n\n# fcvtzs_z_p_z.xml: FCVTZS variant Double-precision to 64-bit\n# PATTERN x65dea000/mask=xffffe000\n\n:fcvtzs Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.D);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 16-bit\n# PATTERN x655ba000/mask=xffffe000\n\n:fcvtzu Zd.H, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m\n{\n\tZd.H = SVE_fcvtzu(Zd.H, Pg3_m, Zn.H);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 32-bit\n# PATTERN x655da000/mask=xffffe000\n\n:fcvtzu Zd.S, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.H);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 64-bit\n# PATTERN x655fa000/mask=xffffe000\n\n:fcvtzu Zd.D, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.H);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Single-precision to 32-bit\n# PATTERN x659da000/mask=xffffe000\n\n:fcvtzu Zd.S, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.S);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Single-precision to 64-bit\n# PATTERN x65dda000/mask=xffffe000\n\n:fcvtzu Zd.D, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.S);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Double-precision to 32-bit\n# PATTERN x65d9a000/mask=xffffe000\n\n:fcvtzu Zd.S, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m\n{\n\tZd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.D);\n}\n\n# fcvtzu_z_p_z.xml: FCVTZU variant Double-precision to 64-bit\n# PATTERN x65dfa000/mask=xffffe000\n\n:fcvtzu Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.D);\n}\n\n# fdiv_z_p_zz.xml: FDIV variant SVE\n# PATTERN x650d8000/mask=xff3fe000\n\n:fdiv Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b110 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fdiv(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fdivr_z_p_zz.xml: FDIVR variant SVE\n# PATTERN x650c8000/mask=xff3fe000\n\n:fdivr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b110 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fdivr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fdup_z_i.xml: FDUP variant SVE\n# PATTERN x2539c000/mask=xff3fe000\n\n:fdup Zd.T, \"#\"^sve_float_imm8\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b111 & sve_b_13=0 & sve_imm8_0512 & sve_zd_0004 & sve_float_imm8 & Zd.T\n{\n\tZd.T = SVE_fdup(Zd.T, sve_float_imm8:1);\n}\n\n# fexpa_z_z.xml: FEXPA variant SVE\n# PATTERN x0420b800/mask=xff3ffc00\n\n:fexpa Zd.T, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_b_1720=0b0000 & sve_b_16=0 & sve_b_1015=0b101110 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T\n{\n\tZd.T = SVE_fexpa(Zd.T, Zn.T);\n}\n\n# fmad_z_p_zzz.xml: FMAD variant SVE\n# PATTERN x65208000/mask=xff20e000\n\n:fmad Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m\n{\n\tZd.T = SVE_fmad(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fmax_z_p_zs.xml: FMAX (immediate) variant SVE\n# PATTERN x651e8000/mask=xff3fe3c0\n\n:fmax Zd.T, Pg3_m, Zd.T_2, sve_float_0010\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fmax(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);\n}\n\n# fmax_z_p_zz.xml: FMAX (vectors) variant SVE\n# PATTERN x65068000/mask=xff3fe000\n\n:fmax Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b011 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmax(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fmaxnm_z_p_zs.xml: FMAXNM (immediate) variant SVE\n# PATTERN x651c8000/mask=xff3fe3c0\n\n:fmaxnm Zd.T, Pg3_m, Zd.T_2, sve_float_0010\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fmaxnm(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);\n}\n\n# fmaxnm_z_p_zz.xml: FMAXNM (vectors) variant SVE\n# PATTERN x65048000/mask=xff3fe000\n\n:fmaxnm Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b010 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmaxnm(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE\n# PATTERN x65042000/mask=xff3fe000\n\n:fmaxnmv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_fmaxnmv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE\n# PATTERN x65042000/mask=xff3fe000\n\n:fmaxnmv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_fmaxnmv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE\n# PATTERN x65042000/mask=xff3fe000\n\n:fmaxnmv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_fmaxnmv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE\n# PATTERN x65042000/mask=xff3fe000\n\n:fmaxnmv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_fmaxnmv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# fmaxv_v_p_z.xml: FMAXV variant SVE\n# PATTERN x65062000/mask=xff3fe000\n\n:fmaxv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_fmaxv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# fmaxv_v_p_z.xml: FMAXV variant SVE\n# PATTERN x65062000/mask=xff3fe000\n\n:fmaxv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_fmaxv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# fmaxv_v_p_z.xml: FMAXV variant SVE\n# PATTERN x65062000/mask=xff3fe000\n\n:fmaxv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_fmaxv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# fmaxv_v_p_z.xml: FMAXV variant SVE\n# PATTERN x65062000/mask=xff3fe000\n\n:fmaxv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_fmaxv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# fmin_z_p_zs.xml: FMIN (immediate) variant SVE\n# PATTERN x651f8000/mask=xff3fe3c0\n\n:fmin Zd.T, Pg3_m, Zd.T_2, sve_float_0010\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fmin(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);\n}\n\n# fmin_z_p_zz.xml: FMIN (vectors) variant SVE\n# PATTERN x65078000/mask=xff3fe000\n\n:fmin Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b011 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmin(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fminnm_z_p_zs.xml: FMINNM (immediate) variant SVE\n# PATTERN x651d8000/mask=xff3fe3c0\n\n:fminnm Zd.T, Pg3_m, Zd.T_2, sve_float_0010\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fminnm(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);\n}\n\n# fminnm_z_p_zz.xml: FMINNM (vectors) variant SVE\n# PATTERN x65058000/mask=xff3fe000\n\n:fminnm Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b010 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fminnm(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fminnmv_v_p_z.xml: FMINNMV variant SVE\n# PATTERN x65052000/mask=xff3fe000\n\n:fminnmv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_fminnmv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# fminnmv_v_p_z.xml: FMINNMV variant SVE\n# PATTERN x65052000/mask=xff3fe000\n\n:fminnmv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_fminnmv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# fminnmv_v_p_z.xml: FMINNMV variant SVE\n# PATTERN x65052000/mask=xff3fe000\n\n:fminnmv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_fminnmv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# fminnmv_v_p_z.xml: FMINNMV variant SVE\n# PATTERN x65052000/mask=xff3fe000\n\n:fminnmv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_fminnmv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# fminv_v_p_z.xml: FMINV variant SVE\n# PATTERN x65072000/mask=xff3fe000\n\n:fminv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_fminv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# fminv_v_p_z.xml: FMINV variant SVE\n# PATTERN x65072000/mask=xff3fe000\n\n:fminv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_fminv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# fminv_v_p_z.xml: FMINV variant SVE\n# PATTERN x65072000/mask=xff3fe000\n\n:fminv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_fminv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# fminv_v_p_z.xml: FMINV variant SVE\n# PATTERN x65072000/mask=xff3fe000\n\n:fminv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_fminv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# fmla_z_p_zzz.xml: FMLA (vectors) variant SVE\n# PATTERN x65200000/mask=xff20e000\n\n:fmla Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmla(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fmla_z_zzzi.xml: FMLA (indexed) variant Half-precision\n# PATTERN x64200000/mask=xffa0fc00\n\n:fmla Zd.H, Zn.H, Zm3.H[sve_i3h_i3l]\nis sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H & sve_i3h_i3l\n{\n\tZd.H = SVE_fmla(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1);\n}\n\n# fmla_z_zzzi.xml: FMLA (indexed) variant Single-precision\n# PATTERN x64a00000/mask=xffe0fc00\n\n:fmla Zd.S, Zn.S, Zm3.S[sve_i2_1920]\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm3.S\n{\n\tZd.S = SVE_fmla(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1);\n}\n\n# fmla_z_zzzi.xml: FMLA (indexed) variant Double-precision\n# PATTERN x64e00000/mask=xffe0fc00\n\n:fmla Zd.D, Zn.D, Zm4.D[sve_i1_20]\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.D & Zm4.D\n{\n\tZd.D = SVE_fmla(Zd.D, Zn.D, Zm4.D, sve_i1_20:1);\n}\n\n# fmls_z_p_zzz.xml: FMLS (vectors) variant SVE\n# PATTERN x65202000/mask=xff20e000\n\n:fmls Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmls(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fmls_z_zzzi.xml: FMLS (indexed) variant Half-precision\n# PATTERN x64200400/mask=xffa0fc00\n\n:fmls Zd.H, Zn.H, Zm3.H[sve_i3h_i3l]\nis sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H & sve_i3h_i3l\n{\n\tZd.H = SVE_fmls(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1);\n}\n\n# fmls_z_zzzi.xml: FMLS (indexed) variant Single-precision\n# PATTERN x64a00400/mask=xffe0fc00\n\n:fmls Zd.S, Zn.S, Zm3.S[sve_i2_1920]\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm3.S\n{\n\tZd.S = SVE_fmls(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1);\n}\n\n# fmls_z_zzzi.xml: FMLS (indexed) variant Double-precision\n# PATTERN x64e00400/mask=xffe0fc00\n\n:fmls Zd.D, Zn.D, Zm4.D[sve_i1_20]\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.D & Zm4.D\n{\n\tZd.D = SVE_fmls(Zd.D, Zn.D, Zm4.D, sve_i1_20:1);\n}\n\n# fmov_cpy_z_p_i.xml: FMOV (zero, predicated) variant SVE\n# ALIASEDBY CPY ., /M, #0 if Never\n# PATTERN x05104000/mask=xff30ffe0\n\n:fmov Zd.T, Pm_m, \"#0.0\"\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_15=0 & sve_m_14=1 & sve_sh_13=0 & sve_imm8_0512=0b00000000 & sve_zd_0004 & Zd.T & Pm_m\n{\n\tZd.T = SVE_fmov(Zd.T, Pm_m);\n}\n\n# fmov_dup_z_i.xml: FMOV (zero, unpredicated) variant SVE\n# ALIASEDBY DUP ., #0 if Never\n# PATTERN x2538c000/mask=xff3fffe0\n\n:fmov Zd.T, \"#0.0\"\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b011 & sve_sh_13=0 & sve_imm8_0512=0b00000000 & sve_zd_0004 & Zd.T\n{\n\tZd.T = SVE_fmov(Zd.T);\n}\n\n# fmov_fcpy_z_p_i.xml: FMOV (immediate, predicated) variant SVE\n# ALIASEDBY FCPY ., /M, # if Unconditionally\n# PATTERN x0510c000/mask=xff30e000\n\n# SKIPPING fmov_fcpy_z_p_i.xml because x0510c000/mask=xff30e000 has already been defined\n\n# fmov_fdup_z_i.xml: FMOV (immediate, unpredicated) variant SVE\n# ALIASEDBY FDUP ., # if Unconditionally\n# PATTERN x2539c000/mask=xff3fe000\n\n# SKIPPING fmov_fdup_z_i.xml because x2539c000/mask=xff3fe000 has already been defined\n\n# fmsb_z_p_zzz.xml: FMSB variant SVE\n# PATTERN x6520a000/mask=xff20e000\n\n:fmsb Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m\n{\n\tZd.T = SVE_fmsb(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fmul_z_p_zs.xml: FMUL (immediate) variant SVE\n# PATTERN x651a8000/mask=xff3fe3c0\n\n:fmul Zd.T, Pg3_m, Zd.T_2, sve_float_0520\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0520 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fmul(Zd.T, Pg3_m, Zd.T_2, sve_float_0520:1);\n}\n\n# fmul_z_p_zz.xml: FMUL (vectors, predicated) variant SVE\n# PATTERN x65028000/mask=xff3fe000\n\n:fmul Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmul(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fmul_z_zz.xml: FMUL (vectors, unpredicated) variant SVE\n# PATTERN x65000800/mask=xff20fc00\n\n:fmul Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b01 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_fmul(Zd.T, Zn.T, Zm.T);\n}\n\n# fmul_z_zzi.xml: FMUL (indexed) variant Half-precision\n# PATTERN x64202000/mask=xffa0fc00\n\n:fmul Zd.H, Zn.H, Zm3.H[sve_i3h_i3l]\nis sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Zm3.H & sve_i3h_i3l\n{\n\tZd.H = SVE_fmul(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1);\n}\n\n# fmul_z_zzi.xml: FMUL (indexed) variant Single-precision\n# PATTERN x64a02000/mask=xffe0fc00\n\n:fmul Zd.S, Zn.S, Zm3.S[sve_i2_1920]\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Zm3.S\n{\n\tZd.S = SVE_fmul(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1);\n}\n\n# fmul_z_zzi.xml: FMUL (indexed) variant Double-precision\n# PATTERN x64e02000/mask=xffe0fc00\n\n:fmul Zd.D, Zn.D, Zm4.D[sve_i1_20]\nis sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm4.D\n{\n\tZd.D = SVE_fmul(Zd.D, Zn.D, Zm4.D, sve_i1_20:1);\n}\n\n# fmulx_z_p_zz.xml: FMULX variant SVE\n# PATTERN x650a8000/mask=xff3fe000\n\n:fmulx Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fmulx(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fneg_z_p_z.xml: FNEG variant SVE\n# PATTERN x041da000/mask=xff3fe000\n\n:fneg Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fneg(Zd.T, Pg3_m, Zn.T);\n}\n\n# fnmad_z_p_zzz.xml: FNMAD variant SVE\n# PATTERN x6520c000/mask=xff20e000\n\n:fnmad Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m\n{\n\tZd.T = SVE_fnmad(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fnmla_z_p_zzz.xml: FNMLA variant SVE\n# PATTERN x65204000/mask=xff20e000\n\n:fnmla Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fnmla(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fnmls_z_p_zzz.xml: FNMLS variant SVE\n# PATTERN x65206000/mask=xff20e000\n\n:fnmls Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fnmls(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# fnmsb_z_p_zzz.xml: FNMSB variant SVE\n# PATTERN x6520e000/mask=xff20e000\n\n:fnmsb Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m\n{\n\tZd.T = SVE_fnmsb(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# frecpe_z_z.xml: FRECPE variant SVE\n# PATTERN x650e3000/mask=xff3ffc00\n\n:frecpe Zd.T, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b001 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T\n{\n\tZd.T = SVE_frecpe(Zd.T, Zn.T);\n}\n\n# frecps_z_zz.xml: FRECPS variant SVE\n# PATTERN x65001800/mask=xff20fc00\n\n:frecps Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_frecps(Zd.T, Zn.T, Zm.T);\n}\n\n# frecpx_z_p_z.xml: FRECPX variant SVE\n# PATTERN x650ca000/mask=xff3fe000\n\n:frecpx Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0011 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frecpx(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Current mode\n# PATTERN x6507a000/mask=xff3fe000\n\n:frinti Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frinti(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Current mode signalling inexact\n# PATTERN x6506a000/mask=xff3fe000\n\n:frintx Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frintx(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Nearest with ties to away\n# PATTERN x6504a000/mask=xff3fe000\n\n:frinta Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frinta(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Nearest with ties to even\n# PATTERN x6500a000/mask=xff3fe000\n\n:frintn Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frintn(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Toward zero\n# PATTERN x6503a000/mask=xff3fe000\n\n:frintz Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frintz(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Toward minus infinity\n# PATTERN x6502a000/mask=xff3fe000\n\n:frintm Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frintm(Zd.T, Pg3_m, Zn.T);\n}\n\n# frinta_z_p_z.xml: FRINT variant Toward plus infinity\n# PATTERN x6501a000/mask=xff3fe000\n\n:frintp Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_frintp(Zd.T, Pg3_m, Zn.T);\n}\n\n# frsqrte_z_z.xml: FRSQRTE variant SVE\n# PATTERN x650f3000/mask=xff3ffc00\n\n:frsqrte Zd.T, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b001 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T\n{\n\tZd.T = SVE_frsqrte(Zd.T, Zn.T);\n}\n\n# frsqrts_z_zz.xml: FRSQRTS variant SVE\n# PATTERN x65001c00/mask=xff20fc00\n\n:frsqrts Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_frsqrts(Zd.T, Zn.T, Zm.T);\n}\n\n# fscale_z_p_zz.xml: FSCALE variant SVE\n# PATTERN x65098000/mask=xff3fe000\n\n:fscale Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b100 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fscale(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fsqrt_z_p_z.xml: FSQRT variant SVE\n# PATTERN x650da000/mask=xff3fe000\n\n:fsqrt Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0011 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fsqrt(Zd.T, Pg3_m, Zn.T);\n}\n\n# fsub_z_p_zs.xml: FSUB (immediate) variant SVE\n# PATTERN x65198000/mask=xff3fe3c0\n\n:fsub Zd.T, Pg3_m, Zd.T_2, sve_float_0510\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fsub(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1);\n}\n\n# fsub_z_p_zz.xml: FSUB (vectors, predicated) variant SVE\n# PATTERN x65018000/mask=xff3fe000\n\n:fsub Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b000 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fsub(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# fsub_z_zz.xml: FSUB (vectors, unpredicated) variant SVE\n# PATTERN x65000400/mask=xff20fc00\n\n:fsub Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_fsub(Zd.T, Zn.T, Zm.T);\n}\n\n# fsubr_z_p_zs.xml: FSUBR (immediate) variant SVE\n# PATTERN x651b8000/mask=xff3fe3c0\n\n:fsubr Zd.T, Pg3_m, Zd.T_2, sve_float_0510\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m\n{\n\tZd.T = SVE_fsubr(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1);\n}\n\n# fsubr_z_p_zz.xml: FSUBR (vectors) variant SVE\n# PATTERN x65038000/mask=xff3fe000\n\n:fsubr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_fsubr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# ftmad_z_zzi.xml: FTMAD variant SVE\n# PATTERN x65108000/mask=xff38fc00\n\n:ftmad Zd.T, Zd.T_2, Zn.T, \"#\"^sve_imm3_1_0to7\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b010 & sve_imm3_1618 & sve_b_1015=0b100000 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & sve_imm3_1_0to7\n{\n\tZd.T = SVE_ftmad(Zd.T, Zd.T_2, Zn.T, sve_imm3_1_0to7:1);\n}\n\n# ftsmul_z_zz.xml: FTSMUL variant SVE\n# PATTERN x65000c00/mask=xff20fc00\n\n:ftsmul Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b01 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_ftsmul(Zd.T, Zn.T, Zm.T);\n}\n\n# ftssel_z_zz.xml: FTSSEL variant SVE\n# PATTERN x0420b000/mask=xff20fc00\n\n:ftssel Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1115=0b10110 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_ftssel(Zd.T, Zn.T, Zm.T);\n}\n\n# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Byte\n# PATTERN x0430e000/mask=xfff0fc00\n\n:incb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_incb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Doubleword\n# PATTERN x04f0e000/mask=xfff0fc00\n\n:incd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_incd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Halfword\n# PATTERN x0470e000/mask=xfff0fc00\n\n:inch Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_inch(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Word\n# PATTERN x04b0e000/mask=xfff0fc00\n\n:incw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_incw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incd_z_zs.xml: INCD, INCH, INCW (vector) variant Doubleword\n# PATTERN x04f0c000/mask=xfff0fc00\n\n:incd Zd.D^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.D = SVE_incd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incd_z_zs.xml: INCD, INCH, INCW (vector) variant Halfword\n# PATTERN x0470c000/mask=xfff0fc00\n\n:inch Zd.H^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.H = SVE_inch(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incd_z_zs.xml: INCD, INCH, INCW (vector) variant Word\n# PATTERN x04b0c000/mask=xfff0fc00\n\n:incw Zd.S^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.S = SVE_incw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# incp_r_p_r.xml: INCP (scalar) variant SVE\n# PATTERN x252c8800/mask=xff3ffe00\n\n:incp Rd_GPR64, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64\n{\n\tRd_GPR64 = SVE_incp(Rd_GPR64, Pn.T);\n}\n\n# incp_z_p_z.xml: INCP (vector) variant SVE\n# PATTERN x252c8000/mask=xff3ffe00\n\n:incp Zd.T, Pn\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn\n{\n\tZd.T = SVE_incp(Zd.T, Pn);\n}\n\n# index_z_ii.xml: INDEX (immediates) variant SVE\n# PATTERN x04204000/mask=xff20fc00\n\n:index Zd.T, \"#\"^sve_imm5s_0509, \"#\"^sve_imm5b_1620\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_imm5b_1620 & sve_b_1015=0b010000 & sve_imm5_0509 & sve_zd_0004 & Zd.T & sve_imm5s_0509\n{\n\tZd.T = SVE_index(Zd.T, sve_imm5s_0509:1, sve_imm5b_1620:1);\n}\n\n# index_z_ir.xml: INDEX (immediate, scalar) variant SVE\n# PATTERN x04204800/mask=xff20fc00\n\n:index Zd.T, \"#\"^sve_imm5_1_m16to15, Rm_GPR64\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010010 & sve_imm5_0509 & sve_zd_0004 & Zd.T & Rm_GPR64 & sve_imm5_1_m16to15\n{\n\tZd.T = SVE_index(Zd.T, sve_imm5_1_m16to15:1, Rm_GPR64);\n}\n\n# index_z_ir.xml: INDEX (immediate, scalar) variant SVE\n# PATTERN x04204800/mask=xff20fc00\n\n:index Zd.T, \"#\"^sve_imm5_1_m16to15, Rm_GPR32\nis sve_b_2431=0b00000100 & (b_23=0 | b_22=0) & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010010 & sve_imm5_0509 & sve_zd_0004 & Zd.T & Rm_GPR32 & sve_imm5_1_m16to15\n{\n\tZd.T = SVE_index(Zd.T, sve_imm5_1_m16to15:1, Rm_GPR32);\n}\n\n# index_z_ri.xml: INDEX (scalar, immediate) variant SVE\n# PATTERN x04204400/mask=xff20fc00\n\n:index Zd.T, Rn_GPR64, \"#\"^sve_imm5_1_m16to15\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_21=1 & sve_imm5_1620 & sve_b_1015=0b010001 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR64 & sve_imm5_1_m16to15\n{\n\tZd.T = SVE_index(Zd.T, Rn_GPR64, sve_imm5_1_m16to15:1);\n}\n\n# index_z_ri.xml: INDEX (scalar, immediate) variant SVE\n# PATTERN x04204400/mask=xff20fc00\n\n:index Zd.T, Rn_GPR32, \"#\"^sve_imm5_1_m16to15\nis sve_b_2431=0b00000100 & (b_23=0 | b_22=0) & sve_b_21=1 & sve_imm5_1620 & sve_b_1015=0b010001 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR32 & sve_imm5_1_m16to15\n{\n\tZd.T = SVE_index(Zd.T, Rn_GPR32, sve_imm5_1_m16to15:1);\n}\n\n# index_z_rr.xml: INDEX (scalars) variant SVE\n# PATTERN x04204c00/mask=xff20fc00\n\n:index Zd.T, Rn_GPR64, Rm_GPR64\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010011 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR64 & Rm_GPR64\n{\n\tZd.T = SVE_index(Zd.T, Rn_GPR64, Rm_GPR64);\n}\n\n# index_z_rr.xml: INDEX (scalars) variant SVE\n# PATTERN x04204c00/mask=xff20fc00\n\n:index Zd.T, Rn_GPR32, Rm_GPR32\nis sve_b_2431=0b00000100 & (b_23=0 | b_22=0) & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010011 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR32 & Rm_GPR32\n{\n\tZd.T = SVE_index(Zd.T, Rn_GPR32, Rm_GPR32);\n}\n\n# insr_z_r.xml: INSR (scalar) variant SVE\n# PATTERN x05243800/mask=xff3ffc00\n\n:insr Zd.T, Rn_GPR64\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b100100001110 & sve_rm_0509 & sve_zdn_0004 & Zd.T & Rn_GPR64\n{\n\tZd.T = SVE_insr(Zd.T, Rn_GPR64);\n}\n\n# insr_z_r.xml: INSR (scalar) variant SVE\n# PATTERN x05243800/mask=xff3ffc00\n\n:insr Zd.T, Rn_GPR32\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1021=0b100100001110 & sve_rm_0509 & sve_zdn_0004 & Zd.T & Rn_GPR32\n{\n\tZd.T = SVE_insr(Zd.T, Rn_GPR32);\n}\n\n# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE\n# PATTERN x05343800/mask=xff3ffc00\n\n:insr Zd.T, Rn_FPR8\nis sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR8\n{\n\tZd.T = SVE_insr(Zd.T, Rn_FPR8);\n}\n\n# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE\n# PATTERN x05343800/mask=xff3ffc00\n\n:insr Zd.T, Rn_FPR32\nis sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR32\n{\n\tZd.T = SVE_insr(Zd.T, Rn_FPR32);\n}\n\n# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE\n# PATTERN x05343800/mask=xff3ffc00\n\n:insr Zd.T, Rn_FPR16\nis sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR16\n{\n\tZd.T = SVE_insr(Zd.T, Rn_FPR16);\n}\n\n# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE\n# PATTERN x05343800/mask=xff3ffc00\n\n:insr Zd.T, Rn_FPR64\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR64\n{\n\tZd.T = SVE_insr(Zd.T, Rn_FPR64);\n}\n\n# lasta_r_p_z.xml: LASTA (scalar) variant SVE\n# PATTERN x0520a000/mask=xff3fe000\n\n:lasta Rd_GPR64, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR64 & Pg3\n{\n\tRd_GPR64 = SVE_lasta(Rd_GPR64, Pg3, Zn.T);\n}\n\n# lasta_r_p_z.xml: LASTA (scalar) variant SVE\n# PATTERN x0520a000/mask=xff3fe000\n\n:lasta Rd_GPR32, Pg3, Zn.T\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b10000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR32 & Pg3\n{\n\tRd_GPR32 = SVE_lasta(Rd_GPR32, Pg3, Zn.T);\n}\n\n# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE\n# PATTERN x05228000/mask=xff3fe000\n\n:lasta Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_lasta(Rd_FPR8, Pg3, Zn.T);\n}\n\n# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE\n# PATTERN x05228000/mask=xff3fe000\n\n:lasta Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_lasta(Rd_FPR32, Pg3, Zn.T);\n}\n\n# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE\n# PATTERN x05228000/mask=xff3fe000\n\n:lasta Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_lasta(Rd_FPR16, Pg3, Zn.T);\n}\n\n# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE\n# PATTERN x05228000/mask=xff3fe000\n\n:lasta Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_lasta(Rd_FPR64, Pg3, Zn.T);\n}\n\n# lastb_r_p_z.xml: LASTB (scalar) variant SVE\n# PATTERN x0521a000/mask=xff3fe000\n\n:lastb Rd_GPR64, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR64 & Pg3\n{\n\tRd_GPR64 = SVE_lastb(Rd_GPR64, Pg3, Zn.T);\n}\n\n# lastb_r_p_z.xml: LASTB (scalar) variant SVE\n# PATTERN x0521a000/mask=xff3fe000\n\n:lastb Rd_GPR32, Pg3, Zn.T\nis sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b10000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR32 & Pg3\n{\n\tRd_GPR32 = SVE_lastb(Rd_GPR32, Pg3, Zn.T);\n}\n\n# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE\n# PATTERN x05238000/mask=xff3fe000\n\n:lastb Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_lastb(Rd_FPR8, Pg3, Zn.T);\n}\n\n# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE\n# PATTERN x05238000/mask=xff3fe000\n\n:lastb Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_lastb(Rd_FPR32, Pg3, Zn.T);\n}\n\n# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE\n# PATTERN x05238000/mask=xff3fe000\n\n:lastb Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_lastb(Rd_FPR16, Pg3, Zn.T);\n}\n\n# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE\n# PATTERN x05238000/mask=xff3fe000\n\n:lastb Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_lastb(Rd_FPR64, Pg3, Zn.T);\n}\n\n# ld1b_z_p_ai.xml: LD1B (vector plus immediate) variant 32-bit element\n# PATTERN x8420c000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to31]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31\n{\n\tZd.S = SVE_ld1b(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31);\n}\n\n# ld1b_z_p_ai.xml: LD1B (vector plus immediate) variant 64-bit element\n# PATTERN xc420c000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to31]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31\n{\n\tZd.D = SVE_ld1b(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31);\n}\n\n# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 8-bit element\n# PATTERN xa400a000/mask=xfff0e000\n\n:ld1b \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_mul4_1_m8to7\n{\n\tZd.B = SVE_ld1b(Zd.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 16-bit element\n# PATTERN xa420a000/mask=xfff0e000\n\n:ld1b \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ld1b(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 32-bit element\n# PATTERN xa440a000/mask=xfff0e000\n\n:ld1b \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ld1b(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 64-bit element\n# PATTERN xa460a000/mask=xfff0e000\n\n:ld1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 8-bit element\n# PATTERN xa4004000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64\n{\n\tZd.B = SVE_ld1b(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 16-bit element\n# PATTERN xa4204000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ld1b(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 32-bit element\n# PATTERN xa4404000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ld1b(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 64-bit element\n# PATTERN xa4604000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1b_z_p_bz.xml: LD1B (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4004000/mask=xffa0e000\n\n:ld1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1b_z_p_bz.xml: LD1B (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84004000/mask=xffa0e000\n\n:ld1b \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1b(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1b_z_p_bz.xml: LD1B (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc440c000/mask=xffe0e000\n\n:ld1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1d_z_p_ai.xml: LD1D (vector plus immediate) variant SVE\n# PATTERN xc5a0c000/mask=xffe0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to248]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to248\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to248);\n}\n\n# ld1d_z_p_bi.xml: LD1D (scalar plus immediate) variant SVE\n# PATTERN xa5e0a000/mask=xfff0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1d_z_p_br.xml: LD1D (scalar plus scalar) variant SVE\n# PATTERN xa5e04000/mask=xffe0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc5a04000/mask=xffa0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #3\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc5804000/mask=xffa0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc5e0c000/mask=xffe0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #3\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc5c0c000/mask=xffe0e000\n\n:ld1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1h_z_p_ai.xml: LD1H (vector plus immediate) variant 32-bit element\n# PATTERN x84a0c000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to62]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62\n{\n\tZd.S = SVE_ld1h(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62);\n}\n\n# ld1h_z_p_ai.xml: LD1H (vector plus immediate) variant 64-bit element\n# PATTERN xc4a0c000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to62]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62);\n}\n\n# ld1h_z_p_bi.xml: LD1H (scalar plus immediate) variant 16-bit element\n# PATTERN xa4a0a000/mask=xfff0e000\n\n:ld1h \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ld1h(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1h_z_p_bi.xml: LD1H (scalar plus immediate) variant 32-bit element\n# PATTERN xa4c0a000/mask=xfff0e000\n\n:ld1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1h_z_p_bi.xml: LD1H (scalar plus immediate) variant 64-bit element\n# PATTERN xa4e0a000/mask=xfff0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1h_z_p_br.xml: LD1H (scalar plus scalar) variant 16-bit element\n# PATTERN xa4a04000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ld1h(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1h_z_p_br.xml: LD1H (scalar plus scalar) variant 32-bit element\n# PATTERN xa4c04000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1h_z_p_br.xml: LD1H (scalar plus scalar) variant 64-bit element\n# PATTERN xa4e04000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84a04000/mask=xffa0e000\n\n:ld1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^\" #1\"]\nis sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4a04000/mask=xffa0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4804000/mask=xffa0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84804000/mask=xffa0e000\n\n:ld1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc4e0c000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc4c0c000/mask=xffe0e000\n\n:ld1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1rb_z_p_bi.xml: LD1RB variant 8-bit element\n# PATTERN x84408000/mask=xffc0e000\n\n:ld1rb \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_opt6_1_0to63\n{\n\tZd.B = SVE_ld1rb(Zd.B, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rb_z_p_bi.xml: LD1RB variant 16-bit element\n# PATTERN x8440a000/mask=xffc0e000\n\n:ld1rb \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt6_1_0to63\n{\n\tZd.H = SVE_ld1rb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rb_z_p_bi.xml: LD1RB variant 32-bit element\n# PATTERN x8440c000/mask=xffc0e000\n\n:ld1rb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to63\n{\n\tZd.S = SVE_ld1rb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rb_z_p_bi.xml: LD1RB variant 64-bit element\n# PATTERN x8440e000/mask=xffc0e000\n\n:ld1rb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to63\n{\n\tZd.D = SVE_ld1rb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rd_z_p_bi.xml: LD1RD variant SVE\n# PATTERN x85c0e000/mask=xffc0e000\n\n:ld1rd \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to504]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to504\n{\n\tZd.D = SVE_ld1rd(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to504);\n}\n\n# ld1rh_z_p_bi.xml: LD1RH variant 16-bit element\n# PATTERN x84c0a000/mask=xffc0e000\n\n:ld1rh \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt6_1_0to126\n{\n\tZd.H = SVE_ld1rh(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126);\n}\n\n# ld1rh_z_p_bi.xml: LD1RH variant 32-bit element\n# PATTERN x84c0c000/mask=xffc0e000\n\n:ld1rh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to126\n{\n\tZd.S = SVE_ld1rh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126);\n}\n\n# ld1rh_z_p_bi.xml: LD1RH variant 64-bit element\n# PATTERN x84c0e000/mask=xffc0e000\n\n:ld1rh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to126\n{\n\tZd.D = SVE_ld1rh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126);\n}\n\n# ld1rqb_z_p_bi.xml: LD1RQB (scalar plus immediate) variant SVE\n# PATTERN xa4002000/mask=xfff0e000\n\n:ld1rqb \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_opt4_1_m128to112\n{\n\tZd.B = SVE_ld1rqb(Zd.B, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112);\n}\n\n# ld1rqb_z_p_br.xml: LD1RQB (scalar plus scalar) variant SVE\n# PATTERN xa4000000/mask=xffe0e000\n\n:ld1rqb \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64\n{\n\tZd.B = SVE_ld1rqb(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1rqd_z_p_bi.xml: LD1RQD (scalar plus immediate) variant SVE\n# PATTERN xa5802000/mask=xfff0e000\n\n:ld1rqd \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt4_1_m128to112\n{\n\tZd.D = SVE_ld1rqd(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112);\n}\n\n# ld1rqd_z_p_br.xml: LD1RQD (scalar plus scalar) variant SVE\n# PATTERN xa5800000/mask=xffe0e000\n\n:ld1rqd \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1rqd(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1rqh_z_p_bi.xml: LD1RQH (scalar plus immediate) variant SVE\n# PATTERN xa4802000/mask=xfff0e000\n\n:ld1rqh \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt4_1_m128to112\n{\n\tZd.H = SVE_ld1rqh(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112);\n}\n\n# ld1rqh_z_p_br.xml: LD1RQH (scalar plus scalar) variant SVE\n# PATTERN xa4800000/mask=xffe0e000\n\n:ld1rqh \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ld1rqh(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1rqw_z_p_bi.xml: LD1RQW (scalar plus immediate) variant SVE\n# PATTERN xa5002000/mask=xfff0e000\n\n:ld1rqw \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt4_1_m128to112\n{\n\tZd.S = SVE_ld1rqw(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112);\n}\n\n# ld1rqw_z_p_br.xml: LD1RQW (scalar plus scalar) variant SVE\n# PATTERN xa5000000/mask=xffe0e000\n\n:ld1rqw \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ld1rqw(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1rsb_z_p_bi.xml: LD1RSB variant 16-bit element\n# PATTERN x85c0c000/mask=xffc0e000\n\n:ld1rsb \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt6_1_0to63\n{\n\tZd.H = SVE_ld1rsb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rsb_z_p_bi.xml: LD1RSB variant 32-bit element\n# PATTERN x85c0a000/mask=xffc0e000\n\n:ld1rsb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to63\n{\n\tZd.S = SVE_ld1rsb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rsb_z_p_bi.xml: LD1RSB variant 64-bit element\n# PATTERN x85c08000/mask=xffc0e000\n\n:ld1rsb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to63\n{\n\tZd.D = SVE_ld1rsb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63);\n}\n\n# ld1rsh_z_p_bi.xml: LD1RSH variant 32-bit element\n# PATTERN x8540a000/mask=xffc0e000\n\n:ld1rsh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to126\n{\n\tZd.S = SVE_ld1rsh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126);\n}\n\n# ld1rsh_z_p_bi.xml: LD1RSH variant 64-bit element\n# PATTERN x85408000/mask=xffc0e000\n\n:ld1rsh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to126\n{\n\tZd.D = SVE_ld1rsh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126);\n}\n\n# ld1rsw_z_p_bi.xml: LD1RSW variant SVE\n# PATTERN x84c08000/mask=xffc0e000\n\n:ld1rsw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to252]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to252\n{\n\tZd.D = SVE_ld1rsw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to252);\n}\n\n# ld1rw_z_p_bi.xml: LD1RW variant 32-bit element\n# PATTERN x8540c000/mask=xffc0e000\n\n:ld1rw \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to252]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to252\n{\n\tZd.S = SVE_ld1rw(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to252);\n}\n\n# ld1rw_z_p_bi.xml: LD1RW variant 64-bit element\n# PATTERN x8540e000/mask=xffc0e000\n\n:ld1rw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to252]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to252\n{\n\tZd.D = SVE_ld1rw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to252);\n}\n\n# ld1sb_z_p_ai.xml: LD1SB (vector plus immediate) variant 32-bit element\n# PATTERN x84208000/mask=xffe0e000\n\n:ld1sb \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to31]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31\n{\n\tZd.S = SVE_ld1sb(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31);\n}\n\n# ld1sb_z_p_ai.xml: LD1SB (vector plus immediate) variant 64-bit element\n# PATTERN xc4208000/mask=xffe0e000\n\n:ld1sb \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to31]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31\n{\n\tZd.D = SVE_ld1sb(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31);\n}\n\n# ld1sb_z_p_bi.xml: LD1SB (scalar plus immediate) variant 16-bit element\n# PATTERN xa5c0a000/mask=xfff0e000\n\n:ld1sb \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ld1sb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1sb_z_p_bi.xml: LD1SB (scalar plus immediate) variant 32-bit element\n# PATTERN xa5a0a000/mask=xfff0e000\n\n:ld1sb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ld1sb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1sb_z_p_bi.xml: LD1SB (scalar plus immediate) variant 64-bit element\n# PATTERN xa580a000/mask=xfff0e000\n\n:ld1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1sb_z_p_br.xml: LD1SB (scalar plus scalar) variant 16-bit element\n# PATTERN xa5c04000/mask=xffe0e000\n\n:ld1sb \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ld1sb(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1sb_z_p_br.xml: LD1SB (scalar plus scalar) variant 32-bit element\n# PATTERN xa5a04000/mask=xffe0e000\n\n:ld1sb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ld1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1sb_z_p_br.xml: LD1SB (scalar plus scalar) variant 64-bit element\n# PATTERN xa5804000/mask=xffe0e000\n\n:ld1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1sb_z_p_bz.xml: LD1SB (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4000000/mask=xffa0e000\n\n:ld1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1sb_z_p_bz.xml: LD1SB (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84000000/mask=xffa0e000\n\n:ld1sb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1sb_z_p_bz.xml: LD1SB (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc4408000/mask=xffe0e000\n\n:ld1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1sh_z_p_ai.xml: LD1SH (vector plus immediate) variant 32-bit element\n# PATTERN x84a08000/mask=xffe0e000\n\n:ld1sh \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to62]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62\n{\n\tZd.S = SVE_ld1sh(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62);\n}\n\n# ld1sh_z_p_ai.xml: LD1SH (vector plus immediate) variant 64-bit element\n# PATTERN xc4a08000/mask=xffe0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to62]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62);\n}\n\n# ld1sh_z_p_bi.xml: LD1SH (scalar plus immediate) variant 32-bit element\n# PATTERN xa520a000/mask=xfff0e000\n\n:ld1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1sh_z_p_bi.xml: LD1SH (scalar plus immediate) variant 64-bit element\n# PATTERN xa500a000/mask=xfff0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1sh_z_p_br.xml: LD1SH (scalar plus scalar) variant 32-bit element\n# PATTERN xa5204000/mask=xffe0e000\n\n:ld1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1sh_z_p_br.xml: LD1SH (scalar plus scalar) variant 64-bit element\n# PATTERN xa5004000/mask=xffe0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84a00000/mask=xffa0e000\n\n:ld1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^\" #1\"]\nis sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4a00000/mask=xffa0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4800000/mask=xffa0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84800000/mask=xffa0e000\n\n:ld1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc4e08000/mask=xffe0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc4c08000/mask=xffe0e000\n\n:ld1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1sw_z_p_ai.xml: LD1SW (vector plus immediate) variant SVE\n# PATTERN xc5208000/mask=xffe0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to124]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124);\n}\n\n# ld1sw_z_p_bi.xml: LD1SW (scalar plus immediate) variant SVE\n# PATTERN xa480a000/mask=xfff0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1sw_z_p_br.xml: LD1SW (scalar plus scalar) variant SVE\n# PATTERN xa4804000/mask=xffe0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc5200000/mask=xffa0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc5000000/mask=xffa0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc5608000/mask=xffe0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc5408000/mask=xffe0e000\n\n:ld1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1w_z_p_ai.xml: LD1W (vector plus immediate) variant 32-bit element\n# PATTERN x8520c000/mask=xffe0e000\n\n:ld1w \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to124]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to124\n{\n\tZd.S = SVE_ld1w(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to124);\n}\n\n# ld1w_z_p_ai.xml: LD1W (vector plus immediate) variant 64-bit element\n# PATTERN xc520c000/mask=xffe0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to124]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124);\n}\n\n# ld1w_z_p_bi.xml: LD1W (scalar plus immediate) variant 32-bit element\n# PATTERN xa540a000/mask=xfff0e000\n\n:ld1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1w_z_p_bi.xml: LD1W (scalar plus immediate) variant 64-bit element\n# PATTERN xa560a000/mask=xfff0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ld1w_z_p_br.xml: LD1W (scalar plus scalar) variant 32-bit element\n# PATTERN xa5404000/mask=xffe0e000\n\n:ld1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1w_z_p_br.xml: LD1W (scalar plus scalar) variant 64-bit element\n# PATTERN xa5604000/mask=xffe0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x85204000/mask=xffa0e000\n\n:ld1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^\" #2\"]\nis sve_b_2331=0b100001010 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc5204000/mask=xffa0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc5004000/mask=xffa0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x85004000/mask=xffa0e000\n\n:ld1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc560c000/mask=xffe0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc540c000/mask=xffe0e000\n\n:ld1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ld2b_z_p_bi.xml: LD2B (scalar plus immediate) variant SVE\n# PATTERN xa420e000/mask=xfff0e000\n\n:ld2b \"{\"^Zt.B, Ztt.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14\n{\n\tZt.B = SVE_ld2b(Zt.B, Ztt.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# ld2b_z_p_br.xml: LD2B (scalar plus scalar) variant SVE\n# PATTERN xa420c000/mask=xffe0e000\n\n:ld2b \"{\"^Zt.B, Ztt.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.B = SVE_ld2b(Zt.B, Ztt.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld2d_z_p_bi.xml: LD2D (scalar plus immediate) variant SVE\n# PATTERN xa5a0e000/mask=xfff0e000\n\n:ld2d \"{\"^Zt.D, Ztt.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14\n{\n\tZt.D = SVE_ld2d(Zt.D, Ztt.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# ld2d_z_p_br.xml: LD2D (scalar plus scalar) variant SVE\n# PATTERN xa5a0c000/mask=xffe0e000\n\n:ld2d \"{\"^Zt.D, Ztt.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.D = SVE_ld2d(Zt.D, Ztt.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld2h_z_p_bi.xml: LD2H (scalar plus immediate) variant SVE\n# PATTERN xa4a0e000/mask=xfff0e000\n\n:ld2h \"{\"^Zt.H, Ztt.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14\n{\n\tZt.H = SVE_ld2h(Zt.H, Ztt.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# ld2h_z_p_br.xml: LD2H (scalar plus scalar) variant SVE\n# PATTERN xa4a0c000/mask=xffe0e000\n\n:ld2h \"{\"^Zt.H, Ztt.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.H = SVE_ld2h(Zt.H, Ztt.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld2w_z_p_bi.xml: LD2W (scalar plus immediate) variant SVE\n# PATTERN xa520e000/mask=xfff0e000\n\n:ld2w \"{\"^Zt.S, Ztt.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14\n{\n\tZt.S = SVE_ld2w(Zt.S, Ztt.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# ld2w_z_p_br.xml: LD2W (scalar plus scalar) variant SVE\n# PATTERN xa520c000/mask=xffe0e000\n\n:ld2w \"{\"^Zt.S, Ztt.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.S = SVE_ld2w(Zt.S, Ztt.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld3b_z_p_bi.xml: LD3B (scalar plus immediate) variant SVE\n# PATTERN xa440e000/mask=xfff0e000\n\n:ld3b \"{\"^Zt.B, Ztt.B, Zttt.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21\n{\n\tZt.B = SVE_ld3b(Zt.B, Ztt.B, Zttt.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# ld3b_z_p_br.xml: LD3B (scalar plus scalar) variant SVE\n# PATTERN xa440c000/mask=xffe0e000\n\n:ld3b \"{\"^Zt.B, Ztt.B, Zttt.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.B = SVE_ld3b(Zt.B, Ztt.B, Zttt.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld3d_z_p_bi.xml: LD3D (scalar plus immediate) variant SVE\n# PATTERN xa5c0e000/mask=xfff0e000\n\n:ld3d \"{\"^Zt.D, Ztt.D, Zttt.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21\n{\n\tZt.D = SVE_ld3d(Zt.D, Ztt.D, Zttt.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# ld3d_z_p_br.xml: LD3D (scalar plus scalar) variant SVE\n# PATTERN xa5c0c000/mask=xffe0e000\n\n:ld3d \"{\"^Zt.D, Ztt.D, Zttt.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.D = SVE_ld3d(Zt.D, Ztt.D, Zttt.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld3h_z_p_bi.xml: LD3H (scalar plus immediate) variant SVE\n# PATTERN xa4c0e000/mask=xfff0e000\n\n:ld3h \"{\"^Zt.H, Ztt.H, Zttt.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21\n{\n\tZt.H = SVE_ld3h(Zt.H, Ztt.H, Zttt.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# ld3h_z_p_br.xml: LD3H (scalar plus scalar) variant SVE\n# PATTERN xa4c0c000/mask=xffe0e000\n\n:ld3h \"{\"^Zt.H, Ztt.H, Zttt.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.H = SVE_ld3h(Zt.H, Ztt.H, Zttt.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld3w_z_p_bi.xml: LD3W (scalar plus immediate) variant SVE\n# PATTERN xa540e000/mask=xfff0e000\n\n:ld3w \"{\"^Zt.S, Ztt.S, Zttt.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21\n{\n\tZt.S = SVE_ld3w(Zt.S, Ztt.S, Zttt.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# ld3w_z_p_br.xml: LD3W (scalar plus scalar) variant SVE\n# PATTERN xa540c000/mask=xffe0e000\n\n:ld3w \"{\"^Zt.S, Ztt.S, Zttt.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.S = SVE_ld3w(Zt.S, Ztt.S, Zttt.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld4b_z_p_bi.xml: LD4B (scalar plus immediate) variant SVE\n# PATTERN xa460e000/mask=xfff0e000\n\n:ld4b \"{\"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28\n{\n\tZt.B = SVE_ld4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# ld4b_z_p_br.xml: LD4B (scalar plus scalar) variant SVE\n# PATTERN xa460c000/mask=xffe0e000\n\n:ld4b \"{\"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.B = SVE_ld4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld4d_z_p_bi.xml: LD4D (scalar plus immediate) variant SVE\n# PATTERN xa5e0e000/mask=xfff0e000\n\n:ld4d \"{\"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28\n{\n\tZt.D = SVE_ld4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# ld4d_z_p_br.xml: LD4D (scalar plus scalar) variant SVE\n# PATTERN xa5e0c000/mask=xffe0e000\n\n:ld4d \"{\"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.D = SVE_ld4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld4h_z_p_bi.xml: LD4H (scalar plus immediate) variant SVE\n# PATTERN xa4e0e000/mask=xfff0e000\n\n:ld4h \"{\"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28\n{\n\tZt.H = SVE_ld4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# ld4h_z_p_br.xml: LD4H (scalar plus scalar) variant SVE\n# PATTERN xa4e0c000/mask=xffe0e000\n\n:ld4h \"{\"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.H = SVE_ld4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ld4w_z_p_bi.xml: LD4W (scalar plus immediate) variant SVE\n# PATTERN xa560e000/mask=xfff0e000\n\n:ld4w \"{\"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28\n{\n\tZt.S = SVE_ld4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# ld4w_z_p_br.xml: LD4W (scalar plus scalar) variant SVE\n# PATTERN xa560c000/mask=xffe0e000\n\n:ld4w \"{\"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & Pg3_z & Rm_GPR64\n{\n\tZt.S = SVE_ld4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1b_z_p_ai.xml: LDFF1B (vector plus immediate) variant 32-bit element\n# PATTERN x8420e000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to31]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31\n{\n\tZd.S = SVE_ldff1b(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31);\n}\n\n# ldff1b_z_p_ai.xml: LDFF1B (vector plus immediate) variant 64-bit element\n# PATTERN xc420e000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to31]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31\n{\n\tZd.D = SVE_ldff1b(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31);\n}\n\n# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 8-bit element\n# PATTERN xa4006000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64\n{\n\tZd.B = SVE_ldff1b(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 16-bit element\n# PATTERN xa4206000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ldff1b(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 32-bit element\n# PATTERN xa4406000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ldff1b(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 64-bit element\n# PATTERN xa4606000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1b(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1b_z_p_bz.xml: LDFF1B (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4006000/mask=xffa0e000\n\n:ldff1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1b_z_p_bz.xml: LDFF1B (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84006000/mask=xffa0e000\n\n:ldff1b \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1b(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1b_z_p_bz.xml: LDFF1B (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc440e000/mask=xffe0e000\n\n:ldff1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1d_z_p_ai.xml: LDFF1D (vector plus immediate) variant SVE\n# PATTERN xc5a0e000/mask=xffe0e000\n\n:ldff1d \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to248]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to248\n{\n\tZd.D = SVE_ldff1d(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to248);\n}\n\n# ldff1d_z_p_br.xml: LDFF1D (scalar plus scalar) variant SVE\n# PATTERN xa5e06000/mask=xffe0e000\n\n:ldff1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc5a06000/mask=xffa0e000\n\n:ldff1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #3\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc5806000/mask=xffa0e000\n\n:ldff1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc5e0e000/mask=xffe0e000\n\n:ldff1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #3\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc5c0e000/mask=xffe0e000\n\n:ldff1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1h_z_p_ai.xml: LDFF1H (vector plus immediate) variant 32-bit element\n# PATTERN x84a0e000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to62]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62\n{\n\tZd.S = SVE_ldff1h(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62);\n}\n\n# ldff1h_z_p_ai.xml: LDFF1H (vector plus immediate) variant 64-bit element\n# PATTERN xc4a0e000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to62]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62\n{\n\tZd.D = SVE_ldff1h(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62);\n}\n\n# ldff1h_z_p_br.xml: LDFF1H (scalar plus scalar) variant 16-bit element\n# PATTERN xa4a06000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ldff1h(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1h_z_p_br.xml: LDFF1H (scalar plus scalar) variant 32-bit element\n# PATTERN xa4c06000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ldff1h(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1h_z_p_br.xml: LDFF1H (scalar plus scalar) variant 64-bit element\n# PATTERN xa4e06000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84a06000/mask=xffa0e000\n\n:ldff1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^\" #1\"]\nis sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4a06000/mask=xffa0e000\n\n:ldff1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4806000/mask=xffa0e000\n\n:ldff1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84806000/mask=xffa0e000\n\n:ldff1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc4e0e000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc4c0e000/mask=xffe0e000\n\n:ldff1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1sb_z_p_ai.xml: LDFF1SB (vector plus immediate) variant 32-bit element\n# PATTERN x8420a000/mask=xffe0e000\n\n:ldff1sb \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to31]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31\n{\n\tZd.S = SVE_ldff1sb(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31);\n}\n\n# ldff1sb_z_p_ai.xml: LDFF1SB (vector plus immediate) variant 64-bit element\n# PATTERN xc420a000/mask=xffe0e000\n\n:ldff1sb \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to31]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31\n{\n\tZd.D = SVE_ldff1sb(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31);\n}\n\n# ldff1sb_z_p_br.xml: LDFF1SB (scalar plus scalar) variant 16-bit element\n# PATTERN xa5c06000/mask=xffe0e000\n\n:ldff1sb \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ldff1sb(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1sb_z_p_br.xml: LDFF1SB (scalar plus scalar) variant 32-bit element\n# PATTERN xa5a06000/mask=xffe0e000\n\n:ldff1sb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ldff1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1sb_z_p_br.xml: LDFF1SB (scalar plus scalar) variant 64-bit element\n# PATTERN xa5806000/mask=xffe0e000\n\n:ldff1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1sb_z_p_bz.xml: LDFF1SB (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4002000/mask=xffa0e000\n\n:ldff1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1sb_z_p_bz.xml: LDFF1SB (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84002000/mask=xffa0e000\n\n:ldff1sb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1sb_z_p_bz.xml: LDFF1SB (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc440a000/mask=xffe0e000\n\n:ldff1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1sh_z_p_ai.xml: LDFF1SH (vector plus immediate) variant 32-bit element\n# PATTERN x84a0a000/mask=xffe0e000\n\n:ldff1sh \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to62]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62\n{\n\tZd.S = SVE_ldff1sh(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62);\n}\n\n# ldff1sh_z_p_ai.xml: LDFF1SH (vector plus immediate) variant 64-bit element\n# PATTERN xc4a0a000/mask=xffe0e000\n\n:ldff1sh \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to62]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62\n{\n\tZd.D = SVE_ldff1sh(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62);\n}\n\n# ldff1sh_z_p_br.xml: LDFF1SH (scalar plus scalar) variant 32-bit element\n# PATTERN xa5206000/mask=xffe0e000\n\n:ldff1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ldff1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1sh_z_p_br.xml: LDFF1SH (scalar plus scalar) variant 64-bit element\n# PATTERN xa5006000/mask=xffe0e000\n\n:ldff1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84a02000/mask=xffa0e000\n\n:ldff1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^\" #1\"]\nis sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4a02000/mask=xffa0e000\n\n:ldff1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc4802000/mask=xffa0e000\n\n:ldff1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x84802000/mask=xffa0e000\n\n:ldff1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc4e0a000/mask=xffe0e000\n\n:ldff1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #1\"]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc4c0a000/mask=xffe0e000\n\n:ldff1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1sw_z_p_ai.xml: LDFF1SW (vector plus immediate) variant SVE\n# PATTERN xc520a000/mask=xffe0e000\n\n:ldff1sw \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to124]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124\n{\n\tZd.D = SVE_ldff1sw(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124);\n}\n\n# ldff1sw_z_p_br.xml: LDFF1SW (scalar plus scalar) variant SVE\n# PATTERN xa4806000/mask=xffe0e000\n\n:ldff1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc5202000/mask=xffa0e000\n\n:ldff1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc5002000/mask=xffa0e000\n\n:ldff1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc560a000/mask=xffe0e000\n\n:ldff1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc540a000/mask=xffe0e000\n\n:ldff1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1w_z_p_ai.xml: LDFF1W (vector plus immediate) variant 32-bit element\n# PATTERN x8520e000/mask=xffe0e000\n\n:ldff1w \"{\"^Zd.S^\"}\", Pg3_z, [Zn.S^sve_opt5_1_0to124]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to124\n{\n\tZd.S = SVE_ldff1w(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to124);\n}\n\n# ldff1w_z_p_ai.xml: LDFF1W (vector plus immediate) variant 64-bit element\n# PATTERN xc520e000/mask=xffe0e000\n\n:ldff1w \"{\"^Zd.D^\"}\", Pg3_z, [Zn.D^sve_opt5_1_0to124]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124\n{\n\tZd.D = SVE_ldff1w(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124);\n}\n\n# ldff1w_z_p_br.xml: LDFF1W (scalar plus scalar) variant 32-bit element\n# PATTERN xa5406000/mask=xffe0e000\n\n:ldff1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ldff1w(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1w_z_p_br.xml: LDFF1W (scalar plus scalar) variant 64-bit element\n# PATTERN xa5606000/mask=xffe0e000\n\n:ldff1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x85206000/mask=xffa0e000\n\n:ldff1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^\" #2\"]\nis sve_b_2331=0b100001010 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc5206000/mask=xffa0e000\n\n:ldff1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^\" #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xc5006000/mask=xffa0e000\n\n:ldff1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod\n{\n\tZd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN x85006000/mask=xffa0e000\n\n:ldff1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod\n{\n\tZd.S = SVE_ldff1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc560e000/mask=xffe0e000\n\n:ldff1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D, \"lsl #2\"]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xc540e000/mask=xffe0e000\n\n:ldff1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D\n{\n\tZd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D);\n}\n\n# ldnf1b_z_p_bi.xml: LDNF1B variant 8-bit element\n# PATTERN xa410a000/mask=xfff0e000\n\n:ldnf1b \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_mul4_1_m8to7\n{\n\tZd.B = SVE_ldnf1b(Zd.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1b_z_p_bi.xml: LDNF1B variant 16-bit element\n# PATTERN xa430a000/mask=xfff0e000\n\n:ldnf1b \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ldnf1b(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1b_z_p_bi.xml: LDNF1B variant 32-bit element\n# PATTERN xa450a000/mask=xfff0e000\n\n:ldnf1b \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ldnf1b(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1b_z_p_bi.xml: LDNF1B variant 64-bit element\n# PATTERN xa470a000/mask=xfff0e000\n\n:ldnf1b \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1b(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1d_z_p_bi.xml: LDNF1D variant SVE\n# PATTERN xa5f0a000/mask=xfff0e000\n\n:ldnf1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1d(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1h_z_p_bi.xml: LDNF1H variant 16-bit element\n# PATTERN xa4b0a000/mask=xfff0e000\n\n:ldnf1h \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ldnf1h(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1h_z_p_bi.xml: LDNF1H variant 32-bit element\n# PATTERN xa4d0a000/mask=xfff0e000\n\n:ldnf1h \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ldnf1h(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1h_z_p_bi.xml: LDNF1H variant 64-bit element\n# PATTERN xa4f0a000/mask=xfff0e000\n\n:ldnf1h \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1h(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1sb_z_p_bi.xml: LDNF1SB variant 16-bit element\n# PATTERN xa5d0a000/mask=xfff0e000\n\n:ldnf1sb \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ldnf1sb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1sb_z_p_bi.xml: LDNF1SB variant 32-bit element\n# PATTERN xa5b0a000/mask=xfff0e000\n\n:ldnf1sb \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ldnf1sb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1sb_z_p_bi.xml: LDNF1SB variant 64-bit element\n# PATTERN xa590a000/mask=xfff0e000\n\n:ldnf1sb \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1sb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1sh_z_p_bi.xml: LDNF1SH variant 32-bit element\n# PATTERN xa530a000/mask=xfff0e000\n\n:ldnf1sh \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ldnf1sh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1sh_z_p_bi.xml: LDNF1SH variant 64-bit element\n# PATTERN xa510a000/mask=xfff0e000\n\n:ldnf1sh \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1sh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1sw_z_p_bi.xml: LDNF1SW variant SVE\n# PATTERN xa490a000/mask=xfff0e000\n\n:ldnf1sw \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1sw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1w_z_p_bi.xml: LDNF1W variant 32-bit element\n# PATTERN xa550a000/mask=xfff0e000\n\n:ldnf1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ldnf1w(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnf1w_z_p_bi.xml: LDNF1W variant 64-bit element\n# PATTERN xa570a000/mask=xfff0e000\n\n:ldnf1w \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnf1w(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnt1b_z_p_bi.xml: LDNT1B (scalar plus immediate) variant SVE\n# PATTERN xa400e000/mask=xfff0e000\n\n:ldnt1b \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_mul4_1_m8to7\n{\n\tZd.B = SVE_ldnt1b(Zd.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnt1b_z_p_br.xml: LDNT1B (scalar plus scalar) variant SVE\n# PATTERN xa400c000/mask=xffe0e000\n\n:ldnt1b \"{\"^Zd.B^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64\n{\n\tZd.B = SVE_ldnt1b(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldnt1d_z_p_bi.xml: LDNT1D (scalar plus immediate) variant SVE\n# PATTERN xa580e000/mask=xfff0e000\n\n:ldnt1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7\n{\n\tZd.D = SVE_ldnt1d(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnt1d_z_p_br.xml: LDNT1D (scalar plus scalar) variant SVE\n# PATTERN xa580c000/mask=xffe0e000\n\n:ldnt1d \"{\"^Zd.D^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64\n{\n\tZd.D = SVE_ldnt1d(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldnt1h_z_p_bi.xml: LDNT1H (scalar plus immediate) variant SVE\n# PATTERN xa480e000/mask=xfff0e000\n\n:ldnt1h \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7\n{\n\tZd.H = SVE_ldnt1h(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnt1h_z_p_br.xml: LDNT1H (scalar plus scalar) variant SVE\n# PATTERN xa480c000/mask=xffe0e000\n\n:ldnt1h \"{\"^Zd.H^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64\n{\n\tZd.H = SVE_ldnt1h(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldnt1w_z_p_bi.xml: LDNT1W (scalar plus immediate) variant SVE\n# PATTERN xa500e000/mask=xfff0e000\n\n:ldnt1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7\n{\n\tZd.S = SVE_ldnt1w(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# ldnt1w_z_p_br.xml: LDNT1W (scalar plus scalar) variant SVE\n# PATTERN xa500c000/mask=xffe0e000\n\n:ldnt1w \"{\"^Zd.S^\"}\", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64\n{\n\tZd.S = SVE_ldnt1w(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# ldr_p_bi.xml: LDR (predicate) variant SVE\n# PATTERN x85800000/mask=xffc0e010\n\n:ldr Pd, [Rn_GPR64xsp^sve_mul9_2_m256to255]\nis sve_b_2231=0b1000010110 & sve_imm9h_1621 & sve_b_1315=0b000 & sve_imm9l_1012 & sve_rn_0509 & sve_b_04=0 & sve_pt_0003 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Pd\n{\n\tPd = SVE_ldr(Pd, Rn_GPR64xsp, sve_mul9_2_m256to255);\n}\n\n# ldr_z_bi.xml: LDR (vector) variant SVE\n# PATTERN x85804000/mask=xffc0e000\n\n:ldr Zd, [Rn_GPR64xsp^sve_mul9_2_m256to255]\nis sve_b_2231=0b1000010110 & sve_imm9h_1621 & sve_b_1315=0b010 & sve_imm9l_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Zd\n{\n\tZd = SVE_ldr(Zd, Rn_GPR64xsp, sve_mul9_2_m256to255);\n}\n\n# lsl_z_p_zi.xml: LSL (immediate, predicated) variant SVE\n# PATTERN x04038000/mask=xff3fe000\n\n:lsl Zd.T_tszh, Pg3_m, Zd.T_tszh_2, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m\n{\n\tZd.T_tszh = SVE_lsl(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1);\n}\n\n# lsl_z_p_zw.xml: LSL (wide elements, predicated) variant SVE\n# PATTERN x041b8000/mask=xff3fe000\n\n:lsl Zd.T, Pg3_m, Zd.T_2, Zn.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D\n{\n\tZd.T = SVE_lsl(Zd.T, Pg3_m, Zd.T_2, Zn.D);\n}\n\n# lsl_z_p_zz.xml: LSL (vectors) variant SVE\n# PATTERN x04138000/mask=xff3fe000\n\n:lsl Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_lsl(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# lsl_z_zi.xml: LSL (immediate, unpredicated) variant SVE\n# PATTERN x04209c00/mask=xff20fc00\n\n:lsl Zd.T_tszh, Zn.T_tszh, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=1 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh\n{\n\tZd.T_tszh = SVE_lsl(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1);\n}\n\n# lsl_z_zw.xml: LSL (wide elements, unpredicated) variant SVE\n# PATTERN x04208c00/mask=xff20fc00\n\n:lsl Zd.T, Zn.T, Zm.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=1 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D\n{\n\tZd.T = SVE_lsl(Zd.T, Zn.T, Zm.D);\n}\n\n# lslr_z_p_zz.xml: LSLR variant SVE\n# PATTERN x04178000/mask=xff3fe000\n\n:lslr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_lslr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# lsr_z_p_zi.xml: LSR (immediate, predicated) variant SVE\n# PATTERN x04018000/mask=xff3fe000\n\n:lsr Zd.T_tszh, Pg3_m, Zd.T_tszh_2, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m\n{\n\tZd.T_tszh = SVE_lsr(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1);\n}\n\n# lsr_z_p_zw.xml: LSR (wide elements, predicated) variant SVE\n# PATTERN x04198000/mask=xff3fe000\n\n:lsr Zd.T, Pg3_m, Zd.T_2, Zn.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D\n{\n\tZd.T = SVE_lsr(Zd.T, Pg3_m, Zd.T_2, Zn.D);\n}\n\n# lsr_z_p_zz.xml: LSR (vectors) variant SVE\n# PATTERN x04118000/mask=xff3fe000\n\n:lsr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_lsr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# lsr_z_zi.xml: LSR (immediate, unpredicated) variant SVE\n# PATTERN x04209400/mask=xff20fc00\n\n:lsr Zd.T_tszh, Zn.T_tszh, \"#\"^sve_imm_shift\nis sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=0 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh\n{\n\tZd.T_tszh = SVE_lsr(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1);\n}\n\n# lsr_z_zw.xml: LSR (wide elements, unpredicated) variant SVE\n# PATTERN x04208400/mask=xff20fc00\n\n:lsr Zd.T, Zn.T, Zm.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=0 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D\n{\n\tZd.T = SVE_lsr(Zd.T, Zn.T, Zm.D);\n}\n\n# lsrr_z_p_zz.xml: LSRR variant SVE\n# PATTERN x04158000/mask=xff3fe000\n\n:lsrr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_lsrr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# mad_z_p_zzz.xml: MAD variant SVE\n# PATTERN x0400c000/mask=xff20e000\n\n:mad Zd.T, Pg3_m, Zm.T, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b11 & sve_b_13=0 & sve_pg_1012 & sve_za_0509 & sve_zdn_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_mad(Zd.T, Pg3_m, Zm.T, Zn.T);\n}\n\n# mla_z_p_zzz.xml: MLA variant SVE\n# PATTERN x04004000/mask=xff20e000\n\n:mla Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b01 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_mla(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# mls_z_p_zzz.xml: MLS variant SVE\n# PATTERN x04006000/mask=xff20e000\n\n:mls Zd.T, Pg3_m, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b01 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_mls(Zd.T, Pg3_m, Zn.T, Zm.T);\n}\n\n# mov_and_p_p_pp.xml: MOV (predicate, predicated, zeroing) variant Not flag setting\n# ALIASEDBY AND .B, /Z, .B, .B if S == '0' && Pn == Pm\n# PATTERN x25004000/mask=xfff0c210\n\n# SKIPPING mov_and_p_p_pp.xml because x25004000/mask=xfff0c210 has already been defined\n\n# mov_cpy_z_p_i.xml: MOV (immediate, predicated) variant SVE\n# ALIASEDBY CPY ., /, #{, } if Unconditionally\n# PATTERN x05100000/mask=xff308000\n\n# SKIPPING mov_cpy_z_p_i.xml because x05100000/mask=xff308000 has already been defined\n\n# mov_cpy_z_p_r.xml: MOV (scalar, predicated) variant SVE\n# ALIASEDBY CPY ., /M, if Unconditionally\n# PATTERN x0528a000/mask=xff3fe000\n\n# SKIPPING mov_cpy_z_p_r.xml because x0528a000/mask=xff3fe000 has already been defined\n\n# mov_cpy_z_p_v.xml: MOV (SIMD&FP scalar, predicated) variant SVE\n# ALIASEDBY CPY ., /M, if Unconditionally\n# PATTERN x05208000/mask=xff3fe000\n\n# SKIPPING mov_cpy_z_p_v.xml because x05208000/mask=xff3fe000 has already been defined\n\n# mov_dup_z_i.xml: MOV (immediate, unpredicated) variant SVE\n# ALIASEDBY DUP ., #{, } if Unconditionally\n# PATTERN x2538c000/mask=xff3fc000\n\n# SKIPPING mov_dup_z_i.xml because x2538c000/mask=xff3fc000 has already been defined\n\n# mov_dup_z_r.xml: MOV (scalar, unpredicated) variant SVE\n# ALIASEDBY DUP ., if Unconditionally\n# PATTERN x05203800/mask=xff3ffc00\n\n# SKIPPING mov_dup_z_r.xml because x05203800/mask=xff3ffc00 has already been defined\n\n# mov_dup_z_zi.xml: MOV (SIMD&FP scalar, unpredicated) variant SVE\n# ALIASEDBY DUP ., .[0] if BitCount(imm2:tsz) == 1\n# ALIASEDBY DUP ., .[] if BitCount(imm2:tsz) > 1\n# PATTERN \n\n# SKIPPING mov_dup_z_zi.xml because there is a mismatch between the XML asmtemplate(4) and regdiagram(1)\n\n# mov_dupm_z_i.xml: MOV (bitmask immediate) variant SVE\n# ALIASEDBY DUPM ., # if SVEMoveMaskPreferred(imm13)\n# PATTERN x05c00000/mask=xfffc0000\n\n# SKIPPING mov_dupm_z_i.xml because x05c00000/mask=xfffc0000 has already been defined\n\n# mov_orr_p_p_pp.xml: MOV (predicate, unpredicated) variant Not flag setting\n# ALIASEDBY ORR .B, /Z, .B, .B if S == '0' && Pn == Pm && Pm == Pg\n# PATTERN x25804000/mask=xfff0c210\n\n# SKIPPING mov_orr_p_p_pp.xml because it is an alias:\n\n# mov_orr_z_zz.xml: MOV (vector, unpredicated) variant SVE\n# ALIASEDBY ORR .D, .D, .D if Zn == Zm\n# PATTERN x04603000/mask=xffe0fc00\n\n# SKIPPING mov_orr_z_zz.xml because it is an alias:\n\n# mov_sel_p_p_pp.xml: MOV (predicate, predicated, merging) variant SVE\n# ALIASEDBY SEL .B, , .B, .B if Pd == Pm\n# PATTERN x25004210/mask=xfff0c210\n\n# SKIPPING mov_sel_p_p_pp.xml because it is an alias:\n\n# mov_sel_z_p_zz.xml: MOV (vector, predicated) variant SVE\n# ALIASEDBY SEL ., , ., . if Zd == Zm\n# PATTERN x0520c000/mask=xff20c000\n\n# SKIPPING mov_sel_z_p_zz.xml because it is an alias:\n\n# movprfx_z_p_z.xml: MOVPRFX (predicated) variant SVE\n# PATTERN x04102000/mask=xff3ee000\n\n:movprfx Zd.T, Pg3_zm, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_m_16 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Pg3_zm & Zd.T & Zn.T\n{\n\tZd.T = SVE_movprfx(Zd.T, Pg3_zm, Zn.T);\n}\n\n# movprfx_z_z.xml: MOVPRFX (unpredicated) variant SVE\n# PATTERN x0420bc00/mask=xfffffc00\n\n:movprfx Zd, Zn\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_1720=0b0000 & sve_b_16=0 & sve_b_1015=0b101111 & sve_zn_0509 & sve_zd_0004 & Zn & Zd\n{\n\tZd = SVE_movprfx(Zd, Zn);\n}\n\n# movs_and_p_p_pp.xml: MOVS (predicated) variant Flag setting\n# ALIASEDBY ANDS .B, /Z, .B, .B if S == '1' && Pn == Pm\n# PATTERN x25404000/mask=xfff0c210\n\n# SKIPPING movs_and_p_p_pp.xml because x25404000/mask=xfff0c210 has already been defined\n\n# movs_orr_p_p_pp.xml: MOVS (unpredicated) variant Flag setting\n# ALIASEDBY ORRS .B, /Z, .B, .B if S == '1' && Pn == Pm && Pm == Pg\n# PATTERN x25c04000/mask=xfff0c210\n\n# SKIPPING movs_orr_p_p_pp.xml because it is an alias:\n\n# msb_z_p_zzz.xml: MSB variant SVE\n# PATTERN x0400e000/mask=xff20e000\n\n:msb Zd.T, Pg3_m, Zm.T, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b11 & sve_b_13=1 & sve_pg_1012 & sve_za_0509 & sve_zdn_0004 & Zd.T & Zm.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_msb(Zd.T, Pg3_m, Zm.T, Zn.T);\n}\n\n# mul_z_p_zz.xml: MUL (vectors) variant SVE\n# PATTERN x04100000/mask=xff3fe000\n\n:mul Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_mul(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# mul_z_zi.xml: MUL (immediate) variant SVE\n# PATTERN x2530c000/mask=xff3fe000\n\n:mul Zd.T, Zd.T_2, \"#\"^sve_imm8_1_m128to127\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b110 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_m128to127\n{\n\tZd.T = SVE_mul(Zd.T, Zd.T_2, sve_imm8_1_m128to127:1);\n}\n\n# nand_p_p_pp.xml: NAND, NANDS variant Flag setting\n# PATTERN x25c04210/mask=xfff0c210\n\n:nands Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_nands(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# nand_p_p_pp.xml: NAND, NANDS variant Not flag setting\n# PATTERN x25804210/mask=xfff0c210\n\n:nand Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_nand(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# neg_z_p_z.xml: NEG variant SVE\n# PATTERN x0417a000/mask=xff3fe000\n\n:neg Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_neg(Zd.T, Pg3_m, Zn.T);\n}\n\n# nor_p_p_pp.xml: NOR, NORS variant Flag setting\n# PATTERN x25c04200/mask=xfff0c210\n\n:nors Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_nors(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# nor_p_p_pp.xml: NOR, NORS variant Not flag setting\n# PATTERN x25804200/mask=xfff0c210\n\n:nor Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_nor(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# not_eor_p_p_pp.xml: NOT (predicate) variant Not flag setting\n# ALIASEDBY EOR .B, /Z, .B, .B if Pm == Pg\n# PATTERN x25004200/mask=xfff0c210\n\n# SKIPPING not_eor_p_p_pp.xml because x25004200/mask=xfff0c210 has already been defined\n\n# not_z_p_z.xml: NOT (vector) variant SVE\n# PATTERN x041ea000/mask=xff3fe000\n\n:not Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_not(Zd.T, Pg3_m, Zn.T);\n}\n\n# nots_eor_p_p_pp.xml: NOTS variant Flag setting\n# ALIASEDBY EORS .B, /Z, .B, .B if Pm == Pg\n# PATTERN x25404200/mask=xfff0c210\n\n# SKIPPING nots_eor_p_p_pp.xml because x25404200/mask=xfff0c210 has already been defined\n\n# orn_orr_z_zi.xml: ORN (immediate) variant SVE\n# ALIASEDBY ORR ., ., #(- - 1) if Never\n# PATTERN x05000000/mask=xfffc0000\n\n:orn Zd.T_imm13, Zd.T_imm13_2, \"#\"^sve_decode_bit_mask\nis sve_b_2431=0b00000101 & sve_b_23=0 & sve_b_22=0 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2\n{\n\tZd.T_imm13 = SVE_orn(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1);\n}\n\n# orn_p_p_pp.xml: ORN, ORNS (predicates) variant Flag setting\n# PATTERN x25c04010/mask=xfff0c210\n\n:orns Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_orns(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# orn_p_p_pp.xml: ORN, ORNS (predicates) variant Not flag setting\n# PATTERN x25804010/mask=xfff0c210\n\n:orn Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_orn(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# orr_p_p_pp.xml: ORR, ORRS (predicates) variant Flag setting\n# PATTERN x25c04000/mask=xfff0c210\n\n:orrs Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_s_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_orrs(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# orr_p_p_pp.xml: ORR, ORRS (predicates) variant Not flag setting\n# PATTERN x25804000/mask=xfff0c210\n\n:orr Pd.B, Pg_z, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=1 & sve_s_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B\n{\n\tPd.B = SVE_orr(Pd.B, Pg_z, Pn.B, Pm.B);\n}\n\n# orr_z_p_zz.xml: ORR (vectors, predicated) variant SVE\n# PATTERN x04180000/mask=xff3fe000\n\n:orr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_orr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# orr_z_zi.xml: ORR (immediate) variant SVE\n# PATTERN x05000000/mask=xfffc0000\n\n# SKIPPING orr_z_zi.xml because x05000000/mask=xfffc0000 has already been defined\n\n# orr_z_zz.xml: ORR (vectors, unpredicated) variant SVE\n# PATTERN x04603000/mask=xffe0fc00\n\n:orr Zd.D, Zn.D, Zm.D\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D\n{\n\tZd.D = SVE_orr(Zd.D, Zn.D, Zm.D);\n}\n\n# orv_r_p_z.xml: ORV variant SVE\n# PATTERN x04182000/mask=xff3fe000\n\n:orv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_orv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# orv_r_p_z.xml: ORV variant SVE\n# PATTERN x04182000/mask=xff3fe000\n\n:orv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_orv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# orv_r_p_z.xml: ORV variant SVE\n# PATTERN x04182000/mask=xff3fe000\n\n:orv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_orv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# orv_r_p_z.xml: ORV variant SVE\n# PATTERN x04182000/mask=xff3fe000\n\n:orv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_orv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# pfalse_p.xml: PFALSE variant SVE\n# PATTERN x2518e400/mask=xfffffff0\n\n:pfalse Pd.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1021=0b011000111001 & sve_b_0409=0b000000 & sve_pd_0003 & Pd.B\n{\n\tPd.B = SVE_pfalse(Pd.B);\n}\n\n# pfirst_p_p_p.xml: PFIRST variant SVE\n# PATTERN x2558c000/mask=xfffffe10\n\n:pfirst Pd.B, Pn, Pd.B_2\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1021=0b011000110000 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pdn_0003 & Pd.B & Pd.B_2 & Pn\n{\n\tPd.B = SVE_pfirst(Pd.B, Pn, Pd.B_2);\n}\n\n# pnext_p_p_p.xml: PNEXT variant SVE\n# PATTERN x2519c400/mask=xff3ffe10\n\n:pnext Pd.T, Pn, Pd.T_2\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1021=0b011001110001 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pdn_0003 & Pd.T & Pd.T_2 & Pn\n{\n\tPd.T = SVE_pnext(Pd.T, Pn, Pd.T_2);\n}\n\n# prfb_i_p_ai.xml: PRFB (vector plus immediate) variant 32-bit element\n# PATTERN x8400e000/mask=xffe0e010\n\n:prfb sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to31]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to31 & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to31);\n}\n\n# prfb_i_p_ai.xml: PRFB (vector plus immediate) variant 64-bit element\n# PATTERN xc400e000/mask=xffe0e010\n\n:prfb sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to31]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to31 & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to31);\n}\n\n# prfb_i_p_bi.xml: PRFB (scalar plus immediate) variant SVE\n# PATTERN x85c00000/mask=xffc0e010\n\n:prfb sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31]\nis sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31);\n}\n\n# prfb_i_p_br.xml: PRFB (scalar plus scalar) variant SVE\n# PATTERN x8400c000/mask=xffe0e010\n\n:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# prfb_i_p_bz.xml: PRFB (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84200000/mask=xffa0e010\n\n:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# prfb_i_p_bz.xml: PRFB (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4200000/mask=xffa0e010\n\n:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# prfb_i_p_bz.xml: PRFB (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc4608000/mask=xffe0e010\n\n:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D]\nis sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3\n{\n\tSVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# prfd_i_p_ai.xml: PRFD (vector plus immediate) variant 32-bit element\n# PATTERN x8580e000/mask=xffe0e010\n\n:prfd sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to248]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to248 & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to248);\n}\n\n# prfd_i_p_ai.xml: PRFD (vector plus immediate) variant 64-bit element\n# PATTERN xc580e000/mask=xffe0e010\n\n:prfd sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to248]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to248 & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to248);\n}\n\n# prfd_i_p_bi.xml: PRFD (scalar plus immediate) variant SVE\n# PATTERN x85c06000/mask=xffc0e010\n\n:prfd sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31]\nis sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31);\n}\n\n# prfd_i_p_br.xml: PRFD (scalar plus scalar) variant SVE\n# PATTERN x8580c000/mask=xffe0e010\n\n:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# prfd_i_p_bz.xml: PRFD (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84206000/mask=xffa0e010\n\n:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^\" #3\"]\nis sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# prfd_i_p_bz.xml: PRFD (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4206000/mask=xffa0e010\n\n:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^\" #3\"]\nis sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# prfd_i_p_bz.xml: PRFD (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc460e000/mask=xffe0e010\n\n:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, \"lsl #3\"]\nis sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3\n{\n\tSVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# prfh_i_p_ai.xml: PRFH (vector plus immediate) variant 32-bit element\n# PATTERN x8480e000/mask=xffe0e010\n\n:prfh sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to62]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to62 & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to62);\n}\n\n# prfh_i_p_ai.xml: PRFH (vector plus immediate) variant 64-bit element\n# PATTERN xc480e000/mask=xffe0e010\n\n:prfh sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to62]\nis sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to62 & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to62);\n}\n\n# prfh_i_p_bi.xml: PRFH (scalar plus immediate) variant SVE\n# PATTERN x85c02000/mask=xffc0e010\n\n:prfh sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31]\nis sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31);\n}\n\n# prfh_i_p_br.xml: PRFH (scalar plus scalar) variant SVE\n# PATTERN x8480c000/mask=xffe0e010\n\n:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# prfh_i_p_bz.xml: PRFH (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84202000/mask=xffa0e010\n\n:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^\" #1\"]\nis sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# prfh_i_p_bz.xml: PRFH (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4202000/mask=xffa0e010\n\n:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^\" #1\"]\nis sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# prfh_i_p_bz.xml: PRFH (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc460a000/mask=xffe0e010\n\n:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, \"lsl #1\"]\nis sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3\n{\n\tSVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# prfw_i_p_ai.xml: PRFW (vector plus immediate) variant 32-bit element\n# PATTERN x8500e000/mask=xffe0e010\n\n:prfw sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to124]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to124 & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to124);\n}\n\n# prfw_i_p_ai.xml: PRFW (vector plus immediate) variant 64-bit element\n# PATTERN xc500e000/mask=xffe0e010\n\n:prfw sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to124]\nis sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to124 & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to124);\n}\n\n# prfw_i_p_bi.xml: PRFW (scalar plus immediate) variant SVE\n# PATTERN x85c04000/mask=xffc0e010\n\n:prfw sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31]\nis sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31);\n}\n\n# prfw_i_p_br.xml: PRFW (scalar plus scalar) variant SVE\n# PATTERN x8500c000/mask=xffe0e010\n\n:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# prfw_i_p_bz.xml: PRFW (scalar plus vector) variant 32-bit scaled offset\n# PATTERN x84204000/mask=xffa0e010\n\n:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^\" #2\"]\nis sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# prfw_i_p_bz.xml: PRFW (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xc4204000/mask=xffa0e010\n\n:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^\" #2\"]\nis sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# prfw_i_p_bz.xml: PRFW (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xc460c000/mask=xffe0e010\n\n:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, \"lsl #2\"]\nis sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3\n{\n\tSVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# ptest_p_p.xml: PTEST variant SVE\n# PATTERN x2550c000/mask=xffffc21f\n\n:ptest Pg, Pn.B\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b01 & sve_b_1419=0b000011 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_01=0 & sve_b_00=0 & Pn.B & Pg\n{\n\tSVE_ptest(Pg, Pn.B);\n}\n\n# ptrue_p_s.xml: PTRUE, PTRUES variant Flag setting\n# PATTERN x2519e000/mask=xff3ffc10\n\n:ptrues Pd.T^sve_opt_pattern\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1721=0b01100 & sve_b_16=1 & sve_b_1015=0b111000 & sve_pattern_0509 & sve_b_04=0 & sve_pd_0003 & sve_pattern & Pd.T & sve_opt_pattern\n{\n\tPd.T = SVE_ptrues(Pd.T, sve_opt_pattern);\n}\n\n# ptrue_p_s.xml: PTRUE, PTRUES variant Not flag setting\n# PATTERN x2518e000/mask=xff3ffc10\n\n:ptrue Pd.T^sve_opt_pattern\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1721=0b01100 & sve_b_16=0 & sve_b_1015=0b111000 & sve_pattern_0509 & sve_b_04=0 & sve_pd_0003 & sve_pattern & Pd.T & sve_opt_pattern\n{\n\tPd.T = SVE_ptrue(Pd.T, sve_opt_pattern);\n}\n\n# punpkhi_p_p.xml: PUNPKHI, PUNPKLO variant High half\n# PATTERN x05314000/mask=xfffffe10\n\n:punpkhi Pd.H, Pn.B\nis sve_b_1731=0b000001010011000 & sve_b_16=1 & sve_b_1015=0b010000 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.H & Pn.B\n{\n\tPd.H = SVE_punpkhi(Pd.H, Pn.B);\n}\n\n# punpkhi_p_p.xml: PUNPKHI, PUNPKLO variant Low half\n# PATTERN x05304000/mask=xfffffe10\n\n:punpklo Pd.H, Pn.B\nis sve_b_1731=0b000001010011000 & sve_b_16=0 & sve_b_1015=0b010000 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.H & Pn.B\n{\n\tPd.H = SVE_punpklo(Pd.H, Pn.B);\n}\n\n# rbit_z_p_z.xml: RBIT variant SVE\n# PATTERN x05278000/mask=xff3fe000\n\n:rbit Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_rbit(Zd.T, Pg3_m, Zn.T);\n}\n\n# rdffr_p_f.xml: RDFFR (unpredicated) variant SVE\n# PATTERN x2519f000/mask=xfffffff0\n\n:rdffr Pd.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1021=0b011001111100 & sve_b_0409=0b000000 & sve_pd_0003 & Pd.B\n{\n\tPd.B = SVE_rdffr(Pd.B);\n}\n\n# rdffr_p_p_f.xml: RDFFR, RDFFRS (predicated) variant Flag setting\n# PATTERN x2558f000/mask=xfffffe10\n\n:rdffrs Pd.B, Pn_z\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1021=0b011000111100 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pn_z\n{\n\tPd.B = SVE_rdffrs(Pd.B, Pn_z);\n}\n\n# rdffr_p_p_f.xml: RDFFR, RDFFRS (predicated) variant Not flag setting\n# PATTERN x2518f000/mask=xfffffe10\n\n:rdffr Pd.B, Pn_z\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1021=0b011000111100 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pn_z\n{\n\tPd.B = SVE_rdffr(Pd.B, Pn_z);\n}\n\n# rdvl_r_i.xml: RDVL variant SVE\n# PATTERN x04bf5000/mask=xfffff800\n\n:rdvl Rd_GPR64, \"#\"^sve_imm6_1_m32to31\nis sve_b_2331=0b000001001 & sve_b_22=0 & sve_b_21=1 & sve_b_1720=0b1111 & sve_b_16=1 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & sve_imm6_1_m32to31 & Rd_GPR64\n{\n\tRd_GPR64 = SVE_rdvl(Rd_GPR64, sve_imm6_1_m32to31:1);\n}\n\n# rev_p_p.xml: REV (predicate) variant SVE\n# PATTERN x05344000/mask=xff3ffe10\n\n:rev Pd.T, Pn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1021=0b110100010000 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T\n{\n\tPd.T = SVE_rev(Pd.T, Pn.T);\n}\n\n# rev_z_z.xml: REV (vector) variant SVE\n# PATTERN x05383800/mask=xff3ffc00\n\n:rev Zd.T, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1021=0b111000001110 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T\n{\n\tZd.T = SVE_rev(Zd.T, Zn.T);\n}\n\n# revb_z_z.xml: REVB, REVH, REVW variant Byte\n# PATTERN x05248000/mask=xff3fe000\n\n:revb Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_revb(Zd.T, Pg3_m, Zn.T);\n}\n\n# revb_z_z.xml: REVB, REVH, REVW variant Halfword\n# PATTERN x05258000/mask=xff3fe000\n\n:revh Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_revh(Zd.T, Pg3_m, Zn.T);\n}\n\n# revb_z_z.xml: REVB, REVH, REVW variant Word\n# PATTERN x05268000/mask=xff3fe000\n\n:revw Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_revw(Zd.D, Pg3_m, Zn.D);\n}\n\n# sabd_z_p_zz.xml: SABD variant SVE\n# PATTERN x040c0000/mask=xff3fe000\n\n:sabd Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_sabd(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# saddv_r_p_z.xml: SADDV variant SVE\n# PATTERN x04002000/mask=xff3fe000\n\n:saddv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_saddv(Rd_FPR64, Zn.T, Pg3);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 16-bit to half-precision\n# PATTERN x6552a000/mask=xffffe000\n\n:scvtf Zd.H, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m\n{\n\tZd.H = SVE_scvtf(Zd.H, Pg3_m, Zn.H);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 32-bit to half-precision\n# PATTERN x6554a000/mask=xffffe000\n\n:scvtf Zd.H, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m\n{\n\tZd.H = SVE_scvtf(Zd.H, Pg3_m, Zn.S);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 32-bit to single-precision\n# PATTERN x6594a000/mask=xffffe000\n\n:scvtf Zd.S, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m\n{\n\tZd.S = SVE_scvtf(Zd.S, Pg3_m, Zn.S);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 32-bit to double-precision\n# PATTERN x65d0a000/mask=xffffe000\n\n:scvtf Zd.D, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m\n{\n\tZd.D = SVE_scvtf(Zd.D, Pg3_m, Zn.S);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 64-bit to half-precision\n# PATTERN x6556a000/mask=xffffe000\n\n:scvtf Zd.H, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m\n{\n\tZd.H = SVE_scvtf(Zd.H, Pg3_m, Zn.D);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 64-bit to single-precision\n# PATTERN x65d4a000/mask=xffffe000\n\n:scvtf Zd.S, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m\n{\n\tZd.S = SVE_scvtf(Zd.S, Pg3_m, Zn.D);\n}\n\n# scvtf_z_p_z.xml: SCVTF variant 64-bit to double-precision\n# PATTERN x65d6a000/mask=xffffe000\n\n:scvtf Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_scvtf(Zd.D, Pg3_m, Zn.D);\n}\n\n# sdiv_z_p_zz.xml: SDIV variant SVE\n# PATTERN x04940000/mask=xffbfe000\n\n:sdiv Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m\n{\n\tZd.T_sz = SVE_sdiv(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz);\n}\n\n# sdivr_z_p_zz.xml: SDIVR variant SVE\n# PATTERN x04960000/mask=xffbfe000\n\n:sdivr Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m\n{\n\tZd.T_sz = SVE_sdivr(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz);\n}\n\n# sdot_z_zzz.xml: SDOT (vectors) variant SVE\n# PATTERN x44800000/mask=xffa0fc00\n\n:sdot Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz\nis sve_b_2431=0b01000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=0 & sve_zm_1620 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zm.Tb_sz & Zd.T_sz & Zn.Tb_sz\n{\n\tZd.T_sz = SVE_sdot(Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz);\n}\n\n# sdot_z_zzzi.xml: SDOT (indexed) variant 32-bit\n# PATTERN x44a00000/mask=xffe0fc00\n\n:sdot Zd.S, Zn.B, Zm3.B[sve_i2_1920]\nis sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.B & Zm3.B\n{\n\tZd.S = SVE_sdot(Zd.S, Zn.B, Zm3.B, sve_i2_1920:1);\n}\n\n# sdot_z_zzzi.xml: SDOT (indexed) variant 64-bit\n# PATTERN x44e00000/mask=xffe0fc00\n\n:sdot Zd.D, Zn.H, Zm4.H[sve_i1_20]\nis sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.H & Zm4.H\n{\n\tZd.D = SVE_sdot(Zd.D, Zn.H, Zm4.H, sve_i1_20:1);\n}\n\n# sel_p_p_pp.xml: SEL (predicates) variant SVE\n# PATTERN x25004210/mask=xfff0c210\n\n:sel Pd.B, Pg, Pn.B, Pm.B\nis sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pn.B & Pm.B & Pg\n{\n\tPd.B = SVE_sel(Pd.B, Pg, Pn.B, Pm.B);\n}\n\n# sel_z_p_zz.xml: SEL (vectors) variant SVE\n# PATTERN x0520c000/mask=xff20c000\n\n:sel Zd.T, Pg, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1415=0b11 & sve_pg_1013 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T & Pg\n{\n\tZd.T = SVE_sel(Zd.T, Pg, Zn.T, Zm.T);\n}\n\n# setffr_f.xml: SETFFR variant SVE\n# PATTERN x252c9000/mask=xffffffff\n\n:setffr \"\"\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_b_1019=0b1100100100 & sve_b_0409=0b000000 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00\nunimpl\n\n# smax_z_p_zz.xml: SMAX (vectors) variant SVE\n# PATTERN x04080000/mask=xff3fe000\n\n:smax Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_smax(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# smax_z_zi.xml: SMAX (immediate) variant SVE\n# PATTERN x2528c000/mask=xff3fe000\n\n:smax Zd.T, Zd.T_2, \"#\"^sve_imm8_1_m128to127\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_m128to127\n{\n\tZd.T = SVE_smax(Zd.T, Zd.T_2, sve_imm8_1_m128to127:1);\n}\n\n# smaxv_r_p_z.xml: SMAXV variant SVE\n# PATTERN x04082000/mask=xff3fe000\n\n:smaxv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_smaxv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# smaxv_r_p_z.xml: SMAXV variant SVE\n# PATTERN x04082000/mask=xff3fe000\n\n:smaxv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_smaxv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# smaxv_r_p_z.xml: SMAXV variant SVE\n# PATTERN x04082000/mask=xff3fe000\n\n:smaxv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_smaxv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# smaxv_r_p_z.xml: SMAXV variant SVE\n# PATTERN x04082000/mask=xff3fe000\n\n:smaxv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_smaxv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# smin_z_p_zz.xml: SMIN (vectors) variant SVE\n# PATTERN x040a0000/mask=xff3fe000\n\n:smin Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_smin(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# smin_z_zi.xml: SMIN (immediate) variant SVE\n# PATTERN x252ac000/mask=xff3fe000\n\n:smin Zd.T, Zd.T_2, \"#\"^sve_imm8_1_m128to127\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_m128to127\n{\n\tZd.T = SVE_smin(Zd.T, Zd.T_2, sve_imm8_1_m128to127:1);\n}\n\n# sminv_r_p_z.xml: SMINV variant SVE\n# PATTERN x040a2000/mask=xff3fe000\n\n:sminv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_sminv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# sminv_r_p_z.xml: SMINV variant SVE\n# PATTERN x040a2000/mask=xff3fe000\n\n:sminv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_sminv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# sminv_r_p_z.xml: SMINV variant SVE\n# PATTERN x040a2000/mask=xff3fe000\n\n:sminv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_sminv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# sminv_r_p_z.xml: SMINV variant SVE\n# PATTERN x040a2000/mask=xff3fe000\n\n:sminv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_sminv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# smulh_z_p_zz.xml: SMULH variant SVE\n# PATTERN x04120000/mask=xff3fe000\n\n:smulh Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_smulh(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# splice_z_p_zz.xml: SPLICE variant SVE\n# PATTERN x052c8000/mask=xff3fe000\n\n:splice Zd.T, Pg3, Zd.T_2, Zn.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1321=0b101100100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3\n{\n\tZd.T = SVE_splice(Zd.T, Pg3, Zd.T_2, Zn.T);\n}\n\n# sqadd_z_zi.xml: SQADD (immediate) variant SVE\n# PATTERN x2524c000/mask=xff3fc000\n\n:sqadd Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_sqadd(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# sqadd_z_zz.xml: SQADD (vectors) variant SVE\n# PATTERN x04201000/mask=xff20fc00\n\n:sqadd Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b10 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_sqadd(Zd.T, Zn.T, Zm.T);\n}\n\n# sqdecb_r_rs.xml: SQDECB variant 32-bit\n# PATTERN x0420f800/mask=xfff0fc00\n\n:sqdecb Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdecb(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecb_r_rs.xml: SQDECB variant 64-bit\n# PATTERN x0430f800/mask=xfff0fc00\n\n:sqdecb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdecb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecd_r_rs.xml: SQDECD (scalar) variant 32-bit\n# PATTERN x04e0f800/mask=xfff0fc00\n\n:sqdecd Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdecd(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecd_r_rs.xml: SQDECD (scalar) variant 64-bit\n# PATTERN x04f0f800/mask=xfff0fc00\n\n:sqdecd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdecd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecd_z_zs.xml: SQDECD (vector) variant SVE\n# PATTERN x04e0c800/mask=xfff0fc00\n\n:sqdecd Zd.D^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.D = SVE_sqdecd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdech_r_rs.xml: SQDECH (scalar) variant 32-bit\n# PATTERN x0460f800/mask=xfff0fc00\n\n:sqdech Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdech(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdech_r_rs.xml: SQDECH (scalar) variant 64-bit\n# PATTERN x0470f800/mask=xfff0fc00\n\n:sqdech Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdech_z_zs.xml: SQDECH (vector) variant SVE\n# PATTERN x0460c800/mask=xfff0fc00\n\n:sqdech Zd.H^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.H = SVE_sqdech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecp_r_p_r.xml: SQDECP (scalar) variant 32-bit\n# PATTERN x252a8800/mask=xff3ffe00\n\n:sqdecp Rd_GPR64, Pn.T, Rd_GPR32\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32 & Rd_GPR64\n{\n\tRd_GPR64 = SVE_sqdecp(Rd_GPR64, Pn.T, Rd_GPR32);\n}\n\n# sqdecp_r_p_r.xml: SQDECP (scalar) variant 64-bit\n# PATTERN x252a8c00/mask=xff3ffe00\n\n:sqdecp Rd_GPR64, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64\n{\n\tRd_GPR64 = SVE_sqdecp(Rd_GPR64, Pn.T);\n}\n\n# sqdecp_z_p_z.xml: SQDECP (vector) variant SVE\n# PATTERN x252a8000/mask=xff3ffe00\n\n:sqdecp Zd.T, Pn\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=0 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn\n{\n\tZd.T = SVE_sqdecp(Zd.T, Pn);\n}\n\n# sqdecw_r_rs.xml: SQDECW (scalar) variant 32-bit\n# PATTERN x04a0f800/mask=xfff0fc00\n\n:sqdecw Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdecw(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecw_r_rs.xml: SQDECW (scalar) variant 64-bit\n# PATTERN x04b0f800/mask=xfff0fc00\n\n:sqdecw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqdecw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqdecw_z_zs.xml: SQDECW (vector) variant SVE\n# PATTERN x04a0c800/mask=xfff0fc00\n\n:sqdecw Zd.S^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.S = SVE_sqdecw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincb_r_rs.xml: SQINCB variant 32-bit\n# PATTERN x0420f000/mask=xfff0fc00\n\n:sqincb Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqincb(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincb_r_rs.xml: SQINCB variant 64-bit\n# PATTERN x0430f000/mask=xfff0fc00\n\n:sqincb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqincb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincd_r_rs.xml: SQINCD (scalar) variant 32-bit\n# PATTERN x04e0f000/mask=xfff0fc00\n\n:sqincd Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqincd(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincd_r_rs.xml: SQINCD (scalar) variant 64-bit\n# PATTERN x04f0f000/mask=xfff0fc00\n\n:sqincd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqincd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincd_z_zs.xml: SQINCD (vector) variant SVE\n# PATTERN x04e0c000/mask=xfff0fc00\n\n:sqincd Zd.D^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.D = SVE_sqincd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqinch_r_rs.xml: SQINCH (scalar) variant 32-bit\n# PATTERN x0460f000/mask=xfff0fc00\n\n:sqinch Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqinch(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqinch_r_rs.xml: SQINCH (scalar) variant 64-bit\n# PATTERN x0470f000/mask=xfff0fc00\n\n:sqinch Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqinch(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqinch_z_zs.xml: SQINCH (vector) variant SVE\n# PATTERN x0460c000/mask=xfff0fc00\n\n:sqinch Zd.H^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.H = SVE_sqinch(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincp_r_p_r.xml: SQINCP (scalar) variant 32-bit\n# PATTERN x25288800/mask=xff3ffe00\n\n:sqincp Rd_GPR64, Pn.T, Rd_GPR32\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32 & Rd_GPR64\n{\n\tRd_GPR64 = SVE_sqincp(Rd_GPR64, Pn.T, Rd_GPR32);\n}\n\n# sqincp_r_p_r.xml: SQINCP (scalar) variant 64-bit\n# PATTERN x25288c00/mask=xff3ffe00\n\n:sqincp Rd_GPR64, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64\n{\n\tRd_GPR64 = SVE_sqincp(Rd_GPR64, Pn.T);\n}\n\n# sqincp_z_p_z.xml: SQINCP (vector) variant SVE\n# PATTERN x25288000/mask=xff3ffe00\n\n:sqincp Zd.T, Pn\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn\n{\n\tZd.T = SVE_sqincp(Zd.T, Pn);\n}\n\n# sqincw_r_rs.xml: SQINCW (scalar) variant 32-bit\n# PATTERN x04a0f000/mask=xfff0fc00\n\n:sqincw Rd_GPR64, Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqincw(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincw_r_rs.xml: SQINCW (scalar) variant 64-bit\n# PATTERN x04b0f000/mask=xfff0fc00\n\n:sqincw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_sqincw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqincw_z_zs.xml: SQINCW (vector) variant SVE\n# PATTERN x04a0c000/mask=xfff0fc00\n\n:sqincw Zd.S^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.S = SVE_sqincw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# sqsub_z_zi.xml: SQSUB (immediate) variant SVE\n# PATTERN x2526c000/mask=xff3fc000\n\n:sqsub Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_sqsub(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# sqsub_z_zz.xml: SQSUB (vectors) variant SVE\n# PATTERN x04201800/mask=xff20fc00\n\n:sqsub Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_sqsub(Zd.T, Zn.T, Zm.T);\n}\n\n# st1b_z_p_ai.xml: ST1B (vector plus immediate) variant 32-bit element\n# PATTERN xe460a000/mask=xffe0e000\n\n:st1b \"{\"^Zd.S^\"}\", Pg3, [Zn.S^sve_opt5_1_0to31]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Zd.S & sve_opt5_1_0to31 & Pg3\n{\n\tSVE_st1b(Zd.S, Pg3, Zn.S, sve_opt5_1_0to31);\n}\n\n# st1b_z_p_ai.xml: ST1B (vector plus immediate) variant 64-bit element\n# PATTERN xe440a000/mask=xffe0e000\n\n:st1b \"{\"^Zd.D^\"}\", Pg3, [Zn.D^sve_opt5_1_0to31]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to31 & Pg3\n{\n\tSVE_st1b(Zd.D, Pg3, Zn.D, sve_opt5_1_0to31);\n}\n\n# st1b_z_p_bi.xml: ST1B (scalar plus immediate) variant SVE\n# PATTERN xe400e000/mask=xff90e000\n\n:st1b \"{\"^Zd.T_size_2122^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_st1b(Zd.T_size_2122, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# st1b_z_p_br.xml: ST1B (scalar plus scalar) variant SVE\n# PATTERN xe4004000/mask=xff80e000\n\n:st1b \"{\"^Zd.T_size_2122^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st1b(Zd.T_size_2122, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st1b_z_p_bz.xml: ST1B (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xe4008000/mask=xffe0a000\n\n:st1b \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1b(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1b_z_p_bz.xml: ST1B (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN xe4408000/mask=xffe0a000\n\n:st1b \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3\n{\n\tSVE_st1b(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# st1b_z_p_bz.xml: ST1B (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xe400a000/mask=xffe0e000\n\n:st1b \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1b(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st1d_z_p_ai.xml: ST1D (vector plus immediate) variant SVE\n# PATTERN xe5c0a000/mask=xffe0e000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Zn.D^sve_opt5_1_0to248]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to248 & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Zn.D, sve_opt5_1_0to248);\n}\n\n# st1d_z_p_bi.xml: ST1D (scalar plus immediate) variant SVE\n# PATTERN xe580e000/mask=xff90e000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# st1d_z_p_br.xml: ST1D (scalar plus scalar) variant SVE\n# PATTERN xe5804000/mask=xff80e000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & Rm_GPR64 & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xe5a08000/mask=xffe0a000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^\" #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xe5808000/mask=xffe0a000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xe5a0a000/mask=xffe0e000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, \"lsl #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xe580a000/mask=xffe0e000\n\n:st1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st1h_z_p_ai.xml: ST1H (vector plus immediate) variant 32-bit element\n# PATTERN xe4e0a000/mask=xffe0e000\n\n:st1h \"{\"^Zd.S^\"}\", Pg3, [Zn.S^sve_opt5_1_0to62]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Zd.S & sve_opt5_1_0to62 & Pg3\n{\n\tSVE_st1h(Zd.S, Pg3, Zn.S, sve_opt5_1_0to62);\n}\n\n# st1h_z_p_ai.xml: ST1H (vector plus immediate) variant 64-bit element\n# PATTERN xe4c0a000/mask=xffe0e000\n\n:st1h \"{\"^Zd.D^\"}\", Pg3, [Zn.D^sve_opt5_1_0to62]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to62 & Pg3\n{\n\tSVE_st1h(Zd.D, Pg3, Zn.D, sve_opt5_1_0to62);\n}\n\n# st1h_z_p_bi.xml: ST1H (scalar plus immediate) variant SVE\n# PATTERN xe480e000/mask=xff90e000\n\n:st1h \"{\"^Zd.T_size_2122^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_st1h(Zd.T_size_2122, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# st1h_z_p_br.xml: ST1H (scalar plus scalar) variant SVE\n# PATTERN xe4804000/mask=xff80e000\n\n:st1h \"{\"^Zd.T_size_2122^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st1h(Zd.T_size_2122, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit scaled offset\n# PATTERN xe4e08000/mask=xffe0a000\n\n:st1h \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^\" #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3\n{\n\tSVE_st1h(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xe4a08000/mask=xffe0a000\n\n:st1h \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^\" #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xe4808000/mask=xffe0a000\n\n:st1h \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN xe4c08000/mask=xffe0a000\n\n:st1h \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3\n{\n\tSVE_st1h(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xe4a0a000/mask=xffe0e000\n\n:st1h \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, \"lsl #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xe480a000/mask=xffe0e000\n\n:st1h \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st1w_z_p_ai.xml: ST1W (vector plus immediate) variant 32-bit element\n# PATTERN xe560a000/mask=xffe0e000\n\n:st1w \"{\"^Zd.S^\"}\", Pg3, [Zn.S^sve_opt5_1_0to124]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Zd.S & sve_opt5_1_0to124 & Pg3\n{\n\tSVE_st1w(Zd.S, Pg3, Zn.S, sve_opt5_1_0to124);\n}\n\n# st1w_z_p_ai.xml: ST1W (vector plus immediate) variant 64-bit element\n# PATTERN xe540a000/mask=xffe0e000\n\n:st1w \"{\"^Zd.D^\"}\", Pg3, [Zn.D^sve_opt5_1_0to124]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to124 & Pg3\n{\n\tSVE_st1w(Zd.D, Pg3, Zn.D, sve_opt5_1_0to124);\n}\n\n# st1w_z_p_bi.xml: ST1W (scalar plus immediate) variant SVE\n# PATTERN xe500e000/mask=xff90e000\n\n:st1w \"{\"^Zd.T_size_2122^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_st1w(Zd.T_size_2122, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# st1w_z_p_br.xml: ST1W (scalar plus scalar) variant SVE\n# PATTERN xe5004000/mask=xff80e000\n\n:st1w \"{\"^Zd.T_size_2122^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st1w(Zd.T_size_2122, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit scaled offset\n# PATTERN xe5608000/mask=xffe0a000\n\n:st1w \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^\" #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3\n{\n\tSVE_st1w(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit unpacked scaled offset\n# PATTERN xe5208000/mask=xffe0a000\n\n:st1w \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^\" #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit unpacked unscaled offset\n# PATTERN xe5008000/mask=xffe0a000\n\n:st1w \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3\n{\n\tSVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1);\n}\n\n# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit unscaled offset\n# PATTERN xe5408000/mask=xffe0a000\n\n:st1w \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3\n{\n\tSVE_st1w(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1);\n}\n\n# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 64-bit scaled offset\n# PATTERN xe520a000/mask=xffe0e000\n\n:st1w \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D, \"lsl #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 64-bit unscaled offset\n# PATTERN xe500a000/mask=xffe0e000\n\n:st1w \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Zm.D]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3\n{\n\tSVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D);\n}\n\n# st2b_z_p_bi.xml: ST2B (scalar plus immediate) variant SVE\n# PATTERN xe430e000/mask=xfff0e000\n\n:st2b \"{\"^Zt.B, Ztt.B^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3\n{\n\tSVE_st2b(Zt.B, Ztt.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# st2b_z_p_br.xml: ST2B (scalar plus scalar) variant SVE\n# PATTERN xe4206000/mask=xffe0e000\n\n:st2b \"{\"^Zt.B, Ztt.B^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st2b(Zt.B, Ztt.B, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st2d_z_p_bi.xml: ST2D (scalar plus immediate) variant SVE\n# PATTERN xe5b0e000/mask=xfff0e000\n\n:st2d \"{\"^Zt.D, Ztt.D^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3\n{\n\tSVE_st2d(Zt.D, Ztt.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# st2d_z_p_br.xml: ST2D (scalar plus scalar) variant SVE\n# PATTERN xe5a06000/mask=xffe0e000\n\n:st2d \"{\"^Zt.D, Ztt.D^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st2d(Zt.D, Ztt.D, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st2h_z_p_bi.xml: ST2H (scalar plus immediate) variant SVE\n# PATTERN xe4b0e000/mask=xfff0e000\n\n:st2h \"{\"^Zt.H, Ztt.H^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3\n{\n\tSVE_st2h(Zt.H, Ztt.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# st2h_z_p_br.xml: ST2H (scalar plus scalar) variant SVE\n# PATTERN xe4a06000/mask=xffe0e000\n\n:st2h \"{\"^Zt.H, Ztt.H^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st2h(Zt.H, Ztt.H, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st2w_z_p_bi.xml: ST2W (scalar plus immediate) variant SVE\n# PATTERN xe530e000/mask=xfff0e000\n\n:st2w \"{\"^Zt.S, Ztt.S^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3\n{\n\tSVE_st2w(Zt.S, Ztt.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14);\n}\n\n# st2w_z_p_br.xml: ST2W (scalar plus scalar) variant SVE\n# PATTERN xe5206000/mask=xffe0e000\n\n:st2w \"{\"^Zt.S, Ztt.S^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st2w(Zt.S, Ztt.S, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st3b_z_p_bi.xml: ST3B (scalar plus immediate) variant SVE\n# PATTERN xe450e000/mask=xfff0e000\n\n:st3b \"{\"^Zt.B, Ztt.B, Zttt.B^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3\n{\n\tSVE_st3b(Zt.B, Ztt.B, Zttt.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# st3b_z_p_br.xml: ST3B (scalar plus scalar) variant SVE\n# PATTERN xe4406000/mask=xffe0e000\n\n:st3b \"{\"^Zt.B, Ztt.B, Zttt.B^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st3b(Zt.B, Ztt.B, Zttt.B, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st3d_z_p_bi.xml: ST3D (scalar plus immediate) variant SVE\n# PATTERN xe5d0e000/mask=xfff0e000\n\n:st3d \"{\"^Zt.D, Ztt.D, Zttt.D^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3\n{\n\tSVE_st3d(Zt.D, Ztt.D, Zttt.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# st3d_z_p_br.xml: ST3D (scalar plus scalar) variant SVE\n# PATTERN xe5c06000/mask=xffe0e000\n\n:st3d \"{\"^Zt.D, Ztt.D, Zttt.D^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st3d(Zt.D, Ztt.D, Zttt.D, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st3h_z_p_bi.xml: ST3H (scalar plus immediate) variant SVE\n# PATTERN xe4d0e000/mask=xfff0e000\n\n:st3h \"{\"^Zt.H, Ztt.H, Zttt.H^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3\n{\n\tSVE_st3h(Zt.H, Ztt.H, Zttt.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# st3h_z_p_br.xml: ST3H (scalar plus scalar) variant SVE\n# PATTERN xe4c06000/mask=xffe0e000\n\n:st3h \"{\"^Zt.H, Ztt.H, Zttt.H^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st3h(Zt.H, Ztt.H, Zttt.H, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st3w_z_p_bi.xml: ST3W (scalar plus immediate) variant SVE\n# PATTERN xe550e000/mask=xfff0e000\n\n:st3w \"{\"^Zt.S, Ztt.S, Zttt.S^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3\n{\n\tSVE_st3w(Zt.S, Ztt.S, Zttt.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21);\n}\n\n# st3w_z_p_br.xml: ST3W (scalar plus scalar) variant SVE\n# PATTERN xe5406000/mask=xffe0e000\n\n:st3w \"{\"^Zt.S, Ztt.S, Zttt.S^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st3w(Zt.S, Ztt.S, Zttt.S, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st4b_z_p_bi.xml: ST4B (scalar plus immediate) variant SVE\n# PATTERN xe470e000/mask=xfff0e000\n\n:st4b \"{\"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3\n{\n\tSVE_st4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# st4b_z_p_br.xml: ST4B (scalar plus scalar) variant SVE\n# PATTERN xe4606000/mask=xffe0e000\n\n:st4b \"{\"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st4d_z_p_bi.xml: ST4D (scalar plus immediate) variant SVE\n# PATTERN xe5f0e000/mask=xfff0e000\n\n:st4d \"{\"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3\n{\n\tSVE_st4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# st4d_z_p_br.xml: ST4D (scalar plus scalar) variant SVE\n# PATTERN xe5e06000/mask=xffe0e000\n\n:st4d \"{\"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st4h_z_p_bi.xml: ST4H (scalar plus immediate) variant SVE\n# PATTERN xe4f0e000/mask=xfff0e000\n\n:st4h \"{\"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3\n{\n\tSVE_st4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# st4h_z_p_br.xml: ST4H (scalar plus scalar) variant SVE\n# PATTERN xe4e06000/mask=xffe0e000\n\n:st4h \"{\"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# st4w_z_p_bi.xml: ST4W (scalar plus immediate) variant SVE\n# PATTERN xe570e000/mask=xfff0e000\n\n:st4w \"{\"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3\n{\n\tSVE_st4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28);\n}\n\n# st4w_z_p_br.xml: ST4W (scalar plus scalar) variant SVE\n# PATTERN xe5606000/mask=xffe0e000\n\n:st4w \"{\"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & Rm_GPR64 & Pg3\n{\n\tSVE_st4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# stnt1b_z_p_bi.xml: STNT1B (scalar plus immediate) variant SVE\n# PATTERN xe410e000/mask=xfff0e000\n\n:stnt1b \"{\"^Zd.B^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.B & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_stnt1b(Zd.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# stnt1b_z_p_br.xml: STNT1B (scalar plus scalar) variant SVE\n# PATTERN xe4006000/mask=xffe0e000\n\n:stnt1b \"{\"^Zd.B^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.B & Rm_GPR64 & Pg3\n{\n\tSVE_stnt1b(Zd.B, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# stnt1d_z_p_bi.xml: STNT1D (scalar plus immediate) variant SVE\n# PATTERN xe590e000/mask=xfff0e000\n\n:stnt1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_stnt1d(Zd.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# stnt1d_z_p_br.xml: STNT1D (scalar plus scalar) variant SVE\n# PATTERN xe5806000/mask=xffe0e000\n\n:stnt1d \"{\"^Zd.D^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #3\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & Rm_GPR64 & Pg3\n{\n\tSVE_stnt1d(Zd.D, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# stnt1h_z_p_bi.xml: STNT1H (scalar plus immediate) variant SVE\n# PATTERN xe490e000/mask=xfff0e000\n\n:stnt1h \"{\"^Zd.H^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.H & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_stnt1h(Zd.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# stnt1h_z_p_br.xml: STNT1H (scalar plus scalar) variant SVE\n# PATTERN xe4806000/mask=xffe0e000\n\n:stnt1h \"{\"^Zd.H^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #1\"]\nis sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.H & Rm_GPR64 & Pg3\n{\n\tSVE_stnt1h(Zd.H, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# stnt1w_z_p_bi.xml: STNT1W (scalar plus immediate) variant SVE\n# PATTERN xe510e000/mask=xfff0e000\n\n:stnt1w \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.S & sve_mul4_1_m8to7 & Pg3\n{\n\tSVE_stnt1w(Zd.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7);\n}\n\n# stnt1w_z_p_br.xml: STNT1W (scalar plus scalar) variant SVE\n# PATTERN xe5006000/mask=xffe0e000\n\n:stnt1w \"{\"^Zd.S^\"}\", Pg3, [Rn_GPR64xsp, Rm_GPR64, \"lsl #2\"]\nis sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.S & Rm_GPR64 & Pg3\n{\n\tSVE_stnt1w(Zd.S, Pg3, Rn_GPR64xsp, Rm_GPR64);\n}\n\n# str_p_bi.xml: STR (predicate) variant SVE\n# PATTERN xe5800000/mask=xffc0e010\n\n:str Pd, [Rn_GPR64xsp^sve_mul9_2_m256to255]\nis sve_b_2231=0b1110010110 & sve_imm9h_1621 & sve_b_1315=0b000 & sve_imm9l_1012 & sve_rn_0509 & sve_b_04=0 & sve_pt_0003 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Pd\n{\n\tSVE_str(Pd, Rn_GPR64xsp, sve_mul9_2_m256to255);\n}\n\n# str_z_bi.xml: STR (vector) variant SVE\n# PATTERN xe5804000/mask=xffc0e000\n\n:str Zd, [Rn_GPR64xsp^sve_mul9_2_m256to255]\nis sve_b_2231=0b1110010110 & sve_imm9h_1621 & sve_b_1315=0b010 & sve_imm9l_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Zd\n{\n\tSVE_str(Zd, Rn_GPR64xsp, sve_mul9_2_m256to255);\n}\n\n# sub_z_p_zz.xml: SUB (vectors, predicated) variant SVE\n# PATTERN x04010000/mask=xff3fe000\n\n:sub Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_sub(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# sub_z_zi.xml: SUB (immediate) variant SVE\n# PATTERN x2521c000/mask=xff3fc000\n\n:sub Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_sub(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# sub_z_zz.xml: SUB (vectors, unpredicated) variant SVE\n# PATTERN x04200400/mask=xff20fc00\n\n:sub Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_sub(Zd.T, Zn.T, Zm.T);\n}\n\n# subr_z_p_zz.xml: SUBR (vectors) variant SVE\n# PATTERN x04030000/mask=xff3fe000\n\n:subr Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_subr(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# subr_z_zi.xml: SUBR (immediate) variant SVE\n# PATTERN x2523c000/mask=xff3fc000\n\n:subr Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_subr(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# sunpkhi_z_z.xml: SUNPKHI, SUNPKLO variant High half\n# PATTERN x05313800/mask=xff3ffc00\n\n:sunpkhi Zd.T, Zn.Tb\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=0 & sve_b_16=1 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T\n{\n\tZd.T = SVE_sunpkhi(Zd.T, Zn.Tb);\n}\n\n# sunpkhi_z_z.xml: SUNPKHI, SUNPKLO variant Low half\n# PATTERN x05303800/mask=xff3ffc00\n\n:sunpklo Zd.T, Zn.Tb\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=0 & sve_b_16=0 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T\n{\n\tZd.T = SVE_sunpklo(Zd.T, Zn.Tb);\n}\n\n# sxtb_z_p_z.xml: SXTB, SXTH, SXTW variant Byte\n# PATTERN x0410a000/mask=xff3fe000\n\n:sxtb Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_sxtb(Zd.T, Pg3_m, Zn.T);\n}\n\n# sxtb_z_p_z.xml: SXTB, SXTH, SXTW variant Halfword\n# PATTERN x0412a000/mask=xff3fe000\n\n:sxth Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_sxth(Zd.T, Pg3_m, Zn.T);\n}\n\n# sxtb_z_p_z.xml: SXTB, SXTH, SXTW variant Word\n# PATTERN x0414a000/mask=xff3fe000\n\n:sxtw Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_sxtw(Zd.D, Pg3_m, Zn.D);\n}\n\n# tbl_z_zz.xml: TBL variant SVE\n# PATTERN x05203000/mask=xff20fc00\n\n:tbl Zd.T, \"{\"^Zn.T^\"}\", Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_tbl(Zd.T, Zn.T, Zm.T);\n}\n\n# trn1_p_pp.xml: TRN1, TRN2 (predicates) variant Even\n# PATTERN x05205000/mask=xff30fe10\n\n:trn1 Pd.T, Pn.T, Pm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=1 & sve_b_11=0 & sve_b_10=0 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T\n{\n\tPd.T = SVE_trn1(Pd.T, Pn.T, Pm.T);\n}\n\n# trn1_p_pp.xml: TRN1, TRN2 (predicates) variant Odd\n# PATTERN x05205400/mask=xff30fe10\n\n:trn2 Pd.T, Pn.T, Pm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=1 & sve_b_11=0 & sve_b_10=1 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T\n{\n\tPd.T = SVE_trn2(Pd.T, Pn.T, Pm.T);\n}\n\n# trn1_z_zz.xml: TRN1, TRN2 (vectors) variant Even\n# PATTERN x05207000/mask=xff20fc00\n\n:trn1 Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b10 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_trn1(Zd.T, Zn.T, Zm.T);\n}\n\n# trn1_z_zz.xml: TRN1, TRN2 (vectors) variant Odd\n# PATTERN x05207400/mask=xff20fc00\n\n:trn2 Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b10 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_trn2(Zd.T, Zn.T, Zm.T);\n}\n\n# uabd_z_p_zz.xml: UABD variant SVE\n# PATTERN x040d0000/mask=xff3fe000\n\n:uabd Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_uabd(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# uaddv_r_p_z.xml: UADDV variant SVE\n# PATTERN x04012000/mask=xff3fe000\n\n:uaddv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_uaddv(Rd_FPR64, Zn.T, Pg3);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 16-bit to half-precision\n# PATTERN x6553a000/mask=xffffe000\n\n:ucvtf Zd.H, Pg3_m, Zn.H\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m\n{\n\tZd.H = SVE_ucvtf(Zd.H, Pg3_m, Zn.H);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 32-bit to half-precision\n# PATTERN x6555a000/mask=xffffe000\n\n:ucvtf Zd.H, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m\n{\n\tZd.H = SVE_ucvtf(Zd.H, Pg3_m, Zn.S);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 32-bit to single-precision\n# PATTERN x6595a000/mask=xffffe000\n\n:ucvtf Zd.S, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m\n{\n\tZd.S = SVE_ucvtf(Zd.S, Pg3_m, Zn.S);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 32-bit to double-precision\n# PATTERN x65d1a000/mask=xffffe000\n\n:ucvtf Zd.D, Pg3_m, Zn.S\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m\n{\n\tZd.D = SVE_ucvtf(Zd.D, Pg3_m, Zn.S);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 64-bit to half-precision\n# PATTERN x6557a000/mask=xffffe000\n\n:ucvtf Zd.H, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m\n{\n\tZd.H = SVE_ucvtf(Zd.H, Pg3_m, Zn.D);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 64-bit to single-precision\n# PATTERN x65d5a000/mask=xffffe000\n\n:ucvtf Zd.S, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m\n{\n\tZd.S = SVE_ucvtf(Zd.S, Pg3_m, Zn.D);\n}\n\n# ucvtf_z_p_z.xml: UCVTF variant 64-bit to double-precision\n# PATTERN x65d7a000/mask=xffffe000\n\n:ucvtf Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_ucvtf(Zd.D, Pg3_m, Zn.D);\n}\n\n# udiv_z_p_zz.xml: UDIV variant SVE\n# PATTERN x04950000/mask=xffbfe000\n\n:udiv Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m\n{\n\tZd.T_sz = SVE_udiv(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz);\n}\n\n# udivr_z_p_zz.xml: UDIVR variant SVE\n# PATTERN x04970000/mask=xffbfe000\n\n:udivr Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m\n{\n\tZd.T_sz = SVE_udivr(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz);\n}\n\n# udot_z_zzz.xml: UDOT (vectors) variant SVE\n# PATTERN x44800400/mask=xffa0fc00\n\n:udot Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz\nis sve_b_2431=0b01000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=0 & sve_zm_1620 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zm.Tb_sz & Zd.T_sz & Zn.Tb_sz\n{\n\tZd.T_sz = SVE_udot(Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz);\n}\n\n# udot_z_zzzi.xml: UDOT (indexed) variant 32-bit\n# PATTERN x44a00400/mask=xffe0fc00\n\n:udot Zd.S, Zn.B, Zm3.B[sve_i2_1920]\nis sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.B & Zm3.B\n{\n\tZd.S = SVE_udot(Zd.S, Zn.B, Zm3.B, sve_i2_1920:1);\n}\n\n# udot_z_zzzi.xml: UDOT (indexed) variant 64-bit\n# PATTERN x44e00400/mask=xffe0fc00\n\n:udot Zd.D, Zn.H, Zm4.H[sve_i1_20]\nis sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.H & Zm4.H\n{\n\tZd.D = SVE_udot(Zd.D, Zn.H, Zm4.H, sve_i1_20:1);\n}\n\n# umax_z_p_zz.xml: UMAX (vectors) variant SVE\n# PATTERN x04090000/mask=xff3fe000\n\n:umax Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_umax(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# umax_z_zi.xml: UMAX (immediate) variant SVE\n# PATTERN x2529c000/mask=xff3fe000\n\n:umax Zd.T, Zd.T_2, \"#\"^sve_imm8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_0to255\n{\n\tZd.T = SVE_umax(Zd.T, Zd.T_2, sve_imm8_1_0to255:1);\n}\n\n# umaxv_r_p_z.xml: UMAXV variant SVE\n# PATTERN x04092000/mask=xff3fe000\n\n:umaxv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_umaxv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# umaxv_r_p_z.xml: UMAXV variant SVE\n# PATTERN x04092000/mask=xff3fe000\n\n:umaxv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_umaxv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# umaxv_r_p_z.xml: UMAXV variant SVE\n# PATTERN x04092000/mask=xff3fe000\n\n:umaxv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_umaxv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# umaxv_r_p_z.xml: UMAXV variant SVE\n# PATTERN x04092000/mask=xff3fe000\n\n:umaxv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_umaxv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# umin_z_p_zz.xml: UMIN (vectors) variant SVE\n# PATTERN x040b0000/mask=xff3fe000\n\n:umin Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_umin(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# umin_z_zi.xml: UMIN (immediate) variant SVE\n# PATTERN x252bc000/mask=xff3fe000\n\n:umin Zd.T, Zd.T_2, \"#\"^sve_imm8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_0to255\n{\n\tZd.T = SVE_umin(Zd.T, Zd.T_2, sve_imm8_1_0to255:1);\n}\n\n# uminv_r_p_z.xml: UMINV variant SVE\n# PATTERN x040b2000/mask=xff3fe000\n\n:uminv Rd_FPR8, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3\n{\n\tRd_FPR8 = SVE_uminv(Rd_FPR8, Pg3, Zn.T);\n}\n\n# uminv_r_p_z.xml: UMINV variant SVE\n# PATTERN x040b2000/mask=xff3fe000\n\n:uminv Rd_FPR32, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3\n{\n\tRd_FPR32 = SVE_uminv(Rd_FPR32, Pg3, Zn.T);\n}\n\n# uminv_r_p_z.xml: UMINV variant SVE\n# PATTERN x040b2000/mask=xff3fe000\n\n:uminv Rd_FPR16, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3\n{\n\tRd_FPR16 = SVE_uminv(Rd_FPR16, Pg3, Zn.T);\n}\n\n# uminv_r_p_z.xml: UMINV variant SVE\n# PATTERN x040b2000/mask=xff3fe000\n\n:uminv Rd_FPR64, Pg3, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3\n{\n\tRd_FPR64 = SVE_uminv(Rd_FPR64, Pg3, Zn.T);\n}\n\n# umulh_z_p_zz.xml: UMULH variant SVE\n# PATTERN x04130000/mask=xff3fe000\n\n:umulh Zd.T, Pg3_m, Zd.T_2, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m\n{\n\tZd.T = SVE_umulh(Zd.T, Pg3_m, Zd.T_2, Zn.T);\n}\n\n# uqadd_z_zi.xml: UQADD (immediate) variant SVE\n# PATTERN x2525c000/mask=xff3fc000\n\n:uqadd Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_uqadd(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# uqadd_z_zz.xml: UQADD (vectors) variant SVE\n# PATTERN x04201400/mask=xff20fc00\n\n:uqadd Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b10 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_uqadd(Zd.T, Zn.T, Zm.T);\n}\n\n# uqdecb_r_rs.xml: UQDECB variant 32-bit\n# PATTERN x0420fc00/mask=xfff0fc00\n\n:uqdecb Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqdecb(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecb_r_rs.xml: UQDECB variant 64-bit\n# PATTERN x0430fc00/mask=xfff0fc00\n\n:uqdecb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqdecb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecd_r_rs.xml: UQDECD (scalar) variant 32-bit\n# PATTERN x04e0fc00/mask=xfff0fc00\n\n:uqdecd Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqdecd(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecd_r_rs.xml: UQDECD (scalar) variant 64-bit\n# PATTERN x04f0fc00/mask=xfff0fc00\n\n:uqdecd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqdecd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecd_z_zs.xml: UQDECD (vector) variant SVE\n# PATTERN x04e0cc00/mask=xfff0fc00\n\n:uqdecd Zd.D^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.D = SVE_uqdecd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdech_r_rs.xml: UQDECH (scalar) variant 32-bit\n# PATTERN x0460fc00/mask=xfff0fc00\n\n:uqdech Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqdech(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdech_r_rs.xml: UQDECH (scalar) variant 64-bit\n# PATTERN x0470fc00/mask=xfff0fc00\n\n:uqdech Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqdech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdech_z_zs.xml: UQDECH (vector) variant SVE\n# PATTERN x0460cc00/mask=xfff0fc00\n\n:uqdech Zd.H^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.H = SVE_uqdech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecp_r_p_r.xml: UQDECP (scalar) variant 32-bit\n# PATTERN x252b8800/mask=xff3ffe00\n\n:uqdecp Rd_GPR32, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32\n{\n\tRd_GPR32 = SVE_uqdecp(Rd_GPR32, Pn.T);\n}\n\n# uqdecp_r_p_r.xml: UQDECP (scalar) variant 64-bit\n# PATTERN x252b8c00/mask=xff3ffe00\n\n:uqdecp Rd_GPR64, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64\n{\n\tRd_GPR64 = SVE_uqdecp(Rd_GPR64, Pn.T);\n}\n\n# uqdecp_z_p_z.xml: UQDECP (vector) variant SVE\n# PATTERN x252b8000/mask=xff3ffe00\n\n:uqdecp Zd.T, Pn\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn\n{\n\tZd.T = SVE_uqdecp(Zd.T, Pn);\n}\n\n# uqdecw_r_rs.xml: UQDECW (scalar) variant 32-bit\n# PATTERN x04a0fc00/mask=xfff0fc00\n\n:uqdecw Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqdecw(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecw_r_rs.xml: UQDECW (scalar) variant 64-bit\n# PATTERN x04b0fc00/mask=xfff0fc00\n\n:uqdecw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqdecw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqdecw_z_zs.xml: UQDECW (vector) variant SVE\n# PATTERN x04a0cc00/mask=xfff0fc00\n\n:uqdecw Zd.S^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.S = SVE_uqdecw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincb_r_rs.xml: UQINCB variant 32-bit\n# PATTERN x0420f400/mask=xfff0fc00\n\n:uqincb Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqincb(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincb_r_rs.xml: UQINCB variant 64-bit\n# PATTERN x0430f400/mask=xfff0fc00\n\n:uqincb Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqincb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincd_r_rs.xml: UQINCD (scalar) variant 32-bit\n# PATTERN x04e0f400/mask=xfff0fc00\n\n:uqincd Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqincd(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincd_r_rs.xml: UQINCD (scalar) variant 64-bit\n# PATTERN x04f0f400/mask=xfff0fc00\n\n:uqincd Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqincd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincd_z_zs.xml: UQINCD (vector) variant SVE\n# PATTERN x04e0c400/mask=xfff0fc00\n\n:uqincd Zd.D^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.D = SVE_uqincd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqinch_r_rs.xml: UQINCH (scalar) variant 32-bit\n# PATTERN x0460f400/mask=xfff0fc00\n\n:uqinch Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqinch(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqinch_r_rs.xml: UQINCH (scalar) variant 64-bit\n# PATTERN x0470f400/mask=xfff0fc00\n\n:uqinch Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqinch(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqinch_z_zs.xml: UQINCH (vector) variant SVE\n# PATTERN x0460c400/mask=xfff0fc00\n\n:uqinch Zd.H^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.H = SVE_uqinch(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincp_r_p_r.xml: UQINCP (scalar) variant 32-bit\n# PATTERN x25298800/mask=xff3ffe00\n\n:uqincp Rd_GPR32, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32\n{\n\tRd_GPR32 = SVE_uqincp(Rd_GPR32, Pn.T);\n}\n\n# uqincp_r_p_r.xml: UQINCP (scalar) variant 64-bit\n# PATTERN x25298c00/mask=xff3ffe00\n\n:uqincp Rd_GPR64, Pn.T\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64\n{\n\tRd_GPR64 = SVE_uqincp(Rd_GPR64, Pn.T);\n}\n\n# uqincp_z_p_z.xml: UQINCP (vector) variant SVE\n# PATTERN x25298000/mask=xff3ffe00\n\n:uqincp Zd.T, Pn\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn\n{\n\tZd.T = SVE_uqincp(Zd.T, Pn);\n}\n\n# uqincw_r_rs.xml: UQINCW (scalar) variant 32-bit\n# PATTERN x04a0f400/mask=xfff0fc00\n\n:uqincw Rd_GPR32^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR32 = SVE_uqincw(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincw_r_rs.xml: UQINCW (scalar) variant 64-bit\n# PATTERN x04b0f400/mask=xfff0fc00\n\n:uqincw Rd_GPR64^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tRd_GPR64 = SVE_uqincw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqincw_z_zs.xml: UQINCW (vector) variant SVE\n# PATTERN x04a0c400/mask=xfff0fc00\n\n:uqincw Zd.S^sve_mul_pattern\nis sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern\n{\n\tZd.S = SVE_uqincw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);\n}\n\n# uqsub_z_zi.xml: UQSUB (immediate) variant SVE\n# PATTERN x2527c000/mask=xff3fc000\n\n:uqsub Zd.T, Zd.T_2, sve_shf8_1_0to255\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255\n{\n\tZd.T = SVE_uqsub(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);\n}\n\n# uqsub_z_zz.xml: UQSUB (vectors) variant SVE\n# PATTERN x04201c00/mask=xff20fc00\n\n:uqsub Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_uqsub(Zd.T, Zn.T, Zm.T);\n}\n\n# uunpkhi_z_z.xml: UUNPKHI, UUNPKLO variant High half\n# PATTERN x05333800/mask=xff3ffc00\n\n:uunpkhi Zd.T, Zn.Tb\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=1 & sve_b_16=1 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T\n{\n\tZd.T = SVE_uunpkhi(Zd.T, Zn.Tb);\n}\n\n# uunpkhi_z_z.xml: UUNPKHI, UUNPKLO variant Low half\n# PATTERN x05323800/mask=xff3ffc00\n\n:uunpklo Zd.T, Zn.Tb\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=1 & sve_b_16=0 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T\n{\n\tZd.T = SVE_uunpklo(Zd.T, Zn.Tb);\n}\n\n# uxtb_z_p_z.xml: UXTB, UXTH, UXTW variant Byte\n# PATTERN x0411a000/mask=xff3fe000\n\n:uxtb Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_uxtb(Zd.T, Pg3_m, Zn.T);\n}\n\n# uxtb_z_p_z.xml: UXTB, UXTH, UXTW variant Halfword\n# PATTERN x0413a000/mask=xff3fe000\n\n:uxth Zd.T, Pg3_m, Zn.T\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m\n{\n\tZd.T = SVE_uxth(Zd.T, Pg3_m, Zn.T);\n}\n\n# uxtb_z_p_z.xml: UXTB, UXTH, UXTW variant Word\n# PATTERN x0415a000/mask=xff3fe000\n\n:uxtw Zd.D, Pg3_m, Zn.D\nis sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m\n{\n\tZd.D = SVE_uxtw(Zd.D, Pg3_m, Zn.D);\n}\n\n# uzp1_p_pp.xml: UZP1, UZP2 (predicates) variant Even\n# PATTERN x05204800/mask=xff30fe10\n\n:uzp1 Pd.T, Pn.T, Pm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=1 & sve_b_10=0 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T\n{\n\tPd.T = SVE_uzp1(Pd.T, Pn.T, Pm.T);\n}\n\n# uzp1_p_pp.xml: UZP1, UZP2 (predicates) variant Odd\n# PATTERN x05204c00/mask=xff30fe10\n\n:uzp2 Pd.T, Pn.T, Pm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=1 & sve_b_10=1 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T\n{\n\tPd.T = SVE_uzp2(Pd.T, Pn.T, Pm.T);\n}\n\n# uzp1_z_zz.xml: UZP1, UZP2 (vectors) variant Even\n# PATTERN x05206800/mask=xff20fc00\n\n:uzp1 Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b01 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_uzp1(Zd.T, Zn.T, Zm.T);\n}\n\n# uzp1_z_zz.xml: UZP1, UZP2 (vectors) variant Odd\n# PATTERN x05206c00/mask=xff20fc00\n\n:uzp2 Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b01 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_uzp2(Zd.T, Zn.T, Zm.T);\n}\n\n# whilele_p_p_rr.xml: WHILELE variant SVE\n# PATTERN x25200410/mask=xff20ec10\n\n:whilele Pd.T, Rn_GPR64, Rm_GPR64\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64\n{\n\tPd.T = SVE_whilele(Pd.T, Rn_GPR64, Rm_GPR64);\n}\n\n# whilele_p_p_rr.xml: WHILELE variant SVE\n# PATTERN x25200410/mask=xff20ec10\n\n:whilele Pd.T, Rn_GPR32, Rm_GPR32\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32\n{\n\tPd.T = SVE_whilele(Pd.T, Rn_GPR32, Rm_GPR32);\n}\n\n# whilelo_p_p_rr.xml: WHILELO variant SVE\n# PATTERN x25200c00/mask=xff20ec10\n\n:whilelo Pd.T, Rn_GPR64, Rm_GPR64\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64\n{\n\tPd.T = SVE_whilelo(Pd.T, Rn_GPR64, Rm_GPR64);\n}\n\n# whilelo_p_p_rr.xml: WHILELO variant SVE\n# PATTERN x25200c00/mask=xff20ec10\n\n:whilelo Pd.T, Rn_GPR32, Rm_GPR32\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32\n{\n\tPd.T = SVE_whilelo(Pd.T, Rn_GPR32, Rm_GPR32);\n}\n\n# whilels_p_p_rr.xml: WHILELS variant SVE\n# PATTERN x25200c10/mask=xff20ec10\n\n:whilels Pd.T, Rn_GPR64, Rm_GPR64\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64\n{\n\tPd.T = SVE_whilels(Pd.T, Rn_GPR64, Rm_GPR64);\n}\n\n# whilels_p_p_rr.xml: WHILELS variant SVE\n# PATTERN x25200c10/mask=xff20ec10\n\n:whilels Pd.T, Rn_GPR32, Rm_GPR32\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32\n{\n\tPd.T = SVE_whilels(Pd.T, Rn_GPR32, Rm_GPR32);\n}\n\n# whilelt_p_p_rr.xml: WHILELT variant SVE\n# PATTERN x25200400/mask=xff20ec10\n\n:whilelt Pd.T, Rn_GPR64, Rm_GPR64\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64\n{\n\tPd.T = SVE_whilelt(Pd.T, Rn_GPR64, Rm_GPR64);\n}\n\n# whilelt_p_p_rr.xml: WHILELT variant SVE\n# PATTERN x25200400/mask=xff20ec10\n\n:whilelt Pd.T, Rn_GPR32, Rm_GPR32\nis sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32\n{\n\tPd.T = SVE_whilelt(Pd.T, Rn_GPR32, Rm_GPR32);\n}\n\n# wrffr_f_p.xml: WRFFR variant SVE\n# PATTERN x25289000/mask=xfffffe1f\n\n:wrffr Pn.B\nis sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_b_1019=0b1000100100 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Pn.B\n{\n\tSVE_wrffr(Pn.B);\n}\n\n# zip1_p_pp.xml: ZIP1, ZIP2 (predicates) variant High halves\n# PATTERN x05204400/mask=xff30fe10\n\n:zip2 Pd.T, Pn.T, Pm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=0 & sve_b_10=1 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T\n{\n\tPd.T = SVE_zip2(Pd.T, Pn.T, Pm.T);\n}\n\n# zip1_p_pp.xml: ZIP1, ZIP2 (predicates) variant Low halves\n# PATTERN x05204000/mask=xff30fe10\n\n:zip1 Pd.T, Pn.T, Pm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=0 & sve_b_10=0 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T\n{\n\tPd.T = SVE_zip1(Pd.T, Pn.T, Pm.T);\n}\n\n# zip1_z_zz.xml: ZIP1, ZIP2 (vectors) variant High halves\n# PATTERN x05206400/mask=xff20fc00\n\n:zip2 Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b00 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_zip2(Zd.T, Zn.T, Zm.T);\n}\n\n# zip1_z_zz.xml: ZIP1, ZIP2 (vectors) variant Low halves\n# PATTERN x05206000/mask=xff20fc00\n\n:zip1 Zd.T, Zn.T, Zm.T\nis sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T\n{\n\tZd.T = SVE_zip1(Zd.T, Zn.T, Zm.T);\n}\n" }, { "path": "pypcode/processors/AARCH64/data/languages/AppleSilicon.ldefs", "content": "\n\n \n AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions\n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/manuals/AARCH64.idx", "content": "@DDI0487H_a_a-profile_architecture_reference_manual.pdf[ARM Architecture Reference Manual - ARM A-profile architecture, December 2021 (ARM DDI 0487H.a)]\n\nabs,\t2017\nadc,\t1144\nadcs,\t1146\nadd,\t2019\naddg,\t1155\naddhn,\t2021\naddp,\t2025\nadds,\t1161\naddv,\t2027\nadr,\t1163\nadrp,\t1164\naesd,\t2029\naese,\t2030\naesimc,\t2031\naesmc,\t2032\nand,\t2033\nands,\t1171\nasr,\t1175\nasrv,\t1177\nat,\t1179\nautda,\t1181\nautdb,\t1182\nautia,\t1183\nautib,\t1186\naxflag,\t1189\nb,\t1191\nbc,\t1192\nbcax,\t2035\nbfc,\t1193\nbfcvt,\t2037\nbfcvtn,\t2038\nbfdot,\t2041\nbfi,\t1195\nbfm,\t1197\nbfmlalb,\t2045\nbfmmla,\t2046\nbfxil,\t1199\nbic,\t2050\nbics,\t1203\nbif,\t2052\nbit,\t2054\nbl,\t1205\nblr,\t1206\nblraa,\t1207\nbr,\t1209\nbraa,\t1210\nbrb,\t1212\nbrk,\t1213\nbsl,\t2056\nbti,\t1214\ncas,\t1223\ncasb,\t1216\ncash,\t1218\ncasp,\t1220\ncbnz,\t1226\ncbz,\t1227\nccmn,\t1230\nccmp,\t1234\ncfinv,\t1236\ncfp,\t1237\ncinc,\t1238\ncinv,\t1240\nclrex,\t1242\ncls,\t2058\nclz,\t2060\ncmeq,\t2064\ncmge,\t2070\ncmgt,\t2076\ncmhi,\t2079\ncmhs,\t2082\ncmle,\t2085\ncmlt,\t2088\ncmn,\t1250\ncmp,\t1256\ncmpp,\t1258\ncmtst,\t2090\ncneg,\t1259\ncnt,\t2092\ncpp,\t1261\ncpyfp,\t1262\ncpyfpn,\t1267\ncpyfprn,\t1272\ncpyfprt,\t1277\ncpyfprtn,\t1282\ncpyfprtrn,\t1287\ncpyfprtwn,\t1292\ncpyfpt,\t1297\ncpyfptn,\t1302\ncpyfptrn,\t1307\ncpyfptwn,\t1312\ncpyfpwn,\t1317\ncpyfpwt,\t1322\ncpyfpwtn,\t1327\ncpyfpwtrn,\t1332\ncpyfpwtwn,\t1337\ncpyp,\t1342\ncpypn,\t1348\ncpyprn,\t1354\ncpyprt,\t1360\ncpyprtn,\t1366\ncpyprtrn,\t1372\ncpyprtwn,\t1378\ncpypt,\t1384\ncpyptn,\t1390\ncpyptrn,\t1396\ncpyptwn,\t1402\ncpypwn,\t1408\ncpypwt,\t1414\ncpypwtn,\t1420\ncpypwtrn,\t1426\ncpypwtwn,\t1432\ncrc32b,\t1438\ncrc32cb,\t1440\ncsdb,\t1442\ncsel,\t1443\ncset,\t1445\ncsetm,\t1447\ncsinc,\t1449\ncsinv,\t1451\ncsneg,\t1453\ndc,\t1455\ndcps1,\t1457\ndcps2,\t1458\ndcps3,\t1459\ndgh,\t1460\ndmb,\t1461\ndrps,\t1463\ndsb,\t1464\ndup,\t2097\ndvp,\t1467\neon,\t1468\neor,\t2099\neor3,\t2101\neret,\t1474\neretaa,\t1475\nesb,\t1476\next,\t2102\nextr,\t1477\nfabd,\t2104\nfabs,\t2109\nfacge,\t2111\nfacgt,\t2115\nfadd,\t2121\nfaddp,\t2125\nfcadd,\t2127\nfccmp,\t2129\nfccmpe,\t2131\nfcmeq,\t2137\nfcmge,\t2144\nfcmgt,\t2151\nfcmla,\t2157\nfcmle,\t2160\nfcmlt,\t2163\nfcmp,\t2166\nfcmpe,\t2168\nfcsel,\t2170\nfcvt,\t2172\nfcvtas,\t2177\nfcvtau,\t2182\nfcvtl,\t2184\nfcvtms,\t2189\nfcvtmu,\t2194\nfcvtn,\t2196\nfcvtns,\t2201\nfcvtnu,\t2206\nfcvtps,\t2211\nfcvtpu,\t2216\nfcvtxn,\t2218\nfcvtzs,\t2229\nfcvtzu,\t2239\nfdiv,\t2243\nfjcvtzs,\t2245\nfmadd,\t2246\nfmax,\t2250\nfmaxnm,\t2254\nfmaxnmp,\t2258\nfmaxnmv,\t2260\nfmaxp,\t2264\nfmaxv,\t2266\nfmin,\t2270\nfminnm,\t2274\nfminnmp,\t2278\nfminnmv,\t2280\nfminp,\t2284\nfminv,\t2286\nfmla,\t2292\nfmlal,\t2296\nfmls,\t2302\nfmlsl,\t2306\nfmov,\t2316\nfmsub,\t2318\nfmul,\t2326\nfmulx,\t2332\nfneg,\t2337\nfnmadd,\t2339\nfnmsub,\t2341\nfnmul,\t2343\nfrecpe,\t2345\nfrecps,\t2348\nfrecpx,\t2351\nfrint32x,\t2355\nfrint32z,\t2359\nfrint64x,\t2363\nfrint64z,\t2367\nfrinta,\t2371\nfrinti,\t2375\nfrintm,\t2379\nfrintn,\t2383\nfrintp,\t2387\nfrintx,\t2391\nfrintz,\t2395\nfrsqrte,\t2397\nfrsqrts,\t2400\nfsqrt,\t2405\nfsub,\t2409\ngmi,\t1479\nhint,\t1480\nhlt,\t1482\nhvc,\t1483\nic,\t1484\nins,\t2413\nirg,\t1485\nisb,\t1487\nld1,\t2419\nld1r,\t2423\nld2,\t2429\nld2r,\t2433\nld3,\t2439\nld3r,\t2443\nld4,\t2449\nld4r,\t2453\nld64b,\t1488\nldadd,\t1493\nldaddb,\t1489\nldaddh,\t1491\nldapr,\t1496\nldaprb,\t1498\nldaprh,\t1500\nldapur,\t1502\nldapurb,\t1504\nldapurh,\t1506\nldapursb,\t1508\nldapursh,\t1510\nldapursw,\t1512\nldar,\t1514\nldarb,\t1516\nldarh,\t1517\nldaxp,\t1518\nldaxr,\t1520\nldaxrb,\t1522\nldaxrh,\t1523\nldclr,\t1528\nldclrb,\t1524\nldclrh,\t1526\nldeor,\t1535\nldeorb,\t1531\nldeorh,\t1533\nldg,\t1538\nldgm,\t1539\nldlar,\t1542\nldlarb,\t1540\nldlarh,\t1541\nldnp,\t2456\nldp,\t2458\nldpsw,\t1550\nldr,\t2468\nldraa,\t1560\nldrb,\t1565\nldrh,\t1570\nldrsb,\t1576\nldrsh,\t1582\nldrsw,\t1588\nldset,\t1594\nldsetb,\t1590\nldseth,\t1592\nldsmax,\t1601\nldsmaxb,\t1597\nldsmaxh,\t1599\nldsmin,\t1608\nldsminb,\t1604\nldsminh,\t1606\nldtr,\t1611\nldtrb,\t1613\nldtrh,\t1615\nldtrsb,\t1617\nldtrsh,\t1619\nldtrsw,\t1621\nldumax,\t1627\nldumaxb,\t1623\nldumaxh,\t1625\nldumin,\t1634\nlduminb,\t1630\nlduminh,\t1632\nldur,\t2471\nldurb,\t1639\nldurh,\t1640\nldursb,\t1641\nldursh,\t1643\nldursw,\t1645\nldxp,\t1646\nldxr,\t1648\nldxrb,\t1650\nldxrh,\t1651\nlsl,\t1654\nlslv,\t1656\nlsr,\t1660\nlsrv,\t1662\nmadd,\t1664\nmla,\t2475\nmls,\t2479\nmneg,\t1666\nmov,\t2488\nmovi,\t2490\nmovk,\t1677\nmovn,\t1679\nmovz,\t1681\nmrs,\t1683\nmsr,\t1688\nmsub,\t1689\nmul,\t2495\nmvn,\t2497\nmvni,\t2498\nneg,\t2501\nnegs,\t1696\nngc,\t1698\nngcs,\t1700\nnop,\t1702\nnot,\t2503\norn,\t2505\norr,\t2509\npacda,\t1709\npacdb,\t1710\npacga,\t1711\npacia,\t1712\npacib,\t1715\npmul,\t2511\npmull,\t2513\nprfm,\t1722\nprfum,\t1724\npsb,\t1726\npssbb,\t1727\nraddhn,\t2515\nrax1,\t2517\nrbit,\t2518\nret,\t1730\nretaa,\t1731\nrev,\t1732\nrev16,\t2520\nrev32,\t2522\nrev64,\t2524\nrmif,\t1739\nror,\t1742\nrorv,\t1744\nrshrn,\t2526\nrsubhn,\t2528\nsaba,\t2530\nsabal,\t2532\nsabd,\t2534\nsabdl,\t2536\nsadalp,\t2538\nsaddl,\t2540\nsaddlp,\t2542\nsaddlv,\t2544\nsaddw,\t2546\nsb,\t1746\nsbc,\t1747\nsbcs,\t1749\nsbfiz,\t1751\nsbfm,\t1753\nsbfx,\t1756\nscvtf,\t2556\nsdiv,\t1758\nsdot,\t2560\nsetf8,\t1759\nsetgp,\t1760\nsetgpn,\t1765\nsetgpt,\t1770\nsetgptn,\t1775\nsetp,\t1780\nsetpn,\t1784\nsetpt,\t1788\nsetptn,\t1792\nsev,\t1796\nsevl,\t1797\nsha1c,\t2562\nsha1h,\t2563\nsha1m,\t2564\nsha1p,\t2565\nsha1su0,\t2566\nsha1su1,\t2567\nsha256h,\t2569\nsha256h2,\t2568\nsha256su0,\t2570\nsha256su1,\t2571\nsha512h,\t2573\nsha512h2,\t2575\nsha512su0,\t2577\nsha512su1,\t2578\nshadd,\t2580\nshl,\t2582\nshll,\t2585\nshrn,\t2587\nshsub,\t2589\nsli,\t2591\nsm3partw1,\t2594\nsm3partw2,\t2596\nsm3ss1,\t2598\nsm3tt1a,\t2600\nsm3tt1b,\t2602\nsm3tt2a,\t2604\nsm3tt2b,\t2606\nsm4e,\t2608\nsm4ekey,\t2610\nsmaddl,\t1798\nsmax,\t2612\nsmaxp,\t2614\nsmaxv,\t2616\nsmc,\t1800\nsmin,\t2618\nsminp,\t2620\nsminv,\t2622\nsmlal,\t2627\nsmlsl,\t2632\nsmmla,\t2634\nsmnegl,\t1801\nsmov,\t2635\nsmstart,\t1802\nsmstop,\t1804\nsmsubl,\t1806\nsmulh,\t1808\nsmull,\t2640\nsqabs,\t2642\nsqadd,\t2644\nsqdmlal,\t2650\nsqdmlsl,\t2657\nsqdmulh,\t2663\nsqdmull,\t2668\nsqneg,\t2671\nsqrdmlah,\t2676\nsqrdmlsh,\t2682\nsqrdmulh,\t2688\nsqrshl,\t2690\nsqrshrn,\t2692\nsqrshrun,\t2695\nsqshl,\t2701\nsqshlu,\t2703\nsqshrn,\t2706\nsqshrun,\t2709\nsqsub,\t2712\nsqxtn,\t2714\nsqxtun,\t2717\nsrhadd,\t2720\nsri,\t2722\nsrshl,\t2725\nsrshr,\t2727\nsrsra,\t2730\nssbb,\t1810\nsshl,\t2733\nsshll,\t2736\nsshr,\t2738\nssra,\t2741\nssubl,\t2744\nssubw,\t2746\nst1,\t2752\nst2,\t2759\nst2g,\t1811\nst3,\t2766\nst4,\t2773\nst64b,\t1813\nst64bv,\t1814\nst64bv0,\t1816\nstadd,\t1822\nstaddb,\t1818\nstaddh,\t1820\nstclr,\t1828\nstclrb,\t1824\nstclrh,\t1826\nsteor,\t1834\nsteorb,\t1830\nsteorh,\t1832\nstg,\t1836\nstgm,\t1838\nstgp,\t1839\nstllr,\t1844\nstllrb,\t1842\nstllrh,\t1843\nstlr,\t1846\nstlrb,\t1848\nstlrh,\t1849\nstlur,\t1850\nstlurb,\t1852\nstlurh,\t1854\nstlxp,\t1856\nstlxr,\t1859\nstlxrb,\t1862\nstlxrh,\t1864\nstnp,\t2777\nstp,\t2779\nstr,\t2786\nstrb,\t1879\nstrh,\t1884\nstset,\t1890\nstsetb,\t1886\nstseth,\t1888\nstsmax,\t1896\nstsmaxb,\t1892\nstsmaxh,\t1894\nstsmin,\t1902\nstsminb,\t1898\nstsminh,\t1900\nsttr,\t1904\nsttrb,\t1906\nsttrh,\t1908\nstumax,\t1914\nstumaxb,\t1910\nstumaxh,\t1912\nstumin,\t1920\nstuminb,\t1916\nstuminh,\t1918\nstur,\t2789\nsturb,\t1924\nsturh,\t1925\nstxp,\t1926\nstxr,\t1929\nstxrb,\t1931\nstxrh,\t1933\nstz2g,\t1935\nstzg,\t1937\nstzgm,\t1939\nsub,\t2791\nsubg,\t1947\nsubhn,\t2793\nsubp,\t1948\nsubps,\t1949\nsubs,\t1955\nsudot,\t2795\nsuqadd,\t2797\nsvc,\t1957\nswp,\t1962\nswpb,\t1958\nswph,\t1960\nsxtb,\t1964\nsxth,\t1966\nsxtl,\t2799\nsxtw,\t1968\nsys,\t1969\nsysl,\t1971\ntbl,\t2801\ntbnz,\t1972\ntbx,\t2803\ntbz,\t1973\ntcancel,\t1974\ntcommit,\t1975\ntlbi,\t1976\ntrn1,\t2805\ntrn2,\t2807\ntsb,\t1982\ntst,\t1984\ntstart,\t1979\nttest,\t1981\nuaba,\t2809\nuabal,\t2811\nuabd,\t2813\nuabdl,\t2815\nuadalp,\t2817\nuaddl,\t2819\nuaddlp,\t2821\nuaddlv,\t2823\nuaddw,\t2825\nubfiz,\t1986\nubfm,\t1988\nubfx,\t1991\nucvtf,\t2835\nudf,\t1993\nudiv,\t1994\nudot,\t2839\nuhadd,\t2841\nuhsub,\t2843\numaddl,\t1995\numax,\t2845\numaxp,\t2847\numaxv,\t2849\numin,\t2851\numinp,\t2853\numinv,\t2855\numlal,\t2860\numlsl,\t2865\nummla,\t2867\numnegl,\t1997\numov,\t2868\numsubl,\t1998\numulh,\t2000\numull,\t2873\nuqadd,\t2875\nuqrshl,\t2877\nuqrshrn,\t2879\nuqshl,\t2885\nuqshrn,\t2887\nuqsub,\t2890\nuqxtn,\t2892\nurecpe,\t2895\nurhadd,\t2896\nurshl,\t2898\nurshr,\t2900\nursqrte,\t2903\nursra,\t2904\nusdot,\t2909\nushl,\t2911\nushll,\t2914\nushr,\t2916\nusmmla,\t2919\nusqadd,\t2920\nusra,\t2922\nusubl,\t2925\nusubw,\t2927\nuxtb,\t2002\nuxth,\t2003\nuxtl,\t2929\nuzp1,\t2931\nuzp2,\t2933\nwfe,\t2004\nwfet,\t2005\nwfi,\t2006\nwfit,\t2007\nxaflag,\t2008\nxar,\t2935\nxpacd,\t2009\nxtn,\t2936\nyield,\t2011\nzip1,\t2938\nzip2,\t2940\n" }, { "path": "pypcode/processors/AARCH64/data/patterns/AARCH64_LE_patterns.xml", "content": " \n \n \n 0xc0 0x03 0x5f 0xd6 \n 0xc0 0x03 0x5f 0xd6 0x1f 0x20 0x03 0xd5 \n 0xc0 0x03 0x5f 0xd6 0x1f 0x20 0x03 0xd5 0x1f 0x20 0x03 0xd5 \n 0xff 0x0f 0x5f 0xd6 \n ........ ........ ........ 000101.. \n 0x20 0x00 0x20 0xd4 \n \n \n \n 0xfd 0x7b 0xbf 0xa9 \n 0xfe .0001111 0x1. 0xf8 \n 111..... .1....11 10...... 0xa9 \n 11101..1 001..011 1011.... 0x6d \n 0xff ..000011 000..... 0xd1 \n 0x7f 0x23 0x03 0xd5 \n .1011111 0x24 0x03 0xd5 \n \n \n \n \n \n \n 111..... .1....11 10...... 0xa9 \n \n \n \n \n 0x........ 111..... .1....11 10...... 0xa9 \n \n \n \n \n 0xfe .0001111 0x1. 0xf8 \n \n \n \n \n 0x........ 0xfe .0001111 0x1. 0xf8 \n \n \n\n \n 0xfd 0x7b 0xbf 0xa9 0xfd 0x03 0x00 0x91 \n \n \n \n \n \n 0x7f 0x23 0x03 0xd5 0xff ..000011 00000... 0xd1 \n \n \n \n \n \n \n\t\t ...10000 ........ ........ 1..10000 \n 00010001 ........ 01...... 0xf9 \n 0x10 ......10 00...... 0x91 \n 0x20 0x02 0x1f 0xd6 \n \n \n \n \n \n \n \n\t\t .1011111 0x24 0x03 0xd5 \n\t\t ...10000 ........ ........ 1..10000 \n 00010001 ........ 01...... 0xf9 \n 0x10 ......10 00...... 0x91 \n 0x20 0x02 0x1f 0xd6 \n \n \n \n \n \n \n \n\t\t .1011111 0x24 0x03 0xd5 \n\t\t 0xf0 0x7b 0xbf 0xa9 \n\t\t ...10000 ........ ........ 1..10000 \n 00010001 ........ 01...... 0xf9 \n 0x10 ......10 00...... 0x91 \n 0x20 0x02 0x1f 0xd6 \n \n \n \n \n\n" }, { "path": "pypcode/processors/AARCH64/data/patterns/AARCH64_win_patterns.xml", "content": "\n \n \n \n \n \n 0xff 0x43 0x00 0xd1 \n ...10001 ........ ........ 1..10000 \n 00110001 ......10 01...... 11111001\n 0xf1 0x63 0x31 0xcb \n 0xf1 0x07 0x00 0xf9 \n 0xc0 0x03 0x5f 0xd6 \n \n \n \n \n \n \n ...10001 ........ ........ 1..10000 \n 0xf0 0x07 0x40 0xf9 \n 00110001 ......10 01...... 11111001\n 0xf0 0x63 0x30 0xcb \n 0x1f 0x02 0x11 0xeb \n ...00001 ........ ........ 01010100\n 0xff 0x43 0x00 0x91 \n 0xc0 0x03 0x5f 0xd6 \n 0x1f 0x20 0x03 0xd5 \n \n \n \n \n \n" }, { "path": "pypcode/processors/AARCH64/data/patterns/patternconstraints.xml", "content": "\n \n AARCH64_LE_patterns.xml\n \n\n" }, { "path": "pypcode/processors/AARCH64/data/patterns/prepatternconstraints.xml", "content": "\n \n \n AARCH64_win_patterns.xml\n \n \n" }, { "path": "pypcode/processors/ARM/data/languages/ARM.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n ;\n offset = *:1 (lr + r3);\n r3 = zext(offset);\n \n \n if (inbounds) goto ;\n offset = *:1 (lr + r12);\n r3 = zext(offset);\n \n \n r3 = r3 * 2;\n \n r12 = lr + r3;\n \n ISAModeSwitch = (r12 & 1) != 1;\n TB = ISAModeSwitch;\n pc = r12 & 0xfffffffe;\n goto [pc];\n ]]>\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM.dwarf", "content": "\n\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n\t\n\t\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM.gdis", "content": "\n\n \n TMode\n \n \n\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM.ldefs", "content": "\n\n\n \n Generic ARM/Thumb v8 little endian\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n Generic ARM/Thumb v8 little endian (Thumb is default)\n \n \n \n \n \n \n \n \n \n \n \n \n \n Generic ARM/Thumb v8 little endian instructions and big endian data\n \n \n \n \n \n \n \n Generic ARM/Thumb v8 big endian\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n Generic ARM/Thumb v8 big endian (Thumb is default)\n \n \n \n \n \n \n \n \n \n \n \n Generic ARM/Thumb v7 little endian\n \n \n \n \n \n \n \n \n \n \n \n\n \n Generic ARM/Thumb v7 little endian instructions and big endian data\n \n \n \n \n \n \n \n Generic ARM/Thumb v7 big endian\n \n \n \n \n \n \n \n \n \n \n\n \n ARM Cortex / Thumb little endian\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n ARM Cortex / Thumb big endian\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n ARM Cortex v8-m little endian\n \n \n \n \n \n \n \n \n \n ARM Cortex v8-m big endian\n \n \n \n \n \n \n \n \n \n \n Generic ARM/Thumb v6 little endian\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n Generic ARM/Thumb v6 big endian\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n Generic ARM/Thumb v5 little endian (T-variant)\n \n \n \n \n \n \n \n \n \n \n\n \n Generic ARM/Thumb v5 big endian (T-variant)\n \n \n \n \n \n \n \n \n \n \n\n \n Generic ARM v5 little endian\n \n \n \n \n \n \n \n \n\n \n Generic ARM v5 big endian\n \n \n \n \n \n \n \n \n\n \n Generic ARM/Thumb v4 little endian (T-variant)\n \n \n \n \n \n \n \n \n \n\n \n Generic ARM/Thumb v4 big endian (T-variant)\n \n \n \n \n \n \n \n \n \n\n \n Generic ARM v4 little endian\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n Generic ARM v4 big endian\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM.sinc", "content": "# Specification for the ARM Version 4, 4T, 5, 5T, 5E\n# The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E\n\ndefine endian=$(ENDIAN);\ndefine alignment=2;\n\ndefine space ram type=ram_space size=4 default;\ndefine space register type=register_space size=4;\n\ndefine register offset=0x0020 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7\tr8 r9 r10 r11 r12 sp lr pc ];\ndefine register offset=0x0060 size=1 [ NG ZR CY OV tmpNG tmpZR tmpCY tmpOV shift_carry TB Q GE1 GE2 GE3 GE4 ]; \ndefine register offset=0x0070 size=4 [ cpsr spsr ];\ndefine register offset=0x0080 size=4 [ mult_addr ];\t# Special internal register for dealing with multiple stores/loads\ndefine register offset=0x0084 size=4 [ r14_svc r13_svc spsr_svc ];\ndefine register offset=0x0090 size=8 [ mult_dat8 ];\t# Special internal register for dealing with multiple stores/loads\ndefine register offset=0x0090 size=16 [ mult_dat16 ];\t# Special internal register for dealing with multiple stores/loads\ndefine register offset=0x00A0 size=4 [ fpsr ];\t\t# floating point state register (for FPA10 floating-point accelerator)\ndefine register offset=0x0078 size=1 [ ISAModeSwitch ]; # generic name for TB ThumbBit - set same as TB\n\n@define FPSCR_N \"fpscr[31,1]\"\n@define FPSCR_Z \"fpscr[30,1]\"\n@define FPSCR_C \"fpscr[29,1]\"\n@define FPSCR_V \"fpscr[28,1]\"\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\ndefine register offset=0x00B0 size=4 [ fpsid fpscr fpexc mvfr0 mvfr1 mvfr2 fpinst fpinst2 ];\n@endif\ndefine register offset=0x0100 size=10 [ fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 ];\t# eight 80-bit floating registers\n\n# pseudo-registers for coprocessor calculations\ndefine register offset=0x0200 size=4 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ];\n\n# Advanced SIMD and VFP extension registers\n@if defined(VFPv2) || defined(VFPv3)\n\n@if ENDIAN == \"little\"\n define register offset=0x0300 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 \n \t\t\t\t\t\t\t\t\t\ts16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 ];\n@else # ENDIAN == \"big\"\n define register offset=0x0300 size=4 [ s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16\n \t\t\t\t\t\t\t\t\t\ts15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 ];\n@endif # ENDIAN = \"big\"\n \n@endif # VFPv2 || VFPv3\n\n@if defined(VFPv2)\n\n@if ENDIAN == \"little\"\n define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];\n@else # ENDIAN == \"big\"\n define register offset=0x0300 size=8 [ d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ];\n@endif # ENDIAN = \"big\"\n\n@endif # VFPv2\n\n@if defined(SIMD) || defined(VFPv3)\n\n@if ENDIAN == \"little\"\n define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 \n \t\t\t\t\t\t\t\t\t\td16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ];\n@else # ENDIAN == \"big\"\n define register offset=0x0300 size=8 [ d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16\n \t\t\t\t\t\t\t\t\t\td15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ];\n@endif # ENDIAN = \"big\"\n\n@endif # SIMD || VFPv3\n\n@if defined(SIMD)\n\n@if ENDIAN == \"little\"\n define register offset=0x0300 size=16 [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ];\n@else # ENDIAN == \"big\"\n define register offset=0x0300 size=16 [ q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 ];\n@endif # ENDIAN = \"big\"\n\n@endif # SIMD\n\n@if defined(CORTEX)\n define register offset=0x400 size=4 [ msplim psplim ];\n@endif\n\n# Define context bits\n# WARNING: when adjusting context keep compiler packing in mind\n# and make sure fields do not span a 32-bit boundary before or \n# after context packing\ndefine register offset=0x00 size=8 contextreg;\ndefine context contextreg\n@ifdef T_VARIANT\n \tTMode\t\t = (0,0) # 1 if in Thumb instruction decode mode\n \tT \t\t = (0,0) # exact copy (alias!) of TMode\n \tLowBitCodeMode = (0,0) # 1 if low bit of instruction address is set on a branch\n \tISA_MODE = (0,0) # 1 for Thumb instruction decode mode\n@endif\n \tLRset = (1,1) noflow # 1 if the instruction right before was a mov lr,pc\n \tREToverride = (2,2) noflow # 1 if the instruction should be a branch not a return\n \tCALLoverride = (3,3) noflow # 1 if the call should actually be a jump\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\tTEEMode = (4,4) # 1 if in ThumbEE mode, changes some instruction behavior, and makes some instructions invalid\n \tcondit = (5,13) noflow # both base and shift\n \tcond_mask = (10,13) # base condition\n \tcond_full = (6,9) # full condition\n \tcond_true = (9,9) # true if this condition should be tested for true\n \tcond_base = (6,8) # shift mask for controlling shift\n \tcond_shft = (9,13) # mask and lower bit of it condition field\n \titmode = (5,5) # true if in ITBlock mode\n \n@endif\n\n\t# Transient context bits\n\tcounter\t\t= (14,18)\t# 0 to 7 counter (for building variable length register lists)\n#\tdreg\t\t= (17,21)\t# D register (attached, for building register lists)\n#\tsreg\t\t= (17,21)\t# S register (attached, for building register lists)\n\tregNum\t\t= (19,23)\t# D register number (see dreg)\n\tcounter2\t= (24,26)\t# 0 to 7 counter (for building variable length register lists)\n#\tdreg2\t\t= (25,29)\t# 2nd D register (attached, for building register lists)\n#\tsreg2\t\t= (25,29)\t# 2nd S register (attached, for building register lists)\n\treg2Num\t\t= (27,31)\t# 2nd D register number (see dreg2)\n# --- do not allow any field to span 32-bit boundary ---\n\tregInc\t\t= (32,33)\t# Pair register increment\n\tARMcond\t\t= (34,34)\t# ARM conditional instruction\n\tARMcondCk\t= (35,35) # Finished ARM condition check phase\n;\n\ndefine pcodeop coprocessor_function;\ndefine pcodeop coprocessor_function2;\ndefine pcodeop coprocessor_load;\ndefine pcodeop coprocessor_load2;\ndefine pcodeop coprocessor_loadlong;\ndefine pcodeop coprocessor_loadlong2;\ndefine pcodeop coprocessor_moveto;\ndefine pcodeop coprocessor_moveto2;\ndefine pcodeop coprocessor_movefromRt;\ndefine pcodeop coprocessor_movefromRt2;\ndefine pcodeop coprocessor_movefrom2;\ndefine pcodeop coprocessor_store;\ndefine pcodeop coprocessor_store2;\ndefine pcodeop coprocessor_storelong;\ndefine pcodeop coprocessor_storelong2;\ndefine pcodeop software_interrupt;\ndefine pcodeop software_bkpt;\ndefine pcodeop software_udf;\ndefine pcodeop software_hlt;\ndefine pcodeop software_hvc;\ndefine pcodeop software_smc;\n\n# CPS methods (Version 6)\ndefine pcodeop setUserMode;\ndefine pcodeop setFIQMode;\ndefine pcodeop setIRQMode;\ndefine pcodeop setSupervisorMode;\ndefine pcodeop setMonitorMode;\ndefine pcodeop setAbortMode;\ndefine pcodeop setUndefinedMode;\ndefine pcodeop setSystemMode;\ndefine pcodeop enableIRQinterrupts;\ndefine pcodeop enableFIQinterrupts;\ndefine pcodeop enableDataAbortInterrupts;\ndefine pcodeop disableIRQinterrupts;\ndefine pcodeop disableFIQinterrupts;\ndefine pcodeop isFIQinterruptsEnabled;\ndefine pcodeop isIRQinterruptsEnabled;\ndefine pcodeop disableDataAbortInterrupts;\ndefine pcodeop hasExclusiveAccess;\ndefine pcodeop isCurrentModePrivileged;\ndefine pcodeop setThreadModePrivileged;\ndefine pcodeop isThreadMode;\n\ndefine pcodeop jazelle_branch;\ndefine pcodeop ClearExclusiveLocal;\ndefine pcodeop HintDebug;\n\ndefine pcodeop DataMemoryBarrier;\ndefine pcodeop DataSynchronizationBarrier;\n\ndefine pcodeop secureMonitorCall;\n\ndefine pcodeop WaitForEvent;\ndefine pcodeop WaitForInterrupt;\n\ndefine pcodeop HintYield;\ndefine pcodeop InstructionSynchronizationBarrier;\n\ndefine pcodeop HintPreloadData;\ndefine pcodeop HintPreloadDataForWrite;\ndefine pcodeop HintPreloadInstruction;\n\ndefine pcodeop SignedSaturate;\ndefine pcodeop SignedDoesSaturate;\ndefine pcodeop UnsignedSaturate;\ndefine pcodeop UnsignedDoesSaturate;\ndefine pcodeop Absolute;\ndefine pcodeop ReverseBitOrder;\ndefine pcodeop SendEvent;\ndefine pcodeop setEndianState;\n\n# Copies ISAModeSwitch to TMode\ndefine pcodeop setISAMode;\n\nmacro affectflags() {\n CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV;\n}\n\nmacro affect_resflags() {\n ZR = tmpZR; NG = tmpNG;\n}\n\nmacro SetISAModeSwitch(value) {\n ISAModeSwitch = value;\n TB = ISAModeSwitch;\n}\n\nmacro SetThumbMode(value) {\n SetISAModeSwitch(value);\n setISAMode();\n}\n\n#\n# simple branch, not inter-working\nmacro BranchWritePC(addr) {\n pc = addr;\n}\n\n#\n# Interworking branch, ARM<->Thumb\nmacro BXWritePC(addr) {\n SetThumbMode((addr & 0x1) != 0);\n local tmp = addr & 0xfffffffe;\n pc = tmp;\n}\n\n#\n# Branch depends on version\nmacro LoadWritePC(addr) {\n@if defined(VERSION_5)\n BXWritePC(addr);\n@else\n BranchWritePC(addr);\n@endif\n}\n\n# Branch depends on version\nmacro ALUWritePC(addr) {\n@if defined(VERSION_7)\n BXWritePC(addr);\n@else\n BranchWritePC(addr);\n@endif\n}\n\n@if defined(T_VARIANT)\n\nItCond: is TMode=1\t\t\t{ }\nCheckInIT_CZNO: is TMode=1 \t { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }\t\t# in older, arms always affect flags\nCheckInIT_CZN: is TMode=1 \t { CY = tmpCY; ZR = tmpZR; NG = tmpNG; }\t\t# in older, arms always affect flags\nCheckInIT_ZN: is TMode=1\t\t\t{ ZR = tmpZR; NG = tmpNG; } \t\t\t\t\t\t\t# in older, arms always affect flags\n\n@endif\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n# conditionals for instruction following IT Block\nthfcc: \"eq\"\tis cond_full=0\t{ local tmp:1 = (ZR!=0); export tmp; }\nthfcc: \"ne\"\tis cond_full=1\t{ local tmp:1 = (ZR==0); export tmp; }\nthfcc: \"cs\"\tis cond_full=2\t{ local tmp:1 = (CY!=0); export tmp; }\nthfcc: \"cc\"\tis cond_full=3\t{ local tmp:1 = (CY==0); export tmp; }\nthfcc: \"mi\"\tis cond_full=4\t{ local tmp:1 = (NG!=0); export tmp; }\nthfcc: \"pl\"\tis cond_full=5\t{ local tmp:1 = (NG==0); export tmp; }\nthfcc: \"vs\"\tis cond_full=6\t{ local tmp:1 = (OV!=0); export tmp; }\nthfcc: \"vc\"\tis cond_full=7\t{ local tmp:1 = (OV==0); export tmp; }\nthfcc: \"hi\"\tis cond_full=8\t{ local tmp:1 = CY && !ZR; export tmp; }\nthfcc: \"ls\"\tis cond_full=9\t{ local tmp:1 = !CY || ZR; export tmp; }\nthfcc: \"ge\"\tis cond_full=10\t{ local tmp:1 = (NG == OV); export tmp; }\nthfcc: \"lt\"\tis cond_full=11\t{ local tmp:1 = (NG != OV); export tmp; }\nthfcc: \"gt\"\tis cond_full=12\t{ local tmp:1 = !ZR && (NG == OV); export tmp; }\nthfcc: \"le\"\tis cond_full=13\t{ local tmp:1 = ZR || (NG != OV); export tmp; }\nthfcc: \"al\" is cond_full=14 { local tmp:1 = 1; export tmp; } #can happen\n#thfcc: \"nv\" is cond_full=15 { local tmp:1 = 0; export tmp; } #unpredictable, shouldn't happen\n\n\n# no ITcondition\nItCond: is TMode=1 & itmode=0 & cond_mask=0 {}\n# ITBlock then/else case - the condition being tested is modified by the shift below\nItCond: \".\"thfcc is TMode=1 & itmode=0 & cond_mask & thfcc [ itmode=1; globalset(inst_next,condit);]\n { if (!thfcc) goto inst_next; }\n\n# last ITBlock then/else case - the condition being tested is modified by the shift below\nItCond: \".\"thfcc is TMode=1 & itmode=0 & cond_mask=8 & thfcc\n { if (!thfcc) goto inst_next; }\n\n# certain Thumb instructions don't affect all flags in the IT block\nCheckInIT_CZNO: is TMode=1 & itmode=1 & cond_mask \t { } # Do nothing to the flag bits\nCheckInIT_CZNO: is TMode=1 & itmode=0 & cond_mask \t { } # Do nothing to the flag bits\nCheckInIT_CZNO: \"s\" is TMode=1 & itmode=0 & cond_mask=0 \t { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }\n\nCheckInIT_CZN: is TMode=1 & itmode=1 & cond_mask \t { } # Do nothing to the flag bits\nCheckInIT_CZN: is TMode=1 & itmode=0 & cond_mask \t { } # Do nothing to the flag bits\nCheckInIT_CZN: \"s\" is TMode=1 & itmode=0 & cond_mask=0 \t { CY = tmpCY; ZR = tmpZR; NG = tmpNG; }\n\nCheckInIT_ZN: is TMode=1 & itmode=1 & cond_mask \t { } # Do nothing to the flag bits\nCheckInIT_ZN: is TMode=1 & itmode=0 & cond_mask \t { } # Do nothing to the flag bits\nCheckInIT_ZN: \"s\" is TMode=1 & itmode=0 & cond_mask=0\t\t\t{ ZR = tmpZR; NG = tmpNG; }\n\n\n:^instruction is itmode=1 & cond_mask=8 & instruction [ condit=0; ] {}\n:^instruction is itmode=1 & cond_mask & instruction [ cond_shft=cond_shft << 1; itmode=0; ]{}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n@include \"ARMinstructions.sinc\"\n\n# THUMB instructions\n@ifdef T_VARIANT\n@include \"ARMTHUMBinstructions.sinc\"\n@endif\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM4_be.slaspec", "content": "\n@define ENDIAN \"big\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM4_le.slaspec", "content": "\n@define ENDIAN \"little\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM4t_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define T_VARIANT \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM4t_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define T_VARIANT \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM5_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM5_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM5t_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n\n@include \"ARM.sinc\"\n\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM5t_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM6_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VFPv2 \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM6_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VFPv2 \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM7_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VERSION_7 \"\"\n@define VERSION_7M \"\"\n@define SIMD \"\"\n@define VFPv3 \"\"\n@define VFPv4 \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM7_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VERSION_7 \"\"\n@define VERSION_7M \"\"\n@define SIMD \"\"\n@define VFPv3 \"\"\n@define VFPv4 \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM8_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VERSION_7 \"\"\n@define VERSION_7M \"\"\n@define VERSION_8 \"\"\n@define SIMD \"\"\n@define VFPv3 \"\"\n@define VFPv4 \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM8_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VERSION_7 \"\"\n@define VERSION_7M \"\"\n@define VERSION_8 \"\"\n@define SIMD \"\"\n@define VFPv3 \"\"\n@define VFPv4 \"\"\n\n@include \"ARM.sinc\"\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM8m_be.slaspec", "content": "\n@define ENDIAN \"big\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VERSION_7 \"\"\n@define VERSION_7M \"\"\n@define VERSION_8 \"\"\n@define SIMD \"\"\n@define CDE \"\"\n@define CORTEX \"\"\n@define VFPv3 \"\"\n@define VFPv4 \"\"\n\n@include \"ARM.sinc\"\n@include \"ARM_CDE.sinc\"\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM8m_le.slaspec", "content": "\n@define ENDIAN \"little\"\n@define T_VARIANT \"\"\n@define VERSION_5 \"\"\n@define VERSION_5E \"\"\n@define VERSION_6 \"\"\n@define VERSION_6K \"\"\n@define VERSION_6T2 \"\"\n@define VERSION_7 \"\"\n@define VERSION_7M \"\"\n@define VERSION_8 \"\"\n@define SIMD \"\"\n@define CDE \"\"\n@define CORTEX \"\"\n@define VFPv3 \"\"\n@define VFPv4 \"\"\n\n@include \"ARM.sinc\"\n@include \"ARM_CDE.sinc\"\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMCortex.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc", "content": "# Specification for the THUMB Version 2\n# This closely follows\n# \"Architecture Reference Manual\" Second Edition Edited by David Seal\n\n#\n# WARNING NOTE: Be very careful taking a subpiece or truncating a register with :# or (#)\n# The LEBE hybrid language causes endian issues if you do not assign the register to a temp\n# variable and then take a subpiece or truncate.\n#\n\ndefine token instr2 (16)\n part2op=(11,15) # this second instruction token is needed for the\n part2J1=(13,13)\n part2J2=(11,11)\n part2cond=(6,9)\n part2imm6=(0,5)\n part2S=(10,10)\n part2imm11=(0,10)\n part2imm10=(0,9)\n part2off=(0,10) # bl and blx instructions which use 2 16-bit instructions\n part2off_10=(1,10) # blx instruction which switches to ARM mode\n part2c1415=(14,15)\n part2c1212=(12,12)\n part2c0615=(6,15)\n part2Rt=(12,15)\n part2c0011=(0,11)\n part2c0909=(9,9)\n part2c0808=(8,8)\n part2c0707=(7,7)\n part2c0505=(5,5)\n part2c0404=(4,4)\n part2Rd0003=(0,3)\n;\n\ndefine token instrThumb (16)\n op4=(4,15)\n op6=(6,15)\n op7=(7,15)\n op8=(8,15)\n op9=(9,15)\n op11=(11,15)\n op12=(12,15)\n op13=(13,15)\n op0=(0,15)\n sop0407=(4,7)\n sop0507=(5,7)\n sop0508=(5,8)\n sop0003=(0,3)\n sop0608=(6,8)\n sop0610=(6,10)\n \n sopit=(0,7)\n\n Ra1215=(12,15)\n Rd0002=(0,2)\n Rd0003=(0,3)\n Rd0810=(8,10)\n Rd0811=(8,11)\n Rd1215hi=(12,15)\n Rn0002=(0,2)\n Rn0003=(0,3)\n Rd0003hi=(0,3)\n Rn0305=(3,5)\n Rn0810=(8,10)\n Rm0305=(3,5)\n Rm0306=(3,6)\n Rm0608=(6,8)\n Rm0003=(0,3)\n Rs0305=(3,5)\n Rt1215=(12,15)\n Rt0811=(8,11)\n \n thI9=(9,9)\n thP8=(8,8)\n thH8=(8,8)\n thL8=(8,8)\n thU7=(7,7)\n thB6=(6,6)\n thN6=(6,6)\n thS6=(6,6)\n thW5=(5,5)\n thL4=(4,4)\n \n thCRd=(12,15)\n thCRn=(0,3)\n thCRm=(0,3)\n\n hrn0002=(0,2)\n hrm0305=(3,5)\n rm0306=(3,6)\n hrd0002=(0,2)\n\n immed3=(6,8)\n immed5=(6,10)\n immed6=(0,5)\n immed7=(0,6)\n immed8=(0,7)\n \n immed12_i=(10,10)\n immed12_imm3=(12,14)\n immed12_imm8=(0,7)\n\n soffset8=(0,7) signed\n offset10=(0,9)\n offset10S=(10,10)\n offset11=(0,10)\n soffset11=(0,10) signed\n offset12=(0,11)\n\n thcond=(8,11)\n thcpn=(8,11)\n thcop=(8,10)\n thopcode1=(4,7)\n thop1=(4,6)\n thopcode2=(5,7)\n thop2=(7,7)\n thopcode3=(0,5)\n thop3=(4,5)\n l07=(7,7)\n l11=(11,11)\n h1=(7,7)\n h2=(6,6)\n R=(8,8)\n sbz=(0,2)\n thwbit=(5,5)\n \n th_psrmask=(8,11)\n \n addr_pbit=(10,10)\n addr_ubit=(9,9)\n addr_wbit=(8,8)\n addr_puw =(8,10)\n addr_puw1 =(5,8)\n \n thsrsMode=(0,4)\n \n fcond=(4,7)\n \n throt=(4,6)\n \n imm3_12=(12,14)\n \n imm3_shft=(12,14)\n imm2_shft=(6,7)\n \n imm5=(3,7)\n \n sysm=(0,7)\n sysm37=(3,7)\n sysm02=(0,2)\n \n\n thc0001=(0,1)\n thc0002=(0,2)\n thc0003=(0,3)\n thc0004=(0,4)\n thc0005=(0,5)\n thc0006=(0,6)\n thc0007=(0,7)\n thc0011=(0,11)\n thc0107=(1,7)\n thc0207=(2,7)\n thc0307=(3,7)\n thc0407=(4,7)\n thc0405=(4,5)\n thc0409=(4,9)\n thc0506=(5,6)\n thc0507=(5,7)\n thc0607=(6,7)\n thc0810=(8,10)\n thc0811=(8,11)\n thc0910=(9,10)\n thc1414=(14,14)\n thc1313=(13,13)\n thc1212=(12,12)\n thc1214=(12,14)\n thc1111=(11,11)\n thc1010=(10,10)\n thc0909=(9,9)\n thc0808=(8,8)\n thc0707=(7,7)\n thc0606=(6,6)\n thc0505=(5,5)\n thc0404=(4,4)\n thc0303=(3,3)\n thc0202=(2,2)\n thc0101=(1,1)\n thc0000=(0,0)\n thc0115=(1,15)\n thc0215=(2,15)\n thc0315=(3,15)\n thc0415=(4,15)\n thc0515=(5,15)\n thc0615=(6,15)\n thc0715=(7,15)\n thc0815=(8,15)\n thc0915=(9,15)\n thc1015=(10,15)\n thc1112=(11,12)\n thc1115=(11,15)\n thc1215=(12,15)\n thc1315=(13,15)\n thc1415=(14,15)\n thc1515=(15,15)\n\n;\n\nattach variables [ Rd0002 Rd0810 Rn0002 Rn0305 Rn0810 Rm0305 Rm0608 Rs0305 ]\n [ r0 r1 r2 r3 r4 r5 r6 r7 ];\n\nattach variables [ Rm0003 Rm0306 Rd0811 Rn0003 Rt1215 Rt0811 Ra1215 Rd0003 part2Rt part2Rd0003 ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ];\nattach variables [ Rd1215hi Rd0003hi ] [ r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc _ ];\n\nattach variables [ thCRn thCRd thCRm ] [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ]; \t\n\nattach names [ thcpn ] [ p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 ];\nattach names [ thcop ] [ p0 p1 p2 p3 p4 p5 p6 p7 ];\n\nattach variables [ hrn0002 hrm0305 hrd0002 ]\n [ r8 r9 r10 r11 r12 sp lr pc ];\n\nmacro th_addflags(op1,op2) {\n tmpCY = carry(op1,op2);\n tmpOV = scarry(op1,op2);\n}\n\n#See ARM Architecture reference section \"Pseudocode details of addition and subtraction\"\nmacro th_add_with_carry_flags(op1,op2){\n local CYz = zext(CY);\n local result = op1 + op2;\n tmpCY = carry( op1, op2 ) || carry( result, CYz );\n tmpOV = scarry( op1, op2) ^^ scarry( result, CYz );\n}\n\n#Note: used for subtraction op1 - (op2 + !CY)\n#sets tmpCY if there is NO borrow\nmacro th_sub_with_carry_flags(op1, op2){\n local result = op1 - op2;\n tmpCY = (op1 > op2) || (result < zext(CY)); \n tmpOV = sborrow(op1,op2) ^^ sborrow(result,zext(!CY));\t\n}\n\n\nmacro th_test_flags(result){\n ZR = (result == 0);\n NG = (result s< 0);\n CY = shift_carry;\n}\n\n# Note (unlike x86) carry flag is SET if there is NO borrow\nmacro th_subflags(op1,op2) {\n tmpCY = op2 <= op1;\n tmpOV = sborrow(op1,op2);\n}\nmacro th_subflags0(op2) {\n tmpCY = op2 == 0;\n tmpOV = sborrow(0,op2);\n}\n\n\n\nmacro resflags(result) {\n tmpNG = result s< 0;\n tmpZR = result == 0;\n}\n\nmacro th_logicflags() {\n tmpCY = shift_carry;\n tmpOV = OV;\n}\n\nmacro th_affectflags() {\n CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV;\n}\n\nmacro readAPSR_nzcvq(r) {\n# TODO: GE bits have not been included\n\tr = zext( (NG<<4) | (ZR<<3) | (CY<<2) | (OV<<1) | (Q) ) << 27;\n}\n\nmacro writeAPSR_nzcvq(r) {\n# TODO: GE bits have not been included\n local tmp = r >> 27 & 0x1f;\n Q = ((tmp ) & 0x1) != 0;\n OV = ((tmp >> 1) & 0x1) != 0;\n CY = ((tmp >> 2) & 0x1) != 0;\n ZR = ((tmp >> 3) & 0x1) != 0;\n NG = ((tmp >> 4) & 0x1) != 0;\n}\n\nmacro readAPSR_nzcv(r) {\n\tr = zext( (NG<<3) | (ZR<<2) | (CY<<1) | (OV) ) << 28;\n}\n\nmacro writeAPSR_nzcv(r) {\n local tmp = r >> 28 & 0xf;\n OV = ((tmp) & 0x1) != 0;\n CY = ((tmp >> 1) & 0x1) != 0;\n ZR = ((tmp >> 2) & 0x1) != 0;\n NG = ((tmp >> 3) & 0x1) != 0;\n}\n\n###############################################################################\n\n# conditionals for the branch instruction\n\nthcc: \"eq\"\tis thcond=0\t{ tmp:1 = (ZR!=0); export tmp; }\nthcc: \"ne\"\tis thcond=1\t{ tmp:1 = (ZR==0); export tmp; }\nthcc: \"cs\"\tis thcond=2\t{ tmp:1 = (CY!=0); export tmp; }\nthcc: \"cc\"\tis thcond=3\t{ tmp:1 = (CY==0); export tmp; }\nthcc: \"mi\"\tis thcond=4\t{ tmp:1 = (NG!=0); export tmp; }\nthcc: \"pl\"\tis thcond=5\t{ tmp:1 = (NG==0); export tmp; }\nthcc: \"vs\"\tis thcond=6\t{ tmp:1 = (OV!=0); export tmp; }\nthcc: \"vc\"\tis thcond=7\t{ tmp:1 = (OV==0); export tmp; }\nthcc: \"hi\"\tis thcond=8\t{ tmp:1 = CY && !ZR; export tmp; }\nthcc: \"ls\"\tis thcond=9\t{ tmp:1 = !CY || ZR; export tmp; }\nthcc: \"ge\"\tis thcond=10\t{ tmp:1 = (NG == OV); export tmp; }\nthcc: \"lt\"\tis thcond=11\t{ tmp:1 = (NG != OV); export tmp; }\nthcc: \"gt\"\tis thcond=12\t{ tmp:1 = !ZR && (NG == OV); export tmp; }\nthcc: \"le\"\tis thcond=13\t{ tmp:1 = ZR || (NG != OV); export tmp; }\n# thcc: \"AL\"\tis thcond=14\t{ tmp = 1; export tmp; }\n# thcc: \"NV\"\tis thcond=15\t{ tmp = 0; export tmp; }\n\n@define THCC \"thcc & (thc1515=0 | thc1414=0 | thc1313=0)\"\n\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\npart2thcc: \"eq\"\tis part2cond=0\t{ tmp:1 = (ZR!=0); export tmp; }\npart2thcc: \"ne\"\tis part2cond=1\t{ tmp:1 = (ZR==0); export tmp; }\npart2thcc: \"cs\"\tis part2cond=2\t{ tmp:1 = (CY!=0); export tmp; }\npart2thcc: \"cc\"\tis part2cond=3\t{ tmp:1 = (CY==0); export tmp; }\npart2thcc: \"mi\"\tis part2cond=4\t{ tmp:1 = (NG!=0); export tmp; }\npart2thcc: \"pl\"\tis part2cond=5\t{ tmp:1 = (NG==0); export tmp; }\npart2thcc: \"vs\"\tis part2cond=6\t{ tmp:1 = (OV!=0); export tmp; }\npart2thcc: \"vc\"\tis part2cond=7\t{ tmp:1 = (OV==0); export tmp; }\npart2thcc: \"hi\"\tis part2cond=8\t{ tmp:1 = CY && !ZR; export tmp; }\npart2thcc: \"ls\"\tis part2cond=9\t{ tmp:1 = !CY || ZR; export tmp; }\npart2thcc: \"ge\"\tis part2cond=10\t{ tmp:1 = (NG == OV); export tmp; }\npart2thcc: \"lt\"\tis part2cond=11\t{ tmp:1 = (NG != OV); export tmp; }\npart2thcc: \"gt\"\tis part2cond=12\t{ tmp:1 = !ZR && (NG == OV); export tmp; }\npart2thcc: \"le\"\tis part2cond=13\t{ tmp:1 = ZR || (NG != OV); export tmp; }\n# part2thcc: \"AL\"\tis part2cond=14\t{ tmp = 1; export tmp; }\n# part2thcc: \"NV\"\tis part2cond=15\t{ tmp = 0; export tmp; }\n\n@define PART2THCC \"part2thcc & (part2c0909=0 | part2c0808=0 | part2c0707=0)\"\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n# conditionals for IT Block\n# Marvel at the UGLINESS: the p-code for pairs (eq,ne) (cs,cc) (mi,pl), etc. are the same\n# The IT block decoding fills in the complement (if necessary) based on the IT mask bit for the instruction\nit_thfcc: \"eq\"\tis fcond=0\t{ tmp:1 = (ZR!=0); export tmp; }\nit_thfcc: \"ne\"\tis fcond=1\t{ tmp:1 = (ZR!=0); export tmp; }\nit_thfcc: \"cs\"\tis fcond=2\t{ tmp:1 = (CY!=0); export tmp; }\nit_thfcc: \"cc\"\tis fcond=3\t{ tmp:1 = (CY!=0); export tmp; }\nit_thfcc: \"mi\"\tis fcond=4\t{ tmp:1 = (NG!=0); export tmp; }\nit_thfcc: \"pl\"\tis fcond=5\t{ tmp:1 = (NG!=0); export tmp; }\nit_thfcc: \"vs\"\tis fcond=6\t{ tmp:1 = (OV!=0); export tmp; }\nit_thfcc: \"vc\"\tis fcond=7\t{ tmp:1 = (OV!=0); export tmp; }\nit_thfcc: \"hi\"\tis fcond=8\t{ tmp:1 = CY && !ZR; export tmp; }\nit_thfcc: \"ls\"\tis fcond=9\t{ tmp:1 = CY && !ZR; export tmp; }\nit_thfcc: \"ge\"\tis fcond=10\t{ tmp:1 = (NG == OV); export tmp; }\nit_thfcc: \"lt\"\tis fcond=11\t{ tmp:1 = (NG == OV); export tmp; }\nit_thfcc: \"gt\"\tis fcond=12\t{ tmp:1 = !ZR && (NG == OV); export tmp; }\nit_thfcc: \"le\"\tis fcond=13\t{ tmp:1 = !ZR && (NG == OV); export tmp; }\nit_thfcc: \"al\"\tis fcond=14\t{ tmp:1 = 1; export tmp; }\n\n@define IT_THFCC \"it_thfcc & (thc0707=0 | thc0606=0 | thc0505=0 | thc0404=0)\"\n\nByteRotate: \"#\"^rot\t\tis throt [rot = throt << 3; ] { export *[const]:1 rot; }\n\nthSBIT_CZNO: is thc0404=0\t { } # Do nothing to the flag bits\nthSBIT_CZNO: \"s\" is thc0404=1\t { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }\nthSBIT_CZN: is thc0404=0 { } # Do nothing to the flags bits\nthSBIT_CZN: \"s\" is thc0404=1 {CY = tmpCY; ZR = tmpZR; NG = tmpNG;}\nthSBIT_ZN: is thc0404=0\t { } # Do nothing to the flag bits\nthSBIT_ZN: \"s\" is thc0404=1\t { ZR = tmpZR; NG = tmpNG; }\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n\n# Addressing modes\n# The capitalized fields are raw register addressing modes\n\nHrd0002: Rd0002\t\tis Rd0002 & h1=0\t{ export Rd0002; }\nHrd0002: hrd0002\tis hrd0002 & h1=1\t{ export hrd0002; }\nHrd0002: pc\t\tis pc & hrd0002=7 & h1=1 { tmp:4 = inst_start + 4; export tmp; }\n\nHrn0002: Rn0002\t\tis Rn0002 & h1=0\t{ export Rn0002; }\nHrn0002: hrn0002\tis hrn0002 & h1=1\t{ export hrn0002; }\nHrn0002: pc\t\tis pc & hrn0002=7 & h1=1 { tmp:4 = inst_start + 4; export tmp; }\n\nHrm0305: Rm0305\t\tis Rm0305 & h2=0\t{ export Rm0305; }\nHrm0305: hrm0305\tis hrm0305 & h2=1\t{ export hrm0305; }\nHrm0305: pc\t\tis pc & hrm0305=7 & h2=1 { tmp:4 = inst_start + 4; export tmp; }\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\nImmed8_4: \"#\"^immval\t\tis immed8 [ immval = immed8 * 4; ]\t\t{ export *[const]:4 immval; }\nImmed4: \"#\"^thc0003\tis thc0003\t\t{ export *[const]:4 thc0003; }\n@endif\n\nImmed8: \"#\"^immed8\t\tis immed8\t\t{ export *[const]:4 immed8; }\nImmed3: \"#\"^immed3\t\tis immed3\t\t{ export *[const]:4 immed3; }\n\nPcrel8: [reloc]\t\tis immed8\n [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ]\n{\n # don't export as an address, may be PIC code, and would add spurious symbols.\n export *[const]:4 reloc;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nPcrel8_s8: [reloc]\t\tis immed8\n [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ]\n{\n export *:8 reloc;\n}\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n\nSprel8:\tsp,\"#\"^immval\tis sp & immed8\t[ immval = immed8 * 4; ]\t{ local tmp = sp + immval; export tmp; }\nImmed7_4: \"#\"^immval\tis immed7\t\t[ immval = immed7 * 4; ] { tmp:4 = immval; export tmp; }\nImmed5: \"#\"^immed5\t\tis immed5\t\t{ export *[const]:4 immed5; }\n\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nImmed12: \"#\"^immed12 is immed12_i; immed12_imm3 & immed12_imm8\n [ immed12=(immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8); ]\n{\n export *[const]:4 immed12;\n}\n\nImmed16: \"#\"^immed16 is immed12_i & sop0003; immed12_imm3 & immed12_imm8\n [ immed16 = (sop0003 << 12) | (immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8); ]\n{\n export *[const]:2 immed16;\n}\n\nPcrelImmed12Addr: reloc\t\tis immed12_i; immed12_imm3 & immed12_imm8\n [ reloc = ((inst_start+4) $and 0xfffffffc) + ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ]\n{\n # don't export as an address, may be PIC code, and would add spurious symbols.\n export *[const]:4 reloc;\n}\n\nNegPcrelImmed12Addr: reloc\tis immed12_i; immed12_imm3 & immed12_imm8\n [ reloc = ((inst_start+4) $and 0xfffffffc) - ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ]\n{\n # don't export as an address, may be PIC code, and would add spurious symbols.\n export *[const]:4 reloc;\n}\n\nPcrelOffset12: [reloc]\t\tis thc0707=1; offset12\n [ reloc = ((inst_start+4) $and 0xfffffffc) + offset12; ]\n{\n export *:4 reloc;\n}\nPcrelOffset12: [reloc]\t\tis thc0707=0; offset12\n [ reloc = ((inst_start+4) $and 0xfffffffc) - offset12; ]\n{\n export *:4 reloc;\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n\n# decode thumb immediate12 encoded value\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nThumbExpandImm12: \"#\"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=0 & immed12_imm8\n [ imm32=immed12_imm8 $and 0xff; ]\n{\n tmp:4 = imm32; shift_carry = CY; export tmp;\n}\nThumbExpandImm12: \"#\"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=1 & immed12_imm8\n [ imm32=(immed12_imm8<<16) | (immed12_imm8); ]\n{\n tmp:4 = imm32; shift_carry = CY; export tmp;\n}\nThumbExpandImm12: \"#\"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=2 & immed12_imm8\n [ imm32=(immed12_imm8<<24) | (immed12_imm8<<8); ]\n{\n tmp:4 = imm32; shift_carry = CY; export tmp;\n}\nThumbExpandImm12: \"#\"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=3 & immed12_imm8\n [ imm32=(immed12_imm8<<24) | (immed12_imm8<<16) | (immed12_imm8<<8) | (immed12_imm8); ]\n{\n tmp:4 = imm32; shift_carry = CY; export tmp;\n}\nThumbExpandImm12: \"#\"^imm32 is immed12_i=0 ; immed12_imm3 & thc0707 & immed7\n [ imm32=(((0x80+immed7)<<(32-((immed12_imm3<<1)|thc0707)))|((0x80+immed7)>>(((immed12_imm3<<1)|thc0707)))) $and 0xffffffff; ]\n{\n tmp:4 = imm32; local tmp1 = (tmp >> 31); shift_carry = tmp1(0); export tmp;\n}\nThumbExpandImm12: \"#\"^imm32 is immed12_i=1 ; immed12_imm3 & thc0707 & immed7\n [ imm32=(((0x80+immed7)<<(32-(16+((immed12_imm3<<1)|thc0707))))|((0x80+immed7)>>((16+((immed12_imm3<<1)|thc0707))))) $and 0xffffffff; ]\n{\n tmp:4 = imm32; local tmp1 = (tmp >> 31); shift_carry = tmp1(0); export tmp;\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nthLsbImm: \"#\"^lsb\tis imm3_shft & imm2_shft [ lsb= (imm3_shft<<2) | imm2_shft; ] { tmp:4 = lsb; export tmp; }\nthMsbImm: \"#\"^thc0004\tis thc0004 { tmp:4 = thc0004; export tmp; }\nthWidthMinus1: \"#\"^width\tis thc0004 [ width = thc0004 + 1; ] { tmp:4 = thc0004; export tmp; }\nthBitWidth: \"#\"^w\tis imm3_shft & imm2_shft & thc0004\t[ w = thc0004 - ((imm3_shft<<2) | imm2_shft) + 1; ] { tmp:4 = w; export tmp; }\n\n@endif # VERSION_6T2 || VERSION_7\n\n\n#####################\n###### thshift2 ######\n#####################\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nthshift2: Rm0003 \t \t\tis imm3_shft=0 & imm2_shft=0 & thc0405=0 & Rm0003\n{\n shift_carry = CY; export Rm0003;\n}\n\nthshift2: Rm0003, \"lsl #\"^shftval \tis imm3_shft & imm2_shft & thc0405=0 & Rm0003\n [ shftval=(imm3_shft<<2) | (imm2_shft); ]\n{\n local tmp1=(Rm0003>>(32-shftval))&1; shift_carry=tmp1(0); local tmp2=Rm0003<>31); shift_carry=tmp1(0); tmp2:4=0; export tmp2;\n}\n\nthshift2: Rm0003, \"lsr #\"^shftval\tis imm3_shft & imm2_shft & thc0405=1 & Rm0003\n [ shftval=(imm3_shft<<2) | (imm2_shft); ]\n{\n local tmp1=(Rm0003>>(shftval-1))&1; shift_carry=tmp1(0); local tmp2=Rm0003>>shftval; export tmp2;\n}\n\nthshift2: Rm0003, \"asr #32\"\t\tis imm3_shft=0 & imm2_shft=0 & thc0405=2 & Rm0003\n{\n local tmp1=(Rm0003>>31); shift_carry=tmp1(0); local tmp2 = Rm0003 s>> 32; export tmp2;\n}\n\nthshift2: Rm0003, \"asr #\"^shftval\tis imm3_shft & imm2_shft & thc0405=2 & Rm0003\n [ shftval=(imm3_shft<<2) | (imm2_shft); ]\n{\n local tmp1=(Rm0003>>(shftval-1))&1; shift_carry=tmp1(0); local tmp2=Rm0003 s>> shftval; export tmp2;\n}\n\nthshift2: Rm0003, \"rrx\"\t\tis imm3_shft=0 & imm2_shft=0 & thc0405=3 & Rm0003\n{\n local tmp1=Rm0003&1; shift_carry=tmp1(0); local tmp2 = (zext(CY)<<31)|(Rm0003>>1); export tmp2;\n}\n\nthshift2: Rm0003, \"ror #\"^shftval\tis imm3_shft & imm2_shft & thc0405=3 & Rm0003\n [ shftval=(imm3_shft<<2) | (imm2_shft); ]\n{\n local tmp1=(Rm0003>>shftval)|(Rm0003<<(32-shftval)); local tmp2=tmp1 >> 31; shift_carry=tmp2(0); export tmp1;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\nAddr5: reloc is imm5 & thc0909\n [ reloc = inst_start + 4 + ((thc0909 << 6) | (imm5 << 1)); ]\n{\n export *:4 reloc;\n}\n\nAddr8:\treloc\tis soffset8\n [ reloc = (inst_start+4) + 2*soffset8; ]\n{\n export *:4 reloc;\n}\n\nAddr11:\treloc\tis soffset11\n [ reloc = (inst_start+4) + 2*soffset11; ]\n{\n export *:4 reloc;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nThAddr20:\treloc\tis part2S=1 & part2imm6; part2J1 & part2J2 & part2imm11\n [ reloc = inst_start + 4 + ((-1 << 20) $or (part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ]\n{\n export *:4 reloc;\n}\n\nThAddr20:\treloc\tis part2S=0 & part2imm6; part2J1 & part2J2 & part2imm11\n [ reloc = inst_start + 4 + ((part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ]\n{\n export *:4 reloc;\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\nThAddr24:\treloc\tis offset10S=0 & offset10; part2J1 & part2J2 & part2off\n [ reloc = inst_start + 4 + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off << 1)); ]\n{\n export *:4 reloc;\n}\n\nThAddr24:\treloc\tis offset10S=1 & offset10; part2J1 & part2J2 & part2off\n [ reloc = inst_start + 4 + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off << 1)); ]\n{\n export *:4 reloc;\n}\n\n@if defined(VERSION_5)\n\nThArmAddr23:\treloc\tis offset10S=0 & offset10; part2J1 & part2J2 & part2off_10\n [ reloc = ((inst_start + 4) $and 0xfffffffc) + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ]\n{\n export *:4 reloc;\n}\n\nThArmAddr23:\treloc\tis offset10S=1 & offset10; part2J1 & part2J2 & part2off_10\n [ reloc = ((inst_start + 4) $and 0xfffffffc) + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ]\n{\n export *:4 reloc;\n}\n\n@endif # VERSION_5\n\n\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=0 & thc0000=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=1 & thc0101=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=2 & thc0202=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=3 & thc0303=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=4 & thc0404=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=5 & thc0505=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=6 & thc0606=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810\tis Rn0810 & thc0810=7 & thc0707=1\t\t\t{ mult_addr = Rn0810; export Rn0810; }\nRn_exclaim: Rn0810!\tis Rn0810 & thc0810\t\t\t\t\t\t\t{ mult_addr = Rn0810; export Rn0810; }\n\nRn_exclaim_WB: \tis Rn0810 & thc0810=0 & thc0000=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=1 & thc0101=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=2 & thc0202=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=3 & thc0303=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=4 & thc0404=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=5 & thc0505=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=6 & thc0606=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810=7 & thc0707=1\t\t\t{ }\nRn_exclaim_WB: \tis Rn0810 & thc0810\t\t\t\t\t\t\t{ Rn0810 = mult_addr; }\n\n# ldlist is the list of registers to be loaded or popped\nLdRtype0: r0\t\t\t\tis thc0000=1 & r0 & thc0107=0\t{ r0 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype0: r0,\t\t\t\tis thc0000=1 & r0 \t\t\t\t{ r0 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype0: \t\t\t\t\tis thc0000=0\t\t\t\t{ }\nLdRtype1: LdRtype0^r1\t\tis LdRtype0 & thc0101=1 & r1 & thc0207=0\t{ r1 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype1: LdRtype0^r1,\t\tis LdRtype0 & thc0101=1 & r1\t\t\t\t{ r1 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype1: LdRtype0\t\t\tis LdRtype0 & thc0101=0\t\t\t\t{ }\nLdRtype2: LdRtype1^r2\t\tis LdRtype1 & thc0202=1 & r2 & thc0307=0\t{ r2 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype2: LdRtype1^r2,\t\tis LdRtype1 & thc0202=1 & r2\t\t\t\t{ r2 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype2: LdRtype1\t\t\tis LdRtype1 & thc0202=0\t\t\t\t{ }\nLdRtype3: LdRtype2^r3\t\tis LdRtype2 & thc0303=1 & r3 & thc0407=0\t{ r3 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype3: LdRtype2^r3,\t\tis LdRtype2 & thc0303=1 & r3\t\t\t\t{ r3 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype3: LdRtype2\t\t\tis LdRtype2 & thc0303=0\t\t\t\t{ }\nLdRtype4: LdRtype3^r4\t\tis LdRtype3 & thc0404=1 & r4 & thc0507=0\t{ r4 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype4: LdRtype3^r4,\t\tis LdRtype3 & thc0404=1 & r4\t\t\t\t{ r4 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype4: LdRtype3\t\t\tis LdRtype3 & thc0404=0\t\t\t\t{ }\nLdRtype5: LdRtype4^r5\t\tis LdRtype4 & thc0505=1 & r5 & thc0607=0\t{ r5 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype5: LdRtype4^r5,\t\tis LdRtype4 & thc0505=1 & r5\t\t\t\t{ r5 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype5: LdRtype4\t\t\tis LdRtype4 & thc0505=0\t\t\t\t{ }\nLdRtype6: LdRtype5^r6\t\tis LdRtype5 & thc0606=1 & r6 & thc0707=0\t{ r6 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype6: LdRtype5^r6,\t\tis LdRtype5 & thc0606=1 & r6\t\t\t\t{ r6 = *mult_addr; mult_addr = mult_addr + 4; }\nLdRtype6: LdRtype5\t\t\tis LdRtype5 & thc0606=0\t\t\t\t{ }\nldlist: LdRtype6^r7\t\tis LdRtype6 & thc0707=1 & r7\t\t\t\t{ r7 = *mult_addr; mult_addr = mult_addr + 4; }\nldlist: LdRtype6\t\t\tis LdRtype6 & thc0707=0\t\t\t\t{ }\n\n#strlist is the list of registers to be stored\nStrType0: r0\t\t\t\tis thc0000=1 & r0 & thc0107=0\t\t\t\t{ *mult_addr = r0; mult_addr = mult_addr + 4; }\nStrType0: r0,\t\t\t\tis thc0000=1 & r0\t\t\t\t\t\t\t{ *mult_addr = r0; mult_addr = mult_addr + 4; }\nStrType0:\t\t\t\t\tis thc0000=0\t\t\t\t\t\t{ }\nStrType1: StrType0^r1\t\tis StrType0 & thc0101=1 & r1 & thc0207=0\t{ *mult_addr = r1; mult_addr = mult_addr + 4; }\nStrType1: StrType0^r1,\t\tis StrType0 & thc0101=1 & r1\t\t\t\t{ *mult_addr = r1; mult_addr = mult_addr + 4; }\nStrType1: StrType0\t\t\tis StrType0 & thc0101=0\t\t\t\t{ }\nStrType2: StrType1^r2\t\tis StrType1 & thc0202=1 & r2 & thc0307=0\t{ *mult_addr = r2; mult_addr = mult_addr + 4; }\nStrType2: StrType1^r2,\t\tis StrType1 & thc0202=1 & r2\t\t\t\t{ *mult_addr = r2; mult_addr = mult_addr + 4; }\nStrType2: StrType1\t\t\tis StrType1 & thc0202=0\t\t\t\t{ }\nStrType3: StrType2^r3\t\tis StrType2 & thc0303=1 & r3 & thc0407=0\t{ *mult_addr = r3; mult_addr = mult_addr + 4; }\nStrType3: StrType2^r3,\t\tis StrType2 & thc0303=1 & r3\t\t\t\t{ *mult_addr = r3; mult_addr = mult_addr + 4; }\nStrType3: StrType2\t\t\tis StrType2 & thc0303=0\t\t\t\t{ }\nStrType4: StrType3^r4\t\tis StrType3 & thc0404=1 & r4 & thc0507=0\t{ *mult_addr = r4; mult_addr = mult_addr + 4; }\nStrType4: StrType3^r4,\t\tis StrType3 & thc0404=1 & r4\t\t\t\t{ *mult_addr = r4; mult_addr = mult_addr + 4; }\nStrType4: StrType3\t\t\tis StrType3 & thc0404=0\t\t\t\t{ }\nStrType5: StrType4^r5\t\tis StrType4 & thc0505=1 & r5 & thc0607=0\t{ *mult_addr = r5; mult_addr = mult_addr + 4; }\nStrType5: StrType4^r5,\t\tis StrType4 & thc0505=1 & r5\t\t\t\t{ *mult_addr = r5; mult_addr = mult_addr + 4; }\nStrType5: StrType4\t\t\tis StrType4 & thc0505=0\t\t\t\t{ }\nStrType6: StrType5^r6\t\tis StrType5 & thc0606=1 & r6 & thc0707=0\t{ *mult_addr = r6; mult_addr = mult_addr + 4; }\nStrType6: StrType5^r6,\t\tis StrType5 & thc0606=1 & r6\t\t\t\t{ *mult_addr = r6; mult_addr = mult_addr + 4; }\nStrType6: StrType5\t\t\tis StrType5 & thc0606=0\t\t\t\t{ }\nStrType7: StrType6^r7\t\tis StrType6 & thc0707=1 & r7\t\t\t\t{ *mult_addr = r7; mult_addr = mult_addr + 4; }\nStrType7: StrType6\t\t\tis StrType6 & thc0707=0\t\t\t{ }\nstrlist: StrType7\t\t\tis StrType7\t\t\t\t\t\t{ }\n\n# pshlist is the list registers to be pushed to memory\n# SCR 10921, fix the order in which the regs appear in the disassembled insn, to be in line with objdump\n# Also add commas between regs\n#\nPshType7: \"\"\t\t\t\tis thc0707=0\t\t\t\t\t\t{ }\nPshType7: r7\t\t\t\tis thc0707=1 & r7\t\t\t\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r7; }\nPshType6: PshType7\t\t\tis PshType7 & thc0606=0\t\t\t\t{ }\nPshType6: r6\t\t\t\tis thc0606=1 & r6 & thc0707=0\t{ mult_addr = mult_addr - 4; *mult_addr = r6; }\nPshType6: r6,PshType7\t\tis PshType7 & thc0606=1 & r6\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r6; }\nPshType5: PshType6\t\t\tis PshType6 & thc0505=0\t\t\t\t{ }\nPshType5: r5\t\t\t\tis thc0505=1 & r5 & thc0607=0\t{ mult_addr = mult_addr - 4; *mult_addr = r5; }\nPshType5: r5,PshType6\t\tis PshType6 & thc0505=1 & r5\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r5; }\nPshType4: PshType5\t\t\tis PshType5 & thc0404=0\t\t\t\t{ }\nPshType4: r4\t\t\t\tis thc0404=1 & r4 & thc0507=0\t{ mult_addr = mult_addr - 4; *mult_addr = r4; }\nPshType4: r4,PshType5\t\tis PshType5 & thc0404=1 & r4\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r4; }\nPshType3: PshType4\t\t\tis PshType4 & thc0303=0\t\t\t\t{ }\nPshType3: r3\t\t\t\tis thc0303=1 & r3 & thc0407=0\t{ mult_addr = mult_addr - 4; *mult_addr = r3; }\nPshType3: r3,PshType4\t\tis PshType4 & thc0303=1 & r3\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r3; }\nPshType2: PshType3\t\t\tis PshType3 & thc0202=0\t\t\t\t{ }\nPshType2: r2\t\t\t\tis thc0202=1 & r2 & thc0307=0\t{ mult_addr = mult_addr - 4; *mult_addr = r2; }\nPshType2: r2,PshType3\t\tis PshType3 & thc0202=1 & r2\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r2; }\nPshType1: PshType2\t\t\tis PshType2 & thc0101=0\t\t\t\t{ }\nPshType1: r1\t\t\t\tis thc0101=1 & r1 & thc0207=0\t{ mult_addr = mult_addr - 4; *mult_addr = r1; }\nPshType1: r1,PshType2\t\tis PshType2 & thc0101=1 & r1\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r1; }\npshlist: PshType1\t\t\tis PshType1 & thc0000=0\t\t\t\t{ }\npshlist: r0\t\t\t\tis thc0000=1 & r0 & thc0107=0\t{ mult_addr = mult_addr - 4; *mult_addr = r0; }\npshlist: r0,PshType1\t\tis PshType1 & thc0000=1 & r0\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = r0; }\n\n# ldlist_inc is the list of registers to be loaded for pop instructions\nthrlist15: r0\t\t\t\tis thc0000=1 & r0 & thc0115=0\t\t\t\t{ r0 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist15: r0,\t\t\t\tis thc0000=1 & r0\t\t\t\t\t\t\t{ r0 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist15:\t\t\t\t\tis thc0000=0\t\t\t\t\t\t\t\t{ }\nthrlist14: thrlist15^r1\t\tis thc0101=1 & thrlist15 & r1 & thc0215=0\t{ r1 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist14: thrlist15^r1,\tis thc0101=1 & thrlist15 & r1\t\t\t\t{ r1 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist14: thrlist15\t\tis thc0101=0 & thrlist15\t\t\t\t\t{ }\nthrlist13: thrlist14^r2\t\tis thc0202=1 & thrlist14 & r2 & thc0315=0\t{ r2 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist13: thrlist14^r2,\tis thc0202=1 & thrlist14 & r2\t\t\t\t{ r2 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist13: thrlist14\t\tis thc0202=0 & thrlist14\t\t\t\t\t{ }\nthrlist12: thrlist13^r3\t\tis thc0303=1 & thrlist13 & r3 & thc0415=0\t{ r3 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist12: thrlist13^r3,\tis thc0303=1 & thrlist13 & r3\t\t\t\t{ r3 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist12: thrlist13\t\tis thc0303=0 & thrlist13\t\t\t\t\t{ }\nthrlist11: thrlist12^r4\t\tis thc0404=1 & thrlist12 & r4 & thc0515=0\t{ r4 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist11: thrlist12^r4,\tis thc0404=1 & thrlist12 & r4\t\t\t\t{ r4 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist11: thrlist12\t\tis thc0404=0 & thrlist12\t\t\t\t\t{ }\nthrlist10: thrlist11^r5\t\tis thc0505=1 & thrlist11 & r5 & thc0615=0\t{ r5 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist10: thrlist11^r5,\tis thc0505=1 & thrlist11 & r5\t\t\t\t{ r5 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist10: thrlist11\t\tis thc0505=0 & thrlist11\t\t\t\t\t{ }\nthrlist9: thrlist10^r6\t\tis thc0606=1 & thrlist10 & r6 & thc0715=0\t{ r6 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist9: thrlist10^r6,\t\tis thc0606=1 & thrlist10 & r6\t\t\t\t{ r6 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist9: thrlist10\t\t\tis thc0606=0 & thrlist10\t\t\t\t\t{ }\nthrlist8: thrlist9^r7\t\tis thc0707=1 & thrlist9 & r7 & thc0815=0\t{ r7 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist8: thrlist9^r7,\t\tis thc0707=1 & thrlist9 & r7\t\t\t\t{ r7 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist8: thrlist9\t\t\tis thc0707=0 & thrlist9\t\t\t\t\t\t{ }\nthrlist7: thrlist8^r8\t\tis thc0808=1 & thrlist8 & r8 & thc0915=0\t{ r8 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist7: thrlist8^r8,\t\tis thc0808=1 & thrlist8 & r8\t\t\t\t{ r8 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist7: thrlist8\t\t\tis thc0808=0 & thrlist8\t\t\t\t\t\t{ }\nthrlist6: thrlist7^r9\t\tis thc0909=1 & thrlist7 & r9 & thc1015=0\t{ r9 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist6: thrlist7^r9,\t\tis thc0909=1 & thrlist7 & r9\t\t\t\t{ r9 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist6: thrlist7\t\t\tis thc0909=0 & thrlist7\t\t\t\t\t\t{ }\nthrlist5: thrlist6^r10\t\tis thc1010=1 & thrlist6 & r10 & thc1115=0\t{ r10 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist5: thrlist6^r10,\t\tis thc1010=1 & thrlist6 & r10\t\t\t\t{ r10 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist5: thrlist6\t\t\tis thc1010=0 & thrlist6\t\t\t\t\t\t{ }\nthrlist4: thrlist5^r11\t\tis thc1111=1 & thrlist5 & r11 & thc1215=0\t{ r11 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist4: thrlist5^r11,\t\tis thc1111=1 & thrlist5 & r11\t\t\t\t{ r11 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist4: thrlist5\t\t\tis thc1111=0 & thrlist5\t\t\t\t\t\t{ }\nthrlist3: thrlist4^r12\t\tis thc1212=1 & thrlist4 & r12 & thc1315=0\t{ r12 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist3: thrlist4^r12,\t\tis thc1212=1 & thrlist4 & r12\t\t\t\t{ r12 = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist3: thrlist4\t\t\tis thc1212=0 & thrlist4\t\t\t\t\t\t{ }\nthrlist2: thrlist3^sp\t\tis thc1313=1 & thrlist3 & sp & thc1415=0\t{ sp = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist2: thrlist3^sp,\t\tis thc1313=1 & thrlist3 & sp\t\t\t\t{ sp = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist2: thrlist3\t\t\tis thc1313=0 & thrlist3\t\t\t\t\t\t{ }\nthrlist1: thrlist2^lr\t\tis thc1414=1 & thrlist2 & lr & thc1515=0\t{ lr = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist1: thrlist2^lr,\t\tis thc1414=1 & thrlist2 & lr\t\t\t\t{ lr = * mult_addr; mult_addr = mult_addr + 4; }\nthrlist1: thrlist2\t\t\tis thc1414=0 & thrlist2\t\t\t\t\t\t{ }\nthldrlist_inc: {thrlist1^pc}\tis thc1515=1 & thrlist1 & pc\t\t\t{ pc = * mult_addr; mult_addr = mult_addr + 4; }\nthldrlist_inc: {thrlist1}\t\tis thc1515=0 & thrlist1\t\t\t\t\t{ }\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n# thstrlist_inc is the list of registers to be stored using IA or IB in Addressing Mode 4\nthsinc15: r0\t\t\t\t\tis thc0000=1 & r0 & thc0115=0\t\t\t\t\t{ * mult_addr = r0; mult_addr = mult_addr + 4; }\nthsinc15: r0,\t\t\t\t\tis thc0000=1 & r0\t\t\t\t\t\t\t\t{ * mult_addr = r0; mult_addr = mult_addr + 4; }\nthsinc15: \t\t\t\t\t\tis thc0000=0\t\t\t\t\t\t{ }\nthsinc14: thsinc15^r1\t\t\tis thc0101=1 & thsinc15 & r1 & thc0215=0\t{ * mult_addr = r1; mult_addr = mult_addr + 4; }\nthsinc14: thsinc15^r1,\t\t\tis thc0101=1 & thsinc15 & r1\t\t\t\t{ * mult_addr = r1; mult_addr = mult_addr + 4; }\nthsinc14: thsinc15\t\t\t\tis thc0101=0 & thsinc15\t\t\t\t{ }\nthsinc13: thsinc14^r2\t\t\tis thc0202=1 & thsinc14 & r2 & thc0315=0\t{ * mult_addr = r2; mult_addr = mult_addr + 4; }\nthsinc13: thsinc14^r2,\t\t\tis thc0202=1 & thsinc14 & r2\t\t\t\t{ * mult_addr = r2; mult_addr = mult_addr + 4; }\nthsinc13: thsinc14\t\t\t\tis thc0202=0 & thsinc14\t\t\t\t{ }\nthsinc12: thsinc13^r3\t\t\tis thc0303=1 & thsinc13 & r3 & thc0415=0\t{ * mult_addr = r3; mult_addr = mult_addr + 4; }\nthsinc12: thsinc13^r3,\t\t\tis thc0303=1 & thsinc13 & r3\t\t\t\t{ * mult_addr = r3; mult_addr = mult_addr + 4; }\nthsinc12: thsinc13\t\t\t\tis thc0303=0 & thsinc13\t\t\t\t{ }\nthsinc11: thsinc12^r4\t\t\tis thc0404=1 & thsinc12 & r4 & thc0515=0\t{ * mult_addr = r4; mult_addr = mult_addr + 4; }\nthsinc11: thsinc12^r4,\t\t\tis thc0404=1 & thsinc12 & r4\t\t\t\t{ * mult_addr = r4; mult_addr = mult_addr + 4; }\nthsinc11: thsinc12\t\t\t\tis thc0404=0 & thsinc12\t\t\t\t{ }\nthsinc10: thsinc11^r5\t\t\tis thc0505=1 & thsinc11 & r5 & thc0615=0\t{ * mult_addr = r5; mult_addr = mult_addr + 4; }\nthsinc10: thsinc11^r5,\t\t\tis thc0505=1 & thsinc11 & r5\t\t\t\t{ * mult_addr = r5; mult_addr = mult_addr + 4; }\nthsinc10: thsinc11\t\t\t\tis thc0505=0 & thsinc11\t\t\t\t{ }\nthsinc9: thsinc10^r6\t\t\tis thc0606=1 & thsinc10 & r6 & thc0715=0\t{ * mult_addr = r6; mult_addr = mult_addr + 4; }\nthsinc9: thsinc10^r6,\t\t\tis thc0606=1 & thsinc10 & r6\t\t\t\t{ * mult_addr = r6; mult_addr = mult_addr + 4; }\nthsinc9: thsinc10\t\t\t\tis thc0606=0 & thsinc10\t\t\t\t{ }\nthsinc8: thsinc9^r7\t\t\t\tis thc0707=1 & thsinc9 & r7 & thc0815=0\t\t{ * mult_addr = r7; mult_addr = mult_addr + 4; }\nthsinc8: thsinc9^r7,\t\t\tis thc0707=1 & thsinc9 & r7\t\t\t\t\t{ * mult_addr = r7; mult_addr = mult_addr + 4; }\nthsinc8: thsinc9\t\t\t\tis thc0707=0 & thsinc9\t\t\t\t{ }\nthsinc7: thsinc8^r8\t\t\t\tis thc0808=1 & thsinc8 & r8 & thc0915=0\t\t{ * mult_addr = r8; mult_addr = mult_addr + 4; }\nthsinc7: thsinc8^r8,\t\t\tis thc0808=1 & thsinc8 & r8\t\t\t\t\t{ * mult_addr = r8; mult_addr = mult_addr + 4; }\nthsinc7: thsinc8\t\t\t\tis thc0808=0 & thsinc8\t\t\t\t{ }\nthsinc6: thsinc7^r9\t\t\t\tis thc0909=1 & thsinc7 & r9 & thc1015=0\t\t{ * mult_addr = r9; mult_addr = mult_addr + 4; }\nthsinc6: thsinc7^r9,\t\t\tis thc0909=1 & thsinc7 & r9\t\t\t\t\t{ * mult_addr = r9; mult_addr = mult_addr + 4; }\nthsinc6: thsinc7\t\t\t\tis thc0909=0 & thsinc7\t\t\t\t{ }\nthsinc5: thsinc6^r10\t\t\tis thc1010=1 & thsinc6 & r10 & thc1115=0\t{ * mult_addr = r10; mult_addr = mult_addr + 4; }\nthsinc5: thsinc6^r10,\t\t\tis thc1010=1 & thsinc6 & r10\t\t\t\t{ * mult_addr = r10; mult_addr = mult_addr + 4; }\nthsinc5: thsinc6\t\t\t\tis thc1010=0 & thsinc6\t\t\t\t{ }\nthsinc4: thsinc5^r11\t\t\tis thc1111=1 & thsinc5 & r11 & thc1215=0\t{ * mult_addr = r11; mult_addr = mult_addr + 4; }\nthsinc4: thsinc5^r11,\t\t\tis thc1111=1 & thsinc5 & r11\t\t\t\t{ * mult_addr = r11; mult_addr = mult_addr + 4; }\nthsinc4: thsinc5\t\t\t\tis thc1111=0 & thsinc5\t\t\t\t{ }\nthsinc3: thsinc4^r12\t\t\tis thc1212=1 & thsinc4 & r12 & thc1315=0\t{ * mult_addr = r12; mult_addr = mult_addr + 4; }\nthsinc3: thsinc4^r12,\t\t\tis thc1212=1 & thsinc4 & r12\t\t\t\t{ * mult_addr = r12; mult_addr = mult_addr + 4; }\nthsinc3: thsinc4\t\t\t\tis thc1212=0 & thsinc4\t\t\t\t{ }\nthsinc2: thsinc3^sp\t\t\t\tis thc1313=1 & thsinc3 & sp & thc1415=0\t\t{ * mult_addr = sp; mult_addr = mult_addr + 4; }\nthsinc2: thsinc3^sp,\t\t\tis thc1313=1 & thsinc3 & sp\t\t\t\t\t{ * mult_addr = sp; mult_addr = mult_addr + 4; }\nthsinc2: thsinc3\t\t\t\tis thc1313=0 & thsinc3\t\t\t\t{ }\nthsinc1: thsinc2^lr\t\t\t\tis thc1414=1 & thsinc2 & lr & thc1515=0\t\t{ * mult_addr = lr; mult_addr = mult_addr + 4; }\nthsinc1: thsinc2^lr,\t\t\tis thc1414=1 & thsinc2 & lr\t\t\t\t\t{ * mult_addr = lr; mult_addr = mult_addr + 4; }\nthsinc1: thsinc2\t\t\t\tis thc1414=0 & thsinc2\t\t\t\t{ }\nthstrlist_inc: {thsinc1^pc}\t\tis thc1515=1 & thsinc1 & pc\t\t\t\t\t{ *:4 mult_addr = inst_start+4; mult_addr = mult_addr + 4; }\nthstrlist_inc: {thsinc1}\t\tis thc1515=0 & thsinc1\t\t\t\t{ }\n\n# thldrlist_dec is the list of registers to be loaded using DA or DB in Addressing Mode 4\nthrldec15: pc\t\t\t\t\t\tis thc1515=1 & pc\t\t\t\t\t\t\t{ pc = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec15:\t\t\t\t\t\t\tis thc1515=0\t\t\t\t\t\t{ }\nthrldec14: lr^thrldec15\t\t\t\tis thc1414=1 & thrldec15 & lr & thc1515=0\t{ lr = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec14: lr,thrldec15\t\t\t\tis thc1414=1 & thrldec15 & lr\t\t\t\t{ lr = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec14: thrldec15\t\t\t\tis thc1414=0 & thrldec15\t\t\t{ }\nthrldec13: sp^thrldec14\t\t\t\tis thc1313=1 & thrldec14 & sp & thc1415=0\t{ sp = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec13: sp,thrldec14\t\t\t\tis thc1313=1 & thrldec14 & sp\t\t\t\t{ sp = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec13: thrldec14\t\t\t\tis thc1313=0 & thrldec14\t\t\t{ }\nthrldec12: r12^thrldec13\t\t\tis thc1212=1 & thrldec13 & r12 & thc1315=0\t{ r12 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec12: r12,thrldec13\t\t\tis thc1212=1 & thrldec13 & r12\t\t\t\t{ r12 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec12: thrldec13\t\t\t\tis thc1212=0 & thrldec13\t\t\t{ }\nthrldec11: r11^thrldec12\t\t\tis thc1111=1 & thrldec12 & r11 & thc1215=0\t{ r11 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec11: r11,thrldec12\t\t\tis thc1111=1 & thrldec12 & r11\t\t\t\t{ r11 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec11: thrldec12\t\t\t\tis thc1111=0 & thrldec12\t\t\t{ }\nthrldec10: r10^thrldec11\t\t\tis thc1010=1 & thrldec11 & r10 & thc1115=0\t{ r10 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec10: r10,thrldec11\t\t\tis thc1010=1 & thrldec11 & r10\t\t\t\t{ r10 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec10: thrldec11\t\t\t\tis thc1010=0 & thrldec11\t\t\t{ }\nthrldec9: r9^thrldec10\t\t\t\tis thc0909=1 & thrldec10 & r9 & thc1015=0\t{ r9 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec9: r9,thrldec10\t\t\t\tis thc0909=1 & thrldec10 & r9\t\t\t\t{ r9 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec9: thrldec10\t\t\t\t\tis thc0909=0 & thrldec10\t\t\t{ }\nthrldec8: r8^thrldec9\t\t\t\tis thc0808=1 & thrldec9 & r8 & thc0915=0\t{ r8 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec8: r8,thrldec9\t\t\t\tis thc0808=1 & thrldec9 & r8\t\t\t\t{ r8 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec8: thrldec9\t\t\t\t\tis thc0808=0 & thrldec9\t\t\t\t{ }\nthrldec7: r7^thrldec8\t\t\t\tis thc0707=1 & thrldec8 & r7 & thc0815=0\t{ r7 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec7: r7,thrldec8\t\t\t\tis thc0707=1 & thrldec8 & r7\t\t\t\t{ r7 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec7: thrldec8\t\t\t\t\tis thc0707=0 & thrldec8\t\t\t\t{ }\nthrldec6: r6^thrldec7\t\t\t\tis thc0606=1 & thrldec7 & r6 & thc0715=0\t{ r6 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec6: r6,thrldec7\t\t\t\tis thc0606=1 & thrldec7 & r6\t\t\t\t{ r6 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec6: thrldec7\t\t\t\t\tis thc0606=0 & thrldec7\t\t\t\t{ }\nthrldec5: r5^thrldec6\t\t\t\tis thc0505=1 & thrldec6 & r5 & thc0615=0\t{ r5 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec5: r5,thrldec6\t\t\t\tis thc0505=1 & thrldec6 & r5\t\t\t\t{ r5 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec5: thrldec6\t\t\t\t\tis thc0505=0 & thrldec6\t\t\t\t{ }\nthrldec4: r4^thrldec5\t\t\t\tis thc0404=1 & thrldec5 & r4 & thc0515=0\t{ r4 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec4: r4,thrldec5\t\t\t\tis thc0404=1 & thrldec5 & r4\t\t\t\t{ r4 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec4: thrldec5\t\t\t\t\tis thc0404=0 & thrldec5\t\t\t\t{ }\nthrldec3: r3^thrldec4\t\t\t\tis thc0303=1 & thrldec4 & r3 & thc0415=0\t{ r3 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec3: r3,thrldec4\t\t\t\tis thc0303=1 & thrldec4 & r3\t\t\t\t{ r3 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec3: thrldec4\t\t\t\t\tis thc0303=0 & thrldec4\t\t\t\t{ }\nthrldec2: r2^thrldec3\t\t\t\tis thc0202=1 & thrldec3 & r2 & thc0315=0\t{ r2 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec2: r2,thrldec3\t\t\t\tis thc0202=1 & thrldec3 & r2\t\t\t\t{ r2 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec2: thrldec3\t\t\t\t\tis thc0202=0 & thrldec3\t\t\t\t{ }\nthrldec1: r1^thrldec2\t\t\t\tis thc0101=1 & thrldec2 & r1 & thc0215=0\t{ r1 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec1: r1,thrldec2\t\t\t\tis thc0101=1 & thrldec2 & r1\t\t\t\t{ r1 = * mult_addr; mult_addr = mult_addr - 4; }\nthrldec1: thrldec2\t\t\t\t\tis thc0101=0 & thrldec2\t\t\t\t{ }\nthldrlist_dec: {r0^thrldec1}\t\tis thc0000=1 & thrldec1 & r0 & thc0115=0\t{ r0 = * mult_addr; mult_addr = mult_addr - 4; }\nthldrlist_dec: {r0,thrldec1}\t\tis thc0000=1 & thrldec1 & r0\t\t\t\t{ r0 = * mult_addr; mult_addr = mult_addr - 4; }\nthldrlist_dec: {thrldec1}\t\t\tis thc0000=0 & thrldec1\t\t\t\t{ }\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n# thstrlist_dec is the list of registers to be pushed\nthsdec15: pc\t\t\t\t\t\tis thc1515=1 & pc\t\t\t\t\t\t\t{ *:4 mult_addr = inst_start+4; mult_addr = mult_addr - 4; }\nthsdec15: \t\t\t\t\t\t\tis thc1515=0\t\t\t\t\t\t{ }\nthsdec14: lr\t\t\t\t\t\tis thc1414=1 & thsdec15 & lr & thc1515=0\t{ * mult_addr=lr; mult_addr = mult_addr - 4; }\nthsdec14: lr,thsdec15\t\t\t\tis thc1414=1 & thsdec15 & lr\t\t\t\t{ * mult_addr=lr; mult_addr = mult_addr - 4; }\nthsdec14: thsdec15\t\t\t\t\tis thc1414=0 & thsdec15\t\t\t\t{ }\nthsdec13: sp\t\t\t\t\t\tis thc1313=1 & sp & thc1415=0\t{ * mult_addr=sp; mult_addr = mult_addr - 4; }\nthsdec13: sp,thsdec14\t\t\t\tis thc1313=1 & thsdec14 & sp\t\t\t\t{ * mult_addr=sp; mult_addr = mult_addr - 4; }\nthsdec13: thsdec14\t\t\t\t\tis thc1313=0 & thsdec14\t\t\t\t{ }\nthsdec12: r12\t\t\t\t\t\tis thc1212=1 & r12 & thc1315=0\t{ * mult_addr=r12; mult_addr = mult_addr - 4; }\nthsdec12: r12,thsdec13\t\t\t\tis thc1212=1 & thsdec13 & r12\t\t\t\t{ * mult_addr=r12; mult_addr = mult_addr - 4; }\nthsdec12: thsdec13\t\t\t\t\tis thc1212=0 & thsdec13\t\t\t\t{ }\nthsdec11: r11\t\t\t\t\t\tis thc1111=1 & r11 & thc1215=0\t{ * mult_addr=r11; mult_addr = mult_addr - 4; }\nthsdec11: r11,thsdec12\t\t\t\tis thc1111=1 & thsdec12 & r11\t\t\t\t{ * mult_addr=r11; mult_addr = mult_addr - 4; }\nthsdec11: thsdec12\t\t\t\t\tis thc1111=0 & thsdec12\t\t\t\t{ }\nthsdec10: r10\t\t\t\t\t\tis thc1010=1 & r10 & thc1115=0\t{ * mult_addr=r10; mult_addr = mult_addr - 4; }\nthsdec10: r10,thsdec11\t\t\t\tis thc1010=1 & thsdec11 & r10\t\t\t\t{ * mult_addr=r10; mult_addr = mult_addr - 4; }\nthsdec10: thsdec11\t\t\t\t\tis thc1010=0 & thsdec11\t\t\t\t{ }\nthsdec9: r9\t\t\t\t\t\t\tis thc0909=1 & r9 & thc1015=0\t{ * mult_addr=r9; mult_addr = mult_addr - 4; }\nthsdec9: r9,thsdec10\t\t\t\tis thc0909=1 & thsdec10 & r9\t\t\t\t{ * mult_addr=r9; mult_addr = mult_addr - 4; }\nthsdec9: thsdec10\t\t\t\t\tis thc0909=0 & thsdec10\t\t\t\t{ }\nthsdec8: r8\t\t\t\t\t\t\tis thc0808=1 & r8 & thc0915=0\t\t{ * mult_addr=r8; mult_addr = mult_addr - 4; }\nthsdec8: r8,thsdec9\t\t\t\t\tis thc0808=1 & thsdec9 & r8\t\t\t\t\t{ * mult_addr=r8; mult_addr = mult_addr - 4; }\nthsdec8: thsdec9\t\t\t\t\tis thc0808=0 & thsdec9\t\t\t\t{ }\nthsdec7: r7\t\t\t\t\t\t\tis thc0707=1 & r7 & thc0815=0\t\t{ * mult_addr=r7; mult_addr = mult_addr - 4; }\nthsdec7: r7,thsdec8\t\t\t\t\tis thc0707=1 & thsdec8 & r7\t\t\t\t\t{ * mult_addr=r7; mult_addr = mult_addr - 4; }\nthsdec7: thsdec8\t\t\t\t\tis thc0707=0 & thsdec8\t\t\t\t{ }\nthsdec6: r6\t\t\t\t\t\t\tis thc0606=1 & r6 & thc0715=0\t\t{ * mult_addr=r6; mult_addr = mult_addr - 4; }\nthsdec6: r6,thsdec7\t\t\t\t\tis thc0606=1 & thsdec7 & r6\t\t\t\t\t{ * mult_addr=r6; mult_addr = mult_addr - 4; }\nthsdec6: thsdec7\t\t\t\t\tis thc0606=0 & thsdec7\t\t\t\t{ }\nthsdec5: r5\t\t\t\t\t\t\tis thc0505=1 & r5 & thc0615=0\t\t{ * mult_addr=r5; mult_addr = mult_addr - 4; }\nthsdec5: r5,thsdec6\t\t\t\t\tis thc0505=1 & thsdec6 & r5\t\t\t\t\t{ * mult_addr=r5; mult_addr = mult_addr - 4; }\nthsdec5: thsdec6\t\t\t\t\tis thc0505=0 & thsdec6\t\t\t\t{ }\nthsdec4: r4\t\t\t\t\t\t\tis thc0404=1 & r4 & thc0515=0\t\t{ * mult_addr=r4; mult_addr = mult_addr - 4; }\nthsdec4: r4,thsdec5\t\t\t\t\tis thc0404=1 & thsdec5 & r4\t\t\t\t\t{ * mult_addr=r4; mult_addr = mult_addr - 4; }\nthsdec4: thsdec5\t\t\t\t\tis thc0404=0 & thsdec5\t\t\t\t{ }\nthsdec3: r3\t\t\t\t\t\t\tis thc0303=1 & r3 & thc0415=0\t\t{ * mult_addr=r3; mult_addr = mult_addr - 4; }\nthsdec3: r3,thsdec4\t\t\t\t\tis thc0303=1 & thsdec4 & r3\t\t\t\t\t{ * mult_addr=r3; mult_addr = mult_addr - 4; }\nthsdec3: thsdec4\t\t\t\t\tis thc0303=0 & thsdec4\t\t\t\t{ }\nthsdec2: r2\t\t\t\t\t\t\tis thc0202=1 & r2 & thc0315=0\t\t{ * mult_addr=r2; mult_addr = mult_addr - 4; }\nthsdec2: r2,thsdec3\t\t\t\t\tis thc0202=1 & thsdec3 & r2\t\t\t\t\t{ * mult_addr=r2; mult_addr = mult_addr - 4; }\nthsdec2: thsdec3\t\t\t\t\tis thc0202=0 & thsdec3\t\t\t\t{ }\nthsdec1: r1\t\t\t\t\t\t\tis thc0101=1 & r1 & thc0215=0\t\t{ * mult_addr=r1; mult_addr = mult_addr - 4; }\nthsdec1: r1,thsdec2\t\t\t\t\tis thc0101=1 & thsdec2 & r1\t\t\t\t\t{ * mult_addr=r1; mult_addr = mult_addr - 4; }\nthsdec1: thsdec2\t\t\t\t\tis thc0101=0 & thsdec2\t\t\t\t{ }\nthstrlist_dec: {r0}\t\t\t\t\tis thc0000=1 & r0 & thc0115=0\t\t\t\t{ * mult_addr=r0; mult_addr = mult_addr - 4; }\nthstrlist_dec: {r0,thsdec1}\t\t\tis thc0000=1 & thsdec1 & r0\t\t\t\t\t{ * mult_addr=r0; mult_addr = mult_addr - 4; }\nthstrlist_dec: {thsdec1^}\t\t\tis thc0000=0 & thsdec1\t\t\t\t{ }\n\nldbrace: {ldlist}\tis ldlist\t\t\t{ }\nstbrace: {strlist}\tis strlist\t\t\t{ }\npsbrace: {pshlist}\tis pshlist\t\t\t{ }\n\n# Some extra subconstructors for the push and pop instructions\npclbrace:{ldlist,pc}\tis ldlist & pc\t\t\t{ build ldlist; pc = *mult_addr; mult_addr = mult_addr + 4; }\npclbrace:{pc}\tis thc0007=0 & pc\t\t\t\t\t{ pc = *mult_addr; mult_addr = mult_addr + 4; }\npcpbrace:{pshlist,lr}\tis pshlist & lr\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = lr; build pshlist; }\npcpbrace:{lr}\tis thc0007=0 & lr\t\t\t\t\t{ mult_addr = mult_addr - 4; *mult_addr = lr; }\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\nRnIndirect12: [Rn0003,\"#\"^offset12]\tis Rn0003; offset12\t { local tmp = Rn0003 + offset12; export tmp; }\n\nRnIndirectPUW: [Rn0003],\"#\"^-immed8\tis Rn0003; addr_puw=1 & immed8\t { local tmp = Rn0003; Rn0003=Rn0003-immed8; export tmp; }\nRnIndirectPUW: [Rn0003],\"#\"^immed8\t is Rn0003; addr_puw=3 & immed8\t { local tmp = Rn0003; Rn0003=Rn0003+immed8; export tmp; }\nRnIndirectPUW: [Rn0003,\"#\"^-immed8]\tis Rn0003; addr_puw=4 & immed8\t { local tmp = Rn0003 - immed8; export tmp; }\nRnIndirectPUW: [Rn0003,\"#\"^-immed8]!\tis Rn0003; addr_puw=5 & immed8\t { local tmp = Rn0003 - immed8; Rn0003=tmp; export tmp; }\nRnIndirectPUW: [Rn0003,\"#\"^immed8]!\tis Rn0003; addr_puw=7 & immed8\t { local tmp = Rn0003 + immed8; Rn0003=tmp; export tmp; }\n\n@define RN_INDIRECT_PUW \"(op0; (addr_puw=4 | thc0808=1)) & RnIndirectPUW\" # constraint for RnIndirectPUW\n\nRnIndirectPUW1: [Rn0003],\"#\"^-immval\tis Rn0003 & addr_puw1=0x3; immed8 [ immval = immed8 * 4; ]\t { local tmp = Rn0003; Rn0003=Rn0003-immval; export tmp; }\nRnIndirectPUW1: [Rn0003],\"#\"^immval\tis Rn0003 & addr_puw1=0x7; immed8 [ immval = immed8 * 4; ]\t { local tmp = Rn0003; Rn0003=Rn0003+immval; export tmp; }\nRnIndirectPUW1: [Rn0003,\"#\"^-immval]\tis Rn0003 & addr_puw1=0xa; immed8 [ immval = immed8 * 4; ]\t { local tmp = Rn0003 - immval; export tmp; }\nRnIndirectPUW1: [Rn0003,\"#\"^-immval]!\tis Rn0003 & addr_puw1=0xb; immed8 [ immval = immed8 * 4; ]\t { local tmp = Rn0003 - immval; Rn0003=tmp; export tmp; }\nRnIndirectPUW1: [Rn0003,\"#\"^immval]\tis Rn0003 & addr_puw1=0xe; immed8 [ immval = immed8 * 4; ]\t { local tmp = Rn0003 + immval; export tmp; }\nRnIndirectPUW1: [Rn0003,\"#\"^immval]!\tis Rn0003 & addr_puw1=0xf; immed8 [ immval = immed8 * 4; ]\t { local tmp = Rn0003 + immval; Rn0003=tmp; export tmp; }\n\n@endif # VERSION_6T2 || VERSION_7\n\n@define RN_INDIRECT_PUW1 \"((thc0808=1 | thc0505=1); op0) & RnIndirectPUW1\" # constraint for RnIndirectPUW1\n\nRnIndirect4: [Rn0305,\"#\"^immval]\tis Rn0305 & immed5\t[ immval = immed5 * 4; ] { local tmp = Rn0305 + immval; export tmp; }\nRnIndirect2: [Rn0305,\"#\"^immval]\tis Rn0305 & immed5\t[ immval = immed5 * 2; ] { local tmp = Rn0305 + immval; export tmp; }\nRnIndirect1: [Rn0305,\"#\"^immed5]\tis Rn0305 & immed5\t{ local tmp = Rn0305 + immed5; export tmp; }\n\nRnRmIndirect: [Rn0305,Rm0608]\tis Rn0305 & Rm0608\t{ local tmp = Rn0305 + Rm0608; export tmp; }\n\nPcrel8Indirect: [reloc]\tis immed8\n [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ]\n{\n export *:4 reloc;\n}\n\nSprel8Indirect: [sp,\"#\"^immval]\tis sp & immed8 [ immval = immed8 * 4; ] { local tmp = sp + immval; export tmp; }\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\ntaddrmode5: [Rn0003,\"#\"^off8]\tis thP8=1 & thU7=1 & thW5=0 & Rn0003; immed8\t\t[ off8=immed8*4; ] { local tmp = Rn0003 + off8; export tmp; }\ntaddrmode5: [Rn0003,\"#\"^noff8]\tis thP8=1 & thU7=0 & thW5=0 & Rn0003; immed8\t\t[ noff8=-(immed8*4); ] { local tmp = Rn0003 + noff8; export tmp; }\ntaddrmode5: [Rn0003,\"#\"^off8]!\tis thP8=1 & thU7=1 & thW5=1 & Rn0003; immed8\t\t[ off8=immed8*4; ] { Rn0003 = Rn0003 + off8; export Rn0003; }\ntaddrmode5: [Rn0003,\"#\"^noff8]!\tis thP8=1 & thU7=0 & thW5=1 & Rn0003; immed8\t\t[ noff8=-(immed8*4); ] { Rn0003 = Rn0003 + noff8; export Rn0003; }\ntaddrmode5: [Rn0003],\"#\"^off8\tis thP8=0 & thU7=1 & thW5=1 & Rn0003; immed8\t\t[ off8=immed8*4; ] { local tmp = Rn0003; Rn0003 = Rn0003+off8; export tmp; }\ntaddrmode5: [Rn0003],\"#\"^noff8\tis thP8=0 & thU7=0 & thW5=1 & Rn0003; immed8\t\t[ noff8=-(immed8*4); ] { local tmp = Rn0003; Rn0003 = Rn0003 + noff8; export tmp; }\ntaddrmode5: [Rn0003],{immed8}\tis thP8=0 & thU7=1 & thW5=0 & Rn0003; immed8\t\t\t\t { export Rn0003; }\n\n@endif # VERSION_6T2 || VERSION_7\n\n#\n# Modes for SRS instructions\n#\nthSRSMode: \"usr\" is thsrsMode=8 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"fiq\" is thsrsMode=9 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"irq\" is thsrsMode=10 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"svc\" is thsrsMode=11 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"mon\" is thsrsMode=14 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"abt\" is thsrsMode=15 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"und\" is thsrsMode=19 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"sys\" is thsrsMode=23 & thc0004 { export *[const]:1 thc0004; }\nthSRSMode: \"#\"^thsrsMode is thsrsMode { export *[const]:1 thsrsMode; }\n\n#\n# Detect if the PC is loaded and do a GOTO\n#\n# TODO: this is how all detections of writes into the PC should be done.\n# Instead of enumerating and splitting the case into PC loaded and non loaded, IE (add PC,#0x...)\n# Should only have one base constructor and have a sub constructor and build to test if the PC was loaded and do the right thing.\n#\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nRtGotoCheck: is Rt1215=15 {\n LoadWritePC(pc);\n goto [pc];\n}\nRtGotoCheck: is Rt1215 {}\n\n@endif # VERSION_6T2 || VERSION_7\n\n############################################################\n\n# Base constructors\n\n# We have the following operand types:\n#\tType\t\tCorresponding syntax in ARM/THUMB manual\n#\n#\tRd0002\t\t with Rd occupying bits 0-2\n#\tRd0810\t\t with Rd occupying bits 8-10\n#\tRm0305\t\t with Rm occupying bits 3-5\n#\tRm0608\t\t with Rm occupying bits 6-8\n#\tRn0002\t\t with Rn occupying bits 0-2\n#\tRn0305\t\t with Rn occupying bits 3-5\n#\tRn0810\t\t with Rn occupying bits 8-10\n#\tHrd0002\t\t with H1 bit in diagram\n#\tHrn0002\t\t with H1 bit in diagram\n#\tHrm0305\t\t with H2 bit in diagram\n#\tRs0305\t\t with Rs occupying bits 3-5\n#\tImmed3\t\t#\n#\tImmed5\t\t#\n#\tImmed8\t\t#\n#\tPcrel8\t\tPC,#*4\n#\tSprel8\t\tSP,#*4\n#\tImmed7_4\t#*4\n#\tthcc\t\t\n#\tAddr8\t\t (for B)\n#\tAddr11\t\t (for B no condition)\n#\tThAddr22\t\t (for double BL, BLX)\n#\timmed8\t\t (no \"#\" as in BKPT and SWI)\n#\tRn_exclaim\t!\n#\tldbrace\t\t (load instructions)\n#\tstrbrace\t (store instructions)\n#\tRnIndirect4\t[,#*4]\n#\tRnIndirect2\t[,#*2]\n#\tRnIndirect1\t[,#]\n#\tRnRmIndirect\t[,]\n#\tPcrel8Indirect\t[PC,#*4]\n#\tSprel8Indirect\t[SP,#*4]\n\n#\n\n\n# Ensure that the condition check phase has been completed\nwith : ARMcondCk=1 {\n\n:adc^CheckInIT_CZNO^ItCond\tRd0002,Rm0305 \t\tis TMode=1 & ItCond & op6=0x105 & Rm0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_add_with_carry_flags(Rd0002,Rm0305);\n Rd0002 = Rd0002 + Rm0305 + zext(CY);\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:adc^thSBIT_CZNO^ItCond\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=0xa & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n th_add_with_carry_flags(Rn0003,ThumbExpandImm12);\n Rd0811 = Rn0003 + ThumbExpandImm12 + zext(CY);\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:adc^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=0xa & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n th_add_with_carry_flags(Rn0003,thshift2);\n local tmp = thshift2+zext(CY);\n Rd0811 = Rn0003+tmp;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n@endif # VERSION_6T2 || VERSION_7\n\n:add^CheckInIT_CZNO^ItCond\tRd0002,Rn0305,Immed3\tis TMode=1 & ItCond & op9=0x0e & Immed3 & Rn0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_addflags(Rn0305,Immed3);\n Rd0002 = Rn0305 + Immed3;\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n:add^CheckInIT_CZNO^ItCond\tRd0810,Immed8\t\tis TMode=1 & ItCond & op11=0x06 & Rd0810 & Immed8 & CheckInIT_CZNO\n{\n build ItCond;\n th_addflags(Rd0810,Immed8);\n Rd0810 = Rd0810 + Immed8;\n resflags(Rd0810);\n build CheckInIT_CZNO;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:add^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=8 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n th_addflags(Rn0003,ThumbExpandImm12);\n Rd0811 = Rn0003+ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:addw^ItCond\tRd0811,Rn0003,Immed12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & Rn0003; thc1515=0 & Rd0811) & Immed12\n{\n build ItCond;\n th_addflags(Rn0003,Immed12);\n Rd0811 = Rn0003+Immed12;\n resflags(Rd0811);\n}\n\n:add^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=8 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n local tmp = thshift2;\n th_addflags(Rn0003,tmp);\n Rd0811 = Rn0003+tmp;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:add^thSBIT_CZNO^ItCond^\".w\"\tRd0811,sp,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=8 & thSBIT_CZNO & sp & sop0003=0xd; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n th_addflags(sp,ThumbExpandImm12);\n Rd0811 = sp+ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:addw^ItCond\tRd0811,sp,Immed12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & sop0003=0xd & sp; thc1515=0 & Rd0811) & Immed12\n{\n build ItCond;\n th_addflags(sp,Immed12);\n Rd0811 = sp+Immed12;\n resflags(Rd0811);\n}\n\n:add^thSBIT_CZNO^ItCond^\".w\"\tRd0811,sp,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=8 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n local tmp = thshift2;\n th_addflags(sp,tmp);\n Rd0811 = sp+tmp;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:add^CheckInIT_CZNO^ItCond\tRd0002,Rn0305,Rm0608\tis TMode=1 & ItCond & op9=0x0c & Rm0608 & Rn0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_addflags(Rn0305,Rm0608);\n Rd0002 = Rn0305 + Rm0608;\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n:add^ItCond\tHrd0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x44 & Hrd0002 & Hrm0305\n{\n build ItCond;\n Hrd0002 = Hrd0002 + Hrm0305;\n}\n\n:add^ItCond\tHrd0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x44 & Hrd0002 & Hrm0305 & hrd0002=7 & h1=1\n{\n build ItCond;\n dest:4 = Hrd0002 + Hrm0305;\n BranchWritePC(dest);\n goto [pc];\n}\n\n:add^ItCond\tRd0810,Sprel8\t\tis TMode=1 & ItCond & op11=0x15 & Rd0810 & Sprel8\n{\n build ItCond;\n Rd0810 = Sprel8;\n}\n\n:add^ItCond\tsp,Immed7_4\t\tis TMode=1 & ItCond & op7=0x160 & sp & Immed7_4\n{\n build ItCond;\n sp = sp + Immed7_4;\n}\n\n:adr^ItCond\tRd0810,Pcrel8\t\tis TMode=1 & ItCond & op11=0x14 & Rd0810 & Pcrel8\n{\n build ItCond;\n Rd0810 = &Pcrel8;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:adr^ItCond^\".w\"\tRd0811,NegPcrelImmed12Addr \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811) & NegPcrelImmed12Addr\n{\n build ItCond;\n Rd0811 = &NegPcrelImmed12Addr;\n}\n\n:adr^ItCond^\".w\"\tRd0811,PcrelImmed12Addr \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811) & PcrelImmed12Addr\n{\n build ItCond;\n Rd0811 = &PcrelImmed12Addr;\n}\n\n:adr^ItCond^\".w\"\tRd0811,NegPcrelImmed12Addr \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811 & thc0811=15) & NegPcrelImmed12Addr\n{\n build ItCond;\n pc = &NegPcrelImmed12Addr;\n goto NegPcrelImmed12Addr;\n}\n\n:adr^ItCond^\".w\"\tRd0811,PcrelImmed12Addr \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811 & thc0811=15) & PcrelImmed12Addr\n{\n build ItCond;\n pc = &PcrelImmed12Addr;\n goto PcrelImmed12Addr;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:and^CheckInIT_ZN^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x100 & Rd0002 & Rm0305 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = Rd0002 & Rm0305;\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:and^thSBIT_ZN^ItCond\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=0 & thSBIT_ZN & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n Rd0811 = Rn0003 & ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n\n:and^thSBIT_ZN^ItCond^\".w\"\tRd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=0 & thSBIT_ZN & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n Rd0811 = Rn0003 & thshift2;\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n@endif # VERSION_6T2 || VERSION_7\n\nmacro th_set_carry_for_asr(op1,shift_count) {\n local bit = (op1 s>> (shift_count-1)) & 1;\n tmpCY = ((shift_count == 0) && CY) || ((shift_count != 0) && (bit != 0));\n}\n\n#note that this is a special case where immed5 = 0, which corresponds to a shift amount of 32\n:asr^CheckInIT_CZN^ItCond\tRd0002,Rm0305,\"#0x20\"\tis TMode=1 & ItCond & op11=0x02 & Immed5 & Rm0305 & Rd0002 & immed5=0 & CheckInIT_CZN\n{\n build ItCond;\n th_set_carry_for_asr(Rm0305,32:1);\n Rd0002 = Rm0305 s>> 32;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n:asr^CheckInIT_CZN^ItCond\tRd0002,Rm0305,Immed5\tis TMode=1 & ItCond & op11=0x02 & Immed5 & Rm0305 & Rd0002 & CheckInIT_CZN\n{\n build ItCond;\n th_set_carry_for_asr(Rm0305,Immed5);\n Rd0002 = Rm0305 s>> Immed5;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n:asr^CheckInIT_CZN^ItCond\tRd0002,Rs0305\t\tis TMode=1 & ItCond & op6=0x104 & Rd0002 & Rs0305 & CheckInIT_CZN\n{\n build ItCond;\n local shift_amount = Rs0305 & 0xff;\n th_set_carry_for_asr(Rd0002,shift_amount);\n Rd0002 = Rd0002 s>> (shift_amount);\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:asr^thSBIT_CZN^ItCond^\".w\"\tRd0811,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=0xf; thc1515=0 & Rd0811 & thc0405=2 & thshift2\n{\n build ItCond;\n build thshift2;\n Rd0811 = thshift2;\n tmpCY = shift_carry;\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n:asr^thSBIT_CZN^ItCond^\".w\"\tRd0811,Rn0003,Rm0003 \t\tis TMode=1 & ItCond & op11=0x1f & thc0910=1 & sop0508=2 & thSBIT_CZN & Rn0003; op12=0xf & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n local shift_amount = Rm0003 & 0xff;\n th_set_carry_for_asr(Rn0003,shift_amount);\n Rd0811 = Rn0003 s>> (shift_amount);\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n@endif # VERSION_6T2 || VERSION_7\n\n# this constructor is identical to 16-bit udf instruction. it looks\n# like it implented an unconditional branch instruction (giving it a\n# made up name), but the thumb 16-bit instruction does not support\n# unconditional branching.\n\n@ifdef NOT_AN_INSTRUCTION\n:bal\tAddr8\t\t\tis TMode=1 & op12=0xd & thcond=14 & Addr8\n{\n goto Addr8;\n}\n@endif\n\n:b^thcc\tAddr8\t\t\tis TMode=1 & ItCond & op12=0b1101 & $(THCC) & Addr8\n{\n if (thcc) goto Addr8;\n}\n\n:b^ItCond\tAddr11\t\t\tis TMode=1 & ItCond & op11=0b11100 & Addr11\n{\n goto Addr11;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:b^part2thcc^\".w\"\tThAddr20 \t\tis TMode=1 & (part2op=0x1e & $(PART2THCC); part2c1415=2 & part2c1212=0) & ThAddr20\n{\n if (part2thcc) goto ThAddr20;\n}\n\n:b^ItCond^\".w\"\tThAddr24 \t\tis TMode=1 & ItCond & (op11=0x1e; part2c1415=2 & part2c1212=1) & ThAddr24\n{\n build ItCond;\n goto ThAddr24;\n}\n@endif # VERSION_6T2 || VERSION_7\n\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n:bfc^ItCond\tRd0811,thLsbImm,thBitWidth \t\tis TMode=1 & ItCond & op0=0xf36f; thc1515=0 & Rd0811 & thc0505=0 & thLsbImm & thMsbImm & thBitWidth\n{\n build ItCond;\n\tclearMask:4 = (-1 << (thMsbImm + 1)) | (-1 >> (32 - thLsbImm));\n\tRd0811 = Rd0811 & clearMask;\n}\n\n:bfi^ItCond\tRd0811,Rn0003,thLsbImm,thBitWidth \t\tis TMode=1 & ItCond & op4=0xf36 & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thLsbImm & thBitWidth\n{\n build ItCond;\n vmask:4 = (1 << thBitWidth) - 1;\n clear:4 = ~(vmask << thLsbImm);\n bits:4 = (Rn0003 & vmask) << thLsbImm;\n Rd0811 = (Rd0811 & clear) | bits;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n\n:bic^CheckInIT_ZN^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x10e & Rd0002 & Rm0305 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = Rd0002 & (~Rm0305);\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:bic^thSBIT_ZN^ItCond Rd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=1 & thSBIT_ZN & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n Rd0811 = Rn0003&(~ThumbExpandImm12);\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n\n:bic^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=1 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n Rd0811 = Rn0003&(~thshift2);\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n@endif # VERSION_6T2 || VERSION_7\n\n\n@if defined(VERSION_5)\n\n# Exception Generation and UDF\n\n:hlt immed6\t\t\t\tis TMode=1 & op6=0b1011101010 & immed6\n{\n\tsoftware_hlt(immed6:4);\n}\n\n:bkpt immed8\t\t\t\tis TMode=1 & ItCond & op8=0xbe & immed8\n{\n\tsoftware_bkpt(immed8:4);\n\t# Not a mistake, breakpoint always unconditional even in IT Block\n\tbuild ItCond;\n}\n\n:hvc \"#\"^tmp\t\t\t\tis TMode=1 & op4=0xf7e & thc0003; op12=0x8 & thc0011 [tmp = thc0003 << 12 | thc0011;]\n{\n\tsoftware_hvc(tmp:4);\n}\n\n# Requires Security Extensions\n:smc^ItCond \"#\"^thc0003\t\t\tis TMode=1 & ItCond & op4=0xf7f & thc0003; op12=0x8\n{\n\tbuild ItCond;\n\tsoftware_smc(thc0003:1);\n}\n\n@ifndef NOT_AN_INSTRUCTION\n:udf^ItCond \"#\"thc0007\t\t\tis TMode=1 & ItCond & op8 = 0xde & thc0007\n{\n\tbuild ItCond;\n\tlocal excaddr:4 = inst_start;\n\tlocal target:4 = software_udf(thc0007:4, excaddr);\n\tgoto [target];\n}\n@endif\n\n:udf^ItCond \"#\"tmp\t\t\tis TMode=1 & ItCond & op4=0xf7f & thc0003; op12=0xa & thc0011 [tmp = thc0003 << 12 | thc0011;]\n{\n\tbuild ItCond;\n\tlocal excaddr:4 = inst_start;\n\tlocal target:4 = software_udf(tmp:4, excaddr);\n\tgoto [target];\n}\n\n@endif # VERSION_5\n\n:bl^ItCond \tThAddr24 \t\t\tis TMode=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=1) & ThAddr24\n{\n build ItCond;\n lr = inst_next|1;\n SetThumbMode(1);\n call ThAddr24;\n}\n\n@ifndef VERSION_6T2\n\n:bl^ItCond \"#\"^off\t\tis TMode=1 & ItCond & op11=0x1e & soffset11 [ off = inst_start + 4 + (soffset11 << 12); ]\n{\n build ItCond;\n lr = off:4;\n}\n\n:bl^ItCond \"#\"^off\t\tis TMode=1 & ItCond & op11=0x1f & offset11 [ off = offset11 << 1; ]\n{\n build ItCond;\n local dest = lr + off:4;\n lr = inst_next|1;\n SetThumbMode(1);\n call [dest];\n}\n\n:bl^ItCond lr\t\t\tis TMode=1 & ItCond & op11=0x1f & offset11=0 & lr\n{\n build ItCond;\n local dest = lr;\n lr = inst_next|1;\n SetThumbMode(1);\n call [dest];\n}\n\n:blx^ItCond \"#\"^off \tis TMode=1 & ItCond & op11=0x1d & offset11 & thc0000=0 [ off = offset11 << 1; ]\n{\n build ItCond;\n local dest = (lr & (~0x3)) + off:4;\n lr = inst_next|1;\n SetThumbMode(0);\n call [dest];\n}\n\n:blx^ItCond lr\t\t\tis TMode=1 & ItCond & op11=0x1d & offset11=0 & thc0000=0 & lr\n{\n build ItCond;\n local dest = (lr & (~0x3));\n lr = inst_next|1;\n SetThumbMode(0);\n call [dest];\n}\n\n@endif\n\n:bl^ItCond \tThAddr24 \t\t\tis TMode=1 & CALLoverride=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=1) & ThAddr24\n{\n build ItCond;\n lr = inst_next|1;\n SetThumbMode(1);\n goto ThAddr24;\n}\n\nbxns: \"\" is thc0003 { }\nbxns: \"ns\" is thc0002=0b100 { }\n\n@if defined(VERSION_5)\n\n:blx^ItCond \tThArmAddr23 \t\t\tis TMode=1 & ItCond & (op11=0x1e;part2op=0x1d) & ThArmAddr23 [ TMode=0; globalset(ThArmAddr23,TMode); TMode=1; ]\n{\n build ItCond;\n lr = inst_next|1;\n SetThumbMode(0);\n call ThArmAddr23;\n # Don't set this, assume return will set for emulation. Was screwing up decompiler. TB = 1;\n}\n\n:blx^ItCond \tThArmAddr23 \t\t\tis TMode=1 & ItCond & CALLoverride=1 & (op11=0x1e;part2op=0x1d) & ThArmAddr23 [ TMode=0; globalset(ThArmAddr23,TMode); TMode=1; ]\n{\n build ItCond;\n lr = inst_next|1;\n SetThumbMode(0);\n goto ThArmAddr23;\n}\n\n:blx^ItCond \tThArmAddr23 \t\t\tis TMode=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=0) & ThArmAddr23 [ TMode=0; globalset(ThArmAddr23,TMode); TMode=1; ]\n{\n build ItCond;\n lr = inst_next|1;\n SetThumbMode(0);\n call ThArmAddr23;\n}\n\n:blx^bxns^ItCond\tHrm0305\t\t\tis TMode=1 & ItCond & op7=0x08f & Hrm0305 & bxns\n{\n build ItCond;\n BXWritePC(Hrm0305);\n lr = inst_next|1;\n call [pc];\n # Don't set this, assume return will set for emulation. Was screwing up decompiler. TB = 1;\n}\n\n@endif # VERSION_5\n\n:bx^bxns^ItCond\tHrm0305\t\t\tis TMode=1 & ItCond & op7=0x08e & Hrm0305 & hrm0305=6 & h2=1 & bxns\n{\n build ItCond;\n BXWritePC(Hrm0305);\n return [pc];\n}\n\n:bx^bxns^ItCond\tHrm0305\t\t\tis TMode=1 & ItCond & op7=0x08e & Hrm0305 & bxns\n{\n build ItCond;\n BXWritePC(Hrm0305);\n goto [pc];\n}\n\n:bx^bxns^ItCond\tHrm0305\t\t\tis TMode=1 & ItCond & LRset=1 & op7=0x08e & Hrm0305 & bxns [ LRset=0; TMode=1; globalset(inst_next,LRset); globalset(inst_next,TMode); ]\n{\n build ItCond;\n BXWritePC(Hrm0305);\n call [pc];\n # Don't set this, assume return will set for emulation. Was screwing up decompiler. TB = 1;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:bxj^ItCond\tRn0003 \t\tis TMode=1 & ItCond & op4=0xf3c & Rn0003; op0=0x8f00\n{\n build ItCond;\n success:1 = jazelle_branch();\n if (success) goto ;\n SetThumbMode( (Rn0003&0x00000001)!=0 );\n local tmp=Rn0003&0xfffffffe;\n goto [tmp];\n \n} # Optional change to THUMB\n\n@endif # VERSION_6T2 || VERSION_7\n\n:cbnz^ItCond Rn0002,Addr5 is TMode=1 & ItCond & op12=0xb & thc1111=1 & thc1010=0 & thc0808=1 & Rn0002 & Addr5\n{\n build ItCond;\n\tlocal tmp = Rn0002 != 0;\n\tif (tmp) goto Addr5;\n}\n\n:cbz^ItCond Rn0002,Addr5 is TMode=1 & ItCond & op12=0xb & thc1111=0 & thc1010=0 & thc0808=1 & Rn0002 & Addr5\n{\n build ItCond;\n\tlocal tmp = Rn0002 == 0;\n\tif (tmp) goto Addr5;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n@ifndef CDE\n:cdp^ItCond thcpn,thopcode1,thCRd,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thopcode1 & thCRn; thCRd & thcpn & thopcode2 & thc0404=0 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thopcode1;\n t_op2:4 = thopcode2;\n coprocessor_function(t_cpn,t_op1,t_op2,thCRd,thCRn,thCRm);\n}\n\n:cdp2^ItCond thcpn,thopcode1,thCRd,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thopcode1 & thCRn; thCRd & thcpn & thopcode2 & thc0404=0 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thopcode1;\n t_op2:4 = thopcode2;\n coprocessor_function2(t_cpn,t_op1,t_op2,thCRd,thCRn,thCRm);\n}\n@endif #CDE\n\ndefine pcodeop IndexCheck;\n\n:chka^ItCond Hrn0002,Rm0306 is TMode=1 & ItCond & TEEMode=1 & op8=0xca & Rm0306 & Hrn0002\n{\n build ItCond;\n local tmp = Hrn0002 <= Rm0306;\n if (!tmp) goto inst_next;\n lr = inst_next|1;\n \tIndexCheck();\n}\n\n:clrex^ItCond is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f2f\n{\n build ItCond;\n ClearExclusiveLocal();\n}\n\n:clz^ItCond\tRd0811,Rm0003\t\tis TMode=1 & ItCond & op4=0xfab & Rm0003; op12=15 & Rd0811\n{\n build ItCond;\n Rd0811 = lzcount(Rm0003);\n}\n\n:cmn^ItCond\tRn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=8 & thc0404=1 & Rn0003; thc1515=0 & thc0811=15) & ThumbExpandImm12\n{\n build ItCond;\n th_addflags(Rn0003,ThumbExpandImm12);\n local tmp = Rn0003 + ThumbExpandImm12;\n resflags(tmp);\n th_affectflags();\n}\n\n:cmn^ItCond^\".w\"\tRn0003,thshift2 \t\tis TMode=1 & ItCond & op4=0xeb1 & Rn0003; thc1515=0 & thc0811=15 & thshift2\n{\n build ItCond;\n build thshift2;\n th_addflags(Rn0003,thshift2);\n local tmp = Rn0003+thshift2;\n resflags(tmp);\n th_affectflags();\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:cmn^ItCond\tRn0002,Rm0305\tis TMode=1 & ItCond & op6=0x10b & Rm0305 & Rn0002\n{\n build ItCond;\n th_addflags(Rn0002,Rm0305);\n local tmp = Rn0002 + Rm0305;\n resflags(tmp);\n th_affectflags();\n}\n\n:cmp^ItCond\tRn0810,Immed8\t\tis TMode=1 & ItCond & op11=5 & Rn0810 & Immed8\n{\n build ItCond;\n th_subflags(Rn0810,Immed8);\n local tmp = Rn0810 - Immed8;\n resflags(tmp);\n th_affectflags();\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:cmp^ItCond^\".w\" Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & thc0404=1 & sop0508=13 & Rn0003; thc1515=0 & thc0811=15) & ThumbExpandImm12\n{\n build ItCond;\n th_subflags(Rn0003,ThumbExpandImm12);\n local tmp = Rn0003 - ThumbExpandImm12;\n resflags(tmp);\n th_affectflags();\n}\n\n:cmp^ItCond^\".w\" Rn0003,thshift2 \t\tis TMode=1 & ItCond & op4=0xebb & Rn0003; thc1515=0 & thc0811=15 & thshift2\n{\n build ItCond;\n th_subflags(Rn0003,thshift2);\n local tmp = Rn0003 - thshift2;\n resflags(tmp);\n th_affectflags();\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:cmp^ItCond\tRn0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x10a & Rm0305 & Rn0002\n{\n build ItCond;\n th_subflags(Rn0002,Rm0305);\n local tmp = Rn0002 - Rm0305;\n resflags(tmp);\n th_affectflags();\n}\n\n:cmp^ItCond\tHrn0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x45 & Hrm0305 & Hrn0002\n{\n build ItCond;\n th_subflags(Hrn0002,Hrm0305);\n local tmp = Hrn0002 - Hrm0305;\n resflags(tmp);\n th_affectflags();\n}\n\n@if defined(VERSION_6)\n\naflag: \"a\" is thc0202=1 & thc0404=0 \t{ enableDataAbortInterrupts(); }\naflag: \"a\" is thc0202=1 \t\t\t\t{ disableDataAbortInterrupts(); }\naflag: is thc0202=0 \t\t\t\t{ }\n\niflag: \"i\" is thc0101=1 & thc0404=0 \t{ enableIRQinterrupts(); } # 7M: set primask\niflag: \"i\" is thc0101=1 \t\t\t\t{ disableIRQinterrupts(); } # 7M: clear primask\niflag: is thc0101=0 \t\t\t\t{ }\n\nfflag: \"f\" is thc0000=1 & thc0404=0 \t{ enableFIQinterrupts(); } # 7M: set faultmask\nfflag: \"f\" is thc0000=1 \t\t\t\t{ disableFIQinterrupts(); } # 7M: clear faultmask\nfflag: is thc0000=0 \t\t\t\t{ }\n\niflags: aflag^iflag^fflag is aflag & iflag & fflag { }\n\n:cpsie^ItCond iflags is TMode=1 & ItCond & op8=0xb6 & sop0507=3 & thc0303=0 & iflags & thc0404=0\n{\n build ItCond;\n build iflags;\n\t# see iflags for semantics\n}\n\n:cpsid^ItCond iflags is TMode=1 & ItCond & op8=0xb6 & sop0507=3 & thc0303=0 & iflags & thc0404=1\n{\n build ItCond;\n build iflags;\n\t# see iflags for semantics\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n# For SCR 11074, implement the \"Encoding T2\" 32-bit Thumb-2 cps change processor state instruction\n# Note the manual says there are no conditions on this insn\n#\nth2_aflag: \"a\" is thc0707=1 & thc0910=0x2\t{ enableDataAbortInterrupts(); }\nth2_aflag: \"a\" is thc0707=1\t\t\t{ disableDataAbortInterrupts(); }\nth2_aflag: is thc0707=0\t\t\t{ }\n\nth2_iflag: \"i\" is thc0606=1 & thc0910=0x2\t{ enableIRQinterrupts(); } # 7M: set primask\nth2_iflag: \"i\" is thc0606=1\t\t\t{ disableIRQinterrupts(); } # 7M: clear primask\nth2_iflag: is thc0606=0\t\t\t{ }\n\nth2_fflag: \"f\" is thc0505=1 & thc0910=0\t\t{ enableFIQinterrupts(); } # 7M: set faultmask\nth2_fflag: \"f\" is thc0505=1\t\t\t{ disableFIQinterrupts(); } # 7M: clear faultmask\nth2_fflag: is thc0505=0\t\t\t{ }\n\nth2_iflags: th2_aflag^th2_iflag^th2_fflag is th2_aflag & th2_iflag & th2_fflag { }\n\nth2_SetMode: \"#\"^16 is thc0004=0x10 { setUserMode(); }\nth2_SetMode: \"#\"^17 is thc0004=0x11 { setFIQMode(); }\nth2_SetMode: \"#\"^18 is thc0004=0x12 { setIRQMode(); }\nth2_SetMode: \"#\"^19 is thc0004=0x13 { setSupervisorMode(); }\nth2_SetMode: \"#\"^22 is thc0004=0x16 { setMonitorMode(); }\nth2_SetMode: \"#\"^23 is thc0004=0x17 { setAbortMode(); }\nth2_SetMode: \"#\"^27 is thc0004=0x1b { setUndefinedMode(); }\nth2_SetMode: \"#\"^31 is thc0004=0x1f { setSystemMode(); }\n\n# 11110 0 1110 1 0 1111 10 0 0 0\n:cpsie th2_iflags, th2_SetMode is\n\tTMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2imm6=0x2f ;\n\tthc0910=0x2 & th2_SetMode & op11=0x10 & th2_iflags\n{\n\tbuild th2_iflags;\n}\n\n:cpsid th2_iflags, th2_SetMode is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2imm6=0x2f ;\n thc0910=0x3 & th2_SetMode & op11=0x10 & th2_iflags\n{\n build th2_iflags;\n}\n\n:cps th2_SetMode is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2imm6=0x2f ;\n thc0808=0x1 & th2_SetMode & op11=0x10 \n{\n}\n\n@endif # (VERSION_6T2) || defined(VERSION_7)\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:dbg^ItCond \"#\"^thc0004 is TMode=1 & ItCond & op0=0xf3af; op4=0x80f & thc0004\n{\n@if defined(VERSION_7)\n\tHintDebug(thc0004:1);\n@endif # VERSION_7\n}\n\n@if defined(VERSION_7)\n:dmb^ItCond \"#\"^thc0004 is TMode=1 & ItCond & op0=0xf3bf; op4=0x8f5 & thc0004\n{\n\tDataMemoryBarrier(thc0004:1);\n}\n\n:dsb^ItCond \"#\"^thc0004 is TMode=1 & ItCond & op0=0xf3bf; op4=0x8f4 & thc0004\n{\n\tDataSynchronizationBarrier(thc0004:1);\n}\n@endif\n\n:eor^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=4 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n Rd0811 = Rn0003 ^ ThumbExpandImm12;\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:eor^thSBIT_CZNO^ItCond^\".w\" Rd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=4 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n Rd0811 = Rn0003 ^ thshift2;\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n\n:enterx^ItCond is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f1f [ TEEMode=1; globalset(inst_next,TEEMode); ]\n{\n build ItCond;\n}\n\n:leavex^ItCond is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f0f [ TEEMode=0; globalset(inst_next,TEEMode); ]\n{\n build ItCond;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n\n:eor^CheckInIT_ZN^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x101 & Rm0305 & Rd0002 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = Rd0002 ^ Rm0305;\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n@if defined(VERSION_7)\n\n:hb^ItCond\t\"#\"^immed8\t\tis TMode=1 & ItCond & TEEMode=1 & op9=0x61 & immed8\n{\n build ItCond;\n}\n\n\n:isb^ItCond \"#\"^thc0004 is TMode=1 & ItCond & op0=0xf3bf; op4=0x8f6 & thc0004\n{\n\tInstructionSynchronizationBarrier(thc0004:1);\n}\n\n@endif # VERSION_7\n\n@if defined(VERSION_8)\n\n# F5.1.178 p2969 SEVL T1 variant\n:sevl\n\tis TMode=1 & op0=0b1011111101010000\n\t& ItCond\n\t{\n\t\tbuild ItCond;\n\t\tSendEvent();\n\t}\n\n@endif # VERSION_8\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\nX: \"t\" is TMode=1 & ((thc0404=1 & thc0303=1) | (thc0404=0 & thc0303=0)) & (thc0202=1 | thc0101=1 | thc0000=1) { }\nX: \"e\" is TMode=1 & ((thc0404=1 & thc0303=0) | (thc0404=0 & thc0303=1)) & (thc0202=1 | thc0101=1 | thc0000=1) { }\nX: \"\" is TMode=1 & thc0404 & thc0303 & (thc0202=0 & thc0101=0 & thc0000=0) { }\nY: \"t\" is TMode=1 & ((thc0404=1 & thc0202=1) | (thc0404=0 & thc0202=0)) & (thc0101=1 | thc0000=1) { }\nY: \"e\" is TMode=1 & ((thc0404=1 & thc0202=0) | (thc0404=0 & thc0202=1)) & (thc0101=1 | thc0000=1) { }\nY: \"\" is TMode=1 & thc0404 & thc0202 & (thc0101=0 & thc0000=0) { }\nZ: \"t\" is TMode=1 & ((thc0404=1 & thc0101=1) | (thc0404=0 & thc0101=0)) & (thc0000=1) { }\nZ: \"e\" is TMode=1 & ((thc0404=1 & thc0101=0) | (thc0404=0 & thc0101=1)) & (thc0000=1) { }\nZ: \"\" is TMode=1 & thc0404 & thc0101 & (thc0000=0) { }\n\nXYZ: is TMode=1 & sop0003=8 { } \nXYZ: X^Y^Z is TMode=1 & X & Y & Z { }\n\n\n:it^XYZ it_thfcc is TMode=1 & op8=0xbf & XYZ & $(IT_THFCC) & thc0507 & thc0004\n [ itmode=0; cond_base = thc0507; cond_shft=thc0004; globalset(inst_next,condit); ]\n{\n\t# just sets up the condition and If Then/Else mask\n}\n\n@ifndef CDE\n:ldc^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x76 & thN6=0 & thL4=1; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_load(t_cpn,thCRd,taddrmode5);\n}\n\n:ldcl^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x76 & thN6=1 & thL4=1; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_loadlong(t_cpn,thCRd,taddrmode5);\n}\n\n:ldc2^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x7e & thN6=0 & thL4=1; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_load(t_cpn,thCRd,taddrmode5);\n}\n\n:ldc2l^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x7e & thN6=1 & thL4=1; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_loadlong(t_cpn,thCRd,taddrmode5);\n}\n@endif # CDE\n@endif # VERSION_6T2 || VERSION_7\n\n:ldmia^ItCond\tRn_exclaim,ldbrace\tis TMode=1 & ItCond & op11=0x19 & Rn_exclaim & ldbrace & Rn_exclaim_WB\n{\n build ItCond;\n build Rn_exclaim;\n build ldbrace;\n build Rn_exclaim_WB;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:ldm^ItCond^\".w\" Rn0003,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=0 & thc0404=1 & Rn0003; thc1313=0 & thldrlist_inc\n{\n build ItCond;\n mult_addr = Rn0003;\n build thldrlist_inc;\n}\n\n:ldm^ItCond^\".w\" Rn0003!,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=1 & thc0404=1 & Rn0003; thc1313=0 & thldrlist_inc\n{\n build ItCond;\n mult_addr = Rn0003;\n build thldrlist_inc;\n Rn0003 = mult_addr;\n}\n\n:ldm^ItCond Rn0003,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=0 & thc0404=1 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_inc\n{\n build ItCond;\n mult_addr = Rn0003;\n build thldrlist_inc;\n LoadWritePC(pc);\n goto [pc];\n}\n\n:ldm^ItCond^\".w\" Rn0003,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=1 & thc0404=1 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_inc\n{\n build ItCond;\n mult_addr = Rn0003;\n build thldrlist_inc;\n Rn0003 = mult_addr;\n LoadWritePC(pc);\n goto [pc];\n}\n\n\n:ldmdb^ItCond Rn0003,thldrlist_dec is TMode=1 & ItCond & op4=0xe91 & Rn0003; thc1313=0 & thldrlist_dec\n{\n build ItCond;\n mult_addr = Rn0003-4;\n build thldrlist_dec;\n}\n\n:ldmdb^ItCond Rn0003!,thldrlist_dec is TMode=1 & ItCond & op4=0xe93 & Rn0003; thc1313=0 & thldrlist_dec\n{\n build ItCond;\n mult_addr = Rn0003-4;\n build thldrlist_dec;\n Rn0003 = mult_addr + 4;\n}\n\n:ldmdb^ItCond Rn0003,thldrlist_dec is TMode=1 & ItCond & op4=0xe91 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_dec\n{\n build ItCond;\n mult_addr = Rn0003-4;\n build thldrlist_dec;\n LoadWritePC(pc);\n goto [pc];\n}\n\n:ldmdb^ItCond Rn0003,thldrlist_dec is TMode=1 & ItCond & op4=0xe93 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_dec\n{\n build ItCond;\n mult_addr = Rn0003-4;\n build thldrlist_dec;\n Rn0003 = mult_addr + 4;\n LoadWritePC(pc);\n goto [pc];\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:ldr^ItCond\tRd0002,RnIndirect4\tis TMode=1 & ItCond & op11=0xd & RnIndirect4 & Rd0002\n{\n build ItCond;\n build RnIndirect4;\n Rd0002 = *RnIndirect4;\n}\n\n:ldr^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x2c & RnRmIndirect & Rd0002\n{\n build ItCond;\n build RnRmIndirect;\n Rd0002 = *RnRmIndirect;\n}\n\n:ldr^ItCond\tRd0810,Pcrel8Indirect\tis TMode=1 & ItCond & op11=9 & Pcrel8Indirect & Rd0810\n{\n build ItCond;\n build Pcrel8Indirect;\n Rd0810 = Pcrel8Indirect;\n}\n\n # Note: NO '*' IS INTENTIONAL\n:ldr^ItCond\tRd0810,Sprel8Indirect\tis TMode=1 & ItCond & op11=0x13 & Sprel8Indirect & Rd0810\n{\n build ItCond;\n build Sprel8Indirect;\n Rd0810 = *Sprel8Indirect;\n}\n\n:ldrb^ItCond\tRd0002,RnIndirect1\tis TMode=1 & ItCond & op11=0xf & RnIndirect1 & Rd0002\n{\n build ItCond;\n build RnIndirect1;\n Rd0002 = zext( *:1 RnIndirect1 );\n}\n\n:ldrb^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x2e & RnRmIndirect & Rd0002\n{\n build ItCond;\n build RnRmIndirect;\n Rd0002 = zext( *:1 RnRmIndirect);\n}\n\n:ldrh^ItCond\tRd0002,RnIndirect2\tis TMode=1 & ItCond & op11=0x11 & RnIndirect2 & Rd0002\n{\n build ItCond;\n build RnIndirect2;\n Rd0002 = zext( *:2 RnIndirect2);\n}\n\n:ldrh^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x2d & RnRmIndirect & Rd0002\n{\n build ItCond;\n build RnRmIndirect;\n Rd0002 = zext( *:2 RnRmIndirect);\n}\n\n:ldrsb^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x2b & RnRmIndirect & Rd0002\n{\n build ItCond;\n build RnRmIndirect;\n Rd0002 = sext( *:1 RnRmIndirect);\n}\n\n:ldrsh^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x2f & RnRmIndirect & Rd0002\n{\n build ItCond;\n build RnRmIndirect;\n Rd0002 = sext( *:2 RnRmIndirect);\n}\n\ndefine pcodeop ExclusiveAccess;\n\n@if defined(VERSION_7)\n\n:ldrexb^ItCond Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; Rt1215 & thc0811=15 & thc0407=4 & thc0003=15\n{\n build ItCond;\n local tmp = Rn0003;\n ExclusiveAccess(tmp);\n val:1 = *tmp;\n Rt1215 = zext(val);\n}\n\n:ldrexh^ItCond Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; Rt1215 & thc0811=15 & thc0407=5 & thc0003=15\n{\n build ItCond;\n local tmp = Rn0003;\n ExclusiveAccess(tmp);\n val:2 = *tmp;\n Rt1215 = zext(val);\n}\n\n:ldrexd^ItCond Rt1215,Rt0811,[Rn0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; Rt1215 & Rt0811 & thc0407=7 & thc0003=15\n{\n build ItCond;\n local tmp = Rn0003;\n ExclusiveAccess(tmp);\n val1:4 = *tmp;\n val2:4 = *(tmp + 4);\n Rt1215 = val1;\n Rt0811 = val2;\n}\n\n@endif # VERSION_7\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:ldrex^ItCond Rt1215,[Rn0003,Immed8_4] is TMode=1 & ItCond & op4=0xe85 & Rn0003; Rt1215 & thc0811=15 & Immed8_4\n{\n build ItCond;\n local tmp = Rn0003 + Immed8_4;\n ExclusiveAccess(tmp);\n Rt1215 = *tmp;\n}\n\n# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first\n:ldr^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf85 & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12\n{\n build ItCond;\n build PcrelOffset12;\n Rt1215 = PcrelOffset12:4;\n build RtGotoCheck;\n}\n\n:ldr^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8d & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12\n{\n build ItCond;\n build PcrelOffset12;\n Rt1215 = PcrelOffset12:4;\n build RtGotoCheck;\n}\n\n:ldr^ItCond^\".w\"\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf8d; Rt1215 & RtGotoCheck) & RnIndirect12\n{\n build ItCond;\n build RnIndirect12;\n Rt1215 = *RnIndirect12;\n build RtGotoCheck;\n}\n\n:ldr^ItCond^\".w\"\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf85; Rt1215 & thc1111=1 & RtGotoCheck) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n Rt1215 = *RnIndirectPUW;\n build RtGotoCheck;\n}\n\n:ldr^ItCond^\".w\" Rt1215,[Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405=0 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + Rm0003;\n Rt1215 = *tmp;\n build RtGotoCheck;\n}\n\n:ldr^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n Rt1215 = *tmp;\n build RtGotoCheck;\n}\n\n:ldrb^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf81 & sop0003=15; Rt1215) & PcrelOffset12\n{\n build ItCond;\n build PcrelOffset12;\n tmp:1 = PcrelOffset12:1;\n Rt1215 = zext(tmp);\n}\n\n# overlaps patterns with the other ldrb intructions when Rn==1111, therefore it must occur first\n:ldrb^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf89 & sop0003=15; Rt1215) & PcrelOffset12\n{\n build ItCond;\n build PcrelOffset12;\n tmp:1 = PcrelOffset12:1;\n Rt1215 = zext(tmp);\n}\n\n:ldrb^ItCond^\".w\"\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf89; Rt1215) & RnIndirect12\n{\n build ItCond;\n build RnIndirect12;\n tmp:1 = *RnIndirect12;\n Rt1215 = zext(tmp);\n}\n\n:ldrb^ItCond^\".w\"\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf81; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n tmp:1 = *RnIndirectPUW;\n Rt1215 = zext(tmp);\n}\n\n:ldrb^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n val:1 = *tmp;\n Rt1215 = zext(val);\n}\n\n\n:ldrbt^ItCond^\".w\" Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n val:1 = *tmp;\n Rt1215 = zext(val);\n}\n\n\n# overlaps patterns with the other ldrd intructions when Rn==1111, therefore it must occur first\n:ldrd^ItCond Rt1215,Rt0811,Pcrel8_s8 is TMode=1 & ItCond & op9=0x74 & thc0606=1 & thc0404=1 & sop0003=15; Rt1215 & Rt0811 & Pcrel8_s8\n{\n build ItCond;\n build Pcrel8_s8;\n local val = Pcrel8_s8;\n Rt1215 = val(4);\n Rt0811 = val(0);\n}\n\n:ldrd^ItCond Rt1215,Rt0811,RnIndirectPUW1 is TMode=1 & ItCond & (op9=0x74 & thc0606=1 & thc0404=1 & Rn0003; Rt1215 & Rt0811) & $(RN_INDIRECT_PUW1)\n{\n build ItCond;\n build RnIndirectPUW1;\n Rt1215 = *RnIndirectPUW1;\n Rt0811 = *(RnIndirectPUW1+4);\n}\n\n\n# pldw must come before ldrh.w because of overlap of Rt != 1111 in ldrh.w\n:pldw^ItCond\tRn0003,\"#\"^offset12 \t\tis TMode=1 & ItCond & op6=0x3e2 & thwbit=1 & thc0404=1 & Rn0003; op12=0xf & offset12\n{\n build ItCond;\n addr:4 = Rn0003 + offset12;\n HintPreloadDataForWrite(addr);\n}\n\n:pldw^ItCond\tRn0003,\"#-\"^immed8 \t\tis TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xfc & immed8\n{\n build ItCond;\n addr:4 = Rn0003 - immed8;\n \tHintPreloadDataForWrite(addr);\n}\n\n:pldw^ItCond\tRn0003,Rm0003,\"lsl #\"^thc0405 \t\tis TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003\n{\n build ItCond;\n addr:4 = Rn0003 + (Rm0003 << thc0405);\n \tHintPreloadDataForWrite(addr);\n}\n\n\n# overlaps patterns with the other ldrh intructions when Rn==1111, therefore it must occur first\n:ldrh^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12\n{\n build ItCond;\n local tmp = PcrelOffset12:2;\n Rt1215 = zext(tmp);\n}\n:ldrh^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12\n{\n build ItCond;\n tmp:2 = PcrelOffset12:2;\n Rt1215 = zext(tmp);\n}\n\n:ldrh.w^ItCond\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf8B; Rt1215) & RnIndirect12\n{\n build ItCond;\n build RnIndirect12;\n tmp:2 = *RnIndirect12;\n Rt1215 = zext(tmp);\n}\n\n:ldrh^ItCond^\".w\"\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf83; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n tmp:2 = *RnIndirectPUW;\n Rt1215 = zext(tmp);\n}\n\n:ldrh^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n val:2 = *tmp;\n Rt1215 = zext(val);\n}\n\n:ldrht^ItCond^\".w\" Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n val:2 = *tmp;\n Rt1215 = zext(val);\n}\n\n\n# pli moevd above ldrsb to avoid conflict for ldrsb when Rt == 1111\n:pli^ItCond\tRn0003,\"#\"^offset12 \t\tis TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12\n{\n build ItCond;\n addr:4 = Rn0003 + offset12;\n HintPreloadInstruction(addr);\n}\n\n:pli^ItCond\tRn0003,\"#-\"^immed8 \t\tis TMode=1 & ItCond & op4=0xf91 & Rn0003; op8=0xfc & immed8\n{\n build ItCond;\n addr:4 = Rn0003 - immed8;\n HintPreloadInstruction(addr);\n}\n\n:pli^ItCond PcrelOffset12\t\tis TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12\n{\n build ItCond;\n HintPreloadInstruction(PcrelOffset12);\n}\n\n:pli^ItCond\tRn0003,Rm0003\"lsl #\"^thc0405 \t\tis TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003\n{\n build ItCond;\n addr:4 = Rn0003 + (Rm0003 << thc0405);\n HintPreloadInstruction(addr);\n}\n\n\n# overlaps patterns with the other ldrsb intructions when Rn==1111, therefore it must occur first\n:ldrsb^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12\n{\n build ItCond;\n tmp:1 = *PcrelOffset12;\n Rt1215 = sext(tmp);\n}\n\n:ldrsb^ItCond^\".w\"\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12\n{\n build ItCond;\n tmp:1 = *RnIndirect12;\n Rt1215 = sext(tmp);\n}\n\n:ldrsb^ItCond^\".w\"\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n tmp:1 = *RnIndirectPUW;\n Rt1215 = sext(tmp);\n}\n\n:ldrsb^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n val:1 = *tmp;\n Rt1215 = sext(val);\n}\n\n:ldrsbt^ItCond^\".w\" Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n val:1 = *tmp;\n Rt1215 = sext(val);\n}\n\n\n# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first\n:ldrsh^ItCond^\".w\" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=1 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12\n{\n build ItCond;\n build PcrelOffset12;\n tmp:2 = *PcrelOffset12;\n Rt1215 = sext(tmp);\n}\n\n:ldrsh^ItCond^\".w\"\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf9B; Rt1215) & RnIndirect12\n{\n build ItCond;\n tmp:2 = *RnIndirect12;\n Rt1215 = sext(tmp);\n}\n\n:ldrsh^ItCond^\".w\"\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf93; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n tmp:2 = *RnIndirectPUW;\n Rt1215 = sext(tmp);\n}\n\n:ldrsh^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n val:2 = *tmp;\n Rt1215 = sext(val);\n}\n\n:ldrsht^ItCond^\".w\" Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n val:2 = *tmp;\n Rt1215 = sext(val);\n}\n\n:ldrt^ItCond^\".w\" \tRt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n Rt1215 = *tmp;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\nmacro th_set_carry_for_lsl(op1,shift_count) {\n local bit = (op1 << (shift_count-1)) & 0x80000000;\n tmpCY = ((shift_count == 0) && CY) || ((shift_count != 0) && (bit != 0));\n}\n\n:lsl^CheckInIT_CZN^ItCond\tRd0002,Rm0305,Immed5\tis TMode=1 & ItCond & op11=0x0 & Immed5 & Rm0305 & Rd0002 & CheckInIT_CZN\n{\n build ItCond;\n th_set_carry_for_lsl(Rm0305,Immed5);\n Rd0002 = Rm0305 << Immed5;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n:lsl^CheckInIT_CZN^ItCond\tRd0002,Rs0305\t\tis TMode=1 & ItCond & op6=0x102 & Rs0305 & Rd0002 & CheckInIT_CZN\n{\n build ItCond;\n local shift_count = Rs0305 & 0xff;\n th_set_carry_for_lsl(Rd0002,shift_count);\n Rd0002 = Rd0002 << shift_count;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\nmacro th_set_carry_for_lsr(op1,shift_count) {\n local bit = (op1 >> (shift_count-1)) & 1;\n tmpCY = ((shift_count == 0) && CY) || ((shift_count != 0) && (bit != 0));\n}\n\n#note that this is a special case where immed5 = 0, which corresponds to a shift amount of 32\n:lsr^CheckInIT_CZN^ItCond\tRd0002,Rm0305,\"#0x20\"\tis TMode=1 & ItCond & op11=1 & Immed5 & Rm0305 & Rd0002 & immed5=0 & CheckInIT_CZN\n{\n build ItCond;\n th_set_carry_for_lsr(Rm0305,32:1);\n Rd0002 = Rm0305 >> 32;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n:lsr^CheckInIT_CZN^ItCond\tRd0002,Rm0305,Immed5\tis TMode=1 & ItCond & op11=1 & Immed5 & Rm0305 & Rd0002 & CheckInIT_CZN\n{\n build ItCond;\n local shift_amount = Immed5;\n th_set_carry_for_lsr(Rm0305,shift_amount);\n Rd0002 = Rm0305 >> Immed5;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n:lsr^CheckInIT_CZN^ItCond\tRd0002,Rs0305\t\tis TMode=1 & ItCond & op6=0x103 & Rd0002 & Rs0305 & CheckInIT_CZN\n{\n build ItCond;\n local shift_amount = (Rs0305 & 0xff);\n th_set_carry_for_lsr(Rd0002,shift_amount);\n Rd0002 = Rd0002 >> (Rs0305 & 0xff);\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:lsl^thSBIT_CZN^ItCond^\".w\" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=0 & Rm0003 & thLsbImm\n{\n build ItCond;\n th_set_carry_for_lsl(Rm0003,thLsbImm);\n Rd0811 = Rm0003 << thLsbImm;\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n:lsl^thSBIT_CZN^ItCond^\".w\" Rd0811,Rn0003,Rm0003 \t\tis TMode=1 & ItCond & op11=0x1f & thc0910=1 & sop0508=0 & thSBIT_CZN & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n local shift_amount = (Rm0003 & 0xff);\n th_set_carry_for_lsl(Rn0003,shift_amount);\n Rd0811 = Rn0003 << (shift_amount);\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n:lsr^thSBIT_CZN^ItCond^\".w\" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=1 & Rm0003 & thLsbImm\n{\n build ItCond;\n th_set_carry_for_lsr(Rm0003,thLsbImm);\n Rd0811 = Rm0003 >> thLsbImm;\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n:lsr^thSBIT_CZN^ItCond^\".w\" Rd0811,Rn0003,Rm0003 \t\tis TMode=1 & ItCond & op11=0x1f & thc0910=1 & sop0508=1 & thSBIT_CZN & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n local shift_amount = Rm0003 & 0xff;\n th_set_carry_for_lsr(Rn0003,shift_amount);\n Rd0811 = Rn0003 >> shift_amount;\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n\n@endif # VERSION_6T2 || VERSION_7\n@ifndef CDE\n:mcr^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thc0507 & thc0404=0 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thc0507;\n t_op2:4 = thopcode2;\n coprocessor_moveto(t_cpn,t_op1,t_op2,Rt1215,thCRn,thCRm);\n}\n\n:mcr2^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thc0507 & thc0404=0 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thc0507;\n t_op2:4 = thopcode2;\n coprocessor_moveto(t_cpn,t_op1,t_op2,Rt1215,thCRn,thCRm);\n}\n\n:mcrr^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xec4 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op:4 = thopcode1;\n coprocessor_moveto2(t_cpn,t_op,Rt1215,Rn0003,thCRm);\n}\n\n:mcrr^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xfc4 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op:4 = thopcode1;\n coprocessor_moveto2(t_cpn,t_op,Rt1215,Rn0003,thCRm);\n}\n@endif # CDE\n\n:mov^CheckInIT_ZN^ItCond\tRd0810,Immed8\t\tis TMode=1 & ItCond & op11=4 & Rd0810 & Immed8 & CheckInIT_ZN\n{\n build ItCond;\n Rd0810 = Immed8;\n resflags(Rd0810);\n build CheckInIT_ZN;\n}\n\n:mov^CheckInIT_ZN^ItCond\tRd0002,Rn0305\t\tis TMode=1 & ItCond & op6=0x000 & Rn0305 & Rd0002 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = Rn0305;\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n:mov^ItCond\tHrd0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x46 & Hrm0305 & Hrd0002\n{\n build ItCond;\n Hrd0002 = Hrm0305;\n}\n\n:mov^ItCond\tHrd0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x46 & Hrm0305 & Hrd0002 & hrd0002=7 & h1=1\n{\n build ItCond;\n dest:4 = Hrm0305;\n BranchWritePC(dest);\n goto [pc];\n}\n\n:mov^ItCond\tHrd0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x46 & Hrm0305 & rm0306=14 & Hrd0002 & hrd0002=7 & h1=1\n{\n build ItCond;\n dest:4 = Hrm0305;\n BranchWritePC(dest);\n return [pc];\n}\n\n:mov^ItCond\tHrd0002,Hrm0305\t\tis TMode=1 & ItCond & op8=0x46 & Hrm0305 & hrm0305=7 & Hrd0002 & hrd0002=6 & h1=1 [ LRset=1; TMode=1; globalset(inst_next,LRset); globalset(inst_next,TMode); ]\n{\n build ItCond;\n Hrd0002 = Hrm0305;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:mov^thSBIT_ZN^ItCond^\".w\"\tRd0811,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_ZN & sop0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n Rd0811 = ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n\n:movw^ItCond\tRd0811,Immed16 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=2 & thc0404=0; thc1515=0 & Rd0811) & Immed16\n{\n build ItCond;\n Rd0811 = zext(Immed16);\n resflags(Rd0811);\n}\n\n:mov^thSBIT_ZN^ItCond^\".w\"\tRd0811,Rm0003 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_ZN & sop0003=15; op12=0 & Rd0811 & thc0407=0 & Rm0003\n{\n build ItCond;\n Rd0811 = Rm0003;\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n\n:movt^ItCond\tRd0811,Immed16 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=6 & thc0404=0; thc1515=0 & Rd0811) & Immed16\n{\n build ItCond;\n Rd0811 = (zext(Immed16) << 16) | (Rd0811 & 0xffff);\n}\n\n@ifndef CDE\n:mrc^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thc0507 & thc0404=1 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thc0507;\n t_op2:4 = thopcode2;\n Rt1215 = coprocessor_movefromRt(t_cpn,t_op1,t_op2,thCRn,thCRm);\n}\n:mrc^ItCond thcpn,thc0507,\"APSR_nzcv\",thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thc0507 & thc0404=1 & thCRn; Rt1215=15 & thcpn & thopcode2 & thc0404=1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thc0507;\n t_op2:4 = thopcode2;\n local tmp:4 = coprocessor_movefromRt(t_cpn,t_op1,t_op2,thCRn,thCRm);\n writeAPSR_nzcv(tmp);\n}\n\n:mrc2^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thc0507 & thc0404=1 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thc0507;\n t_op2:4 = thopcode2;\n Rt1215 = coprocessor_movefromRt(t_cpn,t_op1,t_op2,thCRn,thCRm);\n}\n:mrc2^ItCond thcpn,thc0507,\"APSR_nzcv\",thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thc0507 & thc0404=1 & thCRn; Rt1215=15 & thcpn & thopcode2 & thc0404=1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op1:4 = thc0507;\n t_op2:4 = thopcode2;\n local tmp:4 = coprocessor_movefromRt(t_cpn,t_op1,t_op2,thCRn,thCRm);\n writeAPSR_nzcv(tmp);\n}\n\n:mrrc^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xec5 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op:4 = thopcode1;\n Rt1215 = coprocessor_movefromRt(t_cpn,t_op,thCRm);\n Rn0003 = coprocessor_movefromRt2(t_cpn,t_op,thCRm);\n}\n\n:mrrc2^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xfc5 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm\n{\n build ItCond;\n t_cpn:4 = thcpn;\n t_op:4 = thopcode1;\n Rt1215 = coprocessor_movefromRt(t_cpn,t_op,thCRm);\n Rn0003 = coprocessor_movefromRt2(t_cpn,t_op,thCRm);\n}\n@endif #CDE\n@if defined(VERSION_7M)\n\ndefine pcodeop getMainStackPointer;\ndefine pcodeop getProcessStackPointer;\ndefine pcodeop getBasePriority;\ndefine pcodeop getCurrentExceptionNumber;\n\nmrsipsr: \"i\"\tis thc0000=1 & Rd0811 { \n\tb:1 = isCurrentModePrivileged();\n\tif (!b) goto ;\n\tipsr:4 = getCurrentExceptionNumber();\n\tRd0811 = Rd0811 | (ipsr & 0x1f);\n \n}\nmrsipsr: \t\tis thc0000=0 { }\nmrsepsr: \"e\"\tis thc0101=1 { }\nmrsepsr:\t\tis thc0101=0 { }\nmrsapsr: \t\tis thc0202=1 { }\nmrsapsr: \"a\"\tis thc0202=0 & Rd0811 { readAPSR_nzcvq(Rd0811); }\n\nmrspsr: mrsipsr^mrsepsr^mrsapsr^\"psr\"\tis\tmrsipsr & mrsepsr & mrsapsr & Rd0811\t{\n\tRd0811 = 0;\n\tbuild mrsapsr;\n\tbuild mrsipsr;\n}\nmrspsr: \"xpsr\"\tis\tsysm02=3 & mrsipsr & mrsepsr & mrsapsr & Rd0811\t{\n\tRd0811 = 0;\n\tbuild mrsapsr;\n\tbuild mrsipsr;\n}\n\n:mrs^ItCond Rd0811,mrspsr \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm37=0 & mrspsr\n{\n build ItCond;\n build mrspsr;\n}\n\nmsp: \"msp\" \t\t\t\t\tis epsilon {}\n\n:mrs^ItCond Rd0811,msp \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=8 & msp\n{\n build ItCond;\n Rd0811 = getMainStackPointer();\n}\n\npsp: \"psp\" \t\t\t\t\tis epsilon {}\n\n:mrs^ItCond Rd0811,psp \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=9 & psp\n{\n build ItCond;\n Rd0811 = getProcessStackPointer();\n}\n\nprimask: \"primask\"\t\t\tis epsilon {}\n\n:mrs^ItCond Rd0811,primask \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=16 & primask\n{\n build ItCond;\n Rd0811 = 0;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next; \n Rd0811 = isIRQinterruptsEnabled(); # should reflect primask register/bit\n}\n\nbasepri: \"basepri\"\t\t\tis epsilon {}\n\n:mrs^ItCond Rd0811,basepri \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=17 & basepri\n{\n build ItCond;\n Rd0811 = 0;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n Rd0811 = getBasePriority();\n}\n\nbasepri_max: \"basepri_max\" \tis epsilon {}\n\n:mrs^ItCond Rd0811,basepri_max \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=18 & basepri_max\n{\n build ItCond;\n Rd0811 = 0;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n Rd0811 = getBasePriority();\n}\n\nfaultmask: \"faultmask\"\t\tis epsilon {}\n\n:mrs^ItCond Rd0811,faultmask \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=19 & faultmask\n{\n build ItCond;\n Rd0811 = 0;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n Rd0811 = isFIQinterruptsEnabled(); # should reflect faultmask register/bit\n}\n\ndefine pcodeop isThreadModePrivileged;\ndefine pcodeop isUsingMainStack;\n\ncontrol: \"control\" \t\t\tis epsilon {}\n\n:mrs^ItCond Rd0811,control \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=20 & control\n{\n build ItCond;\n notPrivileged:1 = isThreadModePrivileged() != 1:1;\n altStackMode:1 = isUsingMainStack() != 1:1;\n Rd0811 = zext((altStackMode << 1) | notPrivileged);\n}\n\n@endif\n\n@if defined(CORTEX)\n\ndefine pcodeop setMainStackPointerLimit;\n\n:msr^ItCond msplim,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=10 & msplim\n{\n build ItCond;\n setMainStackPointerLimit(Rn0003);\n}\n\ndefine pcodeop setProcStackPointerLimit;\n\n:msr^ItCond psplim,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=11 & psplim\n{\n build ItCond;\n setProcStackPointerLimit(Rn0003);\n}\n\ndefine pcodeop getMainStackPointerLimit;\n\n:mrs^ItCond Rd0811,msplim \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=10 & msplim\n{\n build ItCond;\n Rd0811 = getMainStackPointerLimit();\n}\n\ndefine pcodeop getProcessStackPointerLimit;\n\n:mrs^ItCond Rd0811,psplim \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=11 & psplim\n{\n build ItCond;\n Rd0811 = getProcessStackPointerLimit();\n}\n\n@endif #CORTEX\n\n:mrs^ItCond Rd0811,cpsr \t\tis TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=0 & cpsr\n{\n build ItCond;\n tmp:4 = 0;\n readAPSR_nzcvq(tmp);\n Rd0811 = tmp;\n}\n\n:mrs^ItCond Rd0811,spsr \t\tis TMode=1 & ItCond & op0=0xf3ff; op12=0x8 & Rd0811 & sysm=0 & spsr\n{\n build ItCond;\n Rd0811 = spsr;\n}\n\n\n@if defined(VERSION_7M)\n\nmsripsr: \"i\"\tis thc0000=1 { }\nmsripsr: \t\tis thc0000=0 { }\nmsrepsr: \"e\"\tis thc0101=1 { }\nmsrepsr: \t\tis thc0101=0 { }\nmsrapsr: \t\tis thc0202=1 { }\nmsrapsr: \"a\"\tis thc0202=0 & Rn0003 {\n\tcpsr = cpsr | (Rn0003 & 0xf8000000);\n\twriteAPSR_nzcvq(cpsr);\n}\n\nmsrpsr: msripsr^msrepsr^msrapsr^\"psr\"\tis\tmsripsr & msrepsr & msrapsr\t{\n\tbuild msrapsr;\n}\nmsrpsr: \"xpsr\"\tis\tsysm02=3 & msrapsr\t{\n\tbuild msrapsr;\n}\n\n:msr^ItCond msrpsr,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm37=0 & msrpsr\n{\n build ItCond;\n build msrpsr;\n}\n\ndefine pcodeop setMainStackPointer;\ndefine pcodeop setProcessStackPointer;\ndefine pcodeop setBasePriority;\n\n:msr^ItCond msp,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=8 & msp\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n setMainStackPointer(Rn0003);\n}\n\n:msr^ItCond psp,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=9 & psp\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n setProcessStackPointer(Rn0003);\n}\n\n:msr^ItCond primask,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=16 & primask\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n enableIRQinterrupts((Rn0003 & 1) == 1); # should set/clear primask register/bit\n}\n\n:msr^ItCond basepri,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=17 & basepri\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n setBasePriority(Rn0003);\n}\n\n:msr^ItCond basepri_max,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=18 & basepri_max\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n if (Rn0003 == 0) goto inst_next;\n# TODO: does the following compare need to be signed??\n cur:4 = getBasePriority();\n if (cur != 0 && Rn0003 >= cur) goto inst_next;\n setBasePriority(Rn0003);\n}\n\n:msr^ItCond faultmask,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=19 & faultmask\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n enableFIQinterrupts((Rn0003 & 1) == 1);\n}\n\ndefine pcodeop setStackMode;\n\n:msr^ItCond control,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=20 & control\n{\n build ItCond;\n b:1 = isCurrentModePrivileged();\n if (!b) goto inst_next;\n privileged:1 = (Rn0003 & 1) == 0;\n setThreadModePrivileged(privileged);\n# TODO: not sure about the following semantics \n b = isThreadMode();\n if (!b) goto inst_next;\n stackMode:1 = isUsingMainStack() == 1:1;\n setStackMode(stackMode);\n# TODO: should we set sp ?\n}\n\n@endif\n\nthpsrmask:\t\t\tis th_psrmask=0\t{ export 0:4; }\nthpsrmask: \"_c\"\t\tis th_psrmask=1\t{ export 0xff:4; }\nthpsrmask: \"_x\"\t\tis th_psrmask=2\t{ export 0xff00:4; }\nthpsrmask: \"_cx\"\tis th_psrmask=3\t{ export 0xffff:4; }\nthpsrmask: \"_s\"\t\tis th_psrmask=4\t{ export 0xff0000:4; }\nthpsrmask: \"_cs\"\tis th_psrmask=5\t{ export 0xff00ff:4; }\nthpsrmask: \"_xs\"\tis th_psrmask=6\t{ export 0xffff00:4; }\nthpsrmask: \"_cxs\"\tis th_psrmask=7\t{ export 0xffffff:4; }\nthpsrmask: \"_f\"\t\tis th_psrmask=8\t{ export 0xff000000:4; }\nthpsrmask: \"_cf\"\tis th_psrmask=9\t{ export 0xff0000ff:4; }\nthpsrmask: \"_xf\"\tis th_psrmask=10\t{ export 0xff00ff00:4; }\nthpsrmask: \"_cxf\"\tis th_psrmask=11\t{ export 0xff00ffff:4; }\nthpsrmask: \"_sf\"\tis th_psrmask=12\t{ export 0xffff0000:4; }\nthpsrmask: \"_csf\"\tis th_psrmask=13\t{ export 0xffff00ff:4; }\nthpsrmask: \"_xsf\"\tis th_psrmask=14\t{ export 0xffffff00:4; }\nthpsrmask: \"_cxsf\"\tis th_psrmask=15\t{ export 0xffffffff:4; }\n\nthcpsrmask: cpsr^thpsrmask\tis thpsrmask & cpsr { export thpsrmask; }\n\n:msr^ItCond thcpsrmask,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & thcpsrmask & thc0007=0\n{\n build ItCond;\n build thcpsrmask;\n cpsr = (cpsr& ~thcpsrmask) | (Rn0003 & thcpsrmask);\n writeAPSR_nzcvq(cpsr);\n}\n\nthspsrmask: spsr^thpsrmask\tis thpsrmask & spsr { export thpsrmask; }\n\n:msr^ItCond thspsrmask,Rn0003 \t\tis TMode=1 & ItCond & op4=0xf39 & Rn0003; op12=0x8 & thspsrmask & thc0007=0\n{\n build ItCond;\n build thspsrmask;\n spsr = (spsr& ~thspsrmask) | (Rn0003 & thspsrmask);\n}\n\n:mvn^thSBIT_ZN^ItCond Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n Rd0811 = ~ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n\n:mvn^thSBIT_ZN^ItCond^\".w\" Rd0811,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n Rd0811 = ~thshift2;\n resflags(Rd0811);\n build thSBIT_ZN;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:mul^CheckInIT_ZN^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x10d & Rm0305 & Rd0002 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = Rm0305 * Rd0002;\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:mla^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb0 & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n Rd0811 = Rn0003 * Rm0003 + Ra1215;\n}\n\n:mls^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb0 & Rn0003; Ra1215 & Rd0811 & sop0407=1 & Rm0003\n{\n build ItCond;\n Rd0811 = Ra1215- Rn0003 * Rm0003;\n}\n\n:mul^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb0 & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n Rd0811 = Rn0003 * Rm0003;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:mvn^CheckInIT_ZN^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x10f & Rm0305 & Rd0002 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = ~Rm0305;\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n:nop^ItCond is TMode=1 & ItCond & op0=0xbf00\n{\n}\n\n:nop^ItCond^\".w\" is TMode=1 & ItCond & op0=0xf3af; op0=0x8000\n{\n}\n\n:nop\tis op0=0x46c0 # This is just like a mov r0 r0\n{\n}\n\n:orr^CheckInIT_ZN^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x10c & Rm0305 & Rd0002 & CheckInIT_ZN\n{\n build ItCond;\n Rd0002 = Rd0002 | Rm0305;\n resflags(Rd0002);\n build CheckInIT_ZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:orn^thSBIT_CZNO^ItCond\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n Rd0811 = Rn0003 | ~(ThumbExpandImm12);\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:orn^thSBIT_CZNO^ItCond^\".w\" Rd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=3 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n Rd0811 = Rn0003 | ~(thshift2);\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:orr^thSBIT_CZNO^ItCond\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n Rd0811 = Rn0003 | ThumbExpandImm12;\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:orr^thSBIT_CZNO^ItCond^\".w\" Rd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n Rd0811 = Rn0003 | thshift2;\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:pkhbt^ItCond^\".w\" Rd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op4=0xeac & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thc0404=0 & thshift2\n{\n build ItCond;\n Rd0811 = (Rn0003 & 0x0000ffff) | (thshift2 & 0xffff0000);\n th_logicflags();\n resflags(Rd0811);\n}\n\n:pkhtb^ItCond^\".w\" Rd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op4=0xeac & Rn0003; thc1515=0 & Rd0811 & thc0505=1 & thc0404=0 & thshift2\n{\n build ItCond;\n Rd0811 = (Rn0003 & 0xffff0000) | (thshift2 & 0x0000ffff);\n th_logicflags();\n resflags(Rd0811);\n}\n\n:pld^ItCond\tRn0003,\"#\"^offset12 \t\tis TMode=1 & ItCond & op6=0x3e2 & thwbit=0 & thc0404=1 & Rn0003; op12=0xf & offset12\n{\n build ItCond;\n addr:4 = Rn0003 + offset12;\n HintPreloadData(addr);\n}\n\n\n:pld^ItCond\tRn0003,\"#-\"^immed8 \t\tis TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xfc & immed8\n{\n build ItCond;\n addr:4 = Rn0003 - immed8;\n HintPreloadData(addr);\n}\n\n:pld^ItCond PcrelOffset12\t\tis TMode=1 & ItCond & (op8=0xf8 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12\n{\n build ItCond;\n HintPreloadData(PcrelOffset12);\n}\n\n:pld^ItCond\tRn0003,Rm0003\"lsl #\"^thc0405 \t\tis TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003\n{\n build ItCond;\n addr:4 = Rn0003 + (Rm0003 << thc0405);\n HintPreloadData(addr);\n}\n\n# pld.w moved above ldrh to avoid conflicts\n\n#pli moved above ldrsb\n\n\n@endif # VERSION_6T2 || VERSION_7\n\n#\n# Removed the masking of the stack pointer on push and pop to ignore the lower 2 bits.\n# This isn't really needed for modeling.\n# NOTE: It may need to be put back in to model correctly for nasty stack shenanigans.\n#\n:pop^ItCond\tldbrace\t\t\tis TMode=1 & ItCond & op9=0x5e & R=0 & ldbrace\n{\n build ItCond;\n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp;\n build ldbrace;\n sp = mult_addr;\n}\n\n:pop^ItCond\tpclbrace\t\tis TMode=1 & ItCond & op9=0x5e & R=1 & pclbrace\n{\n build ItCond;\n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp;\n build pclbrace;\n sp = mult_addr;\n LoadWritePC(pc);\n return [pc];\n}\n\n:pop^ItCond thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thldrlist_inc\n{\n build ItCond;\n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp;\n\tbuild thldrlist_inc;\n\tsp = mult_addr;\n}\n\n:pop^ItCond thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thldrlist_inc & thc1515=1\n{\n build ItCond;\n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp;\n\tbuild thldrlist_inc;\n\tsp = mult_addr;\n\tLoadWritePC(pc);\n\treturn [pc];\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:pop^ItCond^\".w\" thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thc1515=0 & thc1313=0 & thldrlist_inc\n{\n build ItCond;\n mult_addr = sp;\n build thldrlist_inc;\n sp = mult_addr;\n}\n\n:pop^ItCond^\".w\" Rt1215 is TMode=1 & ItCond & op0=0xf85d; Rt1215 & offset12=0xb04\n{\n build ItCond;\n Rt1215 = *sp;\n sp=sp+4;\n}\n\n:pop^ItCond^\".w\" thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thc1515=1 & thc1313=0 & thldrlist_inc\n{\n build ItCond;\n mult_addr = sp;\n build thldrlist_inc;\n sp = mult_addr;\n LoadWritePC(pc);\n return [pc];\n}\n\n:pop^ItCond^\".w\" Rt1215 is TMode=1 & ItCond & op0=0xf85d; Rt1215 & op12=15 & offset12=0xb04\n{\n build ItCond;\n dest:4 = *sp;\n sp=sp+4;\n LoadWritePC(dest);\n return [pc];\n}\n\n:push^ItCond^\".w\" thstrlist_dec is TMode=1 & ItCond & op0=0xe8ad; thc1515=0 & thc1313=0 & thstrlist_dec\n{\n build ItCond;\n mult_addr = sp-4;\n build thstrlist_dec;\n sp = mult_addr + 4;\n}\n\n:push^ItCond^\".w\" Rt1215 is TMode=1 & ItCond & op0=0xf84d; Rt1215 & offset12=0xd04\n{\n build ItCond;\n sp=sp-4;\n *sp = Rt1215;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:push^ItCond\tpsbrace\t\t\tis TMode=1 & ItCond & op9=0x5a & R=0 & psbrace\n{\n build ItCond;\n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp;\n build psbrace;\n sp = mult_addr;\n}\n\n:push^ItCond\tpcpbrace\t\tis TMode=1 & ItCond & op9=0x5a & R=1 & pcpbrace\n{\n build ItCond;\n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp;\n build pcpbrace;\n sp = mult_addr;\n}\n\n:push^ItCond thstrlist_dec is TMode=1 & ItCond & op0=0xe92d; thstrlist_dec\n{\n build ItCond; \n#\tmult_addr = sp & 0xfffffffc;\n mult_addr = sp-4;\n\tbuild thstrlist_dec;\n\tsp = mult_addr+4;\n}\n\n@if defined(VERSION_5E)\n\n:qadd^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x8 & Rm0003\n{\n build ItCond;\n local sum1 = Rm0003 + Rn0003;\n sum1 = SignedSaturate(sum1,32:2);\n Q = SignedDoesSaturate(sum1,32:2);\n Rd0811 = sum1;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:qadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003\n{\n build ItCond;\n local lRn = Rn0003 & 0xffff;\n local lRm = Rm0003 & 0xffff;\n local uRn = (Rn0003) & 0xffff;\n local uRm = (Rm0003 >> 16) & 0xffff;\n sum1:2 = lRn:2 + lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 + uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd0811 = (zext(sum2) << 16) | zext(sum1);\n}\n\n:qadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003\n{\n build ItCond;\n local rn1 = Rn0003 & 0xff;\n local rm1 = Rm0003 & 0xff;\n local rn2 = (Rn0003 >> 8) & 0xff;\n local rm2 = (Rm0003 >> 8) & 0xff;\n local rn3 = (Rn0003 >> 16) & 0xff;\n local rm3 = (Rm0003 >> 16) & 0xff;\n local rn4 = (Rn0003 >> 24) & 0xff;\n local rm4 = (Rm0003 >> 24) & 0xff;\n sum1:1 = rn1:1 + rm1:1;\n sum1 = SignedSaturate(sum1,8:2);\n sum2:1 = rn2:1 + rm2:1;\n sum2 = SignedSaturate(sum2,8:2);\n sum3:1 = rn3:1 + rm3:1;\n sum3 = SignedSaturate(sum3,8:2);\n sum4:1 = rn4:1 + rm4:1;\n sum4 = SignedSaturate(sum4,8:2);\n Rd0811 = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n# qaddsubx\n:qasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003\n{\n build ItCond;\n local lRn = Rn0003 & 0xffff;\n local lRm = Rm0003 & 0xffff;\n local uRn = (Rn0003 >> 16) & 0xffff;\n local uRm = (Rm0003 >> 16) & 0xffff;\n sum1:2 = lRn:2 - lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 + uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd0811 = (zext(sum2) << 16) | zext(sum1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:qdadd^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x9 & Rm0003\n{\n build ItCond;\n tmp:4 = Rn0003 * 2;\n tmp = SignedSaturate(tmp,32:2);\n Q = SignedDoesSaturate(tmp,32:2);\n tmp = tmp + Rm0003;\n tmp = SignedSaturate(tmp,32:2);\n Q = Q | SignedDoesSaturate(tmp,32:2);\n Rd0811 = tmp;\n}\n\n:qdsub^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0xb & Rm0003\n{\n build ItCond;\n tmp:4 = Rn0003 * 2;\n tmp = SignedSaturate(tmp);\n Q = SignedDoesSaturate(tmp,32:2);\n tmp = Rm0003 - tmp;\n tmp = SignedSaturate(tmp,32:2);\n Q = Q | SignedDoesSaturate(tmp,32:2);\n Rd0811 = tmp;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n# qsubaddx\n:qsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003\n{\n build ItCond;\n local lRn = Rn0003 & 0xffff;\n local lRm = Rm0003 & 0xffff;\n local uRn = (Rn0003 >> 16) & 0xffff;\n local uRm = (Rm0003 >> 16) & 0xffff;\n sum1:2 = lRn:2 + lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 - uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd0811 = (zext(sum2) << 16) | zext(sum1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:qsub^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0xa & Rm0003\n{\n build ItCond;\n tmp:4 = Rm0003 - Rn0003;\n tmp = SignedSaturate(tmp,32:2);\n Q = SignedDoesSaturate(tmp,32:2);\n Rd0811 = tmp;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:qsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003\n{\n build ItCond;\n local lRn = Rn0003 & 0xffff;\n local lRm = Rm0003 & 0xffff;\n local uRn = (Rn0003 >> 16) & 0xffff;\n local uRm = (Rm0003 >> 16) & 0xffff;\n sum1:2 = lRn:2 - lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 - uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd0811 = (zext(sum2) << 16) | zext(sum1);\n}\n\n:qsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003\n{\n build ItCond;\n local rn1 = Rn0003 & 0xff;\n local rm1 = Rm0003 & 0xff;\n local rn2 = (Rn0003 >> 8) & 0xff;\n local rm2 = (Rm0003 >> 8) & 0xff;\n local rn3 = (Rn0003 >> 16) & 0xff;\n local rm3 = (Rm0003 >> 16) & 0xff;\n local rn4 = (Rn0003 >> 24) & 0xff;\n local rm4 = (Rm0003 >> 24) & 0xff;\n sum1:1 = rn1:1 - rm1:1;\n sum1 = SignedSaturate(sum1,8:2);\n sum2:1 = rn2:1 - rm2:1;\n sum2 = SignedSaturate(sum2,8:2);\n sum3:1 = rn3:1 - rm3:1;\n sum3 = SignedSaturate(sum3,8:2);\n sum4:1 = rn4:1 - rm4:1;\n sum4 = SignedSaturate(sum4,8:2);\n Rd0811 = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n@endif # VERSION_6\n\n@if defined(THUMB_2)\n\n# WARNING Rm0003 on the first 2 bytes must be the same value as Rm0003 on the last bytes!\n# but there is no easy way to check this now...\n:rev^ItCond Rd0811,Rm0003 is TMode=1 & ItCond & op4=0xfa9; op6=0x2e8 & Rd0811 & Rm0003\n{\n build ItCond;\n local tmp1 = Rm0003 & 0xff;\n local tmp2 = (Rm0003 >> 8) & 0xff;\n local tmp3 = (Rm0003 >> 16) & 0xff;\n local tmp4 = (Rm0003 >> 24) & 0xff;\n Rd0811 = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4;\n}\n\n@endif # THUMB_2\n\n:rsb^CheckInIT_CZNO^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x109 & Rm0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_subflags0(Rm0305);\n Rd0002 = 0-Rm0305;\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n@if defined(VERSION_6)\n\n:rev^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x2e8 & Rd0002 & Rm0305\n{\n build ItCond;\n local tmp1 = Rm0305 & 0xff;\n local tmp2 = (Rm0305 >> 8) & 0xff;\n local tmp3 = (Rm0305 >> 16) & 0xff;\n local tmp4 = (Rm0305 >> 24) & 0xff;\n Rd0002 = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4;\n}\n\n:rev16^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x2e9 & Rd0002 & Rm0305\n{\n build ItCond;\n local tmp1 = Rm0305 & 0xff;\n local tmp2 = (Rm0305 >> 8) & 0xff;\n local tmp3 = (Rm0305 >> 16) & 0xff;\n local tmp4 = (Rm0305 >> 24) & 0xff;\n Rd0002 = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | tmp2;\n}\n\n:revsh^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x2eb & Rd0002 & Rm0305\n{\n build ItCond;\n local tmp1 = Rm0305 & 0xff;\n local tmp2 = (Rm0305 >> 8) & 0xff;\n local result = (tmp1 << 8) | tmp2;\n Rd0002 = sext(result:2);\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nmacro BitReverse(val) {\n tval:1 = val;\n result:1 = 0;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n val = result;\n}\n\n:rbit^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=0xa & Rn0003\n{\n build ItCond;\n t:4 = Rm0003 & 0xff;\n b1:1 = t:1;\n t = (Rm0003 >> 8) & 0xff;\n b2:1 = t:1;\n t = (Rm0003 >> 16) & 0xff;\n b3:1 = t:1;\n t = (Rm0003 >> 24) & 0xff;\n b4:1 = t:1;\n BitReverse(b1);\n BitReverse(b2);\n BitReverse(b3);\n BitReverse(b4);\n Rd0811 = (zext(b1) << 24) | (zext(b2) << 16) | (zext(b3) << 8) | zext(b4);\n}\n\n:rev^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=8 & Rn0003\n{\n build ItCond;\n local tmp1 = Rm0003 & 0xff;\n local tmp2 = (Rm0003 >> 8) & 0xff;\n local tmp3 = (Rm0003 >> 16) & 0xff;\n local tmp4 = (Rm0003 >> 24) & 0xff;\n Rd0811 = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4;\n}\n\n:rev16^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=9 & Rn0003\n{\n build ItCond;\n local tmp1 = Rm0003 & 0xff;\n local tmp2 = (Rm0003 >> 8) & 0xff;\n local tmp3 = (Rm0003 >> 16) & 0xff;\n local tmp4 = (Rm0003 >> 24) & 0xff;\n Rd0811 = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | tmp2;\n}\n\n:revsh^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=0xb & Rn0003\n{\n build ItCond;\n local tmp1 = Rm0003 & 0xff;\n local tmp2 = (Rm0003 >> 8) & 0xff;\n local result = (tmp1 << 8) | tmp2;\n Rd0811 = sext(result:2);\n}\n\n# RFE instructions for Thumb-2 \"Encoding T1\" and \"Encoding T2\" on page 1574\n#\n:rfedb\tpart2Rd0003\tis TMode=1 & part2c0615=0x3a0 & part2c0505=0x0 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000\n{\n # register list is always: pc, cpsr\n ptr:4 = part2Rd0003 - 4;\n cpsr = *ptr;\n ptr = ptr - 4;\n dest:4 = *ptr;\n BranchWritePC(dest);\n return [pc];\n}\n\n:rfedb\tpart2Rd0003^\"!\"\tis TMode=1 & part2c0615=0x3a0 & part2c0505=0x1 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000\n{\n # register list is always: pc, cpsr\n ptr:4 = part2Rd0003 - 4;\n cpsr = *ptr;\n ptr = ptr - 4;\n dest:4 = *ptr;\n part2Rd0003 = ptr;\n BranchWritePC(dest);\n return [pc];\n}\n\n:rfeia\tpart2Rd0003\tis TMode=1 & part2c0615=0x3a6 & part2c0505=0x0 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000\n{\n # register list is always: pc, cpsr\n ptr:4 = part2Rd0003;\n cpsr = *ptr;\n ptr = ptr + 4;\n dest:4 = *ptr;\n BranchWritePC(dest);\n return [pc];\n}\n\n:rfeia\tpart2Rd0003^\"!\"\tis TMode=1 & part2c0615=0x3a6 & part2c0505=0x1 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000\n{\n # register list is always: pc, cpsr\n ptr:4 = part2Rd0003;\n cpsr = *ptr;\n ptr = ptr + 4;\n dest:4 = *ptr;\n part2Rd0003 = ptr + 4;\n BranchWritePC(dest);\n return [pc];\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n\n:rsb^thSBIT_CZNO^ItCond^\".w\" Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=14 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n th_subflags(ThumbExpandImm12,Rn0003);\n Rd0811 = ThumbExpandImm12 - Rn0003;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:rsb^thSBIT_CZNO^ItCond Rd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=14 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n th_subflags(thshift2,Rn0003);\n Rd0811 = thshift2 - Rn0003;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n@endif # VERSION_6\n\nmacro th_set_carry_for_ror(result, count) {\n local bit = result & 0x80000000;\n tmpCY = ((count == 0) && CY) || ((count != 0) && (bit != 0));\n}\n\n:ror^CheckInIT_CZN^ItCond\tRd0002,Rs0305\t\tis TMode=1 & ItCond & op6=0x107 & Rs0305 & Rd0002 & CheckInIT_CZN\n{\n build ItCond;\n local shift_amount = Rs0305 & 0x1f;\n local tmp = (Rd0002 >> shift_amount)|(Rd0002 << (32-shift_amount));\n th_set_carry_for_ror(tmp,Rs0305 & 0xff);\n Rd0002 = tmp;\n resflags(Rd0002);\n build CheckInIT_CZN;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:ror^thSBIT_CZN^ItCond Rd0811,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & thc0003=0xf; thc1515=0 & Rd0811 & thc0405=3 & thshift2\n{\n build ItCond;\n Rd0811 = thshift2;\n tmpCY = shift_carry;\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n:ror^thSBIT_CZN^ItCond^\".w\" Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op8=0xfa & thc0707=0 & thc0506=3 & thSBIT_CZN & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n local shift_amount = Rm0003 & 0x1f;\n local tmp = (Rn0003>>shift_amount)|(Rn0003<<(32-shift_amount)); \n th_set_carry_for_ror(tmp,Rm0003 & 0xff);\n Rd0811 = tmp;\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n:rrx^thSBIT_CZN^ItCond Rd0811,Rm0003 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & thc0003=0xf; thc1515=0 & thc1214=0 & Rd0811 & thc0607=0 & thc0405=3 & Rm0003\n{\n build ItCond;\n local tmp1=Rm0003&1;\n shift_carry=tmp1(0);\n local tmp2 = (zext(CY)<<31)|(Rm0003>>1);\n Rd0811 = tmp2;\n th_logicflags();\n resflags(Rd0811);\n build thSBIT_CZN;\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:sadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n local tmpRn0003 = Rn0003;\n sum1:4 = sext(tmpRn0003[ 0,16]) + sext(tmpRm0003[ 0,16]);\n sum2:4 = sext(tmpRn0003[16,16]) + sext(tmpRm0003[16,16]);\n Rd0811[ 0,16] = sum1:2;\n Rd0811[16,16] = sum2:2;\n GE1 = sum1 s>= 0;\n GE2 = sum1 s>= 0;\n GE3 = sum2 s>= 0;\n GE4 = sum2 s>= 0;\n}\n\n:sadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n local tmpRn0003 = Rn0003;\n sum1:4 = sext(tmpRn0003[ 0,8]) + sext(tmpRm0003[ 0,8]);\n sum2:4 = sext(tmpRn0003[ 8,8]) + sext(tmpRm0003[ 8,8]);\n sum3:4 = sext(tmpRn0003[16,8]) + sext(tmpRm0003[16,8]);\n sum4:4 = sext(tmpRn0003[24,8]) + sext(tmpRm0003[24,8]);\n Rd0811[ 0,8] = sum1:1;\n Rd0811[ 8,8] = sum2:1;\n Rd0811[16,8] = sum3:1;\n Rd0811[24,8] = sum4:1;\n GE1 = sum1 s>= 0;\n GE2 = sum2 s>= 0;\n GE3 = sum3 s>= 0;\n GE4 = sum4 s>= 0;\n}\n\n:sasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n local tmpRn0003 = Rn0003;\n diff:4 = sext(tmpRn0003[ 0,16]) - sext(tmpRm0003[16,16]);\n sum:4 = sext(tmpRn0003[16,16]) + sext(tmpRm0003[ 0,16]);\n Rd0811[ 0,16] = diff[ 0,16];\n Rd0811[16,16] = sum[ 0,16];\n GE1 = diff s>= 0;\n GE2 = diff s>= 0;\n GE3 = sum s>= 0;\n GE4 = sum s>= 0;\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n:sbc^CheckInIT_CZNO^ItCond\tRd0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x106 & Rm0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_sub_with_carry_flags(Rd0002,Rm0305);\n Rd0002 = Rd0002 - Rm0305 - zext(!CY);\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:sbc^thSBIT_CZNO^ItCond\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=11 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n th_sub_with_carry_flags(Rn0003,ThumbExpandImm12);\n Rd0811 = Rn0003 - ThumbExpandImm12 - zext(!CY);\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:sbc^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=11 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n th_sub_with_carry_flags(Rn0003,thshift2);\n Rd0811 = Rn0003 - thshift2 - zext(!CY);\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:sbfx^ItCond\tRd0811,Rn0003,thLsbImm,thWidthMinus1 \t\tis TMode=1 & ItCond & op4=0xf34 & Rn0003; thc1515=0 & Rd0811 & thLsbImm & thWidthMinus1\n{\n build ItCond;\n\tbuild thLsbImm;\n\tbuild thWidthMinus1;\n\tshift:4 = 31 - (thLsbImm + thWidthMinus1); # thMsbImm represents widthMinus1\n\tRd0811 = Rn0003 << shift;\n\tshift = 31 - thWidthMinus1; # msbImm represents widthMinus1\n\tRd0811 = Rd0811 s>> shift;\n}\n\n:sdiv^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb9 & Rn0003; op12=0xf & Rd0811 & thc0407=0xf & Rm0003\n{\n build ItCond;\n local result = Rn0003 s/ Rm0003;\n Rd0811 = result;\n}\n\n:sel^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x8 & Rm0003\n{\n build ItCond;\n Rd0811[ 0,8] = ((GE1 == 1) * Rn0003[ 0,8]) + ((GE1 == 0) * Rm0003[ 0,8]);\n Rd0811[ 8,8] = ((GE2 == 1) * Rn0003[ 8,8]) + ((GE2 == 0) * Rm0003[ 8,8]);\n Rd0811[16,8] = ((GE3 == 1) * Rn0003[16,8]) + ((GE3 == 0) * Rm0003[16,8]);\n Rd0811[24,8] = ((GE4 == 1) * Rn0003[24,8]) + ((GE4 == 0) * Rm0003[24,8]);\n}\n\n:shadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003\n{\n build ItCond;\n sum1:4 = sext(Rn0003[ 0,16]) + sext(Rm0003[ 0,16]);\n sum2:4 = sext(Rn0003[16,16]) + sext(Rm0003[16,16]);\n Rd0811[ 0,16] = sum1[1,16];\n Rd0811[16,16] = sum2[1,16];\n}\n\n:shadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003\n{\n build ItCond;\n sum1:4 = sext(Rn0003[ 0,8]) + sext(Rm0003[ 0,8]);\n sum2:4 = sext(Rn0003[ 8,8]) + sext(Rm0003[ 8,8]);\n sum3:4 = sext(Rn0003[16,8]) + sext(Rm0003[16,8]);\n sum4:4 = sext(Rn0003[24,8]) + sext(Rm0003[24,8]);\n Rd0811[ 0,8] = sum1[1,8];\n Rd0811[ 8,8] = sum2[1,8];\n Rd0811[16,8] = sum3[1,8];\n Rd0811[24,8] = sum4[1,8];\n}\n\n:shasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003\n{\n build ItCond;\n diff:4 = sext(Rn0003[ 0,16]) - sext(Rm0003[16,16]);\n sum:4 = sext(Rn0003[16,16]) + sext(Rm0003[ 0,16]);\n Rd0811[ 0,16] = diff[1,16];\n Rd0811[16,16] = sum[1,16];\n}\n\n:shsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003\n{\n build ItCond;\n sum:4 = sext(Rn0003[ 0,16]) + sext(Rm0003[16,16]);\n diff:4 = sext(Rn0003[16,16]) - sext(Rm0003[ 0,16]);\n Rd0811[ 0,16] = sum[1,16];\n Rd0811[16,16] = diff[1,16];\n}\n\n:shsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003\n{\n build ItCond;\n diff1:4 = sext(Rn0003[ 0,16]) - sext(Rm0003[ 0,16]);\n diff2:4 = sext(Rn0003[16,16]) - sext(Rm0003[16,16]);\n Rd0811[ 0,16] = diff1[1,16];\n Rd0811[16,16] = diff2[1,16];\n}\n\n:shsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003\n{\n build ItCond;\n diff1:4 = sext(Rn0003[ 0,8]) - sext(Rm0003[ 0,8]);\n diff2:4 = sext(Rn0003[ 8,8]) - sext(Rm0003[ 8,8]);\n diff3:4 = sext(Rn0003[16,8]) - sext(Rm0003[16,8]);\n diff4:4 = sext(Rn0003[24,8]) - sext(Rm0003[24,8]);\n Rd0811[ 0,8] = diff1[1,8];\n Rd0811[ 8,8] = diff2[1,8];\n Rd0811[16,8] = diff3[1,8];\n Rd0811[24,8] = diff4[1,8];\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\nthXBIT: \"b\" is Rn0003 ; thc0505=0 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003:2; export tmp_x; }\nthXBIT: \"t\" is Rn0003 ; thc0505=1 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003(2); export tmp_x; }\n\nthYBIT: \"b\" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp_y:2 = tmpRm0003:2; export tmp_y; }\nthYBIT: \"t\" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp_y:2 = tmpRm0003(2); export tmp_y; }\n\n:smla^thXBIT^thYBIT^ItCond Rd0811,Rn0003,Rm0003,Rt1215 is TMode=1 & ItCond & (op4=0xfb1 & Rn0003; Rt1215 & Rd0811 & thc0607=0 & thYBIT & Rm0003) & thXBIT\n{\n\tbuild ItCond;\n\ttmp:4 = sext(thXBIT) * sext(thYBIT);\n\tQ = scarry(tmp,Rt1215) || Q; #Q flag is never cleared by this instruction\n\tRd0811 = tmp + Rt1215;\n}\n\nthdXbot: \"\" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003:2; export tmp; }\nthdXbot: \"X\" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003(2); export tmp; }\n\nthdXtop: \"\" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003(2); export tmp; }\nthdXtop: \"X\" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003:2; export tmp; }\n\n:smlad^thdXbot^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb2 & Rn0003; Ra1215 & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\trnbot:2 = tmpRn0003:2;\n\trntop:2 = tmpRn0003(2);\n\ttmpbot:4 = sext(rnbot) * sext(thdXbot);\n\ttmptop:4 = sext(rntop) * sext(thdXtop);\n\ttmp:4 = sext(tmpbot) + sext(tmptop);\n\tQ = scarry(tmp,Ra1215) || Q; #Q flag is never cleared by this instruction\n Rd0811 = tmp + Ra1215;\n}\n\n:smlald^thdXbot^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbc & Rn0003; Rt1215 & Rd0811 & thc0507=6 & thdXbot & thdXtop & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\trnbot:2 = tmpRn0003:2;\n\trntop:2 = tmpRn0003(2);\n\ttmpbot:4 = sext(rnbot) * sext(thdXbot);\n\ttmptop:4 = sext(rntop) * sext(thdXtop);\n\taccum:8 = (sext(Rd0811) << 32) | zext(Rt1215);\n\ttmp:8 = sext(tmpbot) + sext(tmptop);\n\taccum = tmp + accum;\n Rt1215 = accum:4;\n Rd0811 = accum(4);\n}\n\n:smlal^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbc & Rn0003; Rt1215 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n accum:8 = (sext(Rd0811) << 32) | zext(Rt1215);\n val:8 = sext(Rn0003) * sext(Rm0003) + accum;\n Rt1215 = val(0);\n Rd0811 = val(4);\n}\n\n:smlal^thXBIT^thYBIT^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & (op4=0xfbc & Rn0003; Rt1215 & Rd0811 & thc0607=2 & thYBIT & Rm0003) & thXBIT\n{\n build ItCond;\n tmp:4 = sext(thXBIT) * sext(thYBIT);\n accum:8 = (zext(Rd0811) << 32) | zext(Rt1215);\n val:8 = sext(tmp) + accum;\n Rt1215 = val(0);\n Rd0811 = val(4);\n}\n\n:smlaw^thYBIT^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb3 & Rn0003; Ra1215 & Rd0811 & thc0507=0 & thYBIT & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmp:6 = (sext(Rn0003) * sext(thYBIT));\n\tlocal addend:6 = sext(Ra1215) << 16;\n\tQ = scarry(tmp,addend) || Q; #this instruction never clears the Q flag\n\ttmp = tmp + addend;\n\tRd0811 = tmp(2);\n}\n\n:smlsd^thdXbot^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb4 & Rn0003; Ra1215 & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal rnbot:2 = tmpRn0003:2;\n\tlocal rntop:2 = tmpRn0003(2);\n\tlocal prod1:4 = sext(rnbot) * sext(thdXbot);\n\tlocal prod2:4 = sext(rntop) * sext(thdXtop);\n\tlocal diff = prod1 - prod2;\n\tQ = scarry(diff,Ra1215) || Q; #instruction never clears Q flag\n\tRd0811 = diff + Ra1215;\n}\n\n:smlsld^thdXbot^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbd & Rn0003; Rt1215 & Rd0811 & thc0507=6 & thdXbot & thdXtop & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal rnbot:2 = tmpRn0003:2;\n\tlocal rntop:2 = tmpRn0003(2);\n\tlocal tmpbot:4 = sext(rnbot) * sext(thdXbot);\n\tlocal tmptop:4 = sext(rntop) * sext(thdXtop);\n\tlocal accum:8 = (sext(Rd0811) << 32) | zext(Rt1215);\n\tlocal tmp:8 = sext(tmpbot) - sext(tmptop);\n\taccum = tmp + accum;\n Rt1215 = accum:4;\n Rd0811 = accum(4);\n}\n\n:smmla^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; Ra1215 & Rd0811 & thc0407=0 & Rm0003\n{\n\tbuild ItCond;\n\tlocal val:8 = sext(Rn0003) * sext(Rm0003);\n\tlocal accum:8 = (zext(Ra1215)) << 32;\n\tval = val + accum;\n\tRd0811 = val(4);\n}\n\n:smmlar^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; Ra1215 & Rd0811 & thc0407=1 & Rm0003\n{\n\tbuild ItCond;\n\tlocal val:8 = sext(Rn0003) * sext(Rm0003);\n\tlocal accum:8 = (zext(Ra1215)) << 32;\n\tval = val + accum + 0x80000000;\n\tRd0811 = val(4);\n}\n\n:smmls^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb6 & Rn0003; Ra1215 & Rd0811 & thc0407=0 & Rm0003\n{\n\tbuild ItCond;\n\tlocal val:8 = sext(Rn0003) * sext(Rm0003);\n\tval = (zext(Ra1215) << 32) - val;\n\tRd0811 = val(4);\n}\n\n:smmlsr^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb6 & Rn0003; Ra1215 & Rd0811 & thc0407=1 & Rm0003\n{\n\tbuild ItCond;\n\tlocal val:8 = sext(Rn0003) * sext(Rm0003);\n\tval = (zext(Ra1215) << 32) - val;\n\tval = val + 0x80000000;\n\tRd0811 = val(4);\n}\n\n:smmul^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; thc1215=0xf & Rd0811 & thc0407=0 & Rm0003\n{\n\tbuild ItCond;\n\tval:8 = sext(Rn0003) * sext(Rm0003);\n\tRd0811 = val(4);\n}\n\n:smmulr^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; thc1215=0xf & Rd0811 & thc0407=1 & Rm0003\n{\n\tbuild ItCond;\n\tval:8 = sext(Rn0003) * sext(Rm0003);\n\tval = val + 0x80000000;\n\tRd0811 = val(4);\n}\n\n:smuad^thdXbot^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb2 & Rn0003; thc1215=0xf & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal rnbot:2 = tmpRn0003:2;\n\tlocal rntop:2 = tmpRn0003(2);\n\tlocal prod1:4 = sext(rnbot) * sext(thdXbot);\n\tlocal prod2:4 = sext(rntop) * sext(thdXtop);\n\tQ = scarry(prod1,prod2) || Q; #instruction does not clear the Q flag\n\tRd0811 = prod1 + prod2;\n}\n\n:smulbb^ItCond Rd0811,Rn0003,Rm0003\t\tis TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal tmpRm0003 = Rm0003;\n\top1:2 = tmpRn0003:2;\n\top2:2 = tmpRm0003:2;\n\tRd0811 = sext(op1) * sext(op2);\n}\n\n:smulbt^ItCond Rd0811,Rn0003,Rm0003\t\tis TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=1 & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal tmpRm0003 = Rm0003;\n\top1:2 = tmpRn0003:2;\n\top2:2 = tmpRm0003(2);\n\tRd0811 = sext(op1) * sext(op2);\n}\n\n:smultb^ItCond Rd0811,Rn0003,Rm0003\t\tis TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=2 & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal tmpRm0003 = Rm0003;\n\top1:2 = tmpRn0003(2);\n\top2:2 = tmpRm0003:2;\n\tRd0811 = sext(op1) * sext(op2);\n}\n\n:smultt^ItCond Rd0811,Rn0003,Rm0003\t\tis TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=3 & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\tlocal tmpRm0003 = Rm0003;\n\top1:2 = tmpRn0003(2);\n\top2:2 = tmpRm0003(2);\n\tRd0811 = sext(op1) * sext(op2);\n}\n\n:smull^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb8 & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n val:8 = sext(Rn0003) * sext(Rm0003);\n Ra1215 = val(0);\n Rd0811 = val(4);\n}\n\n:smusd^thdXbot^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb4 & Rn0003; thc1215=0xf & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003\n{\n\tbuild ItCond;\n\tlocal tmpRn0003 = Rn0003;\n\trnbot:2 = tmpRn0003:2;\n\trntop:2 = tmpRn0003(2);\n\ttmpbot:4 = sext(rnbot) * sext(thdXbot);\n\ttmptop:4 = sext(rntop) * sext(thdXtop);\n\ttmp:8 = sext(tmpbot) - sext(tmptop);\n Rd0811 = tmp:4;\n}\n\n:smulw^thYBIT^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb3 & Rn0003; thc1215=0xf & Rd0811 & thc0507=0 & thYBIT & Rm0003\n{\n\tbuild ItCond;\n\ttmp:8 = (sext(Rn0003) * sext(thYBIT)) s>> 16;\n\tRd0811 = tmp:4;\n}\n\n:srsdb^ItCond sp^\"!\",thSRSMode \t\tis TMode=1 & ItCond & op6=0x3a0 & sp & thc0505=1 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode\n{\n build ItCond;\n # register list is always: r14, spsr\n ptr:4 = sp - 4;\n *ptr = lr;\n ptr = ptr - 4;\n *ptr = spsr;\n sp = ptr;\n}\n\n:srsdb^ItCond sp,thSRSMode \t\tis TMode=1 & ItCond & op6=0x3a0 & sp & thc0505=0 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode\n{\n build ItCond;\n # register list is always: r14, spsr\n ptr:4 = sp - 4;\n *ptr = lr;\n ptr = ptr - 4;\n *ptr = spsr;\n}\n\n:srsib^ItCond sp^\"!\",thSRSMode \t\tis TMode=1 & ItCond & op6=0x3a6 & sp & thc0505=1 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode\n{\n build ItCond;\n # register list is always: r14, spsr\n ptr:4 = sp + 4;\n *ptr = lr;\n ptr = ptr + 4;\n *ptr = spsr;\n sp = ptr;\n}\n\n:srsia^ItCond sp,thSRSMode \t\tis TMode=1 & ItCond & op6=0x3a6 & sp & thc0505=0 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode\n{\n build ItCond;\n # register list is always: r14, spsr\n ptr:4 = sp + 4;\n *ptr = lr;\n ptr = ptr + 4;\n *ptr = spsr;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n# ssat and ssat16 were defined elsewhere and moved here to preserve sort order\n\n# shift operands for ssat and usat:\n\nth2_shift0: is imm3_shft=0x0 & imm2_shft=0x0 { }\nth2_shift0: \",lsl \"^thLsbImm is imm3_shft & imm2_shft & thLsbImm { }\nth2_shift1: \",asr \"^thLsbImm is imm3_shft & imm2_shft & thLsbImm { }\nth2_shift1: \",asr #32\" is imm3_shft=0x0 & imm2_shft=0x0 { }\n\n:ssat Rt0811, thMsbImm, part2Rd0003^th2_shift0 is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xc & part2c0505=0x0 & part2c0404=0x0 & part2Rd0003 ;\n thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift0 & thMsbImm & thLsbImm\n{\n # Shift bit is 0\n tmpRn:4 = part2Rd0003 << thLsbImm;\n tmp:4 = SignedSaturate(tmpRn, thMsbImm);\n Q = SignedDoesSaturate(tmpRn, thMsbImm);\n Rt0811 = tmp;\n}\n\n:ssat Rt0811, thMsbImm, part2Rd0003^th2_shift1 is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xc & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003;\n thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift1 & thMsbImm & thLsbImm\n{\n # Shift bit is 1\n tmpRn:4 = part2Rd0003 s>> thLsbImm;\n tmp:4 = SignedSaturate(tmpRn, thMsbImm);\n Q = SignedDoesSaturate(tmpRn, thMsbImm);\n Rt0811 = tmp;\n}\n\n:ssat16 Rt0811, Immed4, part2Rd0003 is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xc & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003;\n op12=0x0 & Rt0811 & thc0407=0x0 & Immed4\n{\n tmp:4 = SignedSaturate(part2Rd0003, Immed4);\n Q = SignedDoesSaturate(part2Rd0003, Immed4);\n Rt0811 = tmp;\n}\n\n:ssax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n sum:4 = sext(Rn0003[ 0,16]) + sext(Rm0003[16,16]);\n diff:4 = sext(Rn0003[16,16]) - sext(Rm0003[ 0,16]);\n Rd0811[ 0,16] = sum[0,16];\n Rd0811[16,16] = diff[0,16];\n GE1 = sum s>= 0;\n GE2 = sum s>= 0;\n GE3 = diff s>= 0;\n GE4 = diff s>= 0;\n}\n\n:ssub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n diff1:4 = sext(Rn0003[ 0,16]) - sext(Rm0003[ 0,16]);\n diff2:4 = sext(Rn0003[16,16]) - sext(Rm0003[16,16]);\n Rd0811[ 0,16] = diff1[0,16];\n Rd0811[16,16] = diff2[0,16];\n GE1 = diff1 s>= 0;\n GE2 = diff1 s>= 0;\n GE3 = diff2 s>= 0;\n GE4 = diff2 s>= 0;\n}\n\n:ssub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n diff1:4 = sext(Rn0003[ 0,8]) - sext(Rm0003[ 0,8]);\n diff2:4 = sext(Rn0003[ 8,8]) - sext(Rm0003[ 8,8]);\n diff3:4 = sext(Rn0003[16,8]) - sext(Rm0003[16,8]);\n diff4:4 = sext(Rn0003[24,8]) - sext(Rm0003[24,8]);\n Rd0811[ 0,8] = diff1[0,8];\n Rd0811[ 8,8] = diff2[0,8];\n Rd0811[16,8] = diff3[0,8];\n Rd0811[24,8] = diff4[0,8];\n GE1 = diff1 s>= 0;\n GE2 = diff2 s>= 0;\n GE3 = diff3 s>= 0;\n GE4 = diff4 s>= 0;\n}\n\n:umull^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfba & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n val:8 = zext(Rn0003) * zext(Rm0003);\n Ra1215 = val(0);\n Rd0811 = val(4);\n}\n\n:umaal^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbe & Rn0003; Ra1215 & Rd0811 & sop0407=6 & Rm0003\n{\n build ItCond;\n val:8 = zext(Rn0003) * zext(Rm0003) + zext(Ra1215) + zext(Rd0811);\n Ra1215 = val(0);\n Rd0811 = val(4);\n}\n\n:umlal^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbe & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003\n{\n build ItCond;\n accum:8 = (zext(Rd0811) << 32) | zext(Ra1215);\n val:8 = zext(Rn0003) * zext(Rm0003) + accum;\n Ra1215 = val(0);\n Rd0811 = val(4);\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n@if defined(VERSION_6)\n\nthumbEndianNess: \"LE\" is op0=0xb650 { export 0:1; }\nthumbEndianNess: \"BE\" is op0=0xb658 { export 1:1; }\n\n:setend^ItCond thumbEndianNess is TMode=1 & ItCond & (op0=0xb650 | op0=0xb658) & thumbEndianNess { setEndianState(thumbEndianNess); }\n\n\n:sev^ItCond is TMode=1 & ItCond & op0=0xbf40\n{\n build ItCond;\n}\n\n:sev^ItCond^\".w\" is TMode=1 & ItCond & op0=0xf3af; op0=8004\n{\n build ItCond;\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n@ifndef CDE\n:stc^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x76 & thN6=0 & thL4=0; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_store(t_cpn,thCRd,taddrmode5);\n}\n\n:stcl^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x76 & thN6=1 & thL4=0; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_storelong(t_cpn,thCRd,taddrmode5);\n}\n\n:stc2^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x7e & thN6=0 & thL4=0; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_store(t_cpn,thCRd,taddrmode5);\n}\n\n:stc2l^ItCond thcpn,thCRd,taddrmode5 \tis (TMode=1 & ItCond & op9=0x7e & thN6=1 & thL4=0; thCRd & thcpn) & taddrmode5\n{\n build ItCond;\n build taddrmode5;\n t_cpn:4 = thcpn;\n coprocessor_storelong(t_cpn,thCRd,taddrmode5);\n}\n@endif # CDE\n\n:stm^ItCond Rn0003,thstrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=0 & thc0404=0 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_inc\n{\n build ItCond;\n mult_addr = Rn0003;\n build thstrlist_inc;\n}\n\n:stm^ItCond^\".w\" Rn0003!,thstrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=1 & thc0404=0 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_inc\n{ \n build ItCond;\n mult_addr = Rn0003;\n build thstrlist_inc;\n Rn0003 = mult_addr;\n}\n\n:stmdb^ItCond Rn0003!,thstrlist_dec is TMode=1 & ItCond & op4=0xe92 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_dec\n{\n build ItCond;\n mult_addr = Rn0003-4;\n build thstrlist_dec;\n Rn0003 = mult_addr + 4;\n}\n\n:stmdb^ItCond Rn0003,thstrlist_dec is TMode=1 & ItCond & op4=0xe90 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_dec\n{\n build ItCond;\n mult_addr = Rn0003-4;\n build thstrlist_dec;\n}\n\n@endif # defined(VERSION_6T2) || defined(VERSION_7)\n\n:stmia^ItCond\tRn_exclaim,stbrace\tis TMode=1 & ItCond & op11=0x18 & Rn_exclaim & stbrace & Rn_exclaim_WB\n{\n build ItCond;\n build Rn_exclaim;\n build stbrace;\n build Rn_exclaim_WB;\n}\n\n:str^ItCond\tRd0002,RnIndirect4\tis TMode=1 & ItCond & op11=0xc & RnIndirect4 & Rd0002\n{\n build ItCond;\n *RnIndirect4 = Rd0002;\n}\n\n:str^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x28 & RnRmIndirect & Rd0002\n{\n build ItCond;\n *RnRmIndirect = Rd0002;\n}\n\n:str^ItCond\tRd0810,Sprel8Indirect\tis TMode=1 & ItCond & op11=0x12 & Sprel8Indirect & Rd0810\n{\n build ItCond;\n *Sprel8Indirect = Rd0810;\n}\n\n\n:strb^ItCond\tRd0002,RnIndirect1\tis TMode=1 & ItCond & op11=0xe & RnIndirect1 & Rd0002\n{\n build ItCond;\n local tmpRd0002 = Rd0002;\n *RnIndirect1 = tmpRd0002:1;\n}\n\n:strb^ItCond\tRd0002,RnRmIndirect\tis TMode=1 & ItCond & op9=0x2a & RnRmIndirect & Rd0002\n{\n build ItCond;\n local tmpRd0002 = Rd0002;\n *RnRmIndirect = tmpRd0002:1;\n}\n\n:strh^ItCond\tRd0002,RnIndirect2\tis TMode=1 & ItCond & op11=0x10 & RnIndirect2 & Rd0002\n{\n build ItCond;\n local tmpRd0002 = Rd0002;\n *RnIndirect2 = tmpRd0002:2;\n}\n\n:strh^ItCond\tRd0002,RnRmIndirect\t\t\tis TMode=1 & ItCond & op9=0x29 & RnRmIndirect & Rd0002\n{\n build ItCond;\n local tmpRd0002 = Rd0002;\n *RnRmIndirect = tmpRd0002:2;\n}\n\n:strt^ItCond^\".w\"\tRt1215,[Rn0003,Immed8]\t\tis TMode=1 & ItCond & op4=0xf84 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n *tmp = Rt1215;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:str.w^ItCond\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf8c; Rt1215) & RnIndirect12\n{\n build ItCond;\n *RnIndirect12 = Rt1215;\n}\n\n:str.w^ItCond\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf84; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n *RnIndirectPUW = Rt1215;\n}\n\n:str^ItCond^\".w\" Rt1215,[Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xf84 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405=0 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + Rm0003;\n *tmp = Rt1215;\n}\n\n:str^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf84 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n *tmp = Rt1215;\n}\n\n:strb^ItCond^\".w\"\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf88; Rt1215) & RnIndirect12\n{\n build ItCond;\n build RnIndirect12;\n local tmpRt1215 = Rt1215;\n *RnIndirect12 = tmpRt1215:1;\n}\n\n:strb^ItCond^\".w\"\tRt1215,RnIndirectPUW \t\tis TMode=1 & ItCond & (op4=0xf80; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n local tmpRt1215 = Rt1215;\n *RnIndirectPUW = tmpRt1215:1;\n}\n\n:strb^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf80 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n local tmpRt1215 = Rt1215;\n *tmp = tmpRt1215:1;\n}\n\n:strbt^ItCond Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf80 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n local tmpRt1215 = Rt1215;\n *tmp = tmpRt1215:1;\n}\n\n:strd^ItCond Rt1215,Rt0811,RnIndirectPUW1 is TMode=1 & ItCond & (op9=0x74 & thc0910=0 & thc0606=1 & thc0404=0 & Rn0003; Rt1215 & Rt0811) & $(RN_INDIRECT_PUW1)\n{\n build ItCond;\n build RnIndirectPUW1;\n local tmp = RnIndirectPUW1;\n *tmp = Rt1215;\n tmp = tmp + 4;\n *tmp = Rt0811;\n}\n\n:strh^ItCond^\".w\"\tRt1215,RnIndirect12 \t\tis TMode=1 & ItCond & (op4=0xf8A; Rt1215) & RnIndirect12\n{\n build ItCond;\n local tmpRt1215 = Rt1215;\n *RnIndirect12 = tmpRt1215:2;\n}\n\n:strh^ItCond Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf82; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)\n{\n build ItCond;\n build RnIndirectPUW;\n local tmpRt1215 = Rt1215;\n\t*RnIndirectPUW = tmpRt1215:2;\n}\n\n:strh^ItCond^\".w\" Rt1215,[Rn0003,Rm0003,\"lsl #\"^thc0405] is TMode=1 & ItCond & op4=0xf82 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 << thc0405);\n local tmpRt1215 = Rt1215;\n *tmp = tmpRt1215:2;\n}\n\n:strht^ItCond Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf82 & Rn0003; Rt1215 & thc0811=14 & Immed8\n{\n build ItCond;\n local tmp = Rn0003 + Immed8;\n local tmpRt1215 = Rt1215;\n *tmp = tmpRt1215:2;\n}\n\n:strex^ItCond Rd0811,Rt1215,[Rn0003,Immed8_4] is TMode=1 & ItCond & op4=0xe84 & Rn0003; Rt1215 & Rd0811 & Immed8_4\n{\n build ItCond;\n local tmp = Rn0003 + Immed8_4;\n local tmpRt = Rt1215;\n access:1 = hasExclusiveAccess(tmp);\n Rd0811 = 1;\n if (!access) goto inst_next;\n Rd0811 = 0;\n *tmp = tmpRt;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n@if defined(VERSION_7)\n\n:strexb^ItCond Rd0003,Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=4 & Rd0003\n{\n build ItCond;\n local tmp = Rn0003;\n local tmpRt = Rt1215;\n access:1 = hasExclusiveAccess(tmp);\n Rd0003 = 1;\n if (!access) goto inst_next;\n Rd0003 = 0;\n *tmp = tmpRt:1;\n}\n\n:strexh^ItCond Rd0003,Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=5 & Rd0003\n{\n build ItCond;\n local tmp = Rn0003;\n local tmpRt = Rt1215;\n access:1 = hasExclusiveAccess(tmp);\n Rd0003 = 1;\n if (!access) goto inst_next;\n Rd0003 = 0;\n *tmp = tmpRt:2;\n}\n\n:strexd^ItCond Rd0003,Rt1215,Rt0811,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & Rt0811 & thc0407=7 & Rd0003\n{\n build ItCond;\n local tmp = Rn0003;\n local tmpRt = Rt1215;\n local tmpRt2 = Rt0811;\n access:1 = hasExclusiveAccess(tmp);\n Rd0003 = 1;\n if (!access) goto inst_next;\n Rd0003 = 0;\n *tmp = tmpRt;\n tmp = tmp + 4;\n *tmp = tmpRt2;\n}\n\n@endif # VERSION_7\n\n:sub^CheckInIT_CZNO^ItCond\tRd0002,Rn0305,Immed3\tis TMode=1 & ItCond & op9=0xf & Immed3 & Rn0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_subflags(Rn0305,Immed3);\n Rd0002 = Rn0305 - Immed3;\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n:sub^CheckInIT_CZNO^ItCond\tRd0810,Immed8\t\tis TMode=1 & ItCond & op11=7 & Rd0810 & Immed8 & CheckInIT_CZNO\n{\n build ItCond;\n th_subflags(Rd0810,Immed8);\n Rd0810 = Rd0810 - Immed8;\n resflags(Rd0810);\n build CheckInIT_CZNO;\n}\n\n:sub^CheckInIT_CZNO^ItCond\tRd0002,Rn0305,Rm0608\tis TMode=1 & ItCond & op9=0xd & Rm0608 & Rn0305 & Rd0002 & CheckInIT_CZNO\n{\n build ItCond;\n th_subflags(Rn0305,Rm0608);\n Rd0002 = Rn0305 - Rm0608;\n resflags(Rd0002);\n build CheckInIT_CZNO;\n}\n\n:sub^ItCond\tsp,Immed7_4\t\tis TMode=1 & ItCond & op7=0x161 & sp & Immed7_4\n{\n build ItCond;\n sp = sp - Immed7_4;\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:sub^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=13 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n th_subflags(Rn0003,ThumbExpandImm12);\n Rd0811 = Rn0003-ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:subw^ItCond\tRd0811,Rn0003,Immed12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & Rn0003; thc1515=0 & Rd0811) & Immed12\n{\n build ItCond;\n th_subflags(Rn0003,Immed12);\n Rd0811 = Rn0003-Immed12;\n resflags(Rd0811);\n}\n\n:sub^thSBIT_CZNO^ItCond^\".w\"\tRd0811,Rn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=13 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n local tmp = thshift2;\n th_subflags(Rn0003,tmp);\n Rd0811 = Rn0003-tmp;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:sub^thSBIT_CZNO^ItCond^\".w\"\tRd0811,sp,ThumbExpandImm12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=13 & thSBIT_CZNO & sp & sop0003=0xd; thc1515=0 & Rd0811) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n th_subflags(sp,ThumbExpandImm12);\n Rd0811 = sp-ThumbExpandImm12;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n:sub^ItCond\tpc,lr,Immed8 \t\tis TMode=1 & ItCond & op4=0xf3d & pc & sop0003=0xe; op8=0x8f & lr & Immed8\n{\n build ItCond;\n build Immed8;\n th_subflags(lr,Immed8);\n dest:4 = lr-Immed8;\n resflags(dest);\n cpsr=spsr;\n SetThumbMode( ((cpsr >> 5) & 1) != 0 );\n pc = dest;\n goto [pc];\n}\n\n:subw^ItCond\tRd0811,sp,Immed12 \t\tis TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xd & sp; thc1515=0 & Rd0811) & Immed12\n{\n build ItCond;\n th_subflags(sp,Immed12);\n Rd0811 = sp-Immed12;\n resflags(Rd0811);\n}\n\n:sub^thSBIT_CZNO^ItCond^\".w\"\tRd0811,sp,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=13 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2\n{\n build ItCond;\n build thshift2;\n local tmp = thshift2;\n th_subflags(sp,tmp);\n Rd0811 = sp-tmp;\n resflags(Rd0811);\n build thSBIT_CZNO;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:svc^ItCond\timmed8\t\t\tis TMode=1 & ItCond & op8=0xdf & immed8\n{\n build ItCond;\n tmp:4 = immed8;\n software_interrupt(tmp);\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:sxtab^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa4 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = sext(tmp:1) + Rn0003;\n}\n\n:sxtab^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa4 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n Rd0811 = sext(tmpRm0003:1) + Rn0003;\n}\n\n:sxtab16^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa2 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n local tmpRn0003 = Rn0003;\n tmpL:2 = sext(tmp:1) + tmpRn0003:2;\n tmp = tmp >> 16;\n tmpH:2 = sext(tmp:1) + tmpRn0003(2);\n Rd0811 = zext(tmpL) + (zext(tmpH) << 16);\n}\n\n:sxtab16^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa2 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRn0003 = Rn0003;\n local tmpRm0003 = Rm0003;\n tmpL:2 = sext(tmpRm0003:1) + tmpRn0003:2;\n local tmp = tmpRm0003 >> 16;\n tmpH:2 = sext(tmp:1) + tmpRn0003(2);\n Rd0811 = zext(tmpL) + (zext(tmpH) << 16);\n}\n\n:sxtah^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa0 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = sext(tmp:2) + Rn0003;\n}\n\n:sxtah^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa0 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n Rd0811 = sext(tmpRm0003:2) + Rn0003;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n@if defined(VERSION_6)\n\n:sxtb^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=0 & thc0606=1 & Rm0305 & Rd0002\n{\n build ItCond;\n local tmpRm0305 = Rm0305;\n Rd0002 = sext(tmpRm0305:1);\n}\n\n:sxtb^ItCond^\".w\" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa4f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = sext(tmp:1);\n}\n\n:sxtb^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa4f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n Rd0811 = sext(tmpRm0003:1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:sxtb16^ItCond Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa2f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003\n \n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n tmpL:2 = sext(tmp:1);\n tmp = tmp >> 16;\n tmpH:2 = sext(tmp:1);\n Rd0811 = zext(tmpL) + (zext(tmpH) << 16);\n}\n\n:sxtb16^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa2f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n tmpL:2 = sext(tmpRm0003:1);\n tmp:4 = tmpRm0003 >> 16;\n tmpH:2 = sext(tmp:1);\n Rd0811 = zext(tmpL) + (zext(tmpH) << 16);\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n@if defined(VERSION_6)\n\n:sxth^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=0 & thc0606=0 & Rm0305 & Rd0002\n{\n build ItCond;\n local tmpRm0305 = Rm0305;\n Rd0002 = sext(tmpRm0305:2);\n}\n\n:sxth^ItCond^\".w\" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa0f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = sext(tmp:2);\n}\n\n:sxth^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa0f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n Rd0811 = sext(tmpRm0003:2);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:tbb^ItCond [Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; op8=0xf0 & thc0507=0 & thc0404=0 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + Rm0003;\n offs:1 = *tmp;\n SetThumbMode(1);\n pc = inst_next + (zext(offs) * 2);\n goto [pc];\n}\n\n:tbh^ItCond [Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; op8=0xf0 & thc0507=0 & thc0404=1 & Rm0003\n{\n build ItCond;\n local tmp = Rn0003 + (Rm0003 * 2);\n offs:2 = *tmp;\n SetThumbMode(1);\n pc = inst_next + (zext(offs) * 2);\n goto [pc];\n}\n\nPcrel: [pc,Rm0003] is Rm0003 & thc0404=0 & pc\n{\n local tmp = Rm0003; tmp = inst_next + tmp; val:1 = *tmp; tmp = zext(val); export tmp;\n}\nPcrel: [pc,Rm0003] is Rm0003 & thc0404=1 & pc\n{\n local tmp = Rm0003; tmp = inst_next + (tmp * 2); val:2 = *tmp; tmp = zext(val); export tmp;\n}\n\n:tbb^ItCond Pcrel is TMode=1 & ItCond & op4=0xe8d & thc0003=15; op8=0xf0 & thc0507=0 & thc0404=0 & Pcrel\n{\n build ItCond;\n SetThumbMode(1);\n pc = inst_next + (Pcrel * 2);\n goto [pc];\n}\n\n:tbh^ItCond Pcrel is TMode=1 & ItCond & op4=0xe8d & thc0003=15; op8=0xf0 & thc0507=0 & thc0404=1 & Pcrel\n{\n build ItCond;\n SetThumbMode(1);\n pc = inst_next + (Pcrel * 2);\n goto [pc];\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n:tst^ItCond\tRn0002,Rm0305\t\tis TMode=1 & ItCond & op6=0x108 & Rm0305 & Rn0002\n{\n build ItCond;\n local tmp = Rn0002 & Rm0305;\n ZR = (tmp == 0);\n NG = (tmp s< 0);\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:teq^ItCond\tRn0003,ThumbExpandImm12 \tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=4 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n local tmp = Rn0003 ^ ThumbExpandImm12;\n th_test_flags(tmp);\n}\n\n:teq^ItCond^\".w\"\tRn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=4 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf & thshift2\n{\n build ItCond;\n build thshift2;\n local tmp = Rn0003 ^ thshift2;\n th_test_flags(tmp);\n}\n\n:tst^ItCond\tRn0003,ThumbExpandImm12 \tis TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=0 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf) & ThumbExpandImm12\n{\n build ItCond;\n build ThumbExpandImm12;\n local tmp = Rn0003 & ThumbExpandImm12;\n th_test_flags(tmp);\n}\n\n:tst^ItCond^\".w\"\tRn0003,thshift2 \t\tis TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=0 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf & thshift2\n{\n build ItCond;\n build thshift2;\n local tmp = Rn0003 & thshift2;\n th_test_flags(tmp);\n}\n\n:uadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003\n{\n build ItCond;\n sum1:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[ 0,16]);\n sum2:4 = zext(Rn0003[16,16]) + zext(Rm0003[16,16]);\n GE1 = carry(Rn0003[0,16],Rm0003[0,16]);\n GE2 = GE1;\n GE3 = carry(Rn0003[16,16],Rm0003[16,16]);\n GE4 = GE3;\n Rd0811[ 0,16] = sum1[0,16];\n Rd0811[16,16] = sum2[0,16];\n}\n\n:uadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003\n{\n build ItCond;\n sum1:4 = zext(Rn0003[ 0,8]) + zext(Rm0003[ 0,8]);\n sum2:4 = zext(Rn0003[ 8,8]) + zext(Rm0003[ 8,8]);\n sum3:4 = zext(Rn0003[16,8]) + zext(Rm0003[16,8]);\n sum4:4 = zext(Rn0003[24,8]) + zext(Rm0003[24,8]);\n GE1 = carry(Rn0003[0,8],Rm0003[0,8]);\n GE2 = carry(Rn0003[8,8],Rm0003[8,8]);\n GE3 = carry(Rn0003[16,8],Rm0003[16,8]);\n GE4 = carry(Rn0003[24,8],Rm0003[24,8]);\n Rd0811[ 0,8] = sum1[0,8];\n Rd0811[ 8,8] = sum2[0,8];\n Rd0811[16,8] = sum3[0,8];\n Rd0811[24,8] = sum4[0,8];\n}\n\n:uasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003\n{\n build ItCond;\n diff:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[16,16]);\n sum:4 = zext(Rn0003[16,16]) + zext(Rm0003[ 0,16]);\n GE1 = diff s>= 0;\n GE2 = GE1;\n GE3 = carry(Rn0003[16,16],Rm0003[0,16]);\n GE4 = GE3;\n Rd0811[ 0,16] = diff[0,16];\n Rd0811[16,16] = sum[0,16];\n }\n\n:uhadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003\n{\n build ItCond;\n sum1:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[ 0,16]);\n sum2:4 = zext(Rn0003[16,16]) + zext(Rm0003[16,16]);\n Rd0811[ 0,16] = sum1[1,16];\n Rd0811[16,16] = sum2[1,16];\n}\n\n:uhadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003\n{\n build ItCond;\n sum1:4 = zext(Rn0003[ 0,8]) + zext(Rm0003[ 0,8]);\n sum2:4 = zext(Rn0003[ 8,8]) + zext(Rm0003[ 8,8]);\n sum3:4 = zext(Rn0003[16,8]) + zext(Rm0003[16,8]);\n sum4:4 = zext(Rn0003[24,8]) + zext(Rm0003[24,8]);\n Rd0811[ 0,8] = sum1[1,8];\n Rd0811[ 8,8] = sum2[1,8];\n Rd0811[16,8] = sum3[1,8];\n Rd0811[24,8] = sum4[1,8];\n}\n\n:uhasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003\n{\n build ItCond;\n diff:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[16,16]);\n sum:4 = zext(Rn0003[16,16]) + zext(Rm0003[ 0,16]);\n Rd0811[ 0,16] = diff[1,16];\n Rd0811[16,16] = sum[1,16];\n}\n\n:uhsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003\n{\n build ItCond;\n sum:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[16,16]);\n diff:4 = zext(Rn0003[16,16]) - zext(Rm0003[ 0,16]);\n Rd0811[ 0,16] = sum[1,16];\n Rd0811[16,16] = diff[1,16];\n}\n\n:uhsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[ 0,16]);\n diff2:4 = zext(Rn0003[16,16]) - zext(Rm0003[16,16]);\n Rd0811[ 0,16] = diff1[1,16];\n Rd0811[16,16] = diff2[1,16];\n}\n\n:uhsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]);\n diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]);\n diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]);\n diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]);\n Rd0811[ 0,8] = diff1[1,8];\n Rd0811[ 8,8] = diff2[1,8];\n Rd0811[16,8] = diff3[1,8];\n Rd0811[24,8] = diff4[1,8];\n}\n\n:uqadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003\n{\n build ItCond;\n sum1:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[ 0,16]);\n sum2:4 = zext(Rn0003[16,16]) + zext(Rm0003[16,16]);\n tmp1:4 = UnsignedSaturate(sum1, 16:2);\n tmp2:4 = UnsignedSaturate(sum2, 16:2);\n Rd0811[ 0,16] = tmp1[0,16];\n Rd0811[16,16] = tmp2[0,16];\n}\n\n:uqadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003\n{\n build ItCond;\n sum1:4 = zext(Rn0003[ 0,8]) + zext(Rm0003[ 0,8]);\n sum2:4 = zext(Rn0003[ 8,8]) + zext(Rm0003[ 8,8]);\n sum3:4 = zext(Rn0003[16,8]) + zext(Rm0003[16,8]);\n sum4:4 = zext(Rn0003[24,8]) + zext(Rm0003[24,8]);\n tmp1:4 = UnsignedSaturate(sum1, 8:2);\n tmp2:4 = UnsignedSaturate(sum2, 8:2);\n tmp3:4 = UnsignedSaturate(sum3, 8:2);\n tmp4:4 = UnsignedSaturate(sum4, 8:2);\n Rd0811[ 0,8] = tmp1[0,8];\n Rd0811[ 8,8] = tmp2[0,8];\n Rd0811[16,8] = tmp3[0,8];\n Rd0811[24,8] = tmp4[0,8];\n}\n\n:uqasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003\n{\n build ItCond;\n diff:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[16,16]);\n sum:4 = zext(Rn0003[16,16]) + zext(Rm0003[ 0,16]);\n tmpdiff:4 = UnsignedSaturate(diff, 16:2);\n tmpsum:4 = UnsignedSaturate(sum, 16:2);\n Rd0811[ 0,16] = tmpdiff[0,16];\n Rd0811[16,16] = tmpsum[0,16];\n}\n\n:uqsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003\n{\n build ItCond;\n sum:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[16,16]);\n diff:4 = zext(Rn0003[16,16]) - zext(Rm0003[ 0,16]);\n tmpsum:4 = UnsignedSaturate(sum, 16:2);\n tmpdiff:4 = UnsignedSaturate(diff, 16:2);\n Rd0811[ 0,16] = tmpsum[0,16];\n Rd0811[16,16] = tmpdiff[0,16];\n}\n\n:uqsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[ 0,16]);\n diff2:4 = zext(Rn0003[16,16]) - zext(Rm0003[16,16]);\n tmp1:4 = UnsignedSaturate(diff1, 16:2);\n tmp2:4 = UnsignedSaturate(diff2, 16:2);\n Rd0811[ 0,16] = tmp1[0,16];\n Rd0811[16,16] = tmp2[0,16];\n}\n\n:uqsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]);\n diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]);\n diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]);\n diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]);\n tmp1:4 = UnsignedSaturate(diff1, 8:2);\n tmp2:4 = UnsignedSaturate(diff2, 8:2);\n tmp3:4 = UnsignedSaturate(diff3, 8:2);\n tmp4:4 = UnsignedSaturate(diff4, 8:2);\n Rd0811[ 0,8] = tmp1[0,8];\n Rd0811[ 8,8] = tmp2[0,8];\n Rd0811[16,8] = tmp3[0,8];\n Rd0811[24,8] = tmp4[0,8];\n}\n\n:usad8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb7 & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]);\n diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]);\n diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]);\n diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]);\n absdiff1:4 = Absolute(diff1);\n absdiff2:4 = Absolute(diff2);\n absdiff3:4 = Absolute(diff3);\n absdiff4:4 = Absolute(diff4);\n Rd0811 = absdiff1 + absdiff2 + absdiff3 + absdiff4;\n}\n\n:usada8^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb7 & Rn0003; Ra1215 & Rd0811 & thc0407=0x0 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]);\n diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]);\n diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]);\n diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]);\n absdiff1:4 = Absolute(diff1);\n absdiff2:4 = Absolute(diff2);\n absdiff3:4 = Absolute(diff3);\n absdiff4:4 = Absolute(diff4);\n # The manual specifies a zero extension of Ra to an unspecified\n # intermediate precision, followed by truncation to 4 bytes. In this\n # model, zext is retained, but it has no effect because the\n # intermediate precision is 4 bytes.\n Rd0811 = zext(Ra1215) + absdiff1 + absdiff2 + absdiff3 + absdiff4;\n}\n\n# usat and ussat16 were defined elsewhere and moved here to preserve sort order\n\n:usat Rt0811, thMsbImm, part2Rd0003^th2_shift0 is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2c0505=0x0 & part2c0404=0x0 & part2Rd0003 ;\n thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift0 & thMsbImm & thLsbImm\n{\n # Shift bit is 0\n\ttmpRn:4 = part2Rd0003 << thLsbImm;\n tmp:4 = UnsignedSaturate(tmpRn, thMsbImm);\n Q = UnsignedDoesSaturate(tmpRn, thMsbImm);\n Rt0811 = tmp;\n}\n\n:usat Rt0811, thMsbImm, part2Rd0003^th2_shift1 is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003 ;\n thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift1 & thMsbImm & thLsbImm\n{\n # Shift bit is 1\n tmpRn:4 = part2Rd0003 s>> thLsbImm;\n tmp:4 = UnsignedSaturate(tmpRn, thMsbImm);\n Q = UnsignedDoesSaturate(tmpRn, thMsbImm);\n Rt0811 = tmp;\n}\n\n:usat16 Rt0811, Immed4, part2Rd0003 is\n TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003 ;\n op12=0x0 & Rt0811 & thc0407=0x0 & Immed4\n{\n tmp:4 = UnsignedSaturate(part2Rd0003, Immed4);\n Q = UnsignedDoesSaturate(part2Rd0003, Immed4);\n Rt0811 = tmp;\n}\n\n:usax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003\n{\n build ItCond;\n sum:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[16,16]);\n diff:4 = zext(Rn0003[16,16]) - zext(Rm0003[ 0,16]);\n Rd0811[ 0,16] = sum[0,16];\n Rd0811[16,16] = diff[0,16];\n # this odd looking condition tests that the 16 bit sum overflowed,\n # which would have made it a negative number. That's how it's\n # documented, but to be consistent they might have used s< 0.\n GE1 = sum s>= 0x10000;\n GE2 = sum s>= 0x10000;\n GE3 = diff s>= 0;\n GE4 = diff s>= 0;\n}\n\n:usub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[ 0,16]);\n diff2:4 = zext(Rn0003[16,16]) - zext(Rm0003[16,16]);\n Rd0811[ 0,16] = diff1[0,16];\n Rd0811[16,16] = diff2[0,16];\n GE1 = diff1 s>= 0;\n GE2 = diff1 s>= 0;\n GE3 = diff2 s>= 0;\n GE4 = diff2 s>= 0;\n}\n\n:usub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003\n{\n build ItCond;\n diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]);\n diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]);\n diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]);\n diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]);\n Rd0811[ 0,8] = diff1[0,8];\n Rd0811[ 8,8] = diff2[0,8];\n Rd0811[16,8] = diff3[0,8];\n Rd0811[24,8] = diff4[0,8];\n GE1 = diff1 s>= 0;\n GE2 = diff2 s>= 0;\n GE3 = diff3 s>= 0;\n GE4 = diff4 s>= 0;\n}\n\n:ubfx^ItCond Rd0811,Rn0003,thLsbImm,thWidthMinus1\tis TMode=1 & ItCond & op4=0xf3c & Rn0003; thc1515=0 & Rd0811 & thLsbImm & thc0505=0 & thWidthMinus1\n{\n build ItCond;\n\tbuild thLsbImm;\n\tbuild thWidthMinus1;\n\tshift:4 = 31 - (thLsbImm + thWidthMinus1); # thMsbImm represents widthMinus1\n\tRd0811 = Rn0003 << shift;\n\tshift = 31 - thWidthMinus1; # msbImm represents widthMinus1\n\tRd0811 = Rd0811 >> shift;\n}\n\n:udiv^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbb & Rn0003; op12=0xf & Rd0811 & thc0407=0xf & Rm0003\n{\n build ItCond;\n result:8 = zext(Rn0003) / zext(Rm0003);\n Rd0811 = result(0);\n}\n\n:uxtab^ItCond Rd0811,Rn0003,Rm0003,ByteRotate \tis TMode=1 & ItCond & op4=0xfa5 & Rn0003; op12=15 & Rd0811 & thc0707=1 & ByteRotate & Rm0003\n{\n build ItCond;\n\ttmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n\tRd0811 = Rn0003 + zext(tmp:1);\n}\n\n:uxtab16^ItCond Rd0811,Rn0003,Rm0003,ByteRotate \tis TMode=1 & ItCond & op4=0xfa3 & Rn0003; op12=15 & Rd0811 & thc0707=1 & ByteRotate & Rm0003\n{\n build ItCond;\n\trotated:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n\tlocal tmp_b = rotated:1;\n\tlocal tmpRn0003 = Rn0003;\n\ttmpl:2 = tmpRn0003:2 + zext(tmp_b);\n\tlocal tmph = (rotated >> 16);\n\ttmp_b = tmph:1;\n\ttmph = (tmpRn0003 >> 16) + zext(tmp_b);\n\tRd0811 = (tmph << 16) | zext(tmpl);\n}\n\n:uxtah^ItCond Rd0811,Rn0003,Rm0003 \tis TMode=1 & ItCond & op4=0xfa1 & Rn0003; op12=15 & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n\tRd0811 = Rn0003 + zext(tmpRm0003:2);\n}\n\n:uxtah^ItCond Rd0811,Rn0003,Rm0003,ByteRotate \tis TMode=1 & ItCond & op4=0xfa1 & Rn0003; op12=15 & Rd0811 & thc0707=1 & ByteRotate & Rm0003\n{\n build ItCond;\n\ttmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n\tRd0811 = Rn0003 + zext(tmp:2);\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n@if defined(VERSION_6)\n\n:uxtb^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=1 & thc0606=1 & Rm0305 & Rd0002\n{\n build ItCond;\n local tmpRm0305 = Rm0305;\n Rd0002 = zext(tmpRm0305:1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:uxtb^ItCond^\".w\" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa5f; op12=0xf & Rd0811 & thc0707=1 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = zext(tmp:1);\n}\n\n:uxtb^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa5f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n Rd0811 = zext(tmpRm0003:1);\n}\n\n:uxtb16^ItCond Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa3f; op12=0xf & Rd0811 & thc0707=1 & ByteRotate & Rm0003\n{\n build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = tmp & 0x00ff00ff;\n}\n\n:uxtb16^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa3f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n Rd0811 = Rm0003 & 0x00ff00ff;\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n@if defined(VERSION_6)\n\n:uxth^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=1 & thc0606=0 & Rm0305 & Rd0002\n{\n build ItCond;\n local tmpRm0305 = Rm0305;\n Rd0002 = zext(tmpRm0305:2);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:uxth^ItCond^\".w\" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa1f; op12=0xf & Rd0811 & thc0707=1 & ByteRotate & Rm0003\n{ build ItCond;\n tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate);\n Rd0811 = zext(tmp:2);\n}\n\n:uxth^ItCond^\".w\" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa1f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003\n{\n build ItCond;\n local tmpRm0003 = Rm0003;\n Rd0811 = zext(tmpRm0003:2);\n}\n\n@endif # VERSION_6T2 || VERSION_7\n\n# V* see ARMneon.sinc\n\n@if defined(VERSION_6)\n\n:wfe^ItCond is TMode=1 & ItCond & op0=0xbf20\n{\n\tWaitForEvent();\n}\n\n:wfi^ItCond is TMode=1 & ItCond & op0=0xbf30\n{\n\tWaitForInterrupt();\n}\n\n:yield^ItCond is TMode=1 & ItCond & op0=0xbf10\n{\n\tHintYield();\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\n:wfe^ItCond^\".w\" is TMode=1 & ItCond & op0=0xf3af; op0=0x8002\n{\n\tWaitForEvent();\n}\n\n:wfi^ItCond^\".w\" is TMode=1 & ItCond & op0=0xf3af; op0=0x8003\n{\n\tWaitForInterrupt();\n}\n\n:yield^ItCond^\".w\" is TMode=1 & ItCond & op0=0xf3af; op0=0x8001\n{\n\tHintYield();\n}\n@endif #VERSION_6T2 || VERSION_7\n\n} # End with : ARMcondCk=1\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM_CDE.sinc", "content": "@if defined(CDE)\n# ARMv8-M Custom Datapath Extension\n\nacc: \"a\" is thc1212=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nacc: \"\" is thc1212=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nvacc: \"a\" is thv_c2828=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nvacc: \"\" is thv_c2828=0 { local tmp:1 = 0; export *[const]:1 tmp; }\n\ncx1_imm: val is thc0005; thop2 & thopcode3 [val=(thc0005 << 7) | (thop2 << 6) | thopcode3;] {export *[const]:4 val; }\ncx2_imm: val is thc0405; thop2 & thopcode3 [val=(thc0405 << 7) | (thop2 << 6) | thopcode3;] {export *[const]:4 val; }\ncx3_imm: val is thop1; thop2 & thop3 [val=(thop1 << 3) | (thop2 << 2) | thop3;] {export *[const]:4 val; }\n\nvcx1_imm: val is thv_c2424 & thv_c1619 & thv_c0707 & thv_c0005 [val = (thv_c2424 << 11) |(thv_c1619 << 7) | (thv_c0707 << 6) | thv_c0005;] {export *[const]:4 val; }\nvcx2_imm: val is thv_c2424 & thv_c1619 & thv_c0707 & thv_c0404 [val = (thv_c2424 << 6 ) |(thv_c1619 << 2) | (thv_c0707 << 1) | thv_c0404;] {export *[const]:4 val; }\nvcx3_imm: val is thv_c2424 & thv_c2021 & thv_c0404 [val = (thv_c2424 << 3 ) |(thv_c2021 << 1) | thv_c0404;] {export *[const]:4 val; }\n\nfvcx1_imm: val is thv_c1619 & thv_c0707 & thv_c0005 [val = (thv_c1619 << 7) | (thv_c0707 << 6) | thv_c0005;] {export *[const]:4 val; }\nfvcx2_imm: val is thv_c1619 & thv_c0707 & thv_c0404 [val = (thv_c1619 << 2) | (thv_c0707 << 1) | thv_c0404;] {export *[const]:4 val; }\nfvcx3_imm: val is thv_c2021 & thv_c0404 [val = (thv_c2021 << 1) | thv_c0404;] {export *[const]:4 val; }\n\n\ncx_coRd: Ra1215 is Ra1215 { export Ra1215; }\ncx_coRd:\"APSR_nzcv\" is Ra1215=15 { tmp:4 = 0; readAPSR_nzcv(tmp); export tmp; }\ncx_coRn: Rn0003 is Rn0003 { export Rn0003; }\ncx_coRn:\"APSR_nzcv\" is Rn0003=15 { tmp:4 = 0; readAPSR_nzcv(tmp); export tmp; }\ncx_coRm: Ra1215 is Ra1215 { export Ra1215; }\ncx_coRm:\"APSR_nzcv\" is Ra1215=15 { tmp:4 = 0; readAPSR_nzcv(tmp); export tmp; }\ncx_coRd0: Rd0003 is Rd0003 { export Rd0003; }\ncx_coRd0:\"APSR_nzcv\" is Rd0003=15 { tmp:4 = 0; readAPSR_nzcv(tmp); export tmp; }\n\n# Pseudo-ops\ndefine pcodeop cx1; # Rd = cx1(Coprocessor #, operation, Rd, accumulator, size)\ndefine pcodeop cx2; # Rd = cx2(Coprocessor #, operation, Rd, Rn, accumulator, size)\ndefine pcodeop cx3; # Rd = cx3(Coprocessor #, operation, Rd, Rn, Rm, accumulator, size)\ndefine pcodeop vcx1; # Rd = vcx1(Coprocessor #, operation, Rd, accumulator, size, vectored)\ndefine pcodeop vcx2; # Rd = vcx2(Coprocessor #, operation, Rd, Rn, accumulator, size, vectored)\ndefine pcodeop vcx3; # Rd = vcx3(Coprocessor #, operation, Rd, Rn, Rm, accumulator, size, vectored)\n\n:cx1^acc^ItCond thcop, cx_coRd, cx1_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0607=0; cx_coRd & thc1111=0 & thcop & thc0606=0) & cx1_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx1_imm;\n\tt_acc:1 = acc;\n\tcx_coRd = cx1(t_cpn, t_op1, cx_coRd, t_acc, 32:1);\n}\n\n:cx1^acc^ItCond thcop, cx_coRd, cx1_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0607=0; (cx_coRd & Ra1215=15) & thc1111=0 & thcop & thc0606=0) & cx1_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx1_imm;\n\tt_acc:1 = acc;\n\tcx_coRd = cx1(t_cpn, t_op1, cx_coRd, t_acc, 32:1);\n\twriteAPSR_nzcv(cx_coRd);\n}\n\n:cx1d^acc^ItCond thcop, Ra1215, Rd1215hi, cx1_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0607=0; Ra1215 & Rd1215hi & thc1111=0 & thcop & thc0606=1) & cx1_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx1_imm;\n\tt_acc:1 = acc;\n\tresult:8 = cx1(t_cpn, t_op1, Ra1215, Rd1215hi, t_acc, 64:1);\n\tRa1215 = result(0);\n\tRd1215hi = result(4);\n}\n\n:cx2^acc^ItCond thcop, cx_coRd, cx_coRn, cx2_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0607=1 & cx_coRn; cx_coRd & thc1111=0 & thcop & thc0606=0) & cx2_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx2_imm;\n\tt_acc:1 = acc;\n\tcx_coRd = cx2(t_cpn, t_op1, cx_coRd, cx_coRn, t_acc, 32:1);\n}\n:cx2^acc^ItCond thcop, cx_coRd, cx_coRn, cx2_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0607=1 & cx_coRn; (cx_coRd & Ra1215=15) & thc1111=0 & thcop & thc0606=0) & cx2_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx2_imm;\n\tt_acc:1 = acc;\n\tcx_coRd = cx2(t_cpn, t_op1, cx_coRd, cx_coRn, t_acc, 32:1);\n\twriteAPSR_nzcv(cx_coRd);\n}\n\n:cx2d^acc^ItCond thcop, Ra1215, Rd1215hi, cx_coRn, cx2_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0607=1 & cx_coRn; Ra1215 & Rd1215hi & thc1111=0 & thcop & thc0606=1) & cx2_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx2_imm;\n\tt_acc:1 = acc;\n\tresult:8 = cx2(t_cpn, t_op1, Ra1215, Rd1215hi, cx_coRn, t_acc, 64:1);\n\tRa1215 = result(0);\n\tRd1215hi = result(4);\n}\n\n:cx3^acc^ItCond thcop, cx_coRd0, cx_coRn, cx_coRm, cx3_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0707=1 & cx_coRn; cx_coRm & thc1111=0 & thcop & thc0606=0 & cx_coRd0) & cx3_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx3_imm;\n\tt_acc:1 = acc;\n\tcx_coRd0 = cx3(t_cpn, t_op1, cx_coRd0, cx_coRn, cx_coRm, t_acc, 32:1);\n}\n:cx3^acc^ItCond thcop, cx_coRd0, cx_coRn, cx_coRm, cx3_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0707=1 & cx_coRn; cx_coRm & thc1111=0 & thcop & thc0606=0 & (cx_coRd0 & Rd0003=15)) & cx3_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx3_imm;\n\tt_acc:1 = acc;\n\tcx_coRd0 = cx3(t_cpn, t_op1, cx_coRd0, cx_coRn, cx_coRm, t_acc, 32:1);\n\twriteAPSR_nzcv(cx_coRd0);\n}\n\n:cx3d^acc^ItCond thcop, Rd0003, Rd0003hi, cx_coRn, cx_coRm, cx3_imm is TMode=1 & ItCond & (op13=7 & acc & thc0811=0xe & thc0707=1 & cx_coRn; cx_coRm & thc1111=0 & thcop & thc0606=1 & Rd0003 & Rd0003hi) & cx3_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thcop;\n\tt_op1:4 = cx3_imm;\n\tt_acc:1 = acc;\n\tresult:8 = cx3(t_cpn, t_op1, Rd0003, Rd0003hi, cx_coRn, cx_coRm, t_acc, 64:1);\n\tRd0003 = result(0);\n\tRd0003hi = result(4);\n}\n\n# Vector CDE instructions - Requires Armv8.1-M MVE\n:vcx1^vacc^ItCond thv_cpn, Qd, vcx1_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2323=0 & thv_c2021=2 & thv_c1111=0 & thv_cpn & thv_c0606=1 & Qd & vcx1_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = vcx1_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 1;\n\tQd = vcx1(t_cpn, t_op1, Qd, t_acc, 32:1, t_vec);\n}\n\n:vcx2^vacc^ItCond thv_cpn, Qd, Qm, vcx2_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2323=0 & thv_c2021=3 & thv_c1111=0 & thv_cpn & thv_c0606=1 & Qm & Qd & vcx2_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = vcx2_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 1;\n\tQd = vcx2(t_cpn, t_op1, Qd, Qm, t_acc, 32:1, t_vec);\n}\n\n\n:vcx3^vacc^ItCond thv_cpn, Qd, Qn, Qm, vcx3_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2323=1 & thv_c1111=0 & thv_cpn & thv_c0606=1 & Qm & Qn & Qd & vcx3_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = vcx3_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 1;\n\tQd = vcx3(t_cpn, t_op1, Qd, Qn, Qm, t_acc, 32:1, t_vec);\n}\n\n\n# Floating-point CDE instructions - Requires Armv8.1-M MVE\n:vcx1^vacc^ItCond thv_cpn, Sd, fvcx1_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2424=0 & thv_c2323=0 & thv_c2021=2 & thv_c1111=0 & thv_cpn & thv_c0606=0 & Sd & fvcx1_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = fvcx1_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 0;\n\tSd = vcx1(t_cpn, t_op1, Sd, t_acc, 32:1, t_vec);\n}\n\n:vcx1^vacc^ItCond thv_cpn, Dd, fvcx1_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2424=1 & thv_c2323=0 & thv_c2021=2 & thv_c1111=0 & thv_cpn & thv_c0606=0 & Dd & fvcx1_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = fvcx1_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 0;\n\tDd = vcx1(t_cpn, t_op1, Dd, t_acc, 64:1, t_vec);\n}\n\n\n\n:vcx2^vacc^ItCond thv_cpn, Sd, Sm, fvcx2_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2424=0 & thv_c2323=0 & thv_c2021=3 & thv_c1111=0 & thv_cpn & thv_c0606=0 & Sm & Sd & fvcx2_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = fvcx2_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 0;\n\tSd = vcx2(t_cpn, t_op1, Sd, Sm, t_acc, 32:1, t_vec);\n}\n\n:vcx2^vacc^ItCond thv_cpn, Dd, Dm, fvcx2_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2424=1 & thv_c2323=0 & thv_c2021=3 & thv_c1111=0 & thv_cpn & thv_c0606=0 & Dm & Dd & fvcx2_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = fvcx2_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 0;\n\tDd = vcx2(t_cpn, t_op1, Dd, Dm, t_acc, 64:1, t_vec);\n}\n\n\n:vcx3^vacc^ItCond thv_cpn, Sd, Sn, Sm, fvcx3_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2424=0 & thv_c2323=1 & thv_c1111=0 & thv_cpn & thv_c0606=0 & Sm & Sn & Sd & fvcx3_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = fvcx3_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 0;\n\tSd = vcx3(t_cpn, t_op1, Sd, Sn, Sm, t_acc, 32:1, t_vec);\n}\n\n:vcx3^vacc^ItCond thv_cpn, Dd, Dn, Dm, fvcx3_imm is TMode=1 & ItCond & thv_c2931=7 & vacc & thv_c2527=6 & thv_c2424=1 & thv_c2323=1 & thv_c1111=0 & thv_cpn & thv_c0606=0 & Dm & Dn & Dd & fvcx3_imm\n{\n\tbuild ItCond;\n\tt_cpn:4 = thv_cpn;\n\tt_op1:4 = fvcx3_imm;\n\tt_acc:1 = vacc;\n\tt_vec:1 = 0;\n\tDd = vcx3(t_cpn, t_op1, Dd, Dn, Dm, t_acc, 64:1, t_vec);\n}\n@endif # CDE" }, { "path": "pypcode/processors/ARM/data/languages/ARM_apcs.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n ;\n offset = *:1 (lr + r3);\n r3 = zext(offset);\n \n \n if (inbounds) goto ;\n offset = *:1 (lr + r12);\n r3 = zext(offset);\n \n \n r3 = r3 * 2;\n \n r12 = lr + r3;\n \n ISAModeSwitch = (r12 & 1) != 1;\n TB = ISAModeSwitch;\n pc = r12 & 0xfffffffe;\n goto [pc];\n ]]>\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM_v45.cspec", "content": "\n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n ;\n offset = *:1 (lr + r3);\n r3 = zext(offset);\n \n \n if (inbounds) goto ;\n offset = *:1 (lr + r12);\n r3 = zext(offset);\n \n \n r3 = r3 * 2;\n \n r12 = lr + r3;\n \n ISAModeSwitch = (r12 & 1) != 1;\n TB = ISAModeSwitch;\n pc = r12 & 0xfffffffe;\n goto [pc];\n ]]>\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM_v45.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARM_win.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n\t\t \n \n \n \n \n \n \n \n \t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMinstructions.sinc", "content": "# Specification for the ARM Version 4, 4T, 5, 5T, 5E\n# The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E\n\n#\n# WARNING NOTE: Be very careful taking a subpiece or truncating a register with :# or (#)\n# The LEBE hybrid language causes endian issues if you do not assign the register to a temp\n# variable and then take a subpiece or truncate.\n#\n\n@if defined(SIMD) || defined(VFPv2) || defined(VFPv3)\n@define INCLUDE_NEON \"\" # Neon instructions included with SIMD, VFPv2 or VFPv3\n@endif\n\n@if defined(T_VARIANT)\n@define AMODE \"TMode=0\"\t# T_VARIANT must restrict ARM instruction decoding and require TMode=0\n@else\n@define AMODE \"epsilon\"\t\t\t# THUMB instructions not supported - ARM only\n@endif\n\n@if defined(T_VARIANT)\n@define VERSION_5_or_T \"\"\n@endif\n@if defined(VERSION_5)\n@define VERSION_5_or_T \"\"\n@endif\n\ndefine token prefix (32)\n pref=(0,31)\n;\n\ndefine token instrArm (32)\n cond=(28,31)\n I25=(25,25)\n P24=(24,24)\n H24=(24,24)\n L24=(24,24)\n U23=(23,23)\n B22=(22,22)\n N22=(22,22)\n S22=(22,22)\n op=(21,24)\n W21=(21,21)\n S20=(20,20)\n L20=(20,20)\n Rn=(16,19)\n RnLo=(0,3)\n msb=(16,20)\n satimm5=(16,20)\n satimm4=(16,19)\n mask=(16,19)\n Rd=(12,15)\n Rd2=(12,15)\n CRd=(12,15)\n CRn=(16,19)\n CRm=(0,3)\n RdHi=(16,19)\n RdLo=(12,15)\n smRd=(16,19)\n smRa=(12,15)\n smRm=(8,11)\n smRn=(0,3)\n immed12=(8,19)\n Rs=(8,11)\n rotate=(8,11)\n immedH=(8,11)\n cpn=(8,11)\n opc1=(21,23)\n opcode1=(20,23)\n opc2=(5,7)\n opcode2=(5,7)\n opcode3=(4,7)\n lsb=(7,11)\n sftimm=(7,11)\n sh=(6,6)\n shft=(5,6)\n immed24=(0,23)\n addr24=(0,23) signed\n offset_12=(0,11)\n immed=(0,7)\n srsMode=(0,4)\n immedL=(0,3)\n immed4=(0,3)\n dbOption=(0,3)\n ibOption=(0,3)\n Rm=(0,3)\n RmHi=(8,11)\n Rm2=(0,3)\n x=(5,5)\n r=(5,5)\n y=(6,6)\n \n\t# Advanced SIMD and VFP instruction fields\n\tD22=(22,22)\n\tN7=(7,7)\n\tL7=(7,7)\n\tQ6=(6,6)\n\tM5=(5,5)\n\tQn0=(16,19)\n\tQd0=(12,15)\n\tQm0=(0,3)\n\tQn1=(16,19)\n\tQd1=(12,15)\n\tQm1=(0,3)\n\tDn0=(16,19)\n\tDd0=(12,15)\n\tDd_1=(12,15)\n\tDd_2=(12,15)\n\tDd_3=(12,15)\n\tDd_4=(12,15)\n\tDd_5=(12,15)\n\tDd_6=(12,15)\n\tDd_7=(12,15)\n\tDd_8=(12,15)\n\tDd_9=(12,15)\n\tDd_10=(12,15)\n\tDd_11=(12,15)\n\tDd_12=(12,15)\n\tDd_13=(12,15)\n\tDd_14=(12,15)\n\tDd_15=(12,15)\n\tDd_16=(12,15)\n\tDm0=(0,3)\n\tDn1=(16,19)\n\tDd1=(12,15)\n\tDm1=(0,3)\n\tDm_3=(0,2)\n\tDm_4=(0,3)\n\tSn0=(16,19)\n\tSd0=(12,15)\n\tSm0=(0,3)\n\tSm0next=(0,3)\n\tSn1=(16,19)\n\tSd1=(12,15)\n\tSm1=(0,3)\n\tSm1next=(0,3)\n\tSm0_3=(0,2)\n\tSm1_3=(0,2)\n\tcmode=(8,11)\n\t\n\t\n\t\n\t# Arbitrary bit fields\n bit31=(31,31)\n bit30=(30,30)\n bit29=(29,29)\n bit28=(28,28)\n c2831=(28,31)\n c2627=(26,27)\n c2531=(25,31)\n c2527=(25,27)\n c2525=(25,25)\n c2427=(24,27)\n c2424=(24,24)\n c2331=(23,31)\n c2327=(23,27)\n c2324=(23,24)\n c2323=(23,23)\n c2222=(22,22)\n c2131=(21,31)\n c2127=(21,27)\n c2124=(21,24)\n c2123=(21,23)\n c2122=(21,22)\n c2121=(21,21)\n c2027=(20,27)\n c2024=(20,24)\n c2022=(20,22)\n c2021=(20,21)\n c2020=(20,20)\n c1921=(19,21)\n c1919=(19,19)\n c1821=(18,21)\n c1819=(18,19)\n c1818=(18,18)\n c1721=(17,21)\n c1719=(17,19)\n c1718=(17,18)\n c1717=(17,17)\n c1631=(16,31)\n c1627=(16,27)\n c1621=(16,21)\n c1620=(16,20)\n c1619=(16,19)\n c1618=(16,18)\n c1617=(16,17)\n c1616=(16,16)\n c1515=(15,15)\n c1415=(14,15)\n c1414=(14,14)\n c1315=(13,15)\n c1313=(13,13)\n c1215=(12,15)\n c1212=(12,12)\n c1115=(11,15)\n c1111=(11,11)\n c1015=(10,15)\n c1011=(10,11)\n c1010=(10,10)\n c0916=(9,16)\n c0915=(9,15)\n c0911=(9,11)\n c0909=(9,9)\n c0815=(8,15)\n c0811=(8,11)\n c0809=(8,9)\n c0808=(8,8)\n c0715=(7,15)\n c0711=(7,11)\n c0709=(7,9)\n c0708=(7,8)\n c0707=(7,7)\n c0615=(6,15)\n c0611=(6,11)\n c0607=(6,7)\n c0606=(6,6)\n c0515=(5,15)\n c0508=(5,8)\n c0507=(5,7)\n c0506=(5,6)\n c0505=(5,5)\n c0431=(4,31)\n c0427=(4,27)\n c0415=(4,15)\n c0411=(4,11)\n c0409=(4,9)\n c0408=(4,8)\n c0407=(4,7)\n c0406=(4,6)\n c0405=(4,5)\n c0404=(4,4)\n c0315=(3,15)\n c0303=(3,3)\n c0215=(2,15)\n c0202=(2,2)\n c0115=(1,15)\n c0101=(1,1)\n c0031=(0,31)\n c0027=(0,27)\n c0014=(0,14)\n c0013=(0,13)\n c0012=(0,12)\n c0011=(0,11)\n c0010=(0,10)\n c0009=(0,9)\n c0008=(0,8)\n c0007=(0,7)\n c0006=(0,6)\n c0005=(0,5)\n c0004=(0,4)\n c0003=(0,3)\n c0002=(0,2)\n c0001=(0,1)\n c0000=(0,0)\n\n# \n# 32-bit Thumb fields which correspond closely with ARM fields for\n# certain coprocessor instructions\n#\n\n@if ENDIAN == \"little\"\n\n\t# Advanced SIMD and VFP instruction fields for 32-bit Little Endian Thumb\n\tthv_D22=(6,6)\n\tthv_N7=(23,23)\n thv_L7=(23,23)\n\tthv_Q6=(22,22)\n\tthv_M5=(21,21)\n\tthv_Qn0=(0,3)\n\tthv_Qd0=(28,31)\n\tthv_Qm0=(16,19)\n\tthv_Qn1=(0,3)\n\tthv_Qd1=(28,31)\n\tthv_Qm1=(16,19)\n\tthv_Dn0=(0,3)\n\tthv_Dd0=(28,31)\n\tthv_Dd_1=(28,31)\n\tthv_Dd_2=(28,31)\n\tthv_Dd_3=(28,31)\n\tthv_Dd_4=(28,31)\n\tthv_Dd_5=(28,31)\n\tthv_Dd_6=(28,31)\n\tthv_Dd_7=(28,31)\n\tthv_Dd_8=(28,31)\n\tthv_Dd_9=(28,31)\n\tthv_Dd_10=(28,31)\n\tthv_Dd_11=(28,31)\n\tthv_Dd_12=(28,31)\n\tthv_Dd_13=(28,31)\n\tthv_Dd_14=(28,31)\n\tthv_Dd_15=(28,31)\n\tthv_Dd_16=(28,31)\n\tthv_Dm0=(16,19)\n\tthv_Dn1=(0,3)\n\tthv_Dd1=(28,31)\n\tthv_Dm1=(16,19)\n\tthv_Dm_3=(16,18)\n\tthv_Dm_4=(16,19)\n\tthv_Sn0=(0,3)\n\tthv_Sd0=(28,31)\n\tthv_Sm0=(16,19)\n\tthv_Sm0next=(16,19)\n\tthv_Sn1=(0,3)\n\tthv_Sd1=(28,31)\n\tthv_Sm1=(16,19)\n\tthv_Sm1next=(16,19)\n\tthv_cmode=(24,27)\n\tthv_Sm0_3=(16,18)\n\tthv_Sm1_3=(16,18)\n\t\n\tthv_Rd=(28,31)\n\tthv_Rt=(28,31)\n\tthv_Rn=(0,3)\n\tthv_Rm=(16,19)\n thv_Rt2=(24,27)\n\tthv_immed=(16,23)\n\tthv_cpn=(8,10)\n\t \n # Arbitrary bit fields for 32-bit Little Endian Thumb\n\n thv_bit31=(15,15)\n thv_bit30=(14,14)\n thv_bit29=(13,13)\n thv_bit28=(12,12)\n thv_bit23=(7,7)\n thv_bit21=(5,5)\n thv_bit20=(4,4)\n thv_bit07=(23,23)\n thv_bit06=(22,22)\n thv_bit00=(16,16)\n thv_c2931=(13,15)\n thv_c2831=(12,15)\n thv_c2828=(12,12)\n thv_c2627=(10,11)\n thv_c2527=(9,11)\n thv_c2525=(9,9)\n thv_c2431=(8,15)\n thv_c2427=(8,11)\n thv_c2424=(8,8)\n thv_c2331=(7,15)\n thv_c2327=(7,11)\n thv_c2324=(7,8)\n thv_c2323=(7,7)\n thv_c2223=(6,7)\n thv_c2222=(6,6)\n thv_c2131=(5,15)\n thv_c2127=(5,11)\n thv_c2124=(5,8)\n thv_c2123=(5,7)\n thv_c2122=(5,6)\n thv_c2121=(5,5)\n thv_c2031=(4,15)\n thv_c2027=(4,11)\n thv_c2024=(4,8)\n thv_c2022=(4,6)\n thv_c2021=(4,5)\n thv_c2020=(4,4)\n thv_c1921=(3,5)\n thv_c1919=(3,3)\n thv_c1821=(2,5)\n thv_c1819=(2,3)\n thv_c1818=(2,2)\n thv_c1721=(1,5)\n thv_c1719=(1,3)\n thv_c1718=(1,2)\n thv_c1717=(1,1)\n thv_c1631=(0,15)\n thv_c1627=(0,11)\n thv_c1621=(0,5)\n thv_c1620=(0,4)\n thv_c1619=(0,3)\n thv_c1618=(0,2)\n thv_c1617=(0,1)\n thv_c1616=(0,0)\n thv_c1515=(31,31)\n thv_c1415=(30,31)\n thv_c1414=(30,30)\n thv_c1313=(29,29)\n thv_c1215=(28,31)\n thv_c1212=(28,28)\n thv_c1111=(27,27)\n thv_c1011=(26,27)\n thv_c1010=(26,26)\n thv_c0911=(25,27)\n thv_c0909=(25,25)\n thv_c0811=(24,27)\n thv_c0809=(24,25)\n thv_c0808=(24,24)\n thv_c0711=(23,27)\n thv_c0709=(23,25)\n thv_c0708=(23,24)\n thv_c0707=(23,23)\n thv_c0611=(22,27)\n thv_c0607=(22,23)\n thv_c0606=(22,22)\n thv_c0508=(21,24)\n thv_c0507=(21,23)\n thv_c0506=(21,22)\n thv_c0505=(21,21)\n thv_c0431=(4,31)\n thv_c0427=(4,27)\n thv_c0411=(20,27)\n thv_c0409=(20,25)\n thv_c0407=(20,23)\n thv_c0406=(20,22)\n thv_c0405=(20,21)\n thv_c0404=(20,20)\n thv_c0303=(19,19)\n thv_c0215=(18,31)\n thv_c0202=(18,18)\n thv_c0101=(17,17)\n thv_c0104=(17,20)\n thv_c0031=(0,31)\n thv_c0027=(0,27)\n thv_c0015=(16,31)\n thv_c0011=(16,27)\n thv_c0010=(16,26)\n thv_c0008=(16,24)\n thv_c0007=(16,23)\n thv_c0006=(16,22)\n thv_c0005=(16,21)\n thv_c0004=(16,20)\n thv_c0003=(16,19)\n thv_c0001=(16,17)\n thv_c0000=(16,16)\n thv_option=(16,19)\n \n@else # ENDIAN == \"big\"\n\n \t# Advanced SIMD and VFP instruction fields for 32-bit Big Endian Thumb\n\tthv_D22=(22,22)\n\tthv_N7=(7,7)\n\tthv_L7=(7,7)\n\tthv_Q6=(6,6)\n\tthv_M5=(5,5)\n\tthv_Qn0=(16,19)\n\tthv_Qd0=(12,15)\n\tthv_Qm0=(0,3)\n\tthv_Qn1=(16,19)\n\tthv_Qd1=(12,15)\n\tthv_Qm1=(0,3)\n\tthv_Dn0=(16,19)\n\tthv_Dd0=(12,15)\n\tthv_Dd_1=(12,15)\n\tthv_Dd_2=(12,15)\n\tthv_Dd_3=(12,15)\n\tthv_Dd_4=(12,15)\n\tthv_Dd_5=(12,15)\n\tthv_Dd_6=(12,15)\n\tthv_Dd_7=(12,15)\n\tthv_Dd_8=(12,15)\n\tthv_Dd_9=(12,15)\n\tthv_Dd_10=(12,15)\n\tthv_Dd_11=(12,15)\n\tthv_Dd_12=(12,15)\n\tthv_Dd_13=(12,15)\n\tthv_Dd_14=(12,15)\n\tthv_Dd_15=(12,15)\n\tthv_Dd_16=(12,15)\n\tthv_Dm0=(0,3)\n\tthv_Dn1=(16,19)\n\tthv_Dd1=(12,15)\n\tthv_Dm1=(0,3)\n\tthv_Dm_3=(0,2)\n\tthv_Dm_4=(0,3)\n\tthv_Sn0=(16,19)\n\tthv_Sd0=(12,15)\n\tthv_Sm0=(0,3)\n\tthv_Sm0next=(0,3)\n\tthv_Sn1=(16,19)\n\tthv_Sd1=(12,15)\n\tthv_Sm1=(0,3)\n\tthv_Sm1next=(0,3)\n\tthv_Sm0_3=(0,2)\n\tthv_Sm1_3=(0,2)\n\tthv_cmode=(8,11)\n\t\n\tthv_Rd=(12,15)\n\tthv_Rt=(12,15)\n\tthv_Rn=(16,19)\n\tthv_Rm=(0,3)\n thv_Rt2=(8,11)\n\tthv_immed=(0,7)\n\tthv_cpn=(24,26)\n\t \n # Arbitrary bit fields for 32-bit Big Endian Thumb\n thv_bit31=(31,31)\n thv_bit30=(30,30)\n thv_bit29=(29,29)\n thv_bit28=(28,28)\n thv_bit23=(23,23)\n thv_bit21=(21,21)\n thv_bit20=(20,20)\n thv_bit07=(7,7)\n thv_bit06=(6,6)\n thv_bit00=(0,0)\n thv_c2931=(29,31)\n thv_c2831=(28,31)\n thv_c2828=(28,28)\n thv_c2627=(26,27)\n thv_c2527=(25,27)\n thv_c2525=(25,25)\n thv_c2431=(24,31)\n thv_c2427=(24,27)\n thv_c2424=(24,24)\n thv_c2331=(23,31)\n thv_c2327=(23,27)\n thv_c2324=(23,24)\n thv_c2323=(23,23)\n thv_c2223=(22,23)\n thv_c2222=(22,22)\n thv_c2131=(21,31)\n thv_c2127=(21,27)\n thv_c2124=(21,24)\n thv_c2123=(21,23)\n thv_c2122=(21,22)\n thv_c2121=(21,21)\n thv_c2031=(20,31)\n thv_c2027=(20,27)\n thv_c2024=(20,24)\n thv_c2022=(20,22)\n thv_c2021=(20,21)\n thv_c2020=(20,20)\n thv_c1921=(19,21)\n thv_c1919=(19,19)\n thv_c1821=(18,21)\n thv_c1819=(18,19)\n thv_c1818=(18,18)\n thv_c1721=(17,21)\n thv_c1719=(17,19)\n thv_c1718=(17,18)\n thv_c1717=(17,17)\n thv_c1631=(16,31)\n thv_c1627=(16,27)\n thv_c1621=(16,21)\n thv_c1620=(16,20)\n thv_c1619=(16,19)\n thv_c1618=(16,18)\n thv_c1617=(16,17)\n thv_c1616=(16,16)\n thv_c1515=(15,15)\n thv_c1415=(14,15)\n thv_c1414=(14,14)\n thv_c1313=(13,13)\n thv_c1215=(12,15)\n thv_c1212=(12,12)\n thv_c1111=(11,11)\n thv_c1011=(10,11)\n thv_c1010=(10,10)\n thv_c0911=(9,11)\n thv_c0909=(9,9)\n thv_c0811=(8,11)\n thv_c0809=(8,9)\n thv_c0808=(8,8)\n thv_c0711=(7,11)\n thv_c0709=(7,9)\n thv_c0708=(7,8)\n thv_c0707=(7,7)\n thv_c0611=(6,11)\n thv_c0607=(6,7)\n thv_c0606=(6,6)\n thv_c0508=(5,8)\n thv_c0507=(5,7)\n thv_c0506=(5,6)\n thv_c0505=(5,5)\n thv_c0431=(4,31)\n thv_c0427=(4,27)\n thv_c0411=(4,11)\n thv_c0409=(4,9)\n thv_c0407=(4,7)\n thv_c0406=(4,6)\n thv_c0405=(4,5)\n thv_c0404=(4,4)\n thv_c0303=(3,3)\n thv_c0215=(2,15)\n thv_c0202=(2,2)\n thv_c0101=(1,1)\n thv_c0104=(1,4)\n thv_c0031=(0,31)\n thv_c0027=(0,27)\n thv_c0015=(0,15)\n thv_c0011=(0,11)\n thv_c0010=(0,10)\n thv_c0008=(0,8)\n thv_c0007=(0,7)\n thv_c0006=(0,6)\n thv_c0005=(0,5)\n thv_c0004=(0,4)\n thv_c0003=(0,3)\n thv_c0001=(0,1)\n thv_c0000=(0,0)\n thv_option=(0,3)\n \n@endif # ENDIAN = \"big\"\n\n;\n\nattach variables [ Rn Rd Rs Rm RdHi RdLo smRd smRn smRm smRa RmHi RnLo ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ];\nattach variables [ Rd2 Rm2 ] [ r1 _ r3 _ r5 _ r7 _ r9 _ r11 _ sp _ _ _ ]; # see LDREXD\nattach variables [ CRd CRn CRm ] [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ]; \t\t\t\t\t\t\t\t\t\t\nattach variables [ thv_Rd thv_Rn thv_Rt thv_Rt2 ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ];\n\nattach names [ cpn ] [ p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 ];\nattach names [ thv_cpn ] [ p0 p1 p2 p3 p4 p5 p6 p7 ];\nattach names [ ibOption ] [ opt0 opt1 opt2 opt3 opt4 opt5 opt6 opt7 opt8 opt9 opt10 opt11 opt12 opt13 opt14 SY ];\nattach names [ dbOption ] [ opt0 opt1 OSHST OSH opt4 opt5 NSHST NSH opt8 opt9 ISHST ISH opt12 opt13 ST SY ];\n\nmacro addflags(op1,op2) {\n tmpCY = carry(op1,op2);\n tmpOV = scarry(op1,op2);\n}\n\n# NOTE: unlike x86, carry flag is SET if there is NO borrow\nmacro subflags(op1,op2) {\n tmpCY = op2 <= op1;\n tmpOV = sborrow(op1,op2);\n}\n\nmacro logicflags() {\n tmpCY = shift_carry;\n tmpOV = OV;\n}\n\nmacro CVunaffected() {\n tmpCY = CY;\n tmpOV = OV;\n}\n\nmacro resultflags(result) {\n tmpNG = result s< 0;\n tmpZR = result == 0;\n}\n\nrn: pc is pc & c1619=15 { tmp:4 = inst_start+8; export tmp; }\nrn: Rn is Rn\t\t\t\t{ export Rn; }\n\nrm: pc is pc & Rm=15 { tmp:4 = inst_start+8; export tmp; }\nrm: Rm is Rm\t\t\t\t{ export Rm; }\n\nrs: pc is pc & Rs=15 { tmp:4 = inst_start+8; export tmp; }\nrs: Rs is Rs\t\t\t\t{ export Rs; }\n\ncc: \"eq\" is cond=0 { export ZR; }\ncc: \"ne\" is cond=1 { tmp:1 = !ZR; export tmp; }\ncc: \"cs\" is cond=2 { export CY; }\ncc: \"cc\" is cond=3 { tmp:1 = !CY; export tmp; }\ncc: \"mi\" is cond=4 { export NG; }\ncc: \"pl\" is cond=5 { tmp:1 = !NG; export tmp; }\ncc: \"vs\" is cond=6 { export OV; }\ncc: \"vc\" is cond=7 { tmp:1 = !OV; export tmp; }\ncc: \"hi\" is cond=8 { tmp:1 = CY && (!ZR); export tmp; }\ncc: \"ls\" is cond=9 { tmp:1 = (!CY) || ZR; export tmp; }\ncc: \"ge\" is cond=10 { tmp:1 = (NG==OV); export tmp; }\ncc: \"lt\" is cond=11 { tmp:1 = (NG!=OV); export tmp; }\ncc: \"gt\" is cond=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; }\ncc: \"le\" is cond=13 { tmp:1 = ZR || (NG!=OV); export tmp; }\n\nCOND: cc is $(AMODE) & cc\t\t { if (!cc) goto inst_next; } # Execute conditionally\nCOND: is $(AMODE) & cond=14\t { }\t\t# Always execute\n#COND: is $(AMODE) & cond=15\t { }\t# Always execute - deprecated, should not be used.\n\n@if defined(INCLUDE_NEON) # Unconditional Neon Thumb instructions share many Conditional Neon ARM constructors \nCOND: ItCond is TMode=1 & thv_c2831=14 & cond & ItCond \t { }\t\t\t # ItCond execute\n#COND: ItCond is TMode=1 & thv_c2831=15 & cond & ItCond \t { }\t\t\t # ItCond execute\n@endif\n\nSBIT_CZNO: is S20=0\t { } # Do nothing to the flag bits\nSBIT_CZNO: \"s\" is S20=1\t { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }\nSBIT_ZN: is S20=0\t { } # Do nothing to the flag bits\nSBIT_ZN: \"s\" is S20=1\t { ZR = tmpZR; NG = tmpNG; }\n\nAddr24: reloc is addr24 [ reloc = (inst_next+4) + (4*addr24); ]\t { export *[ram]:4 reloc; }\n\n# see blx(1) instruction\n@if defined(T_VARIANT) && defined(VERSION_5)\n\nHAddr24: reloc is addr24 & H24\n [ reloc = ((inst_next+4) + (4*addr24) + (2*H24)) & 0xFFFFFFFF; TMode=1; globalset(reloc,TMode); ]\n { export *[ram]:4 reloc; }\n@endif # T_VARIANT && VERSION_5\n\n@if defined(VERSION_5E)\n\nXBIT: \"b\" is x=0 & smRn { local tmpRn = smRn; tmp:2 = tmpRn:2; export tmp; }\nXBIT: \"t\" is x=1 & smRn { local tmpRn = smRn; tmp:2 = tmpRn(2); export tmp; }\n\nYBIT: \"b\" is y=0 & smRm { local tmpRm = smRm; tmp:2 = tmpRm:2; export tmp; }\nYBIT: \"t\" is y=1 & smRm { local tmpRm = smRm; tmp:2 = tmpRm(2); export tmp; }\n\n@endif # VERSION_5E\n\n\n\n#####################\n###### shift1 ######\n#####################\n\nshift1: \"#\"^value \t\tis I25=1 & immed & rotate\n [ value=((immed<<(32-rotate*2))|(immed>>(rotate*2))) $and 0xffffffff; ]\n{\n local tmp:4 = (value >> 31); shift_carry = ((rotate == 0:1) && CY) || ((rotate != 0:1) && tmp(0)); export *[const]:4 value;\n}\n\n####################\ndefine pcodeop coproc_moveto_Main_ID;\ndefine pcodeop coproc_moveto_Cache_Type;\ndefine pcodeop coproc_moveto_TCM_Status;\ndefine pcodeop coproc_moveto_TLB_Type;\ndefine pcodeop coproc_moveto_Control;\ndefine pcodeop coproc_moveto_Auxiliary_Control;\ndefine pcodeop coproc_moveto_Coprocessor_Access_Control;\ndefine pcodeop coproc_moveto_Secure_Configuration;\ndefine pcodeop coproc_moveto_Secure_Debug_Enable;\ndefine pcodeop coproc_moveto_NonSecure_Access_Control;\ndefine pcodeop coproc_moveto_Translation_table_base_0;\ndefine pcodeop coproc_moveto_Translation_table_base_1;\ndefine pcodeop coproc_moveto_Translation_table_control;\ndefine pcodeop coproc_moveto_Domain_Access_Control;\ndefine pcodeop coproc_moveto_Data_Fault_Status;\ndefine pcodeop coproc_moveto_Instruction_Fault_Status;\ndefine pcodeop coproc_moveto_Instruction_Fault_Address;\ndefine pcodeop coproc_moveto_Fault_Address;\ndefine pcodeop coproc_moveto_Instruction_Fault;\ndefine pcodeop coproc_moveto_Wait_for_interrupt;\ndefine pcodeop coproc_moveto_Invalidate_Entire_Instruction;\ndefine pcodeop coproc_moveto_Invalidate_Instruction_Cache_by_MVA;\ndefine pcodeop coproc_moveto_Flush_Prefetch_Buffer;\ndefine pcodeop coproc_moveto_Invalidate_Entire_Data_cache;\ndefine pcodeop coproc_moveto_Invalidate_Entire_Data_by_MVA;\ndefine pcodeop coproc_moveto_Invalidate_Entire_Data_by_Index;\ndefine pcodeop coproc_moveto_Clean_Entire_Data_Cache;\ndefine pcodeop coproc_moveto_Clean_Data_Cache_by_MVA;\ndefine pcodeop coproc_moveto_Clean_Data_Cache_by_Index;\ndefine pcodeop coproc_moveto_Data_Synchronization;\ndefine pcodeop coproc_moveto_Data_Memory_Barrier;\ndefine pcodeop coproc_moveto_Invalidate_Entire_Data_Cache;\ndefine pcodeop coproc_moveto_Invalidate_Data_Cache_by_MVA;\ndefine pcodeop coproc_moveto_Invalidate_unified_TLB_unlocked;\ndefine pcodeop coproc_moveto_Invalidate_unified_TLB_by_MVA;\ndefine pcodeop coproc_moveto_Invalidate_unified_TLB_by_ASID_match;\ndefine pcodeop coproc_moveto_FCSE_PID;\ndefine pcodeop coproc_moveto_Context_ID;\ndefine pcodeop coproc_moveto_User_RW_Thread_and_Process_ID;\ndefine pcodeop coproc_moveto_User_R_Thread_and_Process_ID;\ndefine pcodeop coproc_moveto_Privileged_only_Thread_and_Process_ID;\ndefine pcodeop coproc_moveto_Peripherial_Port_Memory_Remap;\ndefine pcodeop coproc_moveto_Feature_Identification;\ndefine pcodeop coproc_moveto_ISA_Feature_Identification;\ndefine pcodeop coproc_moveto_Peripheral_Port_Memory_Remap;\ndefine pcodeop coproc_moveto_Control_registers;\ndefine pcodeop coproc_moveto_Security_world_control;\ndefine pcodeop coproc_moveto_Translation_table;\ndefine pcodeop coproc_moveto_Instruction_cache;\ndefine pcodeop coproc_moveto_Data_cache_operations;\ndefine pcodeop coproc_moveto_Identification_registers;\ndefine pcodeop coproc_moveto_Peripheral_System;\n\ndefine pcodeop coproc_movefrom_Main_ID;\ndefine pcodeop coproc_movefrom_Cache_Type;\ndefine pcodeop coproc_movefrom_TCM_Status;\ndefine pcodeop coproc_movefrom_TLB_Type;\ndefine pcodeop coproc_movefrom_Control;\ndefine pcodeop coproc_movefrom_Auxiliary_Control;\ndefine pcodeop coproc_movefrom_Coprocessor_Access_Control;\ndefine pcodeop coproc_movefrom_Secure_Configuration;\ndefine pcodeop coproc_movefrom_Secure_Debug_Enable;\ndefine pcodeop coproc_movefrom_NonSecure_Access_Control;\ndefine pcodeop coproc_movefrom_Translation_table_base_0;\ndefine pcodeop coproc_movefrom_Translation_table_base_1;\ndefine pcodeop coproc_movefrom_Translation_table_control;\ndefine pcodeop coproc_movefrom_Domain_Access_Control;\ndefine pcodeop coproc_movefrom_Data_Fault_Status;\ndefine pcodeop coproc_movefrom_Instruction_Fault;\ndefine pcodeop coproc_movefrom_Fault_Address;\ndefine pcodeop coproc_movefrom_Instruction_Fault_Status;\ndefine pcodeop coproc_movefrom_Instruction_Fault_Address;\ndefine pcodeop coproc_movefrom_Wait_for_interrupt;\ndefine pcodeop coproc_movefrom_Invalidate_Entire_Instruction;\ndefine pcodeop coproc_movefrom_Invalidate_Instruction_Cache_by_MVA;\ndefine pcodeop coproc_movefrom_Flush_Prefetch_Buffer;\ndefine pcodeop coproc_movefrom_Invalidate_Entire_Data_cache;\ndefine pcodeop coproc_movefrom_Invalidate_Entire_Data_by_MVA;\ndefine pcodeop coproc_movefrom_Invalidate_Entire_Data_by_Index;\ndefine pcodeop coproc_movefrom_Clean_Entire_Data_Cache;\ndefine pcodeop coproc_movefrom_Clean_Data_Cache_by_MVA;\ndefine pcodeop coproc_movefrom_Clean_Data_Cache_by_Index;\ndefine pcodeop coproc_movefrom_Data_Synchronization;\ndefine pcodeop coproc_movefrom_Data_Memory_Barrier;\ndefine pcodeop coproc_movefrom_Invalidate_Entire_Data_Cache;\ndefine pcodeop coproc_movefrom_Invalidate_Data_Cache_by_MVA;\ndefine pcodeop coproc_movefrom_Invalidate_unified_TLB_unlocked;\ndefine pcodeop coproc_movefrom_Invalidate_unified_TLB_by_MVA;\ndefine pcodeop coproc_movefrom_Invalidate_unified_TLB_by_ASID_match;\ndefine pcodeop coproc_movefrom_FCSE_PID;\ndefine pcodeop coproc_movefrom_Context_ID;\ndefine pcodeop coproc_movefrom_User_RW_Thread_and_Process_ID;\ndefine pcodeop coproc_movefrom_User_R_Thread_and_Process_ID;\ndefine pcodeop coproc_movefrom_Privileged_only_Thread_and_Process_ID;\ndefine pcodeop coproc_movefrom_Peripherial_Port_Memory_Remap;\ndefine pcodeop coproc_movefrom_Feature_Identification;\ndefine pcodeop coproc_movefrom_ISA_Feature_Identification;\ndefine pcodeop coproc_movefrom_Peripheral_Port_Memory_Remap;\ndefine pcodeop coproc_movefrom_Control_registers;\ndefine pcodeop coproc_movefrom_Security_world_control;\ndefine pcodeop coproc_movefrom_Translation_table;\ndefine pcodeop coproc_movefrom_Instruction_cache;\ndefine pcodeop coproc_movefrom_Data_cache_operations;\ndefine pcodeop coproc_movefrom_Identification_registers;\ndefine pcodeop coproc_movefrom_Peripheral_System;\n\nmcrOperands: cpn,opc1,Rd,CRn,CRm,opc2 is CRm & opc2 & cpn & CRn & opc1 & Rd { }\n\n#####################\n###### shift2 ######\n#####################\n\nshift2: rm \t \t\tis I25=0 & sftimm=0 & c0406=0 & rm\n{\n shift_carry = CY; export rm;\n}\n\nshift2: rm, \"lsl #\"^sftimm \tis I25=0 & sftimm & c0406=0 & rm\n{\n local tmp1=(rm>>(32-sftimm))&1; shift_carry=tmp1(0); local tmp2=rm<>31); shift_carry=tmp1(0); tmp2:4=0; export tmp2;\n}\n\nshift2: rm, \"lsr #\"^sftimm\tis I25=0 & sftimm & c0406=2 & rm\n{\n local tmp1=(rm>>(sftimm-1))&1; shift_carry=tmp1(0); local tmp2=rm>>sftimm; export tmp2;\n}\n\nshift2: rm, \"asr #32\"\t\tis I25=0 & sftimm=0 & c0406=4 & rm\n{\n local tmp1=(rm>>31); shift_carry=tmp1(0); local tmp2 = rm s>> 32; export tmp2;\n}\n\nshift2: rm, \"asr #\"^sftimm\tis I25=0 & sftimm & c0406=4 & rm\n{\n local tmp1=(rm>>(sftimm-1))&1; shift_carry=tmp1(0); local tmp2=rm s>> sftimm; export tmp2;\n}\n\nshift2: rm, \"rrx\"\t\tis I25=0 & c0411=6 & rm\n{\n local tmp1=rm&1; shift_carry=tmp1(0); local tmp2 = (zext(CY)<<31)|(rm>>1); export tmp2;\n}\n\nshift2: rm, \"ror #\"^sftimm\tis I25=0 & sftimm & c0406=6 & rm\n{\n local tmp1=(rm>>sftimm)|(rm<<(32-sftimm)); local tmp2=(tmp1>>31)&1; shift_carry=tmp2(0); export tmp1;\n}\n\n#####################\n###### shift3 ######\n#####################\n\nshift3: rm, \"lsl \"^rs \t\tis I25=0 & rs & c0407=1 & rm\n{\n local sa=rs&0xff; local tmp1=(rm>>(32-sa))&1; shift_carry=((sa==0:4)&&CY) || ((sa!=0:4)&&tmp1(0)); local tmp2=rm<>(sa-1))&1; shift_carry=((sa==0:4)&&CY) || ((sa!=0:4)&&tmp1(0)); local tmp2=rm>>sa; export tmp2;\n}\n\nshift3: rm, \"asr \"^rs\t\tis I25=0 & rs & c0407=5 & rm\n{\n local sa=rs&0xff; local tmp1=(rm s>>(sa-1))&1; shift_carry=((sa==0:4)&&CY) || ((sa!=0:4)&&tmp1(0)); local tmp2=rm s>> sa; export tmp2;\n}\n\nshift3: rm, \"ror \"^rs\t\tis I25=0 & rs & c0407=7 & rm\n{\n local sa=rs&0x1f; local tmp1=(rm>>sa)|(rm<<(32-sa)); local tmp2=tmp1>>31; shift_carry=(((rs&0xff)==0:4)&&CY) || (((rs&0xff)!=0:4)&&tmp2(0)); export tmp1;\n}\n\n\n#####################\n###### shift4 ######\n#####################\n@if defined(VERSION_6)\n\nshift4: rm \t \t\tis sftimm=0 & sh=0 & rm\n{\n shift_carry = CY; export rm;\n}\n\nshift4: rm, \"lsl #\"^sftimm \tis sftimm & sh=0 & rm\n{\n local tmp1=(rm>>(32-sftimm))&1; shift_carry=tmp1(0); local tmp2=rm<>31); shift_carry=tmp1(0); local tmp2 = rm s>> 32; export tmp2;\n}\n\nshift4: rm, \"asr #\"^sftimm\tis sftimm & sh=1 & rm\n{\n local tmp1=(rm>>(sftimm-1))&1; shift_carry=tmp1(0); local tmp2=rm s>> sftimm; export tmp2;\n}\n\n@endif # VERSION_6\n\n#####################\n###### ror1 ######\n#####################\n@if defined(VERSION_6)\n\nror1: rm \t\tis c1011=0 & rm\n{\n local tmp = rm;\n export tmp;\n}\n\nror1: rm, \"ror #8\"\t\tis c1011=1 & rm\n{\n local tmp = (rm <<24)| (rm >> 8);\n export tmp;\n}\n\nror1: rm, \"ror #16\"\t\tis c1011=2 & rm\n{\n local tmp = (rm << 16) | (rm >> 16);\n export tmp;\n}\n\nror1: rm, \"ror #24\"\t\tis c1011=3 & rm\n{\n local tmp = (rm << 8) | (rm >> 24);\n export tmp;\n}\n\n@endif # VERSION_6\n\n#####################\n# addrmode2 is the resulting address for Addressing Mode 2\n# it takes care of bits 27-0, except for the B and L flags and the Rd register\n# the Rn register is taken care of including any possible write-back\n# it returns a varnode containing the address\n#####################\n\n# addr2shift is the register rm shifting portion of Addressing Mode 2\naddr2shift: rm\t\t\t\t\tis c0411=0 & rm\t\t\t\t\t\t\t{ export rm; }\naddr2shift: rm,\"lsl #\"^sftimm\tis sftimm & shft=0 & c0404=0 & rm\t\t{ local tmp = rm << sftimm; export tmp; }\naddr2shift: rm,\"lsr #\"^sftimm\tis sftimm & shft=1 & c0404=0 & rm\t\t{ local tmp = rm >> sftimm; export tmp; }\naddr2shift: rm,\"lsr #32\"\t\tis sftimm=0 & shft=1 & c0404=0 & rm\t\t{ tmp:4 = 0; export tmp; }\naddr2shift: rm,\"asr #\"^sftimm\tis sftimm & shft=2 & c0404=0 & rm\t\t{ local tmp = rm s>> sftimm; export tmp; }\naddr2shift: rm,\"asr #32\"\t\tis sftimm=0 & shft=2 & c0404=0 & rm\t\t{ local tmp = rm s>> 32; export tmp; }\naddr2shift: rm,\"ror #\"^sftimm\tis sftimm & shft=3 & c0404=0 & rm\t\t{ local tmp = (rm>>sftimm) | (rm<<(32-sftimm)); export tmp; }\naddr2shift: rm,\"rrx\"\t\t\tis sftimm=0 & shft=3 & c0404=0 & rm\t\t{ tmp:4 = zext(CY); tmp = (tmp<<31) | (rm>>1); export tmp; }\n\n # no writeback\n\naddrmode2: [reloff]\t\tis I25=0 & P24=1 & U23=1 & W21=0 & c1619=15 & offset_12\n [ reloff = inst_start + 8 + offset_12; ]\n{\n export *[const]:4 reloff;\n}\n\naddrmode2: [reloff]\t\tis I25=0 & P24=1 & U23=0 & W21=0 & c1619=15 & offset_12\n [ reloff = inst_start + 8 - offset_12; ]\n{\n export *[const]:4 reloff;\n}\n\naddrmode2: [rn,\"#\"^offset_12]\tis I25=0 & P24=1 & U23=1 & W21=0 & rn & offset_12\t{ local tmp = rn + offset_12; export tmp; }\naddrmode2: [rn,\"#\"^noff]\t\tis I25=0 & P24=1 & U23=0 & W21=0 & rn & offset_12 [ noff = -offset_12; ]\t{ local tmp = rn + noff; export tmp; }\naddrmode2: [rn,addr2shift]\tis I25=1 & P24=1 & U23=1 & W21=0 & rn & addr2shift\t{ local tmp = rn + addr2shift; export tmp; }\naddrmode2: [rn,-addr2shift]\tis I25=1 & P24=1 & U23=0 & W21=0 & rn & addr2shift \t{ local tmp = rn - addr2shift; export tmp; }\n # pre-indexed writeback\naddrmode2: [rn,\"#\"^offset_12]!\tis I25=0 & P24=1 & U23=1 & W21=1 & rn & offset_12\t{ rn = rn + offset_12; export rn; }\naddrmode2: [rn,\"#\"^noff]!\t\tis I25=0 & P24=1 & U23=0 & W21=1 & rn & offset_12 [ noff = -offset_12; ]\t{ rn = rn + noff; export rn; }\naddrmode2: [rn,addr2shift]!\tis I25=1 & P24=1 & U23=1 & W21=1 & rn & addr2shift\t{ rn = rn + addr2shift; export rn; }\naddrmode2: [rn,-addr2shift]!\tis I25=1 & P24=1 & U23=0 & W21=1 & rn & addr2shift\t{ rn = rn - addr2shift; export rn; }\n # post-indexed writeback\naddrmode2: [rn],\"#\"^offset_12\tis I25=0 & P24=0 & U23=1 & W21=0 & rn & offset_12\t{ local tmp = rn; rn = rn + offset_12; export tmp; }\naddrmode2: [rn],\"#\"^noff\t\tis I25=0 & P24=0 & U23=0 & W21=0 & rn & offset_12 [ noff = -offset_12; ]\t{ local tmp = rn; rn = rn + noff; export tmp; }\naddrmode2: [rn],addr2shift \tis I25=1 & P24=0 & U23=1 & W21=0 & rn & addr2shift\t{ local tmp = rn; rn = rn + addr2shift; export tmp; }\naddrmode2: [rn],-addr2shift is I25=1 & P24=0 & U23=0 & W21=0 & rn & addr2shift\t{ local tmp = rn; rn = rn - addr2shift; export tmp; }\n # special-form post-indexed writeback for ldrbt, ldrt, strbt, etc.\naddrmode2: [rn],\"#\"^offset_12 \tis I25=0 & P24=0 & U23=1 & W21=1 & rn & offset_12\t{ local tmp = rn; rn = rn + offset_12; export tmp; }\naddrmode2: [rn],\"#\"^noff\t\tis I25=0 & P24=0 & U23=0 & W21=1 & rn & offset_12 [ noff = -offset_12; ]\t{ local tmp = rn; rn = rn + noff; export tmp; }\naddrmode2: [rn],addr2shift \tis I25=1 & P24=0 & U23=1 & W21=1 & rn & addr2shift\t{ local tmp = rn; rn = rn + addr2shift; export tmp; }\naddrmode2: [rn],-addr2shift is I25=1 & P24=0 & U23=0 & W21=1 & rn & addr2shift\t{ local tmp = rn; rn = rn - addr2shift; export tmp; }\n\n###########################\n# addrmode3 is the resulting address for Addressing Mode 3\n# it takes care of bits 27-0, except for the L, S, and H flags and the Rd register\n# the Rn register is taken care of including any possible write-back\n# it returns a varnode containing the address\n###########################\n\naddrmode3: [reloff]\t\tis P24=1 & U23=1 & c2122=2 & c1619=15 & immedH & immedL\n [ reloff=inst_start+8+((immedH<<4) | immedL);]\n{\n export *:4 reloff;\n}\n\naddrmode3: [reloff]\t\tis P24=1 & U23=0 & c2122=2 & c1619=15 & immedH & immedL\n [ reloff=inst_start+8-((immedH<<4) | immedL);]\n{\n export *:4 reloff;\n}\n\naddrmode3: [rn,\"#\"^off8]\t\tis P24=1 & U23=1 & c2122=2 & rn & immedH & immedL\n [ off8=(immedH<<4)|immedL;]\n{\n local tmp = rn + off8; export tmp;\n}\n\naddrmode3: [rn,\"#\"^noff8]\t\tis P24=1 & U23=0 & c2122=2 & rn & immedH & immedL\n [ noff8=-((immedH<<4)|immedL);]\n{\n local tmp = rn + noff8; export tmp;\n}\n\naddrmode3: [rn,rm]\t\tis P24=1 & U23=1 & c2122=0 & rn & c0811=0 & rm\n{\n local tmp = rn + rm; export tmp;\n}\n\naddrmode3: [rn,-rm]\t\tis P24=1 & U23=0 & c2122=0 & rn & c0811=0 & rm\n{\n local tmp = rn - rm; export tmp;\n}\n\naddrmode3: [rn,\"#\"^off8]!\t\tis P24=1 & U23=1 & c2122=3 & rn & immedH & immedL\n [ off8=(immedH<<4)|immedL;]\n{\n rn=rn + off8; export rn;\n}\n\naddrmode3: [rn,\"#\"^noff8]!\t\tis P24=1 & U23=0 & c2122=3 & rn & immedH & immedL\n [ noff8=-((immedH<<4)|immedL);]\n{\n rn=rn + noff8; export rn;\n}\n\naddrmode3: [rn,rm]!\t\tis P24=1 & U23=1 & c2122=1 & rn & c0811=0 & rm\n{\n rn = rn+rm; export rn;\n}\n\naddrmode3: [rn,-rm]!\t\tis P24=1 & U23=0 & c2122=1 & rn & c0811=0 & rm\n{\n rn = rn - rm; export rn;\n}\n\naddrmode3: [rn],\"#\"^off8\t\tis P24=0 & U23=1 & c2222=1 & rn & immedH & immedL\n [ off8=(immedH<<4)|immedL;]\n{\n local tmp=rn; rn=rn + off8; export tmp;\n}\n\naddrmode3: [rn],\"#\"^noff8\t\tis P24=0 & U23=0 & c2222=1 & rn & immedH & immedL\n [ noff8=-((immedH<<4)|immedL);]\n{\n local tmp=rn; rn=rn + noff8; export tmp;\n}\n\naddrmode3: [rn],rm\t\tis P24=0 & U23=1 & c2222=0 & rn & c0811=0 & rm\n{\n local tmp=rn; rn=rn+rm; export tmp;\n}\n\naddrmode3: [rn],-rm\t\tis P24=0 & U23=0 & c2222=0 & rn & c0811=0 & rm\n{\n local tmp=rn; rn=rn-rm; export tmp;\n}\n\n############################\n# Addressing Mode 4. These 4 types take care of the register_list argument in Addressing Mode 4.\n############################\n\n\n# ldlist_inc is the list of registers to be loaded using IA or IB in Addressing Mode 4\nlinc15: r0\t\t\tis c0000=1 & r0\t\t\t\t{ r0 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc15:\t\t\t\tis c0000=0\t\t\t\t{ }\nlinc14: linc15,r1\tis c0101=1 & linc15 & r1\t{ r1 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc14: r1\t\t\tis c0101=1 & c0000=0 & r1\t{ r1 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc14: linc15\t\tis c0101=0 & linc15\t\t{ }\nlinc13: linc14,r2\tis c0202=1 & linc14 & r2\t{ r2 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc13: r2\t\t\tis c0202=1 & c0001=0 & r2\t{ r2 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc13: linc14\t\tis c0202=0 & linc14\t\t{ }\nlinc12: linc13,r3\tis c0303=1 & linc13 & r3\t{ r3 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc12: r3\t\t\tis c0303=1 & c0002=0 & r3\t{ r3 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc12: linc13\t\tis c0303=0 & linc13\t\t{ }\nlinc11: linc12,r4\tis c0404=1 & linc12 & r4\t{ r4 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc11: r4\t\t\tis c0404=1 & c0003=0 & r4\t{ r4 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc11: linc12\t\tis c0404=0 & linc12\t\t{ }\nlinc10: linc11,r5\tis c0505=1 & linc11 & r5\t{ r5 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc10: r5\t\t\tis c0505=1 & c0004=0 & r5\t{ r5 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc10: linc11\t\tis c0505=0 & linc11\t\t{ }\nlinc9: linc10,r6\tis c0606=1 & linc10 & r6\t{ r6 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc9: r6\t\t\tis c0606=1 & c0005=0 & r6\t{ r6 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc9: linc10\t\tis c0606=0 & linc10\t\t{ }\nlinc8: linc9,r7\t\tis c0707=1 & linc9 & r7\t\t{ r7 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc8: r7\t\t\tis c0707=1 & c0006=0 & r7\t{ r7 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc8: linc9\t\tis c0707=0 & linc9\t\t{ }\nlinc7: linc8,r8\t\tis c0808=1 & linc8 & r8\t\t{ r8 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc7: r8\t\t\tis c0808=1 & c0007=0 & r8\t{ r8 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc7: linc8\t\tis c0808=0 & linc8\t\t{ }\nlinc6: linc7,r9\t\tis c0909=1 & linc7 & r9\t\t{ r9 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc6: r9\t\t\tis c0909=1 & c0008=0 & r9\t{ r9 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc6: linc7\t\tis c0909=0 & linc7\t\t{ }\nlinc5: linc6,r10\tis c1010=1 & linc6 & r10\t{ r10 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc5: r10\t\t\tis c1010=1 & c0009=0 & r10\t{ r10 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc5: linc6\t\tis c1010=0 & linc6\t\t{ }\nlinc4: linc5,r11\tis c1111=1 & linc5 & r11\t{ r11 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc4: r11\t\t\tis c1111=1 & c0010=0 & r11\t{ r11 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc4: linc5\t\tis c1111=0 & linc5\t\t{ }\nlinc3: linc4,r12\tis c1212=1 & linc4 & r12\t{ r12 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc3: r12\t\t\tis c1212=1 & c0011=0 & r12\t{ r12 = * mult_addr; mult_addr = mult_addr + 4; }\nlinc3: linc4\t\tis c1212=0 & linc4\t\t{ }\nlinc2: linc3,sp\t\tis c1313=1 & linc3 & sp\t\t{ sp = * mult_addr; mult_addr = mult_addr + 4; }\nlinc2: sp\t\t\tis c1313=1 & c0012=0 & sp\t{ sp = * mult_addr; mult_addr = mult_addr + 4; }\nlinc2: linc3\t\tis c1313=0 & linc3\t\t{ }\nlinc1: linc2,lr\t\tis c1414=1 & linc2 & lr\t\t{ lr = * mult_addr; mult_addr = mult_addr + 4; }\nlinc1: lr\t\t\tis c1414=1 & c0013=0 & lr\t{ lr = * mult_addr; mult_addr = mult_addr + 4; }\nlinc1: linc2\t\tis c1414=0 & linc2\t\t{ }\nlinc0: linc1,pc\t\tis c1515=1 & linc1 & pc\t\t{ pc = * mult_addr; mult_addr = mult_addr + 4; }\nlinc0: pc\t\t\tis c1515=1 & c0014=0 & pc\t{ pc = * mult_addr; mult_addr = mult_addr + 4; }\nlinc0: linc1\t\tis c1515=0 & linc1\t\t{ }\nldlist_inc: {linc0}\tis linc0\t\t\t\t{ }\n\n# stlist_inc is the list of registers to be stored using IA or IB in Addressing Mode 4\nsinc15: r0\t\t\tis c0000=1 & r0\t\t\t\t{ * mult_addr = r0; mult_addr = mult_addr + 4; }\nsinc15:\t\t\t\tis c0000=0\t\t\t\t{ }\nsinc14: sinc15,r1\tis c0101=1 & sinc15 & r1\t{ * mult_addr = r1; mult_addr = mult_addr + 4; }\nsinc14: r1\t\t\tis c0101=1 & c0000=0 & r1\t{ * mult_addr = r1; mult_addr = mult_addr + 4; }\nsinc14: sinc15\t\tis c0101=0 & sinc15\t\t{ }\nsinc13: sinc14,r2\tis c0202=1 & sinc14 & r2\t{ * mult_addr = r2; mult_addr = mult_addr + 4; }\nsinc13: r2\t\t\tis c0202=1 & c0001=0 & r2\t{ * mult_addr = r2; mult_addr = mult_addr + 4; }\nsinc13: sinc14\t\tis c0202=0 & sinc14\t\t{ }\nsinc12: sinc13,r3\tis c0303=1 & sinc13 & r3\t{ * mult_addr = r3; mult_addr = mult_addr + 4; }\nsinc12: r3\t\t\tis c0303=1 & c0002=0 & r3\t{ * mult_addr = r3; mult_addr = mult_addr + 4; }\nsinc12: sinc13\t\tis c0303=0 & sinc13\t\t{ }\nsinc11: sinc12,r4\tis c0404=1 & sinc12 & r4\t{ * mult_addr = r4; mult_addr = mult_addr + 4; }\nsinc11: r4\t\t\tis c0404=1 & c0003=0 & r4\t{ * mult_addr = r4; mult_addr = mult_addr + 4; }\nsinc11: sinc12\t\tis c0404=0 & sinc12\t\t{ }\nsinc10: sinc11,r5\tis c0505=1 & sinc11 & r5\t{ * mult_addr = r5; mult_addr = mult_addr + 4; }\nsinc10: r5\t\t\tis c0505=1 & c0004=0 & r5\t{ * mult_addr = r5; mult_addr = mult_addr + 4; }\nsinc10: sinc11\t\tis c0505=0 & sinc11\t\t{ }\nsinc9: sinc10,r6\tis c0606=1 & sinc10 & r6\t{ * mult_addr = r6; mult_addr = mult_addr + 4; }\nsinc9: r6\t\t\tis c0606=1 & c0005=0 & r6\t{ * mult_addr = r6; mult_addr = mult_addr + 4; }\nsinc9: sinc10\t\tis c0606=0 & sinc10\t\t{ }\nsinc8: sinc9,r7\t\tis c0707=1 & sinc9 & r7\t\t{ * mult_addr = r7; mult_addr = mult_addr + 4; }\nsinc8: r7\t\t\tis c0707=1 & c0006=0 & r7\t{ * mult_addr = r7; mult_addr = mult_addr + 4; }\nsinc8: sinc9\t\tis c0707=0 & sinc9\t\t{ }\nsinc7: sinc8,r8\t\tis c0808=1 & sinc8 & r8\t\t{ * mult_addr = r8; mult_addr = mult_addr + 4; }\nsinc7: r8\t\t\tis c0808=1 & c0007=0 & r8\t{ * mult_addr = r8; mult_addr = mult_addr + 4; }\nsinc7: sinc8\t\tis c0808=0 & sinc8\t\t{ }\nsinc6: sinc7,r9\t\tis c0909=1 & sinc7 & r9\t\t{ * mult_addr = r9; mult_addr = mult_addr + 4; }\nsinc6: r9\t\t\tis c0909=1 & c0008=0 & r9\t{ * mult_addr = r9; mult_addr = mult_addr + 4; }\nsinc6: sinc7\t\tis c0909=0 & sinc7\t\t{ }\nsinc5: sinc6,r10\tis c1010=1 & sinc6 & r10\t{ * mult_addr = r10; mult_addr = mult_addr + 4; }\nsinc5: r10\t\t\tis c1010=1 & c0009=0 & r10\t{ * mult_addr = r10; mult_addr = mult_addr + 4; }\nsinc5: sinc6\t\tis c1010=0 & sinc6\t\t{ }\nsinc4: sinc5,r11\tis c1111=1 & sinc5 & r11\t{ * mult_addr = r11; mult_addr = mult_addr + 4; }\nsinc4: r11\t\t\tis c1111=1 & c0010=0 & r11\t{ * mult_addr = r11; mult_addr = mult_addr + 4; }\nsinc4: sinc5\t\tis c1111=0 & sinc5\t\t{ }\nsinc3: sinc4,r12\tis c1212=1 & sinc4 & r12\t{ * mult_addr = r12; mult_addr = mult_addr + 4; }\nsinc3: r12\t\t\tis c1212=1 & c0011=0 & r12\t{ * mult_addr = r12; mult_addr = mult_addr + 4; }\nsinc3: sinc4\t\tis c1212=0 & sinc4\t\t{ }\nsinc2: sinc3,sp\t\tis c1313=1 & sinc3 & sp\t\t{ * mult_addr = sp; mult_addr = mult_addr + 4; }\nsinc2: sp\t\t\tis c1313=1 & c0012=0 & sp\t{ * mult_addr = sp; mult_addr = mult_addr + 4; }\nsinc2: sinc3\t\tis c1313=0 & sinc3\t\t{ }\nsinc1: sinc2,lr\t\tis c1414=1 & sinc2 & lr\t\t{ * mult_addr = lr; mult_addr = mult_addr + 4; }\nsinc1: lr\t\t\tis c1414=1 & c0013=0 & lr\t{ * mult_addr = lr; mult_addr = mult_addr + 4; }\nsinc1: sinc2\t\tis c1414=0 & sinc2\t\t{ }\nsinc0: sinc1,pc\t\tis c1515=1 & sinc1 & pc\t\t{ *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; }\nsinc0: pc\t\t\tis c1515=1 & c0014=0 & pc\t{ *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; }\nsinc0: sinc1\t\tis c1515=0 & sinc1\t\t{ }\nstlist_inc: {sinc0}\tis sinc0\t{ }\n\n\n# ldlist_dec is the list of registers to be loaded using DA or DB in Addressing Mode 4\nldec15: pc\t\t\tis c1515=1 & pc\t\t\t{ pc = * mult_addr; mult_addr = mult_addr - 4; }\nldec15:\t\t\t\tis c1515=0\t\t\t\t{ }\nldec14: lr,ldec15\tis c1414=1 & ldec15 & lr\t{ lr = * mult_addr; mult_addr = mult_addr - 4; }\nldec14: lr\t\t\tis c1414=1 & c1515=0 & lr\t{ lr = * mult_addr; mult_addr = mult_addr - 4; }\nldec14: ldec15\t\tis c1414=0 & ldec15\t\t{ }\nldec13: sp,ldec14\tis c1313=1 & ldec14 & sp\t{ sp = * mult_addr; mult_addr = mult_addr - 4; }\nldec13: sp\t\t\tis c1313=1 & c1415=0 & sp\t{ sp = * mult_addr; mult_addr = mult_addr - 4; }\nldec13: ldec14\t\tis c1313=0 & ldec14\t\t{ }\nldec12: r12,ldec13\tis c1212=1 & ldec13 & r12\t{ r12 = * mult_addr; mult_addr = mult_addr - 4; }\nldec12: r12\t\t\tis c1212=1 & c1315=0 & r12\t{ r12 = * mult_addr; mult_addr = mult_addr - 4; }\nldec12: ldec13\t\tis c1212=0 & ldec13\t\t{ }\nldec11: r11,ldec12\tis c1111=1 & ldec12 & r11\t{ r11 = * mult_addr; mult_addr = mult_addr - 4; }\nldec11: r11\t\t\tis c1111=1 & c1215=0 & r11\t{ r11 = * mult_addr; mult_addr = mult_addr - 4; }\nldec11: ldec12\t\tis c1111=0 & ldec12\t\t{ }\nldec10: r10,ldec11\tis c1010=1 & ldec11 & r10\t{ r10 = * mult_addr; mult_addr = mult_addr - 4; }\nldec10: r10\t\t\tis c1010=1 & c1115=0 & r10\t{ r10 = * mult_addr; mult_addr = mult_addr - 4; }\nldec10: ldec11\t\tis c1010=0 & ldec11\t\t{ }\nldec9: r9,ldec10\tis c0909=1 & ldec10 & r9\t{ r9 = * mult_addr; mult_addr = mult_addr - 4; }\nldec9: r9\t\t\tis c0909=1 & c1015=0 & r9\t{ r9 = * mult_addr; mult_addr = mult_addr - 4; }\nldec9: ldec10\t\tis c0909=0 & ldec10\t\t{ }\nldec8: r8,ldec9\t\tis c0808=1 & ldec9 & r8\t\t{ r8 = * mult_addr; mult_addr = mult_addr - 4; }\nldec8: r8\t\t\tis c0808=1 & c0915=0 & r8\t{ r8 = * mult_addr; mult_addr = mult_addr - 4; }\nldec8: ldec9\t\tis c0808=0 & ldec9\t\t{ }\nldec7: r7,ldec8\t\tis c0707=1 & ldec8 & r7\t\t{ r7 = * mult_addr; mult_addr = mult_addr - 4; }\nldec7: r7\t\t\tis c0707=1 & c0815=0 & r7\t{ r7 = * mult_addr; mult_addr = mult_addr - 4; }\nldec7: ldec8\t\tis c0707=0 & ldec8\t\t{ }\nldec6: r6,ldec7\t\tis c0606=1 & ldec7 & r6\t\t{ r6 = * mult_addr; mult_addr = mult_addr - 4; }\nldec6: r6\t\t\tis c0606=1 & c0715=0 & r6\t{ r6 = * mult_addr; mult_addr = mult_addr - 4; }\nldec6: ldec7\t\tis c0606=0 & ldec7\t\t{ }\nldec5: r5,ldec6\t\tis c0505=1 & ldec6 & r5\t\t{ r5 = * mult_addr; mult_addr = mult_addr - 4; }\nldec5: r5\t\t\tis c0505=1 & c0615=0 & r5\t{ r5 = * mult_addr; mult_addr = mult_addr - 4; }\nldec5: ldec6\t\tis c0505=0 & ldec6\t\t{ }\nldec4: r4,ldec5\t\tis c0404=1 & ldec5 & r4\t\t{ r4 = * mult_addr; mult_addr = mult_addr - 4; }\nldec4: r4\t\t\tis c0404=1 & c0515=0 & r4\t{ r4 = * mult_addr; mult_addr = mult_addr - 4; }\nldec4: ldec5\t\tis c0404=0 & ldec5\t\t{ }\nldec3: r3,ldec4\t\tis c0303=1 & ldec4 & r3\t\t{ r3 = * mult_addr; mult_addr = mult_addr - 4; }\nldec3: r3\t\t\tis c0303=1 & c0415=0 & r3\t{ r3 = * mult_addr; mult_addr = mult_addr - 4; }\nldec3: ldec4\t\tis c0303=0 & ldec4\t\t{ }\nldec2: r2,ldec3\t\tis c0202=1 & ldec3 & r2\t\t{ r2 = * mult_addr; mult_addr = mult_addr - 4; }\nldec2: r2\t\t\tis c0202=1 & c0315=0 & r2\t{ r2 = * mult_addr; mult_addr = mult_addr - 4; }\nldec2: ldec3\t\tis c0202=0 & ldec3\t\t{ }\nldec1: r1,ldec2\t\tis c0101=1 & ldec2 & r1\t\t{ r1 = * mult_addr; mult_addr = mult_addr - 4; }\nldec1: r1\t\t\tis c0101=1 & c0215=0 & r1\t{ r1 = * mult_addr; mult_addr = mult_addr - 4; }\nldec1: ldec2\t\tis c0101=0 & ldec2\t\t{ }\nldec0: r0,ldec1\t\tis c0000=1 & ldec1 & r0\t\t{ r0 = * mult_addr; mult_addr = mult_addr - 4; }\nldec0: r0\t\t\tis c0000=1 & c0115=0 & r0\t{ r0 = * mult_addr; mult_addr = mult_addr - 4; }\nldec0: ldec1\t\tis c0000=0 & ldec1\t\t{ }\nldlist_dec: {ldec0}\tis ldec0\t{ }\n\n# stlist_dec is the list of registers to be stored using DA or DB in Addressing Mode 4\nsdec15: pc\t\t\tis c1515=1 & pc\t\t\t\t{ *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr - 4; }\nsdec15:\t\t\t\tis c1515=0\t\t\t\t{ }\nsdec14: lr,sdec15\tis c1414=1 & sdec15 & lr\t{ * mult_addr=lr; mult_addr = mult_addr - 4; }\nsdec14: lr\t\t\tis c1414=1 & c1515=0 & lr\t{ * mult_addr=lr; mult_addr = mult_addr - 4; }\nsdec14: sdec15\t\tis c1414=0 & sdec15\t\t{ }\nsdec13: sp,sdec14\tis c1313=1 & sdec14 & sp\t{ * mult_addr=sp; mult_addr = mult_addr - 4; }\nsdec13: sp\t\t\tis c1313=1 & c1415=0 & sp\t{ * mult_addr=sp; mult_addr = mult_addr - 4; }\nsdec13: sdec14\t\tis c1313=0 & sdec14\t\t{ }\nsdec12: r12,sdec13 is c1212=1 & sdec13 & r12\t{ * mult_addr=r12; mult_addr = mult_addr - 4; }\nsdec12: r12\t\t\tis c1212=1 & c1315=0 & r12\t{ * mult_addr=r12; mult_addr = mult_addr - 4; }\nsdec12: sdec13\t\tis c1212=0 & sdec13\t\t{ }\nsdec11: r11,sdec12\tis c1111=1 & sdec12 & r11\t{ * mult_addr=r11; mult_addr = mult_addr - 4; }\nsdec11: r11\t\t\tis c1111=1 & c1215=0 & r11\t{ * mult_addr=r11; mult_addr = mult_addr - 4; }\nsdec11: sdec12\t\tis c1111=0 & sdec12\t\t{ }\nsdec10: r10,sdec11\tis c1010=1 & sdec11 & r10\t{ * mult_addr=r10; mult_addr = mult_addr - 4; }\nsdec10: r10\t\t\tis c1010=1 & c1115=0 & r10\t{ * mult_addr=r10; mult_addr = mult_addr - 4; }\nsdec10: sdec11\t\tis c1010=0 & sdec11\t\t{ }\nsdec9: r9,sdec10\tis c0909=1 & sdec10 & r9\t{ * mult_addr=r9; mult_addr = mult_addr - 4; }\nsdec9: r9\t\t\tis c0909=1 & c1015=0 & r9\t{ * mult_addr=r9; mult_addr = mult_addr - 4; }\nsdec9: sdec10\t\tis c0909=0 & sdec10\t\t{ }\nsdec8: r8,sdec9\t\tis c0808=1 & sdec9 & r8\t\t{ * mult_addr=r8; mult_addr = mult_addr - 4; }\nsdec8: r8\t\t\tis c0808=1 & c0915=0 & r8\t{ * mult_addr=r8; mult_addr = mult_addr - 4; }\nsdec8: sdec9\t\tis c0808=0 & sdec9\t\t{ }\nsdec7: r7,sdec8\t\tis c0707=1 & sdec8 & r7\t\t{ * mult_addr=r7; mult_addr = mult_addr - 4; }\nsdec7: r7\t\t\tis c0707=1 & c0815=0 & r7\t{ * mult_addr=r7; mult_addr = mult_addr - 4; }\nsdec7: sdec8\t\tis c0707=0 & sdec8\t\t{ }\nsdec6: r6,sdec7\t\tis c0606=1 & sdec7 & r6\t\t{ * mult_addr=r6; mult_addr = mult_addr - 4; }\nsdec6: r6\t\t\tis c0606=1 & c0715=0 & r6\t{ * mult_addr=r6; mult_addr = mult_addr - 4; }\nsdec6: sdec7\t\tis c0606=0 & sdec7\t\t{ }\nsdec5: r5,sdec6\t\tis c0505=1 & sdec6 & r5\t\t{ * mult_addr=r5; mult_addr = mult_addr - 4; }\nsdec5: r5\t\t\tis c0505=1 & c0615=0 & r5\t{ * mult_addr=r5; mult_addr = mult_addr - 4; }\nsdec5: sdec6\t\tis c0505=0 & sdec6\t\t{ }\nsdec4: r4,sdec5\t\tis c0404=1 & sdec5 & r4\t\t{ * mult_addr=r4; mult_addr = mult_addr - 4; }\nsdec4: r4\t\t\tis c0404=1 & c0515=0 & r4\t{ * mult_addr=r4; mult_addr = mult_addr - 4; }\nsdec4: sdec5\t\tis c0404=0 & sdec5\t\t{ }\nsdec3: r3,sdec4\t\tis c0303=1 & sdec4 & r3\t\t{ * mult_addr=r3; mult_addr = mult_addr - 4; }\nsdec3: r3\t\t\tis c0303=1 & c0415=0 & r3\t{ * mult_addr=r3; mult_addr = mult_addr - 4; }\nsdec3: sdec4\t\tis c0303=0 & sdec4\t\t{ }\nsdec2: r2,sdec3\t\tis c0202=1 & sdec3 & r2\t\t{ * mult_addr=r2; mult_addr = mult_addr - 4; }\nsdec2: r2\t\t\tis c0202=1 & c0315=0 & r2\t{ * mult_addr=r2; mult_addr = mult_addr - 4; }\nsdec2: sdec3\t\tis c0202=0 & sdec3\t\t{ }\nsdec1: r1,sdec2\t\tis c0101=1 & sdec2 & r1\t\t{ * mult_addr=r1; mult_addr = mult_addr - 4; }\nsdec1: r1\t\t\tis c0101=1 & c0215=0 & r1\t{ * mult_addr=r1; mult_addr = mult_addr - 4; }\nsdec1: sdec2\t\tis c0101=0 & sdec2\t\t{ }\nsdec0: r0,sdec1\t\tis c0000=1 & sdec1 & r0\t\t{ * mult_addr=r0; mult_addr = mult_addr - 4; }\nsdec0: r0\t\t\tis c0000=1 & c0115=0 & r0\t{ * mult_addr=r0; mult_addr = mult_addr - 4; }\nsdec0: sdec1\t\tis c0000=0 & sdec1\t\t{ }\n\nstlist_dec: {sdec0}\tis sdec0\t{ }\n\n# reglist deals with Addressing Mode 4\n# it takes care of bits 0-27\n# we assume that alignment checking is turned on\nreglist: rn,ldlist_inc\t\tis P24=0 & U23=1 & S22=0 & W21=0 & L20=1 & rn & ldlist_inc\n{\n mult_addr=rn; build ldlist_inc;\n}\n\nreglist: rn,ldlist_inc\"^\"\tis P24=0 & U23=1 & S22=1 & W21=0 & L20=1 & rn & ldlist_inc\n{\n mult_addr=rn; build ldlist_inc;\n}\n\nreglist: rn!,ldlist_inc\t\tis P24=0 & U23=1 & S22=0 & W21=1 & L20=1 & rn & ldlist_inc\n{\n mult_addr=rn; build ldlist_inc; rn=mult_addr;\n}\n\nreglist: rn!,ldlist_inc\"^\"\tis P24=0 & U23=1 & S22=1 & W21=1 & L20=1 & rn & ldlist_inc\n{\n mult_addr=rn; build ldlist_inc; rn=mult_addr;\n}\n\nreglist: rn,ldlist_inc\t\tis P24=1 & U23=1 & S22=0 & W21=0 & L20=1 & rn & ldlist_inc\n{\n mult_addr=(rn+4); build ldlist_inc;\n}\n\nreglist: rn,ldlist_inc\"^\"\tis P24=1 & U23=1 & S22=1 & W21=0 & L20=1 & rn & ldlist_inc\n{\n mult_addr=(rn+4); build ldlist_inc;\n}\n\nreglist: rn!,ldlist_inc\t\tis P24=1 & U23=1 & S22=0 & W21=1 & L20=1 & rn & ldlist_inc\n{\n mult_addr=(rn+4); build ldlist_inc; rn=mult_addr-4;\n}\n\nreglist: rn!,ldlist_inc\"^\"\tis P24=1 & U23=1 & S22=1 & W21=1 & L20=1 & rn & ldlist_inc\n{\n mult_addr=(rn+4); build ldlist_inc; rn=mult_addr-4;\n}\n\nreglist: rn,ldlist_dec\t\tis P24=0 & U23=0 & S22=0 & W21=0 & L20=1 & rn & ldlist_dec\n{\n mult_addr=rn; build ldlist_dec;\n}\n\nreglist: rn,ldlist_dec\"^\"\tis P24=0 & U23=0 & S22=1 & W21=0 & L20=1 & rn & ldlist_dec\n{\n mult_addr=rn; build ldlist_dec;\n}\n\nreglist: rn!,ldlist_dec\t\tis P24=0 & U23=0 & S22=0 & W21=1 & L20=1 & rn & ldlist_dec\n{\n mult_addr=rn; build ldlist_dec; rn=mult_addr;\n}\n\nreglist: rn!,ldlist_dec\"^\"\tis P24=0 & U23=0 & S22=1 & W21=1 & L20=1 & rn & ldlist_dec\n{\n mult_addr=rn; build ldlist_dec; rn=mult_addr;\n}\n\nreglist: rn,ldlist_dec\t\tis P24=1 & U23=0 & S22=0 & W21=0 & L20=1 & rn & ldlist_dec\n{\n mult_addr=(rn-4); build ldlist_dec;\n}\n\nreglist: rn,ldlist_dec\"^\"\tis P24=1 & U23=0 & S22=1 & W21=0 & L20=1 & rn & ldlist_dec\n{\n mult_addr=(rn-4); build ldlist_dec;\n}\n\nreglist: rn!,ldlist_dec\t\tis P24=1 & U23=0 & S22=0 & W21=1 & L20=1 & rn & ldlist_dec\n{\n mult_addr=(rn-4); build ldlist_dec; rn=mult_addr+4;\n}\n\nreglist: rn!,ldlist_dec\"^\"\tis P24=1 & U23=0 & S22=1 & W21=1 & L20=1 & rn & ldlist_dec\n{\n mult_addr=(rn-4); build ldlist_dec; rn=mult_addr+4;\n}\n\nreglist: rn,stlist_inc\t\tis P24=0 & U23=1 & S22=0 & W21=0 & L20=0 & rn & stlist_inc\n{\n mult_addr=rn; build stlist_inc;\n}\n\nreglist: rn,stlist_inc\"^\"\tis P24=0 & U23=1 & S22=1 & W21=0 & L20=0 & rn & stlist_inc\n{\n mult_addr=rn; build stlist_inc;\n}\n\n## This is here to allow old versions of this instruction to decode.\n## The W-Bit21 is specified as (0) in the manual meaning should be 0 but is unpredictable if 1\n## Some older processors did not specify that Writeback was not available if the P24=0 and S22=0,\n## which is a system interrupt instruction.\n## I AM ASSUMING, that the W-bit is honored on these processors and does update the register!!!!\n## This is probably an arbitrary decision, but keeps with what old processor did.\nreglist: rn,stlist_inc\"^\"\tis P24=0 & U23=1 & S22=1 & W21=1 & L20=0 & rn & stlist_inc\n{\n mult_addr=rn; build stlist_inc; rn=mult_addr;\n}\n\n\nreglist: rn!,stlist_inc\t\tis P24=0 & U23=1 & S22=0 & W21=1 & L20=0 & rn & stlist_inc\n{\n mult_addr=rn; build stlist_inc; rn=mult_addr;\n}\n\nreglist: rn,stlist_inc\t\tis P24=1 & U23=1 & S22=0 & W21=0 & L20=0 & rn & stlist_inc\n{\n mult_addr=(rn+4); build stlist_inc;\n}\n\nreglist: rn,stlist_inc\"^\"\tis P24=1 & U23=1 & S22=1 & W21=0 & L20=0 & rn & stlist_inc\n{\n mult_addr=(rn+4); build stlist_inc;\n}\n\nreglist: rn!,stlist_inc\t\tis P24=1 & U23=1 & S22=0 & W21=1 & L20=0 & rn & stlist_inc\n{\n mult_addr=(rn+4); build stlist_inc; rn=mult_addr-4;\n}\n\nreglist: rn,stlist_dec\t\tis P24=0 & U23=0 & S22=0 & W21=0 & L20=0 & rn & stlist_dec\n{\n mult_addr=rn; build stlist_dec;\n}\n\nreglist: rn,stlist_dec\"^\"\tis P24=0 & U23=0 & S22=1 & W21=0 & L20=0 & rn & stlist_dec\n{\n mult_addr=rn; build stlist_dec;\n}\n\nreglist: rn!,stlist_dec\t\tis P24=0 & U23=0 & S22=0 & W21=1 & L20=0 & rn & stlist_dec\n{\n mult_addr=rn; build stlist_dec; rn=mult_addr;\n}\n\nreglist: rn,stlist_dec\t\tis P24=1 & U23=0 & S22=0 & W21=0 & L20=0 & rn & stlist_dec\n{\n mult_addr=(rn-4); build stlist_dec;\n}\n\nreglist: rn,stlist_dec\"^\"\tis P24=1 & U23=0 & S22=1 & W21=0 & L20=0 & rn & stlist_dec\n{\n mult_addr=(rn-4); build stlist_dec;\n}\n\nreglist: rn!,stlist_dec\t\tis P24=1 & U23=0 & S22=0 & W21=1 & L20=0 & rn & stlist_dec\n{\n mult_addr=(rn-4); build stlist_dec; rn=mult_addr+4;\n}\n\n# mdir is for attaching the load/store multiple addressing mode mnemonic to the mnemonic\nmdir: \"ia\"\tis P24=0 & U23=1\t{ }\nmdir: \"ib\"\tis P24=1 & U23=1\t{ }\nmdir: \"da\"\tis P24=0 & U23=0\t{ }\nmdir: \"db\"\tis P24=1 & U23=0\t{ }\n\n# addrmode5 is the parameter in Addressing Mode5\n# it takes care of bits 27-0 except for the N and L flags and CRd and cp#\n# it takes care of possible writebacks to Rn\naddrmode5: [rn,\"#\"^off8]\tis P24=1 & U23=1 & W21=0 & rn & immed\t\t[ off8=immed*4; ] { local tmp = rn + off8; export tmp; }\naddrmode5: [rn,\"#\"^noff8]\tis P24=1 & U23=0 & W21=0 & rn & immed\t\t[ noff8=-(immed*4); ] { local tmp = rn + noff8; export tmp; }\naddrmode5: [rn,\"#\"^off8]!\tis P24=1 & U23=1 & W21=1 & rn & immed\t\t[ off8=immed*4; ] { rn = rn + off8; export rn; }\naddrmode5: [rn,\"#\"^noff8]!\tis P24=1 & U23=0 & W21=1 & rn & immed\t\t[ noff8=-(immed*4); ] { rn = rn + noff8; export rn; }\naddrmode5: [rn],\"#\"^off8\tis P24=0 & U23=1 & W21=1 & rn & immed\t\t[ off8=immed*4; ] { local tmp = rn; rn = rn+off8; export tmp; }\naddrmode5: [rn],\"#\"^noff8\tis P24=0 & U23=0 & W21=1 & rn & immed\t\t[ noff8=-(immed*4); ] { local tmp = rn; rn = rn + noff8; export tmp; }\naddrmode5: [rn],{immed}\tis P24=0 & U23=1 & W21=0 & rn & immed\t\t\t\t { export rn; }\n\n# cpsrmask is the resulting cpsr mask for the msr instruction\n\ncpsrmask:\t\t\t\tis mask=0\t{ export 0:4; }\ncpsrmask: \"cpsr_c\"\t\tis mask=1\t{ export 0xff:4; }\ncpsrmask: \"cpsr_x\"\t\tis mask=2\t{ export 0xff00:4; }\ncpsrmask: \"cpsr_cx\"\t\tis mask=3\t{ export 0xffff:4; }\ncpsrmask: \"cpsr_s\"\t\tis mask=4\t{ export 0xff0000:4; }\ncpsrmask: \"cpsr_cs\"\t\tis mask=5\t{ export 0xff00ff:4; }\ncpsrmask: \"cpsr_xs\"\t\tis mask=6\t{ export 0xffff00:4; }\ncpsrmask: \"cpsr_cxs\"\tis mask=7\t{ export 0xffffff:4; }\ncpsrmask: \"cpsr_f\"\t\tis mask=8\t{ export 0xff000000:4; }\ncpsrmask: \"cpsr_cf\"\t\tis mask=9\t{ export 0xff0000ff:4; }\ncpsrmask: \"cpsr_xf\"\t\tis mask=10\t{ export 0xff00ff00:4; }\ncpsrmask: \"cpsr_cxf\"\tis mask=11\t{ export 0xff00ffff:4; }\ncpsrmask: \"cpsr_sf\"\t\tis mask=12\t{ export 0xffff0000:4; }\ncpsrmask: \"cpsr_csf\"\tis mask=13\t{ export 0xffff00ff:4; }\ncpsrmask: \"cpsr_xsf\"\tis mask=14\t{ export 0xffffff00:4; }\ncpsrmask: \"cpsr_cxsf\"\tis mask=15\t{ export 0xffffffff:4; }\n\n# spsrmask is the mask for spsr in the msr instruction\n\nspsrmask:\t\t\tis mask=0\t{ export 0:4; }\nspsrmask: \"spsr_c\"\tis mask=1\t{ export 0xff:4; }\nspsrmask: \"spsr_x\"\tis mask=2\t{ export 0xff00:4; }\nspsrmask: \"spsr_cx\"\tis mask=3\t{ export 0xffff:4; }\nspsrmask: \"spsr_s\"\tis mask=4\t{ export 0xff0000:4; }\nspsrmask: \"spsr_cs\"\tis mask=5\t{ export 0xff00ff:4; }\nspsrmask: \"spsr_xs\"\tis mask=6\t{ export 0xffff00:4; }\nspsrmask: \"spsr_cxs\"\tis mask=7\t{ export 0xffffff:4; }\nspsrmask: \"spsr_f\"\tis mask=8\t{ export 0xff000000:4; }\nspsrmask: \"spsr_cf\"\tis mask=9\t{ export 0xff0000ff:4; }\nspsrmask: \"spsr_xf\"\tis mask=10\t{ export 0xff00ff00:4; }\nspsrmask: \"spsr_cxf\"\tis mask=11\t{ export 0xff00ffff:4; }\nspsrmask: \"spsr_sf\"\tis mask=12\t{ export 0xffff0000:4; }\nspsrmask: \"spsr_csf\"\tis mask=13\t{ export 0xffff00ff:4; }\nspsrmask: \"spsr_xsf\"\tis mask=14\t{ export 0xffffff00:4; }\nspsrmask: \"spsr_cxsf\"\tis mask=15\t{ export 0xffffffff:4; }\n\n#####################\n###### immediate bit-number data for unsigned/signed saturated instructions \n#####################\n@if defined(VERSION_6)\n\nsSatImm5: \"#\"^satimm is satimm5 [ satimm = satimm5 + 1; ] { export *[const]:2 satimm; }\nsSatImm4: \"#\"^satimm is satimm4 [ satimm = satimm4 + 1; ] { export *[const]:2 satimm; }\nuSatImm5: \"#\"^satimm5 is satimm5 { export *[const]:2 satimm5; }\nuSatImm4: \"#\"^satimm4 is satimm4 { export *[const]:2 satimm4; }\n\n@endif # VERSION_6\n\n@if defined(VERSION_6K) || defined(VERSION_6T2)\noptionImm: \"#\"^immed4\tis immed4\t{ export *[const]:4 immed4; }\n@endif\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\nlsbImm: \"#\"^lsb\tis lsb\t{ export *[const]:4 lsb; }\nmsbImm: \"#\"^msb\tis msb\t{ export *[const]:4 msb; }\nwidthMinus1: \"#\"^width\tis msb [ width = msb + 1; ] { export *[const]:4 msb; }\nbitWidth: \"#\"^w\tis lsb & msb\t[ w = msb - lsb + 1; ] { export *[const]:4 w; }\n\n@endif # VERSION_6T2 || VERSION_7\n\n#\n# Modes for SRS instructions\n#\n@if defined(VERSION_6)\nSRSMode: \"usr\" is srsMode=8 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"fiq\" is srsMode=9 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"irq\" is srsMode=10 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"svc\" is srsMode=11 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"mon\" is srsMode=14 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"abt\" is srsMode=15 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"und\" is srsMode=19 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"sys\" is srsMode=23 & c0004 { export *[const]:1 c0004; }\nSRSMode: \"#\"^srsMode is srsMode { export *[const]:1 srsMode; }\n@endif # VERSION_6\n\n# Perform ARMcond check phase and set ARMcond context variable\n:^instruction is $(AMODE) & ARMcondCk=0 & (bit31=0|bit30=0|bit29=0|bit28=0) & instruction [ ARMcondCk=1; ARMcond=1; ] {}\n:^instruction is ARMcondCk=0 & instruction [ ARMcondCk=1; ARMcond=0; ] {}\n\n# Ensure that the condition check phase has been completed\nwith : ARMcondCk=1 {\n\n#################################################\n#\n# Include the SIMD/VFP instructions before the\n# other ARM instructions to avoid incorrect\n# constructor matching for those that use the\n# COND subconstructor. This also ensures\n# that the various VFP instructions supersede the \n# CDP/MCR/MRC general coprocessor instructions\n#\n#################################################\n@if defined(INCLUDE_NEON)\n@include \"ARMneon.sinc\"\n@endif\n\n#################################################\n#\n# Do the same now for ARMv8, which also has neon\n#\n#################################################\n@if defined(VERSION_8)\n@include \"ARMv8.sinc\"\n@endif # VERSION_8\n\n################################################\n#\n# These instructions must come first because the cond pattern match\n# is more specific than the subconstructor COND. If a base intruction\n# matches and then COND fails (cond=14 or cond=15) then the disassembly\n# will fail\n#\n################################################\n\n@if defined(VERSION_5)\n\n# Exception Generation and UDF\n\n# immed12_4 used in Exception Generation and Media instructions class\n\nimmed12_4: \"#\"^tmp is $(AMODE) & immed12 & immed4 [tmp = (immed12 << 4) | immed4; ] { export *[const]:4 tmp; }\n\n:hlt immed12_4\t\t\tis $(AMODE) & cond=0xe & c2027=0x10 & c0407=0x7 & immed12_4\n{\n\tsoftware_hlt(immed12_4);\n}\n\n:bkpt immed12_4\t\t\tis $(AMODE) & cond=0xe & c2027=0x12 & c0407=0x7 & immed12_4\n{\n\tsoftware_bkpt(immed12_4);\n}\n\n:hvc immed12_4\t\t\tis $(AMODE) & cond=0xe & c2027=0x14 & c0407=0x7 & immed12_4\n{\n\tsoftware_hvc(immed12_4);\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\n\ndefine pcodeop SG;\n\n:sg is TMode=1 & thv_c0031=0xe97fe97f\n{\n\tSG();\n}\n@endif\n\n# Requires Security Extensions\n:smc^COND immed4\t\tis $(AMODE) & COND & c2027=0x16 & c0407=0x7 & immed4\n{\n\tbuild COND;\n\tsoftware_smc(immed4:4);\n}\n\n@if defined(VERSION_6T2) || defined(VERSION_7)\ndefine pcodeop TT;\n\n:tt^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=0 & thv_bit06=0 & thv_Rt2 & thv_Rn\n{\n\tthv_Rt2 = TT(thv_Rn);\n}\n\ndefine pcodeop TTA;\n\n:tta^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=1 & thv_bit06=0 & thv_Rt2 & thv_Rn\n{\n\tthv_Rt2 = TTA(thv_Rn);\n}\n\ndefine pcodeop TTAT;\n\n:ttat^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=1 & thv_bit06=1 & thv_Rt2 & thv_Rn\n{\n\tthv_Rt2 = TTAT(thv_Rn);\n}\n\ndefine pcodeop TTT;\n\n:ttt^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=0 & thv_bit06=1 & thv_Rt2 & thv_Rn\n{\n\tthv_Rt2 = TTT(thv_Rn);\n}\n\n@endif\n\n:udf immed12_4\t\t\tis $(AMODE) & cond=0xe & c2027=0x7f & c0407=0xf & immed12_4\n{\n\tlocal excaddr:4 = inst_start;\n\tlocal target:4 = software_udf(immed12_4:4, excaddr);\n\tgoto [target];\n}\n\n@endif # VERSION_5\n\n@if defined(VERSION_6)\n\nAFLAG: \"a\" is c0808=1 & c1819=2 \t{ enableDataAbortInterrupts(); }\nAFLAG: \"a\" is c0808=1 \t\t\t\t{ disableDataAbortInterrupts(); }\nAFLAG: is c0808=0 \t\t\t\t{ }\nIFLAG: \"i\" is c0707=1 & c1819=2 \t{ enableIRQinterrupts(); }\nIFLAG: \"i\" is c0707=1 \t\t\t\t{ disableIRQinterrupts(); }\nIFLAG: is c0707=0 \t\t\t\t{ }\nFFLAG: \"f\" is c0606=1 & c1819=2 \t{ enableFIQinterrupts(); }\nFFLAG: \"f\" is c0606=1 \t\t\t\t{ disableFIQinterrupts(); }\nFFLAG: is c0606=0 \t\t\t\t{ }\nIFLAGS: AFLAG^IFLAG^FFLAG is AFLAG & IFLAG & FFLAG { }\n\nSetMode: \"#\"^16 is c0004=0x10 { setUserMode(); } \nSetMode: \"#\"^17 is c0004=0x11 { setFIQMode(); } \nSetMode: \"#\"^18 is c0004=0x12 { setIRQMode(); } \nSetMode: \"#\"^19 is c0004=0x13 { setSupervisorMode(); } \nSetMode: \"#\"^22 is c0004=0x16 { setMonitorMode(); }\nSetMode: \"#\"^23 is c0004=0x17 { setAbortMode(); } \nSetMode: \"#\"^27 is c0004=0x1b { setUndefinedMode(); } \nSetMode: \"#\"^31 is c0004=0x1f { setSystemMode(); } \n\n:cps SetMode \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=0 & c1717=1 & c0916=0 & c0508=0 & SetMode { }\n:cpsie IFLAGS \tis $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=2 & c1717=0 & c0916=0 & c0505=0 & c0004=0 & IFLAGS { }\n:cpsid IFLAGS \tis $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=3 & c1717=0 & c0916=0 & c0505=0 & c0004=0 & IFLAGS { }\n:cpsie IFLAGS, SetMode is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=2 & c1717=1 & c0916=0 & c0505=0 & IFLAGS & SetMode { }\n:cpsid IFLAGS, SetMode is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=3 & c1717=1 & c0916=0 & c0505=0 & IFLAGS & SetMode { }\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:pld addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=1 & c2022=5 & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n\tHintPreloadData(addrmode2);\n}\n\n# prevent literal form getting matched by pldw\n:pld addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=1 & c2022=5 & c1619=0xf & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n\tHintPreloadData(addrmode2);\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_7)\n\n:pldw addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=1 & c2022=1 & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n\tHintPreloadDataForWrite(addrmode2);\n}\n\n:pli addrmode2\t\t\tis $(AMODE) & cond=0xf & c2627=1 & c2424=0 & c2022=5 & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n\tHintPreloadInstruction(addrmode2);\n}\n\n@endif # VERSION_7\n\n\n@if defined(VERSION_6)\n\n:rfeia rn \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = rn;\n cpsr = *ptr;\n ptr = ptr + 4;\n pc = *ptr;\n return [pc];\n}\n\n:rfeib rn \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = rn + 4;\n cpsr = *ptr;\n ptr = ptr + 4;\n pc = *ptr;\n return [pc];\n}\n\n:rfeda rn \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = rn;\n cpsr = *ptr;\n ptr = ptr - 4;\n pc = *ptr;\n return [pc];\n}\n\n:rfedb rn \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = rn - 4;\n cpsr = *ptr;\n ptr = ptr - 4;\n pc = *ptr;\n return [pc];\n}\n\n:rfeia Rn! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = Rn;\n cpsr = *ptr;\n ptr = ptr + 4;\n pc = *ptr;\n Rn = ptr + 4;\n return [pc];\n}\n\n:rfeib Rn! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = Rn + 4;\n cpsr = *ptr;\n ptr = ptr + 4;\n pc = *ptr;\n Rn = ptr;\n return [pc];\n}\n\n:rfeda Rn! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = Rn;\n cpsr = *ptr;\n ptr = ptr - 4;\n pc = *ptr;\n Rn = ptr - 4;\n return [pc];\n}\n\n:rfedb Rn! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0\n{\n # register list is always: pc, cpsr\n ptr:4 = Rn - 4;\n cpsr = *ptr;\n ptr = ptr - 4;\n pc = *ptr;\n Rn = ptr;\n return [pc];\n}\n\n:srsia SRSMode \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=1 & W21=0 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp;\n *ptr = lr;\n ptr = ptr + 4;\n *ptr = spsr;\n ptr = ptr + 4;\n}\n\n:srsib SRSMode \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & W21=0 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp + 4;\n *ptr = lr;\n ptr = ptr + 4;\n *ptr = spsr;\n}\n\n:srsda SRSMode \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & W21=0 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp;\n *ptr = lr;\n ptr = ptr - 4;\n *ptr = spsr;\n ptr = ptr - 4;\n}\n\n:srsdb SRSMode \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & W21=0 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp - 4;\n *ptr = lr;\n ptr = ptr - 4;\n *ptr = spsr;\n}\n\n:srsia SRSMode! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=1 & W21=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp;\n *ptr = lr;\n ptr = ptr + 4;\n *ptr = spsr;\n ptr = ptr + 4;\n sp = ptr;\n}\n\n:srsib SRSMode! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & W21=1 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp + 4;\n *ptr = lr;\n ptr = ptr + 4;\n *ptr = spsr;\n sp = ptr;\n}\n\n:srsda SRSMode! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & W21=1 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp;\n *ptr = lr;\n ptr = ptr - 4;\n *ptr = spsr;\n ptr = ptr - 4;\n sp = ptr;\n}\n\n:srsdb SRSMode! \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & W21=1 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode\n{\n # register list is always: r14, spsr\n ptr:4 = sp;\n ptr = ptr - 4;\n *ptr = lr;\n ptr = ptr - 4;\n *ptr = spsr;\n sp = ptr;\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5)\n\n:stc2 cpn,CRd,addrmode5 \tis $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=0\n{\n t_cpn:4 = cpn;\n coprocessor_store2(t_cpn,CRd,addrmode5);\n}\n\n:stc2l cpn,CRd,addrmode5 \tis $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=0\n{\n t_cpn:4 = cpn;\n coprocessor_storelong2(t_cpn,CRd,addrmode5);\n}\n\n@endif # VERSION_5\n\n#################################################\n#\n# Here are the rest of instructions in alphabetical order\n#\n#################################################\n\n#See ARM Architecture reference section \"Pseudocode details of addition and subtraction\"\nmacro add_with_carry_flags(op1,op2){\n local CYz = zext(CY);\n local result = op1 + op2;\n tmpCY = carry( op1, op2) || carry( result, CYz );\n tmpOV = scarry( op1, op2 ) ^^ scarry( result, CYz );\n}\n\n#Note: used for subtraction op1 - (op2 + !CY)\n#sets tmpCY if there is NO borrow\nmacro sub_with_carry_flags(op1, op2){\n local result = op1 - op2;\n tmpCY = (op1 > op2) || (result < zext(CY));\n tmpOV = sborrow(op1,op2) ^^ sborrow(result,zext(!CY));\t\n}\n\n\n:adc^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n add_with_carry_flags(rn,shift1);\n Rd = rn+shift1+zext(CY);\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:adc^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n add_with_carry_flags(rn,shift2);\n Rd = rn+shift2+zext(CY);\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:adc^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n add_with_carry_flags(rn,shift3);\n Rd = rn+shift3+zext(CY);\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:adc^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n add_with_carry_flags(rn,shift1);\n dest:4 = rn + shift1 + zext(CY);\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:adc^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n add_with_carry_flags(rn,shift2);\n dest:4 = rn + shift2 + zext(CY);\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:adc^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n add_with_carry_flags(rn,shift3);\n dest:4 = rn + shift3 + zext(CY);\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\nArmPCRelImmed12: reloff\t\tis U23=1 & immed & rotate\n [ reloff = inst_start + 8 + ( ((immed<<(32-rotate*2))|(immed>>(rotate*2))) $and 0xffffffff); ]\n{\n export *[const]:4 reloff;\n}\n\nArmPCRelImmed12: reloff\t\tis U23=0 & immed & rotate\n [ reloff = inst_start + 8 - ( ((immed<<(32-rotate*2))|(immed>>(rotate*2))) $and 0xffffffff); ]\n{\n export *[const]:4 reloff;\n}\n\n#\n# ADR constructors must appear before ADD constructors to give ADR parsing precedence\n#\n\n:adr^COND Rd,ArmPCRelImmed12\tis $(AMODE) & ARMcond=1 & COND & c2527=1 & (c2024=8 | c2024=4) & Rn=15 & Rd & ArmPCRelImmed12\n{\n build COND;\n Rd = ArmPCRelImmed12;\n}\n\n:adr^COND pc,ArmPCRelImmed12 \tis $(AMODE) & ARMcond=1 & COND & c2527=1 & (c2024=8 | c2024=4) & Rn=15 & Rd=15 & pc & ArmPCRelImmed12\n{\n build COND;\n dest:4 = ArmPCRelImmed12;\n ALUWritePC(dest);\n goto [pc];\n}\n\n\n:add^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n addflags(rn,shift1);\n Rd = rn + shift1;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:add^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n addflags(rn,shift2);\n Rd = rn + shift2;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:add^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n addflags(rn,shift3);\n Rd = rn + shift3;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:add^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n addflags(rn,shift1);\n dest:4 = rn + shift1;\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:add^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n addflags(rn,shift2);\n dest:4 = rn + shift2;\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:add^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n addflags(rn,shift3);\n dest:4 = rn + shift3;\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:and^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n Rd = rn & shift1;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:and^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n Rd = rn & shift2;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:and^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n Rd = rn & shift3;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:and^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n dest:4 = rn & shift1;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:and^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n dest:4 = rn & shift2;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:and^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n dest:4 = rn & shift3;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n# must match first! before conditional goto\n\n:b Addr24 \t\t\tis $(AMODE) & cond=14 & c2527=5 & L24=0 & Addr24\n{\n goto Addr24;\n}\n\n:b^cc Addr24 \t\t\tis $(AMODE) & cc & c2527=5 & L24=0 & Addr24\n{\n if (cc) goto Addr24;\n}\n\n\n\n@if defined(VERSION_6T2)\n\n:bfc^COND Rd,lsbImm,bitWidth\tis $(AMODE) & ARMcond=1 & COND & c2127=0x3e & msbImm & Rd & lsbImm & bitWidth & c0006=0x1f \t{\n\tbuild COND;\n\tbuild lsbImm;\n\tbuild msbImm;\n\tbuild bitWidth;\n\tclearMask:4 = (-1 << (msbImm + 1)) | (-1 >> (32 - lsbImm));\n\tRd = Rd & clearMask;\n}\n\n:bfi^COND Rd,Rm,lsbImm,bitWidth\tis $(AMODE) & ARMcond=1 & COND & c2127=0x3e & Rd & Rm & lsbImm & bitWidth & c0406=1\t{\n\tbuild COND;\n\tbuild lsbImm;\n\tbuild bitWidth;\n\tvmask:4 = (1 << bitWidth) - 1;\n\tclear:4 = ~(vmask << lsbImm);\n\tbits:4 = (Rm & vmask) << lsbImm;\n\tRd = (Rd & clear) | bits;\n}\n\n@endif # VERSION_6T2\n\n:bic^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n Rd = rn&(~shift1);\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:bic^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n Rd = rn&(~shift2);\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:bic^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n Rd = rn&(~shift3);\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:bic^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n dest:4 = rn&(~shift1);\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:bic^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n dest:4 = rn&(~shift2);\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:bic^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n dest:4 = rn&(~shift3);\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n# bl used as a PIC instruction to get at current PC in lr\n:bl Addr24 \t\tis $(AMODE) & cond=14 & c2527=5 & L24=1 & immed24=0xffffff & Addr24\n{\n lr = inst_next;\n goto Addr24;\n}\n\n# bl used as a PIC instruction to get at current PC in lr\n:bl^COND Addr24 \t\tis $(AMODE) & ARMcond=1 & COND & c2527=5 & L24=1 & immed24=0xffffff & Addr24\n{\n build COND;\n build Addr24;\n lr = inst_next;\n goto Addr24;\n}\n\n:bl Addr24 \t\tis $(AMODE) & cond=14 & c2527=5 & L24=1 & Addr24\n{\n lr = inst_next;\n call Addr24;\n}\n\n:bl^COND Addr24 \t\tis $(AMODE) & CALLoverride=0 & COND & c2527=5 & L24=1 & Addr24\n{\n build COND;\n build Addr24;\n lr = inst_next;\n call Addr24;\n}\n\n:bl^COND Addr24 \t\tis $(AMODE) & CALLoverride=1 & COND & c2527=5 & L24=1 & Addr24\n{\n build COND;\n build Addr24;\n lr = inst_next;\n goto Addr24;\n}\n\n# blx(1) instruction\n@if defined(T_VARIANT) && defined(VERSION_5)\n\n# Two forms of blx needed to distinguish from b\n:blx HAddr24\t\t\tis $(AMODE) & CALLoverride=0 & ARMcond=0 & cond=15 & c2527=5 & H24=0 & HAddr24\n{\n lr = inst_next;\n SetISAModeSwitch(1); # TMode done by HAddr24's globalset\n call HAddr24;\n # don't do causes decompiler trouble TB = 0;\n} # Always changes to THUMB mode\n\n:blx HAddr24\t\t\tis $(AMODE) & CALLoverride=1 & ARMcond=0 & cond=15 & c2527=5 & H24=0 & HAddr24\n{\n lr = inst_next;\n SetISAModeSwitch(1); # TMode done by HAddr24's globalset\n goto HAddr24;\n} # Always changes to THUMB mode\n\n\n:blx HAddr24 \t\t\tis $(AMODE) & ARMcond=0 & CALLoverride=0 & cond=15 & c2527=5 & H24=1 & HAddr24\n{\n lr = inst_next;\n SetISAModeSwitch(1); # TMode done by HAddr24's globalset\n call HAddr24;\n # don't do causes decompiler trouble TB = 0;\n} # Always changes to THUMB mode\n\n:blx HAddr24 \t\t\tis $(AMODE) & ARMcond=0 & CALLoverride=1 & cond=15 & c2527=5 & H24=1 & HAddr24\n{\n lr = inst_next;\n SetISAModeSwitch(1); # TMode done by HAddr24's globalset\n goto HAddr24;\n} # Always changes to THUMB mode\n\n@endif # T_VARIANT && VERSION_5\n\n@if defined(VERSION_5)\n\n:blx^COND rm \t\t\tis $(AMODE) & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=3 & rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n lr=inst_next;\n call [pc];\n# don't do causes decompiler trouble TB = 0;\n} # Optional THUMB\n\n:blx^COND rm \t\t\tis $(AMODE) & CALLoverride=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=3 & rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n lr=inst_next;\n goto [pc];\n} # Optional THUMB\n\n@endif # VERSION_5\n\n@if defined(VERSION_5_or_T)\n\n# if branching using lr, assume return\n:bx^COND rm \t\t\tis $(AMODE) & REToverride=0 & LRset=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm & Rm=14\n{\n build COND;\n build rm;\n BXWritePC(rm);\n return [pc];\n} # Optional change to THUMB\n\n:bx^COND rm \t\t\tis $(AMODE) & REToverride=0 & LRset=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm & Rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n goto [pc];\n} # Optional change to THUMB\n\n# if lr has just been set, assume call\n:bx^COND rm \t\t\tis $(AMODE) & REToverride=0 & LRset=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm & Rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n call [pc];\n} # Optional change to THUMB\n\n:bx^COND rm \t\t\tis $(AMODE) & REToverride=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n goto [pc];\n} # Optional change to THUMB\n\n#:bx^COND lr \t\t\tis $(AMODE) & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & Rm=14 & lr\n#{\n# build COND;\n# TB=(lr&0x00000001)!=0;\n# tmp = lr & 0xfffffffe;\n# return [tmp];\n#} # Optional change to THUMB\n\n@endif # VERSION_5_or_T\n\n@if defined(VERSION_6)\n\n# bxj behaves like bx except that Jazelle state is enabled if available (added with Version-5 J-variant)\n\n:bxj^COND rm \t\t\tis $(AMODE) & REToverride=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=2 & rm\n{\n build COND;\n build rm;\n success:1 = jazelle_branch();\n if (success) goto ;\n BXWritePC(rm);\n return [pc];\n \n} # Optional change to THUMB\n\n# if branching using \"ip\" then is a goto\n:bxj^COND rm \t\t\tis $(AMODE) & REToverride=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=2 & rm & Rm=12\n{\n build COND;\n build rm;\n success:1 = jazelle_branch();\n if (success) goto ;\n BXWritePC(rm);\n goto [pc];\n \n} # Optional change to THUMB\n\n:bxj^COND rm \t\t\tis $(AMODE) & REToverride=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=2 & rm\n{\n build COND;\n build rm;\n success:1 = jazelle_branch();\n if (success) goto ;\n BXWritePC(rm);\n goto [pc];\n \n} # Optional change to THUMB\n\n@endif # VERSION_6\n\n@if defined(VERSION_5)\n\n:cdp2 cpn,opcode1,CRd,CRn,CRm,opcode2 is $(AMODE) & ARMcond=0 & cond=15 & c2427=14 & opcode1 & CRn & CRd & cpn & opcode2 & c0404=0 & CRm\n{\n t_cpn:4 = cpn;\n t_op1:4 = opcode1;\n t_op2:4 = opcode2;\n coprocessor_function2(t_cpn,t_op1,t_op2,CRd,CRn,CRm);\n}\n\n@endif # VERSION_5\n\n:cdp^COND cpn,opcode1,CRd,CRn,CRm,opcode2 is $(AMODE) & ARMcond=1 & COND & c2427=14 & opcode1 & CRn & CRd & cpn & opcode2 & c0404=0 & CRm\n{\n build COND;\n t_cpn:4 = cpn;\n t_op1:4 = opcode1;\n t_op2:4 = opcode2;\n coprocessor_function(t_cpn,t_op1,t_op2,CRd,CRn,CRm);\n}\n\n@if defined(VERSION_6K) || defined(VERSION_7)\n\n:clrex\tis $(AMODE) & c0031=0xf57ff01f\t{\n\tClearExclusiveLocal();\n}\n\n@endif # VERSION_6K\n\n@if defined(VERSION_5)\n\n:clz^COND Rd,rm \t\tis $(AMODE) & ARMcond=1 & COND & c2027=22 & c1619=15 & Rd & c0811=15 & c0407=1 & rm\n{\n build COND;\n build rm;\n Rd = lzcount(rm);\n}\n\n@endif # VERSION_5\n\n:cmn^COND rn,shift1 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=23 & rn & c1215=0 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n addflags(rn,shift1);\n local tmp = rn + shift1;\n resultflags(tmp);\n affectflags();\n}\n\n:cmn^COND rn,shift2 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=23 & rn & c1215=0 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n addflags(rn,shift2);\n local tmp = rn + shift2;\n resultflags(tmp);\n affectflags();\n}\n\n:cmn^COND rn,shift3 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=23 & rn & c1215=0 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n addflags(rn,shift3);\n local tmp = rn + shift3;\n resultflags(tmp);\n affectflags();\n}\n\n:cmp^COND rn,shift1 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=21 & rn & c1215=0 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n subflags(rn,shift1);\n local tmp = rn - shift1;\n resultflags(tmp);\n affectflags();\n}\n\n:cmp^COND rn,shift2 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=21 & rn & c1215=0 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n subflags(rn,shift2);\n local tmp = rn - shift2;\n resultflags(tmp);\n affectflags();\n}\n\n:cmp^COND rn,shift3 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=21 & rn & c1215=0 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n subflags(rn,shift3);\n local tmp = rn - shift3;\n resultflags(tmp);\n affectflags();\n}\n\n@if defined(VERSION_6)\n\n# cpy is a pre-UAL synonym for mov\n:cpy^COND pc,rm \tis $(AMODE) & ARMcond=1 & LRset=0 & COND & pc & c2027=0x1a & c1619=0 & c0411=0 & Rd=15 & rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n goto [pc];\n}\n\n:cpy^COND pc,lr \t\tis $(AMODE) & ARMcond=1 & LRset=0 & COND & pc & c2527=0 & S20=0 & c2124=13 & c1619=0 & Rd=15 & sftimm=0 & c0406=0 & Rm=14 & lr\n{\n build COND;\n dest:4 = lr;\n ALUWritePC(dest);\n return [pc];\n}\n\n:cpy^COND pc,rm \tis $(AMODE) & ARMcond=1 & LRset=1 & COND & pc & c2027=0x1a & c1619=0 & c0411=0 & Rd=15 & rm\n{\n build COND;\n build rm;\n BXWritePC(rm);\n call [pc];\n}\n\n:cpy^COND lr,rm \tis $(AMODE) & ARMcond=1 & COND & c2027=0x1a & c1619=0 & c0411=0 & Rd=14 & lr & rm & Rm2=15\n [ LRset=1; globalset(inst_next,LRset); ]\n{\n build COND;\n lr = rm;\n}\n\n:cpy^COND Rd,rm \tis $(AMODE) & ARMcond=1 & COND & c2027=0x1a & c1619=0 & c0411=0 & Rd & rm\n{\n build COND;\n build rm;\n Rd = rm;\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6K) || defined(VERSION_6T2)\n\n:dbg^COND optionImm\tis $(AMODE) & ARMcond=1 & COND & c0427=0x320f0f & optionImm\t{\n@if defined(VERSION_7)\n\tbuild COND;\n\tbuild optionImm;\n\tHintDebug(optionImm);\n@endif # VERSION_7\n}\n\n@endif # VERSION_6K || VERSION_6T2\n\n@if defined(VERSION_7)\n\n\n\n:dmb dbOption\tis $(AMODE) & c0431=0xf57ff05 & dbOption\t{\n\tDataMemoryBarrier(dbOption:1);\n}\n\n:dsb dbOption\tis $(AMODE) & c0431=0xf57ff04 & dbOption\t{\n\tDataSynchronizationBarrier(dbOption:1);\n}\n\n@endif # VERSION_7\n\n:eor^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n Rd = rn^shift1;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:eor^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n Rd = rn^shift2;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:eor^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n Rd = rn^shift3;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:eor^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n dest:4 = rn^shift1;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:eor^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n dest:4 = rn^shift2;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:eor^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n dest:4 = rn^shift3;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n@if defined(VERSION_7)\n\n\n:isb ibOption\tis $(AMODE) & c0431=0xf57ff06 & ibOption\t{\n\tInstructionSynchronizationBarrier(ibOption:1);\n}\n\n@endif # VERSION_7\n\n### These must come first, because of cond=15 match\n@if defined(VERSION_5)\n\n:ldc2 cpn,CRd,addrmode5 \tis $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=1\n{\n t_cpn:4 = cpn;\n coprocessor_load2(t_cpn,CRd,addrmode5);\n}\n\n:ldc2l cpn,CRd,addrmode5 \tis $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=1\n{\n t_cpn:4 = cpn;\n coprocessor_loadlong2(t_cpn,CRd,addrmode5);\n}\n\n@endif # VERSION_5\n######## cond=15 match\n\n:ldc^COND cpn,CRd,addrmode5 \tis $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=1\n{\n build COND;\n build addrmode5;\n t_cpn:4 = cpn;\n coprocessor_load(t_cpn,CRd,addrmode5);\n}\n\n:ldcl^COND cpn,CRd,addrmode5 is $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=1\n{\n build COND;\n build addrmode5;\n t_cpn:4 = cpn;\n coprocessor_loadlong(t_cpn,CRd,addrmode5);\n}\n\n:ldm^mdir^COND reglist \t\tis $(AMODE) & ARMcond=1 & COND & c2527=4 & mdir & L20=1 & c1515=0 & reglist\n{\n build COND;\n build reglist;\n}\n\n:ldm^mdir^COND reglist \t\tis $(AMODE) & ARMcond=1 & COND & c2527=4 & mdir & L20=1 & c1515=1 & reglist\n{\n build COND;\n build reglist;\n LoadWritePC(pc);\n return [pc];\n}\n\n#:ldr^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & B22=0 & L20=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n#{\n# build COND;\n# build addrmode2;\n# tmp:4=addrmode2&0xfffffffc;\n# tmp2:4=(addrmode2&3)<<3;\n# Rd=*tmp;\n# Rd = (Rd >> tmp2) | (Rd << (32-tmp2));\n#}\n\n# The following form of ldr assumes alignment checking is on\n:ldr^COND Rd,addrmode2 \t\tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n Rd = *addrmode2;\n}\n\n# Two forms of ldr with destination=pc needed to distinguish from ldrt\n:ldr^COND pc,addrmode2 \t\tis $(AMODE) & pc & ARMcond=1 & COND & LRset=1 & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=1 & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n [ LRset=0; globalset(inst_next,LRset); ]\n{\n build COND;\n build addrmode2;\n dest:4=*addrmode2;\n SetThumbMode((dest&0x00000001)!=0);\n pc=dest&0xfffffffe;\n call [pc];\n SetThumbMode(0);\n} # No unaligned address\n\n:ldr^COND pc,addrmode2 \t\tis $(AMODE) & pc & ARMcond=1 & COND & LRset=1 & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=0 & W21=0 & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n [ LRset=0; globalset(inst_next,LRset); ]\n{\n build COND;\n build addrmode2;\n dest:4=*addrmode2;\n SetThumbMode((dest&0x00000001)!=0);\n pc=dest&0xfffffffe;\n call [pc];\n SetThumbMode(0);\n} # No unaligned address\n\n# Two forms of ldr with destination=pc needed to distinguish from ldrt\n:ldr^COND pc,addrmode2 \t\tis $(AMODE) & pc & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=1 & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n dest:4=*addrmode2;\n BXWritePC(dest);\n goto [pc];\n} # No unaligned address\n\n:ldr^COND pc,addrmode2 \t\tis $(AMODE) & pc & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=0 & W21=0 & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n dest:4=*addrmode2;\n BXWritePC(dest);\n goto [pc];\n} # No unaligned address\n\n:ldrb^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=1 & L20=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n Rd = zext( *:1 addrmode2);\n}\n\n:ldrbt^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=1 & L20=1 & P24=0 & W21=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n Rd = zext( *:1 addrmode2);\n}\n\n@if defined(VERSION_5E)\n\n:ldrd^COND Rd,Rd2,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & c0407=13 & c1212=0 & L20=0 & Rd & Rd2 & addrmode3\n{\n build COND;\n build addrmode3;\n Rd = *(addrmode3);\n Rd2 = *(addrmode3+4);\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:ldrex^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xf9f\n{\n\tbuild COND;\n\tRd = *Rn;\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6K)\n\n:ldrexb^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xf9f\n{\n\tbuild COND;\n\tRd = zext(*:1 Rn);\n}\n\n:ldrexd^COND Rd,Rd2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xf9f\n{\n build COND;\n local addr:4 = Rn;\n Rd = *(addr);\n Rd2 = *(addr + 4);\n}\n\n:ldrexh^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xf9f\n{\n\tbuild COND;\n\tRd = zext(*:2 Rn);\n}\n\n@endif # VERSION_6K\n\n:ldrh^COND Rd,addrmode3 \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=1 & c0407=11 & Rd & addrmode3\n{\n build COND;\n build addrmode3;\n Rd = zext( *:2 addrmode3);\n}\n\n@if defined(VERSION_6T2)\n\n:ldrht^COND Rd,addrmode3\t\tis $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=1 & c0407=11 & Rd & addrmode3\t{\n build COND;\n build addrmode3;\n Rd = zext( *:2 addrmode3);\n}\n\n@endif # VERSION_6T2\n\n:ldrsb^COND Rd,addrmode3 \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=1 & c0407=13 & Rd & addrmode3\n{\n build COND;\n build addrmode3;\n Rd = sext( *:1 addrmode3);\n}\n\n@if defined(VERSION_6T2)\n\n:ldrsbt^COND Rd,addrmode3\t\tis $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=1 & c0407=13 & Rd & addrmode3\t{\n build COND;\n build addrmode3;\n Rd = sext( *:1 addrmode3);\n}\n\n@endif # VERSION_6T2\n\n:ldrsh^COND Rd,addrmode3 \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=1 & c0407=15 & Rd & addrmode3\n{\n build COND;\n build addrmode3;\n Rd = sext( *:2 addrmode3);\n}\n\n@if defined(VERSION_6T2)\n\n:ldrsht^COND Rd,addrmode3\t\tis $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=1 & c0407=15 & Rd & addrmode3\t{\n build COND;\n build addrmode3;\n Rd = sext( *:2 addrmode3);\n}\n\n@endif # VERSION_6T2\n\n# The following form of ldr assumes alignment checking is on\n:ldrt^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & P24=0 & W21=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n Rd = *addrmode2;\n}\n\n\n###### must come first cond=15\n@if defined(VERSION_5)\n:mcr2 cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=0 & cond=15 & c2427=14 & opc1 & c2020=0 & CRn & Rd & cpn & opc2 & c0404=1 & CRm\n{\n t_cpn:4 = cpn;\n t_op1:4 = opc1;\n t_op2:4 = opc2;\n coprocessor_moveto(t_cpn,t_op1,t_op2,Rd,CRn,CRm);\n}\n@endif # VERSION_5\n###### must come first cond=15\n\n\n# ===== START mcr\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Main_ID(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Cache_Type(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_TCM_Status(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_TLB_Type(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Control(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Auxiliary_Control(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Coprocessor_Access_Control(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Secure_Configuration(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Secure_Debug_Enable(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_NonSecure_Access_Control(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Translation_table_base_0(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Translation_table_base_1(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Translation_table_control(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=3 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Domain_Access_Control(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=5 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Data_Fault_Status(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=5 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Instruction_Fault(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=6 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Fault_Address(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=6 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Instruction_Fault(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Wait_for_interrupt(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Entire_Instruction(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Instruction_Cache_by_MVA(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Flush_Prefetch_Buffer(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=6 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Entire_Data_cache(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=6 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Entire_Data_by_MVA(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=6 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Entire_Data_by_Index(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Clean_Entire_Data_Cache(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Clean_Data_Cache_by_MVA(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Clean_Data_Cache_by_Index(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Data_Synchronization(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=5 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Data_Memory_Barrier(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=14 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Entire_Data_Cache(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=14 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_Data_Cache_by_MVA(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=7 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=8 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_unified_TLB_unlocked(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=7 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=8 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_unified_TLB_by_MVA(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=7 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=8 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Invalidate_unified_TLB_by_ASID_match(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_FCSE_PID(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Context_ID(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_User_RW_Thread_and_Process_ID(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_User_R_Thread_and_Process_ID(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Privileged_only_Thread_and_Process_ID(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=2 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=15 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n coproc_moveto_Peripherial_Port_Memory_Remap(Rd);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opt2:4=opc2;\n coproc_moveto_Feature_Identification(Rd,t_opt2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=2 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opt2:4=opc2;\n coproc_moveto_ISA_Feature_Identification(Rd,t_opt2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=4 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=2 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n coproc_moveto_Peripheral_Port_Memory_Remap(Rd,t_opc2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n coproc_moveto_Control_registers(Rd, t_opc2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n coproc_moveto_Security_world_control(Rd, t_opc2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n coproc_moveto_Translation_table(Rd,t_opc2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n coproc_moveto_Instruction_cache(Rd,t_opc2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n coproc_moveto_Data_cache_operations(Rd,t_opc2);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2; t_crm:4 = CRm;\n coproc_moveto_Identification_registers(Rd,t_opc2,t_crm);\n}\n\n\n:mcr^COND mcrOperands is \n $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=15 & c2020=0 & opc1 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2; t_crm:4 = CRm; t_op1:4 = opc1;\n coproc_moveto_Peripheral_System(Rd,t_opc2,t_crm,t_op1);\n}\n\n\n# ===== END mcr \n\n:mcr^COND cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=1 & COND & c2427=14 & opc1 & c2020=0 & CRn & Rd & cpn & opc2 & c0404=1 & CRm\n{\n build COND;\n t_cpn:4 = cpn;\n t_op1:4 = opc1;\n t_op2:4 = opc2;\n coprocessor_moveto(t_cpn,t_op1,t_op2,Rd,CRn,CRm);\n}\n\n##### must come first cond=15\n@if defined(VERSION_6)\n:mcrr2 cpn,opcode3,Rd,Rn,CRm is $(AMODE) & ARMcond=0 & cond=15 & c2027=0xc4 & cpn & opcode3 & Rd & Rn & CRm\n{\n t_cpn:4 = cpn;\n t_op:4 = opcode3;\n coprocessor_moveto2(t_cpn,t_op,Rd,Rn,CRm);\n}\n\n:mrrc2 cpn,opcode3,Rd,Rn,CRm is $(AMODE) & ARMcond=0 & cond=15 & c2027=0xc5 & cpn & opcode3 & Rd & Rn & CRm\n{\n t_cpn:4 = cpn;\n t_op:4 = opcode3;\n Rd = coprocessor_movefromRt(t_cpn,t_op,CRm);\n Rn = coprocessor_movefromRt2(t_cpn,t_op,CRm);\n}\n@endif # VERSION_6\n##### must come first cond=15\n\n\n@if defined(VERSION_5E)\n\n:mcrr^COND cpn,opcode3,Rd,Rn,CRm is $(AMODE) & c2027=0xc4 & COND & ARMcond=1 & cpn & opcode3 & Rd & Rn & CRm\n{\n build COND;\n t_cpn:4 = cpn;\n t_op:4 = opcode3;\n coprocessor_moveto2(t_cpn,t_op,Rd,Rn,CRm);\n}\n\n:mrrc^COND cpn,opcode3,Rd,Rn,CRm is $(AMODE) & c2027=0xc5 & COND & ARMcond=1 & cpn & opcode3 & Rd & Rn & CRm\n{\n build COND;\n t_cpn:4 = cpn;\n t_op:4 = opcode3;\n Rd = coprocessor_movefromRt(t_cpn,t_op,CRm);\n Rn = coprocessor_movefromRt2(t_cpn,t_op,CRm);\n}\n\n@endif # VERSION_5E\n\n:mla^COND^SBIT_ZN Rn,Rm,Rs,Rd \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=1 & SBIT_ZN & Rn & Rd & Rs & c0407=9 & Rm\n{\n build COND;\n Rn = Rm*Rs + Rd;\n resultflags(Rn);\n build SBIT_ZN;\n}\n\n@if defined(VERSION_6T2)\n\n:mls^COND Rn,Rm,Rs,Rd \tis $(AMODE) & ARMcond=1 & COND & c2027=0x06 & Rn & Rd & Rs & c0407=9 & Rm {\n build COND;\n Rn = Rd - Rm*Rs;\n}\n\n@endif # VERSION_6T2\n\n:mov^COND^SBIT_CZNO Rd,shift1 \tis $(AMODE) & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift1\n{\n build COND;\n build shift1;\n Rd = shift1;\n resultflags(Rd);\n logicflags();\n build SBIT_CZNO;\n}\n\n:mov^COND^SBIT_CZNO Rd,shift2 \tis $(AMODE) & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift2\n{\n build COND;\n build shift2;\n Rd = shift2;\n resultflags(Rd);\n logicflags();\n build SBIT_CZNO;\n}\n\n:mov lr,pc\t\t\t\t\t\tis $(AMODE) & ARMcond=1 & c0031=0xe1a0e00f & lr & pc\n\t\t\t\t\t\t\t\t\t[ LRset=1; globalset(inst_next,LRset); ]\n{\n\tlr = inst_next + 4;\n\tresultflags(lr);\n\tlogicflags();\n}\n\n:mov^COND^SBIT_CZNO Rd,shift3 \tis $(AMODE) & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift3\n{\n build COND;\n build shift3;\n Rd = shift3;\n resultflags(Rd);\n logicflags();\n build SBIT_CZNO;\n}\n\n:mov^COND^SBIT_CZNO pc,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build shift1;\n SetThumbMode((shift1&0x00000001)!=0);\n local tmp=shift1&0xfffffffe;\n resultflags(tmp);\n logicflags();\n build SBIT_CZNO;\n ALUWritePC(tmp);\n goto [pc];\n}\n\n:mov^COND^SBIT_CZNO pc,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build shift2;\n SetThumbMode((shift2&0x00000001)!=0);\n local tmp=shift2&0xfffffffe;\n resultflags(tmp);\n logicflags();\n build SBIT_CZNO;\n ALUWritePC(tmp);\n goto [pc];\n}\n:mov^COND^SBIT_CZNO pc,shift2 \tis $(AMODE) & LRset=1 & pc & COND & ARMcond=1 & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build shift2;\n SetThumbMode((shift2&0x00000001)!=0);\n local tmp=shift2&0xfffffffe;\n resultflags(tmp);\n logicflags();\n build SBIT_CZNO;\n ALUWritePC(tmp);\n call [pc];\n}\n\n:mov^COND^SBIT_CZNO pc,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build shift3;\n SetThumbMode((shift3&0x00000001)!=0);\n local tmp=shift3&0xfffffffe;\n resultflags(tmp);\n logicflags();\n build SBIT_CZNO;\n ALUWritePC(tmp);\n goto [pc];\n}\n\n:mov lr,rm \t\tis $(AMODE) & ARMcond=0 & cond=15 & c2527=0 & S20=0 & c2124=13 & c1619=0 & rm & Rm2=15 & sftimm=0 & c0406=0 & Rd=14 & lr\n [ LRset=1; globalset(inst_next,LRset); ]\n{\n lr = rm;\n}\n\n@if defined(VERSION_6T2)\n\n:movw^COND Rd,\"#\"^val\t\tis $(AMODE) & ARMcond=1 & COND & c2027=0x30 & c1619 & Rd & c0011 [ val = (c1619 << 12) | c0011; ]\t\t{\n\tbuild COND;\n\tRd = val;\n}\n\n:movt^COND Rd,\"#\"^val\t\tis $(AMODE) & ARMcond=1 & COND & c2027=0x34 & c1619 & Rd & c0011 [ val = (c1619 << 12) | c0011; ]\t\t{\n\tbuild COND;\n\tRd = (val << 16) | (Rd & 0xffff);\n}\n\n@endif # VERSION_6T2\n\n###### must come before next instruction because cond=15\n@if defined(VERSION_5)\n\n\n:mrc2 cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=0 & cond=15 & c2427=14 & opc1 & c2020=1 & CRn & Rd & cpn & opc2 & c0404=1 & CRm\n{\n t_cpn:4 = cpn;\n t_op1:4 = opc1;\n t_op2:4 = opc2;\n Rd = coprocessor_movefromRt(t_cpn,t_op1,t_op2,CRn,CRm);\n}\n@endif # VERSION_5\n\n# ===== Start mrc\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Main_ID();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Cache_Type();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_TCM_Status();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_TLB_Type();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Control();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Auxiliary_Control();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Coprocessor_Access_Control();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Secure_Configuration();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Secure_Debug_Enable();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_NonSecure_Access_Control();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Translation_table_base_0();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Translation_table_base_1();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Translation_table_control();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=3 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Domain_Access_Control();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=5 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Instruction_Fault_Status();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=5 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Data_Fault_Status();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=6 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Fault_Address();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=6 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Instruction_Fault_Address();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Wait_for_interrupt();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Entire_Instruction();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Instruction_Cache_by_MVA();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Flush_Prefetch_Buffer();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=6 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Entire_Data_cache();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=6 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Entire_Data_by_MVA();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=6 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Entire_Data_by_Index();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Clean_Entire_Data_Cache();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Clean_Data_Cache_by_MVA();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Clean_Data_Cache_by_Index();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Data_Synchronization();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2=5 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Data_Memory_Barrier();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=14 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Entire_Data_Cache();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=14 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_Data_Cache_by_MVA();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=7 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=8 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_unified_TLB_unlocked();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=7 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=8 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_unified_TLB_by_MVA();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=7 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=8 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Invalidate_unified_TLB_by_ASID_match();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_FCSE_PID();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Context_ID();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_User_RW_Thread_and_Process_ID();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_User_R_Thread_and_Process_ID();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Privileged_only_Thread_and_Process_ID();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=2 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=15 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n Rd = coproc_movefrom_Peripherial_Port_Memory_Remap();\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opt2:4=opc2;\n Rd = coproc_movefrom_Feature_Identification(t_opt2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=2 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_ISA_Feature_Identification(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=4 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=2 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_Peripheral_Port_Memory_Remap(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_Control_registers(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_Security_world_control(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_Translation_table(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=5 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_Instruction_cache(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm=10 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2;\n Rd = coproc_movefrom_Data_cache_operations(t_opc2);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2; t_crm:4 = CRm;\n Rd = coproc_movefrom_Identification_registers(t_opc2,t_crm);\n}\n\n\n\n:mrc^COND mcrOperands is \n $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=15 & c2020=1 & opc1 & c2427=14 & COND & ARMcond=1 &\n mcrOperands\n{\n build COND;\n t_opc2:4 = opc2; t_crm:4 = CRm; t_op1:4 = opc1;\n Rd = coproc_movefrom_Peripheral_System(t_opc2,t_crm,t_op1);\n}\n\n\n\n# ===== End mrc\n\n:mrc^COND cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=1 & COND & c2427=14 & opc1 & c2020=1 & CRn & Rd & cpn & opc2 & c0404=1 & CRm\n{\n build COND;\n t_cpn:4 = cpn;\n t_op1:4 = opc1;\n t_opc2:4 = opc2;\n Rd = coprocessor_movefromRt(t_cpn,t_op1,t_opc2,CRn,CRm);\n}\n\n\n:mrs^COND Rd,cpsr \t\tis $(AMODE) & ARMcond=1 & COND & c2027=16 & c1619=15 & Rd & offset_12=0 & cpsr\n{\n# TODO: GE bits have not been included\n build COND;\n Rd = zext( (NG<<4) | (ZR<<3) | (CY<<2) | (OV<<1) | (Q) ) << 27;\n}\n\n:mrs^COND Rd,spsr \t\tis $(AMODE) & ARMcond=1 & COND & c2027=20 & c1619=15 & Rd & offset_12=0 & spsr\n{\n build COND;\n Rd = spsr;\n}\n\n:msr^COND cpsrmask,shift1 \tis $(AMODE) & ARMcond=1 & COND & c2027=50 & cpsrmask & c1215=15 & c2627=0 & shift1\n{\n build COND;\n build cpsrmask;\n build shift1;\n cpsr = (cpsr& ~cpsrmask) | (shift1 & cpsrmask);\n}\n\n:msr^COND cpsrmask,rm \t\tis $(AMODE) & ARMcond=1 & COND & c2027=18 & cpsrmask & c1215=15 & c0811=0 & c0407=0 & rm\n{\n# TODO: GE bits have not been included\n build COND;\n build cpsrmask;\n cpsr = (cpsr& ~cpsrmask) | (rm & cpsrmask);\n local tmp = cpsr >> 27 & 0x1f;\n Q = ((tmp ) & 0x1) != 0;\n OV = ((tmp >> 1) & 0x1) != 0;\n CY = ((tmp >> 2) & 0x1) != 0;\n ZR = ((tmp >> 3) & 0x1) != 0;\n NG = ((tmp >> 4) & 0x1) != 0;\n}\n\n:msr^COND spsrmask,shift1 \tis $(AMODE) & ARMcond=1 & COND & c2027=54 & spsrmask & c1215=15 & c2627=0 & shift1\n{\n build COND;\n build spsrmask;\n build shift1;\n spsr = (spsr& ~spsrmask) | (shift1 & spsrmask);\n}\n\n:msr^COND spsrmask,rm \t\tis $(AMODE) & ARMcond=1 & COND & c2027=22 & spsrmask & c1215=15 & c0811=0 & c0407=0 & rm\n{\n build COND;\n build spsrmask;\n spsr = (spsr& ~spsrmask) | (rm & spsrmask);\n}\n\n:mul^COND^SBIT_ZN rn,rm,rs \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=0 & SBIT_ZN & rn & c1215=0 & rs & c0407=9 & rm\n{\n build COND;\n build rm;\n build rs;\n rn = rm*rs;\n resultflags(rn);\n build SBIT_ZN;\n}\n\n:mvn^COND^SBIT_CZNO Rd,shift1 \tis $(AMODE) & ARMcond=1 & COND & c2124=15 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift1\n{\n build COND;\n build shift1;\n Rd=~shift1;\n resultflags(Rd);\n logicflags();\n build SBIT_CZNO;\n}\n\n:mvn^COND^SBIT_CZNO Rd,shift2 \tis $(AMODE) & ARMcond=1 & COND & c2124=15 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift2\n{\n build COND;\n build shift2;\n Rd=~shift2;\n resultflags(Rd);\n logicflags();\n build SBIT_CZNO;\n}\n\n:mvn^COND^SBIT_CZNO Rd,shift3 \tis $(AMODE) & ARMcond=1 & COND & c2124=15 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift3\n{\n build COND;\n build shift3;\n Rd=~shift3;\n resultflags(Rd);\n logicflags();\n build SBIT_CZNO;\n}\n\n:mvn^COND^SBIT_ZN pc,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=15 & SBIT_ZN & c1619=0 & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build shift1;\n dest:4 = ~shift1;\n resultflags(dest);\n build SBIT_ZN;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:mvn^COND^SBIT_ZN pc,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=15 & SBIT_ZN & c1619=0 & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build shift2;\n dest:4 = ~shift2;\n resultflags(dest);\n build SBIT_ZN;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:mvn^COND^SBIT_ZN pc,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=15 & SBIT_ZN & c1619=0 & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build shift3;\n dest:4 = ~shift3;\n resultflags(dest);\n build SBIT_ZN;\n ALUWritePC(dest);\n goto [pc];\n}\n\n@if defined(VERSION_6K) || defined(VERSION_6T2) || defined(VERSION_7)\n\n:nop^COND\t\tis $(AMODE) & ARMcond=1 & COND & c0027=0x320f000\t\t{\n}\n\n@endif # VERSION_6K\n\n:orr^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n Rd = rn|shift1;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:orr^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n Rd = rn|shift2;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:orr^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n Rd = rn|shift3;\n logicflags();\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:orr^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n dest:4 = rn|shift1;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:orr^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n dest:4 = rn|shift2;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:orr^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n dest:4 = rn|shift3;\n logicflags();\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n@if defined(VERSION_6)\n\n:pkhbt^COND Rd,rn,shift4 is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & c0406=1 & Rd & rn & shift4\n{\n build COND;\n build rn;\n build shift4;\n Rd = (rn & 0xffff) + (shift4 & 0xffff0000);\n}\n\n:pkhtb^COND Rd,rn,shift4 is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & c0406=5 & Rd & rn & shift4\n{\n build COND;\n build rn;\n build shift4;\n Rd = (shift4 & 0xffff) + (rn & 0xffff0000);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:qadd^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x10 & Rn & Rd & c0811=0 & c0407=5 & Rm\n{\n build COND;\n local sum1 = Rm + Rn;\n sum1 = SignedSaturate(sum1,32:2);\n Q = SignedDoesSaturate(sum1,32:2);\n Rd = sum1;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:qadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=1 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n sum1:2 = lRn:2 + lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 + uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n:qadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=9 & Rn & Rd & Rm\n{\n build COND;\n local rn1 = Rn & 0xff;\n local rm1 = Rm & 0xff;\n local rn2 = (Rn >> 8) & 0xff;\n local rm2 = (Rm >> 8) & 0xff;\n local rn3 = (Rn >> 16) & 0xff;\n local rm3 = (Rm >> 16) & 0xff;\n local rn4 = (Rn >> 24) & 0xff;\n local rm4 = (Rm >> 24) & 0xff;\n sum1:1 = rn1:1 + rm1:1;\n sum1 = SignedSaturate(sum1,8:2);\n sum2:1 = rn2:1 + rm2:1;\n sum2 = SignedSaturate(sum2,8:2);\n sum3:1 = rn3:1 + rm3:1;\n sum3 = SignedSaturate(sum3,8:2);\n sum4:1 = rn4:1 + rm4:1;\n sum4 = SignedSaturate(sum4,8:2);\n Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n# qaddsubx\n:qasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=3 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n sum1:2 = lRn:2 - lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 + uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:qdadd^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x14 & Rn & Rd & c0811=0 & c0407=5 & Rm\n{\n build COND;\n tmp:4 = Rn * 2;\n tmp = SignedSaturate(tmp,32:2);\n Q = SignedDoesSaturate(tmp,32:2);\n tmp = tmp + Rm;\n tmp = SignedSaturate(tmp,32:2);\n Q = Q | SignedDoesSaturate(tmp,32:2);\n Rd = tmp;\n}\n\n:qdsub^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x16 & Rn & Rd & c0811=0 & c0407=5 & Rm\n{\n build COND;\n tmp:4 = Rn * 2;\n tmp = SignedSaturate(tmp);\n Q = SignedDoesSaturate(tmp,32:2);\n tmp = Rm - tmp;\n tmp = SignedSaturate(tmp,32:2);\n Q = Q | SignedDoesSaturate(tmp,32:2);\n Rd = tmp;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n# qsubaddx\n:qsax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=5 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n sum1:2 = lRn:2 + lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 - uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:qsub^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x12 & Rn & Rd & c0811=0 & c0407=5 & Rm\n{\n build COND;\n tmp:4 = Rm - Rn;\n tmp = SignedSaturate(tmp,32:2);\n Q = SignedDoesSaturate(tmp,32:2);\n Rd = tmp;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:qsub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=7 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n sum1:2 = lRn:2 - lRm:2;\n sum1 = SignedSaturate(sum1,16:2);\n sum2:2 = uRn:2 - uRm:2;\n sum2 = SignedSaturate(sum2,16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n:qsub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=15 & Rn & Rd & Rm\n{\n build COND;\n local rn1 = Rn & 0xff;\n local rm1 = Rm & 0xff;\n local rn2 = (Rn >> 8) & 0xff;\n local rm2 = (Rm >> 8) & 0xff;\n local rn3 = (Rn >> 16) & 0xff;\n local rm3 = (Rm >> 16) & 0xff;\n local rn4 = (Rn >> 24) & 0xff;\n local rm4 = (Rm >> 24) & 0xff;\n sum1:1 = rn1:1 - rm1:1;\n sum1 = SignedSaturate(sum1,8:2);\n sum2:1 = rn2:1 - rm2:1;\n sum2 = SignedSaturate(sum2,8:2);\n sum3:1 = rn3:1 - rm3:1;\n sum3 = SignedSaturate(sum3,8:2);\n sum4:1 = rn4:1 - rm4:1;\n sum4 = SignedSaturate(sum4,8:2);\n Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2)\n\nmacro BitReverse_arm(val) {\n tval:1 = val;\n result:1 = 0;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n result = (result << 1) | (tval & 1);\n tval = tval >> 1;\n val = result;\n}\n\n\n:rbit^COND Rd, rm\tis $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=3 & c1619=15 & c0811=15 & Rd & rm\n{\n\tbuild COND;\n \tbuild rm;\n\tlocal t:4 = rm & 0xff;\n local b1:1 = t:1;\n t = (rm >> 8) & 0xff;\n local b2:1 = t:1;\n t = (rm >> 16) & 0xff;\n local b3:1 = t:1;\n t = (rm >> 24) & 0xff;\n local b4:1 = t:1;\n BitReverse_arm(b1);\n BitReverse_arm(b2);\n BitReverse_arm(b3);\n BitReverse_arm(b4);\n Rd = (zext(b1) << 24) | (zext(b2) << 16) | (zext(b3) << 8) | zext(b4);\n}\n\n@endif # VERSION_6T2\n\n@if defined(VERSION_6)\n\n:rev^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=3 & c1619=15 & c0811=15 & Rd & rm\n{\n build COND;\n build rm;\n local tmp1 = rm & 0xff;\n local tmp2 = (rm >> 8) & 0xff;\n local tmp3 = (rm >> 16) & 0xff;\n local tmp4 = (rm >> 24) & 0xff;\n Rd = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4;\n}\n\n:rev16^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=11 & Rd & rm\n{\n build COND;\n build rm;\n local tmp1 = rm & 0xff;\n local tmp2 = (rm >> 8) & 0xff;\n local tmp3 = (rm >> 16) & 0xff;\n local tmp4 = (rm >> 24) & 0xff;\n Rd = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | tmp2;\n}\n\n:revsh^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=11 & Rd & rm\n{\n build COND;\n build rm;\n local tmp1 = rm & 0xff;\n local tmp2 = (rm >> 8) & 0xff;\n tmp3:2 = zext(tmp1:1) << 8 | zext(tmp2:1);\n Rd = sext(tmp3);\n}\n\n@endif # VERSION_6\n\n:rsb^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n subflags(shift1,rn);\n Rd = shift1-rn;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:rsb^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n subflags(shift2,rn);\n Rd = shift2-rn;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:rsb^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n subflags(shift3,rn);\n Rd = shift3-rn;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:rsb^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n subflags(shift1,rn);\n dest:4 = shift1-rn;\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:rsb^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n subflags(shift2,rn);\n dest:4 = shift2-rn;\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:rsb^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n subflags(shift3,rn);\n dest:4 = shift3-rn;\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:rsc^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n sub_with_carry_flags(shift1,rn);\n Rd=shift1-(rn+zext(!CY));\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:rsc^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n sub_with_carry_flags(shift2,rn);\n Rd=shift2-(rn+zext(!CY));\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:rsc^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n sub_with_carry_flags(shift3,rn);\n Rd=shift3-(rn+zext(!CY));\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:rsc^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n sub_with_carry_flags(shift1,rn);\n local dest:4=shift1-(rn+zext(!CY));\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:rsc^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n sub_with_carry_flags(shift2,rn);\n local dest:4=shift2-(rn + zext(!CY));\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:rsc^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n sub_with_carry_flags(shift3,rn);\n local dest:4=shift3-(rn + zext(!CY));\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n@if defined(VERSION_6)\n\n:sadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=1 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn & 0xffff;\n local tmpRm = Rm & 0xffff;\n local sum1 = sext(tmpRn:2) + sext(tmpRm:2);\n GE1 = sum1 s>= 0;\n GE2 = sum1 s>= 0;\n tmpRn = (Rn >> 16) & 0xffff;\n tmpRm = (Rm >> 16) & 0xffff;\n local sum2 = sext(tmpRn:2) + sext(tmpRm:2);\n GE3 = sum2 s>= 0;\n GE4 = sum2 s>= 0;\n Rd = ((sum2 & 0xffff) << 16) | (sum1 & 0xffff);\n}\n\n:sadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=9 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn & 0xff;\n local tmpRm = Rm & 0xff;\n local sum1 = sext(tmpRn:1) + sext(tmpRm:1);\n GE1 = sum1 s>= 0;\n tmpRn = (Rn >> 8) & 0xff;\n tmpRm = (Rm >> 8) & 0xff;\n local sum2 = sext(tmpRn:1) + sext(tmpRm:1);\n GE2 = sum2 s>= 0;\n tmpRn = (Rn >> 16) & 0xff;\n tmpRm = (Rm >> 16) & 0xff;\n local sum3 = sext(tmpRn:1) + sext(tmpRm:1);\n GE3 = sum3 s>= 0;\n tmpRn = (Rn >> 24) & 0xff;\n tmpRm = (Rm >> 24) & 0xff;\n local sum4 = sext(tmpRn:1) + sext(tmpRm:1);\n GE4 = sum4 s>= 0;\n Rd = ((sum4 & 0xff) << 24) | ((sum3 & 0xff) << 16) | ((sum2 & 0xff) << 8) | (sum1 & 0xff);\n}\n\n# saddsubx\n:sasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=3 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n local sum1 = sext(uRn:2) + sext(lRm:2);\n GE3 = sum1 s>= 0;\n GE4 = sum1 s>= 0;\n local diff = sext(lRn:2) - sext(uRm:2);\n GE1 = diff s>= 0;\n GE2 = diff s>= 0;\n\n Rd = ((sum1 & 0xffff) << 16) | (diff & 0xffff);\n}\n\n@endif # VERSION_6\n\n:sbc^SBIT_CZNO^COND Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n sub_with_carry_flags(rn,shift1);\n Rd = rn-(shift1+zext(!CY));\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:sbc^SBIT_CZNO^COND Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n sub_with_carry_flags(rn,shift2);\n Rd = rn-(shift2 + zext(!CY));\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:sbc^SBIT_CZNO^COND Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n sub_with_carry_flags(rn,shift3);\n Rd = rn-(shift3+zext(!CY));\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:sbc^SBIT_CZNO^COND pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n sub_with_carry_flags(rn,shift1);\n local dest:4 = rn-(shift1 + zext(!CY));\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:sbc^SBIT_CZNO^COND pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n sub_with_carry_flags(rn,shift2);\n local dest:4 = rn-(shift2+zext(!CY));\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n:sbc^SBIT_CZNO^COND pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n sub_with_carry_flags(rn,shift3);\n local dest:4 = rn-(shift3 + zext(!CY));\n resultflags(dest);\n build SBIT_CZNO;\n ALUWritePC(dest);\n goto [pc];\n}\n\n@if defined(VERSION_6)\n\n@if defined(VERSION_6T2)\n\n:sbfx^COND Rd,Rm,lsbImm,widthMinus1\tis $(AMODE) & COND & ARMcond=1 & c2127=0x3d & widthMinus1 & Rd & lsbImm & c0406=5 & Rm\n{\n\tbuild COND;\n\tbuild lsbImm;\n\tbuild widthMinus1;\n\tshift:4 = 31 - (lsbImm + widthMinus1);\n\tRd = Rm << shift;\n\tshift = 31 - widthMinus1;\n\tRd = Rd s>> shift;\n}\n\n@endif # VERSION_6T2\n\n@if defined(VERSION_7)\n\n# Warning: note the non-standard use of Rd, Rm, Rn\n:sdiv^COND RdHi,RnLo,RmHi is $(AMODE) & ARMcond=1 & COND & c2027=0x71 & RdHi & c1215=0xf & RmHi & c0407=0x1 & RnLo\n{\n build COND;\n local result = RnLo s/ RmHi;\n RdHi = result;\n}\n\n@endif # VERSION_7\n\n:sel^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & Rn & Rd & c0811=15 & c0407=11 & Rm\n{\n\tbuild COND;\n\tlocal rD1 = ((zext(GE1) * Rn) + (zext(!GE1) * Rm)) & 0x0ff;\n\tlocal rD2 = ((zext(GE2) * Rn) + (zext(!GE2) * Rm)) & 0x0ff00;\n\tlocal rD3 = ((zext(GE3) * Rn) + (zext(!GE3) * Rm)) & 0x0ff0000;\n\tlocal rD4 = ((zext(GE4) * Rn) + (zext(!GE4) * Rm)) & 0x0ff000000;\n\tRd = rD1 | rD2 | rD3 | rD4;\n} \n\n@if defined(VERSION_6K)\n\n:sev^COND\tis $(AMODE) & ARMcond=1 & COND & c0027=0x320f004\n{\n\tbuild COND;\n\tSendEvent();\n}\n\n@endif # VERSION_6K\n\n# Hopefully we never encounter this instruction since we can not change the effective endianness of the language\narmEndianNess: \"LE\" is c0031=0xf1010000 { export 0:1; }\narmEndianNess: \"BE\" is c0031=0xf1010200 { export 1:1; }\n\n:setend armEndianNess is $(AMODE) & (c0031=0xf1010000 | c0031=0xf1010200) & armEndianNess { setEndianState(armEndianNess); }\n\n\n:shadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=1 & Rm \n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n sum1:4 = (sext(tmpRn:2) + sext(tmpRm:2)) >> 1;\n sum2:4 = ((tmpRn s>> 16) + (tmpRm s>> 16)) >> 1;\n Rd = (sum2 << 16) + (sum1 & 0xffff);\n}\n\n:shadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=9 & Rm \n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n sum1:4 = (sext(tmpRn:1) + sext(tmpRm:1)) >> 1;\n local tmpn = tmpRn >> 8;\n local tmpm = tmpRm >> 8;\n sum2:4 = (sext(tmpn:1) + sext(tmpm:1)) >> 1;\n tmpn = tmpRn >> 16;\n tmpm = tmpRm >> 16;\n sum3:4 = (sext(tmpn:1) + sext(tmpm:1)) >> 1;\n tmpn = tmpRn >> 24;\n tmpm = tmpRm >> 24;\n sum4:4 = (sext(tmpn:1) + sext(tmpm:1)) >> 1;\n Rd = (sum4 << 24) + ((sum3 & 0xff) << 16) + ((sum2 & 0xff) << 8) + (sum1 & 0xff);\n}\n\n# shaddsubx\n:shasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=3 & Rm \n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n local diff:4 = sext(tmpRn[ 0,16]) - sext(tmpRm[16,16]);\n local sum:4 = sext(tmpRn[16,16]) + sext(tmpRm[ 0,16]);\n Rd[0,16] = diff[1,16];\n Rd[16,16] = sum[1,16];\n}\n\n# shsubbaddx\n:shsax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=5 & Rm \n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n local sum:4 = sext(tmpRn[ 0,16]) + sext(tmpRm[16,16]);\n local diff:4 = sext(tmpRn[16,16]) - sext(tmpRm[ 0,16]);\n Rd[ 0,16] = sum[1,16];\n Rd[16,16] = diff[1,16];\n}\n\n:shsub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=7 & Rm \n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n sum1:4 = (sext(tmpRn:2) - sext(tmpRm:2)) >> 1;\n sum2:4 = ((tmpRn s>> 16) - (tmpRm s>> 16)) >> 1;\n Rd = (sum2 << 16) + (sum1 & 0xffff);\n}\n\n:shsub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=15 & Rm \n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n sum1:4 = (sext(tmpRn:1) - sext(tmpRm:1)) >> 1;\n local tmpn = tmpRn >> 8;\n local tmpm = tmpRm >> 8;\n sum2:4 = (sext(tmpn:1) - sext(tmpm:1)) >> 1;\n tmpn = tmpRn >> 16;\n tmpm = tmpRm >> 16;\n sum3:4 = (sext(tmpn:1) - sext(tmpm:1)) >> 1;\n tmpn = tmpRn >> 24;\n tmpm = tmpRm >> 24;\n sum4:4 = (sext(tmpn:1) - sext(tmpm:1)) >> 1;\n Rd = (sum4 << 24) + ((sum3 & 0xff) << 16) + ((sum2 & 0xff) << 8) + (sum1 & 0xff);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:smla^XBIT^YBIT^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x10 & smRd & smRn & smRm & c0707=1 & XBIT & YBIT & c0404=0 & smRa\n{\n\tbuild COND;\n\tlocal tmp:4 = sext(XBIT) * sext(YBIT);\n\tQ = scarry(tmp,smRa) || Q; #Q flag is sticky\n\tsmRd = tmp+smRa;\n}\n\n@endif\n\n@if defined(VERSION_6)\n\n:smlad^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=1 & smRd & smRa & smRm & smRn\n{\n build COND;\n local tmpRn = smRn;\n local tmpRm = smRm;\n local tmpLRn = tmpRn:2;\n local tmpURn = tmpRn >> 16;\n local tmpLRm = tmpRm:2;\n local tmpURm = tmpRm >> 16;\n local product1 = sext(tmpLRn) * sext(tmpLRm);\n local product2 = sext(tmpURn:2) * sext(tmpURm:2);\n local tmpprod = product1 + product2;\n Q = scarry(smRa, tmpprod) || Q; #Q is sticky \n smRd = smRa + tmpprod;\n}\n\n:smladx^COND smRd, smRn, smRm, smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=3 & smRd & smRn & smRm & smRa \n{\n build COND;\n local tmpRn = smRn;\n local tmpRm = smRm;\n local tmpLRn = tmpRn:2;\n local tmpURn = tmpRn >> 16;\n local tmpLRm = tmpRm:2;\n local tmpURm = tmpRm >> 16;\n local product1 = sext(tmpLRn) * sext(tmpURm:2);\n local product2 = sext(tmpURn:2) * sext(tmpLRm);\n local tmpprod = product1 + product2;\n Q = scarry(smRa, tmpprod) || Q; #Q is sticky\n smRd = smRa + tmpprod;\n}\n\n@endif # VERSION_6\n\n:smlal^COND^SBIT_ZN RdLo,RdHi,smRn,smRm \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=7 & SBIT_ZN & RdLo & RdHi & smRn & c0407=9 & smRm\n{\n build COND;\n tmp:8 = (zext(RdHi) << 32) | zext(RdLo);\n rs64:8 = sext(smRm);\n rm64:8 = sext(smRn);\n tmp = rs64 * rm64 + tmp;\n resultflags(tmp);\n RdLo = tmp(0);\n RdHi = tmp(4);\n build SBIT_ZN;\n}\n\n@if defined(VERSION_5E)\n\n:smlal^XBIT^YBIT^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x14 & RdLo & RdHi & smRm & c0707=1 & XBIT & YBIT & c0404=0 & smRn\n{\n\tbuild COND;\n\tlocal prod:8 = sext(XBIT) * sext(YBIT);\n\tlocal result:8 = (zext(RdHi) << 32) | zext(RdLo);\n\tresult = result + prod;\n\tRdLo = result(0);\n\tRdHi = result(4);\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:smlald^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdLo & RdHi & c0607=0 & c0405=1 & smRn & smRm\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n\tlocal tmpRm = smRm;\n\tprod1:8 = sext(tmpRn:2) * sext(tmpRm:2);\n\trmHi:2 = tmpRm(2);\n\trnHi:2 = tmpRn(2);\n\tprod2:8 = sext(rmHi) * sext(rnHi);\n\tresult:8 = zext(RdLo) + (zext(RdHi) << 32) + prod1 + prod2;\n\tRdLo = result:4;\n\tRdHi = result(4);\n}\n\n:smlaldx^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdLo & RdHi & c0607=0 & c0405=3 & smRn & smRm\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n\tlocal tmpRm = smRm;\n\trmHi:2 = tmpRm(2);\n\trnHi:2 = tmpRn(2);\n\tprod1:8 = sext(tmpRn:2) * sext(rmHi);\n\tprod2:8 = sext(rnHi) * sext(tmpRm:2);\n\tresult:8 = zext(RdLo) + (zext(RdHi) << 32) + prod1 + prod2;\n\tRdLo = result:4;\n\tRdHi = result(4);\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:smlaw^YBIT^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x12 & smRd & smRn & smRm & c0707=1 & YBIT & x=0 & c0404=0 & smRa\n{\n\tbuild COND;\n\tlocal tmp64:6 = sext(smRn) * sext(YBIT);\n\tlocal tmp32:4 = tmp64(2);\n\tQ = scarry(tmp32, smRa) || Q; #Q flag is sticky\n\tsmRd = tmp32 + smRa;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:smlsd^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & smRn & c0607=1 & x=0 & c0404=1 & smRm & smRa\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n\tlocal tmpRm = smRm;\n\tprod1:4 = sext(tmpRn:2) * sext(tmpRm:2);\n\trnHi:2 = tmpRn(2);\n\trmHi:2 = tmpRm(2);\n\tprod2:4 = sext(rnHi) * sext(rmHi);\n\tdiff:4 = prod1 - prod2;\n\tQ = scarry(diff, smRa) || Q; #Q is sticky\n\tsmRd = smRa + diff;\t\n}\n\n:smlsdx^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & smRn & c0607=1 & x=1 & c0404=1 & smRm & smRa\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n\tlocal tmpRm = smRm;\n\trnHi:2 = tmpRn(2);\n\trmHi:2 = tmpRm(2);\n\tprod1:4 = sext(tmpRn:2) * sext(rmHi);\n\tprod2:4 = sext(rnHi) * sext(tmpRm:2);\n\tdiff:4 = prod1 - prod2;\n\tQ = scarry(diff, smRa) || Q; #Q is sticky\n\tsmRd = smRa + diff;\t\n}\n\n:smlsld^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdHi & RdLo & smRm & c0607=1 & x=0 & c0404=1 & smRn\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n\tlocal tmpRm = smRm;\n\tprod1:8 = sext(tmpRn:2) * sext(tmpRm:2);\n\trnHi:2 = tmpRn(2);\n\trmHi:2 = tmpRm(2);\n\tprod2:8 = sext(rnHi) * sext(rmHi);\n\tresult:8 = zext(RdLo) + (zext(RdHi) << 32) + (prod1 - prod2);\n\tRdLo = result:4;\n\tRdHi = result(4);\n}\n\n:smlsldx^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdHi & RdLo & smRm & c0607=1 & x=1 & c0404=1 & smRn\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n\tlocal tmpRm = smRm;\n\trnHi:2 = tmpRn(2);\n\trmHi:2 = tmpRm(2);\n\tprod1:8 = sext(tmpRn:2) * sext(rmHi);\n\tprod2:8 = sext(rnHi) * sext(tmpRm:2);\n\tresult:8 = zext(RdLo) + (zext(RdHi) << 32) + (prod1 - prod2);\n\tRdLo = result:4;\n\tRdHi = result(4);\n}\n\n:smmla^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=0 & r=0 & c0404=1 & smRa\n{\n\tbuild COND;\n\tval:8 = sext(smRn) * sext(smRm);\n\tval = (zext(smRa) << 32) + val;\n\tsmRd = val(4);\n}\n\n:smmlar^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=0 & r=1 & c0404=1 & smRa\n{\n\tbuild COND;\n\tval:8 = sext(smRn) * sext(smRm);\n\tval = (zext(smRa) << 32) + val + 0x80000000;\n\tsmRd = val(4);\n}\n\n:smmls^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=3 & r=0 & c0404=1 & smRa\n{\n\tbuild COND;\n\tval:8 = sext(smRn) * sext(smRm);\n\tval = (zext(smRa) << 32) - val;\n\tsmRd = val(4);\n}\n\n:smmlsr^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=3 & r=1 & c0404=1 & smRa\n{\n\tbuild COND;\n\tval:8 = sext(smRn) * sext(smRm);\n\tval = (zext(smRa) << 32) - val + 0x80000000;\n\tsmRd = val(4);\n}\n\n:smmul^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & c1215=15 & smRn & c0607=0 & r=0 & c0404=1 & smRm\n{\n\tbuild COND;\n\tval:8 = sext(smRn) * sext(smRm);\n\tsmRd = val(4);\n}\n\n:smmulr^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & c1215=15 & smRn & c0607=0 & r=1 & c0404=1 & smRm\n{\n\tbuild COND;\n\tval:8 = (sext(smRn) * sext(smRm)) + 0x080000000;\n\tsmRd = val(4);\n}\n\n:smuad^COND smRd, smRn, smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=1 & smRd & c1619=15 & smRn & smRm\n{\n build COND;\n local tmpRm = smRm;\n local tmpRn = smRn;\n local tmpLRm = tmpRm:2;\n local tmpURm = tmpRm >> 16;\n local tmpLRn = tmpRn:2;\n local tmpURn = tmpRn >> 16;\n local product1 = sext(tmpLRm) * sext(tmpLRn);\n local product2 = sext(tmpURm:2) * sext(tmpURn:2);\n local tmpprod = product1 + product2;\n Q = scarry(product1, product2);\n smRd = tmpprod;\n}\n\n:smuadx^COND smRd, smRn, smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=3 & smRd & c1619=15 & smRn & smRm\n{\n build COND;\n local tmpRm = smRm;\n local tmpRn = smRn;\n local tmpLRm = tmpRm:2;\n local tmpURm = tmpRm >> 16;\n local tmpLRn = tmpRn:2;\n local tmpURn = tmpRn >> 16;\n local product1 = sext(tmpLRm) * sext(tmpURn:2);\n local product2 = sext(tmpURm:2) * sext(tmpLRn);\n local tmpprod = product1 + product2;\n Q = scarry(product1, product2);\n smRd = tmpprod;\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_5E)\n\n:smul^XBIT^YBIT^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x16 & smRd & c1215=0 & smRm & c0707=1 & XBIT & YBIT & c0404=0 & smRn\n{\n\tbuild COND;\n\ttmp:8 = sext(XBIT) * sext(YBIT);\n\tsmRd = tmp:4;\n}\n\n@endif # VERSION_5E\n\n:smull^COND^SBIT_ZN RdLo,RdHi,smRn,smRm \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=6 & SBIT_ZN & RdHi & RdLo & smRn & c0407=9 & smRm\n{\n build COND;\n rn64:8 = sext(smRn);\n rm64:8 = sext(smRm);\n local tmp = rn64 * rm64;\n resultflags(tmp);\n RdLo = tmp(0);\n RdHi = tmp(4);\n build SBIT_ZN;\n}\n\n@if defined(VERSION_5E)\n\n:smulw^YBIT^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x12 & smRd & c1215=0 & smRn & c0707=1 & YBIT & x=1 & c0404=0 & smRm\n{\n\tbuild COND;\n\ttmp:6 = sext(smRn) * sext(YBIT);\n\ttmp = tmp >> 16;\n\tsmRd = tmp:4;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:smusd^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & c1215=15 & smRm & c0607=1 & x=0 & c0404=1 & smRn\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n local tmpRm = smRm;\n\trmHi:2 = tmpRm(2);\n\tprod1:4 = sext(tmpRn:2) * sext(tmpRm:2);\n\trnHi:2 = tmpRn(2);\n\tprod2:4 = sext(rnHi) * sext(rmHi);\n\tsmRd = prod1 - prod2;\n}\n\n:smusdx^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & c1215=15 & smRm & c0607=1 & x=1 & c0404=1 & smRn\n{\n\tbuild COND;\n\tlocal tmpRn = smRn;\n local tmpRm = smRm;\n\trmHi:2 = tmpRm(2);\n\trnHi:2 = tmpRn(2);\n\tprod1:4 = sext(tmpRn:2) * sext(rmHi);\n\tprod2:4 = sext(rnHi) * sext(tmpRm:2);\n\tsmRd = prod1 - prod2;\n}\n\n\n:ssat^COND Rd, sSatImm5, shift4 is $(AMODE) & ARMcond=1 & COND & c2127=0x35 & c0405=1 & sSatImm5 & Rd & shift4 \n{\n build COND; \n build shift4;\n tmp:4 = SignedSaturate(shift4, sSatImm5);\n Q = SignedDoesSaturate(shift4, sSatImm5);\n Rd = tmp;\n}\n\n:ssat16^COND Rd, sSatImm4, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x6a & c0811=15 & c0407=0x3 & sSatImm4 & Rd & Rm\n{\n build COND;\n build sSatImm4;\n local tmpl = Rm & 0xffff;\n tmpl = SignedSaturate(tmpl, sSatImm4);\n local tmpu = Rm >> 16;\n tmpu = SignedSaturate(tmpu, sSatImm4);\n Q = SignedDoesSaturate(tmpl,sSatImm4) | SignedDoesSaturate(tmpu,sSatImm4);\n Rd = ((tmpu & 0xffff) << 16) | (tmpl & 0xffff);\n}\n\n# ssubaddx\n:ssax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=5 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n local diff = sext(uRn:2) - sext(lRm:2);\n GE3 = diff s>= 0;\n GE4 = diff s>= 0;\n local sum = sext(lRn:2) + sext(uRm:2);\n GE1 = sum s>= 0;\n GE2 = sum s>= 0;\n Rd = ((diff & 0xffff) << 16) | (sum & 0xffff);\n}\n\n:ssub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=7 & Rn & Rd & Rm\n{\n build COND;\n local lRn = Rn & 0xffff;\n local lRm = Rm & 0xffff;\n local uRn = (Rn >> 16) & 0xffff;\n local uRm = (Rm >> 16) & 0xffff;\n local diffl = sext(lRn:2) - sext(lRm:2);\n GE1 = diffl s>= 0;\n GE2 = diffl s>= 0;\n local diffu = sext(uRn:2) - sext(uRm:2); \n GE3 = diffu s>= 0;\n GE4 = diffu s>= 0;\n Rd = ((diffu & 0xffff) << 16) | (diffl & 0xffff);\n}\n\n:ssub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=15 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn & 0xff;\n local tmpRm = Rm & 0xff;\n local diff1 = sext(tmpRn:1) - sext(tmpRm:1);\n GE1 = diff1 s>= 0;\n tmpRn = (Rn >> 8) & 0xff;\n tmpRm = (Rm >> 8) & 0xff;\n local diff2 = sext(tmpRn:1) - sext(tmpRm:1);\n GE2 = diff2 s>= 0;\n tmpRn = (Rn >> 16) & 0xff;\n tmpRm = (Rm >> 16) & 0xff;\n local diff3 = sext(tmpRn:1) - sext(tmpRm:1);\n GE3 = diff3 s>= 0;\n tmpRn = (Rn >> 24) & 0xff;\n tmpRm = (Rm >> 24) & 0xff;\n local diff4 = sext(tmpRn:1) - sext(tmpRm:1);\n GE4 = diff4 s>= 0;\n Rd = ((diff4 & 0xff) << 24) | ((diff3 & 0xff) << 16) | ((diff2 & 0xff) << 8) | (diff1 & 0xff);\n}\n\n@endif # VERSION_6\n\n:stc^COND cpn,CRd,addrmode5 \tis $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=0\n{\n build COND;\n build addrmode5;\n t_cpn:4 = cpn;\n coprocessor_store(t_cpn,CRd,addrmode5);\n}\n\n:stcl^COND cpn,CRd,addrmode5 is $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=0\n{\n build COND;\n build addrmode5;\n t_cpn:4 = cpn;\n coprocessor_storelong(t_cpn,CRd,addrmode5);\n}\n\n:stm^mdir^COND reglist \t\tis $(AMODE) & ARMcond=1 & COND & c2527=4 & mdir & L20=0 & reglist\n{\n build COND;\n build reglist;\n}\n\n#:str^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n#{\n# build COND;\n# build addrmode2;\n# tmp=addrmode2&0xfffffffc;\n# *tmp = Rd;\n#}\n\n# The following form of str assumes alignment checking is on\n:str^COND Rd,addrmode2 \t\tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n *addrmode2 = Rd;\n}\n\n:strb^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=1 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n local tmpRd = Rd;\n *addrmode2 = tmpRd:1;\n}\n\n:strbt^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & P24=0 & B22=1 & W21=1 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n local tmpRd = Rd;\n *addrmode2 = tmpRd:1;\n}\n\n:strh^COND Rd,addrmode3 \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=0 & c0407=11 & Rd & addrmode3\n{\n build COND;\n build addrmode3;\n local tmpRd = Rd;\n *addrmode3 = tmpRd:2;\n}\n\n@if defined(VERSION_5E)\n\n:strd^COND Rd,Rd2,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & c0407=0xf & L20=0 & Rd & Rd2 & addrmode3\n{\n build COND;\n build addrmode3;\n local addr = addrmode3;\n *(addr) = Rd;\n addr = addr + 4;\n *(addr) = Rd2;\n}\n\n@endif # VERSION_5E\n\n@if defined(VERSION_6)\n\n:strex^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x18 & c0411=0xf9 & Rn & Rd & Rm\n{\n\tbuild COND;\n\tlocal tmp = Rn;\n\tlocal tmpRm = Rm;\n\taccess:1 = hasExclusiveAccess(tmp);\n\tRd = 1;\n\tif (!access) goto inst_next;\n\tRd = 0;\n\t*tmp = tmpRm;\n}\n\n@endif # VERSION_6\n\n@if defined(VERSION_6K)\n\n:strexb^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1c & c0411=0xf9 & Rn & Rd & Rm\n{\n\tbuild COND;\n\tlocal tmp = Rn;\n\tlocal tmpRm = Rm;\n\taccess:1 = hasExclusiveAccess(tmp);\n\tRd = 1;\n\tif (!access) goto inst_next;\n\tRd = 0;\n\t*tmp = tmpRm:1;\n}\n\n:strexd^COND Rd,Rm,Rm2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xf9 & c0003 & Rm & Rm2\n{\n\tbuild COND;\n\tlocal addr = Rn;\n\tlocal tmpRm = Rm;\n\tlocal tmpRm2 = Rm2;\n \taccess:1 = hasExclusiveAccess(addr);\n \tRd = 1;\n \tif (!access) goto inst_next;\n \tRd = 0;\n\t*(addr) = tmpRm;\n\taddr = addr + 4;\n\t*(addr) = tmpRm2;\n}\n\n:strexh^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1e & c0411=0xf9 & Rn & Rd & Rm\n{\n\tbuild COND;\n\tlocal tmp = Rn;\n\tlocal tmpRm = Rm;\n \taccess:1 = hasExclusiveAccess(tmp);\n \tRd = 1;\n \tif (!access) goto inst_next;\n \tRd = 0;\n\t*tmp = tmpRm:2;\n}\n\n:strht^COND Rd,addrmode3\t\tis $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=0 & c0407=11 & Rd & addrmode3\t{\n build COND;\n *:2 addrmode3 = Rd;\n}\n\n@endif # VERSION_6K\n\n#:strt^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & P24=0 & W21=1 & Rd & addrmode2\n#{\n# build COND;\n# build addrmode2;\n# tmp=addrmode2&0xfffffffc;\n# *tmp = Rd;\n#}\n\n# The following form of str assumes alignment checking is on\n:strt^COND Rd,addrmode2 \tis $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & P24=0 & W21=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2\n{\n build COND;\n build addrmode2;\n *addrmode2 = Rd;\n}\n\n:sub^COND^SBIT_CZNO Rd,rn,shift1\tis $(AMODE) & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n subflags(rn,shift1);\n Rd = rn-shift1;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:sub^COND^SBIT_CZNO Rd,rn,shift2\tis $(AMODE) & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n subflags(rn,shift2);\n Rd = rn-shift2;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:sub^COND^SBIT_CZNO Rd,rn,shift3\tis $(AMODE) & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n subflags(rn,shift3);\n Rd = rn-shift3;\n resultflags(Rd);\n build SBIT_CZNO;\n}\n\n:sub^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n subflags(rn,shift1);\n dest:4 = rn-shift1;\n resultflags(dest);\n build SBIT_CZNO;\n cpsr = spsr;\n SetThumbMode( ((cpsr >> 5) & 1) != 0 );\n pc = dest;\n goto [pc];\n}\n\n:sub^COND^SBIT_CZNO pc,rn,shift1 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & Rn=14 & I25=1 & immed=0 & rotate=0 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n subflags(rn,shift1);\n dest:4 = rn-shift1;\n resultflags(dest);\n build SBIT_CZNO;\n cpsr = spsr;\n ALUWritePC(dest);\n return [pc];\n}\n\n:sub^COND^SBIT_CZNO pc,rn,shift2 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n subflags(rn,shift2);\n dest:4 = rn-shift2;\n resultflags(dest);\n build SBIT_CZNO;\n cpsr = spsr;\n SetThumbMode( ((cpsr >> 5) & 1) != 0 );\n pc = dest;\n goto [pc];\n}\n\n:sub^COND^SBIT_CZNO pc,rn,shift3 \tis $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n subflags(rn,shift3);\n dest:4 = rn-shift3;\n resultflags(dest);\n build SBIT_CZNO;\n cpsr = spsr;\n SetThumbMode( ((cpsr >> 5) & 1) != 0 );\n pc = dest;\n goto [pc];\n}\n\n:swi^COND immed24 \t\tis $(AMODE) & ARMcond=1 & COND & c2427=15 & immed24\n{\n build COND;\n tmp:4 = immed24;\n software_interrupt(tmp);\n}\n\n#:swp^COND Rd,Rm,Rn \t\tis $(AMODE) & ARMcond=1 & COND & c2027=16 & Rn & Rd & c0811=0 & c0407=9 & Rm\n#{\n# build COND;\n# tmp = Rn & 0xfffffffc;\n# tmp2 = (Rn&3)<<3;\n# val:4 = *tmp;\n# val=(val>>tmp2) | (val << (32-tmp2));\n# *tmp = Rm;\n# Rd = val;\n#}\n\n# Assuming alignment checking is enabled\n:swp^COND Rd,Rm,Rn \t\tis $(AMODE) & ARMcond=1 & COND & c2027=16 & Rn & Rd & c0811=0 & c0407=9 & Rm\n{\n build COND;\n val:4 = *Rn;\n *Rn = Rm;\n Rd = val;\n}\n\n:swpb^COND Rd,Rm,Rn \t\tis $(AMODE) & ARMcond=1 & COND & c2027=20 & Rn & Rd & c0811=0 & c0407=9 & Rm\n{\n build COND;\n local tmp = *:1 Rn;\n local tmpRm = Rm;\n *Rn = tmpRm:1;\n Rd = zext(tmp);\n}\n\n@if defined(VERSION_6)\n\n:sxtab^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=2 & c0407=7 & Rd & Rn & ror1\n{\n build COND;\n build ror1;\n Rd = Rn + sext(ror1:1);\n}\n\n:sxtab16^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & c0407=7 & Rn & Rd & ror1\n{\n build COND;\n build ror1;\n b:1 = ror1:1;\n lo:2 = Rn:2 + sext(b);\n b = ror1(2);\n hi:2 = Rn(2) + sext(b);\n Rd = (zext(hi) << 16) + zext(lo);\n}\n\n:sxtah^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=7 & Rd & Rn & ror1\n{\n build COND;\n build ror1;\n Rd = Rn + sext(ror1:2);\n}\n\n:sxtb^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=2 & c0407=7 & Rd & c1619=15 & ror1\n{\n build COND;\n build ror1;\n Rd = sext(ror1:1);\n}\n\n:sxtb16^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=0 & c0407=7 & Rd & c1619=15 & ror1\n{\n build COND;\n build ror1;\n local tmp1:1 = ror1:1;\n local low:2 = sext(tmp1);\n local tmp2:1 = ror1(2);\n local high:2 = sext(tmp2);\n Rd = (zext(high) << 16) | zext(low);\n}\n\n:sxth^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=7 & Rd & c1619=15 & ror1\n{\n build COND;\n build ror1;\n Rd = sext(ror1:2);\n}\n\n@endif # VERSION_6\n\n:teq^COND rn,shift1 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=0 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n local tmp = rn^shift1;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:teq^COND rn,shift2 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=0 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n local tmp = rn^shift2;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:teq^COND rn,shift3 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=0 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n local tmp = rn^shift3;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:teq^COND^\"p\" rn,shift1 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=15 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n local tmp = rn^shift1;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:teq^COND^\"p\" rn,shift2 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=15 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n local tmp = rn^shift2;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:teq^COND^\"p\" rn,shift3 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=15 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n local tmp = rn^shift3;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n\n:tst^COND rn,shift1 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=17 & rn & c1215=0 & c2627=0 & shift1\n{\n build COND;\n build rn;\n build shift1;\n local tmp = rn & shift1;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:tst^COND rn,shift2 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=17 & rn & c1215=0 & c2627=0 & shift2\n{\n build COND;\n build rn;\n build shift2;\n local tmp = rn & shift2;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n:tst^COND rn,shift3 \t\tis $(AMODE) & ARMcond=1 & COND & c2024=17 & rn & c1215=0 & c2627=0 & shift3\n{\n build COND;\n build rn;\n build shift3;\n local tmp = rn & shift3;\n logicflags();\n resultflags(tmp);\n affectflags();\n}\n\n@if defined(VERSION_6)\n\n:uadd16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=1 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm:2;\n local tcarry = carry(tmp1,tmp2);\n GE1 = tcarry;\n GE2 = tcarry;\n local tmpLow = tmp1 + tmp2;\n tmp1 = rn(2);\n tmp2 = rm(2);\n tcarry = carry(tmp1,tmp2);\n GE3 = tcarry;\n GE4 = tcarry;\n local tmpHigh = tmp1 + tmp2;\n Rd = zext(tmpHigh) << 16 | zext(tmpLow);\n}\n\n:uadd8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=9 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:1 = tmpRn:1;\n tmp2:1 = tmpRm:1;\n GE1 = carry(tmp1,tmp2);\n b1:1 = tmp1 + tmp2;\n tmp1 = rn(1);\n tmp2 = rm(1);\n GE2 = carry(tmp1,tmp2);\n b2:1 = tmp1 + tmp2;\n tmp1 = rn(2);\n tmp2 = rm(2);\n GE3 = carry(tmp1,tmp2);\n b3:1 = tmp1 + tmp2;\n tmp1 = rn(3);\n tmp2 = rm(3);\n GE4 = carry(tmp1,tmp2);\n b4:1 = tmp1 + tmp2;\n Rd = (zext(b4) << 24) | (zext(b3) << 16) | (zext(b2) << 8) | zext(b1);\n}\n\n# uaddsubx\n:uasx^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=3 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm(2);\n local tmpLow:4 = zext(tmp1) - zext(tmp2);\n GE1 = tmpLow s>= 0;\n GE2 = tmpLow s>= 0;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm:2;\n tcarry:1 = carry(tmp1,tmp2);\n GE3 = tcarry;\n GE4 = tcarry;\n local tmpHigh = tmp1 + tmp2;\n Rd[0,16] = tmpLow[0,16];\n Rd[16,16] = tmpHigh;\n }\n\n@endif # VERSION_6\n\n@if defined(VERSION_6T2)\n\n:ubfx^COND Rd,Rm,lsbImm,widthMinus1\tis $(AMODE) & ARMcond=1 & COND & c2127=0x3f & widthMinus1 & Rd & lsbImm & c0406=5 & Rm\n{\n\tbuild COND;\n\tbuild lsbImm;\n\tbuild widthMinus1;\n\tshift:4 = 31 - (lsbImm + widthMinus1);\n\tRd = Rm << shift;\n\tshift = 31 - widthMinus1;\n\tRd = Rd >> shift;\n}\n\n@endif # VERSION_6T2\n\n@if defined(VERSION_7)\n\n:udiv^COND RdHi,RnLo,RmHi is $(AMODE) & ARMcond=1 & COND & c2027=0x73 & RdHi & c1215=0xf & RmHi & c0407=0x1 & RnLo\n{\n build COND;\n result:8 = zext(RnLo) / zext(RmHi);\n RdHi = result(0);\n}\n\n@endif # VERSION_7\n\n@if defined(VERSION_6)\n\n:uhadd16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=1 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:4 = tmpRn & 0xffff;\n tmp2:4 = tmpRm & 0xffff;\n local tmpLow = tmp1 + tmp2;\n local tmpHigh = (tmpRn >> 16) + (tmpRm >> 16);\n Rd[0,16] = tmpLow[1,16];\n Rd[16,16] = tmpHigh[1,16];\n}\n\n:uhadd8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=9 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:1 = tmpRn:1;\n tmp2:1 = tmpRm:1;\n b1:2 = (zext(tmp1) + zext(tmp2)) >> 1;\n tmp1 = tmpRn(1);\n tmp2 = tmpRm(1);\n b2:2 = (zext(tmp1) + zext(tmp2)) >> 1;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm(2);\n b3:2 = (zext(tmp1) + zext(tmp2)) >> 1;\n tmp1 = tmpRn(3);\n tmp2 = tmpRm(3);\n b4:2 = (zext(tmp1) + zext(tmp2)) >> 1;\n Rd = (zext(b4) << 24) | (zext(b3) << 16) | (zext(b2) << 8) | zext(b1);\n}\n\n# uhaddsubx\n:uhasx^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=3 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm(2);\n tmpLow:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm:2;\n tmpHigh:4 = (zext(tmp1) + zext(tmp2)) >> 1;\n Rd = (tmpHigh << 16) | tmpLow;\n}\n\n# uhsubaddx\n:uhsax^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=5 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm(2);\n tmpLow:4 = (zext(tmp1) + zext(tmp2)) >> 1;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm:2;\n tmpHigh:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff;\n Rd = (tmpHigh << 16) | tmpLow;\n}\n\n:uhsub16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=7 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm:2;\n tmpLow:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff;\n tmp1 = rn(2);\n tmp2 = rm(2);\n tmpHigh:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff;\n Rd = (tmpHigh << 16) | tmpLow;\n}\n\n:uhsub8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=15 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:1 = tmpRn:1;\n tmp2:1 = tmpRm:1;\n b1:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff;\n tmp1 = tmpRn(1);\n tmp2 = tmpRm(1);\n b2:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm(2);\n b3:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff;\n tmp1 = tmpRn(3);\n tmp2 = tmpRm(3);\n b4:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff;\n Rd = (b4 << 24) | (b3 << 16) | (b2 << 8) | b1;\n}\n\n:umaal^COND RdLo,RdHi,Rm,Rs is $(AMODE) & ARMcond=1 & COND & c2027=0x04 & RdHi & RdLo & Rs & c0407=9 & Rm\n{\n build COND;\n result:8 = (zext(Rm) * zext(Rs)) + zext(RdLo) + zext(RdHi);\n RdLo = result:4;\n RdHi = result(4);\n}\n\n@endif # VERSION_6\n\n:umlal^COND^SBIT_ZN Rd,Rn,rm,rs \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=5 & SBIT_ZN & Rn & Rd & rs & c0407=9 & rm\n{\n build COND;\n build rm;\n build rs;\n tmp:8 = (zext(Rn) << 32) | zext(Rd);\n rs64:8 = zext(rs);\n rm64:8 = zext(rm);\n tmp = rs64 * rm64 + tmp;\n resultflags(tmp);\n Rd = tmp(0);\n Rn = tmp(4);\n build SBIT_ZN;\n}\n\n:umull^COND^SBIT_ZN Rd,Rn,rm,rs \tis $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=4 & SBIT_ZN & Rn & Rd & rs & c0407=9 & rm\n{\n build COND;\n build rm;\n build rs;\n rs64:8 = zext(rs);\n rm64:8 = zext(rm);\n local tmp = rs64 * rm64;\n resultflags(tmp);\n Rd = tmp(0);\n Rn = tmp(4);\n build SBIT_ZN;\n}\n\n@if defined(VERSION_6)\n\n:uqadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=1 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n tmp2Rn:2 = tmpRn:2;\n tmp2Rm:2 = tmpRm:2;\n sum1:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2);\n tmp2Rn = tmpRn(2);\n tmp2Rm = tmpRm(2);\n sum2:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n:uqadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=9 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n tmp1Rn:1 = tmpRn:1;\n tmp1Rm:1 = tmpRm:1;\n sum1:1 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2);\n tmp1Rn = tmpRn(1);\n tmp1Rm = tmpRm(1);\n sum2:2 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2);\n tmp1Rn = tmpRn(2);\n tmp1Rm = tmpRm(2);\n sum3:2 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2);\n tmp1Rn = tmpRn(3);\n tmp1Rm = tmpRm(3);\n sum4:2 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2);\n Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n# uqaddsubx\n:uqasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=3 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n tmp2Rn:2 = tmpRn:2;\n tmp2Rm:2 = tmpRm(2);\n sum1:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2);\n tmp2Rn = tmpRn(2);\n tmp2Rm = tmpRm:2;\n sum2:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n# uqsubaddx\n:uqsax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=5 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n tmp2Rn:2 = tmpRn:2;\n tmp2Rm:2 = tmpRm(2);\n sum1:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2);\n tmp2Rn = tmpRn(2);\n tmp2Rm = tmpRm:2;\n sum2:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n:uqsub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=7 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n tmp2Rn:2 = tmpRn:2;\n tmp2Rm:2 = tmpRm:2;\n sum1:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2);\n tmp2Rn = tmpRn(2);\n tmp2Rm = tmpRm(2);\n sum2:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2);\n Rd = (zext(sum2) << 16) | zext(sum1);\n}\n\n:uqsub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=15 & Rn & Rd & Rm\n{\n build COND;\n local tmpRn = Rn;\n local tmpRm = Rm;\n tmp1Rn:1 = tmpRn:1;\n tmp1Rm:1 = tmpRm:1;\n sum1:1 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2);\n tmp1Rn = tmpRn(1);\n tmp1Rm = tmpRm(1);\n sum2:2 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2);\n tmp1Rn = tmpRn(2);\n tmp1Rm = tmpRm(2);\n sum3:2 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2);\n tmp1Rn = tmpRn(3);\n tmp1Rm = tmpRm(3);\n sum4:2 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2);\n Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n:usad8^COND Rd, Rm, Rs is $(AMODE) & ARMcond=1 & COND & c2027=0x78 & c1215=15 & c0407=1 & Rd & Rm & Rs\n{\n build COND;\n local tmpRs = Rs;\n local tmpRm = Rm;\n tmp1Rs:1 = tmpRs:1;\n tmp1Rm:1 = tmpRm:1;\n sum1:1 = Absolute(tmp1Rs - tmp1Rm);\n tmp1Rs = tmpRs(1);\n tmp1Rm = tmpRm(1);\n sum2:1 = Absolute(tmp1Rs - tmp1Rm);\n tmp1Rs = tmpRs(2);\n tmp1Rm = tmpRm(2);\n sum3:1 = Absolute(tmp1Rs - tmp1Rm);\n tmp1Rs = tmpRs(3);\n tmp1Rm = tmpRm(3);\n sum4:1 = Absolute(tmp1Rs - tmp1Rm);\n Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1);\n}\n\n:usada8^COND Rd, Rm, Rs, Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x78 & c0407=1 & Rd & Rn& Rm & Rs\n{\n build COND;\n local tmpRs = Rs;\n local tmpRm = Rm;\n tmp1Rs:1 = tmpRs:1;\n tmp1Rm:1 = tmpRm:1;\n sum1:1 = Absolute(tmp1Rs - tmp1Rm);\n tmp1Rs = tmpRs(1);\n tmp1Rm = tmpRm(1);\n sum2:1 = Absolute(tmp1Rs - tmp1Rm);\n tmp1Rs = tmpRs(2);\n tmp1Rm = tmpRm(2);\n sum3:1 = Absolute(tmp1Rs - tmp1Rm);\n tmp1Rs = tmpRs(3);\n tmp1Rm = tmpRm(3);\n sum4:1 = Absolute(tmp1Rs - tmp1Rm);\n Rd = Rn + ((zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1));\n}\n\n:usat^COND Rd, uSatImm5, shift4 is $(AMODE) & ARMcond=1 & COND & c2127=0x37 & c0405=0x1 & uSatImm5 & Rd & shift4\n{\n build COND;\n build uSatImm5;\n build shift4;\n tmp:4 = UnsignedSaturate(shift4, uSatImm5);\n Q = UnsignedDoesSaturate(shift4, uSatImm5);\n Rd = tmp;\n}\n\n:usat16^COND Rd, uSatImm4, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x6e & c0811=15 & c0407=0x3 & uSatImm4 & Rd & Rm\n{\n build COND;\n build uSatImm4;\n local tmpl = Rm & 0xffff;\n tmpl = UnsignedSaturate(tmpl, uSatImm4);\n local tmpu = Rm >> 16;\n tmpu = UnsignedSaturate(tmpu, uSatImm4);\n Q = UnsignedDoesSaturate(tmpl,uSatImm4) | UnsignedDoesSaturate(tmpu,uSatImm4);\n Rd = ((tmpu & 0xffff) << 16) | (tmpl & 0xffff);\n}\n\n# usubaddx\n:usax^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=5 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm(2);\n local tcarry = carry(tmp2,tmp1);\n GE1 = tcarry;\n GE2 = tcarry;\n local tmpLow = tmp1 + tmp2;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm:2;\n tcarry = tmp2 <= tmp1;\n GE3 = tcarry;\n GE4 = tcarry;\n local tmpHigh = tmp1 - tmp2;\n Rd = zext(tmpHigh) << 16 | zext(tmpLow);\n}\n\n:usub16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=7 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:2 = tmpRn:2;\n tmp2:2 = tmpRm:2;\n local tcarry = tmp2 <= tmp1;\n GE1 = tcarry;\n GE2 = tcarry;\n local tmpLow = tmp1 - tmp2;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm(2);\n tcarry = tmp2 <= tmp1;\n GE3 = tcarry;\n GE4 = tcarry;\n local tmpHigh = tmp1 - tmp2;\n Rd = zext(tmpHigh) << 16 | zext(tmpLow);\n}\n\n:usub8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=15 & Rd & rn & rm\n{\n build COND;\n build rn;\n build rm;\n local tmpRn = rn;\n local tmpRm = rm;\n tmp1:1 = tmpRn:1;\n tmp2:1 = tmpRm:1;\n GE1 = tmp2 <= tmp1;\n b1:1 = tmp1 - tmp2;\n tmp1 = tmpRn(1);\n tmp2 = tmpRm(1);\n GE2 = tmp2 <= tmp1;\n b2:1 = tmp1 - tmp2;\n tmp1 = tmpRn(2);\n tmp2 = tmpRm(2);\n GE3 = tmp2 <= tmp1;\n b3:1 = tmp1 - tmp2;\n tmp1 = tmpRn(3);\n tmp2 = tmpRm(3);\n GE4 = tmp2 <= tmp1;\n b4:1 = tmp1 - tmp2;\n Rd = (zext(b4) << 24) | (zext(b3) << 16) | (zext(b2) << 8) | zext(b1);\n}\n\n:uxtab^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=6 & c0407=7 & Rd & Rn & ror1\n{\n build COND;\n build ror1;\n Rd = Rn + zext(ror1:1);\n}\n\n:uxtab16^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=4 & c0407=7 & Rd & Rn & ror1\n{\n build COND;\n build ror1;\n local tmp1 = ror1 & 0xff;\n local tmp2 = (ror1 >> 16) & 0xff;\n local tmp1n = (Rn + tmp1) & 0xffff;\n local tmp2n = (Rn >> 16) + tmp2;\n Rd = (tmp2n << 16) | tmp1n;\n}\n\n:uxtah^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=7 & Rd & Rn & ror1\n{\n build COND;\n build ror1;\n Rd = Rn + zext(ror1:2);\n}\n\n:uxtb^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=6 & c0407=7 & Rd & c1619=15 & ror1\n{\n build COND;\n build ror1;\n Rd = ror1 & 0x0ff;\n}\n\n:uxtb16^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=4 & c0407=7 & Rd & c1619=15 & ror1\n{\n build COND;\n build ror1;\n Rd = ror1 & 0x0ff00ff;\n}\n\n:uxth^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=7 & Rd & c1619=15 & ror1\n{\n build COND;\n build ror1;\n Rd = ror1 & 0x0ffff;\n}\n\n@endif # VERSION_6\n\n# :v* Advanced SIMD and VFP instructions - see ARMneon.sinc\n\n@if defined(VERSION_6K)\n\n:wfe^COND\tis $(AMODE) & ARMcond=1 & COND & c0027=0x320f002\n{\n\tbuild COND;\n\tWaitForEvent();\n}\n\n:wfi^COND\tis $(AMODE) & ARMcond=1 & COND & c0027=0x320f003\n{\n\tbuild COND;\n\tWaitForInterrupt();\n}\n\n:yield^COND\tis $(AMODE) & ARMcond=1 & COND & c0027=0x320f001\n{\n\tbuild COND;\n\tHintYield();\n}\n\n@endif # VERSION_6K\n\n## Some special pseudo ops for better distinguishing\n## indirect calls, and returns\n\n#:callx rm\t\tis $(AMODE) & pref=0xe1a0e00f; cond=14 & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm\n#{\n# lr = inst_next + 8;\n# TB=(rm&0x00000001)!=0;\n# tmp=rm&0xfffffffe;\n# call [tmp];\n# TB=0;\n#} # Optional change to THUMB\n \n#:call^COND^SBIT_CZNO shift1 \tis $(AMODE) & pref=0xe1a0e00f; COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift1\n#{\n# lr = inst_next + 8;\n# build COND;\n# build shift1;\n# pc = shift1;\n# resultflags(pc);\n# logicflags();\n# build SBIT_CZNO;\n# call [pc];\n#}\n\n#:call^COND^SBIT_CZNO shift2 \tis $(AMODE) & pref=0xe1a0e00f; COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift2\n#{\n# lr = inst_next + 8;\n# build COND;\n# build shift2;\n# pc = shift2;\n# resultflags(pc);\n# logicflags();\n# build SBIT_CZNO;\n# call [pc];\n#}\n\n#:call^COND^SBIT_CZNO shift3 \tis $(AMODE) & pref=0xe1a0e00f; COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift3\n#{\n# lr = inst_next + 8;\n# build COND;\n# build shift3;\n# pc = shift3;\n# resultflags(pc);\n# logicflags();\n# build SBIT_CZNO;\n# call [pc];\n#}\n\n\n} # End with : ARMcondCk=1\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMneon.dwarf", "content": "\n\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t \n\t\n\t\n\t\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMneon.sinc", "content": "# Advanced SIMD support / NEON\n\n# WARNING NOTE: Be very careful taking a subpiece or truncating a register with :# or (#)\n# The LEBE hybrid language causes endian issues if you do not assign the register to a temp\n# variable and then take a subpiece or truncate.\n#\n\n@define FPSCR_RMODE \"fpscr[22,2]\"\n\n@define TMODE_E \"TMode=1 & thv_c2831=14\" # check for neon instructions in thumb mode\n@define TMODE_F \"TMode=1 & thv_c2831=15\"\n@define TMODE_EorF \"TMode=1 & thv_c2931=7\"\n\n# The RM field is bits 22 and 23 of FPSCR\n@define FPSCR_RMODE \"fpscr[21,2]\"\n\nzero: \"#0\"\t\t\tis c0000 \t\t\t\t{ export 0:8; }\n\n@if defined(SIMD)\n \nattach variables [ thv_Rm ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ];\n\nattach variables [ Qn0 Qd0 Qm0 thv_Qn0 thv_Qd0 thv_Qm0 ] [ q0 _ q1 _ q2 _ q3 _ q4 _ q5 _ q6 _ q7 _ ];\nattach variables [ Qn1 Qd1 Qm1 thv_Qn1 thv_Qd1 thv_Qm1 ] [ q8 _ q9 _ q10 _ q11 _ q12 _ q13 _ q14 _ q15 _ ];\n\nQd: Qd0\t\tis TMode=0 & Qd0 & D22=0\t{ export Qd0; }\nQd: Qd1\t\tis TMode=0 & Qd1 & D22=1\t{ export Qd1; }\nQd: thv_Qd0\tis TMode=1 & thv_Qd0 & thv_D22=0\t{ export thv_Qd0; }\nQd: thv_Qd1\tis TMode=1 & thv_Qd1 & thv_D22=1\t{ export thv_Qd1; }\n\nQn: Qn0\t\tis TMode=0 & Qn0 & N7=0\t{ export Qn0; }\nQn: Qn1\t\tis TMode=0 & Qn1 & N7=1\t{ export Qn1; }\nQn: thv_Qn0\t\tis TMode=1 & thv_Qn0 & thv_N7=0\t{ export thv_Qn0; }\nQn: thv_Qn1\t\tis TMode=1 & thv_Qn1 & thv_N7=1\t{ export thv_Qn1; }\n\nQm: Qm0\t\tis TMode=0 & Qm0 & M5=0\t{ export Qm0; }\nQm: Qm1\t\tis TMode=0 & Qm1 & M5=1\t{ export Qm1; }\nQm: thv_Qm0\t\tis TMode=1 & thv_Qm0 & thv_M5=0\t{ export thv_Qm0; }\nQm: thv_Qm1\t\tis TMode=1 & thv_Qm1 & thv_M5=1\t{ export thv_Qm1; }\n\n@endif # SIMD\n\n@if defined(SIMD) || defined(VFPv3) || defined(VFPv2)\n \nattach variables [ Dm_3 thv_Dm_3 ] [ d0 d1 d2 d3 d4 d5 d6 d7 ];\n\nattach variables [ Dn0 Dd0 Dm0 Dm_4 thv_Dn0 thv_Dd0 thv_Dm0 thv_Dm_4 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];\nattach variables [ thv_Dd_1 Dd_1 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];\nattach variables [ thv_Dd_2 Dd_2 ] [ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ ];\nattach variables [ thv_Dd_3 Dd_3 ] [ d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ ];\nattach variables [ thv_Dd_4 Dd_4 ] [ d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ ];\nattach variables [ thv_Dd_5 Dd_5 ] [ d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ ];\nattach variables [ thv_Dd_6 Dd_6 ] [ d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ ];\nattach variables [ thv_Dd_7 Dd_7 ] [ d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ ];\nattach variables [ thv_Dd_8 Dd_8 ] [ d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_9 Dd_9 ] [ d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_10 Dd_10 ] [ d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_11 Dd_11 ] [ d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_12 Dd_12 ] [ d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_13 Dd_13 ] [ d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_14 Dd_14 ] [ d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_15 Dd_15 ] [ d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];\nattach variables [ thv_Dd_16 Dd_16 ] [ d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];\n \nDd: Dd0\t\tis TMode=0 & Dd0 & D22=0\t{ export Dd0; }\nDn: Dn0\t\tis TMode=0 & Dn0 & N7=0\t{ export Dn0; }\nDm: Dm0\t\tis TMode=0 & Dm0 & M5=0\t{ export Dm0; }\nDd: thv_Dd0\tis TMode=1 & thv_Dd0 & thv_D22=0\t{ export thv_Dd0; }\nDn: thv_Dn0\tis TMode=1 & thv_Dn0 & thv_N7=0\t{ export thv_Dn0; }\nDm: thv_Dm0\tis TMode=1 & thv_Dm0 & thv_M5=0\t{ export thv_Dm0; }\n\nDd2: Dd\t\tis Dd\t\t\t{ export Dd; }\n\n@endif # SIMD || VFPv3 || VFPv2\n\n@if defined(SIMD) || defined(VFPv3)\n\nattach variables [ Dn1 Dd1 Dm1 thv_Dn1 thv_Dd1 thv_Dm1 ] [ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ];\n \nDd: Dd1\t\tis TMode=0 & Dd1 & D22=1 { export Dd1; }\nDn: Dn1\t\tis TMode=0 & Dn1 & N7=1\t{ export Dn1; }\nDm: Dm1\t\tis TMode=0 & Dm1 & M5=1\t{ export Dm1; }\nDd: thv_Dd1\tis TMode=1 & thv_Dd1 & thv_D22=1 { export thv_Dd1; }\nDn: thv_Dn1\tis TMode=1 & thv_Dn1 & thv_N7=1\t{ export thv_Dn1; }\nDm: thv_Dm1\tis TMode=1 & thv_Dm1 & thv_M5=1\t{ export thv_Dm1; }\n\nattach variables [ Sm0_3 thv_Sm0_3 ][s0 s2 s4 s6 s8 s10 s12 s14];\nattach variables [ Sm1_3 thv_Sm1_3][s1 s3 s5 s7 s9 s11 s13 s15];\n\nSm_3: Sm0_3 is TMode=0 & Sm0_3 & M5=0 { export Sm0_3; }\nSm_3: Sm1_3 is TMode=0 & Sm1_3 & M5=1 { export Sm1_3; }\nSm_3: thv_Sm0_3 is TMode=1 & thv_Sm0_3 & M5=0 { export thv_Sm0_3; }\nSm_3: thv_Sm1_3 is TMode=1 & thv_Sm1_3 & M5=1 { export thv_Sm1_3; }\n\n@endif # SIMD || VFPv3\n\n@if defined(VFPv2) || defined(VFPv3)\n\nattach variables [ Sn0 Sd0 Sm0 thv_Sn0 thv_Sd0 thv_Sm0 ] [ s0 s2 s4 s6 s8 s10 s12 s14 s16 s18 s20 s22 s24 s26 s28 s30 ];\nattach variables [ Sn1 Sd1 Sm1 thv_Sn1 thv_Sd1 thv_Sm1 ] [ s1 s3 s5 s7 s9 s11 s13 s15 s17 s19 s21 s23 s25 s27 s29 s31 ];\n\nattach variables [ Sm0next thv_Sm0next ] [ s1 s3 s5 s7 s9 s11 s13 s15 s17 s19 s21 s23 s25 s27 s29 s31 ];\nattach variables [ Sm1next thv_Sm1next ] [ s2 s4 s6 s8 s10 s12 s14 s16 s18 s20 s22 s24 s26 s28 s30 _ ];\n\n# We need to create separate constructors for each register rather than attaching\n# directly to a context variable\n@if defined (VFPv2) || defined(SIMD)\nSreg: s0 is s0 & regNum=0 { export s0; }\nSreg: s1 is s1 & regNum=1 { export s1; }\nSreg: s2 is s2 & regNum=2 { export s2; }\nSreg: s3 is s3 & regNum=3 { export s3; }\nSreg: s4 is s4 & regNum=4 { export s4; }\nSreg: s5 is s5 & regNum=5 { export s5; }\nSreg: s6 is s6 & regNum=6 { export s6; }\nSreg: s7 is s7 & regNum=7 { export s7; }\nSreg: s8 is s8 & regNum=8 { export s8; }\nSreg: s9 is s9 & regNum=9 { export s9; }\nSreg: s10 is s10 & regNum=10 { export s10; }\nSreg: s11 is s11 & regNum=11 { export s11; }\nSreg: s12 is s12 & regNum=12 { export s12; }\nSreg: s13 is s13 & regNum=13 { export s13; }\nSreg: s14 is s14 & regNum=14 { export s14; }\nSreg: s15 is s15 & regNum=15 { export s15; }\nSreg: s16 is s16 & regNum=16 { export s16; }\nSreg: s17 is s17 & regNum=17 { export s17; }\nSreg: s18 is s18 & regNum=18 { export s18; }\nSreg: s19 is s19 & regNum=19 { export s19; }\nSreg: s20 is s20 & regNum=20 { export s20; }\nSreg: s21 is s21 & regNum=21 { export s21; }\nSreg: s22 is s22 & regNum=22 { export s22; }\nSreg: s23 is s23 & regNum=23 { export s23; }\nSreg: s24 is s24 & regNum=24 { export s24; }\nSreg: s25 is s25 & regNum=25 { export s25; }\nSreg: s26 is s26 & regNum=26 { export s26; }\nSreg: s27 is s27 & regNum=27 { export s27; }\nSreg: s28 is s28 & regNum=28 { export s28; }\nSreg: s29 is s29 & regNum=29 { export s29; }\nSreg: s30 is s30 & regNum=30 { export s30; }\nSreg: s31 is s31 & regNum=31 { export s31; }\n\nSreg2: s0 is s0 & reg2Num=0 { export s0; }\nSreg2: s1 is s1 & reg2Num=1 { export s1; }\nSreg2: s2 is s2 & reg2Num=2 { export s2; }\nSreg2: s3 is s3 & reg2Num=3 { export s3; }\nSreg2: s4 is s4 & reg2Num=4 { export s4; }\nSreg2: s5 is s5 & reg2Num=5 { export s5; }\nSreg2: s6 is s6 & reg2Num=6 { export s6; }\nSreg2: s7 is s7 & reg2Num=7 { export s7; }\nSreg2: s8 is s8 & reg2Num=8 { export s8; }\nSreg2: s9 is s9 & reg2Num=9 { export s9; }\nSreg2: s10 is s10 & reg2Num=10 { export s10; }\nSreg2: s11 is s11 & reg2Num=11 { export s11; }\nSreg2: s12 is s12 & reg2Num=12 { export s12; }\nSreg2: s13 is s13 & reg2Num=13 { export s13; }\nSreg2: s14 is s14 & reg2Num=14 { export s14; }\nSreg2: s15 is s15 & reg2Num=15 { export s15; }\nSreg2: s16 is s16 & reg2Num=16 { export s16; }\nSreg2: s17 is s17 & reg2Num=17 { export s17; }\nSreg2: s18 is s18 & reg2Num=18 { export s18; }\nSreg2: s19 is s19 & reg2Num=19 { export s19; }\nSreg2: s20 is s20 & reg2Num=20 { export s20; }\nSreg2: s21 is s21 & reg2Num=21 { export s21; }\nSreg2: s22 is s22 & reg2Num=22 { export s22; }\nSreg2: s23 is s23 & reg2Num=23 { export s23; }\nSreg2: s24 is s24 & reg2Num=24 { export s24; }\nSreg2: s25 is s25 & reg2Num=25 { export s25; }\nSreg2: s26 is s26 & reg2Num=26 { export s26; }\nSreg2: s27 is s27 & reg2Num=27 { export s27; }\nSreg2: s28 is s28 & reg2Num=28 { export s28; }\nSreg2: s29 is s29 & reg2Num=29 { export s29; }\nSreg2: s30 is s30 & reg2Num=30 { export s30; }\nSreg2: s31 is s31 & reg2Num=31 { export s31; }\n\nDreg: d0 is d0 & regNum=0 { export d0; }\nDreg: d1 is d1 & regNum=1 { export d1; }\nDreg: d2 is d2 & regNum=2 { export d2; }\nDreg: d3 is d3 & regNum=3 { export d3; }\nDreg: d4 is d4 & regNum=4 { export d4; }\nDreg: d5 is d5 & regNum=5 { export d5; }\nDreg: d6 is d6 & regNum=6 { export d6; }\nDreg: d7 is d7 & regNum=7 { export d7; }\nDreg: d8 is d8 & regNum=8 { export d8; }\nDreg: d9 is d9 & regNum=9 { export d9; }\nDreg: d10 is d10 & regNum=10 { export d10; }\nDreg: d11 is d11 & regNum=11 { export d11; }\nDreg: d12 is d12 & regNum=12 { export d12; }\nDreg: d13 is d13 & regNum=13 { export d13; }\nDreg: d14 is d14 & regNum=14 { export d14; }\nDreg: d15 is d15 & regNum=15 { export d15; }\nDreg2: d0 is d0 & reg2Num=0 { export d0; }\nDreg2: d1 is d1 & reg2Num=1 { export d1; }\nDreg2: d2 is d2 & reg2Num=2 { export d2; }\nDreg2: d3 is d3 & reg2Num=3 { export d3; }\nDreg2: d4 is d4 & reg2Num=4 { export d4; }\nDreg2: d5 is d5 & reg2Num=5 { export d5; }\nDreg2: d6 is d6 & reg2Num=6 { export d6; }\nDreg2: d7 is d7 & reg2Num=7 { export d7; }\nDreg2: d8 is d8 & reg2Num=8 { export d8; }\nDreg2: d9 is d9 & reg2Num=9 { export d9; }\nDreg2: d10 is d10 & reg2Num=10 { export d10; }\nDreg2: d11 is d11 & reg2Num=11 { export d11; }\nDreg2: d12 is d12 & reg2Num=12 { export d12; }\nDreg2: d13 is d13 & reg2Num=13 { export d13; }\nDreg2: d14 is d14 & reg2Num=14 { export d14; }\nDreg2: d15 is d15 & reg2Num=15 { export d15; }\n@if defined(SIMD) || defined(VFPv3)\nDreg: d16 is d16 & regNum=16 { export d16; }\nDreg: d17 is d17 & regNum=17 { export d17; }\nDreg: d18 is d18 & regNum=18 { export d18; }\nDreg: d19 is d19 & regNum=19 { export d19; }\nDreg: d20 is d20 & regNum=20 { export d20; }\nDreg: d21 is d21 & regNum=21 { export d21; }\nDreg: d22 is d22 & regNum=22 { export d22; }\nDreg: d23 is d23 & regNum=23 { export d23; }\nDreg: d24 is d24 & regNum=24 { export d24; }\nDreg: d25 is d25 & regNum=25 { export d25; }\nDreg: d26 is d26 & regNum=26 { export d26; }\nDreg: d27 is d27 & regNum=27 { export d27; }\nDreg: d28 is d28 & regNum=28 { export d28; }\nDreg: d29 is d29 & regNum=29 { export d29; }\nDreg: d30 is d30 & regNum=30 { export d30; }\nDreg: d31 is d31 & regNum=31 { export d31; }\nDreg2: d16 is d16 & reg2Num=16 { export d16; }\nDreg2: d17 is d17 & reg2Num=17 { export d17; }\nDreg2: d18 is d18 & reg2Num=18 { export d18; }\nDreg2: d19 is d19 & reg2Num=19 { export d19; }\nDreg2: d20 is d20 & reg2Num=20 { export d20; }\nDreg2: d21 is d21 & reg2Num=21 { export d21; }\nDreg2: d22 is d22 & reg2Num=22 { export d22; }\nDreg2: d23 is d23 & reg2Num=23 { export d23; }\nDreg2: d24 is d24 & reg2Num=24 { export d24; }\nDreg2: d25 is d25 & reg2Num=25 { export d25; }\nDreg2: d26 is d26 & reg2Num=26 { export d26; }\nDreg2: d27 is d27 & reg2Num=27 { export d27; }\nDreg2: d28 is d28 & reg2Num=28 { export d28; }\nDreg2: d29 is d29 & reg2Num=29 { export d29; }\nDreg2: d30 is d30 & reg2Num=30 { export d30; }\nDreg2: d31 is d31 & reg2Num=31 { export d31; }\n@else\n# this is just a placeholder so the parse patterns will match correctly.\n# regNum is 31 when the base pattern matches, and incremented when\n# this constructor actually matches\nDreg: d0 is d0 & regNum=31 { export d0; }\nDreg2: d0 is d0 & reg2Num=31 { export d0; }\n@endif\n@endif\n\nVRm: Rm is TMode=0 & Rm { export Rm; }\nVRm: thv_Rm is TMode=1 & thv_Rm { export thv_Rm; }\n\nVRn: Rn is TMode=0 & Rn { export Rn; }\nVRn: thv_Rn is TMode=1 & thv_Rn { export thv_Rn; }\n\nVRd: Rd is TMode=0 & Rd { export Rd; }\nVRd: thv_Rd is TMode=1 & thv_Rd { export thv_Rd; }\n\nSd: Sd0\t\tis TMode=0 & Sd0 & D22=0\t{ export Sd0; }\nSd: Sd1\t\tis TMode=0 & Sd1 & D22=1\t{ export Sd1; }\nSd: thv_Sd0\tis TMode=1 & thv_Sd0 & thv_D22=0\t{ export thv_Sd0; }\nSd: thv_Sd1\tis TMode=1 & thv_Sd1 & thv_D22=1\t{ export thv_Sd1; }\n\nSn: Sn0\t\tis TMode=0 & Sn0 & N7=0\t{ export Sn0; }\nSn: Sn1\t\tis TMode=0 & Sn1 & N7=1\t{ export Sn1; }\nSn: thv_Sn0\tis TMode=1 & thv_Sn0 & thv_N7=0\t{ export thv_Sn0; }\nSn: thv_Sn1\tis TMode=1 & thv_Sn1 & thv_N7=1\t{ export thv_Sn1; }\n\nSm: Sm0\t\tis TMode=0 & Sm0 & M5=0\t{ export Sm0; }\nSm: Sm1\t\tis TMode=0 & Sm1 & M5=1\t{ export Sm1; }\nSm: thv_Sm0\tis TMode=1 & thv_Sm0 & thv_M5=0\t{ export thv_Sm0; }\nSm: thv_Sm1\tis TMode=1 & thv_Sm1 & thv_M5=1\t{ export thv_Sm1; }\n\nSmNext: Sm0next\t\tis TMode=0 & Sm0next & M5=0\t{ export Sm0next; }\nSmNext: Sm1next\t\tis TMode=0 & Sm1next & M5=1\t{ export Sm1next; }\nSmNext: thv_Sm0next\tis TMode=1 & thv_Sm0next & thv_M5=0\t{ export thv_Sm0next; }\nSmNext: thv_Sm1next\tis TMode=1 & thv_Sm1next & thv_M5=1\t{ export thv_Sm1next; }\n\nSd2: Sd\t\tis Sd\t\t\t{ export Sd; }\n\n@endif # VFPv2 || VFPv3\n\nudt: \"s\"\tis TMode=0 & c2424=0\t\t\t{ export 0:1; }\nudt: \"u\"\tis TMode=0 & c2424=1\t\t\t{ export 1:1; }\nudt: \"s\"\tis TMode=1 & thv_c2828=0\t\t{ export 0:1; }\nudt: \"u\"\tis TMode=1 & thv_c2828=1\t\t{ export 1:1; }\n\nudt7: \"s\"\tis TMode=0 & c0707=0\t\t\t{ export 0:1; }\nudt7: \"u\"\tis TMode=0 & c0707=1\t\t\t{ export 1:1; }\nudt7: \"s\"\tis TMode=1 & thv_c0707=0\t\t{ export 0:1; }\nudt7: \"u\"\tis TMode=1 & thv_c0707=1\t\t{ export 1:1; }\n\nfdt: \"u\"\tis TMode=0 & c0808=0\t\t\t{ export 0:1; }\nfdt: \"f\"\tis TMode=0 & c0808=1\t\t\t{ export 1:1; }\nfdt: \"u\"\tis TMode=1 & thv_c0808=0\t\t{ export 0:1; }\nfdt: \"f\"\tis TMode=1 & thv_c0808=1\t\t{ export 1:1; }\n\nesize2021: \"8\" \t\tis TMode=0 & c2021=0\t\t{ export 1:4; }\nesize2021: \"16\" \tis TMode=0 & c2021=1\t\t{ export 2:4; }\nesize2021: \"32\" \tis TMode=0 & c2021=2\t\t{ export 4:4; }\nesize2021: \"64\" \tis TMode=0 & c2021=3\t\t{ export 8:4; }\nesize2021: \"8\" \t\tis TMode=1 & thv_c2021=0\t{ export 1:4; }\nesize2021: \"16\" \tis TMode=1 & thv_c2021=1\t{ export 2:4; }\nesize2021: \"32\" \tis TMode=1 & thv_c2021=2\t{ export 4:4; }\nesize2021: \"64\" \tis TMode=1 & thv_c2021=3\t{ export 8:4; }\n\nesize2021x2: \"16\" \tis TMode=0 & c2021=0\t\t{ export 2:4; }\nesize2021x2: \"32\" \tis TMode=0 & c2021=1\t\t{ export 4:4; }\nesize2021x2: \"64\" \tis TMode=0 & c2021=2\t\t{ export 8:4; }\nesize2021x2: \"16\" \tis TMode=1 & thv_c2021=0\t{ export 2:4; }\nesize2021x2: \"32\" \tis TMode=1 & thv_c2021=1\t{ export 4:4; }\nesize2021x2: \"64\" \tis TMode=1 & thv_c2021=2\t{ export 8:4; }\n\nesize1819: \"8\" \t\tis TMode=0 & c1819=0\t\t{ export 1:4; }\nesize1819: \"16\" \tis TMode=0 & c1819=1\t\t{ export 2:4; }\nesize1819: \"32\" \tis TMode=0 & c1819=2\t\t{ export 4:4; }\nesize1819: \"64\" \tis TMode=0 & c1819=3\t\t{ export 8:4; }\nesize1819: \"8\" \t\tis TMode=1 & thv_c1819=0\t{ export 1:4; }\nesize1819: \"16\" \tis TMode=1 & thv_c1819=1\t{ export 2:4; }\nesize1819: \"32\" \tis TMode=1 & thv_c1819=2\t{ export 4:4; }\nesize1819: \"64\" \tis TMode=1 & thv_c1819=3\t{ export 8:4; }\n\nesize1819x2: \"16\" \tis TMode=0 & c1819=0\t\t{ export 2:4; }\nesize1819x2: \"32\" \tis TMode=0 & c1819=1\t\t{ export 4:4; }\nesize1819x2: \"64\" \tis TMode=0 & c1819=2\t\t{ export 8:4; }\nesize1819x2: \"16\" \tis TMode=1 & thv_c1819=0\t{ export 2:4; }\nesize1819x2: \"32\" \tis TMode=1 & thv_c1819=1\t{ export 4:4; }\nesize1819x2: \"64\" \tis TMode=1 & thv_c1819=2\t{ export 8:4; }\n\nesize1819x3: \"8\" \tis TMode=0 & c1819=0\t\t{ export 1:4; }\nesize1819x3: \"16\" \tis TMode=0 & c1819=1\t\t{ export 2:4; }\nesize1819x3: \"32\" \tis TMode=0 & c1819=2\t\t{ export 4:4; }\nesize1819x3: \"8\" \tis TMode=1 & thv_c1819=0\t{ export 1:4; }\nesize1819x3: \"16\" \tis TMode=1 & thv_c1819=1\t{ export 2:4; }\nesize1819x3: \"32\" \tis TMode=1 & thv_c1819=2\t{ export 4:4; }\n\nesize1011: \"8\" \t\tis TMode=0 & c1011=0\t { export 1:4; }\nesize1011: \"16\" \tis TMode=0 & c1011=1\t\t{ export 2:4; }\nesize1011: \"32\" \tis TMode=0 & c1011=2\t\t{ export 4:4; }\nesize1011: \"64\" \tis TMode=0 & c1011=3\t\t{ export 8:4; }\nesize1011: \"8\" \t\tis TMode=1 & thv_c1011=0\t{ export 1:4; }\nesize1011: \"16\" \tis TMode=1 & thv_c1011=1\t{ export 2:4; }\nesize1011: \"32\" \tis TMode=1 & thv_c1011=2\t{ export 4:4; }\nesize1011: \"64\" \tis TMode=1 & thv_c1011=3\t{ export 8:4; }\n\nesize0607: \"8\" \t\tis TMode=0 & c0607=0\t{ export 1:4; }\nesize0607: \"16\" \tis TMode=0 & c0607=1\t{ export 2:4; }\nesize0607: \"32\" \tis TMode=0 & c0607=2\t{ export 4:4; }\nesize0607: \"64\" \tis TMode=0 & c0607=3\t{ export 8:4; } # see VLD4 (single 4-element structure to all lanes)\nesize0607: \"8\" \t\tis TMode=1 & thv_c0607=0\t{ export 1:4; }\nesize0607: \"16\" \tis TMode=1 & thv_c0607=1\t{ export 2:4; }\nesize0607: \"32\" \tis TMode=1 & thv_c0607=2\t{ export 4:4; }\nesize0607: \"64\" \tis TMode=1 & thv_c0607=3\t{ export 8:4; } # see VLD4 (single 4-element structure to all lanes)\n\n\nfesize2323: \"16\" \tis TMode=0 & c2323=1\t\t{ export 4:4; }\nfesize2323: \"32\" \tis TMode=0 & c2323=0\t\t{ export 2:4; }\nfesize2323: \"16\" \tis TMode=1 & thv_c2323=1\t{ export 4:4; }\nfesize2323: \"32\" \tis TMode=1 & thv_c2323=0\t{ export 2:4; }\n\nfesize2020: \"16\" \tis TMode=0 & c2020=1\t\t{ export 4:4; }\nfesize2020: \"32\" \tis TMode=0 & c2020=0\t\t{ export 2:4; }\nfesize2020: \"16\" \tis TMode=1 & thv_c2020=1\t{ export 4:4; }\nfesize2020: \"32\" \tis TMode=1 & thv_c2020=0\t{ export 2:4; }\n\nfesize1819: \"16\" \tis TMode=0 & c1819=1\t\t{ export 4:4; }\nfesize1819: \"32\" \tis TMode=0 & c1819=2\t\t{ export 2:4; }\nfesize1819: \"16\" \tis TMode=1 & thv_c1819=1\t{ export 4:4; }\nfesize1819: \"32\" \tis TMode=1 & thv_c1819=2\t{ export 2:4; }\n\nroundType: \"a\" is TMode=0 & c0809=0 { export 0:1; }\nroundType: \"a\" is TMode=1 & thv_c0809=0 { export 0:1; }\nroundType: \"n\" is TMode=0 & c0809=1 { export 1:1; }\nroundType: \"n\" is TMode=1 & thv_c0809=1 { export 1:1; }\nroundType: \"p\" is TMode=0 & c0809=2 { export 2:1; }\nroundType: \"p\" is TMode=1 & thv_c0809=2 { export 2:1; }\nroundType: \"m\" is TMode=0 & c0809=3 { export 3:1; }\nroundType: \"m\" is TMode=1 & thv_c0809=3 { export 3:1; }\n\ndefine pcodeop VFPExpandImmediate;\n\n\n\n# float\nvfpExpImm_4: imm\t\tis TMode=0 & c1919 & c1818 & c1617 & c0003 [ imm = (c1919 << 31) | ((c1818 $xor 1) << 30) | ((c1818 * 0x1f) << 25) | (c1617 << 23) | (c0003 << 19); ] \t{\n\texport *[const]:4 imm; \n}\n\n# float\nvfpExpImm_4: imm\t\tis TMode=1 & thv_c1919 & thv_c1818 & thv_c1617 & thv_c0003 [ imm = (thv_c1919 << 31) | ((thv_c1818 $xor 1) << 30) | ((thv_c1818 * 0x1f) << 25) | (thv_c1617 << 23) | (thv_c0003 << 19); ] \t{\n\texport *[const]:4 imm; \n}\n\n\n# double \nvfpExpImm_8: imm\t\tis TMode=0 & c1919 & c1818 & c1617 & c0003 [ imm = (c1919 << 63) | ((c1818 $xor 1) << 62) | ((c1818 * 0xff) << 54) | (c1617 << 52) | (c0003 << 48); ] \t{\n\texport *[const]:8 imm;\n}\n\n# double \nvfpExpImm_8: imm\t\tis TMode=1 & thv_c1919 & thv_c1818 & thv_c1617 & thv_c0003 [ imm = (thv_c1919 << 63) | ((thv_c1818 $xor 1) << 62) | ((thv_c1818 * 0xff) << 54) | (thv_c1617 << 52) | (thv_c0003 << 48); ] \t{\n\texport *[const]:8 imm;\n}\n\ndefine pcodeop SIMDExpandImmediate;\n\nsimdExpImm_8: \"#0\" \tis TMode=0 & c2424=0 & c1618=0 & c0003=0\t{\n\texport 0:8;\n}\nsimdExpImm_8: \"simdExpand(\"^c0505^\",\"^cmode^\",\"^val^\")\" \tis TMode=0 & c2424 & c1618 & c0505 & c0003 & cmode [ val = (c2424 << 7) | (c1618 << 4) | c0003; ]\t{\n\timm64:8 = SIMDExpandImmediate(c0505:1, cmode:1, val:1);\n\texport imm64;\n}\nsimdExpImm_8: \"#0\" \tis TMode=1 & thv_c2828=0 & thv_c1618=0 & thv_c0003=0\t{\n\texport 0:8;\n}\nsimdExpImm_8: \"simdExpand(\"^thv_c0505^\",\"^thv_cmode^\",\"^val^\")\" \tis TMode=1 & thv_c2828 & thv_c1618 & thv_c0505 & thv_c0003 & thv_cmode [ val = (thv_c2828 << 7) | (thv_c1618 << 4) | thv_c0003; ]\t{\n\timm64:8 = SIMDExpandImmediate(thv_c0505:1, thv_cmode:1, val:1);\n\texport imm64;\n}\n\nsimdExpImm_16: \"#0\" \tis TMode=0 & c2424=0 & c1618=0 & c0003=0\t{\n\ttmp:8 = 0; \n\ttmp1:16 = zext(tmp); \n\texport tmp1;\n}\nsimdExpImm_16: \"simdExpand(\"^c0505^\",\"^cmode^\",\"^val^\")\" \tis TMode=0 & c2424 & c1618 & c0505 & c0003 & cmode [ val = (c2424 << 7) | (c1618 << 4) | c0003; ]\t{\n\timm128:16 = SIMDExpandImmediate(c0505:1, cmode:1, val:1);\n\texport imm128;\n}\nsimdExpImm_16: \"#0\" \tis TMode=1 & thv_c2828=0 & thv_c1618=0 & thv_c0003=0\t{\n\ttmp:8 = 0; \n\ttmp1:16 = zext(tmp); \n\texport tmp1;\n}\nsimdExpImm_16: \"simdExpand(\"^thv_c0505^\",\"^thv_cmode^\",\"^val^\")\" \tis TMode=1 & thv_c2828 & thv_c1618 & thv_c0505 & thv_c0003 & thv_cmode [ val = (thv_c2828 << 7) | (thv_c1618 << 4) | thv_c0003; ]\t{\n\timm128:16 = SIMDExpandImmediate(thv_c0505:1, thv_cmode:1, val:1);\n\texport imm128;\n}\n\nsimdExpImmDT: \"i32\"\tis TMode=0 & c0911=0 { }\nsimdExpImmDT: \"i32\"\tis TMode=0 & c0911=1 { }\nsimdExpImmDT: \"i32\"\tis TMode=0 & c0911=2 { }\nsimdExpImmDT: \"i32\"\tis TMode=0 & c0911=3 { }\nsimdExpImmDT: \"i16\"\tis TMode=0 & c0911=4 { }\nsimdExpImmDT: \"i16\"\tis TMode=0 & c0911=5 { }\nsimdExpImmDT: \"i32\"\tis TMode=0 & c0811=12 { }\nsimdExpImmDT: \"i32\"\tis TMode=0 & c0811=13 { }\nsimdExpImmDT: \"i8\"\tis TMode=0 & c0811=14 & c0505=0 { }\nsimdExpImmDT: \"i64\"\tis TMode=0 & c0811=14 & c0505=1 { }\nsimdExpImmDT: \"f32\"\tis TMode=0 & c0811=15 & c0505=0 { }\n\nsimdExpImmDT: \"i32\"\tis TMode=1 & thv_c0911=0 { }\nsimdExpImmDT: \"i32\"\tis TMode=1 & thv_c0911=1 { }\nsimdExpImmDT: \"i32\"\tis TMode=1 & thv_c0911=2 { }\nsimdExpImmDT: \"i32\"\tis TMode=1 & thv_c0911=3 { }\nsimdExpImmDT: \"i16\"\tis TMode=1 & thv_c0911=4 { }\nsimdExpImmDT: \"i16\"\tis TMode=1 & thv_c0911=5 { }\nsimdExpImmDT: \"i32\"\tis TMode=1 & thv_c0811=12 { }\nsimdExpImmDT: \"i32\"\tis TMode=1 & thv_c0811=13 { }\nsimdExpImmDT: \"i8\"\tis TMode=1 & thv_c0811=14 & thv_c0505=0 { }\nsimdExpImmDT: \"i64\"\tis TMode=1 & thv_c0811=14 & thv_c0505=1 { }\nsimdExpImmDT: \"f32\"\tis TMode=1 & thv_c0811=15 & thv_c0505=0 { }\n\nmacro replicate1to8(bytes, dest) {\n\tlocal val:8 = zext(bytes);\n\tval = val | (val << 8);\n\tval = val | (val << 16);\n\tdest = val | (val << 32);\n}\n\nmacro replicate2to8(bytes, dest) {\n\tlocal val:8 = zext(bytes);\n\tval = val | (val << 16);\n\tdest = val | (val << 32);\n}\n\nmacro replicate4to8(bytes, dest) {\n\tlocal val:8 = zext(bytes);\n\tdest = val | (val << 32);\n}\n\ndefine pcodeop VectorAbsoluteDifferenceAndAccumulate;\ndefine pcodeop VectorAbsoluteDifference;\ndefine pcodeop FloatVectorAbsoluteDifference;\ndefine pcodeop VectorAbsolute;\ndefine pcodeop FloatVectorAbsolute;\n\n@if defined(SIMD)\n# CryptOp(val)\n#\tVarious crypto algorithms, too numerous for explication at\n#\tthis time\n\ndefine pcodeop CryptOp;\n#######\n# AESD single round decryption\n\ndefine pcodeop AESInvShiftRows;\ndefine pcodeop AESInvSubBytes;\n# F6.1.1 p3235 A1/T1\n:aesd.8\t\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001101 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001101 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tlocal shiftRows:16 = AESInvShiftRows(Qd ^ Qm);\n\tQd = AESInvSubBytes(shiftRows);\n}\n\n#######\n# AESE single round encryption\n\ndefine pcodeop AESShiftRows;\ndefine pcodeop AESSubBytes;\n# F6.1.2 p3237 A1/T1\n:aese.8\t\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001100 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001100 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tlocal shiftRows:16 = AESInvShiftRows(Qd ^ Qm);\n\tQd = AESSubBytes(shiftRows);\n}\n\n#######\n# AESIMC inverse mix columns\n\ndefine pcodeop AESInvMixColumns;\n# F6.1.3 p3239 A1/T1\n:aesimc.8\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001111 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001111 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tQd = AESInvMixColumns(Qm);\n}\n\n#######\n# AESMC mix columns\n\ndefine pcodeop AESMixColumns;\n# F6.1.4 p3240 A1/T1\n:aesmc.8\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001110 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001110 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tQd = AESMixColumns(Qm);\n}\n\n#######\n# SHA1C SHA1 hash update (choose)\n\ndefine pcodeop SHA1HashUpdateChoose;\n# F6.1.7 p3248 A1/T1\n:sha1c.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tlocal X = Qd;\n\tlocal Y = Qn:4;\n\tlocal W = Qm;\n\tQd = SHA1HashUpdateChoose(X, Y, W);\n}\n\n#######\n# SHA1H SHA1 fixed rotate\n\n# F6.1.8 p3250 A1/T1\n:sha1h.32\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b01 & c0611=0b001011 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b01 & thv_c0611=0b001011 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tlocal W:4 = Qm(0);\n\tQd = zext(W << 30 | W >> 2);\n}\n\n#######\n# SHA1M SHA1 hash update (majority)\n\ndefine pcodeop SHA1HashUpdateMajority;\n# F6.1.9 p3251 A1/T1\n:sha1m.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tlocal X = Qd;\n\tlocal Y = Qn:4;\n\tlocal W = Qm;\n\tQd = SHA1HashUpdateMajority(X, Y, W);\n}\n\n#######\n# SHA1P SHA1 hash update (parity)\n\ndefine pcodeop SHA1HashUpdateParity;\n# F6.1.10 p3253 A1/T1\n:sha1p.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tlocal X = Qd;\n\tlocal Y = Qn:4;\n\tlocal W = Qm;\n\tQd = SHA1HashUpdateParity(X, Y, W);\n}\n\n#######\n# SHA1SU0 SHA1 schedule update 0\n\n# F6.1.11 p3255 A1/T1\n:sha1su0.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b11 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tlocal op1 = Qd;\n\tlocal op2 = Qn;\n\tlocal op3 = Qm;\n\tlocal op2LowerHalf = zext(op2[0,64]) << 64;\n\tlocal op1UpperHalf = zext(op1[64,64]);\n\top2 = op2LowerHalf | op1UpperHalf;\n\tQd = op1 ^ op2 ^ op3;\n}\n\n#######\n# SHA1SU1 SHA1 schedule update 1\n\n# F6.1.12 p3257 A1/T1\n:sha1su1.32\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001110 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001110 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tlocal X = Qd;\n\tlocal Y = Qm;\n\tlocal Tm = X ^ (Y >> 32);\n\tlocal t0:4 = Tm[0, 32];\n\tlocal t1:4 = Tm[32, 32];\n\tlocal t2:4 = Tm[64, 32];\n\tlocal t3:4 = Tm[96, 32];\n\tlocal W0:4 = (t0 << 1 | t0 >> 31);\n\tlocal W1:4 = (t1 << 1 | t1 >> 31);\n\tlocal W2:4 = (t2 << 1 | t2 >> 31);\n\tlocal W3:4 = (t3 << 1 | t3 >> 31) ^ (t0 << 2 | t0 >> 30);\n\tQd = (zext(W3) << 96) | (zext(W2) << 64) | (zext(W1) << 32) | zext(W0);\n}\n\n#######\n# SHA256H SHA256 hash update part 1\n\ndefine pcodeop SHA256hash;\n# F6.1.13 p3259 A1/T1\n:sha256h.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tlocal part1:1 = 1;\n\tQd = SHA256hash(Qd,Qn,Qm, part1);\n}\n\n#######\n# SHA256H2 SHA256 hash update part 2\n\n# F6.1.14 p3260 A1/T1\n:sha256h2.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tlocal part1:1 = 0;\n\tQd = SHA256hash(Qd,Qn,Qm, part1);\n}\n\n#######\n# SHA256SU0 SHA256 schedule update 0\n\ndefine pcodeop SHA256ScheduleUpdate0;\n# F6.1.15 p3261 A1/T1\n:sha256su0.32\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001111 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001111 & thv_c0404=0))\n\t& Qd & Qm\n{\n\tQd = SHA256ScheduleUpdate0(Qd,Qm);\n}\n\n#######\n# SHA256SU1 SHA256 schedule update 1\n\ndefine pcodeop SHA256ScheduleUpdate1;\n# F6.1.16 p3263 A1/T1\n:sha256su1.32\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))\n\t& Qn & Qd & Qm\n{\n\tQd = SHA256ScheduleUpdate1(Qd,Qn,Qm);\n}\n\n# TODO: watch out for c2021=3\n\n:vaba.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=0 & c0404=1) | \n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_c0606=0 & thv_c0404=1 ) ) & Dm & Dn & Dd & udt & esize2021\n{\n\tDd = VectorAbsoluteDifferenceAndAccumulate(Dn,Dm,esize2021,udt);\n}\n\n:vaba.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=1 & c0404=1) | \n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_c0606=1 & thv_c0404=1 ) ) & Qd & Qn & Qm & udt & esize2021\n{\n\tQd = VectorAbsoluteDifferenceAndAccumulate(Qn,Qm,esize2021,udt);\n}\n\n:vabal.^udt^esize2021 Qd,Dn,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=5 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=5 & thv_c0606=0 & thv_c0404=0 ) ) & Qd & Dm & Dn & udt & esize2021\n{\n\tQd = VectorAbsoluteDifferenceAndAccumulate(Dn,Dm,esize2021,udt);\n}\n\n:vabd.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dm & Dn & Dd & udt & esize2021\n{\n\tDd = VectorAbsoluteDifference(Dn,Dm,esize2021,udt);\n}\n\n:vabd.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_Q6=1 & thv_c0404=0 ) ) & Qd & Qn & Qm & udt & esize2021\n{\n\tQd = VectorAbsoluteDifference(Qn,Qm,esize2021,udt);\n}\n\n:vabdl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=7 & Q6=0 & c0404=0 ) | \n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dm & Dn & Qd & udt & esize2021\n{\n\tQd = VectorAbsoluteDifference(Dn,Dm,esize2021,udt);\n}\n\n:vabd.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=13 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=13 & thv_c0606=0 & thv_c0404=0 ) ) & fesize2020 & Dd & Dm & Dn\n{\n\tDd = FloatVectorAbsoluteDifference(Dn,Dm,fesize2020);\n}\n\n:vabd.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=13 & Q6=1 & c0404=0 ) | \n ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=13 & thv_c0606=1 & thv_c0404=0 ) ) & fesize2020 & Qd & Qm & Qn\n{\n\tQd = FloatVectorAbsoluteDifference(Qn,Qm,fesize2020);\n}\n\n:vabs.s^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=6 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=6 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819\n{\n\tDd = VectorAbsolute(Dm,esize1819);\n}\n\n:vabs.s^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=6 & Q6=1 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=6 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819\n{\n\tQd = VectorAbsolute(Qm,esize1819);\n}\n\n:vabs.f^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xe & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xe & thv_c0606=0 & thv_c0404=0 ) ) & esize1819 & Dm & Dd\n{\n\tDd = FloatVectorAbsolute(Dm,esize1819);\n}\n\n:vabs.f^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xe & Q6=1 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xe & thv_c0606=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm\n{\n\tQd = FloatVectorAbsolute(Qm,esize1819);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vabs^COND^\".f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2b & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sm & Sd\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tSd = abs(Sm);\n}\n\n:vabs^COND^\".f64\" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2f & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Dd & Dm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tDd = abs(Dm);\n}\n\n@endif # VFPv2 || VFPv3\n\ndefine pcodeop FloatCompareGE;\ndefine pcodeop FloatCompareGT;\ndefine pcodeop VectorAbs;\ndefine pcodeop VectorAdd;\ndefine pcodeop VectorSub;\ndefine pcodeop FloatVectorAdd;\ndefine pcodeop VectorPairwiseAdd;\ndefine pcodeop VectorPairwiseMin;\ndefine pcodeop VectorPairwiseMax;\ndefine pcodeop FloatVectorPairwiseAdd;\ndefine pcodeop FloatVectorPairwiseMin;\ndefine pcodeop FloatVectorPairwiseMax;\ndefine pcodeop VectorPairwiseAddLong;\ndefine pcodeop VectorPairwiseAddAccumulateLong;\ndefine pcodeop VectorGetElement;\n\n@if defined(SIMD)\n\n:vacge.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=14 & thv_c0606=0 & thv_c0404=1 ) ) & fesize2020 & Dn & Dd & Dm\n{\n\tDd = FloatCompareGE(Dn,Dm,fesize2020);\n}\n\n:vacge.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=14 & thv_c0606=1 & thv_c0404=1 ) ) & fesize2020 & Qn & Qd & Qm\n{\n\tQd = FloatCompareGE(Qn,Qm,fesize2020);\n}\n\n:vacgt.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_c0606=0 & thv_c0404=1 ) ) & fesize2020 & Dn & Dd & Dm\n{\n\tDd = FloatCompareGT(Dn,Dm,fesize2020);\n}\n\n:vacgt.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_c0606=1 & thv_c0404=1 ) ) & fesize2020 & Qn & Qd & Qm\n{\n\tQd = FloatCompareGT(Qn,Qm,fesize2020);\n}\n\n:vadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & Q6=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorAdd(Dn,Dm,esize2021);\n}\n\n:vadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & Q6=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorAdd(Qn,Qm,esize2021);\n}\n\n:vadd.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd \n{\n\tDd = FloatVectorAdd(Dn,Dm,fesize2020);\n}\n\n:vadd.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qn & Qd & Qm\n{\n\tQd = FloatVectorAdd(Qn,Qm,fesize2020);\n}\n\n:vpadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=11 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=11 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorPairwiseAdd(Dn,Dm,esize2021);\n}\n\n:vpadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021<3 & c0811=11 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=11 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorPairwiseAdd(Qn,Qm,esize2021);\n}\n\n:vpadd.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=13 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm& Dn & Dd \n{\n\tDd = FloatVectorPairwiseAdd(Dn,Dm,fesize2020:1);\n}\n\n\n:vpmax.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=0)) & udt & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorPairwiseMax(Dn,Dm,esize2021,udt);\n}\n\n\n:vpmax.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=15 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd \n{\n\tDd = FloatVectorPairwiseMax(Dn,Dm,fesize2020:1);\n}\n\n:vpmin.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorPairwiseMin(Dn,Dm,esize2021,udt);\n}\n\n:vpmin.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=15 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd \n{\n\tDd = FloatVectorPairwiseMin(Dn,Dm,fesize2020);\n}\n\n:vpadal.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm\n{\n\tDd = VectorPairwiseAddAccumulateLong(Dm,esize1819);\n}\n\n:vpadal.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm\n{\n\tQd = VectorPairwiseAddAccumulateLong(Qm,esize1819);\n}\n\n:vpaddl.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm\n{\n\tDd = VectorPairwiseAddLong(Dm,esize1819);\n}\n\n:vpaddl.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm\n{\n\tQd = VectorPairwiseAddLong(Qm,esize1819);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vadd^COND^\".f16\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=9 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sd & Sn\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild Sn;\n\tlocal result:2 = Sn(0) f+ Sm(0);\n\tSd = zext(result);\n}\n\n:vadd^COND^\".f32\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=10 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sd & Sn\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild Sn;\n\tSd = Sn f+ Sm;\n}\n\n:vadd^COND^\".f64\" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=11 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dd & Dn\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tbuild Dn;\n\tDd = Dn f+ Dm;\n}\n\n@endif # VFPv2 || VFPv3\n\ndefine pcodeop VectorAddReturnHigh;\ndefine pcodeop VectorBitwiseInsertIfFalse;\ndefine pcodeop VectorBitwiseInsertIfTrue;\ndefine pcodeop VectorBitwiseSelect;\ndefine pcodeop VectorCompareEqual;\ndefine pcodeop FloatVectorCompareEqual;\ndefine pcodeop VectorCompareGreaterThanOrEqual;\ndefine pcodeop FloatVectorCompareGreaterThanOrEqual;\ndefine pcodeop VectorCompareGreaterThan;\ndefine pcodeop FloatVectorCompareGreaterThan;\ndefine pcodeop VectorCountLeadingSignBits;\ndefine pcodeop VectorCountLeadingZeros;\ndefine pcodeop VectorComplexAdd;\ndefine pcodeop VectorComplexMultiplyAccumulate;\ndefine pcodeop VectorComplexMultiplyAccumulateByElement;\n\n@if defined(SIMD)\n\n:vaddhn.i^esize2021x2 Dd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021<3 & c0811=4 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_c0606=0 & thv_c0404=0) ) & esize2021x2 & Qn & Dd & Qm\n{\n\tDd = VectorAddReturnHigh(Qn,Qm,esize2021x2);\n}\n\n:vaddl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0 & c0606=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Dn & Qd & Dm\n{\n\tQd = VectorAdd(Dn,Dm,esize2021,udt);\n}\n\n:vaddw.^udt^esize2021 Qd,Qn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=1 & c0606=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=1 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Qn & Qd & Dm\n{\n\tQd = VectorAdd(Qn,Dm,esize2021,udt);\n}\n\n\n:vand Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=1 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm\n{\n\tDd = Dn & Dm;\n}\n\n:vand Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=1 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qn & Qd & Qm\n{\n\tQd = Qn & Qm;\n}\n\n:vbic.i32 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1111=0 & c0808=1 & c0407=3 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1111=0 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8\n{\n\tDd = Dd & ~simdExpImm_8;\n}\n\n:vbic.i32 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1111=0 & c0808=1 & c0407=7 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1111=0 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16\n{\n\tQd = Qd & ~simdExpImm_16;\n}\n\n:vbic.i16 Dd,simdExpImm_8\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=1 & c0407=3 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8\n{\n\tDd = Dd & ~simdExpImm_8;\n}\n\n:vbic.i16 Qd,simdExpImm_16\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=1 & c0407=7 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16\n{\n\tQd = Qd & ~simdExpImm_16;\n}\n\n:vbic Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=1 & c0811=1 & Q6=0 & c0404=1 ) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1) ) & Dm & Dn & Dd\n{\n\tDd = Dn & ~Dm;\n}\n\n:vbic Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=1 & c0811=1 & Q6=1 & c0404=1 ) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd\n{\n\tQd = Qn & ~Qm;\n}\n\n:vbif Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=3 & c0811=1 & Q6=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1) ) & Dm & Dn & Dd\n{\n\tDd = VectorBitwiseInsertIfFalse(Dd,Dn,Dm);\n}\n\n:vbif Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=3 & c0811=1 & Q6=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qm & Qn & Qd\n{\n\tQd = VectorBitwiseInsertIfFalse(Qd,Qn,Qm);\n}\n\n:vbit Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=2 & c0811=1 & Q6=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dm & Dn & Dd\n{\n\tDd = VectorBitwiseInsertIfTrue(Dd,Dn,Dm);\n}\n\n:vbit Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=2 & c0811=1 & Q6=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qm & Qn & Qd\n{\n\tQd = VectorBitwiseInsertIfTrue(Qd,Qn,Qm);\n}\n\n:vbsl Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=1 & c0811=1 & Q6=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dm & Dn & Dd\n{\n\tDd = VectorBitwiseSelect(Dd,Dn,Dm);\n}\n\n:vbsl Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=1 & c0811=1 & Q6=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qm & Qn & Qd\n{\n\tQd = VectorBitwiseSelect(Qd,Qn,Qm);\n}\n\ncrot2424: \"#\"^90 is ($(AMODE) & c2424=0 ) | (TMode=1 & thv_c2424=0) { local tmp:4 = 90; export tmp; }\ncrot2424: \"#\"^270 is ($(AMODE) & c2424=1 ) | (TMode=1 & thv_c2424=1) { local tmp:4 = 270; export tmp; }\n\n\n:vcadd.f^fesize2020 Dd,Dn,Dm,crot2424 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2323=1 & c2121=0 & c0811=8 & Q6=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2121=0 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1)) & crot2424 & fesize2020 & Dm & Dn & Dd\n{\n\tDd = VectorComplexAdd(Dd,Dn,Dm,crot2424,fesize2020);\n}\n\n:vcadd.f^fesize2020 Qd,Qn,Qm,crot2424 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2323=1 & c2121=0 & c0811=8 & Q6=1 & c0404=1 )|\n ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2021=0 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1)) & crot2424 & fesize2020 & Qm & Qn & Qd\n{\n\tQd = VectorComplexAdd(Qd,Qn,Qm,crot2424,fesize2020);\n}\n\n\n:vceq.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1) ) & esize2021 & Dm & Dn & Dd\n{\n\tDd = VectorCompareEqual(Dn,Dm,esize2021);\n}\n\n:vceq.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorCompareEqual(Qn,Qm,esize2021);\n}\n\n:vceq.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=14 & Q6=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd\n{\n\tDd = FloatVectorCompareEqual(Dn,Dm,fesize2020);\n}\n\n:vceq.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=14 & Q6=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qm & Qn & Qd\n{\n\tQd = FloatVectorCompareEqual(Qn,Qm,fesize2020);\n}\n\n:vceq.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero\n{\n\tDd = VectorCompareEqual(Dm,zero,esize1819);\n}\n\n:vceq.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero\n{\n\tQd = VectorCompareEqual(Qm,zero,esize1819);\n}\n\n:vceq.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=10 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=10 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero\n{\n\tDd = FloatVectorCompareEqual(Dm,zero,fesize1819);\n}\n\n:vceq.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=1 & c0711=10 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=1 & thv_c0711=10 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero\n{\n\tQd = FloatVectorCompareEqual(Qm,zero,fesize1819);\n}\n\n:vcge.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=1) ) & udt & esize2021 & Dm & Dn & Dd\n{\n\tDd = VectorCompareGreaterThanOrEqual(Dn,Dm,esize2021,udt);\n}\n\n:vcge.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorCompareGreaterThanOrEqual(Qn,Qm,esize2021,udt);\n}\n\n:vcge.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd\n{\n\tDd = FloatVectorCompareGreaterThanOrEqual(Dn,Dm,2:1,32:1);\n}\n\n:vcge.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qm & Qn & Qd\n{\n\tQd = FloatVectorCompareGreaterThanOrEqual(Qn,Qm,2:1,32:1);\n}\n\n:vcge.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero\n{\n\tDd = VectorCompareGreaterThanOrEqual(Dm,zero,esize1819);\n}\n\n:vcge.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero\n{\n\tQd = VectorCompareGreaterThanOrEqual(Qm,zero,esize1819);\n}\n\n:vcge.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=9 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero\n{\n\tDd = FloatVectorCompareGreaterThanOrEqual(Dm,zero,fesize1819);\n}\n\n:vcge.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=9 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero\n{\n\tQd = FloatVectorCompareGreaterThanOrEqual(Qm,zero,fesize1819);\n}\n\n:vcgt.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=0) ) & udt & esize2021 & Dm & Dn & Dd\n{\n\tDd = VectorCompareGreaterThan(Dn,Dm,esize2021);\n}\n\n:vcgt.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=0) ) & udt & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorCompareGreaterThan(Qn,Qm,esize2021);\n}\n\n:vcgt.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd\n{\n\tDd = FloatVectorCompareGreaterThan(Dn,Dm,fesize2020);\n}\n\n:vcgt.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qm & Qn & Qd\n{\n\tQd = FloatVectorCompareGreaterThan(Qn,Qm,fesize2020);\n}\n\n:vcgt.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=0 & thv_c0404=0 ) ) & esize1819 & Dd & Dm & zero\n{\n\tDd = VectorCompareGreaterThan(Dm,zero,esize1819);\n}\n\n:vcgt.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm & zero\n{\n\tQd = VectorCompareGreaterThan(Qm,zero,esize1819);\n}\n\n:vcgt.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=8 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0 ) ) & fesize1819 & Dd & Dm & zero\n{\n\tDd = FloatVectorCompareGreaterThan(Dm,zero,fesize1819);\n}\n\n:vcgt.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=8 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0 ) ) & fesize1819 & Qd & Qm & zero\n{\n\tQd = FloatVectorCompareGreaterThan(Qm,zero,fesize1819);\n}\n\n:vcle.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm & zero\n{\n\tDd = VectorCompareGreaterThanOrEqual(zero,Dm,esize1819);\n}\n\n:vcle.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm & zero\n{\n\tQd = VectorCompareGreaterThanOrEqual(zero,Qm,esize1819);\n}\n\n:vcle.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xb & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xb & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dd & Dm & zero\n{\n\tDd = FloatVectorCompareGreaterThanOrEqual(zero,Dm,fesize1819);\n}\n\n:vcle.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xb & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xb & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qd & Qm & zero\n{\n\tQd = FloatVectorCompareGreaterThanOrEqual(zero,Qm,fesize1819);\n}\n\n:vcls.s^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm\n{\n\tDd = VectorCountLeadingSignBits(Dm,esize1819);\n}\n\n:vcls.s^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm\n{\n\tQd = VectorCountLeadingSignBits(Qm,esize1819);\n}\n\n:vclt.s^esize1819 Dd,Dm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=0 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero\n{\n\tDd = VectorCompareGreaterThan(zero,Dm,esize1819);\n}\n\n:vclt.s^esize1819 Qd,Qm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=1 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero\n{\n\tQd = VectorCompareGreaterThan(zero,Qm,esize1819);\n}\n\n:vclt.f^fesize1819 Dd,Dm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=12 & Q6=0 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=12 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero\n{\n\tDd = FloatVectorCompareGreaterThan(zero,Dm,fesize1819);\n}\n\n:vclt.f^fesize1819 Qd,Qm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=12 & Q6=1 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=12 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero\n{\n\tQd = FloatVectorCompareGreaterThan(zero,Qm,fesize1819);\n}\n\n:vclz.i^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=9 & Q6=0 & c0404=0) | \n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm\n{\n\tDd = VectorCountLeadingZeros(Dm,esize1819);\n}\n\n:vclz.i^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=9 & Q6=1 & c0404=0) | \n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm\n{\n\tQd = VectorCountLeadingZeros(Qm,esize1819);\n}\n\ncrot2324: \"#\"^0 is ($(AMODE) & c2324=0 ) | (TMode=1 & thv_c2324=0) { local tmp:4 = 0; export tmp; }\ncrot2324: \"#\"^90 is ($(AMODE) & c2324=1 ) | (TMode=1 & thv_c2324=1) { local tmp:4 = 90; export tmp; }\ncrot2324: \"#\"^180 is ($(AMODE) & c2324=2 ) | (TMode=1 & thv_c2324=2) { local tmp:4 = 180; export tmp; }\ncrot2324: \"#\"^270 is ($(AMODE) & c2324=3 ) | (TMode=1 & thv_c2324=3) { local tmp:4 = 270; export tmp; }\ncrot2021: \"#\"^0 is ($(AMODE) & c2021=0 ) | (TMode=1 & thv_c2021=0) { local tmp:4 = 0; export tmp; }\ncrot2021: \"#\"^90 is ($(AMODE) & c2021=1 ) | (TMode=1 & thv_c2021=1) { local tmp:4 = 90; export tmp; }\ncrot2021: \"#\"^180 is ($(AMODE) & c2021=2 ) | (TMode=1 & thv_c2021=2) { local tmp:4 = 180; export tmp; }\ncrot2021: \"#\"^270 is ($(AMODE) & c2021=3 ) | (TMode=1 & thv_c2021=3) { local tmp:4 = 270; export tmp; }\n\n:vcmla.f^fesize2020 Dd,Dn,Dm,crot2324 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2121=1 & c0811=8 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2527=6 & thv_c2121=1 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & crot2324 & fesize2020 & Dm & Dn & Dd\n{\n\tDd = VectorComplexMultiplyAccumulate(Dd,Dn,Dm,crot2324,fesize2020);\n}\n\n:vcmla.f^fesize2020 Qd,Qn,Qm,crot2324 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2121=1 & c0811=8 & Q6=1 & c0404=0 )|\n ($(TMODE_F) & thv_c2527=6 & thv_c2021=1 & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & crot2324 & fesize2020 & Qm & Qn & Qd\n{\n\tQd = VectorComplexMultiplyAccumulate(Qd,Qn,Qm,crot2324,fesize2020);\n}\n\n:vcmla.f^fesize2323 Dd,Dn,Dm,crot2021 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=7 & c2424=0 & c0811=8 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2527=7 & thv_c2424=0 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & crot2021 & fesize2323 & Dm & Dn & Dd\n{\n\tDd = VectorComplexMultiplyAccumulateByElement(Dd,Dn,Dm,crot2021,fesize2323);\n}\n\n:vcmla.f^fesize2323 Qd,Qn,Qm,crot2021 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=7 & c2424=0 & c0811=8 & Q6=1 & c0404=0 )|\n ($(TMODE_F) & thv_c2527=7 & thv_c2424=0 & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & crot2021 & fesize2323 & Qm & Qn & Qd\n{\n\tQd = VectorComplexMultiplyAccumulateByElement(Qd,Qn,Qm,crot2021,fesize2323);\n}\n\n@endif # SIMD\n\n# set float register flags correctly for comparison\nmacro FloatVectorCompare(op1,op2,nanx) {\n\tlocal tNG = op1 f< op2;\n\tlocal tZR = op1 f== op2;\t\n\tlocal tCY = op2 f<= op1;\n\ttOV:1 = nan(op1) | nan(op2); # this is really a comparison with NAN and may also raise an exception when NAN\n\t\n\tfpscr = (fpscr & 0x0fffffff) | (zext(tNG) << 31) | (zext(tZR) << 30) | (zext(tCY) << 29) | (zext(tOV) << 28);\n}\n\n@if defined(VFPv2) || defined(VFPv3)\n\nnanx: \"e\"\tis c0707=1\t{ export 1:1; }\nnanx: \t\tis c0707=0\t{ export 0:1; }\n\n:vcmp^nanx^COND^\".f16\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1001 & c0606=1 & c0404=0) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1001 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & nanx & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tlocal sm16:2 = Sm(0);\n\tlocal sd16:2 = Sd(0);\n\t\n\tFloatVectorCompare(sd16,sm16,nanx);\n}\n\n:vcmp^nanx^COND^\".f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1010 & c0606=1 & c0404=0) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1010 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & nanx & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\n\tFloatVectorCompare(Sd,Sm,nanx);\n}\n\n:vcmp^nanx^COND^\".f64\" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1011 & c0606=1 & c0404=0) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1011 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & nanx & Dm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tFloatVectorCompare(Dd,Dm,nanx);\n}\n\n:vcmp^nanx^COND^\".f16\" Sd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1001 & c0006=0b1000000 ) |\n\t\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1001 & thv_c0006=0b1000000 ) ) & COND & Sd & nanx & zero\n{\n\tbuild COND;\n\tbuild Sd;\n\tlocal Zero:2 = 0;\n\tlocal sd16:2 = Sd(0);\n\t\n\tFloatVectorCompare(sd16,Zero,nanx);\n}\n\n:vcmp^nanx^COND^\".f32\" Sd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1010 & c0006=0b1000000 ) |\n\t\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1010 & thv_c0006=0b1000000 ) ) & COND & Sd & nanx & zero\n{\n\tbuild COND;\n\tbuild Sd;\n\tlocal Zero:4 = 0;\n\tFloatVectorCompare(Sd,Zero,nanx);\n}\n\n:vcmp^nanx^COND^\".f64\" Dd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1011 & c0006=0b1000000 ) |\n\t\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1011 & thv_c0006=0b1000000 ) ) & COND & Dd & nanx & zero\n{\n\tbuild COND;\n\tbuild Dd;\n\tlocal Zero:8 = 0;\n\tFloatVectorCompare(Dd,Zero,nanx);\n}\n\n@endif # VFPv2 || VFPv3\n\ndefine pcodeop VectorCountOneBits;\n\n\n@ifndef VERSION_8\n#second arg to conversion function indicates rounding mode (see RMODE bits of FPSCR)\ndefine pcodeop VectorFloatToSigned;\ndefine pcodeop VectorFloatToUnsigned;\ndefine pcodeop VectorSignedToFloat;\ndefine pcodeop VectorUnsignedToFloat;\n@endif # VERSION_8\n\n@if defined(SIMD)\n#######\n# VCVT (between floating-point and integer, Advanced SIMD)\n#\n\n:vcnt.8 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0711=10 & Q6=0 & c0404=0) |\n\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0711=10 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm\n{\n\tDd = VectorCountOneBits(Dm,8:1,8:1);\n}\n\n:vcnt.8 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819=0 & c1617=0 & c0711=10 & Q6=1 & c0404=0) |\n\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0711=10 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm\n{\n\tQd = VectorCountOneBits(Qm,8:1,8:1);\n}\n\n@ifndef VERSION_8\n:vcvt.s16.f16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n\n{\n\tDd = VectorFloatToSigned(Dm,3:1);\n}\n\n:vcvt.u16.f16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n\n{\n\tDd = VectorFloatToUnsigned(Dm,0:1);\n}\n\n:vcvt.f16.s16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=0 & Q6=0 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n{\n\tDd = VectorSignedToFloat(Dm,0:1);\n}\n\n:vcvt.f16.u16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n\n{\n\tDd = VectorUnsignedToFloat(Dm,0:1);\n}\n\n:vcvt.s32.f32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n\n{\n\tDd = VectorFloatToSigned(Dm,3:1);\n}\n\n:vcvt.u32.f32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n\n{\n\tDd = VectorFloatToUnsigned(Dm,3:1);\n}\n\n:vcvt.f32.s32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=0 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n{\n\tDd = VectorSignedToFloat(Dm,0:1);\n}\n\n:vcvt.f32.u32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n\n{\n\tDd = VectorUnsignedToFloat(Dm,0:1);\n}\n\n\n\n\n\n:vcvt.s16.f16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorFloatToSigned(Qm,6:1);\n}\n\n:vcvt.u16.f16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorFloatToUnsigned(Qm,7:1);\n}\n\n:vcvt.f16.s16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorSignedToFloat(Qm,4:1);\n}\n\n:vcvt.f16.u16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorUnsignedToFloat(Qm,5:1);\n}\n\n:vcvt.s32.f32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorFloatToSigned(Qm,10:1);\n}\n\n:vcvt.u32.f32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorFloatToUnsigned(Qm,11:1);\n}\n\n:vcvt.f32.s32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorSignedToFloat(Qm,8:1);\n}\n\n:vcvt.f32.u32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n\n{\n\tQd = VectorUnsignedToFloat(Qm,9:1);\n}\n\n@endif # ! VERSION_8\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n@ifndef VERSION_8\n#######\n# VCVT (between floating-point and integer, VFP)\n#\n\nroundMode: \"r\"\tis TMode=0 & c0707=0\t\t{ tmp:1 = $(FPSCR_RMODE); export tmp; }\nroundMode: \t\tis TMode=0 & c0707=1\t\t{ export 3:1; } # Round towards zero\nroundMode: \"r\"\tis TMode=1 & thv_c0707=0\t{ tmp:1 = $(FPSCR_RMODE); export tmp; }\nroundMode: \t\tis TMode=1 & thv_c0707=1\t{ export 3:1; } # Round towards zero\n\n:vcvt^roundMode^COND^\".s32.f16\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=4 & c0808=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=4 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm & roundMode\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild roundMode;\n local Sm16:2 = Sm(0);\n\tSd = trunc(Sm16);#VectorFloatToSigned(Sm16,roundMode);\n}\n\n:vcvt^roundMode^COND^\".s32.f32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm & roundMode\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild roundMode;\n\tSd = trunc(Sm);#VectorFloatToSigned(Sm16,roundMode);\n}\n\n:vcvt^roundMode^COND^\".s32.f64\" Sd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & roundMode & Dm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Dm;\n\tbuild roundMode;\n\tSd = VectorFloatToSigned(Dm,roundMode);\n}\n\n:vcvt^roundMode^COND^\".u32.f16\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=4 & c0808=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=4 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & roundMode & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild roundMode;\n local Sm16:2 = Sm(0);\n\tSd = VectorFloatToUnsigned(Sm16,roundMode);\n}\n\n:vcvt^roundMode^COND^\".u32.f32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & COND & roundMode & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild roundMode;\n\tSd = VectorFloatToUnsigned(Sm,roundMode);\n}\n\n:vcvt^roundMode^COND^\".u32.f64\" Sd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0)) & COND & roundMode & Sd & Dm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Dm;\n\tbuild roundMode;\n\tSd = VectorFloatToUnsigned(Dm,roundMode);\n}\n\n:vcvt^COND^\".f16.s32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=4 & c0808=1 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=4 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tlocal mode:1 = $(FPSCR_RMODE);\n\tlocal Sm16:2 = Sm(0);\n\tSd = VectorSignedToFloat(Sm16,mode);\n}\n\n:vcvt^COND^\".f16.u32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=4 & c0808=1 & c0707=0 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=4 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tlocal mode:1 = $(FPSCR_RMODE);\n\tlocal Sm16:2 = Sm(0);\n\tSd = VectorUnsignedToFloat(Sm16,mode);\n}\n\n:vcvt^COND^\".f64.s32\" Dd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Sm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Sm;\n\tmode:1 = $(FPSCR_RMODE);\n\tDd = VectorSignedToFloat(Sm,mode);\n}\n\n:vcvt^COND^\".f32.s32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tmode:1 = $(FPSCR_RMODE);\n\tSd = VectorSignedToFloat(Sm,mode);\n}\n\n:vcvt^COND^\".f32.u32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tmode:1 = $(FPSCR_RMODE);\n\tSd = VectorUnsignedToFloat(Sm,mode);\n}\n\n:vcvt^COND^\".f64.u32\" Dd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Sm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Sm;\n\tmode:1 = $(FPSCR_RMODE);\n\tDd = VectorUnsignedToFloat(Sm,mode);\n}\n\n@endif # ! VERSION_8\n@endif # VFPv2 || VFPv3\n\n@if defined(SIMD)\n@ifndef VERSION_8\ndefine pcodeop VectorFloatToSignedFixed;\ndefine pcodeop VectorFloatToUnsignedFixed;\ndefine pcodeop VectorSignedFixedToFloat;\ndefine pcodeop VectorUnsignedFixedToFloat;\n\n#######\n# VCVT (between floating-point and fixed-point, Advanced SIMD)\n#\n\nfbits: \"#\"val\tis TMode=0 & c1621 [ val = 64 - c1621; ] { tmp:1 = val; export tmp; }\nfbits: \"#\"val\tis TMode=1 & thv_c1621 [ val = 64 - thv_c1621; ] { tmp:1 = val; export tmp; }\n\n:vcvt.s16.f16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm\n{\n\tDd = VectorFloatToSignedFixed(Dm,fbits);\n}\n\n:vcvt.u16.f16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm\n\n{\n\tDd = VectorFloatToUnsignedFixed(Dm,fbits);\n}\n\n:vcvt.f16.s16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=0 & c0707=0 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm\n{\n\tDd = VectorSignedFixedToFloat(Dm,fbits);\n}\n\n:vcvt.f16.u16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=0 & c0707=0 & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm\n{\n\tDd = VectorUnsignedFixedToFloat(Dm,fbits);\n}\n\n:vcvt.s16.f16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorFloatToSignedFixed(Qm,fbits);\n}\n\n:vcvt.u16.f16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorFloatToUnsignedFixed(Qm,fbits);\n}\n\n:vcvt.f16.s16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=0 & c0808=0 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=0 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorSignedFixedToFloat(Qm,fbits);\n}\n\n:vcvt.f16.u16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=0 & c0808=0 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=0 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorUnsignedFixedToFloat(Qm,fbits);\n}\n\n:vcvt.f32.s32 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm\n{\n\tDd = VectorSignedFixedToFloat(Dm,fbits);\n}\n\n:vcvt.f32.u32 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm\n{\n\tDd = VectorUnsignedFixedToFloat(Dm,fbits);\n}\n\n:vcvt.s32.f32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorFloatToSignedFixed(Qm,fbits);\n}\n\n:vcvt.u32.f32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorFloatToUnsignedFixed(Qm,fbits);\n}\n\n:vcvt.f32.s32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorSignedFixedToFloat(Qm,fbits);\n}\n\n:vcvt.f32.u32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm\n{\n\tQd = VectorUnsignedFixedToFloat(Qm,fbits);\n}\n\n@endif # ! VERSION_8\n\n@endif # SIMD\n\n@if defined(VFPv3)\n\n@ifndef VERSION_8\n\n#######\n# VCVT (between floating-point and fixed-point, VFP)\n#\n\nfbits16: \"#\"^val\tis TMode=0 & c0505 & c0003\t[ val = 16 - ((c0003 << 1) + c0505); ] { tmp:1 = val; export tmp; }\nfbits32: \"#\"^val\tis TMode=0 & c0505 & c0003\t[ val = 32 - ((c0003 << 1) + c0505); ] { tmp:1 = val; export tmp; }\nfbits16: \"#\"^val\tis TMode=1 & thv_c0505 & thv_c0003\t[ val = 16 - ((thv_c0003 << 1) + thv_c0505); ] { tmp:1 = val; export tmp; }\nfbits32: \"#\"^val\tis TMode=1 & thv_c0505 & thv_c0003\t[ val = 32 - ((thv_c0003 << 1) + thv_c0505); ] { tmp:1 = val; export tmp; }\n\n:vcvt^COND^\".s16.f16\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorFloatToSignedFixed(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".u16.f16\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".s32.f16\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorFloatToSignedFixed(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".u32.f16\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".s16.f32\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorFloatToSignedFixed(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".u16.f32\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".s32.f32\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorFloatToSignedFixed(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".u32.f32\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".s16.f64\" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits16;\n\tDd = VectorFloatToSignedFixed(Dd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".u16.f64\" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits16;\n\tDd = VectorFloatToUnsignedFixed(Dd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".s32.f64\" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits32;\n\tDd = VectorFloatToSignedFixed(Dd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".u32.f64\" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits32;\n\tDd = VectorFloatToUnsignedFixed(Dd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".f16.s16\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorSignedFixedToFloat(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".f16.u16\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".f16.s32\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorSignedFixedToFloat(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".f16.u32\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".f32.s16\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorSignedFixedToFloat(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".f32.u16\" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits16;\n\tSd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".f32.s32\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorSignedFixedToFloat(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".f32.u32\" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sd2;\n\tbuild fbits32;\n\tSd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".f64.s16\" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits16;\n\tDd = VectorSignedFixedToFloat(Dd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".f64.u16\" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits16;\n\tDd = VectorFloatToUnsignedFixed(Dd2,16:1,fbits16);\n}\n\n:vcvt^COND^\".f64.s32\" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits32;\n\tDd = VectorSignedFixedToFloat(Dd2,32:1,fbits32);\n}\n\n:vcvt^COND^\".f64.u32\" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dd2;\n\tbuild fbits32;\n\tDd = VectorFloatToUnsignedFixed(Dd2,32:1,fbits32);\n}\n\n@endif # ! VERSION_8\n\n@endif # VFPv3\n\ndefine pcodeop VectorFloatDoubleToSingle;\ndefine pcodeop VectorFloatSingleToDouble;\n\n@if defined(VFPv2) || defined(VFPv3)\n\n@ifndef VERSION_8\n#######\n# VCVT (between double-precision and single-precision)\n#\n\n:vcvt^COND^\".f32.f64\" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x37 & c0911=5 & c0808=1 & c0607=3 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x36 & thv_c0911=5 & thv_c0808=1 & thv_c0607=3 & thv_c0404=0 ) ) & COND & Sd & Dm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Dm;\n\tSd = float2float(Dm);\n}\n\n:vcvt^COND^\".f64.f32\" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x37 & c0911=5 & c0808=0 & c0607=3 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x36 & thv_c0911=5 & thv_c0808=0 & thv_c0607=3 & thv_c0404=0 ) ) & COND & Dd & Sm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Sm;\n\tDd = float2float(Sm);\n}\n\n@endif # ! VERSION_8\n@endif # VFPv2 || VFPv3\n\n@if defined(SIMD)\n\n@ifndef VERSION_8\n\ndefine pcodeop VectorFloatSingleToBFloat16;\ndefine pcodeop FloatSingleToBFloat16;\n\n#######\n# VCVT (between single-precision and BFloat16)\n#\n\n:vcvt.bf16.f32 Dd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=1 & thv_c0404=0 ) ) & Dd & Qm\n\n{\n\tDd = VectorFloatSingleToBFloat16(Qm, 4:1, 16:1);\n}\n\n# VCVTB Convert Single-precision to BFloat16 in Bottom\n:vcvtb^COND^\".bf16.f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x25 & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x25 & thv_c0404=0 ) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tlocal w:2 = FloatSingleToBFloat16(Sm);\n\tSd[0,16] = w;\n}\n\n\n# VCVTT Convert Single-precision to BFloat16 in Top\n:vcvtt^COND^\".bf16.f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x27 & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x27 & thv_c0404=0 ) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tw:2 = FloatSingleToBFloat16(Sm);\n\tSd[16,16] = w;\n}\n\ndefine pcodeop VectorFloatSingleToHalf;\ndefine pcodeop VectorFloatHalfToSingle;\n\n#######\n# VCVT (between half-precision and single-precision)\n#\n:vcvt.f16.f32 Dd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & Dd & Qm\n\n{\n\tDd = VectorFloatSingleToHalf(Qm, 4:1, 16:1);\n}\n\n:vcvt.f16.f32 Qd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=1 & c0607=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & Qd & Dm\n\n{\n\tQd = VectorFloatHalfToSingle(Dm, 4:1, 16:1);\n}\n\n\ndefine pcodeop VectorFloatToSignedRound;\ndefine pcodeop VectorFloatToUnsignedRound;\n\n# VCVTA/M/N/P Vector convert floating-point to integer with Rounding\n:vcvt^roundType^\".s16.f16\" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=0 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm\n{\n\tDd = VectorFloatToSignedRound(Dm, 0:1, roundType);\n}\n\n:vcvt^roundType^\".u16.f16\" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=1 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=1 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm\n{\n\tDd = VectorFloatToUnsignedRound(Dm, 0:1, roundType);\n}\n\n:vcvt^roundType^\".s32.f32\" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=0 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm\n{\n\tDd = VectorFloatToSignedRound(Dm, 1:1, roundType);\n}\n\n:vcvt^roundType^\".u32.f32\" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=1 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=1 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm\n{\n\tDd = VectorFloatToUnsignedRound(Dm, 1:1, roundType);\n}\n\n:vcvt^roundType^\".s16.f16\" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=0 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm\n{\n\tQd = VectorFloatToSignedRound(Qm, 0:1, roundType);\n}\n\n:vcvt^roundType^\".u16.f16\" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=1 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm\n{\n\tQd = VectorFloatToUnsignedRound(Qm, 0:1, roundType);\n}\n\n:vcvt^roundType^\".s32.f32\" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=0 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm\n{\n\tQd = VectorFloatToSignedRound(Qm, 1:1, roundType);\n}\n\n:vcvt^roundType^\".u32.f32\" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=1 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm\n{\n\tQd = VectorFloatToUnsignedRound(Qm, 1:1, roundType);\n}\n@endif # ! VERSION_8\n@endif # SIMD\n\n@if defined(VFPv3)\n\n@ifndef VERSION_8\n\ndefine pcodeop FloatToSignedRound;\ndefine pcodeop FloatToUnsignedRound;\n\n# VCVTA/M/N/P Float convert floating-point to integer with Rounding\n\n:vcvt^roundType^\".s32.f16\" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=1 & c0607=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Sm\n{\n\tlocal sm16:2 = Sm(0);\n\tSd = FloatToSignedRound(sm16, roundType);\n}\n\n:vcvt^roundType^\".u32.f16\" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=1 & c0607=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=1 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Sm\n{\n\tlocal sm16:2 = Sm(0);\n\tSd = FloatToUnsignedRound(sm16, roundType);\n}\n\n:vcvt^roundType^\".s32.f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=0 & c0607=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Sm\n{\n\tSd = FloatToSignedRound(Sm, roundType);\n}\n:vcvt^roundType^\".u32.f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=0 & c0607=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=0 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Sm\n{\n\tSd = FloatToUnsignedRound(Sm, roundType);\n}\n\n:vcvt^roundType^\".s32.f64\" Sd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=5 & c0808=1 & c0607=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=5 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Dm\n{\n\t\tSd = FloatToSignedRound(Dm, roundType);\n}\n:vcvt^roundType^\".u32.f64\" Sd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=5 & c0808=1 & c0607=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=5 & thv_c0808=1 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Dm\n{\n\t\tSd = FloatToUnsignedRound(Dm, roundType);\n}\n\n# VCVTB Convert Half-precision in Bottom to Single-precision\n\n:vcvtb^COND^\".f32.f16\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x29 & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tSd = float2float(Sm:2);\n}\n\n:vcvtb^COND^\".f16.f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x29 & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tlocal w:2 = float2float(Sm);\n\tSd[0,16] = w;\n}\n\n:vcvtb^COND^\".f64.f16\" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2d & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Dd & Sm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Sm;\n\tDd = float2float(Sm:2);\n}\n\n:vcvtb^COND^\".f16.f64\" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2d & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Sd & Dm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Dm;\n\tlocal w:2 = float2float(Dm);\n\tSd[0,16] = w;\n}\n\n# VCVTT Convert Half-precision in Top to Single-precision\n\n:vcvtt^COND^\".f32.f16\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2b & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tw:2 = Sm(2);\n\tSd = float2float(w);\n}\n\n:vcvtt^COND^\".f16.f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2b & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tw:2 = float2float(Sm);\n\tSd[16,16] = w;\n}\n\n:vcvtt^COND^\".f64.f16\" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2f & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Dd & Sm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Sm;\n\tw:2 = Sm(2);\n\tDd = float2float(w);\n}\n\n:vcvtt^COND^\".f16.f64\" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2f & c0404=0 ) |\n\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Sd & Dm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Dm;\n\tw:2 = float2float(Dm);\n\tSd[16,16] = w;\n}\n\n@endif # ! VERSION_8\n\n@endif # VFPv3\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vdiv^COND^\".f16\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=9 & c0606=0 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Sn & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild Sn;\n\tlocal sm16:2 = Sm(0);\n\tlocal sn16:2 = Sn(0);\n\tSd = zext(sn16 f/ sm16);\n}\n\n:vdiv^COND^\".f32\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Sn & Sd & Sm\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild Sn;\n\tSd = Sn f/ Sm;\n}\n\n:vdiv^COND^\".f64\" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Dn & Dd & Dm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tbuild Dn;\n\tDd = Dn f/ Dm;\n}\n\n@endif # VFPv2 || VFPv3\n\ndefine pcodeop VectorHalvingAdd;\ndefine pcodeop VectorHalvingSubtract;\ndefine pcodeop VectorRoundHalvingAdd;\ndefine pcodeop VectorRoundAddAndNarrow;\ndefine pcodeop VectorDotProduct;\ndefine pcodeop vectorFusedMultiplyAccumulate;\ndefine pcodeop BfloatMultiplyAccumulate;\ndefine pcodeop VectorMultiplyAddLongVector;\ndefine pcodeop VectorMultiplyAddLongScalar;\n\n\n@if defined(SIMD)\n\n# F6.1.79 VDOT (vector) page F6-8052 line 467006\n# xfc000d00/mask=xffb00f10 NOT MATCHED BY ANY CONSTRUCTOR\n# b_0031=111111000.00........1101...0....\n\n:vdot.bf16 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Dd\n{\n\tDd = VectorDotProduct(Dn,Dm);\n}\n\n:vdot.bf16 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & Qm & Qn & Qd\n{\n\tQd = VectorDotProduct(Qn,Qm);\n}\n\nMindex: \"[\"^M5^\"]\" is TMode=0 & M5 { local idx:1 = M5:1; export idx; }\nMindex: \"[\"^thv_M5^\"]\" is TMode=1 & thv_M5 { local idx:1 = thv_M5:1; export idx; }\n\n:vdot.bf16 Dd, Dn, Dm0^Mindex is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=0 ) ) & Dm0 & Mindex & Dn & Dd\n{\n\tDd = VectorDotProduct(Dn,Dm0,Mindex);\n}\n\n:vdot.bf16 Qd, Qn, Qm0^Mindex is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & Qm0 & Mindex & Qn & Qd\n{\n\tQd = VectorDotProduct(Qn,Qm0,Mindex);\n}\n\n#######\n# VDUP (scalar)\n#\n\nvdupIndex: c1719\tis TMode=0 & c1616=1 & c1719\t{ tmp:4 = c1719; export tmp; }\nvdupIndex: c1819\tis TMode=0 & c1617=2 & c1819\t{ tmp:4 = c1819; export tmp; }\nvdupIndex: c1919\tis TMode=0 & c1618=4 & c1919\t{ tmp:4 = c1919; export tmp; }\n\nvdupIndex: thv_c1719\tis TMode=1 & thv_c1616=1 & thv_c1719\t{ tmp:4 = thv_c1719; export tmp; }\nvdupIndex: thv_c1819\tis TMode=1 & thv_c1617=2 & thv_c1819\t{ tmp:4 = thv_c1819; export tmp; }\nvdupIndex: thv_c1919\tis TMode=1 & thv_c1618=4 & thv_c1919\t{ tmp:4 = thv_c1919; export tmp; }\n\nvdupSize: 8\t\t\tis TMode=0 & c1616=1 \t\t{ }\nvdupSize: 16\t\tis TMode=0 & c1617=2 \t\t{ }\nvdupSize: 32\t\tis TMode=0 & c1618=4 \t\t{ }\nvdupSize: 8\t\t\tis TMode=1 & thv_c1616=1 \t\t{ }\nvdupSize: 16\t\tis TMode=1 & thv_c1617=2 \t\t{ }\nvdupSize: 32\t\tis TMode=1 & thv_c1618=4 \t\t{ }\n\nvdupDm: Dm^\"[\"^vdupIndex^\"]\"\tis Dm & vdupIndex & ((TMode=0 & c1616=1) | (TMode=1 & thv_c1616=1))\n{\n\tptr:4 = &Dm + vdupIndex;\n\tval:8 = 0;\n\treplicate1to8(*[register]:1 ptr, val);\n\texport val;\n}\nvdupDm: Dm^\"[\"^vdupIndex^\"]\"\tis Dm & vdupIndex & ((TMode=0 & c1617=2) | (TMode=1 & thv_c1617=2))\n{\n\tptr:4 = &Dm + (2 * vdupIndex);\n\tval:8 = 0;\n\treplicate2to8(*[register]:2 ptr, val);\n\texport val;\n}\nvdupDm: Dm^\"[\"^vdupIndex^\"]\"\tis Dm & vdupIndex & ((TMode=0 & c1618=4) | (TMode=1 & thv_c1618=4))\n{\n\tptr:4 = &Dm + (4 * vdupIndex);\n\tval:8 = 0;\n\treplicate4to8(*[register]:4 ptr, val);\n\texport val;\n}\n\nvdupDm16: vdupDm\tis vdupDm\t\n{ \n\tval:16 = zext(vdupDm); \n\tval = val | (val << 64); \n\texport val; \n}\n\n:vdup.^vdupSize Dd,vdupDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & vdupSize & c0711=0x18 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c0711=0x18 & thv_Q6=0 & thv_c0404=0 ) ) & Dd & vdupDm\n{\n\tDd = vdupDm;\n}\n\n:vdup.^vdupSize Qd,vdupDm16\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & vdupSize & c0711=0x18 & Q6=1 & c0404=0 ) |\n ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c0711=0x18 & thv_Q6=1 & thv_c0404=0) ) & Qd & vdupDm16\n{\n\tQd = vdupDm16;\n}\n\n#######\n# VDUP (ARM core register)\n#\n\nvdupSize2: 8\t\tis TMode=0 & c2222=1 & c0505=0\t{ }\nvdupSize2: 16\t\tis TMode=0 & c2222=0 & c0505=1\t{ }\nvdupSize2: 32\t\tis TMode=0 & c2222=0 & c0505=0\t{ }\nvdupSize2: 8\t is TMode=1 & thv_c2222=1 & thv_c0505=0\t\t{ }\nvdupSize2: 16\t\tis TMode=1 & thv_c2222=0 & thv_c0505=1 \t\t{ }\nvdupSize2: 32\t\tis TMode=1 & thv_c2222=0 & thv_c0505=0\t\t{ }\n\nvdupRd8: VRd\tis VRd & ((TMode=0 & c2222=1 & c0505=0) | (TMode=1 & thv_c2222=1 & thv_c0505=0))\n{\n\tval:8 = 0;\n\tlocal tmpRd = VRd;\n\treplicate1to8(tmpRd:1, val);\n\texport val;\n}\nvdupRd8: VRd\tis VRd & ((TMode=0 & c2222=0 & c0505=1) | (TMode=1 & thv_c2222=0 & thv_c0505=1))\n{\n\tval:8 = 0;\n\tlocal tmpRd = VRd;\n\treplicate2to8(tmpRd:2, val);\n\texport val;\n}\nvdupRd8: VRd\tis VRd & ((TMode=0 & c2222=0 & c0505=0) | (TMode=1 & thv_c2222=0 & thv_c0505=0))\n{\n\tval:8 = 0;\n\tlocal tmpRd = VRd;\n\treplicate4to8(tmpRd:4, val);\n\texport val;\n}\n\nvdupRd16: vdupRd8\tis vdupRd8\t\n{ \n\tval:16 = zext(vdupRd8); \n\tval = val | (val << 64); \n\texport val; \n}\n\n:vdup^COND^\".\"^vdupSize2 Dn,VRd is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & VRd & COND & Dn & vdupSize2 & vdupRd8\n{\n\tbuild COND;\n\tbuild vdupRd8;\n\tbuild Dn;\n\tDn = vdupRd8;\n}\n\n:vdup^COND^\".\"^vdupSize2 Qn,VRd is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & VRd & COND & Qn & vdupSize2 & vdupRd16\n{\n\tbuild COND;\n\tbuild vdupRd16;\n\tbuild Qn;\n\tQn = vdupRd16;\n}\n\n:veor Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x6 & c2021=0 & c0811=1 & Q6=0 & c0404=1) |\n ($(TMODE_F) &thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm\n\n{\n\tDd = Dn ^ Dm;\n}\n\n:veor Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x6 & c2021=0 & c0811=1 & Q6=1 & c0404=1) |\n ($(TMODE_F) &thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm\n{\n\tQd = Qn ^ Qm;\n}\n\nextImm: \"#\"^c0811\t is TMode=0 & c0811\t\t{ tmp:1 = c0811; export tmp; }\nextImm: \"#\"^thv_c0811\tis TMode=1 & thv_c0811\t{ tmp:1 = thv_c0811; export tmp; }\n\n:vext.8 Dd,Dn,Dm,extImm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021=3 & c0606=0 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dn & Dm & extImm\n{\n\tval:16 = (zext(Dm) << 64) | zext(Dn);\n\tlocal shift = extImm * 8;\n\tval = val >> shift;\n\tDd = val:8;\n}\n\n:vext.8 Qd,Qn,Qm,extImm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021=3 & c0606=1 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qn & Qm & extImm\n{\n\tval:32 = (zext(Qm) << 128) | zext(Qn);\n\tlocal shift = extImm * 8;\n\tval = val >> shift;\n\tQd = val:16;\n}\n\n:vfma.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=0xc & c0606=0 & c0404=1 ) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=1) ) & fesize2020 & Dd & Dn & Dm\n{\n\tDd = vectorFusedMultiplyAccumulate(Dn, Dm, fesize2020);\n}\n\n:vfma.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=0xc & c0606=1 & c0404=1 ) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=1) ) & fesize2020 & Qd & Qn & Qm\n{\n\tQd = vectorFusedMultiplyAccumulate(Qn, Qm, fesize2020);\n}\n\n\n# Floating-point Multiply-Accumulate BFloat (vector)\n:vfmab.BF16 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x3 & c0811=8 & c0606=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Qd & Qn & Qm\n{\n\tQd = BfloatMultiplyAccumulate(Qn, Qm, 0:1);\n}\n\n:vfmat.BF16 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x3 & c0811=8 & c0606=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qn & Qm\n{\n\tQd = BfloatMultiplyAccumulate(Qn, Qm, 1:1);\n}\n\nvmfDm: Dm_3^\"[\"^index^\"]\"\t\tis TMode=0 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ]\t\t\t{ el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; }\nvmfDm: thv_Dm_3^\"[\"^index^\"]\"\tis TMode=1 & thv_Dm_3 & thv_M5 & thv_c0303 [ index = (thv_M5 << 1) + thv_c0303; ]\t{ el:4 = VectorGetElement(thv_Dm_3, index:1, 2:1, 0:1); export el; }\nvmfSm: Sm_3^\"[\"^c0303^\"]\"\t\tis TMode=0 & c0404=1 & Sm_3 & M5 & c0303\t{ el:4 = VectorGetElement(Sm_3, M5:1, 4:1, 0:1); export el; }\nvmfSm: Sm_3^\"[\"^c0303^\"]\"\t\tis TMode=1 & thv_c0404=1 & Sm_3 & thv_M5 & c0303\t{ el:4 = VectorGetElement(Sm_3, thv_M5:1, 4:1, 0:1); export el; }\n\n:vfmab.BF16 Qd,Qn,vmfDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x3 & c0811=8 & c0606=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Qd & Qn & vmfDm\n{\n\tQd = BfloatMultiplyAccumulate(Qn, vmfDm, 0:1);\n}\n\n:vfmat.BF16 Qd,Qn,vmfDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x3 & c0811=8 & c0606=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qn & vmfDm\n{\n\tQd = BfloatMultiplyAccumulate(Qn, vmfDm, 1:1);\n}\n\n:vfmal.F16 Dd,Sn,Sm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x2 & c0811=0x8 & c0606=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x2 & thv_c0811=0x8 & thv_c0606=0 & thv_c0404=1) ) & Dd & Sn & Sm\n{\n\tDd = VectorMultiplyAddLongVector(Sn, Sm, 0:1);\n}\n\n:vfmal.F16 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x2 & c0811=0x8 & c0606=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x2 & thv_c0811=0x8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Dn & Dm\n{\n\tQd = VectorMultiplyAddLongVector(Dn, Dm, 1:1);\n}\n\n:vfmal.F16 Dd,Sn,vmfSm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x2 & c0811=8 & c0606=0 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x2 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Dd & Sn & vmfSm\n{\n\tDd = VectorMultiplyAddLongScalar(Sn, vmfSm, 0:1);\n}\n\n:vfmal.F16 Qd,Dn,vmfDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x2 & c0811=8 & c0606=1 & c0404=1 ) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x2 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Dn & vmfDm\n{\n\tQd = VectorMultiplyAddLongScalar(Dn, vmfDm, 1:1);\n}\n\n\n\n\n:vhadd.^udt^esize2021 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=0 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=0 & thv_Q6=0 & thv_c0404=0) ) & udt & Dm & esize2021 & Dn & Dd\n{\n\tDd = VectorHalvingAdd(Dn,Dm,esize2021,udt);\n}\n\n:vhadd.^udt^esize2021 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=0 & Q6=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=0 & thv_Q6=1 & thv_c0404=0) ) & udt & Qm & esize2021 & Qn & Qd\n{\n\tQd = VectorHalvingAdd(Qn,Qm,esize2021,udt);\n}\n\n\n:vraddhn.i^esize2021x2 Dd,Qn,Qm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=4 & Q6=0 & c0404=0) |\n\t ($(TMODE_F) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_Q6=0 & thv_c0404=0) ) & Qm & esize2021x2 & Qn & Dd\n{\n\tDd = VectorRoundAddAndNarrow(Qn,Qm,esize2021x2);\n}\n\n:vrhadd.^udt^esize2021 Dd,Dn,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=1 & Q6=0 & c0404=0) |\n\t ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=0) ) & udt & Dm & esize2021 & Dn & Dd\n{\n\tDd = VectorRoundHalvingAdd(Dn,Dm,esize2021,udt);\n}\n\n:vrhadd.^udt^esize2021 Qd,Qn,Qm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=1 & Q6=1 & c0404=0) |\n\t ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=0) ) & udt & Qm & esize2021 & Qn & Qd\n{\n\tQd = VectorRoundHalvingAdd(Qn,Qm,esize2021,udt);\n}\n\n:vhsub.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=2 & Q6=0 & c0404=0) |\n\t ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=2 & thv_Q6=0 & thv_c0404=0) ) & udt & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorHalvingSubtract(Dn,Dm,esize2021,udt);\n}\n\n:vhsub.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=2 & Q6=1 & c0404=0) |\n\t ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=2 & thv_Q6=1 & thv_c0404=0) ) & udt & Qm & esize2021 & Qn & Qd\n{\n\tQd = VectorHalvingSubtract(Qn,Qm,esize2021,udt);\n}\n\n#######\n# VFMA VFMS VFNMA and VFNMS\n#\n\n@if defined(VFPv4)\n\n:vfma^COND^\".f16\" Sd,Sn,Sm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = zext(Sd:2 f+ (Sn:2 f* Sm:2));\n}\n\n:vfma^COND^\".f32\" Sd,Sn,Sm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = Sd f+ (Sn f* Sm);\n}\n\n:vfma^COND^\".f64\" Dd,Dn,Dm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=0 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd\n{\n\tDd = Dd f+ (Dn f* Dm);\n}\n\n:vfms^COND^\".f16\" Sd,Sn,Sm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=1 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = zext(Sd:2 f+ ((f- Sn:2) f* Sm:2));\n}\n\n:vfms^COND^\".f32\" Sd,Sn,Sm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=1 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = Sd f+ ((f- Sn) f* Sm);\n}\n\n:vfms^COND^\".f64\" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=1 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd\n{\n\tDd = Dd f+ ((f- Dn) f* Dm);\n}\n\n:vfnma^COND^\".f16\" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=1 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = zext((f- Sd:2) f+ ((f- Sn:2) f* Sm:2));\n}\n\n:vfnma^COND^\".f32\" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=1 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = (f- Sd) f+ ((f- Sn) f* Sm);\n}\n\n:vfnma^COND^\".f64\" Dd,Dn,Dm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=1 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd\n{\n\tDd = (f- Dd) f+ ((f- Dn) f* Dm);\n}\n\n:vfnms^COND^\".f16\" Sd,Sn,Sm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = zext((f- Sd:2) f+ (Sn:2 f* Sm:2));\n}\n\n:vfnms^COND^\".f32\" Sd,Sn,Sm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd\n{\n\tSd = (f- Sd) f+ (Sn f* Sm);\n}\n\n:vfnms^COND^\".f64\" Dd,Dn,Dm\tis ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd\n{\n\tDd = (f- Dd) f+ (Dn f* Dm);\n}\n\n@endif # VFPv4\n\n#######\n# VLD1 (multiple single elements)\n#\n\nbuildVld1DdList: Dreg\t\t\t\t\tis Dreg & counter=1 \t\t\t\t\t[ counter=0; regNum=regNum+1; ]\n{\n\tDreg = * mult_addr;\n}\nbuildVld1DdList: Dreg,buildVld1DdList\tis Dreg & buildVld1DdList [ counter=counter-1; regNum=regNum+1; ]\n{\n\tDreg = * mult_addr;\n\tmult_addr = mult_addr + 8;\n\tbuild buildVld1DdList;\n}\n\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=0 & c0811=7 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=0 & c0811=10 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=0 & c0811=6 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { export 3:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=0 & c0811=2 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { export 4:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { export 3:4; }\nvld1DdList: \"{\"^buildVld1DdList^\"}\"\tis TMode=1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { export 4:4; }\n\n@define Vld1DdList \"(c0811=2 | c0811=6 | c0811=7 | c0811=10)\"\n@define thv_Vld1DdList \"(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10)\"\n\nvldAlign45: is TMode=0 & c0405=0 { }\nvldAlign45: \":64\" is TMode=0 & c0405=1 { }\nvldAlign45: \":128\" is TMode=0 & c0405=2 { }\nvldAlign45: \":256\" is TMode=0 & c0405=3 { }\nvldAlign45: is TMode=1 & thv_c0405=0 { }\nvldAlign45: \":64\" is TMode=1 & thv_c0405=1 { }\nvldAlign45: \":128\" is TMode=1 & thv_c0405=2 { }\nvldAlign45: \":256\" is TMode=1 & thv_c0405=3 { }\n\nRnAligned45: \"[\"^VRn^vldAlign45^\"]\" \tis TMode=0 & VRn & vldAlign45\t{ export VRn; }\nRnAligned45: \"[\"^VRn^vldAlign45^\"]\" \tis TMode=1 & VRn & vldAlign45\t{ export VRn; }\n\n\n:vld1.^esize0607 vld1DdList,RnAligned45\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0003=15 & $(Vld1DdList)) |\n ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0003=15 & $(thv_Vld1DdList)) ) & esize0607 & RnAligned45 & vld1DdList\n{\n \tmult_addr = RnAligned45;\n \tbuild vld1DdList;\n}\n\n:vld1.^esize0607 vld1DdList,RnAligned45^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0003=13 & $(Vld1DdList)) |\n ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0003=13 & $(thv_Vld1DdList)) ) & esize0607 & RnAligned45 & vld1DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vld1DdList;\n\tRnAligned45 = RnAligned45 + (8 * vld1DdList);\n}\n\n:vld1.^esize0607 vld1DdList,RnAligned45,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & $(Vld1DdList)) |\n ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & $(thv_Vld1DdList)) ) & VRm & esize0607 & RnAligned45 & vld1DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vld1DdList;\n\tRnAligned45 = RnAligned45 + VRm;\n}\n\n\n#######\n# VLD1 (single element to one lane)\n#\n\nvld1Index: val\tis TMode=0 & c0507 & c1011\t [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; }\nvld1Index: val\tis TMode=1 & thv_c0507 & thv_c1011\t[ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; }\n\nvld1DdElement2: Dd^\"[\"^vld1Index^\"]\"\tis Dd & vld1Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dd + vld1Index;\n\t*[register]:1 ptr = *:1 mult_addr;\n}\nvld1DdElement2: Dd^\"[\"^vld1Index^\"]\"\tis Dd & vld1Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dd + (2 * vld1Index);\n\t*[register]:2 ptr = *:2 mult_addr;\n}\nvld1DdElement2: Dd^\"[\"^vld1Index^\"]\"\tis Dd & vld1Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dd + (4 * vld1Index);\n\t*[register]:4 ptr = *:4 mult_addr;\n}\n\n@define Vld1DdElement2 \"((c1011=0 & c0404=0) | (c1011=1 & c0505=0) | (c1011=2 & (c0406=0 | c0406=3)))\"\n@define T_Vld1DdElement2 \"((thv_c1011=0 & thv_c0404=0) | (thv_c1011=1 & thv_c0505=0) | (thv_c1011=2 & (thv_c0406=0 | thv_c0406=3)))\"\n\n\nvld1Align2: is TMode=0 & c0404=0 { }\nvld1Align2: \":16\" is TMode=0 & c1011=1 & c0404=1 { }\nvld1Align2: \":32\" is TMode=0 & c1011=2 & c0404=1 { }\nvld1Align2: is TMode=1 & thv_c0404=0 { }\nvld1Align2: \":16\" is TMode=1 & thv_c1011=1 & thv_c0404=1 { }\nvld1Align2: \":32\" is TMode=1 & thv_c1011=2 & thv_c0404=1 { }\n\nRnAligned2: \"[\"^VRn^vld1Align2^\"]\" \tis VRn & vld1Align2\t{ export VRn; }\n\n:vld1.^esize1011 vld1DdElement2,RnAligned2\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0809=0 & c0003=15 & $(Vld1DdElement2) ) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0809=0 & thv_c0003=15 & $(T_Vld1DdElement2) ) ) & RnAligned2 & esize1011 & vld1DdElement2\n{\n \tmult_addr = RnAligned2;\n\tbuild vld1DdElement2;\n}\n\n:vld1.^esize1011 vld1DdElement2,RnAligned2^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0809=0 & c0003=13 & $(Vld1DdElement2) ) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0809=0 & thv_c0003=13 & $(T_Vld1DdElement2) ) ) & RnAligned2 & esize1011 & vld1DdElement2\n{\n\tmult_addr = RnAligned2;\n\tbuild vld1DdElement2;\n\tRnAligned2 = RnAligned2 + esize1011;\n}\n\n:vld1.^esize1011 vld1DdElement2,RnAligned2,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0809=0 & $(Vld1DdElement2) ) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0809=0 & $(T_Vld1DdElement2) ) ) & VRm & RnAligned2 & esize1011 & vld1DdElement2\n{\n\tmult_addr = RnAligned2;\n\tbuild vld1DdElement2;\n\tRnAligned2 = RnAligned2 + VRm;\n}\n\n\n#######\n# VLD1 (single element to all lanes)\n#\n\nvld1RnReplicate:\tis ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & VRn\n{\n\tval:8 = 0;\n\treplicate1to8(*:1 VRn, val);\n\texport val;\n}\nvld1RnReplicate:\tis ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & VRn\n{\n\tval:8 = 0;\n\treplicate2to8(*:2 VRn, val);\n\texport val;\n}\nvld1RnReplicate:\tis ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & VRn\n{\n\tval:8 = 0;\n\treplicate4to8(*:4 VRn, val);\n\texport val;\n}\n\nvld1Dd3: Dreg^\"[]\"\t\tis Dreg\t\t{ export Dreg; }\n\nbuildVld1DdList3:\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVld1DdList3: vld1Dd3\t\t\tis counter=1\t& vld1Dd3\t\t[ counter=0; regNum=regNum+1; ] \n{ \n\tvld1Dd3 = mult_dat8;\n}\nbuildVld1DdList3: vld1Dd3,buildVld1DdList3\t\tis vld1Dd3 & buildVld1DdList3\t[ counter=counter-1; regNum=regNum+1; ] \n{\n\tvld1Dd3 = mult_dat8;\n\tbuild buildVld1DdList3;\n}\n\nvld1DdList3: \"{\"^buildVld1DdList3^\"}\"\tis TMode=0 & c0505=0 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; }\nvld1DdList3: \"{\"^buildVld1DdList3^\"}\"\tis TMode=0 & c0505=1 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; }\nvld1DdList3: \"{\"^buildVld1DdList3^\"}\"\tis TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; }\nvld1DdList3: \"{\"^buildVld1DdList3^\"}\"\tis TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; }\n\nvld1Align3: is TMode=0 & c0404=0 { }\nvld1Align3: \":16\" is TMode=0 & c0404=1 & c0607=1 { }\nvld1Align3: \":32\" is TMode=0 & c0404=1 & c0607=2 { }\nvld1Align3: is TMode=1 & thv_c0404=0 { }\nvld1Align3: \":16\" is TMode=1 & thv_c0404=1 & thv_c0607=1 { }\nvld1Align3: \":32\" is TMode=1 & thv_c0404=1 & thv_c0607=2 { }\n\nRnAligned3: \"[\"^VRn^vld1Align3^\"]\" \tis VRn & vld1Align3\t{ export VRn; }\n\n@define vld1Constrain \"((c0607=0 & c0404=0) | c0607=1 | c0607=2)\"\n@define T_vld1Constrain \"((thv_c0607=0 & thv_c0404=0) | thv_c0607=1 | thv_c0607=2)\"\n\n:vld1.^esize0607 vld1DdList3,RnAligned3 is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=12 & c0003=15 & $(vld1Constrain)) |\n ($(TMODE_F) & thv_c2327=19 & thv_c2021=2 & thv_c0811=12 & thv_c0003=15 & $(T_vld1Constrain)) & esize0607 & RnAligned3 & vld1RnReplicate & vld1DdList3\n{\n\tmult_dat8 = vld1RnReplicate;\n \tbuild vld1DdList3;\n}\n\n:vld1.^esize0607 vld1DdList3,RnAligned3^\"!\" is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=12 & c0003=13 & $(vld1Constrain)) |\n ($(TMODE_F) & thv_c2327=19 & thv_c2021=2 & thv_c0811=12 & thv_c0003=13 & $(T_vld1Constrain)) & esize0607 & RnAligned3 & vld1RnReplicate & vld1DdList3\n{\n\tmult_dat8 = vld1RnReplicate;\n\tbuild vld1DdList3;\n\tRnAligned3 = RnAligned3 + esize0607;\n}\n\n:vld1.^esize0607 vld1DdList3,RnAligned3,VRm is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=12 & $(vld1Constrain)) |\n ($(TMODE_F) & thv_c2327=19 & thv_c2021=2 & thv_c0811=12 & $(T_vld1Constrain)) & esize0607 & VRm & RnAligned3 & vld1RnReplicate & vld1DdList3\n{\n\tmult_dat8 = vld1RnReplicate;\n\tbuild vld1DdList3;\n\tRnAligned3 = RnAligned3 + VRm;\n}\n\n#######\n# VLD2 (multiple 2-element structures)\n#\n\nvld2Dd: Dreg\t\tis (($(AMODE) & c0607=0) | ($(TMODE_F) & thv_c0607=0)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n \tptr2:4 = &Dreg + (regInc * 8);\n@else # ENDIAN == \"big\"\n \tptr2:4 = &Dreg - (regInc * 8);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 8;\n\n\t*[register]:1 ptr1 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\t*[register]:1 ptr2 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 1;\n\tptr2 = ptr2 + 1;\n\tgoto ;\n\n}\nvld2Dd: Dreg\t\tis (($(AMODE) & c0607=1) | ($(TMODE_F) & thv_c0607=1)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n \tptr2:4 = &Dreg + (regInc * 8);\n@else # ENDIAN == \"big\"\n \tptr2:4 = &Dreg - (regInc * 8);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 4;\n\n\t*[register]:2 ptr1 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\t*[register]:2 ptr2 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 2;\n\tptr2 = ptr2 + 2;\n\tgoto ;\n\t\n}\nvld2Dd: Dreg\t\tis (($(AMODE) & c0607=2) | ($(TMODE_F) & thv_c0607=2)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n \tptr2:4 = &Dreg + (regInc * 8);\n@else # ENDIAN == \"big\"\n \tptr2:4 = &Dreg - (regInc * 8);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 2;\n\n\t*[register]:4 ptr1 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\t*[register]:4 ptr2 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 4;\n\tptr2 = ptr2 + 4;\n\tgoto ;\n\t\n}\n\nbuildVld2DdListA:\t\t\t\t\t\t\tis counter=0\t\t\t\t\t\t\t\t{ }\nbuildVld2DdListA: vld2Dd,buildVld2DdListA\tis vld2Dd & buildVld2DdListA & esize0607\t[ counter=counter-1; regNum=regNum+1; ] \n{\n\tbuild vld2Dd;\n\tbuild buildVld2DdListA;\n}\n\nbuildVld2DdListB:\t\t\t\t\t\t\tis counter2=0\t\t\t\t\t\t\t\t{ }\nbuildVld2DdListB: Dreg2\t\t\t\t\t\tis Dreg2 & counter2=1 & esize0607\t\t\t[ counter2=0; reg2Num=reg2Num+1; ] { }\nbuildVld2DdListB: Dreg2,buildVld2DdListB\tis Dreg2 & buildVld2DdListB & esize0607\t\t[ counter2=counter2-1; reg2Num=reg2Num+1; ] { }\n\nvld2DdList: \"{\"^buildVld2DdListA^buildVld2DdListB^\"}\"\tis TMode=0 & c0811=8 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; }\nvld2DdList: \"{\"^buildVld2DdListA^buildVld2DdListB^\"}\"\tis TMode=0 & c0811=9 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; }\nvld2DdList: \"{\"^buildVld2DdListA^buildVld2DdListB^\"}\"\tis TMode=0 & c0811=3 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; export 4:4; }\nvld2DdList: \"{\"^buildVld2DdListA^buildVld2DdListB^\"}\"\tis TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; }\nvld2DdList: \"{\"^buildVld2DdListA^buildVld2DdListB^\"}\"\tis TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; }\nvld2DdList: \"{\"^buildVld2DdListA^buildVld2DdListB^\"}\"\tis TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; export 4:4; }\n\n@define Vld2DdList \"(c0811=3 | c0811=8 | c0811=9)\"\n@define thv_Vld2DdList \"(thv_c0811=3 | thv_c0811=8 | thv_c0811=9)\"\n\n:vld2.^esize0607 vld2DdList,RnAligned45\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0607<3 & c0003=15 & $(Vld2DdList) ) |\n\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0607<3 & thv_c0003=15 & $(thv_Vld2DdList) ) ) & RnAligned45 & esize0607 & vld2DdList\n{\n \tmult_addr = RnAligned45;\n \tbuild vld2DdList;\n}\n\n:vld2.^esize0607 vld2DdList,RnAligned45^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0607<3 & c0003=13 & $(Vld2DdList) ) |\n\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0607<3 & thv_c0003=13 & $(thv_Vld2DdList) ) ) & RnAligned45 & esize0607 & vld2DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vld2DdList;\n\tRnAligned45 = RnAligned45 + (8 * vld2DdList);\n}\n\n:vld2.^esize0607 vld2DdList,RnAligned45,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0607<3 & c0003 & $(Vld2DdList) ) |\n\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0607<3 & thv_c0003 & $(thv_Vld2DdList) ) ) & VRm & RnAligned45 & esize0607 & vld2DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vld2DdList;\n\tRnAligned45 = RnAligned45 + VRm;\n}\n\n#######\n# VLD2 (single 2-element structure to one lane)\n#\n\nvld2Index: val\tis TMode=0 & c0507 & c1011\t[ val = c0507 >> c1011; ]\t{ tmp:4 = val; export tmp; }\nvld2Index: val\tis TMode=1 & thv_c0507 & thv_c1011\t[ val = thv_c0507 >> thv_c1011; ]\t{ tmp:4 = val; export tmp; }\n\nvld2DdElement2: Dreg^\"[\"^vld2Index^\"]\"\tis Dreg & vld2Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dreg + vld2Index;\n\t*[register]:1 ptr = *:1 mult_addr;\n}\n\nvld2DdElement2: Dreg^\"[\"^vld2Index^\"]\"\tis Dreg & vld2Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dreg + (vld2Index * 2);\n\t*[register]:2 ptr = *:2 mult_addr;\n}\n\nvld2DdElement2: Dreg^\"[\"^vld2Index^\"]\"\tis Dreg & vld2Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dreg + (vld2Index * 4);\n\t*[register]:4 ptr = *:4 mult_addr;\n}\n\nvld2Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { }\nvld2Align2: \":16\" is TMode=0 & c1011=0 & c0404=1 { }\nvld2Align2: \":32\" is TMode=0 & c1011=1 & c0404=1 { }\nvld2Align2: \":64\" is TMode=0 & c1011=2 & c0405=1 { }\nvld2Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { }\nvld2Align2: \":16\" is TMode=1 & thv_c1011=0 & thv_c0404=1 { }\nvld2Align2: \":32\" is TMode=1 & thv_c1011=1 & thv_c0404=1 { }\nvld2Align2: \":64\" is TMode=1 & thv_c1011=2 & thv_c0405=1 { }\n\nvld2RnAligned2: \"[\"^VRn^vld2Align2^\"]\" \tis VRn & vld2Align2\t{ export VRn; }\n\nbuildVld2DdList2:\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVld2DdList2: vld2DdElement2\tis counter=1 & vld2DdElement2\t\t[ counter=0; regNum=regNum+regInc; ]\n{\n\tbuild vld2DdElement2;\n}\nbuildVld2DdList2: vld2DdElement2,buildVld2DdList2\t\tis vld2DdElement2 & buildVld2DdList2 & esize1011\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tbuild vld2DdElement2;\n\tmult_addr = mult_addr + esize1011;\n\tbuild buildVld2DdList2;\n}\n\nvld2DdList2: \"{\"^buildVld2DdList2^\"}\"\tis TMode=0 & D22 & c1215 & buildVld2DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single\nvld2DdList2: \"{\"^buildVld2DdList2^\"}\"\tis TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVld2DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double\nvld2DdList2: \"{\"^buildVld2DdList2^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & buildVld2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single\nvld2DdList2: \"{\"^buildVld2DdList2^\"}\"\tis TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVld2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double\n\n\n:vld2.^esize1011 vld2DdList2,vld2RnAligned2\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003=15 ) | \n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003=15 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2\n{\n\tmult_addr = vld2RnAligned2;\n\tbuild vld2DdList2;\n}\n\n:vld2.^esize1011 vld2DdList2,vld2RnAligned2^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003=13 ) | \n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003=13 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2\n{\n\tmult_addr = vld2RnAligned2;\n\tbuild vld2DdList2;\n\tvld2RnAligned2 = vld2RnAligned2 + (2 * esize1011);\n}\n\n:vld2.^esize1011 vld2DdList2,vld2RnAligned2,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003 ) | \n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2\n{\n\tmult_addr = vld2RnAligned2;\n\tbuild vld2DdList2;\n\tvld2RnAligned2 = vld2RnAligned2 + VRm;\n}\n\n#######\n# VLD2 (single 2-element structure to all lanes)\n#\nvld234Replicate:\tis ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0))\n{\n\tval:8 = 0;\n\treplicate1to8(*:1 mult_addr, val);\n\texport val;\n}\nvld234Replicate:\tis ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1))\n{\n\tval:8 = 0;\n\treplicate2to8(*:2 mult_addr, val);\n\texport val;\n}\nvld234Replicate:\tis ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2))\n{\n\tval:8 = 0;\n\treplicate4to8(*:4 mult_addr, val);\n\texport val;\n}\n\nvld2Align3: is TMode=0 & c0404=0 { }\nvld2Align3:\t\":16\" is TMode=0 & c0404=1 & c0607=0 { }\nvld2Align3: \":32\" is TMode=0 & c0404=1 & c0607=1 { }\nvld2Align3: \":64\" is TMode=0 & c0404=1 & c0607=2 { }\nvld2Align3: is TMode=1 & thv_c0404=0 { }\nvld2Align3:\t\":16\" is TMode=1 & thv_c0404=1 & thv_c0607=0 { }\nvld2Align3: \":32\" is TMode=1 & thv_c0404=1 & thv_c0607=1 { }\nvld2Align3: \":64\" is TMode=1 & thv_c0404=1 & thv_c0607=2 { }\n\nvld2RnAligned3: \"[\"^VRn^vld2Align3^\"]\" \tis VRn & vld2Align3\t{ export VRn; }\n\nbuildVld234DdList3:\t\t\t\t\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVld234DdList3: Dreg^\"[]\"\t\t\t\t\t\t\tis counter=1 & Dreg\t& vld234Replicate\t[ counter=0; regNum=regNum+regInc; ]\n{\n\tDreg = vld234Replicate;\n}\nbuildVld234DdList3: Dreg^\"[]\",buildVld234DdList3\t\tis Dreg & buildVld234DdList3 & vld234Replicate & esize0607\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tDreg = vld234Replicate;\n\tmult_addr = mult_addr + esize0607;\n\tbuild buildVld234DdList3;\n}\n\nvld2DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=0 & c0505=0 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single\nvld2DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=0 & c0505=1 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double\nvld2DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single\nvld2DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double\n\n:vld2.^esize0607 vld2DdList3,vld2RnAligned3\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003=15 ) | \n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003=15 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3\n{\n\tmult_addr = vld2RnAligned3;\n\tbuild vld2DdList3;\n}\n\n:vld2.^esize0607 vld2DdList3,vld2RnAligned3^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003=13 ) | \n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003=13 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3\n{\n\tmult_addr = vld2RnAligned3;\n\tbuild vld2DdList3;\n\tvld2RnAligned3 = vld2RnAligned3 + 2 * esize0607;\n}\n\n:vld2.^esize0607 vld2DdList3,vld2RnAligned3,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003) | \n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3\n{\n\tmult_addr = vld2RnAligned3;\n\tbuild vld2DdList3;\n\tvld2RnAligned3 = vld2RnAligned3 + VRm;\n}\n\n#######\n# VLD3 (multiple 3-element structures)\n#\nvld3Align: is TMode=0 & c0404=0 { }\nvld3Align: \":64\" is TMode=0 & c0404=1 { }\nvld3Align: is TMode=1 & thv_c0404=0 { }\nvld3Align: \":64\" is TMode=1 & thv_c0404=1 { }\n\n\nvld3RnAligned: \"[\"^VRn^vld3Align^\"]\" \tis VRn & vld3Align\t{ export VRn; }\n\nvld3Dd: Dreg\t\tis (($(AMODE) & c0607=0) | ($(TMODE_F) & thv_c0607=0)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 8;\n\n\t*[register]:1 ptr1 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\t*[register]:1 ptr2 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\t*[register]:1 ptr3 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 1;\n\tptr2 = ptr2 + 1;\n\tptr3 = ptr3 + 1;\n\tgoto ;\n\n}\nvld3Dd: Dreg\t\tis (($(AMODE) & c0607=1) | ($(TMODE_F) & thv_c0607=1)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 4;\n\n\t*[register]:2 ptr1 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\t*[register]:2 ptr2 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\t*[register]:2 ptr3 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 2;\n\tptr2 = ptr2 + 2;\n\tptr3 = ptr3 + 2;\n\tgoto ;\n\n}\nvld3Dd: Dreg\t\tis (($(AMODE) & c0607=2) | ($(TMODE_F) & thv_c0607=2)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 2;\n\n\t*[register]:4 ptr1 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\t*[register]:4 ptr2 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\t*[register]:4 ptr3 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 4;\n\tptr2 = ptr2 + 4;\n\tptr3 = ptr3 + 4;\n\tgoto ;\n\n}\n\n# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start\nbuildVld3DdList:\t\t\t\t\t\t\tis counter=0 & vld3Dd\t[ regNum=regNum-3*regInc; ]\n{\n\tbuild vld3Dd;\n}\nbuildVld3DdList: Dreg^buildVld3DdList\t\tis counter=1 & Dreg\t& buildVld3DdList\t[ counter=0; regNum=regNum+regInc; ] { }\nbuildVld3DdList: Dreg,buildVld3DdList\t\tis Dreg & buildVld3DdList\t[ counter=counter-1; regNum=regNum+regInc; ] { }\n\nvld3DdList: \"{\"^buildVld3DdList^\"}\"\tis TMode=0 & c0811=4 & D22 & c1215 & buildVld3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single\nvld3DdList: \"{\"^buildVld3DdList^\"}\"\tis TMode=0 & c0811=5 & D22 & c1215 & buildVld3DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double\nvld3DdList: \"{\"^buildVld3DdList^\"}\"\tis TMode=1 & thv_c0811=4 & thv_D22 & thv_c1215 & buildVld3DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single\nvld3DdList: \"{\"^buildVld3DdList^\"}\"\tis TMode=1 & thv_c0811=5 & thv_D22 & thv_c1215 & buildVld3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double\n\n:vld3.^esize0607 vld3DdList,vld3RnAligned\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 & c0003=15 ) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=15) ) & vld3RnAligned & esize0607 & vld3DdList\n{\n\tmult_addr = vld3RnAligned;\n\tbuild vld3DdList;\n}\n\n:vld3.^esize0607 vld3DdList,vld3RnAligned^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 & c0003=13 ) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=13) ) & vld3RnAligned & esize0607 & vld3DdList\n{\n\tmult_addr = vld3RnAligned;\n\tbuild vld3DdList;\n\tvld3RnAligned = vld3RnAligned + (8 * 3);\n}\n\n:vld3.^esize0607 vld3DdList,vld3RnAligned,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 ) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 ) ) & VRm & vld3RnAligned & esize0607 & vld3DdList\n{\n\tmult_addr = vld3RnAligned;\n\tbuild vld3DdList;\n\tvld3RnAligned = vld3RnAligned + VRm;\n}\n\n#######\n# VLD3 (single 3-element structure to one lane)\n#\n\nvld3Index: val\tis TMode=0 & c0507 & c1011\t[ val = c0507 >> c1011; ]\t{ tmp:4 = val; export tmp; }\nvld3Index: val\tis TMode=1 & thv_c0507 & thv_c1011\t[ val = thv_c0507 >> thv_c1011; ]\t{ tmp:4 = val; export tmp; }\n\nvld3DdElement2: Dreg^\"[\"^vld3Index^\"]\"\tis Dreg & vld3Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dreg + vld3Index;\n\t*[register]:1 ptr = *:1 mult_addr;\n}\n\nvld3DdElement2: Dreg^\"[\"^vld3Index^\"]\"\tis Dreg & vld3Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dreg + (vld3Index * 2);\n\t*[register]:2 ptr = *:2 mult_addr;\n}\n\nvld3DdElement2: Dreg^\"[\"^vld3Index^\"]\"\tis Dreg & vld3Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dreg + (vld3Index * 4);\n\t*[register]:4 ptr = *:4 mult_addr;\n}\n\nvld3Rn: \"[\"^VRn^\"]\" \tis VRn { export VRn; }\n\nbuildVld3DdList2:\t\t\t\t\t\t\t\t\t\tis counter=0\t\t\t\t\t\t\t{ }\nbuildVld3DdList2: vld3DdElement2\t\t\t\t\t\tis counter=1 & vld3DdElement2\t\t\t[ counter=0; regNum=regNum+regInc; ]\n{\n\tbuild vld3DdElement2;\n}\nbuildVld3DdList2: vld3DdElement2,buildVld3DdList2\t\tis vld3DdElement2 & buildVld3DdList2 & esize1011\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tbuild vld3DdElement2;\n\tmult_addr = mult_addr + esize1011;\n\tbuild buildVld3DdList2;\n}\n\nvld3DdList2: \"{\"^buildVld3DdList2^\"}\"\tis TMode=0 & D22 & c1215 & buildVld3DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single\nvld3DdList2: \"{\"^buildVld3DdList2^\"}\"\tis TMode=0 & ((c1011=1 & c0405=2) | (c1011=2 & c0406=4)) & D22 & c1215 & buildVld3DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double\nvld3DdList2: \"{\"^buildVld3DdList2^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & buildVld3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single\nvld3DdList2: \"{\"^buildVld3DdList2^\"}\"\tis TMode=1 & ((thv_c1011=1 & thv_c0405=2) | (thv_c1011=2 & thv_c0406=4)) & thv_D22 & thv_c1215 & buildVld3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double\n\n\n:vld3.^esize1011 vld3DdList2,vld3Rn\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2 & c0003=15) |\n\t\t\t\t\t\t\t\t\t\t\t ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15) ) & vld3Rn & esize1011 & vld3DdList2\n{\n\tmult_addr = vld3Rn;\n\tbuild vld3DdList2;\n}\n\n:vld3.^esize1011 vld3DdList2,vld3Rn^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2 & c0003=13) |\n\t\t\t\t\t\t\t\t\t\t\t ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13) ) & vld3Rn & esize1011 & vld3DdList2\n{\n\tmult_addr = vld3Rn;\n\tbuild vld3DdList2;\n\tvld3Rn = vld3Rn + (3 * esize1011);\n}\n\n\n:vld3.^esize1011 vld3DdList2,vld3Rn,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2) |\n\t\t\t\t\t\t\t\t\t\t\t ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2) ) & VRm & vld3Rn & esize1011 & vld3DdList2\n{\n\tmult_addr = vld3Rn;\n\tbuild vld3DdList2;\n\tvld3Rn = vld3Rn + VRm;\n}\n\n#######\n# VLD3 (single 3-element structure to all lanes)\n#\n\nvld3DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=0 & c0505=0 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single\nvld3DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=0 & c0505=1 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double\nvld3DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single\nvld3DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double\n\n:vld3.^esize0607 vld3DdList3,vld3Rn\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0 & c0003=15) |\n\t\t\t\t\t\t\t\t\t\t\t( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=15) ) & vld3Rn & esize0607 & vld3DdList3\n{\n\tmult_addr = vld3Rn;\n\tbuild vld3DdList3;\n}\n\n:vld3.^esize0607 vld3DdList3,vld3Rn^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0 & c0003=13) |\n\t\t\t\t\t\t\t\t\t\t\t( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=13) ) & vld3Rn & esize0607 & vld3DdList3\n{\n\tmult_addr = vld3Rn;\n\tbuild vld3DdList3;\n\tvld3Rn = vld3Rn + 3 * esize0607;\n}\n\n:vld3.^esize0607 vld3DdList3,vld3Rn,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0) |\n\t\t\t\t\t\t\t\t\t\t\t( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0) ) & VRm & vld3Rn & esize0607 & vld3DdList3\n{\n\tmult_addr = vld3Rn;\n\tbuild vld3DdList3;\n\tvld3Rn = vld3Rn + VRm;\n}\n\n\n#######\n# VLD4 (single 4-element structure to one lane)\n#\n\nvld4Index: val\tis TMode=0 & c0507 & c1011\t[ val = c0507 >> c1011; ]\t{ tmp:4 = val; export tmp; }\nvld4Index: val\tis TMode=1 & thv_c0507 & thv_c1011\t[ val = thv_c0507 >> thv_c1011; ]\t{ tmp:4 = val; export tmp; }\n\nvld4DdElement2: Dreg^\"[\"^vld4Index^\"]\"\tis Dreg & vld4Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dreg + vld4Index;\n\t*[register]:1 ptr = *:1 mult_addr;\n}\n\nvld4DdElement2: Dreg^\"[\"^vld4Index^\"]\"\tis Dreg & vld4Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dreg + vld4Index;\n\t*[register]:2 ptr = *:2 mult_addr;\n}\n\nvld4DdElement2: Dreg^\"[\"^vld4Index^\"]\"\tis Dreg & vld4Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dreg + vld4Index;\n\t*[register]:4 ptr = *:4 mult_addr;\n}\n\nvld4Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { }\nvld4Align2: \":32\" is TMode=0 & c1011=0 & c0404=1 { }\nvld4Align2: \":64\" is TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1)) { }\nvld4Align2: \":128\" is TMode=0 & c1011=2 & c0405=2 { }\nvld4Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { }\nvld4Align2: \":32\" is TMode=1 & thv_c1011=0 & thv_c0404=1 { }\nvld4Align2: \":64\" is TMode=1 & ((thv_c1011=1 & thv_c0404=1) | (thv_c1011=2 & thv_c0405=1)) { }\nvld4Align2: \":128\" is TMode=1 & thv_c1011=2 & thv_c0405=2 { }\n\nvld4RnAligned2: \"[\"^VRn^vld4Align2^\"]\" \tis VRn & vld4Align2\t{ export VRn; }\n\nbuildVld4DdList2:\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVld4DdList2: vld4DdElement2\tis counter=1 & vld4DdElement2\t\t[ counter=0; regNum=regNum+regInc; ] { build vld4DdElement2; }\nbuildVld4DdList2: vld4DdElement2,buildVld4DdList2\t\tis vld4DdElement2 & buildVld4DdList2 & esize1011\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tbuild vld4DdElement2;\n\tmult_addr = mult_addr + esize1011;\n\tbuild buildVld4DdList2;\n}\n\nvld4DdList2: \"{\"^buildVld4DdList2^\"}\"\tis TMode=0 & D22 & c1215 & buildVld4DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single\nvld4DdList2: \"{\"^buildVld4DdList2^\"}\"\tis TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVld4DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double\nvld4DdList2: \"{\"^buildVld4DdList2^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & buildVld4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single\nvld4DdList2: \"{\"^buildVld4DdList2^\"}\"\tis TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVld4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double\n\n\n:vld4.^esize1011 vld4DdList2,vld4RnAligned2\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=3 & c0003=15) |\n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=3 & thv_c0003=15 ) ) & esize1011 & vld4RnAligned2 & vld4DdList2\n{\n\tmult_addr = vld4RnAligned2;\n\tbuild vld4DdList2;\n}\n\n:vld4.^esize1011 vld4DdList2,vld4RnAligned2^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=3 & c0003=13) |\n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=3 & thv_c0003=13 ) ) & esize1011 & vld4RnAligned2 & vld4DdList2\n{\n\tmult_addr = vld4RnAligned2;\n\tbuild vld4DdList2;\n\tvld4RnAligned2 = vld4RnAligned2 + (4 * esize1011);\n}\n\n:vld4.^esize1011 vld4DdList2,vld4RnAligned2,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=3 & c0003) |\n\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=3 & thv_c0003 ) ) & esize1011 & VRm & vld4RnAligned2 & vld4DdList2\n {\n\tmult_addr = vld4RnAligned2;\n\tbuild vld4DdList2;\n\tvld4RnAligned2 = vld4RnAligned2 + VRm;\n}\n\n#######\n# VLD4 (single 4-element structure to all lanes)\n#\n\nvld4size0607: \"8\" is TMode=0 & c0607=0 { export 1:4; }\nvld4size0607: \"16\" is TMode=0 & c0607=1 { export 2:4; }\nvld4size0607: \"32\" is TMode=0 & c0607=2 { export 4:4; }\nvld4size0607: \"32\" is TMode=0 & c0607=3 { export 4:4; } # see VLD4 (single 4-element structure to all lanes)\nvld4size0607: \"8\" is TMode=1 & thv_c0607=0 { export 1:4; }\nvld4size0607: \"16\" is TMode=1 & thv_c0607=1 { export 2:4; }\nvld4size0607: \"32\" is TMode=1 & thv_c0607=2 { export 4:4; }\nvld4size0607: \"32\" is TMode=1 & thv_c0607=3 { export 4:4; } # see VLD4 (single 4-element structure to all lanes)\n\nvld4Align3: is TMode=0 & c0404=0 { }\nvld4Align3: \":32\" is TMode=0 & c0404=1 & c0607=0 { }\nvld4Align3: \":64\" is TMode=0 & c0404=1 & (c0607=1 | c0607=2) { }\nvld4Align3: \":128\" is TMode=0 & c0404=1 & c0607=3 { }\nvld4Align3: is TMode=1 & thv_c0404=0 { }\nvld4Align3: \":32\" is TMode=1 & thv_c0404=1 & thv_c0607=0 { }\nvld4Align3: \":64\" is TMode=1 & thv_c0404=1 & (thv_c0607=1 | thv_c0607=2) { }\nvld4Align3: \":128\" is TMode=1 & thv_c0404=1 & thv_c0607=3 { }\n\nvld4RnAligned3: \"[\"^VRn^vld4Align3^\"]\" \tis VRn & vld4Align3\t{ export VRn; }\n\nvld4DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=0 & c0505=0 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single\nvld4DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=0 & c0505=1 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double\nvld4DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single\nvld4DdList3: \"{\"^buildVld234DdList3^\"}\"\tis TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double\n\n:vld4.^vld4size0607 vld4DdList3,vld4RnAligned3\t\tis ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=0xf & c0003=0xf) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=0xf & thv_c0003=0xf) & vld4size0607 & vld4RnAligned3 & vld4DdList3\n{\n\tmult_addr = vld4RnAligned3;\n\tbuild vld4DdList3;\n}\n\n:vld4.^vld4size0607 vld4DdList3,vld4RnAligned3^\"!\"\tis ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=0xf & c0003=0xd) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=0xf & thv_c0003=0xd) & vld4size0607 & vld4RnAligned3 & vld4DdList3\n{\n\tmult_addr = vld4RnAligned3;\n\tbuild vld4DdList3;\n\tvld4RnAligned3 = vld4RnAligned3 + (4 * vld4size0607);\n}\n\n:vld4.^vld4size0607 vld4DdList3,vld4RnAligned3,VRm\tis ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=0xf) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=0xf) & vld4size0607 & VRm & vld4RnAligned3 & vld4DdList3\n{\n\tmult_addr = vld4RnAligned3;\n\tbuild vld4DdList3;\n\tvld4RnAligned3 = vld4RnAligned3 + VRm;\n}\n\n#######\n# VLD4 (multiple 4-element structures)\n#\n\nvld4Align: is TMode=0 & c0405=0 { }\nvld4Align: \":64\" is TMode=0 & c0405=1 { }\nvld4Align: \":128\" is TMode=0 & c0405=2 { }\nvld4Align: \":256\" is TMode=0 & c0405=3 { }\nvld4Align: is TMode=1 & thv_c0405=0 { }\nvld4Align: \":64\" is TMode=1 & thv_c0405=1 { }\nvld4Align: \":128\" is TMode=1 & thv_c0405=2 { }\nvld4Align: \":256\" is TMode=1 & thv_c0405=3 { }\n\nvld4RnAligned: \"[\"^VRn^vld4Align^\"]\" \tis VRn & vld4Align\t{ export VRn; }\n\nvld4Dd: Dreg\t\tis (($(AMODE) & c0607=0) | ($(TMODE_F) & thv_c0607=0)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n\tptr4:4 = &Dreg + (regInc * 24);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n\tptr4:4 = &Dreg - (regInc * 24);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 8;\n\n\t*[register]:1 ptr1 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\t*[register]:1 ptr2 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\t*[register]:1 ptr3 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\t*[register]:1 ptr4 = *:1 mult_addr;\n\tmult_addr = mult_addr + 1;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 1;\n\tptr2 = ptr2 + 1;\n\tptr3 = ptr3 + 1;\n\tptr4 = ptr4 + 1;\n\tgoto ;\n\n}\nvld4Dd: Dreg\t\tis (($(AMODE) & c0607=1) | ($(TMODE_F) & thv_c0607=1)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n\tptr4:4 = &Dreg + (regInc * 24);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n\tptr4:4 = &Dreg - (regInc * 24);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 4;\n\n\t*[register]:2 ptr1 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\t*[register]:2 ptr2 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\t*[register]:2 ptr3 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\t*[register]:2 ptr4 = *:2 mult_addr;\n\tmult_addr = mult_addr + 2;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 2;\n\tptr2 = ptr2 + 2;\n\tptr3 = ptr3 + 2;\n\tptr4 = ptr4 + 2;\n\tgoto ;\n\n}\nvld4Dd: Dreg\t\tis (($(AMODE) & c0607=2) | ($(TMODE_F) & thv_c0607=2)) & Dreg & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n\tptr4:4 = &Dreg + (regInc * 24);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n\tptr4:4 = &Dreg - (regInc * 24);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 2;\n\n\t*[register]:4 ptr1 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\t*[register]:4 ptr2 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\t*[register]:4 ptr3 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\t*[register]:4 ptr4 = *:4 mult_addr;\n\tmult_addr = mult_addr + 4;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 4;\n\tptr2 = ptr2 + 4;\n\tptr3 = ptr3 + 4;\n\tptr4 = ptr4 + 4;\n\tgoto ;\n\n}\n\n# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start\nbuildVld4DdList:\t\t\t\t\t\t\tis counter=0 & vld4Dd\t[ regNum=regNum-4*regInc; ]\n{\n\tbuild vld4Dd;\n}\nbuildVld4DdList: Dreg^buildVld4DdList\t\tis counter=1 & Dreg & buildVld4DdList\t\t[ counter=0; regNum=regNum+regInc; ] { }\nbuildVld4DdList: Dreg,buildVld4DdList\t\tis Dreg & buildVld4DdList\t[ counter=counter-1; regNum=regNum+regInc; ] { }\n\nvld4DdList: \"{\"^buildVld4DdList^\"}\"\tis TMode=0 & c0808=0 & D22 & c1215 & buildVld4DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single\nvld4DdList: \"{\"^buildVld4DdList^\"}\"\tis TMode=0 & c0808=1 & D22 & c1215 & buildVld4DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double\nvld4DdList: \"{\"^buildVld4DdList^\"}\"\tis TMode=1 & thv_c0808=0 & thv_D22 & thv_c1215 & buildVld4DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single\nvld4DdList: \"{\"^buildVld4DdList^\"}\"\tis TMode=1 & thv_c0808=1 & thv_D22 & thv_c1215 & buildVld4DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double\n\n:vld4.^esize0607 vld4DdList,vld4RnAligned\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3 & c0003=15 ) | \n\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList\n{\n\tmult_addr = vld4RnAligned;\n\tbuild vld4DdList;\n}\n\n:vld4.^esize0607 vld4DdList,vld4RnAligned^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3 & c0003=13 ) | \n\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList\n{\n\tmult_addr = vld4RnAligned;\n\tbuild vld4DdList;\n\tvld4RnAligned = vld4RnAligned + (8 * 4);\n}\n\n:vld4.^esize0607 vld4DdList,vld4RnAligned,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3) | \n\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList\n{\n\tmult_addr = vld4RnAligned;\n\tbuild vld4DdList;\n\tvld4RnAligned = vld4RnAligned + VRm;\n}\n\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\n#######\n# VLDM (A1)\n#\n\nvldmRn: Rn\t\tis TMode=0 & Rn & c2121=0\t\t{ export Rn; }\nvldmRn: Rn^\"!\"\tis TMode=0 & Rn & c2121=1\t\t{ export Rn; }\nvldmRn: thv_Rn\t\tis TMode=1 & thv_Rn & thv_c2121=0\t\t{ export thv_Rn; }\nvldmRn: thv_Rn^\"!\"\tis TMode=1 & thv_Rn & thv_c2121=1\t\t{ export thv_Rn; }\nvldmOffset: value is $(AMODE) & immed [ value= immed << 2; ]\t\t{ export *[const]:4 value; }\nvldmOffset: value is TMode=1 & thv_immed [ value= thv_immed << 2; ]\t{ export *[const]:4 value; }\nvldmUpdate: immed is TMode=0 & vldmRn & c2121=0 & immed { }\nvldmUpdate: immed is TMode=0 & vldmRn & c2121=1 & immed { vldmRn = vldmRn + (immed << 2); }\nvldmUpdate: thv_immed is TMode=1 & vldmRn & thv_c2121=0 & thv_immed { }\nvldmUpdate: thv_immed is TMode=1 & vldmRn & thv_c2121=1 & thv_immed { vldmRn = vldmRn + (thv_immed << 2); }\n\nbuildVldmDdList:\t\t\t\t\t\tis counter=0\t\t\t\t{ }\nbuildVldmDdList: Dreg\t\t\t\t\tis counter=1 & Dreg\t\t[ counter=0; regNum=regNum+1; ]\n{\n\tDreg = *mult_addr;\n\tmult_addr = mult_addr + 8;\n}\n\nbuildVldmDdList: Dreg,buildVldmDdList\tis Dreg & buildVldmDdList\t[ counter=counter-1; regNum=regNum+1; ]\n{\n\tDreg = *mult_addr;\n\tmult_addr = mult_addr + 8;\n\tbuild buildVldmDdList;\n}\n\nvldmDdList: \"{\"^buildVldmDdList^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVldmDdList [ regNum=(D22<<4)+c1215 - 1; counter=c0007>>1; ] { }\nvldmDdList: \"{\"^buildVldmDdList^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmDdList [ regNum=(thv_D22<<4)+thv_c1215 - 1; counter=thv_c0007>>1; ] { }\n\n:vldmia^COND vldmRn,vldmDdList\tis ( ($(AMODE) & c2327=0x19 & c2121 & c2020=1 & c0811=11 & c0000=0) | \n ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0) ) & COND & vldmRn & vldmDdList & vldmOffset & vldmUpdate\n{\n\tmult_addr = vldmRn;\n\tbuild vldmDdList;\n\tbuild vldmUpdate;\n}\n\n:vldmdb^COND vldmRn,vldmDdList\tis ( ($(AMODE) & c2327=0x1a & c2121=1 & c2020=1 & c0811=11 & c0000=0) |\n ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0 ) ) & COND & vldmRn & vldmDdList & vldmOffset\n{\n\tlocal start_addr = vldmRn - vldmOffset;\n\tmult_addr = start_addr;\n\tbuild vldmDdList;\n\tvldmRn = start_addr;\n}\n\n@endif # VFPv2 | VFPv3 | SIMD\n\n@if defined(VERSION_8)\n\nwith : TMode=0 {\nfldmSet1: Dd_1 is Rn & Dd_1 { Dd_1 = * Rn; }\nfldmSet2: Dd_2 is Rn & Dd_2 & fldmSet1 { build fldmSet1; Dd_2 = *:8 (Rn + 8:4); }\nfldmSet3: Dd_3 is Rn & Dd_3 & fldmSet2 { build fldmSet2; Dd_3 = *:8 (Rn + 16:4); }\nfldmSet4: Dd_4 is Rn & Dd_4 & fldmSet3 { build fldmSet3; Dd_4 = *:8 (Rn + 24:4); }\nfldmSet5: Dd_5 is Rn & Dd_5 & fldmSet4 { build fldmSet4; Dd_5 = *:8 (Rn + 32:4); }\nfldmSet6: Dd_6 is Rn & Dd_6 & fldmSet5 { build fldmSet5; Dd_6 = *:8 (Rn + 40:4); }\nfldmSet7: Dd_7 is Rn & Dd_7 & fldmSet6 { build fldmSet6; Dd_7 = *:8 (Rn + 48:4); }\nfldmSet8: Dd_8 is Rn & Dd_8 & fldmSet7 { build fldmSet7; Dd_8 = *:8 (Rn + 56:4); }\nfldmSet9: Dd_9 is Rn & Dd_9 & fldmSet8 { build fldmSet8; Dd_9 = *:8 (Rn + 64:4); }\nfldmSet10: Dd_10 is Rn & Dd_10 & fldmSet9 { build fldmSet9; Dd_10 = *:8 (Rn + 72:4); }\nfldmSet11: Dd_11 is Rn & Dd_11 & fldmSet10 { build fldmSet10; Dd_11 = *:8 (Rn + 80:4); }\nfldmSet12: Dd_12 is Rn & Dd_12 & fldmSet11 { build fldmSet11; Dd_12 = *:8 (Rn + 88:4); }\nfldmSet13: Dd_13 is Rn & Dd_13 & fldmSet12 { build fldmSet12; Dd_13 = *:8 (Rn + 96:4); }\nfldmSet14: Dd_14 is Rn & Dd_14 & fldmSet13 { build fldmSet13; Dd_14 = *:8 (Rn + 104:4); }\nfldmSet15: Dd_15 is Rn & Dd_15 & fldmSet14 { build fldmSet14; Dd_15 = *:8 (Rn + 112:4); }\nfldmSet16: Dd_16 is Rn & Dd_16 & fldmSet15 { build fldmSet15; Dd_16 = *:8 (Rn + 120:4); }\n\nfldmSet: \"{\"^Dd_1^\"}\" is Dd_1 & c0007=3 & fldmSet1 { build fldmSet1; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet2^\"}\" is Dd_1 & c0007=5 & fldmSet2 { build fldmSet2; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet3^\"}\" is Dd_1 & c0007=7 & fldmSet3 { build fldmSet3; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet4^\"}\" is Dd_1 & c0007=9 & fldmSet4 { build fldmSet4; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet5^\"}\" is Dd_1 & c0007=11 & fldmSet5 { build fldmSet5; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet6^\"}\" is Dd_1 & c0007=13 & fldmSet6 { build fldmSet6; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet7^\"}\" is Dd_1 & c0007=15 & fldmSet7 { build fldmSet7; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet8^\"}\" is Dd_1 & c0007=17 & fldmSet8 { build fldmSet8; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet9^\"}\" is Dd_1 & c0007=19 & fldmSet9 { build fldmSet9; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet10^\"}\" is Dd_1 & c0007=21 & fldmSet10 { build fldmSet10; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet11^\"}\" is Dd_1 & c0007=23 & fldmSet11 { build fldmSet11; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet12^\"}\" is Dd_1 & c0007=25 & fldmSet12 { build fldmSet12; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet13^\"}\" is Dd_1 & c0007=27 & fldmSet13 { build fldmSet13; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet14^\"}\" is Dd_1 & c0007=29 & fldmSet14 { build fldmSet14; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet15^\"}\" is Dd_1 & c0007=31 & fldmSet15 { build fldmSet15; }\nfldmSet: \"{\"^Dd_1^\"-\"^fldmSet16^\"}\" is Dd_1 & c0007=33 & fldmSet16 { build fldmSet16; }\n\n\nfldmWback: Rn^\"!\" is c2121=1 & c2323=1 & c0007 & Rn { Rn = Rn + (4 * c0007:4); }\nfldmWback: Rn^\"!\" is c2121=1 & c2323=0 & c0007 & Rn { Rn = Rn - (4 * c0007:4); }\nfldmWback: Rn is c2121=0 & Rn { }\n}\n\nwith : TMode=1 {\nfldmSet1: thv_Dd_1 is thv_Rn & thv_Dd_1 { thv_Dd_1 = * thv_Rn; }\nfldmSet2: thv_Dd_2 is thv_Rn & thv_Dd_2 & fldmSet1 { build fldmSet1; thv_Dd_2 = *:8 (thv_Rn + 8:4); }\nfldmSet3: thv_Dd_3 is thv_Rn & thv_Dd_3 & fldmSet2 { build fldmSet2; thv_Dd_3 = *:8 (thv_Rn + 16:4); }\nfldmSet4: thv_Dd_4 is thv_Rn & thv_Dd_4 & fldmSet3 { build fldmSet3; thv_Dd_4 = *:8 (thv_Rn + 24:4); }\nfldmSet5: thv_Dd_5 is thv_Rn & thv_Dd_5 & fldmSet4 { build fldmSet4; thv_Dd_5 = *:8 (thv_Rn + 32:4); }\nfldmSet6: thv_Dd_6 is thv_Rn & thv_Dd_6 & fldmSet5 { build fldmSet5; thv_Dd_6 = *:8 (thv_Rn + 40:4); }\nfldmSet7: thv_Dd_7 is thv_Rn & thv_Dd_7 & fldmSet6 { build fldmSet6; thv_Dd_7 = *:8 (thv_Rn + 48:4); }\nfldmSet8: thv_Dd_8 is thv_Rn & thv_Dd_8 & fldmSet7 { build fldmSet7; thv_Dd_8 = *:8 (thv_Rn + 56:4); }\nfldmSet9: thv_Dd_9 is thv_Rn & thv_Dd_9 & fldmSet8 { build fldmSet8; thv_Dd_9 = *:8 (thv_Rn + 64:4); }\nfldmSet10: thv_Dd_10 is thv_Rn & thv_Dd_10 & fldmSet9 { build fldmSet9; thv_Dd_10 = *:8 (thv_Rn + 72:4); }\nfldmSet11: thv_Dd_11 is thv_Rn & thv_Dd_11 & fldmSet10 { build fldmSet10; thv_Dd_11 = *:8 (thv_Rn + 80:4); }\nfldmSet12: thv_Dd_12 is thv_Rn & thv_Dd_12 & fldmSet11 { build fldmSet11; thv_Dd_12 = *:8 (thv_Rn + 88:4); }\nfldmSet13: thv_Dd_13 is thv_Rn & thv_Dd_13 & fldmSet12 { build fldmSet12; thv_Dd_13 = *:8 (thv_Rn + 96:4); }\nfldmSet14: thv_Dd_14 is thv_Rn & thv_Dd_14 & fldmSet13 { build fldmSet13; thv_Dd_14 = *:8 (thv_Rn + 104:4); }\nfldmSet15: thv_Dd_15 is thv_Rn & thv_Dd_15 & fldmSet14 { build fldmSet14; thv_Dd_15 = *:8 (thv_Rn + 112:4); }\nfldmSet16: thv_Dd_16 is thv_Rn & thv_Dd_16 & fldmSet15 { build fldmSet15; thv_Dd_16 = *:8 (thv_Rn + 120:4); }\n\nfldmSet: \"{\"^thv_Dd_1^\"}\" is thv_Dd_1 & thv_c0007=3 & fldmSet1 { build fldmSet1; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet2^\"}\" is thv_Dd_1 & thv_c0007=5 & fldmSet2 { build fldmSet2; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet3^\"}\" is thv_Dd_1 & thv_c0007=7 & fldmSet3 { build fldmSet3; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet4^\"}\" is thv_Dd_1 & thv_c0007=9 & fldmSet4 { build fldmSet4; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet5^\"}\" is thv_Dd_1 & thv_c0007=11 & fldmSet5 { build fldmSet5; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet6^\"}\" is thv_Dd_1 & thv_c0007=13 & fldmSet6 { build fldmSet6; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet7^\"}\" is thv_Dd_1 & thv_c0007=15 & fldmSet7 { build fldmSet7; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet8^\"}\" is thv_Dd_1 & thv_c0007=17 & fldmSet8 { build fldmSet8; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet9^\"}\" is thv_Dd_1 & thv_c0007=19 & fldmSet9 { build fldmSet9; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet10^\"}\" is thv_Dd_1 & thv_c0007=21 & fldmSet10 { build fldmSet10; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet11^\"}\" is thv_Dd_1 & thv_c0007=23 & fldmSet11 { build fldmSet11; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet12^\"}\" is thv_Dd_1 & thv_c0007=25 & fldmSet12 { build fldmSet12; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet13^\"}\" is thv_Dd_1 & thv_c0007=27 & fldmSet13 { build fldmSet13; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet14^\"}\" is thv_Dd_1 & thv_c0007=29 & fldmSet14 { build fldmSet14; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet15^\"}\" is thv_Dd_1 & thv_c0007=31 & fldmSet15 { build fldmSet15; }\nfldmSet: \"{\"^thv_Dd_1^\"-\"^fldmSet16^\"}\" is thv_Dd_1 & thv_c0007=33 & fldmSet16 { build fldmSet16; }\n\n\nfldmWback: thv_Rn^\"!\" is thv_bit21=1 & thv_bit23=1 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn + (4 * thv_c0007:4); }\nfldmWback: thv_Rn^\"!\" is thv_bit21=1 & thv_bit23=0 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn - (4 * thv_c0007:4); }\nfldmWback: thv_Rn is thv_bit21=0 & thv_Rn { }\n}\n\n:fldmdbx^COND fldmWback, fldmSet is $(AMODE) & COND & ARMcond=1 & c2327=0x1a & c2021=3 & c0811=0xb & c0000=1 & fldmWback & fldmSet\n{\n\tbuild fldmWback;\n\tbuild fldmSet;\n}\n\n:fldmiax^COND fldmWback, fldmSet is $(AMODE) & COND & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=0xb & c0000=1 & fldmWback & fldmSet\n{\n\tbuild fldmSet;\n\tbuild fldmWback;\n}\n\n:fldmdbx^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0x1da & thv_c2021=3 & thv_c0811=0xb & fldmWback & fldmSet\n{\n\tbuild fldmWback;\n\tbuild fldmSet;\n}\n\n:fldmiax^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0x1d9 & thv_bit20=1 & thv_c0811=0xb & fldmWback & fldmSet\n{\n\tbuild fldmSet;\n\tbuild fldmWback;\n}\n\nwith : TMode=0 {\nfstmSet1: Dd_1 is Rn & Dd_1 { * Rn = Dd_1; }\nfstmSet2: Dd_2 is Rn & Dd_2 & fstmSet1 { build fstmSet1; *:8 (Rn + 8:4) = Dd_2; }\nfstmSet3: Dd_3 is Rn & Dd_3 & fstmSet2 { build fstmSet2; *:8 (Rn + 16:4) = Dd_3; }\nfstmSet4: Dd_4 is Rn & Dd_4 & fstmSet3 { build fstmSet3; *:8 (Rn + 24:4) = Dd_4; }\nfstmSet5: Dd_5 is Rn & Dd_5 & fstmSet4 { build fstmSet4; *:8 (Rn + 32:4) = Dd_5; }\nfstmSet6: Dd_6 is Rn & Dd_6 & fstmSet5 { build fstmSet5; *:8 (Rn + 40:4) = Dd_6; }\nfstmSet7: Dd_7 is Rn & Dd_7 & fstmSet6 { build fstmSet6; *:8 (Rn + 48:4) = Dd_7; }\nfstmSet8: Dd_8 is Rn & Dd_8 & fstmSet7 { build fstmSet7; *:8 (Rn + 56:4) = Dd_8; }\nfstmSet9: Dd_9 is Rn & Dd_9 & fstmSet8 { build fstmSet8; *:8 (Rn + 64:4) = Dd_9; }\nfstmSet10: Dd_10 is Rn & Dd_10 & fstmSet9 { build fstmSet9; *:8 (Rn + 72:4) = Dd_10; }\nfstmSet11: Dd_11 is Rn & Dd_11 & fstmSet10 { build fstmSet10; *:8 (Rn + 80:4) = Dd_11; }\nfstmSet12: Dd_12 is Rn & Dd_12 & fstmSet11 { build fstmSet11; *:8 (Rn + 88:4) = Dd_12; }\nfstmSet13: Dd_13 is Rn & Dd_13 & fstmSet12 { build fstmSet12; *:8 (Rn + 96:4) = Dd_13; }\nfstmSet14: Dd_14 is Rn & Dd_14 & fstmSet13 { build fstmSet13; *:8 (Rn + 104:4) = Dd_14; }\nfstmSet15: Dd_15 is Rn & Dd_15 & fstmSet14 { build fstmSet14; *:8 (Rn + 112:4) = Dd_15; }\nfstmSet16: Dd_16 is Rn & Dd_16 & fstmSet15 { build fstmSet15; *:8 (Rn + 120:4) = Dd_16; }\n\nfstmSet: \"{\"^Dd_1^\"}\" is Dd_1 & c0007=3 & fstmSet1 { build fstmSet1; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet2^\"}\" is Dd_1 & c0007=5 & fstmSet2 { build fstmSet2; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet3^\"}\" is Dd_1 & c0007=7 & fstmSet3 { build fstmSet3; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet4^\"}\" is Dd_1 & c0007=9 & fstmSet4 { build fstmSet4; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet5^\"}\" is Dd_1 & c0007=11 & fstmSet5 { build fstmSet5; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet6^\"}\" is Dd_1 & c0007=13 & fstmSet6 { build fstmSet6; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet7^\"}\" is Dd_1 & c0007=15 & fstmSet7 { build fstmSet7; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet8^\"}\" is Dd_1 & c0007=17 & fstmSet8 { build fstmSet8; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet9^\"}\" is Dd_1 & c0007=19 & fstmSet9 { build fstmSet9; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet10^\"}\" is Dd_1 & c0007=21 & fstmSet10 { build fstmSet10; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet11^\"}\" is Dd_1 & c0007=23 & fstmSet11 { build fstmSet11; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet12^\"}\" is Dd_1 & c0007=25 & fstmSet12 { build fstmSet12; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet13^\"}\" is Dd_1 & c0007=27 & fstmSet13 { build fstmSet13; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet14^\"}\" is Dd_1 & c0007=29 & fstmSet14 { build fstmSet14; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet15^\"}\" is Dd_1 & c0007=31 & fstmSet15 { build fstmSet15; }\nfstmSet: \"{\"^Dd_1^\"-\"^fstmSet16^\"}\" is Dd_1 & c0007=33 & fstmSet16 { build fstmSet16; }\n\n\nfstmWback: Rn^\"!\" is c2121=1 & c2323=1 & c0007 & Rn { Rn = Rn + (4 * c0007:4); }\nfstmWback: Rn^\"!\" is c2121=1 & c2323=0 & c0007 & Rn { Rn = Rn - (4 * c0007:4); }\nfstmWback: Rn is c2121=0 & Rn { }\n}\n\nwith : TMode=1 {\nfstmSet1: thv_Dd_1 is thv_Rn & thv_Dd_1 { * thv_Rn = thv_Dd_1; }\nfstmSet2: thv_Dd_2 is thv_Rn & thv_Dd_2 & fstmSet1 { build fstmSet1; *:8 (thv_Rn + 8:4) = thv_Dd_2; }\nfstmSet3: thv_Dd_3 is thv_Rn & thv_Dd_3 & fstmSet2 { build fstmSet2; *:8 (thv_Rn + 16:4) = thv_Dd_3; }\nfstmSet4: thv_Dd_4 is thv_Rn & thv_Dd_4 & fstmSet3 { build fstmSet3; *:8 (thv_Rn + 24:4) = thv_Dd_4; }\nfstmSet5: thv_Dd_5 is thv_Rn & thv_Dd_5 & fstmSet4 { build fstmSet4; *:8 (thv_Rn + 32:4) = thv_Dd_5; }\nfstmSet6: thv_Dd_6 is thv_Rn & thv_Dd_6 & fstmSet5 { build fstmSet5; *:8 (thv_Rn + 40:4) = thv_Dd_6; }\nfstmSet7: thv_Dd_7 is thv_Rn & thv_Dd_7 & fstmSet6 { build fstmSet6; *:8 (thv_Rn + 48:4) = thv_Dd_7; }\nfstmSet8: thv_Dd_8 is thv_Rn & thv_Dd_8 & fstmSet7 { build fstmSet7; *:8 (thv_Rn + 56:4) = thv_Dd_8; }\nfstmSet9: thv_Dd_9 is thv_Rn & thv_Dd_9 & fstmSet8 { build fstmSet8; *:8 (thv_Rn + 64:4) = thv_Dd_9; }\nfstmSet10: thv_Dd_10 is thv_Rn & thv_Dd_10 & fstmSet9 { build fstmSet9; *:8 (thv_Rn + 72:4) = thv_Dd_10; }\nfstmSet11: thv_Dd_11 is thv_Rn & thv_Dd_11 & fstmSet10 { build fstmSet10; *:8 (thv_Rn + 80:4) = thv_Dd_11; }\nfstmSet12: thv_Dd_12 is thv_Rn & thv_Dd_12 & fstmSet11 { build fstmSet11; *:8 (thv_Rn + 88:4) = thv_Dd_12; }\nfstmSet13: thv_Dd_13 is thv_Rn & thv_Dd_13 & fstmSet12 { build fstmSet12; *:8 (thv_Rn + 96:4) = thv_Dd_13; }\nfstmSet14: thv_Dd_14 is thv_Rn & thv_Dd_14 & fstmSet13 { build fstmSet13; *:8 (thv_Rn + 104:4) = thv_Dd_14; }\nfstmSet15: thv_Dd_15 is thv_Rn & thv_Dd_15 & fstmSet14 { build fstmSet14; *:8 (thv_Rn + 112:4) = thv_Dd_15; }\nfstmSet16: thv_Dd_16 is thv_Rn & thv_Dd_16 & fstmSet15 { build fstmSet15; *:8 (thv_Rn + 120:4) = thv_Dd_16; }\n\nfstmSet: \"{\"^thv_Dd_1^\"}\" is thv_Dd_1 & thv_c0007=3 & fstmSet1 { build fstmSet1; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet2^\"}\" is thv_Dd_1 & thv_c0007=5 & fstmSet2 { build fstmSet2; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet3^\"}\" is thv_Dd_1 & thv_c0007=7 & fstmSet3 { build fstmSet3; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet4^\"}\" is thv_Dd_1 & thv_c0007=9 & fstmSet4 { build fstmSet4; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet5^\"}\" is thv_Dd_1 & thv_c0007=11 & fstmSet5 { build fstmSet5; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet6^\"}\" is thv_Dd_1 & thv_c0007=13 & fstmSet6 { build fstmSet6; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet7^\"}\" is thv_Dd_1 & thv_c0007=15 & fstmSet7 { build fstmSet7; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet8^\"}\" is thv_Dd_1 & thv_c0007=17 & fstmSet8 { build fstmSet8; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet9^\"}\" is thv_Dd_1 & thv_c0007=19 & fstmSet9 { build fstmSet9; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet10^\"}\" is thv_Dd_1 & thv_c0007=21 & fstmSet10 { build fstmSet10; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet11^\"}\" is thv_Dd_1 & thv_c0007=23 & fstmSet11 { build fstmSet11; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet12^\"}\" is thv_Dd_1 & thv_c0007=25 & fstmSet12 { build fstmSet12; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet13^\"}\" is thv_Dd_1 & thv_c0007=27 & fstmSet13 { build fstmSet13; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet14^\"}\" is thv_Dd_1 & thv_c0007=29 & fstmSet14 { build fstmSet14; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet15^\"}\" is thv_Dd_1 & thv_c0007=31 & fstmSet15 { build fstmSet15; }\nfstmSet: \"{\"^thv_Dd_1^\"-\"^fstmSet16^\"}\" is thv_Dd_1 & thv_c0007=33 & fstmSet16 { build fstmSet16; }\n\n\nfstmWback: thv_Rn^\"!\" is thv_bit21=1 & thv_bit23=1 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn + (4 * thv_c0007:4); }\nfstmWback: thv_Rn^\"!\" is thv_bit21=1 & thv_bit23=0 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn - (4 * thv_c0007:4); }\nfstmWback: thv_Rn is thv_bit21=0 & thv_Rn { }\n}\n\n:fstmdbx^COND fstmSet, fstmWback is $(AMODE) & COND & ARMcond=1 & c2327=0x1a & c2021=2 & c0811=0xb & c0000=1 & fstmWback & fstmSet\n{\n\tbuild fstmWback;\n\tbuild fstmSet;\n}\n\n:fstmiax^COND fstmSet, fstmWback is $(AMODE) & COND & ARMcond=1 & c2327=0x19 & c2020=0 & c0811=0xb & c0000=1 & fstmWback & fstmSet\n{\n\tbuild fstmSet;\n\tbuild fstmWback;\n}\n\n:fstmdbx^ItCond fstmSet, fstmWback is TMode=1 & ItCond & thv_c2331=0x1da & thv_c2021=2 & thv_c0811=0xb & fstmWback & fstmSet\n{\n\tbuild fstmWback;\n\tbuild fstmSet;\n}\n\n:fstmiax^ItCond fstmSet, fstmWback is TMode=1 & ItCond & thv_c2331=0x1d9 & thv_bit20=0 & thv_c0811=0xb & fstmWback & fstmSet\n{\n\tbuild fstmSet;\n\tbuild fstmWback;\n}\n\n@endif\n\n@if defined(VFPv2) || defined(VFPv3)\n\n#######\n# VLDM (A2)\n#\n\nbuildVldmSdList:\t\t\t\t\t\tis counter=0 { }\nbuildVldmSdList: Sreg\t\t\t\t\tis counter=1 & Sreg [ counter=0; regNum=regNum+1; ]\n{\n\tSreg = *mult_addr;\n\tmult_addr = mult_addr + 4;\n}\nbuildVldmSdList: Sreg,buildVldmSdList\tis Sreg & buildVldmSdList [ counter=counter-1; regNum=regNum+1; ]\n{\n\tSreg = *mult_addr;\n\tmult_addr = mult_addr + 4;\n\tbuild buildVldmSdList;\n}\n\nvldmSdList: \"{\"^buildVldmSdList^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVldmSdList [ regNum=(c1215<<1) + D22 - 1; counter=c0007; ] { }\nvldmSdList: \"{\"^buildVldmSdList^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmSdList [ regNum=(thv_c1215<<1) + thv_D22 - 1; counter=thv_c0007; ] { }\n\n:vldmia^COND vldmRn,vldmSdList\tis ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=10 ) |\n ($(TMODE_E) & thv_c2327=0x19 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset & vldmUpdate\n{\n\tmult_addr = vldmRn;\n\tbuild vldmSdList;\n\tbuild vldmUpdate;\n}\n\n:vldmdb^COND vldmRn,vldmSdList\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=1 & c0811=10 ) |\n ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset\n{\n\tlocal start_addr = vldmRn - vldmOffset;\n\tmult_addr = start_addr;\n\tbuild vldmSdList;\n\tvldmRn = start_addr;\n}\n\n#######\n# VLDR\n#\n\nvldrRn: \"[\"^Rn^\"]\"\t\t\t\tis TMode=0 & Rn & immed=0 & c2323=0\t\t\t\t{ ptr:4 = Rn; export ptr; }\nvldrRn: \"[\"^Rn^\"]\"\t\t\t\tis TMode=0 & Rn & immed=0 & c2323=1\t\t\t\t{ ptr:4 = Rn; export ptr; }\nvldrRn: \"[\"^Rn^\",#-\"^vldrImm^\"]\"\tis TMode=0 & Rn & immed & c2323=0 [ vldrImm = immed * 4; ]\t{ ptr:4 = Rn - vldrImm; export ptr; }\nvldrRn: \"[\"^Rn^\",#\"^vldrImm^\"]\"\tis TMode=0 & Rn & immed & c2323=1\t [ vldrImm = immed * 4; ]\t{ ptr:4 = Rn + vldrImm; export ptr; }\nvldrRn: \"[\"^pc^\"]\"\tis TMode=0 & Rn=15 & pc & immed=0 & c2323=0\t\t{ ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; }\nvldrRn: \"[\"^pc^\"]\"\tis TMode=0 & Rn=15 & pc & immed=0 & c2323=1\t\t{ ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; }\nvldrRn: \"[\"^pc^\",#-\"^vldrImm^\"]\"\tis TMode=0 & Rn=15 & pc & immed & c2323=0 [ vldrImm = immed * 4; ]\t{ ptr:4 = ((inst_start + 8) & 0xfffffffc) - vldrImm; export ptr; }\nvldrRn: \"[\"^pc^\",#\"^vldrImm^\"]\"\tis TMode=0 & Rn=15 & pc & immed & c2323=1\t [ vldrImm = immed * 4; ]\t{ ptr:4 = ((inst_start + 8) & 0xfffffffc) + vldrImm; export ptr; }\nvldrRn: \"[\"^VRn^\"]\"\t\t\t\tis TMode=1 & VRn & thv_immed=0 & thv_c2323=0\t\t\t\t{ ptr:4 = VRn; export ptr; }\nvldrRn: \"[\"^VRn^\"]\"\t\t\t\tis TMode=1 & VRn & thv_immed=0 & thv_c2323=1\t\t\t\t{ ptr:4 = VRn; export ptr; }\nvldrRn: \"[\"^VRn^\",#-\"^vldrImm^\"]\"\tis TMode=1 & VRn & thv_immed & thv_c2323=0\t[ vldrImm = thv_immed * 4; ]\t{ ptr:4 = VRn - vldrImm; export ptr; }\nvldrRn: \"[\"^VRn^\",#\"^vldrImm^\"]\"\tis TMode=1 & VRn & thv_immed & thv_c2323=1\t[ vldrImm = thv_immed * 4; ]\t{ ptr:4 = VRn + vldrImm; export ptr; }\nvldrRn: \"[\"^pc^\"]\"\tis TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=0\t\t{ ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; }\nvldrRn: \"[\"^pc^\"]\"\tis TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=1\t\t{ ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; }\nvldrRn: \"[\"^pc^\",#-\"^vldrImm^\"]\"\tis TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=0\t[ vldrImm = thv_immed * 4; ]\t{ ptr:4 = ((inst_start + 4) & 0xfffffffc) - vldrImm; export ptr; }\nvldrRn: \"[\"^pc^\",#\"^vldrImm^\"]\"\tis TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=1\t[ vldrImm = thv_immed * 4; ]\t{ ptr:4 = ((inst_start + 4) & 0xfffffffc) + vldrImm; export ptr; }\n\n:vldr^COND^\".64\" Dd,vldrRn\tis COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=1 & c0811=11) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=1 & thv_c0811=11)) & Dd & vldrRn\n{\n\tDd = *:8 vldrRn;\n}\n\n:vldr^COND^\".32\" Sd,vldrRn\tis COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=1 & c0811=10) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=1 & thv_c0811=10)) & Sd & vldrRn\n{\n\tSd = *:4 vldrRn;\n}\n\n@endif # VFPv2 | VFPv3\n\ndefine pcodeop VectorMin;\ndefine pcodeop VectorMax;\ndefine pcodeop FloatVectorMin;\ndefine pcodeop FloatVectorMax;\ndefine pcodeop VectorMultiplyAccumulate;\ndefine pcodeop VectorMultiplySubtract;\ndefine pcodeop VectorMultiplySubtractLong;\ndefine pcodeop VectorDoubleMultiplyHighHalf;\ndefine pcodeop VectorRoundDoubleMultiplyHighHalf;\ndefine pcodeop VectorDoubleMultiplyLong;\ndefine pcodeop VectorDoubleMultiplyAccumulateLong;\ndefine pcodeop VectorDoubleMultiplySubtractLong;\ndefine pcodeop FloatVectorMultiplyAccumulate;\ndefine pcodeop FloatVectorMultiplySubtract;\n\n@if defined(SIMD)\n\n:vmax.^udt^esize2021 Dd, Dn, Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=0 & c0404=0 ) |\n ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & udt & Dm & Dn & Dd\n{\n\tDd = VectorMax(Dn,Dm,esize2021,udt);\n}\n\n:vmax.^udt^esize2021 Qd, Qn, Qm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=1 & c0404=0 ) |\n ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & udt & Qm & Qn & Qd\n{\n\tQd = VectorMax(Qn,Qm,esize2021,udt);\n}\n\n:vmax.f32 Dd,Dn,Dm\tis (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=15 & Q6=0 & c0404=0) |\n\t\t\t\t\t\t($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0)) & Dm & Dn & Dd\n{\n\tDd = FloatVectorMax(Dn,Dm,2:4,32:1);\n}\n\n:vmax.f32 Qd,Qn,Qm\tis (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=15 & Q6=1 & c0404=0) |\n\t\t\t\t\t\t($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=15 & thv_Q6=1 & thv_c0404=0)) & Qm & Qn & Qd\n{\n\tQd = FloatVectorMax(Qn,Qm,2:4,32:1);\n}\n\n:vmin.^udt^esize2021 Dd, Dn, Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=0 & c0404=1 ) |\n ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=1 ) ) & esize2021 & udt & Dm & Dn & Dd\n\n{\n\tDd = VectorMin(Dn,Dm,esize2021,udt);\n}\n\n:vmin.^udt^esize2021 Qd, Qn, Qm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=1 & c0404=1 ) |\n ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=1 ) ) & esize2021 & udt & Qm & Qn & Qd\n\n{\n\tQd = VectorMin(Qn,Qm,esize2021,udt);\n}\n\n:vmin.f32 Dd,Dn,Dm\tis (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=15 & Q6=0 & c0404=0) |\n\t\t\t\t\t\t($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0)) & Dm & Dn & Dd\n{\n\tDd = FloatVectorMin(Dn,Dm,2:4,32:1);\n}\n\n:vmin.f32 Qd,Qn,Qm\tis (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=15 & Q6=1 & c0404=0) |\n\t\t\t\t\t\t($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=15 & thv_Q6=1 & thv_c0404=0)) & Qm & Qn & Qd\n{\n\tQd = FloatVectorMin(Qn,Qm,2:4,32:1);\n}\n\n:vmla.i^esize2021 Dd,Dn,Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021<3 & c0811=9 & Q6=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dm & Dn & Dd\n{\n\tDd = VectorMultiplyAccumulate(Dn,Dm,esize2021,0:1);\n} \n\n:vmla.i^esize2021 Qd,Qn,Qm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021<3 & c0811=9 & Q6=1 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorMultiplyAccumulate(Qn,Qm,esize2021,0:1);\n} \n\n:vmls.i^esize2021 Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2424=1 & c2021<3 & c0811=9 & Q6=0 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dm & Dn & Dd\n{\n\tDd = VectorMultiplySubtract(Dn,Dm,esize2021,0:1);\n} \n\n:vmls.i^esize2021 Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2424=1 & c2021<3 & c0811=9 & Q6=1 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorMultiplySubtract(Qn,Qm,esize2021,0:1);\n} \n\n:vmlal.^udt^esize2021 Qd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=8 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Qd & udt & esize2021\n{\n\tQd = VectorMultiplyAccumulate(Dn,Dm,esize2021,udt);\n} \n\n:vmlsl.^udt^esize2021 Qd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=10 & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Qd & udt & esize2021\n{\n\tQd = VectorMultiplySubtractLong(Dn,Dm,esize2021,udt);\n} \n\n:vmla.f^fesize2020 Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=0 & c0404=1) |\n\t ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_c0606=0 & thv_c0404=1)) & fesize2020 & Dn & Dd & Dm\n{\n\tDd = FloatVectorMultiplyAccumulate(Dn,Dm,fesize2020,8:1);\n}\n\n:vmla.f^fesize2020 Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=1 & c0404=1) | \n\t ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_c0606=1 & thv_c0404=1)) & fesize2020 & Qn & Qd & Qm\n{\n\tQd = FloatVectorMultiplyAccumulate(Qn,Qm,fesize2020,16:1);\n}\n\n:vmls.f^fesize2020 Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_c0606=0 & thv_c0404=1)) & fesize2020 & Dn & Dd & Dm\n{\n\tDd = FloatVectorMultiplySubtract(Dn,Dm,fesize2020,8:1);\n}\n\n:vmls.f^fesize2020 Qd,Qn,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=1 & c0404=1) | \n\t ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_c0606=1 & thv_c0404=1)) & fesize2020 & Qn & Qd & Qm\n{\n\tQd = FloatVectorMultiplySubtract(Qn,Qm,fesize2020,16:1);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vmla^COND^\".f32\" Sd,Sn,Sm\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & COND & Sm & Sn & Sd\n{\n\tSd = Sd f+ (Sn f* Sm);\n}\n\n:vmla^COND^\".f64\" Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=0 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & COND & Dm & Dn & Dd\n{\n\tDd = Dd f+ (Dn f* Dm);\n}\n\n:vmls^COND^\".f32\" Sd,Sn,Sm\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=1 & c0404=0) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0)) & COND & Sm & Sn & Sd\n{\n\tSd = Sd f- (Sn f* Sm);\n}\n\n:vmls^COND^\".f64\" Dd,Dn,Dm\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=1 & c0404=0 ) |\n\t\t\t\t\t\t ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & COND & Dm & Dn & Dd\n{\n\tDd = Dd f- (Dn f* Dm);\n}\n\n@endif # VFPv2 || VFPv3\n\n@if defined(SIMD)\n\n#####\n# VML* (by scalar) (A1)\n#\n\nvmlDm: Dm_3^\"[\"^index^\"]\"\tis TMode=0 & c2021=1 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ]\t{ el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; }\nvmlDm: Dm_4^\"[\"^M5^\"]\"\t\tis TMode=0 & c2021=2 & Dm_4 & M5\t\t\t\t\t\t\t\t\t\t\t{ el:4 = VectorGetElement(Dm_4, M5:1, 4:1, 0:1); export el; }\nvmlDm: thv_Dm_3^\"[\"^index^\"]\"\tis TMode=1 & thv_c2021=1 & thv_Dm_3 & thv_M5 & thv_c0303 [ index = (thv_M5 << 1) + thv_c0303; ]\t{ el:4 = VectorGetElement(thv_Dm_3, index:1, 2:1, 0:1); export el; }\nvmlDm: thv_Dm_4^\"[\"^thv_M5^\"]\"\t\tis TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5\t\t\t\t\t\t\t\t\t\t\t{ el:4 = VectorGetElement(thv_Dm_4, thv_M5:1, 4:1, 0:1); export el; }\n\n\n:vmla.i^esize2021 Dd,Dn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2) & c0811=0 & c0606=1 & c0404=0) |\n\t ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm\n{\n\tDd = VectorMultiplyAccumulate(Dn,vmlDm,esize2021);\n}\n\n:vmla.i^esize2021 Qd,Qn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0 & c0606=1 & c0404=0) |\n\t ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm\n{\n\tQd = VectorMultiplyAccumulate(Qn,vmlDm,esize2021);\n}\n\n:vmla.f32 Dd,Dn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=1 & c0606=1 & c0404=0) |\n\t ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm\n{\n\tDd = FloatVectorMultiplyAccumulate(Dn,vmlDm,2:4,32:1);\n}\n\n:vmla.f32 Qd,Qn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2021=2 & c0811=1 & c0606=1 & c0404=0) |\n\t ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm\n{\n\tQd = FloatVectorMultiplyAccumulate(Qn,vmlDm,2:4,32:1);\n}\n\n:vmls.i^esize2021 Dd,Dn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2) & c0811=4 & c0606=1 & c0404=0) |\n\t ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm\n{\n\tDd = VectorMultiplySubtract(Dn,vmlDm,esize2021);\n}\n\n:vmls.i^esize2021 Qd,Qn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2)& c0811=4 & c0606=1 & c0404=0) |\n\t ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm\n{\n\tQd = VectorMultiplySubtract(Qn,vmlDm,esize2021);\n}\n\n:vmls.f32 Dd,Dn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=5 & c0606=1 & c0404=0) |\n\t ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm\n{\n\tDd = FloatVectorMultiplySubtract(Dn,vmlDm,2:4,32:1);\n}\n\n:vmls.f32 Qd,Qn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2021=2 & c0811=5 & c0606=1 & c0404=0) |\n\t ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm\n{\n\tQd = FloatVectorMultiplySubtract(Qn,vmlDm,2:4,32:1);\n}\n\n#####\n# VML* (by scalar) (A2)\n#\n\n\n\n:vmlal.^udt^esize2021 Qd,Dn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=2 & Q6=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=2 & thv_Q6=1 & thv_c0404=0 ) ) & udt & esize2021 & Dn & Qd & vmlDm\n{\n\tQd = VectorMultiplyAccumulate(Dn,vmlDm,esize2021,udt);\n}\n\n:vmlsl.^udt^esize2021 Qd,Dn,vmlDm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=6 & Q6=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=6 & thv_Q6=1 & thv_c0404=0 ) ) & udt & esize2021 & Dn & Qd & vmlDm\n{\n\tQd = VectorMultiplySubtract(Dn,vmlDm,esize2021,udt);\n}\n\n# Addresses all versions of F6.1.134 except A2/T2 with Q=0\n:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0404=1 ) | \n\t\t\t\t\t\t\t\t\t\t( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8\n{\n\tDd = simdExpImm_8;\n}\n\n# Addresses all versions of F6.1.134 except At/T2 with Q=1\n:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0404=1 ) |\n\t\t\t\t\t\t\t\t\t\t( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16\n{\n\tQd = simdExpImm_16;\n}\n\n@endif # SIMD\n\n@if defined(VFPv3)\n\n# F6.1.134 vmov A2/T2\n\n:vmov^COND^\".f16\" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0x90 ) |\n\t\t\t\t\t\t\t\t\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0x90 ) ) & COND & Sd & vfpExpImm_4\n{\n\tbuild COND;\n\tSd = vfpExpImm_4;\n}\n\n:vmov^COND^\".f32\" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xa0 ) |\n\t\t\t\t\t\t\t\t\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xa0 ) ) & COND & Sd & vfpExpImm_4\n{\n\tbuild COND;\n\tSd = vfpExpImm_4;\n}\n\n# F6.1.134 vmov A2/T2\n:vmov^COND^\".f64\" Dd,vfpExpImm_8 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xb0 ) |\n\t\t\t\t\t\t\t\t ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xb0 ) ) & COND & Dd & vfpExpImm_8 \n{\n\tbuild COND;\n\tDd = vfpExpImm_8;\n}\n\n@endif # VFPv3\n\n@if defined(SIMD)\n\n:vmov Dd,Dm\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c1619=c0003 & c0811=1 & c0707=c0505 & Q6=0 & c0404=1 ) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c1619=thv_c0003 & thv_c0811=1 & thv_c0707=thv_c0505 & thv_c0606=0 & thv_c0404=1) ) & Dd & Dm\n{\n\tDd = Dm;\n}\n\n:vmov Qd,Qm\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c1619=c0003 & c0811=1 & c0707=c0505 & Q6=1 & c0404=1 ) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c1619=thv_c0003 & thv_c0811=1 & thv_c0707=thv_c0505 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qm\n{\n\tQd = Qm;\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vmov^COND^\".f32\" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x29 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x29 & thv_c0404=0) ) & COND & Sd & Sm \n{\n\tSd = Sm;\n}\n\n:vmov^COND^\".f64\" Dd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2d & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2d & thv_c0404=0) ) & COND & Dd & Dm\n{\n\tDd = Dm;\n}\n\n@endif # VFPv2 || VFPv3\n\ndefine pcodeop VectorSetElement;\n\n@if defined(SIMD)\n\nvmovIndex: val\tis TMode=0 & c2222=1 & c2121 & c0506\t\t\t\t\t[ val = (c2121 << 2) + c0506; ]\t{ tmp:1 = val; export tmp; }\nvmovIndex: val\tis TMode=0 & c2222=0 & c2121 & c0606 & c0505=1\t[ val = (c2121 << 1) + c0606; ]\t{ tmp:1 = val; export tmp; }\n\nvmovIndex: val\tis TMode=1 & thv_c2222=1 & thv_c2121 & thv_c0506\t\t\t\t\t[ val = (thv_c2121 << 2) + thv_c0506; ]\t{ tmp:1 = val; export tmp; }\nvmovIndex: val\tis TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0606 & thv_c0505=1\t[ val = (thv_c2121 << 1) + thv_c0606; ]\t{ tmp:1 = val; export tmp; }\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\nvmovIndex: c2121 is TMode=0 & c2222=0 & c2121 & c0506=0\t\t\t\t{ tmp:1 = c2121; export tmp; }\nvmovIndex: thv_c2121 is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0506=0\t\t\t\t{ tmp:1 = thv_c2121; export tmp; }\n\n@endif # VFPv2 || VFPv3 || SIMD\n\n\ndNvmovIndex: Dn^\"[\"^vmovIndex^\"]\" is Dn & vmovIndex { }\n\n\n:vmov^COND^\".8\" dNvmovIndex,VRd\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=0 & c0811=11 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=0 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tel:1 = VRd(0);\n\tvmask:8 = 0xf << (vmovIndex*8);\n\tDn = (Dn & ~vmask) | (zext(el) & vmask);\n\t#VectorSetElement(VRd,Dn,vmovIndex);\n}\n\n:vmov^COND^\".16\" dNvmovIndex,VRd\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=0 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tel:2 = VRd(0);\n\tvmask:8 = 0xff << (vmovIndex*16);\n\tDn = (Dn & ~vmask) | (zext(el) & vmask);\n\t#VectorSetElement(VRd,Dn,vmovIndex,vmovSize);\n}\n\n\n:vmov^COND^\".32\" dNvmovIndex,VRd\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=0 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tel:4 = VRd;\n\tvmask:8 = 0xffff << (vmovIndex*32);\n\tDn = (Dn & ~vmask) | (zext(el) & vmask);\n\t#VectorSetElement(VRd,Dn,vmovIndex,vmovSize);\n}\n\n\n:vmov^COND^\".u8\" VRd,dNvmovIndex\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tval:8 = Dn >> (vmovIndex*8);\n\tresult:1 = val(0);\n\tVRd = zext(result);\n\t#VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1);\n}\n\n:vmov^COND^\".u16\" VRd,dNvmovIndex\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=0 & c2020=1 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tval:8 = Dn >> (vmovIndex*16);\n\tresult:2 = val(0);\n\tVRd = zext(result);\n\t#VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1);\n}\n\n:vmov^COND^\".u32\" VRd,dNvmovIndex\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=0 & c2020=1 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tval:8 = Dn >> (vmovIndex*32);\n\tresult:4 = val(0);\n\tVRd = zext(result);\n\t#VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1);\n}\n\n:vmov^COND^\".s8\" VRd,dNvmovIndex\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tval:8 = Dn >> (vmovIndex*8);\n\tresult:1 = val(0);\n\tVRd = sext(result);\n\t#VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1);\n}\n\n:vmov^COND^\".s16\" VRd,dNvmovIndex\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=1 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tval:8 = Dn >> (vmovIndex*16);\n\tresult:2 = val(0);\n\tVRd = sext(result);\n\t#VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1);\n}\n\n:vmov^COND^\".s32\" VRd,dNvmovIndex\tis ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=1 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex\n{\n\tval:8 = Dn >> (vmovIndex*32);\n\tresult:4 = val(0);\n\tVRd = sext(result);\n\t#VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1);\n}\n\n@endif # SIMD\n\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vmov^COND Sn,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=0 & c0811=10 & c0006=0x10) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=0 & thv_c0811=10 & thv_c0006=0x10) ) & COND & Sn & VRd\n{\n\tSn = VRd;\n}\n\n:vmov^COND VRd,Sn is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=1 & c0811=10 & c0006=0x10) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=1 & thv_c0811=10 & thv_c0006=0x10) ) & COND & Sn & VRd\n{\n\tVRd = Sn;\n}\n\n:vmov^COND Sm,SmNext,VRd,VRn is ( ($(AMODE) & ARMcond=1 & c2027=0xc4 & c0611=0x28 & c0404=1) |\n ($(TMODE_E) & thv_c2027=0xc4 & thv_c0611=0x28 & thv_c0404=1) ) & COND & VRn & VRd & Sm & SmNext\n{\n\tSm = VRd;\n\tSmNext = VRn;\n}\n\n:vmov^COND VRd,VRn,Sm,SmNext is ( ($(AMODE) & ARMcond=1 & c2027=0xc5 & c0611=0x28 & c0404=1) |\n ($(TMODE_E) & thv_c2027=0xc5 & thv_c0611=0x28 & thv_c0404=1) ) & COND & VRn & VRd & Sm & SmNext\n{\n\tVRd = Sm;\n\tVRn = SmNext;\n}\n\n@endif # VFPv2 || VFPv3\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\n:vmov^COND Dm,VRd,VRn\tis COND & ( ($(AMODE) & ARMcond=1 & c2027=0xc4 & c0611=0x2c & c0404=1) | ($(TMODE_E) & thv_c2027=0xc4 & thv_c0611=0x2c & thv_c0404=1) ) & Dm & VRn & VRd\n{\n\tDm = (zext(VRn) << 32) + zext(VRd);\n}\n\n:vmov^COND VRd,VRn,Dm\tis COND & ( ($(AMODE) & ARMcond=1 & c2027=0xc5 & c0611=0x2c & c0404=1) | ($(TMODE_E) & thv_c2027=0xc5 & thv_c0611=0x2c & thv_c0404=1) ) & Dm & VRn & VRd\n{\n\tVRn = Dm(4);\n\tVRd = Dm:4;\n}\n\n@endif # VFPv2 || VFPv3 || SIMD\n\ndefine pcodeop VectorCopyLong;\ndefine pcodeop VectorCopyNarrow;\n\n@if defined(SIMD)\n\n:vmovl.^udt^esize2021 Qd,Dm\tis (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c1921=1 | c1921=2 | c1921=4) & c1618=0 & c0611=0x28 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1921=1 | thv_c1921=2 | thv_c1921=4) & thv_c1618=0 & thv_c0611=0x28 & thv_c0404=1) ) & esize2021 & udt & Qd & Dm\n{\n\tQd = VectorCopyLong(Dm,esize2021,udt);\n}\n\n:vmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=8 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=8 & thv_c0404=0) ) & esize1819x2 & Dd & Qm\n{\n\tDd = VectorCopyNarrow(Qm,esize1819x2);\n}\n\n:vmovx.F16 Sd,Sm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1921=0x6 & c1618=0 & c0611=0x29 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1d & thv_c1921=0x6 & thv_c1618=0 & thv_c0611=0x29 & thv_c0404=0) ) & Sd & Sm\n{\n\tlocal SmUpper:2 = Sm(2);\n\tSd = zext(SmUpper);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\nvmrsReg: fpsid is (($(AMODE) & c1619=0) | (TMode=1 & thv_c1619=0)) & fpsid { export fpsid; }\nvmrsReg: fpscr is (($(AMODE) & c1619=1) | (TMode=1 & thv_c1619=1)) & fpscr { export fpscr; }\nvmrsReg: mvfr2 is (($(AMODE) & c1619=5) | (TMode=1 & thv_c1619=5)) & mvfr2 { export mvfr2; }\nvmrsReg: mvfr1 is (($(AMODE) & c1619=6) | (TMode=1 & thv_c1619=6)) & mvfr1 { export mvfr1; }\nvmrsReg: mvfr0 is (($(AMODE) & c1619=7) | (TMode=1 & thv_c1619=7)) & mvfr0 { export mvfr0; }\nvmrsReg: fpexc is (($(AMODE) & c1619=8) | (TMode=1 & thv_c1619=8)) & fpexc { export fpexc; }\nvmrsReg: fpinst is (($(AMODE) & c1619=9) | (TMode=1 & thv_c1619=9)) & fpinst { export mvfr1; }\nvmrsReg: fpinst2 is (($(AMODE) & c1619=0xa) | (TMode=1 & thv_c1619=0xa)) & fpinst2 { export mvfr0; }\n\n:vmrs^COND VRd,vmrsReg is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xef & c0011=0xa10) |\n ($(TMODE_E) & thv_c2027=0xef & thv_c0011=0xa10)) & vmrsReg & VRd\n{\n\tVRd = vmrsReg;\n}\n\napsr: \"apsr\" is epsilon {}\n\n:vmrs^COND apsr,fpscr is ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c1215=15 & c0011=0xa10) |\n ($(TMODE_E) & thv_c1627=0xef1 & thv_c1215=15 & thv_c0011=0xa10) \n) & COND & apsr & fpscr\n{\n\tNG = $(FPSCR_N);\n\tZR = $(FPSCR_Z);\n\tCY = $(FPSCR_C);\n\tOV = $(FPSCR_V);\n}\n\n\n\n:vmsr^COND vmrsReg,VRd is ( ($(AMODE) & ARMcond=1 & c2027=0xee & c0011=0xa10) |\n ($(TMODE_E) & thv_c2027=0xee & thv_c0011=0xa10)\n) & COND & VRd & vmrsReg\n{\n\tvmrsReg = VRd;\n}\n\n@endif # VFPv2 || VFPv3 || SIMD\n\n@if defined(SIMD)\n\n###\n# VMUL (floating Point)\n#\n\ndefine pcodeop FloatVectorMult;\ndefine pcodeop VectorMultiply;\ndefine pcodeop PolynomialMultiply;\n\n:vmul.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=0xd & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm\n{\n\tDd = FloatVectorMult(Dn,Dm,2:1,32:1);\n}\n\n:vmul.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=0xd & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd\n{\n\tQd = FloatVectorMult(Qn,Qm,2:1,32:1);\n}\n\n:vmul.f16 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm\n{\n\tDd = FloatVectorMult(Dn,Dm,4:1,16:1);\n}\n\n:vmul.f16 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd\n{\n\tQd = FloatVectorMult(Qn,Qm,4:1,16:1);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\n:vmul^COND^\".f64\" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dn & Dd \n{\n\tDd = Dn f* Dm;\n}\n\n:vmul^COND^\".f32\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd \n{\n\tSd = Sn f* Sm;\n}\n\n@endif # VFPv2 || VFPv3 || SIMD\n\n@if defined(SIMD)\n\n:vmul^COND^\".f16\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=9 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd \n{\n product:2 = Sn:2 f* Sm:2;\n Sd = zext(product);\n}\n\n###\n# VMUL (Integer and polynomial)\n#\n\n:vmul.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=9 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorMultiply(Dn,Dm,esize2021);\n}\n\n:vmul.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=9 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=1 & thv_c0404=1)) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorMultiply(Qn,Qm,esize2021);\n}\n\n:vmul.p8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=0 & thv_c0404=1) ) & Dn & Dd & Dm\n{\n\tDd = PolynomialMultiply(Dn,Dm,1:1);\n}\n\n:vmul.p8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd\n{\n\tQd = PolynomialMultiply(Qn,Qm,1:1);\n}\n\n:vmull.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0xc & Q6=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xc & thv_Q6=0 & thv_c0404=0) ) & esize2021 & Dm & Dn & Qd & udt\n{\n\tQd = VectorMultiply(Dn,Dm,esize2021,udt);\n}\n\n:vmull.p8 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & c2021=0 & c0811=0xe & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd\n{\n\tQd = PolynomialMultiply(Dn,Dm,1:1);\n}\n\n:vmull.p64 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & c2021=2 & c0811=0xe & Q6=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd\n{\n\tQd = PolynomialMultiply(Dn,Dm,8:1);\n}\n\n# The below is confusing but these sub-constructors are used in a combination of F6.1.148 VMUL (by scalar) and F6.1.150 VMULL (by Scalar)\n\netype: \"I\" is TMode=0 & c0909=0 & c0808=0 {}\netype: \"F\" is TMode=0 & c0909=0 & c0808=1 {}\netype: \"S\" is TMode=0 & c0909=1 & c2424=0 {}\netype: \"U\" is TMode=0 & c0909=1 & c2424=1 {}\netype: \"I\" is TMode=1 & thv_c0909=0 & thv_c0808=0 {}\netype: \"F\" is TMode=1 & thv_c0909=0 & thv_c0808=1 {}\netype: \"S\" is TMode=1 & thv_c0909=1 & thv_c2828=0 {}\netype: \"U\" is TMode=1 & thv_c0909=1 & thv_c2828=1 {}\n\nvmlDmA: Dm_3^\"[\"^index^\"]\"\tis TMode=0 & c2021=1 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ]\t\t\t\t{ el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; }\nvmlDmA: Dm_4^\"[\"^M5^\"]\"\t\tis TMode=0 & c2021=2 & Dm_4 & M5\t\t\t\t\t\t\t\t\t\t\t\t\t{ el:4 = VectorGetElement(Dm_4, M5:1, 4:1, 0:1); export el; }\nvmlDmA: Dm_3^\"[\"^index^\"]\"\tis TMode=1 & thv_c2021=1 & Dm_3 & thv_M5 & c0303 [ index = (thv_M5 << 1) + c0303; ]\t{ el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; }\nvmlDmA: Dm_4^\"[\"^thv_M5^\"]\"\tis TMode=1 & thv_c2021=2 & Dm_4 & thv_M5\t\t\t\t\t\t\t\t\t\t\t{ el:4 = VectorGetElement(Dm_4, thv_M5:1, 4:1, 0:1); export el; }\n\n:vmul.^etype^esize2021 Qd,Qn,vmlDmA is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x07 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | \n ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Qn & Qd & vmlDmA\n{\n\tQd = VectorMultiply(Qn,vmlDmA,esize2021);\n}\n\n:vmul.^etype^esize2021 Dd,Dn,vmlDmA is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | \n ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Dn & Dd & vmlDmA\n{\n\tDd = VectorMultiply(Dn,vmlDmA,esize2021);\n}\n\n:vmull.^etype^esize2021 Qd,Dn,vmlDmA is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=10 & c0606=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=10 & thv_c0606=1 & thv_c0404=0 ) ) & Dd & Dm & esize1819 & etype & esize2021 & Dn & Qd & vmlDmA\n{\n\tQd = VectorMultiply(Dn,vmlDmA,esize2021);\n}\n\n###\n# VMVN (immediate)\n#\n\n:vmvn.i32 Dd,simdExpImm_8\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=3 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8\n{\n\tDd = ~simdExpImm_8;\n}\n\n:vmvn.i32 Qd,simdExpImm_16\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=7 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16\n{\n\tQd = ~simdExpImm_16;\n}\n\n:vmvn.i16 Dd,simdExpImm_8\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=3 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8\n{\n\tDd = ~simdExpImm_8;\n}\n\n:vmvn.i16 Qd,simdExpImm_16\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=7 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16\n{\n\tQd = ~simdExpImm_16;\n}\n\n:vmvn.i32 Dd,simdExpImm_8\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=3 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8\n{\n\tDd = ~simdExpImm_8;\n}\n\n:vmvn.i32 Qd,simdExpImm_16\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=7 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16\n{\n\tQd = ~simdExpImm_16;\n}\n\n###\n# VMVN (register)\n#\n\n:vmvn Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0) ) & Dd & Dm\n{\n\tDd = ~Dm;\n}\n\n:vmvn Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=1 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & Qd & Qm\n{\n\ttmp1:8 = Qm:8;\n\ttmp2:8 = Qm(8);\n\ttmp1 = ~ tmp1;\n\ttmp2 = ~ tmp2;\n\tQd = (zext(tmp2) << 64) | zext(tmp1);\n}\n\ndefine pcodeop FloatVectorNeg;\n\n\n:vneg.s^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819\n{\n\tDd = FloatVectorNeg(Dm,1:1,esize1819);\n}\n\n:vneg.s^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=1 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819\n{\n\tQd = FloatVectorNeg(Qm,1:1,esize1819);\n}\n\n:vneg.f^fesize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=1 & c0711=0xf & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=0 & thv_c0404=0 ) ) & fesize1819 & Dm & Dd\n{\n\tDd = FloatVectorNeg(Dm,2:1,fesize1819);\n}\n\n:vneg.f^fesize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xf & Q6=1 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=1 & thv_c0404=0 ) ) & fesize1819 & Qd & Qm\n{\n\tQd = FloatVectorNeg(Qm,2:1,fesize1819);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n\n:vnmla^COND^\".f64\" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & COND & Dm & Dn & Dd\n{\n\tbuild COND;\n product:8 = Dn f* Dm;\n Dd = (f- Dd) f+ (f- product);\n}\n\n:vnmla^COND^\".f32\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd\n{\n\tbuild COND;\n product:4 = Sn f* Sm;\n Sd = (f- Sd) f+ (f- product);\n}\n\n:vnmla^COND^\".f16\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=9 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd\n{\n\tbuild COND;\n product:2 = Sn:2 f* Sm:2;\n product = (f- Sd:2) f+ (f- product);\n Sd = zext(product);\n}\n\n:vnmls^COND^\".f64\" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dn & Dd\n{\n\tbuild COND;\n product:8 = Dn f* Dm;\n Dd = product f- Dd;\n}\n\n:vnmls^COND^\".f32\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd\n{\n\tbuild COND;\n product:4 = Sn f* Sm;\n Sd = product f- Sd;\n}\n\n:vnmls^COND^\".f16\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=9 & c0606=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd \n{\n\tbuild COND;\n product:2 = Sn:2 f* Sm:2;\n product = product f- Sd:2;\n Sd = zext(product);\n}\n\n:vnmul^COND^\".f64\" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & COND & Dm & Dn & Dd\n{\n\tbuild COND;\n product:8 = Dn f* Dm;\n Dd = f- product;\n}\n\n:vnmul^COND^\".f32\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd\n{\n product:4 = Sn f* Sm;\n Sd = f- product;\n}\n\n:vnmul^COND^\".f16\" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd\n{\n\tbuild COND;\n product:2 = Sn:2 f* Sm:2;\n product = f- product;\n Sd = zext(product);\n}\n\n:vneg^COND^\".f16\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x25 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x25 & thv_c0404=0 ) ) & COND & Sm & Sd\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tlocal tmp:2 = Sm(0);\n\tSd = zext(f- tmp);\n}\n\n:vneg^COND^\".f32\" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x29 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sm & Sd\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tSd = f- Sm;\n}\n\n:vneg^COND^\".f64\" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x2d & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Dd & Dm\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tDd = f- Dm;\n}\n\n@endif # VFPv2 || VFPv3\n\n@if defined(SIMD)\n\n#F6.1.141 VORR (register) 64-bit SIMD vector variant (A1 and T1)\n:vorr Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm\n\n{\n\tDd = Dn | Dm;\n}\n\n#F6.1.141 VORR (register) 128-bit SIMD vector variant (A1 and T1)\n:vorr Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm\n{\n\tQd = Qn | Qm;\n}\n\n#F6.1.140 VORR and F6.1.138 VORN (immediate) 64-bit SIMD vector variant\n:vorr Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=1 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=1) ) & Dd & simdExpImm_8\n{\n\tDd = Dd | simdExpImm_8;\n}\n\n#F6.1.140 VORR and F6.1.138 VORN (immediate) 128-bit SIMD vector variant\n:vorr Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=5 ) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=5) ) & Qd & simdExpImm_16\n{\n\tQd = Qd | simdExpImm_16;\n}\n\n#F6.1.139 VORN (register) 64-bit SIMD vector variant (A1 and T1)\n:vorn Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm\n\n{\n\tDd = Dn | ~Dm;\n}\n\n#F6.1.139 VORN (register) 128-bit SIMD vector variant (A1 and T1)\n:vorn Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm\n{\n\tQd = Qn | ~Qm;\n}\n\n@endif # SIMD\n\n\n#######\n# VPUSH (A2)\n#\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\nbuildVpushSdList: Sreg\t\t\t\t\tis counter=0 & Sreg\t\t\t[ regNum=regNum+1; ] { * mult_addr = Sreg; mult_addr = mult_addr + 4; }\nbuildVpushSdList: Sreg,buildVpushSdList\tis Sreg & buildVpushSdList\t[ counter=counter-1; regNum=regNum+1; ] { * mult_addr = Sreg; mult_addr = mult_addr + 4; }\n\nvpushSdList: \"{\"^buildVpushSdList^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVpushSdList [ regNum=(c1215<<1)+D22-1; counter=c0007-1; ] { sp = sp - c0007 * 4; mult_addr = sp; build buildVpushSdList; }\nvpushSdList: \"{\"^buildVpushSdList^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpushSdList [ regNum=(thv_c1215<<1)+thv_D22-1; counter=thv_c0007-1; ] { sp = sp - thv_c0007 * 4; mult_addr = sp; build buildVpushSdList; }\n\nbuildVpushSd64List: Dreg\t\t\t\t\tis counter=0 & Dreg\t\t\t[ regNum=regNum+1; ] { * mult_addr = Dreg:8; mult_addr = mult_addr + 8; }\nbuildVpushSd64List: Dreg,buildVpushSd64List\tis Dreg & buildVpushSd64List\t[ counter=counter-1; regNum=regNum+1; ] { * mult_addr = Dreg:8; mult_addr = mult_addr + 8; build buildVpushSd64List; }\n\nvpushSd64List: \"{\"^buildVpushSd64List^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVpushSd64List [ regNum=(D22<<4)+c1215-1; counter=c0007 / 2 - 1; ] { sp = sp - c0007 * 4; mult_addr = sp; build buildVpushSd64List; }\nvpushSd64List: \"{\"^buildVpushSd64List^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpushSd64List [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007 / 2 - 1; ] { sp = sp - thv_c0007 * 4; mult_addr = sp; build buildVpushSd64List; }\n\n\n:vpush^COND vpushSd64List is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2021=2 & c0811=11 & c0000=0) | \n ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2021=2 & thv_c0811=11 & thv_c0000=0) ) & COND & vpushSd64List\n{\n\tbuild vpushSd64List;\n}\n\n:vpush^COND vpushSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2021=2 & c0811=10) |\n ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2021=2 & thv_c0811=10) ) & COND & vpushSdList\n{\n\tbuild vpushSdList;\n}\n\nbuildVpopSdList: Sreg\t\t\t\t\tis counter=0 & Sreg\t\t\t[ regNum=regNum+1; ]\n { tmp:4 = *mult_addr; Sreg = zext(tmp); mult_addr = mult_addr + 4; }\nbuildVpopSdList: Sreg,buildVpopSdList\tis Sreg & buildVpopSdList\t[ counter=counter-1; regNum=regNum+1; ]\n { tmp:4 = *mult_addr; Sreg = zext(tmp); mult_addr = mult_addr + 4; }\n\nvpopSdList: \"{\"^buildVpopSdList^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVpopSdList [ regNum=(c1215<<1)+D22-1; counter=c0007-1; ]\n { mult_addr = sp; sp = sp + c0007 * 4; build buildVpopSdList; }\nvpopSdList: \"{\"^buildVpopSdList^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpopSdList [ regNum=(thv_c1215<<1)+thv_D22-1; counter=thv_c0007-1; ]\n { mult_addr = sp; sp = sp + thv_c0007 * 4; build buildVpopSdList; }\n\nbuildVpopSd64List: Dreg\t\t\t\t\tis counter=0 & Dreg\t\t\t[ regNum=regNum+1; ]\n { Dreg = *mult_addr; mult_addr = mult_addr + 8; }\nbuildVpopSd64List: Dreg,buildVpopSd64List\tis Dreg & buildVpopSd64List\t[ counter=counter-1; regNum=regNum+1; ]\n { Dreg = *mult_addr; mult_addr = mult_addr + 8; build buildVpopSd64List; }\n\nvpopSd64List: \"{\"^buildVpopSd64List^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVpopSd64List [ regNum=(D22<<4)+c1215-1; counter=c0007 / 2 - 1; ]\n { mult_addr = sp; sp = sp + c0007 * 4; build buildVpopSd64List; }\nvpopSd64List: \"{\"^buildVpopSd64List^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpopSd64List [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007 / 2 - 1; ]\n { mult_addr = sp; sp = sp + thv_c0007 * 4; build buildVpopSd64List; }\n\n:vpop^COND vpopSd64List is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2021=3 & c0811=11 & c0000=0) | \n ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2021=3 & thv_c0811=11 & thv_c0000=0) ) & COND & vpopSd64List\n{\n\tbuild vpopSd64List;\n}\n\n:vpop^COND vpopSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2021=3 & c0811=10) |\n ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2021=3 & thv_c0811=10) ) & COND & vpopSdList\n{\n\tbuild vpopSdList;\n}\n\n@endif # VFPv2 || VFPv3 || SIMD\n\n@if defined(SIMD)\n\ndefine pcodeop SatQ;\ndefine pcodeop SignedSatQ;\n\n:vqabs^\".s\"^esize1819 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=7 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=7 & thv_Q6=0 & thv_c0404=0)) & esize1819 & Dn & Dd & Dm\n{\n\tDd = VectorAbs(Dn,Dm,esize1819);\n\tDd = SatQ(Dd, esize1819, 0:1);\n}\n\n:vqabs^\".s\"^esize1819 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=7 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=7 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qn & Qd\n{\n\tQd = VectorAbs(Qn,Qm,esize1819);\n\tQd = SatQ(Qd, esize1819, 0:1);\n}\n\n:vqadd.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorAdd(Dn,Dm,esize2021,udt);\n\tDd = SatQ(Dd, esize2021, udt);\n}\n\n:vqadd.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorAdd(Qn,Qm,esize2021,udt);\n\tQd = SatQ(Qd, esize2021, udt);\n}\n\n:vqmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=5 & c0606 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=5 & thv_c0404=0) ) & esize1819x2 & Dd & Qm\n{\n\tDd = VectorCopyNarrow(Qm,esize1819x2,c0606:1);\n\tDd = SatQ(Dd, esize1819x2,0:1);\n}\n\n:vqmovun.i^esize1819x2 Dd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=9 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=9 & thv_c0404=0) ) & esize1819x2 & Dd & Qm\n{\n\tDd = VectorCopyNarrow(Qm,esize1819x2,0:1);\n\tDd = SatQ(Dd, esize1819x2,0:1);\n}\n\n:vqdmlal.S^esize2021 Qd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x9 & c0606=0 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x9 & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd\n\n{\n\tQd = VectorDoubleMultiplyAccumulateLong(Dn,Dm,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmlal.S^esize2021 Qd,Dn,vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x3 & c0606=1 & c0404=0) |\n ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x3 & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd\n\n{\n\tQd = VectorDoubleMultiplyAccumulateLong(Dn,vmlDmA,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmlsl.S^esize2021 Qd, Dn, Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0xb & c0606=0 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd\n\n{\n\tQd = VectorDoubleMultiplySubtractLong(Dn,Dm,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmlsl.S^esize2021 Qd, Dn, vmlDmA\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2)& c0811=0x7 & c0606=1 & c0404=0) |\n ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x7 & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd\n\n{\n\tQd = VectorDoubleMultiplySubtractLong(Dn,vmlDmA,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmulh.S^esize2021 Dd, Dn, Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=0 & (c2021=1 | c2021=2) & c0811=0xb & Q6=0 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Dd\n\n{\n\tDd = VectorDoubleMultiplyHighHalf(Dn,Dm,esize2021,0:1);\n\tDd = SatQ(Dd, esize2021,0:1);\n}\n\n:vqdmulh.S^esize2021 Qd, Qn, Qm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=0 & (c2021=1 | c2021=2) & c0811=0xb & Q6=1 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & Qm & Qn & Qd\n\n{\n\tQd = VectorDoubleMultiplyHighHalf(Qn,Qm,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmulh.S^esize2021 Dd, Dn, vmlDmA\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2)& c0811=0xc & c0606=1 & c0404=0) |\n ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Dd\n\n{\n\tDd = VectorDoubleMultiplyLong(Dn,vmlDmA,esize2021,0:1);\n\tDd = SatQ(Dd, esize2021,0:1);\n}\n\n:vqdmulh.S^esize2021 Qd, Qn, vmlDmA\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0xc & c0606=1 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Qn & Qd\n\n{\n\tQd = VectorDoubleMultiplyLong(Qn,vmlDmA,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmull.S^esize2021 Qd, Dn, Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021<3 & c0811=0xD & Q6=0 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xD & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd\n\n{\n\tQd = VectorDoubleMultiplyLong(Dn,Dm,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqdmull.S^esize2021 Qd, Dn, vmlDmA\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021<3 & c0811=0xb & Q6=1 & c0404=0 ) |\n ( $(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xb & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd\n\n{\n\tQd = VectorDoubleMultiplyLong(Dn,vmlDmA,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqrdmulh.S^esize2021 Dd, Dn, Dm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=2 & (c2021=1 | c2021=2) & c0811=0xb & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Dd\n\n{\n\tDd = VectorRoundDoubleMultiplyHighHalf(Dn,Dm,esize2021,0:1);\n\tDd = SatQ(Dd, esize2021,0:1);\n}\n\n:vqrdmulh.S^esize2021 Qd, Qn, Qm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=2 & (c2021=1 | c2021=2) & c0811=0xb & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & Qm & Qn & Qd\n\n{\n\tQd = VectorRoundDoubleMultiplyHighHalf(Qn,Qm,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n:vqrdmulh.S^esize2021 Dd, Dn, vmlDmA\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2)& c0811=0xd & Q6=1 & c0404=0) |\n ( $(TMODE_E) & thv_c2327=0x1f & thv_c2323=1 & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Dd\n\n{\n\tDd = VectorRoundDoubleMultiplyHighHalf(Dn,vmlDmA,esize2021,0:1);\n\tDd = SatQ(Dd, esize2021,0:1);\n}\n\n:vqrdmulh.S^esize2021 Qd, Qn, vmlDmA\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0xd & Q6=1 & c0404=0) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2323=1 & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Qn & Qd\n\n{\n\tQd = VectorRoundDoubleMultiplyHighHalf(Qn,vmlDmA,esize2021,0:1);\n\tQd = SatQ(Qd, esize2021,0:1);\n}\n\n\n:vqsub.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=2 & Q6=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c0811=2 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorSub(Dn,Dm,esize2021,udt);\n\tDd = SatQ(Dd, esize2021, udt);\n}\n\n:vqsub.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=2 & Q6=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c0811=2 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorSub(Qn,Qm,esize2021,udt);\n\tQd = SatQ(Qd, esize2021, udt);\n}\n\n#######\n# VRECPE\ndefine pcodeop VectorReciprocalEstimate;\n\n:vrecpe.^fdt^32 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=0 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=0 & thv_Q6=1 & thv_c0404=0) ) & fdt & Qm & Qd\n{\n\tQd = VectorReciprocalEstimate(Qm,fdt);\n}\n\n:vrecpe.^fdt^32 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=0 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=0 & thv_Q6=0 & thv_c0404=0) ) & fdt & Dm & Dd\n{\n\tDd = VectorReciprocalEstimate(Dm,fdt);\n}\n\n#######\n# VRECPS\ndefine pcodeop VectorReciprocalStep;\n\n:vrecps.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=0 & c0811=0xf & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0404=1) ) & Qn & Qm & Qd\n{\n\tQd = VectorReciprocalStep(Qn,Qm);\n}\n\n:vrecps.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=0 & c0811=0xf & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=1) ) & Dn & Dm & Dd\n{\n\tDd = VectorReciprocalStep(Dn,Dm);\n}\n\n#######\n# VREV\n#\n\ndefine pcodeop vrev;\n\n:vrev16.^esize1819x3 Qd,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=2 & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & esize1819x3\n{\n\tQd = vrev(Qm,esize1819x3);\n}\n\n:vrev32.^esize1819x3 Qd,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=1 & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & esize1819x3\n{\n\tQd = vrev(Qm,esize1819x3);\n}\n\n:vrev64.^esize1819x3 Qd,Qm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=0 & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & esize1819x3\n{\n\tQd = vrev(Qm,esize1819x3);\n}\n\n:vrev16.^esize1819x3 Dd,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=2 & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & esize1819x3\n{\n\tDd = vrev(Dm,esize1819x3);\n}\n\n:vrev32.^esize1819x3 Dd,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=1 & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & esize1819x3\n{\n\tDd = vrev(Dm,esize1819x3);\n}\n\n:vrev64.^esize1819x3 Dd,Dm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=0 & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & esize1819x3\n{\n\tDd = vrev(Dm,esize1819x3);\n}\n\n#######\n# VSH\n#\n\ndefine pcodeop VectorShiftLeft;\ndefine pcodeop VectorRoundShiftLeft;\ndefine pcodeop VectorShiftRight;\ndefine pcodeop VectorShiftLeftInsert;\ndefine pcodeop VectorShiftRightInsert;\ndefine pcodeop VectorShiftRightNarrow;\ndefine pcodeop VectorShiftRightAccumulate;\ndefine pcodeop VectorRoundShiftRight;\ndefine pcodeop VectorRoundShiftRightNarrow;\ndefine pcodeop VectorRoundShiftRightAccumulate;\n\nShiftSize: \"8\" is TMode=0 & c1921=1 & L7=0 { export 8:8; }\nShiftSize: \"16\" is TMode=0 & c2021=1 & L7=0 { export 16:8; }\nShiftSize: \"32\" is TMode=0 & c2121=1 & L7=0 { export 32:8; }\nShiftSize: \"64\" is TMode=0 & L7=1 { export 64:8; }\nShiftSize: \"8\" is TMode=1 & thv_c1921=1 & thv_L7=0 { export 8:8; }\nShiftSize: \"16\" is TMode=1 & thv_c2021=1 & thv_L7=0 { export 16:8; }\nShiftSize: \"32\" is TMode=1 & thv_c2121=1 & thv_L7=0 { export 32:8; }\nShiftSize: \"64\" is TMode=1 & thv_L7=1 { export 64:8; }\n\n\nShiftImmRLI: \"#\"^shift_amt is TMode=0 & c1921=1 & L7=0 & c1621 [ shift_amt = 16 - c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=0 & c2021=1 & L7=0 & c1621 [ shift_amt = 32 - c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=0 & c2121=1 & L7=0 & c1621 [ shift_amt = 64 - c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=0 & L7=1 & c1621 [ shift_amt = 64 - c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=1 & thv_c1921=1 & thv_L7=0 & thv_c1621 [ shift_amt = 16 - thv_c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=1 & thv_c2021=1 & thv_L7=0 & thv_c1621 [ shift_amt = 32 - thv_c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=1 & thv_c2121=1 & thv_L7=0 & thv_c1621 [ shift_amt = 64 - thv_c1621; ] { export *[const]:8 shift_amt; }\nShiftImmRLI: \"#\"^shift_amt is TMode=1 & thv_L7=1 & thv_c1621 [ shift_amt = 64 - thv_c1621; ] { export *[const]:8 shift_amt; }\n\nShiftImmLLI: \"#\"^shift_amt is TMode=0 & c1921=1 & L7=0 & c1621 [ shift_amt = c1621 - 8; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=0 & c2021=1 & L7=0 & c1621 [ shift_amt = c1621 - 16; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=0 & c2121=1 & L7=0 & c1621 [ shift_amt = c1621 - 32; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=0 & L7=1 & c1621 [ shift_amt = c1621 - 0; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=1 & thv_c1921=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 8; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=1 & thv_c2021=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 16; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=1 & thv_c2121=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 32; ] { export *[const]:8 shift_amt; }\nShiftImmLLI: \"#\"^shift_amt is TMode=1 & thv_L7=1 & thv_c1621 [ shift_amt = thv_c1621 - 0; ] { export *[const]:8 shift_amt; }\n\n:vqrshl.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm\n{\n\tQd = VectorRoundShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt);\n}\n\n:vqrshl.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm\n{\n\tDd = VectorRoundShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt);\n}\n\n\n:vqshrn.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x24 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x24 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm\n{\n\tDd = VectorShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt);\n\tDd = SatQ(Dd,esize2021,udt);\n}\n\n:vqshrun.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x20 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x20 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm\n{\n\tDd = VectorShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt);\n\tDd = SatQ(Dd,esize2021,udt);\n}\n\n:vqrshrn.^udt^esize2021 Dd,Qm, ShiftImmRLI\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x25 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x25 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm\n{\n\tDd = VectorRoundShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt);\n\tDd = SatQ(Dd,esize2021,udt);\n}\n\n:vqrshrun.^udt^esize2021 Dd,Qm, ShiftImmRLI\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x21 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x21 & thv_c0404=1) ) & udt & esize2021 & ShiftImmRLI & Dd & Qm\n{\n\tDd = VectorRoundShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt);\n\tDd = SatQ(Dd,esize2021,udt);\n}\n\n\n:vqshl.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=7 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1621 & thv_c0811=7 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm\n{\n\tQd = VectorShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt);\n}\n\n:vqshl.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=7 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1621 & thv_c0811=7 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm\n{\n\tDd = VectorShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt);\n}\n\n:vqshlu.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=6 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2828=1 & thv_c2327=0x1f & thv_c1621 & thv_c0811=6 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm\n{\n\tQd = VectorShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt);\n}\n\n:vqshlu.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=6 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2828=1 & thv_c2327=0x1f & thv_c1621 & thv_c0811=6 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm\n{\n\tDd = VectorShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt);\n}\n\n\n:vqshl.^udt^esize2021 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=1 & thv_c0404=1) ) & udt & esize2021 & Qd & Qm & Qn\n{\n\tQd = VectorShiftLeft(Qm,Qn,esize2021,udt);\n}\n\n:vqshl.^udt^esize2021 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=0 & thv_c0404=1) ) & udt & esize2021 & Dd & Dm & Dn\n{\n\tDd = VectorShiftLeft(Dm,Dn,esize2021,udt);\n}\n\n\n:vshl.I^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=5 & c0606=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Qd & Qm\n{\n\tQd = VectorShiftLeft(Qm,ShiftImmLLI,ShiftSize,0:1);\n}\n\n:vshl.I^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=5 & c0606=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Dd & Dm\n{\n\tDd = VectorShiftLeft(Dm,ShiftImmLLI,ShiftSize,0:1);\n}\n\n\n:vshl.^udt^esize2021 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=1 & thv_c0404=0) ) & udt & esize2021 & Qd & Qm & Qn\n{\n\tQd = VectorShiftLeft(Qm,Qn,esize2021,udt);\n}\n\n:vshl.^udt^esize2021 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=0 & thv_c0404=0) ) & udt & esize2021 & Dd & Dm & Dn\n{\n\tDd = VectorShiftLeft(Dm,Dn,esize2021,udt);\n}\n\ndefine pcodeop VectorShiftLongLeft;\n\n:vshll.^udt^ShiftSize Qd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=10 & c0607=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=10 & thv_c0607=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Dm\n{\n\tQd = VectorShiftLongLeft(Dm,ShiftImmLLI);\n}\n\n:vshll.^udt^esize1819 Qd, Dm, \"#\"^esize1819x3 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=2 & c0811=3 & c0607=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=2 & thv_c0811=3 & thv_c0607=0 & thv_c0404=0) ) & udt & esize1819 & esize1819x3 & Qd & Dm\n{\n\tQd = VectorShiftLongLeft(Dm,esize1819x3);\n}\n\n:vrshl.^udt^esize2021 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=1 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=1 & thv_c0404=0) ) & udt & esize2021 & Qd & Qm & Qn\n{\n\tQd = VectorRoundShiftLeft(Qm,esize2021,Qn);\n}\n\n:vrshl.^udt^esize2021 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=0 & thv_c0404=0) ) & udt & esize2021 & Dd & Dm & Dn\n{\n\tDd = VectorRoundShiftLeft(Dm,esize2021,Dn);\n}\n\n:vrshr.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=2 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=2 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm\n{\n\tQd = VectorRoundShiftRight(Qm,ShiftImmRLI);\n}\n\n:vrshr.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=2 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=2 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm\n{\n\tDd = VectorRoundShiftRight(Dm,ShiftImmRLI);\n}\n\n:vrshrn.^ShiftSize Dd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=8 & c0707=0 & c0606=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=8 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmRLI & Dd & Qm\n{\n\tDd = VectorRoundShiftRightNarrow(Qm,ShiftImmRLI);\n}\n\n:vrsra.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=3 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=3 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm\n{\n\tQd = VectorRoundShiftRightAccumulate(Qd, Qm,ShiftImmRLI);\n}\n\n:vrsra.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=3 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=3 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm\n{\n\tDd = VectorRoundShiftRightAccumulate(Dd, Dm,ShiftImmRLI);\n}\n\n:vsli.^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c0811=5 & c0606=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Dd & Dm\n{\n\tDd = VectorShiftLeftInsert(Dd, Dm,ShiftImmLLI);\n}\n\n:vsli.^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c0811=5 & c0606=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Qd & Qm\n{\n\tQd = VectorShiftLeftInsert(Qd, Qm,ShiftImmLLI);\n}\n\ndefine pcodeop VectorWidenMultipyAccumulate;\n:vsmmla.s8 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & Dn\n{\n\tDd = VectorWidenMultipyAccumulate(Dm,Dn,0:1);\n}\n\n:vsmmla.s8 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & Qn\n{\n\tQd = VectorWidenMultipyAccumulate(Qm,Qn,0:1);\n}\n\n:vummla.u8 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=1) ) & Dd & Dm & Dn\n{\n\tDd = VectorWidenMultipyAccumulate(Dm,Dn,1:1);\n}\n\n:vummla.u8 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=1) ) & Qd & Qm & Qn\n{\n\tQd = VectorWidenMultipyAccumulate(Qm,Qn,1:1);\n}\n\n:vusmmla.s8 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xc & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & Dn\n{\n\tDd = VectorWidenMultipyAccumulate(Dm,Dn,2:1);\n}\n\n:vusmmla.s8 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xc & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & Qn\n{\n\tQd = VectorWidenMultipyAccumulate(Qm,Qn,2:1);\n}\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\n:vsqrt^COND^\".f32\" Sd,Sm\t\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=1 & c0811=10 & c0607=3 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sd\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tSd = sqrt(Sm);\n}\n\n:vsqrt^COND^\".f64\" Dd,Dm\t\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=1 & c0811=11 & c0606=1 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dd\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tDd = sqrt(Dm);\n}\n\n@endif #VFPv2 | VFPv3 | SIMD\n\n@if defined(SIMD)\n:vsra.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=1 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=1 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm\n{\n\tQd = VectorShiftRightAccumulate(Qd, Qm,ShiftImmRLI);\n}\n\n:vsra.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=1 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=1 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm\n{\n\tDd = VectorShiftRightAccumulate(Dd, Dm,ShiftImmRLI);\n}\n\n:vsri.^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c0811=4 & c0606=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=4 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmRLI & Qd & Qm\n{\n\tQd = VectorShiftRightInsert(Qd, Qm,ShiftImmRLI);\n}\n\n:vsri.^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c0811=4 & c0606=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=4 & thv_c0606=0 & thv_c0404=1) ) & ShiftSize & ShiftImmRLI & Dd & Dm\n{\n\tDd = VectorShiftRightInsert(Dd, Dm,ShiftImmRLI);\n}\n\n#######\n# VSHR\n#\n\n:vshr.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=0 & c0606=1 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=0 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm\n{\n\tQd = VectorShiftRight(Qm,ShiftImmRLI);\n}\n\n:vshr.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=0 & c0606=0 & c0404=1) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=0 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm\n{\n\tDd = VectorShiftRight(Dm,ShiftImmRLI);\n}\n\ndefine pcodeop VectorShiftNarrowRight;\n\n:vshrn.^ShiftSize Dd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=8 & c0607=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=8 & thv_c0607=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Qm\n{ \n\tDd = VectorShiftNarrowRight(Qm,ShiftImmRLI);\n}\n\n#######\n# VRSQRTE\ndefine pcodeop VectorReciprocalSquareRootEstimate;\n\n:vrsqrte.^fdt^32 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=1 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & fdt & Qm & Qd\n{\n\tQd = VectorReciprocalSquareRootEstimate(Qm,fdt);\n}\n\n:vrsqrte.^fdt^32 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=1 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0) ) & fdt & Dm & Dd\n{\n\tDd = VectorReciprocalSquareRootEstimate(Dm,fdt);\n}\n\n#######\n# VRSQRTS\ndefine pcodeop VectorReciprocalSquareRootStep;\n\n:vrsqrts.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=2 & c0811=0xf & Q6=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=0xf & thv_Q6=1 & thv_c0404=1) ) & Qn & Qm & Qd\n{\n\tQd = VectorReciprocalSquareRootStep(Qn,Qm);\n}\n\n:vrsqrts.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=2 & c0811=0xf & Q6=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=1) ) & Dn & Dm & Dd\n{\n\tDd = VectorReciprocalSquareRootStep(Dn,Dm);\n}\n\n\n#######\n# VST1 (multiple single elements)\n#\n\nbuildVst1DdList: Dreg\t\t\t\t\tis Dreg & counter=1 \t\t\t\t\t[ counter=0; regNum=regNum+1; ]\n{\n\t* mult_addr = Dreg;\n}\nbuildVst1DdList: Dreg,buildVst1DdList\tis Dreg & buildVst1DdList\t\t\t\t[ counter=counter-1; regNum=regNum+1; ]\n{\n\t* mult_addr = Dreg;\n\tmult_addr = mult_addr + 8;\n\tbuild buildVst1DdList;\n}\n\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 0 & c0811=7 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 0 & c0811=10 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 0 & c0811=6 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { export 3:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 0 & c0811=2 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { export 4:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { export 3:4; }\nvst1DdList: \"{\"^buildVst1DdList^\"}\"\tis TMode = 1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { export 4:4; }\n\n@define Vst1DdList \"(c0811=2 | c0811=6 | c0811=7 | c0811=10)\"\n@define T_Vst1DdList \"(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10)\"\n\n:vst1.^esize0607 vst1DdList,RnAligned45\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=15 & $(Vst1DdList)) |\n\t\t\t\t\t\t\t\t\t\t\t\t($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & thv_c0003=15 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & vst1DdList\n{\n \tmult_addr = RnAligned45;\n \tbuild vst1DdList;\n}\n\n:vst1.^esize0607 vst1DdList,RnAligned45^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=13 & $(Vst1DdList)) |\n\t\t\t\t\t\t\t\t\t\t\t\t($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & thv_c0003=13 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & vst1DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vst1DdList;\n\tRnAligned45 = RnAligned45 + (8 * vst1DdList);\n}\n\n:vst1.^esize0607 vst1DdList,RnAligned45,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & $(Vst1DdList)) |\n\t\t\t\t\t\t\t\t\t\t\t\t($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & VRm & vst1DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vst1DdList;\n\tRnAligned45 = RnAligned45 + VRm;\n}\n\n#######\n# VST1 (single element to one lane)\n#\n\nvst1Index: val\tis TMode=0 & c0507 & c1011\t[ val = c0507 >> c1011; ]\t{ tmp:4 = val; export tmp; }\nvst1Index: val\tis TMode=1 & thv_c0507 & thv_c1011\t[ val = thv_c0507 >> thv_c1011; ]\t{ tmp:4 = val; export tmp; }\n\nvst1DdElement2: Dd^\"[\"^vst1Index^\"]\"\tis ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) & Dd & vst1Index\n{\n\tptr:4 = &Dd + vst1Index;\n\t*:1 mult_addr = *[register]:1 ptr;\n}\nvst1DdElement2: Dd^\"[\"^vst1Index^\"]\"\tis ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) & Dd & vst1Index\n{\n\tptr:4 = &Dd + (2 * vst1Index);\n\t*:2 mult_addr = *[register]:2 ptr;\n}\nvst1DdElement2: Dd^\"[\"^vst1Index^\"]\"\tis ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) & Dd & vst1Index\n{\n\tptr:4 = &Dd + (4 * vst1Index);\n\t*:4 mult_addr = *[register]:4 ptr;\n}\n\n@define Vst1DdElement2 \"((c1011=0 & c0404=0) | (c1011=1 & c0505=0) | (c1011=2 & (c0406=0 | c0406=3)))\"\n@define T_Vst1DdElement2 \"((thv_c1011=0 & thv_c0404=0) | (thv_c1011=1 & thv_c0505=0) | (thv_c1011=2 & (thv_c0406=0 | thv_c0406=3)))\"\n\n:vst1.^esize1011 vst1DdElement2,RnAligned2 is (($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c0809=0 & c0003=15 & $(Vst1DdElement2)) |\n ($(TMODE_F) & thv_c2327=19 & thv_c2021=0 & thv_c0809=0 & thv_c0003=15 & $(T_Vst1DdElement2))) & RnAligned2 & esize1011 & vst1DdElement2\n{\n \tmult_addr = RnAligned2;\n\tbuild vst1DdElement2;\n}\n\n:vst1.^esize1011 vst1DdElement2,RnAligned2^\"!\" is (($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c0809=0 & c0003=13 & $(Vst1DdElement2)) |\n ($(TMODE_F) & thv_c2327=19 & thv_c2021=0 & thv_c0809=0 & thv_c0003=13 & $(T_Vst1DdElement2))) & RnAligned2 & esize1011 & vst1DdElement2\n{\n\tmult_addr = RnAligned2;\n\tbuild vst1DdElement2;\n\tRnAligned2 = RnAligned2 + esize1011;\n}\n\n:vst1.^esize1011 vst1DdElement2,RnAligned2,VRm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c0809=0 & $(Vst1DdElement2)) |\n ($(TMODE_F) & thv_c2327=19 & thv_c2021=0 & thv_c0809=0 & $(T_Vst1DdElement2))) & VRm & RnAligned2 & esize1011 & vst1DdElement2\n{\n\tmult_addr = RnAligned2;\n\tbuild vst1DdElement2;\n\tRnAligned2 = RnAligned2 + VRm;\n}\n\n\n#######\n# VST2\n#\n\n#######\n# VST2 (multiple 2-element structures)\n#\n\nvst2Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n \tptr2:4 = &Dreg + (regInc * 8);\n@else # ENDIAN == \"big\"\n \tptr2:4 = &Dreg - (regInc * 8);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 8;\n\n\t*:1 mult_addr = *[register]:1 ptr1;\n\tmult_addr = mult_addr + 1;\n\t*:1 mult_addr = *[register]:1 ptr2;\n\tmult_addr = mult_addr + 1;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 1;\n\tptr2 = ptr2 + 1;\n\tgoto ;\n\n}\nvst2Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n \tptr2:4 = &Dreg + (regInc * 8);\n@else # ENDIAN == \"big\"\n \tptr2:4 = &Dreg - (regInc * 8);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 4;\n\n\t*:2 mult_addr = *[register]:2 ptr1;\n\tmult_addr = mult_addr + 2;\n\t*:2 mult_addr = *[register]:2 ptr2;\n\tmult_addr = mult_addr + 2;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 2;\n\tptr2 = ptr2 + 2;\n\tgoto ;\n\t\n}\nvst2Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n \tptr2:4 = &Dreg + (regInc * 8);\n@else # ENDIAN == \"big\"\n \tptr2:4 = &Dreg - (regInc * 8);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 2;\n\n\t*:4 mult_addr = *[register]:4 ptr1;\n\tmult_addr = mult_addr + 4;\n\t*:4 mult_addr = *[register]:4 ptr2;\n\tmult_addr = mult_addr + 4;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 4;\n\tptr2 = ptr2 + 4;\n\tgoto ;\n\t\n}\n\nbuildVst2DdListA:\t\t\t\t\t\t\tis counter=0\t\t\t\t\t\t\t\t{ }\nbuildVst2DdListA: vst2Dd,buildVst2DdListA\tis vst2Dd & buildVst2DdListA & esize0607\t[ counter=counter-1; regNum=regNum+1; ] \n{\n\tbuild vst2Dd;\n\tbuild buildVst2DdListA;\n}\n\nbuildVst2DdListB:\t\t\t\t\t\t\tis counter2=0\t\t\t\t\t\t\t\t{ }\nbuildVst2DdListB: Dreg2\t\t\t\t\t\tis Dreg2 & counter2=1 & esize0607\t\t\t[ counter2=0; reg2Num=reg2Num+1; ] { }\nbuildVst2DdListB: Dreg2,buildVst2DdListB\tis Dreg2 & buildVst2DdListB & esize0607\t\t[ counter2=counter2-1; reg2Num=reg2Num+1; ] { }\n\nvst2DdList: \"{\"^buildVst2DdListA^buildVst2DdListB^\"}\"\tis TMode=0 & c0811=8 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; }\nvst2DdList: \"{\"^buildVst2DdListA^buildVst2DdListB^\"}\"\tis TMode=0 & c0811=9 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; }\nvst2DdList: \"{\"^buildVst2DdListA^buildVst2DdListB^\"}\"\tis TMode=0 & c0811=3 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; export 4:4; }\nvst2DdList: \"{\"^buildVst2DdListA^buildVst2DdListB^\"}\"\tis TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; }\nvst2DdList: \"{\"^buildVst2DdListA^buildVst2DdListB^\"}\"\tis TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; }\nvst2DdList: \"{\"^buildVst2DdListA^buildVst2DdListB^\"}\"\tis TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; export 4:4; }\n\n\n@define Vst2DdList \"(c0811=3 | c0811=8 | c0811=9)\"\n@define T_Vst2DdList \"(thv_c0811=3 | thv_c0811=8 | thv_c0811=9)\"\n\n:vst2.^esize0607 vst2DdList,RnAligned45\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0607<3 & c0003=15 & $(Vst2DdList) ) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0607<3 & thv_c0003=15 & $(T_Vst2DdList) ) ) & RnAligned45 & esize0607 & vst2DdList\n{\n \tmult_addr = RnAligned45;\n \tbuild vst2DdList;\n}\n\n:vst2.^esize0607 vst2DdList,RnAligned45^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0607<3 & c0003=13 & $(Vst2DdList) ) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0607<3 & thv_c0003=13 & $(T_Vst2DdList) ) ) & RnAligned45 & esize0607 & vst2DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vst2DdList;\n\tRnAligned45 = RnAligned45 + (8 * vst2DdList);\n}\n\n:vst2.^esize0607 vst2DdList,RnAligned45,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0607<3 & $(Vst2DdList) ) |\n\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0607<3 & $(T_Vst2DdList) ) ) & RnAligned45 & VRm & esize0607 & vst2DdList\n{\n\tmult_addr = RnAligned45;\n\tbuild vst2DdList;\n\tRnAligned45 = RnAligned45 + VRm;\n}\n\n#######\n# VST2 (single 2-element structure to one lane)\n#\n\nvst2DdElement2: Dreg^\"[\"^vld2Index^\"]\"\tis Dreg & vld2Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dreg + vld2Index;\n\t*:1 mult_addr = *[register]:1 ptr;\n}\n\nvst2DdElement2: Dreg^\"[\"^vld2Index^\"]\"\tis Dreg & vld2Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dreg + (vld2Index * 2);\n\t*:2 mult_addr = *[register]:2 ptr;\n}\n\nvst2DdElement2: Dreg^\"[\"^vld2Index^\"]\"\tis Dreg & vld2Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dreg + (vld2Index * 4);\n\t*:4 mult_addr = *[register]:4 ptr;\n}\n\nvst2Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { }\nvst2Align2: \":16\" is TMode=0 & c1011=0 & c0404=1 { }\nvst2Align2: \":32\" is TMode=0 & c1011=1 & c0404=1 { }\nvst2Align2: \":64\" is TMode=0 & c1011=2 & c0405=1 { }\nvst2Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { }\nvst2Align2: \":16\" is TMode=1 & thv_c1011=0 & thv_c0404=1 { }\nvst2Align2: \":32\" is TMode=1 & thv_c1011=1 & thv_c0404=1 { }\nvst2Align2: \":64\" is TMode=1 & thv_c1011=2 & thv_c0405=1 { }\n\nvst2RnAligned2: \"[\"^VRn^vst2Align2^\"]\" \tis VRn & vst2Align2\t{ export VRn; }\n\nbuildVst2DdList2:\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVst2DdList2: vst2DdElement2\tis counter=1 & vst2DdElement2\t\t[ counter=0; regNum=regNum+regInc; ]\n{\n\tbuild vst2DdElement2;\n}\nbuildVst2DdList2: vst2DdElement2,buildVst2DdList2\t\tis vst2DdElement2 & buildVst2DdList2 & esize1011\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tbuild vst2DdElement2;\n\tmult_addr = mult_addr + esize1011;\n\tbuild buildVst2DdList2;\n}\n\nvst2DdList2: \"{\"^buildVst2DdList2^\"}\"\tis TMode=0 & D22 & c1215 & buildVst2DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single\nvst2DdList2: \"{\"^buildVst2DdList2^\"}\"\tis TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst2DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double\nvst2DdList2: \"{\"^buildVst2DdList2^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & buildVst2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single\nvst2DdList2: \"{\"^buildVst2DdList2^\"}\"\tis TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVst2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double\n\n:vst2.^esize1011 vst2DdList2,vst2RnAligned2\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 & c0003=15 ) |\n ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 & thv_c0003=15 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 \n{\n\tmult_addr = vst2RnAligned2;\n\tbuild vst2DdList2;\n}\n\n:vst2.^esize1011 vst2DdList2,vst2RnAligned2^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 & c0003=13 ) |\n ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 & thv_c0003=13 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2\n{\n\tmult_addr = vst2RnAligned2;\n\tbuild vst2DdList2;\n\tvst2RnAligned2 = vst2RnAligned2 + (2 * esize1011);\n}\n\n:vst2.^esize1011 vst2DdList2,vst2RnAligned2,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 ) |\n ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 & VRm\n{\n\tmult_addr = vst2RnAligned2;\n\tbuild vst2DdList2;\n\tvst2RnAligned2 = vst2RnAligned2 + VRm;\n}\n\n\n#######\n# VST3\n#\n\n#######\n# VST3 (multiple 3-element structures)\n#\n\n\nvst3Align: is TMode=0 & c0404=0 { }\nvst3Align: \":64\" is TMode=0 & c0404=1 { }\nvst3Align: is TMode=1 & thv_c0404=0 { }\nvst3Align: \":64\" is TMode=1 & thv_c0404=1 { }\n\n\nvst3RnAligned: \"[\"^VRn^vst3Align^\"]\" \tis VRn & vst3Align\t{ export VRn; }\n\nvst3Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 8;\n\n\t*:1 mult_addr = *[register]:1 ptr1;\n\tmult_addr = mult_addr + 1;\n\t*:1 mult_addr = *[register]:1 ptr2;\n\tmult_addr = mult_addr + 1;\n\t*:1 mult_addr = *[register]:1 ptr3;\n\tmult_addr = mult_addr + 1;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 1;\n\tptr2 = ptr2 + 1;\n\tptr3 = ptr3 + 1;\n\tgoto ;\n\n}\nvst3Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 4;\n\n\t*:2 mult_addr = *[register]:2 ptr1;\n\tmult_addr = mult_addr + 2;\n\t*:2 mult_addr = *[register]:2 ptr2;\n\tmult_addr = mult_addr + 2;\n\t*:2 mult_addr = *[register]:2 ptr3;\n\tmult_addr = mult_addr + 2;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 2;\n\tptr2 = ptr2 + 2;\n\tptr3 = ptr3 + 2;\n\tgoto ;\n\n}\nvst3Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 2;\n\n\t*:4 mult_addr = *[register]:4 ptr1;\n\tmult_addr = mult_addr + 4;\n\t*:4 mult_addr = *[register]:4 ptr2;\n\tmult_addr = mult_addr + 4;\n\t*:4 mult_addr = *[register]:4 ptr3;\n\tmult_addr = mult_addr + 4;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 4;\n\tptr2 = ptr2 + 4;\n\tptr3 = ptr3 + 4;\n\tgoto ;\n\n}\n\n# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start\nbuildvst3DdList:\t\t\t\t\t\t\tis counter=0 & vst3Dd\t[ regNum=regNum-3*regInc; ]\n{\n\tbuild vst3Dd;\n}\nbuildvst3DdList: Dreg^buildvst3DdList\t\tis counter=1 & Dreg\t& buildvst3DdList\t[ counter=0; regNum=regNum+regInc; ] { }\nbuildvst3DdList: Dreg,buildvst3DdList\t\tis Dreg & buildvst3DdList\t[ counter=counter-1; regNum=regNum+regInc; ] { }\n\nvst3DdList: \"{\"^buildvst3DdList^\"}\"\tis TMode=0 & c0811=4 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single\nvst3DdList: \"{\"^buildvst3DdList^\"}\"\tis TMode=0 & c0811=5 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double\nvst3DdList: \"{\"^buildvst3DdList^\"}\"\tis TMode=1 & thv_c0811=4 & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single\nvst3DdList: \"{\"^buildvst3DdList^\"}\"\tis TMode=1 & thv_c0811=5 & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double\n\n\n:vst3.^esize0607 vst3DdList,vst3RnAligned\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=15 ) |\n ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0003=15 ) ) & vst3RnAligned & esize0607 & vst3DdList\n{\n\tmult_addr = vst3RnAligned;\n\tbuild vst3DdList;\n}\n\n:vst3.^esize0607 vst3DdList,vst3RnAligned^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=13 ) |\n ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0003=13 ) ) & vst3RnAligned & esize0607 & vst3DdList\n{\n\tmult_addr = vst3RnAligned;\n\tbuild vst3DdList;\n\tvst3RnAligned = vst3RnAligned + (8 * 3);\n}\n\n:vst3.^esize0607 vst3DdList,vst3RnAligned,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0) |\n ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 ) ) & vst3RnAligned & esize0607 & vst3DdList & VRm\n{\n\tmult_addr = vst3RnAligned;\n\tbuild vst3DdList;\n\tvst3RnAligned = vst3RnAligned + VRm;\n}\n\n\n#######\n# VST3 (single 3-element structure to one lane)\n#\n\nvst3Rn: \"[\"^VRn^\"]\"\tis VRn\t{ export VRn; }\n\nvst3DdElement2: Dreg^\"[\"^vld3Index^\"]\"\tis Dreg & vld3Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dreg + vld3Index;\n\t*:1 mult_addr = *[register]:1 ptr;\n}\n\nvst3DdElement2: Dreg^\"[\"^vld3Index^\"]\"\tis Dreg & vld3Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dreg + (vld3Index * 2);\n\t*:2 mult_addr = *[register]:2 ptr;\n}\n\nvst3DdElement2: Dreg^\"[\"^vld3Index^\"]\"\tis Dreg & vld3Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dreg + (vld3Index * 4);\n\t*:4 mult_addr = *[register]:4 ptr;\n}\n\n\nbuildVst3DdList2:\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVst3DdList2: vst3DdElement2\tis counter=1 & vst3DdElement2\t\t[ counter=0; regNum=regNum+regInc; ]\n{\n\tbuild vst3DdElement2;\n}\nbuildVst3DdList2: vst3DdElement2,buildVst3DdList2\t\tis vst3DdElement2 & buildVst3DdList2 & esize1011\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tbuild vst3DdElement2;\n\tmult_addr = mult_addr + esize1011;\n\tbuild buildVst3DdList2;\n}\n\nvst3DdList2: \"{\"^buildVst3DdList2^\"}\"\tis TMode=0 & D22 & c1215 & buildVst3DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single\nvst3DdList2: \"{\"^buildVst3DdList2^\"}\"\tis TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst3DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double\nvst3DdList2: \"{\"^buildVst3DdList2^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & buildVst3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single\nvst3DdList2: \"{\"^buildVst3DdList2^\"}\"\tis TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVst3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double\n\n:vst3.^esize1011 vst3DdList2,vst3Rn\t\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 & c0003=15 ) |\n ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15 ) ) & vst3Rn & esize1011 & vst3DdList2 \n{\n\tmult_addr = vst3Rn;\n\tbuild vst3DdList2;\n}\n\n:vst3.^esize1011 vst3DdList2,vst3Rn^\"!\"\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 & c0003=13 ) |\n ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13 ) ) & vst3Rn & esize1011 & vst3DdList2\n{\n\tmult_addr = vst3Rn;\n\tbuild vst3DdList2;\n\tvst3Rn = vst3Rn + (3 * esize1011);\n}\n\n:vst3.^esize1011 vst3DdList2,vst3Rn,VRm\tis ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 ) |\n ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 ) ) & vst3Rn & esize1011 & vst3DdList2 & VRm\n{\n\tmult_addr = vst3Rn;\n\tbuild vst3DdList2;\n\tvst3Rn = vst3Rn + VRm;\n}\n\n#######\n# VST4 (multiple 4-element structures)\n#\n\nvst4Align: is TMode=0 & c0405=0 { }\nvst4Align: \":64\" is TMode=0 & c0405=1 { }\nvst4Align: \":128\" is TMode=0 & c0405=2 { }\nvst4Align: \":256\" is TMode=0 & c0405=3 { }\nvst4Align: is TMode=1 & thv_c0405=0 { }\nvst4Align: \":64\" is TMode=1 & thv_c0405=1 { }\nvst4Align: \":128\" is TMode=1 & thv_c0405=2 { }\nvst4Align: \":256\" is TMode=1 & thv_c0405=3 { }\n\nvst4RnAligned: \"[\"^VRn^vst4Align^\"]\" \tis VRn & vst4Align\t{ export VRn; }\n\nvst4Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n\tptr4:4 = &Dreg + (regInc * 24);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n\tptr4:4 = &Dreg - (regInc * 24);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 8;\n\n\t*:1 mult_addr = *[register]:1 ptr1;\n\tmult_addr = mult_addr + 1;\n\t*:1 mult_addr = *[register]:1 ptr2;\n\tmult_addr = mult_addr + 1;\n\t*:1 mult_addr = *[register]:1 ptr3;\n\tmult_addr = mult_addr + 1;\n\t*:1 mult_addr = *[register]:1 ptr4;\n\tmult_addr = mult_addr + 1;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 1;\n\tptr2 = ptr2 + 1;\n\tptr3 = ptr3 + 1;\n\tptr4 = ptr4 + 1;\n\tgoto ;\n\n}\nvst4Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n\tptr4:4 = &Dreg + (regInc * 24);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n\tptr4:4 = &Dreg - (regInc * 24);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 4;\n\n\t*:2 mult_addr = *[register]:2 ptr1;\n\tmult_addr = mult_addr + 2;\n\t*:2 mult_addr = *[register]:2 ptr2;\n\tmult_addr = mult_addr + 2;\n\t*:2 mult_addr = *[register]:2 ptr3;\n\tmult_addr = mult_addr + 2;\n\t*:2 mult_addr = *[register]:2 ptr4;\n\tmult_addr = mult_addr + 2;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 2;\n\tptr2 = ptr2 + 2;\n\tptr3 = ptr3 + 2;\n\tptr4 = ptr4 + 2;\n\tgoto ;\n\n}\nvst4Dd: Dreg\t\tis Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & regInc\n{\n\tptr1:4 = &Dreg;\n@if ENDIAN == \"little\"\n\tptr2:4 = &Dreg + (regInc * 8);\n\tptr3:4 = &Dreg + (regInc * 16);\n\tptr4:4 = &Dreg + (regInc * 24);\n@else # ENDIAN == \"big\"\n\tptr2:4 = &Dreg - (regInc * 8);\n\tptr3:4 = &Dreg - (regInc * 16);\n\tptr4:4 = &Dreg - (regInc * 24);\n@endif # ENDIAN = \"big\"\n\tmult_dat8 = 2;\n\n\t*:4 mult_addr = *[register]:4 ptr1;\n\tmult_addr = mult_addr + 4;\n\t*:4 mult_addr = *[register]:4 ptr2;\n\tmult_addr = mult_addr + 4;\n\t*:4 mult_addr = *[register]:4 ptr3;\n\tmult_addr = mult_addr + 4;\n\t*:4 mult_addr = *[register]:4 ptr4;\n\tmult_addr = mult_addr + 4;\n\tmult_dat8 = mult_dat8 - 1;\n\tif(mult_dat8 == 0) goto ;\n\tptr1 = ptr1 + 4;\n\tptr2 = ptr2 + 4;\n\tptr3 = ptr3 + 4;\n\tptr4 = ptr4 + 4;\n\tgoto ;\n\n}\n\n# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start\nbuildVst4DdList:\t\t\t\t\t\t\tis counter=0 & vst4Dd\t[ regNum=regNum-4*regInc; ]\n{\n\tbuild vst4Dd;\n}\nbuildVst4DdList: Dreg^buildVst4DdList\t\tis counter=1 & Dreg & buildVst4DdList\t[ counter=0; regNum=regNum+regInc; ] { }\nbuildVst4DdList: Dreg,buildVst4DdList\t\tis Dreg & buildVst4DdList\t[ counter=counter-1; regNum=regNum+regInc; ] { }\n\nvst4DdList: \"{\"^buildVst4DdList^\"}\"\tis TMode=0 & c0808=0 & D22 & c1215 & buildVst4DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single\nvst4DdList: \"{\"^buildVst4DdList^\"}\"\tis TMode=0 & c0808=1 & D22 & c1215 & buildVst4DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double\nvst4DdList: \"{\"^buildVst4DdList^\"}\"\tis TMode=1 & thv_c0808=0 & thv_D22 & thv_c1215 & buildVst4DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single\nvst4DdList: \"{\"^buildVst4DdList^\"}\"\tis TMode=1 & thv_c0808=1 & thv_D22 & thv_c1215 & buildVst4DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double\n\n:vst4.^esize0607 vst4DdList,vst4RnAligned\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3 & c0003=15) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15) ) & vst4RnAligned & esize0607 & vst4DdList\n{\n\tmult_addr = vst4RnAligned;\n\tbuild vst4DdList;\n}\n\n:vst4.^esize0607 vst4DdList,vst4RnAligned^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3 & c0003=13) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13) ) & vst4RnAligned & esize0607 & vst4DdList\n{\n\tmult_addr = vst4RnAligned;\n\tbuild vst4DdList;\n\tvst4RnAligned = vst4RnAligned + (8 * 4);\n}\n\n:vst4.^esize0607 vst4DdList,vst4RnAligned,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3) ) & VRm & vst4RnAligned & esize0607 & vst4DdList\n{\n\tmult_addr = vst4RnAligned;\n\tbuild vst4DdList;\n\tvst4RnAligned = vst4RnAligned + VRm;\n}\n\n#######\n# VST4 (single 4-element structure from one lane)\n#\n\nvst4Index: val\tis TMode=0 & c0507 & c1011\t[ val = c0507 >> c1011; ]\t{ tmp:4 = val; export tmp; }\nvst4Index: val\tis TMode=1 & thv_c0507 & thv_c1011\t[ val = thv_c0507 >> thv_c1011; ]\t{ tmp:4 = val; export tmp; }\n\n\nvst4DdElement2: Dreg^\"[\"^vst4Index^\"]\"\tis Dreg & vst4Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0))\n{\n\tptr:4 = &Dreg + vst4Index;\n\t*:1 mult_addr = *[register]:1 ptr;\n}\n\nvst4DdElement2: Dreg^\"[\"^vst4Index^\"]\"\tis Dreg & vst4Index & TMode=0 & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1))\n{\n\tptr:4 = &Dreg + vst4Index;\n\t*:2 mult_addr = *[register]:2 ptr;\n}\n\nvst4DdElement2: Dreg^\"[\"^vst4Index^\"]\"\tis Dreg & vst4Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2))\n{\n\tptr:4 = &Dreg + vst4Index;\n\t*:4 mult_addr = *[register]:4 ptr;\n}\n\nvst4DdElement2: Dreg^\"[\"^vst4Index^\"]\"\tis Dreg & vst4Index & ((TMode=0 & c1011=3) | (TMode=1 & thv_c1011=3))\n{\n\t*mult_addr = Dreg;\n}\n\nvst4Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { }\nvst4Align2: \":32\" is TMode=0 & c1011=0 & c0404=1 { }\nvst4Align2: \":64\" is TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1)) { }\nvst4Align2: \":128\" is TMode=0 & c1011=2 & c0405=2 { }\nvst4Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { }\nvst4Align2: \":32\" is TMode=1 & thv_c1011=0 & thv_c0404=1 { }\nvst4Align2: \":64\" is TMode=1 & ((thv_c1011=1 & thv_c0404=1) | (thv_c1011=2 & thv_c0405=1)) { }\nvst4Align2: \":128\" is TMode=1 & thv_c1011=2 & thv_c0405=2 { }\n\nvst4RnAligned2: \"[\"^VRn^vst4Align2^\"]\" \tis VRn & vst4Align2\t{ export VRn; }\n\nbuildVst4DdList2:\t\t\t\t\tis counter=0\t\t\t{ }\nbuildVst4DdList2: vst4DdElement2\tis counter=1 & vst4DdElement2\t\t[ counter=0; regNum=regNum+regInc; ] { build vst4DdElement2; }\nbuildVst4DdList2: vst4DdElement2,buildVst4DdList2\t\tis vst4DdElement2 & buildVst4DdList2 & esize1011\t[ counter=counter-1; regNum=regNum+regInc; ]\n{\n\tbuild vst4DdElement2;\n\tmult_addr = mult_addr + esize1011;\n\tbuild buildVst4DdList2;\n}\n\nvst4DdList2: \"{\"^buildVst4DdList2^\"}\"\tis TMode=0 & D22 & c1215 & buildVst4DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single\nvst4DdList2: \"{\"^buildVst4DdList2^\"}\"\tis TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst4DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double\nvst4DdList2: \"{\"^buildVst4DdList2^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & buildVst4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single\nvst4DdList2: \"{\"^buildVst4DdList2^\"}\"\tis TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVst4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double\n\n:vst4.^esize1011 vst4DdList2,vst4RnAligned2\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=3 & c0003=15) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=3 & thv_c0003=15) ) & vst4RnAligned2 & esize1011 & vst4DdList2\n{\n\tmult_addr = vst4RnAligned2;\n\tbuild vst4DdList2;\n}\n\n:vst4.^esize1011 vst4DdList2,vst4RnAligned2^\"!\"\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=3 & c0003=13) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=3 & thv_c0003=13) ) & vst4RnAligned2 & esize1011 & vst4DdList2\n{\n\tmult_addr = vst4RnAligned2;\n\tbuild vst4DdList2;\n\tvst4RnAligned2 = vst4RnAligned2 + (4 * esize1011);\n}\n:vst4.^esize1011 vst4DdList2,vst4RnAligned2,VRm\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=3) |\n\t\t\t\t\t\t\t\t\t\t\t\t\t ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=3) ) & VRm & vst4RnAligned2 & esize1011 & vst4DdList2\n{\n\tmult_addr = vst4RnAligned2;\n\tbuild vst4DdList2;\n\tvst4RnAligned2 = vst4RnAligned2 + VRm;\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)\n\n#######\n# VSTM (A1)\n#\n\nbuildVstmDdList:\t\t\t\t\t\tis counter=0\t\t\t\t{ }\nbuildVstmDdList: Dreg\t\t\t\t\tis counter=1 & Dreg\t\t[ counter=0; regNum=regNum+1; ]\n{\n\t*mult_addr = Dreg;\n\tmult_addr = mult_addr + 8;\n}\nbuildVstmDdList: Dreg,buildVstmDdList\tis Dreg & buildVstmDdList\t[ counter=counter-1; regNum=regNum+1; ]\n{\n\t*mult_addr = Dreg;\n\tmult_addr = mult_addr + 8;\n\tbuild buildVstmDdList;\n}\n\nvstmDdList: \"{\"^buildVstmDdList^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVstmDdList [ regNum=(D22<<4)+c1215-1; counter=c0007>>1; ] { }\nvstmDdList: \"{\"^buildVstmDdList^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVstmDdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007>>1; ] { }\n\n:vstmia^COND vldmRn,vstmDdList\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c2121 & c2020=0 & c0811=11 & c0000=0) | \n ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=0 & thv_c0811=11 & thv_c0000=0) ) & vldmRn & vstmDdList & vldmOffset & vldmUpdate\n{\n\tmult_addr = vldmRn;\n\tbuild vstmDdList;\n\tbuild vldmUpdate;\n}\n\n:vstmdb^COND vldmRn,vstmDdList\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=0 & c0811=11 & c0000=0) | \n ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=0 & thv_c0811=11 & thv_c0000=0) ) & vldmRn & vstmDdList & vldmOffset\n{\n\tlocal start_addr = vldmRn - vldmOffset;\n\tmult_addr = start_addr;\n\tbuild vstmDdList;\n\tvldmRn = start_addr;\n}\n\n@endif # VFPv2 | VFPv3 | SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n#######\n# VSTM (A2)\n#\n\nbuildVstmSdList:\t\t\t\t\t\tis counter=0\t\t\t\t{ }\nbuildVstmSdList: Sreg\t\t\t\t\tis counter=1 & Sreg\t\t[ counter=0; regNum=regNum+1; ]\n{\n\t*mult_addr = Sreg;\n\tmult_addr = mult_addr + 4;\n}\nbuildVstmSdList: Sreg,buildVstmSdList\tis Sreg & buildVstmSdList\t[ counter=counter-1; regNum=regNum+1; ]\n{\n\t*mult_addr = Sreg;\n\tmult_addr = mult_addr + 4;\n\tbuild buildVstmSdList;\n}\n\nvstmSdList: \"{\"^buildVstmSdList^\"}\"\tis TMode=0 & D22 & c1215 & c0007 & buildVstmSdList [ regNum=(c1215<<1) + D22 -1; counter=c0007; ] { }\nvstmSdList: \"{\"^buildVstmSdList^\"}\"\tis TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVstmSdList [ regNum=(thv_c1215<<1) + thv_D22 -1; counter=thv_c0007; ] { }\n\n:vstmia^COND vldmRn,vstmSdList\tis COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x19 & c2121 & c2020=0 & c0811=10 ) |\n ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=0 & thv_c0811=10 ) ) & vldmRn & vstmSdList & vldmOffset & vldmUpdate\n{\n\tmult_addr = vldmRn;\n\tbuild vstmSdList;\n\tbuild vldmUpdate;\n}\n\n:vstmdb^COND vldmRn,vstmSdList\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=0 & c0811=10 ) |\n ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=0 & thv_c0811=10) ) & vldmRn & vstmSdList & vldmOffset\n{\n\tlocal start_addr = vldmRn - vldmOffset;\n\tmult_addr = start_addr;\n\tbuild vstmSdList;\n\tvldmRn = start_addr;\n}\n\n\n#######\n# VSTR\n#\n\n:vstr^COND^\".64\" Dd,vldrRn\tis COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=0 & c0811=11) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=0 & thv_c0811=11)) & Dd & vldrRn\n{\n\t*vldrRn = Dd;\n}\n\n:vstr^COND^\".32\" Sd,vldrRn\tis COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=0 & c0811=10) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=0 & thv_c0811=10)) & Sd & vldrRn\n{\n\t*vldrRn = Sd;\n}\n\n@endif # VFPv2 || VFPv3 || SIMD\n\n\n#######\n# VSUB\n#\n\n@if defined(SIMD)\n\ndefine pcodeop FloatVectorSub;\ndefine pcodeop VectorSubAndNarrow;\n\n:vsub.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=8 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dn & Dd & Dm\n{\n\tDd = VectorSub(Dn,Dm,esize2021);\n}\n\n:vsub.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=8 & Q6=1 & c0404=0) |\n ($(TMODE_F) &thv_c2327=0x1e & thv_c0811=8 & thv_Q6=1 & thv_c0404=0) ) & esize2021 & Qm & Qn & Qd\n{\n\tQd = VectorSub(Qn,Qm,esize2021);\n}\n\n:vsub.f32 Dd,Dn,Dm\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=0 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Dd \n{\n\tDd = FloatVectorSub(Dn,Dm,2:1,32:1);\n}\n\n:vsub.f32 Qd,Qn,Qm\t\tis ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_Q6=1 & thv_c0404=0) ) & Qn & Qd & Qm\n{\n\tQd = FloatVectorSub(Qn,Qm,2:1,32:1);\n}\n\n:vsubhn.i^esize2021x2 Dd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=6 & Q6=0 & c0404=0) |\n \t\t ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=6 & thv_Q6=0 & thv_c0404=0)) & esize2021x2 & Dd & Qn & Qm\n{\n\tDd = VectorSubAndNarrow(Qn,Qm,esize2021x2);\n}\n\n:vsubl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=2 & c0606=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=2 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Dn & Qd & Dm\n{\n\tQd = VectorSub(Dn,Dm,esize2021,udt);\n}\n\n:vsubw.^udt^esize2021 Qd,Qn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=3 & c0606=0 & c0404=0) |\n ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=3 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Qn & Qd & Dm\n{\n\tQd = VectorSub(Qn,Dm,esize2021,udt);\n}\n\n@endif # SIMD\n\n@if defined(VFPv2) || defined(VFPv3)\n\n:vsub^COND^\".f32\" Sd,Sn,Sm\t\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=10 & c0606=1 & c0404=0) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd\n{\n\tbuild COND;\n\tbuild Sd;\n\tbuild Sm;\n\tbuild Sn;\n\tSd = Sn f- Sm;\n}\n\n:vsub^COND^\".f64\" Dd,Dn,Dm\t\tis COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=11 & c0606=1 & c0404=0 ) |\n ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd\n{\n\tbuild COND;\n\tbuild Dd;\n\tbuild Dm;\n\tbuild Dn;\n\tDd = Dn f- Dm;\n}\n\n@endif # VFPv2 || VFPv3\n\n@if defined(SIMD)\n\n\n#######\n# VSWP\n#\n\n:vswp Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=0 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm\n{\n\ttmp:8 = Dm;\n\tDm = Dd;\n\tDd = tmp;\n}\n\n:vswp Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=0 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm\n{\n\ttmp:16 = Qm;\n\tQm = Qd;\n\tQd = tmp;\n}\n\n\n###########\n# VTBL/VTBX\n#\n\ndefine pcodeop VectorTableLookup;\n\nbuildVtblDdList:\t\t\t\t\t\t is counter=0\t\t\t\t\t\t\t{ }\nbuildVtblDdList: Dreg\t\t\t\t\tis Dreg & counter=1 \t\t [ counter=0; regNum=regNum+1; ] { }\nbuildVtblDdList: Dreg,buildVtblDdList\tis Dreg & buildVtblDdList [ counter=counter-1; regNum=regNum+1; ] \n{\n\tbuild buildVtblDdList;\n}\n\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=0 & c0809=0 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=1; ] { export 1:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=0 & c0809=1 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=2; ] { export 2:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=0 & c0809=2 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=3; ] { export 3:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=0 & c0809=3 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=4; ] { export 4:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=1 & thv_c0809=0 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=1; ] { export 1:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=1 & thv_c0809=1 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=2; ] { export 2:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=1 & thv_c0809=2 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=3; ] { export 3:4; }\nvtblDdList: \"{\"^buildVtblDdList^\"}\"\tis TMode=1 & thv_c0809=3 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=4; ] { export 4:4; }\n\n\n:vtbl.8 VRd,vtblDdList,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1011=2 & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1011=2 & thv_c0606=0 & thv_c0404=0 ) ) & VRm & VRd & VRn & vtblDdList\n{\n\tVRd = VectorTableLookup(VRm,VRn,vtblDdList);\n}\n\n:vtbx.8 VRd,vtblDdList,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1011=2 & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1011=2 & thv_c0606=1 & thv_c0404=0 ) ) & VRm & VRd & VRn & vtblDdList\n{\n\tVRd = VectorTableLookup(VRm,VRn,vtblDdList);\n}\n\n\n######\n# VTST\n#\n\ndefine pcodeop VectorTest;\n\n:vtst.^esize2021 Qd, Qn, Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & c0606=1 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd\n{\n Qd = VectorTest(Qn, Qm);\n}\n\n:vtst.^esize2021 Dd, Dn, Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & c0606=0 & c0404=1) |\n ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & esize2021 & Dm & Dn & Dd\n{\n Dd = VectorTest(Dn, Dm);\n}\n\ndefine pcodeop VectorTranspose;\n\n:vtrn^\".\"^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=2 & c0811=0 & c0707=1 & Q6=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=2 & thv_c0811=0 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0)) & esize1819 & Dd & Dm\n{\n\tDd = VectorTranspose(Dm,esize1819);\n}\n\n:vtrn^\".\"^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=2 & c0811=0 & c0707=1 & Q6=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=2 & thv_c0811=0 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd\n{\n\tQd = VectorTranspose(Qm,esize1819);\n}\n\n#####\n# V[SU]DOT\ndefine pcodeop VectorSignedDotProduct;\ndefine pcodeop VectorUnsignedDotProduct;\ndefine pcodeop VectorSignedUnsignedDotProduct;\ndefine pcodeop VectorUnsignedSignedDotProduct;\n\n:vsdot.s8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm0 & Mindex & Dn & Dd\n{\n\tDd = VectorSignedDotProduct(Dn,Dm0,Mindex);\n}\n\n:vsdot.s8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Dm0 & Mindex & Qn & Qd\n{\n\tQd = VectorSignedDotProduct(Qn,Dm0,Mindex);\n}\n\n:vsdot.s8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd\n{\n\tDd = VectorSignedDotProduct(Dn,Dm);\n}\n\n:vsdot.s8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm & Qn & Qd\n{\n\tQd = VectorSignedDotProduct(Qn,Qm);\n}\n\n:vudot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm0 & Mindex & Dn & Dd\n{\n\tDd = VectorUnsignedDotProduct(Dn,Dm0,Mindex);\n}\n\n:vudot.u8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Dm0 & Mindex & Qn & Qd\n{\n\tQd = VectorUnsignedDotProduct(Qn,Dm0,Mindex);\n}\n\n:vudot.u8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm & Dn & Dd\n{\n\tDd = VectorUnsignedDotProduct(Dn,Dm);\n}\n\n:vudot.u8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Qm & Qn & Qd\n{\n\tQd = VectorUnsignedDotProduct(Qn,Qm);\n}\n\n:vsudot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=0 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm0 & Mindex & Dn & Dd\n{\n\tDd = VectorSignedUnsignedDotProduct(Dn,Dm0,Mindex);\n}\n\n:vsudot.u8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=1 & c0404=1) |\n ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Dm0 & Mindex & Qn & Qd\n{\n\tQd = VectorSignedUnsignedDotProduct(Qn,Dm0,Mindex);\n}\n\n:vusdot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm0 & Mindex & Dn & Dd\n{\n\tDd = VectorUnsignedSignedDotProduct(Dn,Dm0,Mindex);\n}\n\n:vusdot.u8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Dm0 & Mindex & Qn & Qd\n{\n\tQd = VectorUnsignedSignedDotProduct(Qn,Dm0,Mindex);\n}\n\n:vusdot.u8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xd & c0606=0 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd\n{\n\tDd = VectorUnsignedSignedDotProduct(Dn,Dm);\n}\n\n:vusdot.u8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xd & c0606=1 & c0404=0) |\n ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm & Qn & Qd\n{\n\tQd = VectorUnsignedSignedDotProduct(Qn,Qm);\n}\n\n#######\n# VUZP\n#\n\ndefine pcodeop VectorUnzip;\n\n:vuzp^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=0 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819\n{\n\tDd = VectorUnzip(Dm,esize1819);\n}\n\n:vuzp^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=1 & c0404=0 ) |\n ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819\n{\n\tQd = VectorUnzip(Qm,esize1819);\n}\n\n\n#######\n# VZIP\n#\n\ndefine pcodeop VectorZip;\n\n:vzip^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=0 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819\n{\n\tDd = VectorZip(Dm,esize1819);\n}\n\n:vzip^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=1 & c0404=0 ) |\n ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819\n{\n\tQd = VectorZip(Qm,esize1819);\n}\n\n\n@endif # SIMD\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMt.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMtTHUMB.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMt_v45.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMt_v6.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/ARM/data/languages/ARMv8.sinc", "content": "\n# This macro is always defined in this file, but the ifdef may be\n# useful if it is moved to ARMinstructions.sinc.\n\ncrc32_type: \"b\"\t\tis TMode=0 & c2122=0b00 & c0909=0 { }\ncrc32_type: \"h\"\t\tis TMode=0 & c2122=0b01 & c0909=0 { }\ncrc32_type: \"w\"\t\tis TMode=0 & c2122=0b10 & c0909=0 { }\ncrc32_type: \"cb\"\tis TMode=0 & c2122=0b00 & c0909=1 { }\ncrc32_type: \"ch\"\tis TMode=0 & c2122=0b01 & c0909=1 { }\ncrc32_type: \"cw\"\tis TMode=0 & c2122=0b10 & c0909=1 { }\ncrc32_type: \"b\"\t\tis TMode=1 & thv_c0405=0b00 { }\ncrc32_type: \"h\"\t\tis TMode=1 & thv_c0405=0b01 { }\ncrc32_type: \"w\"\t\tis TMode=1 & thv_c0405=0b10 { }\n\ndefine pcodeop Crc32Calc;\n\n# F5.1.39,40 p7226,7229 CRC32,CRC32C A1\n:crc32^crc32_type\tRd,Rn,Rm\n\tis TMode=0 & c2831=0b1110 & c2327=0b00010 & c2020=0 & c0407=0b0100 & c1011=0b00 & c0808=0\n\t& crc32_type & Rn & Rd & Rm\n\t{ Rd = Crc32Calc(Rn,Rm); }\n\n# F5.1.39 p7226 CRC32 T1\n:crc32^crc32_type\tthv_Rt2,thv_Rn,thv_Rm\n\tis TMode=1 & thv_c2031=0b111110101100 & thv_c1215=0b1111 & thv_c0607=0b10\n\t& crc32_type & thv_Rn & thv_Rt2 & thv_Rm\n\t{ thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); }\n\n# F5.1.40 p7229 CRC32C T1\n:crc32c^crc32_type\tthv_Rt2,thv_Rn,thv_Rm\n\tis TMode=1 & thv_c2031=0b111110101101 & thv_c1215=0b1111 & thv_c0607=0b10\n\t& crc32_type & thv_Rn & thv_Rt2 & thv_Rm\n\t{ thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); }\n\ndefine pcodeop DCPSInstruction;\n\ndcps_lev:1\t\tis TMode=1 & thv_c0001=0b01 { export 1:1; }\ndcps_lev:2\t\tis TMode=1 & thv_c0001=0b10 { export 2:1; }\ndcps_lev:3\t\tis TMode=1 & thv_c0001=0b11 { export 3:1; }\n\n# F5.1.43 p7235 DCPS1,DCPS2,DCPS3 DSPS1 variant\n:dcps^dcps_lev\n\tis TMode=1 & thv_c1631=0b1111011110001111 & thv_c0215=0b10000000000000 & (thv_c0101=1 | thv_c0000=1) & dcps_lev\n\t{ DCPSInstruction(dcps_lev:1); }\n\n# F5.1.57 p7268 LDA\n:lda^COND Rd,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xc9f\n\t{\n\t\tbuild COND;\n\t\tRd = *Rn;\n\t}\n\n# F5.1.57 p7268 LDA\n:lda thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1010\n\t& ItCond & thv_Rn & thv_Rt\n\t{\n\t\tbuild ItCond;\n\t\tthv_Rt = *thv_Rn;\n\t}\n\n# F5.1.58 p7270 LDAB\n:ldab^COND Rd,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xc9f\n\t{\n\t\tbuild COND;\n\t\tval:1 = *Rn;\n\t\tRd = zext(val);\n\t}\n\n# F5.1.58 p7270 LDAB\n:ldab thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1000\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\tval:1 = *thv_Rn;\n\t\tthv_Rt = zext(val);\n\t}\n\n# F5.1.59 p7272 LDAEX\n:ldaex^COND Rd,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xe9f\n\t{\n\t\tbuild COND;\n\t\tRd = *Rn;\n\t}\n\n# F5.1.59 p7272 LDAEX\n:ldaex thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1110\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\tthv_Rt = *thv_Rn;\n\t}\n\n# F5.1.60 p7274 LDAEXB\n:ldaexb^COND Rd,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xe9f\n\t{\n\t\tbuild COND;\n\t\tval:1 = *Rn;\n\t\tRd = zext(val);\n\t}\n\n# F5.1.60 p7274 LDAEXB\n:ldaexb thv_Rt,thv_Rn\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1100\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\tval:1 = *thv_Rn;\n\t\tthv_Rt = zext(val);\n\t}\n\n# F5.1.61 p7274 LDAEXD\n:ldaexd^COND Rd,Rd2,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f\n\t{\n\t\tlocal addr:4 = Rn;\n\t\tbuild COND;\n@if ENDIAN == \"big\"\n\t\tRd = *(addr + 4);\n\t\tRd2 = *(addr);\n@else\t# ENDIAN == \"little\"\n\t\tRd = *(addr);\n\t\tRd2 = *(addr + 4);\n@endif\t# ENDIAN == \"little\"\n\t}\n\n# F5.1.61 p7274 LDAEXD\n:ldaexd thv_Rt,thv_Rt2,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111\n\t& ItCond & thv_Rt & thv_Rt2 & thv_Rn\n\t{\n\t\tlocal addr:4 = thv_Rn;\n\t\tbuild ItCond;\n@if ENDIAN == \"big\"\n\t\tthv_Rt = *(addr + 4);\n\t\tthv_Rt2 = *(addr);\n@else\t# ENDIAN == \"little\"\n\t\tthv_Rt = *(addr);\n\t\tthv_Rt2 = *(addr + 4);\n@endif\t# ENDIAN == \"little\"\n\t}\n\n# F5.1.62 p7278 LDAEXH\n:ldaexh^COND Rd,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xe9f\n\t{\n\t\tbuild COND;\n\t\tval:2 = *Rn;\n\t\tRd = zext(val);\n\t}\n\n# F5.1.62 p7278 LDAEXH\n:ldaexh thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1101\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\tval:2 = *thv_Rn;\n\t\tthv_Rt = zext(val);\n\t}\n\n# F5.1.63 p7280 LDAH\n:ldah^COND Rd,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xc9f\n\t{\n\t\tbuild COND;\n\t\tval:2 = *Rn;\n\t\tRd = zext(val);\n\t}\n\n# F5.1.63 p7280 LDAH\n:ldah thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1001\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\tval:2 = *thv_Rn;\n\t\tthv_Rt = zext(val);\n\t}\n\n# F5.1.185 p7573 SEVL A1 variant\n:sevl^COND\n\tis TMode=0 & ARMcond=1 & COND & c1627=0b001100100000 & c0007=0b00000101\n\t{\n\t\tbuild COND;\n\t\tSendEvent();\n\t}\n\n# F5.1.185 p7573 SEVL T2 variant\n:sevl.w\n\tis TMode=1 & thv_c2031=0b111100111010 & thv_c1415=0b10 & thv_c1212=0 & thv_c0010=0b00000000101\n\t& ItCond\n\t{\n\t\tbuild ItCond;\n\t\tSendEvent();\n\t}\n\n# F5.1.217 p7642 STL\n:stl^COND Rm,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & c0415=0xfc9 & Rm\n\t{\n\t\tbuild COND;\n\t\t*Rn = Rm;\n\t}\n\n# F5.1.217 p7642 STL\n:stl thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1010\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\t*thv_Rn = thv_Rt;\n\t}\n\n# F5.1.218 p7644 STLB\n:stlb^COND Rm,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & c0415=0xfc9 & Rm\n\t{\n\t\tbuild COND;\n\t\t*:1 Rn = Rm[0,8];\n\t}\n\n# F5.1.218 p7644 STLB\n:stlb thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1000\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\t*:1 thv_Rn = thv_Rt[0,8];\n\t}\n\n# F5.1.219 p7646 STLEX\n:stlex^COND Rd,Rm,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & Rd & c0411=0xe9 & Rm\n\t{\n\t\tbuild COND;\n\t\t*Rn = Rm;\n\t\tRd = 0;\n\t}\n\n# F5.1.219 p7646 STLEX\n:stlex thv_Rm,thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1110\n\t& ItCond & thv_Rm & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\t*thv_Rn = thv_Rt;\n\t\tthv_Rm = 0;\n\t}\n\n# F5.1.220 p7649 STLEXB\n:stlexb^COND Rd,Rm,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & Rd & c0411=0xe9 & Rm\n\t{\n\t\tbuild COND;\n\t\t*:1 Rn = Rm[0,8];\n\t\tRd = 0;\n\t}\n\n# F5.1.220 p7649 STLEXB\n:stlexb thv_Rm,thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1100\n\t& ItCond & thv_Rm & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\t*:1 thv_Rn = thv_Rt[0,8];\n\t\tthv_Rm = 0;\n\t}\n\n# F5.1.221 p7651 STLEXD\n:stlexd^COND Rd,Rm,Rm2,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xe9 & Rm & Rm2\n\t{\n\t\tbuild COND;\n@if ENDIAN == \"big\"\n\t\t*Rn = Rm;\n\t\t*(Rn + 4) = Rm2;\n@else\t# ENDIAN == \"little\"\n\t\t*Rn = Rm2;\n\t\t*(Rn + 4) = Rm;\n@endif\t# ENDIAN == \"little\"\n\t\tRd = 0;\n\t}\n\n# F5.1.221 p7651 STLEXD\n:stlexd thv_Rm,thv_Rt,thv_Rt2,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1111\n\t& ItCond & thv_Rm & thv_Rt & thv_Rt2 & thv_Rn\n\t{\n\t\tbuild ItCond;\n@if ENDIAN == \"big\"\n\t\t*thv_Rn = thv_Rt;\n\t\t*(thv_Rn + 4) = thv_Rt2;\n@else\t# ENDIAN == \"little\"\n\t\t*thv_Rn = thv_Rt2;\n\t\t*(thv_Rn + 4) = thv_Rt;\n@endif\t# ENDIAN == \"little\"\n\t\tthv_Rm = 0;\n\t}\n\n# F5.1.222 p7654 STLEXH\n:stlexh^COND Rd,Rm,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & Rd & c0411=0xe9 & Rm\n\t{\n\t\tbuild COND;\n\t\t*:2 Rn = Rm[0,16];\n\t\tRd = 0;\n\t}\n\n# F5.1.222 p7654 STLEXH\n:stlexh thv_Rm,thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1101\n\t& ItCond & thv_Rm & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\t*:2 thv_Rn = thv_Rt[0,16];\n\t\tthv_Rm = 0;\n\t}\n\n# F5.1.223 p7657 STLH\n:stlh^COND Rm,[Rn]\n\tis TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & c0415=0xfc9 & Rm\n\t{\n\t\tbuild COND;\n\t\t*:2 Rn = Rm[0,16];\n\t}\n\n# F5.1.223 p7657 STLH\n:stlh thv_Rt,[thv_Rn]\n\tis TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1001\n\t& ItCond & thv_Rt & thv_Rn\n\t{\n\t\tbuild ItCond;\n\t\t*:2 thv_Rn = thv_Rt[0,16];\n\t}\n\n@ifdef INCLUDE_NEON\n\n# Advanced SIMD support / NEON in ARMv8\n\n#######\n# macro declarations\n\n# The Inexact flag is bit 4 of FPEXC\n@define FPEXC_IXF \"fpexc[3,1]\"\n\n# Rounding modes, as used in pseudocode, defined as an enumeration\n# '01' N\n@define FPRounding_TIEEVEN\t\"0:1\"\n# '10' P\n@define FPRounding_POSINF\t\"1:1\"\n# '11' M\n@define FPRounding_NEGINF\t\"2:1\"\n@define FPRounding_ZERO\t\t\"3:1\"\n# '00' A\n@define FPRounding_TIEAWAY\t\"4:1\"\n@define FPRounding_ODD\t\t\"5:1\"\n\n#######\n# pcodeop declarations\n\n\n\n# FixedToFP(fp, M, N, fbits, unsigned, rounding)\n# \tConvert M-bit fixed point with fbits fractional bits to N-bit\n# \tfloating point, controlled by unsigned flag and rounding. Can\n# \talso be used with packed \"SIMD\" floats.\n\ndefine pcodeop FixedToFP;\n\n# FPConvert(fp, M, N [, rounding])\n# \tConvert floating point between from M-bit to N-bit precision.\n# \tCan also be used with packed \"SIMD\" floats. Sometimes\n# \tequivalent to float2float. M, N are the input and output sizes\n# \t(16, 32, 64), implied by pseudocode, but given explicitly\n# \there. Rounding is only required when converting to integral\n# \ttype.\n\ndefine pcodeop FPConvert;\n\n# FPConvertInexact()\n#\tAt the end of any rounding or conversion operation, the\n#\tpseudocode tests whether the converted value is identical to\n#\tthe original value. If it is not identical, and if the \"exact\"\n#\targument is true, then it sets the floating point exception\n#\tFPEXC.Inexact bit. This function is understood to return 0/1\n#\tdepending on whether converstion was exact (0) or inexact (1).\n#\n\ndefine pcodeop FPConvertInexact;\n\n# FPToFixed(fp, M, N, fbits, unsigned, rounding)\n# \tConvert M-bit floating point to N-bit fixed point with fbits\n# \tfractional bits, controlled by unsigned flag and rounding.\n# \tbetween different precisions. Can also be used with packed\n# \t\"SIMD\" floats.\n\ndefine pcodeop FPToFixed;\n\n# FPRoundInt(fp, N, rounding, exact)\n#\tRound fp to nearest integral floating point, controlled by\n#\trounding. If exact is true, set FPSR.IXC flag. Can also be\n#\tused with packed \"SIMD\" floats.\n\ndefine pcodeop FPRoundInt;\n\n# PolynomialMult(op1, op2)\n\ndefine pcodeop PolynomialMult;\n\n\n\n#######\n# The VCVT instructions are a large family for converting between\n# floating point numbers and integers, of all sizes and combinations\n\n# F6.1.58 p7998 A1 cases size = 10 (c0809)\n:vcvt^COND^\".f64.f32\"\tDd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))\n\t& COND & Dd & Sm\n\t{ build COND; Dd = float2float(Sm); }\n\n# F6.1.58 p7998 A1 cases size = 11 (c0809)\n:vcvt^COND^\".f32.f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))\n\t& COND & Sd & Dm\n\t{ build COND; Sd = float2float(Dm); }\n\n# F6.1.59 p8000 A1 op == 1 (c0808)\n:vcvt.f32.f16\tQd,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1))\n\t& Qd & Dm\n\t{ \n\t\tQd = float2float(Dm:2);\n\t}\n\n# F6.1.59 p8000 A1 op == 0 (c0808)\n:vcvt.f16.f32\tDd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0))\n\t& Dd & Qm\n\t{ Dd = float2float(Qm); }\n\nvcvt_56_64_dt: \".f32.s32\"\n\tis ((TMode=0 & c0708=0b00)\n\t| (TMode=1 & thv_c0708=0b00))\n\t& Dd & Dm\n\t{ Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_56_64_dt: \".f32.u32\"\n\tis ((TMode=0 & c0708=0b01)\n\t| (TMode=1 & thv_c0708=0b01))\n\t& Dd & Dm\n\t{ Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_56_64_dt: \".s32.f32\"\n\tis ((TMode=0 & c0708=0b10)\n\t| (TMode=1 & thv_c0708=0b10))\n\t& Dd & Dm\n\t{ Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); }\nvcvt_56_64_dt: \".u32.f32\"\n\tis ((TMode=0 & c0708=0b11)\n\t | (TMode=1 & thv_c0708=0b11))\n\t& Dd & Dm\n\t{ Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); }\n\nvcvt_56_128_dt: \".f32.s32\"\n\tis ((TMode=0 & c0708=0b00)\n\t | (TMode=1 & thv_c0708=0b00))\n\t& Qd & Qm\n\t{ Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_56_128_dt: \".f32.u32\"\n\tis ((TMode=0 & c0708=0b01)\n\t| (TMode=1 & thv_c0708=0b01))\n\t& Qd & Qm\n\t{ Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_56_128_dt: \".s32.f32\"\n\tis ((TMode=0 & c0708=0b10)\n\t| (TMode=1 & thv_c0708=0b10))\n\t& Qd & Qm\n\t{ Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); }\nvcvt_56_128_dt: \".u32.f32\"\n\tis ((TMode=0 & c0708=0b11)\n\t| (TMode=1 & thv_c0708=0b11))\n\t& Qd & Qm\n\t{ Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); }\n\n# F6.1.60 p8002 A1 Q == 0 (c0606)\n:vcvt^vcvt_56_64_dt\tDd,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0))\n\t& vcvt_56_64_dt & Dd & Dm\n { }\n\n# F6.1.60 p8002 A1 Q == 1 (c0606)\n:vcvt^vcvt_56_128_dt\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1))\n\t& vcvt_56_128_dt & Qd & Qm\n\t{ }\n\n# F6.1.61 p8005 A1 opc2==100 && size==10 (c1618, c0809)\n:vcvt^COND^\".u32.f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10))\n\t& COND & Sd & Sm\n\t{ build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); }\n\n# F6.1.61 p8005 A1 opc2==101 && size==10 (c1618, c0809)\n:vcvt^COND^\".s32.f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10))\n\t& COND & Sd & Sm\n\t{ build COND; Sd = trunc(Sm); }\n\n# F6.1.61 p8005 A1 opc2==100 && size==11 (c1618, c0809)\n:vcvt^COND^\".u32.f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11))\n\t& COND & Sd & Dm\n\t{ build COND; local tmp:8 = zext(Dm f> 0) * (trunc(Dm)); Sd = tmp:4; }\n\n# F6.1.61 p8005 A1 opc2==101 && size==11 (c1618, c0809)\n:vcvt^COND^\".s32.f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11))\n\t& COND & Sd & Dm\n\t{ build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; }\n\n# The rounding mode depends on c0707=0 => FPSCR else ZERO\n\nvcvt_58_3232_dt: \".f32.u32\"\n\tis ((TMode=0 & c0708=0b00)\n\t| (TMode=1 & thv_c0708=0b00))\n\t& Sd & Sm\n\t{ local tmp:8 = zext(Sm); Sd = int2float(tmp); }\nvcvt_58_3232_dt: \".f32.s32\"\n\tis ((TMode=0 & c0708=0b01)\n\t| (TMode=1 & thv_c0708=0b01))\n\t& Sd & Sm\n\t{ local tmp:8 = sext(Sm); Sd = int2float(tmp); }\n\nvcvt_58_6432_dt: \".f64.u32\"\n\tis ((TMode=0 & c0708=0b10)\n\t| (TMode=1 & thv_c0708=0b10))\n\t& Dd & Sm\n\t{ local tmp:8 = zext(Sm); Dd = int2float(tmp); }\nvcvt_58_6432_dt: \".f64.s32\"\n\tis ((TMode=0 & c0708=0b11)\n\t| (TMode=1 & thv_c0708=0b11))\n\t& Dd & Sm\n\t{ local tmp:8 = sext(Sm); Dd = int2float(tmp); }\n\n# F6.1.62 p8009 A1 size == 10 (c0809)\n:vcvt^COND^vcvt_58_3232_dt\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))\n\t& COND & vcvt_58_3232_dt & Sd & Sm\n\t{ build COND; build vcvt_58_3232_dt; }\n\n# F6.1.62 p8009 A1 size == 11 (c0809)\n:vcvt^COND^vcvt_58_6432_dt\tDd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))\n\t& COND & vcvt_58_6432_dt & Dd & Sm\n\t{ build COND; build vcvt_58_6432_dt; }\n\nvcvt_59_fbits_built: fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { export * [const]:1 fbits; }\nvcvt_59_fbits_built: fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { export * [const]:1 fbits; }\nvcvt_59_fbits: \"#\"^fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { }\nvcvt_59_fbits: \"#\"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { }\n\nvcvt_59_32_dt: \".f32.s32\"\n\tis ((TMode=0 & c0809=2 & c2424=0)\n\t| (TMode=1 & thv_c0809=2 & thv_c2828=0))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_32_dt: \".f32.u32\"\n\tis ((TMode=0 & c0809=2 & c2424=1)\n\t| (TMode=1 & thv_c0809=2 & thv_c2828=1))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_32_dt: \".s32.f32\"\n\tis ((TMode=0 & c0809=3 & c2424=0)\n\t| (TMode=1 & thv_c0809=3 & thv_c2828=0))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_59_32_dt: \".u32.f32\"\n\tis ((TMode=0 & c0809=3 & c2424=1)\n\t| (TMode=1 & thv_c0809=3 & thv_c2828=1))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }\nvcvt_59_32_dt: \".f16.s16\"\n\tis ((TMode=0 & c0809=0 & c2424=0)\n\t| (TMode=1 & thv_c0809=0 & thv_c2828=0))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_32_dt: \".f16.u16\"\n\tis ((TMode=0 & c0809=0 & c2424=1)\n\t| (TMode=1 & thv_c0809=0 & thv_c2828=1))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_32_dt: \".s16.f16\"\n\tis ((TMode=0 & c0809=1 & c2424=0)\n\t| (TMode=1 & thv_c0809=1 & thv_c2828=0))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_59_32_dt: \".u16.f16\"\n\tis ((TMode=0 & c0809=1 & c2424=1)\n\t| (TMode=1 & thv_c0809=1 & thv_c2828=1))\n\t& Dd & Dm & vcvt_59_fbits_built\n\t{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }\n\t\nvcvt_59_64_dt: \".f32.s32\"\n\tis ((TMode=0 & c0809=2 & c2424=0)\n\t| (TMode=1 & thv_c0809=2 & thv_c2828=0))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_64_dt: \".f32.u32\"\n\tis ((TMode=0 & c0809=2 & c2424=1)\n\t| (TMode=1 & thv_c0809=2 & thv_c2828=1))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_64_dt: \".s32.f32\"\n\tis ((TMode=0 & c0809=3 & c2424=0)\n\t| (TMode=1 & thv_c0809=3 & thv_c2828=0))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_59_64_dt: \".u32.f32\"\n\tis ((TMode=0 & c0809=3 & c2424=1)\n\t| (TMode=1 & thv_c0809=3 & thv_c2828=1))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }\nvcvt_59_64_dt: \".f16.s16\"\n\tis ((TMode=0 & c0809=0 & c2424=0)\n\t| (TMode=1 & thv_c0809=0 & thv_c2828=0))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_64_dt: \".f16.u16\"\n\tis ((TMode=0 & c0809=0 & c2424=1)\n\t| (TMode=1 & thv_c0809=0 & thv_c2828=1))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_59_64_dt: \".s16.f16\"\n\tis ((TMode=0 & c0809=1 & c2424=0)\n\t| (TMode=1 & thv_c0809=1 & thv_c2828=0))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_59_64_dt: \".u16.f16\"\n\tis ((TMode=0 & c0809=1 & c2424=1)\n\t| (TMode=1 & thv_c0809=1 & thv_c2828=1))\n\t& Qd & Qm & vcvt_59_fbits_built\n\t{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }\n\n# Should add rounding here, if dt2 is s32 or u32 then rounding is\n# FPRounding_ZERO otherwise FPROunding_TIEEVEN\n\n# F6.1.63 p8012 A1 Q = 0 (c0606)\n:vcvt^vcvt_59_32_dt\tDd,Dm,vcvt_59_fbits\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=0)\n\t| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0))\n\t& vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm\n { }\t\n\n# F6.1.63 p8012 A1 Q = 1 (c0606)\n:vcvt^vcvt_59_64_dt\tQd,Qm,vcvt_59_fbits\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=1)\n\t| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1))\n\t& vcvt_59_64_dt & vcvt_59_fbits & Qd & Qm\n\t{ }\n\nvcvt_60_fbits_built: fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; }\nvcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; }\nvcvt_60_fbits_built: fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; }\nvcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; }\nvcvt_60_fbits: \"#\"^fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { }\nvcvt_60_fbits: \"#\"^fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { }\nvcvt_60_fbits: \"#\"^fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { }\nvcvt_60_fbits: \"#\"^fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { }\n\nvcvt_60_32_dt: \".f32.s16\"\n\tis ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=0)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=0))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_32_dt: \".f32.s32\"\n\tis ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=1)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=1))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_32_dt: \".f32.u16\"\n\tis ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=0)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=0))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_32_dt: \".f32.u32\"\n\tis ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=1)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=1))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_32_dt: \".s16.f32\"\n\tis ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=0)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=0))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_60_32_dt: \".s32.f32\"\n\tis ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=1)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=1))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_60_32_dt: \".u16.f32\"\n\tis ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=0)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=0))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); }\nvcvt_60_32_dt: \".u32.f32\"\n\tis ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=1)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=1))\n\t& Sd & Sd2 & vcvt_60_fbits_built\n\t{ Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); }\n\nvcvt_60_64_dt: \".f64.s16\"\n\tis ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=0)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=0))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_64_dt: \".f64.s32\"\n\tis ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=1)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=1))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_64_dt: \".f64.u16\"\n\tis ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=0)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=0))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_64_dt: \".f64.u32\"\n\tis ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=1)\n\t| (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=1))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }\nvcvt_60_64_dt: \".s16.f64\"\n\tis ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=0)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=0))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_60_64_dt: \".s32.f64\"\n\tis ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=1)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=1))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); }\nvcvt_60_64_dt: \".u16.f64\"\n\tis ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=0)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=0))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); }\nvcvt_60_64_dt: \".u32.f64\"\n\tis ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=1)\n\t| (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=1))\n\t& Dd & Dd2 & vcvt_60_fbits_built\n\t{ Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); }\n\n# F6.1.63 p8012 A1 op=0/1 sf=10 (c1818, c0809)\n:vcvt^COND^vcvt_60_32_dt\tSd,Sd2,vcvt_60_fbits\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b10))\n\t& COND & vcvt_60_fbits & vcvt_60_32_dt & Sd & Sd2\n\t{ build COND; build vcvt_60_32_dt; }\n\n# F6.1.63 p8012 A1 op=0/1 sf=11 (c1818, c0809)\n:vcvt^COND^vcvt_60_64_dt\tDd,Dd2,vcvt_60_fbits\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b11))\n\t& COND & vcvt_60_fbits & vcvt_60_64_dt & Dd & Dd2\n\t{ build COND; build vcvt_60_64_dt; }\n\n# vcvta, vcvtm, vcvtn, and vcvtp\n\nvcvt_amnp_simd_RM: \"a\"\n\tis ((TMode=0 & c0809=0b00)\n\t| (TMode=1 & thv_c0809=0b00))\n\t{ export $(FPRounding_TIEAWAY); }\nvcvt_amnp_simd_RM: \"n\"\n\tis ((TMode=0 & c0809=0b01)\n\t| (TMode=1 & thv_c0809=0b01))\n\t{ export $(FPRounding_TIEEVEN); }\nvcvt_amnp_simd_RM: \"p\"\n\tis ((TMode=0 & c0809=0b10)\n\t| (TMode=1 & thv_c0809=0b10))\n\t{ export $(FPRounding_POSINF); }\nvcvt_amnp_simd_RM: \"m\"\n\tis ((TMode=0 & c0809=0b11)\n\t| (TMode=1 & thv_c0809=0b11))\n\t{ export $(FPRounding_NEGINF); }\n\n# These RM values need to be converted properly\nvcvt_amnp_simd_64_dt: \".s32\" is TMode=0 & c0707=0 & c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); }\nvcvt_amnp_simd_64_dt: \".s32\" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); }\nvcvt_amnp_simd_64_dt: \".u32\" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); }\nvcvt_amnp_simd_64_dt: \".u32\" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); }\n\nvcvt_amnp_simd_128_dt: \".s32\" is TMode=0 & c0707=0 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); }\nvcvt_amnp_simd_128_dt: \".s32\" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); }\nvcvt_amnp_simd_128_dt: \".u32\" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); }\nvcvt_amnp_simd_128_dt: \".u32\" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); }\n\n# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606)\n:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^\".f32\"\tDd,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0))\n\t& vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm\n { }\t\n\n# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606)\n:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^\".f32\"\tQd,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1))\n\t& vcvt_amnp_simd_RM & vcvt_amnp_simd_128_dt & Qd & Qm\n\t{ }\n\nvcvt_amnp_fp_RM: \"a\"\n\tis ((TMode=0 & c1617=0b00)\n\t| (TMode=1 & thv_c1617=0b00))\n\t{ export $(FPRounding_TIEAWAY); }\nvcvt_amnp_fp_RM: \"n\"\n\tis ((TMode=0 & c1617=0b01)\n\t| (TMode=1 & thv_c1617=0b01))\n\t{ export $(FPRounding_TIEEVEN); }\nvcvt_amnp_fp_RM: \"p\"\n\tis ((TMode=0 & c1617=0b10)\n\t| (TMode=1 & thv_c1617=0b10))\n\t{ export $(FPRounding_POSINF); }\nvcvt_amnp_fp_RM: \"m\"\n\tis ((TMode=0 & c1617=0b11)\n\t| (TMode=1 & thv_c1617=0b11))\n\t{ export $(FPRounding_NEGINF); }\n\nvcvt_amnp_fp_s_dt: \".u32\" is TMode=0 & c0707=0 & c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); }\nvcvt_amnp_fp_s_dt: \".u32\" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); }\nvcvt_amnp_fp_s_dt: \".s32\" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }\nvcvt_amnp_fp_s_dt: \".s32\" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }\n\nvcvt_amnp_fp_d_dt: \".u32\" is TMode=0 & c0707=0 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); }\nvcvt_amnp_fp_d_dt: \".u32\" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); }\nvcvt_amnp_fp_d_dt: \".s32\" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }\nvcvt_amnp_fp_d_dt: \".s32\" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }\n\n# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 01 (c0809)\n:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^\".f16\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))\n\t& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm\n\tunimpl\n\t\n# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809)\n:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^\".f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))\n\t& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm\n\t{ }\n\n# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 11 (c0809)\n:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^\".f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))\n\t& vcvt_amnp_fp_RM & vcvt_amnp_fp_d_dt & Sd & Dm\n\t{ }\n\n# vcvtb and vcvtt\n\nvcvt_bt3216_op:\t\"b\"\n\tis ((TMode=0 & c0707=0)\n\t| (TMode=1 & thv_c0707=0))\n\t& Sd & Sm\n\t{ Sd = float2float(Sm:2); }\nvcvt_bt3216_op:\t\"t\"\n\tis ((TMode=0 & c0707=1)\n\t| (TMode=1 & thv_c0707=1))\n\t& Sd & Sm\n\t{ w:2 = Sm(2); Sd = float2float(w); }\n\nvcvt_bt6416_op:\t\"b\"\n\tis ((TMode=0 & c0707=0)\n\t| (TMode=1 & thv_c0707=0))\n\t& Dd & Sm\n\t{ Dd = float2float(Sm:2); }\nvcvt_bt6416_op:\t\"t\"\n\tis ((TMode=0 & c0707=1)\n\t| (TMode=1 & thv_c0707=1))\n\t& Dd & Sm\n\t{ w:2 = Sm(2); Dd = float2float(w); }\n\nvcvt_bt1632_op:\t\"b\"\n\tis ((TMode=0 & c0707=0)\n\t| (TMode=1 & thv_c0707=0))\n\t& Sd & Sm\n\t{ Sd[0,16] = float2float(Sm); }\nvcvt_bt1632_op:\t\"t\"\n\tis ((TMode=0 & c0707=1)\n\t| (TMode=1 & thv_c0707=1))\n\t& Sd & Sm\n\t{ tmp:2 = float2float(Sm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); }\n\nvcvt_bt1664_op:\t\"b\"\n\tis ((TMode=0 & c0707=0)\n\t| (TMode=1 & thv_c0707=0))\n\t& Sd & Dm\n\t{ Sd[0,16] = float2float(Dm); }\nvcvt_bt1664_op:\t\"t\"\n\tis ((TMode=0 & c0707=1)\n\t| (TMode=1 & thv_c0707=1))\n\t& Sd & Dm\n\t{ tmp:2 = float2float(Dm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); }\n\n# F6.1.67 p8023 A1 cases op:sz = 00 (c1616, c0808)\n# F6.1.76 p8044 A1 cases op:sz = 00 (c1616, c0808)\n:vcvt^vcvt_bt3216_op^COND^\".f32.f16\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=0)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=0))\n\t& COND & vcvt_bt3216_op & Sd & Sm\n\t{ build COND; build vcvt_bt3216_op; }\n\n# F6.1.67 p8023 A1 cases op:sz = 01 (c1616, c0808)\n# F6.1.76 p8044 A1 cases op:sz = 01 (c1616, c0808)\n:vcvt^vcvt_bt6416_op^COND^\".f64.f16\"\tDd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=1)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=1))\n\t& COND & vcvt_bt6416_op & Dd & Sm\n\t{ build COND; build vcvt_bt6416_op; }\n\n# F6.1.67 p8023 A1 cases op:sz = 10 (c1616, c0808)\n# F6.1.76 p8044 A1 cases op:sz = 10 (c1616, c0808)\n:vcvt^vcvt_bt1632_op^COND^\".f16.f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=0)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=0))\n\t& COND & vcvt_bt1632_op & Sd & Sm\n\t{ build COND; build vcvt_bt1632_op; }\n\n# F6.1.67 p8023 A1 cases op:sz = 11 (c1616, c0808)\n# F6.1.76 p8044 A1 cases op:sz = 11 (c1616, c0808)\n:vcvt^vcvt_bt1664_op^COND^\".f16.f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=1)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=1))\n\t& COND & vcvt_bt1664_op & Sd & Dm\n\t{ build COND; build vcvt_bt1664_op; }\n\n# vcvtr\n\n# F6.1.75 p8040 A1 case opc2=100 size=10 (c1618, c0809)\n:vcvtr^COND^\".u32.f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10))\n\t& COND & Sd & Sm\n\t{ build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); }\n\n# F6.1.75 p8040 A1 case opc2=101 size=10\n:vcvtr^COND^\".s32.f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10))\n\t& COND & Sd & Sm\n\t{ build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); }\n\n# F6.1.75 p8040 A1 case opc2=100 size=11\n:vcvtr^COND^\".u32.f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11))\n\t& COND & Sd & Dm\n\t{ build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); }\n\n# F6.1.75 p8040 A1 case opc2=101 size=11\n:vcvtr^COND^\".s32.f64\"\tSd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11))\n\t& COND & Sd & Dm\n\t{ build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); }\n\n#######\n# VMAXNM/VMINNM\n\n\n# FPMaxNum(Vn, Vm)\n# \tReturn the maximum of two floating point numbers.\n# \tIncludes FP and SIMD variants of all lane sizes.\n\ndefine pcodeop FPMaxNum;\n\n# FPMinNum(Vn, Vm)\n# \tReturn the minimum of two floating point numbers.\n# \tIncludes FP and SIMD variants of all lane sizes.\n\ndefine pcodeop FPMinNum;\n\n# F6.1.117 p8178 A1/T1 Q = 0 (c0606)\n:vmaxnm^\".f32\"\t\tDd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))\n\t& Dd & Dn & Dm\n\t{ Dd = FPMaxNum(Dn, Dm); }\n\n# F6.1.117 p8178 A1/T1 Q = 1 (c0606)\n:vmaxnm^\".f32\"\t\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))\n\t& Qd & Qn & Qm\n\t{ Qd = FPMaxNum(Qn, Qm); }\n\n# F6.1.117 p8178 A1/T1 Q = 0 (c0606)\n:vmaxnm^\".f16\"\t\tDd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))\n\t& Dd & Dn & Dm\n\t{ Dd = FPMaxNum(Dn, Dm); }\n\n# F6.1.117 p8178 A1/T1 Q = 1 (c0606)\n:vmaxnm^\".f16\"\t\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))\n\t& Qd & Qn & Qm\n\t{ Qd = FPMaxNum(Qn, Qm); }\n\n# F6.1.117 p8178 A2/T2 size = 01 (c0809)\n:vmaxnm^\".f16\"\t\tSd,Sn,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01))\n\t& Sd & Sn & Sm\n\t{ Sd = FPMaxNum(Sn, Sm); }\n\n# F6.1.117 p8178 A2/T2 size = 10 (c0809)\n:vmaxnm^\".f32\"\t\tSd,Sn,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))\n\t& Sd & Sn & Sm\n\t{ Sd = FPMaxNum(Sn, Sm); }\n\n# F6.1.117 p8178 A2/T2 size = 11 (c0809)\n:vmaxnm^\".f64\"\t\tDd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))\n\t& Dd & Dn & Dm\n\t{ Dd = FPMaxNum(Dn, Dm); }\n\n# F6.1.120 p8178 A1/T1 Q = 0 (c0606)\n:vminnm^\".f32\"\t\tDd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))\n\t& Dd & Dn & Dm\n\t{ Dd = FPMinNum(Dn, Dm); }\n\n# F6.1.120 p8178 A1/T1 Q = 1 (c0606)\n:vminnm^\".f32\"\t\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))\n\t& Qd & Qn & Qm\n\t{ Qd = FPMinNum(Qn, Qm); }\n\n# F6.1.120 p8178 A1/T1 Q = 0 (c0606)\n:vminnm^\".f16\"\t\tDd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))\n\t& Dd & Dn & Dm\n\t{ Dd = FPMinNum(Dn, Dm); }\n\n# F6.1.120 p8178 A1/T1 Q = 1 (c0606)\n:vminnm^\".f16\"\t\tQd,Qn,Qm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))\n\t& Qd & Qn & Qm\n\t{ Qd = FPMinNum(Qn, Qm); }\n\n# F6.1.120 p8178 A2/T2 size = 01 (c0809)\n:vminnm^\".f16\"\t\tSd,Sn,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))\n\t& Sd & Sn & Sm\n\t{ Sd = FPMinNum(Sn, Sm); }\n\n# F6.1.120 p8178 A2/T2 size = 10 (c0809)\n:vminnm^\".f32\"\t\tSd,Sn,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))\n\t& Sd & Sn & Sm\n\t{ Sd = FPMinNum(Sn, Sm); }\n\n# F6.1.120 p8178 A2/T2 size = 11 (c0809)\n:vminnm^\".f64\"\t\tDd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))\n\t& Dd & Dn & Dm\n\t{ Dd = FPMinNum(Dn, Dm); }\n\n#######\n# VMULL instructions vector/polynomial multiplication\n\nvmull_dt: \".s8\"\n\tis ((TMode=0 & c0909=0 & c2424=0 & c2021=0b00)\n\t| (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b00))\n\t{ }\n\nvmull_dt: \".s16\"\n\tis ((TMode=0 & c0909=0 & c2424=0 & c2021=0b01)\n\t| (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b01))\n\t{ }\n\nvmull_dt: \".s32\"\n\tis ((TMode=0 & c0909=0 & c2424=0 & c2021=0b10)\n\t| (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b10))\n\t{ }\n\nvmull_dt: \".u8\"\n\tis ((TMode=0 & c0909=0 & c2424=1 & c2021=0b00)\n\t| (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b00))\n\t{ }\n\nvmull_dt: \".u16\"\n\tis ((TMode=0 & c0909=0 & c2424=1 & c2021=0b01)\n\t| (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b01))\n\t{ }\n\nvmull_dt: \".u32\"\n\tis ((TMode=0 & c0909=0 & c2424=1 & c2021=0b10)\n\t| (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b10))\n\t{ }\n\nvmull_dt: \".p8\"\n\tis ((TMode=0 & c0909=1 & c2424=0 & c2021=0b00)\n\t| (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b00))\n\t{ }\n\nvmull_dt: \".p64\"\n\tis ((TMode=0 & c0909=1 & c2424=0 & c2021=0b10)\n\t| (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b10))\n\t{ }\n\n# F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01)\n:vmull^vmull_dt\t\tQd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1)\n\t| (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1))\n\t& vmull_dt & Qd & Dn & Dm\n\t{ Qd = PolynomialMult(Dn, Dm); }\n\n# F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11)\n:vmull^vmull_dt\t\tQd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0)\n\t| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0))\n\t& vmull_dt & Qd & Dn & Dm\n\t{ Qd = VectorMultiply(Dn, Dm); }\n\n#######\n# The VRINT instructions round a \"floating-point to an integral\n# floating point value of the same size\", i.e. trunc.\n# The arguments are\n# 1: floating point value (can be 2 packed in a Q register)\n# 2: rounding mode\n# 3: boolean exact, if true then raise the Inexact exception if the\n# result differs from the original\n\nvrint_simd_RM: \"a\"\n\tis ((TMode=0 & c0709=0b010)\n\t| (TMode=1 & thv_c0709=0b010))\n\t{ export $(FPRounding_TIEAWAY); }\n\nvrint_simd_RM: \"m\"\n\tis ((TMode=0 & c0709=0b101)\n\t| (TMode=1 & thv_c0709=0b101))\n\t{ export $(FPRounding_NEGINF); }\n\nvrint_simd_RM: \"n\"\n\tis ((TMode=0 & c0709=0b000)\n\t| (TMode=1 & thv_c0709=0b000))\n\t{ export $(FPRounding_TIEEVEN); }\n\nvrint_simd_RM: \"p\"\n\tis ((TMode=0 & c0709=0b111)\n\t| (TMode=1 & thv_c0709=0b111))\n\t{ export $(FPRounding_POSINF); }\n\nvrint_simd_RM: \"x\"\n\tis ((TMode=0 & c0709=0b001)\n\t| (TMode=1 & thv_c0709=0b001))\n\t{ export $(FPRounding_TIEEVEN); }\n\nvrint_simd_RM: \"z\"\n\tis ((TMode=0 & c0709=0b011)\n\t| (TMode=1 & thv_c0709=0b011))\n\t{ export $(FPRounding_ZERO); }\n\n# For vrintx, the exact flag is 1, and the IXF flag is set (inexact)\n\nvrint_simd_exact: \"x\"\n\tis ((TMode=0 & c0709=0b001)\n\t| (TMode=1 & thv_c0709=0b001))\n\t{ export 1:1; }\n\nvrint_simd_exact:\n\tis ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0))\n\t| (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0)))\n\t{ export 0:1; }\n\nvrint_simd_ixf:\n\tis ((TMode=0 & c0709=0b001)\n\t| (TMode=1 & thv_c0709=0b001))\n\t{ $(FPEXC_IXF) = FPConvertInexact(); }\n\nvrint_simd_ixf:\n\tis ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0))\n\t| (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0)))\n\t{ }\n\n\n# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 0 (c0606)\n:vrint^vrint_simd_RM^\".f32\"\tDd,Dm\n\tis ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & (( c0707=0 & c0909=0) | ( c0707=1 & c0909=1) | ( c0707=1 & c0909=0)) & c0404=0 & c0606=0)\n\t| (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & ((thv_c0707=0 & thv_c0909=0) | (thv_c0707=1 & thv_c0909=1) | (thv_c0707=1 & thv_c0909=0)) & thv_c0404=0 & thv_c0606=0))\n\t& vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Dd & Dm\n\t{ Dd = FPRoundInt(Dm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; }\n\n# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 1 (c0606)\n:vrint^vrint_simd_RM^\".f32\"\tQd,Qm\n\tis ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & c0404=0 & c0606=1)\n\t| (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & thv_c0404=0 & thv_c0606=1))\n\t& vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Qd & Qm\n\t{ Qd = FPRoundInt(Qm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; }\n\nvrint_fp_RM: \"a\"\n\tis ((TMode=0 & c1617=0b00)\n\t| (TMode=1 & thv_c1617=0b00))\n\t{ export $(FPRounding_TIEAWAY); }\n\nvrint_fp_RM: \"m\"\n\tis ((TMode=0 & c1617=0b11)\n\t| (TMode=1 & thv_c1617=0b11))\n\t{ export $(FPRounding_NEGINF); }\n\nvrint_fp_RM: \"n\"\n\tis ((TMode=0 & c1617=0b01)\n\t| (TMode=1 & thv_c1617=0b01))\n\t{ export $(FPRounding_TIEEVEN); }\n\nvrint_fp_RM: \"p\"\n\tis ((TMode=0 & c1617=0b10)\n\t| (TMode=1 & thv_c1617=0b10))\n\t{ export $(FPRounding_POSINF); }\n\n# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809)\n:vrint^vrint_fp_RM^\".f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10))\n\t& vrint_fp_RM & Sd & Sm\n\t{ Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); }\n\n# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809)\n:vrint^vrint_fp_RM^\".f64\"\tDd,Dm\n\tis ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11))\n\t& vrint_fp_RM & Dd & Dm\n\t{ Dd = FPRoundInt(Dm, 32:1, vrint_fp_RM, 0:1); }\n\nvrint_rxz_RM: \"r\"\n\tis ((TMode=0 & c1616=0 & c0707=0)\n\t| (TMode=1 & thv_c1616=0 & thv_c0707=0))\n\t{ tmp:1 = $(FPSCR_RMODE); export tmp; }\n\nvrint_rxz_RM: \"x\"\n\tis ((TMode=0 & c1616=1 & c0707=0)\n\t| (TMode=1 & thv_c1616=1 & thv_c0707=0))\n\t{ tmp:1 = $(FPSCR_RMODE); export tmp; }\n\nvrint_rxz_RM: \"z\"\n\tis ((TMode=0 & c1616=0 & c0707=1)\n\t| (TMode=1 & thv_c1616=0 & thv_c0707=1))\n\t{ export $(FPRounding_ZERO); }\n\n# For vrintx, the exact flag is 1, and the IXF flag is set (inexact)\n\nvrint_rxz_exact: \"x\"\n\tis ((TMode=0 & c1616=1 & c0707=0)\n\t| (TMode=1 & thv_c1616=1 & thv_c0707=0))\n\t{ export 1:1; }\n\nvrint_rxz_exact:\n\tis ((TMode=0 & ( c1616=0 | c0707=1))\n\t| (TMode=1 & (thv_c1616=0 | thv_c0707=1)))\n\t{ export 0:1; }\n\nvrint_rxz_ixf:\n\tis ((TMode=0 & c1616=1 & c0707=0)\n\t| (TMode=1 & thv_c1616=1 & thv_c0707=0))\n\t{ $(FPEXC_IXF) = FPConvertInexact(); }\n\nvrint_rxz_ixf:\n\tis ((TMode=0 & ( c1616=0 | c0707=1))\n\t| (TMode=1 & (thv_c1616=0 | thv_c0707=1)))\n\t{ }\n\n# F6.1.207,209,211 p8412,8416,8420 A1 size = 10 (c0809)\n:vrint^vrint_rxz_RM^COND^\".f32\"\tSd,Sm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b10))\n\t& vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Sd & Sm\n\t{ build COND; Sd = FPRoundInt(Sm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; }\n\n# F6.1.207,209,211 p8412,8416,8420 A1 size = 11 (c0809)\n:vrint^vrint_rxz_RM^COND^\".f64\"\tDd,Dm\n\tis ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b11))\n\t& vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Dd & Dm\n\t{ build COND; Dd = FPRoundInt(Dm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; }\n\n#######\n# VSEL\n\nvselcond: \"eq\"\n\tis ((TMode=0 & c2021=0b00)\n\t| (TMode=1 & thv_c2021=0b00))\n\t{ tmp:1 = ZR; export tmp; }\nvselcond: \"ge\"\n\tis ((TMode=0 & c2021=0b10)\n\t| (TMode=1 & thv_c2021=0b10))\n\t{ tmp:1 = (NG==OV); export tmp; }\nvselcond: \"gt\"\n\tis ((TMode=0 & c2021=0b11)\n\t| (TMode=1 & thv_c2021=0b11))\n\t{ tmp:1 = (!ZR && NG==OV); export tmp; }\nvselcond: \"vs\"\n\tis ((TMode=0 & c2021=0b01)\n\t| (TMode=1 & thv_c2021=0b01))\n\t{ tmp:1 = OV; export tmp; }\n\n# F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809)\n:vsel^vselcond^\".f64\" Dd,Dn,Dm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))\n\t& vselcond & Dn & Dd & Dm\n\t{ Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; }\n\n# F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809)\n:vsel^vselcond\".f32\" Sd,Sn,Sm\n\tis ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)\n\t| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))\n\t& vselcond & Sn & Sd & Sm\n\t{ Sd = zext(vselcond != 0) * Sn + zext(vselcond == 0) * Sm; }\n\n@endif # INCLUDE_NEON\n" }, { "path": "pypcode/processors/ARM/data/languages/old/ARMv5.lang", "content": "\n\n \n ARM:LE:32:DEPRECATED ARM V5\n ARM\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/ARM/data/languages/old/ARMv5.trans", "content": "\n\n Sleigh-ARMv5\n ARM:LE:32:v5\n\n\n" }, { "path": "pypcode/processors/ARM/data/languages/old/THUMBv2.lang", "content": "\n\n \n ARM:LE:32:DEPRECATED THUMB V2\n ARM\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/ARM/data/languages/old/THUMBv2.trans", "content": "\n\n Sleigh-THUMBv2\n ARM:LE:32:v5t\n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/manuals/ARM.idx", "content": "@DDI0487H_a_a-profile_architecture_reference_manual.pdf[ARM Architecture Reference Manual - ARM A-profile architecture, December 2021 (ARM DDI 0487H.a)]\n\nadc,\t7136\nadd,\t7155\nadr,\t7157\naesd,\t7853\naese,\t7855\naesimc,\t7857\naesmc,\t7859\nand,\t7167\nasr,\t7171\nasrs,\t7175\nb,\t7177\nbfc,\t7180\nbfi,\t7182\nbic,\t7191\nbkpt,\t7193\nbl,\t7195\nblx,\t7198\nbx,\t7200\nbxj,\t7202\ncbnz,\t7203\ncbz,\t7203\nclrex,\t7204\nclz,\t7205\ncmn,\t7212\ncmp,\t7219\ncps,\t7221\ncrc32,\t7226\ncrc32c,\t7229\ncsdb,\t7232\ndbg,\t7234\ndcps1,\t7235\ndcps2,\t7237\ndcps3,\t7239\ndmb,\t7241\ndsb,\t7244\neor,\t7254\neret,\t7256\nesb,\t7258\nfldm,\t7861\nfstmdbx,\t7864\nhlt,\t7260\nhvc,\t7262\nisb,\t7264\nit,\t7266\nlda,\t7268\nldab,\t7270\nldaex,\t7272\nldaexb,\t7274\nldaexd,\t7276\nldaexh,\t7278\nldah,\t7280\nldc,\t7284\nldm,\t7292\nldmda,\t7294\nldmdb,\t7296\nldmib,\t7299\nldr,\t7308\nldrb,\t7317\nldrbt,\t7320\nldrd,\t7329\nldrex,\t7332\nldrexb,\t7334\nldrexd,\t7336\nldrexh,\t7338\nldrh,\t7346\nldrht,\t7349\nldrsb,\t7357\nldrsbt,\t7360\nldrsh,\t7368\nldrsht,\t7371\nldrt,\t7374\nlsl,\t7379\nlsls,\t7383\nlsr,\t7387\nlsrs,\t7391\nmcr,\t7393\nmcrr,\t7395\nmla,\t7397\nmls,\t7399\nmov,\t7411\nmovt,\t7415\nmrc,\t7417\nmrrc,\t7419\nmrs,\t7423\nmsr,\t7433\nmul,\t7436\nmvn,\t7443\nnop,\t7445\norn,\t7449\norr,\t7458\npkhbt,\t7460\npld,\t7468\npli,\t7474\npop,\t7480\npssbb,\t7482\npush,\t7488\nqadd,\t7489\nqadd16,\t7491\nqadd8,\t7493\nqasx,\t7495\nqdadd,\t7497\nqdsub,\t7499\nqsax,\t7501\nqsub,\t7503\nqsub16,\t7505\nqsub8,\t7507\nrbit,\t7509\nrev,\t7511\nrev16,\t7513\nrevsh,\t7515\nrfe,\t7517\nror,\t7522\nrors,\t7526\nrrx,\t7528\nrrxs,\t7530\nrsb,\t7538\nrsc,\t7544\nsadd16,\t7546\nsadd8,\t7548\nsasx,\t7550\nsb,\t7552\nsbc,\t7561\nsbfx,\t7563\nsdiv,\t7565\nsel,\t7567\nsetend,\t7569\nsetpan,\t7570\nsev,\t7571\nsevl,\t7573\nsha1c,\t7867\nsha1h,\t7869\nsha1m,\t7871\nsha1p,\t7873\nsha1su0,\t7875\nsha1su1,\t7877\nsha256h,\t7879\nsha256h2,\t7881\nsha256su0,\t7883\nsha256su1,\t7885\nshadd16,\t7575\nshadd8,\t7577\nshasx,\t7579\nshsax,\t7581\nshsub16,\t7583\nshsub8,\t7585\nsmc,\t7587\nsmlabb,\t7589\nsmlad,\t7591\nsmlal,\t7593\nsmlalbb,\t7595\nsmlald,\t7598\nsmlawb,\t7601\nsmlsd,\t7603\nsmlsld,\t7605\nsmmla,\t7607\nsmmls,\t7609\nsmmul,\t7611\nsmuad,\t7613\nsmulbb,\t7615\nsmull,\t7617\nsmulwb,\t7619\nsmusd,\t7621\nsrs,\t7623\nssat,\t7627\nssat16,\t7629\nssax,\t7631\nssbb,\t7633\nssub16,\t7635\nssub8,\t7637\nstc,\t7639\nstl,\t7642\nstlb,\t7644\nstlex,\t7646\nstlexb,\t7649\nstlexd,\t7651\nstlexh,\t7654\nstlh,\t7657\nstm,\t7663\nstmda,\t7665\nstmdb,\t7667\nstmib,\t7670\nstr,\t7677\nstrb,\t7684\nstrbt,\t7687\nstrd,\t7695\nstrex,\t7698\nstrexb,\t7701\nstrexd,\t7703\nstrexh,\t7706\nstrh,\t7713\nstrht,\t7716\nstrt,\t7720\nsub,\t7739\nsvc,\t7742\nsxtab,\t7744\nsxtab16,\t7746\nsxtah,\t7748\nsxtb,\t7750\nsxtb16,\t7752\nsxth,\t7754\ntbb,\t7756\nteq,\t7762\ntsb,\t7764\ntst,\t7771\nuadd16,\t7773\nuadd8,\t7775\nuasx,\t7777\nubfx,\t7779\nudf,\t7781\nudiv,\t7783\nuhadd16,\t7785\nuhadd8,\t7787\nuhasx,\t7789\nuhsax,\t7791\nuhsub16,\t7793\nuhsub8,\t7795\numaal,\t7797\numlal,\t7799\numull,\t7801\nuqadd16,\t7803\nuqadd8,\t7805\nuqasx,\t7807\nuqsax,\t7809\nuqsub16,\t7811\nuqsub8,\t7813\nusad8,\t7815\nusada8,\t7817\nusat,\t7819\nusat16,\t7821\nusax,\t7823\nusub16,\t7825\nusub8,\t7827\nuxtab,\t7829\nuxtab16,\t7831\nuxtah,\t7833\nuxtb,\t7835\nuxtb16,\t7837\nuxth,\t7839\nvaba,\t7887\nvabal,\t7890\nvabd,\t7894\nvabdl,\t7897\nvabs,\t7899\nvacge,\t7903\nvacgt,\t7908\nvacle,\t7906\nvaclt,\t7911\nvadd,\t7917\nvaddhn,\t7919\nvaddl,\t7921\nvaddw,\t7923\nvand,\t7928\nvbic,\t7933\nvbif,\t7935\nvbit,\t7937\nvbsl,\t7939\nvcadd,\t7941\nvceq,\t7946\nvcge,\t7953\nvcgt,\t7960\nvcle,\t7967\nvcls,\t7970\nvclt,\t7975\nvclz,\t7978\nvcmla,\t7983\nvcmp,\t7986\nvcmpe,\t7990\nvcnt,\t7994\nvcvt,\t8015\nvcvta,\t8021\nvcvtb,\t8026\nvcvtm,\t8030\nvcvtn,\t8034\nvcvtp,\t8038\nvcvtr,\t8040\nvcvtt,\t8047\nvdiv,\t8049\nvdot,\t8054\nvdup,\t8058\nveor,\t8060\nvext,\t8065\nvfma,\t8067\nvfmab,\t8073\nvfmal,\t8078\nvfms,\t8081\nvfmsl,\t8088\nvfnma,\t8091\nvfnms,\t8094\nvhadd,\t8097\nvhsub,\t8100\nvins,\t8103\nvjcvt,\t8105\nvld1,\t8115\nvld2,\t8131\nvld3,\t8145\nvld4,\t8157\nvldm,\t8161\nvldr,\t8169\nvmax,\t8175\nvmaxnm,\t8178\nvmin,\t8185\nvminnm,\t8188\nvmla,\t8198\nvmlal,\t8203\nvmls,\t8211\nvmlsl,\t8216\nvmmla,\t8218\nvmov,\t8241\nvmovl,\t8244\nvmovn,\t8246\nvmovx,\t8248\nvmrs,\t8250\nvmsr,\t8253\nvmul,\t8263\nvmull,\t8269\nvmvn,\t8275\nvneg,\t8277\nvnmla,\t8281\nvnmls,\t8284\nvnmul,\t8287\nvorn,\t8293\nvorr,\t8298\nvpadal,\t8300\nvpadd,\t8305\nvpaddl,\t8307\nvpmax,\t8312\nvpmin,\t8316\nvpop,\t8318\nvpush,\t8320\nvqabs,\t8322\nvqadd,\t8324\nvqdmlal,\t8326\nvqdmlsl,\t8329\nvqdmulh,\t8332\nvqdmull,\t8336\nvqmovn,\t8339\nvqneg,\t8341\nvqrdmlah,\t8343\nvqrdmlsh,\t8347\nvqrdmulh,\t8351\nvqrshl,\t8355\nvqrshrn,\t8359\nvqrshrun,\t8362\nvqshl,\t8367\nvqshrn,\t8371\nvqshrun,\t8374\nvqsub,\t8376\nvraddhn,\t8378\nvrecpe,\t8380\nvrecps,\t8382\nvrev16,\t8384\nvrev32,\t8387\nvrev64,\t8390\nvrhadd,\t8393\nvrinta,\t8398\nvrintm,\t8402\nvrintn,\t8406\nvrintp,\t8410\nvrintr,\t8412\nvrintx,\t8416\nvrintz,\t8420\nvrshl,\t8422\nvrshr,\t8428\nvrshrn,\t8432\nvrsqrte,\t8434\nvrsqrts,\t8436\nvrsra,\t8438\nvrsubhn,\t8441\nvsdot,\t8445\nvseleq,\t8447\nvshl,\t8454\nvshll,\t8457\nvshr,\t8463\nvshrn,\t8467\nvsli,\t8469\nvsmmla,\t8472\nvsqrt,\t8474\nvsra,\t8476\nvsri,\t8479\nvst1,\t8487\nvst2,\t8501\nvst3,\t8512\nvst4,\t8522\nvstm,\t8526\nvstr,\t8531\nvsub,\t8538\nvsubhn,\t8540\nvsubl,\t8542\nvsubw,\t8544\nvsudot,\t8546\nvswp,\t8548\nvtbl,\t8550\nvtrn,\t8553\nvtst,\t8556\nvudot,\t8560\nvummla,\t8562\nvusdot,\t8566\nvusmmla,\t8568\nvuzp,\t8573\nvzip,\t8577\nwfe,\t7841\nwfi,\t7843\nyield,\t7845" }, { "path": "pypcode/processors/ARM/data/patterns/ARM_BE_patterns.xml", "content": "\n \n \n 0xbd .......0 \n 0xbd .......0 0x0000 \n 0xbd .......0 0xbf00 \n 0xbd .......0 0x46c0 \n 0xffff \n 0x46c0 \n 0x4770 \n 0x4770 0x0000 \n 0x4770 0x46c0 \n 0xb0 000..... 0xbd ....0000 \n 0x00bf \n 0x8000f3af \n 0xe8bd 101..... ........ \n 0xf746 \n 0xf8 0x5d 0xfb 0....... \n 0xf8 0x5d 0xfb 0x04 \n 0xe8 0xbd 100..... ........ \n \n \n \n 0xb5 ........ 0xb0 100..... \n 0xb5 ........ 0x1c 00...... \n 0xb5 ........ 0x46 0x.. \n 0xb5 ........ 01.01... 0x.. \n 0xb5 ........ 0x68 0x.. \n 0xb5 ........ 01.01... 0x.. 0xb0 10...... \n 0xb5 1....... 0xaf.. \n 0xb0 100..... 0xb5 ....0000 \n 0x1c 00...... 0xb5 ....0000 \n 0x46 0x.. 0xb5 ....0000 \n 01.01...0x.. 0xb5 ....0000 \n 0x68 0x.. 0xb5 ....0000 \n 0xe92d 0100.... ........ \n 0xf8 0x4d 11101101 0x04 \n \n \n \n \n \n \n \n \n 0xe12fff1. \n 0xe12fff1e 0xe1a00000 \n 0xe12fff1e 0x00000000 \n 0xea...... \n 0xe8 10.11101 10.0.... 0x.. \n 0xe8 10.11101 10.0.... 0x.. 0xe1a00000 \n 0xe8 10.11101 10.0.... 0x.. 0x00000000 \n 0xe4 0x9d 0xf0 0x08 \n 0xe1 0xa0 0xf0 0x0e \n 0xe320f000 0xe1a00000 \n 0xe1a00000 \n \n \n \n 0xe24dd... 11101001 00101101 0100.... ........ \n 11101001 00101101 0100.... ........ 0xe24dd... \n 11101001 00101101 0100.... ........ 0x........ 0xe24dd... \n 11101001 00101101 0100.... ........ 0xe1a0 010.0000 0000000. \n 11101001 00101101 0100.... ........ \n 0xe24dd... 11100101 00101101 1110.... ........ \n 11101001 00101101 0000.... ........ 11100101 00101101 11100000 ......00 \n 11100101 00101101 1110.... ........ 0xe24dd... \n 11100101 00101101 1110.... ........ 0x........ 0xe24dd... \n 0xe5 0x2d 0xe0 0x08 \n 0xe1a0c00d 0xe9 0x2. 11...... 0x.0 \n \n \n \n \n \n \n \n 0xe24dd... 11101001 00101101 0100.... ........ \n \n \n \n \n \n \n \n 0xe5 1001.... 0....... ........ 11101001 00101101 0100.... ....0000 \n \n \n \n \n \n \n \n 0xe....... 11101001 00101101 0100.... ....0000 \n \n \n \n \n \n \n 0xe....... 0xe....... 11101001 00101101 0100.... ....0000 \n \n \n \n \n \n \n 11101001 00101101 0100.... ........ \n \n \n \n \n \n \n 0xe24dd... 11100101 00101101 1110.... ........ \n \n \n \n \n \n \n 11100101 00101101 1110.... ........ 0xe24dd... \n \n \n \n \n\n \n 11101001 00101101 .1...... ....0000 0x........ 0xe24dd... \n \n \n \n \n \n \n 11100101 00101101 1110.... ........ 0x........ 0xe24dd... \n \n \n \n \n \n \n 0xe1a0c00d 0xe9 0x2. 11...... 0x.0 \n \n \n \n \n\n \n 0xb5 ....0000 0xb0 100..... \n \n \n \n \n \n \n 0xe92d 0100.... ........ \n \n \n \n \n \n \n 0xb5 ....0000 0x1c 00...... \n \n \n \n \n \n \n 0xb5 ....0000 0x46 0x.. \n \n \n \n \n \n \n 0xb5 ....0000 01.01... 0x.. \n \n \n \n \n \n \n 0xb5 ....0000 0x68 0x.. \n \n \n \n \n \n \n 0xb5 ....0000 01.01... 0x.. 0xb0 10...... \n \n \n \n \n \n \n 0xb5 1...0000 0xaf.. \n \n \n \n \n \n \n \n \n 0xbd .......0 \n 0xbd .......0 0xbf00 \n 0xe8 0xbd 100..... ........ \n 0x4770 \n 0x4770 0xbf00 \n 11110... ........ 10.1.... ........ \n 111001.. ........ \n \n \n \n 0xb5 ........ 0xb0 100..... \n 0xb5 ........ 0x1c 00...... \n 0xb5 ........ 0x46 0x.. \n 0xb5 ........ 01.01... 0x.. \n 0xb5 ........ 0x68 0x.. \n 0xb5 ........ 01.01... 0x.. 0xb0 10...... \n 0xb5 1....... 0xaf.. \n 0xb0 100..... 0xb5 ....0000 \n 0x1c 00...... 0xb5 ....0000 \n 0x46 0x.. 0xb5 ....0000 \n 01.01...0x.. 0xb5 ....0000 \n 0x68 0x.. 0xb5 ....0000 \n 0xe92d 0100.... ........ \n 0xf8 0x4d 11101101 0x04 \n 0xb5 ...1.... \n 0xb4 ...1.... \n 0xb5 .......0 \n \n \n \n \n \n \n \n 0xe2 0x8f 1100.... ........\n 0xe2 0x8c 1100.... ........ \n 0xe5 0xbc 0xf. 0x.. \n \n \n \n \n\n \n 0xb4 0x03 \n 0x48 0x01\n 0x90 0x01 \n 0xbd 0x01 \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/patterns/ARM_LE_patterns.xml", "content": "\n \n \n .......0 0xbd \n .......0 0xbd 0x0000 \n .......0 0xbd 0x00bf \n .......0 0xbd 0xc0 0x46 \n 0xffff \n 0xc046 \n 0x7047 \n 0x7047 0x0000 \n 0x7047 0xc046 \n 0x7047 0x00bf \n 000..... 0xb0 ....0000 0xbd \n 0x00bf \n 0xaff30080 \n 0xbde8 ........ 1000.... \n 0x46f7 \n 0x5d 0xf8 0....... 0xfb \n 0x5d 0xf8 0x04 0xfb \n 0xbd 0xe8 ........ 100..... \n \n \n \n ........ 0xb5 1....... 0xb0 \n ........ 0xb5 00...... 0x1c \n ........ 0xb5 0x.. 0x46 \n ........ 0xb5 0x.. 01.01... \n ........ 0xb5 0x.. 0x68 \n ........ 0xb5 0x.. 01.01... 10...... 0xb0 \n 1....... 0xb5 0x..af \n 100..... 0xb0 ....0000 0xb5 \n 00...... 0x1c ....0000 0xb5 \n \n 0x.. 01.01... ....0000 0xb5 \n 0x.. 0x68 ....0000 0xb5 \n 0x2de9 ........ 0100.... \n 0x4d 0xf8 0x04 11101101 \n \n \n \n \n \n \n \n \n 0x1.ff2fe1 \n 0x1eff2fe1 0x00000000 \n 0x1eff2fe1 0x0000a0e1 \n 0x......ea \n 0x.. 10.0.... 10.11101 0xe8 \n 0x.. 10.0.... 10.11101 0xe8 0x00000000 \n 0x.. 10.0.... 10.11101 0xe8 0x0000a0e1 \n 0x08 0xf0 0x9d 0xe4 \n 0x0e 0xf0 0xa0 0xe1 \n 0x00f020e3 0x0000a0e1 \n 0x0000a0e1 \n \n \n \n 0x..d.4de2 ........ .10..... 00101101 11101001 \n ........ 0100.... 00101101 11101001 0x..d.4de2 \n ........ 0100.... 00101101 11101001 0x........ 0x..d.4de2 \n ........ 0100.... 00101101 11101001 0000000. 010.0000 0xa0e1 \n ........ 0100.... 00101101 11101001 \n 0x..d.4de2 ........ 1110.... 00101101 11100101 \n ........ 0000.... 00101101 11101001 ......00 11100000 00101101 11100101 \n ........ 1110.... 00101101 11100101 0x..d.4de2 \n ........ 1110.... 00101101 11100101 0x........ 0x..d.4de2 \n 0x08 0xe0 0x2d 0xe5 \n 0x0dc0a0e1 0x.0 11...... 0x2. 0xe9 \n ........ 0100.... 00101101 11101001 \n \n \n \n \n \n \n \n 0x..d.4de2 ........ 0100.... 00101101 11101001 \n \n \n \n \n \n \n\n \n ........ 0....... 1001.... 0xe5 0000.... 0100.... 00101101 11101001 \n \n \n \n \n \n \n\n \n 0x......e. 0000.... 0100.... 00101101 11101001 \n \n \n \n \n \n \n 0x......e. 0x......e. 0000.... 0100.... 00101101 11101001 \n \n \n \n \n \n \n \t \n ........ 0100.... 00101101 11101001 \n \n \n \n \n \n \n ........ 0100.... 00101101 11101001 \n \n \n \n \n \n \n \n 0x..d.4de2 ........ 1110.... 00101101 11100101 \n \n \n \n \n \n \n \n ........ 1110.... 00101101 11100101 0x..d.4de2 \n \n \n \n \n \n\n \n ....0000 .1...... 00101101 11101001 0x........ 0x..d.4de2 \n \n \n \n \n \n \n \n ........ 1110.... 00101101 11100101 0x........ 0x..d.4de2 \n \n \n \n \n \n \n 0x0dc0a0e1 0x.0 11...... 0x2. 0xe9 \n \n \n \n \n\n \n ....0000 0xb5 1....... 0xb0 \n \n \n \n \n \n \n 0x2de9 ........ 010..... \n \n \n \n \n \n \n ....0000 0xb5 00...... 0x1c \n \n \n \n \n \n \n ....0000 0xb5 0x.. 0x46 \n \n \n \n \n \n \n ....0000 0xb5 0x.. 01.01... \n \n \n \n \n \n \n ....0000 0xb5 0x.. 0x68 \n \n \n \n \n \n \n ....0000 0xb5 0x.. 01.01... 10...... 0xb0 \n \n \n \n \n \n \n 1...0000 0xb5 0x..af \n \n \n \n \n \n \n \n \n .......0 0xbd \n .......0 0xbd 0x00bf \n 0xbd 0xe8 ........ 100..... \n 0x7047 \n 0x7047 0x00bf \n ........ 11110... ........ 10.1.... \n ........ 111001.. \n \n \n \n ........ 0xb5 1....... 0xb0 \n ........ 0xb5 00...... 0x1c \n ........ 0xb5 0x.. 0x46 \n ........ 0xb5 0x.. 01.01... \n ........ 0xb5 0x.. 0x68 \n ........ 0xb5 0x.. 01.01... 10...... 0xb0 \n 1....... 0xb5 0x..af \n 100..... 0xb0 ....0000 0xb5 \n 00...... 0x1c ....0000 0xb5 \n \n 0x.. 01.01... ....0000 0xb5 \n 0x.. 0x68 ....0000 0xb5 \n 0x2de9 ........ 0100.... \n 0x4d 0xf8 0x04 11101101 \n ...1.... 0xb5 \n ...1.... 0xb4 \n .......0 0xb5 \n \n \n \n \n \n \n \n ........ 1100.... 0x8f 0xe2 \n ........ 1100.... 0x8c 0xe2 \n 0x.. 0xf. 0xbc 0xe5 \n \n \n \n \n \n \n 0x03 0xb4 \n 0x01 0x48\n 0x01 0x90\n 0x01 0xbd \n \n \n \n \n\n \n 0x10 0xb5 \n 0x02 0x4c \n 0x24 0x68 \n 0x01 0x94 \n 0x10 0xbd \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/ARM/data/patterns/ARM_switch_patterns.xml", "content": "\n \n \n \n \n \n 0x03b4 0x7146 0x0231 0x8908 0x8000 0x8900 0x0858 0x4018 0x8646 0x03bc 0xf746 \n \n \n \n \n \n \n 0x02b4 0x7146 0x4908 0x4900 0x095c 0x4900 0x8e44 0x02bc 0x7047 \n \n \n \n \n \n \n 0x02b4 0x7146 0x4908 0x4900 0x0956 0x4900 0x8e44 0x02bc 0x7047 \n \n \n \n \n \n \n 0x03b4 0x7146 0x4908 0x4000 0x4900 0x095e 0x4900 0x8e44 0x03bc 0x7047 \n \n \n \n \n \n \n 0x03b4 0x7146 0x4908 0x4000 0x4900 0x095a 0x4900 0x8e44 0x03bc 0x7047 \n \n \n \n \n \n \n 0x01c05ee5 0x0c0053e1 0x0330de37 0x0c30de27 0x83 11.00000 0x8ee0 000111.0 0xff2fe1 \n \n \n \n \n \n \n \n 0x01c05ee5 0x0c0053e1 0x0c30de27 0x0330de37 0x83 11.00000 0x8ee0 000111.0 0xff2fe1 \n \n \n \n \n \n\n \n 0x30b4 0x7446 0x641e 0x2578 0x641c 0xab42 0x00d2 0x1d46 0x635d 0x5b00 0xe318 0x30bc 0x1847 \n \n \n \n \n \n" }, { "path": "pypcode/processors/ARM/data/patterns/patternconstraints.xml", "content": "\n \n ARM_LE_patterns.xml\n \n \n \n ARM_BE_patterns.xml\n \n \n \n ARM_LE_patterns.xml\n \n \n\n" }, { "path": "pypcode/processors/ARM/data/patterns/prepatternconstraints.xml", "content": "\n \n ARM_switch_patterns.xml\n \n" }, { "path": "pypcode/processors/Atmel/data/languages/atmega256.pspec", "content": "\n\n\n\n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n\n \n \n \n\n \n\n\t\n \n \n \n\n \n \n\n\t\n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n\t\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\t\n \n \n \n \n \n \n\t\n\t\n \n \n \n\t\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32.opinion", "content": "\n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a.ldefs", "content": "\n\n\n \n Generic AVR32-A big-endian\n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a.pspec", "content": "\n\n\n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a.slaspec", "content": "define endian=big;\ndefine alignment=2;\n\ndefine space RAM type=ram_space size=4 default;\n\ndefine space register type=register_space size=2; \n\n# for the AVR32A\ndefine register offset=0x0000 size=4 [ \n\n\tSR\t\t\tEVBA\t\tACBA\t\tCPUCR\t\tECR\t\t\tRSR_SUP\t\tRSR_INT0\tRSR_INT1\n\tRSR_INT2\tRSR_INT3\tRSR_EX\t\tRSR_NMI\t\tRSR_DBG\t\tRAR_SUP\t\tRAR_INT0\tRAR_INT1\n\tRAR_INT2\tRAR_INT3\tRAR_EX\t\tRAR_NMI\t\tRAR_DBG\t\tJECR\t\tJOSP\t\tJAVA_LV0\n\tJAVA_LV1 \tJAVA_LV2 \tJAVA_LV3 \tJAVA_LV4 \tJAVA_LV5 \tJAVA_LV6 \tJAVA_LV7 \tJTBA\n\tJBCR\n];\n\ndefine register offset=0x0100 size=4 [ \n\tCONFIG0\tCONFIG1\tCOUNT\tCOMPARE\tTLBEHI\t\tTLBELO\t\tPTBR\tTLBEAR\n\tMMUCR\tTLBARLO\tTLBARHI\tPCCNT\tPCNT0\t\tPCNT1\t\tPCCR\tBEAR\n\tMPUAR0\tMPUAR1\tMPUAR2\tMPUAR3\tMPUAR4\t\tMPUAR5\t\tMPUAR6\tMPUAR7\n\tMPUPSR0\tMPUPSR1\tMPUPSR2\tMPUPSR3\tMPUPSR4\t\tMPUPSR5\t\tMPUPSR6\tMPUPSR7\n\tMPUCRA\tMPUCRB\tMPUBRA\tMPUBRB\tMPUAPRA\t\tMPUAPRB\t\tMPUCR\tSS_STATUS\n\tSS_ADRF\tSS_ADRR\tSS_ADR0\tSS_ADR1\tSS_SP_SYS\tSS_SP_APP\tSS_RAR\tSS_RSR\n];\n\n# 103-191 reserved for future use\n# 192-255 implementation defined\n\ndefine register offset=0x1000 size=4 [\n\tR0\tR1\tR2\tR3\tR4\tR5\tR6\tR7\n\tR8\tR9\tR10\tR11\tR12\tSP\tLR\tPC\n];\n\ndefine register offset=0x1100 size=1 [\n\tC Z N V Q L _ _ _ _ _ _ _ _ T R\n\tGM I0M I1M I2M I3M EM M0 M1 M2 _ D DM J H _ _\n\tALWAYS_TRUE\n];\n\nmacro SRTOLOWFLAGS() {\n\tC =\t\t(SR & 0x1) != 0;\n\tZ =\t\t(SR & 0x2) != 0;\n\tN =\t\t(SR & 0x4) != 0;\n\tV =\t\t(SR & 0x8) != 0;\n}\n\nmacro SRTOFLAGS() {\n\tC =\t\t(SR & 0x1) != 0;\n\tZ =\t\t(SR & 0x2) != 0;\n\tN =\t\t(SR & 0x4) != 0;\n\tV =\t\t(SR & 0x8) != 0;\n\tQ =\t\t(SR & 0x10) != 0;\n\tL =\t\t(SR & 0x20) != 0;\n\tT =\t\t(SR & 0x4000) != 0;\n\tR =\t\t(SR & 0x8000) != 0;\n\tGM =\t(SR & 0x10000) != 0;\n\tI0M =\t(SR & 0x20000) != 0;\n\tI1M =\t(SR & 0x40000) != 0;\n\tI2M =\t(SR & 0x80000) != 0;\n\tI3M =\t(SR & 0x100000) != 0;\n\tEM =\t(SR & 0x200000) != 0;\n\tM0 =\t(SR & 0x400000) != 0;\n\tM1 =\t(SR & 0x800000) != 0;\n\tM2 =\t(SR & 0x1000000) != 0;\n\tD =\t\t(SR & 0x4000000) != 0;\n\tDM =\t(SR & 0x8000000) != 0;\n\tJ =\t\t(SR & 0x10000000) != 0;\n\tH =\t\t(SR & 0x20000000) != 0;\n}\n\nmacro CZNVTOSR() {\n\ttmp:4 = zext(C&1) | (zext(Z&1) << 1) | (zext(N&1) << 2) | (zext(V&1) << 3);\n\tSR = (SR & 0xFFFFFFF0) | tmp;\n}\n\nmacro CZNVQTOSR() {\n\ttmp:4 = zext(C&1) | (zext(Z&1) << 1) | (zext(N&1) << 2) | (zext(V&1) << 3) | (zext(Q&1) << 4);\n\tSR = (SR & 0xFFFFFFE0) | tmp;\n}\n\nmacro QTOSR() {\n\tSR = (SR & 0xFFFFFFEF) | (zext(Q&1) << 4);\n}\n\nmacro CZTOSR() {\n\ttmp:4 = zext(C&1) | (zext(Z&1) << 1);\n\tSR = (SR & 0xFFFFFFFC) | tmp;\n}\n\nmacro JRGMTOSR() {\n\ttmp:4 = (zext(R&1) << 15) | (zext(GM&1) << 16) | (zext(J&1) << 28);\n\tSR = (SR & 0xEFFFFE7F) | tmp;\n}\n\nmacro LTOSR() {\n\ttmp:4 = zext(L&1) << 5;\n\tSR = (SR & 0xFFFFFFDF) | tmp;\n}\n\ndefine register offset=0x1200 size=4 [\n stadd ldadd\n];\n\ndefine register offset=0x1300 size=4 contextreg;\ndefine context contextreg\n\tctx_rel10=(0,9) signed noflow\n\tctx_rel8_2=(0,1) noflow\n\tctx_rel0_8=(2,9) noflow\n\tctx_rel21=(0,20) signed noflow\n\tctx_rel0_16=(5,20) noflow\n\tctx_rel16_1=(4,4) noflow\n\tctx_rel17_4=(0,3) noflow\n\tctx_rel3=(0,2) signed noflow\n\tctx_savex=(0,3) noflow\n\tctx_usex=(0,3) noflow\n\tctx_savey=(4,7) noflow\n\tctx_usey=(4,7) noflow\n\tctx_useu=(4,7) noflow\n\tctx_shift=(0,4) noflow\n\tctx_shigh=(0,3) noflow\n\tctx_slow=(4,4) noflow\n\tctx_coop=(0,6) noflow\n\tctx_cohi=(0,1) noflow\n\tctx_comid=(2,5) noflow\n\tctx_colow=(6,6) noflow\n\tctx_rdplus=(8,11) noflow\n\tctx_rdsave=(8,11) noflow\n;\n\ndefine token instr1(16)\n\top13_3 =\t(13,15)\n op11_5 = (11, 15)\n op0_3 = (0, 2)\n\trs9 =\t\t(9,12)\n\trp9 =\t\t(9,12)\n rb9 = (9,12)\n\trx9 = (9,12)\n\top9_4 = \t(9,12)\n\top9_7 = \t(9,15)\n\top9_2 =\t\t(9,10)\n\top7_9 =\t\t(7,15)\n\top7_2 =\t\t(7,8)\n\top4_5 =\t\t(4,8)\n\top4_12 = \t(4,15)\n op9_1 = (9,9)\n op8_1 = (8,8)\n op8_8 = (8,15)\n op0_9 =\t\t(0,8)\n\tb9 = \t\t(9,9)\n\top10_6 = (10,15)\n\tdisp4_3 =\t(4,6)\n disp4_5 = (4,8)\n disp4_7 = (4,10)\n disp4_4 = (4,7)\n\trs0 =\t\t(0,3)\n rs0_hi = (1,3)\n rs0_low = (1,3)\n rd0_hi = (1,3)\n rd0_low = (1,3)\n\trp0 =\t\t(0,3)\n\trd0 =\t\t(0,3)\n\trd9 = (9,12)\n\tri0 =\t\t(0,3)\n rb0 = (0,3)\n ry0 = (0,3)\n b0 = (0,0)\n b02 =\t\t(2,2)\n b03 = (3,3)\n b04 = (4,4)\n b05 = (5,5)\n b06 = (6,6)\n b07 = (7,7)\n b08 = (8,8)\n b09 = (9,9)\n b10 = (10,10)\n b11 = (11,11)\n bp9_4 = (9,12)\n bp4_1 = (4,4)\n bp4_2 =\t\t(4,5)\n bp4_3 =\t\t(4,6)\n bp4_4 =\t\t(4,7)\n bp4_5 =\t\t(4,8)\n bp4_6 =\t\t(4,9)\n bp4_7 =\t\t(4,10)\n\tcond4_4 = \t(4,7)\n\tcond0_4 = \t(0,3)\n\tcond0_3 = \t(0,2)\n imm4_8 = \t(4,11) signed\n imm4_6 = \t(4,9) signed\n imm4_5 = \t(4,8)\n\top12_1 = \t(12,12)\n\top5_4 = \t(5,8)\n\timm9_4 = \t(9,12) signed\n\timm4_1 = \t(4,4)\n\timm0_4 = \t(0,3)\n\tb003 = \t\t(0,3)\n\tdisp4_8\t= \t(4,11)\n\tsdisp4_8 = \t(4,11) signed\n\top3_1 = \t(3,3)\n\top3_6 =\t\t(3,8)\n disp21part2_4_1 = (4,4)\n disp21part3_9_4 = (9,12) signed\n\tshift9_4 = \t(9,12)\n\tshift4_1 = \t(4,4)\n\top12_4 = \t(12,15)\n\top0_4 = \t(0,3)\n\tdisp0_2\t=\t(0,1)\n\tsdisp0_2 = \t(0,1) signed\n\top2_2 = \t(2,3)\n\top0_16 =\t(0,15)\n\tsa0_3 =\t\t(0,2)\n\tsa0_4 =\t\t(0,3)\n coh = (9,9)\n;\n\ndefine token instr2(16)\n\tecop13_3 =\t(13,15)\n disp_16 = (0,15) signed\n ddisp_16 = (0,15) signed\n\tdisp_9 = \t(0,8)\n\tdisp_8 = \t(0,7)\n\tdisp12_4 =\t(12,15)\n\tdisp0_11 = \t(0,10) signed\n\tdisp0_12 =\t(0,11) signed\n\tedisp4_8 =\t(4,11)\n\teop14_2 =\t(14,15)\n\teop11_5 = \t(11,15)\n eop12_4 = (12,15)\n eop6_10 = (6,15)\n\teop8_4 =\t(8,11)\n\teop6_2 =\t(6,7)\n\teop5_3 = \t(5,7)\n eop9_3 = (9,11)\n eop8_8 = (8,15)\n\teop0_9 =\t(0,8)\n eop0_4 = (0,3)\n eop9_7 = (9,15)\t\n eop12_1 = (12,12)\n eop5_11 = (5,15)\n eop0_8 = (0,7)\n eop0_16 = (0,15)\n eop4_12 = (4,15)\n eop4_8 = (4,11)\n eop4_4 = (4,7)\n eop10_6 = (10,15)\n eoff5_5 = (5,9)\n eoff0_5 = (0,4)\n elen0_5 = (0,4)\n eop10_2 = \t(10,11) \n esa0_5\t= \t(0,4)\n ebp5_5 = \t(5,9) \n\tcrd8_4 =\t(8,11)\n\tcrd9_3 = \t(9,11)\n\tcrx4_4 =\t(4,7)\n\tcry0_4 =\t(0,3)\n\taltcrd8_4 =\t(8,11)\n\taltcrx4_4 =\t(4,7)\n\taltcry0_4 =\t(0,3)\n\taltcrd9_3 =\t(9,11)\n\tcrd8_1 = \t(8,8)\n\tcp13_3 =\t(13,15)\n\taltcp13_3 =\t(13,15)\n shift4_2 = (4,5)\n shift4_5 = (4,8)\n shift0_5 = (0,4)\n\tselectorxy4_2 =\t(4,5)\n\ters0 =\t\t(0,3)\n\terb0 =\t\t(0,3)\n\terd0 = \t\t(0,3)\n\terd0a =\t\t(0,3)\n\terp0 = \t\t(0,3)\n ers0_hi = (1,3)\n ers0_low = (1,3)\n erd0_hi = (1,3)\n erd0_low = (1,3)\n\tecond12_4 = (12, 15)\n\tecond8_4 = (8, 11)\n\tecond4_4 = (4, 7)\n\teri8 =\t\t(8,11)\n\teri0 =\t\t(0,3)\n eb0 = \t\t(0,0)\n eb1 = \t\t(1,1)\n eb2 = \t\t(2,2)\n eb3 = \t\t(3,3)\n eb4 = \t\t(4,4)\n eb5 = \t\t(5,5)\n eb6 = \t\t(6,6)\n eb7 = \t\t(7,7)\n eb8 = \t\t(8,8)\n eb9 = \t\t(9,9)\n eb10 = \t\t(10,10)\n eb11 = \t\t(11,11)\n eb12 = \t\t(12,12)\n eb13 = \t\t(13,13)\n eb14 = \t\t(14,14)\n eb15 = \t\t(15,15)\n ypart = \t(4,4)\n upart =\t\t(4,4)\n xpart = \t(5,5)\n imm16 = \t(0,15) \n simm16 = \t(0,15) signed\n simm0_8 = \t(0,7) signed\n imm0_8 = \t(0,7)\n simm0_15 =\t(0,14) signed\n imm12_2 = \t(12,13)\n sysreg = \t(0,7)\n dbgreg =\t(0,7)\n disp21part1_0_16 = (0,15)\n deb0 = \t\t(0,0)\n deb1 = \t\t(1,1)\n deb2 = \t\t(2,2)\n deb3 = \t\t(3,3)\n deb4 = \t\t(4,4)\n deb5 = \t\t(5,5)\n deb6 = \t\t(6,6)\n deb7 = \t\t(7,7)\n deb8 = \t\t(8,8)\n deb9 = \t\t(9,9)\n deb10 = \t(10,10)\n deb11 = \t(11,11)\n deb12 = \t(12,12)\n deb13 = \t(13,13)\n deb14 = \t(14,14)\n deb15 = \t(15,15)\n;\n\nattach variables [ rs9 rp9 rd9 rb9 rs0 rb0 rp0 rx9 ry0 rd0 ri0 ers0 erd0 erb0 eri0 erp0 eri8 ctx_rdplus ctx_usex ctx_usey] [\n\tR0\tR1\tR2\tR3\tR4\tR5\tR6\tR7\n\tR8\tR9\tR10\tR11\tR12\tSP\tLR\tPC\n];\n\nattach variables [ rs0_hi rd0_hi erd0_hi ers0_hi ] [\n R1 R3 R5 R7 R9 R11 SP PC\n];\n\nattach variables [ rs0_low rd0_low erd0_low ers0_low ] [\n R0 R2 R4 R6 R8 R10 R12 LR\n]; \n\nattach variables [ deb0 ] [ R0 R0 ];\nattach variables [ deb1 ] [ R1 R1 ];\nattach variables [ deb2 ] [ R2 R2 ];\nattach variables [ deb3 ] [ R3 R3 ];\nattach variables [ deb4 ] [ R4 R4 ];\nattach variables [ deb5 ] [ R5 R5 ];\nattach variables [ deb6 ] [ R6 R6 ];\nattach variables [ deb7 ] [ R7 R7 ];\nattach variables [ deb8 ] [ R8 R8 ];\nattach variables [ deb9 ] [ R9 R9 ];\nattach variables [ deb10 ] [ R10 R10 ];\nattach variables [ deb11 ] [ R11 R11 ];\nattach variables [ deb12 ] [ R12 R12 ];\nattach variables [ deb13 ] [ SP SP ];\nattach variables [ deb14 ] [ LR LR ];\nattach variables [ deb15 ] [ PC PC ];\n\nattach variables [ sysreg]\n[\n\tSR\t\t\tEVBA\t\tACBA\t\tCPUCR\t\tECR\t\t\tRSR_SUP\t\tRSR_INT0\tRSR_INT1\n\tRSR_INT2\tRSR_INT3\tRSR_EX\t\tRSR_NMI\t\tRSR_DBG\t\tRAR_SUP\t\tRAR_INT0\tRAR_INT1\n\tRAR_INT2\tRAR_INT3\tRAR_EX\t\tRAR_NMI\t\tRAR_DBG\t\tJECR\t\tJOSP\t\tJAVA_LV0\n\tJAVA_LV1 \tJAVA_LV2 \tJAVA_LV3 \tJAVA_LV4 \tJAVA_LV5 \tJAVA_LV6 \tJAVA_LV7 \tJTBA\n\tJBCR\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\tCONFIG0\t\tCONFIG1\t\tCOUNT\t\tCOMPARE\t\tTLBEHI\t\tTLBELO\t\tPTBR\t\tTLBEAR\n\tMMUCR\t\tTLBARLO\t\tTLBARHI\t\tPCCNT\t\tPCNT0\t\tPCNT1\t\tPCCR\t\tBEAR\n\tMPUAR0\t\tMPUAR1\t\tMPUAR2\t\tMPUAR3\t\tMPUAR4\t\tMPUAR5\t\tMPUAR6\t\tMPUAR7\n\tMPUPSR0\t\tMPUPSR1\t\tMPUPSR2\t\tMPUPSR3\t\tMPUPSR4\t\tMPUPSR5\t\tMPUPSR6\t\tMPUPSR7\n\tMPUCRA\t\tMPUCRB\t\tMPUBRA\t\tMPUBRB\t\tMPUAPRA\t\tMPUAPRB\t\tMPUCR\t\tSS_STATUS\n\tSS_ADRF\t\tSS_ADRR\t\tSS_ADR0\t\tSS_ADR1\t\tSS_SP_SYS\tSS_SP_APP\tSS_RAR\t\tSS_RSR\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\t\t\t_\n];\n\n# loadCoprocessorWord(CP:1, CRd:1, address:4)\ndefine pcodeop loadCoprocessorWord;\n\n# loadCoprocessorDWord(CP:1, CRd:1, address:4)\ndefine pcodeop loadCoprocessorDWord;\n\ndefine pcodeop CoProcessorDWordToReg;\ndefine pcodeop CoProcessorWordToReg;\ndefine pcodeop RegToCoProcessorDWord;\ndefine pcodeop RegToCoProcessorWord;\ndefine pcodeop storeCoprocessorDword;\ndefine pcodeop storeCoprocessorWord;\ndefine pcodeop CoprocessorOp;\ndefine pcodeop LoadCoProcessorWord;\ndefine pcodeop LoadCoProcessorDword;\n\ndefine pcodeop trap;\ndefine pcodeop cacheOp;\ndefine pcodeop CacheFetch;\n\ndefine pcodeop doSleep;\n\ndefine pcodeop CheckAndRestoreInterupt;\ndefine pcodeop CheckAndRestoreSupervisor;\n\ndefine pcodeop ReadTLBEntry;\ndefine pcodeop WriteTLBEntry;\ndefine pcodeop SearchTLBEntry;\n\ndefine pcodeop SynchMemory;\n\ndefine pcodeop JavaTrap;\ndefine pcodeop JavaPopContext;\ndefine pcodeop JavaPushContext;\ndefine pcodeop JavaCheckStack;\n\ndefine pcodeop SupervisorCallSetup;\n\ndefine pcodeop MoveToDebugReg;\ndefine pcodeop MoveFromDebugReg;\n\n# conditions\n\n# STATUS REGISTER MAP: (LOW)\n# C - CARRY\n# Z - ZERO\n# N - NEGATIVE\n# V - OVERFLOW\n# Q - SATURATION\n# L - LOCK\n# T - SCRATCH\n# R - REMAP\n\n# STATUS REGISTER MAP: (HIGH)\n# GM - Global Interrupt Mask\n# I0M - Interrupt Level 0 Mask\n# I1M - Interrupt Level 1 Mask\n# I2M - Interrupt Level 2 Mask\n# I3M - Interrupt Level 3 Mask\n# EM - Exception Mask\n# M0 - Execution Mode 0\n# M1 - Execution Mode 1\n# M2 - Execution Mode 2\n# D - Debug State\n# DM - Debug State Mask\n# J - Java State\n# H - Java Handle\n\n\n#Cond4 Registers Extended (12,15)\ncc4_e12: \"EQ\" is econd12_4=0x0 { export Z; }\ncc4_e12: \"NE\" is econd12_4=0x1 { tmp:1 = !Z; export tmp; }\ncc4_e12: \"HS\" is econd12_4=0x2 { tmp:1 = !C; export tmp; }\ncc4_e12: \"LO\" is econd12_4=0x3 { export C; }\ncc4_e12: \"GE\" is econd12_4=0x4 { tmp:1 = N == V; export tmp;}\ncc4_e12: \"LT\" is econd12_4=0x5 { tmp:1 = N!=V; export tmp; }\ncc4_e12: \"MI\" is econd12_4=0x6 { export N; }\ncc4_e12: \"PL\" is econd12_4=0x7 { tmp:1 = !N; export tmp; }\ncc4_e12: \"LS\" is econd12_4=0x8 { tmp:1 = C || Z; export tmp; }\ncc4_e12: \"GT\" is econd12_4=0x9 { tmp:1 = !Z && (N == V); export tmp; }\ncc4_e12: \"LE\" is econd12_4=0xa { tmp:1 = Z || (N!=V); export tmp; }\ncc4_e12: \"HI\" is econd12_4=0xb { tmp:1 = !C && !Z; export tmp; }\ncc4_e12: \"VS\" is econd12_4=0xc { export V; }\ncc4_e12: \"VC\" is econd12_4=0xd { tmp:1 = !V; export tmp; }\ncc4_e12: \"QS\" is econd12_4=0xe { export Q; }\ncc4_e12: \"AL\" is econd12_4=0xf { export ALWAYS_TRUE; }\n\nCOND_e12: cc4_e12 is cc4_e12 { if (!cc4_e12) goto inst_next; }\nCOND_e12: cc4_e12 is cc4_e12 & econd12_4=0xf { }\n\n#Cond4 Registers Extended (4,7)\ncc4_4: \"EQ\" is cond4_4=0x0 { export Z; }\ncc4_4: \"NE\" is cond4_4=0x1 { tmp:1 = !Z; export tmp; }\ncc4_4: \"HS\" is cond4_4=0x2 { tmp:1 = !C; export tmp; }\ncc4_4: \"LO\" is cond4_4=0x3 { export C; }\ncc4_4: \"GE\" is cond4_4=0x4 { tmp:1 = N == V; export tmp;}\ncc4_4: \"LT\" is cond4_4=0x5 { tmp:1 = N!=V; export tmp; }\ncc4_4: \"MI\" is cond4_4=0x6 { export N; }\ncc4_4: \"PL\" is cond4_4=0x7 { tmp:1 = !N; export tmp; }\ncc4_4: \"LS\" is cond4_4=0x8 { tmp:1 = C || Z; export tmp; }\ncc4_4: \"GT\" is cond4_4=0x9 { tmp:1 = !Z && (N == V); export tmp; }\ncc4_4: \"LE\" is cond4_4=0xa { tmp:1 = Z || (N!=V); export tmp; }\ncc4_4: \"HI\" is cond4_4=0xb { tmp:1 = !C && !Z; export tmp; }\ncc4_4: \"VS\" is cond4_4=0xc { export V; }\ncc4_4: \"VC\" is cond4_4=0xd { tmp:1 = !V; export tmp; }\ncc4_4: \"QS\" is cond4_4=0xe { export Q; }\ncc4_4: \"AL\" is cond4_4=0xf { export ALWAYS_TRUE; }\n\nCOND_4_4: cc4_4 is cc4_4 { if (!cc4_4) goto inst_next; }\nCOND_4_4: cc4_4 is cc4_4 & cond4_4=0xf { }\n\n#Cond4 Registers Extended (4,7)\necc4_4: \"EQ\" is econd4_4=0x0 { export Z; }\necc4_4: \"NE\" is econd4_4=0x1 { tmp:1 = !Z; export tmp; }\necc4_4: \"HS\" is econd4_4=0x2 { tmp:1 = !C; export tmp; }\necc4_4: \"LO\" is econd4_4=0x3 { export C; }\necc4_4: \"GE\" is econd4_4=0x4 { tmp:1 = N == V; export tmp;}\necc4_4: \"LT\" is econd4_4=0x5 { tmp:1 = N!=V; export tmp; }\necc4_4: \"MI\" is econd4_4=0x6 { export N; }\necc4_4: \"PL\" is econd4_4=0x7 { tmp:1 = !N; export tmp; }\necc4_4: \"LS\" is econd4_4=0x8 { tmp:1 = C || Z; export tmp; }\necc4_4: \"GT\" is econd4_4=0x9 { tmp:1 = !Z && (N == V); export tmp; }\necc4_4: \"LE\" is econd4_4=0xa { tmp:1 = Z || (N!=V); export tmp; }\necc4_4: \"HI\" is econd4_4=0xb { tmp:1 = !C && !Z; export tmp; }\necc4_4: \"VS\" is econd4_4=0xc { export V; }\necc4_4: \"VC\" is econd4_4=0xd { tmp:1 = !V; export tmp; }\necc4_4: \"QS\" is econd4_4=0xe { export Q; }\necc4_4: \"AL\" is econd4_4=0xf { export ALWAYS_TRUE; }\n\nECOND_4_4: ecc4_4 is ecc4_4 { if (!ecc4_4) goto inst_next; }\nECOND_4_4: ecc4_4 is ecc4_4 & econd4_4=0xf { }\n\n#Cond4 Registers Extended (4,7)\necc8_4: \"EQ\" is econd8_4=0x0 { export Z; }\necc8_4: \"NE\" is econd8_4=0x1 { tmp:1 = !Z; export tmp; }\necc8_4: \"HS\" is econd8_4=0x2 { tmp:1 = !C; export tmp; }\necc8_4: \"LO\" is econd8_4=0x3 { export C; }\necc8_4: \"GE\" is econd8_4=0x4 { tmp:1 = N == V; export tmp;}\necc8_4: \"LT\" is econd8_4=0x5 { tmp:1 = N!=V; export tmp; }\necc8_4: \"MI\" is econd8_4=0x6 { export N; }\necc8_4: \"PL\" is econd8_4=0x7 { tmp:1 = !N; export tmp; }\necc8_4: \"LS\" is econd8_4=0x8 { tmp:1 = C || Z; export tmp; }\necc8_4: \"GT\" is econd8_4=0x9 { tmp:1 = !Z && (N == V); export tmp; }\necc8_4: \"LE\" is econd8_4=0xa { tmp:1 = Z || (N!=V); export tmp; }\necc8_4: \"HI\" is econd8_4=0xb { tmp:1 = !C && !Z; export tmp; }\necc8_4: \"VS\" is econd8_4=0xc { export V; }\necc8_4: \"VC\" is econd8_4=0xd { tmp:1 = !V; export tmp; }\necc8_4: \"QS\" is econd8_4=0xe { export Q; }\necc8_4: \"AL\" is econd8_4=0xf { export ALWAYS_TRUE; }\n\nECOND_8_4: ecc8_4 is ecc8_4 { if (!ecc8_4) goto inst_next; }\nECOND_8_4: ecc8_4 is ecc8_4 & econd8_4=0xf { }\n\n#Cond3 Registers(0 - 2) \ncc3_0: \"eq\" \t\tis cond0_3=0x0\t \t{ export Z; }\ncc3_0: \"ne\" \t\tis cond0_3=0x1\t\t{ tmp:1 = !Z; export tmp; }\ncc3_0: \"cc/hs\" \tis cond0_3=0x2\t\t\t{ tmp:1 = !C; export tmp; }\ncc3_0: \"cc/lo\" \tis cond0_3=0x3\t\t\t{ export C; }\ncc3_0: \"ge\" \t\tis cond0_3=0x4\t\t{ tmp:1 = N == V; export tmp;}\ncc3_0: \"lt\" \t\tis cond0_3=0x5\t\t{ tmp:1 = N!=V; export tmp; }\ncc3_0: \"mi\" \t\tis cond0_3=0x6\t\t{ export N; }\ncc3_0: \"pl\" \t\tis cond0_3=0x7\t\t{ tmp:1 = !N; export tmp; }\n\nCOND_3: cc3_0 \t\tis cc3_0\t\t\t{ export cc3_0; }\n\n#Cond4 Registers(0 - 3)\ncc4_0: \"eq\" \t\tis cond0_4=0x0\t \t{ export Z; }\ncc4_0: \"ne\" \t\tis cond0_4=0x1\t\t{ tmp:1 = !Z; export tmp; }\ncc4_0: \"cc/hs\" \t\tis cond0_4=0x2\t\t{ tmp:1 = !C; export tmp; }\ncc4_0: \"cc/lo\" \t\tis cond0_4=0x3\t\t{ export C; }\ncc4_0: \"ge\" \t\tis cond0_4=0x4\t\t{ tmp:1 = N == V; export tmp;}\ncc4_0: \"lt\" \t\tis cond0_4=0x5\t\t{ tmp:1 = N!=V; export tmp; }\ncc4_0: \"mi\" \t\tis cond0_4=0x6\t\t{ export N; }\ncc4_0: \"pl\" \t\tis cond0_4=0x7\t\t{ tmp:1 = !N; export tmp; }\ncc4_0: \"ls\" \t\tis cond0_4=0x8\t\t{ tmp:1 = C || Z; export tmp; }\ncc4_0: \"gt\" \t\tis cond0_4=0x9\t\t{ tmp:1 = !Z && (N == V); export tmp; }\ncc4_0: \"le\" \t\tis cond0_4=0xa\t\t{ tmp:1 = Z || (N!=V); export tmp; }\ncc4_0: \"hi\" \t\tis cond0_4=0xb\t\t{ tmp:1 = !C && !Z; export tmp; }\ncc4_0: \"vs\" \t\tis cond0_4=0xc\t\t{ export V; }\ncc4_0: \"vc\" \t\tis cond0_4=0xd\t\t{ tmp:1 = !V; export tmp; }\ncc4_0: \"qs\" \t\tis cond0_4=0xe\t\t{ export Q; }\ncc4_0: \"al\" \t\tis cond0_4=0xf\t\t{ export ALWAYS_TRUE; }\n\nCOND_4_0: cc4_0 is cc4_0 { if (!cc4_0) goto inst_next; }\nCOND_4_0: cc4_0 is cc4_0 & cond0_4=0xf { }\n\nRP9bInc: rp9++\t\t\tis rp9\t{ ptr:4 = rp9; rp9 = rp9 + 1; export ptr; }\nRPhInc: rp9++\t\t\tis rp9\t{ ptr:4 = rp9; rp9 = rp9 + 2; export ptr; }\nRPwInc: rp9++\t\t\tis rp9\t{ ptr:4 = rp9; rp9 = rp9 + 4; export ptr; }\nRPdInc: rp9++\t\t\tis rp9\t{ ptr:4 = rp9; rp9 = rp9 + 8; export ptr; }\n\nRP9bDec: --rp9\t\t\tis rp9\t{ rp9 = rp9 - 1; ptr:4 = rp9; export ptr; }\nRPhDec: --rp9\t\t\tis rp9\t{ rp9 = rp9 - 2; ptr:4 = rp9; export ptr; }\nRPwDec: --rp9 is rp9 { rp9 = rp9 - 4; ptr:4 = rp9; export ptr; }\nRPdDec: --rp9 is rp9 { rp9 = rp9 - 8; ptr:4 = rp9; export ptr; }\n\nRPwDec0: --rp0\t\t\tis rp0\t{ rp0 = rp0 - 4; ptr:4 = rp0; export ptr; }\nRPdDec0: --rp0\t\t\tis rp0\t{ rp0 = rp0 - 8; ptr:4 = rp0; export ptr; }\n\nRPbDisp3: rp9[disp4_3]\tis rp9 & disp4_3 { ptr:4 = rp9 + disp4_3; export ptr; }\n\nRPhDisp3: rp9[disp]\tis rp9 & disp4_3\n[ disp = disp4_3 << 1; ]\n{ ptr:4 = rp9 + disp; export ptr; }\n\nRPwDisp4: rp9[disp] is rp9 & disp4_4\n[ disp = disp4_4 << 2; ]\n{ ptr:4 = rp9 + disp; export ptr; }\n\nRPwDisp5: rp9[disp] is rp9 & disp4_5\n[ disp = disp4_5 << 2; ]\n{ ptr:4 = rp9 + disp; export ptr; }\n\nRPwDisp8: rp0[disp]\tis rp0; disp_8\n[ disp = disp_8 << 2; ]\n{ ptr:4 = rp0 + disp; export ptr; }\n\nRPbDisp9: rp9[disp_9]\tis rp9; disp_9 { ptr:4 = rp9 + disp_9; export ptr; }\t\n\nRPhDisp9: rp9[disp]\tis rp9; disp_9\n[ disp = disp_9 << 1; ]\n{ ptr:4 = rp9 + disp; export ptr; }\n\nRPwDisp9: rp9[disp]\tis rp9; disp_9\n[ disp = disp_9 << 2; ]\n{ ptr:4 = rp9 + disp; export ptr; }\n\nRPwDisp12: rp0[disp]\tis rp0; disp12_4 & disp_8\n[ disp = ((disp12_4 << 8) | disp_8) << 2; ]\n{ ptr:4 = rp0 + disp; export ptr; }\n\t\nPCDisp16: loc\t\t\tis disp_16 [ loc = inst_start + disp_16; ] { export *[const]:4 loc; }\n\nRPDisp16: rp9[disp_16] is rp9; disp_16 { ptr:4 = rp9 + disp_16; export ptr; }\nRPDisp16: PC[disp_16] is rp9=15 & PC; disp_16 & PCDisp16 { export PCDisp16; }\n\nRB9Shift: rb9[ri0 \"<<\" shift4_2] is rb9 & ri0; shift4_2 { ptr:4 = rb9 + (ri0 << shift4_2); export ptr; }\n\nRBShift0: rb0[eri0 \"<<\" shift4_2] is rb0; eri0 & shift4_2 { ptr:4 = rb0 + (eri0 << shift4_2); export ptr; }\n\nRBSelector: rb9[ri0\" << 2]\" is rb9 & ri0; selectorxy4_2=0x0 { ptr:4 = rb9 + ((ri0 & 0xff) << 0x02); export ptr; }\nRBSelector: rb9[ri0\" << 2]\" is rb9 & ri0; selectorxy4_2=0x1 { ptr:4 = rb9 + (((ri0 >> 8) & 0xff) << 0x02); export ptr; }\nRBSelector: rb9[ri0\" << 2]\" is rb9 & ri0; selectorxy4_2=0x2 { ptr:4 = rb9 + (((ri0 >> 16) & 0xff) << 0x02); export ptr; }\nRBSelector: rb9[ri0\" << 2]\" is rb9 & ri0; selectorxy4_2=0x3 { ptr:4 = rb9 + (((ri0 >> 24) & 0xff) << 0x02); export ptr; }\n\nRS0A: rs0\t\tis rs0 { export rs0; }\nRS0A: rs0\t\tis rs0 & rs0=0xf { export *[const]:4 inst_start; }\n\nRS9A: rs9\t\tis rs9 { export rs9; }\nRS9A: rs9\t\tis rs9 & rs9=0xf { export *[const]:4 inst_start; }\n\nRX9A: rx9\t\tis rx9 { export rx9; }\nRX9A: rx9\t\tis rx9 & rx9=0xf { export *[const]:4 inst_start; }\n\nRY0A: ry0\t\tis ry0 { export ry0; }\nRY0A: ry0\t\tis ry0 & ry0=0xf { export *[const]:4 inst_start; }\n\nRD0A: rd0\t\tis rd0 { export rd0; }\nRD0A: rd0\t\tis rd0 & rd0=0xf { export *[const]:4 inst_start; }\n\nmacro ZSTATUS(RES) {\n Z = RES == 0;\n CZNVTOSR();\n}\n\nmacro NZSTATUS(RES) {\n N = RES s< 0;\n ZSTATUS(RES);\n CZNVTOSR();\n}\n\nmacro addflags(OP1, OP2, RES) {\n\n ## The REAL way to do it (in the processor spec)\n #V = (OP1[31,1] && OP2[31,1] && !(RES[31,1])) ||\n # (!(OP1[31,1]) && !(OP2[31,1]) && RES[31,1]);\n\n V = scarry(OP1, OP2);\n \n NZSTATUS(RES); \n\n ## The REAL way to do it (in the processor spec)\n #C = (OP1[31,1] && OP2[31,1]) ||\n # (OP1[31,1] && !(RES[31,1])) ||\n # (OP2[31,1] && !(RES[31,1]));\n\n C = carry(OP1, OP2);\n CZNVTOSR();\n}\n\nmacro subflags(OP1, OP2, RES) {\n\n ## The REAL way to do it (in the processor spec)\n #V = (OP1[31,1] && !(OP2[31,1]) && !(RES[31,1])) ||\n # (!(OP1[31,1]) && OP2[31,1] && RES[31,1]);\n\n V = sborrow(OP1, OP2);\n \n NZSTATUS(RES); \n\n ## The REAL way to do it (in the processor spec)\n #C = (!(OP1[31,1]) && (OP2[31,1])) ||\n # (OP2[31,1] && RES[31,1]) ||\n # (!(OP1[31,1]) && RES[31,1]);\n\n C = OP1 < OP2;\n CZNVTOSR();\n}\n\n@include \"avr32a_arithmetic_operations.sinc\"\n@include \"avr32a_multiplication_operations.sinc\"\n@include \"avr32a_logic_operations.sinc\"\n@include \"avr32a_bit_operations.sinc\"\n@include \"avr32a_shift_operations.sinc\"\n@include \"avr32a_data_transfer.sinc\"\n@include \"avr32a_system_control.sinc\"\n@include \"avr32a_coprocessor_interface.sinc\"\n@include \"avr32a_instruction_flow.sinc\"\n@include \"avr32a_simd_operations.sinc\"\n@include \"avr32a_dsp_operations2.sinc\"\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_arithmetic_operations.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.2 Arithmetic Operations\n#---------------------------------------------------------------------\nmacro cpcflags(OP1, OP2, RES) {\n\n ## The REAL way to do it (in the processor spec)\n #V = (OP1[31,1] && !(OP2[31,1]) && !(RES[31,1])) ||\n # (!(OP1[31,1]) && OP2[31,1] && RES[31,1]);\n\n V = sborrow(OP1, OP2);\n\n N = RES s< 0;\n Z = RES == 0 & Z;\n\n ## The REAL way to do it (in the processor spec)\n C = (!(OP1[31,1]) && (OP2[31,1])) ||\n (OP2[31,1] && RES[31,1]) ||\n (!(OP1[31,1]) && RES[31,1]);\n\n #C = OP1 < OP2;\n CZNVTOSR();\n}\n\n# DUPLICATE CPCFLAGS TO ACCOUNT FOR OP2 == 0\nmacro cpcflags0(OP1, RES) {\n\n ## The REAL way to do it (in the processor spec)\n #V = (OP1[31,1] && !(OP2[31,1]) && !(RES[31,1])) ||\n # (!(OP1[31,1]) && OP2[31,1] && RES[31,1]);\n\n V = sborrow(OP1, 0);\n\n N = RES s< 0;\n Z = RES == 0 & Z;\n\n ## The REAL way to do it (in the processor spec)\n #C = (!(OP1[31,1]) && (OP2[31,1])) ||\n # (OP2[31,1] && RES[31,1]) ||\n # (!(OP1[31,1]) && RES[31,1]);\n\n C = 0;\n CZNVTOSR();\n}\n\nmacro acrflags(OP1, tmpC, RES) {\n\t## The REAL way to do it (in the processor spec)\n\t# V = RES[31,1] && !Rd[31,1];\n\tV = scarry(OP1, tmpC);\n\tN = RES s< 0;\n\tZ = ((RES == 0) && Z);\n\t## The REAL way to do it (in the processor spec)\n\t# C = RES[31,1] && Rd[31,1];\n\tC = carry(OP1, tmpC);\n\tCZNVTOSR();\n}\n#---------------------------------------------------------------------\n# ABS - Absolute Value\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n#ABS Format I\n# Operation:\tRd <- abs(Rd);\n# Syntax: \t\tabs Rd\n# 010 1110 00100 dddd\t(Opcode Form)\n# 0101 1100 0100 dddd\t(Byte half Form)\n:ABS rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x4 {\n\tlocal ztst:1 = rd0 s< 0;\n\trd0 = (zext(!ztst)*rd0) + (zext(ztst)*(-rd0));\n\tZSTATUS(rd0); \n}\n\n\n#---------------------------------------------------------------------\n# ACR - Add carry to register\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n#ACR Format I\n# Operation: \tRd <- Rd + C;\n# Syntax: \t\tacr Rd\n# 010 1110 00000 dddd \t(Opcode Form)\n# 0101 1100 0000 dddd \t(Byte half Form)\n:ACR rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x0 {\n\ttmpRd0:4 = rd0;\n\ttmpC:4 = zext(C);\n\trd0 = tmpRd0 + tmpC;\n\tacrflags(tmpRd0, tmpC, rd0);\n}\n\n:ACR rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x0 & rd0=0xf {\n\ttmpRd0:4 = inst_start;\n\ttmpC:4 = zext(C);\n\tPC = tmpRd0 + tmpC;\n\tacrflags(tmpRd0, tmpC, PC);\n\tgoto [PC];\n}\n\n#---------------------------------------------------------------------\n# ADC - Add with Carry\n# I. {d, x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n#ADC Format I\n# Operation: \tRd <- Rx + Ry + C;\n# Syntax:\t\tadc Rd, Rx, Ry\n# 111 xxxx 00000 yyyy 0000 00000100 dddd\t(Opcode Form)\n# 111x xxx0 0000 yyyy 0000 0000 0100 dddd\t(Byte half Form)\n:ADC erd0, RX9A, RY0A is op13_3=0x7 & RX9A & op4_5=0x0 & RY0A; eop12_4=0x0 & eop4_8=0x4 & erd0 {\n\terd0 = RX9A + RY0A + zext(C);\n}\n\n:ADC erd0, RX9A, RY0A is op13_3=0x7 & RX9A & op4_5=0x0 & RY0A; eop12_4=0x0 & eop4_8=0x4 & erd0 & erd0=0xf{\n\tPC = RX9A + RY0A + zext(C);\n\tgoto [PC];\n}\n\n\n#---------------------------------------------------------------------\n# ADD - Add without Carry\n# I. {d, s} -> {0, 1, ..., 15}\n# II. {d, x, y} -> {0, 1, ..., 15}\n# sa -> {0, 1, 2, 3}\n#---------------------------------------------------------------------\n# ADD Format I\n# Operation: Rd <- Rd + Rs\n# Syntax: add Rd, Rs\n# 000s sss0 0000 dddd\n:ADD rd0, RS9A is op13_3=0x0 & op4_5=0x0 & rd0 & RS9A {\n tmpRd0:4 = rd0;\n rd0 = RS9A + tmpRd0;\n addflags(tmpRd0, RS9A, rd0);\n}\n\n:ADD PC, RS9A is op13_3=0x0 & op4_5=0x0 & rd0 & RS9A & rs0=0xf & PC {\n tmpRd0:4 = inst_start;\n PC = RS9A + tmpRd0;\n addflags(tmpRd0, RS9A, PC);\n goto [PC];\n}\n\n# ADD Format II\n# Operation: Rd <- Rx + Ry << sa2\n# Syntax: add Rd, Rx, Ry << sa\n# 111x xxx0 0000 yyyy 0000 0000 00tt dddd\n:ADD erd0, RX9A, RY0A^\" << \" shift4_2 is op13_3=7 & op4_5=0 & RX9A & RY0A;\n eop6_10=0 & erd0 & shift4_2 {\n tmp:4 = RY0A << shift4_2;\n erd0 = RX9A + tmp;\n addflags(RX9A, tmp, erd0);\n}\n\n:ADD erd0, RX9A, RY0A^\" << \" shift4_2 is op13_3=7 & op4_5=0 & RX9A & RY0A;\n eop6_10=0 & erd0 & shift4_2 & ers0=0xf {\n tmp:4 = RY0A << shift4_2;\n PC = RX9A + tmp;\n addflags(RX9A, tmp, PC);\n goto [PC];\n}\n\n\n#---------------------------------------------------------------------\n# ADD{cond4} - Conditional Add\n# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} \n# {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# ADD{cond4} Format I\n# Operation: if(cond4) then\n# Rd <- Rx + Ry\n# Syntax: add{cond4} Rd, Rx, Ry\n# 111x xxx1 1101 yyyy 1110 cccc 0000 dddd\n\n:ADD^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=0 & ECOND_8_4 & erd0)\n{\n build ECOND_8_4;\n erd0 = RX9A + RY0A;\n}\n\n:ADD^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=0 & ECOND_8_4 & erd0 & erd0=0xf)\n{\n build ECOND_8_4;\n PC = RX9A + RY0A;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# ADDABS - Add Absolute Value\n# I. {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# ADDABS Format I\n# Operation: Rd <- Rx + |Ry|\n# Syntax: addabs Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1110 0100 dddd\n\n:ADDABS erd0, RX9A, RY0A is (op13_3=7 & op4_5=0 & RX9A & RY0A; eop4_12=0xe4 & erd0)\n{\n\t\tlocal ztst:1 = RY0A s< 0;\n\t\tlocal ary0:4 = (zext(!ztst)*RY0A) + (zext(ztst)*(-RY0A));\n erd0 = RX9A + ary0;\n ZSTATUS(erd0);\n}\n\n:ADDABS erd0, RX9A, RY0A is (op13_3=7 & op4_5=0 & RX9A & RY0A; eop4_12=0xe4 & erd0 & erd0=0xf)\n{\n\t\tlocal ztst:1 = RY0A s< 0;\n\t\tlocal ary0:4 = (zext(!ztst)*RY0A) + (zext(ztst)*(-RY0A));\n PC = RX9A + ary0;\n ZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# CP.B - Compare Byte\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n# CP.B Format I\n# Operation: Rd[7:0] - Rs[7:0]\n# Syntax: cp.b Rd, Rs\n# 111s sss0 0000 dddd 0001 1000 0000 0000\n\n:CP.B RD0A, RS9A is op13_3=7 & op4_5=0 & RD0A & RS9A; eop0_16=0x1800 {\n\t\t\n tmp:1 = RD0A:1 - RS9A:1;\n\n subflags(RD0A:1, RS9A:1, tmp);\n}\n\n#---------------------------------------------------------------------\n# CP.H - Compare Halfword\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n# CP.H Format I\n# Operation: Rd[15:0] - Rs[15:0]\n# Syntax: cp.h Rd, Rs\n# 111s sss0 0000 dddd 0001 1001 0000 0000\n\n:CP.H RD0A, RS9A is op13_3=7 & op4_5=0 & RD0A & RS9A; eop0_16=0x1900 {\n tmp:2 = RD0A:2 - RS9A:2;\n subflags(RD0A:2, RS9A:2, tmp);\n}\n\n#---------------------------------------------------------------------\n# CP.W - Compare Word\n# I. {d, s} -> {0, 1, ..., 15}\n# II. d -> {0, 1, ..., 15}\n# imm -> {-32, -31, ..., 31}\n# III. d -> {0, 1, ..., 15}\n# imm -> {-1048576, -1048575, ..., 1048575}\n#---------------------------------------------------------------------\n# CP.W Format I\n# Operation: Rd - Rs\n# Syntax: cp.w Rd, Rs\n# 000s sss0 0011 dddd\n\n:CP.W RD0A, RS9A is op13_3=0x0 & op4_5=0x3 & RD0A & RS9A {\n tmp:4 = RD0A - RS9A;\n subflags(RD0A, RS9A, tmp);\n}\n\n# CP.W Format II\n# Operation: Rd - SE(imm6)\n# Syntax: cp.w Rd, imm\n# 0101 10ii iiii dddd\n\n:CP.W RD0A, imm4_6 is op10_6=0x16 & imm4_6 & RD0A {\n tmp:4 = RD0A - imm4_6;\n subflags(RD0A, imm4_6, tmp);\n}\n\n# CP.W Format III\n# Operation: Rd - SE(imm21)\n# Syntax: cp.w Rd, imm\n# 111i iii0 010i dddd iiii iiii iiii iiii\n\n:CP.W RD0A, imm is op13_3=0x7 & op5_4=0x2 & imm9_4 & imm4_1 & RD0A; imm16\n [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ]\n{\n tmp:4 = RD0A - imm;\n subflags(RD0A, imm, tmp);\n}\n\n#---------------------------------------------------------------------\n# CPC - Compare with Carry\n# I. {d, s} -> {0, 1, ..., 15}\n# II. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# CPC Format I\n# Operation: Rd - Rs - C\n# Syntax: cpc Rd, Rs\n# 111s sss0 0000 dddd 0001 0011 0000 0000\n\n:CPC RD0A, RS9A is op13_3=0x7 & op4_5=0x0 & RD0A & RS9A ; eop0_16=0x1300\n{\n temp:4 = RD0A - RS9A - zext(C);\n cpcflags(RD0A, RS9A, temp);\n}\n\n# CPC Format II\n# Operation: Rd - C\n# Syntax: cpc Rd\n# 0101 1100 0010 dddd\n\n:CPC RD0A is op4_12=0x5c2 & RD0A\n{\n temp:4 = RD0A - zext(C);\n cpcflags0(RD0A, temp);\n}\n\n#---------------------------------------------------------------------\n# MAX - Return Maximum Value\n# I. {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MAX Format I\n# Operation: if Rx > Ry\n# Rd <- Rx;\n# else\n# Rd <- Ry;\n# Syntax: max Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1100 0100 dddd\n\n:MAX erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xc4 & erd0\n{\n rxgt:4 = zext(RX9A s> RY0A);\n rxle:4 = zext(RX9A s<= RY0A);\n erd0 = RX9A * rxgt + RY0A * rxle;\n}\n\n:MAX erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xc4 & erd0 & erd0=0xf\n{\n rxgt:4 = zext(RX9A s> RY0A);\n rxle:4 = zext(RX9A s<= RY0A);\n PC = RX9A * rxgt + RY0A * rxle;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# MIN - Return Minimum Value\n# I. {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MIN Format I\n# Operation: if Rx < Ry\n# Rd <- Rx;\n# else\n# Rd <- Ry;\n# Syntax: min Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1101 0100 dddd\n\n:MIN erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xd4 & erd0\n{\n rxlt:4 = zext(RX9A s< RY0A);\n rxge:4 = zext(RX9A s>= RY0A);\n erd0 = RX9A * rxlt + RY0A * rxge;\n}\n\n:MIN erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xd4 & erd0 & erd0=0xf\n{\n rxlt:4 = zext(RX9A s< RY0A);\n rxge:4 = zext(RX9A s>= RY0A);\n PC = RX9A * rxlt + RY0A * rxge;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# NEG - Compare Word\n# I. {d, s} -> {0, 1, ..., 15}\n# II. d -> {0, 1, ..., 15}\n# imm -> {-32, -31, ..., 31}\n# III. d -> {0, 1, ..., 15}\n# imm -> {-1048576, -1048575, ..., 1048575}\n#---------------------------------------------------------------------\n\n# NEG Format I\n# Operation: Rd <- 0 - Rd\n# Syntax: neg Rd\n# 0101 1100 0011 dddd\n\n:NEG rd0 is op4_12=0x5c3 & rd0 {\n save:4 = rd0;\n rd0 = -rd0;\n subflags(0, save, rd0);\n}\n\n:NEG rd0 is op4_12=0x5c3 & rd0 & rd0=0xf {\n\t\ttmp:4 = inst_start;\n PC = -tmp;\n subflags(0, tmp, PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# RSUB - Reverse Subtract\n# I. {d, s} -> {0, 1, ..., 15}\n# II. {d, s} -> {0, 1, ..., 15}\n# imm -> {-128, -127, ..., 127}\n#---------------------------------------------------------------------\n\n# RSUB Format I\n# Operation: Rd <- Rs - Rd\n# Syntax: rsub Rd, Rs\n# 000s sss0 0010 dddd\n\n:RSUB rd0, RS9A is op13_3=0x0 & op4_5=2 & rd0 & RS9A {\n save:4 = rd0;\n rd0 = RS9A - rd0;\n subflags(RS9A, save, rd0);\n}\n\n:RSUB rd0, RS9A is op13_3=0x0 & op4_5=2 & rd0 & RS9A & rd0=0xf {\n PC = RS9A - inst_start;\n subflags(RS9A, inst_start, PC);\n goto [PC];\n}\n\n# RSUB Format II\n# Operation: Rd <- SE(imm8) - Rs\n# Syntax: rsub Rd, Rs, imm\n# 111s sss0 0000 dddd 0001 0001 iiii iiii\n\n:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A;\n eop12_4=1 & eop8_4=1 & simm0_8\n{\n save:4 = simm0_8;\n tmp:4 = RS9A;\n rd0 = save - RS9A;\n subflags(save, tmp, rd0);\n}\n\n:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A & rd0=0xf;\n eop12_4=1 & eop8_4=1 & simm0_8\n{\n save:4 = simm0_8;\n tmp:4 = RS9A;\n PC = save - RS9A;\n subflags(save, tmp, PC);\n goto [PC];\n}\n\n# RSUB Format II\n# Operation: Rd <- SE(imm8) - Rs\n# Syntax: rsub Rd, Rs, imm\n# 111s sss0 0000 dddd 0001 0001 iiii iiii\n#Handles Special Case where Immediate = -0x1 and treat it as a ~ (negate)\n:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A;\n eop12_4=1 & eop8_4=1 & simm0_8 & imm0_8=0xff\n{\n rd0 = ~RS9A;\n subflags(-1:4, RS9A, rd0);\n}\n\n:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A & rd0=0xf;\n eop12_4=1 & eop8_4=1 & simm0_8 & imm0_8=0xff\n{\n PC = ~RS9A;\n subflags(-1:4, RS9A, PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# RSUB{cond4} - Conditional Move Register\n# I. d -> {0, 1, ..., 15}\n# cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}\n# imm -> {-128, -127, ..., 127}\n#---------------------------------------------------------------------\n\n# RSUB{cond4} Format I\n# Operation: if (cond4)\n# Rd <- SE(imm8) - Rd\n# Syntax: rsub{cond4} Rd, imm\n# 1111 1011 1011 dddd 0000 cccc iiii iiii\n\n:RSUB^{ECOND_8_4} rd0, simm0_8 is op4_12=0xfbb & rd0 ; eop12_4=0 & simm0_8 & ECOND_8_4\n{\n build ECOND_8_4;\n rd0 = simm0_8 - rd0;\n}\n\n:RSUB^{ECOND_8_4} rd0, simm0_8 is op4_12=0xfbb & rd0 & rd0=0xf; eop12_4=0 & simm0_8 & ECOND_8_4\n{\n build ECOND_8_4;\n PC = simm0_8 - inst_start;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# SBC - Subtract with Carry\n# I. {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SBC Format I\n# Operation: Rd <- Rx - Ry - C\n# Syntax: sbc Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0001 0100 dddd\n\n:SBC erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0x14 & erd0\n{\n\t\ttmpx:4 = RX9A;\n\t\ttmpy:4 = RY0A;\n erd0 = RX9A - RY0A - zext(C);\n cpcflags(tmpx, tmpy, erd0);\n}\n\n:SBC erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0x14 & erd0 & erd0=0xf\n{\n\t\ttmpx:4 = RX9A;\n\t\ttmpy:4 = RY0A;\n PC = RX9A - RY0A - zext(C);\n cpcflags(tmpx, tmpy, PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# SCR - Subtract Carry from Register\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SCR Format I\n# Operation: Rd <- Rd - C\n# Syntax: scr Rd\n# 0101 1100 0001 dddd\n\n:SCR rd0 is op4_12=0x5c1 & rd0\n{\n save:4 = rd0;\n rd0 = rd0 - zext(C);\n\n V = (save s< 0) && (rd0 s>= 0);\n N = rd0 s< 0;\n Z = (rd0 == 0) && Z;\n C = (save s>= 0) && (rd0 s< 0);\n CZNVTOSR();\n}\n\n:SCR rd0 is op4_12=0x5c1 & rd0 & rd0=0xf\n{\n\t\ttmp:4 = inst_start;\n PC = tmp - zext(C);\n\n V = (tmp s< 0) && (PC s>= 0);\n N = PC s< 0;\n Z = (PC == 0) && Z;\n C = (tmp s>= 0) && (PC s< 0);\n CZNVTOSR();\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# SUB - Subtract (without Carry)\n#---------------------------------------------------------------------\n# SUB Format I\n# 000s sss0 0001 dddd\n\n:SUB rd0, RS9A is op13_3=0 & op4_5=1 & rd0 & RS9A {\n save:4 = rd0;\n tmp:4 = RS9A;\n rd0 = rd0 - RS9A;\n subflags(save, tmp, rd0);\n}\n\n:SUB rd0, RS9A is op13_3=0 & op4_5=1 & rd0 & RS9A & rd0=0xf {\n tmp:4 = RS9A;\n PC = inst_start - RS9A;\n subflags(inst_start, tmp, rd0);\n goto [PC];\n}\n\n# SUB Format II\n# 111x xxx0 0000 yyyy 0000 0001 00tt dddd\n\n:SUB erd0, RX9A, RY0A^\" << \" shift4_2 is op13_3=7 & op4_5=0 & RY0A & RX9A;\n eop6_10=4 & shift4_2 & erd0 {\n save:4 = RX9A;\n val:4 = RY0A << shift4_2;\n erd0 = RX9A - val;\n subflags(save, val, erd0);\n}\n\n:SUB erd0, RX9A, RY0A^\" << \" shift4_2 is op13_3=7 & op4_5=0 & RY0A & RX9A;\n eop6_10=4 & shift4_2 & erd0 & erd0=0xf {\n save:4 = RX9A;\n val:4 = RY0A << shift4_2;\n PC = RX9A - val;\n subflags(save, val, PC);\n goto [PC];\n}\n\n# SUB Format III\n# 0010 iiii iiii dddd\n\n:SUB rd0, imm is op13_3=0x1 & op12_1=0 & imm4_8 & rd0 & b003=0xd\n [ imm = imm4_8 << 2; ]\n{\n save:4 = rd0;\n rd0 = rd0 - imm;\n subflags(save, imm, rd0);\n}\n\n:SUB rd0, imm4_8 is op13_3=0x1 & op12_1=0 & imm4_8 & rd0 {\n save:4 = rd0;\n rd0 = rd0 - imm4_8;\n subflags(save, imm4_8, rd0);\n}\n\n:SUB rd0, imm4_8 is op13_3=0x1 & op12_1=0 & imm4_8 & rd0 & rd0=0xf {\n\t\ttmp:4 = inst_start;\n PC = tmp - imm4_8;\n subflags(tmp, imm4_8, PC);\n goto [PC];\n}\n\n# SUB Format IV\n# 111i iii0 001i dddd iiii iiii iiii iiii\n\n:SUB rd0, imm is op13_3=0x7 & op5_4=0x1 & imm9_4 & imm4_1 & rd0; imm16\n [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ]\n{\n save:4 = rd0;\n rd0 = rd0 - imm;\n subflags(save, imm, rd0);\n}\n\n:SUB rd0, imm is op13_3=0x7 & op5_4=0x1 & imm9_4 & imm4_1 & rd0 & rd0=0xf; imm16\n [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ]\n{\n\t\ttmp:4 = inst_start;\n PC = tmp - imm;\n subflags(tmp, imm, PC);\n goto [PC];\n}\n\n# SUB Format V\n# 111s sss0 1100 dddd iiii iiii iiii iiii\n\n:SUB rd0, RS9A, simm16 is op13_3=0x7 & op4_5=0xc & RS9A & rd0; simm16\n{\n\t\tsave:4 = RS9A;\n rd0 = RS9A - simm16;\n subflags(save, simm16, rd0);\n}\n\n:SUB rd0, RS9A, simm16 is op13_3=0x7 & op4_5=0xc & RS9A & rd0 & rd0=0xf; simm16\n{\n\t\tsave:4 = RS9A;\n PC = RS9A - simm16;\n subflags(save, simm16, PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# SUB{cond4} - Conditional Subtract\n# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} \n# d -> {0, 1, ..., 15}\n# imm -> {-128, -127, ..., 127}\n# II. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} \n# {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SUB{cond4} Format I\n# Operation: if(cond4) then\n# Rd <- Rd - imm8\n# Update flags if opcode[f] field is set\n# Syntax: sub{f}{cond4} Rd, imm\n# 1111 01f1 1011 dddd 0000 cccc iiii iiii\n\nF: \"{F}\" is b09=1 & rd0; simm0_8 {\n pre:4 = rd0 + simm0_8;\n subflags(pre, simm0_8, rd0);\n}\nF: is b09=0 & rd0; simm0_8 { }\n\n:SUB^F^{ECOND_8_4} rd0, simm0_8 is (op10_6=0x3d & op4_5=0x1b & rd0 ;\n eop12_4=0 & simm0_8 & ECOND_8_4) & F\n{\n build ECOND_8_4;\n rd0 = rd0 - simm0_8;\n build F;\n}\n\n:SUB^F^{ECOND_8_4} rd0, simm0_8 is (op10_6=0x3d & op4_5=0x1b & rd0 & rd0=0xf;\n eop12_4=0 & simm0_8 & ECOND_8_4) & F\n{\n build ECOND_8_4;\n PC = inst_start - simm0_8;\n build F;\n goto [PC];\n}\n\n# SUB{cond4} Format II\n# Operation: if(cond4) then\n# Rd <- Rx - Ry\n# Syntax: sub{cond4} Rd, Rx, Ry\n# 111x xxx1 1101 yyyy 1110 cccc 0001 dddd\n\n:SUB^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=1 & ECOND_8_4 & erd0)\n{\n build ECOND_8_4;\n erd0 = RX9A - RY0A;\n}\n\n:SUB^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=1 & ECOND_8_4 & erd0 & erd0=0xf)\n{\n build ECOND_8_4;\n PC = RX9A - RY0A;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# TNBZ - Test if No Byte is Equal to Zero\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# TNBZ Format I\n# Operation: if (Rd[31:24] == 0 |\n# Rd[23:16] == 0 |\n# Rd[23:16] == 0 |\n# Rd[23:16] == 0)\n# Z <- 1;\n# else\n# Z <- 0;\n# Syntax: tnbz Rd\n# 0101 1100 1110 dddd\n\n:TNBZ RD0A is op4_12=0x5ce & RD0A\n{\n Z = ((RD0A & 0xff000000) == 0 ||\n (RD0A & 0x00ff0000) == 0 ||\n (RD0A & 0x0000ff00) == 0 ||\n (RD0A & 0x000000ff) == 0);\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_autogen.sinc", "content": "define token gen_instr1(16)\n g_op13_3 = (13,15)\n g_op12_4 = (12,15)\n g_regsel11_1 = (11,11)\n g_op11_5 = (11,15)\n g_op10_6 = (10,15)\n g_regsel10_1 = (10,10)\n g_op9_7 = (9,15)\n g_rx9_4 = (9,12)\n g_opcode9_2 = (9,10)\n g_rs9_4 = (9,12)\n g_regsel9_1 = (9,9)\n g_offset9_4 = (9,12)\n g_disp9_4 = (9,12)\n g_rp9_4 = (9,12)\n g_update9_1 = (9,9)\n g_rb9_4 = (9,12)\n g_imm9_4 = (9,12)\n g_rd9_4 = (9,12)\n g_shift9_4 = (9,12)\n g_op8_1 = (8,8)\n g_op8_8 = (8,15)\n g_regsel8_1 = (8,8)\n g_op7_9 = (7,15)\n g_op7_2 = (7,8)\n g_regsel7_1 = (7,7)\n g_regsel6_1 = (6,6)\n g_regsel5_1 = (5,5)\n g_op5_4 = (5,8)\n g_imm4_1 = (4,4)\n g_disp4_5 = (4,8)\n g_imm4_6 = (4,9)\n g_shift4_1 = (4,4)\n g_imm4_8 = (4,11)\n g_disp4_1 = (4,4)\n g_offset4_1 = (4,4)\n g_disp4_4 = (4,7)\n g_op4_12 = (4,15)\n g_disp4_8 = (4,11)\n g_disp4_3 = (4,6)\n g_regsel4_1 = (4,4)\n g_imm4_3 = (4,6)\n g_op4_5 = (4,8)\n g_offset4_5 = (4,8)\n g_cond4_4 = (4,7)\n g_disp4_7 = (4,10)\n g_op3_1 = (3,3)\n g_op3_6 = (3,8)\n g_returnflag3_1 = (3,3)\n g_op2_2 = (2,3)\n g_rd1_3 = (1,3)\n g_rs1_3 = (1,3)\n g_ri0_4 = (0,3)\n g_cond0_4 = (0,3)\n g_shift0_4 = (0,3)\n g_op0_16 = (0,15)\n g_op0_9 = (0,8)\n g_op0_1 = (0,0)\n g_offset0_4 = (0,3)\n g_rs0_4 = (0,3)\n g_cond0_3 = (0,2)\n g_op0_3 = (0,2)\n g_opcode0_4 = (0,3)\n g_rd0_4 = (0,3)\n g_shift0_3 = (0,2)\n g_rp0_4 = (0,3)\n g_ry0_4 = (0,3)\n g_disp0_2 = (0,1)\n g_op0_4 = (0,3)\n;\ndefine token gen_instr2(16)\n eg_regsel15_1 = (15,15)\n eg_offset15_1 = (15,15)\n eg_regsel14_1 = (14,14)\n eg_op14_2 = (14,15)\n eg_op13_3 = (13,15)\n eg_xpart13_1 = (13,13)\n eg_cop13_3 = (13,15)\n eg_regsel13_1 = (13,13)\n eg_disp12_4 = (12,15)\n eg_op12_4 = (12,15)\n eg_regsel12_1 = (12,12)\n eg_op12_1 = (12,12)\n eg_update12_1 = (12,12)\n eg_ypart12_1 = (12,12)\n eg_cond12_4 = (12,15)\n eg_opcode12_1 = (12,12)\n eg_opcode11_5 = (11,15)\n eg_regsel11_1 = (11,11)\n eg_regsel10_1 = (10,10)\n eg_op10_6 = (10,15)\n eg_regsel9_1 = (9,9)\n eg_op9_7 = (9,15)\n eg_rd9_3 = (9,11)\n eg_rs9_3 = (9,11)\n eg_op9_3 = (9,11)\n eg_op8_1 = (8,8)\n eg_op8_4 = (8,11)\n eg_rd8_4 = (8,11)\n eg_op8_8 = (8,15)\n eg_cond8_4 = (8,11)\n eg_ri8_4 = (8,11)\n eg_regsel8_1 = (8,8)\n eg_rs8_4 = (8,11)\n eg_regsel7_1 = (7,7)\n eg_op6_3 = (6,8)\n eg_regsel6_1 = (6,6)\n eg_op6_2 = (6,7)\n eg_op6_10 = (6,15)\n eg_op5_11 = (5,15)\n eg_regsel5_1 = (5,5)\n eg_offset5_5 = (5,9)\n eg_xpart5_1 = (5,5)\n eg_regsel4_1 = (4,4)\n eg_rx4_4 = (4,7)\n eg_disp4_8 = (4,11)\n eg_ypart4_1 = (4,4)\n eg_shift4_5 = (4,8)\n eg_cond4_4 = (4,7)\n eg_returnflag4_1 = (4,4)\n eg_op4_12 = (4,15)\n eg_op4_4 = (4,7)\n eg_shift4_2 = (4,5)\n eg_regsel3_1 = (3,3)\n eg_regsel2_1 = (2,2)\n eg_regsel1_1 = (1,1)\n eg_ri0_4 = (0,3)\n eg_opcode0_8 = (0,7)\n eg_rd0_4 = (0,3)\n eg_imm0_8 = (0,7)\n eg_shift0_5 = (0,4)\n eg_regsel0_1 = (0,0)\n eg_disp0_16 = (0,15)\n eg_disp0_12 = (0,11)\n eg_disp0_8 = (0,7)\n eg_bits0_5 = (0,4)\n eg_disp0_9 = (0,8)\n eg_imm0_15 = (0,14)\n eg_rs0_4 = (0,3)\n eg_rb0_4 = (0,3)\n eg_offset0_5 = (0,4)\n eg_op0_8 = (0,7)\n eg_imm0_16 = (0,15)\n eg_op0_9 = (0,8)\n eg_ry0_4 = (0,3)\n eg_op0_16 = (0,15)\n eg_dbgregaddr0_8 = (0,7)\n eg_disp0_11 = (0,10)\n eg_rp0_4 = (0,3)\n eg_op0_4 = (0,3)\n;\n#:ABS g_rd0_4 is g_op4_12=0x5c4 & g_rd0_4 unimpl\n#:ACALL g_disp4_8 is g_op12_4=0xd & g_disp4_8 & g_op0_4=0x0 unimpl\n#:ACR g_rd0_4 is g_op4_12=0x5c0 & g_rd0_4 unimpl\n#:ADC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x4 & eg_rd0_4 unimpl\n#:ADD g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 unimpl\n#:ADD g_rx9_4, g_ry0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x0 & eg_shift4_2 & eg_rd0_4 unimpl\n#:ADD_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x0 & eg_rd0_4 unimpl\n#:ADDABS g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xe4 & eg_rd0_4 unimpl\n#:ADDHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x38 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:AND g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x6 & g_rd0_4 unimpl\n#:AND g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x0 & eg_shift4_5 & eg_rd0_4 unimpl\n#:AND g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x1 & eg_shift4_5 & eg_rd0_4 unimpl\n#:AND_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x2 & eg_rd0_4 unimpl\n#:ANDH g_update9_1, g_rd0_4, eg_imm0_16 is g_op10_6=0x39 & g_update9_1 & g_op4_5=0x1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:ANDL g_update9_1, g_rd0_4, eg_imm0_16 is g_op10_6=0x38 & g_update9_1 & g_op4_5=0x1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:ANDN g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x8 & g_rd0_4 unimpl\n#:ASR g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x84 & eg_rd0_4 unimpl\n#:ASR g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xa & g_shift4_1 & g_rd0_4 unimpl\n#:ASR g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xa0 & eg_shift0_5 unimpl\n#:BFEXTS g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x2c & eg_offset5_5 & eg_bits0_5 unimpl\n#:BFEXTU g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x30 & eg_offset5_5 & eg_bits0_5 unimpl\n#:BFINS g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x34 & eg_offset5_5 & eg_bits0_5 unimpl\n#:BLD g_rd0_4, eg_offset0_5 is g_op4_12=0xedb & g_rd0_4 ; eg_op5_11=0x0 & eg_offset0_5 unimpl\n#:BR_COND g_disp4_8, g_cond0_3 is g_op12_4=0xc & g_disp4_8 & g_op3_1=0x0 & g_cond0_3 unimpl\n#:BR_COND g_disp9_4, g_disp4_1, g_cond0_4, eg_disp0_16 is g_op13_3=0x7 & g_disp9_4 & g_op5_4=0x4 & g_disp4_1 & g_cond0_4 ; eg_disp0_16 unimpl\n#:BREAKPOINT is g_op0_16=0xd673 unimpl\n#:BREV g_rd0_4 is g_op4_12=0x5c9 & g_rd0_4 unimpl\n#:BST g_rd0_4, eg_offset0_5 is g_op4_12=0xefb & g_rd0_4 ; eg_op5_11=0x0 & eg_offset0_5 unimpl\n#:CACHE g_rp0_4, eg_opcode11_5, eg_disp0_11 is g_op4_12=0xf41 & g_rp0_4 ; eg_opcode11_5 & eg_disp0_11 unimpl\n#:CASTS.H g_rd0_4 is g_op4_12=0x5c8 & g_rd0_4 unimpl\n#:CASTS.B g_rd0_4 is g_op4_12=0x5c6 & g_rd0_4 unimpl\n#:CASTU.H g_rd0_4 is g_op4_12=0x5c7 & g_rd0_4 unimpl\n#:CASTU.B g_rd0_4 is g_op4_12=0x5c5 & g_rd0_4 unimpl\n#:CBR g_offset9_4, g_offset4_1, g_rd0_4 is g_op13_3=0x5 & g_offset9_4 & g_op5_4=0xe & g_offset4_1 & g_rd0_4 unimpl\n#:CLZ g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1200 unimpl\n#:COM g_rd0_4 is g_op4_12=0x5cd & g_rd0_4 unimpl\n#:COP g_opcode9_2, g_opcode0_4, eg_cop13_3, eg_opcode12_1, eg_rd8_4, eg_rx4_4, eg_ry0_4 is g_op11_5=0x1c & g_opcode9_2 & g_op4_5=0x1a & g_opcode0_4 ; eg_cop13_3 & eg_opcode12_1 & eg_rd8_4 & eg_rx4_4 & eg_ry0_4 unimpl\n#:CP.B g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1800 unimpl\n#:CP.H g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1900 unimpl\n#:CP.W g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x3 & g_rd0_4 unimpl\n#:CP.W g_imm4_6, g_rd0_4 is g_op10_6=0x16 & g_imm4_6 & g_rd0_4 unimpl\n#:CP.W g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x2 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:CPC g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1300 unimpl\n#:CPC g_rd0_4 is g_op4_12=0x5c2 & g_rd0_4 unimpl\n#:CSRF g_offset4_5 is g_op9_7=0x6a & g_offset4_5 & g_op0_4=0x3 unimpl\n#:CSRFCZ g_offset4_5 is g_op9_7=0x68 & g_offset4_5 & g_op0_4=0x3 unimpl\n#:DIVS g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc0 & eg_rd0_4 unimpl\n#:DIVU g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xd0 & eg_rd0_4 unimpl\n#:EOR g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x5 & g_rd0_4 unimpl\n#:EOR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x10 & eg_shift4_5 & eg_rd0_4 unimpl\n#:EOR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x11 & eg_shift4_5 & eg_rd0_4 unimpl\n#:EOR_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x4 & eg_rd0_4 unimpl\n#:EORH g_rd0_4, eg_imm0_16 is g_op4_12=0xee1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:EORL g_rd0_4, eg_imm0_16 is g_op4_12=0xec1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:FRS is g_op0_16=0xd743 unimpl\n#:ICALL g_rd0_4 is g_op4_12=0x5d1 & g_rd0_4 unimpl\n#:INCJOSP g_imm4_3 is g_op7_9=0x1ad & g_imm4_3 & g_op0_4=0x3 unimpl\n#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x10 & g_rd1_3 & g_op0_1=0x1 unimpl\n#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x11 & g_rd1_3 & g_op0_1=0x0 unimpl\n#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x10 & g_rd1_3 & g_op0_1=0x0 unimpl\n#:LD.D g_rp9_4, g_rd1_3, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xe & g_rd1_3 & g_op0_1=0x0 ; eg_disp0_16 unimpl\n#:LD.D g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x8 & eg_shift4_2 & eg_rd0_4 unimpl\n#:LD.SB g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x12 & g_rd0_4 ; eg_disp0_16 unimpl\n#:LD.SB g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x18 & eg_shift4_2 & eg_rd0_4 unimpl\n#:LD.SB_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x3 & eg_disp0_9 unimpl\n#:LD.UB g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x13 & g_rd0_4 unimpl\n#:LD.UB g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x17 & g_rd0_4 unimpl\n#:LD.UB g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op7_2=0x3 & g_disp4_3 & g_rd0_4 unimpl\n#:LD.UB g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x13 & g_rd0_4 ; eg_disp0_16 unimpl\n#:LD.UB g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x1c & eg_shift4_2 & eg_rd0_4 unimpl\n#:LD.UB_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x4 & eg_disp0_9 unimpl\n#:LD.SH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x11 & g_rd0_4 unimpl\n#:LD.SH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x15 & g_rd0_4 unimpl\n#:LD.SH g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x4 & g_rp9_4 & g_op7_2=0x0 & g_disp4_3 & g_rd0_4 unimpl\n#:LD.SH g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x10 & g_rd0_4 ; eg_disp0_16 unimpl\n#:LD.SH g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x10 & eg_shift4_2 & eg_rd0_4 unimpl\n#:LD.SH_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x1 & eg_disp0_9 unimpl\n#:LD.UH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x12 & g_rd0_4 unimpl\n#:LD.UH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x16 & g_rd0_4 unimpl\n#:LD.UH g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x4 & g_rp9_4 & g_op7_2=0x1 & g_disp4_3 & g_rd0_4 unimpl\n#:LD.UH g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x11 & g_rd0_4 ; eg_disp0_16 unimpl\n#:LD.UH g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x14 & eg_shift4_2 & eg_rd0_4 unimpl\n#:LD.UH_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x2 & eg_disp0_9 unimpl\n#:LD.W g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x10 & g_rd0_4 unimpl\n#:LD.W g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x14 & g_rd0_4 unimpl\n#:LD.W g_rp9_4, g_disp4_5, g_rd0_4 is g_op13_3=0x3 & g_rp9_4 & g_disp4_5 & g_rd0_4 unimpl\n#:LD.W g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xf & g_rd0_4 ; eg_disp0_16 unimpl\n#:LD.W g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0xc & eg_shift4_2 & eg_rd0_4 unimpl\n#:LD.W g_rb9_4, g_ri0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x3e & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:LD.W_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x0 & eg_disp0_9 unimpl\n#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3, eg_disp0_8 is g_op4_12=0xe9a & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl\n#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd9_3 & eg_op0_9=0x50 unimpl\n#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd9_3 & eg_op6_3=0x1 & eg_shift4_2 & eg_ri0_4 unimpl\n#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4, eg_disp0_8 is g_op4_12=0xe9a & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_disp0_8 unimpl\n#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_op0_8=0x40 unimpl\n#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd8_4 & eg_op6_2=0x0 & eg_shift4_2 & eg_ri0_4 unimpl\n#:LDC0.D g_rp0_4, eg_disp12_4, eg_rd9_3, eg_disp0_8 is g_op4_12=0xf3a & g_rp0_4 ; eg_disp12_4 & eg_rd9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl\n#:LDC0.W g_rp0_4, eg_disp12_4, eg_rd8_4, eg_disp0_8 is g_op4_12=0xf1a & g_rp0_4 ; eg_disp12_4 & eg_rd8_4 & eg_disp0_8 unimpl\n#:LDCM.D g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x4 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:LDCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:LDCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:LDDPC g_disp4_7, g_rd0_4 is g_op11_5=0x9 & g_disp4_7 & g_rd0_4 unimpl\n#:LDDSP g_disp4_7, g_rd0_4 is g_op11_5=0x8 & g_disp4_7 & g_rd0_4 unimpl\n#:LDINS.B g_rp9_4, g_rd0_4, eg_xpart13_1, eg_ypart12_1, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op14_2=0x1 & eg_xpart13_1 & eg_ypart12_1 & eg_disp0_12 unimpl\n#:LDINS.H g_rp9_4, g_rd0_4, eg_ypart12_1, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op13_3=0x0 & eg_ypart12_1 & eg_disp0_12 unimpl\n#:LDM g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x38 & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:LDMTS g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x39 & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:LDSWP.SH g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x2 & eg_disp0_12 unimpl\n#:LDSWP.UH g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x3 & eg_disp0_12 unimpl\n#:LDSWP.W g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x8 & eg_disp0_12 unimpl\n#:LSL g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x94 & eg_rd0_4 unimpl\n#:LSL g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xb & g_shift4_1 & g_rd0_4 unimpl\n#:LSL g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xa8 & eg_shift0_5 unimpl\n#:LSR g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xa4 & eg_rd0_4 unimpl\n#:LSR g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xc & g_shift4_1 & g_rd0_4 unimpl\n#:LSR g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xb0 & eg_shift0_5 unimpl\n#:MAC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x34 & eg_rd0_4 unimpl\n#:MACHH.D g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x16 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MACHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x12 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MACS.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x54 & eg_rd0_4 unimpl\n#:MACSATHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x1a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MACU.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x74 & eg_rd0_4 unimpl\n#:MACWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x64 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MAX g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc4 & eg_rd0_4 unimpl\n#:MCALL g_rp0_4, eg_disp0_16 is g_op4_12=0xf01 & g_rp0_4 ; eg_disp0_16 unimpl\n#:MEMC g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xf61 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl\n#:MEMS g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xf81 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl\n#:MEMT g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xfa1 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl\n#:MFDR g_rd0_4, eg_dbgregaddr0_8 is g_op4_12=0xe5b & g_rd0_4 ; eg_op8_8=0x0 & eg_dbgregaddr0_8 unimpl\n#:MFSR g_rd0_4, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xe1b & g_rd0_4 ; eg_op8_8=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:MIN g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xd4 & eg_rd0_4 unimpl\n#:MOV g_imm4_8, g_rd0_4 is g_op12_4=0x3 & g_imm4_8 & g_rd0_4 unimpl\n#:MOV g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x3 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:MOV g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x9 & g_rd0_4 unimpl\n#:MOV_COND g_rs9_4, g_rd0_4, eg_cond4_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x17 & eg_cond4_4 & eg_op0_4=0x0 unimpl\n#:MOV_COND g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op4_12=0xf9b & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl\n#:MOVHI g_rd0_4, eg_imm0_16 is g_op4_12=0xfc1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:MTDR g_rs0_4, eg_dbgregaddr0_8 is g_op4_12=0xe7b & g_rs0_4 ; eg_op8_8=0x0 & eg_dbgregaddr0_8 unimpl\n#:MTSR g_rs0_4, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xe3b & g_rs0_4 ; eg_op8_8=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:MUL g_rs9_4, g_rd0_4 is g_op13_3=0x5 & g_rs9_4 & g_op4_5=0x13 & g_rd0_4 unimpl\n#:MUL g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24 & eg_rd0_4 unimpl\n#:MUL g_rs9_4, g_rd0_4, eg_imm0_8 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x10 & eg_imm0_8 unimpl\n#:MULHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x1e & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULNHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x6 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULNWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x14 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULS.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x44 & eg_rd0_4 unimpl\n#:MULSATHH.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x22 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULSATHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x26 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULSATRNDHH.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x2a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULSATRNDWH.W g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x5c & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULSATWH.W g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x74 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MULU.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x64 & eg_rd0_4 unimpl\n#:MULWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x6c & eg_ypart4_1 & eg_rd0_4 unimpl\n#:MUSFR g_rs0_4 is g_op4_12=0x5d3 & g_rs0_4 unimpl\n#:MUSTR g_rd0_4 is g_op4_12=0x5d2 & g_rd0_4 unimpl\n#:MVCR.D g_rd1_3, eg_cop13_3, eg_rs9_3 is g_op4_12=0xefa & g_rd1_3 & g_op0_1=0x0 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs9_3 & eg_op0_9=0x10 unimpl\n#:MVCR.W g_rd0_4, eg_cop13_3, eg_rs8_4 is g_op4_12=0xefa & g_rd0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_op0_8=0x0 unimpl\n#:MVRC.D g_rs1_3, eg_cop13_3, eg_rd9_3 is g_op4_12=0xefa & g_rs1_3 & g_op0_1=0x0 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd9_3 & eg_op0_9=0x30 unimpl\n#:MVRC.W g_rs0_4, eg_cop13_3, eg_rd8_4 is g_op4_12=0xefa & g_rs0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_op0_8=0x20 unimpl\n#:NEG g_rd0_4 is g_op4_12=0x5c3 & g_rd0_4 unimpl\n#:NOP is g_op0_16=0xd703 unimpl\n#:OR g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x4 & g_rd0_4 unimpl\n#:OR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x8 & eg_shift4_5 & eg_rd0_4 unimpl\n#:OR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x9 & eg_shift4_5 & eg_rd0_4 unimpl\n#:OR_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x3 & eg_rd0_4 unimpl\n#:ORH g_rd0_4, eg_imm0_16 is g_op4_12=0xea1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:ORL g_rd0_4, eg_imm0_16 is g_op4_12=0xe81 & g_rd0_4 ; eg_imm0_16 unimpl\n#:PABS.SB g_rs0_4, eg_rd0_4 is g_op4_12=0xe00 & g_rs0_4 ; eg_op4_12=0x23e & eg_rd0_4 unimpl\n#:PABS.SH g_rs0_4, eg_rd0_4 is g_op4_12=0xe00 & g_rs0_4 ; eg_op4_12=0x23f & eg_rd0_4 unimpl\n#:PACKSH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24c & eg_rd0_4 unimpl\n#:PACKSH.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24d & eg_rd0_4 unimpl\n#:PACKW.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x247 & eg_rd0_4 unimpl\n#:PADD.B g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x230 & eg_rd0_4 unimpl\n#:PADD.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x200 & eg_rd0_4 unimpl\n#:PADDH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x236 & eg_rd0_4 unimpl\n#:PADDH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20c & eg_rd0_4 unimpl\n#:PADDS.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x234 & eg_rd0_4 unimpl\n#:PADDS.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x232 & eg_rd0_4 unimpl\n#:PADDS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x208 & eg_rd0_4 unimpl\n#:PADDS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x204 & eg_rd0_4 unimpl\n#:PADDSUB.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x84 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PADDSUBH.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x8a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PADDSUBS.UH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x88 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PADDSUBS.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x86 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PADDX.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x202 & eg_rd0_4 unimpl\n#:PADDXH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20e & eg_rd0_4 unimpl\n#:PADDXS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20a & eg_rd0_4 unimpl\n#:PADDXS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x206 & eg_rd0_4 unimpl\n#:PASR.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x241 & eg_rd0_4 unimpl\n#:PASR.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x244 & eg_rd0_4 unimpl\n#:PAVG.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23c & eg_rd0_4 unimpl\n#:PAVG.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23d & eg_rd0_4 unimpl\n#:PLSL.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x242 & eg_rd0_4 unimpl\n#:PLSL.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x245 & eg_rd0_4 unimpl\n#:PLSR.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x243 & eg_rd0_4 unimpl\n#:PLSR.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x246 & eg_rd0_4 unimpl\n#:PMAX.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x238 & eg_rd0_4 unimpl\n#:PMAX.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x239 & eg_rd0_4 unimpl\n#:PMIN.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23a & eg_rd0_4 unimpl\n#:PMIN.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23b & eg_rd0_4 unimpl\n#:POPJC is g_op0_16=0xd713 unimpl\n#:POPM g_regsel11_1, g_regsel10_1, g_regsel9_1, g_regsel8_1, g_regsel7_1, g_regsel6_1, g_regsel5_1, g_regsel4_1, g_returnflag3_1 is g_op12_4=0xd & g_regsel11_1 & g_regsel10_1 & g_regsel9_1 & g_regsel8_1 & g_regsel7_1 & g_regsel6_1 & g_regsel5_1 & g_regsel4_1 & g_returnflag3_1 & g_op0_3=0x2 unimpl\n#:PREF g_rp0_4, eg_disp0_16 is g_op4_12=0xf21 & g_rp0_4 ; eg_disp0_16 unimpl\n#:PSAD g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x240 & eg_rd0_4 unimpl\n#:PSUB.B g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x231 & eg_rd0_4 unimpl\n#:PSUB.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x201 & eg_rd0_4 unimpl\n#:PSUBADD.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x85 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PSUBADDH.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x8b & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PSUBADDS.UH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x89 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PSUBADDS.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x87 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:PSUBH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x237 & eg_rd0_4 unimpl\n#:PSUBH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20d & eg_rd0_4 unimpl\n#:PSUBS.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x235 & eg_rd0_4 unimpl\n#:PSUBS.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x233 & eg_rd0_4 unimpl\n#:PSUBS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x209 & eg_rd0_4 unimpl\n#:PSUBS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x205 & eg_rd0_4 unimpl\n#:PSUBX.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x203 & eg_rd0_4 unimpl\n#:PSUBXH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20f & eg_rd0_4 unimpl\n#:PSUBXS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20b & eg_rd0_4 unimpl\n#:PSUBXS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x207 & eg_rd0_4 unimpl\n#:PUNPCKUB.H g_rs9_4, eg_returnflag4_1, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op0_9=0x0 ; eg_op5_11=0x124 & eg_returnflag4_1 & eg_rd0_4 unimpl\n#:PUNPCKSB.H g_rs9_4, eg_returnflag4_1, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op0_9=0x0 ; eg_op5_11=0x125 & eg_returnflag4_1 & eg_rd0_4 unimpl\n#:PUSHJC is g_op0_16=0xd723 unimpl\n#:PUSHM g_regsel11_1, g_regsel10_1, g_regsel9_1, g_regsel8_1, g_regsel7_1, g_regsel6_1, g_regsel5_1, g_regsel4_1 is g_op12_4=0xd & g_regsel11_1 & g_regsel10_1 & g_regsel9_1 & g_regsel8_1 & g_regsel7_1 & g_regsel6_1 & g_regsel5_1 & g_regsel4_1 & g_op0_4=0x1 unimpl\n#:RCALL g_disp4_8, g_disp0_2 is g_op12_4=0xc & g_disp4_8 & g_op2_2=0x3 & g_disp0_2 unimpl\n#:RCALL g_disp9_4, g_disp4_1, eg_disp0_16 is g_op13_3=0x7 & g_disp9_4 & g_op5_4=0x5 & g_disp4_1 & g_op0_4=0x0 ; eg_disp0_16 unimpl\n#:RET_COND g_cond4_4, g_rs0_4 is g_op8_8=0x5e & g_cond4_4 & g_rs0_4 unimpl\n#:RETD is g_op0_16=0xd623 unimpl\n#:RETE is g_op0_16=0xd603 unimpl\n#:RETJ is g_op0_16=0xd633 unimpl\n#:RETS is g_op0_16=0xd613 unimpl\n#:RJMP g_disp4_8, g_disp0_2 is g_op12_4=0xc & g_disp4_8 & g_op2_2=0x2 & g_disp0_2 unimpl\n#:ROL g_rd0_4 is g_op4_12=0x5cf & g_rd0_4 unimpl\n#:ROR g_rd0_4 is g_op4_12=0x5d0 & g_rd0_4 unimpl\n#:RSUB g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x2 & g_rd0_4 unimpl\n#:RSUB g_rs9_4, g_rd0_4, eg_imm0_8 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x11 & eg_imm0_8 unimpl\n#:RSUB_COND g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op4_12=0xfbb & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl\n#:SATADD.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x2c & eg_rd0_4 unimpl\n#:SATADD.W g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc & eg_rd0_4 unimpl\n#:SATRNDS g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf3b & g_rd0_4 ; eg_op10_6=0x0 & eg_offset5_5 & eg_shift0_5 unimpl\n#:SATRNDU g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf3b & g_rd0_4 ; eg_op10_6=0x1 & eg_offset5_5 & eg_shift0_5 unimpl\n#:SATS g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf1b & g_rd0_4 ; eg_op10_6=0x0 & eg_offset5_5 & eg_shift0_5 unimpl\n#:SATSUB.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x3c & eg_rd0_4 unimpl\n#:SATSUB.W g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x1c & eg_rd0_4 unimpl\n#:SATSUB.W g_rs9_4, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0xd & g_rd0_4 ; eg_imm0_16 unimpl\n#:SATU g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf1b & g_rd0_4 ; eg_op10_6=0x1 & eg_offset5_5 & eg_shift0_5 unimpl\n#:SBC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x14 & eg_rd0_4 unimpl\n#:SBR g_offset9_4, g_offset4_1, g_rd0_4 is g_op13_3=0x5 & g_offset9_4 & g_op5_4=0xd & g_offset4_1 & g_rd0_4 unimpl\n#:SCALL is g_op0_16=0xd733 unimpl\n#:SCR g_rd0_4 is g_op4_12=0x5c1 & g_rd0_4 unimpl\n#:SLEEP eg_opcode0_8 is g_op0_16=0xe9b0 ; eg_op8_8=0x0 & eg_opcode0_8 unimpl\n#:SR_COND g_cond4_4, g_rd0_4 is g_op8_8=0x5f & g_cond4_4 & g_rd0_4 unimpl\n#:SSRF g_offset4_5 is g_op9_7=0x69 & g_offset4_5 & g_op0_4=0x3 unimpl\n#:ST.B g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xc & g_rs0_4 unimpl\n#:ST.B g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xf & g_rs0_4 unimpl\n#:ST.B g_rp9_4, g_disp4_3, g_rs0_4 is g_op13_3=0x5 & g_rp9_4 & g_op7_2=0x1 & g_disp4_3 & g_rs0_4 unimpl\n#:ST.B g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x16 & g_rs0_4 ; eg_disp0_16 unimpl\n#:ST.B g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x2c & eg_shift4_2 & eg_rs0_4 unimpl\n#:ST.B_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x7 & eg_disp0_9 unimpl\n#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x12 & g_rs1_3 & g_op0_1=0x0 unimpl\n#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x12 & g_rs1_3 & g_op0_1=0x1 unimpl\n#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x11 & g_rs1_3 & g_op0_1=0x1 unimpl\n#:ST.D g_rp9_4, g_rs1_3, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xe & g_rs1_3 & g_op0_1=0x1 ; eg_disp0_16 unimpl\n#:ST.D g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x20 & eg_shift4_2 & eg_rs0_4 unimpl\n#:ST.H g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xb & g_rs0_4 unimpl\n#:ST.H g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xe & g_rs0_4 unimpl\n#:ST.H g_rp9_4, g_disp4_3, g_rs0_4 is g_op13_3=0x5 & g_rp9_4 & g_op7_2=0x0 & g_disp4_3 & g_rs0_4 unimpl\n#:ST.H g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x15 & g_rs0_4 ; eg_disp0_16 unimpl\n#:ST.H g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x28 & eg_shift4_2 & eg_rs0_4 unimpl\n#:ST.H_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x6 & eg_disp0_9 unimpl\n#:ST.W g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xa & g_rs0_4 unimpl\n#:ST.W g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xd & g_rs0_4 unimpl\n#:ST.W g_rp9_4, g_disp4_4, g_rs0_4 is g_op13_3=0x4 & g_rp9_4 & g_op8_1=0x1 & g_disp4_4 & g_rs0_4 unimpl\n#:ST.W g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x14 & g_rs0_4 ; eg_disp0_16 unimpl\n#:ST.W g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x24 & eg_shift4_2 & eg_rs0_4 unimpl\n#:ST.W_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x5 & eg_disp0_9 unimpl\n#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3, eg_disp0_8 is g_op4_12=0xeba & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl\n#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs9_3 & eg_op0_9=0x70 unimpl\n#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs9_3 & eg_op6_3=0x3 & eg_shift4_2 & eg_ri0_4 unimpl\n#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4, eg_disp0_8 is g_op4_12=0xeba & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_disp0_8 unimpl\n#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_op0_8=0x60 unimpl\n#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs8_4 & eg_op6_2=0x2 & eg_shift4_2 & eg_ri0_4 unimpl\n#:STC0.D g_rp0_4, eg_disp12_4, eg_rs9_3, eg_disp0_8 is g_op4_12=0xf7a & g_rp0_4 ; eg_disp12_4 & eg_rs9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl\n#:STC0.W g_rp0_4, eg_disp12_4, eg_rs8_4, eg_disp0_8 is g_op4_12=0xf5a & g_rp0_4 ; eg_disp12_4 & eg_rs8_4 & eg_disp0_8 unimpl\n#:STCM.D g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x5 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:STCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x3 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:STCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x2 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:STCOND g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x17 & g_rs0_4 ; eg_disp0_16 unimpl\n#:STDSP g_disp4_7, g_rs0_4 is g_op11_5=0xa & g_disp4_7 & g_rs0_4 unimpl\n#:STHH.W g_rx9_4, g_ry0_4, eg_xpart13_1, eg_ypart12_1, eg_disp4_8, eg_rp0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op14_2=0x3 & eg_xpart13_1 & eg_ypart12_1 & eg_disp4_8 & eg_rp0_4 unimpl\n#:STHH.W g_rx9_4, g_ry0_4, eg_xpart13_1, eg_ypart12_1, eg_ri8_4, eg_shift4_2, eg_rb0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op14_2=0x2 & eg_xpart13_1 & eg_ypart12_1 & eg_ri8_4 & eg_op6_2=0x0 & eg_shift4_2 & eg_rb0_4 unimpl\n#:STM g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x3a & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:STMTS g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x3b & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl\n#:STSWP.H g_rp9_4, g_rs0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op12_4=0x9 & eg_disp0_12 unimpl\n#:STSWP.W g_rp9_4, g_rs0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op12_4=0xa & eg_disp0_12 unimpl\n#:SUB g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x1 & g_rd0_4 unimpl\n#:SUB g_rx9_4, g_ry0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x4 & eg_shift4_2 & eg_rd0_4 unimpl\n#:SUB g_imm4_8, g_rd0_4 is g_op12_4=0x2 & g_imm4_8 & g_rd0_4 unimpl\n#:SUB g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x1 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl\n#:SUB g_rs9_4, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0xc & g_rd0_4 ; eg_imm0_16 unimpl\n#:SUB_F_COND g_update9_1, g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op10_6=0x3d & g_update9_1 & g_op4_5=0x1b & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl\n#:SUB_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x1 & eg_rd0_4 unimpl\n#:SUBHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x3c & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl\n#:SWAP.B g_rd0_4 is g_op4_12=0x5cb & g_rd0_4 unimpl\n#:SWAP.BH g_rd0_4 is g_op4_12=0x5cc & g_rd0_4 unimpl\n#:SWAP.H g_rd0_4 is g_op4_12=0x5ca & g_rd0_4 unimpl\n#:SYNC eg_opcode0_8 is g_op0_16=0xebb0 ; eg_op8_8=0x0 & eg_opcode0_8 unimpl\n#:TLBR is g_op0_16=0xd643 unimpl\n#:TLBS is g_op0_16=0xd653 unimpl\n#:TLBW is g_op0_16=0xd663 unimpl\n#:TNBZ g_rd0_4 is g_op4_12=0x5ce & g_rd0_4 unimpl\n#:TST g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x7 & g_rd0_4 unimpl\n#:XCHG g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xb4 & eg_rd0_4 unimpl\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_bit_operations.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.6 Bit Operations\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# BFEXTS - Bitfield extract and sign-extend\n# I. {d,s} -> {0, 1, ..., 15}\n# {bp5, w5} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# BFEXTS Format I\n# Operation: Rd <- SE(Rs[bp5+w5-1:bp5])\n# Syntax: bfexts Rd, Rs, bp5, w5\n# 111d ddd1 1101 ssss 1011 00ff fffw wwww\n\n:BFEXTS rd9, RS0A, eoff5_5, elen0_5 is op13_3=0x7 & rd9 & op4_5=0x1d & RS0A ;\n eop10_6=0x2c & eoff5_5 & elen0_5\n{\n shifted:4 = (RS0A >> eoff5_5);\n mask:4 = (0xffffffff >> (32 - elen0_5));\n isolated:4 = shifted & mask;\n \n # Technically, elen0_5 can be 0, but result is undefined\n # if that's the case so we're ok here.\n signmask:4 = (0xffffffff << (elen0_5 - 1));\n test:4 = zext((signmask & isolated) != 0);\n rd9 = (test * signmask) | isolated;\n NZSTATUS(rd9);\n C = rd9 s< 0;\n CZNVTOSR();\n}\n\n#---------------------------------------------------------------------\n# BFEXTU - Bitfield extract and zero-extend\n# I. {d,s} -> {0, 1, ..., 15}\n# {bp5, w5} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# BFEXTU Format I\n# Operation: Rd <- SE(Rs[bp5+w5-1:bp5])\n# Syntax: bfextu Rd, Rs, bp5, w5\n# 111d ddd1 1101 ssss 1011 00ff fffw wwww\n\n:BFEXTU rd9, RS0A, eoff5_5, elen0_5 is op13_3=0x7 & rd9 & op4_5=0x1d & RS0A ;\n eop10_6=0x30 & eoff5_5 & elen0_5\n{\n shifted:4 = (RS0A >> eoff5_5);\n mask:4 = (0xffffffff >> (32 - elen0_5));\n rd9 = shifted & mask;\n NZSTATUS(rd9);\n C = rd9 s< 0;\n CZNVTOSR();\n}\n\n#---------------------------------------------------------------------\n# BFINS - Bitfield insert\n# I. {d,s} -> {0, 1, ..., 15}\n# {bp5, w5} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# BFINS Format I\n# Operation: Rd[bp5+w5-1:bp5] <- Rs[w5-1:0]\n# Syntax: bfins Rd, Rs, bp5, w5\n# 111d ddd1 1101 ssss 1101 00ff fffw wwww\n\n:BFINS rd9, RS0A, eoff5_5, elen0_5 is op13_3=0x7 & rd9 & op4_5=0x1d & RS0A ;\n eop10_6=0x34 & eoff5_5 & elen0_5\n{\n lowmask:4 = (0xffffffff >> (32 - elen0_5));\n destmask:4 = ~(lowmask << eoff5_5);\n rd9 = (rd9 & destmask) | ((RS0A & lowmask) << elen0_5); \n NZSTATUS(rd9);\n C = rd9 s< 0;\n CZNVTOSR();\n}\n\n#---------------------------------------------------------------------\n# BLD - Bit load from register to C and Z\n# I. d -> {0, 1, ..., 15}\n# bp5 -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# BLD Format I\n# Operation: C <- Rd[bp5]\n# Z <- Rd[bp5]\n# Syntax: bld Rd, bp5\n# 1110 1101 1011 dddd 0000 0000 000f ffff\n\n:BLD rd0, eoff0_5 is op4_12=0xedb & rd0 ;\n eop5_11=0x0 & eoff0_5\n{\n tmp:4 = (rd0 & (1 << eoff0_5));\n test:1 = (tmp != 0);\n C = test;\n Z = test;\n CZNVTOSR();\n}\n\n#---------------------------------------------------------------------\n# BREV - Bit Reverse\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# BREV Format I\n# Operation: Rd[31:0] <- Rd[0:31]\n# Syntax: brev Rd\n# 0101 1100 1001 dddd\n\n# taken from http://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel\n# under the 32 bit word reverse\n\n:BREV rd0 is op4_12=0x5c9 & rd0\n{\n v:4 = rd0;\n v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1);\n v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2);\n v = ((v >> 4) & 0x0F0F0F0F) | ((v & 0x0F0F0F0F) << 4);\n v = ((v >> 8) & 0x00FF00FF) | ((v & 0x00FF00FF) << 8);\n v = (v >> 16) | (v << 16);\n rd0 = v;\n ZSTATUS(rd0);\n}\n\n#---------------------------------------------------------------------\n# BST - Copy C to register bit\n# I. d -> {0, 1, ..., 15}\n# bp5 -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# BST Format I\n# Operation: Rd[bp5] <- C\n# Syntax: bst Rd, bp5\n# 1110 1111 1011 dddd 0000 0000 000f ffff\n\n:BST rd0, eoff0_5 is op4_12=0xefb & rd0 ; eop5_11=0x0 & eoff0_5\n{\n destbit:4 = (1 << eoff0_5);\n cbool:4 = zext(C != 0);\n rd0 = (rd0 & ~destbit) | (cbool * destbit); \n}\n\n#---------------------------------------------------------------------\n# CASTS.{H,B} - Typecast to Signed Word\n# I, II. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# CASTS.H Format I\n# Operation: Rd[31:16] <- Rd[15]\n# Syntax: casts.h Rd\n# 0101 1100 1000 dddd\n\n:CASTS.H rd0 is op4_12=0x5c8 & rd0\n{\n rd0 = sext(rd0:2);\n}\n\n# CASTS.B Format II\n# Operation: Rd[31:8] <- Rd[7]\n# Syntax: casts.b Rd\n# 0101 1100 0110 dddd\n\n:CASTS.B rd0 is op4_12=0x5c6 & rd0\n{\n rd0 = sext(rd0:1); \n}\n\n#---------------------------------------------------------------------\n# CASTU.{H,B} - Typecast to Unsigned Word\n# I, II. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# CASTU.H Format I\n# Operation: Rd[31:16] <- 0\n# Syntax: castu.h Rd\n# 0101 1100 1000 dddd\n\n:CASTU.H rd0 is op4_12=0x5c7 & rd0\n{\n rd0 = zext(rd0:2);\n}\n\n# CASTU.B Format II\n# Operation: Rd[31:8] <- 0\n# Syntax: castu.b Rd\n# 0101 1100 0110 dddd\n\n:CASTU.B rd0 is op4_12=0x5c5 & rd0\n{\n rd0 = zext(rd0:1);\n}\n\n#---------------------------------------------------------------------\n# CBR - Clear Bit in Register\n# I. d -> {0, 1, ..., 15}\n# bp5 -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# CBR Format I\n# Operation: Rd[bp5] <- 0\n# Syntax: cbr Rd, bp5\n# 101f fff1 110f dddd\n\nCSBRH: off is bp9_4 & bp4_1\n[ off = (bp9_4 << 1) | bp4_1; ]\n{\n tmp:4 = off;\n export tmp;\n}\n\n:CBR rd0, CSBRH is op13_3=0x5 & op5_4=0xe & CSBRH & rd0\n{\n destbit:4 = (1 << CSBRH);\n rd0 = (rd0 & ~destbit);\n ZSTATUS(rd0); \n}\n\n#---------------------------------------------------------------------\n# CLZ - Count Leading Zeros\n# I. {d,s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# CLZ Format I\n# Operation: temp <- 32\n# for (i = 31; i >= 0; i--)\n# if (Rs[i] == 1) then\n# temp <- 31 - i;\n# break;\n# Rd <- temp;\n# Syntax: clz Rd, Rs\n# 111s sss0 0000 dddd 0001 0010 0000 0000\n\n:CLZ rd0, RS9A is op13_3=0x7 & op4_5=0x0 & rd0 & RS9A ; eop0_16=0x1200\n{\n rd0 = lzcount(RS9A);\n\n Z = (rd0 == 0);\n C = (rd0 == 32);\n CZNVTOSR();\n}\n\nMEMSH: val\t\t\t\t is simm0_15 [ val = simm0_15 << 2; ] {export *[const]:4 val; }\n:MEMC MEMSH, ctx_shift is op4_12=0xf61 & imm0_4 & ctx_shift; eb15 & MEMSH [ctx_shigh = imm0_4; ctx_slow = eb15;] {\n\ttmp:4 = 0x00000001 << ctx_shift;\n\ttmp = ~tmp;\n\ttmpa:4 = *[RAM]:4 MEMSH;\n\t*[RAM]:4 MEMSH = tmpa & tmp;\n}\n\n:MEMS MEMSH, ctx_shift\t is op4_12=0xf81 & imm0_4 & ctx_shift; eb15 & MEMSH [ctx_shigh = imm0_4; ctx_slow = eb15;] {\n\ttmp:4 = 0x00000001 << ctx_shift;\n\ttmpa:4 = *[RAM]:4 MEMSH;\n\t*[RAM]:4 MEMSH = tmpa & tmp;\n}\n\n:MEMT MEMSH, ctx_shift\t is op4_12=0xfa1 & imm0_4 & ctx_shift; eb15 & MEMSH [ctx_shigh = imm0_4; ctx_slow = eb15;] {\n\ttmp:4 = 0x00000001 << ctx_shift;\n\ttmpa:4 = *[RAM]:4 MEMSH;\n\t*[RAM]:4 MEMSH = tmpa ^ tmp;\n}\n\n#---------------------------------------------------------------------\n# SBR - Clear Bit in Register\n# I. d -> {0, 1, ..., 15}\n# bp5 -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# SBR Format I\n# Operation: Rd[bp5] <- 1\n# Syntax: sbr Rd, bp5\n# 101f fff1 101f dddd\n\n:SBR rd0, CSBRH is op13_3=0x5 & op5_4=0xd & CSBRH & rd0\n{\n destbit:4 = (1 << CSBRH);\n rd0 = (rd0 | destbit);\n Z = 0; \n CZNVTOSR(); \n}\n\n#---------------------------------------------------------------------\n# SWAP.B - Swap Bytes\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SWAP.B Format I\n# Operation: temp <- Rd\n# Rd[31:24] <- temp[7:0]\n# Rd[23:16] <- temp[15:8]\n# Rd[15:8] <- temp[23:16]\n# Rd[7:0] <- temp[31:24]\n# Syntax: swap.b Rd\n# 0101 1100 1011 dddd\n\n:SWAP.B rd0 is op4_12=0x5cb & rd0\n{\n temp:4 = rd0;\n rd0[24,8] = temp[0,8];\n rd0[16,8] = temp[8,8];\n rd0[8,8] = temp[16,8];\n rd0[0,8] = temp[24,8];\n}\n\n#---------------------------------------------------------------------\n# SWAP.BH - Swap Bytes in Halfword\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SWAP.BH Format I\n# Operation: temp <- Rd\n# Rd[31:24] <- temp[23:16]\n# Rd[23:16] <- temp[31:24]\n# Rd[15:8] <- temp[7:0]\n# Rd[7:0] <- temp[15:8]\n# Syntax: swap.bh Rd\n# 0101 1100 1100 dddd\n\n:SWAP.BH rd0 is op4_12=0x5cc & rd0\n{\n temp:4 = rd0;\n rd0[24,8] = temp[16,8];\n rd0[16,8] = temp[24,8];\n rd0[8,8] = temp[0,8];\n rd0[0,8] = temp[8,8];\n}\n\n#---------------------------------------------------------------------\n# SWAP.H - Swap Halfwords\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SWAP.H Format I\n# Operation: temp <- Rd\n# Rd[31:24] <- temp[23:16]\n# Rd[23:16] <- temp[31:24]\n# Rd[15:8] <- temp[7:0]\n# Rd[7:0] <- temp[15:8]\n# Syntax: swap.h Rd\n# 0101 1100 1010 dddd\n\n:SWAP.H rd0 is op4_12=0x5ca & rd0\n{\n temp:4 = rd0;\n rd0[16,16] = temp[0,16];\n rd0[0,16] = temp[16,16];\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_coprocessor_interface.sinc", "content": "#---------------------------------------------------------------------\n# Coprocessor Interface\n#---------------------------------------------------------------------\n\n# COP decodes the coprocessor number for display purposes\n# because the sleigh \"dec\" field attribute doesn't exist\n\nCOPD: \"CP0\" is cp13_3=0x0 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP1\" is cp13_3=0x1 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP2\" is cp13_3=0x2 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP3\" is cp13_3=0x3 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP4\" is cp13_3=0x4 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP5\" is cp13_3=0x5 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP6\" is cp13_3=0x6 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\nCOPD: \"CP7\" is cp13_3=0x7 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; }\n\n# CRD decodes the coprocessor number for display purposes\n# because the sleigh \"dec\" field attribute doesn't exist\n\nCRD: \"CR0\" is crd8_4=0x0 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR1\" is crd8_4=0x1 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR2\" is crd8_4=0x2 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR3\" is crd8_4=0x3 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR4\" is crd8_4=0x4 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR5\" is crd8_4=0x5 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR6\" is crd8_4=0x6 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR7\" is crd8_4=0x7 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR8\" is crd8_4=0x8 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR9\" is crd8_4=0x9 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR10\" is crd8_4=0xa & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR11\" is crd8_4=0xb & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR12\" is crd8_4=0xc & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR13\" is crd8_4=0xd & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR14\" is crd8_4=0xe & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\nCRD: \"CR15\" is crd8_4=0xf & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; }\n\nCRX: \"CR0\" is crx4_4=0x0 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR1\" is crx4_4=0x1 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR2\" is crx4_4=0x2 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR3\" is crx4_4=0x3 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR4\" is crx4_4=0x4 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR5\" is crx4_4=0x5 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR6\" is crx4_4=0x6 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR7\" is crx4_4=0x7 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR8\" is crx4_4=0x8 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR9\" is crx4_4=0x9 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR10\" is crx4_4=0xa & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR11\" is crx4_4=0xb & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR12\" is crx4_4=0xc & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR13\" is crx4_4=0xd & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR14\" is crx4_4=0xe & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\nCRX: \"CR15\" is crx4_4=0xf & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; }\n\nCRY: \"CR0\" is cry0_4=0x0 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR1\" is cry0_4=0x1 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR2\" is cry0_4=0x2 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR3\" is cry0_4=0x3 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR4\" is cry0_4=0x4 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR5\" is cry0_4=0x5 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR6\" is cry0_4=0x6 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR7\" is cry0_4=0x7 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR8\" is cry0_4=0x8 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR9\" is cry0_4=0x9 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR10\" is cry0_4=0xa & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR11\" is cry0_4=0xb & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR12\" is cry0_4=0xc & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR13\" is cry0_4=0xd & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR14\" is cry0_4=0xe & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\nCRY: \"CR15\" is cry0_4=0xf & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; }\n\nCPLoadAddress: is rp0=0xf ; eb15 { ldadd = inst_start; } # Rp=PC \nCPLoadAddress: is rp0 ; eb15 { ldadd = rp0; } # Rp!=PC\n\nLDCMDinc7: \",CR14-CR15\" is eb7=1 { tmp:1 = 14; tmpa:1 = 15; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc6: \",CR12-CR13\" is eb6=1 { tmp:1 = 12; tmpa:1 = 13; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc5: \",CR10-CR11\" is eb5=1 { tmp:1 = 10; tmpa:1 = 11; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc4: \",CR8-CR9\" is eb4=1 { tmp:1 = 8; tmpa:1 = 9; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc3: \",CR6-CR7\" is eb3=1 { tmp:1 = 6; tmpa:1 = 7; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc2: \",CR4-CR5\" is eb2=1 { tmp:1 = 4; tmpa:1 = 5; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc1: \",CR2-CR3\" is eb1=1 { tmp:1 = 2; tmpa:1 = 3; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\nLDCMDinc0: \",CR0-CR1\" is eb0=1 { tmp:1 = 0; tmpa:1 = 1; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; }\n\n\nLDCMWinc15: \",CR15\" is eb7=1 { tmp:1 = 15; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc14: \",CR14\" is eb6=1 { tmp:1 = 14; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc13: \",CR13\" is eb5=1 { tmp:1 = 13; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc12: \",CR12\" is eb4=1 { tmp:1 = 12; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc11: \",CR11\" is eb3=1 { tmp:1 = 11; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc10: \",CR10\" is eb2=1 { tmp:1 = 10; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc9: \",CR9\" is eb1=1 { tmp:1 = 9; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc8: \",CR8\" is eb0=1 { tmp:1 = 8; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\n\nLDCMWinc7: \",CR7\" is eb7=1 { tmp:1 = 7; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc6: \",CR6\" is eb6=1 { tmp:1 = 6; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc5: \",CR5\" is eb5=1 { tmp:1 = 5; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc4: \",CR4\" is eb4=1 { tmp:1 = 4; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc3: \",CR3\" is eb3=1 { tmp:1 = 3; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc2: \",CR2\" is eb2=1 { tmp:1 = 2; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc1: \",CR1\" is eb1=1 { tmp:1 = 1; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\nLDCMWinc0: \",CR0\" is eb0=1 { tmp:1 = 0; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; }\n\nLDCMWinc15: is eb7=0 { }\nLDCMWinc14: is eb6=0 { }\nLDCMWinc13: is eb5=0 { }\nLDCMWinc12: is eb4=0 { }\nLDCMWinc11: is eb3=0 { }\nLDCMWinc10: is eb2=0 { }\nLDCMWinc9: is eb1=0 { }\nLDCMWinc8: is eb0=0 { }\n\nLDCMWinc7: is eb7=0 { }\nLDCMWinc6: is eb6=0 { }\nLDCMWinc5: is eb5=0 { }\nLDCMWinc4: is eb4=0 { }\nLDCMWinc3: is eb3=0 { }\nLDCMWinc2: is eb2=0 { }\nLDCMWinc1: is eb1=0 { }\nLDCMWinc0: is eb0=0 { }\n\nLDCMDinc7: is eb7=0 { }\nLDCMDinc6: is eb6=0 { }\nLDCMDinc5: is eb5=0 { }\nLDCMDinc4: is eb4=0 { }\nLDCMDinc3: is eb3=0 { }\nLDCMDinc2: is eb2=0 { }\nLDCMDinc1: is eb1=0 { }\nLDCMDinc0: is eb0=0 { }\n\nLDCMpp: is rd0 ; eb12=0 { }\nLDCMpp: \"++\" is rd0 ; eb12=1 { rd0 = ldadd; }\n\nLDCMDcommon: LDCMDinc0^LDCMDinc1^LDCMDinc2^LDCMDinc3^LDCMDinc4^LDCMDinc5^LDCMDinc6^LDCMDinc7 is \n\tLDCMDinc0 & LDCMDinc1 & LDCMDinc2 & LDCMDinc3 & LDCMDinc4 & LDCMDinc5 & LDCMDinc6 & LDCMDinc7\n{\n build LDCMDinc7;\n build LDCMDinc6;\n build LDCMDinc5;\n build LDCMDinc4;\n build LDCMDinc3;\n build LDCMDinc2;\n build LDCMDinc1;\n build LDCMDinc0;\n}\n\nLDCMWLcommon: LDCMWinc0^LDCMWinc1^LDCMWinc2^LDCMWinc3^LDCMWinc4^LDCMWinc5^LDCMWinc6^LDCMWinc7 is \n\tLDCMWinc0 & LDCMWinc1 & LDCMWinc2 & LDCMWinc3 & LDCMWinc4 & LDCMWinc5 & LDCMWinc6 & LDCMWinc7\n{\n build LDCMWinc7;\n build LDCMWinc6;\n build LDCMWinc5;\n build LDCMWinc4;\n build LDCMWinc3;\n build LDCMWinc2;\n build LDCMWinc1;\n build LDCMWinc0;\n}\n\nLDCMWHcommon: LDCMWinc8^LDCMWinc9^LDCMWinc10^LDCMWinc11^LDCMWinc12^LDCMWinc13^LDCMWinc14^LDCMWinc15 is \n\tLDCMWinc8 & LDCMWinc9 & LDCMWinc10 & LDCMWinc11 & LDCMWinc12 & LDCMWinc13 & LDCMWinc14 & LDCMWinc15\n{\n build LDCMWinc15;\n build LDCMWinc14;\n build LDCMWinc13;\n build LDCMWinc12;\n build LDCMWinc11;\n build LDCMWinc10;\n build LDCMWinc9;\n build LDCMWinc8;\n}\n\n\nSTCMDdec7: \",CR14-CR15\" is eb7=1 { ldadd = ldadd - 8; tmp:1 = 14; tmpa:1 = 15; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec6: \",CR12-CR13\" is eb6=1 { ldadd = ldadd - 8; tmp:1 = 12; tmpa:1 = 13; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec5: \",CR10-CR11\" is eb5=1 { ldadd = ldadd - 8; tmp:1 = 10; tmpa:1 = 11; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec4: \",CR8-CR9\" is eb4=1 { ldadd = ldadd - 8; tmp:1 = 8; tmpa:1 = 9; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec3: \",CR6-CR7\" is eb3=1 { ldadd = ldadd - 8; tmp:1 = 6; tmpa:1 = 7; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec2: \",CR4-CR5\" is eb2=1 { ldadd = ldadd - 8; tmp:1 = 4; tmpa:1 = 5; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec1: \",CR2-CR3\" is eb1=1 { ldadd = ldadd - 8; tmp:1 = 2; tmpa:1 = 3; storeCoprocessorDword(tmp,tmpa,ldadd); }\nSTCMDdec0: \",CR0-CR1\" is eb0=1 { ldadd = ldadd - 8; tmp:1 = 0; tmpa:1 = 1; storeCoprocessorDword(tmp,tmpa,ldadd); }\n\n\nSTCMWdec15: \",CR15\" is eb7=1 { ldadd = ldadd - 4; tmp:1 = 15; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec14: \",CR14\" is eb6=1 { ldadd = ldadd - 4; tmp:1 = 14; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec13: \",CR13\" is eb5=1 { ldadd = ldadd - 4; tmp:1 = 13; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec12: \",CR12\" is eb4=1 { ldadd = ldadd - 4; tmp:1 = 12; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec11: \",CR11\" is eb3=1 { ldadd = ldadd - 4; tmp:1 = 11; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec10: \",CR10\" is eb2=1 { ldadd = ldadd - 4; tmp:1 = 10; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec9: \",CR9\" is eb1=1 { ldadd = ldadd - 4; tmp:1 = 9; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec8: \",CR8\" is eb0=1 { ldadd = ldadd - 4; tmp:1 = 8; storeCoprocessorWord(tmp,ldadd); }\n\nSTCMWdec7: \",CR7\" is eb7=1 { ldadd = ldadd - 4; tmp:1 = 7; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec6: \",CR6\" is eb6=1 { ldadd = ldadd - 4; tmp:1 = 6; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec5: \",CR5\" is eb5=1 { ldadd = ldadd - 4; tmp:1 = 5; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec4: \",CR4\" is eb4=1 { ldadd = ldadd - 4; tmp:1 = 4; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec3: \",CR3\" is eb3=1 { ldadd = ldadd - 4; tmp:1 = 3; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec2: \",CR2\" is eb2=1 { ldadd = ldadd - 4; tmp:1 = 2; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec1: \",CR1\" is eb1=1 { ldadd = ldadd - 4; tmp:1 = 1; storeCoprocessorWord(tmp,ldadd); }\nSTCMWdec0: \",CR0\" is eb0=1 { ldadd = ldadd - 4; tmp:1 = 0; storeCoprocessorWord(tmp,ldadd); }\n\nSTCMWdec15: is eb7=0 { }\nSTCMWdec14: is eb6=0 { }\nSTCMWdec13: is eb5=0 { }\nSTCMWdec12: is eb4=0 { }\nSTCMWdec11: is eb3=0 { }\nSTCMWdec10: is eb2=0 { }\nSTCMWdec9: is eb1=0 { }\nSTCMWdec8: is eb0=0 { }\n\nSTCMWdec7: is eb7=0 { }\nSTCMWdec6: is eb6=0 { }\nSTCMWdec5: is eb5=0 { }\nSTCMWdec4: is eb4=0 { }\nSTCMWdec3: is eb3=0 { }\nSTCMWdec2: is eb2=0 { }\nSTCMWdec1: is eb1=0 { }\nSTCMWdec0: is eb0=0 { }\n\nSTCMDdec7: is eb7=0 { }\nSTCMDdec6: is eb6=0 { }\nSTCMDdec5: is eb5=0 { }\nSTCMDdec4: is eb4=0 { }\nSTCMDdec3: is eb3=0 { }\nSTCMDdec2: is eb2=0 { }\nSTCMDdec1: is eb1=0 { }\nSTCMDdec0: is eb0=0 { }\n\nSTCMDcommon: STCMDdec0^STCMDdec1^STCMDdec2^STCMDdec3^STCMDdec4^STCMDdec5^STCMDdec6^STCMDdec7 is \n\tSTCMDdec0 & STCMDdec1 & STCMDdec2 & STCMDdec3 & STCMDdec4 & STCMDdec5 & STCMDdec6 & STCMDdec7\n{\n build STCMDdec0;\n build STCMDdec1;\n build STCMDdec2;\n build STCMDdec3;\n build STCMDdec4;\n build STCMDdec5;\n build STCMDdec6;\n build STCMDdec7;\n}\n\nSTCMWLcommon: STCMWdec0^STCMWdec1^STCMWdec2^STCMWdec3^STCMWdec4^STCMWdec5^STCMWdec6^STCMWdec7 is \n\tSTCMWdec0 & STCMWdec1 & STCMWdec2 & STCMWdec3 & STCMWdec4 & STCMWdec5 & STCMWdec6 & STCMWdec7\n{\n build STCMWdec0;\n build STCMWdec1;\n build STCMWdec2;\n build STCMWdec3;\n build STCMWdec4;\n build STCMWdec5;\n build STCMWdec6;\n build STCMWdec7;\n}\n\nSTCMWHcommon: STCMWdec8^STCMWdec9^STCMWdec10^STCMWdec11^STCMWdec12^STCMWdec13^STCMWdec14^STCMWdec15 is \n\tSTCMWdec8 & STCMWdec9 & STCMWdec10 & STCMWdec11 & STCMWdec12 & STCMWdec13 & STCMWdec14 & STCMWdec15\n{\n build STCMWdec8;\n build STCMWdec9;\n build STCMWdec10;\n build STCMWdec11;\n build STCMWdec12;\n build STCMWdec13;\n build STCMWdec14;\n build STCMWdec15;\n}\n\n\nSTCMmm: is rd0 ; eb12=0 { }\nSTCMmm: \"--\" is rd0 ; eb12=1 { rd0 = ldadd; }\n\n:COP COPD,CRD,CRX,CRY,ctx_coop\tis op11_5=0x1c & op4_5=0x1a & op9_2 & op0_4 & ctx_coop; \n\t\t\t\t\t\t\t\teop12_1 & COPD & CRD & CRX & CRY [ctx_cohi = op9_2; ctx_comid = op0_4; ctx_colow = eop12_1;] {\n\ttmp:1 = ctx_coop;\t\t\t\t\t\t\t\n\tCoprocessorOp(COPD,CRD,CRX,CRY,tmp);\n}\n\n#---------------------------------------------------------------------\n# LDC.{D,W} - Load Coprocessor\n#---------------------------------------------------------------------\n\n# LDC.{D,W} Format I\n# 1110 1001 1010 pppp CCC1 DDD0 nnnn nnnn\n\n:LDC.D COPD,CRD,RPwDisp8 is (op4_12=0xe9a;\n eop12_1=0x1 & crd8_1=0x0 & COPD & CRD)\n & RPwDisp8 { \n\tloadCoprocessorDWord(COPD, CRD, RPwDisp8);\n}\n\n# LDC.{D,W} Format II\n# 1110 1111 1010 pppp CCC0 DDD0 0101 0000\n\n:LDC.D COPD,CRD,RPdDec0 is op4_12=0xefa & RPdDec0;\n eop12_1=0x0 & crd8_1=0x0 & eop0_8=0x50\n & COPD & CRD {\n\tloadCoprocessorDWord(COPD, CRD, RPdDec0);\n}\n\n# LDC.{D,W} Format III\n# NOTE: documentation says bits 16-19 are pppp, but we assume they meant bbbb\n# 1110 1111 1010 bbbb CCC1 DDD0 01tt iiii\n\n:LDC.D COPD,CRD,RBShift0 is (op4_12=0xefa;\n eop12_1=0x1 & crd8_1=0x0 & eop6_2=0x1\n & COPD & CRD) & RBShift0 {\n\tloadCoprocessorDWord(COPD, CRD, RBShift0);\n}\n\n# LDC.{D,W} Format IV\n# 1110 1001 1010 pppp CCC0 DDDD nnnn nnnn\n\n:LDC.W COPD,CRD,RPwDisp8 is (op4_12=0xe9a;\n eop12_1=0x0 & COPD & CRD) & RPwDisp8 {\n\tloadCoprocessorWord(COPD, CRD, RPwDisp8);\n}\n\n# LDC.{D,W} Format V\n# 1110 1111 1010 pppp CCC1 DDDD 0100 0000\n\n:LDC.W COPD,CRD,RPwDec0 is op4_12=0xefa & RPwDec0;\n eop12_1=0x1 & eop0_8=0x40 & COPD & CRD {\n\tloadCoprocessorWord(COPD, CRD, RPwDec0);\n}\n\n# LDC.{D,W} Format VI\n# NOTE: documentation says bits 16-19 are pppp, but we assume they meant bbbb\n# 1110 1111 1010 bbbb CCC1 DDDD 00tt iiii\n\n:LDC.W COPD,CRD,RBShift0 is (op4_12=0xefa;\n eop12_1=0x1 & eop6_2=0x0 & COPD & CRD)\n & RBShift0 {\n\tloadCoprocessorWord(COPD, CRD, RBShift0);\n}\n\n#---------------------------------------------------------------------\n# LDC0.{D,W} - Load Coprocessor 0\n#---------------------------------------------------------------------\n\n# LDC0.{D,W} Format I\n# 1111 0011 1010 pppp nnnn DDD0 nnnn nnnn\n\n:LDC0.D \"CP0,\" CRD,RPwDisp12 is (op4_12=0xf3a; crd8_1=0x0 & CRD) & RPwDisp12 {\n\tcp:1 = 0;\n\tloadCoprocessorDWord(cp, CRD, RPwDisp12);\n}\n\n# LDC0.{D,W} Format II\n# 1111 0001 1010 pppp nnnn DDDD nnnn nnnn\n\n:LDC0.W \"CP0,\" CRD,RPwDisp12 is (op4_12=0xf1a; CRD) & RPwDisp12 {\n\tcp:1 = 0;\n\tloadCoprocessorDWord(cp, CRD, RPwDisp12);\n}\n\n\n:LDCM.D ecop13_3,rp0^LDCMpp^LDCMDcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x4 & LDCMDcommon) & LDCMpp & CPLoadAddress {\n\tbuild CPLoadAddress;\n\tbuild LDCMDcommon;\n\tbuild LDCMpp;\n}\n\n:LDCM.W ecop13_3,rp0^LDCMpp^LDCMWHcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x1 & LDCMWHcommon) & LDCMpp & CPLoadAddress {\n\tbuild CPLoadAddress;\n\tbuild LDCMWHcommon;\n\tbuild LDCMpp;\n}\n\n:LDCM.W ecop13_3,rp0^LDCMpp^LDCMWLcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x0 & LDCMWLcommon) & LDCMpp & CPLoadAddress {\n\tbuild CPLoadAddress;\n\tbuild LDCMWLcommon;\n\tbuild LDCMpp;\n}\n\n:MVCR.D COPD,rd0,CRD \tis op4_12=0xefa & b0=0x0 & rd0; COPD & eb12=0x0 & CRD & eop0_9=0x10 {\n\tCoProcessorDWordToReg(COPD, CRD, rd0);\n}\n:MVCR.W COPD,rd0,CRD \tis op4_12=0xefa & b0=0x0 & rd0; COPD & eb12=0x0 & CRD & eop0_8=0x0 {\n\tCoProcessorWordToReg(COPD, CRD, rd0);\n}\n\n:MVRC.D COPD,CRD,rs0 \tis op4_12=0xefa & b0=0x0 & rs0; COPD & eb12=0x0 & CRD & eop0_9=0x30 {\n\tRegToCoProcessorDWord(COPD, CRD, rs0);\n}\n:MVRC.W COPD,CRD,rs0 \tis op4_12=0xefa & b0=0x0 & rs0; COPD & eb12=0x0 & CRD & eop0_9=0x20 {\n\tRegToCoProcessorWord(COPD, CRD, rs0);\n}\n\n:STC.D COPD,RPwDisp8,CRD is (op4_12=0xeba;\n eop12_1=0x1 & crd8_1=0x0 & COPD & CRD)\n & RPwDisp8 { \n\tstoreCoprocessorDword(COPD, CRD, RPwDisp8);\n}\n\n:STC.D COPD,RPdDec0,CRD is op4_12=0xefa & RPdDec0;\n eop12_1=0x0 & crd8_1=0x0 & eop0_8=0x70\n & COPD & CRD {\n\tstoreCoprocessorDword(COPD, CRD, RPdDec0);\n}\n\n:STC.D COPD,RBShift0,CRD is (op4_12=0xefa;\n eop12_1=0x1 & crd8_1=0x0 & eop6_2=0x3\n & COPD & CRD) & RBShift0 {\n\tstoreCoprocessorDword(COPD, CRD, RBShift0);\n}\n\n:STC.W COPD,RPwDisp8,CRD is (op4_12=0xeba;\n eop12_1=0x0 & COPD & CRD) & RPwDisp8 {\n\tstoreCoprocessorWord(COPD, CRD, RPwDisp8);\n}\n\n:STC.W COPD,RPwDec0,CRD is op4_12=0xefa & RPwDec0;\n eop12_1=0x1 & eop0_8=0x60 & COPD & CRD {\n\tstoreCoprocessorWord(COPD, CRD, RPwDec0);\n}\n\n:STC.W COPD,RBShift0,CRD is (op4_12=0xefa;\n eop12_1=0x1 & eop6_2=0x2 & COPD & CRD)\n & RBShift0 {\n\tstoreCoprocessorWord(COPD, CRD, RBShift0);\n}\n\n:STC0.D \"CP0,\" CRD,RPwDisp12 is (op4_12=0xf7a; crd8_1=0x0 & CRD) & RPwDisp12 {\n\tcp:1 = 0;\n\tstoreCoprocessorDword(cp, CRD, RPwDisp12);\n}\n\n:STC0.W \"CP0,\" CRD,RPwDisp12 is (op4_12=0xf5a; CRD) & RPwDisp12 {\n\tcp:1 = 0;\n\tstoreCoprocessorWord(cp, CRD, RPwDisp12);\n}\n\n:STCM.D ecop13_3,STCMmm^rp0^STCMDcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x5 & STCMDcommon) & STCMmm & CPLoadAddress {\n\tbuild CPLoadAddress;\n\tbuild STCMDcommon;\n\tbuild STCMmm;\n}\n\n:STCM.W ecop13_3,STCMmm^rp0^STCMWHcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x3 & STCMWHcommon) & STCMmm & CPLoadAddress {\n\tbuild CPLoadAddress;\n\tbuild STCMWHcommon;\n\tbuild STCMmm;\n}\n\n:STCM.W ecop13_3,STCMmm^rp0^STCMWLcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x2 & STCMWLcommon) & STCMmm & CPLoadAddress {\n\tbuild CPLoadAddress;\n\tbuild STCMWLcommon;\n\tbuild STCMmm;\n}\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_data_transfer.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.9 Data Transfer\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# 8.3.9.1 Move/Load Immediate Operations\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# MOV - Move Data Into Register\n#---------------------------------------------------------------------\n\n# MOV Format I\n# 0011 iiii iiii dddd\n\n:MOV rd0, imm4_8 is op13_3=0x1 & op12_1=1 & rd0 & imm4_8 {\n rd0 = imm4_8;\n}\n\n# MOV Format II\n# 111i iii0 011i dddd iiii iiii iiii iiii\n\n:MOV rd0, imm is op13_3=0x7 & op5_4=0x3 & imm9_4 & imm4_1 & rd0; imm16\n [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ]\n{\n rd0 = imm;\n} \n\n# MOV Format III\n# 000s sss0 1001 dddd\n\n:MOV rd0, rs9 is op13_3=0x0 & op4_5=0x09 & rd0 & rs9 {\n rd0 = rs9;\n}\n\n#---------------------------------------------------------------------\n# MOV{cond4} - Conditional Move Register\n# I. {d, s} -> {0, 1, ..., 15}\n# cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}\n# II. d -> {0, 1, ..., 15}\n# cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}\n# imm -> {-128, -127, ..., 127}\n#---------------------------------------------------------------------\n\n# MOV{cond4} Format I\n# Operation: if (cond4)\n# Rd <- Rs\n# Syntax: mov{cond4} Rd, Rs\n# 111s sss0 0000 dddd 0001 0111 cccc 0000\n\n:MOV^{ECOND_4_4} rd0, rs9 is op13_3=0x7 & op4_5=0 & rd0 & rs9;\n eop8_8=0x17 & eop0_4=0 & ECOND_4_4\n{\n build ECOND_4_4;\n rd0 = rs9;\n}\n\n# MOV{cond4} Format II\n# Operation: if (cond4)\n# Rd <- SE(imm8)\n# Syntax: mov{cond4} Rd, imm\n# 1111 1001 1011 dddd 0000 cccc iiii iiii\n\n:MOV^{ECOND_8_4} rd0, simm0_8 is op4_12=0xf9b & rd0 ;\n eop12_4=0 & simm0_8 & ECOND_8_4\n{\n build ECOND_8_4;\n rd0 = simm0_8;\n}\n\n:MOVH\trd0, imm16\t\tis op4_12=0xfc1 & rd0 ; imm16 {\n\trd0 = imm16 << 16;\n}\n\n#---------------------------------------------------------------------\n# 8.3.9.2 Load/Store Operations\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# LD.D - Load Doubleword\n# I-V. d -> {0, 2, ..., 14}\n# IV. disp -> {-32768, -32767, ..., 32767}\n# V. sa -=> {0, 1, 2, 3}\n#---------------------------------------------------------------------\n\n# LD.D Format I\n# Operation: Rd+1:Rd <- *(Rp)\n# Rp <- Rp + 8;\n# Syntax: ld.d Rd, Rp++\n# 101p ppp1 0000 ddd1\n\n:LD.D rd0_low, RPdInc is op13_3=0x5 & op4_5=0x10 & b0=1 & RPdInc & rd0 & rd0_hi & rd0_low\n{\n rd0_hi = *:4 RPdInc;\n rd0_low = *:4 (RPdInc + 4);\n}\n\n# LD.D Format II\n# Operation: Rp <- Rp - 8;\n# Rd+1:Rd <- *(Rp)\n# Syntax: ld.d Rd, --Rp\n# 101p ppp1 0001 ddd0\n\n:LD.D rd0_low, RPdDec is op13_3=0x5 & op4_5=0x11 & b0=0 & RPdDec & rd0 & rd0_hi & rd0_low\n{\n rd0_hi = *:4 RPdDec;\n rd0_low = *:4 (RPdDec + 4);\n}\n\n# LD.D Format III\n# Operation: Rd+1:Rd <- *(Rp)\n# Syntax: ld.d Rd, Rp\n# 101p ppp1 0000 ddd0\n\n:LD.D rd0_low, rp9 is op13_3=0x5 & op4_5=0x10 & b0=0 & rp9 & rd0 & rd0_hi & rd0_low\n{\n rd0_hi = *:4 rp9;\n rd0_low = *:4 (rp9 + 4);\n}\n\n# LD.D Format IV\n# Operation: Rd+1:Rd <- *(Rp + SE(disp16))\n# Syntax: ld.d Rd, Rp[disp16]\n# 111p ppp0 1110 ddd0 nnnn nnnn nnnn nnnn\n\n:LD.D rd0_low, RPDisp16 is (op13_3=0x7 & op4_5=0xe\n & b0=0 & rd0 & rd0_hi & rd0_low) ... & RPDisp16\n{\n rd0_hi = *:4 RPDisp16;\n rd0_low = *:4 (RPDisp16 + 4);\n}\n\n# LD.D Format V\n# Operation: Rd+1:Rd <- *(Rb + (Ri << sa2))\n# Syntax: ld.d Rd, Rb[Ri< {0, 1, ..., 15}\n# disp -> {0, 4, ..., 508}\n#---------------------------------------------------------------------\n\n# LDDPC Format I\n# Operation: Rd <- *((PC && 0xfffffffc) + (ZE(disp7) << 2))\n# Syntax: lddpc Rd, PC[disp]\n# 0100 1nnn nnnn dddd\n\nLDDPCdisp: disp is disp4_7\n[ disp = (inst_start & 0xfffffffc) + (disp4_7 << 2); ]\n{\n export *:4 disp;\n}\n\n:LDDPC rd0, LDDPCdisp is op11_5=0x9 & LDDPCdisp & rd0\n{\n rd0 = LDDPCdisp;\n}\n\n:LDDPC rd0, LDDPCdisp is op11_5=0x9 & LDDPCdisp & rd0 & rd0=0xf\n{\n PC = LDDPCdisp;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# LDDSP - Load SP-relative with Displacement\n# I. d -> {0, 1, ..., 15}\n# disp -> {0, 4, ..., 508}\n#---------------------------------------------------------------------\n\n# LDDSP Format I\n# Operation: Rd <- *((SP && 0xfffffffc) + (ZE(disp7) << 2))\n# Syntax: lddsp Rd, SP[disp]\n# 0100 0nnn nnnn dddd\n\n:LDDSP rd0^\", SP[\"^disp^\"]\" is op11_5=0x8 & disp4_7 & rd0\n[ disp = (disp4_7 << 2); ]\n{\n ptr:4 = (SP & 0xfffffffc) + disp;\n # assuming SP was pointing into RAM...\n rd0 = * ptr;\n}\n\n:LDDSP rd0^\", SP[\"^disp^\"]\" is op11_5=0x8 & disp4_7 & rd0 & rd0=0xf\n[ disp = (disp4_7 << 2); ]\n{\n ptr:4 = (SP & 0xfffffffc) + disp;\n # assuming SP was pointing into RAM...\n goto [ ptr ];\n}\n\nLDBP: \"B\"\t\t\tis imm12_2=0 {}\nLDBP: \"L\"\t\t\tis imm12_2=1 {}\nLDBP: \"U\"\t\t\tis imm12_2=2 {}\nLDBP: \"T\"\t\t\tis imm12_2=3 {}\n:LDINS.B rd0:LDBP, rp9\"[\"disp0_11\"]\"\t\tis op13_3=0x7 & op4_5=0x1d & rd0 & rp9 ; eop14_2=0x1 & LDBP & disp0_11 & imm12_2 {\n\ttmp:4 = disp0_11;\n\ttmpa:4 = rp9 + tmp;\n\ttmpb:1 = *[RAM]:1 tmpa;\n\ttmpc:4 = zext(tmpb);\n\ttmpd:4 = tmpc << (8 * imm12_2);\n\ttmpe:4 = 0xff;\n\ttmpe = tmpe << (8 * imm12_2);\n\ttmpf:4 = rp9 & ~tmpe;\n\trp9 = tmpf | tmpd;\n}\n\nLDSHIFT12: val\t\tis disp0_11 [ val = disp0_11 << 1; ] { export *[const]:2 val; }\nLDHP: \"B\"\t\t\tis eb12=0 {}\nLDHP: \"T\"\t\t\tis eb12=1 {}\n:LDINS.H rd0:LDHP, rp9[LDSHIFT12]\t\tis op13_3=0x7 & op4_5=0x1d & rd0 & rp9 ; cp13_3=0x0 & eb12 & LDHP & LDSHIFT12 {\n\ttmp:4 = sext(LDSHIFT12);\n\ttmpa:4 = rp9 + tmp;\n\ttmpb:2 = *[RAM]:2 tmpa;\n\ttmpc:4 = zext(tmpb);\n\ttmpd:4 = tmpc << (16 * eb12);\n\ttmpe:4 = 0xffff;\n\ttmpe = tmpe << (16 * eb12);\n\ttmpf:4 = rp9 & ~tmpe;\n\trp9 = tmpf | tmpd;\n}\n\n\nLDSTSWPH: val\t\tis disp0_12 [ val = disp0_12 << 1; ] { export *[const]:2 val; }\nLDSTSWPW: val\t\tis disp0_12 [ val = disp0_12 << 2; ] { export *[const]:2 val; }\n\n:LDSWP.SH rd0, rp9[LDSTSWPH] is op13_3=0x7 & op4_5=0x1d & rp9 & rd0 ; eop12_4=0x2 & LDSTSWPH {\n\ttmp:4 = sext(LDSTSWPH);\n\ttmpa:4 = rp9 + tmp;\n\ttmpb:2 = *[RAM]:2 tmpa; \n\ttmpc:2 = (tmpb << 8) | (tmpb >> 8);\n\trd0 = sext(tmpc);\n}\n\n:LDSWP.UH rd0, rp9[LDSTSWPH] is op13_3=0x7 & op4_5=0x1d & rp9 & rd0 ; eop12_4=0x3 & LDSTSWPH {\n\ttmp:4 = sext(LDSTSWPH);\n\ttmpa:4 = rp9 + tmp;\n\ttmpb:2 = *[RAM]:2 tmpa; \n\ttmpc:2 = (tmpb << 8) | (tmpb >> 8);\n\trd0 = zext(tmpc);\n}\n\n:LDSWP.W rd0, rp9[LDSTSWPW] is op13_3=0x7 & op4_5=0x1d & rp9 & rd0 ; eop12_4=0x8 & LDSTSWPW {\n\ttmp:4 = sext(LDSTSWPW);\n\ttmpa:4 = rp9 + tmp;\n\ttmpb:4 = *[RAM]:4 tmpa;\n\trd0 = (tmpb << 24) | (tmpb >> 24) | ((tmpb & 0x0000FF00) << 8) | ((tmpb & 0x00FF0000) >> 8); \n}\n\n:STSWP.H rp9[LDSTSWPH], rs0 is op13_3=0x7 & op4_5=0x1d & rp9 & rs0 ; eop12_4=0x9 & LDSTSWPH {\n\ttmp:4 = sext(LDSTSWPH);\n\ttmpa:4 = rp9 + tmp;\n\ttmpb:2 = rs0:2;\n\t*[RAM]:2 tmpa = (tmpb >> 8) | (tmpb << 8);\n}\n\n:STSWP.W rp9[LDSTSWPW], rs0 is op13_3=0x7 & op4_5=0x1d & rp9 & rs0 ; eop12_4=0xa & LDSTSWPW {\n\ttmp:4 = sext(LDSTSWPW);\n\ttmpa:4 = rp9 + tmp;\n\t*[RAM]:4 tmpa = (rs0 << 24) | (rs0 >> 24) | ((rs0 & 0x0000FF00) << 8) | ((rs0 & 0x00FF0000) >> 8);\n}\n\n#---------------------------------------------------------------------\n# ST.B - Store Byte\n#---------------------------------------------------------------------\n\n# ST.B Format I\n# 000p ppp0 1100 ssss\n\n:ST.B RP9bInc, rs0 is op13_3=0x0 & op4_5=0x0c & RP9bInc & rs0 {\n *:1 RP9bInc = rs0:1; \n}\n\n# ST.B Format II\n# 000p ppp0 1111 ssss\n\n:ST.B RP9bDec, rs0 is op13_3=0x0 & op4_5=0x0f & RP9bDec & rs0 {\n *:1 RP9bDec = rs0:1;\n}\n\n# ST.B Format III\n# 101p ppp0 1nnn ssss\n\n:ST.B RPbDisp3, rs0 is op13_3=0x5 & op7_2=0x1 & rs0 & RPbDisp3 {\n *:1 RPbDisp3 = rs0:1; \n}\n\n# ST.B Format IV\n# 111p ppp1 0110 ssss nnnn nnnn nnnn nnnn\n\n:ST.B RPDisp16, rs0 is (op13_3=0x7 & op4_5=0x16 & rs0) ... & RPDisp16 {\n *:1 RPDisp16 = rs0:1; \n}\n\n# ST.B Format V\n# 111b bbb0 0000 iiii 0000 1011 00tt ssss\n\n:ST.B RB9Shift, ers0 is (op13_3=0x7 & op4_5=0 & ri0;\n eop12_4=0 & eop8_4=0xb & eop6_2=0 & ers0) & RB9Shift {\n *:1 RB9Shift = ers0:1;\n}\n\n#---------------------------------------------------------------------\n# ST.B{cond4} - Conditionally Store Byte\n#---------------------------------------------------------------------\n\n# ST.B{cond4} Format I\n# 111p ppp1 1111 ssss cccc 111n nnnn nnnn\n\n:ST.B^{COND_e12} RPwDisp9, rs0 is (op13_3=0x7 & op4_5=0x1f & rs0;\n eop9_3=0x7 & COND_e12) & RPwDisp9 { \n build COND_e12;\n *:4 RPwDisp9 = rs0:1;\n}\n\n#---------------------------------------------------------------------\n# ST.D - Store Doubleword\n#---------------------------------------------------------------------\n\n# ST.D Format I\n# 101p ppp1 0010 sss0\n\n:ST.D RPdInc, rs0_low is op13_3=0x5 & op4_5=0x12 & b0=0\n & RPdInc & rs0 & rs0_hi & rs0_low {\n low:8 = zext(rs0_low);\n hi:8 = zext(rs0_hi) << 32;\n *:8 RPdInc = hi | low;\n}\n\n# ST.D Format II\n# 101p ppp1 0010 sss1\n\n:ST.D RPdDec, rs0_low is op13_3=0x5 & op4_5=0x12 & b0=1\n & RPdDec & rs0 & rs0_hi & rs0_low {\n low:8 = zext(rs0_low);\n hi:8 = zext(rs0_hi) << 32;\n *:8 RPdDec = hi | low;\n}\n\n# ST.D Format III\n# 101p ppp1 0001 sss1\n\n:ST.D rp9, rs0_low is op13_3=0x5 & op4_5=0x11 & b0=1\n & rp9 & rs0 & rs0_hi & rs0_low {\n low:8 = zext(rs0_low);\n hi:8 = zext(rs0_hi) << 32;\n *:8 rp9 = hi | low;\n}\n\n# ST.D Format IV\n# 111p ppp0 1110 sss1 nnnn nnnn nnnn nnnn\n\n:ST.D RPDisp16, rs0_low is (op13_3=0x7 & op4_5=0xe\n & b0=1 & rs0 & rs0_hi & rs0_low) ... & RPDisp16\n{\n low:8 = zext(rs0_low);\n hi:8 = zext(rs0_hi) << 32;\n *:8 RPDisp16 = hi | low;\n}\n\n# ST.D Format V\n# 111b bbb0 0000 iiii 0000 1000 00tt ssss\n\n:ST.D RB9Shift, ers0_low is (op13_3=0x7 & op4_5=0 & ri0;\n eop12_4=0 & eop8_4=0x8 & eop6_2=0\n & ers0 & ers0_hi & ers0_low) & RB9Shift\n{ \n low:8 = zext(ers0_low);\n hi:8 = zext(ers0_hi) << 32;\n *:8 RB9Shift = hi | low;\n}\n\n#---------------------------------------------------------------------\n# ST.H - Store Halfword\n#---------------------------------------------------------------------\n\n# ST.H Format I\n# 000p ppp0 1011 ssss\n\n:ST.H RPhInc, rs0 is op13_3=0x0 & op4_5=0x0b & RPhInc & rs0 {\n *:2 RPhInc = rs0:2; \n}\n\n# ST.H Format II\n# 000p ppp0 1110 ssss\n\n:ST.H RPhDec, rs0 is op13_3=0x0 & op4_5=0x0e & RPhDec & rs0 {\n *:2 RPhDec = rs0:2;\n}\n\n# ST.H Format III\n# 101p ppp0 0nnn ssss\n\n:ST.H RPhDisp3, rs0 is op13_3=0x5 & op7_2=0x0 & rs0 & RPhDisp3 {\n *:2 RPhDisp3 = rs0:2; \n}\n\n# ST.H Format IV\n# 111p ppp1 0101 ssss nnnn nnnn nnnn nnnn\n\n:ST.H RPDisp16, rs0 is (op13_3=0x7 & op4_5=0x15 & rs0) ... & RPDisp16 {\n *:2 RPDisp16 = rs0:2; \n}\n\n# ST.H Format V\n# 111b bbb0 0000 iiii 0000 1010 00tt ssss\n\n:ST.H RB9Shift, ers0 is (op13_3=0x7 & op4_5=0 & ri0;\n eop12_4=0 & eop8_4=0xa & eop6_2=0 & ers0) & RB9Shift {\n *:2 RB9Shift = ers0:2;\n}\n\n#---------------------------------------------------------------------\n# ST.H{cond4} - Conditionally Store Halfword\n#---------------------------------------------------------------------\n\n# ST.H{cond4} Format I\n# 111p ppp1 1111 ssss cccc 110n nnnn nnnn\n\n:ST.H^{COND_e12} RPhDisp9, rs0 is (op13_3=0x7 & op4_5=0x1f & rs0;\n eop9_3=0x6 & COND_e12) & RPhDisp9 { \n build COND_e12;\n *:4 RPhDisp9 = rs0:2;\n}\n\nSTXP: \"T\"\tis eb13=1 & ctx_savex {\n\ttmp:4 = ctx_savex;\n\ttmp = tmp >> 16;\n\texport *[const]:4 tmp;\n}\nSTXP: \"B\"\tis eb13=0 & ctx_savex {\n\ttmp:4 = ctx_savex;\n\ttmp = tmp & 0xFFFF;\n\texport *[const]:4 tmp;\n}\nSTYP: \"T\"\tis eb12=1 & ctx_savey {\n\ttmp:4 = ctx_savey;\n\ttmp = tmp >> 16;\n\texport *[const]:4 tmp;\n}\nSTYP: \"B\"\tis eb12=0 & ctx_savey {\n\ttmp:4 = ctx_savey;\n\ttmp = tmp & 0xFFFF;\n\texport *[const]:4 tmp;\n}\nSTHHD: val\tis edisp4_8 [ val = edisp4_8 << 2; ] { export *[const]:2 val; }\n:STHH.W erp0[STHHD],rx9:STXP,ry0:STYP is op13_3=0x7 & op4_5=0x1e & rx9 & ry0 ; eop14_2=0x3 & STXP & STYP & STHHD & erp0 [ctx_savex=rx9; ctx_savey=ry0;] {\n\ttmp:4 = zext(STHHD);\n\ttmp = erp0 + tmp;\n\t*[RAM]:4 tmp = (STXP << 16) | STYP;\n}\n\n:STHH.W erb0[eri8\" << \"shift4_2],rx9:STXP,ry0:STYP is op13_3=0x7 & op4_5=0x1e & rx9 & ry0 ; eop14_2=0x2 & STXP & STYP & eri8 & eop6_2=0x0 & shift4_2 & erb0 [ctx_savex=rx9; ctx_savey=ry0;] {\n\ttmp:4 = eri8 << shift4_2;\n\t*[RAM]:4 tmp = (STXP << 16) | STYP;\n}\n\n#---------------------------------------------------------------------\n# ST.W - Store Word\n#---------------------------------------------------------------------\n\n# ST.W Format I\n# 000p ppp0 1010 ssss\n\n:ST.W RPwInc,rs0 is op13_3=0x0 & op4_5=0x0a & RPwInc & rs0 {\n *:4 RPwInc = rs0;\n}\n\n# ST.W Format II\n# 000p ppp0 1101 ssss\n\n:ST.W RPwDec,rs0 is op13_3=0x0 & op4_5=0x0d & RPwDec & rs0 {\n *:4 RPwDec = rs0;\n}\n\n# ST.W Format III\n# 100p ppp1 nnnn ssss\n\n:ST.W RPwDisp4,rs0 is op13_3=0x4 & op8_1=1 & RPwDisp4 & rs0 {\n *:4 RPwDisp4 = rs0;\n}\n\n# ST.W Format IV\n# 111p ppp1 0100 ssss nnnn nnnn nnnn nnnn\n\n:ST.W RPDisp16,rs0 is (op13_3=7 & op4_5=0x14 & rs0) ... & RPDisp16 {\n *:4 RPDisp16 = rs0;\n}\n\n# ST.W Format V\n# 111b bbb0 0000 iiii 0000 1001 00tt ssss\n\n:ST.W RB9Shift,ers0 is (op13_3=0x7 & op4_5=0 & ri0;\n eop12_4=0 & eop8_4=0x9 & eop6_2=0 & ers0)\n & RB9Shift { \n *:4 RB9Shift = ers0;\n}\n\n#---------------------------------------------------------------------\n# ST.W - Conditionally Store Word\n#---------------------------------------------------------------------\n\n# ST.W{cond4} Format I\n# 111p ppp1 1111 ssss cccc 101n nnnn nnnn\n\n:ST.W^{COND_e12} RPwDisp9, rs0 is (op13_3=0x7 & op4_5=0x1f & rs0;\n eop9_3=0x5 & COND_e12) & RPwDisp9 { \n build COND_e12;\n *:4 RPwDisp9 = rs0;\n}\n\n:STCOND rp9[disp_16],rs0 \tis op13_3=0x7 & rp9 & op4_5=0x17 & rs0 ; disp_16 {\n\tZ = L;\n\tCZTOSR();\n\t\n\tif (!L) goto inst_next;\n\t\n\ttmp:2 = disp_16;\n\ttmpa:4 = sext(tmp);\n\ttmpa = tmpa + rp9;\n\t*[RAM]:4 tmpa = rs0;\n}\n\n#---------------------------------------------------------------------\n# STDSP - Store Stack-Pointer Relative\n# I. disp -> {0, 4, ..., 508}\n# s -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# STDSP Format I\n# Operation: *((SP & 0xfffffffc) + (ZE(disp7) << 2)) <- Rs\n# Syntax: stdsp SP[disp], Rs\n# 0101 0nnn nnnn ssss\n\n:STDSP \"SP[\"^disp4_7^\"], \"^rs0 is op11_5=0xa & disp4_7 & rs0\n{\n ptr:4 = (SP & 0xfffffffc) + (disp4_7 << 2);\n #ptr:4 = (((SP >> 2) + disp4_7) << 2);\n # assuming SP was pointing into RAM...\n *:4 ptr = rs0; \n}\n\n#---------------------------------------------------------------------\n# 8.3.9.3 Multiple Data\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# LDM - Load Multiple Registers\n#---------------------------------------------------------------------\n\n# LDM Format I\n# 1110 00M1 1100 pppp LLLL LLLL LLLL LLLL\n\nmacro status_r12() {\n V = 0;\n N = R12 s< 0;\n Z = R12 == 0;\n C = 0;\n CZNVTOSR();\n}\n\nLoadAddress: is rp0=0xf ; eb15=1 { ldadd = SP; } # Rp=PC and Reglist16[PC]=1\nLoadAddress: is rp0=0xf ; eb15 { ldadd = inst_start; } # Rp=PC and Reglist16[PC]=0\nLoadAddress: is rp0 ; eb15 { ldadd = rp0; } # Rp!=PC\nLoadAddressTS: is rp0 ; eb15 { ldadd = rp0; } \n\nLDMinc15: \", PC\" is eb15=1 { PC = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc14ab: \", LR\" is eb14=1 { LR = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc13ab: \", SP\" is eb13=1 { SP = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc12c: \", R12=0\" is eb14=0 & eb12=0 { R12 = 0; }\nLDMinc12c: \", R12=1\" is eb14=0 & eb12=1 { R12 = 1; }\nLDMinc12c: \", R12=-1\" is eb14=1 { R12 = -1; }\nLDMinc12ab: \", R12\" is eb12=1 { R12 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc12s: is eb15=1 { status_r12(); }\nLDMinc11: \", R11\" is eb11=1 { R11 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc10: \", R10\" is eb10=1 { R10 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc9: \", R9\" is eb9=1 { R9 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc8: \", R8\" is eb8=1 { R8 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc7: \", R7\" is eb7=1 { R7 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc6: \", R6\" is eb6=1 { R6 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc5: \", R5\" is eb5=1 { R5 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc4: \", R4\" is eb4=1 { R4 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc3: \", R3\" is eb3=1 { R3 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc2: \", R2\" is eb2=1 { R2 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc1: \", R1\" is eb1=1 { R1 = *:4 ldadd; ldadd = ldadd + 4; }\nLDMinc0: \", R0\" is eb0=1 { R0 = *:4 ldadd; ldadd = ldadd + 4; }\n\nLDMinc15: is eb15=0 { }\nLDMinc14ab: is eb14=0 { }\nLDMinc13ab: is eb13=0 { }\nLDMinc12ab: is eb12=0 { }\nLDMinc12s: is eb15=0 { }\nLDMinc11: is eb11=0 { }\nLDMinc10: is eb10=0 { }\nLDMinc9: is eb9=0 { }\nLDMinc8: is eb8=0 { }\nLDMinc7: is eb7=0 { }\nLDMinc6: is eb6=0 { }\nLDMinc5: is eb5=0 { }\nLDMinc4: is eb4=0 { }\nLDMinc3: is eb3=0 { }\nLDMinc2: is eb2=0 { }\nLDMinc1: is eb1=0 { }\nLDMinc0: is eb0=0 { }\n\nLDMpp: is op9_1=0 { }\nLDMpp: \"++\" is op9_1=1 & rp0=0xf { SP = ldadd; }\nLDMpp: \"++\" is op9_1=1 & rp0 { rp0 = ldadd; }\n\nLDMTSpp: is op9_1=0 { }\nLDMTSpp: \"++\" is op9_1=1 & rp0 { rp0 = ldadd; }\n\nLDMret: is eb15=1 { return [ PC ]; }\nLDMret: is eb15=0 { }\n\nLDMcommon: LDMinc0^LDMinc1^LDMinc2^LDMinc3^LDMinc4^LDMinc5^LDMinc6^LDMinc7^LDMinc8^LDMinc9^LDMinc10^LDMinc11 is LDMinc0 & LDMinc1 & LDMinc2 & LDMinc3 & LDMinc4 & LDMinc5\n & LDMinc6 & LDMinc7 & LDMinc8 & LDMinc9 & LDMinc10 & LDMinc11\n{\n build LDMinc11;\n build LDMinc10;\n build LDMinc9;\n build LDMinc8;\n build LDMinc7;\n build LDMinc6;\n build LDMinc5;\n build LDMinc4;\n build LDMinc3;\n build LDMinc2;\n build LDMinc1;\n build LDMinc0;\n}\n\nLDMlistd: LDMpp^LDMcommon^LDMinc12ab^LDMinc13ab^LDMinc14ab^LDMinc15 is (LDMpp ; LDMcommon & LDMinc12ab & LDMinc13ab & LDMinc14ab\n & LDMinc12s & LDMinc15 & LDMret) & LoadAddressTS\n{\n build LoadAddressTS;\n build LDMinc15;\n build LDMinc14ab;\n build LDMinc13ab;\n build LDMinc12ab;\n build LDMcommon;\n build LDMpp;\n build LDMret;\n}\n\nLDMlistc: LDMpp^LDMcommon^LDMinc12c^LDMinc15 is (LDMpp ; LDMcommon & LDMinc12c & LDMinc12s & LDMinc15 & LDMret) & LoadAddress\n{\n build LoadAddress;\n build LDMinc15;\n build LDMinc12c;\n build LDMinc12s;\n build LDMcommon;\n build LDMpp;\n build LDMret;\n}\n\nLDMlistb: LDMpp^LDMcommon^LDMinc12ab^LDMinc13ab^LDMinc14ab^LDMinc15 is (LDMpp ; LDMcommon & LDMinc12ab & LDMinc13ab & LDMinc14ab\n & LDMinc12s & LDMinc15 & LDMret) & LoadAddress\n{\n build LoadAddress;\n build LDMinc15;\n build LDMinc14ab;\n build LDMinc13ab;\n build LDMinc12ab;\n build LDMinc12s;\n build LDMcommon;\n build LDMpp;\n build LDMret;\n}\n\nLDMlista: LDMpp^LDMcommon^LDMinc12ab^LDMinc13ab^LDMinc14ab is (LDMpp ; LDMcommon & LDMinc12ab & LDMinc13ab & LDMinc14ab) & LoadAddress\n{\n build LoadAddress;\n build LDMinc14ab;\n build LDMinc13ab;\n build LDMinc12ab;\n build LDMcommon;\n build LDMpp;\n}\n\n:LDM rp0^LDMlistc is (rp0 & rp0=0xf & op10_6=0x38 & op4_5=0x1c ; eb15=1) & LDMlistc\n{\n build LDMlistc;\n}\n\n:LDM rp0^LDMlistb is (rp0 & op10_6=0x38 & op4_5=0x1c ; eb15=1) & LDMlistb\n{\n build LDMlistb;\n}\n\n:LDM rp0^LDMlista is (rp0 & op10_6=0x38 & op4_5=0x1c) ... & LDMlista\n{\n build LDMlista;\n}\n\n:LDMTS rp0^LDMlistd is (rp0 & op10_6=0x39 & op4_5=0x1c) ... & LDMlistd {\n\tbuild LDMlistd;\n}\n\n#---------------------------------------------------------------------\n# POPM - Load Multiple Registers\n#---------------------------------------------------------------------\n\n# POPM Format I\n# 1101 RRRR RRRR k010\nCOM5:\t\t\t\t is bp4_1=0 {}\nCOM5: \",\"\t\t\t is bp4_1 {}\nCOM6:\t\t\t\t is bp4_2=0 {}\nCOM6: \",\"\t\t\t is bp4_2 {}\nCOM7:\t\t\t\t is bp4_3=0 {}\nCOM7: \",\"\t\t\t is bp4_3 {}\nCOM8:\t\t\t\t is bp4_4=0 {}\nCOM8: \",\"\t\t\t is bp4_4 {}\nCOM9:\t\t\t\t is bp4_5=0 {}\nCOM9: \",\"\t\t\t is bp4_5 {}\nCOM10:\t\t\t\t is bp4_6=0 {}\nCOM10: \",\"\t\t\t is bp4_6 {}\nCOM11:\t\t\t\t is bp4_7=0 {}\nCOM11:\t\t\t\t is bp4_7=0x20 & b03=1 {}\nCOM11: \",\"\t\t\t is bp4_7 {}\n\nPOPMinc11: COM11^\"PC\" is b11=1 & COM11 { build COM11; PC = *:4 SP; SP = SP + 4; }\nPOPMinc10b: is b10 { }\nPOPMinc10a: COM10^\"LR\" is b10=1 & COM10 { build COM10; LR = *:4 SP; SP = SP + 4; }\nPOPMinc9b: \",R12=0\" is b11=1 & b10=0 & b09=0 { R12 = 0; }\nPOPMinc9b: \",R12=1\" is b11=1 & b10=0 & b09=1 { R12 = 1; }\nPOPMinc9b: \",R12=-1\" is b11=1 & b10=1 { R12 = -1; }\nPOPMinc9a: COM9^\"R12\" is b09=1 & COM9 { build COM9; R12 = *:4 SP; SP = SP + 4; }\nPOPMinc9s: is b11=1 { status_r12(); }\nPOPMinc8: COM8^\"R11\" is b08=1 & COM8 { build COM8; \n\t\t\t\t\t\t\t\t R11 = *:4 SP; SP = SP + 4; }\nPOPMinc7: COM7^\"R10\" is b07=1 & COM7 { build COM7;\n\t\t\t\t\t\t\t\t R10 = *:4 SP; SP = SP + 4; }\nPOPMinc6: COM6^\"R8-R9\" is b06=1 & COM6 { build COM6; \n\t\t\t\t\t\t\t\t R9 = *:4 SP; SP = SP + 4;\n R8 = *:4 SP; SP = SP + 4; }\nPOPMinc5: COM5^\"R4-R7\" is b05=1 & COM5 { build COM5;\n\t\t\t\t\t\t\t\t R7 = *:4 SP; SP = SP + 4;\n R6 = *:4 SP; SP = SP + 4;\n R5 = *:4 SP; SP = SP + 4;\n R4 = *:4 SP; SP = SP + 4; }\nPOPMinc4: \"R0-R3\" is b04=1 { R3 = *:4 SP; SP = SP + 4;\n R2 = *:4 SP; SP = SP + 4;\n R1 = *:4 SP; SP = SP + 4;\n R0 = *:4 SP; SP = SP + 4; }\nPOPMinc11: is b11=0 { }\nPOPMinc10a: is b10=0 { }\nPOPMinc9a: is b09=0 { }\nPOPMinc9b: is b11=0 { }\nPOPMinc9s: is b11=0 { }\nPOPMinc8: is b08=0 { }\nPOPMinc7: is b07=0 { }\nPOPMinc6: is b06=0 { }\nPOPMinc5: is b05=0 { }\nPOPMinc4: is b04=0 { }\n\nPOPMjump: is b11=1 { return [ PC ]; }\nPOPMjump: is b11=0 { }\n\nPOPMchunk: POPMinc4^POPMinc5^POPMinc6^POPMinc7^POPMinc8 is POPMinc4 & POPMinc5 & POPMinc6 & POPMinc7 & POPMinc8 & POPMinc9s & POPMjump\n{\n build POPMinc9s;\n build POPMinc8;\n build POPMinc7;\n build POPMinc6;\n build POPMinc5;\n build POPMinc4;\n build POPMjump;\n}\n\nPOPMdispa: POPMchunk^POPMinc9a^POPMinc10a^POPMinc11 is POPMchunk & POPMinc9a & POPMinc10a & POPMinc11\n{\n build POPMinc11;\n build POPMinc10a;\n build POPMinc9a;\n build POPMchunk;\n}\n\nPOPMdispb: POPMchunk^POPMinc10b^POPMinc11^POPMinc9b is POPMchunk & POPMinc9b & POPMinc10b & POPMinc11\n{\n build POPMinc11;\n build POPMinc10b;\n build POPMinc9b;\n build POPMchunk;\n}\n\n:POPM POPMdispa is op12_4=0xd & op0_4=0x2 & POPMdispa\n{\n build POPMdispa;\n}\n\n:POPM POPMdispb is op12_4=0xd & op0_4=0xa & POPMdispb\n{\n build POPMdispb;\n}\n\n#---------------------------------------------------------------------\n# PUSHM - Push Multiple Registers to Stack\n# I. Reglist8 -> {R0-R3, R4-R7, R8-R9, R10, R11, R12, LR, PC}\n#---------------------------------------------------------------------\n\n# PUSHM Format I:\n# Operation: if Reglist8[0] == 1 then\n# *(--SP) <- R0;\n# *(--SP) <- R1;\n# *(--SP) <- R2;\n# *(--SP) <- R3;\n# if Reglist8[1] == 1 then\n# *(--SP) <- R4;\n# *(--SP) <- R5;\n# *(--SP) <- R6;\n# *(--SP) <- R7;\n# if Reglist8[2] == 1 then\n# *(--SP) <- R8;\n# *(--SP) <- R9;\n# if Reglist8[3] == 1 then\n# *(--SP) <- R10;\n# if Reglist8[4] == 1 then\n# *(--SP) <- R11;\n# if Reglist8[5] == 1 then\n# *(--SP) <- R12;\n# if Reglist8[6] == 1 then\n# *(--SP) <- LR;\n# if Reglist8[7] == 1 then\n# *(--SP) <- PC;\n# Syntax: pushm Reglist8\n# 1101 RRRR RRRR 0001\n\nPUSHMdec4: \"R0-R3\" is b04=1 { SP = SP - 4; *:4 SP = R0;\n SP = SP - 4; *:4 SP = R1;\n SP = SP - 4; *:4 SP = R2;\n SP = SP - 4; *:4 SP = R3; }\nPUSHMdec5: COM5^\"R4-R7\" is b05=1 & COM5 { build COM5; \n\t\t\t\t\t\t\t\tSP = SP - 4; *:4 SP = R4;\n SP = SP - 4; *:4 SP = R5;\n SP = SP - 4; *:4 SP = R6;\n SP = SP - 4; *:4 SP = R7; }\nPUSHMdec6: COM6^\"R8-R9\" is b06=1 & COM6{ build COM6; \n\t\t\t\t\t\t\t\tSP = SP - 4; *:4 SP = R8;\n SP = SP - 4; *:4 SP = R9; }\nPUSHMdec7: COM7^\"R10\" is b07=1 & COM7 { build COM7; SP = SP - 4; *:4 SP = R10; }\nPUSHMdec8: COM8^\"R11\" is b08=1 & COM8 { build COM8; SP = SP - 4; *:4 SP = R11; }\nPUSHMdec9: COM9^\"R12\" is b09=1 & COM9 { build COM9; SP = SP - 4; *:4 SP = R12; }\nPUSHMdec10: COM10^\"LR\" is b10=1 & COM10 { build COM10; SP = SP - 4; *:4 SP = LR; }\nPUSHMdec11: COM11^\"PC\" is b11=1 & COM11 { build COM11; SP = SP - 4; *:4 SP = inst_start; }\nPUSHMdec4: is b04=0 { }\nPUSHMdec5: is b05=0 { }\nPUSHMdec6: is b06=0 { }\nPUSHMdec7: is b07=0 { }\nPUSHMdec8: is b08=0 { }\nPUSHMdec9: is b09=0 { }\nPUSHMdec10: is b10=0 { }\nPUSHMdec11: is b11=0 { }\n\nPUSHMdisp: PUSHMdec4^PUSHMdec5^PUSHMdec6^PUSHMdec7^PUSHMdec8^PUSHMdec9^PUSHMdec10^PUSHMdec11 is PUSHMdec4 & PUSHMdec5 & PUSHMdec6 & PUSHMdec7 \n & PUSHMdec8 & PUSHMdec9 & PUSHMdec10 & PUSHMdec11\n{\n build PUSHMdec4;\n build PUSHMdec5;\n build PUSHMdec6;\n build PUSHMdec7;\n build PUSHMdec8;\n build PUSHMdec9;\n build PUSHMdec10;\n build PUSHMdec11;\n}\n\n:PUSHM PUSHMdisp is \n op12_4=0xd & op0_4=0x1 & PUSHMdisp\n{\n build PUSHMdisp;\n}\n\n#---------------------------------------------------------------------\n# STM - Store Multiple Registers\n#---------------------------------------------------------------------\n\n# STM Format I\n# 1110 10M1 1100 pppp LLLL LLLL LLLL LLLL\n\nStoreAddress: is rp0 ; eb15 { stadd = rp0; } # Rp!=PC\n\nSTMinc0: ,deb0 is rp0 ; deb0 & eb0=1 { *:4 stadd = R0; stadd = stadd + 4; }\nSTMinc1: ,deb1 is rp0 ; deb1 & eb1=1 { *:4 stadd = R1; stadd = stadd + 4; }\nSTMinc2: ,deb2 is rp0 ; deb2 & eb2=1 { *:4 stadd = R2; stadd = stadd + 4; }\nSTMinc3: ,deb3 is rp0 ; deb3 & eb3=1 { *:4 stadd = R3; stadd = stadd + 4; }\nSTMinc4: ,deb4 is rp0 ; deb4 & eb4=1 { *:4 stadd = R4; stadd = stadd + 4; }\nSTMinc5: ,deb5 is rp0 ; deb5 & eb5=1 { *:4 stadd = R5; stadd = stadd + 4; }\nSTMinc6: ,deb6 is rp0 ; deb6 & eb6=1 { *:4 stadd = R6; stadd = stadd + 4; }\nSTMinc7: ,deb7 is rp0 ; deb7 & eb7=1 { *:4 stadd = R7; stadd = stadd + 4; }\nSTMinc8: ,deb8 is rp0 ; deb8 & eb8=1 { *:4 stadd = R8; stadd = stadd + 4; }\nSTMinc9: ,deb9 is rp0 ; deb9 & eb9=1 { *:4 stadd = R9; stadd = stadd + 4; }\nSTMinc10: ,deb10 is rp0 ; deb10 & eb10=1 { *:4 stadd = R10; stadd = stadd + 4; }\nSTMinc11: ,deb11 is rp0 ; deb11 & eb11=1 { *:4 stadd = R11; stadd = stadd + 4; }\nSTMinc12: ,deb12 is rp0 ; deb12 & eb12=1 { *:4 stadd = R12; stadd = stadd + 4; }\nSTMinc13: ,deb13 is rp0 ; deb13 & eb13=1 { *:4 stadd = SP; stadd = stadd + 4; }\nSTMinc14: ,deb14 is rp0 ; deb14 & eb14=1 { *:4 stadd = LR; stadd = stadd + 4; }\nSTMinc15: ,deb15 is rp0 ; deb15 & eb15=1 { *:4 stadd = inst_start; stadd = stadd + 4; }\nSTMinc0: is rp0 ; eb0=0 { }\nSTMinc1: is rp0 ; eb1=0 { }\nSTMinc2: is rp0 ; eb2=0 { }\nSTMinc3: is rp0 ; eb3=0 { }\nSTMinc4: is rp0 ; eb4=0 { }\nSTMinc5: is rp0 ; eb5=0 { }\nSTMinc6: is rp0 ; eb6=0 { }\nSTMinc7: is rp0 ; eb7=0 { }\nSTMinc8: is rp0 ; eb8=0 { }\nSTMinc9: is rp0 ; eb9=0 { }\nSTMinc10: is rp0 ; eb10=0 { }\nSTMinc11: is rp0 ; eb11=0 { }\nSTMinc12: is rp0 ; eb12=0 { }\nSTMinc13: is rp0 ; eb13=0 { }\nSTMinc14: is rp0 ; eb14=0 { }\nSTMinc15: is rp0 ; eb15=0 { }\n\nSTMdec0: ,deb0 is rp0 ; deb0 & eb0=1 { rp0 = rp0 - 4; *:4 rp0 = R0; }\nSTMdec1: ,deb1 is rp0 ; deb1 & eb1=1 { rp0 = rp0 - 4; *:4 rp0 = R1; }\nSTMdec2: ,deb2 is rp0 ; deb2 & eb2=1 { rp0 = rp0 - 4; *:4 rp0 = R2; }\nSTMdec3: ,deb3 is rp0 ; deb3 & eb3=1 { rp0 = rp0 - 4; *:4 rp0 = R3; }\nSTMdec4: ,deb4 is rp0 ; deb4 & eb4=1 { rp0 = rp0 - 4; *:4 rp0 = R4; }\nSTMdec5: ,deb5 is rp0 ; deb5 & eb5=1 { rp0 = rp0 - 4; *:4 rp0 = R5; }\nSTMdec6: ,deb6 is rp0 ; deb6 & eb6=1 { rp0 = rp0 - 4; *:4 rp0 = R6; }\nSTMdec7: ,deb7 is rp0 ; deb7 & eb7=1 { rp0 = rp0 - 4; *:4 rp0 = R7; }\nSTMdec8: ,deb8 is rp0 ; deb8 & eb8=1 { rp0 = rp0 - 4; *:4 rp0 = R8; }\nSTMdec9: ,deb9 is rp0 ; deb9 & eb9=1 { rp0 = rp0 - 4; *:4 rp0 = R9; }\nSTMdec10: ,deb10 is rp0 ; deb10 & eb10=1 { rp0 = rp0 - 4; *:4 rp0 = R10; }\nSTMdec11: ,deb11 is rp0 ; deb11 & eb11=1 { rp0 = rp0 - 4; *:4 rp0 = R11; }\nSTMdec12: ,deb12 is rp0 ; deb12 & eb12=1 { rp0 = rp0 - 4; *:4 rp0 = R12; }\nSTMdec13: ,deb13 is rp0 ; deb13 & eb13=1 { rp0 = rp0 - 4; *:4 rp0 = SP; }\nSTMdec14: ,deb14 is rp0 ; deb14 & eb14=1 { rp0 = rp0 - 4; *:4 rp0 = LR; }\nSTMdec15: ,deb15 is rp0 ; deb15 & eb15=1 { rp0 = rp0 - 4; *:4 rp0 = inst_start; }\nSTMdec0: is rp0 ; eb0=0 { }\nSTMdec1: is rp0 ; eb1=0 { }\nSTMdec2: is rp0 ; eb2=0 { }\nSTMdec3: is rp0 ; eb3=0 { }\nSTMdec4: is rp0 ; eb4=0 { }\nSTMdec5: is rp0 ; eb5=0 { }\nSTMdec6: is rp0 ; eb6=0 { }\nSTMdec7: is rp0 ; eb7=0 { }\nSTMdec8: is rp0 ; eb8=0 { }\nSTMdec9: is rp0 ; eb9=0 { }\nSTMdec10: is rp0 ; eb10=0 { }\nSTMdec11: is rp0 ; eb11=0 { }\nSTMdec12: is rp0 ; eb12=0 { }\nSTMdec13: is rp0 ; eb13=0 { }\nSTMdec14: is rp0 ; eb14=0 { }\nSTMdec15: is rp0 ; eb15=0 { }\n\nSTMdecdisp: STMdec0^STMdec1^STMdec2^STMdec3^STMdec4^STMdec5^STMdec6^STMdec7^STMdec8^STMdec9^STMdec10^STMdec11^STMdec12^STMdec13^STMdec14^STMdec15 is STMdec0 & STMdec1 & STMdec2 & STMdec3 & \n STMdec4 & STMdec5 & STMdec6 & STMdec7 & \n STMdec8 & STMdec9 & STMdec10 & STMdec11 & \n STMdec12 & STMdec13 & STMdec14 & STMdec15\n{\n build STMdec0;\n build STMdec1;\n build STMdec2;\n build STMdec3;\n build STMdec4;\n build STMdec5;\n build STMdec6;\n build STMdec7;\n build STMdec8;\n build STMdec9;\n build STMdec10;\n build STMdec11;\n build STMdec12;\n build STMdec13;\n build STMdec14;\n build STMdec15;\n}\n\nSTMincdisp: STMinc0^STMinc1^STMinc2^STMinc3^STMinc4^STMinc5^STMinc6^STMinc7^STMinc8^STMinc9^STMinc10^STMinc11^STMinc12^STMinc13^STMinc14^STMinc15 is STMinc0 & STMinc1 & STMinc2 & STMinc3 & \n STMinc4 & STMinc5 & STMinc6 & STMinc7 & \n STMinc8 & STMinc9 & STMinc10 & STMinc11 & \n STMinc12 & STMinc13 & STMinc14 & STMinc15 & StoreAddress\n{\n build StoreAddress;\n build STMinc15;\n build STMinc14;\n build STMinc13;\n build STMinc12;\n build STMinc11;\n build STMinc10;\n build STMinc9;\n build STMinc8;\n build STMinc7;\n build STMinc6;\n build STMinc5;\n build STMinc4;\n build STMinc3;\n build STMinc2;\n build STMinc1;\n build STMinc0;\n}\n \n:STM \"--\"^rp0^STMdecdisp\nis\n (op10_6=0x3a & op4_5=0x1c & op9_1=1 & rp0) ... & STMdecdisp\n{\n}\n\n:STM rp0^STMincdisp\nis\n (op10_6=0x3a & op4_5=0x1c & op9_1=0 & rp0) ... & STMincdisp\n{\n}\n\n:STMTS \"--\"^rp0^STMdecdisp\nis \n\t\t(op10_6=0x3b & op4_5=0x1c & op9_1=1 & rp0) ... & STMdecdisp \n{\n}\n\n:STMTS rp0^STMincdisp \nis \n\t\t(op10_6=0x3b & op4_5=0x1c & op9_1=0 & rp0) ... & STMincdisp \n{\n}\n\n:XCHG rx9, ry0, erd0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0xb4 & erd0 {\n\terd0 = *[RAM]:4 rx9;\n\t*[RAM]:4 rx9 = ry0;\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_dsp_operations.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.4 DSP Operations\n#---------------------------------------------------------------------\noperand1: \":b\" is rx9 ; selectorxy4_2=0x0 {b:4 = sext(rx9[0,16]); export b;}\noperand1: \":b\" is rx9 ; selectorxy4_2=0x1 {b:4 = sext(rx9[0,16]); export b;}\noperand1: \":t\" is rx9 ; selectorxy4_2=0x2 {t:4 = sext(rx9[16,16]); export t;}\noperand1: \":t\" is rx9 ; selectorxy4_2=0x3 {t:4 = sext(rx9[16,16]); export t;}\n\noperand2: \":b\" is ry0 ; selectorxy4_2=0x0 {b:4 = sext(ry0[0,16]); export b;}\noperand2: \":t\" is ry0 ; selectorxy4_2=0x1 {t:4 = sext(ry0[16,16]); export t;}\noperand2: \":b\" is ry0 ; selectorxy4_2=0x2 {b:4 = sext(ry0[0,16]); export b;}\noperand2: \":t\" is ry0 ; selectorxy4_2=0x3 {t:4 = sext(ry0[16,16]); export t;}\n\nrdPlus1: is erd0=0x0 {export R1;}\nrdPlus1: is erd0=0x2 {export R3;}\nrdPlus1: is erd0=0x4 {export R5;}\nrdPlus1: is erd0=0x6 {export R7;}\nrdPlus1: is erd0=0x8 {export R9;}\nrdPlus1: is erd0=0xa {export R11;}\nrdPlus1: is erd0=0xc {export SP;}\nrdPlus1: is erd0=0xe {export *[const]:4 inst_start;}#PC register\n\n#---------------------------------------------------------------------\n# ADDHH.W - Add Halfwords into Word\n# I. {d, x, y} -> {0, 1, ..., 15}\n# part -> {t,b}\n#---------------------------------------------------------------------\n# ADDHH.W Format I\n# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\tRd <- operand1 + operand2;\n# Syntax: addhh.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1110 00XY dddd\n# Assumption: t = 1, b = 0 using XY\n:ADDHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xe & eop6_2=0x0 & selectorxy4_2 & erd0)) & operand1 & operand2 {\n\terd0 = operand1 + operand2;\n\taddflags(operand1, operand2, erd0);\n }\n \n#---------------------------------------------------------------------\n# MACHH.D - Multiply Halfwords and Accumulate in Doubleword\n# I. d \t\t-> {0, 2, 4, ..., 14}\n#\t {x, y} \t-> {0, 1, ..., 15}\n# part \t-> {t,b}\n#---------------------------------------------------------------------\n# MACHH.D Format I\n# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\t(Rd+1:Rd)[63:16] <- (operand1*operand2)[31:0] + (Rd+1:Rd)[63:16];\n#\t\t\t\tRd[15:0] <- 0;\n# Syntax: machh.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0101 10XY dddd\n# Assumption: t = 1, b = 0 using XY\n:MACHH.D erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x5 & eop6_2=0x2 & selectorxy4_2 & erd0 & rdPlus1)) & operand1 & operand2 {\n\tmultAccumulate:8 = (zext(operand1 * operand2) + ((zext(rdPlus1) << 32) | (zext(erd0[16,16]) << 16)));\n\trdPlus1 = multAccumulate[32,32];\n\terd0 = ((zext(multAccumulate[16,16]) << 16) & 0xffff0000);\n}\n\n#---------------------------------------------------------------------\n# MACHH.W - Multiply Halfwords and Accumulate in Word\n# I. {d, x, y} -> {0, 1, ..., 15}\n# part \t -> {t,b}\n#---------------------------------------------------------------------\n# MACHH.W Format I\n# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\tRd <- (operand1*operand2) + Rd;\n# Syntax: machh.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0100 10XY dddd\n# Assumption: t = 1, b = 0 using XY\n:MACHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x4 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 {\n\tmultAccumulate:4 = ((operand1 * operand2) + erd0);\n\terd0 = multAccumulate;\n}\n\n#---------------------------------------------------------------------\n# MACWH.D - Multiply Word with Halfword and Accumulate in Doubleword\n# I. d \t\t-> {0, 2, 4, ..., 14}\n#\t {x, y} \t-> {0, 1, ..., 15}\n# part \t-> {t,b}\n#---------------------------------------------------------------------\n# MACWH.D Format I\n# Operation:\tOperand1 = Rx; \n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\t(Rd+1:Rd)[63:16] <- (operand1*operand2)[47:0] + (Rd+1:Rd)[63:16];\n#\t\t\t\tRd[15:0] <- 0;\n# Syntax: macwh.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1100 100Y dddd\n# Assumption: t = 1, b = 0 using Y\n:MACWH.D erd0, rx9, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xc & eop5_3=0x4 & selectorxy4_2 & erd0 & rdPlus1)) & operand2 {\n\tmult:6 = sext(rx9 * operand2);\n\tmultAccumulate:8 = (zext(mult) + ((zext(rdPlus1) << 32) | (zext(erd0[16,16]) << 16)));\n\trdPlus1 = multAccumulate[32,32];\n\terd0 = ((zext(multAccumulate[16,16]) << 16) & 0xffff0000);\n}\n\n#---------------------------------------------------------------------\n# MULHH.W - Multiply Halfwords with Halfword\n# I. {d, x, y} -> {0, 1, ..., 15}\n# part -> {t,b}\n#---------------------------------------------------------------------\n# MULHH.W Format I\n# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\tRd <- operand1 * operand2;\n# Syntax: mulhh.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0111 10XY dddd\n# Assumption: t = 1, b = 0 using XY\n:MULHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x7 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 {\n\terd0 = operand1 * operand2;\n }\n \n#---------------------------------------------------------------------\n# MULWH.D - Multiply Word with Halfword\n# I. d \t\t-> {0, 2, 4, ..., 14}\n#\t {x, y} \t-> {0, 1, ..., 15}\n# part \t-> {t,b}\n#---------------------------------------------------------------------\n# MULWH.D Format I\n# Operation:\tOperand1 = Rx; \n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\t(Rd+1:Rd)[63:16] <- (operand1*operand2);\n#\t\t\t\tRd[15:0] <- 0;\n# Syntax: mulwh.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1101 100Y dddd\n# Assumption: t = 1, b = 0 using Y\n:MULWH.D erd0, rx9, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xd & eop5_3=0x4 & selectorxy4_2 & erd0 & rdPlus1)) & operand2 {\n\tmultiply:8 = (sext(rx9 * operand2));\n\trdPlus1 = multiply[32,32];\n\terd0 = ((zext(multiply[16,16]) << 16) & 0xffff0000);\n}\n\n#---------------------------------------------------------------------\n# MULNHH.W - Multiply Halfwords with Negated Halfword\n# I. {d, x, y} -> {0, 1, ..., 15}\n# part -> {t,b}\n#---------------------------------------------------------------------\n# MULNHH.W Format I\n# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\tRd <- -(operand1 * operand2);\n# Syntax: mulnhh.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0001 10XY dddd\n# Assumption: t = 1, b = 0 using XY\n:MULNHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x1 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 {\n\tneg1:4 = 0xffffffff; \n\terd0 = (neg1 * (operand1 * operand2));\n }\n \n#---------------------------------------------------------------------\n# MULNWH.D - Multiply Word with Negated Halfword\n# I. d \t\t-> {0, 2, 4, ..., 14}\n#\t {x, y} \t-> {0, 1, ..., 15}\n# part \t-> {t,b}\n#---------------------------------------------------------------------\n# MULNWH.D Format I\n# Operation:\tOperand1 = Rx; \n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\t(Rd+1:Rd)[63:16] <- -(operand1*operand2);\n#\t\t\t\tRd[15:0] <- 0;\n# Syntax: mulnwh.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0010 100Y dddd\n# Assumption: t = 1, b = 0 using Y\n:MULNWH.D erd0, rx9, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x2 & eop5_3=0x4 & selectorxy4_2 & erd0 & rdPlus1)) & operand2 {\n\tneg1:8 = 0xffffffffffffffff;\n\tmultiply:8 = (neg1 * (sext(rx9 * operand2)));\n\trdPlus1 = multiply[32,32];\n\terd0 = ((zext(multiply[16,16]) << 16) & 0xffff0000);\n}\n\n\n#---------------------------------------------------------------------\n# SATADD.W - Saturated Add of Words\n# I. {d, x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\nmacro addSatWflags(RX, RY, TEMP, RD){\n\t#Q = (RX[31,1] && RY[31,1] && !TEMP[31,1]) ||\n\t# (!RX[31,1] && !RY[31,1] && TEMP[31,1]) || Q\n\tQ = sborrow(RX, RY);\n\t\n\t#V = (RX[31,1] && RY[31,1] && !TEMP[31,1]) ||\n\t# (!RX[31,1] && !RY[31,1] && TEMP[31,1])\n\tV = sborrow(RX, RY);\n\t\n\tNZSTATUS(RD);\n\t\n\tC = 0x0;\n}\n\n# SATADD.W Format I\n# Operation: temp <- Rx + Ry;\n#\t\t\t\tIf(Rx[31] && Ry[31] && ~temp[31]) || (~Rx[31] && ~Ry[31] && temp[31]) then\n#\t\t\t\t\tIf Rx[31] == 0 then\n#\t\t\t\t\t\tRd <- 0x7fffffff;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 0x80000000;\n# else\n#\t\t\t\t\t Rd <- temp;\n# Syntax: satadd.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0000 1100 dddd\n:SATADD.W erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0xc & erd0)) {\n\ttemp:4 = rx9 + ry0;\n\tlocal if_state_1 = ((rx9[31,1] && ry0[31,1] && ~temp[31,1]) || (~rx9[31,1] && ~ry0[31,1] && temp[31,1]));\n\tlocal if_state_2 = (rx9[31,1] == 0x0);\n\tlocal else_state_1 = !if_state_1;\n\tlocal else_state_2 = !if_state_2;\n\terd0 = ((zext(if_state_1 * if_state_2) * (0x7fffffff)) + (zext(if_state_1 * else_state_2) * (0x80000000)) + (zext(else_state_1) * temp));\n\taddSatWflags(rx9, ry0, temp, erd0);\n}\n\n\n#---------------------------------------------------------------------\n# SATADD.H - Saturated Add of HalfWords\n# I. {d, x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\nmacro addSatHflags(RX, RY, TEMP, RD){\n\t#Q = (RX[15,1] && RY[15,1] && !TEMP[15,1]) ||\n\t# (!RX[15,1] && !RY[15,1] && TEMP[15,1]) || Q\n\tQ = sborrow(RX[0,15], RY[0,15]);\n\t\n\t#V = (RX[15,1] && RY[15,1] && !TEMP[15,1]) ||\n\t# (!RX[15,1] && !RY[15,1] && TEMP[15,1])\n\tV = sborrow(RX[0,15], RY[0,15]);\n\t\n\tNZSTATUS(RD[0,15]);\n\t\n\tC = 0x0;\n}\n\n# SATADD.H Format I\n# Operation: temp <- Rx + Ry;\n#\t\t\t\tIf(Rx[31] && Ry[31] && ~temp[31]) || (~Rx[31] && ~Ry[31] && temp[31]) then\n#\t\t\t\t\tIf Rx[31] == 0 then\n#\t\t\t\t\t\tRd <- 0x00007fff;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 0xffff8000;\n# else\n#\t\t\t\t\t Rd <- temp;\n# Syntax: satadd.h Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0010 1100 dddd\n:SATADD.H erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0x2c & erd0)) {\n\ttemp:4 = zext(rx9[0,15]) + zext(ry0[0,15]);\n\tlocal if_state_1 = ((rx9[15,1] && ry0[15,1] && ~temp[15,1]) || (~rx9[15,1] && ~ry0[15,1] && temp[15,1]));\n\tlocal if_state_2 = (rx9[15,1] == 0x0);\n\tlocal else_state_1 = !if_state_1;\n\tlocal else_state_2 = !if_state_2;\n\terd0 = ((zext(if_state_1 * if_state_2) * (0x00007fff)) + (zext(if_state_1 * else_state_2) * (0xffff8000)) + (zext(else_state_1) * zext(temp[0,15])));\n\taddSatHflags(rx9, ry0, temp, erd0);\n}\n\n\n#---------------------------------------------------------------------\n# SATSUB.W - Saturated Subtract of Words\n# I. {d, x, y} -> {0, 1, ..., 15}\n# II. {d, s} -> {0, 1, ..., 15}\n# imm -> {-32768, -32767, ..., 32767}\n#---------------------------------------------------------------------\nmacro subSatWflags(OP1, OP2, TEMP, RD){\n\t#Q = (OP1[31,1] && !OP2[31,1] && !TEMP[31,1]) ||\n\t# (!OP1[31,1] && OP2[31,1] && TEMP[31,1]) || Q\n\tQ = sborrow(OP1, OP2);\n\t\n\t#V = (OP1[31,1] && !OP2[31,1] && !TEMP[31,1]) ||\n\t# (!OP1[31,1] && OP2[31,1] && TEMP[31,1])\n\tV = sborrow(OP1, OP2);\n\t\n\tNZSTATUS(RD);\n\t\n\tC = 0x0;\n}\n# SATSUB.W Format I\n# Operation: OP1 = Rx, OP2 = Ry\n#\t\t\t\ttemp <- Rx - Ry;\n#\t\t\t\tIf(OP1[31] && ~OP2[31] && ~temp[31]) || (~OP1[31] && OP2[31] && temp[31]) then\n#\t\t\t\t\tIf OP1[31] == 0 then\n#\t\t\t\t\t\tRd <- 0x7fffffff;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 0x80000000;\n# else\n#\t\t\t\t\t Rd <- temp;\n# Syntax: satsub.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0001 1100 dddd\n:SATSUB.W erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0x1c & erd0)) {\n\ttemp:4 = rx9 - ry0;\n\tlocal if_state_1 = ((rx9[31,1] && ~ry0[31,1] && ~temp[31,1]) || (~rx9[31,1] && ry0[31,1] && temp[31,1]));\n\tlocal if_state_2 = (rx9[31,1] == 0x0);\n\tlocal else_state_1 = !if_state_1;\n\tlocal else_state_2 = !if_state_2;\n\terd0 = ((zext(if_state_1 * if_state_2) * (0x7fffffff)) + (zext(if_state_1 * else_state_2) * (0x80000000)) + (zext(else_state_1) * temp));\n\tsubSatWflags(rx9, ry0, temp, erd0);\n}\n# SATSUB.W Format II\n# Operation: OP1 = Rx, OP2 = sext(imm16)\n#\t\t\t\ttemp <- Rx - Ry;\n#\t\t\t\tIf(OP1[31] && ~OP2[31] && ~temp[31]) || (~OP1[31] && OP2[31] && temp[31]) then\n#\t\t\t\t\tIf OP1[31] == 0 then\n#\t\t\t\t\t\tRd <- 0x7fffffff;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 0x80000000;\n# else\n#\t\t\t\t\t Rd <- temp;\n# Syntax: satsub.w Rd, Rx, Ry\n# 111x xxx0 1101 dddd iiii iiii iiii iiii\n:SATSUB.W rd0, rx9, simm16 is ((op13_3=0x7 & rx9 & op4_5=0xd & rd0) ; (simm16)) \n{\n\ttemp:4 = rx9 - simm16;\n\tsimm16Masked:4 = (simm16 & 0x80000000);\n\tlocal if_state_1 = ((rx9[31,1] && ~simm16Masked[31,1] && ~temp[31,1]) || (~rx9[31,1] && simm16Masked[31,1] && temp[31,1]));\n\tlocal if_state_2 = (rx9[31,1] == 0x0);\n\tlocal else_state_1 = !if_state_1;\n\tlocal else_state_2 = !if_state_2;\n\trd0 = ((zext(if_state_1 * if_state_2) * (0x7fffffff)) + (zext(if_state_1 * else_state_2) * (0x80000000)) + (zext(else_state_1) * temp));\n\tsubSatWflags(rx9, simm16, temp, rd0);\n}\n\n#---------------------------------------------------------------------\n# SATSUB.H - Saturated Subtract of Halfwords\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\nmacro subSatHflags(RX, RY, TEMP, RD){\n\t#Q = (RX[15,1] && !RY[15,1] && !TEMP[15,1]) ||\n\t# (!RX[15,1] && RY[15,1] && TEMP[15,1]) || Q\n\tQ = sborrow(RX[0,15], RY[0,15]);\n\t\n\t#V = (RX[15,1] && !RY[15,1] && !TEMP[15,1]) ||\n\t# (!RX[15,1] && RY[15,1] && TEMP[15,1])\n\tV = sborrow(RX[0,15], RY[0,15]);\n\t\n\tNZSTATUS(RD[0,15]);\n\t\n\tC = 0x0;\n}\n# SATSUB.H Format I\n# Operation: temp <- Rx - Ry;\n#\t\t\t\tIf(Rx[15] && ~Ry[15] && ~temp[15]) || (~Rx[15] && Ry[15] && temp[15]) then\n#\t\t\t\t\tIf Rx[15] == 0 then\n#\t\t\t\t\t\tRd <- 0x00007fff;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 0xffff8000;\n# else\n#\t\t\t\t\t Rd <- temp;\n# Syntax: satsub.h Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0011 1100 dddd\n:SATSUB.H erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0x3c & erd0)) {\n\ttemp:4 = zext(rx9[0,15]) - zext(ry0[0,15]);\n\tlocal if_state_1 = ((rx9[15,1] && ~ry0[15,1] && ~temp[15,1]) || (~rx9[15,1] && ry0[15,1] && temp[15,1]));\n\tlocal if_state_2 = (rx9[15,1] == 0x0);\n\tlocal else_state_1 = !if_state_1;\n\tlocal else_state_2 = !if_state_2;\n\terd0 = ((zext(if_state_1 * if_state_2) * (0x00007fff)) + (zext(if_state_1 * else_state_2) * (0xffff8000)) + (zext(else_state_1) * sext(temp[0,15])));\n\tsubSatHflags(rx9, ry0, temp, erd0);\n}\n\n#---------------------------------------------------------------------\n# SATRNDS - Saturate with Rounding Signed\n# I. {d} -> {0, 1, ..., 15}\n# {sa, bp} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x0) {RDMask:4 = (rd0 & 0x00000000); export RDMask;}#0 //sa should never be 0 for this if case!\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1) {RDMask:4 = (rd0 & 0x00000001); export RDMask;}#1\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x2) {RDMask:4 = (rd0 & 0x00000002); export RDMask;}#2\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x3) {RDMask:4 = (rd0 & 0x00000004); export RDMask;}#3\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x4) {RDMask:4 = (rd0 & 0x00000008); export RDMask;}#4\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x5) {RDMask:4 = (rd0 & 0x00000010); export RDMask;}#5\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x6) {RDMask:4 = (rd0 & 0x00000020); export RDMask;}#6\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x7) {RDMask:4 = (rd0 & 0x00000040); export RDMask;}#7\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x8) {RDMask:4 = (rd0 & 0x00000080); export RDMask;}#8\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x9) {RDMask:4 = (rd0 & 0x00000100); export RDMask;}#9\nSAMINUS1_CALC: is (rd0 ; esa0_5=0xa) {RDMask:4 = (rd0 & 0x00000200); export RDMask;}#10\nSAMINUS1_CALC: is (rd0 ; esa0_5=0xb) {RDMask:4 = (rd0 & 0x00000400); export RDMask;}#11\nSAMINUS1_CALC: is (rd0 ; esa0_5=0xc) {RDMask:4 = (rd0 & 0x00000800); export RDMask;}#12\nSAMINUS1_CALC: is (rd0 ; esa0_5=0xd) {RDMask:4 = (rd0 & 0x00001000); export RDMask;}#13\nSAMINUS1_CALC: is (rd0 ; esa0_5=0xe) {RDMask:4 = (rd0 & 0x00002000); export RDMask;}#14\nSAMINUS1_CALC: is (rd0 ; esa0_5=0xf) {RDMask:4 = (rd0 & 0x00004000); export RDMask;}#15\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x10) {RDMask:4 = (rd0 & 0x00008000); export RDMask;}#16\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x11) {RDMask:4 = (rd0 & 0x00010000); export RDMask;}#17\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x12) {RDMask:4 = (rd0 & 0x00020000); export RDMask;}#18\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x13) {RDMask:4 = (rd0 & 0x00040000); export RDMask;}#19\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x14) {RDMask:4 = (rd0 & 0x00080000); export RDMask;}#20\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x15) {RDMask:4 = (rd0 & 0x00100000); export RDMask;}#21\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x16) {RDMask:4 = (rd0 & 0x00200000); export RDMask;}#22\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x17) {RDMask:4 = (rd0 & 0x00400000); export RDMask;}#23\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x18) {RDMask:4 = (rd0 & 0x00800000); export RDMask;}#24\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x19) {RDMask:4 = (rd0 & 0x01000000); export RDMask;}#25\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1a) {RDMask:4 = (rd0 & 0x02000000); export RDMask;}#26\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1b) {RDMask:4 = (rd0 & 0x04000000); export RDMask;}#27\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1c) {RDMask:4 = (rd0 & 0x08000000); export RDMask;}#28\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1d) {RDMask:4 = (rd0 & 0x10000000); export RDMask;}#29\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1e) {RDMask:4 = (rd0 & 0x20000000); export RDMask;}#30\nSAMINUS1_CALC: is (rd0 ; esa0_5=0x1f) {RDMask:4 = (rd0 & 0x40000000); export RDMask;}#31\n\nGET_TEMP_FINAL_VAL: is (rd0 ; esa0_5) & SAMINUS1_CALC \n{\t\n\tsa:4 = (esa0_5 & 0xffffffff);\n\tlocal if_state_1 = (sa != 0x0);\n\ttempRDShiftTempVal:4 = rd0 >> esa0_5;\n\tRnd:4 = SAMINUS1_CALC;\n\ttempRDShiftFinalVal:4 = (tempRDShiftTempVal + (zext(if_state_1) * Rnd));\n\texport tempRDShiftFinalVal;\n}\n\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x0 & esa0_5)){ if_state_2_calc:1 = 0x1; export if_state_2_calc;}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1 & esa0_5)) & GET_TEMP_FINAL_VAL\n{\ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,1]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x2 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,2]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x3 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,3]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x4 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,4]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x5 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,5]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x6 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,6]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x7 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,7]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x8 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,8]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x9 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,9]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xa & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,10]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xb & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,11]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xc & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,12]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xd & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,13]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xe & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,14]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xf & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,15]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x10 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,16]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x11 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,17]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x12 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,18]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x13 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,19]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x14 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,20]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x15 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 =sext(tempRDShiftFinal[0,21]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x16 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,22]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x17 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,23]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x18 & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,24]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x19 & esa0_5)) & GET_TEMP_FINAL_VAL #?NOT SURE WHY I\"M GETTING \"Unnecessary SEXT warning from here on?\n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,25];#sext(tempRDShiftFinal[0,25]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1a & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,26];#sext(tempRDShiftFinal[0,26]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1b & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,27];#sext(tempRDShiftFinal[0,27]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1c & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,28];#sext(tempRDShiftFinal[0,28]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1d & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,29];#sext(tempRDShiftFinal[0,29]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1e & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,30];#sext(tempRDShiftFinal[0,30]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1f & esa0_5)) & GET_TEMP_FINAL_VAL \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,31]; \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\n\n\n# SATRNDS Format I\n# Operation: temp <- Rd >> sa;\n#\t\t\t\tif(sa != 0)\n#\t\t\t\t\tRnd = Rd[sa - 1];\n#\t\t\t\t\ttemp = temp + Rnd;\n#\t\t\t\tif((temp == sext(temp[bp - 1:0])) || (bp == 0))\n#\t\t\t\t\tRd <- temp;\n# else\n#\t\t\t\t\tif(temp[31] == 1)\n#\t\t\t\t\t\tRd <- -2^(bp - 1);\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 2^(bp - 1);\n# Syntax: satrnds Rd >> sa, bp\n# 1111 0011 1011 dddd 0000 00bb bbbs ssss (where b = bp, s = sa)\n:SATRNDS rd0^\"<<\"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x9 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x0 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC & GET_TEMP_FINAL_VAL {\n\tbp:4 = (ebp5_5 & 0xffffffff);\n\tbpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff);\n\tlocal if_state_2 = GET_IF_STATE2_CALC;\n\ttemp:4 = GET_TEMP_FINAL_VAL;\n\tlocal if_state_3 = (temp[31,1] == 1);\n\tbpM1SecondPowerNeg:4 = ((-2)**bpMinus1);\n\tbpM1SecondPowerPos:4 = (2**bpMinus1);\n\tlocal else_state_2 = !if_state_2;\n\tlocal else_state_3 = !if_state_3;\n\trd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * bpM1SecondPowerNeg) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos));\n}\n\n#---------------------------------------------------------------------\n# SATRNDU - Saturate with Rounding Unsigned\n# I. {d} -> {0, 1, ..., 15}\n# {sa, bp} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n# SATRNDU Format I\n# Operation: temp <- Rd >> sa;\n#\t\t\t\tif(sa != 0)\n#\t\t\t\t\tRnd = Rd[sa - 1];\n#\t\t\t\t\ttemp = temp + Rnd;\n#\t\t\t\tif((temp == zext(temp[bp - 1:0])) || (bp == 0))\n#\t\t\t\t\tRd <- temp;\n# else\n#\t\t\t\t\tif(temp[31] == 1)\n#\t\t\t\t\t\tRd <- 0x00000000;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 2^(bp - 1);\n# Syntax: satrndu Rd >> sa, bp\n# 1111 0011 1011 dddd 0000 01bb bbbs ssss (where b = bp, s = sa)\n:SATRNDU rd0^\"<<\"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x9 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x1 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC & GET_TEMP_FINAL_VAL {\n\tbp:4 = (ebp5_5 & 0xffffffff);\n\tbpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff);\n\tlocal if_state_2 = GET_IF_STATE2_CALC;\n\ttemp:4 = GET_TEMP_FINAL_VAL;\n\tlocal if_state_3 = (temp[31,1] == 1);\n\tzero32BitVal:4 = 0x00000000;\n\tbpM1SecondPowerPos:4 = (2**bpMinus1);\n\tlocal else_state_2 = !if_state_2;\n\tlocal else_state_3 = !if_state_3;\n\trd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * zero32BitVal) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos));\n}\n\n#---------------------------------------------------------------------\n# SATS - Saturate Signed\n# I. {d} -> {0, 1, ..., 15}\n# {sa, bp} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\nGET_TEMP_FINAL_VAL_NR: is (rd0 ; esa0_5) & SAMINUS1_CALC \n{\t\n\ttempRDShiftFinalVal:4 = rd0 >> esa0_5;\n\texport tempRDShiftFinalVal;\n}\n\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x0 & esa0_5)){ if_state_2_calc:1 = 0x1; export if_state_2_calc;}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1 & esa0_5)) & GET_TEMP_FINAL_VAL_NR\n{\ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,1]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x2 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,2]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x3 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,3]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x4 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,4]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x5 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,5]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x6 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,6]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x7 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,7]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x8 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,8]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x9 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,9]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xa & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,10]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xb & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,11]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xc & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,12]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xd & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,13]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xe & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,14]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xf & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,15]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x10 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,16]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x11 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,17]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x12 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,18]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x13 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,19]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x14 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,20]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x15 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 =sext(tempRDShiftFinal[0,21]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x16 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,22]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x17 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,23]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x18 & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,24]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x19 & esa0_5)) & GET_TEMP_FINAL_VAL_NR #?NOT SURE WHY I\"M GETTING \"Unnecessary SEXT warning from here on?\n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,25];#sext(tempRDShiftFinal[0,25]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1a & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,26];#sext(tempRDShiftFinal[0,26]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1b & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,27];#sext(tempRDShiftFinal[0,27]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1c & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,28];#sext(tempRDShiftFinal[0,28]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1d & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,29];#sext(tempRDShiftFinal[0,29]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1e & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,30];#sext(tempRDShiftFinal[0,30]); \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\nGET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1f & esa0_5)) & GET_TEMP_FINAL_VAL_NR \n{ \ttempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR;\n\ttempRDShiftFinalMask:4 = tempRDShiftFinal[0,31]; \n\tlocal if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; \n}\n#SATS Format I\n#Operation: \ttemp <- Rd >> sa;\n#\t\t\t\tif((temp == sext(temp[bp - 1:0])) || (bp == 0))\n#\t\t\t\t\tRd <- temp;\n# else\n#\t\t\t\t\tif(temp[31] == 1)\n#\t\t\t\t\t\tRd <- -2^(bp - 1);\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 2^(bp - 1);\n# Syntax: sats Rd >> sa, bp\n# 1111 0001 1011 dddd 0000 00bb bbbs ssss (where b = bp, s = sa)\n:SATS rd0^\"<<\"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x8 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x0 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC_NR & GET_TEMP_FINAL_VAL_NR {\nbp:4 = (ebp5_5 & 0xffffffff);\n\tbpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff);\n\tlocal if_state_2 = GET_IF_STATE2_CALC_NR;\n\ttemp:4 = GET_TEMP_FINAL_VAL_NR;\n\tlocal if_state_3 = (temp[31,1] == 1);\n\tbpM1SecondPowerNeg:4 = ((-2)**bpMinus1);\n\tbpM1SecondPowerPos:4 = (2**bpMinus1);\n\tlocal else_state_2 = !if_state_2;\n\tlocal else_state_3 = !if_state_3;\n\trd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * bpM1SecondPowerNeg) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos));\n}\n\n#---------------------------------------------------------------------\n# SATU - Saturate Unsigned\n# I. {d} -> {0, 1, ..., 15}\n# {sa, bp} -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n# SATU Format I\n# Operation: temp <- Rd >> sa;\n#\t\t\t\tif((temp == zext(temp[bp - 1:0])) || (bp == 0))\n#\t\t\t\t\tRd <- temp;\n# else\n#\t\t\t\t\tif(temp[31] == 1)\n#\t\t\t\t\t\tRd <- 0x00000000;\n#\t\t\t\t\telse\n#\t\t\t\t\t\tRd <- 2^(bp - 1);\n# Syntax: satrndu Rd >> sa, bp\n# 1111 0011 1011 dddd 0000 01bb bbbs ssss (where b = bp, s = sa)\n:SATU rd0^\"<<\"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x8 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x1 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC_NR & GET_TEMP_FINAL_VAL_NR {\n\tbp:4 = (ebp5_5 & 0xffffffff);\n\tbpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff);\n\tlocal if_state_2 = GET_IF_STATE2_CALC_NR;\n\ttemp:4 = GET_TEMP_FINAL_VAL_NR;\n\tlocal if_state_3 = (temp[31,1] == 1);\n\tzero32BitVal:4 = 0x00000000;\n\tbpM1SecondPowerPos:4 = (2**bpMinus1);\n\tlocal else_state_2 = !if_state_2;\n\tlocal else_state_3 = !if_state_3;\n\trd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * zero32BitVal) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos));\n}\n\n#---------------------------------------------------------------------\n# SUBHH.W - Subtract Halfwords into Word\n# I. {d, x, y} -> {0, 1, ..., 15}\n# part -> {t, b}\n#---------------------------------------------------------------------\n# SUBHH.W Format I\n# Operation:\tIf(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\tRd <- operand1 - operand2;\n# Syntax: subhh.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1111 00XY dddd\n# Assumption: t = 1, b = 0 using XY\n:SUBHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xf & eop6_2=0x0 & selectorxy4_2 & erd0)) & operand1 & operand2 {\n\terd0 = operand1 - operand2;\n\tsubflags(operand1, operand2, erd0);\n }\n \n \n#---------------------------------------------------------------------\n# MULSATHH.W - Multiply Halfwords with Saturation into Halfword\n# I. {d, x, y} -> {0, 1, ..., 15}\n# part -> {t, b}\n#---------------------------------------------------------------------\n# MULSATHH.W Format I\n# Operation:\tIf(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]);\n#\t\t\t\tIf(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]);\n#\t\t\t\tIf(operand1 == operand2 == 0x8000)\t\n#\t\t\t\t\tRd <- 0x7FFF;\n#\t\t\t\telse\n#\t\t\t\t\tRd <- sext((operand1 * operand2) >> 15);\n# Syntax: mulsahh.w Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1000 10XY dddd\n# Assumption: t = 1, b = 0 using XY\n:MULSATHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x8 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 {\n\tcompareValx8000:4 = 0x8000;\n\tlocal if_state_3_a = (operand1 == compareValx8000);\n\tlocal if_state_3_b = (operand2 == compareValx8000);\n\tlocal if_state_3 = (if_state_3_a == if_state_3_b);\n\tlocal else_state_3 = !if_state_3;\n\tsat_clamp_val:4 = 0x7FFF;\n\tnonSatMultVal:4 = ((operand1 * operand2) >> 15);\n\terd0 = ((zext(if_state_3) * sat_clamp_val) + (zext(else_state_3) * nonSatMultVal));\n\t\n }\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_dsp_operations2.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.4 DSP Operations\n#\n# Note: all DSP operations are stubbed out with custom pcode ops,\n# because their literal implementations are generally too difficult.\n#---------------------------------------------------------------------\n\nmacro satdspmulh(OP1, OP2, RES, RND, TMP1) {\n TMP1 = (OP1 == 0x8000) & (OP2 == 0x8000);\n Q = Q | TMP1;\n RES = (zext(TMP1) * 0x3FFF8000) + (zext(TMP1 == 0) * ((sext(OP1) * sext(OP2)) + zext(RND)));\n}\n\nmacro satdspsh(RES) {\n\tV = (RES s> 0x00007FFF) | (RES s< 0xFFFF8000);\n\tQ = V | Q;\n\tRES = (0x00007FFF * zext(RES s> 0x00007FFF)) + (RES * zext(RES s< 0x00008000) * zext(RES s>= 0xFFFF8000)) + (0x00008000 * zext(RES s< 0xFFFF8000));\n}\n\nmacro satdspsw(RES) {\n\tV = (RES s> 0x000000007FFFFFFF) | (RES s< 0xFFFFFFFF80000000);\n\tQ = V | Q;\n\tRES = (0x000000007FFFFFFF * zext(RES s> 0x000000007FFFFFFF)) + (RES * zext(RES s< 0x0000000080000000) * zext(RES s>= 0xFFFFFFFF80000000)) + (0x0000000080000000 * zext(RES s< 0xFFFFFFFF80000000));\n}\n\n\nXPART: \":T\" is ctx_usex & xpart=0x1 {\n\ttmp:4 = ctx_usex;\n\ttmp = tmp >> 16;\n\ttmpa:2 = tmp:2;\n\ttmpb:4 = sext(tmpa);\n\texport *:4 tmpb;\n}\n\nXPART: \":B\" is ctx_usex & xpart=0x0 { \n\ttmp:4 = ctx_usex;\n\ttmp = tmp & 0xFFFF;\n\ttmpa:2 = tmp:2;\n\ttmpb:4 = sext(tmpa);\n\texport *:4 tmpb;\n}\n\nYPART: \":T\" is ctx_usey & ypart=0x1 { \n\ttmp:4 = ctx_usey;\n\ttmp = tmp >> 16;\n\ttmpa:2 = tmp:2;\n\ttmpb:4 = sext(tmpa);\n\texport *:4 tmpb;\n}\n\nYPART: \":B\" is ctx_usey & ypart=0x0 { \n\ttmp:4 = ctx_usey;\n\ttmp = tmp & 0xFFFF;\n\ttmpa:2 = tmp:2;\n\ttmpb:4 = sext(tmpa);\n\texport *:4 tmpb;\n}\n\n:ADDHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x38 & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ]\n{\n\terd0 = XPART + YPART;\n addflags(XPART, YPART, erd0);\t\n}\n\n\n:MACHH.D erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x16 & XPART & YPART & erd0 & erd0a & ctx_rdplus [ctx_savex=rx9; ctx_savey=ry0; ctx_rdsave=erd0a+1; ]\n{\n\ttmp:4 = XPART * YPART;\n\ttmp64a:8 = zext(tmp);\n\ttmp64b:8 = zext(erd0);\n\ttmp64c:8 = zext(ctx_rdplus);\n\ttmp64b = (tmp64c << 32) | tmp64b;\n\ttmp64a = (tmp64a << 16) + tmp64b;\n\ttmp64b = tmp64a >> 32;\n\terd0 = tmp64a:4 & 0xFFFF0000;\n\tctx_rdplus= tmp64b:4;\n}\n\n\n:MACHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x12 & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ]\n{ \n\terd0 = erd0 + (XPART * YPART);\n}\n\n:MACSATHH.W erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x1a & PXPART & PYPART & erd0\n{ \n\tTMPX:2 = PXPART;\n\tTMPY:2 = PYPART;\n\tRES:4 = 0;\n\tRND:2 = 0;\n\tTMP:1 = 0;\n\tsatdspmulh(TMPX,TMPY,RES,RND,TMP);\n\tRES = RES << 1;\n\tBIG:8 = sext(RES) + sext(erd0);\n\tsatdspsw(BIG);\n\tQTOSR();\n}\n\n\n:MACWH.D erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop5_11=0x64 & YPART & erd0 & erd0a & ctx_rdplus [ctx_savey=ry0; ctx_rdsave=erd0a+1; ]\n{\n\ttmp64a:8 = sext(rx9);\n\ttmp64b:8 = sext(YPART);\n\ttmp64a = tmp64a * tmp64b;\n\ttmp64b = zext(ctx_rdplus);\n\ttmp64c:8 = zext(erd0);\n\ttmp64b = (tmp64b << 32) | tmp64c;\n\ttmp64b = tmp64b + (tmp64a << 16);\n\ttmp64a = tmp64b >> 32;\n\terd0 = tmp64b:4 & 0xFFFF0000;\n\tctx_rdplus = tmp64a:4;\n}\n\n\n:MULHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x1e & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ]\n{\n\terd0 = XPART * YPART;\n}\n\n:MULNHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x6 & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ]\n{\n\terd0 = XPART * YPART;\n\tif (erd0 == 0) goto inst_next;\n\terd0 = (~erd0) + 1;\n}\n\n:MULNWH.D erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop5_11=0x14 & YPART & erd0 & erd0a & ctx_rdplus [ctx_savey=ry0; ctx_rdsave=erd0a+1; ]\n{\n\ttmp64a:8 = sext(rx9);\n\ttmp64b:8 = sext(YPART);\n\ttmp64a = tmp64a * tmp64b;\n\terd0 = 0;\n\tctx_rdplus = 0;\n\tif (tmp64a == 0) goto inst_next;\n\ttmp64a = (~tmp64a) + 1;\n\terd0 = tmp64a:4;\n\terd0 = erd0 << 16;\n\ttmp64a = tmp64a s>> 16;\n\tctx_rdplus = tmp64a:4;\t\n}\n\n:MULSATHH.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x22 & PXPART & PYPART & erd0\n{ \n\tTMPX:2 = PXPART;\n\tTMPY:2 = PYPART;\n\tRES:4 = 0;\n\tRND:2 = 0;\n\tTMP:1 = 0;\n\tsatdspmulh(TMPX,TMPY,RES,RND,TMP);\n\tRES = RES >> 15;\n\terd0 = sext(RES:2);\n\tQTOSR();\n}\n\n\n:MULSATHH.W erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x26 & PXPART & PYPART & erd0\n{ \n\tTMPX:2 = PXPART;\n\tTMPY:2 = PYPART;\n\tRES:4 = 0;\n\tRND:2 = 0;\n\tTMP:1 = 0;\n\tsatdspmulh(TMPX,TMPY,RES,RND,TMP);\n\terd0 = RES << 1;\n\tQTOSR();\n}\n\n\n:MULSATRNDHH.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x2a & PXPART & PYPART & erd0\n{ \n\tTMPX:2 = PXPART;\n\tTMPY:2 = PYPART;\n\tRES:4 = 0;\n\tRND:2 = 0x4000;\n\tTMP:1 = 0;\n\tsatdspmulh(TMPX,TMPY,RES,RND,TMP);\n\tRES = RES >> 15;\n\terd0 = sext(RES:2);\n\tQTOSR();\n}\n\n:MULSATRNDWH.W erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop5_11=0x5c & YPART & erd0\n{\n\tSAT:1 = (rx9 == 0x80000000) && (YPART == 0xFFFF8000);\n\tTMP:8 = ((sext(rx9) * sext(YPART)) + 0x4000) s>> 15;\n\terd0 = (zext(SAT) * 0x7FFFFFFF) + zext(SAT == 0) * TMP:4; \n}\n\n\n:MULSATWH.W erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop5_11=0x74 & YPART & erd0\n{ \n\tSAT:1 = (rx9 == 0x80000000) && (YPART == 0xFFFF8000);\n\tTMP:8 = (sext(rx9) * sext(YPART)) s>> 15;\n\terd0 = (zext(SAT) * 0x7FFFFFFF) + zext(SAT == 0) * TMP:4; \n}\n\n\n:MULWH.D erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop5_11=0x6c & YPART & erd0 & erd0a & ctx_rdplus [ctx_savey=ry0; ctx_rdsave=erd0a+1; ]\n{\n\ttmp64a:8 = sext(rx9);\n\ttmp64b:8 = sext(YPART);\n\ttmp64a = tmp64a * tmp64b;\n\terd0 = tmp64a:4;\n\terd0 = erd0 << 16;\n\ttmp64a = tmp64a s>> 16;\n\tctx_rdplus = tmp64a:4;\t\t\n}\n\n:SATADD.H erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop4_12=0x2c & erd0\n{\n\tTMP:4 = zext(rx9:2) + zext(ry0:2);\n\tsatdspsh(TMP);\n\terd0 = sext(TMP:2);\n\tN = (erd0 & 0x8000) != 0;\n\tZ = (erd0 == 0);\n\tC = 0;\n\tCZNVQTOSR();\n}\n\n\n:SATADD.W erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop4_12=0xc & erd0\n{ \n\tTMP:8 = zext(rx9) + zext(ry0);\n\tsatdspsw(TMP);\n\terd0 = TMP:4;\n\tN = (erd0 & 0x80000000) != 0;\n\tZ = (erd0 == 0);\n\tC = 0;\n\tCZNVQTOSR();\n}\n\n\n\n\nSATM:\tis ebp5_5=0 { tmp:4 = 0x00000000; export tmp; }\nSATM:\tis ebp5_5=1 { tmp:4 = 0xFFFFFFFF; export tmp; }\nSATM:\tis ebp5_5=2 { tmp:4 = 0xFFFFFFFE; export tmp; }\nSATM:\tis ebp5_5=3 { tmp:4 = 0xFFFFFFFC; export tmp; }\nSATM:\tis ebp5_5=4 { tmp:4 = 0xFFFFFFF8; export tmp; }\nSATM:\tis ebp5_5=5 { tmp:4 = 0xFFFFFFF0; export tmp; }\nSATM:\tis ebp5_5=6 { tmp:4 = 0xFFFFFFE0; export tmp; }\nSATM:\tis ebp5_5=7 { tmp:4 = 0xFFFFFFC0; export tmp; }\nSATM:\tis ebp5_5=8 { tmp:4 = 0xFFFFFF80; export tmp; }\nSATM:\tis ebp5_5=9 { tmp:4 = 0xFFFFFF00; export tmp; }\nSATM:\tis ebp5_5=10 { tmp:4 = 0xFFFFFE00; export tmp; }\nSATM:\tis ebp5_5=11 { tmp:4 = 0xFFFFFC00; export tmp; }\nSATM:\tis ebp5_5=12 { tmp:4 = 0xFFFFF800; export tmp; }\nSATM:\tis ebp5_5=13 { tmp:4 = 0xFFFFF000; export tmp; }\nSATM:\tis ebp5_5=14 { tmp:4 = 0xFFFFE000; export tmp; }\nSATM:\tis ebp5_5=15 { tmp:4 = 0xFFFFC000; export tmp; }\nSATM:\tis ebp5_5=16 { tmp:4 = 0xFFFF8000; export tmp; }\nSATM:\tis ebp5_5=17 { tmp:4 = 0xFFFF0000; export tmp; }\nSATM:\tis ebp5_5=18 { tmp:4 = 0xFFFE0000; export tmp; }\nSATM:\tis ebp5_5=19 { tmp:4 = 0xFFFC0000; export tmp; }\nSATM:\tis ebp5_5=20 { tmp:4 = 0xFFF80000; export tmp; }\nSATM:\tis ebp5_5=21 { tmp:4 = 0xFFF00000; export tmp; }\nSATM:\tis ebp5_5=22 { tmp:4 = 0xFFE00000; export tmp; }\nSATM:\tis ebp5_5=23 { tmp:4 = 0xFFC00000; export tmp; }\nSATM:\tis ebp5_5=24 { tmp:4 = 0xFF800000; export tmp; }\nSATM:\tis ebp5_5=25 { tmp:4 = 0xFF000000; export tmp; }\nSATM:\tis ebp5_5=26 { tmp:4 = 0xFE000000; export tmp; }\nSATM:\tis ebp5_5=27 { tmp:4 = 0xFC000000; export tmp; }\nSATM:\tis ebp5_5=28 { tmp:4 = 0xF8000000; export tmp; }\nSATM:\tis ebp5_5=29 { tmp:4 = 0xF0000000; export tmp; }\nSATM:\tis ebp5_5=30 { tmp:4 = 0xE0000000; export tmp; }\nSATM:\tis ebp5_5=31 { tmp:4 = 0xC0000000; export tmp; }\n\n:SATRNDS rd0^\" >> \"^esa0_5, ebp5_5^SATM is op4_12=0xf3b & rd0 ;\n eop10_6=0x0 & esa0_5 & ebp5_5 & SATM\n{ \n\tbuild SATM;\n\tBIT:1 = ebp5_5;\n\tBITA:1 = esa0_5;\n\tTMP:4 = rd0 s>> esa0_5;\n\tTMP = TMP + (zext(BITA != 0) * (rd0 & (1 << (esa0_5 - 1))));\n\tTMPA:4 = TMP << (32-ebp5_5);\n\tTMPB:4 = TMPA s>> (32-ebp5_5);\n\tNSAT:1 = (TMP == TMPB) || (BIT == 0x0);\n\tTMPC:1 = (TMP & 0x80000000) != 0;\n\trd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * ((zext(TMPC) * SATM) + ((1 << (ebp5_5-1) - 1) * zext(TMPC == 0)))); \n\tQ = Q || (NSAT != 0);\n\tQTOSR();\n}\n\n\n:SATRNDU rd0^\" >> \"^esa0_5, ebp5_5 is op4_12=0xf3b & rd0 ;\n eop10_6=0x1 & esa0_5 & ebp5_5\n{ \n\tBIT:1 = ebp5_5;\n\tBITA:1 = esa0_5;\n\tTMP:4 = rd0 >> esa0_5;\n\tTMP = TMP + (zext(BITA != 0) * (rd0 & (1 << (esa0_5 - 1))));\n\tTMPA:4 = TMP << (32-ebp5_5);\n\tTMPB:4 = TMPA >> (32-ebp5_5);\n\tNSAT:1 = (TMP == TMPB) || (BIT == 0x0);\n\tTMPC:1 = (TMP & 0x80000000) == 0;\n\trd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * zext(TMPC) * ((1 << ebp5_5) - 1));\n\tQ = Q || (NSAT != 0);\n\tQTOSR();\n}\n\n:SATS rd0^\" >> \"^esa0_5, ebp5_5^SATM is op4_12=0xf1b & rd0 ;\n eop10_6=0x0 & esa0_5 & ebp5_5 & SATM\n{\n\tbuild SATM;\n\tBIT:1 = ebp5_5;\n\tTMP:4 = rd0 s>> esa0_5;\n\tTMPA:4 = TMP << (32-ebp5_5);\n\tTMPB:4 = TMPA s>> (32-ebp5_5);\n\tNSAT:1 = (TMP == TMPB) || (BIT == 0x0);\n\tTMPC:1 = (TMP & 0x80000000) != 0;\n\trd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * ((zext(TMPC) * SATM) + ((1 << (ebp5_5-1) - 1) * zext(TMPC == 0)))); \n\tQ = Q || (NSAT != 0);\n\tQTOSR();\n}\n\n\n:SATSUB.H erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop4_12=0x3c & erd0\n{ \n\tTMP:4 = zext(rx9:2) - zext(ry0:2);\n\tsatdspsh(TMP);\n\terd0 = sext(TMP:2);\n\tN = (erd0 & 0x8000) != 0;\n\tZ = (erd0 == 0);\n\tC = 0;\n\tCZNVQTOSR();\n}\n\n:SATSUB.W erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop4_12=0x1c & erd0\n{ \n\tTMP:8 = zext(rx9) - zext(ry0);\n\tsatdspsw(TMP);\n\terd0 = TMP:4;\n\tN = (erd0 & 0x80000000) != 0;\n\tZ = (erd0 == 0);\n\tC = 0;\n\tCZNVQTOSR();\n}\n\n:SATSUB.W rd0, rs9, simm16 is op13_3=0x7 & op4_5=0xd & rd0 & rs9 ; \n simm16\n{ \n\tTMPY:2 = simm16;\n\tTMP:8 = zext(rs9) - sext(TMPY);\n\tsatdspsw(TMP);\n\trd0 = TMP:4;\n\tN = (rd0 & 0x80000000) != 0;\n\tZ = (rd0 == 0);\n\tC = 0;\n\tCZNVQTOSR();\n}\n\n\n:SATU rd0^\" >> \"^esa0_5, ebp5_5 is op4_12=0xf1b & rd0 ;\n eop10_6=0x1 & esa0_5 & ebp5_5\n{\n\tBIT:1 = ebp5_5;\n\tTMP:4 = rd0 >> esa0_5;\n\tTMPA:4 = TMP << (32-ebp5_5);\n\tTMPB:4 = TMPA >> (32-ebp5_5);\n\tNSAT:1 = (TMP == TMPB) || (BIT == 0x0);\n\tTMPC:1 = (TMP & 0x80000000) == 0;\n\trd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * zext(TMPC) * ((1 << ebp5_5) - 1));\n\tQ = Q || (NSAT != 0);\n\tQTOSR();\n}\n\n\n:SUBHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;\n eop6_10=0x3c & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ]\n{\n\terd0 = XPART - YPART;\n subflags(XPART, YPART, erd0);\t\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_instruction_flow.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.8 INSTRUCTION FLOW\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# ACALL - Application Call\n# I. disp -> {0, 4, ..., 1020}\n#---------------------------------------------------------------------\n\n# ACALL Format I:\n# Operation: LR <- PC + 2\n# Syntax: acall disp\n# 1101 nnnn nnnn 0000\n\nACALLdisp: disp is disp4_8 [ disp = ACBA + (disp4_8 << 2); ] { export *:4 disp; }\n\n:ACALL ACALLdisp is op12_4=0xd & op0_4=0 & ACALLdisp\n{\n LR = inst_next;\n call ACALLdisp;\n}\n \n#---------------------------------------------------------------------\n# RET{cond4} - Conditional Return from Subroutine\n# I.\tcond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}\n#\t\ts -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\nretCond4Sub: rs0 is rs0 & rs0=0xf { R12 = 0x1;}\t\t#PC (0xf)\nretCond4Sub: rs0 is rs0 & rs0=0xe { R12 = -0x1;}\t#LR (0xe)\nretCond4Sub: rs0 is rs0 & rs0=0xd { R12 = 0x0;}\t\t#SP (0xd)\nretCond4Sub: rs0 is rs0 & rs0=0xc {} #Else R12 is R12\nretCond4Sub: rs0 is rs0 {R12 = rs0;} #Else\t\t\n\n\n#RET{Cond4} Format I:\n#Operation:\n#\tConditional return from subroutine with move and test of return value:\n#\tif (Rs != {LR, SP, PC})\n#\t\tR12 <- Rs\n#\t\tPC <- LR\n#\tConditional return from subroutine with return of false value:\n#\telse if (Rs == LR)\n#\t\tR12 <- -1\n#\t\tPC <- LR\n#\tConditional return from subroutine with return of false value:\n#\telse if (Rs == SP)\n#\t\tR12 <- 0\n#\t\tPC <- LR\n#\tConditional return from subroutine with return of true value:\n#\telse if (Rs == PC)\n#\t\tR12 <- 1\n#\t\tPC <- LR\n#Syntax: \tret{cond4} Rs\n#010 1111 0 CCCC ssss\n#0101 1110 CCCC ssss\n:RET^{COND_4_4} retCond4Sub is op13_3=0x2 & op9_4=0xf & op8_1 = 0x0 & COND_4_4 & retCond4Sub {\n\t# Test Condition\n\tbuild COND_4_4;\n\tbuild retCond4Sub;\n\t# Flags Set:\n\tV = 0x0; \t\n\tC = 0x0;\n\tNZSTATUS(R12);\n\t# End Operation:\n\t#PC = LR;\n\treturn [ LR ];\n}\n\n#---------------------------------------------------------------------\n# BR{cond} - Branch if Condition Satisfied\n# I. \tcond3 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl}\n# \t\tdisp -> {-256, -254, ..., 254}\n# II. \tcond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}\n#\t\tdisp -> {-2097152, -2097150, ..., 2097150}\n#---------------------------------------------------------------------\n\nsDisp8: sdisp is sdisp4_8\n[ sdisp = inst_start + (sdisp4_8 << 1); ]\n{\n export *:4 sdisp;\n}\n\nsDisp21: sdisp21 is disp21part2_4_1 & disp21part3_9_4; disp21part1_0_16\n[ sdisp21 = inst_start + (((disp21part3_9_4 << 17) | (disp21part2_4_1 << 16) | disp21part1_0_16) << 1); ]\n{\n export *:4 sdisp21;\n}\n\n#BR{cond3} Format I:\n#Operation:\n#\tBranch if condition satisfied:\n#\tif(cond3)\n#\t\tPC <- PC + (SE(disp8)<<1)\n#\telse\n#\t\tPC <- PC + 2;\n#Syntax:\tbr{cond3}disp\n#110 0 nnnnnnnn 0 CCC\n#1100 nnnn nnnn 0CCC\n\n\n:BR^{COND_3} sDisp8 is op13_3=0x6 & op12_1=0x0 & op3_1 = 0x0 & COND_3 & sDisp8\n{\n\ttst:1 = COND_3;\n\tif (tst) goto sDisp8;\n}\n \n#BR{cond4} Format II:\n#Operation:\n#\tBranch if condition satisfied:\n#\tif(cond4)\n#\t\tPC <- PC + (SE(disp21)<<1)\n#\telse\n#\t\tPC <- PC + 4;\n#Syntax:\tbr{cond3}disp\n#111 nnnn 0100 n CCCC nnnnnnnnnnnnnnnn\n#111n nnn0 100n CCCC nnnn nnnn nnnn nnnn\n:BR^{COND_4_0} sDisp21 is (op13_3=0x7 & op5_4=0x4 & COND_4_0) ... & sDisp21\n{\n\tbuild COND_4_0;\n\tgoto sDisp21;\n}\n\n#---------------------------------------------------------------------\n# RJMP - Relative Jump\n# I. disp -> {-1024, -1022, ..., 1022}\n#---------------------------------------------------------------------\n\n# RJMP Format I:\n# Operation: PC <- PC + (SE(disp10)<<1);\n# Syntax: rjmp PC[disp]\n# 1100 nnnn nnnn 10nn\n\nRJMPdisp: disp is disp4_8 & sdisp0_2\n[ disp = inst_start + (((sdisp0_2 << 8) | disp4_8) << 1); ]\n{\n export *:4 disp;\n}\n\n:RJMP RJMPdisp is op12_4=0xc & op2_2=0x2 & RJMPdisp\n{\n goto RJMPdisp;\n}\n\n#---------------------------------------------------------------------\n# ICALL - Subroutine Call\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# ICALL Format I:\n# Operation: LR <- PC + 2\n# PC <- Rd\n# Syntax: icall Rd\n# 0101 1101 0001 dddd\n\n:ICALL rd0 is op4_12=0x5d1 & rd0 {\n LR = inst_next;\n call [rd0];\n}\n\n#---------------------------------------------------------------------\n# MCALL - Subroutine Call\n# I. p -> {0, 1, ..., 15}\n# disp -> {-131072, -131068, ..., 131068}\n#---------------------------------------------------------------------\n\nRP0Disp16: rp0^\"[\"^disp^\"]\" is rp0; disp_16\n[ disp = (disp_16 << 2); ]\n{\n\t\tval:4 = (rp0 & 0xfffffffc) + disp;\n export *:4 val;\n}\n\nRP0Disp16_2: PC[disp] is disp_16 & PC\n[ disp = (inst_start & 0xfffffffc) + (disp_16 << 2); ]\n{\n export *:4 disp;\n}\n\n# MCALL Format I:\n# Operation: LR <- PC + 4\n# PC <- *((Rp & 0xfffffffc) + (SE(disp16) << 2))\n# Syntax: mcall Rp[disp]\n# 1111 0000 0001 pppp nnnn nnnn nnnn nnnn\n\nIndirectPlaceHolder: \" \" is epsilon{}\n\n:MCALL RP0Disp16 is op4_12=0xf01 ... & RP0Disp16 {\n LR = inst_next;\n PC = RP0Disp16;\n call [PC];\n}\n\n:MCALL RP0Disp16_2^IndirectPlaceHolder is op4_12=0xf01 & rp0=0xf ; RP0Disp16_2 & IndirectPlaceHolder {\n LR = inst_next;\n PC = RP0Disp16_2;\n call [PC];\n}\n\nRelDisp10: val\t\t\tis disp4_8 & disp0_2 [ctx_rel0_8=disp4_8; ctx_rel8_2=disp0_2; val= inst_start + (ctx_rel10 << 1); ] {\n\texport *:4 val;\n}\n\nRelDisp21: val\t\t\tis imm16 [ctx_rel0_16=imm16; val=inst_start + (ctx_rel21 << 1); ] {\n\texport *:4 val;\n}\n\n:RCALL PC[RelDisp10]\tis op13_3=6 & op12_1=0 & b02=1 & b03=1 & PC & RelDisp10 {\n\tLR = inst_next;\n\tcall RelDisp10;\n}\n\n:RCALL PC[RelDisp21]\tis op13_3=7 & op5_4=5 & op0_4=0 & PC & b04 & bp9_4; RelDisp21 [ctx_rel16_1=b04; ctx_rel17_4=bp9_4;] {\n\tLR = inst_next;\n\tcall RelDisp21;\n}\n\n# The RETx instructions are somewhat complicated. The architecutre version (A/B)\n# determines hardware actions as well as the status of the mode bits M2:M0. For now,\n# we follow the \"B\" model as it's simpler and have a custom pcode. For RETE I also\n# picked a given interrupt level that would actually be determined by the mode bits.\n:RETD\t\t\t\t\tis op0_16=0xd623 {\n\tSR = RSR_DBG;\n\tSRTOFLAGS();\n\treturn [ RAR_DBG ];\n}\n\n:RETE\t\t\t\t\tis op0_16=0xd603 {\n\tCheckAndRestoreInterupt();\n\tSR = RSR_INT0;\n\tSRTOFLAGS();\n\tL = 0;\n\tLTOSR();\n\treturn [ RAR_INT0 ];\n}\n\n:RETS\t\t\t\t\tis op0_16=0xd613 {\n\tCheckAndRestoreSupervisor();\n\tSR = RSR_SUP;\n\tSRTOFLAGS();\n\treturn [ RAR_SUP ];\n}\n\n:RETJ \t\t\t\t\tis op0_16=0xd633 {\n\tJavaTrap();\n\tJ = 1;\n\tR = 0;\n\tJRGMTOSR();\n\treturn [ LR ];\n}\n\n:SCALL is op0_16=0xd733 {\n\tSupervisorCallSetup();\n\tLR = inst_next;\n\ttmp:4 = EVBA + 0x100;\n\tcall [ tmp ];\n}\n\nJV3: val\t\t\tis b06=1 & ctx_rel3 [ val = ctx_rel3 << 0; ] { export *[const]:1 val; }\nJV3: val\t\t\tis b06=0 & disp4_3 [ val = disp4_3+1; ] { export *[const]:1 val; }\n:INCJOSP JV3 \t\tis op7_9=0x1ad & op0_4=0x3 & disp4_3 & JV3 [ctx_rel3 = disp4_3;] {\n\tJavaCheckStack(JOSP,JV3);\n\tJOSP = JOSP + sext(JV3);\n}\n\n:POPJC \t\t\t\tis op0_16=0xd713 {\n\tJavaPopContext();\n}\n\n:PUSHJC \t\t\t\tis op0_16=0xd723 {\n\tJavaPushContext();\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_logic_operations.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.5 Logic Operations\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# AND - Logical AND with optional logical shift\n# I. \t {d, s} -> {0, 1, ..., 15}\n# II, III. {d, x, y} -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# AND Format I\n# Operation: Rd <- Rd & Rs\n# Syntax: and Rd, Rs\n# 000s sss0 0110 dddd\n\n:AND rd0, RS9A is op13_3=0x0 & op4_5=0x6 & rd0 & RS9A {\n\trd0 = rd0 & RS9A;\n\tNZSTATUS(rd0);\n}\n\n:AND rd0, RS9A is op13_3=0x0 & op4_5=0x6 & rd0 & RS9A & rd0=0xf {\n\tPC = inst_start & RS9A;\n\tNZSTATUS(PC);\n\tgoto [PC];\n}\n\n# AND Format II\n# Operation: Rd <- Rx & Ry << sa5\n# Syntax: and Rd, Rx, Ry << sa\n# 111x xxx1 1110 yyyy 0000 000t tttt dddd\n\n:AND erd0, RX9A, RY0A^\" << \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=0 & erd0 & shift4_5 {\n erd0 = RX9A & (RY0A << shift4_5);\n NZSTATUS(erd0);\n}\n\n:AND erd0, RX9A, RY0A^\" << \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=0 & erd0 & shift4_5 & erd0=0xf {\n PC = RX9A & (RY0A << shift4_5);\n NZSTATUS(PC);\n goto [PC];\n}\n\n# AND Format III\n# Operation: Rd <- Rx & Ry >> sa5\n# Syntax: and Rd, Rx, Ry >> sa\n# 111x xxx1 1110 yyyy 0000 001t tttt dddd\n\n:AND erd0, RX9A, RY0A^\" >> \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=1 & erd0 & shift4_5 {\n erd0 = RX9A & (RY0A >> shift4_5);\n NZSTATUS(erd0);\n}\n\n:AND erd0, RX9A, RY0A^\" >> \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=1 & erd0 & shift4_5 & erd0=0xf {\n PC = RX9A & (RY0A >> shift4_5);\n NZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# AND{cond4} - Conditional And\n# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} \n# {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# AND{cond4} Format I\n# Operation: if(cond4) then\n# Rd <- Rx & Ry\n# Syntax: and{cond4} Rd, Rx, Ry\n# 111x xxx1 1101 yyyy 1110 cccc 0010 dddd\n\n:AND^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=2 & ECOND_8_4 & erd0)\n{\n build ECOND_8_4;\n erd0 = RX9A & RY0A;\n}\n\n:AND^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=2 & ECOND_8_4 & erd0 & erd0=0xf)\n{\n build ECOND_8_4;\n PC = RX9A & RY0A;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# ANDH, ANDL - Logical AND into high or low half of register\n# I, II, III, IV. d -> {0, 1, ..., 15}\n# imm -> {0, 1, ..., 65535}\n#---------------------------------------------------------------------\n\n# ANDH Format I\n# Operation: Rd[31:16] <- Rd[31:16] & imm16\n# Syntax: andh Rd, imm\n# 1110 01H0 0001 dddd iiii iiii iiii iiii\n# H == 0\n\n:ANDH rd0, imm16 is op10_6=0x39 & coh=0 & op4_5=1 & rd0 ; imm16\n{\n value:4 = (imm16 << 16) | 0xffff;\n rd0 = rd0 & value;\n NZSTATUS(rd0);\n}\n\n:ANDH rd0, imm16 is op10_6=0x39 & coh=0 & op4_5=1 & rd0 & rd0=0xf; imm16\n{\n value:4 = (imm16 << 16) | 0xffff;\n PC = inst_start & value;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# ANDH Format II\n# Operation: Rd[31:16] <- Rd[31:16] & imm16\n# Rd[15:0] <- 0\n# Syntax: andh Rd, imm, COH\n# 1110 01H0 0001 dddd iiii iiii iiii iiii\n# H == 1\n\n:ANDH rd0, imm16^\", COH\" is op10_6=0x39 & coh=1 & op4_5=1 & rd0 ; imm16\n{\n value:4 = imm16 << 16;\n rd0 = rd0 & value;\n NZSTATUS(rd0);\n}\n\n:ANDH rd0, imm16^\", COH\" is op10_6=0x39 & coh=1 & op4_5=1 & rd0 & rd0=0xf; imm16\n{\n value:4 = imm16 << 16;\n PC = inst_start & value;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# ANDL Format III\n# Operation: Rd[15:0] <- Rd[15:0] & imm16\n# Syntax: andl Rd, imm\n# 1110 00H0 0001 dddd iiii iiii iiii iiii\n# H == 0\n\n:ANDL rd0, imm16 is op10_6=0x38 & coh=0 & op4_5=1 & rd0 ; imm16\n{\n value:4 = imm16 | 0xffff0000;\n rd0 = rd0 & value;\n NZSTATUS(rd0);\n}\n\n:ANDL rd0, imm16 is op10_6=0x38 & coh=0 & op4_5=1 & rd0 & rd0=0xf ; imm16\n{\n value:4 = imm16 | 0xffff0000;\n PC = inst_start & value;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# ANDL Format IV\n# Operation: Rd[15:0] <- Rd[15:0] & imm16\n# Rd[31:16] <- 0\n# Syntax: andl Rd, imm, COH\n# 1110 00H0 0001 dddd iiii iiii iiii iiii\n# H == 1\n\n:ANDL rd0, imm16^\", COH\" is op10_6=0x38 & coh=1 & op4_5=1 & rd0 ; imm16\n{\n value:4 = imm16;\n rd0 = rd0 & value;\n NZSTATUS(rd0);\n}\n\n:ANDL rd0, imm16^\", COH\" is op10_6=0x38 & coh=1 & op4_5=1 & rd0 & rd0=0xf; imm16\n{\n value:4 = imm16;\n PC = inst_start & value;\n NZSTATUS(PC);\n}\n\n#---------------------------------------------------------------------\n# ANDN - Logical AND NOT\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# ANDN Format I\n# Operation: Rd <- Rd & Rs\n# Syntax: andn Rd, Rs\n# 000s sss0 1000 dddd\n\n:ANDN rd0, RS9A is op13_3=0 & op4_5=8 & rd0 & RS9A {\n rd0 = rd0 & ~RS9A;\n NZSTATUS(rd0);\n}\n\n:ANDN rd0, RS9A is op13_3=0 & op4_5=8 & rd0 & RS9A & rd0=0xf {\n PC = inst_start & ~RS9A;\n NZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# COM - One's Compliment\n# I. d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# COM Format I\n# Operation: Rd <- ~Rd\n# Syntax: com Rd\n# 0101 1100 1101 dddd\n\n:COM rd0 is op4_12=0x5cd & rd0\n{\n rd0 = ~rd0;\n ZSTATUS(rd0);\n}\n\n#---------------------------------------------------------------------\n# EOR - Logical Exclusive OR with optional logical shift\n# I. {d, s} -> {0, 1, ..., 15}\n# II, III. {d, x, y} -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# EOR Format I\n# Operation: Rd <- Rd & Rs\n# Syntax: eor Rd, Rs\n# 000s sss0 0101 dddd\n\n:EOR rd0, RS9A is op13_3=0x0 & op4_5=0x5 & rd0 & RS9A {\n rd0 = rd0 ^ RS9A;\n NZSTATUS(rd0);\n}\n\n:EOR rd0, RS9A is op13_3=0x0 & op4_5=0x5 & rd0 & RS9A & rd0=0xf {\n PC = inst_start ^ RS9A;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# EOR Format II\n# Operation: Rd <- Rx & Ry << sa5\n# Syntax: eor Rd, Rx, Ry << sa\n# 111x xxx1 1110 yyyy 0010 000t tttt dddd\n\n:EOR erd0, RX9A, RY0A^\" << \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=0x10 & erd0 & shift4_5 {\n erd0 = RX9A ^ (RY0A << shift4_5);\n NZSTATUS(erd0);\n}\n\n:EOR erd0, RX9A, RY0A^\" << \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=0x10 & erd0 & shift4_5 & erd0=0xf {\n PC = RX9A ^ (RY0A << shift4_5);\n NZSTATUS(PC);\n goto [PC];\n}\n\n# EOR Format III\n# Operation: Rd <- Rx & Ry >> sa5\n# Syntax: eor Rd, Rx, Ry >> sa\n# 111x xxx1 1110 yyyy 0010 001t tttt dddd\n\n:EOR erd0, RX9A, RY0A^\" >> \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=0x11 & erd0 & shift4_5 {\n erd0 = RX9A ^ (RY0A >> shift4_5);\n NZSTATUS(erd0);\n}\n\n:EOR erd0, RX9A, RY0A^\" >> \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=0x11 & erd0 & shift4_5 & erd0=0xf {\n PC = RX9A ^ (RY0A >> shift4_5);\n NZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# EOR{cond4} - Conditional Logical EOR\n# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} \n# {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# EOR{cond4} Format I\n# Operation: if(cond4) then\n# Rd <- Rx ^ Ry\n# Syntax: eor{cond4} Rd, Rx, Ry\n# 111x xxx1 1101 yyyy 1110 cccc 0100 dddd\n\n:EOR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=4 & ECOND_8_4 & erd0)\n{\n build ECOND_8_4;\n erd0 = RX9A ^ RY0A;\n}\n\n:EOR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=4 & ECOND_8_4 & erd0 & erd0=0xf)\n{\n build ECOND_8_4;\n PC = RX9A ^ RY0A;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# EORH, EORL - Logical EOR into high or low half of register\n# I, II. d -> {0, 1, ..., 15}\n# imm -> {0, 1, ..., 65535}\n#---------------------------------------------------------------------\n\n# EORH Format I\n# Operation: Rd[31:16] <- Rd[31:16] & imm16\n# Syntax: eorh Rd, imm\n# 1110 1110 0001 dddd iiii iiii iiii iiii\n\n:EORH rd0, imm16 is op4_12=0xee1 & rd0 ; imm16\n{\n value:4 = imm16 << 16;\n rd0 = rd0 ^ value;\n NZSTATUS(rd0);\n}\n\n:EORH rd0, imm16 is op4_12=0xee1 & rd0 & rd0=0xf ; imm16\n{\n value:4 = imm16 << 16;\n PC = inst_start ^ value;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# EORL Format II\n# Operation: Rd[15:0] <- Rd[15:0] & imm16\n# Syntax: eorl Rd, imm\n# 1110 1100 0001 dddd iiii iiii iiii iiii\n\n:EORL rd0, imm16 is op4_12=0xec1 & rd0 ; imm16\n{\n value:4 = imm16;\n rd0 = rd0 ^ value;\n NZSTATUS(rd0);\n}\n\n:EORL rd0, imm16 is op4_12=0xec1 & rd0 & rd0=0xf ; imm16\n{\n value:4 = imm16;\n PC = inst_start ^ value;\n NZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# OR - Logical OR with optional logical shift\n# I. {d, s} -> {0, 1, ..., 15}\n# II, III. {d, x, y} -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# OR Format I\n# Operation: Rd <- Rd & Rs\n# Syntax: or Rd, Rs\n# 000s sss0 0100 dddd\n\n:OR rd0, RS9A is op13_3=0x0 & op4_5=0x4 & rd0 & RS9A {\n rd0 = rd0 | RS9A;\n NZSTATUS(rd0);\n}\n\n:OR rd0, RS9A is op13_3=0x0 & op4_5=0x4 & rd0 & RS9A & rd0=0xf {\n PC = inst_start | RS9A;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# OR Format II\n# Operation: Rd <- Rx & Ry << sa5\n# Syntax: or Rd, Rx, Ry << sa\n# 111x xxx1 1110 yyyy 0001 000t tttt dddd\n\n:OR erd0, RX9A, RY0A^\" << \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=8 & erd0 & shift4_5 {\n erd0 = RX9A | (RY0A << shift4_5);\n NZSTATUS(erd0);\n}\n\n:OR erd0, RX9A, RY0A^\" << \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=8 & erd0 & shift4_5 & erd0=0xf {\n PC = RX9A | (RY0A << shift4_5);\n NZSTATUS(PC);\n goto [PC];\n}\n\n# OR Format III\n# Operation: Rd <- Rx & Ry >> sa5\n# Syntax: or Rd, Rx, Ry >> sa\n# 111x xxx1 1110 yyyy 0001 001t tttt dddd\n\n:OR erd0, RX9A, RY0A^\" >> \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=9 & erd0 & shift4_5 {\n erd0 = RX9A | (RY0A >> shift4_5);\n NZSTATUS(erd0);\n}\n\n:OR erd0, RX9A, RY0A^\" >> \" shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;\n eop9_7=9 & erd0 & shift4_5 & erd0=0xf {\n PC = RX9A | (RY0A >> shift4_5);\n NZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# OR{cond4} - Conditional Logical OR\n# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} \n# {d,x,y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# OR{cond4} Format I\n# Operation: if(cond4) then\n# Rd <- Rx | Ry\n# Syntax: or{cond4} Rd, Rx, Ry\n# 111x xxx1 1101 yyyy 1110 cccc 0011 dddd\n\n:OR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=3 & ECOND_8_4 & erd0)\n{\n build ECOND_8_4;\n erd0 = RX9A | RY0A;\n}\n\n:OR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;\n eop12_4=0xe & eop4_4=3 & ECOND_8_4 & erd0 & erd0=0xf)\n{\n build ECOND_8_4;\n PC = RX9A | RY0A;\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# ORH, ORL - Logical OR into high or low half of register\n# I, II. d -> {0, 1, ..., 15}\n# imm -> {0, 1, ..., 65535}\n#---------------------------------------------------------------------\n\n# ORH Format I\n# Operation: Rd[31:16] <- Rd[31:16] | imm16\n# Syntax: orh Rd, imm\n# 1110 1010 0001 dddd iiii iiii iiii iiii\n\n:ORH rd0, imm16 is op4_12=0xea1 & rd0 ; imm16\n{\n val:4 = (imm16 << 16);\n rd0 = rd0 | val;\n NZSTATUS(rd0);\n}\n\n:ORH rd0, imm16 is op4_12=0xea1 & rd0 & rd0=0xf ; imm16\n{\n val:4 = (imm16 << 16);\n PC = inst_start | val;\n NZSTATUS(PC);\n goto [PC];\n}\n\n# ORL Format II\n# Operation: Rd[15:0] <- Rd[15:0] | imm16\n# Syntax: orl Rd, imm\n# 1110 1000 0001 dddd iiii iiii iiii iiii\n\n:ORL rd0, imm16 is op4_12=0xe81 & rd0 ; imm16\n{\n val:4 = imm16;\n rd0 = rd0 | val;\n NZSTATUS(rd0);\n}\n\n:ORL rd0, imm16 is op4_12=0xe81 & rd0 & rd0=0xf; imm16\n{\n val:4 = imm16;\n PC = inst_start | val;\n NZSTATUS(PC);\n goto [PC];\n}\n\n#---------------------------------------------------------------------\n# TST - Test Register\n# I. {d, s} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# TST Format I\n# Operation: Rd & Rs\n# Syntax: tst Rd, Rs\n# 000s sss0 0111 dddd\n\n:TST RD0A, RS9A is op13_3=0x0 & op4_5=0x7 & RD0A & RS9A {\n test:4 = RD0A & RS9A;\n NZSTATUS(test);\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_multiplication_operations.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.3 Multiplication Operations\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# DIVS - Signed Divide\n# I. d -> {0, 2, ..., 14)\n# {x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# DIVS Format I\n# Operation: Rd <- Rx / Ry\n# Rd+1 <- Rx % Ry\n# Syntax: divs Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1100 0000 dddd\n\n:DIVS erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0xc0 & eb0=0 & erd0 & erd0_low & erd0_hi\n{\n\t\ttmpx:4 = RX9A;\n\t\ttmpy:4 = RY0A;\n erd0_low = tmpx s/ tmpy;\n erd0_hi = tmpx s% tmpy;\n}\n\n#---------------------------------------------------------------------\n# DIVU - Unsigned Divide\n# I. d -> {0, 2, ..., 14)\n# {x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# DIVU Format I\n# Operation: Rd <- Rx / Ry\n# Rd+1 <- Rx % Ry\n# Syntax: divu Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1101 0000 dddd\n\n:DIVU erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0xd0 & eb0=0 & erd0 & erd0_low & erd0_hi\n{\n\t\ttmpx:4 = RX9A;\n\t\ttmpy:4 = RY0A;\n erd0_low = tmpx / tmpy;\n erd0_hi = tmpx % tmpy;\n}\n\n#---------------------------------------------------------------------\n# MAC - Multiply Accumulate\n# I. {d, x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MAC Format I\n# Operation: Rd <- Rx * Ry + Rd\n# Syntax: mac Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0011 0100 dddd\n\n:MAC erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0x34 & erd0\n{\n erd0 = RX9A * RY0A + erd0;\n}\n\n#---------------------------------------------------------------------\n# MACS.D - Multiply Accumulate Signed\n# I. d -> {0, 2, ..., 14)\n# {x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MACS.D Format I\n# Operation: acc <- (Rd+1:Rd)\n# prod <- Rx * Ry\n# res <- prod + acc\n# (Rd+1:Rd) <- res\n# Syntax: macs.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0101 0100 dddd\n\n:MACS.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0x54 & eb0=0 & erd0 & erd0_low & erd0_hi\n{\n acc:8 = zext(erd0_low) | zext(erd0_hi << 32);\n prod:8 = sext(RX9A) * sext(RY0A);\n res:8 = prod + acc;\n erd0_low = res:4;\n tmp:8 = (res s>> 32);\n erd0_hi = tmp:4;\n}\n\n#---------------------------------------------------------------------\n# MACU.D - Multiply Accumulate Unsigned\n# I. d -> {0, 2, ..., 14)\n# {x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MACU.D Format I\n# Operation: acc <- (Rd+1:Rd)\n# prod <- Rx * Ry\n# res <- prod + acc\n# (Rd+1:Rd) <- res\n# Syntax: macu.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0111 0100 dddd\n\n:MACU.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0x74 & eb0=0 & erd0 & erd0_low & erd0_hi\n{\n acc:8 = zext(erd0_low) | zext(erd0_hi << 32);\n prod:8 = zext(RX9A) * zext(RY0A);\n res:8 = prod + acc;\n erd0_low = res:4;\n tmp:8 = (res >> 32);\n erd0_hi = tmp:4;\n}\n\n#---------------------------------------------------------------------\n# MUL - Multiply\n# I. {d, s} -> {0, 1, ..., 15}\n# II. {d, x, y} -> {0, 1, ..., 15}\n# III. {d, s} -> {0, 1, ..., 15}\n# imm -> {-128, -127, ..., 127}\n#---------------------------------------------------------------------\n\n# MUL Format I\n# Operation: Rd <- Rd * Rs\n# Syntax: mul Rd, Rs\n# 101s sss1 0011 dddd\n\n:MUL rd0, RS9A is op13_3=5 & op4_5=0x13 & rd0 & RS9A\n{\n rd0 = rd0 * RS9A;\n}\n\n# MUL Format II\n# Operation: Rd <- Rx * Ry\n# Syntax: mul Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0010 0100 dddd\n\n:MUL erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; eop4_12=0x24 & erd0\n{\n erd0 = RX9A * RY0A;\n}\n\n# MUL Format III\n# Operation: Rd <- Rs * SE(imm8)\n# Syntax: mul Rd, Rs, imm\n# 111s sss0 0000 dddd 0001 0000 iiii iiii\n\n:MUL rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A ; eop8_8=0x10 & simm0_8\n{\n rd0 = RS9A * simm0_8;\n}\n\n#---------------------------------------------------------------------\n# MULS.D - Multiply Signed\n# I. d -> {0, 2, ..., 14)\n# {x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MULS.D Format I\n# Operation: (Rd+1:Rd) <- Rx * Ry\n# Syntax: muls.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0100 0100 dddd\n\n:MULS.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0x44 & eb0=0 & erd0 & erd0_low & erd0_hi\n{\n prod:8 = sext(RX9A) * sext(RY0A);\n erd0_low = prod:4;\n tmp:8 = (prod s>> 32);\n erd0_hi = tmp:4;\n}\n\n#---------------------------------------------------------------------\n# MULU.D - Multiply Unsigned\n# I. d -> {0, 2, ..., 14)\n# {x, y} -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# MULU.D Format I\n# Operation: (Rd+1:Rd) <- Rx * Ry\n# Syntax: mulu.d Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 0110 0100 dddd\n\n:MULU.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ;\n eop4_12=0x64 & eb0=0 & erd0 & erd0_low & erd0_hi\n{\n prod:8 = zext(RX9A) * zext(RY0A);\n erd0_low = prod:4;\n tmp:8 = (prod >> 32);\n erd0_hi = tmp:4;\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_shift_operations.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.7 Shift Operations\n#---------------------------------------------------------------------\n\nmacro do_asr(VAL, SA, DEST) {\n\ttmp:8 = zext(VAL) << 32;\n\ttmp = tmp s>> SA;\n DEST = VAL s>> SA;\n C = (tmp & 0x0000000080000000) != 0;\n NZSTATUS(DEST);\n \n}\n\n#---------------------------------------------------------------------\n# ASR - Arithmetic Shift Right\n# I. {d, x, y} -> {0, 1, ..., 15}\n# II. d -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n# III. {d, s} -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# ASR Format I\n# Operation: Rd <- ASR(Rx, Ry[4:0])\n# Syntax: asr Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1000 0100 dddd\n\n:ASR erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A;\n eop4_12=0x084 & erd0\n{\n do_asr(RX9A, RY0A, erd0);\n}\n\n# ASR Format II\n# Operation: Rd <- ASR(Rd, sa5)\n# Syntax: asr Rd, sa\n# 101t ttt1 010t dddd\n\n:ASR rd0, shift is op13_3=5 & op5_4=0xa & shift9_4 & shift4_1 & rd0\n [ shift = (shift9_4 << 1) | shift4_1; ]\n{\n do_asr(rd0, shift, rd0);\n}\n\n# ASR Format III\n# Operation: Rd <- ASR(Rs, sa5)\n# Syntax: asr Rd, Rs, sa\n# 111s sss0 0000 dddd 0001 0100 000t tttt\n\n:ASR rd0, RS9A, shift0_5 is op13_3=7 & op5_4=0 & RS9A & rd0;\n eop5_11=0xa0 & shift0_5\n{\n do_asr(RS9A, shift0_5, rd0);\n}\n\nmacro do_lsl(VAL, SA, DEST) {\n\ttmp:8 = zext(VAL);\n\ttmp = tmp << SA;\n\tDEST = tmp:4;\n C = (tmp & 0x0000000100000000) != 0;\n NZSTATUS(DEST);\n}\n\n#---------------------------------------------------------------------\n# LSL - Logical Shift Left\n# I. {d, x, y} -> {0, 1, ..., 15}\n# II. d -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n# III. {d, s} -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# LSL Format I\n# Operation: Rd <- LSL(Rx, Ry[4:0])\n# Syntax: lsl Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1001 0100 dddd\n\n:LSL erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A;\n eop4_12=0x094 & erd0\n{\n\t\ttmp:4 = RY0A & 0x0000001F;\n do_lsl(RX9A, tmp, erd0);\n}\n\n# LSL Format II\n# Operation: Rd <- LSL(Rd, sa5)\n# Syntax: lsl Rd, sa\n# 101t ttt1 011t dddd\n\n:LSL rd0, shift is op13_3=5 & op5_4=0xb & shift9_4 & shift4_1 & rd0\n [ shift = (shift9_4 << 1) | shift4_1; ]\n{\n do_lsl(rd0, shift, rd0);\n}\n\n# LSL Format III\n# Operation: Rd <- LSL(Rs, sa5)\n# Syntax: lsl Rd, Rs, sa\n# 111s sss0 0000 dddd 0001 0101 000t tttt\n\n:LSL rd0, RS9A, shift0_5 is op13_3=7 & op5_4=0 & RS9A & rd0;\n eop5_11=0xa8 & shift0_5\n{\n do_lsl(RS9A, shift0_5, rd0);\n}\n\nmacro do_lsr(VAL, SA, DEST) {\n\ttmp:8 = zext(VAL) << 32;\n\ttmp = tmp >> SA;\n DEST = VAL >> SA;\n C = (tmp & 0x0000000080000000) != 0;\n NZSTATUS(DEST);\n}\n\n#---------------------------------------------------------------------\n# LSR - Logical Shift Right\n# I. {d, x, y} -> {0, 1, ..., 15}\n# II. d -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n# III. {d, s} -> {0, 1, ..., 15}\n# sa -> {0, 1, ..., 31}\n#---------------------------------------------------------------------\n\n# LSR Format I\n# Operation: Rd <- LSR(Rx, Ry[4:0])\n# Syntax: lsr Rd, Rx, Ry\n# 111x xxx0 0000 yyyy 0000 1010 0100 dddd\n\n:LSR erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A;\n eop4_12=0x0a4 & erd0\n{\n\t\ttmp:4 = RY0A & 0x0000001F;\n do_lsr(RX9A, tmp, erd0);\n}\n\n# LSR Format II\n# Operation: Rd <- LSR(Rd, sa5)\n# Syntax: lsr Rd, sa\n# 101t ttt1 100t dddd\n\n:LSR rd0, shift is op13_3=5 & op5_4=0xc & shift9_4 & shift4_1 & rd0\n [ shift = (shift9_4 << 1) | shift4_1; ]\n{\n do_lsr(rd0, shift, rd0);\n}\n\n# LSR Format III\n# Operation: Rd <- LSR(Rs, sa5)\n# Syntax: lsr Rd, Rs, sa\n# 111s sss0 0000 dddd 0001 0110 000t tttt\n\n:LSR rd0, RS9A, shift0_5 is op13_3=7 & op5_4=0 & RS9A & rd0;\n eop5_11=0xb0 & shift0_5\n{\n do_lsr(RS9A, shift0_5, rd0);\n}\n\n:ROL rd0 \t\tis op4_12=0x5cf & rd0 {\n\ttmp:4 = rd0 >> 31;\n\ttmpa:4 = zext(C);\n\trd0 = rd0 << 1;\n\trd0 = rd0 | tmpa;\n\tC = tmp:1;\n\tCZNVTOSR();\n}\n \n:ROR rd0 \t\tis op4_12=0x5d0 & rd0 {\n\ttmp:4 = rd0 & 0x1;\n\ttmpa:4 = zext(C);\n\ttmpa = tmpa << 31;\n\trd0 = rd0 >> 1;\n\trd0 = rd0 | tmpa;\n\tC = tmp:1;\n CZNVTOSR();\n}\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_simd_operations.sinc", "content": "\nmacro satub(RES) {\n\tRES = (zext(RES > 0x00FF) * 0x00FF) + (zext(RES < 0x0100) * RES);\n}\n\nmacro satsb(RES) {\n\tRES = (0x007F * zext(RES s> 0x007F)) + (RES * zext(RES s< 0x0080) * zext(RES s>= 0xFF80)) + (0x0080 * zext(RES s< 0xFF80));\n}\n\nmacro satsh(RES) {\n\tRES = (0x00007FFF * zext(RES s> 0x00007FFF)) + (RES * zext(RES s< 0x00008000) * zext(RES s>= 0xFFFF8000)) + (0x00008000 * zext(RES s< 0xFFFF8000));\n}\n\nmacro satuh(RES) {\n\tRES = (0x0000FFFF * zext(RES > 0x0000FFFF)) + (RES * zext(RES < 0x00010000));\n}\n\nmacro sataddub(OP1, OP2, RES) {\n\tRES = zext(OP1) + zext(OP2);\n\tsatub(RES);\n}\n\nmacro sataddsb(OP1, OP2, RES) {\n\tRES = sext(OP1) + sext(OP2);\n\tsatsb(RES);\n}\n\nmacro satsubub(OP1, OP2, RES) {\n\tRES = zext(OP1) - zext(OP2);\n\tsatub(RES);\n}\n\nmacro satsubsb(OP1, OP2, RES) {\n\tRES = sext(OP1) - sext(OP2);\n\tsatsb(RES);\n}\n\nmacro satadduh(OP1, OP2, RES) {\n\tRES = zext(OP1) + zext(OP2);\n\tsatuh(RES);\n}\n\nmacro satsubuh(OP1, OP2, RES) {\n\tRES = zext(OP1) - zext(OP2);\n\tsatuh(RES);\n}\n\nmacro sataddsh(OP1, OP2, RES) {\n\tRES = sext(OP1) + sext(OP2);\n\tsatsh(RES);\n}\n\nmacro satsubsh(OP1, OP2, RES) {\n\tRES = sext(OP1) - sext(OP2);\n\tsatsh(RES);\n}\n\nPXPART: \":T\" is ctx_usex & xpart=0x1 {\n\ttmp:4 = ctx_usex;\n\ttmp = tmp >> 16;\n\texport *[const]:2 tmp;\n}\n\nPXPART: \":B\" is ctx_usex & xpart=0x0 { \n\ttmp:4 = ctx_usex;\n\ttmp = tmp & 0x0000FFFF;\n\texport *[const]:2 tmp;\n}\n\nPYPART: \":T\" is ctx_usey & ypart=0x1 { \n\ttmp:4 = ctx_usey;\n\ttmp = tmp >> 16;\n\texport *[const]:2 tmp;\n}\n\nPYPART: \":B\" is ctx_usey & ypart=0x0 { \n\ttmp:4 = ctx_usey;\n\ttmp = tmp & 0x0000FFFF;\n\texport *[const]:2 tmp;\n}\n\nPUPART: \":T\" is ctx_useu & upart=0x1 { \n\ttmp:4 = ctx_useu;\n\ttmp = tmp >> 16;\n\texport *[const]:2 tmp;\n}\n\nPUPART: \":B\" is ctx_useu & upart=0x0 { \n\ttmp:4 = ctx_useu;\n\ttmp = tmp & 0x0000FFFF;\n\texport *[const]:2 tmp;\n}\n\n\n:PABS.SB erd0, rs0 is op4_12=0xe00 & rs0 ; eop4_12=0x23e & erd0 {\n\ttmps:1 = rs0[24,8];\n\terd0[24,8] = abs(tmps);\n\t\t\n\ttmps = rs0[16,8];\n\terd0[16,8] = abs(tmps);\n\t\t\n\ttmps = rs0[8,8];\n\terd0[8,8] = abs(tmps);\n\t\t\n\ttmps = rs0[0,8];\n\terd0[0,8] = abs(tmps);\t\n}\n\n:PABS.SH erd0, rs0 is op4_12=0xe00 & rs0 ; eop4_12=0x23f & erd0 {\n\ttmps:2 = rs0[16,16];\n\terd0[16,16] = abs(tmps);\n\t\t\n\ttmps = rs0[0,16];\n\terd0[0,16] = abs(tmps);\n}\n\n:PACKSH.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x24c & erd0 {\n\ttmp:2 = rx9[16,16];\n\tsatub(tmp);\n\terd0[24,8] = tmp:1;\n\ttmp = rx9[0,16];\n\tsatub(tmp);\n\terd0[16,8] = tmp:1;\n\ttmp = ry0[16,16];\n\tsatub(tmp);\n\terd0[8,8] = tmp:1;\n\ttmp = ry0[0,16];\n\tsatub(tmp);\n\terd0[0,8] = tmp:1;\n}\n\n:PACKSH.SB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x24d & erd0 {\n\ttmp:2 = rx9[16,16];\n\tsatsb(tmp);\n\terd0[24,8] = tmp:1;\n\ttmp = rx9[0,16];\n\tsatsb(tmp);\n\terd0[16,8] = tmp:1;\n\ttmp = ry0[16,16];\n\tsatsb(tmp);\n\terd0[8,8] = tmp:1;\n\ttmp = ry0[0,16];\n\tsatsb(tmp);\n\terd0[0,8] = tmp:1;\n}\n\n:PACKW.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x247 & erd0 {\n\ttmp:4 = rx9;\n\tsatsh(tmp);\n\terd0[16,16] = tmp:2;\n\ttmp = ry0;\n\tsatsh(tmp);\n\terd0[0,16] = tmp:2;\n}\n\n:PADD.B erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x230 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:1 = tmpx + tmpy;\n\terd0[24,8] = tmpd;\n\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\ttmpd = tmpx + tmpy;\n\terd0[16,8] = tmpd;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\ttmpd = tmpx + tmpy;\n\terd0[8,8] = tmpd;\n\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\ttmpd = tmpx + tmpy;\n\terd0[0,8] = tmpd;\n\t\n}\n\n:PADD.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x200 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:2 = tmpx + tmpy;\n\terd0[16,16] = tmpd;\n\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\ttmpd = tmpx + tmpy;\n\terd0[0,16] = tmpd;\n}\n\n:PADDH.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x236 & erd0 {\n\ttmpx:2 = zext(rx9[24,8]);\n\ttmpy:2 = zext(ry0[24,8]);\n\ttmpd:2 = tmpx + tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[24,8] = tmpd:1;\n\n\ttmpx = zext(rx9[16,8]);\n\ttmpy = zext(ry0[16,8]);\n\ttmpd = tmpx + tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = zext(rx9[8,8]);\n\ttmpy = zext(ry0[8,8]);\n\ttmpd = tmpx + tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[8,8] = tmpd:1;\n\n\ttmpx = zext(rx9[0,8]);\n\ttmpy = zext(ry0[0,8]);\n\ttmpd = tmpx + tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[0,8] = tmpd:1;\n}\n\n:PADDH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20c & erd0 {\n\ttmpx:4 = sext(rx9[16,16]);\n\ttmpy:4 = sext(ry0[16,16]);\n\ttmpd:4 = tmpx + tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[16,16] = tmpd:2;\n\n\ttmpx = sext(rx9[0,16]);\n\ttmpy = sext(ry0[0,16]);\n\ttmpd = tmpx + tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[0,16] = tmpd:2;\n}\n\n:PADDS.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x234 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:2 = 0;\n\tsataddub(tmpx,tmpy,tmpd);\n\terd0[24,8] = tmpd:1;\n\t\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\tsataddub(tmpx,tmpy,tmpd);\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\tsataddub(tmpx,tmpy,tmpd);\n\terd0[8,8] = tmpd:1;\n\t\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\tsataddub(tmpx,tmpy,tmpd);\n\terd0[0,8] = tmpd:1;\n\n}\n\n:PADDS.SB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x232 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:2 = 0;\n\tsataddsb(tmpx,tmpy,tmpd);\n\terd0[24,8] = tmpd:1;\n\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\tsataddsb(tmpx,tmpy,tmpd);\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\tsataddsb(tmpx,tmpy,tmpd);\n\terd0[8,8] = tmpd:1;\n\t\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\tsataddsb(tmpx,tmpy,tmpd);\n\terd0[0,8] = tmpd:1;\n\t\n}\n\n:PADDS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x208 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:4 = 0;\n\tsatadduh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\tsatadduh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PADDS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x204 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:4 = 0;\n\tsataddsh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\tsataddsh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PADDSUB.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x84 & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] {\n\ttmp:2 = PXPART + PYPART;\n\terd0[16,16] = tmp;\n\ttmp = PXPART - PYPART;\n\terd0[0,16] = tmp;\n}\n\n:PADDSUBH.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x8a & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] {\n\ttmp:4 = sext(PXPART) + sext(PYPART);\n\ttmp = tmp s>> 1;\n\terd0[16,16] = tmp:2;\n\ttmp = sext(PXPART) - sext(PYPART);\n\ttmp = tmp s>> 1;\n\terd0[0,16] = tmp:2;\n}\n\n:PADDX.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x202 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[0,16];\n\ttmpd:2 = tmpx + tmpy;\n\terd0[16,16] = tmpd;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[16,16];\n\ttmpd = tmpx + tmpy;\n\terd0[0,16] = tmpd;\n}\n\n:PADDXH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20e & erd0 {\n\ttmpx:4 = sext(rx9[16,16]);\n\ttmpy:4 = sext(ry0[0,16]);\n\ttmpd:4 = tmpx + tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = sext(rx9[0,16]);\n\ttmpy = sext(ry0[16,16]);\n\ttmpd = tmpx + tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[0,16] = tmpd:2;\n}\n\n:PASR.B erd0, rs9, sa0_3 is op13_3=0x7 & rs9 & op3_6=0x0 & sa0_3 ; eop4_12=0x241 & erd0 {\n\ttmp:1 = rs9[24,8];\n\ttmp = tmp s>> sa0_3;\n\terd0[24,8] = tmp;\n\ttmp = rs9[16,8];\n\ttmp = tmp s>> sa0_3;\n\terd0[16,8] = tmp;\n\ttmp = rs9[8,8];\n\ttmp = tmp s>> sa0_3;\n\terd0[8,8] = tmp;\n\ttmp = rs9[0,8];\n\ttmp = tmp s>> sa0_3;\n\terd0[0,8] = tmp;\n}\n\n:PASR.H erd0, rs9, sa0_4 is op13_3=0x7 & rs9 & op4_5=0x0 & sa0_4 ; eop4_12=0x244 & erd0 {\n\ttmp:2 = rs9[16,16];\n\ttmp = tmp s>> sa0_4;\n\terd0[16,16] = tmp;\n\ttmp = rs9[0,16];\n\ttmp = tmp s>> sa0_4;\n\terd0[0,16] = tmp;\n}\n\n:PAVG.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23c & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:2 = (zext(tmpx) + zext(tmpy) + 1) >> 1;\n\terd0[24,8] = tmpd:1;\n\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\ttmpd = (zext(tmpx) + zext(tmpy) + 1) >> 1;\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\ttmpd = (zext(tmpx) + zext(tmpy) + 1) >> 1;\n\terd0[8,8] = tmpd:1;\n\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\ttmpd = (zext(tmpx) + zext(tmpy) + 1) >> 1;\n\terd0[0,8] = tmpd:1;\n}\n\n:PAVG.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23d & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:4 = (sext(tmpx) + sext(tmpy) + 1) s>> 1;\n\terd0[16,16] = tmpd:2;\n\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\ttmpd = (sext(tmpx) + sext(tmpy) + 1) s>> 1;\n\terd0[0,16] = tmpd:2;\n}\n\n:PLSL.B erd0, rs9, sa0_3 is op13_3=0x7 & rs9 & op3_6=0x0 & sa0_3 ; eop4_12=0x242 & erd0 {\n\ttmp:1 = rs9[24,8];\n\ttmp = tmp << sa0_3;\n\terd0[24,8] = tmp;\n\ttmp = rs9[16,8];\n\ttmp = tmp << sa0_3;\n\terd0[16,8] = tmp;\n\ttmp = rs9[8,8];\n\ttmp = tmp << sa0_3;\n\terd0[8,8] = tmp;\n\ttmp = rs9[0,8];\n\ttmp = tmp << sa0_3;\n\terd0[0,8] = tmp;\n}\n\n:PLSL.H erd0, rs9, sa0_4 is op13_3=0x7 & rs9 & op4_5=0x0 & sa0_4 ; eop4_12=0x245 & erd0 {\n\ttmp:2 = rs9[16,16];\n\ttmp = tmp << sa0_4;\n\terd0[16,16] = tmp;\n\ttmp = rs9[0,16];\n\ttmp = tmp << sa0_4;\n\terd0[0,16] = tmp;\n}\n\n:PLSR.B erd0, rs9, sa0_3 is op13_3=0x7 & rs9 & op3_6=0x0 & sa0_3 ; eop4_12=0x243 & erd0 {\n\ttmp:1 = rs9[24,8];\n\ttmp = tmp >> sa0_3;\n\terd0[24,8] = tmp;\n\ttmp = rs9[16,8];\n\ttmp = tmp >> sa0_3;\n\terd0[16,8] = tmp;\n\ttmp = rs9[8,8];\n\ttmp = tmp >> sa0_3;\n\terd0[8,8] = tmp;\n\ttmp = rs9[0,8];\n\ttmp = tmp >> sa0_3;\n\terd0[0,8] = tmp;\n}\n\n:PLSR.H erd0, rs9, sa0_4 is op13_3=0x7 & rs9 & op4_5=0x0 & sa0_4 ; eop4_12=0x246 & erd0 {\n\ttmp:2 = rs9[16,16];\n\ttmp = tmp >> sa0_4;\n\terd0[16,16] = tmp;\n\ttmp = rs9[0,16];\n\ttmp = tmp >> sa0_4;\n\terd0[0,16] = tmp;\n}\n\n:PMAX.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x238 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:1 = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx));\n\terd0[24,8] = tmpd;\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\ttmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx));\n\terd0[16,8] = tmpd;\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\ttmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx));\n\terd0[8,8] = tmpd;\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\ttmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx));\n\terd0[0,8] = tmpd;\n}\n\n:PMAX.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x239 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:2 = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx));\n\terd0[16,16] = tmpd;\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\ttmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx));\n\terd0[0,16] = tmpd;\n}\n\n:PMIN.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23a & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:1 = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx));\n\terd0[24,8] = tmpd;\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\ttmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx));\n\terd0[16,8] = tmpd;\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\ttmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx));\n\terd0[8,8] = tmpd;\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\ttmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx));\n\terd0[0,8] = tmpd;\n}\n\n:PMIN.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23b & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:2 = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx));\n\terd0[16,16] = tmpd;\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\ttmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx));\n\terd0[0,16] = tmpd;\n}\n\n:PADDSUBS.UH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x88 & PXPART & PYPART & erd0 {\n\ttmpx:2 = PXPART;\n\ttmpy:2 = PYPART;\n\ttmpd:4 = 0;\n\tsatadduh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\tsatsubuh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PADDSUBS.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x86 & PXPART & PYPART & erd0 {\n\ttmpx:2 = PXPART;\n\ttmpy:2 = PYPART;\n\ttmpd:4 = 0;\n\tsataddsh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\tsatsubsh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PADDXS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20a & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[0,16];\n\ttmpd:4 = 0;\n\tsatadduh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[16,16];\n\tsatadduh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PADDXS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x206 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[0,16];\n\ttmpd:4 = 0;\n\tsataddsh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[16,16];\n\tsataddsh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PSAD erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x240 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:1 = abs(tmpx - tmpy);\n\terd0 = zext(tmpd);\n\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\ttmpd = abs(tmpx - tmpy);\n\terd0 = erd0 + zext(tmpd);\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\ttmpd = abs(tmpx - tmpy);\n\terd0 = erd0 + zext(tmpd);\n\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\ttmpd = abs(tmpx - tmpy);\n\terd0 = erd0 + zext(tmpd);\n}\n\n:PSUB.B erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x231 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:1 = tmpx - tmpy;\n\terd0[24,8] = tmpd;\n\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\ttmpd = tmpx - tmpy;\n\terd0[16,8] = tmpd;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\ttmpd = tmpx - tmpy;\n\terd0[8,8] = tmpd;\n\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\ttmpd = tmpx - tmpy;\n\terd0[0,8] = tmpd;\n}\n\n:PSUB.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x201 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:2 = tmpx - tmpy;\n\terd0[16,16] = tmpd;\n\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\ttmpd = tmpx - tmpy;\n\terd0[0,16] = tmpd;\n}\n\n:PSUBADD.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x85 & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] {\n\ttmp:2 = PXPART - PYPART;\n\terd0[16,16] = tmp;\n\ttmp = PXPART + PYPART;\n\terd0[0,16] = tmp;\n}\n\n:PSUBADDH.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x8b & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] {\n\ttmp:4 = sext(PXPART) - sext(PYPART);\n\ttmp = tmp s>> 1;\n\terd0[16,16] = tmp:2;\n\ttmp = sext(PXPART) + sext(PYPART);\n\ttmp = tmp s>> 1;\n\terd0[0,16] = tmp:2;\n}\n\n:PSUBADDS.UH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x89 & PXPART & PYPART & erd0 {\n\ttmpx:2 = PXPART;\n\ttmpy:2 = PYPART;\n\ttmpd:4 = 0;\n\tsatsubuh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\tsatadduh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBADDS.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x87 & PXPART & PYPART & erd0 {\n\ttmpx:2 = PXPART;\n\ttmpy:2 = PYPART;\n\ttmpd:4 = 0;\n\tsatsubsh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\tsataddsh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBH.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x237 & erd0 {\n\ttmpx:2 = zext(rx9[24,8]);\n\ttmpy:2 = zext(ry0[24,8]);\n\ttmpd:2 = tmpx - tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[24,8] = tmpd:1;\n\n\ttmpx = zext(rx9[16,8]);\n\ttmpy = zext(ry0[16,8]);\n\ttmpd = tmpx - tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = zext(rx9[8,8]);\n\ttmpy = zext(ry0[8,8]);\n\ttmpd = tmpx - tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[8,8] = tmpd:1;\n\n\ttmpx = zext(rx9[0,8]);\n\ttmpy = zext(ry0[0,8]);\n\ttmpd = tmpx - tmpy;\n\ttmpd = tmpd >> 1;\n\terd0[0,8] = tmpd:1;\n}\n\n:PSUBH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20d & erd0 {\n\ttmpx:4 = sext(rx9[16,16]);\n\ttmpy:4 = sext(ry0[16,16]);\n\ttmpd:4 = tmpx - tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[16,16] = tmpd:2;\n\n\ttmpx = sext(rx9[0,16]);\n\ttmpy = sext(ry0[0,16]);\n\ttmpd = tmpx - tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBS.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x235 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:2 = 0;\n\tsatsubub(tmpx,tmpy,tmpd);\n\terd0[24,8] = tmpd:1;\n\t\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\tsatsubub(tmpx,tmpy,tmpd);\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\tsatsubub(tmpx,tmpy,tmpd);\n\terd0[8,8] = tmpd:1;\n\t\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\tsatsubub(tmpx,tmpy,tmpd);\n\terd0[0,8] = tmpd:1;\n}\n\n:PSUBS.SB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x233 & erd0 {\n\ttmpx:1 = rx9[24,8];\n\ttmpy:1 = ry0[24,8];\n\ttmpd:2 = 0;\n\tsatsubsb(tmpx,tmpy,tmpd);\n\terd0[24,8] = tmpd:1;\n\n\ttmpx = rx9[16,8];\n\ttmpy = ry0[16,8];\n\tsatsubsb(tmpx,tmpy,tmpd);\n\terd0[16,8] = tmpd:1;\n\n\ttmpx = rx9[8,8];\n\ttmpy = ry0[8,8];\n\tsatsubsb(tmpx,tmpy,tmpd);\n\terd0[8,8] = tmpd:1;\n\t\n\ttmpx = rx9[0,8];\n\ttmpy = ry0[0,8];\n\tsatsubsb(tmpx,tmpy,tmpd);\n\terd0[0,8] = tmpd:1;\n}\n\n:PSUBS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x209 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:4 = 0;\n\tsatsubuh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\tsatsubuh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x205 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[16,16];\n\ttmpd:4 = 0;\n\tsatsubsh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[0,16];\n\tsatsubsh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBX.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x203 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[0,16];\n\ttmpd:2 = tmpx - tmpy;\n\terd0[16,16] = tmpd;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[16,16];\n\ttmpd = tmpx - tmpy;\n\terd0[0,16] = tmpd;\n}\n\n:PSUBXH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20f & erd0 {\n\ttmpx:4 = sext(rx9[16,16]);\n\ttmpy:4 = sext(ry0[0,16]);\n\ttmpd:4 = tmpx - tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = sext(rx9[0,16]);\n\ttmpy = sext(ry0[16,16]);\n\ttmpd = tmpx - tmpy;\n\ttmpd = tmpd s>> 1;\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBXS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20b & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[0,16];\n\ttmpd:4 = 0;\n\tsatsubuh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[16,16];\n\tsatsubuh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PSUBXS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x207 & erd0 {\n\ttmpx:2 = rx9[16,16];\n\ttmpy:2 = ry0[0,16];\n\ttmpd:4 = 0;\n\tsatsubsh(tmpx,tmpy,tmpd);\n\terd0[16,16] = tmpd:2;\n\t\n\ttmpx = rx9[0,16];\n\ttmpy = ry0[16,16];\n\tsatsubsh(tmpx,tmpy,tmpd);\n\terd0[0,16] = tmpd:2;\n}\n\n:PUNPCKUB.H erd0, rs9^PUPART is op13_3=0x7 & rs9 & op0_9=0x0 ; eop5_11=0x124 & PUPART & erd0 {\n\ttmp:2 = PUPART;\n\ttmph:1 = tmp[8,8];\n\ttmpl:1 = tmp[0,8];\n\ttmp = zext(tmph);\n\terd0[16,16] = tmp;\n\ttmp = zext(tmpl);\n\terd0[0,16] = tmp;\n}\n\n:PUNPCKSB.H erd0, rs9^PUPART is op13_3=0x7 & rs9 & op0_9=0x0 ; eop5_11=0x125 & PUPART & erd0 {\n\ttmp:2 = PUPART;\n\ttmph:1 = tmp[8,8];\n\ttmpl:1 = tmp[0,8];\n\ttmp = sext(tmph);\n\terd0[16,16] = tmp;\n\ttmp = sext(tmpl);\n\terd0[0,16] = tmp;\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr32a_system_control.sinc", "content": "#---------------------------------------------------------------------\n# 8.3.10 System/Control\n#---------------------------------------------------------------------\n\n#---------------------------------------------------------------------\n# SR{cond} - Set Register Conditionally\n# I. cond4 -> {eq,ne,hs,lo,ge,lt,mi,pl,ls,gt,le,hi,vs,vc,qs,al} \n# d -> {0, 1, ..., 15}\n#---------------------------------------------------------------------\n\n# SR{cond} Format I\n# Operation: if (cond4) Rd <- 1; else Rd <- 0;\n# Syntax: SR{cond4} Rd\n# 0101 1111 cccc dddd\n\n:SR^{COND_4_4} rd0 is op8_8=0x5f & rd0 & COND_4_4 {\n rd0 = 0;\n build COND_4_4;\n rd0 = 1;\n}\n\n:BREAKPOINT \t\t\t\t\tis op0_16=0xd673 {\n\ttrap();\n}\n\n:CACHE rd0[disp0_11],eop11_5\tis op4_12=0xF41 & rd0 ; disp0_11 & eop11_5 {\n\ttmpa:4 = disp0_11;\n\ttmpb:4 = eop11_5;\n\tcacheOp(rd0,tmpa,tmpb);\n}\n\n:CSRF imm4_5 \t\t\t\t\tis op9_7=0x6a & op0_4=0x3 & imm4_5 {\n\ttmp:4 = 1 << imm4_5;\n\tSR = SR & ~tmp;\n\tSRTOFLAGS();\n}\n\n:CSRFCZ imm4_5 \t\t\t\t\tis op9_7=0x68 & imm4_5 & op0_4=0x3 {\n\ttmp:1 = ((SR >> imm4_5) & 0x1) != 0;\n\tC = tmp;\n\tZ = tmp;\n\tCZTOSR();\n}\n\n:FRS is op0_16=0xd743 { }\n\n:MFSR rd0,sysreg\t\t\t\tis op4_12=0xE1B & rd0 ; eop8_8=0 & sysreg {\n\trd0 = sysreg;\n}\n\n:MTSR sysreg,rs0\t\t\t\tis op4_12=0xE3B & rs0 ; eop8_8=0 & sysreg {\n\tsysreg = rs0;\n}\n\n:MFDR rd0, dbgreg \tis op4_12=0xe5b & rd0 ; eop8_8=0x0 & dbgreg {\n\ttmp:1 = dbgreg;\n\tMoveFromDebugReg(rd0,tmp);\n}\n\n:MTDR dbgreg, rs0 \tis op4_12=0xe7b & rs0 ; eop8_8=0x0 & dbgreg {\n\ttmp:1 = dbgreg;\n\tMoveToDebugReg(rs0,tmp);\n}\n\n:MUSFR rs0 \t\tis op4_12=0x5d3 & rs0 {\n\tSR = (SR & 0xFFFFFFF0) | (rs0 & 0xF);\n\tSRTOLOWFLAGS();\n}\n\n:MUSTR rd0 \t\tis op4_12=0x5d2 & rd0 {\n\trd0 = SR & 0xF;\n}\n\n:NOP\t\t\t\t\t\t\tis op0_16=0xD703 {}\n# I found gcc assembler will also use an add r0,r0 for a nop which is an all 0 opcode\n:NOP\t\t\t\t\t\t\tis op0_16=0 {}\n\n:PREF rp0[disp_16] is op4_12=0xf21 & rp0 ; disp_16 {\n\ttmpa:2 = disp_16;\n\ttmp:4 = rp0 + sext(tmpa);\n\tCacheFetch(tmp);\n}\n\nSLGM: val\t\t\tis disp_8 [ val = disp_8 << 0; ] { export *[const]:1 val; }\nSLGM: val\t\t\tis eb7=1 & disp_8 [ val = disp_8 << 0; ] { GM = 0; export *[const]:1 val; } \n:SLEEP SLGM \t\tis op0_16=0xe9b0 ; eop8_8=0x0 & SLGM {\n\tdoSleep(SLGM);\n}\n\n:SSRF imm4_5 \t\t\t\t\tis op9_7=0x69 & op0_4=0x3 & imm4_5 {\n\ttmp:4 = 1 << imm4_5;\n\tSR = SR | tmp;\n\tSRTOFLAGS();\n}\n\n:SYNC eop0_8 \tis op0_16=0xebb0 ; eop8_8=0x0 & eop0_8 {\n\ttmp:1 = eop0_8;\n\tSynchMemory(tmp);\n}\n\n:TLBR is op0_16=0xd643 {\n\tReadTLBEntry();\n}\n\n:TLBS is op0_16=0xd653 {\n\tSearchTLBEntry();\n}\n\n:TLBW is op0_16=0xd663 {\n\tWriteTLBEntry();\n}\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8.ldefs", "content": "\n\n\n\n \n AVR8 with 16-bit word addressable code space\n \n \n \n \n \n \n \n \n AVR8 with 22-bit word addressable with EIND code space\n \n \n \n \n \n AVR8 for an Atmega 256\n \n \n \n \n \n \n \n AVR8 for an Xmega\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8.opinion", "content": "\n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8.pspec", "content": "\n\n\n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n \n \n \n \n \n\n\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8.sinc", "content": "# sleigh specification for the avr8\n#\n# Currently designed for ATMega64 in non-ATmel103 configuration\n# - 0x20-0xff as IO memory, rather than 0x20-0x5f\n#\n# This is a ATMega64 with a 64k sized memory\n# Other parts available have a 4M sized memory so that stack \n# pointer would be three bytes instead\n\ndefine endian=little;\n\n# Declaring space to be word-sized... alternative is to do byte sized\ndefine alignment=2;\n\n# Force fusion of two byte operations in a row by decoding as words\n#@define FUSION \"\"\n#define where the IO space is mapped if not specified\n@ifndef IO_START\n@define IO_START \"0x20\"\n@define EIND \"0x5c\"\n@endif\n\n#define where the registers are located if not specified\n@ifndef REGISTER_SPACE\n@define REGISTER_SPACE \"mem\"\n@endif\n\n# NOTE: DATASIZE other than 2 is not supported yet\n# more changes to mem load/store are necessary\n@ifndef DATASIZE\n@define DATASIZE \"2\"\n@endif\n\n# mem space should really be the default, but the loading scripts will\n# prefer the code space as the default. By being explicit for every\n# instruction, we can eliminate the ambiguity for at least the\n# decompiler. None-the-less, other than when loading the binary into\n# Ghidra, it's still preferable to see the name of IO locations used,\n# rather than code addresses, so leave mem space as the default.\n\ndefine space code type=ram_space size=$(PCBYTESIZE) wordsize=2 default;\ndefine space register type=register_space size=2;\ndefine space mem type=ram_space size=$(DATASIZE) wordsize=1;\n\n# this is a byte address space that should be overlayed on top of the code space\ndefine space codebyte type=ram_space size=$(PCBYTESIZE) wordsize=1;\n\n# Using decimal rather than hex to match specs\n# General registers start at 0 in the iospace for earlier avr8 processors\n# In the Xmega line, they are not accessible in mem, and are in a register space\n#\ndefine $(REGISTER_SPACE) offset=0 size=1 [\n\tR0 R1 R2 R3 R4 R5 R6 R7 R8 R9\n\tR10 R11 R12 R13 R14 R15 R16 R17 R18 R19\n\tR20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi\n\tZlo Zhi\n];\n\ndefine $(REGISTER_SPACE) offset=0 size=2 [\n\tR1R0 R3R2 R5R4 R7R6 R9R8\n\tR11R10 R13R12 R15R14 R17R16 R19R18\n\tR21R20 R23R22 R25R24\n\tX Y Z\n];\n\ndefine $(REGISTER_SPACE) offset=18 size=8 [\n R25R24R23R22R21R20R19R18\n];\n\ndefine $(REGISTER_SPACE) offset=0 size=8 [\n\tR7R6R5R4R3R2R1R0\n\tR15R14R13R12R11R10R9R8\n];\n\n# Technically, the stack pointer is in the i/o space so should be addressable with the\n# rest of the i/o registers. However, Ghidra does not react well to the stack pointer\n# being indirectly addressable so we're making an exception.\ndefine register offset=0x3D size=1 [ SPL SPH ];\ndefine register offset=0x3D size=2 [ SP ];\n\ndefine register offset=0x42 size=$(PCBYTESIZE) [ PC ];\n\ndefine register offset=0x80 size=1 [\n\tCflg Zflg Nflg Vflg Sflg Hflg Tflg Iflg SKIP\n];\n\n#####################################\n# Some AVR processors may have different io layouts not just different io.\n# \n# AVR processors with more than 64 KiB of RAM make use of the RAMP- registers\n# to act as the high bits where the X, Y, or Z registers are used, or in direct\n# addressing instructions.\n#\n# TODO: incorporate the use of RAMPX, RAMPY, RAMPZ in the LD, ST instructions\n# ELPM, and LDS instructions use RAMPZ and RAMPD\n#\n# These IO registers need to be accessible to sleigh instruction PCODE\n# so they are defined here. The bulk of the IO registers are defined\n# as labels in the appropriate .pspec file.\n\n\n\ndefine mem offset=$(IO_START) size = 1 [\n# IO_START + 0x00\n\t _ _ _ _ _ _ _ _\n\t _ _ _ _ _ _ _ _\n# IO_START + 0x10\n\t _ _ _ _ _ _ _ _\n\t _ _ _ _ _ _ _ _\n\t \n# IO_START + 0x20\n\t _ _ _ _ _ _ _ _\n\t _ _ _ _ _ _ _ _\n# IO_START + 0x30\t \t \n\t _ _ _ _ _ _ _ _\n\t RAMPD RAMPX RAMPY RAMPZ _ _ _ SREG\n];\n\n\n# If the AVR processor has more than 128 KiB of ROM, the processor will support the EIND\n# register along with the EIJMP and EICALL extended instructions.\n@if HASEIND == \"1\"\ndefine mem offset=$(EIND) size=1 [ EIND ];\n\n@endif\n\n##############################\n\n# Define context bits\ndefine register offset=0x90 size=4 contextreg;\n\ndefine context contextreg\n\tuseSkipCond = (0,0) noflow # =1 skip instruction if SKIP register is true\n\t\t# transient context\n\tphase = (1,1) # =0 check for useSkipCond, =1 parse instruction\n;\n\n## Following 8051 example rather than define bitrange \n# Works better as distinct variables\n@define Cflag \"Cflg\"\n@define Zflag \"Zflg\"\n@define Nflag \"Nflg\"\n@define Vflag \"Vflg\"\n@define Sflag \"Sflg\"\n@define Hflag \"Hflg\"\n@define Tflag \"Tflg\"\n@define Iflag \"Iflg\"\n\n\ndefine token opword (16)\n\tophi16 = ( 0,15)\n\tophi9 = ( 7,15)\n\tophi8 = ( 8,15)\n\tophi7 = ( 9,15)\n\tophi6 = (10,15)\n\tophi5 = (11,15)\n\tophi4 = (12,15)\n\tophi2 = (14,15)\n\topbit13 = (13,13)\n\topbit12 = (12,12)\n\topbit10 = (10,10)\n\topbit9 = ( 9, 9)\n\topbit8 = ( 8, 8)\n\topbit7 = ( 7, 7)\n\topbit3 = ( 3, 3)\n\topbit2 = ( 2, 2)\n\topbit0 = ( 0, 0)\n\toplow12 = ( 0,11)\n\toplow12signed = ( 0,11) signed\n\toplow4 = ( 0, 3)\n\toplow3_flag = ( 0, 2)\n\toplow3 = ( 0, 2)\n\toplow2 = ( 0, 1)\n\top1to3 = ( 1, 3)\n\top2to3 = ( 2, 3)\n\top3to7 = ( 3, 7)\n\top4to8 = ( 4, 8)\n\top4to6 = ( 4, 6)\n\top4to6_flag = ( 4, 6)\n\top6to7 = ( 6, 7)\n\top8to10 = ( 8,10)\n\top9to10 = ( 9,10)\n\top10to11 = (10,11)\n\tRdHi = ( 4, 7)\n\tRdHi3 = ( 4, 6)\n\tRdFull = ( 4, 8)\n\tRrHi = ( 0, 3)\n\tRrHi3 = ( 0, 2)\n\tRrLow = ( 0, 3)\n\tRrHiLowSel = ( 9, 9)\n\tRdw2 = ( 4, 5)\n\tRdw4 = ( 4, 7)\n\tRrw4 = ( 0, 3)\n\tRstq = ( 3, 3)\n\tRstPtr = ( 2, 3)\n\top0to3 = ( 0, 3)\n\top3to9signed = ( 3, 9) signed\n\top4to7 = ( 4, 7)\n\top8to11 = ( 8,11)\n;\ndefine token immtok(16)\n\tnext16 = (0,15)\n;\n\ndefine token opfusion16(32)\n\top1hi4 = (12,15)\n\top2hi4 = (28,31)\n\top1hi6 = (10,15)\n\top2hi6 = (26,31)\n\top1low4 = ( 0, 3)\n\top2low4 = (16,19)\n\top1bits0to3 = ( 0, 3)\n\top2bits0to3 = (16,19)\n\top1bits1to3 = ( 1, 3)\n\top2bits1to3 = (17,19)\n\top1bits4to8 = ( 4, 8)\n\top2bits4to8 = (20,24)\n\top1bits5to7 = ( 5, 7)\n\top2bits5to7 = (21,23)\n\top1bits5to8 = ( 5, 8)\n\top2bits5to8 = (21,24)\n\top1bits8to11 = ( 8,11)\n\top2bits8to11 = (24,27)\n\top1bit0 = ( 0, 0)\n\top2bit0 = (16,16)\n\top1bit4 = ( 4, 4)\n\top2bit4 = (20,20)\n\top1bit9 = ( 9, 9)\n\top2bit9 = (25,25)\n\top1RdPair = ( 5, 8)\n\top1RdPairHi = ( 5, 7)\n\top1RrPairLow = ( 1, 3)\n\top1RrPairHi = ( 1, 3)\n\top1RrPairSel = ( 9, 9)\n;\n\ndefine token opfusion24(48)\n\tf3op1hi4 = (12,15)\n\tf3op2hi4 = (28,31)\n\tf3op3hi4 = (34,47)\n\tf3op1hi6 = (10,15)\n\tf3op2hi6 = (26,31)\n\tf3op3hi6 = (42,47)\n\tf3op1bits0to3 = ( 0, 3)\n\tf3op2bits0to3 = (16,19)\n\tf3op3bits0to3 = (32,35)\n\tf3op2bits4to7 = (20,23)\n\tf3op1bits5to7 = ( 5, 7)\n\tf3op3bits5to7 = (37,39)\n\tf3op1bits8to11 = ( 8,11)\n\tf3op2bits8to11 = (24,27)\n\tf3op1bit4 = ( 4, 4)\n\tf3op3bit4 = (36,36)\n\tf3op3bit8 = (40,40)\n\tf3op3bit9 = (41,41)\n\tf3op1RdPairHi = ( 5, 7)\n\tf3op2RdHi = (20,23)\n;\n\ndefine token opfusionLdsw(64) # lds lds\n\tldswop1hi7 = ( 9,15)\n\tldswop2hi7 = (41,47)\n\tldswop1low4 = ( 0, 3)\n\tldswop2low4 = (32,35)\n\tldswop1bits5to8 = ( 5, 8)\n\tldswop2bits5to8 = (37,40)\n\tldswop1bit4 = ( 4, 4)\n\tldswop2bit4 = (36,36)\n\tldswop1bit16 = (16,16)\n\tldswop2bit16 = (48,48)\n\tldswop1imm15 = (17,31)\n\tldswop2imm15 = (49,63)\n\tldswop1imm6 = (17,22)\n\tldswop2imm6 = (49,54)\n\tldswop1imm16 = (16,31)\n\tldswop2imm16 = (48,63)\n\tldswop1RdPair = ( 5, 8)\n\tstswop2RdPair = (37,40)\n;\n\nattach variables [ oplow3_flag op4to6_flag ] [\n Cflg Zflg Nflg Vflg Sflg Hflg Tflg Iflg\n];\n\nattach variables [ RdHi RrHi f3op2RdHi ] [ \n R16 R17 R18 R19 \n R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi\n Zlo Zhi ]\n;\nattach variables [ RdHi3 RrHi3 ] [\n R16 R17 R18 R19 \n R20 R21 R22 R23\n];\nattach variables [ RrLow ] [\n R0 R1 R2 R3 R4 R5 R6 R7 R8 R9\n R10 R11 R12 R13 R14 R15 \n];\nattach variables [ RdFull ] [\n R0 R1 R2 R3 R4 R5 R6 R7 R8 R9\n R10 R11 R12 R13 R14 R15 \n R16 R17 R18 R19 \n R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi\n Zlo Zhi\n];\nattach variables [ Rdw2 ] [\n R25R24 X Y Z\n];\nattach variables [ Rstq ] [\n Z Y \n];\nattach variables [ RstPtr ] [\n Z _ Y X\n];\nattach variables [ Rdw4 Rrw4 op1RdPair ldswop1RdPair stswop2RdPair ] [\n R1R0 R3R2 R5R4 R7R6 R9R8 \n R11R10 R13R12 R15R14 R17R16 R19R18 \n R21R20 R23R22 R25R24 \n X Y Z \n];\nattach variables [ op1RrPairLow ] [\n R1R0 R3R2 R5R4 R7R6 R9R8 \n R11R10 R13R12 R15R14 \n];\nattach variables [ op1RrPairHi op1RdPairHi f3op1RdPairHi ] [\n R17R16 R19R18 \n R21R20 R23R22 R25R24 \n X Y Z \n];\n\nRrFull: RrHi is RrHiLowSel=1 & RrHi { tmp:1 = RrHi; export tmp; }\nRrFull: RrLow is RrHiLowSel=0 & RrLow { tmp:1 = RrLow; export tmp; }\n\n# Alternative: try using some subcontructors\nop1RrPair: op1RrPairHi is op1RrPairSel=1 & op1RrPairHi { tmp:2 = op1RrPairHi; export tmp; }\nop1RrPair: op1RrPairLow is op1RrPairSel=0 & op1RrPairLow { tmp:2 = op1RrPairLow; export tmp; }\n\n# I'm uneasy at these... as they require the top of the stack\n# to know what size element to reserve before the push.\n# The docs should probably say that the top of the stack byte is unused...\n#\n# The processor is post-decremented, and because of the way the compiler\n# manipulates the stack pointer it's important to get this correct.\n@if PCBYTESIZE == \"2\"\nmacro pushPC(val) {\n SP = SP - 1;\n *[mem]:2 SP = val;\n\tSP = SP - 1;\n}\n\t\nmacro popPC(val) {\n SP = SP + 1;\n\tval = *[mem]:2 SP;\n\tSP = SP + 1;\n}\n\n@else # PCBYTESIZE == 3\nmacro pushPC(val) {\n\tSP = SP - 2;\n\t*[mem]:3 SP = val;\n\tSP = SP - 1;\n}\n\t\nmacro popPC(val) {\n SP = SP + 1;\n\tval = *[mem]:3 SP;\n\tSP = SP + 2;\n}\n\n@endif\n\t\nmacro push8(val) {\n\t*[mem]:1 SP = val;\n\tSP = SP -1;\n}\n\t\nmacro pop8(val) {\n\tSP = SP + 1;\n\tval = *[mem]:1 SP;\n}\n\n\n\n# .slaspec shortcoming: Hflag isn't computed for most results\nmacro setSflag() {\n\t$(Sflag) = $(Nflag) ^ $(Vflag);\n}\n\nmacro setResultFlags(result) {\n\t$(Nflag) = (result s< 0);\n\t$(Zflag) = (result == 0x0);\n\tsetSflag();\n}\n\nmacro doSubtract(pre,sub,res) {\n\tlocal x = pre - sub;\n\t$(Vflag) = sborrow(pre,sub);\n\t$(Cflag) = (pre < sub);\n\tsetResultFlags(x);\n\t$(Sflag) = pre s< sub;\n\tres = x;\n}\n\nmacro doSubtractWithCarry(pre,sub,res) {\n\tlocal partial = pre - sub;\n\tlocal subCarry = sub + $(Cflag);\n\tlocal x = pre - subCarry;\n\tlocal oldZflag = $(Zflag);\n\t$(Vflag) = sborrow(pre,sub) ^^ sborrow(partial, $(Cflag));\n\t$(Cflag) = (pre < sub) || (partial < $(Cflag));\n\tsetResultFlags(x);\n\t$(Sflag) = $(Nflag)^$(Vflag);\n\t$(Zflag) = oldZflag & $(Zflag);\n\tres = x;\n}\n\nmacro setMulFlags(res) {\n\t$(Cflag) = ((res & 0x8000) != 0);\n\t$(Zflag) = (res == 0);\n}\n\nmacro loadSREG(reg) {\n\treg = (zext(Cflg==1) << 0) | (zext(Zflg==1) << 1) | (zext(Nflg==1) << 2) | (zext(Vflg==1) << 3) | (zext(Sflg==1) << 4) | (zext(Hflg==1) << 5) | (zext(Tflg==1)<<6) | (zext(Iflg==1) << 7);\n SREG = reg;\n}\n\nmacro storeSREG(val) {\n\tCflg = ((val>> 0) & 1);\n\tZflg = ((val>> 1) & 1);\n\tNflg = ((val>> 2) & 1);\n\tVflg = ((val>> 3) & 1);\n\tSflg = ((val>> 4) & 1);\n\tHflg = ((val>> 5) & 1);\n\tTflg = ((val>> 6) & 1);\n\tIflg = ((val>> 7) & 1);\n\tSREG = val;\n}\n\n# Handle possible skip instruction\n# This next line is a NOP except for the phase, which is never really checked.\n# A better fix may be to use -l, and ensure phase=1 is checked on the base constructors.\n:^instruction is phase=0 & useSkipCond=0 & instruction [ phase=1; ] { build instruction; }\n:^instruction is phase=0 & useSkipCond=1 & instruction [ phase=1; ] {\n\tif (SKIP) goto inst_next;\n\tbuild instruction;\n}\n\n# K8 is immediate for Rd,K8 forms\nK8: val is op0to3 & op8to11 [ val = (op8to11 << 4) | op0to3; ] { tmp:1 = val; export tmp; }\n\n@ifdef FUSION\n\nK16fuse: val is op1bits0to3 & op1bits8to11 & op2bits0to3 & op2bits8to11 [ val = (((op2bits8to11 << 4) | op2bits0to3) << 8) | ((op1bits8to11 << 4) | op1bits0to3); ] { tmp:2 = val; export tmp; }\n\nf3cmpK16: val is f3op1bits0to3 & f3op1bits8to11 & f3op2bits0to3 & f3op2bits8to11 [ val = (((f3op2bits8to11 << 4) | f3op2bits0to3) << 8) | ((f3op1bits8to11 << 4) | f3op1bits0to3); ] { tmp:2 = val; export tmp; }\nf3cmpK8: val is f3op2bits0to3 & f3op2bits8to11 [ val = (f3op2bits8to11 << 4) | f3op2bits0to3; ] { tmp:1 = val; export tmp; }\n\n@endif\n\nrel7addr: rel is op3to9signed [ rel = (op3to9signed + inst_next);] { \n export *[code]:2 rel;\n}\n\nrel7dst: byteOffset is op3to9signed & rel7addr [ byteOffset = (op3to9signed + inst_next) << 1;] { \n export rel7addr;\n}\n\nrel12addr: rel is oplow12signed [ rel = oplow12signed + inst_start + 1; ] { \n export *[code]:2 rel;\n}\n\nrel12dst: byteOffset is oplow12signed & rel12addr [ byteOffset = (oplow12signed + inst_start + 1) << 1; ] { \n export rel12addr;\n}\n\nabs22addr: loc is op4to8 & opbit0; next16 [ loc = (op4to8 << 17) | (opbit0 << 16) | next16; ] { \n export *[code]:2 loc;\n}\n\nabs22dst: byteOffset is (op4to8 & opbit0; next16) & abs22addr [ byteOffset = ((op4to8 << 17) | (opbit0 << 16) | next16) << 1; ] { \n export abs22addr;\n}\n\nnext16memPtrVal1: next16 is next16 { export *[mem]:1 next16; }\n\n@if DATASIZE == \"3\"\nnext24constVal: next16 is next16 { export *[const]:$(DATASIZE) next16; }\n@endif\n\n@ifdef FUSION\n\nldswMemPtrVal2: ldswop1imm16 is ldswop1imm16 { export *[mem]:2 ldswop1imm16; }\n\nstswMemPtrVal2: ldswop2imm16 is ldswop2imm16 { export *[mem]:2 ldswop2imm16; }\n\n@endif\n\n# K6 is used in dword operation\nK6: val is oplow4 & op6to7 [ val = (op6to7 << 4) | oplow4; ] { tmp:1 = val; export tmp; }\n\n# K7 is used by lds\nK7addr: val is oplow4 & op9to10 & opbit8 [ val = ((1 ^ opbit8) << 7) | (opbit8 << 6) | (op9to10 << 4) | oplow4; ] {\n\texport *[mem]:1 val;\n}\n\n# Join against various spaces for dataspace...\n# #####################################################################################\n# COMMENTING OUT BECAUSE \"subtable symbol K7addr is not allowed in context block\"\n#K7Ioaddr: val is K7addr [ val = K7addr - 0x20; ] { tmp:1 = val; export tmp; }\n# #####################################################################################\n# COMMENTING OUT BECAUSE \"Subtable symbol K7Ioaddr is not allowed in context block\"\n#A7Ioaddr: val is K7Ioaddr [ val = (K7Ioaddr | 0x00) + 0x20 ; ] { export *[mem]:1 val; }\nAio6: val is oplow4 & op9to10 [ val = ((op9to10 << 4) | oplow4) + $(IO_START); ] { export *[mem]:1 val; }\nAio5: val is op3to7 [ val = (op3to7 | 0x00) + $(IO_START); ] { export *[mem]:1 val; }\n\nq6: val is oplow3 & op10to11 & opbit13 [ val = (opbit13 << 5) | (op10to11 << 3) | oplow3; ] { tmp:1 = val; export tmp; }\n\n@ifdef FUSION\n\n# Predicates to verify that fusion will be valid here.\n# We just want to construct these. The rules are not null to avoid a NOP bug with sleigh\nfusion16rrrrPred: val is op1bit0=0 & op2bit0=1 & op1bit4=0 & op2bit4=1 & op1bit9=op2bit9 & op1bits5to8=op2bits5to8 & op1bits1to3=op2bits1to3 [ val = 0; ] { tmp:2=val; export tmp; }\n\nfusion16rkrkPred: val is op1bits5to7=op2bits5to7 & op1bit4=0 & op2bit4=1 [ val=0; ] { tmp:2 = val; export tmp; }\n\nf3cmpPairPred: val is f3op1bits5to7=f3op3bits5to7 & f3op1bit4=0 & f3op3bit4=1 & f3op3bit8=1 [ val=0; ] { tmp:2 = val; export tmp; }\n\nf3cmpLdiPred: val is f3op3bit9=1 & f3op3bits0to3=f3op2bits4to7 [ val=0; ] { tmp:2 = val; export tmp; }\n\nldswPairPred: val is ldswop1bit4=0 & ldswop2bit4=1 & ldswop1bits5to8=ldswop2bits5to8 [ val=0; ] { tmp:2 = val; export tmp; }\n\nstswPairPred: val is ldswop1bit4=1 & ldswop2bit4=0 & ldswop1bits5to8=ldswop2bits5to8 [ val=0; ] { tmp:2 = val; export tmp; }\n\n# would like to check this for const pair, but hangs sleigh compiler: ldswop1imm15=ldswop2imm15\n# So check as a few in a row \n# Not any better & ldswop1imm5b=ldswop2imm5b & ldswop1imm5c=ldswop2imm5c\nldswConstPairPred: val is ldswop1bit16=0 & ldswop2bit16=1 & ldswop1imm6=ldswop2imm6 [ val=0; ] { tmp:2 = val; export tmp; }\n\nstswConstPairPred: val is ldswop1bit16=1 & ldswop2bit16=0 & ldswop1imm6=ldswop2imm6 [ val=0; ] { tmp:2 = val; export tmp; }\n\n@endif\n\ndefine pcodeop todo;\ndefine pcodeop todoflow;\ndefine pcodeop todoflags;\ndefine pcodeop todotst;\n\ndefine pcodeop break;\n\n@ifdef FUSION\n# add followed by adc\n:addw op1RdPair,op1RrPair is phase=1 & op1hi6=0x3 & op2hi6=0x7 & op1RdPair & op1RrPair & fusion16rrrrPred {\n\tlocal pre = op1RdPair;\n\tlocal post = op1RdPair + op1RrPair;\n\t$(Cflag) = carry(op1RdPair,op1RrPair);\n\t$(Vflag) = scarry(pre,op1RrPair);\n\top1RdPair = post;\n\tsetResultFlags(post);\n}\n\n@endif\n# Rd,Rr\n:adc RdFull,RrFull is phase=1 & ophi6=0x7 & RdFull & RrFull {\n\tlocal res = RdFull + RrFull + $(Cflag);\n\t$(Cflag) = carry(RdFull, RrFull) || carry(RdFull + RrFull, $(Cflag));\n\t$(Vflag) = scarry(RdFull, RrFull) ^^ scarry(RdFull + RrFull, $(Cflag));\n\tsetResultFlags(res);\n\tRdFull = res;\n}\n# Rd,Rr\n:add RdFull,RrFull is phase=1 & ophi6=0x3 & RdFull & RrFull {\n\tlocal res = RdFull + RrFull;\n\t$(Cflag) = carry(RdFull,RrFull);\n\t$(Vflag) = scarry(RdFull,RrFull);\n\tsetResultFlags(res);\n\tRdFull = res;\n}\n# adiw Rd+1:Rd,K6\n:adiw Rdw2,K6 is phase=1 & ophi8=0x96 & Rdw2 & K6 {\n\tlocal pre = Rdw2;\n\tRdw2 = Rdw2 + zext(K6);\n\t$(Cflag) = carry(pre,zext(K6));\n\t$(Vflag) = scarry(Rdw2,zext(K6));\n\tsetResultFlags(Rdw2);\n}\n# and Rd,Rr\n:and RdFull,RrFull is phase=1 & ophi6=8 & RdFull & RrFull {\n\tRdFull = RdFull & RrFull;\n\t$(Vflag) = 0;\n\tsetResultFlags(RdFull);\n}\n# andi Rd,K\n:andi RdHi,K8 is phase=1 & ophi4=7 & RdHi & K8 {\n\tRdHi = RdHi & K8;\n\t$(Vflag) = 0;\n\tsetResultFlags(RdHi);\n}\n# asr Rd\n:asr RdFull is phase=1 & ophi7=0x4a & oplow4=0x5 & RdFull { #done\n\t$(Cflag) = RdFull & 0x01;\n\tRdFull = RdFull s>> 1;\n\t$(Nflag) = (RdFull & 0x80) == 0x80;\n\t$(Vflag) = $(Nflag) ^ $(Cflag);\n\tsetResultFlags(RdFull);\n}\n\n# bclr s\n:bclr op4to6_flag is phase=1 & ophi9=0x129 & oplow4=0x4 & op4to6_flag { #done\n\top4to6_flag = 0;\n}\n\n# bld Rd,b\n:bld RdFull,oplow3 is phase=1 & ophi7=0x7c & opbit3=0 & RdFull & oplow3 {\n\tlocal b = $(Tflag) << oplow3;\n\tlocal mask = 0xff ^ (1 << oplow3);\n\tRdFull = (RdFull & mask) | b;\n}\n# brbc s,k\n:brbc rel7dst,oplow3_flag is phase=1 & ophi6=0x3d & rel7dst & oplow3_flag {\n\tif (!oplow3_flag)\n goto rel7dst;\n}\n# brbs s,k (see prev instruction)\n:brbs rel7dst,oplow3_flag is phase=1 & ophi6=0x3c & rel7dst & oplow3_flag {\n\tif (oplow3_flag)\n goto rel7dst;\n}\n# brcs and brcc seem to be special cases of brbs\n:break is phase=1 & ophi16=0x9598 {\n\tbreak();\n}\n# Probably want to check for various decode logic for conditional branches...\n# ... specifically BRBS 1,k\n# breq k - really is BRBS 1,k\n# bset s\n:bset op4to6_flag is phase=1 & ophi9=(0x94<<1) & oplow4=0x8 & op4to6_flag {\n\top4to6_flag = 1;\n}\n# bst Rd,b\n:bst RdFull,oplow3 is phase=1 & ophi7=0x7d & opbit3=0 & RdFull & oplow3 {\n\t$(Tflag) = (RdFull >> oplow3) & 0x01;\n}\n# call k - todo - handle upper bits for 24 bit architecture\n:call abs22dst is phase=1 & (ophi7=0x4a & op1to3=0x7) ... & abs22dst {\n\ttmp:$(PCBYTESIZE) = inst_next >> 1;\n\tpushPC(tmp);\n\tPC = &abs22dst;\n\tcall abs22dst;\n}\n# cbi A,b\n:cbi Aio5,oplow3 is phase=1 & ophi8=0x98 & Aio5 & oplow3 {\n\tlocal x = Aio5;\n\tx = x & (0xff ^ (1 << oplow3));\n\tAio5 = x;\n}\n# cbr - not actual instruction\n\n# clc, clh, cli, cln ... variants on register clearing\n# sub bits give which bits in SREG to clear\n:clc is phase=1 & ophi16=0x9488 {\n\t$(Cflag) = 0;\n}\n:clh is phase=1 & ophi16=0x94d8 {\n\t$(Hflag) = 0;\n}\n:cli is phase=1 & ophi16=0x94f8 {\n\t$(Iflag) = 0;\n}\n:cln is phase=1 & ophi16=0x94a8 {\n\t$(Nflag) = 0;\n}\n:cls is phase=1 & ophi16=0x94c8 {\n\t$(Sflag) = 0;\n}\n:clt is phase=1 & ophi16=0x94e8 {\n\t$(Tflag) = 0;\n}\n:clv is phase=1 & ophi16=0x94b8 {\n\t$(Vflag) = 0;\n}\n:clz is phase=1 & ophi16=0x9498 {\n\t$(Zflag) = 0;\n}\n# clr Rd - really is EOR Rd, Rd\n:com RdFull is phase=1 & ophi7=0x4a & RdFull {\n\tRdFull = ~RdFull;\n\t$(Vflag) = 0;\n\t$(Cflag) = 1;\n\tsetResultFlags(RdFull);\n}\n:cp RdFull,RrFull is phase=1 & ophi6=0x05 & RdFull & RrFull {\n\tlocal x = RdFull - RrFull;\n\t$(Cflag) = (RdFull < RrFull);\n\t$(Vflag) = sborrow(RdFull,RrFull);\n\tsetResultFlags(x);\n# but doesn't set result into a register\n}\n:cpc RdFull,RrFull is phase=1 & ophi6=0x1 & RdFull & RrFull {\n\tlocal res = 0;\n\tdoSubtractWithCarry(RdFull,RrFull,res);\n\tres = res; # avoid warning\n}\n:cpi RdHi,K8 is phase=1 & ophi4=0x3 & RdHi & K8 {\n\tlocal res = 0;\n\tdoSubtract(RdHi,K8,res);\n\tres = res; # avoid warning\n}\n\n@ifdef FUSION\n# cpi; ldi; cpc sequence\n:cpiw f3op1RdPairHi,f3cmpK16\" ;ldi \"f3op2RdHi,f3cmpK8 is phase=1 & f3op1hi4=0x3 & f3op2hi4=0xe & f3op3hi6=0x1 & f3cmpPairPred & f3cmpLdiPred & f3op1RdPairHi & f3op2RdHi & f3cmpK16 & f3cmpK8 {\n\tlocal res = 3;\n\tdoSubtract(f3op1RdPairHi,f3cmpK16,res);\n\tf3op2RdHi = f3cmpK8;\n}\n# cp; cpc sequence\n:cpw op1RdPair,op1RrPair phase=1 & is op1hi6=0x5 & op2hi6=0x1 & fusion16rrrrPred & op1RdPair & op1RrPair {\n\tlocal res = op1RdPair - op1RrPair;\n\t$(Vflag) = sborrow(op1RdPair,op1RrPair);\n\t$(Cflag) = (op1RdPair < op1RrPair);\n\tsetResultFlags(res);\n\t$(Sflag) = op1RdPair s< op1RrPair;\n}\n\n@endif\n\n:cpse RdFull,RrFull is phase=1 & ophi6=0x4 & RdFull & RrFull [ useSkipCond=1; globalset(inst_next,useSkipCond); ] {\n\tSKIP = (RdFull == RrFull);\n}\n\n:dec RdFull is phase=1 & ophi7=0x4a & oplow4=0xa & RdFull {\n\t# doesn't set the C flag\n\t$(Vflag) = (RdFull == 0x80);\n\tRdFull = RdFull - 1;\n\tsetResultFlags(RdFull);\n}\n\ndefine pcodeop encrypt;\ndefine pcodeop decrypt;\n\n:des op4to7 is phase=1 & ophi8=0x94 & oplow4=0xb & op4to7 {\n\tval:1 = op4to7;\n\tlocal key:8 = R15R14R13R12R11R10R9R8;\n\tlocal result:16 = 0;\n\tif (!Hflg) goto ;\n\tresult = decrypt(R7R6R5R4R3R2R1R0, key, val);\n\tgoto ;\n\n\tresult = encrypt(R7R6R5R4R3R2R1R0, key, val);\n\n\tR7R6R5R4R3R2R1R0 = result(0);\n\tR15R14R13R12R11R10R9R8 = result(8);\n}\n\n@if HASEIND == \"1\"\n:eicall is phase=1 & ophi16=0x9519 {\n\tptr:$(PCBYTESIZE) = inst_next >> 1;\n\tpushPC(ptr);\n\tPC = zext(Z) | (zext(EIND) << 16);\n\tcall [PC];\n}\n\n:eijmp is phase=1 & ophi16=0x9419 {\n\tPC = zext(Z) | (zext(EIND) << 16);\n\tgoto [PC];\n}\n\n@endif\n\n@if PCBYTESIZE == \"3\"\n:elpm is phase=1 & ophi16=0x95d8 {\n\tptr:3 = zext(Z) | (zext(RAMPZ) << 16);\n\tlocal falseRead:1 = *[code]:2 (ptr >> 1);\n\tR0 = *[codebyte]:1 ptr;\n}\n\n:elpm RdFull, Z is phase=1 & ophi7=0x48 & oplow4=0x6 & RdFull & Z {\n\tptr:3 = zext(Z) | (zext(RAMPZ) << 16);\n local falseRead:1 = *[code]:1 (ptr >> 1);\n\tRdFull = *[codebyte]:1 ptr;\n}\n\nElpmPlus: Z^\"+\" is Z {}\n:elpm RdFull, ElpmPlus is phase=1 & ophi7=0x48 & oplow4=0x7 & RdFull & ElpmPlus {\n\tptr:3 = zext(Z) | (zext(RAMPZ) << 16);\n\tlocal falseRead:1 = *[code]:1 (ptr >> 1);\n\tRdFull = *[codebyte]:1 ptr;\n\tptr = ptr + 1;\n\tZ = ptr:2;\n\tRAMPZ = ptr[16,8];\n}\n\n@endif\n\n:eor RdFull,RrFull is phase=1 & ophi6=0x9 & RdFull & RrFull {\n\tRdFull = RdFull ^ RrFull;\n\t$(Vflag) = 0;\n\tsetResultFlags(RdFull);\n}\n\n# Manual uses fmul. I prefer fracmul to distinguish from floating point\n:fracmul RdHi,RrHi is phase=1 & ophi9=0x6 & opbit3=1 & RdHi & RrHi { todo(); }\n:fracmuls RdHi,RrHi is phase=1 & ophi9=0x7 & opbit3=0 & RdHi & RrHi { todo(); }\n:fracmulsu RdHi,RrHi is phase=1 & ophi9=0x7 & opbit3=1 & RdHi & RrHi { todo(); }\n\n:icall is phase=1 & ophi16=0x9509 {\n\tptr:$(PCBYTESIZE) = inst_next >> 1;\n\tpushPC(ptr);\n\tPC = zext(Z);\n\tcall [PC];\n}\n:ijmp is phase=1 & ophi16=0x9409 {\n\tPC = zext(Z);\n\tgoto [PC];\n}\n# in Rd,A\n:in RdFull,Aio6 is phase=1 & ophi5=0x16 & RdFull & Aio6 {\n\tRdFull = Aio6;\n}\n:in RdFull,SPL is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xd & SPL {\n\tRdFull = SPL;\n}\n:in RdFull,SPH is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xe & SPH {\n\tRdFull = SPH;\n}\n:in RdFull,SREG is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xf & SREG {\n\tloadSREG(RdFull);\n}\n\n:inc RdFull is phase=1 & ophi7=0x4a & oplow4=0x3 & RdFull {\n\t# inc doesn't set the C flag.\n\t$(Vflag) = RdFull == 0x7f;\n\tRdFull = RdFull + 1;\n\tsetResultFlags(RdFull);\n}\n:jmp abs22dst is phase=1 & (ophi7=0x4a & op1to3=0x6) ... & abs22dst {\n\tPC = &abs22dst;\n\tgoto abs22dst;\n}\n\n:lac Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x6 & Z & RdFull {\n\ttmp:1 = *[mem]:1 Z;\n\ttmp = tmp & (0xff - RdFull);\n\t*[mem]:1 Z = tmp;\n\tRdFull = tmp;\n}\n\n:las Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x5 & Z & RdFull {\n\ttmp:1 = *[mem]:1 Z;\n\ttmp = tmp | RdFull;\n\t*[mem]:1 Z = tmp;\n\tRdFull = tmp;\n}\n\n:lat Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x7 & Z & RdFull {\n\ttmp:1 = *[mem]:1 Z;\n\ttmp = tmp ^ RdFull;\n\t*[mem]:1 Z = tmp;\n\tRdFull = tmp;\n}\n\n# three forms, really just specifying the increment mode\n# ld Rd,X\n:ld RdFull,X is phase=1 & ophi7=0x48 & oplow4=0xc & X & RdFull {\n\ttmp:2 = X;\n\tRdFull = *[mem]:1 tmp;\n}\n# ld Rd,Y; ld Rd,Z\n# Special case of ldd +q below - will conflict with -i sleigh compile\n:ld RdFull,RstPtr is phase=1 & ophi7=0x40 & oplow3=0x0 & RdFull & RstPtr {\n\ttmp:2 = RstPtr;\n\tRdFull = *[mem]:1 tmp;\n}\n\n# ld Rd,Y+ ; ld Rd, X+; ld Rd, Z+\nLdPlus: RstPtr^\"+\" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; }\n:ld RdFull,LdPlus is phase=1 & ophi7=0x48 & oplow2=0x01 & RdFull & LdPlus {\n RdFull = *[mem]:1 LdPlus;\n}\n\n# ld Rd,-Y ; ld Rd, -X; ld Rd, -Z\nLdPredec: \"-\"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; }\n\n:ld RdFull,LdPredec is phase=1 & ophi7=0x48 & oplow2=0x02 & RdFull & LdPredec {\n\ttmp:2 = LdPredec;\n\tRdFull = *[mem]:1 tmp;\n}\n\n@ifndef AVTINY\n# ldd Rd,Y+q\n# ldd Rd,Z+q\nLddYZq: Rstq^\"+\"^q6 is phase=1 & Rstq & q6 { local ptr = Rstq + zext(q6); export ptr; }\n:ldd RdFull,LddYZq is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=0 & opbit3 & LddYZq & RdFull {\n RdFull = *[mem]:1 LddYZq;\n}\n@endif\n\n# Rd,K\n:ldi RdHi,K8 is phase=1 & ophi4=0xe & RdHi & K8 {\n\tRdHi = K8;\n}\n\n\n@ifdef AVTINY\n# lds Rd,k\n:lds RdHi,K7addr is phase=1 & ophi5=0x14 & RdHi & K7addr { \n RdHi = K7addr;\n}\n@elif DATASIZE == \"2\"\n# lds Rd,k\n:lds RdFull,next16memPtrVal1 is phase=1 & ophi7=0x48 & oplow4=0 & RdFull; next16memPtrVal1 {\n\tRdFull = next16memPtrVal1;\n}\n@else\n:lds RdFull,next24constVal is phase=1 & ophi7=0x48 & oplow4=0 & RdFull; next24constVal {\n\tlocal loc:$(DATASIZE) = (zext(RAMPD) << 16 | next24constVal);\n\tRdFull = *[mem]:1 loc;\n}\n@endif\n\n@ifdef FUSION\n# Fuse together consecuitive lds ; lds\n# \n:ldsw ldswop1RdPair,ldswMemPtrVal2 is phase=1 & ldswop1hi7=0x48 & ldswop2hi7=0x48 & ldswop1low4=0 & ldswop2low4=0 & ldswMemPtrVal2 & ldswop1RdPair & ldswPairPred & ldswConstPairPred {\n\tldswop1RdPair = ldswMemPtrVal2;\n}\n\n@endif\n\n# lpm R0\n:lpm R0 is phase=1 & ophi16=0x95c8 & R0 {\n\tptr:$(PCBYTESIZE) = zext(Z);\n\tlocal falseRead:1 = *[code]:1 (ptr >> 1);\n\tR0 = *[codebyte]:$(PCBYTESIZE) ptr;\n}\n# lpm Rd,Z\n:lpm RdFull,Z is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & Z & opbit0=0 {\n\tptr:$(PCBYTESIZE) = zext(Z);\n\tlocal falseRead:1 = *[code]:1 (ptr >> 1);\n\tRdFull = *[codebyte]:$(PCBYTESIZE) ptr;\n}\n# lpm Rd,Z+\nLpmPlus: Z^\"+\" is Z {}\n:lpm RdFull,LpmPlus is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & LpmPlus & opbit0=1 {\n ptr:$(PCBYTESIZE) = zext(Z);\n local falseRead:1 = *[code]:1 (ptr >> 1);\n RdFull = *[codebyte]:$(PCBYTESIZE) ptr;\n Z = Z + 1;\n}\n\n# lsl - just an assembly mnemonic for add\n:lsr RdFull is phase=1 & ophi7=0x4a & oplow4=0x6 & RdFull {\n\t$(Cflag) = RdFull & 0x01;\n\tRdFull = (RdFull >> 1);\n\t$(Vflag) = $(Cflag);\n\tsetResultFlags(RdFull);\n}\n# mov Rd,Rr\n:mov RdFull,RrFull is phase=1 & ophi6=0xb & RdFull & RrFull {\n\tRdFull = RrFull;\n}\n# movw Rd+1:Rd,Rr+1Rr \n:movw Rdw4,Rrw4 is phase=1 & ophi8=0x1 & Rdw4 & Rrw4 {\n\tRdw4 = Rrw4;\n}\n:mul RdFull,RrFull is phase=1 & ophi6=0x27 & RdFull & RrFull {\n\ta:2 = zext(RdFull);\n\tb:2 = zext(RrFull);\n\tR1R0 = a * b;\n\tsetMulFlags(R1R0);\n}\n:muls RdHi,RrHi is phase=1 & ophi8=0x2 & RdHi & RrHi {\n\ta:2 = sext(RdHi);\n\tb:2 = sext(RrHi);\n\tR1R0 = a * b;\n\tsetMulFlags(R1R0);\n}\n:mulsu RdHi3,RrHi3 is phase=1 & ophi8=0x3 & opbit7=0 & opbit3=0 & RdHi3 & RrHi3 {\n\ta:2 = sext(RdHi3);\n\tb:2 = zext(RrHi3);\n\tR1R0 = a * b;\n\tsetMulFlags(R1R0);\n}\n:neg RdFull is phase=1 & ophi7=0x4a & oplow4=1 & RdFull {\n\tRdFull = -RdFull;\n\t$(Vflag) = (RdFull == 0x80);\n\t$(Cflag) = (RdFull != 0);\n\tsetResultFlags(RdFull);\n}\n:nop is phase=1 & ophi16=0x0 {\n}\n:or RdFull,RrFull is phase=1 & ophi6=0xa & RdFull & RrFull {\n\tRdFull = RdFull | RrFull;\n\t$(Vflag) = 0;\n\tsetResultFlags(RdFull);\n}\n:ori RdHi,K8 is phase=1 & ophi4=0x6 & RdHi & K8 {\n\tRdHi = RdHi | K8;\n\t$(Vflag) = 0;\n\tsetResultFlags(RdHi);\n}\n# out A,Rr # Note: Rr occupies the normal Rd position\n:out Aio6,RdFull is phase=1 & ophi5=0x17 & Aio6 & RdFull {\n\tAio6 = RdFull;\n}\n:out SPL,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xd & SPL {\n\tSPL = RdFull;\n}\n:out SPH,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xe & SPH {\n\tSPH = RdFull;\n}\n:out SREG,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xf & SREG {\n\tstoreSREG(RdFull);\n}\n\n:pop RdFull is phase=1 & ophi7=0x48 & oplow4=0xf & RdFull {\n\tpop8(RdFull);\n}\n# push Rf # Note: Rr occupies the normal Rd position\n:push RdFull is phase=1 & ophi7=0x49 & oplow4=0xf & RdFull {\n\tpush8(RdFull);\n}\n\n# rcall . is used by the compiler to create space on the stack\n:rcall \".\" is phase=1 & ophi4=0xd & oplow12=0 {\n\tptr:$(PCBYTESIZE) = inst_next >> 1;\n\tpushPC(ptr);\n}\n\n:rcall rel12dst is phase=1 & ophi4=0xd & rel12dst {\n\tptr:$(PCBYTESIZE) = inst_next >> 1;\n\tpushPC(ptr);\n\tPC = &rel12dst;\n\tcall rel12dst;\n}\n\n:ret is phase=1 & ophi16=0x9508 {\n\t# Could also handle word size options here\n\tpopPC(PC);\n\treturn [PC];\n}\n:reti is phase=1 & ophi16=0x9518 {\n\t$(Iflag) = 1;\n\tpopPC(PC);\n\treturn [PC];\n}\n# rjmp k\n:rjmp rel12dst is phase=1 & ophi4=0xc & rel12dst {\n\tgoto rel12dst;\n}\n# ROL is ADC Rd,Rd\n:ror RdFull is phase=1 & ophi7=0x4a & oplow4=0x7 & RdFull {\n\tlocal c = $(Cflag);\n\tlocal cnew = RdFull & 0x01;\n\tRdFull = (c << 7) | (RdFull >> 1);\n\t$(Cflag) = cnew;\n\t$(Nflag) = (RdFull & 0x80) == 0x80;\n\t$(Vflag) = $(Cflag) ^ $(Nflag);\n\tsetResultFlags(RdFull);\n}\n\n:sbc RdFull,RrFull is phase=1 & ophi6=0x2 & RdFull & RrFull {\n\tdoSubtractWithCarry(RdFull,RrFull,RdFull);\n}\n\n:sbci RdHi,K8 is phase=1 & ophi4=4 & RdHi & K8 {\n\tdoSubtractWithCarry(RdHi,K8,RdHi);\n}\n\n@ifdef FUSION\n# subi sbci\n:subiw op1RdPairHi,K16fuse is phase=1 & op1hi4=0x5 & op2hi4=0x4 & K16fuse & fusion16rkrkPred & op1RdPairHi {\n\t# doSubtract(op1RdPairHi,K16fuse,op1RdPairHi);\n\tlocal res = op1RdPairHi - K16fuse;\n\tlocal pre = op1RdPairHi;\n\t$(Vflag) = sborrow(pre,K16fuse);\n\t$(Cflag) = (op1RdPairHi < K16fuse);\n\top1RdPairHi = res;\n\tsetResultFlags(res);\n\t$(Sflag) = pre s< K16fuse;\n}\n\n@endif\n:sbi Aio5,oplow3 is phase=1 & ophi8=0x9a & Aio5 & oplow3 {\n\tAio5 = Aio5 | (1 << oplow3);\n}\n\n:sbic Aio5,oplow3 is phase=1 & ophi8=0x99 & Aio5 & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] {\n\tSKIP = ((Aio5 & (1 << oplow3)) == 0);\n}\n:sbis Aio5,oplow3 is phase=1 & ophi8=0x9b & Aio5 & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] {\n\tSKIP = ((Aio5 & (1 << oplow3)) != 0);\n}\n\n:sbiw Rdw2,K6 is phase=1 & ophi8=0x97 & Rdw2 & K6 {\n\tlocal pre = Rdw2;\n\tRdw2 = Rdw2 - zext(K6);\n\t$(Cflag) = (pre < zext(K6));\n\t$(Vflag) = sborrow(pre,zext(K6));\n\tsetResultFlags(Rdw2);\n}\n# sbr is an alias for ori\n\n:sbrc RdFull,oplow3 is phase=1 & ophi7=0x7e & opbit3=0 & RdFull & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] {\n\tSKIP = ((RdFull & (1 << oplow3)) == 0);\n}\n:sbrs RdFull,oplow3 is phase=1 & ophi7=0x7f & opbit3=0 & RdFull & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] {\n\tSKIP = ((RdFull & (1 << oplow3)) != 0);\n}\n\n# More flag setting sec, seh, sei, sen, ses, set, sev, sez\n# Implemented as bset\n:ser RdHi is phase=1 & ophi8=0xef & oplow4=0xf & RdHi {\n\tRdHi = 0xff;\n}\n\ndefine pcodeop sleep;\n\n:sleep is phase=1 & ophi16=0x9588 {\n\tsleep();\n}\n\ndefine pcodeop store_program_mem; # make this stand out.\n\n:spm Z is phase=1 & ophi16=0x95e8 & Z {\n\tptr:$(PCBYTESIZE) = zext(Z) << 1;\n\tlocal falseWrite:1 = *[code]:1 (ptr >> 1);\n\t*[codebyte]:$(PCBYTESIZE) ptr = R1R0;\n\tstore_program_mem();\n}\n\nSpmPlus: Z^\"+\" is Z {}\n:spm SpmPlus is phase=1 & ophi16=0x95f8 & SpmPlus {\n ptr:$(PCBYTESIZE) = zext(Z) << 1;\n local falseWrite:1 = *[code]:1 (ptr >> 1);\n *[codebyte]:$(PCBYTESIZE) ptr = R1R0;\n Z = Z + 1;\n store_program_mem();\n}\n# For stores, see the ld code (just flip bit 9)\n:st X, RdFull is phase=1 & ophi7=0x49 & oplow4=0xc & X & RdFull {\n\ttmp:2 = X;\n\t*[mem]:1 tmp = RdFull;\n}\n# st Rd,Y; st Rd,Z\n:st RstPtr, RdFull is phase=1 & ophi7=0x41 & oplow3=0x0 & RdFull & RstPtr {\n\ttmp:2 = RstPtr;\n\t*[mem]:1 tmp = RdFull;\n}\n\n# st Rd,Y+ ; st Rd, X+; st Rd, Z+\nStPlus: RstPtr^\"+\" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; }\n:st StPlus, RdFull is phase=1 & ophi7=0x49 & oplow2=0x01 & RdFull & StPlus {\n\t*[mem]:1 StPlus = RdFull;\n}\n\n# st Rd,-Y ; st Rd, -X; st Rd, -Z\nStPredec: \"-\"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; }\n\n:st StPredec, RdFull is phase=1 & ophi7=0x49 & oplow2=0x02 & RdFull & StPredec {\n\ttmp:2 = StPredec;\n\t*[mem]:1 tmp = RdFull;\n}\n\n@ifndef AVTINY\n# std Rd,Y+q\n# std Rd,Z+q\nStdYZq: Rstq^\"+\"^q6 is Rstq & q6 { local ptr = Rstq + zext(q6); export ptr; }\n:std StdYZq, RdFull is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=1 & RdFull & opbit3 & StdYZq {\n\t*[mem]:1 StdYZq = RdFull;\n}\n@endif\n\n@ifdef AVTINY\n# see manual for computation of address for 16-bit STS\n:sts K7addr, RdHi is phase=1 & ophi5=0x15 & RdHi & K7addr { \n\tK7addr = RdHi;\n}\n@elif DATASIZE == \"2\"\n:sts next16memPtrVal1,RdFull is phase=1 & ophi7=0x49 & oplow4=0 & RdFull; next16memPtrVal1 {\n\tnext16memPtrVal1 = RdFull;\n}\n@else\n:sts next24constVal,RdFull is phase=1 & ophi7=0x49 & oplow4=0 & RdFull; next24constVal {\n\tlocal loc:3 = (zext(RAMPD) << 16) | next24constVal;\n\t*[mem]:1 loc = RdFull;\n}\n@endif\n\n@ifdef FUSION\n# sts ; sts emits backwards with respect to lds; lds\n:stsw stswMemPtrVal2,stswop2RdPair is phase=1 & ldswop1hi7=0x49 & ldswop2hi7=0x49 & ldswop1low4=0 & ldswop2low4=0 & stswMemPtrVal2 & stswop2RdPair & stswPairPred & stswConstPairPred {\n\tstswMemPtrVal2 = stswop2RdPair;\n}\n\n@endif\n\n:sub RdFull,RrFull is phase=1 & ophi6=0x6 & RdFull & RrFull {\n\tdoSubtract(RdFull,RrFull,RdFull);\n}\n# Rd,K\n:subi RdHi,K8 is phase=1 & ophi4=5 & RdHi & K8 {\n\tdoSubtract(RdHi,K8,RdHi);\n}\n:swap RdFull is phase=1 & ophi7=0x4a & oplow4=2 & RdFull {\n\tRdFull = (RdFull >> 4) | (RdFull << 4);\n}\n\n# tst is AND Rd,Rd\ndefine pcodeop watchdog_reset;\n\n:wdr is phase=1 & ophi16=0x95a8 {\n\twatchdog_reset();\n}\n:xch RdFull is phase=1 & ophi7=0x49 & oplow4=0x4 & RdFull {\n\tptr:2 = Z;\n\tlocal tmp = *[mem]:1 ptr;\n\t*[mem]:1 ptr = RdFull;\n\tRdFull = tmp;\n}\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8.slaspec", "content": "# AVR8 with 16-bit addressable code space\n\n@define PCBYTESIZE \"2\"\n@define HASEIND \"0\"\n \n@include \"avr8.sinc\"\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8e.slaspec", "content": "# AVR8 with 16-bit addressable code space and support for \n\n@define PCBYTESIZE \"2\"\n@define HASEIND \"1\"\n \n@include \"avr8.sinc\"\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8egcc.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8eind.slaspec", "content": "# AVR8 with 22-bit addressable code space\n\n@define PCBYTESIZE \"3\"\n@define HASEIND \"1\"\n \n@include \"avr8.sinc\"\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8gcc.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8iarV1.cspec", "content": "\n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8imgCraftV8.cspec", "content": "\n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8xmega.pspec", "content": "\n\n\n\n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n\n \n \n\n \n \n\n \n \n \n \n\n \n \n\n \n \n\n \n \n \n \n \n \n\n \n \n \n \n\n \n\n \n \n \n\n \n \n \n\n \n\n \n \n\n \n \n\n \n \n \n\n \n \n \n \n\n \n \n\n \n \n\n \n \n \n \n \n \n\n \n \n \n \n\n \n\n \n \n \n\n \n \n \n\n \n \n\n \n \n\n \n \n \n\n \n \n \n \n\n \n \n\n \n \n \n \n \n \n\n \n \n \n \n\n \n\n \n \n \n\n \n \n \n\n \n \n\n \n \n\n \n \n\n \n \n \n \n \n\n \n \n\n \n \n\n \n \n \n \n \n \n\n \n \n \n \n\n \n\n \n \n \n\n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n \n \n\n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n\n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n\n \n \n \n \n \n \n\n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n \n\n \n \n \n \n \n \n\n\n\n" }, { "path": "pypcode/processors/Atmel/data/languages/avr8xmega.slaspec", "content": "# AVR8 with 22-bit addressable code space\n\n@define PCBYTESIZE \"3\"\n@define HASEIND \"1\"\n\n@define IO_START \"0\"\n@define REGISTER_SPACE \"register\"\n@define EIND \"0x3c\"\n \n@include \"avr8.sinc\"\n\n" }, { "path": "pypcode/processors/Atmel/data/manuals/AVR32.idx", "content": "@doc32000.pdf [Atmel AVR32 Architecture Document - 04/2011]\nABS,\t\t123\nACALL,\t\t124\nACR,\t\t125\nADC,\t\t126\nADD,\t\t127\nADD{EQ},\t128\nADD{NE},\t128\nADD{HS},\t128\nADD{LO},\t128\nADD{GE},\t128\nADD{LT},\t128\nADD{MI},\t128\nADD{PL},\t128\nADD{LS},\t128\nADD{GT},\t128\nADD{LE},\t128\nADD{HI},\t128\nADD{VS},\t128\nADD{VC},\t128\nADD{QS},\t128\nADD{AL},\t128\nADDABS,\t\t129\nADDHH.W,\t130\nAND,\t\t131\nAND{EQ},\t133\nAND{NE},\t133\nAND{HS},\t133\nADD{LO},\t133\nAND{GE},\t133\nAND{LT},\t133\nAND{MI},\t133\nAND{PL},\t133\nAND{LS},\t133\nAND{GT},\t133\nAND{LE},\t133\nAND{HI},\t133\nAND{VS},\t133\nAND{VC},\t133\nAND{QS},\t133\nAND{AL},\t133\nANDH,\t\t134\nANDL,\t\t134\nANDN,\t\t136\nASR,\t\t137\nBFEXTS,\t\t139\nBFEXTU,\t\t140\nBFINS,\t\t141\nBLD,\t\t142\nBR{EQ},\t\t143\nBR{NE},\t\t143\nBR{HS},\t\t143\nBR{LO},\t\t143\nBR{GE},\t\t143\nBR{LT},\t\t143\nBR{MI},\t\t143\nBR{PL},\t\t143\nBR{LS},\t\t143\nBR{GT},\t\t143\nBR{LE},\t\t143\nBR{HI},\t\t143\nBR{VS},\t\t143\nBR{VC},\t\t143\nBR{QS},\t\t143\nBR{AL},\t\t143\nBREAKPOINT,\t145\nBREV,\t\t146\nBST,\t\t147\nCACHE,\t\t148\nCASTS.H,\t150\nCASTS.B,\t150\nCASTU.H,\t151\nCASTU.B,\t151\nCBR,\t\t152\nCLZ,\t\t153\nCOM,\t\t154\nCOP,\t\t155\nCP.B,\t\t156\nCP.H,\t\t157\nCP.W,\t\t158\nCPC,\t\t160\nCSRF,\t\t161\nCSRFCZ,\t\t162\nDIVS,\t\t163\nDIVU,\t\t164\nEOR,\t\t165\nEOR{EQ},\t167\t\nEOR{NE},\t167\t\nEOR{HS},\t167\t\nEOR{LO},\t167\t\nEOR{GE},\t167\t\nEOR{LT},\t167\t\nEOR{MI},\t167\t\nEOR{PL},\t167\t\nEOR{LS},\t167\t\nEOR{GT},\t167\t\nEOR{LE},\t167\t\nEOR{HI},\t167\t\nEOR{VS},\t167\t\nEOR{VC},\t167\t\nEOR{QS},\t167\t\nEOR{AL},\t167\t\nEORH,\t\t168\nEORL,\t\t168\nFRS,\t\t169\nICALL,\t\t170\nINCJOSP,\t171\t\nLD.D,\t\t173\nLD.SB,\t\t175\nLD.SB{EQ},\t176\t\nLD.SB{NE},\t176\t\nLD.SB{HS},\t176\t\nLD.SB{LO},\t176\t\nLD.SB{GE},\t176\t\nLD.SB{LT},\t176\t\nLD.SB{MI},\t176\t\nLD.SB{PL},\t176\t\nLD.SB{LS},\t176\t\nLD.SB{GT},\t176\t\nLD.SB{LE},\t176\t\nLD.SB{HI},\t176\t\nLD.SB{VS},\t176\t\nLD.SB{VC},\t176\t\nLD.SB{QS},\t176\t\nLD.SB{AL},\t176\t\nLD.UB,\t\t177\nLD.UB{EQ},\t179\t\nLD.UB{NE},\t179\t\nLD.UB{HS},\t179\t\nLD.UB{LO},\t179\t\nLD.UB{GE},\t179\t\nLD.UB{LT},\t179\t\nLD.UB{MI},\t179\t\nLD.UB{PL},\t179\t\nLD.UB{LS},\t179\t\nLD.UB{GT},\t179\t\nLD.UB{LE},\t179\t\nLD.UB{HI},\t179\t\nLD.UB{VS},\t179\t\nLD.UB{VC},\t179\t\nLD.UB{QS},\t179\t\nLD.UB{AL},\t179\t\nLD.SH,\t\t180\nLD.SH{EQ},\t182\t\nLD.SH{NE},\t182\t\nLD.SH{HS},\t182\t\nLD.SH{LO},\t182\t\nLD.SH{GE},\t182\t\nLD.SH{LT},\t182\t\nLD.SH{MI},\t182\t\nLD.SH{PL},\t182\t\nLD.SH{LS},\t182\t\nLD.SH{GT},\t182\t\nLD.SH{LE},\t182\t\nLD.SH{HI},\t182\t\nLD.SH{VS},\t182\t\nLD.SH{VC},\t182\t\nLD.SH{QS},\t182\t\nLD.SH{AL},\t182\t\nLD.UH,\t\t183\nLD.UH{EQ},\t185\t\nLD.UH{NE},\t185\t\nLD.UH{HS},\t185\t\nLD.UH{LO},\t185\t\nLD.UH{GE},\t185\t\nLD.UH{LT},\t185\t\nLD.UH{MI},\t185\t\nLD.UH{PL},\t185\t\nLD.UH{LS},\t185\t\nLD.UH{GT},\t185\t\nLD.UH{LE},\t185\t\nLD.UH{HI},\t185\t\nLD.UH{VS},\t185\t\nLD.UH{VC},\t185\t\nLD.UH{QS},\t185\t\nLD.UH{AL},\t185\t\nLD.W,\t\t187\nLD.W{EQ},\t189\t\nLD.W{NE},\t189\t\nLD.W{HS},\t189\t\nLD.W{LO},\t189\t\nLD.W{GE},\t189\t\nLD.W{LT},\t189\t\nLD.W{MI},\t189\t\nLD.W{PL},\t189\t\nLD.W{LS},\t189\t\nLD.W{GT},\t189\t\nLD.W{LE},\t189\t\nLD.W{HI},\t189\t\nLD.W{VS},\t189\t\nLD.W{VC},\t189\t\nLD.W{QS},\t189\t\nLD.W{AL},\t189\t\nLDC.D,\t\t190\nLDC.W,\t\t190\nLDC0.D,\t\t192\nLDC0.W,\t\t192\nLDCM.D,\t\t193\nLDCM.W,\t\t193\nLDDPC,\t\t195\nLDDSP,\t\t196\nLDINS.B,\t197\t\nLDINS.H,\t197\t\nLDM,\t\t199\nLDMTS,\t\t201\nLDSWP.SH,\t202\t\nLDSWP.UH,\t202\t\nLDSWP.W,\t202\t\nLSL,\t\t204\nLSR,\t\t206\nMAC,\t\t208\nMACHH.D,\t209\t\nMACHH.W,\t210\t\nMACS.D,\t\t211\nMACSATHH.W,\t212\t\nMACU.D,\t\t213\nMACWH.D,\t214\t\nMAX,\t\t215\nMCALL,\t\t216\nMEMC,\t\t217\nMEMS,\t\t218\nMEMT,\t\t219\nMFDR,\t\t220\nMFSR,\t\t221\nMIN,\t\t222\nMOV,\t\t223\nMOV{EQ},\t225\t\nMOV{NE},\t225\t\nMOV{HS},\t225\t\nMOV{LO},\t225\t\nMOV{GE},\t225\t\nMOV{LT},\t225\t\nMOV{MI},\t225\t\nMOV{PL},\t225\t\nMOV{LS},\t225\t\nMOV{GT},\t225\t\nMOV{LE},\t225\t\nMOV{HI},\t225\t\nMOV{VS},\t225\t\nMOV{VC},\t225\t\nMOV{QS},\t225\t\nMOV{AL},\t225\t\nMOVHI,\t\t227\nMTDR,\t\t228\nMTSR,\t\t229\nMUL,\t\t231\nMULHH.W,\t233\t\nMULNHH.W,\t234\t\nMULNWH.D,\t235\t\nMULS.D,\t\t236\nMULSATHH.H,\t237\t\nMULSATHH.W,\t238\t\nMULSATRNDHH.H,\t239\t\nMULSATRNDWH.W,\t240\t\nMULSATWH.W,\t241\t\nMULU.D,\t\t242\nMULWH.D,\t243\t\nMUSFR,\t\t244\nMUSTR,\t\t245\nMVCR.D,\t\t246\nMVCR.W,\t\t246\nMVRC.D,\t\t247\nMVRC.W,\t\t247\nNEG,\t\t248\nNOP,\t\t249\nOR,\t\t250\nOR{EQ},\t\t252\nOR{NE},\t\t252\nOR{HS},\t\t252\nOR{LO},\t\t252\nOR{GE},\t\t252\nOR{LT},\t\t252\nOR{MI},\t\t252\nOR{PL},\t\t252\nOR{LS},\t\t252\nOR{GT},\t\t252\nOR{LE},\t\t252\nOR{HI},\t\t252\nOR{VS},\t\t252\nOR{VC},\t\t252\nOR{QS},\t\t252\nOR{AL},\t\t252\nORH,\t\t253\nORL,\t\t253\nPABS.SB,\t254\t\nPABS.SH,\t254\t\nPACKSH.UB,\t255\t\nPACKSH.SB,\t255\t\nPACKW.SH,\t257\t\nPADD.B,\t`\t258\nPADD.H,\t\t258\nPADDH.UB,\t259\t\nPADDH.SH,\t259\t\nPADDS.UB,\t260\t\nPADDS.SB,\t260\t\nPADDS.UH,\t260\t\nPADDS.SH,\t260\t\nPADDSUB.H,\t262\t\nPADDSUBH.SH,\t263\t\nPADDSUBS.UH,\t264\t\nPADDSUBS.SH,\t264\t\nPADDX.H,\t266\t\nPADDXH.SH,\t267\t\nPADDXS.UH,\t268\t\nPADDXS.SH,\t268\t\nPASR.B,\t\t269\nPASR.H,\t\t269\nPAVG.UB,\t271\t\nPAGV.SH,\t271\t\nPLSL.B,\t\t273\nPLSL.H,\t\t273\nPLSR.B,\t\t275\nPLSR.H,\t\t275\nPMAX.UB,\t277\t\nPMAX.SH,\t277\t\nPMIN.UB,\t279\t\nPMIN.SH,\t279\t\nPOPJC,\t\t281\nPOPM,\t\t282\nPREF,\t\t284\nPSAD,\t\t285\nPSUB.B,\t\t286\nPSUB.H,\t\t286\nPSUBADD.H,\t287\t\nPSUBADDH.SH,\t288\t\nPSUBADDS.UH,\t289\t\nPSUBADDS.SH,\t289\t\nPSUBS.UB,\t292\t\nPSUBS.SB,\t292\t\nPSUBS.UH,\t292\t\nPSUBS.SH,\t292\t\nPSUBX.H,\t294\t\nPSUBXH.SH,\t295\t\nPSUBXS.UH,\t296\t\nPSUBXS.SH,\t296\t\nPUNPCKSB.H\t298\t\nPUNPCKUB.H,\t298\t\nPUSHJC,\t\t300\nPUSHM,\t\t301\nRCALL,\t\t303\nRET{EQ},\t304\t\nRET{NE},\t304\t\nRET{HS},\t304\t\nRET{LO},\t304\t\nRET{GE},\t304\t\nRET{LT},\t304\t\nRET{MI},\t304\t\nRET{PL},\t304\t\nRET{LS},\t304\t\nRET{GT},\t304\t\nRET{LE},\t304\t\nRET{HI},\t304\t\nRET{VS},\t304\t\nRET{VC},\t304\t\nRET{QS},\t304\t\nRET{AL},\t304\t\nRETD,\t\t305\nRETE,\t\t306\nRETJ,\t\t308\nRETS,\t\t309\nRETTS,\t\t310\nRJMP,\t\t311\nROL,\t\t312\nROR,\t\t313\nRSUB,\t\t314\nRSUB{EQ},\t315\t\nRSUB{NE},\t315\t\nRSUB{HS},\t315\t\nRSUB{LO},\t315\t\nRSUB{GE},\t315\t\nRSUB{LT},\t315\t\nRSUB{MI},\t315\t\nRSUB{PL},\t315\t\nRSUB{LS},\t315\t\nRSUB{GT},\t315\t\nRSUB{LE},\t315\t\nRSUB{HI},\t315\t\nRSUB{VS},\t315\t\nRSUB{VC},\t315\t\nRSUB{QS},\t315\t\nRSUB{AL},\t315\t\nSATADD.H,\t316\t\nSATADD.W,\t317\t\nSATRNDS,\t318\t\nSATRNDU,\t319\t\nSATS,\t\t320\nSATSUB.H,\t321\t\nSATSUB.W,\t322\t\nSATU,\t\t324\nSBC,\t\t325\nSBR,\t\t326\nSCALL,\t\t327\nSCR,\t\t328\nSLEEP,\t\t329\nSR{EQ},\t\t330\nSR{NE},\t\t330\nSR{HS},\t\t330\nSR{LO},\t\t330\nSR{GE},\t\t330\nSR{LT},\t\t330\nSR{MI},\t\t330\nSR{PL},\t\t330\nSR{LS},\t\t330\nSR{GT},\t\t330\nSR{LE},\t\t330\nSR{HI},\t\t330\nSR{VS},\t\t330\nSR{VC},\t\t330\nSR{QS},\t\t330\nSR{AL},\t\t330\nSSCALL,\t\t331\nSSRF,\t\t332\nST.B,\t\t333\nST.B{EQ},\t335\t\nST.B{NE},\t335\t\nST.B{HS},\t335\t\nST.B{LO},\t335\t\nST.B{GE},\t335\t\nST.B{LT},\t335\t\nST.B{MI},\t335\t\nST.B{PL},\t335\t\nST.B{LS},\t335\t\nST.B{GT},\t335\t\nST.B{LE},\t335\t\nST.B{HI},\t335\t\nST.B{VS},\t335\t\nST.B{VC},\t335\t\nST.B{QS},\t335\t\nST.B{AL},\t335\t\nST.D,\t\t336\nST.H,\t\t338\nST.H{EQ},\t340\t\nST.H{NE},\t340\t\nST.H{HS},\t340\t\nST.H{LO},\t340\t\nST.H{GE},\t340\t\nST.H{LT},\t340\t\nST.H{MI},\t340\t\nST.H{PL},\t340\t\nST.H{LS},\t340\t\nST.H{GT},\t340\t\nST.H{LE},\t340\t\nST.H{HI},\t340\t\nST.H{VS},\t340\t\nST.H{VC},\t340\t\nST.H{QS},\t340\t\nST.H{AL},\t340\t\nST.W,\t\t341\nST.W{EQ},\t343\t\nST.W{NE},\t343\t\nST.W{HS},\t343\t\nST.W{LO},\t343\t\nST.W{GE},\t343\t\nST.W{LT},\t343\t\nST.W{MI},\t343\t\nST.W{PL},\t343\t\nST.W{LS},\t343\t\nST.W{GT},\t343\t\nST.W{LE},\t343\t\nST.W{HI},\t343\t\nST.W{VS},\t343\t\nST.W{VC},\t343\t\nST.W{QS},\t343\t\nST.W{AL},\t343\t\nSTC.D,\t\t344\nSTC.W,\t\t344\nSTC0.D,\t\t346\nSTC0.W,\t\t346\nSTCM.D,\t\t347\nSTCM.W,\t\t347\nSTCOND,\t\t349\nSTDSP,\t\t350\nSTHH.W,\t\t351\nSTM,\t\t353\nSTMTS,\t\t354\nSTSWP.H,\t355\t\nSTSWP.W,\t355\t\nSUB,\t\t356\nSUB{EQ},\t358\t\nSUB{NE},\t358\t\nSUB{HS},\t358\t\nSUB{LO},\t358\t\nSUB{GE},\t358\t\nSUB{LT},\t358\t\nSUB{MI},\t358\t\nSUB{PL},\t358\t\nSUB{LS},\t358\t\nSUB{GT},\t358\t\nSUB{LE},\t358\t\nSUB{HI},\t358\t\nSUB{VS},\t358\t\nSUB{VC},\t358\t\nSUB{QS},\t358\t\nSUB{AL},\t358\t\nSUBHH.W,\t360\t\nSWAP.B,\t\t361\nSWAP.BH,\t362\t\nSWAP.H,\t\t363\nSYNC,\t\t364\nTLBR,\t\t365\nTLBS,\t\t366\nTLBW,\t\t368\nTNBZ,\t\t369\nTST,\t\t370\nXCHG,\t\t371\n\n" }, { "path": "pypcode/processors/Atmel/data/manuals/AVR8.idx", "content": "@atmel-0856-avr-instruction-set-manual.pdf [Atmel AVR Instruction Set Manual, 11/2016 (Rev. 0856L)]\nADC, 30\nADD, 32\nADIW, 33\nAND, 35\nANDI, 36\nASR, 37\nBCLR, 38\nBLD, 39\nBRBC, 40\nBRBS, 41\nBRCC, 42\nBRCS, 43\nBREAK, 44\nBREQ, 45\nBRGE, 46\nBRHC, 47\nBRHS, 48\nBRID, 49\nBRIE, 50\nBRLO, 51\nBRLT, 52\nBRMI, 53\nBRNE, 54\nBRPL, 55\nBRSH, 56\nBRTC, 57\nBRTS, 58\nBRVC, 59\nBRVS, 60\nBSET, 61\nBST, 62\nCALL, 63\nCBI, 65\nCBR, 66\nCLC, 67\nCLH, 68\nCLI, 69\nCLN, 70\nCLR, 71\nCLS, 72\nCLT, 73\nCLV, 74\nCLZ, 75\nCOM, 76\nCP, 77\nCPC, 79\nCPI, 81\nCPSE, 83\nDEC, 84\nDES, 86\nEICALL, 87\nEIJMP, 88\nELPM, 89\nEOR, 91\nFMUL, 92\nFMULS, 94\nFMULSU, 96\n# Ghidra currently uses non-standard FRACMUL* mnemonics in place of FMUL*\nFRACMUL, 92\nFRACMULS, 94\nFRACMULSU, 96\nICALL, 98\nIJMP, 99\nIN, 100\nINC, 101\nJMP, 103\nLAC, 104\nLAS, 105\nLAT, 106\nLD, 107\nLDD, 109\nLDI, 115\nLDS, 116\nLPM, 118\nLSL, 120\nLSR, 122\nMOV, 123\nMOVW, 124\nMUL, 125\nMULS, 126\nMULSU, 127\nNEG, 129\nNOP, 131\nOR, 132\nORI, 133\nOUT, 134\nPOP, 135\nPUSH, 136\nRCALL, 137\nRET, 139\nRETI, 140\nRJMP, 142\nROL, 143\nROR, 145\nSBC, 147\nSBCI, 149\nSBI, 151\nSBIC, 152\nSBIS, 153\nSBIW, 154\nSBR, 156\nSBRC, 157\nSBRS, 158\nSEC, 159\nSEH, 160\nSEI, 161\nSEN, 162\nSER, 163\nSES, 164\nSET, 165\nSEV, 166\nSEZ, 167\nSLEEP, 168\nSPM, 169\nST, 173\nSTD, 175\nSTS, 179\nSUB, 181\nSUBI, 183\nSWAP, 185\nTST, 186\nWDR, 187\nXCH, 188\n\n" }, { "path": "pypcode/processors/Atmel/data/patterns/AVR8_patterns.xml", "content": "\n\n \n \n 0x08 0x95 \n 0x18 0x95 \n \n \n \n ....1111 1001001. ....1111 1001001. \n \n \n \n \n \n \n 0x1. 0xe. \n 0xa. 0xe. \n 0xb. 0xe. \n 0xe. 0xe. \n 0xf. 0xe. \n 0x0. 0xe. \n 0x0b 0xbf \n 0x02 0xc0 \n 0x07 0x90 \n 0x0d 0x92 \n 0xa. 0x3. \n 0xb1 0x07 \n 0xd9 0xf7 \n \n \n \n \n\n" }, { "path": "pypcode/processors/Atmel/data/patterns/patternconstraints.xml", "content": "\n \n AVR8_patterns.xml\n \n\n" }, { "path": "pypcode/processors/BPF/data/languages/BPF.cspec", "content": "\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \t \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n" }, { "path": "pypcode/processors/BPF/data/languages/BPF.ldefs", "content": "\n\n \n BPF processor 32-bit little-endian\n \n \n\n\n" }, { "path": "pypcode/processors/BPF/data/languages/BPF.pspec", "content": "\n\n\t \n \n \n \n \n\n" }, { "path": "pypcode/processors/BPF/data/languages/BPF.sinc", "content": "###############################################################################\n# BPF Processor Specification for Ghidra\n###############################################################################\n\ndefine space ram type=ram_space size=4 default;\ndefine space packet type=ram_space size=4;\ndefine space mem type=ram_space size=4;\ndefine space register type=register_space size=4;\n\ndefine register offset=0 size=4 [ A X RS R PC ];\ndefine register offset=0 size=2 [ AH _ XH _ RSH _ RH _ PCH _ ];\ndefine register offset=0 size=1 [ AB _ _ _ XB _ _ _ RSB _ _ _ RB _ _ _ PCB _ _ _ ];\n \n# Instruction encoding: Insop:8, dst_reg:4, src_reg:4, off:16, imm:32 - from lsb to msb\ndefine token instr(64)\n\timm=(32, 63)\n\tjf=(24, 31) signed\n\tjt=(16, 23) signed\n\top_src_K_X=(3, 3)\n\top_alu_jmp_opcode=(4, 7)\n\top_alu_jmp_source=(3, 3)\n\top_alu_mode=(4, 7)\n\top_ld_st_mode=(5, 7)\n\top_ld_st_size=(3, 4)\n\top_insn_class=(0, 2)\n;\n\n:LD imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=imm; }\n:LDH imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x1 & op_insn_class=0x0 { AH=imm:2; A = A & 0xffff; }\n:LDB imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x2 & op_insn_class=0x0 { AB=imm:1; A = A & 0xff;}\n\n:LDX imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x0 & op_insn_class=0x1 { X=imm; }\n:LDXH imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x1 & op_insn_class=0x1 { XH=imm:2; X = X & 0xffff; }\n:LDXB imm is imm & op_ld_st_mode=0x0 & op_ld_st_size=0x2 & op_insn_class=0x1 { XB=imm:1; X = X & 0xff;}\n\n:LD imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=*[packet]:4 imm:4; }\n:LDH imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x1 & op_insn_class=0x0 { A=*[packet]:2 imm:4; A = A & 0xffff; }\n:LDB imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x2 & op_insn_class=0x0 { A=*[packet]:1 imm:4; A = A & 0xff;}\n\n:LDX imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x0 & op_insn_class=0x1 { X=*[packet]:4 imm:4; }\n:LDXH imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x1 & op_insn_class=0x1 { X=*[packet]:2 imm:4; X = X & 0xffff; }\n:LDXB imm is imm & op_ld_st_mode=0x1 & op_ld_st_size=0x2 & op_insn_class=0x1 { X=*[packet]:1 imm:4; X = X & 0xff;}\n\n:ST imm is imm & op_insn_class=0x2 { *[mem]:4 imm:4=A:4; }\n:STX imm is imm & op_insn_class=0x3 { *[mem]:4 imm:4=X:4; }\n\n:LDI imm is imm & op_ld_st_mode=0x2 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=*[packet]:4 (imm:4 + X); }\n:LDIH imm is imm & op_ld_st_mode=0x2 & op_ld_st_size=0x1 & op_insn_class=0x0 { A=*[packet]:2 (imm:4 + X); A = A & 0xffff; }\n:LDIB imm is imm & op_ld_st_mode=0x2 & op_ld_st_size=0x2 & op_insn_class=0x0 { A=*[packet]:1 (imm:4 + X); A = A & 0xff; }\n\n:LD imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x0 { A=*[mem]:4 imm:4; }\n:LDH imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x0 { A=*[mem]:2 imm:4; A = A & 0xffff; }\n:LDB imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x0 { A=*[mem]:1 imm:4; A = A & 0xff; }\n\n:LDX imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x1 { X=*[mem]:4 imm:4; }\n:LDXH imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x1 { X=*[mem]:2 imm:4; X = X & 0xffff; }\n:LDXB imm is imm & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x1 { X=*[mem]:1 imm:4; X = X & 0xff; }\n\n# ALU\n:ADD imm is imm & op_alu_mode=0x0 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A + imm; }\n:ADD X is X & op_alu_mode=0x0 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A + X; }\n:SUB imm is imm & op_alu_mode=0x1 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A - imm; }\n:SUB X is X & op_alu_mode=0x1 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A - X; }\n:MUL imm is imm & op_alu_mode=0x2 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A * imm; }\n:MUL X is X & op_alu_mode=0x2 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A * X; }\n:DIV imm is imm & op_alu_mode=0x3 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A / imm; }\n:DIV X is X & op_alu_mode=0x3 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A / X; }\n:OR imm is imm & op_alu_mode=0x4 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A | imm; }\n:OR X is X & op_alu_mode=0x4 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A | X; }\n:AND imm is imm & op_alu_mode=0x5 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A & imm; }\n:AND X is X & op_alu_mode=0x5 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A & X; }\n:LSH imm is imm & op_alu_mode=0x6 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A << imm; }\n:LSH X is X & op_alu_mode=0x6 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A << X; }\n:RSH imm is imm & op_alu_mode=0x7 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A >> imm; }\n:RSH X is X & op_alu_mode=0x7 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A >> X; }\n:NEG is op_alu_mode=0x8 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= -A; }\n:MOD imm is imm & op_alu_mode=0x9 & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A % imm; }\n:MOD X is X & op_alu_mode=0x9 & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A % X; }\n:XOR imm is imm & op_alu_mode=0xa & op_insn_class=0x4 & op_src_K_X = 0x0 { A= A ^ imm; }\n:XOR X is X & op_alu_mode=0xa & op_insn_class=0x4 & op_src_K_X = 0x1 { A= A ^ X; }\n\n:TAX is op_insn_class=0x7 & op_src_K_X = 0x0 { A= X; }\n:TXA is op_insn_class=0x7 & op_src_K_X = 0x1 { X= A; }\n\n\n:LD_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x0 & op_insn_class=0x0 {\n local t_val = *[packet]:4 imm:4;\n t_val = t_val&0xf;\n t_val = t_val << 2;\n A = t_val;\n}\n\n:LDH_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x1 & op_insn_class=0x0 {\n local t_val = *[packet]:2 imm:4;\n t_val = t_val&0xf;\n t_val = t_val << 2;\n AH = t_val;\n}\n\n:LDB_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x2 & op_insn_class=0x0 {\n local t_val = *[packet]:1 imm:4;\n t_val = t_val&0xf;\n t_val = t_val << 2;\n AB = t_val;\n}\n\n:LDX_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x0 & op_insn_class=0x1 {\n local t_val = *[packet]:4 imm:4;\n t_val = t_val&0xf;\n t_val = t_val << 2;\n X = t_val;\n}\n\n:LDXH_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x1 & op_insn_class=0x1 {\n local t_val = *[packet]:2 imm:4;\n t_val = t_val&0xf;\n t_val = t_val << 2;\n XH = t_val;\n X = X & 0xffff;\n}\n\n:LDXB_MSH imm is imm & op_ld_st_mode=0x5 & op_ld_st_size=0x2 & op_insn_class=0x1 {\n local t_val = *[packet]:1 imm:4;\n t_val = t_val&0xf;\n t_val = t_val << 2;\n XB = t_val;\n X = X & 0xff;\n}\n\n#Branch instructions\n###############################################################################\n\njoff: reloc is imm [ reloc = inst_next + imm * 8; ] { export *:8 reloc; }\njtoff: reloc is jt [ reloc = inst_next + jt * 8; ] { export *:8 reloc; }\njfoff: reloc is jf [ reloc = inst_next + jf * 8; ] { export *:8 reloc; }\n\n:JA joff is joff & op_alu_jmp_opcode=0x0 & op_alu_jmp_source=0 & op_insn_class=0x5 {\n\tgoto joff;\n}\n\n:JEQ jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x1 & op_alu_jmp_source=0 & op_insn_class=0x5 {\t\n\tif (A==imm) goto jtoff;\n\tgoto jfoff;\n}\n\n:JEQ jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x1 & op_alu_jmp_source=1 & op_insn_class=0x5 {\t\n\tif (A==X) goto jtoff;\n\tgoto jfoff;\n}\n\n:JGT jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x2 & op_alu_jmp_source=0 & op_insn_class=0x5 {\t\n\tif (A > imm) goto jtoff;\n\tgoto jfoff;\n}\n\n:JGT jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x2 & op_alu_jmp_source=1 & op_insn_class=0x5 {\t\n\tif (A > X) goto jtoff;\n\tgoto jfoff;\n}\n\n:JGE jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x3 & op_alu_jmp_source=0 & op_insn_class=0x5 {\t\n\tif (A >= imm) goto jtoff;\n\tgoto jfoff;\n}\n\n:JGE jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x3 & op_alu_jmp_source=1 & op_insn_class=0x5 {\t\n\tif (A >= X) goto jtoff;\n\tgoto jfoff;\n}\n\n:JSET jtoff, jfoff, imm is imm & jtoff & jfoff & op_alu_jmp_opcode=0x4 & op_alu_jmp_source=0 & op_insn_class=0x5 {\t\n\tif ((A&imm) != 0) goto jtoff;\n\tgoto jfoff;\n}\n\n:JSET jtoff, jfoff, X is X & jtoff & jfoff & op_alu_jmp_opcode=0x4 & op_alu_jmp_source=1 & op_insn_class=0x5 {\t\n\tif ((A&X) != 0) goto jtoff;\n\tgoto jfoff;\n}\n\n:RETW imm is imm & op_ld_st_size=0 & op_insn_class=0x6 {\n R = imm;\n return [*:8 RS];\n}\n" }, { "path": "pypcode/processors/BPF/data/languages/BPF_le.slaspec", "content": "define endian=little;\n\n@include \"BPF.sinc\"" }, { "path": "pypcode/processors/CP1600/data/languages/CP1600.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/CP1600/data/languages/CP1600.ldefs", "content": "\n\n\n \n General Instruments CP1600\n \n \n\n" }, { "path": "pypcode/processors/CP1600/data/languages/CP1600.opinion", "content": "\n\n" }, { "path": "pypcode/processors/CP1600/data/languages/CP1600.pspec", "content": "\n\n\n \n\n" }, { "path": "pypcode/processors/CP1600/data/languages/CP1600.slaspec", "content": "define endian=big;\ndefine alignment=2;\ndefine space ram type=ram_space wordsize=2 size=2 default;\ndefine space register type=register_space size=2;\n\ndefine register offset=0x00 size=2 [ R0 R1 R2 R3 R4 R5 R6 R7 ];\ndefine register offset=0x10 size=1 [ I C O Z S ];\ndefine register offset=0x20 size=4 [ contextreg ];\n\ndefine token opcode_word (16)\n\ttarget3_5 = (3, 5)\n\treg3_5 = (3, 5)\n\ttarget0_2 = (0, 2)\n\treg0_2 = (0, 2)\n\treg0_1 = (0, 1)\n\toperation_size = (2, 2)\n\t\n\tbranch_sign = (5, 5)\n\tbranch_external = (4, 4)\n\tbranch_condition = (0, 3)\n\texternal_condition = (0, 3)\n\t\n\topcode6_9 = (6, 9)\n\topcode3_9 = (3, 9)\n\topcode2_9 = (2, 9)\n\topcode1_9 = (1, 9)\n\topcode0_9 = (0, 9)\n;\n\ndefine token jump_token (32)\n\ttarget24_25 = (24, 25)\n\treg24_25 = (24, 25)\n\taddress_hi = (18, 23)\n\tjump_type = (16, 17)\n\taddress_lo = (0, 9)\n;\n\ndefine token double16 (32)\n\tvalue_lo = (16, 23)\n\tvalue_hi = (0, 7)\n;\n\ndefine token immediate16 (16)\n\timm16 = (0, 15)\n\taddr16 = (0, 15)\n;\n\ndefine context contextreg\n\tdoublebyte = (0, 0) noflow\n;\n\nattach variables [ reg0_1 ] [ R0 R1 R2 R3 ];\nattach variables [ reg0_2 reg3_5 ] [ R0 R1 R2 R3 R4 R5 R6 R7 ];\nattach variables [ reg24_25 ] [ R4 R5 R6 R7 ];\n\n################################################################\n\njmpdest16: reloc is address_hi & address_lo [ reloc = (address_hi << 10) + address_lo; ] { export *:2 reloc; }\nbranchdest16: reloc is branch_sign=0 ; imm16 [ reloc = inst_start + 2 + imm16; ] { export *:2 reloc; }\nbranchdest16: reloc is branch_sign=1 ; imm16 [ reloc = inst_start + 2 + (imm16 ^ 0xFFFF); ] { export *:2 reloc; }\nsplitimm16: split is value_hi & value_lo [ split = (value_hi << 8) + value_lo; ] { local tmp:2 = split & 0xFFFF; export tmp; }\n\nimpliedval16: reg3_5 is reg3_5 & (target3_5=0 | target3_5=1 | target3_5=2 | target3_5=3 | target3_5=7) & doublebyte=0 {\n\tlocal tmp:2 = *:2 reg3_5;\n\texport tmp;\n}\n\nimpliedval16: reg3_5 is reg3_5 & (target3_5=4 | target3_5=5) & doublebyte=0 {\n\tlocal tmp:2 = *:2 reg3_5;\n\treg3_5 = reg3_5 + 1;\n\texport tmp;\n}\n\nimpliedval16: reg3_5 is reg3_5 & target3_5=6 & doublebyte=0 {\n\treg3_5 = reg3_5 - 1;\n\tlocal tmp:2 = *:2 reg3_5;\n\texport tmp;\n}\n\nimpliedval16: reg3_5 is reg3_5 & (target3_5=4 | target3_5=5) & doublebyte=1 {\n\tlocal val:4 = *:4 reg3_5;\n\tlocal low:1 = val(2);\n\tlocal high:1 = val(0);\n\tlocal tmp:2 = (zext(high) << 8) | zext(low);\n\treg3_5 = reg3_5 + 2;\n\texport tmp;\n}\n\nimpliedval16: reg3_5 is reg3_5 & target3_5=6 & doublebyte=1 {\n\treg3_5 = reg3_5 - 2;\n\tlocal val:4 = *:4 reg3_5;\n\tlocal low:1 = val(2);\n\tlocal high:1 = val(0);\n\tlocal tmp:2 = (zext(high) << 8) | zext(low);\n\texport tmp;\n}\n\nimpliedval16: reg3_5 is reg3_5 & (target3_5=0 | target3_5=1 | target3_5=2 | target3_5=3 | target3_5=7) & doublebyte=1 {\n\tlocal val:2 = *:1 reg3_5;\n\tval = (zext(val) << 8) | zext(val);\n\texport val;\n}\n\ncheckbranch: is reg0_2=7 { goto [R7]; }\ncheckbranch: is reg0_2 {}\nregval0_2: is reg0_2=7 {\n\tlocal tmp:2 = inst_next / 2;\n\texport tmp;\n}\nregval0_2: is reg0_2 { export reg0_2; }\n\ncc: \"\" is branch_external=0 & branch_condition=0 { local tmp:1 = 1; export tmp; }\ncc: \"C\" is branch_external=0 & branch_condition=1 { export C; }\ncc: \"OV\" is branch_external=0 & branch_condition=2 { export O; }\ncc: \"PL\" is branch_external=0 & branch_condition=3 { local tmp = !S; export tmp; }\ncc: \"EQ\" is branch_external=0 & branch_condition=4 { export Z; }\ncc: \"LT\" is branch_external=0 & branch_condition=5 { local tmp = S != O; export tmp; }\ncc: \"LE\" is branch_external=0 & branch_condition=6 { local tmp = (Z == 1) || (S != O); export tmp; }\ncc: \"USC\" is branch_external=0 & branch_condition=7 { local tmp = S != C; export tmp; }\ncc: \"NC\" is branch_external=0 & branch_condition=9 { local tmp = !C; export tmp; }\ncc: \"NOV\" is branch_external=0 & branch_condition=10 { local tmp = !O; export tmp; }\ncc: \"MI\" is branch_external=0 & branch_condition=11 { export S; }\ncc: \"NEQ\" is branch_external=0 & branch_condition=12 { local tmp = !Z; export tmp; }\ncc: \"GE\" is branch_external=0 & branch_condition=13 { local tmp = S == O; export tmp; }\ncc: \"GT\" is branch_external=0 & branch_condition=14 { local tmp = (Z == 0) || (S == O); export tmp; }\ncc: \"ESC\" is branch_external=0 & branch_condition=15 { local tmp = S == C; export tmp; }\n\n################################################################\n\nmacro resultFlags(value) {\n\tZ = value == 0;\n\tS = value s< 0; \n}\n\nmacro addition(first_w, first_r, second) {\n\tlocal tmpC = carry(first_r, second);\n\tlocal tmpO = scarry(first_r, second);\n\tfirst_w = first_r + second;\n\tC = tmpC;\n\tO = tmpO;\n\tresultFlags(first_w);\n}\n\nmacro comparison(first, second) {\n\tlocal __val__ = first - second;\n\tO = sborrow(first, second);\n\tC = first < second; \n\tresultFlags(__val__);\n}\n\nmacro subtraction(first_w, first_r, second) {\n\tlocal __val__ = first_r - second;\n\tO = sborrow(first_r, second);\n\tC = first_r < second; \n\tresultFlags(__val__);\n\tfirst_w = __val__;\n}\n\n################################################################\n\ndefine pcodeop TerminateCurrentInterrupt;\ndefine pcodeop SoftwareInterrupt;\n\n################################################################\n\n:ADD addr16, reg0_2 is opcode3_9=0x0058 & reg0_2 & regval0_2 & checkbranch ; addr16 {\n\tlocal ptr:2 = addr16;\n\taddition(reg0_2, regval0_2, *:2 ptr);\n\tbuild checkbranch;\n}\n\n:ADD@ impliedval16, reg0_2 is opcode6_9=0x000B & reg0_2 & regval0_2 & checkbranch & impliedval16 {\n\taddition(reg0_2, regval0_2, impliedval16);\n\tbuild checkbranch;\n}\n\n:ADCR reg0_2 is opcode3_9=0x0005 & reg0_2 & regval0_2 & checkbranch {\n\tlocal oldC = zext(C);\n\taddition(reg0_2, regval0_2, oldC);\n\tbuild checkbranch;\n}\n\n:ADDR reg3_5, reg0_2 is opcode6_9=0x0003 & reg3_5 & reg0_2 & regval0_2 & checkbranch {\n\taddition(reg0_2, regval0_2, reg3_5);\n\tbuild checkbranch;\n}\n\n:AND addr16, reg0_2 is opcode3_9=0x0070 & reg0_2 & regval0_2 & checkbranch ; addr16 {\n\tlocal ptr:2 = addr16;\n\treg0_2 = regval0_2 & *:2 ptr;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:AND@ impliedval16, reg0_2 is opcode6_9=0x000E & reg0_2 & regval0_2 & checkbranch & impliedval16 {\n\treg0_2 = regval0_2 & impliedval16;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:ANDR reg3_5, reg0_2 is opcode6_9=0x0006 & reg3_5 & reg0_2 & regval0_2 & checkbranch {\n\treg0_2 = regval0_2 & reg3_5;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:B^cc branchdest16 is (opcode6_9=0x0008 & cc) ... & branchdest16 {\n\tif (cc) goto branchdest16;\n}\n\n:BEXT branchdest16, external_condition is (opcode6_9=0x0008 & branch_external=1 & external_condition) ... & branchdest16 {\n\tgoto branchdest16;\n} \n\n:CLRC is opcode0_9=0x0006 {\n\tC = 0;\n}\n\n:CLRR reg0_2 is opcode6_9=0x0007 & reg0_2 & (target0_2=target3_5) & checkbranch {\n\treg0_2 = 0;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:CMP addr16, reg0_2 is opcode3_9=0x0068 & reg0_2 ; addr16 {\n\tlocal ptr:2 = addr16;\n\tcomparison(reg0_2, *:2 ptr);\n}\n\n:CMP@ impliedval16, reg0_2 is opcode6_9=0x000D & reg0_2 & impliedval16 {\n\tcomparison(reg0_2, impliedval16);\n}\n\n:CMPR reg3_5, reg0_2 is opcode6_9=0x0005 & reg3_5 & reg0_2 {\n\tcomparison(reg0_2, reg3_5);\n}\n\n:COMR reg0_2 is opcode3_9=0x0003 & reg0_2 & regval0_2 & checkbranch {\n\treg0_2 = ~regval0_2;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:DECR reg0_2 is opcode3_9=0x0002 & reg0_2 & regval0_2 & checkbranch {\n\treg0_2 = regval0_2 - 1;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:DIS is opcode0_9=0x0003 {\n\tI = 0;\n}\n\n:EIS is opcode0_9=0x0002 {\n\tI = 1;\n}\n\n:GSWD reg0_1 is opcode2_9=0x000C & reg0_1 {\n\tlocal mask:2 = (zext(S) << 7) + (zext(Z) << 6) + (zext(O) << 5) + (zext(C) << 4);\n\treg0_1 = (mask << 8) + mask; \n}\n\n:HLT is opcode0_9=0x0000 {\n\tgoto inst_start;\n}\n\n:INCR reg0_2 is opcode3_9=0x0001 & reg0_2 & regval0_2 & checkbranch {\n\treg0_2 = regval0_2 + 1;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:J jmpdest16 is opcode0_9=0x0004 ; jump_type=0 & target24_25=3 & jmpdest16 {\n\tgoto jmpdest16;\n}\n\n:JD jmpdest16 is opcode0_9=0x0004 ; jump_type=2 & target24_25=3 & jmpdest16 {\n\tI = 0;\n\tgoto jmpdest16;\n}\n\n:JE jmpdest16 is opcode0_9=0x0004 ; jump_type=1 & target24_25=3 & jmpdest16 {\n\tI = 1;\n\tgoto jmpdest16;\n}\n\n:JR reg3_5 is opcode6_9=0x0002 & reg3_5 & reg0_2 & reg0_2=7 {\n\treg0_2 = reg3_5;\n\tresultFlags(reg0_2);\n\treturn [reg0_2];\n}\n\n:JSR reg24_25, jmpdest16 is opcode0_9=0x0004 ; jump_type=0 & reg24_25 & jmpdest16 {\n\treg24_25 = inst_next;\n\tcall jmpdest16;\n}\n\n:JSRD reg24_25, jmpdest16 is opcode0_9=0x0004 ; jump_type=2 & reg24_25 & jmpdest16 {\n\tI = 0;\n\treg24_25 = inst_next;\n\tcall jmpdest16;\n}\n\n:JSRE reg24_25, jmpdest16 is opcode0_9=0x0004 ; jump_type=1 & reg24_25 & jmpdest16 {\n\tI = 1;\n\treg24_25 = inst_next;\n\tcall jmpdest16;\n}\n\n:MOVR reg3_5, reg0_2 is opcode6_9=0x0002 & reg0_2 & reg3_5 & checkbranch {\n\treg0_2 = reg3_5;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:MVI addr16, reg0_2 is opcode3_9=0x0050 & reg0_2 & checkbranch ; addr16 {\n\tlocal ptr:2 = addr16;\n\treg0_2 = *(*:2 ptr);\n\tbuild checkbranch;\n}\n\n:MVI@ impliedval16, reg0_2 is opcode6_9=0x000A & reg0_2 & impliedval16 & checkbranch {\n\treg0_2 = impliedval16;\n\tbuild checkbranch;\n}\n\n:MVO reg0_2, addr16 is opcode3_9=0x0048 & reg0_2 ; addr16 {\n\tlocal ptr:2 = addr16;\n\t*ptr = reg0_2;\n}\n\n:MVO@ reg0_2, reg3_5 is opcode6_9=0x0009 & reg0_2 & reg3_5 & (reg3_5=4 | reg3_5=5) & checkbranch {\n\tlocal ptr:2 = reg3_5; \n\t*ptr = reg0_2;\n\treg3_5 = reg3_5 + 1;\n\tbuild checkbranch;\n}\n\n:MVO@ reg0_2, reg3_5 is opcode6_9=0x0009 & reg0_2 & reg3_5 & checkbranch {\n\tlocal ptr:2 = reg3_5; \n\t*ptr = reg0_2;\n\tbuild checkbranch;\n}\n\n:MVOI reg0_2 is opcode3_9=0x004F & reg0_2 ; imm16 {\n\tlocal tmp:2 = inst_start + 2;\n\t*tmp = reg0_2;\n}\n\n:NEGR reg0_2 is opcode3_9=0x0004 & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmp = regval0_2 ^ 0xFFFF;\n\tlocal tmpC = carry(tmp, 1);\n\tlocal tmpO = scarry(tmp, 1);\n\treg0_2 = -regval0_2;\n\tC = tmpC;\n\tO = tmpO;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:NOP is opcode1_9=0x001A {\n}\n\n:NOPP is opcode6_9=0x0008 & branch_external=0 & branch_condition=8 ; imm16 {\n}\n\n:PSHR reg0_2 is opcode6_9=0x0009 & reg0_2 & reg3_5 & reg3_5=6 {\n\tlocal ptr:2 = reg3_5;\n\t*ptr = reg0_2;\n\treg3_5 = reg3_5 + 1;\n}\n\n:PULR reg0_2 is opcode6_9=0x000A & impliedval16 & reg0_2 & reg3_5=6 {\n\treg0_2 = impliedval16;\n}\n\n:RSWD reg0_2 is opcode3_9=0x0007 & reg0_2 {\n\tC = (reg0_2 & 0b00001000) != 0;\n\tO = (reg0_2 & 0b00010000) != 0;\n\tZ = (reg0_2 & 0b00100000) != 0;\n\tS = (reg0_2 & 0b01000000) != 0;\n}\n\n:SDBD is opcode0_9=0x0001 [ doublebyte=1; globalset(inst_next, doublebyte); ] {\n}\n\n:SETC is opcode0_9=0x0007 {\n\tC = 1;\n}\n\n:SIN is opcode1_9=0x001B {\n\tSoftwareInterrupt();\n}\n\n:SUB addr16, reg0_2 is opcode3_9=0x0060 & reg0_2 & regval0_2 & checkbranch ; addr16 {\n\tlocal ptr:2 = addr16;\n\tsubtraction(reg0_2, regval0_2, *:2 ptr);\n\tbuild checkbranch;\n}\n\n:SUB@ impliedval16, reg0_2 is opcode6_9=0x000C & reg0_2 & regval0_2 & checkbranch & impliedval16 {\n\tsubtraction(reg0_2, regval0_2, impliedval16);\n\tbuild checkbranch;\n}\n\n:SUBR reg3_5, reg0_2 is opcode6_9=0x0004 & reg3_5 & reg0_2 & regval0_2 & checkbranch {\n\tsubtraction(reg0_2, regval0_2, reg3_5);\n\tbuild checkbranch;\n}\n\n:TCI is opcode0_9=0x0005 {\n\tTerminateCurrentInterrupt();\n}\n\n:TSTR reg0_2 is opcode6_9=0x0002 & reg0_2 & (target0_2=target3_5) {\n\tresultFlags(reg0_2);\n}\n\n:XOR addr16, reg0_2 is opcode3_9=0x0078 & reg0_2 & regval0_2 & checkbranch ; addr16 {\n\tlocal ptr:2 = addr16;\n\treg0_2 = regval0_2 ^ *:2 ptr;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:XOR@ impliedval16, reg0_2 is opcode6_9=0x000F & reg0_2 & regval0_2 & checkbranch & impliedval16 {\n\treg0_2 = regval0_2 ^ impliedval16;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:XORR reg3_5, reg0_2 is opcode6_9=0x0007 & reg3_5 & reg0_2 & regval0_2 & checkbranch {\n\treg0_2 = regval0_2 ^ reg3_5;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:RLC reg0_2, 1 is opcode3_9=0x000A & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x8000) != 0;\n\tlocal tmpS = (regval0_2 & 0x4000) != 0;\n\treg0_2 = (regval0_2 << 1) + zext(C);\n\tC = tmpC;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:RRC reg0_2, 1 is opcode3_9=0x000E & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x0001) != 0;\n\tlocal tmpS = (regval0_2 & 0x0100) != 0;\n\treg0_2 = (regval0_2 >> 1) | (zext(C) << 15);\n\tC = tmpC;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SAR reg0_2, 1 is opcode3_9=0x000D & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x0100) != 0;\n\treg0_2 = regval0_2 s>> 1;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SARC reg0_2, 1 is opcode3_9=0x000F & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x0001) != 0;\n\tlocal tmpS = (regval0_2 & 0x0100) != 0;\n\treg0_2 = regval0_2 s>> 1;\n\tC = tmpC;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SLL reg0_2, 1 is opcode3_9=0x0009 & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x4000) != 0;\n\treg0_2 = regval0_2 << 1;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SLLC reg0_2, 1 is opcode3_9=0x000B & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x8000) != 0;\n\tlocal tmpS = (regval0_2 & 0x4000) != 0;\n\treg0_2 = regval0_2 << 1;\n\tC = tmpC;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n} \n\n:SLR reg0_2, 1 is opcode3_9=0x000C & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x0100) != 0;\n\treg0_2 = regval0_2 >> 1;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n} \n\n:SWAP reg0_2, 1 is opcode3_9=0x0008 & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x8000) != 0;\n\tlocal tmp = (regval0_2 << 8) & 0xFF00;\n\treg0_2 = tmp | ((regval0_2 >> 8) & 0x00FF);\n\tS = tmpS;\n\tbuild checkbranch;\n}\n\nwith : operation_size=1 {\n\n:RLC reg0_2, 2 is opcode3_9=0x000A & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x8000) != 0;\n\tlocal tmpO = (regval0_2 & 0x4000) != 0;\n\tlocal tmpS = (regval0_2 & 0x2000) != 0;\n\treg0_2 = (regval0_2 << 2) + (zext(C) << 1) + zext(O);\n\tC = tmpC;\n\tO = tmpO;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:RRC reg0_2, 2 is opcode3_9=0x000E & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x0001) != 0;\n\tlocal tmpO = (regval0_2 & 0x0002) != 0;\n\tlocal tmpS = (regval0_2 & 0x0200) != 0;\n\treg0_2 = (regval0_2 >> 2) | (zext(C) << 14) | (zext(O) << 15);\n\tC = tmpC;\n\tO = tmpO;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SAR reg0_2, 2 is opcode3_9=0x000D & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x0200) != 0;\n\treg0_2 = regval0_2 s>> 2;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SARC reg0_2, 2 is opcode3_9=0x000F & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x0001) != 0;\n\tlocal tmpO = (regval0_2 & 0x0002) != 0;\n\tlocal tmpS = (regval0_2 & 0x0200) != 0;\n\treg0_2 = regval0_2 s>> 2;\n\tC = tmpC;\n\tO = tmpO;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SLL reg0_2, 2 is opcode3_9=0x0009 & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x2000) != 0;\n\treg0_2 = regval0_2 << 2;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SLLC reg0_2, 2 is opcode3_9=0x000B & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpC = (regval0_2 & 0x8000) != 0;\n\tlocal tmpO = (regval0_2 & 0x4000) != 0;\n\tlocal tmpS = (regval0_2 & 0x2000) != 0;\n\treg0_2 = regval0_2 << 2;\n\tC = tmpC;\n\tO = tmpO;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SLR reg0_2, 2 is opcode3_9=0x000C & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x0200) != 0;\n\treg0_2 = regval0_2 >> 2;\n\tS = tmpS;\n\tZ = reg0_2 == 0;\n\tbuild checkbranch;\n}\n\n:SWAP reg0_2, 2 is opcode3_9=0x0008 & reg0_2 & regval0_2 & checkbranch {\n\tlocal tmpS = (regval0_2 & 0x0080) != 0;\n\treg0_2 = (regval0_2 << 8) | (regval0_2 & 0x00FF);\n\tS = tmpS;\n\tbuild checkbranch;\n}\n\n}\n\n:ADDI \"#\"imm16, reg0_2 is opcode3_9=0x005F & reg0_2 & regval0_2 & checkbranch ; imm16 {\n\taddition(reg0_2, regval0_2, imm16);\n\tbuild checkbranch;\n}\n\n:ANDI \"#\"imm16, reg0_2 is opcode3_9=0x0077 & reg0_2 & regval0_2 & checkbranch ; imm16 {\n\treg0_2 = reg0_2 & imm16;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:CMPI \"#\"imm16, reg0_2 is opcode3_9=0x006F & reg0_2 ; imm16 {\n\tcomparison(reg0_2, imm16);\n}\n\n:MVII \"#\"imm16, reg0_2 is opcode3_9=0x0057 & reg0_2 & checkbranch ; imm16 {\n\treg0_2 = imm16;\n\tbuild checkbranch;\n}\n\n:SUBI \"#\"imm16, reg0_2 is opcode3_9=0x0067 & reg0_2 & regval0_2 & checkbranch ; imm16 {\n\tsubtraction(reg0_2, regval0_2, imm16);\n\tbuild checkbranch;\n}\n\n:XORI \"#\"imm16, reg0_2 is opcode3_9=0x007F & reg0_2 & regval0_2 & checkbranch ; imm16 {\n\treg0_2 = regval0_2 ^ imm16;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\nwith : doublebyte=1 {\n\n:ADDI \"#\"splitimm16, reg0_2 is opcode3_9=0x005F & reg0_2 & regval0_2 & checkbranch ; splitimm16 {\n\taddition(reg0_2, regval0_2, splitimm16);\n\tbuild checkbranch;\n}\n\n:ANDI \"#\"splitimm16, reg0_2 is opcode3_9=0x0077 & reg0_2 & regval0_2 & checkbranch ; splitimm16 {\n\treg0_2 = regval0_2 & splitimm16;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n:CMPI \"#\"splitimm16, reg0_2 is opcode3_9=0x006F & reg0_2 ; splitimm16 {\n\tcomparison(reg0_2, splitimm16);\n}\n\n:MVII \"#\"splitimm16, reg0_2 is opcode3_9=0x0057 & reg0_2 & checkbranch ; splitimm16 {\n\treg0_2 = splitimm16;\n\tbuild checkbranch;\n}\n\n:SUBI \"#\"splitimm16, reg0_2 is opcode3_9=0x0067 & reg0_2 & regval0_2 & checkbranch ; splitimm16 {\n\tsubtraction(reg0_2, regval0_2, splitimm16);\n\tbuild checkbranch;\n}\n\n:XORI \"#\"splitimm16, reg0_2 is opcode3_9=0x007F & reg0_2 & regval0_2 & checkbranch ; splitimm16 {\n\treg0_2 = regval0_2 ^ splitimm16;\n\tresultFlags(reg0_2);\n\tbuild checkbranch;\n}\n\n}\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16.ldefs", "content": "\n\n\n\n \n National Semiconductor's CompactRISC CR16C little endian\n \n \n\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16.opinion", "content": "\n \n \n \n\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16.pspec", "content": "\n\n\n\t\n\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16B.sinc", "content": "# CR16B\n\n\n# TODO: instructions not implemented\n\n\n# Basic ================================================================================\n\n# define endian=big; # Defined in file that includes this file\ndefine alignment=2;\n\ndefine space ram \t type=ram_space \t size=3 default;\ndefine space register type=register_space size=2;\n\n# Registers ============================================================================\n\n\n\ndefine register offset=0 size=2 [\n R0 R1 R2 R3 R4 R5 R6 R7\n R8 R9 R10 R11 R12_L R12_H R13_L R13_H \n RA_L RA_H SP_L _\n];\n\n\n\n\n# Fields =================================================================================\n\n\ndefine token instr(16)\n b0=(0,0) # bit0\n op1=(1,4) # operand1\n op2=(5,8) # operand2\n opcode1=(9,12) # opcode1\n i=(13,13) # integer operation length bit: i=0=8bit, i=1=16bit\n opcode2=(14,15) # opcode2\n\n op1_b02=(1,3) # bits 0,1,2 of op1\n op1_b12=(2,3) # bits 1,2 of op1\n\n op2_b23=(7,8) # bits 2,3 of op2\n op2_b12=(6,7) # bits 1,2 of op2\n\n opcode1_b23=(11,12) # bits 2,3 of opcode1\n opcode1_b13=(10,12) # bits 1,2,3 of opcode1\n\n ;\n\n\n# Context variables ====================================================\n\n\n# Attach variables =====================================================\n\n# attach normal registers \n#attach variables [ N_0 M_0 ] [\n# r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15\n#];\n\n\n\n\n\n# Constructors =======================================================================\n\n# MOVES\n\n:MOV is opcode2=1 & i & opcode1=0xc & op2 & op1 & b0=1 {\n\n}\n:MOV is opcode2=0 & i & opcode1=0xc & op2 & op1 & b0 {\n\n}\n\n:MOVXB is opcode2=1 & i=1 & opcode1=0x4 & op2 & op1 & b0=0 {\n\n}\n:MOVZB is opcode2=1 & i=1 & opcode1=0x5 & op2 & op1 & b0=0 {\n\n}\n:MOVD is opcode2=1 & i=1 & opcode1_b13=1 & op2 & op1 & b0=0 {\n\n}\n\n\n# ARITHMETIC\n\n:ADD is opcode2=1 & i & opcode1=0 & op2 & op1 & b0=1 {\n\n}\n:ADD is opcode2=0 & i & opcode1=0 & op2 & op1 & b0 {\n\n}\n\n:ADDU is opcode2=1 & i & opcode1=1 & op2 & op1 & b0=1 {\n\n}\n:ADDU is opcode2=0 & i & opcode1=1 & op2 & op1 & b0 {\n\n}\n\n:ADDC is opcode2=1 & i & opcode1=9 & op2 & op1 & b0=1 {\n\n}\n:ADDC is opcode2=0 & i & opcode1=9 & op2 & op1 & b0 {\n\n}\n\n\n:MUL is opcode2=1 & i & opcode1=3 & op2 & op1 & b0=1 {\n\n}\n:MUL is opcode2=0 & i & opcode1=3 & op2 & op1 & b0 {\n\n}\n\n:MULSB is opcode2=1 & i=1 & opcode1=0 & op2 & op1 & b0=0 {\n\n}\n:MULSW is opcode2=1 & i=1 & opcode1=1 & op2 & op1 & b0=0 {\n\n}\n:MULUW is opcode2=1 & i=1 & opcode1=0xf & op2 & op1_b12=0 & b0=0 {\n\n}\n\n:SUB is opcode2=1 & i & opcode1=0xf & op2 & op1 & b0=1 {\n\n}\n:SUB is opcode2=0 & i & opcode1=0xf & op2 & op1 & b0 {\n\n}\n\n:SUBC is opcode2=1 & i & opcode1=0xd & op2 & op1 & b0=1 {\n\n}\n:SUBC is opcode2=0 & i & opcode1=0xd & op2 & op1 & b0 {\n\n}\n\n\n# INTEGER COMPARISON\n\n:CMP is opcode2=1 & i & opcode1=0x7 & op2 & op1 & b0=1 {\n\n}\n:CMP is opcode2=0 & i & opcode1=0x7 & op2 & op1 & b0 {\n\n}\n\n:BEQ0 is opcode2=0 & i & opcode1=0xa & op2_b12=0 & op1 & b0=1 {\n\n}\n\n:BEQ1 is opcode2=0 & i & opcode1=0xa & op2_b12=1 & op1 & b0=1 {\n\n}\n\n:BNE0 is opcode2=0 & i & opcode1=0xa & op2_b12=2 & op1 & b0=1 {\n\n}\n\n:BNE1 is opcode2=0 & i & opcode1=0xa & op2_b12=3 & op1 & b0=1 {\n\n}\n\n\n\n# LOGICAL / BOOLEAN\n:AND is opcode2=1 & i & opcode1=0x8 & op2 & op1 & b0=1 {\n\n}\n:AND is opcode2=0 & i & opcode1=0x8 & op2 & op1 & b0 {\n\n}\n\n:OR is opcode2=1 & i & opcode1=0xe & op2 & op1 & b0=1 {\n\n}\n:OR is opcode2=0 & i & opcode1=0xe & op2 & op1 & b0 {\n\n}\n\n:S is opcode2=1 & i & opcode1=0x7 & op2 & op1 & b0=0 {\n\n}\n\n:XOR is opcode2=1 & i & opcode1=0x6 & op2 & op1 & b0=1 {\n\n}\n:XOR is opcode2=0 & i & opcode1=0x6 & op2 & op1 & b0 {\n\n}\n\n# SHIFTS\n:ASHU is opcode2=1 & i & opcode1=0x4 & op2 & op1 & b0=1 {\n\n}\n:ASHU is opcode2=0 & i & opcode1=0x4 & op2 & op1 & b0 {\n\n}\n\n:LSH is opcode2=1 & i & opcode1=0x5 & op2 & op1 & b0=1 {\n\n}\n:LSH is opcode2=0 & i & opcode1=0x5 & op2 & op1 & b0 {\n\n}\n\n# BITS\n:TBIT is opcode2=1 & i=1 & opcode1=0xb & op2 & op1 & b0=1 {\n\n}\n:TBIT is opcode2=0 & i=1 & opcode1=0xb & op2 & op1 & b0 {\n\n}\n\n:TBIT is opcode2=1 & i & opcode1=2 & op2_b12=2 & op1 & b0=1 {\n\n}\n:TBIT is opcode2=0 & i & opcode1=2 & op2_b12=2 & op1 & b0=1 {\n\n}\n:TBIT is opcode2=0 & i & opcode1=2 & op2_b12=2 & op1 & b0=0 {\n\n}\n\n:CBIT is opcode2=1 & i & opcode1=2 & op2_b12=0 & op1 & b0=1 {\n\n}\n:CBIT is opcode2=0 & i & opcode1=2 & op2_b12=0 & op1 & b0=1 {\n\n}\n:CBIT is opcode2=0 & i & opcode1=2 & op2_b12=0 & op1 & b0=0 {\n\n}\n\n:SBIT is opcode2=1 & i & opcode1=2 & op2_b12=1 & op1 & b0=1 {\n\n}\n:SBIT is opcode2=0 & i & opcode1=2 & op2_b12=1 & op1 & b0=1 {\n\n}\n:SBIT is opcode2=0 & i & opcode1=2 & op2_b12=1 & op1 & b0=0 {\n\n}\n\n# PROCESSOR REGISTER MANIPULATION\n:LPR is opcode2=1 & i=1 & opcode1=8 & op2 & op1 & b0=0 {\n\n}\n:SPR is opcode2=1 & i=1 & opcode1=9 & op2 & op1 & b0=0 {\n\n}\n\n# JUMPS / LINKS\n:Bcond is opcode2=1 & i=0 & opcode1 & op2 & op1 & b0=0 {\n\n}\n:Bcond is opcode2=0 & i=0 & opcode1=0xa & op2 & op1_b02=7 & b0=0 {\n\n}\n:Bcond is opcode2=1 & i=1 & opcode1=0xa & op2 & op1 & b0=0 {\n\n}\n\n:BAL is opcode2=0 & i=1 & opcode1=0xa & op2 & op1_b02=7 & b0=0 {\n\n}\n:BAL is opcode2=1 & i=1 & opcode1=0xb & op2 & op1 & b0=0 {\n\n}\n\n:BR is opcode2=1 & i=0 & opcode1 & op2=0xe & op1 & b0=0 {\n\n}\n:BR is opcode2=0 & i=0 & opcode1=0xa & op2=0xe & op1_b02=7 & b0=0 {\n\n}\n:BR is opcode2=1 & i=1 & opcode1=0xa & op2=0xe & op1 & b0=0 {\n\n}\n\n:EXCP is opcode2=1 & i=1 & opcode1=0xd & op2=0xf & op1 & b0=0 {\n\n}\n\n:Jcond is opcode2=1 & i=0 & opcode1=0xa & op2 & op1 & b0=1 {\n\n}\n:Jcond is opcode2=0 & i=0 & opcode1=0xb & op2 & op1 & b0=1 {\n\n}\n\n:JAL is opcode2=1 & i=1 & opcode1=0xa & op2 & op1 & b0=1 {\n\n}\n:JAL is opcode2=0 & i=0 & opcode1=0xb & op2 & op1 & b0=0 {\n\n}\n\n:JUMP is opcode2=1 & i=0 & opcode1=0xa & op2=0xe & op1 & b0=1 {\n\n}\n:JUMP is opcode2=0 & i=0 & opcode1=0xb & op2=0xe & op1 & b0=1 {\n\n}\n\n:RETX is opcode2=1 & i=1 & opcode1=0xc & op2=0xf & op1=0xf & b0=0 {\n\n}\n\n:PUSH is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=0 & op1 & b0=0 {\n\n}\n\n:POP is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=1 & op1 & b0=0 {\n\n}\n\n:POPRET is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=2 & op1 & b0=0 {\n\n}\n\n:POPRET is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=3 & op1 & b0=0 {\n\n}\n\n\n# LOAD / STORE\n\n:LOAD is opcode2=2 & i & opcode1 & op2 & op1 & b0 {\n\n}\n:LOAD is opcode2=2 & i & opcode1_b23=2 & op2 & op1 & b0=1 {\n\n}\n:LOAD is opcode2=2 & i & opcode1_b23=3 & op2 & op1 & b0=1 {\n\n}\n:LOAD is opcode2=2 & i & opcode1_b23=3 & op2 & op1=0xf & b0=1 {\n\n}\n\n:LOADM is opcode2=1 & i=1 & opcode1=0xf & op2_b23=0 & op1=2 & b0=0 {\n\n}\n\n:STORE is opcode2=3 & i & opcode1 & op2 & op1 & b0 {\n\n}\n:STORE is opcode2=3 & i & opcode1_b23=2 & op2 & op1 & b0=1 {\n\n}\n:STORE is opcode2=3 & i & opcode1_b23=3 & op2 & op1 & b0=1 {\n\n}\n:STORE is opcode2=3 & i & opcode1_b23=3 & op2 & op1=0xf & b0=1 {\n\n}\n:STORE is opcode2=1 & i & opcode1=2 & op2_b12=3 & op1 & b0=1 {\n\n}\n:STORE is opcode2=0 & i & opcode1=2 & op2_b12=3 & op1 & b0=1 {\n\n}\n:STORE is opcode2=0 & i & opcode1=2 & op2_b12=3 & op1 & b0=0 {\n\n}\n\n:STORM is opcode2=1 & i=1 & opcode1=0xf & op2_b23=1 & op1=2 & b0=0 {\n\n}\n\n\n# MISC\n\n:DI is opcode2=1 & i=1 & opcode1=0xe & op2=0xe & op1=0xf & b0=0 {\n\n}\n:EI is opcode2=1 & i=1 & opcode1=0xe & op2=0xf & op1=0xf & b0=0 {\n\n}\n:NOP is opcode2=0 & i=0 & opcode1=0x1 & op2=0 & op1=0 & b0=0 {\n\n}\n:WAIT is opcode2=1 & i=1 & opcode1=0xf & op2=0xf & op1=0xf & b0=0 {\n\n}\n:EIWAIT is opcode2=1 & i=1 & opcode1=0xf & op2=0xf & op1=0x3 & b0=0 {\n\n}\n\n\n\n\n\n\n\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16B.slaspec", "content": "\ndefine endian=little;\n\n@include \"CR16B.sinc\"\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16C.sinc", "content": "# This module defines CR16C\n\n\n# NOTE: Have assumed for now CFG.SR = 0\n\n# sizes:\n# B = byte = 1 byte\n# W = word = 2 bytes\n# D = doubleword = 4 bytes\n\n\n# Basic =====================================================================\n\ndefine alignment=2;\n\ndefine space ram \t type=ram_space \t size=4 default;\ndefine space register type=register_space size=2;\n\n# Registers ==================================================================\n\n# - When CFG.SR is not set, register pairs are defined as follows:\n# (R1,R0), (R2,R1) ... (R11,R10), (R12_L, R11)\n# R12, R13, RA and SP are double-word registers for direct storage of\n# addresses greater than 16 bits.\n#\n# - The most significant 8 bits of ISP and the least significant bit of ISP \n# are forced to 0\n\n# General purpose registers\n# NOTE: RA_L==RA and SP_L==SP\n# NOTE: R12_H, R13_H, RA_H don't actually exist as named registers\n# (name needed for push/pop instructions implementation only)\ndefine register offset=0 size=2 [\n R0 R1 R2 R3 R4 R5 R6 R7\n R8 R9 R10 R11 R12_L R12_H R13_L R13_H \n RA_L RA_H SP_L SP_H\n];\n\ndefine register offset=0 size=4 [\n R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R12 R13 RA SP \n];\n\ndefine register offset=2 size=4 [\n R2R1 R4R3 R6R5 R8R7 R10R9 R12LR11\n];\n\n# Dedicated address registers\ndefine register offset=50 size=4 [ PC ];\ndefine register offset=60 size=2 [ ISPH ISPL USPH USPL INTBASEH INTBASEL ];\ndefine register offset=60 size=4 [ ISP USP INTBASE ];\n\n# Processor Status register\ndefine register offset=80 size=2 [ PSR ];\n#define register offset=90 size=1 [ C T L U F Z N E P I ]; # cond flags\n@define C \"PSR[0,1]\"\n@define T\t\"PSR[1,1]\"\n@define L\t\"PSR[2,1]\"\n@define U\t\"PSR[3,1]\"\n@define F\t\"PSR[5,1]\"\n@define Z\t\"PSR[6,1]\"\n@define N\t\"PSR[7,1]\"\n@define E\t\"PSR[9,1]\"\n@define P\t\"PSR[10,1]\"\n@define I\t\"PSR[11,1]\"\n\n# Configuration register\ndefine register offset=100 size=2 [ CFG ];\n\n# Debug registers\ndefine register offset=110 size=2 [ DBS DSR DCRH DCRL CAR0H CAR0L CAR1H CAR1L ];\ndefine register offset=114 size=4 [ DCR CAR0 CAR1 ];\n \n# these don't actually exist - they are for prd definition (size=4)\ndefine register offset=130 size=4 [ DBS_1 DSR_1 CFG_1 PSR_1 ]; \n\n\n# Fields ======================================================================\n\ndefine token word1(16)\n hi = (8,15) # opcode8\n lo = (0,7) # \n op = (0,15) # opcode16\n op12 = (4,15) # opcode12\n op9 = (7,15) # opcode9\n op7 = (9,15) # opcode7\n op7p3 = (8,8) # p3 for opcode7\n# op10 = (6,15) # opcode10\n op4 = (12,15) # opcode4\n lo1 = (0,3)\n op13 = (3,15) # opcode13\n op11 = (5,15)\n\n dst = (0,3) # register\n src = (4,7)\n src1 = (0,3)\n reg0 = (0,3)\n reg1 = (0,3)\n reg2 = (0,3)\n reg3 = (0,3)\n reg4 = (0,3)\n reg5 = (0,3)\n reg6 = (0,3)\n reg7 = (0,3)\n dst1 = (4,7)\n\n rp_dst = (0,3) # register pair\n rp_src = (4,7)\n rp_dst2 = (4,7)\n rp_src2 = (0,3)\n\n prp_src1 = (0,3)\n prp_dst1 = (0,3)\n\n cond = (4,7)\n\n x4 = (12,15) # generic, nibble 4\n x3 = (8,11) \n x2 = (4,7)\n x1 = (0,3) \n\n x2s = (4,6)\n x3s = (8,11) signed\n b4_8 = (4,8)\n b4_7 = (4,7)\n b4_6 = (4,6)\n b_ra = (7,7) # RA bit for push/pop, fmt 14\n b_prp = (3,3) # prp bit, fmt 18\n b0_2 = (0,2) # fmt 6\n;\n\ndefine token word2(16)\n w2 = (0,15)\n n4 = (12,15) # nibble 4, sometimes an opcode extension\n n3 = (8,11)\n n2 = (4,7)\n n1 = (0,3)\n w2_b0 = (0,0)\n w2_b1_15 = (1,15) signed\n w2_hi = (8,15)\n \n prd = (4,7) # processor registers\n pr = (4,7)\n \n rp_src3 = (0,3) # register pairs\n rp_dst3 = (0,3)\n rp_src6 = (4,7)\n rp_dst6 = (4,7)\n rp_dst7 = (8,11)\n\n src2 = (0,3) # registers\n dst2 = (0,3)\n src5 = (4,7)\n;\n\ndefine token word3(16)\n w3 = (0,15)\n w3_b0 = (0,0)\n w3_b1_15 = (1,15) \n;\n\n# used this token when operands spanned across 2 words\n# | byte1 byte0 byte3 byte2 |\ndefine token doubleword(32)\n dw = (0,31)\n dw_w1 = (0,15) signed\n dw_w2 = (16,31)\n n8 = (12,15) # nibble 4, sometimes an opcode extension\n n7 = (8,11)\n n6 = (4,7) # (cond)\n n5 = (0,3) \n n5s = (0,3) signed\n b1_15 = (17,31)\n b0_15 = (16,31)\n dw_lo = (0,7) signed # for fmt 5\n dw_hi = (8,15) # (op8) \n dw_op7 = (9,15) # (op7)\n dw_op9 = (7,15) # (op9)\n op10 = (6,15) # (opcode 10)\n b_rs = (8,8) # for fmt 13\n dw_b4_6 = (4,6) \n dw_b_prp = (3,3) # for fmt 17\n f17a = (16,19) # for fmt 17 p3\n f17b = (4,5)\n f17c = (30,31)\n f17d = (24,29)\n dw_n2 = (20,23) # fmt 17, p2, 4-bits\n dw_n2b = (20,22) # fmt 17, p2, 3-bit version\n\n rp_dst4 = (4,7)\n rp_src4 = (4,7)\n rp_dst5 = (0,3)\n rp_src5 = (0,3)\n dst3 = (4,7)\n src3 = (4,7)\n dst4 = (0,3)\n src4 = (0,3)\n prp_dst = (0,3)\n prp_src = (0,3)\n;\n\n\n# Attach variables =====================================================\n\n# normal registers \nattach variables [ src dst src1 dst1 src2 dst2 src3 dst3 src4 dst4 src5 ] [\n R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R13_L RA_L SP_L\n];\n\n# register pairs\nattach variables [ rp_src rp_dst rp_src2 rp_dst2 rp_src3 rp_dst3 \n rp_src4 rp_dst4 rp_src5 rp_dst5 rp_src6 rp_dst6 rp_dst7 ] [\n R1R0 R2R1 R3R2 R4R3 R5R4 R6R5 R7R6 R8R7\n R9R8 R10R9 R11R10 R12LR11 R12 R13 RA SP \n];\n\nattach variables [ prp_src prp_dst prp_src1 prp_dst1 ] [ # rrp\n R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R4R3 R6R5\n R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R4R3 R6R5\n];\n\n# processor registers\nattach variables [ pr ] [\n DBS DSR DCRL DCRH CAR0L CAR0H CAR1L CAR1H CFG PSR INTBASEL INTBASEH ISPL ISPH USPL USPH\n];\n\nattach variables [ prd ] [\n DBS_1 DSR_1 DCR _ CAR0 _ CAR1 _ CFG_1 PSR_1 INTBASE _ ISP _ USP _\n];\n\n# Pseudo instructions =================================================\n\ndefine pcodeop trap;\ndefine pcodeop suspend;\n\n# Macros ==============================================================\n\n# Flags set by add instructions\nmacro addflags(op1, op2) { \n $(C) = (carry(op1, op2)); # Check for carry\n $(F) = (scarry(op1, op2)); # Check for overflow\n}\n# Flags set by add instructions (3 operands)\nmacro addflags2(op1, op2, op3) { \n local tmp = (carry(op1,op2)); # Check for carry\n $(C) = (carry(zext(tmp), op3));\n tmp = (scarry(op1,op2)); # Check for overflow\n $(F) = (scarry(zext(tmp), op3)); \n}\n# Flags set by sub instructions\nmacro subflags(op1, op2) { \n $(C) = (op1 < op2); # Check for borrow\n $(F) = sborrow(op1, op2); # Check for overflow\n}\n# Flags set by sub instructions (3 operands)\nmacro subflags2(op1, op2, op3) { \n $(C) = (op1 < (op2 + op3)); # Check for borrow\n local tmp = sborrow(op1, op2); # Check for overflow\n $(F) = sborrow(zext(tmp), op3);\n}\n\n# Flags set by the compare instructions\nmacro compflags(op1, op2) { \n $(Z) = (op1 == op2); # Equal comparison\n $(N) = (op2 s< op1); # Signed comparison\n $(L) = (op2 < op1); # Unsigned comparison\n}\n\n# Operand Display ====================================================\n\nimm20: \"$\"tmp is n5 & dw_w2 [ tmp = (n5 << 16) + dw_w2; ] { export *[const]:3 tmp; }\nimm32: \"$\"tmp is dw_w1 & dw_w2 [ tmp = (dw_w1 << 16) + dw_w2; ] { export *[const]:4 tmp; }\nimm4: \"$\"x2 is x2 { export *[const]:1 x2; } # imm src\nimm4: \"$\"tmp is x2=9 [ tmp = -1; ] { export *[const]:1 tmp; }\nimm4a: \"$\"x2 is x2 { export *[const]:1 x2; } # imm pos\nimm4b: \"$\"n6 is n6 { export *[const]:1 n6; }\nimm4c: \"$\"dw_n2 is dw_n2 { export *[const]:1 dw_n2; }\nimm4d: \"$\"b4_7 is b4_7 { export *[const]:1 b4_7; } # for ash and lsh (signed count)\nimm16: \"$\"w2 is w2 { export *[const]:2 w2; }\nimm5: \"$\"b4_8 is b4_8 { export *[const]:1 b4_8; } # for ash and lsh (signed count)\nimm3: \"$\"b4_6 is b4_6 { export *[const]:1 b4_6; }\nimm3b: \"$\"dw_b4_6 is dw_b4_6 { export *[const]:1 dw_b4_6; }\nimm3c: \"$\"dw_n2b is dw_n2b { export *[const]:1 dw_n2b; }\nimm3d: \"$\"x2s is x2s { export *[const]:1 x2s; } # for ash and lsh (signed count)\n\ncnt3: \"$\"tmp is b4_6 [ tmp = b4_6 + 1; ] { export *[const]:1 tmp; }\ncnt3b: \"$\"tmp is b0_2 [ tmp = b0_2 + 1; ] { export *[const]:1 tmp; }\n\n# If (abs20 > 0xEFFFF) the resulting address is logically ORed with 0xF00000 \n# i.e. addresses from 1M-64k to 1M are re-mapped by the core to 16M-64k to 16M.\nabs20: tmp is n5=0xf & dw_w2 [ tmp = 0xff0000 | dw_w2; ] { \n export *[const]:3 tmp; \n}\n\nabs20: tmp is n5 & dw_w2 [ tmp = (n5 << 16) + dw_w2; ] { \n export *[const]:3 tmp; \n}\n\nabs24: \"*\"tmp is n5 & n7 & b0_15 \n [ tmp = (n5 << 20) + (n7 << 16) + (b0_15); ] { export *[const]:4 tmp; }\n\n# NOTE: disp24 is sign extended to 25 bits - hopefully that doesn't matter here\n# TODO: display *+/*- relative to PC?\ndisp8: \"*\"tmp is x1 & x3s \n [ tmp = (x3s << 5) + (x1 << 1) + inst_start; ] { export *[ram]:4 tmp; } # fmt 21\ndisp16: \"*\"tmp is w2_b1_15 \n [ tmp = (w2_b1_15 << 1) + inst_start; ] { export *[ram]:4 tmp; } # fmt 5, 22 \ndisp24: \"*\"tmp is n5s & n7 & b1_15 \n [ tmp = (n5s << 20) + (n7 << 16) + (b1_15 << 1) + inst_start; ] { export *[ram]:4 tmp; }\ndisp24b:\"*\"tmp is dw_lo & b1_15 \n [ tmp = (dw_lo << 16) + (b1_15 << 1) + inst_start; ] { export *[ram]:4 tmp; }\ndisp4c: \"*\"tmp is x2\n [ tmp = ((x2 + 1) << 1) + inst_start; ] { export *[ram]:4 tmp; }\n\n# disps not relative to PC\ndisp4: \"*\"tmp is x3 [ tmp = (x3 << 1); ] { export *[const]:3 tmp; }\ndisp4b: \"*\"x3 is x3 { export *[const]:3 x3; }\ndisp16b:\"*\"w2 is w2 { export *[const]:2 w2; }\ndisp20: \"*\"tmp is n7 & dw_w2\n [ tmp = (n7 << 16) + dw_w2; ] { export *[const]:3 tmp; } \ndisp14: \"*\"tmp is f17a & f17b & f17c & f17d\n [ tmp = (f17d << 8) + (f17c << 6) + (f17b << 4) + f17a; ] { export *[const]:3 tmp; }\n\n\ncc: \"eq\" is cond=0 { local tmp = $(Z); export tmp; }\ncc: \"ne\" is cond=1 { local tmp = !$(Z); export tmp; }\ncc: \"cs\" is cond=2 { local tmp = $(C); export tmp; }\ncc: \"cc\" is cond=3 { local tmp = !$(C); export tmp; }\ncc: \"hi\" is cond=4 { local tmp = $(L); export tmp; }\ncc: \"ls\" is cond=5 { local tmp = !$(L); export tmp; }\ncc: \"gt\" is cond=6 { local tmp = $(N); export tmp; }\ncc: \"le\" is cond=7 { local tmp = !$(N); export tmp; }\ncc: \"fs\" is cond=8 { local tmp = $(F); export tmp; }\ncc: \"fc\" is cond=9 { local tmp = !$(F); export tmp; }\ncc: \"lo\" is cond=10 { local tmp = !$(Z) && !$(L); export tmp; }\ncc: \"hs\" is cond=11 { local tmp = $(Z) || $(L); export tmp; }\ncc: \"lt\" is cond=12 { local tmp = !$(Z) && !$(N); export tmp; }\ncc: \"ge\" is cond=13 { local tmp = $(Z) || $(N); export tmp; }\nCOND: cc is cc { if (!cc) goto inst_next; }\n\ncc2: \"eq\" is n6=0 { local tmp = $(Z); export tmp; } \ncc2: \"ne\" is n6=1 { local tmp = !$(Z); export tmp; } \ncc2: \"cs\" is n6=2 { local tmp = $(C); export tmp; } \ncc2: \"cc\" is n6=3 { local tmp = !$(C); export tmp; } \ncc2: \"hi\" is n6=4 { local tmp = $(L); export tmp; } \ncc2: \"ls\" is n6=5 { local tmp = !$(L); export tmp; } \ncc2: \"gt\" is n6=6 { local tmp = $(N); export tmp; } \ncc2: \"le\" is n6=7 { local tmp = !$(N); export tmp; } \ncc2: \"fs\" is n6=8 { local tmp = $(F); export tmp; } \ncc2: \"fc\" is n6=9 { local tmp = !$(F); export tmp; } \ncc2: \"lo\" is n6=10 { local tmp = !($(Z) && $(L)); export tmp; }\ncc2: \"hs\" is n6=11 { local tmp = $(Z) || $(L); export tmp; } \ncc2: \"lt\" is n6=12 { local tmp = !($(Z) && $(N)); export tmp; }\ncc2: \"ge\" is n6=13 { local tmp = $(Z) || $(N); export tmp; } \nCOND2: cc2 is cc2 { if (!cc2) goto inst_next; }\n\n\nra: \"RA\" is epsilon { }\nconst1: \"0x0\" is epsilon { }\n\nrs: \"[R12]\" is b_rs=0 { export R12; }\nrs: \"[R13]\" is b_rs=1 { export R13; }\n\nprp2: \"[R12]\" is dw_b_prp=0 { export R12; }\nprp2: \"[R13]\" is dw_b_prp=1 { export R13; }\n\nprp: \"[R12]\" is b_prp=0 { export R12; }\nprp: \"[R13]\" is b_prp=1 { export R13; }\n\ncinv1: \"[i]\" is epsilon { }\ncinv2: \"[i,u]\" is epsilon { }\ncinv3: \"[d]\" is epsilon { }\ncinv4: \"[d,u]\" is epsilon { }\ncinv5: \"[d,i]\" is epsilon { }\ncinv6: \"[d,i,u]\" is epsilon { }\n\n\n\n# Constructors ===============================================================\n\n# MOVES\n\n# MOVB - move low-order byte only\n:MOVB imm4, dst is hi=0x58 & dst & imm4 {\n dst = (dst & 0xff00) | (zext(imm4) & 0x00ff);\n}\n:MOVB imm16, dst is hi=0x58 & x2=11 & dst ; imm16 {\n dst = (dst & 0xff00) | (imm16 & 0x00ff);\n}\n:MOVB src, dst is hi=0x59 & src & dst {\n dst = (dst & 0xff00) | (zext(src:1) & 0x00ff);\n}\n\n# MOVD - move doubleword\n:MOVD imm20, rp_dst4 is dw_hi=0x05 & rp_dst4 & imm20 {\n rp_dst4 = zext(imm20);\n}\n:MOVD imm32, rp_dst is op12=0x007 & rp_dst ; imm32 {\n rp_dst = imm32;\n}\n:MOVD imm4, rp_dst is hi=0x54 & rp_dst & imm4 {\n rp_dst = sext(imm4);\n}\n:MOVD imm16, rp_dst is hi=0x54 & x2=11 & rp_dst ; imm16 {\n rp_dst = sext(imm16);\n}\n:MOVD rp_src, rp_dst is hi=0x55 & rp_dst & rp_src {\n rp_dst = rp_src;\n}\n\n# MOVW - move word\n:MOVW imm4, dst is hi=0x5a & dst & imm4 {\n dst = sext(imm4);\n}\n:MOVW imm16, dst is hi=0x5a & x2=11 & dst ; imm16 {\n dst = imm16;\n}\n:MOVW src, dst is hi=0x5b & src & dst {\n dst = src;\n}\n\n# MOVXB - move low-order byte of src to word dst with sign extension\n:MOVXB src, dst is hi=0x5c & src & dst {\n dst = sext(src:1);\n}\n# MOVXW - move word src to doubleword dst with sign extension\n:MOVXW src, rp_dst is hi=0x5e & src & rp_dst {\n rp_dst = sext(src);\n}\n\n# MOVZB - move low-order byte of src to word dst with zero extension\n:MOVZB src, dst is hi=0x5d & src & dst {\n dst = zext(src:1);\n}\n# MOVZW - move word src to doubleword dst with zero extension\n:MOVZW src, rp_dst is hi=0x5f & src & rp_dst {\n rp_dst = zext(src);\n}\n\n\n# ARITHMETIC\n\n# ADDB - add low-order byte only\n:ADDB imm4, dst is hi=0x30 & dst & imm4 {\n addflags(dst:1, imm4);\n tmp:1 = dst:1 + imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ADDB imm16, dst is hi=0x30 & x2=11 & dst ; imm16 {\n addflags(dst:1, imm16:1);\n tmp:1 = dst:1 + imm16:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ADDB src, dst is hi=0x31 & src & dst {\n addflags(dst:1, src:1);\n tmp:1 = dst:1 + src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# ADDCB - add with carry low-order byte only\n:ADDCB imm4, dst is hi=0x34 & dst & imm4 {\n addflags2(dst:1, imm4, $(C));\n tmp:1 = dst:1 + imm4 + $(C);\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ADDCB imm16, dst is hi=0x34 & x2=11 & dst ; imm16 {\n addflags2(dst:1, imm16:1, $(C));\n tmp:1 = dst:1 + imm16:1 + $(C);\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ADDCB src, dst is hi=0x35 & src & dst {\n addflags2(dst:1, src:1, $(C));\n tmp:1 = dst:1 + src:1 + $(C);\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# ADDCW - add word with carry\n:ADDCW imm4, dst is hi=0x36 & dst & imm4 {\n tmp2:2 = sext(imm4);\n tmp3:2 = zext($(C));\n addflags2(dst, tmp2, tmp3);\n dst = dst + tmp2 + tmp3;\n}\n:ADDCW imm16, dst is hi=0x36 & x2=11 & dst ; imm16 {\n tmp3:2 = zext($(C));\n addflags2(dst, imm16, tmp3);\n dst = dst + imm16 + tmp3;\n}\n:ADDCW src, dst is hi=0x37 & src & dst {\n tmp3:2 = zext($(C));\n addflags2(dst, src, tmp3);\n dst = dst + src + tmp3;\n}\n\n# ADDD - add doubleword\n:ADDD imm20, rp_dst4 is dw_hi=0x04 & rp_dst4 & imm20 {\n tmp:4 = zext(imm20);\n addflags(tmp, rp_dst4);\n rp_dst4 = rp_dst4 + tmp;\n}\n:ADDD imm32, rp_dst is op12=0x002 & rp_dst ; imm32 {\n addflags(imm32, rp_dst);\n rp_dst = rp_dst + imm32;\n}\n:ADDD imm4, rp_dst is hi=0x60 & rp_dst & imm4 {\n tmp:4 = sext(imm4);\n addflags(tmp, rp_dst);\n rp_dst = rp_dst + tmp;\n}\n:ADDD imm16, rp_dst is hi=0x60 & x2=11 & rp_dst ; imm16 {\n tmp:4 = sext(imm16);\n addflags(tmp, rp_dst);\n rp_dst = rp_dst + tmp;\n}\n:ADDD rp_src, rp_dst is hi=0x61 & rp_dst & rp_src {\n addflags(rp_src, rp_dst);\n rp_dst = rp_dst + rp_src;\n}\n\n# ADDUB - add low-order byte only, PSR flags unaffected\n:ADDUB imm4, dst is hi=0x2c & dst & imm4 {\n tmp:1 = dst:1 + imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:NOP is hi=0x2c & dst=0 & x2=0 {\n\n}\n:ADDUB imm16, dst is hi=0x2c & x2=11 & dst ; imm16 {\n tmp:1 = dst:1 + imm16:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ADDUB src, dst is hi=0x2d & src & dst {\n tmp:1 = dst:1 + src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# ADDUW - add word, PSR flags unaffected\n:ADDUW imm4, dst is hi=0x2e & dst & imm4 {\n tmp:2 = sext(imm4);\n dst = dst + tmp;\n}\n:ADDUW imm16, dst is hi=0x2e & x2=11 & dst ; imm16 {\n dst = dst + imm16;\n}\n:ADDUW src, dst is hi=0x2f & src & dst {\n dst = dst + src;\n}\n\n# ADDW - add word\n:ADDW imm4, dst is hi=0x32 & dst & imm4 {\n tmp:2 = sext(imm4); \n addflags(tmp, dst);\n dst = dst + tmp;\n}\n:ADDW imm16, dst is hi=0x32 & x2=11 & dst ; imm16 {\n addflags(imm16, dst);\n dst = dst + imm16;\n}\n:ADDW src, dst is hi=0x33 & src & dst {\n addflags(src, dst);\n dst = dst + src;\n}\n\n# Multiply Signed Q15 Word and Accumulate Long Result\n:MACQW src2, src5, rp_dst7 is op=0x0014 ; n4=13 & src2 & src5 & rp_dst7 {\n tmp:4 = sext(src2) * sext(src5); # TODO based on what Q15 is, this sext may not be right\n rp_dst7 = rp_dst7 + tmp;\n\n# if (!scarry(rp_dst7, tmp)) goto ;\n# rp_dst7 = 0x7fffffff; # overflowed, set to max\n# goto ;\n#\n# if (!sborrow(rp_dst7, tmp)) goto ;\n# rp_dst7 = 0x80000000; # underflowed, set to min\n#\n\n # TODO: if scarry(rp_dst7, tmp) then rp_dst7 = 0x? TODO what is Q15 signed fractional format\n # if sborrow(rp_dst7, tmp) then rp_dst7 = 0x?\n}\n\n# Unsigned Multiply Word and Accumulate Long Result\n:MACUW src2, src5, rp_dst7 is op=0x0014 ; n4=14 & src2 & src5 & rp_dst7 {\n tmp:4 = zext(src2) * zext(src5);\n rp_dst7 = rp_dst7 + tmp;\n \n # if scarry(rp_dst7, tmp) then rp_dst7 = 0xffffffff\n if (!scarry(rp_dst7, tmp)) goto ;\n rp_dst7 = 0xffffffff; # overflowed, set to max\n\n}\n\n# Signed Multiply Word and Add Long Result\n:MACSW src2, src5, rp_dst7 is op=0x0014 ; n4=15 & src2 & src5 & rp_dst7 {\n tmp:4 = sext(src2) * sext(src5);\n rp_dst7 = rp_dst7 + tmp;\n\n # if scarry(rp_dst7, tmp) then rp_dst7 = 0x7fffffff\n if (!scarry(rp_dst7, tmp)) goto ;\n rp_dst7 = 0x7fffffff; # overflowed, set to max\n goto ;\n\n # if sborrow(rp_dst7, tmp) then rp_dst7 = 0x80000000\n if (!sborrow(rp_dst7, tmp)) goto ;\n rp_dst7 = 0x80000000; # underflowed, set to min\n\n}\n\n# MULB - multiply byte\n:MULB imm4, dst is hi=0x64 & dst & imm4 {\n tmp:1 = dst:1 * imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:MULB imm16, dst is hi=0x64 & x2=11 & dst ; imm16 {\n tmp:1 = dst:1 * imm16:1;\n dst = (dst & 0xff00) + zext(tmp);}\n:MULB src, dst is hi=0x65 & src & dst{\n tmp:1 = dst:1 * src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# Signed Multiply Byte, Word Result\n:MULSB src, dst is hi=0x0b & src & dst {\n dst = sext(src:1) * sext(dst:1);\n}\n\n# Signed Multiply Word, Long Result\n:MULSW src, rp_dst is hi=0x62 & src & rp_dst {\n rp_dst = sext(src) * sext(rp_dst:2);\n}\n\n# Unsigned Multiply Word, Long Result\n:MULUW src, rp_dst is hi=0x63 & src & rp_dst {\n rp_dst = zext(src) * zext(rp_dst:2);\n}\n\n# MULW - multiply word\n:MULW imm4, dst is hi=0x66 & dst & imm4 {\n tmp:2 = sext(imm4);\n dst = dst * tmp;\n}\n:MULW imm16, dst is hi=0x66 & x2=11 & dst ; imm16 {\n dst = dst * imm16;\n}\n:MULW src, dst is hi=0x67 & src & dst {\n dst = dst * src;\n}\n\n# SUBB - subtract low-order byte only\n:SUBB imm4, dst is hi=0x38 & dst & imm4 {\n subflags(dst:1, imm4);\n tmp:1 = dst:1 - imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:SUBB imm16, dst is hi=0x38 & x2=11 & dst ; imm16 {\n subflags(dst:1, imm16:1);\n tmp:1 = dst:1 - imm16:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:SUBB src, dst is hi=0x39 & src & dst {\n subflags(dst:1, src:1);\n tmp:1 = dst:1 - src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# SUBCB - subtract with carry low-order byte only\n:SUBCB imm4, dst is hi=0x3c & dst & imm4 {\n subflags2(dst:1, imm4, $(C));\n tmp:1 = dst:1 - imm4 - $(C);\n dst = (dst & 0xff00) + zext(tmp);\n}\n:SUBCB imm16, dst is hi=0x3c & x2=11 & dst ; imm16 {\n subflags2(dst:1, imm16:1, $(C));\n tmp:1 = dst:1 - imm16:1 - $(C);\n dst = (dst & 0xff00) + zext(tmp);\n}\n:SUBCB src, dst is hi=0x3d & src & dst {\n subflags2(dst:1, src:1, $(C));\n tmp:1 = dst:1 - src:1 - $(C);\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# SUBCW - subtract word with carry\n:SUBCW imm4, dst is hi=0x3e & dst & imm4 {\n tmp2:2 = sext(imm4);\n tmp3:2 = zext($(C));\n subflags2(dst, tmp2, tmp3);\n dst = dst - tmp2 - tmp3;\n}\n:SUBCW imm16, dst is hi=0x3e & x2=11 & dst ; imm16 {\n tmp3:2 = zext($(C));\n subflags2(dst, imm16, tmp3);\n dst = dst - imm16 - tmp3;\n}\n:SUBCW src, dst is hi=0x3f & src & dst {\n tmp3:2 = zext($(C));\n subflags2(dst, src, tmp3);\n dst = dst - src - tmp3;\n}\n\n# SUBD - subtract doubleword\n:SUBD rp_src6, rp_dst3 is op=0x0014 ; n4=12 & n3=0 & rp_src6 & rp_dst3 { # fmt 1\n subflags(rp_dst3, rp_src6);\n rp_dst3 = rp_dst3 - rp_src6;\n}\n:SUBD imm32, rp_dst is op12=0x003 & rp_dst ; imm32 {\n subflags(imm32, rp_dst);\n rp_dst = rp_dst - imm32;\n}\n\n# SUBW - subtract word\n:SUBW imm4, dst is hi=0x3a & dst & imm4 {\n tmp:2 = sext(imm4);\n subflags(tmp, dst);\n dst = dst - tmp;\n}\n:SUBW imm16, dst is hi=0x3a & x2=11 & dst ; imm16 {\n subflags(imm16, dst);\n dst = dst - imm16;\n}\n:SUBW src, dst is hi=0x3b & src & dst {\n subflags(src, dst);\n dst = dst - src;\n}\n\n\n# INTEGER COMPARISON\n\n# CMPB - compare low-order byte only\n:CMPB imm4, src1 is hi=0x50 & src1 & imm4 {\n compflags(imm4, src1:1);\n}\n:CMPB imm16, src1 is hi=0x50 & x2=11 & src1 ; imm16 {\n compflags(imm16:1, src1:1);\n}\n:CMPB src, src1 is hi=0x51 & src & src1 {\n compflags(src:1, src1:1);\n}\n\n# CMPD - compare doubleword\n:CMPD imm32, rp_src2 is op12=0x009 & rp_src2 ; imm32 {\n compflags(imm32, rp_src2);\n}\n:CMPD imm4, rp_src2 is hi=0x56 & rp_src2 & imm4 {\n tmp:4 = sext(imm4);\n compflags(tmp, rp_src2);\n}\n:CMPD imm16, rp_src2 is hi=0x56 & x2=11 & rp_src2 ; imm16 {\n tmp:4 = sext(imm16);\n compflags(tmp, rp_src2);\n}\n:CMPD rp_src, rp_src2 is hi=0x57 & rp_src & rp_src2 {\n compflags(rp_src, rp_src2);\n}\n\n# CMPW - compare word\n:CMPW imm4, src1 is hi=0x52 & src1 & imm4 {\n tmp:2 = sext(imm4);\n compflags(tmp, src1);\n}\n:CMPW imm16, src1 is hi=0x52 & x2=11 & src1 ; imm16 {\n compflags(imm16, src1);\n}\n:CMPW src, src1 is hi=0x53 & src & src1 {\n compflags(src, src1);\n}\n\n\n# LOGICAL / BOOLEAN\n\n# ANDB - and low-order byte only\n:ANDB imm4, dst is hi=0x20 & dst & imm4 {\n tmp:1 = dst:1 & imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ANDB imm16, dst is hi=0x20 & x2=11 & dst ; imm16 {\n tmp:1 = dst:1 & imm16:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ANDB src, dst is hi=0x21 & src & dst {\n tmp:1 = dst:1 & src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# ANDW - and word\n:ANDW imm4, dst is hi=0x22 & dst & imm4 {\n tmp:2 = sext(imm4); \n dst = dst & tmp;\n}\n:ANDW imm16, dst is hi=0x22 & x2=11 & dst ; imm16 {\n dst = dst & imm16;\n}\n:ANDW src, dst is hi=0x23 & src & dst {\n dst = dst & src;\n}\n\n# ANDD - and doubleword\n:ANDD imm32, rp_dst is op12=0x004 & rp_dst ; imm32 {\n rp_dst = rp_dst & imm32;\n}\n:ANDD rp_src6, rp_dst3 is op=0x0014 ; n4=11 & rp_src6 & rp_dst3 { # fmt 1\n rp_dst3 = rp_dst3 & rp_src6;\n}\n\n# ORB - or low-order byte only\n:ORB imm4, dst is hi=0x24 & dst & imm4 {\n tmp:1 = dst:1 | imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ORB imm16, dst is hi=0x24 & x2=11 & dst ; imm16 {\n tmp:1 = dst:1 | imm16:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:ORB src, dst is hi=0x25 & src & dst {\n tmp:1 = dst:1 | src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# ORW - or word\n:ORW imm4, dst is hi=0x26 & dst & imm4 {\n tmp:2 = sext(imm4); \n dst = dst | tmp;\n}\n:ORW imm16, dst is hi=0x26 & x2=11 & dst ; imm16 {\n dst = dst | imm16;\n}\n:ORW src, dst is hi=0x27 & src & dst {\n dst = dst | src;\n}\n\n# ORD - or doubleword\n:ORD imm32, rp_dst is op12=0x005 & rp_dst ; imm32 {\n rp_dst = rp_dst | imm32;\n}\n:ORD rp_src6, rp_dst3 is op=0x0014 ; n4=9 & rp_src6 & rp_dst3 { # fmt 1\n rp_dst3 = rp_dst3 | rp_src6;\n}\n\n# S - save condition as boolean\n:S^COND dst is hi=0x08 & COND & dst {\n dst = 0;\n build COND;\n dst = 1;\n}\n:S dst is hi=0x08 & cond=14 & dst {\n dst = 1;\n}\n:S dst is hi=0x08 & cond=15 & dst {\n dst = 1;\n}\n\n# XORB - xor low-order byte only\n:XORB imm4, dst is hi=0x28 & dst & imm4 {\n tmp:1 = dst:1 ^ imm4;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:XORB imm16, dst is hi=0x28 & x2=11 & dst ; imm16 {\n tmp:1 = dst:1 ^ imm16:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n:XORB src, dst is hi=0x29 & src & dst {\n tmp:1 = dst:1 ^ src:1;\n dst = (dst & 0xff00) + zext(tmp);\n}\n\n# XORW - xor word\n:XORW imm4, dst is hi=0x2a & dst & imm4 {\n tmp:2 = sext(imm4); \n dst = dst ^ tmp;\n}\n:XORW imm16, dst is hi=0x2a & x2=11 & dst ; imm16 {\n dst = dst ^ imm16;\n}\n:XORW src, dst is hi=0x2b & src & dst {\n dst = dst ^ src;\n}\n\n# XORD - xor doubleword\n:XORD imm32, rp_dst is op12=0x006 & rp_dst ; imm32 {\n rp_dst = rp_dst ^ imm32;\n}\n:XORD rp_src6, rp_dst3 is op=0x0014 ; n4=10 & rp_src6 & rp_dst3 { # fmt 1\n rp_dst3 = rp_dst3 ^ rp_src6;\n}\n\n\n# SHIFTS\n\n# TODO: left shift displays \"+\", right shift displays \"-\"\n\nmacro do_ash(count, dest) {\n local shift = count:1;\n local lf = ( shift) * zext(shift s> 0);\n local rt = (-shift) * zext(shift s< 0);\n dest = dest << lf;\n dest = dest s>> rt;\n}\n\nmacro do_ashb(count, dest) {\n local tmp = dest & 0xff;\n do_ash(count, tmp);\n dest = (dest & 0xff00) | (tmp & 0x00ff);\n}\n\nmacro do_lsh(count, dest) {\n local shift = count:1;\n local lf = ( shift) * zext(shift s> 0);\n local rt = (-shift) * zext(shift s< 0);\n dest = dest << lf;\n dest = dest >> rt;\n}\n\nmacro do_lshb(count, dest) {\n local tmp = dest & 0xff;\n do_lsh(count, tmp);\n dest = (dest & 0xff00) | (tmp & 0x00ff);\n}\n\n# ASHUB - Arithmetic shift low-order byte only\n:ASHUB imm3d, dst\tis op9=0b010000000 & imm3d & dst\t{ do_ashb(imm3d, dst); }\n:ASHUB imm3d, dst\tis op9=0b010000001 & imm3d & dst\t{ do_ashb(imm3d-8, dst); }\n:ASHUB src, dst\t\tis hi=0x41 & src & dst\t\t\t{ do_ashb(src, dst); }\n\n# ASHUD - Arithmetic shift doubleword\n:ASHUD imm5, rp_dst\tis op7=0b0100110 & imm5 & rp_dst\t{ do_ash(imm5, rp_dst); }\n:ASHUD imm5, rp_dst\tis op7=0b0100111 & imm5 & rp_dst\t{ do_ash(imm5-32, rp_dst); }\n:ASHUD src, rp_dst\tis hi=0x48 & src & rp_dst\t\t{ do_ash(src, rp_dst); }\n\n# ASHUW - Arithmetic shift word\n:ASHUW imm4d, dst\tis hi=0x42 & imm4d & dst\t\t{ do_ash(imm4d, dst); }\n:ASHUW imm4d, dst\tis hi=0x43 & imm4d & dst\t\t{ do_ash(imm4d-16, dst); }\n:ASHUW src, dst\t\tis hi=0x45 & src & dst\t\t\t{ do_ash(src, dst); }\n\n# LSHB - Logical shift low-order byte only\n:LSHB imm3d, dst\tis op9=0b000010011 & imm3d & dst\t{ do_lshb(imm3d-8, dst); }\n:LSHB src, dst\t\tis hi=0x44 & src & dst\t\t\t{ do_lshb(src, dst); }\n\n# LSHD - Logical shift doubleword\n:LSHD imm5, rp_dst\tis op7=0b0100101 & imm5 & rp_dst\t{ do_lsh(imm5-32, rp_dst); }\n:LSHD src, rp_dst\tis hi=0x47 & src & rp_dst\t\t{ do_lsh(src, rp_dst); }\n\n# LSHW - Logical shift word\n:LSHW imm4d, dst\tis hi=0x49 & imm4d & dst\t\t{ do_lsh(imm4d-16, dst); }\n:LSHW src, dst\t\tis hi=0x46 & src & dst\t\t\t{ do_lsh(src, dst); }\n\n# BITS\n# - for bit ops, dsp(n) is always unsigned\n\n# CBITB - clear bit in low-order byte\n:CBITB imm3c, prp2 disp14(prp_dst) is op10=0x1aa & imm3c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3c;\n $(F) = (val & mask) >> imm3c; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3b, disp20(dst4) is op=0x0010 ; n8=4 & imm3b & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3, const1(rp_dst) is op9=0x0d4 & imm3 & rp_dst & const1 { # fmt 9\n tmp:4 = rp_dst:4;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3;\n $(F) = (val & mask) >> imm3; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3, disp16b(rp_dst) is op9=0x0d6 & imm3 & rp_dst ; disp16b { # fmt 10\n tmp:4 = rp_dst:4 + zext(disp16b);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3;\n $(F) = (val & mask) >> imm3; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3b, disp20(rp_dst5) is op=0x0010 ; n8=5 & imm3b & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3b, disp20(prp_dst) is op=0x0010 ; n8=6 & imm3b & disp20 & prp_dst { # fmt 2\n tmp:4 = prp_dst:4 + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3b, abs20 is dw_op9=0x0d7 & imm3b & abs20 { # fmt 7\n tmp:4 = zext(abs20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3b, rs abs20 is dw_hi=0x68 & imm3b & rs & abs20 { # fmt 8\n tmp:4 = zext(abs20) + rs:4;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n:CBITB imm3b, abs24 is op=0x0010 ; n8=7 & imm3b & abs24 { # fmt 3\n tmp:4 = abs24;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n mask = ~mask;\n *:1 tmp = val & mask; # clear bit, store\n}\n\n# CBITW - clear bit in word\n:CBITW imm4c, prp2 disp14(prp_dst) is op10=0x1ab & imm4c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4c;\n bit:2 = (val & mask) >> imm4c;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4b, disp20(dst4) is op=0x0011 ; n8=4 & imm4b & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4a, const1(rp_dst) is hi=0x6e & imm4a & rp_dst & const1 {\n tmp:4 = rp_dst:4;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4a, disp16b(rp_dst) is hi=0x69 & imm4a & rp_dst ; disp16b {\n tmp:4 = rp_dst:4 + zext(disp16b);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4b, disp20(rp_dst5) is op=0x0011 ; n8=5 & rp_dst5 & imm4b & disp20 {\n tmp:4 = rp_dst5:4 + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4b, disp20(prp_dst) is op=0x0011 ; n8=6 & imm4b & disp20 & prp_dst { # fmt 2\n tmp:4 = prp_dst:4 + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4b, abs20 is dw_hi=0x6f & imm4b & abs20 { # fmt 12\n tmp:4 = zext(abs20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4b, rs abs20 is dw_op7=0x36 & imm4b & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n:CBITW imm4b, abs24 is op=0x0011 ; n8=7 & imm4b & abs24 { # fmt 3\n tmp:4 = abs24;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n mask = ~mask;\n *:2 tmp = val & mask; # clear bit, store\n}\n\n# SBITB - set bit in low-order byte\n:SBITB imm3c, prp2 disp14(prp_dst) is op10=0x1ca & imm3c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3c;\n $(F) = (val & mask) >> imm3c; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3b, disp20(dst4) is op=0x0010 ; n8=8 & imm3b & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3, const1(rp_dst) is op9=0x0e4 & imm3 & rp_dst & const1 { # fmt 9\n tmp:4 = rp_dst:4;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3;\n $(F) = (val & mask) >> imm3; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3, disp16b(rp_dst) is op9=0x0e6 & imm3 & rp_dst ; disp16b { # fmt 10\n tmp:4 = rp_dst:4 + zext(disp16b);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3;\n $(F) = (val & mask) >> imm3; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3b, disp20(rp_dst5) is op=0x0010 ; n8=9 & imm3b & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3b, disp20(prp_dst) is op=0x0010 ; n8=10 & imm3b & disp20 & prp_dst { # fmt 2\n tmp:4 = prp_dst:4 + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3b, abs20 is dw_op9=0x0e7 & imm3b & abs20 { # fmt 7\n tmp:4 = zext(abs20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3b, rs abs20 is dw_hi=0x70 & imm3b & rs & abs20 { # fmt 8\n tmp:4 = zext(abs20) + rs:4;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n:SBITB imm3b, abs24 is op=0x0010 ; n8=11 & imm3b & abs24 { # fmt 3\n tmp:4 = abs24;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n *:1 tmp = val | mask; # set bit, store\n}\n\n# SBITW - set bit in word\n:SBITW imm4c, prp2 disp14(prp_dst) is op10=0x1cb & imm4c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4c;\n bit:2 = (val & mask) >> imm4c;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4b, disp20(dst4) is op=0x0011 ; n8=8 & imm4b & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4a, const1(rp_dst) is hi=0x76 & imm4a & const1 & rp_dst { # fmt 15\n tmp:4 = rp_dst:4;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4a, disp16b(rp_dst) is hi=0x71 & imm4a & rp_dst ; disp16b { # fmt 16\n tmp:4 = rp_dst:4 + zext(disp16b);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4b, disp20(rp_dst5) is op=0x0011 ; n8=9 & rp_dst5 & imm4b & disp20 {\n tmp:4 = rp_dst5:4 + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4b, disp20(prp_dst) is op=0x0011 ; n8=10 & imm4b & disp20 & prp_dst {\n tmp:4 = prp_dst:4 + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4b, abs20 is dw_hi=0x77 & imm4b & abs20 { # fmt 12\n tmp:4 = zext(abs20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4b, rs abs20 is dw_op7=0x3a & imm4b & rs & abs20 { \n tmp:4 = zext(abs20) + rs:4;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n:SBITW imm4b, abs24 is op=0x0011 ; n8=11 & imm4b & abs24 { # fmt 3\n tmp:4 = abs24;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n *:2 tmp = val | mask; # clear bit, store\n}\n\n# TBIT - test bit\n:TBIT imm4a, src1 is hi=0x06 & imm4a & src1 {\n tmp:4 = zext(src1);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n}\n:TBIT src, src1 is hi=0x07 & src & src1 {\n tmp:4 = zext(src1);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << src;\n bit:2 = (val & mask) >> src;\n $(F) = bit:1; # save bit\n}\n\n# TBITB - test bit in low-order byte\n:TBITB imm3c, prp2 disp14(prp_dst) is op10=0x1ea & imm3c & prp2 & disp14 & prp_dst { # fmt 17 (affected by CFG.SR)\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3c;\n $(F) = (val & mask) >> imm3c; # save bit\n}\n:TBITB imm3b, disp20(dst4) is op=0x0010 ; n8=12 & imm3b & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n}\n:TBITB imm3, const1(rp_dst) is op9=0x0f4 & imm3 & rp_dst & const1 { # fmt 9\n tmp:4 = rp_dst:4;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3;\n $(F) = (val & mask) >> imm3; # save bit\n}\n:TBITB imm3, disp16b(rp_dst) is op9=0x0f6 & imm3 & rp_dst ; disp16b { # fmt 10\n tmp:4 = rp_dst:4 + zext(disp16b);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3;\n $(F) = (val & mask) >> imm3; # save bit\n}\n:TBITB imm3b, disp20(rp_dst5) is op=0x0010 ; n8=13 & imm3b & disp20 & rp_dst5 {\n tmp:4 = rp_dst5:4 + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n}\n:TBITB imm3b, disp20(prp_dst) is op=0x0010 ; n8=14 & imm3b & disp20 & prp_dst {\n tmp:4 = prp_dst:4 + zext(disp20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n}\n:TBITB imm3b, abs20 is dw_op9=0x0f7 & imm3b & abs20 { # fmt 7\n tmp:4 = zext(abs20);\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n}\n:TBITB imm3b, rs abs20 is dw_hi=0x78 & imm3b & rs & abs20 { # fmt 8\n tmp:4 = zext(abs20) + rs:4;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n}\n:TBITB imm3b, abs24 is op=0x0010 ; n8=15 & imm3b & abs24 { # fmt 3\n tmp:4 = abs24;\n val:1 = *:1 tmp; # load dst operand\n local mask = 1 << imm3b;\n $(F) = (val & mask) >> imm3b; # save bit\n}\n\n# TBITW - test bit in word\n:TBITW imm4c, prp2 disp14(prp_dst) is op10=0x1eb & imm4c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4c;\n bit:2 = (val & mask) >> imm4c;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4b, disp20(dst4) is op=0x0011 ; n8=12 & imm4b & disp20 & dst4 {\n tmp:4 = zext(dst4) + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4a, const1(rp_dst) is hi=0x7e & imm4a & const1 & rp_dst { # fmt 15\n tmp:4 = rp_dst:4;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4a, disp16b(rp_dst) is hi=0x79 & imm4a & rp_dst ; disp16b { # fmt 16\n tmp:4 = rp_dst:4 + zext(disp16b);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4a;\n bit:2 = (val & mask) >> imm4a;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4b, disp20(rp_dst5) is op=0x0011 ; n8=13 & rp_dst5 & imm4b & disp20 {\n tmp:4 = rp_dst5:4 + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4b, disp20(prp_dst) is op=0x0011 ; n8=14 & imm4b & disp20 & prp_dst {\n tmp:4 = prp_dst:4 + zext(disp20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4b, abs20 is dw_hi=0x7f & imm4b & abs20 {\n tmp:4 = zext(abs20);\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4b, rs abs20 is dw_op7=0x3e & imm4b & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n}\n:TBITW imm4b, abs24 is op=0x0011 ; n8=15 & imm4b & abs24 {\n tmp:4 = abs24;\n val:2 = *:2 tmp; # load dst operand\n mask:2 = 1 << imm4b;\n bit:2 = (val & mask) >> imm4b;\n $(F) = bit:1; # save bit\n}\n\n\n# PROCESSOR REGISTER MANIPULATION\n\n# TODO:\n# For the LPR instruction, if dest is ISPL or INTBASEL the least significant\n# bit (bit 0) of the address is 0. If dest is INTBASEH, ISPH, USPH, CAR0H,\n# or CAR1H bits 8 through 15 are always written as 0.\n# For the LPRD instruction, if dest is ISP or INTBASE the least significant\n# bit (bit 0) of the address is 0. If dest is INTBASE, ISP, USP, CAR0, or\n# CAR1 bits 24 through 31 are always written as 0.\n\n# Load Processor Register (word)\n:LPR src2, pr is op=0x0014 ; n4=0 & n3=0 & pr & src2 {\n pr = src2;\n}\n\n# Load Processor Register (doubleword)\n:LPRD rp_src3, prd is op=0x0014 ; n4=1 & n3=0 & prd & rp_src3 {\n prd = rp_src3;\n}\n\n# Store Processor Register (word)\n:SPR pr, dst2 is op=0x0014 ; n4=2 & n3=0 & pr & dst2 {\n dst2 = pr;\n}\n\n# Store Processor Register (doubleword)\n:SPRD prd, rp_dst3 is op=0x0014 ; n4=3 & n3=0 & prd & rp_dst3 {\n rp_dst3 = prd;\n}\n\n\n# JUMPS AND LINKS\n\n# BAL - Branch and Link\n:BAL (RA), disp24b is dw_hi=0xc0 & disp24b & RA { \n RA = inst_next >> 1; # save bits 1 to 23 in link reg RA\n PC = &disp24b; # PC = PC + sext25(disp) TODO: 25 bits?\n call disp24b;\n}\n:BAL rp_dst4, disp24 is op=0x0010 ; n8=2 & disp24 & rp_dst4 {\n # rp link is at word2 (4,7)\n rp_dst4 = inst_next >> 1; # save bits 1 to 23 in link reg\n PC = &disp24; # PC = PC + sext25(disp) TODO: 25 bits?\n call disp24;\n}\n\n# BEQ0B - branch if low byte equals 0\n:BEQ0B src1, disp4c is hi=0x0c & src1 & disp4c { \n if (src1:1 != 0) goto inst_next; # don't branch if not equal\n PC = &disp4c; # branch\n goto disp4c;\n}\n# BEQ0W - branch if word equals 0\n:BEQ0W src1, disp4c is hi=0x0e & src1 & disp4c {\n if (src1 != 0) goto inst_next; # don't branch if not equal\n PC = &disp4c; # branch\n goto disp4c;\n}\n# BNE0B - branch if low byte does not equal 0\n:BNE0B src1, disp4c is hi=0x0d & src1 & disp4c {\n if (src1:1 == 0) goto inst_next; # don't branch if equal\n PC = &disp4c; # branch\n goto disp4c;\n}\n:BNE0W src1, disp4c is hi=0x0f & src1 & disp4c {\n if (src1 == 0) goto inst_next; # don't branch if equal\n PC = &disp4c; # branch\n goto disp4c;\n}\n\n# BR - branch (conditional and unconditional)\n:BR^COND disp8 is op4=1 & COND & disp8 { # BR (conditional)\n build COND;\n PC = &disp8;\n goto disp8;\n}\n:BR disp8 is op4=1 & cond=14 & disp8 { # BR cond=14 (always)\n PC = &disp8;\n goto disp8;\n}\n:BR disp8 is op4=1 & cond=15 & disp8 { # BR cond=15 (unconditional)\n PC = &disp8;\n goto disp8;\n}\n\n:BR^COND disp16 is hi=0x18 & lo1=0 & COND ; disp16 { # BR (conditional)\n build COND;\n PC = &disp16;\n goto disp16;\n}\n:BR disp16 is hi=0x18 & lo1=0 & cond=14 ; disp16 { # BR cond=14 (always)\n PC = &disp16;\n goto disp16;\n}\n:BR disp16 is hi=0x18 & lo1=0 & cond=15 ; disp16 { # BR cond=15 (unconditional)\n PC = &disp16;\n goto disp16;\n}\n\n:BR^COND2 disp24 is op=0x0010 ; n8=0 & COND2 & disp24 { # BR (conditional)\n build COND2;\n PC = &disp24;\n goto disp24;\n}\n:BR disp24 is op=0x0010 ; n8=0 & n6=14 & disp24 { # BR cond=14 (always)\n PC = &disp24;\n goto disp24;\n}\n:BR disp24 is op=0x0010 ; n8=0 & n6=15 & disp24 { # BR cond=15 (unconditional)\n PC = &disp24;\n goto disp24;\n}\n\n# EXCP - Exception\n:EXCP x1 is op12=0x00c & x1 {\n# *:4(ISP:3) = zext(inst_start);\n *:2(ISP:4) = PSR; # push PSR onto interrupt stack\n ISP = ISP - 2;\n *:4(ISP:4) = inst_start; # push ret addr (current instruction) onto interrupt stack\n ISP = ISP - 4;\n trap();\n}\n\n# JAL - Jump and Link\n:JAL rp_dst is op12=0x00d & rp_dst {\n RA = inst_next >> 1;\n local tmp = rp_dst << 1;\n PC = tmp:4;\n call [PC];\n}\n:JAL rp_dst6 is op=0x0014 ; n4=8 & n3=0 & rp_dst6 & rp_dst3 {\n # rp link is at word2 (0,3)\n rp_dst3 = inst_next >> 1;\n local tmp = rp_dst6 << 1;\n PC = tmp:4;\n call [PC];\n}\n\n# J - Jump - special case jumping through link register\n:J^COND RA is hi=0x0a & COND & rp_dst=14 & RA { # conditional\n build COND;\n local tmp = RA << 1;\n PC = tmp:4;\n return [PC];\n}\n:JUMP RA is hi=0xa & cond=14 & rp_dst=14 & RA { # always\n local tmp = RA << 1;\n PC = tmp:4;\n return [PC]; \n}\n:JUSR RA is hi=0xa & cond=15 & rp_dst=14 & RA { # unconditional\n $(U) = 1;\n local tmp = RA << 1;\n PC = tmp:4;\n return [PC]; \n}\n\n# J - Jump (conditional and unconditional)\n:J^COND rp_dst is hi=0x0a & COND & rp_dst { # conditional\n build COND;\n local tmp = rp_dst << 1;\n PC = tmp:4;\n goto [PC];\n}\n:JUMP rp_dst is hi=0xa & cond=14 & rp_dst { # always\n local tmp = rp_dst << 1;\n PC = tmp:4;\n goto [PC]; \n}\n:JUSR rp_dst is hi=0xa & cond=15 & rp_dst { # unconditional\n $(U) = 1;\n local tmp = rp_dst << 1;\n PC = tmp:4;\n goto [PC]; \n}\n\nattach variables [ reg0 ] [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R13_L RA_L SP_L ];\nattach variables [ reg1 ] [ R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_H RA_H SP_H ];\nattach variables [ reg2 ] [ R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L RA_L SP_L R0 ];\nattach variables [ reg3 ] [ R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_H SP_H R1 ];\nattach variables [ reg4 ] [ R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L SP_L R0 R3 ];\nattach variables [ reg5 ] [ R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L RA_H SP_H R1 R4 ];\nattach variables [ reg6 ] [ R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L RA_H SP_L R0 R2 R5 ];\nattach variables [ reg7 ] [ R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L RA_H SP_L SP_H R1 R3 R6 ];\n\nmacro push_one(reg) {\n SP = SP - 2;\n *SP = reg;\n}\n\nmacro pop_one(reg) {\n reg = *SP;\n SP = SP + 2;\n}\n\nmacro push_ra() {\n SP = SP - 4;\n *SP = RA;\n}\n\nmacro pop_ra() {\n RA = *SP;\n SP = SP + 4;\n}\nmacro do_pop_ret() {\n tmp:4 = RA << 1;\n PC = tmp;\n return [PC];\n}\n\npush_args: \"$\"tmp, reg0 is b_ra=0 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { }\npush_args: \"$\"tmp, reg0, \"ra\" is b_ra=1 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { push_ra(); }\n\npop_args: \"$\"tmp, reg0 is b_ra=0 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { }\npop_args: \"$\"tmp, reg0, \"ra\" is b_ra=1 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { pop_ra(); }\n\n:push push_args\nis hi=1 & b4_6=0 & reg0 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg0);\n}\n\n:push push_args\nis hi=1 & b4_6=1 & reg0 & reg1 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg1);\n\tpush_one(reg0);\n}\n\n:push push_args\nis hi=1 & b4_6=2 & reg0 & reg1 & reg2 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg2);\n\tpush_one(reg1);\n\tpush_one(reg0);\n}\n\n:push push_args\nis hi=1 & b4_6=3 & reg0 & reg1 & reg2 & reg3 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg3);\n\tpush_one(reg2);\n\tpush_one(reg1);\n\tpush_one(reg0);\n}\n\n:push push_args\nis hi=1 & b4_6=4 & reg0 & reg1 & reg2 & reg3 & reg4 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg4);\n\tpush_one(reg3);\n\tpush_one(reg2);\n\tpush_one(reg1);\n\tpush_one(reg0);\n}\n\n:push push_args\nis hi=1 & b4_6=5 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg5);\n\tpush_one(reg4);\n\tpush_one(reg3);\n\tpush_one(reg2);\n\tpush_one(reg1);\n\tpush_one(reg0);\n}\n\n:push push_args\nis hi=1 & b4_6=6 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg6);\n\tpush_one(reg5);\n\tpush_one(reg4);\n\tpush_one(reg3);\n\tpush_one(reg2);\n\tpush_one(reg1);\n\tpush_one(reg0);\n\n}\n\n:push push_args\nis hi=1 & b4_6=7 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 & reg7 & push_args\n{\n\tbuild push_args;\n\tpush_one(reg7);\n\tpush_one(reg6);\n\tpush_one(reg5);\n\tpush_one(reg4);\n\tpush_one(reg3);\n\tpush_one(reg2);\n\tpush_one(reg1);\n\tpush_one(reg0);\n}\n\npop_ret: \"ret\" is hi=3 { do_pop_ret(); }\npop_ret: \"\" is hi=2 { }\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=0 & reg0\n{\n\tpop_one(reg0);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=1 & reg0 & reg1\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=2 & reg0 & reg1 & reg2\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tpop_one(reg2);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=3 & reg0 & reg1 & reg2 & reg3\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tpop_one(reg2);\n\tpop_one(reg3);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=4 & reg0 & reg1 & reg2 & reg3 & reg4\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tpop_one(reg2);\n\tpop_one(reg3);\n\tpop_one(reg4);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=5 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tpop_one(reg2);\n\tpop_one(reg3);\n\tpop_one(reg4);\n\tpop_one(reg5);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=6 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tpop_one(reg2);\n\tpop_one(reg3);\n\tpop_one(reg4);\n\tpop_one(reg5);\n\tpop_one(reg6);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n:pop^pop_ret pop_args\nis pop_ret & pop_args & op7=1 & b4_6=7 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 & reg7\n{\n\tpop_one(reg0);\n\tpop_one(reg1);\n\tpop_one(reg2);\n\tpop_one(reg3);\n\tpop_one(reg4);\n\tpop_one(reg5);\n\tpop_one(reg6);\n\tpop_one(reg7);\n\tbuild pop_args;\n\tbuild pop_ret;\n}\n\n# RETX - Return from Exception\n:RETX is op=0x0003 {\n PC = *(ISP:4) << 1; # PC equals bits 0 to 22 popped from stack shifted left 1\n ISP = ISP + 4;\n PSR = *(ISP:4); # PSR popped/restored from interrupt stack\n ISP = ISP + 2;\n return [PC]; \n}\n\n\n# LOAD / STORE\n# - for loads and stores, dsp(n) is always unsigned\n\n# LOADB - Load low-order byte only\n:LOADB prp const1(prp_src1), dst1 is hi=0xbe & prp & const1 & prp_src1 & dst1 { # fmt 18\n tmp:4 = prp_src1:4 + prp:4;\n dst1 = (dst1 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB prp2 disp14(prp_src), dst3 is op10=0x219 & prp2 & disp14 & prp_src & dst3 { # fmt 17\n tmp:4 = prp_src:4 + prp2:4 + zext(disp14);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB disp20(src4), dst3 is op=0x0012 ; n8=4 & disp20 & src4 & dst3 { # fmt 2\n tmp:4 = zext(src4) + zext(disp20);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB -disp20(src4), dst3 is op=0x0018 ; n8=4 & disp20 & src4 & dst3 {\n tmp:4 = zext(src4) - zext(disp20);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB disp16b(rp_src2), dst1 is hi=0xbf & rp_src2 & dst1 ; disp16b { # fmt 19\n tmp:4 = rp_src2:4 + zext(disp16b);\n dst1 = (dst1 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB disp20(rp_src5), dst3 is op=0x0012 ; n8=5 & disp20 & rp_src5 & dst3 { # fmt 2\n tmp:4 = rp_src5:4 + zext(disp20);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB -disp20(rp_src5), dst3 is op=0x0018 ; n8=5 & disp20 & rp_src5 & dst3 { \n tmp:4 = rp_src5:4 - zext(disp20);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB disp4b(rp_src2), dst1 is op4=0xb & dst1 & disp4b & rp_src2 { # fmt 18\n tmp:4 = rp_src2:4 + zext(disp4b);\n dst1 = (dst1 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB disp20(prp_src), dst3 is op=0x0012 ; n8=6 & disp20 & prp_src & dst3 { # fmt 2 \n tmp:4 = prp_src:4 + zext(disp20);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB abs20, dst3 is dw_hi=0x88 & abs20 & dst3 { # fmt 12\n tmp:4 = zext(abs20);\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB rs abs20, dst3 is dw_op7=0x45 & dst3 & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n dst3 = (dst3 & 0xff00) + zext( *:1 tmp );\n}\n:LOADB abs24, dst3 is op=0x0012 ; n8=7 & dst3 & abs24 { # fmt 3\n dst3 = (dst3 & 0xff00) + zext( *:1 abs24 );\n}\n\n# LOADD - load doubleword\n:LOADD prp const1(prp_src1), rp_dst2 is hi=0xae & prp & const1 & prp_src1 & rp_dst2 { # fmt 18\n tmp:4 = prp_src1:4 + prp:4;\n rp_dst2 = *tmp;\n}\n:LOADD prp2 disp14(prp_src), rp_dst4 is op10=0x21a & prp2 & disp14 & prp_src & rp_dst4 { # fmt 17\n tmp:4 = prp_src:4 + prp2:4 + zext(disp14);\n rp_dst4 = *tmp;\n}\n:LOADD disp20(src4), rp_dst4 is op=0x0012 ; n8=8 & disp20 & src4 & rp_dst4 { # fmt 2 \n tmp:4 = zext(src4) + zext(disp20);\n rp_dst4 = *tmp;\n}\n:LOADD -disp20(src4), rp_dst4 is op=0x0018 ; n8=8 & disp20 & src4 & rp_dst4 {\n tmp:4 = zext(src4) - zext(disp20);\n rp_dst4 = *tmp;\n}\n:LOADD disp16b(rp_src2), rp_dst2 is hi=0xaf & rp_dst2 & rp_src2 ; disp16b { # fmt 19\n tmp:4 = rp_src2:4 + zext(disp16b);\n rp_dst2 = *tmp;\n}\n:LOADD disp20(rp_src5), rp_dst4 is op=0x0012 ; n8=9 & disp20 & rp_src5 & rp_dst4 { # fmt 2\n tmp:4 = rp_src5:4 + zext(disp20);\n rp_dst4 = *tmp;\n}\n:LOADD -disp20(rp_src5), rp_dst4 is op=0x0018 ; n8=9 & disp20 & rp_src5 & rp_dst4 {\n tmp:4 = rp_src5:4 - zext(disp20);\n rp_dst4 = *tmp;\n}\n:LOADD disp4(rp_src2), rp_dst2 is op4=0xa & disp4 & rp_src2 & rp_dst2 {\n tmp:4 = rp_src2:4 + zext(disp4);\n rp_dst2 = *tmp;\n}\n:LOADD disp20(prp_src), rp_dst4 is op=0x0012 ; n8=10 & disp20 & prp_src & rp_dst4 { # fmt 2 \n tmp:4 = prp_src:4 + zext(disp20);\n rp_dst4 = *tmp;\n}\n:LOADD abs20, rp_dst4 is dw_hi=0x87 & abs20 & rp_dst4 { \n tmp:4 = zext(abs20);\n rp_dst4 = *tmp;\n}\n:LOADD rs abs20, rp_dst4 is dw_op7=0x46 & rs & abs20 & rp_dst4 {\n tmp:4 = zext(abs20) + rs:4;\n rp_dst4 = *tmp;\n}\n:LOADD abs24, rp_dst4 is op=0x0012 ; n8=11 & rp_dst4 & abs24 { # fmt 3\n rp_dst4 = *abs24;\n}\n\nmacro load_one_1(rd) {\n\taddr:4 = zext(R0);\n\trd = *addr;\n\tR0 = R0 + 2;\n}\n\nmacro load_one_2(rd) {\n\taddr:4 = R1R0:4;\n\trd = *addr;\n\tR1R0 = R1R0 + 2;\n}\n\n# LOADM/LOADMP - Load Multiple Registers from Memory\n:LOADM cnt3b is op13=0x0014 & b0_2=0 & cnt3b { load_one_1(R2); }\n:LOADM cnt3b is op13=0x0014 & b0_2=1 & cnt3b { load_one_1(R2); load_one_1(R3); }\n:LOADM cnt3b is op13=0x0014 & b0_2=2 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); }\n:LOADM cnt3b is op13=0x0014 & b0_2=3 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); }\n:LOADM cnt3b is op13=0x0014 & b0_2=4 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); }\n:LOADM cnt3b is op13=0x0014 & b0_2=5 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); load_one_1(R9); }\n:LOADM cnt3b is op13=0x0014 & b0_2=6 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); load_one_1(R9); load_one_1(R10); }\n:LOADM cnt3b is op13=0x0014 & b0_2=7 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); load_one_1(R9); load_one_1(R10); load_one_1(R11); }\n\n:LOADMP cnt3b is op13=0x0015 & b0_2=0 & cnt3b { load_one_2(R2); load_one_2(R3); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=1 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=2 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=3 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=4 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=5 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); load_one_2(R9); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=6 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); load_one_2(R9); load_one_2(R10); }\n:LOADMP cnt3b is op13=0x0015 & b0_2=7 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); load_one_2(R9); load_one_2(R10); load_one_2(R11); }\n\n# LOADW - load word\n:LOADW prp const1(prp_src1), dst1 is hi=0x9e & prp & const1 & prp_src1 & dst1 { # fmt 18\n tmp:4 = prp_src1:4 + prp:4;\n dst1 = *tmp;\n}\n:LOADW prp2 disp14(prp_src), dst3 is op10=0x21b & prp2 & disp14 & prp_src & dst3 { # fmt 17\n tmp:4 = prp_src:4 + prp2:4 + zext(disp14);\n dst3 = *tmp;\n}\n:LOADW disp20(src4), dst3 is op=0x0012 ; n8=12 & disp20 & src4 & dst3 { # fmt 2\n tmp:4 = zext(src4) + zext(disp20);\n dst3 = *tmp;\n}\n:LOADW -disp20(src4), dst3 is op=0x0018 ; n8=12 & disp20 & src4 & dst3 {\n tmp:4 = zext(src4) - zext(disp20);\n dst3 = *tmp;\n}\n:LOADW disp16b(rp_src2), dst1 is hi=0x9f & rp_src2 & dst1 ; disp16b { # fmt 19\n tmp:4 = rp_src2:4 + zext(disp16b);\n dst1 = *tmp;\n}\n:LOADW disp20(rp_src5), dst3 is op=0x0012 ; n8=13 & disp20 & rp_src5 & dst3 { # fmt 2\n tmp:4 = rp_src5:4 + zext(disp20);\n dst3 = *tmp;\n}\n:LOADW -disp20(rp_src5), dst3 is op=0x0018 ; n8=13 & disp20 & rp_src5 & dst3 {\n tmp:4 = rp_src5:4 - zext(disp20);\n dst3 = *tmp;\n}\n:LOADW disp4(rp_src2), dst1 is op4=0x9 & disp4 & rp_src2 & dst1 { # fmt 18\n tmp:4 = rp_src2:4 + zext(disp4);\n dst1 = *tmp;\n}\n:LOADW disp20(prp_src), dst3 is op=0x0012 ; n8=14 & disp20 & prp_src & dst3 { # fmt 2\n tmp:4 = prp_src:4 + zext(disp20);\n dst3 = *tmp;\n}\n:LOADW abs20, dst3 is dw_hi=0x89 & abs20 & dst3 {\n tmp:4 = zext(abs20);\n dst3 = *tmp;\n}\n:LOADW rs abs20, dst3 is dw_op7=0x47 & dst3 & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n dst3 = *tmp;\n}\n:LOADW abs24, dst3 is op=0x0012 ; n8=15 & dst3 & abs24 { # fmt 3\n dst3 = *abs24;\n}\n\n# STORB - store low-order byte only\n:STORB src, prp const1(prp_dst1) is hi=0xfe & src & prp & const1 & prp_dst1 { # fmt 18\n tmp:4 = prp_dst1:4 + prp:4;\n *tmp = src:1;\n}\n:STORB src3, prp2 disp14(prp_dst) is op10=0x319 & src3 & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n *tmp = src3:1;\n}\n:STORB src3, disp20(dst4) is op=0x0013 ; n8=4 & src3 & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n *tmp = src3:1;\n}\n:STORB src3, -disp20(dst4) is op=0x0019 ; n8=4 & src3 & disp20 & dst4 {\n tmp:4 = zext(dst4) - zext(disp20);\n *tmp = src3:1;\n}\n:STORB src, disp16b(rp_dst) is hi=0xff & src & rp_dst ; disp16b { # fmt 19\n tmp:4 = rp_dst:4 + zext(disp16b);\n *tmp = src:1;\n}\n:STORB src3, disp20(rp_dst5) is op=0x0013 ; n8=5 & src3 & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n *tmp = src3:1;\n}\n:STORB src3, -disp20(rp_dst5) is op=0x0019 ; n8=5 & src3 & disp20 & rp_dst5 {\n tmp:4 = rp_dst5:4 - zext(disp20);\n *tmp = src3:1;\n}\n:STORB src, disp4b(rp_dst) is op4=0xf & src & disp4b & rp_dst { # fmt 18 <---\n tmp:4 = rp_dst:4 + zext(disp4b);\n *tmp = src:1;\n}\n:STORB src3, disp20(prp_dst) is op=0x0013 ; n8=6 & src3 & disp20 & prp_dst { # fmt 2\n tmp:4 = prp_dst:4 + zext(disp20);\n *tmp = src3:1;\n}\n:STORB src3, abs20 is dw_hi=0xc8 & abs20 & src3 {\n tmp:4 = zext(abs20);\n *tmp = src3:1;\n}\n:STORB src3, rs abs20 is dw_op7=0x65 & src3 & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n *tmp = src3:1;\n}\n:STORB src3, abs24 is op=0x0013 ; n8=7 & src3 & abs24 { # fmt 3\n *abs24 = src3:1;\n}\n\n:STORB imm4c, prp2 disp14(prp_dst) is op10=0x218 & imm4c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n *tmp = imm4c;\n}\n:STORB imm4c, disp20(dst4) is op=0x0012 ; n8=0 & imm4c & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n *tmp = imm4c;\n}\n:STORB imm4a, const1(rp_dst) is hi=0x82 & imm4a & const1 & rp_dst { # fmt 15\n *rp_dst:4 = imm4a;\n}\n:STORB imm4a, disp16b(rp_dst) is hi=0x83 & imm4a & rp_dst ; disp16b { # fmt 16\n tmp:4 = rp_dst:4 + zext(disp16b);\n *tmp = imm4a;\n}\n:STORB imm4c, disp20(rp_dst5) is op=0x0012 ; n8=1 & imm4c & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n *tmp = imm4c;\n}\n:STORB imm4c, disp20(prp_dst) is op=0x0012 ; n8=2 & imm4c & disp20 & prp_dst {\n tmp:4 = prp_dst:4 + zext(disp20);\n *tmp = imm4c;\n}\n:STORB imm4b, abs20 is dw_hi=0x81 & imm4b & abs20 { # fmt 12\n tmp:4 = zext(abs20);\n *tmp = imm4b;\n}\n:STORB imm4b, rs abs20 is dw_op7=0x42 & imm4b & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n *tmp = imm4b;\n}\n:STORB imm4b, abs24 is op=0x0012 ; n8=3 & imm4b & abs24 { # fmt 3\n *abs24 = imm4b;\n}\n\n# STORD - store doubleword\n:STORD rp_src, prp const1(prp_dst1) is hi=0xee & rp_src & prp & const1 & prp_dst1 { # fmt 18\n tmp:4 = prp_dst1:4 + prp:4;\n *tmp = rp_src;\n}\n:STORD rp_src4, prp2 disp14(prp_dst) is op10=0x31a & rp_src4 & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n *tmp = rp_src4;\n}\n:STORD rp_src4, disp20(dst4) is op=0x0013 ; n8=8 & rp_src4 & dst4 & disp20 { # fmt 2 \n tmp:4 = zext(dst4) + zext(disp20);\n *tmp = rp_src4;\n}\n:STORD rp_src4, -disp20(dst4) is op=0x0019 ; n8=8 & rp_src4 & dst4 & disp20 {\n tmp:4 = zext(dst4) - zext(disp20);\n *tmp = rp_src4;\n}\n:STORD rp_src, disp16b(rp_dst) is hi=0xef & rp_src & rp_dst ; disp16b { # fmt 19\n tmp:4 = rp_dst:4 + zext(disp16b);\n *tmp = rp_src;\n}\n:STORD rp_src4, disp20(rp_dst5) is op=0x0013 ; n8=9 & rp_src4 & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n *tmp = rp_src4;\n}\n:STORD rp_src4, -disp20(rp_dst5) is op=0x0019 ; n8=9 & rp_src4 & disp20 & rp_dst5 {\n tmp:4 = rp_dst5:4 - zext(disp20);\n *tmp = rp_src4;\n}\n:STORD rp_src, disp4(rp_dst) is op4=0xe & disp4 & rp_src & rp_dst { # fmt 18\n tmp:4 = rp_dst:4 + zext(disp4);\n *tmp = rp_src;\n}\n:STORD rp_src4, disp20(prp_dst) is op=0x0013 ; n8=10 & rp_src4 & disp20 & prp_dst { # fmt 2\n tmp:4 = prp_dst:4 + zext(disp20);\n *tmp = rp_src4;\n}\n:STORD rp_src4, abs20 is dw_hi=0xc7 & abs20 & rp_src4 {\n tmp:4 = zext(abs20);\n *tmp = rp_src4;\n}\n:STORD rp_src4, rs abs20 is dw_op7=0x66 & rp_src4 & rs & abs20 {\n tmp:4 = zext(abs20) + rs:4;\n *tmp = rp_src4;\n}\n:STORD rp_src4, abs24 is op=0x0013 ; n8=11 & rp_src4 & abs24 { # fmt 3\n *abs24 = rp_src4;\n}\n\nmacro store_one_1(rd) {\n\taddr:4 = zext(R1);\n\t*addr = rd;\n\tR1 = R1 + 2;\n}\n\nmacro store_one_2(rd) {\n\taddr:4 = R7R6:4;\n\t*addr = rd;\n\tR7R6 = R7R6 + 2;\n}\n\n# STORM/STORMP - Store Multiple Registers to Memory\n:STORM cnt3b is op13=0x0016 & b0_2=0 & cnt3b { store_one_1(R2); }\n:STORM cnt3b is op13=0x0016 & b0_2=1 & cnt3b { store_one_1(R2); store_one_1(R3); }\n:STORM cnt3b is op13=0x0016 & b0_2=2 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); }\n:STORM cnt3b is op13=0x0016 & b0_2=3 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); }\n:STORM cnt3b is op13=0x0016 & b0_2=4 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); }\n:STORM cnt3b is op13=0x0016 & b0_2=5 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); store_one_1(R9); }\n:STORM cnt3b is op13=0x0016 & b0_2=6 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); store_one_1(R9); store_one_1(R10); }\n:STORM cnt3b is op13=0x0016 & b0_2=7 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); store_one_1(R9); store_one_1(R10); store_one_1(R11); }\n\n:STORMP cnt3b is op13=0x0017 & b0_2=0 & cnt3b { store_one_2(R2); }\n:STORMP cnt3b is op13=0x0017 & b0_2=1 & cnt3b { store_one_2(R2); store_one_2(R3); }\n:STORMP cnt3b is op13=0x0017 & b0_2=2 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); }\n:STORMP cnt3b is op13=0x0017 & b0_2=3 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); }\n:STORMP cnt3b is op13=0x0017 & b0_2=4 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); }\n:STORMP cnt3b is op13=0x0017 & b0_2=5 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); store_one_2(R9); }\n:STORMP cnt3b is op13=0x0017 & b0_2=6 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); store_one_2(R9); store_one_2(R10); }\n:STORMP cnt3b is op13=0x0017 & b0_2=7 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); store_one_2(R9); store_one_2(R10); store_one_2(R11); }\n\n# STORW - store word\n:STORW src, prp const1(prp_dst1) is hi=0xde & src & prp & const1 & prp_dst1 { # fmt 18\n tmp:4 = prp_dst1:4 + prp:4;\n *tmp = src;\n}\n:STORW src3, prp2 disp14(prp_dst) is op10=0x31b & prp2 & disp14 & src3 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n *tmp = src3;\n}\n:STORW src3, disp20(dst4) is op=0x0013 ; n8=12 & src3 & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n *tmp = src3;\n}\n:STORW src3, -disp20(dst4) is op=0x0019 ; n8=12 & src3 & disp20 & dst4 {\n tmp:4 = zext(dst4) - zext(disp20);\n *tmp = src3;\n}\n:STORW src, disp16b(rp_dst) is hi=0xdf & src & rp_dst ; disp16b {\n tmp:4 = rp_dst:4 + zext(disp16b);\n *tmp = src;\n}\n:STORW src3, disp20(rp_dst5) is op=0x0013 ; n8=13 & src3 & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n *tmp = src3;\n}\n:STORW src3, -disp20(rp_dst5) is op=0x0019 ; n8=13 & src3 & disp20 & rp_dst5 {\n tmp:4 = rp_dst5:4 - zext(disp20);\n *tmp = src3;\n}\n:STORW src, disp4(rp_dst) is op4=0xd & disp4 & src & rp_dst { # fmt 18\n tmp:4 = rp_dst:4 + zext(disp4);\n *tmp = src;\n}\n:STORW src3, disp20(prp_dst) is op=0x0013 ; n8=14 & src3 & disp20 & prp_dst { # fmt 2\n tmp:4 = prp_dst:4 + zext(disp20);\n *tmp = src3;\n}\n:STORW src3, abs20 is dw_hi=0xc9 & abs20 & src3 {\n tmp:4 = zext(abs20);\n *tmp = src3;\n}\n:STORW src3, rs abs20 is dw_op7=0x67 & src3 & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n *tmp = src3;\n}\n:STORW src3, abs24 is op=0x0013 ; n8=15 & src3 & abs24 { # fmt 3\n *abs24 = src3;\n}\n\n:STORW imm4c, prp2 disp14(prp_dst) is op10=0x318 & imm4c & prp2 & disp14 & prp_dst { # fmt 17\n tmp:4 = prp_dst:4 + prp2:4 + zext(disp14);\n *:2 tmp = sext(imm4c);\n}\n:STORW imm4c, disp20(dst4) is op=0x0013 ; n8=0 & imm4c & disp20 & dst4 { # fmt 2\n tmp:4 = zext(dst4) + zext(disp20);\n *:2 tmp = sext(imm4c);\n}\n:STORW imm4a, const1(rp_dst) is hi=0xc2 & imm4a & const1 & rp_dst { # fmt 15\n *:2 rp_dst:4 = sext(imm4a);\n}\n:STORW imm4a, disp16b(rp_dst) is hi=0xc3 & imm4a & rp_dst ; disp16b { # fmt 16\n tmp:4 = rp_dst:4 + zext(disp16b);\n *:2 tmp = sext(imm4a);\n}\n:STORW imm4c, disp20(rp_dst5) is op=0x0013 ; n8=1 & imm4c & disp20 & rp_dst5 { # fmt 2\n tmp:4 = rp_dst5:4 + zext(disp20);\n *:2 tmp = sext(imm4c);\n}\n:STORW imm4c, disp20(prp_dst) is op=0x0013 ; n8=2 & imm4c & disp20 & prp_dst {\n tmp:4 = prp_dst:4 + zext(disp20);\n *:2 tmp = sext(imm4c);\n}\n:STORW imm4b, abs20 is dw_hi=0xc1 & imm4b & abs20 {\n tmp:4 = zext(abs20);\n *:2 tmp = sext(imm4b);\n}\n:STORW imm4b, rs abs20 is dw_op7=0x62 & imm4b & rs & abs20 { # fmt 13\n tmp:4 = zext(abs20) + rs:4;\n *:2 tmp = sext(imm4b);\n}\n:STORW imm4b, abs24 is op=0x0013 ; n8=3 & imm4b & abs24 { # fmt 3\n *:2 abs24 = sext(imm4b);\n}\n\n\n# MISC\n\n# CINV - Cache Invalidate\n:CINV cinv1 is op=0x000a & cinv1 {\n}\n:CINV cinv2 is op=0x000b & cinv2 {\n}\n:CINV cinv3 is op=0x000c & cinv3 {\n}\n:CINV cinv4 is op=0x000d & cinv4 {\n}\n:CINV cinv5 is op=0x000e & cinv5 {\n}\n:CINV cinv6 is op=0x000f & cinv6 {\n}\n\n# Disable Maskable Interrupts\n:DI is op=0x0004 {\n $(E) = 0;\n}\n# Enable Maskable Interrupts\n:EI is op=0x0005 {\n $(E) = 1;\n}\n# Wait for Interrupt\n:WAIT is op=0x0006 {\n suspend();\n}\n# Enable Interrupt and Wait for Interrupt\n:EIWAIT is op=0x0007 {\n $(E) = 1;\n suspend();\n}\n\n\n# Reserved\n\n:undef is op=0x0000 {\n}\n:undef is op=0x0001 {\n}\n\n:undef is op=0x0002 {\n}\n\n:undef is op=0x0008 {\n}\n:undef is op=0x0009 {\n}\n\n:undef is op=0x0010 ; w2 ; w3 {\n}\n:undef is op=0x0011 ; w2 ; w3 {\n}\n:undef is op=0x0014 ; w2 {\n}\n:undef is op=0x0015 ; w2 {\n}\n:undef is op=0x0016 ; w2 {\n}\n:undef is op=0x0017 ; w2 {\n}\n\n:undef is op=0x0018 ; w2 ; w3 {\n}\n:undef is op=0x0019 ; w2 ; w3 {\n}\n\n:undef is op=0x001a ; w2 ; w3 {\n}\n:undef is op=0x001b ; w2 ; w3 {\n}\n:undef is op=0x001c ; w2 ; w3 {\n}\n:undef is op=0x001d ; w2 ; w3 {\n}\n:undef is op=0x001e ; w2 ; w3 {\n}\n:undef is op=0x001f ; w2 ; w3 {\n}\n\n:undef is op12=0x008 ; w2 ; w3 {\n}\n\n:undef is op11=0x007 {\n}\n\n:undef is op9=0x012 ; w2 {\n}\n\n:undef is hi=0x80 {\n}\n\n#:undef is hi=0xc0 {\n#}\n\n:undef is op=0xffff {\n}\n\n" }, { "path": "pypcode/processors/CR16/data/languages/CR16C.slaspec", "content": "\ndefine endian=little;\n\n@include \"CR16C.sinc\"\n" }, { "path": "pypcode/processors/CR16/data/manuals/CR16.idx", "content": "@prog16c.pdf [ Texas Instruments (formerly National Semiconductor), CompactRISC, CR16C Programmer’s Reference Manual. Part Number: 424521772-101. ]\nADDB, 74\nADDW, 74\nADDD, 74\nADDUB, 74\nADDUW, 74\nADDCB, 75\nADDCW, 75\nANDB, 76\nANDW, 76\nANDD, 76\nASHUB, 77\nASHUW, 77\nASHUD, 77\nBAL, 79\nBEQ, 80\nBNE, 80\nBCS, 80\nBCC, 80\nBHI, 80\nBLS, 80\nBGT, 80\nBLE, 80\nBFS, 80\nBFC, 80\nBLO, 80\nBHS, 80\nBLT, 80\nBGE, 80\nBEQ0B, 83\nBEQ0W, 83\nBNE0B, 83\nBNE0W, 83\nBR, 84\nCBITB, 85\nCBITW, 85\nCINV, 87\nCMPB, 88\nCMPW, 88\nCMPD, 88\nDI, 89\nEI, 90\nEIWAIT, 91\nEXCP, 92\nJEQ, 93\nJNE, 93\nJCS, 93\nJCC, 93\nJHI, 93\nJLS, 93\nJGT, 93\nJLE, 93\nJFS, 93\nJFC, 93\nJLO, 93\nJHS, 93\nJLT, 93\nJGE, 93\nJAL, 95\nJUMP, 96\nJUSR, 96\nLOADB, 97\nLOADW, 97\nLOADD, 97\nLOADM, 100\nLOADMP, 100\nLPR, 101\nLPRD, 101\nLSHB, 103\nLSHW, 103\nLSHD, 103\nMACSW, 105\nMACUW, 106\nMACQW, 107\nMOVB, 108\nMOVW, 108\nMOVD, 108\nMOVXB, 109\nMOVXW, 109\nMOVZB, 110\nMOVZW, 110\nMULB, 111\nMULW, 111\nMULSB, 112\nMULSW, 113\nMULUW, 114\nNOP, 115\nORB, 116\nORW, 116\nORD, 116\nPOP, 117\nPOPrt, 117\nPUSH, 120\nRETX, 122\nSBITB, 123\nSBITW, 123\nSNE, 125\nSCS, 125\nSCC, 125\nSHI, 125\nSLS, 125\nSGT, 125\nSEQ SLE, 125\nSFS, 125\nSFC, 125\nSLO, 125\nSHS, 125\nSLT, 125\nSGE, 125\nSPR, 127\nSPRD, 127\nSTORB, 129\nSTORW, 129\nSTORD, 129\nSTORM, 132\nSTORMP, 132\nSUBB, 134\nSUBW, 134\nSUBD, 134\nSUBCB, 135\nSUBCW, 135\nTBIT, 136\nTBITB, 136\nTBITW, 136\nWAIT, 138\nXORB, 139\nXORW, 139\nXORD, 139\n" }, { "path": "pypcode/processors/DATA/data/languages/data-be-64.slaspec", "content": "@define ENDIAN \"big\"\n\n@define RAMSIZE \"8\"\n\n@include \"data.sinc\"\n" }, { "path": "pypcode/processors/DATA/data/languages/data-le-64.slaspec", "content": "@define ENDIAN \"little\"\n\n@define RAMSIZE \"8\"\n\n@include \"data.sinc\"\n" }, { "path": "pypcode/processors/DATA/data/languages/data-ptr16.cspec", "content": "\n\n\n\n\t\n\t \n \n\n\t\n\t\t\n\t\t\n\t\n\n\t\n\n\t\n \t\t\n \t\t\t\n \t\t\t\t\n \t\t\t\t\t\n \t\t\t\t\n \t\t\t\n\t \t\t\n\t\t \n\t\t \n\t\t \n\t \t\t\n\t\t\n\t\n\n\n" }, { "path": "pypcode/processors/DATA/data/languages/data-ptr32.cspec", "content": "\n\n\n\n\t\n\t \n \n\n\t\n\t\t\n\t\t\n\t\n\n\t\n\n\t\n \t\t\n \t\t\t\n \t\t\t\t\n \t\t\t\t\t\n \t\t\t\t\n \t\t\t\n\t \t\t\n\t\t \n\t\t \n\t\t \n\t \t\t\n\t\t\n\t\n\n\n" }, { "path": "pypcode/processors/DATA/data/languages/data-ptr64.cspec", "content": "\n\n\n\n\t\n\t \n \n\n\t\n\t\t\n\t\t\n\t\n\n\t\n\n\t\n \t\t\n \t\t\t\n \t\t\t\t\n \t\t\t\t\t\n \t\t\t\t\n \t\t\t\n\t \t\t\n\t\t \n\t\t \n\t\t \n\t \t\t\n\t\t\n\t\n\n\n" }, { "path": "pypcode/processors/DATA/data/languages/data.ldefs", "content": "\n\n\n \n \n\t\tRaw Data File (Little Endian)\n\t\t\n\t\t\n\t\t\n\t\n\t\n\t\n\t\tRaw Data File (Big Endian)\n\t\t\n\t\t\n\t\t\n\t\n\t\n\n" }, { "path": "pypcode/processors/DATA/data/languages/data.pspec", "content": "\n\n\n\n\n" }, { "path": "pypcode/processors/DATA/data/languages/data.sinc", "content": "define endian = $(ENDIAN);\n\ndefine alignment = 1;\n\ndefine space ram type=ram_space size=8 default;\n\ndefine space register type=register_space size=4;\n\n# # # # # # # # # # # # # # # # # # # # # # # # # # # #\n# AT LEAST ONE REGISTER, AND STACK POINTER ARE REQUIRED\n# # # # # # # # # # # # # # # # # # # # # # # # # # # #\n\ndefine register offset=0x0 size=8 [ sp r0 ];\n\n# Define context bits\ndefine register offset=0x100 size=4 contextreg;\n\ndefine context contextreg\n test=(0,0) \n;\n\n# # # # # # # # # # # # # # # # # # # # # # # # # # # #\n# AT LEAST ONE INSTRUCTION IS REQUIRED\n# # # # # # # # # # # # # # # # # # # # # # # # # # # #\n\n:nop is test=1 unimpl\n\n# # # # # # # # # # # # # # # # # # # # # # # # # # # #\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik.ldefs", "content": "\n\n\n\n \n \n Dalvik Base\n \n \n\n \n Dalvik Base\n \n \n\n \n Dalvik DEX KitKat\n \n \n\n \n Dalvik ODEX KitKat\n \n \n\n \n Dalvik DEX Lollipop\n \n \n \n \n Dalvik DEX Marshmallow\n \n \n\n \n Dalvik DEX Nougat\n \n \n\n \n Dalvik DEX Oreo\n \n \n\n\n Dalvik DEX Pie\n \n \n\n \n Dalvik DEX Android10\n \n \n\n \n Dalvik DEX Android11\n \n \n\n \n Dalvik DEX Android12\n \n \n\n \n \n Dalvik DEX Android13\n \n \n\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik.opinion", "content": "\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_Base.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t\t\n\t\n\n\t\n\n\t\n \t\t\n \t\t\t\n \n \n \n \t\t\t\n\t \t\t\n\t\t \n\t\t \n\t\t \n\t \t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\n \n\t\t\n\t\n\n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_Base.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_Base.sinc", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/[...]/runtime/dex_instruction_list.h\n#\t\twhere [...] is the actual Android version name (ie \"oreo-release\")\n\ndefine endian=little;\n\ndefine alignment=1;\n\n@define CPOOL_METHOD \"0:4\"\n@define CPOOL_FIELD \"1:4\"\n@define CPOOL_STATIC_FIELD \"2:4\"\n@define CPOOL_STATIC_METHOD \"3:4\"\n@define CPOOL_STRING \"4:4\"\n@define CPOOL_CLASSREF \"5:4\"\n@define CPOOL_ARRAYLENGTH \"6:4\"\n@define CPOOL_SUPER \"7:4\"\n@define CPOOL_INSTANCEOF \"8:4\"\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\ndefine space ram\t\ttype=ram_space size=4 default;\n\n#define space object\ttype=ram_space size=4; # object instances\n\n#define space method\ttype=ram_space size=4; # method references\n\n#define space field\t\ttype=ram_space size=4; # field references\n\ndefine space register\ttype=register_space size=4;\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\ndefine register offset=0x0 size=4 [ sp fp resultreg ];\ndefine register offset=0x8 size=8 [ resultregw ];\n\ndefine register offset=0x100 size=4 # Special input registers\n[\n\tiv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7\n\tiv8 iv9 iv10 iv11 iv12 iv13 iv14 iv15\n];\n\ndefine register offset=0x104 size=8\t\t\t\t# Wide input registers ODD\n[\n ivw1 ivw3 ivw5 ivw7 ivw9 ivw11 ivw13\n];\n\ndefine register offset=0x100 size=8 # Wide input registers EVEN\n[\n ivw0 ivw2 ivw4 ivw6 ivw8 ivw10 ivw12 ivw14\n];\n\ndefine register offset=0x1000 size=4\n[\n\t v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 \n\t v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 \n\t v32 v33 v34 v35 v36 v37 v38 v39 v40 v41 v42 v43 v44 v45 v46 v47 \n\t v48 v49 v50 v51 v52 v53 v54 v55 v56 v57 v58 v59 v60 v61 v62 v63 \n\t v64 v65 v66 v67 v68 v69 v70 v71 v72 v73 v74 v75 v76 v77 v78 v79 \n\t v80 v81 v82 v83 v84 v85 v86 v87 v88 v89 v90 v91 v92 v93 v94 v95 \n\t v96 v97 v98 v99 v100 v101 v102 v103 v104 v105 v106 v107 v108 v109 v110 v111 \n\tv112 v113 v114 v115 v116 v117 v118 v119 v120 v121 v122 v123 v124 v125 v126 v127 \n\tv128 v129 v130 v131 v132 v133 v134 v135 v136 v137 v138 v139 v140 v141 v142 v143 \n\tv144 v145 v146 v147 v148 v149 v150 v151 v152 v153 v154 v155 v156 v157 v158 v159 \n\tv160 v161 v162 v163 v164 v165 v166 v167 v168 v169 v170 v171 v172 v173 v174 v175 \n\tv176 v177 v178 v179 v180 v181 v182 v183 v184 v185 v186 v187 v188 v189 v190 v191 \n\tv192 v193 v194 v195 v196 v197 v198 v199 v200 v201 v202 v203 v204 v205 v206 v207 \n\tv208 v209 v210 v211 v212 v213 v214 v215 v216 v217 v218 v219 v220 v221 v222 v223 \n\tv224 v225 v226 v227 v228 v229 v230 v231 v232 v233 v234 v235 v236 v237 v238 v239 \n\tv240 v241 v242 v243 v244 v245 v246 v247 v248 v249 v250 v251 v252 v253 v254 v255 \n];\n\ndefine register offset=0x1004 size=8 # ODD NUMBER WIDE REGISTERS\n[\n\t vw1 vw3 vw5 vw7 vw9 vw11 vw13 vw15 \n\t vw17 vw19 vw21 vw23 vw25 vw27 vw29 vw31 \n\t vw33 vw35 vw37 vw39 vw41 vw43 vw45 vw47 \n\t vw49 vw51 vw53 vw55 vw57 vw59 vw61 vw63 \n\t vw65 vw67 vw69 vw71 vw73 vw75 vw77 vw79 \n\t vw81 vw83 vw85 vw87 vw89 vw91 vw93 vw95 \n\t vw97 vw99 vw101 vw103 vw105 vw107 vw109 vw111 \n\t vw113 vw115 vw117 vw119 vw121 vw123 vw125 vw127 \n\t vw129 vw131 vw133 vw135 vw137 vw139 vw141 vw143 \n\t vw145 vw147 vw149 vw151 vw153 vw155 vw157 vw159 \n\t vw161 vw163 vw165 vw167 vw169 vw171 vw173 vw175 \n\t vw177 vw179 vw181 vw183 vw185 vw187 vw189 vw191 \n\t vw193 vw195 vw197 vw199 vw201 vw203 vw205 vw207 \n\t vw209 vw211 vw213 vw215 vw217 vw219 vw221 vw223 \n\t vw225 vw227 vw229 vw231 vw233 vw235 vw237 vw239 \n\t vw241 vw243 vw245 vw247 vw249 vw251 vw253\n];\n\ndefine register offset=0x1000 size=8 # EVEN NUMBER WIDE REGISTERS\n[\n\t vw0 vw2 vw4 vw6 vw8 vw10 vw12 vw14 \n\t vw16 vw18 vw20 vw22 vw24 vw26 vw28 vw30 \n\t vw32 vw34 vw36 vw38 vw40 vw42 vw44 vw46 \n\t vw48 vw50 vw52 vw54 vw56 vw58 vw60 vw62 \n\t vw64 vw66 vw68 vw70 vw72 vw74 vw76 vw78 \n\t vw80 vw82 vw84 vw86 vw88 vw90 vw92 vw94 \n\t vw96 vw98 vw100 vw102 vw104 vw106 vw108 vw110 \n\tvw112 vw114 vw116 vw118 vw120 vw122 vw124 vw126 \n\tvw128 vw130 vw132 vw134 vw136 vw138 vw140 vw142 \n\tvw144 vw146 vw148 vw150 vw152 vw154 vw156 vw158 \n\tvw160 vw162 vw164 vw166 vw168 vw170 vw172 vw174 \n\tvw176 vw178 vw180 vw182 vw184 vw186 vw188 vw190 \n\tvw192 vw194 vw196 vw198 vw200 vw202 vw204 vw206 \n\tvw208 vw210 vw212 vw214 vw216 vw218 vw220 vw222 \n\tvw224 vw226 vw228 vw230 vw232 vw234 vw236 vw238 \n\tvw240 vw242 vw244 vw246 vw248 vw250 vw252 vw254 \n];\n\n# TODO:\n# 1) test accessing register space past v255. e.g. v12345.\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\ndefine token instruction_byte ( 8 )\n inst0 = ( 0, 7 )\n;\n\ndefine token instruction_byte_w_padding ( 16 )\n inst1 = ( 0, 7 )\n inst1_padding = ( 0, 15 )\n;\n\ndefine token instruction_operands_4_4 ( 8 )\n\tA_BITS_0_3\t\t= (0,3)\n\tB_BITS_0_3\t\t= (0,3)\n\tA_BITS_4_7\t\t= (4,7)\n\tB_BITS_4_7\t\t= (4,7)\n\tB_BITS_4_7_S\t= (4,7) signed \n;\n\ndefine token instruction_operands_8 ( 8 )\n\tA_BITS_0_7\t\t= (0,7)\n\tA_BITS_0_7_S\t= (0,7) signed\n\tB_BITS_0_7\t\t= (0,7)\n\tB_BITS_0_7_S\t= (0,7) signed\n\tC_BITS_0_7\t\t= (0,7)\n\tC_BITS_0_7_S\t= (0,7) signed\n;\n\ndefine token instruction_operands_16 ( 16 )\n\tA_BITS_0_15\t\t= (0,15)\n\tA_BITS_0_15_S\t= (0,15) signed\n\tB_BITS_0_15\t\t= (0,15)\n\tB_BITS_0_15_S\t= (0,15) signed\n\tC_BITS_0_15\t\t= (0,15)\n\tC_BITS_0_15_S\t= (0,15) signed\n;\n\ndefine token instruction_operands_32 ( 32 )\n\tA_BITS_0_31\t\t= (0,31)\n\tA_BITS_0_31_S\t= (0,31) signed\n\tB_BITS_0_31\t\t= (0,31)\n\tB_BITS_0_31_S\t= (0,31) signed\n\tC_BITS_0_31\t\t= (0,31)\n\tC_BITS_0_31_S\t= (0,31) signed\n;\n\ndefine token invoke_operands ( 40 )\n\tN_PARAMS = ( 4, 7)\n\tPARAM_G = ( 0, 3)\n\tMETHOD_INDEX = ( 8,23)\n\tVTABLE_OFFSET = ( 8,23)\n\tINLINE = ( 8,23)\n\tPARAM_D = (28,31)\n\tPARAM_C = (24,27)\n\tPARAM_F = (36,39)\n\tPARAM_E = (32,35)\n;\n\ndefine token array_operands ( 40 )\n\tN_ELEMENTS = ( 4, 7)\n\tELEMENT_G = ( 0, 3)\n\tTYPE_INDEX = ( 8,23)\n\tELEMENT_D = (28,31)\n\tELEMENT_C = (24,27)\n\tELEMENT_F = (36,39)\n\tELEMENT_E = (32,35)\n;\n\ndefine token CONST16 ( 16 ) # one 16 constant\n\tconstant16\t = ( 0,15 )\n\tconstant16s\t = ( 0,15 ) signed\n;\n\ndefine token CONST32 ( 32 ) # one 32 constant\n\tconstant32 = ( 0,31 )\n\tconstant32s = ( 0,31 ) signed\n;\n\ndefine token CONST64 ( 64 ) # one 64 constant\n\tconstant64 = ( 0,63 )\n;\n\n# add \"8\" to skip over \"fp\" and \"sp\" !!\n\nregisterA4: reg is A_BITS_0_3 [ reg = (A_BITS_0_3 * 4) + 0x1000; ] { export *[register]:4 reg; }\nregisterA8: reg is A_BITS_0_7 [ reg = (A_BITS_0_7 * 4) + 0x1000; ] { export *[register]:4 reg; }\nregisterA16: reg is A_BITS_0_15 [ reg = (A_BITS_0_15 * 4) + 0x1000; ] { export *[register]:4 reg; }\n\nregisterA4w: reg is A_BITS_0_3 [ reg = (A_BITS_0_3 * 4) + 0x1000; ] { export *[register]:8 reg; }\nregisterA8w: reg is A_BITS_0_7 [ reg = (A_BITS_0_7 * 4) + 0x1000; ] { export *[register]:8 reg; }\nregisterA16w: reg is A_BITS_0_15 [ reg = (A_BITS_0_15 * 4) + 0x1000; ] { export *[register]:8 reg; }\n\nregisterB4: reg is B_BITS_4_7 [ reg = (B_BITS_4_7 * 4) + 0x1000; ] { export *[register]:4 reg; }\nregisterB8: reg is B_BITS_0_7 [ reg = (B_BITS_0_7 * 4) + 0x1000; ] { export *[register]:4 reg; }\nregisterB16: reg is B_BITS_0_15 [ reg = (B_BITS_0_15 * 4) + 0x1000; ] { export *[register]:4 reg; }\n\nregisterB4w: reg is B_BITS_4_7 [ reg = (B_BITS_4_7 * 4) + 0x1000; ] { export *[register]:8 reg; }\nregisterB8w: reg is B_BITS_0_7 [ reg = (B_BITS_0_7 * 4) + 0x1000; ] { export *[register]:8 reg; }\nregisterB16w: reg is B_BITS_0_15 [ reg = (B_BITS_0_15 * 4) + 0x1000; ] { export *[register]:8 reg; }\n\nregisterC8: reg is C_BITS_0_7 [ reg = (C_BITS_0_7 * 4) + 0x1000; ] { export *[register]:4 reg; }\nregisterC16: reg is C_BITS_0_15 [ reg = (C_BITS_0_15 * 4) + 0x1000; ] { export *[register]:4 reg; }\nregisterC32: reg is C_BITS_0_31 [ reg = (C_BITS_0_31 * 4) + 0x1000; ] { export *[register]:4 reg; }\n\n\nregisterC8w: reg is C_BITS_0_7 [ reg = (C_BITS_0_7 * 4) + 0x1000; ] { export *[register]:8 reg; }\nregisterC16w: reg is C_BITS_0_15 [ reg = (C_BITS_0_15 * 4) + 0x1000; ] { export *[register]:8 reg; }\nregisterC32w: reg is C_BITS_0_31 [ reg = (C_BITS_0_31 * 4) + 0x1000; ] { export *[register]:8 reg; }\n\nregParamC: reg is PARAM_C [ reg = (PARAM_C * 4) + 0x1000; ] { export *[register]:4 reg; }\nregParamD: reg is PARAM_D [ reg = (PARAM_D * 4) + 0x1000; ] { export *[register]:4 reg; }\nregParamE: reg is PARAM_E [ reg = (PARAM_E * 4) + 0x1000; ] { export *[register]:4 reg; }\nregParamF: reg is PARAM_F [ reg = (PARAM_F * 4) + 0x1000; ] { export *[register]:4 reg; }\nregParamG: reg is PARAM_G [ reg = (PARAM_G * 4) + 0x1000; ] { export *[register]:4 reg; }\n\nregElemC: reg is ELEMENT_C [ reg = (ELEMENT_C * 4) + 0x1000; ] { export *[register]:4 reg; }\nregElemD: reg is ELEMENT_D [ reg = (ELEMENT_D * 4) + 0x1000; ] { export *[register]:4 reg; }\nregElemE: reg is ELEMENT_E [ reg = (ELEMENT_E * 4) + 0x1000; ] { export *[register]:4 reg; }\nregElemF: reg is ELEMENT_F [ reg = (ELEMENT_F * 4) + 0x1000; ] { export *[register]:4 reg; }\nregElemG: reg is ELEMENT_G [ reg = (ELEMENT_G * 4) + 0x1000; ] { export *[register]:4 reg; }\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\nrel16: reloc is A_BITS_0_15_S [ reloc = inst_start + ( A_BITS_0_15_S * 2 ); ] { export *[ram]:32 reloc; }\n\ngoto8: reloc is A_BITS_0_7_S [ reloc = inst_start + ( A_BITS_0_7_S * 2 ); ] { export *[ram]:8 reloc; }\ngoto16: reloc is A_BITS_0_15_S [ reloc = inst_start + ( A_BITS_0_15_S * 2 ); ] { export *[ram]:16 reloc; }\ngoto32: reloc is A_BITS_0_31_S [ reloc = inst_start + ( A_BITS_0_31_S ); ] { export *[ram]:32 reloc; }\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Special op which injects correct p-code for invoke*_range instructions\n# It takes two arguments: 1) is the number of parameters for the method 2) is the starting register\ndefine pcodeop moveRangeToIV;\n\ndefine pcodeop monitorEnter;\ndefine pcodeop monitorExit;\n\ndefine pcodeop checkCast;\n\ndefine pcodeop throwException;\n\ndefine pcodeop getStaticFieldVolatile;\ndefine pcodeop setStaticFieldVolatile;\n\ndefine pcodeop getInstanceFieldQuick;\ndefine pcodeop getInstanceFieldVolatile;\ndefine pcodeop setInstanceFieldQuick;\ndefine pcodeop setInstanceFieldVolatile;\n\ndefine pcodeop filledNewArray;\ndefine pcodeop filledNewArrayRange;\n\ndefine pcodeop invokeSuperQuick;\ndefine pcodeop invokeSuperQuickRange;\ndefine pcodeop invokeVirtualQuick;\ndefine pcodeop invokeVirtualQuickRange;\n\ndefine pcodeop switchAssist;\n\ndefine pcodeop breakpoint;\n\n#SOURCE: https://android.googlesource.com/platform/art/+/kitkat-dev/runtime/dex_instruction_list.h\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Waste cycles. \n\n:nop is inst0=0x00\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Move the contents of one non-object register to another.\n# \n# A: destination register (4 bits)\n# B: source register (4 bits)\n\n:move registerA4,registerB4 is inst0=0x01 ; registerA4 & registerB4\n{\n\tregisterA4 = registerB4;\n}\n\n# Move the contents of one non-object register to another.\n# \n# A: destination register (8 bits)\n# B: source register (16 bits)\n\n:move_from_16 registerA8,registerB16 is inst0=0x02 ; registerA8 ; registerB16\n{\n\tregisterA8 = registerB16;\n}\n\n# Move the contents of one non-object register to another.\n# \n# A: destination register (16 bits)\n# B: source register (16 bits)\n\n:move_16 registerA16,registerB16 is inst1=0x03 & inst1_padding ; registerA16 ; registerB16\n{\n\tregisterA16 = registerB16;\n}\n\n# Move the contents of one register-pair to another. \n# \n# A: destination register pair (4 bits)\n# B: source register pair (4 bits)\n\n:move_wide registerA4w,registerB4w is inst0=0x04 ; registerA4w & registerB4w\n{\n\tregisterA4w = registerB4w;\n}\n\n# Move the contents of one register-pair to another. \n# \n# A: destination register pair (8 bits)\n# B: source register pair (16 bits)\n\n:move_wide_from_16 registerA8w,registerB16w is inst0=0x05 ; registerA8w ; registerB16w\n{\n\tregisterA8w = registerB16w;\n}\n\n# Move the contents of one register-pair to another. \n# \n# A: destination register pair (16 bits)\n# B: source register pair (16 bits)\n\n:move_wide_16 registerA16w,registerB16w is inst0=0x06 ; registerA16w ; registerB16w\n{\n\tregisterA16w = registerB16w;\n}\n\n# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #\n# \n# Move the contents of one object-bearing register to another.\n# \n# A: destination register (4 bits)\n# B: source register (4 bits)\n\n:move_object registerA4,registerB4 is inst0=0x07 ; registerA4 & registerB4\n{\n\tregisterA4 = registerB4;\n}\n\n# Move the contents of one object-bearing register to another.\n# \n# A: destination register (8 bits)\n# B: source register (16 bits)\n\n:move_object_from_16 registerA8,registerB16 is inst0=0x08 ; registerA8 ; registerB16\n{\n\tregisterA8 = registerB16;\n}\n\n# Move the contents of one object-bearing register to another.\n# \n# A: destination register (16 bits)\n# B: source register (16 bits)\n\n:move_object_16 registerA16,registerB16 is inst1=0x09 & inst1_padding ; registerA16 ; registerB16\n{\n\tregisterA16 = registerB16;\n}\n\n# Move the single-word non-object result of the most recent invoke-kind \n# into the indicated register. This must be done as the instruction \n# immediately after an invoke-kind whose (single-word, non-object) \n# result is not to be ignored; anywhere else is invalid.\n#\n# A: destination register (8 bits)\n\n:move_result registerA8 is inst0=0x0a ; registerA8\n{\n\tregisterA8 = resultreg;\n}\n\n# Move the double-word result of the most recent invoke-kind into \n# the indicated register pair. This must be done as the instruction \n# immediately after an invoke-kind whose (double-word) result is \n# not to be ignored; anywhere else is invalid.\n#\n# A: destination register pair (8 bits)\n\n:move_result_wide registerA8w is inst0=0x0b ; registerA8w\n{\n\tregisterA8w = resultregw;\n}\n\n# Move the object result of the most recent invoke-kind into \n# the indicated register. This must be done as the instruction \n# immediately after an invoke-kind or filled-new-array whose \n# (object) result is not to be ignored; anywhere else is invalid.\n# \n# A: destination register (8 bits)\n\n:move_result_object registerA8 \t\tis inst0=0x0c ; registerA8\n{\n\tregisterA8 = resultreg;\n}\n\n# Save a just-caught exception into the given register. This must \n# be the first instruction of any exception handler whose caught \n# exception is not to be ignored, and this instruction must only \n# ever occur as the first instruction of an exception handler; \n# anywhere else is invalid.\n# \n# A: destination register (8 bits)\n\n:move_exception registerA8\t\t\tis inst0=0x0d ; registerA8\n{\n\t#TODO pCode\n\t# this requires state!?\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Return from a void method.\n\n:return_void is inst1=0x0e & inst1_padding\n{\n\treturn [sp];\n}\n\n# Return from a single-width (32-bit) non-object value-returning method. \n#\n# A: return value register (8 bits)\n\n:return registerA8\t\t\t\tis inst0=0x0f ; registerA8\n{\n\tresultreg = registerA8;\n\treturn [sp];\n}\n\n# Return from a double-width (64-bit) value-returning method.\n#\n# A: return value register-pair (8 bits)\n\n:return_wide registerA8w\t\t\tis inst0=0x10 ; registerA8w\n{\n\tresultregw = registerA8w;\n\treturn [sp];\n}\n\n# Return from an object-returning method.\n# \n# A: return value register (8 bits)\n\n:return_object registerA8\t\tis inst0=0x11 ; registerA8\n{\n\tresultreg = registerA8;\n\treturn [sp];\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Move the given literal value (sign-extended to 32 bits) into the specified register.\n# \n# A: destination register (4 bits)\n# B: signed int (4 bits)\n\n:const_4 registerA4,B_BITS_4_7_S is inst0=0x12 ; registerA4 & B_BITS_4_7_S\n{\n\tregisterA4 = sext( B_BITS_4_7_S:4) ;\n}\n\n# Move the given literal value (sign-extended to 32 bits) into the specified register.\n# \n# A: destination register (8 bits)\n# B: signed int (16 bits)\n\n:const_16 registerA8,B_BITS_0_15_S\tis inst0=0x13 ; registerA8 ; B_BITS_0_15_S\n{\n\tregisterA8 = sext( B_BITS_0_15_S:4 );\n}\n\n# Move the given literal value into the specified register.\n#\n# A: destination register (8 bits)\n# B: arbitrary 32-bit constant\n\n:\"const\" registerA8,constant32\t\tis inst0=0x14 ; registerA8 ; constant32\n{\n\tregisterA8 = constant32;\n}\n\n# Move the given literal value (right-zero-extended to 32 bits) into the specified register.\n# \n# A: destination register (8 bits)\n# B: signed int (16 bits)\n\n:const_high_16 registerA8,B_BITS_0_15 is inst0=0x15 ; registerA8 ; B_BITS_0_15\n{\n\tregisterA8 = B_BITS_0_15:4 << 16;\n}\n\n# Move the given literal value (sign-extended to 64 bits) into the specified register-pair.\n# \n# A: destination register (8 bits)\n# B: signed int (16 bits)\n\n:const_wide_16 registerA8w,constant16s is inst0=0x16 ; registerA8w ; constant16s\n{\n\tregisterA8w = sext( constant16s:2 );\n}\n\n# Move the given literal value (sign-extended to 64 bits) into the specified register-pair.\n# \n# A: destination register (8 bits)\n# B: signed int (32 bits)\n\n:const_wide_32 registerA8w,constant32s is inst0=0x17 ; registerA8w ; constant32s\n{\n\tregisterA8w = sext( constant32s:4 );\n}\n\n# Move the given literal value into the specified register-pair.\n# \n# A: destination register (8 bits)\n# B: arbitrary double-width (64-bit) constant\n\n:const_wide registerA8w,constant64 is inst0=0x18 ; registerA8w ; constant64\n{\n\tregisterA8w = constant64;\n}\n\n# Move the given literal value (right-zero-extended to 64 bits) into the specified register-pair.\n# \n# A: destination register (8 bits)\n# B: signed int (16 bits)\n\n:const_wide_high_16 registerA8w,B_BITS_0_15_S is inst0=0x19 ; registerA8w ; B_BITS_0_15_S\n{\n\tregisterA8w = B_BITS_0_15_S << 48;\n}\n\n# Move a reference to the string specified by the given index into the specified register.\n# \n# A: destination register (8 bits)\n# B: string index\n\n:const_string registerA8,B_BITS_0_15 is inst0=0x1a ; registerA8 ; B_BITS_0_15\n{\n\tregisterA8 = cpool(0:4, B_BITS_0_15:4, $(CPOOL_STRING));\n}\n\n# Move a reference to the string specified by the given index into the specified register.\n# \n# A: destination register (8 bits)\n# B: string index\n\n:const_string_jumbo registerA8,B_BITS_0_31 is inst0=0x1b ; registerA8 ; B_BITS_0_31\n{\n\tregisterA8 = cpool(0:4, B_BITS_0_31:4, $(CPOOL_STRING));\n}\n\n# Move a reference to the class specified by the given index into the \n# specified register. In the case where the indicated type is primitive, \n# this will store a reference to the primitive type's degenerate class.\n# \n# A: destination register (8 bits)\n# B: type index\n\n:const_class registerA8,B_BITS_0_15 is inst0=0x1c ; registerA8 ; B_BITS_0_15\n{\n\tregisterA8 = cpool( 0:4, B_BITS_0_15:4, $(CPOOL_CLASSREF));\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Acquire the monitor for the indicated object.\n# \n# A: reference-bearing register (8 bits)\n\n:monitor_enter\tregisterA8 is inst0=0x1d ; registerA8\n{\n\tmonitorEnter( registerA8 );\n}\n\n# Release the monitor for the indicated object. \n# \n# A: reference-bearing register (8 bits)\n\n:monitor_exit\tregisterA8 is inst0=0x1e ; registerA8\n{\n\tmonitorExit( registerA8 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Throw a ClassCastException if the reference in the given register \n# cannot be cast to the indicated type. \n# \n# A: reference-bearing register (8 bits)\n# B: type index (16 bits)\n\n:check_cast registerA8,B_BITS_0_15 is inst0=0x1f ; registerA8 ; B_BITS_0_15 \n{\n\tcheckCast( registerA8, cpool( 0:4, B_BITS_0_15:4, $(CPOOL_CLASSREF)) );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Store in the given destination register 1 if the indicated reference \n# is an instance of the given type, or 0 if not. \n#\n# A: destination register (4 bits)\n# B: reference-bearing register (4 bits)\n# C: type index (16 bits)\n\n:instance_of registerA4,registerB4,C_BITS_0_15 is inst0=0x20 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tres:1 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_INSTANCEOF) );\n\tregisterA4 = zext( res );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Store in the given destination register the length of the indicated array, in entries\n# \n# A: destination register (4 bits)\n# B: array reference-bearing register (4 bits)\n\n:array_length registerA4,registerB4 is inst0=0x21 ; registerA4 & registerB4 \n{\n\tregisterA4 = cpool( registerB4, 0:4, $(CPOOL_ARRAYLENGTH) );\n}\n\n# Construct a new instance of the indicated type, storing a reference \n# to it in the destination. The type must refer to a non-array class.\n#\n# A: destination register (8 bits)\n# B: type index\n\n:new_instance registerA8,B_BITS_0_15 is inst0=0x22 ; registerA8 ; B_BITS_0_15\n{\n\tregisterA8 = newobject( cpool( 0:4, B_BITS_0_15:4, $(CPOOL_CLASSREF)) );\n}\n\n# Construct a new array of the indicated type and size. The type must be an array type.\n# \n# A: destination register (8 bits)\n# B: size register\n# C: type index\n\n:new_array registerA4,registerB4,C_BITS_0_15 is inst0=0x23 ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tregisterA4 = newobject( cpool( 0:4, C_BITS_0_15:4, $(CPOOL_CLASSREF)), registerB4 );\n}\n\n# Construct an array of the given type and size, filling it with the supplied \n# contents. The type must be an array type. The array's contents must be \n# single-word (that is, no arrays of long or double, but reference types are \n# acceptable). The constructed instance is stored as a \"result\" in the same \n# way that the method invocation instructions store their results, so the \n# constructed instance must be moved to a register with an immediately \n# subsequent move-result-object instruction (if it is to be used).\n# \n# A: array size and argument word count (4 bits)\n# B: type index (16 bits)\n# C..G: argument registers (4 bits each)\n\n:filled_new_array TYPE_INDEX is inst0=0x24 ; N_ELEMENTS = 0 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG\n{\n\t#TODO pCode\n\tfilledNewArray( TYPE_INDEX:4 );\n}\n:filled_new_array TYPE_INDEX,regElemC is inst0=0x24 ; N_ELEMENTS = 1 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG\n{\n\t#TODO pCode\n\tfilledNewArray( TYPE_INDEX:4, regElemC );\n}\n:filled_new_array TYPE_INDEX,regElemC,regElemD is inst0=0x24 ; N_ELEMENTS = 2 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG\n{\n\t#TODO pCode\n\tfilledNewArray( TYPE_INDEX:4, regElemC, regElemD );\n}\n:filled_new_array TYPE_INDEX,regElemC,regElemD,regElemE is inst0=0x24 ; N_ELEMENTS = 3 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG\n{\n\t#TODO pCode\n\tfilledNewArray( TYPE_INDEX:4, regElemC, regElemD, regElemE );\n}\n:filled_new_array TYPE_INDEX,regElemC,regElemD,regElemE,regElemF is inst0=0x24 ; N_ELEMENTS = 4 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG\n{\n\t#TODO pCode\n\tfilledNewArray( TYPE_INDEX:4, regElemC, regElemD, regElemE, regElemF );\n}\n:filled_new_array TYPE_INDEX,regElemC,regElemD,regElemE,regElemF,regElemG is inst0=0x24 ; N_ELEMENTS = 5 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG\n{\n\t#TODO pCode\n\tfilledNewArray( TYPE_INDEX:4, regElemC, regElemD, regElemE, regElemF, regElemG );\n}\n\n# Construct an array of the given type and size, filling it with \n# the supplied contents. Clarifications and restrictions are the \n# same as filled-new-array, described above.\n# \n# A: array size and argument word count (8 bits)\n# B: type index (16 bits)\n# C: first argument register (16 bits)\n# N = A + C - 1\n\n:filled_new_array_range A_BITS_0_7,B_BITS_0_15,registerC16 is inst0=0x25 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\t#TODO pCode\n\tfilledNewArrayRange( A_BITS_0_7:4, B_BITS_0_15:4, registerC16 );\n}\n\n# Fill the given array with the indicated data. The reference must \n# be to an array of primitives, and the data table must match it in type \n# and must contain no more elements than will fit in the array. That is, \n# the array may be larger than the table, and if so, only the initial \n# elements of the array are set, leaving the remainder alone. \n# \n# A: array reference (8 bits)\n# B: signed \"branch\" offset to table data pseudo-instruction (32 bits) \n\n:fill_array_data registerA8,B_BITS_0_31_S is inst0=0x26 ; registerA8 ; B_BITS_0_31_S\n{\n\t#TODO pCode\n#\tfillArrayData\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Throw the indicated exception.\n#\n# A: exception-bearing register (8 bits)\n\n:throw registerA8 is inst0=0x27 ; registerA8\n{\n\tthrowException( registerA8 );\n\treturn [registerA8];#TODO is the best way to return??\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Unconditionally jump to the indicated instruction. \n# \n# A: signed branch offset (8 bits)\n\n:goto\t\tgoto8\tis inst0=0x28 ; goto8\n{\n\tgoto goto8;\n}\n\n# Unconditionally jump to the indicated instruction. \n#\n# A: signed branch offset (16 bits)\n\n:goto_16\tgoto16\tis inst1=0x29 & inst1_padding ; goto16\n{\n\tgoto goto16;\n}\n\n# Unconditionally jump to the indicated instruction.\n# \n# A: signed branch offset (32 bits)\n\n:goto_32\tgoto32\tis inst1=0x2a & inst1_padding ; goto32\n{\n\tgoto goto32;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Jump to a new instruction based on the value in the given register, \n# using a table of offsets corresponding to each value in a particular \n# integral range, or fall through to the next instruction if there is no match. \n#\n# A: register to test\n# B: signed \"branch\" offset to table data pseudo-instruction (32 bits) \n#\n# NOTE: Offset (B) and destinations must be multiplied by 2.\n\n# TODO use disassembly action??\n\n:packed_switch registerA8,B_BITS_0_31_S is inst0=0x2b ; registerA8 ; B_BITS_0_31_S\n{\n\tdistance:4 = B_BITS_0_31_S * 2;\n\tident:4 = *[ram] ( inst_start + distance );\n\tsize2:2 = *[ram] ( inst_start + distance + 2 );\n\tsze:4 = zext( size2 );\n\tfirst_key:4 = *[ram] ( inst_start + distance + 2 + 2 );\n\n\tif ( registerA8 < first_key ) goto inst_next;\n\tif ( registerA8 >= ( first_key + sze ) ) goto inst_next;\n\n\ttargets:4 = ( inst_start + distance + 2 + 2 + 4 );\n\tdelta:4 = ( registerA8 ) - ( first_key ); # which index into target\n\tvalue:4 = *[ram] ( targets + ( delta * 4 ) );\n\taddress:4 = ( inst_start + ( value * 2 ) );\n\n\tgoto [ address ];\n}\n\n# Jump to a new instruction based on the value in the given register, \n# using an ordered table of value-offset pairs, or fall through to the \n# next instruction if there is no match. \n# \n# A: register to test\n# B: signed \"branch\" offset to table data pseudo-instruction (32 bits) \n#\n# NOTE: Offset (B) and destinations must be multiplied by 2.\n\n:sparse_switch registerA8,B_BITS_0_31_S is inst0=0x2c ; registerA8 ; B_BITS_0_31_S\n{\n\tdistance:4 = B_BITS_0_31_S * 2;\n\ttemp:4 = inst_start;\n\tsize2:2 = *[ram] ( temp + 2 + distance);\n\tsze:4 = zext( size2 );\n\tdefaultPos:4 = inst_next;\n\n\n \taddress:4 = switchAssist( registerA8, sze, defaultPos, temp, distance );\n\tgoto [ address ];\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the indicated floating point or long comparison, \n# setting a to 0 if b == c, 1 if b > c, or -1 if b < c. \n# The \"bias\" listed for the floating point operations indicates \n# how NaN comparisons are treated: \"gt bias\" instructions return 1 for \n# NaN comparisons, and \"lt bias\" instructions return -1.\n#\n# For example, to check to see if floating point x < y it is advisable \n# to use cmpg-float; a result of -1 indicates that the test was true, \n# and the other values indicate it was false either due to a valid \n# comparison or because one of the values was NaN.\n#\n# A: destination register (8 bits)\n# B: first source register or pair\n# C: second source register or pair\n\n:cmpl_float registerA8,registerB8,registerC8 is inst0=0x2d ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = zext( registerC8 f<= registerB8) + zext( registerC8 f< registerB8) - 1;\n}\n\n:cmpg_float registerA8,registerB8,registerC8 is inst0=0x2e ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = zext( registerC8 f<= registerB8) + zext( registerC8 f< registerB8) - 1;\n}\n\n:cmpl_double registerA8,registerB8w,registerC8w is inst0=0x2f ; registerA8 ; registerB8w ; registerC8w\n{\n\tregisterA8 = zext( registerC8w f<= registerB8w) + zext( registerC8w f< registerB8w) - 1;\n}\n\n:cmpg_double registerA8,registerB8w,registerC8w is inst0=0x30 ; registerA8 ; registerB8w ; registerC8w\n{\n\tregisterA8 = zext( registerC8w f<= registerB8w) + zext( registerC8w f< registerB8w) - 1;\n}\n\n:cmp_long registerA8,registerB8w,registerC8w is inst0=0x31 ; registerA8 ; registerB8w ; registerC8w\n{\n\tregisterA8 = zext( registerC8w s<= registerB8w ) + zext( registerC8w s< registerB8w ) - 1;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Branch to the given destination if the given two registers' values compare as specified. \n# \n# A: first register to test (4 bits)\n# B: second register to test (4 bits)\n# C: signed branch offset (16 bits)\n\n:if_eq registerA4,registerB4,rel16\t\tis inst0=0x32 ; registerA4 & registerB4 ; rel16\n{\n\tif ( registerA4 == registerB4 ) goto rel16;\n}\n\n:if_ne registerA4,registerB4,rel16\t\tis inst0=0x33 ; registerA4 & registerB4 ; rel16\n{\n\tif ( registerA4 != registerB4 ) goto rel16;\n}\n\n:if_lt registerA4,registerB4,rel16\t\tis inst0=0x34 ; registerA4 & registerB4 ; rel16\n{\n\tif ( registerA4 s< registerB4 ) goto rel16;\n}\n\n:if_ge registerA4,registerB4,rel16\t\tis inst0=0x35 ; registerA4 & registerB4 ; rel16\n{\n\tif ( registerA4 s>= registerB4 ) goto rel16;\n}\n\n:if_gt registerA4,registerB4,rel16\t\tis inst0=0x36 ; registerA4 & registerB4 ; rel16\n{\n\tif ( registerA4 s> registerB4 ) goto rel16;\n}\n\n:if_le registerA4,registerB4,rel16\t\tis inst0=0x37 ; registerA4 & registerB4 ; rel16\n{\n\tif ( registerA4 s<= registerB4 ) goto rel16;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Branch to the given destination if the given register's value compares with 0 as specified. \n# \n# A: register to test (8 bits)\n# B: signed branch offset (16 bits)\n\n:if_eqz registerA8,rel16 is inst0=0x38 ; registerA8 ; rel16\n{\n\tif ( registerA8 == 0 ) goto rel16;\n}\n\n:if_nez registerA8,rel16 is inst0=0x39 ; registerA8 ; rel16\n{\n\tif ( registerA8 != 0 ) goto rel16;\n}\n\n:if_ltz registerA8,rel16 is inst0=0x3a ; registerA8 ; rel16\n{\n\tif ( registerA8 s< 0 ) goto rel16;\n}\n\n:if_gez registerA8,rel16 is inst0=0x3b ; registerA8 ; rel16\n{\n\tif ( registerA8 s>= 0 ) goto rel16;\n}\n\n:if_gtz registerA8,rel16 is inst0=0x3c ; registerA8 ; rel16\n{\n\tif ( registerA8 s> 0 ) goto rel16;\n}\n\n:if_lez registerA8,rel16 is inst0=0x3d ; registerA8 ; rel16\n{\n\tif ( registerA8 s<= 0 ) goto rel16;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the identified array operation at the identified index \n# of the given array, loading or storing into the value register.\n#\n# A: value register or pair; may be source or dest (8 bits)\n# B: array register (8 bits)\n# C: index register (8 bits)\n\n:aget registerA8,registerB8,registerC8 is inst0=0x44 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = *( registerB8 + registerC8*4 );\n}\n\n:aget_wide registerA8w,registerB8,registerC8 is inst0=0x45 ; registerA8w ; registerB8 ; registerC8\n{\n\tregisterA8w = *( registerB8 + registerC8*8 );\n}\n\n:aget_object registerA8,registerB8,registerC8 is inst0=0x46 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = *( registerB8 + registerC8*4 );\n}\n\n:aget_boolean registerA8,registerB8,registerC8 is inst0=0x47 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = zext( *:1 ( registerB8 + registerC8 ));\n}\n\n:aget_byte registerA8,registerB8,registerC8 is inst0=0x48 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = sext( *:1 (registerB8 + registerC8) );\n}\n\n:aget_char registerA8,registerB8,registerC8 is inst0=0x49 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = zext( *:2 (registerB8 + registerC8*2 ) );\n}\n\n:aget_short registerA8,registerB8,registerC8 is inst0=0x4a ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = sext( *:2 (registerB8 + registerC8 * 2 ) );\n}\n\n:aput registerA8,registerB8,registerC8 is inst0=0x4b ; registerA8 ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8 * 4 ) = registerA8;\n}\n\n:aput_wide registerA8w,registerB8,registerC8 is inst0=0x4c ; registerA8w ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8 * 8 ) = registerA8w;\n}\n\n:aput_object registerA8,registerB8,registerC8 is inst0=0x4d ; registerA8 ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8 * 4 ) = registerA8;\n}\n\n:aput_boolean registerA8,registerB8,registerC8 is inst0=0x4e ; registerA8 ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8 ) = registerA8:1;\n}\n\n:aput_byte registerA8,registerB8,registerC8 is inst0=0x4f ; registerA8 ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8 ) = registerA8:1;\n}\n\n:aput_char registerA8,registerB8,registerC8 is inst0=0x50 ; registerA8 ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8*2 ) = registerA8:2;\n}\n\n:aput_short registerA8,registerB8,registerC8 is inst0=0x51 ; registerA8 ; registerB8 ; registerC8\n{\n\t*( registerB8 + registerC8*2 ) = registerA8:2;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the identified object instance field operation with the \n# identified field, loading or storing into the value register. \n# \n# A: value register or pair; may be source or dest (4 bits)\n# B: object register (4 bits)\n# C: instance field reference index (16 bits)\n\n:iget registerA4,[registerB4:C_BITS_0_15] is inst0=0x52 ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = *ptr;\n}\n\n:iget_wide registerA4w,[registerB4:C_BITS_0_15] is inst0=0x53 ; registerA4w & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4w = *ptr;\n}\n\n:iget_object registerA4,[registerB4:C_BITS_0_15] is inst0=0x54 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = *ptr;\n}\n\n:iget_boolean registerA4,[registerB4:C_BITS_0_15] is inst0=0x55 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = zext( *:1 ptr );\n}\n\n:iget_byte registerA4,[registerB4:C_BITS_0_15] is inst0=0x56 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = sext( *:1 ptr );\n}\n\n:iget_char registerA4,[registerB4:C_BITS_0_15] is inst0=0x57 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = zext( *:2 ptr );\n}\n\n:iget_short registerA4,[registerB4:C_BITS_0_15] is inst0=0x58 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = sext( *:2 ptr );\t\n}\n\n:iput registerA4,[registerB4:C_BITS_0_15] is inst0=0x59 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4;\n}\n\n:iput_wide registerA4w,[registerB4:C_BITS_0_15] is inst0=0x5a ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4w;\n}\n\n:iput_object registerA4,[registerB4:C_BITS_0_15] is inst0=0x5b ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4;\n}\n\n:iput_boolean registerA4,[registerB4:C_BITS_0_15] is inst0=0x5c ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 1;\n}\n\n:iput_byte registerA4,[registerB4:C_BITS_0_15] is inst0=0x5d ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 1;\n}\n\n:iput_char registerA4,[registerB4:C_BITS_0_15] is inst0=0x5e ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 2;\t\n}\n\n:iput_short registerA4,[registerB4:C_BITS_0_15] is inst0=0x5f ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 2;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the identified object static field operation with the identified \n# static field, loading or storing into the value register.\n#\n# A: value register or pair; may be source or dest (8 bits)\n# B: static field reference index (16 bits)\n \n:sget registerA8,B_BITS_0_15 is inst0=0x60 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8 = *ptr;\n}\n:sget_wide registerA8w,B_BITS_0_15 is inst0=0x61 ; registerA8w ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8w = *ptr;\n}\n:sget_object registerA8,B_BITS_0_15 is inst0=0x62 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8 = *ptr;\n}\n:sget_boolean registerA8,B_BITS_0_15 is inst0=0x63 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8 = zext(*:1 ptr);\n}\n:sget_byte registerA8,B_BITS_0_15 is inst0=0x64 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8 = sext(*:1 ptr);\n}\n:sget_char registerA8,B_BITS_0_15 is inst0=0x65 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8 = zext(*:2 ptr);\n}\n:sget_short registerA8,B_BITS_0_15 is inst0=0x66 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\tregisterA8 = sext(*:2 ptr);\n}\n\n:sput registerA8,B_BITS_0_15 is inst0=0x67 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8;\n}\n:sput_wide registerA8w,B_BITS_0_15 is inst0=0x68 ; registerA8w ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8w;\n}\n:sput_object registerA8,B_BITS_0_15 is inst0=0x69 ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8;\n}\n:sput_boolean registerA8,B_BITS_0_15 is inst0=0x6a ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8:1;\n}\n:sput_byte registerA8,B_BITS_0_15 is inst0=0x6b ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8:1;\n}\n:sput_char registerA8,B_BITS_0_15 is inst0=0x6c ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8:2;\n}\n:sput_short registerA8,B_BITS_0_15 is inst0=0x6d ; registerA8 ; B_BITS_0_15\n{\n\tptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD));\n\t*ptr = registerA8:2;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Call the indicated method. The result (if any) may be stored with \n# an appropriate move-result* variant as the immediately subsequent \n# instruction.\n#\n# A: argument word count (4 bits)\n# B: method reference index (16 bits)\n# C..G: argument registers (4 bits each) \n\n# invoke-virtual is used to invoke a normal virtual method \n# (a method that is not private, static, or final, and is also not a constructor).\n\n:invoke_virtual METHOD_INDEX is inst0=0x6e ; N_PARAMS=0 & METHOD_INDEX\n{\n\tdestination:4 = cpool( 0:4, METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_virtual METHOD_INDEX,regParamC is inst0=0x6e ; N_PARAMS=1 & METHOD_INDEX & regParamC\n{\n\tiv0 = regParamC;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_virtual METHOD_INDEX,regParamC,regParamD is inst0=0x6e ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_virtual METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x6e ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_virtual METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x6e ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_virtual METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x6e ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tiv4 = regParamG;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n\n# invoke-super is used to invoke the closest superclass's virtual \n# method (as opposed to the one with the same method_id in the \n# calling class). The same method restrictions hold as for invoke-virtual.\n\n:invoke_super METHOD_INDEX is inst0=0x6f ; N_PARAMS=0 & METHOD_INDEX\n{\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_super METHOD_INDEX,regParamC is inst0=0x6f ; N_PARAMS=1 & METHOD_INDEX & regParamC\n{\n\tiv0 = regParamC;\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_super METHOD_INDEX,regParamC,regParamD is inst0=0x6f ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_super METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x6f ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_super METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x6f ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_super METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x6f ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tiv4 = regParamG;\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n\n# invoke-direct is used to invoke a non-static direct \n# method (that is, an instance method that is by its \n# nature non-overridable, namely either a private instance \n# method or a constructor).\n\n:invoke_direct METHOD_INDEX is inst0=0x70 ; N_PARAMS=0 & METHOD_INDEX\n{\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_METHOD));\n\tcall [destination];\n}\n:invoke_direct METHOD_INDEX,regParamC is inst0=0x70 ; N_PARAMS=1 & METHOD_INDEX & regParamC\n{\n\tiv0 = regParamC;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_direct METHOD_INDEX,regParamC,regParamD, is inst0=0x70 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_direct METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x70 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_direct METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x70 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_direct METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x70 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tiv4 = regParamG;\n\tdestination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n\n# invoke-static is used to invoke a static method \n# (which is always considered a direct method).\n\n:invoke_static METHOD_INDEX is inst0=0x71 ; N_PARAMS=0 & METHOD_INDEX\n{\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\n}\n:invoke_static METHOD_INDEX,regParamC is inst0=0x71 ; N_PARAMS=1 & METHOD_INDEX & regParamC\n{\n\tiv0 = regParamC;\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\t\n}\n:invoke_static METHOD_INDEX,regParamC,regParamD is inst0=0x71 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\n}\n:invoke_static METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x71 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\n}\n:invoke_static METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x71 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\n}\n:invoke_static METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x71 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tiv4 = regParamG;\n\tdestination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\n}\n\n# invoke-interface is used to invoke an interface \n# method, that is, on an object whose concrete \n# class isn't known, using a method_id that refers \n# to an interface.\n\n:invoke_interface METHOD_INDEX is inst0=0x72 ; N_PARAMS=0 & METHOD_INDEX\n{\n\tdestination:4 = cpool( 0:4, METHOD_INDEX,$(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_interface METHOD_INDEX,regParamC is inst0=0x72 ; N_PARAMS=1 & METHOD_INDEX & regParamC\n{\n\tiv0 = regParamC;\n\tdestination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_interface METHOD_INDEX,regParamC,regParamD is inst0=0x72 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tdestination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_interface METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x72 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tdestination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_interface METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x72 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tdestination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_interface METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x72 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tiv0 = regParamC;\n\tiv1 = regParamD;\n\tiv2 = regParamE;\n\tiv3 = regParamF;\n\tiv4 = regParamG;\t\n\tdestination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD));\n\tcall [ destination ];\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Call the indicated method. \n# See first invoke-kind description above for details, caveats, and suggestions. \n# \n# A: argument word count (8 bits)\n# B: method reference index (16 bits)\n# C: first argument register (16 bits)\n# N = A + C - 1\n\n:invoke_virtual_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x74 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tmoveRangeToIV( A_BITS_0_7:4, registerC16 );\n\tdestination:4 = cpool(registerC16, B_BITS_0_15:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_super_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x75 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tmoveRangeToIV( A_BITS_0_7:4, registerC16 );\n\tdestination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), B_BITS_0_15:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_direct_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x76 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tmoveRangeToIV( A_BITS_0_7:4, registerC16 );\n\tdestination:4 = cpool(registerC16, B_BITS_0_15:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n}\n:invoke_static_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x77 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tmoveRangeToIV( A_BITS_0_7:4, registerC16 );\n\tdestination:4 = cpool(0:4, B_BITS_0_15:4, $(CPOOL_STATIC_METHOD));\n\tcall [ destination ];\n}\n:invoke_interface_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x78 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tmoveRangeToIV( A_BITS_0_7:4, registerC16 );\n\tdestination:4 = cpool(registerC16, B_BITS_0_15:4, $(CPOOL_METHOD));\n\tcall [ destination ];\n} \n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the identified unary operation on the source register, \n# storing the result in the destination register.\n#\n# A: destination register or pair (4 bits)\n# B: source register or pair (4 bits)\n\n:neg_int registerA4,registerB4 is inst0=0x7b ; registerA4 & registerB4\n{\n\tregisterA4 = -registerB4;\n}\n\n:not_int registerA4,registerB4 is inst0=0x7c ; registerA4 & registerB4\n{\n\tregisterA4 = ~registerB4;\n}\n\n:neg_long registerA4w,registerB4w is inst0=0x7d ; registerA4w & registerB4w\n{\n\tregisterA4w = -registerB4w;\n}\n\n:not_long registerA4w,registerB4w is inst0=0x7e ; registerA4w & registerB4w\n{\n\tregisterA4w = ~registerB4w;\n}\n\n:neg_float registerA4,registerB4 is inst0=0x7f ; registerA4 & registerB4\n{\n\tregisterA4 = f-registerB4;\n}\n\n:neg_double registerA4,registerB4 is inst0=0x80 ; registerA4 & registerB4\n{\n\tregisterA4 = f-registerB4;\n}\n\n:int_to_long registerA4w,registerB4 is inst0=0x81 ; registerA4w & registerB4\n{\n\tregisterA4w = sext(registerB4);\n}\n\n:int_to_float registerA4,registerB4 is inst0=0x82 ; registerA4 & registerB4\n{\n\tregisterA4 = int2float(registerB4);\n}\n\n:int_to_double registerA4w,registerB4 is inst0=0x83 ; registerA4w & registerB4\n{\n\tregisterA4w = int2float(registerB4);\n}\n\n:long_to_int registerA4,registerB4w is inst0=0x84 ; registerA4 & registerB4w\n{\n\tregisterA4 = registerB4w:4;\n}\n:long_to_float registerA4,registerB4w is inst0=0x85 ; registerA4 & registerB4w\n{\n\tregisterA4 = int2float(registerB4w);\n}\n\n:long_to_double registerA4w,registerB4w is inst0=0x86 ; registerA4w & registerB4w\n{\n\tregisterA4w = int2float(registerB4w);\n}\n\n:float_to_int registerA4,registerB4 is inst0=0x87 ; registerA4 & registerB4\n{\n\tregisterA4 = trunc(registerB4);\n}\n\n:float_to_long registerA4w,registerB4 is inst0=0x88 ; registerA4w & registerB4\n{\n\tregisterA4w = trunc(registerB4);\n}\n\n:float_to_double registerA4w,registerB4 is inst0=0x89 ; registerA4w & registerB4\n{\n\tregisterA4w = float2float(registerB4);\n}\n\n:double_to_int registerA4,registerB4w is inst0=0x8a ; registerA4 & registerB4w\n{\n\tregisterA4 = trunc(registerB4w);\n}\n\n:double_to_long registerA4w,registerB4w is inst0=0x8b ; registerA4w & registerB4w\n{\n\tregisterA4w = trunc(registerB4w);\n}\n\n:double_to_float registerA4,registerB4w is inst0=0x8c ; registerA4 & registerB4w\n{\n\tregisterA4 = float2float(registerB4w);\n}\n\n:int_to_byte registerA4,registerB4 is inst0=0x8d ; registerA4 & registerB4\n{\n\tregisterA4 = sext(registerB4:1);\n}\n\n:int_to_char registerA4,registerB4 is inst0=0x8e ; registerA4 & registerB4\n{\n\tregisterA4 = zext(registerB4:2);\n}\n\n:int_to_short registerA4,registerB4 is inst0=0x8f ; registerA4 & registerB4\n{\n\tregisterA4 = sext(registerB4:2);\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the identified binary operation on the two source registers, \n# storing the result in the destination register.\n# \n# A: destination register or pair (8 bits)\n# B: first source register or pair (8 bits)\n# C: second source register or pair (8 bits)\n\n:add_int\t\tregisterA8,registerB8,registerC8 is inst0=0x90 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 + registerC8;\n}\n:sub_int\t\tregisterA8,registerB8,registerC8 is inst0=0x91 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 - registerC8;\n}\n:mul_int\t\tregisterA8,registerB8,registerC8 is inst0=0x92 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 * registerC8;\n}\n:div_int\t\tregisterA8,registerB8,registerC8 is inst0=0x93 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 s/ registerC8;\n}\n:rem_int\t\tregisterA8,registerB8,registerC8 is inst0=0x94 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 s% registerC8;\n}\n:and_int\t\tregisterA8,registerB8,registerC8 is inst0=0x95 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 & registerC8;\n}\n:or_int\t\t\tregisterA8,registerB8,registerC8 is inst0=0x96 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 | registerC8;\n}\n:xor_int\t\tregisterA8,registerB8,registerC8 is inst0=0x97 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 ^ registerC8;\n}\n:shl_int\t\tregisterA8,registerB8,registerC8 is inst0=0x98 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 << registerC8;\n}\n:shr_int\t\tregisterA8,registerB8,registerC8 is inst0=0x99 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 s>> registerC8;\n}\n:ushr_int\t\tregisterA8,registerB8,registerC8 is inst0=0x9a ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 >> registerC8;\n}\n:add_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0x9b ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w + registerC8w;\n}\n:sub_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0x9c ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w - registerC8w;\n}\n:mul_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0x9d ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w * registerC8w;\n}\n:div_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0x9e ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w s/ registerC8w;\n}\n:rem_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0x9f ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w s% registerC8w;\n}\n:and_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0xa0 ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w & registerC8w;\n}\n:or_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0xa1 ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w | registerC8w;\n}\n:xor_long\t\tregisterA8w,registerB8w,registerC8w is inst0=0xa2 ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w ^ registerC8w;\n}\n:shl_long\t\tregisterA8w,registerB8w,registerC8 is inst0=0xa3 ; registerA8w ; registerB8w ; registerC8\n{\n\tregisterA8w = registerB8w << registerC8;\n}\n:shr_long\t\tregisterA8w,registerB8w,registerC8 is inst0=0xa4 ; registerA8w ; registerB8w ; registerC8\n{\n\tregisterA8w = registerB8w s>> registerC8;\n}\n:ushr_long\t\tregisterA8w,registerB8w,registerC8 is inst0=0xa5 ; registerA8w ; registerB8w ; registerC8\n{\n\tregisterA8w = registerB8w >> registerC8;\n}\n:add_float\t\tregisterA8,registerB8,registerC8 is inst0=0xa6 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 f+ registerC8;\n}\n:sub_float\t\tregisterA8,registerB8,registerC8 is inst0=0xa7 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 f- registerC8;\n}\n:mul_float\t\tregisterA8,registerB8,registerC8 is inst0=0xa8 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 f* registerC8;\n}\n:div_float\t\tregisterA8,registerB8,registerC8 is inst0=0xa9 ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 f/ registerC8;\n}\n:rem_float\t\tregisterA8,registerB8,registerC8 is inst0=0xaa ; registerA8 ; registerB8 ; registerC8\n{\n\tregisterA8 = registerB8 s% registerC8;#TODO how to tell floating point??\n}\n:add_double\t\tregisterA8w,registerB8w,registerC8w is inst0=0xab ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w f+ registerC8w;\n}\n:sub_double\t\tregisterA8w,registerB8w,registerC8w is inst0=0xac ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w f- registerC8w;\n}\n:mul_double\t\tregisterA8w,registerB8w,registerC8w is inst0=0xad ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w f* registerC8w;\n}\n:div_double\t\tregisterA8w,registerB8w,registerC8w is inst0=0xae ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w f/ registerC8w;\n}\n:rem_double\t\tregisterA8w,registerB8w,registerC8w is inst0=0xaf ; registerA8w ; registerB8w ; registerC8w\n{\n\tregisterA8w = registerB8w s% registerC8w;#TODO how to tell floating point??\n} \n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the identified binary operation on the two source registers, \n# storing the result in the first source register.\n# \n# A: destination and first source register or pair (4 bits)\n# B: second source register or pair (4 bits)\n\n:add_int_2addr registerA4,registerB4 is inst0=0xb0 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 + registerB4;\n}\n:sub_int_2addr registerA4,registerB4 is inst0=0xb1 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 - registerB4;\n}\n:mul_int_2addr registerA4,registerB4 is inst0=0xb2 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 * registerB4;\n}\n:div_int_2addr registerA4,registerB4 is inst0=0xb3 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 s/ registerB4;\n}\n:rem_int_2addr registerA4,registerB4 is inst0=0xb4 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 s% registerB4;\n}\n:and_int_2addr registerA4,registerB4 is inst0=0xb5 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 & registerB4;\n}\n:or_int_2addr registerA4,registerB4 is inst0=0xb6 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 | registerB4;\n}\n:xor_int_2addr registerA4,registerB4 is inst0=0xb7 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 ^ registerB4;\n}\n:shl_int_2addr registerA4,registerB4 is inst0=0xb8 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 << registerB4;\n}\n:shr_int_2addr registerA4,registerB4 is inst0=0xb9 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 s>> registerB4;\n}\n:ushr_int_2addr registerA4,registerB4 is inst0=0xba ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 >> registerB4;\n}\n:add_long_2addr registerA4w,registerB4w is inst0=0xbb ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w + registerB4w;\n}\n:sub_long_2addr registerA4w,registerB4w is inst0=0xbc ; registerA4w & registerB4w\n{\n\tregisterA4w= registerA4w - registerB4w;\n}\n:mul_long_2addr registerA4w,registerB4w is inst0=0xbd ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w * registerB4w;\n}\n:div_long_2addr registerA4w,registerB4w is inst0=0xbe ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w s/ registerB4w;\n}\n:rem_long_2addr registerA4w,registerB4w is inst0=0xbf ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w s% registerB4w;\n}\n:and_long_2addr registerA4w,registerB4w is inst0=0xc0 ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w & registerB4w;\n}\n:or_long_2addr registerA4w,registerB4w is inst0=0xc1 ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w | registerB4w;\n}\n:xor_long_2addr registerA4w,registerB4w is inst0=0xc2 ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w ^ registerB4w;\n}\n:shl_long_2addr registerA4w,registerB4 is inst0=0xc3 ; registerA4w & registerB4\n{\n\tregisterA4w = registerA4w << registerB4;\n}\n:shr_long_2addr registerA4w,registerB4 is inst0=0xc4 ; registerA4w & registerB4\n{\n\tregisterA4w = registerA4w s>> registerB4;\n}\n:ushr_long_2addr registerA4w,registerB4 is inst0=0xc5 ; registerA4w & registerB4\n{\n\tregisterA4w = registerA4w >> registerB4;\n}\n:add_float_2addr registerA4,registerB4 is inst0=0xc6 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 f+ registerB4;\n}\n:sub_float_2addr registerA4,registerB4 is inst0=0xc7 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 f- registerB4;\n}\n:mul_float_2addr registerA4,registerB4 is inst0=0xc8 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 f* registerB4;\n}\n:div_float_2addr registerA4,registerB4 is inst0=0xc9 ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 f/ registerB4;\n}\n:rem_float_2addr registerA4,registerB4 is inst0=0xca ; registerA4 & registerB4\n{\n\tregisterA4 = registerA4 s% registerB4;\n}\n:add_double_2addr registerA4w,registerB4w is inst0=0xcb ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w f+ registerB4w;\n}\n:sub_double_2addr registerA4w,registerB4w is inst0=0xcc ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w f- registerB4w;\n}\n:mul_double_2addr registerA4w,registerB4w is inst0=0xcd ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w f* registerB4w;\n}\n:div_double_2addr registerA4w,registerB4w is inst0=0xce ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w f/ registerB4w;\n}\n:rem_double_2addr registerA4w,registerB4w is inst0=0xcf ; registerA4w & registerB4w\n{\n\tregisterA4w = registerA4w s% registerB4w;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the indicated binary op on the indicated register (first argument) \n# and literal value (second argument), storing the result in the destination \n# register.\n# \n# A: destination register (4 bits)\n# B: source register (4 bits)\n# C: signed int constant (16 bits)\n\n:add_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd0 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 + C_BITS_0_15_S;\n}\n:rsub_int registerA4,registerB4,C_BITS_0_15_S is inst0=0xd1 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = C_BITS_0_15_S - registerB4; # Twos-complement reverse subtraction.\n}\n:mul_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd2 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 * C_BITS_0_15_S;\n}\n:div_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd3 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 s/ C_BITS_0_15_S;\n}\n:rem_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd4 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 s% C_BITS_0_15_S;\n}\n:and_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd5 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 & C_BITS_0_15_S;\n}\n:or_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd6 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 | C_BITS_0_15_S;\n}\n:xor_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd7 ; registerA4 & registerB4 ; C_BITS_0_15_S\n{\n\tregisterA4 = registerB4 ^ C_BITS_0_15_S;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# Perform the indicated binary op on the indicated register (first argument) \n# and literal value (second argument), storing the result in the destination \n# register. \n# \n# A: destination register (8 bits)\n# B: source register (8 bits)\n# C: signed int constant (8 bits)\n\n:add_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xd8 ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 + C_BITS_0_7_S;\n}\n:rsub_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xd9 ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = C_BITS_0_7_S - registerB8; # Twos-complement reverse subtraction.\n}\n:mul_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xda ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 * C_BITS_0_7_S;\n}\n:div_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdb ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 s/ C_BITS_0_7_S;\n}\n:rem_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdc ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 s% C_BITS_0_7_S;\n}\n:and_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdd ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 & C_BITS_0_7_S;\n}\n:or_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xde ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 | C_BITS_0_7_S;\n}\n:xor_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdf ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 ^ C_BITS_0_7_S;\n}\n:shl_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xe0 ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 << C_BITS_0_7_S;\n}\n:shr_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xe1 ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 s>> C_BITS_0_7_S;\n}\n:ushr_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xe2 ; registerA8 ; registerB8 ; C_BITS_0_7_S\n{\n\tregisterA8 = registerB8 >> C_BITS_0_7_S; #TODO should this value be signed???\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_Base.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM (base set of instructions)\n#------------------------------------------------------------------------------------\n\n@include \"Dalvik_Base.sinc\"" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Android10.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/android10-release/libdexfile/dex/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_no_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_iput_iget.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n\n@include \"Dalvik_OpCode_FA_FD_dex.sinc\"\n@include \"Dalvik_OpCode_FE_FF_dex.sinc\"\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Android11.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/android11-release/libdexfile/dex/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_no_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_iput_iget.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n\n@include \"Dalvik_OpCode_FA_FD_dex.sinc\"\n@include \"Dalvik_OpCode_FE_FF_dex.sinc\"" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Android12.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/android12-release/libdexfile/dex/dex_instruction_list.h\n# https://android.googlesource.com/platform/art/+/refs/heads/android13-release/libdexfile/dex/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_unused.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_unused.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_unused.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n\n@include \"Dalvik_OpCode_FA_FD_dex.sinc\"\n@include \"Dalvik_OpCode_FE_FF_dex.sinc\"" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_KitKat.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/kitkat-release/runtime/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_unused.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n@include \"Dalvik_OpCode_FA_unused.sinc\"\n@include \"Dalvik_OpCode_FB_unused.sinc\"\n@include \"Dalvik_OpCode_FC_unused.sinc\"\n@include \"Dalvik_OpCode_FD_unused.sinc\"\n@include \"Dalvik_OpCode_FE_unused.sinc\"\n@include \"Dalvik_OpCode_FF_unused.sinc\"\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Lollipop.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/lollipop-release/runtime/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_unused.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n@include \"Dalvik_OpCode_FA_unused.sinc\"\n@include \"Dalvik_OpCode_FB_unused.sinc\"\n@include \"Dalvik_OpCode_FC_unused.sinc\"\n@include \"Dalvik_OpCode_FD_unused.sinc\"\n@include \"Dalvik_OpCode_FE_unused.sinc\"\n@include \"Dalvik_OpCode_FF_unused.sinc\"\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Marshmallow.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/marshmallow-release/runtime/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_no_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_iput_iget.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n@include \"Dalvik_OpCode_FA_unused.sinc\"\n@include \"Dalvik_OpCode_FB_unused.sinc\"\n@include \"Dalvik_OpCode_FC_unused.sinc\"\n@include \"Dalvik_OpCode_FD_unused.sinc\"\n@include \"Dalvik_OpCode_FE_unused.sinc\"\n@include \"Dalvik_OpCode_FF_unused.sinc\"\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Nougat.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/nougat-release/runtime/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_no_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_iput_iget.sinc\"\n\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n\n@include \"Dalvik_OpCode_FA_unused.sinc\"\n@include \"Dalvik_OpCode_FB_unused.sinc\"\n@include \"Dalvik_OpCode_FC_unused.sinc\"\n@include \"Dalvik_OpCode_FD_unused.sinc\"\n@include \"Dalvik_OpCode_FE_unused.sinc\"\n@include \"Dalvik_OpCode_FF_unused.sinc\"\n\ndefine pcodeop invokeLamda;\n\ndefine token invokeLamda_operands ( 24 )\n\tLAMBDA_vB = ( 4 , 7 )\n\tLAMBDA_vG = ( 0 , 3 )\n\tLAMBDA_vD = ( 12 , 15 )\n\tLAMBDA_vC = ( 8 , 11 )\n\tLAMBDA_vF = ( 20 , 23 )\n\tLAMBDA_vE = ( 16 , 19 )\n;\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF3, INVOKE_LAMBDA, \"invoke-lambda\", k25x, false, kIndexNone, kContinue | kThrow | kInvoke | kExperimental, kVerifyRegC /*TODO: | kVerifyVarArg*/) \\\n# k25x, // op vC, {vD, vE, vF, vG} (B: count)\n#\n# See https://android.googlesource.com/platform/art/+/nougat-release/runtime/dex_instruction-inl.h\n#\n# * uint16 ||| uint16\n# * 7-0 15-8 7-0 15-8\n# * |------|-----|||-----|-----|\n# * |opcode|vB|vG|||vD|vC|vF|vE|\n# * |------|-----|||-----|-----|\n#\n#\t\te.g. invoke-lambda vClosure, {vD, vE, vF, vG} -- up to 4 parameters + the closure.\n\n:invoke_lambda LAMBDA_vC,{} is inst0=0xf3 ; LAMBDA_vB=0 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE\n{\n\t#TODO pCode\n}\n:invoke_lambda LAMBDA_vC,{LAMBDA_vD} is inst0=0xf3 ; LAMBDA_vB=1 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE\n{\n\t#TODO pCode\n}\n:invoke_lambda LAMBDA_vC,{LAMBDA_vD,LAMBDA_vE} is inst0=0xf3 ; LAMBDA_vB=2 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE\n{\n\t#TODO pCode\n}\n:invoke_lambda LAMBDA_vC,{LAMBDA_vD,LAMBDA_vE,LAMBDA_vF} is inst0=0xf3 ; LAMBDA_vB=3 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE\n{\n\t#TODO pCode\n}\n:invoke_lambda LAMBDA_vC,{LAMBDA_vD,LAMBDA_vE,LAMBDA_vF,LAMBDA_vG} is inst0=0xf3 ; LAMBDA_vB=4 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE\n{\n\t#TODO pCode\n}\n\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF5, CAPTURE_VARIABLE, \"capture-variable\", k21c, false, kIndexStringRef, kExperimental, kVerifyRegA | kVerifyRegBString) \\\n#\n#\t\te.g. capture-variable v1, \"foobar\"\n\n:capture_variable registerA8,B_BITS_0_15 is inst0=0xf5 ; registerA8 ; B_BITS_0_15\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF6, CREATE_LAMBDA, \"create-lambda\", k21c, false_UNUSED, kIndexMethodRef, kContinue | kThrow | kExperimental, kVerifyRegA | kVerifyRegBMethod) \\\n#\n#\t\te.g. create-lambda v1, \"java/io/PrintStream/print(Ljava/lang/Stream;)V\"\n\n:create_lambda registerA8,B_BITS_0_15 is inst0=0xf6 ; registerA8 ; B_BITS_0_15\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF7, LIBERATE_VARIABLE, \"liberate-variable\", k22c, false, kIndexStringRef, kExperimental, kVerifyRegA | kVerifyRegB | kVerifyRegCString) \\\n#\n#\t\te.g. liberate-variable v0, v1, \"baz\"\n\n:liberate_variable registerA4,registerB4,C_BITS_0_15 is inst0=0xf7 ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF8, BOX_LAMBDA, \"box-lambda\", k22x, true, kIndexNone, kContinue | kExperimental, kVerifyRegA | kVerifyRegB) \\\n\n:box_lambda registerA8,registerB16 is inst0=0xf8 ; registerA8 ; registerB16\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF9, UNBOX_LAMBDA, \"unbox-lambda\", k22c, true, kIndexTypeRef, kContinue | kThrow | kExperimental, kVerifyRegA | kVerifyRegB | kVerifyRegCType) \\\n\n:unbox_lambda registerA4,registerB4,C_BITS_0_15 is inst0=0xf9 ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\t#TODO pCode\n}\n\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Oreo.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/oreo-release/runtime/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_no_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_iput_iget.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n\n@include \"Dalvik_OpCode_FA_FD_dex.sinc\"\n\n@include \"Dalvik_OpCode_FE_unused.sinc\"\n@include \"Dalvik_OpCode_FF_unused.sinc\"\n\n\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Pie.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n\n# Source:\n# https://android.googlesource.com/platform/art/+/refs/heads/pie-release/libdexfile/dex/dex_instruction_list.h\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_return_void_no_barrier.sinc\"\n\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_E3_EA_dex.sinc\"\n\n@include \"Dalvik_OpCode_EB_F2_iput_iget.sinc\"\n\n@include \"Dalvik_OpCode_F3_unused.sinc\"\n@include \"Dalvik_OpCode_F4_unused.sinc\"\n@include \"Dalvik_OpCode_F5_unused.sinc\"\n@include \"Dalvik_OpCode_F6_unused.sinc\"\n@include \"Dalvik_OpCode_F7_unused.sinc\"\n@include \"Dalvik_OpCode_F8_unused.sinc\"\n@include \"Dalvik_OpCode_F9_unused.sinc\"\n\n@include \"Dalvik_OpCode_FA_FD_dex.sinc\"\n@include \"Dalvik_OpCode_FE_FF_dex.sinc\"\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_ODEX_KitKat.slaspec", "content": "#------------------------------------------------------------------------------------\n#\tSleigh specification file for DALVIK VM\n#------------------------------------------------------------------------------------\n#\n# Source:\n# https://android.googlesource.com/platform/dalvik/+/refs/heads/kitkat-release/libdex/DexFile.h\n# https://android.googlesource.com/platform/dalvik/+/refs/heads/kitkat-release/libdex/DexOpcodes.h\n#\n\n@include \"Dalvik_Base.sinc\"\n\n@include \"Dalvik_OpCode_3E_43_unused.sinc\"\n\n@include \"Dalvik_OpCode_73_unused.sinc\"\n@include \"Dalvik_OpCode_79_unused.sinc\"\n@include \"Dalvik_OpCode_7A_unused.sinc\"\n\n@include \"Dalvik_OpCode_FF_unused.sinc\"\n\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iget_volatile registerA4,[registerB4:C_BITS_0_15] is inst0=0xe3 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4 = getInstanceFieldVolatile( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iput_volatile registerA4,[registerB4:C_BITS_0_15] is inst0=0xe4 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldVolatile( registerB4, C_BITS_0_15:16, registerA4 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:sget_volatile registerA8,B_BITS_0_15 is inst0=0xe5 ; registerA8 ; B_BITS_0_15\n{\n\tregisterA8 = getStaticFieldVolatile( B_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:sput_volatile registerA8,B_BITS_0_15 is inst0=0xe6 ; registerA8 ; B_BITS_0_15\n{\n\tsetStaticFieldVolatile( B_BITS_0_15:16, registerA8 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iget_object_volatile registerA4,[registerB4:C_BITS_0_15] is inst0=0xe7 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4 = getInstanceFieldVolatile( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iget_wide_volatile registerA4w,[registerB4:C_BITS_0_15] is inst0=0xe8 ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4w = getInstanceFieldVolatile( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iput_wide_volatile registerA4w,[registerB4:C_BITS_0_15] is inst0=0xe9 ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldVolatile( registerB4, C_BITS_0_15:16, registerA4w );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:sget_wide_volatile registerA8w,B_BITS_0_15 is inst0=0xea ; registerA8w ; B_BITS_0_15\n{\n\tregisterA8w = getStaticFieldVolatile( B_BITS_0_15:16 );\n}\n\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:sput_wide_volatile registerA8w,B_BITS_0_15 is inst0=0xeb ; registerA8w ; B_BITS_0_15\n{\n\tsetStaticFieldVolatile( B_BITS_0_15:16, registerA8w );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n#:iput_byte_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xec ; registerA4 & registerB4 ; C_BITS_0_15 \n#{\n#\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 );\n#}\n\n:breakpoint\t\tis inst0=0xec\n{\n\t#TODO\n\tbreakpoint( );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:throw_verification_error registerA8,registerB16 is inst0=0xed ; registerA8 ; registerB16\n{\n\tregisterA8 = registerB16;\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:execute_inline INLINE,{} is inst0=0xee ; N_PARAMS=0 & INLINE\n{\n\tdestination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n:execute_inline INLINE,{regParamC} is inst0=0xee ; N_PARAMS=1 & INLINE & regParamC\n{\n\tdestination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 );\n\tcall [ destination ];\t\n}\n:execute_inline INLINE,{regParamC,regParamD} is inst0=0xee ; N_PARAMS=2 & INLINE & regParamC & regParamD\n{\n\tdestination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n:execute_inline INLINE,{regParamC,regParamD,regParamE} is inst0=0xee ; N_PARAMS=3 & INLINE & regParamC & regParamD & regParamE\n{\n\tdestination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n:execute_inline INLINE,{regParamC,regParamD,regParamE,regParamF} is inst0=0xee ; N_PARAMS=4 & INLINE & regParamC & regParamD & regParamE & regParamF\n{\n\tdestination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n:execute_inline INLINE,{regParamC,regParamD,regParamE,regParamF,regParamG} is inst0=0xee ; N_PARAMS=5 & INLINE & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tdestination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:execute_inline_range \"inline@\"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xef ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tdestination:4 = *[ram] ( ( 4 * B_BITS_0_15:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# THIS ODEX INSTRUCTION WAS VALID UNTIL API version 13 (OS Version 3.2.x)\n\n# :invoke_direct_empty METHOD_INDEX is inst0=0xf0 ; N_PARAMS=0 & METHOD_INDEX\n# {\n# \tdestination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 );\n# \tcall [ destination ];\n# }\n# :invoke_direct_empty METHOD_INDEX,regParamC is inst0=0xf0 ; N_PARAMS=1 & METHOD_INDEX & regParamC\n# {\n# \tdestination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 );\n# \tcall [ destination ];\t\n# }\n# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD is inst0=0xf0 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n# {\n# \tdestination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 );\n# \tcall [ destination ];\n# }\n# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0xf0 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n# {\n# \tdestination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 );\n# \tcall [ destination ];\n# }\n# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0xf0 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n# {\n# \tdestination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 );\n# \tcall [ destination ];\n# }\n# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xf0 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n# {\n# \tdestination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 );\n# \tcall [ destination ];\n# }\n\n:invoke_object_init_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xf0 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tdestination:4 = *[ram] ( ( 4 * B_BITS_0_15:4 ) + 0xe0000000 );\n\tcall [ destination ];\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:return_void_barrier is inst1=0xf1 & inst1_padding\n{\n\treturn [sp];#TODO\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iget_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf2 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iget_wide_quick \"field@\"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xf3 ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4w = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iget_object_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf4 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iput_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf5 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iput_wide_quick \"field@\"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xf6 ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4w );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iput_object_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf7 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET is inst0=0xf8 ; N_PARAMS=0 & VTABLE_OFFSET\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4 );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC is inst0=0xf8 ; N_PARAMS=1 & VTABLE_OFFSET & regParamC\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD is inst0=0xf8 ; N_PARAMS=2 & VTABLE_OFFSET & regParamC & regParamD\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE is inst0=0xf8 ; N_PARAMS=3 & VTABLE_OFFSET & regParamC & regParamD & regParamE\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF is inst0=0xf8 ; N_PARAMS=4 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xf8 ; N_PARAMS=5 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF, regParamG );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:invoke_virtual_quick_range \"vtable@\"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xf9 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tinvokeVirtualQuickRange( B_BITS_0_15:4, A_BITS_0_7:4, registerC16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:invoke_super_quick \"vtable@\"^VTABLE_OFFSET is inst0=0xfa ; N_PARAMS=0 & VTABLE_OFFSET\n{\n\tinvokeSuperQuick( VTABLE_OFFSET:4 );\n}\n:invoke_super_quick \"vtable@\"^VTABLE_OFFSET,regParamC is inst0=0xfa ; N_PARAMS=1 & VTABLE_OFFSET & regParamC\n{\n\tinvokeSuperQuick( VTABLE_OFFSET:4, regParamC );\n}\n:invoke_super_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD is inst0=0xfa ; N_PARAMS=2 & VTABLE_OFFSET & regParamC & regParamD\n{\n\tinvokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD );\n}\n:invoke_super_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE is inst0=0xfa ; N_PARAMS=3 & VTABLE_OFFSET & regParamC & regParamD & regParamE\n{\n\tinvokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE );\n}\n:invoke_super_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF is inst0=0xfa ; N_PARAMS=4 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF\n{\n\tinvokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF );\n}\n:invoke_super_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xfa ; N_PARAMS=5 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tinvokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF, regParamG );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:invoke_super_quick_range \"vtable@\"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xfb ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tinvokeSuperQuickRange( B_BITS_0_15:4, A_BITS_0_7:4, registerC16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:iput_object_volatile registerA4,registerB4,C_BITS_0_15 is inst0=0xfc ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldVolatile( registerB4, C_BITS_0_15:16, registerA4 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:sget_object_volatile registerA8,B_BITS_0_15 is inst0=0xfd ; registerA8 ; B_BITS_0_15 \n{\n\tregisterA8 = getStaticFieldVolatile( B_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:sput_object_volatile registerA8,B_BITS_0_15 is inst0=0xfe ; registerA8 ; B_BITS_0_15 \n{\n\tsetStaticFieldVolatile( B_BITS_0_15:16, registerA8 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n# 0xff ?\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_3E_43_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x3E, UNUSED_3E, \"unused-3e\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_3e is inst0=0x3e\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x3F, UNUSED_3F, \"unused-3f\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_3f is inst0=0x3f\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x40, UNUSED_40, \"unused-40\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_40 is inst0=0x40\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x41, UNUSED_41, \"unused-41\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_41 is inst0=0x41\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x42, UNUSED_42, \"unused-42\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_42 is inst0=0x42\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x43, UNUSED_43, \"unused-43\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_43 is inst0=0x43\n{\n\t#no pCode\n}\n \n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_barrier.sinc", "content": "#------------------------------------------------------------------------------------\n# V(0x73, RETURN_VOID_BARRIER, \"return-void-barrier\", k10x, false, kNone, kReturn, kVerifyNone) \\\n\n:return_void_barrier is inst1=0x73 & inst1_padding\n{\n\treturn [sp];\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_no_barrier.sinc", "content": "#------------------------------------------------------------------------------------\n# V(0x73, RETURN_VOID_NO_BARRIER, \"return-void-no-barrier\", k10x, false, kNone, kReturn, kVerifyNone) \\\n\n:return_void_no_barrier is inst1=0x73 & inst1_padding\n{\n\treturn [sp];\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_73_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n\n:unused_73 is inst0=0x73\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_79_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x79, UNUSED_79, \"unused-79\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_79 is inst0=0x79\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_7A_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0x7A, UNUSED_7A, \"unused-7a\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_7a is inst0=0x7a\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_dex.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE3, IGET_QUICK, \"iget-quick\", k22c, true, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \\\n\n:iget_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe3 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE4, IGET_WIDE_QUICK, \"iget-wide-quick\", k22c, true, kFieldRef, kContinue | kThrow, kVerifyRegAWide | kVerifyRegB) \\\n\n:iget_wide_quick \"field@\"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xe4 ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4w = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE5, IGET_OBJECT_QUICK, \"iget-object-quick\", k22c, true, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \\\n\n:iget_object_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe5 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tregisterA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE6, IPUT_QUICK, \"iput-quick\", k22c, false, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \\\n\n:iput_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe6 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE7, IPUT_WIDE_QUICK, \"iput-wide-quick\", k22c, false, kFieldRef, kContinue | kThrow, kVerifyRegAWide | kVerifyRegB) \\\n\n:iput_wide_quick \"field@\"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xe7 ; registerA4w & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4w );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE8, IPUT_OBJECT_QUICK, \"iput-object-quick\", k22c, false, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \\\n\n:iput_object_quick \"field@\"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe8 ; registerA4 & registerB4 ; C_BITS_0_15 \n{\n\tsetInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE9, INVOKE_VIRTUAL_QUICK, \"invoke-virtual-quick\", k35c, false, kMethodRef, kContinue | kThrow | kInvoke, kVerifyVarArg) \\\n\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET is inst0=0xe9 ; N_PARAMS=0 & VTABLE_OFFSET\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4 );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC is inst0=0xe9 ; N_PARAMS=1 & VTABLE_OFFSET & regParamC\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD is inst0=0xe9 ; N_PARAMS=2 & VTABLE_OFFSET & regParamC & regParamD\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE is inst0=0xe9 ; N_PARAMS=3 & VTABLE_OFFSET & regParamC & regParamD & regParamE\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF is inst0=0xe9 ; N_PARAMS=4 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF );\n}\n:invoke_virtual_quick \"vtable@\"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xe9 ; N_PARAMS=5 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\tinvokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF, regParamG );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xEA, INVOKE_VIRTUAL_RANGE_QUICK, \"invoke-virtual/range-quick\", k3rc, false, kMethodRef, kContinue | kThrow | kInvoke, kVerifyVarArgRange) \\\n\n:invoke_virtual_quick_range \"vtable@\"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xea ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\tinvokeVirtualQuickRange( B_BITS_0_15:4, A_BITS_0_7:4, registerC16 );\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE3, UNUSED_E3, \"unused-e3\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e3 is inst0=0xe3\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE4, UNUSED_E4, \"unused-e4\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e4 is inst0=0xe4\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE5, UNUSED_E5, \"unused-e5\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e5 is inst0=0xe5\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE6, UNUSED_E6, \"unused-e6\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e6 is inst0=0xe6\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE7, UNUSED_E7, \"unused-e7\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e7 is inst0=0xe7\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE8, UNUSED_E8, \"unused-e8\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e8 is inst0=0xe8\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xE9, UNUSED_E9, \"unused-e9\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_e9 is inst0=0xe9\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xEA, UNUSED_EA, \"unused-ea\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_ea is inst0=0xea\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_iput_iget.sinc", "content": "#------------------------------------------------------------------------------------\n# V(0xEB, IPUT_BOOLEAN_QUICK, \"iput-boolean-quick\", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iput_boolean_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xeb ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 1;\n}\n\n#------------------------------------------------------------------------------------\n# V(0xEC, IPUT_BYTE_QUICK, \"iput-byte-quick\", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iput_byte_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xec ; registerA4 & registerB4 ; C_BITS_0_15\n {\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 1;\n}\n\n#------------------------------------------------------------------------------------\n# V(0xED, IPUT_CHAR_QUICK, \"iput-char-quick\", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iput_char_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xed ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 2;\t\n}\n\n#------------------------------------------------------------------------------------\n# V(0xEE, IPUT_SHORT_QUICK, \"iput-short-quick\", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iput_short_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xee ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\t*ptr = registerA4 : 2;\n}\n\n#------------------------------------------------------------------------------------\n# V(0xEF, IGET_BOOLEAN_QUICK, \"iget-boolean-quick\", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iget_boolean_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xef ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = zext( *:1 ptr );\n}\n\n#------------------------------------------------------------------------------------\n# V(0xF0, IGET_BYTE_QUICK, \"iget-byte-quick\", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iget_byte_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xf0 ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = sext( *:1 ptr );\n}\n\n#------------------------------------------------------------------------------------\n# V(0xF1, IGET_CHAR_QUICK, \"iget-char-quick\", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iget_char_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xf1 ; registerA4 & registerB4 ; C_BITS_0_15\n {\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = zext( *:2 ptr );\n}\n\n#------------------------------------------------------------------------------------\n# V(0xF2, IGET_SHORT_QUICK, \"iget-short-quick\", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \\\n\n:iget_short_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xf2 ; registerA4 & registerB4 ; C_BITS_0_15\n{\n\tptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD));\n\tregisterA4 = sext( *:2 ptr );\t\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xEB, UNUSED_EB, \"unused-eb\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_eb is inst0=0xeb\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xEC, UNUSED_EC, \"unused-ec\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_ec is inst0=0xec\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xED, UNUSED_ED, \"unused-ed\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_ed is inst0=0xed\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xEE, UNUSED_EE, \"unused-ee\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_ee is inst0=0xee\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xEF, UNUSED_EF, \"unused-ef\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_ef is inst0=0xef\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF0, UNUSED_F0, \"unused-f0\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f0 is inst0=0xf0\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF1, UNUSED_F1, \"unused-f1\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f1 is inst0=0xf1\n{\n\t#no pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF2, UNUSED_F2, \"unused-f2\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f2 is inst0=0xf2\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F3_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF3, UNUSED_F3, \"unused-f3\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f3 is inst0=0xf3\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F4_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF4, UNUSED_F4, \"unused-f4\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f4 is inst0=0xf4\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F5_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF5, UNUSED_F5, \"unused-f5\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f5 is inst0=0xf5\n{\n\t#no pCode\n}\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F6_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF6, UNUSED_F6, \"unused-f6\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f6 is inst0=0xf6\n{\n\t#no pCode\n}\n\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F7_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF7, UNUSED_F7, \"unused-f7\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f7 is inst0=0xf7\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F8_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF8, UNUSED_F8, \"unused-f8\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f8 is inst0=0xf8\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F9_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xF9, UNUSED_F9, \"unused-f9\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_f9 is inst0=0xf9\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FA_FD_dex.sinc", "content": "define token invoke_poly_operands_2 ( 8 )\n\tPOLY_ARG_COUNT = ( 4 , 7 )\n\tPOLY_PARAM_G = ( 0 , 3 )\n;\n\ndefine token invoke_poly_operands_1 ( 48 )\n\tPOLY_METHOD_INDEX = ( 0 , 15 )\n\tPOLY_PARAM_D = ( 16 , 19 )\n\tPOLY_PARAM_C = ( 20 , 23 )\n\tPOLY_PARAM_F = ( 24 , 27 )\n\tPOLY_PARAM_E = ( 28 , 31 )\n\tPOLY_PROTO_INDEX = ( 32 , 47 )\n;\n\n#define token invoke_poly_operands_1 ( 64 )\n#\tPOLY_METHOD_INDEX = ( 0 , 15 )\n#\tPOLY_METHOD_HANDLE = ( 16 , 31 )\n#\tPOLY_PARAM_D = ( 32 , 35 )\n#\tPOLY_PARAM_C = ( 36 , 39 )\n#\tPOLY_PARAM_F = ( 40 , 43 )\n#\tPOLY_PARAM_E = ( 44 , 47 )\n#\tPOLY_PROTO_INDEX = ( 48 , 63 )\n#;\n\nregPolyC: reg is POLY_PARAM_C [ reg = (POLY_PARAM_C * 4) + 0x1000; ] { export *[register]:4 reg; }\nregPolyD: reg is POLY_PARAM_D [ reg = (POLY_PARAM_D * 4) + 0x1000; ] { export *[register]:4 reg; }\nregPolyE: reg is POLY_PARAM_E [ reg = (POLY_PARAM_E * 4) + 0x1000; ] { export *[register]:4 reg; }\nregPolyF: reg is POLY_PARAM_F [ reg = (POLY_PARAM_F * 4) + 0x1000; ] { export *[register]:4 reg; }\nregPolyG: reg is POLY_PARAM_G [ reg = (POLY_PARAM_G * 4) + 0x1000; ] { export *[register]:4 reg; }\n\ndefine token invoke_poly_range_operands ( 40 )\n\tPOLY_RANGE_ARG_COUNT\t= ( 0 , 7 )\n\tPOLY_RANGE_METHOD_INDEX\t= ( 8 , 23 )\n\tPOLY_RANGE_PROTO_INDEX\t= ( 24 , 39 )\n;\n\n#------------------------------------------------------------------------------------\n# V(0xFA, INVOKE_POLYMORPHIC, \"invoke-polymorphic\", k45cc, kIndexMethodAndProtoRef, kContinue | kThrow | kInvoke, kVerifyRegBMethod | kVerifyVarArgNonZero | kVerifyRegHPrototype) \\\n#\n# invoke-polymorphic {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH\n#\n#\tA: argument word count (4 bits)\n#\tB: method reference index (16 bits)\n#\tC: method handle reference to invoke (16 bits)\n#\tD..G: argument registers (4 bits each)\n#\tH: prototype reference index (16 bits)\n#\n#\t\tcase Instruction::k45cc: { // op {vC, vD, vE, vF, vG}, method@BBBB, proto@HHHH\n#\n# Invoke the indicated method handle. \n# The result (if any) may be stored with an appropriate move-result* variant as the immediately subsequent instruction. \n# The method reference must be to java.lang.invoke.MethodHandle.invoke or java.lang.invoke.MethodHandle.invokeExact.\n# The prototype reference describes the argument types provided and the expected return type. \n#\n# Present in Dex files from version 038 onwards. \n\n:invoke_polymorphic \"meth@\"^POLY_METHOD_INDEX,\"proto@\"^POLY_PROTO_INDEX,{} is inst0=0xfa ; POLY_ARG_COUNT=0 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX\n{\n\t#TODO pCode\n}\n:invoke_polymorphic \"meth@\"^POLY_METHOD_INDEX,\"proto@\"^POLY_PROTO_INDEX,{regPolyC} is inst0=0xfa ; POLY_ARG_COUNT=1 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC\n{\n\t#TODO pCode\n}\n:invoke_polymorphic \"meth@\"^POLY_METHOD_INDEX,\"proto@\"^POLY_PROTO_INDEX,{regPolyC,regPolyD} is inst0=0xfa ; POLY_ARG_COUNT=2 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD\n{\n\t#TODO pCode\n}\n:invoke_polymorphic \"meth@\"^POLY_METHOD_INDEX,\"proto@\"^POLY_PROTO_INDEX,{regPolyC,regPolyD,regPolyE} is inst0=0xfa ; POLY_ARG_COUNT=3 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD & regPolyE\n{\n\t#TODO pCode\n}\n:invoke_polymorphic \"meth@\"^POLY_METHOD_INDEX,\"proto@\"^POLY_PROTO_INDEX,{regPolyC,regPolyD,regPolyE,regPolyF} is inst0=0xfa ; POLY_ARG_COUNT=4 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD & regPolyE & regPolyF\n{\n\t#TODO pCode\n}\n:invoke_polymorphic \"meth@\"^POLY_METHOD_INDEX,\"proto@\"^POLY_PROTO_INDEX,{regPolyC,regPolyD,regPolyE,regPolyF,regPolyG} is inst0=0xfa ; POLY_ARG_COUNT=5 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD & regPolyE & regPolyF ; regPolyG \n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n# V(0xFB, INVOKE_POLYMORPHIC_RANGE, \"invoke-polymorphic/range\", k4rcc, kIndexMethodAndProtoRef, kContinue | kThrow | kInvoke, kVerifyRegBMethod | kVerifyVarArgRangeNonZero | kVerifyRegHPrototype) \\\n#\n# invoke-polymorphic/range {vCCCC .. vNNNN}, meth@BBBB, proto@HHHH\n#\n#\tA: argument word count (8 bits)\n#\tB: method reference index (16 bits)\n#\tC: method handle reference to invoke (16 bits)\n#\tH: prototype reference index (16 bits)\n#\tN = A + C - 1\n#\n#\t\tcase Instruction::k4rcc: { // op {vCCCC .. v(CCCC+AA-1)}, method@BBBB, proto@HHHH\n#\n# Invoke the indicated method handle. See the invoke-polymorphic description above for details.\n#\n# Present in Dex files from version 038 onwards. \n\n:invoke_polymorphic_range \"meth@\"^POLY_RANGE_METHOD_INDEX,\"cnt@\"^POLY_RANGE_ARG_COUNT,\"proto@\"^POLY_RANGE_PROTO_INDEX is inst0=0xfb ; POLY_RANGE_ARG_COUNT & POLY_RANGE_METHOD_INDEX & POLY_RANGE_PROTO_INDEX\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n# V(0xFC, INVOKE_CUSTOM, \"invoke-custom\", k35c, kIndexCallSiteRef, kContinue | kThrow, kVerifyRegBCallSite | kVerifyVarArg) \\\n#\n# invoke-custom {vC, vD, vE, vF, vG}, call_site@BBBB\n#\n#\tA: argument word count (4 bits)\n#\tB: call site reference index (16 bits)\n#\tC..G: argument registers (4 bits each) \n#\n# Resolves and invokes the indicated call site. \n# The result from the invocation (if any) may be stored with an \n# appropriate move-result* variant as the immediately subsequent instruction.\n#\n# This instruction executes in two phases: call site resolution and call site invocation.\n# \n# Call site resolution checks whether the indicated call site has an associated \n# java.lang.invoke.CallSite instance. If not, the bootstrap linker method for the \n# indicated call site is invoked using arguments present in the DEX file (see call_site_item). \n# The bootstrap linker method returns a java.lang.invoke.CallSite instance that will then \n# be associated with the indicated call site if no association exists. Another thread may \n# have already made the association first, and if so execution of the instruction continues \n# with the first associated java.lang.invoke.CallSite instance.\n#\n# Call site invocation is made on the java.lang.invoke.MethodHandle target of the resolved \n# java.lang.invoke.CallSite instance. The target is invoked as if executing invoke-polymorphic \n# (described above) using the method handle and arguments to the invoke-custom instruction as \n# the arguments to an exact method handle invocation. \n#\n# Present in Dex files from version 038 onwards. \n\n:invoke_custom METHOD_INDEX,{} is inst0=0xfc ; N_PARAMS=0 & METHOD_INDEX\n{\n\t#TODO pCode -- see invoke_direct\n}\n:invoke_custom METHOD_INDEX,{regParamC} is inst0=0xfc ; N_PARAMS=1 & METHOD_INDEX & regParamC\n{\n\t#TODO pCode\n}\n:invoke_custom ^METHOD_INDEX,{regParamC,regParamD} is inst0=0xfc ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD\n{\n\t#TODO pCode\n}\n:invoke_custom METHOD_INDEX,{regParamC,regParamD,regParamE} is inst0=0xfc ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE\n{\n\t#TODO pCode\n}\n:invoke_custom METHOD_INDEX,{regParamC,regParamD,regParamE,regParamF} is inst0=0xfc ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF\n{\n\t#TODO pCode\n}\n:invoke_custom METHOD_INDEX,{regParamC,regParamD,regParamE,regParamF,regParamG} is inst0=0xfc ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n# V(0xFD, INVOKE_CUSTOM_RANGE, \"invoke-custom/range\", k3rc, kIndexCallSiteRef, kContinue | kThrow, kVerifyRegBCallSite | kVerifyVarArgRange) \\\n#\n# invoke-custom/range {vCCCC .. vNNNN}, call_site@BBBB\n#\n#\tA: argument word count (8 bits)\n#\tB: call site reference index (16 bits)\n#\tC: first argument register (16-bits)\n#\tN = A + C - 1\n#\n# Resolve and invoke a call site. See the invoke-custom description above for details.\n#\n# Present in Dex files from version 038 onwards. \n\n:invoke_custom_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xfd ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16\n{\n\t#TODO pCode -- see invoke_direct_range\n}\n\n#------------------------------------------------------------------------------------\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FA_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFA, UNUSED_FA, \"unused-fa\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_fa is inst0=0xfa\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FB_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFB, UNUSED_FB, \"unused-fb\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_fb is inst0=0xfb\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FC_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFC, UNUSED_FC, \"unused-fc\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_fc is inst0=0xfc\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FD_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFD, UNUSED_FD, \"unused-fd\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_fd is inst0=0xfd\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FE_FF_dex.sinc", "content": "\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFE, CONST_METHOD_HANDLE, \"const-method-handle\", k21c, kIndexMethodHandleRef, kContinue | kThrow, 0, kVerifyRegA | kVerifyRegBMethodHandle) \\\n\n:const_method_handle registerA8,B_BITS_0_15 is inst0=0xfe ; registerA8 ; B_BITS_0_15\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFF, CONST_METHOD_TYPE, \"const-method-type\", k21c, kIndexProtoRef, kContinue | kThrow, 0, kVerifyRegA | kVerifyRegBPrototype)\n\n:const_method_type registerA8,B_BITS_0_15 is inst0=0xff ; registerA8 ; B_BITS_0_15\n{\n\t#TODO pCode\n}\n\n#------------------------------------------------------------------------------------\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FE_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFE, UNUSED_FE, \"unused-fe\", k10x, false, kUnknown, 0, kVerifyError) \\\n\n:unused_fe is inst0=0xfe\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FF_unused.sinc", "content": "#------------------------------------------------------------------------------------\n#------------------------------------------------------------------------------------\n# V(0xFF, UNUSED_FF, \"unused-ff\", k10x, false, kUnknown, 0, kVerifyError)\n\n:unused_ff is inst0=0xff\n{\n\t#no pCode\n}\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC05-M68HC05TB.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC05.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC05.ldefs", "content": "\n\n\n \n HC05 (6805) Microcontroller Family\n \n \n \n HC05 (6805) Microcontroller Family - M68HC05TB\n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC05.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC05.slaspec", "content": "# sleigh specification file for Freescale HC05 (6805, 68HC05)\n\n@define HC05 \"1\"\n\n@include \"HCS_HC.sinc\"\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC08-MC68HC908QY4.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC08.ldefs", "content": "\n\n\n \n HC08 Microcontroller Family\n \n \n \n HC08 Microcontroller Family - MC68HC908QY4\n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC08.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HC08.slaspec", "content": "# sleigh specification file for Freescale HC08 (68HC08)\n\n@define HC08 \"1\"\n\n@include \"HCS_HC.sinc\"\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS08-MC9S08GB60.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS08.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS08.ldefs", "content": "\n\n\n \n HCS08 Microcontroller Family\n \n \n \n HCS08 Microcontroller Family - MC9S08GB60\n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS08.opinion", "content": "\n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS08.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS08.slaspec", "content": "# sleigh specification file for Freescale HCS08 (68HCS08)\n\n@define HCS08 \"1\"\n\n@include \"HCS_HC.sinc\"\n" }, { "path": "pypcode/processors/HCS08/data/languages/HCS_HC.sinc", "content": "# common include file for HCS08, HC08 and HC05(6805) constructors\n\ndefine endian=big;\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=2 default;\ndefine space register type=register_space size=1;\n\n@define VECTOR_SWI \"0xFFFC\"\n\n################################################################\n# Registers\n################################################################\n\ndefine register offset=0x00 size=1 [ A ];\n\n@if defined(HC05)\ndefine register offset=0x10 size=1 [ X ];\n@elif defined(HCS08) || defined(HC08)\ndefine register offset=0x10 size=2 [ HIX ]; # H:X in the manual\ndefine register offset=0x10 size=1 [ HI X ];\n@endif\n\ndefine register offset=0x20 size=2 [ PC SP ];\ndefine register offset=0x20 size=1 [ PCH PCL SPH SPL ];\n\ndefine register offset=0x30 size=1 [ CCR ];\n\n@if defined(HCS08) || defined(HC08)\n@define V\t\t\"CCR[7,1]\"\t\t# Two's complement overflow Flag\n@endif\n\n#\t\t\t\t\"CCR[6,1]\"\t\t# unused\n#\t\t\t\t\"CCR[5,1]\"\t\t# unused\n@define H\t\t\"CCR[4,1]\"\t\t# Half Carry Flag\n@define I\t\t\"CCR[3,1]\"\t\t# Maskable interrupt control bit\n@define N\t\t\"CCR[2,1]\"\t\t# Negative Flag\n@define Z\t\t\"CCR[1,1]\"\t\t# Zero Flag\n@define C\t\t\"CCR[0,1]\"\t\t# Carry/Borrow Flag\n\n\n\n################################################################\n# Tokens\n################################################################\n\ndefine token opbyte8 (8)\n\top = (0,7)\n\top4_7 = (4,7)\n\top4_6 = (4,6)\n\tnIndex = (1,3)\n\top0_0 = (0,0)\n;\n\ndefine token opbyte16 (16)\n\top16 = (0,15)\n;\n\ndefine token data8 (8)\n\timm8 = (0,7)\n\tsimm8 = (0,7) signed\n\trel = (0,7) signed\n;\n\ndefine token data16 (16)\n\timm16 = (0,15)\n;\n\n\n################################################################\n# Pseudo Instructions\n################################################################\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\ndefine pcodeop readIRQ;\ndefine pcodeop stop;\ndefine pcodeop wait;\n@endif\n\n@if defined(HCS08) || defined(HC08)\ndefine pcodeop decimalAdjustAccumulator;\ndefine pcodeop decimalAdjustCarry;\n@endif\n\n@if defined(HCS08)\ndefine pcodeop backgroundDebugMode;\n@endif\n\n\n################################################################\n# Addressing tables\n################################################################\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\nopr8a_8:\t\timm8 is imm8 { export *:1 imm8; }\nopr16a_8:\t imm16 is imm16 { export *:1 imm16; }\niopr8i:\t\t \"#\"imm8 is imm8 { export *[const]:1 imm8; }\n@endif\n\n@if defined(HCS08) || defined(HC08)\nopr8a_16:\t imm8 is imm8 { export *:2 imm8; }\niopr8is:\t \"#\"simm8 is simm8 { export *[const]:1 simm8; }\niopr16i:\t\t\"#\"imm16 is imm16 { export *[const]:2 imm16; }\noprx8:\t\t\timm8 is imm8\t { export *[const]:1 imm8; }\noprx8_8_SP:\t\timm8,SP is imm8 & SP { address:2 = SP + zext(imm8:1); export *:1 address; }\noprx16_8_SP:\timm16,SP is imm16 & SP { address:2 = SP + imm16:2; export *:1 address; }\n@endif\n\n@if defined(HCS08)\nopr16a_16:\t imm16 is imm16 { export *:2 imm16; }\noprx8_16_SP:\timm8,SP is imm8 & SP { address:2 = SP + imm8; export *:2 address; }\n@endif\n\n# X or HIX addressing\n\n@if defined(HC05)\noprx8_8_X:\t\timm8,X is imm8 & X { address:2 = zext(X) + imm8; export address; }\noprx16_8_X:\t\timm16,X is imm16 & X { address:2 = zext(X) + imm16; export address; }\ncomma_X:\t\t\",\"X is X\t\t { address:2 = zext(X); export address; }\n@endif\n\n@if defined(HCS08) || defined(HC08)\noprx8_8_X:\t\timm8,X is imm8 & X { address:2 = HIX + imm8; export address; }\noprx16_8_X:\t\timm16,X is imm16 & X { address:2 = HIX + imm16; export address; }\ncomma_X:\t\t\",\"X is X\t\t { address:2 = HIX; export address; }\n@endif\n\n@if defined(HCS08)\noprx8_16_X:\t\timm8,X is imm8 & X { address:2 = HIX + imm8; export *:2 address; }\noprx16_16_X:\timm16,X is imm16 & X { address:2 = HIX + imm16; export *:2 address; }\n@endif\n\n\n# address decoding\n\nOP1: iopr8i\t\tis op4_6=2; iopr8i { export iopr8i; }\nOP1: opr8a_8\tis op4_6=3; opr8a_8 { export opr8a_8; }\nOP1: opr16a_8\tis op4_6=4; opr16a_8 { export opr16a_8; }\nOP1: oprx16_8_X\tis op4_6=5; oprx16_8_X { export *:1 oprx16_8_X; }\nOP1: oprx8_8_X\tis op4_6=6; oprx8_8_X { export *:1 oprx8_8_X; }\nOP1: comma_X\tis op4_6=7 & comma_X { export *:1 comma_X; }\n\n@if defined(HCS08) || defined(HC08)\nop2_opr8a: imm8 is imm8 { export *:1 imm8; }\n@endif\n\n\nADDR: opr8a_8\t\tis op4_6=3; opr8a_8\t\t{ export opr8a_8; }\nADDR: opr16a_8\t\tis op4_6=4; opr16a_8\t{ export opr16a_8; }\n\nADDRI: oprx16_8_X\tis op4_6=5; oprx16_8_X\t{ export oprx16_8_X; }\nADDRI: oprx8_8_X\tis op4_6=6; oprx8_8_X\t{ export oprx8_8_X; }\nADDRI: comma_X\t\tis op4_6=7 & comma_X\t{ export comma_X; }\n\nREL: reloc is rel [ reloc = inst_next + rel; ] { export *:1 reloc; }\n\nNthBit: nthbit is nIndex [ nthbit = (1 << nIndex); ] { export *[const]:1 nthbit; }\n\n\n################################################################\n# Macros\n################################################################\n\n\n@if defined(HCS08) || defined(HC08)\n\nmacro additionFlags(operand1, operand2, result) {\n\tlocal AFmask = -1 >> 4;\n\t$(H) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;\n\t$(V) = scarry(operand1, operand2);\n\t$(N) = result s< 0;\n\t$(C) = carry(operand1, operand2);\n\t$(Z) = (result == 0);\n}\n\nmacro additionWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C));\n\tlocal AFmask = -1 >> 4;\n\t$(H) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0;\n\t$(V) = scarry(operand1, operand2);\n\t$(C) = carry(operand1, operand2);\n\tlocal tempResult = operand1 + operand2;\n\t$(C) = $(C) || carry(tempResult, Ccopy);\n\t$(V) = $(V) ^^ scarry(tempResult, Ccopy);\n\tresult = tempResult + Ccopy;\n\t$(N) =result s< 0;\n\t$(Z) = (result == 0);\n}\n\n@elif defined(HC05)\n\n# V is not implemented in HC05\t\n\nmacro additionFlags(operand1, operand2, result) {\n\tlocal AFmask = -1 >> 4;\n\t$(H) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;\n $(N) =result s< 0;\n $(Z) = (result == 0);\n\t$(C) = carry(operand1, operand2);\n}\n\nmacro additionWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C));\n\tlocal AFmask = -1 >> 4;\n\t$(H) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0;\n\t$(C) = carry(operand1, operand2);\n\tlocal tempResult = operand1 + operand2;\n\t$(C) = $(C) || carry(tempResult, Ccopy);\n\tresult = tempResult + Ccopy;\n $(N) =result s< 0;\n $(Z) = (result == 0);\n}\n\n@endif\n\n\n@if defined(HCS08) || defined(HC08)\n\nmacro subtractionFlags(operand1, operand2, result) {\n\t$(V) = sborrow(operand1, operand2);\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(C) = operand1 < operand2;\n}\n\nmacro subtractWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C));\n\t$(V) = sborrow(operand1, operand2);\n\n\t$(C) = operand1 < operand2;\n\tlocal tempResult = operand1 - operand2;\n\t$(C) = $(C) || (tempResult < Ccopy);\n\t$(V) = $(V) ^^ sborrow(tempResult, Ccopy);\n\tresult = tempResult - Ccopy;\n\t$(N) = result s< 0;\n}\n\n@elif defined(HC05)\nmacro subtractionFlags(operand1, operand2, result) {\n # V is not implemented in HC05\t\n\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(C) = operand1 < operand2;\n}\n\nmacro subtractWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C));\n\t# V is not implemented in HC05\t\n\n\t$(C) = operand1 < operand2;\n\tlocal tempResult = operand1 - operand2;\n\t$(C) = $(C) || (tempResult < Ccopy);\n\tresult = tempResult - Ccopy;\n\t$(N) = result s< 0;\n}\n\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_equals_0() {\n\t$(V) = 0;\n}\n@elif defined(HC05)\nmacro V_equals_0() {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_equals_C() {\n\t$(V) = $(C);\n}\n@elif defined(HC05)\nmacro V_equals_C() {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_equals_N_xor_C() {\n\t$(V) = $(N) ^ $(C);\t\n}\n@elif defined(HC05)\nmacro V_equals_N_xor_C() {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_CMP_flag(operand, result) {\n\t$(V) = ( ((A & ~operand & ~result) | (~A & operand & result)) & 0b10000000 ) != 0;\n}\n@elif defined(HC05)\nmacro V_CMP_flag(operand, result) {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_CPHX_flag(operand, result) {\n\t$(V) = ( ((HIX & ~operand & ~result) | (~HIX & operand & result)) & 0x8000 ) != 0;\n}\n@elif defined(HC05)\nmacro V_CPHX_flag(operand, result) {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_CPX_flag(operand, result) {\n\t$(V) = ( ((X & ~operand & ~result) | (~X & operand & result)) & 0b10000000 ) != 0;\n}\n@elif defined(HC05)\nmacro V_CPX_flag(operand, result) {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_DEC_flag(operand, result) {\n\t$(V) = ( (~result & operand) & 0b10000000 ) != 0;\n}\n@elif defined(HC05)\nmacro V_DEC_flag(operand, result) {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_INC_flag(operand, result) {\n\t$(V) = ( (~operand & result) & 0b10000000 ) != 0;\n}\n@elif defined(HC05)\nmacro V_INC_flag(operand, result) {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08)\nmacro V_NEG_flag(operand, result) {\n\t$(V) = ( (operand & result) & 0b10000000 ) != 0;\n}\n@elif defined(HC05)\nmacro V_NEG_flag(operand, result) {} # empty macro because V is not implemented in HC05\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\nmacro Pull1(operand) {\n\tSP = SP + 1;\n\toperand = *:1 SP;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\nmacro Pull2(operand) {\n\tSP = SP + 1;\n\toperand = *:2 SP;\n\tSP = SP + 1;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\nmacro Push1(operand) {\n\t*:1 SP = operand;\n\tSP = SP - 1;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\nmacro Push2(operand) {\n\tSP = SP - 1;\n\t*:2 SP = operand;\n\tSP = SP - 1;\n}\n@endif\n\n################################################################\n# Constructors\n################################################################\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1\n{\n\top1:1 = OP1;\n\n\tadditionWithCarry(A, op1, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP\n{\n\top1:1 = oprx16_8_SP;\n\n\tadditionWithCarry(A, op1, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP\n{\n\top1:1 = oprx8_8_SP;\n\n\tadditionWithCarry(A, op1, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1\n{ \n\top1:1 = OP1;\n\n\tresult:1 = A + op1;\n\tadditionFlags(A, op1,result);\n\tA = result;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP\n{ \n\top1:1 = oprx16_8_SP;\n\n\tresult:1 = A + op1;\n\tadditionFlags(A, op1,result);\n\tA = result;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP\n{ \n\top1:1 = oprx8_8_SP;\n\n\tresult:1 = A + op1;\n\tadditionFlags(A, op1,result);\n\tA = result;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:AIS iopr8is is op=0xA7; iopr8is\n{\n\tSP = SP + sext(iopr8is);\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:AIX iopr8is is op=0xAF; iopr8is\n{\n\tHIX = HIX + sext(iopr8is);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1\n{ \n\tA = A & OP1;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP\n{ \n\tA = A & oprx16_8_SP;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP\n{ \n\tA = A & oprx8_8_SP;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ASLA is op=0x48 \n{\n\t$(C) = A >> 7;\n\tA = A << 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ASLX is op=0x58 \n{\n\t$(C) = X >> 7;\n\tX = X << 1;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1 \n{\n\ttmp:1 = OP1;\n\t$(C) = tmp >> 7;\n\ttmp = tmp << 1;\n\tOP1 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP\n{\n\ttmp:1 = oprx8_8_SP;\n\t$(C) = tmp >> 7;\n\ttmp = tmp << 1;\n\toprx8_8_SP = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ASRA is op=0x47 \n{\n\t$(C) = A & 1;\n\tA = A s>> 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ASRX is op=0x57 \n{\n\t$(C) = X & 1;\n\tX = X s>> 1;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1 \n{\n\ttmp:1 = OP1;\n\t$(C) = tmp & 1;\n\ttmp = tmp s>> 1;\n\tOP1 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP\n{\n\ttmp:1 = oprx8_8_SP;\n\t$(C) = tmp & 1;\n\ttmp = tmp s>> 1;\n\toprx8_8_SP = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BCC REL is op=0x24; REL\n{\n\tif ($(C) == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8\n{\n\topr8a_8 = opr8a_8 & ~NthBit;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BCS REL is op=0x25; REL\n{\n\tif ($(C) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BEQ REL is op=0x27; REL\n{\n\tif ($(Z) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:BGE REL is op=0x90; REL\n{\n\tif (($(N) ^ $(V)) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08)\n:BGND is op=0x82\n{\n\tbackgroundDebugMode();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:BGT REL is op=0x92; REL\n{\n\tif (($(Z) | ($(N) ^ $(V))) == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BHCC REL is op=0x28; REL\n{\n\tif ($(H) == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BHCS REL is op=0x29; REL\n{\n\tif ($(H) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BHI REL is op=0x22; REL\n{\n\tif (($(C) | $(Z)) == 0) goto REL;\n}\n@endif\n\n#:BHS REL\tis op=0x24; REL\t\tSee BCC\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BIH REL is op=0x2F; REL\n{\n\ttmp:1 = readIRQ();\n\tif (tmp == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BIL REL is op=0x2E; REL\n{\n\ttmp:1 = readIRQ();\n\tif (tmp == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1\n{\n\tresult:1 = A & OP1;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP\n{\n\tresult:1 = A & oprx16_8_SP;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP\n{\n\tresult:1 = A & oprx8_8_SP;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:BLE REL is op=0x93; REL\n{\n\tif ($(Z) | ($(N) ^ $(V))) goto REL;\n}\n@endif\n\n#:BLO REL\tis op=0x25; REL\t\tsee BCS\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BLS REL is op=0x23; REL\n{\n\tif (($(C) | $(Z)) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:BLT REL is op=0x91; REL\n{\n\tif (($(N) ^ $(V)) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BMC REL is op=0x2C; REL\n{\n\tif ($(I) == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BMI REL is op=0x2B; REL\n{\n\tif ($(N) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BMS REL is op=0x2D; REL\n{\n\tif ($(I) == 1) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BNE REL is op=0x26; REL\n{\n\tif ($(Z) == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BPL REL is op=0x2A; REL\n{\n\tif ($(N) == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BRA REL is op=0x20; REL\n{\n\tgoto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL\n{\n\tresult:1 = opr8a_8 & NthBit;\n\t$(C) = (result != 0);\n\tif (result == 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n# branch never is a two-byte nop\n:BRN REL is op=0x21; REL\n{\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL\n{\n\tresult:1 = opr8a_8 & NthBit;\n\t$(C) = (result != 0);\n\tif (result != 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8\n{\n\topr8a_8 = opr8a_8 | NthBit;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:BSR REL is op=0xAD; REL \n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t\n\tcall REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL \n{\n\tif (A == opr8a_8) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CBEQA iopr8i, REL is op=0x41; iopr8i; REL\n{\n\tif (A == iopr8i) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CBEQX iopr8i, REL is op=0x51; iopr8i; REL\n{\n\tif (X == iopr8i) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CBEQ oprx8, X\"+,\", REL is (op=0x61) & X; oprx8; REL \n{\n\ttmp:1 = *:1 (HIX + zext(oprx8));\n\tHIX = HIX + 1;\n\t\n\tif (A == tmp) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CBEQ \",\"X\"+,\", REL is (op=0x71) & X; REL \n{\n\ttmp:1 = *:1 (HIX);\n\tHIX = HIX + 1;\n\t\n\tif (A == tmp) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL \n{\n\tif (A == oprx8_8_SP) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CLC is op=0x98\n{\n\t$(C) = 0;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CLI is op=0x9A\n{\n\t$(I) = 0;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CLRA is op=0x4F \n{\n\tA = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CLRX is op=0x5F \n{\n\tX = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CLRH is op=0x8C \n{\n\tHI = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1 \n{\n\tOP1 = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP\n{\n\toprx8_8_SP = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1\n{ \n\top1:1 = OP1;\n\ttmp:1 = A - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > A);\n\tV_CMP_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP\n{ \n\top1:1 = oprx16_8_SP;\n\ttmp:1 = A - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > A);\n\tV_CMP_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP\n{ \n\top1:1 = oprx8_8_SP;\n\ttmp:1 = A - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > A);\n\tV_CMP_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:COMA is op=0x43 \n{\n\tA = ~A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:COMX is op=0x53 \n{\n\tX = ~X;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1 \n{\n\ttmp:1 = ~OP1;\n\tOP1 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP\n{\n\ttmp:1 = ~oprx8_8_SP;\n\toprx8_8_SP = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:CPHX opr16a_16 is (op=0x3E); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = HIX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > HIX);\n\tV_CPHX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CPHX iopr16i is (op=0x65); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = HIX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > HIX);\n\tV_CPHX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CPHX opr8a_16 is (op=0x75); opr8a_16\n{ \n\top1:2 = *:2 opr8a_16;\n\ttmp:2 = HIX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > HIX);\n\tV_CPHX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08)\n:CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP\n{ \n\top1:2 = oprx8_16_SP;\n\ttmp:2 = HIX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > HIX);\n\tV_CPHX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1\n{ \n\top1:1 = OP1;\n\ttmp:1 = X - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > X);\n\tV_CPX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP\n{ \n\top1:1 = oprx16_8_SP;\n\ttmp:1 = X - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > X);\n\tV_CPX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP\n{ \n\top1:1 = oprx8_8_SP;\n\ttmp:1 = X - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > X);\n\tV_CPX_flag(op1, tmp);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DAA is op=0x72 \n{\n\tA = decimalAdjustAccumulator(A, $(C), $(H));\n\t$(C) = decimalAdjustCarry(A, $(C), $(H));\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\t# V is undefined\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DBNZA REL is op=0x4B; REL\n{\n\tA = A - 1;\n\tif (A != 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DBNZX REL is op=0x5B; REL\n{\n\tX = X - 1;\n\tif (X != 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL \n{\n\tOP1 = OP1 - 1;\n\tif (OP1 != 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL\n{\n\ttmp:1 = oprx8_8_SP - 1;\n\toprx8_8_SP = tmp;\n\tif (tmp != 0) goto REL;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:DECA is op=0x4A \n{\n\ttmp:1 = A;\n\tA = tmp - 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_DEC_flag(tmp, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:DECX is op=0x5A \n{\n\ttmp:1 = X;\n\tX = tmp - 1;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_DEC_flag(tmp, X);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1 \n{\n\ttmp:1 = OP1;\n\tresult:1 = tmp - 1;\n\tOP1 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_DEC_flag(tmp, result);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP\n{\n\ttmp:1 = oprx8_8_SP;\n\tresult:1 = tmp - 1;\n\toprx8_8_SP = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_DEC_flag(tmp, result);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:DIV is op=0x52 \n{\n\ttmp:2 = (zext(HI) << 8) | (zext(A));\n\tresultQ:2 = tmp / zext(X);\n\tA = resultQ:1;\n\tresultR:2 = tmp % zext(X);\n\tHI = resultR:1;\n\t$(Z) = (A == 0);\n\t$(C) = (X == 0) | (resultQ > 0x00FF);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1\n{ \n\top1:1 = OP1;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP\n{ \n\top1:1 = oprx16_8_SP;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP\n{ \n\top1:1 = oprx8_8_SP;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:INCA is op=0x4C \n{\n\ttmp:1 = A;\n\tA = tmp + 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_INC_flag(tmp, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:INCX is op=0x5C \n{\n\ttmp:1 = X;\n\tX = tmp + 1;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_INC_flag(tmp, X);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1 \n{\n\ttmp:1 = OP1;\n\tresult:1 = tmp + 1;\n\tOP1 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_INC_flag(tmp, result);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP\n{\n\ttmp:1 = oprx8_8_SP;\n\tresult:1 = tmp + 1;\n\toprx8_8_SP = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_INC_flag(tmp, result);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR\n{\n\tgoto ADDR;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI\n{\n\tgoto [ADDRI];\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t \n\tcall ADDR;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t \n\tcall [ADDRI];\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1\n{ \n\tA = OP1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP\n{ \n\tA = oprx16_8_SP;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP\n{ \n\tA = oprx8_8_SP;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LDHX iopr16i is (op=0x45); iopr16i\n{\n\tHIX = iopr16i; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LDHX opr8a_16 is (op=0x55); opr8a_16\n{\n\tHIX = opr8a_16; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:LDHX opr16a_16 is (op=0x32); opr16a_16\n{\n\tHIX = opr16a_16; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:LDHX \",\"X is (op16=0x9EAE) & X\n{\n\tHIX = *:2 (HIX); \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X\n{\n\tHIX = oprx16_16_X; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X\n{\n\tHIX = oprx8_16_X; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP\n{\n\tHIX = oprx8_16_SP; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1\n{ \n\tX = OP1;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP\n{ \n\tX = oprx16_8_SP;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP\n{ \n\tX = oprx8_8_SP;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_equals_0();\n}\n@endif\n\n## Logical Shift left is same as arithmetic shift left\n#:LSLA\t\tis op=0x48 \n#:LSLX\t\tis op=0x58 \n#:LSL OP1\tis (op=0x38 | op=0x68 | op=0x78) ... & OP1 \n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:LSRA is op=0x44 \n{\n\t$(C) = (A & 1);\n\tA = (A >> 1);\n\t$(Z) = (A == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:LSRX is op=0x54 \n{\n\t$(C) = (X & 1);\n\tX = (X >> 1);\n\t$(Z) = (X == 0);\n\t$(N) = 0;\t\n\tV_equals_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1 \n{\n\ttmp:1 = OP1;\n\t$(C) = tmp & 1;\n\ttmp = tmp >> 1;\n\tOP1 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP\n{\n\ttmp:1 = oprx8_8_SP;\n\t$(C) = tmp & 1;\n\ttmp = tmp >> 1;\n\toprx8_8_SP = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:MOV opr8a_8, op2_opr8a\tis (op=0x4E); opr8a_8; op2_opr8a\n{\n\tresult:1 = opr8a_8;\n\top2_opr8a = result;\n\tV_equals_0();\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:MOV opr8a_8, X\"+\" is (op=0x5E); opr8a_8 & X\n{\n\tresult:1 = opr8a_8;\n\t*:1 HIX = result;\n\tHIX = HIX + 1;\n\tV_equals_0();\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a\n{\n\tresult:1 = iopr8i;\n\top2_opr8a = result;\n\tV_equals_0();\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:MOV \",\"X\"+,\" op2_opr8a is (op=0x7E) & X; op2_opr8a\n{\n\tresult:1 = *:1 HIX;\n\top2_opr8a = result;\n\tHIX = HIX + 1;\n\tV_equals_0();\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:MUL is op=0x42\n{\n\top1:2 = zext(A);\n\top2:2 = zext(X);\n\tresult:2 = op1 * op2;\n\tA = result:1;\n\tX = result(1);\n\t$(H) = 0;\n\t$(C) = 0;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:NEGA is op=0x40 \n{\n\ttmp:1 = A;\n\tA = -tmp;\n\t$(C) = (A != 0);\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_NEG_flag(tmp, A); \n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:NEGX is op=0x50 \n{\n\ttmp:1 = X;\n\tX = -tmp;\n\t$(C) = (X != 0);\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_NEG_flag(tmp, X); \n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1 \n{\n\ttmp:1 = OP1;\n\tresult:1 = -tmp;\n\tOP1 = result;\n\t$(C) = (result != 0);\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_NEG_flag(tmp, result); \n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP\n{\n\ttmp:1 = oprx8_8_SP;\n\tresult:1 = -tmp;\n\toprx8_8_SP = result;\n\t$(C) = (result != 0);\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_NEG_flag(tmp, result); \n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:NOP is op = 0x9D\n{\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:NSA is op = 0x62\n{\n\tA = (A >> 4) | (A << 4);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1\n{ \n\tA = A | OP1; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP\n{ \n\tA = A | oprx16_8_SP; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP\n{ \n\tA = A | oprx8_8_SP; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:PSHA is op = 0x87\n{\n\tPush1( A );\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:PSHH is op = 0x8B\n{\n\tPush1( HI );\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:PSHX is op = 0x89\n{\n\tPush1( X );\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:PULA is op = 0x86\n{\n\tPull1( A );\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:PULH is op = 0x8A\n{\n\tPull1( HI );\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:PULX is op = 0x88\n{\n\tPull1( X );\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ROLA is op=0x49 \n{\n\ttmpC:1 = $(C) ;\n\t$(C) = A >> 7;\n\tA = (A << 1) | tmpC;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ROLX is op=0x59 \n{\n\ttmpC:1 = $(C);\n\t$(C) = X >> 7;\n\tX = (X << 1) | tmpC;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1 \n{\n\ttmpC:1 = $(C);\n\top1:1 = OP1;\n\t$(C) = op1 >> 7;\n\tresult:1 = (op1 << 1) | tmpC;\n\tOP1 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP\n{\n\ttmpC:1 = $(C);\n\top1:1 = oprx8_8_SP;\n\t$(C) = op1 >> 7;\n\tresult:1 = (op1 << 1) | tmpC;\n\toprx8_8_SP = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:RORA is op=0x46 \n{\n\ttmpC:1 = $(C) << 7;\n\t$(C) = A & 1;\n\tA = (A >> 1) | tmpC;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:RORX is op=0x56 \n{\n\ttmpC:1 = $(C) << 7;\n\t$(C) = X & 1;\n\tX = (X >> 1) | tmpC;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1 \n{\n\ttmpC:1 = $(C) << 7;\n\ttmp:1 = OP1;\n\t$(C) = tmp & 1;\n\ttmp = (tmp >> 1) | tmpC;\n\tOP1 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP\n{\n\ttmpC:1 = $(C) << 7;\n\ttmp:1 = oprx8_8_SP;\n\t$(C) = tmp & 1;\n\ttmp = (tmp >> 1) | tmpC;\n\toprx8_8_SP = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:RSP is op = 0x9C\n{\n\tSP = 0xff;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:RTI is op = 0x80\n{\n\tPull1( CCR );\n\t\n\tPull1( A );\n\t\n\tPull1( X );\n\t\n\ttmp:2 = 0;\n\tPull2( tmp );\n\t\n\treturn [tmp];\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:RTS is op = 0x81\n{\n\ttmp:2 = 0;\n\tPull2( tmp );\n\t\n\treturn [tmp];\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1\n{ \n\top1:1 = OP1;\n\t\n\tsubtractWithCarry(A, op1, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP\n{ \n\top1:1 = oprx16_8_SP;\n\t\n\tsubtractWithCarry(A, op1, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP\n{ \n\top1:1 = oprx8_8_SP;\n\t\n\tsubtractWithCarry(A, op1, A);\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:SEC is op = 0x99 \n{\n\t$(C) = 1;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:SEI is op = 0x9B \n{\n\t$(I) = 1;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1\n{\n\tOP1 = A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP\n{\n\toprx16_8_SP = A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP\n{\n\toprx8_8_SP = A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:STHX opr8a_16 is (op=0x35); opr8a_16\n{\n\topr8a_16 = HIX; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:STHX opr16a_16 is (op=0x96); opr16a_16\n{\n\topr16a_16 = HIX; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08)\n:STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP\n{\n\toprx8_16_SP = HIX; \n\t$(Z) = (HIX == 0);\n\t$(N) = (HI s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:STOP is op=0x8E\n{\n\t$(I) = 0;\n\tstop();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1\n{\n\tOP1 = X;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP\n{\n\toprx16_8_SP = X;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP\n{\n\toprx8_8_SP = X;\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1\n{ \n\top1:1 = OP1;\n\t\n\tresult:1 = A - op1;\n\tsubtractionFlags(A, op1,result);\n\tA = result;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP\n{ \n\top1:1 = oprx16_8_SP;\n\t\n\tresult:1 = A - op1;\n\tsubtractionFlags(A, op1,result);\n\tA = result;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP\n{ \n\top1:1 = oprx8_8_SP;\n\t\n\tresult:1 = A - op1;\n\tsubtractionFlags(A, op1,result);\n\tA = result;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:SWI is op=0x83\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t\n\tPush1( X );\n\t\n\tPush1( A );\n\t\n\tPush1( CCR );\n\t\n\t$(I) = 1;\n\t\n\taddr:2 = $(VECTOR_SWI);\n\tcall [addr];\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:TAP is op=0x84 \n{\n\tCCR = A;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:TAX is op=0x97 \n{\n\tX = A;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:TPA is op=0x85 \n{\n\tA = CCR;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:TSTA is op=0x4D \n{\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:TSTX is op=0x5D \n{\n\t$(Z) = (X == 0);\n\t$(N) = (X s< 0);\t\n\tV_equals_0();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1 \n{\n\top1:1 = OP1;\n\t$(Z) = (op1 == 0);\n\t$(N) = (op1 s< 0);\t\n\tV_equals_0();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP\n{\n\top1:1 = oprx8_8_SP;\n\t$(Z) = (op1 == 0);\n\t$(N) = (op1 s< 0);\t\n\tV_equals_0();\t\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:TSX is op=0x95 \n{\n\tHIX = SP + 1;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:TXA is op=0x9F \n{\n\tA = X;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08)\n:TXS is op=0x94 \n{\n\tSP = HIX - 1;\n}\n@endif\n\n@if defined(HCS08) || defined(HC08) || defined(HC05)\n:WAIT is op=0x8f \n{\n\t$(I) = 0;\n\twait();\n}\n@endif\n" }, { "path": "pypcode/processors/HCS08/data/manuals/HC05.idx", "content": "@M68HC05TB.pdf[ Rev. 2.0 1998 M68HC05 Family, Understanding Small Microcontrollers, NXP.com ]\nADC, 222\nADD, 223\nAND, 224\nASL, 225\nASLA, 225\nASLX, 225\nASR, 226\nASRA, 226\nASRX, 226\nBCC, 227\nBCLR, 228\nBCS, 229\nBEQ, 230\nBHCC, 231\nBHCS, 232\nBHI, 233\nBHS, 234\nBIH, 235\nBIL, 236\nBIT, 237\nBLO, 238\nBLS, 239\nBMC, 240\nBMI, 241\nBMS, 242\nBNE, 243\nBPL, 244\nBRA, 245\nBRCLR, 246\nBRN, 247\nBRSET, 248\nBSET, 249\nBSR, 250\nCLC, 251\nCLI, 252\nCLR, 253\nCLRA, 253\nCLRX, 253\nCMP, 254\nCOM, 255\nCOMA, 255\nCOMX, 255\nCPX, 256\nDEC, 257\nDECA, 257\nDECX, 257\nEOR, 258\nINC, 259\nINCA, 259\nINCX, 259\nJMP, 260\nJSR, 261\nLDA, 262\nLDX, 263\nLSL, 264\nLSLA, 264\nLSLX, 264\nLSR, 265\nLSRA, 265\nLSRX, 265\nMUL, 266\nNEG, 267\nNEGA, 267\nNEGX, 267\nNOP, 268\nORA, 269\nROL, 270\nROLA, 270\nROLX, 270\nROR, 271\nRORA, 271\nRORX, 271\nRSP, 272\nRTI, 273\nRTS, 274\nSBC, 275\nSEC, 276\nSEI, 277\nSTA, 278\nSTOP, 279\nSTX, 280\nSUB, 281\nSWI, 282\nTAX, 283\nTST, 284\nTSTA, 284\nTSTX, 284\nTXA, 285\nWAIT, 286\n" }, { "path": "pypcode/processors/HCS08/data/manuals/HC08.idx", "content": "@CPU08RM.pdf[ Rev. 4 02/2006 M68HC08 Microcontrollers, NXP.com ]\nADC, 63\nADD, 64\nAIS, 65\nAIX, 66\nAND, 67\nASL, 68\nASLA, 68\nASLX, 68\nASR, 69\nASRA, 69\nASRX, 69\nBCC, 70\nBCLR, 71\nBCS, 72\nBEQ, 73\nBGE, 74\nBGT, 75\nBHCC, 76\nBHCS, 77\nBHI, 78\nBHS, 79\nBIH, 80\nBIL, 81\nBIT, 82\nBLE, 83\nBLO, 84\nBLS, 85\nBLT, 86\nBMC, 87\nBMI, 88\nBMS, 89\nBNE, 90\nBPL, 91\nBRA, 92\nBRCLR, 94\nBRN, 95\nBRSET, 96\nBSET, 97\nBSR, 98\nCBEQ, 99\nCBEQA, 99\nCBEQX, 99\nCLC, 100\nCLI, 101\nCLR, 102\nCLRA, 102\nCLRX, 102\nCLRH, 102\nCMP, 103\nCOM, 104\nCOMA, 104\nCOMX, 104\nCPHX, 105\nCPX, 106\nDAA, 107\nDBNZ, 109\nDBNZA, 109\nDBNZX, 109\nDEC, 110\nDECA, 110\nDECX, 110\nDIV, 111\nEOR, 112\nINC, 113\nINCA, 113\nINCX, 113\nJMP, 114\nJSR, 115\nLDA, 116\nLDHX, 117\nLDX, 118\nLSL, 119\nLSLA, 119\nLSLX, 119\nLSR, 120\nLSRA, 120\nLSRX, 120\nMOV, 121\nMUL, 122\nNEG, 123\nNEGA, 123\nNEGX, 123\nNOP, 124\nNSA, 125\nORA, 126\nPSHA, 127\nPSHH, 128\nPSHX, 129\nPULA, 130\nPULH, 131\nPULX, 132\nROL, 133\nROLA, 133\nROLX, 133\nROR, 134\nRORA, 134\nRORX, 134\nRSP, 135\nRTI, 136\nRTS, 137\nSBC, 138\nSEC, 139\nSEI, 140\nSTA, 141\nSTHX, 142\nSTOP, 143\nSTX, 144\nSUB, 145\nSWI, 146\nTAP, 147\nTAX, 148\nTPA, 149\nTST, 150\nTSTA, 150\nTSTX, 150\nTSX, 151\nTXA, 152\nTXS, 153\nWAIT, 154\n" }, { "path": "pypcode/processors/HCS08/data/manuals/HCS08.idx", "content": "@HCS08RMV1.pdf[ Rev. 2 05/2007 M68HCS08 Microcontrollers, NXP.com ]\nADC, 201\nADD, 202\nAIS, 203\nAIX, 204\nAND, 205\nASL, 206\nASLA, 206\nASLX, 206\nASR, 207\nASRA, 207\nASRX, 207\nBCC, 208\nBCLR, 209\nBCS, 210\nBEQ, 211\nBGE, 212\nBGND, 213\nBGT, 214\nBHCC, 215\nBHCS, 216\nBHI, 217\nBHS, 218\nBIH, 219\nBIL, 220\nBIT, 221\nBLE, 222\nBLO, 223\nBLS, 224\nBLT, 225\nBMC, 226\nBMI, 227\nBMS, 228\nBNE, 229\nBPL, 230\nBRA, 231\nBRCLR, 233\nBRN, 234\nBRSET, 235\nBSET, 236\nBSR, 237\nCBEQ, 238\nCBEQA, 238\nCBEQX, 238\nCLC, 239\nCLI, 240\nCLR, 241\nCLRA, 241\nCLRX, 241\nCLRH, 241\nCMP, 242\nCOM, 243\nCOMA, 243\nCOMX, 243\nCPHX, 244\nCPX, 245\nDAA, 246\nDBNZ, 248\nDBNZA, 248\nDBNZX, 248\nDEC, 249\nDECA, 249\nDECX, 249\nDIV, 250\nEOR, 251\nINC, 252\nINCA, 252\nINCX, 252\nJMP, 253\nJSR, 254\nLDA, 255\nLDHX, 256\nLDX, 257\nLSL, 258\nLSLA, 258\nLSLX, 258\nLSR, 259\nLSRA, 259\nLSRX, 259\nMOV, 260\nMUL, 261\nNEG, 262\nNEGA, 262\nNEGX, 262\nNOP, 263\nNSA, 264\nORA, 265\nPSHA, 266\nPSHH, 267\nPSHX, 268\nPULA, 269\nPULH, 270\nPULX, 271\nROL, 272\nROLA, 272\nROLX, 272\nROR, 273\nRORA, 273\nRORX, 273\nRSP, 274\nRTI, 275\nRTS, 276\nSBC, 277\nSEC, 278\nSEI, 279\nSTA, 280\nSTHX, 281\nSTOP, 282\nSTX, 283\nSUB, 284\nSWI, 285\nTAP, 286\nTAX, 287\nTPA, 288\nTST, 289\nTSTA, 289\nTSTX, 289\nTSX, 290\nTXA, 291\nTXS, 292\nWAIT, 293\n" }, { "path": "pypcode/processors/HCS08/data/test-vectors/HC05_tv.s", "content": ".hc05\n\n.area\tDIRECT (PAG)\n;.setdp\t0, DIRECT\n\n;low_data1:\n;.ds\t1\n\n.area PROGRAM\t(ABS)\n.org\t0x80\n\nLOW_SUB_TEST:\n\tRTS\n\n\n.org\t0x2000\n\nHIGH_SUB_TEST:\n\tRTS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1\n\n\tADC #0xFE\n\tADC *0xFE\n\tADC 0xFEDC\n\tADC 0xFEDC,X\n\tADC 0xFE,X\n\tADC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP\n\n;\tADC 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP\n\n;\tADC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1\n\n\tADD #0xFE\n\tADD *0xFE\n\tADD 0xFEDC\n\tADD 0xFEDC,X\n\tADD 0xFE,X\n\tADD ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP\n\n;\tADD 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP\n\n;\tADD 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AIS iopr8is is op=0xA7; iopr8is\n\n;\tAIS #0x7F\n;\tAIS #-0x7F\n\n; @if defined(HCS08) || defined(HC08)\n; : AIX iopr8is is op=0xAF; iopr8is\n\n;\tAIX #0x7F\n;\tAIX #-0x7F\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1\n\n\tAND #0xFE\n\tAND *0xFE\n\tAND 0xFEDC\n\tAND 0xFEDC,X\n\tAND 0xFE,X\n\tAND ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP\n\n;\tAND 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP\n\n;\tAND 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASLA is op=0x48\n\n\tASLA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASLX is op=0x58\n\n\tASLX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1\n\n\tASL *0xFE\n\tASL 0xFE,X\n\tASL ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP\n\n;\tASL 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASRA is op=0x47\n\n\tASRA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASRX is op=0x57\n\n\tASRX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1\n\n\tASR *0xFE\n\tASR 0xFE,X\n\tASR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP\n\n;\tASR 0xFE,S\n\n\nBACKWARDS1:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCC REL is op=0x24; REL\n\n\tBCC BACKWARDS1\n\tBCC FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8\n\n\tBCLR #0, *0xFE\n\tBCLR #1, *0xED\n\tBCLR #2, *0xDC\n\tBCLR #3, *0xCB\n\tBCLR #4, *0xBA\n\tBCLR #5, *0xA9\n\tBCLR #6, *0x98\n\tBCLR #7, *0x87\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCS REL is op=0x25; REL\n\n\tBCS BACKWARDS1\n\tBCS FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BEQ REL is op=0x27; REL\n\n\tBEQ BACKWARDS1\n\tBEQ FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BGE REL is op=0x90; REL\n\n;\tBGE BACKWARDS1\n;\tBGE FORWARDS1\n\n\n; @if defined(HCS08)\n; : BGND is op=0x82\n\n;\tBGND\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BGT REL is op=0x92; REL\n\n;\tBGT BACKWARDS1\n;\tBGT FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHCC REL is op=0x28; REL\n\n\tBHCC BACKWARDS1\n\tBHCC FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHCS REL is op=0x29; REL\n\n\tBHCS BACKWARDS1\n\tBHCS FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHI REL is op=0x22; REL\n\n\tBHI BACKWARDS1\n\tBHI FORWARDS1\n\n\n; :BHS REL\tis op=0x24; REL\t\tSee BCC\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIH REL is op=0x2F; REL\n\n\tBIH BACKWARDS1\n\tBIH FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIL REL is op=0x2E; REL\n\n\tBIL BACKWARDS1\n\tBIL FORWARDS1\n\n\nFORWARDS1:\nBACKWARDS2:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1\n\n\tBIT #0xFE\n\tBIT *0xFE\n\tBIT 0xFEDC\n\tBIT 0xFEDC,X\n\tBIT 0xFE,X\n\tBIT ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP\n\n;\tBIT 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP\n\n;\tBIT 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BLE REL is op=0x93; REL\n\n;\tBLE BACKWARDS2\n;\tBLE FORWARDS2\n\n\n; :BLO REL\tis op=0x25; REL\t\tsee BCS\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BLS REL is op=0x23; REL\n\n\tBLS BACKWARDS2\n\tBLS FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BLT REL is op=0x91; REL\n\n;\tBLT BACKWARDS2\n;\tBLT FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMC REL is op=0x2C; REL\n\n\tBMC BACKWARDS2\n\tBMC FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMI REL is op=0x2B; REL\n\n\tBMI BACKWARDS2\n\tBMI FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMS REL is op=0x2D; REL\n\n\tBMS BACKWARDS2\n\tBMS FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BNE REL is op=0x26; REL\n\n\tBNE BACKWARDS2\n\tBNE FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BPL REL is op=0x2A; REL\n\n\tBPL BACKWARDS2\n\tBPL FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRA REL is op=0x20; REL\n\n\tBRA BACKWARDS2\n\tBRA FORWARDS2\n\n\nFORWARDS2:\nBACKWARDS3:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL\n\n\tBRCLR #0, *0xFE,BACKWARDS3\n\tBRCLR #1, *0xED,BACKWARDS3\n\tBRCLR #2, *0xDC,BACKWARDS3\n\tBRCLR #3, *0xCB,BACKWARDS3\n\tBRCLR #4, *0xBA,BACKWARDS3\n\tBRCLR #5, *0xA9,BACKWARDS3\n\tBRCLR #6, *0x98,BACKWARDS3\n\tBRCLR #7, *0x87,BACKWARDS3\n\n\tBRCLR #0, *0xFE,FORWARDS3\n\tBRCLR #1, *0xED,FORWARDS3\n\tBRCLR #2, *0xDC,FORWARDS3\n\tBRCLR #3, *0xCB,FORWARDS3\n\tBRCLR #4, *0xBA,FORWARDS3\n\tBRCLR #5, *0xA9,FORWARDS3\n\tBRCLR #6, *0x98,FORWARDS3\n\tBRCLR #7, *0x87,FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; branch never is a two-byte nop\n; : BRN REL is op=0x21; REL\n\n\tBRN BACKWARDS3\n\tBRN FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL\n\n\tBRSET #0, *0xFE,BACKWARDS3\n\tBRSET #1, *0xED,BACKWARDS3\n\tBRSET #2, *0xDC,BACKWARDS3\n\tBRSET #3, *0xCB,BACKWARDS3\n\tBRSET #4, *0xBA,BACKWARDS3\n\tBRSET #5, *0xA9,BACKWARDS3\n\tBRSET #6, *0x98,BACKWARDS3\n\tBRSET #7, *0x87,BACKWARDS3\n\n\tBRSET #0, *0xFE,FORWARDS3\n\tBRSET #1, *0xED,FORWARDS3\n\tBRSET #2, *0xDC,FORWARDS3\n\tBRSET #3, *0xCB,FORWARDS3\n\tBRSET #4, *0xBA,FORWARDS3\n\tBRSET #5, *0xA9,FORWARDS3\n\tBRSET #6, *0x98,FORWARDS3\n\tBRSET #7, *0x87,FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8\n\n\tBSET #0, *0xFE\n\tBSET #1, *0xED\n\tBSET #2, *0xDC\n\tBSET #3, *0xCB\n\tBSET #4, *0xBA\n\tBSET #5, *0xA9\n\tBSET #6, *0x98\n\tBSET #7, *0x87\n\nFORWARDS3:\nBACKWARDS4:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BSR REL is op=0xAD; REL\n\n\tBSR BACKWARDS4\n\tBSR FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL\n\n;\tCBEQ *0xFE, BACKWARDS4\n;\tCBEQ *0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL\n\n;\tCBEQA #0xFE, BACKWARDS4\n;\tCBEQA #0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL\n\n;\tCBEQX #0xFE, BACKWARDS4\n;\tCBEQX #0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ oprx8, X\"+\", REL is (op=0x61) & X; oprx8; REL\n\n;\tCBEQ *0xFE, X+, BACKWARDS4\n;\tCBEQ *0xFE, X+, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ \",\"X\"+\", REL is (op=0x71) & X; REL\n\n;\tCBEQ ,X+, BACKWARDS4\n;\tCBEQ ,X+, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL\n\n;\tCBEQ 0xFE,S, BACKWARDS4\n;\tCBEQ 0xFE,S, FORWARDS4\n\n\nFORWARDS4:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLC is op=0x98\n\n\tCLC\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLI is op=0x9A\n\n\tCLI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLRA is op=0x4F\n\n\tCLRA\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLRX is op=0x5F\n\n\tCLRX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CLRH is op=0x8C\n\n;\tCLRH\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1\n\n\tCLR *0xFE\n\tCLR 0xFE,X\n\tCLR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP\n\n;\tCLR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1\n\n\tCMP #0xFE\n\tCMP *0xFE\n\tCMP 0xFEDC\n\tCMP 0xFEDC,X\n\tCMP 0xFE,X\n\tCMP ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP\n\n;\tCMP 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP\n\n;\tCMP 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COMA is op=0x43\n\n\tCOMA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COMX is op=0x53\n\n\tCOMX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1\n\n\tCOM *0xFE\n\tCOM 0xFE,X\n\tCOM ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP\n\n;\tCOM 0xFE,S\n\n\n; @if defined(HCS08)\n; : CPHX opr16a_16 is (op=0x3E); opr16a_16\n\n;\tCPHX 0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPHX iopr16i is (op=0x65); iopr16i\n\n;\tCPHX #0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPHX opr8a_16 is (op=0x75); opr8a_16\n\n;\tCPHX *0xFE\n\n\n; @if defined(HCS08)\n; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP\n\n;\tCPHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1\n\n\tCPX #0xFE\n\tCPX *0xFE\n\tCPX 0xFEDC\n\tCPX 0xFEDC,X\n\tCPX 0xFE,X\n\tCPX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP\n\n;\tCPX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP\n\n;\tCPX 0xFE,S\n\nBACKWARDS5:\n\n; @if defined(HCS08) || defined(HC08)\n; : DAA is op=0x72\n\n;\tDAA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZA REL is op=0x4B; REL\n\n;\tDBNZA BACKWARDS5\n;\tDBNZA FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZX REL is op=0x5B; REL\n\n;\tDBNZX BACKWARDS5\n;\tDBNZX FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL\n\n;\tDBNZ *0xFE, BACKWARDS5\n;\tDBNZ 0xFE,X, BACKWARDS5\n;\tDBNZ ,X, BACKWARDS5\n\n;\tDBNZ *0xFE, FORWARDS5\n;\tDBNZ 0xFE,X, FORWARDS5\n;\tDBNZ ,X, FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL\n\n;\tDBNZ 0xFE,S, BACKWARDS5\n;\tDBNZ 0xFE,S, FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DECA is op=0x4A\n\n\tDECA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DECX is op=0x5A\n\n\tDECX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1\n\n\tDEC *0xFE\n\tDEC 0xFE,X\n\tDEC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP\n\n;\tDEC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DIV is op=0x52\n\n;\tDIV\n\n\nFORWARDS5:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1\n\n\tEOR #0xFE\n\tEOR *0xFE\n\tEOR 0xFEDC\n\tEOR 0xFEDC,X\n\tEOR 0xFE,X\n\tEOR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP\n\n;\tEOR 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP\n\n;\tEOR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INCA is op=0x4C\n\n\tINCA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INCX is op=0x5C\n\n\tINCX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1\n\n\tINC *0xFE\n\tINC 0xFE,X\n\tINC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP\n\n;\tINC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR\n\n\tJMP *LOW_SUB_TEST\n\tJMP HIGH_SUB_TEST\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI\n\n\tJMP 0xFEDC,X\n\tJMP 0xFE,X\n\tJMP ,X\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR\n\n\tJSR *LOW_SUB_TEST\n\tJSR HIGH_SUB_TEST\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI\n\n\tJSR 0xFEDC,X\n\tJSR 0xFE,X\n\tJSR ,X\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1\n\n\tLDA #0xFE\n\tLDA *0xFE\n\tLDA 0xFEDC\n\tLDA 0xFEDC,X\n\tLDA 0xFE,X\n\tLDA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP\n\n;\tLDA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP\n\n;\tLDA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDHX iopr16i is (op=0x45); iopr16i\n\n;\tLDHX #0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDHX opr8a_16 is (op=0x55); opr8a_16\n\n;\tLDHX *0xFE\n\n\n; @if defined(HCS08)\n; : LDHX opr16a_16 is (op=0x32); opr16a_16\n\n;\tLDHX 0xFEDC\n\n\n; @if defined(HCS08)\n; : LDHX \",\"X is (op16=0x9EAE) & X\n\n;\tLDHX ,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X\n\n;\tLDHX 0xFEDC,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X\n\n;\tLDHX 0xFE,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP\n\n;\tLDHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1\n\n\tLDX #0xFE\n\tLDX *0xFE\n\tLDX 0xFEDC\n\tLDX 0xFEDC,X\n\tLDX 0xFE,X\n\tLDX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP\n\n;\tLDX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP\n\n;\tLDX 0xFE,S\n\n\n; ## Logical Shift left is same as arithmetic shift left\n; :LSLA\t\tis op=0x48\n; :LSLX\t\tis op=0x58\n; :LSL OP1\tis (op=0x38 | op=0x68 | op=0x78) ... & OP1\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSRA is op=0x44\n\n\tLSRA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSRX is op=0x54\n\n\tLSRX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1\n\n\tLSR *0xFE\n\tLSR 0xFE,X\n\tLSR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP\n\n;\tLSR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV opr8a_8, op2_opr8a\tis (op=0x4E); opr8a_8; op2_opr8a\n\n;\tMOV *0xFE, *0x97\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV opr8a_8, X\"+\" is (op=0x5E); opr8a_8 & X\n\n;\tMOV 0xFE, X+\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a\n\n;\tMOV #0xFE, *0x97\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV \",\"X\"+,\" op2_opr8a is (op=0x7E) & X; op2_opr8a\n\n;\tMOV ,X+, *0xFE\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : MUL is op=0x42\n\n\tMUL\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEGA is op=0x40\n\n\tNEGA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEGX is op=0x50\n\n\tNEGX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1\n\n\tNEG *0xFE\n\tNEG 0xFE,X\n\tNEG ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP\n\n;\tNEG 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NOP is op = 0x9D\n\n\tNOP\n\n\n; @if defined(HCS08) || defined(HC08)\n; : NSA is op = 0x62\n\n;\tNSA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1\n\n\tORA #0xFE\n\tORA *0xFE\n\tORA 0xFEDC\n\tORA 0xFEDC,X\n\tORA 0xFE,X\n\tORA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP\n\n;\tORA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP\n\n;\tORA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHA is op = 0x87\n\n;\tPSHA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHH is op = 0x8B\n\n;\tPSHH\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHX is op = 0x89\n\n;\tPSHX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULA is op = 0x86\n\n;\tPULA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULH is op = 0x8A\n\n;\tPULH\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULX is op = 0x88\n\n;\tPULX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROLA is op=0x49\n\n\tROLA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROLX is op=0x59\n\n\tROLX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1\n\n\tROL *0xFE\n\tROL 0xFE,X\n\tROL ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP\n\n;\tROL 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RORA is op=0x46\n\n\tRORA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RORX is op=0x56\n\n\tRORX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1\n\n\tROR *0xFE\n\tROR 0xFE,X\n\tROR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP\n\n;\tROR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RSP is op = 0x9C\n\n\tRSP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RTI is op = 0x80\n\n\tRTI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RTS is op = 0x81\n\n\tRTS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1\n\n\tSBC #0xFE\n\tSBC *0xFE\n\tSBC 0xFEDC\n\tSBC 0xFEDC,X\n\tSBC 0xFE,X\n\tSBC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP\n\n;\tSBC 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP\n\n;\tSBC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SEC is op = 0x99\n\n\tSEC\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SEI is op = 0x9B\n\n\tSEI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1\n\n\tSTA *0xFE\n\tSTA 0xFEDC\n\tSTA 0xFEDC,X\n\tSTA 0xFE,X\n\tSTA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP\n\n;\tSTA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP\n\n;\tSTA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STHX opr8a_16 is (op=0x35); opr8a_16\n\n;\tSTHX *0xFE\n\n\n; @if defined(HCS08)\n; : STHX opr16a_16 is (op=0x96); opr16a_16\n\n;\tSTHX 0xFEDC\n\n\n; @if defined(HCS08)\n; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP\n\n;\tSTHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STOP is op=0x8E\n\n\tSTOP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1\n\n\tSTX *0xFE\n\tSTX 0xFEDC\n\tSTX 0xFEDC,X\n\tSTX 0xFE,X\n\tSTX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP\n\n;\tSTX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP\n\n;\tSTX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1\n\n\tSUB #0xFE\n\tSUB *0xFE\n\tSUB 0xFEDC\n\tSUB 0xFEDC,X\n\tSUB 0xFE,X\n\tSUB ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP\n\n;\tSUB 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP\n\n;\tSUB 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SWI is op=0x83\n\n\tSWI\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TAP is op=0x84\n\n;\tTAP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TAX is op=0x97\n\n\tTAX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TPA is op=0x85\n\n;\tTPA\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TSTA is op=0x4D\n\n\tTSTA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TSTX is op=0x5D\n\n\tTSTX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1\n\n\tTST *0xFE\n\tTST 0xFE,X\n\tTST ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP\n\n;\tTST 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TSX is op=0x95\n\n;\tTSX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TXA is op=0x9F\n\n\tTXA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TXS is op=0x94\n\n;\tTXS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : WAIT is op=0x8f\n\n\tWAIT\n\n\nHERE:\n\tBRA\tHERE\n" }, { "path": "pypcode/processors/HCS08/data/test-vectors/HC08_tv.s", "content": ".hc08\n\n.area\tDIRECT (PAG)\n;.setdp\t0, DIRECT\n\n;low_data1:\n;.ds\t1\n\n.area PROGRAM\t(ABS)\n.org\t0x80\n\nLOW_SUB_TEST:\n\tRTS\n\n\n.org\t0x2000\n\nHIGH_SUB_TEST:\n\tRTS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1\n\n\tADC #0xFE\n\tADC *0xFE\n\tADC 0xFEDC\n\tADC 0xFEDC,X\n\tADC 0xFE,X\n\tADC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP\n\n\tADC 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP\n\n\tADC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1\n\n\tADD #0xFE\n\tADD *0xFE\n\tADD 0xFEDC\n\tADD 0xFEDC,X\n\tADD 0xFE,X\n\tADD ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP\n\n\tADD 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP\n\n\tADD 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AIS iopr8is is op=0xA7; iopr8is\n\n\tAIS #0x7F\n\tAIS #-0x7F\n\n; @if defined(HCS08) || defined(HC08)\n; : AIX iopr8is is op=0xAF; iopr8is\n\n\tAIX #0x7F\n\tAIX #-0x7F\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1\n\n\tAND #0xFE\n\tAND *0xFE\n\tAND 0xFEDC\n\tAND 0xFEDC,X\n\tAND 0xFE,X\n\tAND ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP\n\n\tAND 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP\n\n\tAND 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASLA is op=0x48\n\n\tASLA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASLX is op=0x58\n\n\tASLX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1\n\n\tASL *0xFE\n\tASL 0xFE,X\n\tASL ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP\n\n\tASL 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASRA is op=0x47\n\n\tASRA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASRX is op=0x57\n\n\tASRX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1\n\n\tASR *0xFE\n\tASR 0xFE,X\n\tASR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP\n\n\tASR 0xFE,S\n\n\nBACKWARDS1:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCC REL is op=0x24; REL\n\n\tBCC BACKWARDS1\n\tBCC FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8\n\n\tBCLR #0, *0xFE\n\tBCLR #1, *0xED\n\tBCLR #2, *0xDC\n\tBCLR #3, *0xCB\n\tBCLR #4, *0xBA\n\tBCLR #5, *0xA9\n\tBCLR #6, *0x98\n\tBCLR #7, *0x87\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCS REL is op=0x25; REL\n\n\tBCS BACKWARDS1\n\tBCS FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BEQ REL is op=0x27; REL\n\n\tBEQ BACKWARDS1\n\tBEQ FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BGE REL is op=0x90; REL\n\n\tBGE BACKWARDS1\n\tBGE FORWARDS1\n\n\n; @if defined(HCS08)\n; : BGND is op=0x82\n\n;\tBGND\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BGT REL is op=0x92; REL\n\n\tBGT BACKWARDS1\n\tBGT FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHCC REL is op=0x28; REL\n\n\tBHCC BACKWARDS1\n\tBHCC FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHCS REL is op=0x29; REL\n\n\tBHCS BACKWARDS1\n\tBHCS FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHI REL is op=0x22; REL\n\n\tBHI BACKWARDS1\n\tBHI FORWARDS1\n\n\n; :BHS REL\tis op=0x24; REL\t\tSee BCC\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIH REL is op=0x2F; REL\n\n\tBIH BACKWARDS1\n\tBIH FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIL REL is op=0x2E; REL\n\n\tBIL BACKWARDS1\n\tBIL FORWARDS1\n\n\nFORWARDS1:\nBACKWARDS2:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1\n\n\tBIT #0xFE\n\tBIT *0xFE\n\tBIT 0xFEDC\n\tBIT 0xFEDC,X\n\tBIT 0xFE,X\n\tBIT ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP\n\n\tBIT 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP\n\n\tBIT 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BLE REL is op=0x93; REL\n\n\tBLE BACKWARDS2\n\tBLE FORWARDS2\n\n\n; :BLO REL\tis op=0x25; REL\t\tsee BCS\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BLS REL is op=0x23; REL\n\n\tBLS BACKWARDS2\n\tBLS FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BLT REL is op=0x91; REL\n\n\tBLT BACKWARDS2\n\tBLT FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMC REL is op=0x2C; REL\n\n\tBMC BACKWARDS2\n\tBMC FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMI REL is op=0x2B; REL\n\n\tBMI BACKWARDS2\n\tBMI FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMS REL is op=0x2D; REL\n\n\tBMS BACKWARDS2\n\tBMS FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BNE REL is op=0x26; REL\n\n\tBNE BACKWARDS2\n\tBNE FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BPL REL is op=0x2A; REL\n\n\tBPL BACKWARDS2\n\tBPL FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRA REL is op=0x20; REL\n\n\tBRA BACKWARDS2\n\tBRA FORWARDS2\n\n\nFORWARDS2:\nBACKWARDS3:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL\n\n\tBRCLR #0, *0xFE,BACKWARDS3\n\tBRCLR #1, *0xED,BACKWARDS3\n\tBRCLR #2, *0xDC,BACKWARDS3\n\tBRCLR #3, *0xCB,BACKWARDS3\n\tBRCLR #4, *0xBA,BACKWARDS3\n\tBRCLR #5, *0xA9,BACKWARDS3\n\tBRCLR #6, *0x98,BACKWARDS3\n\tBRCLR #7, *0x87,BACKWARDS3\n\n\tBRCLR #0, *0xFE,FORWARDS3\n\tBRCLR #1, *0xED,FORWARDS3\n\tBRCLR #2, *0xDC,FORWARDS3\n\tBRCLR #3, *0xCB,FORWARDS3\n\tBRCLR #4, *0xBA,FORWARDS3\n\tBRCLR #5, *0xA9,FORWARDS3\n\tBRCLR #6, *0x98,FORWARDS3\n\tBRCLR #7, *0x87,FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; branch never is a two-byte nop\n; : BRN REL is op=0x21; REL\n\n\tBRN BACKWARDS3\n\tBRN FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL\n\n\tBRSET #0, *0xFE,BACKWARDS3\n\tBRSET #1, *0xED,BACKWARDS3\n\tBRSET #2, *0xDC,BACKWARDS3\n\tBRSET #3, *0xCB,BACKWARDS3\n\tBRSET #4, *0xBA,BACKWARDS3\n\tBRSET #5, *0xA9,BACKWARDS3\n\tBRSET #6, *0x98,BACKWARDS3\n\tBRSET #7, *0x87,BACKWARDS3\n\n\tBRSET #0, *0xFE,FORWARDS3\n\tBRSET #1, *0xED,FORWARDS3\n\tBRSET #2, *0xDC,FORWARDS3\n\tBRSET #3, *0xCB,FORWARDS3\n\tBRSET #4, *0xBA,FORWARDS3\n\tBRSET #5, *0xA9,FORWARDS3\n\tBRSET #6, *0x98,FORWARDS3\n\tBRSET #7, *0x87,FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8\n\n\tBSET #0, *0xFE\n\tBSET #1, *0xED\n\tBSET #2, *0xDC\n\tBSET #3, *0xCB\n\tBSET #4, *0xBA\n\tBSET #5, *0xA9\n\tBSET #6, *0x98\n\tBSET #7, *0x87\n\nFORWARDS3:\nBACKWARDS4:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BSR REL is op=0xAD; REL\n\n\tBSR BACKWARDS4\n\tBSR FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL\n\n\tCBEQ *0xFE, BACKWARDS4\n\tCBEQ *0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL\n\n\tCBEQA #0xFE, BACKWARDS4\n\tCBEQA #0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL\n\n\tCBEQX #0xFE, BACKWARDS4\n\tCBEQX #0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ oprx8, X\"+\", REL is (op=0x61) & X; oprx8; REL\n\n\tCBEQ *0xFE, X+, BACKWARDS4\n\tCBEQ *0xFE, X+, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ \",\"X\"+\", REL is (op=0x71) & X; REL\n\n\tCBEQ ,X+, BACKWARDS4\n\tCBEQ ,X+, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL\n\n\tCBEQ 0xFE,S, BACKWARDS4\n\tCBEQ 0xFE,S, FORWARDS4\n\n\nFORWARDS4:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLC is op=0x98\n\n\tCLC\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLI is op=0x9A\n\n\tCLI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLRA is op=0x4F\n\n\tCLRA\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLRX is op=0x5F\n\n\tCLRX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CLRH is op=0x8C\n\n\tCLRH\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1\n\n\tCLR *0xFE\n\tCLR 0xFE,X\n\tCLR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP\n\n\tCLR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1\n\n\tCMP #0xFE\n\tCMP *0xFE\n\tCMP 0xFEDC\n\tCMP 0xFEDC,X\n\tCMP 0xFE,X\n\tCMP ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP\n\n\tCMP 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP\n\n\tCMP 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COMA is op=0x43\n\n\tCOMA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COMX is op=0x53\n\n\tCOMX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1\n\n\tCOM *0xFE\n\tCOM 0xFE,X\n\tCOM ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP\n\n\tCOM 0xFE,S\n\n\n; @if defined(HCS08)\n; : CPHX opr16a_16 is (op=0x3E); opr16a_16\n\n;\tCPHX 0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPHX iopr16i is (op=0x65); iopr16i\n\n\tCPHX #0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPHX opr8a_16 is (op=0x75); opr8a_16\n\n\tCPHX *0xFE\n\n\n; @if defined(HCS08)\n; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP\n\n;\tCPHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1\n\n\tCPX #0xFE\n\tCPX *0xFE\n\tCPX 0xFEDC\n\tCPX 0xFEDC,X\n\tCPX 0xFE,X\n\tCPX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP\n\n\tCPX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP\n\n\tCPX 0xFE,S\n\nBACKWARDS5:\n\n; @if defined(HCS08) || defined(HC08)\n; : DAA is op=0x72\n\n\tDAA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZA REL is op=0x4B; REL\n\n\tDBNZA BACKWARDS5\n\tDBNZA FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZX REL is op=0x5B; REL\n\n\tDBNZX BACKWARDS5\n\tDBNZX FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL\n\n\tDBNZ *0xFE, BACKWARDS5\n\tDBNZ 0xFE,X, BACKWARDS5\n\tDBNZ ,X, BACKWARDS5\n\n\tDBNZ *0xFE, FORWARDS5\n\tDBNZ 0xFE,X, FORWARDS5\n\tDBNZ ,X, FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL\n\n\tDBNZ 0xFE,S, BACKWARDS5\n\tDBNZ 0xFE,S, FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DECA is op=0x4A\n\n\tDECA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DECX is op=0x5A\n\n\tDECX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1\n\n\tDEC *0xFE\n\tDEC 0xFE,X\n\tDEC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP\n\n\tDEC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DIV is op=0x52\n\n\tDIV\n\n\nFORWARDS5:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1\n\n\tEOR #0xFE\n\tEOR *0xFE\n\tEOR 0xFEDC\n\tEOR 0xFEDC,X\n\tEOR 0xFE,X\n\tEOR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP\n\n\tEOR 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP\n\n\tEOR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INCA is op=0x4C\n\n\tINCA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INCX is op=0x5C\n\n\tINCX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1\n\n\tINC *0xFE\n\tINC 0xFE,X\n\tINC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP\n\n\tINC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR\n\n\tJMP *LOW_SUB_TEST\n\tJMP HIGH_SUB_TEST\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI\n\n\tJMP 0xFEDC,X\n\tJMP 0xFE,X\n\tJMP ,X\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR\n\n\tJSR *LOW_SUB_TEST\n\tJSR HIGH_SUB_TEST\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI\n\n\tJSR 0xFEDC,X\n\tJSR 0xFE,X\n\tJSR ,X\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1\n\n\tLDA #0xFE\n\tLDA *0xFE\n\tLDA 0xFEDC\n\tLDA 0xFEDC,X\n\tLDA 0xFE,X\n\tLDA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP\n\n\tLDA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP\n\n\tLDA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDHX iopr16i is (op=0x45); iopr16i\n\n\tLDHX #0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDHX opr8a_16 is (op=0x55); opr8a_16\n\n\tLDHX *0xFE\n\n\n; @if defined(HCS08)\n; : LDHX opr16a_16 is (op=0x32); opr16a_16\n\n;\tLDHX 0xFEDC\n\n\n; @if defined(HCS08)\n; : LDHX \",\"X is (op16=0x9EAE) & X\n\n;\tLDHX ,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X\n\n;\tLDHX 0xFEDC,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X\n\n;\tLDHX 0xFE,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP\n\n;\tLDHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1\n\n\tLDX #0xFE\n\tLDX *0xFE\n\tLDX 0xFEDC\n\tLDX 0xFEDC,X\n\tLDX 0xFE,X\n\tLDX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP\n\n\tLDX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP\n\n\tLDX 0xFE,S\n\n\n; ## Logical Shift left is same as arithmetic shift left\n; :LSLA\t\tis op=0x48\n; :LSLX\t\tis op=0x58\n; :LSL OP1\tis (op=0x38 | op=0x68 | op=0x78) ... & OP1\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSRA is op=0x44\n\n\tLSRA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSRX is op=0x54\n\n\tLSRX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1\n\n\tLSR *0xFE\n\tLSR 0xFE,X\n\tLSR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP\n\n\tLSR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV opr8a_8, op2_opr8a\tis (op=0x4E); opr8a_8; op2_opr8a\n\n\tMOV *0xFE, *0x97\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV opr8a_8, X\"+\" is (op=0x5E); opr8a_8 & X\n\n\tMOV 0xFE, X+\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a\n\n\tMOV #0xFE, *0x97\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV \",\"X\"+,\" op2_opr8a is (op=0x7E) & X; op2_opr8a\n\n\tMOV ,X+, *0xFE\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : MUL is op=0x42\n\n\tMUL\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEGA is op=0x40\n\n\tNEGA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEGX is op=0x50\n\n\tNEGX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1\n\n\tNEG *0xFE\n\tNEG 0xFE,X\n\tNEG ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP\n\n\tNEG 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NOP is op = 0x9D\n\n\tNOP\n\n\n; @if defined(HCS08) || defined(HC08)\n; : NSA is op = 0x62\n\n\tNSA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1\n\n\tORA #0xFE\n\tORA *0xFE\n\tORA 0xFEDC\n\tORA 0xFEDC,X\n\tORA 0xFE,X\n\tORA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP\n\n\tORA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP\n\n\tORA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHA is op = 0x87\n\n\tPSHA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHH is op = 0x8B\n\n\tPSHH\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHX is op = 0x89\n\n\tPSHX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULA is op = 0x86\n\n\tPULA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULH is op = 0x8A\n\n\tPULH\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULX is op = 0x88\n\n\tPULX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROLA is op=0x49\n\n\tROLA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROLX is op=0x59\n\n\tROLX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1\n\n\tROL *0xFE\n\tROL 0xFE,X\n\tROL ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP\n\n\tROL 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RORA is op=0x46\n\n\tRORA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RORX is op=0x56\n\n\tRORX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1\n\n\tROR *0xFE\n\tROR 0xFE,X\n\tROR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP\n\n\tROR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RSP is op = 0x9C\n\n\tRSP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RTI is op = 0x80\n\n\tRTI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RTS is op = 0x81\n\n\tRTS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1\n\n\tSBC #0xFE\n\tSBC *0xFE\n\tSBC 0xFEDC\n\tSBC 0xFEDC,X\n\tSBC 0xFE,X\n\tSBC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP\n\n\tSBC 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP\n\n\tSBC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SEC is op = 0x99\n\n\tSEC\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SEI is op = 0x9B\n\n\tSEI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1\n\n\tSTA *0xFE\n\tSTA 0xFEDC\n\tSTA 0xFEDC,X\n\tSTA 0xFE,X\n\tSTA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP\n\n\tSTA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP\n\n\tSTA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STHX opr8a_16 is (op=0x35); opr8a_16\n\n\tSTHX *0xFE\n\n\n; @if defined(HCS08)\n; : STHX opr16a_16 is (op=0x96); opr16a_16\n\n;\tSTHX 0xFEDC\n\n\n; @if defined(HCS08)\n; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP\n\n;\tSTHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STOP is op=0x8E\n\n\tSTOP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1\n\n\tSTX *0xFE\n\tSTX 0xFEDC\n\tSTX 0xFEDC,X\n\tSTX 0xFE,X\n\tSTX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP\n\n\tSTX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP\n\n\tSTX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1\n\n\tSUB #0xFE\n\tSUB *0xFE\n\tSUB 0xFEDC\n\tSUB 0xFEDC,X\n\tSUB 0xFE,X\n\tSUB ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP\n\n\tSUB 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP\n\n\tSUB 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SWI is op=0x83\n\n\tSWI\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TAP is op=0x84\n\n\tTAP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TAX is op=0x97\n\n\tTAX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TPA is op=0x85\n\n\tTPA\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TSTA is op=0x4D\n\n\tTSTA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TSTX is op=0x5D\n\n\tTSTX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1\n\n\tTST *0xFE\n\tTST 0xFE,X\n\tTST ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP\n\n\tTST 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TSX is op=0x95\n\n\tTSX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TXA is op=0x9F\n\n\tTXA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TXS is op=0x94\n\n\tTXS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : WAIT is op=0x8f\n\n\tWAIT\n\n\nHERE:\n\tBRA\tHERE\n" }, { "path": "pypcode/processors/HCS08/data/test-vectors/HCS08_tv.s", "content": ".hcs08\n\n.area\tDIRECT (PAG)\n;.setdp\t0, DIRECT\n\n;low_data1:\n;.ds\t1\n\n.area PROGRAM\t(ABS)\n.org\t0x80\n\nLOW_SUB_TEST:\n\tRTS\n\n\n.org\t0x2000\n\nHIGH_SUB_TEST:\n\tRTS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1\n\n\tADC #0xFE\n\tADC *0xFE\n\tADC 0xFEDC\n\tADC 0xFEDC,X\n\tADC 0xFE,X\n\tADC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP\n\n\tADC 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP\n\n\tADC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1\n\n\tADD #0xFE\n\tADD *0xFE\n\tADD 0xFEDC\n\tADD 0xFEDC,X\n\tADD 0xFE,X\n\tADD ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP\n\n\tADD 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP\n\n\tADD 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AIS iopr8is is op=0xA7; iopr8is\n\n\tAIS #0x7F\n\tAIS #-0x7F\n\n; @if defined(HCS08) || defined(HC08)\n; : AIX iopr8is is op=0xAF; iopr8is\n\n\tAIX #0x7F\n\tAIX #-0x7F\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1\n\n\tAND #0xFE\n\tAND *0xFE\n\tAND 0xFEDC\n\tAND 0xFEDC,X\n\tAND 0xFE,X\n\tAND ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP\n\n\tAND 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP\n\n\tAND 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASLA is op=0x48\n\n\tASLA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASLX is op=0x58\n\n\tASLX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1\n\n\tASL *0xFE\n\tASL 0xFE,X\n\tASL ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP\n\n\tASL 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASRA is op=0x47\n\n\tASRA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASRX is op=0x57\n\n\tASRX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1\n\n\tASR *0xFE\n\tASR 0xFE,X\n\tASR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP\n\n\tASR 0xFE,S\n\n\nBACKWARDS1:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCC REL is op=0x24; REL\n\n\tBCC BACKWARDS1\n\tBCC FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8\n\n\tBCLR #0, *0xFE\n\tBCLR #1, *0xED\n\tBCLR #2, *0xDC\n\tBCLR #3, *0xCB\n\tBCLR #4, *0xBA\n\tBCLR #5, *0xA9\n\tBCLR #6, *0x98\n\tBCLR #7, *0x87\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BCS REL is op=0x25; REL\n\n\tBCS BACKWARDS1\n\tBCS FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BEQ REL is op=0x27; REL\n\n\tBEQ BACKWARDS1\n\tBEQ FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BGE REL is op=0x90; REL\n\n\tBGE BACKWARDS1\n\tBGE FORWARDS1\n\n\n; @if defined(HCS08)\n; : BGND is op=0x82\n\n\tBGND\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BGT REL is op=0x92; REL\n\n\tBGT BACKWARDS1\n\tBGT FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHCC REL is op=0x28; REL\n\n\tBHCC BACKWARDS1\n\tBHCC FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHCS REL is op=0x29; REL\n\n\tBHCS BACKWARDS1\n\tBHCS FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BHI REL is op=0x22; REL\n\n\tBHI BACKWARDS1\n\tBHI FORWARDS1\n\n\n; :BHS REL\tis op=0x24; REL\t\tSee BCC\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIH REL is op=0x2F; REL\n\n\tBIH BACKWARDS1\n\tBIH FORWARDS1\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIL REL is op=0x2E; REL\n\n\tBIL BACKWARDS1\n\tBIL FORWARDS1\n\n\nFORWARDS1:\nBACKWARDS2:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1\n\n\tBIT #0xFE\n\tBIT *0xFE\n\tBIT 0xFEDC\n\tBIT 0xFEDC,X\n\tBIT 0xFE,X\n\tBIT ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP\n\n\tBIT 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP\n\n\tBIT 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BLE REL is op=0x93; REL\n\n\tBLE BACKWARDS2\n\tBLE FORWARDS2\n\n\n; :BLO REL\tis op=0x25; REL\t\tsee BCS\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BLS REL is op=0x23; REL\n\n\tBLS BACKWARDS2\n\tBLS FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08)\n; : BLT REL is op=0x91; REL\n\n\tBLT BACKWARDS2\n\tBLT FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMC REL is op=0x2C; REL\n\n\tBMC BACKWARDS2\n\tBMC FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMI REL is op=0x2B; REL\n\n\tBMI BACKWARDS2\n\tBMI FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BMS REL is op=0x2D; REL\n\n\tBMS BACKWARDS2\n\tBMS FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BNE REL is op=0x26; REL\n\n\tBNE BACKWARDS2\n\tBNE FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BPL REL is op=0x2A; REL\n\n\tBPL BACKWARDS2\n\tBPL FORWARDS2\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRA REL is op=0x20; REL\n\n\tBRA BACKWARDS2\n\tBRA FORWARDS2\n\n\nFORWARDS2:\nBACKWARDS3:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL\n\n\tBRCLR #0, *0xFE,BACKWARDS3\n\tBRCLR #1, *0xED,BACKWARDS3\n\tBRCLR #2, *0xDC,BACKWARDS3\n\tBRCLR #3, *0xCB,BACKWARDS3\n\tBRCLR #4, *0xBA,BACKWARDS3\n\tBRCLR #5, *0xA9,BACKWARDS3\n\tBRCLR #6, *0x98,BACKWARDS3\n\tBRCLR #7, *0x87,BACKWARDS3\n\n\tBRCLR #0, *0xFE,FORWARDS3\n\tBRCLR #1, *0xED,FORWARDS3\n\tBRCLR #2, *0xDC,FORWARDS3\n\tBRCLR #3, *0xCB,FORWARDS3\n\tBRCLR #4, *0xBA,FORWARDS3\n\tBRCLR #5, *0xA9,FORWARDS3\n\tBRCLR #6, *0x98,FORWARDS3\n\tBRCLR #7, *0x87,FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; branch never is a two-byte nop\n; : BRN REL is op=0x21; REL\n\n\tBRN BACKWARDS3\n\tBRN FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL\n\n\tBRSET #0, *0xFE,BACKWARDS3\n\tBRSET #1, *0xED,BACKWARDS3\n\tBRSET #2, *0xDC,BACKWARDS3\n\tBRSET #3, *0xCB,BACKWARDS3\n\tBRSET #4, *0xBA,BACKWARDS3\n\tBRSET #5, *0xA9,BACKWARDS3\n\tBRSET #6, *0x98,BACKWARDS3\n\tBRSET #7, *0x87,BACKWARDS3\n\n\tBRSET #0, *0xFE,FORWARDS3\n\tBRSET #1, *0xED,FORWARDS3\n\tBRSET #2, *0xDC,FORWARDS3\n\tBRSET #3, *0xCB,FORWARDS3\n\tBRSET #4, *0xBA,FORWARDS3\n\tBRSET #5, *0xA9,FORWARDS3\n\tBRSET #6, *0x98,FORWARDS3\n\tBRSET #7, *0x87,FORWARDS3\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8\n\n\tBSET #0, *0xFE\n\tBSET #1, *0xED\n\tBSET #2, *0xDC\n\tBSET #3, *0xCB\n\tBSET #4, *0xBA\n\tBSET #5, *0xA9\n\tBSET #6, *0x98\n\tBSET #7, *0x87\n\nFORWARDS3:\nBACKWARDS4:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : BSR REL is op=0xAD; REL\n\n\tBSR BACKWARDS4\n\tBSR FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL\n\n\tCBEQ *0xFE, BACKWARDS4\n\tCBEQ *0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL\n\n\tCBEQA #0xFE, BACKWARDS4\n\tCBEQA #0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL\n\n\tCBEQX #0xFE, BACKWARDS4\n\tCBEQX #0xFE, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ oprx8, X\"+\", REL is (op=0x61) & X; oprx8; REL\n\n\tCBEQ *0xFE, X+, BACKWARDS4\n\tCBEQ *0xFE, X+, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ \",\"X\"+\", REL is (op=0x71) & X; REL\n\n\tCBEQ ,X+, BACKWARDS4\n\tCBEQ ,X+, FORWARDS4\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL\n\n\tCBEQ 0xFE,S, BACKWARDS4\n\tCBEQ 0xFE,S, FORWARDS4\n\n\nFORWARDS4:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLC is op=0x98\n\n\tCLC\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLI is op=0x9A\n\n\tCLI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLRA is op=0x4F\n\n\tCLRA\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLRX is op=0x5F\n\n\tCLRX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CLRH is op=0x8C\n\n\tCLRH\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1\n\n\tCLR *0xFE\n\tCLR 0xFE,X\n\tCLR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP\n\n\tCLR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1\n\n\tCMP #0xFE\n\tCMP *0xFE\n\tCMP 0xFEDC\n\tCMP 0xFEDC,X\n\tCMP 0xFE,X\n\tCMP ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP\n\n\tCMP 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP\n\n\tCMP 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COMA is op=0x43\n\n\tCOMA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COMX is op=0x53\n\n\tCOMX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1\n\n\tCOM *0xFE\n\tCOM 0xFE,X\n\tCOM ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP\n\n\tCOM 0xFE,S\n\n\n; @if defined(HCS08)\n; : CPHX opr16a_16 is (op=0x3E); opr16a_16\n\n\tCPHX 0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPHX iopr16i is (op=0x65); iopr16i\n\n\tCPHX #0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPHX opr8a_16 is (op=0x75); opr8a_16\n\n\tCPHX *0xFE\n\n\n; @if defined(HCS08)\n; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP\n\n\tCPHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1\n\n\tCPX #0xFE\n\tCPX *0xFE\n\tCPX 0xFEDC\n\tCPX 0xFEDC,X\n\tCPX 0xFE,X\n\tCPX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP\n\n\tCPX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP\n\n\tCPX 0xFE,S\n\nBACKWARDS5:\n\n; @if defined(HCS08) || defined(HC08)\n; : DAA is op=0x72\n\n\tDAA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZA REL is op=0x4B; REL\n\n\tDBNZA BACKWARDS5\n\tDBNZA FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZX REL is op=0x5B; REL\n\n\tDBNZX BACKWARDS5\n\tDBNZX FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL\n\n\tDBNZ *0xFE, BACKWARDS5\n\tDBNZ 0xFE,X, BACKWARDS5\n\tDBNZ ,X, BACKWARDS5\n\n\tDBNZ *0xFE, FORWARDS5\n\tDBNZ 0xFE,X, FORWARDS5\n\tDBNZ ,X, FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL\n\n\tDBNZ 0xFE,S, BACKWARDS5\n\tDBNZ 0xFE,S, FORWARDS5\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DECA is op=0x4A\n\n\tDECA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DECX is op=0x5A\n\n\tDECX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1\n\n\tDEC *0xFE\n\tDEC 0xFE,X\n\tDEC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP\n\n\tDEC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : DIV is op=0x52\n\n\tDIV\n\n\nFORWARDS5:\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1\n\n\tEOR #0xFE\n\tEOR *0xFE\n\tEOR 0xFEDC\n\tEOR 0xFEDC,X\n\tEOR 0xFE,X\n\tEOR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP\n\n\tEOR 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP\n\n\tEOR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INCA is op=0x4C\n\n\tINCA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INCX is op=0x5C\n\n\tINCX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1\n\n\tINC *0xFE\n\tINC 0xFE,X\n\tINC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP\n\n\tINC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR\n\n\tJMP *LOW_SUB_TEST\n\tJMP HIGH_SUB_TEST\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI\n\n\tJMP 0xFEDC,X\n\tJMP 0xFE,X\n\tJMP ,X\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR\n\n\tJSR *LOW_SUB_TEST\n\tJSR HIGH_SUB_TEST\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI\n\n\tJSR 0xFEDC,X\n\tJSR 0xFE,X\n\tJSR ,X\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1\n\n\tLDA #0xFE\n\tLDA *0xFE\n\tLDA 0xFEDC\n\tLDA 0xFEDC,X\n\tLDA 0xFE,X\n\tLDA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP\n\n\tLDA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP\n\n\tLDA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDHX iopr16i is (op=0x45); iopr16i\n\n\tLDHX #0xFEDC\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDHX opr8a_16 is (op=0x55); opr8a_16\n\n\tLDHX *0xFE\n\n\n; @if defined(HCS08)\n; : LDHX opr16a_16 is (op=0x32); opr16a_16\n\n\tLDHX 0xFEDC\n\n\n; @if defined(HCS08)\n; : LDHX \",\"X is (op16=0x9EAE) & X\n\n\tLDHX ,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X\n\n\tLDHX 0xFEDC,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X\n\n\tLDHX 0xFE,X\n\n\n; @if defined(HCS08)\n; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP\n\n\tLDHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1\n\n\tLDX #0xFE\n\tLDX *0xFE\n\tLDX 0xFEDC\n\tLDX 0xFEDC,X\n\tLDX 0xFE,X\n\tLDX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP\n\n\tLDX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP\n\n\tLDX 0xFE,S\n\n\n; ## Logical Shift left is same as arithmetic shift left\n; :LSLA\t\tis op=0x48\n; :LSLX\t\tis op=0x58\n; :LSL OP1\tis (op=0x38 | op=0x68 | op=0x78) ... & OP1\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSRA is op=0x44\n\n\tLSRA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSRX is op=0x54\n\n\tLSRX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1\n\n\tLSR *0xFE\n\tLSR 0xFE,X\n\tLSR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP\n\n\tLSR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV opr8a_8, op2_opr8a\tis (op=0x4E); opr8a_8; op2_opr8a\n\n\tMOV *0xFE, *0x97\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV opr8a_8, X\"+\" is (op=0x5E); opr8a_8 & X\n\n\tMOV 0xFE, X+\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a\n\n\tMOV #0xFE, *0x97\n\n\n; @if defined(HCS08) || defined(HC08)\n; : MOV \",\"X\"+,\" op2_opr8a is (op=0x7E) & X; op2_opr8a\n\n\tMOV ,X+, *0xFE\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : MUL is op=0x42\n\n\tMUL\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEGA is op=0x40\n\n\tNEGA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEGX is op=0x50\n\n\tNEGX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1\n\n\tNEG *0xFE\n\tNEG 0xFE,X\n\tNEG ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP\n\n\tNEG 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : NOP is op = 0x9D\n\n\tNOP\n\n\n; @if defined(HCS08) || defined(HC08)\n; : NSA is op = 0x62\n\n\tNSA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1\n\n\tORA #0xFE\n\tORA *0xFE\n\tORA 0xFEDC\n\tORA 0xFEDC,X\n\tORA 0xFE,X\n\tORA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP\n\n\tORA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP\n\n\tORA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHA is op = 0x87\n\n\tPSHA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHH is op = 0x8B\n\n\tPSHH\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PSHX is op = 0x89\n\n\tPSHX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULA is op = 0x86\n\n\tPULA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULH is op = 0x8A\n\n\tPULH\n\n\n; @if defined(HCS08) || defined(HC08)\n; : PULX is op = 0x88\n\n\tPULX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROLA is op=0x49\n\n\tROLA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROLX is op=0x59\n\n\tROLX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1\n\n\tROL *0xFE\n\tROL 0xFE,X\n\tROL ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP\n\n\tROL 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RORA is op=0x46\n\n\tRORA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RORX is op=0x56\n\n\tRORX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1\n\n\tROR *0xFE\n\tROR 0xFE,X\n\tROR ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP\n\n\tROR 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RSP is op = 0x9C\n\n\tRSP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RTI is op = 0x80\n\n\tRTI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : RTS is op = 0x81\n\n\tRTS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1\n\n\tSBC #0xFE\n\tSBC *0xFE\n\tSBC 0xFEDC\n\tSBC 0xFEDC,X\n\tSBC 0xFE,X\n\tSBC ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP\n\n\tSBC 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP\n\n\tSBC 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SEC is op = 0x99\n\n\tSEC\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SEI is op = 0x9B\n\n\tSEI\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1\n\n\tSTA *0xFE\n\tSTA 0xFEDC\n\tSTA 0xFEDC,X\n\tSTA 0xFE,X\n\tSTA ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP\n\n\tSTA 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP\n\n\tSTA 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STHX opr8a_16 is (op=0x35); opr8a_16\n\n\tSTHX *0xFE\n\n\n; @if defined(HCS08)\n; : STHX opr16a_16 is (op=0x96); opr16a_16\n\n\tSTHX 0xFEDC\n\n\n; @if defined(HCS08)\n; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP\n\n\tSTHX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STOP is op=0x8E\n\n\tSTOP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1\n\n\tSTX *0xFE\n\tSTX 0xFEDC\n\tSTX 0xFEDC,X\n\tSTX 0xFE,X\n\tSTX ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP\n\n\tSTX 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP\n\n\tSTX 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1\n\n\tSUB #0xFE\n\tSUB *0xFE\n\tSUB 0xFEDC\n\tSUB 0xFEDC,X\n\tSUB 0xFE,X\n\tSUB ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP\n\n\tSUB 0xFEDC,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP\n\n\tSUB 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : SWI is op=0x83\n\n\tSWI\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TAP is op=0x84\n\n\tTAP\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TAX is op=0x97\n\n\tTAX\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TPA is op=0x85\n\n\tTPA\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TSTA is op=0x4D\n\n\tTSTA\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TSTX is op=0x5D\n\n\tTSTX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1\n\n\tTST *0xFE\n\tTST 0xFE,X\n\tTST ,X\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP\n\n\tTST 0xFE,S\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TSX is op=0x95\n\n\tTSX\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : TXA is op=0x9F\n\n\tTXA\n\n\n; @if defined(HCS08) || defined(HC08)\n; : TXS is op=0x94\n\n\tTXS\n\n\n; @if defined(HCS08) || defined(HC08) || defined(HC05)\n; : WAIT is op=0x8f\n\n\tWAIT\n\n\nHERE:\n\tBRA\tHERE\n" }, { "path": "pypcode/processors/HCS12/data/languages/HC12.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HC12.pspec", "content": "\n\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HC12.slaspec", "content": "# sleigh specification file for Freescale HC12 (68HC12)\n\n@define HC12 \"1\"\n\n@define SIZE \"2\"\n\n@define MAXFLASHPage \"0xFF\"\n\n@include \"HCS_HC12.sinc\"" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n\n \n \n \n\n \n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12.ldefs", "content": "\n\n\n \n HC12 Microcontroller Family\n \n \n \n \n HCS12 Microcontroller Family\n \n \n \n \n HCS12X Microcontroller Family\n \n \n \n \n \n \n HCS12X Microcontroller Family\n \n \n \n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12.opinion", "content": "\n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12.slaspec", "content": "# sleigh specification file for Freescale HCS12 (68HCS12)\n\n@define HCS12 \"1\"\n\n@define SIZE \"3\"\n\n@define MAXFLASHPage \"0xFF\"\n\n@include \"HCS_HC12.sinc\"" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12X.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n\n \n\n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t R7 = SP;\n\t \n\t \n \n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12X.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/HCS12/data/languages/HCS12X.slaspec", "content": "# sleigh specification file for Freescale HCS12 (68HCS12)\n\n@define HCS12 \"1\"\n@define HCS12X \"1\"\n@define SIZE \"3\"\n\n@define MAXFLASHPage \"0xFF\"\n\n@include \"HCS_HC12.sinc\"\n@include \"XGATE.sinc\"" }, { "path": "pypcode/processors/HCS12/data/languages/HCS_HC12.sinc", "content": "# common include file for HCS12, and HC12 constructors\n\ndefine endian=big;\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=$(SIZE) default;\ndefine space register type=register_space size=2;\n\n@define VECTOR_SWI \t\"0xFFF6\"\n@define VECTOR_TRAP \"0xFFF8\"\n\n################################################################\n# Registers\n################################################################\n\ndefine register offset=0x00 size=1 [ A B ];\ndefine register offset=0x00 size=2 [ D ];\n\n# IX also referred to as X or x; but must be distinct from X bit in CCR\n# IY also referred to as Y or y; made IY to be consistent with IX\ndefine register offset=0x10 size=2 [ IX IY TMP2 TMP3 TMP1 ];\ndefine register offset=0x10 size=1 [ IXH IXL IYH IYL TMP2H TMP2L TMP3H TMP3L TMP1H TMP1L ];\n\n#define register offset=0x20 size=3 [ _ PCE _ SPE ];\ndefine register offset=0x20 size=3 [ _ PCE ];\ndefine register offset=0x20 size=2 [ _ _ PC _ _ SP ];\ndefine register offset=0x20 size=1 [ _ _ _ _ PCH PCL _ _ _ _ SPH SPL ];\n\ndefine register offset=0x30 size=2 [ CCRW ];\ndefine register offset=0x30 size=1 [ CCRH ];\n\ndefine register offset=0x31 size=1 [ CCR ];\n\ndefine register offset = 0x32 size=3 [physPage];\n\ndefine RAM offset=0x11 size=1 [DIRECT];\n\n@ifdef HCS12\ndefine RAM offset=0x30 size=1 [PPAGE];\n@endif\n@ifdef HCS12X\ndefine RAM offset=0x10 size=1 [GPAGE];\ndefine RAM offset=0x16 size=1 [RPAGE];\ndefine RAM offset=0x17 size=1 [EPAGE];\n@endif\n\n\n# Define context bits\n# WARNING: when adjusting context keep compiler packing in mind\n# and make sure fields do not span a 32-bit boundary before or \n# after context packing\ndefine register offset=0x40 size=4 contextreg;\ndefine context contextreg\n \tPrefix18\t = (0,0) # 1 if 0x18 is the first byte\n \tPrefixHCS12X = (0,0) # 1 if first byte is 0x18 so that HCS12X to use GPAGE for memory access\n \tUseGPAGE = (1,1) # 1 if should use GPAGE concatenated to lower 16-bit EA\n \tXGATE = (2,2) # 1 if in xgate instruction decode mode\n;\n\n\n# individual status bits within CCRH\n\n@define IPL_2\t\"CCRH[2,1]\"\t\t\n@define IPL_1\t\"CCRH[1,1]\"\t\t\n@define IPL_0\t\"CCRH[0,1]\"\t\t\n\n@define IPL\t\t\"CCRH[0,3]\"\t\t# entire IPL \n\n# individual status bits within CCR\n\n@define S\t\t\"CCR[7,1]\"\t\t# STOP Enable\n@define X\t\t\"CCR[6,1]\"\t\t# Non-maskable interrupt control bit\n@define H\t\t\"CCR[5,1]\"\t\t# Half Carry Flag\n@define I\t\t\"CCR[4,1]\"\t\t# Maskable interrupt control bit\n@define N\t\t\"CCR[3,1]\"\t\t# Negative Flag\n@define Z\t\t\"CCR[2,1]\"\t\t# Zero Flag\n@define V\t\t\"CCR[1,1]\"\t\t# Two's complement overflow Flag\n@define C\t\t\"CCR[0,1]\"\t\t# Carry/Borrow Flag\n\n################################################################\n# Tokens\n################################################################\n\ndefine token opbyte8 (8)\n\top8 = (0,7)\n\top7_4 = (4,7)\n\top6_4 = (4,6)\n\tnIndex = (1,3)\n\top0_0 = (0,0)\n\ttrapnum = (0,7)\n;\n\ndefine token xb8 (8)\n\trr7_6 = (6,7)\n\trr7_6a = (6,7)\n\txb5_5 = (5,5)\n\tnn4_0 = (0,4) signed\n\t\n\txb7_5 = (5,7)\n\trr4_3 = (3,4)\n\txb2_2 = (2,2)\n\txb2_1 = (1,2) # actually needed this instead of xb2_2\n\tz1_1 = (1,1)\n\ts0_0 = (0,0)\n\tss0_0 = (0,0) signed\n\t\n\txb2_0 = (0,2)\n\n\tp4_4 = (4,4)\n\tdecrement3_3 = (3,3)\n\tnn3_0 = (0,3)\n\t\n\taa1_0 = (0,1)\t\n\taa0_0 = (0,0) # actually needed this instead of aa1_0\t\n;\n\ndefine token eb8 (8)\n\tnotUsed7_7\t= (7,7)\n\tabcdxys6_4 = (4,6)\n\tabc5_4\t\t= (4,5)\n\tdxys2_0\t\t= (0,2)\n\tabcdxys2_0 = (0,2)\n\tcolumns7_4\t= (4,7)\n\trows2_0\t\t= (0,2)\n\trows3_0\t\t= (0,3)\n\tbytes_ABCl_6_4\t\t\t\t= (4,6)\n\tbytes_ABClT3lBXlYlSl_6_4\t= (4,6)\n\tbytes_ABChT3hBXhYhSh_6_4\t= (4,6)\n\twords_CT3DXYS_6_4\t\t\t= (4,6)\n\twords_T3DXYS_6_4\t\t\t= (4,6)\n\tbytes_ABCl_2_0\t\t\t\t= (0,2)\n\tbytes_T3lDlXlYlSl_6_4\t\t= (4,6)\n\twords_T2DXYS_2_0\t\t\t= (0,2)\n\tbytes_T2h_XhYhSh_2_0\t\t= (0,2)\n\tbytes_T2l_XlYlSl_2_0\t\t= (0,2)\n\tbytes_T3l_XlYlSl_6_4\t\t= (4,6)\n\tbytes_T3h_XhYhSh_6_4\t\t= (4,6)\n\twords_T3_XYS_6_4\t\t\t= (4,6)\n\tbytes_T2hDhXhYhSh_2_0\t\t= (0,2)\n\tbytes_T2lDlXlYlSl_2_0\t\t= (0,2) \n;\n\ndefine token opbyte16 (16)\n\top16\t\t= (0,15)\n\top15_13\t\t= (13,15)\n\tsign12_12\t= (12,12) signed\n\tnot_used11\t= (11,11)\n\tsize10_10\t= (10,10)\n\tbyte9_8\t\t= (8,9)\n\tword9_8\t\t= (8,9)\n\trr7_0\t\t= (0,7)\n;\n\ndefine token data8 (8)\n\timm8 = (0,7)\n\tsimm8 = (0,7) signed\n\trel = (0,7) signed\n;\n\ndefine token data16 (16)\n\timm16 = (0,15)\n\timm16p = (12,15)\n\timm16e = (8,15)\n\timm16ev = (0,9)\n\timm16rv = (0,11)\n\timm16pv = (0,13)\n\tsimm16 = (0,15) signed\n;\n\nattach variables [ rr7_6 rr4_3 ]\t[ IX IY SP PC ];\nattach variables [ rr7_6a ]\t\t \t[ IX IY SP _ ]; # PC not valid choice in this case\n\n# TODO would be great if this worked\n# attach names [ rr7_6 rr4_3 ] [ \"X\" \"Y\" \"SP\" \"PC\" ];\n\n\n# TODO do the negative values work?\nattach values [ nn3_0 ] [ 1 2 3 4 5 6 7 8 -8 -7 -6 -5 -4 -3 -2 -1 ];\n\nattach variables [ aa0_0 ] [ A B ];\n\nattach variables [ byte9_8 ] [ A B _ _ ];\n\nattach variables [ word9_8 ] [ D IX IY SP ];\n\nattach variables [ abc5_4 ] [ A B CCR _ ];\n\nattach variables [ dxys2_0 ] [ _ _ _ TMP2 D IX IY SP ];\n\nattach variables [ bytes_ABCl_2_0 ] [ A B CCR _ _ _ _ _ ];\n\nattach variables [ bytes_ABClT3lBXlYlSl_6_4 ] [ A B CCR TMP3L B IXL IYL SPL ];\n\nattach variables [ bytes_ABChT3hBXhYhSh_6_4 ] [ A B CCRH TMP3H B IXH IYH SPH ];\n\nattach variables [ words_T2DXYS_2_0 ] [ _ _ _ TMP2 D IX IY SP ];\n\nattach variables [ bytes_T3lDlXlYlSl_6_4 ] [ _ _ _ TMP3L B IXL IYL SPL ];\n\nattach variables [ words_T3DXYS_6_4 ] [ _ _ _ TMP3 D IX IY SP ];\n\nattach variables [ words_CT3DXYS_6_4 ] [ _ _ CCRW TMP3 D IX IY SP ];\n\nattach variables [ bytes_T2l_XlYlSl_2_0 ] [ _ _ _ TMP2L _ IXL IYL SPL ];\n\nattach variables [ bytes_T2h_XhYhSh_2_0 ] [ _ _ _ TMP2H _ IXH IYH SPH ];\n\nattach variables [ bytes_T3l_XlYlSl_6_4 ] [ _ _ _ TMP3L _ IXL IYL SPL ];\n\nattach variables [ bytes_T3h_XhYhSh_6_4 ] [ _ _ _ TMP3H _ IXH IYH SPH ];\n\nattach variables [ words_T3_XYS_6_4 ] [ _ _ _ TMP3 _ IX IY SP ];\n\nattach variables [ bytes_ABCl_6_4 ] [ A B CCR _ _ _ _ _ ];\n\nattach variables [ bytes_T2hDhXhYhSh_2_0 ] [ _ _ _ TMP2H A IXH IYH SPH ];\n\nattach variables [ bytes_T2lDlXlYlSl_2_0 ] [ _ _ _ TMP2L B IXL IYL SPL ];\n\n################################################################\n# Pseudo Instructions\n################################################################\ndefine pcodeop segment; # Define special pcodeop that calculates the RAM address\n\n# given the segment selector and offset as input\n\ndefine pcodeop readIRQ;\ndefine pcodeop stop;\ndefine pcodeop WaitForInterrupt;\n\ndefine pcodeop decimalAdjustAccumulator;\ndefine pcodeop decimalAdjustCarry;\ndefine pcodeop EMACS;\ndefine pcodeop ETBL;\ndefine pcodeop ETBL_Cflag;\ndefine pcodeop GradeOfMembership;\ndefine pcodeop TableLookupAndInterpolate;\ndefine pcodeop TableLookupAndInterpolateRoundable;\ndefine pcodeop WeightedAverageSOPHigh;\ndefine pcodeop WeightedAverageSOPLow;\ndefine pcodeop WeightedAverageSOW;\ndefine pcodeop WeightedAverageResume;\ndefine pcodeop MinMaxRuleEvaluation;\ndefine pcodeop MinMaxRuleEvaluationCorrect;\ndefine pcodeop MinMaxRuleEvaluationWeighted;\ndefine pcodeop MinMaxRuleEvaluationWeightedCorrect;\n\ndefine pcodeop backgroundDebugMode;\n\n@if defined(HCS12X)\nmacro setHCSphysPage(addr) {\n\tlocal a3:3 = zext(addr);\n\t\n\tlocal isReg:1 = (a3 & 0xfC00) == 0x0;\n\tlocal isEpage:1 = (a3 & 0xfc00) ==0x800;\n\tlocal isEpage_FF:1 = (a3 & 0xfc00) ==0xC00;\n\tlocal isRpage:1 = (a3 & 0xf000) ==0x1000;\n\tlocal isRpage_FE:1 = (a3 & 0xf000) ==0x2000;\n\tlocal isRpage_FF:1 = (a3 & 0xf000) ==0x3000;\n\tlocal isPpage_FD:1 = (a3 & 0xc000) ==0x4000;\n\tlocal isPpage:1 = (a3 & 0xc000) ==0x8000;\n\tlocal isPpage_FF:1 = (a3 & 0xc000) ==0xC000;\n\t\n\tphysPage = (zext(isReg) * 0x0) +\n\t (zext(isEpage) * (0x100000 | ((zext(EPAGE) << 10) ^ 0x800))) +\n\t (zext(isEpage_FF) * ((0x4FF << 10) ^ 0xC00)) +\n\t (zext(isRpage) * (((zext(RPAGE) << 12) ^ 0x1000))) +\n\t (zext(isRpage_FE) * (((0xFE << 12) ^ 0x2000))) +\n\t (zext(isRpage_FF) * (((0xFF << 12) ^ 0x3000))) +\n\t (zext(isPpage_FD) * (0x400000 | ((0x3F4000) ^ 0x4000))) +\n\t (zext(isPpage) * (0x400000 | ((zext(PPAGE) << 14 ) ^ 0x8000))) +\n\t (zext(isPpage_FF) * (0x400000 | ((0x3FC000) ^ 0xC000))) ;\n}\n@elif defined(HCS12) && SIZE==\"3\"\nmacro setHCSphysPage(addr) {\n\tlocal a3:3 = zext(addr);\n\n\tlocal isPpage_3D:1 = (a3 & 0xc000) ==0x0000;\n\tlocal isPpage_3E:1 = (a3 & 0xc000) ==0x4000;\n\tlocal isPpage:1 = (a3 & 0xc000) ==0x8000;\n\tlocal isPpage_3F:1 = (a3 & 0xc000) ==0xC000;\n\t\n#\tphysPage = (zext(isPpage) * (0x000000 | ((zext(PPAGE) << 14 ) ^ 0x8000)));\n\n\tphysPage = (zext(isPpage_3D) * (0x000000 | ((0xF4000) ^ 0x0000))) +\n\t (zext(isPpage_3E) * (0x000000 | ((0xF8000) ^ 0x4000))) +\n\t (zext(isPpage) * (0x000000 | ((zext(PPAGE) << 14 ) ^ 0x8000))) +\n\t (zext(isPpage_3F) * (0x000000 | ((0xFC000) ^ 0xC000))) ;\n}\n@endif\n\nmacro GetPagedAddr(addr,paddr) {\n@if SIZE==\"3\"\n setHCSphysPage(addr);\n paddr = segment(physPage, addr);\n@else\n paddr = addr;\n@endif\n}\n\nmacro Load1(value, addr) {\n local paddr:$(SIZE);\n \n GetPagedAddr(addr,paddr); \n \n\tvalue = *:1 paddr;\n}\nmacro Load2(value, addr) {\n local paddr:$(SIZE);\n \n GetPagedAddr(addr,paddr);\n \n\tvalue = *:2 paddr;\n}\n\nmacro Store(addr, value) {\n local paddr:$(SIZE);\n \n GetPagedAddr(addr,paddr);\n \n\t*paddr = value;\n}\n\n################################################################\n# Addressing tables\n################################################################\n\n#\n# TODO: Paging could be added here as these are constant addresses\n# could factor the overlapping addresses here, unless the\n# page register is always added in then will have to export as a constant\n# since don't know the real address\n#\n\nmacro pageCAddr(addr, shift, page, offset) {\n addr = addr | ((page << shift) | offset);\n}\nmacro pagePAddr(addr, shift, page, offset) {\n addr = addr | ((zext(page) << shift) | offset);\n}\n\n@if defined(HCS12X)\n\n# known EPAGE offsets\nopr16a: imm16 is imm16e=0x8 & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; }\nopr16a: imm16 is imm16e=0x9 & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; }\nopr16a: imm16 is imm16e=0xa & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; }\nopr16a: imm16 is imm16e=0xb & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; }\n\nopr16a: imm16 is imm16e=0xc & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; }\nopr16a: imm16 is imm16e=0xd & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; }\nopr16a: imm16 is imm16e=0xe & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; }\nopr16a: imm16 is imm16e=0xf & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; }\n\n# known RPAGE offsets\nopr16a: imm16 is imm16p=0x1 & imm16 & imm16rv { local addr:3 = 0; pagePAddr(addr,12,RPAGE,imm16rv); export addr; }\nopr16a: imm16 is imm16p=0x2 & imm16 & imm16rv { local addr:3 = 0; pageCAddr(addr,12,0xFE,imm16rv); export addr; }\nopr16a: imm16 is imm16p=0x3 & imm16 & imm16rv { local addr:3 = 0; pageCAddr(addr,12,0xFF,imm16rv); export addr; }\n\n# known PPAGE offsets\nopr16a: imm16 is imm16p=0x4 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x5 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x6 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x7 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; }\n\nopr16a: imm16 is imm16p=0x8 & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\nopr16a: imm16 is imm16p=0x9 & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\nopr16a: imm16 is imm16p=0xa & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\nopr16a: imm16 is imm16p=0xb & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\n\nopr16a: imm16 is imm16p=0xC & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0xD & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0xE & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0xF & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; }\n\nopr16a:\t\t\timm16 is imm16e & imm16 { local addr:3 = imm16; export addr; }\n\nopr8a:\t\t\timm8 is imm8 { export *[const]:3 imm8; }\n\nopr8a_8:\t\timm8 is UseGPAGE=0 & imm8 { export *:1 imm8; }\nopr8a_8:\t\timm8 is UseGPAGE=1 & imm8 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm8); export *:1 addr; }\nopr8a_16:\t\timm8 is UseGPAGE=0 & imm8 { export *:2 imm8; }\nopr8a_16:\t\timm8 is UseGPAGE=1 & imm8 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm8); export *:2 addr; }\n\nopr16a_8:\t opr16a is UseGPAGE=0 & opr16a { export *:1 opr16a; }\nopr16a_8:\t imm16 is UseGPAGE=1 & imm16 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm16); export *:1 addr; }\nopr16a_16:\t opr16a is UseGPAGE=0 & opr16a { export *:2 opr16a; }\nopr16a_16:\t imm16 is UseGPAGE=1 & imm16 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm16); export *:2 addr; }\n\niopr8i:\t\t\t\"#\"imm8 is imm8 { export *[const]:1 imm8; }\niopr16i:\t\t\"#\"imm16 is imm16 { export *[const]:2 imm16; }\nmsk8:\t\t imm8 is imm8 { export *[const]:1 imm8; }\npage:\t\t imm8 is imm8 { export *[const]:1 imm8; }\n\n#PageDest: dest is imm16p=0x8 & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0x9 & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0xa & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0xb & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0xc & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0xd & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0xe & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { \t export *:1 dest; }\n#PageDest: dest is imm16p=0xf & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { \t export *:1 dest; }\nPageDest: opr16a is opr16a; page { export opr16a; }\n\n@else\n\n\n@if SIZE==\"3\"\nopr16a: imm16 is imm16p=0x0 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x1 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x2 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x3 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; }\n\nopr16a: imm16 is imm16p=0x4 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x5 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x6 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0x7 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; }\n\nopr16a: imm16 is imm16p=0x8 & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\nopr16a: imm16 is imm16p=0x9 & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\nopr16a: imm16 is imm16p=0xa & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\nopr16a: imm16 is imm16p=0xb & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; }\n\nopr16a: imm16 is imm16p=0xc & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0xd & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0xe & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; }\nopr16a: imm16 is imm16p=0xf & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; }\n\npage:\t\t imm8 is imm8 { export *[const]:1 imm8; }\n\nPageDest: opr16a is opr16a; page { \t export opr16a; }\n\n@elif SIZE==\"2\"\nopr16a: imm16 is imm16 { local addr:$(SIZE) = imm16; export addr; }\n@endif\n\nopr8a:\t\t\timm8 is imm8 { local addr:$(SIZE) = imm8; export addr; }\n\nopr8a_8:\t\timm8 is UseGPAGE=0 & imm8 { export *:1 imm8; }\nopr8a_16:\t\timm8 is UseGPAGE=0 & imm8 { export *:2 imm8; }\n\nopr16a_8:\t opr16a is opr16a { export *:1 opr16a; }\nopr16a_16:\t opr16a is opr16a { export *:2 opr16a; }\n\niopr8i:\t\t\t\"#\"imm8 is imm8 { export *[const]:1 imm8; }\niopr16i:\t\t\"#\"imm16 is imm16 { export *[const]:2 imm16; }\nmsk8:\t\t imm8 is imm8 { export *[const]:1 imm8; }\n\n@endif\n\n\n#\n# Postbyte Code (xb) address decoding\n# for indexed addressing modes: IDX, IDX1, IDX2, [D,IDX] and [IDX2]\n#\n#\n# per page 29, 30, and 33\n#\n\n#**********\n# IDX\n#**********\n#\n# rr0nnnnn \n#\n# 5-bit constant offset n = -16 to +15\nIDX_a: 0,rr7_6\t\t\tis rr7_6 & xb5_5=0 & nn4_0=0\n\t{ export rr7_6; }\n\t\t\n# TODO make sure that nn4_0 is a signed extension\t\nIDX_b: nn4_0, rr7_6\tis rr7_6 & xb5_5=0 & nn4_0\n\t{ address:2 = rr7_6 + nn4_0; export address; }\t\n\n# rr1pnnnn \n#\n# used xb7_5 in all of these to prevent rr7_6a from ever being 0b11, and overlapping the 111rr0zs decodes\n#\n# Auto pre-decrement\nIDX_c: nn3_0, -rr7_6a\tis (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=0 & decrement3_3=1 & nn3_0\n\t{ rr7_6a = rr7_6a + nn3_0; address:2 = rr7_6a; export address; }\n\t\n# Auto pre-increment\nIDX_d: nn3_0, +rr7_6a\tis (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=0 & decrement3_3=0 & nn3_0\n\t{ rr7_6a = rr7_6a + nn3_0; address:2 = rr7_6a; export address; }\t\t\n\n# Auto post-decrement\t\nIDX_e: nn3_0, rr7_6a-\tis (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=1 & decrement3_3=1 & nn3_0\n\t{ address:2 = rr7_6a; rr7_6a = rr7_6a + nn3_0; export address; }\t\n\t\n# Auto post-increment\t\nIDX_f: nn3_0, rr7_6a+\tis (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=1 & decrement3_3=0 & nn3_0\n\t{ address:2 = rr7_6a; rr7_6a = rr7_6a + nn3_0; export address; }\t\t\n\n# 111rr1aa \n#\n# Accumulator unsigned 8-bit offset indexed\nIDX_g: aa0_0, rr4_3\t\tis xb7_5=0b111 & rr4_3 & xb2_1=0b10 & aa0_0\n\t{ address:2 = rr4_3 + zext(aa0_0); export address; }\nIDX_g: aa0_0, PC\t\tis xb7_5=0b111 & rr4_3=3 & xb2_1=0b10 & aa0_0 & PC\n\t{ address:2 = inst_next + zext(aa0_0); export address; }\t\n\n# Accumulator 16-bit offset indexed\nIDX_h: D, rr4_3\t\t\tis xb7_5=0b111 & rr4_3 & xb2_0=0b110 & D\n\t{ address:2 = rr4_3 + D; export address; }\t\t\nIDX_h: D, PC\t\t\tis xb7_5=0b111 & rr4_3=3 & xb2_0=0b110 & D & PC\n\t{ address:2 = inst_next + D; export address; }\n\n#**********\n# IDX1\n#**********\n#\n# 111rr0zs imm8\n#\n# Constant offset (9-bit signed)\nIDX_i: opr9, rr4_3\t\tis xb7_5=0b111 & rr4_3 & xb2_2=0 & z1_1=0 & ss0_0 ; imm8 [ opr9 = (ss0_0 << 8) | imm8; ]\n\t{ address:2 = rr4_3 + opr9; export address; }\n\nIDX_i_PCRel: target is ss0_0 ; imm8 [ target = inst_next + (ss0_0 << 8) | imm8; ] { export *[const]:2 target; }\nIDX_i: opr9, PC\t\tis (xb7_5=0b111 & rr4_3=3 & xb2_2=0 & z1_1=0 & ss0_0 ; imm8) & IDX_i_PCRel & PC [ opr9 = (ss0_0 << 8) | imm8; ]\n\t{ export IDX_i_PCRel; }\t\n\n#**********\n# IDX2\n#**********\n#\n# 111rr0zs simm16\n#\n# Constant offset (16-bit signed)\nIDX_k: simm16, rr4_3\tis xb7_5=0b111 & rr4_3 & xb2_2=0 & z1_1=1 & s0_0=0; simm16\n\t{ address:2 = rr4_3 + simm16; export address; }\n\nIDX_k_PCRel: target is simm16 [ target = inst_next + simm16; ] { export *[const]:2 target; }\nIDX_k: simm16, PC\tis xb7_5=0b111 & rr4_3=3 & xb2_2=0 & z1_1=1 & s0_0=0; simm16 & PC & IDX_k_PCRel\n\t{ export IDX_k_PCRel; }\n\n#**********\n# [IDX2]\n#**********\n#\n# 111rr011 simm16\n#\n# 16-bit offset indexed-indirect\n\nIDX_l: [simm16, rr4_3]\tis xb7_5=0b111 & rr4_3 & xb2_2=0 & z1_1=1 & s0_0=1; simm16\n\t{ address:2 = rr4_3 + simm16; Load2(address,address); export address; }\n\nIDX_l_PCRel: target is simm16 [ target = inst_next + simm16; ] { export *[const]:2 target; }\nIDX_l: [simm16, PC]\tis xb7_5=0b111 & rr4_3=3 & xb2_2=0 & z1_1=1 & s0_0=1; simm16 & PC & IDX_l_PCRel\n\t{ address:2 = IDX_l_PCRel; Load2(address,address); export address; }\t\n\n#**********\n# [D,IDX]\n#**********\n#\n# 111rr111 \n#\n# Accumulator D offset indexed-indirect\nIDX_m: [D, rr4_3]\t\tis xb7_5=0b111 & rr4_3 & xb2_0=0b111 & D\n\t{ address:2 = rr4_3 + D; Load2(address,address); export address; }\t\n\nIDX_m: [D, PC]\t\tis xb7_5=0b111 & rr4_3=3 & xb2_0=0b111 & D & PC\n\t{ address:2 = inst_next + D; Load2(address,address); export address; }\t\n\n######################################################################\n######################################################################\n#\n# effective address of IDX, IDX1, IDX2\n#\nindexed3: IDX_a is IDX_a { export IDX_a; }\t\t\nindexed3: IDX_b is IDX_b { export IDX_b; }\t\t\nindexed3: IDX_c is IDX_c { export IDX_c; }\t\t\nindexed3: IDX_d is IDX_d { export IDX_d; }\t\t\nindexed3: IDX_e is IDX_e { export IDX_e; }\t\t\nindexed3: IDX_f is IDX_f { export IDX_f; }\t\t\nindexed3: IDX_g is IDX_g { export IDX_g; }\t\t\nindexed3: IDX_h is IDX_h { export IDX_h; }\t\t\nindexed3: IDX_i is IDX_i { export IDX_i; }\t\t\t\t\nindexed3: IDX_k is IDX_k { export IDX_k; }\t\t\n# not indexed3: IDX_l is IDX_l { export IDX_l; }\t\t\n# not indexed3: IDX_m is IDX_m { export IDX_m; }\t\t\n\n#\n# effective address of [IDX2], [D,IDX]\n#\n# not indexedindexed3: IDX_a is IDX_a { export IDX_a; }\t\t\n# not indexedindexed3: IDX_b is IDX_b { export IDX_b; }\t\t\n# not indexedindexed3: IDX_c is IDX_c { export IDX_c; }\t\t\n# not indexedindexed3: IDX_d is IDX_d { export IDX_d; }\t\t\n# not indexedindexed3: IDX_e is IDX_e { export IDX_e; }\t\t\n# not indexedindexed3: IDX_f is IDX_f { export IDX_f; }\t\t\n# not indexedindexed3: IDX_g is IDX_g { export IDX_g; }\t\t\n# not indexedindexed3: IDX_h is IDX_h { export IDX_h; }\t\t\n# not indexedindexed3: IDX_i is IDX_i { export IDX_i; }\t\t\t\n# not indexedindexed3: IDX_k is IDX_k { export IDX_k; }\n@ifdef HCS12\t\nindexed2: IDX_l is IDX_l { export IDX_l; }\t\t\nindexed2: IDX_m is IDX_m { export IDX_m; }\n@endif\n\n#\n# effective address of IDX, IDX1, IDX2, [IDX2], [D,IDX]\n#\nindexed5: IDX_a is IDX_a { export IDX_a; }\t\t\nindexed5: IDX_b is IDX_b { export IDX_b; }\t\t\nindexed5: IDX_c is IDX_c { export IDX_c; }\t\t\nindexed5: IDX_d is IDX_d { export IDX_d; }\t\t\nindexed5: IDX_e is IDX_e { export IDX_e; }\t\t\nindexed5: IDX_f is IDX_f { export IDX_f; }\t\t\nindexed5: IDX_g is IDX_g { export IDX_g; }\t\t\nindexed5: IDX_h is IDX_h { export IDX_h; }\t\t\nindexed5: IDX_i is IDX_i { export IDX_i; }\t\t\nindexed5: IDX_k is IDX_k { export IDX_k; }\t\t\nindexed5: IDX_l is IDX_l { export IDX_l; }\t\t\nindexed5: IDX_m is IDX_m { export IDX_m; }\n\n#\n# effective address of IDX\n#\nindexed1: IDX_a is IDX_a { export IDX_a; }\t\t\nindexed1: IDX_b is IDX_b { export IDX_b; }\t\t\nindexed1: IDX_c is IDX_c { export IDX_c; }\t\t\nindexed1: IDX_d is IDX_d { export IDX_d; }\t\t\nindexed1: IDX_e is IDX_e { export IDX_e; }\t\t\nindexed1: IDX_f is IDX_f { export IDX_f; }\t\t\nindexed1: IDX_g is IDX_g { export IDX_g; }\t\t\nindexed1: IDX_h is IDX_h { export IDX_h; }\t\t\n# not indexed1: IDX_i is IDX_i { export IDX_i; }\t\t\t\n# not indexed1: IDX_k is IDX_k { export IDX_k; }\t\t\n# not indexed1: iIDX_l is iIDX_l { export iIDX_l; }\t\t\n# not indexed1: IDX_m is IDX_m { export IDX_m; }\t\t\n\n\n#\n# indexed0_x - exports the effective address (EA)\n# indexed1_x - exports a single byte at the effective address\n# indexed2_x - exports a double byte at the effective address\n#\n\n@ifndef HCS12X\nindexed1_1: indexed1 is indexed1 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed1,paddr);\n\texport *:1 paddr;\n}\n@endif\n\n@ifdef HCS12\nindexed2_1: indexed1 is indexed1 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed1,paddr);\n\texport *:2 paddr;\n}\n@else\nindexed2_1: indexed1 is indexed1 {\n\texport *:2 indexed1;\n}\n@endif\n\n@ifdef HCS12\nindexed0_2: indexed2 is indexed2 {\n\tlocal val = indexed2; export val;\n}\n@endif\n\n\t\t\t\t\nindexed0_3: indexed3 is indexed3 {\n\tlocal val = indexed3; export val;\n}\n@ifdef HCS12\nindexed1_3: indexed3 is indexed3 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed3,paddr);\n\texport *:1 paddr;\n}\n@else\nindexed1_3: indexed3 is indexed3 {\n\texport *:1 indexed3;\n}\n@endif\n\n@ifdef HCS12\nindexed2_3: indexed3 is indexed3 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed3,paddr);\n\texport *:2 paddr;\n}\n@endif\n\n@ifdef HCS12\nindexedA_5: indexed5 is UseGPAGE=0 & indexed5 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed5,paddr);\n export paddr;\n}\n@else\nindexedA_5: indexed5 is UseGPAGE=0 & indexed5 {\n\texport indexed5;\n}\n@endif\n\n@ifdef HCS12X\nindexedA_5: indexed5 is UseGPAGE=1 & indexed5 {\n\tlocal addr:$(SIZE) = (zext(GPAGE) << 16) | zext(indexed5);\n\texport addr;\n}\n@endif\n\n@ifdef HCS12\nindexed1_5: indexed5 is UseGPAGE=0 & indexed5 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed5,paddr);\n\texport *:1 paddr;\n}\n@else\nindexed1_5: indexed5 is UseGPAGE=0 & indexed5 {\n\texport *:1 indexed5;\n}\n@endif\n\n@ifdef HCS12X\nindexed1_5: indexed5 is UseGPAGE=1 & indexed5 {\n\tlocal addr:$(SIZE) = (zext(GPAGE) << 16) | zext(indexed5);\n\texport *:1 addr;\n}\n@endif\n\n@ifdef HCS12\nindexed2_5: indexed5 is UseGPAGE=0 & indexed5 {\n\tlocal paddr:$(SIZE) = 0;\n\tGetPagedAddr(indexed5,paddr);\n\texport *:2 paddr;\n}\n@else\nindexed2_5: indexed5 is UseGPAGE=0 & indexed5 {\n\texport indexed5;\n}\n@endif\n\n@ifdef HCS12X\nindexed2_5: indexed5 is UseGPAGE=1 & indexed5 {\n\tlocal addr:$(SIZE) = (zext(GPAGE) << 16) | zext(indexed5);\n\texport *:2 addr;\n}\n@endif\n\n# range -128 through +127\nrel8: reloc is rel [ reloc = inst_next + rel; ] { export *:1 reloc; }\n\n# range -256 through +255\nrel9: reloc is sign12_12 & rr7_0 [ reloc = inst_next + ((sign12_12 << 8) | rr7_0); ] { export *:1 reloc; }\n\n# positive range 0 through +65535\nrel16: reloc is simm16 [ reloc = inst_next + simm16; ] { export *:1 reloc; }\n\n\nop2_opr16a_8:\topr16a_8\t\tis opr16a_8\t\t\t{ export opr16a_8; }\nop2_opr16a_16:\topr16a_16\t\tis opr16a_16\t\t{ export opr16a_16; }\n\n@if defined(HCS12X)\nop2_indexed1_5:\tindexed1_5\t\tis indexed1_5\t\t{ export indexed1_5; }\n@else\nop2_indexed1_1:\tindexed1_1\t\tis indexed1_1\t\t{ export indexed1_1; }\n@endif\n\n@if defined(HCS12X)\nop2_indexed2_5:\tindexed2_5\t\tis indexed2_5\t\t{ export indexed2_5; }\n@else\nop2_indexed2_1:\tindexed2_1\t\tis indexed2_1\t\t{ export indexed2_1; }\n@endif\n\n################################################################\n# Macros\n################################################################\n\n\n\nmacro additionWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C));\n\tlocal AFmask = -1 >> 4;\n\t$(H) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0;\n\t$(C) = carry(operand1, operand2);\n\tlocal tempResult = operand1 + operand2;\n\t$(C) = $(C) || carry(tempResult, Ccopy);\n\t$(V) = $(V) ^^ scarry(tempResult, Ccopy);\n\tresult = tempResult + Ccopy;\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n}\n\n\n\nmacro addition_flags1(operand1, operand2,result) {\n\tlocal AFmask = -1 >> 4;\n\t$(H) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;\n\t\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(V) = scarry(operand1,operand2);\n\t$(C) = carry(operand1,operand2);\n}\n\nmacro addition_flags2(operand1, operand2, result) {\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(V) = scarry(operand1,operand2);\n\t$(C) = carry(operand1,operand2);\n}\n\nmacro subtraction_flags1(register, operand, result) {\t\n\t$(V) = sborrow(register,operand);\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(C) = register < operand;\n}\n\nmacro subtraction_flags2(register, operand, result) {\n\t$(V) = sborrow(register,operand);\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(C) = register < operand;\n}\n\nmacro V_equals_0() {\n\t$(V) = 0;\n}\n\nmacro V_equals_C() {\n\t$(V) = $(C);\n}\n\nmacro V_equals_N_xor_C() {\n\t$(V) = $(N) ^ $(C);\t\n}\n\nmacro V_CMP_flag(register, operand) {\n\t$(V) = sborrow(register,operand);\n}\n\nmacro V_DEC_flag(operand) {\n\t$(V) = sborrow(operand,1);\n}\n\nmacro V_DEC_flag2(operand) {\n\t$(V) = sborrow(operand,1);\n}\n\nmacro V_INC_flag(operand) {\n\t$(V) = scarry(operand,1);\n}\n\nmacro V_INC_flag2(operand) {\n\t$(V) = scarry(operand,1);\n}\n\nmacro V_NEG_flag(operand) {\n\t$(V) = sborrow(0,operand);\n}\n\nmacro V_NEG_flag2(operand) {\n\t$(V) = sborrow(0,operand);\n}\n\nmacro Pull1(operand) {\n@if SIZE==\"3\"\n\tsetHCSphysPage(SP);\n\tpaddr:$(SIZE) = segment(physPage,SP);\n@else\n paddr:$(SIZE) = SP;\n@endif\n\toperand = *paddr;\n\tSP = SP + 1;\n}\n\nmacro Pull2(operand) {\n@if SIZE==\"3\"\n\tsetHCSphysPage(SP);\n\tpaddr:$(SIZE) = segment(physPage,SP);\n@else\n paddr:$(SIZE) = SP;\n@endif\n\n\toperand = *paddr;\n\tSP = SP + 2;\n}\n\nmacro Push1(operand) {\n\tSP = SP - 1;\n\n@if SIZE==\"3\"\t\n\tsetHCSphysPage(SP);\n\tpaddr:$(SIZE) = segment(physPage,SP);\n@else\n paddr:$(SIZE) = SP;\n@endif\n\n\t*paddr = operand;\n}\n\nmacro Push2(operand) {\n\tSP = SP - 2;\n\n@if SIZE==\"3\"\t\n\tsetHCSphysPage(SP);\n\tpaddr:$(SIZE) = segment(physPage,SP);\n@else\n paddr:$(SIZE) = SP;\n@endif\n\n\t*paddr = operand;\n}\n\nmacro setCCR( operand ) {\n\t# when CCR is the destination, cannot set the X bit unless it is already set in CCR\n\tCCR = operand & (CCR | 0b10111111);\n}\n\nmacro setCCRW( operand ) {\n\t# when CCRW is the destination, cannot set the X bit unless it is already set in CCRW\n\tCCRW = operand & (CCRW | 0b1111111110111111);\n}\n\n################################################################\n# Constructors\n################################################################\n\nwith : XGATE=0 {\n@ifdef HCS12X\n:^instruction is op8=0x18; instruction [ Prefix18=1; ] {}\n@else\n:^instruction is op8=0x18; instruction [ Prefix18=1; ] {}\n@endif\n\n:ABA is (Prefix18=1 & op8=0x06)\n{\n\tresult:1 = A + B;\n\taddition_flags1(A, B, result);\n\tA = result;\n}\n\n:ABX is Prefix18=0 & (op16=0x1AE5)\n{\n\tIX = zext(B) + IX;\n}\n\n:ABY is Prefix18=0 & (op16=0x19ED)\n{\n\tIY = zext(B) + IY;\n}\n\n:ADCA iopr8i is Prefix18=0 & (op8=0x89); iopr8i\n{\n\top1:1 = iopr8i;\n\n\tlocal result:1;\n\tadditionWithCarry(A, op1, result);\n\t\n\tA = result;\n}\n\n:ADCA opr8a_8 is Prefix18=0 & (op8=0x99); opr8a_8\n{\n\top1:1 = opr8a_8;\n\n\tlocal result:1;\n\tadditionWithCarry(A, op1, result);\n\t\n\tA = result;\n}\n\n:ADCA opr16a_8 is Prefix18=0 & (op8=0xB9); opr16a_8\n{\n\top1:1 = opr16a_8;\n\n\tlocal result:1;\n\tadditionWithCarry(A, op1, result);\n\t\n\tA = result;\n}\n\n:ADCA indexed1_5 is Prefix18=0 & (op8=0xA9); indexed1_5\n{\n\top1:1 = indexed1_5;\n\n\tresult:1 = A + op1 + $(C);\n\taddition_flags1(A, op1, result);\n\tA = result;\n}\n\n:ADCB iopr8i is Prefix18=0 & (op8=0xC9); iopr8i\n{\n\top1:1 = iopr8i;\n\n\tlocal result:1;\n\tadditionWithCarry(A, op1, result);\n\t\n\tB = result;\n}\n\n:ADCB opr8a_8 is Prefix18=0 & (op8=0xD9); opr8a_8\n{\n\top1:1 = opr8a_8;\n\n\tresult:1 = B + op1 + $(C);\n\taddition_flags1(B, op1, result);\n\tB = result;\n}\n\n:ADCB opr16a_8 is Prefix18=0 & (op8=0xF9); opr16a_8\n{\n\top1:1 = opr16a_8;\n\n\tlocal result:1;\n\tadditionWithCarry(B, op1, result);\n\t\n\tB = result;\n}\n\n:ADCB indexed1_5 is Prefix18=0 & (op8=0xE9); indexed1_5\n{\n\top1:1 = indexed1_5;\n\t\n\tlocal result:1;\n\tadditionWithCarry(B, op1, result);\n\n\tB = result;\n}\n\n:ADDA iopr8i is Prefix18=0 & (op8=0x8B); iopr8i\n{ \n\top1:1 = iopr8i;\n\n\tresult:1 = A + op1;\n\taddition_flags1(A, op1, result);\n\n\tA = result;\n}\n\n:ADDA opr8a_8 is Prefix18=0 & (op8=0x9B); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\n\tresult:1 = A + op1;\n\taddition_flags1(A, op1, result);\n\tA = result;\n}\n\n:ADDA opr16a_8 is Prefix18=0 & (op8=0xBB); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\n\tresult:1 = A + op1;\n\taddition_flags1(A, op1, result);\n\tA = result;\n}\n\n:ADDA indexed1_5 is Prefix18=0 & (op8=0xAB); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\n\tresult:1 = A + op1;\n\taddition_flags1(A, op1, result);\n\tA = result;\n}\n\n:ADDB iopr8i is Prefix18=0 & (op8=0xCB); iopr8i\n{ \n\top1:1 = iopr8i;\n\n\tresult:1 = B + op1;\n\taddition_flags1(B, op1, result);\n\tB = result;\n}\n\n:ADDB opr8a_8 is Prefix18=0 & (op8=0xDB); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\n\tresult:1 = B + op1;\n\taddition_flags1(B, op1, result);\n\tB = result;\n}\n\n:ADDB opr16a_8 is Prefix18=0 & (op8=0xFB); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\n\tresult:1 = B + op1;\n\taddition_flags1(B, op1, result);\n\tB = result;\n}\n\n:ADDB indexed1_5 is Prefix18=0 & (op8=0xEB); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\n\tresult:1 = B + op1;\n\taddition_flags1(B, op1, result);\n\tB = result;\n}\n\n:ADDD iopr16i is Prefix18=0 & (op8=0xC3); iopr16i\n{ \n\top1:2 = iopr16i;\n\n\tresult:2 = D + op1;\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n\n:ADDD opr8a_16 is Prefix18=0 & (op8=0xD3); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\n\tresult:2 = D + op1;\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n\n:ADDD opr16a_16 is Prefix18=0 & (op8=0xF3); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\n\tresult:2 = D + op1;\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n\n:ADDD indexed2_5 is Prefix18=0 & (op8=0xE3); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\n\tresult:2 = D + op1;\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n\n@if defined(HCS12X)\n:ADDX iopr16i is Prefix18=1 & (op8=0x8B); iopr16i\n{ \n\top1:2 = iopr16i;\n\n\tresult:2 = IX + op1;\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDX opr8a_16 is Prefix18=1 & (op8=0x9B); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\n\tresult:2 = IX + op1;\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDX opr16a_16 is Prefix18=1 & (op8=0xBB); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\n\tresult:2 = IX + op1;\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDX indexed2_5 is Prefix18=1 & (op8=0xAB); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\n\tresult:2 = IX + op1;\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDY iopr16i is Prefix18=1 & (op8=0xCB); iopr16i\n{ \n\top1:2 = iopr16i;\n\n\tresult:2 = IY + op1;\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDY opr8a_16 is Prefix18=1 & (op8=0xDB); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\n\tresult:2 = IY + op1;\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDY opr16a_16 is Prefix18=1 & (op8=0xFB); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\n\tresult:2 = IY + op1;\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADDY indexed2_5 is Prefix18=1 & (op8=0xEB); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\n\tresult:2 = IY + op1;\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADED iopr16i is Prefix18=1 & (op8=0xC3); iopr16i\n{ \n\top1:2 = iopr16i;\n\n\tresult:2 = D + op1 + zext($(C));\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADED opr8a_16 is Prefix18=1 & (op8=0xD3); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\n\tresult:2 = D + op1 + zext($(C));\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADED opr16a_16 is Prefix18=1 & (op8=0xF3); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\n\tresult:2 = D + op1 + zext($(C));\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADED indexed2_5 is Prefix18=1 & (op8=0xE3); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\n\tresult:2 = D + op1 + zext($(C));\n\taddition_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEX iopr16i is Prefix18=1 & (op8=0x89); iopr16i\n{ \n\top1:2 = iopr16i;\n\n\tresult:2 = IX + op1 + zext($(C));\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEX opr8a_16 is Prefix18=1 & (op8=0x99); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\n\tresult:2 = IX + op1 + zext($(C));\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEX opr16a_16 is Prefix18=1 & (op8=0xb9); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\n\tresult:2 = IX + op1 + zext($(C));\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEX indexed2_5 is Prefix18=1 & (op8=0xa9); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\n\tresult:2 = IX + op1 + zext($(C));\n\taddition_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEY iopr16i is Prefix18=1 & (op8=0xC9); iopr16i\n{ \n\top1:2 = iopr16i;\n\n\tresult:2 = IY + op1 + zext($(C));\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEY opr8a_16 is Prefix18=1 & (op8=0xD9); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\n\tresult:2 = IY + op1 + zext($(C));\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEY opr16a_16 is Prefix18=1 & (op8=0xF9); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\n\tresult:2 = IY + op1 + zext($(C));\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:ADEY indexed2_5 is Prefix18=1 & (op8=0xE9); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\n\tresult:2 = IY + op1 + zext($(C));\n\taddition_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n:ANDA iopr8i is Prefix18=0 & (op8=0x84); iopr8i\n{ \n\tA = A & iopr8i;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n\n:ANDA opr8a_8 is Prefix18=0 & (op8=0x94); opr8a_8\n{ \n\tA = A & opr8a_8;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n\n:ANDA opr16a_8 is Prefix18=0 & (op8=0xB4); opr16a_8\n{ \n\tA = A & opr16a_8;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n\n:ANDA indexed1_5 is Prefix18=0 & (op8=0xA4); indexed1_5\n{ \n\tA = A & indexed1_5;\n\tV_equals_0(); \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n}\n\n:ANDB iopr8i is Prefix18=0 & (op8=0xC4); iopr8i\n{ \n\tB = B & iopr8i;\n\tV_equals_0(); \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n}\n\n:ANDB opr8a_8 is Prefix18=0 & (op8=0xD4); opr8a_8\n{ \n\tB = B & opr8a_8;\n\tV_equals_0(); \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n}\n\n:ANDB opr16a_8 is Prefix18=0 & (op8=0xF4); opr16a_8\n{ \n\tB = B & opr16a_8;\n\tV_equals_0(); \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n}\n\n:ANDB indexed1_5 is Prefix18=0 & (op8=0xE4); indexed1_5\n{ \n\tB = B & indexed1_5;\n\tV_equals_0(); \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n}\n\n:ANDCC iopr8i is Prefix18=0 & (op8=0x10); iopr8i\n{ \n\tCCR = CCR & iopr8i;\n}\n\n@if defined(HCS12X)\n:ANDX iopr16i is Prefix18=1 & (op8=0x84); iopr16i\n{ \n\tIX = IX & iopr16i;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDX opr8a_16 is Prefix18=1 & (op8=0x94); opr8a_16\n{ \n\tIX = IX & opr8a_16;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDX opr16a_16 is Prefix18=1 & (op8=0xB4); opr16a_16\n{ \n\tIX = IX & opr16a_16;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDX indexed2_5 is Prefix18=1 & (op8=0xA4); indexed2_5\n{ \n\tIX = IX & indexed2_5;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDY iopr16i is Prefix18=1 & (op8=0xC4); iopr16i\n{ \n\tIY = IY & iopr16i;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDY opr8a_16 is Prefix18=1 & (op8=0xD4); opr8a_16\n{ \n\tIY = IY & opr8a_16;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDY opr16a_16 is Prefix18=1 & (op8=0xF4); opr16a_16\n{ \n\tIY = IY & opr16a_16;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ANDY indexed2_5 is Prefix18=1 & (op8=0xE4); indexed2_5\n{ \n\tIY = IY & indexed2_5;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n:ASL opr16a_8 is Prefix18=0 & (op8=0x78); opr16a_8\n{\n\ttmp:1 = opr16a_8;\n\t$(C) = tmp[7,1];\n\ttmp = tmp << 1;\n\topr16a_8 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n\n:ASL indexed1_5 is Prefix18=0 & (op8=0x68); indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\t$(C) = tmp[7,1];\n\ttmp = tmp << 1;\n\tindexed1_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n\n:ASLA is Prefix18=0 & op8=0x48 \n{\n\t$(C) = A[7,1];\n\tA = A << 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ASLB is Prefix18=0 & op8=0x58 \n{\n\t$(C) = B[7,1];\n\tB = B << 1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ASLD is Prefix18=0 & op8=0x59 \n{\n\t$(C) = D[15,1];\n\tD = D << 1;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n@if defined(HCS12X)\n:ASLW opr16a_16 is Prefix18=1 & (op8=0x78); opr16a_16\n{\n\tlocal tmp = opr16a_16;\n\t$(C) = tmp[15,1];\n\ttmp = tmp << 1;\n\topr16a_16 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ASLW indexed2_5 is Prefix18=1 & (op8=0x68); indexed2_5 \n{\n\tlocal tmp = indexed2_5;\n\t$(C) = tmp[15,1];\n\ttmp = tmp << 1;\n\tindexed2_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ASLX is Prefix18=1 & op8=0x48\n{\n\t$(C) = IX[15,1];\n\tIX = IX << 1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ASLY is Prefix18=1 & op8=0x58\n{\n\t$(C) = IY[15,1];\n\tIY = IY << 1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n:ASR opr16a_8 is Prefix18=0 & (op8=0x77); opr16a_8\n{\n\ttmp:1 = opr16a_8;\n\t$(C) = tmp[0,1];\n\ttmp = tmp s>> 1;\n\topr16a_8 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ASR indexed1_5 is Prefix18=0 & (op8=0x67); indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\t$(C) = tmp[0,1];\n\ttmp = tmp s>> 1;\n\tindexed1_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ASRA is Prefix18=0 & op8=0x47 \n{\n\t$(C) = A[0,1];\n\tA = A s>> 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ASRB is Prefix18=0 & op8=0x57 \n{\n\t$(C) = B[0,1];\n\tB = B s>> 1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n@if defined(HCS12X)\n:ASRW opr16a_16 is Prefix18=1 & (op8=0x77); opr16a_16\n{\n\tlocal tmp = opr16a_16;\n\t$(C) = tmp[0,1];\n\ttmp = tmp s>> 1;\n\topr16a_16 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ASRW indexed2_5 is Prefix18=1 & (op8=0x67); indexed2_5 \n{\n\tlocal tmp = indexed2_5;\n\t$(C) = tmp[0,1];\n\ttmp = tmp s>> 1;\n\tindexed2_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ASRX is Prefix18=1 & op8=0x47 \n{\n\t$(C) = IX[0,1];\n\tIX = IX s>> 1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ASRY is Prefix18=1 & op8=0x57 \n{\n\t$(C) = IY[0,1];\n\tIY = IY s>> 1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n:BCC rel8 is Prefix18=0 & op8=0x24; rel8\n{\n\tif ($(C) == 0) goto rel8;\n}\n\n:BCLR opr8a_8, msk8\t\tis Prefix18=0 & (op8=0x4D); opr8a_8; msk8\n{\n\top1:1 = opr8a_8;\n\top1 = op1 & ~msk8;\n\topr8a_8 = op1;\n\t$(N) = (op1 s< 0);\n\t$(Z) = (op1 == 0);\n\tV_equals_0(); \n}\n\n:BCLR opr16a_8, msk8\tis Prefix18=0 & (op8=0x1D); opr16a_8; msk8\n{\n\top1:1 = opr16a_8;\n\top1 = op1 & ~msk8;\n\topr16a_8 = op1;\n\t$(N) = (op1 s< 0);\n\t$(Z) = (op1 == 0);\n\tV_equals_0(); \n}\n\n:BCLR indexed1_3, msk8\tis Prefix18=0 & (op8=0x0D); indexed1_3; msk8\n{\n\top1:1 = indexed1_3;\n\top1 = op1 & ~msk8;\n\tindexed1_3 = op1;\n\t$(N) = (op1 s< 0);\n\t$(Z) = (op1 == 0);\n\tV_equals_0(); \n}\n\n:BCS rel8 is Prefix18=0 & op8=0x25; rel8\n{\n\tif ($(C) == 1) goto rel8;\n}\n\n:BEQ rel8 is Prefix18=0 & op8=0x27; rel8\n{\n\tif ($(Z) == 1) goto rel8;\n}\n\n:BGE rel8 is Prefix18=0 & op8=0x2C; rel8\n{\n\tif (($(N) ^ $(V)) == 1) goto rel8;\n}\n\n@if defined(HCS12)\n:BGND is Prefix18=0 & op8=0x00\n{\n\tBDM_return:$(SIZE) = inst_next;\n\t# this could return BDM location, or BDM_return\n\tPCE = backgroundDebugMode(BDM_return);\n\tgoto [PCE];\n}\n@endif\n\n:BGT rel8 is Prefix18=0 & op8=0x2E; rel8\n{\n\tif (($(Z) | ($(N) ^ $(V))) == 0) goto rel8;\n}\n\n:BHI rel8 is Prefix18=0 & op8=0x22; rel8\n{\n\tif (($(C) | $(Z)) == 0) goto rel8;\n}\n\n#:BHS rel8\tis op8=0x24; rel8\t\tSee BCC\n\n:BITA iopr8i is Prefix18=0 & (op8=0x85); iopr8i\n{\n\tresult:1 = A & iopr8i;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITA opr8a_8 is Prefix18=0 & (op8=0x95); opr8a_8\n{\n\tresult:1 = A & opr8a_8;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITA opr16a_8 is Prefix18=0 & (op8=0xB5); opr16a_8\n{\n\tresult:1 = A & opr16a_8;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITA indexed1_5 is Prefix18=0 & (op8=0xA5); indexed1_5\n{\n\tresult:1 = A & indexed1_5;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITB iopr8i is Prefix18=0 & (op8=0xC5); iopr8i\n{\n\tresult:1 = B & iopr8i;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITB opr8a_8 is Prefix18=0 & (op8=0xD5); opr8a_8\n{\n\tresult:1 = B & opr8a_8;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITB opr16a_8 is Prefix18=0 & (op8=0xF5); opr16a_8\n{\n\tresult:1 = B & opr16a_8;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n:BITB indexed1_5 is Prefix18=0 & (op8=0xE5); indexed1_5\n{\n\tresult:1 = B & indexed1_5;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n\n@if defined(HCS12X)\n:BITX iopr16i is Prefix18=1 & (op8=0x85); iopr16i\n{\n\tlocal result = IX & iopr16i;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITX opr8a_16 is Prefix18=1 & (op8=0x95); opr8a_16\n{\n\tlocal result = IX & opr8a_16;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITX opr16a_16 is Prefix18=1 & (op8=0xB5); opr16a_16\n{\n\tlocal result = IX & opr16a_16;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITX indexed2_5 is Prefix18=1 & (op8=0xA5); indexed2_5\n{\n\tlocal result = IX & indexed2_5;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITY iopr16i is Prefix18=1 & (op8=0xC5); iopr16i\n{\n\tlocal result = IY & iopr16i;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITY opr8a_16 is Prefix18=1 & (op8=0xD5); opr8a_16\n{\n\tlocal result = IY & opr8a_16;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITY opr16a_16 is Prefix18=1 & (op8=0xF5); opr16a_16\n{\n\tlocal result = IY & opr16a_16;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:BITY indexed2_5 is Prefix18=1 & (op8=0xE5); indexed2_5\n{\n\tlocal result = IY & indexed2_5;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_equals_0();\n}\n@endif\n\n\n:BLE rel8 is Prefix18=0 & op8=0x2F; rel8\n{\n\tif ($(Z) | ($(N) ^ $(V))) goto rel8;\n}\n\n#:BLO rel8\tis op8=0x25; rel8\t\tsee BCS\n\n:BLS rel8 is Prefix18=0 & op8=0x23; rel8\n{\n\tif (($(C) | $(Z)) == 1) goto rel8;\n}\n\n:BLT rel8 is Prefix18=0 & op8=0x2D; rel8\n{\n\tif (($(N) ^ $(V)) ==1) goto rel8;\n}\n\n:BMI rel8 is Prefix18=0 & op8=0x2B; rel8\n{\n\tif ($(N) == 1) goto rel8;\n}\n\n:BNE rel8 is Prefix18=0 & op8=0x26; rel8\n{\n\tif ($(Z) == 0) goto rel8;\n}\n\n:BPL rel8 is Prefix18=0 & op8=0x2A; rel8\n{\n\tif ($(N) == 0) goto rel8;\n}\n\n:BRA rel8 is Prefix18=0 & op8=0x20; rel8\n{\n\tgoto rel8;\n}\n\n:BRCLR opr8a_8, msk8, rel8 is Prefix18=0 & op8=0x4F; opr8a_8; msk8; rel8\n{\n\tresult:1 = opr8a_8 & msk8;\n\tif (result == 0) goto rel8;\n}\n\n:BRCLR opr16a_8, msk8, rel8 is Prefix18=0 & op8=0x1F; opr16a_8; msk8; rel8\n{\n\tresult:1 = opr16a_8 & msk8;\n\tif (result == 0) goto rel8;\n}\n\n:BRCLR indexed1_3, msk8, rel8 is Prefix18=0 & op8=0x0F; indexed1_3; msk8; rel8\n{\n\tresult:1 = indexed1_3 & msk8;\n\tif (result == 0) goto rel8;\n}\n\n# branch never is a two-byte nop\nSkipNextInstr: dest is epsilon [ dest = inst_next + 1; ] { export *[RAM]:1 dest; }\n\n:BRN SkipNextInstr is Prefix18=0 & op8=0x21 & SkipNextInstr\n{\n\tgoto SkipNextInstr;\n}\n\n:BRSET opr8a_8, msk8, rel8 is Prefix18=0 & op8=0x4E; opr8a_8; msk8; rel8\n{\n\tresult:1 = ~opr8a_8 & msk8;\n\tif (result != 0) goto rel8;\n}\n\n:BRSET opr16a_8, msk8, rel8 is Prefix18=0 & op8=0x1E; opr16a_8; msk8; rel8\n{\n\tresult:1 = ~opr16a_8 & msk8;\n\tif (result != 0) goto rel8;\n}\n\n:BRSET indexed1_3, msk8, rel8 is Prefix18=0 & op8=0x0E; indexed1_3; msk8; rel8\n{\n\tresult:1 = ~indexed1_3 & msk8;\n\tif (result != 0) goto rel8;\n}\n\n:BSET opr8a_8, msk8 is Prefix18=0 & op8=0x4C; opr8a_8; msk8\n{\n\tresult:1 = opr8a_8 | msk8;\n\topr8a_8 = result;\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\tV_equals_0();\n}\n\n:BSET opr16a_8, msk8 is Prefix18=0 & op8=0x1C; opr16a_8; msk8\n{\n\tresult:1 = opr16a_8 | msk8;\n\topr16a_8 = result;\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\tV_equals_0();\n}\n\n:BSET indexed1_3, msk8 is Prefix18=0 & op8=0x0C; indexed1_3; msk8\n{\n\tresult:1 = indexed1_3 | msk8;\n\tindexed1_3 = result;\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\tV_equals_0();\n}\n\n:BSR rel8 is Prefix18=0 & op8=0x07; rel8 \n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t \n\tcall rel8;\n}\n\n@if defined(HCS12X)\n:BTAS opr8a_8, msk8 is Prefix18=1 & (op8=0x35); opr8a_8; msk8\n{ \n\top1:1 = opr8a_8;\n\ttmp:1 = op1 & msk8;\n\t$(N) = tmp[7,1];\n\t$(Z) = (tmp == 0);\n\t$(V) = 0;\n\topr8a_8 = op1 | msk8;\n}\n@endif\n\n@if defined(HCS12X)\n:BTAS opr16a_8, msk8 is Prefix18=1 & (op8=0x36); opr16a_8; msk8\n{ \n\top1:1 = opr16a_8;\n\ttmp:1 = op1 & msk8;\n\t$(N) = tmp[7,1];\n\t$(Z) = (tmp == 0);\n\t$(V) = 0;\n\topr16a_8 = op1 | msk8;\n}\n@endif\n\n@if defined(HCS12X)\n:BTAS indexed1_3, msk8 is Prefix18=1 & (op8=0x37); indexed1_3; msk8\n{ \n\top1:1 = indexed1_3;\n\ttmp:1 = op1 & msk8;\n\t$(N) = tmp[7,1];\n\t$(Z) = (tmp == 0);\n\t$(V) = 0;\n\tindexed1_3 = op1 | msk8;\n}\n@endif\n\n\n:BVC rel8 is Prefix18=0 & op8=0x28; rel8\n{\n\tif ($(V) == 0) goto rel8;\n}\n\n:BVS rel8 is Prefix18=0 & op8=0x29; rel8\n{\n\tif ($(V) == 1) goto rel8;\n}\n\n@ifdef HCS12\nCallDest: PageDest, imm8 is (imm16; imm8) & PageDest {\n\tPPAGE = imm8;\n\n\tbuild PageDest;\n\t\n\texport PageDest;\n}\n\n:CALL CallDest is Prefix18=0 & op8=0x4A; CallDest\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\n\tlocal ppage_tmp:1 = PPAGE;\n\tPush1( PPAGE );\t\n build CallDest;\n \n local dest:$(SIZE) = CallDest;\n\tcall [dest];\n\t\n\tPPAGE = ppage_tmp;\n}\n\n:CALL indexed2_3, page is Prefix18=0 & (op8=0x4B); indexed2_3; page \n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\n\tlocal ppage_tmp:1 = PPAGE;\n\tPush1( PPAGE );\n\tPPAGE = page;\n\t\n\tbuild indexed2_3;\n\n\tlocal dest:$(SIZE);\t\n\tGetPagedAddr(indexed2_3,dest);\n\tcall [dest];\n\tPPAGE = ppage_tmp;\n}\n\n:CALL indexed0_2 is Prefix18=0 & (op8=0x4B); indexed0_2 \n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\n\tlocal ppage_tmp:1 = PPAGE;\n\tPush1( PPAGE );\n\tLoad1(PPAGE, indexed0_2 + 2);\n\n\tlocal addr:2;\n\tLoad2(addr,indexed0_2);\n\t\n\tlocal dest:$(SIZE);\t\n\tGetPagedAddr(addr,dest);\n\tcall [dest];\n\t\n\tPPAGE = ppage_tmp;\n}\n@endif\n\n:CBA is (Prefix18=1 & op8=0x17)\n{ \n\ttmp:1 = A - B;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(A, B);\n\t$(C) = (B > A);\n}\n\n:CLC is Prefix18=0 & op16=0x10FE\n{\n\t$(C) = 0;\n}\n\n:CLI is Prefix18=0 & op16=0x10EF\n{\n\t$(I) = 0;\n}\n\n:CLR opr16a_8 is Prefix18=0 & (op8=0x79); opr16a_8\n{\n\topr16a_8 = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n\n:CLR indexed1_5 is Prefix18=0 & (op8=0x69); indexed1_5 \n{\n\tindexed1_5 = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n\n:CLRA is Prefix18=0 & op8=0x87 \n{\n\tA = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n\n:CLRB is Prefix18=0 & op8=0xC7 \n{\n\tB = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n\n@if defined(HCS12X)\n:CLRW opr16a_16 is Prefix18=1 & (op8=0x79); opr16a_16\n{\n\topr16a_16 = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n@endif\n\n@if defined(HCS12X)\n:CLRW indexed2_5 is Prefix18=1 & (op8=0x69); indexed2_5 \n{\n\tindexed2_5 = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n@endif\n\n@if defined(HCS12X)\n:CLRX is Prefix18=1 & op8=0x87 \n{\n\tIX = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n@endif\n\n@if defined(HCS12X)\n:CLRY is Prefix18=1 & op8=0xC7 \n{\n\tIY = 0;\n\t$(N) = 0;\n\t$(Z) = 1;\n\tV_equals_0();\n\t$(C) = 0;\n}\n@endif\n\n:CLV is Prefix18=0 & op16=0x10FD\n{\n\t$(V) = 0;\n}\n\n:CMPA iopr8i is Prefix18=0 & (op8=0x81); iopr8i\n{ \n\top1:1 = iopr8i;\n\ttmp:1 = A - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(A, op1);\n\t$(C) = (op1 > A);\n}\n\n:CMPA opr8a_8 is Prefix18=0 & (op8=0x91); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\ttmp:1 = A - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(A, op1);\n\t$(C) = (op1 > A);\n}\n\n:CMPA opr16a_8 is Prefix18=0 & (op8=0xB1); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\ttmp:1 = A - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(A, op1);\n\t$(C) = (op1 > A);\n}\n\n:CMPA indexed1_5 is Prefix18=0 & (op8=0xA1); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\ttmp:1 = A - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(A, op1);\n\t$(C) = (op1 > A);\n}\n\n:CMPB iopr8i is Prefix18=0 & (op8=0xC1); iopr8i\n{ \n\top1:1 = iopr8i;\n\ttmp:1 = B - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(B, op1);\n\t$(C) = (op1 > B);\n}\n\n:CMPB opr8a_8 is Prefix18=0 & (op8=0xD1); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\ttmp:1 = B - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(B, op1);\n\t$(C) = (op1 > B);\n}\n\n:CMPB opr16a_8 is Prefix18=0 & (op8=0xF1); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\ttmp:1 = B - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(B, op1);\n\t$(C) = (op1 > B);\n}\n\n:CMPB indexed1_5 is Prefix18=0 & (op8=0xE1); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\ttmp:1 = B - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\tV_CMP_flag(B, op1);\n\t$(C) = (op1 > B);\n}\n\n:COM opr16a_8 is Prefix18=0 & (op8=0x71); opr16a_8\n{\n\ttmp:1 = ~opr16a_8;\n\topr16a_8 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n\n:COM indexed1_5 is Prefix18=0 & (op8=0x61); indexed1_5 \n{\n\ttmp:1 = ~indexed1_5;\n\tindexed1_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n\n:COMA is Prefix18=0 & op8=0x41 \n{\n\tA = ~A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n\n:COMB is Prefix18=0 & op8=0x51 \n{\n\tB = ~B;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n\n@if defined(HCS12X)\n:COMW opr16a_16 is Prefix18=1 & (op8=0x71); opr16a_16\n{\n\tlocal tmp = ~opr16a_16;\n\topr16a_16 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:COMW indexed2_5 is Prefix18=1 & (op8=0x61); indexed2_5 \n{\n\tlocal tmp = ~indexed2_5;\n\tindexed2_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:COMX is Prefix18=1 & op8=0x41 \n{\n\tIX = ~IX;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:COMY is Prefix18=1 & op8=0x51 \n{\n\tIY = ~IY;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\t$(C) = 1;\n\tV_equals_0();\n}\n@endif\n\n:CPD iopr16i is Prefix18=0 & (op8=0x8C); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = D - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n\n:CPD opr8a_16 is Prefix18=0 & (op8=0x9C); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = D - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n\n:CPD opr16a_16 is Prefix18=0 & (op8=0xBC); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = D - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n\n:CPD indexed2_5 is Prefix18=0 & (op8=0xAC); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = D - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n\n@if defined(HCS12X)\n:CPED iopr16i is Prefix18=1 & (op8=0x8C); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = D - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPED opr8a_16 is Prefix18=1 & (op8=0x9C); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = D - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPED opr16a_16 is Prefix18=1 & (op8=0xBC); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = D - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPED indexed2_5 is Prefix18=1 & (op8=0xAC); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = D - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > D);\n\tV_CMP_flag(D, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPES iopr16i is Prefix18=1 & (op8=0x8F); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = SP - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPES opr8a_16 is Prefix18=1 & (op8=0x9F); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = SP - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPES opr16a_16 is Prefix18=1 & (op8=0xBF); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = SP - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPES indexed2_5 is Prefix18=1 & (op8=0xAF); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = SP - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEX iopr16i is Prefix18=1 & (op8=0x8E); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = IX - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEX opr8a_16 is Prefix18=1 & (op8=0x9E); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = IX - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEX opr16a_16 is Prefix18=1 & (op8=0xBE); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = IX - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEX indexed2_5 is Prefix18=1 & (op8=0xAE); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = IX - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEY iopr16i is Prefix18=1 & (op8=0x8D); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = IY - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEY opr8a_16 is Prefix18=1 & (op8=0x9D); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = IY - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEY opr16a_16 is Prefix18=1 & (op8=0xBD); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = IY - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n@endif\n\n@if defined(HCS12X)\n:CPEY indexed2_5 is Prefix18=1 & (op8=0xAD); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = IY - (op1 + zext($(C)));\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n@endif\n\nSkipNext2Bytes: dest is epsilon [ dest = inst_next + 2; ] { export *[RAM]:1 dest; }\n\n:CPS loc is Prefix18=0 & (op8=0x8F) & SkipNext2Bytes [ loc = (inst_next & 0xffffff); ]\n{ \n\tlocal addr:$(SIZE) = inst_next;\n\tlocal op1:2 = *[RAM]:2 addr;\n\ttmp:2 = SP - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n\tgoto SkipNext2Bytes;\n}\n\n:CPS opr8a_16 is Prefix18=0 & (op8=0x9F); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = SP - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n}\n\n:CPS loc is Prefix18=0 & (op8=0xBF) & SkipNext2Bytes [ loc = (inst_next & 0xffffff); ]\n{\n\tlocal addr:$(SIZE) = inst_next;\n\tlocal op1:2 = *[RAM]:2 addr;\n\tLoad2(op1, op1);\n\ttmp:2 = SP - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n\tgoto SkipNext2Bytes;\n}\n\n:CPS indexed2_5 is Prefix18=0 & (op8=0xAF); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = SP - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > SP);\n\tV_CMP_flag(SP, op1);\n}\n\n:CPX iopr16i is Prefix18=0 & (op8=0x8E); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = IX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n\n:CPX opr8a_16 is Prefix18=0 & (op8=0x9E); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = IX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n\n:CPX opr16a_16 is Prefix18=0 & (op8=0xBE); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = IX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n\n:CPX indexed2_5 is Prefix18=0 & (op8=0xAE); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = IX - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IX);\n\tV_CMP_flag(IX, op1);\n}\n\n:CPY iopr16i is Prefix18=0 & (op8=0x8D); iopr16i\n{ \n\top1:2 = iopr16i;\n\ttmp:2 = IY - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n\n:CPY opr8a_16 is Prefix18=0 & (op8=0x9D); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\ttmp:2 = IY - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n\n:CPY opr16a_16 is Prefix18=0 & (op8=0xBD); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\ttmp:2 = IY - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n\n:CPY indexed2_5 is Prefix18=0 & (op8=0xAD); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\ttmp:2 = IY - op1;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\t$(C) = (op1 > IY);\n\tV_CMP_flag(IY, op1);\n}\n\n:DAA is Prefix18=1 & op8=0x07 \n{\n\tA = decimalAdjustAccumulator(A, $(C), $(H));\n\t$(C) = decimalAdjustCarry(A, $(C), $(H));\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\t#V is undefined\n}\n\n:DBEQ byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x0 & size10_10=0 & byte9_8 & rel9\n{\n\tbyte9_8 = byte9_8 - 1;\n\tif (byte9_8 == 0) goto rel9;\n}\n\n:DBEQ word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x0 & size10_10=1 & word9_8 & rel9\n{\n\tword9_8 = word9_8 - 1;\n\tif (word9_8 == 0) goto rel9;\n}\n\n:DBNE byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x1 & size10_10=0 & byte9_8 & rel9\n{\n\tbyte9_8 = byte9_8 - 1;\n\tif (byte9_8 != 0) goto rel9;\n}\n\n:DBNE word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x1 & size10_10=1 & word9_8 & rel9\n{\n\tword9_8 = word9_8 - 1;\n\tif (word9_8 != 0) goto rel9;\n}\n\n:DEC opr16a_8 is Prefix18=0 & (op8=0x73); opr16a_8\n{\n\ttmp:1 = opr16a_8;\n\tresult:1 = tmp - 1;\n\topr16a_8 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_DEC_flag(tmp);\n}\n\n:DEC indexed1_5 is Prefix18=0 & (op8=0x63); indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:1 = tmp - 1;\n\tindexed1_5 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_DEC_flag(tmp);\n}\n\n:DECA is Prefix18=0 & op8=0x43 \n{\n\ttmp:1 = A;\n\tA = tmp - 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_DEC_flag(tmp);\n}\n\n:DECB is Prefix18=0 & op8=0x53 \n{\n\ttmp:1 = B;\n\tB = tmp - 1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_DEC_flag(tmp);\n}\n\n@if defined(HCS12X)\n:DECW opr16a_16 is Prefix18=1 & (op8=0x73); opr16a_16\n{\n\tlocal tmp = opr16a_16;\n\tlocal result = tmp - 1;\n\topr16a_16 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_DEC_flag2(tmp);\n}\n@endif\n\n@if defined(HCS12X)\n:DECW indexed2_5 is Prefix18=1 & (op8=0x63); indexed2_5 \n{\n\tlocal tmp = indexed2_5;\n\tlocal result = tmp - 1;\n\tindexed2_5 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_DEC_flag2(tmp);\n}\n@endif\n\n@if defined(HCS12X)\n:DECX is Prefix18=1 & op8=0x43 \n{\n\tlocal tmp = IX;\n\tIX = tmp - 1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_DEC_flag2(tmp);\n}\n@endif\n\n@if defined(HCS12X)\n:DECY is Prefix18=1 & op8=0x53 \n{\n\tlocal tmp = IY;\n\tIY = tmp - 1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_DEC_flag2(tmp);\n}\n@endif\n\n:DES is Prefix18=0 & op16=0x1B9F \n{\n\tSP = SP - 1;\n}\n\n:DEX is Prefix18=0 & op8=0x09 \n{\n\tIX = IX - 1;\n\t$(Z) = (IX == 0);\n}\n\n:DEY is Prefix18=0 & op8=0x03 \n{\n\tIY = IY - 1;\n\t$(Z) = (IY == 0);\n}\n\n:EDIV is Prefix18=0 & op8=0x11 \n{\n\ttmp:4 = (zext(IY) << 16) | (zext(D));\n\tresultQ:4 = tmp / zext(IX);\n\tresultR:4 = tmp % zext(IX);\n\tIY = resultQ:2;\n\tD = resultR:2;\n\t$(N) = (IY s< 0);\n\t$(Z) = (IY == 0);\n\t$(V) = (resultQ > 0x0000FFFF);\n\t$(C) = (IX == 0);\n}\n\n:EDIVS is Prefix18=1 & op8=0x14 \n{\n\ttmp:4 = (zext(IY) << 16) | (zext(D));\n\tresultQ:4 = tmp s/ sext(IX);\n\tresultR:4 = tmp s% sext(IX);\n\tIY = resultQ:2;\n\tD = resultR:2;\n\t$(N) = (IY s< 0);\n\t$(Z) = (IY == 0);\n\t$(V) = (resultQ s> 0x00007FFF) | (resultQ s< 0x00008000);\n\t$(C) = (IX == 0);\n}\n\n:EMACS opr16a is Prefix18=1 & op8=0x12; opr16a \n{\n\tlocal valx:2 = 0;\n\tlocal valy:2 = 0;\n\tLoad2(valx,IX);\n\tLoad2(valy,IY);\n\tresult:4 = sext(valx) * sext(valy);\n\tStore(opr16a, result);\n\t$(N) = (result s< 0);\n\t$(Z) = (result == 0);\n\t$(V) = (result s> 0x000000007FFFFFFF) | (result s< 0x0000000080000000);\n\t$(C) = (result > 0x00000000FFFFFFFF);\n}\n\n:EMAXD indexed2_5 is Prefix18=1 & op8=0x1A; indexed2_5 \n{\n\tresult:4 = zext(D) - zext(indexed2_5);\n\tif (D > indexed2_5) goto ;\n\t\tD = indexed2_5;\n\t\n\t\n\t$(N) = (result:2 s< 0);\n\t$(Z) = (result:2 == 0);\n\t$(V) = (result s> 0x00007FFF) | (result s< 0x00008000);\n\t$(C) = (result > 0x0000FFFF);\n}\n\n:EMAXM indexed2_5 is Prefix18=1 & op8=0x1E; indexed2_5 \n{\n\tresult:4 = zext(D) - zext(indexed2_5);\n\tif (D > indexed2_5) goto ;\n\t\tindexed2_5 = D;\n\t\n\t\n\t$(N) = (result:2 s< 0);\n\t$(Z) = (result:2 == 0);\n\t$(V) = (result s> 0x00007FFF) | (result s< 0x00008000);\n\t$(C) = (result > 0x0000FFFF);\n}\n\n:EMIND indexed2_5 is Prefix18=1 & op8=0x1B; indexed2_5 \n{\n\tresult:4 = zext(D) - zext(indexed2_5);\n\tif (D < indexed2_5) goto ;\n\t\tD = indexed2_5;\n\t\n\t\n\t$(N) = (result:2 s< 0);\n\t$(Z) = (result:2 == 0);\n\t$(V) = (result s> 0x00007FFF) | (result s< 0x00008000);\n\t$(C) = (result > 0x0000FFFF);\n}\n\n:EMINM indexed2_5 is Prefix18=1 & op8=0x1F; indexed2_5 \n{\n\tresult:4 = zext(D) - zext(indexed2_5);\n\tif (D < indexed2_5) goto ;\n\t\tindexed2_5 = D;\n\t\n\t\n\t$(N) = (result:2 s< 0);\n\t$(Z) = (result:2 == 0);\n\t$(V) = (result s> 0x00007FFF) | (result s< 0x00008000);\n\t$(C) = (result > 0x0000FFFF);\n}\n\n:EMUL is Prefix18=0 & op8=0x13\n{\n\tresult:4 = zext(D) * zext(IY);\n\tIY = result(2);\n\tD = result:2;\n\t$(N) = result[31,1];\n\t$(Z) = (result == 0);\n\t$(C) = result[15,1];\n}\n\n:EMULS is Prefix18=1 & op8=0x13\n{\n\tresult:4 = sext(D) * sext(IY);\n\tIY = result(2);\n\tD = result:2;\n\t$(N) = result[31,1];\n\t$(Z) = (result == 0);\n\t$(C) = result[15,1];\n}\n\n:EORA iopr8i is Prefix18=0 & (op8=0x88); iopr8i\n{ \n\top1:1 = iopr8i;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:EORA opr8a_8 is Prefix18=0 & (op8=0x98); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:EORA opr16a_8 is Prefix18=0 & (op8=0xB8); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:EORA indexed1_5 is Prefix18=0 & (op8=0xA8); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\tA = A ^ op1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:EORB iopr8i is Prefix18=0 & (op8=0xC8); iopr8i\n{ \n\top1:1 = iopr8i;\n\tB = B ^ op1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:EORB opr8a_8 is Prefix18=0 & (op8=0xD8); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\tB = B ^ op1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:EORB opr16a_8 is Prefix18=0 & (op8=0xF8); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\tB = B ^ op1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:EORB indexed1_5 is Prefix18=0 & (op8=0xE8); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\tB = B ^ op1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n@if defined(HCS12X)\n:EORX iopr16i is Prefix18=1 & (op8=0x88); iopr16i\n{ \n\tlocal op1 = iopr16i;\n\tIX = IX ^ op1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORX opr8a_16 is Prefix18=1 & (op8=0x98); opr8a_16\n{ \n\tlocal op1 = opr8a_16;\n\tIX = IX ^ op1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORX opr16a_16 is Prefix18=1 & (op8=0xB8); opr16a_16\n{ \n\tlocal op1 = opr16a_16;\n\tIX = IX ^ op1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORX indexed2_5 is Prefix18=1 & (op8=0xA8); indexed2_5\n{ \n\tlocal op1 = indexed2_5;\n\tIX = IX ^ op1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORY iopr16i is Prefix18=1 & (op8=0xC8); iopr16i\n{ \n\tlocal op1 = iopr16i;\n\tIY = IY ^ op1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORY opr8a_16 is Prefix18=1 & (op8=0xD8); opr8a_16\n{ \n\tlocal op1 = opr8a_16;\n\tIY = IY ^ op1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORY opr16a_16 is Prefix18=1 & (op8=0xF8); opr16a_16\n{ \n\tlocal op1 = opr16a_16;\n\tIY = IY ^ op1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n@endif\n\n@if defined(HCS12X)\n:EORY indexed2_5 is Prefix18=1 & (op8=0xE8); indexed2_5\n{ \n\tlocal op1 = indexed2_5;\n\tIY = IY ^ op1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n@endif\n\n:ETBL indexed2_1 is Prefix18=1 & op8=0x3F; indexed2_1 \n{\n\tD = ETBL( indexed2_1, B );\n\t$(N) = (D s< 0);\n\t$(Z) = (D == 0);\n\t$(C) = ETBL_Cflag( indexed2_1, B );\n}\n\n# this case 'C0' or 'C8', does not display similarly to other members of either its row or column\n:EXG D, A\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x0 & ( columns7_4=0xC ) ) |\n\n\t\t( rows3_0=0x8 & ( columns7_4=0xC ) ) \n\t) &\n\tD & A\n{\n\ttmp:1 = B;\n\tB = A;\n\tA = tmp;\n} \n\n# this case 'C1' or 'C9', does not work similarly to other members of either its row or column\n:EXG D, B\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x1 & ( columns7_4=0xC ) ) |\n\n\t\t( rows3_0=0x9 & ( columns7_4=0xC ) ) \n\t) &\n\tD & B\n{\n\tB = B;\n\tA = 0xFF;\n} \n\n# this case '84' or '8C', does not work similarly to other members of either its row or column\n:EXG A, D\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x4 & ( columns7_4=0x8 ) ) |\n\n\t\t( rows3_0=0xC & ( columns7_4=0x8 ) ) \n\t) &\n\tA & D\n{\n\tD = zext(A);\n} \n\n# this case '94' or '9C', does not work similarly to other members of either its row or column\n:EXG B, D\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x4 & ( columns7_4=0x9 ) ) |\n\n\t\t( rows3_0=0xC & ( columns7_4=0x9 ) ) \n\t) &\n\tB & D\n{\n\tD = zext(B);\n} \n\n# this case 'A8', does not work the same as 'A0'\n:EXG CCRH, A\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x8 & ( columns7_4=0xA ) ) \n\t) &\n\tCCRH & A\n{\n\ttmp:1 = CCRH;\n\tCCRH = A;\n\tA = tmp;\n} \n\n# this case '8A', does not work the same as '82'\n:EXG A, CCRH\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xA & ( columns7_4=0x8 ) ) \n\t) &\n\tA & CCRH\n{\n\ttmp:1 = A;\n\tA = CCRH;\n\tCCRH = tmp;\n} \n\n# this case 'AA', does not display the same as 'A2'\n:EXG CCRW, \"CCRW\"\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xA & ( columns7_4=0xA ) ) \n\t) &\n\tCCRW\n{\n\tCCRW = CCRW;\n} \n\n:EXG bytes_ABCl_6_4, bytes_ABCl_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x0 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\t\t( rows3_0=0x1 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\n\t\t( rows3_0=0x8 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\t\t( rows3_0=0x9 & ( columns7_4=0x8 | columns7_4=0x9 ) ) \n\t) &\n\tbytes_ABCl_6_4 & bytes_ABCl_2_0 \n{\n\ttmp:1 = bytes_ABCl_2_0;\n\tbytes_ABCl_2_0 = bytes_ABCl_6_4;\n\tbytes_ABCl_6_4 = tmp;\n}\n\n:EXG bytes_ABCl_6_4, CCR\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x2 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\n\t\t( rows3_0=0xA & ( columns7_4=0x9 ) ) \n\t) &\n\tbytes_ABCl_6_4 & CCR\n{\n\ttmp:1 = bytes_ABCl_6_4;\n\tbytes_ABCl_6_4 = CCR;\n\tsetCCR( tmp );\n}\n\n:EXG CCR, bytes_ABCl_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x0 & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0x1 & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0x2 & ( columns7_4=0xA ) ) |\n\n\t\t( rows3_0=0x9 & ( columns7_4=0xA ) ) \n\t) &\n\tCCR & bytes_ABCl_2_0 \n{\n\ttmp:1 = bytes_ABCl_2_0;\n\tbytes_ABCl_2_0 = CCR;\n\tsetCCR( tmp );\n}\n\n:EXG bytes_T3l_XlYlSl_6_4, A\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x0 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\tbytes_T3l_XlYlSl_6_4 & words_T3_XYS_6_4 & A \n{\n\ttmp:2 = zext(A);\n\tA = bytes_T3l_XlYlSl_6_4;\n\twords_T3_XYS_6_4 = tmp;\n}\n\n:EXG bytes_T3h_XhYhSh_6_4, A\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x8 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\tbytes_T3h_XhYhSh_6_4 & words_T3_XYS_6_4 & A \n{\n\ttmp:2 = zext(A);\n\tA = bytes_T3h_XhYhSh_6_4;\n\twords_T3_XYS_6_4 = tmp;\n}\n\n:EXG bytes_T3l_XlYlSl_6_4, B\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x1 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\tbytes_T3l_XlYlSl_6_4 & words_T3_XYS_6_4 & B \n{\n\ttmp:2 = 0xFF00 | zext(B);\n\tB = bytes_T3l_XlYlSl_6_4;\n\twords_T3_XYS_6_4 = tmp;\n}\n\n:EXG bytes_T3l_XlYlSl_6_4, B\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x9 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\tbytes_T3l_XlYlSl_6_4 & B \n{\n\ttmp:1 = B;\n\tB = bytes_T3l_XlYlSl_6_4;\n\tbytes_T3l_XlYlSl_6_4 = tmp;\n}\n\n:EXG bytes_T3lDlXlYlSl_6_4, CCR\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x2 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\tbytes_T3lDlXlYlSl_6_4 & words_T3DXYS_6_4 & CCR\n{\n\ttmp:2 = 0xFF00 | zext(CCR);\n\t# when CCR is the destination, cannot set the X bit unless it is already set in CCR\n\tsetCCR( bytes_T3lDlXlYlSl_6_4 );\n\twords_T3DXYS_6_4 = tmp;\n}\n\n:EXG words_T3DXYS_6_4, CCRW\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xA & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\twords_T3DXYS_6_4 & CCRW\n{\n\ttmp:2 = CCRW;\n\tsetCCRW( words_T3DXYS_6_4 );\n\twords_T3DXYS_6_4 = tmp;\n}\n\n# this case 'CB', does not work similarly to other members of either its row or column\n:EXG D, TMP1\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0xC ) ) \n\t) &\n \tD & TMP1\n{\n\ttmp:2 = D;\n\tD = TMP1;\n\tTMP1 = tmp;\n} \n\n# this case 'BC', does not work similarly to other members of either its row or column\n:EXG TMP1, D\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xC & ( columns7_4=0xB ) ) \n\t) &\n\tTMP1 & D\n{\n\ttmp:2 = TMP1;\n\tTMP1 = D;\n\tD = tmp;\n} \n\n:EXG words_T3DXYS_6_4, words_T2DXYS_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n# Case \"C5\" is handled by XGDX\n# Case \"C6\" is handled by XGDY\n\t\t( rows3_0=0x3 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0x4 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0x5 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0x6 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0x7 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\n\t\t( rows3_0=0xB & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0xC & ( columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0xD & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) \n\t) &\n\twords_T3DXYS_6_4 & words_T2DXYS_2_0 \n{\n\ttmp:2 = words_T3DXYS_6_4;\n\twords_T3DXYS_6_4 = words_T2DXYS_2_0;\n\twords_T2DXYS_2_0 = tmp;\n}\n\n:EXG bytes_ABCl_6_4, words_T2DXYS_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x3 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\n\t\t( rows3_0=0x5 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\t\t( rows3_0=0x6 & ( columns7_4=0x8 | columns7_4=0x9 ) ) |\n\t\t( rows3_0=0x7 & ( columns7_4=0x8 | columns7_4=0x9 ) ) \n\t) &\n\tbytes_ABCl_6_4 & words_T2DXYS_2_0 & bytes_T2lDlXlYlSl_2_0 \n{\n\ttmp:2 = zext(bytes_ABCl_6_4);\n\tbytes_ABCl_6_4 = bytes_T2lDlXlYlSl_2_0;\n\twords_T2DXYS_2_0 = tmp;\n}\n\n:EXG bytes_ABCl_6_4, bytes_T2hDhXhYhSh_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0x8 ) ) |\n\n\t\t( rows3_0=0xD & ( columns7_4=0x8 ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0x8 ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0x8 ) ) \n\t) &\n\tbytes_ABCl_6_4 & bytes_T2hDhXhYhSh_2_0 \n{\n\ttmp:1 = bytes_ABCl_6_4;\n\tbytes_ABCl_6_4 = bytes_T2hDhXhYhSh_2_0;\n\tbytes_T2hDhXhYhSh_2_0 = tmp;\n}\n\n# only column 9 with rows B, (skip C), D, E, and F\n:EXG bytes_ABCl_6_4, bytes_T2lDlXlYlSl_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0x9 ) ) |\n\n\t\t( rows3_0=0xD & ( columns7_4=0x9 ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0x9 ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0x9 ) ) \n\t) &\n\tbytes_ABCl_6_4 & bytes_T2lDlXlYlSl_2_0 \n{\n\ttmp:1 = bytes_ABCl_6_4;\n\tbytes_ABCl_6_4 = bytes_T2lDlXlYlSl_2_0;\n\tbytes_T2lDlXlYlSl_2_0 = tmp;\n}\n\n:EXG CCR, words_T2DXYS_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x3 & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0x4 & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0x5 & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0x6 & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0x7 & ( columns7_4=0xA ) ) \n\t) &\n\tCCR & words_T2DXYS_2_0 & bytes_T2lDlXlYlSl_2_0\n{\n\ttmp:2 = zext(CCR);\n\tsetCCR( bytes_T2lDlXlYlSl_2_0 );\n\twords_T2DXYS_2_0 = tmp;\n}\n\n:EXG CCRW, words_T2DXYS_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0xC & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0xD & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0xA ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0xA ) ) \n\t) &\n\tCCRW & words_T2DXYS_2_0\n{\n\ttmp:2 = CCRW;\n\tsetCCRW( words_T2DXYS_2_0 );\n\twords_T2DXYS_2_0 = tmp;\n}\n\n:FDIV is Prefix18=1 & op8=0x11 \n{\n\t$(V) = (IX <= D);\n\t$(C) = (IX == 0);\n\ttmp:4 = (zext(D) << 16);\n\tresultQ:4 = tmp / zext(IX);\n\tresultR:4 = tmp % zext(IX);\n\tIX = resultQ:2;\n\tD = resultR:2;\n\t$(Z) = (IX == 0);\n}\n\n#:GLDAA \tis op16=0x1896\t\tSee GPAGE extended LDAA\n#:GLDAA \tis op16=0x18B6\t\tSee GPAGE extended LDAA\n#:GLDAA \tis op16=0x18A6\t\tSee GPAGE extended LDAA\n\n#:GLDAB \tis op16=0x18D6\t\tSee GPAGE extended LDAB\n#:GLDAB \tis op16=0x18F6\t\tSee GPAGE extended LDAB\n#:GLDAB \tis op16=0x18E6\t\tSee GPAGE extended LDAB\n\n#:GLDD \tis op16=0x18DC\t\tSee GPAGE extended LDD\n#:GLDD \tis op16=0x18FC\t\tSee GPAGE extended LDD\n#:GLDD \tis op16=0x18EC\t\tSee GPAGE extended LDD\n\n#:GLDS \tis op16=0x18DF\t\tSee GPAGE extended LDS\n#:GLDS \tis op16=0x18FF\t\tSee GPAGE extended LDS\n#:GLDS \tis op16=0x18EF\t\tSee GPAGE extended LDS\n\n#:GLDX \tis op16=0x18DE\t\tSee GPAGE extended LDX\n#:GLDX \tis op16=0x18FE\t\tSee GPAGE extended LDX\n#:GLDX \tis op16=0x18EE\t\tSee GPAGE extended LDX\n\n#:GLDY \tis op16=0x18DD\t\tSee GPAGE extended LDY\n#:GLDY \tis op16=0x18FD\t\tSee GPAGE extended LDY\n#:GLDY \tis op16=0x18ED\t\tSee GPAGE extended LDY\n\n#:GSTAA \tis op16=0x185A\t\tSee GPAGE extended STAA\n#:GSTAA \tis op16=0x187A\t\tSee GPAGE extended STAA\n#:GSTAA \tis op16=0x186A\t\tSee GPAGE extended STAA\n\n#:GSTAB \tis op16=0x185B\t\tSee GPAGE extended STAB\n#:GSTAB \tis op16=0x187B\t\tSee GPAGE extended STAB\n#:GSTAB \tis op16=0x186B\t\tSee GPAGE extended STAB\n\n#:GSTD \tis op16=0x185C\t\tSee GPAGE extended STD\n#:GSTD \tis op16=0x187C\t\tSee GPAGE extended STD\n#:GSTD \tis op16=0x186C\t\tSee GPAGE extended STD\n\n#:GSTS \tis op16=0x185F\t\tSee GPAGE extended STS\n#:GSTS \tis op16=0x187F\t\tSee GPAGE extended STS\n#:GSTS \tis op16=0x186F\t\tSee GPAGE extended STS\n\n#:GSTX \tis op16=0x185E\t\tSee GPAGE extended STX\n#:GSTX \tis op16=0x187E\t\tSee GPAGE extended STX\n#:GSTX \tis op16=0x186E\t\tSee GPAGE extended STX\n\n#:GSTY \tis op16=0x185D\t\tSee GPAGE extended STY\n#:GSTY \tis op16=0x187D\t\tSee GPAGE extended STY\n#:GSTY \tis op16=0x186D\t\tSee GPAGE extended STY\n\n\n:IBEQ byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x4 & size10_10=0 & byte9_8 & rel9\n{\n\tbyte9_8 = byte9_8 + 1;\n\tif (byte9_8 == 0) goto rel9;\n}\n\n:IBEQ word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x4 & size10_10=1 & word9_8 & rel9\n{\n\tword9_8 = word9_8 + 1;\n\tif (word9_8 == 0) goto rel9;\n}\n\n:IBNE byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x5 & size10_10=0 & byte9_8 & rel9\n{\n\tbyte9_8 = byte9_8 + 1;\n\tif (byte9_8 != 0) goto rel9;\n}\n\n:IBNE word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x5 & size10_10=1 & word9_8 & rel9\n{\n\tword9_8 = word9_8 + 1;\n\tif (word9_8 != 0) goto rel9;\n}\n\n:IDIV is Prefix18=1 & op8=0x10 \n{\n\t$(C) = (IX == 0);\n\tresultQ:2 = D / IX;\n\tresultR:2 = D % IX;\n\tIX = resultQ;\n\tD = resultR;\n\t$(Z) = (IX == 0);\n\t$(V) = 0;\n}\n\n:IDIVS is Prefix18=1 & op8=0x15 \n{\n\t$(C) = (IX == 0);\n\tresultQ:4 = sext(D) s/ sext(IX);\n\tresultR:4 = sext(D) s% sext(IX);\n\tIX = resultQ:2;\n\tD = resultR:2;\n\t$(N) = (IX s< 0);\n\t$(Z) = (IX == 0);\n\t$(V) = (resultQ s> 0x00007FFF) | (resultQ s< 0x00008000);\n}\n\n:INC opr16a_8 is Prefix18=0 & (op8=0x72); opr16a_8\n{\n\ttmp:1 = opr16a_8;\n\tresult:1 = tmp + 1;\n\topr16a_8 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_INC_flag(tmp);\n}\n\n:INC indexed1_5 is Prefix18=0 & (op8=0x62); indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:1 = tmp + 1;\n\tindexed1_5 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_INC_flag(tmp);\n}\n\n:INCA is Prefix18=0 & op8=0x42 \n{\n\ttmp:1 = A;\n\tA = tmp + 1;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_INC_flag(tmp);\n}\n\n:INCB is Prefix18=0 & op8=0x52 \n{\n\ttmp:1 = B;\n\tB = tmp + 1;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_INC_flag(tmp);\n}\n\n@if defined(HCS12X)\n:INCW opr16a_16 is Prefix18=1 & (op8=0x72); opr16a_16\n{\n\ttmp:2 = opr16a_16;\n\tresult:2 = tmp + 1;\n\topr16a_16 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_INC_flag2(tmp);\n}\n@endif\n\n@if defined(HCS12X)\n:INCW indexed2_5 is Prefix18=1 & (op8=0x62); indexed2_5 \n{\n\ttmp:2 = indexed2_5;\n\tresult:2 = tmp + 1;\n\tindexed2_5 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_INC_flag2(tmp);\n}\n@endif\n\n@if defined(HCS12X)\n:INCX is Prefix18=1 & op8=0x42 \n{\n\tlocal tmp = IX;\n\tIX = tmp + 1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_INC_flag2(tmp);\n}\n@endif\n\n@if defined(HCS12X)\n:INCY is Prefix18=1 & op8=0x52 \n{\n\tlocal tmp = IY;\n\tIY = tmp + 1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_INC_flag2(tmp);\n}\n@endif\n\n:INS is Prefix18=0 & op16=0x1B81 \n{\n\tSP = SP + 1;\n}\n\n:INX is Prefix18=0 & op8=0x08 \n{\n\tIX = IX + 1;\n\t$(Z) = (IX == 0);\n}\n\n:INY is Prefix18=0 & op8=0x02 \n{\n\tIY = IY + 1;\n\t$(Z) = (IY == 0);\n}\n\n:JMP opr16a is Prefix18=0 & (op8=0x06); opr16a\n{\t\n\tgoto [opr16a];\n}\n\n:JMP indexedA_5 is Prefix18=0 & (op8=0x05); indexedA_5\n{\n\tgoto [indexedA_5];\n}\n\n:JSR opr8a is Prefix18=0 & (op8=0x17); opr8a\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t\n\tcall [opr8a];\n}\n\n:JSR opr16a is Prefix18=0 & (op8=0x16); opr16a\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\n\tcall [opr16a];\n}\n\n:JSR indexedA_5 is Prefix18=0 & (op8=0x15); indexedA_5\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\t \n\tcall [indexedA_5];\n}\n\n:LBCC rel16 is Prefix18=1 & op8=0x24; rel16\n{\n\tif ($(C) == 0) goto rel16;\n}\n\n:LBCS rel16 is Prefix18=1 & op8=0x25; rel16\n{\n\tif ($(C) == 1) goto rel16;\n}\n\n:LBEQ rel16 is Prefix18=1 & op8=0x27; rel16\n{\n\tif ($(Z) == 1) goto rel16;\n}\n\n:LBGE rel16 is Prefix18=1 & op8=0x2C; rel16\n{\n\tif (($(N) ^ $(V)) == 1) goto rel16;\n}\n\n:LBGT rel16 is Prefix18=1 & op8=0x2E; rel16\n{\n\tif (($(Z) | ($(N) ^ $(V))) == 0) goto rel16;\n}\n\n:LBHI rel16 is Prefix18=1 & op8=0x22; rel16\n{\n\tif (($(C) | $(Z)) == 0) goto rel16;\n}\n\n#:LBHS rel16\tis Prefix18=1 & op8=0x24; rel16\t\tSee LBCC\n\n:LBLE rel16 is Prefix18=1 & op8=0x2F; rel16\n{\n\tif ($(Z) | ($(N) ^ $(V))) goto rel16;\n}\n\n#:LBLO rel16\tis Prefix18=1 & op8=0x25; rel16\t\tsee LBCS\n\n:LBLS rel16 is Prefix18=1 & op8=0x23; rel16\n{\n\tif (($(C) | $(Z)) == 1) goto rel16;\n}\n\n:LBLT rel16 is Prefix18=1 & op8=0x2D; rel16\n{\n\tif (($(N) ^ $(V)) == 1) goto rel16;\n}\n\n:LBMI rel16 is Prefix18=1 & op8=0x2B; rel16\n{\n\tif ($(N) == 1) goto rel16;\n}\n\n:LBNE rel16 is Prefix18=1 & op8=0x26; rel16\n{\n\tif ($(Z) == 0) goto rel16;\n}\n\n:LBPL rel16 is Prefix18=1 & op8=0x2A; rel16\n{\n\tif ($(N) == 0) goto rel16;\n}\n\n:LBRA rel16 is Prefix18=1 & op8=0x20; rel16\n{\n\tgoto rel16;\n}\n\n# branch never is a four-byte nop\n:LBRN rel16 is Prefix18=1 & op8=0x21; rel16\n{\n}\n\n:LBVC rel16 is Prefix18=1 & op8=0x28; rel16\n{\n\tif ($(V) == 0) goto rel16;\n}\n\n:LBVS rel16 is Prefix18=1 & op8=0x29; rel16\n{\n\tif ($(V) == 1) goto rel16;\n}\n\n:LDAA iopr8i is Prefix18=0 & (op8=0x86); iopr8i\n{ \n\tA = iopr8i;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\nGPaged: \"G\" is Prefix18=1 [ UseGPAGE=1; ] {}\nGPaged: is Prefix18=0 [ UseGPAGE=0; ] {}\n\n:^GPaged^\"LDAA\" opr8a_8 is GPaged & (op8=0x96); opr8a_8 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tA = opr8a_8;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDAA\" opr16a_8 is GPaged & (op8=0xB6); opr16a_8 [ UseGPAGE=Prefix18; ]\n{\n build GPaged;\n\tA = opr16a_8;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDAA\" indexed1_5 is GPaged & (op8=0xA6); indexed1_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tA = indexed1_5;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:LDAB iopr8i is Prefix18=0 & (op8=0xC6); iopr8i\n{ \n\tB = iopr8i;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDAB\" opr8a_8 is GPaged & (op8=0xD6); opr8a_8 [ UseGPAGE=Prefix18; ]\n{ \n build GPaged;\n\tB = opr8a_8;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDAB\" opr16a_8 is GPaged & (op8=0xF6); opr16a_8 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tB = opr16a_8;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDAB\" indexed1_5 is GPaged & (op8=0xE6); indexed1_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tB = indexed1_5;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:LDD iopr16i is Prefix18=0 & (op8=0xCC); iopr16i\n{ \n\tD = iopr16i;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDD\" opr8a_16 is GPaged & (op8=0xDC); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tD = opr8a_16;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDD\" opr16a_16 is GPaged & (op8=0xFC); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tD = opr16a_16;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDD\" indexed2_5 is GPaged & (op8=0xEC); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tD = indexed2_5;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n\ndefine pcodeop LoadStack;\n\n:LDS iopr16i is Prefix18=0 & (op8=0xCF); iopr16i\n{\n\tSP = LoadStack(iopr16i);\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDS\" opr8a_16 is GPaged & (op8=0xDF); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tSP = LoadStack(opr8a_16);\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDS\" opr16a_16 is GPaged & (op8=0xFF); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tSP = LoadStack(opr16a_16);\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDS\" indexed2_5 is GPaged & (op8=0xEF); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tSP = LoadStack(indexed2_5);\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:LDX iopr16i is Prefix18=0 & (op8=0xCE); iopr16i\n{ \n\tIX = iopr16i;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDX\" opr8a_16 is GPaged & (op8=0xDE); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tIX = opr8a_16;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDX\" opr16a_16 is GPaged & (op8=0xFE); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tIX = opr16a_16;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDX\" indexed2_5 is GPaged & (op8=0xEE); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tIX = indexed2_5;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:LDY iopr16i is Prefix18=0 & (op8=0xCD); iopr16i\n{ \n\tIY = iopr16i;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDY\" opr8a_16 is GPaged & (op8=0xDD); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tIY = opr8a_16;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDY\" opr16a_16 is GPaged & (op8=0xFD); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tIY = opr16a_16;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"LDY\" indexed2_5 is GPaged & (op8=0xED); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tIY = indexed2_5;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:LEAS indexed0_3 is Prefix18=0 & (op8=0x1B); indexed0_3\n{ \n\tSP = indexed0_3;\n}\n\n:LEAX indexed0_3 is Prefix18=0 & (op8=0x1A); indexed0_3\n{ \n\tIX = indexed0_3;\n}\n\n:LEAY indexed0_3 is Prefix18=0 & (op8=0x19); indexed0_3\n{ \n\tIY = indexed0_3;\n}\n\n## Logical Shift left is same as arithmetic shift left\n#:LSL \t\tis (op8=0x68 | op8=0x78)\n#:LSLA\t\tis op8=0x48 \n#:LSLB\t\tis op8=0x58 \n#:LSLD\t\tis op8=0x59 \n\n#:LSLW\t\tis op16=0x1878 | op16=0x1868\tsee ASLW\n#:LSLX\t\tis op16=0x1848\t\t\t\t\tsee ASLX\n#:LSLY\t\tis op16=0x1858\t\t\t\t\tsee ASLY\n\n:LSR opr16a_8 is Prefix18=0 & (op8=0x74); opr16a_8\n{\n\ttmp:1 = opr16a_8;\n\t$(C) = tmp & 1;\n\ttmp = tmp >> 1;\n\topr16a_8 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n\n:LSR indexed1_5 is Prefix18=0 & (op8=0x64); indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\t$(C) = tmp & 1;\n\ttmp = tmp >> 1;\n\tindexed1_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n\n:LSRA is Prefix18=0 & op8=0x44 \n{\n\t$(C) = A[0,1];\n\tA = (A >> 1);\n\t$(Z) = (A == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n\n:LSRB is Prefix18=0 & op8=0x54 \n{\n\t$(C) = B[0,1];\n\tB = (B >> 1);\n\t$(Z) = (B == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n\n:LSRD is Prefix18=0 & op8=0x49 \n{\n\t$(C) = D[0,1];\n\tD = (D >> 1);\n\t$(Z) = (D == 0);\n\t$(N) = 0;\n\tV_equals_C();\t\n}\n\n@if defined(HCS12X)\n:LSRW opr16a_16 is Prefix18=1 & (op8=0x74); opr16a_16\n{\n\tlocal tmp = opr16a_16;\n\t$(C) = tmp[0,1];\n\ttmp = tmp >> 1;\n\topr16a_16 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:LSRW indexed2_5 is Prefix18=1 & (op8=0x64); indexed2_5 \n{\n\tlocal tmp = indexed2_5;\n\t$(C) = tmp[0,1];\n\ttmp = tmp >> 1;\n\tindexed2_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:LSRX is Prefix18=1 & op8=0x44 \n{\n\t$(C) = IX[0,1];\n\tIX = IX >> 1;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:LSRY is Prefix18=1 & op8=0x54 \n{\n\t$(C) = IY[0,1];\n\tIY = IY >> 1;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n:MAXA indexed1_5 is Prefix18=1 & op8=0x18; indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:2 = zext(A) - zext(tmp);\n\tif (A > tmp) goto ;\n\t\tA = tmp;\n\t\n\t\n\t$(N) = (result:1 s< 0);\n\t$(Z) = (result:1 == 0);\n\t$(V) = (result s> 0x007F) | (result s< 0x0080);\n\t$(C) = (result > 0x00FF);\n}\n\n:MAXM indexed1_5 is Prefix18=1 & op8=0x1C; indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:4 = zext(A) - zext(tmp);\n\tif (tmp > A) goto ;\n\t\tindexed1_5 = A;\n\t\n\t\n\t$(N) = (result:2 s< 0);\n\t$(Z) = (result:2 == 0);\n\t$(V) = (result s> 0x007F) | (result s< 0x0080);\n\t$(C) = (result > 0x00FF);\n}\n\n:MEM is Prefix18=0 & op8=0x01\n{\n\tlocal val:1 = GradeOfMembership(A, IX, IY);\n\tStore(IY, val);\n\tIY = IY + 1;\n\tIX = IX + 4;\n}\n\n:MINA indexed1_5 is Prefix18=1 & op8=0x19; indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:2 = zext(A) - zext(tmp);\n\tif (A < tmp) goto ;\n\t\tA = tmp;\n\t\n\t\n\t$(N) = (result:1 s< 0);\n\t$(Z) = (result:1 == 0);\n\t$(V) = (result s> 0x007F) | (result s< 0x0080);\n\t$(C) = (result > 0x00FF);\n}\n\n:MINM indexed1_5 is Prefix18=1 & op8=0x1D; indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:4 = zext(A) - zext(tmp);\n\tif (tmp < A) goto ;\n\t\tindexed1_5 = A;\n\t\n\t\n\t$(N) = (result:2 s< 0);\n\t$(Z) = (result:2 == 0);\n\t$(V) = (result s> 0x007F) | (result s< 0x0080);\n\t$(C) = (result > 0x00FF);\n}\n\n:MOVB iopr8i, opr16a_8\t\t\t\tis Prefix18=1 & op8=0x0B; iopr8i; opr16a_8 \n{\n\topr16a_8 = iopr8i;\n}\n\n@if defined(HCS12X)\n:MOVB iopr8i, indexed1_5\t\t\tis Prefix18=1 & op8=0x08; indexed1_5; iopr8i\n{\n\tindexed1_5 = iopr8i;\n}\n@else\n:MOVB iopr8i, indexed1_1\t\t\tis Prefix18=1 & op8=0x08; indexed1_1; iopr8i\n{\n\tindexed1_1 = iopr8i;\n}\n@endif\n\n:MOVB opr16a_8, op2_opr16a_8\t\tis Prefix18=1 & op8=0x0C; opr16a_8; op2_opr16a_8 \n{\n\tbuild opr16a_8;\n\tlocal tmp = opr16a_8;\n\tbuild op2_opr16a_8;\n\top2_opr16a_8 = tmp;\n}\n\n@if defined(HCS12X)\n:MOVB opr16a_8, indexed1_5\t\t\tis Prefix18=1 & op8=0x09; indexed1_5; opr16a_8 \n{\n\tindexed1_5 = opr16a_8;\n}\n@else\n:MOVB opr16a_8, indexed1_1\t\t\tis Prefix18=1 & op8=0x09; indexed1_1; opr16a_8 \n{\n\tindexed1_1 = opr16a_8;\n}\n@endif\n\n@if defined(HCS12X)\n:MOVB indexed1_5, opr16a_8\t\t\tis Prefix18=1 & op8=0x0D; indexed1_5; opr16a_8 \n{\n\topr16a_8 = indexed1_5;\n}\n@else\n:MOVB indexed1_1, opr16a_8\t\t\tis Prefix18=1 & op8=0x0D; indexed1_1; opr16a_8 \n{\n\topr16a_8 = indexed1_1;\n}\n@endif\n\n@if defined(HCS12X)\n:MOVB indexed1_5, op2_indexed1_5\tis Prefix18=1 & op8=0x0A; indexed1_5; op2_indexed1_5 \n{\n\t# two operands share a lower level subconstructor\n\t# MUST do the builds and store the value, or the first operands results will be overwritten\n\tbuild indexed1_5;\n\tlocal tmp = indexed1_5;\n\tbuild op2_indexed1_5;\n\top2_indexed1_5 = tmp;\n}\n@else\n:MOVB indexed1_1, op2_indexed1_1\tis Prefix18=1 & op8=0x0A; indexed1_1; op2_indexed1_1 \n{\n\t# two operands share a lower level subconstructor\n\t# MUST do the builds and store the value, or the first operands results will be overwritten\n\tbuild indexed1_1;\n\tlocal tmp = indexed1_1;\n\tbuild op2_indexed1_1;\n\top2_indexed1_1 = tmp;\n}\n@endif\n\n:MOVW iopr16i, opr16a_16\t\t\t\tis Prefix18=1 & op8=0x03; iopr16i; opr16a_16 \n{\n\topr16a_16 = iopr16i;\n}\n\n@if defined(HCS12X)\n:MOVW iopr16i, indexed2_5\t\t\tis Prefix18=1 & op8=0x00; indexed2_5; iopr16i\n{\n\tindexed2_5 = iopr16i;\n}\n@else\n:MOVW iopr16i, indexed2_1\t\t\tis Prefix18=1 & op8=0x00; indexed2_1; iopr16i\n{\n\tindexed2_1 = iopr16i;\n}\n@endif\n\n:MOVW opr16a_16, op2_opr16a_16\t\tis Prefix18=1 & op8=0x04; opr16a_16; op2_opr16a_16 \n{\n\t# two operands share a lower level subconstructor\n\t# MUST do the builds and store the value, or the first operands results will be overwritten\n\tbuild opr16a_16;\n\tlocal tmp = opr16a_16;\n\tbuild op2_opr16a_16;\n\top2_opr16a_16 = tmp;\n}\n\n@if defined(HCS12X)\n:MOVW opr16a_16, indexed2_5\t\t\tis Prefix18=1 & op8=0x01; indexed2_5; opr16a_16 \n{\n\tindexed2_5 = opr16a_16;\n}\n@else\n:MOVW opr16a_16, indexed2_1\t\t\tis Prefix18=1 & op8=0x01; indexed2_1; opr16a_16 \n{\n\tindexed2_1 = opr16a_16;\n}\n@endif\n\n@if defined(HCS12X)\n:MOVW indexed2_5, opr16a_16\t\t\tis Prefix18=1 & op8=0x05; indexed2_5; opr16a_16 \n{\n\topr16a_16 = indexed2_5;\n}\n@else\n:MOVW indexed2_1, opr16a_16\t\t\tis Prefix18=1 & op8=0x05; indexed2_1; opr16a_16 \n{\n\topr16a_16 = indexed2_1;\n}\n@endif\n\n@if defined(HCS12X)\n:MOVW indexed2_5, op2_indexed2_5\tis Prefix18=1 & op8=0x02; indexed2_5; op2_indexed2_5 \n{\n\t# two operands share a lower level subconstructor\n\t# MUST do the builds and store the value, or the first operands results will be overwritten\n\tbuild indexed2_5;\n\tlocal tmp = indexed2_5;\n\tbuild op2_indexed2_5;\n\top2_indexed2_5 = tmp;\n}\n@else\n:MOVW indexed2_1, op2_indexed2_1\tis Prefix18=1 & op8=0x02; indexed2_1; op2_indexed2_1 \n{\n\t# two operands share a lower level subconstructor\n\t# MUST do the builds and store the value, or the first operands results will be overwritten\n\tbuild indexed2_1;\n\tlocal tmp = indexed2_1;\n\tbuild op2_indexed2_1;\n\top2_indexed2_1 = tmp;\n}\n@endif\n\n\n:MUL is Prefix18=0 & op8=0x12\n{\n\tD = zext(A) * zext(B);\n\t$(C) = B[7,1];\n}\n\n:NEG opr16a_8 is Prefix18=0 & (op8=0x70); opr16a_8\n{\n\ttmp:1 = opr16a_8;\n\tresult:1 = -tmp;\n\topr16a_8 = result;\n\t$(C) = (result != 0);\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_NEG_flag(tmp); \n}\n\n:NEG indexed1_5 is Prefix18=0 & (op8=0x60); indexed1_5 \n{\n\ttmp:1 = indexed1_5;\n\tresult:1 = -tmp;\n\tindexed1_5 = result;\n\t$(C) = (result != 0);\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_NEG_flag(tmp); \n}\n\n:NEGA is Prefix18=0 & op8=0x40 \n{\n\ttmp:1 = A;\n\tA = -tmp;\n\t$(C) = (A != 0);\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_NEG_flag(tmp); \n}\n\n:NEGB is Prefix18=0 & op8=0x50 \n{\n\ttmp:1 = B;\n\tB = -tmp;\n\t$(C) = (B != 0);\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_NEG_flag(tmp); \n}\n\n@if defined(HCS12X)\n:NEGW opr16a_16 is Prefix18=1 & (op8=0x70); opr16a_16\n{\n\ttmp:2 = opr16a_16;\n\tresult:2 = -tmp;\n\topr16a_16 = result;\n\t$(C) = (result != 0);\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_NEG_flag2(tmp); \n}\n@endif\n\n@if defined(HCS12X)\n:NEGW indexed2_5 is Prefix18=1 & (op8=0x60); indexed2_5 \n{\n\ttmp:2 = indexed2_5;\n\tresult:2 = -tmp;\n\tindexed2_5 = result;\n\t$(C) = (result != 0);\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\n\tV_NEG_flag2(tmp); \n}\n@endif\n\n@if defined(HCS12X)\n:NEGX is Prefix18=1 & op8=0x40 \n{\n\ttmp:2 = IX;\n\tIX = -tmp;\n\t$(C) = (IX != 0);\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_NEG_flag2(tmp); \n}\n@endif\n\n@if defined(HCS12X)\n:NEGY is Prefix18=1 & op8=0x50 \n{\n\ttmp:2 = IY;\n\tIY = -tmp;\n\t$(C) = (IY != 0);\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_NEG_flag2(tmp); \n}\n@endif\n\n:NOP is Prefix18=0 & op8=0xA7\n{\n}\n\n:ORAA iopr8i is Prefix18=0 & (op8=0x8A); iopr8i\n{ \n\tA = A | iopr8i; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:ORAA opr8a_8 is Prefix18=0 & (op8=0x9A); opr8a_8\n{ \n\tA = A | opr8a_8; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:ORAA opr16a_8 is Prefix18=0 & (op8=0xBA); opr16a_8\n{ \n\tA = A | opr16a_8; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:ORAA indexed1_5 is Prefix18=0 & (op8=0xAA); indexed1_5\n{ \n\tA = A | indexed1_5; \n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:ORAB iopr8i is Prefix18=0 & (op8=0xCA); iopr8i\n{ \n\tB = B | iopr8i; \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:ORAB opr8a_8 is Prefix18=0 & (op8=0xDA); opr8a_8\n{ \n\tB = B | opr8a_8; \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:ORAB opr16a_8 is Prefix18=0 & (op8=0xFA); opr16a_8\n{ \n\tB = B | opr16a_8; \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:ORAB indexed1_5 is Prefix18=0 & (op8=0xEA); indexed1_5\n{ \n\tB = B | indexed1_5; \n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:ORCC iopr8i is Prefix18=0 & (op8=0x14); iopr8i\n{ \n\tCCR = CCR | (iopr8i & 0b10111111); \n}\n\n@if defined(HCS12X)\n:ORX iopr16i is Prefix18=1 & (op8=0x8A); iopr16i\n{ \n\tIX = IX | iopr16i;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORX opr8a_16 is Prefix18=1 & (op8=0x9A); opr8a_16\n{ \n\tIX = IX | opr8a_16;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORX opr16a_16 is Prefix18=1 & (op8=0xBA); opr16a_16\n{ \n\tIX = IX | opr16a_16;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORX indexed2_5 is Prefix18=1 & (op8=0xAA); indexed2_5\n{ \n\tIX = IX | indexed2_5;\n\tV_equals_0(); \n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORY iopr16i is Prefix18=1 & (op8=0xCA); iopr16i\n{ \n\tIY = IY | iopr16i;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORY opr8a_16 is Prefix18=1 & (op8=0xDA); opr8a_16\n{ \n\tIY = IY | opr8a_16;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORY opr16a_16 is Prefix18=1 & (op8=0xFA); opr16a_16\n{ \n\tIY = IY | opr16a_16;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n@if defined(HCS12X)\n:ORY indexed2_5 is Prefix18=1 & (op8=0xEA); indexed2_5\n{ \n\tIY = IY | indexed2_5;\n\tV_equals_0(); \n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n}\n@endif\n\n:PSHA is Prefix18=0 & op8=0x36\n{\n\tPush1( A );\n}\n\n:PSHB is Prefix18=0 & op8=0x37\n{\n\tPush1( B );\n}\n\n:PSHC is Prefix18=0 & op8=0x39\n{\n\tPush1( CCR );\n}\n\n@if defined(HCS12X)\n:PSHCW is Prefix18=1 & op8=0x39\n{\n\tPush2( CCRW );\n}\n@endif\n\n:PSHD is Prefix18=0 & op8=0x3B\n{\n\tPush2( D );\n}\n\n:PSHX is Prefix18=0 & op8=0x34\n{\n\tPush2( IX );\n}\n\n:PSHY is Prefix18=0 & op8=0x35\n{\n\tPush2( IY );\n}\n\n:PULA is Prefix18=0 & op8=0x32\n{\n\tPull1( A );\n}\n\n:PULB is Prefix18=0 & op8=0x33\n{\n\tPull1( B );\n}\n\n:PULC is Prefix18=0 & op8=0x38\n{\n\tPull1( CCR );\n}\n\n@if defined(HCS12X)\n:PULCW is Prefix18=1 & op8=0x38\n{\n\tPull2( CCRW );\n}\n@endif\n\n:PULD is Prefix18=0 & op8=0x3A\n{\n\tPull2( D );\n}\n\n:PULX is Prefix18=0 & op8=0x30\n{\n\tPull2( IX );\n}\n\n:PULY is Prefix18=0 & op8=0x31\n{\n\tPull2( IY );\n}\n\n:REV is Prefix18=1 & op8=0x3A\n{\n\ttempIX:2 = MinMaxRuleEvaluation(IX, IY, A, $(V));\n\t$(V) = MinMaxRuleEvaluationCorrect(IX, IY, A, $(V));\n\n\tIX = tempIX;\n}\n\n:REVW is Prefix18=1 & op8=0x3B\n{\n\ttempIX:2 = MinMaxRuleEvaluationWeighted(IX, IY, A, $(V), $(C));\n\ttempIY:2 = MinMaxRuleEvaluationWeighted(IX, IY, A, $(V), $(C));\n\t$(V) = MinMaxRuleEvaluationWeightedCorrect(IX, IY, A, $(V), $(C));\n\t\n\tIX = tempIX;\n\tIY = tempIY;\n}\n\n:ROL opr16a_8 is Prefix18=0 & (op8=0x75); opr16a_8\n{\n\ttmpC:1 = $(C);\n\top1:1 = opr16a_8;\n\t$(C) = op1 >> 7;\n\tresult:1 = op1 << 1;\n\tresult = result | tmpC;\n\topr16a_8 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ROL indexed1_5 is Prefix18=0 & (op8=0x65); indexed1_5 \n{\n\ttmpC:1 = $(C);\n\top1:1 = indexed1_5;\n\t$(C) = op1 >> 7;\n\tresult:1 = op1 << 1;\n\tresult = result | tmpC;\n\tindexed1_5 = result;\n\t$(Z) = (result == 0);\n\t$(N) = (result s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ROLA is Prefix18=0 & op8=0x45 \n{\n\ttmpC:1 = $(C) ;\n\t$(C) = A >> 7;\n\tA = A << 1;\n\tA = A | tmpC;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_N_xor_C();\t\n}\n\n:ROLB is Prefix18=0 & op8=0x55 \n{\n\ttmpC:1 = $(C) ;\n\t$(C) = B >> 7;\n\tB = B << 1;\n\tB = B | tmpC;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_N_xor_C();\t\n}\n\n@if defined(HCS12X)\n:ROLW opr16a_16 is Prefix18=1 & (op8=0x75); opr16a_16\n{\n\tlocal tmp = opr16a_16;\n\tlocal tmpC = $(C);\n\t$(C) = tmp[15,1];\n\ttmp = tmp << 1;\n\ttmp = tmp | zext(tmpC);\n\topr16a_16 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ROLW indexed2_5 is Prefix18=1 & (op8=0x65); indexed2_5 \n{\n\tlocal tmp = indexed2_5;\n\tlocal tmpC = $(C);\n\t$(C) = tmp[15,1];\n\ttmp = tmp << 1;\n\ttmp = tmp | zext(tmpC);\n\tindexed2_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ROLX is Prefix18=1 & op8=0x45\n{\n\tlocal tmpC = $(C);\n\t$(C) = IX[15,1];\n\tIX = IX << 1;\n\tIX = IX | zext(tmpC);\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:ROLY is Prefix18=1 & op8=0x55\n{\n\tlocal tmpC = $(C);\n\t$(C) = IY[15,1];\n\tIY = IY << 1;\n\tIY = IY | zext(tmpC);\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n:ROR opr16a_8 is Prefix18=0 & (op8=0x76); opr16a_8\n{\n\ttmpC:1 = $(C) << 7;\n\ttmp:1 = opr16a_8;\n\t$(C) = tmp & 1;\n\ttmp = tmp >> 1;\n\ttmp = tmp | tmpC;\n\topr16a_8 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:ROR indexed1_5 is Prefix18=0 & (op8=0x66); indexed1_5 \n{\n\ttmpC:1 = $(C) << 7;\n\ttmp:1 = indexed1_5;\n\t$(C) = tmp & 1;\n\ttmp = tmp >> 1;\n\ttmp = tmp | tmpC;\n\tindexed1_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:RORA is Prefix18=0 & op8=0x46 \n{\n\ttmpC:1 = $(C) << 7;\n\t$(C) = A & 1;\n\tA = A >> 1;\n\tA = A | tmpC;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n:RORB is Prefix18=0 & op8=0x56 \n{\n\ttmpC:1 = $(C) << 7;\n\t$(C) = B & 1;\n\tB = B >> 1;\n\tB = B | tmpC;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n\n@if defined(HCS12X)\n:RORW opr16a_16 is Prefix18=1 & (op8=0x76); opr16a_16\n{\n\tlocal tmp = opr16a_16;\n\tlocal tmpC = $(C);\n\t$(C) = tmp[0,1];\n\ttmp = tmp >> 1;\n\ttmp = tmp | (zext(tmpC) << 15);\n\topr16a_16 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:RORW indexed2_5 is Prefix18=1 & (op8=0x66); indexed2_5 \n{\n\tlocal tmp = indexed2_5;\n\tlocal tmpC = $(C);\n\t$(C) = tmp[0,1];\n\ttmp = tmp >> 1;\n\ttmp = tmp | (zext(tmpC) << 15);\n\tindexed2_5 = tmp;\n\t$(Z) = (tmp == 0);\n\t$(N) = (tmp s< 0);\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:RORX is Prefix18=1 & op8=0x46\n{\n\tlocal tmpC = $(C);\n\t$(C) = IX[0,1];\n\tIX = IX >> 1;\n\tIX = IX | (zext(tmpC) << 15);\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@if defined(HCS12X)\n:RORY is Prefix18=1 & op8=0x56\n{\n\tlocal tmpC = $(C);\n\t$(C) = IY[0,1];\n\tIY = IY >> 1;\n\tIY = IY | (zext(tmpC) << 15);\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\t\n\tV_equals_N_xor_C();\t\n}\n@endif\n\n@ifdef HCS12\n:RTC is Prefix18=0 & op8=0x0A\n{\n\tPull1( PPAGE );\n\n\ttmp:2 = 0;\n\tPull2( tmp );\n\t\n\treturn [tmp];\n}\n@endif\n\n:RTI is Prefix18=0 & op8=0x0B\n{\n\ttmp:2 = 0;\n\tPull1( CCR );\n\tPull1( B );\n\tPull1( A );\n\tPull2( IX );\n\tPull2( IY );\n\tPull2( tmp ); # as ordered on page 289, not as documented in RTI description\n\t\n\treturn [tmp];\n}\n\n:RTS is Prefix18=0 & op8=0x3D\n{\n\ttmp:2 = 0;\n\tPull2( tmp );\n\t\n\treturn [tmp];\n}\n\n:SBA\t is Prefix18=1 & (op8=0x16)\n{ \n\tresult:1 = A - B;\n\tsubtraction_flags1(A, B, result);\n\tA = result;\n}\n\n:SBCA iopr8i is Prefix18=0 & (op8=0x82); iopr8i\n{ \n\top1:1 = iopr8i;\n\t\n\tresult:1 = A - op1 - $(C);\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SBCA opr8a_8 is Prefix18=0 & (op8=0x92); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\t\n\tresult:1 = A - op1 - $(C);\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SBCA opr16a_8 is Prefix18=0 & (op8=0xB2); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\t\n\tresult:1 = A - op1 - $(C);\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SBCA indexed1_5 is Prefix18=0 & (op8=0xA2); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\t\n\tresult:1 = A - op1 - $(C);\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SBCB iopr8i is Prefix18=0 & (op8=0xC2); iopr8i\n{ \n\top1:1 = iopr8i;\n\t\n\tresult:1 = B - op1 - $(C);\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SBCB opr8a_8 is Prefix18=0 & (op8=0xD2); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\t\n\tresult:1 = B - op1 - $(C);\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SBCB opr16a_8 is Prefix18=0 & (op8=0xF2); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\t\n\tresult:1 = B - op1 - $(C);\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SBCB indexed1_5 is Prefix18=0 & (op8=0xE2); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\t\n\tresult:1 = B - op1 - $(C);\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n@if defined(HCS12X)\n:SBED iopr16i is Prefix18=1 & (op8=0x83); iopr16i\n{\n\top1:2 = iopr16i;\n\t\n\tresult:2 = D - op1 - zext($(C));\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBED opr8a_16 is Prefix18=1 & (op8=0x93); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\t\n\tresult:2 = D - op1 - zext($(C));\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBED opr16a_16 is Prefix18=1 & (op8=0xB3); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\t\n\tresult:2 = D - op1 - zext($(C));\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBED indexed2_5 is Prefix18=1 & (op8=0xA3); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\t\n\tresult:2 = D - op1 - zext($(C));\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEX iopr16i is Prefix18=1 & (op8=0x82); iopr16i\n{ \n\top1:2 = iopr16i;\n\t\n\tresult:2 = IX - op1 - zext($(C));\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEX opr8a_16 is Prefix18=1 & (op8=0x92); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\t\n\tresult:2 = IX - op1 - zext($(C));\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEX opr16a_16 is Prefix18=1 & (op8=0xB2); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\t\n\tresult:2 = IX - op1 - zext($(C));\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEX indexed2_5 is Prefix18=1 & (op8=0xA2); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\t\n\tresult:2 = IX - op1 - zext($(C));\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEY iopr16i is Prefix18=1 & (op8=0xC2); iopr16i\n{ \n\top1:2 = iopr16i;\n\t\n\tresult:2 = IY - op1 - zext($(C));\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEY opr8a_16 is Prefix18=1 & (op8=0xD2); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\t\n\tresult:2 = IY - op1 - zext($(C));\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEY opr16a_16 is Prefix18=1 & (op8=0xF2); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\t\n\tresult:2 = IY - op1 - zext($(C));\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SBEY indexed2_5 is Prefix18=1 & (op8=0xE2); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\t\n\tresult:2 = IY - op1 - zext($(C));\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n:SEC is Prefix18=0 & op16=0x1401 \n{\n\t$(C) = 1;\n}\n\n:SEI is Prefix18=0 & op16=0x1410 \n{\n\t$(I) = 1;\n}\n\n:SEV is Prefix18=0 & op16=0x1402 \n{\n\t$(V) = 1;\n}\n\n\n\n@if defined(HCS12X)\n:SEX A, D is Prefix18=0 & op8=0xB7;\n\t(\n\t\t( rows3_0=0xC & ( columns7_4=0x0 ) ) \n\t) &\n\tA & D\n{\n\tD = sext( A );\n}\n@endif\n\n@if defined(HCS12X)\n:SEX B, D is Prefix18=0 & op8=0xB7;\n\t(\n\t\t( rows3_0=0xC & ( columns7_4=0x1 ) ) \n\t) &\n\tB & D\n{\n\tD = sext( B );\n}\n@endif\n\n@if defined(HCS12X)\n:SEX D, IX is Prefix18=0 & op8=0xB7;\n\t(\n\t\t( rows3_0=0xD & ( columns7_4=0x4 ) ) \n\t) &\n\tD & IX\n{\n\t# generate the sign extension upper word and assign it to destination\n\tlocal tmp:4 = sext( D );\n\tIX = tmp(2);\n}\n@endif\n\n@if defined(HCS12X)\n:SEX D, IY is Prefix18=0 & op8=0xB7;\n\t(\n\t\t( rows3_0=0xE & ( columns7_4=0x4 ) ) \n\t) &\n\tD & IY\n{\n\t# generate the sign extension upper word and assign it to destination\n\tlocal tmp:4 = sext( D );\n\tIY = tmp(2);\n}\n@endif\n\n:SEX abc5_4, dxys2_0 is Prefix18=0 & op8=0xB7;\n\t(\n\t\t( rows3_0=0x3 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | \n\t\t( rows3_0=0x4 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | \n\t\t( rows3_0=0x5 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | \n\t\t( rows3_0=0x6 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | \n\t\t( rows3_0=0x7 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) \n\t) &\n\tabc5_4 & dxys2_0\n{\n\tdxys2_0 = sext(abc5_4);\n}\n\n:^GPaged^\"STAA\" opr8a_8 is GPaged & (op8=0x5A); opr8a_8 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr8a_8 = A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STAA\" opr16a_8 is GPaged & (op8=0x7A); opr16a_8 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr16a_8 = A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STAA\" indexed1_5 is GPaged & (op8=0x6A); indexed1_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tindexed1_5 = A;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STAB\" opr8a_8 is GPaged & (op8=0x5B); opr8a_8 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr8a_8 = B;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STAB\" opr16a_8 is GPaged & (op8=0x7B); opr16a_8 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr16a_8 = B;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STAB\" indexed1_5 is GPaged & (op8=0x6B); indexed1_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tindexed1_5 = B;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STD\" opr8a_16 is GPaged & (op8=0x5C); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr8a_16 = D;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STD\" opr16a_16 is GPaged & (op8=0x7C); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr16a_16 = D;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STD\" indexed2_5 is GPaged & (op8=0x6C); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tindexed2_5 = D;\n\t$(Z) = (D == 0);\n\t$(N) = (D s< 0);\n\tV_equals_0();\n}\n\n:STOP is Prefix18=1 & op8=0x3E\n{\n\tif ($(S) == 0) goto ;\n\t\ttmp:2 = inst_next;\n\t\tPush2( tmp );\n\t\tPush2( IY );\n\t\tPush2( IX );\n\t\tPush1( A );\n\t\tPush1( B );\n\t\tPush1( CCR );\n\t\tstop();\n\t\n}\n\n:^GPaged^\"STS\" opr8a_16 is GPaged & (op8=0x5F); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr8a_16 = SP;\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STS\" opr16a_16 is GPaged & (op8=0x7F); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr16a_16 = SP;\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STS\" indexed2_5 is GPaged & (op8=0x6F); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tindexed2_5 = SP;\n\t$(Z) = (SP == 0);\n\t$(N) = (SP s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STX\" opr8a_16 is GPaged & (op8=0x5E); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr8a_16 = IX;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STX\" opr16a_16 is GPaged & (op8=0x7E); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr16a_16 = IX;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STX\" indexed2_5 is GPaged & (op8=0x6E); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tindexed2_5 = IX;\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STY\" opr8a_16 is GPaged & (op8=0x5D); opr8a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr8a_16 = IY;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STY\" opr16a_16 is GPaged & (op8=0x7D); opr16a_16 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\topr16a_16 = IY;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:^GPaged^\"STY\" indexed2_5 is GPaged & (op8=0x6D); indexed2_5 [ UseGPAGE=Prefix18; ]\n{\n\tbuild GPaged;\n\tindexed2_5 = IY;\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\n}\n\n:SUBA iopr8i is Prefix18=0 & (op8=0x80); iopr8i\n{ \n\top1:1 = iopr8i;\n\t\n\tresult:1 = A - op1;\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SUBA opr8a_8 is Prefix18=0 & (op8=0x90); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\t\n\tresult:1 = A - op1;\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SUBA opr16a_8 is Prefix18=0 & (op8=0xB0); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\t\n\tresult:1 = A - op1;\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SUBA indexed1_5 is Prefix18=0 & (op8=0xA0); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\t\n\tresult:1 = A - op1;\n\tsubtraction_flags1(A, op1, result);\n\tA = result;\n}\n\n:SUBB iopr8i is Prefix18=0 & (op8=0xC0); iopr8i\n{ \n\top1:1 = iopr8i;\n\t\n\tresult:1 = B - op1;\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SUBB opr8a_8 is Prefix18=0 & (op8=0xD0); opr8a_8\n{ \n\top1:1 = opr8a_8;\n\t\n\tresult:1 = B - op1;\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SUBB opr16a_8 is Prefix18=0 & (op8=0xF0); opr16a_8\n{ \n\top1:1 = opr16a_8;\n\t\n\tresult:1 = B - op1;\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SUBB indexed1_5 is Prefix18=0 & (op8=0xE0); indexed1_5\n{ \n\top1:1 = indexed1_5;\n\t\n\tresult:1 = B - op1;\n\tsubtraction_flags1(B, op1, result);\n\tB = result;\n}\n\n:SUBD iopr16i is Prefix18=0 & (op8=0x83); iopr16i\n{ \n\top1:2 = iopr16i;\n\t\n\tresult:2 = D - op1;\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n\n:SUBD opr8a_16 is Prefix18=0 & (op8=0x93); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\t\n\tresult:2 = D - op1;\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n\n:SUBD opr16a_16 is Prefix18=0 & (op8=0xB3); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\t\n\tresult:2 = D - op1;\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n\n:SUBD indexed2_5 is Prefix18=0 & (op8=0xA3); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\t\n\tresult:2 = D - op1;\n\tsubtraction_flags2(D, op1, result);\n\tD = result;\n}\n\n@if defined(HCS12X)\n:SUBX iopr16i is Prefix18=1 & (op8=0x80); iopr16i\n{ \n\top1:2 = iopr16i;\n\t\n\tresult:2 = IX - op1;\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBX opr8a_16 is Prefix18=1 & (op8=0x90); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\t\n\tresult:2 = IX - op1;\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBX opr16a_16 is Prefix18=1 & (op8=0xB0); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\t\n\tresult:2 = IX - op1;\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBX indexed2_5 is Prefix18=1 & (op8=0xA0); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\t\n\tresult:2 = IX - op1;\n\tsubtraction_flags2(IX, op1, result);\n\tIX = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBY iopr16i is Prefix18=1 & (op8=0xC0); iopr16i\n{ \n\top1:2 = iopr16i;\n\t\n\tresult:2 = IY - op1;\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBY opr8a_16 is Prefix18=1 & (op8=0xD0); opr8a_16\n{ \n\top1:2 = opr8a_16;\n\t\n\tresult:2 = IY - op1;\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBY opr16a_16 is Prefix18=1 & (op8=0xF0); opr16a_16\n{ \n\top1:2 = opr16a_16;\n\t\n\tresult:2 = IY - op1;\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n@if defined(HCS12X)\n:SUBY indexed2_5 is Prefix18=1 & (op8=0xE0); indexed2_5\n{ \n\top1:2 = indexed2_5;\n\t\n\tresult:2 = IY - op1;\n\tsubtraction_flags2(IY, op1, result);\n\tIY = result;\n}\n@endif\n\n:SWI is Prefix18=0 & op8=0x3F\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\tPush2( IY );\n\tPush2( IX );\n\tPush1( A );\n\tPush1( B );\n\tPush1( CCR );\n\t\n\t$(I) = 1;\n\t\n\taddr:2 = $(VECTOR_SWI);\n\tcall [addr];\n}\n\n:TAB is Prefix18=1 & op8=0x0E \n{\n\tB = A;\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\t\n}\n\n:TAP is Prefix18=0 & op16=0xB702 \n{\n\tsetCCR( A );\n}\n\n:TBA is Prefix18=1 & op8=0x0F \n{\n\tA = B;\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\t\n}\n\n:TBEQ byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x2 & size10_10=0 & byte9_8 & rel9\n{\n\tif (byte9_8 == 0) goto rel9;\n}\n\n:TBEQ word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x2 & size10_10=1 & word9_8 & rel9\n{\n\tif (word9_8 == 0) goto rel9;\n}\n\n:TBL indexed1_3 is Prefix18=1 & op8=0x3D; indexed1_3\n{\n\tA = TableLookupAndInterpolate(indexed1_3, B);\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n@if defined(HC12)\n\t$(C) = TableLookupAndInterpolateRoundable(indexed1_3, B);\n@endif\n}\n\n:TBNE byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x3 & size10_10=0 & byte9_8 & rel9\n{\n\tif (byte9_8 != 0) goto rel9;\n}\n\n:TBNE word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x3 & size10_10=1 & word9_8 & rel9\n{\n\tif (word9_8 != 0) goto rel9;\n}\n\n:TFR bytes_ABClT3lBXlYlSl_6_4, bytes_ABCl_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n# The case \"20\" is covered by TPA\n\t\t( rows3_0=0x0 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0x1 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\n\t\t( rows3_0=0x8 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x4 ) ) | \n\t\t( rows3_0=0x9 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) \n\t) &\n\tbytes_ABClT3lBXlYlSl_6_4 & bytes_ABCl_2_0 \n{\n\tbytes_ABCl_2_0 = bytes_ABClT3lBXlYlSl_6_4;\n}\n\n:TFR bytes_ABClT3lBXlYlSl_6_4, CCR\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n# The case \"02\" is covered by TAP\n\t\t( rows3_0=0x2 & ( columns7_4=0x1 | columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\n\t\t( rows3_0=0xA & ( columns7_4=0x1 ) ) \n\t) &\n\tbytes_ABClT3lBXlYlSl_6_4 & CCR \n{\n\tsetCCR( bytes_ABClT3lBXlYlSl_6_4 );\n}\n\n:TFR bytes_ABChT3hBXhYhSh_6_4, A\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0x8 & ( columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) \n\t) &\n\tbytes_ABChT3hBXhYhSh_6_4 & A \n{\n\tA = bytes_ABChT3hBXhYhSh_6_4;\n}\n\n:TFR A, CCRH\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xA & ( columns7_4=0x0 ) ) \n\t) &\n\tA & CCRH \n{\n\tCCRH = A;\n}\n\n:TFR words_CT3DXYS_6_4, CCRW\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xA & ( columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) \n\t) &\n\twords_CT3DXYS_6_4 & CCRW \n{\n\tsetCCRW( words_CT3DXYS_6_4 );\n}\n\n:TFR words_T3DXYS_6_4, words_T2DXYS_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n# The case \"57\" is covered by TXS\n# The case \"67\" is covered by TYS\n# The case \"75\" is covered by TSX\n# The case \"76\" is covered by TSY\n\t\t( rows3_0=0x3 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0x4 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0x5 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 ) ) | \n\t\t( rows3_0=0x6 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 ) ) | \n\t\t( rows3_0=0x7 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x7 ) ) |\n\t\t\n\t\t( rows3_0=0xB & ( columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0xC & ( columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0xD & ( columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0xE & ( columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | \n\t\t( rows3_0=0xF & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) \n\t) &\n\twords_T3DXYS_6_4 & words_T2DXYS_2_0 \n{\n\twords_T2DXYS_2_0 = words_T3DXYS_6_4;\n}\n\n:TFR D, TMP1\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0x4 ) ) \n\t) &\n\tD & TMP1 \n{\n\tTMP1 = D;\n}\n\n:TFR TMP1, D\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xC & ( columns7_4=0x3 ) ) \n\t) &\n\tTMP1 & D \n{\n\tD = TMP1;\n}\n\n:TFR CCRW, words_T2DXYS_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0x2 ) ) |\n\t\t( rows3_0=0xC & ( columns7_4=0x2 ) ) |\n\t\t( rows3_0=0xD & ( columns7_4=0x2 ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0x2 ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0x2 ) ) \n\t) &\n\tCCRW & words_T2DXYS_2_0 \n{\n\twords_T2DXYS_2_0 = CCRW;\n}\n\n:TFR A, bytes_T2h_XhYhSh_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0x0 ) ) |\n\n\t\t( rows3_0=0xD & ( columns7_4=0x0 ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0x0 ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0x0 ) ) \n\t) &\n\tA & bytes_T2h_XhYhSh_2_0 \n{\n\tbytes_T2h_XhYhSh_2_0 = A;\n}\n\n:TFR A, bytes_T2l_XlYlSl_2_0\tis Prefix18=0 & ( op8=0xB7 );\n\t(\n\t\t( rows3_0=0xB & ( columns7_4=0x1 ) ) |\n\n\t\t( rows3_0=0xD & ( columns7_4=0x1 ) ) |\n\t\t( rows3_0=0xE & ( columns7_4=0x1 ) ) |\n\t\t( rows3_0=0xF & ( columns7_4=0x1 ) ) \n\t) &\n\tA & bytes_T2l_XlYlSl_2_0 \n{\n\tbytes_T2l_XlYlSl_2_0 = A;\n}\n\n:TPA is Prefix18=0 & op16=0xB720 \n{\n\tA = CCR;\n}\n\n# TODO Not working properly with context regis ter for Prefix18\n:TRAP trapnum\tis Prefix18=1 & op8=0x30 & trapnum\n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\tPush2( IY );\n\tPush2( IX );\n\tPush1( A );\n\tPush1( B );\n\tPush1( CCR );\n\t\n\t$(I) = 1;\n\t\n\taddr:2 = $(VECTOR_TRAP);\n\tcall [addr];\n}\n\n:TST opr16a_8 is Prefix18=0 & (op8=0xF7); opr16a_8\n{\n\top1:1 = opr16a_8;\n\t$(Z) = (op1 == 0);\n\t$(N) = (op1 s< 0);\t\n\tV_equals_0();\n\t$(C) = 0;\t\n}\n\n:TST indexed1_5 is Prefix18=0 & (op8=0xE7); indexed1_5 \n{\n\top1:1 = indexed1_5;\n\t$(Z) = (op1 == 0);\n\t$(N) = (op1 s< 0);\t\n\tV_equals_0();\t\n\t$(C) = 0;\t\n}\n\n:TSTA is Prefix18=0 & op8=0x97 \n{\n\t$(Z) = (A == 0);\n\t$(N) = (A s< 0);\n\tV_equals_0();\t\n\t$(C) = 0;\n}\n\n:TSTB is Prefix18=0 & op8=0xD7 \n{\n\t$(Z) = (B == 0);\n\t$(N) = (B s< 0);\n\tV_equals_0();\t\n\t$(C) = 0;\n}\n\n@if defined(HCS12X)\n:TSTW opr16a_16 is Prefix18=1 & (op8=0xF7); opr16a_16\n{\n\top1:2 = opr16a_16;\n\t$(Z) = (op1 == 0);\n\t$(N) = (op1 s< 0);\t\n\tV_equals_0();\n\t$(C) = 0;\t\n}\n@endif\n\n@if defined(HCS12X)\n:TSTW indexed2_5 is Prefix18=1 & (op8=0xE7); indexed2_5 \n{\n\top1:2 = indexed2_5;\n\t$(Z) = (op1 == 0);\n\t$(N) = (op1 s< 0);\t\n\tV_equals_0();\t\n\t$(C) = 0;\t\n}\n@endif\n\n:TSTX is Prefix18=1 & op8=0x97\n{\n\t$(Z) = (IX == 0);\n\t$(N) = (IX s< 0);\n\tV_equals_0();\t\n}\n\n\n:TSTY is Prefix18=1 & op8=0xD7 \n{\n\t$(Z) = (IY == 0);\n\t$(N) = (IY s< 0);\n\tV_equals_0();\t\n}\n\n:TSX is Prefix18=0 & op16=0xB775 \n{\n\tIX = SP;\n}\n\n:TSY is Prefix18=0 & op16=0xB776 \n{\n\tIY = SP;\n}\n\n:TXS is Prefix18=0 & op16=0xB757 \n{\n\tSP = IX;\n}\n\n:TYS is Prefix18=0 & op16=0xB767 \n{\n\tSP = IY;\n}\n\n:WAI is Prefix18=0 & op8=0x3E \n{\n\ttmp:2 = inst_next;\n\tPush2( tmp );\n\tPush2( IY );\n\tPush2( IX );\n\tPush1( A );\n\tPush1( B );\n\tPush1( CCR );\n\t\n\tWaitForInterrupt();\n}\n \n:WAV is Prefix18=1 & op8=0x3C \n{\n\ttempIY:2 = WeightedAverageSOPHigh(B, IY, IX);\n\ttempD:2 = WeightedAverageSOPLow (B, IY, IX);\n\ttempIX:2 = WeightedAverageSOW(B, IY, IX);\n\t\n\tB = 0;\n\t\n\tIY = tempIY;\n\tD = tempD;\n\tIX = tempIX;\n}\n \n:WAVR is Prefix18=0 & op8=0x3C \n{\n\tWeightedAverageResume();\n}\n\n:XGDX is Prefix18=0 & op16=0xB7C5 \n{\n\ttmp:2 = IX;\n\tIX = D;\n\tD = tmp;\n}\n\n:XGDY is Prefix18=0 & op16=0xB7C6 \n{\n\ttmp:2 = IY;\n\tIY = D;\n\tD = tmp;\n}\n\n} # End with : XGATE=0\n" }, { "path": "pypcode/processors/HCS12/data/languages/XGATE.sinc", "content": "# sleigh specification file for XGATE MCU peripheral co-processor\n\n################################################################\n# Registers\n################################################################\n\n# register R0 always contains the value 0\ndefine register offset=0x100 size=2 [R0 R1 R2 R3 R4 R5 R6 R7];\ndefine register offset=0x100 size=1 [R0.H R0.L R1.H R1.L R2.H R2.L R3.H R3.L R4.H R4.L R5.H R5.L R6.H R6.L R7.H R7.L];\ndefine register offset=0x110 size=2 [XPC XCCR];\ndefine register offset=0x120 size=1 [XC XV XZ XN];\n\n# Individual status bits within the XCCR\n@define XN \"XN\" # XCCR[3,1] # Negative Flag\n@define XZ \"XZ\" # XCCR[2,1] # Zero Flag\n@define XV \"XV\" # XCCR[1,1] # Overflow Flag\n@define XC \"XC\" # XCCR[0,1] # Carry Flag\n\n################################################################\n# Tokens\n################################################################\ndefine token XOpWord16 (16)\n xop16\t\t= (0,15)\n opcode = (11,15)\n reg8 = (8,10)\n reg8_lo = (8,10)\n reg8_hi = (8,10)\n imm3 = (8,10)\n op9_10 = (9,10)\n bit_10 = (10,10)\n\timmrel9 = (0,9) signed\n\timmrel8 = (0,8) signed\n xop8 = (0,7)\n reg5 = (5,7)\n ximm4 = (4,7)\n ximm8 = (0,7)\n op4 = (0,4)\n op3 = (0,3)\n offs5 = (0,5)\n reg2 = (2,4)\n op2 = (0,1)\n;\n\n################################################################\n# Attach variables\n################################################################\n\nattach variables [reg8 reg5 reg2] [R0 R1 R2 R3 R4 R5 R6 R7];\n\nattach variables [reg8_lo ] [R0.L R1.L R2.L R3.L R4.L R5.L R6.L R7.L];\nattach variables [reg8_hi ] [R0.H R1.H R2.H R3.H R4.H R5.H R6.H R7.H];\n\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop leftShiftCarry;\ndefine pcodeop rightShiftCarry;\ndefine pcodeop parity;\ndefine pcodeop clearSemaphore;\ndefine pcodeop setSemaphore;\ndefine pcodeop setInterruptFlag;\ndefine pcodeop TerminateThread;\n\n################################################################\n# Macros Instructions\n################################################################\n\nmacro default_flags(result)\n{\n $(XZ) = (result == 0);\n\t$(XN) = (result s< 0);\n\t$(XV) = 0;\n\t#$(XC) not affected\n}\n\nmacro addition_flags(operand1, operand2, result)\n{\n\t$(XN) = (result s< 0);\n $(XZ) = ((result == 0) & ($(XZ)==1));\n\t$(XV) = (((operand1 & operand2 & ~result) | (~operand1 & ~operand2 & result)) & 0x8000) != 0;\n\t$(XC) = (((operand1 & operand2) | (operand2 & ~result) | (~result & operand1)) & 0x8000) != 0;\n}\n\nmacro subtraction_flags(register, operand, result) {\n\t$(XN) = (result s< 0);\n\t$(XZ) = (result == 0);\n\t$(XV) = ( ((register & ~operand & ~result) | (~register & operand & result)) & 0x8000 ) != 0;\n\t$(XC) = ( ((~register & operand) | (operand & result) | (~register & result)) & 0x8000 ) != 0;\n}\n\nmacro subtraction_flagsB(register, operand, result) {\n\t$(XN) = (result s< 0);\n\t$(XZ) = (result == 0);\n\t$(XV) = ( ((register & ~operand & ~result) | (~register & operand & result)) & 0x80 ) != 0;\n\t$(XC) = ( ((~register & operand) | (operand & result) | (result & ~register)) & 0x80 ) != 0;\n}\n\nmacro subtraction_flagsC(register, operand, result) {\n\t$(XN) = (result s< 0);\n\t$(XZ) = ( (result == 0) & ($(XZ) == 1));\n\t$(XV) = ( ((register & ~operand & ~result) | (~register & operand & result)) & 0x8000 ) != 0;\n\t$(XC) = ( ((~register & operand) | (operand & result) | (~register & result)) & 0x8000 ) != 0;\n}\n\nmacro shiftFlags(result,old)\n{\n\t$(XN) = (result s< 0);\n\t$(XZ) = (result == 0);\n\ttmp:2 = (old >> 15) ^ (result >> 15);\n\t$(XV) = tmp(1);\n}\n\nmacro getbit(res,in,bitnum) {\n res = ((in >> bitnum) & 1) != 0;\n}\n\n#\n# computes a fake PPAGE page mapping based on the 16 bit input address\n# The XGATE memory is mapped to the pages of physical memory\n# Warning: This might not be the correct mapping on all XGATE processors\n#\n# 0000-07ff = 0x00_0000 - 0x00_07ff\n# 0800-7fff = 0x78_0800 - XGFLASH_HIGH\n# 8000-ffff = 0x0f_0800 - 0x0f_ffff\n#\nmacro computePage(addr) {\n\tlocal isReg:1 = addr < 0x800;\n\tlocal isFlash:1 = addr >= 0x800 & addr < 0x7fff;\n\tlocal isRam:1 = addr >= 0x8000;\n\tphysPage = (zext(isReg) * 0x0)+ (zext(isFlash) * (0x78 << 16)) + (zext(isRam) * (0xf<<16));\n}\n\n################################################################\n# Constructors\n################################################################\n\n#rel9 defined in HCS_HC12.sinc\n# range -256 through +255\nwith : XGATE=1 {\nrel9: reloc is immrel8 [ reloc = inst_next + (immrel8 * 2); ] { export *:1 reloc; }\n\n# range -512 through +512\nrel10: reloc is immrel9 [ reloc = inst_next + (immrel9 * 2); ] { export *:1 reloc; }\n\nrd : reg8 is reg8 { export reg8; }\n\nrs1: reg5 is reg5 & reg5=0 { export 0:2; }\nrs1: reg5 is reg5 { export reg5; }\n\nrs2: reg2 is reg2 & reg2=0 { export 0:2; }\nrs2: reg2 is reg2 { export reg2; }\n\n\nrd_lo: reg8 is reg8 & reg8_lo { export reg8_lo; }\nrd_hi: reg8 is reg8 & reg8_hi { export reg8_hi; }\n\n\n\n# Add with carry\n:ADC rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x3\n{\n local result:2 = rs1 + rs2 + zext($(XC));\n rd = result;\n \n addition_flags(rs1, rs2, result);\n}\n\n# Add without carry\n:ADD rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x2\n{\n local result:2 = rs1 + rs2;\n rd = result;\n \n addition_flags(rs1, rs2, result);\n}\n\n# Add immediate 8-bit constant (high byte)\n:ADDH rd, ximm8 is opcode=0x1d & rd & ximm8\n{\n\tlocal val:2 = ximm8 << 8;\n local result:2 = rd + val;\n \n addition_flags(rd, val, result);\n \n rd = result;\n}\n\n# Add immediate 8-bit constant (low byte)\n:ADDL rd, ximm8 is opcode=0x1c & rd & ximm8\n{\n local result:2 = rd + ximm8;\n \n\t$(XN) = (result s< 0);\n $(XZ) = ((result == 0) & ($(XZ)==1));\n\t$(XV) = ((~rd & result) & 0x8000) != 0;\n\t$(XC) = ((rd & ~result) & 0x8000) != 0;\n rd = result;\n}\n\n# Logical AND\n:AND rd, rs1, rs2 is opcode=0x2 & rd & rs1 & rs2 & op2=0x0\n{\n rd = rs1 & rs2;\n \n default_flags(rd);\n}\n\n# Logical AND immediate 8-bit constant (high byte)\n:ANDH rd, ximm8 is opcode=0x11 & rd & ximm8 & rd_hi\n{\n rd_hi = rd_hi & ximm8;\n \n\tdefault_flags(rd_hi);\n}\n\n# Logical AND immediate 8-bit constant (low byte)\n:ANDL rd, ximm8 is opcode=0x10 & rd & ximm8 & rd_lo\n{\n rd_lo = rd_lo & ximm8;\n \n\tdefault_flags(rd_lo);\n}\n\n# Arithmetic Shift Right\n:ASR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0x9\n{\n\tgetbit($(XC), rd, ximm4-1);\n rd = rd s>> ximm4;\n \n default_flags(rd);\n}\n\n:ASR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x11\n{\n\tgetbit($(XC), rd, rs1-1);\n rd = rd s>> rs1;\n \n default_flags(rd);\n}\n\n# Branch if Carry Cleared\n:BCC rel9 is opcode=0x4 & op9_10=0x0 & rel9\n{\n if ($(XC) == 0) goto rel9;\n}\n\n\n# Branch if Carry Set\n:BCS rel9 is opcode=0x4 & op9_10=0x1 & rel9\n{\n if ($(XC) == 1) goto rel9;\n}\n\n# Branch of Equal\n:BEQ rel9 is opcode=0x4 & op9_10=0x3 & rel9\n{\n if ($(XZ) == 1) goto rel9;\n}\n\n# Bit Field Extract\n:BFEXT rd, rs1, rs2 is opcode=0xc & rd & rs1 & rs2 & op2=0x3\n{\n local origin:2 = rs2 & 0xf;\n local width:2 = (rs2 >> 4) & 0xf;\n local mask:2 = (0xffff >> (16-(width + 1))) << origin;\n local result:2 = (rs1 & mask) >> origin;\n \n rd = result;\n \n default_flags(rd);\n}\n\n# Bit Field Find First One\n:BFFO rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x10\n{\n # 15 - count leading zeros\n tmp:2 = rs1;\n $(XC) = (rs1 == 0);\n rd = zext(tmp != 0) * (15 - lzcount(tmp));\n\n\tdefault_flags(rd);\n}\n\n# Bit Field Insert\n:BFINS rd, rs1, rs2 is opcode=0xd & rd & rs1 & rs2 & op2=0x3\n{\n local origin:2 = rs2 & 0xf;\n local width:2 = (rs2 >> 4) & 0xf;\n local mask:2 = (0xffff >> (16-(width + 1))) << origin;\n local result:2 = (rs1 & mask);\n \n rd = (rd & ~mask) | result;\n \n\tdefault_flags(rd);\n}\n\n# Bit Field Insert and Invert\n:BFINSI rd, rs1, rs2 is opcode=0xe & rd & rs1 & rs2 & op2=0x3\n{\n local origin:2 = rs2 & 0xf;\n local width:2 = (rs2 >> 4) & 0xf;\n local mask:2 = (0xffff >> (16-(width + 1))) << origin;\n local result:2 = (~rs1 & mask);\n \n rd = (rd & ~mask) | result;\n \n default_flags(rd);\n}\n\n# Bit Field Insert and XNOR\n:BFINSX rd, rs1, rs2 is opcode=0xf & rd & rs1 & rs2 & op2=0x3\n{\n local origin:2 = rs2 & 0xf;\n local width:2 = (rs2 >> 4) & 0xf;\n local mask:2 = (0xffff >> (16-(width + 1))) << origin;\n local result:2 = (~(rs1 ^ rd) & mask);\n \n rd = (rd & ~mask) | result;\n \n default_flags(rd);\n}\n\n# Branch if Greater than or Equal to Zero\n:BGE rel9 is opcode=0x6 & op9_10=0x2 & rel9\n{\n if (($(XN) ^ $(XV)) == 0) goto rel9;\n}\n\n# Branch if Greater than Zero\n:BGT rel9 is opcode=0x7 & op9_10=0x0 & rel9\n{\n if (($(XZ) | ($(XN) ^ $(XV))) == 0) goto rel9;\n}\n\n# Branch if Higher\n:BHI rel9 is opcode=0x6 & op9_10=0x0 & rel9\n{\n if (($(XC) | $(XZ)) == 0) goto rel9;\n}\n\n#:BHS rel9 is opcode=0x4 & op9_10=0x0 & rel9 see BCC\n\n# Bit Test immediate 8-bit constant (high byte)\n:BITH rd, ximm8 is opcode=0x13 & rd & ximm8 & rd_hi\n{\n local val = rd_hi & ximm8;\n \n default_flags(val);\n}\n\n# Bit Test immediate 8-bit constant (low byte)\n:BITL reg8, ximm8 is opcode=0x12 & reg8 & ximm8 & rd_lo\n{\n local val = rd_lo & ximm8;\n \n default_flags(val);\n}\n\n# Branch if Less or Equal to Zero\n:BLE rel9 is opcode=0x7 & op9_10=0x1 & rel9\n{\n if ($(XZ) | ($(XN) ^ $(XV))) goto rel9;\n}\n\n#:BLO rel9 is opcode=0x4 & op9_10=0x1 & rel9 See BCS\n\n# Branch if Lower or Same\n:BLS rel9 is opcode=0x6 & op9_10=0x1 & rel9\n{\n if (($(XC) | $(XZ)) == 1) goto rel9;\n}\n\n# Branch of Lower than Zero\n:BLT rel9 is opcode=0x6 & op9_10=0x3 & rel9\n{\n if (($(XN) ^ $(XV)) == 1) goto rel9;\n}\n\n# Branch if Minus\n:BMI rel9 is opcode=0x5 & op9_10=0x1 & rel9\n{\n if ($(XN) == 1) goto rel9;\n}\n\n# Branch if Not Equal\n:BNE rel9 is opcode=0x4 & op9_10=0x2 & rel9\n{\n if ($(XZ) == 0) goto rel9;\n}\n\n# Branch if Plus\n:BPL rel9 is opcode=0x5 & op9_10=0x0 & rel9\n{\n\tif ($(XN) == 0) goto rel9;\n}\n\n# Branch Always\n:BRA rel10 is opcode=0x7 & bit_10=0x1 & rel10\n{\n\tgoto rel10;\n}\n# Break\n:BRK is xop16=0x0\n{\n # put xgate into debug mode and set breakpoint\n\tgoto inst_next;\n}\n\n# Branch if Overflow Cleared\n:BVC rel9 is opcode=0x5 & op9_10=0x2 & rel9\n{\n\tif ($(XV) == 0) goto rel9;\n}\n\n# Branch if Overflow Set\n:BVS rel9 is opcode=0x5 & op9_10=0x3 & rel9\n{\n\tif ($(XV) == 2) goto rel9;\n}\n\n# Compare\n# synonym for SUB R0, RS1, RS2\n:CMP rs1, rs2 is opcode=0x3 & reg8=0x0 & rs1 & rs2 & op2=0x0\n{\n\ttmp:2 = rs1 - rs2;\n\tsubtraction_flags(rs1, rs2, tmp);\n}\n\n# Compare Immediate 8-bit constant (low byte)\n:CMPL rd, ximm8 is opcode=0x1a & rd & ximm8\n{\n\tlocal val:1 = rd:1;\n\tlocal tmp:1 = val - ximm8;\n\tlocal xtmp:1 = ximm8;\n\tsubtraction_flagsB(val, xtmp, tmp);\n}\n\n# One's Complement\n:COM rd, rs2 is opcode=0x2 & rd & reg5=0x0 & rs2 & op2=0x3\n{\n\tlocal val:2 = ~rs2;\n\trd = val;\n\t\n\tdefault_flags(rd);\n}\n\n:COM rd is opcode=0x2 & rd & reg5=0x0 & rs2 & reg8=reg2 & op2=0x3\n{\n\tlocal val:2 = ~rs2;\n\trd = val;\n\t\n\tdefault_flags(rd);\n}\n\n# Compare with Carry\n:CPC rs1, rs2 is opcode=0x3 & reg8=0x0 & rs1 & rs2 & op2=0x1\n{\n\tlocal tmp:2 = rs1 - rs2 - zext($(XC));\n\tsubtraction_flags(rs1, rs2, tmp);\n}\n\n# Compare Immediate 8-bit constant with carry (high byte)\n:CPCH rd, ximm8 is opcode=0x1b & rd & ximm8\n{\n\tlocal val:2 = rd >> 8;\n\tlocal tmp:1 = val(1) - ximm8 - $(XC);\n\tlocal xtmp:1 = ximm8;\n\tsubtraction_flagsB(val(1), xtmp, tmp);\n}\n\n# Clear Semaphore\n:CSEM rd is opcode=0x0 & rd & xop8=0xf0\n{\n # treat as NOP\n clearSemaphore(rd);\n}\n\n:CSEM imm3 is opcode=0x0 & imm3 & xop8=0xf1\n{\n\tlocal sem:1 = imm3;\n clearSemaphore(sem);\n}\n\n\n# Logical Shift Left with Carry\n:CSL rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xa\n{\n\tlocal Ctmp:2 = zext($(XC));\n\tlocal shift:2 = ((ximm4-1)%16+1);\n\tlocal oldRd:2 = rd >> 15;\n\tgetbit($(XC), rd, 16-shift);\n\tleftShiftCarry(rd,Ctmp,shift,rd);\n\tshiftFlags(rd,oldRd);\n}\n\n:CSL rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x12\n{\n\tlocal Ctmp:2 = zext($(XC));\n\t#if rs1 > 16, then rs1 = 16\n\tlocal rsgt:2 = zext(rs1>16);\n\tlocal rslt:2 = zext(rs1<16);\n\tlocal shift:2 = rs1*rsgt + 16*rslt;\n\tlocal oldRd:2 = rd >> 15;\n\tgetbit($(XC), rd, 16-shift);\n\tleftShiftCarry(rd,Ctmp,shift,rd);\n\tshiftFlags(rd,oldRd);\n}\n\n# Logical Shift Right with Carry\n:CSR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xb\n{\n\tlocal Ctmp:2 = zext($(XC));\n\tlocal shift:2 = ((ximm4-1)%16+1);\n\tlocal oldRd:2 = rd >> 15;\n\tgetbit($(XC), rd, shift-1);\n\trightShiftCarry(rd,Ctmp,shift,rd);\n\tshiftFlags(rd,oldRd);\n}\n\n:CSR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x13\n{\n\tlocal Ctmp:2 = zext($(XC));\n\t#if rs1 > 16, then rs1 = 16\n\tlocal rsgt:2 = zext(rs1>16);\n\tlocal rslt:2 = zext(rs1<16);\n\tlocal shift:2 = rs1*rsgt + 16*rslt;\n\tlocal oldRd:2 = rd >> 15;\n\tgetbit($(XC), rd, shift-1);\n\trightShiftCarry(rd,Ctmp,shift,rd);\n\tshiftFlags(rd,oldRd);\n}\n\n:CSR rd, rs1 is opcode=0x1 & rd & rs1 & reg5=0 & op4=0x13\n{\n\t$(XN) = (rd s< 0);\n\t$(XZ) = (rd == 0);\n\t$(XV) = 0;\n\t# $(XC) is unaffected\n}\n\n# Jump and Link\n:JAL rd is opcode=0x0 & rd & xop8=0xf6\n{\n\tlocal dest:2 = rd;\n\trd = inst_next;\n\tcall [dest];\n}\n\n# Load byte from memory (low byte)\n:LDB rd, (rs1, offs5) is opcode=0x8 & rd & rs1 & offs5\n{\n\tlocal addr = rs1 + offs5;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = *:1 (dst);\n\trd = (rd & 0xff00) | zext(val);\n}\n\n:LDB rd, (rs1, rs2) is opcode=0xc & rd & rs1 & rs2 & op2=0x0\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = *:1 (dst);\n\trd = (rd & 0xff00) | zext(val);\n}\n\n:LDB rd, (rs1, rs2+) is opcode=0xc & rd & rs1 & rs2 & op2=0x1\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = *:1 (dst);\n\trd = (rd & 0xff00) | zext(val);\n\trs1 = rs1 + 1;\n}\n\n:LDB rd, (rs1, -rs2) is opcode=0xc & rd & rs1 & rs2 & op2=0x2\n{\n\trs2 = rs2 - 1;\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = *:1 (dst);\n\trd = (rd & 0xff00) | zext(val);\n}\n\n\n# Load Immediate 8-bit constant (high byte)\n:LDH rd, ximm8 is opcode=0x1f & rd & ximm8 & rd_hi\n{\n\trd_hi = ximm8;\n}\n\n\n# Load Immediate 8-bit constant (low byte)\n:LDL rd, ximm8 is opcode=0x1e & rd & ximm8\n{\n\trd = ximm8;\n}\n\n# Load Word from Memory\n:LDW rd, (rs1, offs5) is opcode=0x9 & rd & rs1 & offs5\n{\n\tlocal addr = rs1 + offs5;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = *:2 (dst);\n\trd = val;\n}\n\n:LDW rd, (rs1, rs2) is opcode=0xd & rd & rs1 & rs2 & op2=0x0\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = *:2 (dst);\n\trd = val;\t\n}\n\n:LDW rd, (rs1, rs2+) is opcode=0xd & rd & rs1 & rs2 & op2=0x1\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = *:2 (dst);\n\trd = val;\n\trs1 = rs1 + 2;\n}\n:LDW rd, (rs1, -rs2) is opcode=0xd & rd & rs1 & rs2 & op2=0x2\n{\n\trs2 = rs2 - 2;\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = *:2 (dst);\n\trd = val;\n}\n\n# Logical Shift Left\n:LSL rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xc\n{\n\tlocal shift:2 = ((ximm4-1)%16+1);\n\tgetbit($(XC), rd, 16-shift);\n\tlocal oldRd:2 = rd >> 15;\n\trd = rd << shift;\n\tshiftFlags(rd,oldRd);\n}\n\n:LSL rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x14\n{\n\tgetbit($(XC), rd, 16-rs1);\n\tlocal oldRd:2 = rd >> 15;\n\trd = rd << rs1;\n\tshiftFlags(rd,oldRd);\n}\n\n# Logical Shift Right\n:LSR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xd\n{\n\tgetbit($(XC), rd, ximm4-1);\n\tlocal oldRd:2 = rd >> 15;\n\trd = rd >> ximm4;\n\tshiftFlags(rd,oldRd);\n}\n\n:LSR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x15\n{\n\tgetbit($(XC), rd, rs1-1);\n\tlocal oldRd:2 = (rd >> 15);\n\trd = rd >> rs1;\n\tshiftFlags(rd,oldRd);\n}\n\n# Move Register Content\n# Synonym for OR RD, R0, RS\n:MOV rd, rs2 is opcode=0x2 & rd & reg5=0 & rs2 & op2=0x2\n{\n\trd = rs2;\n\n\tdefault_flags(rd);\n}\n\n# Two's Complement\n:NEG rd, rs2 is opcode=0x3 & rd & reg8!=0 & reg5=0x0 & rs2 & op2=0x0\n{\n\tlocal tmp:2 = -rs2;\n\trd = tmp;\n\t$(XN) = (rd s< 0);\n\t$(XZ) = (rd == 0);\n\t$(XV) = (((rs2 & rd) & 0x8000) != 0);\n\t$(XC) = (((rs2 | rd) & 0x8000) != 0);\n}\n\n:NEG rd is opcode=0x3 & rd & reg5=0x0 & rs2 & reg2=reg8 & op2=0x0\n{\n\tlocal tmp:2 = -rs2;\n\trd = tmp;\n\t$(XN) = (rd s< 0);\n\t$(XZ) = (rd == 0);\n\t$(XV) = (((rs2 & rd) & 0x8000) != 0);\n\t$(XC) = (((rs2 | rd) & 0x8000) != 0);\n}\n\n# No Op\n:NOP is xop16=0x100 {}\n\n# Logical OR\n:OR rd, rs1, rs2 is opcode=0x2 & rd & rs1 & rs2 & op2=0x2\n{\n local result:2 = rs1 | rs2;\n rd = result;\n\n\tdefault_flags(result);\n}\n\n# Logical OR Immediate 8-bit Constant (high byte)\n:ORH rd, ximm8 is opcode=0x15 & rd & ximm8 & rd_hi\n{\n rd_hi = rd_hi | ximm8;\n \n\tdefault_flags(rd_hi);\n}\n\n# Logical OR Immediate 8-bit Constant (low byte)\n:ORL rd, ximm8 is opcode=0x14 & rd & ximm8 & rd_lo\n{\n rd_lo = rd_lo | ximm8;\n \n \tdefault_flags(rd_lo);\n}\n\n# Calculate Parity\n:PAR rd is opcode=0x0 & rd & xop8=0xf5\n{\n\tparity(rd, $(XC));\n\t\n default_flags(rd);\n}\n\n# Rotate Left\n:ROL rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xe\n{\n\tlocal cnt:2 = ximm4;\n\trd = (rd << cnt) | (rd >> (16 - cnt));\n\t\n default_flags(rd);\n}\n\n:ROL rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x16\n{\n\tlocal cnt:2 = rs1 & 0xf;\n\trd = (rd << cnt) | (rd >> (16 - cnt));\n\t\n default_flags(rd);\n}\n\n# Rotate Right\n:ROR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xf\n{\n\tlocal cnt:2 = ximm4;\n\trd = (rd >> cnt) | (rd << (16 - cnt));\n\t\n default_flags(rd);\n}\n\n:ROR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x17\n{\n\tlocal cnt:2 = rs1 & 0xf;\n\trd = (rd >> cnt) | (rd << (16 - cnt));\n\t\n default_flags(rd);\n}\n# Return to Scheduler\n# Implement as NOP for now\n:RTS is xop16=0x0200 {\n\tXPC = TerminateThread();\n\treturn [XPC];\n}\n\n# Subtract with Carry\n:SBC rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x1\n{\n\tlocal result:2 = rs1 - rs2 - zext($(XC));\n\trd = result;\n\tsubtraction_flagsC(rs1, rs2, result);\n}\n\n# Sign Extent Byte to Word\n:SEX rd is opcode=0x0 & rd & xop8=0xf4\n{\n\tlocal result:1 = rd:1 & 0xff;\n\trd = sext(result);\n\t\n default_flags(rd);\n}\n# Set Interrupt Flag\n# TODO: implement interrupt flags\n:SIF is xop16=0x0300\n{\n\tsetInterruptFlag();\n}\n\n:SIF rd is opcode=0x0 & rd & xop8=0xf7\n{\n\tsetInterruptFlag();\n}\n\n# Set Semaphore\n# TODO: implement semaphores\n:SSEM imm3 is opcode=0x0 & imm3 & xop8=0xf2\n{\n\tlocal sem:1 = imm3;\n\tsetSemaphore(sem);\n}\n\n:SSEM rd is opcode=0x0 & rd & xop8=0xf3\n{\n\tsetSemaphore(rd);\n}\n\n# Store Byte to Memory (low byte)\n:STB rd, (rs1, offs5) is opcode=0xa & rd & rs1 & offs5\n{\n\tlocal addr = rs1 + offs5;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = rd:1;\n\t*dst = val;\n}\n\n:STB rd, (rs1, rs2) is opcode=0xe & rd & rs1 & rs2 & op2=0x0\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = rd:1;\n\t*dst = val;\n}\n\n:STB rd, (rs1, rs2+) is opcode=0xe & rd & rs1 & rs2 & op2=0x1\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = rd:1;\n\t*dst = val;\n\trs2 = rs2 + 1;\n}\n\n:STB rd, (rs1, -rs2) is opcode=0xe & rd & rs1 & rs2 & op2=0x2\n{\n\trs2 = rs2 - 1;\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:1 = rd:1;\n\t*dst = val;\n}\n\n# Store Word to Memory\n:STW rd, (rs1, offs5) is opcode=0xb & rd & rs1 & offs5\n{\n\tlocal addr = rs1 + offs5;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = rd;\n\t*dst = val;\n}\n\n:STW rd, (rs1, rs2) is opcode=0xf & rd & rs1 & rs2 & op2=0x0\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = rd;\n\t*dst = val;\n\trs2 = rs2 + 1;\n}\n\n:STW rd, (rs1, rs2+) is opcode=0xf & rd & rs1 & rs2 & op2=0x1\n{\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = rd;\n\t*dst = val;\n\trs2 = rs2 + 2;\n}\n\n:STW rd, (rs1, -rs2) is opcode=0xf & rd & rs1 & rs2 & op2=0x2\n{\n\trs2 = rs2 - 2;\n\tlocal addr = rs1 + rs2;\n\tcomputePage(addr);\n\tlocal dst:3 = segment(PPAGE,addr);\n\tlocal val:2 = rd;\n\t*dst = val;\n}\n\n# Subtract without Carry\n:SUB rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x0\n{\n\tlocal result:2 = rs1 - rs2;\n\trd = result;\n\t\n\tsubtraction_flags(rs1, rs2, result);\n}\n\n\n# Subtract Immediate 8-bit constant (high byte)\n:SUBH rd, ximm8 is opcode=0x19 & rd & ximm8\n{\n\tlocal val:2 = ximm8 << 8;\n local result:2 = rd - val;\n \n subtraction_flags(rd, val, result);\n \n rd = result;\n}\n\n# Subtract Immediate 8-bit constant (low byte)\n:SUBL rd, ximm8 is opcode=0x18 & rd & ximm8\n{\n\tlocal val:2 = ximm8;\n local result:2 = rd - val;\n \n\t$(XN) = (result s< 0);\n $(XZ) = ((result == 0) & ($(XZ)==1));\n\t$(XV) = ((~rd & result) & 0x8000) != 0;\n\t$(XC) = ((rd & ~result) & 0x8000) != 0;\n rd = result;\n}\n\n# Transfer from and to Special Registers\n:TFR rd, XCCR is opcode=0x0 & rd & xop8=0xf8 & XCCR\n{\n\tlocal val:1 = ((($(XN) << 1) | $(XZ) << 1) | $(XV) << 1) | $(XC);\n\trd = zext(val);\n}\n\n:TFR XCCR, rd is opcode=0x0 & rd & xop8=0xf9 & XCCR\n{\n\tXCCR = rd & 0xf;\n\t$(XN) = rd[3,1];\n\t$(XZ) = rd[2,1];\n\t$(XV) = rd[1,1];\n\t$(XC) = rd[0,1];\n}\n\n:TFR rd, XPC is opcode=0x0 & rd & xop8=0xfa & XPC\n{\n\trd = inst_next + 2;\n}\n\n# Test Register\n# Synonym for SUB R0, RS, R0\n:TST rs1 is opcode=0x3 & reg8=0x0 & rs1 & reg2=0x0 & op2=0x0\n{\n\tlocal result:2 = rs1;\n\t\n\tsubtraction_flags(rs1,0,result);\n}\n\n# Logical Exclusive NOR\n:XNOR rd, rs1, rs2 is opcode=0x2 & rd & rs1 & rs2 & op2=0x3\n{\n local result:2 = ~(rs1 ^ rs2);\n rd = result;\n \n default_flags(result);\n}\n\n# Logical Exclusive NOR Immediate 8-bit constant (high byte)\n:XNORH rd, ximm8 is opcode=0x17 & rd & ximm8 & rd_hi\n{\n rd_hi = ~(rd_hi ^ ximm8);\n \n\tdefault_flags(rd_hi);\n}\n\n# Logical Exclusive NOR Immediate 8-bit constant (low byte)\n:XNORL rd, ximm8 is opcode=0x16 & rd & ximm8 & rd_lo\n{\n rd_lo= ~(rd_lo^ ximm8);\n \n\tdefault_flags(rd_lo);\n}\n\n}" }, { "path": "pypcode/processors/HCS12/data/manuals/HCS12.idx", "content": "@S12XCPUV2.pdf[ CPU12/CPU12X Reference Manual, Rev. v01.04 21 Apr. 2016, nxp.com ]\nABA, 84\nABX, 85\nABY, 86\nADCA, 87\nADCB, 88\nADDA, 89\nADDB, 90\nADDD, 91\nADDX, 92\nADDY, 93\nADED, 94\nADEX, 95\nADEY, 96\nANDA, 97\nANDB, 98\nANDCC, 99\nANDX, 100\nANDY, 101\nASL, 102\nASLA, 103\nASLB, 104\nASLD, 105\nASLW, 106\nASLX, 107\nASLY, 108\nASR, 109\nASRA, 110\nASRB, 111\nASRW, 112\nASRX, 113\nASRY, 114\nBCC, 115\nBCLR, 116\nBCS, 117\nBEQ, 118\nBGE, 119\nBGND, 120\nBGT, 121\nBHI, 122\nBHS, 123\nBITA, 124\nBITB, 125\nBITX, 126\nBITY, 127\nBLE, 128\nBLO, 129\nBLS, 130\nBLT, 131\nBMI, 132\nBNE, 133\nBPL, 134\nBRA, 135\nBRCLR, 136\nBRN, 137\nBRSET, 138\nBSET, 139\nBSR, 140\nBTAS, 141\nBVC, 142\nBVS, 143\nCALL, 144\nCBA, 145\nCLC, 146\nCLI, 147\nCLR, 148\nCLRA, 149\nCLRB, 150\nCLRW, 151\nCLRX, 152\nCLRY, 153\nCLV, 154\nCMPA, 155\nCMPB, 156\nCOM, 157\nCOMA, 158\nCOMB, 159\nCOMW, 160\nCOMX, 161\nCOMY, 162\nCPD, 163\nCPED, 164\nCPES, 165\nCPEX, 166\nCPEY, 167\nCPS, 168\nCPX, 169\nCPY, 170\nDAA, 171\nDBEQ, 172\nDBNE, 173\nDEC, 174\nDECA, 175\nDECB, 176\nDECW, 177\nDECX, 178\nDECY, 179\nDES, 180\nDEX, 181\nDEY, 182\nEDIV, 183\nEDIVS, 184\nEMACS, 185\nEMAXD, 186\nEMAXM, 187\nEMIND, 188\nEMINM, 189\nEMUL, 190\nEMULS, 191\nEORA, 192\nEORB, 193\nEORX, 194\nEORY, 195\nETBL, 196\nEXG, 197\nFDIV, 199\nGLDAA, 200\nGLDAB, 201\nGLDD, 202\nGLDS, 203\nGLDX, 204\nGLDY, 205\nGSTAA, 206\nGSTAB, 207\nGSTD, 208\nGSTS, 209\nGSTX, 210\nGSTY, 211\nIBEQ, 212\nIBNE, 213\nIDIV, 214\nIDIVS, 215\nINC, 216\nINCA, 217\nINCB, 218\nINCW, 219\nINCX, 220\nINCY, 221\nINS, 222\nINX, 223\nINY, 224\nJMP, 225\nJSR, 226\nLBCC, 227\nLBCS, 228\nLBEQ, 229\nLBGE, 230\nLBGT, 231\nLBHI, 232\nLBHS, 233\nLBLE, 234\nLBLO, 235\nLBLS, 236\nLBLT, 237\nLBMI, 238\nLBNE, 239\nLBPL, 240\nLBRA, 241\nLBRN, 242\nLBVC, 243\nLBVS, 244\nLDAA, 245\nLDAB, 246\nLDD, 247\nLDS, 248\nLDX, 249\nLDY, 250\nLEAS, 251\nLEAX, 252\nLEAY, 253\nLSL, 254\nLSLA, 255\nLSLB, 256\nLSLD, 257\nLSLW, 258\nLSLX, 259\nLSLY, 260\nLSR, 261\nLSRA, 262\nLSRB, 263\nLSRD, 264\nLSRW, 265\nLSRX, 266\nLSRY, 267\nMAXA, 268\nMAXM, 269\nMEM, 270\nMINA, 271\nMINM, 272\nMOVB, 273\nMOVW, 280\nMUL, 287\nNEG, 288\nNEGA, 289\nNEGB, 290\nNEGW, 291\nNEGX, 292\nNEGY, 293\nNOP, 294\nORAA, 295\nORAB, 296\nORCC, 297\nORX, 298\nORY, 299\nPSHA, 300\nPSHB, 301\nPSHC, 302\nPSHCW, 303\nPSHD, 304\nPSHX, 305\nPSHY, 306\nPULA, 307\nPULB, 308\nPULC, 309\nPULCW, 310\nPULD, 311\nPULX, 312\nPULY, 313\nREV, 314\nREVW, 316\nROL, 318\nROLA, 319\nROLB, 320\nROLW, 321\nROLX, 322\nROLY, 323\nROR, 324\nRORA, 325\nRORB, 326\nRORW, 327\nRORX, 328\nRORY, 329\nRTC, 330\nRTI, 331\nRTS, 332\nSBA, 333\nSBCA, 334\nSBCB, 335\nSBED, 336\nSBEX, 337\nSBEY, 338\nSEC, 339\nSEI, 340\nSEV, 341\nSEX, 342\nSTAA, 343\nSTAB, 344\nSTD, 345\nSTOP, 346\nSTS, 348\nSTX, 349\nSTY, 350\nSUBA, 351\nSUBB, 352\nSUBD, 353\nSUBX, 354\nSUBY, 355\nSWI, 356\nSYS, 357\nTAB, 358\nTAP, 359\nTBA, 360\nTBEQ, 361\nTBL, 362\nTBNE, 363\nTFR, 364\nTPA, 366\nTRAP, 367\nTST, 368\nTSTA, 369\nTSTB, 370\nTSTW, 371\nTSTX, 372\nTSTY, 373\nTSX, 374\nTSY, 375\nTXS, 376\nTYS, 377\nWAI, 378\nWAV, 379\nXGDX, 380\nXGDY, 381\n\n@MC9S12XEP100RMV1.pdf[ MC9S12XEP100 Reference Manual, Rev. 1.25 02/2013, nxp.com ]\nADC, 389\nADD, 390\nADDH, 391\nADDL, 392\nAND, 393\nANDH, 394\nANDL, 395\nASR, 396\nBCC, 397\nBCS, 398\nBEQ, 399\nBFEXT, 400\nBFFO, 401\nBFINS, 402\nBFINSI, 403\nBFINSX, 404\nBGE, 405\nBGT, 406\nBHI, 407\nBHS, 408\nBITH, 409\nBITL, 410\nBLE, 411\nBLO, 412\nBLS, 413\nBLT, 414\nBMI, 415\nBNE, 416\nBPL, 417\nBRA, 418\nBRK, 419\nBVC, 420\nBVS, 421\nCMP, 422\nCMPL, 423\nCOM, 424\nCPC, 425\nCPCH, 426\nCSEM, 427\nCSL, 428\nCSR, 429\nJAL, 430\nLDB, 431\nLDH, 432\nLDL, 433\nLDW, 434\nLSL, 435\nLSR, 436\nMOV, 437\nNEG, 438\nNOP, 439\nOR, 440\nORH, 441\nORL, 442\nPAR, 443\nROL, 444\nROR, 445\nRTS, 446\nSBC, 447\nSEX, 448\nSIF, 449\nSSEM, 450\nSTB, 451\nSTW, 452\nSUB, 453\nSUBH, 454\nSUBL, 455\nTFR, 456\nTST, 457\nXNOR, 458\nXNORH, 459\nXNORL, 460\n" }, { "path": "pypcode/processors/JVM/data/languages/JVM.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/JVM/data/languages/JVM.ldefs", "content": "\n\n\n \n Generic JVM\n \n \n \n\n" }, { "path": "pypcode/processors/JVM/data/languages/JVM.opinion", "content": "\n \n \n \n\n" }, { "path": "pypcode/processors/JVM/data/languages/JVM.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/JVM/data/languages/JVM.slaspec", "content": "# Stack Convention:\n# 1) Stack grows to smaller addresses (Subtract to push)\n# 2) Stack pointer points to a valid item on the stack\n\n# A Java \"word\" can hold a boolean, byte, short, float, int, reference, or returnAddress.\n# Two \"words\" hold a long or a double\n@define SIZE \"4\"\t\t# Number of bytes in the Java Word\n@define DOUBLE_SIZE \"8\"\n@define INT_SUPPORT \"1\"\n\n\n\n###############################################################################\n# Basic Definitions\n###############################################################################\ndefine endian=big;\ndefine alignment=1;\n\ndefine space ram type=ram_space size=$(SIZE) default;\ndefine space register type=register_space size=$(SIZE);\ndefine space constantPool\t\t type=ram_space size=$(SIZE);\ndefine space localVariableArray type=ram_space size=$(SIZE);\ndefine space parameterSpace type=ram_space size=$(SIZE);\n\ndefine register offset = 0x0 size=$(DOUBLE_SIZE) [cat2_return_value];\ndefine register offset = 0x0 size=$(SIZE) [_ return_value SP PC switch_target return_address call_target LVA]; \n\n#define register offset = 0x0 size=$(DOUBLE_SIZE) [cat2_return_value];\n#define register offset = 0x8 size=$(SIZE) [return_value SP PC switch_target return_address call_target LVA]; \n\ndefine register offset=0x100 size=16 [ switch_ctrl ];\n\n@define CPOOL_ANEWARRAY \"0:4\"\n@define CPOOL_CHECKCAST \"1:4\"\n@define CPOOL_GETFIELD \"2:4\"\n@define CPOOL_GETSTATIC \"3:4\"\n\n#also used for ldc_w\n@define CPOOL_LDC \"4:4\" \n\n@define CPOOL_LDC2_W \"5:4\"\n@define CPOOL_INSTANCEOF \"6:4\"\n@define CPOOL_INVOKEDYNAMIC \"7:4\"\n@define CPOOL_INVOKEINTERFACE \"8:4\"\n@define CPOOL_INVOKESPECIAL \"9:4\"\n@define CPOOL_INVOKESTATIC \"10:4\"\n@define CPOOL_INVOKEVIRTUAL \"11:4\"\n@define CPOOL_MULTIANEWARRAY \"12:4\"\n@define CPOOL_NEW \"13:4\"\n@define CPOOL_NEWARRAY \"14:4\"\n@define CPOOL_PUTSTATIC \"15:4\"\n@define CPOOL_PUTFIELD \"16:4\"\n@define CPOOL_ARRAYLENGTH \"17:4\"\n\n#\n#defined ops ending in \"CallOther\" are used for pcode injection\n#\n\ndefine pcodeop getFieldCallOther;\ndefine pcodeop getStaticCallOther;\ndefine pcodeop ldcCallOther;\ndefine pcodeop ldc_wCallOther;\ndefine pcodeop ldc2_wCallOther;\ndefine pcodeop invokedynamicCallOther;\ndefine pcodeop invokeinterfaceCallOther;\ndefine pcodeop invokespecialCallOther;\ndefine pcodeop invokestaticCallOther;\ndefine pcodeop invokevirtualCallOther;\ndefine pcodeop multianewarrayCallOther;\ndefine pcodeop putStaticCallOther;\ndefine pcodeop putFieldCallOther;\n\n#\n# defined ops ending in \"Op\" are black-box instructions\n#\n\ndefine pcodeop athrowOp;\ndefine pcodeop checkcastOp;\ndefine pcodeop dremOp;\ndefine pcodeop fremOp;\ndefine pcodeop monitorenterOp;\ndefine pcodeop monitorexitOp;\ndefine pcodeop multianewarrayOp;\ndefine pcodeop multianewarrayProcessAdditionalDimensionsOp;\ndefine pcodeop throwExceptionOp;\n\n###############################################################################\n# Context\n###############################################################################\n\ndefine context switch_ctrl\n\tswitch_low \t = (0,31) noflow\n\tswitch_high \t = (32,63) noflow\n\tswitch_num \t = (64,95) noflow\n\tin_table_switch = (96,97) noflow\n\tin_lookup_switch = (98,99) noflow\n\talignmentPad = (100,101) noflow\n\tpadVal = (100,101) noflow\n;\n\n\n###############################################################################\n# TOKENS\n###############################################################################\ndefine token opcode (8)\n\top = (0,7)\n;\n\ndefine token w_opcode (16)\n w_op = (0,15)\n;\n\ndefine token data8 (8)\n\tn = (0,3)\n\tm = (4,7)\n\tatype = (0,7)\n\tbyte = (0,7)\n\tbyte1 = (0,7)\n\tbyte2 = (0,7)\n\tbyte3 = (0,7)\n\tbyte4 = (0,7)\n\tsbyte = (0,7) signed\n\tbranch = (0,7) signed\n\tbranchbyte1 = (0,7) signed\n\tbranchbyte2 = (0,7)\n\tbranchbyte3\t = (0,7)\n\tbranchbyte4 = (0,7)\n\tindex = (0,7)\n\tindexbyte1 = (0,7)\n\tindexbyte2 = (0,7)\n\tconstant = (0,7)\n\tconstantbyte1= (0,7)\n\tconstantbyte2= (0,7)\n\tnargs = (0,7)\n\tmethod = (0,7)\n\tdefaultbyte1 = (0,7)\n\tdefaultbyte2 = (0,7)\n\tdefaultbyte3 = (0,7)\n\tdefaultbyte4 = (0,7)\n\thighbyte1 = (0,7)\n\thighbyte2 = (0,7)\n\thighbyte3 = (0,7)\n\thighbyte4 = (0,7)\n\tlowbyte1 = (0,7)\n\tlowbyte2 = (0,7)\n\tlowbyte3 = (0,7)\n\tlowbyte4 = (0,7)\n\tnpairsbyte1 = (0,7)\n\tnpairsbyte2\t = (0,7)\n\tnpairsbyte3\t = (0,7)\n\tnpairsbyte4 = (0,7)\n\tdimensions\t = (0,7)\n\tblank1\t\t = (0,7)\n\tblank2\t\t = (0,7)\n\tcount\t\t = (0,7)\n\tpad\t\t\t = (0,7)\n\tpad1\t\t = (0,7)\n\tpad2\t\t = (0,7)\n\tpad3\t\t = (0,7)\n\twide_op = (0,7)\n;\n\ndefine token switch (8)\n\tmatchbyte1 = (0,7)\n\tmatchbyte2 = (0,7)\n\tmatchbyte3 = (0,7)\n\tmatchbyte4 = (0,7)\n\toffsetbyte1 = (0,7)\n\toffsetbyte2 = (0,7)\n\toffsetbyte3 = (0,7)\n\toffsetbyte4 = (0,7)\n;\n\n###############################################################################\n# Macros\n###############################################################################\nmacro push(x)\n{\n\tSP = SP - $(SIZE);\n\t*:$(SIZE) SP = x;\n}\n\nmacro pop(x)\n{\n\tx = *:$(SIZE) SP;\n\tSP = SP + $(SIZE);\n}\n\nmacro push2(x)\n{\n SP = SP - $(DOUBLE_SIZE);\n *:$(DOUBLE_SIZE) SP = x:$(DOUBLE_SIZE);\n}\n\nmacro pop2(x)\n{\n x = *:$(DOUBLE_SIZE) SP;\n SP = SP + $(DOUBLE_SIZE);\n}\n\n###############################################################################\n# Pseudo Instructions\n###############################################################################\nBranch:addr\tis branchbyte1; branchbyte2 [ addr = inst_start + (branchbyte1<<8 | branchbyte2); ]\n{\n\texport *:$(SIZE) addr;\n}\n\nBranch_w:addr\tis branchbyte1; branchbyte2; branchbyte3; branchbyte4 [ addr = inst_start + ((branchbyte1 << 24) | (branchbyte2 << 16) | (branchbyte3 << 8) | branchbyte4); ]\n{\n\texport *:$(SIZE) addr;\n}\n\nDefault:\"default\" addr is defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4 [ addr = inst_start + ((defaultbyte1<<24) | (defaultbyte2<<16) | (defaultbyte3 << 8) | defaultbyte4); ]\n{\n\texport *:$(SIZE) addr;\n}\n\n###############################################################################\n# Constructors\n###############################################################################\n:aaload \tis (in_table_switch=0 & in_lookup_switch=0 & op=0x32)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset:$(SIZE) = _arrayref + $(SIZE) * _index;\n\t_value:$(SIZE) = *[ram] _offset;\n\tpush(_value);\n}\n\n:aastore\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x53) \n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value :$(SIZE) = 0;\n\n\tpop(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset:$(SIZE) = _arrayref + $(SIZE) * _index;\n\t*[ram]:$(SIZE) _offset = _value;\n}\n\n:aconst_null\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x01) \n{\n\tpush(0:4);\n}\n\n:aload index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x19); index \n{\n\tLVA = $(SIZE) * index;\n\t_objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_objectref);\n}\n\n:aload_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x2a)\n{\n\tLVA = 0;\n\t_objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_objectref);\n}\n\n:aload_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x2b)\n{\n\tLVA = 1 * $(SIZE);\n\t_objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_objectref);\n}\n\n:aload_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x2c)\n{\n\tLVA = 2 * $(SIZE);\n\t_objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_objectref);\n}\n\n:aload_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x2d)\n{\n\tLVA = 3 * $(SIZE);\n\t_objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_objectref);\n}\n\n:anewarray index is (in_table_switch=0 & in_lookup_switch=0 & op=0xbd); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] \n{\n _count :$(SIZE) = 0;\n _arrayref :$(SIZE) = 0;\n pop(_count);\n _ref: $(SIZE) = cpool(0:4,index,$(CPOOL_ANEWARRAY));\n _arrayref = newobject(_ref,_count);\n push(_arrayref);\n}\n\n:areturn\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb0)\n{\n\tpop(return_value);\n\treturn [return_address];\n}\n\n:arraylength\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xbe)\n{\n\t_arrayref :$(SIZE) = 0;\n\t_length :$(SIZE) = 0;\n\tpop(_arrayref);\n\t_length = cpool(_arrayref, 0:4, $(CPOOL_ARRAYLENGTH));\n\tpush(_length);\n}\n\n:astore index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x3a); index\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = index*$(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:astore_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x4b)\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 0;\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:astore_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x4c)\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 1 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:astore_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x4d)\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 2 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n\t\n}\n\n:astore_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x4e)\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 3 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:athrow\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xbf)\n{\n\t_objectref :$(SIZE) = 0;\n\tpop(_objectref);\n\tathrowOp(_objectref);\n\t\n\t SP = SP;\n\t goto ;\n}\n\n:baload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x33)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value:1 = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + _index;\n\t_value = *[ram]:1 _offset;\n\t_valueSignExtended:$(SIZE) = sext(_value);\n\tpush(_valueSignExtended);\n}\n\n:bastore\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x54)\n{\n\t_value :$(SIZE) = 0;\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\tpop(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + _index;\n\t*[ram]:1 _offset = _value:1;\n}\n\n:bipush sbyte\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x10); sbyte\n{\n\t_value:$(SIZE) = sext(sbyte:1);\n\tpush(_value);\n}\n\n:caload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x34)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value:2 = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + 2 * _index;\n\t_value = *[ram]:2 _offset;\n\t_valueZeroExtended:$(SIZE) = zext(_value);\n\tpush(_valueZeroExtended);\n}\n\n:castore\tis (in_table_switch=0 & in_lookup_switch=0 & op = 0x55)\n{\n\t_value :$(SIZE) = 0;\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\tpop(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + 2 * _index;\n\t*[ram]:2 _offset = _value:2;\n}\n\n:checkcast index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xc0); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n #_object: $(SIZE) = *:$(SIZE) SP;\n #throwExceptionOp(_object);\n \n #_res:1 = cpool(_object,index,$(CPOOL_CHECKCAST));\n #throwExceptionOp(_res);\n \n \n #_ref: $(SIZE) = cpool(0:4,index,$(CPOOL_CHECKCAST));\n #checkcastOp(_object,_ref);\n \n _object:$(SIZE) = 0;\n\tpop(_object);\n _object = cpool(_object,index,$(CPOOL_CHECKCAST));\n push(_object);\n \n #_res:1 = cpool(_object,index,$(CPOOL_CHECKCAST));\n #_result:$(SIZE) = zext(_res);\n #push(_result);\n}\n\n:d2f\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x90)\n{\n\t_double :$(DOUBLE_SIZE) = 0;\n\t_float :$(SIZE) = 0;\n\tpop2(_double);\n\t_float = float2float(_double);\n\tpush(_float);\n}\n\n#this is not exactly the algorithm that the JVM uses to convert doubles to ints\n#should be good enough \n:d2i\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x8e)\n{\n\t_double :$(DOUBLE_SIZE) = 0;\n\t_int :$(DOUBLE_SIZE) = 0;\n\tpop2(_double);\n\t_int = round(_double);\n\tpush(_int:$(SIZE));\n}\n\n#this is not exactly the algorithm that the JVM uses to convert doubles to longs\n:d2l \t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x8f)\n{\n\t_double :$(DOUBLE_SIZE) = 0;\n\t_long :$(DOUBLE_SIZE) = 0;\n\tpop2(_double);\n\t_long = round(_double);\n\tpush2(_long);\n}\n\n:dadd\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x63)\n{\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 f+ _value2;\n\tpush2(_result);\n}\n\n:daload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x31)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + $(DOUBLE_SIZE) * _index;\n\t_value = *[ram]:$(DOUBLE_SIZE) _offset;\n\tpush2(_value);\n}\n\n:dastore\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x52)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_index:$(SIZE) = 0;\n\t_arrayref:$(SIZE) = 0;\n\tpop2(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + $(DOUBLE_SIZE) * _index;\n\t*[ram]:$(DOUBLE_SIZE) _offset = _value;\n}\n\n:dcmpg\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x98)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1;\n\tpush(_result);\n}\n\n:dcmpl\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x97)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1;\n\tpush(_result);\n}\n\n:dconst_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x0e)\n{\n\t_int :$(DOUBLE_SIZE) = 0;\n\t_double :$(DOUBLE_SIZE) = int2float(_int);\n\tpush2(_double);\n}\n\n:dconst_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x0f)\n{\n\t_int :$(DOUBLE_SIZE) = 1;\n\t_double :$(DOUBLE_SIZE) = int2float(_int);\n\tpush2(_double);\n}\n\n:ddiv\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x6f)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 f/ _value2;\n\tpush2(_result);\n}\n\n:dload\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x18); index\n{\n\tLVA = index*$(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\n}\n\n:dload_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x26)\n{\n LVA = 0;\n _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\t\n}\n\n:dload_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x27)\n{\n\tLVA = 1 * $(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\t\n}\n\n:dload_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x28)\n{\n\tLVA = 2 * $(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\t\n}\n\n:dload_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x29)\n{\n LVA = 3 * $(SIZE);\n _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\t\n}\n\n:dmul\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x6b)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 f* _value2;\n\tpush2(_result);\n}\n\n:dneg\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x77)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\t_result = f- _value;\n\tpush2(_result);\n}\n\n:drem\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x73)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0; \n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = dremOp(_value1, _value2);\n\tpush2(_result);\n}\n\n:dreturn\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xaf)\n{\n pop2(cat2_return_value);\n return [return_address];\n}\n\n:dstore\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x39); index\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = index*$(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:dstore_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x47)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 0;\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:dstore_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x48)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 1 * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:dstore_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x49)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 2 * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:dstore_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x4a)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 3 * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:dsub\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x67)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 f- _value2;\n\tpush2(_result);\n}\n\n:dup\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x59)\n{\n\tlocal word = *:$(SIZE) SP;\n\tpush(word);\n}\n\n:dup_x1 \tis (in_table_switch=0 & in_lookup_switch=0 & op=0x5a)\n{\n\t_value1 :$(SIZE) = 0;\n\t_value2 :$(SIZE) = 0;\n\tpop(_value1);\n\tpop(_value2);\n\tpush(_value1);\n\tpush(_value2);\n\tpush(_value1);\n}\n\n:dup_x2\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x5b)\n{\n\t_value1 :$(SIZE) = 0;\n\t_value2 :$(SIZE) = 0;\n\t_value3 :$(SIZE) = 0;\n\tpop(_value1);\n\tpop(_value2);\n\tpop(_value3);\n\tpush(_value1);\n\tpush(_value3);\n\tpush(_value2);\n\tpush(_value1);\n}\n\n:dup2\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x5c)\n{\n\t_value1 :$(SIZE) = 0;\n\t_value2 :$(SIZE) = 0;\n\tpop(_value1);\n\tpop(_value2);\n\tpush(_value2);\n\tpush(_value1);\n\tpush(_value2);\n\tpush(_value1);\n}\n\n:dup2_x1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x5d)\n{\n\t_value1 :$(SIZE) = 0;\n\t_value2 :$(SIZE) = 0;\n\t_value3 :$(SIZE) = 0;\n\tpop(_value1);\n\tpop(_value2);\n\tpop(_value3);\n\tpush(_value2);\n\tpush(_value1);\n\tpush(_value3);\n\tpush(_value2);\n\tpush(_value1);\n}\n\n:dup2_x2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x5e)\n{\n\t_value1 :$(SIZE) = 0;\n\t_value2 :$(SIZE) = 0;\n\t_value3 :$(SIZE) = 0;\n\t_value4 :$(SIZE) = 0;\n\tpop(_value1);\n\tpop(_value2);\n\tpop(_value3);\n\tpop(_value4);\n\tpush(_value2);\n\tpush(_value1);\n\tpush(_value4);\n\tpush(_value3);\n\tpush(_value2);\n\tpush(_value1);\n}\n\n:f2d\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x8d)\n{\n\t_value :$(SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop(_value);\n\t_result = float2float(_value);\n\tpush2(_result);\n}\n\n#not exactly how the JVM converts floats to ints but close enough\n:f2i\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x8b)\n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\t_result = round(_value);\n\tpush(_result);\n}\n\n#not exactly how the JVM converts floats to longs\n:f2l\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x8c)\n{\n\t_value :$(SIZE) = 0;\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop(_value);\n\t_value2 = float2float(_value);\n\t_result = round(_value2);\n\tpush2(_result);\n}\n\n:fadd\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x62)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 f+ _value2;\n\tpush(_result);\n}\n\n:faload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x30)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value :$(SIZE) = 0;\n\tpop(_index);\n\tpop(_arrayref);\t\n\tlocal _offset = _arrayref + ($(SIZE) * _index);\n\t_value = *[ram] (_offset);\n\tpush(_value);\n}\n\n:fastore\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x51)\n{\n\t_value :$(SIZE) = 0;\n\t_index:$(SIZE) = 0;\n\t_arrayref:$(SIZE) = 0;\n\tpop(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\tlocal _offset = _arrayref + ($(SIZE) * _index);\n\t*[ram] _offset = _value;\n}\n\n:fcmpg\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x96)\n{\n _value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1;\n\tpush(_result);\n}\n\n:fcmpl\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x95)\n{\n _value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1;\n\tpush(_result);\n}\n\n:fconst_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x0b)\n{\n\tf :$(SIZE) = 0;\n\tfAsFloat:$(SIZE) = int2float(f);\n\tpush(fAsFloat);\n}\n\n:fconst_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x0c)\n{\n\tf :$(SIZE) = 1;\n\tfAsFloat:$(SIZE) = int2float(f);\n\tpush(fAsFloat);\n}\n\n:fconst_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x0d)\n{\n\tf :$(SIZE) = 2;\n\tfAsFloat:$(SIZE) = int2float(f);\n\tpush(fAsFloat);\n}\n\n:fdiv\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x6e)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 f/ _value2;\n\tpush(_result);\n}\n\n:fload\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x17); index\n{\n\tLVA = $(SIZE) * index;\n\t _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush(_value);\t\n}\n\n:fload_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x22)\n{\n\tLVA = 0;\n\t _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush(_value);\t\n}\n\n:fload_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x23)\n{\n\tLVA = 1 * $(SIZE);\n\t _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush(_value);\t\n}\n\n:fload_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x24)\n{\n\tLVA = 2 * $(SIZE);\n\t _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush(_value);\t\n}\n\n:fload_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x25)\n{\n\tLVA = 3 * $(SIZE);\n\t _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush(_value);\t\n}\n\n:fmul\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x6a)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 f* _value2;\n\tpush(_result);\n}\n\n:fneg\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x76)\n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\t_result = f- _value;\n\tpush(_result);\n}\n\n:frem\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x72)\n{\n\t_value2 :$(SIZE) = 0; \n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = fremOp(_value1, _value2);\n\tpush(_result);\n}\n\n:freturn\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xae)\n{\n pop(return_value);\n return [return_address];\n}\n\n:fstore\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x38); index\n{\n\t _value :$(SIZE) = 0;\n pop(_value);\n LVA = index*$(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:fstore_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x43)\n{\n\t_value :$(SIZE) = 0;\n pop(_value);\n LVA = 0;\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:fstore_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x44)\n{\n\t_value :$(SIZE) = 0;\n pop(_value);\n LVA = 1 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n:fstore_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x45)\n{\n\t_value :$(SIZE) = 0;\n pop(_value);\n LVA = 2 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n:fstore_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x46)\n{\n\t_value :$(SIZE) = 0;\n pop(_value);\n LVA = 3 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:fsub\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x66)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 f- _value2;\n\tpush(_result);\n}\n\n:getfield\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb4 ); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] \n{ \n getFieldCallOther(index:2);\n}\n\n\n:getstatic \tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb2); indexbyte1; indexbyte2 [index = indexbyte1 << 8 | indexbyte2;]\n{\n\tgetStaticCallOther(index:2);\n}\n\n:goto Branch\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa7); Branch \n{\n\tgoto Branch;\n}\n\n:goto_w Branch_w\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xc8); Branch_w \n{ \n\tgoto Branch_w;\n}\n\n:i2b\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x91) \n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\tlocal _byte = _value:1;\n\t_result = sext(_byte);\n\tpush(_result); \n}\n\n:i2c\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x92) \n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\tlocal _char = _value:2;\n\t_result = zext(_char);\n\tpush(_result); \n}\n\n:i2d\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x87) \n{\n\t_value :$(SIZE) = 0;\n\t_resultAsLong :$(DOUBLE_SIZE) = 0;\n\t_resultAsDouble :$(DOUBLE_SIZE) = 0;\n\tpop(_value);\n\t_resultAsLong = sext(_value);\n\t_resultAsDouble = int2float(_resultAsLong);\n\tpush2(_resultAsDouble); \n}\n\n:i2f\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x86) \n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\t_result = int2float(_value);\n\tpush(_result); \n}\n\n:i2l\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x85) \n{\n\t_value :$(SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop(_value);\n\t_result = sext(_value);\n\tpush2(_result); \n}\n\n:i2s\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x93) \n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\tlocal _short = _value:2;\n\t_result = sext(_short);\n\tpush(_result); \n}\n\n:iadd\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x60)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 + _value2;\n\tpush(_result);\n}\n\n:iaload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x2e) \n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value :$(SIZE) = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\tlocal _offset = _arrayref + ($(SIZE) * _index);\n\t_value = *[ram] (_offset);\n\tpush(_value);\n}\n\n:iand\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x7e)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 & _value2;\n\tpush(_result);\n}\n\n:iastore\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x4f)\n{\n\t_value :$(SIZE) = 0;\n\t_index:$(SIZE) = 0;\n\t_arrayref:$(SIZE) = 0;\n\tpop(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\tlocal _offset = _arrayref + ($(SIZE) * _index);\n\t*[ram] _offset = _value;\n}\n\n:iconst_m1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x02) \n{ \n\t_i :$(SIZE) = -1;\n\tpush(_i); \n}\n\n:iconst_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x03) \n{ \n\t_i :$(SIZE) = 0;\n\tpush(_i); \n}\n\n:iconst_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x04)\n{ \n\t_i :$(SIZE) = 1;\n\tpush(_i); \n}\n\n:iconst_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x05)\n{ \n\t_i :$(SIZE) = 2;\n\tpush(_i); \n}\n\n:iconst_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x06)\n{ \n\t_i :$(SIZE) = 3;\n\tpush(_i); \n}\n\n:iconst_4\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x07)\n{ \n\t_i :$(SIZE) = 4;\n\tpush(_i); \n}\n\n:iconst_5\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x08)\n{ \n\t_i :$(SIZE) = 5;\n\tpush(_i); \n}\n\n:idiv\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x6c)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 s/ _value2;\n\tpush(_result);\n}\n\n:if_acmpeq Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa5); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 == _value2 ) goto Branch;\n}\n\n:if_acmpne Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa6); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 != _value2 ) goto Branch;\n}\n\n:if_icmpeq Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x9f); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 == _value2 ) goto Branch;\n}\n\n:if_icmpne Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa0); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 != _value2 ) goto Branch;\n}\n\n:if_icmplt Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa1); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 s< _value2 ) goto Branch;\n}\n\n:if_icmpge Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa2); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 s>= _value2 ) goto Branch;\n}\n\n:if_icmpgt Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa3); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 s> _value2 ) goto Branch;\n}\n\n:if_icmple Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa4); Branch\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\tpop(_value2); \n\tpop(_value1);\n\tif( _value1 s<= _value2 ) goto Branch;\n}\n\n:ifeq Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x99); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif( _value == 0 ) goto Branch;\n}\n\n:ifne Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x9a); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif( _value != 0 ) goto Branch;\n}\n\n:iflt Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x9b); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif( _value s< 0 ) goto Branch;\n}\n\n:ifge Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x9c); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif( _value s>= 0 ) goto Branch;\n}\n\n:ifgt Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x9d); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif( _value s> 0 ) goto Branch;\n}\n\n:ifle Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x9e); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif( _value s<= 0 ) goto Branch;\n}\n\n:ifnonnull Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xc7); Branch\n{\n _value :$(SIZE) = 0;\n\tpop(_value);\n\tif ( _value != 0) goto Branch;\n}\n\n:ifnull Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xc6); Branch\n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tif ( _value == 0) goto Branch;\n}\n\n:iinc index, constant\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x84); index; constant \n{\n\t_const :$(SIZE) = 0;\n\tLVA = index*$(SIZE);\n\t_const = sext(constant:1);\n\t*[localVariableArray]:$(SIZE) (LVA) = (*[localVariableArray]:$(SIZE) (LVA)) + _const;\n}\n\n:iload index\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x15); index \n{\n\tLVA = index*$(SIZE);\n\t_value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_value);\n}\n\n:iload_0\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x1a) \n{\n LVA = 0;\n\t_value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_value);\n}\n\n:iload_1\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x1b) \n{\n LVA = 1 * $(SIZE);\n\t_value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_value);\n}\n\n:iload_2\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x1c) \n{\tLVA = 2 * $(SIZE);\n _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_value);\n}\n\n:iload_3\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x1d) \n{\n\tLVA = 3 * $(SIZE);\n\t_value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n\tpush(_value);\n}\n\n:imul\t\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x68) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 * _value2;\n\tpush(_result);\n}\n\n:ineg\t\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x74) \n{\n\t_value :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop(_value);\n\t_result = -_value;\n\tpush(_result); \n}\n\n:instanceof index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xc1); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] \n{\n\t_object:$(SIZE) = 0;\n\tpop(_object);\n _res:1 = cpool(_object,index,$(CPOOL_INSTANCEOF));\n _result:$(SIZE) = zext(_res);\n push(_result);\n}\n\n\n:invokedynamic index, blank1, blank2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xba); indexbyte1; indexbyte2; blank1; blank2 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n invokedynamicCallOther(index:2);\t\n}\n\n:invokeinterface index, count, blank1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb9); indexbyte1; indexbyte2; count; blank1 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n invokeinterfaceCallOther(index:2);\n}\n\n:invokespecial index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb7); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n\tinvokespecialCallOther(index:2);\n}\n\n:invokestatic index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb8); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n\tinvokestaticCallOther(index:2);\t\n}\n\n:invokevirtual index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb6); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n invokevirtualCallOther(index:2);\n\n}\n\n:ior\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x80) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 | _value2;\n\tpush(_result); \n}\n\n:irem\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x70) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 s% _value2;\n\tpush(_result);\n}\n\n:ireturn\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xac) \n{\n pop(return_value);\n return [return_address];\n}\n\n:ishl\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x78) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 << (_value2 & 0x1f);\n\tpush(_result);\n}\n\n:ishr\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x7a) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 s>> (_value2 & 0x1f);\n\tpush(_result);\n}\n\n:istore index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x36); index \n{\n _value :$(SIZE) = 0;\n pop(_value);\n LVA = index*$(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:istore_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x3b) \n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 0;\n\t*[localVariableArray]:$(SIZE) (LVA) =_value;\n}\n\n:istore_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x3c) \n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 1 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) =_value;\n}\n\n:istore_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x3d) \n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 2 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) =_value;\n}\n\n:istore_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x3e) \n{\n\t_value :$(SIZE) = 0;\n\tpop(_value);\n\tLVA = 3 * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) =_value;\n}\n\n:isub\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x64) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 - _value2;\n\tpush(_result);\n}\n\n:iushr\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x7c) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 >> (_value2 & 0x1f);\n\tpush(_result);\n}\n\n:ixor\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x82) \n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\t\n\tpop(_value2);\n\tpop(_value1);\n\t_result = _value1 ^ _value2;\n\tpush(_result); \n}\n\n:jsr Branch\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa8); Branch\n{\n\tretAddr :$(SIZE) = inst_next;\n\tpush(retAddr);\n\tgoto Branch;\n}\n\n:jsr_w Branch_w is (in_table_switch=0 & in_lookup_switch=0 & op=0xc9); Branch_w\n{\n\tretAddr :$(SIZE) = inst_next;\n\tpush(retAddr);\n\tgoto Branch_w;\n}\n\n:l2d\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x8a)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\t_result = int2float(_value);\n\tpush2(_result);\n}\n\n:l2f\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x89)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop2(_value);\n\t_result = int2float(_value);\n\tpush(_result);\n}\n\n:l2i \t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x88)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop2(_value);\n\t_result = _value:$(SIZE);\n\tpush(_result);\n}\n\n:ladd\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x61)\n{\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 + _value2;\n\tpush2(_result);\n}\n\n:laload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x2f)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\tlocal _offset = _arrayref + ($(DOUBLE_SIZE) * _index);\n\t_value = *[ram]:$(DOUBLE_SIZE) (_offset);\n\tpush2(_value);\n\t\n}\n\n:land\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x7f)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 & _value2;\n\tpush2(_result);\n}\n\n:lastore\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x50)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_index:$(SIZE) = 0;\n\t_arrayref:$(SIZE) = 0;\n\tpop2(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\tlocal _offset = _arrayref + ($(DOUBLE_SIZE) * _index);\n\t*[ram]:$(DOUBLE_SIZE) _offset = _value;\n\t\n}\n\n:lcmp\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x94)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = zext(_value1 s> _value2) + zext(_value1 s>= _value2) - 1;\n\tpush(_result);\n}\n\n:lconst_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x09)\n{\n\t_l :$(DOUBLE_SIZE) = 0;\n\tpush2(_l);\n}\n\n:lconst_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x0a)\n{\n\t_l :$(DOUBLE_SIZE) = 1;\n\tpush2(_l);\n}\n\n:ldc\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x12); index\n{\n\tldcCallOther(index:1);\n}\n\n:ldc_w\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x13); indexbyte1; indexbyte2 [ index = indexbyte1 << 8 | indexbyte2; ]\n{\n\tldc_wCallOther(index:2);\n}\n\n:ldc2_w\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x14); indexbyte1; indexbyte2 [ index = indexbyte1 << 8 | indexbyte2; ]\n{\n\tldc2_wCallOther(index:2);\n}\n\n:ldiv\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x6d)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 s/ _value2;\n\tpush2(_result);\n}\n\n:lload\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x16); index\n{\n\tLVA = index * $(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\n}\n\n:lload_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x1e)\n{\n\tLVA = 0;\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\n}\n\n:lload_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x1f)\n{\n\tLVA = 1 * $(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\n}\n\n:lload_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x20)\n{\n\tLVA = 2 * $(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\n}\n\n:lload_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x21)\n{\n\tLVA = 3 * $(SIZE);\n\t_value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n\tpush2(_value);\n}\n\n:lmul\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x69)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 * _value2; \n\tpush2(_result);\n}\n\n:lneg\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x75)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\t_result= -_value;\n\tpush2(_result);\n}\n\n##################################################################################################\n# lookupswitch\n##################################################################################################\n\n#compute and display one match,offset pair\nLookupSwitch_match:match _offset is matchbyte1; matchbyte2; matchbyte3; matchbyte4; offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [match = (matchbyte1 << 24) | (matchbyte2 << 16) | (matchbyte3 << 8) | (matchbyte4); _offset = inst_start + ((offsetbyte1 << 24) | (offsetbyte2 << 16) | (offsetbyte3 << 8) | (offsetbyte4)); ]\n{\n}\n\n#consume one match,offset pair and decrement the switch number\n:^LookupSwitch_match, instruction is (in_lookup_switch=1 & in_table_switch=0); LookupSwitch_match; instruction [switch_num = switch_num - 1;]\n{\n}\n\n#leave the switch statement\n:\"\"LookupSwitch_match is (in_lookup_switch=1 & switch_num=1 & in_table_switch=0); LookupSwitch_match [in_lookup_switch=0;]\n{\n}\n\ndefine pcodeop switchAssist;\n\npadSwitch: \"\" is alignmentPad = 3 & padVal & op ; pad1; pad2; pad3\t{ export *[const]:1 padVal; }\npadSwitch: \"\" is alignmentPad = 2 & padVal & op ; pad1; pad2\t\t{ export *[const]:1 padVal; }\npadSwitch: \"\" is alignmentPad = 1 & padVal & op ; pad1\t\t\t\t{ export *[const]:1 padVal; }\npadSwitch: \"\" is alignmentPad = 0 & padVal & op\t\t\t\t\t { export *[const]:1 padVal; }\n\n#Note: \"Default\" constructor does not play nice with switchAssist injection...\ndolookupswitch: _default, npairs is alignmentPad & defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4; npairsbyte1; npairsbyte2; npairsbyte3; npairsbyte4 [ npairs = (npairsbyte1 << 24) | (npairsbyte2 << 16) | (npairsbyte3 << 8) | npairsbyte4; _default = inst_start + ((defaultbyte1 << 24) | (defaultbyte2 << 16) | (defaultbyte3 << 8) | defaultbyte4); switch_num = npairs; in_lookup_switch = 1;]\n{\n local _padding:1 = alignmentPad;\n local _opcodeAddr:$(SIZE) = inst_start;\n local _key:$(SIZE) = 0;\n pop(_key);\n local _address:$(SIZE) = switchAssist(_key,_opcodeAddr,_padding,_default:$(SIZE),npairs:$(SIZE));\n goto [ _address ];\n}\n\n:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 0 ; dolookupswitch; instruction \n{\n\tbuild dolookupswitch;\n}\n:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 1 ; pad1; dolookupswitch; instruction \n{\n\tbuild dolookupswitch;\n}\n:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 2 ; pad1; pad2; dolookupswitch; instruction \n{\n\tbuild dolookupswitch;\n}\n:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 3 ; pad1; pad2; pad3; dolookupswitch; instruction \n{\n\tbuild dolookupswitch;\n}\n\n\n:lor\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x81)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 | _value2;\n\tpush2(_result);\n}\n\n:lrem\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x71)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0; \n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 s% _value2;\n\tpush2(_result);\n}\n\n:lreturn\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xad)\n{\n\tpop2(cat2_return_value);\n return [return_address];\n}\n\n:lshl\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x79)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop(_value2);\n\tpop2(_value1);\n\t_result = _value1 << (_value2 & 0x3f);\n\tpush2(_result);\n}\n\n:lshr\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x7b)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop(_value2);\n\tpop2(_value1);\n\t_result = _value1 s>> (_value2 & 0x3f);\n\tpush2(_result);\n}\n\n:lstore\tindex\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x37); index\n{\n\t _value :$(DOUBLE_SIZE) = 0;\n pop2(_value);\n LVA = index * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:lstore_0\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x3f)\n{\n\t_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 0;\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value;\n}\n\n:lstore_1\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x40)\n{\n_value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 1 * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value;\t\n}\n\n:lstore_2\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x41)\n{\n _value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 2 * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value;\n}\n\n:lstore_3\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x42)\n{\n _value :$(DOUBLE_SIZE) = 0;\n\tpop2(_value);\n\tLVA = 3 * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value;\n}\n\n:lsub\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x65)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 - _value2;\n\tpush2(_result);\n}\n\n:lushr\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x7d)\n{\n\t_value2 :$(SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop(_value2);\n\tpop2(_value1);\n\t_result = _value1 >> (_value2 & 0x3f);\n\tpush2(_result);\n}\n\n:lxor\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x83)\n{\n\t_value2 :$(DOUBLE_SIZE) = 0;\n\t_value1 :$(DOUBLE_SIZE) = 0;\n\t_result :$(DOUBLE_SIZE) = 0;\n\tpop2(_value2);\n\tpop2(_value1);\n\t_result = _value1 ^ _value2;\n\tpush2(_result);\n}\n\n:monitorenter\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xc2)\n{\n\t_objectref :$(SIZE) = 0;\n\tpop(_objectref);\n\tmonitorenterOp(_objectref);\n}\n\n:monitorexit\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xc3)\n{\n\t_objectref :$(SIZE) = 0;\n\tpop(_objectref);\n\tmonitorexitOp(_objectref);\n}\n\n:multianewarray index is (in_table_switch=0 & in_lookup_switch=0 & op=0xc5); indexbyte1; indexbyte2; dimensions [index = indexbyte1<<8 | indexbyte2;]\n{\n multianewarrayCallOther(index:2,dimensions:1);\n}\n\n:new index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xbb); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ]\n{\n local _className = cpool(0:4,index,$(CPOOL_NEW));\n _ref: $(SIZE) = newobject(_className);\n push(_ref);\t\n}\n\n:newarray atype\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xbc); atype \n{\n\t_count:$(SIZE)=0;\n\t_arrayref:$(SIZE)=0;\n\tpop(_count);\n\t_ref:$(SIZE) = cpool(0:4,atype:1,$(CPOOL_NEWARRAY));\n\t_arrayref = newobject(_ref, _count);\n\tpush(_arrayref);\n}\n\n:nop\t\tis (in_table_switch=0 & in_lookup_switch=0 & in_lookup_switch=0 & op=0x00) \n{\n}\n\n:pop\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x57) \n{ \n\tSP = SP + $(SIZE);\n}\n\n:pop2\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x58) \n{\n\tSP = SP + $(DOUBLE_SIZE);\n}\n\n:putfield index \tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb5); indexbyte1; indexbyte2 [ index = indexbyte1 << 8 | indexbyte2; ] \n{ \n putFieldCallOther(index:2);\n}\n\n:putstatic index\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb3); indexbyte1; indexbyte2 [index = indexbyte1 << 8 | indexbyte2; ]\n{\n\tputStaticCallOther(index:2);\n}\n\n:ret index\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xa9); index \n{\n LVA = index * $(SIZE);\n _value:$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n goto [_value];\n}\n\n:return\t\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0xb1)\n{\n\treturn [return_address];\n}\n\n:saload\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x35)\n{\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\t_value:2 = 0;\n\tpop(_index);\n\tpop(_arrayref);\n\t_offset: $(SIZE) = _arrayref + _index * 2;\n\t_value = *[ram]:2 _offset;\n\t_valueSignExtended:$(SIZE) = sext(_value);\n\tpush(_valueSignExtended);\n}\n\n:sastore\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x56) \n{ \n _value :$(SIZE) = 0;\n\t_index :$(SIZE) = 0;\n\t_arrayref :$(SIZE) = 0;\n\tpop(_value);\n\tpop(_index);\n\tpop(_arrayref);\n\tlocal _offset = _arrayref + _index * 2;\n\t*[ram]:$(SIZE) _offset = _value:2;\n}\n\n:sipush short\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x11); byte1; byte2 [ short = byte1<<8 | byte2; ] \n{\n\t_result:$(SIZE) = sext(short:2);\n\tpush(_result);\n}\n\n:swap\t\t\tis (in_table_switch=0 & in_lookup_switch=0 & op=0x5f)\n{\n\t_value1 :$(SIZE) = 0;\n\t_value2 :$(SIZE) = 0;\n\tpop(_value1);\n\tpop(_value2);\n\tpush(_value1);\n\tpush(_value2);\n}\n\n########################################################################################################################\n# tableswitch\n########################################################################################################################\n\n#compute and display one switch offset\nSwitch_offset:_offset is offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [ _offset = inst_start + ((offsetbyte1<<24) | (offsetbyte2<<16) | (offsetbyte3<<8) | offsetbyte4); ]\n{\n}\n\n# Switch entry that's not the last one.\n# no pcode def - this construction is just for consuming all of the bytes of a tableswitch instructions\n# decrements the switch number\n:^Switch_offset, instruction is (in_table_switch=1 & in_lookup_switch=0); Switch_offset; instruction [switch_num = switch_num - 1;]\n{\n}\n\n#Last switch entry. Get out of switch context.\n:\"\"Switch_offset is (in_table_switch=1 & in_lookup_switch=0 &switch_num=0); Switch_offset [ in_table_switch=0; ]\n{\n}\n\ndotableswitch: Default, low, high is alignmentPad & Default;lowbyte1; lowbyte2; lowbyte3; lowbyte4; highbyte1; highbyte2; highbyte3; highbyte4 [ low = (lowbyte1 << 24) | (lowbyte2 << 16) | (lowbyte3 << 8) | lowbyte4; high = (highbyte1 << 24) | (highbyte2 << 16) | (highbyte3 << 8) | highbyte4; switch_low = low; switch_num = high - low; switch_high = high; in_table_switch = 1; ]\n\n{\n\tlocal _offset :$(SIZE) = 0;\n local idx :$(SIZE) = 0;\n local padding:$(SIZE) = alignmentPad;\n \n pop(idx);\n if (idx s< low) goto Default;\n if (idx s> high) goto Default;\n #opcode_address + byte_for_opcode + padding + default + low + high = start of table\n _offset = inst_start + 1 + padding + 4 + 4 + 4 + 4*(idx-low);\n switch_target = inst_start + *:$(SIZE)(_offset);\n goto [switch_target];\n}\n\n:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=0; dotableswitch; instruction \n{\n\tbuild dotableswitch;\n}\n:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=1; pad1; dotableswitch; instruction \n{\n\tbuild dotableswitch;\n}\n:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=2; pad1; pad2; dotableswitch; instruction \n{\n\tbuild dotableswitch;\n}\n:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=3; pad1; pad2; pad3; dotableswitch; instruction \n{\n\tbuild dotableswitch;\n}\n\n#wide loads \n:wide_iload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc415); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ]\n{\n LVA = index * $(SIZE);\n _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n push(_value);\n}\n\n:wide_fload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc417); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ]\n{\n LVA = index * $(SIZE);\n _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n push(_value);\n}\n\n:wide_aload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc419); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ]\n{\n LVA = index * $(SIZE);\n _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n push(_value);\n}\n\n:wide_lload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc416); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ]\n{\n LVA = index * $(SIZE);\n _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n push2(_value);\n}\n\n:wide_dload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc418); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ]\n{\n LVA = index * $(SIZE);\n _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA);\n push2(_value);\n}\n\n\n#wide stores\n:wide_istore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc436); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;]\n{\n _value :$(SIZE) = 0;\n pop(_value);\n LVA = index * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:wide_fstore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc438); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;]\n{\n _value :$(SIZE) = 0;\n pop(_value);\n LVA = index * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:wide_astore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc43a); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;]\n{\n _value :$(SIZE) = 0;\n pop(_value);\n LVA = index * $(SIZE);\n\t*[localVariableArray]:$(SIZE) (LVA) = _value;\n}\n\n:wide_lstore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc437); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;]\n{\n _value :$(DOUBLE_SIZE) = 0;\n pop2(_value);\n LVA = index * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n:wide_dstore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc439); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;]\n{\n _value :$(DOUBLE_SIZE) = 0;\n pop2(_value);\n LVA = index * $(SIZE);\n\t*[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value;\n}\n\n#wide ret\n:wide_ret index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc4a9); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;]\n{\n LVA = index * $(SIZE);\n _value:$(SIZE) = *[localVariableArray]:$(SIZE) (LVA);\n goto [_value];\n}\n\n#wide inc - instruction is called wide format 2 by JVM specification but iinc_w by javap\n:iinc_w index, constant is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc484); indexbyte1; indexbyte2; constantbyte1; constantbyte2 [ index = (indexbyte1 << 8) | indexbyte2; constant = (constantbyte1 << 8) | constantbyte2;]\n{\n fullIndex: $(SIZE) = 4*zext(index:2);\n fullConstant: $(SIZE) = sext(constant:2);\n intVal:$(SIZE) = *[localVariableArray]:$(SIZE) (fullIndex);\n *[localVariableArray]:$(SIZE) (fullIndex) = (intVal + fullConstant); \n}\n" }, { "path": "pypcode/processors/JVM/data/manuals/JVM.idx", "content": "@jvms8.pdf [The Java Virtual Machine Specification - Jave SE 8 Edition]\naaload, 381\naastore, 382\naconst_null, 384\naload, 385\naload_0, 386\naload_1, 386\naload_2, 386\naload_3, 386\nanewarray, 387\nareturn, 388\narraylength, 389\nastore, 390\nastore_0, 391\nastore_1, 391\nastore_2, 391\nastore_3, 391\nathrow, 392\nbaload, 394\nbastore, 395\nbipush, 396\ncaload, 397\ncastore, 398\ncheckcast, 399\nd2f, 401\nd2i, 402\nd2l, 403\ndadd, 404\ndaload, 406\ndastore, 407\ndcmpg, 408\ndcmpl, 408\ndconst_0, 410\ndconst_1, 410\nddiv, 411\ndload, 413\ndload_0, 414\ndload_1, 414\ndload_2, 414\ndload_3, 414\ndmul, 415\ndneg, 417\ndrem, 418\ndreturn, 420\ndstore, 421\ndstore_0, 422\ndstore_1, 422\ndstore_2, 422\ndstore_3, 422\ndsub, 423\ndup, 424\ndup_x1, 425\ndup_x2, 426\ndup2, 427\ndup2_x1, 428\ndup2_x2, 429\nf2d, 431\nf2i, 432\nf2l, 433\nfadd, 434\nfaload, 436\nfastore, 437\nfcmpg, 438\nfcmpl, 438\nfconst_0, 440\nfconst_1, 440\nfconst_2, 440\nfdiv, 441\nfload, 443\nfload_0, 444\nfload_1, 444\nfload_2, 444\nfload_3, 444\nfmul, 445\nfneg, 447\nfrem, 448\nfreturn, 450\nfstore, 451\nfstore_0, 452\nfstore_1, 452\nfstore_2, 452\nfstore_3, 452\nfsub, 453\ngetfield, 454\ngetstatic, 456\ngoto, 458\ngoto_w, 459\ni2b, 460\ni2c, 461\ni2d, 462\ni2f, 463\ni2l, 464\ni2s, 465\niadd, 466\niaload, 467\niand, 468\niastore, 469\niconst_m1, 470\niconst_0, 470\niconst_1, 470\niconst_2, 470\niconst_3, 470\niconst_4, 470\niconst_5, 470\nidiv, 471\nif_acmpeq, 472\nif_acmpne, 472\nif_icmpeq, 473\nif_icmpne, 473\nif_icmplt, 473\nif_icmple, 473\nif_icmpgt, 473\nif_icmpge, 473\nifeq, 475\nifne, 475\niflt, 475\nifge, 475\nifgt, 475\nifle, 475\nifnonnull, 477\nifnull, 478\niinc, 479\niload, 480\niload_0, 481\niload_1, 481\niload_2, 481\niload_3, 481\nimul, 482\nineg, 483\ninstanceof, 484\ninvokedynamic, 486\ninvokeinterface, 491\ninvokespecial, 495\ninvokestatic, 500\ninvokevirtual, 503\nior, 508\nirem, 509\nireturn, 510\nishl, 511\nishr, 512\nistore, 513\nistore_0, 514\nistore_1, 514\nistore_2, 514\nistore_3, 514\nisub, 515\niushr, 516\nixor, 517\njsr, 518\njsr_w, 519\nl2d, 520\nl2f, 521\nl2i, 522\nladd, 523\nlaload, 524\nland, 525\nlastore, 526\nlcmp, 527\nlconst_0, 528\nlconst_1, 528\nldc, 529\nldc_w, 531\nldc2_w, 533\nldiv, 534\nlload, 535\nlload_0, 536\nlload_1, 536\nlload_2, 536\nlload_3, 536\nlmul, 537\nlneg, 538\nlookupswitch, 539\nlor, 541\nlrem, 542\nlreturn, 543\nlshl, 544\nlshr, 545\nlstore, 546\nlstore_0, 547\nlstore_1, 547\nlstore_2, 547\nlstore_3, 547\nlsub, 548\nlushr, 549\nlxor, 550\nmonitorenter, 551\nmonitorexit, 553\nmultianewarray, 555\nnew, 557\nnewarray, 559\nnop, 561\npop, 562\npop2, 563\nputfield, 564\nputstatic, 566\nret, 568\nreturn, 569\nsaload, 570\nsastore, 571\nsipush, 572\nswap, 573\ntableswitch, 574\nwide, 576\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/ilp32d.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/ilp32f.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n\t\t\n \n \n\t\t\n \n \n\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/lasx.sinc", "content": "define pcodeop xvfmadd.s;\n\n#lasx.txt xvfmadd.s mask=0x0a100000\t\n#0x0a100000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfmadd.s xrD, xrJ, xrK, xrA is op20_31=0xa1 & xrD & xrJ & xrK & xrA {\n\txrD = xvfmadd.s(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfmadd.d;\n\n#lasx.txt xvfmadd.d mask=0x0a200000\t\n#0x0a200000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfmadd.d xrD, xrJ, xrK, xrA is op20_31=0xa2 & xrD & xrJ & xrK & xrA {\n\txrD = xvfmadd.d(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfmsub.s;\n\n#lasx.txt xvfmsub.s mask=0x0a500000\t\n#0x0a500000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfmsub.s xrD, xrJ, xrK, xrA is op20_31=0xa5 & xrD & xrJ & xrK & xrA {\n\txrD = xvfmsub.s(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfmsub.d;\n\n#lasx.txt xvfmsub.d mask=0x0a600000\t\n#0x0a600000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfmsub.d xrD, xrJ, xrK, xrA is op20_31=0xa6 & xrD & xrJ & xrK & xrA {\n\txrD = xvfmsub.d(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfnmadd.s;\n\n#lasx.txt xvfnmadd.s mask=0x0a900000\t\n#0x0a900000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfnmadd.s xrD, xrJ, xrK, xrA is op20_31=0xa9 & xrD & xrJ & xrK & xrA {\n\txrD = xvfnmadd.s(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfnmadd.d;\n\n#lasx.txt xvfnmadd.d mask=0x0aa00000\t\n#0x0aa00000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfnmadd.d xrD, xrJ, xrK, xrA is op20_31=0xaa & xrD & xrJ & xrK & xrA {\n\txrD = xvfnmadd.d(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfnmsub.s;\n\n#lasx.txt xvfnmsub.s mask=0x0ad00000\t\n#0x0ad00000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfnmsub.s xrD, xrJ, xrK, xrA is op20_31=0xad & xrD & xrJ & xrK & xrA {\n\txrD = xvfnmsub.s(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfnmsub.d;\n\n#lasx.txt xvfnmsub.d mask=0x0ae00000\t\n#0x0ae00000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvfnmsub.d xrD, xrJ, xrK, xrA is op20_31=0xae & xrD & xrJ & xrK & xrA {\n\txrD = xvfnmsub.d(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvfcmp.caf.s;\n\n#lasx.txt xvfcmp.caf.s mask=0x0c900000\t\n#0x0c900000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.caf.s xrD, xrJ, xrK is op15_31=0x1920 & xrD & xrJ & xrK {\n\txrD = xvfcmp.caf.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.saf.s;\n\n#lasx.txt xvfcmp.saf.s mask=0x0c908000\t\n#0x0c908000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.saf.s xrD, xrJ, xrK is op15_31=0x1921 & xrD & xrJ & xrK {\n\txrD = xvfcmp.saf.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.clt.s;\n\n#lasx.txt xvfcmp.clt.s mask=0x0c910000\t\n#0x0c910000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.clt.s xrD, xrJ, xrK is op15_31=0x1922 & xrD & xrJ & xrK {\n\txrD = xvfcmp.clt.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.slt.s;\n\n#lasx.txt xvfcmp.slt.s mask=0x0c918000\t\n#0x0c918000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.slt.s xrD, xrJ, xrK is op15_31=0x1923 & xrD & xrJ & xrK {\n\txrD = xvfcmp.slt.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.ceq.s;\n\n#lasx.txt xvfcmp.ceq.s mask=0x0c920000\t\n#0x0c920000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.ceq.s xrD, xrJ, xrK is op15_31=0x1924 & xrD & xrJ & xrK {\n\txrD = xvfcmp.ceq.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.seq.s;\n\n#lasx.txt xvfcmp.seq.s mask=0x0c928000\t\n#0x0c928000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.seq.s xrD, xrJ, xrK is op15_31=0x1925 & xrD & xrJ & xrK {\n\txrD = xvfcmp.seq.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cle.s;\n\n#lasx.txt xvfcmp.cle.s mask=0x0c930000\t\n#0x0c930000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cle.s xrD, xrJ, xrK is op15_31=0x1926 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cle.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sle.s;\n\n#lasx.txt xvfcmp.sle.s mask=0x0c938000\t\n#0x0c938000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sle.s xrD, xrJ, xrK is op15_31=0x1927 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sle.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cun.s;\n\n#lasx.txt xvfcmp.cun.s mask=0x0c940000\t\n#0x0c940000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cun.s xrD, xrJ, xrK is op15_31=0x1928 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cun.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sun.s;\n\n#lasx.txt xvfcmp.sun.s mask=0x0c948000\t\n#0x0c948000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sun.s xrD, xrJ, xrK is op15_31=0x1929 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sun.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cult.s;\n\n#lasx.txt xvfcmp.cult.s mask=0x0c950000\t\n#0x0c950000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cult.s xrD, xrJ, xrK is op15_31=0x192a & xrD & xrJ & xrK {\n\txrD = xvfcmp.cult.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sult.s;\n\n#lasx.txt xvfcmp.sult.s mask=0x0c958000\t\n#0x0c958000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sult.s xrD, xrJ, xrK is op15_31=0x192b & xrD & xrJ & xrK {\n\txrD = xvfcmp.sult.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cueq.s;\n\n#lasx.txt xvfcmp.cueq.s mask=0x0c960000\t\n#0x0c960000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cueq.s xrD, xrJ, xrK is op15_31=0x192c & xrD & xrJ & xrK {\n\txrD = xvfcmp.cueq.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sueq.s;\n\n#lasx.txt xvfcmp.sueq.s mask=0x0c968000\t\n#0x0c968000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sueq.s xrD, xrJ, xrK is op15_31=0x192d & xrD & xrJ & xrK {\n\txrD = xvfcmp.sueq.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cule.s;\n\n#lasx.txt xvfcmp.cule.s mask=0x0c970000\t\n#0x0c970000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cule.s xrD, xrJ, xrK is op15_31=0x192e & xrD & xrJ & xrK {\n\txrD = xvfcmp.cule.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sule.s;\n\n#lasx.txt xvfcmp.sule.s mask=0x0c978000\t\n#0x0c978000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sule.s xrD, xrJ, xrK is op15_31=0x192f & xrD & xrJ & xrK {\n\txrD = xvfcmp.sule.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cne.s;\n\n#lasx.txt xvfcmp.cne.s mask=0x0c980000\t\n#0x0c980000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cne.s xrD, xrJ, xrK is op15_31=0x1930 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cne.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sne.s;\n\n#lasx.txt xvfcmp.sne.s mask=0x0c988000\t\n#0x0c988000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sne.s xrD, xrJ, xrK is op15_31=0x1931 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sne.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cor.s;\n\n#lasx.txt xvfcmp.cor.s mask=0x0c9a0000\t\n#0x0c9a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cor.s xrD, xrJ, xrK is op15_31=0x1934 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cor.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sor.s;\n\n#lasx.txt xvfcmp.sor.s mask=0x0c9a8000\t\n#0x0c9a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sor.s xrD, xrJ, xrK is op15_31=0x1935 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sor.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cune.s;\n\n#lasx.txt xvfcmp.cune.s mask=0x0c9c0000\t\n#0x0c9c0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cune.s xrD, xrJ, xrK is op15_31=0x1938 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cune.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sune.s;\n\n#lasx.txt xvfcmp.sune.s mask=0x0c9c8000\t\n#0x0c9c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sune.s xrD, xrJ, xrK is op15_31=0x1939 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sune.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.caf.d;\n\n#lasx.txt xvfcmp.caf.d mask=0x0ca00000\t\n#0x0ca00000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.caf.d xrD, xrJ, xrK is op15_31=0x1940 & xrD & xrJ & xrK {\n\txrD = xvfcmp.caf.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.saf.d;\n\n#lasx.txt xvfcmp.saf.d mask=0x0ca08000\t\n#0x0ca08000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.saf.d xrD, xrJ, xrK is op15_31=0x1941 & xrD & xrJ & xrK {\n\txrD = xvfcmp.saf.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.clt.d;\n\n#lasx.txt xvfcmp.clt.d mask=0x0ca10000\t\n#0x0ca10000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.clt.d xrD, xrJ, xrK is op15_31=0x1942 & xrD & xrJ & xrK {\n\txrD = xvfcmp.clt.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.slt.d;\n\n#lasx.txt xvfcmp.slt.d mask=0x0ca18000\t\n#0x0ca18000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.slt.d xrD, xrJ, xrK is op15_31=0x1943 & xrD & xrJ & xrK {\n\txrD = xvfcmp.slt.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.ceq.d;\n\n#lasx.txt xvfcmp.ceq.d mask=0x0ca20000\t\n#0x0ca20000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.ceq.d xrD, xrJ, xrK is op15_31=0x1944 & xrD & xrJ & xrK {\n\txrD = xvfcmp.ceq.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.seq.d;\n\n#lasx.txt xvfcmp.seq.d mask=0x0ca28000\t\n#0x0ca28000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.seq.d xrD, xrJ, xrK is op15_31=0x1945 & xrD & xrJ & xrK {\n\txrD = xvfcmp.seq.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cle.d;\n\n#lasx.txt xvfcmp.cle.d mask=0x0ca30000\t\n#0x0ca30000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cle.d xrD, xrJ, xrK is op15_31=0x1946 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cle.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sle.d;\n\n#lasx.txt xvfcmp.sle.d mask=0x0ca38000\t\n#0x0ca38000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sle.d xrD, xrJ, xrK is op15_31=0x1947 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sle.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cun.d;\n\n#lasx.txt xvfcmp.cun.d mask=0x0ca40000\t\n#0x0ca40000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cun.d xrD, xrJ, xrK is op15_31=0x1948 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cun.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sun.d;\n\n#lasx.txt xvfcmp.sun.d mask=0x0ca48000\t\n#0x0ca48000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sun.d xrD, xrJ, xrK is op15_31=0x1949 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sun.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cult.d;\n\n#lasx.txt xvfcmp.cult.d mask=0x0ca50000\t\n#0x0ca50000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cult.d xrD, xrJ, xrK is op15_31=0x194a & xrD & xrJ & xrK {\n\txrD = xvfcmp.cult.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sult.d;\n\n#lasx.txt xvfcmp.sult.d mask=0x0ca58000\t\n#0x0ca58000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sult.d xrD, xrJ, xrK is op15_31=0x194b & xrD & xrJ & xrK {\n\txrD = xvfcmp.sult.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cueq.d;\n\n#lasx.txt xvfcmp.cueq.d mask=0x0ca60000\t\n#0x0ca60000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cueq.d xrD, xrJ, xrK is op15_31=0x194c & xrD & xrJ & xrK {\n\txrD = xvfcmp.cueq.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sueq.d;\n\n#lasx.txt xvfcmp.sueq.d mask=0x0ca68000\t\n#0x0ca68000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sueq.d xrD, xrJ, xrK is op15_31=0x194d & xrD & xrJ & xrK {\n\txrD = xvfcmp.sueq.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cule.d;\n\n#lasx.txt xvfcmp.cule.d mask=0x0ca70000\t\n#0x0ca70000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cule.d xrD, xrJ, xrK is op15_31=0x194e & xrD & xrJ & xrK {\n\txrD = xvfcmp.cule.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sule.d;\n\n#lasx.txt xvfcmp.sule.d mask=0x0ca78000\t\n#0x0ca78000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sule.d xrD, xrJ, xrK is op15_31=0x194f & xrD & xrJ & xrK {\n\txrD = xvfcmp.sule.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cne.d;\n\n#lasx.txt xvfcmp.cne.d mask=0x0ca80000\t\n#0x0ca80000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cne.d xrD, xrJ, xrK is op15_31=0x1950 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cne.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sne.d;\n\n#lasx.txt xvfcmp.sne.d mask=0x0ca88000\t\n#0x0ca88000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sne.d xrD, xrJ, xrK is op15_31=0x1951 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sne.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cor.d;\n\n#lasx.txt xvfcmp.cor.d mask=0x0caa0000\t\n#0x0caa0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cor.d xrD, xrJ, xrK is op15_31=0x1954 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cor.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sor.d;\n\n#lasx.txt xvfcmp.sor.d mask=0x0caa8000\t\n#0x0caa8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sor.d xrD, xrJ, xrK is op15_31=0x1955 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sor.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.cune.d;\n\n#lasx.txt xvfcmp.cune.d mask=0x0cac0000\t\n#0x0cac0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.cune.d xrD, xrJ, xrK is op15_31=0x1958 & xrD & xrJ & xrK {\n\txrD = xvfcmp.cune.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcmp.sune.d;\n\n#lasx.txt xvfcmp.sune.d mask=0x0cac8000\t\n#0x0cac8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcmp.sune.d xrD, xrJ, xrK is op15_31=0x1959 & xrD & xrJ & xrK {\n\txrD = xvfcmp.sune.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitsel.v;\n\n#lasx.txt xvbitsel.v mask=0x0d200000\t\n#0x0d200000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvbitsel.v xrD, xrJ, xrK, xrA is op20_31=0xd2 & xrD & xrJ & xrK & xrA {\n\txrD = xvbitsel.v(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvshuf.b;\n\n#lasx.txt xvshuf.b mask=0x0d600000\t\n#0x0d600000\t0xfff00000\tx0:5,x5:5,x10:5,x15:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0']\n:xvshuf.b xrD, xrJ, xrK, xrA is op20_31=0xd6 & xrD & xrJ & xrK & xrA {\n\txrD = xvshuf.b(xrD, xrJ, xrK, xrA);\n}\n\ndefine pcodeop xvld;\n\n#lasx.txt xvld mask=0x2c800000\t\n#0x2c800000\t0xffc00000\tx0:5, r5:5,so10:12\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:xvld xrD, RJsrc,simm10_12 is op22_31=0xb2 & xrD & RJsrc & simm10_12 {\n\txrD = xvld(xrD, RJsrc, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop xvst;\n\n#lasx.txt xvst mask=0x2cc00000\t\n#0x2cc00000\t0xffc00000\tx0:5, r5:5,so10:12\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:xvst xrD, RJsrc,simm10_12 is op22_31=0xb3 & xrD & RJsrc & simm10_12 {\n\txrD = xvst(xrD, RJsrc, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop xvldrepl.d;\n\n#lasx.txt xvldrepl.d mask=0x32100000\t[@orig_fmt=XdJSk9ps3]\n#0x32100000\t0xfff80000\tx0:5, r5:5,so10:9<<3\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0']\n:xvldrepl.d xrD, RJsrc,simm10_9 is op19_31=0x642 & xrD & RJsrc & simm10_9 {\n\txrD = xvldrepl.d(xrD, RJsrc, simm10_9:$(REGSIZE));\n}\n\ndefine pcodeop xvldrepl.w;\n\n#lasx.txt xvldrepl.w mask=0x32200000\t[@orig_fmt=XdJSk10ps2]\n#0x32200000\t0xfff00000\tx0:5, r5:5,so10:10<<2\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0']\n:xvldrepl.w xrD, RJsrc,simm10_10 is op20_31=0x322 & xrD & RJsrc & simm10_10 {\n\txrD = xvldrepl.w(xrD, RJsrc, simm10_10:$(REGSIZE));\n}\n\ndefine pcodeop xvldrepl.h;\n\n#lasx.txt xvldrepl.h mask=0x32400000\t[@orig_fmt=XdJSk11ps1]\n#0x32400000\t0xffe00000\tx0:5, r5:5,so10:11<<1\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0']\n:xvldrepl.h xrD, RJsrc,simm10_11 is op21_31=0x192 & xrD & RJsrc & simm10_11 {\n\txrD = xvldrepl.h(xrD, RJsrc, simm10_11:$(REGSIZE));\n}\n\ndefine pcodeop xvldrepl.b;\n\n#lasx.txt xvldrepl.b mask=0x32800000\t\n#0x32800000\t0xffc00000\tx0:5, r5:5,so10:12\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:xvldrepl.b xrD, RJsrc,simm10_12 is op22_31=0xca & xrD & RJsrc & simm10_12 {\n\txrD = xvldrepl.b(xrD, RJsrc, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop xvstelm.d;\n\n#lasx.txt xvstelm.d mask=0x33100000\t[@orig_fmt=XdJSk8ps3Un2]\n#0x33100000\t0xfff00000\tx0:5, r5:5,so10:8<<3,u18:2\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0']\n:xvstelm.d xrD, RJsrc,simm10_8, imm18_2 is op20_31=0x331 & xrD & RJsrc & simm10_8 & imm18_2 {\n\txrD = xvstelm.d(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE));\n}\n\ndefine pcodeop xvstelm.w;\n\n#lasx.txt xvstelm.w mask=0x33200000\t[@orig_fmt=XdJSk8ps2Un3]\n#0x33200000\t0xffe00000\tx0:5, r5:5,so10:8<<2,u18:3\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0']\n:xvstelm.w xrD, RJsrc,simm10_8, imm18_3 is op21_31=0x199 & xrD & RJsrc & simm10_8 & imm18_3 {\n\txrD = xvstelm.w(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE));\n}\n\ndefine pcodeop xvstelm.h;\n\n#lasx.txt xvstelm.h mask=0x33400000\t[@orig_fmt=XdJSk8ps1Un4]\n#0x33400000\t0xffc00000\tx0:5, r5:5,so10:8<<1,u18:4\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0']\n:xvstelm.h xrD, RJsrc,simm10_8, imm18_4 is op22_31=0xcd & xrD & RJsrc & simm10_8 & imm18_4 {\n\txrD = xvstelm.h(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE));\n}\n\ndefine pcodeop xvstelm.b;\n\n#lasx.txt xvstelm.b mask=0x33800000\t\n#0x33800000\t0xff800000\tx0:5, r5:5,so10:8,u18:5\t['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_5_s0']\n:xvstelm.b xrD, RJsrc,simm10_8, imm18_5 is op23_31=0x67 & xrD & RJsrc & simm10_8 & imm18_5 {\n\txrD = xvstelm.b(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_5:$(REGSIZE));\n}\n\ndefine pcodeop xvldx;\n\n#lasx.txt xvldx mask=0x38480000\t\n#0x38480000\t0xffff8000\tx0:5, r5:5, r10:5\t['xreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:xvldx xrD, RJsrc, RKsrc is op15_31=0x7090 & xrD & RJsrc & RKsrc {\n\txrD = xvldx(xrD, RJsrc, RKsrc);\n}\n\ndefine pcodeop xvstx;\n\n#lasx.txt xvstx mask=0x384c0000\t\n#0x384c0000\t0xffff8000\tx0:5, r5:5, r10:5\t['xreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:xvstx xrD, RJsrc, RKsrc is op15_31=0x7098 & xrD & RJsrc & RKsrc {\n\txrD = xvstx(xrD, RJsrc, RKsrc);\n}\n\ndefine pcodeop xvseq.b;\n\n#lasx.txt xvseq.b mask=0x74000000\t\n#0x74000000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvseq.b xrD, xrJ, xrK is op15_31=0xe800 & xrD & xrJ & xrK {\n\txrD = xvseq.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvseq.h;\n\n#lasx.txt xvseq.h mask=0x74008000\t\n#0x74008000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvseq.h xrD, xrJ, xrK is op15_31=0xe801 & xrD & xrJ & xrK {\n\txrD = xvseq.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvseq.w;\n\n#lasx.txt xvseq.w mask=0x74010000\t\n#0x74010000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvseq.w xrD, xrJ, xrK is op15_31=0xe802 & xrD & xrJ & xrK {\n\txrD = xvseq.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvseq.d;\n\n#lasx.txt xvseq.d mask=0x74018000\t\n#0x74018000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvseq.d xrD, xrJ, xrK is op15_31=0xe803 & xrD & xrJ & xrK {\n\txrD = xvseq.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.b;\n\n#lasx.txt xvsle.b mask=0x74020000\t\n#0x74020000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.b xrD, xrJ, xrK is op15_31=0xe804 & xrD & xrJ & xrK {\n\txrD = xvsle.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.h;\n\n#lasx.txt xvsle.h mask=0x74028000\t\n#0x74028000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.h xrD, xrJ, xrK is op15_31=0xe805 & xrD & xrJ & xrK {\n\txrD = xvsle.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.w;\n\n#lasx.txt xvsle.w mask=0x74030000\t\n#0x74030000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.w xrD, xrJ, xrK is op15_31=0xe806 & xrD & xrJ & xrK {\n\txrD = xvsle.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.d;\n\n#lasx.txt xvsle.d mask=0x74038000\t\n#0x74038000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.d xrD, xrJ, xrK is op15_31=0xe807 & xrD & xrJ & xrK {\n\txrD = xvsle.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.bu;\n\n#lasx.txt xvsle.bu mask=0x74040000\t\n#0x74040000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.bu xrD, xrJ, xrK is op15_31=0xe808 & xrD & xrJ & xrK {\n\txrD = xvsle.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.hu;\n\n#lasx.txt xvsle.hu mask=0x74048000\t\n#0x74048000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.hu xrD, xrJ, xrK is op15_31=0xe809 & xrD & xrJ & xrK {\n\txrD = xvsle.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.wu;\n\n#lasx.txt xvsle.wu mask=0x74050000\t\n#0x74050000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.wu xrD, xrJ, xrK is op15_31=0xe80a & xrD & xrJ & xrK {\n\txrD = xvsle.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsle.du;\n\n#lasx.txt xvsle.du mask=0x74058000\t\n#0x74058000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsle.du xrD, xrJ, xrK is op15_31=0xe80b & xrD & xrJ & xrK {\n\txrD = xvsle.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.b;\n\n#lasx.txt xvslt.b mask=0x74060000\t\n#0x74060000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.b xrD, xrJ, xrK is op15_31=0xe80c & xrD & xrJ & xrK {\n\txrD = xvslt.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.h;\n\n#lasx.txt xvslt.h mask=0x74068000\t\n#0x74068000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.h xrD, xrJ, xrK is op15_31=0xe80d & xrD & xrJ & xrK {\n\txrD = xvslt.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.w;\n\n#lasx.txt xvslt.w mask=0x74070000\t\n#0x74070000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.w xrD, xrJ, xrK is op15_31=0xe80e & xrD & xrJ & xrK {\n\txrD = xvslt.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.d;\n\n#lasx.txt xvslt.d mask=0x74078000\t\n#0x74078000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.d xrD, xrJ, xrK is op15_31=0xe80f & xrD & xrJ & xrK {\n\txrD = xvslt.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.bu;\n\n#lasx.txt xvslt.bu mask=0x74080000\t\n#0x74080000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.bu xrD, xrJ, xrK is op15_31=0xe810 & xrD & xrJ & xrK {\n\txrD = xvslt.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.hu;\n\n#lasx.txt xvslt.hu mask=0x74088000\t\n#0x74088000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.hu xrD, xrJ, xrK is op15_31=0xe811 & xrD & xrJ & xrK {\n\txrD = xvslt.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.wu;\n\n#lasx.txt xvslt.wu mask=0x74090000\t\n#0x74090000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.wu xrD, xrJ, xrK is op15_31=0xe812 & xrD & xrJ & xrK {\n\txrD = xvslt.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvslt.du;\n\n#lasx.txt xvslt.du mask=0x74098000\t\n#0x74098000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvslt.du xrD, xrJ, xrK is op15_31=0xe813 & xrD & xrJ & xrK {\n\txrD = xvslt.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadd.b;\n\n#lasx.txt xvadd.b mask=0x740a0000\t\n#0x740a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadd.b xrD, xrJ, xrK is op15_31=0xe814 & xrD & xrJ & xrK {\n\txrD = xvadd.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadd.h;\n\n#lasx.txt xvadd.h mask=0x740a8000\t\n#0x740a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadd.h xrD, xrJ, xrK is op15_31=0xe815 & xrD & xrJ & xrK {\n\txrD = xvadd.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadd.w;\n\n#lasx.txt xvadd.w mask=0x740b0000\t\n#0x740b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadd.w xrD, xrJ, xrK is op15_31=0xe816 & xrD & xrJ & xrK {\n\txrD = xvadd.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadd.d;\n\n#lasx.txt xvadd.d mask=0x740b8000\t\n#0x740b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadd.d xrD, xrJ, xrK is op15_31=0xe817 & xrD & xrJ & xrK {\n\txrD = xvadd.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsub.b;\n\n#lasx.txt xvsub.b mask=0x740c0000\t\n#0x740c0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsub.b xrD, xrJ, xrK is op15_31=0xe818 & xrD & xrJ & xrK {\n\txrD = xvsub.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsub.h;\n\n#lasx.txt xvsub.h mask=0x740c8000\t\n#0x740c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsub.h xrD, xrJ, xrK is op15_31=0xe819 & xrD & xrJ & xrK {\n\txrD = xvsub.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsub.w;\n\n#lasx.txt xvsub.w mask=0x740d0000\t\n#0x740d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsub.w xrD, xrJ, xrK is op15_31=0xe81a & xrD & xrJ & xrK {\n\txrD = xvsub.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsub.d;\n\n#lasx.txt xvsub.d mask=0x740d8000\t\n#0x740d8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsub.d xrD, xrJ, xrK is op15_31=0xe81b & xrD & xrJ & xrK {\n\txrD = xvsub.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.h.b;\n\n#lasx.txt xvaddwev.h.b mask=0x741e0000\t\n#0x741e0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.h.b xrD, xrJ, xrK is op15_31=0xe83c & xrD & xrJ & xrK {\n\txrD = xvaddwev.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.w.h;\n\n#lasx.txt xvaddwev.w.h mask=0x741e8000\t\n#0x741e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.w.h xrD, xrJ, xrK is op15_31=0xe83d & xrD & xrJ & xrK {\n\txrD = xvaddwev.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.d.w;\n\n#lasx.txt xvaddwev.d.w mask=0x741f0000\t\n#0x741f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.d.w xrD, xrJ, xrK is op15_31=0xe83e & xrD & xrJ & xrK {\n\txrD = xvaddwev.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.q.d;\n\n#lasx.txt xvaddwev.q.d mask=0x741f8000\t\n#0x741f8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.q.d xrD, xrJ, xrK is op15_31=0xe83f & xrD & xrJ & xrK {\n\txrD = xvaddwev.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.h.b;\n\n#lasx.txt xvsubwev.h.b mask=0x74200000\t\n#0x74200000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.h.b xrD, xrJ, xrK is op15_31=0xe840 & xrD & xrJ & xrK {\n\txrD = xvsubwev.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.w.h;\n\n#lasx.txt xvsubwev.w.h mask=0x74208000\t\n#0x74208000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.w.h xrD, xrJ, xrK is op15_31=0xe841 & xrD & xrJ & xrK {\n\txrD = xvsubwev.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.d.w;\n\n#lasx.txt xvsubwev.d.w mask=0x74210000\t\n#0x74210000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.d.w xrD, xrJ, xrK is op15_31=0xe842 & xrD & xrJ & xrK {\n\txrD = xvsubwev.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.q.d;\n\n#lasx.txt xvsubwev.q.d mask=0x74218000\t\n#0x74218000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.q.d xrD, xrJ, xrK is op15_31=0xe843 & xrD & xrJ & xrK {\n\txrD = xvsubwev.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.h.b;\n\n#lasx.txt xvaddwod.h.b mask=0x74220000\t\n#0x74220000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.h.b xrD, xrJ, xrK is op15_31=0xe844 & xrD & xrJ & xrK {\n\txrD = xvaddwod.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.w.h;\n\n#lasx.txt xvaddwod.w.h mask=0x74228000\t\n#0x74228000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.w.h xrD, xrJ, xrK is op15_31=0xe845 & xrD & xrJ & xrK {\n\txrD = xvaddwod.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.d.w;\n\n#lasx.txt xvaddwod.d.w mask=0x74230000\t\n#0x74230000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.d.w xrD, xrJ, xrK is op15_31=0xe846 & xrD & xrJ & xrK {\n\txrD = xvaddwod.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.q.d;\n\n#lasx.txt xvaddwod.q.d mask=0x74238000\t\n#0x74238000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.q.d xrD, xrJ, xrK is op15_31=0xe847 & xrD & xrJ & xrK {\n\txrD = xvaddwod.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.h.b;\n\n#lasx.txt xvsubwod.h.b mask=0x74240000\t\n#0x74240000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.h.b xrD, xrJ, xrK is op15_31=0xe848 & xrD & xrJ & xrK {\n\txrD = xvsubwod.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.w.h;\n\n#lasx.txt xvsubwod.w.h mask=0x74248000\t\n#0x74248000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.w.h xrD, xrJ, xrK is op15_31=0xe849 & xrD & xrJ & xrK {\n\txrD = xvsubwod.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.d.w;\n\n#lasx.txt xvsubwod.d.w mask=0x74250000\t\n#0x74250000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.d.w xrD, xrJ, xrK is op15_31=0xe84a & xrD & xrJ & xrK {\n\txrD = xvsubwod.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.q.d;\n\n#lasx.txt xvsubwod.q.d mask=0x74258000\t\n#0x74258000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.q.d xrD, xrJ, xrK is op15_31=0xe84b & xrD & xrJ & xrK {\n\txrD = xvsubwod.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.h.bu;\n\n#lasx.txt xvaddwev.h.bu mask=0x742e0000\t\n#0x742e0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.h.bu xrD, xrJ, xrK is op15_31=0xe85c & xrD & xrJ & xrK {\n\txrD = xvaddwev.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.w.hu;\n\n#lasx.txt xvaddwev.w.hu mask=0x742e8000\t\n#0x742e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.w.hu xrD, xrJ, xrK is op15_31=0xe85d & xrD & xrJ & xrK {\n\txrD = xvaddwev.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.d.wu;\n\n#lasx.txt xvaddwev.d.wu mask=0x742f0000\t\n#0x742f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.d.wu xrD, xrJ, xrK is op15_31=0xe85e & xrD & xrJ & xrK {\n\txrD = xvaddwev.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.q.du;\n\n#lasx.txt xvaddwev.q.du mask=0x742f8000\t\n#0x742f8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.q.du xrD, xrJ, xrK is op15_31=0xe85f & xrD & xrJ & xrK {\n\txrD = xvaddwev.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.h.bu;\n\n#lasx.txt xvsubwev.h.bu mask=0x74300000\t\n#0x74300000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.h.bu xrD, xrJ, xrK is op15_31=0xe860 & xrD & xrJ & xrK {\n\txrD = xvsubwev.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.w.hu;\n\n#lasx.txt xvsubwev.w.hu mask=0x74308000\t\n#0x74308000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.w.hu xrD, xrJ, xrK is op15_31=0xe861 & xrD & xrJ & xrK {\n\txrD = xvsubwev.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.d.wu;\n\n#lasx.txt xvsubwev.d.wu mask=0x74310000\t\n#0x74310000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.d.wu xrD, xrJ, xrK is op15_31=0xe862 & xrD & xrJ & xrK {\n\txrD = xvsubwev.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwev.q.du;\n\n#lasx.txt xvsubwev.q.du mask=0x74318000\t\n#0x74318000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwev.q.du xrD, xrJ, xrK is op15_31=0xe863 & xrD & xrJ & xrK {\n\txrD = xvsubwev.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.h.bu;\n\n#lasx.txt xvaddwod.h.bu mask=0x74320000\t\n#0x74320000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.h.bu xrD, xrJ, xrK is op15_31=0xe864 & xrD & xrJ & xrK {\n\txrD = xvaddwod.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.w.hu;\n\n#lasx.txt xvaddwod.w.hu mask=0x74328000\t\n#0x74328000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.w.hu xrD, xrJ, xrK is op15_31=0xe865 & xrD & xrJ & xrK {\n\txrD = xvaddwod.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.d.wu;\n\n#lasx.txt xvaddwod.d.wu mask=0x74330000\t\n#0x74330000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.d.wu xrD, xrJ, xrK is op15_31=0xe866 & xrD & xrJ & xrK {\n\txrD = xvaddwod.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.q.du;\n\n#lasx.txt xvaddwod.q.du mask=0x74338000\t\n#0x74338000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.q.du xrD, xrJ, xrK is op15_31=0xe867 & xrD & xrJ & xrK {\n\txrD = xvaddwod.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.h.bu;\n\n#lasx.txt xvsubwod.h.bu mask=0x74340000\t\n#0x74340000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.h.bu xrD, xrJ, xrK is op15_31=0xe868 & xrD & xrJ & xrK {\n\txrD = xvsubwod.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.w.hu;\n\n#lasx.txt xvsubwod.w.hu mask=0x74348000\t\n#0x74348000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.w.hu xrD, xrJ, xrK is op15_31=0xe869 & xrD & xrJ & xrK {\n\txrD = xvsubwod.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.d.wu;\n\n#lasx.txt xvsubwod.d.wu mask=0x74350000\t\n#0x74350000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.d.wu xrD, xrJ, xrK is op15_31=0xe86a & xrD & xrJ & xrK {\n\txrD = xvsubwod.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsubwod.q.du;\n\n#lasx.txt xvsubwod.q.du mask=0x74358000\t\n#0x74358000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsubwod.q.du xrD, xrJ, xrK is op15_31=0xe86b & xrD & xrJ & xrK {\n\txrD = xvsubwod.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.h.bu.b;\n\n#lasx.txt xvaddwev.h.bu.b mask=0x743e0000\t\n#0x743e0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.h.bu.b xrD, xrJ, xrK is op15_31=0xe87c & xrD & xrJ & xrK {\n\txrD = xvaddwev.h.bu.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.w.hu.h;\n\n#lasx.txt xvaddwev.w.hu.h mask=0x743e8000\t\n#0x743e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.w.hu.h xrD, xrJ, xrK is op15_31=0xe87d & xrD & xrJ & xrK {\n\txrD = xvaddwev.w.hu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.d.wu.w;\n\n#lasx.txt xvaddwev.d.wu.w mask=0x743f0000\t\n#0x743f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.d.wu.w xrD, xrJ, xrK is op15_31=0xe87e & xrD & xrJ & xrK {\n\txrD = xvaddwev.d.wu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwev.q.du.d;\n\n#lasx.txt xvaddwev.q.du.d mask=0x743f8000\t\n#0x743f8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwev.q.du.d xrD, xrJ, xrK is op15_31=0xe87f & xrD & xrJ & xrK {\n\txrD = xvaddwev.q.du.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.h.bu.b;\n\n#lasx.txt xvaddwod.h.bu.b mask=0x74400000\t\n#0x74400000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.h.bu.b xrD, xrJ, xrK is op15_31=0xe880 & xrD & xrJ & xrK {\n\txrD = xvaddwod.h.bu.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.w.hu.h;\n\n#lasx.txt xvaddwod.w.hu.h mask=0x74408000\t\n#0x74408000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.w.hu.h xrD, xrJ, xrK is op15_31=0xe881 & xrD & xrJ & xrK {\n\txrD = xvaddwod.w.hu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.d.wu.w;\n\n#lasx.txt xvaddwod.d.wu.w mask=0x74410000\t\n#0x74410000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.d.wu.w xrD, xrJ, xrK is op15_31=0xe882 & xrD & xrJ & xrK {\n\txrD = xvaddwod.d.wu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvaddwod.q.du.d;\n\n#lasx.txt xvaddwod.q.du.d mask=0x74418000\t\n#0x74418000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvaddwod.q.du.d xrD, xrJ, xrK is op15_31=0xe883 & xrD & xrJ & xrK {\n\txrD = xvaddwod.q.du.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.b;\n\n#lasx.txt xvsadd.b mask=0x74460000\t\n#0x74460000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.b xrD, xrJ, xrK is op15_31=0xe88c & xrD & xrJ & xrK {\n\txrD = xvsadd.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.h;\n\n#lasx.txt xvsadd.h mask=0x74468000\t\n#0x74468000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.h xrD, xrJ, xrK is op15_31=0xe88d & xrD & xrJ & xrK {\n\txrD = xvsadd.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.w;\n\n#lasx.txt xvsadd.w mask=0x74470000\t\n#0x74470000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.w xrD, xrJ, xrK is op15_31=0xe88e & xrD & xrJ & xrK {\n\txrD = xvsadd.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.d;\n\n#lasx.txt xvsadd.d mask=0x74478000\t\n#0x74478000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.d xrD, xrJ, xrK is op15_31=0xe88f & xrD & xrJ & xrK {\n\txrD = xvsadd.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.b;\n\n#lasx.txt xvssub.b mask=0x74480000\t\n#0x74480000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.b xrD, xrJ, xrK is op15_31=0xe890 & xrD & xrJ & xrK {\n\txrD = xvssub.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.h;\n\n#lasx.txt xvssub.h mask=0x74488000\t\n#0x74488000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.h xrD, xrJ, xrK is op15_31=0xe891 & xrD & xrJ & xrK {\n\txrD = xvssub.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.w;\n\n#lasx.txt xvssub.w mask=0x74490000\t\n#0x74490000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.w xrD, xrJ, xrK is op15_31=0xe892 & xrD & xrJ & xrK {\n\txrD = xvssub.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.d;\n\n#lasx.txt xvssub.d mask=0x74498000\t\n#0x74498000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.d xrD, xrJ, xrK is op15_31=0xe893 & xrD & xrJ & xrK {\n\txrD = xvssub.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.bu;\n\n#lasx.txt xvsadd.bu mask=0x744a0000\t\n#0x744a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.bu xrD, xrJ, xrK is op15_31=0xe894 & xrD & xrJ & xrK {\n\txrD = xvsadd.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.hu;\n\n#lasx.txt xvsadd.hu mask=0x744a8000\t\n#0x744a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.hu xrD, xrJ, xrK is op15_31=0xe895 & xrD & xrJ & xrK {\n\txrD = xvsadd.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.wu;\n\n#lasx.txt xvsadd.wu mask=0x744b0000\t\n#0x744b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.wu xrD, xrJ, xrK is op15_31=0xe896 & xrD & xrJ & xrK {\n\txrD = xvsadd.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsadd.du;\n\n#lasx.txt xvsadd.du mask=0x744b8000\t\n#0x744b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsadd.du xrD, xrJ, xrK is op15_31=0xe897 & xrD & xrJ & xrK {\n\txrD = xvsadd.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.bu;\n\n#lasx.txt xvssub.bu mask=0x744c0000\t\n#0x744c0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.bu xrD, xrJ, xrK is op15_31=0xe898 & xrD & xrJ & xrK {\n\txrD = xvssub.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.hu;\n\n#lasx.txt xvssub.hu mask=0x744c8000\t\n#0x744c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.hu xrD, xrJ, xrK is op15_31=0xe899 & xrD & xrJ & xrK {\n\txrD = xvssub.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.wu;\n\n#lasx.txt xvssub.wu mask=0x744d0000\t\n#0x744d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.wu xrD, xrJ, xrK is op15_31=0xe89a & xrD & xrJ & xrK {\n\txrD = xvssub.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssub.du;\n\n#lasx.txt xvssub.du mask=0x744d8000\t\n#0x744d8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssub.du xrD, xrJ, xrK is op15_31=0xe89b & xrD & xrJ & xrK {\n\txrD = xvssub.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.h.b;\n\n#lasx.txt xvhaddw.h.b mask=0x74540000\t\n#0x74540000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.h.b xrD, xrJ, xrK is op15_31=0xe8a8 & xrD & xrJ & xrK {\n\txrD = xvhaddw.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.w.h;\n\n#lasx.txt xvhaddw.w.h mask=0x74548000\t\n#0x74548000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.w.h xrD, xrJ, xrK is op15_31=0xe8a9 & xrD & xrJ & xrK {\n\txrD = xvhaddw.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.d.w;\n\n#lasx.txt xvhaddw.d.w mask=0x74550000\t\n#0x74550000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.d.w xrD, xrJ, xrK is op15_31=0xe8aa & xrD & xrJ & xrK {\n\txrD = xvhaddw.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.q.d;\n\n#lasx.txt xvhaddw.q.d mask=0x74558000\t\n#0x74558000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.q.d xrD, xrJ, xrK is op15_31=0xe8ab & xrD & xrJ & xrK {\n\txrD = xvhaddw.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.h.b;\n\n#lasx.txt xvhsubw.h.b mask=0x74560000\t\n#0x74560000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.h.b xrD, xrJ, xrK is op15_31=0xe8ac & xrD & xrJ & xrK {\n\txrD = xvhsubw.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.w.h;\n\n#lasx.txt xvhsubw.w.h mask=0x74568000\t\n#0x74568000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.w.h xrD, xrJ, xrK is op15_31=0xe8ad & xrD & xrJ & xrK {\n\txrD = xvhsubw.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.d.w;\n\n#lasx.txt xvhsubw.d.w mask=0x74570000\t\n#0x74570000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.d.w xrD, xrJ, xrK is op15_31=0xe8ae & xrD & xrJ & xrK {\n\txrD = xvhsubw.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.q.d;\n\n#lasx.txt xvhsubw.q.d mask=0x74578000\t\n#0x74578000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.q.d xrD, xrJ, xrK is op15_31=0xe8af & xrD & xrJ & xrK {\n\txrD = xvhsubw.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.hu.bu;\n\n#lasx.txt xvhaddw.hu.bu mask=0x74580000\t\n#0x74580000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.hu.bu xrD, xrJ, xrK is op15_31=0xe8b0 & xrD & xrJ & xrK {\n\txrD = xvhaddw.hu.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.wu.hu;\n\n#lasx.txt xvhaddw.wu.hu mask=0x74588000\t\n#0x74588000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.wu.hu xrD, xrJ, xrK is op15_31=0xe8b1 & xrD & xrJ & xrK {\n\txrD = xvhaddw.wu.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.du.wu;\n\n#lasx.txt xvhaddw.du.wu mask=0x74590000\t\n#0x74590000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.du.wu xrD, xrJ, xrK is op15_31=0xe8b2 & xrD & xrJ & xrK {\n\txrD = xvhaddw.du.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhaddw.qu.du;\n\n#lasx.txt xvhaddw.qu.du mask=0x74598000\t\n#0x74598000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhaddw.qu.du xrD, xrJ, xrK is op15_31=0xe8b3 & xrD & xrJ & xrK {\n\txrD = xvhaddw.qu.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.hu.bu;\n\n#lasx.txt xvhsubw.hu.bu mask=0x745a0000\t\n#0x745a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.hu.bu xrD, xrJ, xrK is op15_31=0xe8b4 & xrD & xrJ & xrK {\n\txrD = xvhsubw.hu.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.wu.hu;\n\n#lasx.txt xvhsubw.wu.hu mask=0x745a8000\t\n#0x745a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.wu.hu xrD, xrJ, xrK is op15_31=0xe8b5 & xrD & xrJ & xrK {\n\txrD = xvhsubw.wu.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.du.wu;\n\n#lasx.txt xvhsubw.du.wu mask=0x745b0000\t\n#0x745b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.du.wu xrD, xrJ, xrK is op15_31=0xe8b6 & xrD & xrJ & xrK {\n\txrD = xvhsubw.du.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvhsubw.qu.du;\n\n#lasx.txt xvhsubw.qu.du mask=0x745b8000\t\n#0x745b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvhsubw.qu.du xrD, xrJ, xrK is op15_31=0xe8b7 & xrD & xrJ & xrK {\n\txrD = xvhsubw.qu.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadda.b;\n\n#lasx.txt xvadda.b mask=0x745c0000\t\n#0x745c0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadda.b xrD, xrJ, xrK is op15_31=0xe8b8 & xrD & xrJ & xrK {\n\txrD = xvadda.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadda.h;\n\n#lasx.txt xvadda.h mask=0x745c8000\t\n#0x745c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadda.h xrD, xrJ, xrK is op15_31=0xe8b9 & xrD & xrJ & xrK {\n\txrD = xvadda.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadda.w;\n\n#lasx.txt xvadda.w mask=0x745d0000\t\n#0x745d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadda.w xrD, xrJ, xrK is op15_31=0xe8ba & xrD & xrJ & xrK {\n\txrD = xvadda.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadda.d;\n\n#lasx.txt xvadda.d mask=0x745d8000\t\n#0x745d8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadda.d xrD, xrJ, xrK is op15_31=0xe8bb & xrD & xrJ & xrK {\n\txrD = xvadda.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.b;\n\n#lasx.txt xvabsd.b mask=0x74600000\t\n#0x74600000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.b xrD, xrJ, xrK is op15_31=0xe8c0 & xrD & xrJ & xrK {\n\txrD = xvabsd.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.h;\n\n#lasx.txt xvabsd.h mask=0x74608000\t\n#0x74608000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.h xrD, xrJ, xrK is op15_31=0xe8c1 & xrD & xrJ & xrK {\n\txrD = xvabsd.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.w;\n\n#lasx.txt xvabsd.w mask=0x74610000\t\n#0x74610000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.w xrD, xrJ, xrK is op15_31=0xe8c2 & xrD & xrJ & xrK {\n\txrD = xvabsd.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.d;\n\n#lasx.txt xvabsd.d mask=0x74618000\t\n#0x74618000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.d xrD, xrJ, xrK is op15_31=0xe8c3 & xrD & xrJ & xrK {\n\txrD = xvabsd.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.bu;\n\n#lasx.txt xvabsd.bu mask=0x74620000\t\n#0x74620000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.bu xrD, xrJ, xrK is op15_31=0xe8c4 & xrD & xrJ & xrK {\n\txrD = xvabsd.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.hu;\n\n#lasx.txt xvabsd.hu mask=0x74628000\t\n#0x74628000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.hu xrD, xrJ, xrK is op15_31=0xe8c5 & xrD & xrJ & xrK {\n\txrD = xvabsd.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.wu;\n\n#lasx.txt xvabsd.wu mask=0x74630000\t\n#0x74630000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.wu xrD, xrJ, xrK is op15_31=0xe8c6 & xrD & xrJ & xrK {\n\txrD = xvabsd.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvabsd.du;\n\n#lasx.txt xvabsd.du mask=0x74638000\t\n#0x74638000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvabsd.du xrD, xrJ, xrK is op15_31=0xe8c7 & xrD & xrJ & xrK {\n\txrD = xvabsd.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.b;\n\n#lasx.txt xvavg.b mask=0x74640000\t\n#0x74640000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.b xrD, xrJ, xrK is op15_31=0xe8c8 & xrD & xrJ & xrK {\n\txrD = xvavg.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.h;\n\n#lasx.txt xvavg.h mask=0x74648000\t\n#0x74648000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.h xrD, xrJ, xrK is op15_31=0xe8c9 & xrD & xrJ & xrK {\n\txrD = xvavg.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.w;\n\n#lasx.txt xvavg.w mask=0x74650000\t\n#0x74650000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.w xrD, xrJ, xrK is op15_31=0xe8ca & xrD & xrJ & xrK {\n\txrD = xvavg.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.d;\n\n#lasx.txt xvavg.d mask=0x74658000\t\n#0x74658000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.d xrD, xrJ, xrK is op15_31=0xe8cb & xrD & xrJ & xrK {\n\txrD = xvavg.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.bu;\n\n#lasx.txt xvavg.bu mask=0x74660000\t\n#0x74660000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.bu xrD, xrJ, xrK is op15_31=0xe8cc & xrD & xrJ & xrK {\n\txrD = xvavg.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.hu;\n\n#lasx.txt xvavg.hu mask=0x74668000\t\n#0x74668000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.hu xrD, xrJ, xrK is op15_31=0xe8cd & xrD & xrJ & xrK {\n\txrD = xvavg.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.wu;\n\n#lasx.txt xvavg.wu mask=0x74670000\t\n#0x74670000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.wu xrD, xrJ, xrK is op15_31=0xe8ce & xrD & xrJ & xrK {\n\txrD = xvavg.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavg.du;\n\n#lasx.txt xvavg.du mask=0x74678000\t\n#0x74678000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavg.du xrD, xrJ, xrK is op15_31=0xe8cf & xrD & xrJ & xrK {\n\txrD = xvavg.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.b;\n\n#lasx.txt xvavgr.b mask=0x74680000\t\n#0x74680000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.b xrD, xrJ, xrK is op15_31=0xe8d0 & xrD & xrJ & xrK {\n\txrD = xvavgr.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.h;\n\n#lasx.txt xvavgr.h mask=0x74688000\t\n#0x74688000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.h xrD, xrJ, xrK is op15_31=0xe8d1 & xrD & xrJ & xrK {\n\txrD = xvavgr.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.w;\n\n#lasx.txt xvavgr.w mask=0x74690000\t\n#0x74690000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.w xrD, xrJ, xrK is op15_31=0xe8d2 & xrD & xrJ & xrK {\n\txrD = xvavgr.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.d;\n\n#lasx.txt xvavgr.d mask=0x74698000\t\n#0x74698000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.d xrD, xrJ, xrK is op15_31=0xe8d3 & xrD & xrJ & xrK {\n\txrD = xvavgr.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.bu;\n\n#lasx.txt xvavgr.bu mask=0x746a0000\t\n#0x746a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.bu xrD, xrJ, xrK is op15_31=0xe8d4 & xrD & xrJ & xrK {\n\txrD = xvavgr.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.hu;\n\n#lasx.txt xvavgr.hu mask=0x746a8000\t\n#0x746a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.hu xrD, xrJ, xrK is op15_31=0xe8d5 & xrD & xrJ & xrK {\n\txrD = xvavgr.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.wu;\n\n#lasx.txt xvavgr.wu mask=0x746b0000\t\n#0x746b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.wu xrD, xrJ, xrK is op15_31=0xe8d6 & xrD & xrJ & xrK {\n\txrD = xvavgr.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvavgr.du;\n\n#lasx.txt xvavgr.du mask=0x746b8000\t\n#0x746b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvavgr.du xrD, xrJ, xrK is op15_31=0xe8d7 & xrD & xrJ & xrK {\n\txrD = xvavgr.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.b;\n\n#lasx.txt xvmax.b mask=0x74700000\t\n#0x74700000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.b xrD, xrJ, xrK is op15_31=0xe8e0 & xrD & xrJ & xrK {\n\txrD = xvmax.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.h;\n\n#lasx.txt xvmax.h mask=0x74708000\t\n#0x74708000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.h xrD, xrJ, xrK is op15_31=0xe8e1 & xrD & xrJ & xrK {\n\txrD = xvmax.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.w;\n\n#lasx.txt xvmax.w mask=0x74710000\t\n#0x74710000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.w xrD, xrJ, xrK is op15_31=0xe8e2 & xrD & xrJ & xrK {\n\txrD = xvmax.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.d;\n\n#lasx.txt xvmax.d mask=0x74718000\t\n#0x74718000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.d xrD, xrJ, xrK is op15_31=0xe8e3 & xrD & xrJ & xrK {\n\txrD = xvmax.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.b;\n\n#lasx.txt xvmin.b mask=0x74720000\t\n#0x74720000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.b xrD, xrJ, xrK is op15_31=0xe8e4 & xrD & xrJ & xrK {\n\txrD = xvmin.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.h;\n\n#lasx.txt xvmin.h mask=0x74728000\t\n#0x74728000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.h xrD, xrJ, xrK is op15_31=0xe8e5 & xrD & xrJ & xrK {\n\txrD = xvmin.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.w;\n\n#lasx.txt xvmin.w mask=0x74730000\t\n#0x74730000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.w xrD, xrJ, xrK is op15_31=0xe8e6 & xrD & xrJ & xrK {\n\txrD = xvmin.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.d;\n\n#lasx.txt xvmin.d mask=0x74738000\t\n#0x74738000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.d xrD, xrJ, xrK is op15_31=0xe8e7 & xrD & xrJ & xrK {\n\txrD = xvmin.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.bu;\n\n#lasx.txt xvmax.bu mask=0x74740000\t\n#0x74740000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.bu xrD, xrJ, xrK is op15_31=0xe8e8 & xrD & xrJ & xrK {\n\txrD = xvmax.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.hu;\n\n#lasx.txt xvmax.hu mask=0x74748000\t\n#0x74748000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.hu xrD, xrJ, xrK is op15_31=0xe8e9 & xrD & xrJ & xrK {\n\txrD = xvmax.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.wu;\n\n#lasx.txt xvmax.wu mask=0x74750000\t\n#0x74750000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.wu xrD, xrJ, xrK is op15_31=0xe8ea & xrD & xrJ & xrK {\n\txrD = xvmax.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmax.du;\n\n#lasx.txt xvmax.du mask=0x74758000\t\n#0x74758000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmax.du xrD, xrJ, xrK is op15_31=0xe8eb & xrD & xrJ & xrK {\n\txrD = xvmax.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.bu;\n\n#lasx.txt xvmin.bu mask=0x74760000\t\n#0x74760000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.bu xrD, xrJ, xrK is op15_31=0xe8ec & xrD & xrJ & xrK {\n\txrD = xvmin.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.hu;\n\n#lasx.txt xvmin.hu mask=0x74768000\t\n#0x74768000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.hu xrD, xrJ, xrK is op15_31=0xe8ed & xrD & xrJ & xrK {\n\txrD = xvmin.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.wu;\n\n#lasx.txt xvmin.wu mask=0x74770000\t\n#0x74770000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.wu xrD, xrJ, xrK is op15_31=0xe8ee & xrD & xrJ & xrK {\n\txrD = xvmin.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmin.du;\n\n#lasx.txt xvmin.du mask=0x74778000\t\n#0x74778000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmin.du xrD, xrJ, xrK is op15_31=0xe8ef & xrD & xrJ & xrK {\n\txrD = xvmin.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmul.b;\n\n#lasx.txt xvmul.b mask=0x74840000\t\n#0x74840000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmul.b xrD, xrJ, xrK is op15_31=0xe908 & xrD & xrJ & xrK {\n\txrD = xvmul.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmul.h;\n\n#lasx.txt xvmul.h mask=0x74848000\t\n#0x74848000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmul.h xrD, xrJ, xrK is op15_31=0xe909 & xrD & xrJ & xrK {\n\txrD = xvmul.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmul.w;\n\n#lasx.txt xvmul.w mask=0x74850000\t\n#0x74850000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmul.w xrD, xrJ, xrK is op15_31=0xe90a & xrD & xrJ & xrK {\n\txrD = xvmul.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmul.d;\n\n#lasx.txt xvmul.d mask=0x74858000\t\n#0x74858000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmul.d xrD, xrJ, xrK is op15_31=0xe90b & xrD & xrJ & xrK {\n\txrD = xvmul.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.b;\n\n#lasx.txt xvmuh.b mask=0x74860000\t\n#0x74860000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.b xrD, xrJ, xrK is op15_31=0xe90c & xrD & xrJ & xrK {\n\txrD = xvmuh.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.h;\n\n#lasx.txt xvmuh.h mask=0x74868000\t\n#0x74868000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.h xrD, xrJ, xrK is op15_31=0xe90d & xrD & xrJ & xrK {\n\txrD = xvmuh.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.w;\n\n#lasx.txt xvmuh.w mask=0x74870000\t\n#0x74870000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.w xrD, xrJ, xrK is op15_31=0xe90e & xrD & xrJ & xrK {\n\txrD = xvmuh.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.d;\n\n#lasx.txt xvmuh.d mask=0x74878000\t\n#0x74878000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.d xrD, xrJ, xrK is op15_31=0xe90f & xrD & xrJ & xrK {\n\txrD = xvmuh.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.bu;\n\n#lasx.txt xvmuh.bu mask=0x74880000\t\n#0x74880000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.bu xrD, xrJ, xrK is op15_31=0xe910 & xrD & xrJ & xrK {\n\txrD = xvmuh.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.hu;\n\n#lasx.txt xvmuh.hu mask=0x74888000\t\n#0x74888000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.hu xrD, xrJ, xrK is op15_31=0xe911 & xrD & xrJ & xrK {\n\txrD = xvmuh.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.wu;\n\n#lasx.txt xvmuh.wu mask=0x74890000\t\n#0x74890000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.wu xrD, xrJ, xrK is op15_31=0xe912 & xrD & xrJ & xrK {\n\txrD = xvmuh.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmuh.du;\n\n#lasx.txt xvmuh.du mask=0x74898000\t\n#0x74898000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmuh.du xrD, xrJ, xrK is op15_31=0xe913 & xrD & xrJ & xrK {\n\txrD = xvmuh.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.h.b;\n\n#lasx.txt xvmulwev.h.b mask=0x74900000\t\n#0x74900000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.h.b xrD, xrJ, xrK is op15_31=0xe920 & xrD & xrJ & xrK {\n\txrD = xvmulwev.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.w.h;\n\n#lasx.txt xvmulwev.w.h mask=0x74908000\t\n#0x74908000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.w.h xrD, xrJ, xrK is op15_31=0xe921 & xrD & xrJ & xrK {\n\txrD = xvmulwev.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.d.w;\n\n#lasx.txt xvmulwev.d.w mask=0x74910000\t\n#0x74910000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.d.w xrD, xrJ, xrK is op15_31=0xe922 & xrD & xrJ & xrK {\n\txrD = xvmulwev.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.q.d;\n\n#lasx.txt xvmulwev.q.d mask=0x74918000\t\n#0x74918000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.q.d xrD, xrJ, xrK is op15_31=0xe923 & xrD & xrJ & xrK {\n\txrD = xvmulwev.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.h.b;\n\n#lasx.txt xvmulwod.h.b mask=0x74920000\t\n#0x74920000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.h.b xrD, xrJ, xrK is op15_31=0xe924 & xrD & xrJ & xrK {\n\txrD = xvmulwod.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.w.h;\n\n#lasx.txt xvmulwod.w.h mask=0x74928000\t\n#0x74928000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.w.h xrD, xrJ, xrK is op15_31=0xe925 & xrD & xrJ & xrK {\n\txrD = xvmulwod.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.d.w;\n\n#lasx.txt xvmulwod.d.w mask=0x74930000\t\n#0x74930000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.d.w xrD, xrJ, xrK is op15_31=0xe926 & xrD & xrJ & xrK {\n\txrD = xvmulwod.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.q.d;\n\n#lasx.txt xvmulwod.q.d mask=0x74938000\t\n#0x74938000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.q.d xrD, xrJ, xrK is op15_31=0xe927 & xrD & xrJ & xrK {\n\txrD = xvmulwod.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.h.bu;\n\n#lasx.txt xvmulwev.h.bu mask=0x74980000\t\n#0x74980000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.h.bu xrD, xrJ, xrK is op15_31=0xe930 & xrD & xrJ & xrK {\n\txrD = xvmulwev.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.w.hu;\n\n#lasx.txt xvmulwev.w.hu mask=0x74988000\t\n#0x74988000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.w.hu xrD, xrJ, xrK is op15_31=0xe931 & xrD & xrJ & xrK {\n\txrD = xvmulwev.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.d.wu;\n\n#lasx.txt xvmulwev.d.wu mask=0x74990000\t\n#0x74990000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.d.wu xrD, xrJ, xrK is op15_31=0xe932 & xrD & xrJ & xrK {\n\txrD = xvmulwev.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.q.du;\n\n#lasx.txt xvmulwev.q.du mask=0x74998000\t\n#0x74998000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.q.du xrD, xrJ, xrK is op15_31=0xe933 & xrD & xrJ & xrK {\n\txrD = xvmulwev.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.h.bu;\n\n#lasx.txt xvmulwod.h.bu mask=0x749a0000\t\n#0x749a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.h.bu xrD, xrJ, xrK is op15_31=0xe934 & xrD & xrJ & xrK {\n\txrD = xvmulwod.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.w.hu;\n\n#lasx.txt xvmulwod.w.hu mask=0x749a8000\t\n#0x749a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.w.hu xrD, xrJ, xrK is op15_31=0xe935 & xrD & xrJ & xrK {\n\txrD = xvmulwod.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.d.wu;\n\n#lasx.txt xvmulwod.d.wu mask=0x749b0000\t\n#0x749b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.d.wu xrD, xrJ, xrK is op15_31=0xe936 & xrD & xrJ & xrK {\n\txrD = xvmulwod.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.q.du;\n\n#lasx.txt xvmulwod.q.du mask=0x749b8000\t\n#0x749b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.q.du xrD, xrJ, xrK is op15_31=0xe937 & xrD & xrJ & xrK {\n\txrD = xvmulwod.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.h.bu.b;\n\n#lasx.txt xvmulwev.h.bu.b mask=0x74a00000\t\n#0x74a00000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.h.bu.b xrD, xrJ, xrK is op15_31=0xe940 & xrD & xrJ & xrK {\n\txrD = xvmulwev.h.bu.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.w.hu.h;\n\n#lasx.txt xvmulwev.w.hu.h mask=0x74a08000\t\n#0x74a08000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.w.hu.h xrD, xrJ, xrK is op15_31=0xe941 & xrD & xrJ & xrK {\n\txrD = xvmulwev.w.hu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.d.wu.w;\n\n#lasx.txt xvmulwev.d.wu.w mask=0x74a10000\t\n#0x74a10000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.d.wu.w xrD, xrJ, xrK is op15_31=0xe942 & xrD & xrJ & xrK {\n\txrD = xvmulwev.d.wu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwev.q.du.d;\n\n#lasx.txt xvmulwev.q.du.d mask=0x74a18000\t\n#0x74a18000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwev.q.du.d xrD, xrJ, xrK is op15_31=0xe943 & xrD & xrJ & xrK {\n\txrD = xvmulwev.q.du.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.h.bu.b;\n\n#lasx.txt xvmulwod.h.bu.b mask=0x74a20000\t\n#0x74a20000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.h.bu.b xrD, xrJ, xrK is op15_31=0xe944 & xrD & xrJ & xrK {\n\txrD = xvmulwod.h.bu.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.w.hu.h;\n\n#lasx.txt xvmulwod.w.hu.h mask=0x74a28000\t\n#0x74a28000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.w.hu.h xrD, xrJ, xrK is op15_31=0xe945 & xrD & xrJ & xrK {\n\txrD = xvmulwod.w.hu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.d.wu.w;\n\n#lasx.txt xvmulwod.d.wu.w mask=0x74a30000\t\n#0x74a30000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.d.wu.w xrD, xrJ, xrK is op15_31=0xe946 & xrD & xrJ & xrK {\n\txrD = xvmulwod.d.wu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmulwod.q.du.d;\n\n#lasx.txt xvmulwod.q.du.d mask=0x74a38000\t\n#0x74a38000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmulwod.q.du.d xrD, xrJ, xrK is op15_31=0xe947 & xrD & xrJ & xrK {\n\txrD = xvmulwod.q.du.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmadd.b;\n\n#lasx.txt xvmadd.b mask=0x74a80000\t\n#0x74a80000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmadd.b xrD, xrJ, xrK is op15_31=0xe950 & xrD & xrJ & xrK {\n\txrD = xvmadd.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmadd.h;\n\n#lasx.txt xvmadd.h mask=0x74a88000\t\n#0x74a88000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmadd.h xrD, xrJ, xrK is op15_31=0xe951 & xrD & xrJ & xrK {\n\txrD = xvmadd.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmadd.w;\n\n#lasx.txt xvmadd.w mask=0x74a90000\t\n#0x74a90000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmadd.w xrD, xrJ, xrK is op15_31=0xe952 & xrD & xrJ & xrK {\n\txrD = xvmadd.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmadd.d;\n\n#lasx.txt xvmadd.d mask=0x74a98000\t\n#0x74a98000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmadd.d xrD, xrJ, xrK is op15_31=0xe953 & xrD & xrJ & xrK {\n\txrD = xvmadd.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmsub.b;\n\n#lasx.txt xvmsub.b mask=0x74aa0000\t\n#0x74aa0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmsub.b xrD, xrJ, xrK is op15_31=0xe954 & xrD & xrJ & xrK {\n\txrD = xvmsub.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmsub.h;\n\n#lasx.txt xvmsub.h mask=0x74aa8000\t\n#0x74aa8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmsub.h xrD, xrJ, xrK is op15_31=0xe955 & xrD & xrJ & xrK {\n\txrD = xvmsub.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmsub.w;\n\n#lasx.txt xvmsub.w mask=0x74ab0000\t\n#0x74ab0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmsub.w xrD, xrJ, xrK is op15_31=0xe956 & xrD & xrJ & xrK {\n\txrD = xvmsub.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmsub.d;\n\n#lasx.txt xvmsub.d mask=0x74ab8000\t\n#0x74ab8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmsub.d xrD, xrJ, xrK is op15_31=0xe957 & xrD & xrJ & xrK {\n\txrD = xvmsub.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.h.b;\n\n#lasx.txt xvmaddwev.h.b mask=0x74ac0000\t\n#0x74ac0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.h.b xrD, xrJ, xrK is op15_31=0xe958 & xrD & xrJ & xrK {\n\txrD = xvmaddwev.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.w.h;\n\n#lasx.txt xvmaddwev.w.h mask=0x74ac8000\t\n#0x74ac8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.w.h xrD, xrJ, xrK is op15_31=0xe959 & xrD & xrJ & xrK {\n\txrD = xvmaddwev.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.d.w;\n\n#lasx.txt xvmaddwev.d.w mask=0x74ad0000\t\n#0x74ad0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.d.w xrD, xrJ, xrK is op15_31=0xe95a & xrD & xrJ & xrK {\n\txrD = xvmaddwev.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.q.d;\n\n#lasx.txt xvmaddwev.q.d mask=0x74ad8000\t\n#0x74ad8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.q.d xrD, xrJ, xrK is op15_31=0xe95b & xrD & xrJ & xrK {\n\txrD = xvmaddwev.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.h.b;\n\n#lasx.txt xvmaddwod.h.b mask=0x74ae0000\t\n#0x74ae0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.h.b xrD, xrJ, xrK is op15_31=0xe95c & xrD & xrJ & xrK {\n\txrD = xvmaddwod.h.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.w.h;\n\n#lasx.txt xvmaddwod.w.h mask=0x74ae8000\t\n#0x74ae8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.w.h xrD, xrJ, xrK is op15_31=0xe95d & xrD & xrJ & xrK {\n\txrD = xvmaddwod.w.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.d.w;\n\n#lasx.txt xvmaddwod.d.w mask=0x74af0000\t\n#0x74af0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.d.w xrD, xrJ, xrK is op15_31=0xe95e & xrD & xrJ & xrK {\n\txrD = xvmaddwod.d.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.q.d;\n\n#lasx.txt xvmaddwod.q.d mask=0x74af8000\t\n#0x74af8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.q.d xrD, xrJ, xrK is op15_31=0xe95f & xrD & xrJ & xrK {\n\txrD = xvmaddwod.q.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.h.bu;\n\n#lasx.txt xvmaddwev.h.bu mask=0x74b40000\t\n#0x74b40000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.h.bu xrD, xrJ, xrK is op15_31=0xe968 & xrD & xrJ & xrK {\n\txrD = xvmaddwev.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.w.hu;\n\n#lasx.txt xvmaddwev.w.hu mask=0x74b48000\t\n#0x74b48000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.w.hu xrD, xrJ, xrK is op15_31=0xe969 & xrD & xrJ & xrK {\n\txrD = xvmaddwev.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.d.wu;\n\n#lasx.txt xvmaddwev.d.wu mask=0x74b50000\t\n#0x74b50000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.d.wu xrD, xrJ, xrK is op15_31=0xe96a & xrD & xrJ & xrK {\n\txrD = xvmaddwev.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.q.du;\n\n#lasx.txt xvmaddwev.q.du mask=0x74b58000\t\n#0x74b58000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.q.du xrD, xrJ, xrK is op15_31=0xe96b & xrD & xrJ & xrK {\n\txrD = xvmaddwev.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.h.bu;\n\n#lasx.txt xvmaddwod.h.bu mask=0x74b60000\t\n#0x74b60000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.h.bu xrD, xrJ, xrK is op15_31=0xe96c & xrD & xrJ & xrK {\n\txrD = xvmaddwod.h.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.w.hu;\n\n#lasx.txt xvmaddwod.w.hu mask=0x74b68000\t\n#0x74b68000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.w.hu xrD, xrJ, xrK is op15_31=0xe96d & xrD & xrJ & xrK {\n\txrD = xvmaddwod.w.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.d.wu;\n\n#lasx.txt xvmaddwod.d.wu mask=0x74b70000\t\n#0x74b70000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.d.wu xrD, xrJ, xrK is op15_31=0xe96e & xrD & xrJ & xrK {\n\txrD = xvmaddwod.d.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.q.du;\n\n#lasx.txt xvmaddwod.q.du mask=0x74b78000\t\n#0x74b78000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.q.du xrD, xrJ, xrK is op15_31=0xe96f & xrD & xrJ & xrK {\n\txrD = xvmaddwod.q.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.h.bu.b;\n\n#lasx.txt xvmaddwev.h.bu.b mask=0x74bc0000\t\n#0x74bc0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.h.bu.b xrD, xrJ, xrK is op15_31=0xe978 & xrD & xrJ & xrK {\n\txrD = xvmaddwev.h.bu.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.w.hu.h;\n\n#lasx.txt xvmaddwev.w.hu.h mask=0x74bc8000\t\n#0x74bc8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.w.hu.h xrD, xrJ, xrK is op15_31=0xe979 & xrD & xrJ & xrK {\n\txrD = xvmaddwev.w.hu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.d.wu.w;\n\n#lasx.txt xvmaddwev.d.wu.w mask=0x74bd0000\t\n#0x74bd0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.d.wu.w xrD, xrJ, xrK is op15_31=0xe97a & xrD & xrJ & xrK {\n\txrD = xvmaddwev.d.wu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwev.q.du.d;\n\n#lasx.txt xvmaddwev.q.du.d mask=0x74bd8000\t\n#0x74bd8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwev.q.du.d xrD, xrJ, xrK is op15_31=0xe97b & xrD & xrJ & xrK {\n\txrD = xvmaddwev.q.du.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.h.bu.b;\n\n#lasx.txt xvmaddwod.h.bu.b mask=0x74be0000\t\n#0x74be0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.h.bu.b xrD, xrJ, xrK is op15_31=0xe97c & xrD & xrJ & xrK {\n\txrD = xvmaddwod.h.bu.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.w.hu.h;\n\n#lasx.txt xvmaddwod.w.hu.h mask=0x74be8000\t\n#0x74be8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.w.hu.h xrD, xrJ, xrK is op15_31=0xe97d & xrD & xrJ & xrK {\n\txrD = xvmaddwod.w.hu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.d.wu.w;\n\n#lasx.txt xvmaddwod.d.wu.w mask=0x74bf0000\t\n#0x74bf0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.d.wu.w xrD, xrJ, xrK is op15_31=0xe97e & xrD & xrJ & xrK {\n\txrD = xvmaddwod.d.wu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmaddwod.q.du.d;\n\n#lasx.txt xvmaddwod.q.du.d mask=0x74bf8000\t\n#0x74bf8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmaddwod.q.du.d xrD, xrJ, xrK is op15_31=0xe97f & xrD & xrJ & xrK {\n\txrD = xvmaddwod.q.du.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.b;\n\n#lasx.txt xvdiv.b mask=0x74e00000\t\n#0x74e00000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.b xrD, xrJ, xrK is op15_31=0xe9c0 & xrD & xrJ & xrK {\n\txrD = xvdiv.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.h;\n\n#lasx.txt xvdiv.h mask=0x74e08000\t\n#0x74e08000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.h xrD, xrJ, xrK is op15_31=0xe9c1 & xrD & xrJ & xrK {\n\txrD = xvdiv.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.w;\n\n#lasx.txt xvdiv.w mask=0x74e10000\t\n#0x74e10000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.w xrD, xrJ, xrK is op15_31=0xe9c2 & xrD & xrJ & xrK {\n\txrD = xvdiv.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.d;\n\n#lasx.txt xvdiv.d mask=0x74e18000\t\n#0x74e18000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.d xrD, xrJ, xrK is op15_31=0xe9c3 & xrD & xrJ & xrK {\n\txrD = xvdiv.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.b;\n\n#lasx.txt xvmod.b mask=0x74e20000\t\n#0x74e20000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.b xrD, xrJ, xrK is op15_31=0xe9c4 & xrD & xrJ & xrK {\n\txrD = xvmod.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.h;\n\n#lasx.txt xvmod.h mask=0x74e28000\t\n#0x74e28000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.h xrD, xrJ, xrK is op15_31=0xe9c5 & xrD & xrJ & xrK {\n\txrD = xvmod.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.w;\n\n#lasx.txt xvmod.w mask=0x74e30000\t\n#0x74e30000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.w xrD, xrJ, xrK is op15_31=0xe9c6 & xrD & xrJ & xrK {\n\txrD = xvmod.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.d;\n\n#lasx.txt xvmod.d mask=0x74e38000\t\n#0x74e38000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.d xrD, xrJ, xrK is op15_31=0xe9c7 & xrD & xrJ & xrK {\n\txrD = xvmod.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.bu;\n\n#lasx.txt xvdiv.bu mask=0x74e40000\t\n#0x74e40000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.bu xrD, xrJ, xrK is op15_31=0xe9c8 & xrD & xrJ & xrK {\n\txrD = xvdiv.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.hu;\n\n#lasx.txt xvdiv.hu mask=0x74e48000\t\n#0x74e48000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.hu xrD, xrJ, xrK is op15_31=0xe9c9 & xrD & xrJ & xrK {\n\txrD = xvdiv.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.wu;\n\n#lasx.txt xvdiv.wu mask=0x74e50000\t\n#0x74e50000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.wu xrD, xrJ, xrK is op15_31=0xe9ca & xrD & xrJ & xrK {\n\txrD = xvdiv.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvdiv.du;\n\n#lasx.txt xvdiv.du mask=0x74e58000\t\n#0x74e58000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvdiv.du xrD, xrJ, xrK is op15_31=0xe9cb & xrD & xrJ & xrK {\n\txrD = xvdiv.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.bu;\n\n#lasx.txt xvmod.bu mask=0x74e60000\t\n#0x74e60000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.bu xrD, xrJ, xrK is op15_31=0xe9cc & xrD & xrJ & xrK {\n\txrD = xvmod.bu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.hu;\n\n#lasx.txt xvmod.hu mask=0x74e68000\t\n#0x74e68000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.hu xrD, xrJ, xrK is op15_31=0xe9cd & xrD & xrJ & xrK {\n\txrD = xvmod.hu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.wu;\n\n#lasx.txt xvmod.wu mask=0x74e70000\t\n#0x74e70000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.wu xrD, xrJ, xrK is op15_31=0xe9ce & xrD & xrJ & xrK {\n\txrD = xvmod.wu(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvmod.du;\n\n#lasx.txt xvmod.du mask=0x74e78000\t\n#0x74e78000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvmod.du xrD, xrJ, xrK is op15_31=0xe9cf & xrD & xrJ & xrK {\n\txrD = xvmod.du(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsll.b;\n\n#lasx.txt xvsll.b mask=0x74e80000\t\n#0x74e80000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsll.b xrD, xrJ, xrK is op15_31=0xe9d0 & xrD & xrJ & xrK {\n\txrD = xvsll.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsll.h;\n\n#lasx.txt xvsll.h mask=0x74e88000\t\n#0x74e88000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsll.h xrD, xrJ, xrK is op15_31=0xe9d1 & xrD & xrJ & xrK {\n\txrD = xvsll.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsll.w;\n\n#lasx.txt xvsll.w mask=0x74e90000\t\n#0x74e90000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsll.w xrD, xrJ, xrK is op15_31=0xe9d2 & xrD & xrJ & xrK {\n\txrD = xvsll.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsll.d;\n\n#lasx.txt xvsll.d mask=0x74e98000\t\n#0x74e98000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsll.d xrD, xrJ, xrK is op15_31=0xe9d3 & xrD & xrJ & xrK {\n\txrD = xvsll.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrl.b;\n\n#lasx.txt xvsrl.b mask=0x74ea0000\t\n#0x74ea0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrl.b xrD, xrJ, xrK is op15_31=0xe9d4 & xrD & xrJ & xrK {\n\txrD = xvsrl.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrl.h;\n\n#lasx.txt xvsrl.h mask=0x74ea8000\t\n#0x74ea8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrl.h xrD, xrJ, xrK is op15_31=0xe9d5 & xrD & xrJ & xrK {\n\txrD = xvsrl.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrl.w;\n\n#lasx.txt xvsrl.w mask=0x74eb0000\t\n#0x74eb0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrl.w xrD, xrJ, xrK is op15_31=0xe9d6 & xrD & xrJ & xrK {\n\txrD = xvsrl.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrl.d;\n\n#lasx.txt xvsrl.d mask=0x74eb8000\t\n#0x74eb8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrl.d xrD, xrJ, xrK is op15_31=0xe9d7 & xrD & xrJ & xrK {\n\txrD = xvsrl.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsra.b;\n\n#lasx.txt xvsra.b mask=0x74ec0000\t\n#0x74ec0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsra.b xrD, xrJ, xrK is op15_31=0xe9d8 & xrD & xrJ & xrK {\n\txrD = xvsra.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsra.h;\n\n#lasx.txt xvsra.h mask=0x74ec8000\t\n#0x74ec8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsra.h xrD, xrJ, xrK is op15_31=0xe9d9 & xrD & xrJ & xrK {\n\txrD = xvsra.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsra.w;\n\n#lasx.txt xvsra.w mask=0x74ed0000\t\n#0x74ed0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsra.w xrD, xrJ, xrK is op15_31=0xe9da & xrD & xrJ & xrK {\n\txrD = xvsra.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsra.d;\n\n#lasx.txt xvsra.d mask=0x74ed8000\t\n#0x74ed8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsra.d xrD, xrJ, xrK is op15_31=0xe9db & xrD & xrJ & xrK {\n\txrD = xvsra.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvrotr.b;\n\n#lasx.txt xvrotr.b mask=0x74ee0000\t\n#0x74ee0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvrotr.b xrD, xrJ, xrK is op15_31=0xe9dc & xrD & xrJ & xrK {\n\txrD = xvrotr.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvrotr.h;\n\n#lasx.txt xvrotr.h mask=0x74ee8000\t\n#0x74ee8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvrotr.h xrD, xrJ, xrK is op15_31=0xe9dd & xrD & xrJ & xrK {\n\txrD = xvrotr.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvrotr.w;\n\n#lasx.txt xvrotr.w mask=0x74ef0000\t\n#0x74ef0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvrotr.w xrD, xrJ, xrK is op15_31=0xe9de & xrD & xrJ & xrK {\n\txrD = xvrotr.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvrotr.d;\n\n#lasx.txt xvrotr.d mask=0x74ef8000\t\n#0x74ef8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvrotr.d xrD, xrJ, xrK is op15_31=0xe9df & xrD & xrJ & xrK {\n\txrD = xvrotr.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlr.b;\n\n#lasx.txt xvsrlr.b mask=0x74f00000\t\n#0x74f00000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlr.b xrD, xrJ, xrK is op15_31=0xe9e0 & xrD & xrJ & xrK {\n\txrD = xvsrlr.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlr.h;\n\n#lasx.txt xvsrlr.h mask=0x74f08000\t\n#0x74f08000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlr.h xrD, xrJ, xrK is op15_31=0xe9e1 & xrD & xrJ & xrK {\n\txrD = xvsrlr.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlr.w;\n\n#lasx.txt xvsrlr.w mask=0x74f10000\t\n#0x74f10000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlr.w xrD, xrJ, xrK is op15_31=0xe9e2 & xrD & xrJ & xrK {\n\txrD = xvsrlr.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlr.d;\n\n#lasx.txt xvsrlr.d mask=0x74f18000\t\n#0x74f18000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlr.d xrD, xrJ, xrK is op15_31=0xe9e3 & xrD & xrJ & xrK {\n\txrD = xvsrlr.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrar.b;\n\n#lasx.txt xvsrar.b mask=0x74f20000\t\n#0x74f20000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrar.b xrD, xrJ, xrK is op15_31=0xe9e4 & xrD & xrJ & xrK {\n\txrD = xvsrar.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrar.h;\n\n#lasx.txt xvsrar.h mask=0x74f28000\t\n#0x74f28000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrar.h xrD, xrJ, xrK is op15_31=0xe9e5 & xrD & xrJ & xrK {\n\txrD = xvsrar.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrar.w;\n\n#lasx.txt xvsrar.w mask=0x74f30000\t\n#0x74f30000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrar.w xrD, xrJ, xrK is op15_31=0xe9e6 & xrD & xrJ & xrK {\n\txrD = xvsrar.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrar.d;\n\n#lasx.txt xvsrar.d mask=0x74f38000\t\n#0x74f38000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrar.d xrD, xrJ, xrK is op15_31=0xe9e7 & xrD & xrJ & xrK {\n\txrD = xvsrar.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrln.b.h;\n\n#lasx.txt xvsrln.b.h mask=0x74f48000\t\n#0x74f48000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrln.b.h xrD, xrJ, xrK is op15_31=0xe9e9 & xrD & xrJ & xrK {\n\txrD = xvsrln.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrln.h.w;\n\n#lasx.txt xvsrln.h.w mask=0x74f50000\t\n#0x74f50000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrln.h.w xrD, xrJ, xrK is op15_31=0xe9ea & xrD & xrJ & xrK {\n\txrD = xvsrln.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrln.w.d;\n\n#lasx.txt xvsrln.w.d mask=0x74f58000\t\n#0x74f58000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrln.w.d xrD, xrJ, xrK is op15_31=0xe9eb & xrD & xrJ & xrK {\n\txrD = xvsrln.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsran.b.h;\n\n#lasx.txt xvsran.b.h mask=0x74f68000\t\n#0x74f68000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsran.b.h xrD, xrJ, xrK is op15_31=0xe9ed & xrD & xrJ & xrK {\n\txrD = xvsran.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsran.h.w;\n\n#lasx.txt xvsran.h.w mask=0x74f70000\t\n#0x74f70000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsran.h.w xrD, xrJ, xrK is op15_31=0xe9ee & xrD & xrJ & xrK {\n\txrD = xvsran.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsran.w.d;\n\n#lasx.txt xvsran.w.d mask=0x74f78000\t\n#0x74f78000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsran.w.d xrD, xrJ, xrK is op15_31=0xe9ef & xrD & xrJ & xrK {\n\txrD = xvsran.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlrn.b.h;\n\n#lasx.txt xvsrlrn.b.h mask=0x74f88000\t\n#0x74f88000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlrn.b.h xrD, xrJ, xrK is op15_31=0xe9f1 & xrD & xrJ & xrK {\n\txrD = xvsrlrn.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlrn.h.w;\n\n#lasx.txt xvsrlrn.h.w mask=0x74f90000\t\n#0x74f90000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlrn.h.w xrD, xrJ, xrK is op15_31=0xe9f2 & xrD & xrJ & xrK {\n\txrD = xvsrlrn.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrlrn.w.d;\n\n#lasx.txt xvsrlrn.w.d mask=0x74f98000\t\n#0x74f98000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrlrn.w.d xrD, xrJ, xrK is op15_31=0xe9f3 & xrD & xrJ & xrK {\n\txrD = xvsrlrn.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrarn.b.h;\n\n#lasx.txt xvsrarn.b.h mask=0x74fa8000\t\n#0x74fa8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrarn.b.h xrD, xrJ, xrK is op15_31=0xe9f5 & xrD & xrJ & xrK {\n\txrD = xvsrarn.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrarn.h.w;\n\n#lasx.txt xvsrarn.h.w mask=0x74fb0000\t\n#0x74fb0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrarn.h.w xrD, xrJ, xrK is op15_31=0xe9f6 & xrD & xrJ & xrK {\n\txrD = xvsrarn.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsrarn.w.d;\n\n#lasx.txt xvsrarn.w.d mask=0x74fb8000\t\n#0x74fb8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsrarn.w.d xrD, xrJ, xrK is op15_31=0xe9f7 & xrD & xrJ & xrK {\n\txrD = xvsrarn.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrln.b.h;\n\n#lasx.txt xvssrln.b.h mask=0x74fc8000\t\n#0x74fc8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrln.b.h xrD, xrJ, xrK is op15_31=0xe9f9 & xrD & xrJ & xrK {\n\txrD = xvssrln.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrln.h.w;\n\n#lasx.txt xvssrln.h.w mask=0x74fd0000\t\n#0x74fd0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrln.h.w xrD, xrJ, xrK is op15_31=0xe9fa & xrD & xrJ & xrK {\n\txrD = xvssrln.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrln.w.d;\n\n#lasx.txt xvssrln.w.d mask=0x74fd8000\t\n#0x74fd8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrln.w.d xrD, xrJ, xrK is op15_31=0xe9fb & xrD & xrJ & xrK {\n\txrD = xvssrln.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssran.b.h;\n\n#lasx.txt xvssran.b.h mask=0x74fe8000\t\n#0x74fe8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssran.b.h xrD, xrJ, xrK is op15_31=0xe9fd & xrD & xrJ & xrK {\n\txrD = xvssran.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssran.h.w;\n\n#lasx.txt xvssran.h.w mask=0x74ff0000\t\n#0x74ff0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssran.h.w xrD, xrJ, xrK is op15_31=0xe9fe & xrD & xrJ & xrK {\n\txrD = xvssran.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssran.w.d;\n\n#lasx.txt xvssran.w.d mask=0x74ff8000\t\n#0x74ff8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssran.w.d xrD, xrJ, xrK is op15_31=0xe9ff & xrD & xrJ & xrK {\n\txrD = xvssran.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrlrn.b.h;\n\n#lasx.txt xvssrlrn.b.h mask=0x75008000\t\n#0x75008000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrlrn.b.h xrD, xrJ, xrK is op15_31=0xea01 & xrD & xrJ & xrK {\n\txrD = xvssrlrn.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrlrn.h.w;\n\n#lasx.txt xvssrlrn.h.w mask=0x75010000\t\n#0x75010000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrlrn.h.w xrD, xrJ, xrK is op15_31=0xea02 & xrD & xrJ & xrK {\n\txrD = xvssrlrn.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrlrn.w.d;\n\n#lasx.txt xvssrlrn.w.d mask=0x75018000\t\n#0x75018000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrlrn.w.d xrD, xrJ, xrK is op15_31=0xea03 & xrD & xrJ & xrK {\n\txrD = xvssrlrn.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrarn.b.h;\n\n#lasx.txt xvssrarn.b.h mask=0x75028000\t\n#0x75028000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrarn.b.h xrD, xrJ, xrK is op15_31=0xea05 & xrD & xrJ & xrK {\n\txrD = xvssrarn.b.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrarn.h.w;\n\n#lasx.txt xvssrarn.h.w mask=0x75030000\t\n#0x75030000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrarn.h.w xrD, xrJ, xrK is op15_31=0xea06 & xrD & xrJ & xrK {\n\txrD = xvssrarn.h.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrarn.w.d;\n\n#lasx.txt xvssrarn.w.d mask=0x75038000\t\n#0x75038000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrarn.w.d xrD, xrJ, xrK is op15_31=0xea07 & xrD & xrJ & xrK {\n\txrD = xvssrarn.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrln.bu.h;\n\n#lasx.txt xvssrln.bu.h mask=0x75048000\t\n#0x75048000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrln.bu.h xrD, xrJ, xrK is op15_31=0xea09 & xrD & xrJ & xrK {\n\txrD = xvssrln.bu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrln.hu.w;\n\n#lasx.txt xvssrln.hu.w mask=0x75050000\t\n#0x75050000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrln.hu.w xrD, xrJ, xrK is op15_31=0xea0a & xrD & xrJ & xrK {\n\txrD = xvssrln.hu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrln.wu.d;\n\n#lasx.txt xvssrln.wu.d mask=0x75058000\t\n#0x75058000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrln.wu.d xrD, xrJ, xrK is op15_31=0xea0b & xrD & xrJ & xrK {\n\txrD = xvssrln.wu.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssran.bu.h;\n\n#lasx.txt xvssran.bu.h mask=0x75068000\t\n#0x75068000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssran.bu.h xrD, xrJ, xrK is op15_31=0xea0d & xrD & xrJ & xrK {\n\txrD = xvssran.bu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssran.hu.w;\n\n#lasx.txt xvssran.hu.w mask=0x75070000\t\n#0x75070000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssran.hu.w xrD, xrJ, xrK is op15_31=0xea0e & xrD & xrJ & xrK {\n\txrD = xvssran.hu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssran.wu.d;\n\n#lasx.txt xvssran.wu.d mask=0x75078000\t\n#0x75078000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssran.wu.d xrD, xrJ, xrK is op15_31=0xea0f & xrD & xrJ & xrK {\n\txrD = xvssran.wu.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrlrn.bu.h;\n\n#lasx.txt xvssrlrn.bu.h mask=0x75088000\t\n#0x75088000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrlrn.bu.h xrD, xrJ, xrK is op15_31=0xea11 & xrD & xrJ & xrK {\n\txrD = xvssrlrn.bu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrlrn.hu.w;\n\n#lasx.txt xvssrlrn.hu.w mask=0x75090000\t\n#0x75090000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrlrn.hu.w xrD, xrJ, xrK is op15_31=0xea12 & xrD & xrJ & xrK {\n\txrD = xvssrlrn.hu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrlrn.wu.d;\n\n#lasx.txt xvssrlrn.wu.d mask=0x75098000\t\n#0x75098000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrlrn.wu.d xrD, xrJ, xrK is op15_31=0xea13 & xrD & xrJ & xrK {\n\txrD = xvssrlrn.wu.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrarn.bu.h;\n\n#lasx.txt xvssrarn.bu.h mask=0x750a8000\t\n#0x750a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrarn.bu.h xrD, xrJ, xrK is op15_31=0xea15 & xrD & xrJ & xrK {\n\txrD = xvssrarn.bu.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrarn.hu.w;\n\n#lasx.txt xvssrarn.hu.w mask=0x750b0000\t\n#0x750b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrarn.hu.w xrD, xrJ, xrK is op15_31=0xea16 & xrD & xrJ & xrK {\n\txrD = xvssrarn.hu.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvssrarn.wu.d;\n\n#lasx.txt xvssrarn.wu.d mask=0x750b8000\t\n#0x750b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvssrarn.wu.d xrD, xrJ, xrK is op15_31=0xea17 & xrD & xrJ & xrK {\n\txrD = xvssrarn.wu.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitclr.b;\n\n#lasx.txt xvbitclr.b mask=0x750c0000\t\n#0x750c0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitclr.b xrD, xrJ, xrK is op15_31=0xea18 & xrD & xrJ & xrK {\n\txrD = xvbitclr.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitclr.h;\n\n#lasx.txt xvbitclr.h mask=0x750c8000\t\n#0x750c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitclr.h xrD, xrJ, xrK is op15_31=0xea19 & xrD & xrJ & xrK {\n\txrD = xvbitclr.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitclr.w;\n\n#lasx.txt xvbitclr.w mask=0x750d0000\t\n#0x750d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitclr.w xrD, xrJ, xrK is op15_31=0xea1a & xrD & xrJ & xrK {\n\txrD = xvbitclr.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitclr.d;\n\n#lasx.txt xvbitclr.d mask=0x750d8000\t\n#0x750d8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitclr.d xrD, xrJ, xrK is op15_31=0xea1b & xrD & xrJ & xrK {\n\txrD = xvbitclr.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitset.b;\n\n#lasx.txt xvbitset.b mask=0x750e0000\t\n#0x750e0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitset.b xrD, xrJ, xrK is op15_31=0xea1c & xrD & xrJ & xrK {\n\txrD = xvbitset.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitset.h;\n\n#lasx.txt xvbitset.h mask=0x750e8000\t\n#0x750e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitset.h xrD, xrJ, xrK is op15_31=0xea1d & xrD & xrJ & xrK {\n\txrD = xvbitset.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitset.w;\n\n#lasx.txt xvbitset.w mask=0x750f0000\t\n#0x750f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitset.w xrD, xrJ, xrK is op15_31=0xea1e & xrD & xrJ & xrK {\n\txrD = xvbitset.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitset.d;\n\n#lasx.txt xvbitset.d mask=0x750f8000\t\n#0x750f8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitset.d xrD, xrJ, xrK is op15_31=0xea1f & xrD & xrJ & xrK {\n\txrD = xvbitset.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitrev.b;\n\n#lasx.txt xvbitrev.b mask=0x75100000\t\n#0x75100000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitrev.b xrD, xrJ, xrK is op15_31=0xea20 & xrD & xrJ & xrK {\n\txrD = xvbitrev.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitrev.h;\n\n#lasx.txt xvbitrev.h mask=0x75108000\t\n#0x75108000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitrev.h xrD, xrJ, xrK is op15_31=0xea21 & xrD & xrJ & xrK {\n\txrD = xvbitrev.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitrev.w;\n\n#lasx.txt xvbitrev.w mask=0x75110000\t\n#0x75110000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitrev.w xrD, xrJ, xrK is op15_31=0xea22 & xrD & xrJ & xrK {\n\txrD = xvbitrev.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvbitrev.d;\n\n#lasx.txt xvbitrev.d mask=0x75118000\t\n#0x75118000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvbitrev.d xrD, xrJ, xrK is op15_31=0xea23 & xrD & xrJ & xrK {\n\txrD = xvbitrev.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackev.b;\n\n#lasx.txt xvpackev.b mask=0x75160000\t\n#0x75160000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackev.b xrD, xrJ, xrK is op15_31=0xea2c & xrD & xrJ & xrK {\n\txrD = xvpackev.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackev.h;\n\n#lasx.txt xvpackev.h mask=0x75168000\t\n#0x75168000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackev.h xrD, xrJ, xrK is op15_31=0xea2d & xrD & xrJ & xrK {\n\txrD = xvpackev.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackev.w;\n\n#lasx.txt xvpackev.w mask=0x75170000\t\n#0x75170000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackev.w xrD, xrJ, xrK is op15_31=0xea2e & xrD & xrJ & xrK {\n\txrD = xvpackev.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackev.d;\n\n#lasx.txt xvpackev.d mask=0x75178000\t\n#0x75178000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackev.d xrD, xrJ, xrK is op15_31=0xea2f & xrD & xrJ & xrK {\n\txrD = xvpackev.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackod.b;\n\n#lasx.txt xvpackod.b mask=0x75180000\t\n#0x75180000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackod.b xrD, xrJ, xrK is op15_31=0xea30 & xrD & xrJ & xrK {\n\txrD = xvpackod.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackod.h;\n\n#lasx.txt xvpackod.h mask=0x75188000\t\n#0x75188000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackod.h xrD, xrJ, xrK is op15_31=0xea31 & xrD & xrJ & xrK {\n\txrD = xvpackod.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackod.w;\n\n#lasx.txt xvpackod.w mask=0x75190000\t\n#0x75190000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackod.w xrD, xrJ, xrK is op15_31=0xea32 & xrD & xrJ & xrK {\n\txrD = xvpackod.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpackod.d;\n\n#lasx.txt xvpackod.d mask=0x75198000\t\n#0x75198000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpackod.d xrD, xrJ, xrK is op15_31=0xea33 & xrD & xrJ & xrK {\n\txrD = xvpackod.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvl.b;\n\n#lasx.txt xvilvl.b mask=0x751a0000\t\n#0x751a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvl.b xrD, xrJ, xrK is op15_31=0xea34 & xrD & xrJ & xrK {\n\txrD = xvilvl.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvl.h;\n\n#lasx.txt xvilvl.h mask=0x751a8000\t\n#0x751a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvl.h xrD, xrJ, xrK is op15_31=0xea35 & xrD & xrJ & xrK {\n\txrD = xvilvl.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvl.w;\n\n#lasx.txt xvilvl.w mask=0x751b0000\t\n#0x751b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvl.w xrD, xrJ, xrK is op15_31=0xea36 & xrD & xrJ & xrK {\n\txrD = xvilvl.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvl.d;\n\n#lasx.txt xvilvl.d mask=0x751b8000\t\n#0x751b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvl.d xrD, xrJ, xrK is op15_31=0xea37 & xrD & xrJ & xrK {\n\txrD = xvilvl.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvh.b;\n\n#lasx.txt xvilvh.b mask=0x751c0000\t\n#0x751c0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvh.b xrD, xrJ, xrK is op15_31=0xea38 & xrD & xrJ & xrK {\n\txrD = xvilvh.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvh.h;\n\n#lasx.txt xvilvh.h mask=0x751c8000\t\n#0x751c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvh.h xrD, xrJ, xrK is op15_31=0xea39 & xrD & xrJ & xrK {\n\txrD = xvilvh.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvh.w;\n\n#lasx.txt xvilvh.w mask=0x751d0000\t\n#0x751d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvh.w xrD, xrJ, xrK is op15_31=0xea3a & xrD & xrJ & xrK {\n\txrD = xvilvh.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvilvh.d;\n\n#lasx.txt xvilvh.d mask=0x751d8000\t\n#0x751d8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvilvh.d xrD, xrJ, xrK is op15_31=0xea3b & xrD & xrJ & xrK {\n\txrD = xvilvh.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickev.b;\n\n#lasx.txt xvpickev.b mask=0x751e0000\t\n#0x751e0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickev.b xrD, xrJ, xrK is op15_31=0xea3c & xrD & xrJ & xrK {\n\txrD = xvpickev.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickev.h;\n\n#lasx.txt xvpickev.h mask=0x751e8000\t\n#0x751e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickev.h xrD, xrJ, xrK is op15_31=0xea3d & xrD & xrJ & xrK {\n\txrD = xvpickev.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickev.w;\n\n#lasx.txt xvpickev.w mask=0x751f0000\t\n#0x751f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickev.w xrD, xrJ, xrK is op15_31=0xea3e & xrD & xrJ & xrK {\n\txrD = xvpickev.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickev.d;\n\n#lasx.txt xvpickev.d mask=0x751f8000\t\n#0x751f8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickev.d xrD, xrJ, xrK is op15_31=0xea3f & xrD & xrJ & xrK {\n\txrD = xvpickev.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickod.b;\n\n#lasx.txt xvpickod.b mask=0x75200000\t\n#0x75200000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickod.b xrD, xrJ, xrK is op15_31=0xea40 & xrD & xrJ & xrK {\n\txrD = xvpickod.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickod.h;\n\n#lasx.txt xvpickod.h mask=0x75208000\t\n#0x75208000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickod.h xrD, xrJ, xrK is op15_31=0xea41 & xrD & xrJ & xrK {\n\txrD = xvpickod.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickod.w;\n\n#lasx.txt xvpickod.w mask=0x75210000\t\n#0x75210000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickod.w xrD, xrJ, xrK is op15_31=0xea42 & xrD & xrJ & xrK {\n\txrD = xvpickod.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvpickod.d;\n\n#lasx.txt xvpickod.d mask=0x75218000\t\n#0x75218000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvpickod.d xrD, xrJ, xrK is op15_31=0xea43 & xrD & xrJ & xrK {\n\txrD = xvpickod.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvreplve.b;\n\n#lasx.txt xvreplve.b mask=0x75220000\t\n#0x75220000\t0xffff8000\tx0:5,x5:5, r10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0']\n:xvreplve.b xrD, xrJ, RKsrc is op15_31=0xea44 & xrD & xrJ & RKsrc {\n\txrD = xvreplve.b(xrD, xrJ, RKsrc);\n}\n\ndefine pcodeop xvreplve.h;\n\n#lasx.txt xvreplve.h mask=0x75228000\t\n#0x75228000\t0xffff8000\tx0:5,x5:5, r10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0']\n:xvreplve.h xrD, xrJ, RKsrc is op15_31=0xea45 & xrD & xrJ & RKsrc {\n\txrD = xvreplve.h(xrD, xrJ, RKsrc);\n}\n\ndefine pcodeop xvreplve.w;\n\n#lasx.txt xvreplve.w mask=0x75230000\t\n#0x75230000\t0xffff8000\tx0:5,x5:5, r10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0']\n:xvreplve.w xrD, xrJ, RKsrc is op15_31=0xea46 & xrD & xrJ & RKsrc {\n\txrD = xvreplve.w(xrD, xrJ, RKsrc);\n}\n\ndefine pcodeop xvreplve.d;\n\n#lasx.txt xvreplve.d mask=0x75238000\t\n#0x75238000\t0xffff8000\tx0:5,x5:5, r10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0']\n:xvreplve.d xrD, xrJ, RKsrc is op15_31=0xea47 & xrD & xrJ & RKsrc {\n\txrD = xvreplve.d(xrD, xrJ, RKsrc);\n}\n\ndefine pcodeop xvand.v;\n\n#lasx.txt xvand.v mask=0x75260000\t\n#0x75260000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvand.v xrD, xrJ, xrK is op15_31=0xea4c & xrD & xrJ & xrK {\n\txrD = xvand.v(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvor.v;\n\n#lasx.txt xvor.v mask=0x75268000\t\n#0x75268000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvor.v xrD, xrJ, xrK is op15_31=0xea4d & xrD & xrJ & xrK {\n\txrD = xvor.v(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvxor.v;\n\n#lasx.txt xvxor.v mask=0x75270000\t\n#0x75270000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvxor.v xrD, xrJ, xrK is op15_31=0xea4e & xrD & xrJ & xrK {\n\txrD = xvxor.v(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvnor.v;\n\n#lasx.txt xvnor.v mask=0x75278000\t\n#0x75278000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvnor.v xrD, xrJ, xrK is op15_31=0xea4f & xrD & xrJ & xrK {\n\txrD = xvnor.v(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvandn.v;\n\n#lasx.txt xvandn.v mask=0x75280000\t\n#0x75280000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvandn.v xrD, xrJ, xrK is op15_31=0xea50 & xrD & xrJ & xrK {\n\txrD = xvandn.v(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvorn.v;\n\n#lasx.txt xvorn.v mask=0x75288000\t\n#0x75288000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvorn.v xrD, xrJ, xrK is op15_31=0xea51 & xrD & xrJ & xrK {\n\txrD = xvorn.v(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfrstp.b;\n\n#lasx.txt xvfrstp.b mask=0x752b0000\t\n#0x752b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfrstp.b xrD, xrJ, xrK is op15_31=0xea56 & xrD & xrJ & xrK {\n\txrD = xvfrstp.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfrstp.h;\n\n#lasx.txt xvfrstp.h mask=0x752b8000\t\n#0x752b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfrstp.h xrD, xrJ, xrK is op15_31=0xea57 & xrD & xrJ & xrK {\n\txrD = xvfrstp.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvadd.q;\n\n#lasx.txt xvadd.q mask=0x752d0000\t\n#0x752d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvadd.q xrD, xrJ, xrK is op15_31=0xea5a & xrD & xrJ & xrK {\n\txrD = xvadd.q(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsub.q;\n\n#lasx.txt xvsub.q mask=0x752d8000\t\n#0x752d8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsub.q xrD, xrJ, xrK is op15_31=0xea5b & xrD & xrJ & xrK {\n\txrD = xvsub.q(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsigncov.b;\n\n#lasx.txt xvsigncov.b mask=0x752e0000\t\n#0x752e0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsigncov.b xrD, xrJ, xrK is op15_31=0xea5c & xrD & xrJ & xrK {\n\txrD = xvsigncov.b(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsigncov.h;\n\n#lasx.txt xvsigncov.h mask=0x752e8000\t\n#0x752e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsigncov.h xrD, xrJ, xrK is op15_31=0xea5d & xrD & xrJ & xrK {\n\txrD = xvsigncov.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsigncov.w;\n\n#lasx.txt xvsigncov.w mask=0x752f0000\t\n#0x752f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsigncov.w xrD, xrJ, xrK is op15_31=0xea5e & xrD & xrJ & xrK {\n\txrD = xvsigncov.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvsigncov.d;\n\n#lasx.txt xvsigncov.d mask=0x752f8000\t\n#0x752f8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvsigncov.d xrD, xrJ, xrK is op15_31=0xea5f & xrD & xrJ & xrK {\n\txrD = xvsigncov.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfadd.s;\n\n#lasx.txt xvfadd.s mask=0x75308000\t\n#0x75308000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfadd.s xrD, xrJ, xrK is op15_31=0xea61 & xrD & xrJ & xrK {\n\txrD = xvfadd.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfadd.d;\n\n#lasx.txt xvfadd.d mask=0x75310000\t\n#0x75310000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfadd.d xrD, xrJ, xrK is op15_31=0xea62 & xrD & xrJ & xrK {\n\txrD = xvfadd.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfsub.s;\n\n#lasx.txt xvfsub.s mask=0x75328000\t\n#0x75328000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfsub.s xrD, xrJ, xrK is op15_31=0xea65 & xrD & xrJ & xrK {\n\txrD = xvfsub.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfsub.d;\n\n#lasx.txt xvfsub.d mask=0x75330000\t\n#0x75330000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfsub.d xrD, xrJ, xrK is op15_31=0xea66 & xrD & xrJ & xrK {\n\txrD = xvfsub.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmul.s;\n\n#lasx.txt xvfmul.s mask=0x75388000\t\n#0x75388000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmul.s xrD, xrJ, xrK is op15_31=0xea71 & xrD & xrJ & xrK {\n\txrD = xvfmul.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmul.d;\n\n#lasx.txt xvfmul.d mask=0x75390000\t\n#0x75390000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmul.d xrD, xrJ, xrK is op15_31=0xea72 & xrD & xrJ & xrK {\n\txrD = xvfmul.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfdiv.s;\n\n#lasx.txt xvfdiv.s mask=0x753a8000\t\n#0x753a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfdiv.s xrD, xrJ, xrK is op15_31=0xea75 & xrD & xrJ & xrK {\n\txrD = xvfdiv.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfdiv.d;\n\n#lasx.txt xvfdiv.d mask=0x753b0000\t\n#0x753b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfdiv.d xrD, xrJ, xrK is op15_31=0xea76 & xrD & xrJ & xrK {\n\txrD = xvfdiv.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmax.s;\n\n#lasx.txt xvfmax.s mask=0x753c8000\t\n#0x753c8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmax.s xrD, xrJ, xrK is op15_31=0xea79 & xrD & xrJ & xrK {\n\txrD = xvfmax.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmax.d;\n\n#lasx.txt xvfmax.d mask=0x753d0000\t\n#0x753d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmax.d xrD, xrJ, xrK is op15_31=0xea7a & xrD & xrJ & xrK {\n\txrD = xvfmax.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmin.s;\n\n#lasx.txt xvfmin.s mask=0x753e8000\t\n#0x753e8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmin.s xrD, xrJ, xrK is op15_31=0xea7d & xrD & xrJ & xrK {\n\txrD = xvfmin.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmin.d;\n\n#lasx.txt xvfmin.d mask=0x753f0000\t\n#0x753f0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmin.d xrD, xrJ, xrK is op15_31=0xea7e & xrD & xrJ & xrK {\n\txrD = xvfmin.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmaxa.s;\n\n#lasx.txt xvfmaxa.s mask=0x75408000\t\n#0x75408000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmaxa.s xrD, xrJ, xrK is op15_31=0xea81 & xrD & xrJ & xrK {\n\txrD = xvfmaxa.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmaxa.d;\n\n#lasx.txt xvfmaxa.d mask=0x75410000\t\n#0x75410000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmaxa.d xrD, xrJ, xrK is op15_31=0xea82 & xrD & xrJ & xrK {\n\txrD = xvfmaxa.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmina.s;\n\n#lasx.txt xvfmina.s mask=0x75428000\t\n#0x75428000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmina.s xrD, xrJ, xrK is op15_31=0xea85 & xrD & xrJ & xrK {\n\txrD = xvfmina.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfmina.d;\n\n#lasx.txt xvfmina.d mask=0x75430000\t\n#0x75430000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfmina.d xrD, xrJ, xrK is op15_31=0xea86 & xrD & xrJ & xrK {\n\txrD = xvfmina.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcvt.h.s;\n\n#lasx.txt xvfcvt.h.s mask=0x75460000\t\n#0x75460000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcvt.h.s xrD, xrJ, xrK is op15_31=0xea8c & xrD & xrJ & xrK {\n\txrD = xvfcvt.h.s(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvfcvt.s.d;\n\n#lasx.txt xvfcvt.s.d mask=0x75468000\t\n#0x75468000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvfcvt.s.d xrD, xrJ, xrK is op15_31=0xea8d & xrD & xrJ & xrK {\n\txrD = xvfcvt.s.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvffint.s.l;\n\n#lasx.txt xvffint.s.l mask=0x75480000\t\n#0x75480000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvffint.s.l xrD, xrJ, xrK is op15_31=0xea90 & xrD & xrJ & xrK {\n\txrD = xvffint.s.l(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvftint.w.d;\n\n#lasx.txt xvftint.w.d mask=0x75498000\t\n#0x75498000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvftint.w.d xrD, xrJ, xrK is op15_31=0xea93 & xrD & xrJ & xrK {\n\txrD = xvftint.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvftintrm.w.d;\n\n#lasx.txt xvftintrm.w.d mask=0x754a0000\t\n#0x754a0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvftintrm.w.d xrD, xrJ, xrK is op15_31=0xea94 & xrD & xrJ & xrK {\n\txrD = xvftintrm.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvftintrp.w.d;\n\n#lasx.txt xvftintrp.w.d mask=0x754a8000\t\n#0x754a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvftintrp.w.d xrD, xrJ, xrK is op15_31=0xea95 & xrD & xrJ & xrK {\n\txrD = xvftintrp.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvftintrz.w.d;\n\n#lasx.txt xvftintrz.w.d mask=0x754b0000\t\n#0x754b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvftintrz.w.d xrD, xrJ, xrK is op15_31=0xea96 & xrD & xrJ & xrK {\n\txrD = xvftintrz.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvftintrne.w.d;\n\n#lasx.txt xvftintrne.w.d mask=0x754b8000\t\n#0x754b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvftintrne.w.d xrD, xrJ, xrK is op15_31=0xea97 & xrD & xrJ & xrK {\n\txrD = xvftintrne.w.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvshuf.h;\n\n#lasx.txt xvshuf.h mask=0x757a8000\t\n#0x757a8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvshuf.h xrD, xrJ, xrK is op15_31=0xeaf5 & xrD & xrJ & xrK {\n\txrD = xvshuf.h(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvshuf.w;\n\n#lasx.txt xvshuf.w mask=0x757b0000\t\n#0x757b0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvshuf.w xrD, xrJ, xrK is op15_31=0xeaf6 & xrD & xrJ & xrK {\n\txrD = xvshuf.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvshuf.d;\n\n#lasx.txt xvshuf.d mask=0x757b8000\t\n#0x757b8000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvshuf.d xrD, xrJ, xrK is op15_31=0xeaf7 & xrD & xrJ & xrK {\n\txrD = xvshuf.d(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvperm.w;\n\n#lasx.txt xvperm.w mask=0x757d0000\t\n#0x757d0000\t0xffff8000\tx0:5,x5:5,x10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0']\n:xvperm.w xrD, xrJ, xrK is op15_31=0xeafa & xrD & xrJ & xrK {\n\txrD = xvperm.w(xrD, xrJ, xrK);\n}\n\ndefine pcodeop xvseqi.b;\n\n#lasx.txt xvseqi.b mask=0x76800000\t\n#0x76800000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvseqi.b xrD, xrJ,simm10_5 is op15_31=0xed00 & xrD & xrJ & simm10_5 {\n\txrD = xvseqi.b(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvseqi.h;\n\n#lasx.txt xvseqi.h mask=0x76808000\t\n#0x76808000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvseqi.h xrD, xrJ,simm10_5 is op15_31=0xed01 & xrD & xrJ & simm10_5 {\n\txrD = xvseqi.h(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvseqi.w;\n\n#lasx.txt xvseqi.w mask=0x76810000\t\n#0x76810000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvseqi.w xrD, xrJ,simm10_5 is op15_31=0xed02 & xrD & xrJ & simm10_5 {\n\txrD = xvseqi.w(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvseqi.d;\n\n#lasx.txt xvseqi.d mask=0x76818000\t\n#0x76818000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvseqi.d xrD, xrJ,simm10_5 is op15_31=0xed03 & xrD & xrJ & simm10_5 {\n\txrD = xvseqi.d(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.b;\n\n#lasx.txt xvslei.b mask=0x76820000\t\n#0x76820000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslei.b xrD, xrJ,simm10_5 is op15_31=0xed04 & xrD & xrJ & simm10_5 {\n\txrD = xvslei.b(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.h;\n\n#lasx.txt xvslei.h mask=0x76828000\t\n#0x76828000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslei.h xrD, xrJ,simm10_5 is op15_31=0xed05 & xrD & xrJ & simm10_5 {\n\txrD = xvslei.h(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.w;\n\n#lasx.txt xvslei.w mask=0x76830000\t\n#0x76830000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslei.w xrD, xrJ,simm10_5 is op15_31=0xed06 & xrD & xrJ & simm10_5 {\n\txrD = xvslei.w(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.d;\n\n#lasx.txt xvslei.d mask=0x76838000\t\n#0x76838000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslei.d xrD, xrJ,simm10_5 is op15_31=0xed07 & xrD & xrJ & simm10_5 {\n\txrD = xvslei.d(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.bu;\n\n#lasx.txt xvslei.bu mask=0x76840000\t\n#0x76840000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslei.bu xrD, xrJ, imm10_5 is op15_31=0xed08 & xrD & xrJ & imm10_5 {\n\txrD = xvslei.bu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.hu;\n\n#lasx.txt xvslei.hu mask=0x76848000\t\n#0x76848000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslei.hu xrD, xrJ, imm10_5 is op15_31=0xed09 & xrD & xrJ & imm10_5 {\n\txrD = xvslei.hu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.wu;\n\n#lasx.txt xvslei.wu mask=0x76850000\t\n#0x76850000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslei.wu xrD, xrJ, imm10_5 is op15_31=0xed0a & xrD & xrJ & imm10_5 {\n\txrD = xvslei.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslei.du;\n\n#lasx.txt xvslei.du mask=0x76858000\t\n#0x76858000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslei.du xrD, xrJ, imm10_5 is op15_31=0xed0b & xrD & xrJ & imm10_5 {\n\txrD = xvslei.du(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.b;\n\n#lasx.txt xvslti.b mask=0x76860000\t\n#0x76860000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslti.b xrD, xrJ,simm10_5 is op15_31=0xed0c & xrD & xrJ & simm10_5 {\n\txrD = xvslti.b(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.h;\n\n#lasx.txt xvslti.h mask=0x76868000\t\n#0x76868000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslti.h xrD, xrJ,simm10_5 is op15_31=0xed0d & xrD & xrJ & simm10_5 {\n\txrD = xvslti.h(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.w;\n\n#lasx.txt xvslti.w mask=0x76870000\t\n#0x76870000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslti.w xrD, xrJ,simm10_5 is op15_31=0xed0e & xrD & xrJ & simm10_5 {\n\txrD = xvslti.w(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.d;\n\n#lasx.txt xvslti.d mask=0x76878000\t\n#0x76878000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvslti.d xrD, xrJ,simm10_5 is op15_31=0xed0f & xrD & xrJ & simm10_5 {\n\txrD = xvslti.d(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.bu;\n\n#lasx.txt xvslti.bu mask=0x76880000\t\n#0x76880000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslti.bu xrD, xrJ, imm10_5 is op15_31=0xed10 & xrD & xrJ & imm10_5 {\n\txrD = xvslti.bu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.hu;\n\n#lasx.txt xvslti.hu mask=0x76888000\t\n#0x76888000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslti.hu xrD, xrJ, imm10_5 is op15_31=0xed11 & xrD & xrJ & imm10_5 {\n\txrD = xvslti.hu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.wu;\n\n#lasx.txt xvslti.wu mask=0x76890000\t\n#0x76890000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslti.wu xrD, xrJ, imm10_5 is op15_31=0xed12 & xrD & xrJ & imm10_5 {\n\txrD = xvslti.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslti.du;\n\n#lasx.txt xvslti.du mask=0x76898000\t\n#0x76898000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslti.du xrD, xrJ, imm10_5 is op15_31=0xed13 & xrD & xrJ & imm10_5 {\n\txrD = xvslti.du(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvaddi.bu;\n\n#lasx.txt xvaddi.bu mask=0x768a0000\t\n#0x768a0000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvaddi.bu xrD, xrJ, imm10_5 is op15_31=0xed14 & xrD & xrJ & imm10_5 {\n\txrD = xvaddi.bu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvaddi.hu;\n\n#lasx.txt xvaddi.hu mask=0x768a8000\t\n#0x768a8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvaddi.hu xrD, xrJ, imm10_5 is op15_31=0xed15 & xrD & xrJ & imm10_5 {\n\txrD = xvaddi.hu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvaddi.wu;\n\n#lasx.txt xvaddi.wu mask=0x768b0000\t\n#0x768b0000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvaddi.wu xrD, xrJ, imm10_5 is op15_31=0xed16 & xrD & xrJ & imm10_5 {\n\txrD = xvaddi.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvaddi.du;\n\n#lasx.txt xvaddi.du mask=0x768b8000\t\n#0x768b8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvaddi.du xrD, xrJ, imm10_5 is op15_31=0xed17 & xrD & xrJ & imm10_5 {\n\txrD = xvaddi.du(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsubi.bu;\n\n#lasx.txt xvsubi.bu mask=0x768c0000\t\n#0x768c0000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsubi.bu xrD, xrJ, imm10_5 is op15_31=0xed18 & xrD & xrJ & imm10_5 {\n\txrD = xvsubi.bu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsubi.hu;\n\n#lasx.txt xvsubi.hu mask=0x768c8000\t\n#0x768c8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsubi.hu xrD, xrJ, imm10_5 is op15_31=0xed19 & xrD & xrJ & imm10_5 {\n\txrD = xvsubi.hu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsubi.wu;\n\n#lasx.txt xvsubi.wu mask=0x768d0000\t\n#0x768d0000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsubi.wu xrD, xrJ, imm10_5 is op15_31=0xed1a & xrD & xrJ & imm10_5 {\n\txrD = xvsubi.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsubi.du;\n\n#lasx.txt xvsubi.du mask=0x768d8000\t\n#0x768d8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsubi.du xrD, xrJ, imm10_5 is op15_31=0xed1b & xrD & xrJ & imm10_5 {\n\txrD = xvsubi.du(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvbsll.v;\n\n#lasx.txt xvbsll.v mask=0x768e0000\t\n#0x768e0000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvbsll.v xrD, xrJ, imm10_5 is op15_31=0xed1c & xrD & xrJ & imm10_5 {\n\txrD = xvbsll.v(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvbsrl.v;\n\n#lasx.txt xvbsrl.v mask=0x768e8000\t\n#0x768e8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvbsrl.v xrD, xrJ, imm10_5 is op15_31=0xed1d & xrD & xrJ & imm10_5 {\n\txrD = xvbsrl.v(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.b;\n\n#lasx.txt xvmaxi.b mask=0x76900000\t\n#0x76900000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmaxi.b xrD, xrJ,simm10_5 is op15_31=0xed20 & xrD & xrJ & simm10_5 {\n\txrD = xvmaxi.b(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.h;\n\n#lasx.txt xvmaxi.h mask=0x76908000\t\n#0x76908000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmaxi.h xrD, xrJ,simm10_5 is op15_31=0xed21 & xrD & xrJ & simm10_5 {\n\txrD = xvmaxi.h(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.w;\n\n#lasx.txt xvmaxi.w mask=0x76910000\t\n#0x76910000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmaxi.w xrD, xrJ,simm10_5 is op15_31=0xed22 & xrD & xrJ & simm10_5 {\n\txrD = xvmaxi.w(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.d;\n\n#lasx.txt xvmaxi.d mask=0x76918000\t\n#0x76918000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmaxi.d xrD, xrJ,simm10_5 is op15_31=0xed23 & xrD & xrJ & simm10_5 {\n\txrD = xvmaxi.d(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.b;\n\n#lasx.txt xvmini.b mask=0x76920000\t\n#0x76920000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmini.b xrD, xrJ,simm10_5 is op15_31=0xed24 & xrD & xrJ & simm10_5 {\n\txrD = xvmini.b(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.h;\n\n#lasx.txt xvmini.h mask=0x76928000\t\n#0x76928000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmini.h xrD, xrJ,simm10_5 is op15_31=0xed25 & xrD & xrJ & simm10_5 {\n\txrD = xvmini.h(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.w;\n\n#lasx.txt xvmini.w mask=0x76930000\t\n#0x76930000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmini.w xrD, xrJ,simm10_5 is op15_31=0xed26 & xrD & xrJ & simm10_5 {\n\txrD = xvmini.w(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.d;\n\n#lasx.txt xvmini.d mask=0x76938000\t\n#0x76938000\t0xffff8000\tx0:5,x5:5,s10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0']\n:xvmini.d xrD, xrJ,simm10_5 is op15_31=0xed27 & xrD & xrJ & simm10_5 {\n\txrD = xvmini.d(xrD, xrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.bu;\n\n#lasx.txt xvmaxi.bu mask=0x76940000\t\n#0x76940000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmaxi.bu xrD, xrJ, imm10_5 is op15_31=0xed28 & xrD & xrJ & imm10_5 {\n\txrD = xvmaxi.bu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.hu;\n\n#lasx.txt xvmaxi.hu mask=0x76948000\t\n#0x76948000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmaxi.hu xrD, xrJ, imm10_5 is op15_31=0xed29 & xrD & xrJ & imm10_5 {\n\txrD = xvmaxi.hu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.wu;\n\n#lasx.txt xvmaxi.wu mask=0x76950000\t\n#0x76950000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmaxi.wu xrD, xrJ, imm10_5 is op15_31=0xed2a & xrD & xrJ & imm10_5 {\n\txrD = xvmaxi.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmaxi.du;\n\n#lasx.txt xvmaxi.du mask=0x76958000\t\n#0x76958000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmaxi.du xrD, xrJ, imm10_5 is op15_31=0xed2b & xrD & xrJ & imm10_5 {\n\txrD = xvmaxi.du(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.bu;\n\n#lasx.txt xvmini.bu mask=0x76960000\t\n#0x76960000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmini.bu xrD, xrJ, imm10_5 is op15_31=0xed2c & xrD & xrJ & imm10_5 {\n\txrD = xvmini.bu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.hu;\n\n#lasx.txt xvmini.hu mask=0x76968000\t\n#0x76968000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmini.hu xrD, xrJ, imm10_5 is op15_31=0xed2d & xrD & xrJ & imm10_5 {\n\txrD = xvmini.hu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.wu;\n\n#lasx.txt xvmini.wu mask=0x76970000\t\n#0x76970000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmini.wu xrD, xrJ, imm10_5 is op15_31=0xed2e & xrD & xrJ & imm10_5 {\n\txrD = xvmini.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvmini.du;\n\n#lasx.txt xvmini.du mask=0x76978000\t\n#0x76978000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvmini.du xrD, xrJ, imm10_5 is op15_31=0xed2f & xrD & xrJ & imm10_5 {\n\txrD = xvmini.du(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvfrstpi.b;\n\n#lasx.txt xvfrstpi.b mask=0x769a0000\t\n#0x769a0000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvfrstpi.b xrD, xrJ, imm10_5 is op15_31=0xed34 & xrD & xrJ & imm10_5 {\n\txrD = xvfrstpi.b(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvfrstpi.h;\n\n#lasx.txt xvfrstpi.h mask=0x769a8000\t\n#0x769a8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvfrstpi.h xrD, xrJ, imm10_5 is op15_31=0xed35 & xrD & xrJ & imm10_5 {\n\txrD = xvfrstpi.h(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvclo.b;\n\n#lasx.txt xvclo.b mask=0x769c0000\t\n#0x769c0000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclo.b xrD, xrJ is op10_31=0x1da700 & xrD & xrJ {\n\txrD = xvclo.b(xrD, xrJ);\n}\n\ndefine pcodeop xvclo.h;\n\n#lasx.txt xvclo.h mask=0x769c0400\t\n#0x769c0400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclo.h xrD, xrJ is op10_31=0x1da701 & xrD & xrJ {\n\txrD = xvclo.h(xrD, xrJ);\n}\n\ndefine pcodeop xvclo.w;\n\n#lasx.txt xvclo.w mask=0x769c0800\t\n#0x769c0800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclo.w xrD, xrJ is op10_31=0x1da702 & xrD & xrJ {\n\txrD = xvclo.w(xrD, xrJ);\n}\n\ndefine pcodeop xvclo.d;\n\n#lasx.txt xvclo.d mask=0x769c0c00\t\n#0x769c0c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclo.d xrD, xrJ is op10_31=0x1da703 & xrD & xrJ {\n\txrD = xvclo.d(xrD, xrJ);\n}\n\ndefine pcodeop xvclz.b;\n\n#lasx.txt xvclz.b mask=0x769c1000\t\n#0x769c1000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclz.b xrD, xrJ is op10_31=0x1da704 & xrD & xrJ {\n\txrD = xvclz.b(xrD, xrJ);\n}\n\ndefine pcodeop xvclz.h;\n\n#lasx.txt xvclz.h mask=0x769c1400\t\n#0x769c1400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclz.h xrD, xrJ is op10_31=0x1da705 & xrD & xrJ {\n\txrD = xvclz.h(xrD, xrJ);\n}\n\ndefine pcodeop xvclz.w;\n\n#lasx.txt xvclz.w mask=0x769c1800\t\n#0x769c1800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclz.w xrD, xrJ is op10_31=0x1da706 & xrD & xrJ {\n\txrD = xvclz.w(xrD, xrJ);\n}\n\ndefine pcodeop xvclz.d;\n\n#lasx.txt xvclz.d mask=0x769c1c00\t\n#0x769c1c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvclz.d xrD, xrJ is op10_31=0x1da707 & xrD & xrJ {\n\txrD = xvclz.d(xrD, xrJ);\n}\n\ndefine pcodeop xvpcnt.b;\n\n#lasx.txt xvpcnt.b mask=0x769c2000\t\n#0x769c2000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvpcnt.b xrD, xrJ is op10_31=0x1da708 & xrD & xrJ {\n\txrD = xvpcnt.b(xrD, xrJ);\n}\n\ndefine pcodeop xvpcnt.h;\n\n#lasx.txt xvpcnt.h mask=0x769c2400\t\n#0x769c2400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvpcnt.h xrD, xrJ is op10_31=0x1da709 & xrD & xrJ {\n\txrD = xvpcnt.h(xrD, xrJ);\n}\n\ndefine pcodeop xvpcnt.w;\n\n#lasx.txt xvpcnt.w mask=0x769c2800\t\n#0x769c2800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvpcnt.w xrD, xrJ is op10_31=0x1da70a & xrD & xrJ {\n\txrD = xvpcnt.w(xrD, xrJ);\n}\n\ndefine pcodeop xvpcnt.d;\n\n#lasx.txt xvpcnt.d mask=0x769c2c00\t\n#0x769c2c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvpcnt.d xrD, xrJ is op10_31=0x1da70b & xrD & xrJ {\n\txrD = xvpcnt.d(xrD, xrJ);\n}\n\ndefine pcodeop xvneg.b;\n\n#lasx.txt xvneg.b mask=0x769c3000\t\n#0x769c3000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvneg.b xrD, xrJ is op10_31=0x1da70c & xrD & xrJ {\n\txrD = xvneg.b(xrD, xrJ);\n}\n\ndefine pcodeop xvneg.h;\n\n#lasx.txt xvneg.h mask=0x769c3400\t\n#0x769c3400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvneg.h xrD, xrJ is op10_31=0x1da70d & xrD & xrJ {\n\txrD = xvneg.h(xrD, xrJ);\n}\n\ndefine pcodeop xvneg.w;\n\n#lasx.txt xvneg.w mask=0x769c3800\t\n#0x769c3800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvneg.w xrD, xrJ is op10_31=0x1da70e & xrD & xrJ {\n\txrD = xvneg.w(xrD, xrJ);\n}\n\ndefine pcodeop xvneg.d;\n\n#lasx.txt xvneg.d mask=0x769c3c00\t\n#0x769c3c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvneg.d xrD, xrJ is op10_31=0x1da70f & xrD & xrJ {\n\txrD = xvneg.d(xrD, xrJ);\n}\n\ndefine pcodeop xvmskltz.b;\n\n#lasx.txt xvmskltz.b mask=0x769c4000\t\n#0x769c4000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvmskltz.b xrD, xrJ is op10_31=0x1da710 & xrD & xrJ {\n\txrD = xvmskltz.b(xrD, xrJ);\n}\n\ndefine pcodeop xvmskltz.h;\n\n#lasx.txt xvmskltz.h mask=0x769c4400\t\n#0x769c4400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvmskltz.h xrD, xrJ is op10_31=0x1da711 & xrD & xrJ {\n\txrD = xvmskltz.h(xrD, xrJ);\n}\n\ndefine pcodeop xvmskltz.w;\n\n#lasx.txt xvmskltz.w mask=0x769c4800\t\n#0x769c4800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvmskltz.w xrD, xrJ is op10_31=0x1da712 & xrD & xrJ {\n\txrD = xvmskltz.w(xrD, xrJ);\n}\n\ndefine pcodeop xvmskltz.d;\n\n#lasx.txt xvmskltz.d mask=0x769c4c00\t\n#0x769c4c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvmskltz.d xrD, xrJ is op10_31=0x1da713 & xrD & xrJ {\n\txrD = xvmskltz.d(xrD, xrJ);\n}\n\ndefine pcodeop xvmskgez.b;\n\n#lasx.txt xvmskgez.b mask=0x769c5000\t\n#0x769c5000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvmskgez.b xrD, xrJ is op10_31=0x1da714 & xrD & xrJ {\n\txrD = xvmskgez.b(xrD, xrJ);\n}\n\ndefine pcodeop xvmsknz.b;\n\n#lasx.txt xvmsknz.b mask=0x769c6000\t\n#0x769c6000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvmsknz.b xrD, xrJ is op10_31=0x1da718 & xrD & xrJ {\n\txrD = xvmsknz.b(xrD, xrJ);\n}\n\ndefine pcodeop xvseteqz.v;\n\n#lasx.txt xvseteqz.v mask=0x769c9800\t\n#0x769c9800\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvseteqz.v fccD, xrJ is op10_31=0x1da726 & fccD & xrJ {\n\tfccD = xvseteqz.v(fccD, xrJ);\n}\n\ndefine pcodeop xvsetnez.v;\n\n#lasx.txt xvsetnez.v mask=0x769c9c00\t\n#0x769c9c00\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetnez.v fccD, xrJ is op10_31=0x1da727 & fccD & xrJ {\n\tfccD = xvsetnez.v(fccD, xrJ);\n}\n\ndefine pcodeop xvsetanyeqz.b;\n\n#lasx.txt xvsetanyeqz.b mask=0x769ca000\t\n#0x769ca000\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetanyeqz.b fccD, xrJ is op10_31=0x1da728 & fccD & xrJ {\n\tfccD = xvsetanyeqz.b(fccD, xrJ);\n}\n\ndefine pcodeop xvsetanyeqz.h;\n\n#lasx.txt xvsetanyeqz.h mask=0x769ca400\t\n#0x769ca400\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetanyeqz.h fccD, xrJ is op10_31=0x1da729 & fccD & xrJ {\n\tfccD = xvsetanyeqz.h(fccD, xrJ);\n}\n\ndefine pcodeop xvsetanyeqz.w;\n\n#lasx.txt xvsetanyeqz.w mask=0x769ca800\t\n#0x769ca800\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetanyeqz.w fccD, xrJ is op10_31=0x1da72a & fccD & xrJ {\n\tfccD = xvsetanyeqz.w(fccD, xrJ);\n}\n\ndefine pcodeop xvsetanyeqz.d;\n\n#lasx.txt xvsetanyeqz.d mask=0x769cac00\t\n#0x769cac00\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetanyeqz.d fccD, xrJ is op10_31=0x1da72b & fccD & xrJ {\n\tfccD = xvsetanyeqz.d(fccD, xrJ);\n}\n\ndefine pcodeop xvsetallnez.b;\n\n#lasx.txt xvsetallnez.b mask=0x769cb000\t\n#0x769cb000\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetallnez.b fccD, xrJ is op10_31=0x1da72c & fccD & xrJ {\n\tfccD = xvsetallnez.b(fccD, xrJ);\n}\n\ndefine pcodeop xvsetallnez.h;\n\n#lasx.txt xvsetallnez.h mask=0x769cb400\t\n#0x769cb400\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetallnez.h fccD, xrJ is op10_31=0x1da72d & fccD & xrJ {\n\tfccD = xvsetallnez.h(fccD, xrJ);\n}\n\ndefine pcodeop xvsetallnez.w;\n\n#lasx.txt xvsetallnez.w mask=0x769cb800\t\n#0x769cb800\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetallnez.w fccD, xrJ is op10_31=0x1da72e & fccD & xrJ {\n\tfccD = xvsetallnez.w(fccD, xrJ);\n}\n\ndefine pcodeop xvsetallnez.d;\n\n#lasx.txt xvsetallnez.d mask=0x769cbc00\t\n#0x769cbc00\t0xfffffc18\tc0:3,x5:5\t['fcc0_3_s0', 'xreg5_5_s0']\n:xvsetallnez.d fccD, xrJ is op10_31=0x1da72f & fccD & xrJ {\n\tfccD = xvsetallnez.d(fccD, xrJ);\n}\n\ndefine pcodeop xvflogb.s;\n\n#lasx.txt xvflogb.s mask=0x769cc400\t\n#0x769cc400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvflogb.s xrD, xrJ is op10_31=0x1da731 & xrD & xrJ {\n\txrD = xvflogb.s(xrD, xrJ);\n}\n\ndefine pcodeop xvflogb.d;\n\n#lasx.txt xvflogb.d mask=0x769cc800\t\n#0x769cc800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvflogb.d xrD, xrJ is op10_31=0x1da732 & xrD & xrJ {\n\txrD = xvflogb.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfclass.s;\n\n#lasx.txt xvfclass.s mask=0x769cd400\t\n#0x769cd400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfclass.s xrD, xrJ is op10_31=0x1da735 & xrD & xrJ {\n\txrD = xvfclass.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfclass.d;\n\n#lasx.txt xvfclass.d mask=0x769cd800\t\n#0x769cd800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfclass.d xrD, xrJ is op10_31=0x1da736 & xrD & xrJ {\n\txrD = xvfclass.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfsqrt.s;\n\n#lasx.txt xvfsqrt.s mask=0x769ce400\t\n#0x769ce400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfsqrt.s xrD, xrJ is op10_31=0x1da739 & xrD & xrJ {\n\txrD = xvfsqrt.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfsqrt.d;\n\n#lasx.txt xvfsqrt.d mask=0x769ce800\t\n#0x769ce800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfsqrt.d xrD, xrJ is op10_31=0x1da73a & xrD & xrJ {\n\txrD = xvfsqrt.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrecip.s;\n\n#lasx.txt xvfrecip.s mask=0x769cf400\t\n#0x769cf400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrecip.s xrD, xrJ is op10_31=0x1da73d & xrD & xrJ {\n\txrD = xvfrecip.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrecip.d;\n\n#lasx.txt xvfrecip.d mask=0x769cf800\t\n#0x769cf800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrecip.d xrD, xrJ is op10_31=0x1da73e & xrD & xrJ {\n\txrD = xvfrecip.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrsqrt.s;\n\n#lasx.txt xvfrsqrt.s mask=0x769d0400\t\n#0x769d0400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrsqrt.s xrD, xrJ is op10_31=0x1da741 & xrD & xrJ {\n\txrD = xvfrsqrt.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrsqrt.d;\n\n#lasx.txt xvfrsqrt.d mask=0x769d0800\t\n#0x769d0800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrsqrt.d xrD, xrJ is op10_31=0x1da742 & xrD & xrJ {\n\txrD = xvfrsqrt.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrint.s;\n\n#lasx.txt xvfrint.s mask=0x769d3400\t\n#0x769d3400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrint.s xrD, xrJ is op10_31=0x1da74d & xrD & xrJ {\n\txrD = xvfrint.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrint.d;\n\n#lasx.txt xvfrint.d mask=0x769d3800\t\n#0x769d3800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrint.d xrD, xrJ is op10_31=0x1da74e & xrD & xrJ {\n\txrD = xvfrint.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrm.s;\n\n#lasx.txt xvfrintrm.s mask=0x769d4400\t\n#0x769d4400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrm.s xrD, xrJ is op10_31=0x1da751 & xrD & xrJ {\n\txrD = xvfrintrm.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrm.d;\n\n#lasx.txt xvfrintrm.d mask=0x769d4800\t\n#0x769d4800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrm.d xrD, xrJ is op10_31=0x1da752 & xrD & xrJ {\n\txrD = xvfrintrm.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrp.s;\n\n#lasx.txt xvfrintrp.s mask=0x769d5400\t\n#0x769d5400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrp.s xrD, xrJ is op10_31=0x1da755 & xrD & xrJ {\n\txrD = xvfrintrp.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrp.d;\n\n#lasx.txt xvfrintrp.d mask=0x769d5800\t\n#0x769d5800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrp.d xrD, xrJ is op10_31=0x1da756 & xrD & xrJ {\n\txrD = xvfrintrp.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrz.s;\n\n#lasx.txt xvfrintrz.s mask=0x769d6400\t\n#0x769d6400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrz.s xrD, xrJ is op10_31=0x1da759 & xrD & xrJ {\n\txrD = xvfrintrz.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrz.d;\n\n#lasx.txt xvfrintrz.d mask=0x769d6800\t\n#0x769d6800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrz.d xrD, xrJ is op10_31=0x1da75a & xrD & xrJ {\n\txrD = xvfrintrz.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrne.s;\n\n#lasx.txt xvfrintrne.s mask=0x769d7400\t\n#0x769d7400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrne.s xrD, xrJ is op10_31=0x1da75d & xrD & xrJ {\n\txrD = xvfrintrne.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfrintrne.d;\n\n#lasx.txt xvfrintrne.d mask=0x769d7800\t\n#0x769d7800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfrintrne.d xrD, xrJ is op10_31=0x1da75e & xrD & xrJ {\n\txrD = xvfrintrne.d(xrD, xrJ);\n}\n\ndefine pcodeop xvfcvtl.s.h;\n\n#lasx.txt xvfcvtl.s.h mask=0x769de800\t\n#0x769de800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfcvtl.s.h xrD, xrJ is op10_31=0x1da77a & xrD & xrJ {\n\txrD = xvfcvtl.s.h(xrD, xrJ);\n}\n\ndefine pcodeop xvfcvth.s.h;\n\n#lasx.txt xvfcvth.s.h mask=0x769dec00\t\n#0x769dec00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfcvth.s.h xrD, xrJ is op10_31=0x1da77b & xrD & xrJ {\n\txrD = xvfcvth.s.h(xrD, xrJ);\n}\n\ndefine pcodeop xvfcvtl.d.s;\n\n#lasx.txt xvfcvtl.d.s mask=0x769df000\t\n#0x769df000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfcvtl.d.s xrD, xrJ is op10_31=0x1da77c & xrD & xrJ {\n\txrD = xvfcvtl.d.s(xrD, xrJ);\n}\n\ndefine pcodeop xvfcvth.d.s;\n\n#lasx.txt xvfcvth.d.s mask=0x769df400\t\n#0x769df400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvfcvth.d.s xrD, xrJ is op10_31=0x1da77d & xrD & xrJ {\n\txrD = xvfcvth.d.s(xrD, xrJ);\n}\n\ndefine pcodeop xvffint.s.w;\n\n#lasx.txt xvffint.s.w mask=0x769e0000\t\n#0x769e0000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvffint.s.w xrD, xrJ is op10_31=0x1da780 & xrD & xrJ {\n\txrD = xvffint.s.w(xrD, xrJ);\n}\n\ndefine pcodeop xvffint.s.wu;\n\n#lasx.txt xvffint.s.wu mask=0x769e0400\t\n#0x769e0400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvffint.s.wu xrD, xrJ is op10_31=0x1da781 & xrD & xrJ {\n\txrD = xvffint.s.wu(xrD, xrJ);\n}\n\ndefine pcodeop xvffint.d.l;\n\n#lasx.txt xvffint.d.l mask=0x769e0800\t\n#0x769e0800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvffint.d.l xrD, xrJ is op10_31=0x1da782 & xrD & xrJ {\n\txrD = xvffint.d.l(xrD, xrJ);\n}\n\ndefine pcodeop xvffint.d.lu;\n\n#lasx.txt xvffint.d.lu mask=0x769e0c00\t\n#0x769e0c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvffint.d.lu xrD, xrJ is op10_31=0x1da783 & xrD & xrJ {\n\txrD = xvffint.d.lu(xrD, xrJ);\n}\n\ndefine pcodeop xvffintl.d.w;\n\n#lasx.txt xvffintl.d.w mask=0x769e1000\t\n#0x769e1000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvffintl.d.w xrD, xrJ is op10_31=0x1da784 & xrD & xrJ {\n\txrD = xvffintl.d.w(xrD, xrJ);\n}\n\ndefine pcodeop xvffinth.d.w;\n\n#lasx.txt xvffinth.d.w mask=0x769e1400\t\n#0x769e1400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvffinth.d.w xrD, xrJ is op10_31=0x1da785 & xrD & xrJ {\n\txrD = xvffinth.d.w(xrD, xrJ);\n}\n\ndefine pcodeop xvftint.w.s;\n\n#lasx.txt xvftint.w.s mask=0x769e3000\t\n#0x769e3000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftint.w.s xrD, xrJ is op10_31=0x1da78c & xrD & xrJ {\n\txrD = xvftint.w.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftint.l.d;\n\n#lasx.txt xvftint.l.d mask=0x769e3400\t\n#0x769e3400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftint.l.d xrD, xrJ is op10_31=0x1da78d & xrD & xrJ {\n\txrD = xvftint.l.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrm.w.s;\n\n#lasx.txt xvftintrm.w.s mask=0x769e3800\t\n#0x769e3800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrm.w.s xrD, xrJ is op10_31=0x1da78e & xrD & xrJ {\n\txrD = xvftintrm.w.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrm.l.d;\n\n#lasx.txt xvftintrm.l.d mask=0x769e3c00\t\n#0x769e3c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrm.l.d xrD, xrJ is op10_31=0x1da78f & xrD & xrJ {\n\txrD = xvftintrm.l.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrp.w.s;\n\n#lasx.txt xvftintrp.w.s mask=0x769e4000\t\n#0x769e4000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrp.w.s xrD, xrJ is op10_31=0x1da790 & xrD & xrJ {\n\txrD = xvftintrp.w.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrp.l.d;\n\n#lasx.txt xvftintrp.l.d mask=0x769e4400\t\n#0x769e4400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrp.l.d xrD, xrJ is op10_31=0x1da791 & xrD & xrJ {\n\txrD = xvftintrp.l.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrz.w.s;\n\n#lasx.txt xvftintrz.w.s mask=0x769e4800\t\n#0x769e4800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrz.w.s xrD, xrJ is op10_31=0x1da792 & xrD & xrJ {\n\txrD = xvftintrz.w.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrz.l.d;\n\n#lasx.txt xvftintrz.l.d mask=0x769e4c00\t\n#0x769e4c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrz.l.d xrD, xrJ is op10_31=0x1da793 & xrD & xrJ {\n\txrD = xvftintrz.l.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrne.w.s;\n\n#lasx.txt xvftintrne.w.s mask=0x769e5000\t\n#0x769e5000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrne.w.s xrD, xrJ is op10_31=0x1da794 & xrD & xrJ {\n\txrD = xvftintrne.w.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrne.l.d;\n\n#lasx.txt xvftintrne.l.d mask=0x769e5400\t\n#0x769e5400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrne.l.d xrD, xrJ is op10_31=0x1da795 & xrD & xrJ {\n\txrD = xvftintrne.l.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftint.wu.s;\n\n#lasx.txt xvftint.wu.s mask=0x769e5800\t\n#0x769e5800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftint.wu.s xrD, xrJ is op10_31=0x1da796 & xrD & xrJ {\n\txrD = xvftint.wu.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftint.lu.d;\n\n#lasx.txt xvftint.lu.d mask=0x769e5c00\t\n#0x769e5c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftint.lu.d xrD, xrJ is op10_31=0x1da797 & xrD & xrJ {\n\txrD = xvftint.lu.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrz.wu.s;\n\n#lasx.txt xvftintrz.wu.s mask=0x769e7000\t\n#0x769e7000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrz.wu.s xrD, xrJ is op10_31=0x1da79c & xrD & xrJ {\n\txrD = xvftintrz.wu.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrz.lu.d;\n\n#lasx.txt xvftintrz.lu.d mask=0x769e7400\t\n#0x769e7400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrz.lu.d xrD, xrJ is op10_31=0x1da79d & xrD & xrJ {\n\txrD = xvftintrz.lu.d(xrD, xrJ);\n}\n\ndefine pcodeop xvftintl.l.s;\n\n#lasx.txt xvftintl.l.s mask=0x769e8000\t\n#0x769e8000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintl.l.s xrD, xrJ is op10_31=0x1da7a0 & xrD & xrJ {\n\txrD = xvftintl.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftinth.l.s;\n\n#lasx.txt xvftinth.l.s mask=0x769e8400\t\n#0x769e8400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftinth.l.s xrD, xrJ is op10_31=0x1da7a1 & xrD & xrJ {\n\txrD = xvftinth.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrml.l.s;\n\n#lasx.txt xvftintrml.l.s mask=0x769e8800\t\n#0x769e8800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrml.l.s xrD, xrJ is op10_31=0x1da7a2 & xrD & xrJ {\n\txrD = xvftintrml.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrmh.l.s;\n\n#lasx.txt xvftintrmh.l.s mask=0x769e8c00\t\n#0x769e8c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrmh.l.s xrD, xrJ is op10_31=0x1da7a3 & xrD & xrJ {\n\txrD = xvftintrmh.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrpl.l.s;\n\n#lasx.txt xvftintrpl.l.s mask=0x769e9000\t\n#0x769e9000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrpl.l.s xrD, xrJ is op10_31=0x1da7a4 & xrD & xrJ {\n\txrD = xvftintrpl.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrph.l.s;\n\n#lasx.txt xvftintrph.l.s mask=0x769e9400\t\n#0x769e9400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrph.l.s xrD, xrJ is op10_31=0x1da7a5 & xrD & xrJ {\n\txrD = xvftintrph.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrzl.l.s;\n\n#lasx.txt xvftintrzl.l.s mask=0x769e9800\t\n#0x769e9800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrzl.l.s xrD, xrJ is op10_31=0x1da7a6 & xrD & xrJ {\n\txrD = xvftintrzl.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrzh.l.s;\n\n#lasx.txt xvftintrzh.l.s mask=0x769e9c00\t\n#0x769e9c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrzh.l.s xrD, xrJ is op10_31=0x1da7a7 & xrD & xrJ {\n\txrD = xvftintrzh.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrnel.l.s;\n\n#lasx.txt xvftintrnel.l.s mask=0x769ea000\t\n#0x769ea000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrnel.l.s xrD, xrJ is op10_31=0x1da7a8 & xrD & xrJ {\n\txrD = xvftintrnel.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvftintrneh.l.s;\n\n#lasx.txt xvftintrneh.l.s mask=0x769ea400\t\n#0x769ea400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvftintrneh.l.s xrD, xrJ is op10_31=0x1da7a9 & xrD & xrJ {\n\txrD = xvftintrneh.l.s(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.h.b;\n\n#lasx.txt xvexth.h.b mask=0x769ee000\t\n#0x769ee000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.h.b xrD, xrJ is op10_31=0x1da7b8 & xrD & xrJ {\n\txrD = xvexth.h.b(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.w.h;\n\n#lasx.txt xvexth.w.h mask=0x769ee400\t\n#0x769ee400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.w.h xrD, xrJ is op10_31=0x1da7b9 & xrD & xrJ {\n\txrD = xvexth.w.h(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.d.w;\n\n#lasx.txt xvexth.d.w mask=0x769ee800\t\n#0x769ee800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.d.w xrD, xrJ is op10_31=0x1da7ba & xrD & xrJ {\n\txrD = xvexth.d.w(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.q.d;\n\n#lasx.txt xvexth.q.d mask=0x769eec00\t\n#0x769eec00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.q.d xrD, xrJ is op10_31=0x1da7bb & xrD & xrJ {\n\txrD = xvexth.q.d(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.hu.bu;\n\n#lasx.txt xvexth.hu.bu mask=0x769ef000\t\n#0x769ef000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.hu.bu xrD, xrJ is op10_31=0x1da7bc & xrD & xrJ {\n\txrD = xvexth.hu.bu(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.wu.hu;\n\n#lasx.txt xvexth.wu.hu mask=0x769ef400\t\n#0x769ef400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.wu.hu xrD, xrJ is op10_31=0x1da7bd & xrD & xrJ {\n\txrD = xvexth.wu.hu(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.du.wu;\n\n#lasx.txt xvexth.du.wu mask=0x769ef800\t\n#0x769ef800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.du.wu xrD, xrJ is op10_31=0x1da7be & xrD & xrJ {\n\txrD = xvexth.du.wu(xrD, xrJ);\n}\n\ndefine pcodeop xvexth.qu.du;\n\n#lasx.txt xvexth.qu.du mask=0x769efc00\t\n#0x769efc00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvexth.qu.du xrD, xrJ is op10_31=0x1da7bf & xrD & xrJ {\n\txrD = xvexth.qu.du(xrD, xrJ);\n}\n\ndefine pcodeop xvreplgr2vr.b;\n\n#lasx.txt xvreplgr2vr.b mask=0x769f0000\t\n#0x769f0000\t0xfffffc00\tx0:5, r5:5\t['xreg0_5_s0', 'reg5_5_s0']\n:xvreplgr2vr.b xrD, RJsrc is op10_31=0x1da7c0 & xrD & RJsrc {\n\txrD = xvreplgr2vr.b(xrD, RJsrc);\n}\n\ndefine pcodeop xvreplgr2vr.h;\n\n#lasx.txt xvreplgr2vr.h mask=0x769f0400\t\n#0x769f0400\t0xfffffc00\tx0:5, r5:5\t['xreg0_5_s0', 'reg5_5_s0']\n:xvreplgr2vr.h xrD, RJsrc is op10_31=0x1da7c1 & xrD & RJsrc {\n\txrD = xvreplgr2vr.h(xrD, RJsrc);\n}\n\ndefine pcodeop xvreplgr2vr.w;\n\n#lasx.txt xvreplgr2vr.w mask=0x769f0800\t\n#0x769f0800\t0xfffffc00\tx0:5, r5:5\t['xreg0_5_s0', 'reg5_5_s0']\n:xvreplgr2vr.w xrD, RJsrc is op10_31=0x1da7c2 & xrD & RJsrc {\n\txrD = xvreplgr2vr.w(xrD, RJsrc);\n}\n\ndefine pcodeop xvreplgr2vr.d;\n\n#lasx.txt xvreplgr2vr.d mask=0x769f0c00\t\n#0x769f0c00\t0xfffffc00\tx0:5, r5:5\t['xreg0_5_s0', 'reg5_5_s0']\n:xvreplgr2vr.d xrD, RJsrc is op10_31=0x1da7c3 & xrD & RJsrc {\n\txrD = xvreplgr2vr.d(xrD, RJsrc);\n}\n\ndefine pcodeop vext2xv.h.b;\n\n#lasx.txt vext2xv.h.b mask=0x769f1000\t\n#0x769f1000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.h.b xrD, xrJ is op10_31=0x1da7c4 & xrD & xrJ {\n\txrD = vext2xv.h.b(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.w.b;\n\n#lasx.txt vext2xv.w.b mask=0x769f1400\t\n#0x769f1400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.w.b xrD, xrJ is op10_31=0x1da7c5 & xrD & xrJ {\n\txrD = vext2xv.w.b(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.d.b;\n\n#lasx.txt vext2xv.d.b mask=0x769f1800\t\n#0x769f1800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.d.b xrD, xrJ is op10_31=0x1da7c6 & xrD & xrJ {\n\txrD = vext2xv.d.b(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.w.h;\n\n#lasx.txt vext2xv.w.h mask=0x769f1c00\t\n#0x769f1c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.w.h xrD, xrJ is op10_31=0x1da7c7 & xrD & xrJ {\n\txrD = vext2xv.w.h(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.d.h;\n\n#lasx.txt vext2xv.d.h mask=0x769f2000\t\n#0x769f2000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.d.h xrD, xrJ is op10_31=0x1da7c8 & xrD & xrJ {\n\txrD = vext2xv.d.h(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.d.w;\n\n#lasx.txt vext2xv.d.w mask=0x769f2400\t\n#0x769f2400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.d.w xrD, xrJ is op10_31=0x1da7c9 & xrD & xrJ {\n\txrD = vext2xv.d.w(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.hu.bu;\n\n#lasx.txt vext2xv.hu.bu mask=0x769f2800\t\n#0x769f2800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.hu.bu xrD, xrJ is op10_31=0x1da7ca & xrD & xrJ {\n\txrD = vext2xv.hu.bu(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.wu.bu;\n\n#lasx.txt vext2xv.wu.bu mask=0x769f2c00\t\n#0x769f2c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.wu.bu xrD, xrJ is op10_31=0x1da7cb & xrD & xrJ {\n\txrD = vext2xv.wu.bu(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.du.bu;\n\n#lasx.txt vext2xv.du.bu mask=0x769f3000\t\n#0x769f3000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.du.bu xrD, xrJ is op10_31=0x1da7cc & xrD & xrJ {\n\txrD = vext2xv.du.bu(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.wu.hu;\n\n#lasx.txt vext2xv.wu.hu mask=0x769f3400\t\n#0x769f3400\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.wu.hu xrD, xrJ is op10_31=0x1da7cd & xrD & xrJ {\n\txrD = vext2xv.wu.hu(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.du.hu;\n\n#lasx.txt vext2xv.du.hu mask=0x769f3800\t\n#0x769f3800\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.du.hu xrD, xrJ is op10_31=0x1da7ce & xrD & xrJ {\n\txrD = vext2xv.du.hu(xrD, xrJ);\n}\n\ndefine pcodeop vext2xv.du.wu;\n\n#lasx.txt vext2xv.du.wu mask=0x769f3c00\t\n#0x769f3c00\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:vext2xv.du.wu xrD, xrJ is op10_31=0x1da7cf & xrD & xrJ {\n\txrD = vext2xv.du.wu(xrD, xrJ);\n}\n\ndefine pcodeop xvrotri.b;\n\n#lasx.txt xvrotri.b mask=0x76a02000\t\n#0x76a02000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvrotri.b xrD, xrJ, imm10_3 is op13_31=0x3b501 & xrD & xrJ & imm10_3 {\n\txrD = xvrotri.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvrotri.h;\n\n#lasx.txt xvrotri.h mask=0x76a04000\t\n#0x76a04000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvrotri.h xrD, xrJ, imm10_4 is op14_31=0x1da81 & xrD & xrJ & imm10_4 {\n\txrD = xvrotri.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvrotri.w;\n\n#lasx.txt xvrotri.w mask=0x76a08000\t\n#0x76a08000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvrotri.w xrD, xrJ, imm10_5 is op15_31=0xed41 & xrD & xrJ & imm10_5 {\n\txrD = xvrotri.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvrotri.d;\n\n#lasx.txt xvrotri.d mask=0x76a10000\t\n#0x76a10000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvrotri.d xrD, xrJ, imm10_6 is op16_31=0x76a1 & xrD & xrJ & imm10_6 {\n\txrD = xvrotri.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlri.b;\n\n#lasx.txt xvsrlri.b mask=0x76a42000\t\n#0x76a42000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsrlri.b xrD, xrJ, imm10_3 is op13_31=0x3b521 & xrD & xrJ & imm10_3 {\n\txrD = xvsrlri.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlri.h;\n\n#lasx.txt xvsrlri.h mask=0x76a44000\t\n#0x76a44000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrlri.h xrD, xrJ, imm10_4 is op14_31=0x1da91 & xrD & xrJ & imm10_4 {\n\txrD = xvsrlri.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlri.w;\n\n#lasx.txt xvsrlri.w mask=0x76a48000\t\n#0x76a48000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrlri.w xrD, xrJ, imm10_5 is op15_31=0xed49 & xrD & xrJ & imm10_5 {\n\txrD = xvsrlri.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlri.d;\n\n#lasx.txt xvsrlri.d mask=0x76a50000\t\n#0x76a50000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrlri.d xrD, xrJ, imm10_6 is op16_31=0x76a5 & xrD & xrJ & imm10_6 {\n\txrD = xvsrlri.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrari.b;\n\n#lasx.txt xvsrari.b mask=0x76a82000\t\n#0x76a82000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsrari.b xrD, xrJ, imm10_3 is op13_31=0x3b541 & xrD & xrJ & imm10_3 {\n\txrD = xvsrari.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsrari.h;\n\n#lasx.txt xvsrari.h mask=0x76a84000\t\n#0x76a84000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrari.h xrD, xrJ, imm10_4 is op14_31=0x1daa1 & xrD & xrJ & imm10_4 {\n\txrD = xvsrari.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrari.w;\n\n#lasx.txt xvsrari.w mask=0x76a88000\t\n#0x76a88000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrari.w xrD, xrJ, imm10_5 is op15_31=0xed51 & xrD & xrJ & imm10_5 {\n\txrD = xvsrari.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrari.d;\n\n#lasx.txt xvsrari.d mask=0x76a90000\t\n#0x76a90000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrari.d xrD, xrJ, imm10_6 is op16_31=0x76a9 & xrD & xrJ & imm10_6 {\n\txrD = xvsrari.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvinsgr2vr.w;\n\n#lasx.txt xvinsgr2vr.w mask=0x76ebc000\t\n#0x76ebc000\t0xffffe000\tx0:5, r5:5,u10:3\t['xreg0_5_s0', 'reg5_5_s0', 'imm10_3_s0']\n:xvinsgr2vr.w xrD, RJsrc, imm10_3 is op13_31=0x3b75e & xrD & RJsrc & imm10_3 {\n\txrD = xvinsgr2vr.w(xrD, RJsrc, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvinsgr2vr.d;\n\n#lasx.txt xvinsgr2vr.d mask=0x76ebe000\t\n#0x76ebe000\t0xfffff000\tx0:5, r5:5,u10:2\t['xreg0_5_s0', 'reg5_5_s0', 'imm10_2_s0']\n:xvinsgr2vr.d xrD, RJsrc, imm10_2 is op12_31=0x76ebe & xrD & RJsrc & imm10_2 {\n\txrD = xvinsgr2vr.d(xrD, RJsrc, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop xvpickve2gr.w;\n\n#lasx.txt xvpickve2gr.w mask=0x76efc000\t\n#0x76efc000\t0xffffe000\tr0:5,x5:5,u10:3\t['reg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvpickve2gr.w RD, xrJ, imm10_3 is op13_31=0x3b77e & RD & xrJ & imm10_3 {\n\tRD = xvpickve2gr.w(RD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvpickve2gr.d;\n\n#lasx.txt xvpickve2gr.d mask=0x76efe000\t\n#0x76efe000\t0xfffff000\tr0:5,x5:5,u10:2\t['reg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0']\n:xvpickve2gr.d RD, xrJ, imm10_2 is op12_31=0x76efe & RD & xrJ & imm10_2 {\n\tRD = xvpickve2gr.d(RD, xrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop xvpickve2gr.wu;\n\n#lasx.txt xvpickve2gr.wu mask=0x76f3c000\t\n#0x76f3c000\t0xffffe000\tr0:5,x5:5,u10:3\t['reg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvpickve2gr.wu RD, xrJ, imm10_3 is op13_31=0x3b79e & RD & xrJ & imm10_3 {\n\tRD = xvpickve2gr.wu(RD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvpickve2gr.du;\n\n#lasx.txt xvpickve2gr.du mask=0x76f3e000\t\n#0x76f3e000\t0xfffff000\tr0:5,x5:5,u10:2\t['reg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0']\n:xvpickve2gr.du RD, xrJ, imm10_2 is op12_31=0x76f3e & RD & xrJ & imm10_2 {\n\tRD = xvpickve2gr.du(RD, xrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop xvrepl128vei.b;\n\n#lasx.txt xvrepl128vei.b mask=0x76f78000\t\n#0x76f78000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvrepl128vei.b xrD, xrJ, imm10_4 is op14_31=0x1dbde & xrD & xrJ & imm10_4 {\n\txrD = xvrepl128vei.b(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvrepl128vei.h;\n\n#lasx.txt xvrepl128vei.h mask=0x76f7c000\t\n#0x76f7c000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvrepl128vei.h xrD, xrJ, imm10_3 is op13_31=0x3b7be & xrD & xrJ & imm10_3 {\n\txrD = xvrepl128vei.h(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvrepl128vei.w;\n\n#lasx.txt xvrepl128vei.w mask=0x76f7e000\t\n#0x76f7e000\t0xfffff000\tx0:5,x5:5,u10:2\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0']\n:xvrepl128vei.w xrD, xrJ, imm10_2 is op12_31=0x76f7e & xrD & xrJ & imm10_2 {\n\txrD = xvrepl128vei.w(xrD, xrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop xvrepl128vei.d;\n\n#lasx.txt xvrepl128vei.d mask=0x76f7f000\t\n#0x76f7f000\t0xfffff800\tx0:5,x5:5,u10:1\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_1_s0']\n:xvrepl128vei.d xrD, xrJ, imm10_1 is op11_31=0xedefe & xrD & xrJ & imm10_1 {\n\txrD = xvrepl128vei.d(xrD, xrJ, imm10_1:$(REGSIZE));\n}\n\ndefine pcodeop xvinsve0.w;\n\n#lasx.txt xvinsve0.w mask=0x76ffc000\t\n#0x76ffc000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvinsve0.w xrD, xrJ, imm10_3 is op13_31=0x3b7fe & xrD & xrJ & imm10_3 {\n\txrD = xvinsve0.w(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvinsve0.d;\n\n#lasx.txt xvinsve0.d mask=0x76ffe000\t\n#0x76ffe000\t0xfffff000\tx0:5,x5:5,u10:2\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0']\n:xvinsve0.d xrD, xrJ, imm10_2 is op12_31=0x76ffe & xrD & xrJ & imm10_2 {\n\txrD = xvinsve0.d(xrD, xrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop xvpickve.w;\n\n#lasx.txt xvpickve.w mask=0x7703c000\t\n#0x7703c000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvpickve.w xrD, xrJ, imm10_3 is op13_31=0x3b81e & xrD & xrJ & imm10_3 {\n\txrD = xvpickve.w(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvpickve.d;\n\n#lasx.txt xvpickve.d mask=0x7703e000\t\n#0x7703e000\t0xfffff000\tx0:5,x5:5,u10:2\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0']\n:xvpickve.d xrD, xrJ, imm10_2 is op12_31=0x7703e & xrD & xrJ & imm10_2 {\n\txrD = xvpickve.d(xrD, xrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop xvreplve0.b;\n\n#lasx.txt xvreplve0.b mask=0x77070000\t\n#0x77070000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvreplve0.b xrD, xrJ is op10_31=0x1dc1c0 & xrD & xrJ {\n\txrD = xvreplve0.b(xrD, xrJ);\n}\n\ndefine pcodeop xvreplve0.h;\n\n#lasx.txt xvreplve0.h mask=0x77078000\t\n#0x77078000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvreplve0.h xrD, xrJ is op10_31=0x1dc1e0 & xrD & xrJ {\n\txrD = xvreplve0.h(xrD, xrJ);\n}\n\ndefine pcodeop xvreplve0.w;\n\n#lasx.txt xvreplve0.w mask=0x7707c000\t\n#0x7707c000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvreplve0.w xrD, xrJ is op10_31=0x1dc1f0 & xrD & xrJ {\n\txrD = xvreplve0.w(xrD, xrJ);\n}\n\ndefine pcodeop xvreplve0.d;\n\n#lasx.txt xvreplve0.d mask=0x7707e000\t\n#0x7707e000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvreplve0.d xrD, xrJ is op10_31=0x1dc1f8 & xrD & xrJ {\n\txrD = xvreplve0.d(xrD, xrJ);\n}\n\ndefine pcodeop xvreplve0.q;\n\n#lasx.txt xvreplve0.q mask=0x7707f000\t\n#0x7707f000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvreplve0.q xrD, xrJ is op10_31=0x1dc1fc & xrD & xrJ {\n\txrD = xvreplve0.q(xrD, xrJ);\n}\n\ndefine pcodeop xvsllwil.h.b;\n\n#lasx.txt xvsllwil.h.b mask=0x77082000\t\n#0x77082000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsllwil.h.b xrD, xrJ, imm10_3 is op13_31=0x3b841 & xrD & xrJ & imm10_3 {\n\txrD = xvsllwil.h.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsllwil.w.h;\n\n#lasx.txt xvsllwil.w.h mask=0x77084000\t\n#0x77084000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsllwil.w.h xrD, xrJ, imm10_4 is op14_31=0x1dc21 & xrD & xrJ & imm10_4 {\n\txrD = xvsllwil.w.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsllwil.d.w;\n\n#lasx.txt xvsllwil.d.w mask=0x77088000\t\n#0x77088000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsllwil.d.w xrD, xrJ, imm10_5 is op15_31=0xee11 & xrD & xrJ & imm10_5 {\n\txrD = xvsllwil.d.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvextl.q.d;\n\n#lasx.txt xvextl.q.d mask=0x77090000\t\n#0x77090000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvextl.q.d xrD, xrJ is op10_31=0x1dc240 & xrD & xrJ {\n\txrD = xvextl.q.d(xrD, xrJ);\n}\n\ndefine pcodeop xvsllwil.hu.bu;\n\n#lasx.txt xvsllwil.hu.bu mask=0x770c2000\t\n#0x770c2000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsllwil.hu.bu xrD, xrJ, imm10_3 is op13_31=0x3b861 & xrD & xrJ & imm10_3 {\n\txrD = xvsllwil.hu.bu(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsllwil.wu.hu;\n\n#lasx.txt xvsllwil.wu.hu mask=0x770c4000\t\n#0x770c4000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsllwil.wu.hu xrD, xrJ, imm10_4 is op14_31=0x1dc31 & xrD & xrJ & imm10_4 {\n\txrD = xvsllwil.wu.hu(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsllwil.du.wu;\n\n#lasx.txt xvsllwil.du.wu mask=0x770c8000\t\n#0x770c8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsllwil.du.wu xrD, xrJ, imm10_5 is op15_31=0xee19 & xrD & xrJ & imm10_5 {\n\txrD = xvsllwil.du.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvextl.qu.du;\n\n#lasx.txt xvextl.qu.du mask=0x770d0000\t\n#0x770d0000\t0xfffffc00\tx0:5,x5:5\t['xreg0_5_s0', 'xreg5_5_s0']\n:xvextl.qu.du xrD, xrJ is op10_31=0x1dc340 & xrD & xrJ {\n\txrD = xvextl.qu.du(xrD, xrJ);\n}\n\ndefine pcodeop xvbitclri.b;\n\n#lasx.txt xvbitclri.b mask=0x77102000\t\n#0x77102000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvbitclri.b xrD, xrJ, imm10_3 is op13_31=0x3b881 & xrD & xrJ & imm10_3 {\n\txrD = xvbitclri.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvbitclri.h;\n\n#lasx.txt xvbitclri.h mask=0x77104000\t\n#0x77104000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvbitclri.h xrD, xrJ, imm10_4 is op14_31=0x1dc41 & xrD & xrJ & imm10_4 {\n\txrD = xvbitclri.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvbitclri.w;\n\n#lasx.txt xvbitclri.w mask=0x77108000\t\n#0x77108000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvbitclri.w xrD, xrJ, imm10_5 is op15_31=0xee21 & xrD & xrJ & imm10_5 {\n\txrD = xvbitclri.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvbitclri.d;\n\n#lasx.txt xvbitclri.d mask=0x77110000\t\n#0x77110000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvbitclri.d xrD, xrJ, imm10_6 is op16_31=0x7711 & xrD & xrJ & imm10_6 {\n\txrD = xvbitclri.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvbitseti.b;\n\n#lasx.txt xvbitseti.b mask=0x77142000\t\n#0x77142000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvbitseti.b xrD, xrJ, imm10_3 is op13_31=0x3b8a1 & xrD & xrJ & imm10_3 {\n\txrD = xvbitseti.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvbitseti.h;\n\n#lasx.txt xvbitseti.h mask=0x77144000\t\n#0x77144000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvbitseti.h xrD, xrJ, imm10_4 is op14_31=0x1dc51 & xrD & xrJ & imm10_4 {\n\txrD = xvbitseti.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvbitseti.w;\n\n#lasx.txt xvbitseti.w mask=0x77148000\t\n#0x77148000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvbitseti.w xrD, xrJ, imm10_5 is op15_31=0xee29 & xrD & xrJ & imm10_5 {\n\txrD = xvbitseti.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvbitseti.d;\n\n#lasx.txt xvbitseti.d mask=0x77150000\t\n#0x77150000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvbitseti.d xrD, xrJ, imm10_6 is op16_31=0x7715 & xrD & xrJ & imm10_6 {\n\txrD = xvbitseti.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvbitrevi.b;\n\n#lasx.txt xvbitrevi.b mask=0x77182000\t\n#0x77182000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvbitrevi.b xrD, xrJ, imm10_3 is op13_31=0x3b8c1 & xrD & xrJ & imm10_3 {\n\txrD = xvbitrevi.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvbitrevi.h;\n\n#lasx.txt xvbitrevi.h mask=0x77184000\t\n#0x77184000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvbitrevi.h xrD, xrJ, imm10_4 is op14_31=0x1dc61 & xrD & xrJ & imm10_4 {\n\txrD = xvbitrevi.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvbitrevi.w;\n\n#lasx.txt xvbitrevi.w mask=0x77188000\t\n#0x77188000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvbitrevi.w xrD, xrJ, imm10_5 is op15_31=0xee31 & xrD & xrJ & imm10_5 {\n\txrD = xvbitrevi.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvbitrevi.d;\n\n#lasx.txt xvbitrevi.d mask=0x77190000\t\n#0x77190000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvbitrevi.d xrD, xrJ, imm10_6 is op16_31=0x7719 & xrD & xrJ & imm10_6 {\n\txrD = xvbitrevi.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.b;\n\n#lasx.txt xvsat.b mask=0x77242000\t\n#0x77242000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsat.b xrD, xrJ, imm10_3 is op13_31=0x3b921 & xrD & xrJ & imm10_3 {\n\txrD = xvsat.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.h;\n\n#lasx.txt xvsat.h mask=0x77244000\t\n#0x77244000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsat.h xrD, xrJ, imm10_4 is op14_31=0x1dc91 & xrD & xrJ & imm10_4 {\n\txrD = xvsat.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.w;\n\n#lasx.txt xvsat.w mask=0x77248000\t\n#0x77248000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsat.w xrD, xrJ, imm10_5 is op15_31=0xee49 & xrD & xrJ & imm10_5 {\n\txrD = xvsat.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.d;\n\n#lasx.txt xvsat.d mask=0x77250000\t\n#0x77250000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsat.d xrD, xrJ, imm10_6 is op16_31=0x7725 & xrD & xrJ & imm10_6 {\n\txrD = xvsat.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.bu;\n\n#lasx.txt xvsat.bu mask=0x77282000\t\n#0x77282000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsat.bu xrD, xrJ, imm10_3 is op13_31=0x3b941 & xrD & xrJ & imm10_3 {\n\txrD = xvsat.bu(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.hu;\n\n#lasx.txt xvsat.hu mask=0x77284000\t\n#0x77284000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsat.hu xrD, xrJ, imm10_4 is op14_31=0x1dca1 & xrD & xrJ & imm10_4 {\n\txrD = xvsat.hu(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.wu;\n\n#lasx.txt xvsat.wu mask=0x77288000\t\n#0x77288000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsat.wu xrD, xrJ, imm10_5 is op15_31=0xee51 & xrD & xrJ & imm10_5 {\n\txrD = xvsat.wu(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsat.du;\n\n#lasx.txt xvsat.du mask=0x77290000\t\n#0x77290000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsat.du xrD, xrJ, imm10_6 is op16_31=0x7729 & xrD & xrJ & imm10_6 {\n\txrD = xvsat.du(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvslli.b;\n\n#lasx.txt xvslli.b mask=0x772c2000\t\n#0x772c2000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvslli.b xrD, xrJ, imm10_3 is op13_31=0x3b961 & xrD & xrJ & imm10_3 {\n\txrD = xvslli.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvslli.h;\n\n#lasx.txt xvslli.h mask=0x772c4000\t\n#0x772c4000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvslli.h xrD, xrJ, imm10_4 is op14_31=0x1dcb1 & xrD & xrJ & imm10_4 {\n\txrD = xvslli.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvslli.w;\n\n#lasx.txt xvslli.w mask=0x772c8000\t\n#0x772c8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvslli.w xrD, xrJ, imm10_5 is op15_31=0xee59 & xrD & xrJ & imm10_5 {\n\txrD = xvslli.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvslli.d;\n\n#lasx.txt xvslli.d mask=0x772d0000\t\n#0x772d0000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvslli.d xrD, xrJ, imm10_6 is op16_31=0x772d & xrD & xrJ & imm10_6 {\n\txrD = xvslli.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrli.b;\n\n#lasx.txt xvsrli.b mask=0x77302000\t\n#0x77302000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsrli.b xrD, xrJ, imm10_3 is op13_31=0x3b981 & xrD & xrJ & imm10_3 {\n\txrD = xvsrli.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsrli.h;\n\n#lasx.txt xvsrli.h mask=0x77304000\t\n#0x77304000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrli.h xrD, xrJ, imm10_4 is op14_31=0x1dcc1 & xrD & xrJ & imm10_4 {\n\txrD = xvsrli.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrli.w;\n\n#lasx.txt xvsrli.w mask=0x77308000\t\n#0x77308000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrli.w xrD, xrJ, imm10_5 is op15_31=0xee61 & xrD & xrJ & imm10_5 {\n\txrD = xvsrli.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrli.d;\n\n#lasx.txt xvsrli.d mask=0x77310000\t\n#0x77310000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrli.d xrD, xrJ, imm10_6 is op16_31=0x7731 & xrD & xrJ & imm10_6 {\n\txrD = xvsrli.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrai.b;\n\n#lasx.txt xvsrai.b mask=0x77342000\t\n#0x77342000\t0xffffe000\tx0:5,x5:5,u10:3\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0']\n:xvsrai.b xrD, xrJ, imm10_3 is op13_31=0x3b9a1 & xrD & xrJ & imm10_3 {\n\txrD = xvsrai.b(xrD, xrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop xvsrai.h;\n\n#lasx.txt xvsrai.h mask=0x77344000\t\n#0x77344000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrai.h xrD, xrJ, imm10_4 is op14_31=0x1dcd1 & xrD & xrJ & imm10_4 {\n\txrD = xvsrai.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrai.w;\n\n#lasx.txt xvsrai.w mask=0x77348000\t\n#0x77348000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrai.w xrD, xrJ, imm10_5 is op15_31=0xee69 & xrD & xrJ & imm10_5 {\n\txrD = xvsrai.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrai.d;\n\n#lasx.txt xvsrai.d mask=0x77350000\t\n#0x77350000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrai.d xrD, xrJ, imm10_6 is op16_31=0x7735 & xrD & xrJ & imm10_6 {\n\txrD = xvsrai.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlni.b.h;\n\n#lasx.txt xvsrlni.b.h mask=0x77404000\t\n#0x77404000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrlni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd01 & xrD & xrJ & imm10_4 {\n\txrD = xvsrlni.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlni.h.w;\n\n#lasx.txt xvsrlni.h.w mask=0x77408000\t\n#0x77408000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrlni.h.w xrD, xrJ, imm10_5 is op15_31=0xee81 & xrD & xrJ & imm10_5 {\n\txrD = xvsrlni.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlni.w.d;\n\n#lasx.txt xvsrlni.w.d mask=0x77410000\t\n#0x77410000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrlni.w.d xrD, xrJ, imm10_6 is op16_31=0x7741 & xrD & xrJ & imm10_6 {\n\txrD = xvsrlni.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlni.d.q;\n\n#lasx.txt xvsrlni.d.q mask=0x77420000\t\n#0x77420000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvsrlni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba1 & xrD & xrJ & imm10_7 {\n\txrD = xvsrlni.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlrni.b.h;\n\n#lasx.txt xvsrlrni.b.h mask=0x77444000\t\n#0x77444000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrlrni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd11 & xrD & xrJ & imm10_4 {\n\txrD = xvsrlrni.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlrni.h.w;\n\n#lasx.txt xvsrlrni.h.w mask=0x77448000\t\n#0x77448000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrlrni.h.w xrD, xrJ, imm10_5 is op15_31=0xee89 & xrD & xrJ & imm10_5 {\n\txrD = xvsrlrni.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlrni.w.d;\n\n#lasx.txt xvsrlrni.w.d mask=0x77450000\t\n#0x77450000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrlrni.w.d xrD, xrJ, imm10_6 is op16_31=0x7745 & xrD & xrJ & imm10_6 {\n\txrD = xvsrlrni.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrlrni.d.q;\n\n#lasx.txt xvsrlrni.d.q mask=0x77460000\t\n#0x77460000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvsrlrni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba3 & xrD & xrJ & imm10_7 {\n\txrD = xvsrlrni.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.b.h;\n\n#lasx.txt xvssrlni.b.h mask=0x77484000\t\n#0x77484000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrlni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd21 & xrD & xrJ & imm10_4 {\n\txrD = xvssrlni.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.h.w;\n\n#lasx.txt xvssrlni.h.w mask=0x77488000\t\n#0x77488000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrlni.h.w xrD, xrJ, imm10_5 is op15_31=0xee91 & xrD & xrJ & imm10_5 {\n\txrD = xvssrlni.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.w.d;\n\n#lasx.txt xvssrlni.w.d mask=0x77490000\t\n#0x77490000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrlni.w.d xrD, xrJ, imm10_6 is op16_31=0x7749 & xrD & xrJ & imm10_6 {\n\txrD = xvssrlni.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.d.q;\n\n#lasx.txt xvssrlni.d.q mask=0x774a0000\t\n#0x774a0000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrlni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba5 & xrD & xrJ & imm10_7 {\n\txrD = xvssrlni.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.bu.h;\n\n#lasx.txt xvssrlni.bu.h mask=0x774c4000\t\n#0x774c4000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrlni.bu.h xrD, xrJ, imm10_4 is op14_31=0x1dd31 & xrD & xrJ & imm10_4 {\n\txrD = xvssrlni.bu.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.hu.w;\n\n#lasx.txt xvssrlni.hu.w mask=0x774c8000\t\n#0x774c8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrlni.hu.w xrD, xrJ, imm10_5 is op15_31=0xee99 & xrD & xrJ & imm10_5 {\n\txrD = xvssrlni.hu.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.wu.d;\n\n#lasx.txt xvssrlni.wu.d mask=0x774d0000\t\n#0x774d0000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrlni.wu.d xrD, xrJ, imm10_6 is op16_31=0x774d & xrD & xrJ & imm10_6 {\n\txrD = xvssrlni.wu.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlni.du.q;\n\n#lasx.txt xvssrlni.du.q mask=0x774e0000\t\n#0x774e0000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrlni.du.q xrD, xrJ, imm10_7 is op17_31=0x3ba7 & xrD & xrJ & imm10_7 {\n\txrD = xvssrlni.du.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.b.h;\n\n#lasx.txt xvssrlrni.b.h mask=0x77504000\t\n#0x77504000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrlrni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd41 & xrD & xrJ & imm10_4 {\n\txrD = xvssrlrni.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.h.w;\n\n#lasx.txt xvssrlrni.h.w mask=0x77508000\t\n#0x77508000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrlrni.h.w xrD, xrJ, imm10_5 is op15_31=0xeea1 & xrD & xrJ & imm10_5 {\n\txrD = xvssrlrni.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.w.d;\n\n#lasx.txt xvssrlrni.w.d mask=0x77510000\t\n#0x77510000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrlrni.w.d xrD, xrJ, imm10_6 is op16_31=0x7751 & xrD & xrJ & imm10_6 {\n\txrD = xvssrlrni.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.d.q;\n\n#lasx.txt xvssrlrni.d.q mask=0x77520000\t\n#0x77520000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrlrni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba9 & xrD & xrJ & imm10_7 {\n\txrD = xvssrlrni.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.bu.h;\n\n#lasx.txt xvssrlrni.bu.h mask=0x77544000\t\n#0x77544000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrlrni.bu.h xrD, xrJ, imm10_4 is op14_31=0x1dd51 & xrD & xrJ & imm10_4 {\n\txrD = xvssrlrni.bu.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.hu.w;\n\n#lasx.txt xvssrlrni.hu.w mask=0x77548000\t\n#0x77548000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrlrni.hu.w xrD, xrJ, imm10_5 is op15_31=0xeea9 & xrD & xrJ & imm10_5 {\n\txrD = xvssrlrni.hu.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.wu.d;\n\n#lasx.txt xvssrlrni.wu.d mask=0x77550000\t\n#0x77550000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrlrni.wu.d xrD, xrJ, imm10_6 is op16_31=0x7755 & xrD & xrJ & imm10_6 {\n\txrD = xvssrlrni.wu.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrlrni.du.q;\n\n#lasx.txt xvssrlrni.du.q mask=0x77560000\t\n#0x77560000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrlrni.du.q xrD, xrJ, imm10_7 is op17_31=0x3bab & xrD & xrJ & imm10_7 {\n\txrD = xvssrlrni.du.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvsrani.b.h;\n\n#lasx.txt xvsrani.b.h mask=0x77584000\t\n#0x77584000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrani.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd61 & xrD & xrJ & imm10_4 {\n\txrD = xvsrani.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrani.h.w;\n\n#lasx.txt xvsrani.h.w mask=0x77588000\t\n#0x77588000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrani.h.w xrD, xrJ, imm10_5 is op15_31=0xeeb1 & xrD & xrJ & imm10_5 {\n\txrD = xvsrani.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrani.w.d;\n\n#lasx.txt xvsrani.w.d mask=0x77590000\t\n#0x77590000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrani.w.d xrD, xrJ, imm10_6 is op16_31=0x7759 & xrD & xrJ & imm10_6 {\n\txrD = xvsrani.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrani.d.q;\n\n#lasx.txt xvsrani.d.q mask=0x775a0000\t\n#0x775a0000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvsrani.d.q xrD, xrJ, imm10_7 is op17_31=0x3bad & xrD & xrJ & imm10_7 {\n\txrD = xvsrani.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvsrarni.b.h;\n\n#lasx.txt xvsrarni.b.h mask=0x775c4000\t\n#0x775c4000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvsrarni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd71 & xrD & xrJ & imm10_4 {\n\txrD = xvsrarni.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvsrarni.h.w;\n\n#lasx.txt xvsrarni.h.w mask=0x775c8000\t\n#0x775c8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvsrarni.h.w xrD, xrJ, imm10_5 is op15_31=0xeeb9 & xrD & xrJ & imm10_5 {\n\txrD = xvsrarni.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvsrarni.w.d;\n\n#lasx.txt xvsrarni.w.d mask=0x775d0000\t\n#0x775d0000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvsrarni.w.d xrD, xrJ, imm10_6 is op16_31=0x775d & xrD & xrJ & imm10_6 {\n\txrD = xvsrarni.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvsrarni.d.q;\n\n#lasx.txt xvsrarni.d.q mask=0x775e0000\t\n#0x775e0000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvsrarni.d.q xrD, xrJ, imm10_7 is op17_31=0x3baf & xrD & xrJ & imm10_7 {\n\txrD = xvsrarni.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.b.h;\n\n#lasx.txt xvssrani.b.h mask=0x77604000\t\n#0x77604000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrani.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd81 & xrD & xrJ & imm10_4 {\n\txrD = xvssrani.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.h.w;\n\n#lasx.txt xvssrani.h.w mask=0x77608000\t\n#0x77608000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrani.h.w xrD, xrJ, imm10_5 is op15_31=0xeec1 & xrD & xrJ & imm10_5 {\n\txrD = xvssrani.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.w.d;\n\n#lasx.txt xvssrani.w.d mask=0x77610000\t\n#0x77610000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrani.w.d xrD, xrJ, imm10_6 is op16_31=0x7761 & xrD & xrJ & imm10_6 {\n\txrD = xvssrani.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.d.q;\n\n#lasx.txt xvssrani.d.q mask=0x77620000\t\n#0x77620000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrani.d.q xrD, xrJ, imm10_7 is op17_31=0x3bb1 & xrD & xrJ & imm10_7 {\n\txrD = xvssrani.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.bu.h;\n\n#lasx.txt xvssrani.bu.h mask=0x77644000\t\n#0x77644000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrani.bu.h xrD, xrJ, imm10_4 is op14_31=0x1dd91 & xrD & xrJ & imm10_4 {\n\txrD = xvssrani.bu.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.hu.w;\n\n#lasx.txt xvssrani.hu.w mask=0x77648000\t\n#0x77648000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrani.hu.w xrD, xrJ, imm10_5 is op15_31=0xeec9 & xrD & xrJ & imm10_5 {\n\txrD = xvssrani.hu.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.wu.d;\n\n#lasx.txt xvssrani.wu.d mask=0x77650000\t\n#0x77650000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrani.wu.d xrD, xrJ, imm10_6 is op16_31=0x7765 & xrD & xrJ & imm10_6 {\n\txrD = xvssrani.wu.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrani.du.q;\n\n#lasx.txt xvssrani.du.q mask=0x77660000\t\n#0x77660000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrani.du.q xrD, xrJ, imm10_7 is op17_31=0x3bb3 & xrD & xrJ & imm10_7 {\n\txrD = xvssrani.du.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.b.h;\n\n#lasx.txt xvssrarni.b.h mask=0x77684000\t\n#0x77684000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrarni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dda1 & xrD & xrJ & imm10_4 {\n\txrD = xvssrarni.b.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.h.w;\n\n#lasx.txt xvssrarni.h.w mask=0x77688000\t\n#0x77688000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrarni.h.w xrD, xrJ, imm10_5 is op15_31=0xeed1 & xrD & xrJ & imm10_5 {\n\txrD = xvssrarni.h.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.w.d;\n\n#lasx.txt xvssrarni.w.d mask=0x77690000\t\n#0x77690000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrarni.w.d xrD, xrJ, imm10_6 is op16_31=0x7769 & xrD & xrJ & imm10_6 {\n\txrD = xvssrarni.w.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.d.q;\n\n#lasx.txt xvssrarni.d.q mask=0x776a0000\t\n#0x776a0000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrarni.d.q xrD, xrJ, imm10_7 is op17_31=0x3bb5 & xrD & xrJ & imm10_7 {\n\txrD = xvssrarni.d.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.bu.h;\n\n#lasx.txt xvssrarni.bu.h mask=0x776c4000\t\n#0x776c4000\t0xffffc000\tx0:5,x5:5,u10:4\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0']\n:xvssrarni.bu.h xrD, xrJ, imm10_4 is op14_31=0x1ddb1 & xrD & xrJ & imm10_4 {\n\txrD = xvssrarni.bu.h(xrD, xrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.hu.w;\n\n#lasx.txt xvssrarni.hu.w mask=0x776c8000\t\n#0x776c8000\t0xffff8000\tx0:5,x5:5,u10:5\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0']\n:xvssrarni.hu.w xrD, xrJ, imm10_5 is op15_31=0xeed9 & xrD & xrJ & imm10_5 {\n\txrD = xvssrarni.hu.w(xrD, xrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.wu.d;\n\n#lasx.txt xvssrarni.wu.d mask=0x776d0000\t\n#0x776d0000\t0xffff0000\tx0:5,x5:5,u10:6\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0']\n:xvssrarni.wu.d xrD, xrJ, imm10_6 is op16_31=0x776d & xrD & xrJ & imm10_6 {\n\txrD = xvssrarni.wu.d(xrD, xrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop xvssrarni.du.q;\n\n#lasx.txt xvssrarni.du.q mask=0x776e0000\t\n#0x776e0000\t0xfffe0000\tx0:5,x5:5,u10:7\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0']\n:xvssrarni.du.q xrD, xrJ, imm10_7 is op17_31=0x3bb7 & xrD & xrJ & imm10_7 {\n\txrD = xvssrarni.du.q(xrD, xrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop xvextrins.d;\n\n#lasx.txt xvextrins.d mask=0x77800000\t\n#0x77800000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvextrins.d xrD, xrJ, imm10_8 is op18_31=0x1de0 & xrD & xrJ & imm10_8 {\n\txrD = xvextrins.d(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvextrins.w;\n\n#lasx.txt xvextrins.w mask=0x77840000\t\n#0x77840000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvextrins.w xrD, xrJ, imm10_8 is op18_31=0x1de1 & xrD & xrJ & imm10_8 {\n\txrD = xvextrins.w(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvextrins.h;\n\n#lasx.txt xvextrins.h mask=0x77880000\t\n#0x77880000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvextrins.h xrD, xrJ, imm10_8 is op18_31=0x1de2 & xrD & xrJ & imm10_8 {\n\txrD = xvextrins.h(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvextrins.b;\n\n#lasx.txt xvextrins.b mask=0x778c0000\t\n#0x778c0000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvextrins.b xrD, xrJ, imm10_8 is op18_31=0x1de3 & xrD & xrJ & imm10_8 {\n\txrD = xvextrins.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvshuf4i.b;\n\n#lasx.txt xvshuf4i.b mask=0x77900000\t\n#0x77900000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvshuf4i.b xrD, xrJ, imm10_8 is op18_31=0x1de4 & xrD & xrJ & imm10_8 {\n\txrD = xvshuf4i.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvshuf4i.h;\n\n#lasx.txt xvshuf4i.h mask=0x77940000\t\n#0x77940000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvshuf4i.h xrD, xrJ, imm10_8 is op18_31=0x1de5 & xrD & xrJ & imm10_8 {\n\txrD = xvshuf4i.h(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvshuf4i.w;\n\n#lasx.txt xvshuf4i.w mask=0x77980000\t\n#0x77980000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvshuf4i.w xrD, xrJ, imm10_8 is op18_31=0x1de6 & xrD & xrJ & imm10_8 {\n\txrD = xvshuf4i.w(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvshuf4i.d;\n\n#lasx.txt xvshuf4i.d mask=0x779c0000\t\n#0x779c0000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvshuf4i.d xrD, xrJ, imm10_8 is op18_31=0x1de7 & xrD & xrJ & imm10_8 {\n\txrD = xvshuf4i.d(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvbitseli.b;\n\n#lasx.txt xvbitseli.b mask=0x77c40000\t\n#0x77c40000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvbitseli.b xrD, xrJ, imm10_8 is op18_31=0x1df1 & xrD & xrJ & imm10_8 {\n\txrD = xvbitseli.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvandi.b;\n\n#lasx.txt xvandi.b mask=0x77d00000\t\n#0x77d00000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvandi.b xrD, xrJ, imm10_8 is op18_31=0x1df4 & xrD & xrJ & imm10_8 {\n\txrD = xvandi.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvori.b;\n\n#lasx.txt xvori.b mask=0x77d40000\t\n#0x77d40000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvori.b xrD, xrJ, imm10_8 is op18_31=0x1df5 & xrD & xrJ & imm10_8 {\n\txrD = xvori.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvxori.b;\n\n#lasx.txt xvxori.b mask=0x77d80000\t\n#0x77d80000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvxori.b xrD, xrJ, imm10_8 is op18_31=0x1df6 & xrD & xrJ & imm10_8 {\n\txrD = xvxori.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvnori.b;\n\n#lasx.txt xvnori.b mask=0x77dc0000\t\n#0x77dc0000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvnori.b xrD, xrJ, imm10_8 is op18_31=0x1df7 & xrD & xrJ & imm10_8 {\n\txrD = xvnori.b(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvldi;\n\n#lasx.txt xvldi mask=0x77e00000\t\n#0x77e00000\t0xfffc0000\tx0:5,s5:13\t['xreg0_5_s0', 'simm5_13_s0']\n:xvldi xrD,simm5_13 is op18_31=0x1df8 & xrD & simm5_13 {\n\txrD = xvldi(xrD, simm5_13:$(REGSIZE));\n}\n\ndefine pcodeop xvpermi.w;\n\n#lasx.txt xvpermi.w mask=0x77e40000\t\n#0x77e40000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvpermi.w xrD, xrJ, imm10_8 is op18_31=0x1df9 & xrD & xrJ & imm10_8 {\n\txrD = xvpermi.w(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvpermi.d;\n\n#lasx.txt xvpermi.d mask=0x77e80000\t\n#0x77e80000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvpermi.d xrD, xrJ, imm10_8 is op18_31=0x1dfa & xrD & xrJ & imm10_8 {\n\txrD = xvpermi.d(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop xvpermi.q;\n\n#lasx.txt xvpermi.q mask=0x77ec0000\t\n#0x77ec0000\t0xfffc0000\tx0:5,x5:5,u10:8\t['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0']\n:xvpermi.q xrD, xrJ, imm10_8 is op18_31=0x1dfb & xrD & xrJ & imm10_8 {\n\txrD = xvpermi.q(xrD, xrJ, imm10_8:$(REGSIZE));\n}\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/lbt.sinc", "content": "define pcodeop movgr2scr;\n\n#lbt.txt movgr2scr mask=0x00000800\t[@lbt]\n#0x00000800\t0xfffffc1c\tcr0:2, r5:5\t['scr0_2_s0', 'reg5_5_s0']\n:movgr2scr lbtrD, RJ is op10_31=0x2 & op2_4=0x0 & lbtrD & RJ {\n\tmovgr2scr(lbtrD:1, RJ);\n}\n\ndefine pcodeop movscr2gr;\n\n#lbt.txt movscr2gr mask=0x00000c00\t[@lbt]\n#0x00000c00\t0xffffff80\tr0:5,cr5:2\t['reg0_5_s0', 'scr5_2_s0']\n:movscr2gr RD, lbtrJ is op7_31=0x18 & RD & lbtrJ {\n\tRD = movscr2gr(RD, lbtrJ:1);\n}\n\ndefine pcodeop x86mttop;\n\n#lbt.txt x86mttop mask=0x00007000\t[@lbt]\n#0x00007000\t0xffffff1f\tu5:3\t['imm5_3_s0']\n:x86mttop imm5_3 is op8_31=0x70 & op0_4=0x0 & imm5_3 {\n\tx86mttop(imm5_3:$(REGSIZE));\n}\n\ndefine pcodeop x86mftop;\n\n#lbt.txt x86mftop mask=0x00007400\t[@lbt]\n#0x00007400\t0xffffffe0\tr0:5\t['reg0_5_s0']\n:x86mftop RD is op5_31=0x3a0 & RD {\n\tRD = x86mftop(RD);\n}\n\ndefine pcodeop setx86loope;\n\n#lbt.txt x86setloope mask=0x00007800\t[@lbt, @orig_name=setx86loope]\n#0x00007800\t0xfffffc00\tr0:5, r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:setx86loope RD, RJ is op10_31=0x1e & RD & RJ {\n\tRD = setx86loope(RD, RJ);\n}\n\ndefine pcodeop setx86loopne;\n\n#lbt.txt x86setloopne mask=0x00007c00\t[@lbt, @orig_name=setx86loopne]\n#0x00007c00\t0xfffffc00\tr0:5, r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:setx86loopne RD, RJ is op10_31=0x1f & RD & RJ {\n\tRD = setx86loopne(RD, RJ);\n}\n\ndefine pcodeop x86inc.b;\n\n#lbt.txt x86inc.b mask=0x00008000\t[@lbt]\n#0x00008000\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86inc.b RJ is op10_31=0x20 & op0_4=0x0 & RJ {\n\tRJ = x86inc.b(RJ);\n}\n\ndefine pcodeop x86inc.h;\n\n#lbt.txt x86inc.h mask=0x00008001\t[@lbt]\n#0x00008001\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86inc.h RJ is op10_31=0x20 & op0_4=0x1 & RJ {\n\tRJ = x86inc.h(RJ);\n}\n\ndefine pcodeop x86inc.w;\n\n#lbt.txt x86inc.w mask=0x00008002\t[@lbt]\n#0x00008002\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86inc.w RJ is op10_31=0x20 & op0_4=0x2 & RJ {\n\tRJ = x86inc.w(RJ);\n}\n\ndefine pcodeop x86inc.d;\n\n#lbt.txt x86inc.d mask=0x00008003\t[@lbt]\n#0x00008003\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86inc.d RJ is op10_31=0x20 & op0_4=0x3 & RJ {\n\tRJ = x86inc.d(RJ);\n}\n\ndefine pcodeop x86dec.b;\n\n#lbt.txt x86dec.b mask=0x00008004\t[@lbt]\n#0x00008004\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86dec.b RJ is op10_31=0x20 & op0_4=0x4 & RJ {\n\tRJ = x86dec.b(RJ);\n}\n\ndefine pcodeop x86dec.h;\n\n#lbt.txt x86dec.h mask=0x00008005\t[@lbt]\n#0x00008005\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86dec.h RJ is op10_31=0x20 & op0_4=0x5 & RJ {\n\tRJ = x86dec.h(RJ);\n}\n\ndefine pcodeop x86dec.w;\n\n#lbt.txt x86dec.w mask=0x00008006\t[@lbt]\n#0x00008006\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86dec.w RJ is op10_31=0x20 & op0_4=0x6 & RJ {\n\tRJ = x86dec.w(RJ);\n}\n\ndefine pcodeop x86dec.d;\n\n#lbt.txt x86dec.d mask=0x00008007\t[@lbt]\n#0x00008007\t0xfffffc1f\tr5:5\t['reg5_5_s0']\n:x86dec.d RJ is op10_31=0x20 & op0_4=0x7 & RJ {\n\tRJ = x86dec.d(RJ);\n}\n\ndefine pcodeop x86settm;\n\n#lbt.txt x86settm mask=0x00008008\t[@lbt]\n#0x00008008\t0xffffffff\n:x86settm is instword=0x00008008 {\n\tx86settm();\n}\n\ndefine pcodeop x86inctop;\n\n#lbt.txt x86inctop mask=0x00008009\t[@lbt]\n#0x00008009\t0xffffffff\n:x86inctop is instword=0x00008009 {\n\tx86inctop();\n}\n\ndefine pcodeop x86clrtm;\n\n#lbt.txt x86clrtm mask=0x00008028\t[@lbt]\n#0x00008028\t0xffffffff\n:x86clrtm is instword=0x00008028 {\n\tx86clrtm();\n}\n\ndefine pcodeop x86dectop;\n\n#lbt.txt x86dectop mask=0x00008029\t[@lbt]\n#0x00008029\t0xffffffff\n:x86dectop is instword=0x00008029 {\n\tx86dectop();\n}\n\ndefine pcodeop rotr.b;\n\n#lbt.txt rotr.b mask=0x001a0000\t[@lbt]\n#0x001a0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rotr.b RD, RJ, RK is op15_31=0x34 & RD & RJ & RK {\n\tRD = rotr.b(RD, RJ, RK);\n}\n\ndefine pcodeop rotr.h;\n\n#lbt.txt rotr.h mask=0x001a8000\t[@lbt]\n#0x001a8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rotr.h RD, RJ, RK is op15_31=0x35 & RD & RJ & RK {\n\tRD = rotr.h(RD, RJ, RK);\n}\n\ndefine pcodeop addu12i.w;\n\n#lbt.txt addu12i.w mask=0x00290000\t[@lbt]\n#0x00290000\t0xffff8000\tr0:5, r5:5, s10:5\t['reg0_5_s0', 'reg5_5_s0', 'simm10_5_s0']\n:addu12i.w RD, RJ, simm10_5 is op15_31=0x52 & RD & RJ & simm10_5 {\n\tRD = addu12i.w(RD, RJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop addu12i.d;\n\n#lbt.txt addu12i.d mask=0x00298000\t[@lbt]\n#0x00298000\t0xffff8000\tr0:5, r5:5, s10:5\t['reg0_5_s0', 'reg5_5_s0', 'simm10_5_s0']\n:addu12i.d RD, RJ, simm10_5 is op15_31=0x53 & RD & RJ & simm10_5 {\n\tRD = addu12i.d(RD, RJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop adc.b;\n\n#lbt.txt adc.b mask=0x00300000\t[@lbt]\n#0x00300000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:adc.b RD, RJ, RK is op15_31=0x60 & RD & RJ & RK {\n\tRD = adc.b(RD, RJ, RK);\n}\n\ndefine pcodeop adc.h;\n\n#lbt.txt adc.h mask=0x00308000\t[@lbt]\n#0x00308000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:adc.h RD, RJ, RK is op15_31=0x61 & RD & RJ & RK {\n\tRD = adc.h(RD, RJ, RK);\n}\n\ndefine pcodeop adc.w;\n\n#lbt.txt adc.w mask=0x00310000\t[@lbt]\n#0x00310000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:adc.w RD, RJ, RK is op15_31=0x62 & RD & RJ & RK {\n\tRD = adc.w(RD, RJ, RK);\n}\n\ndefine pcodeop adc.d;\n\n#lbt.txt adc.d mask=0x00318000\t[@lbt]\n#0x00318000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:adc.d RD, RJ, RK is op15_31=0x63 & RD & RJ & RK {\n\tRD = adc.d(RD, RJ, RK);\n}\n\ndefine pcodeop sbc.b;\n\n#lbt.txt sbc.b mask=0x00320000\t[@lbt]\n#0x00320000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sbc.b RD, RJ, RK is op15_31=0x64 & RD & RJ & RK {\n\tRD = sbc.b(RD, RJ, RK);\n}\n\ndefine pcodeop sbc.h;\n\n#lbt.txt sbc.h mask=0x00328000\t[@lbt]\n#0x00328000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sbc.h RD, RJ, RK is op15_31=0x65 & RD & RJ & RK {\n\tRD = sbc.h(RD, RJ, RK);\n}\n\ndefine pcodeop sbc.w;\n\n#lbt.txt sbc.w mask=0x00330000\t[@lbt]\n#0x00330000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sbc.w RD, RJ, RK is op15_31=0x66 & RD & RJ & RK {\n\tRD = sbc.w(RD, RJ, RK);\n}\n\ndefine pcodeop sbc.d;\n\n#lbt.txt sbc.d mask=0x00338000\t[@lbt]\n#0x00338000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sbc.d RD, RJ, RK is op15_31=0x67 & RD & RJ & RK {\n\tRD = sbc.d(RD, RJ, RK);\n}\n\ndefine pcodeop rcr.b;\n\n#lbt.txt rcr.b mask=0x00340000\t[@lbt]\n#0x00340000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rcr.b RD, RJ, RK is op15_31=0x68 & RD & RJ & RK {\n\tRD = rcr.b(RD, RJ, RK);\n}\n\ndefine pcodeop rcr.h;\n\n#lbt.txt rcr.h mask=0x00348000\t[@lbt]\n#0x00348000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rcr.h RD, RJ, RK is op15_31=0x69 & RD & RJ & RK {\n\tRD = rcr.h(RD, RJ, RK);\n}\n\ndefine pcodeop rcr.w;\n\n#lbt.txt rcr.w mask=0x00350000\t[@lbt]\n#0x00350000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rcr.w RD, RJ, RK is op15_31=0x6a & RD & RJ & RK {\n\tRD = rcr.w(RD, RJ, RK);\n}\n\ndefine pcodeop rcr.d;\n\n#lbt.txt rcr.d mask=0x00358000\t[@lbt]\n#0x00358000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rcr.d RD, RJ, RK is op15_31=0x6b & RD & RJ & RK {\n\tRD = rcr.d(RD, RJ, RK);\n}\n\ndefine pcodeop armmove;\n\n#lbt.txt armmove mask=0x00364000\t[@lbt]\n#0x00364000\t0xffffc000\tr0:5, r5:5,u10:4\t['reg0_5_s0', 'reg5_5_s0', 'imm10_4_s0']\n:armmove RD, RJ, imm10_4 is op14_31=0xd9 & RD & RJ & imm10_4 {\n\tRD = armmove(RD, RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop setx86j;\n\n#lbt.txt x86setj mask=0x00368000\t[@lbt, @orig_name=setx86j]\n#0x00368000\t0xffffc3e0\tr0:5,u10:4\t['reg0_5_s0', 'imm10_4_s0']\n:setx86j RD, imm10_4 is op14_31=0xda & op5_9=0x0 & RD & imm10_4 {\n\tRD = setx86j(RD, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop setarmj;\n\n#lbt.txt armsetj mask=0x0036c000\t[@lbt, @orig_name=setarmj]\n#0x0036c000\t0xffffc3e0\tr0:5,u10:4\t['reg0_5_s0', 'imm10_4_s0']\n:setarmj RD, imm10_4 is op14_31=0xdb & op5_9=0x0 & RD & imm10_4 {\n\tRD = setarmj(RD, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop armadd.w;\n\n#lbt.txt armadd.w mask=0x00370010\t[@lbt]\n#0x00370010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armadd.w RJ, RK, imm0_4 is op15_31=0x6e & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armadd.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armsub.w;\n\n#lbt.txt armsub.w mask=0x00378010\t[@lbt]\n#0x00378010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armsub.w RJ, RK, imm0_4 is op15_31=0x6f & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armsub.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armadc.w;\n\n#lbt.txt armadc.w mask=0x00380010\t[@lbt]\n#0x00380010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armadc.w RJ, RK, imm0_4 is op15_31=0x70 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armadc.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armsbc.w;\n\n#lbt.txt armsbc.w mask=0x00388010\t[@lbt]\n#0x00388010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armsbc.w RJ, RK, imm0_4 is op15_31=0x71 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armsbc.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armand.w;\n\n#lbt.txt armand.w mask=0x00390010\t[@lbt]\n#0x00390010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armand.w RJ, RK, imm0_4 is op15_31=0x72 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armand.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armor.w;\n\n#lbt.txt armor.w mask=0x00398010\t[@lbt]\n#0x00398010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armor.w RJ, RK, imm0_4 is op15_31=0x73 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armor.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armxor.w;\n\n#lbt.txt armxor.w mask=0x003a0010\t[@lbt]\n#0x003a0010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armxor.w RJ, RK, imm0_4 is op15_31=0x74 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armxor.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armsll.w;\n\n#lbt.txt armsll.w mask=0x003a8010\t[@lbt]\n#0x003a8010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armsll.w RJ, RK, imm0_4 is op15_31=0x75 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armsll.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armsrl.w;\n\n#lbt.txt armsrl.w mask=0x003b0010\t[@lbt]\n#0x003b0010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armsrl.w RJ, RK, imm0_4 is op15_31=0x76 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armsrl.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armsra.w;\n\n#lbt.txt armsra.w mask=0x003b8010\t[@lbt]\n#0x003b8010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armsra.w RJ, RK, imm0_4 is op15_31=0x77 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armsra.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armrotr.w;\n\n#lbt.txt armrotr.w mask=0x003c0010\t[@lbt]\n#0x003c0010\t0xffff8010\tr5:5, r10:5,u0:4\t['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0']\n:armrotr.w RJ, RK, imm0_4 is op15_31=0x78 & op4_4=0x1 & RJ & RK & imm0_4 {\n\tRJ = armrotr.w(RJ, RK, imm0_4:$(REGSIZE));\n}\n\ndefine pcodeop armslli.w;\n\n#lbt.txt armslli.w mask=0x003c8010\t[@lbt, @orig_fmt=JUk5Ud4]\n#0x003c8010\t0xffff8010\tr5:5,u10:5,u0:4\t['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0']\n:armslli.w RJ, imm0_4, imm10_5 is op15_31=0x79 & op4_4=0x1 & RJ & imm0_4 & imm10_5 {\n\tRJ = armslli.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop armsrli.w;\n\n#lbt.txt armsrli.w mask=0x003d0010\t[@lbt, @orig_fmt=JUk5Ud4]\n#0x003d0010\t0xffff8010\tr5:5,u10:5,u0:4\t['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0']\n:armsrli.w RJ, imm0_4, imm10_5 is op15_31=0x7a & op4_4=0x1 & RJ & imm0_4 & imm10_5 {\n\tRJ = armsrli.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop armsrai.w;\n\n#lbt.txt armsrai.w mask=0x003d8010\t[@lbt, @orig_fmt=JUk5Ud4]\n#0x003d8010\t0xffff8010\tr5:5,u10:5,u0:4\t['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0']\n:armsrai.w RJ, imm0_4, imm10_5 is op15_31=0x7b & op4_4=0x1 & RJ & imm0_4 & imm10_5 {\n\tRJ = armsrai.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop armrotri.w;\n\n#lbt.txt armrotri.w mask=0x003e0010\t[@lbt, @orig_fmt=JUk5Ud4]\n#0x003e0010\t0xffff8010\tr5:5,u10:5,u0:4\t['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0']\n:armrotri.w RJ, imm0_4, imm10_5 is op15_31=0x7c & op4_4=0x1 & RJ & imm0_4 & imm10_5 {\n\tRJ = armrotri.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86mul.b;\n\n#lbt.txt x86mul.b mask=0x003e8000\t[@lbt]\n#0x003e8000\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.b RJ, RK is op15_31=0x7d & op0_4=0x0 & RJ & RK {\n\tRJ = x86mul.b(RJ, RK);\n}\n\ndefine pcodeop x86mul.h;\n\n#lbt.txt x86mul.h mask=0x003e8001\t[@lbt]\n#0x003e8001\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.h RJ, RK is op15_31=0x7d & op0_4=0x1 & RJ & RK {\n\tRJ = x86mul.h(RJ, RK);\n}\n\ndefine pcodeop x86mul.w;\n\n#lbt.txt x86mul.w mask=0x003e8002\t[@lbt]\n#0x003e8002\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.w RJ, RK is op15_31=0x7d & op0_4=0x2 & RJ & RK {\n\tRJ = x86mul.w(RJ, RK);\n}\n\ndefine pcodeop x86mul.d;\n\n#lbt.txt x86mul.d mask=0x003e8003\t[@lbt]\n#0x003e8003\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.d RJ, RK is op15_31=0x7d & op0_4=0x3 & RJ & RK {\n\tRJ = x86mul.d(RJ, RK);\n}\n\ndefine pcodeop x86mul.bu;\n\n#lbt.txt x86mul.bu mask=0x003e8004\t[@lbt]\n#0x003e8004\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.bu RJ, RK is op15_31=0x7d & op0_4=0x4 & RJ & RK {\n\tRJ = x86mul.bu(RJ, RK);\n}\n\ndefine pcodeop x86mul.hu;\n\n#lbt.txt x86mul.hu mask=0x003e8005\t[@lbt]\n#0x003e8005\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.hu RJ, RK is op15_31=0x7d & op0_4=0x5 & RJ & RK {\n\tRJ = x86mul.hu(RJ, RK);\n}\n\ndefine pcodeop x86mul.wu;\n\n#lbt.txt x86mul.wu mask=0x003e8006\t[@lbt]\n#0x003e8006\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.wu RJ, RK is op15_31=0x7d & op0_4=0x6 & RJ & RK {\n\tRJ = x86mul.wu(RJ, RK);\n}\n\ndefine pcodeop x86mul.du;\n\n#lbt.txt x86mul.du mask=0x003e8007\t[@lbt]\n#0x003e8007\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86mul.du RJ, RK is op15_31=0x7d & op0_4=0x7 & RJ & RK {\n\tRJ = x86mul.du(RJ, RK);\n}\n\ndefine pcodeop x86add.wu;\n\n#lbt.txt x86add.wu mask=0x003f0000\t[@lbt]\n#0x003f0000\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86add.wu RJ, RK is op15_31=0x7e & op0_4=0x0 & RJ & RK {\n\tRJ = x86add.wu(RJ, RK);\n}\n\ndefine pcodeop x86add.du;\n\n#lbt.txt x86add.du mask=0x003f0001\t[@lbt]\n#0x003f0001\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86add.du RJ, RK is op15_31=0x7e & op0_4=0x1 & RJ & RK {\n\tRJ = x86add.du(RJ, RK);\n}\n\ndefine pcodeop x86sub.wu;\n\n#lbt.txt x86sub.wu mask=0x003f0002\t[@lbt]\n#0x003f0002\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sub.wu RJ, RK is op15_31=0x7e & op0_4=0x2 & RJ & RK {\n\tRJ = x86sub.wu(RJ, RK);\n}\n\ndefine pcodeop x86sub.du;\n\n#lbt.txt x86sub.du mask=0x003f0003\t[@lbt]\n#0x003f0003\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sub.du RJ, RK is op15_31=0x7e & op0_4=0x3 & RJ & RK {\n\tRJ = x86sub.du(RJ, RK);\n}\n\ndefine pcodeop x86add.b;\n\n#lbt.txt x86add.b mask=0x003f0004\t[@lbt]\n#0x003f0004\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86add.b RJ, RK is op15_31=0x7e & op0_4=0x4 & RJ & RK {\n\tRJ = x86add.b(RJ, RK);\n}\n\ndefine pcodeop x86add.h;\n\n#lbt.txt x86add.h mask=0x003f0005\t[@lbt]\n#0x003f0005\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86add.h RJ, RK is op15_31=0x7e & op0_4=0x5 & RJ & RK {\n\tRJ = x86add.h(RJ, RK);\n}\n\ndefine pcodeop x86add.w;\n\n#lbt.txt x86add.w mask=0x003f0006\t[@lbt]\n#0x003f0006\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86add.w RJ, RK is op15_31=0x7e & op0_4=0x6 & RJ & RK {\n\tRJ = x86add.w(RJ, RK);\n}\n\ndefine pcodeop x86add.d;\n\n#lbt.txt x86add.d mask=0x003f0007\t[@lbt]\n#0x003f0007\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86add.d RJ, RK is op15_31=0x7e & op0_4=0x7 & RJ & RK {\n\tRJ = x86add.d(RJ, RK);\n}\n\ndefine pcodeop x86sub.b;\n\n#lbt.txt x86sub.b mask=0x003f0008\t[@lbt]\n#0x003f0008\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sub.b RJ, RK is op15_31=0x7e & op0_4=0x8 & RJ & RK {\n\tRJ = x86sub.b(RJ, RK);\n}\n\ndefine pcodeop x86sub.h;\n\n#lbt.txt x86sub.h mask=0x003f0009\t[@lbt]\n#0x003f0009\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sub.h RJ, RK is op15_31=0x7e & op0_4=0x9 & RJ & RK {\n\tRJ = x86sub.h(RJ, RK);\n}\n\ndefine pcodeop x86sub.w;\n\n#lbt.txt x86sub.w mask=0x003f000a\t[@lbt]\n#0x003f000a\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sub.w RJ, RK is op15_31=0x7e & op0_4=0xa & RJ & RK {\n\tRJ = x86sub.w(RJ, RK);\n}\n\ndefine pcodeop x86sub.d;\n\n#lbt.txt x86sub.d mask=0x003f000b\t[@lbt]\n#0x003f000b\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sub.d RJ, RK is op15_31=0x7e & op0_4=0xb & RJ & RK {\n\tRJ = x86sub.d(RJ, RK);\n}\n\ndefine pcodeop x86adc.b;\n\n#lbt.txt x86adc.b mask=0x003f000c\t[@lbt]\n#0x003f000c\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86adc.b RJ, RK is op15_31=0x7e & op0_4=0xc & RJ & RK {\n\tRJ = x86adc.b(RJ, RK);\n}\n\ndefine pcodeop x86adc.h;\n\n#lbt.txt x86adc.h mask=0x003f000d\t[@lbt]\n#0x003f000d\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86adc.h RJ, RK is op15_31=0x7e & op0_4=0xd & RJ & RK {\n\tRJ = x86adc.h(RJ, RK);\n}\n\ndefine pcodeop x86adc.w;\n\n#lbt.txt x86adc.w mask=0x003f000e\t[@lbt]\n#0x003f000e\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86adc.w RJ, RK is op15_31=0x7e & op0_4=0xe & RJ & RK {\n\tRJ = x86adc.w(RJ, RK);\n}\n\ndefine pcodeop x86adc.d;\n\n#lbt.txt x86adc.d mask=0x003f000f\t[@lbt]\n#0x003f000f\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86adc.d RJ, RK is op15_31=0x7e & op0_4=0xf & RJ & RK {\n\tRJ = x86adc.d(RJ, RK);\n}\n\ndefine pcodeop x86sbc.b;\n\n#lbt.txt x86sbc.b mask=0x003f0010\t[@lbt]\n#0x003f0010\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sbc.b RJ, RK is op15_31=0x7e & op0_4=0x10 & RJ & RK {\n\tRJ = x86sbc.b(RJ, RK);\n}\n\ndefine pcodeop x86sbc.h;\n\n#lbt.txt x86sbc.h mask=0x003f0011\t[@lbt]\n#0x003f0011\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sbc.h RJ, RK is op15_31=0x7e & op0_4=0x11 & RJ & RK {\n\tRJ = x86sbc.h(RJ, RK);\n}\n\ndefine pcodeop x86sbc.w;\n\n#lbt.txt x86sbc.w mask=0x003f0012\t[@lbt]\n#0x003f0012\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sbc.w RJ, RK is op15_31=0x7e & op0_4=0x12 & RJ & RK {\n\tRJ = x86sbc.w(RJ, RK);\n}\n\ndefine pcodeop x86sbc.d;\n\n#lbt.txt x86sbc.d mask=0x003f0013\t[@lbt]\n#0x003f0013\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sbc.d RJ, RK is op15_31=0x7e & op0_4=0x13 & RJ & RK {\n\tRJ = x86sbc.d(RJ, RK);\n}\n\ndefine pcodeop x86sll.b;\n\n#lbt.txt x86sll.b mask=0x003f0014\t[@lbt]\n#0x003f0014\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sll.b RJ, RK is op15_31=0x7e & op0_4=0x14 & RJ & RK {\n\tRJ = x86sll.b(RJ, RK);\n}\n\ndefine pcodeop x86sll.h;\n\n#lbt.txt x86sll.h mask=0x003f0015\t[@lbt]\n#0x003f0015\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sll.h RJ, RK is op15_31=0x7e & op0_4=0x15 & RJ & RK {\n\tRJ = x86sll.h(RJ, RK);\n}\n\ndefine pcodeop x86sll.w;\n\n#lbt.txt x86sll.w mask=0x003f0016\t[@lbt]\n#0x003f0016\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sll.w RJ, RK is op15_31=0x7e & op0_4=0x16 & RJ & RK {\n\tRJ = x86sll.w(RJ, RK);\n}\n\ndefine pcodeop x86sll.d;\n\n#lbt.txt x86sll.d mask=0x003f0017\t[@lbt]\n#0x003f0017\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sll.d RJ, RK is op15_31=0x7e & op0_4=0x17 & RJ & RK {\n\tRJ = x86sll.d(RJ, RK);\n}\n\ndefine pcodeop x86srl.b;\n\n#lbt.txt x86srl.b mask=0x003f0018\t[@lbt]\n#0x003f0018\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86srl.b RJ, RK is op15_31=0x7e & op0_4=0x18 & RJ & RK {\n\tRJ = x86srl.b(RJ, RK);\n}\n\ndefine pcodeop x86srl.h;\n\n#lbt.txt x86srl.h mask=0x003f0019\t[@lbt]\n#0x003f0019\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86srl.h RJ, RK is op15_31=0x7e & op0_4=0x19 & RJ & RK {\n\tRJ = x86srl.h(RJ, RK);\n}\n\ndefine pcodeop x86srl.w;\n\n#lbt.txt x86srl.w mask=0x003f001a\t[@lbt]\n#0x003f001a\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86srl.w RJ, RK is op15_31=0x7e & op0_4=0x1a & RJ & RK {\n\tRJ = x86srl.w(RJ, RK);\n}\n\ndefine pcodeop x86srl.d;\n\n#lbt.txt x86srl.d mask=0x003f001b\t[@lbt]\n#0x003f001b\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86srl.d RJ, RK is op15_31=0x7e & op0_4=0x1b & RJ & RK {\n\tRJ = x86srl.d(RJ, RK);\n}\n\ndefine pcodeop x86sra.b;\n\n#lbt.txt x86sra.b mask=0x003f001c\t[@lbt]\n#0x003f001c\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sra.b RJ, RK is op15_31=0x7e & op0_4=0x1c & RJ & RK {\n\tRJ = x86sra.b(RJ, RK);\n}\n\ndefine pcodeop x86sra.h;\n\n#lbt.txt x86sra.h mask=0x003f001d\t[@lbt]\n#0x003f001d\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sra.h RJ, RK is op15_31=0x7e & op0_4=0x1d & RJ & RK {\n\tRJ = x86sra.h(RJ, RK);\n}\n\ndefine pcodeop x86sra.w;\n\n#lbt.txt x86sra.w mask=0x003f001e\t[@lbt]\n#0x003f001e\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sra.w RJ, RK is op15_31=0x7e & op0_4=0x1e & RJ & RK {\n\tRJ = x86sra.w(RJ, RK);\n}\n\ndefine pcodeop x86sra.d;\n\n#lbt.txt x86sra.d mask=0x003f001f\t[@lbt]\n#0x003f001f\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86sra.d RJ, RK is op15_31=0x7e & op0_4=0x1f & RJ & RK {\n\tRJ = x86sra.d(RJ, RK);\n}\n\ndefine pcodeop x86rotr.b;\n\n#lbt.txt x86rotr.b mask=0x003f8000\t[@lbt]\n#0x003f8000\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotr.b RJ, RK is op15_31=0x7f & op0_4=0x0 & RJ & RK {\n\tRJ = x86rotr.b(RJ, RK);\n}\n\ndefine pcodeop x86rotr.h;\n\n#lbt.txt x86rotr.h mask=0x003f8001\t[@lbt]\n#0x003f8001\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotr.h RJ, RK is op15_31=0x7f & op0_4=0x1 & RJ & RK {\n\tRJ = x86rotr.h(RJ, RK);\n}\n\ndefine pcodeop x86rotr.d;\n\n#lbt.txt x86rotr.d mask=0x003f8002\t[@lbt]\n#0x003f8002\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotr.d RJ, RK is op15_31=0x7f & op0_4=0x2 & RJ & RK {\n\tRJ = x86rotr.d(RJ, RK);\n}\n\ndefine pcodeop x86rotr.w;\n\n#lbt.txt x86rotr.w mask=0x003f8003\t[@lbt]\n#0x003f8003\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotr.w RJ, RK is op15_31=0x7f & op0_4=0x3 & RJ & RK {\n\tRJ = x86rotr.w(RJ, RK);\n}\n\ndefine pcodeop x86rotl.b;\n\n#lbt.txt x86rotl.b mask=0x003f8004\t[@lbt]\n#0x003f8004\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotl.b RJ, RK is op15_31=0x7f & op0_4=0x4 & RJ & RK {\n\tRJ = x86rotl.b(RJ, RK);\n}\n\ndefine pcodeop x86rotl.h;\n\n#lbt.txt x86rotl.h mask=0x003f8005\t[@lbt]\n#0x003f8005\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotl.h RJ, RK is op15_31=0x7f & op0_4=0x5 & RJ & RK {\n\tRJ = x86rotl.h(RJ, RK);\n}\n\ndefine pcodeop x86rotl.w;\n\n#lbt.txt x86rotl.w mask=0x003f8006\t[@lbt]\n#0x003f8006\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotl.w RJ, RK is op15_31=0x7f & op0_4=0x6 & RJ & RK {\n\tRJ = x86rotl.w(RJ, RK);\n}\n\ndefine pcodeop x86rotl.d;\n\n#lbt.txt x86rotl.d mask=0x003f8007\t[@lbt]\n#0x003f8007\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rotl.d RJ, RK is op15_31=0x7f & op0_4=0x7 & RJ & RK {\n\tRJ = x86rotl.d(RJ, RK);\n}\n\ndefine pcodeop x86rcr.b;\n\n#lbt.txt x86rcr.b mask=0x003f8008\t[@lbt]\n#0x003f8008\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcr.b RJ, RK is op15_31=0x7f & op0_4=0x8 & RJ & RK {\n\tRJ = x86rcr.b(RJ, RK);\n}\n\ndefine pcodeop x86rcr.h;\n\n#lbt.txt x86rcr.h mask=0x003f8009\t[@lbt]\n#0x003f8009\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcr.h RJ, RK is op15_31=0x7f & op0_4=0x9 & RJ & RK {\n\tRJ = x86rcr.h(RJ, RK);\n}\n\ndefine pcodeop x86rcr.w;\n\n#lbt.txt x86rcr.w mask=0x003f800a\t[@lbt]\n#0x003f800a\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcr.w RJ, RK is op15_31=0x7f & op0_4=0xa & RJ & RK {\n\tRJ = x86rcr.w(RJ, RK);\n}\n\ndefine pcodeop x86rcr.d;\n\n#lbt.txt x86rcr.d mask=0x003f800b\t[@lbt]\n#0x003f800b\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcr.d RJ, RK is op15_31=0x7f & op0_4=0xb & RJ & RK {\n\tRJ = x86rcr.d(RJ, RK);\n}\n\ndefine pcodeop x86rcl.b;\n\n#lbt.txt x86rcl.b mask=0x003f800c\t[@lbt]\n#0x003f800c\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcl.b RJ, RK is op15_31=0x7f & op0_4=0xc & RJ & RK {\n\tRJ = x86rcl.b(RJ, RK);\n}\n\ndefine pcodeop x86rcl.h;\n\n#lbt.txt x86rcl.h mask=0x003f800d\t[@lbt]\n#0x003f800d\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcl.h RJ, RK is op15_31=0x7f & op0_4=0xd & RJ & RK {\n\tRJ = x86rcl.h(RJ, RK);\n}\n\ndefine pcodeop x86rcl.w;\n\n#lbt.txt x86rcl.w mask=0x003f800e\t[@lbt]\n#0x003f800e\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcl.w RJ, RK is op15_31=0x7f & op0_4=0xe & RJ & RK {\n\tRJ = x86rcl.w(RJ, RK);\n}\n\ndefine pcodeop x86rcl.d;\n\n#lbt.txt x86rcl.d mask=0x003f800f\t[@lbt]\n#0x003f800f\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86rcl.d RJ, RK is op15_31=0x7f & op0_4=0xf & RJ & RK {\n\tRJ = x86rcl.d(RJ, RK);\n}\n\ndefine pcodeop x86and.b;\n\n#lbt.txt x86and.b mask=0x003f8010\t[@lbt]\n#0x003f8010\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86and.b RJ, RK is op15_31=0x7f & op0_4=0x10 & RJ & RK {\n\tRJ = x86and.b(RJ, RK);\n}\n\ndefine pcodeop x86and.h;\n\n#lbt.txt x86and.h mask=0x003f8011\t[@lbt]\n#0x003f8011\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86and.h RJ, RK is op15_31=0x7f & op0_4=0x11 & RJ & RK {\n\tRJ = x86and.h(RJ, RK);\n}\n\ndefine pcodeop x86and.w;\n\n#lbt.txt x86and.w mask=0x003f8012\t[@lbt]\n#0x003f8012\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86and.w RJ, RK is op15_31=0x7f & op0_4=0x12 & RJ & RK {\n\tRJ = x86and.w(RJ, RK);\n}\n\ndefine pcodeop x86and.d;\n\n#lbt.txt x86and.d mask=0x003f8013\t[@lbt]\n#0x003f8013\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86and.d RJ, RK is op15_31=0x7f & op0_4=0x13 & RJ & RK {\n\tRJ = x86and.d(RJ, RK);\n}\n\ndefine pcodeop x86or.b;\n\n#lbt.txt x86or.b mask=0x003f8014\t[@lbt]\n#0x003f8014\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86or.b RJ, RK is op15_31=0x7f & op0_4=0x14 & RJ & RK {\n\tRJ = x86or.b(RJ, RK);\n}\n\ndefine pcodeop x86or.h;\n\n#lbt.txt x86or.h mask=0x003f8015\t[@lbt]\n#0x003f8015\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86or.h RJ, RK is op15_31=0x7f & op0_4=0x15 & RJ & RK {\n\tRJ = x86or.h(RJ, RK);\n}\n\ndefine pcodeop x86or.w;\n\n#lbt.txt x86or.w mask=0x003f8016\t[@lbt]\n#0x003f8016\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86or.w RJ, RK is op15_31=0x7f & op0_4=0x16 & RJ & RK {\n\tRJ = x86or.w(RJ, RK);\n}\n\ndefine pcodeop x86or.d;\n\n#lbt.txt x86or.d mask=0x003f8017\t[@lbt]\n#0x003f8017\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86or.d RJ, RK is op15_31=0x7f & op0_4=0x17 & RJ & RK {\n\tRJ = x86or.d(RJ, RK);\n}\n\ndefine pcodeop x86xor.b;\n\n#lbt.txt x86xor.b mask=0x003f8018\t[@lbt]\n#0x003f8018\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86xor.b RJ, RK is op15_31=0x7f & op0_4=0x18 & RJ & RK {\n\tRJ = x86xor.b(RJ, RK);\n}\n\ndefine pcodeop x86xor.h;\n\n#lbt.txt x86xor.h mask=0x003f8019\t[@lbt]\n#0x003f8019\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86xor.h RJ, RK is op15_31=0x7f & op0_4=0x19 & RJ & RK {\n\tRJ = x86xor.h(RJ, RK);\n}\n\ndefine pcodeop x86xor.w;\n\n#lbt.txt x86xor.w mask=0x003f801a\t[@lbt]\n#0x003f801a\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86xor.w RJ, RK is op15_31=0x7f & op0_4=0x1a & RJ & RK {\n\tRJ = x86xor.w(RJ, RK);\n}\n\ndefine pcodeop x86xor.d;\n\n#lbt.txt x86xor.d mask=0x003f801b\t[@lbt]\n#0x003f801b\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:x86xor.d RJ, RK is op15_31=0x7f & op0_4=0x1b & RJ & RK {\n\tRJ = x86xor.d(RJ, RK);\n}\n\ndefine pcodeop armnot.w;\n\n#lbt.txt armnot.w mask=0x003fc01c\t[@lbt]\n#0x003fc01c\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:armnot.w RJ, imm10_4 is op14_31=0xff & op0_4=0x1c & RJ & imm10_4 {\n\tRJ = armnot.w(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop armmov.w;\n\n#lbt.txt armmov.w mask=0x003fc01d\t[@lbt]\n#0x003fc01d\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:armmov.w RJ, imm10_4 is op14_31=0xff & op0_4=0x1d & RJ & imm10_4 {\n\tRJ = armmov.w(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop armmov.d;\n\n#lbt.txt armmov.d mask=0x003fc01e\t[@lbt]\n#0x003fc01e\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:armmov.d RJ, imm10_4 is op14_31=0xff & op0_4=0x1e & RJ & imm10_4 {\n\tRJ = armmov.d(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop armrrx.w;\n\n#lbt.txt armrrx.w mask=0x003fc01f\t[@lbt]\n#0x003fc01f\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:armrrx.w RJ, imm10_4 is op14_31=0xff & op0_4=0x1f & RJ & imm10_4 {\n\tRJ = armrrx.w(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop rotri.b;\n\n#lbt.txt rotri.b mask=0x004c2000\t[@lbt]\n#0x004c2000\t0xffffe000\tr0:5, r5:5,u10:3\t['reg0_5_s0', 'reg5_5_s0', 'imm10_3_s0']\n:rotri.b RD, RJ, imm10_3 is op13_31=0x261 & RD & RJ & imm10_3 {\n\tRD = rotri.b(RD, RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop rotri.h;\n\n#lbt.txt rotri.h mask=0x004c4000\t[@lbt]\n#0x004c4000\t0xffffc000\tr0:5, r5:5,u10:4\t['reg0_5_s0', 'reg5_5_s0', 'imm10_4_s0']\n:rotri.h RD, RJ, imm10_4 is op14_31=0x131 & RD & RJ & imm10_4 {\n\tRD = rotri.h(RD, RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop rcri.b;\n\n#lbt.txt rcri.b mask=0x00502000\t[@lbt]\n#0x00502000\t0xffffe000\tr0:5, r5:5,u10:3\t['reg0_5_s0', 'reg5_5_s0', 'imm10_3_s0']\n:rcri.b RD, RJ, imm10_3 is op13_31=0x281 & RD & RJ & imm10_3 {\n\tRD = rcri.b(RD, RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop rcri.h;\n\n#lbt.txt rcri.h mask=0x00504000\t[@lbt]\n#0x00504000\t0xffffc000\tr0:5, r5:5,u10:4\t['reg0_5_s0', 'reg5_5_s0', 'imm10_4_s0']\n:rcri.h RD, RJ, imm10_4 is op14_31=0x141 & RD & RJ & imm10_4 {\n\tRD = rcri.h(RD, RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop rcri.w;\n\n#lbt.txt rcri.w mask=0x00508000\t[@lbt]\n#0x00508000\t0xffff8000\tr0:5, r5:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0']\n:rcri.w RD, RJ, imm10_5 is op15_31=0xa1 & RD & RJ & imm10_5 {\n\tRD = rcri.w(RD, RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop rcri.d;\n\n#lbt.txt rcri.d mask=0x00510000\t[@lbt]\n#0x00510000\t0xffff0000\tr0:5, r5:5,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0']\n:rcri.d RD, RJ, imm10_6 is op16_31=0x51 & RD & RJ & imm10_6 {\n\tRD = rcri.d(RD, RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86slli.b;\n\n#lbt.txt x86slli.b mask=0x00542000\t[@lbt]\n#0x00542000\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86slli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x0 & RJ & imm10_3 {\n\tRJ = x86slli.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86srli.b;\n\n#lbt.txt x86srli.b mask=0x00542004\t[@lbt]\n#0x00542004\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86srli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x4 & RJ & imm10_3 {\n\tRJ = x86srli.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86srai.b;\n\n#lbt.txt x86srai.b mask=0x00542008\t[@lbt]\n#0x00542008\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86srai.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x8 & RJ & imm10_3 {\n\tRJ = x86srai.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86rotri.b;\n\n#lbt.txt x86rotri.b mask=0x0054200c\t[@lbt]\n#0x0054200c\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86rotri.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0xc & RJ & imm10_3 {\n\tRJ = x86rotri.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86rcri.b;\n\n#lbt.txt x86rcri.b mask=0x00542010\t[@lbt]\n#0x00542010\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86rcri.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x10 & RJ & imm10_3 {\n\tRJ = x86rcri.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86rotli.b;\n\n#lbt.txt x86rotli.b mask=0x00542014\t[@lbt]\n#0x00542014\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86rotli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x14 & RJ & imm10_3 {\n\tRJ = x86rotli.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86rcli.b;\n\n#lbt.txt x86rcli.b mask=0x00542018\t[@lbt]\n#0x00542018\t0xffffe01f\tr5:5,u10:3\t['reg5_5_s0', 'imm10_3_s0']\n:x86rcli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x18 & RJ & imm10_3 {\n\tRJ = x86rcli.b(RJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop x86slli.h;\n\n#lbt.txt x86slli.h mask=0x00544001\t[@lbt]\n#0x00544001\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86slli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x1 & RJ & imm10_4 {\n\tRJ = x86slli.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86srli.h;\n\n#lbt.txt x86srli.h mask=0x00544005\t[@lbt]\n#0x00544005\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86srli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x5 & RJ & imm10_4 {\n\tRJ = x86srli.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86srai.h;\n\n#lbt.txt x86srai.h mask=0x00544009\t[@lbt]\n#0x00544009\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86srai.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x9 & RJ & imm10_4 {\n\tRJ = x86srai.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86rotri.h;\n\n#lbt.txt x86rotri.h mask=0x0054400d\t[@lbt]\n#0x0054400d\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86rotri.h RJ, imm10_4 is op14_31=0x151 & op0_4=0xd & RJ & imm10_4 {\n\tRJ = x86rotri.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86rcri.h;\n\n#lbt.txt x86rcri.h mask=0x00544011\t[@lbt]\n#0x00544011\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86rcri.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x11 & RJ & imm10_4 {\n\tRJ = x86rcri.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86rotli.h;\n\n#lbt.txt x86rotli.h mask=0x00544015\t[@lbt]\n#0x00544015\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86rotli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x15 & RJ & imm10_4 {\n\tRJ = x86rotli.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86rcli.h;\n\n#lbt.txt x86rcli.h mask=0x00544019\t[@lbt]\n#0x00544019\t0xffffc01f\tr5:5,u10:4\t['reg5_5_s0', 'imm10_4_s0']\n:x86rcli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x19 & RJ & imm10_4 {\n\tRJ = x86rcli.h(RJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop x86slli.w;\n\n#lbt.txt x86slli.w mask=0x00548002\t[@lbt]\n#0x00548002\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86slli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x2 & RJ & imm10_5 {\n\tRJ = x86slli.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86srli.w;\n\n#lbt.txt x86srli.w mask=0x00548006\t[@lbt]\n#0x00548006\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86srli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x6 & RJ & imm10_5 {\n\tRJ = x86srli.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86srai.w;\n\n#lbt.txt x86srai.w mask=0x0054800a\t[@lbt]\n#0x0054800a\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86srai.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0xa & RJ & imm10_5 {\n\tRJ = x86srai.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86rotri.w;\n\n#lbt.txt x86rotri.w mask=0x0054800e\t[@lbt]\n#0x0054800e\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86rotri.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0xe & RJ & imm10_5 {\n\tRJ = x86rotri.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86rcri.w;\n\n#lbt.txt x86rcri.w mask=0x00548012\t[@lbt]\n#0x00548012\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86rcri.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x12 & RJ & imm10_5 {\n\tRJ = x86rcri.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86rotli.w;\n\n#lbt.txt x86rotli.w mask=0x00548016\t[@lbt]\n#0x00548016\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86rotli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x16 & RJ & imm10_5 {\n\tRJ = x86rotli.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86rcli.w;\n\n#lbt.txt x86rcli.w mask=0x0054801a\t[@lbt]\n#0x0054801a\t0xffff801f\tr5:5,u10:5\t['reg5_5_s0', 'imm10_5_s0']\n:x86rcli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x1a & RJ & imm10_5 {\n\tRJ = x86rcli.w(RJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop x86slli.d;\n\n#lbt.txt x86slli.d mask=0x00550003\t[@lbt]\n#0x00550003\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86slli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x3 & RJ & imm10_6 {\n\tRJ = x86slli.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86srli.d;\n\n#lbt.txt x86srli.d mask=0x00550007\t[@lbt]\n#0x00550007\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86srli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x7 & RJ & imm10_6 {\n\tRJ = x86srli.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86srai.d;\n\n#lbt.txt x86srai.d mask=0x0055000b\t[@lbt]\n#0x0055000b\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86srai.d RJ, imm10_6 is op16_31=0x55 & op0_4=0xb & RJ & imm10_6 {\n\tRJ = x86srai.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86rotri.d;\n\n#lbt.txt x86rotri.d mask=0x0055000f\t[@lbt]\n#0x0055000f\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86rotri.d RJ, imm10_6 is op16_31=0x55 & op0_4=0xf & RJ & imm10_6 {\n\tRJ = x86rotri.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86rcri.d;\n\n#lbt.txt x86rcri.d mask=0x00550013\t[@lbt]\n#0x00550013\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86rcri.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x13 & RJ & imm10_6 {\n\tRJ = x86rcri.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86rotli.d;\n\n#lbt.txt x86rotli.d mask=0x00550017\t[@lbt]\n#0x00550017\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86rotli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x17 & RJ & imm10_6 {\n\tRJ = x86rotli.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86rcli.d;\n\n#lbt.txt x86rcli.d mask=0x0055001b\t[@lbt]\n#0x0055001b\t0xffff001f\tr5:5,u10:6\t['reg5_5_s0', 'imm10_6_s0']\n:x86rcli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x1b & RJ & imm10_6 {\n\tRJ = x86rcli.d(RJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop x86settag;\n\n#lbt.txt x86settag mask=0x00580000\t[@lbt]\n#0x00580000\t0xfffc0000\tr0:5,u5:5,u10:8\t['reg0_5_s0', 'imm5_5_s0', 'imm10_8_s0']\n:x86settag RD, imm5_5, imm10_8 is op18_31=0x16 & RD & imm5_5 & imm10_8 {\n\tRD = x86settag(RD, imm5_5:$(REGSIZE), imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop x86mfflag;\n\n#lbt.txt x86mfflag mask=0x005c0000\t[@lbt]\n#0x005c0000\t0xfffc03e0\tr0:5,u10:8\t['reg0_5_s0', 'imm10_8_s0']\n:x86mfflag RD, imm10_8 is op18_31=0x17 & op5_9=0x0 & RD & imm10_8 {\n\tRD = x86mfflag(RD, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop x86mtflag;\n\n#lbt.txt x86mtflag mask=0x005c0020\t[@lbt]\n#0x005c0020\t0xfffc03e0\tr0:5,u10:8\t['reg0_5_s0', 'imm10_8_s0']\n:x86mtflag RD, imm10_8 is op18_31=0x17 & op5_9=0x1 & RD & imm10_8 {\n\tRD = x86mtflag(RD, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop armmfflag;\n\n#lbt.txt armmfflag mask=0x005c0040\t[@lbt]\n#0x005c0040\t0xfffc03e0\tr0:5,u10:8\t['reg0_5_s0', 'imm10_8_s0']\n:armmfflag RD, imm10_8 is op18_31=0x17 & op5_9=0x2 & RD & imm10_8 {\n\tRD = armmfflag(RD, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop armmtflag;\n\n#lbt.txt armmtflag mask=0x005c0060\t[@lbt]\n#0x005c0060\t0xfffc03e0\tr0:5,u10:8\t['reg0_5_s0', 'imm10_8_s0']\n:armmtflag RD, imm10_8 is op18_31=0x17 & op5_9=0x3 & RD & imm10_8 {\n\tRD = armmtflag(RD, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop fcvt.ld.d;\n\n#lbt.txt fcvt.ld.d mask=0x0114e000\t[@lbt]\n#0x0114e000\t0xfffffc00\tf0:5,f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fcvt.ld.d drD,drJ is op10_31=0x4538 & drD & drJ {\n\tdrD = fcvt.ld.d(drD, drJ);\n}\n\ndefine pcodeop fcvt.ud.d;\n\n#lbt.txt fcvt.ud.d mask=0x0114e400\t[@lbt]\n#0x0114e400\t0xfffffc00\tf0:5,f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fcvt.ud.d drD,drJ is op10_31=0x4539 & drD & drJ {\n\tdrD = fcvt.ud.d(drD, drJ);\n}\n\ndefine pcodeop fcvt.d.ld;\n\n#lbt.txt fcvt.d.ld mask=0x01150000\t[@lbt]\n#0x01150000\t0xffff8000\tf0:5,f5:5,f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fcvt.d.ld drD,drJ,drK is op16_31=0x115 & drD & drJ & drK {\n\tdrD = fcvt.d.ld(drD, drJ, drK);\n}\n\ndefine pcodeop ldl.w;\n\n#lbt.txt ldl.w mask=0x2e000000\t[@lbt]\n#0x2e000000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ldl.w RD, RJ, simm10_12 is op22_31=0xb8 & RD & RJ & simm10_12 {\n\tRD = ldl.w(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop ldr.w;\n\n#lbt.txt ldr.w mask=0x2e400000\t[@lbt]\n#0x2e400000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ldr.w RD, RJ, simm10_12 is op22_31=0xb9 & RD & RJ & simm10_12 {\n\tRD = ldr.w(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop ldl.d;\n\n#lbt.txt ldl.d mask=0x2e800000\t[@lbt]\n#0x2e800000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ldl.d RD, RJ, simm10_12 is op22_31=0xba & RD & RJ & simm10_12 {\n\tRD = ldl.d(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop ldr.d;\n\n#lbt.txt ldr.d mask=0x2ec00000\t[@lbt]\n#0x2ec00000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ldr.d RD, RJ, simm10_12 is op22_31=0xbb & RD & RJ & simm10_12 {\n\tRD = ldr.d(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop stl.w;\n\n#lbt.txt stl.w mask=0x2f000000\t[@lbt]\n#0x2f000000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:stl.w RD, RJ, simm10_12 is op22_31=0xbc & RD & RJ & simm10_12 {\n\tRD = stl.w(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop str.w;\n\n#lbt.txt str.w mask=0x2f400000\t[@lbt]\n#0x2f400000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:str.w RD, RJ, simm10_12 is op22_31=0xbd & RD & RJ & simm10_12 {\n\tRD = str.w(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop stl.d;\n\n#lbt.txt stl.d mask=0x2f800000\t[@lbt]\n#0x2f800000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:stl.d RD, RJ, simm10_12 is op22_31=0xbe & RD & RJ & simm10_12 {\n\tRD = stl.d(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop str.d;\n\n#lbt.txt str.d mask=0x2fc00000\t[@lbt]\n#0x2fc00000\t0xffc00000\tr0:5, r5:5, so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:str.d RD, RJ, simm10_12 is op22_31=0xbf & RD & RJ & simm10_12 {\n\tRD = str.d(RD, RJ, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop jiscr0;\n\n#lbt.txt jiscr0 mask=0x48000200\t[@lbt, @orig_fmt=Sd5k16ps2]\n#0x48000200\t0xfc0003e0\ts0:5|10:16<<2\t['simm0_0_s2']\n:jiscr0 Rel26 is op26_31=0x12 & op5_9=0x10 & Rel26 {\n\tjiscr0(Rel26);\n}\n\ndefine pcodeop jiscr1;\n\n#lbt.txt jiscr1 mask=0x48000300\t[@lbt, @orig_fmt=Sd5k16ps2]\n#0x48000300\t0xfc0003e0\ts0:5|10:16<<2\t['simm0_0_s2']\n:jiscr1 Rel26 is op26_31=0x12 & op5_9=0x18 & Rel26 {\n\tjiscr1(Rel26);\n}\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch.ldefs", "content": "\n\n\n \n Loongson 3 32-bit with 32-bit FP\n \n \n \n \n \n Loongson 3 32-bit with 64-bit FP\n \n \n \n \n \n Loongson 3 64-bit with 32-bit FP\n \n \n \n \n \n \n \n Loongson 3 64-bit with 64-bit FP\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch.opinion", "content": "\n\n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n \n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch32.pspec", "content": "\n\n\n\n \n\n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch32_f32.slaspec", "content": "@define REGSIZE 4\n@define FREGSIZE 4\n@define ADDRSIZE 4\n@include \"loongarch_main.sinc\"\n@include \"loongarch32_instructions.sinc\"\n@include \"loongarch_float.sinc\"\n@include \"loongarch_double.sinc\"\n\n\n@include \"lasx.sinc\"\n@include \"lbt.sinc\"\n@include \"lsx.sinc\"\n@include \"lvz.sinc\"\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch32_f64.slaspec", "content": "@define REGSIZE 4\n@define FREGSIZE 8\n@define ADDRSIZE 4\n@include \"loongarch_main.sinc\"\n@include \"loongarch32_instructions.sinc\"\n@include \"loongarch_float.sinc\"\n@include \"loongarch_double.sinc\"\n\n#@include \"lasx.sinc\"\n#@include \"lbt.sinc\"\n#@include \"lsx.sinc\"\n#@include \"lvz.sinc\"\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch32_instructions.sinc", "content": "\n####################\n# Base Instructions\n####################\n\n\n#la-base-32.txt add.w mask=0x00100000\t[@la32, @primary, @qemu]\n#0x00100000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:add.w RD, RJ32src, RK32src is op15_31=0x20 & RD & RJ32src & RK32src {\n\tlocal add1:4 = RJ32src;\n\tlocal add2:4 = RK32src;\n\tlocal result = add1 + add2;\n\tRD = sext(result);\n}\n\n#la-base-32.txt addi.w mask=0x02800000\t[@la32, @primary, @qemu]\n#0x02800000\t0xffc00000\tr0:5,r5:5,s10:12\t['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0']\n:addi.w RD, RJ32src, simm10_12 is op22_31=0xa & RD & RJ32src & simm10_12 {\n\tlocal add1:4 = RJ32src;\n\tlocal add2:4 = simm10_12;\n\tlocal result = add1 + add2;\n\tRD = sext(result);\n}\n\n\n#la-bitops-32.txt sladd.w mask=0x00040000\t[@orig_name=alsl.w, @orig_fmt=DJKUa2pp1, @la32]\n#0x00040000\t0xfffe0000\tr0:5,r5:5,r10:5,u15:2+1\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0']\n:alsl.w RD, RJ32src, RK32src, alsl_shift is op17_31=0x2 & RD & RJ32src & RK32src & alsl_shift {\n\tlocal result:4 = (RJ32src << alsl_shift) + RK32src;\n\tRD = sext(result);\n}\n\n\n#la-base-32.txt and mask=0x00148000\t[@la32, @primary, @qemu]\n#0x00148000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:and RD, RJsrc, RKsrc is op15_31=0x29 & RD & RJsrc & RKsrc {\n\tRD = RJsrc & RKsrc;\n}\n\n#la-base-32.txt andi mask=0x03400000\t[@la32, @primary, @qemu]\n#0x03400000\t0xffc00000\tr0:5,r5:5,u10:12\t['reg0_5_s0', 'reg5_5_s0', 'imm10_12_s0']\n:andi RD, RJsrc, imm10_12 is op22_31=0xd & RD & RJsrc & imm10_12 {\n\tRD = RJsrc & imm10_12;\n}\n\n# alias of andi r0, r0, 0\n:nop is op22_31=0xd & rD=0 & rJ=0 & imm10_12=0 {\n}\n\n#la-base-32.txt andn mask=0x00168000\t[@la32, @primary, @qemu]\n#0x00168000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:andn RD, RJsrc, RKsrc is op15_31=0x2d & RD & RJsrc & RKsrc {\n\tRD = RJsrc & ~(RKsrc);\n}\n\n\n#la-base-32.txt break mask=0x002a0000\t[@la32, @primary]\n#0x002a0000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:break imm0_15 is op15_31=0x54 & imm0_15 {\n\tlocal code:2 = imm0_15;\n\tlocal addr:$(REGSIZE) = break(code);\n\tgoto [addr];\n}\n\n\n#la-base-32.txt cpucfg mask=0x00006c00\t[@la32]\n#0x00006c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:cpucfg RD, RJ32src is op10_31=0x1b & RD & RJ32src {\n\tRD = cpucfg(RJ32src);\n}\n\n\n#la-base-32.txt dbgcall mask=0x002a8000\t[@orig_name=dbcl]\n#0x002a8000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:dbcl imm0_15 is op15_31=0x55 & imm0_15 {\n\tlocal code:2 = imm0_15;\n\tdbcl(code);\n}\n\n\n#la-mul-32.txt div.w mask=0x00200000\t[@la32, @primary, @qemu]\n#0x00200000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:div.w RD, RJ32src, RK32src is op15_31=0x40 & RD & RJ32src & RK32src {\n\ttmp:4 = RJ32src s/ RK32src;\n\tRD = sext(tmp);\n}\n\n#la-mul-32.txt div.wu mask=0x00210000\t[@la32, @primary, @qemu]\n#0x00210000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:div.wu RD, RJ32src, RK32src is op15_31=0x42 & RD & RJ32src & RK32src {\n\ttmp:4 = RJ32src / RK32src;\n\tRD = sext(tmp);\n}\n\n\n#la-base-32.txt sext.b mask=0x00005c00\t[@orig_name=ext.w.b, @la32, @qemu]\n#0x00005c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:ext.w.b RD, RJsrc is op10_31=0x17 & RD & RJsrc {\n\tlocal tmp:1 = RJsrc(0);\n\tRD = sext(tmp);\n}\n\n#la-base-32.txt sext.h mask=0x00005800\t[@orig_name=ext.w.h, @la32, @qemu]\n#0x00005800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:ext.w.h RD, RJsrc is op10_31=0x16 & RD & RJsrc {\n\tlocal tmp:2 = RJsrc(0);\n\tRD = sext(tmp);\n}\n\n\n#la-base-32.txt lu12i.w mask=0x14000000\t[@la32, @primary, @qemu]\n#0x14000000\t0xfe000000\tr0:5,s5:20\t['reg0_5_s0', 'simm5_20_s0']\n:lu12i.w RD, simm12i is op25_31=0xa & RD & simm12i {\n\tRD = sext(simm12i);\n}\n\n\n#la-base-32.txt maskeqz mask=0x00130000\t[@la32, @qemu]\n#0x00130000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:maskeqz RD, RJsrc, RKsrc is op15_31=0x26 & RD & RJsrc & RKsrc {\n\tlocal test = (RKsrc == 0);\n\tRD = (zext(test) * 0) + (zext(!test) * RJsrc);\n}\n\n\n#la-base-32.txt masknez mask=0x00138000\t[@la32, @qemu]\n#0x00138000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:masknez RD, RJsrc, RKsrc is op15_31=0x27 & RD & RJsrc & RKsrc {\n\tlocal test = (RKsrc != 0);\n\tRD = (zext(test) * 0) + (zext(!test) * RJsrc);\n}\n\n\n#la-mul-32.txt mod.w mask=0x00208000\t[@la32, @primary, @qemu]\n#0x00208000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mod.w RD, RJ32src, RK32src is op15_31=0x41 & RD & RJ32src & RK32src {\n\ttmp:4 = RJ32src s% RK32src;\n\tRD = sext(tmp);\n}\n\n\n\n#la-mul-32.txt mod.wu mask=0x00218000\t[@la32, @primary, @qemu]\n#0x00218000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mod.wu RD, RJ32src, RK32src is op15_31=0x43 & RD & RJ32src & RK32src {\n\ttmp:4 = RJ32src % RK32src;\n\tRD = sext(tmp);\n}\n\n\n#la-mul-32.txt mul.w mask=0x001c0000\t[@la32, @primary, @qemu]\n#0x001c0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mul.w RD, RJ32src, RK32src is op15_31=0x38 & RD & RJ32src & RK32src {\n\ttmp1:8 = sext( RJ32src );\n\ttmp2:8 = sext( RK32src );\n\tprod:8 = tmp1 * tmp2;\n\tRD = sext( prod:4 );\n}\n\n#la-mul-32.txt mulh.w mask=0x001c8000\t[@la32, @primary, @qemu]\n#0x001c8000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mulh.w RD, RJ32src, RK32src is op15_31=0x39 & RD & RJ32src & RK32src {\n\ttmp1:8 = sext( RJ32src );\n\ttmp2:8 = sext( RK32src );\n\tprod:8 = tmp1 * tmp2;\n\tprod = prod >> 32;\n\tRD = sext( prod:4 );\n}\n\n#la-mul-32.txt mulh.wu mask=0x001d0000\t[@la32, @primary, @qemu]\n#0x001d0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mulh.wu RD, RJ32src, RK32src is op15_31=0x3a & RD & RJ32src & RK32src {\n\ttmp1:8 = zext( RJ32src );\n\ttmp2:8 = zext( RK32src );\n\tprod:8 = tmp1 * tmp2;\n\tprod = prod >> 32;\n\tRD = sext( prod:4 );\n}\n\n\n#la-base-32.txt nor mask=0x00140000\t[@la32, @primary, @qemu]\n#0x00140000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:nor RD, RJsrc, RKsrc is op15_31=0x28 & RD & RJsrc & RKsrc {\n\tRD = ~(RJsrc | RKsrc);\n}\n\n\n#la-base-32.txt or mask=0x00150000\t[@la32, @primary, @qemu]\n#0x00150000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:or RD, RJsrc, RKsrc is op15_31=0x2a & RD & RJsrc & RKsrc {\n\tRD = RJsrc | RKsrc;\n}\n\n# alias of or rd, rj, zero\n:move RD, RJsrc is op15_31=0x2a & RD & RJsrc & rK=0 {\n\tRD = RJsrc;\n}\n\n#la-base-32.txt ori mask=0x03800000\t[@la32, @primary, @qemu]\n#0x03800000\t0xffc00000\tr0:5,r5:5,u10:12\t['reg0_5_s0', 'reg5_5_s0', 'imm10_12_s0']\n:ori RD, RJsrc, imm10_12 is op22_31=0xe & RD & RJsrc & imm10_12 {\n\tRD = RJsrc | imm10_12;\n}\n\n\n#la-base-32.txt orn mask=0x00160000\t[@la32, @primary, @qemu]\n#0x00160000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:orn RD, RJsrc, RKsrc is op15_31=0x2c & RD & RJsrc & RKsrc {\n\tRD = RJsrc | ~(RKsrc);\n}\n\n\n#la-base-32.txt pcaddu2i mask=0x18000000\t[@orig_name=pcaddi, @la32, @primary, @qemu]\n#0x18000000\t0xfe000000\tr0:5,s5:20\t['reg0_5_s0', 'simm5_20_s0']\n:pcaddi RD,pcadd2 is op25_31=0xc & RD & pcadd2 {\n\tRD = pcadd2;\n}\n\n#la-base-32.txt pcalau12i mask=0x1a000000\t[@la32, @qemu]\n#0x1a000000\t0xfe000000\tr0:5,s5:20\t['reg0_5_s0', 'simm5_20_s0']\n:pcalau12i RD, pcala12 is op25_31=0xd & RD & pcala12 {\n\tRD = pcala12;\n}\n\n\n#la-base-32.txt pcaddu12i mask=0x1c000000\t[@la32, @primary, @qemu]\n#0x1c000000\t0xfe000000\tr0:5,s5:20\t['reg0_5_s0', 'simm5_20_s0']\n:pcaddu12i RD, pcadd12 is op25_31=0xe & RD & pcadd12 {\n\tRD = pcadd12;\n}\n\n\n#la-base-32.txt pcaddu18i mask=0x1e000000\t[@qemu]\n#0x1e000000\t0xfe000000\tr0:5,s5:20\t['reg0_5_s0', 'simm5_20_s0']\n:pcaddu18i RD, pcadd18 is op25_31=0xf & RD & pcadd18 {\n\tRD = pcadd18;\n}\n\n\n#la-base-32.txt rdtimel.w mask=0x00006000\t[@la32, @primary]\n#0x00006000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:rdtimel.w RD32, RJ32 is op10_31=0x18 & RD32 & RJ32 {\n\tlocal tmp:1 = 0;\n\tRD32 = rdtime.counter(tmp);\n\tRJ32 = rdtime.counterid(tmp);\n}\n\n\n#la-base-32.txt rdtimeh.w mask=0x00006400\t[@la32, @primary]\n#0x00006400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:rdtimeh.w RD32, RJ32 is op10_31=0x19 & RD32 & RJ32 {\n\tlocal tmp:1 = 1;\n\tRD32 = rdtime.counter(tmp);\n\tRJ32 = rdtime.counterid(tmp);\n}\n\n\n#la-base-32.txt rotr.w mask=0x001b0000\t[@la32, @qemu]\n#0x001b0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rotr.w RD, RJ32src, RK32src is op15_31=0x36 & RD & RJ32src & RK32src {\n\tlocal shift:1 = RK32src(0) & 0x1f;\n\tlocal tmp1:4 = RJ32src s>> shift;\n\tlocal tmp2:4 = RJ32src << (32 - shift);\n\tlocal result = tmp1 + tmp2;\n\n\tRD = sext(result);\n\n}\n\n#la-base-32.txt rotri.w mask=0x004c8000\t[@la32, @qemu]\n#0x004c8000\t0xffff8000\tr0:5,r5:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0']\n:rotri.w RD, RJ32src, imm10_5 is op15_31=0x99 & RD & RJ32src & imm10_5 {\n\tlocal shift:1 = imm10_5;\n\tlocal tmp1:4 = RJ32src s>> shift;\n\tlocal tmp2:4 = RJ32src << (32 - shift);\n\tlocal result = tmp1 + tmp2;\n\n\tRD = sext(result);\n\n}\n\n\n#la-base-32.txt sll.w mask=0x00170000\t[@la32, @primary, @qemu]\n#0x00170000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sll.w RD, RJ32src, RK32src is op15_31=0x2e & RD & RJ32src & RK32src {\n\tlocal shift:1 = RK32src(0) & 0x1f;\n\tlocal result:4 = RJ32src << shift;\n\tRD = sext(result);\n}\n\n#la-base-32.txt slli.w mask=0x00408000\t[@la32, @primary, @qemu]\n#0x00408000\t0xffff8000\tr0:5,r5:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0']\n:slli.w RD, RJ32src, imm10_5 is op15_31=0x81 & RD & RJ32src& imm10_5 {\n\tlocal shift:1 = imm10_5 & 0x1f;\n\tlocal result:4 = RJ32src << shift;\n\tRD = sext(result);\n}\n\n\n#la-base-32.txt slt mask=0x00120000\t[@la32, @primary, @qemu]\n#0x00120000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:slt RD, RJsrc, RKsrc is op15_31=0x24 & RD & RJsrc & RKsrc {\n\tRD = zext( RJsrc s< RKsrc );\n}\n\n#la-base-32.txt sltu mask=0x00128000\t[@la32, @primary, @qemu]\n#0x00128000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sltu RD, RJsrc, RKsrc is op15_31=0x25 & RD & RJsrc & RKsrc {\n\tRD = zext( RJsrc < RKsrc );\n}\n\n#la-base-32.txt slti mask=0x02000000\t[@la32, @primary, @qemu]\n#0x02000000\t0xffc00000\tr0:5,r5:5,s10:12\t['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0']\n:slti RD, RJsrc, simm10_12 is op22_31=0x8 & RD & RJsrc & simm10_12 {\n\tRD = zext( RJsrc s< simm10_12 );\n}\n\n#la-base-32.txt sltui mask=0x02400000\t[@la32, @primary, @qemu]\n#0x02400000\t0xffc00000\tr0:5,r5:5,s10:12\t['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0']\n:sltui RD, RJsrc, simm10_12 is op22_31=0x9 & RD & RJsrc & simm10_12 {\n\tRD = zext( RJsrc < simm10_12 );\n}\n\n\n#la-base-32.txt srl.w mask=0x00178000\t[@la32, @primary, @qemu]\n#0x00178000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:srl.w RD, RJ32src, RK32src is op15_31=0x2f & RD & RJ32src & RK32src {\n\tlocal shift:1 = RK32src(0) & 0x1f;\n\tlocal result:4 = RJ32src >> shift;\n\tRD = sext(result);\n}\n\n#la-base-32.txt srli.w mask=0x00448000\t[@la32, @primary, @qemu]\n#0x00448000\t0xffff8000\tr0:5,r5:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0']\n:srli.w RD, RJ32src, imm10_5 is op15_31=0x89 & RD & RJ32src & imm10_5 {\n\tlocal shift:1 = imm10_5 & 0x1f;\n\tlocal result:4 = RJ32src >> shift;\n\tRD = sext(result);\n}\n\n\n#la-base-32.txt sra.w mask=0x00180000\t[@la32, @primary, @qemu]\n#0x00180000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sra.w RD, RJ32src, RK32src is op15_31=0x30 & RD & RJ32src & RK32src {\n\tlocal shift:1 = RK32src(0) & 0x1f;\n\tlocal result:4 = RJ32src s>> shift;\n\tRD = sext(result);\n}\n\n#la-base-32.txt srai.w mask=0x00488000\t[@la32, @primary, @qemu]\n#0x00488000\t0xffff8000\tr0:5,r5:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0']\n:srai.w RD, RJ32src, imm10_5 is op15_31=0x91 & RD & RJ32src & imm10_5 {\n\tlocal shift:1 = imm10_5 & 0x1f;\n\tlocal result:4 = RJ32src s>> shift;\n\tRD = sext(result);\n}\n\n\n#la-base-32.txt sub.w mask=0x00110000\t[@la32, @primary, @qemu]\n#0x00110000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sub.w RD, RJ32src, RK32src is op15_31=0x22 & RD & RJ32src & RK32src {\n\tlocal sub1:4 = RJ32src;\n\tlocal sub2:4 = RK32src;\n\tlocal result = sub1 - sub2;\n\tRD = sext(result);\n}\n\n\n#la-base-32.txt syscall mask=0x002b0000\t[@la32, @primary]\n#0x002b0000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:syscall imm0_15 is op15_31=0x56 & imm0_15 {\n\tlocal code:2 = imm0_15;\n\tsyscall(code);\n}\n\n\n#la-base-32.txt xor mask=0x00158000\t[@la32, @primary, @qemu]\n#0x00158000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:xor RD, RJsrc, RKsrc is op15_31=0x2b & RD & RJsrc & RKsrc {\n\tRD = RJsrc ^ RKsrc;\n}\n\n#la-base-32.txt xori mask=0x03c00000\t[@la32, @primary, @qemu]\n#0x03c00000\t0xffc00000\tr0:5,r5:5,u10:12\t['reg0_5_s0', 'reg5_5_s0', 'imm10_12_s0']\n:xori RD, RJsrc, imm10_12 is op22_31=0xf & RD & RJsrc & imm10_12 {\n\tRD = RJsrc ^ imm10_12;\n}\n\n\n##########################\n# Load/Store Instructions\n##########################\n\n#la-base-32.txt ldox4.w mask=0x24000000\t[@orig_name=ldptr.w, @orig_fmt=DJSk14ps2]\n#0x24000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:ldptr.w RD, ldstptr_addr is op24_31=0x24 & RD & RJsrc & ldstptr_addr {\n\tlocal data:4 = *[ram]:4 ldstptr_addr;\n\tRD = sext(data);\n}\n\n\n#la-base-32.txt stox4.w mask=0x25000000\t[@orig_name=stptr.w, @orig_fmt=DJSk14ps2]\n#0x25000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:stptr.w RD, ldstptr_addr is op24_31=0x25 & RD32 & RD & ldstptr_addr {\n\t*[ram]:4 ldstptr_addr = RD32;\n}\n\n\n#la-base-32.txt ld.b mask=0x28000000\t[@la32, @primary, @qemu]\n#0x28000000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.b RD, ldst_addr is op22_31=0xa0 & RD & RJsrc & ldst_addr {\n\tRD = sext(*[ram]:1 ldst_addr);\n}\n\n\n#la-base-32.txt ld.h mask=0x28400000\t[@la32, @primary, @qemu]\n#0x28400000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.h RD, ldst_addr is op22_31=0xa1 & RD & RJsrc & ldst_addr {\n\tRD = sext(*[ram]:2 ldst_addr);\n}\n\n\n#la-base-32.txt ld.w mask=0x28800000\t[@la32, @primary, @qemu]\n#0x28800000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.w RD, ldst_addr is op22_31=0xa2 & RD & RJsrc & ldst_addr {\n\tlocal data:4 = *[ram]:4 ldst_addr;\n\tRD = sext(data);\n}\n\n\n#la-base-32.txt st.b mask=0x29000000\t[@la32, @primary, @qemu]\n#0x29000000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:st.b RDsrc, ldst_addr is op22_31=0xa4 & RDsrc & ldst_addr {\n\t*[ram]:1 ldst_addr = RDsrc:1;\n}\n\n#la-base-32.txt st.h mask=0x29400000\t[@la32, @primary, @qemu]\n#0x29400000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:st.h RDsrc, ldst_addr is op22_31=0xa5 & RDsrc & ldst_addr {\n\t*[ram]:2 ldst_addr = RDsrc:2;\n}\n\n#la-base-32.txt st.w mask=0x29800000\t[@la32, @primary, @qemu]\n#0x29800000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:st.w RDsrc, ldst_addr is op22_31=0xa6 & RDsrc & ldst_addr {\n\t*[ram]:4 ldst_addr = RDsrc:4;\n}\n\n\n#la-base-32.txt ld.bu mask=0x2a000000\t[@la32, @primary, @qemu]\n#0x2a000000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.bu RD, ldst_addr is op22_31=0xa8 & RD & RJsrc & ldst_addr {\n\tRD = zext(*[ram]:1 ldst_addr);\n}\n\n\n#la-base-32.txt ld.hu mask=0x2a400000\t[@la32, @primary, @qemu]\n#0x2a400000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.hu RD, ldst_addr is op22_31=0xa9 & RD & RJsrc & ldst_addr {\n\tRD = zext(*[ram]:2 ldst_addr);\n}\n\n#la-base-32.txt preld mask=0x2ac00000\t[@orig_fmt=Ud5JSk12, @la32, @primary]\n#0x2ac00000\t0xffc00000\tu0:5,r5:5,so10:12\t['imm0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:preld imm0_5, ldst_addr is op22_31=0xab & imm0_5 & op0_4=0 & ldst_addr {\n\tpreld_loadl1cache(0:1, ldst_addr);\n}\n\n:preld imm0_5, ldst_addr is op22_31=0xab & imm0_5 & op0_4=8 & ldst_addr {\n\tlocal hint:1 = imm0_5;\n\tpreld_storel1cache(8:1, ldst_addr);\n}\n\n:preld imm0_5, ldst_addr is op22_31=0xab & imm0_5 & ldst_addr {\n\tpreld_nop();\n}\n\n\n#la-base-32.txt preldx mask=0x382c0000\t[@orig_fmt=Ud5JK]\n#0x382c0000\t0xffff8000\tu0:5,r5:5,r10:5\t['imm0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:preldx imm0_5, RJsrc, RKsrc is op15_31=0x7058 & RJsrc & RKsrc & imm0_5 & op0_4=0 {\n\tpreldx_loadl1cache(0:1, RJsrc, RKsrc);\n}\n\n:preldx imm0_5, RJsrc, RKsrc is op15_31=0x7058 & RJsrc & RKsrc & imm0_5 & op0_4=8 {\n\tpreldx_storel1cache(8:1, RJsrc, RKsrc);\n}\n\n:preldx imm0_5, RJsrc, RKsrc is op15_31=0x7058 & RJsrc & RKsrc & imm0_5 {\n\tpreldx_nop(imm0_5:1, RJsrc, RJsrc);\n}\n#la-base-32.txt ldx.b mask=0x38000000\t[@qemu]\n#0x38000000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.b RD, ldstx_addr is op15_31=0x7000 & RD & ldstx_addr {\n\tRD = sext(*[ram]:1 ldstx_addr);\n}\n\n\n#la-base-32.txt ldx.h mask=0x38040000\t[@qemu]\n#0x38040000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.h RD, ldstx_addr is op15_31=0x7008 & RD & ldstx_addr {\n\tRD = sext(*[ram]:2 ldstx_addr);\n}\n\n\n#la-base-32.txt ldx.w mask=0x38080000\t[@qemu]\n#0x38080000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.w RD, ldstx_addr is op15_31=0x7010 & RD & ldstx_addr {\n\tlocal data:4 = *[ram]:4 ldstx_addr;\n\tRD = sext(data);\n}\n\n\n#la-base-32.txt stx.b mask=0x38100000\t[@qemu]\n#0x38100000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stx.b RDsrc, ldstx_addr is op15_31=0x7020 & RDsrc & ldstx_addr {\n\t*[ram]:1 ldstx_addr = RDsrc:1;\n}\n\n\n#la-base-32.txt stx.h mask=0x38140000\t[@qemu]\n#0x38140000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stx.h RDsrc, ldstx_addr is op15_31=0x7028 & RDsrc & ldstx_addr {\n\t*[ram]:2 ldstx_addr = RDsrc:2;\n}\n\n\n#la-base-32.txt stx.w mask=0x38180000\t[@qemu]\n#0x38180000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stx.w RDsrc, ldstx_addr is op15_31=0x7030 & RDsrc & RD32src & ldstx_addr {\n\t*[ram]:4 ldstx_addr = RD32src;\n}\n\n\n#la-base-32.txt ldx.bu mask=0x38200000\t[@qemu]\n#0x38200000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.bu RD, ldstx_addr is op15_31=0x7040 & RD & ldstx_addr {\n\tRD = zext(*[ram]:1 ldstx_addr);\n}\n\n\n#la-base-32.txt ldx.hu mask=0x38240000\t[@qemu]\n#0x38240000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.hu RD, ldstx_addr is op15_31=0x7048 & RD & ldstx_addr {\n\tRD = zext(*[ram]:2 ldstx_addr);\n}\n\n\n#la-base-32.txt dbar mask=0x38720000\t[@la32, @primary, @qemu]\n#0x38720000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:dbar imm0_15 is op15_31=0x70e4 & imm0_15 {\n\tlocal code:2 = imm0_15;\n\tdbar(code);\n}\n\n\n#la-base-32.txt ibar mask=0x38728000\t[@la32, @primary]\n#0x38728000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:ibar imm0_15 is op15_31=0x70e5 & imm0_15 {\n\tlocal code:2 = imm0_15;\n\tibar(code);\n}\n\n\n######################\n# Branch Instructions\n######################\n\n\n#la-base-32.txt b mask=0x50000000\t[@orig_fmt=Sd10k16ps2, @la32, @primary, @qemu]\n#0x50000000\t0xfc000000\tsb0:10|10:16<<2\t['sbranch0_0_s2']\n:b Rel26 is op26_31=0x14 & Rel26 {\n\tgoto Rel26;\n}\n\n#la-base-32.txt bl mask=0x54000000\t[@orig_fmt=Sd10k16ps2, @la32, @primary, @qemu]\n#0x54000000\t0xfc000000\tsb0:10|10:16<<2\t['sbranch0_0_s2']\n:bl Rel26 is op26_31=0x15 & Rel26 {\n\tra = inst_next;\n\tcall Rel26;\n}\n\n:bl Rel26 is op26_31=0x15 & Rel26 & imm10_16=1 & simm0_10=0 {\n\tra = inst_next;\n\tgoto Rel26;\n}\n\n#la-base-32.txt beq mask=0x58000000\t[@orig_fmt=JDSk16ps2, @la32, @primary, @qemu]\n#0x58000000\t0xfc000000\tr5:5,r0:5,sb10:16<<2\t['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0']\n:beq RDsrc, RJsrc, Rel16 is op26_31=0x16 & RDsrc & RJsrc & Rel16 {\n\tif(RJsrc == RDsrc) goto Rel16;\n}\n\n#la-base-32.txt beqz mask=0x40000000\t[@orig_fmt=JSd5k16ps2, @la32]\n#0x40000000\t0xfc000000\tr5:5,sb0:5|10:16<<2\t['reg5_5_s0', 'sbranch0_0_s2']\n:beqz RJsrc, Rel21 is op26_31=0x10 & RJsrc & Rel21 {\n\tif (RJsrc == 0) goto Rel21;\n}\n\n\n#la-base-32.txt ble mask=0x64000000\t[@orig_name=bge, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu]\n#0x64000000\t0xfc000000\tr5:5,r0:5,sb10:16<<2\t['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0']\n:bge RDsrc, RJsrc, Rel16 is op26_31=0x19 & RDsrc & RJsrc & Rel16 {\n\tif(RJsrc s>= RDsrc) goto Rel16;\n}\n\n:bgez RJsrc, Rel16 is op26_31=0x19 & rD=0 & RJsrc & Rel16 {\n\tif(RJsrc s>= 0) goto Rel16;\n}\n\n:blez RDsrc, Rel16 is op26_31=0x19 & RDsrc & rJ=0 & Rel16 {\n\tif(0 s>= RDsrc) goto Rel16;\n}\n\n#la-base-32.txt bleu mask=0x6c000000\t[@orig_name=bgeu, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu]\n#0x6c000000\t0xfc000000\tr5:5,r0:5,sb10:16<<2\t['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0']\n:bgeu RDsrc, RJsrc, Rel16 is op26_31=0x1b & RDsrc & RJsrc & Rel16 {\n\tif(RJsrc >= RDsrc) goto Rel16;\n}\n\n\n#la-base-32.txt bgt mask=0x60000000\t[@orig_name=blt, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu]\n#0x60000000\t0xfc000000\tr5:5,r0:5,sb10:16<<2\t['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0']\n:blt RDsrc, RJsrc, Rel16 is op26_31=0x18 & RDsrc & RJsrc & Rel16 {\n\tif(RJsrc s< RDsrc) goto Rel16;\n}\n\n:bltz RJsrc, Rel16 is op26_31=0x18 & rD=0 & RJsrc & Rel16 {\n\tif(RJsrc s< 0) goto Rel16;\n}\n\n:bgtz RDsrc, Rel16 is op26_31=0x18 & RDsrc & rJ=0 & Rel16 {\n\tif(0 s< RDsrc) goto Rel16;\n}\n#la-base-32.txt bgtu mask=0x68000000\t[@orig_name=bltu, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu]\n#0x68000000\t0xfc000000\tr5:5,r0:5,sb10:16<<2\t['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0']\n:bltu RDsrc, RJsrc, Rel16 is op26_31=0x1a & RDsrc & RJsrc & Rel16 {\n\tif(RJsrc < RDsrc) goto Rel16;\n}\n\n\n#la-base-32.txt bne mask=0x5c000000\t[@orig_fmt=JDSk16ps2, @la32, @primary, @qemu]\n#0x5c000000\t0xfc000000\tr5:5,r0:5,sb10:16<<2\t['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0']\n:bne RDsrc, RJsrc, Rel16 is op26_31=0x17 & RDsrc & RJsrc & Rel16 {\n\tif(RJsrc != RDsrc) goto Rel16;\n}\n\n#la-base-32.txt bnez mask=0x44000000\t[@orig_fmt=JSd5k16ps2, @la32]\n#0x44000000\t0xfc000000\tr5:5,sb0:5|10:16<<2\t['reg5_5_s0', 'sbranch0_0_s2']\n:bnez RJsrc, Rel21 is op26_31=0x11 & RJsrc & Rel21 {\n\tif (RJsrc != 0) goto Rel21;\n}\n\n\n#la-base-32.txt jirl mask=0x4c000000\t[@orig_fmt=DJSk16ps2, @la32, @primary, @qemu]\n#0x4c000000\t0xfc000000\tr0:5,r5:5,so10:16<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_16_s0']\n:jirl RD, RelJ16 is op26_31=0x13 & RD & RJsrc & RelJ16 {\n\tRD = inst_next;\n\tcall [RelJ16];\n}\n\n# alias of jirl zero, ra, 0\n:ret is op26_31=0x13 & rD=0x0 & rJ=0x1 & RJsrc & simm10_16=0 {\n\tlocal retAddr = RJsrc;\n\treturn [retAddr];\n}\n\n# alias of jirl zero, rj, 0\n:jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & simm10_16=0 {\n\tpc = RJsrc;\n\tgoto [pc];\n}\n\n\n######################\n# Atomic Instructions\n######################\n\n\n#la-atomics-32.txt ll.w mask=0x20000000\t[@orig_fmt=DJSk14ps2, @la32, @primary]\n#0x20000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:ll.w RD, ldstptr_addr is op24_31=0x20 & RD & ldstptr_addr {\n\tlocal data:4 = *[ram]:4 ldstptr_addr;\n\tRD = sext(data);\n}\n\n\n#la-atomics-32.txt sc.w mask=0x21000000\t[@orig_fmt=DJSk14ps2, @la32, @primary]\n#0x21000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:sc.w RD, ldstptr_addr is op24_31=0x21 & RD & ldstptr_addr {\n\t*[ram]:4 ldstptr_addr = RD:4;\n}\n\n\n#la-atomics-32.txt amswap.w mask=0x38600000\t[@orig_fmt=DKJ]\n#0x38600000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amswap.w RD, RJsrc, RK32src is op15_31=0x70c0 & RD & RJsrc & RK32src {\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = RK32src;\n}\n\n\n#la-atomics-32.txt amadd.w mask=0x38610000\t[@orig_fmt=DKJ]\n#0x38610000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amadd.w RD, RJsrc, RK32src is op15_31=0x70c2 & RD & RJsrc & RK32src {\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src + val);\n}\n\n\n#la-atomics-32.txt amand.w mask=0x38620000\t[@orig_fmt=DKJ]\n#0x38620000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amand.w RD, RJsrc, RK32src is op15_31=0x70c4 & RD & RJsrc & RK32src {\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src & val);\n}\n\n\n#la-atomics-32.txt amor.w mask=0x38630000\t[@orig_fmt=DKJ]\n#0x38630000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amor.w RD, RJsrc, RK32src is op15_31=0x70c6 & RD & RJsrc & RK32src {\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src | val);\n}\n\n\n#la-atomics-32.txt amxor.w mask=0x38640000\t[@orig_fmt=DKJ]\n#0x38640000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amxor.w RD, RJsrc, RK32src is op15_31=0x70c8 & RD & RJsrc & RK32src {\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src ^ val);\n}\n\n\n#la-atomics-32.txt ammax.w mask=0x38650000\t[@orig_fmt=DKJ]\n#0x38650000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax.w RD, RJsrc, RK32src is op15_31=0x70ca & RD & RJsrc & RK32src {\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 s>= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-32.txt ammin.w mask=0x38660000\t[@orig_fmt=DKJ]\n#0x38660000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin.w RD, RJsrc, RK32src is op15_31=0x70cc & RD & RJsrc & RK32src {\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 s<= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-32.txt amswap_db.w mask=0x38690000\t[@orig_fmt=DKJ]\n#0x38690000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amswap_db.w RD, RJsrc, RK32src is op15_31=0x70d2 & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = zext(val);\n\t*[ram]:4 RJsrc = RK32src;\n}\n\n\n#la-atomics-32.txt amadd_db.w mask=0x386a0000\t[@orig_fmt=DKJ]\n#0x386a0000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amadd_db.w RD, RJsrc, RK32src is op15_31=0x70d4 & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src + val);\n}\n\n\n#la-atomics-32.txt amand_db.w mask=0x386b0000\t[@orig_fmt=DKJ]\n#0x386b0000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amand_db.w RD, RJsrc, RK32src is op15_31=0x70d6 & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src & val);\n}\n\n\n#la-atomics-32.txt amor_db.w mask=0x386c0000\t[@orig_fmt=DKJ]\n#0x386c0000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amor_db.w RD, RJsrc, RK32src is op15_31=0x70d8 & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src | val);\n}\n\n\n#la-atomics-32.txt amxor_db.w mask=0x386d0000\t[@orig_fmt=DKJ]\n#0x386d0000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amxor_db.w RD, RJsrc, RK32src is op15_31=0x70da & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val:4 = *[ram]:4 RJsrc;\n\tRD = sext(val);\n\t*[ram]:4 RJsrc = (RK32src ^ val);\n}\n\n\n#la-atomics-32.txt ammax_db.w mask=0x386e0000\t[@orig_fmt=DKJ]\n#0x386e0000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax_db.w RD, RJsrc, RK32src is op15_31=0x70dc & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 s>= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-32.txt ammin_db.w mask=0x386f0000\t[@orig_fmt=DKJ]\n#0x386f0000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin_db.w RD, RJsrc, RK32src is op15_31=0x70de & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 s<= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n################################\n# Bit-manipulation Instructions\n################################\n\n\n#la-bitops-32.txt clo.w mask=0x00001000\t[@la32]\n#0x00001000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:clo.w RD, RJ32src is op10_31=0x4 & RD & RJ32src {\n\tRD = lzcount( ~RJ32src );\n}\n\n\n#la-bitops-32.txt clz.w mask=0x00001400\t[@la32, @qemu]\n#0x00001400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:clz.w RD, RJ32src is op10_31=0x5 & RD & RJ32src {\n\tRD = lzcount( RJ32src );\n}\n\n\n\n#define pcodeop tzcount;\n#la-bitops-32.txt cto.w mask=0x00001800\t[@la32]\n#0x00001800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:cto.w RD, RJ32src is op10_31=0x6 & RD & RJ32src {\n\tlocal tmp:4 = 0;\n\ttzcount32(~RJ32src, tmp);\n\tRD = zext(tmp);\n}\n\n#la-bitops-32.txt ctz.w mask=0x00001c00\t[@la32, @qemu]\n#0x00001c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:ctz.w RD, RJ32src is op10_31=0x7 & RD & RJ32src {\n\tlocal tmp:4 = 0;\n\ttzcount32(RJ32src, tmp);\n\tRD = zext(tmp);\n}\n\n\n#la-bitops-32.txt revb.2h mask=0x00003000\t[@la32, @qemu]\n#0x00003000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:revb.2h RD, RJ32src is op10_31=0xc & RD & RJ32src {\n\ttmp0:4 = (zext(RJ32src[0,8]) << 8) + zext(RJ32src[8,8]);\n\ttmp1:4 = (zext(RJ32src[16,8]) << 8) + zext(RJ32src[24,8]);\n\tRD = sext((tmp1 << 16) + tmp0);\n}\n\n\n#la-bitops-32.txt revbit.4b mask=0x00004800\t[@orig_name=bitrev.4b, @la32]\n#0x00004800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:bitrev.4b RD, RJ32src is op10_31=0x12 & RD & RJ32src {\n\tlocal v:4 = 0;\n\tbyterev32(RJ32src, v);\n\tRD = sext(v);\n}\n\n\n#la-bitops-32.txt revbit.w mask=0x00005000\t[@orig_name=bitrev.w, @la32]\n#0x00005000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:bitrev.w RD, RJ32src is op10_31=0x14 & RD & RJ32src {\n\tlocal v:4 = 0;\n\tbitrev32(RJ32src, v);\n\tRD = sext(v);\n}\n\n\n#la-bitops-32.txt catpick.w mask=0x00080000\t[@orig_name=bytepick.w, @la32]\n#0x00080000\t0xfffe0000\tr0:5,r5:5,r10:5,u15:2\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2_s0']\n:bytepick.w RD, RJ32src, RK32src, imm15_2 is op17_31=0x4 & RD & RJ32src & RK32src & imm15_2 {\n\tlocal bitstop:1 = 8 * (4 - imm15_2);\n\tlocal mask:4 = (1 << bitstop) - 1;\n\tlocal tmp_hi:4 = RK32src & ~mask;\n\tlocal tmp_lo:4 = (RJ32src & (mask << (32-bitstop)) >> (32-bitstop));\n\tRD = sext(tmp_hi + tmp_lo);\n}\n\ndefine pcodeop crc.w.b.w;\n\n#la-bitops-32.txt crc.w.b.w mask=0x00240000\t\n#0x00240000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crc.w.b.w RD, RJ32src, RK32src is op15_31=0x48 & RD & RJ32src & RK32src {\n\tlocal val:1 = RJ32src(0);\n\tRD = crc_ieee802.3(RK32src, val, 16:1, 0xedb88320:4);\n}\n\ndefine pcodeop crc.w.h.w;\n\n#la-bitops-32.txt crc.w.h.w mask=0x00248000\t\n#0x00248000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crc.w.h.w RD, RJ32src, RK32src is op15_31=0x49 & RD & RJ32src & RK32src {\n\tlocal val:2 = RJ32src(0);\n\tRD = crc_ieee802.3(RK32src, val, 16:1, 0xedb88320:4);\n}\n\ndefine pcodeop crc.w.w.w;\n\n#la-bitops-32.txt crc.w.w.w mask=0x00250000\t\n#0x00250000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crc.w.w.w RD, RJ32src, RK32src is op15_31=0x4a & RD & RJ32src & RK32src {\n\tRD = crc_ieee802.3(RK32src, RJ32src, 32:1, 0xedb88320:4);\n}\n\ndefine pcodeop crcc.w.b.w;\n\n#la-bitops-32.txt crcc.w.b.w mask=0x00260000\t\n#0x00260000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crcc.w.b.w RD, RJ32src, RK32src is op15_31=0x4c & RD & RJ32src & RK32src {\n\tlocal val:1 = RJ32src(0);\n\tRD = crc_castagnoli(RK32src, val, 8:1, 0x82f63b78:4);\n}\n\ndefine pcodeop crcc.w.h.w;\n\n#la-bitops-32.txt crcc.w.h.w mask=0x00268000\t\n#0x00268000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crcc.w.h.w RD, RJ32src, RK32src is op15_31=0x4d & RD & RJ32src & RK32src {\n\tlocal val:2 = RJ32src(0);\n\tRD = crc_castagnoli(RK32src, val, 16:1, 0x82f63b78:4);\n}\n\ndefine pcodeop crcc.w.w.w;\n\n#la-bitops-32.txt crcc.w.w.w mask=0x00270000\t\n#0x00270000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crcc.w.w.w RD, RJ32src, RK32src is op15_31=0x4e & RD & RJ32src & RK32src {\n\tRD = crc_castagnoli(RK32src, RJ32src, 32:1, 0x82f63b78:4);\n}\n\ndefine pcodeop bstrins.w;\n\n#la-bitops-32.txt bstrins.w mask=0x00600000\t[@orig_fmt=DJUm5Uk5, @la32, @qemu]\n#0x00600000\t0xffe08000\tr0:5,r5:5,u16:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm16_5_s0', 'imm10_5_s0']\n:bstrins.w RD, RJ32src, imm16_5, imm10_5 is op21_31=0x3 & op15_15=0x0 & RD & RD32 & RJ32src & imm10_5 & imm16_5 {\n\tlocal msb:1 = imm16_5;\n\tlocal lsb:1 = imm10_5;\n\tlocal len:1 = msb + 1 - lsb;\n\tlocal mask:4 = (1 << len) - 1;\n\tlocal repl:4 = (RJ32src & (mask << lsb)) >> lsb;\n\tRD = sext((RD32 & (~mask)) | repl);\n}\n\n\n#la-bitops-32.txt bstrpick.w mask=0x00608000\t[@orig_fmt=DJUm5Uk5, @la32, @qemu]\n#0x00608000\t0xffe08000\tr0:5,r5:5,u16:5,u10:5\t['reg0_5_s0', 'reg5_5_s0', 'imm16_5_s0', 'imm10_5_s0']\n:bstrpick.w RD, RJ32src, imm16_5, imm10_5, is op21_31=0x3 & op15_15=0x1 & RD & RJ32src & imm10_5 & imm16_5 {\n\tlocal msb:1 = imm16_5;\n\tlocal lsb:1 = imm10_5;\n\tlocal len:1 = msb + 1 - lsb;\n\tlocal mask:4 = (1 << len) - 1;\n\tlocal repl:4 = (RJ32src & (mask << lsb)) >> lsb;\n\tRD = sext(repl);\n}\n\n\n###############################\n# Bounds-checking Instructions\n###############################\n\n\n#la-bound.txt asrtle mask=0x00010000\t[@orig_name=asrtle.d]\n#0x00010000\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:asrtle.d RJsrc, RKsrc is op15_31=0x2 & op0_4=0x0 & RJsrc & RKsrc {\n\tif (RJsrc <= RKsrc) goto inst_next;\n\taddr_bound_exception(RJsrc, RKsrc);\n}\n\n#la-bound.txt asrtgt mask=0x00018000\t[@orig_name=asrtgt.d]\n#0x00018000\t0xffff801f\tr5:5, r10:5\t['reg5_5_s0', 'reg10_5_s0']\n:asrtgt.d RJsrc, RKsrc is op15_31=0x3 & op0_4=0x0 & RJsrc & RKsrc {\n\tif (RJsrc > RKsrc) goto inst_next;\n\taddr_bound_exception(RJsrc, RKsrc);\n}\n\n\n#la-bound.txt ldgt.b mask=0x38780000\t\n#0x38780000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldgt.b RD, RJsrc, RKsrc is op15_31=0x70f0 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:1 vaddr);\n}\n\n#la-bound.txt ldgt.h mask=0x38788000\t\n#0x38788000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldgt.h RD, RJsrc, RKsrc is op15_31=0x70f1 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:2 vaddr);\n}\n\n#la-bound.txt ldgt.w mask=0x38790000\t\n#0x38790000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldgt.w RD, RJsrc, RKsrc is op15_31=0x70f2 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:4 vaddr);\n}\n\n\n#la-bound.txt ldle.b mask=0x387a0000\t\n#0x387a0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldle.b RD, RJsrc, RKsrc is op15_31=0x70f4 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:1 vaddr);\n}\n\n#la-bound.txt ldle.h mask=0x387a8000\t\n#0x387a8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldle.h RD, RJsrc, RKsrc is op15_31=0x70f5 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:2 vaddr);\n}\n\n#la-bound.txt ldle.w mask=0x387b0000\t\n#0x387b0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldle.w RD, RJsrc, RKsrc is op15_31=0x70f6 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:4 vaddr);\n}\n\n\n#la-bound.txt stgt.b mask=0x387c0000\t\n#0x387c0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stgt.b RDsrc, RJsrc, RKsrc is op15_31=0x70f8 & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(vaddr, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:1 RJsrc = RDsrc:1;\n}\n\n#la-bound.txt stgt.h mask=0x387c8000\t\n#0x387c8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stgt.h RDsrc, RJsrc, RKsrc is op15_31=0x70f9 & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(vaddr, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:2 vaddr = RDsrc:2;\n}\n\n#la-bound.txt stgt.w mask=0x387d0000\t\n#0x387d0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stgt.w RDsrc, RJsrc, RKsrc is op15_31=0x70fa & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:4 vaddr = RDsrc:4;\n}\n\n#la-bound.txt stle.b mask=0x387e0000\t\n#0x387e0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stle.b RDsrc, RJsrc, RKsrc is op15_31=0x70fc & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:1 vaddr = RDsrc:1;\n}\n\n#la-bound.txt stle.h mask=0x387e8000\t\n#0x387e8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stle.h RDsrc, RJsrc, RKsrc is op15_31=0x70fd & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:2 vaddr = RDsrc:2;\n}\n\n#la-bound.txt stle.w mask=0x387f0000\t\n#0x387f0000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stle.w RDsrc, RJsrc, RKsrc is op15_31=0x70fe & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:4 vaddr = RDsrc:4;\n}\n\n\n#########################\n# PRIVILEGED INSTRUCTIONS\n#########################\n\n#la-privileged-32.txt csrxchg mask=0x04000000\t[@primary]\n#0x04000000\t0xff000000\tr0:5,r5:5,u10:14\t['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0']\ncsr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] {\n\texport *[register]:$(REGSIZE) csr;\n}\n\n:csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr {\n\tlocal csrval:$(REGSIZE) = csr;\n\tlocal mask = RJsrc;\n\tcsr = (RD & mask) | (csrval & ~mask);\n\tRD = csrval;\n}\n\n:csrrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr {\n\tRD = csr;\n}\n\n:csrrw RD, csr is op24_31=0x4 & RD & op5_9=1 & csr {\n\tlocal csrval:$(REGSIZE) = csr;\n\tcsr = RD;\n\tRD = csrval;\n}\n\ndefine pcodeop cacop;\n#la-privileged-32.txt cacop mask=0x06000000\t[@orig_fmt=Ud5JSk12, @primary]\n#0x06000000\t0xffc00000\tu0:5,r5:5,s10:12\t['imm0_5_s0', 'reg5_5_s0', 'simm10_12_s0']\ncache_obj: op0_2 is op0_2 { local tmp:1 = op0_2; export *[const]:1 tmp; }\nop_type: \"initialization\" is op3_4=0 { export 0:1; } \nop_type: \"consistency\" is op3_4=1 { export 1:1; } \nop_type: \"coherency\" is op3_4=2 { export 2:1; } \nop_type: \"Custom\" is op3_4=3 { export 3:1; }\n\n:cacop op_type^\"(\"^cache_obj^\")\", ldst_addr is op22_31=0x18 & cache_obj & op_type & ldst_addr {\n\tcacop(op_type, cache_obj, ldst_addr);\n}\n\n\ndefine pcodeop lddir;\nlevel: imm10_8 is imm10_8 { export *[const]:1 imm10_8; }\n#la-privileged-32.txt lddir mask=0x06400000\t\n#0x06400000\t0xfffc0000\tr0:5,r5:5,u10:8\t['reg0_5_s0', 'reg5_5_s0', 'imm10_8_s0']\n:lddir RD, RJsrc, level is op18_31=0x190 & RD & RJsrc & level {\n\tRD = lddir(RJsrc, level);\n}\n\n\ndefine pcodeop ldpte;\nseq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; }\n#la-privileged-32.txt ldpte mask=0x06440000\t\n#0x06440000\t0xfffc001f\tr5:5,u10:8\t['reg5_5_s0', 'imm10_8_s0']\n:ldpte RJsrc, seq is op18_31=0x191 & op0_4=0x0 & RJsrc & seq {\n\tldpte(RJsrc, seq);\n}\n\n\n\n#la-privileged-32.txt iocsrrd.b mask=0x06480000\t\n#0x06480000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrrd.b RD, RJsrc is op10_31=0x19200 & RD & RJsrc {\n\tlocal val:1 = *[iocsr]:1 RJsrc;\n\tRD = sext(val);\n}\n\n\n#la-privileged-32.txt iocsrrd.h mask=0x06480400\t\n#0x06480400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrrd.h RD, RJsrc is op10_31=0x19201 & RD & RJsrc {\n\tlocal val:2 = *[iocsr]:2 RJsrc;\n\tRD = sext(val);\n}\n\n\n#la-privileged-32.txt iocsrrd.w mask=0x06480800\t\n#0x06480800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrrd.w RD, RJsrc is op10_31=0x19202 & RD & RJsrc {\n\tlocal val:4 = *[iocsr]:4 RJsrc;\n\tRD = sext(val);\n}\n\n\n\n#la-privileged-32.txt iocsrwr.b mask=0x06481000\t\n#0x06481000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrwr.b RDsrc, RJsrc is op10_31=0x19204 & RDsrc & RJsrc {\n local val:1 = RDsrc:1;\n *[iocsr]:1 RJsrc = val;\n}\n\n\n#la-privileged-32.txt iocsrwr.h mask=0x06481400\t\n#0x06481400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrwr.h RDsrc, RJsrc is op10_31=0x19205 & RDsrc & RJsrc {\n local val:2= RDsrc:2;\n *[iocsr]:2 RJsrc = val;\n}\n\n\n#la-privileged-32.txt iocsrwr.w mask=0x06481800\t\n#0x06481800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrwr.w RDsrc, RJsrc is op10_31=0x19206 & RDsrc & RJsrc {\n local val:4= RDsrc:4;\n *[iocsr]:4 RJsrc = val;\n}\n\n\ndefine pcodeop tlbclr;\n#la-privileged-32.txt tlbclr mask=0x06482000\t\n#0x06482000\t0xffffffff\n:tlbclr is instword=0x06482000 {\n\ttlbclr();\n}\n\n\ndefine pcodeop tlbflush;\n#la-privileged-32.txt tlbflush mask=0x06482400\t\n#0x06482400\t0xffffffff\n:tlbflush is instword=0x06482400 {\n\ttlbflush();\n}\n\n\ndefine pcodeop tlbsrch;\n#la-privileged-32.txt tlbsrch mask=0x06482800\t[@primary]\n#0x06482800\t0xffffffff\n:tlbsrch is instword=0x06482800 {\n\ttlbsrch();\n}\n\n\ndefine pcodeop tlbrd;\n#la-privileged-32.txt tlbrd mask=0x06482c00\t[@primary]\n#0x06482c00\t0xffffffff\n:tlbrd is instword=0x06482c00 {\n\ttlbrd();\n}\n\n\ndefine pcodeop tlbwr;\n#la-privileged-32.txt tlbwr mask=0x06483000\t[@primary]\n#0x06483000\t0xffffffff\n:tlbwr is instword=0x06483000 {\n\ttlbwr();\n}\n\n\ndefine pcodeop tlbfill;\n#la-privileged-32.txt tlbfill mask=0x06483400\t[@primary]\n#0x06483400\t0xffffffff\n:tlbfill is instword=0x06483400 {\n\ttlbfill();\n}\n\n\ndefine pcodeop ertn;\n#la-privileged-32.txt eret mask=0x06483800\t[@orig_name=ertn, @primary]\n#0x06483800\t0xffffffff\n:ertn is instword=0x06483800 {\n\tlocal ret:$(REGSIZE) = ertn();\n\treturn [ret];\n}\n\n\ndefine pcodeop idle;\n#la-privileged-32.txt idle mask=0x06488000\t[@primary]\n#0x06488000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:idle imm0_15 is op15_31=0xc91 & imm0_15 {\n\tidle(imm0_15:2);\n}\n\n\ndefine pcodeop invtlb;\n#la-privileged-32.txt tlbinv mask=0x06498000\t[@orig_name=invtlb, @orig_fmt=Ud5JK, @primary]\n#0x06498000\t0xffff8000\tu0:5,r5:5,r10:5\t['imm0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:invtlb RJsrc, RKsrc, imm0_5 is op15_31=0xc93 & RJsrc & RKsrc & imm0_5 {\n\tinvtlb(RJsrc, RKsrc, imm0_5:1);\n}\n\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch64.pspec", "content": "\n\n\n\n \n\n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch64_f32.slaspec", "content": "@define LA64 \"\"\n\n@define REGSIZE 8\n@define FREGSIZE 4\n@define ADDRSIZE 8\n@include \"loongarch_main.sinc\"\n@include \"loongarch32_instructions.sinc\"\n@include \"loongarch64_instructions.sinc\"\n@include \"loongarch_float.sinc\"\n@include \"loongarch_double.sinc\"\n\n\n@include \"lasx.sinc\"\n@include \"lbt.sinc\"\n@include \"lsx.sinc\"\n@include \"lvz.sinc\"\n\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch64_f64.slaspec", "content": "@define LA64 \"\"\n\n@define REGSIZE 8\n@define FREGSIZE 8\n@define ADDRSIZE 8\n@include \"loongarch_main.sinc\"\n@include \"loongarch32_instructions.sinc\"\n@include \"loongarch64_instructions.sinc\"\n@include \"loongarch_float.sinc\"\n@include \"loongarch_double.sinc\"\n\n@include \"lasx.sinc\"\n@include \"lbt.sinc\"\n@include \"lsx.sinc\"\n@include \"lvz.sinc\"\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch64_instructions.sinc", "content": "###################\n# Base Instructions\n###################\n\n#la-base-64.txt add.d mask=0x00108000\t[@qemu]\n#0x00108000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:add.d RD, RJsrc, RKsrc is op15_31=0x21 & RD & RJsrc & RKsrc {\n\tRD = RJsrc + RKsrc;\n}\n\n#la-base-64.txt addi.d mask=0x02c00000\t[@qemu]\n#0x02c00000\t0xffc00000\tr0:5,r5:5,s10:12\t['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0']\n:addi.d RD, RJsrc,simm10_12 is op22_31=0xb & RD & RJsrc & simm10_12 {\n\tRD = RJsrc + simm10_12;\n}\n\n#la-base-64.txt addu16i.d mask=0x10000000\t[@qemu]\n#0x10000000\t0xfc000000\tr0:5,r5:5,s10:16\t['reg0_5_s0', 'reg5_5_s0', 'simm10_16_s0']\n:addu16i.d RD, RJsrc, addu16_imm is op26_31=0x4 & RD & RJsrc & addu16_imm {\n\tRD = RJsrc + addu16_imm;\n}\n\n\n#la-bitops-64.txt sladd.d mask=0x002c0000\t[@orig_name=alsl.d, @orig_fmt=DJKUa2pp1]\n#0x002c0000\t0xfffe0000\tr0:5,r5:5,r10:5,u15:2+1\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0']\n:alsl.d RD, RJsrc, RKsrc, alsl_shift is op17_31=0x16 & RD & RJsrc & RKsrc & alsl_shift {\n\tRD = (RJsrc << alsl_shift) + RKsrc;\n}\n\n#la-bitops-64.txt sladd.wu mask=0x00060000\t[@orig_name=alsl.wu, @orig_fmt=DJKUa2pp1]\n#0x00060000\t0xfffe0000\tr0:5,r5:5,r10:5,u15:2+1\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0']\n:alsl.wu RD, RJ32src, RK32src, alsl_shift is op17_31=0x3 & RD & RJ32src & RK32src & alsl_shift {\n\tlocal result:4 = (RJ32src << alsl_shift) + RK32src;\n\tRD = zext(result);\n}\n\n\n#la-mul-64.txt div.d mask=0x00220000\t[@qemu]\n#0x00220000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:div.d RD, RJsrc, RKsrc is op15_31=0x44 & RD & RJsrc & RKsrc {\n\tRD = RJsrc s/ RKsrc;\n}\n\n\n\n\n#la-mul-64.txt div.du mask=0x00230000\t[@qemu]\n#0x00230000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:div.du RD, RJsrc, RKsrc is op15_31=0x46 & RD & RJsrc & RKsrc {\n\tRD = RJsrc / RKsrc;\n}\n\n\n#la-mul-64.txt mod.d mask=0x00228000\t[@qemu]\n#0x00228000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mod.d RD, RJsrc, RKsrc is op15_31=0x45 & RD & RJsrc & RKsrc {\n\tRD = RJsrc s% RKsrc;\n}\n\n#la-mul-64.txt mod.du mask=0x00238000\t[@qemu]\n#0x00238000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mod.du RD, RJsrc, RKsrc is op15_31=0x47 & RD & RJsrc & RKsrc {\n\tRD = RJsrc % RKsrc;\n}\n\n\n#la-mul-64.txt mul.d mask=0x001d8000\t[@qemu]\n#0x001d8000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mul.d RD, RJsrc, RKsrc is op15_31=0x3b & RD & RJsrc & RKsrc {\n\ttmp1:16 = sext( RJsrc );\n\ttmp2:16 = sext( RKsrc );\n\tprod:16 = tmp1 * tmp2;\n\tRD = prod:8;\n}\n\n#la-mul-64.txt mulh.d mask=0x001e0000\t[@qemu]\n#0x001e0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mulh.d RD, RJsrc, RKsrc is op15_31=0x3c & RD & RJsrc & RKsrc {\n\ttmp1:16 = sext( RJsrc );\n\ttmp2:16 = sext( RKsrc );\n\tprod:16 = tmp1 * tmp2;\n\tprod = prod >> 64;\n\tRD = prod:8;\n}\n\n#la-mul-64.txt mulh.du mask=0x001e8000\t[@qemu]\n#0x001e8000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mulh.du RD, RJsrc, RKsrc is op15_31=0x3d & RD & RJsrc & RKsrc {\n\ttmp1:16 = zext( RJsrc );\n\ttmp2:16 = zext( RKsrc );\n\tprod:16 = tmp1 * tmp2;\n\tprod = prod >> 64;\n\tRD = prod:8;\n}\n\n\n#la-mul-64.txt mulw.d.w mask=0x001f0000\t\n#0x001f0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mulw.d.w RD, RJ32src, RK32src is op15_31=0x3e & RD & RJ32src & RK32src {\n\ttmp1:8 = sext( RJ32src );\n\ttmp2:8 = sext( RK32src );\n\tprod:8 = tmp1 * tmp2;\n\tRD = prod;\n}\n\n#la-mul-64.txt mulw.d.wu mask=0x001f8000\t\n#0x001f8000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:mulw.d.wu RD, RJ32src, RK32src is op15_31=0x3f & RD & RJ32src & RK32src {\n\ttmp1:8 = zext( RJ32src );\n\ttmp2:8 = zext( RK32src );\n\tprod:8 = tmp1 * tmp2;\n\tRD = prod;\n}\n\n\n#la-base-64.txt rdtime.d mask=0x00006800\t\n#0x00006800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:rdtime.d RD, RJ is op10_31=0x1a & RD & RJ {\n\tlocal tmp:1 = 2;\n\tRD = rdtime.counter(tmp);\n\tRJ = rdtime.counterid(tmp);\n}\n\n\n#la-base-64.txt rotr.d mask=0x001b8000\t[@qemu]\n#0x001b8000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:rotr.d RD, RJsrc, RKsrc is op15_31=0x37 & RD & RJsrc & RKsrc {\n\tlocal shift:1 = RKsrc(0) & 0x3f;\n\tlocal tmp1:8 = RJsrc s>> shift;\n\tlocal tmp2:8 = RJsrc << (64 - shift);\n\tRD = tmp1 + tmp2;\n}\n\n#la-base-64.txt rotri.d mask=0x004d0000\t[@qemu]\n#0x004d0000\t0xffff0000\tr0:5,r5:5,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0']\n:rotri.d RD, RJsrc, imm10_6 is op16_31=0x4d & RD & RJsrc & imm10_6 {\n\tlocal shift:1 = imm10_6 & 0x3f;\n\tlocal tmp1:8 = RJsrc s>> shift;\n\tlocal tmp2:8 = RJsrc << (64 - shift);\n\tRD = tmp1 + tmp2;\n}\n\n\n#la-base-64.txt sll.d mask=0x00188000\t[@qemu]\n#0x00188000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sll.d RD, RJsrc, RKsrc is op15_31=0x31 & RD & RJsrc & RKsrc {\n\tlocal shift:1 = RKsrc(0) & 0x3f;\n\tRD = RJsrc << shift;\n}\n\n#la-base-64.txt slli.d mask=0x00410000\t[@qemu]\n#0x00410000\t0xffff0000\tr0:5,r5:5,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0']\n:slli.d RD, RJsrc, imm10_6 is op16_31=0x41 & RD & RJsrc & imm10_6 {\n\tlocal shift:1 = imm10_6 & 0x1f;\n\tRD = RJsrc << shift;\n}\n\n\n#la-base-64.txt sra.d mask=0x00198000\t[@qemu]\n#0x00198000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sra.d RD, RJsrc, RKsrc is op15_31=0x33 & RD & RJsrc & RKsrc {\n\tlocal shift:1 = RKsrc(0) & 0x3f;\n\tRD = RJsrc s>> shift;\n}\n\n#la-base-64.txt srai.d mask=0x00490000\t[@qemu]\n#0x00490000\t0xffff0000\tr0:5,r5:5,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0']\n:srai.d RD, RJsrc, imm10_6 is op16_31=0x49 & RD & RJsrc & imm10_6 {\n\tlocal shift:1 = imm10_6 & 0x1f;\n\tRD = RJsrc s>> shift;\n}\n\n\n#la-base-64.txt srl.d mask=0x00190000\t[@qemu]\n#0x00190000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:srl.d RD, RJsrc, RKsrc is op15_31=0x32 & RD & RJsrc & RKsrc {\n\tlocal shift:1 = RKsrc(0) & 0x3f;\n\tRD = RJsrc >> shift;\n}\n\n#la-base-64.txt srli.d mask=0x00450000\t[@qemu]\n#0x00450000\t0xffff0000\tr0:5,r5:5,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0']\n:srli.d RD, RJsrc, imm10_6 is op16_31=0x45 & RD & RJsrc & imm10_6 {\n\tlocal shift:1 = imm10_6 & 0x1f;\n\tRD = RJsrc >> shift;\n}\n\n\n#la-base-64.txt sub.d mask=0x00118000\t[@qemu]\n#0x00118000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:sub.d RD, RJsrc, RKsrc is op15_31=0x23 & RD & RJsrc & RKsrc {\n\tRD = RJsrc - RKsrc;\n}\n\n\n##########################\n# Load/Store Instructions\n##########################\n\n\n#la-base-64.txt cu52i.d mask=0x03000000\t[@orig_name=lu52i.d, @qemu]\n#0x03000000\t0xffc00000\tr0:5,r5:5,s10:12\t['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0']\n:lu52i.d RD, RJsrc, simm52i is op22_31=0xc & RD & RJsrc & simm52i {\n\tRD = simm52i + (RJsrc & 0xfffffffffffff);\n}\n\n\n#la-base-64.txt cu32i.d mask=0x16000000\t[@orig_name=lu32i.d, @qemu]\n#0x16000000\t0xfe000000\tr0:5,s5:20\t['reg0_5_s0', 'simm5_20_s0']\n:lu32i.d RD, simm32i is op25_31=0xb & RD & RD32 & simm32i {\n\tRD = simm32i + zext(RD32);\n}\n\n\n#la-base-64.txt ldox4.d mask=0x26000000\t[@orig_name=ldptr.d, @orig_fmt=DJSk14ps2]\n#0x26000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:ldptr.d RD, ldstptr_addr is op24_31=0x26 & RD & ldstptr_addr {\n\tRD = *[ram]:8 ldstptr_addr;\n}\n\n\n#la-base-64.txt stox4.d mask=0x27000000\t[@orig_name=stptr.d, @orig_fmt=DJSk14ps2]\n#0x27000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:stptr.d RDsrc, ldstptr_addr is op24_31=0x27 & RDsrc & ldstptr_addr {\n\t*[ram]:8 ldstptr_addr = RDsrc;\n}\n\n\n#la-base-64.txt ld.d mask=0x28c00000\t[@qemu]\n#0x28c00000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.d RD, ldst_addr is op22_31=0xa3 & RD & ldst_addr {\n\tRD = *[ram]:8 ldst_addr;\n}\n\n\n#la-base-64.txt st.d mask=0x29c00000\t[@qemu]\n#0x29c00000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:st.d RDsrc, ldst_addr is op22_31=0xa7 & RDsrc & ldst_addr {\n\t*[ram]:8 ldst_addr = RDsrc;\n}\n\n\n#la-base-64.txt ld.wu mask=0x2a800000\t[@qemu]\n#0x2a800000\t0xffc00000\tr0:5,r5:5,so10:12\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:ld.wu RD, ldst_addr is op22_31=0xaa & RD & ldst_addr {\n\tRD = zext(*[ram]:4 ldst_addr);\n}\n\n\n#la-base-64.txt ldx.d mask=0x380c0000\t[@qemu]\n#0x380c0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.d RD, ldstx_addr is op15_31=0x7018 & RD & ldstx_addr {\n\tRD = *[ram]:8 ldstx_addr;\n}\n\n\n#la-base-64.txt stx.d mask=0x381c0000\t[@qemu]\n#0x381c0000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stx.d RDsrc, ldstx_addr is op15_31=0x7038 & RDsrc & ldstx_addr {\n\t*[ram]:8 ldstx_addr = RDsrc;\n}\n\n\n#la-base-64.txt ldx.wu mask=0x38280000\t[@qemu]\n#0x38280000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldx.wu RD, ldstx_addr is op15_31=0x7050 & RD & ldstx_addr {\n\tRD = zext(*[ram]:4 ldstx_addr);\n}\n\n\n######################\n# Atomic Instructions\n######################\n\n\n#la-atomics-64.txt ll.d mask=0x22000000\t[@orig_fmt=DJSk14ps2]\n#0x22000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:ll.d RD, ldstptr_addr is op24_31=0x22 & RD & ldstptr_addr {\n\tRD = *[ram]:8 ldstptr_addr;\n}\n\n\n#la-atomics-64.txt sc.d mask=0x23000000\t[@orig_fmt=DJSk14ps2]\n#0x23000000\t0xff000000\tr0:5,r5:5,so10:14<<2\t['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0']\n:sc.d RD, ldstptr_addr is op24_31=0x23 & RD & ldstptr_addr {\n\t*[ram]:8 ldstptr_addr = RD;\n}\n\n\n#la-atomics-64.txt amswap.d mask=0x38608000\t[@orig_fmt=DKJ]\n#0x38608000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amswap.d RD, RJsrc, RKsrc is op15_31=0x70c1 & RD & RJsrc & RKsrc {\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = RKsrc;\n}\n\n\n#la-atomics-64.txt amadd.d mask=0x38618000\t[@orig_fmt=DKJ]\n#0x38618000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amadd.d RD, RJsrc, RKsrc is op15_31=0x70c3 & RD & RJsrc & RKsrc {\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc + val);\n}\n\n\n#la-atomics-64.txt amand.d mask=0x38628000\t[@orig_fmt=DKJ]\n#0x38628000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amand.d RD, RJsrc, RKsrc is op15_31=0x70c5 & RD & RJsrc & RKsrc {\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc & val);\n}\n\n\n#la-atomics-64.txt amor.d mask=0x38638000\t[@orig_fmt=DKJ]\n#0x38638000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amor.d RD, RJsrc, RKsrc is op15_31=0x70c7 & RD & RJsrc & RKsrc {\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc | val);\n}\n\n\n#la-atomics-64.txt amxor.d mask=0x38648000\t[@orig_fmt=DKJ]\n#0x38648000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amxor.d RD, RJsrc, RKsrc is op15_31=0x70c9 & RD & RJsrc & RKsrc {\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc ^ val);\n}\n\n\n#la-atomics-64.txt ammax.d mask=0x38658000\t[@orig_fmt=DKJ]\n#0x38658000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax.d RD, RJsrc, RKsrc is op15_31=0x70cb & RD & RJsrc & RKsrc {\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 s>= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammin.d mask=0x38668000\t[@orig_fmt=DKJ]\n#0x38668000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin.d RD, RJsrc, RKsrc is op15_31=0x70cd & RD & RJsrc & RKsrc {\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 s<= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammax.wu mask=0x38670000\t[@orig_fmt=DKJ]\n#0x38670000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax.wu RD, RJsrc, RK32src is op15_31=0x70ce & RD & RJsrc & RK32src {\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 >= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammax.du mask=0x38678000\t[@orig_fmt=DKJ]\n#0x38678000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax.du RD, RJsrc, RKsrc is op15_31=0x70cf & RD & RJsrc & RKsrc {\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 >= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammin.wu mask=0x38680000\t[@orig_fmt=DKJ]\n#0x38680000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin.wu RD, RJsrc, RK32src is op15_31=0x70d0 & RD & RJsrc & RK32src {\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 <= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammin.du mask=0x38688000\t[@orig_fmt=DKJ]\n#0x38688000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin.du RD, RJsrc, RKsrc is op15_31=0x70d1 & RD & RJsrc & RKsrc {\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 <= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt amswap_db.d mask=0x38698000\t[@orig_fmt=DKJ]\n#0x38698000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amswap_db.d RD, RJsrc, RKsrc is op15_31=0x70d3 & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = RKsrc;\n}\n\n\n#la-atomics-64.txt amadd_db.d mask=0x386a8000\t[@orig_fmt=DKJ]\n#0x386a8000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amadd_db.d RD, RJsrc, RKsrc is op15_31=0x70d5 & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc + val);\n}\n\n\n#la-atomics-64.txt amand_db.d mask=0x386b8000\t[@orig_fmt=DKJ]\n#0x386b8000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amand_db.d RD, RJsrc, RKsrc is op15_31=0x70d7 & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc & val);\n}\n\n\n#la-atomics-64.txt amor_db.d mask=0x386c8000\t[@orig_fmt=DKJ]\n#0x386c8000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amor_db.d RD, RJsrc, RKsrc is op15_31=0x70d9 & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc | val);\n}\n\n\n#la-atomics-64.txt amxor_db.d mask=0x386d8000\t[@orig_fmt=DKJ]\n#0x386d8000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:amxor_db.d RD, RJsrc, RKsrc is op15_31=0x70db & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val:8 = *[ram]:8 RJsrc;\n\tRD = val;\n\t*[ram]:8 RJsrc = (RKsrc ^ val);\n}\n\n\n#la-atomics-64.txt ammax_db.d mask=0x386e8000\t[@orig_fmt=DKJ]\n#0x386e8000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax_db.d RD, RJsrc, RKsrc is op15_31=0x70dd & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 s>= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammin_db.d mask=0x386f8000\t[@orig_fmt=DKJ]\n#0x386f8000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin_db.d RD, RJsrc, RKsrc is op15_31=0x70df & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 s<= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammax_db.wu mask=0x38700000\t[@orig_fmt=DKJ]\n#0x38700000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax_db.wu RD, RJsrc, RK32src is op15_31=0x70e0 & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 >= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammax_db.du mask=0x38708000\t[@orig_fmt=DKJ]\n#0x38708000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammax_db.du RD, RJsrc, RKsrc is op15_31=0x70e1 & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 >= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammin_db.wu mask=0x38710000\t[@orig_fmt=DKJ]\n#0x38710000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin_db.wu RD, RJsrc, RK32src is op15_31=0x70e2 & RD & RJsrc & RK32src {\n\tdbar(0:1);\n\tlocal val1:4 = *[ram]:4 RJsrc;\n\tlocal val2:4 = RK32src;\n\tlocal test = (val1 <= val2);\n\tRD = sext(val1);\n\t*[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n#la-atomics-64.txt ammin_db.du mask=0x38718000\t[@orig_fmt=DKJ]\n#0x38718000\t0xffff8000\tr0:5,r10:5,r5:5\t['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0']\n:ammin_db.du RD, RJsrc, RKsrc is op15_31=0x70e3 & RD & RJsrc & RKsrc {\n\tdbar(0:1);\n\tlocal val1:8 = *[ram]:8 RJsrc;\n\tlocal val2:8 = RKsrc;\n\tlocal test = (val1 <= val2);\n\tRD = val1;\n\t*[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2);\n}\n\n\n################################\n# Bit-manipulation Instructions\n################################\n\n\n#la-bitops-64.txt clo.d mask=0x00002000\t\n#0x00002000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:clo.d RD, RJsrc is op10_31=0x8 & RD & RJsrc {\n\tRD = lzcount( ~RJsrc );\n}\n\n\n#la-bitops-64.txt clz.d mask=0x00002400\t[@qemu]\n#0x00002400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:clz.d RD, RJsrc is op10_31=0x9 & RD & RJsrc {\n\tRD = lzcount( RJsrc );\n}\n\n\n#la-bitops-64.txt cto.d mask=0x00002800\t\n#0x00002800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:cto.d RD, RJsrc is op10_31=0xa & RD & RJsrc {\n\tlocal tmp:8 = 0;\n\ttzcount64(~RJsrc, tmp);\n\tRD = tmp;\n}\n\n\n#la-bitops-64.txt ctz.d mask=0x00002c00\t[@qemu]\n#0x00002c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:ctz.d RD, RJsrc is op10_31=0xb & RD & RJsrc {\n\tlocal tmp:8 = 0;\n\ttzcount64(RJsrc, tmp);\n\tRD = tmp;\n}\n\n\n#la-bitops-64.txt revb.4h mask=0x00003400\t\n#0x00003400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:revb.4h RD, RJsrc is op10_31=0xd & RD & RJsrc {\n\ttmp0:8 = (zext(RJsrc[0,8]) << 8) + zext(RJsrc[8,8]);\n\ttmp1:8 = (zext(RJsrc[16,8]) << 8) + zext(RJsrc[24,8]);\n\ttmp2:8 = (zext(RJsrc[32,8]) << 8) + zext(RJsrc[40,8]);\n\ttmp3:8 = (zext(RJsrc[48,8]) << 8) + zext(RJsrc[56,8]);\n\n\tRD = (tmp3 << 48) + (tmp2 << 32) + (tmp1 << 16) + tmp0;\n}\n\n\n#la-bitops-64.txt revb.2w mask=0x00003800\t[@qemu]\n#0x00003800\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:revb.2w RD, RJsrc is op10_31=0xe & RD & RJsrc {\n\ttmp0:8 = (zext(RJsrc[0,8]) << 24) + (zext(RJsrc[8,8]) << 16) + (zext(RJsrc[16,8]) << 8) + zext(RJsrc[24,8]);\n\ttmp1:8 = (zext(RJsrc[32,8]) << 24) + (zext(RJsrc[40,8]) << 16) + (zext(RJsrc[48,8]) << 8) + zext(RJsrc[56,8]);\n\n\tRD = (tmp1 << 32) + tmp0;\n}\n\n\n#la-bitops-64.txt revb.d mask=0x00003c00\t[@qemu]\n#0x00003c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:revb.d RD, RJsrc is op10_31=0xf & RD & RJsrc {\n\ttmp0:8 = zext(RJsrc[0,8]);\n\ttmp1:8 = zext(RJsrc[8,8]);\n\ttmp2:8 = zext(RJsrc[16,8]);\n\ttmp3:8 = zext(RJsrc[24,8]);\n\ttmp4:8 = zext(RJsrc[32,8]);\n\ttmp5:8 = zext(RJsrc[40,8]);\n\ttmp6:8 = zext(RJsrc[48,8]);\n\ttmp7:8 = zext(RJsrc[56,8]);\n\n\tRD = (tmp0 << 56) + (tmp1 << 48) + (tmp2 << 40) + (tmp3 << 32) + (tmp4 << 24) + (tmp5 << 16) + (tmp6 << 8) + tmp7;\n}\n\n\n#la-bitops-64.txt revh.2w mask=0x00004000\t\n#0x00004000\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:revh.2w RD, RJsrc is op10_31=0x10 & RD & RJsrc {\n\ttmp0:8 = (zext(RJsrc[0,16]) << 16) + zext(RJsrc[16,16]);\n\ttmp1:8 = (zext(RJsrc[32,16]) << 8) + zext(RJsrc[48,16]);\n\n\tRD = (tmp1 << 32) + tmp0;\n}\n\n\n#la-bitops-64.txt revh.d mask=0x00004400\t\n#0x00004400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:revh.d RD, RJsrc is op10_31=0x11 & RD & RJsrc {\n\ttmp0:8 = zext(RJsrc[0,16]);\n\ttmp1:8 = zext(RJsrc[16,16]);\n\ttmp2:8 = zext(RJsrc[32,16]);\n\ttmp3:8 = zext(RJsrc[48,16]);\n\n\tRD = (tmp3 << 48) + (tmp2 << 32) + (tmp1 << 16) + tmp0;\n}\n\n\n#la-bitops-64.txt revbit.8b mask=0x00004c00\t[@orig_name=bitrev.8b]\n#0x00004c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:bitrev.8b RD, RJsrc is op10_31=0x13 & RD & RJsrc {\n\tlocal v:8 = 0;\n\tbyterev64(RJsrc, v);\n\tRD = v;\n}\n\n\n#la-bitops-64.txt revbit.d mask=0x00005400\t[@orig_name=bitrev.d]\n#0x00005400\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:bitrev.d RD, RJsrc is op10_31=0x15 & RD & RJsrc {\n\tlocal v:8 = 0;\n\tbitrev64(RJsrc, v);\n\tRD = v;\n}\n\ndefine pcodeop bytepick.d;\n\n#la-bitops-64.txt catpick.d mask=0x000c0000\t[@orig_name=bytepick.d]\n#0x000c0000\t0xfffc0000\tr0:5,r5:5,r10:5,u15:3\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_3_s0']\n:bytepick.d RD, RJsrc, RKsrc, imm15_3 is op18_31=0x3 & RD & RJsrc & RKsrc & imm15_3 {\n\tlocal bitstop:1 = 8 * (8 - imm15_3);\n\tlocal mask:8 = (1 << bitstop) - 1;\n\tlocal tmp_hi:8 = RKsrc & ~mask;\n\tlocal tmp_lo:8 = (RJsrc & (mask << (64-bitstop)) >> (64-bitstop));\n\tRD = tmp_hi + tmp_lo;\n}\n\ndefine pcodeop crc.w.d.w;\n\n#la-bitops-64.txt crc.w.d.w mask=0x00258000\t\n#0x00258000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crc.w.d.w RD, RJsrc, RKsrc is op15_31=0x4b & RD & RJsrc & RKsrc {\n\tRD = crc_ieee802.3(RKsrc, RJsrc, 64:1, 0xedb88320:4);\n}\n\ndefine pcodeop crcc.w.d.w;\n\n#la-bitops-64.txt crcc.w.d.w mask=0x00278000\t\n#0x00278000\t0xffff8000\tr0:5,r5:5,r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:crcc.w.d.w RD, RJsrc, RKsrc is op15_31=0x4f & RD & RJsrc & RKsrc {\n\tRD = crc_castagnoli(RKsrc, RJsrc, 64:1, 0x82f63b78:4);\n}\n\n\n#la-bitops-64.txt bstrins.d mask=0x00800000\t[@orig_fmt=DJUm6Uk6, @qemu]\n#0x00800000\t0xffc00000\tr0:5,r5:5,u16:6,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm16_6_s0', 'imm10_6_s0']\n:bstrins.d RD, RJsrc, imm16_6, imm10_6 is op22_31=0x2 & RD & RJsrc & imm10_6 & imm16_6 {\n\tlocal msb:1 = imm16_6;\n\tlocal lsb:1 = imm10_6;\n\tlocal len:1 = msb + 1 - lsb;\n\tlocal mask:8 = (1 << len) - 1;\n\tlocal repl:8 = (RJsrc & (mask << lsb)) >> lsb;\n\n\tRD = (RD & (~mask)) | repl;\n}\n\n\n#la-bitops-64.txt bstrpick.d mask=0x00c00000\t[@orig_fmt=DJUm6Uk6, @qemu]\n#0x00c00000\t0xffc00000\tr0:5,r5:5,u16:6,u10:6\t['reg0_5_s0', 'reg5_5_s0', 'imm16_6_s0', 'imm10_6_s0']\n:bstrpick.d RD, RJsrc, imm16_6, imm10_6 is op22_31=0x3 & RD & RJsrc & imm10_6 & imm16_6 {\n\tlocal msb:1 = imm16_6;\n\tlocal lsb:1 = imm10_6;\n\tlocal len:1 = msb + 1 - lsb;\n\tlocal mask:8 = (1 << len) - 1;\n\tlocal repl:8 = (RJsrc & (mask << lsb)) >> lsb;\n\n\tRD = repl;\n}\n\n\n###############################\n# Bounds-checking Instructions\n###############################\n\n\n#la-bound-64.txt ldgt.d mask=0x38798000\t\n#0x38798000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldgt.d RD, RJsrc, RKsrc is op15_31=0x70f3 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:8 vaddr);\n}\n\n#la-bound-64.txt ldle.d mask=0x387b8000\t\n#0x387b8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:ldle.d RD, RJsrc, RKsrc is op15_31=0x70f7 & RD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tRD = sext(*[ram]:1 vaddr);\n}\n\n\n#la-bound-64.txt stgt.d mask=0x387d8000\t\n#0x387d8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stgt.d RDsrc, RJsrc, RKsrc is op15_31=0x70fb & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:8 vaddr = RDsrc:8;\n}\n\n#la-bound-64.txt stle.d mask=0x387f8000\t\n#0x387f8000\t0xffff8000\tr0:5, r5:5, r10:5\t['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:stle.d RDsrc, RJsrc, RKsrc is op15_31=0x70ff & RDsrc & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:8 vaddr = RDsrc:8;\n}\n\n\n#########################\n# PRIVILEGED INSTRUCTIONS\n#########################\n\n#la-privileged-64.txt iocsrrd.d mask=0x06480c00\t\n#0x06480c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrrd.d RD, RJsrc is op10_31=0x19203 & RD & RJsrc {\n\tRD = *[iocsr]:8 RJsrc;\n}\n\n\n#la-privileged-64.txt iocsrwr.d mask=0x06481c00\t\n#0x06481c00\t0xfffffc00\tr0:5,r5:5\t['reg0_5_s0', 'reg5_5_s0']\n:iocsrwr.d RDsrc, RJsrc is op10_31=0x19207 & RDsrc & RJsrc {\n\t*[iocsr]:8 RJsrc = RDsrc;\n}\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch_double.sinc", "content": "\n\n\n#la-fp-d.txt fadd.d mask=0x01010000\t\n#0x01010000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fadd.d drD, drJ, drK is op15_31=0x202 & drD & drJ & drK {\n\tdrD = drJ f+ drK;\n}\n\n\n#la-fp-d.txt fsub.d mask=0x01030000\t\n#0x01030000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fsub.d drD, drJ, drK is op15_31=0x206 & drD & drJ & drK {\n\tdrD = drJ f- drK;\n}\n\n\n#la-fp-d.txt fmul.d mask=0x01050000\t\n#0x01050000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmul.d drD, drJ, drK is op15_31=0x20a & drD & drJ & drK {\n\tdrD = drJ f* drK;\n}\n\n\n#la-fp-d.txt fdiv.d mask=0x01070000\t\n#0x01070000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fdiv.d drD, drJ, drK is op15_31=0x20e & drD & drJ & drK {\n\tdrD = drJ f/ drK;\n}\n\n\n#la-fp-d.txt fmax.d mask=0x01090000\t\n#0x01090000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmax.d drD, drJ, drK is op15_31=0x212 & drD & drJ & drK {\n\tlocal jval = drJ;\n\tlocal kval = drK;\n\tlocal test = jval f>= kval;\n\tdrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n\n#la-fp-d.txt fmin.d mask=0x010b0000\t\n#0x010b0000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmin.d drD, drJ, drK is op15_31=0x216 & drD & drJ & drK {\n\tlocal jval = drJ;\n\tlocal kval = drK;\n\tlocal test = jval f<= kval;\n\tdrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n\n#la-fp-d.txt fmaxa.d mask=0x010d0000\t\n#0x010d0000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmaxa.d drD, drJ, drK is op15_31=0x21a & drD & drJ & drK {\n\tlocal jval = drJ;\n\tlocal kval = drK;\n\tlocal test = (abs(jval) f>= abs(kval));\n\tdrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n\n#la-fp-d.txt fmina.d mask=0x010f0000\t\n#0x010f0000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmina.d drD, drJ, drK is op15_31=0x21e & drD & drJ & drK {\n\tlocal jval = drJ;\n\tlocal kval = drK;\n\tlocal test = (abs(jval) f<= abs(kval));\n\tdrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n\n#la-fp-d.txt fscaleb.d mask=0x01110000\t\n#0x01110000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fscaleb.d drD, drJ, drK is op15_31=0x222 & drD & drJ & drK {\n\tdrD = f_scaleb(drJ, drK);\n}\n\n\n#la-fp-d.txt fcopysign.d mask=0x01130000\t\n#0x01130000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fcopysign.d drD, drJ, drK is op15_31=0x226 & drD & drJ & drK {\n\tlocal kval = drK & 0x8000000000000000;\n\tlocal jval = drJ & 0x7fffffffffffffff;\n\tdrD = kval | jval ;\n}\n\n\n#la-fp-d.txt fabs.d mask=0x01140800\t\n#0x01140800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fabs.d drD, drJ is op10_31=0x4502 & drD & drJ {\n\tdrD = abs(drJ);\n}\n\n\n#la-fp-d.txt fneg.d mask=0x01141800\t\n#0x01141800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fneg.d drD, drJ is op10_31=0x4506 & drD & drJ {\n\tdrD = f- drJ;\n}\n\n\n#la-fp-d.txt flogb.d mask=0x01142800\t\n#0x01142800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:flogb.d drD, drJ is op10_31=0x450a & drD & drJ {\n\tdrD = f_logb(drJ);\n}\n\n\n#la-fp-d.txt fclass.d mask=0x01143800\t\n#0x01143800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fclass.d drD, drJ is op10_31=0x450e & drD & drJ {\n\tdrD = f_class(drD, drJ);\n}\n\n\n#la-fp-d.txt fsqrt.d mask=0x01144800\t\n#0x01144800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fsqrt.d drD, drJ is op10_31=0x4512 & drD & drJ {\n\tdrD = sqrt(drJ);\n}\n\n\n#la-fp-d.txt frecip.d mask=0x01145800\t\n#0x01145800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:frecip.d drD, drJ is op10_31=0x4516 & drD & drJ {\n\tlocal one:4 = 1;\n\tdrD = int2float(one) f/ drJ;\n}\n\n#la-fp-d.txt frsqrt.d mask=0x01146800\t\n#0x01146800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:frsqrt.d drD, drJ is op10_31=0x451a & drD & drJ {\n\tlocal one:4 = 1;\n\tdrD = int2float(one) f/ sqrt(drJ);\n}\n\n#la-fp-d.txt fmov.d mask=0x01149800\t\n#0x01149800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fmov.d drD, drJ is op10_31=0x4526 & drD & drJ {\n\tdrD = drJ;\n}\n\n@ifdef LA64\n#la-fp-d.txt movgr2fr.d mask=0x0114a800\t\n#0x0114a800\t0xfffffc00\tf0:5, r5:5\t['freg0_5_s0', 'reg5_5_s0']\n:movgr2fr.d drD, RJsrc is op10_31=0x452a & drD & RJsrc {\n\tdrD = RJsrc;\n}\n\n\n#la-fp-d.txt movfr2gr.d mask=0x0114b800\t\n#0x0114b800\t0xfffffc00\tr0:5, f5:5\t['reg0_5_s0', 'freg5_5_s0']\n:movfr2gr.d RD, drJ is op10_31=0x452e & RD & drJ {\n\tRD = drJ;\n}\n\n@endif\n\n#la-fp-d.txt fcvt.s.d mask=0x01191800\t\n#0x01191800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fcvt.s.d drD, drJ is op10_31=0x4646 & drD & drJ & frD {\n\tfrD = float2float(drJ);\n}\n\n#la-fp-d.txt fcvt.d.s mask=0x01192400\t\n#0x01192400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fcvt.d.s drD, drJ is op10_31=0x4649 & drD & drJ & frJ {\n\tdrD = float2float(frJ);\n}\n\n\n#la-fp-d.txt ftintrm.w.d mask=0x011a0800\t\n#0x011a0800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrm.w.d drD, drJ is op10_31=0x4682 & drD & drJ {\n\tlocal val:4 = trunc(drJ);\n\tdrD = zext(val);\n}\n\n#la-fp-d.txt ftintrm.l.d mask=0x011a2800\t\n#0x011a2800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrm.l.d drD, drJ is op10_31=0x468a & drD & drJ {\n\tdrD = trunc(drJ);\n}\n\n\n#la-fp-d.txt ftintrp.w.d mask=0x011a4800\t\n#0x011a4800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrp.w.d drD, drJ is op10_31=0x4692 & drD & drJ {\n\tlocal val:4 = trunc(drJ);\n\tdrD = zext(val);\n}\n\n#la-fp-d.txt ftintrp.l.d mask=0x011a6800\t\n#0x011a6800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrp.l.d drD, drJ is op10_31=0x469a & drD & drJ {\n\tdrD = trunc(drJ);\n}\n\n\n#la-fp-d.txt ftintrz.w.d mask=0x011a8800\t\n#0x011a8800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrz.w.d drD, drJ is op10_31=0x46a2 & drD & drJ {\n\tlocal val:4 = trunc(drJ);\n\tdrD = zext(val);\n}\n\n#la-fp-d.txt ftintrz.l.d mask=0x011aa800\t\n#0x011aa800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrz.l.d drD, drJ is op10_31=0x46aa & drD & drJ {\n\tdrD = trunc(drJ);\n}\n\n\n#la-fp-d.txt ftintrne.w.d mask=0x011ac800\t\n#0x011ac800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrne.w.d drD, drJ is op10_31=0x46b2 & drD & drJ {\n\tlocal val:4 = round_even(drJ);\n\tdrD = zext(val);\n}\n\n#la-fp-d.txt ftintrne.l.d mask=0x011ae800\t\n#0x011ae800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrne.l.d drD, drJ is op10_31=0x46ba & drD & drJ {\n\tdrD = round_even(drJ);\n}\n\n\n#la-fp-d.txt ftint.w.d mask=0x011b0800\t\n#0x011b0800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftint.w.d drD, drJ is op10_31=0x46c2 & drD & drJ {\n\tlocal val:4 = trunc(drJ);\n\tdrD = zext(val);\n}\n\n#la-fp-d.txt ftint.l.d mask=0x011b2800\t\n#0x011b2800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftint.l.d drD, drJ is op10_31=0x46ca & drD & drJ {\n\tdrD = trunc(drJ);\n}\n\n\n#la-fp-d.txt ffint.d.w mask=0x011d2000\t\n#0x011d2000\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ffint.d.w drD, drJ is op10_31=0x4748 & drD & drJ & frJ {\n\tdrD = int2float(frJ);\n}\n\n#la-fp-d.txt ffint.d.l mask=0x011d2800\t\n#0x011d2800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ffint.d.l drD, drJ is op10_31=0x474a & drD & drJ {\n\tdrD = int2float(drJ);\n}\n\n\n#la-fp-d.txt frint.d mask=0x011e4800\t\n#0x011e4800\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:frint.d drD, drJ is op10_31=0x4792 & drD & drJ {\n\tlocal val:8 = trunc(drJ);\n\tdrD = int2float(val);\n}\n\n\n#la-fp-d.txt fmadd.d mask=0x08200000\t\n#0x08200000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fmadd.d drD, drJ, drK, drA is op20_31=0x82 & drD & drJ & drK & drA {\n\tdrD = (drJ f* drK) f+ drA;\n}\n\n#la-fp-d.txt fmsub.d mask=0x08600000\t\n#0x08600000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fmsub.d drD, drJ, drK, drA is op20_31=0x86 & drD & drJ & drK & drA {\n\tdrD = (drJ f* drK) f- drA;\n}\n\n#la-fp-d.txt fnmadd.d mask=0x08a00000\t\n#0x08a00000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fnmadd.d drD, drJ, drK, drA is op20_31=0x8a & drD & drJ & drK & drA {\n\tdrD = f- ((drJ f* drK) f+ drA);\n}\n\n#la-fp-d.txt fnmsub.d mask=0x08e00000\t\n#0x08e00000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fnmsub.d drD, drJ, drK, drA is op20_31=0x8e & drD & drJ & drK & drA {\n\tdrD = f- ((drJ f* drK) f- drA);\n}\n\ndSNaN: \"c\" is ccf_s = 0 { }\ndSNaN: \"s\" is ccf_s = 1 { }\n\ndcond: dSNaN^\"af\" is ccf=0x0 & dSNaN { DCMPR = 0; }\ndcond: dSNaN^\"lt\" is ccf=0x1 & dSNaN { DCMPR = DCMP1 f< DCMP2; }\ndcond: dSNaN^\"eq\" is ccf=0x2 & dSNaN { DCMPR = DCMP1 f== DCMP2; }\ndcond: dSNaN^\"le\" is ccf=0x3 & dSNaN { DCMPR = DCMP1 f<= DCMP2; }\ndcond: dSNaN^\"un\" is ccf=0x4 & dSNaN { DCMPR = nan(DCMP1) || nan(DCMP2); }\ndcond: dSNaN^\"ult\" is ccf=0x5 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f< DCMP2); }\ndcond: dSNaN^\"ueq\" is ccf=0x6 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f== DCMP2); }\ndcond: dSNaN^\"ule\" is ccf=0x7 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f<= DCMP2); }\ndcond: dSNaN^\"ne\" is ccf=0x8 & dSNaN { DCMPR = DCMP1 f!= DCMP2; }\ndcond: dSNaN^\"or\" is ccf=0xa & dSNaN { DCMPR = !(nan(DCMP1) || nan(DCMP2)); }\ndcond: dSNaN^\"une\" is ccf=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f!= DCMP2); }\n\n#la-fp-d.txt fcmp.caf.d mask=0x0c200000\t\n#0x0c200000\t0xffff8018\tc0:3, f5:5, f10:5\t['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fcmp.^dcond^\".d\" fccD, drJ, drK is op20_31=0xc2 & dcond & op3_4 = 0 & fccD & drJ & drK {\n\tDCMP1 = drJ;\n\tDCMP2 = drK;\n\tbuild dcond;\n\tfccD = DCMPR;\n}\n\n\n#la-fp-d.txt fld.d mask=0x2b800000\t\n#0x2b800000\t0xffc00000\tf0:5, r5:5, so10:12\t['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:fld.d drD, ldst_addr is op22_31=0xae & drD & ldst_addr {\n\tdrD = sext(*[ram]:8 ldst_addr);\n}\n\n\n#la-fp-d.txt fst.d mask=0x2bc00000\t\n#0x2bc00000\t0xffc00000\tf0:5, r5:5, so10:12\t['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:fst.d drD, ldst_addr is op22_31=0xaf & drD & ldst_addr {\n\t*[ram]:8 ldst_addr = drD;\n}\n\n\n#la-fp-d.txt fldx.d mask=0x38340000\t\n#0x38340000\t0xffff8000\tf0:5, r5:5, r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fldx.d drD, ldstx_addr is op15_31=0x7068 & drD & ldstx_addr {\n\tdrD = *[ram]:8 ldstx_addr;\n}\n\n\n#la-fp-d.txt fstx.d mask=0x383c0000\t\n#0x383c0000\t0xffff8000\tf0:5, r5:5, r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fstx.d drD, ldstx_addr is op15_31=0x7078 & drD & ldstx_addr {\n\t*[ram]:8 ldstx_addr = drD;\n}\n\n#la-bound-fp-d.txt fldgt.d mask=0x38748000\t\n#0x38748000\t0xffff8000\tf0:5,r5:5,r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fldgt.d drD, RJsrc, RKsrc is op15_31=0x70e9 & drD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tdrD = sext(*[ram]:8 vaddr);\n}\n\n\n#la-bound-fp-d.txt fldle.d mask=0x38758000\t\n#0x38758000\t0xffff8000\tf0:5,r5:5,r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fldle.d drD, RJsrc, RKsrc is op15_31=0x70eb & drD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tdrD = sext(*[ram]:8 vaddr);\n}\n\ndefine pcodeop fstgt.d;\n\n#la-bound-fp-d.txt fstgt.d mask=0x38768000\t\n#0x38768000\t0xffff8000\tf0:5,r5:5,r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fstgt.d drD, RJsrc, RKsrc is op15_31=0x70ed & drD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:8 vaddr = drD;\n}\n\ndefine pcodeop fstle.d;\n\n#la-bound-fp-d.txt fstle.d mask=0x38778000\t\n#0x38778000\t0xffff8000\tf0:5,r5:5,r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fstle.d drD, RJsrc, RKsrc is op15_31=0x70ef & drD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:8 vaddr = drD;\n}\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch_float.sinc", "content": "####\n# General Floating-Point Instructions\n####\n\n\n#la-fp.txt fcsrwr mask=0x0114c000\t[@orig_name=movgr2fcsr, @orig_fmt=DJ]\n#0x0114c000\t0xfffffc1c\tfc0:2,r5:5\t['fcreg0_2_s0', 'reg5_5_s0']\n:movgr2fcsr fcsr, RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=0 {\n\tfcsr = RJ32src;\n}\n\n:movgr2fcsr fcsr^\".enables\", RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=1 {\n\tlocal mask:4 = 0x1f;\n\tfcsr = (fcsr & ~mask) + (RJ32src & mask);\n}\n\n:movgr2fcsr fcsr^\".flags_cause\", RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=2 {\n\tlocal mask:4 = 0x1f1f0000;\n\tfcsr = (fcsr & ~mask) + (RJ32src & mask);\n}\n\n:movgr2fcsr fcsr^\".rm\", RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=3 {\n\tlocal mask:4 = 0x300;\n\tfcsr = (fcsr & ~mask) + (RJ32src & mask);\n}\n\ndefine pcodeop uncertain_fcsr;\n\n# per the manual: if the fcsr does not exist, the result is uncertain\n:movgr2fcsr fcsr, RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5 {\n\tuncertain_fcsr(imm0_5:1);\n\tfcsr = RJ32src;\n}\n\n#la-fp.txt fcsrrd mask=0x0114c800\t[@orig_name=movfcsr2gr, @orig_fmt=DJ]\n#0x0114c800\t0xffffff80\tr0:5,fc5:2\t['reg0_5_s0', 'fcreg5_2_s0']\n:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=0 {\n\tRD = sext(fcsr);\n}\n\n:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=1 {\n\tlocal mask:4 = 0x1f;\n\tRD = sext(fcsr & mask);\n}\n\n:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=2 {\n\tlocal mask:4 = 0x1f1f0000;\n\tRD = sext(fcsr & mask);\n}\n\n:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=3 {\n\tlocal mask:4 = 0x300;\n\tRD = sext(fcsr & mask);\n}\n\n# per the manual: if the fcsr does not exist, the result is uncertain\n:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5 {\n\tuncertain_fcsr(imm5_5:1);\n\tRD = sext(fcsr);\n}\n\n\n#la-fp.txt movfr2fcc mask=0x0114d000\t[@orig_name=movfr2cf]\n#0x0114d000\t0xfffffc18\tc0:3,f5:5\t['fcc0_3_s0', 'freg5_5_s0']\n:movfr2cf fccD, FRJ is op11_31=0x229a & fccD & FRJ {\n\tfccD = FRJ[0,1];\n}\n\n#la-fp.txt movfcc2fr mask=0x0114d400\t[@orig_name=movcf2fr]\n#0x0114d400\t0xffffff00\tf0:5,c5:3\t['freg0_5_s0', 'fcc5_3_s0']\n:movcf2fr FRD, fccJ is op10_31=0x4535 & FRD & fccJ {\n\tFRD[0,1] = fccJ[0,1];\n}\n\n#la-fp.txt movgr2fcc mask=0x0114d800\t[@orig_name=movgr2cf]\n#0x0114d800\t0xfffffc18\tc0:3,r5:5\t['fcc0_3_s0', 'reg5_5_s0']\n:movgr2cf fccD, RJsrc is op10_31=0x4536 & fccD & RJsrc {\n\tfccD = RJsrc[0,1];\n}\n\n#la-fp.txt movfcc2gr mask=0x0114dc00\t[@orig_name=movcf2gr]\n#0x0114dc00\t0xffffff00\tr0:5,c5:3\t['reg0_5_s0', 'fcc5_3_s0']\n:movcf2gr RD, fccJ is op10_31=0x4537 & RD & fccJ {\n\tRD[0,1] = fccJ[0,1];\n}\n\n\n#la-fp.txt fsel mask=0x0d000000\t\n#0x0d000000\t0xfffc0000\tf0:5,f5:5,f10:5,c15:3\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'fcc15_3_s0']\n:fsel FRD, FRJ, FRK, fccA is op20_31=0xd0 & FRD & FRJ & FRK & fccA {\n\tlocal test:1 = (fccA == 0);\n\tFRD = (zext(!test) * FRK) + (zext(test) * FRJ);\n}\n\n\n#la-fp.txt bceqz mask=0x48000000\t[@orig_fmt=CjSd5k16ps2]\n#0x48000000\t0xfc000300\tc5:3,sb0:5|10:16<<2\t['fcc5_3_s0', 'sbranch0_0_s2']\n:bceqz fccJ, Rel21 is op26_31=0x12 & fccJ & op8_9=0 & Rel21 {\n\tif(fccJ == 0) goto Rel21;\n}\n\n\n#la-fp.txt bcnez mask=0x48000100\t[@orig_fmt=CjSd5k16ps2]\n#0x48000100\t0xfc000300\tc5:3,sb0:5|10:16<<2\t['fcc5_3_s0', 'sbranch0_0_s2']\n:bcnez fccJ, Rel21 is op26_31=0x12 & fccJ & op8_9=1 & Rel21 {\n\tif(fccJ != 0) goto Rel21;\n}\n\n\n#####################################\n# Floating-Point Single Instructions\n#####################################\n\n\n#la-fp-s.txt fadd.s mask=0x01008000\t\n#0x01008000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fadd.s frD, frJ, frK is op15_31=0x201 & frD & frJ & frK {\n\tfrD = frJ f+ frK;\n}\n\n#la-fp-s.txt fsub.s mask=0x01028000\t\n#0x01028000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fsub.s frD, frJ, frK is op15_31=0x205 & frD & frJ & frK {\n\tfrD = frJ f- frK;\n}\n\n#la-fp-s.txt fmul.s mask=0x01048000\t\n#0x01048000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmul.s frD, frJ, frK is op15_31=0x209 & frD & frJ & frK {\n\tfrD = frJ f* frK;\n}\n\n#la-fp-s.txt fdiv.s mask=0x01068000\t\n#0x01068000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fdiv.s frD, frJ, frK is op15_31=0x20d & frD & frJ & frK {\n\tfrD = frJ f/ frK;\n}\n\n\n#la-fp-s.txt fmadd.s mask=0x08100000\t\n#0x08100000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fmadd.s frD, frJ, frK, frA is op20_31=0x81 & frD & frJ & frK & frA {\n\tfrD = (frJ f* frK) f+ frA;\n}\n\n#la-fp-s.txt fmsub.s mask=0x08500000\t\n#0x08500000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fmsub.s frD, frJ, frK, frA is op20_31=0x85 & frD & frJ & frK & frA {\n\tfrD = (frJ f* frK) f- frA;\n}\n\n#la-fp-s.txt fnmadd.s mask=0x08900000\t\n#0x08900000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fnmadd.s frD, frJ, frK, frA is op20_31=0x89 & frD & frJ & frK & frA {\n\tfrD = f- ((frJ f* frK) f+ frA);\n}\n\n#la-fp-s.txt fnmsub.s mask=0x08d00000\t\n#0x08d00000\t0xfff00000\tf0:5, f5:5, f10:5, f15:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0']\n:fnmsub.s frD, frJ, frK, frA is op20_31=0x8d & frD & frJ & frK & frA {\n\tfrD = f- ((frJ f* frK) f- frA);\n}\n\n\n#la-fp-s.txt fmax.s mask=0x01088000\t\n#0x01088000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmax.s frD, frJ, frK is op15_31=0x211 & frD & frJ & frK {\n\tlocal jval = frJ;\n\tlocal kval = frK;\n\tlocal test = (jval f>= kval);\n\tfrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n#la-fp-s.txt fmin.s mask=0x010a8000\t\n#0x010a8000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmin.s frD, frJ, frK is op15_31=0x215 & frD & frJ & frK {\n\tlocal jval = frJ;\n\tlocal kval = frK;\n\tlocal test = (jval f<= kval);\n\tfrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n\n#la-fp-s.txt fmaxa.s mask=0x010c8000\t\n#0x010c8000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmaxa.s frD, frJ, frK is op15_31=0x219 & frD & frJ & frK {\n\tlocal jval = frJ;\n\tlocal kval = frK;\n\tlocal test = (abs(jval) f>= abs(kval));\n\tfrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n#la-fp-s.txt fmina.s mask=0x010e8000\t\n#0x010e8000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fmina.s frD, frJ, frK is op15_31=0x21d & frD & frJ & frK {\n\tlocal jval = frJ;\n\tlocal kval = frK;\n\tlocal test = (abs(jval) f<= abs(kval));\n\tfrD = (zext(test) * jval) + (zext(!test) * kval);\n}\n\n\n#la-fp-s.txt fabs.s mask=0x01140400\t\n#0x01140400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fabs.s frD, frJ is op10_31=0x4501 & frD & frJ {\n\tfrD = abs(frJ);\n}\n\n#la-fp-s.txt fneg.s mask=0x01141400\t\n#0x01141400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fneg.s frD, frJ is op10_31=0x4505 & frD & frJ {\n\tfrD = f- frJ;\n}\n\n\n#la-fp-s.txt fsqrt.s mask=0x01144400\t\n#0x01144400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fsqrt.s frD, frJ is op10_31=0x4511 & frD & frJ {\n\tfrD = sqrt(frJ);\n}\n\n#la-fp-s.txt frecip.s mask=0x01145400\t\n#0x01145400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:frecip.s frD, frJ is op10_31=0x4515 & frD & frJ {\n\tlocal one:4 = 1;\n\tfrD = int2float(one) f/ frJ;\n}\n\n#la-fp-s.txt frsqrt.s mask=0x01146400\t\n#0x01146400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:frsqrt.s frD, frJ is op10_31=0x4519 & frD & frJ {\n\tlocal one:4 = 1;\n\tfrD = int2float(one) f/ sqrt(frJ);\n}\n\n\n#la-fp-s.txt fscaleb.s mask=0x01108000\t\n#0x01108000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fscaleb.s frD, frJ, frK is op15_31=0x221 & frD & frJ & frK {\n\tfrD = f_scaleb(frJ, frK);\n}\n\n\n#la-fp-s.txt flogb.s mask=0x01142400\t\n#0x01142400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:flogb.s frD, frJ is op10_31=0x4509 & frD & frJ {\n\tfrD = f_logb(frJ);\n}\n\n#la-fp-s.txt fcopysign.s mask=0x01128000\t\n#0x01128000\t0xffff8000\tf0:5, f5:5, f10:5\t['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fcopysign.s frD, frJ, frK is op15_31=0x225 & frD & frJ & frK {\n\tlocal kval = frK & 0x80000000;\n\tlocal jval = frJ & 0x7fffffff;\n\tfrD = kval | jval ;\n}\n\n\n#la-fp-s.txt fclass.s mask=0x01143400\t\n#0x01143400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fclass.s frD, frJ is op10_31=0x450d & frD & frJ {\n\tfrD = f_class(frJ);\n}\n\n\n#la-fp-s.txt fmov.s mask=0x01149400\t\n#0x01149400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:fmov.s frD, frJ is op10_31=0x4525 & frD & frJ {\n\tfrD = frJ;\n}\n\n\n#la-fp-s.txt movgr2fr.w mask=0x0114a400\t\n#0x0114a400\t0xfffffc00\tf0:5,r5:5\t['freg0_5_s0', 'reg5_5_s0']\n:movgr2fr.w frD, RJ32src is op10_31=0x4529 & frD & RJ32src {\n\tfrD = RJ32src;\n}\n\n#la-fp-s.txt movgr2frh.w mask=0x0114ac00\t\n#0x0114ac00\t0xfffffc00\tf0:5,r5:5\t['freg0_5_s0', 'reg5_5_s0']\n:movgr2frh.w drD, RJ32src is op10_31=0x452b & drD & RJ32src {\n\tdrD = (zext(RJ32src) << 32) | (drD & 0xffffffff);\n}\n\n\n#la-fp-s.txt movfr2gr.s mask=0x0114b400\t\n#0x0114b400\t0xfffffc00\tr0:5, f5:5\t['reg0_5_s0', 'freg5_5_s0']\n:movfr2gr.s RD, frJ is op10_31=0x452d & RD & frJ {\n\tRD = sext(frJ);\n}\n\n#la-fp-s.txt movfrh2gr.s mask=0x0114bc00\t\n#0x0114bc00\t0xfffffc00\tr0:5, f5:5\t['reg0_5_s0', 'freg5_5_s0']\n:movfrh2gr.s RD, drJ is op10_31=0x452f & RD & drJ {\n\tRD = sext(drJ[32,32]);\n}\n\n\n#la-fp-s.txt ftintrm.w.s mask=0x011a0400\t\n#0x011a0400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrm.w.s frD, frJ is op10_31=0x4681 & frD & frJ {\n\tfrD = trunc(frJ);\n}\n\n#la-fp-s.txt ftintrm.l.s mask=0x011a2400\t\n#0x011a2400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrm.l.s frD, frJ is op10_31=0x4689 & frD & frJ {\n\tlocal val:8 = trunc(frJ);\n\tfrD = val(0);\n}\n\n\n#la-fp-s.txt ftintrp.w.s mask=0x011a4400\t\n#0x011a4400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrp.w.s frD, frJ is op10_31=0x4691 & frD & frJ {\n\tfrD = trunc(frJ);\n}\n\n#la-fp-s.txt ftintrp.l.s mask=0x011a6400\t\n#0x011a6400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrp.l.s frD, frJ is op10_31=0x4699 & frD & frJ {\n\tlocal val:8 = trunc(frJ);\n\tfrD = val(0);\n}\n\n\n#la-fp-s.txt ftintrz.w.s mask=0x011a8400\t\n#0x011a8400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrz.w.s frD, frJ is op10_31=0x46a1 & frD & frJ {\n\tfrD = trunc(frJ);\n}\n\n#la-fp-s.txt ftintrz.l.s mask=0x011aa400\t\n#0x011aa400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrz.l.s frD, frJ is op10_31=0x46a9 & frD & frJ {\n\tlocal val:8 = trunc(frJ);\n\tfrD = val(0);\n}\n\n\n#la-fp-s.txt ftintrne.w.s mask=0x011ac400\t\n#0x011ac400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrne.w.s frD, frJ is op10_31=0x46b1 & frD & frJ {\n\tfrD = round_even(frJ);\n}\n\n#la-fp-s.txt ftintrne.l.s mask=0x011ae400\t\n#0x011ae400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftintrne.l.s frD, frJ is op10_31=0x46b9 & frD & frJ {\n\tlocal val:8 = round_even(frJ);\n\tfrD = val(0);\n}\n\n\n#la-fp-s.txt ftint.w.s mask=0x011b0400\t\n#0x011b0400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftint.w.s frD, frJ is op10_31=0x46c1 & frD & frJ {\n\tfrD = trunc(frJ);\n}\n\n#la-fp-s.txt ftint.l.s mask=0x011b2400\t\n#0x011b2400\t0xfffffc00\tf0:5, f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ftint.l.s frD, frJ is op10_31=0x46c9 & frD & frJ {\n\tlocal val:8 = trunc(frJ);\n\tfrD = val(0);\n}\n\n\n#la-fp-s.txt ffint.s.w mask=0x011d1000\t\n#0x011d1000\t0xfffffc00\tf0:5,f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ffint.s.w frD,frJ is op10_31=0x4744 & frD & frJ {\n\tfrD =int2float(frJ);\n}\n\n\n#la-fp-s.txt ffint.s.l mask=0x011d1800\t\n#0x011d1800\t0xfffffc00\tf0:5,f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:ffint.s.l frD, drD is op10_31=0x4746 & frD & drD {\n\tfrD = int2float(drD);\n}\n\n\n#la-fp-s.txt frint.s mask=0x011e4400\t\n#0x011e4400\t0xfffffc00\tf0:5,f5:5\t['freg0_5_s0', 'freg5_5_s0']\n:frint.s frD,frJ is op10_31=0x4791 & frD & frJ {\n\tlocal val:4 = trunc(frJ);\n\tfrD = int2float(val);\n}\n\n\n#la-fp-s.txt fld.s mask=0x2b000000\t\n#0x2b000000\t0xffc00000\tf0:5,r5:5,so10:12\t['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:fld.s frD, ldst_addr is op22_31=0xac & frD & ldst_addr {\n\tfrD = *[ram]:4 ldst_addr;\n}\n\n\n#la-fp-s.txt fst.s mask=0x2b400000\t\n#0x2b400000\t0xffc00000\tf0:5,r5:5,so10:12\t['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:fst.s frD, ldst_addr is op22_31=0xad & frD & ldst_addr {\n\t*[ram]:4 ldst_addr = frD:4;\n}\n\n\n#la-fp-s.txt fldx.s mask=0x38300000\t\n#0x38300000\t0xffff8000\tf0:5,r5:5,r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fldx.s frD, ldstx_addr is op15_31=0x7060 & frD & ldstx_addr {\n\tfrD = *[ram]:4 ldstx_addr;\n}\n\n#la-fp-s.txt fstx.s mask=0x38380000\t\n#0x38380000\t0xffff8000\tf0:5,r5:5,r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fstx.s frD, ldstx_addr is op15_31=0x7070 & frD & ldstx_addr {\n\t*[ram]:4 ldstx_addr = frD;\n}\n\nSNaN: \"c\" is ccf_s = 0 { }\nSNaN: \"s\" is ccf_s = 1 { }\n\nfcond: SNaN^\"af\" is ccf=0x0 & SNaN { FCMPR = 0; }\nfcond: SNaN^\"lt\" is ccf=0x1 & SNaN { FCMPR = FCMP1 f< FCMP2; }\nfcond: SNaN^\"eq\" is ccf=0x2 & SNaN { FCMPR = FCMP1 f== FCMP2; }\nfcond: SNaN^\"le\" is ccf=0x3 & SNaN { FCMPR = FCMP1 f<= FCMP2; }\nfcond: SNaN^\"un\" is ccf=0x4 & SNaN { FCMPR = nan(FCMP1) || nan(FCMP2); }\nfcond: SNaN^\"ult\" is ccf=0x5 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f< FCMP2); }\nfcond: SNaN^\"ueq\" is ccf=0x6 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f== FCMP2); }\nfcond: SNaN^\"ule\" is ccf=0x7 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f<= FCMP2); }\nfcond: SNaN^\"ne\" is ccf=0x8 & SNaN { FCMPR = FCMP1 f!= FCMP2; }\nfcond: SNaN^\"or\" is ccf=0xa & SNaN { FCMPR = !(nan(FCMP1) || nan(FCMP2)); }\nfcond: SNaN^\"une\" is ccf=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f!= FCMP2); }\n\n#la-fp-s.txt fcmp.caf.s mask=0x0c100000\t\n#0x0c100000\t0xffff8018\tc0:3, f5:5, f10:5\t['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0']\n:fcmp.^fcond^\".s\" fccD, frJ, frK is op20_31=0xc1 & fcond & op3_4 = 0 & fccD & frJ & frK {\n\tFCMP1 = frJ;\n\tFCMP2 = frK;\n\tbuild fcond;\n\tfccD = FCMPR;\n}\n\n\n#la-bound-fp-s.txt fldgt.s mask=0x38740000\t\n#0x38740000\t0xffff8000\tf0:5, r5:5, r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fldgt.s frD, RJsrc, RKsrc is op15_31=0x70e8 & frD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tfrD = sext(*[ram]:4 vaddr);\n}\n\n\n#la-bound-fp-s.txt fldle.s mask=0x38750000\t\n#0x38750000\t0xffff8000\tf0:5, r5:5, r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fldle.s frD, RJsrc, RKsrc is op15_31=0x70ea & frD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\tfrD = sext(*[ram]:4 vaddr);\n}\n\n\n#la-bound-fp-s.txt fstgt.s mask=0x38760000\t\n#0x38760000\t0xffff8000\tf0:5, r5:5, r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fstgt.s frD, RJsrc, RKsrc is op15_31=0x70ec & frD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr > RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:4 vaddr = frD;\n}\n\n\n#la-bound-fp-s.txt fstle.s mask=0x38770000\t\n#0x38770000\t0xffff8000\tf0:5, r5:5, r10:5\t['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:fstle.s frD, RJsrc, RKsrc is op15_31=0x70ee & frD & RJsrc & RKsrc {\n\tlocal vaddr = RJsrc;\n\tif (vaddr <= RKsrc) goto ;\n\tbound_check_exception(RJsrc, RKsrc);\n\tgoto inst_next;\n\t\n\t*[ram]:4 vaddr = frD;\n}\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/loongarch_main.sinc", "content": "\ndefine endian=little;\n\ndefine alignment=4;\n\ndefine space ram type=ram_space size=$(REGSIZE) default;\ndefine space iocsr type=ram_space size=$(REGSIZE);\ndefine space register type=register_space size=4;\n\ndefine register offset=0x0 size=$(REGSIZE) [\n\tpc scr0 scr1 scr2 scr3\n];\n\ndefine register offset=0x40 size=1 [\n\tfcc0 fcc1 fcc2 fcc3 fcc4 fcc5 fcc6 fcc7\n];\n\ndefine register offset=0x48 size=4 [\n\tfcsr\n];\n\n# ABI names:\n# \"$zero\", \"$ra\", \"$tp\", \"$sp\", \"$a0\", \"$a1\", \"$a2\", \"$a3\",\n# \"$a4\", \"$a5\", \"$a6\", \"$a7\", \"$t0\", \"$t1\", \"$t2\", \"$t3\",\n# \"$t4\", \"$t5\", \"$t6\", \"$t7\", \"$t8\", \"$x\", \"$fp\", \"$s0\",\n# \"$s1\", \"$s2\", \"$s3\", \"$s4\", \"$s5\", \"$s6\", \"$s7\", \"$s8\",\n\n# GPR General Purpose Registers\ndefine register offset=0x100 size=$(REGSIZE) [\n\tzero ra tp sp a0 a1 a2 a3\n\ta4 a5 a6 a7 t0 t1 t2 t3\n\tt4 t5 t6 t7 t8 r21 fp s0\n\ts1 s2 s3 s4 s5 s6 s7 s8\n];\n\n@ifdef LA64\n\ndefine register offset=0x100 size=4 [\n\tr0_lo r0_hi ra_lo ra_hi tp_lo tp_hi sp_lo sp_hi\n\ta0_lo a0_hi a1_lo a1_hi a2_lo a2_hi a3_lo a3_hi\n\ta4_lo a4_hi a5_lo a5_hi a6_lo a6_hi a7_lo a7_hi\n\tt0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi\n\tt4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi\n\tt8_lo t8_hi r21_lo r21_hi fp_lo fp_hi s0_lo s0_hi\n\ts1_lo s1_hi s2_lo s2_hi s3_lo s3_hi s4_lo s4_hi\n\ts5_lo s5_hi s6_lo s6_hi s7_lo s7_hi s8_lo s8_hi\n];\n\n@endif\n\n# Floating Point registers (either 32- or 64-bit)\n@if FREGSIZE == \"4\"\ndefine register offset=0x1000 size=4 [\n\tfa0 _ _ _ _ _ _ _ fa1 _ _ _ _ _ _ _\n\tfa2 _ _ _ _ _ _ _ fa3 _ _ _ _ _ _ _\n\tfa4 _ _ _ _ _ _ _ fa5 _ _ _ _ _ _ _\n\tfa6 _ _ _ _ _ _ _ fa7 _ _ _ _ _ _ _\n\tft0 _ _ _ _ _ _ _ ft1 _ _ _ _ _ _ _\n\tft2 _ _ _ _ _ _ _ ft3 _ _ _ _ _ _ _\n\tft4 _ _ _ _ _ _ _ ft5 _ _ _ _ _ _ _\n\tft6 _ _ _ _ _ _ _ ft7 _ _ _ _ _ _ _\n\tft8 _ _ _ _ _ _ _ ft9 _ _ _ _ _ _ _\n\tft10 _ _ _ _ _ _ _ ft11 _ _ _ _ _ _ _\n\tft12 _ _ _ _ _ _ _ ft13 _ _ _ _ _ _ _\n\tft14 _ _ _ _ _ _ _ ft15 _ _ _ _ _ _ _\n\tfs0 _ _ _ _ _ _ _ fs1 _ _ _ _ _ _ _\n\tfs2 _ _ _ _ _ _ _ fs3 _ _ _ _ _ _ _\n\tfs4 _ _ _ _ _ _ _ fs5 _ _ _ _ _ _ _\n\tfs6 _ _ _ _ _ _ _ fs7 _ _ _ _ _ _ _\n];\n\ndefine register offset=0x1000 size=8 [\n\tfa0_1 _ _ _ fa2_3 _ _ _\n\tfa4_5 _ _ _ fa6_7 _ _ _\n\tft8_9 _ _ _ ft10_11 _ _ _\n\tft12_13 _ _ _ ft14_15 _ _ _\n\tft16_17 _ _ _ ft18_19 _ _ _\n\tft20_21 _ _ _ ft22_23 _ _ _\n\tfs24_25 _ _ _ fs26_27 _ _ _\n\tfs28_29 _ _ _ fs30_31 _ _ _\n];\n\n@else\n\ndefine register offset=0x1000 size=4 [\n\tfa0_lo _ _ _ _ _ _ _ fa1_lo _ _ _ _ _ _ _\n\tfa2_lo _ _ _ _ _ _ _ fa3_lo _ _ _ _ _ _ _\n\tfa4_lo _ _ _ _ _ _ _ fa5_lo _ _ _ _ _ _ _\n\tfa6_lo _ _ _ _ _ _ _ fa7_lo _ _ _ _ _ _ _\n\tft0_lo _ _ _ _ _ _ _ ft1_lo _ _ _ _ _ _ _\n\tft2_lo _ _ _ _ _ _ _ ft3_lo _ _ _ _ _ _ _\n\tft4_lo _ _ _ _ _ _ _ ft5_lo _ _ _ _ _ _ _\n\tft6_lo _ _ _ _ _ _ _ ft7_lo _ _ _ _ _ _ _\n\tft8_lo _ _ _ _ _ _ _ ft9_lo _ _ _ _ _ _ _\n\tft10_lo _ _ _ _ _ _ _ ft11_lo _ _ _ _ _ _ _\n\tft12_lo _ _ _ _ _ _ _ ft13_lo _ _ _ _ _ _ _\n\tft14_lo _ _ _ _ _ _ _ ft15_lo _ _ _ _ _ _ _\n\tfs0_lo _ _ _ _ _ _ _ fs1_lo _ _ _ _ _ _ _\n\tfs2_lo _ _ _ _ _ _ _ fs3_lo _ _ _ _ _ _ _\n\tfs4_lo _ _ _ _ _ _ _ fs5_lo _ _ _ _ _ _ _\n\tfs6_lo _ _ _ _ _ _ _ fs7_lo _ _ _ _ _ _ _\n];\n\ndefine register offset=0x1000 size=8 [\n\tfa0 _ _ _ fa1 _ _ _ fa2 _ _ _ fa3 _ _ _\n\tfa4 _ _ _ fa5 _ _ _ fa6 _ _ _ fa7 _ _ _\n\tft0 _ _ _ ft1 _ _ _ ft2 _ _ _ ft3 _ _ _\n\tft4 _ _ _ ft5 _ _ _ ft6 _ _ _ ft7 _ _ _\n\tft8 _ _ _ ft9 _ _ _ ft10 _ _ _ ft11 _ _ _\n\tft12 _ _ _ ft13 _ _ _ ft14 _ _ _ ft15 _ _ _\n\tfs0 _ _ _ fs1 _ _ _ fs2 _ _ _ fs3 _ _ _\n\tfs4 _ _ _ fs5 _ _ _ fs6 _ _ _ fs7 _ _ _\n];\n\n@endif #FREGSIZE == 32\n\n# SIMD eXtension 256-bit registers (lsx)\n# overlaps the floating point registers above\ndefine register offset=0x1000 size=16 [\n\tv0 _ v1 _ v2 _ v3 _ v4 _ v5 _ v6 _ v7 _\n\tv8 _ v9 _ v10 _ v11 _ v12 _ v13 _ v14 _ v15 _\n\tv16 _ v17 _ v18 _ v19 _ v20 _ v21 _ v22 _ v23 _\n\tv24 _ v25 _ v26 _ v27 _ v28 _ v29 _ v30 _ v31 _\n];\n\n# AdVanced SIMD eXtension 256-bit registers (lasx)\n# overlaps the floating point registers above\ndefine register offset=0x1000 size=32 [\n\tx0 x1 x2 x3 x4 x5 x6 x7\n\tx8 x9 x10 x11 x12 x13 x14 x15\n\tx16 x17 x18 x19 x20 x21 x22 x23\n\tx24 x25 x26 x27 x28 x29 x30 x31\n];\n\n@define CSR_OFFSET \"0x2000\" #used for the csr instructions csrxchg/cssrd/cssrw\ndefine register offset=$(CSR_OFFSET) size=$(REGSIZE) [\n\tcrmd prmd euen misc ecfg estat era badv\n\tbadi csr9 csr10 csr11 eentry csr13 csr14 csr15\n\ttlbidx tlbehi tlbelo0 tlbelo1 csr20 csr21 csr22 csr23\n\tasid pgdl pgdh pgd pwcl pwch stlbps rvacfg\n\tcpuid prcfg1 prcfg2 prcfg3 csr36 csr37 csr38 csr39\n\tcsr40 csr41 csr42 csr43 csr44 csr45 csr46 csr47\n\tsave0 save1 save2 save3 save4 save5 save6 save7\n\tsave8 save9 save10 save11 save12 save13 save14 save15\n\ttid tcfg tval cntc ticlr csr69 csr70 csr71\n\tcsr72 csr73 csr74 csr75 csr76 csr77\t csr78 csr79\n\tcsr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87\n\tcsr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95\n\tllbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103\n\tcsr104 csr105 csr106 csr107 csr108 csr109 csr110 csr111\n\tcsr112 csr113 csr114 csr115 csr116 csr117 csr118 csr119\n\tcsr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127\n\timpctl1 impctl2 csr130 csr131 csr132 csr133 csr134 csr135\n\ttlbrentry tlbrbadv tlbrera tlbrsave tlbrelo0 tlbrelo1 tlbrehi tlbrprmd\n\tmerrctl merrinfo1 merrinfo2 merrentry merrera merrsave csr150 csr151\n\tctag csr153 csr154 csr155 csr156 csr157 csr158 csr159\n\tcsr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167\n\tcsr168 csr169 csr170 csr171 csr172 csr173 csr174 csr175\n\tcsr176 csr177 csr178 csr179 csr180 csr181 csr182 csr183\n\tcsr184 csr185 csr186 csr187 csr188 csr189 csr190 csr191\n\tcsr192 csr193 csr194 csr195 csr196 csr197 csr198 csr199\n\tcsr200 csr201 csr202 csr203 csr204 csr205 csr206 csr207\n\tcsr208 csr209 csr210 csr211 csr212 csr213 csr214 csr215\n\tcsr216 csr217 csr218 csr219 csr220 csr221 csr222 csr223\n\tcsr224 csr225 csr226 csr227 csr228 csr229 csr230 csr231\n\tcsr232 csr233 csr234 csr235 csr236 csr237 csr238 csr239\n\tcsr240 csr241 csr242 csr243 csr244 csr245 csr246 csr247\n\tcsr248 csr249 csr250 csr251 csr252 csr253 csr254 csr255\n\tcsr256 csr257 csr258 csr259 csr260 csr261 csr262 csr263\n];\n\n# Dummy registers for floating point comparison\ndefine register offset=0x5000 size=4 [\n\tFCMP1 FCMP2\n];\n\ndefine register offset=0x5008 size=1 [\n\tFCMPR\n];\n\ndefine register offset=0x5100 size=8 [\n\tDCMP1 DCMP2\n];\n\ndefine register offset=0x5110 size=1 [\n\tDCMPR\n];\n\ndefine register offset=0x50 size=4 contextreg;\n\ndefine context contextreg\n\tphase = (0,1) ;\n\ndefine token instr(32)\n\tinstword = ( 0,31)\n\top26_31 = (26,31)\n\top25_31 = (25,31)\n\top24_31 = (24,31)\n\top23_31 = (23,31)\n\top22_31 = (22,31)\n\top21_31 = (21,31)\n\top20_31 = (20,31)\n\top19_31 = (19,31)\n\top18_31 = (18,31)\n\top18_19 = (18,19)\n\top17_31 = (17,31)\n\top16_31 = (16,31)\n\top15_31 = (15,31)\n\top15_15 = (15,15)\n\top14_31 = (14,31)\n\top13_31 = (13,31)\n\top12_31 = (12,31)\n\top11_31 = (11,31)\n\top10_31 = (10,31)\n\top8_31 = ( 8,31)\n\top8_9 = ( 8, 9)\n\top7_31 = ( 7,31)\n\top5_9 = ( 5, 9)\n\top5_31 = ( 5,31)\n\top4_4 = ( 4, 4)\n\top3_4 = ( 3, 4)\n\top2_4 = ( 2, 4)\n\top0_2 = ( 0, 2)\n\top0_4 = ( 0, 4)\n\top0_31 = ( 0,31)\n\n\tccf = (16,19)\n\tccf_s = (15,15)\n\n\tsimm5_20 = ( 5,24) signed\n\tsimm5_13 = ( 5,17) signed\n\tsimm10_9 = (10,18) signed\n\tsimm10_8 = (10,17) signed\n\tsimm10_5 = (10,14) signed\n\tsimm10_14 = (10,23) signed\n\tsimm10_16 = (10,25) signed\n\tsimm10_12 = (10,21) signed\n\tsimm10_11 = (10,20) signed\n\tsimm10_10 = (10,19) signed\n\tsimm0_5 = ( 0, 4) signed\n\tsimm0_10 = ( 0, 9) signed\n\n\trK = (10,14)\n\trK32 = (10,14)\n\n\trJ = ( 5, 9)\n\trJ32 = ( 5, 9)\n\n\trD = ( 0, 4)\n\trD32 = ( 0, 4)\n\n\txrK = (10,14)\n\txrJ = ( 5, 9)\n\txrD = ( 0, 4)\n\txrA = (15,19)\n\n\tvrK = (10,14)\n\tvrJ = ( 5, 9)\n\tvrD = ( 0, 4)\n\tvrA = (15,19)\n\n\tlbtrJ = ( 5, 6)\n\tlbtrD = ( 0, 1)\n\n\tfrK = (10,14)\n\tfrJ = ( 5, 9)\n\tfrD = ( 0, 4)\n\tfrA = (15,19)\n\n\tdrK = (10,14)\n\tdrJ = ( 5, 9)\n\tdrD = ( 0, 4)\n\tdrA = (15,19)\n\n\tfccJ = ( 5, 7)\n\tfccD = ( 0, 2)\n\tfccA = (15,17)\n\n\timm5_5 = ( 5, 9)\n\timm5_3 = ( 5, 7)\n\timm18_5 = (18,22)\n\timm18_4 = (18,21)\n\timm18_3 = (18,20)\n\timm18_2 = (18,19)\n\timm18_1 = (18,18)\n\timm16_6 = (16,21)\n\timm16_5 = (16,20)\n\timm15_3 = (15,17)\n\timm15_2 = (15,16)\n\timm10_8 = (10,17)\n\timm10_7 = (10,16)\n\timm10_6 = (10,15)\n\timm10_5 = (10,14)\n\timm10_4 = (10,13)\n\timm10_3 = (10,12)\n\timm10_2 = (10,11)\n\timm10_16 = (10,25)\n\timm10_14 = (10,23)\n\timm10_12 = (10,21)\n\timm10_1 = (10,10)\n\timm0_5 = ( 0, 4)\n\timm0_4 = ( 0, 3)\n\timm0_15 = ( 0,14)\n;\n\nattach variables [ rD rJ rK ] [\n\tzero\tra\ttp\tsp\ta0\ta1\ta2\ta3\n\ta4\ta5\ta6\ta7\tt0\tt1\tt2\tt3\n\tt4\tt5\tt6\tt7\tt8\tr21\tfp\ts0\n\ts1\ts2\ts3\ts4\ts5\ts6\ts7\ts8\n];\n\n@ifdef LA64\nattach variables [ rD32 rJ32 rK32 ] [\n\tr0_lo\tra_lo\ttp_lo\tsp_lo\n\ta0_lo\ta1_lo\ta2_lo\ta3_lo\n\ta4_lo\ta5_lo\ta6_lo\ta7_lo\n\tt0_lo\tt1_lo\tt2_lo\tt3_lo\n\tt4_lo\tt5_lo\tt6_lo\tt7_lo\n\tt8_lo\tr21_lo\tfp_lo\ts0_lo\n\ts1_lo\ts2_lo\ts3_lo\ts4_lo\n\ts5_lo\ts6_lo\ts7_lo\ts8_lo\n];\n\n@else\n# For LA32 these are the same as rD, rJ, rK\nattach variables [ rD32 rJ32 rK32 ] [\n\tzero\tra\ttp\tsp\ta0\ta1\ta2\ta3\n\ta4\ta5\ta6\ta7\tt0\tt1\tt2\tt3\n\tt4\tt5\tt6\tt7\tt8\tr21\tfp\ts0\n\ts1\ts2\ts3\ts4\ts5\ts6\ts7\ts8\n];\n\n@endif\n\n\n@if FREGSIZE == \"8\"\n# For 64-bit floating point single instruction operands use only the low part\nattach variables [ frD frJ frK ] [\n\tfa0_lo\tfa1_lo\tfa2_lo\tfa3_lo\tfa4_lo\tfa5_lo\tfa6_lo\tfa7_lo\n\tft0_lo\tft1_lo\tft2_lo\tft3_lo\tft4_lo\tft5_lo\tft6_lo\tft7_lo\n\tft8_lo\tft9_lo\tft10_lo\tft11_lo\tft12_lo\tft13_lo\tft14_lo\tft15_lo\n\tfs0_lo\tfs1_lo\tfs2_lo\tfs3_lo\tfs4_lo\tfs5_lo\tfs6_lo\tfs7_lo\n];\n\nattach variables [ drD drJ drK ] [\n\tfa0\t\tfa1\t\tfa2\t\tfa3\t\tfa4\t\tfa5\t\tfa6\t\tfa7\t\n\tft0\t\tft1\t\tft2\t\tft3\t\tft4\t\tft5\t\tft6\t\tft7\t\n\tft8\t\tft9\t\tft10\tft11\tft12\tft13\tft14\tft15\n\tfs0\t\tfs1\t\tfs2\t\tfs3\t\tfs4\t\tfs5\t\tfs6\t\tfs7\t\n];\n\n@else\n\nattach variables [ frD frJ frK ] [\n\tfa0\t\tfa1\t\tfa2\t\tfa3\t\tfa4\t\tfa5\t\tfa6\t\tfa7\t\n\tft0\t\tft1\t\tft2\t\tft3\t\tft4\t\tft5\t\tft6\t\tft7\t\n\tft8\t\tft9\t\tft10\tft11\tft12\tft13\tft14\tft15\n\tfs0\t\tfs1\t\tfs2\t\tfs3\t\tfs4\t\tfs5\t\tfs6\t\tfs7\t\n];\n\n# For 64-bit floating point Double instruction operands need to bond two 32-bit FPRs\nattach variables [ drD drJ drK ] [\n\tfa0_1\t_\tfa2_3\t_\tfa4_5\t_\tfa6_7\t_\n\tft8_9\t_\tft10_11\t_\tft12_13\t_\tft14_15\t_\n\tft16_17\t_\tft18_19\t_\tft20_21\t_\tft22_23\t_\n\tfs24_25\t_\tfs26_27\t_\tfs28_29\t_\tfs30_31\t_\n];\n\n@endif\n\n\nattach variables [vrD vrJ vrK vrA] [\n\tv0\tv1\tv2\tv3\tv4\tv5\tv6\tv7 \n\tv8\tv9\tv10\tv11\tv12\tv13\tv14\tv15 \n\tv16\tv17\tv18\tv19\tv20\tv21\tv22\tv23 \n\tv24\tv25\tv26\tv27\tv28\tv29\tv30\tv31 \n];\n\n\nattach variables [xrD xrJ xrK xrA] [\n\tx0\tx1\tx2\tx3\tx4\tx5\tx6\tx7\n\tx8\tx9\tx10\tx11\tx12\tx13\tx14\tx15\n\tx16\tx17\tx18\tx19\tx20\tx21\tx22\tx23\n\tx24\tx25\tx26\tx27\tx28\tx29\tx30\tx31\n];\n\n\nattach variables [ fccD fccJ fccA] [\n\tfcc0 fcc1 fcc2 fcc3 fcc4 fcc5 fcc6 fcc7\n];\n\n# Register subconstructors\nRD: rD is rD { export rD; }\n\nRDsrc: rD is rD { export rD; }\nRDsrc: rD is rD & rD=0 { export 0:$(REGSIZE); }\n\nRJ: rJ is rJ { export rJ; }\n\nRJsrc: rJ is rJ { export rJ; }\nRJsrc: rJ is rJ & rJ=0 { export 0:$(REGSIZE); }\n\nRK: rK is rK { export rK; }\n\nRKsrc: rK is rK { export rK; }\nRKsrc: rK is rK & rK=0 { export 0:$(REGSIZE); }\n\nRD32: rD is rD & rD32 { export rD32; }\n\nRD32src: rD is rD & rD32 { export rD32; }\nRD32src: rD is rD & rD32=0 { export 0:4; }\n\nRJ32: rJ is rJ & rJ32 { export rJ32; }\n\nRJ32src: rJ is rJ & rJ32 { export rJ32; }\nRJ32src: rJ is rJ & rJ32=0 { export 0:4; }\n\nRK32: rK is rK & rK32 { export rK32; }\n\nRK32src: rK is rK & rK32 { export rK32; }\nRK32src: rK is rK & rK32=0 { export 0:4; }\n\n@if FREGSIZE == \"8\"\n\nFRD: drD is drD { export drD; }\n\nFRJ: drJ is drJ { export drJ; }\n\nFRK: drK is drK { export drK; }\n\n@else\n\nFRD: frD is frD { export frD; }\n\nFRJ: frJ is frJ { export frJ; }\n\nFRK: frK is frK { export frK; }\n\n@endif\n\n# Immediate operand sub-constructors\naddu16_imm: val is simm10_16 [val = simm10_16 << 16;] { export *[const]:$(REGSIZE) val; }\n\nalsl_shift: sa2 is imm15_2 [sa2 = imm15_2 + 1;] { export *[const]:1 sa2; }\n\nldst_addr: RJsrc(simm10_12) is RJsrc & simm10_12 { local vaddr:$(REGSIZE) = RJsrc + simm10_12; export vaddr; }\n\nldstptr_addr: RJsrc(voffs) is RJsrc & simm10_14 [voffs = (simm10_14 << 2);] { local vaddr:$(REGSIZE) = RJsrc + voffs; export vaddr; }\n\nldstx_addr: RJsrc(RKsrc) is RJsrc & RKsrc { local vaddr:$(REGSIZE) = RJsrc + RKsrc; export vaddr; }\n\npcadd2: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 2);] { export *[const]:$(REGSIZE) reloffs; }\npcadd12: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; }\n\npcala12: reloffs is simm5_20 [reloffs = (inst_start & ~0xfff) + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; }\n\npcadd18: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 18);] { export *[const]:$(REGSIZE) reloffs; }\n\nRel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; }\nRel21: reloc is imm10_16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; }\nRel26: reloc is imm10_16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; }\n\nRelJ16: RJsrc, simm10_16 is RJsrc & simm10_16 { local tmp:$(ADDRSIZE) = RJsrc + (simm10_16 << 2); export tmp; }\n\nsimm12i: immed is simm5_20 [immed = simm5_20 << 12; ] { export *[const]:$(REGSIZE) immed; }\n\nsimm32i: immed is simm5_20 [immed = simm5_20 << 32; ] { export *[const]:$(REGSIZE) immed; }\n\nsimm52i: immed is simm10_12 [immed = simm10_12 << 52; ] { export *[const]:$(REGSIZE) immed; }\n\n# general pcodeops\ndefine pcodeop break;\ndefine pcodeop cpucfg;\n\ndefine pcodeop addr_bound_exception;\ndefine pcodeop bound_check_exception;\n\ndefine pcodeop crc_ieee802.3;\ndefine pcodeop crc_castagnoli;\n\ndefine pcodeop dbcl;\n\ndefine pcodeop dbar;\ndefine pcodeop ibar;\n\ndefine pcodeop iocsrrd;\ndefine pcodeop iocsrwr;\n\ndefine pcodeop preld_loadl1cache;\ndefine pcodeop preld_storel1cache;\ndefine pcodeop preld_nop;\n\ndefine pcodeop preldx_loadl1cache;\ndefine pcodeop preldx_storel1cache;\ndefine pcodeop preldx_nop;\n\n# param: 0 = low word, 1 = high word, 2 = both (for rdtime.d)\ndefine pcodeop rdtime.counter;\ndefine pcodeop rdtime.counterid;\ndefine pcodeop syscall;\n\ndefine pcodeop f_scaleb;\ndefine pcodeop f_logb;\ndefine pcodeop f_class;\ndefine pcodeop round_even;\n\n#\n# MACROS\n#\nmacro bitrev32(input, output) {\n\tlocal v = input;\n\tv = ((v & 0xffff0000) >> 16) | ((v & 0x0000ffff) << 16);\n\tv = ((v & 0xff00ff00) >> 8) | ((v & 0x00ff00ff) << 8);\n\tv = ((v & 0xf0f0f0f0) >> 4) | ((v & 0x0f0f0f0f) << 4);\n\tv = ((v & 0xcccccccc) >> 2) | ((v & 0x33333333) << 2);\n\tv = ((v & 0xaaaaaaaa) >> 1) | ((v & 0x55555555) << 1);\n\toutput = v;\n}\n\nmacro bitrev64(input, output) {\n\tlocal v = input;\n\tv = ((v & 0xffffffff00000000) >> 32) | ((v & 0x00000000ffffffff) << 32);\n\tv = ((v & 0xffff0000ffff0000) >> 16) | ((v & 0x0000ffff0000ffff) << 16);\n\tv = ((v & 0xff00ff00ff00ff00) >> 8) | ((v & 0x00ff00ff00ff00ff) << 8);\n\tv = ((v & 0xf0f0f0f0f0f0f0f0) >> 4) | ((v & 0x0f0f0f0f0f0f0f0f) << 4);\n\tv = ((v & 0xcccccccccccccccc) >> 2) | ((v & 0x3333333333333333) << 2);\n\tv = ((v & 0xaaaaaaaaaaaaaaaa) >> 1) | ((v & 0x5555555555555555) << 1);\n\toutput = v;\n}\n\nmacro byterev(input, output) {\n\tlocal v = input;\n\tv = ((v & 0xf0) >> 4) | ((v & 0x0f) << 4);\n\tv = ((v & 0xcc) >> 2) | ((v & 0x33) << 2);\n\tv = ((v & 0xaa) >> 1) | ((v & 0x55) << 1);\n\toutput = v;\n}\n\nmacro byterev32(input, output) {\n\tlocal v = input;\n\tv = ((v & 0xf0f0f0f0) >> 4) | ((v & 0x0f0f0f0f) << 4);\n\tv = ((v & 0xcccccccc) >> 2) | ((v & 0x33333333) << 2);\n\tv = ((v & 0xaaaaaaaa) >> 1) | ((v & 0x55555555) << 1);\n\toutput = v;\n}\n\nmacro byterev64(input, output) {\n\tlocal v = input;\n\tv = ((v & 0xf0f0f0f0f0f0f0f0) >> 4) | ((v & 0x0f0f0f0f0f0f0f0f) << 4);\n\tv = ((v & 0xcccccccccccccccc) >> 2) | ((v & 0x3333333333333333) << 2);\n\tv = ((v & 0xaaaaaaaaaaaaaaaa) >> 1) | ((v & 0x5555555555555555) << 1);\n\toutput = v;\n}\n\nmacro tzcount32(input, count) {\n\tcount = 32;\n\tlocal v = input & (-input);\n\tcount = count - zext(v != 0);\n\tcount = count - 16 * zext((v & 0x0000ffff) != 0);\n\tcount = count - 8 * zext((v & 0x00ff00ff) != 0);\n\tcount = count - 4 * zext((v & 0x0f0f0f0f) != 0);\n\tcount = count - 2 * zext((v & 0x33333333) != 0);\n\tcount = count - 1 * zext((v & 0x55555555) != 0);\n}\n\nmacro tzcount64(input, count) {\n\tcount = 64;\n\tlocal v:8 = input & (-input);\n\tcount = count - 1 * zext(v != 0);\n\tcount = count - 32 * zext((v & 0x00000000ffffffff) != 0);\n\tcount = count - 16 * zext((v & 0x0000ffff0000ffff) != 0);\n\tcount = count - 8 * zext((v & 0x00ff00ff00ff00ff) != 0);\n\tcount = count - 4 * zext((v & 0x0f0f0f0f0f0f0f0f) != 0);\n\tcount = count - 2 * zext((v & 0x3333333333333333) != 0);\n\tcount = count - 1 * zext((v & 0x5555555555555555) != 0);\n}\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/lp64d.cspec", "content": "\n\n \n \t\n\t\n\t\n\t\n \n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/lp64f.cspec", "content": "\n\n \n \t\n\t\n\t\n\t\n \n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/lsx.sinc", "content": "define pcodeop vfmadd.s;\n\n#lsx.txt vfmadd.s mask=0x09100000\t\n#0x09100000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfmadd.s vrD, vrJ, vrK, vrA is op20_31=0x91 & vrD & vrJ & vrK & vrA {\n\tvrD = vfmadd.s(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfmadd.d;\n\n#lsx.txt vfmadd.d mask=0x09200000\t\n#0x09200000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfmadd.d vrD, vrJ, vrK, vrA is op20_31=0x92 & vrD & vrJ & vrK & vrA {\n\tvrD = vfmadd.d(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfmsub.s;\n\n#lsx.txt vfmsub.s mask=0x09500000\t\n#0x09500000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfmsub.s vrD, vrJ, vrK, vrA is op20_31=0x95 & vrD & vrJ & vrK & vrA {\n\tvrD = vfmsub.s(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfmsub.d;\n\n#lsx.txt vfmsub.d mask=0x09600000\t\n#0x09600000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfmsub.d vrD, vrJ, vrK, vrA is op20_31=0x96 & vrD & vrJ & vrK & vrA {\n\tvrD = vfmsub.d(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfnmadd.s;\n\n#lsx.txt vfnmadd.s mask=0x09900000\t\n#0x09900000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfnmadd.s vrD, vrJ, vrK, vrA is op20_31=0x99 & vrD & vrJ & vrK & vrA {\n\tvrD = vfnmadd.s(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfnmadd.d;\n\n#lsx.txt vfnmadd.d mask=0x09a00000\t\n#0x09a00000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfnmadd.d vrD, vrJ, vrK, vrA is op20_31=0x9a & vrD & vrJ & vrK & vrA {\n\tvrD = vfnmadd.d(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfnmsub.s;\n\n#lsx.txt vfnmsub.s mask=0x09d00000\t\n#0x09d00000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfnmsub.s vrD, vrJ, vrK, vrA is op20_31=0x9d & vrD & vrJ & vrK & vrA {\n\tvrD = vfnmsub.s(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfnmsub.d;\n\n#lsx.txt vfnmsub.d mask=0x09e00000\t\n#0x09e00000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vfnmsub.d vrD, vrJ, vrK, vrA is op20_31=0x9e & vrD & vrJ & vrK & vrA {\n\tvrD = vfnmsub.d(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vfcmp.caf.s;\n\n#lsx.txt vfcmp.caf.s mask=0x0c500000\t\n#0x0c500000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.caf.s vrD, vrJ, vrK is op15_31=0x18a0 & vrD & vrJ & vrK {\n\tvrD = vfcmp.caf.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.saf.s;\n\n#lsx.txt vfcmp.saf.s mask=0x0c508000\t\n#0x0c508000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.saf.s vrD, vrJ, vrK is op15_31=0x18a1 & vrD & vrJ & vrK {\n\tvrD = vfcmp.saf.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.clt.s;\n\n#lsx.txt vfcmp.clt.s mask=0x0c510000\t\n#0x0c510000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.clt.s vrD, vrJ, vrK is op15_31=0x18a2 & vrD & vrJ & vrK {\n\tvrD = vfcmp.clt.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.slt.s;\n\n#lsx.txt vfcmp.slt.s mask=0x0c518000\t\n#0x0c518000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.slt.s vrD, vrJ, vrK is op15_31=0x18a3 & vrD & vrJ & vrK {\n\tvrD = vfcmp.slt.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.ceq.s;\n\n#lsx.txt vfcmp.ceq.s mask=0x0c520000\t\n#0x0c520000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.ceq.s vrD, vrJ, vrK is op15_31=0x18a4 & vrD & vrJ & vrK {\n\tvrD = vfcmp.ceq.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.seq.s;\n\n#lsx.txt vfcmp.seq.s mask=0x0c528000\t\n#0x0c528000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.seq.s vrD, vrJ, vrK is op15_31=0x18a5 & vrD & vrJ & vrK {\n\tvrD = vfcmp.seq.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cle.s;\n\n#lsx.txt vfcmp.cle.s mask=0x0c530000\t\n#0x0c530000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cle.s vrD, vrJ, vrK is op15_31=0x18a6 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cle.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sle.s;\n\n#lsx.txt vfcmp.sle.s mask=0x0c538000\t\n#0x0c538000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sle.s vrD, vrJ, vrK is op15_31=0x18a7 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sle.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cun.s;\n\n#lsx.txt vfcmp.cun.s mask=0x0c540000\t\n#0x0c540000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cun.s vrD, vrJ, vrK is op15_31=0x18a8 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cun.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sun.s;\n\n#lsx.txt vfcmp.sun.s mask=0x0c548000\t\n#0x0c548000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sun.s vrD, vrJ, vrK is op15_31=0x18a9 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sun.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cult.s;\n\n#lsx.txt vfcmp.cult.s mask=0x0c550000\t\n#0x0c550000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cult.s vrD, vrJ, vrK is op15_31=0x18aa & vrD & vrJ & vrK {\n\tvrD = vfcmp.cult.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sult.s;\n\n#lsx.txt vfcmp.sult.s mask=0x0c558000\t\n#0x0c558000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sult.s vrD, vrJ, vrK is op15_31=0x18ab & vrD & vrJ & vrK {\n\tvrD = vfcmp.sult.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cueq.s;\n\n#lsx.txt vfcmp.cueq.s mask=0x0c560000\t\n#0x0c560000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cueq.s vrD, vrJ, vrK is op15_31=0x18ac & vrD & vrJ & vrK {\n\tvrD = vfcmp.cueq.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sueq.s;\n\n#lsx.txt vfcmp.sueq.s mask=0x0c568000\t\n#0x0c568000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sueq.s vrD, vrJ, vrK is op15_31=0x18ad & vrD & vrJ & vrK {\n\tvrD = vfcmp.sueq.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cule.s;\n\n#lsx.txt vfcmp.cule.s mask=0x0c570000\t\n#0x0c570000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cule.s vrD, vrJ, vrK is op15_31=0x18ae & vrD & vrJ & vrK {\n\tvrD = vfcmp.cule.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sule.s;\n\n#lsx.txt vfcmp.sule.s mask=0x0c578000\t\n#0x0c578000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sule.s vrD, vrJ, vrK is op15_31=0x18af & vrD & vrJ & vrK {\n\tvrD = vfcmp.sule.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cne.s;\n\n#lsx.txt vfcmp.cne.s mask=0x0c580000\t\n#0x0c580000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cne.s vrD, vrJ, vrK is op15_31=0x18b0 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cne.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sne.s;\n\n#lsx.txt vfcmp.sne.s mask=0x0c588000\t\n#0x0c588000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sne.s vrD, vrJ, vrK is op15_31=0x18b1 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sne.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cor.s;\n\n#lsx.txt vfcmp.cor.s mask=0x0c5a0000\t\n#0x0c5a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cor.s vrD, vrJ, vrK is op15_31=0x18b4 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cor.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sor.s;\n\n#lsx.txt vfcmp.sor.s mask=0x0c5a8000\t\n#0x0c5a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sor.s vrD, vrJ, vrK is op15_31=0x18b5 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sor.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cune.s;\n\n#lsx.txt vfcmp.cune.s mask=0x0c5c0000\t\n#0x0c5c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cune.s vrD, vrJ, vrK is op15_31=0x18b8 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cune.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sune.s;\n\n#lsx.txt vfcmp.sune.s mask=0x0c5c8000\t\n#0x0c5c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sune.s vrD, vrJ, vrK is op15_31=0x18b9 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sune.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.caf.d;\n\n#lsx.txt vfcmp.caf.d mask=0x0c600000\t\n#0x0c600000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.caf.d vrD, vrJ, vrK is op15_31=0x18c0 & vrD & vrJ & vrK {\n\tvrD = vfcmp.caf.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.saf.d;\n\n#lsx.txt vfcmp.saf.d mask=0x0c608000\t\n#0x0c608000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.saf.d vrD, vrJ, vrK is op15_31=0x18c1 & vrD & vrJ & vrK {\n\tvrD = vfcmp.saf.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.clt.d;\n\n#lsx.txt vfcmp.clt.d mask=0x0c610000\t\n#0x0c610000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.clt.d vrD, vrJ, vrK is op15_31=0x18c2 & vrD & vrJ & vrK {\n\tvrD = vfcmp.clt.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.slt.d;\n\n#lsx.txt vfcmp.slt.d mask=0x0c618000\t\n#0x0c618000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.slt.d vrD, vrJ, vrK is op15_31=0x18c3 & vrD & vrJ & vrK {\n\tvrD = vfcmp.slt.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.ceq.d;\n\n#lsx.txt vfcmp.ceq.d mask=0x0c620000\t\n#0x0c620000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.ceq.d vrD, vrJ, vrK is op15_31=0x18c4 & vrD & vrJ & vrK {\n\tvrD = vfcmp.ceq.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.seq.d;\n\n#lsx.txt vfcmp.seq.d mask=0x0c628000\t\n#0x0c628000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.seq.d vrD, vrJ, vrK is op15_31=0x18c5 & vrD & vrJ & vrK {\n\tvrD = vfcmp.seq.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cle.d;\n\n#lsx.txt vfcmp.cle.d mask=0x0c630000\t\n#0x0c630000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cle.d vrD, vrJ, vrK is op15_31=0x18c6 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cle.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sle.d;\n\n#lsx.txt vfcmp.sle.d mask=0x0c638000\t\n#0x0c638000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sle.d vrD, vrJ, vrK is op15_31=0x18c7 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sle.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cun.d;\n\n#lsx.txt vfcmp.cun.d mask=0x0c640000\t\n#0x0c640000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cun.d vrD, vrJ, vrK is op15_31=0x18c8 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cun.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sun.d;\n\n#lsx.txt vfcmp.sun.d mask=0x0c648000\t\n#0x0c648000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sun.d vrD, vrJ, vrK is op15_31=0x18c9 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sun.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cult.d;\n\n#lsx.txt vfcmp.cult.d mask=0x0c650000\t\n#0x0c650000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cult.d vrD, vrJ, vrK is op15_31=0x18ca & vrD & vrJ & vrK {\n\tvrD = vfcmp.cult.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sult.d;\n\n#lsx.txt vfcmp.sult.d mask=0x0c658000\t\n#0x0c658000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sult.d vrD, vrJ, vrK is op15_31=0x18cb & vrD & vrJ & vrK {\n\tvrD = vfcmp.sult.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cueq.d;\n\n#lsx.txt vfcmp.cueq.d mask=0x0c660000\t\n#0x0c660000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cueq.d vrD, vrJ, vrK is op15_31=0x18cc & vrD & vrJ & vrK {\n\tvrD = vfcmp.cueq.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sueq.d;\n\n#lsx.txt vfcmp.sueq.d mask=0x0c668000\t\n#0x0c668000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sueq.d vrD, vrJ, vrK is op15_31=0x18cd & vrD & vrJ & vrK {\n\tvrD = vfcmp.sueq.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cule.d;\n\n#lsx.txt vfcmp.cule.d mask=0x0c670000\t\n#0x0c670000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cule.d vrD, vrJ, vrK is op15_31=0x18ce & vrD & vrJ & vrK {\n\tvrD = vfcmp.cule.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sule.d;\n\n#lsx.txt vfcmp.sule.d mask=0x0c678000\t\n#0x0c678000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sule.d vrD, vrJ, vrK is op15_31=0x18cf & vrD & vrJ & vrK {\n\tvrD = vfcmp.sule.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cne.d;\n\n#lsx.txt vfcmp.cne.d mask=0x0c680000\t\n#0x0c680000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cne.d vrD, vrJ, vrK is op15_31=0x18d0 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cne.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sne.d;\n\n#lsx.txt vfcmp.sne.d mask=0x0c688000\t\n#0x0c688000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sne.d vrD, vrJ, vrK is op15_31=0x18d1 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sne.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cor.d;\n\n#lsx.txt vfcmp.cor.d mask=0x0c6a0000\t\n#0x0c6a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cor.d vrD, vrJ, vrK is op15_31=0x18d4 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cor.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sor.d;\n\n#lsx.txt vfcmp.sor.d mask=0x0c6a8000\t\n#0x0c6a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sor.d vrD, vrJ, vrK is op15_31=0x18d5 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sor.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.cune.d;\n\n#lsx.txt vfcmp.cune.d mask=0x0c6c0000\t\n#0x0c6c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.cune.d vrD, vrJ, vrK is op15_31=0x18d8 & vrD & vrJ & vrK {\n\tvrD = vfcmp.cune.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcmp.sune.d;\n\n#lsx.txt vfcmp.sune.d mask=0x0c6c8000\t\n#0x0c6c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcmp.sune.d vrD, vrJ, vrK is op15_31=0x18d9 & vrD & vrJ & vrK {\n\tvrD = vfcmp.sune.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitsel.v;\n\n#lsx.txt vbitsel.v mask=0x0d100000\t\n#0x0d100000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vbitsel.v vrD, vrJ, vrK, vrA is op20_31=0xd1 & vrD & vrJ & vrK & vrA {\n\tvrD = vbitsel.v(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vshuf.b;\n\n#lsx.txt vshuf.b mask=0x0d500000\t\n#0x0d500000\t0xfff00000\tv0:5,v5:5,v10:5,v15:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0']\n:vshuf.b vrD, vrJ, vrK, vrA is op20_31=0xd5 & vrD & vrJ & vrK & vrA {\n\tvrD = vshuf.b(vrD, vrJ, vrK, vrA);\n}\n\ndefine pcodeop vld;\n\n#lsx.txt vld mask=0x2c000000\t\n#0x2c000000\t0xffc00000\tv0:5, r5:5, so10:12\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:vld vrD, RJsrc, simm10_12 is op22_31=0xb0 & vrD & RJsrc & simm10_12 {\n\tvrD = vld(vrD, RJsrc, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop vst;\n\n#lsx.txt vst mask=0x2c400000\t\n#0x2c400000\t0xffc00000\tv0:5, r5:5, so10:12\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:vst vrD, RJsrc, simm10_12 is op22_31=0xb1 & vrD & RJsrc & simm10_12 {\n\tvrD = vst(vrD, RJsrc, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop vldrepl.d;\n\n#lsx.txt vldrepl.d mask=0x30100000\t[@orig_fmt=VdJSk9ps3]\n#0x30100000\t0xfff80000\tv0:5, r5:5, so10:9<<3\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0']\n:vldrepl.d vrD, RJsrc, simm10_9 is op19_31=0x602 & vrD & RJsrc & simm10_9 {\n\tvrD = vldrepl.d(vrD, RJsrc, simm10_9:$(REGSIZE));\n}\n\ndefine pcodeop vldrepl.w;\n\n#lsx.txt vldrepl.w mask=0x30200000\t[@orig_fmt=VdJSk10ps2]\n#0x30200000\t0xfff00000\tv0:5, r5:5, so10:10<<2\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0']\n:vldrepl.w vrD, RJsrc, simm10_10 is op20_31=0x302 & vrD & RJsrc & simm10_10 {\n\tvrD = vldrepl.w(vrD, RJsrc, simm10_10:$(REGSIZE));\n}\n\ndefine pcodeop vldrepl.h;\n\n#lsx.txt vldrepl.h mask=0x30400000\t[@orig_fmt=VdJSk11ps1]\n#0x30400000\t0xffe00000\tv0:5, r5:5, so10:11<<1\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0']\n:vldrepl.h vrD, RJsrc, simm10_11 is op21_31=0x182 & vrD & RJsrc & simm10_11 {\n\tvrD = vldrepl.h(vrD, RJsrc, simm10_11:$(REGSIZE));\n}\n\ndefine pcodeop vldrepl.b;\n\n#lsx.txt vldrepl.b mask=0x30800000\t\n#0x30800000\t0xffc00000\tv0:5, r5:5, so10:12\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0']\n:vldrepl.b vrD, RJsrc, simm10_12 is op22_31=0xc2 & vrD & RJsrc & simm10_12 {\n\tvrD = vldrepl.b(vrD, RJsrc, simm10_12:$(REGSIZE));\n}\n\ndefine pcodeop vstelm.d;\n\n#lsx.txt vstelm.d mask=0x31100000\t[@orig_fmt=VdJSk8ps3Un1]\n#0x31100000\t0xfff80000\tv0:5, r5:5, so10:8<<3,u18:1\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_1_s0']\n:vstelm.d vrD, RJsrc, simm10_8, imm18_1 is op19_31=0x622 & vrD & RJsrc & simm10_8 & imm18_1 {\n\tvrD = vstelm.d(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_1:$(REGSIZE));\n}\n\ndefine pcodeop vstelm.w;\n\n#lsx.txt vstelm.w mask=0x31200000\t[@orig_fmt=VdJSk8ps2Un2]\n#0x31200000\t0xfff00000\tv0:5, r5:5, so10:8<<2,u18:2\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0']\n:vstelm.w vrD, RJsrc, simm10_8, imm18_2 is op20_31=0x312 & vrD & RJsrc & simm10_8 & imm18_2 {\n\tvrD = vstelm.w(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE));\n}\n\ndefine pcodeop vstelm.h;\n\n#lsx.txt vstelm.h mask=0x31400000\t[@orig_fmt=VdJSk8ps1Un3]\n#0x31400000\t0xffe00000\tv0:5, r5:5, so10:8<<1,u18:3\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0']\n:vstelm.h vrD, RJsrc, simm10_8, imm18_3 is op21_31=0x18a & vrD & RJsrc & simm10_8 & imm18_3 {\n\tvrD = vstelm.h(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE));\n}\n\ndefine pcodeop vstelm.b;\n\n#lsx.txt vstelm.b mask=0x31800000\t\n#0x31800000\t0xffc00000\tv0:5, r5:5, so10:8,u18:4\t['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0']\n:vstelm.b vrD, RJsrc, simm10_8, imm18_4 is op22_31=0xc6 & vrD & RJsrc & simm10_8 & imm18_4 {\n\tvrD = vstelm.b(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE));\n}\n\ndefine pcodeop vldx;\n\n#lsx.txt vldx mask=0x38400000\t\n#0x38400000\t0xffff8000\tv0:5, r5:5, r10:5\t['vreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:vldx vrD, RJsrc, RKsrc is op15_31=0x7080 & vrD & RJsrc & RKsrc {\n\tvrD = vldx(vrD, RJsrc, RKsrc);\n}\n\ndefine pcodeop vstx;\n\n#lsx.txt vstx mask=0x38440000\t\n#0x38440000\t0xffff8000\tv0:5, r5:5, r10:5\t['vreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0']\n:vstx vrD, RJsrc, RKsrc is op15_31=0x7088 & vrD & RJsrc & RKsrc {\n\tvrD = vstx(vrD, RJsrc, RKsrc);\n}\n\ndefine pcodeop vseq.b;\n\n#lsx.txt vseq.b mask=0x70000000\t\n#0x70000000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vseq.b vrD, vrJ, vrK is op15_31=0xe000 & vrD & vrJ & vrK {\n\tvrD = vseq.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vseq.h;\n\n#lsx.txt vseq.h mask=0x70008000\t\n#0x70008000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vseq.h vrD, vrJ, vrK is op15_31=0xe001 & vrD & vrJ & vrK {\n\tvrD = vseq.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vseq.w;\n\n#lsx.txt vseq.w mask=0x70010000\t\n#0x70010000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vseq.w vrD, vrJ, vrK is op15_31=0xe002 & vrD & vrJ & vrK {\n\tvrD = vseq.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vseq.d;\n\n#lsx.txt vseq.d mask=0x70018000\t\n#0x70018000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vseq.d vrD, vrJ, vrK is op15_31=0xe003 & vrD & vrJ & vrK {\n\tvrD = vseq.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.b;\n\n#lsx.txt vsle.b mask=0x70020000\t\n#0x70020000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.b vrD, vrJ, vrK is op15_31=0xe004 & vrD & vrJ & vrK {\n\tvrD = vsle.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.h;\n\n#lsx.txt vsle.h mask=0x70028000\t\n#0x70028000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.h vrD, vrJ, vrK is op15_31=0xe005 & vrD & vrJ & vrK {\n\tvrD = vsle.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.w;\n\n#lsx.txt vsle.w mask=0x70030000\t\n#0x70030000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.w vrD, vrJ, vrK is op15_31=0xe006 & vrD & vrJ & vrK {\n\tvrD = vsle.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.d;\n\n#lsx.txt vsle.d mask=0x70038000\t\n#0x70038000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.d vrD, vrJ, vrK is op15_31=0xe007 & vrD & vrJ & vrK {\n\tvrD = vsle.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.bu;\n\n#lsx.txt vsle.bu mask=0x70040000\t\n#0x70040000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.bu vrD, vrJ, vrK is op15_31=0xe008 & vrD & vrJ & vrK {\n\tvrD = vsle.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.hu;\n\n#lsx.txt vsle.hu mask=0x70048000\t\n#0x70048000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.hu vrD, vrJ, vrK is op15_31=0xe009 & vrD & vrJ & vrK {\n\tvrD = vsle.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.wu;\n\n#lsx.txt vsle.wu mask=0x70050000\t\n#0x70050000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.wu vrD, vrJ, vrK is op15_31=0xe00a & vrD & vrJ & vrK {\n\tvrD = vsle.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsle.du;\n\n#lsx.txt vsle.du mask=0x70058000\t\n#0x70058000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsle.du vrD, vrJ, vrK is op15_31=0xe00b & vrD & vrJ & vrK {\n\tvrD = vsle.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.b;\n\n#lsx.txt vslt.b mask=0x70060000\t\n#0x70060000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.b vrD, vrJ, vrK is op15_31=0xe00c & vrD & vrJ & vrK {\n\tvrD = vslt.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.h;\n\n#lsx.txt vslt.h mask=0x70068000\t\n#0x70068000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.h vrD, vrJ, vrK is op15_31=0xe00d & vrD & vrJ & vrK {\n\tvrD = vslt.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.w;\n\n#lsx.txt vslt.w mask=0x70070000\t\n#0x70070000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.w vrD, vrJ, vrK is op15_31=0xe00e & vrD & vrJ & vrK {\n\tvrD = vslt.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.d;\n\n#lsx.txt vslt.d mask=0x70078000\t\n#0x70078000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.d vrD, vrJ, vrK is op15_31=0xe00f & vrD & vrJ & vrK {\n\tvrD = vslt.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.bu;\n\n#lsx.txt vslt.bu mask=0x70080000\t\n#0x70080000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.bu vrD, vrJ, vrK is op15_31=0xe010 & vrD & vrJ & vrK {\n\tvrD = vslt.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.hu;\n\n#lsx.txt vslt.hu mask=0x70088000\t\n#0x70088000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.hu vrD, vrJ, vrK is op15_31=0xe011 & vrD & vrJ & vrK {\n\tvrD = vslt.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.wu;\n\n#lsx.txt vslt.wu mask=0x70090000\t\n#0x70090000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.wu vrD, vrJ, vrK is op15_31=0xe012 & vrD & vrJ & vrK {\n\tvrD = vslt.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vslt.du;\n\n#lsx.txt vslt.du mask=0x70098000\t\n#0x70098000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vslt.du vrD, vrJ, vrK is op15_31=0xe013 & vrD & vrJ & vrK {\n\tvrD = vslt.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadd.b;\n\n#lsx.txt vadd.b mask=0x700a0000\t\n#0x700a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadd.b vrD, vrJ, vrK is op15_31=0xe014 & vrD & vrJ & vrK {\n\tvrD = vadd.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadd.h;\n\n#lsx.txt vadd.h mask=0x700a8000\t\n#0x700a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadd.h vrD, vrJ, vrK is op15_31=0xe015 & vrD & vrJ & vrK {\n\tvrD = vadd.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadd.w;\n\n#lsx.txt vadd.w mask=0x700b0000\t\n#0x700b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadd.w vrD, vrJ, vrK is op15_31=0xe016 & vrD & vrJ & vrK {\n\tvrD = vadd.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadd.d;\n\n#lsx.txt vadd.d mask=0x700b8000\t\n#0x700b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadd.d vrD, vrJ, vrK is op15_31=0xe017 & vrD & vrJ & vrK {\n\tvrD = vadd.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsub.b;\n\n#lsx.txt vsub.b mask=0x700c0000\t\n#0x700c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsub.b vrD, vrJ, vrK is op15_31=0xe018 & vrD & vrJ & vrK {\n\tvrD = vsub.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsub.h;\n\n#lsx.txt vsub.h mask=0x700c8000\t\n#0x700c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsub.h vrD, vrJ, vrK is op15_31=0xe019 & vrD & vrJ & vrK {\n\tvrD = vsub.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsub.w;\n\n#lsx.txt vsub.w mask=0x700d0000\t\n#0x700d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsub.w vrD, vrJ, vrK is op15_31=0xe01a & vrD & vrJ & vrK {\n\tvrD = vsub.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsub.d;\n\n#lsx.txt vsub.d mask=0x700d8000\t\n#0x700d8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsub.d vrD, vrJ, vrK is op15_31=0xe01b & vrD & vrJ & vrK {\n\tvrD = vsub.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.h.b;\n\n#lsx.txt vaddwev.h.b mask=0x701e0000\t\n#0x701e0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.h.b vrD, vrJ, vrK is op15_31=0xe03c & vrD & vrJ & vrK {\n\tvrD = vaddwev.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.w.h;\n\n#lsx.txt vaddwev.w.h mask=0x701e8000\t\n#0x701e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.w.h vrD, vrJ, vrK is op15_31=0xe03d & vrD & vrJ & vrK {\n\tvrD = vaddwev.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.d.w;\n\n#lsx.txt vaddwev.d.w mask=0x701f0000\t\n#0x701f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.d.w vrD, vrJ, vrK is op15_31=0xe03e & vrD & vrJ & vrK {\n\tvrD = vaddwev.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.q.d;\n\n#lsx.txt vaddwev.q.d mask=0x701f8000\t\n#0x701f8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.q.d vrD, vrJ, vrK is op15_31=0xe03f & vrD & vrJ & vrK {\n\tvrD = vaddwev.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.h.b;\n\n#lsx.txt vsubwev.h.b mask=0x70200000\t\n#0x70200000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.h.b vrD, vrJ, vrK is op15_31=0xe040 & vrD & vrJ & vrK {\n\tvrD = vsubwev.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.w.h;\n\n#lsx.txt vsubwev.w.h mask=0x70208000\t\n#0x70208000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.w.h vrD, vrJ, vrK is op15_31=0xe041 & vrD & vrJ & vrK {\n\tvrD = vsubwev.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.d.w;\n\n#lsx.txt vsubwev.d.w mask=0x70210000\t\n#0x70210000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.d.w vrD, vrJ, vrK is op15_31=0xe042 & vrD & vrJ & vrK {\n\tvrD = vsubwev.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.q.d;\n\n#lsx.txt vsubwev.q.d mask=0x70218000\t\n#0x70218000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.q.d vrD, vrJ, vrK is op15_31=0xe043 & vrD & vrJ & vrK {\n\tvrD = vsubwev.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.h.b;\n\n#lsx.txt vaddwod.h.b mask=0x70220000\t\n#0x70220000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.h.b vrD, vrJ, vrK is op15_31=0xe044 & vrD & vrJ & vrK {\n\tvrD = vaddwod.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.w.h;\n\n#lsx.txt vaddwod.w.h mask=0x70228000\t\n#0x70228000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.w.h vrD, vrJ, vrK is op15_31=0xe045 & vrD & vrJ & vrK {\n\tvrD = vaddwod.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.d.w;\n\n#lsx.txt vaddwod.d.w mask=0x70230000\t\n#0x70230000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.d.w vrD, vrJ, vrK is op15_31=0xe046 & vrD & vrJ & vrK {\n\tvrD = vaddwod.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.q.d;\n\n#lsx.txt vaddwod.q.d mask=0x70238000\t\n#0x70238000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.q.d vrD, vrJ, vrK is op15_31=0xe047 & vrD & vrJ & vrK {\n\tvrD = vaddwod.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.h.b;\n\n#lsx.txt vsubwod.h.b mask=0x70240000\t\n#0x70240000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.h.b vrD, vrJ, vrK is op15_31=0xe048 & vrD & vrJ & vrK {\n\tvrD = vsubwod.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.w.h;\n\n#lsx.txt vsubwod.w.h mask=0x70248000\t\n#0x70248000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.w.h vrD, vrJ, vrK is op15_31=0xe049 & vrD & vrJ & vrK {\n\tvrD = vsubwod.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.d.w;\n\n#lsx.txt vsubwod.d.w mask=0x70250000\t\n#0x70250000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.d.w vrD, vrJ, vrK is op15_31=0xe04a & vrD & vrJ & vrK {\n\tvrD = vsubwod.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.q.d;\n\n#lsx.txt vsubwod.q.d mask=0x70258000\t\n#0x70258000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.q.d vrD, vrJ, vrK is op15_31=0xe04b & vrD & vrJ & vrK {\n\tvrD = vsubwod.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.h.bu;\n\n#lsx.txt vaddwev.h.bu mask=0x702e0000\t\n#0x702e0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.h.bu vrD, vrJ, vrK is op15_31=0xe05c & vrD & vrJ & vrK {\n\tvrD = vaddwev.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.w.hu;\n\n#lsx.txt vaddwev.w.hu mask=0x702e8000\t\n#0x702e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.w.hu vrD, vrJ, vrK is op15_31=0xe05d & vrD & vrJ & vrK {\n\tvrD = vaddwev.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.d.wu;\n\n#lsx.txt vaddwev.d.wu mask=0x702f0000\t\n#0x702f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.d.wu vrD, vrJ, vrK is op15_31=0xe05e & vrD & vrJ & vrK {\n\tvrD = vaddwev.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.q.du;\n\n#lsx.txt vaddwev.q.du mask=0x702f8000\t\n#0x702f8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.q.du vrD, vrJ, vrK is op15_31=0xe05f & vrD & vrJ & vrK {\n\tvrD = vaddwev.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.h.bu;\n\n#lsx.txt vsubwev.h.bu mask=0x70300000\t\n#0x70300000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.h.bu vrD, vrJ, vrK is op15_31=0xe060 & vrD & vrJ & vrK {\n\tvrD = vsubwev.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.w.hu;\n\n#lsx.txt vsubwev.w.hu mask=0x70308000\t\n#0x70308000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.w.hu vrD, vrJ, vrK is op15_31=0xe061 & vrD & vrJ & vrK {\n\tvrD = vsubwev.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.d.wu;\n\n#lsx.txt vsubwev.d.wu mask=0x70310000\t\n#0x70310000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.d.wu vrD, vrJ, vrK is op15_31=0xe062 & vrD & vrJ & vrK {\n\tvrD = vsubwev.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwev.q.du;\n\n#lsx.txt vsubwev.q.du mask=0x70318000\t\n#0x70318000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwev.q.du vrD, vrJ, vrK is op15_31=0xe063 & vrD & vrJ & vrK {\n\tvrD = vsubwev.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.h.bu;\n\n#lsx.txt vaddwod.h.bu mask=0x70320000\t\n#0x70320000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.h.bu vrD, vrJ, vrK is op15_31=0xe064 & vrD & vrJ & vrK {\n\tvrD = vaddwod.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.w.hu;\n\n#lsx.txt vaddwod.w.hu mask=0x70328000\t\n#0x70328000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.w.hu vrD, vrJ, vrK is op15_31=0xe065 & vrD & vrJ & vrK {\n\tvrD = vaddwod.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.d.wu;\n\n#lsx.txt vaddwod.d.wu mask=0x70330000\t\n#0x70330000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.d.wu vrD, vrJ, vrK is op15_31=0xe066 & vrD & vrJ & vrK {\n\tvrD = vaddwod.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.q.du;\n\n#lsx.txt vaddwod.q.du mask=0x70338000\t\n#0x70338000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.q.du vrD, vrJ, vrK is op15_31=0xe067 & vrD & vrJ & vrK {\n\tvrD = vaddwod.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.h.bu;\n\n#lsx.txt vsubwod.h.bu mask=0x70340000\t\n#0x70340000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.h.bu vrD, vrJ, vrK is op15_31=0xe068 & vrD & vrJ & vrK {\n\tvrD = vsubwod.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.w.hu;\n\n#lsx.txt vsubwod.w.hu mask=0x70348000\t\n#0x70348000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.w.hu vrD, vrJ, vrK is op15_31=0xe069 & vrD & vrJ & vrK {\n\tvrD = vsubwod.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.d.wu;\n\n#lsx.txt vsubwod.d.wu mask=0x70350000\t\n#0x70350000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.d.wu vrD, vrJ, vrK is op15_31=0xe06a & vrD & vrJ & vrK {\n\tvrD = vsubwod.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsubwod.q.du;\n\n#lsx.txt vsubwod.q.du mask=0x70358000\t\n#0x70358000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsubwod.q.du vrD, vrJ, vrK is op15_31=0xe06b & vrD & vrJ & vrK {\n\tvrD = vsubwod.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.h.bu.b;\n\n#lsx.txt vaddwev.h.bu.b mask=0x703e0000\t\n#0x703e0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.h.bu.b vrD, vrJ, vrK is op15_31=0xe07c & vrD & vrJ & vrK {\n\tvrD = vaddwev.h.bu.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.w.hu.h;\n\n#lsx.txt vaddwev.w.hu.h mask=0x703e8000\t\n#0x703e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.w.hu.h vrD, vrJ, vrK is op15_31=0xe07d & vrD & vrJ & vrK {\n\tvrD = vaddwev.w.hu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.d.wu.w;\n\n#lsx.txt vaddwev.d.wu.w mask=0x703f0000\t\n#0x703f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.d.wu.w vrD, vrJ, vrK is op15_31=0xe07e & vrD & vrJ & vrK {\n\tvrD = vaddwev.d.wu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwev.q.du.d;\n\n#lsx.txt vaddwev.q.du.d mask=0x703f8000\t\n#0x703f8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwev.q.du.d vrD, vrJ, vrK is op15_31=0xe07f & vrD & vrJ & vrK {\n\tvrD = vaddwev.q.du.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.h.bu.b;\n\n#lsx.txt vaddwod.h.bu.b mask=0x70400000\t\n#0x70400000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.h.bu.b vrD, vrJ, vrK is op15_31=0xe080 & vrD & vrJ & vrK {\n\tvrD = vaddwod.h.bu.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.w.hu.h;\n\n#lsx.txt vaddwod.w.hu.h mask=0x70408000\t\n#0x70408000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.w.hu.h vrD, vrJ, vrK is op15_31=0xe081 & vrD & vrJ & vrK {\n\tvrD = vaddwod.w.hu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.d.wu.w;\n\n#lsx.txt vaddwod.d.wu.w mask=0x70410000\t\n#0x70410000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.d.wu.w vrD, vrJ, vrK is op15_31=0xe082 & vrD & vrJ & vrK {\n\tvrD = vaddwod.d.wu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vaddwod.q.du.d;\n\n#lsx.txt vaddwod.q.du.d mask=0x70418000\t\n#0x70418000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vaddwod.q.du.d vrD, vrJ, vrK is op15_31=0xe083 & vrD & vrJ & vrK {\n\tvrD = vaddwod.q.du.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.b;\n\n#lsx.txt vsadd.b mask=0x70460000\t\n#0x70460000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.b vrD, vrJ, vrK is op15_31=0xe08c & vrD & vrJ & vrK {\n\tvrD = vsadd.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.h;\n\n#lsx.txt vsadd.h mask=0x70468000\t\n#0x70468000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.h vrD, vrJ, vrK is op15_31=0xe08d & vrD & vrJ & vrK {\n\tvrD = vsadd.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.w;\n\n#lsx.txt vsadd.w mask=0x70470000\t\n#0x70470000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.w vrD, vrJ, vrK is op15_31=0xe08e & vrD & vrJ & vrK {\n\tvrD = vsadd.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.d;\n\n#lsx.txt vsadd.d mask=0x70478000\t\n#0x70478000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.d vrD, vrJ, vrK is op15_31=0xe08f & vrD & vrJ & vrK {\n\tvrD = vsadd.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.b;\n\n#lsx.txt vssub.b mask=0x70480000\t\n#0x70480000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.b vrD, vrJ, vrK is op15_31=0xe090 & vrD & vrJ & vrK {\n\tvrD = vssub.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.h;\n\n#lsx.txt vssub.h mask=0x70488000\t\n#0x70488000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.h vrD, vrJ, vrK is op15_31=0xe091 & vrD & vrJ & vrK {\n\tvrD = vssub.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.w;\n\n#lsx.txt vssub.w mask=0x70490000\t\n#0x70490000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.w vrD, vrJ, vrK is op15_31=0xe092 & vrD & vrJ & vrK {\n\tvrD = vssub.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.d;\n\n#lsx.txt vssub.d mask=0x70498000\t\n#0x70498000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.d vrD, vrJ, vrK is op15_31=0xe093 & vrD & vrJ & vrK {\n\tvrD = vssub.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.bu;\n\n#lsx.txt vsadd.bu mask=0x704a0000\t\n#0x704a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.bu vrD, vrJ, vrK is op15_31=0xe094 & vrD & vrJ & vrK {\n\tvrD = vsadd.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.hu;\n\n#lsx.txt vsadd.hu mask=0x704a8000\t\n#0x704a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.hu vrD, vrJ, vrK is op15_31=0xe095 & vrD & vrJ & vrK {\n\tvrD = vsadd.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.wu;\n\n#lsx.txt vsadd.wu mask=0x704b0000\t\n#0x704b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.wu vrD, vrJ, vrK is op15_31=0xe096 & vrD & vrJ & vrK {\n\tvrD = vsadd.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsadd.du;\n\n#lsx.txt vsadd.du mask=0x704b8000\t\n#0x704b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsadd.du vrD, vrJ, vrK is op15_31=0xe097 & vrD & vrJ & vrK {\n\tvrD = vsadd.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.bu;\n\n#lsx.txt vssub.bu mask=0x704c0000\t\n#0x704c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.bu vrD, vrJ, vrK is op15_31=0xe098 & vrD & vrJ & vrK {\n\tvrD = vssub.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.hu;\n\n#lsx.txt vssub.hu mask=0x704c8000\t\n#0x704c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.hu vrD, vrJ, vrK is op15_31=0xe099 & vrD & vrJ & vrK {\n\tvrD = vssub.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.wu;\n\n#lsx.txt vssub.wu mask=0x704d0000\t\n#0x704d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.wu vrD, vrJ, vrK is op15_31=0xe09a & vrD & vrJ & vrK {\n\tvrD = vssub.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssub.du;\n\n#lsx.txt vssub.du mask=0x704d8000\t\n#0x704d8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssub.du vrD, vrJ, vrK is op15_31=0xe09b & vrD & vrJ & vrK {\n\tvrD = vssub.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.h.b;\n\n#lsx.txt vhaddw.h.b mask=0x70540000\t\n#0x70540000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.h.b vrD, vrJ, vrK is op15_31=0xe0a8 & vrD & vrJ & vrK {\n\tvrD = vhaddw.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.w.h;\n\n#lsx.txt vhaddw.w.h mask=0x70548000\t\n#0x70548000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.w.h vrD, vrJ, vrK is op15_31=0xe0a9 & vrD & vrJ & vrK {\n\tvrD = vhaddw.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.d.w;\n\n#lsx.txt vhaddw.d.w mask=0x70550000\t\n#0x70550000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.d.w vrD, vrJ, vrK is op15_31=0xe0aa & vrD & vrJ & vrK {\n\tvrD = vhaddw.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.q.d;\n\n#lsx.txt vhaddw.q.d mask=0x70558000\t\n#0x70558000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.q.d vrD, vrJ, vrK is op15_31=0xe0ab & vrD & vrJ & vrK {\n\tvrD = vhaddw.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.h.b;\n\n#lsx.txt vhsubw.h.b mask=0x70560000\t\n#0x70560000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.h.b vrD, vrJ, vrK is op15_31=0xe0ac & vrD & vrJ & vrK {\n\tvrD = vhsubw.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.w.h;\n\n#lsx.txt vhsubw.w.h mask=0x70568000\t\n#0x70568000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.w.h vrD, vrJ, vrK is op15_31=0xe0ad & vrD & vrJ & vrK {\n\tvrD = vhsubw.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.d.w;\n\n#lsx.txt vhsubw.d.w mask=0x70570000\t\n#0x70570000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.d.w vrD, vrJ, vrK is op15_31=0xe0ae & vrD & vrJ & vrK {\n\tvrD = vhsubw.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.q.d;\n\n#lsx.txt vhsubw.q.d mask=0x70578000\t\n#0x70578000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.q.d vrD, vrJ, vrK is op15_31=0xe0af & vrD & vrJ & vrK {\n\tvrD = vhsubw.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.hu.bu;\n\n#lsx.txt vhaddw.hu.bu mask=0x70580000\t\n#0x70580000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.hu.bu vrD, vrJ, vrK is op15_31=0xe0b0 & vrD & vrJ & vrK {\n\tvrD = vhaddw.hu.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.wu.hu;\n\n#lsx.txt vhaddw.wu.hu mask=0x70588000\t\n#0x70588000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.wu.hu vrD, vrJ, vrK is op15_31=0xe0b1 & vrD & vrJ & vrK {\n\tvrD = vhaddw.wu.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.du.wu;\n\n#lsx.txt vhaddw.du.wu mask=0x70590000\t\n#0x70590000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.du.wu vrD, vrJ, vrK is op15_31=0xe0b2 & vrD & vrJ & vrK {\n\tvrD = vhaddw.du.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhaddw.qu.du;\n\n#lsx.txt vhaddw.qu.du mask=0x70598000\t\n#0x70598000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhaddw.qu.du vrD, vrJ, vrK is op15_31=0xe0b3 & vrD & vrJ & vrK {\n\tvrD = vhaddw.qu.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.hu.bu;\n\n#lsx.txt vhsubw.hu.bu mask=0x705a0000\t\n#0x705a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.hu.bu vrD, vrJ, vrK is op15_31=0xe0b4 & vrD & vrJ & vrK {\n\tvrD = vhsubw.hu.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.wu.hu;\n\n#lsx.txt vhsubw.wu.hu mask=0x705a8000\t\n#0x705a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.wu.hu vrD, vrJ, vrK is op15_31=0xe0b5 & vrD & vrJ & vrK {\n\tvrD = vhsubw.wu.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.du.wu;\n\n#lsx.txt vhsubw.du.wu mask=0x705b0000\t\n#0x705b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.du.wu vrD, vrJ, vrK is op15_31=0xe0b6 & vrD & vrJ & vrK {\n\tvrD = vhsubw.du.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vhsubw.qu.du;\n\n#lsx.txt vhsubw.qu.du mask=0x705b8000\t\n#0x705b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vhsubw.qu.du vrD, vrJ, vrK is op15_31=0xe0b7 & vrD & vrJ & vrK {\n\tvrD = vhsubw.qu.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadda.b;\n\n#lsx.txt vadda.b mask=0x705c0000\t\n#0x705c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadda.b vrD, vrJ, vrK is op15_31=0xe0b8 & vrD & vrJ & vrK {\n\tvrD = vadda.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadda.h;\n\n#lsx.txt vadda.h mask=0x705c8000\t\n#0x705c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadda.h vrD, vrJ, vrK is op15_31=0xe0b9 & vrD & vrJ & vrK {\n\tvrD = vadda.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadda.w;\n\n#lsx.txt vadda.w mask=0x705d0000\t\n#0x705d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadda.w vrD, vrJ, vrK is op15_31=0xe0ba & vrD & vrJ & vrK {\n\tvrD = vadda.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadda.d;\n\n#lsx.txt vadda.d mask=0x705d8000\t\n#0x705d8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadda.d vrD, vrJ, vrK is op15_31=0xe0bb & vrD & vrJ & vrK {\n\tvrD = vadda.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.b;\n\n#lsx.txt vabsd.b mask=0x70600000\t\n#0x70600000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.b vrD, vrJ, vrK is op15_31=0xe0c0 & vrD & vrJ & vrK {\n\tvrD = vabsd.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.h;\n\n#lsx.txt vabsd.h mask=0x70608000\t\n#0x70608000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.h vrD, vrJ, vrK is op15_31=0xe0c1 & vrD & vrJ & vrK {\n\tvrD = vabsd.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.w;\n\n#lsx.txt vabsd.w mask=0x70610000\t\n#0x70610000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.w vrD, vrJ, vrK is op15_31=0xe0c2 & vrD & vrJ & vrK {\n\tvrD = vabsd.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.d;\n\n#lsx.txt vabsd.d mask=0x70618000\t\n#0x70618000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.d vrD, vrJ, vrK is op15_31=0xe0c3 & vrD & vrJ & vrK {\n\tvrD = vabsd.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.bu;\n\n#lsx.txt vabsd.bu mask=0x70620000\t\n#0x70620000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.bu vrD, vrJ, vrK is op15_31=0xe0c4 & vrD & vrJ & vrK {\n\tvrD = vabsd.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.hu;\n\n#lsx.txt vabsd.hu mask=0x70628000\t\n#0x70628000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.hu vrD, vrJ, vrK is op15_31=0xe0c5 & vrD & vrJ & vrK {\n\tvrD = vabsd.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.wu;\n\n#lsx.txt vabsd.wu mask=0x70630000\t\n#0x70630000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.wu vrD, vrJ, vrK is op15_31=0xe0c6 & vrD & vrJ & vrK {\n\tvrD = vabsd.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vabsd.du;\n\n#lsx.txt vabsd.du mask=0x70638000\t\n#0x70638000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vabsd.du vrD, vrJ, vrK is op15_31=0xe0c7 & vrD & vrJ & vrK {\n\tvrD = vabsd.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.b;\n\n#lsx.txt vavg.b mask=0x70640000\t\n#0x70640000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.b vrD, vrJ, vrK is op15_31=0xe0c8 & vrD & vrJ & vrK {\n\tvrD = vavg.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.h;\n\n#lsx.txt vavg.h mask=0x70648000\t\n#0x70648000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.h vrD, vrJ, vrK is op15_31=0xe0c9 & vrD & vrJ & vrK {\n\tvrD = vavg.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.w;\n\n#lsx.txt vavg.w mask=0x70650000\t\n#0x70650000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.w vrD, vrJ, vrK is op15_31=0xe0ca & vrD & vrJ & vrK {\n\tvrD = vavg.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.d;\n\n#lsx.txt vavg.d mask=0x70658000\t\n#0x70658000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.d vrD, vrJ, vrK is op15_31=0xe0cb & vrD & vrJ & vrK {\n\tvrD = vavg.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.bu;\n\n#lsx.txt vavg.bu mask=0x70660000\t\n#0x70660000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.bu vrD, vrJ, vrK is op15_31=0xe0cc & vrD & vrJ & vrK {\n\tvrD = vavg.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.hu;\n\n#lsx.txt vavg.hu mask=0x70668000\t\n#0x70668000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.hu vrD, vrJ, vrK is op15_31=0xe0cd & vrD & vrJ & vrK {\n\tvrD = vavg.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.wu;\n\n#lsx.txt vavg.wu mask=0x70670000\t\n#0x70670000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.wu vrD, vrJ, vrK is op15_31=0xe0ce & vrD & vrJ & vrK {\n\tvrD = vavg.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavg.du;\n\n#lsx.txt vavg.du mask=0x70678000\t\n#0x70678000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavg.du vrD, vrJ, vrK is op15_31=0xe0cf & vrD & vrJ & vrK {\n\tvrD = vavg.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.b;\n\n#lsx.txt vavgr.b mask=0x70680000\t\n#0x70680000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.b vrD, vrJ, vrK is op15_31=0xe0d0 & vrD & vrJ & vrK {\n\tvrD = vavgr.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.h;\n\n#lsx.txt vavgr.h mask=0x70688000\t\n#0x70688000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.h vrD, vrJ, vrK is op15_31=0xe0d1 & vrD & vrJ & vrK {\n\tvrD = vavgr.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.w;\n\n#lsx.txt vavgr.w mask=0x70690000\t\n#0x70690000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.w vrD, vrJ, vrK is op15_31=0xe0d2 & vrD & vrJ & vrK {\n\tvrD = vavgr.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.d;\n\n#lsx.txt vavgr.d mask=0x70698000\t\n#0x70698000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.d vrD, vrJ, vrK is op15_31=0xe0d3 & vrD & vrJ & vrK {\n\tvrD = vavgr.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.bu;\n\n#lsx.txt vavgr.bu mask=0x706a0000\t\n#0x706a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.bu vrD, vrJ, vrK is op15_31=0xe0d4 & vrD & vrJ & vrK {\n\tvrD = vavgr.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.hu;\n\n#lsx.txt vavgr.hu mask=0x706a8000\t\n#0x706a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.hu vrD, vrJ, vrK is op15_31=0xe0d5 & vrD & vrJ & vrK {\n\tvrD = vavgr.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.wu;\n\n#lsx.txt vavgr.wu mask=0x706b0000\t\n#0x706b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.wu vrD, vrJ, vrK is op15_31=0xe0d6 & vrD & vrJ & vrK {\n\tvrD = vavgr.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vavgr.du;\n\n#lsx.txt vavgr.du mask=0x706b8000\t\n#0x706b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vavgr.du vrD, vrJ, vrK is op15_31=0xe0d7 & vrD & vrJ & vrK {\n\tvrD = vavgr.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.b;\n\n#lsx.txt vmax.b mask=0x70700000\t\n#0x70700000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.b vrD, vrJ, vrK is op15_31=0xe0e0 & vrD & vrJ & vrK {\n\tvrD = vmax.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.h;\n\n#lsx.txt vmax.h mask=0x70708000\t\n#0x70708000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.h vrD, vrJ, vrK is op15_31=0xe0e1 & vrD & vrJ & vrK {\n\tvrD = vmax.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.w;\n\n#lsx.txt vmax.w mask=0x70710000\t\n#0x70710000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.w vrD, vrJ, vrK is op15_31=0xe0e2 & vrD & vrJ & vrK {\n\tvrD = vmax.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.d;\n\n#lsx.txt vmax.d mask=0x70718000\t\n#0x70718000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.d vrD, vrJ, vrK is op15_31=0xe0e3 & vrD & vrJ & vrK {\n\tvrD = vmax.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.b;\n\n#lsx.txt vmin.b mask=0x70720000\t\n#0x70720000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.b vrD, vrJ, vrK is op15_31=0xe0e4 & vrD & vrJ & vrK {\n\tvrD = vmin.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.h;\n\n#lsx.txt vmin.h mask=0x70728000\t\n#0x70728000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.h vrD, vrJ, vrK is op15_31=0xe0e5 & vrD & vrJ & vrK {\n\tvrD = vmin.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.w;\n\n#lsx.txt vmin.w mask=0x70730000\t\n#0x70730000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.w vrD, vrJ, vrK is op15_31=0xe0e6 & vrD & vrJ & vrK {\n\tvrD = vmin.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.d;\n\n#lsx.txt vmin.d mask=0x70738000\t\n#0x70738000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.d vrD, vrJ, vrK is op15_31=0xe0e7 & vrD & vrJ & vrK {\n\tvrD = vmin.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.bu;\n\n#lsx.txt vmax.bu mask=0x70740000\t\n#0x70740000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.bu vrD, vrJ, vrK is op15_31=0xe0e8 & vrD & vrJ & vrK {\n\tvrD = vmax.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.hu;\n\n#lsx.txt vmax.hu mask=0x70748000\t\n#0x70748000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.hu vrD, vrJ, vrK is op15_31=0xe0e9 & vrD & vrJ & vrK {\n\tvrD = vmax.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.wu;\n\n#lsx.txt vmax.wu mask=0x70750000\t\n#0x70750000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.wu vrD, vrJ, vrK is op15_31=0xe0ea & vrD & vrJ & vrK {\n\tvrD = vmax.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmax.du;\n\n#lsx.txt vmax.du mask=0x70758000\t\n#0x70758000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmax.du vrD, vrJ, vrK is op15_31=0xe0eb & vrD & vrJ & vrK {\n\tvrD = vmax.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.bu;\n\n#lsx.txt vmin.bu mask=0x70760000\t\n#0x70760000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.bu vrD, vrJ, vrK is op15_31=0xe0ec & vrD & vrJ & vrK {\n\tvrD = vmin.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.hu;\n\n#lsx.txt vmin.hu mask=0x70768000\t\n#0x70768000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.hu vrD, vrJ, vrK is op15_31=0xe0ed & vrD & vrJ & vrK {\n\tvrD = vmin.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.wu;\n\n#lsx.txt vmin.wu mask=0x70770000\t\n#0x70770000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.wu vrD, vrJ, vrK is op15_31=0xe0ee & vrD & vrJ & vrK {\n\tvrD = vmin.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmin.du;\n\n#lsx.txt vmin.du mask=0x70778000\t\n#0x70778000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmin.du vrD, vrJ, vrK is op15_31=0xe0ef & vrD & vrJ & vrK {\n\tvrD = vmin.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmul.b;\n\n#lsx.txt vmul.b mask=0x70840000\t\n#0x70840000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmul.b vrD, vrJ, vrK is op15_31=0xe108 & vrD & vrJ & vrK {\n\tvrD = vmul.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmul.h;\n\n#lsx.txt vmul.h mask=0x70848000\t\n#0x70848000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmul.h vrD, vrJ, vrK is op15_31=0xe109 & vrD & vrJ & vrK {\n\tvrD = vmul.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmul.w;\n\n#lsx.txt vmul.w mask=0x70850000\t\n#0x70850000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmul.w vrD, vrJ, vrK is op15_31=0xe10a & vrD & vrJ & vrK {\n\tvrD = vmul.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmul.d;\n\n#lsx.txt vmul.d mask=0x70858000\t\n#0x70858000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmul.d vrD, vrJ, vrK is op15_31=0xe10b & vrD & vrJ & vrK {\n\tvrD = vmul.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.b;\n\n#lsx.txt vmuh.b mask=0x70860000\t\n#0x70860000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.b vrD, vrJ, vrK is op15_31=0xe10c & vrD & vrJ & vrK {\n\tvrD = vmuh.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.h;\n\n#lsx.txt vmuh.h mask=0x70868000\t\n#0x70868000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.h vrD, vrJ, vrK is op15_31=0xe10d & vrD & vrJ & vrK {\n\tvrD = vmuh.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.w;\n\n#lsx.txt vmuh.w mask=0x70870000\t\n#0x70870000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.w vrD, vrJ, vrK is op15_31=0xe10e & vrD & vrJ & vrK {\n\tvrD = vmuh.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.d;\n\n#lsx.txt vmuh.d mask=0x70878000\t\n#0x70878000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.d vrD, vrJ, vrK is op15_31=0xe10f & vrD & vrJ & vrK {\n\tvrD = vmuh.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.bu;\n\n#lsx.txt vmuh.bu mask=0x70880000\t\n#0x70880000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.bu vrD, vrJ, vrK is op15_31=0xe110 & vrD & vrJ & vrK {\n\tvrD = vmuh.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.hu;\n\n#lsx.txt vmuh.hu mask=0x70888000\t\n#0x70888000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.hu vrD, vrJ, vrK is op15_31=0xe111 & vrD & vrJ & vrK {\n\tvrD = vmuh.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.wu;\n\n#lsx.txt vmuh.wu mask=0x70890000\t\n#0x70890000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.wu vrD, vrJ, vrK is op15_31=0xe112 & vrD & vrJ & vrK {\n\tvrD = vmuh.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmuh.du;\n\n#lsx.txt vmuh.du mask=0x70898000\t\n#0x70898000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmuh.du vrD, vrJ, vrK is op15_31=0xe113 & vrD & vrJ & vrK {\n\tvrD = vmuh.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.h.b;\n\n#lsx.txt vmulwev.h.b mask=0x70900000\t\n#0x70900000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.h.b vrD, vrJ, vrK is op15_31=0xe120 & vrD & vrJ & vrK {\n\tvrD = vmulwev.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.w.h;\n\n#lsx.txt vmulwev.w.h mask=0x70908000\t\n#0x70908000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.w.h vrD, vrJ, vrK is op15_31=0xe121 & vrD & vrJ & vrK {\n\tvrD = vmulwev.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.d.w;\n\n#lsx.txt vmulwev.d.w mask=0x70910000\t\n#0x70910000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.d.w vrD, vrJ, vrK is op15_31=0xe122 & vrD & vrJ & vrK {\n\tvrD = vmulwev.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.q.d;\n\n#lsx.txt vmulwev.q.d mask=0x70918000\t\n#0x70918000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.q.d vrD, vrJ, vrK is op15_31=0xe123 & vrD & vrJ & vrK {\n\tvrD = vmulwev.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.h.b;\n\n#lsx.txt vmulwod.h.b mask=0x70920000\t\n#0x70920000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.h.b vrD, vrJ, vrK is op15_31=0xe124 & vrD & vrJ & vrK {\n\tvrD = vmulwod.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.w.h;\n\n#lsx.txt vmulwod.w.h mask=0x70928000\t\n#0x70928000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.w.h vrD, vrJ, vrK is op15_31=0xe125 & vrD & vrJ & vrK {\n\tvrD = vmulwod.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.d.w;\n\n#lsx.txt vmulwod.d.w mask=0x70930000\t\n#0x70930000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.d.w vrD, vrJ, vrK is op15_31=0xe126 & vrD & vrJ & vrK {\n\tvrD = vmulwod.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.q.d;\n\n#lsx.txt vmulwod.q.d mask=0x70938000\t\n#0x70938000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.q.d vrD, vrJ, vrK is op15_31=0xe127 & vrD & vrJ & vrK {\n\tvrD = vmulwod.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.h.bu;\n\n#lsx.txt vmulwev.h.bu mask=0x70980000\t\n#0x70980000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.h.bu vrD, vrJ, vrK is op15_31=0xe130 & vrD & vrJ & vrK {\n\tvrD = vmulwev.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.w.hu;\n\n#lsx.txt vmulwev.w.hu mask=0x70988000\t\n#0x70988000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.w.hu vrD, vrJ, vrK is op15_31=0xe131 & vrD & vrJ & vrK {\n\tvrD = vmulwev.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.d.wu;\n\n#lsx.txt vmulwev.d.wu mask=0x70990000\t\n#0x70990000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.d.wu vrD, vrJ, vrK is op15_31=0xe132 & vrD & vrJ & vrK {\n\tvrD = vmulwev.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.q.du;\n\n#lsx.txt vmulwev.q.du mask=0x70998000\t\n#0x70998000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.q.du vrD, vrJ, vrK is op15_31=0xe133 & vrD & vrJ & vrK {\n\tvrD = vmulwev.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.h.bu;\n\n#lsx.txt vmulwod.h.bu mask=0x709a0000\t\n#0x709a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.h.bu vrD, vrJ, vrK is op15_31=0xe134 & vrD & vrJ & vrK {\n\tvrD = vmulwod.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.w.hu;\n\n#lsx.txt vmulwod.w.hu mask=0x709a8000\t\n#0x709a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.w.hu vrD, vrJ, vrK is op15_31=0xe135 & vrD & vrJ & vrK {\n\tvrD = vmulwod.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.d.wu;\n\n#lsx.txt vmulwod.d.wu mask=0x709b0000\t\n#0x709b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.d.wu vrD, vrJ, vrK is op15_31=0xe136 & vrD & vrJ & vrK {\n\tvrD = vmulwod.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.q.du;\n\n#lsx.txt vmulwod.q.du mask=0x709b8000\t\n#0x709b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.q.du vrD, vrJ, vrK is op15_31=0xe137 & vrD & vrJ & vrK {\n\tvrD = vmulwod.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.h.bu.b;\n\n#lsx.txt vmulwev.h.bu.b mask=0x70a00000\t\n#0x70a00000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.h.bu.b vrD, vrJ, vrK is op15_31=0xe140 & vrD & vrJ & vrK {\n\tvrD = vmulwev.h.bu.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.w.hu.h;\n\n#lsx.txt vmulwev.w.hu.h mask=0x70a08000\t\n#0x70a08000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.w.hu.h vrD, vrJ, vrK is op15_31=0xe141 & vrD & vrJ & vrK {\n\tvrD = vmulwev.w.hu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.d.wu.w;\n\n#lsx.txt vmulwev.d.wu.w mask=0x70a10000\t\n#0x70a10000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.d.wu.w vrD, vrJ, vrK is op15_31=0xe142 & vrD & vrJ & vrK {\n\tvrD = vmulwev.d.wu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwev.q.du.d;\n\n#lsx.txt vmulwev.q.du.d mask=0x70a18000\t\n#0x70a18000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwev.q.du.d vrD, vrJ, vrK is op15_31=0xe143 & vrD & vrJ & vrK {\n\tvrD = vmulwev.q.du.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.h.bu.b;\n\n#lsx.txt vmulwod.h.bu.b mask=0x70a20000\t\n#0x70a20000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.h.bu.b vrD, vrJ, vrK is op15_31=0xe144 & vrD & vrJ & vrK {\n\tvrD = vmulwod.h.bu.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.w.hu.h;\n\n#lsx.txt vmulwod.w.hu.h mask=0x70a28000\t\n#0x70a28000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.w.hu.h vrD, vrJ, vrK is op15_31=0xe145 & vrD & vrJ & vrK {\n\tvrD = vmulwod.w.hu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.d.wu.w;\n\n#lsx.txt vmulwod.d.wu.w mask=0x70a30000\t\n#0x70a30000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.d.wu.w vrD, vrJ, vrK is op15_31=0xe146 & vrD & vrJ & vrK {\n\tvrD = vmulwod.d.wu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmulwod.q.du.d;\n\n#lsx.txt vmulwod.q.du.d mask=0x70a38000\t\n#0x70a38000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmulwod.q.du.d vrD, vrJ, vrK is op15_31=0xe147 & vrD & vrJ & vrK {\n\tvrD = vmulwod.q.du.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmadd.b;\n\n#lsx.txt vmadd.b mask=0x70a80000\t\n#0x70a80000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmadd.b vrD, vrJ, vrK is op15_31=0xe150 & vrD & vrJ & vrK {\n\tvrD = vmadd.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmadd.h;\n\n#lsx.txt vmadd.h mask=0x70a88000\t\n#0x70a88000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmadd.h vrD, vrJ, vrK is op15_31=0xe151 & vrD & vrJ & vrK {\n\tvrD = vmadd.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmadd.w;\n\n#lsx.txt vmadd.w mask=0x70a90000\t\n#0x70a90000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmadd.w vrD, vrJ, vrK is op15_31=0xe152 & vrD & vrJ & vrK {\n\tvrD = vmadd.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmadd.d;\n\n#lsx.txt vmadd.d mask=0x70a98000\t\n#0x70a98000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmadd.d vrD, vrJ, vrK is op15_31=0xe153 & vrD & vrJ & vrK {\n\tvrD = vmadd.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmsub.b;\n\n#lsx.txt vmsub.b mask=0x70aa0000\t\n#0x70aa0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmsub.b vrD, vrJ, vrK is op15_31=0xe154 & vrD & vrJ & vrK {\n\tvrD = vmsub.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmsub.h;\n\n#lsx.txt vmsub.h mask=0x70aa8000\t\n#0x70aa8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmsub.h vrD, vrJ, vrK is op15_31=0xe155 & vrD & vrJ & vrK {\n\tvrD = vmsub.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmsub.w;\n\n#lsx.txt vmsub.w mask=0x70ab0000\t\n#0x70ab0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmsub.w vrD, vrJ, vrK is op15_31=0xe156 & vrD & vrJ & vrK {\n\tvrD = vmsub.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmsub.d;\n\n#lsx.txt vmsub.d mask=0x70ab8000\t\n#0x70ab8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmsub.d vrD, vrJ, vrK is op15_31=0xe157 & vrD & vrJ & vrK {\n\tvrD = vmsub.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.h.b;\n\n#lsx.txt vmaddwev.h.b mask=0x70ac0000\t\n#0x70ac0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.h.b vrD, vrJ, vrK is op15_31=0xe158 & vrD & vrJ & vrK {\n\tvrD = vmaddwev.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.w.h;\n\n#lsx.txt vmaddwev.w.h mask=0x70ac8000\t\n#0x70ac8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.w.h vrD, vrJ, vrK is op15_31=0xe159 & vrD & vrJ & vrK {\n\tvrD = vmaddwev.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.d.w;\n\n#lsx.txt vmaddwev.d.w mask=0x70ad0000\t\n#0x70ad0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.d.w vrD, vrJ, vrK is op15_31=0xe15a & vrD & vrJ & vrK {\n\tvrD = vmaddwev.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.q.d;\n\n#lsx.txt vmaddwev.q.d mask=0x70ad8000\t\n#0x70ad8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.q.d vrD, vrJ, vrK is op15_31=0xe15b & vrD & vrJ & vrK {\n\tvrD = vmaddwev.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.h.b;\n\n#lsx.txt vmaddwod.h.b mask=0x70ae0000\t\n#0x70ae0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.h.b vrD, vrJ, vrK is op15_31=0xe15c & vrD & vrJ & vrK {\n\tvrD = vmaddwod.h.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.w.h;\n\n#lsx.txt vmaddwod.w.h mask=0x70ae8000\t\n#0x70ae8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.w.h vrD, vrJ, vrK is op15_31=0xe15d & vrD & vrJ & vrK {\n\tvrD = vmaddwod.w.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.d.w;\n\n#lsx.txt vmaddwod.d.w mask=0x70af0000\t\n#0x70af0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.d.w vrD, vrJ, vrK is op15_31=0xe15e & vrD & vrJ & vrK {\n\tvrD = vmaddwod.d.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.q.d;\n\n#lsx.txt vmaddwod.q.d mask=0x70af8000\t\n#0x70af8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.q.d vrD, vrJ, vrK is op15_31=0xe15f & vrD & vrJ & vrK {\n\tvrD = vmaddwod.q.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.h.bu;\n\n#lsx.txt vmaddwev.h.bu mask=0x70b40000\t\n#0x70b40000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.h.bu vrD, vrJ, vrK is op15_31=0xe168 & vrD & vrJ & vrK {\n\tvrD = vmaddwev.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.w.hu;\n\n#lsx.txt vmaddwev.w.hu mask=0x70b48000\t\n#0x70b48000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.w.hu vrD, vrJ, vrK is op15_31=0xe169 & vrD & vrJ & vrK {\n\tvrD = vmaddwev.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.d.wu;\n\n#lsx.txt vmaddwev.d.wu mask=0x70b50000\t\n#0x70b50000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.d.wu vrD, vrJ, vrK is op15_31=0xe16a & vrD & vrJ & vrK {\n\tvrD = vmaddwev.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.q.du;\n\n#lsx.txt vmaddwev.q.du mask=0x70b58000\t\n#0x70b58000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.q.du vrD, vrJ, vrK is op15_31=0xe16b & vrD & vrJ & vrK {\n\tvrD = vmaddwev.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.h.bu;\n\n#lsx.txt vmaddwod.h.bu mask=0x70b60000\t\n#0x70b60000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.h.bu vrD, vrJ, vrK is op15_31=0xe16c & vrD & vrJ & vrK {\n\tvrD = vmaddwod.h.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.w.hu;\n\n#lsx.txt vmaddwod.w.hu mask=0x70b68000\t\n#0x70b68000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.w.hu vrD, vrJ, vrK is op15_31=0xe16d & vrD & vrJ & vrK {\n\tvrD = vmaddwod.w.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.d.wu;\n\n#lsx.txt vmaddwod.d.wu mask=0x70b70000\t\n#0x70b70000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.d.wu vrD, vrJ, vrK is op15_31=0xe16e & vrD & vrJ & vrK {\n\tvrD = vmaddwod.d.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.q.du;\n\n#lsx.txt vmaddwod.q.du mask=0x70b78000\t\n#0x70b78000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.q.du vrD, vrJ, vrK is op15_31=0xe16f & vrD & vrJ & vrK {\n\tvrD = vmaddwod.q.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.h.bu.b;\n\n#lsx.txt vmaddwev.h.bu.b mask=0x70bc0000\t\n#0x70bc0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.h.bu.b vrD, vrJ, vrK is op15_31=0xe178 & vrD & vrJ & vrK {\n\tvrD = vmaddwev.h.bu.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.w.hu.h;\n\n#lsx.txt vmaddwev.w.hu.h mask=0x70bc8000\t\n#0x70bc8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.w.hu.h vrD, vrJ, vrK is op15_31=0xe179 & vrD & vrJ & vrK {\n\tvrD = vmaddwev.w.hu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.d.wu.w;\n\n#lsx.txt vmaddwev.d.wu.w mask=0x70bd0000\t\n#0x70bd0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.d.wu.w vrD, vrJ, vrK is op15_31=0xe17a & vrD & vrJ & vrK {\n\tvrD = vmaddwev.d.wu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwev.q.du.d;\n\n#lsx.txt vmaddwev.q.du.d mask=0x70bd8000\t\n#0x70bd8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwev.q.du.d vrD, vrJ, vrK is op15_31=0xe17b & vrD & vrJ & vrK {\n\tvrD = vmaddwev.q.du.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.h.bu.b;\n\n#lsx.txt vmaddwod.h.bu.b mask=0x70be0000\t\n#0x70be0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.h.bu.b vrD, vrJ, vrK is op15_31=0xe17c & vrD & vrJ & vrK {\n\tvrD = vmaddwod.h.bu.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.w.hu.h;\n\n#lsx.txt vmaddwod.w.hu.h mask=0x70be8000\t\n#0x70be8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.w.hu.h vrD, vrJ, vrK is op15_31=0xe17d & vrD & vrJ & vrK {\n\tvrD = vmaddwod.w.hu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.d.wu.w;\n\n#lsx.txt vmaddwod.d.wu.w mask=0x70bf0000\t\n#0x70bf0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.d.wu.w vrD, vrJ, vrK is op15_31=0xe17e & vrD & vrJ & vrK {\n\tvrD = vmaddwod.d.wu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmaddwod.q.du.d;\n\n#lsx.txt vmaddwod.q.du.d mask=0x70bf8000\t\n#0x70bf8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmaddwod.q.du.d vrD, vrJ, vrK is op15_31=0xe17f & vrD & vrJ & vrK {\n\tvrD = vmaddwod.q.du.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.b;\n\n#lsx.txt vdiv.b mask=0x70e00000\t\n#0x70e00000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.b vrD, vrJ, vrK is op15_31=0xe1c0 & vrD & vrJ & vrK {\n\tvrD = vdiv.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.h;\n\n#lsx.txt vdiv.h mask=0x70e08000\t\n#0x70e08000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.h vrD, vrJ, vrK is op15_31=0xe1c1 & vrD & vrJ & vrK {\n\tvrD = vdiv.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.w;\n\n#lsx.txt vdiv.w mask=0x70e10000\t\n#0x70e10000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.w vrD, vrJ, vrK is op15_31=0xe1c2 & vrD & vrJ & vrK {\n\tvrD = vdiv.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.d;\n\n#lsx.txt vdiv.d mask=0x70e18000\t\n#0x70e18000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.d vrD, vrJ, vrK is op15_31=0xe1c3 & vrD & vrJ & vrK {\n\tvrD = vdiv.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.b;\n\n#lsx.txt vmod.b mask=0x70e20000\t\n#0x70e20000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.b vrD, vrJ, vrK is op15_31=0xe1c4 & vrD & vrJ & vrK {\n\tvrD = vmod.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.h;\n\n#lsx.txt vmod.h mask=0x70e28000\t\n#0x70e28000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.h vrD, vrJ, vrK is op15_31=0xe1c5 & vrD & vrJ & vrK {\n\tvrD = vmod.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.w;\n\n#lsx.txt vmod.w mask=0x70e30000\t\n#0x70e30000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.w vrD, vrJ, vrK is op15_31=0xe1c6 & vrD & vrJ & vrK {\n\tvrD = vmod.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.d;\n\n#lsx.txt vmod.d mask=0x70e38000\t\n#0x70e38000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.d vrD, vrJ, vrK is op15_31=0xe1c7 & vrD & vrJ & vrK {\n\tvrD = vmod.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.bu;\n\n#lsx.txt vdiv.bu mask=0x70e40000\t\n#0x70e40000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.bu vrD, vrJ, vrK is op15_31=0xe1c8 & vrD & vrJ & vrK {\n\tvrD = vdiv.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.hu;\n\n#lsx.txt vdiv.hu mask=0x70e48000\t\n#0x70e48000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.hu vrD, vrJ, vrK is op15_31=0xe1c9 & vrD & vrJ & vrK {\n\tvrD = vdiv.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.wu;\n\n#lsx.txt vdiv.wu mask=0x70e50000\t\n#0x70e50000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.wu vrD, vrJ, vrK is op15_31=0xe1ca & vrD & vrJ & vrK {\n\tvrD = vdiv.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vdiv.du;\n\n#lsx.txt vdiv.du mask=0x70e58000\t\n#0x70e58000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vdiv.du vrD, vrJ, vrK is op15_31=0xe1cb & vrD & vrJ & vrK {\n\tvrD = vdiv.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.bu;\n\n#lsx.txt vmod.bu mask=0x70e60000\t\n#0x70e60000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.bu vrD, vrJ, vrK is op15_31=0xe1cc & vrD & vrJ & vrK {\n\tvrD = vmod.bu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.hu;\n\n#lsx.txt vmod.hu mask=0x70e68000\t\n#0x70e68000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.hu vrD, vrJ, vrK is op15_31=0xe1cd & vrD & vrJ & vrK {\n\tvrD = vmod.hu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.wu;\n\n#lsx.txt vmod.wu mask=0x70e70000\t\n#0x70e70000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.wu vrD, vrJ, vrK is op15_31=0xe1ce & vrD & vrJ & vrK {\n\tvrD = vmod.wu(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vmod.du;\n\n#lsx.txt vmod.du mask=0x70e78000\t\n#0x70e78000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vmod.du vrD, vrJ, vrK is op15_31=0xe1cf & vrD & vrJ & vrK {\n\tvrD = vmod.du(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsll.b;\n\n#lsx.txt vsll.b mask=0x70e80000\t\n#0x70e80000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsll.b vrD, vrJ, vrK is op15_31=0xe1d0 & vrD & vrJ & vrK {\n\tvrD = vsll.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsll.h;\n\n#lsx.txt vsll.h mask=0x70e88000\t\n#0x70e88000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsll.h vrD, vrJ, vrK is op15_31=0xe1d1 & vrD & vrJ & vrK {\n\tvrD = vsll.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsll.w;\n\n#lsx.txt vsll.w mask=0x70e90000\t\n#0x70e90000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsll.w vrD, vrJ, vrK is op15_31=0xe1d2 & vrD & vrJ & vrK {\n\tvrD = vsll.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsll.d;\n\n#lsx.txt vsll.d mask=0x70e98000\t\n#0x70e98000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsll.d vrD, vrJ, vrK is op15_31=0xe1d3 & vrD & vrJ & vrK {\n\tvrD = vsll.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrl.b;\n\n#lsx.txt vsrl.b mask=0x70ea0000\t\n#0x70ea0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrl.b vrD, vrJ, vrK is op15_31=0xe1d4 & vrD & vrJ & vrK {\n\tvrD = vsrl.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrl.h;\n\n#lsx.txt vsrl.h mask=0x70ea8000\t\n#0x70ea8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrl.h vrD, vrJ, vrK is op15_31=0xe1d5 & vrD & vrJ & vrK {\n\tvrD = vsrl.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrl.w;\n\n#lsx.txt vsrl.w mask=0x70eb0000\t\n#0x70eb0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrl.w vrD, vrJ, vrK is op15_31=0xe1d6 & vrD & vrJ & vrK {\n\tvrD = vsrl.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrl.d;\n\n#lsx.txt vsrl.d mask=0x70eb8000\t\n#0x70eb8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrl.d vrD, vrJ, vrK is op15_31=0xe1d7 & vrD & vrJ & vrK {\n\tvrD = vsrl.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsra.b;\n\n#lsx.txt vsra.b mask=0x70ec0000\t\n#0x70ec0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsra.b vrD, vrJ, vrK is op15_31=0xe1d8 & vrD & vrJ & vrK {\n\tvrD = vsra.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsra.h;\n\n#lsx.txt vsra.h mask=0x70ec8000\t\n#0x70ec8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsra.h vrD, vrJ, vrK is op15_31=0xe1d9 & vrD & vrJ & vrK {\n\tvrD = vsra.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsra.w;\n\n#lsx.txt vsra.w mask=0x70ed0000\t\n#0x70ed0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsra.w vrD, vrJ, vrK is op15_31=0xe1da & vrD & vrJ & vrK {\n\tvrD = vsra.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsra.d;\n\n#lsx.txt vsra.d mask=0x70ed8000\t\n#0x70ed8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsra.d vrD, vrJ, vrK is op15_31=0xe1db & vrD & vrJ & vrK {\n\tvrD = vsra.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vrotr.b;\n\n#lsx.txt vrotr.b mask=0x70ee0000\t\n#0x70ee0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vrotr.b vrD, vrJ, vrK is op15_31=0xe1dc & vrD & vrJ & vrK {\n\tvrD = vrotr.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vrotr.h;\n\n#lsx.txt vrotr.h mask=0x70ee8000\t\n#0x70ee8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vrotr.h vrD, vrJ, vrK is op15_31=0xe1dd & vrD & vrJ & vrK {\n\tvrD = vrotr.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vrotr.w;\n\n#lsx.txt vrotr.w mask=0x70ef0000\t\n#0x70ef0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vrotr.w vrD, vrJ, vrK is op15_31=0xe1de & vrD & vrJ & vrK {\n\tvrD = vrotr.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vrotr.d;\n\n#lsx.txt vrotr.d mask=0x70ef8000\t\n#0x70ef8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vrotr.d vrD, vrJ, vrK is op15_31=0xe1df & vrD & vrJ & vrK {\n\tvrD = vrotr.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlr.b;\n\n#lsx.txt vsrlr.b mask=0x70f00000\t\n#0x70f00000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlr.b vrD, vrJ, vrK is op15_31=0xe1e0 & vrD & vrJ & vrK {\n\tvrD = vsrlr.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlr.h;\n\n#lsx.txt vsrlr.h mask=0x70f08000\t\n#0x70f08000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlr.h vrD, vrJ, vrK is op15_31=0xe1e1 & vrD & vrJ & vrK {\n\tvrD = vsrlr.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlr.w;\n\n#lsx.txt vsrlr.w mask=0x70f10000\t\n#0x70f10000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlr.w vrD, vrJ, vrK is op15_31=0xe1e2 & vrD & vrJ & vrK {\n\tvrD = vsrlr.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlr.d;\n\n#lsx.txt vsrlr.d mask=0x70f18000\t\n#0x70f18000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlr.d vrD, vrJ, vrK is op15_31=0xe1e3 & vrD & vrJ & vrK {\n\tvrD = vsrlr.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrar.b;\n\n#lsx.txt vsrar.b mask=0x70f20000\t\n#0x70f20000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrar.b vrD, vrJ, vrK is op15_31=0xe1e4 & vrD & vrJ & vrK {\n\tvrD = vsrar.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrar.h;\n\n#lsx.txt vsrar.h mask=0x70f28000\t\n#0x70f28000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrar.h vrD, vrJ, vrK is op15_31=0xe1e5 & vrD & vrJ & vrK {\n\tvrD = vsrar.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrar.w;\n\n#lsx.txt vsrar.w mask=0x70f30000\t\n#0x70f30000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrar.w vrD, vrJ, vrK is op15_31=0xe1e6 & vrD & vrJ & vrK {\n\tvrD = vsrar.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrar.d;\n\n#lsx.txt vsrar.d mask=0x70f38000\t\n#0x70f38000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrar.d vrD, vrJ, vrK is op15_31=0xe1e7 & vrD & vrJ & vrK {\n\tvrD = vsrar.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrln.b.h;\n\n#lsx.txt vsrln.b.h mask=0x70f48000\t\n#0x70f48000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrln.b.h vrD, vrJ, vrK is op15_31=0xe1e9 & vrD & vrJ & vrK {\n\tvrD = vsrln.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrln.h.w;\n\n#lsx.txt vsrln.h.w mask=0x70f50000\t\n#0x70f50000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrln.h.w vrD, vrJ, vrK is op15_31=0xe1ea & vrD & vrJ & vrK {\n\tvrD = vsrln.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrln.w.d;\n\n#lsx.txt vsrln.w.d mask=0x70f58000\t\n#0x70f58000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrln.w.d vrD, vrJ, vrK is op15_31=0xe1eb & vrD & vrJ & vrK {\n\tvrD = vsrln.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsran.b.h;\n\n#lsx.txt vsran.b.h mask=0x70f68000\t\n#0x70f68000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsran.b.h vrD, vrJ, vrK is op15_31=0xe1ed & vrD & vrJ & vrK {\n\tvrD = vsran.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsran.h.w;\n\n#lsx.txt vsran.h.w mask=0x70f70000\t\n#0x70f70000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsran.h.w vrD, vrJ, vrK is op15_31=0xe1ee & vrD & vrJ & vrK {\n\tvrD = vsran.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsran.w.d;\n\n#lsx.txt vsran.w.d mask=0x70f78000\t\n#0x70f78000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsran.w.d vrD, vrJ, vrK is op15_31=0xe1ef & vrD & vrJ & vrK {\n\tvrD = vsran.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlrn.b.h;\n\n#lsx.txt vsrlrn.b.h mask=0x70f88000\t\n#0x70f88000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlrn.b.h vrD, vrJ, vrK is op15_31=0xe1f1 & vrD & vrJ & vrK {\n\tvrD = vsrlrn.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlrn.h.w;\n\n#lsx.txt vsrlrn.h.w mask=0x70f90000\t\n#0x70f90000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlrn.h.w vrD, vrJ, vrK is op15_31=0xe1f2 & vrD & vrJ & vrK {\n\tvrD = vsrlrn.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrlrn.w.d;\n\n#lsx.txt vsrlrn.w.d mask=0x70f98000\t\n#0x70f98000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrlrn.w.d vrD, vrJ, vrK is op15_31=0xe1f3 & vrD & vrJ & vrK {\n\tvrD = vsrlrn.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrarn.b.h;\n\n#lsx.txt vsrarn.b.h mask=0x70fa8000\t\n#0x70fa8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrarn.b.h vrD, vrJ, vrK is op15_31=0xe1f5 & vrD & vrJ & vrK {\n\tvrD = vsrarn.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrarn.h.w;\n\n#lsx.txt vsrarn.h.w mask=0x70fb0000\t\n#0x70fb0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrarn.h.w vrD, vrJ, vrK is op15_31=0xe1f6 & vrD & vrJ & vrK {\n\tvrD = vsrarn.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsrarn.w.d;\n\n#lsx.txt vsrarn.w.d mask=0x70fb8000\t\n#0x70fb8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsrarn.w.d vrD, vrJ, vrK is op15_31=0xe1f7 & vrD & vrJ & vrK {\n\tvrD = vsrarn.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrln.b.h;\n\n#lsx.txt vssrln.b.h mask=0x70fc8000\t\n#0x70fc8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrln.b.h vrD, vrJ, vrK is op15_31=0xe1f9 & vrD & vrJ & vrK {\n\tvrD = vssrln.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrln.h.w;\n\n#lsx.txt vssrln.h.w mask=0x70fd0000\t\n#0x70fd0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrln.h.w vrD, vrJ, vrK is op15_31=0xe1fa & vrD & vrJ & vrK {\n\tvrD = vssrln.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrln.w.d;\n\n#lsx.txt vssrln.w.d mask=0x70fd8000\t\n#0x70fd8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrln.w.d vrD, vrJ, vrK is op15_31=0xe1fb & vrD & vrJ & vrK {\n\tvrD = vssrln.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssran.b.h;\n\n#lsx.txt vssran.b.h mask=0x70fe8000\t\n#0x70fe8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssran.b.h vrD, vrJ, vrK is op15_31=0xe1fd & vrD & vrJ & vrK {\n\tvrD = vssran.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssran.h.w;\n\n#lsx.txt vssran.h.w mask=0x70ff0000\t\n#0x70ff0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssran.h.w vrD, vrJ, vrK is op15_31=0xe1fe & vrD & vrJ & vrK {\n\tvrD = vssran.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssran.w.d;\n\n#lsx.txt vssran.w.d mask=0x70ff8000\t\n#0x70ff8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssran.w.d vrD, vrJ, vrK is op15_31=0xe1ff & vrD & vrJ & vrK {\n\tvrD = vssran.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrlrn.b.h;\n\n#lsx.txt vssrlrn.b.h mask=0x71008000\t\n#0x71008000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrlrn.b.h vrD, vrJ, vrK is op15_31=0xe201 & vrD & vrJ & vrK {\n\tvrD = vssrlrn.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrlrn.h.w;\n\n#lsx.txt vssrlrn.h.w mask=0x71010000\t\n#0x71010000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrlrn.h.w vrD, vrJ, vrK is op15_31=0xe202 & vrD & vrJ & vrK {\n\tvrD = vssrlrn.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrlrn.w.d;\n\n#lsx.txt vssrlrn.w.d mask=0x71018000\t\n#0x71018000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrlrn.w.d vrD, vrJ, vrK is op15_31=0xe203 & vrD & vrJ & vrK {\n\tvrD = vssrlrn.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrarn.b.h;\n\n#lsx.txt vssrarn.b.h mask=0x71028000\t\n#0x71028000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrarn.b.h vrD, vrJ, vrK is op15_31=0xe205 & vrD & vrJ & vrK {\n\tvrD = vssrarn.b.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrarn.h.w;\n\n#lsx.txt vssrarn.h.w mask=0x71030000\t\n#0x71030000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrarn.h.w vrD, vrJ, vrK is op15_31=0xe206 & vrD & vrJ & vrK {\n\tvrD = vssrarn.h.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrarn.w.d;\n\n#lsx.txt vssrarn.w.d mask=0x71038000\t\n#0x71038000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrarn.w.d vrD, vrJ, vrK is op15_31=0xe207 & vrD & vrJ & vrK {\n\tvrD = vssrarn.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrln.bu.h;\n\n#lsx.txt vssrln.bu.h mask=0x71048000\t\n#0x71048000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrln.bu.h vrD, vrJ, vrK is op15_31=0xe209 & vrD & vrJ & vrK {\n\tvrD = vssrln.bu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrln.hu.w;\n\n#lsx.txt vssrln.hu.w mask=0x71050000\t\n#0x71050000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrln.hu.w vrD, vrJ, vrK is op15_31=0xe20a & vrD & vrJ & vrK {\n\tvrD = vssrln.hu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrln.wu.d;\n\n#lsx.txt vssrln.wu.d mask=0x71058000\t\n#0x71058000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrln.wu.d vrD, vrJ, vrK is op15_31=0xe20b & vrD & vrJ & vrK {\n\tvrD = vssrln.wu.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssran.bu.h;\n\n#lsx.txt vssran.bu.h mask=0x71068000\t\n#0x71068000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssran.bu.h vrD, vrJ, vrK is op15_31=0xe20d & vrD & vrJ & vrK {\n\tvrD = vssran.bu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssran.hu.w;\n\n#lsx.txt vssran.hu.w mask=0x71070000\t\n#0x71070000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssran.hu.w vrD, vrJ, vrK is op15_31=0xe20e & vrD & vrJ & vrK {\n\tvrD = vssran.hu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssran.wu.d;\n\n#lsx.txt vssran.wu.d mask=0x71078000\t\n#0x71078000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssran.wu.d vrD, vrJ, vrK is op15_31=0xe20f & vrD & vrJ & vrK {\n\tvrD = vssran.wu.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrlrn.bu.h;\n\n#lsx.txt vssrlrn.bu.h mask=0x71088000\t\n#0x71088000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrlrn.bu.h vrD, vrJ, vrK is op15_31=0xe211 & vrD & vrJ & vrK {\n\tvrD = vssrlrn.bu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrlrn.hu.w;\n\n#lsx.txt vssrlrn.hu.w mask=0x71090000\t\n#0x71090000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrlrn.hu.w vrD, vrJ, vrK is op15_31=0xe212 & vrD & vrJ & vrK {\n\tvrD = vssrlrn.hu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrlrn.wu.d;\n\n#lsx.txt vssrlrn.wu.d mask=0x71098000\t\n#0x71098000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrlrn.wu.d vrD, vrJ, vrK is op15_31=0xe213 & vrD & vrJ & vrK {\n\tvrD = vssrlrn.wu.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrarn.bu.h;\n\n#lsx.txt vssrarn.bu.h mask=0x710a8000\t\n#0x710a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrarn.bu.h vrD, vrJ, vrK is op15_31=0xe215 & vrD & vrJ & vrK {\n\tvrD = vssrarn.bu.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrarn.hu.w;\n\n#lsx.txt vssrarn.hu.w mask=0x710b0000\t\n#0x710b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrarn.hu.w vrD, vrJ, vrK is op15_31=0xe216 & vrD & vrJ & vrK {\n\tvrD = vssrarn.hu.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vssrarn.wu.d;\n\n#lsx.txt vssrarn.wu.d mask=0x710b8000\t\n#0x710b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vssrarn.wu.d vrD, vrJ, vrK is op15_31=0xe217 & vrD & vrJ & vrK {\n\tvrD = vssrarn.wu.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitclr.b;\n\n#lsx.txt vbitclr.b mask=0x710c0000\t\n#0x710c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitclr.b vrD, vrJ, vrK is op15_31=0xe218 & vrD & vrJ & vrK {\n\tvrD = vbitclr.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitclr.h;\n\n#lsx.txt vbitclr.h mask=0x710c8000\t\n#0x710c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitclr.h vrD, vrJ, vrK is op15_31=0xe219 & vrD & vrJ & vrK {\n\tvrD = vbitclr.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitclr.w;\n\n#lsx.txt vbitclr.w mask=0x710d0000\t\n#0x710d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitclr.w vrD, vrJ, vrK is op15_31=0xe21a & vrD & vrJ & vrK {\n\tvrD = vbitclr.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitclr.d;\n\n#lsx.txt vbitclr.d mask=0x710d8000\t\n#0x710d8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitclr.d vrD, vrJ, vrK is op15_31=0xe21b & vrD & vrJ & vrK {\n\tvrD = vbitclr.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitset.b;\n\n#lsx.txt vbitset.b mask=0x710e0000\t\n#0x710e0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitset.b vrD, vrJ, vrK is op15_31=0xe21c & vrD & vrJ & vrK {\n\tvrD = vbitset.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitset.h;\n\n#lsx.txt vbitset.h mask=0x710e8000\t\n#0x710e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitset.h vrD, vrJ, vrK is op15_31=0xe21d & vrD & vrJ & vrK {\n\tvrD = vbitset.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitset.w;\n\n#lsx.txt vbitset.w mask=0x710f0000\t\n#0x710f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitset.w vrD, vrJ, vrK is op15_31=0xe21e & vrD & vrJ & vrK {\n\tvrD = vbitset.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitset.d;\n\n#lsx.txt vbitset.d mask=0x710f8000\t\n#0x710f8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitset.d vrD, vrJ, vrK is op15_31=0xe21f & vrD & vrJ & vrK {\n\tvrD = vbitset.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitrev.b;\n\n#lsx.txt vbitrev.b mask=0x71100000\t\n#0x71100000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitrev.b vrD, vrJ, vrK is op15_31=0xe220 & vrD & vrJ & vrK {\n\tvrD = vbitrev.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitrev.h;\n\n#lsx.txt vbitrev.h mask=0x71108000\t\n#0x71108000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitrev.h vrD, vrJ, vrK is op15_31=0xe221 & vrD & vrJ & vrK {\n\tvrD = vbitrev.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitrev.w;\n\n#lsx.txt vbitrev.w mask=0x71110000\t\n#0x71110000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitrev.w vrD, vrJ, vrK is op15_31=0xe222 & vrD & vrJ & vrK {\n\tvrD = vbitrev.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vbitrev.d;\n\n#lsx.txt vbitrev.d mask=0x71118000\t\n#0x71118000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vbitrev.d vrD, vrJ, vrK is op15_31=0xe223 & vrD & vrJ & vrK {\n\tvrD = vbitrev.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackev.b;\n\n#lsx.txt vpackev.b mask=0x71160000\t\n#0x71160000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackev.b vrD, vrJ, vrK is op15_31=0xe22c & vrD & vrJ & vrK {\n\tvrD = vpackev.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackev.h;\n\n#lsx.txt vpackev.h mask=0x71168000\t\n#0x71168000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackev.h vrD, vrJ, vrK is op15_31=0xe22d & vrD & vrJ & vrK {\n\tvrD = vpackev.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackev.w;\n\n#lsx.txt vpackev.w mask=0x71170000\t\n#0x71170000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackev.w vrD, vrJ, vrK is op15_31=0xe22e & vrD & vrJ & vrK {\n\tvrD = vpackev.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackev.d;\n\n#lsx.txt vpackev.d mask=0x71178000\t\n#0x71178000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackev.d vrD, vrJ, vrK is op15_31=0xe22f & vrD & vrJ & vrK {\n\tvrD = vpackev.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackod.b;\n\n#lsx.txt vpackod.b mask=0x71180000\t\n#0x71180000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackod.b vrD, vrJ, vrK is op15_31=0xe230 & vrD & vrJ & vrK {\n\tvrD = vpackod.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackod.h;\n\n#lsx.txt vpackod.h mask=0x71188000\t\n#0x71188000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackod.h vrD, vrJ, vrK is op15_31=0xe231 & vrD & vrJ & vrK {\n\tvrD = vpackod.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackod.w;\n\n#lsx.txt vpackod.w mask=0x71190000\t\n#0x71190000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackod.w vrD, vrJ, vrK is op15_31=0xe232 & vrD & vrJ & vrK {\n\tvrD = vpackod.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpackod.d;\n\n#lsx.txt vpackod.d mask=0x71198000\t\n#0x71198000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpackod.d vrD, vrJ, vrK is op15_31=0xe233 & vrD & vrJ & vrK {\n\tvrD = vpackod.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvl.b;\n\n#lsx.txt vilvl.b mask=0x711a0000\t\n#0x711a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvl.b vrD, vrJ, vrK is op15_31=0xe234 & vrD & vrJ & vrK {\n\tvrD = vilvl.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvl.h;\n\n#lsx.txt vilvl.h mask=0x711a8000\t\n#0x711a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvl.h vrD, vrJ, vrK is op15_31=0xe235 & vrD & vrJ & vrK {\n\tvrD = vilvl.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvl.w;\n\n#lsx.txt vilvl.w mask=0x711b0000\t\n#0x711b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvl.w vrD, vrJ, vrK is op15_31=0xe236 & vrD & vrJ & vrK {\n\tvrD = vilvl.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvl.d;\n\n#lsx.txt vilvl.d mask=0x711b8000\t\n#0x711b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvl.d vrD, vrJ, vrK is op15_31=0xe237 & vrD & vrJ & vrK {\n\tvrD = vilvl.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvh.b;\n\n#lsx.txt vilvh.b mask=0x711c0000\t\n#0x711c0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvh.b vrD, vrJ, vrK is op15_31=0xe238 & vrD & vrJ & vrK {\n\tvrD = vilvh.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvh.h;\n\n#lsx.txt vilvh.h mask=0x711c8000\t\n#0x711c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvh.h vrD, vrJ, vrK is op15_31=0xe239 & vrD & vrJ & vrK {\n\tvrD = vilvh.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvh.w;\n\n#lsx.txt vilvh.w mask=0x711d0000\t\n#0x711d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvh.w vrD, vrJ, vrK is op15_31=0xe23a & vrD & vrJ & vrK {\n\tvrD = vilvh.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vilvh.d;\n\n#lsx.txt vilvh.d mask=0x711d8000\t\n#0x711d8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vilvh.d vrD, vrJ, vrK is op15_31=0xe23b & vrD & vrJ & vrK {\n\tvrD = vilvh.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickev.b;\n\n#lsx.txt vpickev.b mask=0x711e0000\t\n#0x711e0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickev.b vrD, vrJ, vrK is op15_31=0xe23c & vrD & vrJ & vrK {\n\tvrD = vpickev.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickev.h;\n\n#lsx.txt vpickev.h mask=0x711e8000\t\n#0x711e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickev.h vrD, vrJ, vrK is op15_31=0xe23d & vrD & vrJ & vrK {\n\tvrD = vpickev.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickev.w;\n\n#lsx.txt vpickev.w mask=0x711f0000\t\n#0x711f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickev.w vrD, vrJ, vrK is op15_31=0xe23e & vrD & vrJ & vrK {\n\tvrD = vpickev.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickev.d;\n\n#lsx.txt vpickev.d mask=0x711f8000\t\n#0x711f8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickev.d vrD, vrJ, vrK is op15_31=0xe23f & vrD & vrJ & vrK {\n\tvrD = vpickev.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickod.b;\n\n#lsx.txt vpickod.b mask=0x71200000\t\n#0x71200000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickod.b vrD, vrJ, vrK is op15_31=0xe240 & vrD & vrJ & vrK {\n\tvrD = vpickod.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickod.h;\n\n#lsx.txt vpickod.h mask=0x71208000\t\n#0x71208000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickod.h vrD, vrJ, vrK is op15_31=0xe241 & vrD & vrJ & vrK {\n\tvrD = vpickod.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickod.w;\n\n#lsx.txt vpickod.w mask=0x71210000\t\n#0x71210000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickod.w vrD, vrJ, vrK is op15_31=0xe242 & vrD & vrJ & vrK {\n\tvrD = vpickod.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vpickod.d;\n\n#lsx.txt vpickod.d mask=0x71218000\t\n#0x71218000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vpickod.d vrD, vrJ, vrK is op15_31=0xe243 & vrD & vrJ & vrK {\n\tvrD = vpickod.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vreplve.b;\n\n#lsx.txt vreplve.b mask=0x71220000\t\n#0x71220000\t0xffff8000\tv0:5,v5:5, r10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0']\n:vreplve.b vrD, vrJ, RKsrc is op15_31=0xe244 & vrD & vrJ & RKsrc {\n\tvrD = vreplve.b(vrD, vrJ, RKsrc);\n}\n\ndefine pcodeop vreplve.h;\n\n#lsx.txt vreplve.h mask=0x71228000\t\n#0x71228000\t0xffff8000\tv0:5,v5:5, r10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0']\n:vreplve.h vrD, vrJ, RKsrc is op15_31=0xe245 & vrD & vrJ & RKsrc {\n\tvrD = vreplve.h(vrD, vrJ, RKsrc);\n}\n\ndefine pcodeop vreplve.w;\n\n#lsx.txt vreplve.w mask=0x71230000\t\n#0x71230000\t0xffff8000\tv0:5,v5:5, r10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0']\n:vreplve.w vrD, vrJ, RKsrc is op15_31=0xe246 & vrD & vrJ & RKsrc {\n\tvrD = vreplve.w(vrD, vrJ, RKsrc);\n}\n\ndefine pcodeop vreplve.d;\n\n#lsx.txt vreplve.d mask=0x71238000\t\n#0x71238000\t0xffff8000\tv0:5,v5:5, r10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0']\n:vreplve.d vrD, vrJ, RKsrc is op15_31=0xe247 & vrD & vrJ & RKsrc {\n\tvrD = vreplve.d(vrD, vrJ, RKsrc);\n}\n\ndefine pcodeop vand.v;\n\n#lsx.txt vand.v mask=0x71260000\t\n#0x71260000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vand.v vrD, vrJ, vrK is op15_31=0xe24c & vrD & vrJ & vrK {\n\tvrD = vand.v(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vor.v;\n\n#lsx.txt vor.v mask=0x71268000\t\n#0x71268000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vor.v vrD, vrJ, vrK is op15_31=0xe24d & vrD & vrJ & vrK {\n\tvrD = vor.v(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vxor.v;\n\n#lsx.txt vxor.v mask=0x71270000\t\n#0x71270000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vxor.v vrD, vrJ, vrK is op15_31=0xe24e & vrD & vrJ & vrK {\n\tvrD = vxor.v(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vnor.v;\n\n#lsx.txt vnor.v mask=0x71278000\t\n#0x71278000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vnor.v vrD, vrJ, vrK is op15_31=0xe24f & vrD & vrJ & vrK {\n\tvrD = vnor.v(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vandn.v;\n\n#lsx.txt vandn.v mask=0x71280000\t\n#0x71280000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vandn.v vrD, vrJ, vrK is op15_31=0xe250 & vrD & vrJ & vrK {\n\tvrD = vandn.v(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vorn.v;\n\n#lsx.txt vorn.v mask=0x71288000\t\n#0x71288000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vorn.v vrD, vrJ, vrK is op15_31=0xe251 & vrD & vrJ & vrK {\n\tvrD = vorn.v(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfrstp.b;\n\n#lsx.txt vfrstp.b mask=0x712b0000\t\n#0x712b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfrstp.b vrD, vrJ, vrK is op15_31=0xe256 & vrD & vrJ & vrK {\n\tvrD = vfrstp.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfrstp.h;\n\n#lsx.txt vfrstp.h mask=0x712b8000\t\n#0x712b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfrstp.h vrD, vrJ, vrK is op15_31=0xe257 & vrD & vrJ & vrK {\n\tvrD = vfrstp.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vadd.q;\n\n#lsx.txt vadd.q mask=0x712d0000\t\n#0x712d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vadd.q vrD, vrJ, vrK is op15_31=0xe25a & vrD & vrJ & vrK {\n\tvrD = vadd.q(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsub.q;\n\n#lsx.txt vsub.q mask=0x712d8000\t\n#0x712d8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsub.q vrD, vrJ, vrK is op15_31=0xe25b & vrD & vrJ & vrK {\n\tvrD = vsub.q(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsigncov.b;\n\n#lsx.txt vsigncov.b mask=0x712e0000\t\n#0x712e0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsigncov.b vrD, vrJ, vrK is op15_31=0xe25c & vrD & vrJ & vrK {\n\tvrD = vsigncov.b(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsigncov.h;\n\n#lsx.txt vsigncov.h mask=0x712e8000\t\n#0x712e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsigncov.h vrD, vrJ, vrK is op15_31=0xe25d & vrD & vrJ & vrK {\n\tvrD = vsigncov.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsigncov.w;\n\n#lsx.txt vsigncov.w mask=0x712f0000\t\n#0x712f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsigncov.w vrD, vrJ, vrK is op15_31=0xe25e & vrD & vrJ & vrK {\n\tvrD = vsigncov.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vsigncov.d;\n\n#lsx.txt vsigncov.d mask=0x712f8000\t\n#0x712f8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vsigncov.d vrD, vrJ, vrK is op15_31=0xe25f & vrD & vrJ & vrK {\n\tvrD = vsigncov.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfadd.s;\n\n#lsx.txt vfadd.s mask=0x71308000\t\n#0x71308000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfadd.s vrD, vrJ, vrK is op15_31=0xe261 & vrD & vrJ & vrK {\n\tvrD = vfadd.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfadd.d;\n\n#lsx.txt vfadd.d mask=0x71310000\t\n#0x71310000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfadd.d vrD, vrJ, vrK is op15_31=0xe262 & vrD & vrJ & vrK {\n\tvrD = vfadd.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfsub.s;\n\n#lsx.txt vfsub.s mask=0x71328000\t\n#0x71328000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfsub.s vrD, vrJ, vrK is op15_31=0xe265 & vrD & vrJ & vrK {\n\tvrD = vfsub.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfsub.d;\n\n#lsx.txt vfsub.d mask=0x71330000\t\n#0x71330000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfsub.d vrD, vrJ, vrK is op15_31=0xe266 & vrD & vrJ & vrK {\n\tvrD = vfsub.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmul.s;\n\n#lsx.txt vfmul.s mask=0x71388000\t\n#0x71388000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmul.s vrD, vrJ, vrK is op15_31=0xe271 & vrD & vrJ & vrK {\n\tvrD = vfmul.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmul.d;\n\n#lsx.txt vfmul.d mask=0x71390000\t\n#0x71390000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmul.d vrD, vrJ, vrK is op15_31=0xe272 & vrD & vrJ & vrK {\n\tvrD = vfmul.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfdiv.s;\n\n#lsx.txt vfdiv.s mask=0x713a8000\t\n#0x713a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfdiv.s vrD, vrJ, vrK is op15_31=0xe275 & vrD & vrJ & vrK {\n\tvrD = vfdiv.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfdiv.d;\n\n#lsx.txt vfdiv.d mask=0x713b0000\t\n#0x713b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfdiv.d vrD, vrJ, vrK is op15_31=0xe276 & vrD & vrJ & vrK {\n\tvrD = vfdiv.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmax.s;\n\n#lsx.txt vfmax.s mask=0x713c8000\t\n#0x713c8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmax.s vrD, vrJ, vrK is op15_31=0xe279 & vrD & vrJ & vrK {\n\tvrD = vfmax.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmax.d;\n\n#lsx.txt vfmax.d mask=0x713d0000\t\n#0x713d0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmax.d vrD, vrJ, vrK is op15_31=0xe27a & vrD & vrJ & vrK {\n\tvrD = vfmax.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmin.s;\n\n#lsx.txt vfmin.s mask=0x713e8000\t\n#0x713e8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmin.s vrD, vrJ, vrK is op15_31=0xe27d & vrD & vrJ & vrK {\n\tvrD = vfmin.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmin.d;\n\n#lsx.txt vfmin.d mask=0x713f0000\t\n#0x713f0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmin.d vrD, vrJ, vrK is op15_31=0xe27e & vrD & vrJ & vrK {\n\tvrD = vfmin.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmaxa.s;\n\n#lsx.txt vfmaxa.s mask=0x71408000\t\n#0x71408000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmaxa.s vrD, vrJ, vrK is op15_31=0xe281 & vrD & vrJ & vrK {\n\tvrD = vfmaxa.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmaxa.d;\n\n#lsx.txt vfmaxa.d mask=0x71410000\t\n#0x71410000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmaxa.d vrD, vrJ, vrK is op15_31=0xe282 & vrD & vrJ & vrK {\n\tvrD = vfmaxa.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmina.s;\n\n#lsx.txt vfmina.s mask=0x71428000\t\n#0x71428000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmina.s vrD, vrJ, vrK is op15_31=0xe285 & vrD & vrJ & vrK {\n\tvrD = vfmina.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfmina.d;\n\n#lsx.txt vfmina.d mask=0x71430000\t\n#0x71430000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfmina.d vrD, vrJ, vrK is op15_31=0xe286 & vrD & vrJ & vrK {\n\tvrD = vfmina.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcvt.h.s;\n\n#lsx.txt vfcvt.h.s mask=0x71460000\t\n#0x71460000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcvt.h.s vrD, vrJ, vrK is op15_31=0xe28c & vrD & vrJ & vrK {\n\tvrD = vfcvt.h.s(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vfcvt.s.d;\n\n#lsx.txt vfcvt.s.d mask=0x71468000\t\n#0x71468000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vfcvt.s.d vrD, vrJ, vrK is op15_31=0xe28d & vrD & vrJ & vrK {\n\tvrD = vfcvt.s.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vffint.s.l;\n\n#lsx.txt vffint.s.l mask=0x71480000\t\n#0x71480000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vffint.s.l vrD, vrJ, vrK is op15_31=0xe290 & vrD & vrJ & vrK {\n\tvrD = vffint.s.l(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vftint.w.d;\n\n#lsx.txt vftint.w.d mask=0x71498000\t\n#0x71498000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vftint.w.d vrD, vrJ, vrK is op15_31=0xe293 & vrD & vrJ & vrK {\n\tvrD = vftint.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vftintrm.w.d;\n\n#lsx.txt vftintrm.w.d mask=0x714a0000\t\n#0x714a0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vftintrm.w.d vrD, vrJ, vrK is op15_31=0xe294 & vrD & vrJ & vrK {\n\tvrD = vftintrm.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vftintrp.w.d;\n\n#lsx.txt vftintrp.w.d mask=0x714a8000\t\n#0x714a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vftintrp.w.d vrD, vrJ, vrK is op15_31=0xe295 & vrD & vrJ & vrK {\n\tvrD = vftintrp.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vftintrz.w.d;\n\n#lsx.txt vftintrz.w.d mask=0x714b0000\t\n#0x714b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vftintrz.w.d vrD, vrJ, vrK is op15_31=0xe296 & vrD & vrJ & vrK {\n\tvrD = vftintrz.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vftintrne.w.d;\n\n#lsx.txt vftintrne.w.d mask=0x714b8000\t\n#0x714b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vftintrne.w.d vrD, vrJ, vrK is op15_31=0xe297 & vrD & vrJ & vrK {\n\tvrD = vftintrne.w.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vshuf.h;\n\n#lsx.txt vshuf.h mask=0x717a8000\t\n#0x717a8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vshuf.h vrD, vrJ, vrK is op15_31=0xe2f5 & vrD & vrJ & vrK {\n\tvrD = vshuf.h(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vshuf.w;\n\n#lsx.txt vshuf.w mask=0x717b0000\t\n#0x717b0000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vshuf.w vrD, vrJ, vrK is op15_31=0xe2f6 & vrD & vrJ & vrK {\n\tvrD = vshuf.w(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vshuf.d;\n\n#lsx.txt vshuf.d mask=0x717b8000\t\n#0x717b8000\t0xffff8000\tv0:5,v5:5,v10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0']\n:vshuf.d vrD, vrJ, vrK is op15_31=0xe2f7 & vrD & vrJ & vrK {\n\tvrD = vshuf.d(vrD, vrJ, vrK);\n}\n\ndefine pcodeop vseqi.b;\n\n#lsx.txt vseqi.b mask=0x72800000\t\n#0x72800000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vseqi.b vrD, vrJ, simm10_5 is op15_31=0xe500 & vrD & vrJ & simm10_5 {\n\tvrD = vseqi.b(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vseqi.h;\n\n#lsx.txt vseqi.h mask=0x72808000\t\n#0x72808000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vseqi.h vrD, vrJ, simm10_5 is op15_31=0xe501 & vrD & vrJ & simm10_5 {\n\tvrD = vseqi.h(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vseqi.w;\n\n#lsx.txt vseqi.w mask=0x72810000\t\n#0x72810000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vseqi.w vrD, vrJ, simm10_5 is op15_31=0xe502 & vrD & vrJ & simm10_5 {\n\tvrD = vseqi.w(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vseqi.d;\n\n#lsx.txt vseqi.d mask=0x72818000\t\n#0x72818000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vseqi.d vrD, vrJ, simm10_5 is op15_31=0xe503 & vrD & vrJ & simm10_5 {\n\tvrD = vseqi.d(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.b;\n\n#lsx.txt vslei.b mask=0x72820000\t\n#0x72820000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslei.b vrD, vrJ, simm10_5 is op15_31=0xe504 & vrD & vrJ & simm10_5 {\n\tvrD = vslei.b(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.h;\n\n#lsx.txt vslei.h mask=0x72828000\t\n#0x72828000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslei.h vrD, vrJ, simm10_5 is op15_31=0xe505 & vrD & vrJ & simm10_5 {\n\tvrD = vslei.h(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.w;\n\n#lsx.txt vslei.w mask=0x72830000\t\n#0x72830000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslei.w vrD, vrJ, simm10_5 is op15_31=0xe506 & vrD & vrJ & simm10_5 {\n\tvrD = vslei.w(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.d;\n\n#lsx.txt vslei.d mask=0x72838000\t\n#0x72838000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslei.d vrD, vrJ, simm10_5 is op15_31=0xe507 & vrD & vrJ & simm10_5 {\n\tvrD = vslei.d(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.bu;\n\n#lsx.txt vslei.bu mask=0x72840000\t\n#0x72840000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslei.bu vrD, vrJ, imm10_5 is op15_31=0xe508 & vrD & vrJ & imm10_5 {\n\tvrD = vslei.bu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.hu;\n\n#lsx.txt vslei.hu mask=0x72848000\t\n#0x72848000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslei.hu vrD, vrJ, imm10_5 is op15_31=0xe509 & vrD & vrJ & imm10_5 {\n\tvrD = vslei.hu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.wu;\n\n#lsx.txt vslei.wu mask=0x72850000\t\n#0x72850000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslei.wu vrD, vrJ, imm10_5 is op15_31=0xe50a & vrD & vrJ & imm10_5 {\n\tvrD = vslei.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslei.du;\n\n#lsx.txt vslei.du mask=0x72858000\t\n#0x72858000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslei.du vrD, vrJ, imm10_5 is op15_31=0xe50b & vrD & vrJ & imm10_5 {\n\tvrD = vslei.du(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.b;\n\n#lsx.txt vslti.b mask=0x72860000\t\n#0x72860000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslti.b vrD, vrJ, simm10_5 is op15_31=0xe50c & vrD & vrJ & simm10_5 {\n\tvrD = vslti.b(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.h;\n\n#lsx.txt vslti.h mask=0x72868000\t\n#0x72868000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslti.h vrD, vrJ, simm10_5 is op15_31=0xe50d & vrD & vrJ & simm10_5 {\n\tvrD = vslti.h(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.w;\n\n#lsx.txt vslti.w mask=0x72870000\t\n#0x72870000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslti.w vrD, vrJ, simm10_5 is op15_31=0xe50e & vrD & vrJ & simm10_5 {\n\tvrD = vslti.w(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.d;\n\n#lsx.txt vslti.d mask=0x72878000\t\n#0x72878000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vslti.d vrD, vrJ, simm10_5 is op15_31=0xe50f & vrD & vrJ & simm10_5 {\n\tvrD = vslti.d(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.bu;\n\n#lsx.txt vslti.bu mask=0x72880000\t\n#0x72880000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslti.bu vrD, vrJ, imm10_5 is op15_31=0xe510 & vrD & vrJ & imm10_5 {\n\tvrD = vslti.bu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.hu;\n\n#lsx.txt vslti.hu mask=0x72888000\t\n#0x72888000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslti.hu vrD, vrJ, imm10_5 is op15_31=0xe511 & vrD & vrJ & imm10_5 {\n\tvrD = vslti.hu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.wu;\n\n#lsx.txt vslti.wu mask=0x72890000\t\n#0x72890000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslti.wu vrD, vrJ, imm10_5 is op15_31=0xe512 & vrD & vrJ & imm10_5 {\n\tvrD = vslti.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslti.du;\n\n#lsx.txt vslti.du mask=0x72898000\t\n#0x72898000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslti.du vrD, vrJ, imm10_5 is op15_31=0xe513 & vrD & vrJ & imm10_5 {\n\tvrD = vslti.du(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vaddi.bu;\n\n#lsx.txt vaddi.bu mask=0x728a0000\t\n#0x728a0000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vaddi.bu vrD, vrJ, imm10_5 is op15_31=0xe514 & vrD & vrJ & imm10_5 {\n\tvrD = vaddi.bu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vaddi.hu;\n\n#lsx.txt vaddi.hu mask=0x728a8000\t\n#0x728a8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vaddi.hu vrD, vrJ, imm10_5 is op15_31=0xe515 & vrD & vrJ & imm10_5 {\n\tvrD = vaddi.hu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vaddi.wu;\n\n#lsx.txt vaddi.wu mask=0x728b0000\t\n#0x728b0000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vaddi.wu vrD, vrJ, imm10_5 is op15_31=0xe516 & vrD & vrJ & imm10_5 {\n\tvrD = vaddi.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vaddi.du;\n\n#lsx.txt vaddi.du mask=0x728b8000\t\n#0x728b8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vaddi.du vrD, vrJ, imm10_5 is op15_31=0xe517 & vrD & vrJ & imm10_5 {\n\tvrD = vaddi.du(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsubi.bu;\n\n#lsx.txt vsubi.bu mask=0x728c0000\t\n#0x728c0000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsubi.bu vrD, vrJ, imm10_5 is op15_31=0xe518 & vrD & vrJ & imm10_5 {\n\tvrD = vsubi.bu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsubi.hu;\n\n#lsx.txt vsubi.hu mask=0x728c8000\t\n#0x728c8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsubi.hu vrD, vrJ, imm10_5 is op15_31=0xe519 & vrD & vrJ & imm10_5 {\n\tvrD = vsubi.hu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsubi.wu;\n\n#lsx.txt vsubi.wu mask=0x728d0000\t\n#0x728d0000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsubi.wu vrD, vrJ, imm10_5 is op15_31=0xe51a & vrD & vrJ & imm10_5 {\n\tvrD = vsubi.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsubi.du;\n\n#lsx.txt vsubi.du mask=0x728d8000\t\n#0x728d8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsubi.du vrD, vrJ, imm10_5 is op15_31=0xe51b & vrD & vrJ & imm10_5 {\n\tvrD = vsubi.du(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vbsll.v;\n\n#lsx.txt vbsll.v mask=0x728e0000\t\n#0x728e0000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vbsll.v vrD, vrJ, imm10_5 is op15_31=0xe51c & vrD & vrJ & imm10_5 {\n\tvrD = vbsll.v(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vbsrl.v;\n\n#lsx.txt vbsrl.v mask=0x728e8000\t\n#0x728e8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vbsrl.v vrD, vrJ, imm10_5 is op15_31=0xe51d & vrD & vrJ & imm10_5 {\n\tvrD = vbsrl.v(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.b;\n\n#lsx.txt vmaxi.b mask=0x72900000\t\n#0x72900000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmaxi.b vrD, vrJ, simm10_5 is op15_31=0xe520 & vrD & vrJ & simm10_5 {\n\tvrD = vmaxi.b(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.h;\n\n#lsx.txt vmaxi.h mask=0x72908000\t\n#0x72908000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmaxi.h vrD, vrJ, simm10_5 is op15_31=0xe521 & vrD & vrJ & simm10_5 {\n\tvrD = vmaxi.h(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.w;\n\n#lsx.txt vmaxi.w mask=0x72910000\t\n#0x72910000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmaxi.w vrD, vrJ, simm10_5 is op15_31=0xe522 & vrD & vrJ & simm10_5 {\n\tvrD = vmaxi.w(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.d;\n\n#lsx.txt vmaxi.d mask=0x72918000\t\n#0x72918000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmaxi.d vrD, vrJ, simm10_5 is op15_31=0xe523 & vrD & vrJ & simm10_5 {\n\tvrD = vmaxi.d(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.b;\n\n#lsx.txt vmini.b mask=0x72920000\t\n#0x72920000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmini.b vrD, vrJ, simm10_5 is op15_31=0xe524 & vrD & vrJ & simm10_5 {\n\tvrD = vmini.b(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.h;\n\n#lsx.txt vmini.h mask=0x72928000\t\n#0x72928000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmini.h vrD, vrJ, simm10_5 is op15_31=0xe525 & vrD & vrJ & simm10_5 {\n\tvrD = vmini.h(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.w;\n\n#lsx.txt vmini.w mask=0x72930000\t\n#0x72930000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmini.w vrD, vrJ, simm10_5 is op15_31=0xe526 & vrD & vrJ & simm10_5 {\n\tvrD = vmini.w(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.d;\n\n#lsx.txt vmini.d mask=0x72938000\t\n#0x72938000\t0xffff8000\tv0:5,v5:5, s10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0']\n:vmini.d vrD, vrJ, simm10_5 is op15_31=0xe527 & vrD & vrJ & simm10_5 {\n\tvrD = vmini.d(vrD, vrJ, simm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.bu;\n\n#lsx.txt vmaxi.bu mask=0x72940000\t\n#0x72940000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmaxi.bu vrD, vrJ, imm10_5 is op15_31=0xe528 & vrD & vrJ & imm10_5 {\n\tvrD = vmaxi.bu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.hu;\n\n#lsx.txt vmaxi.hu mask=0x72948000\t\n#0x72948000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmaxi.hu vrD, vrJ, imm10_5 is op15_31=0xe529 & vrD & vrJ & imm10_5 {\n\tvrD = vmaxi.hu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.wu;\n\n#lsx.txt vmaxi.wu mask=0x72950000\t\n#0x72950000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmaxi.wu vrD, vrJ, imm10_5 is op15_31=0xe52a & vrD & vrJ & imm10_5 {\n\tvrD = vmaxi.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmaxi.du;\n\n#lsx.txt vmaxi.du mask=0x72958000\t\n#0x72958000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmaxi.du vrD, vrJ, imm10_5 is op15_31=0xe52b & vrD & vrJ & imm10_5 {\n\tvrD = vmaxi.du(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.bu;\n\n#lsx.txt vmini.bu mask=0x72960000\t\n#0x72960000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmini.bu vrD, vrJ, imm10_5 is op15_31=0xe52c & vrD & vrJ & imm10_5 {\n\tvrD = vmini.bu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.hu;\n\n#lsx.txt vmini.hu mask=0x72968000\t\n#0x72968000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmini.hu vrD, vrJ, imm10_5 is op15_31=0xe52d & vrD & vrJ & imm10_5 {\n\tvrD = vmini.hu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.wu;\n\n#lsx.txt vmini.wu mask=0x72970000\t\n#0x72970000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmini.wu vrD, vrJ, imm10_5 is op15_31=0xe52e & vrD & vrJ & imm10_5 {\n\tvrD = vmini.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vmini.du;\n\n#lsx.txt vmini.du mask=0x72978000\t\n#0x72978000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vmini.du vrD, vrJ, imm10_5 is op15_31=0xe52f & vrD & vrJ & imm10_5 {\n\tvrD = vmini.du(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vfrstpi.b;\n\n#lsx.txt vfrstpi.b mask=0x729a0000\t\n#0x729a0000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vfrstpi.b vrD, vrJ, imm10_5 is op15_31=0xe534 & vrD & vrJ & imm10_5 {\n\tvrD = vfrstpi.b(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vfrstpi.h;\n\n#lsx.txt vfrstpi.h mask=0x729a8000\t\n#0x729a8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vfrstpi.h vrD, vrJ, imm10_5 is op15_31=0xe535 & vrD & vrJ & imm10_5 {\n\tvrD = vfrstpi.h(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vclo.b;\n\n#lsx.txt vclo.b mask=0x729c0000\t\n#0x729c0000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclo.b vrD, vrJ is op10_31=0x1ca700 & vrD & vrJ {\n\tvrD = vclo.b(vrD, vrJ);\n}\n\ndefine pcodeop vclo.h;\n\n#lsx.txt vclo.h mask=0x729c0400\t\n#0x729c0400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclo.h vrD, vrJ is op10_31=0x1ca701 & vrD & vrJ {\n\tvrD = vclo.h(vrD, vrJ);\n}\n\ndefine pcodeop vclo.w;\n\n#lsx.txt vclo.w mask=0x729c0800\t\n#0x729c0800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclo.w vrD, vrJ is op10_31=0x1ca702 & vrD & vrJ {\n\tvrD = vclo.w(vrD, vrJ);\n}\n\ndefine pcodeop vclo.d;\n\n#lsx.txt vclo.d mask=0x729c0c00\t\n#0x729c0c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclo.d vrD, vrJ is op10_31=0x1ca703 & vrD & vrJ {\n\tvrD = vclo.d(vrD, vrJ);\n}\n\ndefine pcodeop vclz.b;\n\n#lsx.txt vclz.b mask=0x729c1000\t\n#0x729c1000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclz.b vrD, vrJ is op10_31=0x1ca704 & vrD & vrJ {\n\tvrD = vclz.b(vrD, vrJ);\n}\n\ndefine pcodeop vclz.h;\n\n#lsx.txt vclz.h mask=0x729c1400\t\n#0x729c1400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclz.h vrD, vrJ is op10_31=0x1ca705 & vrD & vrJ {\n\tvrD = vclz.h(vrD, vrJ);\n}\n\ndefine pcodeop vclz.w;\n\n#lsx.txt vclz.w mask=0x729c1800\t\n#0x729c1800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclz.w vrD, vrJ is op10_31=0x1ca706 & vrD & vrJ {\n\tvrD = vclz.w(vrD, vrJ);\n}\n\ndefine pcodeop vclz.d;\n\n#lsx.txt vclz.d mask=0x729c1c00\t\n#0x729c1c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vclz.d vrD, vrJ is op10_31=0x1ca707 & vrD & vrJ {\n\tvrD = vclz.d(vrD, vrJ);\n}\n\ndefine pcodeop vpcnt.b;\n\n#lsx.txt vpcnt.b mask=0x729c2000\t\n#0x729c2000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vpcnt.b vrD, vrJ is op10_31=0x1ca708 & vrD & vrJ {\n\tvrD = vpcnt.b(vrD, vrJ);\n}\n\ndefine pcodeop vpcnt.h;\n\n#lsx.txt vpcnt.h mask=0x729c2400\t\n#0x729c2400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vpcnt.h vrD, vrJ is op10_31=0x1ca709 & vrD & vrJ {\n\tvrD = vpcnt.h(vrD, vrJ);\n}\n\ndefine pcodeop vpcnt.w;\n\n#lsx.txt vpcnt.w mask=0x729c2800\t\n#0x729c2800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vpcnt.w vrD, vrJ is op10_31=0x1ca70a & vrD & vrJ {\n\tvrD = vpcnt.w(vrD, vrJ);\n}\n\ndefine pcodeop vpcnt.d;\n\n#lsx.txt vpcnt.d mask=0x729c2c00\t\n#0x729c2c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vpcnt.d vrD, vrJ is op10_31=0x1ca70b & vrD & vrJ {\n\tvrD = vpcnt.d(vrD, vrJ);\n}\n\ndefine pcodeop vneg.b;\n\n#lsx.txt vneg.b mask=0x729c3000\t\n#0x729c3000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vneg.b vrD, vrJ is op10_31=0x1ca70c & vrD & vrJ {\n\tvrD = vneg.b(vrD, vrJ);\n}\n\ndefine pcodeop vneg.h;\n\n#lsx.txt vneg.h mask=0x729c3400\t\n#0x729c3400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vneg.h vrD, vrJ is op10_31=0x1ca70d & vrD & vrJ {\n\tvrD = vneg.h(vrD, vrJ);\n}\n\ndefine pcodeop vneg.w;\n\n#lsx.txt vneg.w mask=0x729c3800\t\n#0x729c3800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vneg.w vrD, vrJ is op10_31=0x1ca70e & vrD & vrJ {\n\tvrD = vneg.w(vrD, vrJ);\n}\n\ndefine pcodeop vneg.d;\n\n#lsx.txt vneg.d mask=0x729c3c00\t\n#0x729c3c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vneg.d vrD, vrJ is op10_31=0x1ca70f & vrD & vrJ {\n\tvrD = vneg.d(vrD, vrJ);\n}\n\ndefine pcodeop vmskltz.b;\n\n#lsx.txt vmskltz.b mask=0x729c4000\t\n#0x729c4000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vmskltz.b vrD, vrJ is op10_31=0x1ca710 & vrD & vrJ {\n\tvrD = vmskltz.b(vrD, vrJ);\n}\n\ndefine pcodeop vmskltz.h;\n\n#lsx.txt vmskltz.h mask=0x729c4400\t\n#0x729c4400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vmskltz.h vrD, vrJ is op10_31=0x1ca711 & vrD & vrJ {\n\tvrD = vmskltz.h(vrD, vrJ);\n}\n\ndefine pcodeop vmskltz.w;\n\n#lsx.txt vmskltz.w mask=0x729c4800\t\n#0x729c4800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vmskltz.w vrD, vrJ is op10_31=0x1ca712 & vrD & vrJ {\n\tvrD = vmskltz.w(vrD, vrJ);\n}\n\ndefine pcodeop vmskltz.d;\n\n#lsx.txt vmskltz.d mask=0x729c4c00\t\n#0x729c4c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vmskltz.d vrD, vrJ is op10_31=0x1ca713 & vrD & vrJ {\n\tvrD = vmskltz.d(vrD, vrJ);\n}\n\ndefine pcodeop vmskgez.b;\n\n#lsx.txt vmskgez.b mask=0x729c5000\t\n#0x729c5000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vmskgez.b vrD, vrJ is op10_31=0x1ca714 & vrD & vrJ {\n\tvrD = vmskgez.b(vrD, vrJ);\n}\n\ndefine pcodeop vmsknz.b;\n\n#lsx.txt vmsknz.b mask=0x729c6000\t\n#0x729c6000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vmsknz.b vrD, vrJ is op10_31=0x1ca718 & vrD & vrJ {\n\tvrD = vmsknz.b(vrD, vrJ);\n}\n\ndefine pcodeop vseteqz.v;\n\n#lsx.txt vseteqz.v mask=0x729c9800\t\n#0x729c9800\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vseteqz.v fccD, vrJ is op10_31=0x1ca726 & fccD & vrJ {\n\tfccD = vseteqz.v(fccD, vrJ);\n}\n\ndefine pcodeop vsetnez.v;\n\n#lsx.txt vsetnez.v mask=0x729c9c00\t\n#0x729c9c00\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetnez.v fccD, vrJ is op10_31=0x1ca727 & fccD & vrJ {\n\tfccD = vsetnez.v(fccD, vrJ);\n}\n\ndefine pcodeop vsetanyeqz.b;\n\n#lsx.txt vsetanyeqz.b mask=0x729ca000\t\n#0x729ca000\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetanyeqz.b fccD, vrJ is op10_31=0x1ca728 & fccD & vrJ {\n\tfccD = vsetanyeqz.b(fccD, vrJ);\n}\n\ndefine pcodeop vsetanyeqz.h;\n\n#lsx.txt vsetanyeqz.h mask=0x729ca400\t\n#0x729ca400\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetanyeqz.h fccD, vrJ is op10_31=0x1ca729 & fccD & vrJ {\n\tfccD = vsetanyeqz.h(fccD, vrJ);\n}\n\ndefine pcodeop vsetanyeqz.w;\n\n#lsx.txt vsetanyeqz.w mask=0x729ca800\t\n#0x729ca800\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetanyeqz.w fccD, vrJ is op10_31=0x1ca72a & fccD & vrJ {\n\tfccD = vsetanyeqz.w(fccD, vrJ);\n}\n\ndefine pcodeop vsetanyeqz.d;\n\n#lsx.txt vsetanyeqz.d mask=0x729cac00\t\n#0x729cac00\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetanyeqz.d fccD, vrJ is op10_31=0x1ca72b & fccD & vrJ {\n\tfccD = vsetanyeqz.d(fccD, vrJ);\n}\n\ndefine pcodeop vsetallnez.b;\n\n#lsx.txt vsetallnez.b mask=0x729cb000\t\n#0x729cb000\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetallnez.b fccD, vrJ is op10_31=0x1ca72c & fccD & vrJ {\n\tfccD = vsetallnez.b(fccD, vrJ);\n}\n\ndefine pcodeop vsetallnez.h;\n\n#lsx.txt vsetallnez.h mask=0x729cb400\t\n#0x729cb400\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetallnez.h fccD, vrJ is op10_31=0x1ca72d & fccD & vrJ {\n\tfccD = vsetallnez.h(fccD, vrJ);\n}\n\ndefine pcodeop vsetallnez.w;\n\n#lsx.txt vsetallnez.w mask=0x729cb800\t\n#0x729cb800\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetallnez.w fccD, vrJ is op10_31=0x1ca72e & fccD & vrJ {\n\tfccD = vsetallnez.w(fccD, vrJ);\n}\n\ndefine pcodeop vsetallnez.d;\n\n#lsx.txt vsetallnez.d mask=0x729cbc00\t\n#0x729cbc00\t0xfffffc18\tc0:3,v5:5\t['fcc0_3_s0', 'vreg5_5_s0']\n:vsetallnez.d fccD, vrJ is op10_31=0x1ca72f & fccD & vrJ {\n\tfccD = vsetallnez.d(fccD, vrJ);\n}\n\ndefine pcodeop vflogb.s;\n\n#lsx.txt vflogb.s mask=0x729cc400\t\n#0x729cc400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vflogb.s vrD, vrJ is op10_31=0x1ca731 & vrD & vrJ {\n\tvrD = vflogb.s(vrD, vrJ);\n}\n\ndefine pcodeop vflogb.d;\n\n#lsx.txt vflogb.d mask=0x729cc800\t\n#0x729cc800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vflogb.d vrD, vrJ is op10_31=0x1ca732 & vrD & vrJ {\n\tvrD = vflogb.d(vrD, vrJ);\n}\n\ndefine pcodeop vfclass.s;\n\n#lsx.txt vfclass.s mask=0x729cd400\t\n#0x729cd400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfclass.s vrD, vrJ is op10_31=0x1ca735 & vrD & vrJ {\n\tvrD = vfclass.s(vrD, vrJ);\n}\n\ndefine pcodeop vfclass.d;\n\n#lsx.txt vfclass.d mask=0x729cd800\t\n#0x729cd800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfclass.d vrD, vrJ is op10_31=0x1ca736 & vrD & vrJ {\n\tvrD = vfclass.d(vrD, vrJ);\n}\n\ndefine pcodeop vfsqrt.s;\n\n#lsx.txt vfsqrt.s mask=0x729ce400\t\n#0x729ce400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfsqrt.s vrD, vrJ is op10_31=0x1ca739 & vrD & vrJ {\n\tvrD = vfsqrt.s(vrD, vrJ);\n}\n\ndefine pcodeop vfsqrt.d;\n\n#lsx.txt vfsqrt.d mask=0x729ce800\t\n#0x729ce800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfsqrt.d vrD, vrJ is op10_31=0x1ca73a & vrD & vrJ {\n\tvrD = vfsqrt.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrecip.s;\n\n#lsx.txt vfrecip.s mask=0x729cf400\t\n#0x729cf400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrecip.s vrD, vrJ is op10_31=0x1ca73d & vrD & vrJ {\n\tvrD = vfrecip.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrecip.d;\n\n#lsx.txt vfrecip.d mask=0x729cf800\t\n#0x729cf800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrecip.d vrD, vrJ is op10_31=0x1ca73e & vrD & vrJ {\n\tvrD = vfrecip.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrsqrt.s;\n\n#lsx.txt vfrsqrt.s mask=0x729d0400\t\n#0x729d0400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrsqrt.s vrD, vrJ is op10_31=0x1ca741 & vrD & vrJ {\n\tvrD = vfrsqrt.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrsqrt.d;\n\n#lsx.txt vfrsqrt.d mask=0x729d0800\t\n#0x729d0800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrsqrt.d vrD, vrJ is op10_31=0x1ca742 & vrD & vrJ {\n\tvrD = vfrsqrt.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrint.s;\n\n#lsx.txt vfrint.s mask=0x729d3400\t\n#0x729d3400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrint.s vrD, vrJ is op10_31=0x1ca74d & vrD & vrJ {\n\tvrD = vfrint.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrint.d;\n\n#lsx.txt vfrint.d mask=0x729d3800\t\n#0x729d3800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrint.d vrD, vrJ is op10_31=0x1ca74e & vrD & vrJ {\n\tvrD = vfrint.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrm.s;\n\n#lsx.txt vfrintrm.s mask=0x729d4400\t\n#0x729d4400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrm.s vrD, vrJ is op10_31=0x1ca751 & vrD & vrJ {\n\tvrD = vfrintrm.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrm.d;\n\n#lsx.txt vfrintrm.d mask=0x729d4800\t\n#0x729d4800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrm.d vrD, vrJ is op10_31=0x1ca752 & vrD & vrJ {\n\tvrD = vfrintrm.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrp.s;\n\n#lsx.txt vfrintrp.s mask=0x729d5400\t\n#0x729d5400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrp.s vrD, vrJ is op10_31=0x1ca755 & vrD & vrJ {\n\tvrD = vfrintrp.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrp.d;\n\n#lsx.txt vfrintrp.d mask=0x729d5800\t\n#0x729d5800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrp.d vrD, vrJ is op10_31=0x1ca756 & vrD & vrJ {\n\tvrD = vfrintrp.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrz.s;\n\n#lsx.txt vfrintrz.s mask=0x729d6400\t\n#0x729d6400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrz.s vrD, vrJ is op10_31=0x1ca759 & vrD & vrJ {\n\tvrD = vfrintrz.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrz.d;\n\n#lsx.txt vfrintrz.d mask=0x729d6800\t\n#0x729d6800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrz.d vrD, vrJ is op10_31=0x1ca75a & vrD & vrJ {\n\tvrD = vfrintrz.d(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrne.s;\n\n#lsx.txt vfrintrne.s mask=0x729d7400\t\n#0x729d7400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrne.s vrD, vrJ is op10_31=0x1ca75d & vrD & vrJ {\n\tvrD = vfrintrne.s(vrD, vrJ);\n}\n\ndefine pcodeop vfrintrne.d;\n\n#lsx.txt vfrintrne.d mask=0x729d7800\t\n#0x729d7800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfrintrne.d vrD, vrJ is op10_31=0x1ca75e & vrD & vrJ {\n\tvrD = vfrintrne.d(vrD, vrJ);\n}\n\ndefine pcodeop vfcvtl.s.h;\n\n#lsx.txt vfcvtl.s.h mask=0x729de800\t\n#0x729de800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfcvtl.s.h vrD, vrJ is op10_31=0x1ca77a & vrD & vrJ {\n\tvrD = vfcvtl.s.h(vrD, vrJ);\n}\n\ndefine pcodeop vfcvth.s.h;\n\n#lsx.txt vfcvth.s.h mask=0x729dec00\t\n#0x729dec00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfcvth.s.h vrD, vrJ is op10_31=0x1ca77b & vrD & vrJ {\n\tvrD = vfcvth.s.h(vrD, vrJ);\n}\n\ndefine pcodeop vfcvtl.d.s;\n\n#lsx.txt vfcvtl.d.s mask=0x729df000\t\n#0x729df000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfcvtl.d.s vrD, vrJ is op10_31=0x1ca77c & vrD & vrJ {\n\tvrD = vfcvtl.d.s(vrD, vrJ);\n}\n\ndefine pcodeop vfcvth.d.s;\n\n#lsx.txt vfcvth.d.s mask=0x729df400\t\n#0x729df400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vfcvth.d.s vrD, vrJ is op10_31=0x1ca77d & vrD & vrJ {\n\tvrD = vfcvth.d.s(vrD, vrJ);\n}\n\ndefine pcodeop vffint.s.w;\n\n#lsx.txt vffint.s.w mask=0x729e0000\t\n#0x729e0000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vffint.s.w vrD, vrJ is op10_31=0x1ca780 & vrD & vrJ {\n\tvrD = vffint.s.w(vrD, vrJ);\n}\n\ndefine pcodeop vffint.s.wu;\n\n#lsx.txt vffint.s.wu mask=0x729e0400\t\n#0x729e0400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vffint.s.wu vrD, vrJ is op10_31=0x1ca781 & vrD & vrJ {\n\tvrD = vffint.s.wu(vrD, vrJ);\n}\n\ndefine pcodeop vffint.d.l;\n\n#lsx.txt vffint.d.l mask=0x729e0800\t\n#0x729e0800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vffint.d.l vrD, vrJ is op10_31=0x1ca782 & vrD & vrJ {\n\tvrD = vffint.d.l(vrD, vrJ);\n}\n\ndefine pcodeop vffint.d.lu;\n\n#lsx.txt vffint.d.lu mask=0x729e0c00\t\n#0x729e0c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vffint.d.lu vrD, vrJ is op10_31=0x1ca783 & vrD & vrJ {\n\tvrD = vffint.d.lu(vrD, vrJ);\n}\n\ndefine pcodeop vffintl.d.w;\n\n#lsx.txt vffintl.d.w mask=0x729e1000\t\n#0x729e1000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vffintl.d.w vrD, vrJ is op10_31=0x1ca784 & vrD & vrJ {\n\tvrD = vffintl.d.w(vrD, vrJ);\n}\n\ndefine pcodeop vffinth.d.w;\n\n#lsx.txt vffinth.d.w mask=0x729e1400\t\n#0x729e1400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vffinth.d.w vrD, vrJ is op10_31=0x1ca785 & vrD & vrJ {\n\tvrD = vffinth.d.w(vrD, vrJ);\n}\n\ndefine pcodeop vftint.w.s;\n\n#lsx.txt vftint.w.s mask=0x729e3000\t\n#0x729e3000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftint.w.s vrD, vrJ is op10_31=0x1ca78c & vrD & vrJ {\n\tvrD = vftint.w.s(vrD, vrJ);\n}\n\ndefine pcodeop vftint.l.d;\n\n#lsx.txt vftint.l.d mask=0x729e3400\t\n#0x729e3400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftint.l.d vrD, vrJ is op10_31=0x1ca78d & vrD & vrJ {\n\tvrD = vftint.l.d(vrD, vrJ);\n}\n\ndefine pcodeop vftintrm.w.s;\n\n#lsx.txt vftintrm.w.s mask=0x729e3800\t\n#0x729e3800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrm.w.s vrD, vrJ is op10_31=0x1ca78e & vrD & vrJ {\n\tvrD = vftintrm.w.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrm.l.d;\n\n#lsx.txt vftintrm.l.d mask=0x729e3c00\t\n#0x729e3c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrm.l.d vrD, vrJ is op10_31=0x1ca78f & vrD & vrJ {\n\tvrD = vftintrm.l.d(vrD, vrJ);\n}\n\ndefine pcodeop vftintrp.w.s;\n\n#lsx.txt vftintrp.w.s mask=0x729e4000\t\n#0x729e4000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrp.w.s vrD, vrJ is op10_31=0x1ca790 & vrD & vrJ {\n\tvrD = vftintrp.w.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrp.l.d;\n\n#lsx.txt vftintrp.l.d mask=0x729e4400\t\n#0x729e4400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrp.l.d vrD, vrJ is op10_31=0x1ca791 & vrD & vrJ {\n\tvrD = vftintrp.l.d(vrD, vrJ);\n}\n\ndefine pcodeop vftintrz.w.s;\n\n#lsx.txt vftintrz.w.s mask=0x729e4800\t\n#0x729e4800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrz.w.s vrD, vrJ is op10_31=0x1ca792 & vrD & vrJ {\n\tvrD = vftintrz.w.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrz.l.d;\n\n#lsx.txt vftintrz.l.d mask=0x729e4c00\t\n#0x729e4c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrz.l.d vrD, vrJ is op10_31=0x1ca793 & vrD & vrJ {\n\tvrD = vftintrz.l.d(vrD, vrJ);\n}\n\ndefine pcodeop vftintrne.w.s;\n\n#lsx.txt vftintrne.w.s mask=0x729e5000\t\n#0x729e5000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrne.w.s vrD, vrJ is op10_31=0x1ca794 & vrD & vrJ {\n\tvrD = vftintrne.w.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrne.l.d;\n\n#lsx.txt vftintrne.l.d mask=0x729e5400\t\n#0x729e5400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrne.l.d vrD, vrJ is op10_31=0x1ca795 & vrD & vrJ {\n\tvrD = vftintrne.l.d(vrD, vrJ);\n}\n\ndefine pcodeop vftint.wu.s;\n\n#lsx.txt vftint.wu.s mask=0x729e5800\t\n#0x729e5800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftint.wu.s vrD, vrJ is op10_31=0x1ca796 & vrD & vrJ {\n\tvrD = vftint.wu.s(vrD, vrJ);\n}\n\ndefine pcodeop vftint.lu.d;\n\n#lsx.txt vftint.lu.d mask=0x729e5c00\t\n#0x729e5c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftint.lu.d vrD, vrJ is op10_31=0x1ca797 & vrD & vrJ {\n\tvrD = vftint.lu.d(vrD, vrJ);\n}\n\ndefine pcodeop vftintrz.wu.s;\n\n#lsx.txt vftintrz.wu.s mask=0x729e7000\t\n#0x729e7000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrz.wu.s vrD, vrJ is op10_31=0x1ca79c & vrD & vrJ {\n\tvrD = vftintrz.wu.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrz.lu.d;\n\n#lsx.txt vftintrz.lu.d mask=0x729e7400\t\n#0x729e7400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrz.lu.d vrD, vrJ is op10_31=0x1ca79d & vrD & vrJ {\n\tvrD = vftintrz.lu.d(vrD, vrJ);\n}\n\ndefine pcodeop vftintl.l.s;\n\n#lsx.txt vftintl.l.s mask=0x729e8000\t\n#0x729e8000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintl.l.s vrD, vrJ is op10_31=0x1ca7a0 & vrD & vrJ {\n\tvrD = vftintl.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftinth.l.s;\n\n#lsx.txt vftinth.l.s mask=0x729e8400\t\n#0x729e8400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftinth.l.s vrD, vrJ is op10_31=0x1ca7a1 & vrD & vrJ {\n\tvrD = vftinth.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrml.l.s;\n\n#lsx.txt vftintrml.l.s mask=0x729e8800\t\n#0x729e8800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrml.l.s vrD, vrJ is op10_31=0x1ca7a2 & vrD & vrJ {\n\tvrD = vftintrml.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrmh.l.s;\n\n#lsx.txt vftintrmh.l.s mask=0x729e8c00\t\n#0x729e8c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrmh.l.s vrD, vrJ is op10_31=0x1ca7a3 & vrD & vrJ {\n\tvrD = vftintrmh.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrpl.l.s;\n\n#lsx.txt vftintrpl.l.s mask=0x729e9000\t\n#0x729e9000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrpl.l.s vrD, vrJ is op10_31=0x1ca7a4 & vrD & vrJ {\n\tvrD = vftintrpl.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrph.l.s;\n\n#lsx.txt vftintrph.l.s mask=0x729e9400\t\n#0x729e9400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrph.l.s vrD, vrJ is op10_31=0x1ca7a5 & vrD & vrJ {\n\tvrD = vftintrph.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrzl.l.s;\n\n#lsx.txt vftintrzl.l.s mask=0x729e9800\t\n#0x729e9800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrzl.l.s vrD, vrJ is op10_31=0x1ca7a6 & vrD & vrJ {\n\tvrD = vftintrzl.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrzh.l.s;\n\n#lsx.txt vftintrzh.l.s mask=0x729e9c00\t\n#0x729e9c00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrzh.l.s vrD, vrJ is op10_31=0x1ca7a7 & vrD & vrJ {\n\tvrD = vftintrzh.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrnel.l.s;\n\n#lsx.txt vftintrnel.l.s mask=0x729ea000\t\n#0x729ea000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrnel.l.s vrD, vrJ is op10_31=0x1ca7a8 & vrD & vrJ {\n\tvrD = vftintrnel.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vftintrneh.l.s;\n\n#lsx.txt vftintrneh.l.s mask=0x729ea400\t\n#0x729ea400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vftintrneh.l.s vrD, vrJ is op10_31=0x1ca7a9 & vrD & vrJ {\n\tvrD = vftintrneh.l.s(vrD, vrJ);\n}\n\ndefine pcodeop vexth.h.b;\n\n#lsx.txt vexth.h.b mask=0x729ee000\t\n#0x729ee000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.h.b vrD, vrJ is op10_31=0x1ca7b8 & vrD & vrJ {\n\tvrD = vexth.h.b(vrD, vrJ);\n}\n\ndefine pcodeop vexth.w.h;\n\n#lsx.txt vexth.w.h mask=0x729ee400\t\n#0x729ee400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.w.h vrD, vrJ is op10_31=0x1ca7b9 & vrD & vrJ {\n\tvrD = vexth.w.h(vrD, vrJ);\n}\n\ndefine pcodeop vexth.d.w;\n\n#lsx.txt vexth.d.w mask=0x729ee800\t\n#0x729ee800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.d.w vrD, vrJ is op10_31=0x1ca7ba & vrD & vrJ {\n\tvrD = vexth.d.w(vrD, vrJ);\n}\n\ndefine pcodeop vexth.q.d;\n\n#lsx.txt vexth.q.d mask=0x729eec00\t\n#0x729eec00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.q.d vrD, vrJ is op10_31=0x1ca7bb & vrD & vrJ {\n\tvrD = vexth.q.d(vrD, vrJ);\n}\n\ndefine pcodeop vexth.hu.bu;\n\n#lsx.txt vexth.hu.bu mask=0x729ef000\t\n#0x729ef000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.hu.bu vrD, vrJ is op10_31=0x1ca7bc & vrD & vrJ {\n\tvrD = vexth.hu.bu(vrD, vrJ);\n}\n\ndefine pcodeop vexth.wu.hu;\n\n#lsx.txt vexth.wu.hu mask=0x729ef400\t\n#0x729ef400\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.wu.hu vrD, vrJ is op10_31=0x1ca7bd & vrD & vrJ {\n\tvrD = vexth.wu.hu(vrD, vrJ);\n}\n\ndefine pcodeop vexth.du.wu;\n\n#lsx.txt vexth.du.wu mask=0x729ef800\t\n#0x729ef800\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.du.wu vrD, vrJ is op10_31=0x1ca7be & vrD & vrJ {\n\tvrD = vexth.du.wu(vrD, vrJ);\n}\n\ndefine pcodeop vexth.qu.du;\n\n#lsx.txt vexth.qu.du mask=0x729efc00\t\n#0x729efc00\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vexth.qu.du vrD, vrJ is op10_31=0x1ca7bf & vrD & vrJ {\n\tvrD = vexth.qu.du(vrD, vrJ);\n}\n\ndefine pcodeop vreplgr2vr.b;\n\n#lsx.txt vreplgr2vr.b mask=0x729f0000\t\n#0x729f0000\t0xfffffc00\tv0:5, r5:5\t['vreg0_5_s0', 'reg5_5_s0']\n:vreplgr2vr.b vrD, RJsrc is op10_31=0x1ca7c0 & vrD & RJsrc {\n\tvrD = vreplgr2vr.b(vrD, RJsrc);\n}\n\ndefine pcodeop vreplgr2vr.h;\n\n#lsx.txt vreplgr2vr.h mask=0x729f0400\t\n#0x729f0400\t0xfffffc00\tv0:5, r5:5\t['vreg0_5_s0', 'reg5_5_s0']\n:vreplgr2vr.h vrD, RJsrc is op10_31=0x1ca7c1 & vrD & RJsrc {\n\tvrD = vreplgr2vr.h(vrD, RJsrc);\n}\n\ndefine pcodeop vreplgr2vr.w;\n\n#lsx.txt vreplgr2vr.w mask=0x729f0800\t\n#0x729f0800\t0xfffffc00\tv0:5, r5:5\t['vreg0_5_s0', 'reg5_5_s0']\n:vreplgr2vr.w vrD, RJsrc is op10_31=0x1ca7c2 & vrD & RJsrc {\n\tvrD = vreplgr2vr.w(vrD, RJsrc);\n}\n\ndefine pcodeop vreplgr2vr.d;\n\n#lsx.txt vreplgr2vr.d mask=0x729f0c00\t\n#0x729f0c00\t0xfffffc00\tv0:5, r5:5\t['vreg0_5_s0', 'reg5_5_s0']\n:vreplgr2vr.d vrD, RJsrc is op10_31=0x1ca7c3 & vrD & RJsrc {\n\tvrD = vreplgr2vr.d(vrD, RJsrc);\n}\n\ndefine pcodeop vrotri.b;\n\n#lsx.txt vrotri.b mask=0x72a02000\t\n#0x72a02000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vrotri.b vrD, vrJ, imm10_3 is op13_31=0x39501 & vrD & vrJ & imm10_3 {\n\tvrD = vrotri.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vrotri.h;\n\n#lsx.txt vrotri.h mask=0x72a04000\t\n#0x72a04000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vrotri.h vrD, vrJ, imm10_4 is op14_31=0x1ca81 & vrD & vrJ & imm10_4 {\n\tvrD = vrotri.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vrotri.w;\n\n#lsx.txt vrotri.w mask=0x72a08000\t\n#0x72a08000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vrotri.w vrD, vrJ, imm10_5 is op15_31=0xe541 & vrD & vrJ & imm10_5 {\n\tvrD = vrotri.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vrotri.d;\n\n#lsx.txt vrotri.d mask=0x72a10000\t\n#0x72a10000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vrotri.d vrD, vrJ, imm10_6 is op16_31=0x72a1 & vrD & vrJ & imm10_6 {\n\tvrD = vrotri.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrlri.b;\n\n#lsx.txt vsrlri.b mask=0x72a42000\t\n#0x72a42000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsrlri.b vrD, vrJ, imm10_3 is op13_31=0x39521 & vrD & vrJ & imm10_3 {\n\tvrD = vsrlri.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsrlri.h;\n\n#lsx.txt vsrlri.h mask=0x72a44000\t\n#0x72a44000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrlri.h vrD, vrJ, imm10_4 is op14_31=0x1ca91 & vrD & vrJ & imm10_4 {\n\tvrD = vsrlri.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrlri.w;\n\n#lsx.txt vsrlri.w mask=0x72a48000\t\n#0x72a48000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrlri.w vrD, vrJ, imm10_5 is op15_31=0xe549 & vrD & vrJ & imm10_5 {\n\tvrD = vsrlri.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrlri.d;\n\n#lsx.txt vsrlri.d mask=0x72a50000\t\n#0x72a50000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrlri.d vrD, vrJ, imm10_6 is op16_31=0x72a5 & vrD & vrJ & imm10_6 {\n\tvrD = vsrlri.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrari.b;\n\n#lsx.txt vsrari.b mask=0x72a82000\t\n#0x72a82000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsrari.b vrD, vrJ, imm10_3 is op13_31=0x39541 & vrD & vrJ & imm10_3 {\n\tvrD = vsrari.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsrari.h;\n\n#lsx.txt vsrari.h mask=0x72a84000\t\n#0x72a84000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrari.h vrD, vrJ, imm10_4 is op14_31=0x1caa1 & vrD & vrJ & imm10_4 {\n\tvrD = vsrari.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrari.w;\n\n#lsx.txt vsrari.w mask=0x72a88000\t\n#0x72a88000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrari.w vrD, vrJ, imm10_5 is op15_31=0xe551 & vrD & vrJ & imm10_5 {\n\tvrD = vsrari.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrari.d;\n\n#lsx.txt vsrari.d mask=0x72a90000\t\n#0x72a90000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrari.d vrD, vrJ, imm10_6 is op16_31=0x72a9 & vrD & vrJ & imm10_6 {\n\tvrD = vsrari.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vinsgr2vr.b;\n\n#lsx.txt vinsgr2vr.b mask=0x72eb8000\t\n#0x72eb8000\t0xffffc000\tv0:5, r5:5,u10:4\t['vreg0_5_s0', 'reg5_5_s0', 'imm10_4_s0']\n:vinsgr2vr.b vrD, RJsrc, imm10_4 is op14_31=0x1cbae & vrD & RJsrc & imm10_4 {\n\tvrD = vinsgr2vr.b(vrD, RJsrc, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vinsgr2vr.h;\n\n#lsx.txt vinsgr2vr.h mask=0x72ebc000\t\n#0x72ebc000\t0xffffe000\tv0:5, r5:5,u10:3\t['vreg0_5_s0', 'reg5_5_s0', 'imm10_3_s0']\n:vinsgr2vr.h vrD, RJsrc, imm10_3 is op13_31=0x3975e & vrD & RJsrc & imm10_3 {\n\tvrD = vinsgr2vr.h(vrD, RJsrc, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vinsgr2vr.w;\n\n#lsx.txt vinsgr2vr.w mask=0x72ebe000\t\n#0x72ebe000\t0xfffff000\tv0:5, r5:5,u10:2\t['vreg0_5_s0', 'reg5_5_s0', 'imm10_2_s0']\n:vinsgr2vr.w vrD, RJsrc, imm10_2 is op12_31=0x72ebe & vrD & RJsrc & imm10_2 {\n\tvrD = vinsgr2vr.w(vrD, RJsrc, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop vinsgr2vr.d;\n\n#lsx.txt vinsgr2vr.d mask=0x72ebf000\t\n#0x72ebf000\t0xfffff800\tv0:5, r5:5,u10:1\t['vreg0_5_s0', 'reg5_5_s0', 'imm10_1_s0']\n:vinsgr2vr.d vrD, RJsrc, imm10_1 is op11_31=0xe5d7e & vrD & RJsrc & imm10_1 {\n\tvrD = vinsgr2vr.d(vrD, RJsrc, imm10_1:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.b;\n\n#lsx.txt vpickve2gr.b mask=0x72ef8000\t\n#0x72ef8000\t0xffffc000\tr0:5,v5:5,u10:4\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vpickve2gr.b RD, vrJ, imm10_4 is op14_31=0x1cbbe & RD & vrJ & imm10_4 {\n\tRD = vpickve2gr.b(RD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.h;\n\n#lsx.txt vpickve2gr.h mask=0x72efc000\t\n#0x72efc000\t0xffffe000\tr0:5,v5:5,u10:3\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vpickve2gr.h RD, vrJ, imm10_3 is op13_31=0x3977e & RD & vrJ & imm10_3 {\n\tRD = vpickve2gr.h(RD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.w;\n\n#lsx.txt vpickve2gr.w mask=0x72efe000\t\n#0x72efe000\t0xfffff000\tr0:5,v5:5,u10:2\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_2_s0']\n:vpickve2gr.w RD, vrJ, imm10_2 is op12_31=0x72efe & RD & vrJ & imm10_2 {\n\tRD = vpickve2gr.w(RD, vrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.d;\n\n#lsx.txt vpickve2gr.d mask=0x72eff000\t\n#0x72eff000\t0xfffff800\tr0:5,v5:5,u10:1\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_1_s0']\n:vpickve2gr.d RD, vrJ, imm10_1 is op11_31=0xe5dfe & RD & vrJ & imm10_1 {\n\tRD = vpickve2gr.d(RD, vrJ, imm10_1:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.bu;\n\n#lsx.txt vpickve2gr.bu mask=0x72f38000\t\n#0x72f38000\t0xffffc000\tr0:5,v5:5,u10:4\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vpickve2gr.bu RD, vrJ, imm10_4 is op14_31=0x1cbce & RD & vrJ & imm10_4 {\n\tRD = vpickve2gr.bu(RD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.hu;\n\n#lsx.txt vpickve2gr.hu mask=0x72f3c000\t\n#0x72f3c000\t0xffffe000\tr0:5,v5:5,u10:3\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vpickve2gr.hu RD, vrJ, imm10_3 is op13_31=0x3979e & RD & vrJ & imm10_3 {\n\tRD = vpickve2gr.hu(RD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.wu;\n\n#lsx.txt vpickve2gr.wu mask=0x72f3e000\t\n#0x72f3e000\t0xfffff000\tr0:5,v5:5,u10:2\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_2_s0']\n:vpickve2gr.wu RD, vrJ, imm10_2 is op12_31=0x72f3e & RD & vrJ & imm10_2 {\n\tRD = vpickve2gr.wu(RD, vrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop vpickve2gr.du;\n\n#lsx.txt vpickve2gr.du mask=0x72f3f000\t\n#0x72f3f000\t0xfffff800\tr0:5,v5:5,u10:1\t['reg0_5_s0', 'vreg5_5_s0', 'imm10_1_s0']\n:vpickve2gr.du RD, vrJ, imm10_1 is op11_31=0xe5e7e & RD & vrJ & imm10_1 {\n\tRD = vpickve2gr.du(RD, vrJ, imm10_1:$(REGSIZE));\n}\n\ndefine pcodeop vreplvei.b;\n\n#lsx.txt vreplvei.b mask=0x72f78000\t\n#0x72f78000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vreplvei.b vrD, vrJ, imm10_4 is op14_31=0x1cbde & vrD & vrJ & imm10_4 {\n\tvrD = vreplvei.b(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vreplvei.h;\n\n#lsx.txt vreplvei.h mask=0x72f7c000\t\n#0x72f7c000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vreplvei.h vrD, vrJ, imm10_3 is op13_31=0x397be & vrD & vrJ & imm10_3 {\n\tvrD = vreplvei.h(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vreplvei.w;\n\n#lsx.txt vreplvei.w mask=0x72f7e000\t\n#0x72f7e000\t0xfffff000\tv0:5,v5:5,u10:2\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_2_s0']\n:vreplvei.w vrD, vrJ, imm10_2 is op12_31=0x72f7e & vrD & vrJ & imm10_2 {\n\tvrD = vreplvei.w(vrD, vrJ, imm10_2:$(REGSIZE));\n}\n\ndefine pcodeop vreplvei.d;\n\n#lsx.txt vreplvei.d mask=0x72f7f000\t\n#0x72f7f000\t0xfffff800\tv0:5,v5:5,u10:1\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_1_s0']\n:vreplvei.d vrD, vrJ, imm10_1 is op11_31=0xe5efe & vrD & vrJ & imm10_1 {\n\tvrD = vreplvei.d(vrD, vrJ, imm10_1:$(REGSIZE));\n}\n\ndefine pcodeop vsllwil.h.b;\n\n#lsx.txt vsllwil.h.b mask=0x73082000\t\n#0x73082000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsllwil.h.b vrD, vrJ, imm10_3 is op13_31=0x39841 & vrD & vrJ & imm10_3 {\n\tvrD = vsllwil.h.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsllwil.w.h;\n\n#lsx.txt vsllwil.w.h mask=0x73084000\t\n#0x73084000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsllwil.w.h vrD, vrJ, imm10_4 is op14_31=0x1cc21 & vrD & vrJ & imm10_4 {\n\tvrD = vsllwil.w.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsllwil.d.w;\n\n#lsx.txt vsllwil.d.w mask=0x73088000\t\n#0x73088000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsllwil.d.w vrD, vrJ, imm10_5 is op15_31=0xe611 & vrD & vrJ & imm10_5 {\n\tvrD = vsllwil.d.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vextl.q.d;\n\n#lsx.txt vextl.q.d mask=0x73090000\t\n#0x73090000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vextl.q.d vrD, vrJ is op10_31=0x1cc240 & vrD & vrJ {\n\tvrD = vextl.q.d(vrD, vrJ);\n}\n\ndefine pcodeop vsllwil.hu.bu;\n\n#lsx.txt vsllwil.hu.bu mask=0x730c2000\t\n#0x730c2000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsllwil.hu.bu vrD, vrJ, imm10_3 is op13_31=0x39861 & vrD & vrJ & imm10_3 {\n\tvrD = vsllwil.hu.bu(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsllwil.wu.hu;\n\n#lsx.txt vsllwil.wu.hu mask=0x730c4000\t\n#0x730c4000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsllwil.wu.hu vrD, vrJ, imm10_4 is op14_31=0x1cc31 & vrD & vrJ & imm10_4 {\n\tvrD = vsllwil.wu.hu(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsllwil.du.wu;\n\n#lsx.txt vsllwil.du.wu mask=0x730c8000\t\n#0x730c8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsllwil.du.wu vrD, vrJ, imm10_5 is op15_31=0xe619 & vrD & vrJ & imm10_5 {\n\tvrD = vsllwil.du.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vextl.qu.du;\n\n#lsx.txt vextl.qu.du mask=0x730d0000\t\n#0x730d0000\t0xfffffc00\tv0:5,v5:5\t['vreg0_5_s0', 'vreg5_5_s0']\n:vextl.qu.du vrD, vrJ is op10_31=0x1cc340 & vrD & vrJ {\n\tvrD = vextl.qu.du(vrD, vrJ);\n}\n\ndefine pcodeop vbitclri.b;\n\n#lsx.txt vbitclri.b mask=0x73102000\t\n#0x73102000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vbitclri.b vrD, vrJ, imm10_3 is op13_31=0x39881 & vrD & vrJ & imm10_3 {\n\tvrD = vbitclri.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vbitclri.h;\n\n#lsx.txt vbitclri.h mask=0x73104000\t\n#0x73104000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vbitclri.h vrD, vrJ, imm10_4 is op14_31=0x1cc41 & vrD & vrJ & imm10_4 {\n\tvrD = vbitclri.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vbitclri.w;\n\n#lsx.txt vbitclri.w mask=0x73108000\t\n#0x73108000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vbitclri.w vrD, vrJ, imm10_5 is op15_31=0xe621 & vrD & vrJ & imm10_5 {\n\tvrD = vbitclri.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vbitclri.d;\n\n#lsx.txt vbitclri.d mask=0x73110000\t\n#0x73110000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vbitclri.d vrD, vrJ, imm10_6 is op16_31=0x7311 & vrD & vrJ & imm10_6 {\n\tvrD = vbitclri.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vbitseti.b;\n\n#lsx.txt vbitseti.b mask=0x73142000\t\n#0x73142000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vbitseti.b vrD, vrJ, imm10_3 is op13_31=0x398a1 & vrD & vrJ & imm10_3 {\n\tvrD = vbitseti.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vbitseti.h;\n\n#lsx.txt vbitseti.h mask=0x73144000\t\n#0x73144000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vbitseti.h vrD, vrJ, imm10_4 is op14_31=0x1cc51 & vrD & vrJ & imm10_4 {\n\tvrD = vbitseti.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vbitseti.w;\n\n#lsx.txt vbitseti.w mask=0x73148000\t\n#0x73148000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vbitseti.w vrD, vrJ, imm10_5 is op15_31=0xe629 & vrD & vrJ & imm10_5 {\n\tvrD = vbitseti.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vbitseti.d;\n\n#lsx.txt vbitseti.d mask=0x73150000\t\n#0x73150000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vbitseti.d vrD, vrJ, imm10_6 is op16_31=0x7315 & vrD & vrJ & imm10_6 {\n\tvrD = vbitseti.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vbitrevi.b;\n\n#lsx.txt vbitrevi.b mask=0x73182000\t\n#0x73182000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vbitrevi.b vrD, vrJ, imm10_3 is op13_31=0x398c1 & vrD & vrJ & imm10_3 {\n\tvrD = vbitrevi.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vbitrevi.h;\n\n#lsx.txt vbitrevi.h mask=0x73184000\t\n#0x73184000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vbitrevi.h vrD, vrJ, imm10_4 is op14_31=0x1cc61 & vrD & vrJ & imm10_4 {\n\tvrD = vbitrevi.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vbitrevi.w;\n\n#lsx.txt vbitrevi.w mask=0x73188000\t\n#0x73188000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vbitrevi.w vrD, vrJ, imm10_5 is op15_31=0xe631 & vrD & vrJ & imm10_5 {\n\tvrD = vbitrevi.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vbitrevi.d;\n\n#lsx.txt vbitrevi.d mask=0x73190000\t\n#0x73190000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vbitrevi.d vrD, vrJ, imm10_6 is op16_31=0x7319 & vrD & vrJ & imm10_6 {\n\tvrD = vbitrevi.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsat.b;\n\n#lsx.txt vsat.b mask=0x73242000\t\n#0x73242000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsat.b vrD, vrJ, imm10_3 is op13_31=0x39921 & vrD & vrJ & imm10_3 {\n\tvrD = vsat.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsat.h;\n\n#lsx.txt vsat.h mask=0x73244000\t\n#0x73244000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsat.h vrD, vrJ, imm10_4 is op14_31=0x1cc91 & vrD & vrJ & imm10_4 {\n\tvrD = vsat.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsat.w;\n\n#lsx.txt vsat.w mask=0x73248000\t\n#0x73248000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsat.w vrD, vrJ, imm10_5 is op15_31=0xe649 & vrD & vrJ & imm10_5 {\n\tvrD = vsat.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsat.d;\n\n#lsx.txt vsat.d mask=0x73250000\t\n#0x73250000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsat.d vrD, vrJ, imm10_6 is op16_31=0x7325 & vrD & vrJ & imm10_6 {\n\tvrD = vsat.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsat.bu;\n\n#lsx.txt vsat.bu mask=0x73282000\t\n#0x73282000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsat.bu vrD, vrJ, imm10_3 is op13_31=0x39941 & vrD & vrJ & imm10_3 {\n\tvrD = vsat.bu(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsat.hu;\n\n#lsx.txt vsat.hu mask=0x73284000\t\n#0x73284000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsat.hu vrD, vrJ, imm10_4 is op14_31=0x1cca1 & vrD & vrJ & imm10_4 {\n\tvrD = vsat.hu(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsat.wu;\n\n#lsx.txt vsat.wu mask=0x73288000\t\n#0x73288000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsat.wu vrD, vrJ, imm10_5 is op15_31=0xe651 & vrD & vrJ & imm10_5 {\n\tvrD = vsat.wu(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsat.du;\n\n#lsx.txt vsat.du mask=0x73290000\t\n#0x73290000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsat.du vrD, vrJ, imm10_6 is op16_31=0x7329 & vrD & vrJ & imm10_6 {\n\tvrD = vsat.du(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vslli.b;\n\n#lsx.txt vslli.b mask=0x732c2000\t\n#0x732c2000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vslli.b vrD, vrJ, imm10_3 is op13_31=0x39961 & vrD & vrJ & imm10_3 {\n\tvrD = vslli.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vslli.h;\n\n#lsx.txt vslli.h mask=0x732c4000\t\n#0x732c4000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vslli.h vrD, vrJ, imm10_4 is op14_31=0x1ccb1 & vrD & vrJ & imm10_4 {\n\tvrD = vslli.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vslli.w;\n\n#lsx.txt vslli.w mask=0x732c8000\t\n#0x732c8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vslli.w vrD, vrJ, imm10_5 is op15_31=0xe659 & vrD & vrJ & imm10_5 {\n\tvrD = vslli.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vslli.d;\n\n#lsx.txt vslli.d mask=0x732d0000\t\n#0x732d0000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vslli.d vrD, vrJ, imm10_6 is op16_31=0x732d & vrD & vrJ & imm10_6 {\n\tvrD = vslli.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrli.b;\n\n#lsx.txt vsrli.b mask=0x73302000\t\n#0x73302000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsrli.b vrD, vrJ, imm10_3 is op13_31=0x39981 & vrD & vrJ & imm10_3 {\n\tvrD = vsrli.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsrli.h;\n\n#lsx.txt vsrli.h mask=0x73304000\t\n#0x73304000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrli.h vrD, vrJ, imm10_4 is op14_31=0x1ccc1 & vrD & vrJ & imm10_4 {\n\tvrD = vsrli.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrli.w;\n\n#lsx.txt vsrli.w mask=0x73308000\t\n#0x73308000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrli.w vrD, vrJ, imm10_5 is op15_31=0xe661 & vrD & vrJ & imm10_5 {\n\tvrD = vsrli.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrli.d;\n\n#lsx.txt vsrli.d mask=0x73310000\t\n#0x73310000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrli.d vrD, vrJ, imm10_6 is op16_31=0x7331 & vrD & vrJ & imm10_6 {\n\tvrD = vsrli.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrai.b;\n\n#lsx.txt vsrai.b mask=0x73342000\t\n#0x73342000\t0xffffe000\tv0:5,v5:5,u10:3\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0']\n:vsrai.b vrD, vrJ, imm10_3 is op13_31=0x399a1 & vrD & vrJ & imm10_3 {\n\tvrD = vsrai.b(vrD, vrJ, imm10_3:$(REGSIZE));\n}\n\ndefine pcodeop vsrai.h;\n\n#lsx.txt vsrai.h mask=0x73344000\t\n#0x73344000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrai.h vrD, vrJ, imm10_4 is op14_31=0x1ccd1 & vrD & vrJ & imm10_4 {\n\tvrD = vsrai.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrai.w;\n\n#lsx.txt vsrai.w mask=0x73348000\t\n#0x73348000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrai.w vrD, vrJ, imm10_5 is op15_31=0xe669 & vrD & vrJ & imm10_5 {\n\tvrD = vsrai.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrai.d;\n\n#lsx.txt vsrai.d mask=0x73350000\t\n#0x73350000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrai.d vrD, vrJ, imm10_6 is op16_31=0x7335 & vrD & vrJ & imm10_6 {\n\tvrD = vsrai.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrlni.b.h;\n\n#lsx.txt vsrlni.b.h mask=0x73404000\t\n#0x73404000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrlni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd01 & vrD & vrJ & imm10_4 {\n\tvrD = vsrlni.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrlni.h.w;\n\n#lsx.txt vsrlni.h.w mask=0x73408000\t\n#0x73408000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrlni.h.w vrD, vrJ, imm10_5 is op15_31=0xe681 & vrD & vrJ & imm10_5 {\n\tvrD = vsrlni.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrlni.w.d;\n\n#lsx.txt vsrlni.w.d mask=0x73410000\t\n#0x73410000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrlni.w.d vrD, vrJ, imm10_6 is op16_31=0x7341 & vrD & vrJ & imm10_6 {\n\tvrD = vsrlni.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrlni.d.q;\n\n#lsx.txt vsrlni.d.q mask=0x73420000\t\n#0x73420000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vsrlni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a1 & vrD & vrJ & imm10_7 {\n\tvrD = vsrlni.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vsrlrni.b.h;\n\n#lsx.txt vsrlrni.b.h mask=0x73444000\t\n#0x73444000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrlrni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd11 & vrD & vrJ & imm10_4 {\n\tvrD = vsrlrni.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrlrni.h.w;\n\n#lsx.txt vsrlrni.h.w mask=0x73448000\t\n#0x73448000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrlrni.h.w vrD, vrJ, imm10_5 is op15_31=0xe689 & vrD & vrJ & imm10_5 {\n\tvrD = vsrlrni.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrlrni.w.d;\n\n#lsx.txt vsrlrni.w.d mask=0x73450000\t\n#0x73450000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrlrni.w.d vrD, vrJ, imm10_6 is op16_31=0x7345 & vrD & vrJ & imm10_6 {\n\tvrD = vsrlrni.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrlrni.d.q;\n\n#lsx.txt vsrlrni.d.q mask=0x73460000\t\n#0x73460000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vsrlrni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a3 & vrD & vrJ & imm10_7 {\n\tvrD = vsrlrni.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.b.h;\n\n#lsx.txt vssrlni.b.h mask=0x73484000\t\n#0x73484000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrlni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd21 & vrD & vrJ & imm10_4 {\n\tvrD = vssrlni.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.h.w;\n\n#lsx.txt vssrlni.h.w mask=0x73488000\t\n#0x73488000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrlni.h.w vrD, vrJ, imm10_5 is op15_31=0xe691 & vrD & vrJ & imm10_5 {\n\tvrD = vssrlni.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.w.d;\n\n#lsx.txt vssrlni.w.d mask=0x73490000\t\n#0x73490000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrlni.w.d vrD, vrJ, imm10_6 is op16_31=0x7349 & vrD & vrJ & imm10_6 {\n\tvrD = vssrlni.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.d.q;\n\n#lsx.txt vssrlni.d.q mask=0x734a0000\t\n#0x734a0000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrlni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a5 & vrD & vrJ & imm10_7 {\n\tvrD = vssrlni.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.bu.h;\n\n#lsx.txt vssrlni.bu.h mask=0x734c4000\t\n#0x734c4000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrlni.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cd31 & vrD & vrJ & imm10_4 {\n\tvrD = vssrlni.bu.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.hu.w;\n\n#lsx.txt vssrlni.hu.w mask=0x734c8000\t\n#0x734c8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrlni.hu.w vrD, vrJ, imm10_5 is op15_31=0xe699 & vrD & vrJ & imm10_5 {\n\tvrD = vssrlni.hu.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.wu.d;\n\n#lsx.txt vssrlni.wu.d mask=0x734d0000\t\n#0x734d0000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrlni.wu.d vrD, vrJ, imm10_6 is op16_31=0x734d & vrD & vrJ & imm10_6 {\n\tvrD = vssrlni.wu.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrlni.du.q;\n\n#lsx.txt vssrlni.du.q mask=0x734e0000\t\n#0x734e0000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrlni.du.q vrD, vrJ, imm10_7 is op17_31=0x39a7 & vrD & vrJ & imm10_7 {\n\tvrD = vssrlni.du.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.b.h;\n\n#lsx.txt vssrlrni.b.h mask=0x73504000\t\n#0x73504000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrlrni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd41 & vrD & vrJ & imm10_4 {\n\tvrD = vssrlrni.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.h.w;\n\n#lsx.txt vssrlrni.h.w mask=0x73508000\t\n#0x73508000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrlrni.h.w vrD, vrJ, imm10_5 is op15_31=0xe6a1 & vrD & vrJ & imm10_5 {\n\tvrD = vssrlrni.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.w.d;\n\n#lsx.txt vssrlrni.w.d mask=0x73510000\t\n#0x73510000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrlrni.w.d vrD, vrJ, imm10_6 is op16_31=0x7351 & vrD & vrJ & imm10_6 {\n\tvrD = vssrlrni.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.d.q;\n\n#lsx.txt vssrlrni.d.q mask=0x73520000\t\n#0x73520000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrlrni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a9 & vrD & vrJ & imm10_7 {\n\tvrD = vssrlrni.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.bu.h;\n\n#lsx.txt vssrlrni.bu.h mask=0x73544000\t\n#0x73544000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrlrni.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cd51 & vrD & vrJ & imm10_4 {\n\tvrD = vssrlrni.bu.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.hu.w;\n\n#lsx.txt vssrlrni.hu.w mask=0x73548000\t\n#0x73548000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrlrni.hu.w vrD, vrJ, imm10_5 is op15_31=0xe6a9 & vrD & vrJ & imm10_5 {\n\tvrD = vssrlrni.hu.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.wu.d;\n\n#lsx.txt vssrlrni.wu.d mask=0x73550000\t\n#0x73550000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrlrni.wu.d vrD, vrJ, imm10_6 is op16_31=0x7355 & vrD & vrJ & imm10_6 {\n\tvrD = vssrlrni.wu.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrlrni.du.q;\n\n#lsx.txt vssrlrni.du.q mask=0x73560000\t\n#0x73560000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrlrni.du.q vrD, vrJ, imm10_7 is op17_31=0x39ab & vrD & vrJ & imm10_7 {\n\tvrD = vssrlrni.du.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vsrani.b.h;\n\n#lsx.txt vsrani.b.h mask=0x73584000\t\n#0x73584000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrani.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd61 & vrD & vrJ & imm10_4 {\n\tvrD = vsrani.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrani.h.w;\n\n#lsx.txt vsrani.h.w mask=0x73588000\t\n#0x73588000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrani.h.w vrD, vrJ, imm10_5 is op15_31=0xe6b1 & vrD & vrJ & imm10_5 {\n\tvrD = vsrani.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrani.w.d;\n\n#lsx.txt vsrani.w.d mask=0x73590000\t\n#0x73590000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrani.w.d vrD, vrJ, imm10_6 is op16_31=0x7359 & vrD & vrJ & imm10_6 {\n\tvrD = vsrani.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrani.d.q;\n\n#lsx.txt vsrani.d.q mask=0x735a0000\t\n#0x735a0000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vsrani.d.q vrD, vrJ, imm10_7 is op17_31=0x39ad & vrD & vrJ & imm10_7 {\n\tvrD = vsrani.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vsrarni.b.h;\n\n#lsx.txt vsrarni.b.h mask=0x735c4000\t\n#0x735c4000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vsrarni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd71 & vrD & vrJ & imm10_4 {\n\tvrD = vsrarni.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vsrarni.h.w;\n\n#lsx.txt vsrarni.h.w mask=0x735c8000\t\n#0x735c8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vsrarni.h.w vrD, vrJ, imm10_5 is op15_31=0xe6b9 & vrD & vrJ & imm10_5 {\n\tvrD = vsrarni.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vsrarni.w.d;\n\n#lsx.txt vsrarni.w.d mask=0x735d0000\t\n#0x735d0000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vsrarni.w.d vrD, vrJ, imm10_6 is op16_31=0x735d & vrD & vrJ & imm10_6 {\n\tvrD = vsrarni.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vsrarni.d.q;\n\n#lsx.txt vsrarni.d.q mask=0x735e0000\t\n#0x735e0000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vsrarni.d.q vrD, vrJ, imm10_7 is op17_31=0x39af & vrD & vrJ & imm10_7 {\n\tvrD = vsrarni.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.b.h;\n\n#lsx.txt vssrani.b.h mask=0x73604000\t\n#0x73604000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrani.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd81 & vrD & vrJ & imm10_4 {\n\tvrD = vssrani.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.h.w;\n\n#lsx.txt vssrani.h.w mask=0x73608000\t\n#0x73608000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrani.h.w vrD, vrJ, imm10_5 is op15_31=0xe6c1 & vrD & vrJ & imm10_5 {\n\tvrD = vssrani.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.w.d;\n\n#lsx.txt vssrani.w.d mask=0x73610000\t\n#0x73610000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrani.w.d vrD, vrJ, imm10_6 is op16_31=0x7361 & vrD & vrJ & imm10_6 {\n\tvrD = vssrani.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.d.q;\n\n#lsx.txt vssrani.d.q mask=0x73620000\t\n#0x73620000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrani.d.q vrD, vrJ, imm10_7 is op17_31=0x39b1 & vrD & vrJ & imm10_7 {\n\tvrD = vssrani.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.bu.h;\n\n#lsx.txt vssrani.bu.h mask=0x73644000\t\n#0x73644000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrani.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cd91 & vrD & vrJ & imm10_4 {\n\tvrD = vssrani.bu.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.hu.w;\n\n#lsx.txt vssrani.hu.w mask=0x73648000\t\n#0x73648000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrani.hu.w vrD, vrJ, imm10_5 is op15_31=0xe6c9 & vrD & vrJ & imm10_5 {\n\tvrD = vssrani.hu.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.wu.d;\n\n#lsx.txt vssrani.wu.d mask=0x73650000\t\n#0x73650000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrani.wu.d vrD, vrJ, imm10_6 is op16_31=0x7365 & vrD & vrJ & imm10_6 {\n\tvrD = vssrani.wu.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrani.du.q;\n\n#lsx.txt vssrani.du.q mask=0x73660000\t\n#0x73660000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrani.du.q vrD, vrJ, imm10_7 is op17_31=0x39b3 & vrD & vrJ & imm10_7 {\n\tvrD = vssrani.du.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.b.h;\n\n#lsx.txt vssrarni.b.h mask=0x73684000\t\n#0x73684000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrarni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cda1 & vrD & vrJ & imm10_4 {\n\tvrD = vssrarni.b.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.h.w;\n\n#lsx.txt vssrarni.h.w mask=0x73688000\t\n#0x73688000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrarni.h.w vrD, vrJ, imm10_5 is op15_31=0xe6d1 & vrD & vrJ & imm10_5 {\n\tvrD = vssrarni.h.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.w.d;\n\n#lsx.txt vssrarni.w.d mask=0x73690000\t\n#0x73690000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrarni.w.d vrD, vrJ, imm10_6 is op16_31=0x7369 & vrD & vrJ & imm10_6 {\n\tvrD = vssrarni.w.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.d.q;\n\n#lsx.txt vssrarni.d.q mask=0x736a0000\t\n#0x736a0000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrarni.d.q vrD, vrJ, imm10_7 is op17_31=0x39b5 & vrD & vrJ & imm10_7 {\n\tvrD = vssrarni.d.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.bu.h;\n\n#lsx.txt vssrarni.bu.h mask=0x736c4000\t\n#0x736c4000\t0xffffc000\tv0:5,v5:5,u10:4\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0']\n:vssrarni.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cdb1 & vrD & vrJ & imm10_4 {\n\tvrD = vssrarni.bu.h(vrD, vrJ, imm10_4:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.hu.w;\n\n#lsx.txt vssrarni.hu.w mask=0x736c8000\t\n#0x736c8000\t0xffff8000\tv0:5,v5:5,u10:5\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0']\n:vssrarni.hu.w vrD, vrJ, imm10_5 is op15_31=0xe6d9 & vrD & vrJ & imm10_5 {\n\tvrD = vssrarni.hu.w(vrD, vrJ, imm10_5:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.wu.d;\n\n#lsx.txt vssrarni.wu.d mask=0x736d0000\t\n#0x736d0000\t0xffff0000\tv0:5,v5:5,u10:6\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0']\n:vssrarni.wu.d vrD, vrJ, imm10_6 is op16_31=0x736d & vrD & vrJ & imm10_6 {\n\tvrD = vssrarni.wu.d(vrD, vrJ, imm10_6:$(REGSIZE));\n}\n\ndefine pcodeop vssrarni.du.q;\n\n#lsx.txt vssrarni.du.q mask=0x736e0000\t\n#0x736e0000\t0xfffe0000\tv0:5,v5:5,u10:7\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0']\n:vssrarni.du.q vrD, vrJ, imm10_7 is op17_31=0x39b7 & vrD & vrJ & imm10_7 {\n\tvrD = vssrarni.du.q(vrD, vrJ, imm10_7:$(REGSIZE));\n}\n\ndefine pcodeop vextrins.d;\n\n#lsx.txt vextrins.d mask=0x73800000\t\n#0x73800000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vextrins.d vrD, vrJ, imm10_8 is op18_31=0x1ce0 & vrD & vrJ & imm10_8 {\n\tvrD = vextrins.d(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vextrins.w;\n\n#lsx.txt vextrins.w mask=0x73840000\t\n#0x73840000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vextrins.w vrD, vrJ, imm10_8 is op18_31=0x1ce1 & vrD & vrJ & imm10_8 {\n\tvrD = vextrins.w(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vextrins.h;\n\n#lsx.txt vextrins.h mask=0x73880000\t\n#0x73880000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vextrins.h vrD, vrJ, imm10_8 is op18_31=0x1ce2 & vrD & vrJ & imm10_8 {\n\tvrD = vextrins.h(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vextrins.b;\n\n#lsx.txt vextrins.b mask=0x738c0000\t\n#0x738c0000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vextrins.b vrD, vrJ, imm10_8 is op18_31=0x1ce3 & vrD & vrJ & imm10_8 {\n\tvrD = vextrins.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vshuf4i.b;\n\n#lsx.txt vshuf4i.b mask=0x73900000\t\n#0x73900000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vshuf4i.b vrD, vrJ, imm10_8 is op18_31=0x1ce4 & vrD & vrJ & imm10_8 {\n\tvrD = vshuf4i.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vshuf4i.h;\n\n#lsx.txt vshuf4i.h mask=0x73940000\t\n#0x73940000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vshuf4i.h vrD, vrJ, imm10_8 is op18_31=0x1ce5 & vrD & vrJ & imm10_8 {\n\tvrD = vshuf4i.h(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vshuf4i.w;\n\n#lsx.txt vshuf4i.w mask=0x73980000\t\n#0x73980000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vshuf4i.w vrD, vrJ, imm10_8 is op18_31=0x1ce6 & vrD & vrJ & imm10_8 {\n\tvrD = vshuf4i.w(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vshuf4i.d;\n\n#lsx.txt vshuf4i.d mask=0x739c0000\t\n#0x739c0000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vshuf4i.d vrD, vrJ, imm10_8 is op18_31=0x1ce7 & vrD & vrJ & imm10_8 {\n\tvrD = vshuf4i.d(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vbitseli.b;\n\n#lsx.txt vbitseli.b mask=0x73c40000\t\n#0x73c40000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vbitseli.b vrD, vrJ, imm10_8 is op18_31=0x1cf1 & vrD & vrJ & imm10_8 {\n\tvrD = vbitseli.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vandi.b;\n\n#lsx.txt vandi.b mask=0x73d00000\t\n#0x73d00000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vandi.b vrD, vrJ, imm10_8 is op18_31=0x1cf4 & vrD & vrJ & imm10_8 {\n\tvrD = vandi.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vori.b;\n\n#lsx.txt vori.b mask=0x73d40000\t\n#0x73d40000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vori.b vrD, vrJ, imm10_8 is op18_31=0x1cf5 & vrD & vrJ & imm10_8 {\n\tvrD = vori.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vxori.b;\n\n#lsx.txt vxori.b mask=0x73d80000\t\n#0x73d80000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vxori.b vrD, vrJ, imm10_8 is op18_31=0x1cf6 & vrD & vrJ & imm10_8 {\n\tvrD = vxori.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vnori.b;\n\n#lsx.txt vnori.b mask=0x73dc0000\t\n#0x73dc0000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vnori.b vrD, vrJ, imm10_8 is op18_31=0x1cf7 & vrD & vrJ & imm10_8 {\n\tvrD = vnori.b(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\ndefine pcodeop vldi;\n\n#lsx.txt vldi mask=0x73e00000\t\n#0x73e00000\t0xfffc0000\tv0:5, s5:13\t['vreg0_5_s0', 'simm5_13_s0']\n:vldi vrD, simm5_13 is op18_31=0x1cf8 & vrD & simm5_13 {\n\tvrD = vldi(vrD, simm5_13:$(REGSIZE));\n}\n\ndefine pcodeop vpermi.w;\n\n#lsx.txt vpermi.w mask=0x73e40000\t\n#0x73e40000\t0xfffc0000\tv0:5,v5:5,u10:8\t['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0']\n:vpermi.w vrD, vrJ, imm10_8 is op18_31=0x1cf9 & vrD & vrJ & imm10_8 {\n\tvrD = vpermi.w(vrD, vrJ, imm10_8:$(REGSIZE));\n}\n\n" }, { "path": "pypcode/processors/Loongarch/data/languages/lvz.sinc", "content": "define pcodeop gcsrxchg;\n\n#lvz.txt gcsrxchg mask=0x05000000\t[@lvz]\n#0x05000000\t0xff000000\tr0:5, r5:5,u10:14\t['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0']\n:gcsrxchg RD, RJsrc,imm10_14 is op24_31=0x5 & RD & RJsrc & imm10_14 {\n\tRD = gcsrxchg(RD, RJsrc, imm10_14:$(REGSIZE));\n}\n\ndefine pcodeop gtlbclr;\n\n#lvz.txt gtlbclr mask=0x06482001\t[@lvz]\n:gtlbclr is instword=0x06482001 {\n\tgtlbclr();\n}\n\ndefine pcodeop gtlbflush;\n\n#lvz.txt gtlbflush mask=0x06482401\t[@lvz]\n#0x06482401\t0xffffffff\t\t['']\n:gtlbflush is instword=0x06482401 {\n\tgtlbflush();\n}\n\ndefine pcodeop gtlbsrch;\n\n#lvz.txt gtlbsrch mask=0x06482801\t[@lvz]\n:gtlbsrch is instword=0x06482801 {\n\tgtlbsrch();\n}\n\ndefine pcodeop gtlbrd;\n\n#lvz.txt gtlbrd mask=0x06482c01\t[@lvz]\n:gtlbrd is instword=0x06482c01 {\n\tgtlbrd();\n}\n\ndefine pcodeop gtlbwr;\n\n#lvz.txt gtlbwr mask=0x06483001\t[@lvz]\n:gtlbwr is instword=0x06483001 {\n\tgtlbwr();\n}\n\ndefine pcodeop gtlbfill;\n\n#lvz.txt gtlbfill mask=0x06483401\t[@lvz]\n:gtlbfill is instword=0x06483401 {\n\tgtlbfill();\n}\n\ndefine pcodeop hvcl;\n\n#lvz.txt hypcall mask=0x002b8000\t[@lvz, @orig_name=hvcl]\n#0x002b8000\t0xffff8000\tu0:15\t['imm0_15_s0']\n:hvcl imm0_15 is op15_31=0x57 & imm0_15 {\n\thvcl(imm0_15:$(REGSIZE));\n}\n\n" }, { "path": "pypcode/processors/Loongarch/data/manuals/loongarch.idx", "content": "@LoongArch-Vol1-EN.pdf[LoongArch Reference Manual - Volume 1: Basic Architecture]\nadd,\t23\nsub,\t23\naddi,\t24\naddu16id,\t24\nalsl,\t25\nlu12i.w,\t26\nlu32i.d,\t26\nlu52i.d,\t26\nslt,\t26\nsltu,\t26\nslti,\t27\nsltui,\t27\npcaddi,\t28\npcaddu12i,\t28\npcaddu18i,\t28\npcalau12i,\t28\nand,\t29\nor,\t29\nnor,\t29\nxor,\t29\nandn,\t29\norn,\t29\nandi,\t30\nori,\t30\nxori,\t30\nmul,\t31\nmulh,\t31\nmulw,\t32\ndiv,\t32\nmod,\t32\nsll.w,\t34\nsrl.w,\t34\nsra.w,\t34\nrotr.w,\t34\nslli.w,\t35\nsrli.w,\t35\nsrai.w,\t35\nrotri.w,\t35\nsll.d,\t36\nsrl.d,\t36\nsra.d,\t36\nrotr.d,\t36\nslli.d,\t37\nsrli.d,\t37\nsrai.d,\t37\nrotri.d,\t37\next.w.b,\t38\next.w.h,\t38\nclo,\t38\nclz,\t38\ncto,\t38\nctz,\t38\nbytepick,\t40\nrevb,\t40\nrevh,\t41\nbitrev.4b,\t42\nbitrev.8b,\t42\nbitrev.w,\t43\nbitrev.d,\t43\nbstrins,\t43\nbstrpick,\t44\nmaskeqz,\t44\nmasknez,\t44\nbeq,\t45\nbne,\t45\nblt,\t45\nbge,\t45\nbltu,\t45\nbgeu,\t45\nbeqz,\t46\nbnez,\t46\nb,\t47\nbl,\t47\njirl,\t48\nld,\t49\nst,\t49\nldx,\t51\nstx,\t51\nldptr,\t53\nstptr,\t53\npreld,\t54\npreldx,\t55\nlgdt,\t56\nldle,\t56\nstgt,\t56\nstle,\t56\namswap,\t60\namadd,\t60\namand,\t60\namor,\t60\namxor,\t60\nammax,\t60\nammin,\t60\nll,\t62\nsc,\t62\ndbar,\t62\nibar,\t63\ncrc,\t63\ncrcc,\t63\nsyscall,\t64\nbreak,\t64\nasrtle,\t65\nasrtgt,\t65\nrdtime,\t65\nrdtimel,\t65\nrdtimeh,\t65\ncpucfg,\t65\nfadd,\t78\nfsub,\t78\nfmul,\t78\nfmadd,\t80\nfmsub,\t80\nfnmadd,\t80\nfnmsub,\t80\nfmax,\t81\nfmin,\t81\nfmaxa,\t82\nfmina,\t82\nfabs,\t83\nfneg,\t83\nfsqrt,\t83\nfrecip,\t83\nfrsqrt,\t83\nfscaleb,\t85\nflogb,\t85\nfcopysign,\t85\nfclass,\t86\nfcmp,\t86\nfcvt,\t88\nffint,\t88\nftint,\t88\nftintrm,\t90\nftintrp,\t90\nftintrz,\t90\nftintrne,\t90\nfrint,\t92\nfmov,\t93\nfsel,\t94\nmovgr2fr,\t94\nmovgr2frh,\t94\nmovfr2gr,\t95\nmovfrh2gr,\t95\nmovgr2fcsr,\t95\nmovfcsr2gr,\t95\nmovfr2cf,\t96\nmovcf2fr,\t96\nmovgr2cf,\t96\nmovcf2gr,\t96\nbceqz,\t97\nbcnez,\t97\nfld,\t97\nfst,\t97\nfldx,\t98\nfstx,\t98\nfldgt,\t100\nfldle,\t100\nfstgt,\t100\nfstle,\t100\ncsrrd,\t103\ncsrwr,\t103\ncsrxchg,\t103\niocsrrd,\t104\niocsrwr,\t104\ncacop,\t104\ntlbsrch,\t105\ntlbrd,\t106\ntlbwr,\t106\ntlbfill,\t106\ntlbclr,\t107\ntlbflush,\t107\ninvtlb,\t107\nlddir,\t108\nldpte,\t108\nertn,\t109\ndbcl,\t110\nidle,\t110\n\n\n\n\n" }, { "path": "pypcode/processors/Loongarch/data/patterns/loongarch_patterns.xml", "content": "\n\n \n \n \n 0x20 0x00 0x00 0x4c \n \n \n 0x63 ......00 111..... 0x02 01100001 .....000 11...... 0x29 \n \n \n \n \n \n \n \n \n 11111111 ......11 ........ 01010011 \n 0x80 0x01 0x00 0x4c \n \n \n 0x63 ......00 111..... 0x02 \n \n \n \n \n \n \n \n 0x20 0x00 0x00 0x4c \n \n \n 0x63 ......00 111..... 0x02 \n \n \n \n \n" }, { "path": "pypcode/processors/Loongarch/data/patterns/patternconstraints.xml", "content": "\n \n loongarch_patterns.xml\n \n\n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_60.cspec", "content": "\n\n\n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \t\n \n \n\t\n\t\n \n \n \n\t\n\t\n \n \n \n \n \n \n \n\t\n \n \n\n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_60.ldefs", "content": "\n\n\n \n \n Renesas M16C/60 16-Bit MicroComputer\n \n \n \n\n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_60.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_60.slaspec", "content": "# Renesas M16C/60 16-Bit MicroComputer\n\n#\n# Memory Architecture\n#\ndefine endian=little;\n\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=3 default;\ndefine space register type=register_space size=2;\n\n#\n# General Registers\n#\ndefine register offset=0x0000 size=2 [\n R1 R3 R0 R2 A0 A1\n];\n\ndefine register offset=0x0000 size=1 [\n R1L R1H _ _ R0L R0H\n];\n\ndefine register offset=0x0000 size=4 [\n R3R1 R2R0 A1A0\n];\n\ndefine register offset=0x1000 size=3 [\n PC # Program Counter \n];\n\ndefine register offset=0x2000 size=3 [\n INTB # Interrupt Table Register\n];\n\ndefine register offset=0x2000 size=2 [\n INTBL INTBH\n];\n\ndefine register offset=0x3000 size=2 [\n SP # Current Stack Pointer (Represents active stack pointer: ISP or USP)\n FB # Frame Base Register \n SB # Static Base Register\n FLG # Flag Register\n ISP # Interrupt Stack Pointer\n];\n\n# Flag Register Contents (FLG)\n#\n# b15 - Reserved area\n# b14:b12 - Processor interrupt priority level\n# b11:b8 - Reserved area\n# b7 - (U) Stack pointer select flag\n# b6 - (I) Interrupt enable flag\n# b5 - (O) Overflow flag\n# b4 - (B) Register bank select flag\n# b3 - (S) Sign flag\n# b2 - (Z) Zero flag\n# b1 - (D) Debug flag\n# b0 - (C) Carry flag\n@define CARRY \"FLG[0,1]\"\n@define DEBUG \"FLG[1,1]\"\n@define ZERO \"FLG[2,1]\"\n@define SIGN \"FLG[3,1]\"\n@define REG_BANK \"FLG[4,1]\"\n@define OVERFLOW \"FLG[5,1]\"\n@define INTERRUPT \"FLG[6,1]\"\n@define STACK_SEL \"FLG[7,1]\"\n@define IPL \"FLG[12,3]\"\n\n# Define context bits\ndefine register offset=0xA000 size=4 contextreg;\n\ndefine context contextreg\n dstFollowsSrc = (0,1) # =1 destination add-on data follows 4-bit encoded source add-on data\n # =2 destination add-on data follows 8-bit data\n;\n\ndefine token b0(8)\n b0_0007 = (0,7)\n;\n\ndefine token b1(8)\n b1_d2 = (0,1)\n b1_d3 = (0,2)\n b1_d3_2 = (2,2)\n b1_2_reg8 = (2,2)\n b1_2_regAx = (2,2)\n b1_3_regAx = (3,3)\n b1_3_reg8 = (3,3)\n b1_size_0 = (0,0)\n b1_0407 = (4,7)\n b1_0307 = (3,7)\n b1_0107 = (1,7)\n b1_0007 = (0,7)\n b1_0002 = (0,2)\n b1_bit = (0,2)\n;\n\ndefine token b2(8)\n b2_d4_reg8 = (0,1)\n b2_s4_reg8 = (4,5)\n b2_d4_reg16 = (0,1)\n b2_s4_reg16 = (4,5)\n b2_d4_reg32 = (0,0)\n b2_s4_reg32 = (4,4)\n b2_reg32 = (4,4)\n b2_d4_regAxSF = (0,1) # selects A0, A1, SB or FB\n b2_s4_regAxSF = (4,5) # selects A0, A1, SB or FB\n b2_d4_regAx = (0,0)\n b2_s4_regAx = (4,4)\n b2_reg16 = (4,6)\n b2_creg16 = (4,6)\n b2_d4 = (0,3)\n b2_d4_3 = (3,3)\n b2_d4_23 = (2,3)\n b2_d4_13 = (1,3)\n b2_s4 = (4,7)\n b2_s4_23 = (6,7)\n b2_s4_13 = (5,7)\n b2_shiftSign_7 = (7,7)\n b2_shiftSign_3 = (3,3)\n b2_0707 = (7,7)\n b2_0607 = (6,7)\n b2_0507 = (5,7)\n b2_0407 = (4,7)\n b2_0406 = (4,6)\n b2_0307 = (3,7)\n b2_0303 = (3,3)\n b2_0007 = (0,7)\n b2_0003 = (0,3)\n b2_0002 = (0,2)\n b2_simm4_0407 = (4,7) signed\n b2_simm4_0003 = (0,3) signed\n;\n\ndefine token b3(8)\n b3_0407 = (4,7)\n b3_0007 = (0,7)\n b3_0003 = (0,3)\n;\n\ndefine token b4(8)\n b4_0007 = (0,7)\n;\n\ndefine token b5(8)\n b5_0007 = (0,7)\n;\n\ndefine token b6(8)\n b6_0007 = (0,7)\n;\n\ndefine token imm8(8)\n simm8_dat = (0,7) signed\n imm8_dat = (0,7)\n imm8_base = (3,7) # bit,base byte displacement\n imm8_bit = (0,2) # bit,base bit number\n simm8_base = (3,7) signed # bit,base signed byte displacement\n simm8_bit = (0,2) # bit,base signed bit number\n imm6_dat = (0,5) # int number\n cnd8_dat = (0,7)\n imm8_0607 = (6,7)\n imm8_0407 = (4,7)\n imm8_0003 = (0,3)\n regBit7 = (7,7)\n regBit6 = (6,6)\n regBit5 = (5,5)\n regBit4 = (4,4)\n regBit3 = (3,3)\n regBit2 = (2,2)\n regBit1 = (1,1)\n regBit0 = (0,0)\n;\n\ndefine token imm16(16)\n simm16_dat = (0,15) signed\n imm16_dat = (0,15)\n imm16_base = (3,15) # bit,base byte displacement\n imm16_bit = (0, 2) # bit,base bit number\n;\n\ndefine token imm24(24)\n simm24_dat = (0,23) signed\n imm24_dat = (0,23)\n simm20_dat = (0,19)\n imm20_dat = (0,19)\n;\n\ndefine token imm32(32)\n simm32_dat = (0,31) signed\n imm32_dat = (0,31)\n;\n\nattach variables [ b2_s4_reg16 b2_d4_reg16 ] [ R0 R1 R2 R3 ];\nattach variables [ b2_s4_reg8 b2_d4_reg8 ] [ R0L R0H R1L R1H ];\nattach variables [ b1_2_reg8 b1_3_reg8 ] [ R0L R0H ];\nattach variables [ b2_s4_regAx b2_d4_regAx b1_3_regAx b1_2_regAx ] [ A0 A1 ];\nattach variables [ b2_s4_regAxSF b2_d4_regAxSF ] [ A0 A1 SB FB ];\nattach variables [ b2_reg16 ] [ R0 R1 R2 R3 A0 A1 _ _ ];\nattach variables [ b2_creg16 ] [ _ INTBL INTBH FLG ISP SP SB FB ];\nattach variables [ b2_reg32 b2_d4_reg32 ] [ R2R0 R3R1 ];\n\n#\n# PCode Op\n# \ndefine pcodeop Break; # BRK\ndefine pcodeop DecimalAdd; # DADD\ndefine pcodeop DecimalAddWithCarry; # DADC\ndefine pcodeop DecimalSubtractWithBorrow; # DSBB\ndefine pcodeop DecimalSubtract; # DSUB\ndefine pcodeop Wait; # WAIT\n\n#\n# FLAG MACROS...\n#\n# Set zero and sign flags from result\nmacro setResultFlags(result) {\n $(SIGN) = (result s< 0x0);\n $(ZERO) = (result == 0x0);\n}\n\n# Set carry and overflow flags for addition\nmacro setAdd3Flags(v1, v2, v3) {\n local add13 = v1 + v3;\n $(CARRY) = carry(v1,v3) || carry(v2,add13);\n $(OVERFLOW) = scarry(v1,v3) || scarry(v2,add13);\n}\n\n# Set carry and overflow flags for addition\nmacro setAddFlags(v1, v2) {\n $(CARRY) = carry(v1, v2);\n $(OVERFLOW) = scarry(v1, v2);\n}\n\n# Set overflow flags for subtraction of op3,op2 from op1 (op1-op2-op3)\nmacro setSubtract3Flags(v1, v2, v3) {\n local add12 = v1 - v2;\n $(CARRY) = (v1 >= v2) || (add12 >= v3);\n $(OVERFLOW) = sborrow(v1, v2) || sborrow(add12, v3);\n}\n\n# Set overflow flags for subtraction of op2 from op1 (op1-op2)\nmacro setSubtractFlags(v1, v2) {\n $(CARRY) = (v1 s>= v2);\n $(OVERFLOW) = sborrow(v1, v2);\n}\n\nmacro push1(val) {\n SP = SP - 1;\n ptr:3 = zext(SP);\n *:1 ptr = val;\n}\n\nmacro push2(val) {\n SP = SP - 2;\n ptr:3 = zext(SP);\n *:2 ptr = val;\n}\n\nmacro push3(val) {\n SP = SP - 3;\n ptr:3 = zext(SP);\n *:3 ptr = val;\n}\n\nmacro push4(val) {\n SP = SP - 4;\n ptr:3 = zext(SP);\n *:4 ptr = val;\n}\n\nmacro pop1(val) {\n ptr:3 = zext(SP);\n val = *:1 ptr;\n SP = SP + 1;\n}\n\nmacro pop2(val) {\n ptr:3 = zext(SP);\n val = *:2 ptr;\n SP = SP + 2;\n}\n\nmacro pop3(val) {\n ptr:3 = zext(SP);\n val = *:3 ptr;\n SP = SP + 3;\n}\n\nmacro pop4(val) {\n ptr:3 = zext(SP);\n val = *:4 ptr;\n SP = SP + 4;\n}\n\n#\n# Source operand location data\n#\n# Obtain base offset displacement for [AX | SB | FB] - AX and SB uses unsigned displacements, FB uses signed displacement\nsrc4dsp8: imm8_dat^\":8\" is b1_0007; b2_s4; imm8_dat { export *[const]:2 imm8_dat; }\nsrc4dsp8: simm8_dat^\":8\" is b1_0007; b2_s4=0xb; simm8_dat { export *[const]:2 simm8_dat; } \nsrc4dsp16: imm16_dat^\":16\" is b1_0007; b2_s4; imm16_dat { export *[const]:2 imm16_dat; }\n\n# src4... Handle 4-bit encoded Source specified by b2_s4(4-bits)\n# Variable length pattern starting at instruction byte b1\n# associated src4 add-on data immediately follows instruction byte b2\n# abs16 cases are broken out differently to facilitate export of constant addresses in certain cases\n# 1-Byte source value/location specified by 4-bit encoding (b2_d4)\nsrc4B: b2_s4_reg8 is b1_0007; b2_s4_23=0x0 & b2_s4_reg8 { export b2_s4_reg8; } # Rx\nsrc4B: b2_s4_regAx is b1_0007; b2_s4_13=0x2 & b2_s4_regAx { tmp:1 = b2_s4_regAx:1; export tmp; } # Ax\nsrc4B: [b2_s4_regAx] is b1_0007; b2_s4_13=0x3 & b2_s4_regAx { ptr:3 = zext(b2_s4_regAx); export *:1 ptr; } # [Ax]\nsrc4B: src4dsp8^[b2_s4_regAxSF] is (b1_0007; b2_s4_23=0x2 & b2_s4_regAxSF) ... & src4dsp8 { ptr:3 = zext(b2_s4_regAxSF + src4dsp8); export *:1 ptr; } # dsp:8[Ax|SB|FB]\nsrc4B: src4dsp16^[b2_s4_regAxSF] is (b1_0007; b2_s4_23=0x3 & b2_s4_regAxSF) ... & src4dsp16 { ptr:3 = zext(b2_s4_regAxSF + src4dsp16); export *:1 ptr; } # dsp:16[Ax|SB|FB]\nsrc4B: imm16_dat is b1_0007; b2_s4=0xf; imm16_dat { export *:1 imm16_dat; } # abs16 (special constant address case)\n\n# 2-Byte source value/location specified by 2-bit encoding (b2_d4)\nsrc4W: b2_s4_reg16 is b1_0007; b2_s4_23=0x0 & b2_s4_reg16 { export b2_s4_reg16; } # Rx\nsrc4W: b2_s4_regAx is b1_0007; b2_s4_13=0x2 & b2_s4_regAx { export b2_s4_regAx; } # Ax\nsrc4W: [b2_s4_regAx] is b1_0007; b2_s4_13=0x3 & b2_s4_regAx { ptr:3 = zext(b2_s4_regAx); export *:2 ptr; } # [Ax]\nsrc4W: src4dsp8^[b2_s4_regAxSF] is (b1_0007; b2_s4_23=0x2 & b2_s4_regAxSF) ... & src4dsp8 { ptr:3 = zext(b2_s4_regAxSF + src4dsp8); export *:2 ptr; } # dsp:8[Ax|SB|FB]\nsrc4W: src4dsp16^[b2_s4_regAxSF] is (b1_0007; b2_s4_23=0x3 & b2_s4_regAxSF) ... & src4dsp16 { ptr:3 = zext(b2_s4_regAxSF + src4dsp16); export *:2 ptr; } # dsp:16[Ax|SB|FB]\nsrc4W: imm16_dat is b1_0007; b2_s4=0xf; imm16_dat { export *:2 imm16_dat; } # abs16 (special constant address case)\n\n#\n# Destination operand location data (may also be used as a source in certain cases)\n#\n# Skip instruction and source add-on bytes which occur before destination add-on bytes\n# Starting position is at b1\nskipBytesBeforeDst4: is b1_0007; b2_s4 { }\nskipBytesBeforeDst4: is dstFollowsSrc=1 & b1_0007; b2_s4_23=0x2; imm8_dat { } # src4: dsp8\nskipBytesBeforeDst4: is dstFollowsSrc=1 & b1_0007; b2_s4_23=0x3; imm16_dat { } # src4: dsp16/abs16\nskipBytesBeforeDst4: is dstFollowsSrc=2 & b1_0007; b2_d4; imm8_dat { } # dsp8\n\n# Obtain base offset displacement for [AX | SB | FB] - AX and SB uses unsigned displacements, FB uses signed displacement\ndst4dsp8: imm8_dat^\":8\" is (skipBytesBeforeDst4; imm8_dat) { export *[const]:2 imm8_dat; }\ndst4dsp8: simm8_dat^\":8\" is (b1_0007; b2_d4=0xb) ... & (skipBytesBeforeDst4; simm8_dat) { export *[const]:2 simm8_dat; } \ndst4dsp16: imm16_dat^\":16\" is (skipBytesBeforeDst4; imm16_dat) { export *[const]:2 imm16_dat; }\n\n# dst4... Handle 4-bit encoded Destination specified by b2_d4(4-bits)\n# Ax direct case is read-only! Instruction must use dst4Ax for write/update case\n# Variable length pattern starting at instruction byte b1\n# abs16 cases are broken out differently to facilitate export of constant addresses in certain cases\n# 1-Byte destination value/location specified by 4-bit encoding (b2_d4)\ndst4B: b2_d4_reg8 is b1_0007; b2_d4_23=0x0 & b2_d4_reg8 { export b2_d4_reg8; } # Rx\ndst4B: b2_d4_regAx is b1_0007; b2_d4_13=0x2 & b2_d4_regAx { tmp:1 = b2_d4_regAx:1; export tmp; } # Ax - read-only use !\ndst4B: [b2_d4_regAx] is b1_0007; b2_d4_13=0x3 & b2_d4_regAx { ptr:3 = zext(b2_d4_regAx); export *:1 ptr; } # [Ax]\ndst4B: dst4dsp8^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x2 & b2_d4_regAxSF) ... & dst4dsp8 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp8); export *:1 ptr; } # dsp:8[Ax|SB|FB]\ndst4B: dst4dsp16^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x3 & b2_d4_regAxSF) ... & dst4dsp16 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp16); export *:1 ptr; } # dsp:16[Ax|SB]\ndst4B: imm16_dat is (b1_0007; b2_d4=0xf) ... & (skipBytesBeforeDst4; imm16_dat) { export *:1 imm16_dat; } # abs16 (special constant address case)\n\n# 2-Byte destination value/location specified by 4-bit encoding (b2_d4)\ndst4W: b2_d4_reg16 is b1_0007; b2_d4_23=0x0 & b2_d4_reg16 { export b2_d4_reg16; } # Rx\ndst4W: b2_d4_regAx is b1_0007; b2_d4_13=0x2 & b2_d4_regAx { export b2_d4_regAx; } # Ax\ndst4W: [b2_d4_regAx] is b1_0007; b2_d4_13=0x3 & b2_d4_regAx { ptr:3 = zext(b2_d4_regAx); export *:2 ptr; } # [Ax]\ndst4W: dst4dsp8^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x2 & b2_d4_regAxSF) ... & dst4dsp8 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp8); export *:2 ptr; } # dsp:8[Ax|SB|FB]\ndst4W: dst4dsp16^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x3 & b2_d4_regAxSF) ... & dst4dsp16 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp16); export *:2 ptr; } # dsp:16[Ax|SB]\ndst4W: imm16_dat is (b1_0007; b2_d4=0xf) ... & (skipBytesBeforeDst4; imm16_dat) { export *:2 imm16_dat; } # abs16 (special constant address case)\n\n# 4-Byte destination value/location specified by 4-bit encoding (b2_d4)\ndst4L: b2_d4_reg32 is b1_0007; b2_d4_13=0x0 & b2_d4_reg32 { export b2_d4_reg32; } # Rx\ndst4L: A1A0 is A1A0 & b1_0007; b2_d4=0x4 { export A1A0; } # A1A0\ndst4L: [b2_d4_regAx] is b1_0007; b2_d4_13=0x3 & b2_d4_regAx { ptr:3 = zext(b2_d4_regAx); export *:4 ptr; } # [Ax]\ndst4L: dst4dsp8^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x2 & b2_d4_regAxSF) ... & dst4dsp8 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp8); export *:4 ptr; } # dsp:8[Ax|SB|FB]\ndst4L: dst4dsp16^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x3 & b2_d4_regAxSF) ... & dst4dsp16 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp16); export *:4 ptr; } # dsp:16[Ax|SB]\ndst4L: imm16_dat is (b1_0007; b2_d4=0xf) ... & (skipBytesBeforeDst4; imm16_dat) { export *:4 imm16_dat; } # abs16 (special constant address case)\n\n# 3-Byte destination value/location specified by 4-bit encoding (b2_d4) - use DST4L to constrain, and dst4L for register Ax/Rx non-memory cases\ndst4T: [b2_d4_regAx] is b1_0007; b2_d4_13=0x3 & b2_d4_regAx { ptr:3 = zext(b2_d4_regAx); export *:3 ptr; } # [Ax]\ndst4T: dst4dsp8^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x2 & b2_d4_regAxSF) ... & dst4dsp8 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp8); export *:3 ptr; } # dsp:8[Ax|SB|FB]\ndst4T: dst4dsp16^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x3 & b2_d4_regAxSF) ... & dst4dsp16 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp16); export *:3 ptr; } # dsp:16[Ax|SB]\ndst4T: imm16_dat is (b1_0007; b2_d4=0xf) ... & (skipBytesBeforeDst4; imm16_dat) { export *:3 imm16_dat; } # abs16 (special constant address case)\n\n# 3-Byte effective address specified by 4-bit encoding (b2_d4)\ndst4A: dst4dsp8^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x2 & b2_d4_regAxSF) ... & dst4dsp8 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp8); export ptr; } # dsp:8[Ax|SB|FB]\ndst4A: dst4dsp16^[b2_d4_regAxSF] is (b1_0007; b2_d4_23=0x3 & b2_d4_regAxSF) ... & dst4dsp16 { ptr:3 = zext(b2_d4_regAxSF + dst4dsp16); export ptr; } # dsp:16[Ax|SB]\ndst4A: imm16_dat is (b1_0007; b2_d4=0xf) ... & (skipBytesBeforeDst4; imm16_dat) { export *[const]:3 imm16_dat; } # abs16 (special constant address case)\n\n# Ax destination specified by 4-bit encoding (b2_d4)\n# NOTE! Ax destination is special case and must be handled separately by each instruction\n# Starting position is at instruction b1\ndst4Ax: b2_d4_regAx is b1_0007; b2_d4_regAx { export b2_d4_regAx; }\n\n# 1/2-Byte destination value/location specified by 4-bit encoding (b2_d4)\n# This handles the case for dst4B, dst4W and dst4L where 5-bit encoded Source (src4) add-on bytes may exist before Destination add-on bytes\n# Variable length pattern starting at instruction byte b1\ndst4B_afterSrc4: dst4B is dst4B [ dstFollowsSrc=1; ] { export dst4B; }\n\ndst4W_afterSrc4: dst4W is dst4W [ dstFollowsSrc=1; ] { export dst4W; }\n\ndst4L_afterSrc4: dst4L is dst4L [ dstFollowsSrc=1; ] { export dst4L; }\n\n#\n# The following macros are used to constrain bit patterns when using dst4\n# These should be used by constructor pattern matching instead of the corresponding dst4 sub-constructor\n#\n@define DST4AX \"((b1_0007; b2_d4_13=0x2) & dst4Ax)\"\n@define DST4A \"((b1_0007; b2_d4_3=1) ... & dst4A)\"\n@define DST4T \"((b1_0007; (b2_d4_3=1 | b2_d4_13=3)) ... & dst4T)\"\n\n# Skip instruction and source add-on bytes which occur before destination add-on bytes\n# Starting position is at b1\nskipBytesBeforeDst2: is b1_d2 { }\nskipBytesBeforeDst2: is dstFollowsSrc=2 & b1_d2; imm8_dat { } # dsp8\n\n#\n# destination value/location specified by 2/3-bit encoding, R0H/R0L choice controlled by destination-bit (b1_0002)\n#\ndst2B: R0L is (R0L & b1_d3=0x4) { export R0L; }\ndst2B: R0H is (R0H & b1_d3=0x0) { export R0H; }\ndst2B: imm8_dat^[SB] is (SB & b1_d2=0x1) ... & (skipBytesBeforeDst2; imm8_dat) { ptr:3 = zext(SB + imm8_dat); export *:1 ptr; }\ndst2B: simm8_dat^[FB] is (FB & b1_d2=0x2) ... & (skipBytesBeforeDst2; simm8_dat) { ptr:3 = zext(FB + simm8_dat); export *:1 ptr; }\ndst2B: imm16_dat is (b1_d2=0x3) ... & (skipBytesBeforeDst2; imm16_dat) { export *:1 imm16_dat; }\n\n#\n# destination value/location specified by 3-bit encoding (must be constrained by DST3B or DST3B_AFTER_DSP8)\n#\ndst3B: R0L is (R0L & b1_d3=0x4) { export R0L; }\ndst3B: R0H is (R0H & b1_d3=0x3) { export R0H; }\ndst3B: imm8_dat^[SB] is (SB & b1_d3=0x5) ... & (skipBytesBeforeDst2; imm8_dat) { ptr:3 = zext(SB + imm8_dat); export *:1 ptr; }\ndst3B: simm8_dat^[FB] is (FB & b1_d3=0x6) ... & (skipBytesBeforeDst2; simm8_dat) { ptr:3 = zext(FB + simm8_dat); export *:1 ptr; }\ndst3B: imm16_dat is (b1_d3=0x7) ... & (skipBytesBeforeDst2; imm16_dat) { export *:1 imm16_dat; }\n\n# 1-Byte destination value/location specified by 3-bit encoding (b2_d3)\n# This handles the case for dst3B where Dsp8 add-on bytes always exist before Destination add-on bytes\n# Variable length pattern starting at instruction byte b1\ndst3B_afterDsp8: dst3B is dst3B [ dstFollowsSrc=2; ] { export dst3B; }\n\n#\n# The following macros are used to constrain bit patterns when using dst2 for a 3-bit src/dest\n# These should be used by constructor pattern matching instead of the corresponding dst4 sub-constructor\n#\n@define DST3B \"((b1_d3=3 | b1_d3_2=1) ... & dst3B)\"\n@define DST3B_AFTER_DSP8 \"((b1_d3=3 | b1_d3_2=1) ... & dst3B_afterDsp8)\"\n\n# Special dsp8[SP] source/destination - starting point is on dsp8 data\ndsp8spB: simm8_dat^\":8\"^[SP] is simm8_dat & SP { ptr:3 = zext(SP + simm8_dat); export *:1 ptr; }\n\ndsp8spW: simm8_dat^\":8\"^[SP] is simm8_dat & SP { ptr:3 = zext(SP + simm8_dat); export *:2 ptr; }\n\n# Special dsp20[A0] source/destination - starting point is on dsp20 data\ndsp20A0B: simm20_dat^\":20[\"^A0^\"]\" is A0 & simm20_dat { ptr:3 = zext(A0 + simm20_dat); export *:1 ptr; }\n\ndsp20A0W: simm20_dat^\":20[\"^A0^\"]\" is A0 & simm20_dat { ptr:3 = zext(A0 + simm20_dat); export *:2 ptr; }\n\n#\n# Bit base - associated add-on data immediately follows instruction byte b2\n# There are three cases which must be broken-out by instruction (regBase, memBaseAx, memBase)\n#\n# bit-base is bit,byte specified by [Ax] (constrain instruction pattern using b2_d4_13=0x3) - contexts of Ax are exported\nmemBaseAx: [b2_d4_regAx] is b1_0007; b2_d4_13=0x3 & b2_d4_regAx { export b2_d4_regAx; } # [Ax] (special case! bit operand does not appear)\n\n# bit-base is 16-bit register: Rx or Ax (constrain instruction pattern using b2_d4_3=0)\nregBase: b2_d4_reg16 is b1_0007; b2_d4_23=0x0 & b2_d4_reg16 { export b2_d4_reg16; } # Rx\nregBase: b2_d4_regAx is b1_0007; b2_d4_13=0x2 & b2_d4_regAx { export b2_d4_regAx; } # Ax \n\n# bit-base is byte location within memory\nmemBase: imm8_base^\":8\"^[b2_d4_regAxSF] is b1_0007; b2_d4_23=0x2 & b2_d4_regAxSF; imm8_base { ptr:3 = zext(b2_d4_regAxSF + imm8_base); export *:1 ptr; } # dsp:8[Ax|SB]\nmemBase: simm8_base^\":8\"^[FB] is b1_0007; b2_d4_23=0x2 & b2_d4=0xb & FB; simm8_base { ptr:3 = zext(FB + simm8_base); export *:1 ptr; } # dsp:8[FB]\nmemBase: imm16_base^\":16\"^[b2_d4_regAxSF] is b1_0007; b2_d4_23=0x3 & b2_d4_regAxSF; imm16_base { ptr:3 = zext(b2_d4_regAxSF + imm16_base); export *:1 ptr; } # dsp:16[Ax|SB]\nmemBase: imm16_base^\":16\" is b1_0007; b2_d4=0xf; imm16_base { export *:1 imm16_base; } # abs16 (special constant address case)\n\nmemBase11: imm8_dat^\":11\"^[SB] is SB & b1_0007; imm8_dat { ptr:3 = zext(SB + imm8_dat); export *:1 ptr; } # dsp:11[SB]\n\n# Bit operand associated with regBase operand\n# TODO: imm8_0407=0 constraint removed due to sleigh compiler issue\nregBit: imm8_0003 is b1_0007; b2_d4; imm8_0003 { export *[const]:1 imm8_0003; } # Rx, Ax\n\n# Bit operand associated with memBase operand\nmemBit: imm8_bit is b1_0007; b2_d4; imm8_bit { export *[const]:1 imm8_bit; } # dsp:8[Ax|SB|FB]\nmemBit: imm16_bit is b1_0007; b2_d4_23=3; imm16_bit { export *[const]:1 imm16_bit; } # dsp:16[Ax|SB], base:16\n\n#\n# Immediate data operand\n# Fixed length - current position is at start of immediate data\n#\nsrcImm3: \"#\"^b2_0002 is b2_0002 { export *[const]:1 b2_0002; }\nsrcImm8: \"#\"^imm8_dat is imm8_dat { export *[const]:1 imm8_dat; }\nsrcImm16: \"#\"^imm16_dat is imm16_dat { export *[const]:2 imm16_dat; }\n\nsrcSimm8: \"#\"^simm8_dat is simm8_dat { export *[const]:1 simm8_dat; }\nsrcSimm16: \"#\"^simm16_dat is simm16_dat { export *[const]:2 simm16_dat; }\n\n# Signed immediate data from 4-bit value: -8 <= value <= 7\n# NOTE! There are two different cases based upon the bits used from b2\nsrcSimm4_0407: \"#\"^b2_simm4_0407 is b2_simm4_0407 { export *[const]:1 b2_simm4_0407; }\nsrcSimm4_0003: \"#\"^b2_simm4_0003 is b2_simm4_0003 { export *[const]:1 b2_simm4_0003; }\n\n# Signed immediate shift amount from 4-bit value: -8 <= value <= -1 || 1 <= value <= 8\n# NOTE! There are two different cases based upon the bits used from b2\nsrcSimm4Shift_0407: \"#\"^val is b2_shiftSign_7=0 & b2_0406 [ val = b2_0406 + 1; ] { export *[const]:1 val; }\nsrcSimm4Shift_0407: \"#\"^val is b2_shiftSign_7=1 & b2_0406 [ val = -(b2_0406 + 1); ] { export *[const]:1 val; }\nsrcSimm4Shift_0003: \"#\"^val is b2_shiftSign_3=0 & b2_0002 [ val = b2_0002 + 1; ] { export *[const]:1 val; }\nsrcSimm4Shift_0003: \"#\"^val is b2_shiftSign_3=1 & b2_0002 [ val = -(b2_0002 + 1); ] { export *[const]:1 val; }\n\nsrcZero8: \"#0\" is b1_0007 { export 0:1; }\n\n# special 6-bit immediate for INT number\nsrcIntNum: \"#\"^imm6_dat is imm6_dat { export *[const]:1 imm6_dat; }\n\n#\n# Offset label operand\n#\nabs20offset: imm20_dat is imm20_dat { export *:1 imm20_dat; }\n\nabs20offsetW: imm20_dat is imm20_dat { export *:2 imm20_dat; }\n\nabs16offset: imm16_dat is imm16_dat { export *:1 imm16_dat; }\n\n# Relative address offsets\nrel16offset1: offs is simm16_dat [ offs = inst_start + 1 + simm16_dat; ] { export *:1 offs; }\n\nrel8offset1: offs is simm8_dat [ offs = inst_start + 1 + simm8_dat; ] { export *:1 offs; }\nrel8offset2: offs is simm8_dat [ offs = inst_start + 2 + simm8_dat; ] { export *:1 offs; }\n\nrel3offset2: offs is b1_0002 [ offs = inst_start + 2 + b1_0002; ] { export *:1 offs; }\n\nreloffset_dst4W: dst4W is dst4W { local reladdr = inst_start + dst4W; export *:3 reladdr; }\n\nreloffset_dst4L: dst4L is dst4L { local reladdr = inst_start + dst4L; export *:3 reladdr; }\n\nreloffset_dst4T: dst4T is $(DST4T) { local reladdr = inst_start + dst4T; export *:3 reladdr; }\n\n#\n# Conditionals\n#\ncnd8: \"GEU\" is cnd8_dat=0x00 { tstCnd:1 = ($(CARRY) == 1); export tstCnd; } # Equal to or greater than (<=), C flag is 1 \ncnd8: \"GTU\" is cnd8_dat=0x01 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 1); export tstCnd; } # Greater than (<)\ncnd8: \"EQ\" is cnd8_dat=0x02 { tstCnd:1 = ($(ZERO) == 1); export tstCnd; } # Equal to (=), Z flag is 1\ncnd8: \"N\" is cnd8_dat=0x03 { tstCnd:1 = ($(SIGN) == 1); export tstCnd; } # Negative (0>)\ncnd8: \"LE\" is cnd8_dat=0x04 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 1); export tstCnd; } # Equal to or less than (signed value) (>=)\ncnd8: \"O\" is cnd8_dat=0x05 { tstCnd:1 = ($(OVERFLOW) == 1); export tstCnd; } # O flag is 1\ncnd8: \"GE\" is cnd8_dat=0x06 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 0); export tstCnd; } # Equal to or greater than (signed value) (<=)\ncnd8: \"LTU\" is cnd8_dat=0xf8 { tstCnd:1 = ($(CARRY) == 0); export tstCnd; } # less than (>), C flag is 0\ncnd8: \"LEU\" is cnd8_dat=0xf9 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 0); export tstCnd; } # Equal to or less than (>=)\ncnd8: \"NE\" is cnd8_dat=0xfa { tstCnd:1 = ($(ZERO) == 0); export tstCnd; } # Not Equal to (=), Z flag is 0 \ncnd8: \"PZ\" is cnd8_dat=0xfb { tstCnd:1 = ($(SIGN) == 0); export tstCnd; } # Positive or zero (0<=)\ncnd8: \"GT\" is cnd8_dat=0xfc { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 0); export tstCnd; } # Greater than (signed value) (<)\ncnd8: \"NO\" is cnd8_dat=0xfd { tstCnd:1 = ($(OVERFLOW) == 0); export tstCnd; } # O flag is 0\ncnd8: \"LT\" is cnd8_dat=0xfe { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 1); export tstCnd; } # less than (signed value) (<=)\n\nb2cnd4: \"GEU\" is b2_0003=0x0 { tstCnd:1 = ($(CARRY) == 1); export tstCnd; } # Equal to or greater than (<=), C flag is 1 \nb2cnd4: \"GTU\" is b2_0003=0x1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 1); export tstCnd; } # Greater than (<)\nb2cnd4: \"EQ\" is b2_0003=0x2 { tstCnd:1 = ($(ZERO) == 1); export tstCnd; } # Equal to (=), Z flag is 1\nb2cnd4: \"N\" is b2_0003=0x3 { tstCnd:1 = ($(SIGN) == 1); export tstCnd; } # Negative (0>)\nb2cnd4: \"LTU\" is b2_0003=0x4 { tstCnd:1 = ($(CARRY) == 0); export tstCnd; } # less than (>), C flag is 0\nb2cnd4: \"LEU\" is b2_0003=0x5 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 0); export tstCnd; } # Equal to or less than (>=)\nb2cnd4: \"NE\" is b2_0003=0x6 { tstCnd:1 = ($(ZERO) == 0); export tstCnd; } # Not Equal to (=), Z flag is 0\nb2cnd4: \"PZ\" is b2_0003=0x7 { tstCnd:1 = ($(SIGN) == 0); export tstCnd; } # Positive or zero (0<=)\nb2cnd4: \"LE\" is b2_0003=0x8 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 1); export tstCnd; } # Equal to or less than (signed value) (>=)\nb2cnd4: \"O\" is b2_0003=0x9 { tstCnd:1 = ($(OVERFLOW) == 1); export tstCnd; } # O flag is 1\nb2cnd4: \"GE\" is b2_0003=0xa { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 0); export tstCnd; } # Equal to or greater than (signed value) (<=)\nb2cnd4: \"GT\" is b2_0003=0xc { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 0); export tstCnd; } # Greater than (signed value) (<)\nb2cnd4: \"NO\" is b2_0003=0xd { tstCnd:1 = ($(OVERFLOW) == 0); export tstCnd; } # O flag is 0\nb2cnd4: \"LT\" is b2_0003=0xe { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 1); export tstCnd; } # less than (signed value) (<=)\n\n# Special case of b2cnd4 where b2_0003=1 (see JCnd)\nb2cnd3: \"LE\" is b2_0002=0x0 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 1); export tstCnd; } # Equal to or less than (signed value) (>=)\nb2cnd3: \"O\" is b2_0002=0x1 { tstCnd:1 = ($(OVERFLOW) == 1); export tstCnd; } # O flag is 1\nb2cnd3: \"GE\" is b2_0002=0x2 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 0); export tstCnd; } # Equal to or greater than (signed value) (<=)\nb2cnd3: \"GT\" is b2_0002=0x4 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 0); export tstCnd; } # Greater than (signed value) (<)\nb2cnd3: \"NO\" is b2_0002=0x5 { tstCnd:1 = ($(OVERFLOW) == 0); export tstCnd; } # O flag is 0\nb2cnd3: \"LT\" is b2_0002=0x6 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 1); export tstCnd; } # less than (signed value) (<=)\n\nb1cnd3: \"LTU\" is b1_0002=4 { tstCnd:1 = ($(CARRY) == 0); export tstCnd; } # less than (>), C flag is 0\nb1cnd3: \"LEU\" is b1_0002=5 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 0); export tstCnd; } # Equal to or less than (>=)\nb1cnd3: \"NE\" is b1_0002=6 { tstCnd:1 = ($(ZERO) == 0); export tstCnd; } # Not Equal to (=), Z flag is 0 \nb1cnd3: \"PZ\" is b1_0002=7 { tstCnd:1 = ($(SIGN) == 0); export tstCnd; } # Positive or zero (0<=)\nb1cnd3: \"GEU\" is b1_0002=0 { tstCnd:1 = ($(CARRY) == 1); export tstCnd; } # Equal to or greater than (<=), C flag is 1 \nb1cnd3: \"GTU\" is b1_0002=1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 1); export tstCnd; } # Greater than (<)\nb1cnd3: \"EQ\" is b1_0002=2 { tstCnd:1 = ($(ZERO) == 1); export tstCnd; } # Equal to (=), Z flag is 1\nb1cnd3: \"N\" is b1_0002=3 { tstCnd:1 = ($(SIGN) == 1); export tstCnd; } # Negative (0>)\n\n#\n# Flag bit operand\n#\nflagBit: \"C\" is b2_0406=0 { export 0:2; }\nflagBit: \"D\" is b2_0406=1 { export 1:2; }\nflagBit: \"Z\" is b2_0406=2 { export 2:2; }\nflagBit: \"S\" is b2_0406=3 { export 3:2; }\nflagBit: \"B\" is b2_0406=4 { export 4:2; }\nflagBit: \"O\" is b2_0406=5 { export 5:2; }\nflagBit: \"I\" is b2_0406=6 { export 6:2; }\nflagBit: \"U\" is b2_0406=7 { export 7:2; }\n\n#\n# Instruction Constructors\n#\n### ABS ###\n:ABS.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xf) ... & dst4B {\n local tmp = dst4B;\n $(OVERFLOW) = (tmp == 0x80);\n local ztst = (tmp s< 0);\n tmp = (zext(ztst) * -tmp) + (zext(!ztst) * tmp);\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# 0111 0110 1111 0100 ABS.B A0\n# 0111 0110 1111 0001 ABS.B R0H\n:ABS.B dst4Ax is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xf) & $(DST4AX) {\n local tmp = dst4Ax:1;\n $(OVERFLOW) = (tmp == 0x80);\n local ztst = (tmp s< 0);\n tmp = (zext(ztst) * -tmp) + (zext(!ztst) * tmp);\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n:ABS.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0xf) ... & dst4W {\n local tmp = dst4W;\n $(OVERFLOW) = (tmp == 0x8000);\n local ztst = (tmp s< 0);\n tmp = (zext(ztst) * -tmp) + (zext(!ztst) * tmp);\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### ADC ###\n\n# (1) ADC.B #simm, dst\n:ADC.B srcSimm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x6) ... & dst4B); srcSimm8 {\n tmp:1 = dst4B;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, srcSimm8, c);\n tmp = tmp + srcSimm8 + c;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADC.B #simm, Ax\n:ADC.B srcSimm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x6) & $(DST4AX)); srcSimm8 {\n tmp:1 = dst4Ax:1;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, srcSimm8, c);\n tmp = tmp + srcSimm8 + c;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ADC.W #simm, dst\n:ADC.W srcSimm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x6) ... & dst4W); srcSimm16 {\n tmp:2 = dst4W;\n c:2 = zext($(CARRY));\n setAdd3Flags(tmp, srcSimm16, c);\n tmp = tmp + srcSimm16 + c;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADC.B src, dst\n:ADC.B src4B, dst4B_afterSrc4 is (b1_0107=0x58 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4;\n src:1 = src4B;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, src, c);\n tmp = tmp + src + c;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADC.B src, Ax\n:ADC.B src4B, dst4Ax is (b1_0107=0x58 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1;\n src:1 = src4B;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, src, c);\n tmp = tmp + src + c;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ADC.W src, dst\n:ADC.W src4W, dst4W_afterSrc4 is (b1_0107=0x58 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4;\n src:2 = src4W;\n c:2 = zext($(CARRY));\n setAdd3Flags(tmp, src, c);\n tmp = tmp + src + c;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n\n### ADCF ###\n\n:ADCF.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xe) ... & dst4B {\n tmp:1 = dst4B;\n c:1 = $(CARRY);\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n:ADCF.B dst4Ax is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xe) & $(DST4AX) {\n tmp:1 = dst4Ax:1;\n c:1 = $(CARRY);\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n:ADCF.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0xe) ... & dst4W {\n tmp:2 = dst4W;\n c:2 = zext($(CARRY));\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### ADD ###\n\n# (1) ADD.B:G #simm, dst\n:ADD^\".B:G\" srcSimm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x4) ... & dst4B); srcSimm8 {\n tmp:1 = dst4B;\n setAddFlags(tmp, srcSimm8);\n tmp = tmp + srcSimm8;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADD.B:G #simm, Ax\n:ADD^\".B:G\" srcSimm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x4) & $(DST4AX)); srcSimm8 {\n tmp:1 = dst4Ax:1;\n setAddFlags(tmp, srcSimm8);\n tmp = tmp + srcSimm8;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ADD.W:G #simm, dst\n:ADD^\".W:G\" srcSimm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x4) ... & dst4W); srcSimm16 {\n tmp:2 = dst4W;\n setAddFlags(tmp, srcSimm16);\n tmp = tmp + srcSimm16;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADD.B:Q #simm4, dst\n:ADD^\".B:Q\" srcSimm4_0407, dst4B is (b1_0107=0x64 & b1_size_0=0; srcSimm4_0407) ... & dst4B {\n tmp:1 = dst4B;\n setAddFlags(tmp, srcSimm4_0407);\n tmp = tmp + srcSimm4_0407;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADD.B:Q #simm4, Ax\n:ADD^\".B:Q\" srcSimm4_0407, dst4Ax is (b1_0107=0x64 & b1_size_0=0; srcSimm4_0407) & $(DST4AX) {\n tmp:1 = dst4Ax:1;\n setAddFlags(tmp, srcSimm4_0407);\n tmp = tmp + srcSimm4_0407;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ADD.W:Q #simm4, dst\n:ADD^\".W:Q\" srcSimm4_0407, dst4W is (b1_0107=0x64 & b1_size_0=1; srcSimm4_0407) ... & dst4W {\n tmp:2 = dst4W;\n imm:2 = sext(srcSimm4_0407);\n setAddFlags(tmp, imm);\n tmp = tmp + imm;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (3) ADD.B:S #imm, dst\n:ADD^\".B:S\" srcSimm8, dst3B_afterDsp8 is (b1_0307=0x10; srcSimm8) ... & $(DST3B_AFTER_DSP8) {\n tmp:1 = dst3B_afterDsp8;\n setAddFlags(tmp, srcSimm8);\n tmp = tmp + srcSimm8;\n dst3B_afterDsp8 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) ADD.B:G src, dst\n:ADD^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x50 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4;\n src:1 = src4B;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) ADD.B:G src, Ax\n:ADD^\".B:G\" src4B, dst4Ax is (b1_0107=0x50 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1;\n src:1 = src4B;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (4) ADD.W:G src, dst\n:ADD^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x50 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4;\n src:2 = src4W;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (5) ADD.B:S src, R0H/R0L\n:ADD^\".B:S\" dst2B, b1_2_reg8 is (b1_0307=0x4 & b1_2_reg8) ... & dst2B {\n src:1 = dst2B;\n setAddFlags(b1_2_reg8, src);\n b1_2_reg8 = b1_2_reg8 + src;\n setResultFlags(b1_2_reg8);\n}\n\n# (6) ADD.B:G #simm, SP\n:ADD^\".B:G\" srcSimm8, SP is SP & b1_0107=0x3e & b1_size_0=0; b2_0007=0xeb; srcSimm8 {\n imm:2 = sext(srcSimm8);\n setAddFlags(SP, imm);\n SP = SP + imm;\n setResultFlags(SP);\n}\n\n# (6) ADD.W:G #simm, SP\n:ADD^\".W:G\" srcSimm16, SP is SP & b1_0107=0x3e & b1_size_0=1; b2_0007=0xeb; srcSimm16 {\n setAddFlags(SP, srcSimm16);\n SP = SP + srcSimm16;\n setResultFlags(SP);\n}\n\n# (7) ADD.W:Q #simm, SP\n:ADD^\".B:Q\" srcSimm4_0003, SP is SP & b1_0007=0x7d; b2_0407=0xb & srcSimm4_0003 {\n imm:2 = sext(srcSimm4_0003);\n setAddFlags(SP, imm);\n SP = SP + imm;\n setResultFlags(SP);\n}\n\n### ADJNZ ###\n\n:ADJNZ.B srcSimm4_0407, dst4B is ((b1_0107=0x7c & b1_size_0=0; srcSimm4_0407) ... & dst4B); rel8offset2 {\n tmp:1 = dst4B + srcSimm4_0407;\n dst4B = tmp;\n if (tmp != 0) goto rel8offset2;\n}\n\n:ADJNZ.B srcSimm4_0407, dst4Ax is ((b1_0107=0x7c & b1_size_0=0; srcSimm4_0407) & $(DST4AX)); rel8offset2 {\n tmp:1 = dst4Ax:1 + srcSimm4_0407;\n dst4Ax = zext(tmp);\n if (tmp != 0) goto rel8offset2;\n}\n\n:ADJNZ.W srcSimm4_0407, dst4W is ((b1_0107=0x7c & b1_size_0=1; srcSimm4_0407) ... & dst4W); rel8offset2 {\n tmp:2 = dst4W + sext(srcSimm4_0407);\n dst4W = tmp;\n if (tmp != 0) goto rel8offset2;\n}\n\n### AND ###\n\n# (1) AND.B:G #imm, dst\n:AND^\".B:G\" srcImm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x2) ... & dst4B); srcImm8 {\n tmp:1 = dst4B & srcImm8;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) AND.B:G #imm, Ax\n:AND^\".B:G\" srcImm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x2) & $(DST4AX)); srcImm8 {\n tmp:1 = dst4Ax:1 & srcImm8;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) AND.W:G #imm, dst\n:AND^\".W:G\" srcImm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x2) ... & dst4W); srcImm16 {\n tmp:2 = dst4W & srcImm16;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) AND.B:S #imm, dst\n:AND^\".B:S\" srcImm8, dst3B_afterDsp8 is (b1_0307=0x12; srcImm8) ... & $(DST3B_AFTER_DSP8) {\n tmp:1 = dst3B_afterDsp8 & srcImm8;\n dst3B_afterDsp8 = tmp;\n setResultFlags(tmp);\n}\n\n# (3) AND.B:G src, dst\n:AND^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x48 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4 & src4B;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (3) AND.B:G src, Ax\n:AND^\".B:G\" src4B, dst4Ax is (b1_0107=0x48 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1 & src4B;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (3) AND.W:G src, dst\n:AND^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x48 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4 & src4W;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) AND.B:S src, R0L/R0H\n:AND^\".B:S\" dst2B, b1_2_reg8 is (b1_0307=0x2 & b1_2_reg8) ... & dst2B {\n tmp:1 = dst2B & b1_2_reg8;\n b1_2_reg8 = tmp;\n setResultFlags(tmp);\n}\n\n### BAND ###\n\n# BAND bit,Rx/Ax\n:BAND regBit, regBase is (b1_0007=0x7e; b2_0407=0x4 & b2_d4_3=0) ... & regBase ... & regBit {\n bitValue:2 = (regBase >> regBit) & 1;\n $(CARRY) = $(CARRY) & bitValue:1;\n}\n\n# BAND [Ax]\n:BAND memBaseAx is (b1_0007=0x7e; b2_0407=0x4 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n bitValue:1 = (val >> bit) & 1;\n $(CARRY) = $(CARRY) & bitValue;\n}\n\n# BAND bit,base\n:BAND memBit, memBase is (b1_0007=0x7e; b2_0407=0x4) ... & memBase & memBit {\n bitValue:1 = (memBase >> memBit) & 1;\n $(CARRY) = $(CARRY) & bitValue;\n}\n\n\n### BCLR ###\n\n# (1) BCLR:G bit,Rx/Ax\n:BCLR^\":G\" regBit, regBase is (b1_0007=0x7e; b2_0407=0x8 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = ~(1 << regBit);\n regBase = regBase & mask;\n}\n\n# (1) BCLR:G [Ax]\n:BCLR^\":G\" memBaseAx is (b1_0007=0x7e; b2_0407=0x8 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = ~(1 << bit);\n *:1 ptr = val & mask;\n}\n\n# (1) BCLR:G bit,base\n:BCLR^\":G\" memBit, memBase is (b1_0007=0x7e; b2_0407=0x8) ... & memBase & memBit {\n mask:1 = ~(1 << memBit);\n memBase = memBase & mask;\n}\n\n# (2) BCLR:S bit,base:11[SB]\n:BCLR^\":S\" b1_bit, memBase11 is (b1_0307=0x08 & b1_bit) ... & memBase11 {\n mask:1 = ~(1 << b1_bit);\n memBase11 = memBase11 & mask;\n}\n\n### BMcnd ###\n\n# (1) BMcnd bit,Rx/Ax\n:BM^cnd8 regBit, regBase is ((b1_0007=0x7e; b2_0407=0x2 & b2_d4_3=0) ... & regBase ... & regBit); cnd8 {\n mask:2 = ~(1 << regBit);\n regBase = ((zext(cnd8) << regBit) | (regBase & mask));\n}\n\n# (1) BMcnd [Ax]\n:BM^cnd8 memBaseAx is ((b1_0007=0x7e; b2_0407=0x2 & b2_d4_13=0x3) & memBaseAx); cnd8 {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = ~(1 << bit);\n *:1 ptr = ((cnd8 << bit) | (val & mask));\n}\n\n# (1) BMcnd bit,base\n:BM^cnd8 memBit, memBase is ((b1_0007=0x7e; b2_0407=0x2) ... & memBase & memBit); cnd8 {\n mask:1 = ~(1 << memBit);\n memBase = ((cnd8 << memBit) | (memBase & mask));\n}\n\n# (2) BMcnd C\n:BM^b2cnd4 \"C\" is b1_0007=0x7d; b2_0407=0xd & b2cnd4 {\n $(CARRY) = b2cnd4;\n}\n\n### BNAND ###\n\n# BNAND bit,Rx/Ax\n:BNAND regBit, regBase is (b1_0007=0x7e; b2_0407=0x5 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n $(CARRY) = $(CARRY) && (bitValue == 0);\n}\n\n# BNAND [Ax]\n:BNAND memBaseAx is (b1_0007=0x7e; b2_0407=0x5 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n $(CARRY) = $(CARRY) && (bitValue == 0);\n}\n\n# BNAND bit,base\n:BNAND memBit, memBase is (b1_0007=0x7e; b2_0407=0x5) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n $(CARRY) = $(CARRY) && (bitValue == 0);\n}\n\n### BNOR ###\n\n# BNOR bit,Rx/Ax\n:BNOR regBit, regBase is (b1_0007=0x7e; b2_0407=0x7 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n $(CARRY) = $(CARRY) || (bitValue == 0);\n}\n\n# BNOR [Ax]\n:BNOR memBaseAx is (b1_0007=0x7e; b2_0407=0x7 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n $(CARRY) = $(CARRY) || (bitValue == 0);\n}\n\n# BNOR bit,base\n:BNOR memBit, memBase is (b1_0007=0x7e; b2_0407=0x7) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n $(CARRY) = $(CARRY) || (bitValue == 0);\n}\n\n### BNOT ###\n\n# (1) BNOT:G bit,Rx/Ax\n:BNOT^\":G\" regBit, regBase is (b1_0007=0x7e; b2_0407=0xa & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (~regBase & mask);\n regBase = (regBase & ~mask) | bitValue;\n}\n\n# (1) BNOT:G [Ax]\n:BNOT^\":G\" memBaseAx is (b1_0007=0x7e; b2_0407=0xa & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (~val & mask);\n *:1 ptr = (val & ~mask) | bitValue;\n}\n\n# (1) BNOT:G bit,base\n:BNOT^\":G\" memBit, memBase is (b1_0007=0x7e; b2_0407=0xa) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n val:1 = memBase;\n bitValue:1 = (~val & mask);\n memBase = (val & ~mask) | bitValue;\n}\n\n# (2) BNOT:S bit,base:11[SB]\n:BNOT^\":S\" b1_bit, memBase11 is (b1_0307=0x0a & b1_bit) ... & memBase11 {\n mask:1 = (1 << b1_bit);\n val:1 = memBase11;\n bitValue:1 = (~val & mask);\n memBase11 = (val & ~mask) | bitValue;\n}\n\n### BNTST ###\n\n# BNTST bit,Rx/Ax\n:BNTST regBit, regBase is (b1_0007=0x7e; b2_0407=0x3 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = z;\n $(ZERO) = z;\n}\n\n# BNTST [Ax]\n:BNTST memBaseAx is (b1_0007=0x7e; b2_0407=0x3 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = z;\n $(ZERO) = z;\n}\n\n# BNTST bit,base\n:BNTST memBit, memBase is (b1_0007=0x7e; b2_0407=0x3) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = z;\n $(ZERO) = z;\n}\n\n### BNXOR ###\n\n# BNXOR bit,Rx/Ax\n:BNXOR regBit, regBase is (b1_0007=0x7e; b2_0407=0xd & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n $(CARRY) = $(CARRY) ^ (bitValue == 0);\n}\n\n# BNXOR [Ax]\n:BNXOR memBaseAx is (b1_0007=0x7e; b2_0407=0xd & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n $(CARRY) = $(CARRY) ^ (bitValue == 0);\n}\n\n# BNXOR bit,base\n:BNXOR memBit, memBase is (b1_0007=0x7e; b2_0407=0xd) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n $(CARRY) = $(CARRY) ^ (bitValue == 0);\n}\n\n### BOR ###\n\n# BOR bit,Rx/Ax\n:BOR regBit, regBase is (b1_0007=0x7e; b2_0407=0x6 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n $(CARRY) = $(CARRY) || (bitValue != 0);\n}\n\n# BOR [Ax]\n:BOR memBaseAx is (b1_0007=0x7e; b2_0407=0x6 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n $(CARRY) = $(CARRY) || (bitValue != 0);\n}\n\n# BOR bit,base\n:BOR memBit, memBase is (b1_0007=0x7e; b2_0407=0x6) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n $(CARRY) = $(CARRY) || (bitValue != 0);\n}\n\n### BRK ###\n\n:BRK is b1_0007=0x0 {\n # most likely not necessary to model break behavior\n Break();\n}\n\n### BSET ###\n\n# (1) BSET:G bit,Rx/Ax\n:BSET^\":G\" regBit, regBase is (b1_0007=0x7e; b2_0407=0x9 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n regBase = regBase | mask;\n}\n\n# (1) BSET:G [Ax]\n:BSET^\":G\" memBaseAx is (b1_0007=0x7e; b2_0407=0x9 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n *:1 ptr = val | mask;\n}\n\n# (1) BSET:G bit,base\n:BSET^\":G\" memBit, memBase is (b1_0007=0x7e; b2_0407=0x9) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n memBase = memBase | mask;\n}\n\n# (2) BSET:S bit,base:11[SB]\n:BSET^\":S\" b1_bit, memBase11 is (b1_0307=0x09 & b1_bit) ... & memBase11 {\n mask:1 = (1 << b1_bit);\n memBase11 = memBase11 | mask;\n}\n\n### BTST ###\n\n# (1) BTST:G bit,Rx/Ax\n:BTST^\":G\" regBit, regBase is (b1_0007=0x7e; b2_0407=0xb & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n# (1) BTST:G [Ax]\n:BTST^\":G\" memBaseAx is (b1_0007=0x7e; b2_0407=0xb & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n# (1) BTST:G bit,base\n:BTST^\":G\" memBit, memBase is (b1_0007=0x7e; b2_0407=0xb) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n# (2) BTST:S bit,base:11[SB]\n:BTST^\":S\" b1_bit, memBase11 is (b1_0307=0x0b & b1_bit) ... & memBase11 {\n mask:1 = (1 << b1_bit);\n bitValue:1 = (memBase11 & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n### BTSTC ###\n\n# BTSTC bit,Rx/Ax\n:BTSTC regBit, regBase is (b1_0007=0x7e; b2_0407=0x0 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n regBase = regBase & ~mask;\n}\n\n# BTSTC [Ax]\n:BTSTC memBaseAx is (b1_0007=0x7e; b2_0407=0x0 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n *:1 ptr = val & ~mask;\n}\n\n# BTSTC bit,base\n:BTSTC memBit, memBase is (b1_0007=0x7e; b2_0407=0x0) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n val:1 = memBase;\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n memBase = val & ~mask;\n}\n\n### BTSTS ###\n\n# BTSTS bit,Rx/Ax\n:BTSTS regBit, regBase is (b1_0007=0x7e; b2_0407=0x1 & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n regBase = regBase | mask;\n}\n\n# BTSTS [Ax]\n:BTSTS memBaseAx is (b1_0007=0x7e; b2_0407=0x1 & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n *:1 ptr = val | mask;\n}\n\n# BTSTS bit,base\n:BTSTS memBit, memBase is (b1_0007=0x7e; b2_0407=0x1) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n val:1 = memBase;\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n memBase = val | mask;\n}\n\n### BXOR ###\n\n# BXOR bit,Rx/Ax\n:BXOR regBit, regBase is (b1_0007=0x7e; b2_0407=0xc & b2_d4_3=0) ... & regBase ... & regBit {\n mask:2 = (1 << regBit);\n bitValue:2 = (regBase & mask);\n $(CARRY) = $(CARRY) ^ (bitValue != 0);\n}\n\n# BXOR [Ax]\n:BXOR memBaseAx is (b1_0007=0x7e; b2_0407=0xc & b2_d4_13=0x3) & memBaseAx {\n ptr:3 = zext(memBaseAx >> 3);\n bit:1 = memBaseAx:1 & 0x7;\n val:1 = *:1 ptr;\n mask:1 = (1 << bit);\n bitValue:1 = (val & mask);\n $(CARRY) = $(CARRY) ^ (bitValue != 0);\n}\n\n# BXOR bit,base\n:BXOR memBit, memBase is (b1_0007=0x7e; b2_0407=0xc) ... & memBase & memBit {\n mask:1 = (1 << memBit);\n bitValue:1 = (memBase & mask);\n $(CARRY) = $(CARRY) ^ (bitValue != 0);\n}\n\n### CMP ###\n\n# (1) CMP.B:G #simm, dst\n:CMP^\".B:G\" srcSimm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x8) ... & dst4B); srcSimm8 {\n tmp:1 = dst4B;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n setResultFlags(tmp);\n}\n\n# (1) CMP.B:G #simm, Ax\n:CMP^\".B:G\" srcSimm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x8) & $(DST4AX)); srcSimm8 {\n tmp:1 = dst4Ax:1;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n setResultFlags(tmp);\n}\n\n# (1) CMP.W:G #simm, dst\n:CMP^\".W:G\" srcSimm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x8) ... & dst4W); srcSimm16 {\n tmp:2 = dst4W;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n setResultFlags(tmp);\n}\n\n# (2) CMP.B:Q #simm4, dst\n:CMP^\".B:Q\" srcSimm4_0407, dst4B is (b1_0107=0x68 & b1_size_0=0; srcSimm4_0407) ... & dst4B {\n tmp:1 = dst4B;\n setSubtractFlags(tmp, srcSimm4_0407);\n tmp = tmp - srcSimm4_0407;\n setResultFlags(tmp);\n}\n\n# (2) CMP.B:Q #simm4, Ax\n:CMP^\".B:Q\" srcSimm4_0407, dst4Ax is (b1_0107=0x68 & b1_size_0=0; srcSimm4_0407) & $(DST4AX) {\n tmp:1 = dst4Ax:1;\n setSubtractFlags(tmp, srcSimm4_0407);\n tmp = tmp - srcSimm4_0407;\n setResultFlags(tmp);\n}\n\n# (2) CMP.W:Q #simm4, dst\n:CMP^\".W:Q\" srcSimm4_0407, dst4W is (b1_0107=0x68 & b1_size_0=1; srcSimm4_0407) ... & dst4W {\n tmp:2 = dst4W;\n imm:2 = sext(srcSimm4_0407);\n setSubtractFlags(tmp, imm);\n tmp = tmp - imm;\n setResultFlags(tmp);\n}\n\n# (3) CMP.B:S #imm, dst\n:CMP^\".B:S\" srcSimm8, dst3B_afterDsp8 is (b1_0307=0x1c; srcSimm8) ... & $(DST3B_AFTER_DSP8) {\n tmp:1 = dst3B_afterDsp8;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n setResultFlags(tmp);\n}\n\n# (4) CMP.B:G src, dst\n:CMP^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x60 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4;\n src:1 = src4B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (4) CMP.B:G src, Ax\n:CMP^\".B:G\" src4B, dst4Ax is (b1_0107=0x60 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1;\n src:1 = src4B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (4) CMP.W:G src, dst\n:CMP^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x60 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4;\n src:2 = src4W;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (5) CMP.B:S src, R0H/R0L\n:CMP^\".B:S\" dst2B, b1_2_reg8 is (b1_0307=0x7 & b1_2_reg8) ... & dst2B {\n src:1 = dst2B;\n setSubtractFlags(b1_2_reg8, src);\n b1_2_reg8 = b1_2_reg8 - src;\n setResultFlags(b1_2_reg8);\n}\n\n### DADC ###\n\n# (1) DADC.B #imm, R0L\n:DADC.B srcImm8, R0L is R0L & b1_0007=0x7c; b2_0007=0xee; srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(R0L);\n tmp:2 = DecimalAddWithCarry(src, dst);\n R0L = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (2) DADC.W #imm, R0\n:DADC.W srcImm16, R0 is R0 & b1_0007=0x7d; b2_0007=0xee; srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(R0);\n tmp:4 = DecimalAddWithCarry(src, dst);\n R0 = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (3) DADC.B R0H, R0L\n:DADC.B R0H, R0L is R0H & R0L & b1_0007=0x7c; b2_0007=0xe6 {\n src:2 = zext(R0H);\n dst:2 = zext(R0L);\n tmp:2 = DecimalAddWithCarry(src, dst);\n R0L = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (4) DADC.W R1, R0\n:DADC.W R1, R0 is R1 & R0 & b1_0007=0x7d; b2_0007=0xe6 {\n src:4 = zext(R1);\n dst:4 = zext(R0);\n tmp:4 = DecimalAddWithCarry(src, dst);\n R0 = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n### DADD ###\n\n# (1) DADD.B #imm, R0L\n:DADD.B srcImm8, R0L is R0L & b1_0007=0x7c; b2_0007=0xec; srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(R0L);\n tmp:2 = DecimalAdd(src, dst);\n R0L = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (2) DADD.W #imm, R0\n:DADD.W srcImm16, R0 is R0 & b1_0007=0x7d; b2_0007=0xec; srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(R0);\n tmp:4 = DecimalAdd(src, dst);\n R0 = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (3) DADD.B R0H, R0L\n:DADD.B R0H, R0L is R0H & R0L & b1_0007=0x7c; b2_0007=0xe4 {\n src:2 = zext(R0H);\n dst:2 = zext(R0L);\n tmp:2 = DecimalAdd(src, dst);\n R0L = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (4) DADD.W R1, R0\n:DADD.W R1, R0 is R1 & R0 & b1_0007=0x7d; b2_0007=0xe4 {\n src:4 = zext(R1);\n dst:4 = zext(R0);\n tmp:4 = DecimalAdd(src, dst);\n R0 = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n### DEC ###\n\n# (1) DEC.B dst\n:DEC.B dst3B is b1_0307=0x15 ... & $(DST3B) {\n dst:1 = dst3B;\n setSubtractFlags(dst, 1);\n dst = dst - 1;\n dst3B = dst;\n setResultFlags(dst);\n}\n\n# (2) DEC.W dst\n:DEC.W b1_3_regAx is b1_0407=0xf & b1_0002=0x2 & b1_3_regAx {\n dst:2 = b1_3_regAx;\n setSubtractFlags(dst, 1);\n dst = dst - 1;\n b1_3_regAx = dst;\n setResultFlags(dst);\n}\n\n### DIV ###\n\n# (1) DIV.B #imm\n:DIV.B srcSimm8 is b1_0107=0x3e & b1_size_0=0; b2_0007=0xe1; srcSimm8 {\n d:2 = sext(srcSimm8);\n q:2 = R0 s/ d;\n r:2 = R0 s% d; # remainder has same sign as R0 (dividend)\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (1) DIV.W #imm\n:DIV.W srcSimm16 is b1_0107=0x3e & b1_size_0=1; b2_0007=0xe1; srcSimm16 {\n d:4 = sext(srcSimm16);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d; # remainder has same sign as R0 (dividend)\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIV.B src\n:DIV.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xd) ... & dst4B {\n d:2 = sext(dst4B);\n q:2 = R0 s/ d;\n r:2 = R0 s% d; # remainder has same sign as R0 (dividend)\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIV.W src\n:DIV.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0xd) ... & dst4W {\n d:4 = sext(dst4W);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d; # remainder has same sign as R0 (dividend)\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n### DIVU ###\n\n# (1) DIVU.B #imm\n:DIVU.B srcImm8 is b1_0107=0x3e & b1_size_0=0; b2_0007=0xe0; srcImm8 {\n d:2 = zext(srcImm8);\n q:2 = R0 / d;\n r:2 = R0 % d;\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (1) DIVU.W #imm\n:DIVU.W srcImm16 is b1_0107=0x3e & b1_size_0=1; b2_0007=0xe0; srcImm16 {\n d:4 = zext(srcImm16);\n q:4 = R2R0 / d;\n r:4 = R2R0 % d;\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVU.B src\n:DIVU.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xc) ... & dst4B {\n d:2 = zext(dst4B);\n q:2 = R0 / d;\n r:2 = R0 % d;\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVU.W src\n:DIVU.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0xc) ... & dst4W {\n d:4 = zext(dst4W);\n q:4 = R2R0 / d;\n r:4 = R2R0 % d;\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n### DIVX ###\n\n# (1) DIVX.B #imm\n:DIVX.B srcSimm8 is b1_0107=0x3e & b1_size_0=0; b2_0007=0xe3; srcSimm8 {\n d:2 = sext(srcSimm8);\n q:2 = R0 s/ d;\n r:2 = R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (1) DIVX.W #imm\n:DIVX.W srcSimm16 is b1_0107=0x3e & b1_size_0=1; b2_0007=0xe3; srcSimm16 {\n d:4 = sext(srcSimm16);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVX.B src\n:DIVX.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0x9) ... & dst4B {\n d:2 = sext(dst4B);\n q:2 = R0 s/ d;\n r:2 = R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVX.W src\n:DIVX.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0x9) ... & dst4W {\n d:4 = sext(dst4W);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n### DSBB ###\n\n# (1) DSBB.B #imm8, R0L\n:DSBB.B srcImm8, R0L is R0L & b1_0007=0x7c; b2_0007=0xef; srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(R0L);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:2 = DecimalSubtractWithBorrow(dst, src);\n R0L = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (2) DSBB.W #imm16, R0\n:DSBB.W srcImm16, R0 is R0 & b1_0007=0x7d; b2_0007=0xef; srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(R0);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:4 = DecimalSubtractWithBorrow(dst, src);\n R0 = tmp:2;\n setResultFlags(tmp:2);\n}\n\n# (3) DSBB.B R0H, R0L\n:DSBB.B R0H, R0L is R0H & R0L & b1_0007=0x7c; b2_0007=0xe7 {\n src:2 = zext(R0H);\n dst:2 = zext(R0L);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:2 = DecimalSubtractWithBorrow(dst, src);\n R0L = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (4) DSBB.W R1, R0\n:DSBB.W R1, R0 is R0 & R1 & b1_0007=0x7d; b2_0007=0xe7 {\n src:4 = zext(R1);\n dst:4 = zext(R0);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:4 = DecimalSubtractWithBorrow(dst, src);\n R0 = tmp:2;\n setResultFlags(tmp:2);\n}\n\n### DSUB ###\n\n# (1) DSUB.B #imm8, R0L\n:DSUB.B srcImm8, R0L is R0L & b1_0007=0x7c; b2_0007=0xed; srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(R0L);\n $(CARRY) = (dst >= src);\n tmp:2 = DecimalSubtract(dst, src);\n R0L = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (2) DSUB.W #imm16, R0\n:DSUB.W srcImm16, R0 is R0 & b1_0007=0x7d; b2_0007=0xed; srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(R0);\n $(CARRY) = (dst >= src);\n tmp:4 = DecimalSubtract(dst, src);\n R0 = tmp:2;\n setResultFlags(tmp:2);\n}\n\n# (3) DSUB.B R0H, R0L\n:DSUB.B R0H, R0L is R0H & R0L & b1_0007=0x7c; b2_0007=0xe5 {\n src:2 = zext(R0H);\n dst:2 = zext(R0L);\n $(CARRY) = (dst >= src);\n tmp:2 = DecimalSubtract(dst, src);\n R0L = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (4) DSUB.W R1, R0\n:DSUB.W R1, R0 is R0 & R1 & b1_0007=0x7d; b2_0007=0xe5 {\n src:4 = zext(R1);\n dst:4 = zext(R0);\n $(CARRY) = (dst >= src);\n tmp:4 = DecimalSubtract(dst, src);\n R0 = tmp:2;\n setResultFlags(tmp:2);\n}\n\n### ENTER ###\n\n:ENTER srcImm8 is b1_0007=0x7c; b2_0007=0xf2; srcImm8 {\n push2(FB);\n FB = SP;\n SP = SP - zext(srcImm8);\n}\n\n### EXITD ###\n\n:EXITD is b1_0007=0x7d; b2_0007=0xf2 {\n SP = FB;\n pop2(FB);\n pc:3 = 0;\n pop3(pc);\n return [pc];\n}\n\n### EXTS ###\n\n# (1) EXTS.B dst\n:EXTS.B dst4B is (b1_0007=0x7c; b2_0407=0x6) ... & dst4B & dst4W {\n tmp:2 = sext(dst4B);\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) EXTS.B Ax\n:EXTS.B dst4Ax is (b1_0007=0x7c; b2_0407=0x6) & $(DST4AX) {\n tmp:2 = sext(dst4Ax:1);\n dst4Ax = tmp;\n setResultFlags(tmp);\n}\n\n# (2) EXTS.W R0\n:EXTS.W R0 is R0 & b1_0007=0x7c; b2_0007=0xf3 {\n tmp:4 = sext(R0);\n R2R0 = tmp;\n setResultFlags(tmp);\n}\n\n### FCLR ###\n\n:FCLR flagBit is b1_0007=0xeb; b2_0707=0 & flagBit & b2_0003=0x5 {\n mask:2 = ~(1 << flagBit);\n FLG = FLG & mask;\n}\n\n### FSET ###\n\n:FSET flagBit is b1_0007=0xeb; b2_0707=0 & flagBit & b2_0003=0x4 {\n mask:2 = (1 << flagBit);\n FLG = FLG | mask;\n}\n\n### INC ###\n\n# (1) INC.B dst\n:INC.B dst3B is b1_0307=0x14 ... & $(DST3B) {\n tmp:1 = dst3B + 1;\n dst3B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) INC.W dst\n:INC.W b1_3_regAx is b1_0407=0xb & b1_0002=0x2 & b1_3_regAx {\n tmp:2 = b1_3_regAx + 1;\n b1_3_regAx = tmp;\n setResultFlags(tmp);\n}\n\n### INT ###\n\n:INT srcIntNum is b1_0007=0xeb; imm8_0607=3 & srcIntNum {\n push1(FLG:1);\n next:3 = inst_next;\n push3(next);\n ptr3:3 = (INTB + (zext(srcIntNum) * 0x4));\n pc:3 = *:3 ptr3;\n $(STACK_SEL) = ((srcIntNum > 0x1f) * $(STACK_SEL));\n $(INTERRUPT) = 0x0;\n $(DEBUG) = 0x0;\n call [pc];\n}\n\n##### INTO #####\n\n:INTO is b1_0007=0xf6 {\n if ($(OVERFLOW) == 0) goto inst_next;\n push1(FLG:1);\n next:3 = inst_next;\n push3(next);\n $(STACK_SEL) = 0;\n $(INTERRUPT) = 0x0;\n $(DEBUG) = 0x0;\n call 0x0fffe0;\n}\n\n### JCnd ###\n\n# (1) JCnd3 dsp8\n:J^b1cnd3 rel8offset1 is b1_0307=0x0d & b1cnd3; rel8offset1 {\n if (b1cnd3) goto rel8offset1;\n}\n\n# (2) JCnd4 dsp8\n:J^b2cnd3 rel8offset2 is b1_0007=0x7d; b2_0407=0xc & b2_0303=1 & b2cnd3; rel8offset2 {\n if (b2cnd3) goto rel8offset2;\n}\n\n### JMP ###\n\n# (1) JMP.S dsp3\n:JMP.S rel3offset2 is b1_0307=0x0c & rel3offset2 {\n goto rel3offset2;\n}\n\n# (2) JMP.B dsp8\n:JMP.B rel8offset1 is b1_0007=0xfe; rel8offset1 {\n goto rel8offset1;\n}\n\n# (3) JMP.W dsp16\n:JMP.W rel16offset1 is b1_0007=0xf4; rel16offset1 {\n goto rel16offset1;\n}\n\n# (4) JMP.A abs20\n:JMP.A abs20offset is b1_0007=0xfc; abs20offset {\n goto abs20offset;\n}\n\n### JMPI ###\n\n# JMPI.W dst\n:JMPI.W reloffset_dst4W is (b1_0007=0x7d; b2_0407=0x2) ... & reloffset_dst4W {\n goto reloffset_dst4W;\n}\n\n# JMPI.A dst (dst=register)\n:JMPI.A reloffset_dst4L is (b1_0007=0x7d; b2_0407=0x0) ... & reloffset_dst4L {\n goto reloffset_dst4L;\n}\n\n# JMPI.A dst (dst=memory)\n:JMPI.A reloffset_dst4T is (b1_0007=0x7d; b2_0407=0x0) ... & reloffset_dst4T {\n goto reloffset_dst4T;\n}\n\n### JMPS ###\n\n:JMPS srcImm8 is b1_0007=0xee; srcImm8 {\n # 18 <= srcImm8 <= 255 (range restriction not enforced by pattern match)\n ptr:3 = 0x0ffffe - (zext(srcImm8) << 1);\n pc:3 = 0x0f0000 | zext(*:2 ptr);\n goto [pc];\n}\n\n### JSR ###\n\n:JSR.W rel16offset1 is b1_0007=0xf5; rel16offset1 {\n next:3 = inst_next;\n push3(next);\n call rel16offset1;\n}\n\n:JSR.A abs20offset is b1_0007=0xfd; abs20offset {\n next:3 = inst_next;\n push3(next);\n call abs20offset;\n}\n\n### JSRI ###\n\n# JSRI.W dst\n:JSRI.W reloffset_dst4W is (b1_0007=0x7d; b2_0407=0x3) ... & reloffset_dst4W {\n next:3 = inst_next;\n push3(next);\n call reloffset_dst4W;\n}\n\n# JSRI.A dst (dst=register)\n:JSRI.A dst4L is (b1_0007=0x7d; b2_0407=0x1) ... & dst4L {\n next:3 = inst_next;\n push3(next);\n pc:3 = dst4L:3;\n call [pc];\n}\n\n# JSRI.A dst (dst=memory)\n:JSRI.A dst4T is (b1_0007=0x7d; b2_0407=0x1) ... & $(DST4T) {\n next:3 = inst_next;\n push3(next);\n pc:3 = dst4T;\n call [pc];\n}\n\n### JSRS ###\n\n:JSRS srcImm8 is b1_0007=0xef; srcImm8 {\n # 18 <= srcImm8 <= 255 (range restriction not enforced by pattern match)\n next:3 = inst_next;\n push3(next);\n ptr:3 = 0x0ffffe - (zext(srcImm8) << 1);\n pc:3 = 0x0f0000 | zext(*:2 ptr);\n call [pc];\n}\n\n### LDC ###\n\n:LDC srcImm16, b2_creg16 is b1_0007=0xeb; b2_0707=0 & b2_creg16 & b2_0003=0x0; srcImm16 {\n b2_creg16 = srcImm16;\n}\n\n:LDC dst4W, b2_creg16 is (b1_0007=0x7a; b2_0707=1 & b2_creg16) ... & dst4W {\n b2_creg16 = dst4W;\n}\n\n### LDCTX ###\n\n:LDCTX abs16offset, abs20offset is b1_0007=0x7c; b2_0007=0xf0; abs16offset; imm20_dat & abs20offset {\n\n taskNum:1 = abs16offset; # load task number stored at abs16\n ptr:3 = imm20_dat + (zext(taskNum) * 2); # compute table entry address relative to abs20\n regInfo:1 = *:1 ptr;\n ptr = ptr + 1;\n spCorrect:1 = *:1 ptr;\n\n ptr = zext(SP);\n\n if ((regInfo & 1) == 0) goto ;\n R0 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n R1 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n R2 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n R3 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n A0 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n A1 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n SB = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n FB = *:2 ptr;\n ptr = ptr + 2;\n \n SP = SP + zext(spCorrect);\n}\n\n### LDE ###\n\n# (1) LDE.B abs20, dst\n:LDE.B abs20offset, dst4B is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0x8) ... & dst4B); abs20offset {\n tmp:1 = abs20offset;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) LDE.B abs20, Ax\n:LDE.B abs20offset, dst4Ax is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0x8) & $(DST4AX)); abs20offset {\n tmp:1 = abs20offset;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) LDE.W abs20, dst\n:LDE.W abs20offsetW, dst4W is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0x8) ... & dst4W); abs20offsetW {\n tmp:2 = abs20offsetW;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) LDE.B dsp20, dst \n:LDE.B dsp20A0B, dst4B is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0x9) ... & dst4B); dsp20A0B {\n tmp:1 = dsp20A0B;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) LDE.B dsp20, Ax \n:LDE.B dsp20A0B, dst4Ax is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0x9) & $(DST4AX)); dsp20A0B {\n tmp:1 = dsp20A0B;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) LDE.W dsp20, dst \n:LDE.W dsp20A0W, dst4W is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0x9) ... & dst4W); dsp20A0W {\n tmp:2 = dsp20A0W;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (3) LDE.B [A1A0], dst\n:LDE.B [A1A0], dst4B is (A1A0 & b1_0107=0x3a & b1_size_0=0; b2_0407=0xa) ... & dst4B {\n ptr:3 = A1A0:3;\n tmp:1 = *:1 ptr;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (3) LDE.B [A1A0], Ax\n:LDE.B [A1A0], dst4Ax is (A1A0 & b1_0107=0x3a & b1_size_0=0; b2_0407=0xa) & $(DST4AX) {\n ptr:3 = A1A0:3;\n tmp:1 = *:1 ptr;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (3) LDE.W [A1A0], dst\n:LDE.W [A1A0], dst4W is (A1A0 & b1_0107=0x3a & b1_size_0=1; b2_0407=0xa) ... & dst4W {\n ptr:3 = A1A0:3;\n tmp:2 = *:2 ptr;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### LDINTB ###\n# LDINTB operand value\nldIntbVal: \"#\"^val is b1_0007; b2_0007; b3_0003; b4_0007; b5_0007; b6_0007; imm16_dat [ val = (b3_0003 << 16) + imm16_dat; ] {\n export *[const]:3 val;\n}\n\n# NOTE: Although this is documented as a macro for two LDE instructions, the encoding is different ??\n:LDINTB ldIntbVal is (b1_0007=0xeb; b2_0007=0x20; b3_0407=0x0; b4_0007=0x0; b5_0007=0xeb; b6_0007=0x10) ... & ldIntbVal {\n INTB = ldIntbVal;\n}\n\n### LDIPL ###\n\n:LDIPL srcImm3 is b1_0007=0x7d; b2_0307=0x14 & srcImm3 {\n $(IPL) = srcImm3;\n}\n\n### MOV ###\n\n# (1) MOV.B:G #imm, dst\n:MOV^\".B:G\" srcImm8, dst4B is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0xc) ... & dst4B); srcImm8 {\n val:1 = srcImm8;\n dst4B = val;\n setResultFlags(val);\n}\n\n# (1) MOV.B:G #imm, Ax\n:MOV^\".B:G\" srcImm8, dst4Ax is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0xc) & $(DST4AX)); srcImm8 {\n val:1 = srcImm8;\n dst4Ax = zext(val);\n setResultFlags(val);\n}\n\n# (1) MOV.W:G #imm, dst\n:MOV^\".W:G\" srcImm16, dst4W is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0xc) ... & dst4W); srcImm16 {\n val:2 = srcImm16;\n dst4W = val;\n setResultFlags(val);\n}\n\n# (2) MOV.B:Q #simm4, dst\n:MOV^\".B:Q\" srcSimm4_0407, dst4B is (b1_0107=0x6c & b1_size_0=0; srcSimm4_0407) ... & dst4B {\n val:1 = srcSimm4_0407;\n dst4B = val;\n setResultFlags(val);\n}\n\n# (2) MOV.B:Q #simm4, Ax\n:MOV^\".B:Q\" srcSimm4_0407, dst4Ax is (b1_0107=0x6c & b1_size_0=0; srcSimm4_0407) & $(DST4AX) {\n val:1 = srcSimm4_0407;\n dst4Ax = zext(val);\n setResultFlags(val);\n}\n\n# (2) MOV.W:Q #simm4, dst\n:MOV^\".W:Q\" srcSimm4_0407, dst4W is (b1_0107=0x6c & b1_size_0=1; srcSimm4_0407) ... & dst4W {\n val:2 = sext(srcSimm4_0407);\n dst4W = val;\n setResultFlags(val);\n}\n\n# (3) MOV.B:S #imm, dst\n:MOV^\".B:S\" srcImm8, dst3B_afterDsp8 is (b1_0307=0x18; srcImm8) ... & $(DST3B_AFTER_DSP8) {\n val:1 = srcImm8;\n dst3B_afterDsp8 = val;\n setResultFlags(val);\n}\n\n# (4) MOV.B:S #imm, dst\n:MOV^\".B:S\" srcImm8, b1_3_regAx is b1_0407=0xe & b1_3_regAx & b1_0002=0x2; srcImm8 {\n val:1 = srcImm8;\n b1_3_regAx = zext(val);\n setResultFlags(val);\n}\n\n# (4) MOV.W:S #imm, Ax\n:MOV^\".W:S\" srcImm16, b1_3_regAx is b1_0407=0xa & b1_3_regAx & b1_0002=0x2; srcImm16 {\n val:2 = srcImm16;\n b1_3_regAx = val;\n setResultFlags(val);\n}\n\n# (5) MOV.B:Z #0, dst\n:MOV^\".B:Z\" srcZero8, dst3B is (srcZero8 & b1_0307=0x16) ... & $(DST3B) {\n dst3B = 0;\n $(SIGN) = 0;\n $(ZERO) = 1;\n}\n\n# (6) MOV.B:G src, dst\n:MOV^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x39 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n val:1 = src4B;\n dst4B_afterSrc4 = val;\n setResultFlags(val);\n}\n\n# (6) MOV.B:G src, Ax\n:MOV^\".B:G\" src4B, dst4Ax is (b1_0107=0x39 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n val:1 = src4B;\n dst4Ax = zext(val);\n setResultFlags(val);\n}\n\n# (6) MOV.W:G src, dst\n:MOV^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x39 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n val:2 = src4W;\n dst4W_afterSrc4 = val;\n setResultFlags(val);\n}\n\n# (7) MOV.B:S src, Ax\n:MOV^\".B:S\" dst2B, b1_2_regAx is (b1_0307=0x06 & b1_2_regAx) ... & dst2B {\n val:1 = dst2B;\n b1_2_regAx = zext(val);\n setResultFlags(val);\n}\n\n# (8) MOV.B:S R0H/R0L, dst\n# TODO: Is it really necessary to exclude R0H/R0L as valid destination ??\n:MOV^\".B:S\" b1_2_reg8, dst2B is (b1_0307=0x0 & b1_2_reg8) ... & dst2B {\n val:1 = b1_2_reg8;\n dst2B = val;\n setResultFlags(val);\n}\n\n# (9) MOV.B:S src, R0H/R0L\n:MOV^\".B:S\" dst2B, b1_2_reg8 is (b1_0307=0x1 & b1_2_reg8) ... & dst2B {\n val:1 = dst2B;\n b1_2_reg8 = val;\n setResultFlags(val);\n}\n\n# (10) MOV.B:G dsp:8[SP], dst\n:MOV^\".B:G\" dsp8spB, dst4B is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0xb) ... & dst4B); dsp8spB {\n val:1 = dsp8spB;\n dst4B = val;\n setResultFlags(val);\n}\n\n# (10) MOV.B:G dsp:8[SP], Ax\n:MOV^\".B:G\" dsp8spB, dst4Ax is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0xb) & $(DST4AX)); dsp8spB {\n val:1 = dsp8spB;\n dst4Ax = zext(val);\n setResultFlags(val);\n}\n\n# (10) MOV.W:G dsp:8[SP], dst\n:MOV^\".W:G\" dsp8spW, dst4W is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0xb) ... & dst4W); dsp8spW {\n val:2 = dsp8spW;\n dst4W = val;\n setResultFlags(val);\n}\n\n# (11) MOV.B:G src, dsp:8[SP]\n:MOV^\".B:G\" dst4B, dsp8spB is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0x3) ... & dst4B); dsp8spB {\n val:1 = dst4B;\n dsp8spB = val;\n setResultFlags(val);\n}\n\n# (11) MOV.W:G src, dsp:8[SP]\n:MOV^\".W:G\" dst4W, dsp8spW is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0x3) ... & dst4W); dsp8spW {\n val:2 = dst4W;\n dsp8spW = val;\n setResultFlags(val);\n}\n\n### MOVA ###\n\n:MOVA dst4A, b2_reg16 is (b1_0007=0xeb; b2_0707=0 & b2_reg16) ... & $(DST4A) {\n b2_reg16 = dst4A:2;\n}\n\n### MOVDir ###\n\n# TODO: dst4B=Ax/R0L cases will parse but are not valid\n\n# (1) MOVDir R0L, dst\n:MOVLL R0L, dst4B is (R0L & b1_0007=0x7c; b2_0407=0x8) ... & dst4B {\n dst4B = (R0L & 0x0f) | (dst4B & 0xf0);\n}\n:MOVHL R0L, dst4B is (R0L & b1_0007=0x7c; b2_0407=0x9) ... & dst4B {\n dst4B = ((R0L & 0xf0) >> 4) | (dst4B & 0xf0);\n}\n:MOVLH R0L, dst4B is (R0L & b1_0007=0x7c; b2_0407=0xa) ... & dst4B {\n dst4B = ((R0L & 0x0f) << 4) | (dst4B & 0x0f);\n}\n:MOVHH R0L, dst4B is (R0L & b1_0007=0x7c; b2_0407=0xb) ... & dst4B {\n dst4B = (R0L & 0xf0) | (dst4B & 0x0f);\n}\n\n# (1) MOVDir dst, R0L\n:MOVLL dst4B, R0L is (R0L & b1_0007=0x7c; b2_0407=0x0) ... & dst4B {\n R0L = (dst4B & 0x0f) | (R0L & 0xf0);\n}\n:MOVHL dst4B, R0L is (R0L & b1_0007=0x7c; b2_0407=0x1) ... & dst4B {\n R0L = ((dst4B & 0xf0) >> 4) | (R0L & 0xf0);\n}\n:MOVLH dst4B, R0L is (R0L & b1_0007=0x7c; b2_0407=0x2) ... & dst4B {\n R0L = ((dst4B & 0x0f) << 4) | (R0L & 0x0f);\n}\n:MOVHH dst4B, R0L is (R0L & b1_0007=0x7c; b2_0407=0x3) ... & dst4B {\n R0L = (dst4B & 0xf0) | (R0L & 0x0f);\n}\n\n### MUL ###\n\n# TODO: Illegal MUL destination cases will parse but are not valid (e.g., R0H, R2, R1H, R3)\n\n# (1) MUL.B #imm, dst\n:MUL.B srcSimm8, dst4B is ((b1_0107=0x3e & b1_size_0=0; b2_0407=0x5) ... & dst4B & dst4W); srcSimm8 {\n dst4W = sext(srcSimm8) * sext(dst4B);\n}\n\n# (1) MUL.W #imm, dst\n:MUL.W srcSimm16, dst4W is ((b1_0107=0x3e & b1_size_0=1; b2_0407=0x5) ... & dst4W & dst4L); srcSimm16 {\n dst4L = sext(srcSimm16) * sext(dst4W);\n}\n\n# (2) MUL.B src, dst\n:MUL.B src4B, dst4B_afterSrc4 is (b1_0107=0x3c & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... & dst4W_afterSrc4 ... {\n dst4W_afterSrc4 = sext(src4B) * sext(dst4B_afterSrc4);\n}\n\n# (2) MUL.W src, dst\n:MUL.W src4W, dst4W_afterSrc4 is (b1_0107=0x3c & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... & dst4L_afterSrc4 ... {\n dst4L_afterSrc4 = sext(src4W) * sext(dst4W_afterSrc4);\n}\n\n### MULU ###\n\n# TODO: Illegal MULU destination cases will parse but are not valid (e.g., R0H, R2, R1H, R3)\n\n# (1) MULU.B #imm, dst\n:MULU.B srcImm8, dst4B is ((b1_0107=0x3e & b1_size_0=0; b2_0407=0x4) ... & dst4B & dst4W); srcImm8 {\n dst4W = zext(srcImm8) * zext(dst4B);\n}\n\n# (1) MULU.W #imm, dst\n:MULU.W srcImm16, dst4W is ((b1_0107=0x3e & b1_size_0=1; b2_0407=0x4) ... & dst4W & dst4L); srcImm16 {\n dst4L = zext(srcImm16) * zext(dst4W);\n}\n\n# (2) MULU.B src, dst\n:MULU.B src4B, dst4B_afterSrc4 is (b1_0107=0x38 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... & dst4W_afterSrc4 ... {\n dst4W_afterSrc4 = zext(src4B) * zext(dst4B_afterSrc4);\n}\n\n# (2) MULU.W src, dst\n:MULU.W src4W, dst4W_afterSrc4 is (b1_0107=0x38 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... & dst4L_afterSrc4 ... {\n dst4L_afterSrc4 = zext(src4W) * zext(dst4W_afterSrc4);\n}\n\n### NEG ###\n\n# (1) NEG.B dst\n:NEG.B dst4B is (b1_0107=0x3a & b1_size_0=0; b2_0407=0x5) ... & dst4B {\n tmp:1 = dst4B;\n setSubtractFlags(0:1, tmp);\n tmp = -tmp;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) NEG.W dst\n:NEG.W dst4W is (b1_0107=0x3a & b1_size_0=1; b2_0407=0x5) ... & dst4W {\n tmp:2 = dst4W;\n setSubtractFlags(0:2, tmp);\n tmp = -tmp;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### NOP ###\n\n:NOP is b1_0007=0x04 {\n}\n\n### NOT ###\n\n# (1) NOT.B dst\n:NOT.B dst4B is (b1_0107=0x3a & b1_size_0=0; b2_0407=0x7) ... & dst4B {\n tmp:1 = ~dst4B;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) NOT.W dst\n:NOT.W dst4W is (b1_0107=0x3a & b1_size_0=1; b2_0407=0x7) ... & dst4W {\n tmp:2 = ~dst4W;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) NOT.B:S dst\n:NOT^\".B:S\" dst3B is (b1_0307=0x17) ... & $(DST3B) {\n tmp:1 = ~dst3B;\n dst3B = tmp;\n setResultFlags(tmp);\n}\n\n### OR ###\n\n# (1) OR.B:G #imm, dst\n:OR^\".B:G\" srcImm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x3) ... & dst4B); srcImm8 {\n tmp:1 = dst4B | srcImm8;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) OR.B:G #imm, Ax\n:OR^\".B:G\" srcImm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x3) & $(DST4AX)); srcImm8 {\n tmp:1 = dst4Ax:1 | srcImm8;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) OR.W:G #imm, dst\n:OR^\".W:G\" srcImm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x3) ... & dst4W); srcImm16 {\n tmp:2 = dst4W | srcImm16;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) OR.B:S #imm, dst\n:OR^\".B:S\" srcImm8, dst3B_afterDsp8 is (b1_0307=0x13; srcImm8) ... & $(DST3B_AFTER_DSP8) {\n tmp:1 = dst3B_afterDsp8 | srcImm8;\n dst3B_afterDsp8 = tmp;\n setResultFlags(tmp);\n}\n\n# (3) OR.B:G src, dst\n:OR^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x4c & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4 | src4B;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (3) OR.B:G src, Ax\n:OR^\".B:G\" src4B, dst4Ax is (b1_0107=0x4c & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1 | src4B;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (3) OR.W:G src, dst\n:OR^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x4c & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4 | src4W;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) OR.B:S src, R0L/R0H\n:OR^\".B:S\" dst2B, b1_2_reg8 is (b1_0307=0x3 & b1_2_reg8) ... & dst2B {\n tmp:1 = dst2B | b1_2_reg8;\n b1_2_reg8 = tmp;\n setResultFlags(tmp);\n}\n\n### POP ###\n\n# (1) POP.B:G dst\n:POP^\".B:G\" dst4B is (b1_0107=0x3a & b1_size_0=0; b2_0407=0xd) ... & dst4B {\n pop1(dst4B);\n}\n\n# (1) POP.B:G Ax\n:POP^\".B:G\" dst4Ax is (b1_0107=0x3a & b1_size_0=0; b2_0407=0xd) & $(DST4AX) {\n val:1 = 0;\n pop1(val);\n dst4Ax = zext(val);\n}\n\n# (1) POP.W:G dst\n:POP^\".W:G\" dst4W is (b1_0107=0x3a & b1_size_0=1; b2_0407=0xd) ... & dst4W {\n pop2(dst4W);\n}\n\n# (2) POP.B:S R0L/R0H\n:POP^\".B:S\" b1_3_reg8 is b1_0407=0x9 & b1_3_reg8 & b1_0002=0x2 {\n pop1(b1_3_reg8);\n}\n\n# (3) POP.W:S Ax\n:POP^\".W:S\" b1_3_regAx is b1_0407=0xd & b1_3_regAx & b1_0002=0x2 {\n pop2(b1_3_regAx);\n}\n\n### POPC ###\n\n:POPC b2_creg16 is b1_0007=0xeb; b2_0707=0 & b2_creg16 & b2_0003=0x3 {\n pop2(b2_creg16);\n}\n\n### POPM ###\npopRegFB: FB is regBit7=1 & FB { pop2(FB); }\npopRegFB: is regBit7=0 { }\n\npopRegSB: SB popRegFB is regBit6=1 & popRegFB & SB { pop2(SB); build popRegFB; }\npopRegSB: popRegFB is popRegFB { build popRegFB; }\n\npopRegA1: A1 popRegSB is regBit5=1 & popRegSB & A1 { pop2(A1); build popRegSB; }\npopRegA1: popRegSB is popRegSB { build popRegSB; }\npopRegA0: A0 popRegA1 is regBit4=1 & popRegA1 & A0 { pop2(A0); build popRegA1; }\npopRegA0: popRegA1 is popRegA1 { build popRegA1; }\n\npopRegR3: R3 popRegA0 is regBit3=1 & popRegA0 & R3 { pop2(R3); build popRegA0; }\npopRegR3: popRegA0 is popRegA0 { build popRegA0; }\npopRegR2: R2 popRegR3 is regBit2=1 & popRegR3 & R2 { pop2(R2); build popRegR3; }\npopRegR2: popRegR3 is popRegR3 { build popRegR3; }\npopRegR1: R1 popRegR2 is regBit1=1 & popRegR2 & R1 { pop2(R1); build popRegR2; }\npopRegR1: popRegR2 is popRegR2 { build popRegR2; }\npopRegR0: R0 popRegR1 is regBit0=1 & popRegR1 & R0 { pop2(R0); build popRegR1; }\npopRegR0: popRegR1 is popRegR1 { build popRegR1; }\n\npopRegList: \"( \"^popRegR0^\")\" is popRegR0 { build popRegR0; }\n\n:POPM popRegList is b1_0007=0xed; popRegList {\n build popRegList;\n}\n\n### PUSH ###\n\n# (1) PUSH.B:G #imm\n:PUSH^\".B:G\" srcImm8 is b1_0107=0x3e & b1_size_0=0; b2_0007=0xe2; srcImm8 {\n push1(srcImm8);\n}\n\n# (1) PUSH.W:G #imm\n:PUSH^\".W:G\" srcImm16 is b1_0107=0x3e & b1_size_0=1; b2_0007=0xe2; srcImm16 {\n push2(srcImm16);\n}\n\n# (2) PUSH.B:G src\n:PUSH^\".B:G\" dst4B is (b1_0107=0x3a & b1_size_0=0; b2_0407=0x4) ... & dst4B {\n push1(dst4B);\n}\n\n# (2) PUSH.W:G src\n:PUSH^\".W:G\" dst4W is (b1_0107=0x3a & b1_size_0=1; b2_0407=0x4) ... & dst4W {\n push2(dst4W);\n}\n\n# (3) PUSH.B:S R0H/R0L\n:PUSH^\".B:S\" b1_3_reg8 is b1_0407=0x8 & b1_3_reg8 & b1_0002=0x2 {\n push1(b1_3_reg8);\n}\n\n# (4) PUSH.W:S Ax\n:PUSH^\".W:S\" b1_3_regAx is b1_0407=0xc & b1_3_regAx & b1_0002=0x2 {\n push2(b1_3_regAx);\n}\n\n### PUSHA ###\n\n:PUSHA dst4A is (b1_0007=0x7d; b2_0407=0x9) ... & $(DST4A) {\n push2(dst4A:2);\n}\n\n### PUSHC ###\n\n:PUSHC b2_creg16 is b1_0007=0xeb; b2_0707=0 & b2_creg16 & b2_0003=0x2 {\n push2(b2_creg16);\n}\n\n### PUSHM ###\npushRegR0: R0 is regBit7=1 & R0 { push2(R0); }\npushRegR0: is regBit7=0 { }\npushRegR1: pushRegR0 R1 is regBit6=1 & pushRegR0 & R1 { push2(R1); build pushRegR0; }\npushRegR1: pushRegR0 is pushRegR0 { build pushRegR0; }\npushRegR2: pushRegR1 R2 is regBit5=1 & pushRegR1 & R2 { push2(R2); build pushRegR1; }\npushRegR2: pushRegR1 is pushRegR1 { build pushRegR1; }\npushRegR3: pushRegR2 R3 is regBit4=1 & pushRegR2 & R3 { push2(R3); build pushRegR2; }\npushRegR3: pushRegR2 is pushRegR2 { build pushRegR2; }\n\npushRegA0: pushRegR3 A0 is regBit3=1 & pushRegR3 & A0 { push3(A0); build pushRegR3; }\npushRegA0: pushRegR3 is pushRegR3 { build pushRegR3; }\npushRegA1: pushRegA0 A1 is regBit2=1 & pushRegA0 & A1 { push3(A1); build pushRegA0; }\npushRegA1: pushRegA0 is pushRegA0 { build pushRegA0; }\n\npushRegSB: pushRegA1 SB is regBit1=1 & pushRegA1 & SB { push3(SB); build pushRegA1; }\npushRegSB: pushRegA1 is pushRegA1 { build pushRegA1; }\n\npushRegFB: pushRegSB FB is regBit0=1 & pushRegSB & FB { push3(FB); build pushRegSB; }\npushRegFB: pushRegSB is pushRegSB { build pushRegSB; }\n\npushRegList: \"(\"^pushRegFB^\" )\" is pushRegFB { build pushRegFB; }\n\n:PUSHM pushRegList is b1_0007=0xec; pushRegList {\n build pushRegList;\n}\n\n### REIT ###\n\n:REIT is b1_0007=0xfb {\n pc:3 = 0;\n pop3(pc);\n f:1 = 0;\n pop1(f);\n FLG = zext(f); # TODO: Not sure what state upper FLG bits should be in ?? \n return [pc];\n}\n\n### RMPA ###\n\n:RMPA.B is b1_0107=0x3e & b1_size_0=0; b2_0007=0xf1 {\n if (R3 == 0) goto inst_next;\n ptr0:3 = zext(A0);\n ptr1:3 = zext(A1);\n a:1 = *:1 ptr0;\n b:1 = *:1 ptr1;\n A0 = A0 + 1;\n A1 = A1 + 1;\n prod:2 = sext(a) * sext(b);\n o:1 = scarry(R0, prod);\n $(OVERFLOW) = o | $(OVERFLOW);\n R0 = R0 + prod;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:RMPA.W is b1_0107=0x3e & b1_size_0=1; b2_0007=0xf1 {\n if (R3 == 0) goto inst_next;\n ptr0:3 = zext(A0);\n ptr1:3 = zext(A1);\n a:2 = *:2 ptr0;\n b:2 = *:2 ptr1;\n A0 = A0 + 2;\n A1 = A1 + 2;\n prod:4 = sext(a) * sext(b);\n o:1 = scarry(R2R0, prod);\n $(OVERFLOW) = o | $(OVERFLOW);\n R2R0 = R2R0 + prod;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n### ROLC ###\n\n:ROLC.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xa) ... & dst4B {\n c:1 = $(CARRY);\n tmp:1 = dst4B;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n:ROLC.B dst4Ax is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xa) & $(DST4AX) {\n c:1 = $(CARRY);\n tmp:1 = dst4Ax:1;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n:ROLC.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0xa) ... & dst4W {\n c:2 = zext($(CARRY));\n tmp:2 = dst4W;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### RORC ###\n\n:RORC.B dst4B is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xb) ... & dst4B {\n c:1 = $(CARRY);\n tmp:1 = dst4B;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 7);\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n:RORC.B dst4Ax is (b1_0107=0x3b & b1_size_0=0; b2_0407=0xb) & $(DST4AX) {\n c:1 = $(CARRY);\n tmp:1 = dst4Ax:1;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 7);\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n:RORC.W dst4W is (b1_0107=0x3b & b1_size_0=1; b2_0407=0xb) ... & dst4W {\n c:2 = zext($(CARRY));\n tmp:2 = dst4W;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 15);\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### ROT ###\n\n# (1) ROT.B #imm, dst (right)\n:ROT.B srcSimm4Shift_0407, dst4B is (b1_0107=0x70 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=1) ... & dst4B {\n rightShift:1 = -srcSimm4Shift_0407;\n tmp:1 = dst4B;\n $(CARRY) = (tmp >> (rightShift - 1)) & 1;\n tmp = (tmp >> rightShift) | (tmp << (8 - rightShift));\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.B #imm, Ax (right)\n:ROT.B srcSimm4Shift_0407, dst4Ax is (b1_0107=0x70 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=1) & $(DST4AX) {\n rightShift:1 = -srcSimm4Shift_0407;\n tmp:1 = dst4Ax:1;\n $(CARRY) = (tmp >> (rightShift - 1)) & 1;\n tmp = (tmp >> rightShift) | (tmp << (8 - rightShift));\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ROT.W #imm, dst (right)\n:ROT.W srcSimm4Shift_0407, dst4W is (b1_0107=0x70 & b1_size_0=1; srcSimm4Shift_0407 & b2_shiftSign_7=1) ... & dst4W {\n rightShift:1 = -srcSimm4Shift_0407;\n tmp:2 = dst4W;\n c:2 = (tmp >> (rightShift - 1));\n $(CARRY) = c:1 & 1;\n tmp = (tmp >> rightShift) | (tmp << (16 - rightShift));\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.B #imm, dst (left)\n:ROT.B srcSimm4Shift_0407, dst4B is (b1_0107=0x70 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=0) ... & dst4B {\n leftShift:1 = srcSimm4Shift_0407;\n tmp:1 = dst4B;\n $(CARRY) = (tmp >> (8 - leftShift)) & 1;\n tmp = (tmp << leftShift) | (tmp >> (8 - leftShift));\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.B #imm, Ax (left)\n:ROT.B srcSimm4Shift_0407, dst4Ax is (b1_0107=0x70 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=0) & $(DST4AX) {\n leftShift:1 = srcSimm4Shift_0407;\n tmp:1 = dst4Ax:1;\n $(CARRY) = (tmp >> (8 - leftShift)) & 1;\n tmp = (tmp << leftShift) | (tmp >> (8 - leftShift));\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ROT.W #imm, dst (left)\n:ROT.W srcSimm4Shift_0407, dst4W is (b1_0107=0x70 & b1_size_0=1; srcSimm4Shift_0407 & b2_shiftSign_7=0) ... & dst4W {\n leftShift:1 = srcSimm4Shift_0407;\n tmp:2 = dst4W;\n c:2 = (tmp >> (16 - leftShift));\n $(CARRY) = c:1 & 1;\n tmp = (tmp << leftShift) | (tmp >> (16 - leftShift));\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ROT.B R1H, dst\n:ROT.B R1H, dst4B is (R1H & b1_0107=0x3a & b1_size_0=0; b2_0407=0x6) ... & dst4B {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 8;\n tmp:1 = dst4B;\n if (shift s>= 0) goto ;\n shift = -shift;\n $(CARRY) = (tmp >> (shift - 1)) & 1;\n tmp = (tmp >> shift) | (tmp << (8 - shift));\n goto ;\n \n $(CARRY) = (tmp >> (8 - shift)) & 1;\n tmp = (tmp << shift) | (tmp >> (8 - shift));\n \n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ROT.B R1H, Ax\n:ROT.B R1H, dst4Ax is (R1H & b1_0107=0x3a & b1_size_0=0; b2_0407=0x6) & $(DST4AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 8;\n tmp:1 = dst4Ax:1;\n if (shift s>= 0) goto ;\n shift = -shift;\n $(CARRY) = (tmp >> (shift - 1)) & 1;\n tmp = (tmp >> shift) | (tmp << (8 - shift));\n goto ;\n \n $(CARRY) = (tmp >> (8 - shift)) & 1;\n tmp = (tmp << shift) | (tmp >> (8 - shift));\n \n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ROT.W R1H, dst\n:ROT.W R1H, dst4W is (R1H & b1_0107=0x3a & b1_size_0=1; b2_0407=0x6) ... & dst4W {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 16;\n tmp:2 = dst4W;\n if (shift s>= 0) goto ;\n shift = -shift;\n c:2 = (tmp >> (shift - 1));\n tmp = (tmp >> shift) | (tmp << (16 - shift));\n goto ;\n \n c = (tmp >> (16 - shift));\n tmp = (tmp << shift) | (tmp >> (16 - shift));\n \n $(CARRY) = c:1 & 1;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n### RTS ###\n\n:RTS is b1_0007=0xf3 {\n pc:3 = 0;\n pop3(pc);\n return [pc];\n}\n\n### SBB ###\n\n# (1) SBB.B #imm, dst\n:SBB.B srcSimm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x7) ... & dst4B); srcSimm8 {\n tmp:1 = dst4B;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, srcSimm8, c);\n tmp = tmp - srcSimm8 - c;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SBB.B #imm, Ax\n:SBB.B srcSimm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x7) & $(DST4AX)); srcSimm8 {\n tmp:1 = dst4Ax:1;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, srcSimm8, c);\n tmp = tmp - srcSimm8 - c;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) SBB.W #imm, dst\n:SBB.W srcSimm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x7) ... & dst4W); srcSimm16 {\n tmp:2 = dst4W;\n c:2 = zext($(CARRY));\n setSubtract3Flags(tmp, srcSimm16, c);\n tmp = tmp - srcSimm16 - c;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SBB.B src, dst\n:SBB.B src4B, dst4B_afterSrc4 is (b1_0107=0x5c & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4;\n s:1 = src4B;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SBB.B src, Ax\n:SBB.B src4B, dst4Ax is (b1_0107=0x5c & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1;\n s:1 = src4B;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) SBB.W src, dst\n:SBB.W src4W, dst4W_afterSrc4 is (b1_0107=0x5c & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4;\n s:2 = src4W;\n c:2 = zext($(CARRY));\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n##### SBJNZ - PSUEDO-OP! SAME AS ADJNZ #####\n### SHA ###\nmacro SHAsetShiftRightFlags(val,shift,result) {\n local c = (val >> (shift - 1)) & 1;\n $(CARRY) = c:1;\n local mask = ~(-(1 << shift));\n allOnes:1 = (mask & val) == mask;\n allZeros:1 = (mask & val) == 0;\n $(OVERFLOW) = (result s< 0 && allOnes) || (result s>= 0 && allZeros);\n setResultFlags(result);\n} \n\nmacro SHAsetShiftLeftFlags(val,shift,result,sze) {\n local c = (val >> (sze - shift)) & 1;\n $(CARRY) = c:1;\n local mask = -(1 << shift);\n allOnes:1 = (mask & val) == mask;\n allZeros:1 = (mask & val) == 0;\n $(OVERFLOW) = (result s< 0 && allOnes) || (result s>= 0 && allZeros);\n setResultFlags(result);\n}\n\n# (1) SHA.B #imm4, dst (right)\n:SHA.B srcSimm4Shift_0407, dst4B is (b1_0107=0x78 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=1) ... & dst4B {\n val:1 = dst4B;\n shift:1 = -srcSimm4Shift_0407;\n tmp:1 = val s>> shift;\n dst4B = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.B #imm4, Ax (right)\n:SHA.B srcSimm4Shift_0407, dst4Ax is (b1_0107=0x78 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=1) & $(DST4AX) {\n val:1 = dst4Ax:1;\n shift:1 = -srcSimm4Shift_0407;\n tmp:1 = val s>> shift;\n dst4Ax = zext(tmp);\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.W #imm4, dst (right)\n:SHA.W srcSimm4Shift_0407, dst4W is (b1_0107=0x78 & b1_size_0=1; srcSimm4Shift_0407 & b2_shiftSign_7=1) ... & dst4W {\n val:2 = dst4W;\n shift:1 = -srcSimm4Shift_0407;\n tmp:2 = val s>> shift;\n dst4W = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.B #imm4, dst (left)\n:SHA.B srcSimm4Shift_0407, dst4B is (b1_0107=0x78 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=0) ... & dst4B {\n val:1 = dst4B;\n shift:1 = srcSimm4Shift_0407;\n tmp:1 = val << shift;\n dst4B = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHA.B #imm4, Ax (left)\n:SHA.B srcSimm4Shift_0407, dst4Ax is (b1_0107=0x78 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=0) & $(DST4AX) {\n val:1 = dst4Ax:1;\n shift:1 = srcSimm4Shift_0407;\n tmp:1 = val << shift;\n dst4Ax = zext(tmp);\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHA.W #imm4, dst (left)\n:SHA.W srcSimm4Shift_0407, dst4W is (b1_0107=0x78 & b1_size_0=1; srcSimm4Shift_0407 & b2_shiftSign_7=0) ... & dst4W {\n val:2 = dst4W;\n shift:1 = srcSimm4Shift_0407;\n tmp:2 = val << shift;\n dst4W = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (2) SHA.B R1H, dst\n:SHA.B R1H, dst4B is (R1H & b1_0107=0x3a & b1_size_0=0; b2_0407=0xf) ... & dst4B {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst4B;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val s>> shift;\n dst4B = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst4B = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (2) SHA.B R1H, Ax\n:SHA.B R1H, dst4Ax is (R1H & b1_0107=0x3a & b1_size_0=0; b2_0407=0xf) & $(DST4AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst4Ax:1;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val s>> shift;\n dst4Ax = zext(tmp);\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst4Ax = zext(tmp);\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (2) SHA.W R1H, dst\n:SHA.W R1H, dst4W is (R1H & b1_0107=0x3a & b1_size_0=1; b2_0407=0xf) ... & dst4W {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:2 = dst4W;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:2 = val s>> shift;\n dst4W = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst4W = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (3) SHA.L #imm4, R2R0/R3R1 (right)\n:SHA.L srcSimm4Shift_0003, b2_reg32 is b1_0007=0xeb; b2_0507=0x5 & b2_reg32 & srcSimm4Shift_0003 & b2_shiftSign_3=1 {\n val:4 = b2_reg32;\n shift:1 = -srcSimm4Shift_0003;\n tmp:4 = val s>> shift;\n b2_reg32 = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (3) SHA.L #imm4, R2R0/R3R1 (left)\n:SHA.L srcSimm4Shift_0003, b2_reg32 is b1_0007=0xeb; b2_0507=0x5 & b2_reg32 & srcSimm4Shift_0003 & b2_shiftSign_3=0 {\n val:4 = b2_reg32;\n shift:1 = srcSimm4Shift_0003;\n tmp:4 = val << shift;\n b2_reg32 = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n# (4) SHA.L R1H, R2R0/R3R1\n:SHA.L R1H, b2_reg32 is R1H & b1_0007=0xeb; b2_0507=0x1 & b2_reg32 & b2_0003=0x1 {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:4 = b2_reg32;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val s>> shift;\n b2_reg32 = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n b2_reg32 = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n### SHL ###\nmacro SHLsetShiftRightFlags(val,shift,result) {\n local c = (val >> (shift - 1)) & 1;\n $(CARRY) = c:1;\n setResultFlags(result);\n} \n\nmacro SHLsetShiftLeftFlags(val,shift,result,sze) {\n local c = (val >> (sze - shift)) & 1;\n $(CARRY) = c:1;\n setResultFlags(result);\n}\n\n# (1) SHL.B #imm4, dst (right)\n:SHL.B srcSimm4Shift_0407, dst4B is (b1_0107=0x74 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=1) ... & dst4B {\n val:1 = dst4B;\n shift:1 = -srcSimm4Shift_0407;\n tmp:1 = val >> shift;\n dst4B = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.B #imm4, Ax (right)\n:SHL.B srcSimm4Shift_0407, dst4Ax is (b1_0107=0x74 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=1) & $(DST4AX) {\n val:1 = dst4Ax:1;\n shift:1 = -srcSimm4Shift_0407;\n tmp:1 = val >> shift;\n dst4Ax = zext(tmp);\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.W #imm4, dst (right)\n:SHL.W srcSimm4Shift_0407, dst4W is (b1_0107=0x74 & b1_size_0=1; srcSimm4Shift_0407 & b2_shiftSign_7=1) ... & dst4W {\n val:2 = dst4W;\n shift:1 = -srcSimm4Shift_0407;\n tmp:2 = val >> shift;\n dst4W = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.B #imm4, dst (left)\n:SHL.B srcSimm4Shift_0407, dst4B is (b1_0107=0x74 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=0) ... & dst4B {\n val:1 = dst4B;\n shift:1 = srcSimm4Shift_0407;\n tmp:1 = val << shift;\n dst4B = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHL.B #imm4, Ax (left)\n:SHL.B srcSimm4Shift_0407, dst4Ax is (b1_0107=0x74 & b1_size_0=0; srcSimm4Shift_0407 & b2_shiftSign_7=0) & $(DST4AX) {\n val:1 = dst4Ax:1;\n shift:1 = srcSimm4Shift_0407;\n tmp:1 = val << shift;\n dst4Ax = zext(tmp);\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHL.W #imm4, dst (left)\n:SHL.W srcSimm4Shift_0407, dst4W is (b1_0107=0x74 & b1_size_0=1; srcSimm4Shift_0407 & b2_shiftSign_7=0) ... & dst4W {\n val:2 = dst4W;\n shift:1 = srcSimm4Shift_0407;\n tmp:2 = val << shift;\n dst4W = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (2) SHL.B R1H, dst\n:SHL.B R1H, dst4B is (R1H & b1_0107=0x3a & b1_size_0=0; b2_0407=0xe) ... & dst4B {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst4B;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val >> shift;\n dst4B = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst4B = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (2) SHL.B R1H, Ax\n:SHL.B R1H, dst4Ax is (R1H & b1_0107=0x3a & b1_size_0=0; b2_0407=0xe) & $(DST4AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst4Ax:1;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val >> shift;\n dst4Ax = zext(tmp);\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst4Ax = zext(tmp);\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (2) SHL.W R1H, dst\n:SHL.W R1H, dst4W is (R1H & b1_0107=0x3a & b1_size_0=1; b2_0407=0xe) ... & dst4W {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:2 = dst4W;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:2 = val >> shift;\n dst4W = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst4W = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (3) SHL.L #imm4, R2R0/R3R1 (right)\n:SHL.L srcSimm4Shift_0003, b2_reg32 is b1_0007=0xeb; b2_0507=0x4 & b2_reg32 & srcSimm4Shift_0003 & b2_shiftSign_3=1 {\n val:4 = b2_reg32;\n shift:1 = -srcSimm4Shift_0003;\n tmp:4 = val >> shift;\n b2_reg32 = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (3) SHL.L #imm4, R2R0/R3R1 (left)\n:SHL.L srcSimm4Shift_0003, b2_reg32 is b1_0007=0xeb; b2_0507=0x4 & b2_reg32 & srcSimm4Shift_0003 & b2_shiftSign_3=0 {\n val:4 = b2_reg32;\n shift:1 = srcSimm4Shift_0003;\n tmp:4 = val << shift;\n b2_reg32 = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n# (4) SHL.L R1H, R2R0/R3R1\n:SHL.L R1H, b2_reg32 is R1H & b1_0007=0xeb; b2_0507=0x0 & b2_reg32 & b2_0003=0x1 {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:4 = b2_reg32;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val >> shift;\n b2_reg32 = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n b2_reg32 = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n### SMOVB ###\n\n:SMOVB.B is b1_0107=0x3e & b1_size_0=0; b2_0007=0xe9 {\n if (R3 == 0) goto inst_next;\n ptr0:3 = (zext(R1H) << 16) + zext(A0);\n ptr1:3 = zext(A1);\n *:1 ptr1 = *:1 ptr0;\n A1 = A1 - 1;\n ptr0 = ptr0 - 1;\n A0 = ptr0:2;\n R1H = ptr0(2);\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SMOVB.W is b1_0107=0x3e & b1_size_0=1; b2_0007=0xe9 {\n if (R3 == 0) goto inst_next;\n ptr0:3 = (zext(R1H) << 16) + zext(A0);\n ptr1:3 = zext(A1);\n *:2 ptr1 = *:2 ptr0;\n A1 = A1 - 2;\n ptr0 = ptr0 - 2;\n A0 = ptr0:2;\n R1H = ptr0(2);\n R3 = R3 - 1;\n goto inst_start;\n}\n\n### SMOVF ###\n\n:SMOVF.B is b1_0107=0x3e & b1_size_0=0; b2_0007=0xe8 {\n if (R3 == 0) goto inst_next;\n ptr0:3 = (zext(R1H) << 16) + zext(A0);\n ptr1:3 = zext(A1);\n *:1 ptr1 = *:1 ptr0;\n A1 = A1 + 1;\n ptr0 = ptr0 + 1;\n A0 = ptr0:2;\n R1H = ptr0(2);\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SMOVF.W is b1_0107=0x3e & b1_size_0=1; b2_0007=0xe8 {\n if (R3 == 0) goto inst_next;\n ptr0:3 = (zext(R1H) << 16) + zext(A0);\n ptr1:3 = zext(A1);\n *:2 ptr1 = *:2 ptr0;\n A1 = A1 + 2;\n ptr0 = ptr0 + 2;\n A0 = ptr0:2;\n R1H = ptr0(2);\n R3 = R3 - 1;\n goto inst_start;\n}\n\n### SSTR ###\n\n:SSTR.B is b1_0107=0x3e & b1_size_0=0; b2_0007=0xea {\n if (R3 == 0) goto inst_next;\n ptr1:3 = zext(A1);\n *:1 ptr1 = R0L;\n A1 = A1 + 1;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SSTR.W is b1_0107=0x3e & b1_size_0=1; b2_0007=0xea {\n if (R3 == 0) goto inst_next;\n ptr1:3 = zext(A1);\n *:2 ptr1 = R0;\n A1 = A1 + 2;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n### STC ###\n\n# (1) STC src, dst\n:STC b2_creg16, dst4W is (b1_0007=0x7b; b2_0707=1 & b2_creg16) ... & dst4W {\n dst4W = b2_creg16;\n}\n\n# (2) STC PC, dst (dst=register)\n:STC PC, dst4L is (PC & b1_0007=0x7c; b2_0407=0xc) ... & dst4L {\n dst4L = zext(PC);\n}\n\n# (2) STC PC, dst (dst=memory)\n:STC PC, dst4T is (PC & b1_0007=0x7c; b2_0407=0xc) ... & $(DST4T) {\n dst4T = inst_next; # PC value refers to next instruction address\n}\n\n### STCTX ###\n\n:STCTX abs16offset, abs20offset is b1_0007=0xb6; b2_0007=0xd3; abs16offset; imm20_dat & abs20offset {\n\n taskNum:1 = abs16offset; # load task number stored at abs16\n ptr:3 = imm20_dat + (zext(taskNum) * 2); # compute table entry address relative to abs20\n regInfo:1 = *:1 ptr;\n ptr = ptr + 1;\n spCorrect:1 = *:1 ptr;\n\n ptr = zext(SP);\n\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = FB;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = SB;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = A1;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = A0;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R3;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R2;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R1;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R0;\n \n SP = SP - zext(spCorrect);\n}\n\n### STE ###\n\n# (1) STE.B src, abs20\n:STE.B dst4B, abs20offset is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0) ... & dst4B); abs20offset {\n val:1 = dst4B;\n abs20offset = val;\n setResultFlags(val);\n}\n\n# (1) STE.W src, abs20\n:STE.W dst4W, abs20offsetW is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0) ... & dst4W); abs20offsetW {\n val:2 = dst4W;\n abs20offsetW = val;\n setResultFlags(val);\n}\n\n# (2) STE.B src, dsp:20[A0]\n:STE.B dst4B, dsp20A0B is ((b1_0107=0x3a & b1_size_0=0; b2_0407=0x1) ... & dst4B); dsp20A0B {\n val:1 = dst4B;\n dsp20A0B = val;\n setResultFlags(val);\n}\n\n# (2) STE.W src, dsp:20[A0]\n:STE.W dst4W, dsp20A0W is ((b1_0107=0x3a & b1_size_0=1; b2_0407=0x1) ... & dst4W); dsp20A0W {\n val:2 = dst4W;\n dsp20A0W = val;\n setResultFlags(val);\n}\n\nsteA1A0B: \"[\"^A1A0^\"]\" is A1A0 { ptr:3 = A1A0:3; export *:1 ptr; }\n\nsteA1A0W: \"[\"^A1A0^\"]\" is A1A0 { ptr:3 = A1A0:3; export *:2 ptr; }\n\n# (3) STE.B src, [A1A0]\n:STE.B dst4B, steA1A0B is (steA1A0B & b1_0107=0x3a & b1_size_0=0; b2_0407=0x2) ... & dst4B {\n val:1 = dst4B;\n steA1A0B = val;\n setResultFlags(val);\n}\n\n# (3) STE.W src, [A1A0]\n:STE.W dst4W, steA1A0W is (steA1A0W & b1_0107=0x3a & b1_size_0=1; b2_0407=0x2) ... & dst4W {\n val:2 = dst4W;\n steA1A0W = val;\n setResultFlags(val);\n}\n\n### STNZ ###\n\n:STNZ srcImm8, dst3B_afterDsp8 is (b1_0307=0x1a; srcImm8) ... & $(DST3B_AFTER_DSP8) {\n if ($(ZERO) != 0) goto inst_next;\n dst3B_afterDsp8 = srcImm8;\n}\n\n### STZ ###\n\n:STZ srcImm8, dst3B_afterDsp8 is (b1_0307=0x19; srcImm8) ... & $(DST3B_AFTER_DSP8) {\n if ($(ZERO) == 0) goto inst_next;\n dst3B_afterDsp8 = srcImm8;\n}\n\n### STZX ###\nskipBytesBeforeImm82: is b1_0007; imm8_dat { } # imm81\nskipBytesBeforeImm82: is b1_d3=0x5; imm16_dat { } # imm81; dsp8\nskipBytesBeforeImm82: is b1_d3=0x6; imm16_dat { } # imm81; dsp8\nskipBytesBeforeImm82: is b1_d3=0x7; imm24_dat { } # imm81; abs16\n\nstzxImm82: \"#\"^imm8_dat is skipBytesBeforeImm82; imm8_dat { export *[const]:1 imm8_dat; }\n\n:STZX srcImm8, stzxImm82, dst3B_afterDsp8 is (b1_0307=0x1b; srcImm8) ... & $(DST3B_AFTER_DSP8) ... & stzxImm82 {\n z:1 = $(ZERO);\n dst3B_afterDsp8 = (z * srcImm8) + (!z * stzxImm82);\n}\n\n### SUB ###\n\n# (1) SUB.B:G #simm, dst\n:SUB^\".B:G\" srcSimm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x5) ... & dst4B); srcSimm8 {\n tmp:1 = dst4B;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SUB.B:G #simm, Ax\n:SUB^\".B:G\" srcSimm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x5) & $(DST4AX)); srcSimm8 {\n tmp:1 = dst4Ax:1;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) SUB.W:G #simm, dst\n:SUB^\".W:G\" srcSimm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x5) ... & dst4W); srcSimm16 {\n tmp:2 = dst4W;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SUB.B:S #simm, dst\n:SUB^\".B:S\" srcSimm8, dst3B_afterDsp8 is (b1_0307=0x11; srcSimm8) ... & $(DST3B_AFTER_DSP8) {\n tmp:1 = dst3B_afterDsp8;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n dst3B_afterDsp8 = tmp;\n setResultFlags(tmp);\n}\n\n# (3) SUB.B:G src, dst\n:SUB^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x54 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4;\n src:1 = src4B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (3) SUB.B:G src, Ax\n:SUB^\".B:G\" src4B, dst4Ax is (b1_0107=0x54 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1;\n src:1 = src4B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (3) SUB.W:G src, dst\n:SUB^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x54 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4;\n src:2 = src4W;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) SUB.B:S src, R0H/R0L\n:SUB^\".B:S\" dst2B, b1_2_reg8 is (b1_0307=0x5 & b1_2_reg8) ... & dst2B {\n tmp:1 = b1_2_reg8;\n src:1 = dst2B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n b1_2_reg8 = tmp;\n setResultFlags(tmp);\n}\n\n### TST ###\n\n# (1) TST.B #imm, dst\n:TST.B srcImm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x0) ... & dst4B); srcImm8 {\n tmp:1 = dst4B & srcImm8;\n setResultFlags(tmp);\n}\n\n# (1) TST.W #imm, dst\n:TST.W srcImm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x0) ... & dst4W); srcImm16 {\n tmp:2 = dst4W & srcImm16;\n setResultFlags(tmp);\n}\n\n# (2) TST.B src, dst\n:TST.B src4B, dst4B_afterSrc4 is (b1_0107=0x40 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4 & src4B;\n setResultFlags(tmp);\n}\n\n# (2) TST.W src, dst\n:TST.W src4W, dst4W_afterSrc4 is (b1_0107=0x40 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4 & src4W;\n setResultFlags(tmp);\n}\n\n##### UND #####\n# Don't implement this \"Undefined\" instruction\n# :UND is b1_0007=0xff\n\n### WAIT ###\n\n:WAIT is b1_0007=0x7d; b2_0007=0xf3 {\n Wait();\n}\n\n### XCHG ###\n\n:XCHG.B b2_s4_reg8, dst4B is (b1_0107=0x3d & b1_size_0=0; b2_0607=0 & b2_s4_reg8) ... & dst4B {\n tmp:1 = dst4B;\n dst4B = b2_s4_reg8;\n b2_s4_reg8 = tmp;\n}\n\n:XCHG.B b2_s4_reg8, dst4Ax is (b1_0107=0x3d & b1_size_0=0; b2_0607=0 & b2_s4_reg8) & $(DST4AX) {\n tmp:1 = dst4Ax:1;\n dst4Ax = zext(b2_s4_reg8);\n b2_s4_reg8 = tmp;\n}\n\n:XCHG.W b2_s4_reg16, dst4W is (b1_0107=0x3d & b1_size_0=1; b2_0607=0 & b2_s4_reg16) ... & dst4W {\n tmp:2 = dst4W;\n dst4W = b2_s4_reg16;\n b2_s4_reg16 = tmp;\n}\n\n### XOR ###\n\n# (1) XOR.B:G #imm, dst\n:XOR^\".B:G\" srcImm8, dst4B is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x1) ... & dst4B); srcImm8 {\n tmp:1 = dst4B ^ srcImm8;\n dst4B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) XOR.B:G #imm, Ax\n:XOR^\".B:G\" srcImm8, dst4Ax is ((b1_0107=0x3b & b1_size_0=0; b2_0407=0x1) & $(DST4AX)); srcImm8 {\n tmp:1 = dst4Ax:1 ^ srcImm8;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) XOR.W:G #imm, dst\n:XOR^\".W:G\" srcImm16, dst4W is ((b1_0107=0x3b & b1_size_0=1; b2_0407=0x1) ... & dst4W); srcImm16 {\n tmp:2 = dst4W ^ srcImm16;\n dst4W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) XOR.B:G src, dst\n:XOR^\".B:G\" src4B, dst4B_afterSrc4 is (b1_0107=0x44 & b1_size_0=0) ... & src4B ... & dst4B_afterSrc4 ... {\n tmp:1 = dst4B_afterSrc4 ^ src4B;\n dst4B_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) XOR.B:G src, Ax\n:XOR^\".B:G\" src4B, dst4Ax is (b1_0107=0x44 & b1_size_0=0) ... & src4B & $(DST4AX) ... {\n tmp:1 = dst4Ax:1 ^ src4B;\n dst4Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) XOR.W:G src, dst\n:XOR^\".W:G\" src4W, dst4W_afterSrc4 is (b1_0107=0x44 & b1_size_0=1) ... & src4W ... & dst4W_afterSrc4 ... {\n tmp:2 = dst4W_afterSrc4 ^ src4W;\n dst4W_afterSrc4 = tmp;\n setResultFlags(tmp);\n}\n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_80.cspec", "content": "\n\n\n \n \n \n \n \n \n\t\n\t\t\t\n \n \n \n \n \n\t\n\t\n \n \n \n\t\n\t\n \n \n \n \n\t\n \n \n\n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_80.ldefs", "content": "\n\n\n \n \n Renesas M16C/80 16-Bit MicroComputer\n \n \n \n\n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_80.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n" }, { "path": "pypcode/processors/M16C/data/languages/M16C_80.slaspec", "content": "#\n# Renesas M16C/80 16-Bit MicroComputer\n#\n\n#\n# Memory Architecture\n#\ndefine endian=little;\n\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=3 default;\ndefine space register type=register_space size=2;\n\n#\n# General Registers\n#\ndefine register offset=0x0000 size=2 [\n R0 R2 R1 R3\n];\n\ndefine register offset=0x0000 size=1 [\n R0L R0H _ _ R1L R1H _ _\n];\n\ndefine register offset=0x0000 size=4 [\n R2R0 R3R1\n];\n\ndefine register offset=0x0000 size=6 [\n R1R2R0\n];\n\ndefine register offset=0x2000 size=3 [\n A0 A1\n];\n\ndefine register offset=0x3000 size=3 [\n PC # Program Counter\n SVP # Save PC Register\n VCT # Vector Register \n byteIndexOffset # Byte offset for memory (see useByteIndex)\n bitIndex # Index offset for bit operations (see useBitIndex)\n];\n\ndefine register offset=0x4000 size=3 [\n INTB\n];\n\ndefine register offset=0x4000 size=2 [\n INTBL INTBH\n];\n\ndefine register offset=0x5000 size=3 [\n SP # Stack Pointer (Represents active stack pointer: ISP or USP)\n FB # Frame Base Register\n SB # Static Base Register \n ISP # Interrupt Stack Pointer\n];\n\ndefine register offset=0x6000 size=2 [\n FLG # Flag Register\n SVF # Save Flag Register\n];\n\n@define CARRY \"FLG[0,1]\"\n@define DEBUG \"FLG[1,1]\"\n@define ZERO \"FLG[2,1]\"\n@define SIGN \"FLG[3,1]\"\n@define REG_BANK \"FLG[4,1]\"\n@define OVERFLOW \"FLG[5,1]\"\n@define INTERRUPT \"FLG[6,1]\"\n@define STACK_SEL \"FLG[7,1]\"\n@define IPL \"FLG[12,3]\"\n\ndefine register offset=0x7000 size=2 [\n # These are really 1-Byte registers\n DMD0 # DMA mode register\n DMD1 # DMA mode register\n];\n\ndefine register offset=0x8000 size=2 [\n DCT0 # DMA transfer count register\n DCT1 # DMA transfer count register\n DRC0 # DMA transfer count reload register\n DRC1 # DMA transfer count reload register\n];\n\ndefine register offset=0x9000 size=3 [\n DMA0 # DMA memory address register\n DMA1 # DMA memory address register\n DSA0 # DMA SFR address register\n DSA1 # DMA SFR address register\n DRA0 # DMA memory address reload register\n DRA1 # DMA memory address reload register\n];\n\n# Define context bits\ndefine register offset=0xA000 size=4 contextreg;\n\ndefine context contextreg\n useBitIndex = (0, 0) noflow # =1 use bitIndex instead of bit specified by instruction\n useByteIndexOffset = (1, 2) noflow \n useSrcByteIndexOffset = (1, 1) noflow\n useDstByteIndexOffset = (2, 2) noflow\n\n # transient context:\n phase = (3, 4) # guard for saving off modes before starting instructions\n indDst = (5, 5) # =1 indirect destination\n indSrc = (6, 6) # =1 indirect source\n dstFollowsSrc = (7, 8) # =1 destination add-on data follows 5-bit encoded source add-on data\n # =2 destination add-on data follows 8-bit data\n;\n\ndefine token b0(8)\n b0_0007 = (0,7)\n;\n\ndefine token b1(8)\n b1_s5 = (4,6)\n b1_s5_4 = (6,6)\n b1_d5 = (1,3)\n b1_d5_4 = (3,3)\n b1_d2 = (4,5)\n b1_d1_regAx = (0,0)\n b1_size_5 = (5,5)\n b1_size_4 = (4,4)\n b1_size_0 = (0,0)\n b1_0707 = (7,7)\n b1_0607 = (6,7)\n b1_0507 = (5,7)\n b1_0505 = (5,5)\n b1_0407 = (4,7)\n b1_0406 = (4,6)\n b1_0405 = (4,5)\n b1_0104 = (1,4)\n b1_0103 = (1,3)\n b1_0007 = (0,7)\n b1_0000 = (0,0)\n;\n\ndefine token b2(8)\n b2_d5_reg8 = (6,7)\n b2_s5_reg8 = (4,5)\n b2_d5_reg16 = (6,7)\n b2_s5_reg16 = (4,5)\n b2_d5_reg32 = (6,6) # only d0 used to select double register\n b2_s5_reg32 = (4,4) # only s0 used to select double register\n b2_d5_regAxSF = (6,7) # selects A0, A1, SB or FB\n b2_s5_regAxSF = (4,5) # selects A0, A1, SB or FB\n b2_d5_regAx = (6,6)\n b2_s5_regAx = (4,4)\n b2_d5 = (6,7)\n b2_s5 = (4,5)\n b2_d5_1 = (7,7)\n b2_d5_0 = (6,6)\n b2_s5_1 = (5,5)\n b2_s5_0 = (4,4)\n b2_0707 = (7,7)\n b2_0606 = (6,6)\n b2_0405 = (4,5)\n b2_0307 = (3,7)\n b2_0305 = (3,5)\n b2_0105 = (1,5)\n b2_0102 = (1,2)\n b2_0101 = (1,1)\n b2_0007 = (0,7)\n b2_0005 = (0,5)\n b2_0003 = (0,3)\n b2_0002 = (0,2)\n b2_simm4 = (0,3) signed\n b2_shiftSign = (3,3)\n b2_bit = (0,2)\n b2_reg8 = (0,2)\n b2_reg16 = (0,2)\n b2_creg16 = (0,2)\n b2_creg24 = (0,2)\n b2_dreg24 = (0,2)\n b2_reg32 = (0,0)\n b2_regAx = (0,0)\n;\n\ndefine token imm8(8)\n simm8_dat = (0,7) signed\n imm8_dat = (0,7)\n imm6_dat = (2,7)\n cnd_dat = (0,3)\n imm8_0001 = (0,1)\n regBit7 = (7,7)\n regBit6 = (6,6)\n regBit5 = (5,5)\n regBit4 = (4,4)\n regBit3 = (3,3)\n regBit2 = (2,2)\n regBit1 = (1,1)\n regBit0 = (0,0)\n;\n\ndefine token imm16(16)\n simm16_dat = (0,15) signed\n imm16_dat = (0,15)\n;\n\ndefine token imm24(24)\n simm24_dat = (0,23) signed\n imm24_dat = (0,23)\n;\n\ndefine token imm32(32)\n simm32_dat = (0,31) signed\n imm32_dat = (0,31)\n;\n\nattach variables [ b2_s5_reg32 b2_d5_reg32 ] [ R2R0 R3R1 ];\nattach variables [ b2_s5_reg16 b2_d5_reg16 ] [ R2 R3 R0 R1 ];\nattach variables [ b2_s5_reg8 b2_d5_reg8 ] [ R0H R1H R0L R1L ];\nattach variables [ b2_s5_regAx b2_d5_regAx b1_d1_regAx b2_regAx ] [ A0 A1 ];\nattach variables [ b2_s5_regAxSF b2_d5_regAxSF ] [ A0 A1 SB FB ];\nattach variables [ b2_creg16 ] [ DCT0 DCT1 FLG SVF DRC0 DRC1 DMD0 DMD1 ];\nattach variables [ b2_creg24 ] [ INTB SP SB FB SVP VCT _ ISP ];\nattach variables [ b2_dreg24 ] [ _ _ DMA0 DMA1 DRA0 DRA1 DSA0 DSA1 ];\nattach variables [ b2_reg32 ] [ R2R0 R3R1 ];\n\n# XCHG register attach\nattach variables [ b2_reg8 ] [ R0L R1L _ _ R0H R1H _ _ ];\nattach variables [ b2_reg16 ] [ R0 R1 _ _ R2 R3 _ _ ];\n\n#\n# PCode Op\n# \ndefine pcodeop Break; # BRK\ndefine pcodeop Break2; # BRK2\ndefine pcodeop DecimalAdd; # DADD\ndefine pcodeop DecimalAddWithCarry; # DADC\ndefine pcodeop DecimalSubtractWithBorrow; # DSBB\ndefine pcodeop DecimalSubtract; # DSUB\ndefine pcodeop Wait; # WAIT\n\n#\n# FLAG MACROS...\n#\n# Set zero and sign flags from result\nmacro setResultFlags(result) {\n $(SIGN) = (result s< 0x0);\n $(ZERO) = (result == 0x0);\n}\n\n# Set carry and overflow flags for addition\nmacro setAdd3Flags(v1, v2, v3) {\n local add13 = v1 + v3;\n $(CARRY) = carry(v1,v3) || carry(v2,add13);\n $(OVERFLOW) = scarry(v1,v3) || scarry(v2,add13);\n}\n\n# Set carry and overflow flags for addition\nmacro setAddFlags(v1, v2) {\n $(CARRY) = carry(v1, v2);\n $(OVERFLOW) = scarry(v1, v2);\n}\n\n# Set overflow flags for subtraction of op3,op2 from op1 (op1-op2-op3)\nmacro setSubtract3Flags(v1, v2, v3) {\n local add12 = v1 - v2;\n $(CARRY) = (v1 >= v2) || (add12 >= v3);\n $(OVERFLOW) = sborrow(v1, v2) || sborrow(add12, v3);\n}\n\n# Set overflow flags for subtraction of op2 from op1 (op1-op2)\nmacro setSubtractFlags(v1, v2) {\n $(CARRY) = (v1 s>= v2);\n $(OVERFLOW) = sborrow(v1, v2);\n}\n\nmacro push1(val) {\n SP = SP - 2;\n *:1 SP = val;\n}\n\nmacro push2(val) {\n SP = SP - 2;\n *:2 SP = val;\n}\n\nmacro push3(val) {\n SP = SP - 4;\n *:3 SP = val;\n}\n\nmacro push4(val) {\n SP = SP - 4;\n *:4 SP = val;\n}\n\nmacro pop1(val) {\n val = *:1 SP;\n SP = SP + 2;\n}\n\nmacro pop2(val) {\n val = *:2 SP;\n SP = SP + 2;\n}\n\nmacro pop3(val) {\n val = *:3 SP;\n SP = SP + 4;\n}\n\nmacro pop4(val) {\n val = *:4 SP;\n SP = SP + 4;\n}\n\n:^instruction is phase=0 & b0_0007 & instruction [ phase=1; ] {}\n:^instruction is phase=0 & b0_0007=0x09; instruction [ indDst=1; phase=1; ] {} # indirect destination prefix\n:^instruction is phase=0 & b0_0007=0x41; instruction [ indSrc=1; phase=1; ] {} # indirect source prefix \n:^instruction is phase=0 & b0_0007=0x49; instruction [ indDst=1; indSrc=1; phase=1; ] {} # indirect source and destination prefix\n\n#\n# Source operand location data\n#\n# Obtain additional source byte offset as a result of an INDEX instruction (flagged by useSrcByteIndexOffset context bit)\nsrcIndexOffset: is useSrcByteIndexOffset=0 { export 0:3; }\nsrcIndexOffset: is useSrcByteIndexOffset=1 { export byteIndexOffset; }\n\n# Obtain base offset displacement for [AX | SB | FB] - AX and SB uses unsigned displacements, FB uses signed displacement\nsrc5dsp8: imm8_dat^\":8\" is b1_s5; b2_s5; imm8_dat { export *[const]:3 imm8_dat; }\nsrc5dsp8: simm8_dat^\":8\" is b1_s5; b2_s5=0x3; simm8_dat { export *[const]:3 simm8_dat; }\n\nsrc5dsp16: imm16_dat^\":16\" is b1_s5; b2_s5; imm16_dat { export *[const]:3 imm16_dat; }\nsrc5dsp16: simm16_dat^\":16\" is b1_s5; b2_s5=0x3; simm16_dat { export *[const]:3 simm16_dat; }\n\nsrc5dsp24: imm24_dat^\":24\" is b1_s5; b2_s5; imm24_dat { export *[const]:3 imm24_dat; }\nsrc5dsp24: simm24_dat^\":24\" is b1_s5; b2_s5=0x3; simm24_dat { export *[const]:3 simm24_dat; }\n\n# src5... Handle 5-bit encoded Source specified by b1_s(3-bits) and b2_s(2-bits)\n# Variable length pattern starting at instruction byte b1\n# associated src5 add-on data immediately follows instruction byte b2\n# abs16 and abs24 cases are broken out differently to facilitate export of constant addresses in certain cases\n# 1-Byte source value/location specified by 5-bit encoding (b1_d5/b2_d5) - supports indirect prefix and byteIndexOffset\nsrc5B: b2_s5_reg8 is b1_s5=0x4; b2_s5_reg8 { export b2_s5_reg8; } # Rx\nsrc5B: b2_s5_regAx is b1_s5=0x0; b2_s5_1=1 & b2_s5_regAx { tmp:1 = b2_s5_regAx:1; export tmp; } # Ax\nsrc5B: [b2_s5_regAx] is indSrc=1 & b1_s5=0x0; b2_s5_1=1 & b2_s5_regAx { ptr:3 = b2_s5_regAx; export *:1 ptr; } # [Ax] - w/ indirect prefix\nsrc5B: [b2_s5_regAx] is srcIndexOffset & b1_s5=0x0; b2_s5_1=0 & b2_s5_regAx { ptr:3 = b2_s5_regAx + srcIndexOffset; export *:1 ptr; } # [Ax]\nsrc5B: [[b2_s5_regAx]] is indSrc=1 & srcIndexOffset & b1_s5=0x0; b2_s5_1=0 & b2_s5_regAx { ptr:3 = b2_s5_regAx + srcIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [[Ax]]\nsrc5B: src5dsp8^[b2_s5_regAxSF] is (srcIndexOffset & b1_s5=0x1; b2_s5_regAxSF) ... & src5dsp8 { ptr:3 = b2_s5_regAxSF + src5dsp8 + srcIndexOffset; export *:1 ptr; } # dsp:8[Ax|SB|FB]\nsrc5B: [src5dsp8^[b2_s5_regAxSF]] is (indSrc=1 & srcIndexOffset & b1_s5=0x1; b2_s5_regAxSF) ... & src5dsp8 { ptr:3 = b2_s5_regAxSF + src5dsp8 + srcIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [dsp:8[Ax|SB|FB]]\nsrc5B: src5dsp16^[b2_s5_regAxSF] is (srcIndexOffset & b1_s5=0x2; b2_s5_regAxSF) ... & src5dsp16 { ptr:3 = b2_s5_regAxSF + src5dsp16 + srcIndexOffset; export *:1 ptr; } # dsp:16[Ax|SB|FB]\nsrc5B: [src5dsp16^[b2_s5_regAxSF]] is (indSrc=1 & srcIndexOffset & b1_s5=0x2; b2_s5_regAxSF) ... & src5dsp16 { ptr:3 = b2_s5_regAxSF + src5dsp16 + srcIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [dsp:16[Ax|SB|FB]]\nsrc5B: src5dsp24^[b2_s5_regAx] is (srcIndexOffset & b1_s5=0x3; b2_s5_1=0 & b2_s5_regAx) ... & src5dsp24 { ptr:3 = b2_s5_regAx + src5dsp24 + srcIndexOffset; export *:1 ptr; } # dsp:24[Ax]\nsrc5B: [src5dsp24^[b2_s5_regAx]] is (indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5_1=0 & b2_s5_regAx) ... & src5dsp24 { ptr:3 = b2_s5_regAx + src5dsp24 + srcIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [dsp:24[Ax]]\nsrc5B: imm16_dat is indSrc=0 & useSrcByteIndexOffset=1 & b1_s5=0x3; b2_s5=0x3; imm16_dat { ptr:3 = imm16_dat + byteIndexOffset; export *:1 ptr; } # abs16 (+byteIndexOffset)\nsrc5B: imm16_dat is indSrc=0 & b1_s5=0x3; b2_s5=0x3; imm16_dat { export *:1 imm16_dat; } # abs16 (special constant address case)\nsrc5B: [imm16_dat] is indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5=0x3; imm16_dat { ptr:3 = imm16_dat + srcIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [abs16]\nsrc5B: imm24_dat is indSrc=0 & useSrcByteIndexOffset=1 & b1_s5=0x3; b2_s5=0x2; imm24_dat { ptr:3 = imm24_dat + byteIndexOffset; export *:1 ptr; } # abs24 (+byteIndexOffset)\nsrc5B: imm24_dat is indSrc=0 & b1_s5=0x3; b2_s5=0x2; imm24_dat { export *:1 imm24_dat; } # abs24 (special constant address case)\nsrc5B: [imm24_dat] is indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5=0x2; imm24_dat { ptr:3 = imm24_dat + srcIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [abs24]\n\n# 2-Byte source value/location specified by 5-bit encoding (b1_d5/b2_d5) - supports indirect prefix and byteIndexOffset\nsrc5W: b2_s5_reg16 is b1_s5=0x4; b2_s5_reg16 { export b2_s5_reg16; } # Rx\nsrc5W: b2_s5_regAx is b1_s5=0x0; b2_s5_1=1 & b2_s5_regAx { tmp:2 = b2_s5_regAx:2; export tmp; } # Ax\nsrc5W: [b2_s5_regAx] is indSrc=1 & b1_s5=0x0; b2_s5_1=1 & b2_s5_regAx { ptr:3 = b2_s5_regAx; export *:2 ptr; } # [Ax] - w/ indirect prefix\nsrc5W: [b2_s5_regAx] is srcIndexOffset & b1_s5=0x0; b2_s5_1=0 & b2_s5_regAx { ptr:3 = b2_s5_regAx + srcIndexOffset; export *:2 ptr; } # [Ax]\nsrc5W: [[b2_s5_regAx]] is indSrc=1 & srcIndexOffset & b1_s5=0x0; b2_s5_1=0 & b2_s5_regAx { ptr:3 = b2_s5_regAx + srcIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [[Ax]]\nsrc5W: src5dsp8^[b2_s5_regAxSF] is (srcIndexOffset & b1_s5=0x1; b2_s5_regAxSF) ... & src5dsp8 { ptr:3 = b2_s5_regAxSF + src5dsp8 + srcIndexOffset; export *:2 ptr; } # dsp:8[Ax|SB|FB]\nsrc5W: [src5dsp8^[b2_s5_regAxSF]] is (indSrc=1 & srcIndexOffset & b1_s5=0x1; b2_s5_regAxSF) ... & src5dsp8 { ptr:3 = b2_s5_regAxSF + src5dsp8 + srcIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [dsp:8[Ax|SB|FB]]\nsrc5W: src5dsp16^[b2_s5_regAxSF] is (srcIndexOffset & b1_s5=0x2; b2_s5_regAxSF) ... & src5dsp16 { ptr:3 = b2_s5_regAxSF + src5dsp16 + srcIndexOffset; export *:2 ptr; } # dsp:16[Ax|SB|FB]\nsrc5W: [src5dsp16^[b2_s5_regAxSF]] is (indSrc=1 & srcIndexOffset & b1_s5=0x2; b2_s5_regAxSF) ... & src5dsp16 { ptr:3 = b2_s5_regAxSF + src5dsp16 + srcIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [dsp:16[Ax|SB|FB]]\nsrc5W: src5dsp24^[b2_s5_regAx] is (srcIndexOffset & b1_s5=0x3; b2_s5_1=0 & b2_s5_regAx) ... & src5dsp24 { ptr:3 = b2_s5_regAx + src5dsp24 + srcIndexOffset; export *:2 ptr; } # dsp:24[Ax]\nsrc5W: [src5dsp24^[b2_s5_regAx]] is (indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5_1=0 & b2_s5_regAx) ... & src5dsp24 { ptr:3 = b2_s5_regAx + src5dsp24 + srcIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [dsp:24[Ax]]\nsrc5W: imm16_dat is indSrc=0 & useSrcByteIndexOffset=1 & b1_s5=0x3; b2_s5=0x3; imm16_dat { ptr:3 = imm16_dat + byteIndexOffset; export *:2 ptr; } # abs16 (+byteIndexOffset)\nsrc5W: imm16_dat is indSrc=0 & b1_s5=0x3; b2_s5=0x3; imm16_dat { export *:2 imm16_dat; } # abs16 (special constant address case) \nsrc5W: [imm16_dat] is indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5=0x3; imm16_dat { ptr:3 = imm16_dat + srcIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [abs16]\nsrc5W: imm24_dat is indSrc=0 & useSrcByteIndexOffset=1 & b1_s5=0x3; b2_s5=0x2; imm24_dat { ptr:3 = imm24_dat + byteIndexOffset; export *:2 ptr; } # abs24 (+byteIndexOffset)\nsrc5W: imm24_dat is indSrc=0 & b1_s5=0x3; b2_s5=0x2; imm24_dat { export *:2 imm24_dat; } # abs24 (special constant address case)\nsrc5W: [imm24_dat] is indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5=0x2; imm24_dat { ptr:3 = imm24_dat + srcIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [abs24]\n\n# 4-Byte source value/location specified by 5-bit encoding (b1_d5/b2_d5) - supports indirect prefix and byteIndexOffset\nsrc5L: b2_s5_reg32 is b1_s5=0x4; b2_s5_1=1 & b2_s5_reg32 { export b2_s5_reg32; } # Rx\nsrc5L: b2_s5_regAx is b1_s5=0x0; b2_s5_1=1 & b2_s5_regAx { tmp:4 = zext(b2_s5_regAx); export tmp; } # Ax\nsrc5L: [b2_s5_regAx] is indSrc=1 & b1_s5=0x0; b2_s5_1=1 & b2_s5_regAx { ptr:3 = b2_s5_regAx; export *:4 ptr; } # [Ax] - w/ indirect prefix\nsrc5L: [b2_s5_regAx] is srcIndexOffset & b1_s5=0x0; b2_s5_1=0 & b2_s5_regAx { ptr:3 = b2_s5_regAx + srcIndexOffset; export *:4 ptr; } # [Ax]\nsrc5L: [[b2_s5_regAx]] is indSrc=1 & srcIndexOffset & b1_s5=0x0; b2_s5_1=0 & b2_s5_regAx { ptr:3 = b2_s5_regAx + srcIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [[Ax]]\nsrc5L: src5dsp8^[b2_s5_regAxSF] is (srcIndexOffset & b1_s5=0x1; b2_s5_regAxSF) ... & src5dsp8 { ptr:3 = b2_s5_regAxSF + src5dsp8 + srcIndexOffset; export *:4 ptr; } # dsp:8[Ax|SB|FB]\nsrc5L: [src5dsp8^[b2_s5_regAxSF]] is (indSrc=1 & srcIndexOffset & b1_s5=0x1; b2_s5_regAxSF) ... & src5dsp8 { ptr:3 = b2_s5_regAxSF + src5dsp8 + srcIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [dsp:8[Ax|SB|FB]]\nsrc5L: src5dsp16^[b2_s5_regAxSF] is (srcIndexOffset & b1_s5=0x2; b2_s5_regAxSF) ... & src5dsp16 { ptr:3 = b2_s5_regAxSF + src5dsp16 + srcIndexOffset; export *:4 ptr; } # dsp:16[Ax|SB|FB]\nsrc5L: [src5dsp16^[b2_s5_regAxSF]] is (indSrc=1 & srcIndexOffset & b1_s5=0x2; b2_s5_regAxSF) ... & src5dsp16 { ptr:3 = b2_s5_regAxSF + src5dsp16 + srcIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [dsp:16[Ax|SB|FB]]\nsrc5L: src5dsp24^[b2_s5_regAx] is (srcIndexOffset & b1_s5=0x3; b2_s5_1=0 & b2_s5_regAx) ... & src5dsp24 { ptr:3 = b2_s5_regAx + src5dsp24 + srcIndexOffset; export *:4 ptr; } # dsp:24[Ax]\nsrc5L: [src5dsp24^[b2_s5_regAx]] is (indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5_1=0 & b2_s5_regAx) ... & src5dsp24 { ptr:3 = b2_s5_regAx + src5dsp24 + srcIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [dsp:24[Ax]]\nsrc5L: imm16_dat is indSrc=0 & useSrcByteIndexOffset=1 & b1_s5=0x3; b2_s5=0x3; imm16_dat { ptr:3 = imm16_dat + byteIndexOffset; export *:4 ptr; } # abs16 (+byteIndexOffset)\nsrc5L: imm16_dat is indSrc=0 & b1_s5=0x3; b2_s5=0x3; imm16_dat { export *:4 imm16_dat; } # abs16 (special constant address case)\nsrc5L: [imm16_dat] is indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5=0x3; imm16_dat { ptr:3 = imm16_dat + srcIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [abs16]\nsrc5L: imm24_dat is indSrc=0 & useSrcByteIndexOffset=1 & b1_s5=0x3; b2_s5=0x2; imm24_dat { ptr:3 = imm24_dat + byteIndexOffset; export *:4 ptr; } # abs24 (+byteIndexOffset)\nsrc5L: imm24_dat is indSrc=0 & b1_s5=0x3; b2_s5=0x2; imm24_dat { export *:4 imm24_dat; } # abs24 (special constant address case)\nsrc5L: [imm24_dat] is indSrc=1 & srcIndexOffset & b1_s5=0x3; b2_s5=0x2; imm24_dat { ptr:3 = imm24_dat + srcIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [abs24]\n\n#\n# The following macros are used to elliminate illegal bit patterns when using src5\n# These should be used by constructor pattern matching instead of the corresponding src5 subconstructor\n#\n@define SRC5B \"((b1_s5=4 | b1_s5_4=0) ... & src5B)\"\n@define SRC5W \"((b1_s5=4 | b1_s5_4=0) ... & src5W)\"\n@define SRC5L \"((b1_s5=4 | b1_s5_4=0) ... & src5L)\"\n\n#\n# Destination operand location data (may also be used as a source in certain cases)\n#\n# Skip instruction and source add-on bytes which occur before destination add-on bytes\n# Starting position is at b1\nskipBytesBeforeDst5: is b1_s5; b2_s5 { }\nskipBytesBeforeDst5: is dstFollowsSrc=1 & b1_s5=1; b2_s5; imm8_dat { } # src5: dsp8\nskipBytesBeforeDst5: is dstFollowsSrc=1 & b1_s5=2; b2_s5; imm16_dat { } # src5: dsp16\nskipBytesBeforeDst5: is dstFollowsSrc=1 & b1_s5=3; b2_s5; imm24_dat { } # src5: dsp24/abs24\nskipBytesBeforeDst5: is dstFollowsSrc=1 & b1_s5=3; b2_s5=3; imm16_dat { } # src5: abs16\nskipBytesBeforeDst5: is dstFollowsSrc=2 & b1_d5; b2_d5; imm8_dat { } # dsp8\n\n# Obtain additional destination byte offset as a result of an INDEX instruction (flagged by useDstByteIndexOffset context bit)\ndstIndexOffset: is useDstByteIndexOffset=0 { export 0:3; }\ndstIndexOffset: is useDstByteIndexOffset=1 { export byteIndexOffset; }\n\n# Obtain base offset displacement for [AX | SB | FB] - AX and SB uses unsigned displacements, FB uses signed displacement\ndst5dsp8: imm8_dat^\":8\" is (skipBytesBeforeDst5; imm8_dat) { export *[const]:3 imm8_dat; }\ndst5dsp8: simm8_dat^\":8\" is (b1_d5; b2_d5=0x3) ... & (skipBytesBeforeDst5; simm8_dat) { export *[const]:3 simm8_dat; } \ndst5dsp16: imm16_dat^\":16\" is (skipBytesBeforeDst5; imm16_dat) { export *[const]:3 imm16_dat; }\ndst5dsp16: simm16_dat^\":16\" is (b1_d5; b2_d5=0x3) ... & (skipBytesBeforeDst5; simm16_dat) { export *[const]:3 simm16_dat; } \ndst5dsp24: imm24_dat^\":24\" is (skipBytesBeforeDst5; imm24_dat) { export *[const]:3 imm24_dat; }\n\n# dst5... Handle 5-bit encoded Destination specified by b1_d5(3-bits) and b2_d5(2-bits)\n# Ax direct case is read-only! Instruction must use dst5Ax for write/update case\n# Variable length pattern starting at instruction byte b1\n# abs16 and abs24 cases are broken out differently to facilitate export of constant addresses in certain cases\n# 1-Byte destination value/location specified by 5-bit encoding (b1_d5/b2_d5) - supports indirect prefix and byteIndexOffset\ndst5B: b2_d5_reg8 is b1_d5=0x4; b2_d5_reg8 { export b2_d5_reg8; } # Rx\ndst5B: b2_d5_regAx is b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { tmp:1 = b2_d5_regAx:1; export tmp; } # Ax - read-only use !\ndst5B: [b2_d5_regAx] is indDst=1 & b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { ptr:3 = b2_d5_regAx; export *:1 ptr; } # [Ax] - w/ indirect prefix\ndst5B: [b2_d5_regAx] is dstIndexOffset & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + dstIndexOffset; export *:1 ptr; } # [Ax]\ndst5B: [[b2_d5_regAx]] is indDst=1 & dstIndexOffset & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + dstIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [[Ax]]\ndst5B: dst5dsp8^[b2_d5_regAxSF] is (dstIndexOffset & b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8 + dstIndexOffset; export *:1 ptr; } # dsp:8[Ax|SB|FB]\ndst5B: [dst5dsp8^[b2_d5_regAxSF]] is (indDst=1 & dstIndexOffset & b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8 + dstIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [dsp:8[Ax|SB|FB]]\ndst5B: dst5dsp16^[b2_d5_regAxSF] is (dstIndexOffset & b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16 + dstIndexOffset; export *:1 ptr; } # dsp:16[Ax|SB|FB]\ndst5B: [dst5dsp16^[b2_d5_regAxSF]] is (indDst=1 & dstIndexOffset & b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16 + dstIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [dsp:16[Ax|SB|FB]]\ndst5B: dst5dsp24^[b2_d5_regAx] is (dstIndexOffset & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24 + dstIndexOffset; export *:1 ptr; } # dsp:24[Ax]\ndst5B: [dst5dsp24^[b2_d5_regAx]] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24 + dstIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [dsp:24[Ax]]\ndst5B: imm16_dat is (indDst=0 & useDstByteIndexOffset=1 & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { ptr:3 = imm16_dat + byteIndexOffset; export *:1 ptr; } # abs16 (+byteIndexOffset)\ndst5B: imm16_dat is (indDst=0 & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { export *:1 imm16_dat; } # abs16 (special constant address case)\ndst5B: [imm16_dat] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { ptr:3 = imm16_dat + dstIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [abs16]\ndst5B: imm24_dat is (indDst=0 & useDstByteIndexOffset=1 & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { ptr:3 = imm24_dat + byteIndexOffset; export *:1 ptr; } # abs24\ndst5B: imm24_dat is (indDst=0 & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { export *:1 imm24_dat; } # abs24 (special constant address case)\ndst5B: [imm24_dat] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { ptr:3 = imm24_dat + dstIndexOffset; ptr = *:3 ptr; export *:1 ptr; } # [abs24]\n\n# 2-Byte destination value/location specified by 5-bit encoding (b1_d5/b2_d5) - supports indirect prefix and byteIndexOffset\ndst5W: b2_d5_reg16 is b1_d5=0x4; b2_d5_reg16 { export b2_d5_reg16; } # Rx\ndst5W: b2_d5_regAx is b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { tmp:2 = b2_d5_regAx:2; export tmp; } # Ax - read-only use !\ndst5W: [b2_d5_regAx] is indDst=1 & b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { ptr:3 = b2_d5_regAx; export *:2 ptr; } # [Ax] - w/ indirect prefix\ndst5W: [b2_d5_regAx] is dstIndexOffset & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + dstIndexOffset; export *:2 ptr; } # [Ax]\ndst5W: [[b2_d5_regAx]] is indDst=1 & dstIndexOffset & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + dstIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [[Ax]]\ndst5W: dst5dsp8^[b2_d5_regAxSF] is (dstIndexOffset & b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8 + dstIndexOffset; export *:2 ptr; } # dsp:8[Ax|SB|FB]\ndst5W: [dst5dsp8^[b2_d5_regAxSF]] is (indDst=1 & dstIndexOffset & b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8 + dstIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [dsp:8[Ax|SB|FB]]\ndst5W: dst5dsp16^[b2_d5_regAxSF] is (dstIndexOffset & b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16 + dstIndexOffset; export *:2 ptr; } # dsp:16[Ax|SB|FB]\ndst5W: [dst5dsp16^[b2_d5_regAxSF]] is (indDst=1 & dstIndexOffset & b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16 + dstIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [dsp:16[Ax|SB|FB]]\ndst5W: dst5dsp24^[b2_d5_regAx] is (dstIndexOffset & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24 + dstIndexOffset; export *:2 ptr; } # dsp:24[Ax]\ndst5W: [dst5dsp24^[b2_d5_regAx]] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24 + dstIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [dsp:24[Ax]]\ndst5W: imm16_dat is (indDst=0 & useDstByteIndexOffset=1 & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { ptr:3 = imm16_dat + byteIndexOffset; export *:2 ptr; } # abs16 (+byteIndexOffset)\ndst5W: imm16_dat is (indDst=0 & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { export *:2 imm16_dat; } # abs16 (special constant address case)\ndst5W: [imm16_dat] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { ptr:3 = imm16_dat + dstIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [abs16]\ndst5W: imm24_dat is (indDst=0 & useDstByteIndexOffset=1 & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { ptr:3 = imm24_dat + byteIndexOffset; export *:2 ptr; } # abs24\ndst5W: imm24_dat is (indDst=0 & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { export *:2 imm24_dat; } # abs24 (special constant address case)\ndst5W: [imm24_dat] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { ptr:3 = imm24_dat + dstIndexOffset; ptr = *:3 ptr; export *:2 ptr; } # [abs24]\n\n# 4-Byte destination value/location specified by 5-bit encoding (b1_d5/b2_d5) - supports indirect prefix and byteIndexOffset\ndst5L: b2_d5_reg32 is b1_d5=0x4; b2_d5_1=1 & b2_d5_reg32 { export b2_d5_reg32; } # Rx\ndst5L: b2_d5_regAx is b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { tmp:4 = zext(b2_d5_regAx); export tmp; } # Ax - read-only use !\ndst5L: [b2_d5_regAx] is indDst=1 & b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { ptr:3 = b2_d5_regAx; export *:4 ptr; } # [Ax] - w/ indirect prefix\ndst5L: [b2_d5_regAx] is dstIndexOffset & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + dstIndexOffset; export *:4 ptr; } # [Ax]\ndst5L: [[b2_d5_regAx]] is indDst=1 & dstIndexOffset & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + dstIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [[Ax]]\ndst5L: dst5dsp8^[b2_d5_regAxSF] is (dstIndexOffset & b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8 + dstIndexOffset; export *:4 ptr; } # dsp:8[Ax|SB|FB]\ndst5L: [dst5dsp8^[b2_d5_regAxSF]] is (indDst=1 & dstIndexOffset & b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8 + dstIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [dsp:8[Ax|SB|FB]]\ndst5L: dst5dsp16^[b2_d5_regAxSF] is (dstIndexOffset & b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16 + dstIndexOffset; export *:4 ptr; } # dsp:16[Ax|SB|FB]\ndst5L: [dst5dsp16^[b2_d5_regAxSF]] is (indDst=1 & dstIndexOffset & b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16 + dstIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [dsp:16[Ax|SB|FB]]\ndst5L: dst5dsp24^[b2_d5_regAx] is (dstIndexOffset & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24 + dstIndexOffset; export *:4 ptr; } # dsp:24[Ax]\ndst5L: [dst5dsp24^[b2_d5_regAx]] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24 + dstIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [dsp:24[Ax]]\ndst5L: imm16_dat is (indDst=0 & useDstByteIndexOffset=1 & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { ptr:3 = imm16_dat + byteIndexOffset; export *:4 ptr; } # abs16 (+byteIndexOffset)\ndst5L: imm16_dat is (indDst=0 & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { export *:4 imm16_dat; } # abs16 (special constant address case)\ndst5L: [imm16_dat] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { ptr:3 = imm16_dat + dstIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [abs16]\ndst5L: imm24_dat is (indDst=0 & useDstByteIndexOffset=1 & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { ptr:3 = imm24_dat + byteIndexOffset; export *:4 ptr; } # abs24\ndst5L: imm24_dat is (indDst=0 & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { export *:4 imm24_dat; } # abs24 (special constant address case)\ndst5L: [imm24_dat] is (indDst=1 & dstIndexOffset & b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { ptr:3 = imm24_dat + dstIndexOffset; ptr = *:3 ptr; export *:4 ptr; } # [abs24]\n\n# 3-Byte destination effective address specified by 5-bit encoding (b1_d5/b2_d5)\ndst5A: dst5dsp8^[b2_d5_regAxSF] is (b1_d5=0x1; b2_d5_regAxSF) ... & dst5dsp8 { ptr:3 = b2_d5_regAxSF + dst5dsp8; export ptr; } # dsp:8[Ax|SB|FB]\ndst5A: dst5dsp16^[b2_d5_regAxSF] is (b1_d5=0x2; b2_d5_regAxSF) ... & dst5dsp16 { ptr:3 = b2_d5_regAxSF + dst5dsp16; export ptr; } # dsp:16[Ax|SB|FB]\ndst5A: dst5dsp24^[b2_d5_regAx] is (b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & dst5dsp24 { ptr:3 = b2_d5_regAx + dst5dsp24; export ptr; } # dsp:24[Ax]\ndst5A: imm16_dat is (b1_d5=0x3; b2_d5=0x3) ... & (skipBytesBeforeDst5; imm16_dat) { export *[const]:3 imm16_dat; } # abs16 (special constant address case)\ndst5A: imm24_dat is (b1_d5=0x3; b2_d5=0x2) ... & (skipBytesBeforeDst5; imm24_dat) { export *[const]:3 imm24_dat; } # abs24 (special constant address case)\n\n# Ax destination specified by 5-bit encoding (b1_d5/b2_d5)\n# NOTE! Ax destination is special case and must be handled seperately by each instruction\n# Starting position is at instruction b1\ndst5Ax: b2_d5_regAx is b1_d5; b2_d5_regAx { export b2_d5_regAx; }\n\n# 1/2/4-Byte destination value/location specified by 5-bit encoding (b1_d5/b2_d5)\n# This handles the case for dst5B, dst5W and dst5L where 5-bit encoded Source (src5) add-on bytes may exist before Destination add-on bytes\n# Variable length pattern starting at instruction byte b1\ndst5B_afterSrc5: dst5B is dst5B [ dstFollowsSrc=1; ] { export dst5B; }\n\ndst5W_afterSrc5: dst5W is dst5W [ dstFollowsSrc=1; ] { export dst5W; }\n\ndst5L_afterSrc5: dst5L is dst5L [ dstFollowsSrc=1; ] { export dst5L; }\n\n# 1/2/4-Byte destination value/location specified by 5-bit encoding (b1_d5/b2_d5)\n# This handles the case for dst5B, dst5W and dst5L where Dsp8 add-on bytes always exist before Destination add-on bytes\n# Variable length pattern starting at instruction byte b1\ndst5B_afterDsp8: dst5B is dst5B [ dstFollowsSrc=2; ] { export dst5B; }\n\ndst5W_afterDsp8: dst5W is dst5W [ dstFollowsSrc=2; ] { export dst5W; }\n\n#\n# The following macros are used to elliminate illegal bit patterns when using dst5\n# These should be used by constructor pattern matching instead of the corresponding dst5 subconstructor\n#\n@define DST5B \"((b1_d5=4 | b1_d5_4=0) ... & dst5B)\"\n@define DST5W \"((b1_d5=4 | b1_d5_4=0) ... & dst5W)\"\n@define DST5L \"((b1_d5=4 | b1_d5_4=0) ... & dst5L)\"\n@define DST5A \"((b1_d5_4=0) ... & dst5A)\"\n@define DST5AX \"((b1_d5=0x0; b2_d5_1=1) & dst5Ax)\" \n@define DST5B_AFTER_SRC5 \"((b1_d5=4 | b1_d5_4=0) ... & dst5B_afterSrc5)\"\n@define DST5W_AFTER_SRC5 \"((b1_d5=4 | b1_d5_4=0) ... & dst5W_afterSrc5)\"\n@define DST5L_AFTER_SRC5 \"((b1_d5=4 | b1_d5_4=0) ... & dst5L_afterSrc5)\"\n@define DST5B_AFTER_DSP8 \"((b1_d5=4 | b1_d5_4=0) ... & dst5B_afterDsp8)\"\n@define DST5W_AFTER_DSP8 \"((b1_d5=4 | b1_d5_4=0) ... & dst5W_afterDsp8)\"\n@define DST5L_AFTER_DSP8 \"((b1_d5=4 | b1_d5_4=0) ... & dst5L_afterDsp8)\"\n\n# dst2... Handle 2-bit encoded Destination specified by b1_d2\n# Variable length pattern starting at instruction byte b1\n# TODO? Certain uses of dst2 should exclude the R0 case (b1_d2=0)\n# 1-Byte destination value/location specified by 2-bit encoding (b1_d2)\ndst2B: R0L is b1_d2=0 & R0L { export R0L; }\ndst2B: imm16_dat is b1_d2=1; imm16_dat { export *:1 imm16_dat; }\ndst2B: [imm16_dat] is indDst=1 & b1_d2=1; imm16_dat { ptr:3 = imm16_dat; ptr = *:3 ptr; export *:1 ptr; }\ndst2B: imm8_dat^\":8\"^[SB] is b1_d2=2 & SB; imm8_dat { ptr:3 = SB + imm8_dat; export *:1 ptr; }\ndst2B: [imm8_dat^\":8\"^[SB]] is indDst=1 & b1_d2=2 & SB; imm8_dat { ptr:3 = SB + imm8_dat; ptr = *:3 ptr; export *:1 ptr; }\ndst2B: simm8_dat^\":8\"^[FB] is b1_d2=3 & FB; simm8_dat { ptr:3 = FB + simm8_dat; export *:1 ptr; }\ndst2B: [simm8_dat^\":8\"^[FB]] is indDst=1 & b1_d2=3 & FB; simm8_dat { ptr:3 = FB + simm8_dat; ptr = *:3 ptr; export *:1 ptr; }\n\n# 2-Byte destination value/location specified by 2-bit encoding (b1_d2)\ndst2W: R0 is b1_d2=0 & R0 { export R0; }\ndst2W: imm16_dat is b1_d2=1; imm16_dat { export *:2 imm16_dat; }\ndst2W: [imm16_dat] is indDst=1 & b1_d2=1; imm16_dat { ptr:3 = imm16_dat; ptr = *:3 ptr; export *:2 ptr; }\ndst2W: imm8_dat^\":8\"^[SB] is b1_d2=2 & SB; imm8_dat { ptr:3 = SB + imm8_dat; export *:2 ptr; }\ndst2W: [imm8_dat^\":8\"^[SB]] is indDst=1 & b1_d2=2 & SB; imm8_dat { ptr:3 = SB + imm8_dat; ptr = *:3 ptr; export *:2 ptr; }\ndst2W: simm8_dat^\":8\"^[FB] is b1_d2=3 & FB; simm8_dat { ptr:3 = FB + simm8_dat; export *:2 ptr; }\ndst2W: [simm8_dat^\":8\"^[FB]] is indDst=1 & b1_d2=3 & FB; simm8_dat { ptr:3 = FB + simm8_dat; ptr = *:3 ptr; export *:2 ptr; }\n\n# 4-Byte destination value/location specified by 2-bit encoding (b1_d2)\ndst2L: R2R0 is b1_d2=0 & R2R0 { export R2R0; }\ndst2L: imm16_dat is b1_d2=1; imm16_dat { export *:4 imm16_dat; }\ndst2L: [imm16_dat] is indDst=1 & b1_d2=1; imm16_dat { ptr:3 = imm16_dat; ptr = *:3 ptr; export *:4 ptr; }\ndst2L: imm8_dat^\":8\"^[SB] is b1_d2=2 & SB; imm8_dat { ptr:3 = SB + imm8_dat; export *:4 ptr; }\ndst2L: [imm8_dat^\":8\"^[SB]] is indDst=1 & b1_d2=2 & SB; imm8_dat { ptr:3 = SB + imm8_dat; ptr = *:3 ptr; export *:4 ptr; }\ndst2L: simm8_dat^\":8\"^[FB] is b1_d2=3 & FB; simm8_dat { ptr:3 = FB + simm8_dat; export *:4 ptr; }\ndst2L: [simm8_dat^\":8\"^[FB]] is indDst=1 & b1_d2=3 & FB; simm8_dat { ptr:3 = FB + simm8_dat; ptr = *:3 ptr; export *:4 ptr; }\n\ndsp8spB: simm8_dat^\":8\"^[SP] is simm8_dat & SP { ptr:3 = SP + simm8_dat; export *:1 ptr; }\n\ndsp8spW: simm8_dat^\":8\"^[SP] is simm8_dat & SP { ptr:3 = SP + simm8_dat; export *:2 ptr; }\n\n#\n# Bit base - associated add-on data immediately follows instruction byte b2\n# (Ax destination case must be handled seperately)\n#\n# Obtain bitbase offset displacement for [AX | SB | FB] - AX and SB uses unsigned displacements, FB uses signed displacement\nbitbaseDsp8: imm8_dat^\":11\" is b1_d5; b2_d5; imm8_dat { export *[const]:3 imm8_dat; }\nbitbaseDsp8: simm8_dat^\":11\" is b1_d5; b2_d5=0x3; simm8_dat { export *[const]:3 simm8_dat; }\n\nbitbaseDsp16: imm16_dat^\":19\" is b1_d5; b2_d5; imm16_dat { export *[const]:3 imm16_dat; }\nbitbaseDsp16: simm16_dat^\":19\" is b1_d5; b2_d5=0x3; simm16_dat { export *[const]:3 simm16_dat; }\n\nbitbaseDsp24: imm24_dat^\":27\" is b1_d5; b2_d5; imm24_dat { export *[const]:3 imm24_dat; }\nbitbaseDsp24: simm24_dat^\":27\" is b1_d5; b2_d5=0x3; simm24_dat { export *[const]:3 simm24_dat; }\n\nbitbase: b2_d5_reg8 is useBitIndex=0 & b1_d5=0x4; b2_d5_reg8 { export b2_d5_reg8; } # Rx\nbitbase: b2_d5_regAx is useBitIndex=0 & b1_d5=0x0; b2_d5_1=1 & b2_d5_regAx { tmp:1 = b2_d5_regAx:1; export tmp; } # Ax - read-only case\nbitbase: [b2_d5_regAx] is useBitIndex=0 & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx; export *:1 ptr; } # [Ax]\nbitbase: bitbaseDsp8^[b2_d5_regAxSF] is (useBitIndex=0 & b1_d5=0x1; b2_d5_regAxSF) ... & bitbaseDsp8 { ptr:3 = b2_d5_regAxSF + bitbaseDsp8; export *:1 ptr; } # base:11[Ax|SB|FB]\nbitbase: bitbaseDsp16^[b2_d5_regAxSF] is (useBitIndex=0 & b1_d5=0x2; b2_d5_regAxSF) ... & bitbaseDsp16 { ptr:3 = b2_d5_regAxSF + bitbaseDsp16; export *:1 ptr; } # base:19[Ax|SB|FB]\nbitbase: bitbaseDsp24^[b2_d5_regAx] is (useBitIndex=0 & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & bitbaseDsp24 { ptr:3 = b2_d5_regAx + bitbaseDsp24; export *:1 ptr; } # base:27[Ax]\nbitbase: imm16_dat^\":19\" is useBitIndex=0 & b1_d5=0x3; b2_d5=0x3; imm16_dat { export *:1 imm16_dat; } # base:19\nbitbase: imm24_dat^\":27\" is useBitIndex=0 & b1_d5=0x3; b2_d5=0x2; imm24_dat { export *:1 imm24_dat; } # base:27\n\nbitbase: [b2_d5_regAx] is useBitIndex=1 & b1_d5=0x0; b2_d5_1=0 & b2_d5_regAx { ptr:3 = b2_d5_regAx + (bitIndex / 8); export *:1 ptr; } # [Ax] w/bitIndex\nbitbase: bitbaseDsp8^[b2_d5_regAxSF] is (useBitIndex=1 & b1_d5=0x1; b2_d5_regAxSF) ... & bitbaseDsp8 { ptr:3 = b2_d5_regAxSF + bitbaseDsp8 + (bitIndex / 8); export *:1 ptr; } # base:11[Ax|SB|FB] w/bitIndex\nbitbase: bitbaseDsp16^[b2_d5_regAxSF] is (useBitIndex=1 & b1_d5=0x2; b2_d5_regAxSF) ... & bitbaseDsp16 { ptr:3 = b2_d5_regAxSF + bitbaseDsp16 + (bitIndex / 8); export *:1 ptr; } # base:19[Ax|SB|FB] w/bitIndex\nbitbase: bitbaseDsp24^[b2_d5_regAx] is (useBitIndex=1 & b1_d5=0x3; b2_d5_1=0 & b2_d5_regAx) ... & bitbaseDsp24 { ptr:3 = b2_d5_regAx + bitbaseDsp24 + (bitIndex / 8); export *:1 ptr; } # base:27[Ax] w/bitIndex\nbitbase: imm16_dat^\":19\" is useBitIndex=1 & b1_d5=0x3; b2_d5=0x3; imm16_dat { ptr:3 = imm16_dat + (bitIndex / 8); export *:1 ptr; } # base:19 w/bitIndex\nbitbase: imm24_dat^\":27\" is useBitIndex=1 & b1_d5=0x3; b2_d5=0x2; imm24_dat { ptr:3 = imm24_dat + (bitIndex / 8); export *:1 ptr; } # base:27 w/bitIndex\n\n# Ax bitbase destination specified by 5-bit encoding (b1_d5/b2_d5)\n# NOTE! Ax destination is special case and must be handled seperately by each instruction\n# Starting position is at instruction b1\nbitbaseAx: b2_d5_regAx is b1_d5; b2_d5_regAx { export b2_d5_regAx; }\n\nbitbaseAbs16: imm16_dat is imm16_dat { export *:1 imm16_dat; }\n\n#\n# The following macros are used to elliminate illegal bit patterns when using dst5\n# These should be used by constructor pattern matching instead of the corresponding dst5 subconstructor\n#\n@define BITBASE \"((b1_d5=4 | b1_d5_4=0) ... & bitbase)\"\n@define BITBASE_AX \"((b1_d5=0x0; b2_d5_1=1) & bitbaseAx)\"\n\n# Bit identifier (may be overriden if useBitIndex has been set by BINDEX instruction\nbit: b2_bit is useBitIndex=0 & b2_bit { export *[const]:1 b2_bit; }\nbit: [bitIndex] is useBitIndex=1 & bitIndex { val:3 = bitIndex % 8; b:1 = val:1; export b; }\n\n#\n# Immediate data operand\n# Fixed length - current position is at start of immediate data\n#\nsrcImm3: \"#\"^b2_0002 is b2_0002 { export *[const]:1 b2_0002; }\nsrcImm8: \"#\"^imm8_dat is imm8_dat { export *[const]:1 imm8_dat; }\n\nsrcImm8a: \"#\"^imm8_dat is imm8_dat { export *[const]:1 imm8_dat; } # used when two imm8 are needed\n\nsrcImm16: \"#\"^imm16_dat is imm16_dat { export *[const]:2 imm16_dat; }\n\nsrcImm16a: \"#\"^imm16_dat is imm16_dat { export *[const]:2 imm16_dat; } # used when two imm16 are needed\n\nsrcImm24: \"#\"^imm24_dat is imm24_dat { export *[const]:3 imm24_dat; }\nsrcImm32: \"#\"^imm32_dat is imm32_dat { export *[const]:4 imm32_dat; }\n\n# Unsigned immediate data from 1-bit value: 1 <= value <= 2 (1 added to unsigned bit value)\nsrcImm1p: \"#\"^val is b1_0505 [ val = b1_0505 + 1; ] { export *[const]:1 val; }\n\n# Unsigned immediate data from 2-bit value: 1 <= value <= 8 (1 added to unsigned bit value)\nsrcImm3p: \"#\"^val is b1_0405 & b1_0000 [ val = (b1_0405 << 1) + b1_0000 + 1; ] { export *[const]:1 val; }\n\nsrcSimm8: \"#\"^simm8_dat is simm8_dat { export *[const]:1 simm8_dat; }\nsrcSimm16: \"#\"^simm16_dat is simm16_dat { export *[const]:2 simm16_dat; }\nsrcSimm32: \"#\"^simm32_dat is simm32_dat { export *[const]:4 simm32_dat; }\n\n# Signed immediate data from signed 4-bit value: -8 <= value <= 7\nsrcSimm4: \"#\"^b2_simm4 is b2_simm4 { export *[const]:1 b2_simm4; }\n\nsrcSimm8a: srcSimm8 is srcSimm8 { export srcSimm8; }\n\nsrcSimm16a: srcSimm16 is srcSimm16 { export srcSimm16; }\n\n# Signed immediate shift amount from 4-bit value: -8 <= value <= -1 || 1 <= value <= 8\nsrcSimm4Shift: \"#\"^val is b2_shiftSign=0 & b2_0002 [ val = b2_0002 + 1; ] { export *[const]:1 val; }\nsrcSimm4Shift: \"#\"^val is b2_shiftSign=1 & b2_0002 [ val = -(b2_0002 + 1); ] { export *[const]:1 val; }\n\nsrcZero8: \"#0\" is b1_0007 { export 0:1; }\nsrcZero16: \"#0\" is b1_0007 { export 0:2; }\n\n# special 6-bit immediate for INT number\nsrcIntNum: \"#\"^imm6_dat is imm6_dat { export *[const]:1 imm6_dat; }\n\n#\n# Offset label operand\n#\nabs24offset: imm24_dat is imm24_dat { export *:1 imm24_dat; }\n\nabs16offset: imm16_dat is imm16_dat { export *:1 imm16_dat; }\n\n# Relative address offsets\nrel16offset1: offs is simm16_dat [ offs = inst_start + 1 + simm16_dat; ] { export *:1 offs; }\n\nrel8offset1: offs is simm8_dat [ offs = inst_start + 1 + simm8_dat; ] { export *:1 offs; }\nrel8offset2: offs is simm8_dat [ offs = inst_start + 2 + simm8_dat; ] { export *:1 offs; }\n\nrel3offset2: offs is b1_0405 & b1_0000 [ offs = inst_start + 2 + ((b1_0405 << 1) + b1_0000); ] { export *:1 offs; }\n\nreloffset_dst5W: dst5W is $(DST5W) { local reladdr = inst_start + dst5W; export *:3 reladdr; }\n\nreloffset_dst5L: dst5L is $(DST5L) { local reladdr = inst_start + dst5L; export *:3 reladdr; }\n\nreloffset_dst5Ax: dst5Ax is $(DST5AX) { local reladdr = inst_start + dst5Ax; export *:3 reladdr; }\n\n#\n# Conditionals (see BMcnd)\n#\n# TODO!! Need to verify conditional logic pulled from old slaspec\n# TODO: the 'cnd' subconstructor should really constrain the bits 4-7 to 0x0, however this exposes a sleigh compiler problem\ncnd: \"LTU\" is cnd_dat=0x0 { tstCnd:1 = ($(CARRY) == 0); export tstCnd; } # less than (>), C flag is 0\ncnd: \"LEU\" is cnd_dat=0x1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 0); export tstCnd; } # Equal to or less than (>=)\ncnd: \"NE\" is cnd_dat=0x2 { tstCnd:1 = ($(ZERO) == 0); export tstCnd; } # Not Equal to (=), Z flag is 0 \ncnd: \"PZ\" is cnd_dat=0x3 { tstCnd:1 = ($(SIGN) == 0); export tstCnd; } # Positive or zero (0<=)\ncnd: \"NO\" is cnd_dat=0x4 { tstCnd:1 = ($(OVERFLOW) == 0); export tstCnd; } # O flag is 0\ncnd: \"GT\" is cnd_dat=0x5 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 0); export tstCnd; } # Greater than (signed value) (<)\ncnd: \"GE\" is cnd_dat=0x6 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 0); export tstCnd; } # Equal to or greater than (signed value) (<=)\ncnd: \"GEU\" is cnd_dat=0x8 { tstCnd:1 = ($(CARRY) == 1); export tstCnd; } # Equal to or greater than (<=), C flag is 1 \ncnd: \"GTU\" is cnd_dat=0x9 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 1); export tstCnd; } # Greater than (<)\ncnd: \"EQ\" is cnd_dat=0xa { tstCnd:1 = ($(ZERO) == 1); export tstCnd; } # Equal to (=), Z flag is 1\ncnd: \"N\" is cnd_dat=0xb { tstCnd:1 = ($(SIGN) == 1); export tstCnd; } # Negative (0>)\ncnd: \"O\" is cnd_dat=0xc { tstCnd:1 = ($(OVERFLOW) == 1); export tstCnd; } # O flag is 1\ncnd: \"LE\" is cnd_dat=0xd { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 1); export tstCnd; } # Equal to or less than (signed value) (>=)\ncnd: \"LT\" is cnd_dat=0xe { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 1); export tstCnd; } # less than (signed value) (<=)\n\nb2cnd: \"LTU\" is b2_0606=0 & b2_0002=0 { tstCnd:1 = ($(CARRY) == 0); export tstCnd; } # less than (>), C flag is 0\nb2cnd: \"LEU\" is b2_0606=0 & b2_0002=1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 0); export tstCnd; } # Equal to or less than (>=)\nb2cnd: \"NE\" is b2_0606=0 & b2_0002=2 { tstCnd:1 = ($(ZERO) == 0); export tstCnd; } # Not Equal to (=), Z flag is 0 \nb2cnd: \"PZ\" is b2_0606=0 & b2_0002=3 { tstCnd:1 = ($(SIGN) == 0); export tstCnd; } # Positive or zero (0<=)\nb2cnd: \"NO\" is b2_0606=0 & b2_0002=4 { tstCnd:1 = ($(OVERFLOW) == 0); export tstCnd; } # O flag is 0\nb2cnd: \"GT\" is b2_0606=0 & b2_0002=5 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 0); export tstCnd; } # Greater than (signed value) (<)\nb2cnd: \"GE\" is b2_0606=0 & b2_0002=6 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 0); export tstCnd; } # Equal to or greater than (signed value) (<=)\nb2cnd: \"GEU\" is b2_0606=1 & b2_0002=0 { tstCnd:1 = ($(CARRY) == 1); export tstCnd; } # Equal to or greater than (<=), C flag is 1 \nb2cnd: \"GTU\" is b2_0606=1 & b2_0002=1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 1); export tstCnd; } # Greater than (<)\nb2cnd: \"EQ\" is b2_0606=1 & b2_0002=2 { tstCnd:1 = ($(ZERO) == 1); export tstCnd; } # Equal to (=), Z flag is 1\nb2cnd: \"N\" is b2_0606=1 & b2_0002=3 { tstCnd:1 = ($(SIGN) == 1); export tstCnd; } # Negative (0>)\nb2cnd: \"O\" is b2_0606=1 & b2_0002=4 { tstCnd:1 = ($(OVERFLOW) == 1); export tstCnd; } # O flag is 1\nb2cnd: \"LE\" is b2_0606=1 & b2_0002=5 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 1); export tstCnd; } # Equal to or less than (signed value) (>=)\nb2cnd: \"LT\" is b2_0606=1 & b2_0002=6 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 1); export tstCnd; } # less than (signed value) (<=)\n\nb1cnd: \"LTU\" is b1_0406=0 & b1_0000=0 { tstCnd:1 = ($(CARRY) == 0); export tstCnd; } # less than (>), C flag is 0\nb1cnd: \"LEU\" is b1_0406=0 & b1_0000=1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 0); export tstCnd; } # Equal to or less than (>=)\nb1cnd: \"NE\" is b1_0406=1 & b1_0000=0 { tstCnd:1 = ($(ZERO) == 0); export tstCnd; } # Not Equal to (=), Z flag is 0 \nb1cnd: \"PZ\" is b1_0406=1 & b1_0000=1 { tstCnd:1 = ($(SIGN) == 0); export tstCnd; } # Positive or zero (0<=)\nb1cnd: \"NO\" is b1_0406=2 & b1_0000=0 { tstCnd:1 = ($(OVERFLOW) == 0); export tstCnd; } # O flag is 0\nb1cnd: \"GT\" is b1_0406=2 & b1_0000=1 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 0); export tstCnd; } # Greater than (signed value) (<)\nb1cnd: \"GE\" is b1_0406=3 & b1_0000=0 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 0); export tstCnd; } # Equal to or greater than (signed value) (<=)\nb1cnd: \"GEU\" is b1_0406=4 & b1_0000=0 { tstCnd:1 = ($(CARRY) == 1); export tstCnd; } # Equal to or greater than (<=), C flag is 1 \nb1cnd: \"GTU\" is b1_0406=4 & b1_0000=1 { tstCnd:1 = (($(CARRY) & (!$(ZERO))) == 1); export tstCnd; } # Greater than (<)\nb1cnd: \"EQ\" is b1_0406=5 & b1_0000=0 { tstCnd:1 = ($(ZERO) == 1); export tstCnd; } # Equal to (=), Z flag is 1\nb1cnd: \"N\" is b1_0406=5 & b1_0000=1 { tstCnd:1 = ($(SIGN) == 1); export tstCnd; } # Negative (0>)\nb1cnd: \"O\" is b1_0406=6 & b1_0000=0 { tstCnd:1 = ($(OVERFLOW) == 1); export tstCnd; } # O flag is 1\nb1cnd: \"LE\" is b1_0406=6 & b1_0000=1 { tstCnd:1 = ((($(SIGN) ^ $(OVERFLOW)) | $(ZERO)) == 1); export tstCnd; } # Equal to or less than (signed value) (>=)\nb1cnd: \"LT\" is b1_0406=7 & b1_0000=0 { tstCnd:1 = (($(SIGN) ^ $(OVERFLOW)) == 1); export tstCnd; } # less than (signed value) (<=)\n\n#\n# Flag bit operand\n#\nflagBit: \"C\" is b2_0002=0 { export 0:2; }\nflagBit: \"D\" is b2_0002=1 { export 1:2; }\nflagBit: \"Z\" is b2_0002=2 { export 2:2; }\nflagBit: \"S\" is b2_0002=3 { export 3:2; }\nflagBit: \"B\" is b2_0002=4 { export 4:2; }\nflagBit: \"O\" is b2_0002=5 { export 5:2; }\nflagBit: \"I\" is b2_0002=6 { export 6:2; }\nflagBit: \"U\" is b2_0002=7 { export 7:2; }\n\nwith: phase=1 {\n#\n# Instruction Constructors\n#\n##### ABS #####\n# (1) ABS.B dst\n# 1010 0100 1001 1111 0011 0100 0001 0010 ABS.B 0x1234:16[SB]\n# 0000 1001 1010 0100 1001 1111 0011 0100 0001 0010 ABS.B [0x1234:16[SB]] \n:ABS.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x1f) ... & $(DST5B) ... {\n tmp:1 = dst5B;\n $(OVERFLOW) = (tmp == 0x80);\n if (tmp s>= 0) goto ;\n tmp = -tmp;\n dst5B = tmp;\n \n setResultFlags(tmp);\n}\n\n# (1) ABS.B Ax\n:ABS.B dst5Ax is (b1_0407=0xa & b1_size_0=0; b2_0005=0x1f) ... & $(DST5AX) ... {\n tmp:1 = dst5Ax:1;\n $(OVERFLOW) = (tmp == 0x80);\n if (tmp s>= 0) goto ;\n tmp = -tmp;\n dst5Ax = zext(tmp);\n \n setResultFlags(tmp);\n}\n\n# (1) ABS.W dst\n# 1010 0101 1001 1111 0011 0100 0001 0010 ABS.W 0x1234:16[SB]\n# 0000 1001 1010 0101 1001 1111 0011 0100 0001 0010 ABS.W [0x1234:16[SB]] \n:ABS.W dst5W is (b1_0407=0xa & b1_size_0=1; b2_0005=0x1f) ... & $(DST5W) ... {\n tmp:2 = dst5W;\n $(OVERFLOW) = (tmp == 0x8000);\n if (tmp s>= 0) goto ;\n tmp = -tmp;\n dst5W = tmp;\n \n setResultFlags(tmp);\n}\n\n# (1) ABS.W Ax\n:ABS.W dst5Ax is (b1_0407=0xa & b1_size_0=1; b2_0005=0x1f) ... & $(DST5AX) ... {\n tmp:2 = dst5Ax:2;\n $(OVERFLOW) = (tmp == 0x8000);\n if (tmp s>= 0) goto ;\n tmp = -tmp;\n dst5Ax = zext(tmp);\n \n setResultFlags(tmp);\n}\n\n##### ADC #####\n\n# (1) ADC.B #simm, dst\n# 0000 0001 1000 0100 1010 1110 0011 0100 0001 0010 0101 0110 ADC.B 0x56, 0x1234:16[SB]\n# 0000 1001 0000 0001 1000 0100 1010 1110 0011 0100 0001 0010 0101 0110 ABS.B 0x56, [0x1234:16[SB]] \n:ADC.B srcSimm8, dst5B is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B)); srcSimm8 {\n tmp:1 = dst5B;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, srcSimm8, c);\n tmp = tmp + srcSimm8 + c;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADC.B #simm, Ax\n:ADC.B srcSimm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2e) & $(DST5AX)); srcSimm8 {\n tmp:1 = dst5Ax:1;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, srcSimm8, c);\n tmp = tmp + srcSimm8 + c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ADC.W #simm, dst\n:ADC.W srcSimm16, dst5W is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W)); srcSimm16 {\n tmp:2 = dst5W;\n c:2 = zext($(CARRY));\n setAdd3Flags(tmp, srcSimm16, c);\n tmp = tmp + srcSimm16 + c;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADC.B #simm, Ax\n:ADC.W srcSimm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2e) & $(DST5AX)); srcSimm16 {\n tmp:2 = dst5Ax:2;\n c:2 = zext($(CARRY));\n setAdd3Flags(tmp, srcSimm16, c);\n tmp = tmp + srcSimm16 + c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ADC.B src5, dst5\n:ADC.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x4) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n tmp:1 = dst5B_afterSrc5;\n s:1 = src5B;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, s, c);\n tmp = tmp + s + c;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADC.B src5, Ax\n:ADC.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x4) ... & $(SRC5B) & $(DST5AX) ...) {\n tmp:1 = dst5Ax:1;\n s:1 = src5B;\n c:1 = $(CARRY);\n setAdd3Flags(tmp, s, c);\n tmp = tmp + s + c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ADC.W src5, dst5\n:ADC.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x4) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n tmp:2 = dst5W_afterSrc5;\n s:2 = src5W;\n c:2 = zext($(CARRY));\n setAdd3Flags(tmp, s, c);\n tmp = tmp + s + c;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADC.W src5, Ax\n:ADC.W src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x4) ... & $(SRC5W) & $(DST5AX) ...) {\n tmp:2 = dst5Ax:2;\n s:2 = src5W;\n c:2 = zext($(CARRY));\n setAdd3Flags(tmp, s, c);\n tmp = tmp + s + c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### ADCF #####\n\n# (1) ADCF.B dst\n:ADCF.B dst5B is (b1_0407=0xb & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B) {\n tmp:1 = dst5B;\n c:1 = $(CARRY);\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADCF.B Ax\n:ADCF.B dst5Ax is (b1_0407=0xb & b1_size_0=0; b2_0005=0x1e) & $(DST5AX) {\n tmp:1 = dst5Ax:1;\n c:1 = $(CARRY);\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ADCF.W dst\n:ADCF.W dst5W is (b1_0407=0xb & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W) {\n tmp:2 = dst5W;\n c:2 = zext($(CARRY));\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADCF.B Ax\n:ADCF.W dst5Ax is (b1_0407=0xb & b1_size_0=1; b2_0005=0x1e) & $(DST5AX) {\n tmp:2 = dst5Ax:2;\n c:2 = zext($(CARRY));\n setAddFlags(tmp, c);\n tmp = tmp + c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### ADD #####\n\n# (1) ADD.B:G #simm, dst\n:ADD^\".B:G\" srcSimm8, dst5B is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B)); srcSimm8 {\n tmp:1 = dst5B;\n setAddFlags(tmp, srcSimm8);\n tmp = tmp + srcSimm8;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADD.B:G #simm, Ax\n:ADD^\".B:G\" srcSimm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2e) & $(DST5AX)); srcSimm8 {\n tmp:1 = dst5Ax:1;\n setAddFlags(tmp, srcSimm8);\n tmp = tmp + srcSimm8;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ADD.W:G #simm, dst\n:ADD^\".W:G\" srcSimm16, dst5W is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W)); srcSimm16 {\n tmp:2 = dst5W;\n setAddFlags(tmp, srcSimm16);\n tmp = tmp + srcSimm16;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADD.W:G #simm, Ax\n:ADD^\".W:G\" srcSimm16, dst5Ax is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2e) & $(DST5AX)); srcSimm16 {\n tmp:2 = dst5Ax:2;\n setAddFlags(tmp, srcSimm16);\n tmp = tmp + srcSimm16;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ADD.L:G #simm, dst\n:ADD^\".L:G\" srcSimm32, dst5L is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x31) ... & $(DST5L)); srcSimm32 {\n tmp:4 = dst5L;\n setAddFlags(tmp, srcSimm32);\n tmp = tmp + srcSimm32;\n dst5L = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADD.L:G #simm, Ax\n:ADD^\".L:G\" srcSimm32, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x31) & $(DST5AX)); srcSimm32 {\n tmp:4 = zext(dst5Ax);\n setAddFlags(tmp, srcSimm32);\n tmp = tmp + srcSimm32;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (3) ADD.B:G #simm4, dst\n:ADD^\".B:G\" srcSimm4, dst5B is (b1_0507=0x7 & b1_size_4=0 & b1_size_0=0; b2_0405=3 & srcSimm4) ... & $(DST5B) {\n tmp:1 = dst5B;\n setAddFlags(tmp, srcSimm4);\n tmp = tmp + srcSimm4;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (3) ADD.B:G #simm4, Ax\n:ADD^\".B:G\" srcSimm4, dst5Ax is (b1_0507=0x7 & b1_d5=0x0 & b1_size_4=0 & b1_size_0=0; b2_0405=3 & srcSimm4) & $(DST5AX) {\n tmp:1 = dst5Ax:1;\n setAddFlags(tmp, srcSimm4);\n tmp = tmp + srcSimm4;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (3) ADD.W:Q #simm4, dst\n:ADD^\".W:Q\" srcSimm4, dst5W is (b1_0507=0x7 & b1_size_4=0 & b1_size_0=1; b2_0405=3 & srcSimm4) ... & $(DST5W) {\n tmp:2 = dst5W;\n imm:2 = sext(srcSimm4);\n setAddFlags(tmp, imm);\n tmp = tmp + imm;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (3) ADD.W:Q #simm4, Ax\n:ADD^\".W:Q\" srcSimm4, dst5Ax is (b1_0507=0x7 & b1_d5=0x0 & b1_size_4=0 & b1_size_0=1; b2_0405=3 & srcSimm4) & $(DST5AX) {\n tmp:2 = dst5Ax:2;\n imm:2 = sext(srcSimm4);\n setAddFlags(tmp, imm);\n tmp = tmp + imm;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (3) ADD.L:Q #simm4, dst\n:ADD^\".L:Q\" srcSimm4, dst5L is (b1_0507=0x7 & b1_size_4=1 & b1_size_0=0; b2_0405=3 & srcSimm4) ... & $(DST5L) {\n tmp:4 = dst5L;\n imm:4 = sext(srcSimm4);\n setAddFlags(tmp, imm);\n tmp = tmp + imm;\n dst5L = tmp;\n setResultFlags(tmp);\n}\n\n# (3) ADD.L:Q #simm4, Ax\n:ADD^\".L:Q\" srcSimm4, dst5Ax is (b1_0507=0x7 & b1_d5=0x0 & b1_size_4=1 & b1_size_0=0; b2_0405=3 & srcSimm4) & $(DST5AX) {\n tmp:4 = sext(dst5Ax);\n imm:4 = sext(srcSimm4);\n setAddFlags(tmp, imm);\n tmp = tmp + imm;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (4) ADD.B:S #simm, dst\n:ADD^\".B:S\" srcSimm8, dst2B is ((b1_0607=0 & b1_0103=3 & b1_size_0=0) ... & dst2B); srcSimm8 {\n tmp:1 = dst2B;\n setAddFlags(tmp, srcSimm8);\n tmp = tmp + srcSimm8;\n dst2B = tmp;\n setResultFlags(tmp);\n}\n\n# (4) ADD.W:S #simm, dst\n# 0010 0111 0101 0110 0011 0100 0001 0010 ADD.W:S #0x1234, 0x56:8[SB]\n:ADD^\".W:S\" srcSimm16, dst2W is ((b1_0607=0 & b1_0103=3 & b1_size_0=1) ... & dst2W); srcSimm16 {\n tmp:2 = dst2W;\n setAddFlags(tmp, srcSimm16);\n tmp = tmp + srcSimm16;\n dst2W = tmp;\n setResultFlags(tmp);\n}\n\n# (5) ADD.L:S #imm1, Ax\n:ADD^\".L:S\" srcImm1p, b1_d1_regAx is b1_0607=2 & srcImm1p & b1_0104=0x6 & b1_d1_regAx {\n tmp:4 = sext(b1_d1_regAx);\n imm:4 = zext(srcImm1p);\n setAddFlags(tmp, imm);\n tmp = tmp + imm;\n b1_d1_regAx = tmp:3;\n setResultFlags(tmp);\n}\n\n# (6) ADD.B:G src, dst\n# 1011 0110 0001 1000 0101 0110 0011 0100 0001 0010 0011 0011 0010 0010 0001 0001 ADD.B:G 0x123456:24[A0], 112233[A1]\n# 1100 0101 1111 1000 0011 0100 0001 0010 ADD.W:G R1, 0x1234:16[FB]\n:ADD^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x8) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... {\n tmp:1 = dst5B_afterSrc5;\n src:1 = src5B;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (6) ADD.B:G src, Ax - Ax destination case\n:ADD^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x8) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:1 = dst5Ax:1;\n src:1 = src5B;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (6) ADD.W:G src, dst\n:ADD^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x8) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... {\n tmp:2 = dst5W_afterSrc5;\n src:2 = src5W;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (6) ADD.W:G src, Ax - Ax destination case\n:ADD^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x8) ... & $(SRC5W) & $(DST5AX) ... {\n tmp:2 = dst5Ax:2;\n src:2 = src5W;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (7) ADD.L:G src, dst\n:ADD^\".L:G\" src5L, dst5L_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x2) ... & $(SRC5L) ... & $(DST5L_AFTER_SRC5) ... {\n tmp:4 = dst5L_afterSrc5;\n src:4 = src5L;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5L_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (7) ADD.L:G src, Ax - Ax destination case\n:ADD^\".L:G\" src5L, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x2) ... & $(SRC5L) & $(DST5AX) ... {\n tmp:4 = zext(dst5Ax);\n src:4 = src5L;\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (8) ADD.l:G #simm16, SP\n:ADD^\".L:G\" srcSimm16, SP is b1_0007=0xb6 & SP; b2_0007=0x13; srcSimm16 {\n # not done as 32-bit calculation to simplify stack analysis\n imm:3 = sext(srcSimm16);\n setAddFlags(SP, imm);\n SP = SP + imm;\n setResultFlags(SP);\n}\n\n# (9) ADD.L:Q #imm3, SP\n:ADD^\".L:Q\" srcImm3p, SP is b1_0607=1 & srcImm3p & b1_0103=1 & SP {\n # not done as 32-bit calculation to simplify stack analysis\n imm:3 = zext(srcImm3p);\n setAddFlags(SP, imm);\n SP = SP + imm;\n setResultFlags(SP);\n}\n\n# (10) ADD.L:S #simm8, SP\n:ADD^\".L:S\" srcSimm8, SP is b1_0007=0xb6 & SP; b2_0007=0x03; srcSimm8 {\n # not done as 32-bit calculation to simplify stack analysis\n imm:3 = sext(srcSimm8);\n setAddFlags(SP, imm);\n SP = SP + imm;\n setResultFlags(SP);\n}\n\n##### ADDX #####\n\n# (1) ADDX #simm, dst5\n:ADDX srcSimm8, dst5L is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x11) ... & $(DST5L)); srcSimm8 {\n tmp:4 = dst5L;\n src:4 = sext(srcSimm8);\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5L = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ADDX #simm, Ax\n:ADDX srcSimm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x11) & $(DST5AX)); srcSimm8 {\n tmp:4 = zext(dst5Ax);\n src:4 = sext(srcSimm8);\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (2) ADDX src5, dst5\n:ADDX src5B, dst5L_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x2) ... & $(SRC5B) ... & $(DST5L_AFTER_SRC5) ... {\n tmp:4 = dst5L_afterSrc5;\n src:4 = sext(src5B);\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5L_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ADDX src5, Ax\n:ADDX src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x2) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:4 = zext(dst5Ax);\n src:4 = sext(src5B);\n setAddFlags(tmp, src);\n tmp = tmp + src;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n##### ADJNZ #####\n\n# ADJNZ.B #simm4, dst, rel8offset2\n# 1111 1000 1001 1111 0000 0110 ADJNZ #-0x1,R0L,\n:ADJNZ.B srcSimm4, dst5B, rel8offset2 is ((b1_0407=0xf & b1_size_0=0; b2_0405=1 & srcSimm4) ... & $(DST5B)); rel8offset2 {\n tmp:1 = dst5B + srcSimm4;\n dst5B = tmp;\n if (tmp != 0) goto rel8offset2;\n}\n\n# ADJNZ.B #simm4, Ax, , rel8offset2\n:ADJNZ.B srcSimm4, dst5Ax, rel8offset2 is ((b1_0407=0xf & b1_size_0=0; b2_0405=1 & srcSimm4) & $(DST5AX)); rel8offset2 {\n tmp:1 = dst5Ax:1 + srcSimm4;\n dst5Ax = zext(tmp);\n if (tmp != 0) goto rel8offset2;\n}\n\n# ADJNZ.W #simm4, dst, rel8offset2\n:ADJNZ.W srcSimm4, dst5W, rel8offset2 is ((b1_0407=0xf & b1_size_0=1; b2_0405=1 & srcSimm4) ... & $(DST5W)); rel8offset2 {\n tmp:2 = dst5W + sext(srcSimm4);\n dst5W = tmp;\n if (tmp != 0) goto rel8offset2;\n}\n\n# ADJNZ.W #simm4, Ax, rel8offset2\n:ADJNZ.W srcSimm4, dst5Ax, rel8offset2 is ((b1_0407=0xf & b1_size_0=1; b2_0405=1 & srcSimm4) & $(DST5AX)); rel8offset2 {\n tmp:2 = dst5Ax:2 + sext(srcSimm4);\n dst5Ax = zext(tmp);\n if (tmp != 0) goto rel8offset2;\n}\n\n##### AND #####\n\n# (1) AND.B:G #imm, dst\n:AND^\".B:G\" srcImm8, dst5B is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3f) ... & $(DST5B)); srcImm8 {\n tmp:1 = dst5B & srcImm8;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) AND.B:G #imm, Ax\n:AND^\".B:G\" srcImm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3f) & $(DST5AX)); srcImm8 {\n tmp:1 = dst5Ax:1 & srcImm8;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) AND.W:G #imm, dst\n:AND^\".W:G\" srcImm16, dst5W is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3f) ... & $(DST5W)); srcImm16 {\n tmp:2 = dst5W & srcImm16;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) AND.W:G #imm, Ax\n:AND^\".W:G\" srcImm16, dst5Ax is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3f) & $(DST5AX)); srcImm16 {\n tmp:2 = dst5Ax:2 & srcImm16;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) AND.B:S #imm, dst\n:AND^\".B:S\" srcImm8, dst2B is ((b1_0607=1 & b1_0103=6 & b1_size_0=0) ... & dst2B); srcImm8 {\n tmp:1 = dst2B & srcImm8;\n dst2B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) AND.W:S #imm, dst\n:AND^\".W:S\" srcImm16, dst2W is ((b1_0607=1 & b1_0103=6 & b1_size_0=1) ... & dst2W); srcImm16 {\n tmp:2 = dst2W & srcImm16;\n dst2W = tmp;\n setResultFlags(tmp);\n}\n\n# (3) AND.B:G src5, dst5\n:AND^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0xd) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... {\n tmp:1 = dst5B_afterSrc5 & src5B;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n} \n\n# (3) AND.B:G src5, Ax\n:AND^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0xd) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:1 = dst5Ax:1 & src5B;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n} \n\n# (3) AND.W:G src5, dst5\n:AND^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0xd) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... {\n tmp:2 = dst5W_afterSrc5 & src5W;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n} \n\n# (3) AND.W:G src5, Ax\n:AND^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0xd) ... & $(SRC5W) & $(DST5AX) ... {\n tmp:2 = dst5Ax:2 & src5W;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n} \n\n##### BAND #####\n\n# BAND bit,bitbase\n# 0000 0001 1101 0110 0000 1011 0101 0110 0011 0100 0001 0010 BAND 0x3,0x123456[A0]\n:BAND bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x1 & bit) ... & $(BITBASE)) {\n bitValue:1 = (bitbase >> bit) & 1;\n $(CARRY) = $(CARRY) & bitValue;\n}\n\n##### BCLR #####\n\n# BCLR bit,bitbase\n# 1101 0110 0011 0011 0101 0110 0011 0100 0001 0010 BCLR 0x3,0x123456[A0]\n:BCLR bit, bitbase is (b1_0407=0xd & b1_size_0=0; b2_0305=0x6 & bit) ... & $(BITBASE) {\n mask:1 = ~(1 << bit);\n bitbase = bitbase & mask;\n}\n\n# BCLR bit,Ax\n:BCLR b2_bit, bitbaseAx is (b1_0407=0xd & b1_size_0=0; b2_0305=0x6 & b2_bit) & $(BITBASE_AX) {\n mask:3 = ~(1 << b2_bit);\n bitbaseAx = bitbaseAx & mask;\n}\n\n##### BITINDEX #####\n\n# BITINDEX.B src -- dst5B used as source\n# 1100 1000 1010 1110 BINDEX.B R0L\n:BITINDEX.B dst5B is (b1_0407=0xc & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B) \n [ useBitIndex=1; globalset(inst_next,useBitIndex); useBitIndex=0; ] {\n bitIndex = zext(dst5B);\n}\n\n# BITINDEX.W src -- dst5W used as source\n:BITINDEX.W dst5W is (b1_0407=0xc & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W) \n [ useBitIndex=1; globalset(inst_next,useBitIndex); useBitIndex=0; ] {\n bitIndex = zext(dst5W);\n}\n\n##### BMCnd #####\n\n# (1) BMcnd bit, bitbase\n:BM^cnd bit, bitbase is ((b1_0407=0xd & b1_size_0=0; b2_0305=0x2 & bit) ... & $(BITBASE)); cnd {\n mask:1 = ~(1 << bit);\n bitbase = ((cnd << bit) | (bitbase & mask));\n}\n\n# (1) BMcnd bit, Ax\n:BM^cnd b2_bit, bitbaseAx is ((b1_0407=0xd & b1_size_0=0; b2_0305=0x2 & b2_bit) & $(BITBASE_AX)); cnd {\n mask:3 = ~(1 << b2_bit);\n bitbaseAx = ((zext(cnd) << b2_bit) | (bitbaseAx & mask));\n}\n\n# (2) BMcnd C\n:BM^b2cnd \"C\" is b1_0007=0xd9; b2_0707=0 & b2_0305=5 & b2cnd {\n $(CARRY) = b2cnd;\n}\n\n##### BNAND #####\n\n:BNAND bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x3 & bit) ... & $(BITBASE)) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n $(CARRY) = $(CARRY) && (bitValue == 0);\n}\n\n:BNAND b2_bit, bitbaseAx is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x3 & b2_bit) & $(BITBASE_AX)) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n $(CARRY) = $(CARRY) && (bitValue == 0);\n}\n\n##### BNOR #####\n\n:BNOR bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x6 & bit) ... & $(BITBASE)) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n $(CARRY) = $(CARRY) || (bitValue == 0);\n}\n\n:BNOR b2_bit, bitbaseAx is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x6 & b2_bit) & $(BITBASE_AX)) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n $(CARRY) = $(CARRY) || (bitValue == 0);\n}\n\n##### BNOT #####\n\n# BNOT bit,bitbase\n:BNOT bit, bitbase is (b1_0407=0xd & b1_size_0=0; b2_0305=0x3 & bit) ... & $(BITBASE) {\n mask:1 = (1 << bit);\n val:1 = bitbase;\n bitValue:1 = (~val & mask);\n bitbase = (val & ~mask) | bitValue;\n}\n\n# BNOT bit,Ax\n:BNOT b2_bit, bitbaseAx is (b1_0407=0xd & b1_size_0=0; b2_0305=0x3 & b2_bit) & $(BITBASE_AX) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (~bitbaseAx & mask);\n bitbaseAx = (bitbaseAx & ~mask) | bitValue;\n}\n\n##### BNTST #####\n\n:BNTST bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x0 & bit) ... & $(BITBASE)) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = z;\n $(ZERO) = z;\n}\n\n:BNTST b2_bit, bitbaseAx is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x0 & b2_bit) & $(BITBASE_AX)) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = z;\n $(ZERO) = z;\n}\n\n##### BNXOR #####\n\n:BNXOR bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x7 & bit) ... & $(BITBASE)) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n $(CARRY) = $(CARRY) ^ (bitValue == 0);\n}\n\n:BNXOR b2_bit, bitbaseAx is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x7 & b2_bit) & $(BITBASE_AX)) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n $(CARRY) = $(CARRY) ^ (bitValue == 0);\n}\n\n##### BOR #####\n\n:BOR bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x4 & bit) ... & $(BITBASE)) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n $(CARRY) = $(CARRY) || (bitValue != 0);\n}\n\n:BOR b2_bit, bitbaseAx is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x4 & b2_bit) & $(BITBASE_AX)) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n $(CARRY) = $(CARRY) || (bitValue != 0);\n}\n\n##### BRK #####\n\n:BRK is b1_0007=0x0 {\n # I don't think it is necessary to model break behavior\n Break();\n}\n\n##### BRK2 #####\n\n:BRK2 is b1_0007=0x8 {\n # I don't think it is necessary to model break behavior\n Break2();\n}\n\n##### BSET #####\n\n:BSET bit, bitbase is (b1_0407=0xd & b1_size_0=0; b2_0305=0x7 & bit) ... & $(BITBASE) {\n mask:1 = (1 << bit);\n bitbase = bitbase | mask;\n}\n\n:BSET b2_bit, bitbaseAx is (b1_0407=0xd & b1_size_0=0; b2_0305=0x7 & b2_bit) & $(BITBASE_AX) {\n mask:3 = (1 << b2_bit);\n bitbaseAx = bitbaseAx | mask;\n}\n\n##### BTST #####\n\n# (1) BTST bit, bitbase\n:BTST bit, bitbase is (b1_0407=0xd & b1_size_0=0; b2_0305=0x0 & bit) ... & $(BITBASE) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n# (1) BTST bit, Ax\n:BTST b2_bit, bitbaseAx is (b1_0407=0xd & b1_size_0=0; b2_0305=0x0 & b2_bit) & $(BITBASE_AX) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n# (2) BTST bit, bitbase\n:BTST b, bitbaseAbs16 is b1_0607=0 & b1_0405 & b1_0103=5 & b1_0000; bitbaseAbs16 [ b = (b1_0405 << 1) + b1_0000; ] {\n mask:1 = (1 << b);\n bitValue:1 = (bitbaseAbs16 & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n}\n\n##### BTSTC #####\n\n# (1) BTSTC bit, bitbase\n:BTSTC bit, bitbase is (b1_0407=0xd & b1_size_0=0; b2_0305=0x4 & bit) ... & $(BITBASE) {\n mask:1 = (1 << bit);\n val:1 = bitbase;\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n bitbase = val & ~mask;\n}\n\n# (1) BTSTC bit, Ax\n:BTSTC b2_bit, bitbaseAx is (b1_0407=0xd & b1_size_0=0; b2_0305=0x4 & b2_bit) & $(BITBASE_AX) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n bitbaseAx = bitbaseAx & ~mask;\n}\n\n##### BTSTS #####\n\n# (1) BTSTS bit, bitbase\n:BTSTS bit, bitbase is (b1_0407=0xd & b1_size_0=0; b2_0305=0x5 & bit) ... & $(BITBASE) {\n mask:1 = (1 << bit);\n val:1 = bitbase;\n bitValue:1 = (val & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n bitbase = val | mask;\n}\n\n# (1) BTSTS bit, Ax\n:BTSTS b2_bit, bitbaseAx is (b1_0407=0xd & b1_size_0=0; b2_0305=0x5 & b2_bit) & $(BITBASE_AX) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n z:1 = (bitValue == 0);\n $(CARRY) = !z;\n $(ZERO) = z;\n bitbaseAx = bitbaseAx | mask;\n}\n\n##### BXOR #####\n\n:BXOR bit, bitbase is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x5 & bit) ... & $(BITBASE)) {\n mask:1 = (1 << bit);\n bitValue:1 = (bitbase & mask);\n $(CARRY) = $(CARRY) ^ (bitValue != 0);\n}\n\n:BXOR b2_bit, bitbaseAx is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=0; b2_0305=0x5 & b2_bit) & $(BITBASE_AX)) {\n mask:3 = (1 << b2_bit);\n bitValue:3 = (bitbaseAx & mask);\n $(CARRY) = $(CARRY) ^ (bitValue != 0);\n}\n\n##### CLIP #####\n\n# CLIP.B #simm, #simm, dst5\n:CLIP.B srcSimm8, srcSimm8a, dst5B is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B)); srcSimm8; srcSimm8a {\n val:1 = dst5B;\n cmp1:1 = srcSimm8 s> val;\n cmp2:1 = srcSimm8a s< val;\n dst5B = (cmp1 * srcSimm8) + (cmp2 * srcSimm8a) + ((!cmp1 * !cmp2) * val);\n}\n\n# CLIP.B #simm, #simm, Ax\n:CLIP.B srcSimm8, srcSimm8a, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3e) & $(DST5AX)); srcSimm8; srcSimm8a {\n val:1 = dst5Ax:1;\n cmp1:1 = srcSimm8 s> val;\n cmp2:1 = srcSimm8a s< val;\n dst5Ax = zext((cmp1 * srcSimm8) + (cmp2 * srcSimm8a) + ((!cmp1 * !cmp2) * val));\n}\n\n# CLIP.W #simm, #simm, dst5\n:CLIP.W srcSimm16, srcSimm16a, dst5W is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3e) ... & $(DST5W)); srcSimm16; srcSimm16a {\n val:2 = dst5W;\n cmp1:1 = srcSimm16 s> val;\n cmp2:1 = srcSimm16a s< val;\n dst5W = (zext(cmp1) * srcSimm16) + (zext(cmp2) * srcSimm16a) + (zext(!cmp1 * !cmp2) * val);\n}\n\n# CLIP.W #simm, #simm, Ax\n:CLIP.W srcSimm16, srcSimm16a, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3e) & $(DST5AX)); srcSimm16; srcSimm16a {\n val:2 = dst5Ax:2;\n cmp1:1 = srcSimm16 s> val;\n cmp2:1 = srcSimm16a s< val;\n dst5Ax = zext((zext(cmp1) * srcSimm16) + (zext(cmp2) * srcSimm16a) + (zext(!cmp1 * !cmp2) * val));\n}\n\n##### CMP #####\n\n# (1) CMP.B:G #simm, dst5\n:CMP^\".B:G\" srcSimm8, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B)); srcSimm8 {\n tmp:1 = dst5B;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n setResultFlags(tmp);\n}\n\n# (1) CMP.B:G #simm, Ax\n:CMP^\".B:G\" srcSimm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x2e) & $(DST5AX)); srcSimm8 {\n tmp:1 = dst5Ax:1;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n setResultFlags(tmp);\n}\n\n# (1) CMP.W:G #simm, dst5\n:CMP^\".W:G\" srcSimm16, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W)); srcSimm16 {\n tmp:2 = dst5W;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n setResultFlags(tmp);\n}\n\n# (1) CMP.W:G #simm, Ax\n:CMP^\".W:G\" srcSimm16, dst5Ax is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x2e) & $(DST5AX)); srcSimm16 {\n tmp:2 = dst5Ax:2;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n setResultFlags(tmp);\n}\n\n# (2) CMP.L:G #simm, dst5\n:CMP^\".L:G\" srcSimm32, dst5L is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x31) ... & $(DST5L)); srcSimm32 {\n tmp:4 = dst5L;\n setSubtractFlags(tmp, srcSimm32);\n tmp = tmp - srcSimm32;\n setResultFlags(tmp);\n}\n\n# (2) CMP.L:G #simm, Ax\n:CMP^\".L:G\" srcSimm32, dst5Ax is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x31) & $(DST5AX)); srcSimm32 {\n tmp:4 = zext(dst5Ax);\n setSubtractFlags(tmp, srcSimm32);\n tmp = tmp - srcSimm32;\n setResultFlags(tmp);\n}\n\n# (3) CMP.B:Q #simm4, dst5\n:CMP^\".B:Q\" srcSimm4, dst5B is (b1_0407=0xe & b1_size_0=0; b2_0405=1 & srcSimm4) ... & $(DST5B) {\n tmp:1 = dst5B;\n setSubtractFlags(tmp, srcSimm4);\n tmp = tmp - srcSimm4;\n setResultFlags(tmp);\n}\n\n# (3) CMP.B:Q #simm4, Ax\n:CMP^\".B:Q\" srcSimm4, dst5Ax is (b1_0407=0xe & b1_size_0=0; b2_0405=1 & srcSimm4) & $(DST5AX) {\n tmp:1 = dst5Ax:1;\n setSubtractFlags(tmp, srcSimm4);\n tmp = tmp - srcSimm4;\n setResultFlags(tmp);\n}\n\n# (3) CMP.W:Q #simm4, dst5\n:CMP^\".W:Q\" srcSimm4, dst5W is (b1_0407=0xe & b1_size_0=1; b2_0405=1 & srcSimm4) ... & $(DST5W) {\n tmp:2 = dst5W;\n imm:2 = sext(srcSimm4);\n setSubtractFlags(tmp, imm);\n tmp = tmp - imm;\n setResultFlags(tmp);\n}\n\n# (3) CMP.W:Q #simm4, Ax\n:CMP^\".W:Q\" srcSimm4, dst5Ax is (b1_0407=0xe & b1_size_0=1; b2_0405=1 & srcSimm4) & $(DST5AX) {\n tmp:2 = dst5Ax:2;\n imm:2 = sext(srcSimm4);\n setSubtractFlags(tmp, imm);\n tmp = tmp - imm;\n setResultFlags(tmp);\n}\n\n# (4) CMP.B:S #simm, dst2\n:CMP^\".B:S\" srcSimm8, dst2B is ((b1_0607=1 & b1_0103=3 & b1_size_0=0) ... & dst2B); srcSimm8 {\n tmp:1 = dst2B;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n setResultFlags(tmp);\n}\n\n# (4) CMP.W:S #simm, dst2\n:CMP^\".W:S\" srcSimm16, dst2W is ((b1_0607=1 & b1_0103=3 & b1_size_0=1) ... & dst2W); srcSimm16 {\n tmp:2 = dst2W;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n setResultFlags(tmp);\n}\n\n# (5) CMP.B:G src5, dst5\n:CMP^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x6) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) {\n tmp:1 = dst5B_afterSrc5;\n src:1 = src5B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (5) CMP.B:G src5, Ax\n:CMP^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x6) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:1 = dst5Ax:1;\n src:1 = src5B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (5) CMP.W:G src5, dst5\n:CMP^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x6) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) {\n tmp:2 = dst5W_afterSrc5;\n src:2 = src5W;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (5) CMP.W:G src5, Ax\n:CMP^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x6) ... & $(SRC5W) & $(DST5AX) ... {\n tmp:2 = dst5Ax:2;\n src:2 = src5W;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (6) CMP.L:G src5, dst5\n:CMP^\".L:G\" src5L, dst5L_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=1) ... & $(SRC5L) ... & $(DST5L_AFTER_SRC5) ... {\n tmp:4 = dst5L_afterSrc5;\n src:4 = src5L;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (6) CMP.L:G src5, Ax\n:CMP^\".L:G\" src5L, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=1) ... & $(SRC5L) & $(DST5AX) ... {\n tmp:4 = zext(dst5Ax);\n src:4 = src5L;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n setResultFlags(tmp);\n}\n\n# (7) CMP.B:S src2, R0L\n:CMP^\".B:S\" dst2B, R0L is (b1_0607=1 & b1_0103=0 & b1_size_0=0 & R0L) ... & dst2B {\n tmp:1 = dst2B;\n setSubtractFlags(R0L, tmp);\n tmp = tmp - R0L;\n setResultFlags(tmp);\n}\n\n# (7) CMP.W:S src2, R0\n:CMP^\".W:S\" dst2W, R0 is (b1_0607=1 & b1_0103=0 & b1_size_0=1 & R0) ... & dst2W {\n tmp:2 = dst2W;\n setSubtractFlags(R0, tmp);\n tmp = tmp - R0;\n setResultFlags(tmp);\n}\n\n##### CMPX #####\n\n# CMPX #simm, dst5\n:CMPX srcSimm8, dst5L is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x11) ... & $(DST5L)); srcSimm8 {\n tmp:4 = dst5L;\n imm:4 = sext(srcSimm8);\n setSubtractFlags(tmp, imm);\n tmp = tmp - imm;\n setResultFlags(tmp);\n}\n\n# CMPX #simm, Ax\n:CMPX srcSimm8, dst5Ax is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x11) & $(DST5AX)); srcSimm8 {\n tmp:4 = zext(dst5Ax);\n imm:4 = sext(srcSimm8);\n setSubtractFlags(tmp, imm);\n tmp = tmp - imm;\n setResultFlags(tmp);\n}\n\n##### DADC #####\n\n# (1) DADC.B #imm, dst5\n:DADC.B srcImm8, dst5B is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5B);\n tmp:2 = DecimalAddWithCarry(src, dst);\n dst5B = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (1) DADC.B #imm, Ax\n:DADC.B srcImm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x0e) & $(DST5AX)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5Ax:1);\n tmp:2 = DecimalAddWithCarry(src, dst);\n dst5Ax = zext(tmp:1);\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (1) DADC.W #imm, dst5\n:DADC.W srcImm16, dst5W is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5W);\n tmp:4 = DecimalAddWithCarry(src, dst);\n dst5W = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (1) DADC.W #imm, Ax\n:DADC.W srcImm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x0e) & $(DST5AX)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5Ax:2);\n tmp:4 = DecimalAddWithCarry(src, dst);\n dst5Ax = zext(tmp:2);\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (2) DADC.B src5, dst5\n:DADC.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x8) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5B_afterSrc5);\n tmp:2 = DecimalAddWithCarry(src, dst);\n dst5B_afterSrc5 = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (2) DADC.B src5, Ax\n:DADC.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x8) ... & $(SRC5B) & $(DST5AX) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5Ax:1);\n tmp:2 = DecimalAddWithCarry(src, dst);\n dst5Ax = zext(tmp:1);\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (2) DADC.W src5, dst5\n:DADC.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x8) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5W_afterSrc5);\n tmp:4 = DecimalAddWithCarry(src, dst);\n dst5W_afterSrc5 = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (2) DADC.W src5, Ax\n:DADC.W src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x8) ... & $(SRC5W) & $(DST5AX) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5Ax:2);\n tmp:4 = DecimalAddWithCarry(src, dst);\n dst5Ax = zext(tmp:2);\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n##### DADD #####\n\n# (1) DADD.B #imm, dst5\n:DADD.B srcImm8, dst5B is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5B);\n tmp:2 = DecimalAdd(src, dst);\n dst5B = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (1) DADD.B #imm, Ax\n:DADD.B srcImm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x1e) & $(DST5AX)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5Ax:1);\n tmp:2 = DecimalAdd(src, dst);\n dst5Ax = zext(tmp:1);\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (1) DADD.W #imm, dst5\n:DADD.W srcImm16, dst5W is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5W);\n tmp:4 = DecimalAdd(src, dst);\n dst5W = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (1) DADD.W #imm, Ax\n:DADD.W srcImm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x1e) & $(DST5AX)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5Ax:2);\n tmp:4 = DecimalAdd(src, dst);\n dst5Ax = zext(tmp:2);\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (2) DADD.B src5, dst5\n:DADD.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x0) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5B_afterSrc5);\n tmp:2 = DecimalAdd(src, dst);\n dst5B_afterSrc5 = tmp:1;\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (2) DADD.B src5, Ax\n:DADD.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x0) ... & $(SRC5B) & $(DST5AX) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5Ax:1);\n tmp:2 = DecimalAdd(src, dst);\n dst5Ax = zext(tmp:1);\n $(CARRY) = (tmp > 0x99);\n setResultFlags(tmp:1);\n}\n\n# (2) DADD.W src5, dst5\n:DADD.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x0) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5W_afterSrc5);\n tmp:4 = DecimalAdd(src, dst);\n dst5W_afterSrc5 = tmp:2;\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n# (2) DADD.W src5, Ax\n:DADD.W src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x0) ... & $(SRC5W) & $(DST5AX) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5Ax:2);\n tmp:4 = DecimalAdd(src, dst);\n dst5Ax = zext(tmp:2);\n $(CARRY) = (tmp > 0x9999);\n setResultFlags(tmp:2);\n}\n\n##### DEC #####\n\n# DEC.B dst5\n:DEC.B dst5B is (b1_0407=0xb & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B) {\n tmp:1 = dst5B - 1;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# DEC.B Ax\n:DEC.B dst5Ax is (b1_0407=0xb & b1_size_0=0; b2_0005=0x0e) & $(DST5AX) {\n tmp:1 = dst5Ax:1 - 1;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# DEC.W dst5\n:DEC.W dst5W is (b1_0407=0xb & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W) {\n tmp:2 = dst5W - 1;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# DEC.W Ax\n:DEC.W dst5Ax is (b1_0407=0xb & b1_size_0=1; b2_0005=0x0e) & $(DST5AX) {\n tmp:2 = dst5Ax:2 - 1;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### DIV #####\n\n# (1) DIV.B #imm\n:DIV.B srcSimm8 is b1_0007=0xb0; b2_0007=0x43; srcSimm8 {\n d:2 = sext(srcSimm8);\n q:2 = R0 s/ d;\n r:2 = R0 s% d; # remainder has same sign as R0 (dividend)\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (1) DIV.W #imm\n:DIV.W srcSimm16 is b1_0007=0xb0; b2_0007=0x53; srcSimm16 {\n d:4 = sext(srcSimm16);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d; # remainder has same sign as R0 (dividend)\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIV.B src5\n:DIV.B dst5B is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B) {\n d:2 = sext(dst5B);\n q:2 = R0 s/ d;\n r:2 = R0 s% d; # remainder has same sign as R0 (dividend)\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIV.W src5\n:DIV.W dst5W is (b1_0407=0x8 & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W) {\n d:4 = sext(dst5W);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d; # remainder has same sign as R0 (dividend)\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n##### DIVU #####\n\n# (1) DIVU.B #imm\n:DIVU.B srcImm8 is b1_0007=0xb0; b2_0007=0x03; srcImm8 {\n d:2 = zext(srcImm8);\n q:2 = R0 / d;\n r:2 = R0 % d;\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (1) DIVU.W #imm\n:DIVU.W srcImm16 is b1_0007=0xb0; b2_0007=0x13; srcImm16 {\n d:4 = zext(srcImm16);\n q:4 = R2R0 / d;\n r:4 = R2R0 % d;\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVU.B src5\n:DIVU.B dst5B is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B) {\n d:2 = zext(dst5B);\n q:2 = R0 / d;\n r:2 = R0 % d;\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVU.W src5\n:DIVU.W dst5W is (b1_0407=0x8 & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W) {\n d:4 = zext(dst5W);\n q:4 = R2R0 / d;\n r:4 = R2R0 % d;\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n##### DIVX #####\n\n# (1) DIVX.B #imm\n:DIVX.B srcSimm8 is b1_0007=0xb2; b2_0007=0x43; srcSimm8 {\n d:2 = sext(srcSimm8);\n q:2 = R0 s/ d;\n r:2 = R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (1) DIVX.W #imm\n:DIVX.W srcSimm16 is b1_0007=0xb2; b2_0007=0x53; srcSimm16 {\n d:4 = sext(srcSimm16);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVX.B src5\n:DIVX.B dst5B is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B) {\n d:2 = sext(dst5B);\n q:2 = R0 s/ d;\n r:2 = R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n differ:1 = (r s< 0) != (d s< 0);\n r = (zext(differ) * (-r)) + (zext(!differ) * r);\n R0L = q:1;\n R0H = r:1;\n q = q s>> 8;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n# (2) DIVX.W src5\n:DIVX.W dst5W is (b1_0407=0x9 & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W) {\n d:4 = sext(dst5W);\n q:4 = R2R0 s/ d;\n r:4 = R2R0 s% d;\n\n #according to the manual the remainder has the same sign as the quotient\n R0 = q:2;\n R2 = r:2;\n q = q s>> 16;\n $(OVERFLOW) = (d == 0) || ((q != 0) && (q != -1));\n}\n\n##### DSBB #####\n\n# (1) DSBB.B #imm, dst5\n:DSBB.B srcImm8, dst5B is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5B);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:2 = DecimalSubtractWithBorrow(dst, src);\n dst5B = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (1) DSBB.B #imm, Ax\n:DSBB.B srcImm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x0e) & $(DST5AX)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5Ax:1);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:2 = DecimalSubtractWithBorrow(dst, src);\n dst5Ax = zext(tmp:1);\n setResultFlags(tmp:1);\n}\n\n# (1) DSBB.W #imm, dst5\n:DSBB.W srcImm16, dst5W is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5W);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:4 = DecimalSubtractWithBorrow(dst, src);\n dst5W = tmp:2;\n setResultFlags(tmp:2);\n}\n\n# (1) DSBB.W #imm, Ax\n:DSBB.W srcImm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x0e) & $(DST5AX)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5Ax:2);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:4 = DecimalSubtractWithBorrow(dst, src);\n dst5Ax = zext(tmp:2);\n setResultFlags(tmp:2);\n}\n\n# (2) DSBB.B src5, dst5\n:DSBB.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xa) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5B_afterSrc5);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:2 = DecimalSubtractWithBorrow(dst, src);\n dst5B_afterSrc5 = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (2) DSBB.B src5, Ax\n:DSBB.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xa) ... & $(SRC5B) & $(DST5AX) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5Ax:1);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:2 = DecimalSubtractWithBorrow(dst, src);\n dst5Ax = zext(tmp:1);\n setResultFlags(tmp:1);\n}\n\n# (2) DSBB.W src5, dst5\n:DSBB.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0xa) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5W_afterSrc5);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:4 = DecimalSubtractWithBorrow(dst, src);\n dst5W_afterSrc5 = tmp:2;\n setResultFlags(tmp:2);\n}\n\n# (2) DSBB.W src5, Ax\n:DSBB.W src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0xa) ... & $(SRC5W) & $(DST5AX) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5Ax:2);\n c:1 = $(CARRY);\n $(CARRY) = (c && (dst > src)) || (!c && (dst >= src));\n tmp:4 = DecimalSubtractWithBorrow(dst, src);\n dst5Ax = zext(tmp:2);\n setResultFlags(tmp:2);\n}\n\n##### DSUB #####\n\n# (1) DSUB.B #imm, dst5\n:DSUB.B srcImm8, dst5B is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5B);\n $(CARRY) = (dst >= src);\n tmp:2 = DecimalSubtract(dst, src);\n dst5B = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (1) DSUB.B #imm, Ax\n:DSUB.B srcImm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x1e) & $(DST5AX)); srcImm8 {\n src:2 = zext(srcImm8);\n dst:2 = zext(dst5Ax:1);\n $(CARRY) = (dst >= src);\n tmp:2 = DecimalSubtract(dst, src);\n dst5Ax = zext(tmp:1);\n setResultFlags(tmp:1);\n}\n\n# (1) DSUB.W #imm, dst5\n:DSUB.W srcImm16, dst5W is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5W);\n $(CARRY) = (dst >= src);\n tmp:4 = DecimalSubtract(dst, src);\n dst5W = tmp:2;\n setResultFlags(tmp:2);\n}\n\n# (1) DSUB.W #imm, Ax\n:DSUB.W srcImm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x1e) & $(DST5AX)); srcImm16 {\n src:4 = zext(srcImm16);\n dst:4 = zext(dst5Ax:2);\n $(CARRY) = (dst >= src);\n tmp:4 = DecimalSubtract(dst, src);\n dst5Ax = zext(tmp:2);\n setResultFlags(tmp:2);\n}\n\n# (2) DSUB.B src5, dst5\n:DSUB.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x2) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5B_afterSrc5);\n $(CARRY) = (dst >= src);\n tmp:2 = DecimalSubtract(dst, src);\n dst5B_afterSrc5 = tmp:1;\n setResultFlags(tmp:1);\n}\n\n# (2) DSUB.B src5, Ax\n:DSUB.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x2) ... & $(SRC5B) & $(DST5AX) ...) {\n src:2 = zext(src5B);\n dst:2 = zext(dst5Ax:1);\n $(CARRY) = (dst >= src);\n tmp:2 = DecimalSubtract(dst, src);\n dst5Ax = zext(tmp:1);\n setResultFlags(tmp:1);\n}\n\n# (2) DSUB.W src5, dst5\n:DSUB.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x2) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5W_afterSrc5);\n $(CARRY) = (dst >= src);\n tmp:4 = DecimalSubtract(dst, src);\n dst5W_afterSrc5 = tmp:2;\n setResultFlags(tmp:2);\n}\n\n# (2) DSUB.W src5, Ax\n:DSUB.W src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x2) ... & $(SRC5W) & $(DST5AX) ...) {\n src:4 = zext(src5W);\n dst:4 = zext(dst5Ax:2);\n $(CARRY) = (dst >= src);\n tmp:4 = DecimalSubtract(dst, src);\n dst5Ax = zext(tmp:2);\n setResultFlags(tmp:2);\n}\n\n##### ENTER #####\n\n:ENTER srcImm8 is b1_0007=0xec; srcImm8 {\n push3(FB);\n FB = SP;\n SP = SP - zext(srcImm8);\n}\n\n##### EXITD #####\n\n:EXITD is b1_0007=0xfc {\n SP = FB;\n pop3(FB);\n pc:3 = 0;\n pop3(pc);\n return [pc];\n}\n\n##### EXTS #####\n\n# (1) EXTS.B dst5\n:EXTS.B dst5B is (b1_0407=0xc & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B) & $(DST5W) {\n tmp:2 = sext(dst5B);\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) EXTS.B Ax\n:EXTS.B dst5Ax is (b1_0407=0xc & b1_size_0=0; b2_0005=0x1e) & $(DST5AX) {\n tmp:2 = sext(dst5Ax:1);\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) EXTS.W dst5\n:EXTS.W dst5W is (b1_0407=0xc & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W) & $(DST5L) {\n tmp:4 = sext(dst5W);\n dst5L = tmp;\n setResultFlags(tmp);\n}\n\n# (1) EXTS.W Ax\n:EXTS.W dst5Ax is (b1_0407=0xc & b1_size_0=1; b2_0005=0x1e) & $(DST5AX) {\n tmp:4 = sext(dst5Ax:2);\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (2) EXTS.B src5, dst5\n:EXTS.B src5B, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x7) ... & $(SRC5B) ... & $(DST5W_AFTER_SRC5) ...) {\n tmp:2 = sext(src5B);\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) EXTS.B src5, Ax\n:EXTS.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x7) ... & $(SRC5B) & $(DST5AX) ...) {\n tmp:2 = sext(src5B);\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### EXTZ #####\n\n# (1) EXTZ.B src5, dst5\n:EXTZ.B src5B, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xb) ... & $(SRC5B) ... & $(DST5W_AFTER_SRC5) ...) {\n tmp:2 = zext(src5B);\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (1) EXTZ.B src5, Ax\n:EXTZ.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xb) ... & $(SRC5B) & $(DST5AX) ...) {\n tmp:2 = zext(src5B);\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### FCLR #####\n\n:FCLR flagBit is b1_0007=0xd3; b2_0307=0x1d & flagBit {\n mask:2 = ~(1 << flagBit);\n FLG = FLG & mask;\n}\n\n##### FREIT #####\n\n:FREIT is b1_0007=0x9f {\n FLG = SVF;\n return [SVP];\n}\n\n##### FSET #####\n\n:FSET flagBit is b1_0007=0xd1; b2_0307=0x1d & flagBit {\n mask:2 = (1 << flagBit);\n FLG = FLG | mask;\n}\n\n##### INC #####\n\n# INC.B dst5\n:INC.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B) {\n tmp:1 = dst5B + 1;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# INC.B Ax\n:INC.B dst5Ax is (b1_0407=0xa & b1_size_0=0; b2_0005=0x0e) & $(DST5AX) {\n tmp:1 = dst5Ax:1 + 1;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# INC.W dst5\n:INC.W dst5W is (b1_0407=0xa & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W) {\n tmp:2 = dst5W + 1;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# INC.W Ax\n:INC.W dst5Ax is (b1_0407=0xa & b1_size_0=1; b2_0005=0x0e) & $(DST5AX) {\n tmp:2 = dst5Ax:2 + 1;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### INDEXB #####\n\n# 1000 1000 0100 0011 INDEXB.B R1H\n:INDEXB.B dst5B is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x03) ... & $(DST5B) \n [ useByteIndexOffset=3; globalset(inst_next,useByteIndexOffset); useByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B);\n}\n\n:INDEXB.W dst5W is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x13) ... & $(DST5W) \n [ useByteIndexOffset=3; globalset(inst_next,useByteIndexOffset); useByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W);\n}\n\n##### INDEXBD #####\n\n:INDEXBD.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x03) ... & $(DST5B) \n [ useDstByteIndexOffset=3; globalset(inst_next,useDstByteIndexOffset); useDstByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B);\n}\n\n:INDEXBD.W dst5W is (b1_0407=0xa & b1_size_0=0; b2_0005=0x13) ... & $(DST5W) \n [ useDstByteIndexOffset=3; globalset(inst_next,useDstByteIndexOffset); useDstByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W);\n}\n\n##### INDEXBS #####\n\n:INDEXBS.B dst5B is (b1_0407=0xc & b1_size_0=0; b2_0005=0x03) ... & $(DST5B) \n [ useSrcByteIndexOffset=3; globalset(inst_next,useSrcByteIndexOffset); useSrcByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B);\n}\n\n:INDEXBS.W dst5W is (b1_0407=0xc & b1_size_0=0; b2_0005=0x13) ... & $(DST5W) \n [ useSrcByteIndexOffset=3; globalset(inst_next,useSrcByteIndexOffset); useSrcByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W);\n}\n\n##### INDEXL #####\n\n:INDEXL.B dst5B is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x23) ... & $(DST5B) \n [ useByteIndexOffset=3; globalset(inst_next,useByteIndexOffset); useByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B) * 4;\n}\n\n:INDEXL.W dst5W is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x33) ... & $(DST5W) \n [ useByteIndexOffset=3; globalset(inst_next,useByteIndexOffset); useByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W) * 4;\n}\n\n##### INDEXLD #####\n\n:INDEXLD.B dst5B is (b1_0407=0xb & b1_size_0=0; b2_0005=0x23) ... & $(DST5B) \n [ useDstByteIndexOffset=3; globalset(inst_next,useDstByteIndexOffset); useDstByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B) * 4;\n}\n\n:INDEXLD.W dst5W is (b1_0407=0xb & b1_size_0=0; b2_0005=0x33) ... & $(DST5W) \n [ useDstByteIndexOffset=3; globalset(inst_next,useDstByteIndexOffset); useDstByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W) * 4;\n}\n\n##### INDEXLS #####\n\n:INDEXLS.B dst5B is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x03) ... & $(DST5B) \n [ useSrcByteIndexOffset=3; globalset(inst_next,useSrcByteIndexOffset); useSrcByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B) * 4;\n}\n\n:INDEXLS.W dst5W is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x13) ... & $(DST5W) \n [ useSrcByteIndexOffset=3; globalset(inst_next,useSrcByteIndexOffset); useSrcByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W) * 4;\n}\n\n##### INDEXW #####\n\n:INDEXW.B dst5B is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x23) ... & $(DST5B) \n [ useByteIndexOffset=3; globalset(inst_next,useByteIndexOffset); useByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B) * 2;\n}\n\n:INDEXW.W dst5W is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x33) ... & $(DST5W) \n [ useByteIndexOffset=3; globalset(inst_next,useByteIndexOffset); useByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W) * 2;\n}\n\n##### INDEXWD #####\n\n:INDEXWD.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x23) ... & $(DST5B) \n [ useDstByteIndexOffset=3; globalset(inst_next,useDstByteIndexOffset); useDstByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B) * 2;\n}\n\n:INDEXWD.W dst5W is (b1_0407=0xa & b1_size_0=0; b2_0005=0x33) ... & $(DST5W) \n [ useDstByteIndexOffset=3; globalset(inst_next,useDstByteIndexOffset); useDstByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W) * 2;\n}\n\n##### INDEXWS #####\n\n:INDEXWS.B dst5B is (b1_0407=0xc & b1_size_0=0; b2_0005=0x23) ... & $(DST5B) \n [ useSrcByteIndexOffset=3; globalset(inst_next,useSrcByteIndexOffset); useSrcByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5B) * 2;\n}\n\n:INDEXWS.W dst5W is (b1_0407=0xc & b1_size_0=0; b2_0005=0x33) ... & $(DST5W) \n [ useSrcByteIndexOffset=3; globalset(inst_next,useSrcByteIndexOffset); useSrcByteIndexOffset=0; ] {\n byteIndexOffset = zext(dst5W) * 2;\n}\n\n##### INT #####\n\n:INT srcIntNum is b1_0007=0xbe; imm8_0001=0 & srcIntNum {\n push2(FLG);\n next:3 = inst_next;\n push3(next);\n ptr3:3 = (INTB + (zext(srcIntNum) * 0x4));\n pc:3 = *:3 ptr3;\n $(STACK_SEL) = ((srcIntNum > 0x1f) * $(STACK_SEL));\n $(INTERRUPT) = 0x0;\n $(DEBUG) = 0x0;\n call [pc];\n}\n\n##### INTO #####\n\n:INTO is b1_0007=0xbf {\n if ($(OVERFLOW) == 0) goto inst_next;\n push2(FLG);\n next:3 = inst_next;\n push3(next);\n $(STACK_SEL) = 0;\n $(INTERRUPT) = 0x0;\n $(DEBUG) = 0x0;\n call 0x0ffffe0;\n}\n\n##### JCnd #####\n\n:J^b1cnd rel8offset1 is b1_0707=1 & b1_0103=5 & b1cnd; rel8offset1 {\n if (b1cnd) goto rel8offset1;\n}\n\n##### JMP #####\n\n:JMP.S rel3offset2 is b1_0607=1 & b1_0103=5 & rel3offset2 {\n goto rel3offset2;\n}\n\n:JMP.B rel8offset1 is b1_0007=0xbb; rel8offset1 {\n goto rel8offset1;\n}\n\n:JMP.W rel16offset1 is b1_0007=0xce; rel16offset1 {\n goto rel16offset1;\n}\n\n:JMP.A abs24offset is b1_0007=0xcc; abs24offset {\n goto abs24offset;\n}\n\n##### JMPI #####\n:JMPI.W reloffset_dst5W is (b1_0407=0xc & b1_size_0=1; b2_0005=0x0f) ... & reloffset_dst5W {\n goto reloffset_dst5W;\n}\n\n:JMPI.A reloffset_dst5L is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x01) ... & reloffset_dst5L {\n goto reloffset_dst5L;\n}\n\n:JMPI.A reloffset_dst5Ax is (b1_0407=0x8 & b1_size_0=0; b2_0005=0x01) & reloffset_dst5Ax {\n goto reloffset_dst5Ax;\n}\n\n##### JMPS #####\n\n:JMPS srcImm8 is b1_0007=0xdc; srcImm8 {\n # 18 <= srcImm8 <= 255 (range restriction not enforced by pattern match)\n ptr:3 = 0x0fffe - (zext(srcImm8) << 1);\n pc:3 = 0xff0000 | zext(*:2 ptr);\n goto [pc];\n}\n\n##### JSR #####\n\n:JSR.W rel16offset1 is b1_0007=0xcf; rel16offset1 {\n next:3 = inst_next;\n push3(next);\n call rel16offset1;\n}\n\n:JSR.A abs24offset is b1_0007=0xcd; abs24offset {\n next:3 = inst_next;\n push3(next);\n call abs24offset;\n}\n\n##### JSRI #####\n\n:JSRI.W reloffset_dst5W is (b1_0407=0xc & b1_size_0=1; b2_0005=0x1f) ... & reloffset_dst5W {\n next:3 = inst_next;\n push3(next);\n call reloffset_dst5W;\n}\n\n:JSRI.A dst5L is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x01) ... & $(DST5L) {\n next:3 = inst_next;\n push3(next);\n pc:3 = dst5L:3;\n call [pc];\n}\n\n:JSRI.A dst5Ax is (b1_0407=0x9 & b1_size_0=0; b2_0005=0x01) & $(DST5AX) {\n next:3 = inst_next;\n push3(next);\n call [dst5Ax];\n}\n\n##### JSRS #####\n\n:JSRS srcImm8 is b1_0007=0xdd; srcImm8 {\n # 18 <= srcImm8 <= 255 (range restriction not enforced by pattern match)\n next:3 = inst_next;\n push3(next);\n ptr:3 = 0x0fffe - (zext(srcImm8) << 1);\n pc:3 = 0xff0000 | zext(*:2 ptr);\n call [pc];\n}\n\n##### LDC #####\n\n# (1) LDC #imm16, b2_creg16\n:LDC srcImm16, b2_creg16 is b1_0007=0xd5; b2_0307=0x15 & b2_creg16; srcImm16 {\n b2_creg16 = srcImm16;\n}\n\n# (2) LDC #imm24, b2_creg24\n:LDC srcImm24, b2_creg24 is b1_0007=0xd5; b2_0307=0x05 & b2_creg24; srcImm24 {\n b2_creg24 = srcImm24;\n}\n\n# (3) LDC #imm24, b2_dreg24\n:LDC srcImm24, b2_dreg24 is b1_0007=0xd5; b2_0307=0x0d & b2_dreg24; srcImm24 {\n b2_dreg24 = srcImm24;\n}\n\n# (4) LDC dst5, b2_creg16\n:LDC dst5W, b2_creg16 is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=1; b2_0305=1 & b2_creg16) ... & $(DST5W)) {\n b2_creg16 = dst5W;\n}\n\n# (5) LDC dst5, b2_creg24\n:LDC dst5L, b2_creg24 is (b1_0407=0xd & b1_size_0=1; b2_0305=0 & b2_creg24) ... & $(DST5L) {\n b2_creg24 = dst5L:3;\n}\n\n# (6) LDC dst5, b2_dreg24\n:LDC dst5L, b2_dreg24 is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=1; b2_0305=0 & b2_dreg24) ... & $(DST5L)) {\n b2_dreg24 = dst5L:3;\n}\n\n##### LDCTX #####\n\n:LDCTX abs16offset, abs24offset is b1_0007=0xb6; b2_0007=0xc3; abs16offset; imm24_dat & abs24offset {\n\n taskNum:1 = abs16offset; # load task number stored at abs16\n ptr:3 = imm24_dat + (zext(taskNum) * 2); # compute table entry address relative to abs24\n regInfo:1 = *:1 ptr;\n ptr = ptr + 1;\n spCorrect:1 = *:1 ptr;\n\n ptr = SP;\n\n if ((regInfo & 1) == 0) goto ;\n R0 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n R1 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n R2 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n R3 = *:2 ptr;\n ptr = ptr + 2;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n tmp:4 = *:4 ptr;\n A0 = tmp:3;\n ptr = ptr + 4;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n tmp = *:4 ptr;\n A1 = tmp:3;\n ptr = ptr + 4;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n tmp = *:4 ptr;\n SB = tmp:3;\n ptr = ptr + 4;\n \n regInfo = regInfo >> 1;\n if ((regInfo & 1) == 0) goto ;\n tmp = *:4 ptr;\n FB = tmp:3;\n ptr = ptr + 4;\n \n SP = SP + zext(spCorrect);\n}\n\n##### LDIPL #####\n\n:LDIPL srcImm3 is b1_0007=0xd5; b2_0307=0x1d & srcImm3 {\n $(IPL) = srcImm3;\n}\n\n##### MAX #####\n\n# (1) MAX.B #imm, dst5\n:MAX.B srcSimm8, dst5B is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3f) ... & $(DST5B)); srcSimm8 {\n if (srcSimm8 s<= dst5B) goto inst_next;\n dst5B = srcSimm8;\n}\n\n# (1) MAX.B #imm, Ax\n:MAX.B srcSimm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3f) & $(DST5AX)); srcSimm8 {\n if (srcSimm8 s<= dst5Ax:1) goto inst_next;\n dst5Ax = zext(srcSimm8);\n}\n\n# (1) MAX.W #imm, dst5\n:MAX.W srcSimm16, dst5W is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3f) ... & $(DST5W)); srcSimm16 {\n if (srcSimm16 s<= dst5W) goto inst_next;\n dst5W = srcSimm16;\n}\n\n# (1) MAX.W #imm, Ax\n:MAX.W srcSimm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3f) & $(DST5AX)); srcSimm16 {\n if (srcSimm16 s<= dst5Ax:2) goto inst_next;\n dst5Ax = zext(srcSimm16);\n}\n\n# (2) MAX.B src5, dst5\n:MAX.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xd) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n val:1 = src5B;\n if (val s<= dst5B_afterSrc5) goto inst_next;\n dst5B_afterSrc5 = val;\n} \n\n# (2) MAX.B src5, Ax\n:MAX.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xd) ... & $(SRC5B) & $(DST5AX) ...) {\n val:1 = src5B;\n if (val s<= dst5Ax:1) goto inst_next;\n dst5Ax = zext(val);\n} \n\n# (2) MAX.W src5, dst5\n:MAX.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0xd) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n val:2 = src5W;\n if (val s<= dst5W_afterSrc5) goto inst_next;\n dst5W_afterSrc5 = val;\n} \n\n# (2) MAX.W src5, Ax\n:MAX.B src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0xd) ... & $(SRC5W) & $(DST5AX) ...) {\n val:2 = src5W;\n if (val s<= dst5Ax:2) goto inst_next;\n dst5Ax = zext(val);\n} \n\n##### MIN #####\n\n# (1) MIN.B #imm, dst5\n:MIN.B srcSimm8, dst5B is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2f) ... & $(DST5B)); srcSimm8 {\n if (srcSimm8 s>= dst5B) goto inst_next;\n dst5B = srcSimm8;\n}\n\n# (1) MIN.B #imm, Ax\n:MIN.B srcSimm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2f) & $(DST5AX)); srcSimm8 {\n if (srcSimm8 s>= dst5Ax:1) goto inst_next;\n dst5Ax = zext(srcSimm8);\n}\n\n# (1) MIN.W #imm, dst5\n:MIN.W srcSimm16, dst5W is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2f) ... & $(DST5W)); srcSimm16 {\n if (srcSimm16 s>= dst5W) goto inst_next;\n dst5W = srcSimm16;\n}\n\n# (1) MIN.W #imm, Ax\n:MIN.W srcSimm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2f) & $(DST5AX)); srcSimm16 {\n if (srcSimm16 s>= dst5Ax:2) goto inst_next;\n dst5Ax = zext(srcSimm16);\n}\n\n# (2) MIN.B src5, dst5\n:MIN.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xc) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n val:1 = src5B;\n if (val s>= dst5B_afterSrc5) goto inst_next;\n dst5B_afterSrc5 = val;\n} \n\n# (2) MIN.B src5, Ax\n:MIN.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0xc) ... & $(SRC5B) & $(DST5AX) ...) {\n val:1 = src5B;\n if (val s>= dst5Ax:1) goto inst_next;\n dst5Ax = zext(val);\n} \n\n# (2) MIN.W src5, dst5\n:MIN.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0xc) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n val:2 = src5W;\n if (val s>= dst5W_afterSrc5) goto inst_next;\n dst5W_afterSrc5 = val;\n} \n\n# (2) MIN.W src5, Ax\n:MIN.B src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0xc) ... & $(SRC5W) & $(DST5AX) ...) {\n val:2 = src5W;\n if (val s>= dst5Ax:2) goto inst_next;\n dst5Ax = zext(val);\n} \n\n##### MOV #####\n\n# (1) MOV.B:G #imm, dst5\n:MOV^\".B:G\" srcImm8, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x2f) ... & $(DST5B)); srcImm8 {\n val:1 = srcImm8;\n dst5B = val;\n setResultFlags(val);\n}\n\n# (1) MOV.B:G #imm, Ax\n:MOV^\".B:G\" srcImm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x2f) & $(DST5AX)); srcImm8 {\n val:1 = srcImm8;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (1) MOV.W:G #imm, dst5\n:MOV^\".W:G\" srcImm16, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x2f) ... & $(DST5W)); srcImm16 {\n val:2 = srcImm16;\n dst5W = val;\n setResultFlags(val);\n}\n\n# (1) MOV.W:G #imm, Ax\n:MOV^\".W:G\" srcImm16, dst5Ax is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x2f) & $(DST5AX)); srcImm16 {\n val:2 = srcImm16;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (2) MOV.L:G #imm, dst5\n:MOV^\".L:G\" srcImm32, dst5L is ((b1_0407=0xb & b1_size_0=0; b2_0005=0x31) ... & $(DST5L)); srcImm32 {\n val:4 = srcImm32;\n dst5L = val;\n setResultFlags(val);\n}\n\n# (2) MOV.L:G #imm, Ax\n:MOV^\".L:G\" srcImm32, dst5Ax is ((b1_0407=0xb & b1_size_0=0; b2_0005=0x31) & $(DST5AX)); srcImm32 {\n val:4 = srcImm32;\n dst5Ax = val:3;\n setResultFlags(val);\n}\n\n# (3) MOV.B:Q #imm4, dst5\n:MOV^\".B:Q\" srcSimm4, dst5B is (b1_0407=0xf & b1_size_0=0; b2_0405=2 & srcSimm4) ... & $(DST5B) {\n val:1 = srcSimm4;\n dst5B = val;\n setResultFlags(val);\n}\n\n# (3) MOV.B:Q #imm4, Ax\n:MOV^\".B:Q\" srcSimm4, dst5Ax is (b1_0407=0xf & b1_size_0=0; b2_0405=2 & srcSimm4) & $(DST5AX) {\n val:1 = srcSimm4;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (3) MOV.W:Q #imm4, dst5\n:MOV^\".W:Q\" srcSimm4, dst5W is (b1_0407=0xf & b1_size_0=1; b2_0405=2 & srcSimm4) ... & $(DST5W) {\n val:2 = sext(srcSimm4);\n dst5W = val;\n setResultFlags(val);\n}\n\n# (3) MOV.W:Q #imm4, Ax\n:MOV^\".W:Q\" srcSimm4, dst5Ax is (b1_0407=0xf & b1_size_0=1; b2_0405=2 & srcSimm4) & $(DST5AX) {\n val:2 = sext(srcSimm4);\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (4) MOV.B:S #imm, dst2\n:MOV^\".B:S\" srcImm8, dst2B is ((b1_0607=0 & b1_0103=2 & b1_size_0=0) ... & dst2B); srcImm8 {\n val:1 = srcImm8;\n dst2B = val;\n setResultFlags(val);\n}\n\n# (4) MOV.W:S #imm, dst2\n:MOV^\".W:S\" srcImm16, dst2W is ((b1_0607=0 & b1_0103=2 & b1_size_0=1) ... & dst2W); srcImm16 {\n val:2 = srcImm16;\n dst2W = val;\n setResultFlags(val);\n}\n\n# (5) MOV.W:S #imm16, Ax\n:MOV^\".W:S\" srcImm16, b1_d1_regAx is b1_0607=2 & b1_size_5=0 & b1_0104=0xe & b1_d1_regAx; srcImm16 {\n val:2 = srcImm16;\n b1_d1_regAx = zext(val);\n setResultFlags(val);\n}\n\n# (5) MOV.L:S #imm24, Ax\n:MOV^\".L:S\" srcImm24, b1_d1_regAx is b1_0607=2 & b1_size_5=1 & b1_0104=0xe & b1_d1_regAx; srcImm24 {\n val:3 = srcImm24;\n b1_d1_regAx = val;\n setResultFlags(val);\n}\n\n# (6) MOV.B:Z #0, dst2\n:MOV^\".B:Z\" srcZero8, dst2B is (b1_0607=0 & b1_0103=1 & b1_size_0=0 & srcZero8) ... & dst2B {\n dst2B = 0;\n $(SIGN) = 0;\n $(ZERO) = 1;\n}\n\n# (6) MOV.W:Z #0, dst2\n:MOV^\".W:Z\" srcZero16, dst2W is (b1_0607=0 & b1_0103=1 & b1_size_0=1 & srcZero16) ... & dst2W {\n dst2W = 0;\n $(SIGN) = 0;\n $(ZERO) = 1;\n}\n\n# (7) MOV.B:G src5, dst5\n:MOV^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0xb) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... {\n val:1 = src5B;\n dst5B_afterSrc5 = val;\n setResultFlags(val);\n}\n\n# (7) MOV.B:G src5, Ax\n:MOV^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0xb) ... & $(SRC5B) & $(DST5AX) ... {\n val:1 = src5B;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (7) MOV.W:G src5, dst5\n:MOV^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0xb) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... {\n val:2 = src5W;\n dst5W_afterSrc5 = val;\n setResultFlags(val);\n}\n\n# (7) MOV.W:G src5, Ax\n:MOV^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0xb) ... & $(SRC5W) & $(DST5AX) ... {\n val:2 = src5W;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (8) MOV.L:G src5, dst5\n:MOV^\".L:G\" src5L, dst5L_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x3) ... & $(SRC5L) ... & $(DST5L_AFTER_SRC5) ... {\n val:4 = src5L;\n dst5L_afterSrc5 = val;\n setResultFlags(val);\n} \n\n# (8) MOV.L:G src5, Ax\n:MOV^\".L:G\" src5L, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x3) ... & $(SRC5L) & $(DST5AX) ... {\n val:4 = src5L;\n dst5Ax = val:3;\n setResultFlags(val);\n} \n\n# (9) MOV.B:S src2, R0L\n:MOV^\".B:S\" dst2B, R0L is (R0L & b1_0607=0 & b1_0103=4 & b1_size_0=0) ... & dst2B {\n val:1 = dst2B;\n R0L = val;\n setResultFlags(val);\n}\n\n# (9) MOV.W:S src2, R0\n:MOV^\".W:S\" dst2W, R0 is (R0 & b1_0607=0 & b1_0103=4 & b1_size_0=1) ... & dst2W {\n val:2 = dst2W;\n R0 = val;\n setResultFlags(val);\n}\n\n# (10) MOV.B:S src2, R1L\n:MOV^\".B:S\" dst2B, R1L is (R1L & b1_0607=1 & b1_0103=7 & b1_size_0=0) ... & dst2B {\n val:1 = dst2B;\n R1L = val;\n setResultFlags(val);\n}\n\n# (10) MOV.W:S src2, R1\n:MOV^\".W:S\" dst2W, R1 is (R1 & b1_0607=1 & b1_0103=7 & b1_size_0=1) ... & dst2W {\n val:2 = dst2W;\n R1 = val;\n setResultFlags(val);\n}\n\n# (11) MOV.B:S R0L, dst2 \n:MOV^\".B:S\" R0L, dst2B is (R0L & b1_0607=0 & b1_0103=0 & b1_size_0=0) ... & dst2B {\n val:1 = R0L;\n dst2B = val;\n setResultFlags(val);\n}\n\n# (11) MOV.W:S R0, dst2 \n:MOV^\".W:S\" R0, dst2W is (R0 & b1_0607=0 & b1_0103=0 & b1_size_0=1) ... & dst2W {\n val:2 = R0;\n dst2W = val;\n setResultFlags(val);\n}\n\n# (12) MOV.L:S src2L, Ax \n:MOV^\".L:S\" dst2L, b1_d1_regAx is (b1_0607=1 & b1_0103=4 & b1_d1_regAx) ... & dst2L {\n val:4 = dst2L;\n b1_d1_regAx = val:3;\n setResultFlags(val);\n}\n\n# (13) MOV.B:G dsp:8[SP], dst5\n# 1011 0110 1000 1111 0001 0010 1110 1111 1100 1101 1010 1011 MOV.G:G 0x12(SP),0xabcdef\n:MOV^\".B:G\" dsp8spB, dst5B_afterDsp8 is (b1_0407=0xb & b1_size_0=0; b2_0005=0x0f; dsp8spB) ... & $(DST5B_AFTER_DSP8) {\n val:1 = dsp8spB;\n dst5B_afterDsp8 = val;\n setResultFlags(val);\n}\n\n# (13) MOV.B:G dsp:8[SP], Ax\n:MOV^\".B:G\" dsp8spB, dst5Ax is (b1_0407=0xb & b1_size_0=0; b2_0005=0x0f; dsp8spB) & $(DST5AX) ... {\n val:1 = dsp8spB;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (13) MOV.W:G dsp:8[SP], dst5\n:MOV^\".W:G\" dsp8spW, dst5W_afterDsp8 is (b1_0407=0xb & b1_size_0=1; b2_0005=0x0f; dsp8spW) ... & $(DST5W_AFTER_DSP8) {\n val:2 = dsp8spW;\n dst5W_afterDsp8 = val;\n setResultFlags(val);\n}\n\n# (13) MOV.W:G dsp:8[SP], Ax\n:MOV^\".W:G\" dsp8spW, dst5Ax is (b1_0407=0xb & b1_size_0=1; b2_0005=0x0f; dsp8spW) & $(DST5AX) ... {\n val:2 = dsp8spW;\n dst5Ax = zext(val);\n setResultFlags(val);\n}\n\n# (14) MOV.B:G src5, dsp:8[SP]\n:MOV^\".B:G\" dst5B, dsp8spB is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x0f) ... & $(DST5B)); dsp8spB {\n val:1 = dst5B;\n dsp8spB = val;\n setResultFlags(val);\n}\n\n# (14) MOV.W:G src5, dsp:8[SP]\n:MOV^\".W:G\" dst5W, dsp8spW is ((b1_0407=0xa & b1_size_0=1; b2_0005=0x0f) ... & $(DST5W)); dsp8spW {\n val:2 = dst5W;\n dsp8spW = val;\n setResultFlags(val);\n}\n\n##### MOVA #####\n\n# MOVA dst5A, RxRx\n:MOVA dst5A, b2_reg32 is (b1_0407=0xd & b1_size_0=1; b2_0105=0xc & b2_reg32) ... & $(DST5A) {\n b2_reg32 = zext(dst5A);\n}\n\n# MOVA dst5A, Ax\n:MOVA dst5A, b2_regAx is (b1_0407=0xd & b1_size_0=1; b2_0105=0xd & b2_regAx) ... & $(DST5A) {\n b2_regAx = dst5A;\n}\n\n##### MOVDir #####\n\n# TODO: dst5B=Ax case will parse but is not valid\n\n# (1) MOVDir R0L, dst\n:MOVLL R0L, dst5B is R0L & b0_0007=0x1; ((b1_0407=0xb & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B)) {\n dst5B = (R0L & 0x0f) | (dst5B & 0xf0);\n}\n:MOVHL R0L, dst5B is R0L & b0_0007=0x1; ((b1_0407=0xb & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B)) {\n dst5B = ((R0L & 0xf0) >> 4) | (dst5B & 0xf0);\n}\n:MOVLH R0L, dst5B is R0L & b0_0007=0x1; ((b1_0407=0xb & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B)) {\n dst5B = ((R0L & 0x0f) << 4) | (dst5B & 0x0f);\n}\n:MOVHH R0L, dst5B is R0L & b0_0007=0x1; ((b1_0407=0xb & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B)) {\n dst5B = (R0L & 0xf0) | (dst5B & 0x0f);\n}\n\n# (2) MOVDir dst, R0L\n:MOVLL dst5B, R0L is R0L & b0_0007=0x1; ((b1_0407=0xa & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B)) {\n R0L = (dst5B & 0x0f) | (R0L & 0xf0);\n}\n:MOVHL dst5B, R0L is R0L & b0_0007=0x1; ((b1_0407=0xa & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B)) {\n R0L = ((dst5B & 0xf0) >> 4) | (R0L & 0xf0);\n}\n:MOVLH dst5B, R0L is R0L & b0_0007=0x1; ((b1_0407=0xa & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B)) {\n R0L = ((dst5B & 0x0f) << 4) | (R0L & 0x0f);\n}\n:MOVHH dst5B, R0L is R0L & b0_0007=0x1; ((b1_0407=0xa & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B)) {\n R0L = (dst5B & 0xf0) | (R0L & 0x0f);\n}\n\n##### MOVX #####\n\n:MOVX srcSimm8, dst5L is ((b1_0407=0xb & b1_size_0=0; b2_0005=0x11) ... & $(DST5L)); srcSimm8 {\n val:4 = sext(srcSimm8);\n dst5L = val;\n setResultFlags(val);\n}\n\n:MOVX srcSimm8, dst5Ax is ((b1_0407=0xb & b1_size_0=0; b2_0005=0x11) & $(DST5AX)); srcSimm8 {\n val:3 = sext(srcSimm8);\n dst5Ax = val;\n setResultFlags(val);\n}\n\n##### MUL #####\n\n# TODO: Illegal MUL destination cases will parse but are not valid (e.g., R0H/R2, R1H/R3)\n\n# (1) MUL.B #imm, dst5\n:MUL.B srcSimm8, dst5B is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x1f) ... & $(DST5W) & $(DST5B)); srcSimm8 {\n dst5W = sext(srcSimm8) * sext(dst5B);\n}\n\n# (1) MUL.B #imm, Ax\n:MUL.B srcSimm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x1f) & $(DST5AX)); srcSimm8 {\n val:2 = sext(srcSimm8) * sext(dst5Ax:1);\n dst5Ax = zext(val);\n}\n\n# (1) MUL.W #imm, dst5\n:MUL.W srcSimm16, dst5W is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x1f) ... & $(DST5L) & $(DST5W)); srcSimm16 {\n dst5L = sext(srcSimm16) * sext(dst5W);\n}\n\n# (1) MUL.W #imm, Ax\n:MUL.W srcSimm16, dst5Ax is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x1f) & $(DST5AX)); srcSimm16 {\n val:4 = sext(srcSimm16) * sext(dst5Ax:2);\n dst5Ax = val:3;\n}\n\n# (2) MUL.B src5, dst5\n:MUL.B src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0xc) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... & $(DST5W_AFTER_SRC5) ... {\n dst5W_afterSrc5 = sext(src5B) * sext(dst5B_afterSrc5);\n}\n\n# (2) MUL.B src5, Ax\n:MUL.B src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0xc) ... & $(SRC5B) & $(DST5AX) ... {\n val:2 = sext(src5B) * sext(dst5Ax:1);\n dst5Ax = zext(val);\n}\n\n# (2) MUL.W src5, dst5\n:MUL.W src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0xc) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... & $(DST5L_AFTER_SRC5) ... {\n dst5L_afterSrc5 = sext(src5W) * sext(dst5W_afterSrc5);\n}\n\n# (2) MUL.W src5, Ax\n:MUL.W src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0xc) ... & $(SRC5W) & $(DST5AX) ... {\n val:4 = sext(src5W) * sext(dst5Ax:2);\n dst5Ax = val:3;\n}\n\n##### MULEX #####\n\n:MULEX dst5W is (b1_0407=0xc & b1_size_0=1; b2_0005=0x3e) ... & $(DST5W) {\n R1R2R0 = sext(R2R0) * sext(dst5W);\n}\n\n##### MULU #####\n\n# TODO: Illegal MULU destination cases will parse but are not valid (e.g., R0H/R2, R1H/R3)\n\n# (1) MULU.B #imm, dst5\n:MULU.B srcImm8, dst5B is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x0f) ... & $(DST5B) & $(DST5W)); srcImm8 {\n dst5W = zext(srcImm8) * zext(dst5B);\n}\n\n# (1) MULU.B #imm, Ax\n:MULU.B srcImm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x0f) & $(DST5AX)); srcImm8 {\n val:2 = zext(srcImm8) * zext(dst5Ax:1);\n dst5Ax = zext(val);\n}\n\n# (1) MULU.W #imm, dst5\n:MULU.W srcImm16, dst5W is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x0f) ... & $(DST5W) & $(DST5L)); srcImm16 {\n dst5L = zext(srcImm16) * zext(dst5W);\n}\n\n# (1) MULU.W #imm, Ax\n:MULU.W srcImm16, dst5Ax is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x0f) & $(DST5AX)); srcImm16 {\n val:4 = zext(srcImm16) * zext(dst5Ax:2);\n dst5Ax = val:3;\n}\n\n# (2) MULU.B src5, dst5\n:MULU.B src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x4) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... & $(DST5W_AFTER_SRC5) ... {\n dst5W_afterSrc5 = zext(src5B) * zext(dst5B_afterSrc5);\n}\n\n# (2) MULU.B src5, Ax\n:MULU.B src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x4) ... & $(SRC5B) & $(DST5AX) ... {\n val:2 = zext(src5B) * zext(dst5Ax:1);\n dst5Ax = zext(val);\n}\n\n# (2) MULU.W src5, dst5\n:MULU.W src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x4) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... & $(DST5L_AFTER_SRC5) ... {\n dst5L_afterSrc5 = zext(src5W) * zext(dst5W_afterSrc5);\n}\n\n# (2) MULU.W src5, Ax\n:MULU.W src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x4) ... & $(SRC5W) & $(DST5AX) ... {\n val:4 = zext(src5W) * zext(dst5Ax:2);\n dst5Ax = val:3;\n}\n\n##### NEG #####\n\n# NEG.B dst5\n:NEG.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x2f) ... & $(DST5B) {\n tmp:1 = dst5B;\n setSubtractFlags(0:1, tmp);\n tmp = -tmp;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# NEG.B Ax\n:NEG.B dst5Ax is (b1_0407=0xa & b1_size_0=0; b2_0005=0x2f) & $(DST5AX) {\n tmp:1 = dst5Ax:1;\n setSubtractFlags(0:1, tmp);\n tmp = -tmp;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# NEG.W dst5\n:NEG.W dst5W is (b1_0407=0xa & b1_size_0=1; b2_0005=0x2f) ... & $(DST5W) {\n tmp:2 = dst5W;\n setSubtractFlags(0:2, tmp);\n tmp = -tmp;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# NEG.W Ax\n:NEG.W dst5Ax is (b1_0407=0xa & b1_size_0=1; b2_0005=0x2f) & $(DST5AX) {\n tmp:2 = dst5Ax:2;\n setSubtractFlags(0:2, tmp);\n tmp = -tmp;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### NOP #####\n\n:NOP is b1_0007=0xde {\n}\n\n##### NOT #####\n\n# NOT.B dst5\n:NOT.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x1e) ... & $(DST5B) {\n tmp:1 = ~dst5B;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# NOT.B Ax\n:NOT.B dst5Ax is (b1_0407=0xa & b1_size_0=0; b2_0005=0x1e) & $(DST5AX) {\n tmp:1 = ~dst5Ax:1;\n tmp = tmp;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# NOT.W dst5\n:NOT.W dst5W is (b1_0407=0xa & b1_size_0=1; b2_0005=0x1e) ... & $(DST5W) {\n tmp:2 = ~dst5W;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# NOT.W Ax\n:NOT.W dst5Ax is (b1_0407=0xa & b1_size_0=1; b2_0005=0x1e) & $(DST5AX) {\n tmp:2 = ~dst5Ax:2;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### OR #####\n\n# (1) OR.B:G #imm, dst\n:OR^\".B:G\" srcImm8, dst5B is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2f) ... & $(DST5B)); srcImm8 {\n tmp:1 = dst5B & srcImm8;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) OR.B:G #imm, Ax\n:OR^\".B:G\" srcImm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x2f) & $(DST5AX)); srcImm8 {\n tmp:1 = dst5Ax:1 & srcImm8;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) OR.W:G #imm, dst\n:OR^\".W:G\" srcImm16, dst5W is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2f) ... & $(DST5W)); srcImm16 {\n tmp:2 = dst5W & srcImm16;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) OR.W:G #imm, Ax\n:OR^\".W:G\" srcImm16, dst5Ax is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x2f) & $(DST5AX)); srcImm16 {\n tmp:2 = dst5Ax:2 & srcImm16;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) OR.B:S #imm, dst\n:OR^\".B:S\" srcImm8, dst2B is ((b1_0607=1 & b1_0103=2 & b1_size_0=0) ... & dst2B); srcImm8 {\n tmp:1 = dst2B & srcImm8;\n dst2B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) OR.W:S #imm, dst\n:OR^\".W:S\" srcImm16, dst2W is ((b1_0607=1 & b1_0103=2 & b1_size_0=1) ... & dst2W); srcImm16 {\n tmp:2 = dst2W & srcImm16;\n dst2W = tmp;\n setResultFlags(tmp);\n}\n\n# (3) OR.B:G src5, dst5\n:OR^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x5) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... {\n tmp:1 = dst5B_afterSrc5 & src5B;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n} \n\n# (3) OR.B:G src5, Ax\n:OR^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x5) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:1 = dst5Ax:1 & src5B;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n} \n\n# (3) OR.W:G src5, dst5\n:OR^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x5) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... {\n tmp:2 = dst5W_afterSrc5 & src5W;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n} \n\n# (3) OR.W:G src5, Ax\n:OR^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x5) ... & $(SRC5W) & $(DST5AX) ... {\n tmp:2 = dst5Ax:2 & src5W;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n} \n\n##### POP #####\n\n# POP.B dst5\n:POP.B dst5B is (b1_0407=0xb & b1_size_0=0; b2_0005=0x2f) ... & $(DST5B) {\n pop1(dst5B);\n}\n\n# POP.B Ax\n:POP.B dst5Ax is (b1_0407=0xb & b1_size_0=0; b2_0005=0x2f) & $(DST5AX) {\n val:1 = 0;\n pop1(val);\n dst5Ax = zext(val);\n}\n\n# POP.W dst5\n:POP.W dst5W is (b1_0407=0xb & b1_size_0=1; b2_0005=0x2f) ... & $(DST5W) {\n pop2(dst5W);\n}\n\n# POP.W Ax\n:POP.W dst5Ax is (b1_0407=0xb & b1_size_0=1; b2_0005=0x2f) & $(DST5AX) {\n val:2 = 0;\n pop2(val);\n dst5Ax = zext(val);\n}\n\n##### POPC #####\n\n# (1) POPC reg16\n:POPC b2_creg16 is b1_0007=0xd3; b2_0307=0x15 & b2_creg16 {\n pop2(b2_creg16);\n}\n\n# (2) POPC reg24\n:POPC b2_creg24 is b1_0007=0xd3; b2_0307=0x05 & b2_creg24 {\n pop3(b2_creg24);\n}\n\n##### POPM #####\npopRegFB: FB is regBit7=1 & FB { pop3(FB); }\npopRegFB: is regBit7=0 { }\n\npopRegSB: SB popRegFB is regBit6=1 & popRegFB & SB { pop3(SB); build popRegFB; }\npopRegSB: popRegFB is popRegFB { build popRegFB; }\n\npopRegA1: A1 popRegSB is regBit5=1 & popRegSB & A1 { pop3(A1); build popRegSB; }\npopRegA1: popRegSB is popRegSB { build popRegSB; }\npopRegA0: A0 popRegA1 is regBit4=1 & popRegA1 & A0 { pop3(A0); build popRegA1; }\npopRegA0: popRegA1 is popRegA1 { build popRegA1; }\n\npopRegR3: R3 popRegA0 is regBit3=1 & popRegA0 & R3 { pop2(R3); build popRegA0; }\npopRegR3: popRegA0 is popRegA0 { build popRegA0; }\npopRegR2: R2 popRegR3 is regBit2=1 & popRegR3 & R2 { pop2(R2); build popRegR3; }\npopRegR2: popRegR3 is popRegR3 { build popRegR3; }\npopRegR1: R1 popRegR2 is regBit1=1 & popRegR2 & R1 { pop2(R1); build popRegR2; }\npopRegR1: popRegR2 is popRegR2 { build popRegR2; }\npopRegR0: R0 popRegR1 is regBit0=1 & popRegR1 & R0 { pop2(R0); build popRegR1; }\npopRegR0: popRegR1 is popRegR1 { build popRegR1; }\n\npopRegList: \"( \"^popRegR0^\")\" is popRegR0 { build popRegR0; }\n\n:POPM popRegList is b1_0007=0x8e; popRegList {\n build popRegList;\n}\n\n##### PUSH #####\n\n# (1) PUSH.B #imm\n:PUSH.B srcImm8 is b1_0007=0xae; srcImm8 {\n push1(srcImm8);\n#tmp:2 = zext(srcImm8); # This differs from what really happens - decompiler tries to resolve source of unknown byte on stack\n#push2(tmp);\n}\n\n# (1) PUSH.W #imm\n:PUSH.B srcImm16 is b1_0007=0xaf; srcImm16 {\n push2(srcImm16);\n}\n\n# (2) PUSH.B src5\n:PUSH.B dst5B is (b1_0407=0xc & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B) {\n push1(dst5B);\n#tmp:2 = zext(dst5B); # This differs from what really happens - decompiler tries to resolve source of unknown byte on stack\n#push2(tmp);\n}\n\n# (2) PUSH.W src5\n:PUSH.W dst5W is (b1_0407=0xc & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W) {\n push2(dst5W);\n}\n\n# (3) PUSH.L #imm\n:PUSH.L srcImm32 is b1_0007=0xb6; b2_0007=0x53; srcImm32 {\n push4(srcImm32);\n}\n\n# (4) PUSH.L src5\n:PUSH.L dst5L is (b1_0407=0xa & b1_size_0=0; b2_0005=0x01) ... & $(DST5L) {\n push4(dst5L);\n}\n\n##### PUSHA #####\n\n:PUSHA dst5A is (b1_0407=0xb & b1_size_0=0; b2_0005=0x01) ... & $(DST5A) {\n push3(dst5A);\n#tmp:4 = zext(dst5A); # This differs from what really happens - decompiler tries to resolve source of unknown byte on stack\n#push4(tmp);\n}\n\n##### PUSHC #####\n\n# (1) PUSHC reg16\n:PUSHC b2_creg16 is b1_0007=0xd1; b2_0307=0x15 & b2_creg16 {\n push2(b2_creg16);\n}\n\n# (2) PUSHC reg24\n:PUSHC b2_creg24 is b1_0007=0xd1; b2_0307=0x05 & b2_creg24 {\n push3(b2_creg24);\n#tmp:4 = zext(b2_creg24); # This differs from what really happens - decompiler tries to resolve source of unknown byte on stack\n#push4(tmp);\n}\n\n##### PUSHM #####\npushRegR0: R0 is regBit7=1 & R0 { push2(R0); }\npushRegR0: is regBit7=0 { }\npushRegR1: pushRegR0 R1 is regBit6=1 & pushRegR0 & R1 { push2(R1); build pushRegR0; }\npushRegR1: pushRegR0 is pushRegR0 { build pushRegR0; }\npushRegR2: pushRegR1 R2 is regBit5=1 & pushRegR1 & R2 { push2(R2); build pushRegR1; }\npushRegR2: pushRegR1 is pushRegR1 { build pushRegR1; }\npushRegR3: pushRegR2 R3 is regBit4=1 & pushRegR2 & R3 { push2(R3); build pushRegR2; }\npushRegR3: pushRegR2 is pushRegR2 { build pushRegR2; }\n\npushRegA0: pushRegR3 A0 is regBit3=1 & pushRegR3 & A0 { push3(A0); build pushRegR3; }\npushRegA0: pushRegR3 is pushRegR3 { build pushRegR3; }\npushRegA1: pushRegA0 A1 is regBit2=1 & pushRegA0 & A1 { push3(A1); build pushRegA0; }\npushRegA1: pushRegA0 is pushRegA0 { build pushRegA0; }\n\npushRegSB: pushRegA1 SB is regBit1=1 & pushRegA1 & SB { push3(SB); build pushRegA1; }\npushRegSB: pushRegA1 is pushRegA1 { build pushRegA1; }\n\npushRegFB: pushRegSB FB is regBit0=1 & pushRegSB & FB { push3(FB); build pushRegSB; }\npushRegFB: pushRegSB is pushRegSB { build pushRegSB; }\n\npushRegList: \"(\"^pushRegFB^\" )\" is pushRegFB { build pushRegFB; }\n\n:PUSHM pushRegList is b1_0007=0x8f; pushRegList {\n build pushRegList;\n}\n\n##### REIT #####\n\n:REIT is b1_0007=0x9e {\n pc:3 = 0;\n pop3(pc);\n pop2(FLG);\n return [pc];\n}\n\n##### RMPA #####\n\n:RMPA.B is b1_0007=0xb8; b2_0007=0x43 {\n if (R3 == 0) goto inst_next;\n a:1 = *:1 A0;\n b:1 = *:1 A1;\n A0 = A0 + 1;\n A1 = A1 + 1;\n prod:6 = sext(a) * sext(b);\n o:1 = scarry(R1R2R0, prod);\n $(OVERFLOW) = o | $(OVERFLOW);\n R1R2R0 = R1R2R0 + prod;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:RMPA.W is b1_0007=0xb8; b2_0007=0x53 {\n if (R3 == 0) goto inst_next;\n a:2 = *:2 A0;\n b:2 = *:2 A1;\n A0 = A0 + 2;\n A1 = A1 + 2;\n prod:6 = sext(a) * sext(b);\n o:1 = scarry(R1R2R0, prod);\n $(OVERFLOW) = o | $(OVERFLOW);\n R1R2R0 = R1R2R0 + prod;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n##### ROLC #####\n\n:ROLC.B dst5B is (b1_0407=0xb & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B) {\n c:1 = $(CARRY);\n tmp:1 = dst5B;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n:ROLC.B dst5Ax is (b1_0407=0xb & b1_size_0=0; b2_0005=0x2e) & $(DST5AX) {\n c:1 = $(CARRY);\n tmp:1 = dst5Ax:1;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n:ROLC.W dst5W is (b1_0407=0xb & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W) {\n c:2 = zext($(CARRY));\n tmp:2 = dst5W;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n:ROLC.W dst5Ax is (b1_0407=0xb & b1_size_0=1; b2_0005=0x2e) & $(DST5AX) {\n c:2 = zext($(CARRY));\n tmp:2 = dst5Ax:2;\n $(CARRY) = tmp s< 0;\n tmp = (tmp << 1) | c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### RORC #####\n\n:RORC.B dst5B is (b1_0407=0xa & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B) {\n c:1 = $(CARRY);\n tmp:1 = dst5B;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 7);\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n:RORC.B dst5Ax is (b1_0407=0xa & b1_size_0=0; b2_0005=0x2e) & $(DST5AX) {\n c:1 = $(CARRY);\n tmp:1 = dst5Ax:1;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 7);\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n:RORC.W dst5W is (b1_0407=0xa & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W) {\n c:2 = zext($(CARRY));\n tmp:2 = dst5W;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 15);\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n:RORC.W dst5Ax is (b1_0407=0xa & b1_size_0=1; b2_0005=0x2e) & $(DST5AX) {\n c:2 = zext($(CARRY));\n tmp:2 = dst5Ax:2;\n $(CARRY) = (tmp & 1) == 1;\n tmp = (tmp >> 1) | (c << 15);\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### ROT #####\n\n# (1) ROT.B #imm4, dst5 (right)\n:ROT.B srcSimm4Shift, dst5B is (b1_0407=0xe & b1_size_0=0; b2_0405=2 & b2_shiftSign=1 & srcSimm4Shift) ... & $(DST5B) {\n rightShift:1 = -srcSimm4Shift;\n tmp:1 = dst5B;\n $(CARRY) = (tmp >> (rightShift - 1)) & 1;\n tmp = (tmp >> rightShift) | (tmp << (8 - rightShift));\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.B #imm4, Ax (right)\n:ROT.B srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=0; b2_0405=2 & b2_shiftSign=1 & srcSimm4Shift) & $(DST5AX) {\n rightShift:1 = -srcSimm4Shift;\n tmp:1 = dst5Ax:1;\n $(CARRY) = (tmp >> (rightShift - 1)) & 1;\n tmp = (tmp >> rightShift) | (tmp << (8 - rightShift));\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ROT.W #imm4, dst5 (right)\n:ROT.W srcSimm4Shift, dst5W is (b1_0407=0xe & b1_size_0=1; b2_0405=2 & b2_shiftSign=1 & srcSimm4Shift) ... & $(DST5W) {\n rightShift:1 = -srcSimm4Shift;\n tmp:2 = dst5W;\n c:2 = (tmp >> (rightShift - 1));\n $(CARRY) = c:1 & 1;\n tmp = (tmp >> rightShift) | (tmp << (16 - rightShift));\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.W #imm4, Ax (right)\n:ROT.W srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=1; b2_0405=2 & b2_shiftSign=1 & srcSimm4Shift) & $(DST5AX) {\n rightShift:1 = -srcSimm4Shift;\n tmp:2 = dst5Ax:2;\n c:2 = (tmp >> (rightShift - 1));\n $(CARRY) = c:1 & 1;\n tmp = (tmp >> rightShift) | (tmp << (16 - rightShift));\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ROT.B #imm4, dst5 (left)\n:ROT.B srcSimm4Shift, dst5B is (b1_0407=0xe & b1_size_0=0; b2_0405=2 & b2_shiftSign=0 & srcSimm4Shift) ... & $(DST5B) {\n leftShift:1 = srcSimm4Shift;\n tmp:1 = dst5B;\n $(CARRY) = (tmp >> (8 - leftShift)) & 1;\n tmp = (tmp << leftShift) | (tmp >> (8 - leftShift));\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.B #imm4, Ax (left)\n:ROT.B srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=0; b2_0405=2 & b2_shiftSign=0 & srcSimm4Shift) & $(DST5AX) {\n leftShift:1 = srcSimm4Shift;\n tmp:1 = dst5Ax:1;\n $(CARRY) = (tmp >> (8 - leftShift)) & 1;\n tmp = (tmp << leftShift) | (tmp >> (8 - leftShift));\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) ROT.W #imm4, dst5 (left)\n:ROT.W srcSimm4Shift, dst5W is (b1_0407=0xe & b1_size_0=1; b2_0405=2 & b2_shiftSign=0 & srcSimm4Shift) ... & $(DST5W) {\n leftShift:1 = srcSimm4Shift;\n tmp:2 = dst5W;\n c:2 = (tmp >> (16 - leftShift));\n $(CARRY) = c:1 & 1;\n tmp = (tmp << leftShift) | (tmp >> (16 - leftShift));\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) ROT.W #imm4, Ax (left)\n:ROT.W srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=1; b2_0405=2 & b2_shiftSign=0 & srcSimm4Shift) & $(DST5AX) {\n leftShift:1 = srcSimm4Shift;\n tmp:2 = dst5Ax:2;\n c:2 = (tmp >> (16 - leftShift));\n $(CARRY) = c:1 & 1;\n tmp = (tmp << leftShift) | (tmp >> (16 - leftShift));\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ROT.B R1H, dst5\n:ROT.B R1H, dst5B is (R1H & b1_0407=0xa & b1_size_0=0; b2_0005=0x3f) ... & $(DST5B) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 8;\n tmp:1 = dst5B;\n if (shift s>= 0) goto ;\n shift = -shift;\n $(CARRY) = (tmp >> (shift - 1)) & 1;\n tmp = (tmp >> shift) | (tmp << (8 - shift));\n goto ;\n \n $(CARRY) = (tmp >> (8 - shift)) & 1;\n tmp = (tmp << shift) | (tmp >> (8 - shift));\n \n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ROT.B R1H, Ax\n:ROT.B R1H, dst5Ax is (R1H & b1_0407=0xa & b1_size_0=0; b2_0005=0x3f) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 8;\n tmp:1 = dst5Ax:1;\n if (shift s>= 0) goto ;\n shift = -shift;\n $(CARRY) = (tmp >> (shift - 1)) & 1;\n tmp = (tmp >> shift) | (tmp << (8 - shift));\n goto ;\n \n $(CARRY) = (tmp >> (8 - shift)) & 1;\n tmp = (tmp << shift) | (tmp >> (8 - shift));\n \n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) ROT.W R1H, dst5\n:ROT.W R1H, dst5W is (R1H & b1_0407=0xa & b1_size_0=1; b2_0005=0x3f) ... & $(DST5W) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 16;\n tmp:2 = dst5W;\n if (shift s>= 0) goto ;\n shift = -shift;\n c:2 = (tmp >> (shift - 1));\n tmp = (tmp >> shift) | (tmp << (16 - shift));\n goto ;\n \n c = (tmp >> (16 - shift));\n tmp = (tmp << shift) | (tmp >> (16 - shift));\n \n $(CARRY) = c:1 & 1;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (2) ROT.W R1H, Ax\n:ROT.W R1H, dst5Ax is (R1H & b1_0407=0xa & b1_size_0=1; b2_0005=0x3f) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H s% 16;\n tmp:2 = dst5Ax:2;\n if (shift s>= 0) goto ;\n shift = -shift;\n c:2 = (tmp >> (shift - 1));\n tmp = (tmp >> shift) | (tmp << (16 - shift));\n goto ;\n \n c = (tmp >> (16 - shift));\n tmp = (tmp << shift) | (tmp >> (16 - shift));\n \n $(CARRY) = c:1 & 1;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### RTS #####\n\n:RTS is b1_0007=0xdf {\n pc:3 = 0;\n pop3(pc);\n return [pc];\n}\n\n##### SBB #####\n\n# (1) SBB.B #simm, dst\n:SBB.B srcSimm8, dst5B is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x2e) ... & $(DST5B)); srcSimm8 {\n tmp:1 = dst5B;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, srcSimm8, c);\n tmp = tmp - srcSimm8 - c;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SBB.B #simm, Ax\n:SBB.B srcSimm8, dst5Ax is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x2e) & $(DST5AX)); srcSimm8 {\n tmp:1 = dst5Ax:1;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, srcSimm8, c);\n tmp = tmp - srcSimm8 - c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) SBB.W #simm, dst\n:SBB.W srcSimm16, dst5W is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x2e) ... & $(DST5W)); srcSimm16 {\n tmp:2 = dst5W;\n c:2 = zext($(CARRY));\n setSubtract3Flags(tmp, srcSimm16, c);\n tmp = tmp - srcSimm16 - c;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SBB.B #simm, Ax\n:SBB.W srcSimm16, dst5Ax is b0_0007=0x1; ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x2e) & $(DST5AX)); srcSimm16 {\n tmp:2 = dst5Ax:2;\n c:2 = zext($(CARRY));\n setSubtract3Flags(tmp, srcSimm16, c);\n tmp = tmp - srcSimm16 - c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) SBB.B src5, dst5\n:SBB.B src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x6) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n tmp:1 = dst5B_afterSrc5;\n s:1 = src5B;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SBB.B src5, Ax\n:SBB.B src5B, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x6) ... & $(SRC5B) & $(DST5AX) ...) {\n tmp:1 = dst5Ax:1;\n s:1 = src5B;\n c:1 = $(CARRY);\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) SBB.W src5, dst5\n:SBB.W src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x6) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n tmp:2 = dst5W_afterSrc5;\n s:2 = src5W;\n c:2 = zext($(CARRY));\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SBB.W src5, Ax\n:SBB.W src5W, dst5Ax is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x6) ... & $(SRC5W) & $(DST5AX) ...) {\n tmp:2 = dst5Ax:2;\n s:2 = src5W;\n c:2 = zext($(CARRY));\n setSubtract3Flags(tmp, s, c);\n tmp = tmp - s - c;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n##### SBJNZ - PSUEDO-OP! SAME AS ADJNZ #####\n\n##### SCCnd #####\n\n:SC^b2cnd dst5W is (b1_0407=0xd & b1_size_0=1; b2_0405=3 & b2cnd) ... & $(DST5W) {\n dst5W = zext(b2cnd);\n}\n\n:SC^b2cnd dst5Ax is (b1_0407=0xd & b1_size_0=1; b2_0405=3 & b2cnd) & $(DST5AX) {\n dst5Ax = zext(b2cnd);\n}\n\n##### SCMPU #####\n\n:SCMPU.B is b1_0007=0xb8; b2_0007=0xc3 {\n tmp0:1 = *:1 A0;\n tmp2:1 = *:1 A1;\n setSubtractFlags(tmp0, tmp2);\n tmp:1 = tmp0 - tmp2;\n setResultFlags(tmp);\n A0 = A0 + 1;\n A1 = A1 + 1;\n if ((tmp0 != 0) && (tmp0 == tmp2)) goto inst_start;\n}\n\n:SCMPU.W is b1_0007=0xb8; b2_0007=0xd3 {\n # TODO: The symantic description looks suspicious - manual may be incorrect ??\n tmp0:1 = *:1 A0;\n tmp2:1 = *:1 A1;\n setSubtractFlags(tmp0, tmp2);\n setResultFlags(tmp0 - tmp2);\n A0 = A0 + 1;\n A1 = A1 + 1;\n tmp1:1 = *:1 A0;\n tmp3:1 = *:1 A1;\n A0 = A0 + 1;\n A1 = A1 + 1;\n if (tmp0 == 0 || tmp0 != tmp2) goto ;\n setSubtractFlags(tmp1, tmp3);\n setResultFlags(tmp1 - tmp3);\n \n if ((tmp0 != 0) && (tmp1 != 0) && (tmp0 == tmp2) && (tmp1 == tmp3)) goto inst_start;\n}\n\n##### SHA #####\nmacro SHAsetShiftRightFlags(val,shift,result) {\n local c = (val >> (shift - 1)) & 1;\n $(CARRY) = c:1;\n local mask = ~(-(1 << shift));\n allOnes:1 = (mask & val) == mask;\n allZeros:1 = (mask & val) == 0;\n $(OVERFLOW) = (result s< 0 && allOnes) || (result s>= 0 && allZeros);\n setResultFlags(result);\n} \n\nmacro SHAsetShiftLeftFlags(val,shift,result,sze) {\n local c = (val >> (sze - shift)) & 1;\n $(CARRY) = c:1;\n local mask = -(1 << shift);\n allOnes:1 = (mask & val) == mask;\n allZeros:1 = (mask & val) == 0;\n $(OVERFLOW) = (result s< 0 && allOnes) || (result s>= 0 && allZeros);\n setResultFlags(result);\n}\n\n# (1) SHA.B #imm4, dst5 (right)\n:SHA.B srcSimm4Shift, dst5B is (b1_0407=0xf & b1_size_0=0; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) ... & $(DST5B) {\n val:1 = dst5B;\n shift:1 = -srcSimm4Shift;\n tmp:1 = val s>> shift;\n dst5B = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.B #imm4, Ax (right)\n:SHA.B srcSimm4Shift, dst5Ax is (b1_0407=0xf & b1_size_0=0; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) & $(DST5AX) {\n val:1 = dst5Ax:1;\n shift:1 = -srcSimm4Shift;\n tmp:1 = val s>> shift;\n dst5Ax = zext(tmp);\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.W #imm4, dst5 (right)\n:SHA.W srcSimm4Shift, dst5W is (b1_0407=0xf & b1_size_0=1; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) ... & $(DST5W) {\n val:2 = dst5W;\n shift:1 = -srcSimm4Shift;\n tmp:2 = val s>> shift;\n dst5W = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.W #imm4, Ax (right)\n:SHA.W srcSimm4Shift, dst5Ax is (b1_0407=0xf & b1_size_0=1; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) & $(DST5AX) {\n val:2 = dst5Ax:2;\n shift:1 = -srcSimm4Shift;\n tmp:2 = val s>> shift;\n dst5Ax = zext(tmp);\n SHAsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHA.B #imm4, dst5 (left)\n:SHA.B srcSimm4Shift, dst5B is (b1_0407=0xf & b1_size_0=0; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) ... & $(DST5B) {\n val:1 = dst5B;\n shift:1 = srcSimm4Shift;\n tmp:1 = val << shift;\n dst5B = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHA.B #imm4, Ax (left)\n:SHA.B srcSimm4Shift, dst5Ax is (b1_0407=0xf & b1_size_0=0; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) & $(DST5AX) {\n val:1 = dst5Ax:1;\n shift:1 = srcSimm4Shift;\n tmp:1 = val << shift;\n dst5Ax = zext(tmp);\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHA.W #imm4, dst5 (left)\n:SHA.W srcSimm4Shift, dst5W is (b1_0407=0xf & b1_size_0=1; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) ... & $(DST5W) {\n val:2 = dst5W;\n shift:1 = srcSimm4Shift;\n tmp:2 = val << shift;\n dst5W = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (1) SHA.W #imm4, Ax (left)\n:SHA.W srcSimm4Shift, dst5Ax is (b1_0407=0xf & b1_size_0=1; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) & $(DST5AX) {\n val:2 = dst5Ax:2;\n shift:1 = srcSimm4Shift;\n tmp:2 = val << shift;\n dst5Ax = zext(tmp);\n SHAsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (2) SHA.L #imm, dst5\n:SHA.L srcSimm8, dst5L is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x21) ... & $(DST5L)); srcSimm8 {\n # Unable to pattern match on sign bit due to interior ellipses\n shift:1 = srcSimm8;\n val:4 = dst5L;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val s>> shift;\n dst5L = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5L = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n# (2) SHA.L #imm, Ax\n:SHA.L srcSimm8, dst5Ax is ((b1_0407=0xa & b1_size_0=0; b2_0005=0x21) & $(DST5AX)); srcSimm8 {\n # Unable to pattern match on sign bit due to interior ellipses\n shift:1 = srcSimm8;\n val:4 = zext(dst5Ax);\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val s>> shift;\n dst5Ax = tmp:3;\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = tmp:3;\n# No flags set\n}\n\n# (3) SHA.B R1H, dst5\n:SHA.B R1H, dst5B is (R1H & b1_0407=0xb & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst5B;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val s>> shift;\n dst5B = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5B = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (3) SHA.B R1H, Ax\n:SHA.B R1H, dst5Ax is (R1H & b1_0407=0xb & b1_size_0=0; b2_0005=0x3e) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst5Ax:1;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val s>> shift;\n dst5Ax = zext(tmp);\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = zext(tmp);\n SHAsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (3) SHA.W R1H, dst5\n:SHA.W R1H, dst5W is (R1H & b1_0407=0xb & b1_size_0=1; b2_0005=0x3e) ... & $(DST5W) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:2 = dst5W;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:2 = val s>> shift;\n dst5W = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5W = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (3) SHA.W R1H, Ax\n:SHA.W R1H, dst5Ax is (R1H & b1_0407=0xb & b1_size_0=1; b2_0005=0x3e) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:2 = dst5Ax:2;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:2 = val s>> shift;\n dst5Ax = zext(tmp);\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = zext(tmp);\n SHAsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (4) SHA.L R1H, dst5\n:SHA.L R1H, dst5L is (R1H & b1_0407=0xc & b1_size_0=0; b2_0005=0x11) ... & $(DST5L) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:4 = dst5L;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val s>> shift;\n dst5L = tmp;\n SHAsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5L = tmp;\n SHAsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n# (4) SHA.L R1H, Ax\n:SHA.L R1H, dst5Ax is (R1H & b1_0407=0xc & b1_size_0=0; b2_0005=0x11) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:4 = zext(dst5Ax);\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val s>> shift;\n dst5Ax = tmp:3;\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = tmp:3;\n# No flags set\n}\n\n##### SHL #####\nmacro SHLsetShiftRightFlags(val,shift,result) {\n local c = (val >> (shift - 1)) & 1;\n $(CARRY) = c:1;\n setResultFlags(result);\n} \n\nmacro SHLsetShiftLeftFlags(val,shift,result,sze) {\n local c = (val >> (sze - shift)) & 1;\n $(CARRY) = c:1;\n setResultFlags(result);\n}\n\n# (1) SHL.B #imm4, dst5 (right)\n:SHL.B srcSimm4Shift, dst5B is (b1_0407=0xe & b1_size_0=0; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) ... & $(DST5B) {\n val:1 = dst5B;\n shift:1 = -srcSimm4Shift;\n tmp:1 = val >> shift;\n dst5B = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.B #imm4, Ax (right)\n:SHL.B srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=0; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) & $(DST5AX) {\n val:1 = dst5Ax:1;\n shift:1 = -srcSimm4Shift;\n tmp:1 = val >> shift;\n dst5Ax = zext(tmp);\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.W #imm4, dst5 (right)\n:SHL.W srcSimm4Shift, dst5W is (b1_0407=0xe & b1_size_0=1; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) ... & $(DST5W) {\n val:2 = dst5W;\n shift:1 = -srcSimm4Shift;\n tmp:2 = val >> shift;\n dst5W = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.W #imm4, Ax (right)\n:SHL.W srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=1; b2_0405=0 & b2_shiftSign=1 & srcSimm4Shift) & $(DST5AX) {\n val:2 = dst5Ax:2;\n shift:1 = -srcSimm4Shift;\n tmp:2 = val >> shift;\n dst5Ax = zext(tmp);\n SHLsetShiftRightFlags(val, shift, tmp);\n}\n\n# (1) SHL.B #imm4, dst5 (left)\n:SHL.B srcSimm4Shift, dst5B is (b1_0407=0xe & b1_size_0=0; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) ... & $(DST5B) {\n val:1 = dst5B;\n shift:1 = srcSimm4Shift;\n tmp:1 = val << shift;\n dst5B = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHL.B #imm4, Ax (left)\n:SHL.B srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=0; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) & $(DST5AX) {\n val:1 = dst5Ax:1;\n shift:1 = srcSimm4Shift;\n tmp:1 = val << shift;\n dst5Ax = zext(tmp);\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (1) SHL.W #imm4, dst5 (left)\n:SHL.W srcSimm4Shift, dst5W is (b1_0407=0xe & b1_size_0=1; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) ... & $(DST5W) {\n val:2 = dst5W;\n shift:1 = srcSimm4Shift;\n tmp:2 = val << shift;\n dst5W = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (1) SHL.W #imm4, Ax (left)\n:SHL.W srcSimm4Shift, dst5Ax is (b1_0407=0xe & b1_size_0=1; b2_0405=0 & b2_shiftSign=0 & srcSimm4Shift) & $(DST5AX) {\n val:2 = dst5Ax:2;\n shift:1 = srcSimm4Shift;\n tmp:2 = val << shift;\n dst5Ax = zext(tmp);\n SHLsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (2) SHL.L #imm, dst5\n:SHL.L srcSimm8, dst5L is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x21) ... & $(DST5L)); srcSimm8 {\n # Unable to pattern match on sign bit due to interior ellipses\n shift:1 = srcSimm8;\n val:4 = dst5L;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val >> shift;\n dst5L = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5L = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n# (2) SHL.L #imm, Ax\n:SHL.L srcSimm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x21) & $(DST5AX)); srcSimm8 {\n # Unable to pattern match on sign bit due to interior ellipses\n shift:1 = srcSimm8;\n val:4 = zext(dst5Ax);\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val >> shift;\n dst5Ax = tmp:3;\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = tmp:3;\n# No flags set\n}\n\n# (3) SHL.B R1H, dst5\n:SHL.B R1H, dst5B is (R1H & b1_0407=0xa & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst5B;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val >> shift;\n dst5B = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5B = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (3) SHL.B R1H, Ax\n:SHL.B R1H, dst5Ax is (R1H & b1_0407=0xa & b1_size_0=0; b2_0005=0x3e) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:1 = dst5Ax:1;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:1 = val >> shift;\n dst5Ax = zext(tmp);\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = zext(tmp);\n SHLsetShiftLeftFlags(val, shift, tmp, 8);\n}\n\n# (3) SHL.W R1H, dst5\n:SHL.W R1H, dst5W is (R1H & b1_0407=0xa & b1_size_0=1; b2_0005=0x3e) ... & $(DST5W) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:2 = dst5W;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:2 = val >> shift;\n dst5W = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5W = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (3) SHL.W R1H, Ax\n:SHL.W R1H, dst5Ax is (R1H & b1_0407=0xa & b1_size_0=1; b2_0005=0x3e) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:2 = dst5Ax:2;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:2 = val >> shift;\n dst5Ax = zext(tmp);\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = zext(tmp);\n SHLsetShiftLeftFlags(val, shift, tmp, 16);\n}\n\n# (4) SHL.L R1H, dst5\n:SHL.L R1H, dst5L is (R1H & b1_0407=0xc & b1_size_0=0; b2_0005=0x01) ... & $(DST5L) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:4 = dst5L;\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val >> shift;\n dst5L = tmp;\n SHLsetShiftRightFlags(val, shift, tmp);\n goto inst_next;\n \n tmp = val << shift;\n dst5L = tmp;\n SHLsetShiftLeftFlags(val, shift, tmp, 32);\n}\n\n# (4) SHL.L R1H, Ax\n:SHL.L R1H, dst5Ax is (R1H & b1_0407=0xc & b1_size_0=0; b2_0005=0x01) & $(DST5AX) {\n if (R1H == 0) goto inst_next;\n shift:1 = R1H;\n val:4 = zext(dst5Ax);\n if (shift s> 0) goto ;\n shift = -shift;\n tmp:4 = val >> shift;\n dst5Ax = tmp:3;\n goto inst_next;\n \n tmp = val << shift;\n dst5Ax = tmp:3;\n# No flags set\n}\n\n##### SIN #####\n\n:SIN.B is b1_0007=0xb2; b2_0007=0x83 {\n if (R3 == 0) goto inst_next;\n *:1 A1 = *:1 A0;\n A1 = A1 + 1;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SIN.W is b1_0007=0xb2; b2_0007=0x93 {\n if (R3 == 0) goto inst_next;\n *:2 A1 = *:2 A0;\n A1 = A1 + 2;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n##### SMOVB #####\n\n:SMOVB.B is b1_0007=0xb6; b2_0007=0x83 {\n if (R3 == 0) goto inst_next;\n *:1 A1 = *:1 A0;\n A1 = A1 - 1;\n A0 = A0 - 1;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SMOVB.W is b1_0007=0xb6; b2_0007=0x93 {\n if (R3 == 0) goto inst_next;\n *:2 A1 = *:2 A0;\n A1 = A1 - 2;\n A0 = A0 - 2;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n##### SMOVF #####\n\n:SMOVF.B is b1_0007=0xb0; b2_0007=0x83 {\n if (R3 == 0) goto inst_next;\n *:1 A1 = *:1 A0;\n A1 = A1 + 1;\n A0 = A0 + 1;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SMOVF.W is b1_0007=0xb0; b2_0007=0x93 {\n if (R3 == 0) goto inst_next;\n *:2 A1 = *:2 A0;\n A1 = A1 + 2;\n A0 = A0 + 2;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n##### SMOVU #####\n\n:SMOVU.B is b1_0007=0xb8; b2_0007=0x83 {\n local tmp:1 = *:1 A0;\n *:1 A1 = tmp;\n A0 = A0 + 1;\n A1 = A1 + 1;\n if (tmp != 0) goto inst_start;\n}\n\n:SMOVU.W is b1_0007=0xb8; b2_0007=0x93 {\n local tmp:2 = *:2 A0;\n *:2 A1 = tmp;\n A0 = A0 + 2;\n A1 = A1 + 2;\n local tmp0:2 = tmp & 0xff;\n local tmp1:2 = tmp & 0xff00;\n if ((tmp0 != 0) && (tmp1 != 0)) goto inst_start;\n}\n\n##### SOUT #####\n\n:SOUT.B is b1_0007=0xb4; b2_0007=0x83 {\n if (R3 == 0) goto inst_next;\n *:1 A1 = *:1 A0;\n A0 = A0 + 1;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SOUT.W is b1_0007=0xb4; b2_0007=0x93 {\n if (R3 == 0) goto inst_next;\n *:2 A1 = *:2 A0;\n A0 = A0 + 2;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n##### SSTR #####\n\n:SSTR.B is b1_0007=0xb8; b2_0007=0x03 {\n if (R3 == 0) goto inst_next;\n *:1 A1 = R0L;\n A1 = A1 + 1;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n:SSTR.W is b1_0007=0xb8; b2_0007=0x13 {\n if (R3 == 0) goto inst_next;\n *:2 A1 = R0;\n A1 = A1 + 2;\n R3 = R3 - 1;\n goto inst_start;\n}\n\n##### STC #####\n\n# (1) STC dreg24, dst5\n:STC b2_dreg24, dst5L is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=1; b2_0305=0x2 & b2_dreg24) ... & $(DST5L)) {\n dst5L = zext(b2_dreg24);\n}\n\n# (1) STC dreg24, Ax\n:STC b2_dreg24, dst5Ax is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=1; b2_0305=0x2 & b2_dreg24) & $(DST5AX)) {\n dst5Ax = b2_dreg24;\n}\n\n# (2) STC reg16, dst5\n:STC b2_creg16, dst5W is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=1; b2_0305=0x3 & b2_creg16) ... & $(DST5W)) {\n dst5W = b2_creg16;\n}\n\n# (2) STC reg16, Ax\n:STC b2_creg16, dst5Ax is b0_0007=0x1; ((b1_0407=0xd & b1_size_0=1; b2_0305=0x3 & b2_creg16) & $(DST5AX)) {\n dst5Ax = zext(b2_creg16);\n}\n\n# (3) STC reg24, dst5L\n:STC b2_creg24, dst5L is (b1_0407=0xd & b1_size_0=1; b2_0305=0x2 & b2_creg24) ... & $(DST5L) {\n dst5L = zext(b2_creg24);\n}\n\n# (3) STC reg24, Ax\n:STC b2_creg24, dst5Ax is (b1_0407=0xd & b1_size_0=1; b2_0305=0x2 & b2_creg24) & $(DST5AX) {\n dst5Ax = b2_creg24;\n}\n\n##### STCTX #####\n\n:STCTX abs16offset, abs24offset is b1_0007=0xb6; b2_0007=0xd3; abs16offset; imm24_dat & abs24offset {\n\n taskNum:1 = abs16offset; # load task number stored at abs16\n ptr:3 = imm24_dat + (zext(taskNum) * 2); # compute table entry address relative to abs24\n regInfo:1 = *:1 ptr;\n ptr = ptr + 1;\n spCorrect:1 = *:1 ptr;\n\n ptr = SP;\n\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 4;\n *:4 ptr = FB;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 4;\n *:4 ptr = SB;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 4;\n *:4 ptr = A1;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 4;\n *:4 ptr = A0;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R3;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R2;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R1;\n \n regInfo = regInfo << 1;\n if ((regInfo & 0x80) == 0) goto ;\n ptr = ptr - 2;\n *:2 ptr = R0;\n \n SP = SP - zext(spCorrect);\n}\n\n##### STNZ #####\n\n# (1) STNZ.B #imm, dst5\n:STNZ.B srcImm8, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x1f) ... & $(DST5B)); srcImm8 {\n if ($(ZERO) != 0) goto inst_next;\n dst5B = srcImm8;\n}\n\n# (1) STNZ.B #imm, Ax\n:STNZ.B srcImm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x1f) & $(DST5AX)); srcImm8 {\n if ($(ZERO) != 0) goto inst_next;\n dst5Ax = zext(srcImm8);\n}\n\n# (1) STNZ.W #imm, dst5\n:STNZ.W srcImm16, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x1f) ... & $(DST5W)); srcImm16 {\n if ($(ZERO) != 0) goto inst_next;\n dst5W = srcImm16;\n}\n\n# (1) STNZ.W #imm, Ax\n:STNZ.W srcImm16, dst5Ax is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x1f) & $(DST5AX)); srcImm16 {\n if ($(ZERO) != 0) goto inst_next;\n dst5Ax = zext(srcImm16);\n}\n\n##### STZ #####\n\n# (1) STZ.B #imm, dst5\n:STZ.B srcImm8, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x0f) ... & $(DST5B)); srcImm8 {\n if ($(ZERO) == 0) goto inst_next;\n dst5B = srcImm8;\n}\n\n# (1) STZ.B #imm, Ax\n:STZ.B srcImm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x0f) & $(DST5AX)); srcImm8 {\n if ($(ZERO) == 0) goto inst_next;\n dst5Ax = zext(srcImm8);\n}\n\n# (1) STZ.W #imm, dst5\n:STZ.W srcImm16, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x0f) ... & $(DST5W)); srcImm16 {\n if ($(ZERO) == 0) goto inst_next;\n dst5W = srcImm16;\n}\n\n# (1) STZ.W #imm, Ax\n:STZ.W srcImm16, dst5Ax is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x0f) & $(DST5AX)); srcImm16 {\n if ($(ZERO) == 0) goto inst_next;\n dst5Ax = zext(srcImm16);\n}\n\n##### STZX #####\n\n# STZX.B #imm, #imm, dst5\n:STZX.B srcImm8, srcImm8a, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x3f) ... & $(DST5B)); srcImm8; srcImm8a {\n z:1 = $(ZERO);\n dst5B = (z * srcImm8) + (!z * srcImm8a);\n}\n\n# STZX.B #imm, #imm, Ax\n:STZX.B srcImm8, srcImm8a, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x3f) & $(DST5AX)); srcImm8; srcImm8a {\n z:1 = $(ZERO);\n dst5Ax = zext((z * srcImm8) + (!z * srcImm8a));\n}\n\n# STZX.W #imm, #imm, dst5\n:STZX.W srcImm16, srcImm16a, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x3f) ... & $(DST5W)); srcImm16; srcImm16a {\n z:1 = $(ZERO);\n dst5W = (zext(z) * srcImm16) + (zext(!z) * srcImm16a);\n}\n\n# STZX.W #imm, #imm, Ax\n:STZX.W srcImm16, srcImm16a, dst5Ax is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x3f) & $(DST5AX)); srcImm16; srcImm16a {\n z:1 = $(ZERO);\n dst5Ax = zext((zext(z) * srcImm16) + (zext(!z) * srcImm16a));\n}\n\n##### SUB #####\n\n# (1) SUB.B:G #simm, dst\n:SUB^\".B:G\" srcSimm8, dst5B is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B)); srcSimm8 {\n tmp:1 = dst5B;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SUB.B:G #simm, Ax\n:SUB^\".B:G\" srcSimm8, dst5Ax is ((b1_0407=0x8 & b1_size_0=0; b2_0005=0x3e) & $(DST5AX)); srcSimm8 {\n tmp:1 = dst5Ax:1;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) SUB.W:G #simm, dst\n:SUB^\".W:G\" srcSimm16, dst5W is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3e) ... & $(DST5W)); srcSimm16 {\n tmp:2 = dst5W;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SUB.W:G #simm, Ax\n:SUB^\".W:G\" srcSimm16, dst5Ax is ((b1_0407=0x8 & b1_size_0=1; b2_0005=0x3e) & $(DST5AX)); srcSimm16 {\n tmp:2 = dst5Ax:2;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) SUB.L:G #simm, dst\n:SUB^\".L:G\" srcSimm32, dst5L is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x31) ... & $(DST5L)); srcSimm32 {\n tmp:4 = dst5L;\n setSubtractFlags(tmp, srcSimm32);\n tmp = tmp - srcSimm32;\n dst5L = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SUB.L:G #simm, Ax\n:SUB^\".L:G\" srcSimm32, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x31) & $(DST5AX)); srcSimm32 {\n tmp:4 = zext(dst5Ax);\n setSubtractFlags(tmp, srcSimm32);\n tmp = tmp - srcSimm32;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (3) SUB.B:S #simm, dst\n:SUB^\".B:S\" srcSimm8, dst2B is ((b1_0607=0 & b1_0103=7 & b1_size_0=0) ... & dst2B); srcSimm8 {\n tmp:1 = dst2B;\n setSubtractFlags(tmp, srcSimm8);\n tmp = tmp - srcSimm8;\n dst2B = tmp;\n setResultFlags(tmp);\n}\n\n# (3) SUB.W:S #simm, dst\n:SUB^\".W:S\" srcSimm16, dst2W is ((b1_0607=0 & b1_0103=7 & b1_size_0=1) ... & dst2W); srcSimm16 {\n tmp:2 = dst2W;\n setSubtractFlags(tmp, srcSimm16);\n tmp = tmp - srcSimm16;\n dst2W = tmp;\n setResultFlags(tmp);\n}\n\n# (4) SUB.B:G src, dst\n:SUB^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0xa) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... {\n tmp:1 = dst5B_afterSrc5;\n src:1 = src5B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) SUB.B:G src, Ax - Ax destination case\n:SUB^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0xa) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:1 = dst5Ax:1;\n src:1 = src5B;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (4) SUB.W:G src, dst\n:SUB^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0xa) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... {\n tmp:2 = dst5W_afterSrc5;\n src:2 = src5W;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (4) SUB.W:G src, Ax - Ax destination case\n:SUB^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0xa) ... & $(SRC5W) & $(DST5AX) ... {\n tmp:2 = dst5Ax:2;\n src:2 = src5W;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (5) SUB.L:G src, dst\n:SUB^\".L:G\" src5L, dst5L_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x0) ... & $(SRC5L) ... & $(DST5L_AFTER_SRC5) ... {\n tmp:4 = dst5L_afterSrc5;\n src:4 = src5L;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5L_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (5) SUB.L:G src, Ax - Ax destination case\n:SUB^\".L:G\" src5L, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x0) ... & $(SRC5L) & $(DST5AX) ... {\n tmp:4 = zext(dst5Ax);\n src:4 = src5L;\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n##### SUBX #####\n\n# (1) SUBX #simm, dst5\n:SUBX srcSimm8, dst5L is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x11) ... & $(DST5L)); srcSimm8 {\n tmp:4 = dst5L;\n src:4 = sext(srcSimm8);\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5L = tmp;\n setResultFlags(tmp);\n}\n\n# (1) SUBX #simm, Ax\n:SUBX srcSimm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x11) & $(DST5AX)); srcSimm8 {\n tmp:4 = zext(dst5Ax);\n src:4 = sext(srcSimm8);\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n# (2) SUBX src5, dst5\n:SUBX src5B, dst5L_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x0) ... & $(SRC5B) ... & $(DST5L_AFTER_SRC5) ... {\n tmp:4 = dst5L_afterSrc5;\n src:4 = sext(src5B);\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5L_afterSrc5 = tmp;\n setResultFlags(tmp);\n}\n\n# (2) SUBX src5, Ax\n:SUBX src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x0) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:4 = zext(dst5Ax);\n src:4 = sext(src5B);\n setSubtractFlags(tmp, src);\n tmp = tmp - src;\n dst5Ax = tmp:3;\n setResultFlags(tmp);\n}\n\n##### TST #####\n\n# (1) TST.B:G #imm, dst\n:TST^\".B:G\" srcImm8, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x3e) ... & $(DST5B)); srcImm8 {\n tmp:1 = dst5B & srcImm8;\n setResultFlags(tmp);\n}\n\n# (1) TST.W:G #imm, dst\n:TST^\".W:G\" srcImm16, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x3e) ... & $(DST5W)); srcImm16 {\n tmp:2 = dst5W & srcImm16;\n setResultFlags(tmp);\n}\n\n# (2) TST.B:S #imm, dst\n:TST^\".B:S\" srcImm8, dst2B is ((b1_0607=0 & b1_0103=6 & b1_size_0=0) ... & dst2B); srcImm8 {\n tmp:1 = dst2B & srcImm8;\n setResultFlags(tmp);\n}\n\n# (2) TST.W:S #imm, dst\n:TST^\".W:S\" srcImm16, dst2W is ((b1_0607=0 & b1_0103=6 & b1_size_0=1) ... & dst2W); srcImm16 {\n tmp:2 = dst2W & srcImm16;\n setResultFlags(tmp);\n}\n\n# (3) TST.B:G src5, dst5\n:TST^\".B:G\" src5B, dst5B_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=0; b2_0003=0x9) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ...) {\n tmp:1 = dst5B_afterSrc5 & src5B;\n setResultFlags(tmp);\n} \n\n# (3) TST.W:G src5, dst5\n:TST^\".W:G\" src5W, dst5W_afterSrc5 is b0_0007=0x1; ((b1_0707=1 & b1_size_0=1; b2_0003=0x9) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ...) {\n tmp:2 = dst5W_afterSrc5 & src5W;\n setResultFlags(tmp);\n} \n\n##### UND #####\n# Don't implement this \"Undefined\" instruction\n# :UND is b1_0007=0xff\n\n##### WAIT #####\n\n:WAIT is b1_0007=0xb2; b2_0007=0x03 {\n Wait();\n}\n\n##### XCHG #####\n\n# XCHG.B reg8, dst5\n:XCHG.B b2_reg8, dst5B is (b1_0407=0xd & b1_size_0=0; b2_0305=1 & b2_0101=0 & b2_reg8) ... & $(DST5B) {\n tmp:1 = dst5B;\n dst5B = b2_reg8;\n b2_reg8 = tmp;\n}\n\n# XCHG.B Ax, dst5\n:XCHG.B b2_regAx, dst5B is (b1_0407=0xd & b1_size_0=0; b2_0305=1 & b2_0102=1 & b2_regAx) ... & $(DST5B) {\n tmp:1 = dst5B;\n dst5B = b2_regAx:1;\n b2_regAx = zext(tmp);\n}\n\n# XCHG.B reg8, Ax\n:XCHG.B b2_reg8, dst5Ax is (b1_0407=0xd & b1_size_0=0; b2_0305=1 & b2_0101=0 & b2_reg8) & $(DST5AX) {\n tmp:1 = dst5Ax:1;\n dst5Ax = zext(b2_reg8);\n b2_reg8 = tmp;\n}\n\n# XCHG.B Ax, Ax\n:XCHG.B b2_regAx, dst5Ax is (b1_0407=0xd & b1_size_0=0; b2_0305=1 & b2_0102=1 & b2_regAx) & $(DST5AX) {\n tmp:1 = dst5Ax:1;\n dst5Ax = zext(b2_regAx:1);\n b2_regAx = zext(tmp);\n}\n\n# XCHG.W reg16, dst5\n:XCHG.W b2_reg16, dst5W is (b1_0407=0xd & b1_size_0=1; b2_0305=1 & b2_0101=0 & b2_reg16) ... & $(DST5W) {\n tmp:2 = dst5W;\n dst5W = b2_reg16;\n b2_reg16 = tmp;\n}\n\n# XCHG.W Ax, dst5\n:XCHG.W b2_regAx, dst5W is (b1_0407=0xd & b1_size_0=1; b2_0305=1 & b2_0102=1 & b2_regAx) ... & $(DST5W) {\n tmp:2 = dst5W;\n dst5W = b2_regAx:2;\n b2_regAx = zext(tmp);\n}\n\n# XCHG.W reg16, Ax\n:XCHG.W b2_reg16, dst5Ax is (b1_0407=0xd & b1_size_0=1; b2_0305=1 & b2_0101=0 & b2_reg16) & $(DST5AX) {\n tmp:2 = dst5Ax:2;\n dst5Ax = zext(b2_reg16);\n b2_reg16 = tmp;\n}\n\n# XCHG.W Ax, Ax\n:XCHG.W b2_regAx, dst5Ax is (b1_0407=0xd & b1_size_0=1; b2_0305=1 & b2_0102=1 & b2_regAx) & $(DST5AX) {\n tmp:3 = dst5Ax;\n dst5Ax = zext(b2_regAx:2); # dest Ax recieves low 16-bits of src Ax zero extended\n b2_regAx = tmp; # src Ax recieves all 24-bits of dest Ax\n}\n\n##### XOR #####\n\n# (1) XOR.B #imm, dst\n:XOR^\".B:G\" srcImm8, dst5B is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x0e) ... & $(DST5B)); srcImm8 {\n tmp:1 = dst5B ^ srcImm8;\n dst5B = tmp;\n setResultFlags(tmp);\n}\n\n# (1) XOR.B #imm, Ax\n:XOR^\".B:G\" srcImm8, dst5Ax is ((b1_0407=0x9 & b1_size_0=0; b2_0005=0x0e) & $(DST5AX)); srcImm8 {\n tmp:1 = dst5Ax:1 ^ srcImm8;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (1) XOR.W #imm, dst\n:XOR^\".W:G\" srcImm16, dst5W is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x0e) ... & $(DST5W)); srcImm16 {\n tmp:2 = dst5W ^ srcImm16;\n dst5W = tmp;\n setResultFlags(tmp);\n}\n\n# (1) XOR.W #imm, Ax\n:XOR^\".W:G\" srcImm16, dst5Ax is ((b1_0407=0x9 & b1_size_0=1; b2_0005=0x0e) & $(DST5AX)); srcImm16 {\n tmp:2 = dst5Ax:2 ^ srcImm16;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n# (2) XOR.B src5, dst5\n:XOR^\".B:G\" src5B, dst5B_afterSrc5 is (b1_0707=1 & b1_size_0=0; b2_0003=0x9) ... & $(SRC5B) ... & $(DST5B_AFTER_SRC5) ... {\n tmp:1 = dst5B_afterSrc5 ^ src5B;\n dst5B_afterSrc5 = tmp;\n setResultFlags(tmp);\n} \n\n# (2) XOR.B src5, Ax\n:XOR^\".B:G\" src5B, dst5Ax is (b1_0707=1 & b1_size_0=0; b2_0003=0x9) ... & $(SRC5B) & $(DST5AX) ... {\n tmp:1 = dst5Ax:1 ^ src5B;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n} \n\n# (2) XOR.W src5, dst5\n:XOR^\".W:G\" src5W, dst5W_afterSrc5 is (b1_0707=1 & b1_size_0=1; b2_0003=0x9) ... & $(SRC5W) ... & $(DST5W_AFTER_SRC5) ... {\n tmp:2 = dst5W_afterSrc5 ^ src5W;\n dst5W_afterSrc5 = tmp;\n setResultFlags(tmp);\n} \n\n# (2) XOR.W src5, Ax\n:XOR^\".W:G\" src5W, dst5Ax is (b1_0707=1 & b1_size_0=1; b2_0003=0x9) ... & $(SRC5W) & $(DST5AX) ... {\n tmp:2 = dst5Ax:2 ^ src5W;\n dst5Ax = zext(tmp);\n setResultFlags(tmp);\n}\n\n} # end phase=1\n\n" }, { "path": "pypcode/processors/M16C/data/manuals/M16C_60.idx", "content": "@m16csm.pdf\nABS, 55\nADC, 56\nADCF, 57\nADD, 58\nADJNZ, 60\nAND, 61\nBAND, 63\nBCLR, 64\nBM, 65\nBNAND, 66\nBNOR, 67\nBNOT, 68\nBNTST, 69\nBNXOR, 70\nBOR, 71\nBRK, 72\nBSET, 73\nBTST, 74\nBTSTC, 75\nBTSTS, 76\nBXOR, 77\nCMP, 78\nDADC, 80\nDADD, 81\nDEC, 82\nDIV, 83\nDIVU, 84\nDIVX, 85\nDSBB, 86\nDSUB, 87\nENTER, 88\nEXITD, 89\nEXTS, 90\nFCLR, 91\nFSET, 92\nINC, 93\nINT, 94\nINTO, 95\nJ, 96\nJMP, 97\nJMPI, 98\nJMPS, 99\nJSR, 100\nJSRI, 101\nJSRS, 102\nLDC, 103\nLDCTX, 104\nLDE, 105\nLDINTB, 106\nLDIPL, 107\nMOV, 108\nMOVA, 110\nMOVHH, 111\nMOVHL, 111\nMOVLH, 111\nMOVLL, 111\nMUL, 112\nMULU, 113\nNEG, 114\nNOP, 115\nNOT, 116\nOR, 117\nPOP, 119\nPOPC, 120\nPOPM, 121\nPUSH, 122\nPUSHA, 123\nPUSHC, 124\nPUSHM, 125\nREIT, 126\nRMPA, 127\nROLC, 128\nRORC, 129\nROT, 130\nRTS, 131\nSBB, 132\nSBJNZ, 133\nSHA, 134\nSHL, 135\nSMOVB, 136\nSMOVF, 137\nSSTR, 138\nSTC, 139\nSTCTX, 140\nSTE, 141\nSTNZ, 142\nSTZ, 143\nSTZX, 144\nSUB, 145\nTST, 147\nUND, 148\nWAIT, 149\nXCHG, 150\nXOR, 151\n" }, { "path": "pypcode/processors/M16C/data/manuals/M16C_80.idx", "content": "@m16c80.pdf\nABS, 60\nADC, 61\nADCF, 62\nADD, 63\nADDX, 65\nADJNZ, 66\nAND, 67\nBAND, 69\nBCLR, 70\nBITINDEX, 71\nBM, 72\nBNAND, 73\nBNOR, 74\nBNOT, 75\nBNTST, 76\nBNXOR, 77\nBOR, 78\nBRK, 79\nBRK2, 80\nBSET, 81\nBTST, 82\nBTSTC, 83\nBTSTS, 84\nBXOR, 85\nCLIP, 86\nCMP, 87\nCMPX, 89\nDADC, 90\nDADD, 91\nDEC, 92\nDIV, 93\nDIVU, 94\nDIVX, 95\nDSBB, 96\nDSUB, 97\nENTER, 98\nEXITD, 99\nEXTS, 100\nEXTZ, 101\nFLCR, 102\nFREIT, 103\nFSET, 104\nINC, 105\nINDEX, 175\nINT, 107\nINTO, 108\nJ, 109\nJMP, 110\nJMPI, 111\nJMPS, 112\nJSR, 113\nJSRI, 114\nJSRS, 115\nLDC, 116\nLDCTX, 117\nLDIPL, 118\nMAX, 119\nMIN, 120\nMOV, 121\nMOVA, 123\nMOVHH, 124\nMOVHL, 124\nMOVLH, 124\nMOVLL, 124\nMOVX, 125\nMUL, 126\nMULEX, 127\nMULU, 128\nNEG, 129\nNOP, 130\nNOT, 131\nOR, 132\nPOP, 134\nPOPC, 135\nPOPM, 136\nPUSH, 137\nPUSHA, 138\nPUSHC, 139\nPUSHM, 140\nREIT, 141\nRMPA, 142\nROLC, 143\nRORC, 144\nROT, 145\nRTS, 146\nSBB, 147\nSBJNZ, 148\nSC, 149\nSCMPU, 150\nSHA, 151\nSHL, 153\nSIN, 155\nSMOVB, 156\nSMOVF, 157\nSMOVU, 158\nSOUT, 159\nSSTR, 160\nSTC, 161\nSTCTX, 162\nSTNZ, 163\nSTZ, 164\nSTZX, 165\nSUB, 166\nSUBX, 168\nTST, 169\nUND, 171\nWAIT, 172\nXCHG, 173\nXOR, 174\n" }, { "path": "pypcode/processors/M8C/data/languages/m8c.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/M8C/data/languages/m8c.ldefs", "content": "\n\n\n \n Cypress M8C Microcontroller Family\n \n \n\n" }, { "path": "pypcode/processors/M8C/data/languages/m8c.opinion", "content": "\n \n \n \n\n" }, { "path": "pypcode/processors/M8C/data/languages/m8c.pspec", "content": "\n\n\n \n\n\n\n \n \n \n\n\n\n\n\n" }, { "path": "pypcode/processors/M8C/data/languages/m8c.slaspec", "content": "# sleigh specification file for Cypress M8C\n\ndefine endian=big;\ndefine alignment=1;\n\n\ndefine space CODE type=ram_space size=2 default;\ndefine space RAM type=ram_space size=1;\ndefine space BANK0 type=ram_space size=1;\ndefine space BANK1 type=ram_space size=1;\ndefine space register type=register_space size=1;\n\n\n################################################################\n# Registers\n################################################################\n\ndefine register offset=0x00 size=1 [ A X SP F];\ndefine register offset=0x10 size=2 [ PC ];\ndefine register offset=0x30 size=4 [ contextreg ];\n\n# individual bits within Flags Register F\n\n@define XIO\t\t\"F[4,1]\"\t\t# Extend I/O bank select\n@define S\t\t\"F[3,1]\"\t\t# Supervisor code\n@define C\t\t\"F[2,1]\"\t\t# Carry\n@define Z\t\t\"F[1,1]\"\t\t# Zero\n@define IE\t\t\"F[0,1]\"\t\t# Global Interrupt Enable\n\n\ndefine context contextreg\n\tregbank=(0,0)\n;\n\n################################################################\n# Tokens\n################################################################\n\ndefine token opcode (8)\n\top8 = (0,7)\n op71 = (1,7)\t\n op73 = (3,7)\t\n\top74 = (4,7)\n\top20 = (0,2)\n\top10 = (0,1)\n\top0 = (0,0)\n;\n\ndefine token data8 (8)\n\taddr8 = (0,7)\n\timm8 = (0,7)\n\tsimm8 = (0,7) signed\n\trel = (0,7) signed\n\trsb = (4,4)\n\tsign = (7,7)\n;\n\ndefine token data16 (16)\n\timm16 = (0,15)\n\tsimm16 = (0,15) signed\n\taddr16 = (0,15)\n;\n\ndefine token relinstr (16)\n\top4 = (12,15)\n\tsrel12 = (0,11) signed\n;\t\n\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop halt;\ndefine pcodeop nop;\ndefine pcodeop syscall;\n\nmacro push8(val)\n{\n *[RAM]:1 SP = val;\n SP = SP + 1;\n}\n\nmacro push16(val)\n{\n *[RAM]:2 SP = val;\n SP = SP + 2;\n}\n\nmacro pop8(val)\n{\n SP = SP - 1;\n val = *[RAM]:1 SP;\n}\n\nmacro pop16(val)\n{\n SP = SP - 2;\n val = *[RAM]:2 SP;\n}\n\nmacro compflags(op1, op2)\n{\n tmp1:1 = op1;\n tmp2:1 = op2;\n $(C) = (tmp1 < tmp2);\n $(Z) = (tmp1 == tmp2);\n}\n\nmacro testflags(op1, op2)\n{\n $(Z) = ((op1 & op2) == 0);\n}\n\nmacro addflags(op1, op2)\n{\n t1:2 = zext(op1);\n t2:2 = zext(op2);\n tmp:2 = t1 + t2;\n $(C) = tmp > 255;\n $(Z) = (((op1 + op2) & 0xFF) == 0);\n}\n\nmacro resultflags(result)\n{\n $(C) = result s< 0;\n $(Z) = result == 0;\n}\n\nmacro zeroflag(result)\n{\n $(Z) = result == 0;\n}\n\n################################################################\n# Addressing tables\n################################################################\n\nregAorX: A is op0=0 & A { export A; }\nregAorX: X is op0=1 & X { export X; } \nAddr8: addr8 is addr8 { export *[RAM]:1 addr8; } \nSAddr8: addr8 is addr8 { export *[RAM]:1 addr8; } \nXAddr8: [X+simm8] is X & simm8 & sign=0 { ptr:1 = X + simm8; export *[RAM]:1 ptr; }\nXAddr8: [X+simm8] is X & simm8 & sign=1 { ptr:1 = X - ~simm8; export *[RAM]:1 ptr; }\nAddr8Incr: [Addr8]\"++\" is Addr8 { export Addr8; }\n\nRAddr8: addr8 is addr8 & regbank=0 { export *[BANK0]:1 addr8; } \nRAddr8: addr8 is addr8 & regbank=1 { export *[BANK1]:1 addr8; } \nRXAddr8: [X+simm8] is X & simm8 & regbank=0 { ptr:1 = X + simm8; export *[BANK0]:1 ptr; }\nRXAddr8: [X+simm8] is X & simm8 & regbank=1 { ptr:1 = X + simm8; export *[BANK1]:1 ptr; }\n\nImm8:\t\t \"#\"imm8 is imm8 { export *[const]:1 imm8; }\n\nAddr16: addr16 is addr16 { export *:2 addr16; }\nRelAddr: reladdr is srel12 [ reladdr = inst_start + 1 + srel12; ] { export *:2 reladdr; }\nCallAddr: calladdr is srel12 [ calladdr = inst_start + 2 + srel12; ] { export *:2 calladdr; }\nIndexAddr: indexaddr is srel12 [ indexaddr = inst_start + 2 + srel12;] { export *[CODE]:2 indexaddr; } \n\n################################################################\n# Constructors\n################################################################\n\n:ADC A, Imm8\tis op73=0x01 & op20=0x01 & A; Imm8 \n{\n\tA = A + Imm8 + $(C);\n\tresultflags(A);\n}\n\n:ADC A, Addr8\tis op73=0x01 & op20=0x02 & A; Addr8 \n{\n\tA = A + Addr8 + $(C);\n\tresultflags(A);\n}\n\n:ADC A, XAddr8\tis op73=0x01 & op20=0x03 & A; XAddr8 \n{\n\tA = A + XAddr8 + $(C);\n\tresultflags(A);\n}\n\n:ADC Addr8, A\tis op73=0x01 & op20=0x04 & A; Addr8 \n{\n\ttmp:1 = Addr8 + A + $(C);\n\tAddr8 = tmp;\n\tresultflags(tmp);\n}\n\n:ADC XAddr8, A\tis op73=0x01 & op20=0x05 & A; XAddr8 \n{\n\ttmp:1 = XAddr8 + A + $(C);\n\tXAddr8 = tmp;\n\tresultflags(tmp);\n}\n\n:ADC Addr8, Imm8 is op73=0x01 & op20=0x06; Addr8; Imm8 \n{\n\ttmp:1 = Addr8 + Imm8 + $(C);\n\tAddr8 = tmp;\n\tresultflags(tmp);\n\t\n}\n\n:ADC XAddr8, Imm8\tis op73=0x01 & op20=0x07; XAddr8; Imm8 \n{\n\ttmp:1 = XAddr8 + Imm8 + $(C);\n\tXAddr8 = tmp;\n\tresultflags(tmp);\n\t\n}\n\n:ADD A, Imm8\tis op73=0x00 & op20=0x01 & A; Imm8 \n{\n\taddflags(A, Imm8);\n\tA = A + Imm8;\n}\n\n:ADD A, Addr8\tis op73=0x00 & op20=0x02 & A; Addr8 \n{\n\taddflags(A, Addr8);\n\tA = A + Addr8;\n}\n\n:ADD A, XAddr8\tis op73=0x00 & op20=0x03 & A; XAddr8 \n{\n\taddflags(A, XAddr8);\n\tA = A + XAddr8;\n}\n\n:ADD Addr8, A\tis op73=0x00 & op20=0x04 & A; Addr8 \n{\n\taddflags(Addr8, A);\n\tAddr8 = Addr8 + A;\n}\n\n:ADD XAddr8, A\tis op73=0x00 & op20=0x05 & A; XAddr8 \n{\n\taddflags(XAddr8, A);\n\tXAddr8 = XAddr8 + A;\n}\n\n:ADD Addr8, Imm8 is op73=0x00 & op20=0x06; Addr8; Imm8 \n{\n\taddflags(Addr8, Imm8);\n\tAddr8 = Addr8 + Imm8;\n}\n\n:ADD XAddr8, Imm8\tis op73=0x00 & op20=0x07; XAddr8; Imm8 \n{\n\taddflags(XAddr8, Imm8);\n\tXAddr8 = XAddr8 + Imm8;\n}\n\n:ADD SP, simm8\tis op8=0x38 & SP; simm8 \n{\n\tSP = SP + simm8;\n}\n\n:AND A, Imm8\tis op73=0x04 & op20=0x01 & A; Imm8 \n{\n\tA = A & Imm8;\n\tzeroflag(A);\n}\n\n:AND A, Addr8\tis op73=0x04 & op20=0x02 & A; Addr8 \n{\n\tA = A & Addr8;\n\tzeroflag(A);\n}\n\n:AND A, XAddr8\tis op73=0x04 & op20=0x03 & A; XAddr8 \n{\n\tA = A & XAddr8;\n\tzeroflag(A);\n}\n\n:AND Addr8, A\tis op73=0x04 & op20=0x04 & A; Addr8 \n{\n\ttmp:1 = Addr8 & A;\n\tAddr8 = tmp;\n\tzeroflag(tmp);\n}\n\n:AND XAddr8, A\tis op73=0x04 & op20=0x05 & A; XAddr8 \n{\n\ttmp:1 = XAddr8 & A;\n\tXAddr8 = tmp;\n\tzeroflag(tmp);\n}\n\n:AND Addr8, Imm8 is op73=0x04 & op20=0x06; Addr8; Imm8 \n{\n\ttmp:1 = Addr8 & Imm8;\n\tAddr8 = tmp;\n\tzeroflag(tmp);\n}\n\n:AND XAddr8, Imm8\tis op73=0x04 & op20=0x07; XAddr8; Imm8 \n{\n\ttmp:1 = XAddr8 & Imm8;\n\tXAddr8 = tmp;\n\tzeroflag(tmp);\n}\n\n:AND RAddr8, Imm8 is op8=0x41; RAddr8; Imm8 \n{\n\ttmp:1 = RAddr8 & Imm8;\n\tRAddr8 = tmp;\n\tzeroflag(tmp);\n}\n\n:AND RXAddr8, Imm8\tis op8=0x42; RXAddr8; Imm8 \n{\n\ttmp:1 = RXAddr8 & Imm8;\n\tRXAddr8 = tmp;\n\tzeroflag(tmp);\n}\n\n:AND F, imm8 is op8=0x70 & F; imm8 & rsb\n\t[ regbank = regbank & rsb; globalset(inst_next, regbank); ]\n{\n\tF = F & imm8;\n}\n\n:ASL A\tis op8=0x64 & A\n{\n\tA = A << 1:1;\n}\n\n:ASL Addr8\tis op8=0x65; Addr8\n{\n\tAddr8 = Addr8 << 1:1;\n}\n\n:ASL XAddr8\tis op8=0x66; XAddr8\n{\n\tXAddr8 = XAddr8 << 1:1;\n}\n\n:ASR A\tis op8=0x67 & A\n{\n\tA = A >> 1:1;\n}\n\n:ASR Addr8\tis op8=0x68; Addr8\n{\n\tAddr8 = Addr8 >> 1:1;\n}\n\n:ASR XAddr8\tis op8=0x69; XAddr8\n{\n\tXAddr8 = XAddr8 >> 1:1;\n}\n\n:CALL CallAddr is op4=0x9 & CallAddr\n{\n\tret:2 = inst_next;\n\tpush16(ret);\n\tcall CallAddr;\n}\n\n:CMP A, Imm8\tis op8=0x39 & A; Imm8\n{\n\tcompflags(A, Imm8);\n}\n\n:CMP A, Addr8\tis op8=0x3A & A; Addr8\n{\n\t\n\tcompflags(A, Addr8);\n}\n\n:CMP A, XAddr8\tis op8=0x3B & A; XAddr8 \n{\n\tcompflags(A, XAddr8);\n}\n\n:CMP Addr8, Imm8 is op8=0x3C; Addr8; Imm8\n{\n\tcompflags(Addr8, Imm8);\n}\n\n:CMP XAddr8, Imm8 is op8=0x3D; XAddr8; Imm8\n{\n\ttemp:1 = XAddr8;\n\tcompflags(temp, Imm8);\n}\n\n:CPL A\t\tis op8=0x73 & A\n{\n\tA = ~A;\n}\n\n:DEC regAorX\tis op71=0x3C & regAorX\n{\n\tregAorX = regAorX - 1:1;\n\tresultflags(regAorX);\n}\n\n:DEC Addr8\tis op71=0x3D & op0=0; Addr8\n{\n\tAddr8 = Addr8 - 1:1;\n\tresultflags(Addr8);\n}\n\n:DEC XAddr8\tis op71=0x3D & op0=1; XAddr8\n{\n\tXAddr8 = XAddr8 - 1:1;\n\tresultflags(XAddr8);\n}\n\n:HALT\t\tis op8=0x30\n{\n\thalt();\n}\n\n:INC regAorX\tis op71=0x3A & regAorX\n{\n\taddflags(regAorX, 1:1);\n\tregAorX = regAorX + 1:1;\n}\n\n:INC Addr8\tis op71=0x3B & op0=0; Addr8\n{\n\taddflags(Addr8, 1:1);\n\tAddr8 = Addr8 + 1:1;\n}\n\n:INC XAddr8\tis op71=0x3B & op0=1; XAddr8\n{\n\taddflags(XAddr8, 1:1);\n\tXAddr8 = XAddr8 + 1:1;\n}\n\n:INDEX\tIndexAddr\tis op4=0xF & IndexAddr & srel12\n{\n ptr:2 = inst_start + 2 + srel12 + zext(A);\n\tA = *[CODE]:1 ptr;\n}\n\n:JACC RelAddr\tis op4=0xE & RelAddr\n{\n\ttmp:2 = sext(A);\n\ttarget:2 = RelAddr + sext(A);\n\tgoto [target];\n}\n\n:JC RelAddr\t\tis op4=0xC & RelAddr\n{\n\tif ($(C) != 0) goto RelAddr;\n}\n\n:JMP RelAddr\tis op4=0x8 & RelAddr\n{\n\tgoto RelAddr;\n}\n\n:JNC RelAddr\tis op4=0xD & RelAddr\n{\n\tif ($(C) == 0) goto RelAddr;\n}\n\n:JNZ RelAddr \tis op4=0xB & RelAddr\n{\n\tif ($(Z) == 0) goto RelAddr;\n}\n\n:JZ RelAddr\t\tis op4=0xA & RelAddr\n{\n\tif ($(Z) == 1) goto RelAddr;\n}\n\n:LCALL Addr16\tis op8=0x7C; Addr16\n{\n\tret:2 = inst_next;\n\tpush16(ret);\n\tcall Addr16;\n}\n\n:LJMP Addr16\tis op8=0x7D; Addr16\n{\n\tgoto Addr16;\n}\n\n:MOV X, SP\t\tis op8=0x4F & X & SP\n{\n\tX = SP;\n}\n\n:MOV A, Imm8\tis op8=0x50 & A; Imm8\n{\n\tA = Imm8;\n\tzeroflag(A);\n}\n\n:MOV A, Addr8\tis op8=0x51 & A; Addr8\n{\n\tA = Addr8;\n\tzeroflag(A);\n}\n\n:MOV A, XAddr8 \tis op8=0x52 & A; XAddr8\n{\n\tA = XAddr8;\t\n\tzeroflag(A);\n}\n\n:MOV Addr8, A\tis op8=0x53 & A; Addr8\n{\n\tAddr8 = A;\n}\n\n:MOV XAddr8, A\tis op8=0x54 & A; XAddr8\n{\n\tXAddr8 = A;\n}\n\n:MOV Addr8, Imm8 is op8=0x55; Addr8; Imm8\n{\n\tAddr8 = Imm8;\n}\n\n:MOV XAddr8, Imm8 is op8=0x56; XAddr8; Imm8\n{\n\tXAddr8 = Imm8;\n}\n\n:MOV X, Imm8\tis op8=0x57 & X; Imm8\n{\n\tX = Imm8;\n}\n\n:MOV X, Addr8\tis op8=0x58 & X; Addr8\n{\n\tX = Addr8;\n}\n\n:MOV X, XAddr8 \tis op8=0x59 & X; XAddr8\n{\n\tX = XAddr8;\t\n}\n\n:MOV Addr8, X\tis op8=0x5A & X; Addr8\n{\n\tAddr8 = X;\n}\n\n:MOV A, X \t\tis op8=0x5B & A & X\n{\n\tA = X;\n\tzeroflag(A);\n}\n\n:MOV X, A \t\tis op8=0x5C & A & X\n{\n\tX = A;\n}\n\n:MOV A, RAddr8\tis op8=0x5D & A; RAddr8\n{\n\tA = RAddr8;\n\tzeroflag(A);\n}\n\n:MOV A, RXAddr8 \tis op8=0x5E & A; RXAddr8\n{\n\tA = RXAddr8;\t\n\tzeroflag(A);\n}\n\n:MOV Addr8, SAddr8\tis op8=0x5F; Addr8; SAddr8\n{\n\tAddr8 = SAddr8;\n}\n\n:MOV RAddr8, A\tis op8=0x60 & A; RAddr8\n{\n\tRAddr8 = A;\n}\n\n:MOV RXAddr8, A is op8=0x61 & A; RXAddr8\n{\n\tRXAddr8 = A;\t\n}\n\n:MOV RAddr8, Imm8\tis op8=0x62; RAddr8; Imm8\n{\n\tRAddr8 = Imm8;\n}\n\n:MOV RXAddr8, Imm8 is op8=0x63; RXAddr8; Imm8\n{\n\tRXAddr8 = Imm8;\t\n}\n\n:MVI A, Addr8Incr \tis op8=0x3E & A; Addr8Incr\n{\n\tptr:1 = Addr8Incr;\n\tA = *[RAM]:1 ptr;\n\tzeroflag(A);\n\tAddr8Incr = ptr + 1:1;\n}\n\n:MVI Addr8Incr, A\tis op8=0x3F & A; Addr8Incr\n{\n\tptr:1 = Addr8Incr;\n\t*[RAM]:1 ptr = A;\n\tAddr8Incr = ptr + 1:1;\n}\n\n:NOP\t\tis op8=0x40\n{\n\tnop();\n}\n\n:OR A, Imm8\tis op73=0x05 & op20=0x01 & A; Imm8 \n{\n\tA = A | Imm8;\n\tzeroflag(A);\n}\n\n:OR A, Addr8\tis op73=0x05 & op20=0x02 & A; Addr8 \n{\n\tA = A | Addr8;\n\tzeroflag(A);\n}\n\n:OR A, XAddr8\tis op73=0x05 & op20=0x03 & A; XAddr8 \n{\n\tA = A | XAddr8;\n\tzeroflag(A);\n}\n\n:OR Addr8, A\tis op73=0x05 & op20=0x04 & A; Addr8 \n{\n\ttmp:1 = Addr8 | A;\n\tzeroflag(tmp);\n\tAddr8 = tmp;\n}\n\n:OR XAddr8, A\tis op73=0x05 & op20=0x05 & A; XAddr8 \n{\n\ttmp:1 = XAddr8 | A;\n\tzeroflag(tmp);\n\tXAddr8 = tmp;\n}\n\n:OR Addr8, Imm8 is op73=0x05 & op20=0x06; Addr8; Imm8 \n{\n\ttmp:1 = Addr8 | Imm8;\n\tzeroflag(tmp);\n\tAddr8 = tmp;\n}\n\n:OR XAddr8, Imm8\tis op73=0x05 & op20=0x07; XAddr8; Imm8 \n{\n\ttmp:1 = XAddr8 | Imm8;\n\tzeroflag(tmp);\n\tXAddr8 = tmp;\n}\n\n:OR RAddr8, Imm8 is op8=0x43; RAddr8; Imm8 \n{\n\ttmp:1 = RAddr8 | Imm8;\n\tzeroflag(tmp);\n\tRAddr8 = tmp;\n}\n\n:OR RXAddr8, Imm8\tis op8=0x44; RXAddr8; Imm8 \n{\n\ttmp:1 = RXAddr8 | Imm8;\n\tzeroflag(tmp);\n\tRXAddr8 = tmp;\n}\n\n:OR F, imm8 is op8=0x71 & F; imm8 & rsb\n\t[ regbank = regbank | rsb; globalset(inst_next, regbank); ]\n{\n\tF = F | imm8;\n}\n\n:POP X\t\tis op8=0x20 & X\n{\n\tpop8(X);\n}\n\n:POP A\t\tis op8=0x18 & A\n{\n\tpop8(A);\n}\n\n:PUSH X\t\tis op8=0x10 & X\n{\n\tpush8(X);\n}\n\n:PUSH A\t\tis op8=0x08 & A\n{\n\tpush8(A);\n}\n\n:RETI\t\tis op8=0x7E\n{\n\tpc:2 = 0;\n\tpop16(pc);\n\treturn[pc];\n}\n\n:RET\t\tis op8=0x7F\n{\n\tpc:2 = 0;\n\tpop16(pc);\n\treturn[pc];\n}\n\n:RLC A\tis op8=0x6A & A\n{\n\tc:1 = (A & 0x80) >> 7:1;\n\tA = (A << 1:1) | $(C);\n\t$(C) = c;\n}\n\n:RLC Addr8 is op8=0x6B; Addr8\n{\n tmp:1 = Addr8;\n\tc:1 = (tmp & 0x80) >> 7:1;\n\tAddr8 = (tmp << 1) | $(C);\n\t$(C) = c;\n}\n\n:RLC XAddr8 is op8=0x6C; XAddr8\n{\n tmp:1 = XAddr8;\n\tc:1 = (tmp & 0x80) >> 7:1;\n\tXAddr8 = (tmp << 1) | $(C);\n\t$(C) = c;\n}\n\n:ROMX\t\tis op8=0x28\n{\n\tmsb:2 = zext(A) << 8:1;\n\tptr:2 = msb | zext(X);\n\tA = *[CODE]:1 ptr;\n\tzeroflag(A);\n}\n\n:RRC A\tis op8=0x6D & A\n{\n\tc:1 = A & 0x01:1;\n\tA = (A >> 1) | ($(C) << 7:1);\n\t$(C) = c;\n}\n\n:RRC Addr8\tis op8=0x6E; Addr8\n{\n\ttmp:1 = Addr8;\n\tc:1 = tmp & 0x01:1;\n\tAddr8 = (tmp >> 1:1) | ($(C) << 7:1);\n\t$(C) = c;\n}\n\n:RRC XAddr8\tis op8=0x6F; XAddr8\n{\n\ttmp:1 = XAddr8;\n\tc:1 = tmp & 0x01;\n\tXAddr8 = (tmp >> 1:1) | ($(C) << 7:1);\n\t$(C) = c;\n}\n\n:SBB A, Imm8\tis op73 = 0x03 & op20=0x01 & A; Imm8 \n{\n\tA = A - (Imm8 + $(C));\n\tresultflags(A);\n}\n\n:SBB A, Addr8\tis op73 = 0x03 & op20=0x02 & A; Addr8 \n{\n\tA = A - (Addr8 + $(C));\n\tresultflags(A);\n}\n\n:SBB A, XAddr8\tis op73 = 0x03 & op20=0x03 & A; XAddr8 \n{\n\tA = A - (XAddr8 + $(C));\n\tresultflags(A);\n}\n\n:SBB Addr8, A\tis op73 = 0x03 & op20=0x04 & A; Addr8 \n{\n\ttmp:1 = Addr8 - (A + $(C));\n\tresultflags(tmp);\n\tAddr8 = tmp;\n}\n\n:SBB XAddr8, A\tis op73 = 0x03 & op20=0x05 & A; XAddr8 \n{\n\ttmp:1 = XAddr8 - (A + $(C));\n\tresultflags(tmp);\n\tXAddr8 = tmp;\n}\n\n:SBB Addr8, Imm8 is op73 = 0x03 & op20=0x06; Addr8; Imm8 \n{\n\ttmp:1 = Addr8 - (Imm8 + $(C));\n\tresultflags(tmp);\n\tAddr8 = tmp;\n}\n\n:SBB XAddr8, Imm8\tis op73 = 0x03 & op20=0x07; XAddr8; Imm8 \n{\n\tlocal tmp = XAddr8 - (Imm8 + $(C));\n\tresultflags(tmp);\n\tXAddr8 = tmp;\n}\n\n:SSC\t\tis op8=0x00 \n{\n\tsyscall(A);\n}\n\n:SUB A, Imm8\tis op73 = 0x02 & op20=0x01 & A; Imm8 \n{\n\tA = A - Imm8;\n\tresultflags(A);\n}\n\n:SUB A, Addr8\tis op73 = 0x02 & op20=0x02 & A; Addr8 \n{\n\tA = A - Addr8;\n\tresultflags(A);\n}\n\n:SUB A, XAddr8\tis op73 = 0x02 & op20=0x03 & A; XAddr8 \n{\n\tA = A - XAddr8;\n\tresultflags(A);\n}\n\n:SUB Addr8, A\tis op73 = 0x02 & op20=0x04 & A; Addr8 \n{\n\ttmp:1 = Addr8 - A;\n\tresultflags(tmp);\n\tAddr8 = tmp;\n}\n\n:SUB XAddr8, A\tis op73 = 0x02 & op20=0x05 & A; XAddr8 \n{\n\ttmp:1 = XAddr8 - A;\n\tresultflags(tmp);\n\tXAddr8 = tmp;\n}\n\n:SUB Addr8, Imm8 is op73 = 0x02 & op20=0x06; Addr8; Imm8 \n{\n\ttmp:1 = Addr8 - Imm8;\n\tresultflags(tmp);\n\tAddr8 = tmp;\n}\n\n:SUB XAddr8, Imm8\tis op73 = 0x02 & op20=0x07; XAddr8; Imm8 \n{\n\ttmp:1 = XAddr8 - Imm8;\n\tresultflags(tmp);\n\tXAddr8 = tmp;\n}\n\n:SWAP A, X\tis op8=0x4B & A & X\n{\n\ttmp:1 = A;\n\tA = X;\n\tX = tmp;\n}\n\n:SWAP regAorX, Addr8\tis op71=0x26 & regAorX; Addr8\n{\n\ttmp:1 = regAorX;\n\tregAorX = Addr8;\n\tAddr8 = tmp;\n}\n\n:SWAP A, SP\tis op8=0x4E & A & SP\n{\n\ttmp:1 = A;\n\tA = SP;\n\tSP = tmp;\n}\n\n:TST Addr8, Imm8 is op8=0x47; Addr8; Imm8\n{\n\ttmp:1 = Addr8;\n\ttestflags(tmp, Imm8);\n}\n\n:TST XAddr8, Imm8 is op8=0x48; XAddr8; Imm8\n{\n\ttmp:1 = XAddr8;\n\ttestflags(tmp, Imm8);\n}\n\n:TST RAddr8, Imm8 is op8=0x49; RAddr8; Imm8\n{\n\ttmp:1 = RAddr8;\n\ttestflags(tmp, Imm8);\n}\n\n:TST RXAddr8, Imm8 is op8=0x4A; RXAddr8; Imm8\n{\n\ttmp:1 = RXAddr8;\n\ttestflags(tmp, Imm8);\n}\n\n:XOR A, Imm8\tis op73=0x06 & op20=0x01 & A; Imm8 \n{\n\tA = A ^ Imm8;\n\tzeroflag(A);\n}\n\n:XOR A, Addr8\tis op73=0x06 & op20=0x02 & A; Addr8 \n{\n\tA = A ^ Addr8;\n\tzeroflag(A);\n}\n\n:XOR A, XAddr8\tis op73=0x06 & op20=0x03 & A; XAddr8 \n{\n\tA = A ^ XAddr8;\n\tzeroflag(A);\n}\n\n:XOR Addr8, A\tis op73=0x06 & op20=0x04 & A; Addr8 \n{\n\ttmp:1 = Addr8 ^ A;\n\tzeroflag(Addr8);\n\tAddr8 = tmp;\n}\n\n:XOR XAddr8, A\tis op73=0x06 & op20=0x05 & A; XAddr8 \n{\n\ttmp:1 = XAddr8 ^ A;\n\tzeroflag(tmp);\n\tXAddr8 = tmp;\n}\n\n:XOR Addr8, Imm8 is op73=0x06 & op20=0x06; Addr8; Imm8 \n{\n\ttmp:1 = Addr8 ^ Imm8;\n\tzeroflag(tmp);\n\tAddr8 = tmp;\n}\n\n:XOR XAddr8, Imm8\tis op73=0x06 & op20=0x07; XAddr8; Imm8 \n{\n\ttmp:1 = XAddr8 ^ Imm8;\n\tzeroflag(tmp);\n\tXAddr8 = tmp;\n}\n\n:XOR RAddr8, Imm8 is op8=0x45; RAddr8; Imm8 \n{\n\ttmp:1 = RAddr8 ^ Imm8;\n\tzeroflag(tmp);\n\tRAddr8 = tmp;\n}\n\n:XOR RXAddr8, Imm8\tis op8=0x46; RXAddr8; Imm8 \n{\n\ttmp:1 = RXAddr8 ^ Imm8;\n\tzeroflag(tmp);\n\tRXAddr8 = tmp;\n}\n\n:XOR F, imm8 is op8=0x72 & F; imm8 & rsb\n\t[ regbank = regbank ^ rsb; globalset(inst_next, regbank); ]\n{\n\ttmp:1 = F ^ imm8;\n\tresultflags(tmp);\n\tF = tmp;\n}\n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6800.ldefs", "content": "\n\n \n 6809 Microprocessor\n \n \n \n\t\n\t\n\t\n \n \n Hitachi 6309 Microprocessor, extension of 6809, 6309 addressing modes, missing many instructions\n \n \n \n" }, { "path": "pypcode/processors/MC6800/data/languages/6805.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6805.ldefs", "content": "\n\n \n 6805 Microcontroller Family\n \n\t\n \n" }, { "path": "pypcode/processors/MC6800/data/languages/6805.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6805.slaspec", "content": "# sleigh specification file for Motorola 6805\ndefine endian=big;\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=2 default;\ndefine space register type=register_space size=1;\n\ndefine register offset=0x00 size=1 [ A X ];\ndefine register offset=0x20 size=2 [ PC SP];\ndefine register offset=0x30 size=1 [H I N Z C];\t# status bits\n\ndefine RAM offset=0x3ffc size=2 [ SWI_VECTOR ];\n#TOKENS\n\ndefine token opbyte (8)\n op = (0,7)\n op4_7\t= (4,7)\n op4_6\t= (4,6)\n n\t\t= (1,3)\n bit_0\t= (0,0)\n;\n\ndefine token data8 (8)\n imm8\t\t= (0,7)\n rel\t\t= (0,7) signed\n;\n\ndefine token data (16)\n\timm16 = (0,15)\n;\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop readIRQ;\n\n################################################################\nREL: reloc\t\tis rel\t[ reloc = inst_next + rel; ] { export *:2 reloc; } \n\nOP1: \"#\"imm8\tis op4_6=2; imm8\t\t{ tmp:1 = imm8; export tmp; }\nOP1: imm8 \t\tis op4_6=3; imm8\t\t{ export *:1 imm8; }\nOP1: imm16 \t\tis op4_6=4; imm16 \t{ export *:1 imm16; }\nOP1: imm16,X \tis op4_6=5 & X; imm16 \t{ tmp:2 = imm16 + zext(X); export *:1 tmp; }\nOP1: imm8,X \tis op4_6=6 & X; imm8 \t{ tmp:2 = imm8 + zext(X); export *:1 tmp; }\nOP1: \",\"X\t\t\tis op4_6=7 & X\t\t\t{ tmp:2 = zext(X); export *:1 tmp; }\n\nADDR: imm8 \t\t\tis op4_6=3; imm8\t\t{ export *:1 imm8; }\nADDR: imm16 \t\tis op4_6=4; imm16 \t{ export *:1 imm16; }\nADDRI: imm16,X \tis op4_6=5 & X; imm16 \t{ tmp:2 = imm16 + zext(X); export *:1 tmp; }\nADDRI: imm8,X \tis op4_6=6 & X; imm8 \t{ tmp:2 = imm8 + zext(X); export *:1 tmp; }\nADDRI: \",\"X\t\t\tis op4_6=7 & X\t\t\t{ tmp:2 = zext(X); export *:1 tmp; }\n\n\nDIRECT: imm8\tis imm8\t\t\t\t\t{ export *:1 imm8; }\n\n:ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1\n{\n\t local op1 = OP1;\n\n\t# compute half carry\n\tlocal halfop1 = op1 & 0xF;\t\n\tlocal halfA = A & 0xF;\n\tlocal halfresult = halfop1 + halfA + C;\n\tH = (halfresult >> 4) & 1;\n\n\tlocal result = A + op1;\n\tlocal tmpC = carry(A, op1);\n\n\tA = result + C;\n\tC = carry(result, C);\n\tC = C | tmpC;\n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n:ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1\n{ \n\tlocal op1 = OP1;\n\n\t# compute half carry\n\tlocal halfop1 = op1 & 0xF;\t\n\tlocal halfA = A & 0xF;\n\tlocal halfresult = halfop1 + halfA;\n\tH = (halfresult >> 4) & 1;\n\n\tC = carry(A, op1);\n\tA = A + op1; \n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n\n:AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1\n{ \n\tA = A & OP1; \n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n\n:ASLA\t\tis op=0x48 \n{\n\tC = A >> 7;\n\tA = A << 1;\n\tZ = (A == 0);\n\tN = (A s< 0);\t\n}\n:ASLX\t\tis op=0x58 \n{\n\tC = X >> 7;\n\tX = X << 1;\n\tZ = (X == 0);\n\tN = (X s< 0);\t\n}\n:ASL OP1\tis (op=0x38 | op=0x68 | op=0x78) ... & OP1 \n{\n\tlocal tmp = OP1;\n\tC = tmp >> 7;\n\ttmp = tmp << 1;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = (tmp s< 0);\t\n}\n:ASRA\t\tis op=0x47 \n{\n\tC = A & 1;\n\tA = A s>> 1;\n\tZ = (A == 0);\n\tN = (A s< 0);\t\n}\n:ASRX\t\tis op=0x57 \n{\n\tC = X & 1;\n\tX = X s>> 1;\n\tZ = (X == 0);\n\tN = (X s< 0);\t\n}\n:ASR OP1\tis (op=0x37 | op=0x67 | op=0x77) ... & OP1 \n{\n\tlocal tmp = OP1;\n\tC = tmp & 1;\n\ttmp = tmp s>> 1;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = (tmp s< 0);\t\n}\n\n:BCC REL\tis op=0x24;REL\n{\n\tif (C == 0) goto REL;\n}\n\n:BCLR n,DIRECT\tis op4_7=1 & bit_0=1 & n; DIRECT {\n\tlocal mask = ~(1 << n);\n\tDIRECT = DIRECT & mask;\n}\n:BCS REL\tis op=0x25;REL\n{\n\tif (C) goto REL;\n}\n:BEQ REL\tis op=0x27;REL\n{\n\tif (Z) goto REL;\n}\n:BHCC REL\tis op=0x28;REL\n{\n\tif (H == 0) goto REL;\n}\n:BHCS REL\tis op=0x29;REL\n{\n\tif (H) goto REL;\n}\n:BHI REL\tis op=0x22;REL\n{\n\tlocal tmp = C || Z;\n\tif (tmp == 0) goto REL;\n}\n\n#:BHS REL\tis op=0x24;REL\t\tSee BCC\n\n:BIH REL\tis op=0x2F;REL\n{\n\ttmp:1 = readIRQ();\n\tif (tmp) goto REL;\n}\n:BIL REL\tis op=0x2E;REL\n{\n\ttmp:1 = readIRQ();\n\tif (tmp == 0) goto REL;\n}\n:BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1\n{\n\tlocal result = A & OP1;\n\tZ = (result == 0);\n\tN = (result s< 0);\n}\n#:BLO REL\tis op=0x25;REL\t\tsee BCS\n\n:BLS REL\tis op=0x23;REL\n{\n\tlocal tmp = C || Z;\n\tif (tmp) goto REL;\n}\n\n:BMC REL\tis op=0x2C;REL\n{\n\tif (I == 0) goto REL;\n}\n:BMI REL\tis op=0x2B;REL\n{\n\tif (N) goto REL;\n}\n:BMS REL\tis op=0x2D;REL\n{\n\tif (I) goto REL;\n}\n:BNE REL\tis op=0x26;REL\n{\n\tif (Z == 0) goto REL;\n}\n:BPL REL\tis op=0x2A;REL\n{\n\tif (N == 0) goto REL;\n}\n:BRA REL\tis op=0x20;REL\n{\n\tgoto REL;\n}\n\n:BRN REL\tis op=0x21;REL\n{\n}\n\n:BRCLR n,DIRECT,REL\t\tis op4_7=0 & bit_0=1 & n; DIRECT; REL\n{\n\tlocal mask = (1 << n);\n\tlocal result = DIRECT & mask;\n\tif (result == 0) goto REL;\n}\n\n:BRSET n,DIRECT,REL\t\tis op4_7=0 & bit_0=0 & n; DIRECT; REL\n{\n\tlocal mask = (1 << n);\n\tlocal result = DIRECT & mask;\n\tif (result != 0) goto REL;\n}\n\n:BSET n,DIRECT\tis op4_7=1 & bit_0=0 & n; DIRECT {\n\tlocal mask = (1 << n);\n\tDIRECT = DIRECT | mask;\n}\n\n:BSR REL\t\tis op=0xAD; REL \n{\n\tSP=SP-1;\n\t*:2 SP = inst_next;\n\tSP=SP-1; \n\tcall REL;\n}\n\n:CLC\t\tis op=0x98\n{\n\tC = 0;\n}\n\n:CLI\t\tis op=0x9A\n{\n\tI = 0;\n}\n:CLRA\t\tis op=0x4F \n{\n\tA = 0;\n\tZ = 1;\n\tN = 0;\n}\n:CLRX\t\tis op=0x5F \n{\n\tX = 0;\n\tZ = 1;\n\tN = 0;\n}\n:CLR OP1\tis (op=0x3F | op=0x6F | op=0x7F) ... & OP1 \n{\n\tOP1 = 0;\n\tZ = 1;\n\tN = 0;\n}\n:CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tlocal tmp = A - op1;\n\tZ = tmp == 0;\n\tN = tmp s< 0;\n\tC = (A < op1);\n}\n\n:COMA\t\tis op=0x43 \n{\n\tA = ~A;\n\tZ = (A == 0);\n\tN = (A s< 0);\n\tC = 1;\n}\n:COMX\t\tis op=0x53 \n{\n\tX = ~X;\n\tZ = (X == 0);\n\tN = (X s< 0);\n\tC = 1;\n}\n:COM OP1\tis (op=0x33 | op=0x63 | op=0x73) ... & OP1 \n{\n\tlocal tmp = ~OP1;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = (tmp s< 0);\n\tC = 1;\n}\n:CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tlocal tmp = X - op1;\n\tZ = tmp == 0;\n\tN = tmp s< 0;\n\tC = (X < op1);\n}\n:DECA\t\tis op=0x4A \n{\n\tA = A - 1;\n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n:DECX\t\tis op=0x5A \n{\n\tX = X - 1;\n\tZ = (X == 0);\n\tN = (X s< 0);\n}\n:DEC OP1\tis (op=0x3A | op=0x6A | op=0x7A) ... & OP1 \n{\n\tlocal tmp = OP1 - 1;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = (tmp s< 0);\n}\n:EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tA = A ^ op1;\n\tZ = A == 0;\n\tN = A s< 0;\n}\n:INCA\t\tis op=0x4C \n{\n\tA = A + 1;\n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n:INCX\t\tis op=0x5C \n{\n\tX = X + 1;\n\tZ = (X == 0);\n\tN = (X s< 0);\n}\n:INC OP1\tis (op=0x3C | op=0x6C | op=0x7C) ... & OP1 \n{\n\tlocal tmp = OP1 + 1;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = (tmp s< 0);\n}\n:JMP ADDR\tis (op=0xBC | op=0xCC) ... & ADDR\n{\n\tgoto ADDR;\n}\n\n:JMP ADDRI\tis (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI\n{\n\tgoto [ADDRI];\n}\n\n\n:JSR ADDR\tis (op=0xBD | op=0xCD) ... & ADDR\n{\n\t*:2 (SP-1) = inst_next;\n\tSP=SP-2; \n\tcall ADDR;\n}\n:JSR ADDRI\tis (op=0xDD | op=0xED | op=0xFD) ... & ADDRI\n{\n\t*:2 (SP-1) = inst_next;\n\tSP=SP-2; \n\tcall [ADDRI];\n}\n\n:LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1\n{ \n\tA = OP1;\n\tZ = A == 0;\n\tN = A s< 0;\n}\n\n:LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1\n{ \n\tX = OP1;\n\tZ = X == 0;\n\tN = X s< 0;\n}\n\n## Logical Shift left is same as arithmetic shift left\n#:LSLA\t\tis op=0x48 \n#:LSLX\t\tis op=0x58 \n#:LSL OP1\tis (op=0x38 | op=0x68 | op=0x78) ... & OP1 \n:LSRA\t\tis op=0x44 \n{\n\tC = A & 1;\n\tA = A >> 1;\n\tZ = (A == 0);\n\tN = 0;\t\n}\n:LSRX\t\tis op=0x54 \n{\n\tC = X & 1;\n\tX = X >> 1;\n\tZ = (X == 0);\n\tN = 0;\t\n}\n:LSR OP1\tis (op=0x34 | op=0x64 | op=0x74) ... & OP1 \n{\n\tlocal tmp = OP1;\n\tC = tmp & 1;\n\ttmp = tmp >> 1;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = 0;\t\n}\n\n:MUL\t\tis op=0x42\n{\n\top1:2 = zext(A);\n\top2:2 = zext(X);\n\tlocal result = op1 * op2;\n\tA = result:1;\n\tresult = result >> 8;\n\tX = result:1;\n}\n\n:NEGA\t\tis op=0x40 \n{\n\tC = A != 0;\n\tA = -A;\n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n:NEGX\t\tis op=0x50 \n{\n\tC = X != 0;\n\tX = -X;\n\tZ = (X == 0);\n\tN = (X s< 0);\n}\n:NEG OP1\tis (op=0x30 | op=0x60 | op=0x70) ... & OP1 \n{\n\tlocal op1 = OP1;\n\tC = op1 != 0;\n\tOP1 = -op1;\n\tZ = (op1 == 0);\n\tN = (op1 s< 0);\n}\n\n:NOP\t\tis op = 0x9D\n{\n}\n\n:ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1\n{ \n\tA = A | OP1; \n\tZ = (A == 0);\n\tN = (A s< 0);\n}\n\n:ROLA\t\tis op=0x49 \n{\n\tlocal tmp = C ;\n\tC = A >> 7;\n\tA = A << 1;\n\tA = A | tmp;\n\tZ = (A == 0);\n\tN = (A s< 0);\t\n}\n:ROLX\t\tis op=0x59 \n{\n\tlocal tmp = C;\n\tC = X >> 7;\n\tX = X << 1;\n\tX = X | tmp;\n\tZ = (X == 0);\n\tN = (X s< 0);\t\n}\n:ROL OP1\tis (op=0x39 | op=0x69 | op=0x79) ... & OP1 \n{\n\tlocal tmpC = C;\n\tlocal op1 = OP1;\n\tC = op1 >> 7;\n\tlocal result = op1 << 1;\n\tresult = result | tmpC;\n\tOP1 = result;\n\tZ = (result == 0);\n\tN = (result s< 0);\t\n}\n:RORA\t\tis op=0x46 \n{\n\tlocal tmpC = C << 7;\n\tC = A & 1;\n\tA = A s>> 1;\n\tA = A | tmpC;\n\tZ = (A == 0);\n\tN = (A s< 0);\t\n}\n:RORX\t\tis op=0x56 \n{\n\tlocal tmpC = C << 7;\n\tC = X & 1;\n\tX = X s>> 1;\n\tX = X | tmpC;\n\tZ = (X == 0);\n\tN = (X s< 0);\t\n}\n:ROR OP1\tis (op=0x36 | op=0x66 | op=0x76) ... & OP1 \n{\n\tlocal tmpC = C << 7;\n\tlocal tmp = OP1;\n\tC = tmp & 1;\n\ttmp = tmp s>> 1;\n\ttmp = tmp | tmpC;\n\tOP1 = tmp;\n\tZ = (tmp == 0);\n\tN = (tmp s< 0);\t\n}\n\n:RSP\t\tis op = 0x9C\n{\n\tSP = 0xff;\n}\n\n:RTI\t\tis op = 0x80\n{\n\tSP = SP+1;\n\tlocal ccr = *:1 SP;\n\tH = ccr[4,1];\n\tI = ccr[3,1];\n\tN = ccr[2,1];\n\tZ = ccr[1,1];\n\tC = ccr[0,1];\n\t\n\tSP = SP+1;\n\tA = *:1 SP;\n\t\n\tSP = SP+1;\n\tX = *:1 SP;\n\tSP = SP+1;\n\ttmp:2 = *:2 SP;\n\tSP = SP+1;\n\t\n\treturn [tmp];\n}\n\n:RTS\t\tis op = 0x81\n{\n\tSP = SP+1;\n\ttmp:2 = *:2 SP;\n\tSP = SP+1;\n\t\n\treturn [tmp];\n}\n\n:SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tlocal tmp = A - op1 - C;\n\tZ = tmp == 0;\n\tN = tmp s< 0;\n\tC = ((A <= op1) * C) | (A < op1);\n\tA = tmp;\n}\n\n:SEC \t\tis op = 0x99 \n{\n\tC = 1;\n}\n\n:SEI \t\tis op = 0x9B \n{\n\tI = 1;\n}\n\n:STA OP1\tis (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1\n{\n\tOP1 = A;\n\tZ = A == 0;\n\tN = A s< 0;\n}\n\n:STOP\t\tis op=0x8E\n{\n\tI = 0;\n}\n\n:STX OP1\tis (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1\n{\n\tOP1 = X;\n\tZ = X == 0;\n\tN = X s< 0;\n}\n\n:SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1\n{ \n\tlocal op1 = OP1;\n\tC = (A < op1);\n\tA = A - op1;\n\tZ = A == 0;\n\tN = A s< 0;\n\tA = A;\n}\n\n:SWI\t\tis op=0x83\n{\n\tSP=SP-1;\n\t*:2 SP = inst_next;\n\tSP=SP-1; \n\t*:1 SP = X;\n\tSP=SP-1;\n\t*:1 SP = A;\n\ttmp:1 = 0b11100000 | (H << 4) | (I << 3) | (N << 2) | ( Z << 1) | C;\n\tSP=SP-1;\n\t*:1 SP = tmp;\n\tI = 1;\n\tcall [SWI_VECTOR];\n}\n\n:TAX\tis op=0x97 \n{\n\tX = A;\n}\n \n:TSTA\t\tis op=0x4D \n{\n\tZ = (A == 0);\n\tN = (A s< 0);\t\n}\n:TSTX\t\tis op=0x5D \n{\n\tZ = (X == 0);\n\tN = (X s< 0);\t\n}\n:TST OP1\tis (op=0x3D | op=0x6D | op=0x7D) ... & OP1 \n{\n\tlocal op1 = OP1;\n\tZ = (op1 == 0);\n\tN = (op1 s< 0);\t\n}\n \n:TXA\tis op=0x9F \n{\n\tA = X;\n}\n\n:WAIT\tis op=0x8f \n{\n\tI = 0;\n}\n" }, { "path": "pypcode/processors/MC6800/data/languages/6809.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6809.pspec", "content": "\n\n\n \n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6809.slaspec", "content": "# sleigh specification file for Motorola 6809\n\n@define M6809 \"\"\n\n@include \"6x09.sinc\"\n@include \"6x09_push.sinc\"\n@include \"6x09_pull.sinc\"\n@include \"6x09_exg_tfr.sinc\"\n" }, { "path": "pypcode/processors/MC6800/data/languages/6x09.sinc", "content": "# sleigh specification file for Motorola 6809/Hitachi 6309\n\ndefine endian=big;\ndefine alignment=1;\n\n@define SWI3_VECTOR \"0xFFF2\"\n@define SWI2_VECTOR \"0xFFF4\"\n@define FIRQ_VECTOR \"0xFFF6\"\n@define IRQ_VECTOR \"0xFFF8\"\n@define SWI_VECTOR \"0xFFFA\"\n@define NMI_VECTOR \"0xFFFC\"\n@define RST_VECTOR \"0xFFFE\"\n\ndefine space RAM type=ram_space size=2 default;\ndefine space register type=register_space size=1;\n\n@ifdef H6309\n# 8-bit registers A, B, E, F, MD\ndefine register offset=0 size=1 [ A B E F MD ];\n# 16-bit registers D, W\ndefine register offset=0 size=2 [ D W ];\n# 16-bit register V\ndefine register offset=12 size=2 [ V ];\n# 32-bit register Q\ndefine register offset=0 size=4 [ Q ];\n@else\n# 8-bit registers A, B\ndefine register offset=0 size=1 [ A B ];\n# 16-bit register D\ndefine register offset=0 size=2 [ D ];\n@endif\n\n# 8-bit condition code register, direct page register\ndefine register offset=8 size=1 [ CC DP ];\n# 16-bit registers:\n# PC: Program counter\n# S: Stack pointer\n# U: alternate stack pointer/index register\n# X,Y: index register\ndefine register offset=16 size=2 [ PC X Y U S ];\n\n# Pseudo registers used for EXG instruction.\ndefine register offset=32 size=2 [ exg16_r0 exg16_r1 ];\ndefine register offset=32 size=1 [ exg8h_r0 exg8l_r0 exg8h_r1 exg8l_r1 ];\n\n# define status bits: (See also 8051/z80).\n@define C \"CC[0,1]\" # C: Carry (or borrow) flag\n@define V \"CC[1,1]\" # V: Overflow flag\n@define Z \"CC[2,1]\" # Z: Zero result\n@define N \"CC[3,1]\" # N: Negative result (twos complement)\n@define I \"CC[4,1]\" # I: IRQ interrupt masked\n@define H \"CC[5,1]\" # H: Half carry flag\n@define F \"CC[6,1]\" # F: FIRQ interrupt masked\n@define E \"CC[7,1]\" # E: Entire register state stacked\n\ndefine token opbyte (8)\n op = (0,7)\n op45 = (4,5)\n op47 = (4,7)\n;\n\ndefine token data8 (8)\n imm8 = (0,7)\n simm8 = (0,7) signed\n simm5 = (0,4) signed\n idxMode = (0,4)\n noOffset5 = (7,7)\n idxReg = (5,6)\n imm80 = (0,0)\n imm81 = (1,1)\n imm82 = (2,2)\n imm83 = (3,3)\n imm84 = (4,4)\n imm85 = (5,5)\n imm86 = (6,6)\n imm87 = (7,7)\n reg0_exg = (4,7)\n reg1_exg = (0,3)\n;\n\ndefine token data (16)\n imm16 = (0,15)\n simm16 = (0,15) signed\n;\n\nattach variables [ idxReg ] [ X Y U S ];\n\nEA: simm5,idxReg is simm5 & idxReg & noOffset5=0\n{\n local offs:1 = simm5;\n local addr:2 = idxReg + sext(offs);\n export addr; \n}\nEA: \",\"^idxReg is idxReg & noOffset5=1 & idxMode=0b00100 # no offset\n{\n local addr:2 = idxReg;\n export addr; \n}\nEA: simm8,idxReg is idxReg & noOffset5=1 & idxMode=0b01000; simm8 # 8-bit offset\n{\n local addr:2 = idxReg + simm8;\n export addr; \n}\nEA: simm16,idxReg is idxReg & noOffset5=1 & idxMode=0b01001; simm16 # 16-bit offset\n{\n local addr:2 = idxReg + simm16;\n export addr; \n}\n\n@ifdef H6309\nEA: \",\"^W is idxReg=0b00 & noOffset5=1 & idxMode=0b01111 & W # no offset\n{\n local addr:2 = W;\n export addr; \n}\nEA: simm16,W is idxReg=0b01 & noOffset5=1 & idxMode=0b01111; simm16 & W # 16-bit offset\n{\n local addr:2 = W + simm16;\n export addr; \n}\n@endif # H6309\n\nEA: A,idxReg is idxReg & noOffset5=1 & idxMode=0b00110 & A # A,R\n{\n local addr:2 = idxReg + sext(A);\n export addr; \n}\nEA: B,idxReg is idxReg & noOffset5=1 & idxMode=0b00101 & B # B,R\n{\n local addr:2 = idxReg + sext(B);\n export addr; \n}\nEA: D,idxReg is idxReg & noOffset5=1 & idxMode=0b01011 & D # D,R\n{\n local addr:2 = idxReg + D;\n export addr; \n}\n\n@ifdef H6309\nEA: E,idxReg is idxReg & noOffset5=1 & idxMode=0b00111 & E # E,R\n{\n local addr:2 = idxReg + sext(E);\n export addr; \n}\nEA: F,idxReg is idxReg & noOffset5=1 & idxMode=0b01010 & F # F,R\n{\n local addr:2 = idxReg + sext(F);\n export addr; \n}\nEA: W,idxReg is idxReg & noOffset5=1 & idxMode=0b01110 & W # W,R\n{\n local addr:2 = idxReg + W;\n export addr; \n}\n@endif # H6309\n\n\nEA: \",\"^idxReg^\"+\" is idxReg & noOffset5=1 & idxMode=0b00000 # ,R+\n{\n addr:2 = idxReg;\n idxReg = idxReg + 1;\n export addr;\n}\nEA: \",\"^idxReg^\"++\" is idxReg & noOffset5=1 & idxMode=0b00001 # ,R++\n{\n local addr:2 = idxReg;\n idxReg = idxReg + 2;\n export addr;\n}\nEA: \",-\"^idxReg is idxReg & noOffset5=1 & idxMode=0b00010 # ,-R\n{\n idxReg = idxReg - 1;\n local addr:2 = idxReg;\n export addr;\n}\nEA: \",--\"^idxReg is idxReg & noOffset5=1 & idxMode=0b00011 # ,--R\n{\n idxReg = idxReg - 2;\n local addr:2 = idxReg;\n export addr;\n}\n\n@ifdef H6309\nEA: \",\"^W^\"++\" is idxReg=0b10 & noOffset5=1 & idxMode=0b01111 & W # ,W++\n{\n local addr:2 = W;\n W = W + 2;\n export addr;\n}\nEA: \",--\"^W is idxReg=0b11 & noOffset5=1 & idxMode=0b01111 & W # ,--W\n{\n W = W - 2;\n local addr:2 = W;\n export addr;\n}\n@endif # H6309\n\nEA: addr,\"PCR\" is noOffset5=1 & idxMode=0b01100; simm8 [ addr = inst_next + simm8; ] \n{\n export *[const]:2 addr; \n}\nEA: addr,\"PCR\" is noOffset5=1 & idxMode=0b01101; simm16 [ addr = inst_next + simm16; ] \n{\n export *[const]:2 addr; \n}\nEA: \"[,\"idxReg\"]\" is idxReg & noOffset5=1 & idxMode=0b10100\n{\n local addr:2 = *:2 idxReg;\n export addr; \n}\nEA: \"[\"simm8,idxReg\"]\" is idxReg & noOffset5=1 & idxMode=0b11000; simm8\n{\n local offs:1 = simm8;\n local addr:2 = idxReg + sext(offs);\n addr = *:2 addr;\n export addr; \n}\nEA: \"[\"simm16,idxReg\"]\" is idxReg & noOffset5=1 & idxMode=0b11001; simm16\n{\n local addr:2 = idxReg + simm16;\n addr = *:2 addr;\n export addr; \n}\n\n@ifdef H6309\nEA: \"[,\"W\"]\" is idxReg=0b00 & noOffset5=1 & idxMode=0b10000 & W\n{\n local addr:2 = *:2 W;\n export addr; \n}\nEA: \"[\"simm16,W\"]\" is idxReg=0b01 & noOffset5=1 & idxMode=0b10000; simm16 & W\n{\n local addr:2 = W + simm16;\n addr = *:2 addr;\n export addr; \n}\n@endif # H6309\n\nEA: \"[\"^A,idxReg\"]\" is A & idxReg & noOffset5=1 & idxMode=0b10110\n{\n local addr:2 = idxReg + sext(A);\n addr = *:2 addr;\n export addr; \n}\nEA: \"[\"^B,idxReg\"]\" is B & idxReg & noOffset5=1 & idxMode=0b10101\n{\n local addr:2 = idxReg + sext(B);\n addr = *:2 addr;\n export addr; \n}\nEA: \"[\"^D,idxReg\"]\" is D & idxReg & noOffset5=1 & idxMode=0b11011\n{\n local addr:2 = idxReg + D;\n addr = *:2 addr;\n export addr; \n}\n\n@ifdef H6309\nEA: \"[\"^E,idxReg\"]\" is E & idxReg & noOffset5=1 & idxMode=0b10111\n{\n local addr:2 = idxReg + sext(E);\n addr = *:2 addr;\n export addr; \n}\nEA: \"[\"^F,idxReg\"]\" is F & idxReg & noOffset5=1 & idxMode=0b11010\n{\n local addr:2 = idxReg + sext(F);\n addr = *:2 addr;\n export addr; \n}\nEA: \"[\"^W,idxReg\"]\" is W & idxReg & noOffset5=1 & idxMode=0b11110\n{\n local addr:2 = idxReg + W;\n addr = *:2 addr;\n export addr; \n}\n@endif # H6309\n\n\nEA: \"[,\"idxReg\"++]\" is idxReg & noOffset5=1 & idxMode=0b10001\n{\n local addr:2 = idxReg;\n addr = *:2 addr;\n idxReg = idxReg + 2;\n export addr;\n}\nEA: \"[,--\"idxReg\"]\" is idxReg & noOffset5=1 & idxMode=0b10011\n{\n idxReg = idxReg - 2;\n local addr:2 = idxReg;\n addr = *:2 addr;\n export addr;\n}\n\n@ifdef H6309\nEA: \"[,\"^W^\"++]\" is W & idxReg=0b10 & noOffset5=1 & idxMode=0b10000\n{\n local addr:2 = W;\n addr = *:2 addr;\n W = W + 2;\n export addr;\n}\nEA: \"[,--\"^W^\"]\" is W & idxReg=0b11 & noOffset5=1 & idxMode=0b10000\n{\n W = W - 2;\n local addr:2 = W;\n addr = *:2 addr;\n export addr;\n}\n@endif # H6309\n\nEA: \"[\"addr\",PCR]\" is noOffset5=1 & idxMode=0b11100; simm8 [ addr = inst_next + simm8; ] \n{\n local eaddr:2 = inst_next + simm8;\n eaddr = *:2 eaddr;\n export eaddr; \n}\nEA: \"[\"addr\",PCR]\" is noOffset5=1 & idxMode=0b11101; simm16 [ addr = inst_next + simm16; ] \n{\n local eaddr:2 = inst_next + simm16;\n eaddr = *:2 eaddr;\n export eaddr; \n}\n\nEA: \"[\"imm16\"]\" is noOffset5=1 & idxReg=0b00 & idxMode=0b11111; imm16\n{\n local eaddr:2 = imm16;\n eaddr = *:2 eaddr;\n export eaddr; \n}\n\n################################################################\n# Constructors\n################################################################\n\nPAGE2: is op=0x10 { } # PAGE2 opcode prefix (0x10)\nPAGE3: is op=0x11 { } # PAGE3 opcode prefix (0x11)\n\nIMMED1: \"#\"imm8 is imm8 { export *[const]:1 imm8; }\n\nREL: addr is simm8 [ addr = inst_next + simm8; ] { export *:2 addr; } \nREL2: addr is simm16 [ addr = inst_next + simm16; ] { export *:2 addr; } \n\n# 1-byte operand, immediate/direct/indexed/extended addressing mode\nOP1: \"#\"imm8 is op45=0; imm8\n{\n export *[const]:1 imm8;\n}\nOP1: \"<\"imm8 is (op47=0 | op47=9 | op47=0xD); imm8\n{\n local tmp:2 = (zext(DP) << 8) + imm8;\n export *:1 tmp;\n}\nOP1: EA is op45=2; EA\n{\n local tmp:2 = EA;\n export *:1 tmp;\n}\nOP1: imm16 is op45=3; imm16\n{\n export *:1 imm16;\n}\n\n# 2-byte operand, direct/indexed/extended addressing mode\nOP2: \"#\"imm16 is (op47=8 | op47=0xC); imm16\n{\n export *[const]:2 imm16;\n}\n\nOP2: \"<\"imm8 is (op47=0 | op47=9 | op47=0xD); imm8\n{\n local tmp:2 = (zext(DP) << 8) + imm8;\n export *:2 tmp;\n}\nOP2: EA is (op47=3 | op47=6 | op47=0xA | op47=0xE); EA\n{\n local tmp:2 = EA;\n export *:2 tmp;\n}\nOP2: imm16 is (op47=7 | op47=0xB | op47=0xF); imm16\n{\n export *:2 imm16;\n}\n\n#JMP and JSR treat the direct/indexed/extended address modes differently\nOP2J: \"<\"imm8 is (op47=0 | op47=9); imm8\n{\n local tmp:2 = (zext(DP) << 8) + imm8;\n export tmp;\n}\nOP2J: EA is (op47=6 | op47=0xA); EA\n{\n export EA;\n}\nOP2J: imm16 is (op47=7 | op47=0xB ); imm16\n{\n export *[const]:2 imm16;\n}\n\n################################################################\n# Macros\n################################################################\n\nmacro setNZFlags(result)\n{\n $(Z) = (result == 0);\n $(N) = (result s< 0);\n}\n\nmacro setHFlag(reg, op)\n{\n local mask = 0x0F; # Low nibble mask\n\n $(H) = (((reg & mask) + (op & mask)) >> 4) & 1;\n}\n\n# Negate twos complement value in op.\n# P-code INT_2COMP.\nmacro negate(op)\n{\n $(V) = (op == 0x80);\n $(C) = (op != 0);\n op = -op;\n setNZFlags(op);\n}\n\n# Logical complement of op. (0 => 1; 1 => 0)\n# P-code INT_NEGATE.\nmacro complement(op)\n{\n $(V) = 0;\n $(C) = 1;\n op = ~op;\n setNZFlags(op);\n}\n\n# Signed shift right.\n# P-code INT_SRIGHT.\nmacro arithmeticShiftRight(op)\n{\n $(C) = op & 1;\n op = (op s>> 1);\n setNZFlags(op);\n}\n\nmacro logicalShiftRight(op)\n{\n $(C) = op & 1;\n op = op >> 1;\n $(Z) = (op == 0);\n $(N) = 0;\n}\n\nmacro rotateRightWithCarry(op)\n{\n local carryOut = $(C) << 7;\n $(C) = op & 1;\n op = (op s>> 1) | carryOut;\n setNZFlags(op);\n}\n\nmacro logicalShiftLeft(op)\n{\n local tmp = (op >> 7);\n $(C) = tmp;\n op = op << 1;\n $(V) = tmp ^ (op >> 7);\n setNZFlags(op);\n}\n\nmacro rotateLeftWithCarry(op)\n{\n local carryIn = $(C);\n local tmp = (op >> 7);\n $(C) = tmp;\n op = (op << 1) | carryIn;\n $(V) = tmp ^ (op >> 7);\n setNZFlags(op);\n}\n\nmacro increment(op)\n{\n $(V) = (op == 0x7F);\n op = op + 1;\n setNZFlags(op);\n}\n\nmacro decrement(op)\n{\n $(V) = (op == 0x80);\n op = op - 1;\n setNZFlags(op);\n}\n\nmacro test(op)\n{\n $(V) = 0;\n setNZFlags(op);\n}\n\nmacro clear(op)\n{\n $(V) = 0;\n op = 0;\n $(Z) = 1;\n $(N) = 0;\t\n $(C) = 0;\n}\n\nmacro addition(reg, op)\n{\n local tmp = reg;\n local val = op;\n $(C) = carry(tmp, val);\n $(V) = scarry(tmp, val);\n\n tmp = tmp + val;\n\n setNZFlags(tmp);\n reg = tmp;\n}\n\nmacro additionWithCarry(reg, op)\n{\n local carryIn = zext($(C));\n local tmp = reg;\n local val = op;\n local mask = 0x0F; # Low nibble mask\n local result = tmp + val;\n\n $(H) = (((tmp & mask) + (val & mask) + carryIn) >> 4) & 1;\n $(C) = carry(tmp, val) || carry(result, carryIn);\n $(V) = scarry(tmp, val) ^^ scarry(result, carryIn);\n\n tmp = result + carryIn;\n\n setNZFlags(tmp);\n reg = tmp;\n}\n\nmacro subtraction(reg, op)\n{\n local tmp = reg;\n local val = op;\n $(V) = sborrow(tmp, val);\n $(C) = (tmp < val);\n tmp = tmp - val;\n setNZFlags(tmp);\n reg = tmp;\n}\n\nmacro subtractionWithCarry(reg, op)\n{\n local carryIn = zext($(C));\n local tmp = reg;\n local val = op;\n local tmpResult = tmp - val;\n\n $(C) = (tmp < val) || (tmpResult < carryIn);\n $(V) = sborrow(tmp, val) ^^ sborrow(tmpResult, carryIn);\n tmp = tmpResult - carryIn;\n setNZFlags(tmp);\n reg = tmp;\n}\n\nmacro compare(reg, op)\n{\n local tmp = reg;\n local val = op;\n $(V) = sborrow(tmp, val);\n $(C) = (tmp < val);\n tmp = tmp - val;\n setNZFlags(tmp);\n}\n\nmacro logicalAnd(reg, op)\n{\n reg = reg & op;\n setNZFlags(reg);\n $(V) = 0;\n}\n\nmacro logicalOr(reg, op)\n{\n reg = reg | op;\n setNZFlags(reg);\n $(V) = 0;\n}\n\nmacro logicalExclusiveOr(reg, op)\n{\n reg = reg ^ op;\n setNZFlags(reg);\n $(V) = 0;\n}\n\nmacro bitTest(reg, op)\n{\n local tmp = reg & op;\n setNZFlags(tmp);\n $(V) = 0;\n}\n\nmacro loadRegister(reg, op)\n{\n reg = op;\n setNZFlags(reg);\n $(V) = 0;\n}\n\nmacro storeRegister(reg, op)\n{\n op = reg;\n setNZFlags(reg);\n $(V) = 0;\n}\n\n# Push 1 byte operand op1\nmacro Push1(reg, op)\n{\n reg = reg - 1;\n *:1 reg = op;\n}\n\n# Push 2 byte operand op2\nmacro Push2(reg, op)\n{\n reg = reg - 2;\n *:2 reg = op;\n}\n\n# Pull 1 byte operand op1\nmacro Pull1(reg, op)\n{\n op = *:1 reg;\n reg = reg + 1;\n}\n\n# Pull 2 byte operand op2\nmacro Pull2(reg, op)\n{\n op = *:2 reg;\n reg = reg + 2;\n}\n\nmacro PushUYXDpD()\n{\n Push2(S, U);\n Push2(S, Y);\n Push2(S, X);\n Push1(S, DP);\n Push2(S, D);\n}\n\nmacro PullDDpXYU()\n{\n Pull2(S, D);\n Pull1(S, DP);\n Pull2(S, X);\n Pull2(S, Y);\n Pull2(S, U);\n}\n\nmacro PushEntireState()\n{\n local tmp:2 = inst_next;\n\n $(E) = 1;\n Push2(S, tmp); # return PC address\n PushUYXDpD();\n Push1(S, CC);\n}\n\n################################################################\n# Instructions\n################################################################\n\n################################################################\n# Opcode 0x00 - 0x0F, relative addressing\n# Opcode 0x40 - 0x4F, register A addressing\n# Opcode 0x50 - 0x5F, register B addressing\n# Opcode 0x60 - 0x6F, indexed addressing\n# Opcode 0x70 - 0x7F, extended addressing\n################################################################\n\n:NEGA is op=0x40\n{\n negate(A);\n}\n\n:NEGB \tis op=0x50\n{\n negate(B);\n}\n\n:NEG OP1 is (op=0x00 | op=0x60 | op=0x70) ... & OP1\n{\n negate(OP1);\n}\n\n:COMA \tis op=0x43\n{\n complement(A);\n}\n\n:COMB \tis op=0x53\n{\n complement(B);\n}\n\n:COM OP1 is (op=0x03 | op=0x63 | op=0x73) ... & OP1\n{\n complement(OP1);\n}\n\n:LSRA \tis op=0x44\n{\n logicalShiftRight(A);\n}\n\n:LSRB \tis op=0x54\n{\n logicalShiftRight(B);\n}\n\n:LSR OP1 is (op=0x04 | op=0x64 | op=0x74) ... & OP1\n{\n logicalShiftRight(OP1);\n}\n\n:RORA \tis op=0x46\n{\n rotateRightWithCarry(A);\n}\n\n:RORB \tis op=0x56\n{\n rotateRightWithCarry(B);\n}\n\n:ROR OP1 is (op=0x06 | op=0x66 | op=0x76) ... & OP1\n{\n rotateRightWithCarry(OP1);\n}\n\n:ASRA \tis op=0x47\n{\n arithmeticShiftRight(A);\n}\n\n:ASRB \tis op=0x57\n{\n arithmeticShiftRight(B);\n}\n\n:ASR OP1 is (op=0x07 | op=0x67 | op=0x77) ... & OP1\n{\n arithmeticShiftRight(OP1);\n}\n\n:LSLA \tis op=0x48\n{\n logicalShiftLeft(A);\n}\n\n:LSLB \tis op=0x58\n{\n logicalShiftLeft(B);\n}\n\n:LSL OP1 is (op=0x08 | op=0x68 | op=0x78) ... & OP1\n{\n logicalShiftLeft(OP1);\n}\n\n:ROLA is op=0x49 \n{\n rotateLeftWithCarry(A);\n}\n \n:ROLB is op=0x59 \n{\n rotateLeftWithCarry(B);\n}\n \n:ROL OP1 is (op=0x09 | op=0x69 | op=0x79) ... & OP1\n{\n rotateLeftWithCarry(OP1);\n}\n \n:DECA is op=0x4A \n{\n decrement(A);\n}\n \n:DECB is op=0x5A \n{\n decrement(B);\n}\n \n:DEC OP1 is (op=0x0A | op=0x6A | op=0x7A) ... & OP1\n{\n decrement(OP1);\n}\n \n:INCA is op=0x4C \n{\n increment(A);\n}\n \n:INCB is op=0x5C \n{\n increment(B);\n}\n \n:INC OP1 is (op=0x0C | op=0x6C | op=0x7C) ... & OP1\n{\n increment(OP1);\n}\n \n:TSTA is op=0x4D \n{\n test(A);\n}\n \n:TSTB is op=0x5D \n{\n test(B);\n}\n \n:TST OP1 is (op=0x0D | op=0x6D | op=0x7D) ... & OP1\n{\n test(OP1);\n}\n \n:JMP OP2J is (op=0x0E | op=0x6E | op=0x7E) ... & OP2J\n{\n local target = OP2J;\n goto [target];\n}\n\n:CLRA is op=0x4F \n{\n clear(A);\n}\n \n:CLRB is op=0x5F \n{\n clear(B);\n}\n \n:CLR OP1 is (op=0x0F | op=0x6F | op=0x7F) ... & OP1\n{\n clear(OP1);\n}\n \n################################################################\n# Opcode 0x10 - 0x1F, misc. addressing\n################################################################\n\n:NOP is op=0x12\n{\n}\n\n:SYNC is op=0x13\n{\n}\n\n:LBRA REL2 is op=0x16; REL2\n{\n goto REL2;\n}\n\n:LBSR REL2 is op=0x17; REL2 \n{\n local tmp:2 = inst_next;\n Push2(S, tmp);\n call REL2;\n}\n\n:DAA is op=0x19\n{\n local highA:1 = A >> 4;\n local lowA:1 = A & 0x0F;\n local cc1 = ($(C) == 1 | highA > 9 | (highA > 8) & (lowA > 9));\n local cc2 = ($(H) == 1 | lowA > 9);\n\n if ( cc1 & cc2 )\n goto ;\n if ( cc1 )\n goto ;\n if ( cc2 )\n goto ;\n goto ;\n\n \n $(C) = carry(A, 0x66);\n A = A + 0x66;\n goto ;\n \n $(C) = carry(A, 0x60);\n A = A + 0x60;\n goto ;\n \n $(C) = carry(A, 0x06);\n A = A + 0x06;\n goto ;\n\n \n setNZFlags(A);\n}\n\n:ORCC IMMED1 is op=0x1A; IMMED1\n{\n CC = CC | IMMED1;\n}\n\n:ANDCC IMMED1 is op=0x1C; IMMED1\n{\n CC = CC & IMMED1;\n}\n\n:SEX is op=0x1D\n{\n D = sext(B);\n}\n\n################################################################\n# Opcode 0x20 - 0x2F, relative addressing\n################################################################\n\n:BRA REL is op=0x20; REL\n{\n goto REL;\n}\n\n:BRN REL is op=0x21; REL\n{\n}\n\n:BHI REL is op=0x22; REL\n{\n local tmp = $(C) + $(Z);\n if (tmp == 0) goto REL;\n}\n\n:BLS REL is op=0x23; REL\n{\n local tmp = $(C) + $(Z);\n if (tmp) goto REL;\n}\n\n#:BHS REL is op=0x24; REL # See BCC\n\n:BCC REL\tis op=0x24; REL\n{\n if ($(C) == 0) goto REL;\n}\n\n#:BLO REL is op=0x25; REL # see BCS\n\n:BCS REL is op=0x25; REL\n{\n if ($(C)) goto REL;\n}\n\n:BNE REL is op=0x26; REL\n{\n if ($(Z) == 0) goto REL;\n}\n\n:BEQ REL is op=0x27; REL\n{\n if ($(Z)) goto REL;\n}\n\n:BVC REL is op=0x28; REL\n{\n if ($(V) == 0) goto REL;\n}\n\n:BVS REL is op=0x29; REL\n{\n if ($(V)) goto REL;\n}\n\n:BPL REL is op=0x2A; REL\n{\n if ($(N) == 0) goto REL;\n}\n\n:BMI REL is op=0x2B; REL\n{\n if ($(N)) goto REL;\n}\n\n:BGE REL is op=0x2C; REL\n{\n if ($(N) == $(V)) goto REL;\n}\n\n:BLT REL is op=0x2D; REL\n{\n local tmp = $(C) ^ $(Z);\n if (tmp) goto REL;\n}\n\n:BGT REL is op=0x2E; REL\n{\n if (($(N) == $(V)) & $(C)) goto REL;\n}\n\n:BLE REL is op=0x2F; REL\n{\n local tmp = $(N) ^ $(V);\n if (tmp | $(Z)) goto REL;\n}\n\n################################################################\n# Opcode 0x30 - 0x3F, misc. addressing\n################################################################\n\n:LEAX EA is op=0x30; EA\n{\n local tmp = EA;\n X = tmp;\n $(Z) = (tmp == 0);\n}\n\n:LEAY EA is op=0x31; EA\n{\n local tmp = EA;\n Y = tmp;\n $(Z) = (tmp == 0);\n}\n\n:LEAS EA is op=0x32; EA\n{\n S = EA;\n}\n\n:LEAU EA is op=0x33; EA\n{\n U = EA;\n}\n\n:RTS is op=0x39\n{\n local addr:2;\n Pull2(S, addr);\n return [addr];\n}\n\n:ABX is op=0x3A\n{\n X = X + zext(B);\n}\n\n:RTI is op=0x3B\n{\n local addr:2;\n Pull1(S, CC);\n if ($(E)==0) goto ;\n PullDDpXYU();\n \n Pull2(S, addr);\n return [addr];\n}\n\n:CWAI IMMED1 is op=0x3C; IMMED1\n{\n CC = CC & IMMED1;\n PushEntireState();\n}\n\n:MUL is op=0x3D\n{\n D = zext(A) * zext(B);\n $(Z) = (D == 0);\n $(C) = B >> 7;\n}\n\n:SWI is op=0x3F\n{\n PushEntireState();\n $(I) = 1;\n $(F) = 1;\n tmp:2 = $(SWI_VECTOR);\n call [tmp];\n}\n\n################################################################\n# Opcode 0x80 - 0x8F, immediate addressing\n# Opcode 0x90 - 0x9F, direct addressing\n# Opcode 0xA0 - 0xAF, indexed addressing\n# Opcode 0xB0 - 0xBF, extended addressing\n# Opcode 0xC0 - 0xCF, immediate addressing\n# Opcode 0xD0 - 0xDF, direct addressing\n# Opcode 0xE0 - 0xEF, indexed addressing\n# Opcode 0xF0 - 0xFF, extended addressing\n################################################################\n\n:SUBA OP1 is (op=0x80 | op=0x90 | op=0xA0 | op=0xB0) ... & OP1\n{\n subtraction(A, OP1);\n}\n\n:SUBB OP1 is (op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1\n{\n subtraction(B, OP1);\n}\n\n:CMPA OP1 is (op=0x81 | op=0x91 | op=0xA1 | op=0xB1) ... & OP1\n{\n compare(A, OP1);\n}\n\n:CMPB OP1 is (op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1\n{\n compare(B, OP1);\n}\n\n:SBCA OP1 is (op=0x82 | op=0x92 | op=0xA2 | op=0xB2) ... & OP1\n{\n subtractionWithCarry(A, OP1);\n}\n\n:SBCB OP1 is (op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1\n{\n subtractionWithCarry(B, OP1);\n}\n\n:SUBD OP2 is (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2\n{\n subtraction(D, OP2);\n}\n\n:ADDD OP2 is (op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP2\n{\n addition(D, OP2);\n}\n\n:ANDA OP1 is (op=0x84 | op=0x94 | op=0xA4 | op=0xB4) ... & OP1\n{\n logicalAnd(A, OP1);\n}\n\n:ANDB OP1 is (op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1\n{\n logicalAnd(B, OP1);\n}\n\n:BITA OP1 is (op=0x85 | op=0x95 | op=0xA5 | op=0xB5) ... & OP1\n{\n bitTest(A, OP1);\n}\n\n:BITB OP1 is (op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1\n{\n bitTest(B, OP1);\n}\n\n:LDA OP1 is (op=0x86 | op=0x96 | op=0xA6 | op=0xB6) ... & OP1\n{\n loadRegister(A, OP1);\n}\n\n:LDB OP1 is (op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1\n{\n loadRegister(B, OP1);\n}\n\n:STA OP1 is (op=0x97 | op=0xA7 | op=0xB7) ... & OP1\n{\n storeRegister(A, OP1);\n}\n\n:STB OP1 is (op=0xD7 | op=0xE7 | op=0xF7) ... & OP1\n{\n storeRegister(B, OP1);\n}\n\n:EORA OP1 is (op=0x88 | op=0x98 | op=0xA8 | op=0xB8) ... & OP1\n{\n logicalExclusiveOr(A, OP1);\n}\n\n:EORB OP1 is (op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1\n{\n logicalExclusiveOr(B, OP1);\n}\n\n:ADCA OP1 is (op=0x89 | op=0x99 | op=0xA9 | op=0xB9) ... & OP1\n{\n additionWithCarry(A, OP1);\n}\n\n:ADCB OP1 is (op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1\n{\n additionWithCarry(B, OP1);\n}\n\n:ORA OP1 is (op=0x8A | op=0x9A | op=0xAA | op=0xBA) ... & OP1\n{\n logicalOr(A, OP1);\n}\n\n:ORB OP1 is (op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1\n{\n logicalOr(B, OP1);\n}\n\n:ADDA OP1 is (op=0x8B | op=0x9B | op=0xAB | op=0xBB) ... & OP1\n{\n setHFlag(A, OP1);\n addition(A, OP1);\n}\n\n:ADDB OP1 is (op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1\n{\n setHFlag(B, OP1);\n addition(B, OP1);\n}\n\n:CMPX OP2 is (op=0x8C | op=0x9C | op=0xAC | op=0xBC) ... & OP2\n{\n compare(X, OP2);\n}\n\n:LDD OP2 is (op=0xCC | op=0xDC | op=0xEC | op=0xFC) ... & OP2\n{\n loadRegister(D, OP2);\n}\n\n:BSR REL is op=0x8D; REL\n{\n local addr:2 = inst_next;\n Push2(S, addr);\n call REL;\n}\n\n:JSR OP2J is (op=0x9D | op=0xAD | op=0xBD) ... & OP2J \n{\n local addr:2 = inst_next;\n Push2(S, addr);\n local target = OP2J;\n call [target];\n}\n\n:STD OP2 is (op=0xDD | op=0xED | op=0xFD) ... & OP2\n{\n storeRegister(D, OP2);\n}\n\n:LDX OP2 is (op=0x8E | op=0x9E | op=0xAE | op=0xBE) ... & OP2\n{\n loadRegister(X, OP2);\n}\n\n:LDU OP2 is (op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP2\n{\n loadRegister(U, OP2);\n}\n\n:STX OP2 is (op=0x9F | op=0xAF | op=0xBF) ... & OP2\n{\n storeRegister(X, OP2);\n}\n\n:STU OP2 is (op=0xDF | op=0xEF | op=0xFF) ... & OP2\n{\n storeRegister(U, OP2);\n}\n\n################################################################\n# Page 2 Opcodes (prefix 0x10)\n################################################################\n:LBRN REL2 is PAGE2; op=0x21; REL2\n{\n}\n\n:LBHI REL2 is PAGE2; op=0x22; REL2\n{\n local tmp = $(C) + $(Z);\n if (tmp == 0) goto REL2;\n}\n\n:LBLS REL2 is PAGE2; op=0x23; REL2\n{\n local tmp = $(C) + $(Z);\n if (tmp) goto REL2;\n}\n\n:LBCC REL2 is PAGE2; op=0x24; REL2\n{\n if ($(C) == 0) goto REL2;\n}\n\n#:LBLO REL2 is PAGE2; op=0x25; REL2 # see LBCS\n\n:LBCS REL2 is PAGE2; op=0x25; REL2\n{\n if ($(C)) goto REL2;\n}\n\n:LBNE REL2 is PAGE2; op=0x26; REL2\n{\n if ($(Z) == 0) goto REL2;\n}\n\n:LBEQ REL2 is PAGE2; op=0x27; REL2\n{\n if ($(Z)) goto REL2;\n}\n\n:LBVC REL2 is PAGE2; op=0x28; REL2\n{\n if ($(V) == 0) goto REL2;\n}\n\n:LBVS REL2 is PAGE2; op=0x29; REL2\n{\n if ($(V)) goto REL2;\n}\n\n:LBPL REL2 is PAGE2; op=0x2A; REL2\n{\n if ($(N) == 0) goto REL2;\n}\n\n:LBMI REL2 is PAGE2; op=0x2B; REL2\n{\n if ($(N)) goto REL2;\n}\n\n:LBGE REL2 is PAGE2; op=0x2C; REL2\n{\n if ($(N) == $(V)) goto REL2;\n}\n\n:LBLT REL2 is PAGE2; op=0x2D; REL2\n{\n local tmp = $(C) ^ $(Z);\n if (tmp) goto REL2;\n}\n\n:LBGT REL2 is PAGE2; op=0x2E; REL2\n{\n if (($(N) == $(V)) & $(C)) goto REL2;\n}\n\n:LBLE REL2 is PAGE2; op=0x2F; REL2\n{\n local tmp = $(N) ^ $(V);\n if (tmp | $(Z)) goto REL2;\n}\n\n:SWI2 is PAGE2; op=0x3F\n{\n PushEntireState();\n tmp:2 = $(SWI2_VECTOR);\n call [tmp];\n}\n\n:CMPD OP2 is PAGE2; (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2\n{\n compare(D, OP2);\n}\n\n:CMPY OP2 is PAGE2; (op=0x8C | op=0x9C | op=0xAC | op=0xBC) ... & OP2\n{\n compare(Y, OP2);\n}\n\n:LDY OP2 is PAGE2; (op=0x8E | op=0x9E | op=0xAE | op=0xBE) ... & OP2\n{\n loadRegister(Y, OP2);\n}\n\n:STY OP2 is PAGE2; (op=0x9F | op=0xAF | op=0xBF) ... & OP2\n{\n storeRegister(Y, OP2);\n}\n\n:LDS OP2 is PAGE2; (op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP2\n{\n loadRegister(S, OP2);\n}\n\n:STS OP2 is PAGE2; (op=0xDF | op=0xEF | op=0xFF) ... & OP2\n{\n storeRegister(S, OP2);\n}\n\n################################################################\n# Page 3 Opcodes (prefix 0x11)\n################################################################\n\n:SWI3 is PAGE3; op=0x3F\n{\n PushEntireState();\n tmp:2 = $(SWI3_VECTOR);\n call [tmp];\n}\n\n:CMPU OP2 is PAGE3; (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2\n{\n compare(U, OP2);\n}\n\n:CMPS OP2 is PAGE3; (op=0x8C | op=0x9C | op=0xAC | op=0xBC) ... & OP2\n{\n compare(S, OP2);\n}\n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6x09_exg_tfr.sinc", "content": "# sleigh specification file for Motorola 6809/Hitachi 6309\n\n################################################################\n# EXG, TFR helper\n################################################################\n\n@ifdef H6309\nEXG_r0Tmp: D is reg0_exg=0 & D { exg16_r0 = D; }\nEXG_r0Tmp: X is reg0_exg=1 & X { exg16_r0 = X; }\nEXG_r0Tmp: Y is reg0_exg=2 & Y { exg16_r0 = Y; }\nEXG_r0Tmp: U is reg0_exg=3 & U { exg16_r0 = U; }\nEXG_r0Tmp: S is reg0_exg=4 & S { exg16_r0 = S; }\nEXG_r0Tmp: PC is reg0_exg=5 & PC { exg16_r0 = inst_next; }\nEXG_r0Tmp: W is reg0_exg=6 & W { exg16_r0 = 0x0; }\nEXG_r0Tmp: V is reg0_exg=7 & V { exg16_r0 = 0x0; }\nEXG_r0Tmp: A is reg0_exg=8 & A { exg8l_r0 = A; exg8h_r0 = A; }\nEXG_r0Tmp: B is reg0_exg=9 & B { exg8l_r0 = B; exg8h_r0 = B; }\nEXG_r0Tmp: CC is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;}\nEXG_r0Tmp: DP is reg0_exg=11 & DP { exg8l_r0 = DP; exg8h_r0 = DP;}\nEXG_r0Tmp: 0 is reg0_exg=12 { exg16_r0 = 0x0; }\nEXG_r0Tmp: 0 is reg0_exg=13 { exg16_r0 = 0x0; }\nEXG_r0Tmp: E is reg0_exg=14 & E { exg8l_r0 = E; exg8h_r0 = E; }\nEXG_r0Tmp: F is reg0_exg=15 & F { exg8l_r0 = F; exg8h_r0 = F; }\n\nEXG_r1Tmp: D is reg1_exg=0 & D { exg16_r1 = D; }\nEXG_r1Tmp: X is reg1_exg=1 & X { exg16_r1 = X; }\nEXG_r1Tmp: Y is reg1_exg=2 & Y { exg16_r1 = Y; }\nEXG_r1Tmp: U is reg1_exg=3 & U { exg16_r1 = U; }\nEXG_r1Tmp: S is reg1_exg=4 & S { exg16_r1 = S; }\nEXG_r1Tmp: PC is reg1_exg=5 & PC { exg16_r1 = inst_next; }\nEXG_r1Tmp: W is reg1_exg=6 & W { exg16_r1 = 0x0; }\nEXG_r1Tmp: V is reg1_exg=7 & V { exg16_r1 = 0x0; }\nEXG_r1Tmp: A is reg1_exg=8 & A { exg8l_r1 = A; exg8h_r1 = A; }\nEXG_r1Tmp: B is reg1_exg=9 & B { exg8l_r1 = B; exg8h_r1 = B; }\nEXG_r1Tmp: CC is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = CC;}\nEXG_r1Tmp: DP is reg1_exg=11 & DP { exg8l_r1 = DP; exg8h_r1 = DP;}\nEXG_r1Tmp: 0 is reg1_exg=12 { exg16_r1 = 0x0; }\nEXG_r1Tmp: 0 is reg1_exg=13 { exg16_r1 = 0x0; }\nEXG_r1Tmp: E is reg1_exg=14 & E { exg8l_r1 = E; exg8h_r1 = E; }\nEXG_r1Tmp: F is reg1_exg=15 & F { exg8l_r1 = F; exg8h_r1 = F; }\n\nEXG_r0Set: D is reg0_exg=0 & D { D = exg16_r1; }\nEXG_r0Set: X is reg0_exg=1 & X { X = exg16_r1; }\nEXG_r0Set: Y is reg0_exg=2 & Y { Y = exg16_r1; }\nEXG_r0Set: U is reg0_exg=3 & U { U = exg16_r1; }\nEXG_r0Set: S is reg0_exg=4 & S { S = exg16_r1; }\nEXG_r0Set: PC is reg0_exg=5 & PC { PC = exg16_r1; } # must GOTO\nEXG_r0Set: W is reg0_exg=6 & W { W = exg16_r1; }\nEXG_r0Set: V is reg0_exg=7 & V { V = exg16_r1; }\nEXG_r0Set: A is reg0_exg=8 & A { A = exg8h_r1; }\nEXG_r0Set: B is reg0_exg=9 & B { B = exg8l_r1; }\nEXG_r0Set: CC is reg0_exg=10 & CC { CC = exg8l_r1; }\nEXG_r0Set: DP is reg0_exg=11 & DP { DP = exg8h_r1; }\nEXG_r0Set: 0 is reg0_exg=12 { }\nEXG_r0Set: 0 is reg0_exg=13 { }\nEXG_r0Set: E is reg0_exg=14 & E { E = exg8h_r1; }\nEXG_r0Set: F is reg0_exg=15 & F { F = exg8l_r1; }\n\nEXG_r1Set: D is reg1_exg=0 & D { D = exg16_r0; }\nEXG_r1Set: X is reg1_exg=1 & X { X = exg16_r0; }\nEXG_r1Set: Y is reg1_exg=2 & Y { Y = exg16_r0; }\nEXG_r1Set: U is reg1_exg=3 & U { U = exg16_r0; }\nEXG_r1Set: S is reg1_exg=4 & S { S = exg16_r0; }\nEXG_r1Set: PC is reg1_exg=5 & PC { PC = exg16_r0; } # must GOTO\nEXG_r1Set: W is reg1_exg=6 & W { W = exg16_r0; }\nEXG_r1Set: V is reg1_exg=7 & V { V = exg16_r0; }\nEXG_r1Set: A is reg1_exg=8 & A { A = exg8h_r0; }\nEXG_r1Set: B is reg1_exg=9 & B { B = exg8l_r0; }\nEXG_r1Set: CC is reg1_exg=10 & CC { CC = exg8l_r0; }\nEXG_r1Set: DP is reg1_exg=11 & DP { DP = exg8h_r0; }\nEXG_r1Set: 0 is reg1_exg=12 { }\nEXG_r1Set: 0 is reg1_exg=13 { }\nEXG_r1Set: E is reg1_exg=14 & E { E = exg8h_r0; }\nEXG_r1Set: F is reg1_exg=15 & F { F = exg8l_r0; }\n@endif\n\n@ifdef M6809\nEXG_r0Tmp: D is reg0_exg=0 & D { exg16_r0 = D; }\nEXG_r0Tmp: X is reg0_exg=1 & X { exg16_r0 = X; }\nEXG_r0Tmp: Y is reg0_exg=2 & Y { exg16_r0 = Y; }\nEXG_r0Tmp: U is reg0_exg=3 & U { exg16_r0 = U; }\nEXG_r0Tmp: S is reg0_exg=4 & S { exg16_r0 = S; }\nEXG_r0Tmp: PC is reg0_exg=5 & PC { exg16_r0 = inst_next; }\nEXG_r0Tmp: \"inv\" is reg0_exg=6 { exg16_r0 = 0xFFFF; }\nEXG_r0Tmp: \"inv\" is reg0_exg=7 { exg16_r0 = 0xFFFF; }\nEXG_r0Tmp: A is reg0_exg=8 & A { exg8l_r0 = A; exg8h_r0 = 0xFF; }\nEXG_r0Tmp: B is reg0_exg=9 & B { exg8l_r0 = B; exg8h_r0 = 0xFF; }\nEXG_r0Tmp: CC is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;}\nEXG_r0Tmp: DP is reg0_exg=11 & DP { exg8l_r0 = DP; exg8h_r0 = DP;}\nEXG_r0Tmp: \"inv\" is reg0_exg=12 { exg16_r0 = 0xFFFF; }\nEXG_r0Tmp: \"inv\" is reg0_exg=13 { exg16_r0 = 0xFFFF; }\nEXG_r0Tmp: \"inv\" is reg0_exg=14 { exg16_r0 = 0xFFFF; }\nEXG_r0Tmp: \"inv\" is reg0_exg=15 { exg16_r0 = 0xFFFF; }\n\nEXG_r1Tmp: D is reg1_exg=0 & D { exg16_r1 = D; }\nEXG_r1Tmp: X is reg1_exg=1 & X { exg16_r1 = X; }\nEXG_r1Tmp: Y is reg1_exg=2 & Y { exg16_r1 = Y; }\nEXG_r1Tmp: U is reg1_exg=3 & U { exg16_r1 = U; }\nEXG_r1Tmp: S is reg1_exg=4 & S { exg16_r1 = S; }\nEXG_r1Tmp: PC is reg1_exg=5 & PC { exg16_r1 = inst_next; }\nEXG_r1Tmp: \"inv\" is reg1_exg=6 { exg16_r1 = 0xFFFF; }\nEXG_r1Tmp: \"inv\" is reg1_exg=7 { exg16_r1 = 0xFFFF; }\nEXG_r1Tmp: A is reg1_exg=8 & A { exg8l_r1 = A; exg8h_r1 = 0xFF; }\nEXG_r1Tmp: B is reg1_exg=9 & B { exg8l_r1 = B; exg8h_r1 = 0xFF; }\nEXG_r1Tmp: CC is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = 0xFF;}\nEXG_r1Tmp: DP is reg1_exg=11 & DP { exg8l_r1 = DP; exg8h_r1 = 0xFF;}\nEXG_r1Tmp: \"inv\" is reg1_exg=12 { exg16_r1 = 0xFFFF; }\nEXG_r1Tmp: \"inv\" is reg1_exg=13 { exg16_r1 = 0xFFFF; }\nEXG_r1Tmp: \"inv\" is reg1_exg=14 { exg16_r1 = 0xFFFF; }\nEXG_r1Tmp: \"inv\" is reg1_exg=15 { exg16_r1 = 0xFFFF; }\n\nEXG_r0Set: D is reg0_exg=0 & D { D = exg16_r1; }\nEXG_r0Set: X is reg0_exg=1 & X { X = exg16_r1; }\nEXG_r0Set: Y is reg0_exg=2 & Y { Y = exg16_r1; }\nEXG_r0Set: U is reg0_exg=3 & U { U = exg16_r1; }\nEXG_r0Set: S is reg0_exg=4 & S { S = exg16_r1; }\nEXG_r0Set: PC is reg0_exg=5 & PC { PC = exg16_r1; } # must GOTO\nEXG_r0Set: \"inv\" is reg0_exg=6 { }\nEXG_r0Set: \"inv\" is reg0_exg=7 { }\nEXG_r0Set: A is reg0_exg=8 & A { A = exg8l_r1; }\nEXG_r0Set: B is reg0_exg=9 & B { B = exg8l_r1; }\nEXG_r0Set: CC is reg0_exg=10 & CC { CC = exg8l_r1; }\nEXG_r0Set: DP is reg0_exg=11 & DP { DP = exg8l_r1; }\nEXG_r0Set: \"inv\" is reg0_exg=12 { }\nEXG_r0Set: \"inv\" is reg0_exg=13 { }\nEXG_r0Set: \"inv\" is reg0_exg=14 { }\nEXG_r0Set: \"inv\" is reg0_exg=15 { }\n\nEXG_r1Set: D is reg1_exg=0 & D { D = exg16_r0; } # Must to r1 set first so A,D = A,B switch\nEXG_r1Set: X is reg1_exg=1 & X { X = exg16_r0; }\nEXG_r1Set: Y is reg1_exg=2 & Y { Y = exg16_r0; }\nEXG_r1Set: U is reg1_exg=3 & U { U = exg16_r0; }\nEXG_r1Set: S is reg1_exg=4 & S { S = exg16_r0; }\nEXG_r1Set: PC is reg1_exg=5 & PC { PC = exg16_r0; } # must GOTO\nEXG_r1Set: \"inv\" is reg1_exg=6 { }\nEXG_r1Set: \"inv\" is reg1_exg=7 { }\nEXG_r1Set: A is reg1_exg=8 & A { A = exg8l_r0; }\nEXG_r1Set: B is reg1_exg=9 & B { B = exg8l_r0; }\nEXG_r1Set: CC is reg1_exg=10 & CC { CC = exg8l_r0; }\nEXG_r1Set: DP is reg1_exg=11 & DP { DP = exg8l_r0; }\nEXG_r1Set: \"inv\" is reg1_exg=12 { }\nEXG_r1Set: \"inv\" is reg1_exg=13 { }\nEXG_r1Set: \"inv\" is reg1_exg=14 { }\nEXG_r1Set: \"inv\" is reg1_exg=15 { }\n@endif\n\nEXG_GOTO: is reg0_exg=5 | reg1_exg=5 { goto [PC]; }\nEXG_GOTO: is reg0_exg & reg1_exg { } # PC not set\n\nTFR_GOTO: is reg1_exg=5 { goto [PC]; }\nTFR_GOTO: is reg1_exg { } # PC not set\n\n# Exchange two registers\n:EXG EXG_r0Set,EXG_r1Set is op=0x1E; EXG_r0Set & EXG_r1Set & EXG_r0Tmp & EXG_r1Tmp & EXG_GOTO \n{\n build EXG_r0Tmp;\n build EXG_r1Tmp;\n build EXG_r1Set;\n build EXG_r0Set;\n build EXG_GOTO;\n}\n\n# Transfer register to another register\n:TFR EXG_r0Tmp,EXG_r1Set is op=0x1F; EXG_r1Set & EXG_r0Tmp & TFR_GOTO\n{\n build EXG_r0Tmp;\n build EXG_r1Set;\n build TFR_GOTO;\n}\n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6x09_pull.sinc", "content": "# sleigh specification file for Motorola 6809/Hitachi 6309\n\n#################################################################\n# PULS helper\n################################################################\n\npuls0: CC is CC & imm80=1 { Pull1(S, CC); }\npuls0: is imm80=0 { }\npuls1: puls0\" \"A is A & imm81=1 & puls0 { Pull1(S, A); }\npuls1: puls0 is imm81=0 & puls0 { }\npuls2: puls1\" \"B is B & imm82=1 & puls1 { Pull1(S, B); }\npuls2: puls1 is imm82=0 & puls1 { }\npuls3: puls2\" \"DP is DP & imm83=1 & puls2 { Pull1(S, DP); }\npuls3: puls2 is imm83=0 & puls2 { }\npuls4: puls3\" \"X is X & imm84=1 & puls3 { Pull2(S, X); }\npuls4: puls3 is imm84=0 & puls3 { }\npuls5: puls4\" \"Y is Y & imm85=1 & puls4 { Pull2(S, Y); }\npuls5: puls4 is imm85=0 & puls4 { }\npuls6: puls5\" \"U is U & imm86=1 & puls5 { Pull2(S, U); }\npuls6: puls5 is imm86=0 & puls5 { }\npuls7: puls6\" \"PC is PC & imm87=1 & puls6 { local t:2 = 0; Pull2(S, t); goto [t]; }\npuls7: puls6 is imm87=0 & puls6 { }\n\n:PULS puls7 is op=0x35; puls7 { } \n\n################################################################\n# PULU helper\n################################################################\n\npulu0: CC is CC & imm80=1 { Pull1(U, CC); }\npulu0: is imm80=0 { }\npulu1: pulu0\" \"A is A & imm81=1 & pulu0 { Pull1(U, A); }\npulu1: pulu0 is imm81=0 & pulu0 { }\npulu2: pulu1\" \"B is B & imm82=1 & pulu1 { Pull1(U, B); }\npulu2: pulu1 is imm82=0 & pulu1 { }\npulu3: pulu2\" \"DP is DP & imm83=1 & pulu2 { Pull1(U, DP); }\npulu3: pulu2 is imm83=0 & pulu2 { }\npulu4: pulu3\" \"X is X & imm84=1 & pulu3 { Pull2(U, X); }\npulu4: pulu3 is imm84=0 & pulu3 { }\npulu5: pulu4\" \"Y is Y & imm85=1 & pulu4 { Pull2(U, Y); }\npulu5: pulu4 is imm85=0 & pulu4 { }\npulu6: pulu5\" \"S is S & imm86=1 & pulu5 { Pull2(U, S); }\npulu6: pulu5 is imm86=0 & pulu5 { }\npulu7: pulu6\" \"PC is PC & imm87=1 & pulu6 { local t:2 = 0; Pull2(U, t); goto [t]; }\npulu7: pulu6 is imm87=0 & pulu6 { }\n\n:PULU pulu7 is op=0x37; pulu7 { }\n\n" }, { "path": "pypcode/processors/MC6800/data/languages/6x09_push.sinc", "content": "# sleigh specification file for Motorola 6809/Hitachi 6309\n\n################################################################\n# PSHS helper\n################################################################\n\n\npshs7: \" \"PC is PC & imm87=1 { local t:2 = inst_next; Push2(S, t); }\npshs7: is imm87=0 { }\npshs6: pshs7\" \"U is U & imm86=1 & pshs7 { Push2(S, U); }\npshs6: pshs7 is imm86=0 & pshs7 { }\npshs5: pshs6\" \"Y is Y & imm85=1 & pshs6 { Push2(S, Y); }\npshs5: pshs6 is imm85=0 & pshs6 { }\npshs4: pshs5\" \"X is X & imm84=1 & pshs5 { Push2(S, X); }\npshs4: pshs5 is imm84=0 & pshs5 { }\npshs3: pshs4\" \"DP is DP & imm83=1 & pshs4 { Push1(S, DP); }\npshs3: pshs4 is imm83=0 & pshs4 { }\npshs2: pshs3\" \"B is B & imm82=1 & pshs3 { Push1(S, B); }\npshs2: pshs3 is imm82=0 & pshs3 { }\npshs1: pshs2\" \"A is A & imm81=1 & pshs2 { Push1(S, A); }\npshs1: pshs2 is imm81=0 & pshs2 { }\npshs0: pshs1\" \"CC is CC & imm80=1 & pshs1 { Push1(S, CC); }\npshs0: pshs1 is imm80=0 & pshs1 { }\n\n:PSHS pshs0 is op=0x34; pshs0 { } \n################################################################\n# PSHU helper\n################################################################\n\npshu7: PC is PC & imm87=1 { local t:2 = inst_next; Push2(U, t); }\npshu7: is imm87=0 { }\npshu6: pshu7\" \"S is S & imm86=1 & pshu7 { Push2(U, S); }\npshu6: pshu7 is imm86=0 & pshu7 { }\npshu5: pshu6\" \"Y is Y & imm85=1 & pshu6 { Push2(U, Y); }\npshu5: pshu6 is imm85=0 & pshu6 { }\npshu4: pshu5\" \"X is X & imm84=1 & pshu5 { Push2(U, X); }\npshu4: pshu5 is imm84=0 & pshu5 { }\npshu3: pshu4\" \"DP is DP & imm83=1 & pshu4 { Push1(U, DP); }\npshu3: pshu4 is imm83=0 & pshu4 { }\npshu2: pshu3\" \"B is B & imm82=1 & pshu3 { Push1(U, B); }\npshu2: pshu3 is imm82=0 & pshu3 { }\npshu1: pshu2\" \"A is A & imm81=1 & pshu2 { Push1(U, A); }\npshu1: pshu2 is imm81=0 & pshu2 { }\npshu0: pshu1\" \"CC is CC & imm80=1 & pshu1 { Push1(U, CC); }\npshu0: pshu1 is imm80=0 & pshu1 { }\n\n:PSHU pshu0 is op=0x36; pshu0 { }\n\n" }, { "path": "pypcode/processors/MC6800/data/languages/H6309.slaspec", "content": "# sleigh specification file for Hitachi 6309\n# Compatible with MC6809 with some extended instructions\n# and addressing modes\n\n@define H6309 \"\"\n\n@include \"6x09.sinc\"\n@include \"6x09_push.sinc\"\n@include \"6x09_pull.sinc\"\n@include \"6x09_exg_tfr.sinc\"\n" }, { "path": "pypcode/processors/MC6800/data/manuals/6809.idx", "content": "@M6809PM.rev0_May83.pdf [MC6809-MC6809E Microprocessor Programming Manual, May 1983 (M6809PM/AD)]\nABX, 51\nADCA, 52\nADCB, 52\nADDA, 53\nADDB, 53\nADDD, 54\nANDA, 55\nANDB, 55\nANDCC, 56\nASL, 57\nASLA, 57\nASLB, 57\nASR, 58\nASRA, 58\nASRB, 58\nBCC, 59\nLBCC, 59\nBCS, 60\nLBCS, 60\nBEQ, 61\nLBEQ, 61\nBGE, 62\nLBGE, 62\nBGT, 63\nLBGT, 63\nBHI, 64\nLBHI, 64\nBHS, 65\nLBHS, 65\nBITA, 66\nBITB, 66\nBLE, 67\nLBLE, 67\nBLO, 68\nLBLO, 68\nBLS, 69\nLBLS, 69\nBLT, 70\nLBLT, 70\nBMI, 71\nLBMI, 71\nBNE, 72\nLBNE, 72\nBPL, 73\nLBPL, 73\nBRA, 74\nLBRA, 74\nBRN, 75\nLBRN, 75\nBSR, 76\nLBSR, 76\nBVC, 77\nLBVC, 77\nBVS, 78\nLBVS, 78\nCLR, 79\nCMPA, 80\nCMPB, 80\nCMPD, 81\nCMPX, 81\nCMPY, 81\nCMPU, 81\nCMPS, 81\nCOM, 82\nCOMA, 82\nCOMB, 82\nCWAI, 83\nDDA, 84\nDEC, 85\nDECA, 85\nDECB, 85\nEORA, 86\nEORB, 86\nEXG, 87\nINC, 88\nINCA, 88\nINCB, 88\nJMP, 89\nJSR, 90\nLDA, 91\nLDB, 91\nLDD, 92\nLDX, 92\nLDY, 92\nLDS, 92\nLDU, 92\nLEAX, 93\nLEAY, 93\nLEAS, 93\nLEAU, 93\nLSL, 94\nLSLA, 94\nLSLB, 94\nLSR, 95\nLSRA, 95\nLSRB, 95\nMUL, 96\nNEG, 97\nNEGA, 97\nNEGB, 97\nNOP, 98\nORA, 99\nORB, 99\nORCC, 100\nPSHS, 101\nPSHU, 102\nPULS, 103\nPULU, 104\nROL, 105\nROLA, 105\nROLB, 105\nROR, 106\nRORA, 106\nRORB, 106\nRTI, 107\nRTS, 108\nSBCA, 109\nSBCB, 109\nSEX, 110\nSTA, 111\nSTB, 111\nSTD, 112\nSTX, 112\nSTY, 112\nSTS, 112\nSTU, 112\nSUBA, 113\nSUBB, 113\nSUBD, 114\nSWI, 115\nSWI2, 116\nSWI3, 117\nSYNC, 118\nTFR, 119\nTST, 120\nTSTA, 120\nTSTB, 120" }, { "path": "pypcode/processors/MCS96/data/languages/MCS96.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MCS96/data/languages/MCS96.ldefs", "content": "\n\n\n \n Intel MCS-96 Microcontroller Family\n \n \n\n" }, { "path": "pypcode/processors/MCS96/data/languages/MCS96.pspec", "content": "\n\n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MCS96/data/languages/MCS96.sinc", "content": "\ndefine endian=little;\n\ndefine alignment=1;\n\ndefine space RAM type=ram_space size=2 wordsize=1 default;\ndefine space register type=register_space size=1;\n\n################################################################\n# Registers\n################################################################\ndefine register offset=0x00 size=2 [ PSW ];\n\ndefine register offset=0x10 size=2 [ PC ];\n\ndefine register offset=0x18 size=2 [ SP ];\n\n# Special registers\ndefine RAM offset=0x00 size=1\n[\n\tZRlo ZRhi AD_resultlo AD_resulthi HSI_timelo HSI_timehi\n\tHSI_status SBUF INT_MASK INT_PEND TIMER1lo TIMER1hi\n\tTIMER2lo TIMER2hi PORT0 PORT1 PORT2 SP_STAT INT_PEND1\n\tINT_MASK1 WSR IOS0 IOS1 IOS2\n];\n\ndefine RAM offset=0x00 size=2\n[\n\tZR AD_result HSI_time\n\tHSI_SBUF INTERRUPT TIMER1\n\tTIMER2 PORT01 PORT2_SPS INT1\n\tWSR_IOS0 IOS12\n];\n\ndefine RAM offset=0x00 size=4\n[\n\tZR_AD HSI INT_TIMER1\n\tTIMER2_PORT01 PORT2_INT1\n\tWSR_IOS012\n];\n\n# Stack pointer\ndefine RAM offset=0x18 size=1 [ SPlo SPhi];\ndefine RAM offset=0x18 size=2 [ SPR ];\ndefine RAM offset=0x18 size=4 [ SPR1A ];\n\n\n# Byte registers\ndefine RAM offset=0x1a size=1\n[\n\tR1A R1B R1C R1D R1E R1F\n\tR20 R21 R22 R23 R24 R25 R26 R27\n\tR28 R29 R2A R2B R2C R2D R2E R2F\n\tR30 R31 R32 R33 R34 R35 R36 R37\n\tR38 R39 R3A R3B R3C R3D R3E R3F\n\tR40 R41 R42 R43 R44 R45 R46 R47\n\tR48 R49 R4A R4B R4C R4D R4E R4F\n\tR50 R51 R52 R53 R54 R55 R56 R57\n\tR58 R59 R5A R5B R5C R5D R5E R5F\n\tR60 R61 R62 R63 R64 R65 R66 R67\n\tR68 R69 R6A R6B R6C R6D R6E R6F\n\tR70 R71 R72 R73 R74 R75 R76 R77\n\tR78 R79 R7A R7B R7C R7D R7E R7F\n\tR80 R81 R82 R83 R84 R85 R86 R87\n\tR88 R89 R8A R8B R8C R8D R8E R8F\n\tR90 R91 R92 R93 R94 R95 R96 R97\n\tR98 R99 R9A R9B R9C R9D R9E R9F\n\tRA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7\n\tRA8 RA9 RAA RAB RAC RAD RAE RAF\n\tRB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7\n\tRB8 RB9 RBA RBB RBC RBD RBE RBF\n\tRC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7\n\tRC8 RC9 RCA RCB RCC RCD RCE RCF\n\tRD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7\n\tRD8 RD9 RDA RDB RDC RDD RDE RDF\n\tRE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7\n\tRE8 RE9 REA REB REC RED REE REF\n\tRF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7\n\tRF8 RF9 RFA RFB RFC RFD RFE RFF\n\tR100 R101 R102 R103 R104 R105 R106 R107\n\tR108 R109 R10A R10B R10C R10D R10E R10F\n\tR110 R111 R112 R113 R114 R115 R116 R117\n\tR118 R119 R11A R11B R11C R11D R11E R11F\n\tR120 R121 R122 R123 R124 R125 R126 R127\n\tR128 R129 R12A R12B R12C R12D R12E R12F\n\tR130 R131 R132 R133 R134 R135 R136 R137\n\tR138 R139 R13A R13B R13C R13D R13E R13F\n\tR140 R141 R142 R143 R144 R145 R146 R147\n\tR148 R149 R14A R14B R14C R14D R14E R14F\n\tR150 R151 R152 R153 R154 R155 R156 R157\n\tR158 R159 R15A R15B R15C R15D R15E R15F\n\tR160 R161 R162 R163 R164 R165 R166 R167\n\tR168 R169 R16A R16B R16C R16D R16E R16F\n\tR170 R171 R172 R173 R174 R175 R176 R177\n\tR178 R179 R17A R17B R17C R17D R17E R17F\n\tR180 R181 R182 R183 R184 R185 R186 R187\n\tR188 R189 R18A R18B R18C R18D R18E R18F\n\tR190 R191 R192 R193 R194 R195 R196 R197\n\tR198 R199 R19A R19B R19C R19D R19E R19F\n\tR1A0 R1A1 R1A2 R1A3 R1A4 R1A5 R1A6 R1A7\n\tR1A8 R1A9 R1AA R1AB R1AC R1AD R1AE R1AF\n\tR1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7\n\tR1B8 R1B9 R1BA R1BB R1BC R1BD R1BE R1BF\n\tR1C0 R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7\n\tR1C8 R1C9 R1CA R1CB R1CC R1CD R1CE R1CF\n\tR1D0 R1D1 R1D2 R1D3 R1D4 R1D5 R1D6 R1D7\n\tR1D8 R1D9 R1DA R1DB R1DC R1DD R1DE R1DF\n\tR1E0 R1E1 R1E2 R1E3 R1E4 R1E5 R1E6 R1E7\n\tR1E8 R1E9 R1EA R1EB R1EC R1ED R1EE R1EF\n\tR1F0 R1F1 R1F2 R1F3 R1F4 R1F5 R1F6 R1F7\n\tR1F8 R1F9 R1FA R1FB R1FC R1FD R1FE R1FF\n];\n\n# Word registers\ndefine RAM offset=0x1a size=2\n[\n\tRW1A RW1C RW1E\n\tRW20 RW22 RW24 RW26 RW28 RW2A RW2C RW2E\n\tRW30 RW32 RW34 RW36 RW38 RW3A RW3C RW3E\n\tRW40 RW42 RW44 RW46 RW48 RW4A RW4C RW4E\n\tRW50 RW52 RW54 RW56 RW58 RW5A RW5C RW5E\n\tRW60 RW62 RW64 RW66 RW68 RW6A RW6C RW6E\n\tRW70 RW72 RW74 RW76 RW78 RW7A RW7C RW7E\n\tRW80 RW82 RW84 RW86 RW88 RW8A RW8C RW8E\n\tRW90 RW92 RW94 RW96 RW98 RW9A RW9C RW9E\n\tRWA0 RWA2 RWA4 RWA6 RWA8 RWAA RWAC RWAE\n\tRWB0 RWB2 RWB4 RWB6 RWB8 RWBA RWBC RWBE\n\tRWC0 RWC2 RWC4 RWC6 RWC8 RWCA RWCC RWCE\n\tRWD0 RWD2 RWD4 RWD6 RWD8 RWDA RWDC RWDE\n\tRWE0 RWE2 RWE4 RWE6 RWE8 RWEA RWEC RWEE\n\tRWF0 RWF2 RWF4 RWF6 RWF8 RWFA RWFC RWFE\n\tRW100 RW102 RW104 RW106 RW108 RW10A RW10C RW10E\n\tRW110 RW112 RW114 RW116 RW118 RW11A RW11C RW11E\n\tRW120 RW122 RW124 RW126 RW128 RW12A RW12C RW12E\n\tRW130 RW132 RW134 RW136 RW138 RW13A RW13C RW13E\n\tRW140 RW142 RW144 RW146 RW148 RW14A RW14C RW14E\n\tRW150 RW152 RW154 RW156 RW158 RW15A RW15C RW15E\n\tRW160 RW162 RW164 RW166 RW168 RW16A RW16C RW16E\n\tRW170 RW172 RW174 RW176 RW178 RW17A RW17C RW17E\n\tRW180 RW182 RW184 RW186 RW188 RW18A RW18C RW18E\n\tRW190 RW192 RW194 RW196 RW198 RW19A RW19C RW19E\n\tRW1A0 RW1A2 RW1A4 RW1A6 RW1A8 RW1AA RW1AC RW1AE\n\tRW1B0 RW1B2 RW1B4 RW1B6 RW1B8 RW1BA RW1BC RW1BE\n\tRW1C0 RW1C2 RW1C4 RW1C6 RW1C8 RW1CA RW1CC RW1CE\n\tRW1D0 RW1D2 RW1D4 RW1D6 RW1D8 RW1DA RW1DC RW1DE\n\tRW1E0 RW1E2 RW1E4 RW1E6 RW1E8 RW1EA RW1EC RW1EE\n\tRW1F0 RW1F2 RW1F4 RW1F6 RW1F8 RW1FA RW1FC RW1FE\n];\n\n# Double-word registers\ndefine RAM offset=0x1c size=4\n[\n\tRL1C\n\tRL20 RL24 RL28 RL2C RL30 RL34 RL38 RL3C\n\tRL40 RL44 RL48 RL4C RL50 RL54 RL58 RL5C\n\tRL60 RL64 RL68 RL6C RL70 RL74 RL78 RL7C\n\tRL80 RL84 RL88 RL8C RL90 RL94 RL98 RL9C\n\tRLA0 RLA4 RLA8 RLAC RLB0 RLB4 RLB8 RLBC\n\tRLC0 RLC4 RLC8 RLCC RLD0 RLD4 RLD8 RLDC\n\tRLE0 RLE4 RLE8 RLEC RLF0 RLF4 RLF8 RLFC\n\tRL100 RL104 RL108 RL10C RL110 RL114 RL118 RL11C\n\tRL120 RL124 RL128 RL12C RL130 RL134 RL138 RL13C\n\tRL140 RL144 RL148 RL14C RL150 RL154 RL158 RL15C\n\tRL160 RL164 RL168 RL16C RL170 RL174 RL178 RL17C\n\tRL180 RL184 RL188 RL18C RL190 RL194 RL198 RL19C\n\tRL1A0 RL1A4 RL1A8 RL1AC RL1B0 RL1B4 RL1B8 RL1BC\n\tRL1C0 RL1C4 RL1C8 RL1CC RL1D0 RL1D4 RL1D8 RL1DC\n\tRL1E0 RL1E4 RL1E8 RL1EC RL1F0 RL1F4 RL1F8 RL1FC\n];\n\n# Individual status bits within the Program Status Word\n@define Z\t\t\"PSW[7,1]\"\t\t# Zero Flag\n@define N\t\t\"PSW[6,1]\"\t\t# Negative Flag\n@define V\t\t\"PSW[5,1]\"\t\t# Overflow Flag\n@define VT\t\t\"PSW[4,1]\"\t\t# Overflow Trap Flag\n@define C\t\t\"PSW[3,1]\"\t\t# Carry Flag\n@define PSE\t\t\"PSW[2,1]\"\t\t# Peripheral Transaction Server flag\n@define I\t\t\"PSW[1,1]\"\t\t# global Interrupt disable bit\n@define ST\t\t\"PSW[0,1]\" # STicky bit Flag\n\n################################################################\n# Tokens\n################################################################\n# All instructions have a single-byte opcode except for a\n# handful of multiplication/division instructions which have\n# a two-byte op-code with the first byte as 'FE'\ndefine token opbyte (8)\n\top8 = (0,7)\n\top6 = (2,7)\n\top5 = (3,7)\n\tcond = (0,3)\n\top4 = (4,7)\n\taa = (0,1)\n\tbitno = (0,2)\n\thighb = (4,7)\n\timm8 = (0,7) signed # immediate\n\tsimm8 = (0,7) signed # immediate\n\tbaop = (0,7) # byte register\n\tbreg8 = (0,7) # byte register\n\tdbreg = (0,7) # byte register\n\twaop = (0,7) # word register\n\twreg8 = (0,7) # word register\n\tdwreg = (0,7) # word register\n\tlreg = (0,7) # long/double register\n\tdlreg = (0,7) # long/double register\n\timm7 = (1,7)\n\tiwreg7 = (1,7)\n\taddbit8 = (0,0)\n;\n\ndefine token opword (16)\n\timm16 = ( 0, 15 )\n\tdisp16 = (0,15) signed\n\top16 = (3,7)\n\tjmp11_hi = (0,2) signed #relative offset\n\tjmp11_lo = (8,15)\n;\n\nattach variables [ baop breg8 dbreg ]\n[\n ZRlo ZRhi AD_resultlo AD_resulthi HSI_timelo HSI_timehi\n HSI_status SBUF INT_MASK INT_PEND TIMER1lo TIMER1hi\n TIMER2lo TIMER2hi PORT0 PORT1 PORT2 SP_STAT INT_PEND1\n INT_MASK1 WSR IOS0 IOS1 IOS2 SPlo SPhi\n R1A R1B R1C R1D R1E R1F\n R20 R21 R22 R23 R24 R25 R26 R27\n R28 R29 R2A R2B R2C R2D R2E R2F\n R30 R31 R32 R33 R34 R35 R36 R37\n R38 R39 R3A R3B R3C R3D R3E R3F\n R40 R41 R42 R43 R44 R45 R46 R47\n R48 R49 R4A R4B R4C R4D R4E R4F\n R50 R51 R52 R53 R54 R55 R56 R57\n R58 R59 R5A R5B R5C R5D R5E R5F\n R60 R61 R62 R63 R64 R65 R66 R67\n R68 R69 R6A R6B R6C R6D R6E R6F\n R70 R71 R72 R73 R74 R75 R76 R77\n R78 R79 R7A R7B R7C R7D R7E R7F\n R80 R81 R82 R83 R84 R85 R86 R87\n R88 R89 R8A R8B R8C R8D R8E R8F\n R90 R91 R92 R93 R94 R95 R96 R97\n R98 R99 R9A R9B R9C R9D R9E R9F\n RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7\n RA8 RA9 RAA RAB RAC RAD RAE RAF\n RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7\n RB8 RB9 RBA RBB RBC RBD RBE RBF\n RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7\n RC8 RC9 RCA RCB RCC RCD RCE RCF\n RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7\n RD8 RD9 RDA RDB RDC RDD RDE RDF\n RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7\n RE8 RE9 REA REB REC RED REE REF\n RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7\n RF8 RF9 RFA RFB RFC RFD RFE RFF\n];\n\nattach variables [ waop wreg8 dwreg ]\n[\n ZR _ AD_result _ HSI_time _\n HSI_SBUF _ INTERRUPT _ TIMER1 _\n TIMER2 _ PORT01 _ PORT2_SPS _ INT1 _\n WSR_IOS0 _ IOS12 _ SP _\n RW1A _ RW1C _ RW1E _\n RW20 _ RW22 _ RW24 _ RW26 _ RW28 _ RW2A _ RW2C _ RW2E _\n RW30 _ RW32 _ RW34 _ RW36 _ RW38 _ RW3A _ RW3C _ RW3E _\n RW40 _ RW42 _ RW44 _ RW46 _ RW48 _ RW4A _ RW4C _ RW4E _\n RW50 _ RW52 _ RW54 _ RW56 _ RW58 _ RW5A _ RW5C _ RW5E _\n RW60 _ RW62 _ RW64 _ RW66 _ RW68 _ RW6A _ RW6C _ RW6E _\n RW70 _ RW72 _ RW74 _ RW76 _ RW78 _ RW7A _ RW7C _ RW7E _\n RW80 _ RW82 _ RW84 _ RW86 _ RW88 _ RW8A _ RW8C _ RW8E _\n RW90 _ RW92 _ RW94 _ RW96 _ RW98 _ RW9A _ RW9C _ RW9E _\n RWA0 _ RWA2 _ RWA4 _ RWA6 _ RWA8 _ RWAA _ RWAC _ RWAE _\n RWB0 _ RWB2 _ RWB4 _ RWB6 _ RWB8 _ RWBA _ RWBC _ RWBE _\n RWC0 _ RWC2 _ RWC4 _ RWC6 _ RWC8 _ RWCA _ RWCC _ RWCE _\n RWD0 _ RWD2 _ RWD4 _ RWD6 _ RWD8 _ RWDA _ RWDC _ RWDE _\n RWE0 _ RWE2 _ RWE4 _ RWE6 _ RWE8 _ RWEA _ RWEC _ RWEE _\n RWF0 _ RWF2 _ RWF4 _ RWF6 _ RWF8 _ RWFA _ RWFC _ RWFE _\n];\n\nattach variables [iwreg7]\n[\n ZR AD_result HSI_time\n HSI_SBUF INTERRUPT TIMER1\n TIMER2 PORT01 PORT2_SPS INT1\n WSR_IOS0 IOS12 SP\n RW1A RW1C RW1E\n RW20 RW22 RW24 RW26 RW28 RW2A RW2C RW2E\n RW30 RW32 RW34 RW36 RW38 RW3A RW3C RW3E\n RW40 RW42 RW44 RW46 RW48 RW4A RW4C RW4E\n RW50 RW52 RW54 RW56 RW58 RW5A RW5C RW5E\n RW60 RW62 RW64 RW66 RW68 RW6A RW6C RW6E\n RW70 RW72 RW74 RW76 RW78 RW7A RW7C RW7E\n RW80 RW82 RW84 RW86 RW88 RW8A RW8C RW8E\n RW90 RW92 RW94 RW96 RW98 RW9A RW9C RW9E\n RWA0 RWA2 RWA4 RWA6 RWA8 RWAA RWAC RWAE\n RWB0 RWB2 RWB4 RWB6 RWB8 RWBA RWBC RWBE\n RWC0 RWC2 RWC4 RWC6 RWC8 RWCA RWCC RWCE\n RWD0 RWD2 RWD4 RWD6 RWD8 RWDA RWDC RWDE\n RWE0 RWE2 RWE4 RWE6 RWE8 RWEA RWEC RWEE\n RWF0 RWF2 RWF4 RWF6 RWF8 RWFA RWFC RWFE\n];\n\nattach variables [ lreg dlreg ]\n[\n ZR_AD _ _ _ HSI _ _ _ INT_TIMER1 _ _ _\n TIMER2_PORT01 _ _ _ PORT2_INT1 _ _ _\n WSR_IOS012 _ _ _ SPR1A _ _ _\n RL1C _ _ _\n RL20 _ _ _ RL24 _ _ _ RL28 _ _ _ RL2C _ _ _ RL30 _ _ _ RL34 _ _ _ RL38 _ _ _ RL3C _ _ _\n RL40 _ _ _ RL44 _ _ _ RL48 _ _ _ RL4C _ _ _ RL50 _ _ _ RL54 _ _ _ RL58 _ _ _ RL5C _ _ _\n RL60 _ _ _ RL64 _ _ _ RL68 _ _ _ RL6C _ _ _ RL70 _ _ _ RL74 _ _ _ RL78 _ _ _ RL7C _ _ _\n RL80 _ _ _ RL84 _ _ _ RL88 _ _ _ RL8C _ _ _ RL90 _ _ _ RL94 _ _ _ RL98 _ _ _ RL9C _ _ _\n RLA0 _ _ _ RLA4 _ _ _ RLA8 _ _ _ RLAC _ _ _ RLB0 _ _ _ RLB4 _ _ _ RLB8 _ _ _ RLBC _ _ _\n RLC0 _ _ _ RLC4 _ _ _ RLC8 _ _ _ RLCC _ _ _ RLD0 _ _ _ RLD4 _ _ _ RLD8 _ _ _ RLDC _ _ _\n RLE0 _ _ _ RLE4 _ _ _ RLE8 _ _ _ RLEC _ _ _ RLF0 _ _ _ RLF4 _ _ _ RLF8 _ _ _ RLFC _ _ _\n];\n\nimmed8: imm8 is imm8 { export *[const]:1 imm8; }\n\nsimmed8: simm8 is simm8 { export *[const]:1 simm8; }\n\nimmed16: imm16 is imm16 { export *[const]:2 imm16; }\n\nbaop8: baop is baop & baop=0 { local tmp:1 = 0:1; export tmp; }\nbaop8: baop is baop & baop=1 { local tmp:1 = 0:1; export tmp; }\nbaop8: baop is baop { export baop; }\n\nwaop16: waop is waop & waop=0 { local tmp:2 = 0:2; export tmp; }\nwaop16: waop is waop { export waop; }\n\niwreg: iwreg7 is iwreg7 & iwreg7=0 { local tmp:2 = 0:2; export tmp; }\niwreg: iwreg7 is iwreg7 { export iwreg7; }\n\nbreg: breg8 is breg8 & breg8=0 { local tmp:1 = 0:1; export tmp; }\nbreg: breg8 is breg8 & breg8=1 { local tmp:1 = 0:1; export tmp; }\nbreg: breg8 is breg8 { export breg8; }\n\nwreg: wreg8 is wreg8 & wreg8=0 { local tmp:2 = 0:2; export tmp; }\nwreg: wreg8 is wreg8 { export wreg8; }\n\n# See reference manual pp. 29-30 and note 1 on page 113\n# 1-byte operands\noper8: baop8 is aa=0x0; baop8 { export baop8; } #direct\noper8: \"#\"immed8 is aa=0x1; immed8 { export immed8; } #immediate\noper8: \"[\"iwreg\"]\" is aa=0x2; iwreg & addbit8=0 {\n\tlocal tmp = iwreg;\n\texport *[RAM]:1 tmp;\n} #indirect\noper8: \"[\"iwreg\"]+\" is aa=0x2; iwreg & addbit8=1 {\n\tlocal tmp = iwreg;\n\tiwreg = iwreg + 1;\n\texport *[RAM]:1 tmp;\n} #indirect+\noper8: simmed8\"[\"iwreg\"]\" is aa=0x3; iwreg & addbit8=0; simmed8 {\n\tlocal tmp = iwreg;\n\ttmp = tmp + sext(simmed8);\n\texport *[RAM]:1 tmp;\n} #indexed short\noper8: immed16\", LOOKUP[\"iwreg\"]\" is aa=0x3; iwreg & addbit8=1; immed16 {\n\tlocal tmp = iwreg;\n\ttmp = tmp + immed16;\n\texport *[RAM]:1 tmp;\n} #indexed long\n\n# 2-byte operands\noper16: waop16 is aa=0x0; waop16 { export waop16; } #direct\noper16: \"#\"immed16 is aa=0x1; immed16 { export immed16; } #immediate\noper16: \"[\"iwreg\"]\" is aa=0x2; iwreg & addbit8=0 {\n\tlocal tmp = iwreg;\n\texport *[RAM]:2 tmp;\n} #indirect\noper16: \"[\"iwreg\"]+\" is aa=0x2; iwreg & addbit8=1 {\n\tlocal tmp = iwreg;\n\tiwreg = iwreg + 2;\n\texport *[RAM]:2 tmp;\n} #indirect\noper16: simmed8\"[\"iwreg\"]\" is aa=0x3; iwreg & addbit8=0; simmed8 {\n\tlocal tmp = iwreg;\n\ttmp = tmp + sext(simmed8);\n\texport *[RAM]:2 tmp;\n} #indexed short\noper16: immed16\", TABLE[\"iwreg\"]\" is aa=0x3 ; iwreg & addbit8=1; immed16 {\n\tlocal tmp = iwreg;\n\ttmp = tmp + immed16;\n\texport *[RAM]:2 tmp;\n} #indexed long\n\n# range -128 through +127\njmpdest: reloc is simm8 [ reloc = inst_next + simm8; ] { export *:1 reloc; }\n\n# range -1023 through 1024\njmpdest11: reloc is jmp11_hi & jmp11_lo [reloc = inst_next + ((jmp11_hi << 8) | jmp11_lo);] { export *:2 reloc; }\njmpdest16: reloc is disp16 [reloc = inst_next + disp16;] { export *:2 reloc; }\n\n################################################################\n# Pseudo Instructions\n################################################################\n#define pcodeop blockMove;\ndefine pcodeop idlePowerdown;\ndefine pcodeop normalize;\n\n################################################################\n# Macros\n################################################################\nmacro push(val) {\n\tSP = SP - 2;\n\t*:2 SP = val;\n}\n\nmacro pop(val) {\n\tval = *:2 SP;\n\tSP = SP + 2;\n}\n\nmacro resetFlags() {\n\tPSW = 0;\n}\n\nmacro resultFlags(res) {\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(C) = 0;\n\t$(V) = 0;\n}\n\nmacro additionFlags(op1, op2, res) {\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(C) = carry(op1, op2);\n\t$(V) = scarry(op1, op2);\n\t$(VT) = $(V) | $(VT);\n}\n\nmacro subtractFlags(op1, op2, res) {\n\t$(N) = (res s< 0);\n\t$(Z) = (res == 0);\n\t$(C) = (op1 < op2) == 0;\n\t$(V) = sborrow(op1, op2);\n\t$(VT) = $(VT) | $(V);\n}\n\nmacro stickyFlagW(source, shift) {\n\tlocal mask:2 = -1;\n\tmask = (mask >> (16 - shift + 1)) * zext(shift > 1);\n\tlocal result:2 = source & mask;\n\n\t$(ST) = (result != 0);\n}\n\nmacro stickyFlagB(source, shift) {\n\tlocal mask:1 = -1;\n\tmask = (mask >> (8 - shift + 1)) * (shift > 1);\n\tlocal result:1 = source & mask;\n\n\t$(ST) = (result != 0);\n}\n\nmacro stickyFlagL(source, shift) {\n\tlocal mask:4 = -1;\n\tmask = (mask >> (32 - shift + 1)) * zext(shift > 1);\n\tlocal result:4 = source & mask;\n\n\t$(ST) = (result != 0);\n}\n\nmacro blockMove(ptrs, cntreg) {\n\tlocal tsptr:4 = (ptrs & 0xffff0000) >> 0x10;\n\tlocal srcPtr:2 = tsptr(2);\n\tlocal dstPtr:2 = ptrs(2);\n\tlocal cnt = cntreg;\n\t\n\tlocal data:2 = *srcPtr;\n\t*dstPtr = data;\n\tsrcPtr = srcPtr + 2;\n\tdstPtr = dstPtr + 2;\n\tcnt = cnt - 1;\n\tif cnt != 0 goto ;\n\tptrs = zext(dstPtr) | (zext(srcPtr) << 0x10);\n}\n\nmacro setShiftLeftCarryFlag(shiftee,amount) {\n\tshifting:1 = amount != 0;\n\tlocal tmp = ((shiftee >> (16-amount)) & 1);\n\t$(C) = (shifting & tmp:1);\n}\n\nmacro setShiftRightCarryFlag(shiftee,amount) {\n\tshifting:1 = amount != 0;\n\tlocal tmp = (shiftee >> (amount-1)) & 1;\n\t$(C) = (shifting & tmp:1);\n}\n\nmacro setSignedShiftRightCarryFlag(shiftee,amount) {\n\tshifting:1 = amount != 0;\n\tlocal tmp = (shiftee s>> (amount-1)) & 1;\n\t$(C) = (shifting & tmp:1);\n}\n\n################################################################\n# Constructors\n################################################################\n# 2-op\n:ADD wreg, oper16 is op6=0x19 ... & oper16; wreg {\n\tlocal tmpD = wreg + oper16;\n\tadditionFlags(wreg, oper16, tmpD);\n\twreg = tmpD;\n}\n\n# 3 op\n:ADD dwreg, wreg, oper16 is op6=0x11 ... & oper16; wreg; dwreg {\n\tlocal tmpD = wreg + oper16;\n\tdwreg = tmpD;\n\tadditionFlags(wreg, oper16, tmpD);\n}\n\n# 2-op\n:ADDB breg, oper8 is op6=0x1d ... & oper8; breg {\n\tlocal tmp = breg + oper8;\n\tadditionFlags(breg, oper8, tmp);\n\tbreg = tmp;\n}\n\n:ADDB dbreg, breg, oper8 is op6=0x15 ... & oper8; breg; dbreg {\n\tlocal tmp = breg + oper8;\n\tdbreg = tmp;\n\tadditionFlags(breg, oper8, tmp);\n}\n\n:ADDC wreg, oper16 is op6=0x29 ... & oper16; wreg {\n\tlocal tmp = oper16 + zext($(C));\n\tlocal res = wreg + tmp;\n\tlocal oldz = $(Z);\n\tadditionFlags(wreg, tmp, res);\n\t$(Z) = oldz & $(Z); # only cleared, not set\n\twreg = res;\n}\n\n:ADDCB breg, oper8 is op6=0x2d ... & oper8; breg {\n\tlocal tmp = oper8 + $(C);\n\tlocal res =breg + tmp;\n\tlocal oldz = $(Z);\n\tadditionFlags(breg, tmp, res);\n\t$(Z) = oldz & $(Z); # only cleared, not set\n\tbreg = res;\n}\n\n# 2-op\n:AND wreg, oper16 is op6=0x18 ... & oper16; wreg {\n\twreg = wreg & oper16;\n\tresultFlags(wreg);\n}\n\n# 3-op\n:AND dwreg, wreg, oper16 is op6=0x10 ... & oper16; wreg; dwreg {\n\tdwreg = wreg & oper16;\n\tresultFlags(dwreg);\n}\n\n:ANDB breg, oper8 is op6=0x1c ... & oper8; breg {\n\tbreg = breg & oper8;\n\tresultFlags(breg);\n}\n\n:ANDB dbreg, breg, oper8 is op6=0x14 ... & oper8; breg; dbreg {\n\tdbreg = breg & oper8;\n\tresultFlags(dbreg);\n}\n\n:BMOV lreg, wreg is op8=0xc1; wreg ; lreg {\n\tblockMove(lreg, wreg);\n}\n\n:BMOVI lreg, wreg is op8=0xcd; wreg; lreg {\n\tblockMove(lreg, wreg);\n}\n\n:BR [ wreg ] is op8=0xe3; wreg {\n\tgoto [wreg];\n}\n\n:CLR wreg is op8=0x1; wreg {\n\twreg = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\t$(C) = 0;\n\t$(V) = 0;\n}\n\n:CLRB breg is op8=0x11; breg {\n\tbreg = 0;\n\t$(Z) = 1;\n\t$(N) = 0;\n\t$(C) = 0;\n\t$(V) = 0;\n}\n\n:CLRC is op8=0xf8 {\n\t$(C) = 0;\n}\n\n:CLRVT is op8=0xfc {\n\t$(VT) = 0;\n}\n\n:CMP wreg, oper16 is op6=0x22 ... & oper16; wreg {\n\top1:2 = oper16;\n\ttmp:2 = wreg - op1;\n\tsubtractFlags(wreg, op1, tmp);\n}\n\n:CMPB breg, oper8 is op6=0x26 ... & oper8; breg {\n\top1:1 = oper8;\n\ttmp:1 = breg - op1;\n\tsubtractFlags(breg, op1, tmp);\n}\n\n@if defined(C196KB) || defined(C196KC)\n:CMPL dlreg, lreg is op8=0xc5; lreg; dlreg {\n\top1:4 = lreg;\n\ttmp:4 = dlreg - op1;\n\t$(N) = (tmp s< 0);\n\t$(Z) = (tmp == 0);\n\t$(C) = scarry(dlreg, op1);\n\t$(V) = (((dlreg & ~op1 & ~tmp) | (~dlreg & op1 & tmp)) & 0x80000000 ) != 0;\n\t$(VT) = $(VT) | $(V);\n}\n\n@endif\n\n:DEC wreg is op8=0x05; wreg {\n\tlocal tmp = wreg - 1;\n\tsubtractFlags(wreg, 1, tmp);\n\twreg = tmp;\n}\n\n:DECB breg is op8=0x15; breg {\n\tlocal tmp = breg - 1;\n\tsubtractFlags(breg, 1, tmp);\n\tbreg = tmp;\n}\n\n:DI is op8=0xfa {\n\t$(I) = 0;\n}\n\n:DIV lreg, oper16 is op8=0xfe; op6=0x23 ... & oper16; lreg {\n\tlocal num = lreg;\n\tlocal den = oper16;\n\tlocal div = num s/ sext(den);\n\tlocal rem = num s% sext(den);\n\tlreg = zext(div:2 << 16) | rem;\n@if defined(C196KB) || defined(C196KC)\n\t$(V) = ((div s> 0x7fff) | (div s< 0x8001));\n@endif\n\t$(VT) = $(VT) | $(V);\n}\n\n:DIVB wreg, oper8 is op8=0xfe; op6=0x27 ... & oper8; wreg {\n\tlocal num = wreg;\n\tlocal den = oper8;\n\tlocal div = num s/ sext(den);\n\tlocal rem = num s% sext(den);\n\twreg = zext(div:1 << 8) | rem;\n@if defined(C196KB) || defined(C196KC)\n\t$(V) = ((div s> 0x7f) | (div s< 0x81));\n@endif\n\t$(VT) = $(VT) | $(V);\n}\n\n:DIVU lreg, oper16 is op6=0x23 ... & oper16; lreg {\n\tlocal num = lreg;\n\tlocal den = oper16;\n\tlocal div = num / zext(den);\n\tlocal rem = num % zext(den);\n\tlreg = zext(div:2 << 16) | rem;\n\t$(V) = (div > 0xffff);\n\t$(VT) = $(VT) | $(V);\n}\n\n:DIVUB wreg, oper8 is op6=0x27 ... & oper8; wreg {\n\tlocal num = wreg;\n\tlocal den = oper8;\n\tlocal div = num / zext(den);\n\tlocal rem = num % zext(den);\n\twreg = zext(div:1 << 8) | rem;\n\t$(V) = (div > 0xff);\n\t$(VT) = $(VT) | $(V);\n}\n\n:DJNZ breg, jmpdest is op8=0xe0; breg; jmpdest {\n\tbreg = breg - 1;\n\tif (breg != 0) goto jmpdest;\n}\n\n@if defined(C196KB) || defined(C196KC)\n:DJNZW wreg, jmpdest is op8=0xe1; wreg; jmpdest {\n\twreg = wreg - 1;\n\tif (wreg != 0) goto jmpdest;\n}\n\n@endif\n\n@if defined(C196KC)\n:DPTS is op8=0xec {\n\t$(PSE) = 0;\n}\n\n@endif\n\n:EI is op8=0xfb {\n\t$(I) = 1;\n}\n\n@if defined(C196KC)\n:EPTS is op8=0xed {\n\t$(PSE) = 1;\n}\n\n@endif\n\n:EXT lreg is op8=0x6; lreg {\n\ttmp:4 = lreg & 0xffff;\n\tlreg = sext(tmp);\n\tresultFlags(lreg);\n}\n\n:EXTB wreg is op8=0x16; wreg {\n\ttmp:2 = wreg & 0xff;\n\twreg = sext(tmp);\n\tresultFlags(wreg);\n}\n\n:INC wreg is op8=0x7; wreg {\n\tlocal tmp = wreg + 1;\n\tadditionFlags(wreg, 1, tmp);\n\twreg = tmp;\n}\n\n:INCB breg is op8=0x17; breg {\n\tlocal tmp = breg + 1;\n\tadditionFlags(breg, 1, tmp);\n\tbreg = tmp;\n}\n\n@if defined(C196KB) || defined(C196KC)\n:IDLPD \"#\"immed8 is op8=0xf6; immed8 {\n\tidlePowerdown();\n\t$(Z) = 0;\n\t$(N) = 0;\n\t$(C) = 0;\n\t$(V) = 0;\n\t$(VT) = 0;\n\t$(ST) = 0;\n}\n\n@endif\n\n:JBC breg, bitno, jmpdest is op5=0x6 & bitno; breg; jmpdest {\n\tlocal bit = (breg >> bitno) & 0x1;\n\tif (bit == 0) goto jmpdest;\n}\n\n:JBS breg, bitno, jmpdest is op5=0x7 & bitno; breg; jmpdest {\n\tlocal bit = (breg >> bitno) & 0x1;\n\tif (bit == 1) goto jmpdest;\n}\n\ncc: \"NST\" is cond=0 { tmp:1 = ($(ST) == 0); export tmp; }\ncc: \"NH\" is cond=1 { tmp:1 = (($(C) == 0) | ($(Z) == 1)); export tmp; }\ncc: \"GT\" is cond=2 { tmp:1 = (($(N) == 0) & ($(Z) == 0)); export tmp; }\ncc: \"NC\" is cond=3 { tmp:1 = ($(C) == 0); export tmp; }\ncc: \"NVT\" is cond=4 { tmp:1 = ($(VT) == 0); $(VT) = 0; export tmp; }\ncc: \"NV\" is cond=5 { tmp:1 = ($(V) == 0); export tmp; }\ncc: \"GE\" is cond=6 { tmp:1 = ($(N) == 0); export tmp; }\ncc: \"NE\" is cond=7 { tmp:1 = ($(Z) == 0); export tmp; }\ncc: \"ST\" is cond=8 { tmp:1 = ($(ST) == 1); export tmp; }\ncc: \"H\" is cond=9 { tmp:1 = (($(C) == 1) & ($(Z) == 0)); export tmp; }\ncc: \"LE\" is cond=10 { tmp:1 = (($(N) == 1) | ($(Z) == 1)); export tmp; }\ncc: \"C\" is cond=11 { tmp:1 = ($(C) == 1); export tmp; }\ncc: \"VT\" is cond=12 { tmp:1 = ($(VT) == 1); $(VT) = 0; export tmp; }\ncc: \"V\" is cond=13 { tmp:1 = ($(V) == 1); export tmp; }\ncc: \"LT\" is cond=14 { tmp:1 = ($(N) == 1); export tmp; }\ncc: \"E\" is cond=15 { tmp:1 = ($(Z) == 1); export tmp; }\n\n:J^cc jmpdest is op4=0xd & cc; jmpdest\n{if (cc) goto jmpdest;}\n\n\n:LCALL jmpdest16 is op8=0xef; jmpdest16 {\n\tret:2 = inst_next;\n\tpush(ret);\n\tcall jmpdest16;\n} \n\n:LD wreg, oper16 is op6=0x28 ... & oper16; wreg {\n\twreg = oper16;\n}\n\n:LDB breg, oper8 is op6=0x2c ... & oper8; breg {\n\tbreg = oper8;\n}\n\n:LDBSE wreg, oper8 is op6=0x2f ... & oper8; wreg {\n\twreg = sext(oper8);\n}\n\n:LDBZE wreg, oper8 is op6=0x2b ... & oper8; wreg {\n\twreg = zext(oper8);\n}\n\n:LJMP jmpdest16 is op8=0xe7; jmpdest16 {\n\tgoto jmpdest16;\n}\n\n# 2-op\n:MUL lreg, oper16 is op8=0xfe; op6=0x1b ... & oper16; lreg {\n\ttmpD:4 = sext(lreg:2);\n\ttmpS:4 = sext(oper16);\n\ttmpD = tmpD * tmpS;\n\tlreg = tmpD;\n}\n\n# 3-op\n:MUL lreg, wreg, oper16 is op8=0xfe; op6=0x13 ... & oper16; wreg; lreg {\n\ttmpD:4 = sext(wreg);\n\ttmpS:4 = sext(oper16);\n\ttmpD = tmpD * tmpS;\n\tlreg = tmpD;\n}\n\n# 2-op\n:MULB wreg, oper8 is op8=0xfe; op6=0x1f ... & oper8; wreg {\n\ttmpD:2 = sext(wreg:1);\n\ttmpS:2 = sext(oper8);\n\ttmpD = tmpD * tmpS;\n\twreg = tmpD;\n}\n\n# 3-op\n:MULB wreg, breg, oper8 is op8=0xfe; op6=0x17 ... & oper8; breg; wreg {\n\ttmpD:2 = sext(breg);\n\ttmpS:2 = sext(oper8);\n\ttmpD = tmpD * tmpS;\n\twreg = tmpD;\n}\n\n# 2-op\n:MULU lreg, oper16 is op6=0x1b ... & oper16; lreg {\n\ttmpD:4 = zext(lreg:2);\n\ttmpS:4 = zext(oper16);\n\ttmpD = tmpD * tmpS;\n\tlreg = tmpD;\n}\n\n# 3-op\n:MULU lreg, wreg, oper16 is op6=0x13 ... & oper16; wreg; lreg {\n\ttmpD:4 = zext(wreg);\n\ttmpS:4 = zext(oper16);\n\ttmpD = tmpD * tmpS;\n\tlreg = tmpD;\n}\n\n# 2-op\n:MULUB wreg, oper8 is op6=0x1f ... & oper8; wreg {\n\ttmpD:2 = zext(wreg:1);\n\ttmpS:2 = zext(oper8);\n\ttmpD = tmpD * tmpS;\n\twreg = tmpD;\n}\n\n# 3-op\n:MULUB wreg, breg, oper8 is op6=0x17 ... & oper8; breg; wreg {\n\tlocal tmpD:2 = zext(breg);\n\tlocal tmpS:2 = zext(oper8);\n\ttmpD = tmpD * tmpS;\n\twreg = tmpD;\n}\n\n:NEG wreg is op8=0x03; wreg {\n\tlocal tmp:2 = -wreg;\n\tlocal zero:2 = 0;\n\tsubtractFlags(zero, wreg, tmp);\n\twreg = tmp;\n}\n\n:NEGB breg is op8=0x13; breg {\n\tlocal tmp:1 = -breg;\n\tlocal zero:1 = 0;\n\tsubtractFlags(zero, breg, tmp);\n\tbreg = tmp;\n}\n\n:NOP is op8=0xfd { } #NOP\n\n:NORML lreg, breg is op8=0xf; breg; lreg {\n\t#The LONG-INTEGER operand is normalized; i.e., it is shifted to the left until its\n\t#most significant bit is 1. If the most significant bit is still 0 after 31 shifts, the\n\t#process stops and the zero flag is set. The number of shifts actually performed\n\t#is stored in the second operand.\n\tnormalize(lreg, breg);\n\t$(Z) = (lreg == 0);\n\t$(C) = 0;\n# $(N) is undefined\n}\n\n:NOT wreg is op8 = 0x2; wreg {\n\twreg = ~wreg;\n\tresultFlags(wreg);\n}\n\n:NOTB breg is op8=0x12; breg {\n\tbreg = ~breg;\n\tresultFlags(breg);\n}\n\n:OR wreg, oper16 is op6=0x20 ... & oper16; wreg {\n\ttmpD:2 = wreg;\n\ttmpS:2 = oper16;\n\ttmpD = tmpD | tmpS;\n\twreg = tmpD;\n\tresultFlags(wreg);\n}\n\n:ORB breg, oper8 is op6=0x24 ... & oper8; breg {\n\ttmpD:1 = breg;\n\ttmpS:1 = oper8;\n\ttmpD = tmpD | tmpS;\n\tbreg = tmpD;\n\tresultFlags(breg);\n}\n\n:POP oper16 is op6=0x33 ... & oper16 {\n\tlocal result:2 = 0;\n\tpop(result);\n\toper16 = result;\n}\n\n@if defined(C196KB) || defined(C196KC)\n:POPA is op8=0xf5 {\n\tlocal result:2 = 0;\n\tpop(result);\n\tWSR = result:1 & 0xff;\n\tlocal resultHi = result >> 8;\n\tINT_MASK1 = resultHi:1;\n\tpop(result);\n\tINT_MASK = result:1 & 0xff;\n\tresultHi = result >> 8;\n\tPSW = resultHi:1;\n}\n\n@endif\n\n:POPF is op8=0xf3 {\n\tlocal result:2 = 0;\n\tpop(result);\n\tPSW = zext(result:1);\n\tlocal resultHi = result >> 8;\n\tINT_MASK = resultHi:1;\n}\n\n:PUSH oper16 is op6=0x32 ... & oper16 {\n\tval:2 = oper16;\n\tpush(val);\n}\n\n@if defined(C196KB) || defined(C196KC)\n:PUSHA is op8=0xf4 {\n\tlocal val:2 = (zext(INT_MASK) << 8) | zext(WSR);\n\tpush(val);\n\tval = (zext(INT_MASK) << 8) | zext(PSW);\n\tpush(val);\n\tresetFlags();\n}\n\n@endif\n\n:PUSHF is op8=0xf2 {\n\tval:2 = (zext(INT_MASK) << 8) | zext(PSW);\n\tpush(val);\n\tresetFlags();\n}\n\n:RET is op8=0xf0 {\n\tlocal retDest:2 = 0;\n\tpop(retDest);\n\treturn [retDest];\n}\n\n:RST is op8=0xff {\n\tresetFlags();\n\tPC = 0x2080;\n\tgoto [PC];\n}\n\n:SCALL jmpdest11 is op16=0x5 & jmpdest11 {\n\tret:2 = inst_next;\n\tpush(ret);\n\tcall jmpdest11;\n}\n\n:SETC is op8=0xf9 {\n\t$(C) = 1;\n}\n\n:SHL wreg, \"#\"immed8 is op8=0x09; immed8 & (highb = 0x0); wreg {\n\tlocal source = wreg;\n\tlocal shift = immed8;\n\tsetShiftLeftCarryFlag(source, shift);\n\tlocal res = source << shift;\n\t$(Z) = (res == 0);\n\t$(V) = 0;\n\t$(VT) = $(VT) | $(V);\n\twreg = res;\n}\n\n:SHL wreg, breg is op8=0x09; breg & (highb != 0x0); wreg {\n\tlocal source = wreg;\n\tlocal shift = breg;\n\tsetShiftLeftCarryFlag(source, shift);\n\tlocal res = source << shift;\n\t$(Z) = (res == 0);\n\t$(V) = 0;\n\t$(VT) = $(VT) | $(V);\n\twreg = res;\n}\n\n:SHLB dbreg, \"#\"immed8 is op8=0x19; immed8 & (highb = 0x0); dbreg {\n\tlocal source = dbreg;\n\tlocal shift = immed8;\n\tsetShiftLeftCarryFlag(source, shift);\n\tlocal res = source << shift;\n\t$(Z) = (res == 0);\n\t$(V) = 0;\n\t$(VT) = $(VT) | $(V);\n\tdbreg = res;\n}\n\n:SHLB dbreg, breg is op8=0x19; breg & (highb != 0x0); dbreg {\n\tlocal source = dbreg;\n\tlocal shift = breg;\n\tsetShiftLeftCarryFlag(source, shift);\n\tlocal res = source << shift;\n\t$(Z) = (res == 0);\n\t$(V) = 0;\n\t$(VT) = $(VT) | $(V);\n\tdbreg = res;\n}\n\n:SHLL lreg, \"#\"immed8 is op8=0x0d; immed8 & (highb = 0x0); lreg {\n\tlocal source = lreg;\n\tlocal shift = immed8;\n\tsetShiftLeftCarryFlag(source, shift);\n\tlocal res = source << shift;\n\t$(Z) = (res == 0);\n\t$(V) = 0;\n\t$(VT) = $(VT) | $(V);\n\tlreg = res;\n}\n\n:SHLL lreg, breg is op8=0x0d; breg & (highb != 0x0); lreg {\n\tlocal source = lreg;\n\tlocal shift = breg;\n\tsetShiftLeftCarryFlag(source, shift);\n\tlocal res = source << shift;\n\t$(Z) = (res == 0);\n\t$(V) = 0;\n\t$(VT) = $(VT) | $(V);\n\tlreg = res;\n}\n\n:SHR wreg, \"#\"immed8 is op8=0x08; immed8 & (highb = 0x0); wreg {\n\tlocal source = wreg;\n\tlocal shift = immed8;\n\t$(ST) = 0;\n\tsetShiftRightCarryFlag(source, shift);\n\tlocal res = source >> shift;\n\t$(Z) = (res == 0);\n\t$(N) = 0;\n\t$(V) = 0;\n\twreg = res;\n\tstickyFlagW(source, shift);\n}\n\n:SHR wreg, breg is op8=0x08; breg & (highb != 0x0); wreg {\n\tlocal source = wreg;\n\tlocal shift = breg;\n\tsetShiftRightCarryFlag(source, shift);\n\tlocal res = source >> shift;\n\t$(Z) = (res == 0);\n\t$(N) = 0;\n\t$(V) = 0;\n\twreg = res;\n\tstickyFlagW(source, shift);\n}\n\n:SHRA wreg, \"#\"immed8 is op8=0x0a; immed8 & (highb = 0x0); wreg {\n\tlocal source = wreg;\n\tlocal shift = immed8;\n\tsetSignedShiftRightCarryFlag(source, shift);\n\tlocal res = source s>> shift;\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(V) = 0;\n\twreg = res;\n\tstickyFlagW(source, shift);\n}\n\n:SHRA wreg, breg is op8=0x0a; breg & (highb != 0x0); wreg {\n\tlocal source = wreg;\n\tlocal shift = breg;\n\tsetSignedShiftRightCarryFlag(source, shift);\n\tlocal res = source s>> shift;\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(V) = 0;\n\twreg = res;\n\tstickyFlagW(source, shift);\n}\n\n:SHRAB dbreg, \"#\"immed8 is op8=0x1a; immed8 & (highb = 0x0); dbreg {\n\tlocal source = dbreg;\n\tlocal shift = immed8;\n\tsetSignedShiftRightCarryFlag(source, shift);\n\tlocal res = source s>> shift;\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(V) = 0;\n\tdbreg = res;\n\tstickyFlagB(source, shift);\n}\n\n:SHRAB dbreg, breg is op8=0x1a; breg & (highb != 0x0); dbreg {\n\tlocal source = dbreg;\n\tlocal shift = breg;\n\tsetSignedShiftRightCarryFlag(source, shift);\n\tlocal res = source s>> shift;\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(V) = 0;\n\tdbreg = res;\n\tstickyFlagB(source, shift);\n}\n\n:SHRAL lreg, \"#\"immed8 is op8=0x0e; immed8 & (highb = 0x0); lreg {\n\tlocal source = lreg;\n\tlocal shift = immed8;\n\tsetSignedShiftRightCarryFlag(source, shift);\n\tlocal res = source s>> shift;\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(V) = 0;\n\tlreg = res;\n\tstickyFlagL(source, shift);\n}\n\n:SHRAL lreg, breg is op8=0x0e; breg & (highb != 0x0); lreg {\n\tlocal source = lreg;\n\tlocal shift = breg;\n\tsetSignedShiftRightCarryFlag(source, shift);\n\tlocal res = source s>> shift;\n\t$(Z) = (res == 0);\n\t$(N) = (res s< 0);\n\t$(V) = 0;\n\tlreg = res;\n\tstickyFlagL(source, shift);\n}\n\n:SHRB dbreg, \"#\"immed8 is op8=0x18; immed8 & (highb = 0x0); dbreg {\n\tlocal source = dbreg;\n\tlocal shift = immed8;\n\tsetShiftRightCarryFlag(source, shift);\n\tlocal res = source >> shift;\n\t$(Z) = (res == 0);\n\t$(N) = 0;\n\t$(V) = 0;\n\tdbreg = res;\n\tstickyFlagB(source, shift);\n}\n\n:SHRB dbreg, breg is op8=0x18; breg & (highb != 0x0); dbreg {\n\tlocal source = dbreg;\n\tlocal shift = breg;\n\tsetShiftRightCarryFlag(source, shift);\n\tlocal res = source >> shift;\n\t$(Z) = (res == 0);\n\t$(N) = 0;\n\t$(V) = 0;\n\tdbreg = res;\n\tstickyFlagB(source, shift);\n}\n\n:SHRL lreg, \"#\"immed8 is op8=0x0c; immed8 & (highb = 0x0); lreg {\n\tlocal source = lreg;\n\tlocal shift = immed8;\n\tsetShiftRightCarryFlag(source, shift);\n\tlocal res = source >> shift;\n\t$(Z) = (res == 0);\n\t$(N) = 0;\n\t$(V) = 0;\n\tlreg = res;\n\tstickyFlagL(source, shift);\n}\n\n:SHRL lreg, breg is op8=0x0c; breg & (highb != 0x0); lreg {\n\tlocal source = lreg;\n\tlocal shift = breg;\n\tsetShiftRightCarryFlag(source, shift);\n\tlocal res = source >> shift;\n\t$(Z) = (res == 0);\n\t$(N) = 0;\n\t$(V) = 0;\n\tlreg = res;\n\tstickyFlagL(source, shift);\n}\n\n:SJMP jmpdest11 is op16=0x4 & jmpdest11 {\n\tgoto jmpdest11;\n}\n\n:SKIP is op8=0x00 {\n\tlocal tmp:1 = 0;\n\ttmp = tmp; # avoid warning\n} #2-byte NOP\n\n:ST wreg, oper16 is op6=0x30 ... & oper16; wreg {\n\toper16 = wreg;\n}\n\n:STB breg, oper8 is op6=0x31 ... & oper8; breg {\n\toper8 = breg;\n}\n\n# 2-op\n:SUB wreg, oper16 is op6=0x1a ... & oper16; wreg {\n\tlocal tmp = wreg - oper16;\n\tsubtractFlags(wreg, oper16, tmp);\n\twreg = tmp;\n}\n\n# 3 op\n:SUB dwreg, wreg, oper16 is op6=0x12 ... & oper16; wreg; dwreg {\n\tdwreg = wreg - oper16;\n\tsubtractFlags(wreg, oper16, dwreg);\n}\n\n# 2-op\n:SUBB breg, oper8 is op6=0x1e ... & oper8; breg {\n\tlocal tmp = breg - oper8;\n\tsubtractFlags(breg, oper8, tmp);\n}\n\n:SUBB dbreg, breg, oper8 is op6=0x16 ... & oper8; breg; dbreg {\n\tdbreg = breg - oper8;\n\tsubtractFlags(breg, oper8, dbreg);\n}\n\n:SUBC wreg, oper16 is op6=0x2a ... & oper16; wreg {\n\tlocal tmp = wreg - oper16 - zext(1 - $(C));\n\tlocal oldz = $(Z);\n\tsubtractFlags(wreg, oper16-zext(1-$(C)), tmp);\n\twreg = tmp;\n\t$(Z) = oldz & $(Z);\n}\n\n:SUBCB breg, oper8 is op6=0x2e ... & oper8; breg {\n\tlocal tmp = breg - oper8 - zext(1 - $(C));\n\tlocal oldz = $(Z);\n\tsubtractFlags(breg, oper8-zext(1-$(C)), tmp);\n\tbreg = tmp;\n\t$(Z) = oldz & $(Z);\n}\n\n@if defined(C196KC)\n:TIJMP dwreg, \"[\"wreg\"]\" \"#\"immed8 is op8=0xe2; wreg; immed8; dwreg {\n\tlocal index = *wreg;\n\tlocal jmpOffset = zext(index & immed8);\n\tlocal tBase = dwreg;\n\tlocal destX = (jmpOffset << 1) + tBase;\n\tlocal jmpDest = *:2 destX;\n\n\tgoto [jmpDest];\n}\n\n@endif\n\n:TRAP is op8=0xf7 {\n\tret:2 = inst_next;\n\tpush(ret);\n\ttrapv:2 = 0x2010;\n\tPC = *trapv;\n\tgoto [PC];\n}\n\n:XOR wreg, oper16 is op6=0x21 ... & oper16; wreg {\n\ttmpD:2 = wreg;\n\ttmpS:2 = oper16;\n\ttmpD = tmpD ^ tmpS;\n\twreg = tmpD;\n\tresultFlags(wreg);\n}\n\n@if defined(C196KC)\n:XCH wreg, waop16 is op8=0x04; waop16; wreg {\n\tlocal tmp = wreg;\n\twreg = waop16;\n\twaop16 = tmp;\n}\n\n:XCH wreg, immed8\", TABLE[\"iwreg\"]\" is op8=0x0b; iwreg & addbit8=0; immed8; wreg {\n\tlocal tmp = iwreg;\n\ttmp = tmp + sext(immed8);\n\tlocal val = *[RAM]:2 tmp;\n\n\tlocal wreg_tmp = wreg;\n\twreg = val;\n\t*[RAM]:2 tmp = wreg_tmp;\n}\n\n:XCH wreg, immed16\", TABLE[\"iwreg\"]\" is op8=0x0b; iwreg & addbit8=1; immed16; wreg {\n\tlocal tmp = iwreg;\n\ttmp = tmp + immed16;\n\tlocal val = *[RAM]:2 tmp;\n\n\tlocal wreg_tmp = wreg;\n\twreg = val;\n\t*[RAM]:2 tmp = wreg_tmp;\n}\n\n@endif\n\n@if defined(C196KC)\n:XCHB breg, baop8 is op8=0x14 ; baop8; breg {\n\tlocal tmp = breg;\n\tbreg = baop8;\n\tbaop8 = tmp;\n}\n\n:XCHB breg, immed8\", TABLE[\"iwreg\"]\" is op8=0x1b ; iwreg & addbit8=0; immed8; breg {\n\tlocal tmp = iwreg;\n\ttmp = tmp + sext(immed8);\n\tlocal val = *[RAM]:1 tmp;\n\n\tlocal wreg_tmp = breg;\n\tbreg = val;\n\t*[RAM]:1 tmp = wreg_tmp;\n}\n\n:XCHB breg, immed16\", TABLE[\"iwreg\"]\" is op8=0x1b ; iwreg & addbit8=1; immed16; breg {\n\tlocal tmp = iwreg;\n\ttmp = tmp + sext(immed16);\n\tlocal val = *[RAM]:1 tmp;\n\n\tlocal wreg_tmp = breg;\n\tbreg = val;\n\t*[RAM]:1 tmp = wreg_tmp;\n}\n\n@endif\n\n:XORB breg, oper8 is op6=0x25 ... & oper8; breg {\n\ttmpD:1 = breg;\n\ttmpS:1 = oper8;\n\ttmpD = tmpD ^ tmpS;\n\tbreg = tmpD;\n\tresultFlags(breg);\n}\n\n\n\n" }, { "path": "pypcode/processors/MCS96/data/languages/MCS96.slaspec", "content": "@define C196KB \"1\"\n@define C196KC \"1\"\n\n@include \"MCS96.sinc\"\n" }, { "path": "pypcode/processors/MCS96/data/manuals/MCS96.idx", "content": "@1991_Intel_16-Bit_Embedded_Controller_Handbook.pdf[1991 Intel 16-Bit Embedded Controller Handbook]\nADD, 175\nADDB, 176\nADDC, 177\nADDCB, 177\nAND, 178\nANDB, 179\nBMOV, 180\nBMOVI, 181\nBR, 182\nCLR, 182\nCLRB, 183\nCLRC, 183\nCLRVT, 184\nCMP, 184\nCMPB, 185\nCMPL, 185\nDEC, 186\nDECB, 186\nDI, 186\nDIV, 187\nDIVB 187\nDIVU, 188\nDIVUB, 188\nDJNZ, 189\nDJNZWM 189\nDPTS, 190\nEI, 190\nEPTS, 191\nEXT, 191\nEXTB, 192\nINC, 192\nINCB, 193\nIDLPD, 193\nJBC, 194\nJBS, 195\nJC, 195\nJE, 196\nJGE, 196\nJGT, 197\nJH, 197\nJLE, 198\nJLT, 198\nJNC, 199\nJNE, 199\nJNH, 200\nJNST, 200\nJNV, 201\nJNVT, 201\nJST, 202\nJV, 202\nJVT, 203\nLCALL, 203\nLD, 204\nLDB, 204\nLDBSE, 205\nLDBZE, 205\nLJMP, 206\nMUL, 206\nMULB, 207\nMULU, 208\nMULUB, 209\nNEG, 210\nNEGB, 211\nNOP, 211\nNORML, 212\nNOT, 212\nNOTB, 213\nOR, 213\nORB, 214\nPOP, 214\nPOPA, 215\nPOPF, 215\nPUSH, 216\nPUSHA, 216\nPUSHF, 217\nRET, 217\nRST, 218\nSCALL, 218\nSETC, 219\nSHL, 219\nSHLB, 220\nSHLL, 221\nSHR, 222\nSHRA, 223\nSHRAB, 224\nSHRAL, 225\nSHRB, 226\nSHRL, 227\nSJMP, 228\nSKIP, 228\nST, 229\nSTB, 229\nSUB, 230\nSUBB, 231\nSUBC, 232\nSUBCB, 232\nTIJMP, 233\nTRAP, 234\nXOR, 234\nXCH, 235\nXCHB, 235\nXORB, 236\n" }, { "path": "pypcode/processors/MIPS/data/languages/MIPS.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n \n\n \n\n\n\n \n\t \n \n\n \n \n \n\t \n\t \n\n \n\t \n\n \n \n\n \n \n\n \n \n \n \n \n \n \n \n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n\n \n \n \n\n \n\t\n \n\n\t\n \n\n \n\n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips.dwarf", "content": "\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t \n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips.ldefs", "content": "\n\n \n MIPS32 32-bit addresses, big endian, with mips16e\n \n \n \n \n \n \n \n \n \n \n \n MIPS32 32-bit addresses, little endian, with mips16e\n \n \n \n \n \n \n \n \n \n \n \n MIPS32 Release-6 32-bit addresses, big endian, with microMIPS\n \n \n \n \n \n \n \n MIPS32 Release-6 32-bit addresses, little endian, with microMIPS\n \n \n \n \n \n \n \n MIPS64 64-bit addresses, big endian, with mips16e\n \n \n \n \n \n \n \n \n \n MIPS64 64-bit addreses, little endian, with mips16e\n \n \n \n \n \n \n \n \n \n \n MIPS64 64-bit addresses, big endian, with microMIPS\n \n \n \n \n \n \n MIPS64 64-bit addresses, little endian, with microMIPS\n \n \n \n \n \n \n \n MIPS64 Release-6 64-bit addresses, big endian, with microMIPS\n \n \n \n \n \n \n \n \n MIPS64 Release-6 64-bit addresses, little endian, with microMIPS\n \n \n \n \n \n \n \n \n \n MIPS64 32-bit addresses, big endian, with mips16e\n \n \n \n \n \n \n \n \n \n \n \n \n \n MIPS64 32-bit addresses, little endian, with mips16e\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n MIPS64 32-bit addresses, little endian, with microMIPS\n \n \n \n \n \n \n \n \n \n \n \n MIPS64 32-bit addresses, big endian, with microMIPS\n \n \n \n \n \n \n \n \n \n \n MIPS64 Release-6 big endian with 32 bit addressing and microMIPS\n \n \n \n \n \n \n \n \n \n \n \n \n MIPS64 Release-6 with 32-bit addresses, little endian, with microMIPS\n \n \n \n \n \n \n \n \n \n \n \n \n \n MIPS32 32-bit addresses, big endian, with microMIPS\n \n \n \n \n \n \n MIPS32 32-bit addresses, little endian, with microMIPS\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips.sinc", "content": "# MIPS Common specification file for 32 and 64-bit processors\n# Appropriate defines (MIPS32, MIPS64, MIPS64_32ADDRS) must be\n# specified before including this file\n\n# The following Coprocessor configuration is supported:\n# COP0: integrated CPU virtual memory and exception handler\n# COP1: Floating-point Unit (FPU)\n# COP2: \n# COP3: Used for MIPS64 FPU extended instructions (see COP1X)\n#\n# ################################\n#\n# Notes for the elf header e_flags \"secondary\" field in the MIPS.opinion file.\n#\n# \"-\" indicates don't care\n#\n# 0x5-------\tMIPS32 Release 1, 32-bit addresses, ABI is o32, FREGSIZE = 4, gcc -mips32\n#\t\tExample: 0x50001001, secondary=\"1342181377\"\n#\n# 0x6-----2-\tMIPS64 Release 1, 32-bit addresses, ABI is n32, FREGSIZE = 8, gcc -mips64\n#\n# 0x6-----0- MIPS64 Release 1, 64-bit addresses, ABI is n64, FREGSIZE = 8, gcc -mips64 -mabi-64\n#\n# 0x7------- MIPS32 Release 2, ABI is o32, gcc -mips32r2 to r5\n#\t\tif 0x00000200 is set then FREGSIZE = 8 else FREGSIZE = 4\n# 0x70001001, secondary=\"1879052289\"\n#\t\twith mips16: 0x74001001\n#\n# 0x8-----2- MIPS64 Release 2, 32-bit addresses, ABI is n32, FREGSIZE = 8, gcc -mips64r2 to r5\n#\t\t0x80000021, secondary=\"2147483681\"\n#\n# 0x8-----0- MIPS64 Release 2, 64-bit addresses, ABI is n64, gcc -mips64r2 to r5 -mabi-64\n#\t\t0x80000001\n#\n# 0x9------- MIPS32 Release 6, ABI is o32, gcc -mips32r6\n# if 0x00000200 is set then FREGSIZE = 8 else FREGSIZE = 4\n#\n# 0xa-----2- MIPS64 Release 6, 32-bit addresses, ABI is n32, FREGSIZE = 8, gcc -mips64r6\n#\t\t0xa0000421\n#\n# 0xa-----0- MIPS64 Release 6, 64-bit addresses, ABI is n64, FREGSIZE = 8, gcc -mips64r6 -mabi-64\n#\n# Masks:\n#\n# 0x04000000\tMIPS-16\n#\n# 0x02000000\tMicroMIPS\n#\n# ################################\n#\n# Notes about register names and function args:\n#\n# Function args are passed in a0 - a3, which are the same as $4 - $7, other args are on the stack\n# Floating point args are in f12 and f14\n#\n# Function return values are stored in v0 (and v1 if the regs are 32-bit and return type is 64-bits)\n# v0 and v1 are the same as general purpose regs $2 and $3\n# Floating point return values are in f0 (and f1 if needed for binding)\n#\n# $29 is the stack pointer sp\n# $30 is the frame pointer fp also called s8\n# $31 is the return address ra\n#\n# ################################\n# There is now support for single and double floating point instructions, with the following limitations:\n#\n# The PS paired single fmt1 format is not implemented. In paired single instructions,\n# the specified 64-bit floating point register operands are each considered as two separate\n# 32-bit floating points numbers, and they are processed in parallel with the same instuction.\n# (This is supposed to be the first microprocessor implementation of SIMD.)\n#\n# Only COP1 Floating point coprocessor unit 1 is supported (there is no support for unit 2)\n#\n# Some notes about MIPS Floating Point, derived from the FPU table on page 87 of the MIPS\n# Architecture Volume 1, 2014\n#\n# FPU configuration is stored in a 32-bit read-only Floating Point Implementation Register (FIR),\n# this is also known as CP1 Control Register 0.\n# Bit 22, called F64 or also called the FR bit, is = 1 when you have 64-bit FPRs,\n# else if the FR bit = 0 then you have 32-bit FPRs\n#\n# The macro FREGSIZE = 4 for 32-bit FPRs, and = 8 for 64-bit FPRs\n#\n# Other info is in the FCSR register, CP1 Register 31.\n# Bit 23 is one condition code, and bits 25-31 is the FCC with other condition codes,\n# which are set after a compare. Note this FCRE register is removed in Release 6.\n#\n# MIPS32 Release 1:\n# The FPU (floating point unit) has 32 32-bit FPRs\n# 64-bit floating point doubles are stored in even-odd pairs of FPRs\n# F64 = 0\n#\n# MIPS32 Release 2 and later:\n# FPU has 32 64-bit FPRs\n# F64 = 1\n# Use these gcc options to get 64-bit floating point instructions: -mips32r2 -mfp64\n# (gcc default is 32-bit FPRs)\n#\n# MIPS64 Release 1 - 5\n# The FPU has 32 64-bit FPRs\n# F64 = 1\n#\n# MIPS32 Release 6:\n# In \"strictly 32-bit\" mode there are 32 32-bit FPRs, and bonding of two 32-bit FPRs to support\n# 64-bit floating point is not allowed\n# F64 = 0\n#\n# MIPS64 Release 6:\n# FPU has 32 64-bit FPRs, when F64 = 1\n# In \"strictly 32-bit\" mode there are 32 32-bit FPRs, and bonding of two 32-bit FPRs is not allowed\n# F64 = 0\n#\n# Release 6:\n# Floating point condition codes are removed, and replaced by a new CMP.condn.fmt instruction\n# The PS paired-single format in floating point instructions is removed - this was when\n# two 32-bit floats were stuffed into one 64-bit FPR, and supported SIMD.\n#\n# In function calls, floating point args are passed in FPRs f12 to f15, and the return value is in f0\n#\n# When you have 32-bit FPRs, then 64-bit double floats are created by bonding a pair of 32-bit FPRs.\n# f0 is the low half or has the LSB or also called lower word of the double, and\n# f1 is the high half or has the MSB or also called upper word of the double\n#\n# When you have a 64-bit longword integer:\n# For function return longword values:\n# $2 (same as v0) holds the MSB top half of the longword\n# $3 (same as v1) holds the LSB bottom half of the longword\n#\n# Note that when FREGSIZE = 8 (ie, 64-bit FPRs) and you have a single 32-bit float, then the\n# 32-bit float data is stored in bits 0-31 of the FPR. (Bits 32-63 are \"unused\".)\n#\n# Note that when conversions are done to/from floats, doubles, ints, and longs (64-bit) that rounding\n# errors can occur in the simulator, so equality comparisons should be done carefully.\n#\n# ################################\n#\n#-----\n@ifdef MIPS64\n\n@ifdef MIPS64_32ADDRS # used for 64-bit mips restricted to 32-bit addresses\n\n@define REGSIZE \"8\" # General purpose register size (8 or 4)\n@define FREGSIZE \"8\" # Floating point register size (8 or 4)\n@define ADDRSIZE \"4\" # Memory address size (8 or 4, virtual and physical)\n@define DREGSIZE \"16\" # 2x REGSIZE used for accumulators\n@define SIZETO4 \"4\" # In 32-bit mode, no truncation needed\n@define ADDRCAST \":4\" # need to down cast to pointer size\n@define NEEDCAST \"1\"\n\n@else # full 64 bit ptrs\n\n@define REGSIZE \"8\" # General purpose register size (8 or 4)\n@define FREGSIZE \"8\" # Floating point register size (8 or 4)\n@define ADDRSIZE \"8\" # Memory address size (8 or 4, virtual and physical)\n@define DREGSIZE \"16\" # 2x REGSIZE used for accumulators\n@define SIZETO4 \"4\" # In 64-bit mode, use when need to do 32-bit operation\n@define ADDRCAST \"\" # no need to down cast to pointer size\n\n@endif #MIPS64_32ADDRS\n\n\n@else # MIPS32\n\n@define REGSIZE \"4\" # General purpose register size (8 or 4)\n# FREGSIZE for mips32 is set in slaspec file\n@define ADDRSIZE \"4\" # Memory address size (8 or 4, virtual and physical)\n@define DOUBLE \"8\" # 2x REGSIZE used for accumulators\n@define DREGSIZE \"8\"\n@define SIZETO4 \"4\"\n@define ADDRCAST \"\" # no need to down cast to pointer size\n\n@endif\n#-----\n\ndefine endian=$(ENDIAN);\n\ndefine alignment=2;\n\ndefine space ram type=ram_space size=$(ADDRSIZE) default;\ndefine space register type=register_space size=4;\n\n# General purpose registers\ndefine register offset=0 size=$(REGSIZE) [ \n zero at v0 v1 \n a0 a1 a2 a3 \n t0 t1 t2 t3 \n t4 t5 t6 t7 \n s0 s1 s2 s3 \n s4 s5 s6 s7 \n t8 t9 k0 k1 \n gp sp s8 ra\n pc\n];\n\n@ifdef MIPS64\n# We need the 32-bit pieces of the main registers for the 32-bit instructions\n@if ENDIAN == \"big\"\ndefine register offset=0 size=4 [\n zero_hi zero_lo at_hi at_lo v0_hi v0_lo v1_hi v1_lo\n a0_hi a0_lo a1_hi a1_lo a2_hi a2_lo a3_hi a3_lo\n t0_hi t0_lo t1_hi t1_lo t2_hi t2_lo t3_hi t3_lo\n t4_hi t4_lo t5_hi t5_lo t6_hi t6_lo t7_hi t7_lo\n s0_hi s0_lo s1_hi s1_lo s2_hi s2_lo s3_hi s3_lo\n s4_hi s4_lo s5_hi s5_lo s6_hi s6_lo s7_hi s7_lo\n t8_hi t8_lo t9_hi t9_lo k0_hi k0_lo k1_hi k1_lo\n gp_hi gp_lo sp_hi sp_lo s8_hi s8_lo ra_hi ra_lo\n pc_hi pc_lo\n];\n@else\ndefine register offset=0 size=4 [\n zero_lo zero_hi at_lo at_hi v0_lo v0_hi v1_lo v1_hi\n a0_lo a0_hi a1_lo a1_hi a2_lo a2_hi a3_lo a3_hi\n t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi\n t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi\n s0_lo s0_hi s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi\n s4_lo s4_hi s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi\n t8_lo t8_hi t9_lo t9_hi k0_lo k0_hi k1_lo k1_hi\n gp_lo gp_hi sp_lo sp_hi s8_lo s8_hi ra_lo ra_hi\n pc_lo pc_hi\n];\n@endif # ENDIAN\n\n@endif # MIPS64\n\n# Floating point registers\n@if FREGSIZE == \"4\"\n@if ENDIAN == \"big\"\n# For 64-bit Double floating point operands need to bond two 32-bit FPRs\ndefine register offset=0x1000 size=4 [\n f1 f0 f3 f2 f5 f4 f7 f6\n f9 f8 f11 f10 f13 f12 f15 f14\n f17 f16 f19 f18 f21 f20 f23 f22\n f25 f24 f27 f26 f29 f28 f31 f30\n];\n@else\ndefine register offset=0x1000 size=4 [\n f0 f1 f2 f3 f4 f5 f6 f7\n f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23\n f24 f25 f26 f27 f28 f29 f30 f31\n];\n@endif # ENDIAN\n\n# Note ftD, fsD, and fdD and frD have been added to support 64-bit double floats\ndefine register offset=0x1000 size=8 [\n f0_1 f2_3 f4_5 f6_7\n f8_9 f10_11 f12_13 f14_15\n f16_17 f18_19 f20_21 f22_23\n f24_25 f26_27 f28_29 f30_31\n];\n@else # FREGSIZE == \"8\"\ndefine register offset=0x1000 size=8 [\n f0 f1 f2 f3 f4 f5 f6 f7\n f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23\n f24 f25 f26 f27 f28 f29 f30 f31\n];\n@endif # FREGSIZE\n\n# Floating point control registers (common to both MIPS32 and MIPS64)\ndefine register offset=0x1200 size=4 [\n fir fccr fexr fenr fcsr\n];\n\n# COP-0 control registers, sel=0\ndefine register offset=0x2000 size=$(REGSIZE) [\n Index Random EntryLo0 EntryLo1 \n Context PageMask Wired HWREna \n BadVAddr Count EntryHi Compare \n Status Cause EPC PRId \n Config LLAddr WatchLo WatchHi \n XContext cop0_reg21 cop0_reg22 Debug\n DEPC PerfCnt ErrCtl CacheErr\n TagLo TagHi ErrorEPC DESAVE \n];\n\n# COP-0 control registers, sel=1\ndefine register offset=0x2100 size=$(REGSIZE) [\n MVPControl VPEControl TCStatus cop0_reg3.1\n ContextConfig PageGrain SRSConf0 cop0_reg7.1\n cop0_reg8.1 cop0_reg9.1 cop0_reg10.1 cop0_reg11.1\n IntCtl cop0_reg13.1 cop0_reg14.1 EBase\n Config1 cop0_reg17.1 WatchLo.1 WatchHi.1\n cop0_reg20.1 cop0_reg21.1 cop0_reg22.1 TraceControl\n cop0_reg24.1 PerfCnt.1 cop0_reg26.1 CacheErr.1\n DataLo.1 DataHi.1 cop0_reg30.1 cop0_reg31.1\n];\n\n# COP-0 control registers, sel=2\ndefine register offset=0x2200 size=$(REGSIZE) [\n MVPConf0 VPEConf0 TCBind cop0_reg3.2\n cop0_reg4.2 cop0_reg5.2 SRSConf1 cop0_reg7.2\n cop0_reg8.2 cop0_reg9.2 cop0_reg10.2 cop0_reg11.2\n SRSCtl cop0_reg13.2 cop0_reg14.2 cop0_reg15.2\n Config2 cop0_reg17.2 WatchLo.2 WatchHi.2\n cop0_reg20.2 cop0_reg21.2 cop0_reg22.2 TraceControl2\n cop0_reg24.2 PerfCnt.2 cop0_reg26.2 CacheErr.2\n TagLo.2 TagHi.2 cop0_reg30.2 cop0_reg31.2\n];\n\n# COP-0 control registers, sel=3\ndefine register offset=0x2300 size=$(REGSIZE) [\n MVPConf1 VPEConf1 TCRestart cop0_reg3.3\n cop0_reg4.3 cop0_reg5.3 SRSConf2 cop0_reg7.3\n cop0_reg8.3 cop0_reg9.3 cop0_reg10.3 cop0_reg11.3\n SRSMap cop0_reg13.3 cop0_reg14.3 cop0_reg15.3\n Config3 cop0_reg17.3 WatchLo.3 WatchHi.3\n cop0_reg20.3 cop0_reg21.3 cop0_reg22.3 UserTraceData\n cop0_reg24.3 PerfCnt.3 cop0_reg26.3 CacheErr.3\n DataLo.3 DataHi.3 cop0_reg30.3 cop0_reg31.3\n];\n\n# COP-0 control registers, sel=4\ndefine register offset=0x2400 size=$(REGSIZE) [\n cop0_reg0.4 YQMask TCHalt cop0_reg3.4\n cop0_reg4.4 cop0_reg5.4 SRSConf3 cop0_reg7.4\n cop0_reg8.4 cop0_reg9.4 cop0_reg10.4 cop0_reg11.4\n cop0_reg12.4 cop0_reg13.4 cop0_reg14.4 cop0_reg15.4\n cop0_reg16.4 cop0_reg17.4 WatchLo.4 WatchHi.4\n cop0_reg20.4 cop0_reg21.4 cop0_reg22.4 TraceBPC\n cop0_reg24.4 PerfCnt.4 cop0_reg26.4 CacheErr.4\n TagLo.4 TagHi.4 cop0_reg30.4 cop0_reg31.4\n];\n\n# COP-0 control registers, sel=5\ndefine register offset=0x2500 size=$(REGSIZE) [\n cop0_reg0.5 VPESchedule TCContext cop0_reg3.5\n cop0_reg4.5 cop0_reg5.5 SRSConf4 cop0_reg7.5\n cop0_reg8.5 cop0_reg9.5 cop0_reg10.5 cop0_reg11.5\n cop0_reg12.5 cop0_reg13.5 cop0_reg14.5 cop0_reg15.5\n cop0_reg16.5 cop0_reg17.5 WatchLo.5 WatchHi.5\n cop0_reg20.5 cop0_reg21.5 cop0_reg22.5 cop0_reg23.5\n cop0_reg24.5 PerfCnt.5 cop0_reg26.5 CacheErr.5\n DataLo.5 DataHi.5 cop0_reg30.5 cop0_reg31.5\n];\n\n# COP-0 control registers, sel=6\ndefine register offset=0x2600 size=$(REGSIZE) [\n cop0_reg0.6 VPEScheFBack TCSchedule cop0_reg3.6\n cop0_reg4.6 cop0_reg5.6 cop0_reg6.6 cop0_reg7.6\n cop0_reg8.6 cop0_reg9.6 cop0_reg10.6 cop0_reg11.6\n cop0_reg12.6 cop0_reg13.6 cop0_reg14.6 cop0_reg15.6\n cop0_reg16.6 cop0_reg17.6 WatchLo.6 WatchHi.6\n cop0_reg20.6 cop0_reg21.6 cop0_reg22.6 cop0_reg23.6\n cop0_reg24.6 PerfCnt.6 cop0_reg26.6 CacheErr.6\n TagLo.6 TagHi.6 cop0_reg30.6 cop0_reg31.6\n];\n\n# COP-0 control registers, sel=7\ndefine register offset=0x2700 size=$(REGSIZE) [\n cop0_reg0.7 VPEOpt TCScheFBack cop0_reg3.7\n cop0_reg4.7 cop0_reg5.7 cop0_reg6.7 cop0_reg7.7\n cop0_reg8.7 cop0_reg9.7 cop0_reg10.7 cop0_reg11.7\n cop0_reg12.7 cop0_reg13.7 cop0_reg14.7 cop0_reg15.7\n cop0_reg16.7 cop0_reg17.7 WatchLo.7 WatchHi.7\n cop0_reg20.7 cop0_reg21.7 cop0_reg22.7 cop0_reg23.7\n cop0_reg24.7 PerfCnt.7 cop0_reg26.7 CacheErr.7\n DataLo.7 DataHi.7 cop0_reg30.7 cop0_reg31.7\n];\n\n# Some other internal registers\ndefine register offset=0x3000 size=$(REGSIZE) [\n@if ENDIAN == \"big\"\n hi lo hi1 lo1 hi2 lo2 hi3 lo3\n@else\n lo hi lo1 hi1 lo2 hi2 lo3 hi3\n@endif # ENDIAN\n tsp\n];\n\n# MIPS dsp lo/hi combined registers\ndefine register offset=0x3000 size=$(DREGSIZE) [ ac0 ac1 ac2 ac3 ];\n\ndefine register offset=0x3100 size=$(REGSIZE) [ DSPControl ];\n\ndefine register offset=0x3200 size=$(REGSIZE) [\n\tHW_CPUNUM\tHW_SYNCI_STEP\tHW_CC\t\tHW_CCRe\n\tHW_PerfCtr\tHW_XNP\t\t\tHW_RES6\t\tHW_RES7\n\tHW_RES8\t\tHW_RES9\t\t\tHW_RES10\tHW_RES11\n\tHW_RES12\tHW_RES13\t\tHW_RES14\tHW_RES15\n\tHW_RES16\tHW_RES17\t\tHW_RES18\tHW_RES19\n\tHW_RES20\tHW_RES21\t\tHW_RES22\tHW_RES23\n\tHW_RES24\tHW_RES25\t\tHW_RES26\tHW_RES27\n\tHW_RES28\tHW_ULR\t\t\tHW_RESIM30\tHW_RESIM31\n];\n\n@ifdef ISA_VARIANT \ndefine register offset=0x3F00 size=1 [ ISAModeSwitch ];\n@endif\n\n# Dummy registers for multi-threading\ndefine register offset=0x3300 size=$(REGSIZE) [\n\tthread_zero\tthread_at\tthread_v0\tthread_v1\tthread_a0\tthread_a1\tthread_a2\tthread_a3\n\tthread_t0\tthread_t1\tthread_t2\tthread_t3\tthread_t4\tthread_t5\tthread_t6\tthread_t7\n\tthread_s0\tthread_s1\tthread_s2\tthread_s3\tthread_s4\tthread_s5\tthread_s6\tthread_s7\n\tthread_t8\tthread_t9\tthread_k0\tthread_k1\tthread_gp\tthread_sp\tthread_s8\tthread_ra\n\t\n\tthread_f0\tthread_f1\tthread_f2\tthread_f3\tthread_f4\tthread_f5\tthread_f6\tthread_f7\n\tthread_f8\tthread_f9\tthread_f10\tthread_f11\tthread_f12\tthread_f13\tthread_f14\tthread_f15\n\tthread_f16\tthread_f17\tthread_f18\tthread_f19\tthread_f20\tthread_f21\tthread_f22\tthread_f23\n\tthread_f24\tthread_f25\tthread_f26\tthread_f27\tthread_f28\tthread_f29\tthread_f30\tthread_f31\n\t\n\tthread_lo0\tthread_hi0\tthread_acx0\t_\tthread_lo1\tthread_hi1\tthread_acx1\t_\n\tthread_lo2\tthread_hi2\tthread_acx2\t_\tthread_lo3\tthread_hi3\tthread_acx3\t_\n\t\n\tthread_fir\tthread_fccr\tthread_fexr\tthread_fenr\tthread_fcsr\n];\n\n# Define context bits\ndefine register offset=0x4000 size=4 contextreg;\ndefine context contextreg\n PAIR_INSTRUCTION_FLAG=(0,0) noflow # =1 paired instruction\n REL6=(31,31)\t\t\t\t\t\t\t # =1 Release 6, =0 Pre release 6, (Fixed, set via pspec)\n RELP=(30,30)\t\t\t\t\t\t\t # =1 Mips16e, =0 MicroMips. REL6, RELP can't both be 1 (Fixed, set via pspec)\n@ifdef ISA_VARIANT \n ISA_MODE=(1,1)\t\t\t\t\t\t # =1 Decode using alternate ISA, variable.\n LowBitCodeMode = (1,1)\t\t\t\t # =1 if low bit of instruction address is set on a branch\n#below here is for mips16e. Overlaps with micromips \n ext_isjal=(2,2) noflow\n ext_value=(3,13) noflow\n ext_value_select=(3,5) noflow\n ext_value_1005=(3,8) noflow\n ext_value_1004=(3,9) noflow\n ext_value_sa40=(3,7) noflow\n ext_value_xreg=(3,5) noflow\n ext_value_frame=(6,9) noflow\n ext_value_areg=(10,13) noflow\n ext_value_b0=(13,13) noflow\n ext_value_b1=(12,12) noflow\n ext_value_b2=(11,11) noflow\n ext_value_b3=(10,10) noflow\n ext_value_saz=(8,13) noflow\n ext_value_1511=(9,13) noflow\n ext_value_1511s=(9,13) signed noflow\n ext_value_1411=(10,13) noflow\n ext_value_1411s=(10,13) signed noflow\n ext_tgt_2521=(3,7) noflow\n ext_tgt_2016=(8,12) noflow\n ext_tgt_x=(13,13) noflow\n ext_is_ext=(14,14) noflow\n ext_m16r32=(15,19) noflow\n ext_m16r32a=(15,19) noflow\n ext_reg_high=(15,16) noflow\n ext_reg_low=(17,19) noflow\n ext_svrs_sreg=(20,24) noflow\n ext_svrs_xs=(20,22) noflow\n ext_svrs_s1=(23,23) noflow\n ext_svrs_s0=(24,24) noflow\n ext_done=(25,25) noflow\n ext_delay=(26,27) noflow\n\n # 16e2\n ext_rb=(11,13) noflow\n ext_imm_2426=(3, 5)\n ext_imm_2526=(3,4) noflow\n ext_imm_1620=(9,13) noflow\n ext_imm_1920=(9,10) noflow\n ext_imm_2124=(5, 8) noflow\n ext_imm_2123=(6, 8) noflow\n ext_imm_21=(8,8) noflow\n ext_imm_2226=(3,7) noflow\n\n\n#below here is for micromips. Overlaps with mips16e\n ext_t4_name=(2,5) noflow\n ext_t4=(2,5) noflow\n ext_tra=(6,6) noflow\n ext_32_code=(7,16) noflow\n ext_32_codes=(7,16) signed noflow\n ext_32_addim=(10,16) noflow\n ext_32_addims=(10,16) signed noflow\n ext_32_imm2=(15,16) noflow\n ext_32_imm2s=(15,16) signed noflow\n ext_32_imm3=(14,16) noflow \n ext_32_imm3s=(14,16) signed noflow \n ext_32_imm5=(12,16) noflow\n ext_32_imm5s=(12,16) signed noflow\n ext_32_imm6=(11,16) noflow\n ext_32_rlist=(7,11) noflow\n ext_32_base=(12,16) noflow\n ext_32_basea=(12,16) noflow\n\n ext_32_rd=(7,11) noflow\n ext_32_rdset=(7,11) noflow \n ext_32_rs1=(7,11) noflow\n ext_32_rs1lo=(7,11) noflow\n ext_32_rs1set=(7,11) noflow\n ext_16_rs=(7,9) noflow\n ext_16_rslo=(7,8) noflow\n ext_16_rshi=(9,9) noflow\n \n ext_off16_s=(7,22) signed noflow\n ext_off16_u=(7,22) noflow\n@endif # ISA_VARIANT \n;\n\n\n\n# Instruction fields\n\ndefine token instr(32)\n prime = (26,31)\n bit25 = (25,25)\n zero2425 = (24,25)\n zero2325 = (23,25)\n zero1 = (22,25)\n rs32 = (21,25)\n frD = (21,25)\n rs = (21,25)\n fr = (21,25)\n base = (21,25)\n format = (21,25)\n copop = (21,25)\n mfmc0 = (21,25)\n zero21 = (21,25)\n jsub = (21,25)\n sa_dsp2 = (21,25)\n shift21 = (21,25)\n sz = (21,25)\n \n acf = (21,22)\n acflo = (21,22)\n acfhi = (21,22)\n shift20 = (20,25)\n breakcode = (6,25)\n off26 = (0,25) signed\t\t\t# 26 bit signed offset, e.g. balc, bc\n ind26 = (0,25)\t\t\t\t# 26 bit unsigned index, e.g. jal\n copfill = (6,24)\n cofun = (0,24)\n off21 = (0,20) signed\t\t# 21 bit signed offset in conditional branch/link\n off16 = (0,15) signed\t\t# 16 bit signed offset in conditional branch/link\n bit21 = (21,21)\n bitz19 = (19,20)\n pcrel = (19,20)\n pcrel2 = (18,20)\n cc = (18,20)\n immed1625 = (16,25) signed\n immed1623 = (16,23) signed\n rt32 = (16,20)\n rt = (16,20)\n rtmtdsp = (16,20)\n RT0thread = (16,20)\n RTthread = (16,20)\n FTthread = (16,20)\n FCTthread = (16,20)\n ftD = (16,20)\n ft = (16,20)\n index = (16,20)\n hint = (16,20)\n cop1code = (16,20)\n synci = (16,20)\n cond = (16,20)\n op = (16,20)\n zero1620 = (16,20)\n \n zero1619 = (16,19)\n lohiacx = (16,19)\n nd = (17,17)\n tf = (16,16)\n zero1320 = (13,20)\n zero1315 = (13,15)\n szero = (11,25)\n mask = (11,20)\n baser6 = (11,15)\n rd32 = (11,15)\n rd = (11,15)\n rdmtdsp = (11,15)\n rd0_0 = (11,15)\n rd0_1 = (11,15)\n rd0_2 = (11,15)\n rd0_3 = (11,15)\n rd0_4 = (11,15)\n rd0_5 = (11,15)\n rd0_6 = (11,15)\n rd0_7 = (11,15)\n rd_hw = (11,15)\n cp2cprSel0\t= (11,15)\n cp2cprSel1\t= (11,15)\n cp2cprSel2\t= (11,15)\n cp2cprSel3\t= (11,15)\n cp2cprSel4\t= (11,15)\n cp2cprSel5\t= (11,15)\n cp2cprSel6\t= (11,15)\n cp2cprSel7\t= (11,15)\n fsD = (11,15)\n fs = (11,15)\n RD0thread = (11,15)\n RDthread = (11,15)\n FDthread = (11,15)\n FCRthread = (16,20)\n sa_dsp = (11,15)\n fs_unk = (11,15)\n fs_fcr = (11,15)\n zero4 = (11,15)\n msbd = (11,15)\n \n lohiacx2 = (11,14)\n aclo = (11,12)\n achi = (11,12)\n ac = (11,12)\n bp = (11,12)\n bit10 = (10,10)\n spec2 = (9,10)\n spec3 = (8,10)\n simmed9 = (7,15)\n zero2 = (7,10)\n code = (6,15)\n fdD = (6,10)\n fd = (6,10)\n stype = (6,10)\n sa = (6,10)\n lsb = (6,10)\n fct2 = (6,10)\n zero5 = (6,10)\n wsbh = (6,10)\n \n bp3 = (6,8)\n sel_0608 = (6,8)\n sa2 = (6,7)\n bp2 = (6,7)\n zero6 = (3,10)\n bigfunct = (0,10)\n fct = (0,5)\n bshfl = (0,5)\n bit6 = (6,6)\n zero3 = (0,4)\n bit5 = (5,5)\n h = (4,4)\n op4 = (3,5)\n bit3 = (3,3)\n sel = (0,2)\n format1X = (0,2)\n simmed19 = (0,18) signed\n simmed18 = (0,17) signed\n immed = (0,15)\n simmed = (0,15) signed\n simmseq = (6,15) signed\n simmed11 = (0,10)\n;\n\nattach variables [ rs rt rd base index baser6 ] [ \n zero at v0 v1 a0 a1 a2 a3\n t0 t1 t2 t3 t4 t5 t6 t7\n s0 s1 s2 s3 s4 s5 s6 s7\n t8 t9 k0 k1 gp sp s8 ra\n];\n\nattach variables [ rd_hw ] [\n\tHW_CPUNUM\tHW_SYNCI_STEP\tHW_CC\t\tHW_CCRe\n\tHW_PerfCtr\tHW_XNP\t\t\tHW_RES6\t\tHW_RES7\n\tHW_RES8\t\tHW_RES9\t\t\tHW_RES10\tHW_RES11\n\tHW_RES12\tHW_RES13\t\tHW_RES14\tHW_RES15\n\tHW_RES26\tHW_RES17\t\tHW_RES18\tHW_RES19\n\tHW_RES20\tHW_RES21\t\tHW_RES22\tHW_RES23\n\tHW_RES24\tHW_RES25\t\tHW_RES26\tHW_RES27\n\tHW_RES28\tHW_ULR\t\t\tHW_RESIM30\tHW_RESIM31\n];\n\n@ifdef MIPS64\nattach variables [ rs32 rt32 rd32 ] [ \n zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo\n t0_lo t1_lo t2_lo t3_lo t4_lo t5_lo t6_lo t7_lo\n s0_lo s1_lo s2_lo s3_lo s4_lo s5_lo s6_lo s7_lo\n t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo \n];\n@else\n# For MIPS32 these are the same as rs, rt, and rd\nattach variables [ rs32 rt32 rd32 ] [ \n zero at v0 v1 a0 a1 a2 a3\n t0 t1 t2 t3 t4 t5 t6 t7\n s0 s1 s2 s3 s4 s5 s6 s7\n t8 t9 k0 k1 gp sp s8 ra \n];\n@endif\n \nattach variables [ fs ft fd fr ] [\n f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31\n];\n\n@if FREGSIZE == \"4\"\n# For 64-bit floating point Double instruction operands need to bond two 32-bit FPRs\nattach variables [ fsD ftD fdD frD ] [\n f0_1 _ f2_3 _ f4_5 _ f6_7 _\n f8_9 _ f10_11 _ f12_13 _ f14_15 _\n f16_17 _ f18_19 _ f20_21 _ f22_23 _\n f24_25 _ f26_27 _ f28_29 _ f30_31 _\n];\n@else # FREGSIZE == \"8\"\nattach variables [ fsD ftD fdD frD ] [\n f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31\n];\n@endif\n\n# Only a few Floating Point Control (FCR) registers are defined\nattach variables [ fs_fcr ] [\n\tfir\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\tfccr\tfexr\t_\t\tfenr\t_\t\t_\t\tfcsr\n];\n \nattach variables [ rd0_0 ] [\n Index Random EntryLo0 EntryLo1 \n Context PageMask Wired HWREna \n BadVAddr Count EntryHi Compare \n Status Cause EPC PRId \n Config LLAddr WatchLo WatchHi \n XContext cop0_reg21 cop0_reg22 Debug\n DEPC PerfCnt ErrCtl CacheErr\n TagLo TagHi ErrorEPC DESAVE \n];\n\nattach variables [ rd0_1 ] [\n MVPControl VPEControl TCStatus cop0_reg3.1\n ContextConfig PageGrain SRSConf0 cop0_reg7.1\n cop0_reg8.1 cop0_reg9.1 cop0_reg10.1 cop0_reg11.1\n IntCtl cop0_reg13.1 cop0_reg14.1 EBase\n Config1 cop0_reg17.1 WatchLo.1 WatchHi.1\n cop0_reg20.1 cop0_reg21.1 cop0_reg22.1 TraceControl\n cop0_reg24.1 PerfCnt.1 cop0_reg26.1 CacheErr.1\n DataLo.1 DataHi.1 cop0_reg30.1 cop0_reg31.1\n];\n\nattach variables [ rd0_2 ] [\n MVPConf0 VPEConf0 TCBind cop0_reg3.2\n cop0_reg4.2 cop0_reg5.2 SRSConf1 cop0_reg7.2\n cop0_reg8.2 cop0_reg9.2 cop0_reg10.2 cop0_reg11.2\n SRSCtl cop0_reg13.2 cop0_reg14.2 cop0_reg15.2\n Config2 cop0_reg17.2 WatchLo.2 WatchHi.2\n cop0_reg20.2 cop0_reg21.2 cop0_reg22.2 TraceControl2\n cop0_reg24.2 PerfCnt.2 cop0_reg26.2 CacheErr.2\n TagLo.2 TagHi.2 cop0_reg30.2 cop0_reg31.2\n];\n\nattach variables [ rd0_3 ] [\n MVPConf1 VPEConf1 TCRestart cop0_reg3.3\n cop0_reg4.3 cop0_reg5.3 SRSConf2 cop0_reg7.3\n cop0_reg8.3 cop0_reg9.3 cop0_reg10.3 cop0_reg11.3\n SRSMap cop0_reg13.3 cop0_reg14.3 cop0_reg15.3\n Config3 cop0_reg17.3 WatchLo.3 WatchHi.3\n cop0_reg20.3 cop0_reg21.3 cop0_reg22.3 UserTraceData\n cop0_reg24.3 PerfCnt.3 cop0_reg26.3 CacheErr.3\n DataLo.3 DataHi.3 cop0_reg30.3 cop0_reg31.3\n];\n\nattach variables [ rd0_4 ] [\n cop0_reg0.4 YQMask TCHalt cop0_reg3.4\n cop0_reg4.4 cop0_reg5.4 SRSConf3 cop0_reg7.4\n cop0_reg8.4 cop0_reg9.4 cop0_reg10.4 cop0_reg11.4\n cop0_reg12.4 cop0_reg13.4 cop0_reg14.4 cop0_reg15.4\n cop0_reg16.4 cop0_reg17.4 WatchLo.4 WatchHi.4\n cop0_reg20.4 cop0_reg21.4 cop0_reg22.4 TraceBPC\n cop0_reg24.4 PerfCnt.4 cop0_reg26.4 CacheErr.4\n TagLo.4 TagHi.4 cop0_reg30.4 cop0_reg31.4\n];\n\nattach variables [ rd0_5 ] [\n cop0_reg0.5 VPESchedule TCContext cop0_reg3.5\n cop0_reg4.5 cop0_reg5.5 SRSConf4 cop0_reg7.5\n cop0_reg8.5 cop0_reg9.5 cop0_reg10.5 cop0_reg11.5\n cop0_reg12.5 cop0_reg13.5 cop0_reg14.5 cop0_reg15.5\n cop0_reg16.5 cop0_reg17.5 WatchLo.5 WatchHi.5\n cop0_reg20.5 cop0_reg21.5 cop0_reg22.5 cop0_reg23.5\n cop0_reg24.5 PerfCnt.5 cop0_reg26.5 CacheErr.5\n DataLo.5 DataHi.5 cop0_reg30.5 cop0_reg31.5\n];\n\nattach variables [ rd0_6 ] [\n cop0_reg0.6 VPEScheFBack TCSchedule cop0_reg3.6\n cop0_reg4.6 cop0_reg5.6 cop0_reg6.6 cop0_reg7.6\n cop0_reg8.6 cop0_reg9.6 cop0_reg10.6 cop0_reg11.6\n cop0_reg12.6 cop0_reg13.6 cop0_reg14.6 cop0_reg15.6\n cop0_reg16.6 cop0_reg17.6 WatchLo.6 WatchHi.6\n cop0_reg20.6 cop0_reg21.6 cop0_reg22.6 cop0_reg23.6\n cop0_reg24.6 PerfCnt.6 cop0_reg26.6 CacheErr.6\n TagLo.6 TagHi.6 cop0_reg30.6 cop0_reg31.6\n];\n\nattach variables [ rd0_7 ] [\n cop0_reg0.7 VPEOpt TCScheFBack cop0_reg3.7\n cop0_reg4.7 cop0_reg5.7 cop0_reg6.7 cop0_reg7.7\n cop0_reg8.7 cop0_reg9.7 cop0_reg10.7 cop0_reg11.7\n cop0_reg12.7 cop0_reg13.7 cop0_reg14.7 cop0_reg15.7\n cop0_reg16.7 cop0_reg17.7 WatchLo.7 WatchHi.7\n cop0_reg20.7 cop0_reg21.7 cop0_reg22.7 cop0_reg23.7\n cop0_reg24.7 PerfCnt.7 cop0_reg26.7 CacheErr.7\n DataLo.7 DataHi.7 cop0_reg30.7 cop0_reg31.7\n];\n\nattach variables [ aclo acflo ] [ lo lo1 lo2 lo3 ];\nattach variables [ achi acfhi ] [ hi hi1 hi2 hi3 ];\nattach variables [ ac acf ] [ ac0 ac1 ac2 ac3 ];\n\nattach names hint [ \n \"load\" \"store\" \"hint2\" \"hint3\" \"load_streamed\" \"store_streamed\" \"load_retained\" \"store_retained\"\n \"hint8\" \"hint9\" \"hint10\" \"hint11\" \"hint12\" \"hint13\" \"hint14\" \"hint15\"\n \"hint16\" \"hint17\" \"hint18\" \"hint19\" \"hint20\" \"hint21\" \"hint22\" \"hint23\" \"hint24\"\n \"writeback_invalidate\" \"hint26\" \"hint27\" \"hint28\" \"hint29\" \"PrepareForStore\" \"hint31\" ];\n\nattach variables [RTthread RDthread] [\n\tthread_zero\tthread_at\tthread_v0\tthread_v1\tthread_a0\tthread_a1\tthread_a2\tthread_a3\n\tthread_t0\tthread_t1\tthread_t2\tthread_t3\tthread_t4\tthread_t5\tthread_t6\tthread_t7\n\tthread_s0\tthread_s1\tthread_s2\tthread_s3\tthread_s4\tthread_s5\tthread_s6\tthread_s7\n\tthread_t8\tthread_t9\tthread_k0\tthread_k1\tthread_gp\tthread_sp\tthread_s8\tthread_ra\n];\n\nattach variables [ FTthread FDthread ] [\n\tthread_f0\tthread_f1\tthread_f2\tthread_f3\tthread_f4\tthread_f5\tthread_f6\tthread_f7\n\tthread_f8\tthread_f9\tthread_f10\tthread_f11\tthread_f12\tthread_f13\tthread_f14\tthread_f15\n\tthread_f16\tthread_f17\tthread_f18\tthread_f19\tthread_f20\tthread_f21\tthread_f22\tthread_f23\n\tthread_f24\tthread_f25\tthread_f26\tthread_f27\tthread_f28\tthread_f29\tthread_f30\tthread_f31\n];\n\nattach variables [ rtmtdsp rdmtdsp ] [\n\tthread_lo0\tthread_hi0\tthread_acx0\t_\tthread_lo1\tthread_hi1\tthread_acx1\t_\n\tthread_lo2\tthread_hi2\tthread_acx2\t_\tthread_lo3\tthread_hi3\tthread_acx3\t_\n\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\t_\n];\n\nattach variables [ FCTthread FCRthread ] [\n\tthread_fir\t_\t\t\t_\t\t\t_\t_\t\t\t_\t_\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t_\t\t\t_\t_\t_\n\t_\t\t\t_\t\t\t_\t\t\t_\t_\t\t\t_\t_\t_\n\t_\t\t\tthread_fccr\tthread_fexr\t_\tthread_fenr\t_\t_\tthread_fcsr\n];\n\n# Subconstructors\nRD0: rd0_0 is rd0_0 & sel=0 { export rd0_0; }\nRD0: rd0_1 is rd0_1 & sel=1 { export rd0_1; }\nRD0: rd0_2 is rd0_2 & sel=2 { export rd0_2; }\nRD0: rd0_3 is rd0_3 & sel=3 { export rd0_3; }\nRD0: rd0_4 is rd0_4 & sel=4 { export rd0_4; }\nRD0: rd0_5 is rd0_5 & sel=5 { export rd0_5; }\nRD0: rd0_6 is rd0_6 & sel=6 { export rd0_6; }\nRD0: rd0_7 is rd0_7 & sel=7 { export rd0_7; }\n\nRD: rd is rd { export rd; }\nRDsrc: rd is rd { export rd; }\nRDsrc: rd is rd & rd=0 { export 0:$(REGSIZE); }\n\nRS: rs \tis rs { export rs; }\nRSsrc: rs is rs { export rs; }\nRSsrc: rs is rs & rs=0 { export 0:$(REGSIZE); }\n\nRT: rt is rt { export rt; }\nRTsrc: rt is rt { export rt; }\nRTsrc: rt is rt & rt=0 { export 0:$(REGSIZE); }\n\nRD32: rd is rd & rd32 { export rd32; }\nRS32src: rs is rs & rs32 { export rs32; }\nRS32src: rs is rs & rs32=0 { export 0:4; }\nRT32: rt is rt & rt32 { export rt32; }\nRT32src: rt is rt & rt32 { export rt32; }\nRT32src: rt is rt & rt32=0 { export 0:4; }\n\n@ifdef NEEDCAST\nmacro MemSrcCast(dest,src) {\n\tdest = *(src:$(ADDRSIZE));\n}\nmacro MemDestCast(dest,src) {\n\t*(dest:$(ADDRSIZE)) = src;\n}\nmacro ValCast(dest,src) {\n\tdest = src:$(ADDRSIZE);\n}\n@else\nmacro MemSrcCast(dest,src) {\n\tdest = *(src);\n}\nmacro MemDestCast(dest,src) {\n\t*(dest) = src;\n}\nmacro ValCast(dest,src) {\n\tdest = src;\n}\n@endif\n\nOFF_BASE: simmed(base) is simmed & base { tmp:$(REGSIZE) = base + simmed; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nINDEX_BASE: index(base) is index & base { tmp:$(REGSIZE) = base + index; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\n\nOFF_BASER6: simmed(base)\tis REL6=0 & simmed & base\t{ tmp:$(REGSIZE) = base + simmed; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_BASER6: simmed9(base)\tis REL6=1 & simmed9 & base\t{ tmp:$(REGSIZE) = base + simmed9; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\n\nS18L3: val\t\t\t\t\t\t\tis simmed18 [ val = simmed18 << 3; ] { export *[const]:4 val; }\nS19L2: val\t\t\t\t\t\t\tis simmed19 [ val = simmed19 << 2; ] { export *[const]:4 val; }\nS16L16: val\t\t\t\t\t\t\tis simmed [ val = simmed << 16; ] { export *[const]:4 val; }\nS16L32: val\t\t\t\t\t\t\tis simmed [ val = simmed << 32; ] { export *[const]:8 val; }\nS16L48: val\t\t\t\t\t\t\tis simmed [ val = simmed << 48; ] { export *[const]:8 val; }\nSAV: val\t\t\t\t\t\t\tis sa2 [ val = sa2+1; ] { export *[const]:1 val; }\n\nRel16: reloc\t\tis off16\t[ reloc=inst_start+4+4*off16; ]\t\t\t\t\t{ export *:$(ADDRSIZE) reloc; }\nRel21: reloc\t\tis off21\t[ reloc=inst_start+4+4*off21; ]\t\t\t\t\t{ export *:$(ADDRSIZE) reloc; }\nRel26: reloc\t\tis off26\t[ reloc=inst_start+4+4*off26; ]\t\t\t\t\t{ export *:$(ADDRSIZE) reloc; }\nAbs26: reloc\t\tis ind26\t[ reloc=((inst_start+4) $and 0xfffffffff0000000) | 4*ind26; ]\t{ export *:$(ADDRSIZE) reloc; }\n\nInsSize: mysize is msbd & lsb [ mysize = msbd - lsb + 1; ] { tmp:1 = mysize; export tmp; }\nExtSize: mysize is msbd [ mysize = msbd + 1; ] { tmp:1 = mysize; export tmp; }\n\n@ifdef MIPS64\nDextmSize: mysize is msbd [ mysize = msbd + 1 + 32; ] { tmp:1 = mysize; export tmp; }\nDXuPos: pos is lsb [ pos = lsb + 32; ] { tmp:1 = pos; export tmp; }\nDinsXSize: mysize is msbd & lsb [ mysize = msbd - lsb + 1 + 32; ] { tmp:1 = mysize; export tmp; }\n@endif\n\nmacro JXWritePC(addr) {\n@ifdef ISA_VARIANT \n ISAModeSwitch = (addr & 0x1) != 0;\n tmp:$(REGSIZE) = -2;\n tmp = tmp & addr;\n pc = tmp;\n@else\n pc=addr;\n@endif\n}\n\n# Floating point formats\n#fmt: \"S\" is format=0x10 { }\n#fmt: \"D\" is format=0x11 { }\n#fmt: \"W\" is format=0x14 { }\n#fmt: \"L\" is format=0x15 { }\n#fmt: \"PS\" is format=0x16 { }\n\nfmt1: \"S\" is format=0x10 { }\nfmt1: \"D\" is format=0x11 { }\nfmt1: \"PS\" is format=0x16 { }\n\nfmt2: \"S\" is format=0x10 { }\nfmt2: \"D\" is format=0x11 { }\n\nfmt3: \"S\" is format=0x10 { }\nfmt3: \"W\" is format=0x14 { }\nfmt3: \"L\" is format=0x15 { }\n\nfmt4: \"D\" is format=0x11 { }\nfmt4: \"W\" is format=0x14 { }\nfmt4: \"L\" is format=0x15 { }\n\nfmt5: \"S\" is format1X=0x0 { }\nfmt5: \"D\" is format1X=0x1 { }\nfmt5: \"PS\" is format1X=0x6 { }\n\n# Release 6 and later:\nfmt6: \"S\"\tis format=0x14 { }\nfmt6: \"D\"\tis format=0x15 { }\n\n# Custom Pcode Operations\n#\n# To add a new pcodeop op that is implemented in Java code:\n#\n# In this directory:\n# ./ghidra/Ghidra/Processors/MIPS/src/main/java/ghidra/program/emulation\n# Edit this file to register a new Java method that implements the pcodeop:\n# MIPSEmulateInstructionStateModifier.java\n# (Be sure to also import the new class)\n#\n# The mips.pspec file must have this key set (this has already been done):\n# \n#\n# Add the Java class file for the new pcodeop here:\n# ./ghidra/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/pcode/emulate/callother\n#\ndefine pcodeop break;\ndefine pcodeop trap;\ndefine pcodeop wait;\ndefine pcodeop syscall;\ndefine pcodeop cacheOp;\ndefine pcodeop signalDebugBreakpointException;\ndefine pcodeop disableInterrupts;\ndefine pcodeop enableInterrupts;\ndefine pcodeop hazzard;\ndefine pcodeop lockload;\ndefine pcodeop lockwrite;\ndefine pcodeop synch;\ndefine pcodeop tlbop;\ndefine pcodeop bitSwap;\ndefine pcodeop disableProcessor;\ndefine pcodeop enableProcessor;\ndefine pcodeop signalReservedInstruction;\ndefine pcodeop TLB_invalidate;\ndefine pcodeop TLB_invalidate_flush;\ndefine pcodeop TLB_probe_for_matching_entry;\ndefine pcodeop TLB_read_indexed_entryHi;\ndefine pcodeop TLB_read_indexed_entryLo0;\ndefine pcodeop TLB_read_indexed_entryLo1;\ndefine pcodeop TLB_read_indexed_entryPageMask;\ndefine pcodeop TLB_write_indexed_entry;\ndefine pcodeop TLB_write_random_entry;\n\n# prefetch(vaddr, hint); \ndefine pcodeop prefetch;\n\n# getFpCondition(cc)\ndefine pcodeop getFpCondition;\n\n# getCopCondition(cop_num, cc)\ndefine pcodeop getCopCondition;\n\n# setCopControlWord(cop_num, reg_num, value)\ndefine pcodeop setCopControlWord;\n\n# getCopControlWord(cop_num, reg_num)\ndefine pcodeop getCopControlWord;\n\n# copFunction(cop_num, func)\ndefine pcodeop copFunction;\n\n# getCopReg(cop_num, reg_num)\ndefine pcodeop getCopReg;\ndefine pcodeop getCopRegH;\n\n# setCopReg(cop_num, reg_num, value)\ndefine pcodeop setCopReg;\ndefine pcodeop setCopRegH;\n\n# extractField(value, msbd, lsb)\ndefine pcodeop extractField;\n\n# setShadow(sgpr, value)\ndefine pcodeop setShadow;\n\n# getHWRegister(reg, sel)\ndefine pcodeop getHWRegister;\n\n# gpr = getShadow(sgpr)\ndefine pcodeop getShadow;\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips16.sinc", "content": "################\n#\n# MIPS16e\n#\n# From MIPS32 Architecture for PRogrammers Volume IV-a:\n# The MIPS16e Application Specific Extension to the MIPS32\n# Architecture.\n#\n# Document #: MD00076 Rev 2.63 July 16, 2013\n#\n################\n\ndefine token m16instr (16)\n m16_op=(11,15)\n m16_i_imm=(0,4)\n m16_rx=(8,10)\n m16_rxa=(8,10)\n m16_ri_imm=(0,4)\n m16_ri_z=(5,7)\n m16_ry=(5,7)\n m16_rya=(5,7)\n m16_rr_f=(0,4)\n m16_rr_nd=(7,7)\n m16_rr_l=(6,6)\n m16_rr_ra=(5,5)\n m16_rr_z=(5,7)\n m16_rri_imm=(0,4)\n m16_rz=(2,4)\n m16_rza=(2,4)\n m16_rrr_f=(0,1)\n m16_rria_f=(4,4)\n m16_rria_imm=(0,3)\n m16_rria_simm=(0,3) signed\n m16_shft_sa=(2,4)\n m16_shft_f=(0,1)\n m16_i8_f=(8,10)\n m16_i8_imm=(0,4)\n m16_is8_imm=(0,7) signed\n m16_mv_rz=(0,2)\n m16_mv_rza=(0,2)\n m16_i8_rz=(5,7)\n m16_i8_r32=(0,4)\n m16_i8_r32a=(0,4)\n m16_i8_r32_20=(5,7)\n m16_i8_r32_43=(3,4)\n m16_i8_svrs=(8,10)\n m16_i8_sw=(8,10)\n m16_iu8_imm=(0,7)\n m16_b_imm=(0,4)\n m16_b_z=(5,10)\n m16_cb_z=(5,7)\n m16_b_off=(0,10) signed\n m16_cb_off=(0,7) signed \n m16_svrs_s=(7,7)\n m16_svrs_ra=(6,6)\n m16_svrs_s0=(5,5)\n m16_svrs_s1=(4,4)\n m16_svrs_frame=(0,3)\n m16_ext_val=(0,10)\n m16_tgt_1500=(0,15)\n m16_tgt_2521=(0,4)\n m16_tgt_2016=(5,9)\n m16_jal=(10,10)\n m16_code=(5,10)\n;\n \nattach variables [ m16_rx m16_ry m16_rz m16_mv_rz ext_rb ]\n [ s0 s1 v0 v1 a0 a1 a2 a3 ];\n \nattach variables [ ext_m16r32 m16_i8_r32 ] [ \n zero at v0 v1 a0 a1 a2 a3\n t0 t1 t2 t3 t4 t5 t6 t7\n s0 s1 s2 s3 s4 s5 s6 s7\n t8 t9 k0 k1 gp sp s8 ra \n];\n\n@ifdef MIPS64\nattach variables [ m16_rxa m16_rya m16_rza m16_mv_rza]\n\t\t\t\t [ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ];\n\nattach variables [ ext_m16r32a m16_i8_r32a ] [ \n zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo\n t0_lo t1_lo t2_lo t3_lo t4_lo t5_lo t6_lo t7_lo\n s0_lo s1_lo s2_lo s3_lo s4_lo s5_lo s6_lo s7_lo\n t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo \n];\n\nRZ: m16_rz is m16_rz\t\t{ export m16_rz; }\n\n@else # !MIPS64\nattach variables [ m16_rxa m16_rya m16_rza m16_mv_rza ]\n [ s0 s1 v0 v1 a0 a1 a2 a3 ];\n\nattach variables [ ext_m16r32a m16_i8_r32a ] [ \n zero at v0 v1 a0 a1 a2 a3\n t0 t1 t2 t3 t4 t5 t6 t7\n s0 s1 s2 s3 s4 s5 s6 s7\n t8 t9 k0 k1 gp sp s8 ra \n];\n\nRZ: is epsilon {}\n\n@endif # MIPS64\n\nRX: m16_rx is m16_rx \t\t{ export m16_rx; }\nRX32: m16_rx\t\tis m16_rx & m16_rxa \t\t{ export m16_rxa; }\nRY32: m16_ry\t\tis m16_ry & m16_rya \t\t{ export m16_rya; }\nRZ32: m16_rz\t\tis m16_rz & m16_rza \t\t{ export m16_rza; }\n\n\nattach names [ ext_svrs_sreg][\n\t_\t\t\"s0\"\t\t\"s1\"\t\"s0-s1\"\n\t\"s2\"\t\"s0,s2\"\t\t\"s1-s2\"\t\"s0-s2\"\n\t\"s2-s3\"\t\"s0,s2-s3\"\t\"s1-s3\"\t\"s0-s3\"\n\t\"s2-s4\"\t\"s0,s2-s4\"\t\"s1-s4\"\t\"s0-s4\"\n\t\"s2-s5\"\t\"s0,s2-s5\"\t\"s1-s5\"\t\"s0-s5\"\n\t\"s2-s6\"\t\"s0,s2-s6\"\t\"s1-s6\"\t\"s0-s6\"\n\t\"s2-s7\"\t\"s0,s2-s7\"\t\"s1-s7\"\t\"s0-s7\"\n\t\"s2-s8\"\t\"s0,s2-s8\"\t\"s1-s8\"\t\"s0-s8\"\n];\n\nAbs26_m16: reloc \t\tis m16_tgt_1500 & ext_tgt_2016 & ext_tgt_2521 [ reloc=((inst_start+4) $and 0xfffffffff0000000)+4*(m16_tgt_1500 | (ext_tgt_2016 << 16) | (ext_tgt_2521 << 21)); ] { export *:$(ADDRSIZE) reloc; } \nRel16_m16: reloc \t\tis ext_is_ext=1 & m16_b_z=0 & m16_b_imm & ext_value_1005 & ext_value_1511s [ reloc=inst_start+4+2*((ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_b_imm); ] { export *:$(ADDRSIZE) reloc; } \nRel16_m16: reloc \t\tis ext_is_ext=0 & m16_b_off [ reloc=inst_start+2+2*m16_b_off; ] { export *:$(ADDRSIZE) reloc; } \n\nCRel16_m16: reloc \t\tis ext_is_ext=1 & m16_cb_z=0 & m16_b_imm & ext_value_1005 & ext_value_1511s [ reloc=inst_start+4+2*((ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_b_imm); ] { export *:$(ADDRSIZE) reloc; } \nCRel16_m16: reloc \t\tis ext_is_ext=0 & m16_cb_off [ reloc=inst_start+2+2*m16_cb_off; ] { export *:$(ADDRSIZE) reloc; } \n\n:^instruction\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & m16_op=0b11110 & ext_done=0 & ext_isjal=0 & m16_ext_val; instruction [ext_value=m16_ext_val; ext_is_ext=1; ext_done=1; ] { build instruction; }\n:^instruction\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & m16_op=0b00011 & ext_done=0 & ext_isjal=0 & m16_jal & m16_tgt_2016 & m16_tgt_2521; instruction [ext_tgt_2016=m16_tgt_2016; ext_tgt_2521=m16_tgt_2521; ext_tgt_x=m16_jal; ext_isjal=1; ext_done=1; ] { build instruction; }\n \nEXT_I: val\t\t\t\t\t\t\tis m16_i_imm [ val = m16_i_imm << 2; ] { export *[const]:2 val; }\nEXT_IS0: val\t\t\t\t\t\tis m16_i_imm [ val = m16_i_imm << 0; ] { export *[const]:2 val; }\nEXT_IS1: val\t\t\t\t\t\tis m16_i_imm [ val = m16_i_imm << 1; ] { export *[const]:2 val; }\nEXT_RI: val\t\t\t\t\t\t\tis ext_value_1511 & ext_value_1005 & m16_ri_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_ri_imm; ] { export *[const]:2 val; }\nEXT_RRIA: val\t\t\t\t\t\tis ext_is_ext=1 & ext_value_1411s & ext_value_1004 & m16_rria_imm [ val=(ext_value_1411s << 11) | (ext_value_1004 << 4) | m16_rria_imm; ] { export *[const]:2 val; }\nEXT_RRIA: m16_rria_simm\t\t\t\tis ext_is_ext=0 & m16_rria_simm { export *[const]:2 m16_rria_simm; }\n\nEXT_IS8: val\t\t\t\t\t\tis ext_is_ext=1 & ext_value_1511s & ext_value_1005 & m16_i8_imm [val=(ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }\nEXT_IS8: m16_is8_imm\t\t\t\tis ext_is_ext=0 & m16_is8_imm { export *[const]:2 m16_is8_imm; }\nEXT_IS8L3: val\t\t\t\t\t\tis ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_imm [val = m16_is8_imm << 3; ] { export *[const]:2 val; }\n\nEXT_IU8: val\t\t\t\t\t\tis ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }\nEXT_IU8: val\t\t\t\t\t\tis ext_is_ext=0 & m16_iu8_imm [val = m16_iu8_imm << 2; ] { export *[const]:2 val; }\n\nEXT_LIU8: val\t\t\t\t\t\tis ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }\nEXT_LIU8: m16_iu8_imm\t\t\t\tis ext_is_ext=0 & m16_iu8_imm { export *[const]:2 m16_iu8_imm; }\n\nEXT_SHIFT: ext_value_sa40\t\t\tis ext_is_ext=1 & ext_value_saz=0 & m16_shft_sa=0 & ext_value_sa40 { export *[const]:1 ext_value_sa40;}\nEXT_SHIFT: val\t\t\t\t\t\tis ext_is_ext=0 & m16_shft_sa=0 \t\t\t\t [val = 8; ] { export *[const]:1 val;}\nEXT_SHIFT: m16_shft_sa\t\t\t\tis ext_is_ext=0 & m16_shft_sa\t\t\t\t \t \t\t\t { export *[const]:1 m16_shft_sa;}\n\nEXT_SET: val\t\t\t\t\t\tis ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:4 val; }\nEXT_SET: m16_iu8_imm\t\t\t\tis ext_is_ext=0 & m16_iu8_imm { export *[const]:4 m16_iu8_imm; }\n\nOFF_M16: EXT_IS8(m16_rx) \t\t\tis ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16: EXT_I(m16_rx) \t\t\tis ext_is_ext=0 & EXT_I & m16_rx { tmp:$(REGSIZE) = m16_rx + zext(EXT_I); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16S0: EXT_IS8(m16_rx) \t\tis ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16S0: EXT_IS0(m16_rx) \t\tis ext_is_ext=0 & EXT_IS0 & m16_rx { tmp:$(REGSIZE) = m16_rx + zext(EXT_IS0); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16S1: EXT_IS8(m16_rx) \t\tis ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16S1: EXT_IS1(m16_rx) \t\tis ext_is_ext=0 & EXT_IS1 & m16_rx { tmp:$(REGSIZE) = m16_rx + zext(EXT_IS1); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\n\nOFF_M16PC: EXT_IS8(pc) \t\t\tis ext_is_ext=1 & m16_i8_rz=0 & EXT_IS8 & pc { tmp:$(REGSIZE) = (inst_start + sext(EXT_IS8)) & 0xFFFFFFFC; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16PC: val(pc) \t\t\t\tis ext_is_ext=0 & m16_iu8_imm & pc & ext_delay [ val = m16_iu8_imm << 2; ] { tmp:$(REGSIZE) = (inst_start + val - (ext_delay << 1)) & 0xFFFFFFFC; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\n\nOFF_M16SP: EXT_IS8(sp) \t\t\tis ext_is_ext=1 & m16_i8_rz=0 & EXT_IS8 & sp { tmp:$(REGSIZE) = sp + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\nOFF_M16SP: val(sp) \t\t\t\t\tis ext_is_ext=0 & m16_iu8_imm & sp [ val = m16_iu8_imm << 2; ] { tmp:$(REGSIZE) = sp + val; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }\n\nEXT_FRAME: val\t\t\t\t\t\tis ext_value_frame=0 & m16_svrs_frame=0 [val = 128; ] {export *[const]:2 val;}\nEXT_FRAME: val\t\t\t\t\t\tis ext_value_frame & m16_svrs_frame [val = ((ext_value_frame << 4) | m16_svrs_frame) << 3;] {export *[const]:2 val;}\n\nREGRS_STAT:\t\t\t\t\t\t\tis ext_value_areg {}\nREGRS_STAT:\t\",a3\"\t\t\t\t\tis (ext_value_areg=1 | ext_value_areg=5 | ext_value_areg=9 |ext_value_areg=0xd) {\n \ttsp = tsp-4;\n\tMemSrcCast(a3,tsp);\n}\nREGRS_STAT:\t\",a2-a3\"\t\t\t\tis (ext_value_areg=2 | ext_value_areg=6 | ext_value_areg=0xa) {\n \ttsp = tsp-4;\n\tMemSrcCast(a3,tsp);\n \ttsp = tsp-4;\n\tMemSrcCast(a2,tsp);\n}\nREGRS_STAT:\t\",a1-a3\"\t\t\t\tis (ext_value_areg=3 | ext_value_areg=7) {\n \ttsp = tsp-4;\n\tMemSrcCast(a3,tsp);\n \ttsp = tsp-4;\n\tMemSrcCast(a2,tsp);\n \ttsp = tsp-4;\n\tMemSrcCast(a1,tsp);\n}\nREGRS_STAT:\t\",a0-a3\"\t\t\t\tis ext_value_areg=0xB {\n \ttsp = tsp-4;\n\tMemSrcCast(a3,tsp);\n \ttsp = tsp-4;\n\tMemSrcCast(a2,tsp);\n \ttsp = tsp-4;\n\tMemSrcCast(a1,tsp);\n \ttsp = tsp-4;\n\tMemSrcCast(a0,tsp);\n}\n\nREST_STAT:\t\t\t\t\t\t\tis ext_value_areg=0 | ext_value_areg=4 | ext_value_areg=8 | ext_value_areg=0xc | ext_value_areg=0xe {}\nREST_STAT: REGRS_STAT\t\t\t\tis REGRS_STAT {\n\tbuild REGRS_STAT;\n}\n\n\nREGSV_STAT:\t\t\t\t\t\t\tis ext_value_areg {}\nREGSV_STAT:\t\",a3\"\t\t\t\t\tis (ext_value_areg=1 | ext_value_areg=5 | ext_value_areg=9 | ext_value_areg=0xd) {\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a3);\n}\nREGSV_STAT:\t\",a2-a3\"\t\t\t\t\tis (ext_value_areg=2 | ext_value_areg=6 | ext_value_areg=0xa) {\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a3);\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a2);\n}\nREGSV_STAT:\t\",a1-a3\"\t\t\t\tis (ext_value_areg=3 | ext_value_areg=7) {\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a3);\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a2);\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a1);\n}\nREGSV_STAT:\t\",a0-a3\"\t\t\t\tis ext_value_areg=0xb { \n \ttsp = tsp-4;\n\tMemDestCast(tsp,a3);\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a2);\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a1);\n \ttsp = tsp-4;\n\tMemDestCast(tsp,a0);\n}\n\nSAVE_STAT:\t\t\t\t\t\t\tis ext_value_areg=0 | ext_value_areg=4 | ext_value_areg=8 | ext_value_areg=0xc | ext_value_areg=0xe {}\nSAVE_STAT: REGSV_STAT\t\t\t\tis REGSV_STAT {\n\tbuild REGSV_STAT;\n}\n\nREGSV_BLD1:\t\t\t\t\t\t\tis ext_value_b2=0 {}\nREGSV_BLD1:\t\"a0,\"\t\t\t\t\tis ext_value_b2=1 {\n ptr:$(REGSIZE) = sp;\n MemDestCast(ptr,a0);\n}\n\nREGSV_BLD2:\tREGSV_BLD1\t\t\t\tis REGSV_BLD1 { build REGSV_BLD1; }\nREGSV_BLD2:\t\"a0-a1,\"\t\t\t\tis ext_value_b3=1 & ext_value_b2=0 & (ext_value_b1=0 | ext_value_b0=0) {\n ptr:$(REGSIZE) = sp;\n MemDestCast(ptr,a0);\n ptr = sp+4;\n MemDestCast(ptr,a1);\n}\n\nREGSV_BLD3:\tREGSV_BLD2\t\t\t\tis REGSV_BLD2 { build REGSV_BLD2; }\nREGSV_BLD3:\t\"a0-a2,\"\t\t\t\tis ext_value_b3=1 & ext_value_b2=1 & ext_value_b1=0 {\n ptr:$(REGSIZE) = sp;\n MemDestCast(ptr,a0);\n ptr = sp+4;\n MemDestCast(ptr,a1);\n ptr = sp+8;\n MemDestCast(ptr,a2);\n}\n\nREGSV_BLD4:\tREGSV_BLD3\t\t\t\tis REGSV_BLD3 { build REGSV_BLD3; }\nREGSV_BLD4:\t\"a0-a3,\"\t\t\t\tis ext_value_areg=0b1110 {\n ptr:$(REGSIZE) = sp;\n MemDestCast(ptr,a0);\n ptr = sp+4;\n MemDestCast(ptr,a1);\n ptr = sp+8;\n MemDestCast(ptr,a2);\n ptr = sp+12;\n MemDestCast(ptr,a3);\n}\n\nSAVE_ARG:\t\t\t\t\t\t\tis ext_value_areg=0 | ext_value_areg=1 | ext_value_areg=2 | ext_value_areg=3 | ext_value_areg=0xb | ext_value_areg=0xf {}\nSAVE_ARG: REGSV_BLD4\t\t\t\tis REGSV_BLD4 {\n\tbuild REGSV_BLD4;\n}\n\nREGRS_S0:\t\t\tis m16_svrs_s0 \t\t\t\t {}\nREGRS_S0:\t\t\tis m16_svrs_s0=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s0,tsp); }\n\nREGRS_S1:\t\t\tis m16_svrs_s1 \t\t\t\t {}\nREGRS_S1:\t\t\tis m16_svrs_s1=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s1,tsp); }\n\nREGRS_S8:\t\t\tis ext_value_xreg=6 \t {}\nREGRS_S8:\t\t\tis ext_value_xreg { tsp = tsp-$(REGSIZE); MemSrcCast(s8,tsp); }\n\nREGRS_S7:\t\t\tis ext_value_xreg=5 \t {}\nREGRS_S7:\t\t\tis REGRS_S8 { build REGRS_S8; tsp = tsp-$(REGSIZE); MemSrcCast(s7,tsp); }\n\nREGRS_S6:\t\t\tis ext_value_xreg=4 \t {}\nREGRS_S6:\t\t\tis REGRS_S7 { build REGRS_S7; tsp = tsp-$(REGSIZE); MemSrcCast(s6,tsp); }\n\nREGRS_S5:\t\t\tis ext_value_xreg=3 \t {}\nREGRS_S5:\t\t\tis REGRS_S6 { build REGRS_S6; tsp = tsp-$(REGSIZE); MemSrcCast(s5,tsp); }\n\nREGRS_S4:\t\t\tis ext_value_xreg=2 \t {}\nREGRS_S4:\t\t\tis REGRS_S5 { build REGRS_S5; tsp = tsp-$(REGSIZE); MemSrcCast(s4,tsp); }\n\nREGRS_S3:\t\t\tis ext_value_xreg=1 \t {}\nREGRS_S3:\t\t\tis REGRS_S4 { build REGRS_S4; tsp = tsp-$(REGSIZE); MemSrcCast(s3,tsp); }\n\nREGRS_S2:\t\t\tis ext_value_xreg=0 \t {}\nREGRS_S2:\t\t\tis REGRS_S3 { build REGRS_S3; tsp = tsp-$(REGSIZE); MemSrcCast(s2,tsp); }\n\nREST_SREG:\t\t\t\t\t\t\tis m16_svrs_s0=0 & m16_svrs_s1=0 & ext_value_xreg=0 {}\nREST_SREG: \",\"ext_svrs_sreg\t\t\tis m16_svrs_s0 & m16_svrs_s1 & ext_value_xreg & ext_svrs_sreg & REGRS_S0 & REGRS_S1 & REGRS_S2 \n\t\t\t\t\t\t\t\t\t[ext_svrs_s0=m16_svrs_s0;ext_svrs_s1=m16_svrs_s1;ext_svrs_xs=ext_value_xreg;] {\n\tbuild REGRS_S2;\n\tbuild REGRS_S1;\n\tbuild REGRS_S0;\n}\n\nREGSV_S0:\t\t\tis m16_svrs_s0 \t\t\t\t {}\nREGSV_S0:\t\t\tis m16_svrs_s0=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s0);}\n\nREGSV_S1:\t\t\tis m16_svrs_s1 \t\t\t\t {}\nREGSV_S1:\t\t\tis m16_svrs_s1=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s1); }\n\nREGSV_S8:\t\t\tis ext_value_xreg=6 \t {}\nREGSV_S8:\t\t\tis \text_value_xreg\t\t { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s8); }\n\nREGSV_S7:\t\t\tis ext_value_xreg=5 \t {}\nREGSV_S7:\t\t\tis REGSV_S8 { build REGSV_S8; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s7); }\n\nREGSV_S6:\t\t\tis ext_value_xreg=4 \t {}\nREGSV_S6:\t\t\tis REGSV_S7 { build REGSV_S7; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s6); }\n\nREGSV_S5:\t\t\tis ext_value_xreg=3 \t {}\nREGSV_S5:\t\t\tis REGSV_S6 { build REGSV_S6; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s5); }\n\nREGSV_S4:\t\t\tis ext_value_xreg=2 \t {}\nREGSV_S4:\t\t\tis REGSV_S5 { build REGSV_S5; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s4); }\n\nREGSV_S3:\t\t\tis ext_value_xreg=1 \t {}\nREGSV_S3:\t\t\tis REGSV_S4 { build REGSV_S4; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s3); }\n\nREGSV_S2:\t\t\tis ext_value_xreg=0 \t {}\nREGSV_S2:\t\t\tis REGSV_S3 { build REGSV_S3; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s2); }\n\nSAVE_SREG:\t\t\t\t\t\t\tis m16_svrs_s0=0 & m16_svrs_s1=0 & ext_value_xreg=0 {}\nSAVE_SREG: \",\"ext_svrs_sreg\t\t\tis m16_svrs_s0 & m16_svrs_s1 & ext_value_xreg & ext_svrs_sreg & REGSV_S0 & REGSV_S1 & REGSV_S2 \n\t\t\t\t\t\t\t\t\t[ext_svrs_s0=m16_svrs_s0;ext_svrs_s1=m16_svrs_s1;ext_svrs_xs=ext_value_xreg;] {\n\tbuild REGSV_S2;\n\tbuild REGSV_S1;\n\tbuild REGSV_S0;\n}\n\nREST_RA: \t \t\t\t\t\t\tis m16_svrs_ra=0 {}\nREST_RA: \",ra\" \t\t\t\t\t\tis m16_svrs_ra=1 {\n\ttsp = tsp-$(REGSIZE);\n\tMemSrcCast(ra,tsp);\n}\n\nSAVE_RA: \t \t\t\t\t\t\tis m16_svrs_ra=0 {}\nSAVE_RA: \",ra\" \t\t\t\t\t\tis m16_svrs_ra=1 {\n \ttsp = tsp-$(REGSIZE);\n MemDestCast(tsp,ra);\n}\n\nREST_TOP: EXT_FRAME^REST_RA^REST_SREG^REST_STAT\t\t\t\tis EXT_FRAME & REST_RA & REST_SREG & REST_STAT {\n\tbuild EXT_FRAME;\n\n\ttmp:2 = EXT_FRAME;\n\ttsp = sp+zext(tmp);\n\n\tbuild REST_RA;\n\tbuild REST_SREG;\n\tbuild REST_STAT;\n\t\n\tsp = sp+zext(tmp);\n}\n\nSAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT\tis EXT_FRAME & SAVE_RA & SAVE_SREG & SAVE_ARG & SAVE_STAT { \n\ttsp = sp;\n\t\n\tbuild SAVE_ARG;\n\tbuild SAVE_RA;\n\tbuild SAVE_SREG;\n\tbuild SAVE_STAT;\n\tbuild EXT_FRAME;\n\t\n\ttmp:2 = EXT_FRAME;\n\tsp = sp - zext(tmp);\n}\n\n# The non-extended PC relative clears the lower 2 bits *after* the add.\n# The extended version clears the lower 2 bits *before* the add. The difference in how they do it is correct\n:addiu RX32, pc, EXT_IU8\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00001 & ext_is_ext=0 & RX32 & EXT_IU8 & pc & ext_delay & RX {\n\ttmp:4 = zext(EXT_IU8);\n\ttmpa:4 = ext_delay;\n\tRX32 = (inst_start + tmp - (tmpa << 1)) & 0xFFFFFFFC; \n@ifdef MIPS64\n RX = sext(RX32);\n@endif\n}\n:addiu RX32, pc, EXT_IS8\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00001 & ext_is_ext=1 & RX32 & EXT_IS8 & pc & RX {\n\ttmp:4 = sext(EXT_IS8);\n\tRX32 = (inst_start & 0xFFFFFFFC) + tmp;\n@ifdef MIPS64\n RX = sext(RX32);\n@endif\n}\n\n:addiu RX32, EXT_IS8\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01001 & RX32 & EXT_IS8 & RX {\n\ttmp:4 = sext(EXT_IS8);\n\tRX32 = RX32 + tmp;\n@ifdef MIPS64\n RX = sext(RX32);\n@endif\n}\n\n:addiu RY32, RX32, EXT_RRIA\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01000 & m16_rria_f=0 & RX32 & RY32 & EXT_RRIA & RX {\n\ttmp:4 = sext(EXT_RRIA);\n\tRY32 = RX32 + tmp;\n@ifdef MIPS64\n RX = sext(RX32);\n@endif\n}\n\n:addiu sp, EXT_IS8L3\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b011 & ext_is_ext=0 & sp & EXT_IS8L3 {\n\ttmp:$(REGSIZE) = sext(EXT_IS8L3);\n\tsp = sp + tmp;\n}\t\n\n:addiu sp, EXT_IS8\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b011 & ext_is_ext=1 & sp & EXT_IS8 {\n\ttmp:$(REGSIZE) = sext(EXT_IS8);\n\tsp = sp + tmp;\n}\n\n:addiu RX32, sp, EXT_IU8\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00000 & ext_is_ext=0 & sp & RX32 & EXT_IU8 & RX {\n\ttmp:4 = zext(EXT_IU8);\t\n\tRX32 = sp:4 + tmp;\n@ifdef MIPS64\n RX = sext(RX32);\n@endif\n}\n\n:addiu RX32, sp, EXT_IS8\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00000 & ext_is_ext=1 & sp & RX32 & EXT_IS8 & RX {\n\ttmp:4 = sext(EXT_IS8);\n\tRX32 = sp:4 + tmp;\n@ifdef MIPS64\n RX = sext(RX32);\n@endif\n}\n\n:addu RZ32, RX32, RY32\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=0 & m16_op=0b11100 & m16_rrr_f=0b01 & RX32 & RY32 & RZ32 & RZ {\n\tRZ32 = RX32 + RY32;\n@ifdef MIPS64\n RZ = sext(RZ32);\n@endif\n}\n\n:and m16_rx, m16_ry\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01100 & m16_rx & m16_ry {\n\tm16_rx = m16_rx & m16_ry;\n}\n\n:asmacro ext_value_select\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b11100 & ext_value_select {\n}\n\n:b Rel16_m16\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00010 & Rel16_m16 {\n\tgoto Rel16_m16;\n}\n\n:beqz RX32, CRel16_m16\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00100 & RX32 & CRel16_m16 {\n\tif (RX32 == 0) goto CRel16_m16;\n}\n\n:bnez RX32, CRel16_m16\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00101 & RX32 & CRel16_m16 {\n\tif (RX32 != 0) goto CRel16_m16;\n}\n\n:break m16_code\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00101 & m16_code {\n tmp:4=m16_code; \n trap(tmp); \n}\n\n:bteqz CRel16_m16\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b000 & CRel16_m16 {\n\tif (t8 == 0) goto CRel16_m16;\n}\n\n:btnez CRel16_m16\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b001 & CRel16_m16 {\n\tif (t8 != 0) goto CRel16_m16;\n}\n\n:cmp m16_rx, m16_ry\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01010 & m16_rx & m16_ry {\n\tt8 = m16_rx ^ m16_ry;\n}\n\n:cmpi m16_rx, m16_iu8_imm\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01110 & ext_is_ext=0 & m16_rx & m16_iu8_imm {\n\ttmpa:1 = m16_iu8_imm;\n\ttmp:$(REGSIZE) = zext(tmpa);\n\tt8 = m16_rx ^ tmp;\n}\n\n:cmpi m16_rx, EXT_RI\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01110 & ext_is_ext=1 & m16_rx & EXT_RI {\n\ttmp:$(REGSIZE) = zext(EXT_RI);\n\tt8 = m16_rx ^ tmp;\n}\n\n:div RX32, RY32\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11010 & RX32 & RY32 {\n\tif (RY32 == 0) goto ;\n lo = sext(RX32 s/ RY32); \n hi = sext(RX32 s% RY32); \n \n}\n\n:divu RX32, RY32\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11011 & RX32 & RY32 {\n\tif (RY32 == 0) goto ;\n lo = sext(RX32 / RY32); \n hi = sext(RX32 % RY32); \n \n}\n\n:jal Abs26_m16\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=0 & Abs26_m16 [ ext_delay=0b10; globalset(inst_next, ext_delay);] {\n ra = inst_next | 0x1; \n delayslot( 1 ); \n call Abs26_m16;\n #double check gpr31 bit\n}\n\n:jalr m16_rx\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx\n[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { \n\tJXWritePC(m16_rx); \n ra = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jalrc m16_rx\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=1 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx { \n\tJXWritePC(m16_rx); \n ra = inst_next | 0x1; \n call [pc];\n}\n\n:jalx Abs26_m16\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=1 & Abs26_m16 \n[ ext_delay=0b10; ISA_MODE = 0; globalset(Abs26_m16, ISA_MODE); globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] {\n ra = inst_next | 0x1; \n delayslot( 1 );\n ISAModeSwitch = 0; \n call Abs26_m16;\n}\n\n:jr ra\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0\n[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { \n\tJXWritePC(ra); \n delayslot( 1 ); \n return [pc];\n}\n\n:jr m16_rx\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx\n[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { \n\tJXWritePC(m16_rx); \n delayslot( 1 ); \n goto [pc];\n}\n\n:jrc ra\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=1 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0 { \n\tJXWritePC(ra); \n return [pc];\n}\n\n:jrc m16_rx\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=1 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx { \n\tJXWritePC(m16_rx); \n goto [pc];\n}\n\n:lb m16_ry, OFF_M16S0\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10000 & m16_ry & OFF_M16S0 {\n m16_ry = sext(*[ram]:1 OFF_M16S0); \n}\n\n:lbu m16_ry, OFF_M16S0\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10100 & m16_ry & OFF_M16S0 {\n m16_ry = zext(*[ram]:1 OFF_M16S0); \n}\n\n:lh m16_ry, OFF_M16S1\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10001 & m16_ry & OFF_M16S1 {\n m16_ry = sext(*[ram]:2 OFF_M16S1); \n}\n\n:lhu m16_ry, OFF_M16S1\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10101 & m16_ry & OFF_M16S1 {\n m16_ry = zext(*[ram]:2 OFF_M16S1); \n}\n\n:li m16_rx, EXT_LIU8\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01101 & m16_rx & EXT_LIU8 {\n\tm16_rx = zext(EXT_LIU8);\n}\n\n:lw m16_ry, OFF_M16\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10011 & m16_ry & OFF_M16 {\n m16_ry = sext(*[ram]:4 OFF_M16); \n}\n\n:lw m16_rx, OFF_M16PC\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10110 & m16_rx & OFF_M16PC {\n m16_rx = sext(*[ram]:4 OFF_M16PC); \n}\n\n:lw m16_rx, OFF_M16SP\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10010 & m16_rx & OFF_M16SP {\n m16_rx = sext(*[ram]:4 OFF_M16SP); \n}\n\n:mfhi m16_rx\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10000 & m16_rr_z=0 & m16_rx {\n\tm16_rx = hi;\n}\n\n:mflo m16_rx\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10010 & m16_rr_z=0 & m16_rx {\n\tm16_rx = lo;\n}\n\n:move ext_m16r32, m16_mv_rz\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b101 & ext_m16r32 & m16_mv_rz & m16_i8_r32_20 & m16_i8_r32_43 [ ext_reg_low = m16_i8_r32_20; ext_reg_high = m16_i8_r32_43 ; ] {\n\text_m16r32 = m16_mv_rz;\n}\n\n:move m16_ry, m16_i8_r32\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b111 & m16_ry & m16_i8_r32 {\n\tm16_ry = m16_i8_r32;\n}\n\n:mult RX32, RY32\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11000 & RX32 & RY32 {\n tmp1:8 = sext( RX32 );\n tmp2:8 = sext( RY32 );\n prod:8 = tmp1 * tmp2;\n lo = sext(prod:4); \n prod = prod >> 32;\n hi = sext(prod:4); \n}\n\n:multu RX32, RY32\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11001 & RX32 & RY32 {\n tmp1:8 = zext( RX32 );\n tmp2:8 = zext( RY32 );\n prod:8 = tmp1 * tmp2;\n lo = sext(prod:4); \n prod = prod >> 32;\n hi = sext(prod:4); \n}\n\n:neg RX, RY32\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01011 & RX & RY32 {\n\tRX = sext(0-RY32);\n}\n\n:not m16_rx, m16_ry\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01111 & m16_rx & m16_ry {\n\tm16_rx = ~m16_ry;\n}\n\n# nop is technically a special case of a move instruction that moves 0 to 0\n:nop\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b101 & m16_i8_imm=0 & m16_ri_z=0 {}\n\n:or m16_rx, m16_ry\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01101 & m16_rx & m16_ry {\n\tm16_rx = m16_rx | m16_ry;\n}\n\n\n# save/restore argument format\n#,,,,\n:restore REST_TOP\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b100 & m16_svrs_s=0 & REST_TOP {\n\tbuild REST_TOP;\n}\n\n:save SAVE_TOP\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b100 & m16_svrs_s=1 & SAVE_TOP {\n\tbuild SAVE_TOP;\n}\n\n:sb RY32, OFF_M16S0\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11000 & RY32 & OFF_M16S0 {\n *[ram]:1 OFF_M16S0 = RY32:1; \n}\n\n:sdbbp m16_code \t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00001 & m16_code {\n signalDebugBreakpointException();\n}\n\n:seb m16_rx\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10001 & m16_rr_z=0b100 & m16_rx {\n\ttmp:1 = m16_rx:1;\n\ttmpb:$(REGSIZE) = sext(tmp);\n\tm16_rx = tmpb;\n}\n\n:seh m16_rx\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10001 & m16_rr_z=0b101 & m16_rx {\n\ttmp:2 = m16_rx:2;\n\ttmpb:$(REGSIZE) = sext(tmp);\n\tm16_rx = tmpb;\n}\n\n:sh m16_ry, OFF_M16S1\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11001 & m16_ry & OFF_M16S1 {\n\t*[ram]:2 OFF_M16S1 = m16_ry:2;\n}\n\n:sll m16_rx, m16_ry, EXT_SHIFT\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00110 & m16_shft_f=0b00 & m16_rx & m16_ry & EXT_SHIFT {\n\tm16_rx = m16_ry << EXT_SHIFT;\n}\n\n:sllv m16_ry, m16_rx\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00100 & m16_rx & m16_ry {\n\tm16_ry = m16_ry << (m16_rx & 0x1f);\n}\n\n:slt m16_rx, m16_ry\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00010 & m16_rx & m16_ry {\n t8 = zext( m16_rx s< m16_ry ); \n}\n\n:slti m16_rx, EXT_SET \t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01010 & m16_rx & EXT_SET {\n\ttmpa:4 = EXT_SET;\n\ttmp:$(REGSIZE) = sext(tmpa);\n\tt8 = zext( m16_rx s< tmp);\n}\n\n:sltiu m16_rx, EXT_SET \t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01011 & m16_rx & EXT_SET {\n\ttmpa:4 = EXT_SET;\n\ttmp:$(REGSIZE) = sext(tmpa);\n\tt8 = zext( m16_rx < tmp);\n}\n\n:sltu m16_rx, m16_ry\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00011 & m16_rx & m16_ry {\n t8 = zext( m16_rx < m16_ry ); \n}\n\n:sra m16_rx, m16_ry, EXT_SHIFT\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00110 & m16_shft_f=0b11 & m16_rx & m16_ry & EXT_SHIFT {\n\tm16_rx = m16_ry s>> EXT_SHIFT;\n}\n\n:srav m16_ry, m16_rx\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00111 & m16_rx & m16_ry {\n\tm16_ry = m16_ry s>> (m16_rx & 0x1f);\n}\n\n:srl m16_rx, m16_ry, EXT_SHIFT\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00110 & m16_shft_f=0b10 & m16_rx & m16_ry & EXT_SHIFT {\n\tm16_rx = m16_ry >> EXT_SHIFT;\n}\n\n:srlv m16_ry, m16_rx\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00110 & m16_rx & m16_ry {\n\tm16_ry = m16_ry >> (m16_rx & 0x1f);\n}\n\n:subu RZ32, RX32, RY32\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=0 & m16_op=0b11100 & m16_rrr_f=0b11 & RX32 & RY32 & RZ32 & RZ {\n\tRZ32 = RX32 - RY32;\n@ifdef MIPS64\n RZ = sext(RZ32);\n@endif\n}\n\n:sw m16_ry, OFF_M16\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11011 & m16_ry & OFF_M16 {\n *[ram]:4 OFF_M16 = m16_ry:4; \n}\n\n:sw m16_rx, OFF_M16SP\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11010 & m16_rx & OFF_M16SP {\n *[ram]:4 OFF_M16SP = m16_rx:4; \n}\n\n:sw ra, OFF_M16SP\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_sw=0b010 & ra & OFF_M16SP {\n *[ram]:4 OFF_M16SP = ra:4; \n}\n\n:xor m16_rx, m16_ry\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01110 & m16_rx & m16_ry {\n m16_rx = m16_rx ^ m16_ry; \n}\n\n:zeb m16_rx\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_z=0b000 & m16_rr_f=0b10001 & m16_rx {\n\ttmp:1 = m16_rx:1;\n m16_rx = zext(tmp); \n}\n\n:zeh m16_rx\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_z=0b001 & m16_rr_f=0b10001 & m16_rx {\n\ttmp:2 = m16_rx:2;\n m16_rx = zext(tmp); \n}\n\n\n\n################\n#\n# MIPS16e2\n#\n# MIPS16e2 Application Specific Extension\n# Technical Reference Manual\n#\n# Document #: MD01172 Rev 1.00 April 26, 2016\n#\n################\n\n\nE2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 << 5);] { export *[const]:2 imm; }\n\n\n:addiu m16_rx, gp, EXT_IS8\t\t\t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b00000 & ext_is_ext=1 & gp & m16_rx & m16_ri_z=1 & EXT_IS8 {\n\tm16_rx = gp + sext(EXT_IS8);\n}\n\n:andi m16_rx, EXT_LIU8\t\t\t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=3 & EXT_LIU8 {\n\tm16_rx = m16_rx & zext(EXT_LIU8);\n}\n\n:cache ext_imm_1620, E2_REGOFF(m16_rx)\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1620 & m16_op=0b11010 & m16_rx & m16_ri_z=5 & E2_REGOFF {\n local tmp:$(REGSIZE) = m16_rx + sext(E2_REGOFF);\n cacheOp(ext_imm_1620:1, tmp);\n}\n\n:di\t \t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00110 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0b01100 {\n Status = Status & ~1;\n}\n:di m16_ry\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00010 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0b01100 {\n m16_ry = Status;\n Status = Status & ~1; # clearing last bit (ffff..fffe == -2 signed)\n}\n\n:dmt\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00110 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=1 {\n\t# Clear VPEControl IE bit (bit 15)\n\tVPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0;\n}\n:dmt m16_ry\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00010 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=1 {\n # Clear VPEControl IE bit (bit 15)\n\tm16_ry = VPEControl; VPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0;\n}\n\n:dvpe m16_ry\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00010 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0 {\n\t# Clear MVPControl EVP bit (bit 0)\n\tm16_ry = MVPControl; MVPControl = MVPControl & ~0x1;\n}\n:dvpe\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00110 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0 {\n\t# Clear MVPControl EVP bit (bit 0)\n\tMVPControl = MVPControl & ~0x1;\n}\n\n:ehb\t\t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0b00011 & ext_imm_21=0 & ext_imm_1620=0 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=4 & m16_shft_f=0 {\n}\n\n:ei\t \t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00111 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0b01100 {\n Status = Status | 1;\n}\n:ei m16_ry\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00011 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0b01100 {\n m16_ry = Status;\n Status = Status | 1;\n}\n\n:emt\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00111 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=1 {\n # Set VPEControl TE bit (bit 15)\n\tVPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1;\n}\n:emt m16_ry\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00011 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=1 {\n # Set VPEControl TE bit (bit 15)\n\tm16_ry = VPEControl; VPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1;\n}\n\n:evpe\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00111 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0 {\n # Set MVPControl EVP bit (bit 0)h\n\tMVPControl = MVPControl | 0x1;\n}\n:evpe m16_ry\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00011 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0 {\n # Set MVPControl EVP bit (bit 0)h\n\tm16_ry = MVPControl;\n\tMVPControl = MVPControl | 0x1;\n}\n\n:ext m16_ry, m16_rx, ext_imm_2226, ext_size \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=1 & ext_imm_1620 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0 [ ext_size = ext_imm_1620+1; ] {\n local rs_tmp:$(REGSIZE) = m16_rx << ($(REGSIZE) * 8 - (ext_size + ext_imm_2226));\n rs_tmp = rs_tmp >> ($(REGSIZE) * 8 - ext_size);\n m16_ry = zext(rs_tmp);\n}\n:ins m16_ry, m16_rx, ext_imm_2226, ins_size\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=1 & ext_imm_1620 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0 [ ins_size = ext_imm_1620 - ext_imm_2226 + 1; ] {\n local tmpa:$(REGSIZE) = -1;\n tmpa = tmpa >> ($(REGSIZE) * 8 - ins_size);\n local tmpb:$(REGSIZE) = m16_rx & tmpa;\n tmpa = tmpa << ext_imm_2226;\n tmpa = ~tmpa;\n tmpb = tmpb << ext_imm_2226;\n m16_ry = (m16_ry & tmpa) | tmpb;\n\n}\n:ins m16_ry, zero, ext_imm_2226, ins_size\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=0 & ext_imm_1620 & m16_op=0b00110 & m16_rx=0 & m16_ry & m16_shft_sa=1 & m16_shft_f=0 & zero [ ins_size = ext_imm_1620 - ext_imm_2226 + 1; ] {\n\tlocal tmpa:$(REGSIZE) = -1;\n tmpa = tmpa >> ($(REGSIZE) * 8 - ins_size);\n tmpa = tmpa << ext_imm_2226;\n tmpa = ~tmpa;\n m16_ry = (m16_ry & tmpa);\n}\n\n# LB/LBU/LH/LHU/LW - handled by mips16\n\n:ll m16_rx, E2_REGOFF(ext_rb)\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0 & ext_rb & m16_op=0b10010 & m16_rx & m16_ri_z=6 & E2_REGOFF {\n local tmp:$(REGSIZE) = sext(E2_REGOFF);\n\ttmp = tmp + ext_rb;\n\tlocal tmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n m16_rx = sext(*[ram]:4 tmpa);\n lockload(tmp);\n}\n\n:lui m16_rx, EXT_LIU8\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01101 & m16_rx & m16_ri_z=1 & EXT_LIU8 {\n\tm16_rx = zext(EXT_LIU8) << 16;\n}\n\n:lwl m16_rx, E2_REGOFF(ext_rb)\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0 & ext_rb & m16_op=0b10010 & m16_rx & m16_ri_z=7 & E2_REGOFF {\n\tlocal tmp:$(REGSIZE) = sext(E2_REGOFF);\n\ttmp = tmp + ext_rb;\n local shft:$(REGSIZE) = tmp & 0x3;\n local addr:$(REGSIZE) = tmp - shft;\n local valOrig:4 = m16_rx:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8));\n local valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad << (shft * 8);\n m16_rx = sext( valLoad | valOrig );\n}\n\n:lwr m16_rx, E2_REGOFF(ext_rb)\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0b10 & ext_rb & m16_op=0b10010 & m16_rx & m16_ri_z=7 & E2_REGOFF {\n\tlocal tmp:$(REGSIZE) = sext(E2_REGOFF);\n\ttmp = tmp + ext_rb;\n local shft:$(REGSIZE) = tmp & 0x3;\n local addr:$(REGSIZE) = tmp - shft;\n local valOrig:4 = m16_rx:$(SIZETO4) & (0xffffffff << ((shft+1) * 8));\n local valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad >> ((3-shft) * 8);\n m16_rx = sext( valOrig | valLoad );\n}\n\n:mfc0 m16_ry, m16_i_imm, ext_imm_2123\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=0 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm {\n m16_ry = getCopReg(0:1,m16_i_imm:1,ext_imm_2123:1);\n}\n:mtc0 m16_ry, m16_i_imm, ext_imm_2123\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=1 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm {\n setCopReg(0:1,m16_ry,m16_i_imm:1,ext_imm_2123:1);\n}\n\n:movz m16_rx, m16_ry, ext_rb\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 {\n if(m16_ry != 0) goto inst_next;\n m16_rx = ext_rb;\n}\n\n:movz m16_rx, zero, m16_ry\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb=0 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 & zero {\n if(m16_ry != 0) goto inst_next;\n m16_rx = 0;\n}\n\n:movn m16_rx, m16_ry, ext_rb\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0b10 {\n if(m16_ry == 0) goto inst_next;\n m16_rx = ext_rb;\n}\n\n:movn m16_rx, zero, m16_ry\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb=0 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0b10 & zero {\n if(m16_ry == 0) goto inst_next;\n m16_rx = 0;\n}\n\n:movtn m16_rx, zero\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=6 & m16_shft_f=0b10 & zero {\n if(t8 == 0) goto inst_next;\n m16_rx = 0;\n}\n\n:movtn m16_rx, ext_rb\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=6 & m16_shft_f=0b10 {\n if(t8 == 0) goto inst_next;\n m16_rx = ext_rb;\n}\n\n:movtz m16_rx, zero\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=5 & m16_shft_f=0b10 & zero {\n if(t8 != 0) goto inst_next;\n m16_rx = 0;\n}\n\n:movtz m16_rx, ext_rb\t \tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=5 & m16_shft_f=0b10 {\n if(t8 != 0) goto inst_next;\n m16_rx = ext_rb;\n}\n\n:pause is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0b00101 & ext_imm_21=0 & ext_imm_1620=0 & m16_op=0b00110 & m16_rx=0 & m16_rr_z=0 & m16_shft_sa=6 & m16_shft_f=0 {\n wait();\n}\n\n:pref ext_imm_1620, E2_REGOFF(m16_rx) \t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1620 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=4 & E2_REGOFF {\n local tmp:$(REGSIZE) = m16_rx + sext(E2_REGOFF);\n prefetch(tmp, ext_imm_1620:1);\n}\n\n:ori m16_rx, EXT_LIU8\t\t\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=2 & EXT_LIU8 {\n\tm16_rx = m16_rx | zext(EXT_LIU8);\n}\n\n:rdhwr m16_ry, ext_imm_1620 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1620 & m16_op=0b00110 & m16_rx=0 & m16_ry & m16_shft_sa=3 & m16_shft_f=0 {\n m16_ry = getHWRegister(ext_imm_1620:1);\n}\n\n# SB/SH/SW - handled by mips16\n\n:sc\tm16_rx, E2_REGOFF(ext_rb)\t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=6 & E2_REGOFF{\n local tmp:$(REGSIZE) = sext(E2_REGOFF);\n\ttmp = tmp + ext_rb;\n lockwrite(tmp);\n\tlocal tmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = m16_rx;\n\tm16_rx = 1;\n}\n\n:swl m16_rx, E2_REGOFF(ext_rb)\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0b00 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=7 & E2_REGOFF{\n local tmp:$(REGSIZE) = sext(E2_REGOFF);\n\ttmp = tmp + ext_rb;\n local tmpRT:4 = m16_rx:$(SIZETO4);\n local shft:$(REGSIZE) = tmp & 0x3;\n local addr:$(REGSIZE) = tmp - shft;\n local valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff << ((4-shft) * 8));\n local valStore:4 = (tmpRT >> (shft * 8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swr m16_rx, E2_REGOFF(ext_rb)\t\tis ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0b10 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=7 & E2_REGOFF {\n local tmp:$(REGSIZE) = sext(E2_REGOFF);\n\ttmp = tmp + ext_rb;\n local tmpRT:4 = m16_rx:$(SIZETO4);\n local shft:$(REGSIZE) = tmp & 0x3;\n local addr:$(REGSIZE) = tmp - shft;\n local valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff >> ((shft+1) * 8));\n local valStore:4 = (tmpRT << ((3-shft)*8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:sync ext_imm_2226 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=0 & ext_imm_1620=0 & m16_op=0b00110 & m16_rx=0 & m16_ry=0 & m16_shft_sa=5 & m16_shft_f=0b00 {\n SYNC(ext_imm_2226:1);\n}\n\n:xori m16_rx, EXT_LIU8\t\t is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=4 & EXT_LIU8 {\n\tm16_rx = m16_rx ^ zext(EXT_LIU8);\n}\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32Instructions.sinc", "content": "############################\n#\n# MIPS32\n# Basic and FP (COP1) instructions\n# \n# (See bottom of file for MIPS64 instructions included with MIPS32)\n#\n############################\n\n@if defined(ISA_VARIANT)\n@define AMODE \"ISA_MODE=0\"\t# ISA_MODE must restrict MIPS instruction decoding and require ISA_MODE=0\n@else\n@define AMODE \"epsilon\"\t\t\t# Mips16 instructions not supported - Mips32 only\n@endif\n\n# 0000 00ss ssst tttt dddd d000 0010 0000\n:add RD32, RS32src, RT32src is $(AMODE) & prime=0 & sa=0 & fct=0x20 & RD32 & RS32src & RT32src & RD {\n RD32 = RS32src + RT32src;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n\n# 0010 01ss ssst tttt iiii iiii iiii iiii\n:addiu RT32, RS32src, simmed is $(AMODE) & prime=9 & RT32 & RS32src & simmed & RT {\n RT32 = RS32src + simmed;\n@ifdef MIPS64\n RT = sext(RT32);\n@endif\n}\n\n# 0000 00ss ssst tttt dddd d000 0010 0001\n:addu RD32, RS32src, RT32src is $(AMODE) & prime=0 & fct=0x21 & RS32src & RT32src & RD32 & sa=0 & RD {\n RD32 = RS32src + RT32src;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n\n# 0000 00ss ssst tttt dddd d000 0010 0100\n:and RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x24 & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc & RTsrc; \n}\n\n# 0011 00ss ssst tttt iiii iiii iiii iiii\n:andi RT, RSsrc, immed is $(AMODE) & prime=0xC & RSsrc & RT & immed {\n RT = RSsrc & immed; \n}\n\n# 0001 0000 0000 0000 iiii iiii iiii iiii \n:b Rel16 is $(AMODE) & prime=4 & rs=0 & rt=0 & Rel16 {\n delayslot(1); \n goto Rel16; \n}\n\n# 0001 00ss ssst tttt iiii iiii iiii iiii \n:beq RSsrc, RTsrc, Rel16 is $(AMODE) & prime=4 & RSsrc & RTsrc & Rel16 {\n delayflag:1 = ( RSsrc == RTsrc ); \n delayslot( 1 ); \n if delayflag goto Rel16; \n}\n\n# 0000 01ss sss0 0001 iiii iiii iiii iiii \n:bgez RSsrc, Rel16 is $(AMODE) & prime=1 & cond=1 & RSsrc & Rel16 {\n delayflag:1 = ( RSsrc s>= 0 ); \n delayslot( 1 ); \n if delayflag goto Rel16; \n}\n# 0001 11ss sss0 0000 iiii iiii iiii iiii \n:bgtz RSsrc, Rel16 is $(AMODE) & prime=7 & cond=0 & RSsrc & Rel16 {\n delayflag:1 = ( RSsrc s> 0 ); \n delayslot( 1 ); \n if delayflag goto Rel16; \n} \n# 0001 10ss sss0 0000 iiii iiii iiii iiii \n:blez RSsrc, Rel16 is $(AMODE) & prime=6 & cond=0 & RSsrc & Rel16 {\n delayflag:1 = ( RSsrc s<= 0 ); \n delayslot( 1 ); \n if delayflag goto Rel16; \n}\n\n# 0000 01ss sss0 0000 iiii iiii iiii iiii \n:bltz RSsrc, Rel16 is $(AMODE) & prime=1 & cond=0 & RSsrc & Rel16 {\n delayflag:1 = ( RSsrc s< 0 ); \n delayslot( 1 ); \n if delayflag goto Rel16; \n}\n# 0001 01ss ssst tttt iiii iiii iiii iiii \n:bne RSsrc, RTsrc, Rel16 is $(AMODE) & prime=5 & RSsrc & RTsrc & Rel16 {\n delayflag:1 = ( RSsrc != RTsrc ); \n delayslot( 1 ); \n if delayflag goto Rel16; \n}\n\n# 0000 00cc cccc cccc cccc cccc cc00 1101\n:break breakcode is $(AMODE) & prime=0 & fct=0xD & breakcode {\n tmp:4=breakcode; \n trap(tmp); \n}\n\n# 1011 11bb bbbo oooo iiii iiii iiii iiii\n:cache op, OFF_BASER6 is $(AMODE) & ((prime=0x2F & REL6=0) | (prime=0x1F & REL6=1 & fct=0x25 & bit6=0)) & OFF_BASER6 & op {\n cacheOp(op:1, OFF_BASER6); \n}\n\n:cachee op, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1B & bit6=0 & OFF_BASER6 & op {\n cacheOp(op:1, OFF_BASER6); \n}\n\n:cfc0 RT, RD0 is $(AMODE) & prime=0x10 & copop=2 & RT & RD0 & bigfunct=0 {\n RT = sext( RD0:$(SIZETO4) );\n}\n\n# 0100 1000 010t tttt ssss s000 0000 0000\n:cfc2 RT, immed is $(AMODE) & prime=0x12 & copop=2 & RT & immed {\n tmp:4 = getCopControlWord( 2:1, immed:4 );\n RT = sext(tmp);\n}\n\n# Special case of ADDU\n# 0000 0000 0000 0000 dddd d000 0010 0001\n:clear RD is $(AMODE) & prime=0 & fct=0x21 & rs=0 & rt=0 & RD & sa=0 {\n RD = 0; \n}\n\ndefine pcodeop special2;\n\n# 0111 00ss ssst tttt dddd daaa aaxx xyyy\n# valid values of x and y:\n# x: 0 y: 3,6,7\n# x: 1 y: 0-7\n# x: 2 y: 0-7\n# x: 3 y: 0-7\n# x: 4 y: 2,3,6,7\n# x: 5 y: 0-7\n# x: 6 y: 0-7\n# x: 7 y: 0-6\n:SPECIAL2 RD, RSsrc, RTsrc, sa, fct is $(AMODE) & prime=0x1C & sa & RD & RSsrc & RTsrc & fct {\n tmp:1 = fct;\n tmp2:1 = sa;\n RD = special2(RSsrc, RTsrc, tmp2, tmp);\n}\n\n# 0100 101c cccc cccc cccc cccc cccc cccc\n:cop2 cofun is $(AMODE) & prime=0x12 & bit25=1 & cofun {\n arg:4 = cofun;\n copFunction(2:1, arg);\n}\n\n:ctc0 RTsrc, RD0 is $(AMODE) & prime=0x10 & copop=6 & RTsrc & RD0 & bigfunct=0 {\n RD0 = RTsrc;\n}\n# 0100 1000 110t tttt iiii iiii iiii iiii\n:ctc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=6 & RTsrc & immed {\n setCopControlWord( 2:1, immed:4, RTsrc );\n}\n\n# 0100 0010 0000 0000 0000 0000 0001 1111 \n:deret is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x0 & fct=0x1F {\n return[DEPC];\n}\n\n# 0100 0001 011t tttt 0110 0000 0000 0000\n:di is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x0 & zero3=0x0 & rt=0x0 {\n Status = Status & -2; # clearing last bit (ffff..fffe == -2 signed)\n}\n:di RT is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x0 & zero3=0x0 & RT {\n RT = Status;\n Status = Status & -2; # clearing last bit (ffff..fffe == -2 signed)\n}\n\n# 0000 0000 0000 0000 0000 0000 1100 0000\n:ehb is $(AMODE) & prime=0x0 & rs=0x0 & rt=0x0 & rd=0x0 & fct2=0x3 & fct=0x0 {\n} \n\n# 0100 0001 011t tttt 0110 0000 0010 0000\n:ei is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x01 & zero3=0x0 & rt=0x0 {\n Status = Status | 1;\n}\n:ei RT is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x01 & zero3=0x0 & RT {\n RT = Status;\n Status = Status | 1;\n}\n\n# MIPS R3000 and prior only, replaced with ERET in R4000 and later\n# 0100 0010 0000 0000 0000 0000 0001 0000\n:rfe is $(AMODE) & prime=0x10 & fct=0x10 & bit25=1 & copfill=0 {\n local currentStatus = Status;\n Status = (currentStatus & 0xfffffff0) | ((currentStatus & 0x3c) >> 2);\n}\n\n# 0100 0010 0000 0000 0000 0000 0001 1000\n:eret is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=0 {\n return[EPC];\n}\n\n:eretnc\t\t\t\t\t\t\tis $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=1 {\n return[EPC];\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0000 \n:ext RT, RSsrc, lsb, ExtSize is $(AMODE) & prime=0x1F & fct=0x0 & RT & RSsrc & lsb & msbd & ExtSize {\n # Extract Bit Field\n # RT = extractField(RSsrc, msbd:1, lsb:1);\n # Note that msbd = size - 1\n rs_tmp:$(REGSIZE) = RSsrc << ($(REGSIZE) * 8 - (msbd + lsb + 1));\n rs_tmp = rs_tmp >> ($(REGSIZE) * 8 - (msbd + 1));\n RT = zext(rs_tmp);\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0100\n:ins RT, RSsrc, lsb, InsSize is $(AMODE) & prime=0x1F & fct=0x04 & RT & RTsrc & RSsrc & lsb & msbd & InsSize {\n tmpa:$(REGSIZE) = -1;\n tmpa = tmpa >> ($(REGSIZE) * 8 - InsSize);\n tmpb:$(REGSIZE) = RSsrc & tmpa;\n tmpa = tmpa << lsb;\n tmpa = ~tmpa;\n tmpb = tmpb << lsb;\n RT = (RT & tmpa) | tmpb;\n}\n\n# 0000 10aa aaaa aaaa aaaa aaaa aaaa aaaa\n:j Abs26 is $(AMODE) & prime=2 & Abs26 {\n delayslot( 1 ); \n goto Abs26; \n}\n# 0000 11aa aaaa aaaa aaaa aaaa aaaa aaaa\n:jal Abs26 is $(AMODE) & prime=3 & Abs26 {\n ra = inst_next; \n delayslot( 1 ); \n call Abs26; \n}\n@ifdef ISA_VARIANT\n# 0000 00ss sss0 0000 dddd dhhh hh00 1001\n:jalr RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD {\n\tbuild RD;\n\tbuild RSsrc;\n\tJXWritePC(RSsrc); \n RD = inst_next;\n delayslot( 1 );\n call [pc];\n}\n:jalr RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F {\n\tbuild RSsrc;\n\tJXWritePC(RSsrc); \n ra = inst_next; \n delayslot( 1 ); \n call [pc];\n}\n@else\n# 0000 00ss sss0 0000 dddd dhhh hh00 1001\n:jalr RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD {\n RD = inst_next;\n delayslot( 1 );\n\ttmp:$(ADDRSIZE) = 0;\n\tValCast(tmp,RSsrc);\n call [tmp]; \n}\n:jalr RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F {\n ra = inst_next; \n delayslot( 1 ); \n\ttmp:$(ADDRSIZE) = 0;\n\tValCast(tmp,RSsrc);\n call [tmp]; \n}\n@endif\n@ifdef ISA_VARIANT\n# 0000 00ss sss0 0000 dddd d1hh hh00 1001\n:jalr.hb RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD & bit10=1 {\n\tbuild RD;\n\tbuild RSsrc;\n\tJXWritePC(RSsrc); \n RD = inst_next; \n delayslot( 1 ); \n call [pc];\n}\n:jalr.hb RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F & bit10=1 {\n \tbuild RSsrc;\n\tJXWritePC(RSsrc); \n ra = inst_next; \n delayslot( 1 ); \n call [pc];\n}\n@else\n# 0000 00ss sss0 0000 dddd d1hh hh00 1001\n:jalr.hb RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD & bit10=1 {\n RD = inst_next; \n delayslot( 1 ); \n\ttmp:$(ADDRSIZE) = 0;\n\tValCast(tmp,RSsrc);\n call [tmp]; \n}\n:jalr.hb RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F & bit10=1 {\n ra = inst_next; \n delayslot( 1 ); \n\ttmp:$(ADDRSIZE) = 0;\n\tValCast(tmp,RSsrc);\n call [tmp]; \n}\n@endif\n\n@ifdef ISA_VARIANT\n# 0000 00ss sss0 0000 0000 0hhh hh00 1000\n:jr RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 {\n \tbuild RSsrc;\n\tJXWritePC(RSsrc); \n delayslot(1); \n goto [pc]; \n}\n@else\n# 0000 00ss sss0 0000 0000 0hhh hh00 1000\n:jr RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 {\n delayslot(1); \n \ttmp:$(ADDRSIZE) = 0;\n\tValCast(tmp,RSsrc);\n goto [tmp]; \n}\n@endif\n@ifdef ISA_VARIANT\n# 0000 00ss sss0 0000 0000 01hh hh00 1000\n:jr.hb RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 & bit10=1 {\n \tbuild RSsrc;\n\tJXWritePC(RSsrc); \n delayslot(1); \n goto [pc]; \n}\n@else\n# 0000 00ss sss0 0000 0000 01hh hh00 1000\n:jr.hb RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 & bit10=1 {\n delayslot(1); \n \ttmp:$(ADDRSIZE) = 0;\n\tValCast(tmp,RSsrc);\n goto [tmp]; \n}\n@endif\n\n# Special case of JR\n# 0000 0011 1110 0000 0000 0hhh hh00 1000\n@ifdef ISA_VARIANT\n:jr ra is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & rs=0x1F & ra & rt=0 & rd=0 & sa=0 {\n\tJXWritePC(ra); \n delayslot(1); \n return[pc]; \n}\n@else\n:jr ra is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & rs=0x1F & ra & rt=0 & rd=0 & sa=0 {\n delayslot(1); \n return[ra]; \n}\n@endif\n\n\n\n\n# 1000 00bb bbbt tttt iiii iiii iiii iiii\n:lb RT, OFF_BASE is $(AMODE) & prime=0x20 & OFF_BASE & RT {\n RT = sext(*[ram]:1 OFF_BASE); \n}\n\n:lbe RT, OFF_BASER6 \tis $(AMODE) & prime=0x1F & fct=0x2C & bit6=0 & OFF_BASER6 & RT {\n RT = sext(*[ram]:1 OFF_BASER6); \n}\n\n# 1001 00bb bbbt tttt iiii iiii iiii iiii\n:lbu RT, OFF_BASE is $(AMODE) & prime=0x24 & OFF_BASE & RT {\n RT = zext( *[ram]:1 OFF_BASE );\n}\n\n:lbue RT, OFF_BASER6 \tis $(AMODE) & prime=0x1F & fct=0x28 & bit6=0 & OFF_BASER6 & RT {\n RT = zext( *[ram]:1 OFF_BASER6 );\n}\n\n# 1000 01bb bbbt tttt iiii iiii iiii iiii\n:lh RT, OFF_BASE is $(AMODE) & prime=0x21 & OFF_BASE & RT {\n RT = sext( *[ram]:2 OFF_BASE );\n}\n\n:lhe RT, OFF_BASER6 \tis $(AMODE) & prime=0x1F & fct=0x2D & bit6=0 & OFF_BASER6 & RT {\n RT = sext( *[ram]:2 OFF_BASER6 );\n}\n\n# 1001 01bb bbbt tttt iiii iiii iiii iiii\n:lhu RT, OFF_BASE is $(AMODE) & prime=0x25 & OFF_BASE & RT {\n RT = zext( *[ram]:2 OFF_BASE ); \n}\n\n:lhue RT, OFF_BASER6 \tis $(AMODE) & prime=0x1F & fct=0x29 & bit6=0 & OFF_BASER6 & RT {\n RT = zext( *[ram]:2 OFF_BASER6 ); \n}\n\n:lle RT, OFF_BASER6 \tis $(AMODE) & prime=0x1F & fct=0x2E & bit6=0 & OFF_BASER6 & RT {\n RT = sext(*[ram]:4 OFF_BASER6);\n}\n\n# 1000 11bb bbbt tttt iiii iiii iiii iiii\n:lw RT, OFF_BASE is $(AMODE) & prime=0x23 & OFF_BASE & RT {\n RT = sext( *[ram]:4 OFF_BASE );\n}\n\n:lwe RT, OFF_BASER6 \tis $(AMODE) & prime=0x1F & fct=0x2F & bit6=0 & OFF_BASER6 & RT {\n RT = sext( *[ram]:4 OFF_BASER6 );\n}\n\n:lbx RD, INDEX_BASE\t\tis $(AMODE) & prime=0x1F & RD & fct=10 & fct2=22 & INDEX_BASE {\n RD = sext(*[ram]:1 INDEX_BASE);\n}\n\n\n:lhux RD, INDEX_BASE\t\tis $(AMODE) & prime=0x1F & RD & fct=10 & fct2=20 & INDEX_BASE {\n RD = zext(*[ram]:2 INDEX_BASE);\n}\n\n@ifdef MIPS64\n:lwux RD, INDEX_BASE\t\tis $(AMODE) & prime=0x1F & RD & fct=10 & fct2=16 & INDEX_BASE {\n RD = zext(*[ram]:4 INDEX_BASE);\n}\n@endif\n\n# 0100 0000 000t tttt dddd d000 0000 0sss\n:mfc0 RT, RD0 is $(AMODE) & prime=0x10 & copop=0 & RT & RD0 & zero6=0 {\n RT = sext( RD0:$(SIZETO4) );\n}\n\n# 0100 1000 000t tttt iiii iiii iiii iiii\n:mfc2 RT, immed is $(AMODE) & prime=0x12 & copop=0 & RT & immed {\n tmp:$(REGSIZE) = getCopReg(2:1, immed:4);\n RT = sext( tmp );\n}\n\n# 0100 1000 011t tttt iiii iiii iiii iiii\n:mfhc2 RT, immed is $(AMODE) & prime=0x12 & copop=3 & RT & fs & immed {\n tmp:$(REGSIZE) = getCopReg(2:1, immed:4);\n RT = sext(tmp >> 32);\n}\n\n# Special case of ADDIU\n# 0010 0100 000t tttt iiii iiii iiii iiii\n:li RT, simmed is $(AMODE) & prime=9 & rs=0 & RT & simmed {\n RT = simmed;\n}\n# Special case of ADDU\n# 0000 0000 000t tttt dddd d000 0010 0001\n:move RD, RTsrc is $(AMODE) & prime=0 & fct=0x21 & rs=0 & RD & RTsrc & sa=0 {\n RD = RTsrc;\n}\n# Special case of ADDU\n# 0000 00ss sss0 0000 dddd d000 0010 0001\n:move RD, RSsrc is $(AMODE) & prime=0 & fct=0x21 & RSsrc & rt=0 & RD & sa=0 {\n RD = RSsrc; \n}\n\n# 0100 0000 100t tttt dddd d000 0000 0sss\n:mtc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=4 & RTsrc & RD0 & zero6=0 & sel {\n\tsetCopReg(0:1, RD0, RTsrc, sel:1); \n}\n# 0100 1000 100t tttt iiii iiii iiii iiii\n:mtc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=4 & RTsrc & immed {\n setCopReg(2:1, immed:4, RTsrc);\n}\n\n:mthc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=6 & RTsrc & RD0 & zero6=0 & sel {\n\tsetCopReg(0:1, RD0, RTsrc, sel:1); \n}\n\n# 0100 1000 111t tttt iiii iiii iiii iiii\n:mthc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=0x07 & RTsrc & immed {\n arg:4 = immed;\n tmp:4 = RTsrc:$(SIZETO4);\n low:4 = getCopReg(2:1, arg);\n val:8 = (zext(tmp) << 32) + zext(low);\n setCopReg(2:1, arg, val);\n}\n\n:nal \t\t\t\tis $(AMODE) & REL6=0 & prime=1 & cond=0x10 & zero21=0 {\n\tdelayslot(1);\n\tra = inst_next;\n} \n\n# 0000 0000 0000 0000 0000 0000 0000 0000 \n:nop is $(AMODE) & prime=0 & rs=0 & rt=0 & rd=0 & sa=0 & fct=0 {\n}\n\n# 0000 00ss ssst tttt dddd d000 0010 0111\n:nor RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x27 & RSsrc & RTsrc & RD & sa=0 {\n RD = ~(RSsrc | RTsrc); \n}\n# 0000 00ss ssst tttt dddd d000 0010 0101\n:or RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x25 & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc | RTsrc; \n}\n# 0011 01ss ssst tttt iiii iiii iiii iiii\n:ori RT, RSsrc, immed is $(AMODE) & prime=0xD & RSsrc & RT & immed {\n RT = RSsrc | immed; \n}\n\n:pause\t\t\t\t\t\t\tis $(AMODE) & prime=0 & szero=0 & fct=0 & fct2=0x05 {\n\twait();\n}\n\n:pref hint, OFF_BASE is $(AMODE) & prime=0x33 & hint & OFF_BASE {\n prefetch(OFF_BASE, hint:1); \n}\n\n:prefe hint, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x23 & bit6=0 & OFF_BASER6 & hint {\n prefetch(OFF_BASER6, hint:1); \n} \n\n# 0111 1100 000t tttt dddd d000 0011 1011\n:rdhwr RT, rd_hw is $(AMODE) & prime=0x1F & rs=0 & fct2=0 & fct=0x3B & RT & rd_hw & rd!=4 {\n RT = getHWRegister(rd_hw);\n}\n\n# 0111 1100 000t tttt dddd d000 0011 1011\n:rdhwr RT, rd_hw, sel_0608 is $(AMODE) & REL6=1 & prime=0x1F & rs=0 & spec2=0 & fct=0x3B & RT & rd_hw & rd=4 & sel_0608 {\n RT = getHWRegister(rd_hw, sel_0608:1);\n}\n\n# 0100 0001 010t tttt dddd d000 0000 0000 \n:rdpgpr RD, RT is $(AMODE) & prime=0x10 & rs=10 & bigfunct=0 & RD & RT {\n RD = getShadow(RT);\n}\n\n# 0000 0000 001t tttt dddd daaa aa00 0010\n:rotr RD32, RT32src, sa is $(AMODE) & prime=0 & zero1=0 & bit21=1 & fct=2 & RD32 & RT32src & sa & RD {\n tmp1:4 = RT32src >> sa;\n tmp2:4 = RT32src << (32 - sa);\n RD32 = tmp1 + tmp2;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 00ss ssst tttt dddd d000 0100 0110\n:rotrv RD32, RT32src, RS32src is $(AMODE) & prime=0 & zero2=0 & bit6=1 & fct=6 & RD32 & RT32src & RS32src & RD {\n shift:4 = RS32src & 0x1f;\n tmp1:4 = RT32src >> shift;\n tmp2:4 = RT32src << (32 - shift);\n RD32 = tmp1 + tmp2;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n\n# 1010 00bb bbbt tttt iiii iiii iiii iiii\n:sb RTsrc, OFF_BASE is $(AMODE) & prime=0x28 & OFF_BASE & RTsrc {\n *[ram]:1 OFF_BASE = RTsrc:1;\n}\n\n:sbe RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1C & bit6=0 & OFF_BASER6 & RTsrc {\n *[ram]:1 OFF_BASER6 = RTsrc:1;\n}\n\n:sce RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1E & bit6=0 & OFF_BASER6 & RTsrc {\n *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4);\n RTsrc = 1;\n}\n\n# 0111 00cc cccc cccc cccc cccc cc11 1111\n:sdbbp breakcode is $(AMODE) & prime=0x1C & fct=0x3F & breakcode {\n signalDebugBreakpointException();\n}\n\n@ifndef COPR_C\n# 1111 10bb bbbt tttt iiii iiii iiii iiii \n:sdc2 RTsrc, OFF_BASE is $(AMODE) & prime=0x3E & OFF_BASE & RTsrc {\n *[ram]:8 OFF_BASE = getCopReg(2:1, RTsrc);\n}\n@endif\n\n# 0111 1100 000t tttt dddd d100 0010 0000\n:seb RD, RTsrc is $(AMODE) & prime=0x1F & rs=0 & fct2=0x10 & fct=0x20 & RD & RTsrc {\n RD = sext( RTsrc:1 );\n}\n# 0111 1100 000t tttt dddd d110 0010 0000\n:seh RD, RTsrc is $(AMODE) & prime=0x1F & rs=0 & fct2=0x18 & fct=0x20 & RD & RTsrc {\n RD = sext( RTsrc:2 ); \n}\n# 1010 01bb bbbt tttt iiii iiii iiii iiii\n:sh RTsrc, OFF_BASE is $(AMODE) & prime=0x29 & OFF_BASE & RTsrc {\n *[ram]:2 OFF_BASE = RTsrc:2; \n}\n\n:she RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1D & bit6=0 & OFF_BASER6 & RTsrc {\n *[ram]:2 OFF_BASER6 = RTsrc:2; \n}\n\n# 0000 0000 000t tttt dddd daaa aa00 0000\n:sll RD32, RT32src, sa is $(AMODE) & prime=0 & fct=0 & rs=0 & RD32 & RT32src & sa & RD {\n RD32 = RT32src << sa;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 00ss ssst tttt dddd d000 0000 0100\n:sllv RD32, RT32src, RS32src is $(AMODE) & prime=0 & fct=4 & RS32src & RT32src & RD32 & sa=0 & RD {\n shift:4 = RS32src & 0x1f;\n RD32 = RT32src << shift;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 00ss ssst tttt dddd d000 0010 1010\n:slt RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2A & RSsrc & RTsrc & RD & sa=0 {\n RD = zext( RSsrc s< RTsrc ); \n}\n# 0010 10ss ssst tttt iiii iiii iiii iiii\n:slti RT, RSsrc, simmed is $(AMODE) & prime=10 & RSsrc & RT & simmed {\n RT = zext( RSsrc s< simmed ); \n}\n# 0010 11ss ssst tttt iiii iiii iiii iiii\n:sltiu RT, RSsrc, simmed is $(AMODE) & prime=0xB & RSsrc & RT & simmed {\n RT = zext( RSsrc < simmed ); \n}\n# 0000 00ss ssst tttt dddd d000 0010 1011\n:sltu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2B & RSsrc & RTsrc & RD & sa=0 {\n RD = zext( RSsrc < RTsrc ); \n}\n\n# 0000 0000 000t tttt dddd daaa aa00 0011\n:sra RD32, RT32src, sa is $(AMODE) & prime=0 & fct=3 & rs=0 & RT32src & RD32 & sa & RD {\n RD32 = RT32src s>> sa;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 00ss ssst tttt dddd d000 0000 0111\n:srav RD32, RT32src, RS32src is $(AMODE) & prime=0 & fct=7 & RS32src & RT32src & RD32 & sa=0 & RD {\n shift:4 = RS32src & 0x1f;\n RD32 = RT32src s>> shift;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 0000 000t tttt dddd daaa aa00 0010\n:srl RD32, RT32src, sa is $(AMODE) & prime=0 & fct=2 & rs=0 & RT32src & RD32 & sa & RD {\n RD32 = RT32src >> sa; \n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 00ss ssst tttt dddd d000 0000 0110\n:srlv RD32, RT32src, RS32src is $(AMODE) & prime=0 & fct=6 & RS32src & RT32src & RD32 & sa=0 & RD {\n shift:4 = RS32src & 0x1f;\n RD32 = RT32src >> shift; \n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n\n# 0000 0000 0000 0000 0000 0000 0100 0000\n:ssnop is $(AMODE) & prime=0 & rs=0 & rt=0 & rd=0 & sa=1 & fct=0 {\n}\n\n# 0000 00ss ssst tttt dddd d000 0010 0010 \n:sub RD32, RS32src, RT32src is $(AMODE) & prime=0 & fct=0x22 & RS32src & RT32src & RD32 & sa=0 & RD {\n RD32 = RS32src - RT32src; \n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n# 0000 00ss ssst tttt dddd d000 0010 0011\n:subu RD32, RS32src, RT32src is $(AMODE) & prime=0 & fct=0x23 & RS32src & RT32src & RD32 & sa=0 & RD {\n RD32 = RS32src - RT32src;\n@ifdef MIPS64\n RD = sext(RD32);\n@endif\n}\n\n# 1010 11bb bbbt tttt iiii iiii iiii iiii\n:sw RTsrc, OFF_BASE is $(AMODE) & prime=0x2B & OFF_BASE & RTsrc {\n *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4); \n}\n\n@ifndef COPR_C\n# 1110 10bb bbbt tttt iiii iiii iiii iiii\n:swc2 hint, OFF_BASE is $(AMODE) & prime=0x3A & OFF_BASE & hint {\n\ttmp:4 = getCopReg(2:1, hint:4);\n *[ram]:4 OFF_BASE = tmp; \n}\n@endif\n\n:swe RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1F & bit6=0 & OFF_BASER6 & RTsrc {\n *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4); \n}\n\ndefine pcodeop SYNC;\n\n# 0000 0000 0000 0000 0000 0yyy yy00 1111\n:sync scalar is $(AMODE) & prime=0 & fct=0xF & szero=0 & stype [ scalar = stype + 0; ] {\n SYNC(scalar:1);\n}\n\n# 0000 01bb bbb1 1111 iiii iiii iiii iiii\n:synci OFF_BASE is $(AMODE) & prime=1 & OFF_BASE & synci=0x1F {\n}\n\n# 0000 00cc cccc cccc cccc cccc cc00 1100\n:syscall is $(AMODE) & prime=0 & fct=0xC & breakcode {\n tmp:4=breakcode; \n syscall(tmp); \n}\n\n# 0000 0000 0000 0000 cccc cccc cc11 0100\n# trap always\n:teq RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x34 & RSsrc & RTsrc & code & rs=0 & rt=0 {\n\ttmp:2 = code;\n local dest:$(ADDRSIZE) = trap(tmp);\n goto [dest];\n}\n\n# 0000 00ss ssst tttt cccc cccc cc11 0100\n:teq RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x34 & RSsrc & RTsrc & code {\n if (RSsrc != RTsrc) goto ; \n tmp:2=code; \n trap(tmp);\n \n}\n\n# 0000 00ss ssst tttt cccc cccc cc11 0000\n:tge RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x30 & RSsrc & RTsrc & code {\n if (RSsrc < RTsrc) goto ; \n tmp:2=code; \n trap(tmp);\n \n}\n# 0000 00ss ssst tttt cccc cccc cc11 0001\n:tgeu RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x31 & RSsrc & RTsrc & code {\n if (RSsrc < RTsrc) goto ; \n tmp:2=code; \n trap(tmp);\n \n}\n\n:tlbinv\t\tis $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x03 {\n TLB_invalidate(Index, EntryHi);\n}\n\n:tlbinvf\tis $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x04 {\n TLB_invalidate_flush(Index);\n}\n\n:tlbp\t\tis $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x08 {\n Index = TLB_probe_for_matching_entry(EntryHi);\n}\n\n:tlbr is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x01 {\n EntryHi = TLB_read_indexed_entryHi(Index);\n EntryLo0 = TLB_read_indexed_entryLo0(Index);\n EntryLo1 = TLB_read_indexed_entryLo1(Index);\n PageMask = TLB_read_indexed_entryPageMask(Index);\n}\n\n:tlbwi\t\tis $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x02 {\n TLB_write_indexed_entry(Index, EntryHi, EntryLo0, EntryLo1, PageMask);\n}\n\n:tlbwr is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x06 {\n TLB_write_random_entry(Random, EntryHi, EntryLo0, EntryLo1, PageMask);\n}\n\n# 0000 00ss ssst tttt cccc cccc cc11 0010\n:tlt RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x32 & RSsrc & RTsrc & code {\n if (RSsrc s>= RTsrc) goto ; \n tmp:2=code; \n trap(tmp);\n \n}\n# 0000 00ss ssst tttt cccc cccc cc11 0011\n:tltu RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x33 & RSsrc & RTsrc & code {\n if (RSsrc >= RTsrc) goto ; \n tmp:2=code; \n trap(tmp);\n \n}\n# 0000 00ss ssst tttt cccc cccc cc11 0110\n:tne RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x36 & RSsrc & RTsrc & code {\n if (RSsrc == RTsrc) goto ; \n tmp:2=code; \n trap(tmp);\n \n}\n\n# 0100 001c cccc cccc cccc cccc cc10 0000\n:wait is $(AMODE) & prime=0x10 & fct=0x20 & copfill & bit25=1 {\n tmp:4 = copfill; \n wait(tmp); \n}\n\n# 0100 0001 110t tttt dddd d000 0000 0000\n:wrpgpr RD, RTsrc is $(AMODE) & prime=0x10 & format=0xE & RTsrc & RD & bigfunct=0 {\n setShadow(RD, RTsrc);\n}\n\n# 0111 1100 000t tttt dddd d000 1010 0000\n:wsbh RD, RTsrc is $(AMODE) & prime=0x1F & format=0 & RTsrc & RD & wsbh=2 & bshfl=0x20 {\n tmp1:$(REGSIZE) = RTsrc & 0xff; \n tmp2:$(REGSIZE) = (RTsrc >> 8) & 0xff;\n tmp3:$(REGSIZE) = (RTsrc >> 16) & 0xff; \n tmp4:$(REGSIZE) = (RTsrc >> 24) & 0xff;\n RD = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | (tmp2); \n}\n\n# 0000 00ss ssst tttt dddd d000 0010 0110\n:xor RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x26 & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc ^ RTsrc; \n}\n# 0011 10ss ssst tttt iiii iiii iiii iiii \n:xori RT, RSsrc, immed is $(AMODE) & prime=0xE & RSsrc & RT & immed {\n RT = RSsrc ^ immed; \n}\n\n############################\n#\n# MIPS64 Instructions to be included with all MIPS32 processors\n#\n############################\n\n## Allow MIPS 64 instructions below for compilers\n## using a 64-bit chip, but really keeping things to 32-bits\n\n# Special case of daddu\n# 0000 00ss ssst tttt dddd d000 0010 1101\n:clear RD is $(AMODE) & prime=0 & fct=0x2D & rs=0 & rt=0 & RD & sa=0 {\n RD = 0; \n}\n\n# 0000 00ss ssst tttt dddd d000 0010 1100\n:dadd RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2C & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc + RTsrc; \n}\n# 0110 01ss ssst tttt iiii iiii iiii iiii\n:daddiu RT, RSsrc, simmed is $(AMODE) & prime=0x19 & RSsrc & RT & simmed {\n RT = RSsrc + simmed; \n}\n# 0000 00ss ssst tttt dddd d000 0010 1101\n:daddu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2D & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc + RTsrc; \n}\n\n####\n#\n# Pre-6 semantics\n#\n####\n# 0010 00ss ssst tttt iiii iiii iiii iiii\n:addi RT32, RS32src, simmed is $(AMODE) & REL6=0 & prime=8 & RT32 & RS32src & simmed & RT {\n RT32 = RS32src + simmed;\n@ifdef MIPS64\n RT = sext(RT32);\n@endif\n}\n\n# 0000 01ss sss1 0001 iiii iiii iiii iiii\n:bal Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x11 & rs=0 & Rel16 {\n ra = inst_next; \n delayslot( 1 ); \n call Rel16; \n}\n\n# Special case PIC\n:bal Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x11 & rs=0 & off16=1 & Rel16 {\n ra = inst_next; \n delayslot( 1 ); \n goto Rel16; \n}\n\n# 0100 1001 000c cc00 iiii iiii iiii iiii\n:bc2f Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=0 & tf=0 & Rel16 {\n tmp:1 = getCopCondition(2:1, 0:1); \n delayslot(1); \n if (tmp != 0) goto inst_next; \n goto Rel16; \n}\n:bc2f cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=0 & tf=0 & Rel16 {\n tmp:1 = getCopCondition(2:1, cc:1); \n delayslot(1); \n if (tmp != 0) goto inst_next; \n goto Rel16; \n}\n# 0100 1001 000c cc10 iiii iiii iiii iiii\n:bc2fl Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=1 & tf=0 & Rel16 {\n tmp:1 = getCopCondition(2:1, 0:1); \n if (tmp != 0) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n:bc2fl cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=1 & tf=0 & Rel16 {\n tmp:1 = getCopCondition(2:1, cc:1); \n if (tmp != 0) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n# 0100 1001 000c cc01 iiii iiii iiii iiii\n:bc2t Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=0 & tf=1 & Rel16 {\n tmp:1 = getCopCondition(2:1, 0:1); \n delayslot(1); \n if (tmp == 0) goto inst_next; \n goto Rel16; \n}\n:bc2t cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=0 & tf=1 & Rel16 {\n tmp:1 = getCopCondition(2:1, cc:1); \n delayslot(1); \n if (tmp == 0) goto inst_next; \n goto Rel16; \n}\n# 0100 1001 000c cc11 iiii iiii iiii iiii\n:bc2tl Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=1 & tf=1 & Rel16 {\n tmp:1 = getCopCondition(2:1, 0:1); \n if (tmp == 0) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n:bc2tl cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=1 & tf=1 & Rel16 {\n tmp:1 = getCopCondition(2:1, cc:1); \n if (tmp == 0) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n\n# 0101 00ss ssst tttt iiii iiii iiii iiii\n:beql RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x14 & RSsrc & RTsrc & Rel16 {\n if (!(RSsrc==RTsrc)) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n\n:bgezal RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x11 & RSsrc & Rel16 {\n ra = inst_next; \n delayflag:1 = ( RSsrc s>= 0 ); \n delayslot( 1 ); \n if (!delayflag) goto inst_next; \n call Rel16; \n}\n\n# 0000 01ss sss1 0011 iiii iiii iiii iiii\n:bgezall RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x13 & RSsrc & Rel16 {\n ra = inst_next; \n if (!(RSsrc s>= 0)) goto inst_next; \n delayslot( 1 ); \n call Rel16; \n}\n# 0000 01ss sss0 0011 iiii iiii iiii iiii \n:bgezl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=3 & RSsrc & Rel16 {\n if (!(RSsrc s>= 0)) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n# 0101 11ss sss0 0000 iiii iiii iiii iiii \n:bgtzl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x17 & cond=0 & RSsrc & Rel16 {\n if (!(RSsrc s> 0)) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n# 0101 10ss sss0 0000 iiii iiii iiii iiii \n:blezl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x16 & cond=0 & RSsrc & Rel16 {\n if (!(RSsrc s<= 0)) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n# 0000 01ss sss1 0000 iiii iiii iiii iiii\n:bltzal RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x10 & RSsrc & Rel16 {\n ra = inst_next; \n delayflag:1 = ( RSsrc s< 0 ); \n delayslot( 1 ); \n if (!delayflag) goto inst_next; \n call Rel16; \n}\n# 0000 01ss sss1 0010 iiii iiii iiii iiii\n:bltzall RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x12 & RSsrc & Rel16 {\n ra = inst_next; \n if (!(RSsrc s< 0)) goto inst_next; \n delayslot(1); \n call Rel16; \n}\n# 0000 01ss sss0 0010 iiii iiii iiii iiii \n:bltzl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=2 & RSsrc & Rel16 {\n if (!(RSsrc s< 0)) goto inst_next; \n delayslot(1);\n goto Rel16; \n}\n# 0101 01ss ssst tttt iiii iiii iiii iiii \n:bnel RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x15 & RSsrc & RTsrc & Rel16 {\n if (!(RSsrc!=RTsrc)) goto inst_next; \n delayslot(1); \n goto Rel16; \n}\n\n# 0111 00ss ssst tttt dddd d000 0010 0001\n:clo RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1C & sa=0x0 & fct=0x21 & RD & RSsrc {\n # Count leading ones in a word\n RD = lzcount( ~RSsrc );\n}\n\n# 0111 00ss ssst tttt dddd d000 0010 0000\n:clz RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1C & sa=0x0 & fct=0x20 & RD & RSsrc {\n # Count leading zeros in a word\n RD = lzcount( RSsrc );\n}\n\n# 0000 00ss ssst tttt 0000 0000 0001 1010\n:div RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x1A & RS32src & RT32src & rd=0 & sa=0 {\n lo = sext(RS32src s/ RT32src); \n hi = sext(RS32src s% RT32src); \n}\n# 0000 00ss ssst tttt 0000 0000 0001 1011\n:divu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x1B & RS32src & RT32src & rd=0 & sa=0 {\n lo = sext(RS32src / RT32src); \n hi = sext(RS32src % RT32src); \n}\n@ifdef ISA_VARIANT\n# 0111 01aa aaaa aaaa aaaa aaaa aaaa aaaa\n:jalx Abs26 is $(AMODE) & REL6=0 & prime=0x1D & Abs26 [ ISA_MODE = 1; globalset(Abs26, ISA_MODE);] {\n ra = inst_next; \n delayslot( 1 );\n ISAModeSwitch = 1;\n call Abs26; \n}\n@endif\n\n@ifndef COPR_C\n# 1101 10bb bbbt tttt iiii iiii iiii iiii\n:ldc2 rt, OFF_BASE is $(AMODE) & REL6=0 & prime=0x36 & OFF_BASE & rt {\n setCopReg(2:1, rt, *[ram]:8 OFF_BASE);\n}\n@endif\n\n# 1100 00bb bbbt tttt iiii iiii iiii iiii\n:ll RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x30 & OFF_BASE & RT {\n RT = sext(*[ram]:4 OFF_BASE);\n}\n\n# 0011 1100 000t tttt iiii iiii iiii iiii\n:lui RT, immed is $(AMODE) & REL6=0 & prime=0xF & rs=0 & RT & immed {\n tmp:4 = immed << 16;\n RT = sext(tmp); \n}\n\n@ifndef COPR_C\n# 1100 10bb bbbt tttt iiii iiii iiii iiii\n:lwc2 rt, OFF_BASE is $(AMODE) & REL6=0 & prime=0x32 & OFF_BASE & rt {\n setCopReg( 2:1, rt, *[ram]:4 OFF_BASE ); \n}\n@endif\n\n@if ENDIAN == \"big\"\n# 1000 10bb bbbt tttt iiii iiii iiii iiii\n:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & RTsrc {\n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8));\n valLoad:4 = *(addr) << (shft * 8); \n RT = sext( valLoad | valOrig ); \n}\n\n# 1001 10bb bbbt tttt iiii iiii iiii iiii\n:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & RTsrc {\n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((shft+1) * 8));\n valLoad:4 = *(addr) >> ((3-shft) * 8);\n RT = sext( valOrig | valLoad );\n}\n:lwle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x19 & bit6=0 & OFF_BASER6 & RTsrc & RT {\n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8));\n valLoad:4 = *(addr) << (shft * 8); \n RT = sext( valLoad | valOrig ); \n}\n\n:lwre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x1A & bit6=0 & OFF_BASER6 & RTsrc & RT {\n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((shft+1) * 8));\n valLoad:4 = *(addr) >> ((3-shft) * 8);\n RT = sext( valOrig | valLoad );\n}\n@else\n:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & RTsrc {\n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8));\n valLoad:4 = *(addr) << ((3-shft) * 8); \n RT = sext( valLoad | valOrig ); \n}\n\n# 1001 10bb bbbt tttt iiii iiii iiii iiii\n:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & RTsrc {\n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((4-shft)* 8));\n valLoad:4 = *(addr) >> (shft * 8);\n RT = sext( valOrig | valLoad );\n}\n:lwle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x19 & bit6=0 & OFF_BASER6 & RTsrc & RT {\n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8));\n valLoad:4 = *(addr) << ((3-shft) * 8); \n RT = sext( valLoad | valOrig ); \n}\n\n:lwre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x1A & bit6=0 & OFF_BASER6 & RTsrc & RT {\n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((4-shft)* 8));\n valLoad:4 = *(addr) >> (shft * 8);\n RT = sext( valOrig | valLoad );\n}\n@endif\n\n# lwl and lwr almost always come in pairs. \n# When the analyzer does finds a matching lwl/lwr pair, the pcode is simplified so that \n# lwl does all the loading while lwr is a no-op\n@if ENDIAN == \"big\"\n:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n RT = sext( *[ram]:4 OFF_BASE ); \n}\n:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n}\n@else\n:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n}\n:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n RT = sext( *[ram]:4 OFF_BASE ); \n}\n@endif\n\n# 0111 00ss ssst tttt 000a a000 0000 0000\n:madd RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x0 & RS32src & RT32src & ac=0 & achi & aclo {\n tmp1:8 = sext(RS32src);\n tmp2:8 = sext(RT32src);\n prod:8 = tmp1 * tmp2;\n aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n sum:8 = (zext(achi) << 32) + zext(aclo) + prod;\n aclo = sext(sum:4);\n sum = sum >> 32;\n achi = sext(sum:4);\n}\n\n# 0111 00ss ssst tttt 000a a000 0000 0001\n:maddu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x01 & RS32src & RT32src & ac=0 & achi & aclo {\n tmp1:8 = zext(RS32src);\n tmp2:8 = zext(RT32src);\n prod:8 = tmp1 * tmp2;\n aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n sum:8 = (zext(achi) << 32) + zext(aclo) + prod;\n aclo = sext(sum:4);\n sum = sum >> 32;\n achi = sext(sum:4);\n}\n\n# 0000 0000 0aa0 0000 dddd d000 0001 0000\n:mfhi RD is $(AMODE) & REL6=0 & prime=0 & fct=0x10 & RD & zero5=0 & zero1620=0 & zero2325=0 & acf=0 & acfhi {\n RD = acfhi;\n}\n\n# 0000 0000 0aa0 0000 dddd d000 0001 0010\n:mflo RD is $(AMODE) & REL6=0 & prime=0 & fct=0x12 & RD & zero5=0 & zero1620=0 & zero2325=0 & acf=0 & acflo {\n RD = acflo;\n}\n\n# 0000 00ss ssst tttt dddd d000 0000 1011\n:movn RD, RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & zero5=0 & fct=0xB & RD & RSsrc & RTsrc {\n if (RTsrc == 0) goto ; \n RD = RSsrc;\n \n}\n\n# 0000 00ss ssst tttt dddd d000 0000 1010\n:movz RD, RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & zero5=0 & fct=10 & RD & RSsrc & RTsrc {\n if (RTsrc != 0) goto ; # We can't use goto inst_next because it fails if we are in a delay slot\n RD = RSsrc;\n \n}\n\n\n# 0111 00ss ssst tttt 000a a000 0000 0100\n:msub RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & fct2=0 & fct=0x04 & RS32src & RT32src & zero1315=0 & aclo & achi {\n tmp1:8 = sext(RS32src);\n tmp2:8 = sext(RT32src);\n prod:8 = tmp1 * tmp2;\n aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n sum:8 = (zext(achi) << 32) + zext(aclo) - prod;\n aclo = sext(sum:4);\n sum = sum >> 32;\n achi = sext(sum:4);\n}\n\n# 0111 00ss ssst tttt 000a a000 0000 0101\n:msubu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & fct2=0 & fct=0x05 & RS32src & RT32src & zero1315=0 & ac=0 & aclo & achi {\n tmp1:8 = zext(RS32src);\n tmp2:8 = zext(RT32src);\n prod:8 = tmp1 * tmp2;\n aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n sum:8 = (zext(achi) << 32) + zext(aclo) - prod;\n aclo = sext(sum:4);\n sum = sum >> 32;\n achi = sext(sum:4);\n}\n\n# 0000 00ss sss0 0000 000a a000 0001 0001\n:mthi RSsrc is $(AMODE) & REL6=0 & prime=0 & fct=0x11 & RSsrc & zero5=0 & zero1320=0 & ac=0 & achi {\n achi = RSsrc;\n}\n\n# 0000 00ss sss0 0000 000a a000 0001 0011\n:mtlo RSsrc is $(AMODE) & REL6=0 & prime=0 & fct=0x13 & RSsrc & zero5=0 & zero1320=0 & ac=0 & aclo {\n aclo = RSsrc;\n}\n\n# 0111 00ss ssst tttt dddd d000 0000 0010\n:mul RD, RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & sa=0x0 & fct=0x02 & RD & RS32src & RT32src {\n tmp1:8 = sext( RS32src );\n tmp2:8 = sext( RT32src );\n prod:8 = tmp1 * tmp2;\n RD = sext( prod:4 );\n}\n\n# 0000 00ss ssst tttt 000a a000 0001 1000\n:mult RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x18 & RS32src & RT32src & zero5=0 & zero1315=0 & aclo & achi {\n tmp1:8 = sext( RS32src );\n tmp2:8 = sext( RT32src );\n prod:8 = tmp1 * tmp2;\n aclo = sext(prod:4);\n prod = prod >> 32;\n achi = sext(prod:4);\n}\n\n# 0000 00ss ssst tttt 000a a000 0001 1001\n:multu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x19 & RS32src & RT32src & zero5=0 & zero1315=0 & aclo & achi {\n tmp1:8 = zext( RS32src );\n tmp2:8 = zext( RT32src );\n prod:8 = tmp1 * tmp2;\n aclo = sext(prod:4);\n prod = prod >> 32;\n achi = sext(prod:4);\n}\n\n# 0100 0110 110t tttt ssss sddd dd10 1100\n:pll.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2C & ft & fs & fd\n unimpl\n\n# 0100 0110 110t tttt ssss sddd dd10 1101\n:plu.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2D & ft & fs & fd\n unimpl \n\n#:prefx\n\n# 0100 0110 110t tttt ssss sddd dd10 1110\n:pul.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2E & fd & fs & ft\n unimpl\n# 0100 0110 110t tttt ssss sddd dd10 1111\n:puu.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2F & fd & fs & ft\n unimpl\n\n# 1110 00bb bbbt tttt iiii iiii iiii iiii\n:sc RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x38 & OFF_BASE & RT & RTsrc {\n *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4);\n RT = 1;\n}\n\n@if ENDIAN == \"big\"\n# 1010 10bb bbbt tttt iiii iiii iiii iiii\n:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc {\n tmpRT:4 = RTsrc:$(SIZETO4); \n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = *(addr) & (0xffffffff << ((4-shft) * 8));\n valStore:4 = tmpRT >> (shft * 8);\n *(addr) = valOrig | valStore; \n}\n# 1011 10bb bbbt tttt iiii iiii iiii iiii\n:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc {\n tmpRT:4 = RTsrc:$(SIZETO4);\n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = *(addr) & (0xffffffff >> ((shft+1) * 8));\n valStore:4 = tmpRT << ((3-shft)*8);\n *(addr) = valOrig | valStore;\n}\n:swle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x21 & bit6=0 & OFF_BASER6 & RTsrc & RT {\n tmpRT:4 = RTsrc:$(SIZETO4); \n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = *(addr) & (0xffffffff << ((4-shft) * 8));\n valStore:4 = tmpRT >> (shft * 8);\n *(addr) = valOrig | valStore; \n}\n:swre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x22 & bit6=0 & OFF_BASER6 & RTsrc & RT {\n tmpRT:4 = RTsrc:$(SIZETO4);\n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = *(addr) & (0xffffffff >> ((shft+1) * 8));\n valStore:4 = tmpRT << ((3-shft)*8);\n *(addr) = valOrig | valStore;\n}\n\n@else\n# 1010 10bb bbbt tttt iiii iiii iiii iiii\n:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc {\n tmpRT:4 = RTsrc:$(SIZETO4); \n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = *(addr) & (0xffffffff << ((shft+1) * 8));\n valStore:4 = tmpRT >> ((3-shft) * 8);\n *(addr) = valOrig | valStore; \n}\n# 1011 10bb bbbt tttt iiii iiii iiii iiii\n:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc {\n tmpRT:4 = RTsrc:$(SIZETO4);\n shft:$(ADDRSIZE) = OFF_BASE & 0x3; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:4 = *(addr) & (0xffffffff >> ((4-shft) * 8));\n valStore:4 = tmpRT << (shft*8);\n *(addr) = valOrig | valStore;\n}\n:swle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x21 & bit6=0 & OFF_BASER6 & RTsrc & RT {\n tmpRT:4 = RTsrc:$(SIZETO4); \n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = *(addr) & (0xffffffff << ((shft+1) * 8));\n valStore:4 = tmpRT >> ((3-shft) * 8);\n *(addr) = valOrig | valStore; \n}\n:swre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x22 & bit6=0 & OFF_BASER6 & RTsrc & RT {\n tmpRT:4 = RTsrc:$(SIZETO4);\n shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; \n addr:$(ADDRSIZE) = OFF_BASER6 - shft; \n valOrig:4 = *(addr) & (0xffffffff >> ((4-shft) * 8));\n valStore:4 = tmpRT << (shft*8);\n *(addr) = valOrig | valStore;\n}\n\n@endif\n\n# When the analyzer finds a matching swl/swr pair, the pcode is simplified so that \n# swl does all the storing while swr is a no-op\n@if ENDIAN == \"big\"\n:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4);\n}\n:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ]{\n}\n@else\n:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n}\n:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ]{\n *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4);\n}\n@endif\n\n# 0000 01ss sss0 1100 iiii iiii iiii iiii\n:teqi RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=0xC & RSsrc & simmed {\n if (RSsrc != simmed) goto ; \n trap();\n \n}\n# 0000 01ss sss0 1000 iiii iiii iiii iiii\n:tgei RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=8 & RSsrc & simmed {\n if (RSsrc s< simmed) goto ; \n trap();\n \n}\n# 0000 01ss sss0 1001 iiii iiii iiii iiii\n:tgeiu RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=9 & RSsrc & simmed {\n if (RSsrc < simmed) goto ; \n trap();\n \n}\n# 0000 01ss sss0 1010 iiii iiii iiii iiii\n:tlti RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=10 & RSsrc & simmed {\n if (RSsrc s>= simmed) goto ; \n trap();\n \n}\n# 0000 01ss sss0 1011 iiii iiii iiii iiii\n:tltiu RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=0xB & RSsrc & simmed {\n if (RSsrc >= simmed) goto ; \n trap();\n \n}\n# 0000 01ss sss0 1110 iiii iiii iiii iiii\n:tnei RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=0xE & RSsrc & simmed {\n if (RSsrc == simmed) goto ; \n trap();\n \n}\n\n############################\n#\n# MIPS64 Instructions to be included with all MIPS32 processors\n#\n############################\n\n## Allow MIPS 64 instructions below for compilers\n## using a 64-bit chip, but really keeping things to 32-bits\n# 0110 00ss ssst tttt iiii iiii iiii iiii\n:daddi RT, RSsrc, simmed is $(AMODE) & REL6=0 & prime=0x18 & RSsrc & RT & simmed {\n RT = RSsrc + simmed; \n}\n\n####\n#\n# Release 6 semantics\n#\n####\n\n:addiupc RSsrc, S19L2\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3B & bitz19=0 & RSsrc & S19L2 {\n\tRSsrc = inst_start + sext(S19L2);\n}\n\n:align RD, RS32src, RT32src, bp2 \tis $(AMODE) & REL6=1 & prime=0x1F & spec3=0x2 & fct=0x20 & bp2 & RS32src & RT32src & RD {\n\ttmp:4 = RT32src << (8 * bp2);\n\ttmp = tmp | (RS32src >> (32 - (8 * bp2)));\n\tRD = sext(tmp);\n}\n\n:aluipc RSsrc, S16L16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3B & op=0x1F & RSsrc & S16L16 {\n\tRSsrc = inst_start + sext(S16L16);\n\tRSsrc = RSsrc & ~0xFFFF;\n}\n\n:aui RTsrc, RSsrc, S16L16\t\t\tis $(AMODE) & REL6=1 & prime=0x0F & RSsrc & RTsrc & S16L16 {\n\tRTsrc = RSsrc + sext(S16L16);\n}\n\n:auipc RSsrc, S16L16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3B & op=0x1E & RSsrc & S16L16 {\n\tRSsrc = inst_start + sext(S16L16);\n}\n\n# 0000 0100 0001 0001 iiii iiii iiii iiii\n:bal Rel16 \t\t\tis $(AMODE) & REL6=1 & prime=0x01 & cond=0x11 & rs=0 & Rel16 {\n ra = inst_next; \n delayslot(1); \n call Rel16; \n}\n\n:bal Rel16 \t\t\tis $(AMODE) & REL6=1 & prime=0x01 & cond=0x11 & rs=0 & off16=1 & Rel16 {\n ra = inst_next; \n delayslot(1); \n goto Rel16; \n}\n\n:balc Rel26\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3A & Rel26 {\n ra = inst_next; \n call Rel26; \n} \n\n:bc Rel26\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x32 & Rel26 {\n\tgoto Rel26;\n}\n\n:bc2eqz op, Rel16\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x12 & copop=0x09 & op & Rel16 {\n tmp:1 = getCopCondition(2:1, op:1); \n if (tmp == 0) goto inst_next; \n goto Rel16; \n}\n\n:bc2nez op, Rel16\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x12 & copop=0x0D & op & Rel16 {\n tmp:1 = getCopCondition(2:1, op:1); \n if (tmp != 0) goto inst_next; \n goto Rel16; \n}\n\n:bad1\t\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x06 & rs=0 & rt=0 unimpl\n:blezalc RTsrc, Rel16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x06 & rs=0 & RTsrc & Rel16 {\n\tif (RTsrc s> 0) goto inst_next;\n ra = inst_next; \n\tcall Rel16;\n}\n\n:bgezalc RTsrc, Rel16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x06 & rs=rt & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s< 0) goto inst_next;\n ra = inst_next; \n\tcall Rel16;\n}\t\n\n:bgeuc RSsrc, RTsrc, Rel16\t\t\tis $(AMODE) & REL6=1 & prime=0x06 & rt!=0 & rs!=rt & RSsrc & RTsrc & Rel16 {\n\tif (RSsrc >= RTsrc) goto Rel16;\n}\n\n:bad2\t\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x07 & rs=0 & rt=0 unimpl\n:bgtzalc RTsrc, Rel16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x07 & rs=0 & RTsrc & Rel16 {\n\tif (RTsrc s<= 0) goto inst_next;\n ra = inst_next; \n\tcall Rel16;\n}\n\n:bltzalc RTsrc, Rel16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x07 & rs=rt & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s>= 0) goto inst_next;\n ra = inst_next; \n\tcall Rel16;\n}\t\n\n:bltuc RSsrc, RTsrc, Rel16\t\t\tis $(AMODE) & REL6=1 & prime=0x07 & rt!=0 & rs!=rt & RSsrc & RTsrc & Rel16 {\n\tif (RSsrc < RTsrc) goto Rel16;\n}\n\n\n:beqzalc RTsrc, Rel16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x08 & rs=0 & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s> 0) goto inst_next;\n ra = inst_next; \n\tcall Rel16;\n}\n\n:beqc RSsrc, RTsrc, Rel16\t\t\tis $(AMODE) & REL6=1 & prime=0x08 & rs!=0 & rs 0x7FFFFFFF) || (tmpS s< -2147483648);\n@if REGSIZE == \"8\"\n\ttmpF = tmpF || (RTsrc s> 0x7FFFFFFF) || (RTsrc s< -2147483648) || (RSsrc s> 0x7FFFFFFF) || (RSsrc s< -2147483648);\n@endif\n\tif (tmpF == 1) goto Rel16;\n}\n\n:bnezalc RTsrc, Rel16\t\t\t\tis $(AMODE) & REL6=1 & prime=0x18 & rs=0 & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc == 0) goto inst_next;\n ra = inst_next; \n\tcall Rel16;\n}\n\n:bnec RSsrc, RTsrc, Rel16\t\t\tis $(AMODE) & REL6=1 & prime=0x18 & rs!=0 & rs 0x7FFFFFFF) || (tmpS s< -2147483648);\n@if REGSIZE == \"8\"\n\ttmpF = tmpF || (RTsrc s> 0x7FFFFFFF) || (RTsrc s< -2147483648) || (RSsrc s> 0x7FFFFFFF) || (RSsrc s< -2147483648);\n@endif\n\tif (tmpF == 0) goto Rel16;\n}\n\n:bad3\t\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x16 & rs=0 & rt=0 unimpl\n:blezc RTsrc, Rel16\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x16 & rs=0 & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s<= 0) goto Rel16;\n}\n:bgezc RTsrc, Rel16\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x16 & rs=rt & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s>= 0) goto Rel16;\n}\n:bgec RSsrc, RTsrc, Rel16\t\t\tis $(AMODE) & REL6=1 & prime=0x16 & RSsrc & RTsrc & Rel16 {\n\tif (RSsrc s>= RTsrc) goto Rel16;\n}\n\n\n:bad4\t\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x17 & rs=0 & rt=0 unimpl\n:bgtzc RTsrc, Rel16\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x17 & rs=0 & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s> 0) goto Rel16;\n}\n\n:bltzc RTsrc, Rel16\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x17 & rs=rt & rt!=0 & RTsrc & Rel16 {\n\tif (RTsrc s< 0) goto Rel16;\n}\n\n:bltc RSsrc, RTsrc, Rel16\t\t\tis $(AMODE) & REL6=1 & prime=0x17 & RSsrc & RTsrc & Rel16 {\n\tif (RSsrc s< RTsrc) goto Rel16;\n}\n\n# The jic instruction takes care of the 'bad' case here\n:beqzc RSsrc, Rel21\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x36 & RSsrc & Rel21 {\n\tif (RSsrc == 0) goto Rel21;\n}\n\n# The jialc instruction takes care of the 'bad' case here\n:bnezc RSsrc, Rel21\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3E & RSsrc & Rel21 {\n\tif (RSsrc != 0) goto Rel21;\n}\n\n:bitswap RD, RT32src\t\t\t\tis $(AMODE) & REL6=1 & prime=0x1F & zero21=0 & fct2=0 & bshfl=0x20 & RT32src & RD {\n\ttmp:4 = bitSwap(RT32src);\n\tRD = sext(tmp);\n}\n\n:clo RD, RSsrc \tis $(AMODE) & REL6=1 & prime=0x00 & op=0 & sa=0x1 & fct=0x11 & RD & RSsrc {\n RD = lzcount( ~RSsrc );\n}\n\n:clz RD, RSsrc \tis $(AMODE) & REL6=1 & prime=0x00 & op=0 & sa=0x1 & fct=0x10 & RD & RSsrc {\n RD = lzcount( RSsrc );\n}\n\n:div RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1A & fct2=0x02 & RD & RS32src & RT32src {\n\ttmp:4 = RS32src s/ RT32src;\n\tRD = sext(tmp);\n}\n\n:mod RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1A & fct2=0x03 & RD & RS32src & RT32src {\n\ttmp:4 = RS32src s% RT32src;\n\tRD = sext(tmp);\n}\n\n:divu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1B & fct2=0x02 & RD & RS32src & RT32src {\n\ttmp:4 = RS32src / RT32src;\n\tRD = sext(tmp);\n}\n\n:modu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1B & fct2=0x03 & RD & RS32src & RT32src {\n\ttmp:4 = RS32src % RT32src;\n\tRD = sext(tmp);\n}\n\n:dvp RT \t\t\tis $(AMODE) & REL6=1 & prime=0x10 & mfmc0=0x0B & fct=0x24 & RT & RD0 & zero5=0 & zero4=0 {\n\tdisableProcessor(RT);\n}\n\n:evp RT \t\t\tis $(AMODE) & REL6=1 & prime=0x10 & mfmc0=0x0B & fct=0x04 & RT & RD0 & zero5=0 & zero4=0 {\n\tenableProcessor(RT);\n}\n\n# NOTE: Unlike almost every other branch/jump that has an immediate, the immediate is *IS NOT* shifted. This allows\n# this instruction to serve same function as jalx in pre-6.\n:jialc RTsrc, simmed\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3E & jsub=0x00 & RTsrc & simmed {\n\tbuild RTsrc;\n\ttmp:$(REGSIZE) = sext(simmed:2) + RTsrc;\t\n\tJXWritePC(tmp); \n ra = inst_next; \n call [pc];\n}\n\n:jic RTsrc, simmed\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed {\n\tbuild RTsrc;\n\ttmp:$(REGSIZE) = sext(simmed:2) + RTsrc;\t\n\tJXWritePC(tmp); \n goto [pc];\n}\n\n:jic RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed & immed=0x00 & rt=0x1f {\n build RTsrc;\n JXWritePC(ra);\n\treturn [pc];\n}\n\n@ifndef COPR_C\n:ldc2 RTsrc, simmed11(baser6) is $(AMODE) & REL6=1 & prime=0x12 & copop=0x0E & simmed11 & baser6 & RTsrc {\n\ttmp:$(REGSIZE) = simmed11;\n\ttmp = tmp + baser6;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n setCopReg(2:1, RTsrc, *[ram]:8 tmpa);\n}\n@endif\n\n:ll RT, OFF_BASER6 \tis $(AMODE) & REL6=1 & prime=0x1F & fct=0x36 & bit6=0 & OFF_BASER6 & RT {\n RT = sext(*[ram]:4 OFF_BASER6);\n}\n\n:llx RT, OFF_BASER6 \tis $(AMODE) & REL6=1 & prime=0x1F & fct=0x36 & bit6=1 & OFF_BASER6 & RT {\n RT = sext(*[ram]:4 OFF_BASER6);\n}\n\n:llxe RT, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x27 & bit6=1 & OFF_BASER6 & RT {\n RT = sext(*[ram]:4 OFF_BASER6);\n}\n\n:lsa RD, RS32src, RT32src, SAV\t\tis $(AMODE) & REL6=1 & prime=0x00 & fct=0x05 & spec3=0 & SAV & RD & RS32src & RT32src {\n\ttmp:4 = (RS32src << SAV) + RT32src;\n\tRD = sext(tmp);\n}\n\n@ifndef COPR_C\n:lwc2 RTsrc, simmed11(baser6) is $(AMODE) & REL6=1 & prime=0x12 & copop=0x0A & simmed11 & baser6 & RTsrc {\n\ttmp:$(REGSIZE) = simmed11;\n\ttmp = tmp + baser6;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n setCopReg( 2:1, RTsrc, *[ram]:4 tmpa); \n}\n@endif\n\n:lwpc RS, S19L2\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3B & pcrel=0x1 & RS & S19L2 {\n\ttmp:$(REGSIZE) = inst_start + sext(S19L2);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tRS = sext(*[ram]:4 tmpa);\n}\n\n:mul RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x18 & fct2=0x02 & RD & RS32src & RT32src {\n\ttmpS:8 = sext(RS32src);\n\ttmpT:8 = sext(RT32src);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[0,32];\n\tRD = sext(tmp);\n}\n\n:muh RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x18 & fct2=0x03 & RD & RS32src & RT32src {\n\ttmpS:8 = sext(RS32src);\n\ttmpT:8 = sext(RT32src);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[32,32];\n\tRD = sext(tmp);\n}\n\n:mulu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x19 & fct2=0x02 & RD & RS32src & RT32src {\n\ttmpS:8 = zext(RS32src);\n\ttmpT:8 = zext(RT32src);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[0,32];\n\tRD = sext(tmp);\n}\n\n:muhu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x19 & fct2=0x03 & RD & RS32src & RT32src {\n\ttmpS:8 = zext(RS32src);\n\ttmpT:8 = zext(RT32src);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[32,32];\n\tRD = sext(tmp);\n}\n\n:scx RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x26 & bit6=1 & OFF_BASER6 & RTsrc {\n *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4);\n}\n\n:scxe RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x1E & bit6=1 & OFF_BASER6 & RTsrc {\n *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4);\n RTsrc = 1;\n}\n\n:seleqz RD, RSsrc, RTsrc \tis $(AMODE) & REL6=1 & prime=0x00 & fct=0x35 & fct2=0x00 & RD & RSsrc & RTsrc {\n\t# We use tmp to cover case where rs and rd are the same reg\n\ttmps:$(REGSIZE) = RSsrc;\n\ttmpt:$(REGSIZE) = RTsrc;\n\tRD = 0;\n\tif (tmpt != 0) goto ;\n\tRD = tmps;\n\t\n}\n\n:selnez RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x37 & fct2=0x00 & RD & RSsrc & RTsrc {\n\t# We use tmp to cover case where rs and rd are the same reg\n\ttmps:$(REGSIZE) = RSsrc;\n\ttmpt:$(REGSIZE) = RTsrc;\n\tRD = 0;\n\tif (tmpt == 0) goto ;\n\tRD = tmps;\n\t\n}\n\n:sigrie immed\t\t\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x01 & zero21=0 & cond=0x17 & immed {\n\tsignalReservedInstruction(immed:2);\n}\n\n\n@include \"mipsfloat.sinc\"\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32R6.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32R6be.slaspec", "content": "# SLA specification file for MIPS32 big endian\n\n@define ENDIAN \"big\"\n@define FREGSIZE \"8\"\n@define ISA_VARIANT \"\"\n\n@include \"mips.sinc\"\n@include \"mips32Instructions.sinc\"\n@include \"mips16.sinc\"\n@include \"mipsmicro.sinc\"\n@include \"mips_dsp.sinc\"\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32R6le.slaspec", "content": "# SLA specification file for MIPS32 little endian\n\n@define ENDIAN \"little\"\n@define FREGSIZE \"8\"\n@define ISA_VARIANT \"\"\n\n@include \"mips.sinc\"\n@include \"mips32Instructions.sinc\"\n@include \"mips16.sinc\"\n@include \"mipsmicro.sinc\"\n@include \"mips_dsp.sinc\"" }, { "path": "pypcode/processors/MIPS/data/languages/mips32_eabi.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32_fp64.cspec", "content": "\n\n\n \n \n \n \n \n \n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32be.cspec", "content": "\n\n\n \n \n \n \n \n \n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\t\t\n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \t\t\t\t\n \n \n \n \t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32be.slaspec", "content": "# SLA specification file for MIPS32 big endian\n\n@define ENDIAN \"big\"\n@define FREGSIZE \"4\" \n@define ISA_VARIANT \"\"\n\n@include \"mips.sinc\"\n@include \"mips32Instructions.sinc\"\n@include \"mips16.sinc\"\n@include \"mipsmicro.sinc\"\n@include \"mips_mt.sinc\"\n@include \"mips_dsp.sinc\"\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32le.cspec", "content": "\n\n\n \n \n \n \n \n \n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\t\t\t\t\t\n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32le.slaspec", "content": "# SLA specification file for MIPS32 little endian\n\n@define ENDIAN \"little\"\n@define FREGSIZE \"4\" \n@define ISA_VARIANT \"\"\n\n@include \"mips.sinc\"\n@include \"mips32Instructions.sinc\"\n@include \"mips16.sinc\"\n@include \"mipsmicro.sinc\"\n@include \"mips_mt.sinc\"\n@include \"mips_dsp.sinc\"\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips32micro.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64Instructions.sinc", "content": "\n############################\n#\n# MIPS64 Instructions\n#\n############################\n\n# 0111 00ss ssst tttt dddd d000 0010 0101\n:dclo RD, RSsrc is $(AMODE) & ((REL6=0 & prime=0x1C & sa=0x0 & fct=0x25) | (REL6=1 & prime=0x00 & sa=0x1 & fct=0x13 & op=0)) & RD & RSsrc {\n RD = lzcount( ~RSsrc );\n}\n# 0111 00ss ssst tttt dddd d000 0010 0100\n:dclz RD, RSsrc is $(AMODE) & ((REL6=0 & prime=0x1C & sa=0x0 & fct=0x24) | (REL6=1 & prime=0x00 & sa=0x1 & fct=0x12 & op=0)) & RD & RSsrc {\n RD = lzcount( RSsrc );\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0011\n:dext RT, RSsrc, lsb, ExtSize is $(AMODE) & prime=0x1F & fct=0x03 & RT & RSsrc & lsb & msbd & ExtSize {\n val:8 = (RSsrc >> lsb);\n val = val & (0xffffffff >> (32 - ExtSize));\n RT = zext(val);\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0001\n:dextm RT, RSsrc, lsb, DextmSize is $(AMODE) & prime=0x1F & fct=0x01 & RT & RSsrc & lsb & msbd & DextmSize {\n val:8 = (RSsrc >> lsb);\n val = val & (0xffffffffffffffff >> (64 - DextmSize));\n RT = zext(val);\n}\n# 0111 11ss ssst tttt mmmm mLLL LL00 0010\n:dextu RT, RSsrc, DXuPos, ExtSize is $(AMODE) & prime=0x1F & fct=0x02 & RT & RSsrc & lsb & msbd & DXuPos & ExtSize {\n val:8 = (RSsrc >> DXuPos);\n val = val & (0xffffffff >> (32 - ExtSize));\n RT = zext(val);\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0111\n:dins RT, RSsrc, lsb, InsSize is $(AMODE) & prime=0x1F & fct=0x07 & RT & RTsrc & RSsrc & lsb & msbd & InsSize {\n\ttmpa:$(REGSIZE) = -1;\n\ttmpa = tmpa >> ($(REGSIZE)*8 - InsSize);\n\ttmpb:$(REGSIZE) = RSsrc & tmpa;\n\ttmpa = tmpa << lsb;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << lsb;\n\tRT = (RT & tmpa) | tmpb;\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0101\n:dinsm RT, RSsrc, lsb, DinsXSize is $(AMODE) & prime=0x1F & fct=0x05 & RT & RTsrc & RSsrc & lsb & msbd & DinsXSize {\n\ttmpa:$(REGSIZE) = -1;\n\ttmpa = tmpa >> ($(REGSIZE)*8 - DinsXSize);\n\ttmpb:$(REGSIZE) = RSsrc & tmpa;\n\ttmpa = tmpa << lsb;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << lsb;\n\tRT = (RT & tmpa) | tmpb;\n}\n\n# 0111 11ss ssst tttt mmmm mLLL LL00 0110\n:dinsu RT, RSsrc, DXuPos, InsSize is $(AMODE) & prime=0x1F & fct=0x06 & RT & RTsrc & RSsrc & lsb & msbd & DXuPos & InsSize {\n\ttmpa:$(REGSIZE) = -1;\n\ttmpa = tmpa >> ($(REGSIZE)*8 - InsSize);\n\ttmpb:$(REGSIZE) = RSsrc & tmpa;\n\ttmpa = tmpa << DXuPos;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << DXuPos;\n\tRT = (RT & tmpa) | tmpb;\n}\n\n# 0100 0000 001t tttt dddd d000 0000 0eee\n:dmfc0 RT, RD0 is $(AMODE) & prime=16 & copop=1 & RT & RD0 & zero6=0 { \n RT = RD0;\n}\n:dmfc1 RT, fs is $(AMODE) & prime=17 & copop=1 & RT & fs & bigfunct=0 { \n RT = fs;\n}\n:dmfc2 RT, immed is $(AMODE) & prime=18 & copop=1 & RT & immed {\n RT = getCopReg(2:1, immed:4);\n}\n\n# 0100 0000 101t tttt dddd d000 0000 0eee\n:dmtc0 RTsrc, RD0 is $(AMODE) & prime=16 & copop=5 & RTsrc & RD0 & zero6=0 { \n RD0 = RTsrc;\n}\n# 0100 0100 101t tttt ssss s000 0000 0000\n:dmtc1 RTsrc, fs is $(AMODE) & prime=17 & copop=5 & RTsrc & fs & bigfunct=0 {\n fs = RTsrc;\n}\n:dmtc2 RTsrc, immed is $(AMODE) & prime=18 & copop=5 & RTsrc & immed {\n setCopReg(2:1, immed:4, RTsrc);\n}\n\n# 0000 0000 001t tttt dddd daaa aa11 1010\n:drotr RD, RTsrc, sa is $(AMODE) & prime=0x0 & zero1=0x0 & bit21=0x1 & fct=0x3A & RD & RTsrc & sa {\n tmp:8 = RTsrc;\n tmp1:8 = tmp >> sa;\n tmp2:8 = tmp << (64 - sa);\n RD = tmp1 + tmp2;\n}\n# 0000 0000 001t tttt dddd daaa aa11 1110 \n:drotr32 RD, RTsrc, sa is $(AMODE) & prime=0x0 & zero1=0x0 & bit21=0x1 & fct=0x3E & RD & RTsrc & sa {\n shift:1 = sa + 32;\n tmp:8 = RTsrc;\n tmp1:8 = tmp >> shift;\n tmp2:8 = tmp << (64 - shift);\n RD = tmp1 + tmp2;\n}\n# 0000 00ss ssst tttt dddd d000 0101 0110\n:drotrv RD, RTsrc, RSsrc is $(AMODE) & prime=0x0 & zero2=0x0 & bit6=0x1 & fct=0x16 & RD & RTsrc & RSsrc {\n shift:8 = RSsrc & 0x3f;\n tmp:8 = RTsrc;\n tmp1:8 = tmp >> shift;\n tmp2:8 = tmp << (32 - shift);\n RD = tmp1 + tmp2;\n}\n\n# 0111 1100 000t tttt dddd d000 1010 0100\n:dsbh RD, RTsrc is $(AMODE) & prime=0x1F & rs=0x0 & fct2=0x02 & fct=0x24 & RD & RTsrc { \n tmp1:8 = RTsrc & 0xff; \n tmp2:8 = (RTsrc >> 8) & 0xff;\n tmp3:8 = (RTsrc >> 16) & 0xff; \n tmp4:8 = (RTsrc >> 24) & 0xff;\n tmp5:8 = (RTsrc >> 32) & 0xff;\n tmp6:8 = (RTsrc >> 40) & 0xff;\n tmp7:8 = (RTsrc >> 48) & 0xff;\n tmp8:8 = (RTsrc >> 56) & 0xff;\n RD = (tmp7 << 56) | (tmp8 << 48) | (tmp5 << 40) | (tmp6 << 32) \n | (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | (tmp2); \n}\n# 0111 1100 000t tttt dddd d001 0110 0100\n:dshd RD, RTsrc is$(AMODE) & prime=0x1F & rs=0x0 & fct2=0x05 & fct=0x24 & RD & RTsrc {\n tmp1:8 = RTsrc & 0xffff;\n tmp2:8 = (RTsrc >> 16) & 0xffff;\n tmp3:8 = (RTsrc >> 32) & 0xffff;\n tmp4:8 = (RTsrc >> 48) & 0xffff;\n RD = (tmp1 << 48) | (tmp2 << 32) | (tmp3 << 16) | tmp4;\n}\n\n# 0000 0000 000t tttt dddd daaa aa11 1000\n:dsll RD, RTsrc, sa is $(AMODE) & prime=0 & fct=56 & rs=0 & RTsrc & RD & sa {\n RD = RTsrc << sa;\n}\n# 0000 0000 000t tttt dddd daaa aa11 1100\n:dsll32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=60 & rs=0 & RTsrc & RD & sa {\n RD = RTsrc << (sa + 32);\n}\n# 0000 00ss ssst tttt dddd d000 0001 0100\n:dsllv RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=20 & RSsrc & RTsrc & RD & sa=0 {\n RD = RTsrc << RSsrc;\n}\n# 0000 0000 000t tttt dddd daaa aa11 1011\n:dsra RD, RTsrc, sa is $(AMODE) & prime=0 & fct=59 & rs=0 & RTsrc & RD & sa {\n RD = RTsrc s>> sa;\n}\n# 0000 0000 000t tttt dddd daaa aa11 1111\n:dsra32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=63 & rs=0 & RTsrc & RD & sa {\n RD = RTsrc s>> (sa + 32);\n}\n# 0000 00ss ssst tttt dddd d000 0001 0111\n:dsrav RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=23 & RSsrc & RTsrc & RD & sa=0 {\n RD = RTsrc s>> RSsrc;\n}\n# 0000 0000 000t tttt dddd daaa aa11 1010\n:dsrl RD, RTsrc, sa is $(AMODE) & prime=0 & fct=58 & rs=0 & RTsrc & RD & sa {\n RD = RTsrc >> sa;\n}\n# 0000 0000 000t tttt dddd daaa aa11 1110\n:dsrl32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=62 & rs=0 & RTsrc & RD & sa {\n RD = RTsrc >> (sa + 32);\n}\n# 0000 00ss ssst tttt dddd d000 0101 0110\n:dsrlv RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=22 & RSsrc & RTsrc & RD & sa=0 {\n RD = RTsrc >> RSsrc;\n}\n\n# 0000 00ss ssst tttt dddd d000 0010 1110\n:dsub RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=46 & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc - RTsrc;\n}\n# 0000 00ss ssst tttt dddd d000 0010 1111\n:dsubu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=47 & RSsrc & RTsrc & RD & sa=0 {\n RD = RSsrc - RTsrc;\n}\n\n# 1101 11bb bbbt tttt iiii iiii iiii iiii\n:ld RT, OFF_BASE is $(AMODE) & prime=55 & OFF_BASE & RT { \n RT = *[ram]:8 OFF_BASE; \n}\n\n@if ENDIAN == \"big\"\n# 0110 10bb bbbt tttt iiii iiii iiii iiii\n:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT { \n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = RT & (0xffffffffffffffff >> ((8-shft) * 8));\n valLoad:8 = *(addr) << (shft * 8); \n RT = valLoad | valOrig;\n}\n# 0110 11bb bbbt tttt iiii iiii iiii iiii\n:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT {\n # no-op\n # see ldl instruction \n \n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = RT & (0xffffffffffffffff << ((shft+1) * 8));\n valLoad:8 = *(addr) >> ((7-shft) * 8);\n RT = valOrig | valLoad;\n}\n@else # ENDIAN == \"little\n# 0110 10bb bbbt tttt iiii iiii iiii iiii\n:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT { \n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = RT & (0xffffffffffffffff >> ((shft+1) * 8));\n valLoad:8 = *(addr) << ((7-shft) * 8); \n RT = valLoad | valOrig;\n}\n# 0110 11bb bbbt tttt iiii iiii iiii iiii\n:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT {\n # no-op\n # see ldl instruction \n \n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = RT & (0xffffffffffffffff << ((8-shft) * 8));\n valLoad:8 = *(addr) >> (shft * 8);\n RT = valOrig | valLoad;\n}\n@endif # ENDIAN\n\n# ldl and ldr almost always come in pairs. \n# When the analyzer does finds a matching ldl/ldr pair, the pcode is simplified so that \n# ldl does all the loading while ldr is a no-op\n@if ENDIAN == \"big\"\n:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { \n RT = *[ram]:8 OFF_BASE;\n} \n:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n}\n@else\n:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { \n} \n:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n RT = *[ram]:8 OFF_BASE;\n}\n@endif\n\n# 1101 00bb bbbt tttt iiii iiii iiii iiii\n:lld RT, OFF_BASE is $(AMODE) & prime=52 & OFF_BASE & RT { \n RT = *[ram]:8 OFF_BASE;\n}\n# 1001 11bb bbbt tttt iiii iiii iiii iiii\n:lwu RT, OFF_BASE is $(AMODE) & prime=39 & OFF_BASE & RT { \n RT = zext( *[ram]:4 OFF_BASE );\n}\n\n# 1111 00bb bbbt tttt iiii iiii iiii iiii\n:scd RTsrc, OFF_BASE is $(AMODE) & prime=60 & OFF_BASE & RT & RTsrc { \n *[ram]:8 OFF_BASE = RTsrc;\n RT = 1;\n}\n# 1111 11bb bbbt tttt iiii iiii iiii iiii\n:sd RTsrc, OFF_BASE is $(AMODE) & prime=63 & OFF_BASE & RTsrc {\n *[ram]:8 OFF_BASE = RTsrc;\n}\n\n@if ENDIAN == \"big\"\n# 1011 00bb bbbt tttt iiii iiii iiii iiii\n:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc { \n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = *(addr) & (0xffffffffffffffff << ((8-shft) * 8));\n valStore:8 = RTsrc >> (shft * 8);\n *(addr) = valOrig | valStore; \n}\n# 1011 01bb bbbt tttt iiii iiii iiii iiii\n:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc {\n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = *(addr) & (0xffffffffffffffff >> ((shft+1) * 8));\n valStore:8 = RTsrc << ((7-shft)*8);\n *(addr) = valStore | valOrig;\n}\n@else # ENDIAN == \"little\n# 1011 00bb bbbt tttt iiii iiii iiii iiii\n:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc { \n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = *(addr) & (0xffffffffffffffff << ((shft+1) * 8));\n valStore:8 = RTsrc >> ((7-shft) * 8);\n *(addr) = valOrig | valStore; \n}\n# 1011 01bb bbbt tttt iiii iiii iiii iiii\n:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc {\n shft:$(ADDRSIZE) = OFF_BASE & 0x7; \n addr:$(ADDRSIZE) = OFF_BASE - shft; \n valOrig:8 = *(addr) & (0xffffffffffffffff >> ((8-shft) * 8));\n valStore:8 = RTsrc << (shft*8);\n *(addr) = valStore | valOrig;\n}\n@endif # ENDIAN\n\n# When the analyzer finds a matching sdl/sdr pair, the pcode is simplified so that \n# sdl does all the storing while sdr is a no-op\n@if ENDIAN == \"big\"\n:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { \n *[ram]:8 OFF_BASE = RTsrc;\n}\n:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n}\n@else\n:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { \n}\n:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n *[ram]:8 OFF_BASE = RTsrc;\n}\n@endif\n####\n#\n# Pre-6 semantics\n#\n####\n# 0000 00ss ssst tttt 0000 0000 0001 1110\n:ddiv RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=30 & RSsrc & RTsrc & rd=0 & sa=0 {\n lo = RSsrc s/ RTsrc;\n hi = RSsrc s% RTsrc;\n}\n# 0000 00ss ssst tttt 0000 0000 0001 1111\n:ddivu RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=31 & RSsrc & RTsrc & rd=0 & sa=0 {\n lo = RSsrc / RTsrc; \n hi = RSsrc % RTsrc; \n}\n\n# 0000 00ss ssst tttt 0000 0000 0001 1100\n:dmult RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=28 & RSsrc & RTsrc & rd=0 & sa=0 {\n prod:16 = sext( RSsrc ) * sext( RTsrc );\n lo = prod(0);\n hi = prod(8); \n}\n# 0000 00ss ssst tttt 0000 0000 0001 1101\n:dmultu RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=29 & RSsrc & RTsrc & rd=0 & sa=0 {\n prod:16 = zext( RSsrc ) * zext( RTsrc ); \n lo = prod(0); \n hi = prod(8); \n}\n\n\n####\n#\n# Release 6 semantics\n#\n####\n:dalign RD, RSsrc, RTsrc, bp3 \tis $(AMODE) & REL6=1 & prime=0x1F & spec2=0x1 & fct=0x24 & bp3 & RSsrc & RTsrc & RD {\n\ttmp:8 = RTsrc << (8 * bp3);\n\ttmp = tmp | (RSsrc >> (64 - (8 * bp3)));\n\tRD = sext(tmp);\n}\n\n:daui RTsrc, RSsrc, S16L16\t\t\tis $(AMODE) & REL6=1 & prime=0x1D & rs!=0 & RSsrc & RTsrc & S16L16 {\n\tRTsrc = RSsrc + sext(S16L16);\n}\n\n:dahi RSsrc, S16L32\t\t\t\tis $(AMODE) & REL6=1 & prime=0x01 & op=0x06 & RSsrc & S16L32 {\n\tRSsrc = RSsrc + sext(S16L32);\n}\n\n:dati RSsrc, S16L48\t\t\t\tis $(AMODE) & REL6=1 & prime=0x01 & op=0x1E & RSsrc & S16L48 {\n\tRSsrc = RSsrc + sext(S16L48);\n}\n\n:dbitswap RD, RTsrc\t\t\t\tis $(AMODE) & REL6=1 & prime=0x1F & zero21=0 & fct2=0 & bshfl=0x24 & RTsrc & RD {\n\tRD = bitSwap(RTsrc);\n}\n\n:ddiv RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1E & fct2=0x02 & RD & RSsrc & RTsrc {\n\tRD = RSsrc s/ RTsrc;\n}\n\n:dmod RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1E & fct2=0x03 & RD & RSsrc & RTsrc {\n\tRD = RSsrc s% RTsrc;\n}\n\n:ddivu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1F & fct2=0x02 & RD & RSsrc & RTsrc {\n\tRD = RSsrc / RTsrc;\n}\n\n:dmodu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1F & fct2=0x03 & RD & RSsrc & RTsrc {\n\tRD = RSsrc % RTsrc;\n}\n\n:dmul RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1C & fct2=0x02 & RD & RSsrc & RTsrc {\n\ttmpS:16 = sext(RSsrc);\n\ttmpT:16 = sext(RTsrc);\n\ttmpS = tmpS * tmpT;\n\tRD = tmpS[0,64];\n}\n\n:dmuh RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1C & fct2=0x03 & RD & RSsrc & RTsrc {\n\ttmpS:16 = sext(RSsrc);\n\ttmpT:16 = sext(RTsrc);\n\ttmpS = tmpS * tmpT;\n\tRD = tmpS[64,64];\n}\n\n:dmulu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1D & fct2=0x02 & RD & RSsrc & RTsrc {\n\ttmpS:16 = zext(RSsrc);\n\ttmpT:16 = zext(RTsrc);\n\ttmpS = tmpS * tmpT;\n\tRD = tmpS[0,64];\n}\n\n:dmuhu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1D & fct2=0x03 & RD & RSsrc & RTsrc {\n\ttmpS:16 = zext(RSsrc);\n\ttmpT:16 = zext(RTsrc);\n\ttmpS = tmpS * tmpT;\n\tRD = tmpS[64,64];\n}\n\n:dlsa RD, RSsrc, RTsrc, SAV\t\tis $(AMODE) & REL6=1 & prime=0x00 & fct=0x15 & spec3=0 & SAV & RD & RSsrc & RTsrc {\n\tRD = (RSsrc << SAV) + RTsrc;\n}\n\n:ldpc RS, S18L3\t\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3B & pcrel2=0x6 & RS & S18L3 {\n\ttmp:8 = inst_start + sext(S18L3);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tRS = sext(*[ram]:8 tmpa);\n}\n\n:lldx RT, OFF_BASER6 \t\t\tis $(AMODE) & REL6=1 & prime=0x1F & fct=0x37 & bit6=1 & OFF_BASER6 & RT {\n RT = *[ram]:8 OFF_BASER6;\n}\n\n:lwupc RS, S19L2\t\t\t\tis $(AMODE) & REL6=1 & prime=0x3B & pcrel=0x2 & RS & S19L2 {\n\ttmp:8 = inst_start + sext(S19L2);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tRS = zext(*[ram]:4 tmpa);\n}\n\n:sdcx RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1E & fct=0x27 & bit6=1 & OFF_BASER6 & RTsrc {\n *[ram]:8 OFF_BASER6 = RTsrc;\n}\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64R6.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64_32_n32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64_32_o32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64_32_o64.cspec", "content": "\n\n\n \n\t\n \n \n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64be.cspec", "content": "\n\n \n\t\n\t\n\t\n\t\n \n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \t\n \t\n \t \n \t \n \t \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64be.slaspec", "content": "# SLA specification file for MIPS r5000 big endian\n\n@define ENDIAN \"big\"\n@define MIPS64 \"\"\n@define ISA_VARIANT \"\"\n\n@include \"mips.sinc\"\n@include \"mips32Instructions.sinc\"\n@include \"mips16.sinc\"\n@include \"mipsmicro.sinc\"\n@include \"mips64Instructions.sinc\"\n@include \"mips_dsp.sinc\"\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64le.cspec", "content": "\n\n \n\t\n\t\n\t\n\t\n \n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \t\n \t\n \t \n \t \n \t \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64le.slaspec", "content": "# SLA specification file for MIPS r5000 little endian\n\n@define ENDIAN \"little\"\n@define MIPS64 \"\"\n@define ISA_VARIANT \"\"\n\n@include \"mips.sinc\"\n@include \"mips32Instructions.sinc\"\n@include \"mips16.sinc\"\n@include \"mipsmicro.sinc\"\n@include \"mips64Instructions.sinc\"\n@include \"mips_dsp.sinc\"\n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips64micro.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips_dsp.sinc", "content": "\ndefine pcodeop ABSQ_S.PH;\ndefine pcodeop ABSQ_S.QB;\ndefine pcodeop ABSQ_S.W;\ndefine pcodeop ADDQ.PH;\ndefine pcodeop ADDQ_S.W;\ndefine pcodeop ADDQH.PH;\ndefine pcodeop ADDQH.W;\ndefine pcodeop ADDSC;\ndefine pcodeop ADDU.PH;\ndefine pcodeop ADDU.QB;\ndefine pcodeop ADDWC;\ndefine pcodeop ADDUH.QB;\ndefine pcodeop BITREV;\ndefine pcodeop DPA.W.PH;\ndefine pcodeop DPAQ_S.W.PH;\ndefine pcodeop DPAQ_SA.L.W;\ndefine pcodeop DPAQX_S.W.PH;\ndefine pcodeop DPAQX_SA.W.PH;\ndefine pcodeop DPAU.H.QBL;\ndefine pcodeop DPAU.H.QBR;\ndefine pcodeop DPAX.W.PH;\ndefine pcodeop DPS.W.PH;\ndefine pcodeop DPSQ_S.W.PH;\ndefine pcodeop DPSQ_SA.L.W;\ndefine pcodeop DPSQX_S.W.PH;\ndefine pcodeop DPSQX_SA.W.PH;\ndefine pcodeop DPSU.H.QBL;\ndefine pcodeop DPSU.H.QBR;\ndefine pcodeop DPSX.W.PH;\ndefine pcodeop EXTP;\ndefine pcodeop EXTPDP;\ndefine pcodeop EXTPDPV;\ndefine pcodeop EXTPV;\ndefine pcodeop EXTR.W;\ndefine pcodeop EXTR_S.H;\ndefine pcodeop EXTRV.W;\ndefine pcodeop EXTRV_S.H;\ndefine pcodeop INSV;\ndefine pcodeop MAQ_S.W.PHL;\ndefine pcodeop MAQ_S.W.PHR;\ndefine pcodeop MUL.PH;\ndefine pcodeop MULEQ_S.W.PHL;\ndefine pcodeop MULEQ_S.W.PHR;\ndefine pcodeop MULEU_S.PH.QBL;\ndefine pcodeop MULEU_S.PH.QBR;\ndefine pcodeop MULQ_RS.PH;\ndefine pcodeop MULQ_RS.W;\ndefine pcodeop MULQ_S.PH;\ndefine pcodeop MULQ_S.W;\ndefine pcodeop MULSA.W.PH;\ndefine pcodeop MULSAQ_S.W.PH;\ndefine pcodeop PRECEQ.W.PHL;\ndefine pcodeop PRECEQ.W.PHR;\ndefine pcodeop PRECEQU.PH.QBL;\ndefine pcodeop PRECEQU.PH.QBLA;\ndefine pcodeop PRECEQU.PH.QBR;\ndefine pcodeop PRECEQU.PH.QBRA;\ndefine pcodeop PRECEU.PH.QBL;\ndefine pcodeop PRECEU.PH.QBLA;\ndefine pcodeop PRECEU.PH.QBR;\ndefine pcodeop PRECEU.PH.QBRA;\ndefine pcodeop PRECR.QB.PH;\ndefine pcodeop PRECR_SRA.PH.W;\ndefine pcodeop PRECRQ.PH.W;\ndefine pcodeop PRECRQ.QB.PH;\ndefine pcodeop PRECRQU_S.QB.PH;\ndefine pcodeop PRECRQ_RS.PH.W;\ndefine pcodeop RADDU.W.QB;\ndefine pcodeop REPLV.PH;\ndefine pcodeop REPLV.QB;\ndefine pcodeop SHLL.PH;\ndefine pcodeop SHLL.QB;\ndefine pcodeop SHLLV.PH;\ndefine pcodeop SHLLV.QB;\ndefine pcodeop SHLLV_S.W;\ndefine pcodeop SHLL_S.W;\ndefine pcodeop SHRA.QB;\ndefine pcodeop SHRA.PH;\ndefine pcodeop SHRAV.PH;\ndefine pcodeop SHRAV.QB;\ndefine pcodeop SHRAV_R.W;\ndefine pcodeop SHRA_R.W;\ndefine pcodeop SHRL.PH;\ndefine pcodeop SHRL.QB;\ndefine pcodeop SHRLV.PH;\ndefine pcodeop SHRLV.QB;\ndefine pcodeop SUBQ.PH;\ndefine pcodeop SUBQ_S.W;\ndefine pcodeop SUBQH.PH;\ndefine pcodeop SUBQH.W;\ndefine pcodeop SUBU.PH;\ndefine pcodeop SUBU.QB;\ndefine pcodeop SUBUH.QB;\n\n\n# ABSQ_S.PH\tPurpose: Find Absolute Value of Two Fractional Halfwords\n:absq_s.ph RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x9 & fct=0x12 {\n\tRD = ABSQ_S.PH(RTsrc);\n}\n\n\n# ABSQ_S.QB\tPurpose: Find Absolute Value of Four Fractional Byte Values\n:absq_s.qb RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1 & fct=0x12 {\n\tRD = ABSQ_S.QB(RTsrc);\n}\n\n\n# ABSQ_S.W\tPurpose: Find Absolute Value of Fractional Word\n:absq_s.w RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x11 & fct=0x12 {\n\tRD = ABSQ_S.W(RTsrc);\n}\n\n\n# ADDQ[_S].PH\tPurpose: Add Fractional Halfword Vectors\n:addq.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xa & fct=0x10 {\n\tRD = ADDQ.PH(RSsrc, RTsrc);\n}\n\n:addq_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x10 {\n\tRD = ADDQ.PH(RSsrc, RTsrc);\n}\n\n\n# ADDQ_S.W\tPurpose: Add Fractional Words\n:addq_s.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x16 & fct=0x10 {\n\tRD = ADDQ_S.W(RSsrc, RTsrc);\n}\n\n\n# ADDQH[_R].PH\tPurpose: Add Fractional Halfword Vectors And Shift Right to Halve Results\n:addqh.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x8 & fct=0x18 {\n\tRD = ADDQH.PH(RSsrc, RTsrc);\n}\n\n:addqh_r.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xa & fct=0x18 {\n\tRD = ADDQH.PH(RSsrc, RTsrc);\n}\n\n\n# ADDQH[_R].W\tPurpose: Add Fractional Words And Shift Right to Halve Results\n:addqh.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x10 & fct=0x18 {\n\tRD = ADDQH.W(RSsrc, RTsrc);\n}\n\n:addqh_r.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x12 & fct=0x18 {\n\tRD = ADDQH.W(RSsrc, RTsrc);\n}\n\n\n# ADDSC\tPurpose: Add Signed Word and Set Carry Bit\n:addsc RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x10 & fct=0x10 {\n\tRD = ADDSC(RSsrc, RTsrc);\n}\n\n\n# ADDU[_S].PH\tPurpose: Unsigned Add Integer Halfwords\n:addu.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x8 & fct=0x10 {\n\tRD = ADDU.PH(RSsrc, RTsrc);\n}\n\n:addu_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xc & fct=0x10 {\n\tRD = ADDU.PH(RSsrc, RTsrc);\n}\n\n\n# ADDU[_S].QB\tPurpose: Unsigned Add Quad Byte Vectors\n:addu.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x0 & fct=0x10 {\n\tRD = ADDU.QB(RSsrc, RTsrc);\n}\n\n:addu_s.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x4 & fct=0x10 {\n\tRD = ADDU.QB(RSsrc, RTsrc);\n}\n\n\n# ADDWC\tPurpose: Add Word with Carry Bit\n:addwc RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x11 & fct=0x10 {\n\tRD = ADDWC(RSsrc, RTsrc);\n}\n\n\n# ADDUH[_R].QB\tPurpose: Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results\n:adduh.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x0 & fct=0x18 {\n\tRD = ADDUH.QB(RSsrc, RTsrc);\n}\n\n:adduh_r.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x2 & fct=0x18 {\n\tRD = ADDUH.QB(RSsrc, RTsrc);\n}\n\n\n# APPEND\tPurpose: Left Shift and Append Bits to the LSB\n:append RTsrc, RSsrc, sa_dsp \tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & sa_dsp & fct2=0x0 & fct=0x31 {\n\tRSval:$(REGSIZE) = RSsrc & (2^sa_dsp-1);\n\tRTsrc = (RTsrc << sa_dsp) | (RSval);\n}\n\n\n# BALIGN\tPurpose: Byte Align Contents from Two Registers\n:balign RTsrc, RSsrc, bp\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & bp & fct2=0x10 & fct=0x31 {\n\tRTsrc = (RTsrc << 8*bp) | (RSsrc >> 8*(4-bp));\n}\n\n\n# BITREV\tPurpose: Bit-Reverse Halfword\n:bitrev RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1b & fct=0x12 {\n\tRD = BITREV(RTsrc);\n}\n\n\n# BPOSGE32\tPurpose: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field\n:bposge32 Rel16\tis $(AMODE) & prime=0x1 & zero21=0x0 & op=0x1c & Rel16 {\n\tdsp_pos:$(REGSIZE) = DSPControl & 0x1f;\n\tif (dsp_pos < 32) goto inst_next;\n delayslot(1);\n goto Rel16; \n}\n\n# BPOSGE32C\tPurpose: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field Compact\n# no branch delay\n:bposge32c Rel16\tis $(AMODE) & prime=0x1 & zero21=0x0 & op=0x1a & Rel16 {\n\tdsp_pos:$(REGSIZE) = DSPControl & 0x1f;\n\tif (dsp_pos < 32) goto inst_next;\n goto Rel16; \n}\n\n# CMP.cond.PH\tPurpose: Compare Vectors of Signed Integer Halfword Values\n:cmp.eq.ph RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x8 & fct=0x11 {\n\ttmp_rs:2 = RSsrc(0) & 0xffff;\n\ttmp_rt:2 = RTsrc(0) & 0xffff;\n\tcca:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xffff;\n\ttmp_rt = RTsrc(2) & 0xffff;\n\tccb:1 = (tmp_rs == tmp_rt);\n\tflags:$(REGSIZE) = 0xfcffffff;\n\tDSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25);\n}\n\n:cmp.lt.ph RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x9 & fct=0x11 {\n\ttmp_rs:2 = RSsrc(0) & 0xffff;\n\ttmp_rt:2 = RTsrc(0) & 0xffff;\n\tcca:1 = (tmp_rs s< tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xffff;\n\ttmp_rt = RTsrc(2) & 0xffff;\n\tccb:1 = (tmp_rs s< tmp_rt);\n\tflags:$(REGSIZE) = 0xfcffffff;\n\tDSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25);\n}\n\n:cmp.le.ph RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0xa & fct=0x11 {\n\ttmp_rs:2 = RSsrc(0) & 0xffff;\n\ttmp_rt:2 = RTsrc(0) & 0xffff;\n\tcca:1 = (tmp_rs s<= tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xffff;\n\ttmp_rt = RTsrc(2) & 0xffff;\n\tccb:1 = (tmp_rs s<= tmp_rt);\n\tflags:$(REGSIZE) = 0xfcffffff;\n\tDSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25);\n}\n\n\n# CMPGDU.cond.QB\tPurpose: Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl\n:cmpgdu.eq.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x18 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:$(REGSIZE) = zext(tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:$(REGSIZE) = zext(tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:$(REGSIZE) = zext(tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:$(REGSIZE) = zext(tmp_rs == tmp_rt);\n\tflags:$(REGSIZE) = 0xf0ffffff;\n\tDSPControl = (DSPControl & flags) | (ccd << 27) | (ccc << 26) | (ccb << 25) | (cca << 24);\n\tRD = (ccd << 3) | (ccc << 2) | (ccb << 1) | (cca);\n}\n\n:cmpgdu.lt.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x19 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:$(REGSIZE) = zext(tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:$(REGSIZE) = zext(tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:$(REGSIZE) = zext(tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:$(REGSIZE) = zext(tmp_rs < tmp_rt);\n\tflags:$(REGSIZE) = 0xf0ffffff;\n\tDSPControl = (DSPControl & flags) | (cca << 24) | (ccb << 25) | (ccc << 26) | (ccd << 27);\n\tRD = (cca) | (ccb << 1) | (ccc << 2) | (ccd << 3);\n}\n\n:cmpgdu.le.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1a & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:$(REGSIZE) = zext(tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:$(REGSIZE) = zext(tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:$(REGSIZE) = zext(tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:$(REGSIZE) = zext(tmp_rs <= tmp_rt);\n\tflags:$(REGSIZE) = 0xf0ffffff;\n\tDSPControl = (DSPControl & flags) | (cca << 24) | (ccb << 25) | (ccc << 26) | (ccd << 27);\n\tRD = (cca) | (ccb << 1) | (ccc << 2) | (ccd << 3);\n}\n\n\n# CMPGU.cond.QB\tPurpose: Compare Vectors of Unsigned Byte Values and Write Results to a GPR\n:cmpgu.eq.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x4 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:1 = (tmp_rs == tmp_rt);\n\tRD = zext(cca) | zext(ccb << 1) | zext(ccc << 2) | zext(ccd << 3);\n}\n\n:cmpgu.lt.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x5 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:1 = (tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:1 = (tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:1 = (tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:1 = (tmp_rs < tmp_rt);\n\tRD = zext(cca) | zext(ccb << 1) | zext(ccc << 2) | zext(ccd << 3);\n}\n\n:cmpgu.le.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x6 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:1 = (tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:1 = (tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:1 = (tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:1 = (tmp_rs <= tmp_rt);\n\tRD = zext(cca) | zext(ccb << 1) | zext(ccc << 2) | zext(ccd << 3);\n}\n\n\n# CMPU.cond.QB\tPurpose: Compare Vectors of Unsigned Byte Values\n:cmpu.eq.qb RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x0 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:1 = (tmp_rs == tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:1 = (tmp_rs == tmp_rt);\n\tflags:$(REGSIZE) = 0xf0ffffff;\n\tDSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25) | zext(ccc << 26) | zext(ccd << 27);\n}\n\n:cmpu.lt.qb RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x1 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:1 = (tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:1 = (tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:1 = (tmp_rs < tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:1 = (tmp_rs < tmp_rt);\n\tflags:$(REGSIZE) = 0xf0ffffff;\n\tDSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25) | zext(ccc << 26) | zext(ccd << 27);\n}\n\n:cmpu.le.qb RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x2 & fct=0x11 {\n\ttmp_rs:1 = RSsrc(0) & 0xff;\n\ttmp_rt:1 = RTsrc(0) & 0xff;\n\tcca:1 = (tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(1) & 0xff;\n\ttmp_rt = RTsrc(1) & 0xff;\n\tccb:1 = (tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(2) & 0xff;\n\ttmp_rt = RTsrc(2) & 0xff;\n\tccc:1 = (tmp_rs <= tmp_rt);\n\ttmp_rs = RSsrc(3) & 0xff;\n\ttmp_rt = RTsrc(3) & 0xff;\n\tccd:1 = (tmp_rs <= tmp_rt);\n\tflags:$(REGSIZE) = 0xf0ffffff;\n\tDSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25) | zext(ccc << 26) | zext(ccd << 27);\n}\n\n\n# DPA.W.PH\tPurpose: Dot Product with Accumulate on Vector Integer Halfword Elements\n:dpa.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x0 & fct=0x30 {\n\tac = DPA.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPAQ_S.W.PH\tPurpose: Dot Product with Accumulation on Fractional Halfword Elements\n:dpaq_s.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x4 & fct=0x30 {\n\tac = DPAQ_S.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPAQ_SA.L.W\tPurpose: Dot Product with Accumulate on Fractional Word Element\n:dpaq_sa.l.w ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xc & fct=0x30 {\n\tac = DPAQ_SA.L.W(ac, RSsrc, RTsrc);\n}\n\n\n# DPAQX_S.W.PH\tPurpose: Cross Dot Product with Accumulation on Fractional Halfword Elements\n:dpaqx_s.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x18 & fct=0x30 {\n\tac = DPAQX_S.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPAQX_SA.W.PH\tPurpose: Cross Dot Product with Accumulation on Fractional Halfword Elements\n:dpaqx_sa.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x1a & fct=0x30 {\n\tac = DPAQX_SA.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPAU.H.QBL\tPurpose: Dot Product with Accumulate on Vector Unsigned Byte Elements\n:dpau.h.qbl ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x3 & fct=0x30 {\n\tac = DPAU.H.QBL(ac, RSsrc, RTsrc);\n}\n\n\n# DPAU.H.QBR\tPurpose: Dot Product with Accumulate on Vector Unsigned Byte Elements\n:dpau.h.qbr ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x7 & fct=0x30 {\n\tac = DPAU.H.QBR(ac, RSsrc, RTsrc);\n}\n\n\n# DPAX.W.PH\tPurpose: Cross Dot Product with Accumulate on Vector Integer Halfword Elements\n:dpax.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x8 & fct=0x30 {\n\tac = DPAX.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPS.W.PH\tPurpose: Dot Product with Subtract on Vector Integer Half-Word Elements\n:dps.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x1 & fct=0x30 {\n\tac = DPS.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPSQ_S.W.PH\tPurpose: Dot Product with Subtraction on Fractional Halfword Elements\n:dpsq_s.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x5 & fct=0x30 {\n\tac = DPSQ_S.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPSQ_SA.L.W\tPurpose: Dot Product with Subtraction on Fractional Word Element\n:dpsq_sa.l.w ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xd & fct=0x30 {\n\tac = DPSQ_SA.L.W(ac, RSsrc, RTsrc);\n}\n\n\n# DPSQX_S.W.PH\tPurpose: Cross Dot Product with Subtraction on Fractional Halfword Elements\n:dpsqx_s.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x19 & fct=0x30 {\n\tac = DPSQX_S.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPSQX_SA.W.PH\tPurpose: Cross Dot Product with Subtraction on Fractional Halfword Elements\n:dpsqx_sa.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x1b & fct=0x30 {\n\tac = DPSQX_SA.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# DPSU.H.QBL\tPurpose: Dot Product with Subtraction on Vector Unsigned Byte Elements\n:dpsu.h.qbl ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xb & fct=0x30 {\n\tac = DPSU.H.QBL(ac, RSsrc, RTsrc);\n}\n\n\n# DPSU.H.QBR\tPurpose: Dot Product with Subtraction on Vector Unsigned Byte Elements\n:dpsu.h.qbr ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xf & fct=0x30 {\n\tac = DPSU.H.QBR(ac, RSsrc, RTsrc);\n}\n\n\n# DPSX.W.PH\tPurpose: Cross Dot Product with Subtract on Vector Integer Halfword Elements\n:dpsx.w.ph ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x9 & fct=0x30 {\n\tac = DPSX.W.PH(ac, RSsrc, RTsrc);\n}\n\n\n# EXTP\tPurpose: Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR\n:extp RT, ac, sz\tis $(AMODE) & prime=0x1f & sz & RT & zero1315=0x0 & ac & fct2=0x2 & fct=0x38 {\n\tRT = EXTP(ac, sz:1);\n}\n\n\n# EXTPDP\tPurpose: Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos\n:extpdp RT, ac, sz\tis $(AMODE) & prime=0x1f & sz & RT & zero1315=0x0 & ac & fct2=0xa & fct=0x38 {\n\tRT = EXTPDP(ac, sz:1);\n}\n\n\n# EXTPDPV\tPurpose: Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos\n:extpdpv RT, ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0xb & fct=0x38 {\n\tRT = EXTPDPV(ac, RSsrc);\n}\n\n\n# EXTPV\tPurpose: Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR\n:extpv RT, ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x3 & fct=0x38 {\n\tRT = EXTPV(ac, RSsrc);\n}\n\n\n# EXTR[_RS].W\tPurpose: Extract Word Value With Right Shift From Accumulator to GPR\n:extr.w RT, ac, shift21\tis $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0x0 & fct=0x38 {\n\tval:$(DREGSIZE) = ac >> shift21:1;\n\tresult:4 = val(0);\n\tRT = zext(result);\n}\n\n:extr_r.w RT, ac, shift21\tis $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0x4 & fct=0x38 {\n\tval:$(DREGSIZE) = ac >> shift21:1;\n\tresult:4 = val(0);\n\tRT = EXTR.W(result, 1:1);\n}\n\n:extr_rs.w RT, ac, shift21\tis $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0x6 & fct=0x38 {\n\tval:$(DREGSIZE) = ac >> shift21:1;\n\tresult:4 = val(0);\n\tRT = EXTR.W(result, 2:1);\n}\n\n\n# EXTR_S.H\tPurpose: Extract Halfword Value From Accumulator to GPR With Right Shift and Saturate\n:extr_s.h RT, ac, shift21\tis $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0xe & fct=0x38 {\n\tval:$(DREGSIZE) = ac >> shift21:1;\n\tresult:2 = val(0);\n\tRT = EXTR_S.H(result);\n}\n\n\n# EXTRV[_RS].W\tPurpose: Extract Word Value With Variable Right Shift From Accumulator to GPR\n:extrv.w RT, ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x1 & fct=0x38 {\n\tshift:1 = RSsrc(0) & 0x3f;\n\tval:$(DREGSIZE) = ac >> shift;\n\tresult:4 = val(0);\n\tRT = EXTRV.W(result, 0:1);\n}\n\n:extrv_r.w RT, ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x5 & fct=0x38 {\n\tshift:1 = RSsrc(0) & 0x3f;\n\tval:$(DREGSIZE) = ac >> shift;\n\tresult:4 = val(0);\n\tRT = EXTRV.W(result, 1:1);\n}\n\n:extrv_rs.w RT, ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x7 & fct=0x38 {\n\tshift:1 = RSsrc(0) & 0x3f;\n\tval:$(DREGSIZE) = ac >> shift;\n\tresult:4 = val(0);\n\tRT = EXTRV.W(result, 2:1);\n}\n\n\n# EXTRV_S.H\tPurpose: Extract Halfword Value Variable From Accumulator to GPR With Right Shift and Saturate\n:extrv_s.h RT, ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0xf & fct=0x38 {\n\tshift:1 = RSsrc(0) & 0x3f;\n\tval:$(DREGSIZE) = ac >> shift;\n\tresult:2 = val(0);\n\tRT = EXTR_S.H(result);\n}\n\n\n# INSV\tPurpose: Insert Bit Field Variable\n:insv RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x0 & fct=0xc {\n\tRTsrc = INSV(RTsrc, RSsrc);\n}\n\n\n# LBUX\tPurpose: Load Unsigned Byte Indexed\n:lbux RD, INDEX_BASE\tis $(AMODE) & prime=0x1f & INDEX_BASE & RD & fct2=0x6 & fct=0xa {\n\tRD = zext(*[ram]:1 INDEX_BASE);\n}\n\n@ifdef MIPS64\n# LDX\tLoad Doubleword Indexed\n:ldx RD, INDEX_BASE\t\tis $(AMODE) & prime=0x1F & RD & fct=10 & fct2=8 & INDEX_BASE {\n RD = *[ram]:8 INDEX_BASE;\n}\n@endif\n\n# LHX\tPurpose: Load Halfword Indexed\n:lhx RD, INDEX_BASE\tis $(AMODE) & prime=0x1f & INDEX_BASE & RD & fct2=0x4 & fct=0xa {\n RD = sext(*[ram]:2 INDEX_BASE);\n}\n\n\n# LWX\tPurpose: Load Word Indexed\n:lwx RD, INDEX_BASE\tis $(AMODE) & prime=0x1f & INDEX_BASE & RD & fct2=0x0 & fct=0xa {\n@ifdef MIPS64\n RD = sext(*[ram]:4 INDEX_BASE);\n@else\n RD = *[ram]:4 INDEX_BASE;\n@endif\n}\n\n# MADD\tPurpose: Multiply Word and Add to Accumulator\n:madd ac, RS32src, RT32src\tis $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x0 {\n tmp1:$(DREGSIZE) = zext(RS32src);\n tmp2:$(DREGSIZE) = zext(RT32src);\n prod:$(DREGSIZE) = tmp1 * tmp2;\n ac = ac + prod;\n}\n\n\n# MADDU\tPurpose: Multiply Unsigned Word and Add to Accumulator\n:maddu ac, RS32src, RT32src\tis $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x1 {\n tmp1:$(DREGSIZE) = zext(RS32src);\n tmp2:$(DREGSIZE) = zext(RT32src);\n prod:$(DREGSIZE) = tmp1 * tmp2;\n ac = ac + prod;\n\n}\n\n\n# MAQ_S[A].W.PHL\tPurpose: Multiply with Accumulate Single Vector Fractional Halfword Element\n:maq_s.w.phl ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x14 & fct=0x30 {\n\tac = MAQ_S.W.PHL(RSsrc, RTsrc);\n}\n\n:maq_sa.w.phl ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x10 & fct=0x30 {\n\tac = MAQ_S.W.PHL(RSsrc, RTsrc);\n}\n\n\n# MAQ_S[A].W.PHR\tPurpose: Multiply with Accumulate Single Vector Fractional Halfword Element\n:maq_s.w.phr ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x16 & fct=0x30 {\n\tac = MAQ_S.W.PHR(RSsrc, RTsrc);\n}\n\n:maq_sa.w.phr ac, RSsrc, RTsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x12 & fct=0x30 {\n\tac = MAQ_S.W.PHR(RSsrc, RTsrc);\n}\n\n\n# MFHI\tPurpose: Move from HI register\n:mfhi RD, acfhi\tis $(AMODE) & prime=0x0 & zero2325=0x0 & acfhi & zero1620=0x0 & RD & fct2=0x0 & fct=0x10 {\n\tRD = acfhi;\n}\n\n\n# MFLO\tPurpose: Move from LO register\n:mflo RD, acflo\tis $(AMODE) & prime=0x0 & zero2325=0x0 & acflo & zero1620=0x0 & RD & fct2=0x0 & fct=0x12 {\n\tRD = acflo;\n}\n\n\n# MODSUB\tPurpose: Modular Subtraction on an Index Value\n:modsub RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x12 & fct=0x10 {\n\tdecr:1 = RTsrc(0);\n\tlastIdx:2 = RTsrc(1);\n\tequals:1 = (RSsrc == 0);\n\tRD = (zext(equals) * zext(lastIdx)) + (zext(!equals) * (RSsrc - zext(decr)));\n}\n\n\n# MSUB\tPurpose: Multiply Word and Subtract from Accumulator\n:msub ac, RS32src, RT32src\tis $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & aclo & achi & fct2=0x0 & fct=0x4 {\n tmp1:$(DREGSIZE) = sext(RS32src);\n tmp2:$(DREGSIZE) = sext(RT32src);\n prod:$(DREGSIZE) = tmp1 * tmp2;\n ac = ac - prod;\n}\n\n\n# MSUBU\tPurpose: Multiply Unsigned Word and Add to Accumulator\n\n:msubu ac, RS32src, RT32src\tis $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x5 {\n tmp1:$(DREGSIZE) = zext(RS32src);\n tmp2:$(DREGSIZE) = zext(RT32src);\n prod:$(DREGSIZE) = tmp1 * tmp2;\n ac = ac - prod;\n}\n\n\n# MTHI\tPurpose: Move to HI register\n:mthi RS, achi\tis $(AMODE) & prime=0x0 & RS & zero1320=0x0 & achi & fct2=0x0 & fct=0x11 {\n\tRS = achi;\n}\n\n\n# MTHLIP\tPurpose: Copy LO to HI and a GPR to LO and Increment Pos by 32\n:mthlip RS, ac\tis $(AMODE) & prime=0x1f & RS & zero1320=0x0 & ac & aclo & achi & fct2=0x1f & fct=0x38 {\n\tachi = aclo;\n\taclo = RS;\n\t# increment DSPControl pos field by 32\n}\n\n\n# MTLO\tPurpose: Move to LO register\n:mtlo RS, aclo\tis $(AMODE) & prime=0x0 & RS & zero1320=0x0 & aclo & fct2=0x0 & fct=0x13 {\n\tRS=aclo;\n}\n\n\n# MUL[_S].PH\tPurpose: Multiply Vector Integer HalfWords to Same Size Products\n:mul.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xc & fct=0x18 {\n\tRD = MUL.PH(RSsrc, RTsrc);\n}\n\n:mul_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x18 {\n\tRD = MUL.PH(RSsrc, RTsrc);\n}\n\n\n# MULEQ_S.W.PHL\tPurpose: Multiply Vector Fractional Left Halfwords to Expanded Width Products\n:muleq_s.w.phl RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1c & fct=0x10 {\n\tRD = MULEQ_S.W.PHL(RSsrc, RTsrc);\n}\n\n\n# MULEQ_S.W.PHR\tPurpose: Multiply Vector Fractional Right Halfwords to Expanded Width Products\n:muleq_s.w.phr RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1d & fct=0x10 {\n\tRD = MULEQ_S.W.PHR(RSsrc, RTsrc);\n}\n\n\n# MULEU_S.PH.QBL\tPurpose: Multiply Unsigned Vector Left Bytes by Halfwords to Halfword Products\n:muleu_s.ph.qbl RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x6 & fct=0x10 {\n\tRD = MULEU_S.PH.QBL(RSsrc, RTsrc);\n}\n\n\n# MULEU_S.PH.QBR\tPurpose: Multiply Unsigned Vector Right Bytes with halfwords to Half Word Products\n:muleu_s.ph.qbr RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x7 & fct=0x10 {\n\tRD = MULEU_S.PH.QBR(RSsrc, RTsrc);\n}\n\n\n# MULQ_RS.PH\tPurpose: Multiply Vector Fractional Halfwords to Fractional Halfword Products\n:mulq_rs.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1f & fct=0x10 {\n\tRD = MULQ_RS.PH(RSsrc, RTsrc);\n}\n\n\n# MULQ_RS.W\tPurpose: Multiply Fractional Words to Same Size Product with Saturation and Rounding\n:mulq_rs.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x17 & fct=0x18 {\n\tRD = MULQ_RS.W(RSsrc, RTsrc);\n}\n\n\n# MULQ_S.PH\tPurpose: Multiply Vector Fractional Half-Words to Same Size Products\n:mulq_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1e & fct=0x10 {\n\tRD = MULQ_S.PH(RSsrc, RTsrc);\n}\n\n\n# MULQ_S.W\tPurpose: Multiply Fractional Words to Same Size Product with Saturation\n:mulq_s.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x16 & fct=0x18 {\n\tRD = MULQ_S.W(RSsrc, RTsrc);\n}\n\n\n# MULSA.W.PH\tPurpose: Multiply and Subtract Vector Integer Halfword Elements and Accumulate\n:mulsa.w.ph ac, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x2 & fct=0x30 {\n\tac = MULSA.W.PH(RSsrc, RTsrc);\n}\n\n\n# MULSAQ_S.W.PH\tPurpose: Multiply And Subtract Vector Fractional Halfwords And Accumulate\n:mulsaq_s.w.ph ac, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x6 & fct=0x30 {\n\tac = MULSAQ_S.W.PH(RSsrc, RTsrc);\n}\n\n\n# MULT\tPurpose: Multiply Word\n:mult ac, RS32src, RT32src\tis $(AMODE) & prime=0x0 & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x18 {\n tmp1:$(DREGSIZE) = sext( RS32src );\n tmp2:$(DREGSIZE) = sext( RT32src );\n ac = tmp1 * tmp2;\n}\n\n\n# MULTU\tPurpose: Multiply Unsigned Word\n:multu ac, RS32src, RT32src\tis $(AMODE) & prime=0x0 & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x19 {\n tmp1:$(DREGSIZE) = zext( RS32src );\n tmp2:$(DREGSIZE) = zext( RT32src );\n ac = tmp1 * tmp2;\n}\n\n\n# PACKRL.PH\tPurpose: Pack a Vector of Halfwords from Vector Halfword Sources\n:packrl.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x11 {\n\tsrc1:2 = RSsrc(0);\n\tsrc2:2 = RTsrc(2);\n\tRD = zext(src1 << 16) + zext(src2);\n}\n\n\n# PICK.PH\tPurpose: Pick a Vector of Halfword Values Based on Condition Code Bits\n:pick.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x11 {\n\tcc24:1 = DSPControl[24,1];\n\tcc25:1 = DSPControl[25,1];\n\t\n\tval1:2 = RSsrc(0);\n\tval2:2 = RTsrc(0);\n\ttmp1:2 = (zext(cc24 == 1) * val1) + ((zext(cc24==0)) * val2);\n\t\n\tval1 = RSsrc(2);\n\tval2 = RTsrc(2);\n\ttmp2:2 = (zext(cc25 == 1) * val1) + ((zext(cc25==0)) * val2);\n\t\n\tRD = zext(tmp1) + zext(tmp2 << 16);\n}\n\n\n# PICK.QB\tPurpose: Pick a Vector of Byte Values Based on Condition Code Bits\n:pick.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x3 & fct=0x11 {\n\tlocal cc1:1 = DSPControl[24,1];\n\tlocal cc2:1 = DSPControl[25,1];\n\tlocal cc3:1 = DSPControl[26,1];\n\tlocal cc4:1 = DSPControl[27,1];\n\t\n\tlocal val1:1 = RSsrc(0);\n\tlocal val2:1 = RTsrc(0);\n\tlocal tmp1:1 = ((cc1 == 1) * val1) + (((cc1==0)) * val2);\n\n\tval1 = RSsrc(1);\n\tval2 = RTsrc(1);\n\tlocal tmp2:1 = ((cc2 == 1) * val1) + (((cc2==0)) * val2);\n\t\n\tval1 = RSsrc(2);\n\tval2 = RTsrc(2);\n\tlocal tmp3:1 = ((cc3 == 1) * val1) + (((cc3==0)) * val2);\n\n\tval1 = RSsrc(3);\n\tval2 = RTsrc(3);\n\tlocal tmp4:1 = ((cc4 == 1) * val1) + (((cc4==0)) * val2);\n\t\n\tRD = zext(tmp1) + zext(tmp2 << 8) + zext(tmp3 << 16) + zext(tmp4 << 24);\n}\n\n\n# PRECEQ.W.PHL\tPurpose: Precision Expand Fractional Halfword to Fractional Word Value\n:preceq.w.phl RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0xc & fct=0x12 {\n\tRD = PRECEQ.W.PHL(RTsrc);\n}\n\n\n# PRECEQ.W.PHR\tPurpose: Precision Expand Fractional Halfword to Fractional Word Value\n:preceq.w.phr RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0xd & fct=0x12 {\n\tRD = PRECEQ.W.PHR(RTsrc);\n}\n\n\n# PRECEQU.PH.QBL\tPurpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values\n:precequ.ph.qbl RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x4 & fct=0x12 {\n\tRD = PRECEQU.PH.QBL(RTsrc);\n}\n\n\n# PRECEQU.PH.QBLA\tPurpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values\n:precequ.ph.qbla RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x6 & fct=0x12 {\n\tRD = PRECEQU.PH.QBLA(RTsrc);\n}\n\n\n# PRECEQU.PH.QBR\tPurpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values\n:precequ.ph.qbr RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x5 & fct=0x12 {\n\tRD = PRECEQU.PH.QBR(RTsrc);\n}\n\n\n# PRECEQU.PH.QBRA\tPurpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values\n:precequ.ph.qbra RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x7 & fct=0x12 {\n\tRD = PRECEQU.PH.QBRA(RTsrc);\n}\n\n\n# PRECEU.PH.QBL\tPurpose: Precision Expand Two Unsigned Bytes to Unsigned Halfword Values\n:preceu.ph.qbl RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1c & fct=0x12 {\n\tRD = PRECEU.PH.QBL(RTsrc);\n}\n\n\n# PRECEU.PH.QBLA\tPurpose: Precision Expand Two Unsigned Bytes to Unsigned Halfword Values\n:preceu.ph.qbla RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1e & fct=0x12 {\n\tRD = PRECEU.PH.QBLA(RTsrc);\n}\n\n\n# PRECEU.PH.QBR\tPurpose: Precision Expand two Unsigned Bytes to Unsigned Halfword Values\n:preceu.ph.qbr RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1d & fct=0x12 {\n\tRD = PRECEU.PH.QBR(RTsrc);\n}\n\n\n# PRECEU.PH.QBRA\tPurpose: Precision Expand Two Unsigned Bytes to Unsigned Halfword Values\n:preceu.ph.qbra RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1f & fct=0x12 {\n\tRD = PRECEU.PH.QBRA(RTsrc);\n}\n\n\n# PRECR.QB.PH\tPurpose: Precision Reduce Four Integer Halfwords to Four Bytes\n:precr.qb.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xd & fct=0x11 {\n\tRD = PRECR.QB.PH(RSsrc, RTsrc);\n}\n\n\n# PRECR_SRA[_R].PH.W\tPurpose: Precision Reduce Two Integer Words to Halfwords after a Right Shift\n:precr_sra.ph.w rt, rs, sa_dsp\tis $(AMODE) & prime=0x1f & rs & rt & sa_dsp & fct2=0x1e & fct=0x11 {\n\tPRECR_SRA.PH.W();\n}\n\n:precr_sra_r.ph.w rt, rs, sa_dsp\tis $(AMODE) & prime=0x1f & rs & rt & sa_dsp & fct2=0x1f & fct=0x11 {\n\tPRECR_SRA.PH.W();\n}\n\n\n# PRECRQ.PH.W\tPurpose: Precision Reduce Fractional Words to Fractional Halfwords\n:precrq.ph.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x14 & fct=0x11 {\n\tRD = PRECRQ.PH.W(RSsrc, RTsrc);\n}\n\n\n# PRECRQ.QB.PH\tPurpose: Precision Reduce Four Fractional Halfwords to Four Bytes\n:precrq.qb.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xc & fct=0x11 {\n\tRD = PRECRQ.QB.PH(RSsrc, RTsrc);\n}\n\n\n# PRECRQU_S.QB.PH\tPurpose: Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation\n:precrqu_s.qb.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xf & fct=0x11 {\n\tRD = PRECRQU_S.QB.PH(RSsrc, RTsrc);\n}\n\n\n# PRECRQ_RS.PH.W\tPurpose: Precision Reduce Fractional Words to Halfwords With Rounding and Saturation\n:precrq_rs.ph.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x15 & fct=0x11 {\n\tRD = PRECRQ_RS.PH.W(RSsrc, RTsrc);\n}\n\n\n# PREPEND\tPurpose: Right Shift and Prepend Bits to the MSB\n:prepend RT, RSsrc, sa_dsp\tis $(AMODE) & prime=0x1f & RSsrc & RT & sa_dsp & fct2=0x1 & fct=0x31 {\n\tshift_val:1 = sa_dsp;\n\ttrunc_val:1 = ($(REGSIZE) * 8) - shift_val;\n\ttemp:$(REGSIZE) = (RSsrc << shift_val) + (RT >> trunc_val);\n\tRT = (zext(shift_val == 0) * RT) + (zext(shift_val != 0) * temp);\n}\n\n\n# RADDU.W.QB\tPurpose: Unsigned Reduction Add Vector Quad Bytes\n:raddu.w.qb RD, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & zero1620=0x0 & RD & fct2=0x14 & fct=0x10 {\n\tRD = RADDU.W.QB(RSsrc);\n}\n\n\n# RDDSP\tPurpose: Read DSPControl Register Fields to a GPR\n:rddsp RD, immed1625\tis $(AMODE) & prime=0x1f & immed1625 & RD & fct2=0x12 & fct=0x38 {\n\tRD = DSPControl & immed1625:$(REGSIZE);\n}\n\n:rddsp RD\tis $(AMODE) & prime=0x1f & immed1625=0x1f & RD & fct2=0x12 & fct=0x38 {\n\tRD = DSPControl;\n}\n\n\n# REPL.PH\tPurpose: Replicate Immediate Integer into all Vector Element Positions\n:repl.ph RD, immed1625\tis $(AMODE) & prime=0x1f & immed1625 & RD & fct2=0xa & fct=0x12 {\n\tval:2 = immed1625;\n\trepl:$(REGSIZE) = sext(val) << 16 | zext(val);\n\tRD = repl;\n}\n\n\n# REPL.QB\tPurpose: Replicate Immediate Integer into all Vector Element Positions\n:repl.qb RD, immed1623\tis $(AMODE) & prime=0x1f & zero2425=0x0 & immed1623 & RD & fct2=0x2 & fct=0x12 {\n\tbyte:1 = immed1623;\n\tRD = sext((byte << 24) | (byte << 16) | (byte << 8) | (byte));\n}\n\n\n# REPLV.PH\tPurpose: Replicate a Halfword into all Vector Element Positions\n:replv.ph RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0xb & fct=0x12 {\n\tRD = REPLV.PH(RTsrc);\n}\n\n\n# REPLV.QB\tPurpose: Replicate Byte into all Vector Element Positions\n:replv.qb RD, RTsrc\tis $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x3 & fct=0x12 {\n\tRD = REPLV.QB(RTsrc);\n}\n\n\n# SHILO\tPurpose: Shift an Accumulator Value Leaving the Result in the Same Accumulator\n:shilo ac, shift20\tis $(AMODE) & prime=0x1f & shift20 & zero1619=0x0 & zero1315=0x0 & ac & fct2=0x1a & fct=0x38 {\n\tshift_val:1 = shift20;\n\tac = (zext(shift_val s>= 0) * (ac >> shift_val)) + (zext(shift_val s< 0) * (ac << (-shift_val)));\n}\n\n\n# SHILOV\tPurpose: Variable Shift of Accumulator Value Leaving the Result in the Same Accumulator\n:shilov ac, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & zero1620=0x0 & zero1315=0x0 & ac & fct2=0x1b & fct=0x38 {\n\tshift_val:1 = RSsrc(1) & 0x7f;\n\tac = (zext(shift_val s>= 0) * (ac >> shift_val)) + (zext(shift_val s< 0) * (ac << (-shift_val)));\n}\n\n\n# SHLL[_S].PH\tPurpose: Shift Left Logical Vector Pair Halfwords\n:shll.ph RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0x8 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHLL.PH(RTsrc, shift_val);\n}\n\n:shll_s.ph RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0xc & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD= SHLL.PH(RTsrc, shift_val);\n}\n\n\n# SHLL.QB\tPurpose: Shift Left Logical Vector Quad Bytes\n:shll.qb RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x0 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHLL.QB(RTsrc, shift_val);\n}\n\n\n# SHLLV[_S].PH\tPurpose: Shift Left Logical Variable Vector Pair Halfwords\n:shllv.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xa & fct=0x13 {\n\tRD = SHLLV.PH(RTsrc, RSsrc);\n}\n\n:shllv_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x13 {\n\tRD = SHLLV.PH(RTsrc, RSsrc);\n}\n\n\n# SHLLV.QB\tPurpose: Shift Left Logical Variable Vector Quad Bytes\n:shllv.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x2 & fct=0x13 {\n\tRD = SHLLV.QB(RTsrc, RSsrc);\n}\n\n\n# SHLLV_S.W\tPurpose: Shift Left Logical Variable Vector Word\n:shllv_s.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x16 & fct=0x13 {\n\tRD = SHLLV_S.W(RTsrc, RSsrc);\n}\n\n\n# SHLL_S.W\tPurpose: Shift Left Logical Word with Saturation\n:shll_s.w RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x14 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHLL_S.W(RTsrc, shift_val);\n}\n\n\n# SHRA[_R].QB\tPurpose: Shift Right Arithmetic Vector of Four Bytes\n:shra.qb RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x4 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRA.QB(RTsrc, shift_val);\n}\n\n:shra_r.qb RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x5 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRA.QB(RTsrc, shift_val);\n}\n\n\n# SHRA[_R].PH\tPurpose: Shift Right Arithmetic Vector Pair Halfwords\n:shra.ph RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0x9 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRA.PH(RTsrc, shift_val);\n}\n\n:shra_r.ph RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0xd & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRA.PH(RTsrc, shift_val);\n}\n\n\n# SHRAV[_R].PH\tPurpose: Shift Right Arithmetic Variable Vector Pair Halfwords\n:shrav.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x13 {\n\tRD = SHRAV.PH(RTsrc, RSsrc);\n}\n\n:shrav_r.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xf & fct=0x13 {\n\tRD = SHRAV.PH(RTsrc, RSsrc);\n}\n\n\n# SHRAV[_R].QB\tPurpose: Shift Right Arithmetic Variable Vector of Four Bytes\n:shrav.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x6 & fct=0x13 {\n\tRD = SHRAV.QB(RTsrc, RSsrc);\n}\n\n:shrav_r.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x7 & fct=0x13 {\n\tRD = SHRAV.QB(RTsrc, RSsrc);\n}\n\n\n# SHRAV_R.W\tPurpose: Shift Right Arithmetic Variable Word with Rounding\n:shrav_r.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x17 & fct=0x13 {\n\tRD = SHRAV_R.W(RTsrc, RSsrc);\n}\n\n\n# SHRA_R.W\tPurpose: Shift Right Arithmetic Word with Rounding\n:shra_r.w RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x15 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRA_R.W(RTsrc, shift_val);\n}\n\n\n# SHRL.PH\tPurpose: Shift Right Logical Two Halfwords\n:shrl.ph RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0x19 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRL.PH(RTsrc, shift_val);\n}\n\n\n# SHRL.QB\tPurpose: Shift Right Logical Vector Quad Bytes\n:shrl.qb RD, RTsrc, sa_dsp2\tis $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x1 & fct=0x13 {\n\tshift_val:1 = sa_dsp2;\n\tRD = SHRL.QB(RTsrc, shift_val);\n}\n\n\n# SHRLV.PH\tPurpose: Shift Variable Right Logical Pair of Halfwords\n:shrlv.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1b & fct=0x13 {\n\tRD = SHRLV.PH(RTsrc, RSsrc);\n}\n\n\n# SHRLV.QB\tPurpose: Shift Right Logical Variable Vector Quad Bytes\n:shrlv.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x3 & fct=0x13 {\n\tRD = SHRLV.QB(RTsrc, RSsrc);\n}\n\n\n# SUBQ[_S].PH\tPurpose: Subtract Fractional Halfword Vector\n:subq.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x10 {\n\tRD = SUBQ.PH(RSsrc, RTsrc);\n}\n\n:subq_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xf & fct=0x10 {\n\tRD = SUBQ.PH(RSsrc, RTsrc);\n}\n\n\n# SUBQ_S.W\tPurpose: Subtract Fractional Word\n:subq_s.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x17 & fct=0x10 {\n\tRD = SUBQ_S.W(RSsrc, RTsrc);\n}\n\n\n# SUBQH[_R].PH\tPurpose: Subtract Fractional Halfword Vectors And Shift Right to Halve Results\n:subqh.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x9 & fct=0x18 {\n\tRD = SUBQH.PH(RSsrc, RTsrc);\n}\n\n:subqh_r.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x18 {\n\tRD = SUBQH.PH(RSsrc, RTsrc);\n}\n\n\n# SUBQH[_R].W\tPurpose: Subtract Fractional Words And Shift Right to Halve Results\n:subqh.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x11 & fct=0x18 {\n\tRD = SUBQH.W(RSsrc, RTsrc);\n}\n\n:subqh_r.w RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x13 & fct=0x18 {\n\tRD = SUBQH.W(RSsrc, RTsrc);\n}\n\n\n# SUBU[_S].PH\tPurpose: Subtract Unsigned Integer Halfwords\n:subu.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x9 & fct=0x10 {\n\tRD = SUBU.PH(RSsrc, RTsrc);\n}\n\n:subu_s.ph RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xd & fct=0x10 {\n\tRD = SUBU.PH(RSsrc, RTsrc);\n}\n\n\n# SUBU[_S].QB\tPurpose: Subtract Unsigned Quad Byte Vector\n:subu.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1 & fct=0x10 {\n\tRD = SUBU.QB(RSsrc, RTsrc);\n}\n\n:subu_s.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x5 & fct=0x10 {\n\tRD = SUBU.QB(RSsrc, RTsrc);\n}\n\n\n# SUBUH[_R].QB\tPurpose: Subtract Unsigned Bytes And Right Shift to Halve Results\n:subuh.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1 & fct=0x18 {\n\tRD = SUBUH.QB(RSsrc, RTsrc);\n}\n\n:subuh_r.qb RD, RTsrc, RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x3 & fct=0x18 {\n\tRD = SUBUH.QB(RSsrc, RTsrc);\n}\n\n\n# WRDSP\tPurpose: Write Fields to DSPControl Register from a GPR\n:wrdsp RSsrc, mask\tis $(AMODE) & prime=0x1f & RSsrc & mask & fct2=0x13 & fct=0x38 {\n\tDSPControl = (RSsrc & mask);\n}\n\n:wrdsp RSsrc\tis $(AMODE) & prime=0x1f & RSsrc & mask=0x1f & fct2=0x13 & fct=0x38 {\n\tDSPControl = RSsrc;\n}\n" }, { "path": "pypcode/processors/MIPS/data/languages/mips_mt.sinc", "content": "define pcodeop fork;\ndefine pcodeop move_from_thread_context;\ndefine pcodeop move_from_thread_cp0;\ndefine pcodeop move_from_thread_gpr;\ndefine pcodeop move_from_thread_dsp;\ndefine pcodeop move_from_thread_fpr;\ndefine pcodeop move_from_thread_fpcr;\ndefine pcodeop move_from_thread_cop2_data;\ndefine pcodeop move_from_thread_cop2_control;\ndefine pcodeop move_to_thread_context;\ndefine pcodeop move_to_thread_cp0;\ndefine pcodeop move_to_thread_gpr;\ndefine pcodeop move_to_thread_dsp;\ndefine pcodeop move_to_thread_fpr;\ndefine pcodeop move_to_thread_fpcr;\ndefine pcodeop move_to_thread_cop2_data;\ndefine pcodeop move_to_thread_cop2_control;\ndefine pcodeop yield;\n\n# Disable multi-threaded execution. Returns VPEControl\n:dmt RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x1 & zero5=0xF & fct=0x1 & RT {\n\t# Clear VPEControl IE bit (bit 15)\n\tRT = VPEControl; VPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0;\n}\n\n# Disable Virtual Processor Execution. Returns VPEControl\n:dvpe RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x0 & zero5=0x0 & fct=0x1 & RT {\n\t# Clear MVPControl EVP bit (bit 0)\n\tRT = MVPControl; MVPControl = MVPControl & ~0x1;\n}\n\n# Enable multi-threaded execution. Returns VPEControl\n:emt RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x1 & zero5=0xF & fct=0x21 & RT {\n\t# Set VPEControl TE bit (bit 15)\n\tRT = VPEControl; VPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1;\n} \n\n# Enable Virtual Processor Execution. Returns VPEControl\n:evpe RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x0 & zero5=0x0 & fct=0x21 & RT {\n# Set MVPControl EVP bit (bit 0)h\n\tRT = MVPControl;\n\tMVPControl = MVPControl | 0x1;\n}\n\n:fork \"Thread_GPR[\"^RDsrc^\"]\", RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0x1F & zero5=0x0 & fct=0x8 & RDsrc & RSsrc & RTsrc {\n\tfork(RDsrc, RSsrc, RTsrc);\n}\n\n# Move From Thread Context\n# MFTR general instruction\n:mftr RD, RTsrc, bit5, sel, h is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5 & h & bit3=0 & sel & RD & RTsrc {\n\ttmp:$(REGSIZE) = move_from_thread_context(RTsrc, bit5:1, sel:1, h:1);\n\tRD = tmp;\n}\n\n# MFTR instructions have many idioms for sub-decodings\n# Move from coprocessor 0 register rt, sel=sel\n:mftc0 RD, \"Thread_Co0[\"^RT0thread^\"]\", sel is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=0 & bit3=0 & RD & RT0thread & sel {\n\tRD = move_from_thread_cp0(RT0thread:1, sel:1);\n}\n\n:mftc0 RD, \"Thread_Co0[\"^RT0thread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=0 & bit3=0 & RD & RT0thread & sel=0 {\n\tRD = move_from_thread_cp0(RT0thread:1, 0:1);\n}\n\n# Move from GPR[rt]\n:mftgpr RD, \"Thread_GPR[\"^RTthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x0 & RD & RTthread {\n\tRD = move_from_thread_gpr(RTthread);\n}\n\nRtDSP: \"lo\" is lohiacx=0 { }\nRtDSP: \"hi\" is lohiacx=1 { }\nRtDSP: \"acx\" is lohiacx=2 { }\nRtDSP: \"dsp\" is rtmtdsp=16 { }\n\n\n:mft^RtDSP RD, rtmtdsp is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x1 & RD & RtDSP & rtmtdsp {\n\tRD = move_from_thread_dsp(rtmtdsp);\n}\n\n# Move from FPR[rt]\n:mftc1 RD, \"Thread_FPR[\"^FTthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & h=0 & bit3=0 & sel=0x2 & RD & FTthread {\n\tRD = move_from_thread_fpr(FTthread, 0:1);\n}\n\n:mfthc1 RD, \"Thread_FPR[\"^FTthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & h=1 & bit3=0 & sel=0x2 & RD & FTthread {\n\tRD = move_from_thread_fpr(FTthread, 1:1);\n}\n\n# Move from FPCR[rt]\n:cftc1 RD, \"Thread_FPCR[\"^FCTthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x3 & RD & FCTthread {\n\tRD = move_from_thread_fpcr(FCTthread);\n}\n\n# Skipping for now: MFTR for C0P2 Data and C0P2 Control (bit5=1, sel=4/5)\n\n# Move to Thread Context\n# MTTR general instruction\n:mttr RDsrc, RTsrc, bit5, sel, h is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5 & h & bit3=0 & sel & RDsrc & RTsrc {\n\tmove_to_thread_context(RDsrc, RTsrc, bit5:1, sel:1, h:1);\n}\n\n# MTTR instructions have many idioms for sub-decodings\n# Move rt to coprocessor 0 register rd, sel=sel\n:mttc0 RTsrc, \"Thread_Co0[\"^RD0thread^\"]\", sel is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=0 & bit3=0 & RTsrc & RD0thread & sel {\n\tmove_to_thread_cp0(RD0thread:1, RTsrc, sel:1);\n}\n\n:mttc0 RTsrc, \"Thread_Co0[\"^RD0thread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=0 & bit3=0 & RTsrc & RD0thread & sel=0 {\n\tmove_to_thread_cp0(RD0thread:1, RTsrc, 0:1);\n}\n\n# Move to GPR[rd]\n:mttgpr RTsrc, \"Thread_GPR[\"^RDthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=1 & bit3=0 & sel=0x0 & RTsrc & RDthread {\n\tmove_to_thread_gpr(RDthread, RTsrc);\n}\n\nRdDSP: \"lo\" is lohiacx2=0 { }\nRdDSP: \"hi\" is lohiacx2=1 { }\nRdDSP: \"acx\" is lohiacx2=2 { }\nRdDSP: \"dsp\" is rdmtdsp=16 { }\n\n# Move to DSP[rd]\n:mtt^RdDSP RTsrc, rdmtdsp is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=1 & bit3=0 & sel=0x1 & RTsrc & RdDSP & rdmtdsp {\n\tmove_to_thread_dsp(rdmtdsp, RTsrc);\n}\n\n# Move to FPR[rd]\n:mttc1 RTsrc, \"Thread_FPR[\"^FDthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & h=0 & bit3=0 & sel=0x2 & RTsrc & FDthread {\n\tmove_to_thread_fpr(FDthread, RTsrc, 0:1);\n}\n\n:mtthc1 RTsrc, \"Thread_FPR[\"^FDthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & h=1 & bit3=0 & sel=0x2 & RTsrc & FDthread {\n\tmove_to_thread_fpr(FDthread, RTsrc, 1:1);\n}\n\n# Move to FPCR[rd]\n:cttc1 RTsrc, \"Thread_FPCR[\"^FCRthread^\"]\" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & bit3=0 & sel=0x3 & RTsrc & FCRthread {\n\tmove_to_thread_fpcr(FCRthread, RTsrc);\n}\n\n# Skipping for now: MTTR for C0P2 Data and C0P2 control (bit5=1, sel=4/5)\n\n# Conditionally Deschedule or Deallocate the Current Thread\n:yield RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1F & op=0 & zero5=0x0 & fct=0x9 & RD & RSsrc {\n\tyield(RSsrc);\n\tRD = RSsrc & YQMask;\n}\n\n:yield RSsrc is $(AMODE) & REL6=0 & prime=0x1F & op=0 & zero5=0x0 & fct=0x9 & rd=0 & RSsrc {\n\tyield(RSsrc);\n}\n" }, { "path": "pypcode/processors/MIPS/data/languages/mipsfloat.sinc", "content": "\n############################\n#\n# MIPS Floating Point (COP1 - coprocessor 1) instructions\n# includes arithmetic, compares, branch on FP condition flag, conversions\n# Also Coprocessor 0 instructions\n#\n# Note a MIPS word is 32-bits, and a long is a 64-bit integer\n#\n# mipsP6float.sinc contains floating point instructions that are in pre-Release 6 but not in Release 6\n#\n# mipsR6float.sinc contains floating point instructions that are in Release 6 and later\n#\n############################\n\ndefine pcodeop mipsFloatPS;\n\n# 0100 01ff fff0 0000 ssss sddd dd00 0101\n:abs.S fd, fs is $(AMODE) & prime=17 & fct=5 & fmt1 & format=0x10 & fs & fd {\n\tfd[0,32] = abs( fs:4 );\n}\n:abs.D fd, fs is $(AMODE) & prime=17 & fct=5 & fmt1 & format=0x11 & fs & fd & fsD & fdD {\n fdD = abs(fsD);\n}\n:abs.PS fd, fs is $(AMODE) & REL6=0 & prime=17 & fct=5 & fmt1 & fs & fd & format=0x16 & fdD & fsD {\n fdD = mipsFloatPS(fsD);\n}\n\n# 0100 01ff ffft tttt ssss sddd dd00 0000\n:add.S fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x10 & ft & fs & fd {\n fd[0,32] = fs:4 f+ ft:4;\n}\n:add.D fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x11 & ft & fs & fd & ftD & fsD & fdD {\n fdD = fsD f+ ftD;\n}\n:add.PS fd, fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=0 & fmt1 & ft & fs & fd & format=0x16 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 1010\n:ceil.l.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0A & fmt2 & fd & fs & format=0x10 & fdD {\n # Note this instruction is in release 2 and later\n fd_tmp:4 = ceil(fs:4); # Note that ceil returns a float the same size as its argument\n fdD = trunc(fd_tmp); # Note that trunc converts a float to an integer\n}\n\n:ceil.l.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0A & fmt2 & fd & fs & format=0x11 & fsD & fdD {\n # Note this instruction is in release 2 and later\n fsD_tmp:8 = ceil(fsD); # Note that ceil returns a float the same size as its argument\n fdD = trunc(fsD_tmp); # Convert to 64-bit integer\n}\n# 0100 01ff fff0 0000 ssss sddd dd00 1110\n:ceil.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x10 {\n fs_ceil_tmp:4 = ceil(fs:4); # Note that ceil returns a float the same size as its argument\n fd[0,32] = trunc(fs_ceil_tmp);\n}\n:ceil.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x11 & fsD {\n fs_tmp:8 = ceil(fsD); # Note that ceil returns a float the same size as its argument\n fd[0,32] = trunc( fs_tmp ); # Need to set only 32 bits of fd\n}\n\n# 0100 0100 010t tttt ssss s000 0000 0000\n:cfc1 RT, fs_unk is $(AMODE) & prime=17 & copop=2 & RT & fs_unk & bigfunct=0 { \n tmp:4 = getCopControlWord( 1:1, fs_unk:4 );\n RT = sext(tmp);\n}\n:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & (fs=0 | fs=25 | fs=26 | fs=28 | fs=31) & bigfunct=0 { \n RT = sext(fs_fcr);\n}\n# Since we don't track the state of the FCSR bits, no sense in introducing complex code\n#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=25 & bigfunct=0 { \n# tmp1:4 = (fcsr & 0x00800000) >> 23; \n# tmp2:4 = (fcsr & 0xfe000000) >> 24;\n# RT = sext(tmp2 + tmp1);\n#}\n#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=26 & bigfunct=0 {\n# tmp1:4 = fcsr & 0x0003f07c; \n# RT = sext(tmp1);\n#}\n#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=28 & bigfunct=0 {\n# tmp1:4 = fcsr & 0x00000f83;\n# tmp2:4 = (fcsr & 0x01000000) >> 24; \n# RT = sext(tmp1 + tmp2);\n#}\n#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=31 & bigfunct=0 {\n# RT = sext(fcsr);\n#}\n\n# 0100 0100 110t tttt ssss s000 0000 0000\n:ctc1 RTsrc, fs_unk is $(AMODE) & prime=17 & copop=6 & RTsrc & fs_unk & bigfunct=0 { \n setCopControlWord( 1:1, fs_unk:4, RTsrc );\n}\n:ctc1 RTsrc, fs_fcr is $(AMODE) & prime=17 & copop=6 & RTsrc & fs_fcr & (fs=0 | fs=25 | fs=26 | fs=28 | fs=31) & bigfunct=0 { \n fs_fcr = RTsrc:$(SIZETO4);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd10 0001\n:cvt.d.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x21 & fmt3 & fd & fs & format=0x10 & fdD {\n # Convert from single float to double float\n fdD = float2float(fs:4);\n}\n:cvt.d.W fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x21 & fmt3 & fd & fs & format=0x14 & fdD {\n # Convert from 32-bit int word source to double float\n fs_tmp:4 = fs:4;\n fdD = int2float(fs_tmp);\n}\n:cvt.d.L fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x21 & fmt3 & fd & fs & format=0x15 & fdD & fsD {\n # Note this instruction is in release 2 and later\n # Convert from 64-bit long source to double float\n fdD = int2float(fsD);\n}\n# 0100 01ff fff0 0000 ssss sddd dd10 0101\n:cvt.l.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x25 & fmt2 & fd & fs & format=0x10 & fdD {\n # Note this instruction is in release 2 and later\n # Convert from single float source to 64-bit long integer, using the fcsr RM rounding mode bits\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n fs_tmp:4 = fs:4; # Get the lower 32-bits as a floating point single\n fs_cvt_tmp:4 = 0;\n if (rm_tmp == 0) goto ;\n fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fs_cvt_tmp = round(fs_tmp); # round returns a float\n \n fdD = trunc(fs_cvt_tmp); # trunc returns an integer\n}\n:cvt.l.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x25 & fmt2 & fd & fs & format=0x11 & fsD & fdD {\n # Note this instruction is in release 2 and later\n # Convert from double float to 64-bit long integer, using fcsr RM rounding mode bits\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n if (rm_tmp == 0) goto ;\n fd_tmp:8 = floor(fsD); # RM is 1, no rounding\n goto ;\n \n fd_tmp = round(fsD);\n \n fdD = trunc(fd_tmp);\n}\n# 0100 0110 000t tttt ssss sddd dd10 0110\n:cvt.PS.S fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x10 & fct=0x26 & fd & fs & ft & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd10 0000\n:cvt.s.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x20 & fmt4 & fd & fs & format=0x11 & fsD {\n fd[0,32] = float2float(fsD);\n}\n:cvt.s.W fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x20 & fmt4 & fd & fs & format=0x14 {\n fd[0,32] = int2float(fs:4);\n}\n:cvt.s.L fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x20 & fmt4 & fd & fs & format=0x15 & fsD {\n # Note this instruction is in release 2 and later\n fd[0,32] = int2float(fsD);\n}\n# 0100 0110 1100 0000 ssss sddd dd10 1000\n:cvt.s.pl fd, fs is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & ft=0x0 & fct=0x28 & fd & fs & fdD & fsD {\n fdD = mipsFloatPS(fsD);\n}\n# 0100 0110 1100 0000 ssss sddd dd10 0000\n:cvt.s.pu fd, fs is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & ft=0x0 & fct=0x20 & fd & fs & fdD & fsD {\n fdD = mipsFloatPS(fsD);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd10 0100\n:cvt.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x24 & fmt2 & fd & fs & format=0x10 {\n # Convert from single float source to 32-bit integer word, using the fcsr RM rounding mode bits\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n fs_tmp:4 = fs:4;\n fs_cvt_tmp:4 = 0;\n if (rm_tmp == 0) goto ;\n fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fs_cvt_tmp = round(fs_tmp); # round returns a float\n \n fd[0,32] = trunc(fs_cvt_tmp);\t# trunc returns an integer\n}\n:cvt.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x24 & fmt2 & fd & fs & format=0x11 & fsD {\n # Convert from double float source to 32-bit integer word, using the fcsr RM rounding mode bits\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n if (rm_tmp == 0) goto ;\n fs_tmp:8 = floor(fsD); # RM is 1, no rounding\n goto ;\n \n fs_tmp = round(fsD);\n \n fd[0,32] = trunc(fs_tmp);\n}\n\n# 0100 01ff ffft tttt ssss sddd dd00 0011\n:div.S fd, fs, ft is $(AMODE) & prime=17 & fct=3 & fmt2 & ft & fs & fd & format=0x10 {\n fd[0,32] = fs:4 f/ ft:4;\n}\n:div.D fd, fs, ft is $(AMODE) & prime=17 & fct=3 & fmt2 & ft & fs & fd & format=0x11 & fdD & fsD & ftD {\n fdD = fsD f/ ftD;\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 1011\n:floor.l.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0B & fmt2 & fd & fs & format=0x10 & fdD {\n # Note this instruction is in release 2 and later\n # Convert floor of single float to a 64-bit long integer\n fd_tmp:4 = floor(fs:4); # returns a float\n fdD = trunc(fd_tmp); # converts float to int\n}\n:floor.l.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0B & fmt2 & fd & fs & format=0x11 & fdD & fsD {\n # Note this instruction is in release 2 and later\n fsD_tmp:8 = floor(fsD);\n fdD = trunc(fsD_tmp);\n}\n# 0100 01ff fff0 0000 ssss sddd dd00 1111\n:floor.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0F & fmt2 & fd & fs & format=0x10 {\n # Floor of single float copied to a 32-bit integer word\n fd_tmp:4 = floor(fs:4); # returns a float\n fd = trunc(fd_tmp); # converts float to int\n}\n:floor.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0F & fmt2 & fd & fs & format=0x11 & fsD {\n # Floor of double float to a 32-bit integer word\n fd[0,32] = trunc(floor(fsD));\n}\n\n# 1101 01bb bbbt tttt iiii iiii iiii iiii\n:ldc1 ft, OFF_BASE is $(AMODE) & prime=53 & OFF_BASE & ft & ftD {\n ftD = *[ram]:8 OFF_BASE;\n}\n\n# 1111 01bb bbbt tttt iiii iiii iiii iiii\n:sdc1 ft, OFF_BASE is $(AMODE) & prime=61 & OFF_BASE & ft & ftD {\n *[ram]:8 OFF_BASE = ftD;\n}\n\n# 1100 01bb bbbt tttt iiii iiii iiii iiii\n:lwc1 ft, OFF_BASE is $(AMODE) & prime=49 & OFF_BASE & ft { \n ft[0,32] = *[ram]:4 OFF_BASE;\n}\n\n# 0100 0100 000t tttt ssss s000 0000 0000\n:mfc1 RT, fs is $(AMODE) & prime=17 & copop=0 & RT & fs & bigfunct=0 {\n # Move just a word, 32-bits\n RT = sext( fs:$(SIZETO4) );\n}\n\n# 0100 0100 011t tttt ssss s000 0000 0000\n:mfhc1 RT, fs is $(AMODE) & prime=17 & copop=3 & bigfunct=0 & RT & fs & fsD {\n RT = sext(fsD[32,32]);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 0110\n:mov.S fd, fs is $(AMODE) & prime=17 & fct=6 & fmt1 & fs & fd & format=0x10 {\n fd[0,32] = fs:4;\n}\n:mov.D fd, fs is $(AMODE) & prime=17 & fct=6 & fmt1 & fs & fd & format=0x11 & fdD & fsD {\n fdD = fsD;\n}\n:mov.PS fd, fs is $(AMODE) & REL6=0 & prime=17 & fct=6 & fmt1 & fs & fd & format=0x16 & fsD & fdD {\n fdD = mipsFloatPS(fsD);\n}\n\n# 0100 0100 100t tttt dddd d000 0000 0000\n:mtc1 RTsrc, fs is $(AMODE) & prime=17 & copop=4 & RTsrc & fs & bigfunct=0 {\n # Move 32-bits of RTsrc to Low Half of FPR fs\n\tfs[0,32] = RTsrc:$(SIZETO4);\n}\n\n# 0100 0100 111t tttt ssss s000 0000 0000\n:mthc1 RTsrc, fs is $(AMODE) & prime=17 & copop=0x07 & bigfunct=0x0 & RTsrc & fs & fsD {\n # Move 32-bits of RTsrc to High Half of FPR\n fsD[32,32] = RTsrc:4;\n}\n\n# 0100 01ff ffft tttt ssss sddd dd00 0010\n:mul.S fd, fs, ft is $(AMODE) & prime=17 & fct=2 & fmt1 & ft & fs & fd & format=0x10 {\n fd[0,32] = fs:4 f* ft:4; # need to only get the single float 32-bit (fs might be 64-bits)\n}\n:mul.D fd, fs, ft is $(AMODE) & prime=17 & fct=2 & fmt1 & ft & fs & fd & format=0x11 & fdD & fsD & ftD {\n fdD = fsD f* ftD;\n}\n:mul.PS fd, fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=2 & fmt1 & ft & fs & fd & format=0x16 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 0111\n:neg.S fd, fs is $(AMODE) & prime=17 & fct=7 & fmt1 & fs & fd & format=0x10 {\n fd[0,32] = f- fs:4;\n}\n:neg.D fd, fs is $(AMODE) & prime=17 & fct=7 & fmt1 & fs & fd & format=0x11 & fdD & fsD {\n fdD = f- fsD;\n}\n:neg.PS fd, fs is $(AMODE) & REL6=0 & prime=17 & fct=7 & fmt1 & fs & fd & format=0x16 & fsD & fdD {\n fdD = mipsFloatPS(fsD);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd01 0101\n:recip.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=21 & fmt2 & fd & fs & format=0x10 {\n fd[0,32] = 1:4 f/ fs:4;\n}\n:recip.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=21 & fmt2 & fd & fs & format=0x11 & fdD & fsD {\n fdD = 1:8 f/ fsD;\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 1000\n:round.l.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=8 & fmt2 & fd & fs & format=0x10 & fdD {\n # Note this instruction is in release 2 and later\n fd_tmp:4 = round(fs:4); # round returns a float of the same size are the arg\n fdD = trunc(fd_tmp); # trunc converts to any size integer\n}\n:round.l.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=8 & fmt2 & fd & fs &format=0x11 & fsD & fdD {\n # Note this instruction is in release 2 and later\n fsD_tmp:8 = round(fsD);\n fdD = trunc(fsD_tmp);\n}\n# 0100 01ff fff0 0000 ssss sddd dd00 1100\n:round.w.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=12 & fmt2 & fd & fs & format=0x10 {\n fd_tmp:4 = round(fs:4);\n fd = trunc(fd_tmp);\n}\n:round.w.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=12 & fmt2 & fd & fs & format=0x11 & fsD {\n fdD_tmp:8 = round(fsD); # round returns a float, not an int\n fd[0,32] = trunc(fdD_tmp); # We need only a 32-bit integer\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd01 0110\n:rsqrt.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=22 & fmt2 & fd & fs & format=0x10 {\n fd[0,32] = 1:4 f/ sqrt(fs:4);\n}\n:rsqrt.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=22 & fmt2 & fd & fs & format=0x11 & fdD & fsD {\n fdD = 1:8 f/ sqrt(fsD);\n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 0100\n:sqrt.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=4 & fmt2 & fd & fs & format=0x10 {\n fd[0,32] = sqrt(fs:4);\n}\n:sqrt.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=4 & fmt2 & fd & fs & format=0x11 & fsD & fdD {\n fdD = sqrt(fsD);\n}\n\n# 0100 01ff ffft tttt ssss sddd dd00 0001\n:sub.S fmt1 fd, fs, ft is $(AMODE) & prime=17 & fct=1 & fmt1 & ft & fs & fd & format=0x10 {\n fd[0,32] = fs:4 f- ft:4;\n}\n:sub.D fmt1 fd, fs, ft is $(AMODE) & prime=17 & fct=1 & fmt1 & ft & fs & fd & format=0x11 & fdD & fsD & ftD {\n fdD = fsD f- ftD;\n}\n:sub.PS fmt1 fd, fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=1 & fmt1 & ft & fs & fd & format=0x16 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 1110 01bb bbbt tttt iiii iiii iiii iiii\n:swc1 ft, OFF_BASE is $(AMODE) & prime=57 & OFF_BASE & ft { \n *[ram]:4 OFF_BASE = ft:$(SIZETO4); \n}\n\n# 0100 01ff fff0 0000 ssss sddd dd00 1001\n:trunc.l.S fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=9 & format=0x10 & fdD {\n # Note this instruction is in release 2 and later\n fd = trunc(fs:4);\n}\n:trunc.l.D fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=9 & format=0x11 & fdD & fsD {\n # Note this instruction is in release 2 and later\n fdD = trunc(fsD);\n}\n# 0100 01ff fff0 0000 ssss sddd dd00 1101\n:trunc.w.S fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=13 & format=0x10 {\n fd[0,32] = trunc(fs:4);\n}\n:trunc.w.D fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=13 & format=0x11 & fsD {\n fd[0,32] = trunc(fsD);\n}\n\n############################\n#\n# COP1X (Extended FP)\n#\n############################\n\n# 0100 11ss ssst tttt ssss sddd dd01 1110\n:alnv.PS fd, fs, ft, rs is $(AMODE) & REL6=0 & prime=0x13 & fct=0x1E & rs & ft & fs & fd & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 11bb bbbi iiii 0000 0ddd dd00 0001\n:ldxc1 fd, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero4=0 & fct=0x01 & INDEX_BASE & fd & fdD { \n fdD = *[ram]:8 INDEX_BASE;\n}\n\n# 0100 11bb bbbi iiii 0000 0ddd dd00 0101\n:luxc1 fd, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero4=0 & fct=0x05 & INDEX_BASE & fd & fdD {\n ptr:$(ADDRSIZE) = INDEX_BASE & -16:$(ADDRSIZE); \n fdD = *[ram]:8 ptr;\n}\n\n# 0100 11bb bbbi iiii 0000 0ddd dd00 0000\n:lwxc1 fd, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero4=0 & fct=0x0 & INDEX_BASE & fd {\n fd[0,32] = *[ram]:4 INDEX_BASE;\n}\n\n# 0100 11rr rrrt tttt ssss sddd dd10 0fff\n:madd.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x04 & fmt5 & fd & fr & fs & ft & format1X=0x0 {\n fd[0,32] = (fs:4 f* ft:4) f+ fr:4; # must do floating arithmetic in 32 bit\n}\n:madd.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x04 & fmt5 & fd & fr & fs & ft &\n\t\t\t\tformat1X=0x1 & fdD & fsD & frD & ftD {\n fdD = (fsD f* ftD) f+ frD;\n}\n:madd.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x04 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 11rr rrrt tttt ssss sddd dd10 1fff\n:msub.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x05 & fmt5 & fd & fr & fs & ft & format1X=0x0 {\n fd[0,32] = (fs:4 f* ft:4) f- fr:4; # must do floating arithmetic in 32 bit\n}\n:msub.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x05 & fmt5 & fd & fr & fs & ft &\n\t\t\t\tformat1X=0x1 & fdD & fsD & ftD & frD {\n fdD = (fsD f* ftD) f- frD;\n}\n:msub.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x05 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 11rr rrrt tttt ssss sddd dd11 0fff\n:nmadd.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x06 & fmt5 & fd & fr & fs & ft & format1X=0x0 {\n fd[0,32] = f- (fs:4 f* ft:4) f+ fr:4; # must do floating arithmetic in 32 bit\n}\n:nmadd.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x06 & fmt5 & fd & fr & fs & ft &\n\t\t\t\tformat1X=0x1 & fdD & fsD & ftD & frD {\n fdD = f- ((fsD f* ftD) f+ frD);\n}\n:nmadd.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x06 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 11rr rrrt tttt ssss sddd dd11 1fff\n:nmsub.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x07 & fmt5 & fd & fr & fs & ft & format1X=0x0 {\n fd[0,32] = f- (fs:4 f* ft:4) f- fr:4; # must do floating arithmetic in 32 bit\n}\n:nmsub.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x07 & fmt5 & fd & fr & fs & ft &\n\t\t\t\tformat1X=0x1 & fdD & fsD & ftD & frD {\n fdD = f- ((fsD f* ftD) f- frD);\n}\n:nmsub.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x07 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 11bb bbbi iiii hhhh h000 0000 1111\n:prefx hint, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero5=0x0 & fct=0x0F & hint & INDEX_BASE {\n prefetch(INDEX_BASE, hint:1); \n}\n# 0100 11bb bbbi iiii ssss s000 0000 1001\n:sdxc1 fs, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero5=0x0 & fct=0x09 & fs & fsD & INDEX_BASE {\n *[ram]:8 INDEX_BASE = fsD;\n}\n# 0100 11bb bbbi iiii ssss s000 0000 1101\n:suxc1 fs, INDEX_BASE is $(AMODE) & REL6=0 & prime=19 & fct=13 & INDEX_BASE & fs & fsD {\n INDEX_BASE = INDEX_BASE & 0xfffffffffffffff0; \n *[ram]:8 INDEX_BASE = fsD; \n}\n# 0100 11bb bbbi iiii ssss s000 0000 1000\n:swxc1 fs, INDEX_BASE is $(AMODE) & REL6=0 & prime=19 & INDEX_BASE & fs & fd=0 & fct=8 {\n *[ram]:4 INDEX_BASE = fs:$(SIZETO4); \n}\n####\n#\n# Pre-6 semantics\n#\n####\n# 0100 0101 000c cc00 iiii iiii iiii iiii\n:bc1f Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=0 & tf=0 & Rel16 {\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n delayslot(1);\n if (tmp != 0) goto inst_next;\n goto Rel16;\n}\n:bc1f cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=0 & tf=0 & Rel16 {\n # tmp:1 = getFpCondition(cc:1); # Note that other cc conditions are not implemented\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n delayslot(1);\n if (tmp != 0) goto inst_next;\n goto Rel16;\n}\n# 0100 0101 000c cc10 iiii iiii iiii iiii\n:bc1fl Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=1 & tf=0 & Rel16 {\n tmp:1 = fcsr[23,1];\n if (tmp != 0) goto inst_next;\n delayslot(1);\n goto Rel16;\n}\n:bc1fl cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=1 & tf=0 & Rel16 {\n # tmp:1 = getFpCondition(cc:1);\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n if (tmp != 0) goto inst_next;\n delayslot(1);\n goto Rel16;\n}\n\n# 0100 0101 000c cc01 iiii iiii iiii iiii\n:bc1t Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=0 & tf=1 & Rel16 {\n tmp:1 = fcsr[23,1];\n delayslot(1);\n if (tmp == 0) goto inst_next;\n goto Rel16;\n}\n:bc1t cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=0 & tf=1 & Rel16 {\n # tmp:1 = getFpCondition(cc:1);\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n delayslot(1);\n if (tmp == 0) goto inst_next;\n goto Rel16;\n}\n# 0100 0101 000c cc11 iiii iiii iiii iiii\n:bc1tl Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=1 & tf=1 & Rel16 {\n tmp:1 = fcsr[23,1];\n if (tmp == 0) goto inst_next;\n delayslot(1);\n goto Rel16;\n}\n:bc1tl cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=1 & tf=1 & Rel16 {\n # tmp:1 = getFpCondition(cc:1);\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n if (tmp == 0) goto inst_next;\n delayslot(1);\n goto Rel16;\n}\n\n# The pre-release 6 floating point compare instructions, c.condn.S or .D, set the fcsr bit 23\n\nmacro trapIfNaN(x1, x2) { }\nmacro trapIfSNaN(x1, x2) { }\n\n:c.f.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=48 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = 0; # Always false\n}\n:c.f.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=48 & fmt1 & format=0x11 & fs & ft & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = 0;\n}\n:c.f.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=48 & fmt1 & fs & ft & format=0x16 & ftD & fsD & fdD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.un.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=49 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = nan(fs:4) || nan(ft:4); # True if operands are NaN\n}\n:c.un.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=49 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = nan(fsD) || nan(ftD);\n}\n:c.un.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=49 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.eq.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=50 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f== ft:4);\n}\n:c.eq.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=50 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = (fsD f== ftD);\n}\n:c.eq.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=50 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ueq.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=51 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f== ft:4);\n}\n:c.ueq.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=51 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = (fsD f== ftD);\n}\n:c.ueq.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=51 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.olt.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=52 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f< ft:4);\n}\n:c.olt.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=52 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = (fsD f< ftD);\n}\n:c.olt.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=52 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ult.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=53 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f< ft:4) || nan(fs:4) || nan(ft:4); # Less than or NaN\n}\n:c.ult.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=53 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = (fsD f< ftD) || nan(fsD) || nan(ftD);\n}\n:c.ult.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=53 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ole.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=54 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f<= ft:4);\n}\n:c.ole.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=54 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = (fsD f<= ftD);\n}\n:c.ole.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=54 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ule.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=55 & fmt1 & format=0x10 & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f<= ft:4) || nan(fs:4) || nan(ft:4); # Less than or equal or NaN\n}\n:c.ule.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=55 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fcsr[23,1] = (fsD f<= ftD) || nan(fsD) || nan(ftD);\n}\n:c.ule.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=55 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n# The pre-release 6 floating point compare instructions that trap if either operand is NaN (either QNaN or SNaN)\n\n:c.sf.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=56 & fmt1 & fs & ft & format=0x10 {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = 0; # Always false\n}\n:c.sf.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=56 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = 0;\n}\n:c.sf.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=56 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ngle.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=57 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = nan(fs:4) || nan(ft:4);\n}\n:c.ngle.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=57 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = nan(fsD) || nan(ftD);\n}\n:c.ngle.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=57 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.seq.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=58 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f== ft:4);\n}\n:c.seq.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=58 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = (fsD f== ftD);\n}\n:c.seq.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=58 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ngl.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=59 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f== ft:4) || nan(fs:4) || nan(ft:4);\n}\n:c.ngl.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=59 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = (fsD f== ftD) || nan(fsD) || nan(ftD);\n}\n:c.ngl.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=59 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.lt.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=60 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f< ft:4);\n}\n:c.lt.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=60 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = (fsD f< ftD);\n}\n:c.lt.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=60 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.nge.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=61 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f< ft:4) || nan(fs:4) || nan(ft:4);\n}\n:c.nge.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=61 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = (fsD f< ftD) || nan(fsD) || nan(ftD);\n}\n:c.nge.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=61 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.le.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=62 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f<= ft:4);\n}\n:c.le.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=62 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = (fsD f<= ftD);\n}\n:c.le.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=62 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n:c.ngt.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=63 & fmt1 & format=0x10 & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fcsr[23,1] = (fs:4 f<= ft:4) || nan(fs:4) || nan(ft:4); # Less than or equal or NaN\n}\n:c.ngt.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=63 & fmt1 & fs & ft & format=0x11 & fsD & ftD {\n trapIfNaN(fsD, ftD);\n fcsr[23,1] = (fsD f<= ftD) || nan(fsD) || nan(ftD);\n}\n:c.ngt.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=63 & fmt1 & fs & ft & format=0x16 & ftD & fsD {\n fcsr[23,1] = mipsFloatPS(fsD, ftD);\n}\n\n# 0000 00ss sssc cc00 dddd d000 0000 0001\n:movf RD, RSsrc, cc is $(AMODE) & REL6=0 & prime=0 & nd=0 & tf=0 & zero5=0 & fct=1 & RD & RSsrc & cc {\n # Move if FP condition flag is false\n tmp:1 = fcsr[23,1];\n if (tmp != 0) goto ;\n RD = RSsrc;\n \n}\n\n# 0100 01ff fffc cc00 ssss sddd dd01 0001\n:movf.S fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=0 & fct=17 & fmt1 & fd & fs & cc & format=0x10 {\n # Move if FP condition flag is false\n tmp:1 = fcsr[23,1];\n if (tmp != 0) goto ;\n fd[0,32] = fs:4;\n \n}\n:movf.D fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=0 & fct=17 & fmt1 & fd & fs & cc & format=0x11 & fdD & fsD {\n # Move if FP condition flag is false\n tmp:1 = fcsr[23,1];\n if (tmp != 0) goto ;\n fdD = fsD;\n \n}\n:movf.PS fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=0 & fct=17 & fmt1 & fd & fs & cc & format=0x16 & fsD & fdD {\n fdD = mipsFloatPS(fcsr[23,1], fsD);\n}\n\n# 0100 01ff ffft tttt ssss sddd dd01 0011\n:movn.S fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=19 & fmt1 & fd & fs & RTsrc & format=0x10 {\n if (RTsrc == 0) goto ;\n fd[0,32] = fs:4;\n \n}\n:movn.D fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=19 & fmt1 & fd & fs & RTsrc & format=0x11 & fdD & fsD {\n if (RTsrc == 0) goto ;\n fdD = fsD;\n \n}\n:movn.PS fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=19 & fmt1 & fd & fs & RTsrc & format=0x16 & fsD & fdD {\n fdD = mipsFloatPS(fcsr[23,1], fsD);\n}\n\n# 0000 00ss sssc cc01 dddd d000 0000 0001\n:movt RD, RSsrc, cc is $(AMODE) & REL6=0 & prime=0 & nd=0 & tf=1 & zero5=0 & fct=1 & RD & RSsrc & cc {\n # Move if FP condition flag is true\n tmp:1 = fcsr[23,1];\n if (tmp != 1) goto ;\n RD = RSsrc;\n \n}\n\n# 0100 01ff fffc cc01 ssss sddd dd01 0001\n:movt.S fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=1 & fct=17 & fmt1 & fd & fs & cc & format=0x10 {\n # Move if FP condition flag is true\n tmp:1 = fcsr[23,1];\n if (tmp != 1) goto ;\n fd[0,32] = fs:4;\n \n}\n:movt.D fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=1 & fct=17 & fmt1 & fd & fs & cc & format=0x11 & fdD & fsD {\n # Move if FP condition flag is true\n tmp:1 = fcsr[23,1];\n if (tmp != 1) goto ;\n fdD = fsD;\n \n}\n:movt.PS fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=1 & fct=17 & fmt1 & fd & fs & cc & format=0x16 & fsD & ftD & fdD {\n fdD = mipsFloatPS(fsD, ftD);\n}\n\n# 0100 01ff ffft tttt ssss sddd dd01 0010\n:movz.S fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=18 & fmt1 & fd & fs & RTsrc & format=0x10 {\n if (RTsrc != 0) goto ;\n fd[0,32] = fs:4;\n \n}\n:movz.D fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=18 & fmt1 & fd & fs & RTsrc & format=0x11 & fdD & fsD {\n if (RTsrc != 0) goto ;\n fdD = fsD;\n \n}\n:movz.PS fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=18 & fmt1 & fd & fs & RTsrc & format=0x16 & fsD & fdD {\n fdD = mipsFloatPS(RTsrc, fsD);\n}\n\n####\n#\n# Release 6 semantics\n#\n####\n:bc1eqz ft,Rel16\tis $(AMODE) & REL6=1 & prime=0x11 & format=0x09 & Rel16 & ft {\n # Branch if FPR ft LSB equals 0 (false) (This insn replaces bc1f)\n tmp:1 = ft[0,8] & 0x01; # Only need to check the LSB\n delayslot(1);\n if (tmp == 0x00) goto Rel16;\n}\n\n:bc1nez ft,Rel16 is $(AMODE) & REL6=1 & prime=0x11 & format=0x0d & Rel16 & ft & ftD {\n # Branch if FPR ft LSB equals 1 (true) (This insn replaces bc1t)\n tmp:1 = ft[0,8] & 0x01; # Only need to check the LSB\n delayslot(1);\n if (tmp == 0x01) goto Rel16;\n}\n\n:class.S fd,fs\tis $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & op=0x00 & fct=0x1b & fd & fs {\n # Set fd to the 10-bit mask that is the IEEE floating point class of the value in fs\n # Bit 0: signaling SNaN\n # Bit 1: quiet QNaN\n # Bit 2: negative infinity\n\n # Bit 3: negative normalized number\n # Bit 4: negative subnormal, ie denormalized\n # Bit 5: negative zero\n # Bit 6: positive infinity\n # Bit 7: positive normal\n # Bit 8: positive subnormal\n # Bit 9: positive zero\n # Bits 31-10 are set to 0\n\n tmp_fs:4 = fs:4; # Get just the 4 byte single floating point value\n tmp_exponent:4 = zext(tmp_fs[23,8]);\n tmp_fraction:4 = zext(tmp_fs[0,23]);\n tmp_sign:4 = zext(tmp_fs[31,1]);\n tmp_b1:4 = zext(tmp_fs[22,1]); # High order bit of fraction, used for NaN\n\n tmp_SNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0)); \n tmp_QNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01));\n tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0));\n tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff));\n tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0));\n tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff));\n tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n\n tmp_fd:4 = 0;\n tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) |\n\t\t(tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) |\n\t\t(tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9);\n\n fd = zext(tmp_fd);\n}\n\n:class.D fd,fs is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & op=0x00 & fct=0x1b & fd & fs & fdD & fsD {\n # Set fd to the 10-bit mask that is the IEEE floating point class of the value in fs\n # Bit 0: signaling SNaN\n # Bit 1: quiet QNaN\n # Bit 2: negative infinity\n # Bit 3: negative normalized number\n # Bit 4: negative subnormal, ie denormalized\n # Bit 5: negative zero\n # Bit 6: positive infinity\n # Bit 7: positive normal\n # Bit 8: positive subnormal\n # Bit 9: positive zero\n # Bits 31-10 are set to 0\n\n tmp_fs:8 = fsD;\n tmp_sign:4 = zext(tmp_fs[63,1]);\n tmp_exponent:4 = zext(tmp_fs[52,11]);\n tmp_fraction:8 = zext(tmp_fs[0,51]);\n tmp_b1:4 = zext(tmp_fs[51,1]); # High order bit of fraction, used for NaN\n\n tmp_SNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0));\n tmp_QNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01));\n tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0));\n tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff));\n tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0));\n tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff));\n tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n\n tmp_fd:4 = 0;\n tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) |\n (tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) |\n (tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9);\n\n fdD = zext(tmp_fd);\n}\n\n:sel.S fd,fs,ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & fct=0x10 & fd & fs & ft {\n # Floating point select, if LSB of fd == 1 then fd = ft, else fd = fs\n # Note that the data in the FPRs might be 32-bit ints, ie there's no interpretation of the values\n tmp:1 = (fd[0,1] == 0x01);\n fd = (zext(tmp) * ft) | (zext(tmp == 0x0) * fs);\n}\n:sel.D fd,fs,ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & fct=0x10 & fd & fs & ft & fdD & fsD & ftD {\n # Floating point select, if LSB of fd == 1 then fd = ft, else fd = fs\n # Note that the data in the FPRs might be 64-bit ints, ie there's no interpretation of the values\n tmp:1 = (fdD[0,1] == 0x01);\n fdD = (zext(tmp) * ftD) | (zext(tmp == 0x0) * fsD);\n}\n\n#\n# The R6 floating point compare cmp instruction is described on page 146 of the\n# MIPS64 Architecture Volume II ISA manual\n#\n# Note that when the condition is true the target FPR is set to all ones, and to 0 if false.\n# If the target is 32-bit and you have 64-bit FPRs, then setting the top word is optional\n#\n# Note that when the format is Single and you have 64-bit FPRS,\n# then you need to first pull out the 32-bit float word and then pass that to the correct p-code\n#\n# TBD: Note that when fct bits 5 and 4 (left most 2 bits) are 01 then the condition is negated\n#\n\n:cmp.af.S fd, fs, ft\tis $(AMODE) & REL6=1 & prime=0x11 & fct=0x00 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfSNaN(fs:4, ft:4); # Trap if either operand is a Signaling NaN\n fd = 0x0; # Always false\n}\n:cmp.af.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x00 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & ft & fsD & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = 0x0;\n}\n\n:cmp.un.S fd, fs, ft\tis $(AMODE) & REL6=1 & prime=0x11 & fct=0x01 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext((nan(fs:4) || nan(ft:4)) * 0xff); # True if operands are NaN\n}\n:cmp.un.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x01 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { \n trapIfSNaN(fsD, ftD);\n fdD = sext((nan(fsD) || nan(ftD)) * 0xff);\n}\n\n:cmp.or.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x11 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext( (!(nan(fs:4) || nan(ft:4))) * 0xff); # The negated predicate of \"c.un\"\n}\n:cmp.or.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x11 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext( (!(nan(fsD) || nan(ftD))) * 0xff);\n}\n\n:cmp.eq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x02 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext((fs:4 f== ft:4) * 0xff);\n}\n:cmp.eq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x02 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext((fsD f== ftD) * 0xff);\n}\n\n:cmp.une.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x12 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # The negated predicate of cmp.eq\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext((fs:4 f!= ft:4) * 0xff);\n}\n:cmp.une.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x12 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext((fsD f!= ftD) * 0xff);\n}\n\n:cmp.ueq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x03 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # NaN or equal\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) ) * 0xff);\n}\n:cmp.ueq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x03 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f== ftD) ) * 0xff);\n}\n\n:cmp.ne.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x13 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # The negated predicate of cmp.ueq\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext( (!( ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) ))) * 0xff);\n}\n:cmp.ne.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x13 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext( (!( ( nan(fsD) || nan(ftD) || (fsD f== ftD) ))) * 0xff);\n}\n\n:cmp.lt.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x04 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext((fs:4 f< ft:4) * 0xff);\n}\n:cmp.lt.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x04 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext((fsD f< ftD) * 0xff);\n}\n\n:cmp.ult.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x05 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # NaN or less than\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f< ft:4) ) * 0xff);\n}\n:cmp.ult.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x05 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f< ftD) ) * 0xff);\n}\n\n:cmp.le.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x06 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # Less than or equal\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext((fs:4 f<= ft:4) * 0xff);\n}\n:cmp.le.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x06 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext((fsD f<= ftD) * 0xff);\n}\n\n:cmp.ule.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x07 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # NaN or less than or equal\n trapIfSNaN(fs:4, ft:4);\n fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f<= ft:4) ) * 0xff);\n}\n:cmp.ule.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x07 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfSNaN(fsD, ftD);\n fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f<= ftD) ) * 0xff);\n}\n\n# The cmp instructions that signal (ie trap) if either of the operands are NaN\n\n:cmp.saf.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x08 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd = 0x0; # Always false\n}\n:cmp.saf.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x08 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = 0x0;\n}\n\n:cmp.sun.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x09 & bit5=0 & fmt6 & format=0x14 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext((nan(fs:4) || nan(ft:4)) * 0xff);\n}\n:cmp.sun.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x09 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext((nan(fsD) || nan(ftD)) * 0xff);\n}\n\n:cmp.sor.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x19 & bit5=0 & fmt6 & format=0x14 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext( (!(nan(fs:4) || nan(ft:4))) * 0xff); # negate of cmp.sun\n}\n:cmp.sor.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x19 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( (!(nan(fsD) || nan(ftD))) * 0xff);\n}\n\n:cmp.seq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0a & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext((fs:4 f== ft:4) * 0xff);\n}\n:cmp.seq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0a & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext((fsD f== ftD) * 0xff);\n}\n\n:cmp.sune.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1a & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext((fs:4 f!= ft:4) * 0xff);\n}\n:cmp.sune.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1a & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext((fsD f!= ftD) * 0xff);\n}\n\n:cmp.sueq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0b & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n # NaN or equal\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) ) * 0xff);\n}\n:cmp.sueq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0b & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f== ftD) ) * 0xff);\n}\n\n:cmp.sne.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1b & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4); # negate of cmp.sueq\n fd[0,32] = sext( (! ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) )) * 0xff);\n}\n:cmp.sne.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1b & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( (! ( nan(fsD) || nan(ftD) || (fsD f== ftD) )) * 0xff);\n}\n\n:cmp.slt.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0c & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext( (fs:4 f< ft:4) * 0xff);\n}\n:cmp.slt.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0c & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( (fsD f< ftD) * 0xff);\n}\n\n:cmp.sult.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0d & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f< ft:4) ) * 0xff);\n}\n:cmp.sult.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0d & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f< ftD) ) * 0xff);\n}\n\n:cmp.sle.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0e & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext( (fs:4 f<= ft:4) * 0xff);\n}\n:cmp.sle.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0e & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( (fsD f<= ftD) * 0xff);\n}\n\n:cmp.sule.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0f & bit5=0 & fmt6 & format=0x14 & fd & fs & ft {\n trapIfNaN(fs:4, ft:4);\n fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f<= ft:4) ) * 0xff);\n}\n:cmp.sule.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0f & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD {\n trapIfNaN(fsD, ftD);\n fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f<= ftD) ) * 0xff);\n}\n\n:rint.S fd, fs\t\tis $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & fct=0x1a {\n # floating point round to integral floating point\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n fs_tmp:4 = fs:4;\n if (rm_tmp == 0) goto ;\n fd[0,32] = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fd[0,32] = round(fs_tmp); # round returns a float\n \n}\n\n:rint.D fd, fs is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & fsD & fdD & fct=0x1a {\n # floating point round to integral floating point\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n if (rm_tmp == 0) goto ;\n fdD = floor(fsD); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fdD = round(fsD); # round returns a float\n \n}\n\n:min.S fd, fs, ft\tis $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1c {\n # set floating point fd to the min of fs and ft, TBD special case for NaN\n tmp_cond:1 = fs:4 f< ft:4;\n fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) );\n}\n:min.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1c \n\t\t\t\t& fsD & fdD & ftD {\n tmp_cond:1 = fsD f< ftD;\n fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) );\n}\n\n:max.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1d {\n # set floating point fd to the max of fs and ft, TBD special case for NaN\n tmp_cond:1 = fs:4 f> ft:4;\n fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) );\n}\n:max.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1d\n & fsD & fdD & ftD {\n tmp_cond:1 = fsD f> ftD;\n fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) );\n}\n\n:mina.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1e {\n # set floating point fd to the min of absolute values of fs and ft, TBD special case for NaN\n tmp_cond:1 = abs(fs:4) f< abs(ft:4);\n fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) );\n}\n:mina.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1e \n & fsD & fdD & ftD {\n tmp_cond:1 = abs(fsD) f< abs(ftD);\n fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) );\n}\n\n:maxa.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1f {\n # set floating point fd to the max of absolute values of fs and ft, TBD special case for NaN\n tmp_cond:1 = abs(fs:4) f> abs(ft:4);\n fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) );\n}\n:maxa.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1f\n & fsD & fdD & ftD {\n tmp_cond:1 = abs(fsD) f> abs(ftD);\n fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) );\n}\n\n:maddf.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x18 {\n # set floating point fd = fd + fs * ft, using 32-bit floating values\n fd[0,32] = fd:4 f+ (fs:4 f* ft:4);\n}\n:maddf.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x18\n & fsD & fdD & ftD {\n fdD = fdD f+ (fsD f* ftD);\n}\n\n:msubf.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x19 {\n # set floating point fd = fd - fs * ft, using 32-bit floating values\n fd[0,32] = fd:4 f- (fs:4 f* ft:4);\n}\n:msubf.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x19 \n & fsD & fdD & ftD {\n fdD = fdD f- (fsD f* ftD);\n}\n\n:seleqz.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x14 {\n # Set floating point register fd to fs if ft[0] == 0, else if == 1 then set fd to 0, TBD special case for NaN\n # Note that the description of these select instructions in the MIPS manual does not properly use the C conditional operator\n fd = zext(fs * zext(ft[0,1] == 0));\n}\n:seleqz.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x14\n & fsD & fdD & ftD {\n fdD = zext(fsD * zext(ftD[0,1] == 0));\n}\n\n:selnez.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x17 {\n # set floating point register fd to fs if ft[0] == 1, else if == 0 then set fd to 0, TBD special case for NaN\n fd = zext(fs * zext(ft[0,1] == 1));\n}\n:selnez.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x17\n & fsD & fdD & ftD {\n fdD = zext(fsD * zext(ftD[0,1] == 1));\n}\n" }, { "path": "pypcode/processors/MIPS/data/languages/mipsmicro.sinc", "content": "define token micinstr (16)\n mic_op=(10,15)\n mic_code=(0,9)\n mic_code4=(0,3)\n mic_code4s=(0,3) signed\n mic_code4r6=(6,9)\n mic_off4r6=(4,7)\n\n mic_base0=(0,4)\n mic_base4=(4,6)\n mic_index=(5,9)\n \n mic_rd7=(7,9)\n mic_rd7lo=(7,9)\n mic_rd1=(1,3)\n mic_rd1lo=(7,9)\n\n mic_rs0=(0,2)\n mic_rs0lo=(0,2) \n mic_rs1=(1,3)\n mic_rs1lo=(1,3)\n mic_rs4=(4,6)\n mic_rs4lo=(4,6)\n mic_rs7=(7,9)\n mic_rs7lo=(7,9)\n \n mic_rt3=(3,5)\n mic_rt3lo=(3,5)\n mic_rt4=(4,6)\n mic_rt4lo=(4,6)\n mic_rt7=(7,9)\n mic_rt7lo=(7,9)\n \n \n\n mic_rd32_5=(5,9)\n mic_rd32_5lo=(5,9)\n mic_rd32_11=(11,15)\n mic_rd32_0=(0,4)\n\n mic_rs32_0=(0,4)\n mic_rs32_0a=(0,4)\n mic_rs32_0b=(0,4)\n mic_rs32_0lo=(0,4)\n mic_rs32_hw=(0,4)\n mic_rs32_5=(5,9)\n\n mic_rt32_0=(0,4)\n mic_rt32_5=(5,9)\n mic_rt32_5a=(5,9)\n mic_rt32_5lo=(5,9)\n \n mic_fd=(0,4)\n mic_fdD=(0,4)\n mic_fs=(0,4)\n mic_fsD=(0,4)\n mic_fs_5=(5,9)\n mic_fsD_5=(5,9)\n mic_ft_0=(0,4)\n mic_ft_5=(5,9)\n mic_ftD_5=(5,9) \n mic_ct=(0,4)\n\n mic_stype=(0,4)\n mic_funci=(5,9)\n mic_cop5=(5,9)\n mic_impl=(0,4)\n mic_pcf=(0,4)\n mic_pcz=(3,4)\n mic_cc=(2,4)\n mic_pcf2=(2,4)\n mic_cp2z=(0,1)\n mic_rlist=(5,9)\n mic_imm10=(0,9)\n mic_imm9=(1,9)\n mic_imm9s=(1,9) signed\n mic_imm9e=(0,8)\n mic_imm7=(0,6)\n mic_imm6=(1,6)\n mic_imm6r6=(0,5)\n mic_imm5=(0,4)\n mic_imm5s=(0,4) signed\n mic_imm5r6=(5,9)\n mic_imm4=(1,4)\n mic_imm4s=(1,4) signed\n mic_imm3=(1,3)\n mic_imm03=(0,3)\n mic_imm02=(0,2)\n mic_imm01=(0,1)\n mic_bit0=(0,0)\n mic_bit01=(0,1)\n mic_bit3=(3,3)\n mic_bit10=(10,10)\n mic_sub2=(5,9)\n mic_csub=(6,9)\n mic_csubr6=(0,3)\n mic_jalr=(5,9)\n mic_jalrr6=(0,4)\n mic_off12=(0,11)\n mic_off10=(0,9)\n mic_soff10=(0,9) signed\n mic_off7=(0,6)\n mic_soff7=(0,6) signed\n mic_off4=(0,3)\n mic_break=(4,9)\n mic_breakr6=(0,5)\n mic_ja32=(6,15)\n mic_list=(4,5)\n mic_listr6=(8,9)\n mic_cofun=(3,15)\n mic_encrs=(1,3)\n mic_encrt=(4,6)\n mic_encrd=(7,9)\n mic_encre=(7,9)\n mic_encrt2=(7,9)\n mic_sa=(1,3)\n;\n\ndefine token micinstrb (16)\n micb_imm16=(0,15)\n micb_simm16=(0,15) signed\n micb_poolax=(0,5)\n micb_poolfx=(0,5)\n micb_bp=(9,10)\n micb_bp8=(8,10)\n micb_flt6=(6,12)\n micb_fmt14=(14,14)\n micb_fmt=(13,14)\n micb_fmt8=(8,9)\n micb_fmt9=(9,10)\n micb_fmt10=(10,11)\n micb_spec=(0,5)\n micb_axf=(6,15)\n micb_axf2=(0,9)\n micb_axf3=(6,11)\n micb_code10=(6,15)\n micb_asel=(6,8)\n micb_fxf=(6,15)\n micb_fxf2=(0,10)\n micb_fxf3=(0,7)\n micb_fxf4=(6,13)\n micb_fxf5=(0,8)\n micb_bit10=(10,10)\n micb_bit11=(11,11)\n micb_bit12=(12,12)\n micb_bit15=(15,15)\n micb_cc=(13,15)\n \n micb_rd32=(11,15)\n micb_rd32lo=(11,15)\n micb_rs32=(6,10)\n \n micb_fd=(11,15)\n micb_fdD=(11,15)\n \n micb_fr=(6,10)\n micb_frD=(6,10)\n \n micb_rx=(6,10)\n micb_pos=(6,10)\n micb_size=(11,15)\n micb_sa=(11,15)\n micb_sa9=(9,10)\n micb_hint=(11,15)\n micb_offset12=(0,11)\n micb_offset12s=(0,11) signed\n micb_offset11=(0,10)\n micb_offset11s=(0,10) signed\n micb_offset9=(0,8)\n micb_offset9s=(0,8) signed\n micb_func12=(12,15)\n micb_trap=(6,11)\n micb_cond=(6,9)\n micb_cond2=(6,10)\n micb_sub9=(9,11)\n micb_cop=(0,2)\n micb_cofun=(3,15)\n micb_z14=(14,15)\n micb_z12=(12,15)\n micb_z11=(11,12)\n micb_z9=(9,10)\n micb_z68=(6,8)\n micb_z67=(6,7)\n micb_sel=(11,13)\n micb_cpf=(6,10)\n;\n\nattach variables [ mic_rd7 mic_rd1 mic_rt4 mic_rs1 mic_rs7 mic_rs0 mic_rs4 mic_rt3 mic_rt7 mic_base4 ]\n [ s0 s1 v0 v1 a0 a1 a2 a3 ];\n\nattach variables [ mic_rs32_hw ] [\n\tHW_CPUNUM\tHW_SYNCI_STEP\tHW_CC\t\tHW_CCRe\n\tHW_PerfCtr\tHW_XNP\t\t\tHW_RES6\t\tHW_RES7\n\tHW_RES8\t\tHW_RES9\t\t\tHW_RES10\tHW_RES11\n\tHW_RES12\tHW_RES13\t\tHW_RES14\tHW_RES15\n\tHW_RES16\tHW_RES17\t\tHW_RES18\tHW_RES19\n\tHW_RES20\tHW_RES21\t\tHW_RES22\tHW_RES23\n\tHW_RES24\tHW_RES25\t\tHW_RES26\tHW_RES27\n\tHW_RES28\tHW_ULR\t\t\tHW_RESIM30\tHW_RESIM31\n];\n\n@ifdef MIPS64\nattach variables [ mic_rd7lo mic_rd1lo mic_rt4lo mic_rs1lo mic_rs7lo mic_rs0lo mic_rs4lo mic_rt3lo mic_rt7lo ]\n\t\t\t\t [ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ];\n\nattach variables [ mic_rs32_0lo mic_rt32_5lo micb_rd32lo mic_rd32_5lo ext_32_rs1lo] [ \n zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo\n t0_lo t1_lo t2_lo t3_lo t4_lo t5_lo t6_lo t7_lo\n s0_lo s1_lo s2_lo s3_lo s4_lo s5_lo s6_lo s7_lo\n t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo \n];\n@else\nattach variables [ mic_rd7lo mic_rd1lo mic_rt4lo mic_rs1lo mic_rs7lo mic_rs0lo mic_rs4lo mic_rt3lo mic_rt7lo ]\n\t\t\t\t [ s0 s1 v0 v1 a0 a1 a2 a3 ];\n\nattach variables [ mic_rs32_0lo mic_rt32_5lo micb_rd32lo mic_rd32_5lo ext_32_rs1lo] [ \n zero at v0 v1 a0 a1 a2 a3\n t0 t1 t2 t3 t4 t5 t6 t7\n s0 s1 s2 s3 s4 s5 s6 s7\n t8 t9 k0 k1 gp sp s8 ra \n];\n@endif\n\n\nattach variables [ mic_encrs mic_encrt ext_16_rs]\n\t\t\t\t [ zero s1 v0 v1 s0 s2 s3 s4 ];\n\t\t\t\t \nattach variables [ mic_encrt2]\n\t\t\t\t [ zero s1 v0 v1 a0 a1 a2 a3 ];\n\t\t\t\t \nattach variables [ mic_encrd]\n\t\t\t\t [ a1 a1 a2 a0 a0 a0 a0 a0 ];\n\t\t\t\t \nattach variables [ mic_encre]\n\t\t\t\t [ a2 a3 a3 s5 s6 a1 a2 a3 ];\n\nattach variables [ mic_rd32_5 mic_rs32_0 mic_rs32_5 mic_rt32_5 mic_rd32_11 mic_rd32_0 ext_32_base micb_rd32 ext_32_rd micb_rs32 mic_base0 ext_32_rs1 mic_index] [ \n zero at v0 v1 a0 a1 a2 a3\n t0 t1 t2 t3 t4 t5 t6 t7\n s0 s1 s2 s3 s4 s5 s6 s7\n t8 t9 k0 k1 gp sp s8 ra \n];\n\nattach variables [ mic_fs mic_ft_5 micb_fd micb_fr mic_fs_5 mic_fd] [ \n f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 \n];\n\n@if FREGSIZE == \"4\"\n# For 64-bit floating point Double instruction operands need to bond two 32-bit FPRs\nattach variables [ mic_fsD mic_ftD_5 micb_fdD micb_frD mic_fsD_5 mic_fdD] [\n f0_1 _ f2_3 _ f4_5 _ f6_7 _\n f8_9 _ f10_11 _ f12_13 _ f14_15 _\n f16_17 _ f18_19 _ f20_21 _ f22_23 _\n f24_25 _ f26_27 _ f28_29 _ f30_31 _\n];\n@else # FREGSIZE == \"8\"\nattach variables [ mic_fsD mic_ftD_5 micb_fdD micb_frD mic_fsD_5 mic_fdD] [\n f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31\n];\n@endif\n\nattach names [ ext_t4_name][\n\t_\t\t\"s0\" \"s0-s1\" \"s0-s2\" \n\t\"s0-s3\"\t\"s0-s4\"\t\"s0-s5\" \"s0-s6\" \n\t\"s0-s7\"\t\"s0-s8\" _\t\t_\n\t_\t\t_\t\t_\t\t_\n];\n\nRD5L: mic_rd32_5\tis mic_rd32_5 & mic_rd32_5lo\t{ export mic_rd32_5lo; }\nRD5L: mic_rd32_5\tis mic_rd32_5 & mic_rd32_5lo=0\t{ tmp:4 = 0; export tmp; }\n\nRD7R1: mic_rd7\t\tis mic_rd7 & REL6=0\t\t\t\t{ export mic_rd7; }\nRD7R1: mic_rd1\t\tis mic_rd1 & REL6=1\t\t\t\t{ export mic_rd1; }\n\nRSEXTL: ext_32_rs1\tis ext_32_rs1 & ext_32_rs1lo\t{ export ext_32_rs1lo; }\nRSEXTL: ext_32_rs1\tis ext_32_rs1 & ext_32_rs1lo=0\t{ tmp:4 = 0; export tmp; }\n\nRS0L: mic_rs32_0\tis mic_rs32_0 & mic_rs32_0lo\t{ export mic_rs32_0lo; }\nRS0L: mic_rs32_0\tis mic_rs32_0 & mic_rs32_0lo=0\t{ tmp:4 = 0; export tmp; }\nRS4L: mic_rs4\t\tis mic_rs4 & mic_rs4lo\t\t\t{ export mic_rs4lo; }\n\nRS0R4: mic_rs0\t\tis mic_rs0 & REL6=0\t\t\t\t{ export mic_rs0; }\nRS0R4: mic_rs4\t\tis mic_rs4 & REL6=1\t\t\t\t{ export mic_rs4; }\nRS0R5: mic_rs32_0\tis mic_rs32_0 & REL6=0\t\t\t{ export mic_rs32_0; }\nRS0R5: mic_rs32_0\tis mic_rs32_0 & mic_rs32_0=0 & REL6=0\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\nRS0R5: mic_rs32_5\tis mic_rs32_5 & REL6=1\t\t\t{ export mic_rs32_5; }\nRS0R5: mic_rs32_5\tis mic_rs32_5 & mic_rs32_5=0 & REL6=1\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\n\nRS1R7L: mic_rs1\t\tis mic_rs1 & mic_rs1lo & REL6=0 { export mic_rs1lo; }\nRS1R7L: mic_rs7\t\tis mic_rs7 & mic_rs7lo & REL6=1 { export mic_rs7lo; }\n\nRT4L: mic_rt4\t\tis mic_rt4 & mic_rt4lo \t\t\t{ export mic_rt4lo; }\nRT5L: mic_rt32_5\tis mic_rt32_5 & mic_rt32_5lo\t{ export mic_rt32_5lo; }\nRT5L: mic_rt32_5\tis mic_rt32_5 & mic_rt32_5lo=0\t{ tmp:4 = 0; export tmp; }\n\n\nRT3R7: mic_rt3\t\tis mic_rt3 & REL6=0\t\t\t\t{ export mic_rt3; }\nRT3R7: mic_rt7\t\tis mic_rt7 & REL6=1\t\t\t\t{ export mic_rt7; }\n\nRST7R5: mic_rs7\t\tis mic_rs7 & REL6=0 \t\t\t{ export mic_rs7; }\nRST7R5: mic_rt32_5\tis mic_rt32_5 & REL6=1 \t\t\t{ export mic_rt32_5; }\nRST7R5: mic_rt32_5\tis mic_rt32_5 & mic_rt32_5=0 & REL6=1 \t\t{ tmp:$(REGSIZE) = 0; export tmp; }\n\n\nRT5RD5: ext_32_rd\tis ext_32_rd & REL6=0\t\t\t{ export ext_32_rd; }\nRT5RD5: ext_32_rd\tis ext_32_rd & ext_32_rd=0 & REL6=0\t\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\nRT5RD5: micb_rd32\tis micb_rd32 & REL6=1\t\t\t{ export micb_rd32; }\nRT5RD5: micb_rd32\tis micb_rd32 & micb_rd32=0 & REL6=1\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\n\nRS0RT5: mic_rs32_0\tis mic_rs32_0 & REL6=0\t\t\t{ export mic_rs32_0; }\nRS0RT5: mic_rs32_0\tis mic_rs32_0 & mic_rs32_0=0 & REL6=0\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\nRS0RT5: mic_rt32_5\tis mic_rt32_5 & REL6=1\t\t\t{ export mic_rt32_5; }\nRS0RT5: mic_rt32_5\tis mic_rt32_5 & mic_rt32_5=0 & REL6=1\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\n\nENCRS: mic_encrs\tis mic_encrs & REL6=0\t\t\t{ export mic_encrs; }\nENCRS: mic_encrs\tis mic_encrs & mic_encrs=0 & REL6=0\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\nENCRS: ext_16_rs\tis ext_16_rs & REL6=1\t\t\t{ export ext_16_rs; }\nENCRS: ext_16_rs\tis ext_16_rs & ext_16_rs=0 & REL6=1\t\t{ tmp:$(REGSIZE) = 0; export tmp; }\n\nAbs26_mic1: reloc \tis ext_32_code & micb_imm16 [ reloc=((inst_start+4) $and 0xfffffffff8000000)+2*(micb_imm16 | (ext_32_code << 16)); ] { export *:$(ADDRSIZE) reloc; } \nAbs26_mic2: reloc \tis ext_32_code & micb_imm16 [ reloc=((inst_start+4) $and 0xfffffffff0000000)+4*(micb_imm16 | (ext_32_code << 16)); ] { export *:$(ADDRSIZE) reloc; } \nRel26_mic: reloc\t\t\t\tis micb_imm16 [ reloc=inst_start+4+2*((ext_32_codes << 16) | micb_imm16); ] { export *:$(ADDRSIZE) reloc; } \nRel21_mic: reloc\t\t\t\tis micb_imm16 [ reloc=inst_start+4+2*((ext_32_imm5s << 16) | micb_imm16); ] { export *:$(ADDRSIZE) reloc; } \nRel16_mic: reloc \tis micb_simm16 [ reloc=inst_start+4+2*micb_simm16; ] { export *:$(ADDRSIZE) reloc; } \nRel10_mic: reloc \tis mic_soff10 [ reloc=inst_start+2+2*mic_soff10; ] { export *:$(ADDRSIZE) reloc; } \nRel7_mic: reloc \t\tis mic_soff7 [ reloc=inst_start+2+2*mic_soff7; ] { export *:$(ADDRSIZE) reloc; }\n\nEXT_CODE3: val\t\t\t\t\tis mic_imm3=0 [ext_off16_s = 0x0001; val = ext_off16_s; ] { export *[const]:2 val; }\nEXT_CODE3: val\t\t\t\t\tis mic_imm3=7 [ext_off16_s = 0xFFFF; val = ext_off16_s; ] { export *[const]:2 val; }\nEXT_CODE3: val\t\t\t\t\tis mic_imm3 [ext_off16_s = mic_imm3 << 2; val = ext_off16_s; ] { export *[const]:2 val; }\n\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x0 [ext_off16_u = 0x80; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x1 [ext_off16_u = 0x1; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x2 [ext_off16_u = 0x2; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x3 [ext_off16_u = 0x3; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x4 [ext_off16_u = 0x4; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x5 [ext_off16_u = 0x7; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x6 [ext_off16_u = 0x8; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x7 [ext_off16_u = 0xf; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x8 [ext_off16_u = 0x10; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0x9 [ext_off16_u = 0x1f; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0xa [ext_off16_u = 0x20; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0xb [ext_off16_u = 0x3f; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0xc [ext_off16_u = 0x40; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0xd [ext_off16_u = 0xff; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0xe [ext_off16_u = 0x8000; val = ext_off16_u; ] { export *[const]:2 val; }\nEXT_CODE4A: val\t\t\t\t\tis mic_imm03=0xf [ext_off16_u = 0xffff; val = ext_off16_u; ] { export *[const]:2 val; }\n\nEXT_CODE4B: val\t\t\t\t\tis mic_code4=0xf [ ext_off16_s = 0xffff; val = ext_off16_s; ] { export *[const]:2 val; }\nEXT_CODE4B: val\t\t\t\t\tis mic_code4\t [ ext_off16_s = mic_code4; val = ext_off16_s; ] { export *[const]:2 val; }\n\nEXT_CODE4C: val\t\t\t\t\tis mic_code4 [ val = mic_code4 << 1; ] { export *[const]:2 val; }\n\nEXT_CODE4D: val\t\t\t\t\tis mic_code4s [ val = mic_code4s << 2; ] { export *[const]:2 val; }\n\nEXT_CODE4E: val\t\t\t\t\tis mic_code4 & REL6=0 [ val = mic_code4 << 2; ] { export *[const]:2 val; }\nEXT_CODE4E: val\t\t\t\t\tis mic_off4r6 & REL6=1 [ val = mic_off4r6 << 2; ] { export *[const]:2 val; }\nEXT_CODE5R6: val\t\t\t\tis mic_imm5r6 [ val = mic_imm5r6 << 2; ] { export *[const]:2 val; }\n\n\nEXT_CODE5: val\t\t\t\t\tis mic_imm5 [ val = mic_imm5 << 2; ] { export *[const]:2 val; }\n\nEXT_CODE7: val\t\t\t\t\tis mic_imm7=0x7f [ ext_off16_s = 0xffff; val = ext_off16_s; ] { export *[const]:2 val; }\nEXT_CODE7: val\t\t\t\t\tis mic_imm7\t\t [ ext_off16_s = mic_imm7; val = ext_off16_s; ] { export *[const]:2 val; }\n\nEXT_CODE7A: val\t\t\t\t\tis mic_soff7 [ val = mic_soff7 << 2; ] { export *[const]:2 val; }\n\nEXT_CODE9: val\t\t\t\t\tis mic_imm9=0x000 [ext_off16_s = 0x0100; val = ext_off16_s << 2; ] { export *[const]:2 val; }\nEXT_CODE9: val\t\t\t\t\tis mic_imm9=0x001 [ext_off16_s = 0x0101; val = ext_off16_s << 2; ] { export *[const]:2 val; }\nEXT_CODE9: val\t\t\t\t\tis mic_imm9=0x1fe [ext_off16_s = 0xfefe; val = ext_off16_s << 2; ] { export *[const]:2 val; }\nEXT_CODE9: val\t\t\t\t\tis mic_imm9=0x1ff [ext_off16_s = 0xfeff; val = ext_off16_s << 2; ] { export *[const]:2 val; }\nEXT_CODE9: val\t\t\t\t\tis mic_imm9s [ val = mic_imm9s << 2; ] { export *[const]:2 val; }\n\nEXT_CODE9E: val\t\t\t\t\tis micb_offset9s [ val = micb_offset9s << 0; ] { export *[const]:2 val; }\nEXT_CODE12: val\t\t\t\t\tis micb_offset12s [ val = micb_offset12s << 0; ] { export *[const]:2 val; }\n\nEXT_CODE16: val\t\t\t\t\tis micb_code10 [ val = (ext_32_imm6 << 10) | micb_code10; ] { export *[const]:2 val; }\n\nEXT_MS16: val\t\t\t\t\tis micb_simm16 [ val = micb_simm16 << 0; ] { export *[const]:2 val; }\nEXT_MS18: val\t\t\t\t\tis micb_imm16 [ val = (ext_32_imm2s << 19) | (micb_imm16 << 3); ] { export *[const]:4 val; }\n\nEXT_MS19: val\t\t\t\t\tis micb_imm16 [ val = (ext_32_imm3s << 18) | (micb_imm16 << 2); ] { export *[const]:4 val; }\n\nEXT_MS32: val\t\t\t\t\tis micb_simm16 [ val = micb_simm16 << 16; ] { export *[const]:4 val; }\nEXT_MS48: val\t\t\t\t\tis micb_simm16 [ val = micb_simm16 << 32; ] { export *[const]:8 val; }\nEXT_MS64: val\t\t\t\t\tis micb_simm16 [ val = micb_simm16 << 48; ] { export *[const]:8 val; }\n\nEXT_MSPC: val\t\t\t\t\tis ext_32_imm3s & micb_imm16 & REL6=1 [val = (ext_32_imm3s << 18) | (micb_imm16 << 2); ] { export *[const]:4 val; }\n\nEXT_MSPC: val\t\t\t\t\tis ext_32_addims & micb_imm16 & REL6=0 [val = (ext_32_addims << 18) | (micb_imm16 << 2); ] { export *[const]:4 val; }\n\nEXT_MU23: val\t\t\t\t\tis ext_32_code & micb_cofun [val = (ext_32_code << 13) | micb_cofun; ] { export *[const]:4 val; }\n\nEXT_MU6: val\t\t\t\t\tis mic_imm6 [val = mic_imm6 << 2; ] { export *[const]:1 val; }\n\nEXT_SA: val\t\t\t\t\t\tis mic_sa=0 [ val = 8; ] { export *[const]:1 val; }\nEXT_SA: val\t\t\t\t\t\tis mic_sa [ val = mic_sa << 0; ] {export *[const]:1 val; }\n\nEXT_SA9: val\t\t\t\t\tis micb_sa9 [ val = micb_sa9+1; ] { export *[const]:1 val; }\n\nDIDISP:\t\t\t\t\t\t\tis mic_rs32_0=0 {}\nDIDISP: mic_rs32_0\t\t\t\tis mic_rs32_0 {}\n\nRTIMP:\t\t\t\t\t\t\tis mic_rt32_5=31 {}\nRTIMP: mic_rt32_5\", \"\t\t\tis mic_rt32_5 {}\n\nSIZEP: val\t\t\t\t\t\tis micb_size [ val = micb_size+1; ] { export *[const]:1 val; }\nSIZEPLG: val\t\t\t\t\tis micb_size [ val = micb_size+1+32; ] { export *[const]:1 val; }\nSIZEQ: val\t\t\t\t\t\tis micb_size & micb_pos [ val = micb_size + 1 - micb_pos; ] { export *[const]:1 val; }\nSIZEQLG: val\t\t\t\t\tis micb_size & micb_pos [ val = micb_size + 1 - micb_pos + 32; ] { export *[const]:1 val; }\nPOSHI: val\t\t\t\t\t\tis micb_pos [ val = micb_pos+32; ] { export *[const]:1 val; }\n\nCPSEL:\t\t\t\t\t\t\tis micb_sel=0 {}\nCPSEL: \", \"micb_sel\t\t\t\tis micb_sel {}\n\nSTYPE:\t\t\t\t\t\t\tis mic_stype=0 {}\nSTYPE: val\t\t\t\t\t\tis mic_stype [ val = mic_stype << 0; ] {}\n\nSDB16: mic_code4\t\t\t\tis mic_code4 & REL6=0\t{ export *[const]:1 mic_code4; }\nSDB16: mic_code4r6\t\t\t\tis mic_code4r6 & REL6=1 { export *[const]:1 mic_code4r6; }\n\nSA32: val\t\t\t\t\t\tis micb_sa [ val = micb_sa+32; ] { export *[const]:1 val; }\n\nCOP2CC:\t\t\t\t\t\t\tis mic_cc=0 {}\nCOP2CC: val\", \"\t\t\t\t\tis mic_cc [ val = mic_cc << 0; ] {}\n\nLOAD_S8:\t\t\t\t\t\tis ext_t4=8 {}\nLOAD_S8:\t\t\t\t\t\tis ext_t4 { MemSrcCast(s8,tsp); tsp = tsp+$(REGSIZE); }\n\nLOAD_S7:\t\t\t\t\t\tis ext_t4=7 {}\nLOAD_S7:\t\t\t\t\t\tis LOAD_S8 { MemSrcCast(s7,tsp); tsp = tsp+$(REGSIZE); build LOAD_S8; }\n\nLOAD_S6:\t\t\t\t\t\tis ext_t4=6 {}\nLOAD_S6:\t\t\t\t\t\tis LOAD_S7 { MemSrcCast(s6,tsp); tsp = tsp+$(REGSIZE); build LOAD_S7; }\n\nLOAD_S5:\t\t\t\t\t\tis ext_t4=5 {}\nLOAD_S5:\t\t\t\t\t\tis LOAD_S6 {MemSrcCast(s5,tsp); tsp = tsp+$(REGSIZE); build LOAD_S6; }\n\nLOAD_S4:\t\t\t\t\t\tis ext_t4=4 {}\nLOAD_S4:\t\t\t\t\t\tis LOAD_S5 { MemSrcCast(s4,tsp); tsp = tsp+$(REGSIZE); build LOAD_S5; }\n\nLOAD_S3:\t\t\t\t\t\tis ext_t4=3 {}\nLOAD_S3:\t\t\t\t\t\tis LOAD_S4 { MemSrcCast(s3,tsp); tsp = tsp+$(REGSIZE); build LOAD_S4; }\n\nLOAD_S2:\t\t\t\t\t\tis ext_t4=2 {}\nLOAD_S2:\t\t\t\t\t\tis LOAD_S3 { MemSrcCast(s2,tsp); tsp = tsp+$(REGSIZE); build LOAD_S3; }\n\nLOAD_S1:\t\t\t\t\t\tis ext_t4=1 {}\nLOAD_S1:\t\t\t\t\t\tis LOAD_S2 { MemSrcCast(s1,tsp); tsp = tsp+$(REGSIZE); build LOAD_S2; }\n\nLOAD_S0:\t\t\t\t\t\tis ext_t4=0 {}\nLOAD_S0:\t\t\t\t\t\tis LOAD_S1 { MemSrcCast(s0,tsp); tsp = tsp+$(REGSIZE); build LOAD_S1; }\n\nLOAD_SREG:\t\t\t\t\t\tis ext_t4=0 {}\nLOAD_SREG: ext_t4_name\",\"\t\tis LOAD_S0 & ext_t4_name { build LOAD_S0; }\n\nLOAD_RA:\t\t\t\t\t\tis ext_tra=0 {}\nLOAD_RA: \"ra,\"\t\t\t\t\tis ext_tra=1 { MemSrcCast(ra,tsp); tsp = tsp+$(REGSIZE); }\n\nLOAD_TOP: LOAD_SREG^LOAD_RA EXT_CODE12(ext_32_base)\tis LOAD_SREG & LOAD_RA & ext_32_base & ext_32_rlist & EXT_CODE12 [ext_t4 = ext_32_rlist $and 0xf; ext_tra = ext_32_rlist >> 4; ] {\n\tbuild EXT_CODE12;\n\t\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttsp = ext_32_base + tmp;\n\t\n\tbuild LOAD_SREG;\n\tbuild LOAD_RA;\n}\nLOAD_TOP16: LOAD_SREG^ra,EXT_CODE4E(sp) is mic_list & REL6=0 & LOAD_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_list+1;] {\n\tbuild EXT_CODE4E;\n\n\ttmp:$(REGSIZE) = zext(EXT_CODE4E);\n\ttsp = sp + tmp;\n\t\n\tbuild LOAD_SREG;\n\tMemSrcCast(ra,tsp);\n}\nLOAD_TOP16: LOAD_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & LOAD_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_listr6+1;] {\n\tbuild EXT_CODE4E;\n\n\ttmp:$(REGSIZE) = zext(EXT_CODE4E);\n\ttsp = sp + tmp;\n\t\n\tbuild LOAD_SREG;\n\tMemSrcCast(ra,tsp);\n}\n\n\nSTORE_S8:\t\t\t\t\t\tis ext_t4=8 {}\nSTORE_S8:\t\t\t\t\t\tis ext_t4 { MemDestCast(tsp,s8); tsp = tsp+$(REGSIZE); }\n\nSTORE_S7:\t\t\t\t\t\tis ext_t4=7 {}\nSTORE_S7:\t\t\t\t\t\tis STORE_S8 { MemDestCast(tsp,s7); tsp = tsp+$(REGSIZE); build STORE_S8; }\n\nSTORE_S6:\t\t\t\t\t\tis ext_t4=6 {}\nSTORE_S6:\t\t\t\t\t\tis STORE_S7 { MemDestCast(tsp,s6); tsp = tsp+$(REGSIZE); build STORE_S7; }\n\nSTORE_S5:\t\t\t\t\t\tis ext_t4=5 {}\nSTORE_S5:\t\t\t\t\t\tis STORE_S6 { MemDestCast(tsp,s5); tsp = tsp+$(REGSIZE); build STORE_S6; }\n\nSTORE_S4:\t\t\t\t\t\tis ext_t4=4 {}\nSTORE_S4:\t\t\t\t\t\tis STORE_S5 { MemDestCast(tsp,s4); tsp = tsp+$(REGSIZE); build STORE_S5; }\n\nSTORE_S3:\t\t\t\t\t\tis ext_t4=3 {}\nSTORE_S3:\t\t\t\t\t\tis STORE_S4 { MemDestCast(tsp,s3); tsp = tsp+$(REGSIZE); build STORE_S4; }\n\nSTORE_S2:\t\t\t\t\t\tis ext_t4=2 {}\nSTORE_S2:\t\t\t\t\t\tis STORE_S3 { MemDestCast(tsp,s2); tsp = tsp+$(REGSIZE); build STORE_S3; }\n\nSTORE_S1:\t\t\t\t\t\tis ext_t4=1 {}\nSTORE_S1:\t\t\t\t\t\tis STORE_S2 { MemDestCast(tsp,s1); tsp = tsp+$(REGSIZE); build STORE_S2; }\n\nSTORE_S0:\t\t\t\t\t\tis ext_t4=0 {}\nSTORE_S0:\t\t\t\t\t\tis STORE_S1 { MemDestCast(tsp,s0); tsp = tsp+$(REGSIZE); build STORE_S1; }\n\nSTORE_SREG:\t\t\t\t\t\tis ext_t4=0 {}\nSTORE_SREG: ext_t4_name\",\"\t\tis STORE_S0 & ext_t4_name { build STORE_S0; }\n\nSTORE_RA:\t\t\t\t\t\tis ext_tra=0 {}\nSTORE_RA: \"ra,\"\t\t\t\t\tis ext_tra=1 { MemDestCast(tsp,ra); tsp = tsp+$(REGSIZE); }\n\nSTORE_TOP: STORE_SREG^STORE_RA EXT_CODE12(ext_32_base)\tis STORE_SREG & STORE_RA & ext_32_base & ext_32_rlist & EXT_CODE12 [ext_t4 = ext_32_rlist $and 0xf; ext_tra = ext_32_rlist >> 4; ] {\n\tbuild EXT_CODE12;\n\t\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttsp = ext_32_base + tmp;\n\t\n\tbuild STORE_SREG;\n\tbuild STORE_RA;\n}\nSTORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_list & REL6=0 & STORE_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_list+1;] {\n\tbuild EXT_CODE4E;\n\n\ttmp:$(REGSIZE) = zext(EXT_CODE4E);\n\ttsp = sp + tmp;\n\t\n\tbuild STORE_SREG;\n\tMemDestCast(tsp,ra);\n}\nSTORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & STORE_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_listr6+1;] {\n\tbuild EXT_CODE4E;\n\n\ttmp:$(REGSIZE) = zext(EXT_CODE4E);\n\ttsp = sp + tmp;\n\t\n\tbuild STORE_SREG;\n\tMemDestCast(tsp,ra);\n}\n\n####\n#\n# Common semantics\n#\n####\n\n:abs.S mic_ft_5, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b0001101 {\n fs_tmp:4 = mic_fs:4;\n fd_tmp:4 = abs(fs_tmp);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:abs.D mic_ft_5, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b0001101 {\n mic_ftD_5 = abs(mic_fsD);\n}\n\n:add micb_rd32, RS0L, RT5L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0100010000 & micb_bit10=0 & micb_rd32 {\n\ttmps:8 = zext(RS0L);\n\ttmpt:8 = zext(RT5L);\n\ttmps = tmps + tmpt;\n\ttmpt = tmps >> 32;\n\tif (tmpt != 0) goto ;\n\tmicb_rd32 = sext(tmps:4);\n\t\t\n}\n\n:add.S micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b00110000 {\n fd_tmp:4 = mic_fs:4 f+ mic_ft_5:4;\n micb_fd = zext(fd_tmp);\n}\n\n:add.D micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b00110000 {\n micb_fdD = mic_fsD f+ mic_ftD_5;\n}\n\n:addiu mic_rt32_5, RS0L, EXT_MS16\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001100 & RS0L & mic_rt32_5 ; EXT_MS16 {\n\ttmp:4 = sext(EXT_MS16);\n\ttmp = tmp + RS0L;\n\tmic_rt32_5 = sext(tmp);\n}\n\n:addiupc RST7R5, EXT_MSPC\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011110 & RST7R5 & mic_imm7 & (REL6=0 | (REL6=1 & mic_pcz=0)); EXT_MSPC [ ext_32_addim=mic_imm7; ] {\n\ttmpa:$(REGSIZE) = inst_start & ~3;\n\ttmpb:$(REGSIZE) = sext(EXT_MSPC);\n\tRST7R5 = tmpa + tmpb;\n}\n\n:addiur1sp mic_rd7, EXT_MU6\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011011 & mic_bit0=1 & mic_rd7 & EXT_MU6 {\n@if REGSIZE == \"4\"\n\ttmp:4 = sp + zext(EXT_MU6);\n@else\n\ttmp:4 = sp_lo + zext(EXT_MU6);\n@endif\n\tmic_rd7 = sext(tmp);\n}\n\n:addiur2 mic_rd7, RS4L, EXT_CODE3\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011011 & mic_bit0=0 & RS4L & mic_rd7 & EXT_CODE3 {\n\ttmp:4 = RS4L + sext(EXT_CODE3);\n\tmic_rd7 = sext(tmp);\n}\n\n:addiusp EXT_CODE9\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010011 & mic_bit0=1 & EXT_CODE9 {\n@if REGSIZE == \"4\"\n\ttmp:4 = sp + sext(EXT_CODE9);\n@else\n\ttmp:4 = sp_lo + sext(EXT_CODE9);\n@endif\n\tsp = sext(tmp);\n}\n\n:addius5 RD5L, mic_imm4s\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010011 & mic_bit0=0 & mic_rd32_5 & RD5L & mic_imm4s {\n\ttmp:4 = mic_imm4s;\n\ttmp = tmp + RD5L;\n\tmic_rd32_5 = sext(tmp);\n}\n\n:addu micb_rd32, RS0L, RT5L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0101010000 & micb_bit10=0 & micb_rd32 {\n\ttmp:4 = RS0L + RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:addu16 RD7R1, RT4L, RS1R7L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000001 & mic_bit0=0 & RD7R1 & RT4L & RS1R7L {\n\ttmp:4 = RT4L + RS1R7L;\n\tRD7R1 = sext(tmp);\n}\n\n:and micb_rd32, mic_rs32_0, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1001010000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 & mic_rt32_5;\n}\n\n:and16 RT3R7, RS0R4\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0010 & REL6=0) | (mic_csubr6=0b0001 & REL6=1)) {\n\tRT3R7 = RT3R7 & RS0R4;\n}\n\n:andi mic_rt32_5, mic_rs32_0, micb_imm16\tis ISA_MODE=1 & RELP=0 & mic_op=0b110100 & mic_rs32_0 & mic_rt32_5 ; micb_imm16 {\n\ttmp:$(REGSIZE) = micb_imm16;\n\tmic_rt32_5 = mic_rs32_0 & tmp;\n}\n\n:andi16\tmic_rd7, mic_rs4, EXT_CODE4A \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001011 & mic_rd7 & mic_rs4 & EXT_CODE4A {\n\tmic_rd7 = mic_rs4 & zext(EXT_CODE4A);\n}\n\n:break\t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 ; micb_poolax=0b000111 {\n\tbreak();\n}\n\n:break16\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & SDB16 & ((mic_break=0b101000 & REL6=0) | (mic_breakr6=0b011011 & REL6=1)) {\n\tbreak();\n}\n\n:cachee mic_cop5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_cop5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b011 & EXT_CODE9E {\n\tcacheOp();\n}\n\n:ceil.l.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b01001100 {\n fd_tmp:4 = ceil(mic_fs:4); \n mic_ftD_5 = trunc(fd_tmp); \n}\n\n:ceil.l.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b01001100 {\n fsD_tmp:8 = ceil(mic_fsD); \n mic_ftD_5 = trunc(fsD_tmp); \n}\n\n:ceil.w.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b01101100 {\n fs_ceil_tmp:4 = ceil(mic_fs:4); \n fd_tmp:4 = trunc(fs_ceil_tmp);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:ceil.w.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b01101100 {\n fs_tmp:8 = ceil(mic_fsD); \n fd_tmp:4 = trunc(fs_tmp); \n mic_ft_5 = zext(fd_tmp);\n}\n\n:cfc1 mic_rt32_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0001000000 {\n mic_rt32_5 = getCopControlWord( 1:1, mic_fs:4 );\n}\n\n:cfc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolfx=0b111100 & micb_axf=0b1100110100 {\n\ttmpa:1 = 2;\n\ttmpb:1 = mic_impl;\n\tmic_rt32_5 = getCopControlWord(tmpa,tmpb);\n}\n\n:clo mic_rt32_5, RS0L\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0100101100 {\n mic_rt32_5 = lzcount( ~RS0L );\n}\n\n:clz mic_rt32_5, RS0L\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0101101100 {\n mic_rt32_5 = lzcount( RS0L );\n}\n\n:cop2 EXT_MU23\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code ; micb_cop=0b010 & EXT_MU23 [ ext_32_code=mic_code; ] {\n\ttmp:1 = 2;\n\tcopFunction(tmp,EXT_MU23);\n}\n\n:ctc1 RT5L, mic_fs\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & RT5L & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0001100000 {\n setCopControlWord( 1:1, mic_fs:4, RT5L );\n}\n\n:ctc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b1101110100 {\n\ttmpa:1 = 2;\n\ttmpb:1 = mic_impl;\n\tsetCopControlWord(tmpa,tmpb,mic_rt32_5);\t\n}\n\n:cvt.d.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b1001101 {\n fs_tmp:4 = mic_fs:4;\n mic_ftD_5 = float2float(fs_tmp);\n}\n\n:cvt.d.W mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b1001101 {\n fs_tmp:4 = mic_fs:4;\n mic_ftD_5 = int2float(fs_tmp);\n}\n\n:cvt.d.L mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b1001101 {\n mic_ftD_5 = int2float(mic_fsD);\n}\n\n:cvt.l.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00000100 {\n rm_tmp:1 = fcsr[0,2]; \n fs_tmp:4 = mic_fs:4;\n fs_cvt_tmp:4 = 0;\n if (rm_tmp == 0) goto ;\n fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fs_cvt_tmp = round(fs_tmp); # round returns a float\n \n mic_ftD_5 = trunc(fs_cvt_tmp);\n}\n\n:cvt.l.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00000100 {\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n if (rm_tmp == 0) goto ;\n fd_tmp:8 = floor(mic_fsD); # RM is 1, no rounding\n goto ;\n \n fd_tmp = round(mic_fsD);\n \n mic_ftD_5 = trunc(fd_tmp);\n}\n\n:cvt.s.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b1101101 {\n fd_tmp:4 = float2float(mic_fsD);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:cvt.s.W mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b1101101 {\n fs_tmp:4 = mic_fs:4;\n fd_tmp:4 = int2float(fs_tmp);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:cvt.s.L mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b1101101 {\n fd_tmp:4 = int2float(mic_fsD);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:cvt.w.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00100100 {\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n fs_tmp:4 = mic_fs:4;\n fs_cvt_tmp:4 = 0;\n if (rm_tmp == 0) goto ;\n fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fs_cvt_tmp = round(fs_tmp); # round returns a float\n \n fd_tmp:4 = trunc(fs_cvt_tmp);\n mic_ft_5 = zext(fd_tmp); # trunc returns an integer\n}\n\n:cvt.w.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00100100 {\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n if (rm_tmp == 0) goto ;\n fs_tmp:8 = floor(mic_fsD); # RM is 1, no rounding\n goto ;\n \n fs_tmp = round(mic_fsD);\n \n fd_tmp:4 = trunc(fs_tmp);\n mic_ft_5 = zext(fd_tmp); # In 64-bit FPUs, fd might be 64-bits, so need to set top half to something\n}\n\n:deret \t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b1110001101 {}\n\n:di DIDISP \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5=0 & DIDISP ; micb_poolax=0b111100 & micb_axf=0b0100011101 {\n\tdisableInterrupts(DIDISP);\n}\n\n:div.S micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b11110000 {\n fs_tmp:4 = mic_fs:4; # need to only get the single float 32-bit (mic_fs might be 64-bits)\n ft_tmp:4 = mic_ft_5:4;\n fd_tmp:4 = fs_tmp f/ ft_tmp;\n micb_fd = zext(fd_tmp);\n}\n\n:div.D micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b11110000 {\n micb_fdD = mic_fsD f/ mic_ftD_5;\n}\n\n:ehb \t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0b0000000000 ; micb_poolax=0 & micb_rx=0 & micb_rd32=3 {\n\thazzard();\n}\n\n:ei DIDISP \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5=0 & DIDISP ; micb_poolax=0b111100 & micb_axf=0b0101011101 {\n\tenableInterrupts(DIDISP);\n}\n\n:eret \t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b1111001101 {}\n\n:eretnc \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=1 ; micb_poolax=0b111100 & micb_axf=0b1111001101 {}\n\n:ext mic_rt32_5, RS0L, micb_pos, SIZEP\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b101100 & micb_pos & SIZEP {\n\ttmpa:4 = 0xFFFFFFFF;\n\ttmpa = tmpa >> (32 - SIZEP);\n\ttmpb:4 = RS0L;\n\ttmpb = (tmpb >> micb_pos) & tmpa;\n\tmic_rt32_5 = sext(tmpb);\n}\n\n:floor.l.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00001100 {\n fs_tmp:4 = mic_fs:4;\n fd_tmp:4 = floor(fs_tmp); # returns a float\n mic_ftD_5 = trunc(fd_tmp); # converts float to int\n}\n\n:floor.l.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00001100 {\n fsD_tmp:8 = floor(mic_fsD);\n mic_ftD_5 = trunc(fsD_tmp);\n}\n\n:floor.w.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00101100 {\n fs_tmp:4 = mic_fs:4;\n fd_tmp:4 = floor(fs_tmp); # returns a float\n mic_ft_5 = trunc(fd_tmp); # converts float to int\n}\n\n:floor.w.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00101100 {\n fs_tmp:8 = floor(mic_fsD);\n fd_tmp:4 = trunc(fs_tmp);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:ins RT5L, RS0L, micb_pos, SIZEQ\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L & RT5L ; micb_poolax=0b001100 & micb_pos & SIZEQ {\n\ttmpa:4 = 0xFFFFFFFF;\n\ttmpa = tmpa >> (32 - SIZEQ);\n\ttmpb:4 = RS0L & tmpa;\n\ttmpa = tmpa << micb_pos;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << micb_pos;\n\tRT5L = (RT5L & tmpa) | tmpb;\n\tmic_rt32_5 = sext(RT5L);\n}\n\n:lb mic_rt32_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000111 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:1 tmpa); \n}\n\n:lbe mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b100 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:1 tmpa); \n}\n\n:lbu mic_rt32_5, EXT_MS16(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000101 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = zext(*[ram]:1 tmpa); \n}\n\n:lbue mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = zext(*[ram]:1 tmpa); \n}\n\n:lbu16 mic_rt7, EXT_CODE4B(mic_base4)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000010 & mic_rt7 & mic_base4 & EXT_CODE4B {\n\ttmp:$(REGSIZE) = sext(EXT_CODE4B);\n\ttmp = tmp + mic_base4;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt7 = zext(*[ram]:1 tmpa); \n}\n\n:ldc1 mic_ft_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101111 & mic_base0 & mic_ft_5 & mic_ftD_5; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_ftD_5 = *[ram]:8 tmpa;\n}\n\n:ldc2 mic_rt32_5, EXT_CODE12(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0010 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tsetCopReg(2:1,mic_rt32_5,*[ram]:8 tmpa);\n}\n\n:lh mic_rt32_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001111 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:2 tmpa); \n}\n\n:lhe mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b101 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:2 tmpa); \n}\n\n:lhu mic_rt32_5, EXT_MS16(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001101 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = zext(*[ram]:2 tmpa); \n}\n\n:lhue mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b001 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = zext(*[ram]:2 tmpa); \n}\n\n:lhu16 mic_rt7, EXT_CODE4C(mic_base4)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001010 & mic_rt7 & mic_base4 & EXT_CODE4C {\n\ttmp:$(REGSIZE) = sext(EXT_CODE4C);\n\ttmp = tmp + mic_base4;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt7 = zext(*[ram]:2 tmpa); \n}\n\n:li16 mic_rd7, EXT_CODE7\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111011 & mic_rd7 & EXT_CODE7 {\n\tmic_rd7 = sext(EXT_CODE7);\n}\n\n:ll mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0011 & micb_sub9=0 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa);\n lockload(tmp);\n}\n\n:lle mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b110 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa);\n lockload(tmp);\n}\n\n:lui RS0RT5, micb_imm16\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & RS0RT5 & ((mic_op=0b010000 & mic_sub2=0b01101 & REL6=0) | (mic_op=0b000100 & mic_rs32_0=0 & REL6=1)); micb_imm16 {\n\ttmp:4 = micb_imm16;\n\ttmp = tmp << 16;\n\tRS0RT5 = sext(tmp);\n}\n\n:lw mic_rt32_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111111 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa); \n}\n\n:lwe mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b111 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa); \n}\n\n:lw16 mic_rt7, EXT_CODE4D(mic_base4) \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011010 & mic_rt7 & mic_base4 & EXT_CODE4D {\n\ttmp:$(REGSIZE) = sext(EXT_CODE4D);\n\ttmp = tmp + mic_base4;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt7 = sext(*[ram]:4 tmpa); \n}\n\n:lwm16 LOAD_TOP16\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & LOAD_TOP16 & ((mic_csub=0b0100 & REL6=0) | (mic_csubr6=0b0010 & REL6=1)) { \n\tbuild LOAD_TOP16; \n}\n\n:lwm32 LOAD_TOP\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_base0 & mic_rlist ; micb_func12=0b0101 & LOAD_TOP [ ext_32_basea=mic_base0; ext_32_rlist=mic_rlist; ] { \n\tbuild LOAD_TOP; \n}\n\n:lwc1 mic_ft_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100111 & mic_base0 & mic_ft_5 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_ft_5 = sext( *[ram]:4 tmpa);\n}\n\n:lwc2 mic_rt32_5, EXT_CODE12(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0000 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tsetCopReg(2:1,mic_rt32_5,*[ram]:4 tmpa);\n}\n\n:lwp mic_rd32_5, EXT_CODE12(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rd32_5 & mic_base0 & ext_32_rd ; micb_func12=0b0001 & EXT_CODE12 [ext_32_rdset = mic_rd32_5+1;] {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tmic_rd32_5 = sext( *[ram]:4 tmpa);\n\ttmp = tmp + 4;\n\tValCast(tmpa,tmp);\n\text_32_rd = sext( *[ram]:4 tmpa);\n}\n\n:lwgp mic_rt7, EXT_CODE7A(gp)\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011001 & mic_rt7 & gp & EXT_CODE7A {\n\ttmp:$(REGSIZE) = sext(EXT_CODE7A);\n\ttmp = tmp + gp;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt7 = sext( *[ram]:4 tmpa);\n}\n\n:lwsp mic_rt32_5, EXT_CODE5(sp)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010010 & mic_rt32_5 & sp & EXT_CODE5 {\n\ttmp:$(REGSIZE) = zext(EXT_CODE5);\n\ttmp = tmp + sp;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext( *[ram]:4 tmpa);\n}\n\n:lwxs micb_rd32, mic_index(mic_base0) \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_index & mic_base0 ; micb_bit10=0 & micb_rd32 & ((micb_axf2=0b0100011000 & REL6=0) | (micb_axf2=0b0100000000 & REL6=1)) {\n\ttmp:$(REGSIZE) = mic_base0 + (mic_index << 2);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n micb_rd32 = sext( *[ram]:4 tmpa);\n}\n\n:mfc0 mic_rt32_5, mic_rs32_0, CPSEL\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b00011 & micb_poolax=0b111100 & CPSEL {\n\tmic_rt32_5 = getCopReg(0:1,mic_rs32_0,CPSEL);\n}\n\n:mfc1 mic_rt32_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0010000000 {\n mic_rt32_5 = sext(mic_fs:4);\n}\n\n:mfc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b0100110100 {\n\tmic_rt32_5 = getCopReg(2:1,mic_impl:1);\n}\n\n:mfhc0 mic_rt32_5, mic_rs32_0, CPSEL\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b00011 & micb_poolax=0b110100 & CPSEL {\n\tmic_rt32_5 = getCopRegH(0:1,mic_rs32_0,CPSEL);\n}\n\n:mfhc1 mic_rt32_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0011000000 {\n\ttmp:4 = mic_fsD[32,32];\n\tmic_rt32_5 = sext(tmp);\n}\n\n:mfhc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b1000110100 {\n\tmic_rt32_5 = getCopRegH(2:1,mic_impl:1);\n}\n\n:mov.S mic_ft_5, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b0000001 {\n mic_ft_5 = zext(mic_fs:4);\n}\n\n:mov.D mic_ft_5, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b0000001 {\n mic_ftD_5 = mic_fsD;\n}\n\n:move16 mic_rd32_5, mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000011 & mic_rd32_5 & mic_rs32_0 {\n\tmic_rd32_5 = mic_rs32_0;\n}\n\n# The docs are not clear if this format is pre and/or post R6.\n:movep mic_encrd, mic_encre, ENCRS, mic_encrt is ISA_MODE=1 & RELP=0 & mic_op=0b100001 & mic_bit0=0 & mic_encrd & mic_encre & ENCRS & mic_encrt & mic_bit3 & mic_bit01 [ext_16_rshi=mic_bit3; ext_16_rslo=mic_bit01;] {\n\tmic_encrd = ENCRS;\n\tmic_encre = mic_encrt;\n}\n\n:mtc0 mic_rt32_5, mic_rs32_0, CPSEL\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b01011 & micb_poolax=0b111100 & CPSEL {\n\tsetCopReg(0:1,mic_rs32_0,mic_rt32_5,CPSEL);\n}\n\n:mtc1 RT5L, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & RT5L & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0010100000 {\n\tmic_fs[0,32] = RT5L;\n}\n\n:mtc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b0101110100 {\n\tsetCopReg(2:1,mic_rt32_5,mic_impl:1);\n}\n\n:mthc0 mic_rt32_5, mic_rs32_0, CPSEL\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b01011 & micb_poolax=0b110100 & CPSEL {\n\tsetCopRegH(0:1,mic_rs32_0,mic_rt32_5,CPSEL);\n}\n\n:mthc1 RT5L, mic_fs\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & RT5L & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0011100000 {\n\tmic_fsD[32,32] = RT5L;\n}\n\n:mthc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b1001110100 {\n\tsetCopRegH(2:1,mic_rt32_5,mic_impl:1);\n}\n\n:mul micb_rd32, RS0L, RT5L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_rd32 & micb_bit10=0 & ((micb_axf2=0b1000010000 & REL6=0) | (micb_axf2=0b0000011000 & REL6=1)) {\n\ttmp:4 = RS0L * RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:mul.S micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b10110000 {\n fd_tmp:4 = mic_fs:4 f* mic_ft_5:4;\n micb_fd = zext(fd_tmp);\n}\n\n:mul.D micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b10110000 {\n micb_fdD = mic_fsD f* mic_ftD_5;\n}\n\n:neg.S mic_ft_5, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b0101101 {\n fs_tmp:4 = mic_fs:4;\n fd_tmp:4 = f- fs_tmp;\n mic_ft_5 = zext(fd_tmp);\n}\n\n:neg.D mic_ft_5, mic_fs\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b0101101 {\n mic_ftD_5 = f- mic_fsD;\n}\n\n# This is a special case of sll\n:nop \t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0=0 & mic_rt32_5=0 ; micb_sa=0 & micb_axf2=0b0000000000 & micb_bit10=0 {\n}\n\n:nor micb_rd32, mic_rs32_0, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1011010000 & micb_bit10=0 & micb_rd32 {\n micb_rd32 = ~(mic_rs32_0 | mic_rt32_5); \n}\n\n:not16 RT3R7, RS0R4\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0000 & REL6=0) | (mic_csubr6=0b0000 & REL6=1)) {\n\tRT3R7 = ~RS0R4;\n}\n\n:or micb_rd32, mic_rs32_0, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1010010000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 | mic_rt32_5;\n}\n\n:ori mic_rt32_5, mic_rs32_0, micb_imm16\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010100 & mic_rs32_0 & mic_rt32_5 ; micb_imm16 {\n\ttmp:$(REGSIZE) = micb_imm16;\n\tmic_rt32_5 = mic_rs32_0 | tmp;\n}\n\n:or16 RT3R7, RS0R4\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0011 & REL6=0) | (mic_csubr6=0b1001 & REL6=1)) {\n\tRT3R7 = RT3R7 | RS0R4;\n}\n\n:pause \t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0=0 & mic_rt32_5=0 ; micb_sa=0b00101 & micb_axf2=0b0000000000 & micb_bit10=0 {\n\twait();\n}\n\n:pref mic_cop5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_cop5 & mic_base0 ; micb_func12=0b0100 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = zext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\tprefetch(mic_cop5:1,tmp);\n}\n\n:prefe mic_cop5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_cop5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b010 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = zext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\tprefetch(mic_cop5:1,tmp);\n}\n\n:rdpgpr mic_rt32_5, mic_rs32_0 \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b1110000101 {\n\tmic_rt32_5 = getShadow(mic_rs32_0);\n}\n\n:recip.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b01001000 {\n fd_tmp:4 = 1:4 f/ mic_fs:4;\n mic_ft_5 = zext(fd_tmp);\n}\n\n:recip.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b01001000 {\n mic_ftD_5 = 1:8 f/ mic_fsD;\n}\n\n:rotr mic_rt32_5, RS0L, micb_sa\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0011000000 & micb_bit10=0 {\n\ttmpa:4 = RS0L >> micb_sa;\n\ttmpb:4 = RS0L << (32 - micb_sa);\n\ttmpa = tmpa | tmpb;\n\tmic_rt32_5 = sext(tmpa);\n}\n\n:rotrv micb_rd32, RT5L, RS0L\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_rd32 & micb_axf2=0b0011010000 & micb_bit10=0 {\n\ttmpr:1 = RS0L[0,5];\n\ttmpa:4 = RT5L >> tmpr;\n\ttmpb:4 = RT5L << (32 - tmpr);\n\ttmpa = tmpa | tmpb;\n\tmicb_rd32 = sext(tmpa);\n}\n\n:round.l.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b11001100 {\n fd_tmp:4 = round(mic_fs:4); # round returns a float of the same size are the arg\n mic_ftD_5 = trunc(fd_tmp); # trunc converts to any size integer\n}\n\n:round.l.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b11001100 {\n fsD_tmp:8 = round(mic_fsD);\n mic_ftD_5 = trunc(fsD_tmp);\n}\n\n:round.w.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b11101100 {\n fd_tmp:4 = round(mic_fs:4);\n mic_ft_5 = trunc(fd_tmp);\n}\n\n:round.w.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b11101100 {\n fdD_tmp:8 = round(mic_fsD); # round returns a float, not an int\n fd_tmp:4 = trunc(fdD_tmp); # We need only a 32-bit integer\n mic_ft_5 = zext(fd_tmp); # But fill the top half with 0s if we have a 64-bit FPU\n}\n\n:rsqrt.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00001000 {\n fd_tmp:4 = 1:4 f/ sqrt(mic_fs:4);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:rsqrt.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00001000 {\n mic_ftD_5 = 1:8 f/ sqrt( mic_fsD );\n}\n\n:sb RT5L, EXT_MS16(mic_base0)\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000110 & RT5L & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:1 tmpa = RT5L:1;\n}\n\n:sbe RT5L, EXT_CODE9E(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b100 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:1 tmpa = RT5L:1;\n}\n\n:sb16 mic_encrt2, mic_off4(mic_base4)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100010 & mic_encrt2 & mic_base4 & mic_off4 {\n\ttmp:$(REGSIZE) = mic_off4;\n\ttmp = tmp + mic_base4;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:1 tmpa = mic_encrt2:1;\n}\n\n:sc RT5L, EXT_CODE9E(mic_base0)\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1011 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n lockwrite(tmp);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L;\n\tRT5L = 1;\n}\n\n:sce RT5L, EXT_CODE9E(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b110 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L;\n lockwrite(tmp);\n}\n\n:sdbbp mic_code \t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code ; micb_poolax=0b111100 & micb_axf=0b1101101101 {\n\tbreak(mic_code:2);\n}\n\n:sdbbp16 SDB16\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100010 & SDB16 & ((mic_break=0b101100 & REL6=0) | (mic_breakr6=0b111011 & REL6=1)) {\n\tbreak(SDB16);\n}\n\n:sdc1 mic_ft_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101110 & mic_base0 & mic_ft_5 & mic_ftD_5 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:8 tmpa = mic_ftD_5;\n}\n\n:sdc2 mic_rt32_5, EXT_CODE12(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:8 tmpa = getCopReg(2:1,mic_rt32_5); \n}\n\n:seb mic_rt32_5, RS0L \t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0010101100 {\n\tmic_rt32_5 = sext(RS0L:1);\n}\n\n:seh mic_rt32_5, RS0L \t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0011101100 {\n\tmic_rt32_5 = sext(RS0L:2);\n}\n\n:sh RT5L, EXT_MS16(mic_base0)\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001110 & RT5L & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:2 tmpa = RT5L:2;\n}\n\n:she RT5L, EXT_CODE9E(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b101 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:2 tmpa = RT5L:2;\n}\n\n:sh16 mic_encrt2, EXT_CODE4C(mic_base4)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101010 & mic_encrt2 & mic_base4 & EXT_CODE4C {\n\ttmp:$(REGSIZE) = sext(EXT_CODE4C);\n\ttmp = tmp + mic_base4;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:2 tmpa = mic_encrt2:2;\n}\n\n:sll mic_rt32_5, RS0L, micb_sa\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0000000000 & micb_bit10=0 {\n\tmic_rt32_5 = sext(RS0L << micb_sa);\n}\n\n:sllv micb_rd32, RT5L, RS0L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0000010000 & micb_bit10=0 & micb_rd32 {\n\ttmp:1 = RS0L[0,5];\n\tmicb_rd32 = sext(RT5L << tmp);\n}\n\n:sll16 mic_rd7, RT4L, EXT_SA\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001001 & mic_bit0=0 & mic_rd7 & RT4L & EXT_SA {\n\tmic_rd7 = sext(RT4L << EXT_SA);\n}\n\n:slt micb_rd32, mic_rs32_0, mic_rt32_5 \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1101010000 & micb_bit10=0 & micb_rd32 {\n\ttmp:1 = mic_rs32_0 s< mic_rt32_5;\n\tmicb_rd32 = zext(tmp);\n}\n\n:slti mic_rt32_5, mic_rs32_0, EXT_MS16\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100100 & mic_rs32_0 & mic_rt32_5 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmpa:1 = mic_rs32_0 s< tmp;\n\tmic_rt32_5 = zext(tmpa);\n}\n\n:sltiu mic_rt32_5, mic_rs32_0, EXT_MS16\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101100 & mic_rs32_0 & mic_rt32_5 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmpa:1 = mic_rs32_0 < tmp;\n\tmic_rt32_5 = zext(tmpa);\n}\n\n:sltu micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1110010000 & micb_bit10=0 & micb_rd32 {\n\ttmp:1 = mic_rs32_0 < mic_rt32_5;\n\tmicb_rd32 = zext(tmp);\n}\n\n:sqrt.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00101000 {\n fd_tmp:4 = sqrt(mic_fs:4);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:sqrt.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00101000 {\n mic_ftD_5 = sqrt(mic_fsD);\n}\n\n:sra mic_rt32_5, RS0L, micb_sa\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0010000000 & micb_bit10=0 {\n\tmic_rt32_5 = sext(RS0L s>> micb_sa);\n}\n\n:srav micb_rd32, RT5L, RS0L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0010010000 & micb_bit10=0 & micb_rd32 {\n\ttmp:1 = RS0L[0,5];\n\tmicb_rd32 = sext(RT5L s>> tmp);\n}\n\n:srl mic_rt32_5, RS0L, micb_sa\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0001000000 & micb_bit10=0 {\n\tmic_rt32_5 = sext(RS0L >> micb_sa);\n}\n\n:srlv micb_rd32, RT5L, RS0L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0001010000 & micb_bit10=0 & micb_rd32 {\n\ttmp:1 = RS0L[0,5];\n\tmicb_rd32 = sext(RT5L >> tmp);\n}\n\n:srl16 mic_rd7, RT4L, EXT_SA\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001001 & mic_bit0=1 & mic_rd7 & RT4L & EXT_SA {\n\tmic_rd7 = sext(RT4L >> EXT_SA);\n}\n\n:ssnop \t\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0=0 & mic_rt32_5=0 ; micb_sa=1 & micb_axf2=0b0000000000 & micb_bit10=0 {}\n\n:sub micb_rd32, RS0L, RT5L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0110010000 & micb_bit10=0 & micb_rd32 {\n# Do we want this check?\n\t#tmpa:8 = sext(RS0L);\n\t#tmpb:8 = sext(RT5L);\n\t#tmpa = tmpa - tmpb;\n\t#if (tmpa[31,1] != tmpa[32,1]) goto ;\n\tmicb_rd32 = sext(RS0L - RT5L);\n\t#\n}\n\n:sub.S micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b01110000 {\n fd_tmp:4 = mic_fs:4 f- mic_ft_5:4;\n micb_fd = zext(fd_tmp);\n}\n\n:sub.D micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b01110000 {\n micb_fdD = mic_fsD f- mic_ftD_5;\n}\n\n:subu micb_rd32, RS0L, RT5L\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0111010000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = sext(RS0L - RT5L);\n}\n\n:subu16 RD7R1, RS1R7L, RT4L \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000001 & mic_bit0=1 & RD7R1 & RT4L & RS1R7L {\n\tRD7R1 = sext(RS1R7L - RT4L);\n}\n\n:sw RT5L, EXT_MS16(mic_base0)\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111110 & RT5L & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L:4;\n}\n\n:swe RT5L, EXT_CODE9E(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b111 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L:4;\n}\n\n:sw16 mic_encrt2, EXT_CODE4E(mic_base4)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111010 & mic_encrt2 & mic_base4 & EXT_CODE4E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE4E);\n\ttmp = tmp + mic_base4;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = mic_encrt2:4;\n}\n\n:swc1 mic_ft_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100110 & mic_base0 & mic_ft_5 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:4 tmpa = mic_ft_5:4; \n}\n\n:swc2 mic_rt32_5, micb_offset11s(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1000 & micb_bit11=0 & micb_offset11s {\n\ttmp:$(REGSIZE) = micb_offset11s;\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = getCopReg(2:1,mic_rt32_5); \n}\n\n:swsp RT5L, EXT_CODE5(sp)\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110010 & RT5L & sp & EXT_CODE5 {\n\ttmp:$(REGSIZE) = zext(EXT_CODE5);\n\ttmp = tmp + sp;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L;\n}\n\n:swp RT5L, EXT_CODE12(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & RT5L & mic_base0 & RSEXTL & mic_rs32_5; micb_func12=0b1001 & EXT_CODE12 [ext_32_rs1set = mic_rs32_5+1;] {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L;\n\ttmp = tmp + 4;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RSEXTL;\n}\n\n:swm16 STORE_TOP16\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & STORE_TOP16 & ((mic_csub=0b0101 & REL6=0) | (mic_csubr6=0b1010 & REL6=1)) { \n\tbuild STORE_TOP16; \n}\n\n:swm32 STORE_TOP\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_base0 & mic_rlist ; micb_func12=0b1101 & STORE_TOP [ ext_32_basea=mic_base0; ext_32_rlist=mic_rlist; ] { \n\tbuild STORE_TOP; \n}\n\n:sync STYPE \t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_funci=0 & STYPE ; micb_poolax=0b111100 & micb_axf=0b0110101101 {\n\tsynch(STYPE);\n}\n\n:synci EXT_MS16(mic_base0)\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & mic_base0 & ((mic_funci=0b10000 & REL6=0) | (mic_funci=0b01100 & REL6=1)); EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\tsynch(tmp);\n}\n\n:syscall \t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 ; micb_poolax=0b111100 & micb_axf=0b1000101101 {\n\tsyscall();\n}\n\n:teq mic_rs32_0, mic_rt32_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b000000 {\n\tif (mic_rs32_0 != mic_rt32_5) goto ;\n\ttrap();\n\t\n}\n\n:tge mic_rs32_0, mic_rt32_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b001000 {\n\tif (mic_rt32_5 s< mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tgeu mic_rs32_0, mic_rt32_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b010000 {\n\tif (mic_rt32_5 < mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tlbinv \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0100001101 {\n\ttlbop(0:1);\n}\n\n:tlbinvf \t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0101001101 {\n\ttlbop(1:1);\n}\n\n:tlbp \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0000001101 {\n\ttlbop(2:1);\n}\n\n:tlbr \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0001001101 {\n\ttlbop(3:1);\n}\n\n:tlbwi \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0010001101 {\n\ttlbop(4:1);\n}\n\n:tlbwr \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0011001101 {\n\ttlbop(5:1);\n}\n\n:tlt mic_rs32_0, mic_rt32_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b100000 {\n\tif (mic_rt32_5 s>= mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tltu mic_rs32_0, mic_rt32_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b101000 {\n\tif (mic_rt32_5 >= mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tne mic_rs32_0, mic_rt32_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b110000 {\n\tif (mic_rt32_5 == mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:trunk.l.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b10001100 {\n mic_ft_5 = trunc(mic_fs:4);\n}\n\n:trunk.l.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b10001100 {\n mic_ftD_5 = trunc(mic_fsD);\n}\n\n:trunk.w.S mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b10101100 {\n fd_tmp:4 = trunc(mic_fs:4);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:trunk.w.D mic_ft_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b10101100 {\n fd_tmp:4 = trunc(mic_fsD);\n mic_ft_5 = zext(fd_tmp);\n}\n\n:wait \t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 ; micb_poolax=0b111100 & micb_axf=0b1001001101 {\n\twait();\n}\n\n:wrpgpr mic_rt32_5, mic_rs32_0 \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b1111000101 {\n\tsetShadow(mic_rt32_5,mic_rs32_0);\n}\n\n:wsbh mic_rt32_5, RS0L \t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0111101100 {\n\ttmp1:4 = zext(RS0L[24,8]);\n\ttmp2:4 = zext(RS0L[16,8]);\n\ttmp3:4 = zext(RS0L[8,8]);\n\ttmp4:4 = zext(RS0L[0,8]);\n\ttmp5:4 = (tmp2 << 24) | (tmp1 << 16) | (tmp4 << 8) | tmp3;\n\tmic_rt32_5 = sext(tmp5);\n}\n\n:xor micb_rd32, mic_rs32_0, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1100010000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 ^ mic_rt32_5;\n}\n\n:xori mic_rt32_5, mic_rs32_0, micb_imm16\tis ISA_MODE=1 & RELP=0 & mic_op=0b011100 & mic_rs32_0 & mic_rt32_5 ; micb_imm16 {\n\ttmp:$(REGSIZE) = micb_imm16;\n\tmic_rt32_5 = mic_rs32_0 ^ tmp;\n}\n\n:xor16 RT3R7, RS0R4\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0001 & REL6=0) | (mic_csubr6=0b1000 & REL6=1)) {\n\tRT3R7 = RT3R7 ^ RS0R4;\n}\n\n@ifdef MIPS64\n:dadd micb_rd32, mic_rs32_0, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0100010000 & micb_bit10=0 & micb_rd32 {\n\t# The dest doesn't get modified if there's an overflow. As our sleigh max size is 64bits, checking for this is a little complicated.\n\t# Should we include this check or not?\n#\ttmpsl:8 = zext(mic_rs32_0:4);\n#\ttmptl:8 = zext(mic_rt32_5:4);\n#\ttmpsh:8 = zext(mic_rs32_0[32,32]);\n#\ttmpth:8 = zext(mic_rt32_5[32,32]);\n#\ttmpres:8 = tmpsl + tmptl;\n#\ttmpres = tmpres >> 32;\n#\ttmpres = tmpres + tmpsh + tmpth;\n#\ttmpres = tmpres >> 32;\n#\tif (tmpres == 1) goto ;\n\tmicb_rd32 = mic_rs32_0 + mic_rt32_5;\n#\t\n}\n\n:daddiu mic_rt32_5, mic_rs32_0, EXT_MS16\tis ISA_MODE=1 & RELP=0 & mic_op=0b010111 & mic_rs32_0 & mic_rt32_5 ; EXT_MS16 {\n\ttmp:8 = sext(EXT_MS16);\n\tmic_rt32_5 = mic_rs32_0 + tmp;\n}\n\n:daddu micb_rd32, mic_rs32_0, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0101010000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 + mic_rt32_5;\n}\n\n:dclo mic_rt32_5, mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0100101100 {\n mic_rt32_5 = lzcount( ~mic_rs32_0 );\n}\n\n:dclz mic_rt32_5, mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0101101100 {\n mic_rt32_5 = lzcount( mic_rs32_0 );\n}\n\n:dext mic_rt32_5, mic_rs32_0, micb_pos, SIZEP \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b101100 & micb_pos & SIZEP {\n\ttmpa:8 = 0xFFFFFFFFFFFFFFFF;\n\ttmpa = tmpa >> (64 - SIZEP);\n\ttmpb:8 = mic_rs32_0;\n\ttmpb = (tmpb >> micb_pos) & tmpa;\n\tmic_rt32_5 = tmpb;\n}\n\n:dextm mic_rt32_5, mic_rs32_0, micb_pos, SIZEPLG \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b100100 & micb_pos & SIZEPLG {\n\ttmpa:8 = 0xFFFFFFFFFFFFFFFF;\n\ttmpa = tmpa >> (64 - SIZEPLG);\n\ttmpb:8 = mic_rs32_0;\n\ttmpb = (tmpb >> micb_pos) & tmpa;\n\tmic_rt32_5 = tmpb;\n}\n\n:dextu mic_rt32_5, mic_rs32_0, POSHI, SIZEP \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b010100 & POSHI & SIZEP {\n\ttmpa:8 = 0xFFFFFFFFFFFFFFFF;\n\ttmpa = tmpa >> (64 - SIZEP);\n\ttmpb:8 = mic_rs32_0;\n\ttmpb = (tmpb >> POSHI) & tmpa;\n\tmic_rt32_5 = tmpb;\n}\n\n:dins mic_rt32_5, mic_rs32_0, micb_pos, SIZEQ\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b001100 & micb_pos & SIZEQ {\n\ttmpa:8 = 0xFFFFFFFFFFFFFFFF;\n\ttmpa = tmpa >> (64 - SIZEQ);\n\ttmpb:8 = mic_rs32_0 & tmpa;\n\ttmpa = tmpa << micb_pos;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << micb_pos;\n\tmic_rt32_5 = (mic_rt32_5 & tmpa) | tmpb;\n}\n\n:dinsm mic_rt32_5, mic_rs32_0, micb_pos, SIZEQLG\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b000100 & micb_pos & SIZEQLG {\n\ttmpa:8 = 0xFFFFFFFFFFFFFFFF;\n\ttmpa = tmpa >> (64 - SIZEQLG);\n\ttmpb:8 = mic_rs32_0 & tmpa;\n\ttmpa = tmpa << micb_pos;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << micb_pos;\n\tmic_rt32_5 = (mic_rt32_5 & tmpa) | tmpb;\n}\n\n:dinsu mic_rt32_5, mic_rs32_0, POSHI, SIZEQ\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b110100 & POSHI & SIZEQ {\n\ttmpa:8 = 0xFFFFFFFFFFFFFFFF;\n\ttmpa = tmpa >> (64 - SIZEQ);\n\ttmpb:8 = mic_rs32_0 & tmpa;\n\ttmpa = tmpa << POSHI;\n\ttmpa = ~tmpa;\n\ttmpb = tmpb << POSHI;\n\tmic_rt32_5 = (mic_rt32_5 & tmpa) | tmpb;\n}\n\n:dmfc0 mic_rt32_5, mic_rs32_0, CPSEL\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b00011 & micb_poolax=0b111100 & CPSEL {\n\tmic_rt32_5 = getCopReg(0:1,mic_rs32_0,CPSEL);\n}\n\n:dmfc1 mic_rt32_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0010010000 {\n mic_rt32_5 = mic_fsD;\n}\n\n:dmfc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b0110110100 {\n\tmic_rt32_5 = getCopReg(2:1,mic_impl:1);\n}\n\n:dmtc0 mic_rt32_5, mic_rs32_0, CPSEL\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b01011 & micb_poolax=0b111100 & CPSEL {\n\tsetCopReg(0:1,mic_rs32_0,mic_rt32_5,CPSEL);\n}\n\n:dmtc1 mic_rt32_5, mic_fs\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0010110000 {\n\tmic_fsD = mic_rt32_5;\n}\n\n:dmtc2 mic_rt32_5, mic_impl\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b000011 & micb_axf=0b0111110100 {\n\tsetCopReg(2:1,mic_rt32_5,mic_impl:1);\n}\n\n:drotr mic_rt32_5, mic_rs32_0, micb_sa\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0011000000 & micb_bit10=0 {\n\ttmpa:8 = mic_rs32_0 >> micb_sa;\n\ttmpb:8 = mic_rs32_0 << (64 - micb_sa);\n\ttmpa = tmpa | tmpb;\n\tmic_rt32_5 = tmpa;\n}\n\n:drotr32 mic_rt32_5, mic_rs32_0, SA32\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0011001000 & micb_bit10=0 {\n\ttmpa:8 = mic_rs32_0 >> SA32;\n\ttmpb:8 = mic_rs32_0 << (64 - SA32);\n\ttmpa = tmpa | tmpb;\n\tmic_rt32_5 = tmpa;\n}\n\n:drotrv micb_rd32, mic_rt32_5, RS0L\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_rd32 & micb_axf2=0b0011010000 & micb_bit10=0 {\n\ttmpr:1 = RS0L[0,6];\n\ttmpa:8 = mic_rt32_5 >> tmpr;\n\ttmpb:8 = mic_rt32_5 << (64 - tmpr);\n\ttmpa = tmpa | tmpb;\n\tmicb_rd32 = tmpa;\n}\n\n:dsbh mic_rt32_5, mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0111101100 {\n\ttmp1:8 = zext(mic_rs32_0[56,8]);\n\ttmp2:8 = zext(mic_rs32_0[48,8]);\n\ttmp3:8 = zext(mic_rs32_0[40,8]);\n\ttmp4:8 = zext(mic_rs32_0[32,8]);\n\ttmp5:8 = zext(mic_rs32_0[24,8]);\n\ttmp6:8 = zext(mic_rs32_0[16,8]);\n\ttmp7:8 = zext(mic_rs32_0[8,8]);\n\ttmp8:8 = zext(mic_rs32_0[0,8]);\n\ttmp9:8 = (tmp2 << 56) | (tmp1 << 48) | (tmp4 << 40) | (tmp3 << 32) | (tmp6 << 24) | (tmp5 << 16) | (tmp8 << 8) | tmp7;\n\tmic_rt32_5 = tmp9;\n}\n\n:dshd mic_rt32_5, mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b1111101100 {\n\ttmp1:8 = zext(mic_rs32_0[48,16]);\n\ttmp2:8 = zext(mic_rs32_0[32,16]);\n\ttmp3:8 = zext(mic_rs32_0[16,16]);\n\ttmp4:8 = zext(mic_rs32_0[0,16]);\n\ttmp5:8 = (tmp4 << 48) | (tmp3 << 32) | (tmp2 << 16) | tmp1;\n\tmic_rt32_5 = tmp5;\n}\n\n:dsll mic_rt32_5, mic_rs32_0, micb_sa\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0000000000 & micb_bit10=0 {\n\tmic_rt32_5 = mic_rs32_0 << micb_sa;\n}\n\n:dsll32 mic_rt32_5, mic_rs32_0, SA32\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0000001000 & micb_bit10=0 {\n\tmic_rt32_5 = mic_rs32_0 << SA32;\n}\n\n:dsllv micb_rd32, mic_rt32_5, RS0L\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_axf2=0b0000010000 & micb_bit10=0 & micb_rd32 {\n\ttmps:1 = RS0L[0,6];\n\tmicb_rd32 = mic_rt32_5 << tmps;\n}\n\n:dsra mic_rt32_5, mic_rs32_0, micb_sa\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0010000000 & micb_bit10=0 {\n\tmic_rt32_5 = mic_rs32_0 s>> micb_sa;\n}\n\n:dsra32 mic_rt32_5, mic_rs32_0, SA32\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0010000100 & micb_bit10=0 {\n\tmic_rt32_5 = mic_rs32_0 s>> SA32;\n}\n\n:dsrav micb_rd32, mic_rt32_5, RS0L\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_axf2=0b0010010000 & micb_bit10=0 & micb_rd32 {\n\ttmps:1 = RS0L[0,6];\n\tmicb_rd32 = mic_rt32_5 s>> tmps;\n}\n\n:dsrl mic_rt32_5, mic_rs32_0, micb_sa\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0001000000 & micb_bit10=0 {\n\tmic_rt32_5 = mic_rs32_0 >> micb_sa;\n}\n\n:dsrl32 mic_rt32_5, mic_rs32_0, SA32\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0001001000 & micb_bit10=0 {\n\tmic_rt32_5 = mic_rs32_0 >> SA32;\n}\n\n:dsrlv micb_rd32, mic_rt32_5, RS0L\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_axf2=0b0001010000 & micb_bit10=0 & micb_rd32 {\n\ttmps:1 = RS0L[0,6];\n\tmicb_rd32 = mic_rt32_5 >> tmps;\n}\n\n:dsub micb_rd32, mic_rs32_0, mic_rt32_5 \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0110010000 & micb_bit10=0 & micb_rd32 {\n# Do we want to test for this?\n\t#tmpt:1 = zext(mic_rt32_5[63,1]);\n\t#tmps:1 = zext(mic_rs32_0[63,1]);\n\t#tmp:8 = mic_rs32_0 - mic_rt32_5;\n\t#tmpa:1 = zext(tmp[63,1]);\n\t#if ((tmpa ^ tmps) & (tmpt ^ tmps)) goto ;\n\tmicb_rd32 = mic_rs32_0 - mic_rt32_5;\n\t#\n}\n\n:dsubu micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0111010000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 - mic_rt32_5;\n}\n\n:ld mic_rt32_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110111 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = *[ram]:8 tmpa; \n}\n\n:lld mic_rt32_5, EXT_CODE12(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0111 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n lockload(tmp);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = *[ram]:8 tmpa;\n}\n\n:lwu mic_rt32_5, EXT_CODE12(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1110 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\ttmpb:4 = *[ram]:4 tmpa;\n\tmic_rt32_5 = zext(tmpb);\n}\n\n:scd mic_rt32_5, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1111 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n lockwrite(tmp);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:8 tmpa = mic_rt32_5;\n\tmic_rt32_5 = 1;\n}\n\n:sd mic_rt32_5, EXT_MS16(mic_base0)\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110110 & mic_rt32_5 & mic_base0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:8 tmpa = mic_rt32_5; \n}\n\n@endif\n\n\n####\n#\n# Pre-6 semantics\n#\n####\n:abs.PS mic_ft_5, mic_fs\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b0001101 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n:add.PS\tmicb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b00110000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:addi mic_rt32_5, RS0L, EXT_MS16\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000100 & REL6=0 & RS0L & mic_rt32_5; EXT_MS16 {\n\ttmp:4 = sext(EXT_MS16);\n\ttmp = tmp + RS0L;\n\tmic_rt32_5 = sext(tmp);\n}\n\n:alnv.ps micb_fd, mic_fs, mic_ft_5, micb_rs32 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_rs32 & micb_poolfx=0b011001 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:b Rel16_mic\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_rs32_0=0 & mic_rt32_5=0 ; Rel16_mic {\n delayslot( 1 );\n\tgoto Rel16_mic;\n}\n\n:b16 Rel10_mic\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110011 & REL6=0 & Rel10_mic {\n delayslot( 1 );\n\tgoto Rel10_mic;\n}\n\n:bal Rel16_mic\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00011 & mic_rs32_0=0 ; Rel16_mic {\n ra = inst_next | 0x1; \n delayslot( 1 ); \n call Rel16_mic;\n}\n\n:bc1f COP2CC^Rel16_mic\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b11100 & mic_cp2z=0 & COP2CC ; Rel16_mic {\n # tmp:1 = getFpCondition(cc:1); # Note that other cc conditions are not implemented\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n delayslot(1);\n if (tmp != 0) goto inst_next;\n goto Rel16_mic;\n}\n\n:bc1t COP2CC^Rel16_mic\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b11101 & mic_cp2z=0 & COP2CC ; Rel16_mic {\n # tmp:1 = getFpCondition(cc:1);\n tmp:1 = fcsr[23,1]; # The floating point condition bit\n delayslot(1);\n if (tmp == 0) goto inst_next;\n goto Rel16_mic;\n}\n\n:bc2f COP2CC^Rel16_mic\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10100 & mic_cp2z=0 & COP2CC ; Rel16_mic {\n tmp:1 = getCopCondition(2:1, COP2CC); \n delayslot(1); \n if (tmp != 0) goto inst_next; \n goto Rel16_mic; \n}\n\n:bc2t COP2CC^Rel16_mic\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10101 & mic_cp2z=0 & COP2CC ; Rel16_mic {\n tmp:1 = getCopCondition(2:1, COP2CC); \n delayslot(1); \n if (tmp == 0) goto inst_next; \n goto Rel16_mic; \n}\n\n:beq mic_rs32_0, mic_rt32_5, Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b100101 & REL6=0 & mic_rs32_0 & mic_rt32_5; Rel16_mic {\n delayflag:1 = ( mic_rs32_0 == mic_rt32_5 ); \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:beqz16 mic_rs7, Rel7_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100011 & REL6=0 & mic_rs7 & Rel7_mic {\n delayflag:1 = ( mic_rs7 == 0 ); \n delayslot( 1 );\n if (delayflag) goto Rel7_mic;\n}\n\n:beqzc mic_rs32_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00111 & mic_rs32_0 ; Rel16_mic {\n if (mic_rs32_0 == 0) goto Rel16_mic;\n}\n\n:bgez mic_rs32_0, Rel16_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00010 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s>= 0); \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bgezal mic_rs32_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00011 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s>= 0); \n ra = inst_next | 0x1; \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bgezals mic_rs32_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10011 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s>= 0); \n ra = inst_next | 0x1; \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bgtz mic_rs32_0, Rel16_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00110 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s> 0); \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:blez mic_rs32_0, Rel16_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00100 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s<= 0); \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bltz mic_rs32_0, Rel16_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00000 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s< 0); \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bltzal mic_rs32_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00001 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s< 0); \n ra = inst_next | 0x1; \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bltzals mic_rs32_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10001 & mic_rs32_0 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 s< 0); \n ra = inst_next | 0x1; \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bne mic_rs32_0, mic_rt32_5, Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b101101 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; Rel16_mic {\n delayflag:1 = (mic_rs32_0 != mic_rt32_5); \n delayslot( 1 );\n if (delayflag) goto Rel16_mic;\n}\n\n:bnez16 mic_rs7, Rel7_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101011 & REL6=0 & mic_rs7 & Rel7_mic {\n delayflag:1 = (mic_rs7 != 0); \n delayslot( 1 );\n if (delayflag) goto Rel7_mic;\n}\n\n:bnezc mic_rs32_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00101 & mic_rs32_0 ; Rel16_mic {\n if (mic_rs32_0 != 0) goto Rel16_mic;\n}\n\n:c.f.S micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=0 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = 0; # Always false, no trap\n}\n:c.f.D micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=0 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = 0; # Always false, no trap\n}\n:c.f.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=0 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.un.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=1 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = nan(mic_fs:4) || nan(mic_ft_5:4); # True if an operand is NaN, no trap\n}\n\n:c.un.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=1 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = nan(mic_fsD) || nan(mic_ftD_5); # True if an operand is NaN, no trap\n}\n\n:c.un.PS micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=1 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.eq.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=2 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4); # No trap\n}\n\n:c.eq.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=2 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f== mic_ftD_5);\n}\n\n:c.eq.PS micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=2 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ueq.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=3 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4); # No trap\n}\n\n:c.ueq.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=3 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f== mic_ftD_5); # No trap\n}\n\n:c.ueq.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=3 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.olt.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=4 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4); # No trap\n}\n\n:c.olt.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=4 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f< mic_ftD_5); # No trap\n}\n\n:c.olt.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=4 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ult.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=5 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # Less than or NaN No trap\n}\n\n:c.ult.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=5 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f< mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # No trap\n}\n\n:c.ult.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=5 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ole.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=6 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4); # No trap\n}\n\n:c.ole.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=6 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f<= mic_ftD_5); # No trap\n}\n\n:c.ole.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=6 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ule.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=7 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # Less than or equal or NaN No trap\n}\n\n:c.ule.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=7 & micb_poolfx=0b111100 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f<= mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # No trap\n}\n\n:c.ule.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=7 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.sf.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=8 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = 0; # Always false, trap if either operand is NaN\n}\n\n:c.sf.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=8 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = 0; # Always false, trap\n}\n\n:c.sf.PS micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=8 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ngle.S micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=9 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = nan(mic_fs:4) || nan(mic_ft_5:4); # True if an operand is NaN, trap\n}\n\n:c.ngle.D micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=9 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = nan(mic_fsD) || nan(mic_ftD_5); # True if an operand is NaN, trap\n}\n\n:c.ngle.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=9 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.seq.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=10 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4); # trap\n}\n\n:c.seq.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=10 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f== mic_ftD_5); # trap\n}\n\n:c.seq.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=10 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ngl.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=11 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # trap\n}\n\n:c.ngl.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=11 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f== mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # trap\n}\n\n:c.ngl.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=11 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.lt.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=12 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4); # trap\n}\n\n:c.lt.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=12 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f< mic_ftD_5); # trap\n}\n\n:c.lt.PS micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=12 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.nge.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=13 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # trap\n}\n\n:c.nge.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=13 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f< mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # trap\n}\n\n:c.nge.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=13 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.le.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=14 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4); # Less than or equal trap\n}\n\n:c.le.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=14 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f<= mic_ftD_5); # trap\n}\n\n:c.le.PS micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=14 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:c.ngt.S micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=15 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # Less than or equal or NaN trap\n}\n\n:c.ngt.D micb_cc, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=15 & micb_poolfx=0b111100 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n fcsr[23,1] = (mic_fsD f<= mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # trap\n}\n\n:c.ngt.PS micb_cc, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=15 & micb_poolfx=0b111100 {\n fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:cache mic_cop5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & REL6=0 & mic_cop5 & mic_base0 ; micb_func12=0b0110 & EXT_CODE12 {\n\tcacheOp();\n}\n\n:cvt.PS micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fxf2=0b00110000000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:cvt.s.PL mic_ft_5, mic_fs\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_poolfx=0b111011 & micb_fxf4=0b10000100 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n:cvt.s.PU mic_ft_5, mic_fs\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_poolfx=0b111011 & micb_fxf4=0b10100100 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n:div RT5L, RS0L \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RS0L & RT5L ; micb_poolax=0b111100 & micb_axf=0b1010101100 {\n lo = sext(RS0L s/ RT5L); \n hi = sext(RS0L s% RT5L); \n}\n\n:divu RS0L, RT5L \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RS0L & RT5L ; micb_poolax=0b111100 & micb_axf=0b1011101100 {\n lo = sext(RS0L / RT5L); \n hi = sext(RS0L % RT5L); \n}\n\n:j Abs26_mic1\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110101 & REL6=0 & mic_code ; Abs26_mic1 [ ext_32_code = mic_code; ] {\n delayslot( 1 );\n\tgoto Abs26_mic1;\n}\n\n:jal Abs26_mic1\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111101 & REL6=0 & mic_code ; Abs26_mic1 [ ext_32_code = mic_code; ] {\n ra = inst_next | 0x1; \n delayslot( 1 ); \n call Abs26_mic1;\n}\n\n:jalr RTIMP^mic_rs32_0\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0000111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n mic_rt32_5 = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jalr.hb RTIMP^mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0001111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n mic_rt32_5 = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jalr16 mic_rs32_0\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01110 & mic_rs32_0 {\n\tJXWritePC(mic_rs32_0); \n ra = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jalrs16 mic_rs32_0\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01111 & mic_rs32_0 {\n\tJXWritePC(mic_rs32_0); \n ra = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jalrs RTIMP^mic_rs32_0\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0100111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n mic_rt32_5 = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jalrs.hb RTIMP^mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0101111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n mic_rt32_5 = inst_next | 0x1; \n delayslot( 1 ); \n call [pc];\n}\n\n:jals Abs26_mic1\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011101 & REL6=0 & mic_code ; Abs26_mic1 [ ext_32_code = mic_code; ] {\n ra = inst_next | 0x1; \n delayslot( 1 ); \n call Abs26_mic1;\n}\n\n:jalx Abs26_mic2\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111100 & REL6=0 & mic_code ; Abs26_mic2 [ ext_32_code = mic_code; ISA_MODE = 0; globalset(Abs26_mic2, ISA_MODE);] {\n ra = inst_next | 0x1; \n delayslot( 1 );\n ISAModeSwitch = 0; \n call Abs26_mic2;\n}\n\n:jr mic_rs32_0\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5=0 ; micb_axf=0b0000111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n delayslot( 1 ); \n goto [pc];\n}\n\n:jr.hb mic_rs32_0\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5=0 ; micb_axf=0b0001111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n delayslot( 1 ); \n goto [pc];\n}\n\n:jr16 mic_rs32_0\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01100 & mic_rs32_0 {\n\tJXWritePC(mic_rs32_0); \n delayslot( 1 ); \n goto [pc];\n}\n\n:jr16 ra\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01100 & mic_rs32_0=31 & ra {\n\tJXWritePC(ra); \n delayslot( 1 ); \n return [pc];\n}\n\n:jraddiusp EXT_CODE5\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b11000 & EXT_CODE5 {\n\ttmp:4 = zext(EXT_CODE5);\n@if REGSIZE == \"4\"\n\tsp = sp + tmp;\n@else\n\tsp_lo = sp_lo + tmp;\n\tsp = sext(sp_lo);\n@endif\n\tJXWritePC(ra); \n return [pc];\n}\n\n:jrc mic_rs32_0\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01101 & mic_rs32_0 {\n\tJXWritePC(mic_rs32_0); \n goto [pc];\n}\n\n:jrc\t ra\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01101 & mic_rs32_0=31 & ra {\n\tJXWritePC(ra); \n return [pc];\n}\n\n@if ENDIAN == \"big\"\n\n:lwl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0000 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad << (shft * 8); \n mic_rt32_5 = sext( valLoad | valOrig ); \n}\n\n:lwle mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b010 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad << (shft * 8); \n mic_rt32_5 = sext( valLoad | valOrig ); \n}\n\n:lwr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0001 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((shft+1) * 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad >> ((3-shft) * 8);\n mic_rt32_5 = sext( valOrig | valLoad );\n}\n\n:lwre mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b011 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((shft+1) * 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad >> ((3-shft) * 8);\n mic_rt32_5 = sext( valOrig | valLoad );\n}\n\n@else\n\n:lwl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0000 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad << ((3-shft) * 8); \n mic_rt32_5 = sext( valLoad | valOrig ); \n}\n\n:lwle mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b010 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad << ((3-shft) * 8); \n mic_rt32_5 = sext( valLoad | valOrig ); \n}\n\n:lwr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0001 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((4-shft)* 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad >> (shft * 8);\n mic_rt32_5 = sext( valOrig | valLoad );\n}\n\n:lwre mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b011 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((4-shft)* 8));\n valLoad:4 = 0;\n MemSrcCast(valLoad,addr);\n valLoad = valLoad >> (shft * 8);\n mic_rt32_5 = sext( valOrig | valLoad );\n}\n\n@endif\n# lwl and lwr almost always come in pairs. \n# When the analyzer does finds a matching lwl/lwr pair, the pcode is simplified so that \n# lwl does all the loading while lwr is a no-op\n@if ENDIAN == \"big\"\n:lwl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext( *[ram]:4 tmpa ); \n}\n:lwr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n}\n@else\n:lwl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n}\n:lwr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext( *[ram]:4 tmpa ); \n}\n@endif\n\n\n\n:lwxc1 micb_fd, mic_index(mic_base0) \tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fxf2=0b00001001000 {\n\ttmpa:$(REGSIZE) = mic_index + mic_base0;\n\ttmpb:$(ADDRSIZE) = 0;\n\tValCast(tmpb,tmpa);\n tmp:4 = *[ram]:4 tmpb;\n micb_fd = (micb_fd ^ 0xffffffff) + zext(tmp);\n}\n\n:madd RS0L, RT5L \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1100101100 {\n\ttmp1:8 = sext(RS0L);\n\ttmp2:8 = sext(RT5L);\n\tprod:8 = tmp1 * tmp2;\n lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n\tsum:8 = (zext(hi) << 32) + zext(lo) + prod;\n lo = sext(sum:4); \n sum = sum >> 32;\n hi = sext(sum:4); \n}\n\n:madd.S micb_fd, micb_fr, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_fd & micb_fr & micb_poolfx=0b000001 {\n fd_tmp:4 = (mic_fs:4 f* mic_ft_5:4) f+ micb_fr:4;\n micb_fd = zext(fd_tmp);\n}\n\n:madd.D micb_fd, micb_fr, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD; micb_fd & micb_fdD & micb_fr &micb_frD & micb_poolfx=0b001001 {\n micb_fdD = (mic_fsD f* mic_ftD_5) f+ micb_frD;\n}\n\n:madd.PS micb_fd, micb_fr, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD ; micb_fd & micb_fdD & micb_fr & micb_poolfx=0b010001 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:maddu RS0L, RT5L \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1101101100 {\n\ttmp1:8 = zext(RS0L);\n\ttmp2:8 = zext(RT5L);\n\tprod:8 = tmp1 * tmp2;\n lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n\tsum:8 = (zext(hi) << 32) + zext(lo) + prod;\n lo = sext(sum:4);\n sum = sum >> 32;\n hi = sext(sum:4); \n}\n\n:mfhi mic_rs32_0 \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0000110101 {\n\tmic_rs32_0 = hi;\n}\n\n:mfhi16 mic_rd32_0\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_sub2=0b10000 & mic_rd32_0 {\n\tmic_rd32_0 = hi;\t\n}\n\n:mflo mic_rs32_0 \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0001110101 {\n\tmic_rs32_0 = lo;\n}\n\n:mflo16 mic_rd32_0\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_sub2=0b10010 & mic_rd32_0 {\n\tmic_rd32_0 = lo;\t\n}\n\n:mov.PS mic_ft_5, mic_fs\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_ftD_5 & mic_fsD ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b0000001 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n:movf mic_rt32_5, mic_rs32_0, micb_cc\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_cc & micb_poolfx=0b111011 & micb_flt6=0b0000101 {\n tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1);\n if (tmp != 0) goto ;\n mic_rt32_5 = mic_rs32_0;\n \n}\n\n:movf.S mic_ft_5, mic_fs, micb_cc\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_cc & micb_fmt9=0 & micb_z11=0 & micb_fxf5=0b000100000 {\n tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1);\n if (tmp != 0) goto ;\n fs_tmp:4 = mic_fs:4;\n mic_ft_5 = zext(fs_tmp);\n \n}\n\n:movf.D mic_ft_5, mic_fs, micb_cc\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_cc & micb_fmt9=1 & micb_z11=0 & micb_fxf5=0b000100000 {\n tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1);\n if (tmp != 0) goto ;\n mic_ftD_5 = mic_fsD;\n \n}\n\n:movf.PS mic_ft_5, mic_fs, micb_cc\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD ; micb_cc & micb_fmt9=2 & micb_z11=0 & micb_fxf5=0b000100000 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n\n:movn micb_rd32, mic_rs32_0, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0000011000 & micb_bit10=0 & micb_rd32 {\n\tif (mic_rt32_5 == 0) goto ;\n\tmicb_rd32 = mic_rs32_0;\n\t\n}\n\n:movn.S micb_fd, mic_fs, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b00111000 {\n if (mic_rt32_5 == 0) goto ;\n fs_tmp:4 = mic_fs:4;\n micb_fd = zext(fs_tmp);\n \n}\n\n:movn.D micb_fd, mic_fs, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b00111000 {\n if (mic_rt32_5 == 0) goto ;\n micb_fdD = mic_fsD;\n \n}\n\n:movn.PS micb_fd, mic_fs, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b00111000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:movt mic_rt32_5, mic_rs32_0, micb_cc\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_cc & micb_poolfx=0b111011 & micb_flt6=0b0100101 {\n tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1);\n if (tmp == 0) goto ;\n mic_rt32_5 = mic_rs32_0;\n \n}\n\n:movt.S mic_ft_5, mic_fs, micb_cc\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_cc & micb_fmt9=0 & micb_z11=0 & micb_fxf5=0b001100000 {\n tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1);\n if (tmp == 0) goto ;\n fs_tmp:4 = mic_fs:4;\n mic_ft_5 = zext(fs_tmp);\n \n}\n\n:movt.D mic_ft_5, mic_fs, micb_cc\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_cc & micb_fmt9=1 & micb_z11=0 & micb_fxf5=0b001100000 {\n tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1);\n if (tmp == 0) goto ;\n mic_ftD_5 = mic_fsD;\n \n}\n\n:movt.PS mic_ft_5, mic_fs, micb_cc\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD ; micb_cc & micb_fmt9=2 & micb_z11=0 & micb_fxf5=0b001100000 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n:movz micb_rd32, mic_rs32_0, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0001011000 & micb_bit10=0 & micb_rd32 {\n\tif (mic_rt32_5 != 0) goto ;\n\tmicb_rd32 = mic_rs32_0;\n\t\n}\n\n:movz.S micb_fd, mic_fs, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b01111000 {\n if (mic_rt32_5 != 0) goto ;\n fs_tmp:4 = mic_fs:4;\n micb_fd = zext(fs_tmp);\n \n}\n\n:movz.D micb_fd, mic_fs, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b01111000 {\n if (mic_rt32_5 != 0) goto ;\n micb_fdD = mic_fsD;\n \n}\n\n:movz.PS micb_fd, mic_fs, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b01111000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:msub RS0L, RT5L \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1110101100 {\n\ttmp1:8 = sext(RS0L);\n\ttmp2:8 = sext(RT5L);\n\tprod:8 = tmp1 * tmp2;\n lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n \tsum:8 = (zext(hi) << 32) + zext(lo) - prod;\n lo = sext(sum:4); \n sum = sum >> 32;\n hi = sext(sum:4); \n}\n\n:msub.S micb_fd, micb_fr, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_fd & micb_fr & micb_poolfx=0b100001 {\n fd_tmp:4 = (mic_fs:4 f* mic_ft_5:4) f- micb_fr:4;\n micb_fd = zext(fd_tmp);\n}\n\n:msub.D micb_fd, micb_fr, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fdD & micb_frD & micb_fd & micb_fr & micb_poolfx=0b101001 {\n micb_fdD = (mic_fsD f* mic_ftD_5) f- micb_frD;\n}\n\n:msub.PS micb_fd, micb_fr, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fr & micb_poolfx=0b110001 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:msubu RS0L, RT5L \t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1111101100 {\n\ttmp1:8 = zext(RS0L);\n\ttmp2:8 = zext(RT5L);\n\tprod:8 = tmp1 * tmp2;\n lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum\n\tsum:8 = (zext(hi) << 32) + zext(lo) - prod;\n lo = sext(sum:4); \n sum = sum >> 32;\n hi = sext(sum:4); \n}\n\n:mthi mic_rs32_0 \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0010110101 {\n\thi = mic_rs32_0;\n}\n\n:mtlo mic_rs32_0 \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0011110101 {\n\tlo = mic_rs32_0;\n}\n\n:mul.PS micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b10110000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:mult RS0L, RT5L \t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1000101100 {\n\ttmps:8 = sext(RS0L);\n\ttmpt:8 = sext(RT5L);\n\ttmpr:8= tmps * tmpt;\n\tlo = sext(tmpr[0,32]);\n\thi = sext(tmpr[32,32]);\n}\n\n:multu RS0L, RT5L \t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1001101100 {\n\ttmps:8 = zext(RS0L);\n\ttmpt:8 = zext(RT5L);\n\ttmpr:8= tmps * tmpt;\n\tlo = sext(tmpr[0,32]);\n\thi = sext(tmpr[32,32]);\n}\n\n:neg.PS mic_ft_5, mic_fs\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_ftD_5 & mic_fsD ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b0101101 {\n mic_ftD_5 = mipsFloatPS(mic_fsD);\n}\n\n:pll.PS micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00010000000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:plu.PS micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00011000000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:prefx micb_hint, mic_index(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_index & mic_base0 ; micb_axf2=0b0110100000 & micb_bit10=0 & micb_hint {\n\ttmp:$(REGSIZE) = mic_index + mic_base0;\n\tprefetch(tmp,micb_hint:1);\n}\n\n:pul.PS micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00100000000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:puu.PS micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00101000000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n:rdhwr mic_rt32_5, mic_rs32_hw \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5 & mic_rs32_hw ; micb_poolax=0b111100 & micb_axf=0b0110101100 {\n\tmic_rt32_5 = getHWRegister(mic_rs32_hw);\n}\n\n:sub.PS micb_fd, mic_fs, mic_ft_5\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b01110000 {\n micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5);\n}\n\n@if ENDIAN == \"big\"\n\n:swl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1000 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4); \n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft;\n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff << ((4-shft) * 8));\n valStore:4 = (tmpRT >> (shft * 8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swle mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4); \n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff << ((4-shft) * 8));\n valStore:4 = (tmpRT >> (shft * 8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1001 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4);\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff >> ((shft+1) * 8));\n valStore:4 = (tmpRT << ((3-shft)*8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swre mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b001 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4);\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff >> ((shft+1) * 8));\n valStore:4 = (tmpRT << ((3-shft)*8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n@else\n\n:swl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1000 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4); \n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff << ((shft+1) * 8));\n valStore:4 = (tmpRT >> ((3-shft) * 8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swle mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4); \n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff << ((shft+1) * 8));\n valStore:4 = (tmpRT >> ((3-shft) * 8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1001 & EXT_CODE12 {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4);\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff >> ((4-shft) * 8));\n valStore:4 = (tmpRT << (shft*8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n:swre mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b001 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n tmpRT:4 = mic_rt32_5:$(SIZETO4);\n shft:$(REGSIZE) = tmp & 0x3; \n addr:$(REGSIZE) = tmp - shft; \n valOrig:4 = 0;\n MemSrcCast(valOrig,addr);\n valOrig = valOrig & (0xffffffff >> ((4-shft) * 8));\n valStore:4 = (tmpRT << (shft*8)) | valOrig;\n MemDestCast(addr,valStore);\n}\n\n@endif\n# When the analyzer finds a matching swl/swr pair, the pcode is simplified so that \n# swl does all the storing while swr is a no-op\n@if ENDIAN == \"big\"\n:swl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:4 tmpa = mic_rt32_5:$(SIZETO4);\n}\n:swr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n}\n@else\n:swl mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {\n}\n:swr mic_rt32_5, EXT_CODE12(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] {\n\ttmp:$(REGSIZE) = sext(EXT_CODE12);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:4 tmpa = mic_rt32_5:$(SIZETO4);\n}\n@endif\n\n:sdxc1 micb_fd, mic_index(mic_base0) \tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fdD & micb_fxf2=0b00100001000 {\n\ttmp:$(REGSIZE) = mic_index + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:8 tmpa = micb_fdD;\n}\n\n:swxc1 micb_fd, mic_index(mic_base0) \tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fxf2=0b00010001000 {\n\ttmp:$(REGSIZE) = mic_index + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n *[ram]:4 tmpa = micb_fd:4; \n}\n\n:teqi mic_rs32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01110 & mic_rs32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\tif (mic_rs32_0 != tmp) goto ;\n\ttrap();\n\t\n}\n\n:tgei mic_rs32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01001 & mic_rs32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\tif (tmp s< mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tgeiu mic_rs32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01011 & mic_rs32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\tif (tmp < mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tlti mic_rs32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01000 & mic_rs32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\tif (tmp s>= mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tltiu mic_rs32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01010 & mic_rs32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\tif (tmp >= mic_rs32_0) goto ;\n\ttrap();\n\t\n}\n\n:tnei mic_rs32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01100 & mic_rs32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = sext(EXT_MS16);\n\tif (mic_rs32_0 == tmp) goto ;\n\ttrap();\n\t\n}\n\n@ifdef MIPS64\n:ddiv mic_rt32_5, mic_rs32_0 \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_poolax=0b111100 & micb_axf=0b1010101100 {\n lo = mic_rs32_0 s/ mic_rt32_5;\n hi = mic_rs32_0 s% mic_rt32_5;\n}\n\n:ddivu mic_rt32_5, mic_rs32_0 \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_poolax=0b111100 & micb_axf=0b1011101100 {\n lo = mic_rs32_0 / mic_rt32_5;\n hi = mic_rs32_0 % mic_rt32_5;\n}\n\n:luxc1 micb_fd, mic_index(mic_base0) \tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fxf2=0b00101001000 {\n\ttmp:$(REGSIZE) = mic_index + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n ptr:$(ADDRSIZE) = tmpa; \n micb_fd = *[ram]:8 ptr;\n}\n\n\n@endif\n\n####\n#\n# Release 6 semantics\n#\n####\n:align micb_rd32, RS0L, RT5L, micb_bp\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RT5L & RS0L ; micb_poolax=0b011111 & micb_z68=0 & micb_rd32 & micb_bp {\n\ttmp:4 = RT5L << (8 * micb_bp);\n\ttmp = tmp | (RS0L >> (32 - (8 * micb_bp)));\n\tmicb_rd32 = sext(tmp);\n}\n\n:aluipc mic_rt32_5, EXT_MS32\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcf=0b11111 & mic_rt32_5 ; EXT_MS32 {\n\ttmp:$(REGSIZE) = sext(EXT_MS32);\n\ttmp = tmp + inst_start;\n\ttmp = tmp & ~0xFFFF;\n\tmic_rt32_5 = tmp;\n}\n\n:aui mic_rt32_5, RS0L, EXT_MS32 \t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000100 & REL6=1 & mic_rt32_5 & RS0L ; EXT_MS32 {\n\ttmp:4 = RS0L + EXT_MS32;\n\tmic_rt32_5 = sext(tmp);\n}\n\n:auipc mic_rt32_5, EXT_MS32\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcf=0b11110 & mic_rt32_5 ; EXT_MS32 {\n\ttmp:$(REGSIZE) = sext(EXT_MS32);\n\ttmp = tmp + inst_start;\n\tmic_rt32_5 = tmp;\n}\n\n# Check this. Says left shift by 1 bit, but then says 4 byte alligned. BC instruction is simlar though it says left shift by 2 bits.\n# Either way, there is a mistake in the documentation\n:balc Rel26_mic\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101101 & REL6=1 ; Rel26_mic {\n ra = inst_next | 0x1; \n call Rel26_mic;\n}\n\n:bc Rel26_mic\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100101 & REL6=1 ; Rel26_mic {\n\tgoto Rel26_mic;\n}\n\n:bc16 Rel10_mic\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110011 & REL6=1 & Rel10_mic {\n\tgoto Rel10_mic;\n}\n\n:bc1eqzc mic_ft_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01000 & mic_ft_0; Rel16_mic {\n tmp:1 = mic_ft_0[0,8] & 0x01; # Only need to check the LSB\n if (tmp == 0x00) goto Rel16_mic;\n}\n\n:bc1nezc mic_ft_0, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01001 & mic_ft_0; Rel16_mic {\n tmp:1 = mic_ft_0[0,8] & 0x01; # Only need to check the LSB\n if (tmp == 0x01) goto Rel16_mic;\n}\n\n:bc2eqzc mic_ct, Rel16_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01010 & mic_ct; Rel16_mic {\n tmp:1 = getCopCondition(2:1, mic_ct:1); \n if (tmp == 0) goto inst_next; \n goto Rel16_mic; \n}\n\n:bc2nezc mic_ct, Rel16_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01011 & mic_ct; Rel16_mic {\n tmp:1 = getCopCondition(2:1, mic_ct:1); \n if (tmp == 1) goto inst_next; \n goto Rel16_mic; \n}\n\n:beqzc16 mic_rs7, Rel7_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100011 & REL6=1 & mic_rs7 & Rel7_mic {\n if (mic_rs7 == 0) goto Rel7_mic;\n}\n\n:bnezc16 mic_rs7, Rel7_mic\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101011 & REL6=1 & mic_rs7 & Rel7_mic {\n if (mic_rs7 != 0) goto Rel7_mic;\n}\n\n# Some of the branch instructions have a != in the pattern description in mips documentation.\n# In order to avoid pattern blowup in sleigh, I use some fake instructions as sinks when possible.\n# It was not possible to avoid all instances of != in the constructors\n:bad1\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_code=0; Rel16_mic unimpl\n:blezalc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic {\n\tif (mic_rt32_5 s> 0) goto inst_next;\n ra = inst_next | 0x1; \n\tcall Rel16_mic;\n}\n\n:bgezalc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic {\n\tif (mic_rt32_5 s< 0) goto inst_next;\n ra = inst_next | 0x1; \n\tcall Rel16_mic;\n}\n\n:bgeuc mic_rs32_0,mic_rt32_5,Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic {\n\tif (mic_rs32_0 >= mic_rt32_5) goto Rel16_mic;\n}\n\n:bad2\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_code=0; Rel16_mic unimpl\n:bgtzalc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic {\n\tif (mic_rt32_5 s<= 0) goto inst_next;\n ra = inst_next | 0x1; \n\tcall Rel16_mic;\n}\n\n:bltzalc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic {\n\tif (mic_rt32_5 s>= 0) goto inst_next;\n ra = inst_next | 0x1; \n\tcall Rel16_mic;\n}\n:bltuc mic_rs32_0,mic_rt32_5,Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic {\n\tif (mic_rs32_0 < mic_rt32_5) goto Rel16_mic;\n}\n\n# for this case, bovc is the catch-all. \n:beqzalc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011101 & REL6=1 & mic_rs32_0=0 & mic_rt32_5 & mic_rt32_5a!=0; Rel16_mic {\n\tif (mic_rt32_5 != 0) goto inst_next;\n ra = inst_next | 0x1; \n\tcall Rel16_mic;\n}\n\n:beqc mic_rs32_0, mic_rt32_5, Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b011101 & REL6=1 & mic_rt32_5 & mic_rs32_0 & mic_rs32_0a!=0 & mic_rs32_0b 0x7FFFFFFF) || (tmpS s< -2147483648);\n@if REGSIZE == \"8\"\n\ttmpF = tmpF || (mic_rt32_5 s> 0x7FFFFFFF) || (mic_rt32_5 s< -2147483648) || (mic_rs32_0 s> 0x7FFFFFFF) || (mic_rs32_0 s< -2147483648);\n@endif\n\tif (tmpF == 1) goto Rel16_mic;\n}\n\n# for this case, bnvc is the catch-all.\n:bnezalc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011111 & REL6=1 & mic_rs32_0=0 & mic_rt32_5 & mic_rt32_5a!=0; Rel16_mic {\n\tif (mic_rt32_5 == 0) goto inst_next;\n ra = inst_next | 0x1; \n\tcall Rel16_mic;\n}\n\n:bnec mic_rs32_0, mic_rt32_5, Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b011111 & REL6=1 & mic_rt32_5 & mic_rs32_0 & mic_rs32_0a!=0 & mic_rs32_0b 0x7FFFFFFF) || (tmpS s< -2147483648);\n@if FREGSIZE == \"8\"\n\ttmpF = tmpF || (mic_rt32_5 s> 0x7FFFFFFF) || (mic_rt32_5 s< -2147483648) || (mic_rs32_0 s> 0x7FFFFFFF) || (mic_rs32_0 s< -2147483648);\n@endif\n\tif (tmpF == 0) goto Rel16_mic;\n}\n\n:bad3\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_code=0; Rel16_mic unimpl\n:blezc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic {\n\tif (mic_rt32_5 s<= 0) goto Rel16_mic;\n}\n\n:bgezc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic {\n\tif (mic_rt32_5 s>= 0) goto Rel16_mic;\n}\n\n:bgec mic_rs32_0,mic_rt32_5,Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic {\n\tif (mic_rs32_0 s>= mic_rt32_5) goto Rel16_mic;\n}\n\n:bad4\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_code=0; Rel16_mic unimpl\n:bgtzc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic {\n\tif (mic_rt32_5 s> 0) goto Rel16_mic;\n}\n\n:bltzc mic_rt32_5, Rel16_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic {\n\tif (mic_rt32_5 s< 0) goto Rel16_mic;\n}\n\n:bltc mic_rs32_0,mic_rt32_5,Rel16_mic\tis ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic {\n\tif (mic_rs32_0 s< mic_rt32_5) goto Rel16_mic;\n}\n\n:beqzc mic_rs32_5, Rel21_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100000 & REL6=1 & mic_rs32_5 & mic_imm5; Rel21_mic [ext_32_imm5 = mic_imm5;] {\n\tif (mic_rs32_5 == 0) goto Rel21_mic;\n}\n\n:bad6\t\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b10100 & REL6=1 & mic_rs32_5=0; Rel21_mic unimpl\n:bnezc mic_rs32_5, Rel21_mic\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b10100 & REL6=1 & mic_rs32_5 & mic_imm5; Rel21_mic [ext_32_imm5 = mic_imm5;] {\n\tif (mic_rs32_5 != 0) goto Rel21_mic;\n}\n\n:bitswap mic_rd32_0, RT5L\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RT5L & mic_rd32_0 ; micb_poolax=0b111100 & micb_axf3=0b101100 & micb_z12=0 {\n\ttmp:4 = bitSwap(RT5L);\n\tmic_rd32_0 = sext(tmp);\n}\n\n:cache mic_cop5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b001000 & REL6=1 & mic_cop5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0 & EXT_CODE9E {\n\tcacheOp();\n}\n\n:class.S mic_fd, mic_fs_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd ; micb_size=0 & micb_fmt9=0 & micb_fxf5=0b001100000 {\n tmp_fs:4 = mic_fs_5:4; # Get just the 4 byte single floating point value\n tmp_exponent:4 = zext(tmp_fs[23,8]);\n tmp_fraction:4 = zext(tmp_fs[0,23]);\n tmp_sign:4 = zext(tmp_fs[31,1]);\n tmp_b1:4 = zext(tmp_fs[22,1]); # High order bit of fraction, used for NaN\n\n tmp_SNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0)); \n tmp_QNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01));\n tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0));\n tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff));\n tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0));\n tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff));\n tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n\n tmp_fd:4 = 0;\n tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) |\n\t\t(tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) |\n\t\t(tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9);\n\n mic_fd = zext(tmp_fd);\n}\n\n:class.D mic_fd, mic_fs_5 \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd & mic_fsD_5 & mic_fdD ; micb_size=0 & micb_fmt9=1 & micb_fxf5=0b001100000 {\n tmp_fs:8 = mic_fsD_5;\n tmp_sign:4 = zext(tmp_fs[63,1]);\n tmp_exponent:4 = zext(tmp_fs[52,11]);\n tmp_fraction:8 = zext(tmp_fs[0,51]);\n tmp_b1:4 = zext(tmp_fs[51,1]); # High order bit of fraction, used for NaN\n\n tmp_SNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0));\n tmp_QNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01));\n tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0));\n tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff));\n tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0));\n tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff));\n tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0));\n tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0));\n\n tmp_fd:4 = 0;\n tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) |\n (tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) |\n (tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9);\n\n mic_fdD = zext(tmp_fd);\n}\n\n#:cmp.condn.fmt\n:cmp.af.S micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x00 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = 0x0;\n}\n\n:cmp.af.D micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x00 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = 0x0;\n}\n\n:cmp.un.S micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x01 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext((nan(mic_fs:4) || nan(mic_ft_5:4)) * 0xff);\n}\n\n:cmp.un.D micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_cond2=0x01 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((nan(mic_fsD) || nan(mic_ftD_5)) * 0xff);\n}\n\n:cmp.eq.S micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x02 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext((mic_fs:4 f== mic_ft_5:4) * 0xff);\n}\n\n:cmp.eq.D micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x02 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((mic_fsD f== mic_ftD_5) * 0xff);\n}\n\n:cmp.ueq.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x03 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) ) * 0xff);\n}\n\n:cmp.ueq.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x03 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) ) * 0xff);\n}\n\n:cmp.lt.S micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x04 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext((mic_fs:4 f< mic_ft_5:4) * 0xff);\n}\n\n:cmp.lt.D micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x04 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((mic_fsD f< mic_ftD_5) * 0xff);\n}\n\n:cmp.ult.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x05 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f< mic_ft_5:4) ) * 0xff);\n}\n\n:cmp.ult.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x05 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f< mic_ftD_5) ) * 0xff);\n}\n\n:cmp.le.S micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x06 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext((mic_fs:4 f<= mic_ft_5:4) * 0xff);\n}\n\n:cmp.le.D micb_fd, mic_fs, mic_ft_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x06 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((mic_fsD f<= mic_ftD_5) * 0xff);\n}\n\n:cmp.ule.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x07 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN\n micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f<= mic_ft_5:4) ) * 0xff);\n}\n\n:cmp.ule.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x07 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f<= mic_ftD_5) ) * 0xff);\n}\n\n:cmp.saf.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x08 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = 0x0;\n}\n\n:cmp.saf.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x08 & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = 0x0;\n}\n\n:cmp.sun.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x09 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext((nan(mic_fs:4) || nan(mic_ft_5:4)) * 0xff);\n}\n\n:cmp.sun.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x09 & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((nan(mic_fsD) || nan(mic_ftD_5)) * 0xff);\n}\n\n:cmp.seq.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0A & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext((mic_fs:4 f== mic_ft_5:4) * 0xff);\n}\n\n:cmp.seq.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0A & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((mic_fsD f== mic_ftD_5) * 0xff);\n}\n\n:cmp.sueq.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0B & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) ) * 0xff);\n}\n\n:cmp.sueq.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0B & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) ) * 0xff);\n}\n\n:cmp.slt.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0C & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( (mic_fs:4 f< mic_ft_5:4) * 0xff);\n}\n\n:cmp.slt.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0C & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( (mic_fsD f< mic_ftD_5) * 0xff);\n}\n\n:cmp.sult.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0D & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f< mic_ft_5:4) ) * 0xff);\n}\n\n:cmp.sult.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0D & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f< mic_ftD_5) ) * 0xff);\n}\n\n:cmp.sle.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0E & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( (mic_fs:4 f<= mic_ft_5:4) * 0xff);\n}\n\n:cmp.sle.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0E & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( (mic_fsD f<= mic_ftD_5) * 0xff);\n}\n\n:cmp.sule.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0F & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f<= mic_ft_5:4) ) * 0xff);\n}\n\n:cmp.sule.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0F & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f<= mic_ftD_5) ) * 0xff);\n}\n\n:cmp.or.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x11 & micb_poolfx=0b000101 {\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( (!(nan(mic_fs:4) || nan(mic_ft_5:4))) * 0xff); # The negated predicate of \"c.un\"\n}\n\n:cmp.or.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x11 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( (!(nan(mic_fsD) || nan(mic_ftD_5))) * 0xff);\n}\n\n:cmp.une.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x12 & micb_poolfx=0b000101 {\n # The negated predicate of cmp.eq\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext((mic_fs:4 f!= mic_ft_5:4) * 0xff);\n}\n\n:cmp.une.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x12 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((mic_fsD f!= mic_ftD_5) * 0xff);\n}\n\n:cmp.ne.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x13 & micb_poolfx=0b000101 {\n # The negated predicate of cmp.ueq\n trapIfSNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( (!( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) ))) * 0xff);\n}\n\n:cmp.ne.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x13 & micb_poolfx=0b010101 {\n trapIfSNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( (!( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) ))) * 0xff);\n}\n\n:cmp.sor.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x19 & micb_poolfx=0b000101 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext( (!(nan(mic_fs:4) || nan(mic_ft_5:4))) * 0xff); # negate of cmp.sun\n}\n\n:cmp.sor.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x19 & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( (!(nan(mic_fsD) || nan(mic_ftD_5))) * 0xff);\n}\n\n:cmp.sune.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x1A & micb_poolfx=0b000101 {\n trapIfNaN(mic_fs:4, mic_ft_5:4);\n micb_fd = sext((mic_fs:4 f!= mic_ft_5:4) * 0xff);\n}\n\n:cmp.sune.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x1A & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext((mic_fsD f!= mic_ftD_5) * 0xff);\n}\n\n:cmp.sne.S micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x1B & micb_poolfx=0b000101 {\n trapIfNaN(mic_fs:4, mic_ft_5:4); # negate of cmp.sueq\n micb_fd = sext( (! ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) )) * 0xff);\n}\n\n:cmp.sne.D micb_fd, mic_fs, mic_ft_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x1B & micb_poolfx=0b010101 {\n trapIfNaN(mic_fsD, mic_ftD_5);\n micb_fdD = sext( (! ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) )) * 0xff);\n}\n\n:div micb_rd32, RS0L, RT5L \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0100011000 & micb_bit10=0 & micb_rd32 {\n\ttmp:4 = RS0L s/ RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:divu micb_rd32, RS0L, RT5L \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0110011000 & micb_bit10=0 & micb_rd32 {\n\ttmp:4 = RS0L / RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:dvp STYPE \t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_funci=0 & STYPE ; micb_poolax=0b111100 & micb_axf=0b0001100101 {\n\tdisableProcessor(STYPE);\n}\n\n:evp STYPE \t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_funci=0 & STYPE ; micb_poolax=0b111100 & micb_axf=0b0011100101 {\n\tenableProcessor(STYPE);\n}\n\n:jalrc RTIMP^mic_rs32_0\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_0 & RTIMP ; micb_axf=0b0000111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n mic_rt32_5 = inst_next | 0x1; \n call [pc];\n}\n\n:jalrc.hb RTIMP^mic_rs32_0\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_0 & RTIMP ; micb_axf=0b0001111100 & micb_poolax=0b111100 {\n\tJXWritePC(mic_rs32_0); \n mic_rt32_5 = inst_next | 0x1; \n call [pc];\n}\n\n:jalrc16 mic_rs32_5\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b01110 & mic_rs32_5 {\n\tJXWritePC(mic_rs32_5); \n ra = inst_next | 0x1; \n call [pc];\n}\n\n:jialc mic_rt32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b101000 & REL6=1 & mic_index=0 & mic_rt32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = mic_rt32_0 + sext(EXT_MS16);\n\tJXWritePC(tmp);\n ra = inst_next | 0x1; \n\tgoto [pc];\n}\n\n:jic mic_rt32_0, EXT_MS16\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b100000 & REL6=1 & mic_index=0 & mic_rt32_0 ; EXT_MS16 {\n\ttmp:$(REGSIZE) = mic_rt32_0 + sext(EXT_MS16);\n\tJXWritePC(tmp);\n\tgoto [pc];\n}\n\n:jrcaddiusp EXT_CODE5R6\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b10011 & EXT_CODE5R6 {\n\ttmp:$(REGSIZE) = zext(EXT_CODE5R6);\n\tsp = sp + tmp;\n\tJXWritePC(ra); \n goto [pc];\n}\n\n:jrc16 mic_rs32_5\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b01100 & mic_rs32_5 {\n\tJXWritePC(mic_rs32_5); \n goto [pc];\n}\n\n:jrc16 ra\t\t\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b01100 & mic_rs32_5=31 & ra {\n\tJXWritePC(ra); \n return [pc];\n}\n\n:llx mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b0001 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa);\n lockload(tmp);\n}\n\n:llxe mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b010 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa);\n lockload(tmp);\n}\n\n:lsa micb_rd32, RS0L, RT5L, EXT_SA9 \tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_poolax=0b001111 & micb_asel=0b000 & EXT_SA9 & micb_rd32 {\n\ttmp:4 = (RS0L << EXT_SA9) + RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:lwpc mic_rt32_5, EXT_MS19\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcz=0b01 & mic_rt32_5 & mic_imm02 ; EXT_MS19 [ ext_32_imm3=mic_imm02; ] {\n\ttmp:$(REGSIZE) = inst_start + sext(EXT_MS19);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\ttmpl:4 = *[ram]:4 tmpa;\n\tmic_rt32_5 = sext(tmpl);\n}\n\n:lwupc mic_rt32_5, EXT_MS19\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcz=0b10 & mic_rt32_5 & mic_imm02 ; EXT_MS19 [ ext_32_imm3=mic_imm02; ] {\n\ttmp:$(REGSIZE) = inst_start + sext(EXT_MS19);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\ttmpl:4 = *[ram]:4 tmpa;\n\tmic_rt32_5 = zext(tmpl);\n}\n\n:maddf.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b110111000 {\n tmp:4 = micb_fd:4 f+ (mic_fs:4 f* mic_ft_5:4);\n micb_fd = zext(tmp);\n}\n\n:maddf.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b110111000 {\n micb_fdD = micb_fdD f+ (mic_fsD f* mic_ftD_5);\n}\n\n:max.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000001011 {\n # set floating point fd to the max of fs and ft, TBD special case for NaN\n tmp_cond:1 = mic_fs:4 f> mic_ft_5:4;\n micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) );\n}\n\n:max.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000001011 {\n tmp_cond:1 = mic_fsD f> mic_ftD_5;\n micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) );\n}\n\n:maxa.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000101011 {\n # set floating point fd to the max of absolute values of fs and ft, TBD special case for NaN\n tmp_cond:1 = abs(mic_fs:4) f> abs(mic_ft_5:4);\n micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) );\n}\n\n:maxa.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000101011 {\n tmp_cond:1 = abs(mic_fsD) f> abs(mic_ftD_5);\n micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) );\n}\n\n:min.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000000011 {\n # set floating point fd to the min of fs and ft, TBD special case for NaN\n tmp_cond:1 = mic_fs:4 f< mic_ft_5:4;\n micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) );\n}\n\n:min.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000000011 {\n tmp_cond:1 = mic_fsD f< mic_ftD_5;\n micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) );\n}\n\n:mina.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000100011 {\n # set floating point fd to the min of absolute values of fs and ft, TBD special case for NaN\n tmp_cond:1 = abs(mic_fs:4) f< abs(mic_ft_5:4);\n micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) );\n}\n\n:mina.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000100011 {\n tmp_cond:1 = abs(mic_fsD) f< abs(mic_ftD_5);\n micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) );\n}\n\n:mod micb_rd32, RS0L, RT5L \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0101011000 & micb_bit10=0 & micb_rd32 {\n\ttmp:4 = RS0L s% RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:modu micb_rd32, RS0L, RT5L \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0111011000 & micb_bit10=0 & micb_rd32 {\n\ttmp:4 = RS0L % RT5L;\n\tmicb_rd32 = sext(tmp);\n}\n\n:msubf.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b111111000 {\n # set floating point fd = fd - fs * ft, using 32-bit floating values\n tmp:4 = micb_fd:4 f- (mic_fs:4 f* mic_ft_5:4);\n micb_fd = zext(tmp);\n}\n\n:msubf.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b111111000 {\n micb_fdD = micb_fdD f- (mic_fsD f* mic_ftD_5);\n}\n\n:muh micb_rd32, RS0L, RT5L \t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0001011000 & micb_bit10=0 & micb_rd32 {\n\ttmpS:8 = sext(RS0L);\n\ttmpT:8 = sext(RT5L);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[32,32];\n\tmicb_rd32 = sext(tmp);\n}\n\n:mulu micb_rd32, RS0L, RT5L \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0010011000 & micb_bit10=0 & micb_rd32 {\n\ttmpS:8 = zext(RS0L);\n\ttmpT:8 = zext(RT5L);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[0,32];\n\tmicb_rd32 = sext(tmp);\n}\n\n:muhu micb_rd32, RS0L, RT5L \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0011011000 & micb_bit10=0 & micb_rd32 {\n\ttmpS:8 = zext(RS0L);\n\ttmpT:8 = zext(RT5L);\n\ttmpS = tmpS * tmpT;\n\ttmp:4 = tmpS[32,32];\n\tmicb_rd32 = sext(tmp);\n}\n\n#sel only valid for PerfCtr\n:rdhwr mic_rt32_5, mic_rs32_hw, micb_sel\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_hw & mic_rs32_0=4; micb_sel & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 {\n\tmic_rt32_5 = getHWRegister(mic_rs32_hw, micb_sel:1);\n}\n\n:rdhwr mic_rt32_5, mic_rs32_hw\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_hw & mic_rs32_0!=4; micb_sel=0 & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 {\n\tmic_rt32_5 = getHWRegister(mic_rs32_hw);\n}\n\n:rint.S mic_fd, mic_fs_5\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd ; micb_fd=0 & micb_fmt9=0 & micb_fxf5=0b000100000 {\n # floating point round to integral floating point\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n fs_tmp:4 = mic_fs_5:4;\n fs_cvt_tmp:4 = 0;\n if (rm_tmp == 0) goto ;\n fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n fs_cvt_tmp = round(fs_tmp); # round returns a float\n \n mic_fd = zext(fs_cvt_tmp);\n}\n\n:rint.D mic_fd, mic_fs_5\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd & mic_fsD_5 & mic_fdD; micb_fd=0 & micb_fmt9=1 & micb_fxf5=0b000100000 {\n # floating point round to integral floating point\n rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits\n if (rm_tmp == 0) goto ;\n mic_fdD = floor(mic_fsD_5); # RM is 1, no rounding, and floor returns a float\n goto ;\n \n mic_fdD = round(mic_fsD_5); # round returns a float\n \n}\n\n:scx RT5L, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & RT5L & mic_base0 ; micb_func12=0b1001 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n lockwrite(tmp);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L;\n\tRT5L = 1;\n}\n\n:scxe RT5L, EXT_CODE9E(mic_base0)\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:4 tmpa = RT5L;\n lockwrite(tmp);\n}\n\n:seleqz micb_rd32, mic_rs32_0, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0101000000 & micb_bit10=0 & micb_rd32 {\n\t# We use tmp to cover case where rs and rd are the same reg\n\ttmps:$(REGSIZE) = mic_rs32_0;\n\ttmpt:$(REGSIZE) = mic_rt32_5;\n\tmicb_rd32 = 0;\n\tif (tmpt != 0) goto inst_next;\n\tmicb_rd32 = tmps;\n}\n\n:selnez micb_rd32, mic_rs32_0, mic_rt32_5\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0110000000 & micb_bit10=0 & micb_rd32 {\n\t# We use tmp to cover case where rs and rd are the same reg\n\ttmps:$(REGSIZE) = mic_rs32_0;\n\ttmpt:$(REGSIZE) = mic_rt32_5;\n\tmicb_rd32 = 0;\n\tif (tmpt == 0) goto inst_next;\n\tmicb_rd32 = tmps;\n}\n\n:sel.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b010111000 {\n tmp:1 = (micb_fd[0,1] == 0x01);\n micb_fd = (zext(tmp) * mic_ft_5) | (zext(tmp == 0x0) * mic_fs);\n}\n\n:sel.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_fsD & mic_ft_5 & mic_ftD_5; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b010111000 {\n tmp:1 = (micb_fdD[0,1] == 0x01);\n micb_fdD = (zext(tmp) * mic_ftD_5) | (zext(tmp == 0x0) * mic_fsD);\n}\n\n:seleqz.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000111000 {\n micb_fd = zext(mic_fs * zext(mic_ft_5[0,1] == 0));\n}\n\n:seleqz.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000111000 {\n micb_fdD = zext(mic_fsD * zext(mic_ftD_5[0,1] == 0));\n}\n\n:selnez.S mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b001111000 {\n micb_fd = zext(mic_fs * zext(mic_ft_5[0,1] == 1));\n}\n\n:selnez.D mic_ft_5, mic_fs, micb_fd\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b001111000 {\n micb_fdD = zext(mic_fsD * zext(mic_ftD_5[0,1] == 1));\n}\n\n:sigrie\tEXT_CODE16\t\t\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_code4r6=0 & mic_imm6r6; micb_poolax=0b111111 & EXT_CODE16 [ ext_32_imm6 = mic_imm6r6; ] {\n\tsignalReservedInstruction(EXT_CODE16);\n}\n\n@ifdef MIPS64\n:dalign micb_rd32, mic_rs32_0, mic_rt32_5, micb_bp8\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b011100 & micb_z67=0 & micb_rd32 & micb_bp8 {\n\ttmp:8 = mic_rt32_5 << (8 * micb_bp8);\n\tmicb_rd32 = tmp | (mic_rs32_0 >> (64 - (8 * micb_bp8)));\n}\n\n:dahi mic_rs32_0, EXT_MS48 \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b10001 & mic_rs32_0 ; EXT_MS48 {\n\tmic_rs32_0 = mic_rs32_0 + EXT_MS48;\n}\n\n:dati mic_rs32_0, EXT_MS64 \t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b10000 & mic_rs32_0 ; EXT_MS64 {\n\tmic_rs32_0 = mic_rs32_0 + EXT_MS64;\n}\n\n:daui mic_rt32_5, mic_rs32_0, EXT_MS32 is ISA_MODE=1 & RELP=0 & mic_op=0b111100 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; EXT_MS32 {\n\tmic_rt32_5 = mic_rs32_0 + sext(EXT_MS32);\n}\n\n:dbitswap mic_rd32_0, mic_rt32_5\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rd32_0 ; micb_poolax=0b111100 & micb_axf3=0b101100 & micb_z12=0 {\n\tmic_rd32_0 = bitSwap(mic_rt32_5);\n}\n\n:ddiv micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0100011000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 s/ mic_rt32_5;\n}\n\n:ddivu micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0110011000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 / mic_rt32_5;\n}\n\n:dlsa micb_rd32, mic_rs32_0, mic_rt32_5, EXT_SA9 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_poolax=0b000100 & micb_asel=0b100 & EXT_SA9 & micb_rd32 {\n\tmicb_rd32 = (mic_rs32_0 << EXT_SA9) + mic_rt32_5;\n}\n\n:dmod micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0101011000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 s% mic_rt32_5;\n}\n\n:dmodu micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0111011000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 % mic_rt32_5;\n}\n\n:dmul micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0000011000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 * mic_rt32_5;\n}\n\n:dmuh micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0001011000 & micb_bit10=0 & micb_rd32 {\n\ttmp:16 = sext(mic_rs32_0) * sext(mic_rt32_5);\n micb_rd32 = tmp(8); \n}\n\n:dmulu micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0010011000 & micb_bit10=0 & micb_rd32 {\n\tmicb_rd32 = mic_rs32_0 * mic_rt32_5;\n}\n\n:dmuhu micb_rd32, mic_rs32_0, mic_rt32_5 \tis ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0011011000 & micb_bit10=0 & micb_rd32 {\n\ttmp:16 = zext(mic_rs32_0) * zext(mic_rt32_5);\n micb_rd32 = tmp(8); \n}\n\n:ldpc mic_rt32_5, EXT_MS18\t\t\t\tis ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcf2=0b110 & mic_rt32_5 & mic_imm01 ; EXT_MS18 [ ext_32_imm2=mic_imm01; ] {\n\ttmp:8 = inst_start + sext(EXT_MS18);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\tmic_rt32_5 = *[ram]:8 tmpa; \n}\n\n:lldx mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b0101 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n mic_rt32_5 = sext(*[ram]:4 tmpa);\n lockload(tmp);\n}\n\n# The documentation is partly wrong for this instruction and generates a conflict (same pattern) as lldx instruction. The op-code map section of the document\n# does have the difference between this and the lldx so I went with that. \n:scdx mic_rt32_5, EXT_CODE9E(mic_base0)\tis ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b1101 & micb_sub9=0b000 & EXT_CODE9E {\n\ttmp:$(REGSIZE) = sext(EXT_CODE9E);\n\ttmp = tmp + mic_base0;\n lockwrite(tmp);\n\ttmpa:$(ADDRSIZE) = 0;\n\tValCast(tmpa,tmp);\n\t*[ram]:8 tmpa = mic_rt32_5;\n\tmic_rt32_5 = 1;\n}\n\n@endif\n" }, { "path": "pypcode/processors/MIPS/data/manuals/MIPS.idx", "content": "@mips64v2.pdf[MIPS64 Architecture For Programmers - Volume II, July 2005 (MD00087)]\nabs. , 49\nadd\t\t , 50\nadd. , 51\naddi\t\t, 52\naddiu\t\t, 53\naddu\t\t, 54\nalnv.ps , 55\nand\t\t , 58\nandi\t\t, 59\nb , 60\nbal , 61\nbc1f , 62\nbc1fl , 64\nbc1t , 66\nbc1tl , 68\nbc2f , 70\nbc2fl , 71\nbc2t , 73\nbc2tl , 74\nbeq\t\t , 76\nbeql\t\t, 77\nbgez\t\t, 79\nbgezal\t , 80\nbgezall\t , 81\nbgezl\t\t, 83\nbgtz\t\t, 85\nbgtzl\t\t, 86\nblez\t\t, 88\nblezl\t\t, 89\nbltz\t\t, 91\nbltzal\t , 92\nbltzall\t , 93\nbltzl\t\t, 95\nbne\t\t , 97\nbnel\t\t, 98\nbreak\t\t, 100\nc. , 101\ncache\t\t, 106\nceil.l. , 113\nceil.w. , 115\ncfc1\t\t, 116\ncfc2 , 118\nclear , 54\nclo , 119\nclz , 121\ncop2\t\t, 120\nctc1 , 122\nctc2\t\t, 124\ncvt.d. , 125\ncvt.l. , 126\ncvt.ps.s , 128\ncvt.s.d , 130\ncvt.s.l , 130\ncvt.s.pl , 131\ncvt.s.pu , 132\ncvt.s.w , 130\ncvt.w. , 133\ndadd\t\t, 134\ndaddi\t\t, 135\ndaddiu\t , 136\ndaddu\t\t, 137\ndclo , 138\ndclz , 139\nddiv\t\t, 140\nddivu\t\t, 141\nderet , 142\ndext , 144\ndextm , 146\ndextu , 148\ndi , 150\ndins , 152\ndinsm , 154\ndinsu , 156\ndiv\t\t , 158\ndiv. , 160\ndivu\t\t, 161\ndmfc0\t\t, 162\ndmfc1 , 163\ndmfc2 , 164\ndmtc0\t\t, 165\ndmtc1 , 166\ndmtc2 , 167\ndmult\t\t, 168\ndmultu \t, 169\ndrotr , 170\ndrotrv , 172\ndrotr32 , 171\ndsbh , 173\ndshd , 175\ndsll\t\t, 177\ndsllv\t\t, 179\ndsll32 , 178\ndsra\t\t, 180\ndsrav\t\t, 182\ndsra32 , 181\ndsrl\t\t, 183\ndsrlv\t\t, 185\ndsrl32\t , 184\ndsub\t\t, 186\ndsubu\t\t, 187\nehb , 188\nei , 189\neret\t\t, 191\next , 193\nfloor.l. , 195\nfloor.w. , 197\nins , 198\nj\t\t , 200\njal\t \t, 201\njalr\t\t, 202\njalr.hb , 204\njr\t\t , 207\njr.hb , 209\nlb\t\t , 212\nlbu\t\t , 213\nld\t\t , 214\nldc1\t\t, 215\nldc2 , 216\nldl\t\t , 217\nldr\t\t , 219\nldxc1 , 222\nlh\t\t , 223\nlhu\t \t, 224\nll\t \t, 225\nlld\t \t, 227\nlui\t\t , 229\nluxc1 , 230\nlw\t\t , 231\nlwc1\t\t, 232\nlwc2 , 233\nlwl\t\t , 234\nlwr\t\t , 237\nlwu\t\t , 241\nlwxc1 , 242\nmadd , 243\nmadd.d , 244\nmadd.ps , 244\nmadd.s , 244\nmaddu , 246\nmfc0\t\t, 247\nmfc1 , 248\nmfc2 , 249\nmfhc1 , 250\nmfhc2 , 251\nmfhi\t\t, 252\nmflo\t\t, 253\nmov. , 254\nmove , 254\nmovf , 255\nmovf. , 256\nmovn , 258\nmovn. , 259\nmovt , 261\nmovt. , 262\nmovz , 264\nmovz. , 265\nmsub , 267\nmsub. , 268\nmsubu , 270\nmtc0\t\t, 271\nmtc1 , 272\nmtc2 , 273\nmthc1\t\t, 274\nmthc2 , 275\nmthi\t\t, 276\nmtlo\t\t, 277\nmul , 278\nmul. , 279\nmult\t\t, 280\nmultu\t\t, 281\nneg. , 282\nnmadd. , 283\nnmsub. , 285\nnop , 287\nnor\t \t, 288\nor\t\t , 289\nori\t\t , 290\npll.ps , 291\nplu.ps , 292\npref , 293\nprefx , 297\npul.ps , 298\npuu.ps , 299\nrdhwr , 300\nrdpgpr , 302\nrecip. , 303\nretn , 207\nrotr , 305\nrotrv , 306\nround.l. , 307\nround.w. , 309\nrsqrt. , 311\nsb\t \t, 313\nsc\t \t, 314\nscd\t \t, 317\nsd\t \t, 320\nsdbbp , 321\nsdc1\t\t, 322\nsdc2 , 323\nsdl\t\t , 324\nsdr\t\t , 327\nsdxc1 , 330\nseb , 331\nseh , 332\nsh\t\t , 334\nsll\t\t , 335\nsllv\t\t, 336\nslt\t\t , 337\nslti\t\t, 338\nsltiu\t\t, 339\nsltu\t\t, 340\nsqrt. , 341\nsra\t \t, 342\nsrav\t\t, 343\nsrl\t\t , 344\nsrlv\t\t, 345\nssnop , 346\nsub\t\t , 347\nsub. , 348\nsubu\t\t, 349\nsuxc1 , 350\nsw\t\t , 351\nswc1\t\t, 352\nswcw , 353\nswl\t\t , 354\nswr\t\t , 356\nswxc1 , 358\nsync\t\t, 359\nsynci , 363\nsyscall\t , 366\nteq\t\t , 367\nteqi\t\t, 368\ntge\t\t , 369\ntgei\t\t, 370\ntgeiu\t\t, 371\ntgeu\t\t, 372\ntlbp\t\t, 373\ntlbr\t\t, 374\ntlbwi\t\t, 376\ntlbwr\t\t, 378\ntlt\t\t , 380\ntlti\t\t, 381\ntltiu\t\t, 382\ntltu\t\t, 383\ntne\t\t , 384\ntnei\t\t, 385\ntrunc.l. , 386\ntrunc.w. , 388\nwait , 390\nwrpgpr , 392\nwsbh , 393\nxor\t \t, 394\nxori\t\t, 395\n" }, { "path": "pypcode/processors/MIPS/data/manuals/mipsM16.idx", "content": "@MD00087-2B-MIPS64BIS-AFP-6.06.pdf [MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual, MD00087, 6.06, December 15, 2016]\nabs.d,44\nabs.ps,44\nabs.s,44\nadd,45\nadd.d,46\nadd.ps,46\nadd.s,46\naddi,47\naddiu,48\naddiupc,49\naddu,50\nalign,51\nalnv.ps,53\naluipc,55\nand,56\nandi,57\naui,58\nauipc,60\nb,61\nb.af.c,94\nb.at.c,94\nb.eq.c,94\nb.f.c,94\nb.ge.c,94\nb.gl.c,94\nb.gle.c,94\nb.gt.c,94\nb.le.c,94\nb.lt.c,94\nb.ne.c,94\nb.neq.c,94\nb.nge.c,94\nb.ngl.c,94\nb.ngle.c,94\nb.ngt.c,94\nb.nle.c,94\nb.nlt.c,94\nb.oge.c,94\nb.ogl.c,94\nb.ogt.c,94\nb.ole.c,94\nb.olt.c,94\nb.or.c,94\nb.saf.c,94\nb.sat.c,94\nb.seq.c,94\nb.sf.c,94\nb.sle.c,94\nb.slt.c,94\nb.sne.c,94\nb.soge.c,94\nb.sogt.c,94\nb.sor.c,94\nb.st.c,94\nb.sueq.c,94\nb.suge.c,94\nb.sugt.c,94\nb.sule.c,94\nb.sult.c,94\nb.sun.c,94\nb.sune.c,94\nb.t.c,94\nb.ueq.c,94\nb.uge.c,94\nb.ugt.c,94\nb.ule.c,94\nb.ult.c,94\nb.un.c,94\nb.une.c,94\nbal,62\nbalc,64\nbc,65\nbc1eqz,66\nbc1f,68\nbc1fl,70\nbc1nez,66\nbc1t,72\nbc1tl,74\nbc2eqz,76\nbc2f,78\nbc2fl,79\nbc2nez,76\nbc2t,81\nbc2tl,82\nbeq,84\nbeql,85\nbeqzalc,89\nbgez,87\nbgezal,88\nbgezalc,89\nbgezall,92\nbgezl,98\nbgtz,100\nbgtzalc,89\nbgtzl,101\nbitswap,103\nblez,105\nblezalc,89\nblezl,106\nbltz,108\nbltzal,109\nbltzalc,89\nbltzall,110\nbltzl,112\nbne,114\nbnel,115\nbnezalc,89\nbnvc,117\nbovc,117\nbreak,119\nc.af.d,120\nc.af.ps,120\nc.af.s,120\nc.at.d,120\nc.at.ps,120\nc.at.s,120\nc.eq.d,120\nc.eq.ps,120\nc.eq.s,120\nc.f.d,120\nc.f.ps,120\nc.f.s,120\nc.ge.d,120\nc.ge.ps,120\nc.ge.s,120\nc.gl.d,120\nc.gl.ps,120\nc.gl.s,120\nc.gle.d,120\nc.gle.ps,120\nc.gle.s,120\nc.gt.d,120\nc.gt.ps,120\nc.gt.s,120\nc.le.d,120\nc.le.ps,120\nc.le.s,120\nc.lt.d,120\nc.lt.ps,120\nc.lt.s,120\nc.ne.d,120\nc.ne.ps,120\nc.ne.s,120\nc.neq.d,120\nc.neq.ps,120\nc.neq.s,120\nc.nge.d,120\nc.nge.ps,120\nc.nge.s,120\nc.ngl.d,120\nc.ngl.ps,120\nc.ngl.s,120\nc.ngle.d,120\nc.ngle.ps,120\nc.ngle.s,120\nc.ngt.d,120\nc.ngt.ps,120\nc.ngt.s,120\nc.nle.d,120\nc.nle.ps,120\nc.nle.s,120\nc.nlt.d,120\nc.nlt.ps,120\nc.nlt.s,120\nc.oge.d,120\nc.oge.ps,120\nc.oge.s,120\nc.ogl.d,120\nc.ogl.ps,120\nc.ogl.s,120\nc.ogt.d,120\nc.ogt.ps,120\nc.ogt.s,120\nc.ole.d,120\nc.ole.ps,120\nc.ole.s,120\nc.olt.d,120\nc.olt.ps,120\nc.olt.s,120\nc.or.d,120\nc.or.ps,120\nc.or.s,120\nc.saf.d,120\nc.saf.ps,120\nc.saf.s,120\nc.sat.d,120\nc.sat.ps,120\nc.sat.s,120\nc.seq.d,120\nc.seq.ps,120\nc.seq.s,120\nc.sf.d,120\nc.sf.ps,120\nc.sf.s,120\nc.sle.d,120\nc.sle.ps,120\nc.sle.s,120\nc.slt.d,120\nc.slt.ps,120\nc.slt.s,120\nc.sne.d,120\nc.sne.ps,120\nc.sne.s,120\nc.soge.d,120\nc.soge.ps,120\nc.soge.s,120\nc.sogt.d,120\nc.sogt.ps,120\nc.sogt.s,120\nc.sor.d,120\nc.sor.ps,120\nc.sor.s,120\nc.st.d,120\nc.st.ps,120\nc.st.s,120\nc.sueq.d,120\nc.sueq.ps,120\nc.sueq.s,120\nc.suge.d,120\nc.suge.ps,120\nc.suge.s,120\nc.sugt.d,120\nc.sugt.ps,120\nc.sugt.s,120\nc.sule.d,120\nc.sule.ps,120\nc.sule.s,120\nc.sult.d,120\nc.sult.ps,120\nc.sult.s,120\nc.sun.d,120\nc.sun.ps,120\nc.sun.s,120\nc.sune.d,120\nc.sune.ps,120\nc.sune.s,120\nc.t.d,120\nc.t.ps,120\nc.t.s,120\nc.ueq.d,120\nc.ueq.ps,120\nc.ueq.s,120\nc.uge.d,120\nc.uge.ps,120\nc.uge.s,120\nc.ugt.d,120\nc.ugt.ps,120\nc.ugt.s,120\nc.ule.d,120\nc.ule.ps,120\nc.ule.s,120\nc.ult.d,120\nc.ult.ps,120\nc.ult.s,120\nc.un.d,120\nc.un.ps,120\nc.un.s,120\nc.une.d,120\nc.une.ps,120\nc.une.s,120\ncache,124\ncache,125\ncachee,130\nceil.l.d,136\nceil.l.s,136\nceil.w.d,137\nceil.w.s,137\ncfc1,138\ncfc2,140\nclass.d,141\nclass.s,141\nclo,143\nclz,144\ncmp.af.d,145\ncmp.af.s,145\ncmp.at.d,145\ncmp.at.s,145\ncmp.eq.d,145\ncmp.eq.s,145\ncmp.f.d,145\ncmp.f.s,145\ncmp.ge.d,145\ncmp.ge.s,145\ncmp.gl.d,145\ncmp.gl.s,145\ncmp.gle.d,145\ncmp.gle.s,145\ncmp.gt.d,145\ncmp.gt.s,145\ncmp.le.d,145\ncmp.le.s,145\ncmp.lt.d,145\ncmp.lt.s,145\ncmp.ne.d,145\ncmp.ne.s,145\ncmp.neq.d,145\ncmp.neq.s,145\ncmp.nge.d,145\ncmp.nge.s,145\ncmp.ngl.d,145\ncmp.ngl.s,145\ncmp.ngle.d,145\ncmp.ngle.s,145\ncmp.ngt.d,145\ncmp.ngt.s,145\ncmp.nle.d,145\ncmp.nle.s,145\ncmp.nlt.d,145\ncmp.nlt.s,145\ncmp.oge.d,145\ncmp.oge.s,145\ncmp.ogl.d,145\ncmp.ogl.s,145\ncmp.ogt.d,145\ncmp.ogt.s,145\ncmp.ole.d,145\ncmp.ole.s,145\ncmp.olt.d,145\ncmp.olt.s,145\ncmp.or.d,145\ncmp.or.s,145\ncmp.saf.d,145\ncmp.saf.s,145\ncmp.sat.d,145\ncmp.sat.s,145\ncmp.seq.d,145\ncmp.seq.s,145\ncmp.sf.d,145\ncmp.sf.s,145\ncmp.sle.d,145\ncmp.sle.s,145\ncmp.slt.d,145\ncmp.slt.s,145\ncmp.sne.d,145\ncmp.sne.s,145\ncmp.soge.d,145\ncmp.soge.s,145\ncmp.sogt.d,145\ncmp.sogt.s,145\ncmp.sor.d,145\ncmp.sor.s,145\ncmp.st.d,145\ncmp.st.s,145\ncmp.sueq.d,145\ncmp.sueq.s,145\ncmp.suge.d,145\ncmp.suge.s,145\ncmp.sugt.d,145\ncmp.sugt.s,145\ncmp.sule.d,145\ncmp.sule.s,145\ncmp.sult.d,145\ncmp.sult.s,145\ncmp.sun.d,145\ncmp.sun.s,145\ncmp.sune.d,145\ncmp.sune.s,145\ncmp.t.d,145\ncmp.t.s,145\ncmp.ueq.d,145\ncmp.ueq.s,145\ncmp.uge.d,145\ncmp.uge.s,145\ncmp.ugt.d,145\ncmp.ugt.s,145\ncmp.ule.d,145\ncmp.ule.s,145\ncmp.ult.d,145\ncmp.ult.s,145\ncmp.un.d,145\ncmp.un.s,145\ncmp.une.d,145\ncmp.une.s,145\ncop2,150\ncrc32b,152\ncrc32cb,155\ncrc32cd,155\ncrc32ch,155\ncrc32cw,155\ncrc32d,152\ncrc32h,152\ncrc32w,152\nctc1,158\nctc2,161\ncvt.d.l,162\ncvt.d.s,162\ncvt.d.w,162\ncvt.l.d,163\ncvt.l.s,163\ncvt.ps.s,164\ncvt.s.d,168\ncvt.s.l,168\ncvt.s.pl,166\ncvt.s.pu,167\ncvt.s.w,168\ncvt.w.d,169\ncvt.w.s,169\ndadd,170\ndaddi,171\ndaddiu,172\ndaddu,173\ndahi,58\ndalign,51\ndati,58\ndaui,58\ndbitswap,103\ndclo,174\ndclz,175\nddiv,176\nddivu,177\nderet,178\ndext,179\ndextm,181\ndextu,183\ndi,185\ndins,186\ndinsm,188\ndinsu,190\ndiv,192\ndiv.d,197\ndiv.s,197\ndivu,194\ndlsa,294\ndmfc0,199\ndmfc1,200\ndmfc2,201\ndmod,194\ndmodu,194\ndmtc0,202\ndmtc1,203\ndmtc2,204\ndmuh,363\ndmuhu,363\ndmul,363\ndmult,205\ndmultu,206\ndmulu,363\ndrotr,207\ndrotr32,208\ndrotrv,209\ndsbh,210\ndshd,211\ndsll,212\ndsll32,213\ndsllv,214\ndsra,215\ndsra32,216\ndsrav,217\ndsrl,218\ndsrl32,219\ndsrlv,220\ndsub,221\ndsubu,222\ndvp,223\nehb,226\nei,227\neret,228\neretnc,230\nevp,232\next,234\nfloor.l.d,236\nfloor.l.s,236\nfloor.w.d,237\nfloor.w.s,237\nginvi,239\nginvt,241\nins,244\nj,246\njal,247\njalr,248\njalr.hb,250\njalx,253\njialc,255\njic,257\njr,258\njr.hb,260\nlb,263\nlbe,264\nlbu,265\nlbue,266\nld,267\nldc1,268\nldc2,269\nldl,271\nldpc,273\nldr,274\nldxc1,276\nlh,277\nlhe,278\nlhu,279\nlhue,280\nll,281\nlld,283\nlldp,288\nlle,286\nllwp,290\nllwpe,292\nlsa,294\nlui,295\nluxc1,296\nlw,297\nlwc1,298\nlwc2,299\nlwe,300\nlwl,301\nlwle,304\nlwpc,307\nlwr,308\nlwre,311\nlwre,312\nlwu,315\nlwupc,316\nlwxc1,317\nmadd,318\nmadd.d,319\nmadd.ps,319\nmadd.s,319\nmaddf.d,321\nmaddf.s,321\nmaddu,323\nmax.d,324\nmax.s,324\nmaxa.d,324\nmaxa.s,324\nmfc0,328\nmfc1,329\nmfc2,330\nmfhc0,331\nmfhc1,333\nmfhc2,334\nmfhi,335\nmflo,336\nmin.d,324\nmin.s,324\nmina.d,324\nmina.s,324\nmod,194\nmodu,194\nmov.d,337\nmov.ps,337\nmov.s,337\nmovf,338\nmovf.d,339\nmovf.ps,339\nmovf.s,339\nmovn,341\nmovn.d,342\nmovn.ps,342\nmovn.s,342\nmovt,343\nmovt.d,344\nmovt.ps,344\nmovt.s,344\nmovz,346\nmovz.d,347\nmovz.ps,347\nmovz.s,347\nmsub,348\nmsub.d,349\nmsub.ps,349\nmsub.s,349\nmsubf.d,321\nmsubf.s,321\nmsubu,351\nmtc0,352\nmtc1,354\nmtc2,355\nmthc0,356\nmthc1,358\nmthc2,359\nmthi,360\nmtlo,361\nmuh,363\nmuhu,363\nmul,362\nmul.d,366\nmul.ps,366\nmul.s,366\nmult,367\nmultu,368\nmulu,363\nnal,369\nneg.d,370\nneg.ps,370\nneg.s,370\nnmadd.d,371\nnmadd.ps,371\nnmadd.s,371\nnmsub.d,373\nnmsub.ps,373\nnmsub.s,373\nnop,375\nnor,376\nor,377\nori,378\npause,379\npll.ps,381\nplu.ps,382\npref,383\nprefe,387\nprefx,391\npul.ps,392\npuu.ps,393\nrdhwr,394\nrdpgpr,397\nrecip.d,398\nrecip.s,398\nrint.d,399\nrint.s,399\nrotr,401\nrotrv,402\nround.l.d,403\nround.l.s,403\nround.w.d,404\nround.w.s,404\nrsqrt.d,405\nrsqrt.s,405\nsb,406\nsbe,407\nsc,408\nscd,412\nscdp,415\nsce,418\nscwp,422\nscwpe,426\nsd,429\nsdbbp,430\nsdc1,431\nsdc2,432\nsdl,433\nsdr,435\nsdxc1,437\nseb,438\nseh,439\nsel.d,441\nsel.s,441\nseleqz,442\nseleqz.d,444\nseleqz.s,444\nselnez,442\nsh,446\nshe,447\nsigrie,448\nsll,449\nsllv,450\nslt,451\nslti,452\nsltiu,453\nsltu,454\nsqrt.d,455\nsqrt.s,455\nsra,456\nsrav,457\nsrl,458\nsrlv,459\nssnop,460\nsub,461\nsub.d,462\nsub.ps,462\nsub.s,462\nsubu,463\nsuxc1,464\nsw,465\nswc2,467\nswe,468\nswl,469\nswle,471\nswr,473\nswre,475\nswxc1,477\nsync,478\nsynci,483\nsyscall,486\nteq,487\nteqi,488\ntge,489\ntgei,490\ntgeiu,491\ntgeu,492\ntlbinv,493\ntlbinvf,495\ntlbp,497\ntlbr,498\ntlbwi,500\ntlbwr,502\ntlt,504\ntlti,505\ntltiu,506\ntltu,507\ntne,508\ntnei,509\ntrunc.l.d,510\ntrunc.l.s,510\ntrunc.w.d,511\ntrunc.w.s,511\nwait,512\nwrpgpr,514\nwsbh,515\nxor,516\nxori,517\n@MD00076-2B-MIPS1632-AFP-02.63.pdf [MIPS32 Architecture for Programmers Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture, MD00076 2.63, July 16, 2013]\nasmacro,65\nbeqz,68\nbnez,70\nbteqz,73\nbtnez,75\ncmp,77\ncmpi,78\njrc,90\nretnc,90\nneq,114\nrestore,118\nsave,123\nzeb,159\nzeh,160\n" }, { "path": "pypcode/processors/MIPS/data/manuals/mipsMic.idx", "content": "@MD00087-2B-MIPS64BIS-AFP-6.06.pdf [MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual, MD00087, 6.06, December 15, 2016]\nabs.d,44\nabs.ps,44\nabs.s,44\nadd,45\nadd.d,46\nadd.ps,46\nadd.s,46\naddi,47\naddiu,48\naddiupc,49\naddu,50\nalign,51\nalnv.ps,53\naluipc,55\nand,56\nandi,57\naui,58\nauipc,60\nb,61\nb.af.c,94\nb.at.c,94\nb.eq.c,94\nb.f.c,94\nb.ge.c,94\nb.gl.c,94\nb.gle.c,94\nb.gt.c,94\nb.le.c,94\nb.lt.c,94\nb.ne.c,94\nb.neq.c,94\nb.nge.c,94\nb.ngl.c,94\nb.ngle.c,94\nb.ngt.c,94\nb.nle.c,94\nb.nlt.c,94\nb.oge.c,94\nb.ogl.c,94\nb.ogt.c,94\nb.ole.c,94\nb.olt.c,94\nb.or.c,94\nb.saf.c,94\nb.sat.c,94\nb.seq.c,94\nb.sf.c,94\nb.sle.c,94\nb.slt.c,94\nb.sne.c,94\nb.soge.c,94\nb.sogt.c,94\nb.sor.c,94\nb.st.c,94\nb.sueq.c,94\nb.suge.c,94\nb.sugt.c,94\nb.sule.c,94\nb.sult.c,94\nb.sun.c,94\nb.sune.c,94\nb.t.c,94\nb.ueq.c,94\nb.uge.c,94\nb.ugt.c,94\nb.ule.c,94\nb.ult.c,94\nb.un.c,94\nb.une.c,94\nbal,62\nbalc,64\nbc,65\nbc1eqz,66\nbc1f,68\nbc1fl,70\nbc1nez,66\nbc1t,72\nbc1tl,74\nbc2eqz,76\nbc2f,78\nbc2fl,79\nbc2nez,76\nbc2t,81\nbc2tl,82\nbeq,84\nbeql,85\nbeqzalc,89\nbgez,87\nbgezal,88\nbgezalc,89\nbgezall,92\nbgezl,98\nbgtz,100\nbgtzalc,89\nbgtzl,101\nbitswap,103\nblez,105\nblezalc,89\nblezl,106\nbltz,108\nbltzal,109\nbltzalc,89\nbltzall,110\nbltzl,112\nbne,114\nbnel,115\nbnezalc,89\nbnvc,117\nbovc,117\nbreak,119\nc.af.d,120\nc.af.ps,120\nc.af.s,120\nc.at.d,120\nc.at.ps,120\nc.at.s,120\nc.eq.d,120\nc.eq.ps,120\nc.eq.s,120\nc.f.d,120\nc.f.ps,120\nc.f.s,120\nc.ge.d,120\nc.ge.ps,120\nc.ge.s,120\nc.gl.d,120\nc.gl.ps,120\nc.gl.s,120\nc.gle.d,120\nc.gle.ps,120\nc.gle.s,120\nc.gt.d,120\nc.gt.ps,120\nc.gt.s,120\nc.le.d,120\nc.le.ps,120\nc.le.s,120\nc.lt.d,120\nc.lt.ps,120\nc.lt.s,120\nc.ne.d,120\nc.ne.ps,120\nc.ne.s,120\nc.neq.d,120\nc.neq.ps,120\nc.neq.s,120\nc.nge.d,120\nc.nge.ps,120\nc.nge.s,120\nc.ngl.d,120\nc.ngl.ps,120\nc.ngl.s,120\nc.ngle.d,120\nc.ngle.ps,120\nc.ngle.s,120\nc.ngt.d,120\nc.ngt.ps,120\nc.ngt.s,120\nc.nle.d,120\nc.nle.ps,120\nc.nle.s,120\nc.nlt.d,120\nc.nlt.ps,120\nc.nlt.s,120\nc.oge.d,120\nc.oge.ps,120\nc.oge.s,120\nc.ogl.d,120\nc.ogl.ps,120\nc.ogl.s,120\nc.ogt.d,120\nc.ogt.ps,120\nc.ogt.s,120\nc.ole.d,120\nc.ole.ps,120\nc.ole.s,120\nc.olt.d,120\nc.olt.ps,120\nc.olt.s,120\nc.or.d,120\nc.or.ps,120\nc.or.s,120\nc.saf.d,120\nc.saf.ps,120\nc.saf.s,120\nc.sat.d,120\nc.sat.ps,120\nc.sat.s,120\nc.seq.d,120\nc.seq.ps,120\nc.seq.s,120\nc.sf.d,120\nc.sf.ps,120\nc.sf.s,120\nc.sle.d,120\nc.sle.ps,120\nc.sle.s,120\nc.slt.d,120\nc.slt.ps,120\nc.slt.s,120\nc.sne.d,120\nc.sne.ps,120\nc.sne.s,120\nc.soge.d,120\nc.soge.ps,120\nc.soge.s,120\nc.sogt.d,120\nc.sogt.ps,120\nc.sogt.s,120\nc.sor.d,120\nc.sor.ps,120\nc.sor.s,120\nc.st.d,120\nc.st.ps,120\nc.st.s,120\nc.sueq.d,120\nc.sueq.ps,120\nc.sueq.s,120\nc.suge.d,120\nc.suge.ps,120\nc.suge.s,120\nc.sugt.d,120\nc.sugt.ps,120\nc.sugt.s,120\nc.sule.d,120\nc.sule.ps,120\nc.sule.s,120\nc.sult.d,120\nc.sult.ps,120\nc.sult.s,120\nc.sun.d,120\nc.sun.ps,120\nc.sun.s,120\nc.sune.d,120\nc.sune.ps,120\nc.sune.s,120\nc.t.d,120\nc.t.ps,120\nc.t.s,120\nc.ueq.d,120\nc.ueq.ps,120\nc.ueq.s,120\nc.uge.d,120\nc.uge.ps,120\nc.uge.s,120\nc.ugt.d,120\nc.ugt.ps,120\nc.ugt.s,120\nc.ule.d,120\nc.ule.ps,120\nc.ule.s,120\nc.ult.d,120\nc.ult.ps,120\nc.ult.s,120\nc.un.d,120\nc.un.ps,120\nc.un.s,120\nc.une.d,120\nc.une.ps,120\nc.une.s,120\ncache,124\ncache,125\ncachee,130\nceil.l.d,136\nceil.l.s,136\nceil.w.d,137\nceil.w.s,137\ncfc1,138\ncfc2,140\nclass.d,141\nclass.s,141\nclo,143\nclz,144\ncmp.af.d,145\ncmp.af.s,145\ncmp.at.d,145\ncmp.at.s,145\ncmp.eq.d,145\ncmp.eq.s,145\ncmp.f.d,145\ncmp.f.s,145\ncmp.ge.d,145\ncmp.ge.s,145\ncmp.gl.d,145\ncmp.gl.s,145\ncmp.gle.d,145\ncmp.gle.s,145\ncmp.gt.d,145\ncmp.gt.s,145\ncmp.le.d,145\ncmp.le.s,145\ncmp.lt.d,145\ncmp.lt.s,145\ncmp.ne.d,145\ncmp.ne.s,145\ncmp.neq.d,145\ncmp.neq.s,145\ncmp.nge.d,145\ncmp.nge.s,145\ncmp.ngl.d,145\ncmp.ngl.s,145\ncmp.ngle.d,145\ncmp.ngle.s,145\ncmp.ngt.d,145\ncmp.ngt.s,145\ncmp.nle.d,145\ncmp.nle.s,145\ncmp.nlt.d,145\ncmp.nlt.s,145\ncmp.oge.d,145\ncmp.oge.s,145\ncmp.ogl.d,145\ncmp.ogl.s,145\ncmp.ogt.d,145\ncmp.ogt.s,145\ncmp.ole.d,145\ncmp.ole.s,145\ncmp.olt.d,145\ncmp.olt.s,145\ncmp.or.d,145\ncmp.or.s,145\ncmp.saf.d,145\ncmp.saf.s,145\ncmp.sat.d,145\ncmp.sat.s,145\ncmp.seq.d,145\ncmp.seq.s,145\ncmp.sf.d,145\ncmp.sf.s,145\ncmp.sle.d,145\ncmp.sle.s,145\ncmp.slt.d,145\ncmp.slt.s,145\ncmp.sne.d,145\ncmp.sne.s,145\ncmp.soge.d,145\ncmp.soge.s,145\ncmp.sogt.d,145\ncmp.sogt.s,145\ncmp.sor.d,145\ncmp.sor.s,145\ncmp.st.d,145\ncmp.st.s,145\ncmp.sueq.d,145\ncmp.sueq.s,145\ncmp.suge.d,145\ncmp.suge.s,145\ncmp.sugt.d,145\ncmp.sugt.s,145\ncmp.sule.d,145\ncmp.sule.s,145\ncmp.sult.d,145\ncmp.sult.s,145\ncmp.sun.d,145\ncmp.sun.s,145\ncmp.sune.d,145\ncmp.sune.s,145\ncmp.t.d,145\ncmp.t.s,145\ncmp.ueq.d,145\ncmp.ueq.s,145\ncmp.uge.d,145\ncmp.uge.s,145\ncmp.ugt.d,145\ncmp.ugt.s,145\ncmp.ule.d,145\ncmp.ule.s,145\ncmp.ult.d,145\ncmp.ult.s,145\ncmp.un.d,145\ncmp.un.s,145\ncmp.une.d,145\ncmp.une.s,145\ncop2,150\ncrc32b,152\ncrc32cb,155\ncrc32cd,155\ncrc32ch,155\ncrc32cw,155\ncrc32d,152\ncrc32h,152\ncrc32w,152\nctc1,158\nctc2,161\ncvt.d.l,162\ncvt.d.s,162\ncvt.d.w,162\ncvt.l.d,163\ncvt.l.s,163\ncvt.ps.s,164\ncvt.s.d,168\ncvt.s.l,168\ncvt.s.pl,166\ncvt.s.pu,167\ncvt.s.w,168\ncvt.w.d,169\ncvt.w.s,169\ndadd,170\ndaddi,171\ndaddiu,172\ndaddu,173\ndahi,58\ndalign,51\ndati,58\ndaui,58\ndbitswap,103\ndclo,174\ndclz,175\nddiv,176\nddivu,177\nderet,178\ndext,179\ndextm,181\ndextu,183\ndi,185\ndins,186\ndinsm,188\ndinsu,190\ndiv,192\ndiv.d,197\ndiv.s,197\ndivu,194\ndlsa,294\ndmfc0,199\ndmfc1,200\ndmfc2,201\ndmod,194\ndmodu,194\ndmtc0,202\ndmtc1,203\ndmtc2,204\ndmuh,363\ndmuhu,363\ndmul,363\ndmult,205\ndmultu,206\ndmulu,363\ndrotr,207\ndrotr32,208\ndrotrv,209\ndsbh,210\ndshd,211\ndsll,212\ndsll32,213\ndsllv,214\ndsra,215\ndsra32,216\ndsrav,217\ndsrl,218\ndsrl32,219\ndsrlv,220\ndsub,221\ndsubu,222\ndvp,223\nehb,226\nei,227\neret,228\neretnc,230\nevp,232\next,234\nfloor.l.d,236\nfloor.l.s,236\nfloor.w.d,237\nfloor.w.s,237\nginvi,239\nginvt,241\nins,244\nj,246\njal,247\njalr,248\njalr.hb,250\njalx,253\njialc,255\njic,257\njr,258\njr.hb,260\nlb,263\nlbe,264\nlbu,265\nlbue,266\nld,267\nldc1,268\nldc2,269\nldl,271\nldpc,273\nldr,274\nldxc1,276\nlh,277\nlhe,278\nlhu,279\nlhue,280\nll,281\nlld,283\nlldp,288\nlle,286\nllwp,290\nllwpe,292\nlsa,294\nlui,295\nluxc1,296\nlw,297\nlwc1,298\nlwc2,299\nlwe,300\nlwl,301\nlwle,304\nlwpc,307\nlwr,308\nlwre,311\nlwre,312\nlwu,315\nlwupc,316\nlwxc1,317\nmadd,318\nmadd.d,319\nmadd.ps,319\nmadd.s,319\nmaddf.d,321\nmaddf.s,321\nmaddu,323\nmax.d,324\nmax.s,324\nmaxa.d,324\nmaxa.s,324\nmfc0,328\nmfc1,329\nmfc2,330\nmfhc0,331\nmfhc1,333\nmfhc2,334\nmfhi,335\nmflo,336\nmin.d,324\nmin.s,324\nmina.d,324\nmina.s,324\nmod,194\nmodu,194\nmov.d,337\nmov.ps,337\nmov.s,337\nmovf,338\nmovf.d,339\nmovf.ps,339\nmovf.s,339\nmovn,341\nmovn.d,342\nmovn.ps,342\nmovn.s,342\nmovt,343\nmovt.d,344\nmovt.ps,344\nmovt.s,344\nmovz,346\nmovz.d,347\nmovz.ps,347\nmovz.s,347\nmsub,348\nmsub.d,349\nmsub.ps,349\nmsub.s,349\nmsubf.d,321\nmsubf.s,321\nmsubu,351\nmtc0,352\nmtc1,354\nmtc2,355\nmthc0,356\nmthc1,358\nmthc2,359\nmthi,360\nmtlo,361\nmuh,363\nmuhu,363\nmul,362\nmul.d,366\nmul.ps,366\nmul.s,366\nmult,367\nmultu,368\nmulu,363\nnal,369\nneg.d,370\nneg.ps,370\nneg.s,370\nnmadd.d,371\nnmadd.ps,371\nnmadd.s,371\nnmsub.d,373\nnmsub.ps,373\nnmsub.s,373\nnop,375\nnor,376\nor,377\nori,378\npause,379\npll.ps,381\nplu.ps,382\npref,383\nprefe,387\nprefx,391\npul.ps,392\npuu.ps,393\nrdhwr,394\nrdpgpr,397\nrecip.d,398\nrecip.s,398\nrint.d,399\nrint.s,399\nrotr,401\nrotrv,402\nround.l.d,403\nround.l.s,403\nround.w.d,404\nround.w.s,404\nrsqrt.d,405\nrsqrt.s,405\nsb,406\nsbe,407\nsc,408\nscd,412\nscdp,415\nsce,418\nscwp,422\nscwpe,426\nsd,429\nsdbbp,430\nsdc1,431\nsdc2,432\nsdl,433\nsdr,435\nsdxc1,437\nseb,438\nseh,439\nsel.d,441\nsel.s,441\nseleqz,442\nseleqz.d,444\nseleqz.s,444\nselnez,442\nsh,446\nshe,447\nsigrie,448\nsll,449\nsllv,450\nslt,451\nslti,452\nsltiu,453\nsltu,454\nsqrt.d,455\nsqrt.s,455\nsra,456\nsrav,457\nsrl,458\nsrlv,459\nssnop,460\nsub,461\nsub.d,462\nsub.ps,462\nsub.s,462\nsubu,463\nsuxc1,464\nsw,465\nswc2,467\nswe,468\nswl,469\nswle,471\nswr,473\nswre,475\nswxc1,477\nsync,478\nsynci,483\nsyscall,486\nteq,487\nteqi,488\ntge,489\ntgei,490\ntgeiu,491\ntgeu,492\ntlbinv,493\ntlbinvf,495\ntlbp,497\ntlbr,498\ntlbwi,500\ntlbwr,502\ntlt,504\ntlti,505\ntltiu,506\ntltu,507\ntne,508\ntnei,509\ntrunc.l.d,510\ntrunc.l.s,510\ntrunc.w.d,511\ntrunc.w.s,511\nwait,512\nwrpgpr,514\nwsbh,515\nxor,516\nxori,517\n@MD00594-2B-microMIPS64-AFP-6.05.pdf [MIPS Architecture for Programmers Volume II-B: microMIPS64 Instruction Set, MD00594, 6.05, December 15, 2016]\nabs.d,128\nabs.s,128\nadd,129\nadd.d,130\nadd.s,130\naddiu,131\naddiupc,132\naddiur1sp,69\naddiur2,70\naddius5,72\naddiusp,74\naddu,133\naddu16,76\nalign,134\naluipc,136\nand,137\nand16,77\nandi,138\nandi16,78\naui,139\nauipc,141\nb.af.c,149\nb.at.c,149\nb.eq.c,149\nb.f.c,149\nb.ge.c,149\nb.gl.c,149\nb.gle.c,149\nb.gt.c,149\nb.le.c,149\nb.lt.c,149\nb.ne.c,149\nb.neq.c,149\nb.nge.c,149\nb.ngl.c,149\nb.ngle.c,149\nb.ngt.c,149\nb.nle.c,149\nb.nlt.c,149\nb.oge.c,149\nb.ogl.c,149\nb.ogt.c,149\nb.ole.c,149\nb.olt.c,149\nb.or.c,149\nb.saf.c,149\nb.sat.c,149\nb.seq.c,149\nb.sf.c,149\nb.sle.c,149\nb.slt.c,149\nb.sne.c,149\nb.soge.c,149\nb.sogt.c,149\nb.sor.c,149\nb.st.c,149\nb.sueq.c,149\nb.suge.c,149\nb.sugt.c,149\nb.sule.c,149\nb.sult.c,149\nb.sun.c,149\nb.sune.c,149\nb.t.c,149\nb.ueq.c,149\nb.uge.c,149\nb.ugt.c,149\nb.ule.c,149\nb.ult.c,149\nb.un.c,149\nb.une.c,149\nbalc,142\nbc,152\nbc16,79\nbc1eqzc,143\nbc1nezc,143\nbc2eqzc,145\nbc2nezc,145\nbeqzalc,147\nbeqzc16,80\nbgezalc,147\nbgtzalc,147\nbitswap,154\nblezalc,147\nbltzalc,147\nbnezalc,147\nbnezc16,81\nbnvc,156\nbovc,156\nbreak,153\nbreak16,82\ncache,158\ncachee,164\nceil.l.d,170\nceil.l.s,170\nceil.w.d,171\nceil.w.s,171\ncfc1,172\ncfc2,174\nclass.d,175\nclass.s,175\nclo,177\nclz,178\ncmp.af.d,179\ncmp.af.s,179\ncmp.at.d,179\ncmp.at.s,179\ncmp.eq.d,179\ncmp.eq.s,179\ncmp.f.d,179\ncmp.f.s,179\ncmp.ge.d,179\ncmp.ge.s,179\ncmp.gl.d,179\ncmp.gl.s,179\ncmp.gle.d,179\ncmp.gle.s,179\ncmp.gt.d,179\ncmp.gt.s,179\ncmp.le.d,179\ncmp.le.s,179\ncmp.lt.d,179\ncmp.lt.s,179\ncmp.ne.d,179\ncmp.ne.s,179\ncmp.neq.d,179\ncmp.neq.s,179\ncmp.nge.d,179\ncmp.nge.s,179\ncmp.ngl.d,179\ncmp.ngl.s,179\ncmp.ngle.d,179\ncmp.ngle.s,179\ncmp.ngt.d,179\ncmp.ngt.s,179\ncmp.nle.d,179\ncmp.nle.s,179\ncmp.nlt.d,179\ncmp.nlt.s,179\ncmp.oge.d,179\ncmp.oge.s,179\ncmp.ogl.d,179\ncmp.ogl.s,179\ncmp.ogt.d,179\ncmp.ogt.s,179\ncmp.ole.d,179\ncmp.ole.s,179\ncmp.olt.d,179\ncmp.olt.s,179\ncmp.or.d,179\ncmp.or.s,179\ncmp.saf.d,179\ncmp.saf.s,179\ncmp.sat.d,179\ncmp.sat.s,179\ncmp.seq.d,179\ncmp.seq.s,179\ncmp.sf.d,179\ncmp.sf.s,179\ncmp.sle.d,179\ncmp.sle.s,179\ncmp.slt.d,179\ncmp.slt.s,179\ncmp.sne.d,179\ncmp.sne.s,179\ncmp.soge.d,179\ncmp.soge.s,179\ncmp.sogt.d,179\ncmp.sogt.s,179\ncmp.sor.d,179\ncmp.sor.s,179\ncmp.st.d,179\ncmp.st.s,179\ncmp.sueq.d,179\ncmp.sueq.s,179\ncmp.suge.d,179\ncmp.suge.s,179\ncmp.sugt.d,179\ncmp.sugt.s,179\ncmp.sule.d,179\ncmp.sule.s,179\ncmp.sult.d,179\ncmp.sult.s,179\ncmp.sun.d,179\ncmp.sun.s,179\ncmp.sune.d,179\ncmp.sune.s,179\ncmp.t.d,179\ncmp.t.s,179\ncmp.ueq.d,179\ncmp.ueq.s,179\ncmp.uge.d,179\ncmp.uge.s,179\ncmp.ugt.d,179\ncmp.ugt.s,179\ncmp.ule.d,179\ncmp.ule.s,179\ncmp.ult.d,179\ncmp.ult.s,179\ncmp.un.d,179\ncmp.un.s,179\ncmp.une.d,179\ncmp.une.s,179\ncop2,184\ncrc32b,186\ncrc32cb,189\ncrc32cd,189\ncrc32ch,189\ncrc32cw,189\ncrc32d,186\ncrc32h,186\ncrc32w,186\nctc1,192\nctc2,195\ncvt.d.l,196\ncvt.d.s,196\ncvt.d.w,196\ncvt.l.d,197\ncvt.l.s,197\ncvt.s.d,198\ncvt.s.l,198\ncvt.s.w,198\ncvt.w.d,199\ncvt.w.s,199\ndadd,200\ndaddiu,201\ndaddu,202\ndahi,139\ndalign,134\ndati,139\ndaui,139\ndbitswap,154\ndclo,203\ndclz,204\nddiv,220\nddivu,220\nderet,205\ndext,206\ndextm,208\ndextu,210\ndi,212\ndins,213\ndinsm,215\ndinsu,217\ndiv,220\ndiv.d,219\ndiv.s,219\ndivu,220\ndlsa,300\ndmfc0,224\ndmfc1,225\ndmfc2,226\ndmod,220\ndmodu,220\ndmtc0,227\ndmtc1,228\ndmtc2,229\ndmuh,330\ndmuhu,330\ndmul,330\ndmulu,330\ndrotr,230\ndrotr32,231\ndrotrv,232\ndsbh,233\ndshd,234\ndsll,235\ndsll32,236\ndsllv,237\ndsra,238\ndsra32,239\ndsrav,240\ndsrl,241\ndsrl32,242\ndsrlv,243\ndsub,244\ndsubu,245\ndvp,246\nehb,249\nei,250\neret,251\neretnc,252\nevp,254\next,256\nfloor.l.d,258\nfloor.l.s,258\nfloor.w.d,259\nfloor.w.s,259\nginvi,260\nginvt,262\nins,265\njalrc,267\njalrc.hb,269\njalrc16,83\njialc,272\njic,274\njrc16,87\njrcaddiusp,85\nlb,276\nlbe,277\nlbu,278\nlbu16,88\nlbue,279\nld,280\nldc1,281\nldc2,282\nldm,90\nldp,92\nldpc,283\nlh,284\nlhe,285\nlhu,286\nlhu16,94\nlhue,287\nli16,95\nll,288\nlld,290\nlldp,294\nlle,291\nllwp,296\nllwpe,298\nlsa,300\nlui,301\nlw,302\nlw16,97\nlwc1,303\nlwc2,304\nlwe,305\nlwgp,102\nlwm16,100\nlwm32,98\nlwp,96\nlwpc,306\nlwsp,103\nlwu,308\nlwupc,307\nmaddf.d,309\nmaddf.s,309\nmax.d,311\nmax.s,311\nmaxa.d,311\nmaxa.s,311\nmfc0,315\nmfc1,316\nmfc2,317\nmfhc0,318\nmfhc1,320\nmfhc2,321\nmin.d,311\nmin.s,311\nmina.d,311\nmina.s,311\nmod,220\nmodu,220\nmov.d,322\nmov.s,322\nmove16,104\nmovep,105\nmsubf.d,309\nmsubf.s,309\nmtc0,323\nmtc1,324\nmtc2,325\nmthc0,326\nmthc1,328\nmthc2,329\nmuh,330\nmuhu,330\nmul,330\nmul.d,333\nmul.s,333\nmulu,330\nneg.d,334\nneg.s,334\nnop,335\nnor,336\nnot16,107\nor,337\nor16,108\nori,338\npause,339\npref,341\nprefe,345\nrdhwr,349\nrdpgpr,352\nrecip.d,353\nrecip.s,353\nrotr,356\nrotrv,357\nround.l.d,358\nround.l.s,358\nround.w.d,359\nround.w.s,359\nrsqrt.d,360\nrsqrt.s,360\nsb,361\nsb16,109\nsbe,362\nsc,363\nscd,370\nscdp,373\nsce,367\nscwp,376\nscwpe,380\nsd,383\nsdbbp,384\nsdbbp16,110\nsdc1,385\nsdc2,386\nsdm,111\nsdp,113\nseb,387\nseh,388\nseleqz,391\nseleqz.d,393\nseleqz.s,393\nselnez,391\nsh,395\nsh16,114\nshe,396\nsigrie,397\nsll,398\nsll16,115\nsllv,399\nslt,400\nslti,401\nsltiu,402\nsltu,403\nsqrt.d,404\nsqrt.s,404\nsra,405\nsrav,406\nsrl,407\nsrl16,116\nsrlv,408\nssnop,409\nsub,410\nsub.d,411\nsub.s,411\nsubu,412\nsubu16,118\nsw,413\nsw16,119\nswc2,416\nswe,414\nswm16,121\nswm32,123\nswp,125\nswsp,120\nsync,417\nsynci,422\nsyscall,425\nteq,426\ntge,427\ntgeu,428\ntlbinv,430\ntlbinvf,433\ntlbp,435\ntlbr,436\ntlbwi,438\ntlbwr,440\ntlt,442\ntltu,443\ntne,444\ntrunc.l.d,445\ntrunc.l.s,445\ntrunc.w.d,446\ntrunc.w.s,446\nwait,447\nwrpgpr,449\nwsbh,450\nxor,451\nxor16,126\nxori,452\n@MIPS_Architecture_microMIPS32_InstructionSet_AFP_P_MD00582_06.04.pdf [MIPS Architecture for Programmers Volume II-B: microMIPS32 Instruction Set, MD00582, 6.04, June 6, 2016]\naddiur1sp,65\naddiur2,66\naddius5,67\naddiusp,69\naddu16,71\nand16,72\nandi16,73\nbc16,74\nbeqzc16,75\nbnezc16,76\nbreak16,77\njalrc16,78\njrcaddiusp,80\njrc16,82\nlbu16,83\nlhu16,85\nli16,86\nlwp,87\nlw16,88\nlwm32,89\nlwm16,91\nlwgp,93\nlwsp,94\nmove16,95\nmovep,96\nnot16,98\nor16,99\nsb16,100\nsdbbp16,101\nsh16,102\nsll16,103\nsrl16,104\nsubu16,105\nsw16,106\nswsp,107\nswm16,108\nswm32,110\nswp,112\nxor16,113\nabs.s,115\nabs.d,115\nadd,116\nadd.s,117\nadd.d,117\naddiu,118\naddiupc,119\naddu,120\nalign,121\naluipc,123\nand,124\nandi,125\naui,126\nauipc,127\nbalc,128\nbc1eqzc,129\nbc1nezc,129\nbc2eqzc,131\nbc2nezc,131\nblezalc,133\nbgezalc,133\nbgtzalc,133\nbltzalc,133\nbeqzalc,133\nbnezalc,133\nb.f.c,135\nb.un.c,135\nb.eq.c,135\nb.ueq.c,135\nb.olt.c,135\nb.ult.c,135\nb.ole.c,135\nb.ule.c,135\nb.sf.c,135\nb.ngle.c,135\nb.seq.c,135\nb.ngl.c,135\nb.lt.c,135\nb.nge.c,135\nb.le.c,135\nb.ngt.c,135\nbc,138\nbreak,139\nbitswap,140\nbovc,142\nbnvc,142\ncache,144\ncachee,150\nceil.l.s,156\nceil.l.d,156\nceil.w.s,157\nceil.w.d,157\ncfc1,158\ncfc2,160\nclass.s,161\nclass.d,161\nclo,163\nclz,164\ncmp.f.s,165\ncmp.un.s,165\ncmp.eq.s,165\ncmp.ueq.s,165\ncmp.olt.s,165\ncmp.ult.s,165\ncmp.ole.s,165\ncmp.ule.s,165\ncmp.sf.s,165\ncmp.ngle.s,165\ncmp.seq.s,165\ncmp.ngl.s,165\ncmp.lt.s,165\ncmp.nge.s,165\ncmp.le.s,165\ncmp.ngt.s,165\ncmp.f.d,165\ncmp.un.d,165\ncmp.eq.d,165\ncmp.ueq.d,165\ncmp.olt.d,165\ncmp.ult.d,165\ncmp.ole.d,165\ncmp.ule.d,165\ncmp.sf.d,165\ncmp.ngle.d,165\ncmp.seq.d,165\ncmp.ngl.d,165\ncmp.lt.d,165\ncmp.nge.d,165\ncmp.le.d,165\ncmp.ngt.d,165\ncop2,170\nctc1,171\nctc2,174\ncvt.d.s,175\ncvt.d.w,175\ncvt.d.l,175\ncvt.l.s,176\ncvt.l.d,176\ncvt.s.d,177\ncvt.s.w,177\ncvt.s.l,177\ncvt.w.s,178\ncvt.w.d,178\nderet,179\ndi,180\ndiv.s,181\ndiv.d,181\ndiv,182\nmod,182\ndivu,182\nmodu,182\ndvp,185\nehb,188\nei,189\neret,190\neretnc,191\next,193\nevp,196\nfloor.l.s,198\nfloor.l.d,198\nfloor.w.s,199\nfloor.w.d,199\nins,200\njalrc,202\njalrc.hb,204\njialc,207\njic,209\nlb,211\nlbe,212\nlbu,213\nlbue,214\nldc1,215\nldc2,216\nlh,217\nlhe,218\nlhu,219\nlhue,220\nll,221\nlle,223\nllwp,226\nllwpe,228\nlsa,230\nlui,231\nlw,232\nlwc1,233\nlwc2,234\nlwe,235\nlwpc,236\nmaddf.s,237\nmaddf.d,237\nmsubf.s,237\nmsubf.d,237\nmax.s,239\nmax.d,239\nmin.s,239\nmin.d,239\nmaxa.s,239\nmaxa.d,239\nmina.s,239\nmina.d,239\nmfc0,243\nmfc1,244\nmfc2,245\nmfhc0,246\nmfhc1,247\nmfhc2,248\nmov.s,249\nmov.d,249\nmtc0,250\nmtc1,251\nmtc2,252\nmthc0,253\nmthc1,254\nmthc2,255\nmul,256\nmuh,256\nmulu,256\nmuhu,256\nmul.s,258\nmul.d,258\nneg.s,259\nneg.d,259\nnop,260\nnor,261\nor,262\nori,263\npause,264\npref,266\nprefe,270\nrdhwr,274\nrdpgpr,277\nrecip.s,278\nrecip.d,278\nrotr,281\nrotrv,282\nround.l.s,283\nround.l.d,283\nround.w.s,284\nround.w.d,284\nrsqrt.s,285\nrsqrt.d,285\nsb,286\nsbe,287\nsc,288\nsce,291\nscwp,294\nscwpe,298\nsdbbp,301\nsdc1,302\nsdc2,303\nseb,304\nseh,305\nseleqz,307\nselnez,307\nseleqz.s,309\nseleqz.d,309\nsh,311\nshe,312\nsigrie,313\nsll,314\nsllv,315\nslt,316\nslti,317\nsltiu,318\nsltu,319\nsqrt.s,320\nsqrt.d,320\nsra,321\nsrav,322\nsrl,323\nsrlv,324\nssnop,325\nsub,326\nsub.s,327\nsub.d,327\nsubu,328\nsw,329\nswe,330\nswc2,332\nsync,333\nsynci,338\nsyscall,341\nteq,342\ntge,343\ntgeu,344\ntlbinv,346\ntlbinvf,349\ntlbp,351\ntlbr,352\ntlbwi,354\ntlbwr,356\ntlt,358\ntltu,359\ntne,360\ntrunc.l.s,361\ntrunc.l.d,361\ntrunc.w.s,362\ntrunc.w.d,362\nwait,363\nwrpgpr,365\nwsbh,366\nxor,367\nxori,368\n" }, { "path": "pypcode/processors/MIPS/data/manuals/r4000.idx", "content": "@r4000.pdf[MIPS R4000 Microprocessor User's Manual, Second Edition, July 2005]\nadd\t\t, 479\naddi\t\t, 480\naddiu\t\t, 481\naddu\t\t, 482\nand\t\t, 483\nandi\t\t, 484\nbczf\t\t, 485\nbczfl\t\t, 487\nbczt\t\t, 489\nbcztl\t\t, 491\nbeq\t\t, 493\nbeql\t\t, 494\nbgez\t\t, 495\nbgezal\t, 496\nbgezall\t, 497\nbgezl\t\t, 498\nbgtz\t\t, 499\nbgtzl\t\t, 500\nblez\t\t, 501\nblezl\t\t, 502\nbltz\t\t, 503\nbltzal\t, 504\nbltzall\t, 505\nbltzl\t\t, 506\nbne\t\t, 507\nbnel\t\t, 508\nbreak\t\t, 509\ncache\t\t, 510\ncfc\t\t, 516\ncop\t\t, 517\nctc\t\t, 518\ndadd\t\t, 519\ndaddi\t\t, 520\ndaddiu\t, 521\ndaddu\t\t, 522\nddiv\t\t, 523\nddivu\t\t, 524\ndiv\t\t, 525\ndivu\t\t, 527\ndmfc0\t\t, 529\ndmtc0\t\t, 530\ndmult\t\t, 531\ndmultu\t, 532\ndsll\t\t, 533\ndsllv\t\t, 534\ndsll32\t, 535\ndsra\t\t, 536\ndsrav\t\t, 537\ndsra32\t, 538\ndsrl\t\t, 539\ndsrlv\t\t, 540\ndsrl32\t, 541\ndsub\t\t, 542\ndsubu\t\t, 543\neret\t\t, 544\nj\t\t, 545\njal\t\t, 546\njalr\t\t, 547\njr\t\t, 548\nlb\t\t, 549\nlbu\t\t, 550\nld\t\t, 551\nldc\t\t, 552\nldl\t\t, 554\nldr\t\t, 557\nlh\t\t, 560\nlhu\t\t, 561\nll\t\t, 562\nlld\t\t, 564\nlui\t\t, 566\nlw\t\t, 567\nlwc\t\t, 568\nlwl\t\t, 570\nlwr\t\t, 573\nlwu\t\t, 576\nmfc0\t\t, 577\nmfcz\t\t, 578\nmfhi\t\t, 580\nmflo\t\t, 581\nmtc0\t\t, 582\nmtcz\t\t, 583\nmthi\t\t, 584\nmtlo\t\t, 585\nmult\t\t, 586\nmultu\t\t, 588\nnor\t\t, 590\nor\t\t, 591\nori\t\t, 592\nsb\t\t, 593\nsc\t\t, 594\nscd\t\t, 596\nsd\t\t, 598\nsdcz\t\t, 599\nsdl\t\t, 601\nsdr\t\t, 604\nsh\t\t, 607\nsll\t\t, 608\nsllv\t\t, 609\nslt\t\t, 610\nslti\t\t, 611\nsltiu\t\t, 612\nsltu\t\t, 613\nsra\t\t, 614\nsrav\t\t, 615\nsrl\t\t, 616\nsrlv\t\t, 617\nsub\t\t, 618\nsubu\t\t, 619\nsw\t\t, 620\nswcz\t\t, 621\nswl\t\t, 623\nswr\t\t, 626\nsync\t\t, 629\nsyscall\t, 630\nteq\t\t, 631\nteqi\t\t, 632\ntge\t\t, 633\ntgei\t\t, 634\ntgeiu\t\t, 635\ntgeu\t\t, 636\ntlbp\t\t, 637\ntlbr\t\t, 638\ntlbwi\t\t, 639\ntlbwr\t\t, 640\ntlt\t\t, 641\ntlti\t\t, 642\ntltiu\t\t, 643\ntltu\t\t, 644\ntne\t\t, 645\ntnei\t\t, 646\nxor\t\t, 647\nxori\t\t, 648\nabs\t\t, 663\nadd\t\t, 664\nbc1f\t\t, 665\nbc1fl \t, 666\nbc1t\t\t, 667\nbc1tl\t\t, 668\nc.\t\t, 669\nceil.l.\t, 671\nceil.W.\t, 673\ncfc1\t\t, 675\nctc1\t\t, 676\ncvt.\t\t, 677\ndiv.\t\t, 681\ndmfc1\t\t, 682\ndmtc1\t\t, 683\nfloor.\t, 684\nldc1\t\t, 688\nlwc1\t\t, 690\nmfc1\t\t, 692\nmov.\t\t, 693\nmtc1\t\t, 694\nmul.\t\t, 695\nneg.\t\t, 696\nround.\t, 697\nsdc1\t\t, 701\nsqrt\t\t, 703\nsub\t\t, 704\nswc1\t\t, 705\ntrunc\t\t, 707\n" }, { "path": "pypcode/processors/MIPS/data/patterns/MIPS_BE_patterns.xml", "content": "\n \n \n 0x03e00008 0x........ \n 0x03e00008 0x........ 0x00000000 \n 0x03e00008 0x........ 0x00000000 0x00000000 \n 0x03e00008 0x........ 0x00000000 0x00000000 0x00000000 \n 000010.. 0x...... 0.100111 0xbd 0....... ......00 \n 000010.. 0x...... 0.100111 0xbd 0....... ......00 0x00000000 \n 0x1000.... 0.100111 0xbd 0....... ......00 \n 0x1000.... 0.100111 0xbd 0....... ......00 0x00000000 \n 0x03 0x20 00000... ..001000 0.100111 0xbd 0x0. 0x.. \n \n \n 0.100111 10111101 1....... ......00 \n 0x3c...... 0.100111 0xbd 1....... ......00 \n 100011.. 0x...... 0.100111 0xbd 1....... ......00 \n 0x3c...... 100011.. 0x...... 0.100111 0xbd 1....... ......00 \n 0x3c1c.... 0.100111 0x9c.... \n \n \n \n \n \n 0x03e00008 0x........ \n 0x03e00008 0x........ 0x00000000 \n 0x03e00008 0x........ 0x00000000 0x00000000 \n 0x03e00008 0x........ 0x00000000 0x00000000 0x00000000 \n 000010.. 0x...... 0.100111 0xbd 0....... ......00 \n 0x1000.... 0.100111 0xbd 0....... ......00 \n 0x03 0x20 00000... ..001000 0.100111 0xbd 0x0. 0x.. \n \n \n 0x3c06.... \n \n \n \n\n \n 01100111 10111101 1....... ......00 0xff 0xbc 0....... ......00 \n \n \n \n\n \n 00100111 10111101 1....... ......00 0xaf 0xbc 0....... ......00 \n \n \n \n \n \n 0x3c 0x0f 0x.. 0x.. 0x8d 0xf9 0x.. 0x.. 0x03 0x20 00000... 0x08 0x25 0xf8 0x.. 0x.. \n \n \n \n\n \n 0xb2 0x03 0x9a 0x60 0x65 .....010 0xeb 0x00 0x65 .....011 \n \n \n \n \n \n" }, { "path": "pypcode/processors/MIPS/data/patterns/MIPS_LE_patterns.xml", "content": "\n \n \n 0x0800e003 0x........ \n 0x0800e003 0x........ 0x00000000 \n 0x0800e003 0x........ 0x00000000 0x00000000 \n 0x0800e003 0x........ 0x00000000 0x00000000 0x00000000 \n 0x...... 000010.. ......00 0....... 0xbd 0.100111 \n 0x....0010 ......00 0....... 0xbd 0.100111 \n ..001000 00000... 0x20 0x03 0x0. 0x.. 0xbd 0.100111 \n \n \n ......00 1....... 10111101 00100111 \n 0x......3c ......00 1....... 0xbd 0.100111 \n 0x...... 100011.. ......00 1....... 0xbd 0.100111 \n 0x......3c 0x...... 100011.. ......00 1....... 0xbd 0.100111 \n 0x....1c3c 0x....9c 0.100111 \n \n \n \n \n \n 0x0800e003 0x........ \n 0x0800e003 0x........ 0x00000000 \n 0x0800e003 0x........ 0x00000000 0x00000000 \n 0x0800e003 0x........ 0x00000000 0x00000000 0x00000000 \n 0x...... 000010.. ......00 0....... 0xbd 0.100111 \n 0x....0010 ......00 0....... 0xbd 0.100111 \n ..001000 00000... 0x20 0x03 0x0. 0x.. 0xbd 0.100111 \n \n \n 0x....063c \n \n \n \n\n \n ......00 1....... 10111101 01100111 ......00 0....... 0xbc 0xff \n \n \n \n\n \n ......00 1....... 10111101 00100111 ......00 0....... 0xbc 0xaf \n \n \n \n\n \n 0x.. 0x.. 0x0f 0x3c 0x.. 0x.. 0xf9 0x8d 0x08 00000... 0x20 0x03 0x.. 0x.. 0xf8 0x25 \n \n \n \n\n \n 0x03 0xb2 0x60 0x9a .....010 0x65 0x00 0xeb .....011 0x65 \n \n \n \n \n \n" }, { "path": "pypcode/processors/MIPS/data/patterns/patternconstraints.xml", "content": "\n \n MIPS_BE_patterns.xml\n \n \n MIPS_LE_patterns.xml\n \n\n" }, { "path": "pypcode/processors/NDS32/data/languages/lsmw.sinc", "content": "Dreg: a0 is a0 & regNum=0 { export a0; }\nDreg: a1 is a1 & regNum=1 { export a1; }\nDreg: a2 is a2 & regNum=2 { export a2; }\nDreg: a3 is a3 & regNum=3 { export a3; }\nDreg: a4 is a4 & regNum=4 { export a4; }\nDreg: a5 is a5 & regNum=5 { export a5; }\nDreg: s0 is s0 & regNum=6 { export s0; }\nDreg: s1 is s1 & regNum=7 { export s1; }\nDreg: s2 is s2 & regNum=8 { export s2; }\nDreg: s3 is s3 & regNum=9 { export s3; }\nDreg: s4 is s4 & regNum=10 { export s4; }\nDreg: s5 is s5 & regNum=11 { export s5; }\nDreg: s6 is s6 & regNum=12 { export s6; }\nDreg: s7 is s7 & regNum=13 { export s7; }\nDreg: s8 is s8 & regNum=14 { export s8; }\nDreg: ta is ta & regNum=15 { export ta; }\nDreg: t0 is t0 & regNum=16 { export t0; }\nDreg: t1 is t1 & regNum=17 { export t1; }\nDreg: t2 is t2 & regNum=18 { export t2; }\nDreg: t3 is t3 & regNum=19 { export t3; }\nDreg: t4 is t4 & regNum=20 { export t4; }\nDreg: t5 is t5 & regNum=21 { export t5; }\nDreg: t6 is t6 & regNum=22 { export t6; }\nDreg: t7 is t7 & regNum=23 { export t7; }\nDreg: t8 is t8 & regNum=24 { export t8; }\nDreg: t9 is t9 & regNum=25 { export t9; }\nDreg: p0 is p0 & regNum=26 { export p0; }\nDreg: p1 is p1 & regNum=27 { export p1; }\nDreg: fp is fp & regNum=28 { export fp; }\nDreg: gp is gp & regNum=29 { export gp; }\nDreg: lp is lp & regNum=30 { export lp; }\nDreg: sp is sp & regNum=31 { export sp; }\n\nmacro Smwad(reg) {\n mult_addr = mult_addr - 4;\n *mult_addr = reg;\n}\n\nmacro LmwOp(reg) {\n\treg = *mult_addr;\n}\n\nmacro SmwOp(reg) {\n *mult_addr = reg;\n}\n\nmacro MwDec() { mult_addr = mult_addr - 4; }\nmacro MwInc() { mult_addr = mult_addr + 4; }\n\nLsmw_id: is LsmwId=0 { MwInc(); }\nLsmw_id: is LsmwId=1 { MwDec(); }\n\nLmw.fp: fp is Lsmw_id & LsmwBa=0 & Enable4_fp=1 & fp { LmwOp(fp); build Lsmw_id; }\nLmw.fp: fp is Lsmw_id & LsmwBa=1 & Enable4_fp=1 & fp { build Lsmw_id; LmwOp(fp); }\nLmw.fp: is Enable4_fp=0 { }\nLmw.gp: gp is Lsmw_id & LsmwBa=0 & Enable4_gp=1 & gp { LmwOp(gp); build Lsmw_id; }\nLmw.gp: gp is Lsmw_id & LsmwBa=1 & Enable4_gp=1 & gp { build Lsmw_id; LmwOp(gp); }\nLmw.gp: is Enable4_gp=0 { }\nLmw.lp: lp is Lsmw_id & LsmwBa=0 & Enable4_lp=1 & lp { LmwOp(lp); build Lsmw_id; }\nLmw.lp: lp is Lsmw_id & LsmwBa=1 & Enable4_lp=1 & lp { build Lsmw_id; LmwOp(lp); }\nLmw.lp: is Enable4_lp=0 { }\nLmw.sp: sp is Lsmw_id & LsmwBa=0 & Enable4_sp=1 & sp { LmwOp(sp); build Lsmw_id; }\nLmw.sp: sp is Lsmw_id & LsmwBa=1 & Enable4_sp=1 & sp { build Lsmw_id; LmwOp(sp); }\nLmw.sp: is Enable4_sp=0 { }\n\n# Terminating condition\nLmwReg: Dreg is LsmwId=0 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; LmwOp(Dreg); MwInc(); }\nLmwReg: Dreg is LsmwId=1 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; LmwOp(Dreg); MwDec(); }\n\nLmwReg: Dreg is LsmwId=0 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; MwInc(); LmwOp(Dreg); }\nLmwReg: Dreg is LsmwId=1 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; MwDec(); LmwOp(Dreg); }\n\nLmwReg: Dreg, LmwReg is LsmwId=0 & LsmwBa=0 & Dreg & LmwReg [ counter = counter-1; regNum=regNum+1;] { LmwOp(Dreg); MwInc(); build LmwReg; }\nLmwReg: Dreg, LmwReg is LsmwId=1 & LsmwBa=0 & Dreg & LmwReg [ counter = counter-1; regNum=regNum-1;] { LmwOp(Dreg); MwDec(); build LmwReg; }\n\nLmwReg: Dreg, LmwReg is LsmwId=0 & LsmwBa=1 & Dreg & LmwReg [ counter = counter-1; regNum=regNum+1;] { MwInc(); LmwOp(Dreg); build LmwReg; }\nLmwReg: Dreg, LmwReg is LsmwId=1 & LsmwBa=1 & Dreg & LmwReg [ counter = counter-1; regNum=regNum-1;] { MwDec(); LmwOp(Dreg); build LmwReg; }\n\n# Initial conditions\nLmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp) ... & LmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build LmwReg; build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; }\nLmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp) ... & LmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; build LmwReg; }\nLmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; }\nLmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; }\n\nLmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp) ... & LmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build LmwReg; build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; }\nLmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp) ... & LmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; build LmwReg; }\nLmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; }\nLmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; }\n\nSmw.fp: fp is Lsmw_id & LsmwBa=0 & Enable4_fp=1 & fp { SmwOp(fp); build Lsmw_id; }\nSmw.fp: fp is Lsmw_id & LsmwBa=1 & Enable4_fp=1 & fp { build Lsmw_id; SmwOp(fp); }\nSmw.fp: is Enable4_fp=0 { }\nSmw.gp: gp is Lsmw_id & LsmwBa=0 & Enable4_gp=1 & gp { SmwOp(gp); build Lsmw_id; }\nSmw.gp: gp is Lsmw_id & LsmwBa=1 & Enable4_gp=1 & gp { build Lsmw_id; SmwOp(gp); }\nSmw.gp: is Enable4_gp=0 { }\nSmw.lp: lp is Lsmw_id & LsmwBa=0 & Enable4_lp=1 & lp { SmwOp(lp); build Lsmw_id; }\nSmw.lp: lp is Lsmw_id & LsmwBa=1 & Enable4_lp=1 & lp { build Lsmw_id; SmwOp(lp); }\nSmw.lp: is Enable4_lp=0 { }\nSmw.sp: sp is Lsmw_id & LsmwBa=0 & Enable4_sp=1 & sp { SmwOp(sp); build Lsmw_id; }\nSmw.sp: sp is Lsmw_id & LsmwBa=1 & Enable4_sp=1 & sp { build Lsmw_id; SmwOp(sp); }\nSmw.sp: is Enable4_sp=0 { }\n\n# Terminating condition\nSmwReg: Dreg is LsmwId=0 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; SmwOp(Dreg); MwInc(); }\nSmwReg: Dreg is LsmwId=1 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; SmwOp(Dreg); MwDec(); }\n\nSmwReg: Dreg is LsmwId=0 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; MwInc(); SmwOp(Dreg); }\nSmwReg: Dreg is LsmwId=1 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; MwDec(); SmwOp(Dreg); }\n\nSmwReg: Dreg, SmwReg is LsmwId=0 & LsmwBa=0 & Dreg & SmwReg [ counter = counter-1; regNum=regNum+1;] { build Dreg; SmwOp(Dreg); MwInc(); build SmwReg; }\nSmwReg: Dreg, SmwReg is LsmwId=1 & LsmwBa=0 & Dreg & SmwReg [ counter = counter-1; regNum=regNum-1;] { build Dreg; SmwOp(Dreg); MwDec(); build SmwReg; }\n\nSmwReg: Dreg, SmwReg is LsmwId=0 & LsmwBa=1 & Dreg & SmwReg [ counter = counter-1; regNum=regNum+1;] { build Dreg; MwInc(); SmwOp(Dreg); build SmwReg; }\nSmwReg: Dreg, SmwReg is LsmwId=1 & LsmwBa=1 & Dreg & SmwReg [ counter = counter-1; regNum=regNum-1;] { build Dreg; MwDec(); SmwOp(Dreg); build SmwReg; }\n\n# Initial conditions\nSmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp) ... & SmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build SmwReg; build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; }\nSmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp) ... & SmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; build SmwReg; }\nSmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; }\nSmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; }\n\nSmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp) ... & SmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build SmwReg; build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; }\nSmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp) ... & SmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; build SmwReg; }\nSmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; }\nSmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; }\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32.dwarf", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32.ldefs", "content": "\n\n\n \n NDS32 default processor 32-bit big-endian\n \n \n \n \n \n NDS32 default processor 32-bit little-endian\n \n \n \n \n\n\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32.opinion", "content": "\n \n \n \n\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32.pspec", "content": "\n\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32.sinc", "content": "### General ###\n\ndefine endian=big;\ndefine alignment=2;\ndefine space ram type=ram_space size=4 wordsize=1 default;\ndefine space register type=register_space size=4;\n\ndefine space csreg type=ram_space size=2 wordsize=4;\n\n@define CSR_REG_START \"0x0000\"\n\ndefine register offset=0 size=4\n[a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp];\n\ndefine register offset=0x90 size=4\n[pc mult_addr mult_inc];\n\ndefine register offset=0x100 size=8\n[d0 d1];\n\ndefine register offset=0x100 size=4\n[d0.hi d0.lo d1.hi d1.lo];\n\ndefine register offset=0x200 size=4\n[ itb lb lc le ifc_lp\n fpcsr fpcfg\n];\n\ndefine register offset=0x1000 size=4\n[ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7\n fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15\n fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23\n fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31\n];\n\ndefine register offset=0x1000 size=8\n[ fd0 fd1 fd2 fd3 fd4 fd5 fd6 fd7\n fd8 fd9 fd10 fd11 fd12 fd13 fd14 fd15\n fd16 fd17 fd18 fd19 fd20 fd21 fd22 fd23\n fd24 fd25 fd26 fd27 fd28 fd29 fd30 fd31\n];\n\ndefine csreg offset=0x0a9 size=4\n[\n\tipc\n];\n\ndefine register offset=0x300 size=8 contextreg;\ndefine context contextreg\n\tcounter\t\t= (22,26)\n\tregNum\t\t= (27,31)\t# register for load/store multiple instructions\n;\n\ndefine token instr32(32)\n OpSz = (31, 31)\n Opc = (25, 30)\n Rt = (20, 24)\n Fst = (20, 24)\n Fdt = (20, 24)\n Rth = (21, 24)\n Rtl = (21, 24)\n Ra = (15, 19)\n Fsa = (15, 19)\n Fda = (15, 19)\n Rb = (10, 14)\n Fsb = (10, 14)\n Fdb = (10, 14)\n Rd = (5, 9)\n Rs = (5, 9)\n Sub5 = (0, 4)\n Sub6 = (0, 5)\n Sub7 = (0, 6)\n Sub8 = (0, 7)\n Sub3 = (7, 9)\n fop4 = (6, 9)\n cop4 = (0, 3)\n f2op = (10, 14)\n fcnd = (7, 9)\n cmpe = (6, 6)\n fbi = (7, 7)\n cpn = (13, 14)\n fsbi = (12, 12)\n Imm8u = (7,14)\n Imm5u = (10, 14)\n Imm5s = (10, 14) signed\n Br1t = (14, 14)\n Br2t = (16, 19)\n Alu2Mod = (6, 9)\n Dtl = (22, 24)\n Dt = (21, 21)\n Dtlow = (21, 21)\n Dthigh = (21, 21)\n Dtr = (20, 20)\n JIt = (24, 24)\n Imm19s = (0, 18) signed\n Imm18s = (0, 17) signed\n Imm17s = (0, 16) signed\n Imm16s = (0, 15) signed\n Imm14s = (0, 13) signed\n Imm15u = (0, 14)\n Imm15s = (0, 14) signed\n Imm20u = (0, 19)\n Imm20s = (0, 19) signed\n Imm24s = (0, 23) signed\n Imm12s = (0, 11) signed\n Imm11s = (8, 18) signed\n Imm8s = (0, 7) signed\n sv = (8, 9)\n SrIdx = (10, 19)\n Swid = (5, 19)\n\n CctlZ = (11, 14)\n CctlLevel = (10, 10)\n CctlSub = (5, 9)\n\n MsyncZ = (8, 19)\n MsyncSub = (5, 7)\n\n DtIt = (8, 9)\n Jz = (6, 7)\n JrHint = (5, 5)\n\n ToggleL = (21, 24)\n Toggle = (20, 20)\n\n Usr = (15, 19)\n Group = (10, 14)\n\n DprefD = (24, 24)\n DprefSub = (20, 23)\n\n TlbopSub = (5, 9)\n\n StandbyZ = (7, 9)\n StandbySub = (5, 6)\n \n GpSub1 = (19, 19)\n GpSub2 = (18, 19)\n GpSub3 = (17, 19)\n\n sh = (5, 9)\n \n Bxxc\t\t= (19, 19)\n\n LsmwRa = (15, 19)\n LsmwRb = (20, 24)\n LsmwRb_ = (20, 24)\n LsmwRe = (10, 14)\n LsmwRe_ = (10, 14)\n Enable4 = (6, 9)\n Enable4_fp = (9, 9)\n Enable4_gp = (8, 8)\n Enable4_lp = (7, 7)\n Enable4_sp = (6, 6)\n LsmwLs = (5, 5)\n LsmwBa = (4, 4)\n LsmwId = (3, 3)\n LsmwM = (2, 2)\n LsmwSub = (0, 1)\n;\n\nattach variables [Rt Rs Ra Rb Rd LsmwRa LsmwRb LsmwRe] [\n a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp\n];\n\nattach variables [Rtl] [\n a0 a2 a4 s0 s2 s4 s6 s8 t0 t2 t4 t6 t8 p0 fp lp\n];\n\nattach variables [Rth] [\n a1 a3 a5 s1 s3 s5 s7 ta t1 t3 t5 t7 t9 p1 gp sp\n];\n\nattach variables [Dt] [\n d0 d1\n];\n\nattach variables [Dtlow] [\n d0.lo d1.lo\n];\n\nattach variables [Dthigh] [\n d0.hi d1.hi\n];\n\nattach variables [ Fst Fsa Fsb ]\n[ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7\n fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15\n fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23\n fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31\n];\n\nattach variables [ Fdt Fda Fdb ]\n[ fd0 fd1 fd2 fd3 fd4 fd5 fd6 fd7\n fd8 fd9 fd10 fd11 fd12 fd13 fd14 fd15\n fd16 fd17 fd18 fd19 fd20 fd21 fd22 fd23\n fd24 fd25 fd26 fd27 fd28 fd29 fd30 fd31\n];\n\n@define I32 \"(OpSz=0)\"\n@define LBGP \"(Opc=0b010111)\"\n@define LWC \"(Opc=0b011000)\"\n@define SWC \"(Opc=0b011001)\"\n@define LDC \"(Opc=0b011010)\"\n@define SDC \"(Opc=0b011011)\"\n@define LSMW \"(Opc=0b011101)\"\n@define MEM \"(Opc=0b011100)\"\n@define HWGP \"(Opc=0b011110)\"\n@define SBGP \"(Opc=0b011111)\"\n@define ALU_1 \"(Opc=0b100000)\"\n@define ALU_2 \"(Opc=0b100001)\"\n@define JI \"(Opc=0b100100)\"\n@define JREG \"(Opc=0b100101)\"\n@define BR1 \"(Opc=0b100110)\"\n@define BR2 \"(Opc=0b100111)\"\n@define BR3 \"(Opc=0b101101)\"\n@define MISC \"(Opc=0b110010)\"\n@define COP \"(Opc=0b110101)\"\n@define SIMD \"(Opc=0b111000)\"\n\n@define ALU2Z \"(Alu2Mod=0b0000)\"\n@define GPR \"(Alu2Mod=0b0001)\"\n\n\n### ALU Instruction with Immediate ###\n\n:addi Rt, Ra, Imm15s is $(I32) & Opc=0b101000 & Rt & Ra & Imm15s { Rt = Ra + Imm15s; }\n:subri Rt, Ra, Imm15s is $(I32) & Opc=0b101001 & Rt & Ra & Imm15s { Rt = Imm15s - Ra; }\n:andi Rt, Ra, Imm15u is $(I32) & Opc=0b101010 & Rt & Ra & Imm15u { Rt = Ra & Imm15u; }\n:ori Rt, Ra, Imm15u is $(I32) & Opc=0b101100 & Rt & Ra & Imm15u { Rt = Ra | Imm15u; }\n:xori Rt, Ra, Imm15u is $(I32) & Opc=0b101011 & Rt & Ra & Imm15u { Rt = Ra ^ Imm15u; }\n:slti Rt, Ra, Imm15s is $(I32) & Opc=0b101110 & Rt & Ra & Imm15s { Rt = zext(Ra < Imm15s); }\n:sltsi Rt, Ra, Imm15s is $(I32) & Opc=0b101111 & Rt & Ra & Imm15s { Rt = zext(Ra s< Imm15s); }\n:movi Rt, Imm20s is $(I32) & Opc=0b100010 & Rt & Imm20s { Rt = Imm20s; }\n:sethi Rt, Imm20u is $(I32) & Opc=0b100011 & Rt & Imm20u { Rt = Imm20u << 12;}\n\n\n### ALU Instruction ###\n\n:add Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00000 { Rt = Ra + Rb; }\n:sub Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00001 { Rt = Ra - Rb; }\n:and Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00010 { Rt = Ra & Rb; }\n:xor Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00011 { Rt = Ra ^ Rb; }\n:or Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00100 { Rt = Ra | Rb; }\n:nor Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00101 { Rt = ~(Ra | Rb); }\n:slt Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00110 { Rt = zext(Ra < Rb); }\n:slts Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00111 { Rt = zext(Ra s< Rb); }\n:sva Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11000 { Rt = zext(scarry(Ra, Rb)); }\n:svs Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11001 { Rt = zext(sborrow(Ra, Rb)); }\n:seb Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10000 { local tmp = Ra; Rt = sext(tmp:1); }\n:seh Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10001 { local tmp = Ra; Rt = sext(tmp:2); }\n:zeb Rt, Ra is $(I32) & Opc=0b101010 & Rt & Ra & Imm15u=0xff { local tmp = Ra; Rt = zext(tmp:1); }\n:zeh Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10011 { local tmp = Ra; Rt = zext(tmp:2); }\n:wsbh Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10100\n{\n Rt = ((Ra & 0x000000ff) << 8)\n | ((Ra & 0x0000ff00) >> 8)\n | ((Ra & 0x00ff0000) << 8)\n | ((Ra & 0xff000000) >> 8);\n}\n\n\n### Shifter Instruction ###\n\n:slli Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01000 { Rt = Ra << Imm5u; }\n:srli Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01001 { Rt = Ra >> Imm5u; }\n:srai Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01010 { Rt = Ra s>> Imm5u; }\n:rotri Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01011 { Rt = (Ra >> Imm5u) | (Ra << (32 - Imm5u)); }\n:sll Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01100 { tmp:4 = Rb & 0b11111; Rt = Ra << tmp; }\n:srl Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01101 { tmp:4 = Rb & 0b11111; Rt = Ra >> tmp; }\n:sra Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01110 { tmp:4 = Rb & 0b11111; Rt = Ra s>> tmp; }\n:rotr Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01111 { tmp:4 = Rb & 0b11111; Rt = (Ra >> tmp) | (Ra << (32 - tmp)); }\n\n\n### Multiply Instruction ###\n\n:mul Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b100100 { Rt = Ra * Rb; }\n:mults64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101000 { Dt = sext(Ra) * sext(Rb); }\n:mult64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101001 { Dt = zext(Ra) * zext(Rb); }\n:madds64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101010 { Dt = Dt + (sext(Ra) * sext(Rb)); }\n:madd64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101011 { Dt = Dt + (zext(Ra) * zext(Rb)); }\n:msubs64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101100 { Dt = Dt - (sext(Ra) * sext(Rb)); }\n:msub64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101101 { Dt = Dt - (zext(Ra) * zext(Rb)); }\n:mult32 Dtlow, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dtlow & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b110001 { Dtlow = Ra * Rb; }\n:madd32 Dtlow, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dtlow & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b110011 { Dtlow = Dtlow + (Ra * Rb); }\n:msub32 Dtlow, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dtlow & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b110101 { Dtlow = Dtlow - (Ra * Rb); }\n\n\n# Group 0\nUsrName: d0.lo is Group=0 & Usr=0 & d0.lo { export d0.lo; }\nUsrName: d0.hi is Group=0 & Usr=1 & d0.hi { export d0.hi; }\nUsrName: d1.lo is Group=0 & Usr=2 & d1.lo { export d1.lo; }\nUsrName: d1.hi is Group=0 & Usr=3 & d1.hi { export d1.hi; }\nUsrName: lb is Group=0 & Usr=25 & lb { export lb; }\nUsrName: le is Group=0 & Usr=26 & le { export le; }\nUsrName: lc is Group=0 & Usr=27 & lc { export lc; }\nUsrName: itb is Group=0 & Usr=28 & itb { export itb; }\nUsrName: ifc_lp is Group=0 & Usr=29 & ifc_lp { export ifc_lp; }\n#UsrName: pc is Group=0 & Usr=31 & pc { export pc; } # handled separately\n\n# Group 1\nUsrName: \"dma_cfg\" is Group=1 & Usr=0 { tmp:2 = 0x280; export *[csreg]:4 tmp; }\nUsrName: \"dma_gcsw\" is Group=1 & Usr=1 { tmp:2 = 0x288; export *[csreg]:4 tmp; }\nUsrName: \"dma_chnsel\" is Group=1 & Usr=2 { tmp:2 = 0x290; export *[csreg]:4 tmp; }\nUsrName: \"dma_act\" is Group=1 & Usr=3 { tmp:2 = 0x298; export *[csreg]:4 tmp; }\nUsrName: \"dma_setup\" is Group=1 & Usr=4 { tmp:2 = 0x2a0; export *[csreg]:4 tmp; }\nUsrName: \"dma_isaddr\" is Group=1 & Usr=5 { tmp:2 = 0x2a8; export *[csreg]:4 tmp; }\nUsrName: \"dma_esaddr\" is Group=1 & Usr=6 { tmp:2 = 0x2b0; export *[csreg]:4 tmp; }\nUsrName: \"dma_tcnt\" is Group=1 & Usr=7 { tmp:2 = 0x2b8; export *[csreg]:4 tmp; }\nUsrName: \"dma_status\" is Group=1 & Usr=8 { tmp:2 = 0x2c0; export *[csreg]:4 tmp; }\nUsrName: \"dma_2dset\" is Group=1 & Usr=9 { tmp:2 = 0x2c8; export *[csreg]:4 tmp; }\nUsrName: \"dma_rcnt\" is Group=1 & Usr=23 { tmp:2 = 0x2b9; export *[csreg]:4 tmp; }\nUsrName: \"dma_hstatus\" is Group=1 & Usr=24 { tmp:2 = 0x2c1; export *[csreg]:4 tmp; }\nUsrName: \"dma_2dsctl\" is Group=1 & Usr=25 { tmp:2 = 0x2c9; export *[csreg]:4 tmp; }\n\n# Group 2\nUsrName: \"pfmc0\" is Group=2 & Usr=0 { tmp:2 = 0x200; export *[csreg]:4 tmp; }\nUsrName: \"pfmc1\" is Group=2 & Usr=1 { tmp:2 = 0x201; export *[csreg]:4 tmp; }\nUsrName: \"pfmc2\" is Group=2 & Usr=2 { tmp:2 = 0x202; export *[csreg]:4 tmp; }\nUsrName: \"pfm_ctl\" is Group=2 & Usr=4 { tmp:2 = 0x208; export *[csreg]:4 tmp; }\n\n\n:mfusr Rt, UsrName is $(I32) & $(ALU_2) & Rt & UsrName & $(ALU2Z) & Sub6=0b100000 { Rt = UsrName; }\n:mfusr Rt, pc is $(I32) & $(ALU_2) & Rt & Group=0 & Usr=0b11111 & $(ALU2Z) & Sub6=0b100000 & pc { Rt = inst_next; } \n:mtusr Rt, UsrName is $(I32) & $(ALU_2) & Rt & UsrName & $(ALU2Z) & Sub6=0b100001 { UsrName = Rt; }\n:mtusr Rt, pc is $(I32) & $(ALU_2) & Rt & Group=0 & Usr=0b11111 & $(ALU2Z) & Sub6=0b100001 & pc { pc = Rt; goto[pc]; } # Not sure this works correctly\n\n\n### Divide Instructions ###\n\n:div Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtlow & Dthigh & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101111 { Dtlow = Ra / Rb; Dthigh = Ra % Rb; }\n:divs Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtlow & Dthigh & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101110 { Dtlow = Ra s/ Rb; Dthigh = Ra s% Rb; }\n\n\n### Load / Store Instruction (immediate) ###\n\nByteOffset: off is Imm15s [ off = Imm15s << 0; ] { export *[const]:4 off; }\nHalfOffset: off is Imm15s [ off = Imm15s << 1; ] { export *[const]:4 off; }\nWordOffset: off is Imm15s [ off = Imm15s << 2; ] { export *[const]:4 off; }\n\nAddrByteRaImm15s: [Ra + ByteOffset] is Ra & ByteOffset { addr:4 = Ra + ByteOffset; export addr; }\nAddrHalfRaImm15s: [Ra + HalfOffset] is Ra & HalfOffset { addr:4 = Ra + HalfOffset; export addr; }\nAddrWordRaImm15s: [Ra + WordOffset] is Ra & WordOffset { addr:4 = Ra + WordOffset; export addr; }\n\n:lwi Rt, AddrWordRaImm15s is $(I32) & Opc=0b000010 & Rt & AddrWordRaImm15s { Rt = *AddrWordRaImm15s; }\n:lhi Rt, AddrHalfRaImm15s is $(I32) & Opc=0b000001 & Rt & AddrHalfRaImm15s { local tmp:2 = *AddrHalfRaImm15s; Rt = zext(tmp); }\n:lhsi Rt, AddrHalfRaImm15s is $(I32) & Opc=0b010001 & Rt & AddrHalfRaImm15s { local tmp:2 = *AddrHalfRaImm15s; Rt = sext(tmp); }\n:lbi Rt, AddrByteRaImm15s is $(I32) & Opc=0b000000 & Rt & AddrByteRaImm15s { local tmp:1 = *AddrByteRaImm15s; Rt = zext(tmp); }\n:lbsi Rt, AddrByteRaImm15s is $(I32) & Opc=0b010000 & Rt & AddrByteRaImm15s { local tmp:1 = *AddrByteRaImm15s; Rt = sext(tmp); }\n:swi Rt, AddrWordRaImm15s is $(I32) & Opc=0b001010 & Rt & AddrWordRaImm15s { *AddrWordRaImm15s = Rt; }\n:shi Rt, AddrHalfRaImm15s is $(I32) & Opc=0b001001 & Rt & AddrHalfRaImm15s { local tmp = Rt; *AddrHalfRaImm15s = tmp:2; }\n:sbi Rt, AddrByteRaImm15s is $(I32) & Opc=0b001000 & Rt & AddrByteRaImm15s { local tmp = Rt; *AddrByteRaImm15s = tmp:1; }\n\n### Load / Store Instruction (immediate, postincr) ###\n\n:lwi.bi Rt, [Ra], WordOffset is $(I32) & Opc=0b000110 & Rt & Ra & WordOffset { Rt = *Ra; Ra = Ra + WordOffset; }\n:lhi.bi Rt, [Ra], HalfOffset is $(I32) & Opc=0b000101 & Rt & Ra & HalfOffset { local tmp:2 = *Ra; Rt = zext(tmp); Ra = Ra + HalfOffset; }\n:lhsi.bi Rt, [Ra], HalfOffset is $(I32) & Opc=0b010101 & Rt & Ra & HalfOffset { local tmp:2 = *Ra; Rt = sext(tmp); Ra = Ra + HalfOffset; }\n:lbi.bi Rt, [Ra], ByteOffset is $(I32) & Opc=0b000100 & Rt & Ra & ByteOffset { local tmp:1 = *Ra; Rt = zext(tmp); Ra = Ra + ByteOffset; }\n:lbsi.bi Rt, [Ra], ByteOffset is $(I32) & Opc=0b010100 & Rt & Ra & ByteOffset { local tmp:1 = *Ra; Rt = sext(tmp); Ra = Ra + ByteOffset; }\n:swi.bi Rt, [Ra], WordOffset is $(I32) & Opc=0b001110 & Rt & Ra & WordOffset { *Ra = Rt; Ra = Ra + WordOffset; }\n:shi.bi Rt, [Ra], HalfOffset is $(I32) & Opc=0b001101 & Rt & Ra & HalfOffset { local tmp = Rt; *Ra = tmp:2; Ra = Ra + HalfOffset; }\n:sbi.bi Rt, [Ra], ByteOffset is $(I32) & Opc=0b001100 & Rt & Ra & ByteOffset { local tmp = Rt; *Ra = tmp:1; Ra = Ra + ByteOffset; }\n\n\n### Load / Store Instruction (register) ###\n\nOffsetRbsv: (Rb \"<<\" sv) is Rb & sv { off:4 = Rb << sv; export off; }\nAddrRaRbsv: [Ra + OffsetRbsv] is Ra & OffsetRbsv { addr:4 = Ra + OffsetRbsv; export addr; }\n\n:lw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00000010 { Rt = *AddrRaRbsv; }\n:lh Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00000001 { local tmp:2 = *AddrRaRbsv; Rt = zext(tmp); }\n:lhs Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00010001 { local tmp:2 = *AddrRaRbsv; Rt = sext(tmp); }\n:lb Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00000000 { local tmp:1 = *AddrRaRbsv; Rt = zext(tmp); }\n:lbs Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00010000 { local tmp:1 = *AddrRaRbsv; Rt = sext(tmp); }\n:sw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00001010 { *AddrRaRbsv = Rt; }\n:sh Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00001001 { local tmp = Rt; *AddrRaRbsv = tmp:2; }\n:sb Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00001000 { local tmp = Rt; *AddrRaRbsv = tmp:1; }\n\n\n### Load / Store Instruction (register, postincr) ###\n\n:lw.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00000110 { Rt = *Ra; Ra = Ra + OffsetRbsv; }\n:lh.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00000101 { local tmp:2 = *Ra; Rt = zext(tmp); Ra = Ra + OffsetRbsv; }\n:lhs.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00010101 { local tmp:2 = *Ra; Rt = sext(tmp); Ra = Ra + OffsetRbsv; }\n:lb.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00000100 { local tmp:1 = *Ra; Rt = zext(tmp); Ra = Ra + OffsetRbsv; }\n:lbs.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00010100 { local tmp:1 = *Ra; Rt = sext(tmp); Ra = Ra + OffsetRbsv; }\n:sw.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00001110 { *Ra = Rt; Ra = Ra + OffsetRbsv; }\n:sh.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00001101 { local tmp = Rt; *Ra = tmp:2; Ra = Ra + OffsetRbsv; }\n:sb.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00001100 { local tmp = Rt; *Ra = tmp:1; Ra = Ra + OffsetRbsv; }\n\n\n### Load / Store Multiple Word Instruction ###\n\n\n@include \"lsmw.sinc\"\n\nLsmwBa_: \"b\" is LsmwBa=0 { }\nLsmwBa_: \"a\" is LsmwBa=1 { }\n\nLsmwId_: \"i\" is LsmwId=0 { }\nLsmwId_: \"d\" is LsmwId=1 { }\n\nLsmwM_: \"\" is LsmwRa & LsmwM=0 { }\nLsmwM_: \"m\" is LsmwRa & LsmwM=1 { LsmwRa = mult_addr; }\n\n\n:lmw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00) ... & Lmw.regs\n{\n mult_addr = LsmwRa;\n build Lmw.regs;\n build LsmwM_;\n}\n\n:smw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00) ... & Smw.regs\n{\n mult_addr = LsmwRa;\n build Smw.regs;\n build LsmwM_;\n}\n\n\n### Load / Store Instruction for Atomic Updates ###\n\n:llw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00011000 { Rt = *AddrRaRbsv; }\n:scw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00011001 { *AddrRaRbsv = Rt; }\n\n\n### Load / Store Instructions with User-mode Privilege ###\n\n# TODO : special constraint (user-mode address translation)\n\n:lwup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00100010 { Rt = *AddrRaRbsv; }\n:swup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00101010 { *AddrRaRbsv = Rt; }\n\n\n### Jump Instruction ###\n\nRel24: addr is Imm24s [ addr = inst_start + (Imm24s << 1); ] { export *:4 addr; }\n\n:j Rel24 is $(I32) & $(JI) & JIt=0 & Rel24 { goto Rel24; }\n:jal Rel24 is $(I32) & $(JI) & JIt=1 & Rel24 { lp = inst_next; call Rel24; }\n:jr Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00000 { goto [Rb]; }\n:ret Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=1 & Sub5=0b00000 { return [Rb]; }\n:jral Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00001 { Rt = inst_next; call [Rb]; }\n\n\n### Branch Instruction ###\nRel14: addr is Imm14s [ addr = inst_start + (Imm14s << 1); ] { export *:4 addr; }\nRel16: addr is Imm16s [ addr = inst_start + (Imm16s << 1); ] { export *:4 addr; }\n\n:beq Rt, Ra, Rel14 is $(I32) & $(BR1) & Rt & Ra & Br1t=0 & Rel14 { if(Rt == Ra) goto Rel14; }\n:bne Rt, Ra, Rel14 is $(I32) & $(BR1) & Rt & Ra & Br1t=1 & Rel14 { if(Rt != Ra) goto Rel14; }\n:beqz Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0010 & Rel16 { if(Rt == 0) goto Rel16; }\n:bnez Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0011 & Rel16 { if(Rt != 0) goto Rel16; }\n:bgez Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0100 & Rel16 { if(Rt s>= 0) goto Rel16; }\n:bltz Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0101 & Rel16 { if(Rt s< 0) goto Rel16; }\n:bgtz Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0110 & Rel16 { if(Rt s> 0) goto Rel16; }\n:blez Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0111 & Rel16 { if(Rt s<= 0) goto Rel16; }\n\n\n### Branch with link Instruction ###\n\n:bgezal Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b1100 & Rel16\n{ \n lp = inst_next;\n if(Rt s>= 0) goto ;\n call Rel16;\n \n}\n\n:bltzal Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b1101 & Rel16\n{ \n lp = inst_next;\n if(Rt s< 0) goto ;\n call Rel16;\n \n}\n\n\n### Read / Write System Registers ###\n\n# TODO : special instruction, do we create the system registers ?\ndefine pcodeop mfsr;\ndefine pcodeop mtsr;\n\ncsr: csr_reg is SrIdx [ csr_reg = $(CSR_REG_START) + SrIdx; ] { export *[csreg]:4 csr_reg; }\n\n:mfsr Rt, csr is $(I32) & $(MISC) & Rt & csr & Rd=0 & Sub5=0b00010 { Rt = csr; }\n:mtsr Rt, csr is $(I32) & $(MISC) & Rt & csr & Rd=0 & Sub5=0b00011 { csr = Rt; }\n\n\n### Jump Register with System Register Update ###\n\n# TODO : special constraint (address translation off)\n\n:jr.itoff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b01 & Jz=0 & JrHint=0 & Sub5=0b00000 { goto [Rb]; }\n:jr.toff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b11 & Jz=0 & JrHint=0 & Sub5=0b00000 { goto [Rb]; }\n:jral.iton Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b01 & Jz=0 & JrHint=0 & Sub5=0b00001 { Rt = inst_next; call [Rb]; }\n:jral.ton Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b11 & Jz=0 & JrHint=0 & Sub5=0b00001 { Rt = inst_next; call [Rb]; }\n\n\n### MMU Instruction ###\n\ndefine pcodeop TLB_TargetRead;\ndefine pcodeop TLB_TargetWrite;\ndefine pcodeop TLB_RWrite;\ndefine pcodeop TLB_RWriteLock;\ndefine pcodeop TLB_Unlock;\ndefine pcodeop TLB_Probe;\ndefine pcodeop TLB_Invalidate;\ndefine pcodeop TLB_FlushAll;\n\n:tlbop Ra,\"TargetRead\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=0 & Sub5=0b01110 { TLB_TargetRead(Ra:4); }\n:tlbop Ra,\"TargetWrite\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=1 & Sub5=0b01110 { TLB_TargetWrite(Ra:4); }\n:tlbop Ra,\"RWrite\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=2 & Sub5=0b01110 { TLB_RWrite(Ra:4); }\n:tlbop Ra,\"RWriteLock\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=3 & Sub5=0b01110 { TLB_RWriteLock(Ra:4); }\n:tlbop Ra,\"Unlock\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=4 & Sub5=0b01110 { TLB_Unlock(Ra:4); }\n:tlbop Rt,Ra,\"Probe\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=5 & Sub5=0b01110 { TLB_Probe(Rt:4, Ra:4); }\n:tlbop Ra,\"Invalidate\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=6 & Sub5=0b01110 { TLB_Invalidate(Ra:4); }\n:tlbop \"FlushAll\" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=7 & Sub5=0b01110 { TLB_FlushAll(); }\n\n\n### Conditional Move ###\n\n:cmovz Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11010\n{\n if(Rb != 0) goto ;\n Rt = Ra;\n \n}\n\n:cmovn Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11011\n{\n if(Rb == 0) goto ;\n Rt = Ra;\n \n}\n\n\n### Synchronization Instruction ###\n\n# TODO : special function, and subfunctions\n\ndefine pcodeop msync;\ndefine pcodeop isync;\n\n:msync MsyncSub is $(I32) & $(MISC) & Rt=0 & MsyncZ=0 & MsyncSub & Sub5=0b01100 { msync(MsyncSub:1); }\n:isync Rt is $(I32) & $(MISC) & Rt & Ra=0 & Rb=0 & Rd=0 & Sub5=0b01101 { isync(Rt:4); }\n\n### Prefetch Instruction ###\n\ndefine pcodeop dpref;\n\nOffsetRbsv2: (Rb \"<<\" sv) is Rb & sv { off:4 = Rb << (sv + 1); export off; }\nAddrRaRbsv2: [Ra + OffsetRbsv2] is Ra & OffsetRbsv2 { addr:4 = Ra + OffsetRbsv2; export addr; }\n\n:dpref DprefSub, AddrRaRbsv2 is $(I32) & $(MEM) & DprefD=0 & DprefSub & AddrRaRbsv2 & Sub8=0b00010011 {\n dpref(DprefSub:1, AddrRaRbsv2:4);\n}\n\nDprefD_: \"w\" is DprefD=0 { }\nDprefD_: \"d\" is DprefD=1 { }\n\nDprefiAddr: [Ra + Offset] is DprefD=0 & Ra & Imm15s [ Offset = Imm15s << 2; ] { export *[const]:4 Offset; }\nDprefiAddr: [Ra + Offset] is DprefD=1 & Ra & Imm15s [ Offset = Imm15s << 3; ] { export *[const]:4 Offset; }\n\n:dprefi.^DprefD_ DprefSub, DprefiAddr is $(I32) & Opc=0b010011 & DprefD_ & DprefSub & DprefiAddr {\n dpref(DprefSub:1, DprefiAddr:4);\n}\n\n\n### NOP Instruction ###\n\n:nop is $(I32) & $(ALU_1) & Rt=0 & Ra=0 & Imm5u=0 & Rd=0 & Sub5=0b01001 { }\n\n\n### Serialization Instruction ###\n\ndefine pcodeop dsb;\ndefine pcodeop isb;\n\n:dsb is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & Rd=0 & Sub5=0b01000 { dsb(); }\n:isb is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & Rd=0 & Sub5=0b01001 { isb(); }\n\n\n### Exception Generation Instruction ###\n\ndefine pcodeop break;\ndefine pcodeop syscall;\ndefine pcodeop trap;\n\n:break Swid is $(I32) & $(MISC) & Rt=0 & Swid & Sub5=0b01010 { break(Swid:4); }\n:syscall Swid is $(I32) & $(MISC) & Rt=0 & Swid & Sub5=0b01011 { syscall(Swid:4); }\n:trap Swid is $(I32) & $(MISC) & Rt=0 & Swid & Sub5=0b00101 { trap(Swid:4); }\n\n:teqz Rt, Swid is $(I32) & $(MISC) & Rt & Swid & Sub5=0b00110\n{\n if(Rt != 0) goto ;\n trap(Swid:4);\n \n}\n\n:tnez Rt, Swid is $(I32) & $(MISC) & Rt & Swid & Sub5=0b00111\n{\n if(Rt == 0) goto ;\n trap(Swid:4);\n \n}\n\n\n### Special Return Instruction ###\n\n:iret is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & Rd=0 & Sub5=0b00100 { return [ipc]; }\n\n# TODO : special constraint (address translation off)\n:ret.itoff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b01 & Jz=0 & JrHint=1 & Sub5=0b00000 { return [Rb]; }\n:ret.toff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b11 & Jz=0 & JrHint=1 & Sub5=0b00000 { return [Rb]; }\n\n\n### Cache Control Instruction ###\n\n# TODO : special function, with subfunctions\ndefine pcodeop cctl;\n\n:cctl Rt, Ra, CctlLevel, CctlSub is $(I32) & $(MISC) & Rt & Ra & CctlZ=0 & CctlLevel & CctlSub & Sub5=0b00001 { cctl(Rt:4, Ra:4, CctlLevel:1, CctlSub:1); }\n\n\n# Miscellaneous Instructions (Baseline)\n\n# TODO : special function. Not sure if we use context or registers for this.\n\ndefine pcodeop setgie;\n\nSetgieEN: \"d\" is Toggle=0 { setgie(0:1); }\nSetgieEN: \"e\" is Toggle=1 { setgie(1:1); }\n\n:setgie.^SetgieEN is $(I32) & $(MISC) & ToggleL=0 & SetgieEN & SrIdx=0b0010000000 & Rd=0b00010 & Sub5=0b00011 { }\n\ndefine pcodeop setend;\n\nSetendBE: \"l\" is Toggle=0 { setend(0:1); }\nSetendBE: \"b\" is Toggle=1 { setend(1:1); }\n\n:setend.^SetendBE is $(I32) & $(MISC) & ToggleL=0 & SetendBE & SrIdx=0b0010000000 & Rd=0b00001 & Sub5=0b00011 { }\n\n:standby StandbySub is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & StandbyZ=0 & StandbySub & Sub5=0b00000 { goto inst_start; }\n\n\n\n### 32-bit Baseline V2 instructions ###\n\n### ALU Instructions ###\n\n:addi.gp is $(I32) & $(SBGP) & Rt & GpSub1=0b1 & Imm19s { Rt = gp + Imm19s; }\n\n\n### Multiply and Divide Instructions (V2) ###\n\n:mulr64 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b101001 & Rtl & Rth\n{\n res:8 = zext(Ra) * zext(Rb);\n Rtl = res[32,32];\n Rth = res[0,32];\n\n}\n\n:mulsr64 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b101000 & Rtl & Rth\n{\n res:8 = sext(Ra) * sext(Rb);\n Rtl = res[32,32];\n Rth = res[0,32];\n}\n\n:maddr32 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b110011 { Rt = Rt + (Ra * Rb); }\n:msubr32 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b110101 { Rt = Rt - (Ra * Rb); }\n:divr Rt, Rs, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rs & Sub5=0b10111 { local div = Ra / Rb; local mod = Ra % Rb; Rs = mod; Rt = div; }\n:divsr Rt, Rs, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rs & Sub5=0b10110 { local div = Ra s/ Rb; local mod = Ra s% Rb; Rs = mod; Rt = div; }\n\n\n### Load/Store Instructions ###\n\nGpByteAddress: [+ off] is Imm19s [ off = Imm19s << 0; ] { addr:4 = gp + off; export addr; }\nGpHalfAddress: [+ off] is Imm18s [ off = Imm18s << 1; ] { addr:4 = gp + off; export addr; }\nGpWordAddress: [+ off] is Imm17s [ off = Imm17s << 2; ] { addr:4 = gp + off; export addr; }\n\n:lbi.gp Rt, GpByteAddress is $(I32) & $(LBGP) & Rt & GpSub1=0b0 & GpByteAddress { local tmp:1 = *GpByteAddress; Rt = zext(tmp); }\n:lbsi.gp Rt, GpByteAddress is $(I32) & $(LBGP) & Rt & GpSub1=0b1 & GpByteAddress { local tmp:1 = *GpByteAddress; Rt = sext(tmp); }\n:lhi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b00 & GpHalfAddress { local tmp:2 = *GpHalfAddress; Rt = zext(tmp); }\n:lhsi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b01 & GpHalfAddress { local tmp:2 = *GpHalfAddress; Rt = sext(tmp); }\n:lwi.gp Rt, GpWordAddress is $(I32) & $(HWGP) & Rt & GpSub3=0b110 & GpWordAddress { Rt = *GpWordAddress; }\n:sbi.gp Rt, GpByteAddress is $(I32) & $(SBGP) & Rt & GpSub1=0b0 & GpByteAddress { local tmp = Rt; *GpByteAddress = tmp:1; }\n:shi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b10 & GpHalfAddress { local tmp = Rt; *GpHalfAddress = tmp:2; }\n:swi.gp Rt, GpWordAddress is $(I32) & $(HWGP) & Rt & GpSub3=0b111 & GpWordAddress { *GpWordAddress = Rt; }\n\n\n:lmwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01) ... & Lmwa.regs\n{\n mult_addr = LsmwRa;\n build Lmwa.regs;\n build LsmwM_;\n}\n\n:smwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01) ... & Smwa.regs\n{\n mult_addr = LsmwRa;\n build Smwa.regs;\n build LsmwM_;\n}\n\n:lbup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00100000 { local tmp:1 = *AddrRaRbsv; Rt = zext(tmp); }\n:sbup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00101000 { local tmp = Rt; *AddrRaRbsv = tmp:1; }\n\n\n\n### 32-bit Baseline V3 instructions ###\n\n### ALU Instructions with Shift Operation (v3) ###\n\n:add_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00000 { Rt = Ra + (Rb << sh); }\n:and_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00010 { Rt = Ra & (Rb << sh); }\n:or_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00100 { Rt = Ra | (Rb << sh); }\n:sub_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00001 { Rt = Ra - (Rb << sh); }\n:xor_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00011 { Rt = Ra ^ (Rb << sh); }\n\n:add_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11100 { Rt = Ra + (Rb << sh); }\n:and_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11110 { Rt = Ra & (Rb << sh); }\n:or_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b10101 { Rt = Ra | (Rb << sh); }\n:sub_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11101 { Rt = Ra - (Rb << sh); }\n:xor_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11111 { Rt = Ra ^ (Rb << sh); }\n\n### Conditional Branch and Jump Instructions (V3) ###\n\nRel8: addr is Imm8s [ addr = inst_start + (Imm8s << 1); ] { export *:4 addr; }\n:beqc Rt, Imm11s, Rel8 is $(I32) & $(BR3) & Rt & Bxxc=0 & Imm11s & Rel8 { if(Rt == Imm11s) goto Rel8; }\n:bnec Rt, Imm11s, Rel8 is $(I32) & $(BR3) & Rt & Bxxc=1 & Imm11s & Rel8 { if(Rt != Imm11s) goto Rel8; }\n\n:jralnez Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00011 { if(Rb == 0) goto ; Rt = inst_next; call [Rb]; }\n:jrnez Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00010 { if(Rb == 0) goto ; goto [Rb]; }\n\n### Bit Manipulation Instructions (V3) ###\n\n:bitc Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b10010 { Rt = Ra & (~Rb); }\n:bitci Rt, Ra, Imm15u is $(I32) & Opc=0b110011 & Rt & Ra & Imm15u { Rt = Ra & (~Imm15u); }\n\n### Cache Control Instruction (V3) ###\n\n# TODO: Add CCTL L1D_WBALL, level\n\n\n### 32-bit ISA extension ###\n\n### ALU Instruction (Performance) ###\n\n\n:abs Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Rb=0 & $(ALU2Z) & Sub6=0b000011\n{\n gez:4 = zext(Ra s>= 0);\n ltz:4 = zext(Ra s< 0);\n Rt = (Ra * gez) | ((-Ra) * ltz);\n}\n\n:ave Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b000010\n{\n Rt = (Ra + Rb + 1) s>> 2;\n}\n\n:max Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b000000\n{\n altb:4 = zext(Ra s< Rb);\n ageb:4 = zext(Ra s>= Rb);\n Rt = (Ra * ageb) | (Rb * altb);\n}\n\n:min Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b000001\n{\n altb:4 = zext(Ra s< Rb);\n ageb:4 = zext(Ra s>= Rb);\n Rt = (Ra * altb) | (Rb * ageb);\n}\n\n:bset Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001000 { Rt = Ra | (1 << Imm5u); }\n:bclr Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001001 { Rt = Ra & ~(1 << Imm5u); }\n:btgl Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001010 { Rt = Ra ^ (1 << Imm5u); }\n:btst Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001011 { Rt = (Ra >> Imm5u) & 1; }\n\n:clips Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b000100\n{\n local upper:4 = (1 << Imm5u) - 1;\n local lower:4 = -(1 << Imm5u);\n if(Ra s<= upper) goto ;\n Rt = upper;\n goto ;\n \n if(Ra s>= lower) goto ;\n Rt = lower;\n goto ;\n \n Rt = Ra;\n \n}\n:clip Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b000101\n{\n local upper:4 = (1 << Imm5u) - 1;\n if(Ra s<= upper) goto ;\n Rt = upper;\n goto ;\n \n if(Ra s>= 0) goto ;\n Rt = 0;\n goto ;\n \n Rt = Ra;\n \n}\n\n:clz Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Imm5u=0 & $(ALU2Z) & Sub6=0b000111\n{\n countTmp:4 = 0;\n inputTmp:4 = Ra;\n\n \n if ((inputTmp & 0x80000000) != 0) goto ;\n\n countTmp = countTmp + 1;\n inputTmp = (inputTmp << 1) | 1;\n goto ;\n\n \n Rt = countTmp;\n}\n\n:clo Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Imm5u=0 & $(ALU2Z) & Sub6=0b000110\n{\n countTmp:4 = 0;\n inputTmp:4 = Ra;\n\n \n if ((inputTmp & 0x80000000) == 0) goto ;\n\n countTmp = countTmp + 1;\n inputTmp = (inputTmp << 1) | 1;\n goto ;\n\n \n Rt = countTmp;\n}\n\n\n### Performance Extension V2 ###\n\n\n# TODO : arithmetic functions: bs*\n:bse is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b001100 unimpl\n:bsp is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b001101 unimpl\n\nmacro add_abs_diff(dst, src1, src2, shift)\n{\n local src1_ = src1 >> shift;\n local src2_ = src2 >> shift;\n local src1__ = src1_:1;\n local src2__ = src2_:1;\n local a:1 = src1__ - src2__;\n local agez:1 = zext(a s>= 0);\n local altz:1 = zext(a s< 0);\n local aabs:1 = (a * agez) | ((-a) * altz);\n dst = dst + zext(aabs);\n}\n:pbsad Rt, Ra, Rb is $(I32) & $(SIMD) & Rt & Ra & Rb & Rd=0 & Sub5=0b0000\n{\n Rt = 0;\n add_abs_diff(Rt, Ra, Rb, 0);\n add_abs_diff(Rt, Ra, Rb, 8);\n add_abs_diff(Rt, Ra, Rb, 16);\n add_abs_diff(Rt, Ra, Rb, 24);\n}\n:pbsada Rt, Ra, Rb is $(I32) & $(SIMD) & Rt & Ra & Rb & Rd=0 & Sub5=0b0001\n{\n add_abs_diff(Rt, Ra, Rb, 0);\n add_abs_diff(Rt, Ra, Rb, 8);\n add_abs_diff(Rt, Ra, Rb, 16);\n add_abs_diff(Rt, Ra, Rb, 24);\n}\n\n\n# 32-bit String Extension\n:ffb Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b0001110 {\n\tmatch:1 = Rb[0,8];\n\tm1:1 = (Ra[0,8] == match);\n\tm2:1 = (Ra[8,8] == match);\n\tm3:1 = (Ra[16,8] == match);\n\tm4:1 = (Ra[24,8] == match);\n\tRt = -4;\n\tif (m1) goto inst_next;\n\tRt = -3;\n\tif (m2) goto inst_next;\n\tRt = -2;\n\tif (m3) goto inst_next;\n\tRt = -1;\n\tif (m4) goto inst_next;\n\tRt = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n}\n\n:ffbi Rt, Ra, Imm8u is $(I32) & $(ALU_2) & Rt & Ra & Imm8u & Sub7=0b1001110 {\n\tmatch:1 = Imm8u;\n\tm1:1 = (Ra[0,8] == match);\n\tm2:1 = (Ra[8,8] == match);\n\tm3:1 = (Ra[16,8] == match);\n\tm4:1 = (Ra[24,8] == match);\n\tRt = -4;\n\tif (m1) goto inst_next;\n\tRt = -3;\n\tif (m2) goto inst_next;\n\tRt = -2;\n\tif (m3) goto inst_next;\n\tRt = -1;\n\tif (m4) goto inst_next;\n\tRt = 0;\n}\n\n:ffmism Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b0001111 {\n\tmatch:1 = Rb[0,8];\n\tm1:1 = (Ra[0,8] != Rb[0,8]);\n\tm2:1 = (Ra[8,8] != Rb[8,8]);\n\tm3:1 = (Ra[16,8] != Rb[16,8]);\n\tm4:1 = (Ra[24,8] != Rb[24,8]);\n@if ENDIAN == \"little\"\n\tRt = -4;\n\tif (m1) goto inst_next;\n\tRt = -3;\n\tif (m2) goto inst_next;\n\tRt = -2;\n\tif (m3) goto inst_next;\n\tRt = -1;\n\tif (m4) goto inst_next;\n\tRt = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n@else\n\tRt = -4;\n\tif (m4) goto inst_next;\n\tRt = -3;\n\tif (m3) goto inst_next;\n\tRt = -2;\n\tif (m2) goto inst_next;\n\tRt = -1;\n\tif (m1) goto inst_next;\n\tRt = 0;\n@endif\n}\n\n:flmism Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b1001111 {\n\tmatch:1 = Rb[0,8];\n\tm1:1 = (Ra[0,8] != Rb[0,8]);\n\tm2:1 = (Ra[8,8] != Rb[8,8]);\n\tm3:1 = (Ra[16,8] != Rb[16,8]);\n\tm4:1 = (Ra[24,8] != Rb[24,8]);\n@if ENDIAN == \"little\"\n\tRt = -1;\n\tif (m4) goto inst_next;\n\tRt = -2;\n\tif (m3) goto inst_next;\n\tRt = -3;\n\tif (m2) goto inst_next;\n\tRt = -4;\n\tif (m1) goto inst_next;\n\tRt = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n@else\n\tRt = -1;\n\tif (m1) goto inst_next;\n\tRt = -2;\n\tif (m2) goto inst_next;\n\tRt = -3;\n\tif (m3) goto inst_next;\n\tRt = -4;\n\tif (m4) goto inst_next;\n\tRt = 0;\n@endif\n}\n\n########### 16b ############\n\ndefine token instr16(16)\n opsz = (15, 15)\n opc4 = (11, 14)\n opc5 = (10, 14)\n opc6 = (9, 14)\n opc7 = (8, 14)\n opc8 = (7, 14)\n opc10 = (5, 14)\n re2 = (5, 6)\n rt5 = (5, 9)\n ra4 = (5, 8)\n rt4 = (5, 8)\n ra5 = (0, 4)\n rb5 = (0, 4)\n rt5b = (0, 4)\n rt3 = (6, 8)\n rt3b = (8, 10)\n ra3 = (3, 5)\n rb3 = (0, 2)\n bit5 = (5,5)\n bit6 = (6,6)\n bit7 = (7,7)\n bit8 = (8,8)\n imm3u = (0, 2)\n imm3ub = (3, 5)\n imm4u = (5, 8)\n imm5u = (0, 4)\n imm5s = (0, 4) signed\n imm6u = (0, 5)\n imm7u = (0, 6)\n imm8s = (0, 7) signed\n imm10s = (0, 9) signed\n xwi37_ls = (7, 7)\n swid9 = (0, 8)\n rt5e1 = (4, 7)\n rt5e2 = (4, 7)\n ra5e1 = (0, 3)\n ra5e2 = (0, 3)\n;\n\nattach variables [rt5 ra5 rb5 rt5b] [\n a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp\n];\n\nattach variables [ra4 rt4] [\n a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 t0 t1 t2 t3\n];\n\nattach variables [rt3 ra3 rt3b rb3] [\n a0 a1 a2 a3 a4 a5 s0 s1\n];\n\nattach variables [ra5e1 rt5e1] [\n a0 a2 a4 s0 s2 s4 s6 s8 t0 t2 t4 t6 t8 p0 fp lp\n];\nattach variables [ra5e2 rt5e2] [\n a1 a3 a5 s1 s3 s5 s7 ta t1 t3 t5 t7 t9 p1 gp sp\n];\n\nattach variables [re2] [\n s0 s2 s4 s8\n];\n\n\n@define I16 \"(opsz=1)\"\n@define BFMI333 \"(opc6=0b001011)\"\n@define XWI37 \"(opc4=0b0111)\"\n@define XWI37SP \"(opc4=0b1110)\"\n@define MISC33 \"(opc6=0b111111)\"\n\n\n### Move Instruction ###\n\n:movi55 rt5, imm5s is $(I16) & opc5=0b00001 & rt5 & imm5s { rt5 = imm5s; }\n:mov55 rt5, ra5 is $(I16) & opc5=0b00000 & rt5 & ra5 { rt5 = ra5; }\n\n\n### Add/Sub Instruction with Immediate ###\n\n:addi45 rt4, imm5u is $(I16) & opc6=0b000110 & rt4 & imm5u { rt4 = rt4 + imm5u; }\n:addi333 rt3, ra3, imm3u is $(I16) & opc6=0b001110 & rt3 & ra3 & imm3u { rt3 = ra3 + imm3u; }\n:subi45 rt4, imm5u is $(I16) & opc6=0b000111 & rt4 & imm5u { rt4 = rt4 - imm5u; }\n:subi333 rt3, ra3, imm3u is $(I16) & opc6=0b001111 & rt3 & ra3 & imm3u { rt3 = ra3 - imm3u; }\n\n\n### Add/Sub Instruction ###\n\n:add45 rt4, rb5 is $(I16) & opc6=0b000100 & rt4 & rb5 { rt4 = rt4 + rb5; }\n:add333 rt3, ra3, rb3 is $(I16) & opc6=0b001100 & rt3 & ra3 & rb3 { rt3 = ra3 + rb3; }\n:sub45 rt4, rb5 is $(I16) & opc6=0b000101 & rt4 & rb5 { rt4 = rt4 - rb5; }\n:sub333 rt3, ra3, rb3 is $(I16) & opc6=0b001101 & rt3 & ra3 & rb3 { rt3 = ra3 - rb3; }\n\n\n### Shift Instruction with Immediate ###\n\n:srai45 rt4, imm5u is $(I16) & opc6=0b001000 & rt4 & imm5u { rt4 = rt4 s>> imm5u; }\n:srli45 rt4, imm5u is $(I16) & opc6=0b001001 & rt4 & imm5u { rt4 = rt4 >> imm5u; }\n:slli333 rt3, ra3, imm3u is $(I16) & opc6=0b001010 & rt3 & ra3 & imm3u { rt3 = ra3 << imm3u; }\n\n\n### Bit Field Mask Instruction with Immediate ###\n\n:zeb33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b000 { local tmp = ra3; rt3 = zext(tmp:1); }\n:zeh33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b001 { local tmp = ra3; rt3 = zext(tmp:2); }\n:seb33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b010 { local tmp = ra3; rt3 = sext(tmp:1); }\n:seh33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b011 { local tmp = ra3; rt3 = sext(tmp:2); }\n:xlsb33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b100 { rt3 = ra3 & 1; }\n:x11b33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b101 { rt3 = ra3 & 0x7ff; }\n\n\n### Load / Store Instruction ###\n\n:lwi450 rt4,[ra5] is $(I16) & opc6=0b011010 & rt4 & ra5 { rt4 = *ra5; }\n\nrel3w: off is imm3u [ off = imm3u << 2; ] { export *[const]:4 off; }\nrel3h: off is imm3u [ off = imm3u << 1; ] { export *[const]:4 off; }\nrel3b: off is imm3u [ off = imm3u << 0 ; ] { export *[const]:4 off; }\nra3_rel3w: [ra3 + rel3w] is ra3 & rel3w { addr:4 = ra3 + rel3w; export addr; }\nra3_rel3h: [ra3 + rel3h] is ra3 & rel3h { addr:4 = ra3 + rel3h; export addr; }\nra3_rel3b: [ra3 + rel3b] is ra3 & rel3b { addr:4 = ra3 + rel3b; export addr; }\n\n:lwi333 rt3, ra3_rel3w is $(I16) & opc6=0b010000 & rt3 & ra3_rel3w { rt3 = *ra3_rel3w; }\n:lwi333.bi rt3, [ra3], rel3w is $(I16) & opc6=0b010001 & rt3 & ra3 & rel3w { rt3 = *ra3; ra3 = ra3 + rel3w; }\n:lhi333 rt3, ra3_rel3h is $(I16) & opc6=0b010010 & rt3 & ra3_rel3h { local tmp:2 = *ra3_rel3h; rt3 = zext(tmp); }\n:lbi333 rt3, ra3_rel3b is $(I16) & opc6=0b010011 & rt3 & ra3_rel3b { local tmp:1 = *ra3_rel3b; rt3 = zext(tmp); }\n:swi450 rt4, [ra5] is $(I16) & opc6=0b011011 & rt4 & ra5 { *ra5 = rt4; }\n:swi333 rt3, ra3_rel3w is $(I16) & opc6=0b010100 & rt3 & ra3_rel3w { *ra3_rel3w = rt3; }\n:swi333.bi rt3, [ra3], rel3w is $(I16) & opc6=0b010101 & rt3 & ra3 & rel3w { *ra3 = rt3; ra3 = ra3 + rel3w; }\n:shi333 rt3, ra3_rel3h is $(I16) & opc6=0b010110 & rt3 & ra3_rel3h { local tmp = rt3; *ra3_rel3h = tmp:2; }\n:sbi333 rt3, ra3_rel3b is $(I16) & opc6=0b010111 & rt3 & ra3_rel3b { local tmp = rt3; *ra3_rel3b = tmp:1; }\n\n\n### Load/Store Instruction with Implied FP ###\n\nrel7w: off is imm7u [ off = imm7u << 2; ] { export *[const]:4 off; }\nfp_rel7w: [fp + rel7w] is fp & rel7w { addr:4 = fp + rel7w; export addr; }\n\n:lwi37 rt3b, fp_rel7w is $(I16) & rt3b & $(XWI37) & xwi37_ls=0 & fp_rel7w { rt3b = *fp_rel7w; }\n:swi37 rt3b, fp_rel7w is $(I16) & rt3b & $(XWI37) & xwi37_ls=1 & fp_rel7w { *fp_rel7w = rt3b; }\n\n\n### Branch and Jump Instruction ###\n\nrel8: addr is imm8s [ addr = inst_start + (imm8s << 1); ] { export *:4 addr; }\n\n\n:beqs38 rt3b,rel8 is $(I16) & opc4=0b1010 & rt3b & rel8 { if(a5 == rt3b) goto rel8; }\n:bnes38 rt3b,rel8 is $(I16) & opc4=0b1011 & rt3b & rel8 { if(a5 != rt3b) goto rel8; }\n:beqz38 rt3b,rel8 is $(I16) & opc4=0b1000 & rt3b & rel8 { if(rt3b == 0) goto rel8; }\n:bnez38 rt3b,rel8 is $(I16) & opc4=0b1001 & rt3b & rel8 { if(rt3b != 0) goto rel8; }\n\n:j8 rel8 is $(I16) & opc7=0b1010101 & rel8 { goto rel8; }\n:jr5 rb5 is $(I16) & opc10=0b1011101000 & rb5 { goto [rb5]; }\n:ret5 rb5 is $(I16) & opc10=0b1011101100 & rb5 { return [rb5]; }\n:jral5 rb5 is $(I16) & opc10=0b1011101001 & rb5 { lp = inst_next; call [rb5]; }\n\n\n### Compare and Branch Instruction ###\n\n:slti45 ra4, imm5u is $(I16) & opc6=0b110011 & ra4 & imm5u { ta = zext(ra4 < imm5u); }\n:sltsi45 ra4, imm5u is $(I16) & opc6=0b110010 & ra4 & imm5u { ta = zext(ra4 s< imm5u); }\n:slt45 ra4, rb5 is $(I16) & opc6=0b110001 & ra4 & rb5 { ta = zext(ra4 < rb5); }\n:slts45 ra4, rb5 is $(I16) & opc6=0b110000 & ra4 & rb5 { ta = zext(ra4 s< rb5); }\n\n:beqzs8 rel8 is $(I16) & opc7=0b1101000 & rel8 { if(ta == 0) goto rel8; }\n:bnezs8 rel8 is $(I16) & opc7=0b1101001 & rel8 { if(ta != 0) goto rel8; }\n\n\n### Misc Instruction ###\n\n# V3 doesn't allow break16 with SWID greater than 31\n:break16 swid9 is $(I16) & opc6=0b110101 & imm4u=0 & swid9 { break(swid9:4); }\n:nop16 is $(I16) & opc6=0b001001 & rt4=0 & imm5u=0 { }\n\n\n### ALU Instructions (V2) ###\n\n:addi10.sp imm10s is $(I16) & opc5=0b11011 & imm10s { sp = sp + imm10s; }\n\n\n### Load/Store Instruction (V2) ###\n\nsp_rel7w: [+ rel7w] is rel7w { addr:4 = sp + rel7w; export addr; }\n\n:lwi37.sp rt3b, sp_rel7w is $(I16) & rt3b & $(XWI37SP) & xwi37_ls=0 & sp_rel7w { rt3b = *sp_rel7w; }\n:swi37.sp rt3b, sp_rel7w is $(I16) & rt3b & $(XWI37SP) & xwi37_ls=1 & sp_rel7w { *sp_rel7w = rt3b; }\n\n\n\n### 16-bit Baseline V3 instructions ###\n\n### ALU Instructions (V3 16-bit) ###\n\nimm6u_: imm8 is imm6u [ imm8 = imm6u << 2; ] { export *[const]:4 imm8; }\n:addri36.sp rt3, imm6u_ is $(I16) & opc6=0b011000 & rt3 & imm6u_ { rt3 = sp + imm6u_; }\n:add5.pc rt5b is $(I16) & opc10=0b1011101101 & rt5b { rt5b = pc + rt5b; }\n:and33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b110 { rt3 = rt3 & ra3; }\n:neg33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b010 { rt3 = -ra3; }\n:not33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b011 { rt3 = ~ra3; }\n:or33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b111 { rt3 = rt3 | ra3; }\n:xor33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b101 { rt3 = rt3 ^ ra3; }\n\n### Bit Manipulation Instructions (V3 16-bit) ###\n\n:bmski33 rt3, imm3ub is $(I16) & opc6=0b001011 & rt3 & imm3ub & imm3u=0b110 { rt3 = (rt3 >> imm3ub) & 1; }\n:fexti33 rt3, imm3ub is $(I16) & opc6=0b001011 & rt3 & imm3ub & imm3u=0b111 { rt3 = rt3 & ((1 << (imm3ub + 1)) - 1); }\n\n### Misc. Instructions (V3 16-bit) ###\n\nimm7n: off is imm5u [ off = -((32 - imm5u) << 2); ] { export *[const]:4 off; }\n:lwi45.fe rt4, [imm7n] is $(I16) & opc6=0b011001 & rt4 & imm7n { addr:4 = s2 + imm7n; rt4 = *addr; }\n\n:movd44 rt5e1, ra5e1 is $(I16) & opc7=0b1111101 & rt5e1 & rt5e2 & ra5e1 & ra5e2 { rt5e1 = ra5e1; rt5e2 = ra5e2; }\n\nimm5u_: imm6 is imm5u [ imm6 = imm5u + 16; ] { export *[const]:4 imm6; }\n:movpi45 rt4, imm5u_ is $(I16) & opc6=0b111101 & rt4 & imm5u_ { rt4 = imm5u_; }\n\n:mul33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b100 { rt3 = rt3 * ra3; }\n\n# Note: POP25 and PUSH25 are highly untested ! And they just look messy :/\nimm5u__: imm8 is imm5u [ imm8 = imm5u << 3; ] { export *[const]:4 imm8; }\n\nmacro push25_special() { Smwad(lp); Smwad(gp); Smwad(fp); }\nmacro push25_s0() { Smwad(s0); }\nmacro push25_s2() { Smwad(s2); Smwad(s1); push25_s0(); }\nmacro push25_s4() { Smwad(s4); Smwad(s3); push25_s2(); }\nmacro push25_s8() { Smwad(s8); Smwad(s7); Smwad(s6); Smwad(s5); push25_s4(); }\n\npush25_re: re2 is re2 & re2=0 { push25_s0(); }\npush25_re: re2 is re2 & re2=1 { push25_s2(); }\npush25_re: re2 is re2 & re2=2 { push25_s4(); }\npush25_re: re2 is re2 & re2=3 { push25_s8(); }\n\n:push25 push25_re, imm5u__ is $(I16) & opc8=0b11111000 & re2 & push25_re & imm5u__ {\n\tmult_addr = sp;\n\tpush25_special();\n\tbuild push25_re;\n\tsp = mult_addr - imm5u__;\n\tif(re2 < 1) goto ;\n\t\ts2 = pc & 0xfffffffc;\n\t\n}\n\nmacro pop25_special() { LmwOp(fp); LmwOp(gp); LmwOp(lp); }\nmacro pop25_s0() { LmwOp(s0); }\nmacro pop25_s2() { pop25_s0(); LmwOp(s1); LmwOp(s2); }\nmacro pop25_s4() { pop25_s2(); LmwOp(s3); LmwOp(s4); }\nmacro pop25_s8() { pop25_s4(); LmwOp(s5); LmwOp(s6); LmwOp(s7); LmwOp(s8); }\n\npop25_re: re2 is re2 & re2=0 { pop25_s0(); }\npop25_re: re2 is re2 & re2=1 { pop25_s2(); }\npop25_re: re2 is re2 & re2=2 { pop25_s4(); }\npop25_re: re2 is re2 & re2=3 { pop25_s8(); }\n\n:pop25 pop25_re, imm5u__ is $(I16) & opc8=0b11111001 & re2 & pop25_re & imm5u__ {\n\tmult_addr = sp;\n\tbuild pop25_re;\n\tpop25_special();\n\tsp = mult_addr + imm5u__;\n\treturn [lp];\n}\n\n\n# EX9.IT\n\nimm9u_: imm9 is imm5u & imm4u [ imm9 = (imm4u << 5) | imm5u; ] { export *[const]:4 imm9; }\ndefine pcodeop ex9;\n\n# TODO: Depending on the value of ITB.HW the address is either set by hardware or set by ITB.Addr\n:ex9.it imm9u_ is $(I16) & opc6=0b110101 & (bit5=1 | bit6=1 | bit7=1 | bit8=1) & imm9u_ {\n\tex9(imm9u_);\n}\n\n:ex9.it imm5u is $(I16) & opc10=0b1011101010 & imm5u {\n\tex9(imm5u:4);\n}\n\n\n##########################\n# Floating Point Extension\n\n# FPU_FS1\ndefine pcodeop fadds;\n:fadds Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x0 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fadds(Fsa, Fsb);\n}\n\ndefine pcodeop fsubs;\n:fsubs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x1 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fsubs(Fsa, Fsb);\n}\n\ndefine pcodeop fcpynss;\n:fcpynss Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x2 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fcpynss(Fsa, Fsb);\n}\n\ndefine pcodeop fcpyss;\n:fcpyss Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x3 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fcpyss(Fsa, Fsb);\n}\n\ndefine pcodeop fmadds;\n:fmadds Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x4 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fmadds(Fsa, Fsb);\n}\n\ndefine pcodeop fmsubs;\n:fmsubs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x5 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fmsubs(Fsa, Fsb);\n}\n\ndefine pcodeop fcmovns;\n:fcmovns Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x6 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fcmovns(Fsa, Fsb);\n}\n\ndefine pcodeop fcmovzs;\n:fcmovzs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x7 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fcmovzs(Fsa, Fsb);\n}\n\ndefine pcodeop fnmadds;\n:fnmadds Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x8 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fnmadds(Fsa, Fsb);\n}\n\ndefine pcodeop fnmsubs;\n:fnmsubs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x9 & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fnmsubs(Fsa, Fsb);\n}\n\ndefine pcodeop fmuls;\n:fmuls Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xa & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fmuls(Fsa, Fsb);\n}\n\ndefine pcodeop fdivs;\n:fdivs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xb & Fst & Fsa & Fsb & cop4=0x0 {\n\tFst = fdivs(Fsa, Fsb);\n}\n\n# FPU_FS1_F2OP\n\ndefine pcodeop fs2d;\n:fs2d Fdt, Fsa is $(I32) & $(COP) & fop4=0xf & Fdt & Fsa & f2op=0 & cop4=0x0 {\n\tFdt = fs2d(Fsa);\n}\n\ndefine pcodeop fsqrts;\n:fsqrts Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=1 & cop4=0x0 {\n\tFst = fsqrts(Fsa);\n}\n\ndefine pcodeop fabss;\n:fabss Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x5 & cop4=0x0 {\n\tFst = fabss(Fsa);\n}\n\ndefine pcodeop fui2s;\n:fui2s Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x8 & cop4=0x0 {\n\tFst = fui2s(Fsa);\n}\n\ndefine pcodeop fsi2s;\n:fsi2s Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0xc & cop4=0x0 {\n\tFst = fsi2s(Fsa);\n}\n\ndefine pcodeop fs2ui;\n:fs2ui Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x10 & cop4=0x0 {\n\tFst = fs2ui(Fsa);\n}\n\ndefine pcodeop fs2ui.z;\n:fs2ui.z Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x14 & cop4=0x0 {\n\tFst = fs2ui.z(Fsa);\n}\n\ndefine pcodeop fs2si;\n:fs2si Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x18 & cop4=0x0 {\n\tFst = fs2si(Fsa);\n}\n\ndefine pcodeop fs2si.z;\n:fs2si.z Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x1c & cop4=0x0 {\n\tFst = fs2si.z(Fsa);\n}\n\n# FPU_FS2\nfcond: \"eq\" is fcnd=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nfcond: \"lt\" is fcnd=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nfcond: \"le\" is fcnd=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nfcond: \"un\" is fcnd=3 { local tmp:1 = 3; export *[const]:1 tmp; }\n\nfcmpe: \"\" is cmpe=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nfcmpe: \".e\" is cmpe=1 { local tmp:1 = 1; export *[const]:1 tmp; }\ndefine pcodeop fcmps;\n:fcmp^fcond^\"s\"^fcmpe Fst, Fsa, Fsb is $(I32) & $(COP) & Fst & Fsa & Fsb & cop4=0x4 & fcond & fcmpe {\n\tFst = fcmps(Fsa, Fsb, fcond, fcmpe);\n}\n\n# FPU_FD1\n\ndefine pcodeop faddd;\n:faddd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x0 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = faddd(Fda, Fdb);\n}\n\ndefine pcodeop fsubd;\n:fsubd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x1 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fsubd(Fda, Fdb);\n}\n\ndefine pcodeop fcpynsd;\n:fcpynsd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x2 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fcpynsd(Fda, Fdb);\n}\n\ndefine pcodeop fcpysd;\n:fcpysd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x3 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fcpysd(Fda, Fdb);\n}\n\ndefine pcodeop fmaddd;\n:fmaddd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x4 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fmaddd(Fda, Fdb);\n}\n\ndefine pcodeop fmsubd;\n:fmsubd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x5 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fmsubd(Fda, Fdb);\n}\n\ndefine pcodeop fcmovnd;\n:fcmovnd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x6 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fcmovnd(Fda, Fdb);\n}\n\ndefine pcodeop fcmovzd;\n:fcmovzd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x7 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fcmovzd(Fda, Fdb);\n}\n\ndefine pcodeop fnmaddd;\n:fnmaddd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x8 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fnmaddd(Fda, Fdb);\n}\n\ndefine pcodeop fnmsubd;\n:fnmsubd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x9 & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fnmsubd(Fda, Fdb);\n}\n\ndefine pcodeop fmuld;\n:fmuld Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xa & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fmuld(Fda, Fdb);\n}\n\ndefine pcodeop fdivd;\n:fdivd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xb & Fdt & Fda & Fdb & cop4=0x8 {\n\tFdt = fdivd(Fda, Fdb);\n}\n\n# FPU_FD1_F2OP\ndefine pcodeop fd2s;\n:fd2s Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0 & cop4=0x8 {\n\tFst = fd2s(Fda);\n}\n\ndefine pcodeop fsqrtd;\n:fsqrtd Fdt, Fda is $(I32) & $(COP) & fop4=0xf & Fdt & Fda & f2op=1 & cop4=0x8 {\n\tFdt = fsqrtd(Fda);\n}\n\ndefine pcodeop fabsd;\n:fabsd Fdt, Fda is $(I32) & $(COP) & fop4=0xf & Fdt & Fda & f2op=0x5 & cop4=0x8 {\n\tFdt = fabsd(Fda);\n}\n\ndefine pcodeop fui2d;\n:fui2d Fdt, Fsa is $(I32) & $(COP) & fop4=0xf & Fdt & Fsa & f2op=0x8 & cop4=0x8 {\n\tFdt = fui2d(Fsa);\n}\n\ndefine pcodeop fsi2d;\n:fsi2d Fdt, Fsa is $(I32) & $(COP) & fop4=0xf & Fdt & Fsa & f2op=0xc & cop4=0x8 {\n\tFdt = fsi2d(Fsa);\n}\n\ndefine pcodeop fd2ui;\n:fd2ui Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x10 & cop4=0x8 {\n\tFst = fd2ui(Fda);\n}\n\ndefine pcodeop fd2ui.z;\n:fd2ui.z Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x14 & cop4=0x8 {\n\tFst = fs2ui.z(Fda);\n}\n\ndefine pcodeop fd2si;\n:fd2si Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x18 & cop4=0x8 {\n\tFst = fd2si(Fda);\n}\n\ndefine pcodeop fd2si.z;\n:fd2si.z Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x1c & cop4=0x8 {\n\tFst = fs2si.z(Fda);\n}\n\n# FPU_FS2\ndefine pcodeop fcmpd;\n:fcmp^fcond^\"d\"^fcmpe Fst, Fda, Fdb is $(I32) & $(COP) & Fst & Fda & Fdb & cop4=0xc & fcond & fcmpe {\n\tFst = fcmpd(Fda, Fdb, fcond, fcmpe);\n}\n\n# FPU_MFCP\ndefine pcodeop fmfsr;\n:fmfsr Rt, Fsa is $(I32) & $(COP) & fop4=0x0 & Rt & Fsa & f2op=0x0 & cop4=0x1 {\n\tRt = fmfsr(Fsa);\n}\n\ndefine pcodeop fmfdr;\n:fmfdr Rt, Fda is $(I32) & $(COP) & fop4=0x1 & Rt & Fda & f2op=0x0 & cop4=0x1 {\n\tRt = fmfdr(Fda);\n}\n\n# FPU_MTCP\ndefine pcodeop fmtsr;\n:fmtsr Rt, Fsa is $(I32) & $(COP) & fop4=0x0 & Rt & Fsa & f2op=0x0 & cop4=0x9 {\n\tFsa = fmtsr(Rt);\n}\n\ndefine pcodeop fmtdr;\n:fmtdr Rt, Fda is $(I32) & $(COP) & fop4=0x1 & Rt & Fda & f2op=0x0 & cop4=0x9 {\n\tFda = fmtdr(Rt);\n}\n\n# FPU_FLS\n\n:fls Fst, AddrRaRbsv is $(I32) & $(COP) & Fst & AddrRaRbsv & fbi=0 & cop4=0x2 {\n\tFst = *AddrRaRbsv;\n}\n\n:fls.bi Fst [Ra], OffsetRbsv is $(I32) & $(COP) & Fst & Ra & OffsetRbsv & fbi=1 & cop4=2 {\n\tFst = *Ra;\n\tRa = Ra + OffsetRbsv;\n}\n\n# FPU_FLD\n\n:fld Fdt, AddrRaRbsv is $(I32) & $(COP) & Fdt & AddrRaRbsv & fbi=0 & cop4=0x3 {\n\tFdt = *AddrRaRbsv;\n}\n\n:fld.bi Fdt [Ra], OffsetRbsv is $(I32) & $(COP) & Fdt & Ra & OffsetRbsv & fbi=1 & cop4=3 {\n\tFdt = *Ra;\n\tRa = Ra + OffsetRbsv;\n}\n\n# FPU_FSS\n\n:fss Fst, AddrRaRbsv is $(I32) & $(COP) & Fst & AddrRaRbsv & fbi=0 & cop4=0xa {\n\t*AddrRaRbsv = Fst;\n}\n\n:fss.bi Fst [Ra], OffsetRbsv is $(I32) & $(COP) & Fst & Ra & OffsetRbsv & fbi=1 & cop4=0xa {\n\t*Ra = Fst;\n\tRa = Ra + OffsetRbsv;\n}\n\n# FPU_FSD\n:fsd Fdt, AddrRaRbsv is $(I32) & $(COP) & Fdt & AddrRaRbsv & fbi=0 & cop4=0xb {\n\t*AddrRaRbsv = Fdt;\n}\n\n:fsd.bi Fdt [Ra], OffsetRbsv is $(I32) & $(COP) & Fdt & Ra & OffsetRbsv & fbi=1 & cop4=0xb {\n\t*Ra = Fdt;\n\tRa = Ra + OffsetRbsv;\n}\n\n\n# LWC0\nAddrRaImm12s: [Ra + offs] is Ra & Imm12s [ offs = Imm12s << 2; ] { addr:4 = Ra + offs; export addr; }\nOffImm12s: (offs) is Imm12s [ offs = Imm12s << 2; ] { export *[const]:4 offs; }\n\n:flsi Fst, AddrRaImm12s is $(I32) & $(LWC) & Fst & cpn=0 & fsbi=0 & AddrRaImm12s {\n\tFst = *AddrRaImm12s;\n}\n\n:flsi.bi Fst [Ra], OffImm12s is $(I32) & $(LWC) & Fst & Ra & cpn=0 & fsbi=1 & OffImm12s {\n\tFst = *Ra;\n\tRa = Ra + OffImm12s;\n}\n\n# LDC0\n\n:fldi Fdt, AddrRaImm12s is $(I32) & $(LDC) & Fdt & cpn=0 & fsbi=0 & AddrRaImm12s {\n\tFdt = *AddrRaImm12s;\n}\n\n:fldi.bi Fdt [Ra], OffImm12s is $(I32) & $(LDC) & Fdt & Ra & cpn=0 & fsbi=1 & OffImm12s {\n\tFdt = *Ra;\n\tRa = Ra + OffImm12s;\n}\n\n# SWC0\n\n:fssi Fst, AddrRaImm12s is $(I32) & $(SWC) & Fst & cpn=0 & fsbi=0 & AddrRaImm12s {\n\t*AddrRaImm12s = Fst;\n}\n\n:fssi.bi Fst [Ra], OffImm12s is $(I32) & $(SWC) & Fst & Ra & cpn=0 & fsbi=1 & OffImm12s {\n\t*Ra = Fst;\n\tRa = Ra + OffImm12s;\n}\n\n# SDC0\n:fsdi Fdt, AddrRaImm12s is $(I32) & $(SDC) & Fdt & cpn=0 & fsbi=0 & AddrRaImm12s {\n\t*AddrRaImm12s = Fdt;\n}\n\n:fsdi.bi Fdt [Ra], OffImm12s is $(I32) & $(SDC) & Fdt & Ra & cpn=0 & fsbi=1 & OffImm12s {\n\t*Ra = Fdt;\n\tRa = Ra + OffImm12s;\n}\n\n:fmfcfg Rt is $(I32) & $(COP) & fop4=0xc & Rt & f2op=0x0 & cop4=0x1 {\n\tRt = fpcfg;\n}\n\n:fmfcsr Rt is $(I32) & $(COP) & fop4=0xc & Rt & f2op=0x1 & cop4=0x1 {\n\tRt = fpcsr;\n}\n\n:fmtcsr Rt is $(I32) & $(COP) & fop4=0xc & Rt & Fsa & f2op=0x1 & cop4=0x9 {\n\tfpcsr = Rt;\n}\n\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32be.slaspec", "content": "@define ENDIAN \"big\"\n\n@include \"nds32.sinc\"\n" }, { "path": "pypcode/processors/NDS32/data/languages/nds32le.slaspec", "content": "@define ENDIAN \"little\"\n\n@include \"nds32.sinc\"\n" }, { "path": "pypcode/processors/NDS32/data/patterns/nds32_patterns.xml", "content": "\n \n \n 0xfc 1....... \n 0xdd 0x9e \n \n \n 0xfc 0....... \n \n \n \n" }, { "path": "pypcode/processors/NDS32/data/patterns/patternconstraints.xml", "content": "\n \n nds32_patterns.xml\n \n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-risc.ldefs", "content": "\n\n\n \n Generic PA-RISC 32-bit big endian\n \n \n \n \n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-risc.opinion", "content": "\n\t\n\t\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-risc.sinc", "content": "# PA-RISC common specification file for 32 and 64-bit processors\n# Appropriate defines (PARISC32, PARISC64) must be\n# specified before including this file\n\n# Known Issues:\n# The branch target is annotated onto the line following the branch, not the branch itself\n# There may still be issues with condition codes and instructions like INST,=,N r2,r3,r2 that write back into one of the input argument registers.\n# The condition uses the final value in r2, when it should use the value passed in to r2 before the operation.\n# The implementation of space registers is incorrect. There should really be a 64 bit address space with space register in the upper 64 bits.\n# Right now, the space register is either ignored or else just added to the base address.\n# Some of the pcode could be simplified.\n\n\n# Attention- Sometimes the source and destination registers can be the same registers.\n# When you write to a destination reg, it's important that your pcode always keeps a temp copy\n# of the original if you later refer to a source reg.\n\n\n# Register conventions\n#\n# r0 is always 0\n# r1 scratch register, caller saved\n# r2 is rp is the return pointer\n# r3 to r18 callee saves\n# r19 to r22 caller saves\n# r23 is arg3\n# r24 is arg2\n# r25 is arg1\n# r26 is arg0\n# r27 is the global data pointer dp and must be set to the .data symbol in the elf header\n# r28 is ret0 the subroutine return value, high order word if a 64-bit return value\n# r29 is ret1 the low order word of a 64-bit return value\n# r30 is sp the stack pointer\n# r31 is the millicode return pointer\n#\n# fr0 is farg0 if floating arg is 32-bits, 64-bit args are in farg1 high and low\n# fr1 is farg0 if floating arg is 32-bits\n# fr2 is farg0 if floating arg is 32-bits, 64-bit args are in farg3 high and low\n# fr0 is farg0 if floating arg is 32-bits\n# fr4 is fret floating point return (8 bytes)\n#\n# Note- only two double arguments can be passed in registers.\n# If a function return value is larger than 64 bits, then the caller passes the address in r28\n#\n# Note- function calls and returns are usually through relocation stubs\n#\n\n#-----\n@ifdef PARISC64\n@define REGSIZE \"8\" # General purpose register size (8 or 4)\n@define ADDRSIZE \"8\" # Memory address size (8 bytes in 64 bit mode)\n\n@else # PARISC32\n@define REGSIZE \"4\" # General purpose register size (8 or 4)\n@define ADDRSIZE \"4\" # Memory address size (8 bytes, using the space registers as the upper 32 bits and the regular base and offset as the lower 32 bits)\n@endif\n#-----\n\ndefine endian=$(ENDIAN);\n\ndefine alignment=4;\n\n# I'm not sure what to set for the sizes of these spaces -- TODO set these correctly\ndefine space ram type=ram_space size=$(ADDRSIZE) default;\ndefine space register type=register_space size=4; # this is a large enough address space to address all the registers. Two bytes would probably be enough\n\n# General purpose registers\ndefine register offset=0 size=$(REGSIZE) [ \n r0 r1 rp r3\n r4 r5 r6 r7\n r8 r9 r10 r11\n r12 r13 r14 r15\n r16 r17 r18 r19\n r20 r21 r22 r23\n r24 r25 r26 dp\n r28 r29 sp r31 \n];\n\n# Floating point registers\ndefine register offset=0x1000 size=8 [\n fr0 fpe23 fpe45 fpe67 fr4 fr5 fr6 fr7\n fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15\n fr16 fr17 fr18 fr19 fr20 fr21 fr22 fr23\n fr24 fr25 fr26 fr27 fr28 fr29 fr30 fr31\n];\n\ndefine register offset=0x1000 size=4 [\n\tfr0R fr0L fpe2 fpe3 fpe4 fpe5 fpe6 fpe7\n\tfr4L fr4R fr5L fr5R fr6L fr6R fr7L fr7R\n\tfr8L fr8R fr9L fr9R fr10L fr10R\n\tfr11L fr11R fr12L fr12R fr13L fr13R fr14L fr14R\n\tfr15L fr15R fr16L fr16R fr17L fr17R fr18L fr18R\n\tfr19L fr19R fr20L fr20R fr21L fr21R fr22L fr22R\n\tfr23L fr23R fr24L fr24R fr25L fr25R fr26L fr26R\n\tfr27L fr27R fr28L fr28R fr29L fr29R fr30L fr30R\n\tfr31L fr31R\n];\n\n# Floating Point Status Register\n# Only the compare bit and the compare queue are implemented here\n# and the Condition Queue is only 8 bits, rather than 10\ndefine register offset=0x1100 size=1 [\n\tcompareBit\tcompareQueue\n];\n\n# Shadow Registers\ndefine register offset=0x2000 size=$(REGSIZE) [\n\tshr0 shr1 shr2 shr3 shr4 shr5 shr6\n];\n\n# Space Registers\ndefine register offset=0x3000 size=4 [\n\tsr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7\n];\n\n# Processor Status Word\ndefine register offset=0x4000 size=1 [\n\tpswY pswZ pswE pswS pswT pswH pswL pswN pswX pswB pswC pswV pswM pswCB pswG pswF pswR pswQ pswP pswD pswI\n];\n\n# Control Registers\ndefine register offset=0x5000 size=4 [\n\tcr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7\n\tcr8 cr9 cr10 sar cr12 cr13 cr14 cr15\n\tcr16 cr17 cr18 cr19 cr20 cr21 cr22 cr23\n\tcr24 cr25 cr26 cr27 cr28 cr29 cr30 cr31\n];\n\n# instruction address offset and instruction address space queues\n# these are used for branching, to compute target addresses and deal with branch delay slots\ndefine register offset=0x6000 size=4 [\n\tiasq_front iasq_back iaoq_front iaoq_back\n];\n\n# special hidden registers to support the nullify and delay slot features of PA-RISC\ndefine register offset=0x7000 size=1 [nullifyCond nullifyNextCond branchCond branchExecuted]; \ndefine register offset=0x7100 size=4 [branchIndDest nullifyCondResult];\n\ndefine register offset=0x7200 size=12 contextreg;\ndefine context contextreg\n\n # transient context \n phase = (0,2) noflow\n temp1\t\t = (3,3)\n \n # stored context\n nullifyEnable = (4,4) noflow\n branchCouldBeNullified = (5,5) noflow\n branchEnable = (6,6) noflow\n branchType = (7,9) noflow\n# These do not appear to be used:\n# branchIsInd = (7,7) noflow\n# branchIsCond = (8,8) noflow\n# branchIsCall = (9,9) noflow\n branchIsReturn = (10,10) noflow # used for returns\n padding = (10,31) noflow\n branchImmDest = (32,63) noflow \n temp32 = (64,95) noflow\n;\n\n@define COMMON \"phase=1 \" \n\n# Instruction fields\n\ndefine token instr(32)\n opfam\t = (26,31)\n cr\t\t\t= (21,25)\n crname2\t\t= (21,25)\n freg2\t\t= (21,25)\n freg2sgl\t= (21,25)\n fr2half\t\t= (21,25)\n fusedr2\t\t= (21,25)\n reg2 = (21,25)\n b\t\t\t= (21,25)\n bboffset\t= (21,25)\n crname1\t\t= (21,25)\n bit20\t\t= (20,20) signed\n fpc1sub2\t= (17,20)\n highIm10\t= (16,25)\n reg1 = (16,20)\n fusedr1\t\t= (16,20)\n freg1\t\t= (16,20)\n freg1sgl\t= (16,20)\n fr1half\t\t= (16,20)\n r = (16,20)\n highIm5\t\t= (16,20) signed\n highIm5less16\t= (17,20)\n tr\t\t\t= (16,20)\n x\t\t\t= (16,20)\n w1\t\t\t= (16,20)\n bit16\t\t= (16,16)\n fpc1sub\t\t= (15,16)\n srbit1\t\t= (15,15)\n s\t\t\t= (14,15)\n srbit0\t\t= (14,14)\n im13\t\t= (13,25) signed\n SEDCondSym\t= (13,15)\n RegUnitCondSym\t= (13,15)\n InvUnitCondSym\t= (13,15)\n RegLogicCondSym = (13,15)\n InvLogicCondSym = (13,15)\n RegAddCondSym\t= (13,15)\n InvAddCondSym\t= (13,15)\n RegCSCondSym = (13,15)\n InvCSCondSym = (13,15)\n c = (13,15)\n fpsub\t\t= (13,15)\n srbit2\t\t= (13,13)\n fpdf\t\t= (13,14)\n fixeddf\t\t= (13,14)\n fpdfraw\t\t= (13,14)\n fixedsf\t\t= (13,14)\n a\t\t\t= (13,13)\n u\t\t\t= (13,13)\n fpr1x\t\t= (12,12)\n f\t\t\t= (12,12)\n fv\t\t\t= (12,12)\n zero\t\t= (12,12)\n one\t\t\t= (12,12)\n subop1012\t= (10,12)\n im15\t\t= (11,25)\n sopim10\t\t= (11,20) signed\n sopim5\t\t= (11,15) signed\n fpta\t\t= (11,15)\n fusedta\t\t= (11,15)\n fpsf\t\t= (11,12)\n fpsfraw\t\t= (11,12)\n fpfmt\t\t= (11,12)\n fpfmt1bit\t= (11,11)\n bit11\t\t= (11,11)\n cc\t\t\t= (10,11)\n ldcc\t\t= (10,11)\n stcc\t\t= (10,11)\n ldcwcc\t\t= (10,11)\n bit10\t\t= (10,10)\n sopim17\t\t= (9,25)\n pmuop\t\t= (9,13)\n specop\t\t= (9,10)\n fpclass\t\t= (9,10)\n bit9\t\t= (9,9)\n bit8\t\t= (8,8)\n fpx\t\t\t= (8,8)\n bits78\t\t= (7,8)\n fpr2x\t\t= (7,7)\n fpra\t\t= (6,10)\n fusedra\t\t= (6,10)\n ext4\t\t= (6,9)\n C\t\t\t= (6,9)\n subop\t\t= (6,9)\n sysopshifted= (6,13)\n sysopshiftedshort\t= (6,12)\n op\t\t\t= (6,11)\n sfu\t\t\t= (6,8)\n fp0czero\t= (6,8)\n fptx\t\t= (6,6)\t\t\n bit6\t\t= (6,6)\n sysop\t\t= (5,12)\n i2\t\t\t= (5,11)\n bits59\t\t= (5,9)\n cp\t\t\t= (5,9)\n fusedfmt\t= (5,5)\n bit5\t\t= (5,5)\n m\t\t\t= (5,5)\n spn\t\t\t= (5,5)\n w2\t\t\t= (2,12)\n w2_2\t\t= (2,2)\n w2less2\t\t= (3,12)\n n\t\t\t= (1,1)\n im26\t\t= (0,25) signed\n sim21\t\t= (0,20) signed\n sim14\t\t= (0,13) signed\n im21less0\t= (1,20)\n im21_1_12\t= (1,11)\n im21_12_14\t= (12,13)\n im21_14_16\t= (14,15)\n im21_16_21\t= (16,20)\n im14\t\t= (0,13)\n im14less0\t= (1,13)\n im11\t\t= (0,10) signed\n im11less0\t= (1,11)\n sim5\t\t= (0,4) signed\n im5\t\t\t= (0,4)\n im5less0\t= (1,4)\n fpcond\t\t= (0,4)\n fptest\t\t= (0,4)\n fpt\t\t\t= (0,4)\n fptsgl\t\t= (0,4)\n fusedrt\t\t= (0,4)\n fpthalf\t\t= (0,4)\n crnamet\t\t= (0,4)\n t\t\t\t= (0,4)\n bit0\t\t= (0,0)\n w\t\t\t= (0,0) \n;\n\n# general purpose registers\nattach variables [reg1 reg2 t r b x] [\n\tr0 r1 rp r3 r4 r5 r6 r7\n\tr8 r9 r10 r11 r12 r13 r14 r15\n\tr16 r17 r18 r19 r20 r21 r22 r23\n\tr24 r25 r26 dp r28 r29 sp r31\n];\n\n# fp registers - 64 bit doubles\nattach variables [ freg2 freg1 fpt fpra fpta ] [ \n fr0 fpe23 fpe45 fpe67 fr4 fr5 fr6 fr7\n fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15\n fr16 fr17 fr18 fr19 fr20 fr21 fr22 fr23\n fr24 fr25 fr26 fr27 fr28 fr29 fr30 fr31\n];\n\n# 64 bit fp registers when used as 32 bit (.sgl completer)\n# This mapping goes from bit pattern N -> register NL\nattach variables [ freg2sgl freg1sgl fptsgl ] [ \n fr0L fpe2 fpe4 fpe6 fr4L fr5L fr6L fr7L\n fr8L fr9L fr10L fr11L fr12L fr13L fr14L fr15L\n fr16L fr17L fr18L fr19L fr20L fr21L fr22L fr23L\n fr24L fr25L fr26L fr27L fr28L fr29L fr30L fr31L\n];\n\n# 32 bit single precision mode fpra fpta for mult-add and mult-sub instructions\nattach variables [ fusedra fusedta fusedr2 fusedr1 fusedrt ] [ \n fr16L fr17L fr18L fr19L fr20L fr21L fr22L fr23L\n fr24L fr25L fr26L fr27L fr28L fr29L fr30L fr31L\n fr16R fr17R fr18R fr19R fr20R fr21R fr22R fr23R\n fr24R fr25R fr26R fr27R fr28R fr29R fr30R fr31R\n];\n\n# control registers\nattach variables [ cr ] [\n\tcr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7\n\tcr8 cr9 cr10 sar cr12 cr13 cr14 cr15\n\tcr16 cr17 cr18 cr19 cr20 cr21 cr22 cr23\n\tcr24 cr25 cr26 cr27 cr28 cr29 cr30 cr31\n];\n\n# control registers by their purpose names\nattach names [ crname2 crname1 crnamet ] [\n\tRCTR CR1 CR2 CR3 CR4 CR5 CR6 CR7\n\tPID1 PID2 CCR SAR PID3 PID4 IVA EIEM\n\tITMR IIASQ IIAOQ IIR ISR IOR IPSW EIRR\n\tTMP0 TMP1 TMP2 TMP3 TMP4 TMP5 TMP6 TMP7 \n];\n\nattach names [ ldcc ] [\n\tnone resv sl resv\n];\n\nattach names [ stcc ] [\n\tnone BC SL resv\n];\n\nattach names [ ldcwcc ] [\n\tnone CO resv resv\n];\n\n# Table 5-7\nattach names [ SEDCondSym ] [\n\t\"\" \",=\" \",<\" \",OD\" \",TR\" \",<>\" \",>=\" \",EV\"\n];\n\nattach names [ RegUnitCondSym ] [\n\t\"\" _ \",SBZ\" \",SHZ\" \",SDC\" _ \",SBC\" \",SHC\"\n];\n\nattach names [ InvUnitCondSym ] [\n\t\"\" _ \",NBZ\" \",NHZ\" \",NDC\" _ \",NBC\" \",NHC\"\n];\n\nattach names [ RegLogicCondSym ] [\n\t\"\" \",=\" \",<\" \",<=\" _ _ _ \",OD\"\n];\n\nattach names [ InvLogicCondSym ] [\n\t\"\" \",<>\" \",>=\" \",>\" _ _ _ \",EV\"\n];\n\n# Table 5-4\nattach names [ RegAddCondSym ] [\n\t\"\" \",=\" \",<\" \",<=\" \",NUV\" \",ZNV\" \",SV\" \",OD\"\n];\n\nattach names [ InvAddCondSym ] [\n\t\"\" \",<>\" \",>=\" \",>\" \",UV\" \",VNZ\" \",NSV\" \",EV\"\n];\n\nattach names [ RegCSCondSym ] [\n\t\"\" \",=\" \",<\" \",<=\" \",<<\" \",<<=\" \",SV\" \",OD\"\n];\n\nattach names [ InvCSCondSym ] [\n\t\"\" \",<>\" \",>=\" \",>\" \",>>=\" \",>>\" \",NSV\" \",EV\"\n];\n\n# the different tests used by the FTEST instruction\nattach names [ fptest ] [\n\t\"\" \"ACC\" \"REJ\" _ _ \"ACC8\" \"REJ8\" _ _ \"ACC6\" _ _ _ \"ACC4\" _ _ _ \"ACC2\" _ _ _ _ _ _ _ _ _ _ _ _ _ _\n];\n\n# the floating point number types\nattach names [ fpsf fpdf fpfmt ] [\n\t\",SGL\" \",DBL\" \",QUAD\" _\n];\n\nattach names [ fpfmt1bit ] [\n\t\",SGL\" \",DBL\"\n];\n\n# the fixed point number types\nattach names [ fixedsf fixeddf ] [\n\t\",UW\" \",UD\" \",UQ\" _\n];\n\n# the floating point number types for fused ops\nattach names [ fusedfmt ] [\n\t\",DBL\" \",SGL\" \n];\n\n\n######################################################################################\n# caret instruction builders for nullify and branch\n######################################################################################\n# These all assume a fall through from a preceding branch\n# If there is a branch into the delay slot of a different branch,\n# then the branch logic will still be present from the preceding instruction\n# and the control flow will branch to that destination.\n# This case should result in a red bookmark due to the disassembly context difference\n# These all also assume that the instruction following a branch (in the delay slot)\n# does not nullify its succeeding instruction \n#######################################################################################\n# no branch, no nullify\n# previous instruction was not a branch and did not nullify this instruction\n:^instruction is phase=0 & branchEnable=0 & nullifyEnable=0 & instruction [ phase=1; ] {\n\tnullifyNextCond=0;\n\t\tbuild instruction;\n\tnullifyCond=nullifyNextCond;\n}\n\n# previous instruction was not a branch, but may have conditionally nullified this instruction\n:^instruction is phase=0 & branchEnable=0 & nullifyEnable=1 & instruction [ phase=1; ] {\n\tlocal wasNullified = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tif (wasNullified) goto ;\n\t\tbuild instruction;\n\t\tnullifyCond=nullifyNextCond;\n\t\t\n}\n\n#\n# Handle branches that don't nullify their branch delay slot instructions\n# These instructions themselves may have been nullified, so we need to\n# check and conditionally execute the branch based on that.\n#\n# Need to reset branchCond = 0 before build instruction because the insruction does not reset it,\n# and if branchcond is not reset, then it persists to subsequent instructions.\n\nimmediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }\n\n# previous instruction was a branch, but this instruction was not nullified\n# but branch instruction could have been nullified\n# branchType = 0, unconditional immediate branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=0 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( previousBranchExecuted ) goto immediateDest;\n\tnullifyCond=nullifyNextCond;\n}\n\n# previous instruction was a branch, but this instruction was not nullified\n# branchType = 0, unconditional immediate branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=0 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n branchCond = 0;\n\tbranchExecuted=0;\n\tbuild instruction;\n\tgoto immediateDest;\n}\n\n# branchType = 1, unconditional immediate call\n# this doesn't handle the case where the inst in the delay slot nullifies the next instruction\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=1 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! previousBranchExecuted ) goto ;\n\tcall immediateDest;\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 1, unconditional immediate call\n# this doesn't handle the case where the inst in the delay slot nullifies the next instruction\n# this is the case where the branch could not have been nullified\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=1 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tcall immediateDest;\n}\n\n# branchType = 2, conditional immediate branch\n# the preceding instruction was a branch that may or may not have been taken and may or may not have been nullified\n# but was not nullifying itself (the delay slot must execute)\n# this doesn't handle the case where the instruction in the branch delay slot nullifies the next instruction\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=2 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbuild instruction;\n\tif (previousBranchCond && previousBranchExecuted) goto immediateDest;\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 2, conditional immediate branch\n# the preceding instruction was a branch that may or may not have been taken and may or may not have been nullified\n# but was not nullifying itself (the delay slot must execute)\n# this doesn't handle the case where the instruction in the branch delay slot nullifies the next instruction\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=2 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbuild instruction;\n\tif (previousBranchCond) goto immediateDest;\n\tnullifyCond=nullifyNextCond;}\n\n# branchType = 3, conditional immediate call, (currently not used, may not exist in PA-RISC)\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=3 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! (previousBranchCond && previousBranchExecuted) ) goto ;\n\tcall immediateDest;\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 3, conditional immediate call, (currently not used, may not exist in PA-RISC)\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=3 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tnullifyNextCond=0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! (previousBranchCond) ) goto ;\n\tcall immediateDest;\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 4, unconditional indirect branch\n# the preceding instruction was a branch that did not nullify its branch delay slot inst\n# The branch is indirect and may have been nullified\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=1 & branchType=4 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! previousBranchExecuted ) goto ;\n\tgoto [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 4, unconditional indirect branch and also return\n# the preceding instruction was a branch that did not nullify its branch delay slot inst\n# The branch is indirect and WAS NOT nullified\n#\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=0 & branchType=4 & instruction & branchIsReturn=0 [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tgoto [branchIndDest];\n}\n\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=0 & branchType=4 & instruction & branchIsReturn=1 [ phase=1; ] {\n nullifyCond = 0;\n nullifyNextCond = 0;\n branchExecuted = 0;\n build instruction;\n return [branchIndDest];\n}\n\n\n# branchType = 5, unconditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=5 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! previousBranchExecuted ) goto ;\n\t\tcall [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 5, unconditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=5 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tcall [branchIndDest];\n}\n\n# branchType = 6, conditional indirect branch\n# previous instruction was a conditional branch that may or may not be taken and may have been nullified\n# however, the branch does not nullify the inst in its branch delay slot\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=6 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! previousBranchExecuted || ! previousBranchCond) goto ;\n\tgoto [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 6, conditional indirect branch\n# previous instruction was a conditional branch that may or may not be taken and may have been nullified\n# however, the branch does not nullify the inst in its branch delay slot\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=6 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbuild instruction;\n\tif ( ! previousBranchCond ) goto ;\n\tgoto [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 7, conditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=7 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tbuild instruction;\n\tif ( ! previousBranchExecuted || ! previousBranchCond) goto ;\n\tcall [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 7, conditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=7 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond= branchCond;\n\tbranchCond = 0;\n\tbuild instruction;\n\tif ( ! previousBranchCond) goto ;\n\tcall [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n#\n# Handle branches with nullification -- the branch may nullify its branch delay slot\n#\n\n# branchType = 0, unconditional immediate branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=0 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tif ( previousBranchExecuted ) goto immediateDest;\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 0, unconditional immediate branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=0 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tgoto immediateDest;\n}\n\n# branchType = 1, unconditional immediate call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=1 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tif ( ! previousBranchExecuted ) goto ;\n\tcall immediateDest;\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 1, unconditional immediate call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=1 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tcall immediateDest;\n}\n\n# branchType = 2, conditional immediate branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=2 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tif (previousBranchCond && previousBranchExecuted) goto immediateDest;\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 2, conditional immediate branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=2 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n\tbranchCond = 0; # Need to reset branchCond\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tif (previousBranchCond) goto immediateDest;\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 3, conditional immediate call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=3 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tif ( ! (previousBranchCond && previousBranchExecuted) ) goto ;\n\tcall immediateDest;\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 3, conditional immediate call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=3 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyNextCond=0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\tbuild instruction;\n\t\n\tif ( ! previousBranchCond ) goto ;\n\tcall immediateDest;\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 4, unconditional indirect branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=4 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tif ( ! previousBranchExecuted ) goto ;\n\tgoto [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 4, unconditional indirect branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=4 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tgoto [branchIndDest];\n}\n\n# branchType = 5, unconditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=5 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tif ( ! previousBranchExecuted ) goto ;\n\tcall [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 5, unconditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=5 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond = 0;\n\tbranchExecuted = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tcall [branchIndDest];\n}\n\n# branchType = 6, conditional indirect branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=6 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tif ( ! previousBranchExecuted || ! previousBranchCond) goto ;\n\tgoto [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 6, conditional indirect branch\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=6 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyCond = 0;\n\tnullifyNextCond=0;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tif ( ! previousBranchCond) goto ;\n\tgoto [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 7, conditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=7 & branchCouldBeNullified=1 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyNextCond=0;\n\tlocal previousBranchExecuted = branchExecuted;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n branchCond = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tif ( ! previousBranchExecuted || ! previousBranchCond) goto ;\n\tcall [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n# branchType = 7, conditional indirect call\n:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=7 & branchCouldBeNullified=0 & instruction [ phase=1; ] {\n\tlocal nullify = nullifyCond;\n\tnullifyNextCond=0;\n\tbranchExecuted = 0;\n\tlocal previousBranchCond = branchCond;\n\tbranchCond = 0;\n\tif (nullify) goto ;\n\t\tbuild instruction;\n\t\n\tif ( ! previousBranchCond ) goto ;\n\tcall [branchIndDest];\n\t\n\tnullifyCond=nullifyNextCond;\n}\n\n############################################################\n# Subconstructors\n############################################################\n\n#############################\n# general purpose registers selected \n# by different fields for different purposes (index, base, general, src, target, ...)\n#############################\nR1: reg1\t\t\t\t\tis reg1 & reg1=0 { export 0:$(REGSIZE); }\nR1: reg1\t\t\t\t\tis reg1 { export reg1; }\nR1dst: reg1\t\t\t\t\tis reg1 { export reg1; }\n\nR2: reg2\t\t\t\t\tis reg2 & reg2=0 { export 0:$(REGSIZE); }\nR2: reg2\t\t\t\t\tis reg2 { export reg2; }\nR2dst: reg2\t\t\t\t\tis reg2 { export reg2; }\n\nRT:\tt\t\t\t\t\t\tis t { export t; }\n\nRB: b\t\t\t\t\t\tis b & b=0 { export 0:$(REGSIZE); }\nRB: b\t\t\t\t\t\tis b { export b; }\n\nRX:\t\t\t\t\t\t\tis x=0 { export 0:$(REGSIZE); }\nRX: x\t\t\t\t\t\tis x { export x; }\n\nRR: r\t\t\t\t\t\tis r & r=0 { export 0:$(REGSIZE); }\nRR: r\t\t\t\t\t\tis r { export r; }\n\nSAR: \"SAR\"\t\t\t\tis epsilon { export sar; }\nSR0: sr0\t\t\t\tis sr0 { export sr0; }\nR31: r31\t\t\t\tis r31 { export r31; }\n\n# 64 bit fp register access\nFPR164: freg1\t\t\t\tis freg1 { export freg1; }\nFPR264: freg2\t\t\t\tis freg2 { export freg2; }\nFPRT64: fpt\t\t\t\t\tis fpt { export fpt; }\n\n# register encoding for fused ops (fmpyadd, fmpysub)\nFUSEDR1: fusedr1\t\t\tis fusedr1 { export fusedr1; }\nFUSEDR2: fusedr2\t\t\tis fusedr2 { export fusedr2; }\nFUSEDRA: fusedra\t\t\tis fusedra { export fusedra; }\nFUSEDTA: fusedta\t\t\tis fusedta { export fusedta; }\nFUSEDRT: fusedrt\t\t\tis fusedrt { export fusedrt; }\n\n# 32 bit fp register access, lower half (L) and upper half (R)\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 0 { export fr0L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 1 { export fpe2; }\nFPR132: freg1^\"L\"\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 2 { export fpe4; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 3 { export fpe6; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 4 { export fr4L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 5 { export fr5L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 6 { export fr6L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 7 { export fr7L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 8 { export fr8L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 9 { export fr9L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 10 { export fr10L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 11 { export fr11L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 12 { export fr12L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 13 { export fr13L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 14 { export fr14L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 15 { export fr15L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 16 { export fr16L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 17 { export fr17L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 18 { export fr18L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 19 { export fr19L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 20 { export fr20L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 21 { export fr21L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 22 { export fr22L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 23 { export fr23L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 24 { export fr24L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 25 { export fr25L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 26 { export fr26L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 27 { export fr27L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 28 { export fr28L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 29 { export fr29L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 30 { export fr30L; }\nFPR132: freg1^\"L\"\t\t\t\t\tis fpr1x = 0 & freg1 & fr1half = 31 { export fr31L; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 0 { export fr0R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 1 { export fpe3; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 2 { export fpe5; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 3 { export fpe7; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 4 { export fr4R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 5 { export fr5R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 6 { export fr6R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 7 { export fr7R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 8 { export fr8R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 9 { export fr9R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 10 { export fr10R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 11 { export fr11R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 12 { export fr12R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 13 { export fr13R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 14 { export fr14R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 15 { export fr15R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 16 { export fr16R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 17 { export fr17R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 18 { export fr18R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 19 { export fr19R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 20 { export fr20R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 21 { export fr21R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 22 { export fr22R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 23 { export fr23R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 24 { export fr24R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 25 { export fr25R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 26 { export fr26R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 27 { export fr27R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 28 { export fr28R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 29 { export fr29R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 30 { export fr30R; }\nFPR132: freg1^\"R\"\t\t\t\t\tis freg1 & fpr1x = 1 & fr1half = 31 { export fr31R; }\n\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 0 { export fr0L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 1 { export fpe2; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 2 { export fpe4; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 3 { export fpe6; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 4 { export fr4L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 5 { export fr5L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 6 { export fr6L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 7 { export fr7L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 8 { export fr8L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 9 { export fr9L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 10 { export fr10L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 11 { export fr11L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 12 { export fr12L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 13 { export fr13L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 14 { export fr14L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 15 { export fr15L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 16 { export fr16L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 17 { export fr17L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 18 { export fr18L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 19 { export fr19L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 20 { export fr20L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 21 { export fr21L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 22 { export fr22L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 23 { export fr23L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 24 { export fr24L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 25 { export fr25L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 26 { export fr26L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 27 { export fr27L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 28 { export fr28L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 29 { export fr29L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 30 { export fr30L; }\nFPR232: freg2^\"L\"\t\t\t\t\tis fpr2x = 0 & freg2 & fr2half = 31 { export fr31L; }\n\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 0 { export fr0R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 1 { export fpe3; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 2 { export fpe5; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 3 { export fpe7; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 4 { export fr4R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 5 { export fr5R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 6 { export fr6R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 7 { export fr7R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 8 { export fr8R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 9 { export fr9R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 10 { export fr10R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 11 { export fr11R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 12 { export fr12R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 13 { export fr13R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 14 { export fr14R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 15 { export fr15R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 16 { export fr16R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 17 { export fr17R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 18 { export fr18R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 19 { export fr19R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 20 { export fr20R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 21 { export fr21R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 22 { export fr22R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 23 { export fr23R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 24 { export fr24R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 25 { export fr25R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 26 { export fr26R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 27 { export fr27R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 28 { export fr28R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 29 { export fr29R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 30 { export fr30R; }\nFPR232: freg2^\"R\"\t\t\t\t\tis freg2 & fpr2x = 1 & fr2half = 31 { export fr31R; }\n\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 0 { export fr0L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 1 { export fpe2; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 2 { export fpe4; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 3 { export fpe6; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 4 { export fr4L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 5 { export fr5L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 6 { export fr6L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 7 { export fr7L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 8 { export fr8L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 9 { export fr9L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 10 { export fr10L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 11 { export fr11L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 12 { export fr12L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 13 { export fr13L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 14 { export fr14L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 15 { export fr15L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 16 { export fr16L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 17 { export fr17L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 18 { export fr18L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 19 { export fr19L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 20 { export fr20L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 21 { export fr21L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 22 { export fr22L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 23 { export fr23L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 24 { export fr24L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 25 { export fr25L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 26 { export fr26L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 27 { export fr27L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 28 { export fr28L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 29 { export fr29L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 30 { export fr30L; }\nFPRT32: fpt^\"L\"\t\t\t\t\tis fptx = 0 & fpt & fpthalf = 31 { export fr31L; }\n\n# 32 bit fp register access, upper half (R)\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 0 { export fr0R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 1 { export fpe3; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 2 { export fpe5; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 3 { export fpe7; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 4 { export fr4R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 5 { export fr5R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 6 { export fr6R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 7 { export fr7R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 8 { export fr8R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 9 { export fr9R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 10 { export fr10R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 11 { export fr11R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 12 { export fr12R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 13 { export fr13R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 14 { export fr14R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 15 { export fr15R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 16 { export fr16R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 17 { export fr17R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 18 { export fr18R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 19 { export fr19R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 20 { export fr20R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 21 { export fr21R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 22 { export fr22R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 23 { export fr23R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 24 { export fr24R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 25 { export fr25R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 26 { export fr26R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 27 { export fr27R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 28 { export fr28R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 29 { export fr29R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 30 { export fr30R; }\nFPRT32: fpt^\"R\"\t\t\t\t\tis fptx = 1 & fpt & fpthalf = 31 { export fr31R; }\n\n\nfpcmp: \",FALSE?\"\t\tis fpcond=0 { result:1 = 0; export result; }\nfpcmp: \",false\"\t\t\tis fpcond=1 { result:1 = 0; export result; }\nfpcmp: \",?\"\t\t\t\tis fpcond=2 { result:1 = 0; export result; }\nfpcmp: \",!<=>\"\t\t\tis fpcond=3 { result:1 = 0; export result; }\nfpcmp: \",=\"\t\t\t\tis fpcond=4 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; }\nfpcmp: \",=T\"\t\t\tis fpcond=5 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; }\nfpcmp: \",?=\"\t\t\tis fpcond=6 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; }\nfpcmp: \",!<>\"\t\t\tis fpcond=7 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; }\nfpcmp: \",!?>=\"\t\t\tis fpcond=8 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; }\nfpcmp: \",<\"\t\t\t\tis fpcond=9 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; }\nfpcmp: \",?<\"\t\t\tis fpcond=10 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; }\nfpcmp: \",!>=\"\t\t\tis fpcond=11 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; }\nfpcmp: \",!?>\"\t\t\tis fpcond=12 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; }\nfpcmp: \",<=\"\t\t\tis fpcond=13 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; }\nfpcmp: \",?<=\"\t\t\tis fpcond=14 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; }\nfpcmp: \",!>\"\t\t\tis fpcond=15 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; }\nfpcmp: \",!?<=\"\t\t\tis fpcond=16 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; }\nfpcmp: \",>\"\t\t\t\tis fpcond=17 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; }\nfpcmp: \",?>\"\t\t\tis fpcond=18 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; }\nfpcmp: \",!<=\"\t\t\tis fpcond=19 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; }\nfpcmp: \",!?<\"\t\t\tis fpcond=20 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; }\nfpcmp: \",>=\"\t\t\tis fpcond=21 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; }\nfpcmp: \",?>=\"\t\t\tis fpcond=22 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; }\nfpcmp: \",!<;\"\t\t\tis fpcond=23 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; }\nfpcmp: \",!?=\"\t\t\tis fpcond=24 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; }\nfpcmp: \",<>\"\t\t\tis fpcond=25 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; }\nfpcmp: \",!=\"\t\t\tis fpcond=26 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; }\nfpcmp: \",!=T\"\t\t\tis fpcond=27 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; }\nfpcmp: \",!?\"\t\t\tis fpcond=28 { result:1 = 1; export result; }\nfpcmp: \",<=>\"\t\t\tis fpcond=29 { result:1 = 1; export result; }\nfpcmp: \",TRUE?\"\t\t\tis fpcond=30 { result:1 = 1; export result; }\nfpcmp: \",TRUE\"\t\t\tis fpcond=31 { result:1 = 1; export result; }\n\nfpcmp64: \",FALSE?\"\t\tis fpcond=0 { result:1 = 0; export result; }\nfpcmp64: \",false\"\t\tis fpcond=1 { result:1 = 0; export result; }\nfpcmp64: \",?\"\t\t\tis fpcond=2 { result:1 = 0; export result; }\nfpcmp64: \",!<=>;\"\t\tis fpcond=3 { result:1 = 0; export result; }\nfpcmp64: \",=\"\t\t\tis fpcond=4 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; }\nfpcmp64: \",=T\"\t\t\tis fpcond=5 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; }\nfpcmp64: \",?=\"\t\t\tis fpcond=6 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; }\nfpcmp64: \",!<>\"\t\t\tis fpcond=7 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; }\nfpcmp64: \",!?>=\"\t\tis fpcond=8 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; }\nfpcmp64: \",<\"\t\t\tis fpcond=9 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; }\nfpcmp64: \",?<\"\t\t\tis fpcond=10 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; }\nfpcmp64: \",!>=\"\t\t\tis fpcond=11 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; }\nfpcmp64: \",!?>\"\t\t\tis fpcond=12 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; }\nfpcmp64: \",<=\"\t\t\tis fpcond=13 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; }\nfpcmp64: \",?<=\"\t\t\tis fpcond=14 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; }\nfpcmp64: \",!>\"\t\t\tis fpcond=15 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; }\nfpcmp64: \",!?<=\"\t\tis fpcond=16 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; }\nfpcmp64: \",>\"\t\t\tis fpcond=17 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; }\nfpcmp64: \",?>\"\t\t\tis fpcond=18 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; }\nfpcmp64: \",!<=\"\t\t\tis fpcond=19 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; }\nfpcmp64: \",!?<\"\t\t\tis fpcond=20 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; }\nfpcmp64: \",>=\"\t\t\tis fpcond=21 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; }\nfpcmp64: \",?>=\"\t\t\tis fpcond=22 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; }\nfpcmp64: \",!<\"\t\t\tis fpcond=23 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; }\nfpcmp64: \",!?=\"\t\t\tis fpcond=24 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; }\nfpcmp64: \",<>\"\t\t\tis fpcond=25 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; }\nfpcmp64: \",!=\"\t\t\tis fpcond=26 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; }\nfpcmp64: \",!=T\"\t\t\tis fpcond=27 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; }\nfpcmp64: \",!?\"\t\t\tis fpcond=28 { result:1 = 1; export result; }\nfpcmp64: \",<=>\"\t\t\tis fpcond=29 { result:1 = 1; export result; }\nfpcmp64: \",TRUE?\"\t\tis fpcond=30 { result:1 = 1; export result; }\nfpcmp64: \",TRUE\"\t\tis fpcond=31 { result:1 = 1; export result; }\n \t\n\n#################################\n# space register subconstructors\n#################################\nSR: \"srN\"\t\t\t\t\tis s = 0 { export 0:4; }\nSR: sr1\t\t\t\t\t\tis s = 1 & sr1 { export sr1; }\nSR: sr2\t\t\t\t\t\tis s = 2 & sr2 { export sr2; }\nSR: sr3\t\t\t\t\t\tis s = 3 & sr3 { export sr3; }\n\nSR3bit: sr0\t\t\t\t\tis srbit2=0 & srbit1=0 & srbit0=0 & sr0 { export sr0; }\nSR3bit: sr1\t\t\t\t\tis srbit2=0 & srbit1=0 & srbit0=1 & sr1 { export sr1; }\nSR3bit: sr2\t\t\t\t\tis srbit2=0 & srbit1=1 & srbit0=0 & sr2 { export sr2; }\nSR3bit: sr3\t\t\t\t\tis srbit2=0 & srbit1=1 & srbit0=1 & sr3 { export sr3; }\nSR3bit: sr4\t\t\t\t\tis srbit2=1 & srbit1=0 & srbit0=0 & sr4 { export sr4; }\nSR3bit: sr5\t\t\t\t\tis srbit2=1 & srbit1=0 & srbit0=1 & sr5 { export sr5; }\nSR3bit: sr6\t\t\t\t\tis srbit2=1 & srbit1=1 & srbit0=0 & sr6 { export sr6; }\nSR3bit: sr7\t\t\t\t\tis srbit2=1 & srbit1=1 & srbit0=1 & sr7 { export sr7; }\n\n# These two are the cosmetic constructors for printing purposes\n# They print out SR,RB or else just RB if the space register is determined by the lower bits of RB\n# s=0 means use the least significant two bits of the address in RB as the space register selection (added to 4)\nSRRB: (RB)\t\t\t\t\t\tis RB & s=0 { }\n# s=1-3 means use SR1 - SR3\nSRRB: (SR,RB)\t\t\t\t\tis SR & RB { }\n\n# BE uses three bits for the space register\nSRRB3bit: (SR3bit,RB)\t\t\t\tis SR3bit & RB { }\n\n# these are the semantic constructors dealing with space registers\n# this first one gets the value in the appropriate space register and returns it.\n# it is used by LDSID.\nSRVAL:\tSR\t\t\t\t\t\tis SR & RB & s=0 {\n\t\t\t\t\t\t\t\t local selbits = (RB >> 30);\n\t\t\t\t\t\t\t\t srreg:4 = &sr4 + 4 * selbits;\n\t\t\t\t\t\t\t\t spc:4 = *[register] srreg;\n\t\t\t\t\t\t\t\t export spc; \n}\n\nSRVAL: sr1\t\t\t\t\t\tis sr1 & s=1 { export sr1; }\nSRVAL: sr2\t\t\t\t\t\tis sr2 & s=2 { export sr2; }\nSRVAL: sr3\t\t\t\t\t\tis sr3 & s=3 { export sr3; }\n\n# TODO This is broken until we decide on how to handle space registers and a 64 bit extended address space\nSPCBASE:\t\tis SRVAL & RB {\n#\t\t\t\t\t\t\t\tspace:$(ADDRSIZE) = zext(SRVAL);\n\t\t\t\t\t\t\t\toff:$(ADDRSIZE) = zext(RB); # need to decide whether to remove the lower bits to hide privilege-- TODO & 0xFFFFFFFFFFFFFFFC;\n#\t\t\t\t\t\t\t\taddress:$(ADDRSIZE) = (space << 32) | offset;\n#\t\t\t\t\t\t\t\texport address;\n\t\t\t\t\t\t\t\texport off; \n}\t\t\t\t\n\n###############################################\n# encodings for branches\n###############################################\n# 12 bit displacement encoded using assemble_12\ndisplacement2W: target\t\t\t\tis w & w2 [ target = (1-(w*2)) * ( ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; }\n#branchTarget2W: target\t\t\t\tis w & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; }\n# this has the space register added\n#branchTarget2W: target\t\tis w & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; temp = temp + (iasq_front<<32); export *:$(ADDRSIZE) temp; }\n##### good before caret branchTarget2W: target\t\tis w & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { export *:$(ADDRSIZE) target; }\n#branchTarget2W: target\tis w & w2 [\nbranchTarget2W: target is w & w2less2 & w2_2\n\t[ \n#\t\ttarget = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) );\n\t\ttarget = inst_start + 8 + 4 * (\n\t\t\t((-1 * w) << 11) |\n\t\t\t(w2_2 << 10) |\n\t\t\tw2less2\n\t\t);\n\t\ttemp32 = branchImmDest;\n\t\tbranchImmDest = target;\n\t\tglobalset(inst_next, branchImmDest);\n\t\tbranchImmDest = temp32;\n\t]\n\t{ export *:$(ADDRSIZE) target; }\n\n\n# 17 bit displacement encoded using assemble_17\n#displacement3W: target\t\t\t\tis w & w1 & w2 [ target = 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; }\ndisplacement3W: target\t\t\t\tis w & w1 & w2less2 & w2_2 [ target = 4 * (\n\t((-1 * w) << 16) |\n\t(w1 << 11) |\n\t(w2_2 << 10) |\n\tw2less2\n);] { temp:$(ADDRSIZE) = target; export temp; }\n#branchTarget3W: target\t\t\t\tis w & w1 & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; }\n#branchTarget3W: target\t\t\t\tis w & w1 & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; target = target + (iasq_front << 32); export temp; }\n#####good before caret branchTarget3W: target\t\t\t\tis w & w1 & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { export *:$(ADDRSIZE) target; }\n#branchTarget3W: target\tis w & w1 & w2\nbranchTarget3W: target\t\t\t\tis w & w1 & w2less2 & w2_2\n\t[\n#\t\ttarget = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) );\n\t\ttarget = inst_start + 8 + 4 * (\n\t\t\t((-1 * w) << 16) |\n\t\t\t(w1 << 11) |\n\t\t\t(w2_2 << 10) |\n\t\t\tw2less2\n\t\t);\n\t\ttemp32 = branchImmDest;\n\t\tbranchImmDest = target;\n\t\tglobalset(inst_next, branchImmDest);\n\t\tbranchImmDest = temp32;\n\t]\n\t{ export *:$(ADDRSIZE) target; }\n\n# simple IP relative branch\nIPRelativeIndexedTarget: \t\t\t\t\t\tis RX\n{\n\ttarget:$(ADDRSIZE) = inst_start + (RX<<3) + 8;\n\tbranchIndDest = target;\n\texport target;\n}\n\n# vectored (base register plus index register) branch\nIndexedTarget:\t\t\t\t\t\t\t\t\tis RX & RB\n\t{\n\t\ttarget:$(ADDRSIZE) = (RX<<3) + RB;\n\t\tbranchIndDest = target;\n\t\texport target;\n\t}\n\n# vectored (base register plus index register -- but index register is r0 so skip it since this is a return) branch\nReturnTarget:\t\t\t\t\t\t\t\t\tis RB\n\t{\n\t\tbranchIndDest = RB;\n\t\texport RB;\n\t}\n\n# generate the target address for an external branch\nexternalTarget: displacement3W^SRRB3bit\t\t\t\tis RB & displacement3W & SRRB3bit {\n#\tspaceID:$(ADDRSIZE) = zext(SRVAL);\n#\tspaceID = spaceID << 32;\n#\tspaceID:$(ADDRSIZE) = 0;\n# currently ignoring the spaceID TODO FIX THIS?\n#\ttarget = spaceID + sext(RB) + sext(displacement3W);\n\ttarget:$(ADDRSIZE) = sext(displacement3W) + sext(RB);\n\tbranchIndDest = target;\n\texport target;\n}\n\nshiftC: shift\t\t\t\tis cp [ shift=31-cp; ] { amount:4 = shift; export amount; }\nshiftCLen: shift\t\t\tis im5 [ shift=32-im5; ] { amount:4 = shift; export amount; }\n\n#lse14: offset\t\t\t\tis sim14 & bit0 [ offset = (-1 * bit0) * ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = offset; export temp; }\n#lse14: offset\t\t\t\tis sim14 & bit0 [ offset = (-1 * 0x2000 * bit0) | ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = sext(offset:4); export temp; }\nlse14: off\t\t\t\tis im14less0 & bit0 [ off = ((-1 * bit0) << 13) | im14less0; ] { temp:4 = sext(off:4); export temp; }\n####lse14: offset\t\t\t\tis sim14 & bit0 [ offset = (0xFFFFFFFFFFFFE000 * bit0) | ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = offset; export temp; }\n\n#lse5: offset\t\t\t\tis sim5 & bit0 [ offset = (-1 * 0x10 * bit0) | ( (sim5 >> 1) & 0xF ); ] { temp:1 = sext(offset:1); export temp; }\nlse5: off\t\t\t\tis im5less0 & bit0 [ off = ((-1 * bit0) << 4) | im5less0; ] { temp:1 = sext(off:1); export temp; }\n\n#highlse5: offset\t\t\tis highIm5 & bit16 [ offset = (-1 * 0x10 * bit16) | ( (highIm5 >> 1) & 0xF ); ] { temp:1 = offset; export temp; }\nhighlse5: off\t\t\tis highIm5less16 & bit16 [ off = ((-1 * bit16) << 4) | highIm5less16; ] { temp:1 = off; export temp; }\n\n#lse21: offset\t\t\t\tis sim21 [ offset = ( ((sim21 & 0x1) * 0xFFFFFFFFFFF00000) | ((sim21 & 0xFFE) << 8) | ((sim21 & 0xC000) >> 7) | ((sim21 & 0x1F0000) >> 14) | ((sim21 & 0x3000) >> 12) ) << 11 ; ] { temp:$(REGSIZE) = offset; export temp; }\nlse21: off\t\t\t\tis im21less0 & bit0 & im21_1_12 & im21_12_14 & im21_14_16 & im21_16_21 [\n\toff = (\n\t\t((-1 * bit0) << 20) |\n\t\t(im21_1_12 << 9) |\n\t\t(im21_14_16 << 7) |\n\t\t(im21_16_21 << 2) |\n\t\tim21_12_14\n\t) << 11;\n] { temp:$(REGSIZE) = off; export temp; }\n\n# Note for the im11 11-bit immediate, the sign is in bit 0, and the rest of the value is in bit 1 to 10.\n# Negative numbers are stored 2s complement, with bit0 set to 1.\n#\n# Need to set temp32 to lse11 since the value of lse11 does not propogate so well to uplevel tables, maybe a compiler bug\n#\n#lse11: immed\t\t\t\tis im11 & bit0\nlse11: immed\t\t\t\tis im11less0 & bit0\n\t[ immed\t= ((-1*bit0) << 10) | im11less0; temp32 = immed; ]\n#\t[ immed = (bit0 * 0xFFFFFFFFFFFFFC00) | ( (im11 >> 1) & 0x3FF ); temp32 = immed; ]\n\t{ temp:4 = immed; export temp; }\n\nOFF_BASE_14: lse14^SRRB\tis lse14 & SRRB & SPCBASE { temp:$(ADDRSIZE) = SPCBASE + sext(lse14); export temp; }\n\n#############################\n# condition codes\n#############################\n\n# shift conditions. There are no inverted forms of these conditions.\nShiftCond:\t\t\t\tis c=0 { export 0:1; } # never \nShiftCond:\t\t\t\tis c=1 & RT { tmp:1 = (nullifyCondResult == 0) ; export tmp; } # equal \nShiftCond:\t\t\t\tis c=2 & RT { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) != 0) ; export tmp; } # leftmost bit is one\nShiftCond:\t\t\t\tis c=3 & RT { tmp:1 = ((nullifyCondResult & 0x1) != 0) ; export tmp; } # rightmost bit is 1 (odd)\nShiftCond:\t\t\t\tis c=4 { export 1:1; } # always\nShiftCond:\t\t\t\tis c=5 & RT { tmp:1 = (nullifyCondResult != 0) ; export tmp; } # some bits are one\nShiftCond:\t\t\t\tis c=6 & RT { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) == 0) ; export tmp; } # leftmost bit is zero\nShiftCond:\t\t\t\tis c=7 & RT { tmp:1 = ((nullifyCondResult & 0x1) == 0) ; export tmp; } # rightmost bit is zero (even)\n\nShiftCondNullify:\tis c=0 { }\nShiftCondNullify:\tis ShiftCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = ShiftCond;\n}\n\n# deposit conditions. There are no inverted forms of these conditions.\nDepCond:\t\t\t\tis c=0 { export 0:1; } # never \nDepCond:\t\t\t\tis c=1 { tmp:1 = (nullifyCondResult == 0) ; export tmp; } # equal \nDepCond:\t\t\t\tis c=2 { tmp:1 = (nullifyCondResult s< 0) ; export tmp; } # leftmost bit is one (< 0)\nDepCond:\t\t\t\tis c=3 { tmp:1 = ((nullifyCondResult & 0x1) == 1) ; export tmp; } # rightmost bit is 1 (odd)\nDepCond:\t\t\t\tis c=4 { export 1:1; } # always\nDepCond:\t\t\t\tis c=5 { tmp:1 = (nullifyCondResult != 0) ; export tmp; } # some bits are one\nDepCond:\t\t\t\tis c=6 { tmp:1 = (nullifyCondResult s>= 0) ; export tmp; } # leftmost bit is zero (>=)\nDepCond:\t\t\t\tis c=7 { tmp:1 = ((nullifyCondResult & 0x1) == 0) ; export tmp; } # rightmost bit is zero (even)\n\nDepCondNullify:\tis c=0 { }\nDepCondNullify:\tis DepCond [nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = DepCond;\n}\n\n# extract conditions. The extract ops target R1, not R2 like deposit does\nExtrCond:\t\t\t\tis c=0 { export 0:1; } # never \nExtrCond:\t\t\t\tis c=1 { tmp:1 = (nullifyCondResult == 0); export tmp; } # equal \nExtrCond:\t\t\t\tis c=2 { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) != 0); export tmp; } # leftmost bit is one\nExtrCond:\t\t\t\tis c=3 { tmp:1 = ((nullifyCondResult & 0x1) != 0) ; export tmp; } # rightmost bit is 1 (odd)\nExtrCond:\t\t\t\tis c=4 { export 1:1; } # always\nExtrCond:\t\t\t\tis c=5 { tmp:1 = (nullifyCondResult != 0); export tmp; } # some bits are one\nExtrCond:\t\t\t\tis c=6 { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) == 0); export tmp; } # leftmost bit is zero\nExtrCond:\t\t\t\tis c=7 { tmp:1 = ((nullifyCondResult & 0x1) == 0); export tmp; } # rightmost bit is zero (even)\n\nExtrCondNullify:\tis c=0 { }\nExtrCondNullify:\tis ExtrCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = ExtrCond;\n}\n\n\n# a subset of the SED conditions used for bit tests\nBVBCond:\t\t\t\tis c=2 & R1 { tmp:1 = ((R1 >> (31-sar)) & 0x1) == 1 ; export tmp; } # target bit is one\nBVBCond:\t\t\t\tis c=6 & R1 { tmp:1 = ((R1 >> (31-sar)) & 0x1) == 0 ; export tmp; } # target bit is zero\n\nBBCond:\t\t\t\t\tis c=2 & R1 & bboffset { tmp:1 = ((R1 >> (31-bboffset)) & 0x1) == 1 ; export tmp; } # target bit is one\nBBCond:\t\t\t\t\tis c=6 & R1 & bboffset { tmp:1 = ((R1 >> (31-bboffset)) & 0x1) == 0 ; export tmp; } # target bit is zero\n\n#\n# unit conditions for checking byte ranges within a word\n#\nRegUnitCond:\t\tis c=0 { export 0:1; } # never\nRegUnitCond:\t\tis c=2 & RT { tmp:1 = (RT:1 == 0) || ((RT:2 & 0xFF00) == 0) || ((RT:3 & 0xFF0000) == 0) || ((RT & 0xFF000000) == 0) ; export tmp; } # some byte zero\nRegUnitCond:\t\tis c=3 & RT { tmp:1 = ((RT:2 & 0xFFFF) == 0) || ((RT & 0xFFFF0000) == 0) ; export tmp; } # some halfword zero\nRegUnitCond:\t\tis c=4 { export 0:1; } # some digit carry -- TODO FIGURE OUT BCD\nRegUnitCond:\t\tis c=6 { export 0:1; } # some byte carry -- TODO BCD\nRegUnitCond:\t\tis c=7 { export 0:1; } # some halfword carry -- TODO BCD\n\nUnitCond: \"\"\t\t\tis RegUnitCond & fv=0 { export RegUnitCond; }\nUnitCond: \"\"\t\t\tis RegUnitCond & fv=1 { tmp:1 = ! RegUnitCond; export tmp; }\n\nUnitCondNullify:\tis c=0 & fv=0 { }\nUnitCondNullify:\tis UnitCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = UnitCond;\n}\n\nUnitCondSym: RegUnitCondSym\tis RegUnitCondSym & fv=0 { }\nUnitCondSym: InvUnitCondSym\tis InvUnitCondSym & fv=1 { }\n\n#\n##### The Add Conditions from table 5-4 on page 5-5\n#\nRegAddCond: \t\tis c = 0 { export 0:1; } # never\nRegAddCond: \t\tis c = 1 & R1 & R2 { tmp:1 = (R1 == R2) ; export tmp; } # equal\nRegAddCond: \t\tis c = 2 & R1 & R2 { tmp:1 = (R1 s< -R2) ; export tmp; } # signed less than negative of R2 \nRegAddCond: \t\tis c = 3 & R1 & R2 { tmp:1 = (R1 s<= R2) ; export tmp; } # signed less than or equal to R2\nRegAddCond: \t\tis c = 4 & R1 & R2 { tmp:1 = ! carry(R1,R2) ; export tmp; } # unsigned sum does not overflow\nRegAddCond: \t\tis c = 5 & R1 & R2 { tmp:1 = (R1 + R2) == 0 ; export tmp; } # sum is zero or no overflow (why two definitions??)\nRegAddCond: \t\tis c = 6 & R1 & R2 { tmp:1 = scarry(R1,R2); export tmp; } # signed sum overflows\nRegAddCond: \t\tis c = 7 & R1 & R2 { tmp:1 = ((R1+R2) & 0x1) == 0x1 ; export tmp; } # sum is odd\n\nAddCond:\t\t\tis RegAddCond & fv=0 { export RegAddCond; }\nAddCond:\t\t\tis RegAddCond & fv=1 { tmp:1 = ! RegAddCond; export tmp; }\n\nAddCondNullify:\tis c=0 & fv=0 { }\nAddCondNullify:\tis AddCond [ nullifyEnable=1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = AddCond;\n}\n\nAddCondSym: RegAddCondSym\tis RegAddCondSym & fv=0 { }\nAddCondSym: InvAddCondSym\tis InvAddCondSym & fv=1 { }\n\nRegAddCondI: \t\tis c = 0 { export 0:1; } # never\nRegAddCondI: \t\tis c = 1 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val == -R2) ; export tmp; } # equal to negated\nRegAddCondI: \t\tis c = 2 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val s< -R2) ; export tmp; } # signed less than negated R2 \nRegAddCondI: \t\tis c = 3 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val s<= -R2) ; export tmp; } # signed less than or equal to R2\nRegAddCondI: \t\tis c = 4 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = ! carry(val,R2) ; export tmp; } # unsigned sum does not overflow\nRegAddCondI: \t\tis c = 5 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val + R2) == 0 ; export tmp; } # sum is zero or no overflow (why two definitions??)\nRegAddCondI: \t\tis c = 6 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = scarry(val,R2); export tmp; } # signed sum overflows\nRegAddCondI: \t\tis c = 7 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = ((val+R2) & 0x1) == 0x1 ; export tmp; } # sum is odd\n\n\n# Some notes-\n#\tlse11 is derived from an 11-bit immediate, so we need to take 2 bytes, not 1 byte as in the original coding\n# \tR2 must sometimes be negated before the comparison, as per the manual, Table 5-4\n#\tThe arithmetic comparison must be performed on a larger size temp than the original, so that negating 0x80000000 works correctly\n#\ttemp32 is used because the value of lse11 in the pcode does not flow so well to here - maybe a compiler bug?\n#\n\nRegAddCondI11: is c = 0 { export 0:1; } # never\n\nRegAddCondI11: is temp32 & c = 1 & lse11 & R2 {\n val:8 = sext(temp32:2); tmp_R2:8 = sext(R2);\n\t\t\t\ttmp:1 = (val == -tmp_R2) ; export tmp; } # equal\n\nRegAddCondI11: is temp32 & c = 2 & lse11 & R2 {\n val:8 = sext(temp32:2); tmp_R2:8 = sext(R2);\n\t\t\t\ttmp:1 = (val s< -tmp_R2) ; export tmp; } # signed less than negative of R2\n\nRegAddCondI11: is temp32 & c = 3 & lse11 & R2 {\n\t\t\t\tval:8 = sext(temp32:2); tmp_R2:8 = sext(R2);\n\t\t\t\ttmp:1 = (val s<= -tmp_R2) ; export tmp; } # signed less than or equal to R2\n\nRegAddCondI11: is temp32 & c = 4 & lse11 & R2 {\n\t\t\t\tval:$(REGSIZE) = sext(temp32:2);\n\t\t\t\ttmp:1 = ! carry(val,R2) ; export tmp; } # unsigned sum does not overflow\n\nRegAddCondI11: is temp32 & c = 5 & lse11 & R2 {\n\t\t\t\t# Don't need 64-bit arithmetic here\n\t\t\t\tval:$(REGSIZE) = sext(temp32:2);\n\t\t\t\ttmp:1 = (val + R2) == 0 ; export tmp; } # sum is zero or no overflow (why two definitions??)\n\nRegAddCondI11: is temp32 & c = 6 & lse11 & R2 {\n\t\t\t\tval:$(REGSIZE) = sext(temp32:2);\n\t\t\t\ttmp:1 = scarry(val,R2); export tmp; } # signed sum overflows\n\nRegAddCondI11: is temp32 & c = 7 & lse11 & R2 {\n\t\t\t\tval:8 = sext(temp32:2); tmp_R2:8 = sext(R2);\n\t\t\t\ttmp:1 = ((val+tmp_R2) & 0x1) == 0x1 ; export tmp; } # sum is odd\n\nAddCondI11:\t\tis RegAddCondI11 & fv=0 { export RegAddCondI11; }\nAddCondI11:\t\tis RegAddCondI11 & fv=1 { temp:1 = ! RegAddCondI11; export temp; }\n\nAddCondI11Nullify:\tis c=0 & fv=0 { }\nAddCondI11Nullify:\tis AddCondI11 [ nullifyEnable=1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = AddCondI11;\n}\n\n#\n#### Compare / Subtract Instructions\n#\nRegCSCond: \t\tis c=0 & R1 & R2 { export 0:1; } # never\nRegCSCond: \t\tis c=1 & R1 & R2 { tmp:1 = (R1 == R2) ; export tmp; } # equal\nRegCSCond: \t\tis c=2 & R1 & R2 { tmp:1 = (R1 s< R2) ; export tmp; } # signed less than\nRegCSCond: \t\tis c=3 & R1 & R2 { tmp:1 = (R1 s<= R2) ; export tmp; } # signed less than equal\nRegCSCond: \t\tis c=4 & R1 & R2 { tmp:1 = (R1 < R2) ; export tmp; } # unsigned less than \nRegCSCond: \t\tis c=5 & R1 & R2 { tmp:1 = (R1 <= R2) ; export tmp; } # unsigned less than equal\nRegCSCond: \t\tis c=6 & R1 & R2 { tmp:1 = sborrow(R1,R2) ; export tmp; } # signed minus overflows (borrows)\nRegCSCond: \t\tis c=7 & R1 & R2 { tmp:1 = ((R1 - R2) & 0x1) == 1 ; export tmp; } # odd\n\nCSCond: \tis fv=0 & RegCSCond { export RegCSCond; }\nCSCond: \tis fv=1 & RegCSCond { tmp:1 = ! RegCSCond; export tmp; }\n\nCSCondNullify:\tis c=0 & fv=0 { }\nCSCondNullify:\tis CSCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = CSCond;\n}\n\nCSCondSym: RegCSCondSym\tis RegCSCondSym & fv=0 { }\nCSCondSym: InvCSCondSym\tis InvCSCondSym & fv=1 { }\n\n# The Compare or Subtract conditions compared with 5 bit immediates\n# This is used in the COMIB[TF] instructions. The inverted versions are never used.\nRegCSCondI: \t\tis c=0 & R2 & highlse5 { export 0:1; } # never\nRegCSCondI: \t\tis c=1 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val == R2) ; export tmp; } # equal\nRegCSCondI: \t\tis c=2 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val s< R2) ; export tmp; } # signed less than\nRegCSCondI: \t\tis c=3 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val s<= R2) ; export tmp; } # signed less than equal\nRegCSCondI: \t\tis c=4 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val < R2) ; export tmp; } # unsigned less than \nRegCSCondI: \t\tis c=5 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val <= R2) ; export tmp; } # unsigned less than equal\nRegCSCondI: \t\tis c=6 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); local diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow\nRegCSCondI: \t\tis c=7 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = ((val - R2) & 0x1) == 1 ; export tmp; } # odd\n\n# The Compare or Subtract conditions compared with 11 bit immediates. These are used with the SUBI[O] and COMICLR instructions. Both regular and inverted forms are used.\nRegCSCondI11: \t\tis c=0 & R2 & lse11 { export 0:1; } # never\nRegCSCondI11: \t\tis c=1 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val == R2) ; export tmp; } # equal\nRegCSCondI11: \t\tis c=2 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val s< R2) ; export tmp; } # signed less than\nRegCSCondI11: \t\tis c=3 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val s<= R2) ; export tmp; } # signed less than equal\nRegCSCondI11: \t\tis c=4 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val < R2) ; export tmp; } # unsigned less than \nRegCSCondI11: \t\tis c=5 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val <= R2) ; export tmp; } # unsigned less than equal\nRegCSCondI11: \t\tis c=6 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); local diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow\nRegCSCondI11: \t\tis c=7 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = ((val - R2) & 0x1) == 1 ; export tmp; } # odd\n\nCSCondI11:\t\tis RegCSCondI11 & fv=0 { export RegCSCondI11; }\nCSCondI11:\t\tis RegCSCondI11 & fv=1 { temp:1 = ! RegCSCondI11; export temp; }\n\nCSCondI11Nullify:\tis c=0 & fv=0 { }\nCSCondI11Nullify:\tis CSCondI11 [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = CSCondI11;\n}\n\n#\n#### Logical Conditions\n#\nRegLogicCond:\t\tis c=0 { export 0:1; } # never\nRegLogicCond:\t\tis c=1 & RT { tmp:1 = (RT == 0) ; export tmp; } # equal, all zeros\nRegLogicCond:\t\tis c=2 & RT { tmp:1 = (RT & 0x80000000) != 0 ; export tmp; } # <, leftmost bit is 1\nRegLogicCond:\t\tis c=3 & RT { tmp:1 = ((RT & 0x80000000) != 0) || RT == 0 ; export tmp; } # <=, leftmost bit is 1 or all bits are zero\nRegLogicCond:\t\tis c=7 & RT { tmp:1 = (RT & 0x1) == 0x1; export tmp; } # odd, rightmost bit is 1\n\nLogicCond:\t\tis fv=0 & RegLogicCond { tmp:1 = RegLogicCond; export tmp; } # non-inverted cases\nLogicCond:\t\tis fv=1 & RegLogicCond { tmp:1 = ! RegLogicCond; export tmp; } # inverted cases\n\nLogicCondSym: RegLogicCondSym\tis RegLogicCondSym & fv=0 { }\nLogicCondSym: InvLogicCondSym\tis InvLogicCondSym & fv=1 { }\n\nLogicCondNullify:\tis c=0 & fv=0 { }\nLogicCondNullify:\tis LogicCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]\n{\n\tnullifyNextCond = LogicCond;\n}\n\n##########################################\n# Completers from the tables in chapter 5\n##########################################\n\n# Table 5-11 on page 5-22\n# The shifted form for byte doesn't shift, as byte addressing is single byte aligned\nindexedByteAccessCmplt: \t\t\t\t\tis u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none\nindexedByteAccessCmplt: \",M\"\t\t\t\tis u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX\nindexedByteAccessCmplt: \",S\"\t\t\t\tis u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # S, shift left by 2\nindexedByteAccessCmplt: \",SM\"\t\t\t\tis u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX); export off; } # SM, shift and modify\n\n# The shifted form for halfword shifts by 2 bytes, since that is the size of a halfword\nindexedHalfwordAccessCmplt: \t\t\t\t\tis u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none\nindexedHalfwordAccessCmplt: \",M\"\t\t\t\tis u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX\nindexedHalfwordAccessCmplt: \",S\"\t\t\t\tis u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 1)); export off; } # S, shift left by 1\nindexedHalfwordAccessCmplt: \",SM\"\t\t\t\tis u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 1); export off; } # SM, shift and modify\n\n# The shifted form for words shifts by 2 (x4), since words are aligned on 4 and increment by 4\nindexedWordAccessCmplt: \t\t\t\t\tis u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none\nindexedWordAccessCmplt: \",M\"\t\t\t\tis u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX\nindexedWordAccessCmplt: \",S\"\t\t\t\tis u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 2)); export off; } # S, shift left by 2\nindexedWordAccessCmplt: \",SM\"\t\t\t\tis u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 2); export off; } # SM, shift and modify\n\n# same as above, but shifts by 3 bits. Used for the LDCWX instruction\nindexedDoublewordAccessCmplt: \t\t\t\t\tis u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none\nindexedDoublewordAccessCmplt: \",M\"\t\t\t\tis u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX\nindexedDoublewordAccessCmplt: \",S\"\t\t\t\tis u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 3)); export off; } # S, shift left by 3 NOTE YES THIS IS 3\nindexedDoublewordAccessCmplt: \",SM\"\t\t\tis u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 3); export off; } # SM, shift and modify\n\n# Table 5-12 on Page 5-24\n# these are for loads, e.g. ldws\nshortDispCmplt: \t\t\t\t\t\tis m=0 & highlse5 & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(highlse5); export off; } # no modification\nshortDispCmplt: \",MA\"\t\t\t\t\tis u=0 & m=1 & RB & RX & SPCBASE & highlse5 { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(highlse5); export off; } # modify after\nshortDispCmplt: \",MB\"\t\t\t\t\tis u=1 & m=1 & RB & RX & SPCBASE & highlse5 { local lse = sext(highlse5); off:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export off; } # modify before\n\n# short displacement for stores, e.g. stws\nstoreShortDispCmplt: \t\t\t\t\t\tis m=0 & lse5 & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # no modification\nstoreShortDispCmplt: \",MA\"\t\t\t\t\tis u=0 & m=1 & RB & RX & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(lse5); export off; } # modify after\nstoreShortDispCmplt: \",MB\"\t\t\t\t\tis u=1 & m=1 & RB & RX & SPCBASE & lse5 { local lse = sext(lse5); off:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export off; } # modify before\n\n# Table 5-13 on page 5-26\nstoreBytesShortCmplt: \t\t\t\t\tis u=0 & m=0 & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # none / beginning, don't modify base register\nstoreBytesShortCmplt: \",BM\"\t\t\t\tis u=0 & m=1 & SPCBASE & RR & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export off; } # beginning, modify base register\nstoreBytesShortCmplt: \",E\"\t\t\t\tis u=1 & m=0 & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # ending, don't modify\nstoreBytesShortCmplt: \",EM\"\t\t\t\tis u=1 & m=1 & SPCBASE & RR & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export off; } # ending, modify\n\n# u fixed at 0, Table 5-11 on page 5-22, for LPA and related system level opcodes\nsysCmplt: \t\t\t\t\t\t\tis m=0 { }\nsysCmplt: \",M\"\t\t\t\t\t\tis m=1 { }\n\n# Table 5-8 on page 5-17\nloadCC: \t\t\t\t\t\t\tis cc=0 { }\nloadCC: \",SL\"\t\t\t\t\t\tis cc=2 { }\n\n# Table 5-9 on page 5-18\nstoreCC: \t\t\t\t\t\t\tis cc=0 { }\nstoreCC: \",BC\"\t\t\t\t\t\tis cc=1 { }\nstoreCC: \",SL\"\t\t\t\t\t\tis cc=2 { }\n\n# Table 5-10 on page 5-18\nloadClearCC: \t\t\t\t\t\tis cc=0 { }\nloadClearCC: \",CO\"\t\t\t\t\tis cc=1 { }\n\n# nullification as used with branches\n#####nullifyForBranch:\t\t\t\t\tis n=0 { export 0:1; }\n#####nullifyForBranch: \",N\"\t\t\t\tis n=1 { export 1:1; }\n# caret versions\nnullifyForBranch:\t\t\t\t\t\tis n=0 { export 0:1; }\nnullifyForBranch: \",N\"\t\t\t\t\tis n=1 [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] { export 1:1; }\n\nnullifySymForBranch:\t\t\t\t\tis n=0 { }\nnullifySymForBranch: \",N\"\t\t\t\tis n=1 { }\n\n# nullification as used with special function unit ops\nnullifyForSpecial:\t\t\t\t\t\tis spn=0 { }\nnullifyForSpecial: \",N\"\t\t\t\t\tis spn=1 { }\n\n# Floating point completers\n#csize: \"SGL\"\t\t\t\t\t\t\tis fpsize=0 & opfam=0x0C { }\n#csize: \"DBL\"\t\t\t\t\t\t\tis fpsize=1 & opfam=0x0C { }\n#csize: \"QUAD\"\t\t\t\t\t\t\tis fpsize=3 & opfam=0x0C { }\n\n#esize: \"SGL\"\t\t\t\t\t\t\tis fpsize=0 & opfam=0x0E { }\n#esize: \"DBL\"\t\t\t\t\t\t\tis fpsize=1 & opfam=0x0E { }\n\nSFU: sfu\t\t\t\t\t\t\t\tis sfu { }\n\n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-risc32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-risc32.pspec", "content": "\n\n\n \n \n \n\n \n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-risc32be.slaspec", "content": "# SLA specification file for PA-RISC 32 bit big endian\n\n@define ENDIAN \"big\"\n@define BITS \"32\"\n\n@include \"pa-risc.sinc\"\n@include \"pa-riscInstructions.sinc\"\n\n" }, { "path": "pypcode/processors/PA-RISC/data/languages/pa-riscInstructions.sinc", "content": "############################\n#\n# PA-RISC 1.1 Instructions\n#\n############################\n\nwith : phase=1 {\n\n############################\n# Load and Store and Address Generation Instructions\n############################\n:LDW OFF_BASE_14,R1dst\t\tis opfam=0x12 & OFF_BASE_14 & R1dst {\n\taddr:$(ADDRSIZE) = OFF_BASE_14;\n R1dst = zext(*[ram]:4 addr) ;\n } \n\n:LDH OFF_BASE_14,R1dst\t\tis opfam=0x11 & OFF_BASE_14 & R1dst { \n\taddr:$(ADDRSIZE) = OFF_BASE_14;\n R1dst = zext(*[ram]:2 addr) ;\n}\n\n:LDB OFF_BASE_14,R1dst\t\tis opfam=0x10 & OFF_BASE_14 & R1dst {\n\taddr:$(ADDRSIZE) = OFF_BASE_14;\n R1dst = zext(*[ram]:1 addr) ;\n} \n\n:STW R1,OFF_BASE_14\t\tis opfam=0x1A & OFF_BASE_14 & R1 {\n\taddr:$(ADDRSIZE) = OFF_BASE_14;\n\t*[ram]:4 addr = R1:4; \n } \n\n:STH R1,OFF_BASE_14 \t\tis opfam=0x19 & R1 & OFF_BASE_14 { \n\taddr:$(ADDRSIZE) = OFF_BASE_14;\n\t*[ram]:2 addr = R1:2; \n}\n:STB R1,OFF_BASE_14\t\tis opfam=0x18 & OFF_BASE_14 & R1 {\n\taddr:$(ADDRSIZE) = OFF_BASE_14;\n\t*[ram]:1 addr = R1:1; \n} \n\n:LDW^\",M\" OFF_BASE_14,R1dst\t\tis opfam=0x13 & OFF_BASE_14 & R1dst & RB & SPCBASE & lse14 {\n\toff:$(ADDRSIZE) = 0;\n\tif (lse14 s>= 0x0) goto ;\n\toff = sext(lse14);\n\t \n\taddr:$(ADDRSIZE) = SPCBASE + off;\n\tRB = RB + lse14;\n R1dst = zext( *[ram]:4 addr );\n} \n\n:STW^\",M\" R1,OFF_BASE_14\t\tis opfam=0x1B & OFF_BASE_14 & R1 & RB & SPCBASE & lse14 {\n\taddr:$(ADDRSIZE) = SPCBASE;\n local imm = sext(lse14);\n\tif (imm s>= 0x0) goto ;\n\taddr = addr + imm;\n\t \n\t*[ram]:4 addr = R1; \n\tRB = RB + imm;\n} \n\n# LDWX\n:LDW^indexedWordAccessCmplt^loadCC RX^SRRB,RT is opfam=0x03 & subop=2 & zero=0 & indexedWordAccessCmplt & loadCC & RX & RT & SRRB {\n\taddress:$(ADDRSIZE) = indexedWordAccessCmplt; \n RT = zext(*[ram]:4 address) ;\n }\n \n #LDHX\n:LDH^indexedHalfwordAccessCmplt^loadCC RX^SRRB,RT is opfam=0x03 & subop=1 & zero=0 & indexedHalfwordAccessCmplt & loadCC & RX & SRRB & RT {\n\taddress:$(ADDRSIZE) = indexedHalfwordAccessCmplt; \n RT = zext(*[ram]:2 address) ;\n}\n\n#LDBX\n:LDB^indexedByteAccessCmplt^loadCC RX^SRRB,RT is opfam=0x03 & subop=0 & zero=0 & indexedByteAccessCmplt & loadCC & RX & SRRB & RT {\n\taddress:$(ADDRSIZE) = indexedByteAccessCmplt; \n RT = zext(*[ram]:1 address) ;\n}\n\n# same as LDWX, except that it checks privilege levels\n:LDWAX^indexedWordAccessCmplt^loadCC RX(RB),RT \t\t\t\tis opfam=0x03 & subop=6 & zero=0 & s=0 & indexedWordAccessCmplt & loadCC & RX & SRRB & RB & RT {\n\taddress:$(ADDRSIZE) = indexedWordAccessCmplt; \n RT = zext(*[ram]:4 address) ;\n}\n\n:LDCWX^indexedDoublewordAccessCmplt^loadClearCC RX^SRRB,RT \t\tis opfam=0x03 & subop=7 & zero=0 & indexedDoublewordAccessCmplt & loadClearCC & RX & SRRB & RT {\n\taddress:$(ADDRSIZE) = indexedDoublewordAccessCmplt; \n RT = zext(*[ram]:4 address);\n *[ram]:4 address = 0:4; \n }\n\n# LDWS\n:LDW^shortDispCmplt^loadCC highlse5^SRRB,RT\t\t\tis opfam=0x03 & subop=2 & one=1 & shortDispCmplt & loadCC & highlse5 & SRRB & RT {\n\taddr:$(ADDRSIZE) = shortDispCmplt;\n RT = zext(*[ram]:4 addr) ;\n}\n\n# LDHS\n:LDH^shortDispCmplt^loadCC highlse5^SRRB,RT\t\t\tis opfam=0x03 & subop=1 & one=1 & shortDispCmplt & loadCC & highlse5 & SRRB & RT {\n\taddr:$(ADDRSIZE) = shortDispCmplt;\n RT = zext(*[ram]:2 addr) ;\n}\n\n# LDBS\n:LDB^shortDispCmplt^loadCC highlse5^SRRB,RT\t\t\tis opfam=0x03 & subop=0 & one=1 & shortDispCmplt & loadCC & highlse5 & SRRB & RT {\n\taddr:$(ADDRSIZE) = shortDispCmplt;\n RT = zext(*[ram]:1 addr) ;\n}\n\n#STWS\n:STW^storeShortDispCmplt^storeCC RR,lse5^SRRB\t\t\t\tis opfam=0x03 & subop=0xA & one=1 & storeShortDispCmplt & storeCC & lse5 & SRRB & RR {\n\taddr:$(ADDRSIZE) = storeShortDispCmplt;\n\t*[ram]:4 addr = RR:4; \n}\n\n#STHS\n:STH^storeShortDispCmplt^storeCC RR,lse5^SRRB\t\t\t\tis opfam=0x03 & subop=0x9 & one=1 & storeShortDispCmplt & storeCC & lse5 & SRRB & RR {\n\taddr:$(ADDRSIZE) = storeShortDispCmplt;\n\t*[ram]:2 addr = RR:2; \n}\n\n#STBS\n:STB^storeShortDispCmplt^storeCC RR,lse5^SRRB\t\t\t\tis opfam=0x03 & subop=0x8 & one=1 & storeShortDispCmplt & storeCC & lse5 & SRRB & RR {\n\taddr:$(ADDRSIZE) = storeShortDispCmplt;\n\t*[ram]:1 addr = RR:1; \n}\n\n:LDWAS^shortDispCmplt^loadCC highlse5(RB),RT\t\t\tis opfam=0x03 & subop=6 & one=1 & shortDispCmplt & loadCC & highlse5 & RB & RT {\n\taddr:$(ADDRSIZE) = shortDispCmplt;\n RT = zext(*[ram]:4 addr) ;\n}\n\n:LDCWS^shortDispCmplt^loadClearCC highlse5^SRRB,RT\t\tis opfam=0x03 & subop=7 & one=1 & shortDispCmplt & loadClearCC & highlse5 & SRRB & RT {\n\taddress:$(ADDRSIZE) = shortDispCmplt; \n RT = zext(*:4 address);\n *[ram]:4 address = 0:4; \n}\n\n:STWAS^shortDispCmplt^storeCC RR,lse5(RB)\t\t\t\tis opfam=0x03 & subop=0xE & one=1 & shortDispCmplt & storeCC & lse5 & RB & RR {\n\taddr:$(ADDRSIZE) = shortDispCmplt;\n\t*[ram] :4 addr = RR:4; \n}\n\n# This is the \"begin\" version for big endian. I am not doing the little endian version.\n:STBYS^storeBytesShortCmplt^storeCC RR,lse5^SRRB \t\tis opfam=0x03 & subop=0xC & one=1 & storeBytesShortCmplt & storeCC & lse5 & SRRB & RR & u=0 {\n\t# get the address, which is most likely not word aligned\n\taddr:$(ADDRSIZE) = storeBytesShortCmplt;\n\t# figure out how many bytes need to be written\n\tlocal numBytes = 4 - (addr & 0x3);\n\t# this is the address where we stop (one byte past the last address to which we write)\n\tlocal finalAddr = addr + numBytes;\n\t# copy the contents of RR\n\tdata:$(REGSIZE) = RR >> ((4 - numBytes) * 8);\n\t# use a for loop to write out the 1,2,3, or 4 bytes\n\t\n\tif (addr == finalAddr) goto ;\n\t*[ram]:1 addr = data:1;\n\tdata = data >> 8;\n\taddr = addr + 1;\n\tgoto ;\n\t\n}\n\n# This is the \"end\" version for big endian. I am not doing the little endian version.\n:STBYS^storeBytesShortCmplt^storeCC RR,lse5^SRRB \t\tis opfam=0x03 & subop=0xC & one=1 & storeBytesShortCmplt & storeCC & lse5 & SRRB & RR & u=1 {\n\t# get the address, which is most likely not word aligned\n\taddr:$(ADDRSIZE) = storeBytesShortCmplt;\n\t# figure out how many bytes need to be written\n\tlocal numBytes = (addr & 0x3);\n\t# now make a word aligned address\n\taddr = addr & 0x3;\n\t# this is the address where we stop (one byte past the last address to which we write)\n\tlocal finalAddr = addr + numBytes;\n\t# copy the contents of RR\n\tdata:$(REGSIZE) = RR >> ((4 - numBytes) * 8);\n\n\t# use a for loop to write out the 1,2,3, or 4 bytes\n\t\n\tif (addr == finalAddr) goto ;\n\t*[ram]:1 addr = data:1;\n\tdata = data >> 8;\n\taddr = addr + 1;\n\tgoto ;\n\t\n}\n\n# Note: LDO and LDIL do not access memory, they just load an address into a register\n# LDI is a pseudo-op that is commonly used to load immediate values into registers. The values may or may not be addresses.\n:LDO lse14(RB),R1dst\t\t\t\t\t\t\t\t\t\tis opfam=0x0D & lse14 & RB & R1dst {\n\tR1dst = RB + lse14;\n }\n\n# LDO is often used as a copy operator, so when the offset is zero, we display it as a copy\n:COPY RB,R1dst\t\t\t\t\t\t\t\t\t\tis opfam=0x0D & im14=0 & RB & R1dst {\n\tR1dst = RB;\n }\n \n:LDI lse14,R1dst\t\t\t\t\t\t\t\t\tis opfam=0x0D & b=0 & lse14 & R1dst {\n\tR1dst = lse14;\n}\n\n:LDIL lse21,R2\t\t\t\t\t\t\t\t\tis opfam=0x08 & R2 & lse21 {\n\tR2 = lse21;\n}\n\n# this instruction adds lse21 + R2 and puts the result into the hard coded r1 register\n# (not the register specified by bitfield reg1, the actual register r1)\n:ADDIL lse21, R2, r1\t\t\t\t\t\t\tis opfam=0x0A & R2 & lse21 & r1 {\n\tr1 = R2 + lse21;\n}\n\n################################################################################\n# Branch Instructions\n################################################################################\n\n################################################################################\n# unconditional immediate calls\n################################################################################\n# non-nullifying unconditional immediate call\n:B^\",L\"^nullifyForBranch branchTarget3W,R2dst\t\t\t\t\t\tis opfam=0x3A & c=0x0 & R2dst & nullifyForBranch & n=0 & branchTarget3W & $(COMMON) \n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 1; # unconditional imm call\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = inst_start+8;\n\tbranchExecuted = 1;\n}\n\n# nullifying unconditional immediate call\n# special case that doesn't need the deferral mechanism \n:B^\",L\"^nullifySymForBranch branchTarget3W,R2dst\t\t\t\t\t\tis opfam=0x3A & c=0x0 & R2dst & nullifySymForBranch & n=1 & branchTarget3W & $(COMMON) \n{\n\tR2dst = inst_start+8;\n\tcall branchTarget3W;\n}\n\n################################################################################\n# unconditional immediate branches\n# since PA-RISC doesn't have a straight branch without link, it uses branch and link into the R0 register.\n# By having a second op for it, we can use a goto and prevent analysis tools from thinking this is a legitimate subroutine call\n################################################################################\n# non-nullifying unconditional immediate branch (no link)\n:B^nullifyForBranch branchTarget3W\t\t\t\t\t\t\tis opfam=0x3A & c=0x0 & reg2=0 & nullifyForBranch & n=0 & branchTarget3W & $(COMMON) \n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 0; # unconditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t \n\t]\n{\n\tbranchExecuted = 1;\n}\n\n# nullifying unconditional immediate branch (no link)\n# This is a special case, as we just do the branch and don't use\n# our defered branching mechanism\n:B^nullifySymForBranch branchTarget3W\t\t\t\t\t\t\tis opfam=0x3A & c=0x0 & reg2=0 & nullifySymForBranch & n=1 & branchTarget3W & $(COMMON) \n{\n\tgoto branchTarget3W;\n}\n\n################################################################################\n# conditional immediate branches - comparison with registers\n################################################################################\n:CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W\t\tis opfam=0x20 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = RegCSCond;\n\tbranchExecuted = 1;\n}\n\n :CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W\t\tis opfam=0x20 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = RegCSCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W\t\tis opfam=0x22 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = ! RegCSCond;\n\tbranchExecuted = 1;\n}\n\n:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W\t\tis opfam=0x22 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = ! RegCSCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n################################################################################\n# conditional immediate branches -- comparison with immediates\n################################################################################\n:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W\tis opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = RegCSCondI;\n\tbranchExecuted = 1;\n}\n\n:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W\tis opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = RegCSCondI;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W\tis opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = !RegCSCondI;\n\tbranchExecuted = 1;\n}\n\n:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W\tis opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = !RegCSCondI;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n################################################################################\n# unconditional indirect calls & branches\n################################################################################\n# IP relative unconditional indirect call\n:BLR^nullifyForBranch RR,R2dst\t\t\t\t\t\t\t\t\tis opfam=0x3A & c=0x2 & R2dst & nullifyForBranch & RR & IPRelativeIndexedTarget & n=0 & $(COMMON)\n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 5; # unconditional indirect call\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = inst_start+8;\n\tbranchExecuted = 1;\n}\n\n# IP relative unconditional indirect call\n:BLR^nullifySymForBranch RR,R2dst\t\t\t\t\t\t\t\t\tis opfam=0x3A & c=0x2 & R2dst & nullifySymForBranch & RR & IPRelativeIndexedTarget & n=1 & $(COMMON)\n{\n\tR2dst = inst_start+8;\n\tcall [branchIndDest];\n}\n\n# vectored (offset register plus index register) unconditional indirect branch\n:BV^nullifyForBranch RX(RB)\t\t\t\t\t\t\t\t\tis opfam=0x3A & c=0x6 & RB & nullifyForBranch & RX & IndexedTarget & bit0=0 & n=0 & $(COMMON)\n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 4; # unconditional indirect branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchExecuted = 1;\n}\n\n# vectored (offset register plus index register) unconditional indirect branch\n:BV^nullifySymForBranch RX(RB)\t\t\t\t\t\t\t\tis opfam=0x3A & c=0x6 & RB & nullifySymForBranch & RX & IndexedTarget & bit0=0 & n=1 & $(COMMON)\n{\n\tgoto [branchIndDest];\n}\n\n# this is the idiom for return from subroutine\n# currently we pull it out so we don't print out the R0, but we could modify this to do a return...\n:BV^nullifyForBranch (RB)\t\t\t\t\t\t\t\t\tis opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=0 & $(COMMON)\n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 4; # unconditional indirect branch\n\t globalset(inst_next, branchType);\n\t branchIsReturn=1;\n\t globalset(inst_next, branchIsReturn);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchExecuted = 1;\n}\n\n# this is the idiom for return from subroutine\n# currently we pull it out so we don't print out the R0, but we could modify this to do a return...\n:BV^nullifyForBranch (RB)\t\t\t\t\t\t\t\t\tis opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=1 & $(COMMON)\n{\n\treturn [branchIndDest];\n}\n\n###########################\n\n#### MOVB\n\n:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W\t\t\tis opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = R1;\n\tnullifyCondResult = R1;\n\tbuild DepCond; # force the condition evaluation after the move\n\tbranchCond = DepCond;\n\tbranchExecuted = 1;\n}\n\n:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W\t\t\tis opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = R1;\n\tnullifyCondResult = R1;\n\tbuild DepCond; # force the condition evaluation after the move\n\tbranchCond = DepCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n###########################\n\n#### MOVIB\n\n:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W\t\tis opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = sext(im5:1);\n\tnullifyCondResult = sext(im5:1);\n\tbuild DepCond; # force the condition evaluation after the move\n\tbranchExecuted = 1;\n\tbranchCond = DepCond;\n}\n\n:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W\t\tis opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = sext(im5:1);\n\tnullifyCondResult = sext(im5:1);\n\tbuild DepCond; # force the condition evaluation after the move\n\tbranchCond = DepCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n###########################\n:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W\t\tis opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 & $(COMMON) \n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCond; # force the condition evaluation before the move\n\tbranchCond = RegAddCond;\n\tbranchExecuted = 1;\n\tR2dst = R1 + R2;\n}\n\n:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W\t\tis opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegAddCond & RegAddCondSym & n=1 & $(COMMON) \n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCond; # force the condition evaluation before the move\n\tbranchCond = RegAddCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n\n\tR2dst = R1 + R2;\n}\n\n###########################\n:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W\t\tis opfam=0x2A & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCond; # force the condition evaluation before the move\n\tbranchCond = !RegAddCond;\n\tbranchExecuted = 1;\n\tR2dst = R1 + R2;\n}\n\n:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W\t\tis opfam=0x2A & R1 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondSym & RegAddCond & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCond; # force the condition evaluation before the move\n\tbranchCond = !RegAddCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n\tR2dst = R1 + R2;\n}\n\n###########################\n:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W\tis opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCondI; # force the condition evaluation before the move\n\tbranchCond = RegAddCondI;\n\tbranchExecuted = 1;\n\tR2dst = R2 + sext(highlse5);\n}\n\n:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W\tis opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCondI; # force the condition evaluation before the move\n\tbranchCond = RegAddCondI;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n\tR2dst = R2 + sext(highlse5);\n}\n\n:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W\tis opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCondI; # force the condition evaluation before the move\n\tbranchCond = ! RegAddCondI;\n\tbranchExecuted = 1;\n\tR2dst = R2 + sext(highlse5);\n}\n\n:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W\tis opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 & $(COMMON)\n \t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbuild RegAddCondI; # force the condition evaluation before the move\n\tbranchCond = ! RegAddCondI;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n\tR2dst = R2 + sext(highlse5);\n}\n\t\n#######################################\n:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W\t\t\t\tis opfam=0x30 & branchTarget2W & nullifyForBranch & R1 & BVBCond & SEDCondSym & SAR & n=0 & $(COMMON)\n\t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = BVBCond;\n\tbranchExecuted = 1;\n}\t\t\t\t\t\t\n\n:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W\t\t\t\tis opfam=0x30 & branchTarget2W & nullifyForBranch & displacement2W & R1 & BVBCond & SEDCondSym & SAR & n=1 & $(COMMON) \n\t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = BVBCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n#######################################\n:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W\t\t\tis opfam=0x31 & branchTarget2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=0 & bboffset & $(COMMON)\n\t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = BBCond;\n\tbranchExecuted = 1;\n}\t\t\t\t\t\t\n\n:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W\t\t\tis opfam=0x31 & branchTarget2W & displacement2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=1 & bboffset & $(COMMON)\n\t[ branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 2; # conditional imm branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tbranchCond = BBCond;\n\tbranchExecuted = 1;\n\tnullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );\n}\n\n#######################################\n# These instructions change the privilege level or the space register\ndefine pcodeop changePrivLevel;\ndefine pcodeop changeSpace;\ndefine pcodeop getCurrentSpace;\n\n:BE^nullifyForBranch externalTarget\t\tis opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=0 & $(COMMON)\n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 4; # unconditional indirect branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tiasq_front = SR3bit; # set the space ID to the new space ID\n\t# with the current deferral system, this will mean the sr is wrong during the delay slot\n\tbranchExecuted = 1;\n}\n\n:BE^nullifyForBranch externalTarget\t\tis opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=1 & $(COMMON)\n{\n\tiasq_front = SR3bit; # set the space ID to the new space ID\n\tgoto [externalTarget];\n}\n\n:BE^\",L\"^nullifyForBranch externalTarget,SR0,R31\tis opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=0 & $(COMMON)\n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 5; # unconditional indirect call\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tr31 = inst_next+4; # store the link/return address\n\tsr0 = iasq_front; # store the link/return space ID \n\tiasq_front = SR3bit; # set the space ID to the new space ID\n\t# with the current deferral system, this will mean the sr is wrong during the delay slot\n\tbranchExecuted = 1;\n}\n\n:BE^\",L\"^nullifyForBranch externalTarget,SR0,R31\tis opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=1 & $(COMMON)\n{\n\tr31 = inst_next+4; # store the link/return address\n\tsr0 = iasq_front; # store the link/return space ID \n\tiasq_front = SR3bit; # set the space ID to the new space ID\n\tcall [externalTarget];\n}\n\n:B^\",GATE\"^nullifyForBranch branchTarget3W,R2dst\t\t\t\t\tis opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=0 & $(COMMON) \n\t[\n\t branchEnable = 1;\n\t globalset(inst_next, branchEnable);\n\t branchType = 0; # unconditional immediate branch\n\t globalset(inst_next, branchType);\n\t branchCouldBeNullified = nullifyEnable;\n\t globalset(inst_next, branchCouldBeNullified);\n\t]\n{\n\tR2dst = changePrivLevel();\n\tbranchExecuted = 1;\n}\n\n:B^\",GATE\"^nullifyForBranch branchTarget3W,R2dst\t\t\t\t\tis opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=1 & $(COMMON)\n{\n\tR2dst = changePrivLevel();\n\tgoto [branchTarget3W];\n}\n\n\n#######################################\n#######################################\n# General Arithmetic/Logic Instructions\n#######################################\n#######################################\ndefine pcodeop trap;\n\n:ADD^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x18 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tpswCB = carry(R1,R2);\n\tRT = R1 + R2;\n\tbuild AddCondNullify;\n}\n\n# this version intentionally does not set the carry bits\n:ADD^\",L\"^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x28 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tRT = R1 + R2;\n\tbuild AddCondNullify;\n}\n\n:ADDO^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x38 & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify {\n\tif (scarry(R1,R2)) goto ;\n\tpswCB = carry(R1,R2);\n\tRT = R1 + R2;\n\tgoto ;\n\t\n\ttrap();\n\t\n\tbuild AddCondNullify;\n}\n\n:ADD^\",C\"^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x1C & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify {\n\tlocal partialSum = R2 + zext(pswCB);\n\tpswCB = carry(partialSum, R1);\n\tRT = partialSum + R1;\n\tbuild AddCondNullify;\n}\n\n# TODO This may need some work\n:ADD^\",CO\"^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x3C & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify {\n\tlocal partialSum = R2 + zext(pswCB);\n\tpartialCarry:1 = carry(R2, zext(pswCB));\n\tpartialOverflow:1 = scarry(R2, zext(pswCB));\n\ttakeTrap:1 = partialOverflow == 0x1:1; \n\tif (takeTrap) goto ;\n\tRT = partialSum + R1;\n\tfinalCarry:1 = carry(partialSum, R1);\n\tfinalOverflow:1 = scarry(partialSum, R1);\n\ttakeTrap = finalOverflow == 0x1:1;\n\tif (takeTrap) goto ;\n\tgoto ;\n\t\n\ttrap();\n\t\n\tpswCB = partialCarry ^ finalCarry;\n\tbuild AddCondNullify;\n}\n\n:SH1ADD^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x19 & m=0 & R1 & R2 & RT & AddCond & AddCondSym & AddCondNullify {\n\tlocal shiftedR1 = R1 << 1;\n\tpswCB = carry(shiftedR1,R2);\n\tRT = shiftedR1 + R2;\n\tbuild AddCondNullify;\n}\n\n:SH1ADDL^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x29 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tlocal shiftedR1 = R1 << 1;\n\tRT = shiftedR1 + R2;\n\tbuild AddCondNullify;\n}\n\n:SH1ADDO^SEDCondSym R1,R2,RT\tis opfam=0x02 & op=0x39 & m=0 & R1 & R2 & RT & AddCondNullify & SEDCondSym {\n\tlocal shiftedR1 = R1 << 1;\n\tif (scarry(shiftedR1, R2)) goto ;\n\tpswCB = carry(shiftedR1,R2);\n\tRT = shiftedR1 + R2;\n\tgoto ;\n\t\n\ttrap();\n\t\n\tbuild AddCondNullify;\n}\n\n:SH2ADD^SEDCondSym R1,R2,RT\tis opfam=0x02 & op=0x1A & m=0 & R1 & R2 & RT & AddCondNullify & SEDCondSym {\n\tlocal shiftedR1 = R1 << 2;\n\tpswCB = carry(shiftedR1,R2);\n\tRT = shiftedR1 + R2;\n\tbuild AddCondNullify;\n}\n\n:SH2ADDL^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x2A & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tlocal shiftedR1 = R1 << 2;\n\tRT = shiftedR1 + R2;\n\tbuild AddCondNullify;\n}\n\n:SH2ADDO^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x3A & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tlocal shiftedR1 = R1 << 2;\n\tif (scarry(shiftedR1, R2)) goto ;\n\tpswCB = carry(shiftedR1,R2);\n\tRT = shiftedR1 + R2;\n\tgoto ;\n\t\n\ttrap();\n\t\n\tbuild AddCondNullify;\n}\n\n:SH3ADD^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x1B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tlocal shiftedR1 = R1 << 3;\n\tpswCB = carry(shiftedR1,R2);\n\tRT = shiftedR1 + R2;\n\tbuild AddCondNullify;\n}\n\n:SH3ADDL^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x2B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tlocal shiftedR1 = R1 << 3;\n\tRT = shiftedR1 + R2;\n\tbuild AddCondNullify;\n}\n\n:SH3ADDO^AddCondSym R1,R2,RT\tis opfam=0x02 & op=0x3B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {\n\tlocal shiftedR1 = R1 << 3;\n\tif (scarry(shiftedR1, R2)) goto ;\n\tpswCB = carry(shiftedR1,R2);\n\tRT = shiftedR1 + R2;\n\tgoto ;\n\t\n\ttrap();\n\t\n\tbuild AddCondNullify;\n}\n\n:SUB^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x10 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify {\n\tpswCB = ! (R1 < R2);\n\tRT = R1 - R2;\n\tbuild CSCondNullify;\n}\n\n:SUB\",O\"^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x30 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify {\n\tif (sborrow(R1,R2)) goto ;\n\tpswCB = ! (R1 < R2);\n\tRT = R1 - R2;\n\tbuild CSCondNullify;\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n:SUB\",B\"^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x14 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify {\n\tright:$(REGSIZE) = ~R2 + zext(pswCB);\n\tpswCB = ! (R1 < right); #! carry(R1, right);\n\tRT = R1 + right;\n\tbuild CSCondNullify;\n}\n\n:SUB\",BO\"^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x34 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify {\n\tright:$(REGSIZE) = ~R2 + zext(pswCB);\n\tif (sborrow(R1,right)) goto ;\n\tpswCB = ! (R1 < right);\n\tRT = R1 + right;\n\tbuild CSCondNullify;\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n# subtract and trap on condition\n# this instruction does not have a nullify form\n:SUB\",T\"^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x13 & m=0 & R1 & R2 & RT & CSCondSym & CSCond {\n\tpswCB = ! (R1 < R2);\n\tRT = R1 - R2;\n\tbuild CSCond;\n\tif (CSCond) goto ;\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n:SUB\",TO\"^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x33 & m=0 & R1 & R2 & RT & CSCondSym & CSCond {\n\tif (sborrow(R1,R2)) goto ;\n\tpswCB = ! (R1;\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n# R1 is partial remainder, R2 is denominator, RT is updated partial remainder\n:DS^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x11 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify {\n\tlocal origR2 = R2;\n\tleft:$(REGSIZE) = (R1 << 1) | zext(pswCB);\n\tif (pswV) goto ;\n\t\tright:$(REGSIZE) = R2;\n\t\tgoto ;\n\t\n\t\tright = ~R2 + 1;\n\t\t\n\n\tRT = left + right;\n\n\tpswCB = carry(left,right);\n\n# handle pswV -- I'm using R2 here, the book says R2, but non-restoring algorithms usually use R1, so\n# this could be the error.\n\tshiftBit:1 = ((origR2 >> 31) & 0x1) == 1;\n\tpswV = pswCB ^ shiftBit;\n\t\t\n# handle nullification -- TODO This condition is special and the stock CSCondNullify won't work -- broken -- see page 5-103\n\tbuild CSCondNullify;\n}\n\n:CMPCLR^CSCondSym R1,R2,RT\tis opfam=0x02 & op=0x22 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify\n{\n\tbuild CSCondNullify; # must do this before setting register\n\tRT = 0;\n}\n\n# COPY is a pseudo-op using OR to move values between registers\n:COPY R1,RT\t\t\t\tis opfam=0x02 & op=0x09 & m=0 & R1 & reg2=0 & RT & c=0 & fv=0 {\n\tRT = R1;\n }\n \n# nop is a pseudo-op for OR R0,R0, which is one way to make a nop\n:NOP\t\t\t\t\tis opfam=0x02 & op=0x09 & m=0 & reg1=0 & reg2=0 & t=0 & c=0 & fv=0 { } # intentionally left blank\n\n:OR^LogicCondSym R1,R2,RT\tis opfam=0x02 & op=0x09 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify {\n\tRT = R1 | R2;\n\tbuild LogicCondNullify;\n}\n\n:XOR^LogicCondSym R1,R2,RT\tis opfam=0x02 & op=0x0A & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify {\n\tRT = R1 ^ R2;\n\tbuild LogicCondNullify;\n}\n\n:AND^LogicCondSym R1,R2,RT\tis opfam=0x02 & op=0x08 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify {\n\tRT = R1 & R2;\n\tbuild LogicCondNullify;\n}\n\n:ANDCM^LogicCondSym R1,R2,RT\tis opfam=0x02 & op=0x00 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify {\n\tRT = R1 & ~R2;\n\tbuild LogicCondNullify;\n}\n\n:UXOR^UnitCondSym R1,R2,RT\t\tis opfam=0x02 & op=0x0E & m=0 & R1 & R2 & RT & UnitCondSym & UnitCondNullify {\n\tRT = R1 ^ R2;\n\tbuild UnitCondNullify;\n}\n\n:UADDCM^UnitCondSym R1,R2,RT\tis opfam=0x02 & op=0x26 & m=0 & R1 & R2 & RT & UnitCondSym & UnitCondNullify {\n\tRT = R1 + ~R2;\n\tbuild UnitCondNullify;\n\t\n}\n\n:UADDCMT^UnitCondSym R1,R2,RT\tis opfam=0x02 & op=0x27 & m=0 & R1 & R2 & RT & UnitCond & UnitCondSym {\n\tif (UnitCond) goto ;\n\tRT = R1 + ~R2;\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n:ADDI^AddCondSym lse11,R2,R1dst\tis opfam=0x2D & bit11=0 & lse11 & R2 & R1dst & AddCondSym & AddCondI11Nullify {\n\ttmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2\n\tR1dst = R2 + lse11;\n\tpswCB = carry(tmp,lse11);\n\tbuild AddCondI11Nullify;\n}\n\n# PA1.1 this is ADDIO, PA2.0 is ADDI,TSV (trap on signed overflow)\n:ADDI^\",TSV\"^AddCondSym lse11,R2,R1dst\tis opfam=0x2D & bit11=1 & lse11 & R2 & R1dst & AddCondSym & AddCondI11Nullify {\n tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2\n\tif (scarry(R2, lse11) == 1:1) goto ;\n\tR1dst = R2 + lse11;\n\tpswCB = carry(tmp,sext(lse11));\n\tgoto ;\n\t\n\ttrap();\n\t\n\tbuild AddCondI11Nullify;\n}\n\n# PA11 this is ADDIT, PA2.0 this is ADDI,TC\n:ADDI^\",TC\"^AddCondSym lse11,R2,R1dst\tis opfam=0x2C & bit11=0 & lse11 & R2 & R1dst & AddCondSym & AddCondI11 {\n tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2\n\tR1dst = R2 + lse11;\n\tbuild AddCondI11;\n\tif (AddCondI11) goto ;\n\tpswCB = carry(tmp,lse11);\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n# PA11 this is ADDITO, PA2.0 this is ADDI,TC,TSV\n:ADDI^\",TC,TSV\"^AddCondSym lse11,R2,R1dst\tis opfam=0x2C & bit11=1 & lse11 & R2 & R1dst & AddCondSym & AddCondI11 {\n tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2\n\tR1dst = R2 + lse11;\n\tbuild AddCondI11;\n\tif (AddCondI11) goto ;\n\tif (scarry(tmp, lse11) == 1:1) goto ;\n\tpswCB = carry(tmp,lse11);\n\tgoto ;\n\t\n\ttrap();\n\t\n}\n\n:SUBI^CSCondSym lse11,R2,R1dst\t\tis opfam=0x25 & bit11=0 & lse11 & R2 & R1dst & CSCondI11Nullify & CSCondSym {\n tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2\n\tR1dst = lse11 - R2;\n\tpswCB = !(lse11 < tmp);\n\tbuild CSCondI11Nullify;\n}\n\n:SUBI^\",TSV\"^CSCondSym lse11,R2,R1dst\tis opfam=0x25 & bit11=1 & lse11 & R2 & R1dst & CSCondI11 & CSCondSym & CSCondI11Nullify {\n tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2\n\tif (sborrow(lse11, R2) == 1:1) goto ;\n\tR1dst = lse11 - R2;\n\tpswCB = !(lse11 < tmp);\n\tgoto ;\n\t\n\ttrap();\n\t\n\tbuild CSCondI11Nullify;\n}\n\n:CMPICLR^CSCondSym lse11,R2,R1dst\tis opfam=0x24 & bit11=0 & lse11 & R2 & R1dst & CSCondI11Nullify & CSCondSym\n{\n\tR1dst = 0;\n}\n\n:SHRPW^SEDCondSym R1,R2,SAR,RT\t\tis opfam=0x34 & subop1012=0 & bits59=0 & R1 & R2 & RT & ShiftCondNullify & SEDCondSym & SAR {\n\tleft:8 = zext( (R1 & 0x7FFFFFFF) ) << 32;\n\tconcat:8 = left | zext(R2);\n\tconcat = concat >> SAR;\n\tnullifyCondResult=concat:$(REGSIZE);\n\tRT = concat:4;\n\t\n\tbuild ShiftCondNullify; \n}\n\n# previously this was shd, now is shrpw form 14\n:SHRPW^SEDCondSym R1,R2,shiftC,RT\tis opfam=0x34 & R2 & R1 & subop1012=2 & shiftC & RT & SEDCondSym & ShiftCondNullify {\n\tleft:8 = zext( (R1 & 0x7FFFFFFF) ) << 32;\n\tconcat:8 = left | zext(R2);\n\tconcat = concat >> shiftC;\n\tnullifyCondResult=concat:$(REGSIZE);\n\tRT = concat:4;\n\t\n\tbuild ShiftCondNullify; \n}\n\n# extract unsigned using SAR\n:EXTRW\",U\"^SEDCondSym R2,SAR,shiftCLen,R1dst\tis opfam=0x34 & bits59=0 & subop1012=4 & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & SAR {\n\tlocal value = R2 >> (31-SAR);\n\tmask:4 = 0xffffffff >> (32 - shiftCLen);\n\tnullifyCondResult = value & mask;\n\tR1dst = nullifyCondResult;\n\t\n\tbuild ExtrCondNullify; \n}\n\n# extract signed using SAR\n:EXTRW\",S\"^SEDCondSym R2,SAR,shiftCLen,R1dst\tis opfam=0x34 & bits59=0 & subop1012=5 & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & SAR {\n\tlocal value = R2 s>> (31-SAR);\n\tvalue = value << (32 - shiftCLen);\n\tvalue = value s>> (32 - shiftCLen);\n\tnullifyCondResult = value;\n\tR1dst = value;\n\tbuild ExtrCondNullify;\n}\n\n# extract unsigned using immediate\n:EXTRW^\",U\"^SEDCondSym R2,cp,shiftCLen,R1dst\tis opfam=0x34 & subop1012=6 & cp & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & shiftC {\n\tlocal value = R2 >> shiftC;\n\tmask:4 = 0xffffffff >> (32-shiftCLen);\n\tnullifyCondResult = value & mask;\n\tR1dst = nullifyCondResult;\n\n\tbuild ExtrCondNullify;\n}\n\n# extract signed using immediate\n:EXTRW^\",S\"^SEDCondSym R2,cp,shiftCLen,R1dst\tis opfam=0x34 & subop1012=7 & cp & R2 & shiftC & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify {\n\tlocal value = R2 s>> shiftC;\n\tvalue = value << (32 - shiftCLen);\n\tvalue = value s>> (32 - shiftCLen);\n\tnullifyCondResult = value;\n\tR1dst = value;\n\tbuild ExtrCondNullify;\n}\n\n# non-zeroing SAR version (VDEP)\n:DEPW^SEDCondSym R1,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=1 & R1 & R2 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & SAR {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n local value = R1 & mask;\n value = value << (31-SAR);\n mask = mask << (31-SAR);\n local result = R2 & ~mask;\n result = result | value; \n R2dst = result;\n nullifyCondResult = result;\n \n build DepCondNullify;\n}\n\n# non-zeroing constant version (DEP)\n:DEPW^SEDCondSym R1,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=3 & shiftC & shiftCLen & R1 & R2 & R2dst & DepCondNullify & SEDCondSym & cp {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n local value = R1 & mask;\n value = value << cp;\n mask = mask << cp;\n local result = R2 & ~mask;\n result = result | value;\n R2dst = result;\n nullifyCondResult = result;\n build DepCondNullify;\n}\n\n# non-zeroing immediate SAR version (VDEPI)\n:DEPWI^SEDCondSym highlse5,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=5 & shiftCLen & highlse5 & R2 & R2dst & DepCondNullify & SEDCondSym & SAR {\n mask:4 = 0xffffffff >> (32 - shiftCLen);\n depbits:4 = sext(highlse5);\n depbits = sext(depbits); \n local value = depbits & mask;\n value = value << (31-SAR);\n mask = mask << (31-SAR);\n local result = R2 & ~mask;\n result = result | value;\n R2dst = result;\n nullifyCondResult = result;\n build DepCondNullify;\n}\n\n# non-zeroing immediate constant version (DEPI)\n:DEPWI^SEDCondSym highlse5,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=7 & shiftC & highlse5 & R2 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & cp {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n depbits:4 = sext(highlse5);\n local value = depbits & mask;\n value = value << cp;\n mask = mask << cp;\n local result = R2 & ~mask;\n result = result | value;\n R2dst = result;\n nullifyCondResult = result;\n build DepCondNullify;\n}\n\n# DEPW,Z SAR version (ZVDEP)\n:DEPW\",Z\"^SEDCondSym R1,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=0 & R1 & shiftCLen & R2 & R2dst & DepCondNullify & SEDCondSym & SAR {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n local value = R1 & mask;\n value = value << (31-SAR);\n R2dst = value;\n nullifyCondResult = value;\n build DepCondNullify;\n}\n\n# DEPW,Z constant version (ZDEP)\n:DEPW^\",Z\"^SEDCondSym R1,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=2 & shiftC & R2 & R2dst & shiftCLen & R1 & DepCondNullify & SEDCondSym & cp {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n local value = R1 & mask;\n value = value << cp;\n R2dst = value;\n nullifyCondResult = value;\n build DepCondNullify;\n}\n\n# DEPWI,Z SAR version (ZVDEPI)\n:DEPWI\",Z\"^SEDCondSym highlse5,SAR,shiftCLen,R2dst is opfam=0x35 & SAR & bits59=0 & subop1012=4 & shiftCLen & highlse5 & R2dst & DepCondNullify & SEDCondSym {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n depbits:4 = sext(highlse5);\n local value = depbits & mask;\n value = value << (31-SAR);\n R2dst = value;\n nullifyCondResult = value;\n build DepCondNullify;\n}\n\n# DEPWI,Z constant version (ZDEPI)\n:DEPWI\",Z\"^SEDCondSym highlse5,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=6 & shiftC & highlse5 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & cp {\n mask:4 = 0xffffffff >> (32-shiftCLen);\n depbits:4 = sext(highlse5);\n local value = depbits & mask;\n value = value << cp;\n nullifyCondResult = value;\n R2dst = value;\n\n build DepCondNullify;\n}\n\n\n# BCD instructions\n:DCOR^UnitCondSym R2,RT\t\tis opfam=0x02 & op=0x2E & R2 & reg1=0x0 & RT & UnitCond & UnitCondSym { } # TODO\n:IDCOR^UnitCondSym R2,RT\t\tis opfam=0x02 & op=0x2F & R2 & reg1=0x0 & RT & UnitCond & UnitCondSym { } # TODO\n\n#################################################\n# System Instructions\n#################################################\ndefine pcodeop break;\n:BREAK im5,im13\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x00 & im5 & im13 { break(); }\n\n:RFI\t\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x60 & im5=0x0 {\n\tiaoq_back = cr18;\n\tiaoq_front = cr18;\n\tiasq_back = cr17;\n\tiasq_front = cr17; \n\tupperBits:8 = zext(iasq_front);\n\tlowerBits:8 = zext(iaoq_front);\n\tlocal returnAddr = (upperBits << 32) | lowerBits;\n\tgoto [returnAddr];\n }\n\n:RFI^\",R\"\t\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x65 & im5=0x0 {\n\tr1 = shr0;\n\tr8 = shr1;\n\tr9 = shr2;\n\tr16 = shr3;\n\tr17 = shr4;\n\tr24 = shr5;\n\tr25 = shr6;\n\t# psw = ipsw;\n\n\tiaoq_back = cr18;\n\tiaoq_front = cr18;\n\tiasq_back = cr17;\n\tiasq_front = cr17;\n\tupperBits:8 = zext(iasq_front);\n\tlowerBits:8 = zext(iaoq_front); \n\treturnAddr:8 = (upperBits << 32) | lowerBits;\n\tgoto [returnAddr];\n}\n\n:SSM highIm10,RT\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x6B & c=0x0 & highIm10 & RT {\n\twidePswG:4 = zext(pswG);\n\twidePswF:4 = zext(pswG);\n\twidePswR:4 = zext(pswG);\n\twidePswP:4 = zext(pswG);\n\twidePswD:4 = zext(pswG);\n\twidePswI:4 = zext(pswG);\n\tRT = (widePswG << 31) | (widePswF << 30) | (widePswR << 29) | (widePswP << 27) | (widePswD << 26) | (widePswI << 25);\n\tpswG = pswG || (highIm10 & 0x40);\n\tpswF = pswF || (highIm10 & 0x20);\n\tpswR = pswR || (highIm10 & 0x10);\n\tpswP = pswP || (highIm10 & 0x4); \n\tpswD = pswD || (highIm10 & 0x2); \n\tpswI = pswI || (highIm10 & 0x1); \n}\n\n:RSM highIm10,RT\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x73 & c=0x0 & highIm10 & RT {\n\twidePswG:4 = zext(pswG);\n\twidePswF:4 = zext(pswG);\n\twidePswR:4 = zext(pswG);\n\twidePswP:4 = zext(pswG);\n\twidePswD:4 = zext(pswG);\n\twidePswI:4 = zext(pswG);\n\tRT = (widePswG << 31) | (widePswF << 30) | (widePswR << 29) | (widePswP << 27) | (widePswD << 26) | (widePswI << 25);\n\tpswG = pswG && ((highIm10 & 0x40:1) == 0);\n\tpswF = pswF && ((highIm10 & 0x20:1) == 0);\n\tpswR = pswR && ((highIm10 & 0x10:1) == 0);\n\tpswP = pswP && ((highIm10 & 0x4:1) == 0); \n\tpswD = pswD && ((highIm10 & 0x2:1) == 0); \n\tpswI = pswI && ((highIm10 & 0x1:1) == 0); \n }\n\n:MTSM R1\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0xC3 & c=0x0 & im5=0 & R1 {\n\tpswG = ((R1 & 0x00000040:4) != 0);\n\tpswF = (R1 & 0x00000020:4) != 0;\n\tpswR = (R1 & 0x00000010:4) != 0;\n\tpswQ = (R1 & 0x00000008:4) != 0;\n\tpswP = (R1 & 0x00000004:4) != 0;\n\tpswD = (R1 & 0x00000002:4) != 0;\n\tpswI = (R1 & 0x00000001:4) != 0;\n}\n\n:LDSID SRRB,RT\t\t\t\t\t\tis opfam=0x0 & sysop=0x85 & u=0 & RT & SRRB & SR & SRVAL {\n\t\t\t\t\t\t\t\t\t\t\tRT = SRVAL;\n}\n\n:MTSP R1,SR3bit\t\t\t\t\t\t\tis opfam=0x0 & sysop=0xC1 & im5=0 & R1 & SR3bit {\n\tSR3bit = R1;\n }\n\n:MTCTL R1,crname2\t\t\t\t\t\tis opfam=0x0 & sysop=0xC2 & im5=0 & R1 & crname2 & cr {\n\tcr = R1;\n }\n\n:MTSAR R1\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0xC2 & im5=0 & R1 & crname2 & cr=11 {\n\tsar = (R1 & 0x1F);\n }\n\n:MFSP SR3bit,RT\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x25 & reg1=0x0 & RT & SR3bit {\n\tRT = SR3bit;\n}\n\n:MFCTL crname2,RT\t\t\t\t\t\tis opfam=0x0 & sysop=0x45 & RT & crname2 & reg1=0 & cr {\n\tRT = cr;\n}\n\n# this instruction is PA-RISC 2.0 only, but here to avoid disassembler comparison issues\n:MFIA RT\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0xA5 & RT & reg1=0 {\n\tRT = iaoq_front;\n}\n\ndefine pcodeop sync;\n:SYNC\t\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x20 & im5=0 & c=0 & bit20=0 { sync(); } # sync cache\n:SYNCDMA\t\t\t\t\t\t\t\tis opfam=0x0 & sysop=0x20 & im5=0 & c=0 & bit20=1 { sync(); } # sync DMA\ndefine pcodeop probe;\n:PROBER SRRB,R1,RT\t\t\t\t\tis opfam=0x1 & sysopshifted=0x46 & m=0 & SRRB & R1 & RT & SPCBASE { RT = probe(R1, SPCBASE); } # probe read\n:PROBERI SRRB,highIm5,RT\t\t\t\tis opfam=0x1 & sysopshifted=0xC6 & m=0 & SRRB & highIm5 & RT & SPCBASE { RT = probe(highIm5:1, SPCBASE); } # probe read imm\n:PROBEW SRRB,R1,RT\t\t\t\t\tis opfam=0x1 & sysopshifted=0x47 & m=0 & SRRB & R1 & RT & SPCBASE { RT = probe(R1, SPCBASE); } # probe write\n:PROBEWI SRRB,highIm5,RT\t\t\t\tis opfam=0x1 & sysopshifted=0xC7 & m=0 & SRRB & highIm5 & RT & SPCBASE { RT = probe(highIm5:1, SPCBASE); } # probe write imm\ndefine pcodeop physicalAddress;\n:LPA^sysCmplt RX^SRRB,RT \t\t\t\tis opfam=0x1 & sysopshifted=0x4D & sysCmplt & RX & SRRB & RT & SPCBASE { RT = physicalAddress(SPCBASE); } # virt to phy addr translation\ndefine pcodeop coherenceIndex;\n:LCI RX^SRRB,RT\t\t\t\t\t\tis opfam=0x1 & sysopshifted=0x4C & m=0 & RX & SRRB & RT & SPCBASE { RT = coherenceIndex(SPCBASE); } # load coherence index\ndefine pcodeop purgeTLB;\n:PDTLB^sysCmplt RX^SRRB3bit\t\t\t\tis opfam=0x1 & sysopshifted=0x48 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); }\n:PDTLB^sysCmplt RX^SRRB3bit\t\t\t\tis opfam=0x1 & sysopshifted=0x48 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); }\n\n:PITLB^sysCmplt RX^SRRB3bit\t\t\t\tis opfam=0x1 & sysopshifted=0x8 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); }\n:PITLB^sysCmplt RX^SRRB3bit\t\t\t\tis opfam=0x1 & sysopshifted=0x8 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); }\n\n:PDTLBE^sysCmplt RX^SRRB3bit\t\t\tis opfam=0x1 & sysopshifted=0x49 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); }\n:PDTLBE^sysCmplt RX^SRRB3bit\t\t\tis opfam=0x1 & sysopshifted=0x49 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); }\n\n:PITLBE^sysCmplt RX^SRRB3bit\t\t\tis opfam=0x1 & sysopshifted=0x9 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); }\n:PITLBE^sysCmplt RX^SRRB3bit\t\t\tis opfam=0x1 & sysopshifted=0x9 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); }\n\ndefine pcodeop insertTLBEntry;\n:IDTLBA R1,SRRB\t\t\t\t\t\t\tis opfam=0x1 & sysopshifted=0x41 & m=0 & SRRB & R1 & SPCBASE & im5=0 { insertTLBEntry(SPCBASE, R1); }\n:IITLBA R1,(SR3bit,RB)\t\t\t\t\tis opfam=0x1 & sysopshiftedshort=0x01 & m=0 & SR3bit & RB & R1 & im5=0 { insertTLBEntry(SR3bit, RB, R1); }\n:IDTLBP R1,SRRB\t\t\t\t\t\t\tis opfam=0x1 & sysopshifted=0x40 & m=0 & SRRB & R1 & SPCBASE & im5=0 { insertTLBEntry(SPCBASE, R1); }\n:IITLBP R1,(SR3bit,RB)\t\t\t\t\tis opfam=0x1 & sysopshiftedshort=0x00 & m=0 & im5=0 & SR3bit & RB & R1 { insertTLBEntry(SR3bit, RB, R1); }\n:IITLBT R1, R2\t\t\t\t\t\t\tis opfam=0x1 & sysopshiftedshort=0x20 & m=0 & im5=0 & fpsub=0 & R2 & R1 { insertTLBEntry(R1, R2); }\n\ndefine pcodeop purgeCache;\n:PDC^indexedWordAccessCmplt RX^SRRB\t\t\tis opfam=0x1 & sysopshifted=0x4E & indexedWordAccessCmplt & RX & SRRB & SPCBASE & im5=0 & m=0 { purgeCache(SPCBASE, RX); }\n:PDC^indexedWordAccessCmplt RX^SRRB\t\t\tis opfam=0x1 & sysopshifted=0x4E & indexedWordAccessCmplt & RX & SRRB & SPCBASE & RB & im5=0 & m=1 { purgeCache(SPCBASE, RX); RB = RB + RX; }\n\n:FDC^indexedWordAccessCmplt RX^SRRB\t\t\tis opfam=0x1 & sysopshifted=0x4A & indexedWordAccessCmplt & RX & SRRB & SPCBASE & m=0 { purgeCache(SPCBASE, RX); }\n:FDC^indexedWordAccessCmplt RX^SRRB\t\t\tis opfam=0x1 & sysopshifted=0x4A & indexedWordAccessCmplt & RX & SRRB & SPCBASE & RB & m=1 { purgeCache(SPCBASE, RX); RB = RB + RX; }\n\n:FIC^indexedWordAccessCmplt RX(SR3bit,RB)\t\tis opfam=0x1 & sysopshiftedshort=0x0A & indexedWordAccessCmplt & RX & SR3bit & RB & m=0 { purgeCache(SR3bit, RB, RX); }\n:FIC^indexedWordAccessCmplt RX(SR3bit,RB)\t\tis opfam=0x1 & sysopshiftedshort=0x0A & indexedWordAccessCmplt & RX & SR3bit & RB & m=1 { purgeCache(SR3bit, RB, RX); RB = RB + RX;}\n\n:FDCE^indexedWordAccessCmplt RX^SRRB\t\t\tis opfam=0x1 & sysopshifted=0x4B & indexedWordAccessCmplt & RX & SRRB & SPCBASE & m=0 { purgeCache(SPCBASE, RX); }\n:FDCE^indexedWordAccessCmplt RX^SRRB\t\t\tis opfam=0x1 & sysopshifted=0x4B & indexedWordAccessCmplt & RX & SRRB & SPCBASE & RB & m=1 { purgeCache(SPCBASE, RX); RB = RB + RX; }\n\n:FICE^indexedWordAccessCmplt RX(SR3bit,RB) \tis opfam=0x1 & sysopshiftedshort=0x0B & indexedWordAccessCmplt & RX & SR3bit & RB & m=0 { purgeCache(SR3bit, RB, RX); }\n:FICE^indexedWordAccessCmplt RX(SR3bit,RB) \tis opfam=0x1 & sysopshiftedshort=0x0B & indexedWordAccessCmplt & RX & SR3bit & RB & m=1 { purgeCache(SR3bit, RB, RX); RB = RB + RX; }\n\ndefine pcodeop diag;\n:DIAG im26\t\t\t\t\t\t\t\tis opfam=0x05 & im26 { diag(im26:4); }\n\n#################################################\n# Coprocessor and Special Function Instructions\n#################################################\n:SPOP0,SFU^nullifyForSpecial sop\t\t\t\t\tis opfam=0x04 & specop=0 & SFU & nullifyForSpecial & im5 & im15 [ sop=(im15 << 5) | im5; ] unimpl\n:SPOP1,SFU^nullifyForSpecial sop\t\t\t\t\tis opfam=0x04 & specop=1 & SFU & nullifyForSpecial & im5 & sopim10 [ sop=(sopim10 << 5) | im5; ] unimpl\n:SPOP2,SFU^nullifyForSpecial sop R2\t\t\t\t\tis opfam=0x04 & specop=2 & SFU & nullifyForSpecial & R2 & im5 & sopim5 [ sop=(sopim5 << 5) | im5; ] unimpl\n:SPOP3,SFU^nullifyForSpecial sop R1,R2\t\t\t\tis opfam=0x04 & specop=3 & SFU & nullifyForSpecial & R1 & R2 & im5 & sopim5 [ sop=(sopim5 << 5) | im5; ] unimpl\n:COPR,SFU,sop^nullifyForSpecial\t\t\t\t\t\tis opfam=0x0C & SFU & nullifyForSpecial & im5 & sopim17 [ sop=(sopim17 << 5) | im5; ] unimpl\n\n:CLDW,SFU^indexedWordAccessCmplt^loadCC RX^SRRB,RT\t\tis opfam=0x09 & bit9=0 & zero=0 & RX & SRRB & RT & SFU & indexedWordAccessCmplt & loadCC unimpl \n:CLDD,SFU^indexedDoublewordAccessCmplt^loadCC RX^SRRB,RT\t\tis opfam=0x0B & bit9=0 & zero=0 & RX & SRRB & RT & SFU & indexedDoublewordAccessCmplt & loadCC unimpl\n:CSTW,SFU^indexedWordAccessCmplt^storeCC RT,RX^SRRB\tis opfam=0x09 & bit9=1 & zero=0 & RX & SRRB & RT & SFU & indexedWordAccessCmplt & storeCC unimpl\n:CSTD,SFU^indexedDoublewordAccessCmplt^storeCC RT,RX^SRRB\tis opfam=0x0B & bit9=1 & zero=0 & RX & SRRB & RT & SFU & indexedDoublewordAccessCmplt & storeCC unimpl\n\n:CLDW,SFU^shortDispCmplt^loadCC highlse5^SRRB,RT\tis opfam=0x09 & bit9=0 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & loadCC unimpl \n:CLDD,SFU^shortDispCmplt^loadCC highlse5^SRRB,RT\tis opfam=0x0B & bit9=0 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & loadCC unimpl \n:CSTW,SFU^shortDispCmplt^storeCC RT,highlse5^SRRB\tis opfam=0x09 & bit9=1 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & storeCC unimpl \n:CSTD,SFU^shortDispCmplt^storeCC RT,highlse5^SRRB\tis opfam=0x0B & bit9=1 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & storeCC unimpl\n \n \n#################################################\n# Floating Point Instructions\n#################################################\n# These ld/st instructions are the same as the coprocessor instructions, with an SFU of zero or one\n\n# Floating Point Loads, 32 bit, indirect/indexed\n:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32\t\tis opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RX & FPRT32 & SPCBASE & u=0 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n FPRT32 = zext(*:4 addr);\n} \n\n:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32\t\tis opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RX & FPRT32 & SPCBASE & u=1 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2);\n FPRT32 = zext(*:4 addr);\n} \n\n:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32\t\tis opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RX & RB & FPRT32 & SPCBASE & u=0 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n FPRT32 = zext(*:4 addr);\n RB = RB + RX;\n} \n\n:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32\t\tis opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RB & RX & FPRT32 & SPCBASE & u=1 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2);\n FPRT32 = zext(*:4 addr);\n RB = RB + RX;\n} \n\n# Floating Point Loads, 64 bit, indirect/indexed\n:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64\t\tis opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RX & FPRT64 & SPCBASE & u=0 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n FPRT64 = zext(*:8 addr);\n} \n\n:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64\t\tis opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RX & FPRT64 & SPCBASE & u=1 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2);\n FPRT64 = zext(*:8 addr);\n} \n\n:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64\t\tis opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RX & RB & FPRT64 & SPCBASE & u=0 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n FPRT64 = zext(*:8 addr);\n RB = RB + RX;\n} \n\n:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64\t\tis opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RB & RX & FPRT64 & SPCBASE & u=1 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 3);\n FPRT64 = zext(*:8 addr);\n RB = RB + RX;\n} \n\n\n# Floating Point Stores -- 32 and 64 bits\n:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB\t\tis opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & FPRT32 & SPCBASE & u=0 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n\t*addr = FPRT32:4; \n}\n\n:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB\t\tis opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & FPRT32 & SPCBASE & u=1 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2);\n\t*addr = FPRT32:4; \n}\n\n:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB\t\tis opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & RB & FPRT32 & SPCBASE & u=0 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n\t*addr = FPRT32:4; \n RB = RB + RX;\n}\n\n:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB\t\tis opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & RB & FPRT32 & SPCBASE & u=1 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2);\n\t*addr = FPRT32:4; \n RB = RB + RX;\n}\n\n:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB\t\tis opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & FPRT64 & SPCBASE & u=0 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n\t*addr = FPRT64:8; \n}\n\n:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB\t\tis opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & FPRT64 & SPCBASE & u=1 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 3);\n\t*addr = FPRT64:8; \n}\n\n:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB\t\tis opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & RB & FPRT64 & SPCBASE & u=0 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(RX);\n\t*addr = FPRT64:8; \n RB = RB + RX;\n}\n\n:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB\t\tis opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & RB & FPRT64 & SPCBASE & u=1 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2);\n\t*addr = FPRT64:8; \n RB = RB + RX;\n}\n\n\n# Floating Point Load Word with Short Displacement, no modification to RB\n:FLDW^shortDispCmplt^loadCC highlse5^SRRB,FPRT32\tis opfam=0x09 & one=1 & bit9=0 & bits78=0 & shortDispCmplt & loadCC & SRRB & SPCBASE & FPRT32 & highlse5 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n FPRT32 = zext(*:4 addr);\n}\n\n# Floating Point Load Word with Short Displacement, post-modification to RB\n:FLDW^shortDispCmplt^loadCC highlse5^SRRB,FPRT32\tis opfam=0x09 & one=1 & bit9=0 & bits78=0 & shortDispCmplt & loadCC & SRRB & SPCBASE & FPRT32 & RB & highlse5 & m=1 & u=0 {\n\taddr:$(ADDRSIZE) = SPCBASE;\n FPRT32 = zext(*:4 addr);\n RB = RB + sext(highlse5);\n}\n\n# Floating Point Load Word with Short Displacement, pre-modification to RB\n:FLDW^shortDispCmplt^loadCC highlse5^SRRB,FPRT32\tis opfam=0x09 & one=1 & bit9=0 & bits78=0 & shortDispCmplt & loadCC & SRRB & RB & SPCBASE & FPRT32 & highlse5 & m=1 & u=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n FPRT32 = zext(*:4 addr);\n RB = RB + sext(highlse5);\n}\n\n:FLDD^shortDispCmplt^loadCC highlse5^SRRB,FPRT64\tis opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=0 & shortDispCmplt & loadCC & SRRB & SPCBASE & FPRT64 & highlse5 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n FPRT64 = zext(*:8 addr);\n}\n\n:FLDD^shortDispCmplt^loadCC highlse5^SRRB,FPRT64\tis opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=0 & shortDispCmplt & loadCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & m=1 & u=0 {\n\taddr:$(ADDRSIZE) = SPCBASE;\n FPRT64 = zext(*:8 addr);\n RB = RB + sext(highlse5);\n}\n\n:FLDD^shortDispCmplt^loadCC highlse5^SRRB,FPRT64\tis opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=0 & shortDispCmplt & loadCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & m=1 & u=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n FPRT64 = zext(*:8 addr);\n RB = RB + sext(highlse5);\n}\n\n:FSTW^shortDispCmplt^storeCC FPRT32,highlse5^SRRB\tis opfam=0x09 & one=1 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & FPRT32 & highlse5 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n\t*addr = FPRT32:4; \n}\n\n:FSTW^shortDispCmplt^storeCC FPRT32,highlse5^SRRB\tis opfam=0x09 & one=1 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & RB & FPRT32 & highlse5 & m=1 & u=0 {\n\taddr:$(ADDRSIZE) = SPCBASE;\n\t*addr = FPRT32:4;\n\tRB = RB + sext(highlse5);\n}\n\n:FSTW^shortDispCmplt^storeCC FPRT32,highlse5^SRRB\tis opfam=0x09 & one=1 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & RB & FPRT32 & highlse5 & m=1 & u=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n\t*addr = FPRT32:4;\n\tRB = RB + sext(highlse5);\n}\n\n:FSTD^shortDispCmplt^storeCC FPRT64,highlse5^SRRB\tis opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & FPRT64 & highlse5 & m=0 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n\t*addr = FPRT64:8; \n}\n\n:FSTD^shortDispCmplt^storeCC FPRT64,highlse5^SRRB\tis opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & u=0 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE;\n\t*addr = FPRT64:8;\n\tRB = RB + sext(highlse5);\n}\n\n:FSTD^shortDispCmplt^storeCC FPRT64,highlse5^SRRB\tis opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & u=1 & m=1 {\n\taddr:$(ADDRSIZE) = SPCBASE + sext(highlse5);\n\t*addr = FPRT64:8;\n\tRB = RB + sext(highlse5);\n}\n\n# Floating Point Format Conversion Instructions\n:FCNV^fpsf^fpdf FPR232,FPRT32\t\t\t\t\t\tis opfam=0x0E & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fpdf {\n\tFPRT32 = float2float(FPR232);\n}\n \n:FCNV^fpsf^fpdf FPR264,FPRT64\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fpdf & freg2sgl & fptsgl {\n# if src format is sgl, this is sgl to dbl\n# if src format is dbl, this is dbl to sgl\n# sgl to sgl or dbl to dbl don't make sense\n# and we don't support quad right now\t\n\tFPRT64 = float2float(freg2sgl);\n}\n\n:FCNV^fpsf^fpdf FPR264,FPRT64\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fpdf & freg2sgl & fptsgl {\n# if src format is sgl, this is sgl to dbl\n# if src format is dbl, this is dbl to sgl\n# sgl to sgl or dbl to dbl don't make sense\n# and we don't support quad right now\t\n\tfptsgl = float2float(FPR264);\n}\n \n:FCNVXF^fpsf^fpdf FPR232,FPRT32\t\t\t\t\t\t\tis opfam=0x0E & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fpdf {\n\tFPRT32 = int2float(FPR232);\n} \n\n# int2float -- support single/double size ints and single/double floats\n# so handle 4 different cases\n:FCNVXF^fixedsf^fpdf FPR264,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=0 & fpdfraw=0 {\n\tfptsgl = int2float(freg2sgl);\n}\n\n:FCNVXF^fixedsf^fpdf FPR264,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=0 & fpdfraw=1 {\n\tFPRT64 = int2float(freg2sgl);\n}\n\n:FCNVXF^fixedsf^fpdf FPR264,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=1 & fpdfraw=0 {\n\tfptsgl = int2float(FPR264);\n}\n\n:FCNVXF^fixedsf^fpdf FPR264,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=1 & fpdfraw=1 {\n\tFPRT64 = int2float(FPR264);\n}\n\n:FCNVFX^fpsf^fixeddf FPR232,FPRT32\t\t\t\t\t\t\tis opfam=0x0E & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fixeddf {\n\ttemp:4 = round(FPR232);\n\tFPRT32 = trunc(temp);\n}\n\n:FCNVFX^fpsf^fixeddf FPR264,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fixeddf & fptsgl & freg2sgl {\n\tlocal temp:8 = FPR264; \n\ttemp = round(temp);\n\tFPRT64 = trunc(temp);\n} \n\n:FCNVFX^fpsf^fixeddf FPR264,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fixeddf & fptsgl & freg2sgl {\n\tlocal temp:8 = float2float(freg2sgl); # convert single precision to double\n\ttemp = round(temp);\n\tFPRT64 = trunc(temp);\n}\n \n:FCNVFXT^fpsf^fixeddf FPR232,FPRT32\t\t\t\t\t\tis opfam=0x0E & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fixeddf {\n\tFPRT32 = trunc(FPR232);\n} \n\n:FCNVFXT^fpsf^fixeddf FPR264,FPRT64\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fixeddf & fpsfraw & fptsgl & freg2sgl {\n\tlocal value:4 = float2float(FPR264); # convert double precision to single\n\tfptsgl = trunc(value);\n}\n\n:FCNVFXT^fpsf^fixeddf FPR264,FPRT64\t\t\t\t\t\tis opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fixeddf & fpsfraw & fptsgl & freg2sgl {\n\tlocal value:4 = freg2sgl; # get single precision value from left half of 64 bit register\n\tfptsgl = trunc(value);\n}\n\n # Floating Point Functions\n:FCPY^fpfmt FPR232,FPRT32\t\t\t\t\t\t\t\tis opfam=0x0E & fpclass=0 & fpsub=2 & freg1=0 & FPR232 & FPRT32 & fpfmt {\n\tFPRT32 = FPR232;\n} \n\n:FCPY^fpfmt FPR264,FPRT64\t\t\t\t\t\t\t\tis opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fpsfraw=1 & fptsgl & freg2sgl {\n\tfptsgl = freg2sgl;\n}\n\n:FCPY^fpfmt FPR264,FPRT64\t\t\t\t\t\t\t\tis opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fpsfraw=0 & fptsgl & freg2sgl {\n\tFPRT64 = FPR264;\n}\n\n:FABS^fpfmt FPR232,FPRT32\t\t\t\t\t\t\t\tis opfam=0x0E & fpclass=0 & fpsub=3 & freg1=0 & bit5=0 & bit8=0 & FPR232 & FPRT32 & fpfmt {\n\tFPRT32 = abs(FPR232);\n} \n\n:FABS^fpfmt FPR264,FPRT64\t\t\t\t\t\t\t\tis opfam=0x0C & fpclass=0 & fpsub=3 & freg1=0 & bits59=0 & bit10=0 & FPR264 & FPRT64 & fpfmt {\n\tFPRT64 = abs(FPR264);\n}\n\n:FSQRT^fpfmt FPR232,FPRT32\t\t\t\t\t\t\t\tis opfam=0x0E & fpclass=0 & fpsub=4 & freg1=0 & FPR232 & FPRT32 & fpfmt {\n\tFPRT32 = sqrt(FPR232);\n} \n:FSQRT^fpfmt FPR264,FPRT64\t\t\t\t\t\t\t\tis opfam=0x0C & fpclass=0 & fpsub=4 & freg1=0 & FPR264 & FPRT64 & fpfmt {\n\tFPRT64 = sqrt(FPR264);\n}\n\n:FRND^fpfmt FPR232,FPRT32\t\t\t\t\t\t\t\tis opfam=0x0E & fpclass=0 & fpsub=5 & FPR232 & FPRT32 & fpfmt {\n\tFPRT32 = round(FPR232);\n } \n\n:FRND^fpfmt FPR264,FPRT64\t\t\t\t\t\t\t\tis opfam=0x0C & fpclass=0 & fpsub=5 & FPR264 & FPRT64 & fpfmt {\n\tFPRT64 = round(FPR264);\n}\n\n:FADD^fpfmt FPR232,FPR132,FPRT32\t\t\t\t\t\t\tis opfam=0x0E & fpclass=3 & fpsub=0 & FPR232 & FPR132 & FPRT32 & fpfmt {\n\tFPRT32 = FPR132 f+ FPR232;\n} \n\n:FADD^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & freg1sgl & freg2sgl & fptsgl {\n\tfptsgl = freg1sgl f+ freg2sgl;\n}\n\n:FADD^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & freg1sgl & freg2sgl & fptsgl {\n\tFPRT64 = FPR164 f+ FPR264;\n}\n\n:FSUB^fpfmt FPR232,FPR132,FPRT32\t\t\t\t\t\t\tis opfam=0x0E & fpclass=3 & fpsub=1 & FPR232 & FPR132 & FPRT32 & fpfmt {\n\tFPRT32 = FPR232 f- FPR132;\n} \n\n:FSUB^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl {\n\tfptsgl = freg2sgl f- freg1sgl;\n}\n\n:FSUB^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl {\n\tFPRT64 = FPR264 f- FPR164;\n}\n\n:FMPY^fpfmt FPR232,FPR132,FPRT32\t\t\t\t\t\t\tis opfam=0x0E & fpclass=3 & fpsub=2 & bit8=0 & FPR232 & FPR132 & FPRT32 & fpfmt {\n\tFPRT32 = FPR132 f* FPR232;\n} \n\n:FMPY^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl {\n\tfptsgl = freg1sgl f* freg2sgl;\n}\n\n:FMPY^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl {\n\tFPRT64 = FPR164 f* FPR264;\n}\n\n:FDIV^fpfmt FPR232,FPR132,FPRT32\t\t\t\t\t\t\tis opfam=0x0E & fpclass=3 & fpsub=3 & FPR232 & FPR132 & FPRT32 & fpfmt {\n\tFPRT32 = FPR232 f/ FPR132;\n} \n\n:FDIV^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl {\n\tfptsgl = freg2sgl f/ freg1sgl;\n}\n\n:FDIV^fpfmt FPR264,FPR164,FPRT64\t\t\t\t\t\t\tis opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl {\n\tFPRT64 = FPR264 f/ FPR164;\n}\n\n# 64 bit version\n:FMPYADD^fusedfmt FPR264,FPR164,FPRT64,fpra,fpta\t\t\t\tis opfam=0x06 & FPR264 & FPR164 & FPRT64 & fusedfmt & fpra & fpta & bit5=0 {\n\tFPRT64 = FPR164 f* FPR264;\n\tfpta = fpta f+ fpra;\n}\n\n# 32 bit version -- this uses a special encoding of the 32 bit registers and can only use 16-31{LR}, not the lower registers\n:FMPYADD^fusedfmt FUSEDR2,FUSEDR1,FUSEDRT,FUSEDRA,FUSEDTA\t\t\t\tis opfam=0x06 & FUSEDR2 & FUSEDR1 & FUSEDRT & fusedfmt & FUSEDRA & FUSEDTA & bit5=1 {\n\tFUSEDRT = FUSEDR1 f* FUSEDR2;\n\tFUSEDTA = FUSEDTA f+ FUSEDRA;\n\n}\n\n:FMPYSUB^fusedfmt FPR264,FPR164,FPRT64,fpra,fpta\t\t\t\tis opfam=0x26 & FPR264 & FPR164 & FPRT64 & fusedfmt & fpra & fpta & bit5=0 {\n\tFPRT64 = FPR164 f* FPR264;\n\tfpta = fpta f- fpra;\n}\n\n:FMPYSUB^fusedfmt FUSEDR2,FUSEDR1,FUSEDRT,FUSEDRA,FUSEDTA\t\t\t\tis opfam=0x26 & FUSEDR2 & FUSEDR1 & FUSEDRT & fusedfmt & FUSEDRA & FUSEDTA & bit5=1 {\n\tFUSEDRT = FUSEDR1 f* FUSEDR2;\n\tFUSEDTA = FUSEDTA f- FUSEDRA;\n}\n\n# Fixed Point / Integer Multiply\n:XMPYU^fpfmt FPR232,FPR132,FPRT64\t\t\t\t\t\t\t\tis opfam=0x0E & fpclass=3 & fpsub=2 & bit8=1 & FPR232 & FPR132 & FPRT64 & fpfmt & fptsgl {\n\targ1:8 = zext(FPR232);\n\targ2:8 = zext(FPR132);\n\tprod:8 = arg1 * arg2;\n\tFPRT64 = prod;\n } \n\n# Floating Point Compare\n# 32 bit register comparison\n:FCMP^fpfmt1bit^fpcmp FPR232,FPR132\t\t\t\t\t\tis opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & bit11=0 & fpcmp {\n\tlocal result:1 = 0:1;\n\t# shift the previous compareBit onto the compareQueue\n\tcompareQueue = (compareQueue << 1);\n\tcompareQueue = compareQueue | compareBit;\n\tresult = fpcmp;\n\tcompareBit = result;\n}\n\n:FCMP^fpfmt1bit^fpcmp64 FPR232,FPR132\t\t\t\t\t\tis opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & bit11=1 & fpcmp64 {\n\tlocal result:1 = 0:1;\n\t# shift the previous compareBit onto the compareQueue\n\tcompareQueue = (compareQueue << 1);\n\tcompareQueue = compareQueue | compareBit;\n\tresult = fpcmp64;\n\tcompareBit = result;\n}\n\n# 64 bit register comparison \n:FCMP^fpfmt^fpcmp FPR264,FPR164\t\t\t\t\t\tis opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpsfraw=0 & fpcmp {\n\tlocal result:1 = 0:1;\n\t# shift the previous compareBit onto the compareQueue\n\tcompareQueue = (compareQueue << 1);\n\tcompareQueue = compareQueue | compareBit;\n\tresult = fpcmp;\n\tcompareBit = result;\n}\n\n:FCMP^fpfmt^fpcmp64 FPR264,FPR164\t\t\t\t\t\tis opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpsfraw=1 & fpcmp64 {\n\tlocal result:1 = 0:1;\n\t# shift the previous compareBit onto the compareQueue\n\tcompareQueue = (compareQueue << 1);\n\tcompareQueue = compareQueue | compareBit;\n\tresult = fpcmp64;\n\tcompareBit = result;\n}\n\n:FTEST^fptest\t\t\t\t\t\t\t\t\t\tis opfam=0x0C & fpclass=2 & fpsub=1 & fptest & $(COMMON)\n\t[\n\t nullifyEnable = 1;\n\t globalset(inst_next, nullifyEnable);\n\t] \n{\n\tnullifyNextCond = compareBit;\n}\n\n# Misc Floating Point Functions\n:COPR.0.0\t\t\t\t\t\t\t\t\t\t\tis opfam=0x0C & im26=0x0 { }\n\n###############################################################\n# Performance Montioring Unit Instructions\n###############################################################\n:PMENB\t\t\t\t\t\t\t\t\t\t\t\tis opfam=0x0C & bit5=0 & sfu=0x2 & pmuop=0x3 { }\n:PMDIS\t\t\t\t\t\t\t\t\t\t\t\tis opfam=0x0C & bit5=0 & sfu=0x2 & pmuop=0x1 { }\n\n} # end with : phase=1\n" }, { "path": "pypcode/processors/PA-RISC/data/manuals/pa11_acd.idx", "content": "@pa11_acd.pdf[PA-RISC 1.1 Architecture and Instruction Set Reference Manual, HP Part Number: 09740-90039, February 1994, Third Edition]\nADD\t, 171\nADDB\t, 163\nADDBF\t, 164\nADDBT\t, 163\nADDO\t, 173\nADDIB\t, 165\nADDIBF\t, 166\nADDIBT\t, 165\nADDIL\t, 145\nADDL\t, 172\nADDI\t, 203\nADDIT\t, 205\nADDITO\t, 206\nADDIO\t, 204\nADDC\t, 174\nADDCO\t, 175\nAND\t, 195\nANDCM\t, 196\nB\t, 150\nBL\t, 150\nBLE\t, 156\nBLR\t, 153\nBE\t, 155\nBB\t, 168\nBVB\t, 167\nBV\t, 154\nBREAK\t, 226\nCOMB\t, 159\nCMPBF\t, 160\nCMPBT\t, 159\nCMPCLR\t, 192\nCMPIB\t, 161\nCMPIBF\t, 162\nCMPIBT\t, 161\nCMPICLR\t, 209\nCLDDX\t, 276\nCLDDS\t, 280\nCLDWX\t, 275\nCLDWS\t, 279\nCOPR\t, 274\nCSTDX\t, 278\nCSTDS\t, 282\nCSTWX\t, 277\nCSTWS\t, 281\nCOPY\t, 193\nDCOR\t, 200\nDEPW\t, 217\nDEPWI\t, 219\nDIAG\t, 263\nDS\t, 191\nXOR\t, 194\nEXTRW\t, 214\nXMPYU\t, 341\nFABS\t, 332\nFADD\t, 335\nFCMP\t, 342\nFCNVXF\t, 328\nFCNVFX\t, 329\nFCNVFXT\t, 330\nFCNVFF\t, 327\nFCPY\t, 331\nFDIV\t, 338\nCOPR\t, 345\nFLDDX\t, 320\nFLDDS\t, 324\nFLDWX\t, 319\nFLDWS\t, 323\nFMPY\t, 337\nFMPYADD\t, 339\nFMPYSUB\t, 340\nFRND\t, 334\nFSQRT\t, 333\nFSTDX\t, 322\nFSTDS\t, 326\nFSTWX\t, 321\nFSTWS\t, 325\nFSUB\t, 336\nFTEST\t, 344\nFDC\t, 259\nFDCE\t, 261\nFIC\t, 260\nFICE\t, 262\nGATE\t, 151\nDEBUGID\t, 356\nSPOP1\t, 271\nOR\t, 193\nIDTLBA\t, 253\nIDTLBP\t, 255\nIITLBA\t, 254\nIITLBP\t, 256\nIDCOR\t, 202\nLDCWX\t, 128\nLDCWS\t, 134\nLDB\t, 118\nLDBX\t, 126\nLDBS\t, 132\nLCI\t, 248\nLDH\t, 117\nLDHX\t, 125\nLDHS\t, 131\nLDI\t, 143\nLDIL\t, 144\nLDO\t, 143\nLPA\t, 246\nLDSID\t, 234\nLDW\t, 116\nLDWAX\t, 127\nLDWAS\t, 133\nLDWM\t, 122\nLDWX\t, 124\nLDWS\t, 130\nMOVB\t, 157\nMFCTL\t, 239\nMFDBAM\t, 357\nMFDBAO\t, 358\nMFIBAM\t, 359\nMFIBAO\t, 360\nMFSP\t, 238\nMOVIB\t, 158\nMTCTL\t, 236\nMTDBAM\t, 361\nMTDBAO\t, 362\nMTIBAM\t, 363\nMTIBAO\t, 364\nMTSAR\t, 237\nMTSP\t, 235\nMTSM\t, 233\nNOP\t, 193\nPMDIS\t, 350\nPMENB\t, 349\nPROBER\t, 242\nPROBERI\t, 243\nPROBEW\t, 244\nPROBEWI\t, 245\nPDC\t, 257\nPDTLB\t, 249\nPDTLBE\t, 251\nPITLB\t, 250\nPITLBE\t, 252\nRSM\t, 232\nRFI\t, 227\nRFIR\t, 229\nSSM\t, 231\nSHRPW\t, 211\nSH1ADD\t, 176\nSH1ADDL\t, 177\nSH1ADDO\t, 178\nSH3ADD\t, 182\nSH3ADDL\t, 183\nSH3ADDO\t, 184\nSH2ADD\t, 179\nSH2ADDL\t, 180\nSH2ADDO\t, 181\nSPOP1\t, 271\nSPOP3\t, 273\nSPOP2\t, 272\nSPOP0\t, 270\nSTB\t, 121\nSTBS\t, 138\nSTBYS\t, 140\nSTH\t, 120\nSTHS\t, 137\nSTW\t, 119\nSTWAS\t, 139\nSTWM\t, 123\nSTWS\t, 136\nSUB\t, 185\nSUBT\t, 189\nSUBTO\t, 190\nSUBO\t, 186\nSUBI\t, 207\nSUBIO\t, 208\nSUBB\t, 187\nSUBBO\t, 188\nSYNC\t, 240\nSYNCDMA\t, 241\nUADDCM\t, 198\nUADDCMT\t, 199\nUXOR\t, 197\nVDEP\t, 216\nVDEPI\t, 218\nVEXTRS\t, 213\nVEXTRU\t, 212\nVSHD\t, 210\nZDEP\t, 221\nZDEPI\t, 223\nZVDEP\t, 220\nZVDEPI\t, 222\n" }, { "path": "pypcode/processors/PA-RISC/data/patterns/pa-risc_patterns.xml", "content": "\n\n \n\n \n 0xe840c002 \t\t\t\t\n 0xe840c000 0x........ \t\t\n \n\n \n 0x6bc23fd9 \t\t\n 0x6bc23fd9 0x08030241 0x081e0243 \t\n 0x........ 0x08030241 \t\t\n 0x........ 0x........ 0x08030241 \t\n \n \n\n \n\n \n" }, { "path": "pypcode/processors/PA-RISC/data/patterns/patternconstraints.xml", "content": "\n \n pa-risc_patterns.xml\n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t\n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n\t\t\n\t\t\n \n \n \n \n \n \n \n\t\n \n \n \n\t\n\t\n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n\t\t\n\t\t\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24.ldefs", "content": "\n\n\n \n PIC-24E\n \n \n \n PIC-24F\n \n \n \n PIC-24H\n \n \n \n dsPIC30F\n \n \n \n \n dsPIC33F\n \n \n \n \n dsPIC33E\n \n \n \n \n dsPIC33C\n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24.pspec", "content": "\n\n\n\t\n\t\t\n\t\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24.sinc", "content": "#TODO: relative branches are not computed as addresses in []\n\n# TODO: byte oriented inst_next/inst_start must be changed to word oriented when storing into reg/stack...\n\n\n# NOTE: No support for stack pointer limit register (SPLIM)\n# NOTE: Some registers are larger than PIC defines.\n# NOTE: No support for signal emulation.\n# NOTE: No support for mapping a 32Kbyte section of program memory space into upper 32 Kbytes of data address space.\n# NOTE: No repeat loop status bit.\n# NOTE: Split flags register, which could cause side effects.\n# NOTE: pwrsav pcode is not defined.\n# TODO: Support for fractional multiplier mode.\n# TODO: Check ACCA and ACCB staturation modes.\n# TODO: Check accumulator staturation and rounding modes.\n# TODO: Test Stack Frame Active (SFA) status bit.\n\n# Basic ================================================================================\n\n#define endian=little; # little endian only\ndefine alignment=2; # 2 signifies how the PC moves per instruction\n\ndefine space ram type=ram_space \t size=2; # (2x8=)16-bit address space\ndefine space register type=register_space size=2; # (2x8=)16-bit address space\ndefine space rom type=ram_space size=3 wordsize=2 default ; # (3x8=)24-bit address space\n # (2x8=)16-bit word per address\n # 24-bit canonical instruction:\n # address : code\n # 0 : byte2 | byte1\n # 1 : pad | byte3\n # 2 : byte2 | byte1\n # 3 : pad | byte3\n # .\n # .\n # .\n # etc\n\n\n# Registers ============================================================================\n\ndefine ram offset=0 size=2 [\n W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 \n];\n\ndefine ram offset=0 size=4 [\n W1W0 W3W2 W5W4 W7W6 W9W8 W11W10 W13W12 W15W14 \n];\n\n# define ram offset=28 size=3 [ FP ];\n# define ram offset=32 size=3 [ SP ];\n\n# Note: This assumes little endian only\ndefine ram offset=0 size=1 [\n W0byte _ W1byte _ W2byte _ W3byte _\n W4byte _ W5byte _ W6byte _ W7byte _ \n W8byte _ W9byte _ W10byte _ W11byte _\n W12byte _ W13byte _ W14byte _ W15byte _\n];\n\ndefine register offset=0 size=2 [\n SHADOW_W0 SHADOW_W1 SHADOW_W2 SHADOW_W3\n];\n\ndefine ram offset=0x20 size=2 [ SPLIM ]; # Stack Pointer Limit\n\n# Note: ACCxU implemented here as a 16 bit, actual register is only 8 bits in PIC3x\n# Note: This assumes little endian only\ndefine ram offset=0x22 size=2 [\n ACCAL ACCAH ACCAU\n ACCBL ACCBH ACCBU\n];\n\n# Note: Like above ACCx implemented here as a 48 bit, actual register is only 40 bits in PIC3x\ndefine ram offset=0x22 size=6 [\n ACCA\n ACCB\n];\n\ndefine ram offset=0x2E size=3 [ PC ];\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\ndefine ram offset=0x32 size=2 [ DSRPAG ]; # 9bit Data Space Read Page Address\ndefine ram offset=0x34 size=2 [ DSWPAG ]; # 8bit Data Space Write Page Address\ndefine ram offset=0x36 size=2 [ RCOUNT ]; # Repeat counter\n# TODO: Re-implement with shadow stack\n# define ram offset=0x38 size=2 [ DCOUNT ]; # 13 bits long DO Loop counter\ndefine ram offset=0x54 size=1 [ TBLPAG ]; # 7bit Data Table Page Address\n@else\ndefine ram offset=0x32 size=1 [ TBLPAG ]; # 8bit Data Table Page Address\ndefine ram offset=0x34 size=1 [ PSVPAG ]; # Program Memory Visibility Page Address Pointer\ndefine ram offset=0x36 size=2 [ RCOUNT ]; # Repeat counter\ndefine ram offset=0x38 size=2 [ DCOUNT ]; # 13 bits long DO Loop counter\ndefine ram offset=0x3A size=3 [ DOSTART ];\ndefine ram offset=0x3E size=3 [ DOEND ];\n@endif \n\ndefine ram offset=0x44 size=2 [ CORCON ]; # Core Control Register\ndefine ram offset=0x46 size=2 [ MODCON ];\ndefine ram offset=0x48 size=2 [ XMODSRT ];\ndefine ram offset=0x4A size=2 [ XMODEND ];\ndefine ram offset=0x4C size=2 [ YMODSRT ];\ndefine ram offset=0x4E size=2 [ YMODEND ];\ndefine ram offset=0x50 size=2 [ XBREV ];\ndefine ram offset=0x52 size=2 [ DISICNT ]; # Disable Interrupts Counter\n\n# Control registers\ndefine register offset=1024 size=1 [\n SRL\n SRH\n];\n\n# SR component register fields (pseudo)\ndefine register offset=1536 size=1 [\n SRH_OA\n SRH_OB\n SRH_SA\n SRH_SB\n SRH_OAB\n SRH_SAB\n SRH_DA\n SRH_DC\n\n SRL_IPL2\n SRL_IPL1\n SRL_IPL0\n SRL_RA\n SRL_N\n SRL_OV\n SRL_Z\n SRL_C\n\n DISI\n\n SHADOW_SRH_DC\n\n SHADOW_SRL_N\n SHADOW_SRL_OV\n SHADOW_SRL_Z\n SHADOW_SRL_C\n];\n\n\n# System register - Program Counter\n# Note: actual PC is 23-bits wide, with a fixed 0 for the zeroeth bit\ndefine register offset=2048 size=3 [\n\t# dsPIC33E uses array of registers to have 4 deep zero overhead do loops\n@if defined(dsPIC33E) || defined(dsPIC33C)\n DOSTART # 24 bits long bit23=bit0=0 DO Loop Start Address\n DOSTART1\n DOSTART2\n DOSTART3\n DOEND # 24 bits long bit23=bit0=0 DO Loop End Address\n DOEND1\n DOEND2\n DOEND3\n@endif\n DOSTART_SHADOW\n DOEND_SHADOW\n];\n\n\n# System register - CPU Core Control Register # ????? connect this to meta-model?\ndefine register offset=2560 size=2 [\n WDTcount # ????? formal name not documented, true size unknown\n WDTprescalarA # ????? formal name not documented, true size unknown\n WDTprescalarB # ????? formal name not documented, true size unknown\n];\n\n\n# CORCON component register fields (pseudo)\ndefine register offset=3072 size=1 [\n CORCON_VAR\n CORCON_IPL3\n CORCON_PSV\n CORCON_SFA\n@if defined(dsPIC33E) || defined(dsPIC33C)\n CORCON_DL # DO loop nesting level status bits (3 bit long)\n@endif\n];\n\n\n# NOTE: Technically this section only apply to dsPIC30F, dsPIC33F, dsPIC33E, and dsPIC33C but we will allow all profiles to see it.\n\n# This supports the zero overhead do loop specific registers\ndefine register offset=4096 size=2 [\n\n# dsPIC33E uses array of registers to have 4 deep zero overhead do loops\n@if defined(dsPIC33E) || defined(dsPIC33C)\n DCOUNT # 13 bits long DO Loop counter\n DCOUNT1 \n DCOUNT2 \n DCOUNT3\n@else\n# dsPIC30 and dsPIC33F use shadow register to have allow one level deep zero overhead do loop (doesn't hurt to have in other variants)\n DCOUNT_SHADOW \n@endif\n];\n\n# This supports the \"skip next instruction\" conditionals\ndefine register offset=4608 size=1 [\n SkipNextFlag # pseudo run-time register to flag skipping over this instruction (making it a NOP)\n];\n\n\n# contextreg is our instruction context\n# here we are only using it for zero overhead do loops\n\n# NOTE: At first i used size=2 and it seem to be having problems?\ndefine register offset=5120 size=4 [ contextreg ];\n\ndefine context contextreg \n blockEnd=(0,0) noflow # Flag to indicate end do zero overhead do loop\n phase=(2,3) # Flag to indicate that we are in the middle of a instruction and not to change context\n repeatInstr=(4,4) noflow # Flag to indicate end of repeat instruction loop\n skipInstr=(5,5) noflow\n # Flag to indicate that we are in the next instruction after a \"skip next instruction\" command\n;\n\n# Tokens ============================================================================\n\ndefine token instr(32)\n padding=(24,31) # padding for 4th byte that is not decoded in actual processor\n OP_31_0 =(0,31)\n OP_31_4 =(4,31)\n \n OP_23_0 =(0,23)\n OP_23_1 =(1,23)\n OP_23_4 =(4,23)\n OP_23_11=(11,23)\n OP_23_12=(12,23)\n OP_23_14=(14,23)\n OP_23_15=(15,23)\n OP_23_16=(16,23)\n OP_23_18=(18,23)\n OP_23_19=(19,23)\n OP_23_20=(20,23)\n \n OP_21_20=(20,21)\n \n OP_19_16=(16,19)\n OP_19_17=(17,19)\n OP_19_18=(18,19)\n \n OP_15_8 =(8,15)\n OP_15_12=(12,15)\n OP_15_14=(14,15)\n \n OP_14_0 =(0,14)\n OP_14_4 =(4,14)\n OP_14_6 =(6,14)\n OP_14_7 =(7,14)\n OP_14_11=(11,14)\n OP_14_12=(12,14)\n \n OP_13_4 =(4,13)\n \n OP_11_7 =(7,11)\n OP_11_8 =(8,11)\n OP_11_10=(10,11)\n \n OP_10_8 =(8,10)\n OP_10_7 =(7,10)\n OP_10_4 =(4,10)\n \n OP_9_4 =(4,9)\n OP_9_8 =(8,9)\n \n OP_7_0 =(0,7)\n OP_7_4 =(4,7)\n OP_7_5 =(5,7)\n OP_7_6 =(6,7)\n \n OP_6_0 =(0,6)\n OP_6_4 =(4,6)\n OP_6_5 =(5,6)\n \n OP_5_4 =(4,5)\n \n OP_3_0 =(0,3) \n \n OP_1_0 =(0,1)\n \n OP_19 =(19,19)\n OP_15 =(15,15)\n OP_14 =(14,14)\n OP_13 =(13,13)\n OP_12 =(12,12)\n OP_11 =(11,11)\n OP_7 =(7,7)\n OP_6 =(6,6)\n OP_5 =(5,5)\n OP_3 =(3,3)\n OP_0 =(0,0)\n \n TOK_n =(16,16)\n TOK_A =(15,15)\n TOK_B =(14,14)\n TOK_Bb =(10,10)\n TOK_CCCC =(16,19)\n TOK_D =(13,13)\n TOK_W =(6,6)\n TOK_Z =(15,15)\n TOK_Zb =(11,11)\n\n TOK_f12 =(1,12)\n TOK_f13 =(0,12)\n TOK_f15 =(1,15)\n TOK_f15b =(4,18)\n TOK_k3 =(0,2)\n TOK_k4 =(0,3)\n TOK_k5 =(0,4)\n TOK_k6 =(0,5) signed\n TOK_k8a =(0,4)\n TOK_k4b =(4,7)\n TOK_k8b =(7,9)\n TOK_k8c =(4,11)\n TOK_k10 =(4,13)\n TOK_k14 =(0,13)\n TOK_k15 =(0,14)\n TOK_k16 =(4,19)\n TOK_k16t =(0,15)\n \n TOK_r4 =(7,10) signed\n TOK_bit4word =(0,0)\n TOK_b3 =(13,15)\n TOK_b1 =(0,0)\n TOK_b4 =(12,15)\n TOK_n6 =(4,9) signed\n TOK_n7 =(0,6)\n TOK_n15 =(1,15)\n TOK_n16 =(0,15) signed\n\n TOK_0 =(0,0)\n TOK_7 =(7,7)\n TOK_13\t\t =(13,13)\n \n TOK_3_0_Wreg =(0,3) # 16-bit full reg\n TOK_3_0_Breg =(0,3) # 8-bit LSB of reg\n TOK_3_1_Dreg =(1,3) # 32-bit reg pair, e.g., W1:W0\n TOK_3_1_Dregn =(1,3) # 32-bit reg pair name, e.g., W0\n \n TOK_4_0_U =(0,4)\n \n TOK_6_4_U =(4,6)\n \n TOK_9_0_U =(0,9) \n\n TOK_10_7_Wreg =(7,10) # 16-bit full reg\n TOK_10_7_Breg =(7,10) # 8-bit LSB of reg\n TOK_10_7_Wregp =(7,10) # 16-bit full reg offset by one\n TOK_10_8_Dreg =(8,10) # 32-bit reg pair, e.g., W1:W0\n TOK_10_8_Dregn =(8,10) # 32-bit reg pair name, e.g., W0\n \n TOK_11_8_Wreg =(8,11) # 16-bit full reg\n\n TOK_13_11_U =(11,13)\n\n TOK_14_12_Dreg =(12,14) # 32-bit reg pair, e.g., W1:W0\n TOK_14_12_Dregn=(12,14) # 32-bit reg pair name, e.g., W0\n TOK_14_11_Wreg =(11,14) # 16-bit full reg\n TOK_14_11_Wregn=(11,14) # 16-bit full reg offset by one\n TOK_14_11_Breg =(11,14) # 8-bit LSB of reg\n\n TOK_18_15_Wreg =(15,18) # 16-bit full reg\n TOK_18_15_Breg =(15,18) # 8-bit LSB of reg\n TOK_18_15_S =(15,18) signed\n \n TOK_17_16_mm =(16,17)\n TOK_18_16_mmm =(16,18)\n TOK_13_12_xx =(12,13)\n TOK_13_12_kk =(12,13)\n TOK_11_10_yy =(10,11)\n TOK_11_10_PP =(10,11)\n TOK_9_6_iiii =(6,9)\n TOK_5_2_jjjj =(2,5)\n TOK_1_0_aa =(0,1)\n ;\n\n\n\n\n# Attach variables =====================================================\n\n# attach normal registers \nattach variables [ TOK_18_15_Wreg TOK_3_0_Wreg TOK_10_7_Wreg TOK_11_8_Wreg TOK_14_11_Wreg ] [\n\n W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15\n];\n\nattach variables [ TOK_14_11_Wregn ] [\n\t_\t\tW0\t\tW1\t\tW2\t\tW3\t\tW4\t\tW5\t\tW6\n\tW7\t\tW8\t\tW9\t\tW10\t\tW11\t\tW12\t\tW13\t\tW14\n];\n\nattach variables [ TOK_10_7_Wregp ] [\n\tW0\t\tW1\t\tW2\t\tW3\t\tW4\t\tW5\t\tW6\t\tW7\n\tW8\t\tW9\t\tW10\t\tW11\t\tW12\t\tW13\t\tW14\t\tW0\n];\n\n# attach lower byte sub-registers\nattach variables [ TOK_18_15_Breg TOK_3_0_Breg TOK_10_7_Breg TOK_14_11_Breg ] [\n\n W0byte W1byte W2byte W3byte W4byte W5byte W6byte W7byte\n W8byte W9byte W10byte W11byte W12byte W13byte W14byte W15byte\n];\n\n# attach double registers (ref by even reg only)\nattach variables [ TOK_3_1_Dreg TOK_10_8_Dreg TOK_14_12_Dreg ] [\n\n W1W0 \t\tW3W2 W5W4 W7W6 W9W8 W11W10 W13W12 W15W14 \n];\nattach variables [ TOK_3_1_Dregn TOK_10_8_Dregn TOK_14_12_Dregn ] [\n\n W0 \tW2 W4 W6 W8 W10 W12 W14 \n];\n\n\n# Sub-constructors ====================================================================\n \n@define WSconstraint \"(OP_6=0 | OP_5=0)\"\n@define WDconstraint \"(OP_13=0 | OP_12=0)\"\n\n# Use must be constrained by $(WSconstraint)\nWs_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWs_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:2 TOK_3_0_Wreg; }\n\nWs_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; }\n\nWs_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; }\n\nWs_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWs_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; }\n\n\n# Use must be constrained by $(WSconstraint)\nWsd_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_1_Dreg & OP_0=0\n { export TOK_3_1_Dreg; }\n\nWsd_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:4 TOK_3_0_Wreg; }\n\nWsd_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 tmp; }\n\nWsd_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 tmp; }\n\nWsd_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 TOK_3_0_Wreg; }\n\nWsd_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 TOK_3_0_Wreg; }\n\n\n# Use must be constrained by $(WSconstraint)\nWsnd_t: TOK_3_0_Wreg is TOK_13_11_U=0x0 & TOK_3_0_Wreg & TOK_3_1_Dreg & OP_0=0\n { export TOK_3_1_Dreg; }\n\nWsnd_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:4 TOK_3_0_Wreg; }\n\nWsnd_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 tmp; }\n\nWsnd_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 tmp; }\n\nWsnd_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 TOK_3_0_Wreg; }\n\nWsnd_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 TOK_3_0_Wreg; }\n\n\n# Use must be constrained by $(WSconstraint)\nWsb_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWsb_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:2 TOK_3_0_Wreg; }\n\nWsb_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; }\n\nWsb_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; }\n\nWsb_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWsb_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; }\n\n\n# Use must be constrained by $(WSconstraint)\nWsbyte_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nWsbyte_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:1 TOK_3_0_Wreg; }\n\nWsbyte_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 tmp; }\n\nWsbyte_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 tmp; }\n\nWsbyte_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 TOK_3_0_Wreg; }\n\nWsbyte_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 TOK_3_0_Wreg; }\n\n\n# Use must be constrained by $(WSconstraint)\nWsbbyte_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nWsbbyte_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:1 TOK_3_0_Wreg; }\n\nWsbbyte_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 tmp; }\n\nWsbbyte_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 tmp; }\n\nWsbbyte_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 TOK_3_0_Wreg; }\n\nWsbbyte_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 TOK_3_0_Wreg; }\n\n\n# Use must be constrained by $(WDconstraint)\nWd_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg\n { export TOK_10_7_Wreg; }\n\nWd_t: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { export *[ram]:2 TOK_10_7_Wreg; }\n\nWd_t: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 tmp; }\n\nWd_t: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; }\n\nWd_t: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 TOK_10_7_Wreg; }\n\nWd_t: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 TOK_10_7_Wreg; }\n\n\n# Use must be constrained by $(WDconstraint)\nWdd_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg & TOK_10_8_Dreg & OP_7=0\n { export TOK_10_8_Dreg; }\n\nWdd_t: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { export *[ram]:4 TOK_10_7_Wreg; }\n\nWdd_t: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 4; export *[ram]:4 tmp; }\n\nWdd_t: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 4; export *[ram]:4 tmp; }\n\nWdd_t: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg - 4; export *[ram]:4 TOK_10_7_Wreg; }\n\nWdd_t: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg + 4; export *[ram]:4 TOK_10_7_Wreg; }\n\n\n# Use must be constrained by $(WDconstraint)\nWdbyte_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg & TOK_10_7_Breg\n { export TOK_10_7_Breg; }\n\nWdbyte_t: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { export *[ram]:1 TOK_10_7_Wreg; }\n\nWdbyte_t: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 tmp; }\n\nWdbyte_t: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 tmp; }\n\nWdbyte_t: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 TOK_10_7_Wreg; }\n\nWdbyte_t: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 TOK_10_7_Wreg; }\n\n\n# A lot like WdWRD_t\nmovWs: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nmovWs: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:2 TOK_3_0_Wreg; }\n\nmovWs: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; }\n\nmovWs: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; }\n\nmovWs: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nmovWs: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nmovWs: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { local tmp = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\nmovWs: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { local tmp = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\n\nmovWsbyte: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nmovWsbyte: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:1 TOK_3_0_Wreg; }\n\nmovWsbyte: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 tmp; }\n\nmovWsbyte: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 tmp; }\n\nmovWsbyte: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 TOK_3_0_Wreg; }\n\nmovWsbyte: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 TOK_3_0_Wreg; }\n\nmovWsbyte: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; }\n\nmovWsbyte: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; }\n\n\n\nmovWd: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg\n { export TOK_10_7_Wreg; }\n\nmovWd: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { export *[ram]:2 TOK_10_7_Wreg; }\n\nmovWd: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 tmp; }\n\nmovWd: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; }\n\nmovWd: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 TOK_10_7_Wreg; }\n\nmovWd: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 TOK_10_7_Wreg; }\n\nmovWd: \"[\"TOK_10_7_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_13_11_U=0x6 & TOK_18_15_Wreg & TOK_10_7_Wreg\n { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\nmovWd: \"[\"TOK_10_7_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_13_11_U=0x7 & TOK_18_15_Wreg & TOK_10_7_Wreg\n { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\n\n\nmovWdbyte: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg & TOK_10_7_Breg\n { export TOK_10_7_Breg; }\n\nmovWdbyte: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { export *[ram]:1 TOK_10_7_Wreg; }\n\nmovWdbyte: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 tmp; }\n\nmovWdbyte: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 tmp; }\n\nmovWdbyte: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 TOK_10_7_Wreg; }\n\nmovWdbyte: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 TOK_10_7_Wreg; }\n\nmovWdbyte: \"[\"TOK_10_7_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_13_11_U=0x6 & TOK_18_15_Wreg & TOK_10_7_Wreg\n { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; }\n\nmovWdbyte: \"[\"TOK_10_7_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_13_11_U=0x7 & TOK_18_15_Wreg & TOK_10_7_Wreg\n { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; }\n\n\n\n\n\nWn_t: TOK_3_0_Wreg is TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWnbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nWnd_t: TOK_10_7_Wreg is TOK_10_7_Wreg\n { export TOK_10_7_Wreg; }\n \nWndd_t: TOK_10_8_Dregn is TOK_10_8_Dreg & TOK_10_8_Dregn\n { export TOK_10_8_Dreg; }\n\nWnda_t: TOK_10_7_Wreg is TOK_10_7_Wreg\n { export TOK_10_7_Wreg; }\n\nWnbf_t: TOK_11_8_Wreg is TOK_11_8_Wreg\n { export TOK_11_8_Wreg; }\n \nWdpp_t: \"[\"TOK_10_7_Wreg\"++]\" is TOK_10_7_Wreg\n { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; }\n \nWndabyte_t: TOK_10_7_Wreg is TOK_10_7_Wreg & TOK_10_7_Breg\n { export TOK_10_7_Breg; }\n\nWndb_t: TOK_3_0_Wreg is TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWndbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nWns_t: TOK_3_0_Wreg is TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWnsbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nWb_t: TOK_18_15_Wreg is TOK_18_15_Wreg\n { export TOK_18_15_Wreg; }\n\nWbbyte_t: TOK_18_15_Wreg is TOK_18_15_Wreg & TOK_18_15_Breg\n { export TOK_18_15_Breg; }\n\nWbb_t: TOK_14_11_Wreg is TOK_14_11_Wreg\n { export TOK_14_11_Wreg; }\n\nWbds_t: TOK_14_12_Dregn is TOK_14_12_Dreg & TOK_14_12_Dregn\n { export TOK_14_12_Dreg; }\n\nWbbbyte_t: TOK_14_11_Wreg is TOK_14_11_Wreg & TOK_14_11_Breg\n { export TOK_14_11_Breg; }\n\nWnb_t: TOK_3_0_Wreg is TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWnbbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg\n { export TOK_3_0_Breg; }\n\nWbd_t: TOK_14_11_Wreg is TOK_14_11_Wreg \n { export TOK_14_11_Wreg; }\n\nWREG_t: \",wreg\" is TOK_B=0 & TOK_D=0\n { export W0; }\n\nWREG_t: \"\" is TOK_B=0 & TOK_D=1 & TOK_f13\n { export *[ram]:2 TOK_f13; }\n\nWREGbyte_t: \",wreg\" is TOK_B=1 & TOK_D=0\n { export W0byte; }\n\nWREGbyte_t: \"\" is TOK_B=1 & TOK_D=1 & TOK_f13\n { export *[ram]:1 TOK_f13; }\n\nWREGb_t: \"wreg\" is TOK_B=0 & TOK_D=0\n { export W0; }\n\nWREGbbyte_t: \"wreg\" is TOK_B=1 & TOK_D=0\n { export W0byte; }\n\nWREG_W0_t: \"wreg\" is TOK_B=0 \n { export W0; }\n\nWREG_W0byte_t: \"wreg\" is TOK_B=1 \n { export W0byte; }\n\nf13b_t: TOK_f13 is TOK_B=0 & TOK_D=1 & TOK_f13\n { export *[ram]:2 TOK_f13; }\n\nf13bbyte_t: TOK_f13 is TOK_B=1 & TOK_D=1 & TOK_f13\n { export *[ram]:1 TOK_f13; }\n\nf12_t: val \t is TOK_f12 [ val = TOK_f12 << 1; ]\n { export *[ram]:2 val; }\n\nf13_t: TOK_f13 is TOK_B=0 & TOK_f13\n { export *[ram]:2 TOK_f13; }\n\nf13byte_t: TOK_f13 is TOK_B=1 & TOK_f13\n { export *[ram]:1 TOK_f13; }\n\nf15_t: addr is TOK_f15\n [ addr = ( TOK_f15 << 1 ); ] { export *[ram]:2 addr; }\n\nf15b_t: addr is TOK_f15b\n [ addr = ( TOK_f15b << 1 ); ] { export *[ram]:2 addr; }\n\nk3_t: \"#\"TOK_k3 is TOK_k3\n { export *[const]:1 TOK_k3; }\n \nk4_t: \"#\"TOK_k4 is TOK_k4\n { export *[const]:1 TOK_k4; }\n\nk5: \"#\"TOK_k5 is TOK_k5\n { export *[const]:2 TOK_k5; }\n \nk5_t: \"#\"TOK_k5 is TOK_B=0 & TOK_k5\n { export *[const]:2 TOK_k5; }\n\nk5byte_t: \"#\"TOK_k5 is TOK_B=1 & TOK_k5\n { export *[const]:1 TOK_k5; }\n\nk5_B10_t: \"#\"TOK_k5 is TOK_Bb=0 & TOK_k5\n { export *[const]:2 TOK_k5; }\n\nk5byte_B10_t: \"#\"TOK_k5 is TOK_Bb=1 & TOK_k5\n { export *[const]:1 TOK_k5; }\n\n\nk10_t: \"#\"TOK_k10 is TOK_B=0 & TOK_k10\n { export *[const]:2 TOK_k10; }\n\nk10byte_t: \"#\"TOK_k10 is TOK_B=1 & TOK_13_12_xx=0 & TOK_k10\n { export *[const]:1 TOK_k10; }\n\nk13_12_t: \"#\"TOK_13_12_kk is TOK_13_12_kk\n { export *[const]:1 TOK_13_12_kk; }\n \nk14_t: \"#\"TOK_k14 is TOK_k14\n { export *[const]:2 TOK_k14; }\n\nk15_t: \"#\"TOK_k15 is TOK_k15\n { export *[const]:2 TOK_k15; }\n \nk16_t: \"#\"TOK_k16 is TOK_k16\n { export *[const]:2 TOK_k16; }\n\nbit4_t: \"#\"bit4 is TOK_b3 & TOK_b1 [ bit4 = (TOK_b1 << 3) | TOK_b3; ] \n { export *[const]:1 bit4; }\n\nbit4byte_t: \".w\" is TOK_bit4word=1 { } #display only\n\nbit4byte_t: \".b\" is TOK_bit4word=0 { } #display only\n\nBbit4_t: \"#\"TOK_b4 is TOK_b4\n { export *[const]:1 TOK_b4; }\n\nn15_t: TOK_n15 is TOK_n15 { export *:3 TOK_n15; }\nn16_t: dest is TOK_n16 [ dest = inst_next + ( TOK_n16 << 1 ); ] { export *:3 dest; }\ndest24_t: dest is TOK_n15 ; TOK_n7 [ dest = (( TOK_n7 << 16 ) $or ( TOK_n15 << 1 )); ] { export *:3 dest; }\n\nWordInstNext: winstNext is epsilon [ winstNext = inst_next + 0; ] { export *[const]:3 winstNext; }\nWordInstNext4: winstNext is epsilon [ winstNext = inst_next + 0; ] { export *[const]:4 winstNext; }\n\nWnDest_t: TOK_3_0_Wreg is TOK_3_0_Wreg { dest:3 = zext(TOK_3_0_Wreg & 0xFFFE); export dest; }\nWnRDest_t: TOK_3_0_Wreg is TOK_3_0_Wreg { dest:3 = 2 * zext(TOK_3_0_Wreg); export dest; }\n\n\n# *2\nWsSlit10_t: \"[\"TOK_3_0_Wreg\"+\"val\"]\" is TOK_18_15_S & TOK_13_11_U & TOK_6_4_U & TOK_3_0_Wreg\n [ val = ((TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U) << 1; ]\n { tmp:2 = (TOK_3_0_Wreg + val); export *[ram]:2 tmp; } \n\nWsSlit10byte_t: \"[\"TOK_3_0_Wreg\"+\"val\"]\" is TOK_18_15_S & TOK_13_11_U & TOK_6_4_U & TOK_3_0_Wreg\n [ val = (TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U; ]\n { tmp:2 = (TOK_3_0_Wreg + val); export *[ram]:1 tmp; }\n\n# *2\nWdSlit10_t: \"[\"TOK_10_7_Wreg\"+\"val\"]\" is TOK_18_15_S & TOK_13_11_U & TOK_10_7_Wreg & TOK_6_4_U\n [ val = ((TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U) << 1; ]\n { tmp:2 = (TOK_10_7_Wreg + val); export *[ram]:2 tmp; } \n\nWdSlit10byte_t: \"[\"TOK_10_7_Wreg\"+\"val\"]\" is TOK_18_15_S & TOK_13_11_U & TOK_10_7_Wreg & TOK_6_4_U\n [ val = (TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U; ]\n { tmp:2 = (TOK_10_7_Wreg + val); export *[ram]:1 tmp; }\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\nn6_t: dest is TOK_n6 [ dest = inst_next + ( 2 * TOK_n6 ); ]\n { export *:3 dest; }\n\nk8_t: \"#\"k8 is TOK_k8b & TOK_k8a [ k8 = (TOK_k8b << 5) | TOK_k8a; ] \n { export *[const]:2 k8; }\n \nk8byte_t: \"#\"k8 is TOK_k8b & TOK_k8a [ k8 = (TOK_k8b << 5) | TOK_k8a; ] \n { export *[const]:1 k8; }\n\nWnWn1_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_14_11_Wreg\n { dest:3 = ( ( zext( TOK_14_11_Wreg & 0x007F ) << 16 ) | zext( TOK_3_0_Wreg & 0xFFFE ) ); export *:3 dest; }\n@endif\n\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\nWbsft_t: TOK_3_0_Wreg is TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nACCA_t: ACCA is TOK_A=0 & ACCA\n { export ACCA; } \n\nACCB_t: ACCB is TOK_A=1 & ACCB\n { export ACCB; }\n\n\nr4_t: \tis TOK_r4 & OP_10_7=0\n { export *[const]:1 TOK_r4; }\n\nr4_t: \",#\"TOK_r4 is TOK_r4\n { export *[const]:1 TOK_r4; }\n\nk6_t: \"#\"TOK_k6 is TOK_k6\n { export *[const]:1 TOK_k6; }\n\n\n\nWsWRO_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWsWRO_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:2 TOK_3_0_Wreg; }\n\nWsWRO_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; }\n\nWsWRO_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; }\n\nWsWRO_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWsWRO_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWsWRO_t: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\nWsWRO_t: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\n\nWdWRO_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWdWRO_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:2 TOK_3_0_Wreg; }\n\nWdWRO_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; }\n\nWdWRO_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; }\n\nWdWRO_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWdWRO_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWdWRO_t: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\nWdWRO_t: \"[\"TOK_3_0_Wreg\"+\"TOK_18_15_Wreg\"]\" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg\n { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; }\n\n\n\n\nWx_t: \",[\"W8\"],\" is TOK_9_6_iiii=0x0 & W8\n { export *[ram]:2 W8; }\n\nWx_t: \",[\"W8\"]+=2,\" is TOK_9_6_iiii=0x1 & W8\n { tmp:2 = W8; W8 = W8 + 2; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W8\"]+=4,\" is TOK_9_6_iiii=0x2 & W8\n { tmp:2 = W8; W8 = W8 + 4; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W8\"]+=6,\" is TOK_9_6_iiii=0x3 & W8\n { tmp:2 = W8; W8 = W8 + 6; export *[ram]:2 tmp; }\n\nWx_t: \"\" is TOK_9_6_iiii=0x4 # No Prefetch for X Data Space\n { tmp:2 = 0; export tmp; }\n\nWx_t: \",[\"W8\"]-=6,\" is TOK_9_6_iiii=0x5 & W8\n { tmp:2 = W8; W8 = W8 - 6; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W8\"]-=4,\" is TOK_9_6_iiii=0x6 & W8\n { tmp:2 = W8; W8 = W8 - 4; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W8\"]-=2,\" is TOK_9_6_iiii=0x7 & W8\n { tmp:2 = W8; W8 = W8 - 2; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"],\" is TOK_9_6_iiii=0x8 & W9\n { export *[ram]:2 W9; }\n\nWx_t: \",[\"W9\"]+=2,\" is TOK_9_6_iiii=0x9 & W9\n { tmp:2 = W9; W9 = W9 + 2; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"]+=4,\" is TOK_9_6_iiii=0xA & W9\n { tmp:2 = W9; W9 = W9 + 4; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"]+=6,\" is TOK_9_6_iiii=0xB & W9\n { tmp:2 = W9; W9 = W9 + 6; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"+\"W12\"],\" is TOK_9_6_iiii=0xC & W9 & W12\n { tmp:2 = (W9 + W12); export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"]-=6,\" is TOK_9_6_iiii=0xD & W9\n { tmp:2 = W9; W9 = W9 - 6; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"]-=4,\" is TOK_9_6_iiii=0xE & W9\n { tmp:2 = W9; W9 = W9 - 4; export *[ram]:2 tmp; }\n\nWx_t: \",[\"W9\"]-=2,\" is TOK_9_6_iiii=0xF & W9\n { tmp:2 = W9; W9 = W9 - 2; export *[ram]:2 tmp; }\n\n\n\nWxd_t: \",\"W4 is TOK_13_12_xx=0x0 & W4\n { export W4; }\n\nWxd_t: \",\"W5 is TOK_13_12_xx=0x1 & W5\n { export W5; }\n\nWxd_t: \",\"W6 is TOK_13_12_xx=0x2 & W6\n { export W6; }\n\nWxd_t: \",\"W7 is TOK_13_12_xx=0x3 & W7\n { export W7; }\n\n\n\nWy_t: \",[\"W10\"],\" is TOK_5_2_jjjj=0x0 & W10\n { export *[ram]:2 W10; }\n\nWy_t: \",[\"W10\"]+=2,\" is TOK_5_2_jjjj=0x1 & W10\n { tmp:2 = W10; W10 = W10 + 2; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W10\"]+=4,\" is TOK_5_2_jjjj=0x2 & W10\n { tmp:2 = W10; W10 = W10 + 4; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W10\"]+=6,\" is TOK_5_2_jjjj=0x3 & W10\n { tmp:2 = W10; W10 = W10 + 6; export *[ram]:2 tmp; }\n\nWy_t: \"\" is TOK_5_2_jjjj=0x4 # No Prefetch for Y Data Space\n { tmp:2 = 0; export tmp; }\n\nWy_t: \",[\"W10\"]-=6,\" is TOK_5_2_jjjj=0x5 & W10\n { tmp:2 = W10; W10 = W10 - 6; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W10\"]-=4,\" is TOK_5_2_jjjj=0x6 & W10\n { tmp:2 = W10; W10 = W10 - 4; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W10\"]-=2,\" is TOK_5_2_jjjj=0x7 & W10\n { tmp:2 = W10; W10 = W10 - 2; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"]\" is TOK_5_2_jjjj=0x8 & W11\n { export *[ram]:2 W11; }\n\nWy_t: \",[\"W11\"]+=2,\" is TOK_5_2_jjjj=0x9 & W11\n { tmp:2 = W11; W11 = W11 + 2; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"]+=4,\" is TOK_5_2_jjjj=0xA & W11\n { tmp:2 = W11; W11 = W11 + 4; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"]+=6,\" is TOK_5_2_jjjj=0xB & W11\n { tmp:2 = W11; W11 = W11 + 6; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"+\"W12\"],\" is TOK_5_2_jjjj=0xC & W11 & W12\n { tmp:2 = (W11 + W12); export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"]-=6,\" is TOK_5_2_jjjj=0xD & W11\n { tmp:2 = W11; W11 = W11 - 6; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"]-=4,\" is TOK_5_2_jjjj=0xE & W11\n { tmp:2 = W11; W11 = W11 - 4; export *[ram]:2 tmp; }\n\nWy_t: \",[\"W11\"]-=2,\" is TOK_5_2_jjjj=0xF & W11\n { tmp:2 = W11; W11 = W11 - 2; export *[ram]:2 tmp; }\n\n\n\nWmWm_t: W4\"*W4\" is TOK_17_16_mm=0x0 & W4\n { tmp:6 = (sext(W4) * sext(W4)); export tmp; }\n\nWmWm_t: W5\"*W5\" is TOK_17_16_mm=0x1 & W5\n { tmp:6 = (sext(W5) * sext(W5)); export tmp; }\n\nWmWm_t: W6\"*W6\" is TOK_17_16_mm=0x2 & W6\n { tmp:6 = (sext(W6) * sext(W6)); export tmp; }\n\nWmWm_t: W7\"*W7\" is TOK_17_16_mm=0x3 & W7\n { tmp:6 = (sext(W7) * sext(W7)); export tmp; }\n\n\n\nWmWn_t: W4\"*\"W5 is TOK_18_16_mmm=0x0 & W4 & W5\n { tmp:6 = (sext(W4) * sext(W5)); export tmp; }\n\nWmWn_t: W4\"*\"W6 is TOK_18_16_mmm=0x1 & W4 & W6\n { tmp:6 = (sext(W4) * sext(W6)); export tmp; }\n\nWmWn_t: W4\"*\"W7 is TOK_18_16_mmm=0x2 & W4 & W7\n { tmp:6 = (sext(W4) * sext(W7)); export tmp; }\n\nWmWn_t: \"invalid\" is TOK_18_16_mmm=0x3\n { tmp:6 = 0; export tmp; }\n\nWmWn_t: W5\"*\"W6 is TOK_18_16_mmm=0x4 & W5 & W6\n { tmp:6 = (sext(W5) * sext(W6)); export tmp; }\n\nWmWn_t: W5\"*\"W7 is TOK_18_16_mmm=0x5 & W5 & W7\n { tmp:6 = (sext(W5) * sext(W7)); export tmp; }\n\nWmWn_t: W6\"*\"W7 is TOK_18_16_mmm=0x6 & W6 & W7\n { tmp:6 = (sext(W6) * sext(W7)); export tmp; }\n\nWmWn_t: \"invalid\" is TOK_18_16_mmm=0x7\n { tmp:6 = 0; export tmp; }\n\n\n\nWyd_t: \",\"W4 is TOK_11_10_yy=0x0 & W4\n { export W4; }\n\nWyd_t: \",\"W5 is TOK_11_10_yy=0x1 & W5\n { export W5; }\n\nWyd_t: \",\"W6 is TOK_11_10_yy=0x2 & W6\n { export W6; }\n\nWyd_t: \",\"W7 is TOK_11_10_yy=0x3 & W7\n { export W7; }\n\n\nAWB_t: \",\"W13 is TOK_1_0_aa=0x0 & W13\n { export W13; }\n\nAWB_t: \",[\"W13\"]+=2\" is TOK_1_0_aa=0x1 & W13\n { tmp:2 = W13; W13 = W13 + 2; export *[ram]:2 tmp; }\n\nAWB_t: \"\" is TOK_1_0_aa=0x2 # No write back\n { tmp:2 = 0; export tmp; }\n\nAWB_t: \",invalid\" is TOK_1_0_aa=0x3 # invalid\n { tmp:2 = 0; export tmp; }\n@endif\n\n\n# Use must be constrained by $(WSconstraint)\nWsMUL_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg\n { export TOK_3_0_Wreg; }\n\nWsMUL_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { export *[ram]:2 TOK_3_0_Wreg; }\n\nWsMUL_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; }\n\nWsMUL_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; }\n\nWsMUL_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; }\n\nWsMUL_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; }\n\n\n\n# Use must be constrained by $(WDconstraint)\nWdMUL_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg\n { export TOK_10_7_Wreg; }\n\nWdMUL_t: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { export *[ram]:2 TOK_10_7_Wreg; }\n\nWdMUL_t: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 tmp; }\n\nWdMUL_t: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; }\n\nWdMUL_t: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 TOK_10_7_Wreg; }\n\nWdMUL_t: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 TOK_10_7_Wreg; }\n\n\n# Use must be constrained by $(WSconstraint)\nWsROM_t: \"[\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x1 & TOK_3_0_Wreg\n { addr:3 = (zext(TBLPAG)<<16) | zext(TOK_3_0_Wreg); export addr; }\n\nWsROM_t: \"[\"TOK_3_0_Wreg\"--]\" is TOK_6_4_U=0x2 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp - 2; export addr; }\n\nWsROM_t: \"[\"TOK_3_0_Wreg\"++]\" is TOK_6_4_U=0x3 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp + 2; export addr; }\n\nWsROM_t: \"[--\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x4 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg - 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp; export addr; }\n\nWsROM_t: \"[++\"TOK_3_0_Wreg\"]\" is TOK_6_4_U=0x5 & TOK_3_0_Wreg\n { tmp:2 = TOK_3_0_Wreg + 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp; export addr; }\n\n\n# Use must be constrained by $(WDconstraint)\nWdROM_t: \"[\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x1 & TOK_10_7_Wreg\n { addr:3 = (zext(TBLPAG)<<16) | zext(TOK_10_7_Wreg); export addr; }\n\nWdROM_t: \"[\"TOK_10_7_Wreg\"--]\" is TOK_13_11_U=0x2 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp - 2; export addr; }\n\nWdROM_t: \"[\"TOK_10_7_Wreg\"++]\" is TOK_13_11_U=0x3 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp + 2; export addr; }\n\nWdROM_t: \"[--\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x4 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg - 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp; export addr; }\n\nWdROM_t: \"[++\"TOK_10_7_Wreg\"]\" is TOK_13_11_U=0x5 & TOK_10_7_Wreg\n { tmp:2 = TOK_10_7_Wreg + 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp; export addr; }\n\n\n# Macros ==========================================================================\n\n## 16-bit working register math flag support\n\n# for decimal carry of a byte\nmacro testSRH_DCbyte(a) {\n SRH_DC = ( 0x10 & a ) != 0;\n}\n\n# for decimal carry of a word\nmacro testSRH_DCword(a) {\n SRH_DC = ( 0x100 & a ) != 0;\n}\n\n# for negative of a byte or word\nmacro testSRL_N(a) {\n SRL_N = (a s< 0);\n}\n\n# for (signed) addition of bytes or words: a + b\nmacro testSRL_OVadd(a,b) {\n SRL_OV = scarry(a,b);\n}\n\n# for (signed) addition of words with carry: a + b + c\nmacro testSRL_OVaddc(a,b,c) {\n tmp:4 \t= sext(a) + sext(b) + zext(c);\n SRL_OV \t= (tmp s< -0x00008000) || (tmp s> 0x00007FFF);\n}\n\n# for (signed) addition of bytes with carry: a + b + c\nmacro testSRL_OVaddcByte(a,b,c) {\n tmp:2 \t= sext(a) + sext(b) + zext(c);\n SRL_OV \t= (tmp s< -0x0080) || (tmp s> 0x007F);\n}\n\n# for (signed) subtraction of bytes or words: a - b\nmacro testSRL_OVsub(a,b) {\n SRL_OV = sborrow(a,b);\n}\n\n# for (signed) subtraction of words with carry: a - b - c\nmacro testSRL_OVsubc(a,b,c) {\n tmp:4 \t= sext(a) - sext(b) - zext(c);\n SRL_OV\t= (tmp s< -0x00008000) || (tmp s> 0x00007FFF);\n}\n\n# for (signed) subtraction of bytes with carry: a - b - c\nmacro testSRL_OVsubcByte(a,b,c) {\n tmp:2 \t= sext(a) - sext(b) - zext(c);\n SRL_OV \t= (tmp s< -0x0080) || (tmp s> 0x007F);\n}\n\n# for zero of a byte or word\nmacro testSRL_Z(a) {\n SRL_Z = (a == 0);\n}\n\n# for zero sticky of a byte or word\nmacro testSRL_Zsticky(a) {\n SRL_Z = SRL_Z && (a == 0);\n}\n\nmacro addflags(a,b) {\n\tSRL_C = carry(a,b);\n\tSRL_OV = scarry(a,b);\n}\n\nmacro addflagsWithCarry(a,b,c) {\n local ab = a + b;\n\tSRL_C = carry(a,b) || carry(ab,c);\n\tSRL_OV = scarry(a,b) || scarry(ab,c);\n}\n\nmacro subflags(a,b) {\n\tSRL_C = a >= b; # inverted for borrow\n\tSRL_OV = sborrow(a,b);\n}\n\nmacro subflagsWithCarry(a,b,c) {\n local bc = b + c;\n\tSRL_C = (a >= b) && (a >= bc); # inverted for borrow\n\tSRL_OV = sborrow(a,b) || sborrow(a,bc); \n}\n\n\n## 40-bit ACCA and ACCB register math flag support\n\n# for addition (signed)\nmacro testSRH_OA() {\n SRH_OA \t= ( ACCA & 0xFFFF00000000 ) != 0;\n SRH_OAB \t= SRH_OA || SRH_OB;\n}\n\n# for addition (signed)\nmacro testSRH_OB() {\n SRH_OB \t= ( ACCB & 0xFFFF00000000 ) != 0;\n SRH_OAB \t= SRH_OA || SRH_OB;\n}\n\n# for addition (signed)\n# Note: sticky bits\nmacro testSRH_SA() {\n SRH_SA\t= SRH_SA | ( ( ACCA & 0x000100000000 ) != 0 );\n SRH_SAB \t= SRH_SAB | SRH_SA;\n}\n\n# for addition (signed)\n# Note: sticky bits\nmacro testSRH_SB() {\n SRH_SB \t= SRH_SB | ( ( ACCB & 0x000100000000 ) != 0 );\n SRH_SAB \t= SRH_SAB | SRH_SB;\n}\n\n\n# 1000 0000\n@define SRH_OAbit \"0x80\"\n\n# 0100 0000\n@define SRH_OBbit \"0x40\"\n\n# 0010 0000\n@define SRH_SAbit \"0x20\"\n\n# 0001 0000\n@define SRH_SBbit \"0x10\"\n\n# 0000 1000\n@define SRH_OABbit \"0x08\"\n\n# 0000 0100\n@define SRH_SABbit \"0x04\"\n\n# 0000 0010\n@define SRH_DAbit \"0x02\"\n\n# 0000 0001\n@define SRH_DCbit \"0x01\"\n\n\n# SR component register fields (pseudo)\nmacro unpackSRH( unpackByte ) {\n SRH_OA = ( $(SRH_OAbit) & unpackByte ) != 0;\n SRH_OB = ( $(SRH_OBbit) & unpackByte ) != 0;\n SRH_SA = ( $(SRH_SAbit) & unpackByte ) != 0;\n SRH_SB = ( $(SRH_SBbit) & unpackByte ) != 0;\n SRH_OAB = ( $(SRH_OABbit) & unpackByte ) != 0;\n SRH_SAB = ( $(SRH_SABbit) & unpackByte ) != 0;\n SRH_DA = ( $(SRH_DAbit) & unpackByte ) != 0;\n SRH_DC = ( $(SRH_DCbit) & unpackByte ) != 0;\n}\n\n\nmacro packSRH( packByte ) {\n packByte = (SRH_OA * $(SRH_OAbit)) |\n (SRH_OB * $(SRH_OBbit)) |\n (SRH_SA * $(SRH_SAbit)) |\n (SRH_SB * $(SRH_SBbit)) |\n (SRH_OAB * $(SRH_OABbit)) |\n (SRH_SAB * $(SRH_SABbit)) |\n (SRH_DA * $(SRH_DAbit)) |\n (SRH_DC * $(SRH_DCbit)) ;\n}\n\n\n# 1000 0000\n@define SRL_IPL2bit \"0x80\"\n\n# 0100 0000\n@define SRL_IPL1bit \"0x40\"\n\n# 0010 0000\n@define SRL_IPL0bit \"0x20\"\n\n# 0001 0000\n@define SRL_RAbit \"0x10\"\n\n# 0000 1000\n@define SRL_Nbit \"0x08\"\n\n# 0000 0100\n@define SRL_OVbit \"0x04\"\n\n# 0000 0010\n@define SRL_Zbit \"0x02\"\n\n# 0000 0001\n@define SRL_Cbit \"0x01\"\n\n\nmacro unpackSRL( unpackByte ) {\n SRL_IPL2 = ( $(SRL_IPL2bit) & unpackByte ) != 0;\n SRL_IPL1 = ( $(SRL_IPL1bit) & unpackByte ) != 0;\n SRL_IPL0 = ( $(SRL_IPL0bit) & unpackByte ) != 0;\n SRL_RA = ( $(SRL_RAbit) & unpackByte ) != 0;\n SRL_N = ( $(SRL_Nbit) & unpackByte ) != 0;\n SRL_OV = ( $(SRL_OVbit) & unpackByte ) != 0;\n SRL_Z = ( $(SRL_Zbit) & unpackByte ) != 0;\n SRL_C = ( $(SRL_Cbit) & unpackByte ) != 0;\n}\n\n\nmacro packSRL( packByte ) {\n packByte = (SRL_IPL2 * $(SRL_IPL2bit)) |\n (SRL_IPL1 * $(SRL_IPL1bit)) |\n (SRL_IPL0 * $(SRL_IPL0bit)) |\n (SRL_RA * $(SRL_RAbit)) |\n (SRL_N * $(SRL_Nbit)) |\n (SRL_OV * $(SRL_OVbit)) |\n (SRL_Z * $(SRL_Zbit)) |\n (SRL_C * $(SRL_Cbit)) ;\n}\n\n\n# Constructors ====================================================================\n\n\n@if defined(dsPIC30) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n# The \"blockEnd\" is the flag to indicate where the goto to cause the loop must be inserted.\n# Previously an :do instruction figured out the address it needed an goto to be inserted and do something like\n# do: .... [ blockEnd=1; globalset(addressForGoto,blockEnd); ] which will cause the context bit blockEnd to be\n# set on the end of loop address.\n\n# PHASE-0 Handle end-of-loop\n\ngetDOSTART: is epsilon { export *:3 DOSTART; }\n\n:^instruction is phase=0 & blockEnd=1 & instruction & getDOSTART [ phase = 1; ] {\n\n@if defined(dsPIC30F) || defined(dsPIC33F)\n DCOUNT = DCOUNT - 1;\n if (DCOUNT != 0) goto getDOSTART;\n\n DCOUNT = DCOUNT_SHADOW;\n DOEND = DOEND_SHADOW;\n DOSTART = DOSTART_SHADOW;\n@endif\n@if defined(dsPIC33E) || defined(dsPIC33C)\n DL:2 = zext(CORCON_DL);\n *[register]:2 (&:2 DCOUNT + DL*2) = (*[register]:2 (&:2 DCOUNT + DL*2)) - 1;\t\n count:2 = *[register]:2 (&:2 DCOUNT + DL*2);\n if (count != 0) goto getDOSTART;\n\n # stack 4 levels deep but we don't enforce this\n CORCON_DL = CORCON_DL - 1;\n@endif\n\n}\n@endif\n\n:^instruction is phase=0 & instruction [ phase = 1; ] {\n build instruction;\n}\n\n# PHASE-1 Handle repeat / skip\n\n:^instruction is phase=1 & repeatInstr=1 & instruction [ phase = 2; ] {\n\n if (RCOUNT == 0) goto ;\n RCOUNT = RCOUNT - 1;\n build instruction;\n goto inst_start;\n\n}\n\n\n\n# TODO: Why is context/^instruction used instead of simply having skip instructions branch around next instruction? \n\n# skipNext global support:\n:^instruction is phase=1 & skipInstr=1 & instruction [ phase = 2; ] { \n\n if ( SkipNextFlag == 1 ) goto ;\n build instruction;\n\n}\n\n:^instruction is phase=1 & instruction [ phase = 2; ] {\n build instruction;\n}\n\n\n\nwith : phase = 2 {\n\n:add.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=0 & WREG_t & f13_t {\n\n local src = f13_t;\n addflags( src, W0 );\n\n local result = src + W0;\n WREG_t = result;\n\n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n}\n\n\n:add.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=0 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n addflags( src, W0byte );\n\n local result = src + W0byte;\n WREGbyte_t = result;\n\n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n}\n\n\n:add.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=0 & k10_t & Wn_t {\n\n local src = k10_t;\n addflags( src, Wn_t );\n\n local result = src + Wn_t;\n Wn_t = result;\n\n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:add.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=0 & k10byte_t & Wnbyte_t {\n\n local src = k10byte_t;\n addflags( src, Wnbyte_t );\n\n local result = src + Wnbyte_t;\n Wnbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n}\n\n\n:add.w Wb_t,k5_t,Wd_t is OP_23_20=0x4 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n addflags( k5_t, Wb_t );\n\n local result = k5_t + Wb_t;\n build Wd_t;\n Wd_t = result;\n\n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:add.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x4 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n addflags( k5byte_t, Wbbyte_t );\n\n local result = k5byte_t + Wbbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:add.w Wb_t,Ws_t,Wd_t is OP_23_20=0x4 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n addflags( Wb_t, src );\n \n local result = Wb_t + src;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n}\n\n:add.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x4 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n addflags( Wbbyte_t, src );\n\n local result = Wbbyte_t + src;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:add ACCA_t is OP_23_20=0xC & OP_19_16=0xB & ACCA_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n ACCA = ACCA + ACCB;\n testSRH_OA();\n testSRH_SA();\n} \n\n:add ACCB_t is OP_23_20=0xC & OP_19_16=0xB & ACCB_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n ACCB = ACCA + ACCB;\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:add WsWRO_t^r4_t,ACCA_t is OP_23_20=0xC & OP_19_16=0x9 & ACCA_t & r4_t & WsWRO_t {\n\n ACCA = (sext(WsWRO_t) << (16 - r4_t)) + ACCA;\n testSRH_OA();\n testSRH_SA();\n} \n\n:add WsWRO_t^r4_t,ACCB_t is OP_23_20=0xC & OP_19_16=0x9 & ACCB_t & r4_t & WsWRO_t {\n\n ACCB = (sext(WsWRO_t) << (16 - r4_t)) + ACCB;\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n:addc.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=1 & WREG_t & f13_t {\n\n local c:2 = zext(SRL_C);\n local src = f13_t;\n addflagsWithCarry( src, W0, c );\n\n local result = src + W0 + c;\n WREG_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n:addc.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local c = SRL_C;\n local src = f13byte_t;\n addflagsWithCarry( src, W0byte, c );\n\n local result = src + W0byte + c;\n WREGbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n}\n\n\n:addc.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=1 & k10_t & Wn_t {\n\n local c:2 = zext(SRL_C);\n addflagsWithCarry( k10_t, Wn_t, c );\n\n Wn_t = k10_t + Wn_t + c;\n\n testSRL_N ( Wn_t );\n testSRL_Zsticky( Wn_t );\n testSRH_DCword ( Wn_t );\n} \n\n\n:addc.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=1 & k10byte_t & Wnbyte_t {\n\n local c = SRL_C;\n addflagsWithCarry( k10byte_t, Wnbyte_t, c );\n\n Wnbyte_t = k10byte_t + Wnbyte_t + c;\n\n testSRL_N ( Wnbyte_t );\n testSRL_Zsticky( Wnbyte_t );\n testSRH_DCbyte ( Wnbyte_t );\n}\n\n\n:addc.w Wb_t,k5_t,Wd_t is OP_23_20=0x4 & OP_19=0x1 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n local c:2 = zext(SRL_C);\n addflagsWithCarry( k5_t, Wb_t, c );\n\n local result = k5_t + Wb_t + c;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n\n:addc.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x4 & OP_19=0x1 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n local c = SRL_C;\n addflagsWithCarry( k5byte_t, Wbbyte_t, c );\n\n local result = k5byte_t + Wbbyte_t + c;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n} \n\n\n:addc.w Wb_t,Ws_t,Wd_t is OP_23_20=0x4 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local c:2 = zext(SRL_C);\n local src = Ws_t;\n addflagsWithCarry( Wb_t, src, c );\n\n local result = Wb_t + src + c;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n\n:addc.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x4 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local c = SRL_C;\n local src = Wsbyte_t;\n addflagsWithCarry( Wbbyte_t, src, c );\n\n local result = Wbbyte_t + src + c;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n} \n\n\n:and.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=0 & WREG_t & f13_t {\n\n WREG_t = f13_t & W0;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n} \n\n\n:and.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=0 & WREGbyte_t & f13byte_t {\n\n WREGbyte_t = f13byte_t & W0byte;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n}\n\n\n:and.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=0 & k10_t & Wn_t {\n\n Wn_t = k10_t & Wn_t;\n\n testSRL_N ( Wn_t );\n testSRL_Z ( Wn_t );\n} \n\n\n:and.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=0 & k10byte_t & Wnbyte_t {\n\n Wnbyte_t = k10byte_t & Wnbyte_t;\n\n testSRL_N ( Wnbyte_t );\n testSRL_Z ( Wnbyte_t );\n}\n\n\n:and.w Wb_t,k5_t,Wd_t is OP_23_20=0x6 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n local result = k5_t & Wb_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:and.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x6 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n local result = k5byte_t & Wbbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:and.w Wb_t,Ws_t,Wd_t is OP_23_20=0x6 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local result = Wb_t & Ws_t;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:and.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x6 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local result = Wbbyte_t & Wsbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:asr.w f13_t^WREG_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=1 & WREG_t & f13_t {\n\n local src = f13_t;\n SRL_C = ( src & 1 ) != 0;\n WREG_t = src s>> 1;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n} \n\n\n:asr.b f13byte_t^WREGbyte_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n SRL_C = ( src & 1 ) != 0;\n WREGbyte_t = src s>> 1;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n}\n\n\n:asr.w Ws_t,Wd_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n \n SRL_C = ( src & 1 ) != 0;\n local result = src s>> 1;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:asr.b Wsbyte_t,Wdbyte_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n \n SRL_C = ( src & 1 ) != 0;\n local result = src s>> 1;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:asr.w Wbd_t,k4_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x1 & OP_6_4=0x4 & Wbd_t & Wnd_t & k4_t {\n\n Wnd_t = Wbd_t s>> k4_t;\n\n testSRL_N ( Wnd_t );\n testSRL_Z ( Wnd_t );\n} \n\n\n:asr.w Wbd_t,Wns_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x1 & OP_6_4=0x0 & Wbd_t & Wnd_t & Wns_t {\n\n Wnd_t = Wbd_t s>> ( Wns_t & 0x001F );\n\n testSRL_N ( Wnd_t );\n testSRL_Z ( Wnd_t );\n} \n\n\n# The pdf manual is very confusing for this instruction. The final conclusion is that the .B\n# is really a pseudo instruction and that everything is actually encoded as a word with the\n# 'f' bits being left shifted by 1\n:bclr.w f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0x9 & bit4_t & f12_t {\n\n local mask:2 = ~(1 << bit4_t);\n f12_t = f12_t & mask;\n} \n\n\n# DSRPAG ????? \n:bclr.w Wsb_t,Bbit4_t is\n OP_23_20=0xA & OP_19_16=0x1 & Bbit4_t & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = ~(1 << Bbit4_t);\n Wsb_t = Wsb_t & mask;\n} \n\n\n:bclr.b Wsbbyte_t,Bbit4_t is\n OP_23_20=0xA & OP_19_16=0x1 & Bbit4_t & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t {\n\n local mask:1 = ~(1 << Bbit4_t);\n Wsbbyte_t = Wsbbyte_t & mask;\n} \n\n\n@if defined(dsPIC33C)\n:bfext TOK_k4 \"#\"wid5, Wsb_t, Wnbf_t is\n\tOP_23_16=0x0A & OP_15_12=0x8 & Wnbf_t & TOK_k4b & TOK_k4;\n\tOP_23_16=0x0 & OP_15_8=0x0 & OP_7=0x0 & Wsb_t\n[wid5 = TOK_k4b - TOK_k4 + 1;]\n{\n local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4;\n local result:2 = (Wsb_t & mask) >> TOK_k4;\n\tWnbf_t = result;\n}\n\n:bfext TOK_k4 \"#\"wid5, n15_t, Wnbf_t is\n\tOP_23_16=0x0A & OP_15_12=0xA & Wnbf_t & TOK_k4b & TOK_k4;\n\tOP_23_16=0x0 & OP_0=0x0 & n15_t\n[wid5 = TOK_k4b - TOK_k4 + 1;]\n{\n local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4;\n local word = *:2 n15_t;\n local result:2 = (word & mask) >> TOK_k4;\n\tWnbf_t = result;\n}\n\n:bfins TOK_k4 \"#\"wid5, Wnbf_t, Wsb_t is\n\tOP_23_16=0x0A & OP_15_12=0x0 & Wnbf_t & TOK_k4b & TOK_k4;\n\tOP_23_16=0x0 & OP_15_8=0x0 & OP_7=0x0 & Wsb_t\n[wid5 = TOK_k4b - TOK_k4 + 1;]\n{\n local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4;\n local result:2 = (Wnbf_t & mask) >> TOK_k4;\n\tWsb_t = result;\n}\n\n:bfins TOK_k4 \"#\"wid5, Wnbf_t, n15_t is\n\tOP_23_16=0x0A & OP_15_12=0x2 & Wnbf_t & TOK_k4b & TOK_k4;\n\tOP_23_16=0x0 & OP_0=0x0 & n15_t\n[wid5 = TOK_k4b - TOK_k4 + 1;]\n{\n local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4;\n local result:2 = (Wnbf_t & mask) >> TOK_k4;\n\t*:2 n15_t = result;\n}\n\n\n@endif\n\n\n@if defined(dsPIC24F) || defined(dsPIC33E) || defined(dsPIC33C)\ndefine pcodeop bootswap;\n:bootswp is OP_23_0=0xFE2000 {\n bootswap();\n}\n@endif\n\n\n:bra n16_t is OP_23_20=0x3 & OP_19_16=0x7 & n16_t {\n\n goto n16_t;\n} \n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:bra Wns_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x6 & OP_11_8=0x0 & OP_7_4=0x0 & Wns_t & WordInstNext {\n\n #Note: identical operation as below, unique targets\n dest:3 = WordInstNext + 2 * sext(Wns_t);\n goto [dest];\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:bra Wns_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x6 & OP_7_4=0x0 & Wns_t {\n\n #Note: identical operation as above, unique targets\n # inst_next is byte oriented here, and word oriented inside of [ ];\n dest:3 = (inst_next/2) + 2 * sext(Wns_t);\n goto [dest];\n} \n@endif\n\n\ncond1: \"c\" is TOK_CCCC=0x1 { tmpBool:1 = SRL_C; export tmpBool; }\ncond1: \"ge\" is TOK_CCCC=0xD { tmpBool:1 = ((SRL_N && SRL_OV) || (!SRL_N && !SRL_OV)); export tmpBool; }\n#Note: same as branch C, not supported in disassembly\n# cond1: \"geu\" is TOK_CCCC=0x1 { tmpBool:1 = SRL_C ); export tmpBool; }\ncond1: \"gt\" is TOK_CCCC=0xC\n { tmpBool:1 = ((!SRL_Z && SRL_N && SRL_OV) || (!SRL_Z && !SRL_N && !SRL_OV)); export tmpBool; }\ncond1: \"gtu\" is TOK_CCCC=0xE { tmpBool:1 = SRL_C && !SRL_Z; export tmpBool; }\ncond1: \"le\" is TOK_CCCC=0x4\n { tmpBool:1 = (SRL_Z || (SRL_N != SRL_OV)); export tmpBool; }\ncond1: \"leu\" is TOK_CCCC=0x6 { tmpBool:1 = (!SRL_C || SRL_Z); export tmpBool; }\ncond1: \"lt\" is TOK_CCCC=0x5 { tmpBool:1 = ((SRL_N && !SRL_OV) || (!SRL_N && SRL_OV)); export tmpBool; }\ncond1: \"n\" is TOK_CCCC=0x3 { tmpBool:1 = (SRL_N); export tmpBool; }\ncond1: \"nc\" is TOK_CCCC=0x9 { tmpBool:1 = (!SRL_C); export tmpBool; }\ncond1: \"nn\" is TOK_CCCC=0xB { tmpBool:1 = (!SRL_N); export tmpBool; }\ncond1: \"nov\" is TOK_CCCC=0x8 { tmpBool:1 = (!SRL_OV); export tmpBool; }\ncond1: \"nz\" is TOK_CCCC=0xA { tmpBool:1 = (!SRL_Z); export tmpBool; }\ncond2: \"oa\" is TOK_CCCC=0xC { tmpBool:1 = (SRH_OA); export tmpBool; }\ncond2: \"ob\" is TOK_CCCC=0xD { tmpBool:1 = (SRH_OB); export tmpBool; }\ncond1: \"ov\" is TOK_CCCC=0x0 { tmpBool:1 = (SRL_OV); export tmpBool; }\ncond2: \"sa\" is TOK_CCCC=0xE { tmpBool:1 = (SRH_SA); export tmpBool; }\ncond2: \"sb\" is TOK_CCCC=0xF { tmpBool:1 = (SRH_SB); export tmpBool; }\ncond1: \"z\" is TOK_CCCC=0x2 { tmpBool:1 = (SRL_Z); export tmpBool; }\n\n\n\n##\n##\n##\n## conditional branch for the 16-bit status branches above\n##\n##\n##\n:bra cond1,n16_t is OP_23_20=0x3 & cond1 & n16_t {\n\n if ( cond1 ) goto n16_t;\n} \n\n\n##\n##\n##\n## conditional branch for the 40-bit status branches above\n##\n##\n##\n:bra cond2,n16_t is OP_23_20=0x0 & cond2 & n16_t {\n\n if ( cond2 ) goto n16_t;\n} \n\n\n:bset.w f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0x8 & bit4byte_t & bit4_t & f12_t {\n \n local mask:2 = 1 << bit4_t;\n f12_t = f12_t | mask;\n} \n\n\n:bset.w Wsb_t,Bbit4_t is\n OP_23_20=0xA & OP_19_16=0x0 & Bbit4_t & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = 1 << Bbit4_t;\n Wsb_t = Wsb_t | mask;\n} \n\n\n:bset.b Wsbbyte_t,Bbit4_t is\n OP_23_20=0xA & OP_19_16=0x0 & Bbit4_t & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t {\n\n local mask:1 = 1 << Bbit4_t;\n Wsbbyte_t = Wsbbyte_t | mask;\n} \n\n\n:bsw.c Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0xD & TOK_Z=0 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t {\n\n # clear the bit and or flag in; write the bit\n local bit = Wbd_t & 0xF;\n Ws_t = ( Ws_t & ~(1 << bit) ) | (zext(SRL_C) << bit);\n} \n\n\n:bsw.z Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0xD & TOK_Z=1 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t {\n\n # clear the bit and or flag in; write the bit\n local bit = Wbd_t & 0xF;\n Ws_t = ( Ws_t & ~(1 << bit) ) | (zext(SRL_Z) << bit);\n} \n\n\n:btg^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xA & bit4byte_t & bit4_t & f12_t {\n\n local mask:2 = 1 << bit4_t;\n f12_t = f12_t ^ mask;\n} \n\n\n# DSRPAG ????? \n:btg.w Wsb_t,Bbit4_t is\n OP_23_20=0xA & OP_19_16=0x2 & Bbit4_t & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = 1 << Bbit4_t;\n Wsb_t = Wsb_t ^ mask;\n} \n\n\n:btg.b Wsbbyte_t,Bbit4_t is\n OP_23_20=0xA & OP_19_16=0x2 & Bbit4_t & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t {\n\n local mask:1 = 1 << Bbit4_t;\n Wsbbyte_t = Wsbbyte_t ^ mask;\n} \n\n\n:btsc^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xF & bit4byte_t & bit4_t & f12_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n local mask:2 = 1 << bit4_t;\n SkipNextFlag = ( ( f12_t & mask ) == 0 );\n} \n\n\n:btsc.w Wsb_t,Bbit4_t is OP_23_16=0xa7 & OP_11_7=0x0 & Bbit4_t & $(WSconstraint) & Wsb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n local mask:2 = 1 << Bbit4_t;\n SkipNextFlag = ( ( Wsb_t & mask ) == 0 );\n} \n\n\n:btss^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xE & bit4byte_t & bit4_t & f12_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n local mask:2 = 1 << bit4_t;\n SkipNextFlag = ( ( f12_t & mask ) != 0 );\n} \n\n\n:btss.w Wsb_t,Bbit4_t is OP_23_16=0xa6 & OP_11_7=0x0 & Bbit4_t & $(WSconstraint) & Wsb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n local mask:2 = 1 << Bbit4_t;\n SkipNextFlag = ( ( Wsb_t & mask ) != 0 );\n} \n\n\n:btst.w f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xB & bit4byte_t & bit4_t & f12_t {\n\n local mask:2 = 1 << bit4_t;\n SRL_Z = ( ( f12_t & mask ) == 0 );\n} \n\n\n# \t\t\t\t\t\t1010 0011 1111 0000 0000 0001\n:btst.c Wsb_t,Bbit4_t is \n\t\n OP_23_16=0xa3 & OP_10_7=0x0 &\n\tBbit4_t & TOK_Zb=0 & OP_10_8=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = 1 << Bbit4_t;\n \n # set C to value of bit\n SRL_C = ( Wsb_t & mask ) != 0;\n} \n\n\n:btst.z Wsb_t,Bbit4_t is \n \n OP_23_20=0xA & OP_19_16=0x3 & Bbit4_t & TOK_Zb=1 & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = 1 << Bbit4_t;\n\n # set Z to value of bit complemented\n SRL_Z = ( Wsb_t & mask ) == 0;\n} \n\n\n:btst.c Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0x5 & TOK_Z=0 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t {\n\n # set C to value of bit\n SRL_C = ( Ws_t & (1 << (Wbd_t & 0xF)) ) != 0;\n} \n\n\n:btst.z Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0x5 & TOK_Z=1 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t {\n\n # set Z to value of bit complemented\n SRL_Z = ( Ws_t & (1 << (Wbd_t & 0xF)) ) == 0;\n} \n\n\n:btsts^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xC & bit4byte_t & bit4_t & f12_t {\n\n local mask:2 = 1 << bit4_t;\n \n # set Z to value of bit complemented\n SRL_Z = ( ( f12_t & mask ) == 0 );\n\n # set value of bit to 1\n f12_t = f12_t | mask;\n} \n\n\n# DSRPAG ????? \n:btsts.c Wsb_t,Bbit4_t is OP_23_20=0xA & OP_19_16=0x4 & Bbit4_t & TOK_Zb=0 & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = 1 << Bbit4_t;\n local wsSrc = Wsb_t;\n \n # set C to value of bit\n SRL_C = ( wsSrc & mask ) != 0;\n\n # set value of bit to 1\n Wsb_t = wsSrc | mask;\n} \n\n\n:btsts.z Wsb_t,Bbit4_t is OP_23_20=0xA & OP_19_16=0x4 & Bbit4_t & TOK_Zb=1 & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local mask:2 = 1 << Bbit4_t;\n local wsSrc = Wsb_t;\n \n # set Z to value of bit complemented\n SRL_Z = ( wsSrc & mask ) == 0;\n\n # set value of bit to 1\n Wsb_t = wsSrc | mask;\n} \n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F)\n:call dest24_t is ( OP_23_20=0x0 & OP_19_16=0x2 & OP_0=0x0 & WordInstNext4;\n OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7=0x0 ) & dest24_t {\n\n *[ram]:4 W15 = WordInstNext4;\n W15 = W15 + 4;\n\n call dest24_t;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:call dest24_t is ( OP_23_20=0x0 & OP_19_16=0x2 & OP_0=0x0;\n OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7=0x0 ) & dest24_t {\n\n *[ram]:4 W15 = (inst_next / 2) | zext(CORCON_SFA);\n W15 = W15 + 4;\n\n call dest24_t;\n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:call WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & WnDest_t & WordInstNext4 {\n\n *[ram]:4 W15 = WordInstNext4;\n W15 = W15 + 4;\n\n call [WnDest_t];\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:call WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & WnDest_t & WordInstNext4 {\n\n *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA);\n W15 = W15 + 4;\n\n call [WnDest_t];\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:call.l WnWn1_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15=0x1 & WnWn1_t & OP_10_8=0x0 & OP_7_4=0x0 & WordInstNext4 {\n\n *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA);\n W15 = W15 + 4;\n\n call [WnWn1_t];\n} \n@endif\n\n\n:clr.w f13b_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & f13b_t {\n\n f13b_t = 0;\n} \n\n\n:clr.w WREGb_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & WREGb_t {\n\n WREGb_t = 0;\n} \n\n\n:clr.b f13bbyte_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & f13bbyte_t {\n\n f13bbyte_t = 0;\n}\n\n\n:clr.b WREGbbyte_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & WREGbbyte_t {\n\n WREGbbyte_t = 0;\n}\n\n\n:clr.w Wd_t is OP_23_20=0xE & OP_19_16=0xB & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & OP_6_4=0x0 & OP_3_0=0x0 {\n\n Wd_t = 0;\n} \n\n\n:clr.b Wdbyte_t is OP_23_20=0xE & OP_19_16=0xB & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & OP_6_4=0x0 & OP_3_0=0x0 {\n\n Wdbyte_t = 0;\n} \n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n#\n# Note: The following constructors have three optional parameters, Wx, Wy and AWB. To implement them\n# without if-then-else constructs, the permutations were made. The TOK tokens correspond, in order,\n# with the elements that are removed (commented out) from the constructor when the \"no prefetch\"\n# or \"no write back\" cases occur. Corresponding sub-constructors were also removed from the display\n# section because an unused destination would otherwise be displayed (i.e. \"clr ACCAW4W4\" -> \"clr ACCA\").\n#\n\n##\n##\n## ACCA series\n##\n##\n\n:clr ACCA_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:clr ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # 0 -> ACCA\n ACCA \t\t= 0;\n SRH_OA \t= 0;\n SRH_SA \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n##\n##\n## ACCB series\n##\n##\n\n:clr ACCB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n}\n\n \n:clr ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 &\n\n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n ACCB \t\t= 0;\n SRH_OB \t= 0;\n SRH_SB \t= 0;\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n}\n@endif\n\n\n:clrwdt is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0x6 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n WDTcount = 0; # ????? formal name not documented\n WDTprescalarA = 0; # ????? formal name not documented\n WDTprescalarB = 0; # ????? formal name not documented\n}\n\n\n:com.w f13_t^WREG_t is OP_23_20=0xE & OP_19_16=0xE & OP_15=1 & WREG_t & f13_t {\n\n WREG_t = ~f13_t;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n} \n\n:com.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xE & OP_15=1 & WREGbyte_t & f13byte_t {\n\n WREGbyte_t = ~f13byte_t;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n}\n\n\n:com.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0xA & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local result = ~Ws_t;\n build Wd_t;\n Wd_t = result;\n\n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:com.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0xA & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local result = ~Wsbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:cp.w f13_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=0 & OP_13=0 & f13_t {\n\n local src = f13_t;\n subflags( src, W0 );\n\n local tmp:2 = src - W0;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCword( tmp );\n} \n\n\n:cp.b f13byte_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=0 & OP_13=0 & f13byte_t {\n\n local src = f13byte_t;\n subflags( src, W0byte );\n\n local tmp:1 = src - W0byte;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCbyte( tmp );\n}\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:cp.w Wbb_t,k5_B10_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & OP_9_8=0x0 & OP_7_5=0x3 & Wbb_t & k5_B10_t {\n\n subflags( Wbb_t, k5_B10_t );\n\n tmp:2 = Wbb_t - k5_B10_t;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCword( tmp );\n} \n\n\n:cp.b Wbbbyte_t,k5byte_B10_t is\n OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & OP_9_8=0x0 & OP_7_5=0x3 & Wbbbyte_t & k5byte_B10_t {\n\n subflags( Wbbbyte_t, k5byte_B10_t );\n\n tmp:1 = Wbbbyte_t - k5byte_B10_t;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCbyte( tmp );\n} \n@endif\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n\n:cp.w Wbb_t,k8_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=0 & OP_6_5=0x3 & Wbb_t & k8_t {\n\n subflags( Wbb_t, k8_t );\n\n tmp:2 = Wbb_t - k8_t;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCword( tmp );\n} \n\n\n:cp.b Wbbbyte_t,k8byte_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=1 & OP_6_5=0x3 & Wbbbyte_t & k8byte_t {\n\n subflags( Wbbbyte_t, k8byte_t );\n\n tmp:1 = Wbbbyte_t - k8byte_t;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCbyte( tmp );\n} \n@endif\n\n\n:cp.w Wbb_t,Wsb_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & Wbb_t & $(WSconstraint) & Wsb_t {\n\n local src = Wsb_t;\n subflags( Wbb_t, src );\n\n tmp:2 = Wbb_t - src;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCword( tmp );\n} \n\n\n:cp.b Wbbbyte_t,Wsbbyte_t is\n OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & Wbbbyte_t & $(WSconstraint) & Wsbbyte_t {\n\n local src = Wsbbyte_t;\n subflags( Wbbbyte_t, src );\n\n tmp:1 = Wbbbyte_t - src;\n\n testSRL_N ( tmp );\n testSRL_Z ( tmp );\n testSRH_DCbyte( tmp );\n} \n\n\n:cp0.w f13_t is OP_23_20=0xE & OP_19_16=0x2 & OP_15=0 & OP_13=0 & f13_t {\n\n local src = f13_t;\n local zero:2 = 0;\n subflags( src, zero );\n\n testSRL_N ( src );\n testSRL_Z ( src );\n testSRH_DCword( src );\n} \n\n\n:cp0.b f13byte_t is OP_23_20=0xE & OP_19_16=0x2 & OP_15=0 & OP_13=0 & f13byte_t {\n\n local src = f13byte_t;\n local zero:1 = 0;\n subflags( src, zero );\n\n testSRL_N ( src );\n testSRL_Z ( src );\n testSRH_DCbyte( src );\n}\n\n\n:cp0.w Wsb_t is OP_23_20=0xE & OP_19_16=0x0 & OP_15_12=0x0 & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t {\n\n local src = Wsb_t;\n local zero:2 = 0;\n subflags( src, zero );\n\n testSRL_N ( src );\n testSRL_Z ( src );\n testSRH_DCword( src );\n} \n\n\n:cp0.b Wsbbyte_t is OP_23_20=0xE & OP_19_16=0x0 & OP_15_12=0x0 & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t {\n\n local src = Wsbbyte_t;\n local zero:1 = 0;\n subflags( src, zero );\n\n testSRL_N ( src );\n testSRL_Z ( src );\n testSRH_DCbyte( src );\n} \n\n\n:cpb.w f13_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=1 & OP_13=0 & f13_t {\n\n local notCarry:2 = zext(!SRL_C);\n local src = f13_t;\n subflagsWithCarry( src, W0, notCarry );\n\n tmp:2 = src - W0 - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCword ( tmp );\n} \n\n\n:cpb.b f13byte_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=1 & OP_13=0 & f13byte_t {\n\n local notCarry = !SRL_C;\n local src = f13byte_t;\n subflagsWithCarry( src, W0byte, notCarry );\n\n tmp:1 = src - W0byte - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCbyte ( tmp );\n}\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:cpb.w Wb_t,k5_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & OP_9_8=0x0 & OP_7_5=0x3 & Wb_t & k5_t {\n\n local notCarry:2 = zext(!SRL_C);\n subflagsWithCarry( Wb_t, k5_t, notCarry );\n\n tmp:2 = Wb_t - k5_t - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCword ( tmp );\n} \n\n\n:cpb.b Wbbyte_t,k5byte_t is\n OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & OP_9_8=0x0 & OP_7_5=0x3 & Wbbyte_t & k5byte_t {\n\n local notCarry = !SRL_C;\n subflagsWithCarry( Wbbyte_t, k5byte_t, notCarry );\n\n tmp:1 = Wbbyte_t - k5byte_t - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCbyte ( tmp );\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpb.w Wbb_t,k8_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=0 & OP_6_5=0x3 & Wbb_t & k8_t {\n\n local notCarry:2 = zext(!SRL_C);\n subflagsWithCarry( Wbb_t, k8_t, notCarry );\n\n tmp:2 = Wbb_t - k8_t - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCword ( tmp );\n} \n\n\n:cpb.b Wbbbyte_t,k8byte_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=1 & OP_6_5=0x3 & Wbbbyte_t & k8byte_t {\n\n local notCarry = !SRL_C;\n subflagsWithCarry( Wbbbyte_t, k8byte_t, notCarry );\n\n tmp:1 = Wbbbyte_t - k8byte_t - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCbyte ( tmp );\n} \n@endif\n\n\n:cpb.w Wbb_t,Wsb_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & Wbb_t & $(WSconstraint) & Wsb_t {\n\n local notCarry:2 = zext(!SRL_C);\n local src = Wsb_t;\n subflagsWithCarry( Wbb_t, src, notCarry );\n \n tmp:2 = Wbb_t - src - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCword ( tmp );\n} \n\n\n:cpb.b Wbbbyte_t,Wsbbyte_t is\n OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & Wbbbyte_t & $(WSconstraint) & Wsbbyte_t {\n\n local notCarry = !SRL_C;\n local src = Wsbbyte_t;\n subflagsWithCarry( Wbbbyte_t, src, notCarry );\n\n tmp:1 = Wbbbyte_t - src - notCarry;\n\n testSRL_N ( tmp );\n testSRL_Zsticky( tmp );\n testSRH_DCbyte ( tmp );\n} \n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpbeq.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t {\n\n if (Wbb_t == Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting?\n} \n\n\n:cpbeq.b Wbbbyte_t,Wnbbyte_t,n6_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t {\n\n if (Wbbbyte_t == Wnbbyte_t) goto n6_t;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpbgt.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t {\n\n if (Wbb_t s> Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting?\n} \n\n\n:cpbgt.b Wbbbyte_t,Wnbbyte_t,n6_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t {\n\n if (Wbbbyte_t s> Wnbbyte_t) goto n6_t;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpblt.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t {\n\n if (Wbb_t s< Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting?\n} \n\n\n:cpblt.b Wbbbyte_t,Wnbbyte_t,n6_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t {\n\n if (Wbbbyte_t s< Wnbbyte_t) goto n6_t;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpbne.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t {\n\n if (Wbb_t != Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting?\n} \n\n\n:cpbne.b Wbbbyte_t,Wnbbyte_t,n6_t is OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t {\n\n if (Wbbbyte_t != Wnbbyte_t) goto n6_t;\n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:cpseq.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t == Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpseq.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t == Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpseq.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t == Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpseq.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t == Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:cpsgt.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t s> Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpsgt.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t s> Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpsgt.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t s> Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpsgt.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t s> Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:cpslt.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t s< Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpslt.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t s< Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpslt.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t s< Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpslt.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t s< Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:cpsne.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t != Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpsne.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t != Wnbbyte_t);\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:cpsne.w Wbb_t,Wnb_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbb_t != Wnb_t); # ????? what about the flags, examples show them setting?\n} \n\n\n:cpsne.b Wbbbyte_t,Wnbbyte_t is\n OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t\n [ skipInstr = 1; globalset(inst_next,skipInstr); ] {\n\n SkipNextFlag = (Wbbbyte_t != Wnbbyte_t);\n} \n@endif\n\n\n@if defined(dsPIC33E) || defined(dsPIC33C)\ndefine pcodeop contextswap;\n:ctxtswp k3_t is OP_23_4=0xFE200 & OP_3=0x0 & k3_t {\n contextswap(k3_t);\n}\n\n:ctxtswp Wndb_t is OP_23_4=0xFEF00 & Wndb_t {\n contextswap(Wndb_t);\n}\n@endif\n\n:daw.b Wnsbyte_t is OP_23_20=0xF & OP_19_16=0xD & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & Wnsbyte_t {\n\n if !( ( ( Wnsbyte_t & 0x0F ) > 0x09 ) || SRH_DC ) goto ;\n Wnsbyte_t = Wnsbyte_t + 0x06;\n \n\n if !( ( ( Wnsbyte_t & 0xF0 ) > 0x90 ) || SRL_C ) goto ;\n Wnsbyte_t = Wnsbyte_t + 0x60;\n SRL_C = 1;\n \n} \n\n\n:dec.w f13_t,^WREG_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=0 & WREG_t & f13_t {\n\n local src = f13_t;\n local one:2 = 1;\n subflags( src, one );\n\n WREG_t = src - one;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n testSRH_DCword( WREG_t );\n} \n\n\n:dec.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=0 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n local one:1 = 1;\n subflags( src, one );\n\n WREGbyte_t = src - one;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n testSRH_DCbyte( WREGbyte_t );\n}\n\n\n:dec.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local one:2 = 1;\n subflags( src, one );\n\n local result = src - one;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:dec.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n local one:1 = 1;\n subflags( src, one );\n\n local result = src - one;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:dec2.w f13_t^WREG_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=1 & WREG_t & f13_t {\n\n local src = f13_t;\n local two:2 = 2;\n subflags( src, two );\n\n WREG_t = src - two;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n testSRH_DCword( WREG_t );\n} \n\n\n:dec2.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n local two:1 = 2;\n subflags( src, two );\n\n WREGbyte_t = src - two;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n testSRH_DCbyte( WREGbyte_t );\n}\n\n\n:dec2.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local two:2 = 2;\n subflags( src, two );\n\n local result = src - two;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:dec2.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n local two:1 = 2;\n subflags( src, two );\n \n local result = src - two;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:disi k14_t is OP_23_20=0xF & OP_19_16=0xC & OP_15_14=0x0 & k14_t {\n\n DISICNT \t= k14_t;\n DISI \t\t= 1;\n} \n\n\n:repeat\" 0x11 div.sw\" TOK_10_7_Wreg,TOK_3_0_Wreg is\n OP_31_0=0x090011;\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg {\n\n # Note: this implementation is not iterative, like the actual op.\n # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support.\n local div:2 = sext(TOK_10_7_Wreg) s/ sext(TOK_3_0_Wreg);\n local rem:2 = sext(TOK_10_7_Wreg) s% sext(TOK_3_0_Wreg);\n\n W0 = zext(div:1);\n W1 = zext(rem:1);\n \n testSRL_N ( W1 );\n\n # overflow as defined in note 2\n SRL_OV = (TOK_10_7_Wreg == 0x8000) && (TOK_3_0_Wreg == 0xFFFF);\n\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n} \n\ndefine pcodeop pic30_div;\ndefine pcodeop pic30_rem;\n\n:div.sw TOK_10_7_Wreg,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg {\n local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg);\n local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg);\n\n W0 = div;\n W1 = rem;\n \n testSRL_N ( W1 );\n # overflow as defined in note 2\n SRL_OV = (TOK_10_7_Wreg == 0x8000) && (TOK_3_0_Wreg == 0xFFFF);\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\ndefine pcodeop isDivideOverflow;\n\n:repeat\" 0x11 div.sd\" TOK_10_8_Dregn,TOK_3_0_Wreg is\n OP_31_0=0x090011;\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 &\n TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg {\n\n # overflow as defined in note 2\n SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg);\n \n # Note: this implementation is not iterative, like the actual op.\n # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support.\n local div:4 = TOK_10_8_Dreg s/ sext(TOK_3_0_Wreg);\n local rem:4 = TOK_10_8_Dreg s% sext(TOK_3_0_Wreg);\n W0 = div:2;\n W1 = rem:2;\n\n testSRL_N ( W1 );\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n:div.sd TOK_10_8_Dregn,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 &\n TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg {\n\n # overflow as defined in note 2\n SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg);\n\n local div:4 = pic30_div(TOK_10_8_Dreg,TOK_3_0_Wreg);\n local rem:4 = pic30_rem(TOK_10_8_Dreg,TOK_3_0_Wreg);\n \n W0 = div:2;\n W1 = rem:2;\n\n testSRL_N ( W1 );\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n\n:repeat\" 0x11 div.uw\" TOK_10_7_Wreg,TOK_3_0_Wreg is\n OP_31_0=0x090011;\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & \n TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg {\n\n # Note: this implementation is not iterative, like the actual op.\n # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support.\n local div:2 = zext(TOK_10_7_Wreg) / zext(TOK_3_0_Wreg);\n local rem:2 = zext(TOK_10_7_Wreg) % zext(TOK_3_0_Wreg);\n\n W0 = zext(div:1);\n W1 = zext(rem:1);\n\n testSRL_N ( W1 );\n\n # overflow as defined in note 2\n SRL_OV = 0;\n\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n} \n\n:div.uw TOK_10_7_Wreg,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & \n TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg {\n local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg);\n local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg);\n\n W0 = div;\n W1 = rem;\n\n testSRL_N ( W1 );\n\n # overflow as defined in note 2\n SRL_OV = 0;\n\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n} \n\n:repeat\" 0x11 div.ud\" TOK_10_8_Dregn,TOK_3_0_Wreg is\n OP_31_0=0x090011;\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 &\n TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg {\n\n # overflow as defined in note 2\n SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg);\n \n # Note: this implementation is not iterative, like the actual op.\n # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support.\n local div:4 = TOK_10_8_Dreg / sext(TOK_3_0_Wreg);\n local rem:4 = TOK_10_8_Dreg % sext(TOK_3_0_Wreg);\n W0 = div:2;\n W1 = rem:2;\n\n testSRL_N ( W1 );\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n:div.ud TOK_10_8_Dregn,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 &\n TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg {\n\n # overflow as defined in note 2\n SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg);\n \n local div:4 = pic30_div(TOK_10_8_Dreg,TOK_3_0_Wreg);\n local rem:4 = pic30_rem(TOK_10_8_Dreg,TOK_3_0_Wreg);\n W0 = div:2;\n W1 = rem:2;\n\n\n testSRL_N ( W1 );\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:repeat\" 0x11 divf\" TOK_14_11_Wreg,TOK_3_0_Wreg is\n OP_31_0=0x090011;\n OP_23_20=0xD & OP_19_16=0x9 & OP_15=0x0 &\n TOK_14_11_Wreg & OP_10_8=0x0 & OP_7_4=0x0 & TOK_3_0_Wreg {\n\n dividend:4 \t= (sext(TOK_14_11_Wreg) << 16);\n local tmp0:4 \t\t= dividend s/ sext(TOK_3_0_Wreg);\n W0 \t\t\t= tmp0:2;\n local tmp1 \t\t\t= dividend s% sext(TOK_3_0_Wreg);\n W1 \t\t\t= tmp1:2;\n\n testSRL_N ( W1 );\n\n # overflow as defined in note 1\n SRL_OV = (TOK_14_11_Wreg s>= TOK_3_0_Wreg);\n\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n:divf TOK_14_11_Wreg,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x9 & OP_15=0x0 &\n TOK_14_11_Wreg & OP_10_8=0x0 & OP_7_4=0x0 & TOK_3_0_Wreg {\n\n # Note: this implementation is not iterative, like the actual op.\n # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support.\n local dividend:4 \t= (sext(TOK_14_11_Wreg) << 16);\n local tmp0:4 \t\t= pic30_div(dividend,TOK_3_0_Wreg);\n W0 \t\t\t= tmp0:2;\n local tmp1:4 \t\t= pic30_rem(dividend,TOK_3_0_Wreg);\n W1 \t\t\t= tmp1:2;\n\n testSRL_N ( W1 );\n\n # overflow as defined in note 1\n SRL_OV = (TOK_14_11_Wreg s>= TOK_3_0_Wreg);\n\n testSRL_Z ( W1 );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n@endif\n\n\n@if defined(dsPIC33C)\ndefine pcodeop pic30_fdiv;\ndefine pcodeop pic30_frem;\n\n:divf2 TOK_14_11_Wreg,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x9 & OP_15=0x0 &\n TOK_14_11_Wreg & OP_10_8=0x0 & OP_7_4=0x2 & TOK_3_0_Wreg & TOK_14_11_Wregn {\n\n # Note: this implementation is not iterative, like the actual op.\n # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support.\n local dividend:4 \t= (sext(TOK_14_11_Wreg) << 16);\n local tmp0:4 \t\t= pic30_fdiv(dividend,TOK_3_0_Wreg,TOK_14_11_Wregn);\n local tmp1:4 \t\t= pic30_frem(dividend,TOK_3_0_Wreg,TOK_14_11_Wregn);\n TOK_14_11_Wregn \t= tmp0:2;\n TOK_14_11_Wreg\t= tmp1:2;\n\n testSRL_N ( TOK_14_11_Wreg );\n\n # overflow as defined in note 1\n SRL_OV = (TOK_14_11_Wreg s>= TOK_3_0_Wreg);\n\n testSRL_Z ( TOK_14_11_Wreg );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\ndefine pcodeop pic30_div2;\ndefine pcodeop pic30_rem2;\n:div2.sw TOK_10_7_Wreg,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & TOK_10_7_Wreg & TOK_10_7_Wregp & TOK_W=0 & OP_5_4=0x2 & TOK_3_0_Wreg {\n local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg);\n local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg);\n\n TOK_10_7_Wreg = div;\n TOK_10_7_Wregp = rem;\n \n testSRL_N ( TOK_10_7_Wregp );\n # overflow as defined in note 2\n SRL_OV = (TOK_10_7_Wreg == 0x8000) && (TOK_3_0_Wreg == 0xFFFF);\n testSRL_Z ( TOK_10_7_Wregp );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n:div2.sd TOK_10_8_Dregn,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 &\n TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x2 & TOK_3_0_Wreg {\n\n # overflow as defined in note 2\n SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg);\n\n local div:2 = pic30_div2(TOK_10_8_Dreg,TOK_3_0_Wreg);\n local rem:2 = pic30_rem2(TOK_10_8_Dreg,TOK_3_0_Wreg);\n \n TOK_10_8_Dreg = (zext(rem) << 16) + zext(div);\n\n testSRL_N ( rem );\n testSRL_Z ( rem );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n\n:div2.uw TOK_10_7_Wreg,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & TOK_10_7_Wreg & TOK_10_7_Wregp & TOK_W=0 & OP_5_4=0x2 & TOK_3_0_Wreg {\n local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg);\n local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg);\n\n TOK_10_7_Wreg = div;\n TOK_10_7_Wregp = rem;\n \n testSRL_N ( TOK_10_7_Wregp );\n # overflow as defined in note 2\n SRL_OV = 0;\n testSRL_Z ( TOK_10_7_Wregp );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n\n:div2.ud TOK_10_8_Dregn,TOK_3_0_Wreg is\n OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 &\n TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x2 & TOK_3_0_Wreg {\n\n # overflow as defined in note 2\n SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg);\n\n local div:2 = pic30_div2(TOK_10_8_Dreg,TOK_3_0_Wreg);\n local rem:2 = pic30_rem2(TOK_10_8_Dreg,TOK_3_0_Wreg);\n \n TOK_10_8_Dreg = (zext(rem) << 16) + zext(div);\n\n testSRL_N ( rem );\n testSRL_Z ( rem );\n\n # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis\n SRL_C = 0;\n}\n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) \n:do k14_t,n16_t is OP_23_20=0x0 & OP_19_16=0x8 & OP_15_14=0x0 & k14_t ;\n OP_23_20=0x0 & OP_19_16=0x0 & n16_t & WordInstNext\n [ blockEnd=1; globalset(n16_t,blockEnd);] \n{\n DCOUNT_SHADOW = DCOUNT;\n DCOUNT = k14_t + 1;\n DOEND_SHADOW = DOEND;\n DOEND = &n16_t;\n DOSTART_SHADOW = DOSTART;\n DOSTART = WordInstNext;\n}\n@endif\n\n\n@if defined(dsPIC33E) || defined(dsPIC33C)\n:do k15_t,n16_t is OP_23_20=0x0 & OP_19_16=0x8 & OP_15=0x0 & k15_t ;\n OP_23_20=0x0 & OP_19_16=0x0 & n16_t & WordInstNext\n [ blockEnd=1; globalset(n16_t,blockEnd); ]\n{\n # stack 4 levels deep but we don't enforce this\n DL:2 = zext(CORCON_DL);\n *[register]:2 (&:2 DCOUNT + DL*2) = k15_t + 1;\n *[register]:3 (&:2 DOEND + DL*2) = &n16_t;\n *[register]:3 (&:2 DOSTART + DL*2) = WordInstNext;\n CORCON_DL = CORCON_DL + 1;\n}\n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) \n:do Wns_t,n16_t is OP_23_20=0x0 & OP_19_16=0x8 & OP_15_12=0x8 & OP_11_8=0x0 & OP_7_4=0x0 & Wns_t ;\n OP_23_20=0x0 & OP_19_16=0x0 & n16_t & WordInstNext\n [ blockEnd=1; globalset(n16_t,blockEnd); ]\n{\n DCOUNT_SHADOW = DCOUNT;\n DCOUNT = Wns_t + 1;\n DOEND_SHADOW = DOEND;\n DOEND = &n16_t;\n DOSTART_SHADOW = DOSTART;\n DOSTART = WordInstNext;\n}\n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:ed WmWm_t,ACCA_t,Wx_t,Wy_t,Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x1 &\n Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x3 {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCA\n ACCA = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx] - [Wy]) -> Wxd\n # (Wx) +/- kx -> Wx\n # (Wy) +/- ky -> Wy\n Wxd_t = Wx_t - Wy_t;\n}\n\n\n:ed WmWm_t,ACCB_t,Wx_t,Wy_t,Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x1 &\n Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x3 {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCB\n ACCB = WmWm_t;\n testSRH_OB();\n testSRH_SB();\n\n # ([Wx] - [Wy]) -> Wxd\n # (Wx) +/- kx -> Wx\n # (Wy) +/- ky -> Wy\n Wxd_t = Wx_t - Wy_t;\n}\n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:edac WmWm_t,ACCA_t,Wx_t,Wy_t,Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x1 &\n Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x2 {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wm) -> ACCA\n ACCA = ACCA + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx] - [Wy]) -> Wxd\n # (Wx) +/- kx -> Wx\n # (Wy) +/- ky -> Wy\n Wxd_t = Wx_t - Wy_t;\n}\n\n\n:edac WmWm_t,ACCB_t,Wx_t,Wy_t,Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x1 &\n Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x2 {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wm) -> ACCB\n ACCB = ACCB + WmWm_t;\n testSRH_OB();\n testSRH_SB();\n\n # ([Wx] - [Wy]) -> Wxd\n # (Wx) +/- kx -> Wx\n # (Wy) +/- ky -> Wy\n Wxd_t = Wx_t - Wy_t;\n}\n@endif\n\n\n:exch Wns_t,Wnd_t is\n OP_23_20=0xF & OP_19_16=0xD & OP_15_12=0x0 & OP_11=0x0 & Wnd_t & OP_6_4=0x0 & Wns_t {\n\n tmp:2 = Wnd_t;\n Wnd_t = Wns_t;\n Wns_t = tmp;\n}\n\n\n# OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n:fbcl Ws_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xF & OP_15_12=0x0 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n \n sign:2 \t= src & 0x8000;\n temp:2 \t= src << 1;\n shift:2 \t= 0;\n\n \n if !( (shift < 15) && ((temp & 0x8000) == sign) ) goto ;\n temp \t= temp << 1;\n shift = shift + 1;\n goto ;\n\n \n\n SRL_C = (shift == 15);\n Wnd_t = -shift;\n}\n\n# TODO: locate encoding details for FEX instruction \n# :fex\n\n:ff1l Ws_t,Wnd_t is OP_23_20=0xC & OP_19_16=0xF & OP_15_12=0x8 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t {\n\n temp:2 \t= Ws_t;\n shift:2 \t= 1;\n\n \n if !( (shift < 17) && ((temp & 0x8000) == 0) ) goto ;\n temp \t= temp << 1;\n shift = shift + 1;\n goto ;\n\n \n\n # If (Shift == Max_Shift)\n # C = 1\n # 0 (Wnd)\n # Else\n # C = 0\n # Shift (Wnd)\n #\n SRL_C = (shift == 17);\n Wnd_t = shift * zext(!SRL_C);\n}\n\n\n:ff1r Ws_t,Wnd_t is OP_23_20=0xC & OP_19_16=0xF & OP_15_12=0x0 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t {\n\n temp:2 \t= Ws_t;\n shift:2 \t= 1;\n\n \n if !( (shift < 17) && ((temp & 0x0001) == 0) ) goto ;\n temp \t= temp >> 1;\n shift = shift + 1;\n goto ;\n\n \n\n # If (Shift == Max_Shift)\n # C = 1\n # 0 (Wnd)\n # Else\n # C = 0\n # Shift (Wnd)\n #\n SRL_C = (shift == 17);\n Wnd_t = shift * zext(!SRL_C);\n}\n\n\n@if defined(dsPIC33C)\ndefine pcodeop force_data_range;\n\n:flim Wbds_t, Ws_t is OP_23_16=0xE4 & OP_15=0x0 & OP_10_7=0x0 & Wbds_t & Ws_t {\n force_data_range(Ws_t, Wbds_t);\n}\n\n:flim.v Wbds_t, Ws_t, Wnd_t is OP_23_16=0xE5 & OP_15=1 & Wnd_t & Wbds_t & Ws_t{\n Wnd_t = force_data_range(Ws_t, Wbds_t);\n}\n@endif\n\n\n:goto dest24_t is ( OP_23_20=0x0 & OP_19_16=0x4 & OP_0=0x0 ;\n OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7=0x0 ) & dest24_t {\n\n goto dest24_t;\n} \n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:goto WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & WnDest_t {\n\n goto [WnDest_t];\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:goto WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x4 & OP_7_4=0x0 & WnDest_t {\n\n goto [WnDest_t];\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:goto.l WnWn1_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15=0x1 & WnWn1_t & OP_10_8=0x4 & OP_7_4=0x0 {\n\n goto [WnWn1_t];\n} \n@endif\n\n\n:inc.w f13_t^WREG_t is OP_23_20=0xE & OP_19_16=0xC & OP_15=0 & WREG_t & f13_t {\n\n local src = f13_t;\n local one:2 = 1;\n addflags( src, one );\n\n WREG_t = src + one;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n testSRH_DCword( WREG_t );\n}\n\n\n:inc.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xC & OP_15=0 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n local one:1 = 1;\n addflags( src, one );\n\n WREGbyte_t = src + one;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n testSRH_DCbyte( WREGbyte_t );\n}\n\n\n:inc.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0x8 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local one:2 = 1;\n addflags( src, one );\n\n local result = src + one;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n:inc.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0x8 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n local one:1 = 1;\n addflags( src, one );\n\n local result = src + one;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:inc2.w f13_t^WREG_t is OP_23_16=0xEC & OP_15=1 & WREG_t & f13_t {\n\n local src = f13_t;\n local two:2 = 2;\n addflags( src, two );\n\n WREG_t = src + two;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n testSRH_DCword( WREG_t );\n}\n\n\n:inc2.b f13byte_t^WREGbyte_t is OP_23_16=0xEC & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n local two:1 = 2;\n addflags( src, two );\n\n WREGbyte_t = src + two;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n testSRH_DCbyte( WREGbyte_t );\n}\n\n\n:inc2.w Ws_t,Wd_t is OP_23_16=0xE8 & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local two:2 = 2;\n addflags( src, two );\n\n local result = src + two;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n:inc2.b Wsbyte_t,Wdbyte_t is OP_23_16=0xE8 & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n local two:1 = 2;\n addflags( src, two );\n\n local result = src + two;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:ior.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=0 & WREG_t & f13_t {\n\n WREG_t = f13_t | W0;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n}\n\n\n:ior.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=0 & WREGbyte_t & f13byte_t {\n\n WREGbyte_t = f13byte_t | W0byte;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n}\n\n\n:ior.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x3 & OP_15=0 & k10_t & Wn_t {\n\n Wn_t = k10_t | Wn_t;\n\n testSRL_N ( Wn_t );\n testSRL_Z ( Wn_t );\n} \n\n\n:ior.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x3 & OP_15=0 & k10byte_t & Wnbyte_t {\n\n Wnbyte_t = k10byte_t | Wnbyte_t;\n\n testSRL_N ( Wnbyte_t );\n testSRL_Z ( Wnbyte_t );\n}\n\n\n:ior.w Wb_t,k5_t,Wd_t is OP_23_20=0x7 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n local result = k5_t | Wb_t;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:ior.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x7 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n local result = k5byte_t | Wbbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n:ior.w Wb_t,Ws_t,Wd_t is OP_23_20=0x7 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local result = Wb_t | Ws_t;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n:ior.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x7 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local result = Wbbyte_t | Wsbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:lac WsWRO_t^r4_t,ACCA_t is OP_23_20=0xC & OP_19_16=0xA & ACCA_t & r4_t & WsWRO_t {\n\n ACCA = (sext(WsWRO_t) << (16 - r4_t));\n testSRH_OA();\n testSRH_SA();\n} \n\n:lac WsWRO_t^r4_t,ACCB_t is OP_23_20=0xC & OP_19_16=0xA & ACCB_t & r4_t & WsWRO_t {\n\n ACCB = (sext(WsWRO_t) << (16 - r4_t));\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n@if defined(dsPIC33C)\n:lac.d Wsd_t^r4_t,ACCA_t is OP_23_16=0xDB & OP_14_11=0x0 & ACCA_t & r4_t & Wsd_t {\n\n ACCA = (sext(Wsd_t) << (16 - r4_t));\n testSRH_OA();\n testSRH_SA();\n} \n\n:lac.d Wsd_t^r4_t,ACCB_t is OP_23_16=0xDB & OP_14_11=0x0 & ACCB_t & r4_t & Wsd_t {\n\n ACCB = (sext(Wsd_t) << (16 - r4_t));\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n@if defined(dsPIC33C)\nPSV_t: Ws_t is Ws_t {\n\tlocal psv_addr = (Ws_t & 0xf7 ) + (DSRPAG & 0xff) << 0xf;\n\texport *[rom]:3 psv_addr;\n}\n\nEDS_t: Wdpp_t is Wdpp_t {\n\tlocal eds_addr = (Wdpp_t & 0xf7 ) + (DSWPAG & 0xff) << 0xf;\n\texport *[rom]:2 eds_addr;\n}\n\ndefine pcodeop loadslave;\n:ldslv PSV_t, EDS_t, k13_12_t is OP_23_16=0x03 & OP_15_14=0x0 & OP_11=0 & k13_12_t & EDS_t & PSV_t {\n EDS_t = loadslave(PSV_t, k13_12_t);\n}\n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:lnk k14_t is OP_23_20=0xF & OP_19_16=0xA & OP_15_14=0x0 & k14_t & OP_0=0x0 {\n\n *[ram]:2 W15 = W14;\n W15 = W15 + 2;\n\n W14 = W15;\n W15 = W15 + k14_t;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:lnk k14_t is OP_23_20=0xF & OP_19_16=0xA & OP_15_14=0x0 & k14_t & OP_0=0x0 {\n\n *[ram]:2 W15 = W14;\n W15 = W15 + 2;\n\n W14 = W15;\n CORCON_SFA = 1;\n W15 = W15 + k14_t;\n} \n@endif\n\n\n:lsr.w f13_t^WREG_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=0 & WREG_t & f13_t {\n\n local src = f13_t;\n SRL_C = ( src & 0x0001 ) != 0;\n\n WREG_t = src >> 1;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n}\n\n\n:lsr.b f13byte_t^WREGbyte_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=0 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n SRL_C = ( src & 0x01 ) != 0;\n\n WREGbyte_t = src >> 1;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n}\n\n\n:lsr.w Ws_t,Wd_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n SRL_C = ( src & 0x0001 ) != 0;\n\n local result = src >> 1;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n} \n\n:lsr.b Wsbyte_t,Wdbyte_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n SRL_C = ( src & 0x01 ) != 0;\n\n local result = src >> 1;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( Wdbyte_t );\n testSRL_Z ( Wdbyte_t );\n} \n\n\n:lsr.w Wbd_t,k4_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x0 & OP_6_4=0x4 & Wbd_t & Wnd_t & k4_t {\n\n Wnd_t = Wbd_t >> k4_t;\n\n testSRL_N ( Wnd_t );\n testSRL_Z ( Wnd_t );\n} \n\n\n:lsr.w Wbd_t,Wns_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x0 & OP_6_4=0x0 & Wbd_t & Wnd_t & Wns_t {\n\n Wnd_t = Wbd_t >> ( Wns_t & 0x001F );\n\n testSRL_N ( Wnd_t );\n testSRL_Z ( Wnd_t );\n} \n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n##\n##\n## ACCA series\n##\n##\n\n:mac WmWn_t,ACCA_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:mac WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wn) -> ACCA\n ACCA = ACCA + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:mac WmWn_t,ACCB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:mac WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wn) -> ACCB\n ACCB = ACCB + WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n##\n##\n## ACCA series\n##\n##\n\n:mac WmWm_t,ACCA_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wm) -> ACCA\n ACCA = ACCA + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mac WmWm_t,ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wm) -> ACCA\n ACCA = ACCA + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mac WmWm_t,ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wm) -> ACCA\n ACCA = ACCA + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mac WmWm_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCA + (Wm)*(Wm) -> ACCA\n ACCA = ACCA + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:mac WmWm_t,ACCB_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wm) -> ACCB\n ACCB = ACCB + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mac WmWm_t,ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wm) -> ACCB\n ACCB = ACCB + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mac WmWm_t,ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wm) -> ACCB\n ACCB = ACCB + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mac WmWm_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # ACCB + (Wm)*(Wm) -> ACCB\n ACCB = ACCB + WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n@endif\n\n\n@if defined(dsPIC33C)\n\n:max ACCA_t is OP_23_16=0xCE & ACCA_t & OP_14_0=0x1000 {\n local val = ACCA_t - ACCB;\n ACCA_t = (ACCA)*zext(val s<= 0) + (ACCB)*zext(val s> 0);\n SRL_Z = zext(val s<= 0);\n SRL_N = 0;\n SRL_OV = 0;\n}\n\n:max ACCB_t is OP_23_16=0xCE & ACCB_t & OP_14_0=0x1000 {\n local val = ACCB_t - ACCA;\n ACCB_t = (ACCB)*zext(val s<= 0) + (ACCA)*zext(val s> 0);\n SRL_Z = zext(val s<= 0);\n SRL_N = 0;\n SRL_OV = 0;\n}\n\n\n:max.v ACCA_t, Ws_t is OP_23_16=0xCE & ACCA_t & OP_14_7=0x30 & Ws_t {\n local val = ACCA_t - ACCB;\n ACCA_t = (ACCA)*zext(val s<= 0) + (ACCB)*zext(val s> 0);\n Ws_t = (val:2)*zext(val s> 0);\n SRL_Z = zext(val s<= 0);\n SRL_N = 0;\n SRL_OV = 0;\n}\n\n:max.v ACCB_t, Ws_t is OP_23_16=0xCE & ACCB_t & OP_14_7=0x30 & Ws_t {\n local val = ACCB_t - ACCA;\n ACCB_t = (ACCB)*zext(val s<= 0) + (ACCA)*zext(val s> 0);\n Ws_t = (val:2)*zext(val s> 0);\n SRL_Z = zext(val s<= 0);\n SRL_N = 0;\n SRL_OV = 0;\n}\n\n\n:min ACCA_t is OP_23_16=0xCE & ACCA_t & OP_14_0=0x3000 {\n local val = ACCA_t - ACCB;\n ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n:min ACCB_t is OP_23_16=0xCE & ACCB_t & OP_14_0=0x3000 {\n local val = ACCB_t - ACCA;\n ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n:min.v ACCA_t, Ws_t is OP_23_16=0xCE & ACCA_t & OP_14_7=0x70 & Ws_t {\n local val = ACCA_t - ACCB;\n ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0);\n Ws_t = (val:2)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n:min.v ACCB_t, Ws_t is OP_23_16=0xCE & ACCB_t & OP_14_7=0x70 & Ws_t {\n local val = ACCB_t - ACCA;\n ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0);\n Ws_t = (val:2)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n\n:minz ACCA_t is OP_23_16=0xCE & ACCA_t & OP_14_0=0x3400 {\n if (SRL_Z == 0) goto inst_next;\n local val = ACCA_t - ACCB;\n ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n:minz ACCB_t is OP_23_16=0xCE & ACCB_t & OP_14_0=0x3400 {\n if (SRL_Z == 0) goto inst_next;\n local val = ACCB_t - ACCA;\n ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n:minz.v ACCA_t, Ws_t is OP_23_16=0xCE & ACCA_t & OP_14_7=0x78 & Ws_t {\n if (SRL_Z == 0) goto inst_next;\n local val = ACCA_t - ACCB;\n ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0);\n Ws_t = (val:2)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n\n:minz.v ACCB_t, Ws_t is OP_23_16=0xCE & ACCB_t & OP_14_7=0x78 & Ws_t {\n if (SRL_Z == 0) goto inst_next;\n local val = ACCB_t - ACCA;\n ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0);\n Ws_t = (val:2)*zext(val s< 0);\n SRL_Z = zext(val s>= 0);\n SRL_N = zext(val s< 0);\n SRL_OV = 0;\n}\n@endif\n\n\n:mov.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0xF & OP_15=1 & WREG_t & f13_t {\n\n WREG_t = f13_t;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n}\n\n\n:mov.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0xF & OP_15=1 & WREGbyte_t & f13byte_t {\n\n WREGbyte_t = f13byte_t;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n}\n\n\n:mov.w WREG_W0_t,f13_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=1 & WREG_W0_t & OP_13=1 & f13_t {\n\n f13_t = WREG_W0_t;\n}\n\n\n:mov.b WREG_W0byte_t,f13byte_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=1 & WREG_W0byte_t & OP_13=1 & f13byte_t {\n\n f13byte_t = WREG_W0byte_t;\n}\n\n\n:mov.w f15b_t,Wndb_t is OP_23_20=0x8 & OP_19=0x0 & f15b_t & Wndb_t {\n\n Wndb_t = f15b_t;\n}\n\n\n:mov.w Wns_t,f15b_t is OP_23_20=0x8 & OP_19=0x1 & f15b_t & Wns_t {\n\n f15b_t = Wns_t;\n}\n\n\n:mov.b TOK_k8c,Wndbyte_t is OP_23_20=0xB & OP_19_16=0x3 & OP_15_12=0xC & TOK_k8c & Wndbyte_t {\n\n Wndbyte_t = TOK_k8c;\n}\n\n\n:mov.w k16_t,Wndb_t is OP_23_20=0x2 & k16_t & Wndb_t {\n\n Wndb_t = k16_t;\n}\n\n\n:mov.w WsSlit10_t,Wnda_t is OP_23_20=0x9 & OP_19=0 & TOK_B=0 & WsSlit10_t & Wnda_t {\n\n Wnda_t = WsSlit10_t;\n}\n\n:mov.b WsSlit10byte_t,Wndabyte_t is OP_23_20=0x9 & OP_19=0 & TOK_B=1 & WsSlit10byte_t & Wndabyte_t {\n\n Wndabyte_t = WsSlit10byte_t;\n}\n\n\n:mov.w Wn_t,WdSlit10_t is OP_23_20=0x9 & OP_19=1 & TOK_B=0 & WdSlit10_t & Wn_t {\n\n WdSlit10_t = Wn_t;\n}\n\n:mov.b Wnbyte_t,WdSlit10byte_t is OP_23_20=0x9 & OP_19=1 & TOK_B=1 & WdSlit10byte_t & Wnbyte_t {\n\n WdSlit10byte_t = Wnbyte_t;\n}\n\n\n:mov.w movWs,movWd is OP_23_20=0x7 & OP_19=1 & TOK_B=0 & movWd & movWs {\n\n local result = movWs;\n build movWd;\n movWd = result;\n}\n\n\n:mov.b movWsbyte,movWdbyte is OP_23_20=0x7 & OP_19=1 & TOK_B=1 & movWdbyte & movWsbyte {\n\n local result = movWsbyte;\n build movWdbyte;\n movWdbyte = result;\n}\n\n\n:mov.d Wsd_t,Wndd_t is\n OP_23_20=0xB & OP_19_16=0xE & OP_15_12=0x0 & OP_11=0x0 & Wndd_t & OP_7=0x0 & $(WSconstraint) & Wsd_t {\n\n Wndd_t = Wsd_t;\n}\n\n\n:mov.d TOK_3_1_Dregn,Wdd_t is \n OP_23_20=0xb & OP_19_16=0xe & OP_15_14=0x2 & OP_6_4=0x0 & TOK_3_1_Dreg & TOK_3_1_Dregn & OP_0=0 & $(WDconstraint) & Wdd_t { \n \n\tlocal result = TOK_3_1_Dreg;\t\n\tbuild Wdd_t;\n\tWdd_t = result;\n}\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\nTOK_9_0_U_t: is TOK_9_0_U { export *[const]:2 TOK_9_0_U; }\n\n:movpag TOK_9_0_U_t,DSRPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xC & TOK_11_10_PP=0 & TOK_9_0_U_t & DSRPAG {\n DSRPAG = TOK_9_0_U_t;\n}\n\n:movpag TOK_9_0_U_t,DSWPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xC & TOK_11_10_PP=1 & TOK_9_0_U_t & DSWPAG {\n DSWPAG = TOK_9_0_U_t;\n}\n\n:movpag TOK_9_0_U_t,TBLPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xC & TOK_11_10_PP=2 & TOK_9_0_U_t & TBLPAG {\n TBLPAG = TOK_9_0_U_t:1;\n}\n\n:movpag TOK_3_0_Wreg,DSRPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xD & TOK_11_10_PP=0 & OP_9_4=0x0 & TOK_3_0_Wreg & DSRPAG {\n DSRPAG = TOK_3_0_Wreg;\n}\n:movpag TOK_3_0_Wreg,DSWPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xD & TOK_11_10_PP=1 & OP_9_4=0x0 & TOK_3_0_Wreg & DSWPAG {\n DSWPAG = TOK_3_0_Wreg;\n} \n:movpag TOK_3_0_Wreg,TBLPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xD & TOK_11_10_PP=2 & OP_9_4=0x0 & TOK_3_0_Wreg & TBLPAG {\n TBLPAG = TOK_3_0_Wreg:1;\n} \n@endif \n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n##\n##\n## ACCA series\n##\n##\n\n:movsac ACCA_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:movsac ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:movsac ACCB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:movsac ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:mpy WmWn_t,ACCA_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCA\n ACCA = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWn_t,ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCA\n ACCA = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mpy WmWn_t,ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCA\n ACCA = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCA\n ACCA = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:mpy WmWn_t,ACCB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCB\n ACCB = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWn_t,ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCB\n ACCB = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mpy WmWn_t,ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCB\n ACCB = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wn) -> ACCB\n ACCB = WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:mpy WmWm_t,ACCA_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCA\n ACCA = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWm_t,ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCA\n ACCA = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mpy WmWm_t,ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCA\n ACCA = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWm_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCA\n ACCA = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:mpy WmWm_t,ACCB_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCB\n ACCB = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWm_t,ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCB\n ACCB = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mpy WmWm_t,ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCB\n ACCB = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy WmWm_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # (Wm)*(Wm) -> ACCB\n ACCB = WmWm_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:mpy.n WmWn_t,ACCA_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCA\n ACCA = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy.n WmWn_t,ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCA\n ACCA = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mpy.n WmWn_t,ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCA\n ACCA = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy.n WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCA\n ACCA = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:mpy.n WmWn_t,ACCB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCB\n ACCB = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy.n WmWn_t,ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCB\n ACCB = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n\n\n:mpy.n WmWn_t,ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 &\n TOK_5_2_jjjj=0x4 &\n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCB\n ACCB = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n} \n\n\n:mpy.n WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t {\n\n# Note: MAC-class instruction\n\n # -(Wm)*(Wn) -> ACCB\n ACCB = -WmWn_t;\n testSRH_OA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:msc WmWn_t,ACCA_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n# AWB_t = ACCBH;\n} \n\n\n:msc WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCA - (Wm)*(Wn) -> ACCA\n ACCA = ACCA - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCB rounded -> AWB\n AWB_t = ACCBH;\n} \n\n\n##\n##\n## ACCB series\n##\n##\n\n:msc WmWn_t,ACCB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_9_6_iiii=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n# Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^Wx_t^Wxd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^Wx_t^Wxd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_5_2_jjjj=0x4 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n# Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n TOK_1_0_aa=0x2 & \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n# AWB_t = ACCAH;\n} \n\n\n:msc WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is \n OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 &\n \n Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t {\n\n# Note: MAC-class instruction\n\n # ACCB - (Wm)*(Wn) -> ACCB\n ACCB = ACCB - WmWn_t;\n testSRH_OA();\n testSRH_SA();\n\n # ([Wx]) -> Wxd\n # (Wx) +/- kx -> Wx\n Wxd_t = Wx_t;\n\n # ([Wy]) -> Wyd\n # (Wy) +/- ky -> Wy\n Wyd_t = Wy_t;\n\n # ACCA rounded -> AWB\n AWB_t = ACCAH;\n} \n@endif\n\n\n:mul.w f13_t is OP_23_16=0xbc & OP_15=0 & OP_13=0x0 & OP_14=0 & f13_t { \n\n W3W2 = zext(f13_t) * zext(W0);\n}\n:mul.b f13byte_t is OP_23_16=0xbc & OP_15=0 & OP_13=0x0 & OP_14=1 & f13byte_t { \n\n W2 = zext(f13byte_t) * zext(W0byte);\n}\n\n\n:mul.ss Wbd_t,WsMUL_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x9 & OP_15=1 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = sext(Wbd_t) * sext(WsMUL_t);\n}\n\n\n@if defined(dsPIC33E) || defined(dsPIC33C)\nA7_t: ACCA is TOK_7=0 & ACCA\n { export ACCA; }\n\nA7_t: ACCB is TOK_7=1 & ACCB\n { export ACCB; }\n\n:mul.ss Wbd_t,WsMUL_t,A7_t is OP_23_20=0xb & OP_19_16=0x9 & OP_15=1 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { \n\n A7_t = sext(Wbd_t) * sext(WsMUL_t);\n}\n@endif\n\n\n:mul.su Wbd_t,k5,Wndd_t is OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & OP_6_5=3 & k5 { \n\n Wndd_t = sext(Wbd_t) * zext(k5);\n}\n\n:mul.su Wbd_t,WsMUL_t,Wndd_t is OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = sext(Wbd_t) * zext(WsMUL_t);\n}\n\n\n@if defined(dsPIC33E) || defined(dsPIC33C)\n:mul.su Wbd_t,WsMUL_t,A7_t is\n OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { \n\n A7_t = sext(Wbd_t) * zext(WsMUL_t);\n}\n\n\n:mul.su Wbd_t,k5,A7_t is\n OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & OP_6_5=0x3 & k5 {\n \n A7_t = sext(Wbd_t) * zext(k5); \n}\n@endif\n\n\n:mul.us Wbd_t,WsMUL_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=1 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = zext(Wbd_t) * sext(WsMUL_t);\n}\n\n\n@if defined(dsPIC33E) || defined(dsPIC33C)\n:mul.us Wbd_t,WsMUL_t,A7_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=1 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { \n\n A7_t = zext(Wbd_t) * sext(WsMUL_t);\n}\n@endif\n\n\n:mul.uu Wbd_t,k5,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & OP_6_5=0x3 & k5 { \n\n Wndd_t = zext(Wbd_t) * zext(k5);\n}\n\n:mul.uu Wbd_t,WsMUL_t,Wndd_t is OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = zext(Wbd_t) * zext(WsMUL_t);\n}\n\n\n@if defined(dsPIC33E) || defined(dsPIC33C)\n:mul.uu Wbd_t,WsMUL_t,A7_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { \n\n A7_t = zext(Wbd_t) * zext(WsMUL_t);\n}\n\n\n:mul.uu Wbd_t,k5,A7_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & OP_6_5=0x3 & k5 { \n\n A7_t = zext(Wbd_t) * zext(k5);\n}\n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:mulw.ss Wbd_t,WsMUL_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x9 & OP_15=1 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = sext(Wbd_t) * sext(WsMUL_t);\n}\n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:mulw.su Wbd_t,WsMUL_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = sext(Wbd_t) * zext(WsMUL_t);\n}\n\n\n:mulw.su Wbd_t,k5_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & OP_6_5=3 & k5_t { \n\n Wndd_t = sext(Wbd_t) * zext(k5_t);\n}\n@endif\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n\n:mulw.us Wbd_t,WsMUL_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=1 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = zext(Wbd_t) * sext(WsMUL_t);\n}\n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:mulw.uu Wbd_t,WsMUL_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { \n\n Wndd_t = zext(Wbd_t) * zext(WsMUL_t);\n}\n\n\n:mulw.uu Wbd_t,k5_t,Wndd_t is\n OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & OP_6_5=3 & k5_t { \n\n Wndd_t = zext(Wbd_t) * zext(k5_t);\n}\n@endif\n\n\n:neg.w f13_t^WREG_t is OP_23_16=0xee & OP_15=0 & OP_14=0 & WREG_t & f13_t { \n\n WREG_t = -f13_t;\n\n SRH_DC = 0;\n SRL_OV = 0;\n SRL_C = 0;\n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n}\n\n:neg.b f13byte_t^WREGbyte_t is OP_23_16=0xee & OP_15=0 & OP_14=1 & WREGbyte_t & f13byte_t { \n\n WREGbyte_t = -f13byte_t;\n\n SRH_DC = 0;\n SRL_OV = 0;\n SRL_C = 0;\n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t);\t\n}\n\n\n:neg.w Ws_t,Wd_t is OP_23_16=0xea & OP_15=0 & OP_14=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { \n\n local result = -Ws_t;\n build Wd_t;\n Wd_t = result;\n \n SRH_DC = 0;\n SRL_OV = 0;\n SRL_C = 0;\n testSRL_N(result);\n testSRL_Z(result);\n}\n\n:neg.b Wsbyte_t,Wdbyte_t is OP_23_16=0xea & OP_15=0 & OP_14=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { \n\n local result = -Wsbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n SRH_DC = 0;\n SRL_OV = 0;\n SRL_C = 0;\n testSRL_N(result);\n testSRL_Z(result);\n}\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:neg ACCA_t is OP_23_20=0xC & OP_19_16=0xB & ACCA_t &\n OP_14_12=0x1 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n ACCA = -ACCA;\n testSRH_OA();\n testSRH_SA();\n} \n\n:neg ACCB_t is OP_23_20=0xC & OP_19_16=0xB & ACCB_t &\n OP_14_12=0x1 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n ACCB = -ACCB;\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n:nop is OP_23_16=0x0 { \n # No definition on purpose \n}\n\n\n#\n:nopr is OP_23_16=0xff {\n # No definition on purpose \n}\n\n\n:pop f15_t is OP_23_20=0xF & OP_19_16=0x9 & f15_t & OP_0=0x0 {\n\n W15 \t= W15 - 2;\n f15_t = *[ram]:2 W15;\n}\n\n\n:pop movWd is OP_23_20=0x7 & OP_19=0x1 & movWd & OP_14=0x0 & OP_6_4=0x4 & OP_3_0=0xF {\n\n W15 \t= W15 - 2;\n local result = *[ram]:2 W15;\n build movWd;\n movWd = result;\n}\n\n\n:pop.d Wndd_t is OP_23_20=0xB & OP_19_16=0xE & OP_15_12=0x0 & OP_11=0x0 & Wndd_t & OP_7_4=0x4 & OP_3_0=0xF {\n\n W15 = W15 - 4;\n Wndd_t = *[ram]:4 W15;\n}\n\n\n:pop.s is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0x8 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n W0 = SHADOW_W0;\n W1 = SHADOW_W1;\n W2 = SHADOW_W2;\n W3 = SHADOW_W3;\n\n SRL_C = SHADOW_SRL_C;\n SRL_Z = SHADOW_SRL_Z;\n SRL_OV = SHADOW_SRL_OV;\n SRL_N = SHADOW_SRL_N;\n SRH_DC = SHADOW_SRH_DC;\n}\n\n\n:push f15_t is OP_23_20=0xF & OP_19_16=0x8 & f15_t & OP_0=0x0 {\n\n *[ram]:2 W15 \t= f15_t;\n W15 = W15 + 2;\n}\n\n\n:push movWs is OP_23_20=0x7 & OP_19=0x1 & movWs & OP_14_12=0x1 & OP_11_8=0xF & OP_7=0x1 {\n\n *[ram]:2 W15 \t= movWs;\n W15 = W15 + 2;\n}\n\n\n:push.d TOK_3_1_Dregn is OP_23_20=0xB & OP_19_16=0xE & OP_15_12=0x9 & OP_11_8=0xF & OP_7_4=0x8 & TOK_3_1_Dreg & TOK_3_1_Dregn & OP_0=0x0 {\n\n *[ram]:4 W15 \t= TOK_3_1_Dreg;\n W15 \t\t\t= W15 + 4;\n}\n\n\n:push.s is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xA & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n SHADOW_W0 = W0;\n SHADOW_W1 = W1;\n SHADOW_W2 = W2;\n SHADOW_W3 = W3;\n\n SHADOW_SRL_C = SRL_C;\n SHADOW_SRL_Z = SRL_Z;\n SHADOW_SRL_OV = SRL_OV;\n SHADOW_SRL_N = SRL_N;\n SHADOW_SRH_DC = SRH_DC;\n}\n\n\ndefine pcodeop pwrsavOp;\n\n:pwrsav OP_0 is OP_23_1=0x7f2000 & OP_0 { \n\tpwrsavOp();\n}\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:rcall n16_t is OP_23_20=0x0 & OP_19_16=0x7 & n16_t & WordInstNext4 {\n *[ram]:4 W15 = WordInstNext4;\n W15 = W15 + 4;\n\n call n16_t;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:rcall n16_t is OP_23_20=0x0 & OP_19_16=0x7 & n16_t & WordInstNext4 {\n *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA);\n W15 = W15 + 4;\n CORCON_SFA = 0;\n\n call n16_t; \n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:rcall WnRDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x2 & OP_11_8=0x0 & OP_7_4=0x0 & WnRDest_t & WordInstNext4 {\n *[ram]:4 W15 = WordInstNext4;\n W15 = W15 + 4;\n\n call [WnRDest_t];\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:rcall WnRDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x2 & OP_7_4=0x0 & WnRDest_t & WordInstNext4 {\n *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA);\n W15 = W15 + 4;\n CORCON_SFA = 0;\n\n call [WnRDest_t]; \n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:repeat k14_t is OP_23_14=0x24 & k14_t\n\t[ repeatInstr=1; globalset(inst_next,repeatInstr); ] \n{ \n\tRCOUNT = k14_t + 1;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:repeat k15_t is OP_23_16=0x09 & OP_15=0 & k15_t\n\t[ repeatInstr=1; globalset(inst_next,repeatInstr); ] \n{\n\tRCOUNT = k15_t + 1;\n} \n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:repeat TOK_3_0_Wreg is OP_23_4=0x9800 & TOK_3_0_Wreg \n\t[ repeatInstr=1; globalset(inst_next,repeatInstr); ] \n{ \n\tRCOUNT = TOK_3_0_Wreg & 0x7FFF;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:repeat TOK_3_0_Wreg is OP_23_4=0x9800 & TOK_3_0_Wreg\n\t[ repeatInstr=1; globalset(inst_next,repeatInstr); ] \n{ \n\tRCOUNT = TOK_3_0_Wreg;\n} \n@endif\n\n\n:reset is OP_23_0=0xfe0000 {\n SRH_OA \t= 0;\n SRH_OB \t= 0;\n SRH_OAB \t= 0;\n SRH_SA \t= 0;\n SRH_SB \t= 0;\n SRH_SAB \t= 0;\n SRH_DA \t= 0;\n SRH_DC \t= 0;\n SRL_IPL2 \t= 0;\n SRL_IPL1 \t= 0;\n SRL_IPL0 \t= 0;\n SRL_RA \t= 0;\n SRL_N \t= 0;\n SRL_OV \t= 0;\n SRL_Z \t= 0;\n SRL_C \t= 0;\n CORCON_SFA = 0; \n PC \t\t= 0;\n goto [PC];\n}\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:retfie is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n tmpSRL:1 = tmp(3);\n unpackSRL( tmpSRL );\n CORCON_IPL3 = (tmp & 0x00800000) != 0;\n return [tmp & 0x7FFFFF];\n}\n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:retfie is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n tmpSRL:1 = tmp(3);\n unpackSRL( tmpSRL );\n CORCON_IPL3 = (tmp & 0x00800000) != 0;\n CORCON_SFA = (tmp & 0x1) != 0;\n return [tmp & 0x7FFFFE];\n}\n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:retlw.w k10_t,Wn_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10_t & Wn_t {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n tmpSRL:1 = tmp(3);\n unpackSRL( tmpSRL );\n CORCON_IPL3 = (tmp & 0x00800000) != 0;\n Wn_t = k10_t;\n return [tmp & 0x7FFFFF];\n} \n\n\n:retlw.b k10byte_t,Wnbyte_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10byte_t & Wnbyte_t {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n tmpSRL:1 = tmp(3);\n unpackSRL( tmpSRL );\n CORCON_IPL3 = (tmp & 0x00800000) != 0;\n Wnbyte_t = k10byte_t;\n return [tmp & 0x7FFFFF];\n}\n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:retlw.w k10_t,Wn_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10_t & Wn_t {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n tmpSRL:1 = tmp(3);\n unpackSRL( tmpSRL );\n CORCON_IPL3 = (tmp & 0x00800000) != 0;\n CORCON_SFA = (tmp & 0x1) != 0;\n Wn_t = k10_t;\n return [tmp & 0x7FFFFE];\n} \n\n\n:retlw.b k10byte_t,Wnbyte_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10byte_t & Wnbyte_t {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n tmpSRL:1 = tmp(3);\n unpackSRL( tmpSRL );\n CORCON_IPL3 = (tmp & 0x00800000) != 0;\n CORCON_SFA = \t(tmp & 0x1) != 0;\n Wnbyte_t = k10byte_t;\n return [tmp & 0x7FFFFE];\n}\n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:return is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n return [tmp & 0x7FFFFF];\n}\n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:return is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n W15 \t= W15 - 4;\n local tmp \t= *[ram]:4 W15;\n CORCON_SFA = ( tmp & 0x0001 ) != 0;\n tmp = tmp & 0x7FFFFE;\n return [tmp];\n}\n@endif\n\n\n:rlc.w f13_t^WREG_t is OP_23_16=0xd6 & OP_15=1 & WREG_t & f13_t { \n\n local src = f13_t;\n WREG_t = ( src << 1 ) | zext(SRL_C);\n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n SRL_C = ( src & 0x8000 ) != 0; \t\n}\n\n:rlc.b f13byte_t^WREGbyte_t is OP_23_16=0xd6 & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n WREGbyte_t = ( src << 1 ) | SRL_C;\n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t);\n SRL_C = ( src & 0x80 ) != 0; \t\n}\n\n\n:rlc.w Ws_t,Wd_t is OP_23_16=0xd2 & OP_15=1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n \n local src = Ws_t;\n local result = (src << 1) | zext(SRL_C);\n build Wd_t;\n Wd_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n SRL_C = (src & 0x8000) != 0; \n}\n\n\n:rlc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd2 & OP_15=1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { \n \n local src = Wsbyte_t;\n local result = (src << 1) | SRL_C;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n SRL_C = (src & 0x80) != 0; \n}\n\n\n:rlnc.w f13_t^WREG_t is OP_23_16=0xd6 & OP_15=0 & WREG_t & f13_t { \n\n local src = f13_t;\n WREG_t = (src << 1) | ((src & 0x8000) >> 15);\n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n}\n:rlnc.b f13byte_t^WREGbyte_t is OP_23_16=0xd6 & OP_15=0 & WREGbyte_t & f13byte_t { \n\n local src = f13byte_t;\n WREGbyte_t = (src << 1) | ((src & 0x80) >> 7);\n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t);\n}\n\n\n:rlnc.w Ws_t,Wd_t is OP_23_16=0xd2 & OP_15=0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local result = (src << 1) | ((src & 0x8000) >> 15);\n build Wd_t;\n Wd_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n}\n\n:rlnc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd2 & OP_15=0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n local result = (src << 1) | ((src & 0x80) >> 7);\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n}\n\n\n:rrc.w f13_t^WREG_t is OP_23_16=0xd7 & OP_15=1 & WREG_t & f13_t { \n\n local src = f13_t;\n WREG_t \t= ((zext(SRL_C)) * 0x8000) | (src >> 1);\n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n SRL_C \t= (src & 1) != 0; \n}\n\n\n:rrc.b f13byte_t^WREGbyte_t is OP_23_16=0xd7 & OP_15=1 & WREGbyte_t & f13byte_t {\n \n local src = f13byte_t;\n WREGbyte_t \t= (SRL_C * 0x80) | (src >> 1) ;\n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t);\n SRL_C \t= (src & 1) != 0; \n}\n\n\n:rrc.w Ws_t,Wd_t is OP_23_16=0xd3 & OP_15=1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local result = ((zext(SRL_C)) * 0x8000) | (src >> 1);\n build Wd_t;\n Wd_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n SRL_C = (src & 1) != 0; \n}\n\n\n:rrc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd3 & OP_15=1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { \n\n local src = Wsbyte_t;\n local result = (SRL_C * 0x80) | (src >> 1);\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n SRL_C = (src & 1) != 0; \n}\n\n\n:rrnc.w f13_t^WREG_t is OP_23_16=0xd7 & OP_15=0 & TOK_B=0 & WREG_t & f13_t { \n\n local src = f13_t;\n WREG_t = (src >> 1) | ((src & 1) * 0x8000); \n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n}\n\n\n:rrnc.b f13byte_t^WREGbyte_t is OP_23_16=0xd7 & OP_15=0 & TOK_B=1 & WREGbyte_t & f13byte_t {\n \n local src = f13byte_t;\n WREGbyte_t = (src >> 1) | ((src & 1) * 0x80); \n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t);\n}\n\n\n:rrnc.w Ws_t,Wd_t is OP_23_16=0xd3 & OP_15=0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n local result = (src >> 1) | ((src & 1) * 0x8000); \n build Wd_t;\n Wd_t = result;\n \n testSRL_N(Wd_t);\n testSRL_Z(Wd_t);\n}\n\n\n:rrnc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd3 & OP_15=0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { \n\n local src = Wsbyte_t;\n local result = (src >> 1) | ((src & 1) * 0x80); \n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n}\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:sac ACCA_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xC & ACCA_t & r4_t & WdWRO_t {\n\n local tmp:6 \t= ACCA s>> (16 + r4_t);\n WdWRO_t \t= tmp:2;\n} \n\n:sac ACCB_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xC & ACCB_t & r4_t & WdWRO_t {\n\n local tmp:6 \t= ACCB s>> (16 + r4_t);\n WdWRO_t \t= tmp:2;\n} \n@endif\n\n\n@if defined(dsPIC33C)\n:sac.d ACCA_t^r4_t,Wsnd_t is OP_23_16=0xDC & OP_14=0x0 & OP_7_4=0x0 & ACCA_t & r4_t & Wsnd_t {\n\n local tmp:6 \t= ACCA s>> (16 + r4_t);\n Wsnd_t \t= tmp:4;\n} \n\n:sac.d ACCB_t^r4_t,Wsnd_t is OP_23_16=0xDC & OP_14=0x0 & OP_7_4=0x0 & ACCB_t & r4_t & Wsnd_t {\n\n local tmp:6 \t= ACCB s>> (16 + r4_t);\n Wsnd_t \t= tmp:4;\n}\n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:sac.r ACCA_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xD & ACCA_t & r4_t & WdWRO_t {\n\n local tmp:6 \t= ( ACCA + (0x80000000 >> (16 - r4_t)) ) s>> (16 + r4_t);\n WdWRO_t \t= tmp:2;\n} \n\n:sac.r ACCB_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xD & ACCB_t & r4_t & WdWRO_t {\n\n local tmp:6 \t= ( ACCB + (0x80000000 >> (16 - r4_t)) ) s>> (16 + r4_t);\n WdWRO_t \t= tmp:2;\n} \n@endif\n\n\n:se Ws_t,Wnd_t is OP_23_11=0x1f60 & Wnd_t & $(WSconstraint) & Ws_t { \n\n Wnd_t = sext(Ws_t:1);\n testSRL_N(Wnd_t);\n testSRL_Z(Wnd_t);\n SRL_C = !SRL_N;\n}\n\n\n:setm.w f13_t^WREG_t is OP_23_16=0xef & OP_15=1 & WREG_t & f13_t {\n\n WREG_t = 0xFFFF; \n}\n\n:setm.b f13byte_t^WREGbyte_t is OP_23_16=0xef & OP_15=1 & WREGbyte_t & f13byte_t {\n\n WREGbyte_t = 0xFF; \n}\n\n\n:setm.w Wd_t is OP_23_16=0xeb & OP_15=1 & OP_6_0=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t {\n \n Wd_t = 0xFFFF;\n}\n\n\n:setm.b Wdbyte_t is OP_23_16=0xeb & OP_15=1 & OP_6_0=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t { \n\n Wdbyte_t = 0xFF;\n}\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:sftac ACCA_t,k6_t is\n OP_23_20=0xC & OP_19_16=0x8 & ACCA_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_6=0x1 & k6_t {\n\n local tmp:8 = (sext(ACCA) << (16 - k6_t)) >> 16;\n ACCA \t= tmp:6;\n testSRH_OA();\n testSRH_SA();\n} \n\n:sftac ACCB_t,k6_t is\n OP_23_20=0xC & OP_19_16=0x8 & ACCB_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_6=0x1 & k6_t {\n\n local tmp:8 = (sext(ACCB) << (16 - k6_t)) >> 16;\n ACCB \t= tmp:6;\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:sftac ACCA_t,Wbsft_t is\n OP_23_20=0xC & OP_19_16=0x8 & ACCA_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & Wbsft_t {\n\n local tmp:8 = (sext(ACCA) << (16 - Wbsft_t)) >> 16;\n ACCA \t= tmp:6;\n testSRH_OA();\n testSRH_SA();\n} \n\n:sftac ACCB_t,Wbsft_t is\n OP_23_20=0xC & OP_19_16=0x8 & ACCB_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & Wbsft_t {\n\n local tmp:8 = (sext(ACCB) << (16 - Wbsft_t)) >> 16;\n ACCB \t= tmp:6;\n testSRH_OB();\n testSRH_SB();\n} \n@endif\n\n\n:sl.w f13_t^WREG_t is OP_23_20=0xD & OP_19_16=0x4 & OP_15=0x0 & WREG_t & f13_t { \n\n local src = f13_t;\n WREG_t = src << 1;\n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n SRL_C = ((src & 0x8000) != 0);\n}\n\n\n:sl.b f13byte_t^WREGbyte_t is OP_23_20=0xD & OP_19_16=0x4 & OP_15=0x0 & WREGbyte_t & f13byte_t { \n\n local src = f13byte_t;\n WREGbyte_t = src << 1;\n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t);\n SRL_C = ((src & 0x80) != 0);\n}\n\n\n:sl.w Ws_t,Wd_t is OP_23_20=0xD & OP_19_16=0x0 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { \n\n local src = Ws_t;\n local result \t= src << 1;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n SRL_C = ((src & 0x8000) != 0);\n}\n\n:sl.b Wsbyte_t,Wdbyte_t is OP_23_20=0xD & OP_19_16=0x0 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n local result = src << 1;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n SRL_C = ((src & 0x80) != 0);\n}\n\n\n:sl Wbd_t,k4_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xD & OP_15=0x0 & Wbd_t & Wnd_t & OP_6_4=0x4 & k4_t {\n \n Wnd_t = Wbd_t << k4_t;\n testSRL_N(Wnd_t);\n testSRL_Z(Wnd_t);\n}\n\n\n:sl Wbd_t,Wns_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xD & OP_15=0x0 & Wbd_t & Wnd_t & OP_6_4=0x0 & Wns_t { \n\n Wnd_t = Wbd_t << (Wns_t & 0x1F);\n testSRL_N(Wnd_t);\n testSRL_Z(Wnd_t);\n}\n\n# SSTEP - ICD instruction compatible with Microchips ICD debugging hardware\n# TODO: locate encoding details for SSTEP instruction \n# define pcodeop sstep;\n# :sstep is OP_23_0=?? {\n#\tsstep(); # In-Circuit Debugger (ICD) Single Step\n# }\n\n:sub.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=0 & WREG_t & f13_t {\n\n local src = f13_t;\n subflags( src, W0 );\n\n WREG_t = src - W0;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n testSRH_DCword( WREG_t );\n}\n\n\n:sub.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=0 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n subflags( src, W0byte );\n\n WREGbyte_t = src - W0byte;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n testSRH_DCbyte( WREGbyte_t );\n}\n\n\n:sub.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=0 & k10_t & Wn_t {\n\n subflags( Wn_t, k10_t );\n\n Wn_t = Wn_t - k10_t;\n\n testSRL_N ( Wn_t );\n testSRL_Z ( Wn_t );\n testSRH_DCword( Wn_t );\n} \n\n\n:sub.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=0 & k10byte_t & Wnbyte_t {\n\n subflags( Wnbyte_t, k10byte_t );\n\n Wnbyte_t = Wnbyte_t - k10byte_t;\n\n testSRL_N ( Wnbyte_t );\n testSRL_Z ( Wnbyte_t );\n testSRH_DCbyte( Wnbyte_t );\n}\n\n\n:sub.w Wb_t,k5_t,Wd_t is OP_23_20=0x5 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n subflags( Wb_t, k5_t );\n\n local result = Wb_t - k5_t;\n build Wd_t;\n Wd_t = result;\n\n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:sub.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x5 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n subflags( Wbbyte_t, k5byte_t );\n\n local result = Wbbyte_t - k5byte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:sub.w Wb_t,Ws_t,Wd_t is OP_23_20=0x5 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t; \n subflags( Wb_t, src );\n\n local result = Wb_t - src;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:sub.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x5 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n subflags( Wbbyte_t, src );\n\n local result = Wbbyte_t - src;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C)\n:sub ACCA_t is\n OP_23_20=0xC & OP_19_16=0xB & ACCA_t & OP_14_12=0x3 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n ACCA = ACCB - ACCA;\n testSRH_OA();\n testSRH_SA();\n} \n\n:sub ACCB_t is\n OP_23_20=0xC & OP_19_16=0xB & ACCB_t & OP_14_12=0x3 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n ACCB = ACCA - ACCB;\n testSRH_OB();\n testSRH_SB();\n}\n@endif\n\n\n:subb.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=1 & WREG_t & f13_t {\n\n local notCarry:2 = zext(!SRL_C);\n subflagsWithCarry( f13_t, W0, notCarry );\n\n WREG_t = f13_t - W0 - notCarry;\n\n testSRL_N ( WREG_t );\n testSRL_Zsticky( WREG_t );\n testSRH_DCword ( WREG_t );\n} \n\n:subb.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local notCarry = !SRL_C;\n subflagsWithCarry( f13byte_t, W0byte, notCarry );\n\n WREGbyte_t = f13byte_t - W0byte - notCarry;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Zsticky( WREGbyte_t );\n testSRH_DCbyte ( WREGbyte_t );\n}\n\n\n:subb.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=1 & k10_t & Wn_t {\n\n local notCarry:2 = zext(!SRL_C);\n subflagsWithCarry( Wn_t, k10_t, notCarry );\n\n Wn_t = Wn_t - k10_t - notCarry;\n\n testSRL_N ( Wn_t );\n testSRL_Zsticky( Wn_t );\n testSRH_DCword ( Wn_t );\n} \n\n\n:subb.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=1 & k10byte_t & Wnbyte_t {\n\n local notCarry = !SRL_C;\n subflagsWithCarry( Wnbyte_t, k10byte_t, notCarry );\n\n Wnbyte_t = Wnbyte_t - k10byte_t - notCarry;\n\n testSRL_N ( Wnbyte_t );\n testSRL_Zsticky( Wnbyte_t );\n testSRH_DCbyte ( Wnbyte_t );\n}\n\n\n:subb.w Wb_t,k5_t,Wd_t is OP_23_20=0x5 & OP_19=0x1 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n local notCarry:2 = zext(!SRL_C);\n subflagsWithCarry( Wb_t, k5_t, notCarry );\n\n local result = Wb_t - k5_t - notCarry;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n:subb.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x5 & OP_19=0x1 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n local notCarry = !SRL_C;\n subflagsWithCarry( Wbbyte_t, k5byte_t, notCarry );\n\n local result = Wbbyte_t - k5byte_t - notCarry;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n} \n\n\n:subb.w Wb_t,Ws_t,Wd_t is OP_23_20=0x5 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local notCarry:2 = zext(!SRL_C);\n local src = Ws_t;\n subflagsWithCarry( Wb_t, src, notCarry );\n\n local result = Wb_t - src - notCarry;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n\n:subb.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x5 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local notCarry = !SRL_C;\n local src = Wsbyte_t;\n subflagsWithCarry( Wbbyte_t, src, notCarry );\n\n local result = Wbbyte_t - src - notCarry;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n} \n\n\n:subbr.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=1 & WREG_t & f13_t {\n\n local notCarry:2 = zext(!SRL_C);\n local src = f13_t;\n subflagsWithCarry( W0, src, notCarry );\n\n WREG_t = W0 - src - notCarry;\n\n testSRL_N ( WREG_t );\n testSRL_Zsticky( WREG_t );\n testSRH_DCword ( WREG_t );\n} \n\n:subbr.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=1 & WREGbyte_t & f13byte_t {\n\n local notCarry = !SRL_C;\n local src = f13byte_t;\n subflagsWithCarry( W0byte, src, notCarry );\n\n WREGbyte_t = W0byte - src - notCarry;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Zsticky( WREGbyte_t );\n testSRH_DCbyte ( WREGbyte_t );\n}\n\n\n:subbr.w Wb_t,k5_t,Wd_t is OP_23_20=0x1 & OP_19=0x1 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n local notCarry:2 = zext(!SRL_C);\n subflagsWithCarry( k5_t, Wb_t, notCarry );\n\n local result = k5_t - Wb_t - notCarry;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n\n:subbr.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x1 & OP_19=0x1 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n local notCarry = !SRL_C;\n subflagsWithCarry( k5byte_t, Wbbyte_t, notCarry );\n\n local result = k5byte_t - Wbbyte_t - notCarry;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n} \n\n\n:subbr.w Wb_t,Ws_t,Wd_t is OP_23_20=0x1 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local notCarry:2 = zext(!SRL_C);\n local src = Ws_t;\n subflagsWithCarry( src, Wb_t, notCarry );\n\n local result = src - Wb_t - notCarry;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCword ( result );\n} \n\n\n:subbr.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x1 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local notCarry = !SRL_C;\n local src = Wsbyte_t;\n subflagsWithCarry( src, Wbbyte_t, notCarry );\n\n local result = src - Wbbyte_t - notCarry;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Zsticky( result );\n testSRH_DCbyte ( result );\n} \n\n\n:subr.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=0 & WREG_t & f13_t {\n\n local src = f13_t;\n subflags( W0, src );\n\n WREG_t = W0 - src;\n\n testSRL_N ( WREG_t );\n testSRL_Z ( WREG_t );\n testSRH_DCword( WREG_t );\n}\n\n\n:subr.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=0 & WREGbyte_t & f13byte_t {\n\n local src = f13byte_t;\n subflags( W0byte, src );\n\n WREGbyte_t = W0byte - src;\n\n testSRL_N ( WREGbyte_t );\n testSRL_Z ( WREGbyte_t );\n testSRH_DCbyte( WREGbyte_t );\n}\n\n\n:subr.w Wb_t,k5_t,Wd_t is OP_23_20=0x1 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t {\n\n subflags( k5_t, Wb_t );\n\n local result = k5_t - Wb_t;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:subr.b Wbbyte_t,k5byte_t,Wdbyte_t is\n OP_23_20=0x1 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t {\n\n subflags( k5byte_t, Wbbyte_t );\n\n local result = k5byte_t - Wbbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:subr.w Wb_t,Ws_t,Wd_t is OP_23_20=0x1 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n\n local src = Ws_t;\n subflags( src, Wb_t );\n\n local result = src - Wb_t;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCword( result );\n} \n\n\n:subr.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x1 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local src = Wsbyte_t;\n subflags( src, Wbbyte_t );\n\n local result = src - Wbbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N ( result );\n testSRL_Z ( result );\n testSRH_DCbyte( result );\n} \n\n\n:swap.w Wn_t is OP_23_20=0xF & OP_19_16=0xD & OP_15=1 & OP_13_4=0x0 & TOK_B=0 & Wn_t {\n\n Wn_t = ((Wn_t & 0xFF) << 8) | ((Wn_t & 0xFF00) >> 8);\n}\n\n\n:swap.b Wnbyte_t is OP_23_20=0xF & OP_19_16=0xD & OP_15=1 & OP_13_4=0x0 & TOK_B=1 & Wnbyte_t {\n\n Wnbyte_t = ((Wnbyte_t & 0xF) << 4) | ((Wnbyte_t & 0xF0) >> 4); \n}\n\n\n# constructor Encoding: 1011 1010 1Bqq qddd dppp ssss \n:tblrdh.w WsROM_t,Wd_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & WsROM_t {\n \n local src = WsROM_t;\n local result\t= zext( *[rom]:1 (src | 1) );\n build Wd_t;\n Wd_t = result;\n}\n\n:tblrdh.b WsROM_t,Wdbyte_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & WsROM_t { \n\n local src = WsROM_t;\n local result:1 = 0;\n \n if ( (src & 0x1) != 0) goto ;\n result = *[rom]:1 (src | 1);\n \n\n build Wdbyte_t;\n Wdbyte_t = result;\n}\n\n\n# constructor Encoding: 1011 1010 0Bqq qddd dppp ssss \n:tblrdl.w WsROM_t,Wd_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & WsROM_t { \n local src = WsROM_t;\n local result\t= *[rom]:2 (src & 0xfffffe);\n build Wd_t;\n Wd_t = result;\n}\n\n:tblrdl.b WsROM_t,Wdbyte_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & WsROM_t { \n local src = WsROM_t;\n local lbit = src & 1;\n local val = *[rom]:2 (src & 0xfffffe);\n if (lbit == 0) goto ;\n val = val >> 8;\n \n local result = val:1;\n build Wdbyte_t;\n Wdbyte_t = result;\n}\n\n\n:tblwth.w Ws_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=1 & TOK_B=0 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Ws_t {\n \n local src = Ws_t;\n local addr = WdROM_t | 1; # add 1, should be word alligned\n # writing to upper byte PM<23:16>, can't write to padding byte\n *[rom]:1 addr = src;\n}\n\n:tblwth.b Wsbyte_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=1 & TOK_B=1 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Wsbyte_t { \n\n local src = Wsbyte_t;\n local addr = WdROM_t;\n local lbit = addr & 1;\n \n if ( lbit != 0) goto ;\n addr = addr | 1;\n *[rom]:1 addr = src;\n\n \n}\n\n\n:tblwtl.w Ws_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=0 & TOK_B=0 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Ws_t {\n \n local src = Ws_t;\n local addr = WdROM_t & 0xfffffe;\n *[rom]:2 addr = src;\n}\n\n:tblwtl.b Wsbyte_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=0 & TOK_B=1 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Wsbyte_t { \n\n local src = zext(Wsbyte_t);\n local addr = WdROM_t;\n local lobit = addr & 1;\n local val = *[rom]:2 addr;\n local mask = 0xff00;\n # if dest is not word aligned, then write to PM<15:7>\n if (lobit == 0) goto ;\n mask = mask >> 8; # writing to second byte of word, protect low byte\n src = src << 8;\n \n *[rom]:2 addr = (val & mask) | src;\n}\n\n\n@if defined(dsPIC30F) || defined(dsPIC33F) \ndefine pcodeop Vector;\n\n:trap TOK_n,TOK_k16t is OP_23_20=0 & OP_19_17=5 & TOK_n & TOK_k16t & WordInstNext4 {\n *[ram]:4 W15 = WordInstNext4;\n W15 = W15 + 4;\n\n *[ram]:2 W15 \t= TOK_k16t;\n \n ptr:3 = Vector(TOK_n:1); # uncertain about vector storage\n \n call [ptr];\n} \n@endif\n\n\n@if defined(dsPIC33C)\ndefine pcodeop verifyslave;\n:vfslv PSV_t, EDS_t, k13_12_t is OP_23_16=0x03 & OP_15_14=0x2 & OP_11=0 & k13_12_t & EDS_t & PSV_t {\n verifyslave(PSV_t, EDS_t, k13_12_t);\n}\n@endif\n\n\n@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) \n:ulnk is OP_23_20=0xF & OP_19_16=0xA & OP_15_12=0x08 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n W15 = W14;\n W15 = W15 - 2;\n\n W14 = *[ram]:2 W15;\n} \n@endif\n\n\n@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C)\n:ulnk is OP_23_20=0xF & OP_19_16=0xA & OP_15_12=0x08 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 {\n\n W15 \t= W14;\n W15 \t= W15 - 2;\n\n W14 \t= *[ram]:2 W15;\n CORCON_SFA = 0;\n} \n@endif\n\n# URUN - ICD instruction compatible with Microchips ICD debugging hardware\ndefine pcodeop urun;\n:urun is OP_23_0=0xDAC000 {\n\turun(); # In-Circuit Debugger (ICD) Run\n}\n\n:xor.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=1 & WREG_t & f13_t { \n\n WREG_t = W0 ^ f13_t; \n testSRL_N(WREG_t);\n testSRL_Z(WREG_t);\n}\n\n:xor.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=1 & WREGbyte_t & f13byte_t {\n\n WREGbyte_t = W0byte ^ f13byte_t;\n testSRL_N(WREGbyte_t);\n testSRL_Z(WREGbyte_t); \n}\n\n\n:xor.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=1 & k10_t & Wn_t {\n \n Wn_t = Wn_t ^ k10_t;\n testSRL_N(Wn_t);\n testSRL_Z(Wn_t);\n}\n\n:xor.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=1 & k10byte_t & Wnbyte_t {\n\n Wnbyte_t = Wnbyte_t ^ k10byte_t;\n testSRL_N(Wnbyte_t);\n testSRL_Z(Wnbyte_t);\n}\n\n\n:xor.w Wb_t,k5_t,Wd_t is OP_23_20=0x6 & OP_19=0x1 & Wb_t & $(WDconstraint) & Wd_t & OP_6_5=0x3 & k5_t {\n \n Wd_t = Wb_t ^ k5_t;\n testSRL_N(Wd_t);\n testSRL_Z(Wd_t);\n}\n\n:xor.b Wbbyte_t,k5byte_t,Wdbyte_t is OP_23_20=0x6 & OP_19=0x1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & OP_6_5=0x3 & k5byte_t { \n\n Wdbyte_t = Wbbyte_t ^ k5byte_t;\n testSRL_N(Wdbyte_t);\n testSRL_Z(Wdbyte_t);\n}\n\n\n:xor.w Wb_t,Ws_t,Wd_t is OP_23_20=0x6 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t {\n \n local result = Wb_t ^ Ws_t;\n build Wd_t;\n Wd_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n}\n\n:xor.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x6 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t {\n\n local result = Wbbyte_t ^ Wsbyte_t;\n build Wdbyte_t;\n Wdbyte_t = result;\n \n testSRL_N(result);\n testSRL_Z(result);\n}\n\n\n:ze Ws_t,Wnd_t is OP_23_20=0xF & OP_19_16=0xB & OP_15_12=0x8 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t {\n \n local result = zext(Ws_t:1);\n build Wnd_t;\n Wnd_t = result;\n \n SRL_N = 0;\n testSRL_Z(result);\n SRL_C = 1;\n}\n\n\n# UNVERIFIED - not found in manual but was produced by toolchain for PIC30F2010\n# There appear to be a few variations of this encoding produced by toolchain \n# but do not decode with objdump\ndefine pcodeop break;\n:break is OP_23_0=0xDA4000 {\n\tbreak();\n}\n\n} # end with : phase = 2\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24E.slaspec", "content": "# This module defines Microchip PIC-24. \n\n# Based on \"Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf)\n\ndefine endian=little; # little endian only\n\n@define PIC24E \"1\" \n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24F.slaspec", "content": "# This module defines Microchip PIC-24. \n\n# Based on \"Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf)\n\ndefine endian=little; # little endian only\n\n@define PIC24F \"1\" \n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC24H.slaspec", "content": "# This module defines Microchip PIC-24. \n\n# Based on \"Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf)\n\ndefine endian=little; # little endian only\n\n@define PIC24H \"1\" \n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC30.dwarf", "content": "\n\t\n\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n\t\n\t\n\n" }, { "path": "pypcode/processors/PIC/data/languages/PIC33.dwarf", "content": "\n\t\n\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n\t\n\t\n\n" }, { "path": "pypcode/processors/PIC/data/languages/dsPIC30F.slaspec", "content": "# This module defines Microchip PIC-24. \n\n# Based on \"Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf)\n\ndefine endian=little; # little endian only\n\n@define dsPIC30F \"1\" \n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/dsPIC33C.slaspec", "content": "# This module defines Microchip PIC-24. \n\ndefine endian=little; # little endian only\n\n@define dsPIC33C \"1\"\n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/dsPIC33E.slaspec", "content": "# This module defines Microchip PIC-24. \n\n# Based on \"Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf)\n\ndefine endian=little; # little endian only\n\n@define dsPIC33E \"1\" \n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/dsPIC33F.slaspec", "content": "# This module defines Microchip PIC-24. \n\n# Based on \"Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf)\n\ndefine endian=little; # little endian only\n\n@define dsPIC33F \"1\" \n\n@include \"PIC24.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/pic12.sinc", "content": "#\n# PIC-12 Main Section\n# includes constants, memory space and common register space definitions\n#\n\n# STATUS bit definitions\n@define STATUS_PA0_BIT\t5\n@define STATUS_Z_BIT\t2\n@define STATUS_DC_BIT\t1\n@define STATUS_C_BIT\t0\n\n# STATUS bit masks used for setting\n@define STATUS_PA_MASK\t0x60\n@define STATUS_Z_MASK\t0x04\n@define STATUS_DC_MASK\t0x02\n@define STATUS_C_MASK\t0x01\n\n# STATUS bit masks used for clearing\n@define STATUS_PA_CLEARMASK\t0x9F\n@define STATUS_Z_CLEARMASK\t0xFB\n@define STATUS_DC_CLEARMASK\t0xFD\n@define STATUS_C_CLEARMASK\t0xFE\n\n@define FSR_BSEL_MASK\t\t0x60\t\t# FSR<5:6> Bank Select bits : Direct Addressing\n\ndefine endian=little;\ndefine alignment=2;\n\n# Instruction Memory (ROM-based)\ndefine space CODE type=ram_space wordsize=2 size=2 default;\n\n# General Purpose Register Memory consists of 2-banks of 32-bytes each\n# Bank selection occurs using FSR bits <6:5>\ndefine space DATA type=ram_space size=1; \n\n# HWSTACK consists of a 2-word by 12-bit RAM and a corresponding to a hidden stack pointer (STKPTR).\ndefine space HWSTACK type=ram_space wordsize=2 size=1; # WORDSIZE is actually 12-bits\n \ndefine space register type=register_space size=2; \n\n# Program Counter (9-bits) - PC Latch: PCL\ndefine register offset=0x0000 size=2 [ PC ];\n\n# Stack Pointer\ndefine register offset=0x0002 size=1 [ STKPTR ];\n\n# Working register\ndefine register offset=0x0003 size=1 [ W ];\n\n# PC Latch register (real register is memory based)\ndefine register offset=0x0004 size=1 [ PCL ];\n\n# File Selection register (real register is memory based)\ndefine register offset=0x0005 size=1 [ FSR ];\n\n# STATUS register (real register is memory based)\ndefine register offset=0x0006 size=1 [ STATUS ];\n\n# Status bit registers (these do not really exist and must get reflected into the STATUS byte register)\ndefine register offset=0x0007 size=1 [ PA Z DC C ];\n\n# Option Register\ndefine register offset=0x00b size=1 [ OPTION ];\n" }, { "path": "pypcode/processors/PIC/data/languages/pic12_instructions.sinc", "content": "#\n# PIC-12 Instruction Section\n# includes token definitions, macros, sub-constructors and instruction definitions\n#\n\n# Little-endian bit numbering\ndefine token instr16(16)\n\top12 =\t(0,11)\n\top6 =\t(6,11)\n\top4 =\t(8,11)\n\top3 =\t(9,11)\n\td =\t\t(5,5)\n\tb3 =\t(5,7)\n\tf5 =\t(0,4)\n\tf5h =\t(4,4)\n\tk8 =\t(0,7)\n\tk9 =\t(0,8)\n;\n\n#\n# Unsupported Operations\n#\n\ndefine pcodeop clearWatchDogTimer;\n\ndefine pcodeop sleep;\n\n#\n# MACROS\n#\n\n# Pack status bits into STATUS register\nmacro packStatus() {\n#\tSTATUS = (PA << $(STATUS_PA0_BIT))\n#\t\t\t\t| (Z << $(STATUS_Z_BIT))\n#\t\t\t\t| (DC << $(STATUS_DC_BIT))\n#\t\t\t\t| (C << $(STATUS_C_BIT));\n}\n\n# Unpack status bits from STATUS register\nmacro unpackStatus() {\n#\tPA = (STATUS & $(STATUS_PA_MASK)) >> $(STATUS_PA0_BIT);\n#\tZ = ((STATUS & $(STATUS_Z_MASK)) != 0);\n#\tDC = ((STATUS & $(STATUS_DC_MASK)) != 0);\n#\tC = ((STATUS & $(STATUS_C_MASK)) != 0);\n}\n\nmacro setResultFlags(result) {\n\tZ = (result == 0);\n}\n\nmacro setAddCCarryFlag(op1,op2) {\n\tC = (carry(op1,C) || carry(op2,op1 + C));\n}\n\nmacro setAddCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tDC = (carry(tmp1,DC) || carry(tmp2,tmp1 + DC));\n}\n\nmacro setAddCFlags(op1,op2) {\n\tsetAddCCarryFlag(op1,op2);\n\tsetAddCDigitCarryFlag(op1,op2);\n}\n\nmacro setAddFlags(op1,op2) {\n\tC = carry(op1,op2);\n\tDC = carry(op1<<4,op2<<4);\n}\n\nmacro setSubtractCCarryFlag(op1,op2) {\n\tlocal notC = ~C;\n\tC = ((op1 < notC) || (op2 < (op1 - notC)));\n}\n\nmacro setSubtractCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal notDC = ~DC;\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tmp3 = (tmp1 - notDC) << 4;\n\tDC = ((tmp1 < notDC) || (tmp2 < tmp3));\n}\n\nmacro setSubtractCFlags(op1,op2) {\n\tsetSubtractCCarryFlag(op1,op2);\n\tsetSubtractCDigitCarryFlag(op1,op2);\n}\n\nmacro setSubtractFlags(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\t# NOTE: carry flag is SET if there is NO borrow\n\tC = (op1 >= op2);\n\tDC = ((op1<<4) < (op2<<4));\n}\n\nmacro push(val) {\t# TODO: Uncertain about this !!\n\t*[HWSTACK]:2 STKPTR = val;\n\tSTKPTR = STKPTR + 2;\n}\n\nmacro pop(val) {\t# TODO: Uncertain about this !!\n\tSTKPTR = STKPTR - 2;\n\tval = *[HWSTACK]:2 STKPTR;\n}\n\n#\n# SUB-CONSTRUCTORS\n#\n\n# File register index (f5!=0): bank selection determined by FSR<5:6> bits \nfREGLoc: f5\tis f5\t\t\t\t\t\t\t\t\t\t\t\t{ \n\t addr:1 = (FSR & $(FSR_BSEL_MASK)) + f5;\n\t export *[DATA]:1 addr;\n}\n\n# File register index (f5=0): INDF use implies indirect data access using FSR value\nfREGLoc: \"INDF\"\tis f5=0\t\t\t\t\t\t\t\t\t\t\t\t{ \n\taddr:1 = FSR; # only low order 7-bits are used for indirect address\n\texport *[DATA]:1 addr; \n}\n\n# File register index : low 16-bytes of each bank always mapped to Bank-0\nfREGLoc: f5\tis f5h=0x0 & f5\t\t\t\t\t\t\t\t{ export *[DATA]:1 f5; }\n\n# Special File Registers which have been mirrored into the register space\n# to improve decompiler results\nfREGLoc: \"STATUS\"\tis f5=0x03\t\t\t\t\t\t\t\t{ packStatus(); export STATUS; }\nfREGLoc: \"FSR\"\t\tis f5=0x04\t\t\t\t\t\t\t\t{ export FSR; }\nfREGLoc: \"PCL\"\t\tis f5=0x02\t\t\t\t\t\t\t\t{ export PCL; }\n\n# File register index (bank selection determined by RP bits in STATUS reg)\nsrcREG: fREGLoc\tis fREGLoc\t\t\t\t\t\t\t\t{ export fREGLoc; }\n#srcREG: \"STATUS\"\tis f5=0x03\t\t\t\t\t\t\t\t{ packStatus(); export STATUS; }\n#srcREG: \"FSR\"\t\tis f5=0x04\t\t\t\t\t\t\t\t{ export FSR; }\nsrcREG: \"PCL\"\t\tis f5=0x02\t\t\t\t\t\t\t\t{\n\t# PCL and PA1:PA0 is latched\n\taddr:2 = inst_start >> 1; # Compenstate for CODE wordsize\n\tPCL = addr:1;\n\taddr = (addr >> 9) & 0x3;\n\tPA = addr:1;\n\texport PCL; \n}\n\n# Destination register (either srcREG or W)\ndestREG: \"0\"\tis d=0\t\t\t\t\t\t\t\t\t{ export W; }\ndestREG: \"1\"\tis d=1 & srcREG\t\t\t\t\t\t\t{ export srcREG; }\n#destREG: \"1\"\tis d=1 & f5=0x03\t\t\t\t\t\t{ export STATUS; }\n#destREG: \"1\"\tis d=1 & f5=0x04\t\t\t\t\t\t{ export FSR; }\n#destREG: \"1\"\tis d=1 & f5=0x02\t\t\t\t\t\t{ \n#\t# Storing to PCL causes a branch, \n#\t# PC<8> is always cleared for CALL and modifying instructions.\n#\t# The MOVWF, ADDWF, BSF and BCF definition below has a specific case to handle this write to PCL\n#\texport PCL; \n#}\n#destREG: \"1\"\tis d=1 & f5=0x00 & fREGLoc\t\t\t\t{ \n#\t# INDF use (indirect data access)\n#\texport *[DATA]:1 fREGLoc; \n#}\n\n# Destination operand representation (w: W register is destination; f: specified srcREG is destination)\nD: \"w\"\t\tis d=0\t\t\t\t\t\t\t\t\t\t{ }\nD: \"f\"\t\tis d=1\t\t\t\t\t\t\t\t\t\t{ }\n\n# Absolute addresses generated from k8 or k9 and STATUS.PA\nabsAddr8: k8\tis k8\t\t\t\t\t\t\t\t\t{\n\taddr:2 = (zext(PA) << 9) + k8;\n\texport addr; \n}\nabsAddr9: k9\tis k9\t\t\t\t\t\t\t\t\t{\n\taddr:2 = (zext(PA) << 9) + k9;\n\texport addr; \n}\n\n# Skip instruction address\nskipInst: inst_skip\tis op12\t[ inst_skip = inst_next + 1; ]\t\t{export *[CODE]:2 inst_skip; }\n\n# Immediate Data (Literal operation)\nimm8: \"#\"k8\tis k8\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k8; }\n\n# Bit identifier\nbit: \"#\"b3\t\tis b3\t\t\t\t\t\t\t\t\t{ export *[const]:1 b3; }\n\n# PC register write - instruction must set PC with PCLATH/PCL and perform branch operation\npcl: \"PC\" \t\t\tis f5=0x02\t\t\t\t{ export PCL; }\n\n# STATUS register\nstatus: \"STATUS\" \tis f5=0x03\t\t\t\t{ export STATUS; }\n\n#\n# BYTE-ORIENTED FILE REGISTER OPERATIONS\n#\n\n:ADDWF srcREG, D\tis op6=0x07 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0001 11df ffff\n\t# 0000 0001 1100 0000\t->\tADDWF INDF, 0 \n\t# 0000 0001 1110 0000\t->\tADDWF INDF, 1\n\t# 0000 0001 1101 0010\t->\tADDWF 0x12, 0\n\t# 0000 0001 1111 0010\t->\tADDWF 0x12, 1\n\ttmp:1 = srcREG;\n\tsetAddFlags(W, tmp); \n\ttmp = W + tmp;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ADDWF pcl, D\t\tis op6=0x07 & D & pcl\t{\n\t# ---- 0001 11df ffff\n\t# 0000 0001 1110 0010 -> ADDWF PCL, w, ACCESS\n\taddr:2 = (inst_start >> 1) & 0x3f; # shift compenstates for CODE wordsize\n\ttmpLo:1 = addr:1;\n\tPA = addr(1);\n\tsetAddFlags(tmpLo, W);\n\ttmpLo = tmpLo + W;\n\tsetResultFlags(tmpLo);\n\taddr = (zext(PA) << 9) + zext(tmpLo);\n\tPCL = tmpLo;\n\tgoto [addr];\n}\n\n:ANDLW imm8\t\t\t\tis op4=0xe & imm8\t\t\t\t\t\t\t\t{\n\t# ---- 1110 kkkk kkkk\n\t# 0000 1110 0001 0010\t->\tANDLW #0x12\n\tW = W & imm8;\n\tsetResultFlags(W);\n}\n\n:ANDWF srcREG, D\tis op6=0x05 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0001 01df ffff\n\t# 0000 0001 0100 0000\t->\tANDWF INDF, 0 \n\t# 0000 0001 0110 0000\t->\tANDWF INDF, 1\n\t# 0000 0001 0101 0010\t->\tANDWF 0x12, 0\n\t# 0000 0001 0111 0010\t->\tANDWF 0x12, 1\n\ttmp:1 = W & srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:BCF srcREG, bit\t\t\tis op4=0x4 & bit & srcREG\t\t\t\t\t\t\t{\n\t# ---- 0100 bbbf ffff\n\t# 0000 0100 1000 0000\t->\tBCF INDF, #0x4\n\t# 0000 0100 1001 0010\t->\tBCF 0x12, #0x4\n\tlocal bitmask = ~(1 << bit);\n\tsrcREG = srcREG & bitmask;\n}\n\n:BCF status, bit\t\tis op4=0x4 & b3=0 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0100 bbbf ffff\n\t# 0000 0100 0000 0000\t->\tBCF STATUS, #C\n\tC = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit\t\tis op4=0x4 & b3=1 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0100 bbbf ffff\n\t# 0000 0100 0010 0000\t->\tBCF STATUS, #DC\n\tDC = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit\t\tis op4=0x4 & b3=2 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0100 bbbf ffff\n\t# 0000 0100 0100 0000\t->\tBCF STATUS, #Z\n\tZ = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit\t\tis op4=0x4 & b3=5 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0100 bbbf ffff\n\t# 0000 0100 1010 0000\t->\tBCF STATUS, #PA0\n\tPA = PA & 0x1;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit\t\tis op4=0x4 & b3=6 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0100 bbbf ffff\n\t# 0000 0100 1100 0000\t->\tBCF STATUS, #PA1\n\tPA = PA & 0x2;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BSF srcREG, bit\t\t\tis op4=0x5 & bit & srcREG\t\t\t\t\t\t\t{\n\t# ---- 0101 bbbf ffff\n\t# 0000 0101 1000 0000\t->\tBSF INDF, #0x4\n\t# 0000 0101 1001 0010\t->\tBSF 0x12, #0x4\n\tlocal bitmask = 1 << bit;\n\tsrcREG = srcREG | bitmask;\n}\n\n:BSF status, bit\t\t\tis op4=0x5 & b3=0 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0101 bbbf ffff\n\t# 0000 0101 0000 0000\t->\tBSF STATUS, #C\n\tC = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit\t\t\tis op4=0x5 & b3=1 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0101 bbbf ffff\n\t# 0000 0101 0010 0000\t->\tBSF STATUS, #DC\n\tDC = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit\t\t\tis op4=0x5 & b3=2 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0101 bbbf ffff\n\t# 0000 0101 0100 0000\t->\tBSF STATUS, #Z\n\tZ = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit\t\t\tis op4=0x5 & b3=5 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0101 bbbf ffff\n\t# 0000 0101 1010 0000\t->\tBSF STATUS, #PA0\n\tPA = PA | 0x1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit\t\t\tis op4=0x5 & b3=6 & bit & status\t\t\t\t\t\t\t{\n\t# ---- 0101 bbbf ffff\n\t# 0000 0101 1100 0000\t->\tBSF STATUS, #PA1\n\tPA = PA | 0x2;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BTFSC srcREG, bit\t\tis op4=0x6 & bit & srcREG\t& skipInst\t\t\t\t{\n\t# ---- 0110 bbbf ffff\n\t# 0000 0110 1000 0000\t->\tBTFSC INDF, #0x4\n\t# 0000 0110 1001 0010\t->\tBTFSC 0x12, #0x4\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcREG & bitmask;\n\tif (tmp == 0) goto skipInst;\n}\n\n:BTFSC status, bit\t\tis op4=0x6 & b3=0 & bit & status & skipInst\t\t\t\t{\n\t# ---- 0110 bbbf ffff\n\t# 0000 0110 0000 0000\t->\tBTFSC STATUS, #C\n\tif (C == 0) goto skipInst;\n}\n\n:BTFSC status, bit\t\tis op4=0x6 & b3=1 & bit & status & skipInst\t\t\t\t{\n\t# ---- 0110 bbbf ffff\n\t# 0000 0110 0010 0000\t->\tBTFSC STATUS, #DC\n\tif (DC == 0) goto skipInst;\n}\n\n:BTFSC status, bit\t\tis op4=0x6 & b3=2 & bit & status & skipInst\t\t\t\t{\n\t# ---- 0110 bbbf ffff\n\t# 0000 0110 0100 0000\t->\tBTFSC STATUS, #Z\n\tif (Z == 0) goto skipInst;\n}\n\n:BTFSS srcREG, bit\t\tis op4=0x7 & bit & srcREG\t& skipInst\t\t\t\t{\n\t# ---- 0111 bbbf ffff\n\t# 0000 0111 1000 0000\t->\tBTFSS INDF, #0x4\n\t# 0000 0111 1001 0010\t->\tBTFSS 0x12, #0x4\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcREG & bitmask;\n\tif (tmp != 0) goto skipInst;\n}\n\n:BTFSS status, bit\t\tis op4=0x7 & b3=0 & bit & status & skipInst\t\t\t\t{\n\t# ---- 0111 bbbf ffff\n\t# 0000 0111 0000 0000\t->\tBTFSS STATUS, #C\n\tif (C != 0) goto skipInst;\n}\n\n:BTFSS status, bit\t\tis op4=0x7 & b3=1 & bit & status & skipInst\t\t\t\t{\n\t# ---- 0111 bbbf ffff\n\t# 0000 0111 0010 0000\t->\tBTFSS STATUS, #DC\n\tif (DC != 0) goto skipInst;\n}\n\n:BTFSS status, bit\t\tis op4=0x7 & b3=2 & bit & status & skipInst\t\t\t\t{\n\t# ---- 0111 bbbf ffff\n\t# 0000 0111 0100 0000\t->\tBTFSS STATUS, #Z\n\tif (Z != 0) goto skipInst;\n}\n\n:CALL absAddr8\t\t\tis op4=0x9 & absAddr8\t\t\t\t\t\t\t{\n\t# ---- 1001 kkkk kkkk\n\t# 0000 1001 0010 0011\t->\tCALL 0x23\n\t# 0000 1001 0001 0000\t->\tCALL 0x10\n\tpush(&:2 inst_next);\n\tcall [absAddr8];\n}\n\n:CLRF srcREG\t\t\t\tis op6=0x01 & d=1 & srcREG\t\t\t\t\t\t{\n\t# ---- 0000 011f ffff\n\t# 0000 0000 0110 0000\t->\tCLRF INDF\n\t# 0000 0000 0111 0010\t->\tCLRF 0x12\n\tsrcREG = 0;\n\tZ = 1;\n}\n\n:CLRW\t\t\t\t\tis op6=0x01 & d=0 & f5=0\t\t\t\t\t\t{\n\t# ---- 0000 0100 0000\n\t# 0000 0001 0000 0000\t->\tCLRW\n\tW = 0;\n\tZ = 1;\n}\n\n:CLRWDT\t\t\t\t\tis op12=0x0004\t\t\t\t{\n\t# ---- 0000 0000 0100\n\t# Clear Watchdog Timer - Not Implemented\n\tclearWatchDogTimer();\n}\n\n:COMF srcREG, D\t\tis op6=0x09 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0010 01df ffff\n\t# 0000 0010 0100 0000\t->\tCOMF INDF, 0 \n\t# 0000 0010 0110 0000\t->\tCOMF INDF, 1\n\t# 0000 0010 0101 0010\t->\tCOMF 0x12, 0\n\t# 0000 0010 0111 0010\t->\tCOMF 0x12, 1\n\ttmp:1 = ~srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:DECF srcREG, D\t\tis op6=0x03 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0000 11df ffff\n\t# 0000 0000 1100 0000\t->\tDECF INDF, 0 \n\t# 0000 0000 1110 0000\t->\tDECF INDF, 1\n\t# 0000 0000 1101 0010\t->\tDECF 0x12, 0\n\t# 0000 0000 1111 0010\t->\tDECF 0x12, 1\n\ttmp:1 = srcREG - 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:DECFSZ srcREG, D\t\tis op6=0x0b & srcREG & D & destREG & skipInst\t\t{\n\t# ---- 0010 11df ffff\n\t# 0000 0010 1100 0000\t->\tDECFSZ INDF, 0 \n\t# 0000 0010 1110 0000\t->\tDECFSZ INDF, 1\n\t# 0000 0010 1101 0010\t->\tDECFSZ 0x12, 0\n\t# 0000 0010 1111 0010\t->\tDECFSZ 0x12, 1\n\ttmp:1 = srcREG - 1;\n\tdestREG = tmp;\n\tif (tmp == 0) goto skipInst;\n}\n\n:GOTO absAddr9\t\t\tis op3=0x5 & absAddr9\t\t\t\t\t\t\t{\n\t# ---- 101k kkkk kkkk\n\t# 0000 1011 0010 0011\t->\tGOTO 0x123\n\t# 0000 1010 0001 0000\t->\tGOTO 0x10\n\tgoto [absAddr9];\n}\n\n:INCF srcREG, D\t\tis op6=0x0a & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0010 10df ffff\n\t# 0000 0010 1000 0000\t->\tINCF INDF, 0 \n\t# 0000 0010 1010 0000\t->\tINCF INDF, 1\n\t# 0000 0010 1001 0010\t->\tINCF 0x12, 0\n\t# 0000 0010 1011 0010\t->\tINCF 0x12, 1\n\ttmp:1 = srcREG + 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:INCFSZ srcREG, D\t\tis op6=0x0f & srcREG & D & destREG & skipInst\t\t{\n\t# ---- 0011 11df ffff\n\t# 0000 0011 1100 0000\t->\tINCFSZ INDF, 0 \n\t# 0000 0011 1110 0000\t->\tINCFSZ INDF, 1\n\t# 0000 0011 1101 0010\t->\tINCFSZ 0x12, 0\n\t# 0000 0011 1111 0010\t->\tINCFSZ 0x12, 1\n\ttmp:1 = srcREG + 1;\n\tdestREG = tmp;\n\tif (tmp == 0) goto skipInst;\n}\n\n:IORLW imm8\t\t\t\tis op4=0xd & imm8\t\t\t\t\t\t\t\t{\n\t# ---- 1101 kkkk kkkk\n\t# 0000 1101 0001 0010\t->\tIORLW #0x12\n\tW = W | imm8;\n\tsetResultFlags(W);\n}\n\n:IORWF srcREG, D\t\tis op6=0x04 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0001 00df ffff\n\t# 0000 0001 0000 0000\t->\tIORWF INDF, 0 \n\t# 0000 0001 0010 0000\t->\tIORWF INDF, 1\n\t# 0000 0001 0001 0010\t->\tIORWF 0x20, 0\n\t# 0000 0001 0011 0010\t->\tIORWF 0x20, 1\n\ttmp:1 = W | srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:MOVLW imm8\t\t\t\tis op4=0xc & imm8\t\t\t\t\t\t\t\t{\n\t# ---- 1100 kkkk kkkk\n\t# 0000 1100 0001 0010\t->\tMOVLW #0x12\n\tW = imm8;\n}\n\n:MOVF srcREG, D\t\tis op6=0x08 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0010 00df ffff\n\t# 0000 0010 0000 0000\t->\tMOVF INDF, 0 \n\t# 0000 0010 0010 0000\t->\tMOVF INDF, 1\n\t# 0000 0010 0001 0010\t->\tMOVF 0x12, 0\n\t# 0000 0010 0011 0010\t->\tMOVF 0x12, 1\n\ttmp:1 = srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:MOVWF srcREG\t\t\t\tis op6=0x00 & d=1 & srcREG\t\t\t\t\t\t{\n\t# ---- 0000 001f ffff\n\t# 0000 0000 0010 0000\t->\tMOVWF INDF\n\t# 0000 0000 0011 0010\t->\tMOVWF 0x12\n\tsrcREG = W;\n}\n\n:MOVWF pcl\t\t\t\t\tis op6=0x00 & pcl\t\t\t \t\t\t\t{\n\t# ---- 0000 001f ffff\n\t# 0000 0000 0010 0010\t->\tMOVWF PCL\n\tPCL = W;\n\taddr:2 = (zext(PA) << 9) + zext(PCL);\n\tgoto [addr];\n}\n\n:NOP\t\t\t\t\tis op12=0x00\t\t\t\t\t\t{\n\t# ---- 0000 0000 0000\n}\n\n:OPTION\t\t\t\t\tis op12=0x0002\t\t\t\t\t\t{\n\t# ---- 0000 0000 0010\n\tOPTION = W;\n}\n\n:RETLW imm8\t\t\t\tis op4=0x8 & imm8\t\t\t\t\t\t\t\t{\n\t# ---- 1000 kkkk kkkk\n\t# 0000 1000 0001 0010\t->\tRETLW #0x12\n\tW = imm8;\n\tretAddr:2 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RLF srcREG, D\t\tis op6=0x0d & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0011 01df ffff\n\t# 0000 0011 0100 0000\t->\tRLF INDF, 0 \n\t# 0000 0011 0110 0000\t->\tRLF INDF, 1\n\t# 0000 0011 0101 0010\t->\tRLF 0x12, 0\n\t# 0000 0011 0111 0010\t->\tRLF 0x12, 1\n\tlocal tmpC = C;\n\ttmp:1 = srcREG;\n\tC = (tmp s< 0);\n\ttmp = (tmp << 1) | tmpC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:RRF srcREG, D\t\tis op6=0x0c & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0011 00df ffff\n\t# 0000 0011 0000 0000\t->\tRRF INDF, 0 \n\t# 0000 0011 0010 0000\t->\tRRF INDF, 1\n\t# 0000 0011 0001 0010\t->\tRRF 0x12, 0\n\t# 0000 0011 0011 0010\t->\tRRF 0x12, 1\n\tlocal tmpC = C << 7;\n\ttmp:1 = srcREG;\n\tC = (tmp & 1) != 0;\n\ttmp = (tmp >> 1) | tmpC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SLEEP\t\t\t\t\tis op12=0x0003\t\t\t\t{ \n\t# ---- 0000 0000 0011\n\t# Sleep - Not Implemented\n\tsleep();\n}\n\n:SUBWF srcREG, D\t\tis op6=0x02 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0000 10df ffff\n\t# 0000 0000 1000 0000\t->\tSUBWF INDF, 0 \n\t# 0000 0000 1010 0000\t->\tSUBWF INDF, 1\n\t# 0000 0000 1001 0010\t->\tSUBWF 0x12, 0\n\t# 0000 0000 1011 0010\t->\tSUBWF 0x12, 1\n\ttmp:1 = srcREG;\n\tsetSubtractFlags(tmp, W); \n\ttmp = tmp - W;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SWAPF srcREG, D\t\tis op6=0x0e & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0011 10df ffff\n\t# 0000 0011 1000 0000\t->\tSUBWF INDF, 0 \n\t# 0000 0011 1010 0000\t->\tSUBWF INDF, 1\n\t# 0000 0011 1001 0010\t->\tSUBWF 0x12, 0\n\t# 0000 0011 1011 0010\t->\tSUBWF 0x12, 1\n\ttmp:1 = srcREG;\n\tdestREG = (tmp << 4) | (tmp >> 4);\n}\n\n:XORLW imm8\t\t\t\tis op4=0xf & imm8\t\t\t\t\t\t\t\t{\n\t# ---- 1111 kkkk kkkk\n\t# 0000 1111 0001 0010\t->\tXORLW #0x12\n\tW = imm8 ^ W;\n\tsetResultFlags(W);\n}\n\n:XORWF srcREG, D\t\tis op6=0x06 & srcREG & D & destREG\t\t\t\t\t{\n\t# ---- 0001 10df ffff\n\t# 0000 0001 1000 0000\t->\tXORWF INDF, 0 \n\t# 0000 0001 1010 0000\t->\tXORWF INDF, 1\n\t# 0000 0001 1001 0010\t->\tXORWF 0x12, 0\n\t# 0000 0001 1011 0010\t->\tXORWF 0x12, 1\n\ttmp:1 = W ^ srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic12c5xx.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic12c5xx.ldefs", "content": "\n\n\n \n PIC-12C5xx\n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic12c5xx.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic12c5xx.slaspec", "content": "@define PROCESSOR \"PIC_12C5XX\"\n\n@include \"pic12.sinc\"\n\n#\n# NOTES\t-\n#\t1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and\n# slightly modified to specify a the correct Register File Map.\n#\n\n# Bank-0 File Registers\ndefine DATA offset=0x00 size=1 [\n\tINDF\tTMR0\tPCL.0\tSTATUS.0 FSR.0\tOSCCAL\tGPIO\n];\n\n@include \"pic12_instructions.sinc\"\n\n# IO Tristate Register\ndefine register offset=0x0020 size=1 [ TRIS ];\n\n# TRIS register\ntrisREG: \"6\"\tis f5=0x6\t\t\t\t\t\t\t\t{ export TRIS; }\n\n:TRIS trisREG\t\t\t\tis op6=0x00 & d=0 & trisREG\t\t\t\t\t{\n\t# ---- 0000 0000 0fff\n\t# 0000 0000 0000 0110\t->\tTRIS 6\n\ttrisREG = W;\n}\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16.ldefs", "content": "\n\n\n \n PIC-16(C,CR)XXX\n \n \n \n \n PIC-16(L)FXXX\n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16.pspec", "content": "\n\n\n \n \n \n \t\n \t\t\n \t\n \t\n \t\t\n \t\n \t\n \t\t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16.sinc", "content": "#\n# PIC-16 Main Section\n# includes constants, memory space and common register space definitions\n#\ndefine endian=little;\ndefine alignment=2;\n\n# Instruction Memory (ROM-based)\ndefine space CODE type=ram_space wordsize=2 size=2 default;\n\n# General Purpose Register Memory consists of 4-banks of 255-bytes for PIC16,\n# or 32-banks of 255 bytes each for PIC_16F.\n# Bank selection occurs using STATUS register bits RP0 & RP1\ndefine space DATA type=ram_space size=2; \n\n# HWSTACK consists of a 8-word by 13-bit RAM and a corresponding to a hidden stack pointer (STKPTR).\ndefine space HWSTACK type=ram_space wordsize=2 size=1; # WORDSIZE is actually 13-bits\n \ndefine space register type=register_space size=2; \n\n# Program Counter (13-bits) - PC Latch: PCLATH / PCL\ndefine register offset=0x0000 size=2 [ PC ];\n\n# Stack Pointer\ndefine register offset=0x0002 size=1 [ STKPTR ];\n\n# Working register\ndefine register offset=0x0003 size=1 [ W SkipNext ];\n\n# Status bit registers (these do not really exist and must get reflected into the STATUS byte register)\ndefine register offset=0x0007 size=1 [ IRP RP ];\n\n@define C \"STATUS[0,1]\"\n@define DC \"STATUS[1,1]\"\n@define Z \"STATUS[2,1]\"\n@define PD \"STATUS[3,1]\"\n@define TO \"STATUS[4,1]\"\n@define RP \"STATUS[5,2]\"\n@define IRP \"STATUS[7,1]\"\n\n# STATUS bit definitions\n@define STATUS_IRP_BIT\t7\n@define STATUS_RP_BIT\t5\n@define STATUS_Z_BIT\t2\n@define STATUS_DC_BIT\t1\n@define STATUS_C_BIT\t0\n\n# STATUS bit masks used for setting\n@define STATUS_IRP_MASK 0x80\n@define STATUS_RP_MASK\t0x60\n@define STATUS_Z_MASK\t0x04\n@define STATUS_DC_MASK\t0x02\n@define STATUS_C_MASK\t0x01\n\n# STATUS bit masks used for clearing\n@define STATUS_IRP_CLEARMASK 0x7F\n@define STATUS_RP_CLEARMASK\t0x9F\n@define STATUS_Z_CLEARMASK\t0xFB\n@define STATUS_DC_CLEARMASK\t0xFD\n@define STATUS_C_CLEARMASK\t0xFE\n\n\n#\n# WARNING! - Reflection of these DATA-based registers with the corresponding register\n# is not fully implemented due to the complexity of doing so within this language specification.\n# Reflection of certain registers (e.g., STATUS) within other memory banks is also not modeled.\n#\n# NOTES\t-\n# 1. Chips with voltage comparator and reference functions may replace A/D registers (ADCON0 and ADCON1) with (VMCON and VRCON)\n# Instances of this include PIC16F627A/628A/648A (there could be others)\n#\t2. If a specific PIC-16 has a different register set, this file and the pic16.pspec file may be copied/renamed and\n# slightly modified to specify a the correct Register File Map. \n#\n\n#\n# Bank-0 File Registers\n#\n@if PROCESSOR == \"PIC_16\"\ndefine DATA offset=0x0000 size=1 [\n\t\t\t\tINDF\t_ PCL\t\tSTATUS FSR\t\t_ _ _ _ _ PCLATH INTCON\t_\t\t_ _ _\n];\n@elif PROCESSOR == \"PIC_16F\"\ndefine DATA offset=0x0000 size=1 [\n\t\t\t\tINDF0\tINDF1\tPCL\t\tSTATUS\tFSR0L\tFSR0H\tFSR1L\tFSR1H\tBSR\t\tWREG\tPCLATH\tINTCON\t_\t\t_\t\t_\t\t_\n];\ndefine DATA offset=0x0004 size=2 [ FSR0 FSR1 ];\n@endif\n\n# Additional Data Bank data registers are defined in the .PSPEC file.\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16.slaspec", "content": "@define PROCESSOR \"PIC_16\"\n\n@include \"pic16.sinc\"\n\n@include \"pic16_instructions.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16_instructions.sinc", "content": "#\n# PIC-16 Instruction Section\n# includes token definitions, macros, sub-constructors and instruction definitions\n#\n# PC register write - instruction must set PC with PCLATH/PCL and perform branch operation\n\n# Little-endian bit numbering\ndefine token instr16(16)\n\top14 =\t(0,13)\n\top12 = (2,13)\n\top11 =\t(3,13)\n\top9 =\t(5,13)\n\top8 = \t(6,13)\n\top7 = \t(7,13)\n\top6 =\t(8,13)\n\top5 =\t(9,13)\n\top4 =\t(10,13)\n\top3 =\t(11,13)\n\td =\t\t(7,7)\n\tb3 =\t(7,9)\n\tIntConBits = (7,9)\n\tStatusBit = (7,9)\n\tf7 =\t(0,6)\n\tlf7 = \t(0,3)\n\tuf7 =\t(4,6)\n\tfsr = \t(2,2)\n\tfsrk =\t(6,6)\n\tk5 = \t(0,4)\n\tk6 = \t(0,5)\n\tk7 = \t(0,6)\n\tk8 =\t(0,7)\n\tsk9 = (0,8) signed\n\tk11 =\t(0,10)\n\tsk6 =\t(0,5) signed\n\tl5 =\t(0,4)\t# low order 5-bits of instr16\n\tmm =\t(0,1)\n;\n\ndefine register offset=0x100 size=4 contextreg;\ndefine context contextreg\n\tdoPseudo = (0,0)\n\tpossibleSkip = (1,1) noflow\n;\n\n\n@if PROCESSOR == \"PIC_16F\"\n\nattach names [IntConBits] [ IOCIF INTF TMR0IF IOCIE INTE TMR0IE PEIE GIE ];\n\nattach variables [ fsr fsrk ] [ FSR0 FSR1 ];\n\n@endif\n\n#\n# Unsupported Operations\n#\n\ndefine pcodeop clearWatchDogTimer;\n\ndefine pcodeop sleep;\ndefine pcodeop reset;\n\n#\n# MACROS\n#\n\n# Pack status bits into STATUS register\nmacro packStatus() {\n#\tSTATUS = (IRP << $(STATUS_IRP_BIT))\n#\t\t\t\t| (RP << $(STATUS_RP0_BIT))\n#\t\t\t\t| (Z << $(STATUS_Z_BIT))\n#\t\t\t\t| (DC << $(STATUS_DC_BIT))\n#\t\t\t\t| (C << $(STATUS_C_BIT));\n}\n\n# Unpack status bits from STATUS register\nmacro unpackStatus() {\n#\tIRP = ((STATUS & $(STATUS_IRP_MASK)) != 0);\n#\tRP = (STATUS & $(STATUS_RP_MASK)) >> $(STATUS_RP0_BIT);\n#\tZ = ((STATUS & $(STATUS_Z_MASK)) != 0);\n#\tDC = ((STATUS & $(STATUS_DC_MASK)) != 0);\n#\tC = ((STATUS & $(STATUS_C_MASK)) != 0);\n}\n\nmacro setResultFlags(result) {\n\t$(Z) = (result == 0);\n}\n\nmacro setAddCCarryFlag(op1,op2) {\n\tlocal tc = $(C);\n\t$(C) = (carry(op1,tc) || carry(op2,op1 + tc));\n}\n\nmacro setAddCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tdc = $(DC);\n\t$(DC) = (carry(tmp1,tdc) || carry(tmp2,tmp1 + tdc));\n}\n\nmacro setAddCFlags(op1,op2) {\n\tsetAddCCarryFlag(op1,op2);\n\tsetAddCDigitCarryFlag(op1,op2);\n}\n\nmacro setAddFlags(op1,op2) {\n\t$(C)= carry(op1,op2);\n\t$(DC) = carry(op1<<4,op2<<4);\n}\n\nmacro setSubtractCCarryFlag(op1,op2) {\n\tlocal tc = $(C);\n\tlocal notC = !tc;\n\t$(C) = op2 >= !tc & op1 >= (op2 - !tc);\n}\n\nmacro setSubtractCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal notDC = ~$(DC);\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tmp3 = (tmp1 - notDC) << 4;\n\t$(DC) = ((tmp1 < notDC) || (tmp2 < tmp3));\n}\n\nmacro setSubtractCFlags(op1,op2) {\n\tsetSubtractCCarryFlag(op1,op2);\n\tsetSubtractCDigitCarryFlag(op1,op2);\n}\n\nmacro setSubtractFlags(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\t# NOTE: carry flag is SET if there is NO borrow\n\t$(C) = (op1 >= op2);\n\t$(DC) = ((op1<<4) < (op2<<4));\n}\n\nmacro push(val) {\t# TODO: Uncertain about this !!\n\t*[HWSTACK]:2 STKPTR = val;\n\tSTKPTR = STKPTR + 2;\n}\n\nmacro pop(val) {\t# TODO: Uncertain about this !!\n\tSTKPTR = STKPTR - 2;\n\tval = *[HWSTACK]:2 STKPTR;\n}\n\n#\n# SUB-CONSTRUCTORS\n#\n\n# File register index (f7!=0): bank selection determined by RP bits in STATUS reg\n@if PROCESSOR == \"PIC_16\"\nsrcREG: f7\t\tis f7\t\t\t\t\t\t\t\t\t{ \n\t addr:2 = (zext(RP) << 7) + f7;\n\t export *[DATA]:1 addr;\n}\n@elif PROCESSOR == \"PIC_16F\"\nsrcREG: f7\t\tis f7\t\t\t\t\t\t\t\t\t{ \n\t addr:2 = (zext(BSR) << 7) + f7;\n\t export *[DATA]:1 addr;\n}\n@endif\n\n# Top 16 bytes are shared RAM on PIC16 and PIC16F\nsrcREG: fv\t\tis uf7=0x7 & lf7 [fv = 0x70 + lf7; ]\t\t\t\t\t\t\t\t{ \n\t addr:2 = fv;\n\t export *[DATA]:1 addr;\n}\n\n# The registers listed here are explicitly defined as registers in sleigh.\n# There are other registers but they are named in the .pspec file.\n# The reason this is done is to have cross references created to certain registers, and to have\n# only the registers that must be accessed directly in sleigh (e.g. PCL, FSR) defined in sleigh.\n# Register explicitly defined in sleigh will not have xref's created to them.\n# Registers named only in the .pspec file will have xref's to them in most cases.\n#\n# Also, these registers ignore RP, or BSR which allow more registers to be in a different register bank.\n#\n#\tPIC16 : INDF \t_ \t\tPCL \tSTATUS \tFSR \t_\t\t_\t\t_\t\t_ \t_\tPCLATH\tINTCON\t_ _ _ _\n#\tPIC16F: INDF0\tINDF1\tPCL\t\tSTATUS\tFSR0L\tFSR0H\tFSR1L\tFSR1H\tBSR\tW\tPCLATH\tINTCON\t_ _ _ _\n\n# File register index (f7=0): INDF use implies indirect data access using FSR value and IRP bit in STATUS reg\n@if PROCESSOR == \"PIC_16\"\nsrcREG: INDF\t\tis f7=0 & INDF\t\t\t\t\t\t\t\t{ \n\taddr:2 = (zext(IRP) << 8) + zext(FSR);\n\texport *[DATA]:1 addr; \n}\nsrcREG: lf7\t\tis f7=1\t& lf7\t\t\t\t\t\t\t\t{ \n\trpval:2 = zext(RP == 1) + zext(RP == 3);\n addr:2 = (zext(rpval) << 7) + 1;\n\texport *[DATA]:1 addr;\n}\n\n@elif PROCESSOR == \"PIC_16F\"\n\nsrcREG: INDF0\t\tis f7=0 & INDF0\t\t\t\t\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\nsrcREG: INDF1\t\tis f7=1 & INDF1\t\t\t\t\t\t\t\t\t{ \n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n@endif\n\n# Special File Registers always mapped to Bank-0\nsrcREG: PCL\tis f7=0x02 & PCL {\n\t# PCL and PCLATH must be latched\n\taddr:2 = inst_start >> 1; # Compensate for CODE wordsize\n\tPCL = addr:1;\n\tPCLATH = addr(1);\n\texport PCL;\n}\n\nsrcREG: STATUS\t\tis f7=0x03 & STATUS\t\t\t\t{ export STATUS; }\n@if PROCESSOR == \"PIC_16\"\nsrcREG: FSR\t\tis f7=0x04 & FSR\t\t\t\t{ export FSR; }\n@elif PROCESSOR == \"PIC_16F\"\nsrcREG: FSR0L\t\tis f7=0x04 & FSR0L\t\t\t\t{ export FSR0L; }\nsrcREG: FSR0H\t\tis f7=0x05 & FSR0H\t\t\t\t{ export FSR0H; }\nsrcREG: FSR1L\t\tis f7=0x06 & FSR1L\t\t\t\t{ export FSR1L; }\nsrcREG: FSR1H\t\tis f7=0x07 & FSR1H\t\t\t\t{ export FSR1H; }\nsrcREG: BSR\t\tis f7=0x08 & BSR\t\t\t\t{ export BSR; }\nsrcREG: W\t\tis f7=0x09 & W\t\t\t\t{ export W; }\n@endif\nsrcREG: PCLATH\t\tis f7=0x0a & PCLATH\t\t\t\t{ export PCLATH; }\nsrcREG: INTCON\t\tis f7=0x0b & INTCON\t\t\t\t{ export INTCON; }\n\n\n# Destination register (either srcREG or W)\ndestREG: \"0\"\t\tis d=0\t\t\t\t\t\t\t\t\t{ export W; }\n\n# Destination register: bank selection determined by RP bits in STATUS reg\ndestREG: \"1\"\t\tis d=1 & f7 & srcREG\t\t\t\t\t{ export srcREG; }\n\n# Destination register: Special File Registers always mapped to Bank-0\ndestREG: \"1\"\t\tis d=1 & f7=0x02\t\t\t{ export PCL; } # PCL (special behavior reqd)\n\n# Destination operand representation (w: W register is destination; f: specified srcREG is destination)\nD: \"w\"\t\tis d=0\t\t\t\t\t\t\t\t\t\t{ }\nD: \"f\"\t\tis d=1\t\t\t\t\t\t\t\t\t\t{ }\n\n# Absolute address generated from k11 and PCLATH<4:3>\nabsAddr11: k11\tis k11\t\t\t\t\t\t\t\t\t{\n\taddr:2 = ((zext(PCLATH) & 0x18) << 8) | k11;\n\texport addr; \n}\n\n@if PROCESSOR == \"PIC_16F\"\n\n# Relative address\nrelAddr9: addr\tis sk9\t[ addr = inst_next + sk9; ]\t\t\t\t\t\t\t\t{\n\texport *[CODE]:2 addr;\n}\n\n@endif\n\n# Immediate Data (Literal operation)\nimm8: \"#\"k8\tis k8\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k8; }\n\n@if PROCESSOR == \"PIC_16F\"\n# Immediate Data (Literal operation)\nimm7: \"#\"k7\tis k7\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k7; }\n\n# Immediate Data (Literal operation)\nimm6: \"#\"k6\tis k6\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k6; }\n\n# Immediate Data (Literal operation)\nimm5: \"#\"k5\tis k5\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k5; }\n\n@endif\n\n# Bit identifier\nbit: \"#\"b3\t\tis b3\t\t\t\t\t\t\t\t\t{ export *[const]:1 b3; }\n\n# TRIS register (TODO: not sure if this TRIS mapping is correct - see TRIS instruction)\n@if PROCESSOR == \"PIC_16\"\ntrisREG: \"5\"\tis l5=5\t\t\t\t\t\t\t\t\t\t\t\t{ local trl:2 = 0x89; export *[DATA]:1 trl; } # TRISA\ntrisREG: \"6\"\tis l5=6\t\t\t\t\t\t\t\t\t\t\t\t{ local trl:2 = 0x187; export *[DATA]:1 trl; } # TRISB\ntrisREG: \"7\"\tis l5=7\t\t\t\t\t\t\t\t\t\t\t\t{ local trl:2 = 0x188; export *[DATA]:1 trl; } # TRISC\n@elif PROCESSOR == \"PIC_16F\"\ntrisREG: \"5\"\tis l5=5\t\t\t\t\t\t\t\t\t\t\t\t{ local trl:2 = 0x10C; export *[DATA]:1 trl; } # TRISA\ntrisREG: \"6\"\tis l5=6\t\t\t\t\t\t\t\t\t\t\t\t{ local trl:2 = 0x10D; export *[DATA]:1 trl; } # TRISB\ntrisREG: \"7\"\tis l5=7\t\t\t\t\t\t\t\t\t\t\t\t{ local trl:2 = 0x10E; export *[DATA]:1 trl; } # TRISC\n@endif\n\n:^instruction is possibleSkip=1 & instruction [ possibleSkip=0; ] {\n\tif (SkipNext) goto inst_next;\n\tbuild instruction;\n}\n\n\n\n#\n# BYTE-ORIENTED FILE REGISTER OPERATIONS\n#\n\n@if PROCESSOR == \"PIC_16F\"\n\n:ADDFSR fsrk, sk6\tis op7=0x62 & fsrk & sk6 {\n\tfsrk = fsrk + sk6;\n}\n@endif\n\n:ADDLW imm8\t\t\t\tis op6=0x3e & imm8\t\t\t\t\t\t\t\t{\n\t# --11 111x kkkk kkkk\n\t# 0011 1110 0001 0010\t->\tADDLW #0x12\n\tsetAddFlags(W, imm8); \n\tW = W + imm8;\n\tsetResultFlags(W);\n}\n\n:ADDWF srcREG, D\tis op6=0x07 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 0111 dfff ffff\n\t# 0000 0111 0000 0000\t->\tADDWF INDF, 0 \n\t# 0000 0111 1000 0000\t->\tADDWF INDF, 1\n\t# 0000 0111 0010 0000\t->\tADDWF 0x20, 0\n\t# 0000 0111 1010 0000\t->\tADDWF 0x20, 1\n\tval:1 = srcREG;\n\tsetAddFlags(W, val); \n\tval = W + val;\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:ADDWF PC, D\t\tis op6=0x07 & D & d=1 & f7=0x02 & PC\t{\n\t# --00 0111 dfff ffff\n\t# 0000 0111 1000 0010 -> ADDWF PCL, w, ACCESS\n\taddr:2 = inst_start >> 1; # Compenstate for CODE wordsize\n\tPCLATH = addr(1);\n\ttmp:1 = addr:1;\n\tsetAddFlags(tmp, W);\n\ttmp = tmp + W;\n\taddr = ((zext(PCLATH) & 0x1F) << 8) | zext(tmp);\n\tPCL = tmp;\n\tsetResultFlags(tmp);\n\tgoto [addr];\n}\n\n:ADDWFC srcREG, D\tis op6=0x3D & srcREG & D & destREG\t\t\t\t\t{\n\tval:1 = srcREG;\n\tlocal tmpC = $(C);\n\t\n\tsetAddFlags(W, val);\n\tval = W + val;\n\tlocal tc = $(C);\n\t\n\tsetAddFlags(val,tmpC);\n\t$(C) = $(C) | tc;\n\tval = val + tmpC;\n\t\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:ADDWFC PC, D\t\tis op6=0x3D & D & d=1 & f7=0x02 & PC\t{\n\t# --00 0111 dfff ffff\n\t# 0000 0111 1000 0010 -> ADDWF PCL, w, ACCESS\n\taddr:2 = inst_start >> 1; # Compenstate for CODE wordsize\n\tPCLATH = addr(1);\n\tval:1 = addr:1;\n\t\n\tlocal tmpC = $(C);\n\tsetAddFlags(W, val);\n\tlocal tc = $(C);\n\tval = W + val;\n\n\tsetAddFlags(val,tmpC);\n\t$(C) = $(C) | tc;\n\tval = val + tmpC;\n\t\n\taddr = ((zext(PCLATH) & 0x1F) << 8) | zext(val);\n\tPCL = val;\n\tsetResultFlags(val);\n\tgoto [addr];\n}\n\n:ANDLW imm8\t\t\t\tis op6=0x39 & imm8\t\t\t\t\t\t\t\t{\n\t# --11 1001 kkkk kkkk\n\t# 0011 1001 0001 0010\t->\tANDLW #0x12\n\tW = W & imm8;\n\tsetResultFlags(W);\n}\n\n:ANDWF srcREG, D\tis op6=0x05 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 0101 dfff ffff\n\t# 0000 0101 0000 0000\t->\tANDWF INDF, 0 \n\t# 0000 0101 1000 0000\t->\tANDWF INDF, 1\n\t# 0000 0101 0010 0000\t->\tANDWF 0x20, 0\n\t# 0000 0101 1010 0000\t->\tANDWF 0x20, 1\n\tval:1 = srcREG;\n\tval = W & val;\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:ASRF srcREG, D\t\t\t\tis op6=0x37 & srcREG & D & destREG\t\t\t\t\t{\n\t# --11 0111 dfff ffff\n\t$(C) = srcREG & 0x1;\n\tval:1 = srcREG s>> 1;\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:BCF srcREG, bit\t\t\tis op4=0x4 & srcREG & bit\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0010 0000 0000\t->\tBCF INDF, #0x4\n\t# 0001 0010 0010 0000\t->\tBCF 0x20, #0x4\n\tlocal bitmask = ~(1 << bit);\n\tsrcREG = srcREG & bitmask;\n}\n\n\n:BCF srcREG, IntConBits\t\t\tis op4=0x4 & f7=0xb & bit & srcREG & IntConBits\t\t\t\t\t\t\t{\n\tlocal bitmask = ~(1 << bit);\n\tsrcREG = srcREG & bitmask;\n}\n\n:BCF STATUS, \"C\"\t\t\tis op4=0x4 & b3=0 & f7=0x3 & STATUS\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0000 0000 0011\t->\tBCF STATUS, #C\n\t$(C) = 0;\n}\n\n:BCF STATUS, \"DC\"\t\tis op4=0x4 & b3=1 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0000 1000 0011\t->\tBCF STATUS, #DC\n\t$(DC) = 0;\n}\n\n\n:BCF STATUS, \"Z\"\t\t\tis op4=0x4 & b3=2 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0001 0000 0011\t->\tBCF STATUS, #Z\n\t$(Z) = 0;\n}\n\n\n:BCF STATUS, \"RP0\"\t\t\tis op4=0x4 & b3=5 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0010 1000 0011\t->\tBCF STATUS, #RP0\n\tRP = RP & 0x2;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n\n:BCF STATUS, \"RP1\"\t\t\tis op4=0x4 & b3=6 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0011 0000 0011\t->\tBCF STATUS, #RP1\n\tRP = RP & 0x1;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n\n:BCF STATUS, \"IRP\"\t\t\tis op4=0x4 & b3=7 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 00bb bfff ffff\n\t# 0001 0011 1000 0011\t->\tBCF STATUS, #IRP\n\tIRP = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BSF srcREG, bit\t\t\tis op4=0x5 & bit & srcREG\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0110 0000 0000\t->\tBSF INDF, #0x4\n\t# 0001 0110 0010 0000\t->\tBSF 0x20, #0x4\n\tlocal bitmask = 1 << bit;\n\tsrcREG = srcREG | bitmask;\n}\n\n:BSF srcREG, IntConBits\t\t\tis op4=0x5 & f7=0xb & bit & srcREG & IntConBits\t\t\t\t\t\t\t{\n\tlocal bitmask = 1 << bit;\n\tsrcREG = srcREG | bitmask;\n}\n\n:BSF STATUS, \"C\"\t\t\tis op4=0x5 & b3=0 & f7=0x3 & STATUS\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0100 0000 0011\t->\tBSF STATUS, #C\n\t$(C) = 1;\n}\n\n:BSF STATUS, \"DC\"\t\t\tis op4=0x5 & b3=1 & f7=0x3 & STATUS\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0100 1000 0011\t->\tBSF STATUS, #DC\n\t$(DC) = 1;\n}\n\n:BSF STATUS, \"Z\"\t\t\tis op4=0x5 & b3=2 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0111 0000 0011\t->\tBSF STATUS, #Z\n\t$(Z) = 1;\n}\n\n:BSF STATUS, \"RP0\"\t\t\tis op4=0x5 & b3=5 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0110 1000 0011\t->\tBSF STATUS, #RP0\n\tRP = RP | 0x1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF STATUS, \"RP1\"\t\t\tis op4=0x5 & b3=6 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0111 0000 0011\t->\tBSF STATUS, #RP1\n\tRP = RP | 0x2;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n\n:BSF STATUS, \"IRP\"\t\t\tis op4=0x5 & b3=7 & f7=0x3 & STATUS & bit\t\t\t\t\t\t\t{\n\t# --01 01bb bfff ffff\n\t# 0001 0111 1000 0011\t->\tBSF STATUS, #IRP\n\tIRP = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BTFSC srcREG, bit\t\tis op4=0x6 & bit & srcREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 10bb bfff ffff\n\t# 0001 1010 0000 0000\t->\tBTFSC INDF, #0x4\n\t# 0001 1010 0010 0000\t->\tBTFSC 0x20, #0x4\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcREG & bitmask;\n\tSkipNext = (tmp == 0); \n}\n\n:BC absAddr11\tis doPseudo=1 & op4=0x6 & b3=0 & bit & f7=0x3 ; op3=0x5 & absAddr11 {\n\tif ($(C) == 0) goto inst_next;\n\tgoto [absAddr11];\n}\n\n@if PROCESSOR == \"PIC_16F\"\n\n:BRA relAddr9 is op5=0x19 & relAddr9 {\n\tgoto [relAddr9];\n}\n\n:BRW \t\t\tis op14=0xb {\n\t# inst_next is byte, not word offset, need to load PC with word offset\n\tPC = (inst_next >> 1) + zext(W);\n\tgoto [PC];\n}\n\n@endif\n\n:BTFSC STATUS, bit\t\tis op4=0x6 & b3=0 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 10bb bfff ffff\n\t# 0001 1000 0000 0011\t->\tBTFSC STATUS, #C\n\tSkipNext = ($(C) == 0);\n}\n\n:SKPC is doPseudo=1 & op4=0x6 & b3=0 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n SkipNext = ($(C) == 1);\n}\n\n:SKPNC is doPseudo=1 & op4=0x7 & b3=0 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n SkipNext = ($(C) != 1);\n}\n\n:SKPZ is doPseudo=1 & op4=0x6 & b3=2 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n SkipNext = ($(Z) == 1);\n}\n\n:SKPNZ is doPseudo=1 & op4=0x7 & b3=2 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n SkipNext = ($(Z) != 1);\n}\n\n:BTFSC STATUS, bit\t\tis op4=0x6 & b3=1 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 10bb bfff ffff\n\t# 0001 1000 1000 0011\t->\tBTFSC STATUS, #DC\n SkipNext = ($(DC) == 0);\n}\n\n:BZ absAddr11\tis doPseudo=1 & op4=0x6 & b3=2 & bit & f7=0x3 ; op3=0x5 & absAddr11 {\n\tif ($(Z) == 0) goto inst_next;\n\tgoto [absAddr11];\n}\n\n:BTFSC STATUS, bit\t\tis op4=0x6 & b3=2 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 10bb bfff ffff\n\t# 0001 1001 0000 0011\t->\tBTFSC STATUS, #Z\n SkipNext = ($(Z) == 0);\n}\n\n:BTFSS srcREG, bit\t\tis op4=0x7 & bit & srcREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 11bb bfff ffff\n\t# 0001 1110 0000 0000\t->\tBTFSS INDF, #0x4\n\t# 0001 1110 0010 0000\t->\tBTFSS 0x20, #0x4\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcREG & bitmask;\n SkipNext = (tmp != 0);\n}\n\n:BNC absAddr11\tis doPseudo=1 & op4=0x7 & b3=0 & bit & f7=0x3 ; op3=0x5 & absAddr11 {\n\tif ($(C) != 0) goto inst_next;\n\tgoto [absAddr11];\n}\n\n:BTFSS STATUS, bit\t\tis op4=0x7 & b3=0 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 11bb bfff ffff\n\t# 0001 1100 0000 0011\t->\tBTFSS STATUS, #C\n SkipNext = ($(C) != 0);\n}\n\n:BTFSS STATUS, bit\t\tis op4=0x7 & b3=1 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ]{\n\t# --01 11bb bfff ffff\n\t# 0001 1100 1000 0011\t->\tBTFSS STATUS, #DC\n SkipNext = ($(DC) != 0);\n}\n\n:BNZ absAddr11\tis doPseudo=1 & op4=0x7 & b3=2 & bit & f7=0x3 ; op3=0x5 & absAddr11 {\n\tif ($(Z) != 0) goto inst_next;\n\tgoto [absAddr11];\n}\n\n:BTFSS STATUS, bit\t\tis op4=0x7 & b3=2 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --01 11bb bfff ffff\n\t# 0001 1101 0000 0011\t->\tBTFSS STATUS, #Z\n SkipNext = ($(Z) != 0);\n}\n\n:CALL absAddr11\t\t\tis op3=0x4 & absAddr11\t\t\t\t\t\t\t{\n\t# --10 0kkk kkkk kkkk\n\t# 0010 0001 0010 0011\t->\tCALL 0x123\n\t# 0010 0000 0001 0000\t->\tCALL 0x10\n\tpush(&:2 inst_next);\n\tcall [absAddr11];\n}\n\n:CALLW\t\t\t\t\tis op14=0x000a\t\t\t\t\t\t{\n\t# --00 0000 0000 1010\n\tpush(&:2 inst_next);\n\tcall [W];\n}\n\t\n:CLRF srcREG\t\t\t\tis op6=0x01 & d=1 & srcREG\t\t\t\t\t\t{\n\t# --00 0001 1fff ffff\n\t# 0000 0001 1000 0000\t->\tCLRF INDF\n\t# 0000 0001 1010 0000\t->\tCLRF 0x20\n\tsrcREG = 0;\n\t$(Z) = 1;\n}\n\n:CLRF STATUS\t\t\t\tis op6=0x01 & d=1 & f7=0x3 & STATUS\t\t\t\t\t\t{\n\t# --00 0001 1fff ffff\n\t# 0000 0001 1000 0011\t->\tCLRF STATUS\n\tSTATUS = 0;\n\tIRP = 0;\n\tRP = 0;\n\t$(Z) = 0;\n\t$(DC) = 0;\n\t$(C) = 0;\n}\n\n:CLRW\t\t\t\t\tis op12=0b000001000000 & mm\t\t\t{\n\t# --00 0001 0xxx xxxx\n\t# 0000 0001 0000 0000\t->\tCLRW\n\tW = 0;\n\t$(Z) = 1;\n}\n\n:CLRWDT\t\t\t\t\tis op14=0x0064\t\t\t\t{\n\t# --00 0000 0110 0100\n\t# Clear Watchdog Timer - Not Implemented\n\tclearWatchDogTimer();\n}\n\n:COMF srcREG, D\t\tis op6=0x09 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 1001 dfff ffff\n\t# 0000 1001 0000 0000\t->\tCOMF INDF, 0 \n\t# 0000 1001 1000 0000\t->\tCOMF INDF, 1\n\t# 0000 1001 0010 0000\t->\tCOMF 0x20, 0\n\t# 0000 1001 1010 0000\t->\tCOMF 0x20, 1\n\ttmp:1 = ~srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:DECF srcREG, D\t\tis op6=0x03 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 0011 dfff ffff\n\t# 0000 0011 0000 0000\t->\tDECF INDF, 0 \n\t# 0000 0011 1000 0000\t->\tDECF INDF, 1\n\t# 0000 0011 0010 0000\t->\tDECF 0x20, 0\n\t# 0000 0011 1010 0000\t->\tDECF 0x20, 1\n\tval:1 = srcREG - 1;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n\n:DECFSZ srcREG, D\t\tis op6=0x0b & srcREG & D & destREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --00 1011 dfff ffff\n\t# 0000 1011 0000 0000\t->\tDECFSZ INDF, 0 \n\t# 0000 1011 1000 0000\t->\tDECFSZ INDF, 1\n\t# 0000 1011 0010 0000\t->\tDECFSZ 0x20, 0\n\t# 0000 1011 1010 0000\t->\tDECFSZ 0x20, 1\n\tval:1 = srcREG - 1;\n\tdestREG = val;\n\tSkipNext = (val == 0);\n}\n\n:GOTO absAddr11\t\t\tis op3=0x5 & absAddr11\t\t\t\t\t\t\t{\n\t# --10 1kkk kkkk kkkk\n\t# 0010 1001 0010 0011\t->\tGOTO 0x123\n\t# 0010 1000 0001 0000\t->\tGOTO 0x10\n\tgoto [absAddr11];\n}\n\n:INCF srcREG, D\t\tis op6=0x0a & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 1010 dfff ffff\n\t# 0000 1010 0000 0000\t->\tINCF INDF, 0 \n\t# 0000 1010 1000 0000\t->\tINCF INDF, 1\n\t# 0000 1010 0010 0000\t->\tINCF 0x20, 0\n\t# 0000 1010 1010 0000\t->\tINCF 0x20, 1\n\tval:1 = srcREG + 1;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n\n:INCFSZ srcREG, D\t\tis op6=0x0f & srcREG & D & destREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {\n\t# --00 1111 dfff ffff\n\t# 0000 1111 0000 0000\t->\tINCFSZ INDF, 0 \n\t# 0000 1111 1000 0000\t->\tINCFSZ INDF, 1\n\t# 0000 1111 0010 0000\t->\tINCFSZ 0x20, 0\n\t# 0000 1111 1010 0000\t->\tINCFSZ 0x20, 1\n\tval:1 = srcREG + 1;\n\tdestREG = val;\n SkipNext = (val == 0);\n}\n\n:IORLW imm8\t\t\t\tis op6=0x38 & imm8\t\t\t\t\t\t\t\t{\n\t# --11 1000 kkkk kkkk\n\t# 0011 1000 0001 0010\t->\tIORLW #0x12\n\tW = W | imm8;\n\tsetResultFlags(W);\n}\n\n:IORWF srcREG, D\t\tis op6=0x04 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 0100 dfff ffff\n\t# 0000 0100 0000 0000\t->\tIORWF INDF, 0 \n\t# 0000 0100 1000 0000\t->\tIORWF INDF, 1\n\t# 0000 0100 0010 0000\t->\tIORWF 0x20, 0\n\t# 0000 0100 1010 0000\t->\tIORWF 0x20, 1\n\tval:1 = W | srcREG;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n\n@if PROCESSOR == \"PIC_16F\"\n\nsrcFSR: \"++\"fsr\t\tis fsr & mm=0 { fsr = fsr + 1; addr:2 = fsr; export *[DATA]:1 addr; }\nsrcFSR: \"--\"fsr\t\tis fsr & mm=1 { fsr = fsr - 1; addr:2 = fsr; export *[DATA]:1 addr; }\nsrcFSR: fsr\"++\"\t\tis fsr & mm=2 { addr:2 = fsr; fsr = fsr + 1; export *[DATA]:1 addr; }\nsrcFSR: fsr\"--\"\t\tis fsr & mm=3 { addr:2 = fsr; fsr = fsr - 1; export *[DATA]:1 addr; }\n\nsrcFSRk: sk6\"[\"fsrk\"]\" is fsrk & sk6 {\n\taddr:2 = fsrk + sk6; export *[DATA]:1 addr;\n}\n\n:LSLF srcREG, D\t\t\t\tis op6=0x35 & srcREG & D & destREG\t\t\t\t\t{\n\t# --11 0101 dfff ffff\n\t$(C) = (srcREG & 0x80) != 0;\n\tval:1 = srcREG << 1;\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:LSRF srcREG, D\t\t\t\tis op6=0x36 & srcREG & D & destREG\t\t\t\t\t{\n\t# --11 0110 dfff ffff\n\t$(C) = srcREG & 0x1;\n\tval:1 = srcREG >> 1;\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:MOVIW srcFSR\t\t\tis op11=2 & srcFSR {\n\tW = srcFSR;\n\tsetResultFlags(W);\n}\n\n:MOVIW srcFSRk\t\t\tis op7=0x7e & srcFSRk {\n\tW = srcFSRk;\n\tsetResultFlags(W);\n}\n\n:MOVWI srcFSR\t\t\tis op11=3 & srcFSR {\n\tsrcFSR = W;\n}\n\n:MOVWI srcFSRk\t\t\tis op7=0x7f & srcFSRk {\n\tsrcFSRk = W;\n}\n\n:MOVLB imm5\t\t\tis op9=0x1 & imm5 {\n\tBSR = imm5;\n}\n\n# Alternate variant in certain pic16f variants\n:MOVLB imm6\t\t\tis op8=0x5 & imm6 {\n\tBSR = imm6;\n}\n\n:MOVLP imm7\t\t\t\tis op7=0x63 & imm7 {\n\tPCLATH = imm7 & 0x1F;\n}\n@endif\n\n:MOVLW imm8\t\t\t\tis op6=0x30 & imm8\t\t\t\t\t\t\t\t{\n\t# --11 00xx kkkk kkkk\n\t# 0011 0000 0001 0010\t->\tMOVLW #0x12\n\tW = imm8;\n}\n\n:MOVF srcREG, D\t\tis op6=0x08 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 1000 dfff ffff\n\t# 0000 1000 0000 0000\t->\tMOVF INDF, 0 \n\t# 0000 1000 1000 0000\t->\tMOVF INDF, 1\n\t# 0000 1000 0010 0000\t->\tMOVF 0x20, 0\n\t# 0000 1000 1010 0000\t->\tMOVF 0x20, 1\n\tval:1 = srcREG;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n\n:MOVWF srcREG\t\t\t\tis op6=0x00 & d=1 & srcREG\t\t\t\t\t\t{\n\t# --00 0000 1fff ffff\n\t# 0000 0000 1000 0000\t->\tMOVWF INDF\n\t# 0000 0000 1010 0000\t->\tMOVWF 0x20\n\tsrcREG = W;\n}\n\n:MOVWF PC\t\t\t\t\tis op6=0x00 & d=1 & f7=0x02 & PC\t\t\t \t\t\t\t{\n\t# --00 0000 1fff ffff\n\t# 0000 0000 1000 0010\t->\tMOVWF PCL\n\tPCL = W;\n\taddr:2 = ((zext(PCLATH) & 0x1F) << 8) | zext(PCL);\n\tgoto [addr];\n}\n\n:NOP\t\t\t\t\tis op6=0 & d=0 & l5=0\t\t\t\t{\n\t# --00 0000 0xx0 0000\n}\n\n:OPTION\t\t\t\t\tis op14=0x0062\t\t\t\t\t\t{\n\t# --00 0000 0110 0010\n\tOPTION = W;\n}\n\n:RESET is op14=0x0001 {\n\treset();\n\tgoto 0x0;\n}\n\n:RETFIE\t\t\t\t\tis op14=0x0009\t\t\t\t\t\t{\n\t# --00 0000 0000 1001\n\tINTCON = 0x80 | INTCON; # set INTCON.GIE bit\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETLW imm8\t\t\t\tis op4=0xd & imm8\t\t\t\t\t\t\t\t{\n\t# --11 01xx kkkk kkkk\n\t# 0011 0100 0001 0010\t->\tRETLW #0x12\n\tW = imm8;\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETURN\t\t\t\t\tis op14=0x0008\t\t\t\t\t\t{\n\t# --00 0000 0000 1000\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RLF srcREG, D\t\tis op6=0x0d & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 1101 dfff ffff\n\t# 0000 1101 0000 0000\t->\tRLF INDF, 0 \n\t# 0000 1101 1000 0000\t->\tRLF INDF, 1\n\t# 0000 1101 0010 0000\t->\tRLF 0x20, 0\n\t# 0000 1101 1010 0000\t->\tRLF 0x20, 1\n\tlocal tmpC = $(C);\n\tval:1 = srcREG;\n\t$(C) = (val s< 0);\n\tval = (val << 1) | tmpC;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n\n:RRF srcREG, D\t\tis op6=0x0c & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 1100 dfff ffff\n\t# 0000 1100 0000 0000\t->\tRRF INDF, 0 \n\t# 0000 1100 1000 0000\t->\tRRF INDF, 1\n\t# 0000 1100 0010 0000\t->\tRRF 0x20, 0\n\t# 0000 1100 1010 0000\t->\tRRF 0x20, 1\n\tlocal tmpC = $(C) << 7;\n\tval:1 = srcREG;\n\t$(C) = (val & 1) != 0;\n\tval = (val >> 1) | tmpC;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n\n:SLEEP\t\t\t\t\tis op14=0x0063\t\t\t\t{ \n\t# --00 0000 0110 0011\n\t# Sleep - Not Implemented\n\tsleep();\n}\n\n:SUBLW imm8\t\t\t\tis op6=0x3c & imm8\t\t\t\t\t\t\t\t{\n\t# --11 110x kkkk kkkk\n\t# 0011 1100 0001 0010\t->\tSUBLW #0x12\n\tsetSubtractFlags(imm8, W); \n\tW = imm8 - W;\n\tsetResultFlags(W);\n}\n\n:SUBWF srcREG, D\t\tis op6=0x02 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 0010 dfff ffff\n\t# 0000 0010 0000 0000\t->\tSUBWF INDF, 0 \n\t# 0000 0010 1000 0000\t->\tSUBWF INDF, 1\n\t# 0000 0010 0010 0000\t->\tSUBWF 0x20, 0\n\t# 0000 0010 1010 0000\t->\tSUBWF 0x20, 1\n\tval:1 = srcREG;\n\tsetSubtractFlags(val, W); \n\tval = val - W;\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:SUBWFB srcREG, D\t\tis op6=0x3b & srcREG & D & destREG {\n\tval:1 = srcREG;\n\tbor:1 = !$(C);\n\n\tsetSubtractFlags(val, W);\n\tval = val - W;\n\ttb:1 = $(C);\n\n\tsetSubtractFlags(val,bor);\n\t# first subtraction could cause borrow\n\t$(C) = $(C) & tb; # borrow if C not set\n\tval = val - bor;\n\n\tsetResultFlags(val);\n\tdestREG = val;\n}\n\n:SWAPF srcREG, D\t\tis op6=0x0e & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 1110 dfff ffff\n\t# 0000 1110 0000 0000\t->\tSUBWF INDF, 0 \n\t# 0000 1110 1000 0000\t->\tSUBWF INDF, 1\n\t# 0000 1110 0010 0000\t->\tSUBWF 0x20, 0\n\t# 0000 1110 1010 0000\t->\tSUBWF 0x20, 1\n\tval:1 = srcREG;\n\tdestREG = (val << 4) | (val >> 4);\n}\n\n:TRIS trisREG\t\t\t\tis op9=0x3 & trisREG\t\t\t\t{\n\t# --00 0000 0110 0fff\n\t# 0000 0000 0110 0101\t->\tTRIS 5\n\ttrisREG = W;\n}\n\n:XORLW imm8\t\t\t\tis op6=0x3a & imm8\t\t\t\t\t\t\t\t{\n\t# --11 1010 kkkk kkkk\n\t# 0011 1010 0001 0010\t->\tXORLW #0x12\n\tW = imm8 ^ W;\n\tsetResultFlags(W);\n}\n\n:XORWF srcREG, D\t\tis op6=0x06 & srcREG & D & destREG\t\t\t\t\t{\n\t# --00 0110 dfff ffff\n\t# 0000 0110 0000 0000\t->\tXORWF INDF, 0 \n\t# 0000 0110 1000 0000\t->\tXORWF INDF, 1\n\t# 0000 0110 0010 0000\t->\tXORWF 0x20, 0\n\t# 0000 0110 1010 0000\t->\tXORWF 0x20, 1\n\tval:1 = W ^ srcREG;\n\tdestREG = val;\n\tsetResultFlags(val);\n}\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16c5x.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16c5x.ldefs", "content": "\n\n\n \n PIC-16C5x\n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16c5x.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16c5x.slaspec", "content": "@define PROCESSOR \"PIC_12C5XX\"\n\n@include \"pic12.sinc\"\n\n#\n# NOTES\t-\n#\t1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and\n# slightly modified to specify a the correct Register File Map.\n#\n\n# Bank-0 File Registers\ndefine DATA offset=0x00 size=1 [\n\tINDF\tTMR0\tPCL.0\tSTATUS.0 FSR.0\tPORTA\tPORTB\tPORTC\n];\n\n@include \"pic12_instructions.sinc\"\n\n# IO Tristate Registers\ndefine register offset=0x0020 size=1 [ TRISA TRISB TRISC ];\n\n# TRIS register\ntrisREG: \"5\"\tis f5=0x5\t\t\t\t\t\t\t\t{ export TRISA; }\ntrisREG: \"6\"\tis f5=0x6\t\t\t\t\t\t\t\t{ export TRISB; }\ntrisREG: \"7\"\tis f5=0x7\t\t\t\t\t\t\t\t{ export TRISC; }\n\n:TRIS trisREG\t\t\t\tis op6=0x00 & d=0 & trisREG\t\t\t\t\t{\n\t# ---- 0000 0000 0fff\n\t# 0000 0000 0000 0110\t->\tTRIS 6\n\ttrisREG = W;\n}\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16f.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16f.pspec", "content": "\n\n\n \n \n \n \t\n \t\t\n \t\n \t\n \t\t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \t\n \t \t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic16f.slaspec", "content": "@define PROCESSOR \"PIC_16F\"\n\n@include \"pic16.sinc\"\n\n@include \"pic16_instructions.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/pic17c7xx.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic17c7xx.ldefs", "content": "\n\n\n \n PIC-17C7xx\n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic17c7xx.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic17c7xx.sinc", "content": "#\n# PIC-17C7xx Main Section\n# includes constants, memory space and common register space definitions\n#\n\n@define SFR_BASE 0x0F80\n@define BANK15_BASE 0x0F00\n\n# ALUSTA bit definitions\n@define STATUS_OV_BIT\t3\n@define STATUS_Z_BIT\t2\n@define STATUS_DC_BIT\t1\n@define STATUS_C_BIT\t0\n\n# ALUSTA bit masks used for clearing\n@define STATUS_OV_CLEARMASK\t0xF7\n@define STATUS_Z_CLEARMASK\t0xFB\n@define STATUS_DC_CLEARMASK\t0xFD\n@define STATUS_C_CLEARMASK\t0xFE\n\ndefine endian=little;\ndefine alignment=2;\n\n# Instruction Memory (ROM-based)\ndefine space CODE type=ram_space wordsize=2 size=2 default;\n\n# General Purpose Register Memory\n# 0x00 - 0x0f : Unbanked registers\n# 0x10 - 0x17 : Banked registers (9 banks controlled by lower nibble of BSR)\n# 0x18 - 0x19 : Unbanked registers\n# 0x1a - 0x1f : Unbanked GPRs\n# 0x20 - 0xff : Banked GPRs (4 banks controlled by upper nibble of BSR)\ndefine space DATA type=ram_space size=2; \n\n# The HWSTACK consists of a 16_word by 16_bit RAM and a corresponding 4_bit STKPTR register (which is not readable or writable).\n# There is no means of directly accessing the stack space other than via a CALL, RETURN, RETLW or RETFIE\ndefine space HWSTACK type=ram_space size=1; # implemented as independently addressable bytes (each location is 2-bytes wide)\n \ndefine space register type=register_space size=2; \n\n# Program Counter\ndefine register offset=0x0000 size=2 [ PC ];\n\n# Stack Pointer (4-bits)\ndefine register offset=0x0004 size=1 [ STKPTR ];\n\n# ALUSTA bit registers (these do not really exist and must get reflected into the STATUS byte register)\ndefine register offset=0x0005 size=1 [ FS32 FS10 OV Z DC C ];\n\n# Table Latch (not visible)\ndefine register offset=0x0010 size=1 [ TBLATL TBLATH ];\ndefine register offset=0x0010 size=2 [ TBLAT ];\n\n# Mirrored registers for improved decompiler behavior\ndefine register offset=0x0020 size=1 [ WREG ];\n" }, { "path": "pypcode/processors/PIC/data/languages/pic17c7xx.slaspec", "content": "@define PROCESSOR \"PIC_17C7xx\"\n\n@include \"pic17c7xx.sinc\"\n\n# 0x00 - 0x0f (Unbanked - BSR ignored, WREG hidden and mirrored in register space)\ndefine DATA offset=0x000 size=1 [\n\tINDF0\tFSR0\tPCL\t\tPCLATH\tALUSTA\tT0STA\tCPUSTA\tINTSTA\tINDF1\tFSR1\t_\tTMR0L\tTMR0H\tTBLPTRL\tTBLPTRH\tBSR\n];\n\n# Bank-0 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x010 size=1 [\n\tPORTA\tDDRB\tPORTB\tRCSTA1\tRCREG1\tTXSTA1\tTXREG1\tSPBRG1\n];\n\n# Bank-1 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x110 size=1 [\n\tDDRC\tPORTC\tDDRD\tPORTD\tDDRE\tPORTE\tPIR1\tPIE1\n];\n\n# Bank-2 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x210 size=1 [\n\tTMR1\tTMR2\tTMR3L\tTMR3H\tPR1\t\tPR2\t\tPR3LCA1L\tPR3HCA1H\n];\n\n# Bank-3 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x310 size=1 [\n\tPW1DCL\tPW2DCL\tPW1DCH\tPW2DCH\tCA2L\tCA2H\tTCON1\tTCON2\n];\n\n# Bank-4 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x410 size=1 [\n\tPIR2\tPIE2\t_\t\tRCSTA2\tRCREG2\tTXSTA2\tTXREG2\tSPBRG2\n];\n\n# Bank-5 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x510 size=1 [\n\tDDRF\tPORTF\tDDRG\tPORTG\tADCON0\tADCON1\tADRESL\tADRESH\n];\n\n# Bank-6 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x610 size=1 [\n\tSSPADD\tSSPCON1\tSSPCON2\tSSPSTAT\tSSPBUF\n];\n\n# Bank-7 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x710 size=1 [\n\tPW3DCL\tPW3DCH\tCA3L\tCA3H\tCA4L\tCA4H\tTCON3\n];\n\n# Bank-8 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>)\ndefine DATA offset=0x810 size=1 [\n\tDDRH\tPORTH\tDDRJ\tPORTJ\n];\n\n# 0x18 - 0x1f (Unbanked - BSR ignored)\ndefine DATA offset=0x018 size=1 [\n\tPRODL\tPRODH\n];\n\ndefine DATA offset=0x00d size=2 [ TBLPTR ];\ndefine DATA offset=0x002 size=2 [ PCLAT ];\n\ndefine DATA offset=0x018 size=2 [ PROD ];\n\ndefine DATA offset=0x516 size=2 [ ADRES ];\n\n@include \"pic17c7xx_instructions.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/pic17c7xx_instructions.sinc", "content": "#\n# PIC-17C7xx Instruction Section\n# includes token definitions, macros, sub-constructors and instruction definitions\n#\n\n# 16-bit instruction token uses big-endian bit numbering which agrees with\n# instruction bit numbering with PIC documentation.\n# \t15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0 \ndefine token instr16(16)\n\top16 =\t(0,15)\n\top8 =\t(8,15)\n\top7 =\t(9,15)\n\top6 =\t(10,15)\n\top5 =\t(11,15)\n\top3 =\t(13,15)\n\tt =\t\t(9,9)\n\td =\t\t(8,8)\n\ts =\t\t(8,8)\n\ti =\t\t(8,8)\n\tb3 =\t(8,10)\n\tp5_4 =\t(12,12)\n\tp5_3 =\t(11,11)\n\tp5 =\t(8,12)\n\tp5reg =\t(8,12)\n\tu4hi =\t(4,7)\n\tu4lo =\t(0,3)\n\tf8 =\t(0,7)\n\tf8hi =\t(5,7)\n\tf8_4 =\t(4,4)\n\tf8_3 =\t(3,3)\n\tf8reg = (0,4) \n\tk8 =\t(0,7)\n\tk8_h =\t(4,7)\n\tk8_l =\t(0,3)\n\tk13 =\t(0,12)\n;\n\nattach variables [ f8reg p5reg ] [ \n INDF0\tFSR0\tPCL\t\tPCLATH\tALUSTA\tT0STA\tCPUSTA\tINTSTA\n \tINDF1\tFSR1\tWREG\tTMR0L\tTMR0H\tTBLPTRL\tTBLPTRH\tBSR\n \t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n \tPRODL\tPRODH\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n];\n\nattach variables [ t ] [ TBLATL TBLATH ];\n\n#\n# Special PIC-17 Operations\n#\n\n# Return a decimal adjusted value for the value provided (see DAW instruction)\ndefine pcodeop decimalAdjust;\n\n# Perform a Master Clear Reset\ndefine pcodeop reset;\n\ndefine pcodeop clearWatchDogTimer;\n\ndefine pcodeop sleep;\n\n#\n# MACROS\n#\n\nmacro setResultFlags(result) {\n\tZ = (result == 0);\n}\n\nmacro setAddCOverflowFlag(op1,op2) {\n\tlocal tmpC = C & 1;\n\tOV = scarry(op1,tmpC) || scarry(op2,op1 + tmpC);\n}\n\nmacro setAddCCarryFlag(op1,op2) {\n\tlocal tmpC = C & 1;\n\tC = carry(op1,tmpC) || carry(op2,op1 + tmpC);\n}\n\nmacro setAddCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tmpDC = DC & 1;\n\tDC = carry(tmp1,tmpDC) || carry(tmp2,tmp1 + tmpDC);\n}\n\nmacro setAddCFlags(op1,op2) {\n\tsetAddCCarryFlag(op1,op2);\n\tsetAddCDigitCarryFlag(op1,op2);\n\tsetAddCOverflowFlag(op1,op2);\n}\n\nmacro setAddFlags(op1,op2) {\n\tC = carry(op1,op2);\n\tDC = carry(op1<<4,op2<<4);\n\tOV = scarry(op1,op2);\n}\n\nmacro setSubtractCOverflowFlag(op1,op2) {\n\tlocal notC = ~(C & 1);\n\tOV = sborrow(op1,notC) || sborrow(op2,op1 - notC);\n}\n\nmacro setSubtractCCarryFlag(op1,op2) {\n\tlocal notC = ~(C & 1);\n\tC = (op1 < notC) || (op2 < (op1 - notC));\n}\n\nmacro setSubtractCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal notDC = ~(DC & 1);\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tmp3 = (tmp1 - notDC) << 4;\n\tDC = (tmp1 < notDC) || (tmp2 < tmp3);\n}\n\nmacro setSubtractCFlags(op1,op2) {\n\tsetSubtractCCarryFlag(op1,op2);\n\tsetSubtractCDigitCarryFlag(op1,op2);\n\tsetSubtractCOverflowFlag(op1,op2);\n}\n\nmacro setSubtractFlags(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\t# NOTE: carry flag is SET if there is NO borrow\n\tC = (op1 >= op2);\n\tDC = ((op1<<4) < (op2<<4));\n\tOV = sborrow(op1,op2);\n}\n\nmacro push(val) {\t# TODO: Uncertain about this !!\n#\tCheckStackFull();\n\t*[HWSTACK]:2 STKPTR = val;\n\tSTKPTR = STKPTR + 2;\n}\n\nmacro pop(rval) {\t# TODO: Uncertain about this !!\n#\tCheckStackUnderflow();\n\tSTKPTR = STKPTR - 2;\n\trval = *[HWSTACK]:2 STKPTR;\n}\n\n#\n# SUB-CONSTRUCTORS\n#\n\n# PC register write - instruction must set PCLATH/PCL and perform branch operation\nfPC: \"PC\" \t\t\tis f8=0x02\t\t\t\t{ export PCL; }\npPC: \"PC\" \t\t\tis p5=0x02\t\t\t\t{ export PCL; }\n\n# ALUSTA register\nfALUSTA: f8reg \t\tis f8=0x04 & f8reg\t\t{ export f8reg; }\n#pALUSTA: p5reg \t\tis p5=0x04 & p5reg\t\t{ export p5reg; }\n\n#\n# f Register subconstructors\n#\n\n# 0x00-0x0f Unbanked registers\nfREGLoc: f8reg\t\tis f8hi=0 & f8_4=0 & f8reg\t\t\t{ export f8reg; }\n\n# 0x10-0x1f Banked registers\nfREGLoc: f8\t\t\tis f8hi=0 & f8_4=1 & f8_3=0 & f8\t{ ptr:2 = (zext(BSR & 0x0f) << 8) + f8; export *[DATA]:1 ptr; }\n\n# 0x18-0x19 Unbanked registers (PRODL,PRODH)\nfREGLoc: f8reg\t\tis f8=0x18 & f8reg\t\t\t\t\t{ export f8reg; }\nfREGLoc: f8reg\t\tis f8=0x19 & f8reg\t\t\t\t\t{ export f8reg; }\n\n# Unbanked general purpose RAM\nfREGLoc: f8\t\t\tis f8hi=0 & f8_4=1 & f8_3=1 & f8\t{ export *[DATA]:1 f8; }\n\n# Banked general purpose RAM\nfREGLoc: f8\t\t\tis f8\t\t\t\t\t\t\t\t{ ptr:2 = (zext(BSR & 0xf0) << 4) + f8; export *[DATA]:1 ptr; }\n\n\n# Indirect File Register access - INDF0\nfREGLoc: f8reg\t\tis f8=0x00 & f8reg\t\t{\n\taddr:1 = FSR0;\n\tval:1 = ((FS10 == 0x1) * 1) + ((FS10 == 0x0) * -1);\n\tFSR0 = addr + val;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF1\nfREGLoc: f8reg\t\tis f8=0x08 & f8reg\t\t{\n\taddr:1 = FSR1;\n\tval:1 = ((FS32 == 0x1) * 1) + ((FS32 == 0x0) * -1);\n\tFSR1 = addr + val;\n\texport *[DATA]:1 addr; \n}\n\n\n#\n# p Register subconstructors\n#\n\n# 0x00-0x0f Unbanked registers\npREGLoc: p5reg\t\tis p5_4=0 & p5reg\t\t\t{ export p5reg; }\n\n# 0x10-0x17 Banked registers\npREGLoc: p5\t\t\tis p5_4=1 & p5_3=0 & p5\t\t{ ptr:2 = (zext(BSR & 0x0f) << 8) + p5; export *[DATA]:1 ptr; }\n\n# 0x18-0x19 Unbanked registers (PRODL,PRODH)\npREGLoc: p5reg\t\tis p5=0x18 & p5reg\t\t\t{ export p5reg; }\npREGLoc: p5reg\t\tis p5=0x19 & p5reg\t\t\t{ export p5reg; }\n\n# Unbanked general purpose RAM\npREGLoc: p5\t\t\tis p5_4=1 & p5_3=1 & p5\t{ export *[DATA]:1 p5; }\n\n# Indirect File Register access - INDF0\npREGLoc: p5reg\t\tis p5=0x00 & p5reg\t\t{\n\taddr:1 = FSR0;\n\tval:1 = ((FS10 == 0x1) * 1) + ((FS10 == 0x0) * -1);\n\tFSR0 = addr + val;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF1\npREGLoc: p5reg\t\tis p5=0x08 & p5reg\t\t{\n\taddr:1 = FSR1;\n\tval:1 = ((FS32 == 0x1) * 1) + ((FS32 == 0x0) * -1);\n\tFSR1 = addr + val;\n\texport *[DATA]:1 addr; \n}\n\n\n# Direct File register data\nsrcFREG: fREGLoc\t\tis fREGLoc\t\t\t\t\t\t\t\t\t{ export fREGLoc; }\n\n# PCL read - latch PC into PCL and PCLATH\nsrcFREG: \"PC\"\t\tis f8=0x02\t\t\t\t\t\t{\n\tPCLAT = inst_start;\n\texport PCL; \n}\n\n# Destination register (always fREGLoc)\ndestFREG: fREGLoc\t\tis fREGLoc\t\t\t\t\t\t\t\t\t{ export fREGLoc; }\n\n# Destination register (either fREGLoc or WREG)\ndestREG: \"0\"\tis d=0\t\t\t\t\t\t\t\t\t\t\t\t{ export WREG; }\ndestREG: \"1\"\tis d=1 & fREGLoc\t\t\t\t\t\t\t\t\t{ export fREGLoc; }\n\n# Direct File register data\nsrcPREG: pREGLoc\t\tis pREGLoc\t\t\t\t\t\t\t\t\t{ export pREGLoc; }\n\n# PCL read - latch PC into PCL and PCLATH\nsrcPREG: \"PC\"\t\tis p5=0x02\t\t\t\t\t\t{\n\tPCLAT = inst_start;\n\texport PCL; \n}\n\n# Destination register (always pREGLoc)\ndestPREG: pREGLoc\t\tis pREGLoc\t\t\t\t\t\t\t\t\t{ export pREGLoc; }\n\n# Destination operand representation (w: W register is destination; f: specified fREG is destination)\nD: \"w\"\t\tis d=0\t\t\t\t\t\t\t\t\t\t{ }\nD: \"f\"\t\tis d=1\t\t\t\t\t\t\t\t\t\t{ }\n\n# s-flag used by those instructions which can optionally store result in both srcFREG and WREG\nS: \"0\"\t\tis s=0\t\t\t\t\t\t\t\t\t\t{ }\nS: \"1\"\t\tis s=1\t\t\t\t\t\t\t\t\t\t{ }\n\n# Table read/write i-flag\nI: \"0\"\t\tis i=0\t\t\t\t\t\t\t\t\t\t{ }\nI: \"1\"\t\tis i=1\t\t\t\t\t\t\t\t\t\t{ }\n\n# Table read/write t-flag identifies table latch register (high or low byte)\nT: t\t\tis t\t\t\t\t\t\t\t\t\t\t{ export t; }\n\n# Relative instruction location with an 8K page\nshortAddr: nLoc is k13\t\t\t\t[ nLoc = (inst_next & 0xe000) + k13; ]\t{ \n\ttmp:2 = nLoc:2 >> 8;\n\tPCLATH = tmp:1;\n\texport *[CODE]:2 nLoc;\n}\n\n# Absolute instruction location within 64K space (PCLATH contain upper 8-bits)\nlongAddr: k8\tis k8\t\t\t\t\t\t\t\t\t\t\t\t\t\t{\n\taddr:2 = (zext(PCLATH) << 8) + k8;\n\texport addr;\n}\n\n# Skip instruction address\nskipInst: inst_skip\tis op16\t[ inst_skip = inst_next + 1; ]\t\t{export *[CODE]:2 inst_skip; }\n\n# Immediate Data (Literal operation)\nimm8: \"#\"k8\t\tis k8\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k8; }\nimm8h: \"#\"k8_h\tis k8_h\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k8_h; }\nimm8l: \"#\"k8_l\tis k8_l\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k8_l; }\n\n# Bit identifier\nbit: \"#\"b3\t\tis b3\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 b3; }\n\n\n#\n# Instructions\n#\n\n:ADDLW imm8\t\tis op8=0xb1 & imm8\t\t{\n\t# 1011 0001 kkkk kkkk\n\ttmp1:1 = WREG;\n\ttmp2:1 = imm8;\n\tsetAddFlags(tmp1, tmp2); \n\tlocal tmp = tmp1 + tmp2;\n\tWREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ADDWF srcFREG, D\tis op7=0x07 & D & srcFREG & destREG {\n\t# 0000 111d ffff ffff\n\ttmp1:1 = srcFREG; # read only once!\n\ttmp2:1 = WREG;\n\tsetAddFlags(tmp1, tmp2); \n\tlocal tmp = tmp1 + tmp2;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ADDWF fPC, D\t\tis op7=0x07 & D & d=1 & fPC\t{\n\t# 0000 111d ffff ffff\n\t# 0000 1110 ffff ffff -> ADDWF PCL, w\n\taddr:2 = inst_start >> 1; # Compenstate for CODE wordsize\n\taddrHi:1 = addr(1);\n\tPCLATH = addrHi;\n\taddrLo:1 = addr:1;\n\ttmpW:1 = WREG;\n\tsetAddFlags(addrLo, tmpW);\n\taddrLo = addrLo + tmpW;\n\taddr = (zext(addrHi) << 8) + zext(addrLo);\n\tsetResultFlags(addrLo);\n\tgoto [addr];\n}\n\n:ADDWFC srcFREG, D\tis op7=0x08 & D & srcFREG & destREG {\n\t# 0001 000d ffff ffff\n\tlocal tmpC = C & 1;\n\ttmp1:1 = srcFREG; # read only once!\n\ttmp2:1 = WREG;\n\tsetAddCFlags(tmp1, tmp2); \n\tlocal tmp = tmp1 + tmp2 + tmpC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ANDLW imm8\tis op8=0xb5 & imm8\t{\n\t# 1011 0101 kkkk kkkk\n\ttmp:1 = WREG & imm8;\n\tWREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ANDWF srcFREG, D\tis op7=0x05 & D & srcFREG & destREG {\n\t# 0000 101d ffff ffff\n\ttmp:1 = srcFREG & WREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:BCF srcFREG, bit\t\t\tis op5=0x11 & bit & srcFREG\t\t\t\t\t\t\t{\n\t# 1000 1bbb ffff ffff\n\tlocal bitmask = ~(1 << bit);\n\tsrcFREG = srcFREG & bitmask;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=0 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1000 0000 0100\t->\tBCF ALUSTA, #C\n\tC = 0;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=1 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1001 0000 0100\t->\tBCF ALUSTA, #DC\n\tDC = 0;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=2 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1010 0000 0100\t->\tBCF ALUSTA, #Z\n\tZ = 0;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=3 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1011 0000 0100\t->\tBCF ALUSTA, #OV\n\tOV = 0;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=4 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1100 0000 0100\t->\tBCF ALUSTA, #FS0\n\tFS10 = FS10 & 0x2;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=5 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1101 0000 0100\t->\tBCF ALUSTA, #FS1\n\tFS10 = FS10 & 0x1;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=6 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1110 0000 0100\t->\tBCF ALUSTA, #FS2\n\tFS32 = FS32 & 0x2;\n}\n\n:BCF fALUSTA, bit\t\t\tis op5=0x11 & b3=7 & fALUSTA & bit\t\t\t\t\t\t\t{\n\t# 1000 1111 0000 0100\t->\tBCF ALUSTA, #FS3\n\tFS32 = FS32 & 0x1;\n}\n\n:BSF srcFREG, bit\t\t\tis op5=0x10 & bit & srcFREG\t\t\t\t{\n\t# 1000 0bbb ffff ffff\n\tlocal bitmask = 1 << bit;\n\tsrcFREG = srcFREG | bitmask;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=0 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #C\n\tC = 1;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=1 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #DC\n\tDC = 1;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=2 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #Z\n\tZ = 1;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=3 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #OV\n\tOV = 1;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=4 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #FS0\n\tFS10 = FS10 | 0x1;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=5 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #FS1\n\tFS10 = FS10 | 0x2;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=6 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #FS2\n\tFS32 = FS32 | 0x1;\n}\n\n:BSF fALUSTA, bit\t\t\tis op5=0x10 & b3=7 & bit & fALUSTA\t\t{\n\t# 1000 0000 0000 0100\t->\tBSF ALUSTA, #FS3\n\tFS32 = FS32 | 0x2;\n}\n\n:BTFSC srcFREG, bit\t\tis op5=0x13 & bit & srcFREG\t& skipInst\t\t\t\t{\n\t# 1001 1bbb ffff ffff\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcFREG & bitmask;\n\tif (tmp == 0) goto skipInst;\n}\n\n:BTFSC fALUSTA, bit\t\tis op5=0x13 & b3=0 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1000 0000 0100\t->\tBTFSC STATUS, #C\n\tif (C == 0) goto skipInst;\n}\n\n:BTFSC fALUSTA, bit\t\tis op5=0x13 & b3=1 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1001 0000 0100\t->\tBTFSC STATUS, #DC\n\tif (DC == 0) goto skipInst;\n}\n\n:BTFSC fALUSTA, bit\t\tis op5=0x13 & b3=2 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1010 0000 0100\t->\tBTFSC STATUS, #Z\n\tif (Z == 0) goto skipInst;\n}\n\n:BTFSC fALUSTA, bit\t\tis op5=0x13 & b3=3 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1011 0000 0100\t->\tBTFSC STATUS, #OV\n\tif (OV == 0) goto skipInst;\n}\n\n:BTFSS srcFREG, bit\t\tis op5=0x12 & bit & srcFREG\t& skipInst\t\t\t\t{\n\t# 1001 0bbb ffff ffff\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcFREG & bitmask;\n\tif (tmp != 0) goto skipInst;\n}\n\n:BTFSS fALUSTA, bit\t\tis op5=0x12 & b3=0 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1000 0000 0100\t->\tBTFSS STATUS, #C\n\tif (C != 0) goto skipInst;\n}\n\n:BTFSS fALUSTA, bit\t\tis op5=0x12 & b3=1 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1001 0000 0100\t->\tBTFSS STATUS, #DC\n\tif (DC != 0) goto skipInst;\n}\n\n:BTFSS fALUSTA, bit\t\tis op5=0x12 & b3=2 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1010 0000 0100\t->\tBTFSS STATUS, #Z\n\tif (Z != 0) goto skipInst;\n}\n\n:BTFSS fALUSTA, bit\t\tis op5=0x12 & b3=3 & bit & fALUSTA & skipInst\t\t\t\t{\n\t# 1001 1011 0000 0100\t->\tBTFSS STATUS, #OV\n\tif (OV != 0) goto skipInst;\n}\n\n:BTG srcFREG, bit\t\tis op5=0x7 & bit & srcFREG & skipInst \t\t{\n\t# 0011 1bbb ffff ffff\n\tlocal bitmask = 1 << bit;\n\ttmp:1 = srcFREG;\n\tsrcFREG = ~(tmp & bitmask) | (tmp & ~bitmask);\n}\n\n:CALL shortAddr\t\t\tis op3=0x7 & shortAddr\t\t\t\t\t\t{\n\t# 111k kkkk kkkk kkkk\n\tpush(&:2 inst_next);\n\tcall shortAddr;\n}\n\n# Special case for Call which appears to correspond to uninitialized\n:BADCALL shortAddr\t\t\tis op16=0xffff & shortAddr\t\t{ addr:2 = shortAddr; return [addr]; }\n\n:CLRF destFREG, S\t\tis op7=0x14 & s=0 & S & destFREG\t\t\t\t\t{\n\t# 0010 1000 ffff ffff\n\tdestFREG = 0;\n\tWREG = 0;\n}\n\n:CLRF destFREG, S\t\tis op7=0x14 & s=1 & S & destFREG\t\t\t\t\t{\n\t# 0010 1001 ffff ffff\n\tdestFREG = 0;\n}\n\n:CLRF fALUSTA, S\t\tis op7=0x14 & s=0 & S & fALUSTA\t\t\t\t\t{\n\t# 0010 1000 0000 0100\n\tC = 0;\n\tDC = 0;\n\tZ = 0;\n\tOV = 0;\n\tFS10 = 0;\n\tFS32 = 0;\n\tWREG = 0;\n}\n\n:CLRF fALUSTA, S\t\tis op7=0x14 & s=1 & S & fALUSTA\t\t\t\t\t{\n\t# 0010 1001 0000 0100\n\tC = 0;\n\tDC = 0;\n\tZ = 0;\n\tOV = 0;\n\tFS10 = 0;\n\tFS32 = 0;\n}\n\n:CLRWDT\t\t\t\tis op16=0x0004 \t\t\t{\n\t# 0000 0000 0000 0100\n\tclearWatchDogTimer();\n}\n\n:COMF srcFREG, D\tis op7=0x09 & D & srcFREG & destREG\t\t\t{\n\t# 0001 001d ffff ffff\n\ttmp:1 = ~srcFREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:CPFSEQ srcFREG\t\tis op8=0x31 & srcFREG & skipInst\t\t{\n\t# 0011 0001 ffff ffff\n\tif (srcFREG == WREG) goto skipInst;\n}\n\n:CPFSGT srcFREG\t\tis op8=0x32 & srcFREG & skipInst\t\t{\n\t# 0011 0010 ffff ffff\n\tif (srcFREG > WREG) goto skipInst;\n}\n\n:CPFSLT srcFREG\t\tis op8=0x30 & srcFREG & skipInst\t\t{\n\t# 0011 0000 ffff ffff\n\tif (srcFREG < WREG) goto skipInst;\n}\n\n:DAW destFREG, S\tis op7=0x17 & s=0 & S & destFREG\t\t\t{ \n\t# 0010 1110 ffff ffff\n\ttmp:1 = decimalAdjust(WREG);\n\tdestFREG = tmp;\n\tWREG = tmp;\n}\n\n:DAW destFREG, S\tis op7=0x17 & s=1 & S & destFREG\t\t\t{ \n\t# 0010 1111 ffff ffff\n\ttmp:1 = decimalAdjust(WREG);\n\tdestFREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:DECF srcFREG, D\tis op7=0x03 & D & srcFREG & destREG\t\t{\n\t# 0000 011d ffff ffff\n\ttmp:1 = srcFREG;\n\tsetSubtractFlags(tmp, 1); \n\ttmp = tmp - 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:DECFSZ srcFREG, D\tis op7=0x0b & D & srcFREG & destREG\t& skipInst\t{\n\t# 0001 011d ffff ffff\n\tval:1 = srcFREG - 1;\n\tdestREG = val;\n\tif (val == 0) goto skipInst;\n}\n\n:DCFSNZ srcFREG, D\tis op7=0x13 & D & srcFREG & destREG & skipInst\t{\n\t# 0010 011d ffff ffff\n\tval:1 = srcFREG - 1;\n\tdestREG = val;\n\tif (val != 0) goto skipInst;\n}\n\n:GOTO shortAddr\t\tis op3=0x6 & shortAddr {\n\t# 110k kkkk kkkk kkkk\n\tgoto shortAddr;\n}\n\n:INCF srcFREG, D\tis op7=0x0a & D & srcFREG & destREG\t\t\t{\n\t# 0001 010d ffff ffff\n\ttmp:1 = srcFREG; # read once only!\n\tsetAddFlags(tmp, 1); \n\ttmp = tmp + 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:INCFSZ srcFREG, D\tis op7=0x0f & D & srcFREG & destREG\t& skipInst\t\t{\n\t# 0001 111d ffff ffff\n\tval:1 = srcFREG + 1;\n\tdestREG = val;\n\tif (val == 0) goto skipInst;\t\n}\n\n:INFSNZ srcFREG, D\tis op7=0x12 & D & srcFREG & destREG\t& skipInst\t\t{\n\t# 0010 010d ffff ffff\n\tval:1 = srcFREG + 1;\n\tdestREG = val;\n\tif (val != 0) goto skipInst;\t\n}\n\n:IORLW imm8\t\t\tis op8=0xb3 & imm8\t\t{\n\t# 1011 0011 kkkk kkkk\n\ttmp:1 = WREG | imm8;\n\tWREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:IORWF srcFREG, D\tis op7=0x04 & D & srcFREG & destREG\t\t{\n\t# 0000 100d ffff ffff\n\ttmp:1 = WREG | srcFREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:LCALL longAddr\t\tis op8=0xb7 & longAddr\t\t\t\t\t{\n\t# 1011 0111 kkkk kkkk\n\tpush(&:2 inst_next);\n\tcall [longAddr];\n}\n\n:MOVFP srcFREG, destPREG\tis op3=0x3 & srcFREG & destPREG\t\t{\n\t# 011p pppp ffff ffff\n\tdestPREG = srcFREG;\n}\n\n:MOVFP srcFREG, pPC\t\t\tis op3=0x3 & srcFREG & pPC\t\t{\n\t# 0110 0010 ffff ffff\n\taddr:2 = (zext(PCLATH) << 8) + zext(srcFREG);\n\tgoto [addr];\n}\n\n:MOVLB imm8l\t\t\tis op8=0xb8 & u4hi=0 & imm8l \t\t{\n\t# 1011 1000 0000 kkkk\n\tBSR = (BSR & 0xf0) | imm8l;\n}\n\n:MOVLR imm8h\t\t\tis op7=0x5d & u4lo=0 & imm8h\t\t\t{\n\t# 1011 101x kkkk 0000\n\tBSR = (BSR & 0x0f) | (imm8h << 4);\n}\n\n:MOVLW imm8\t\t\tis op8=0xb0 & imm8\t\t\t\t{\n\t# 1011 0000 kkkk kkkk\n\tWREG = imm8;\n}\n\n:MOVPF srcPREG, destFREG\tis op3=0x2 & srcPREG & destFREG\t\t{\n\t# 010p pppp ffff ffff\n\ttmp:1 = srcPREG;\n\tdestFREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:MOVPF srcPREG, fPC\tis op3=0x2 & srcPREG & fPC\t\t{\n\ttmp:1 = srcPREG;\n\taddr:2 = (zext(PCLATH) << 8) + zext(tmp);\n\tsetResultFlags(tmp);\n\tgoto [addr];\n}\n\n:MOVWF destFREG\t\t\t\tis op8=0x01 & destFREG\t\t{\n\t# 0000 0001 ffff ffff\n\tdestFREG = WREG;\n}\n\n:MOVWF fPC\t\t\t\t\tis op8=0x01 & fPC\t\t{\n\taddr:2 = (zext(PCLATH) << 8) + zext(WREG);\n\tgoto [addr];\n}\n\n:MULLW imm8\t\t\t\t\tis op8=0xbc & imm8\t\t{\n\t# 1011 1100 kkkk kkkk\n\tPROD = zext(WREG) * zext(imm8);\n}\n\n:MULLWF srcFREG\t\t\t\tis op8=0x34\t& srcFREG\t\t\t{\n\t# 0011 0100 ffff ffff\n\tPROD = zext(WREG) * zext(srcFREG);\n}\n\n:NEGW destFREG, S\t\t\tis op7=0x16 & s=0 & S & destFREG\t{\n\t# 0010 110s ffff ffff\n\ttmp:1 = -WREG;\n\tdestFREG = tmp;\n\tWREG = tmp;\n\tC = (tmp s< 0);\n\tOV = sborrow(0,tmp);\n\tsetResultFlags(tmp);\n}\n\n:NEGW destFREG, S\t\t\tis op7=0x16 & s=1 & S & destFREG\t{\n\t# 0010 110s ffff ffff\n\ttmp:1 = -WREG;\n\tdestFREG = tmp;\n\tC = (tmp s< 0);\n\tOV = sborrow(0,tmp);\n\tsetResultFlags(tmp);\n}\n\n:NOP\t\t\t\t\t\tis op16=0x0\t\t{ }\n\n:RETFIE\t\t\t\t\t\tis op16=0x0005\t\t{\n\t# 0000 0000 0000 0101\n\tretAddr:2 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETLW imm8\t\t\t\t\tis op8=0xb6 & imm8\t\t{\n\t# 1011 0110 kkkk kkkk\n\tWREG = imm8;\n\tretAddr:2 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETURN \t\t\t\t\tis op16=0x0002\t\t\t{\n\t# 0000 0000 0000 0010\n\tretAddr:2 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RLCF srcFREG, D\t\t\tis op7=0x0d & D & srcFREG & destREG\t\t{\n\t# 0001 101d ffff ffff\n\tlocal tmpC = C;\n\tval:1 = srcFREG;\n\tC = (val s< 0);\n\tval = (val << 1) | tmpC;\n\tdestREG = val;\n}\n\n:RLNCF srcFREG, D\t\t\tis op7=0x11 & D & srcFREG & destREG\t\t{\n\t# 0010 001d ffff ffff\n\ttmp:1 = srcFREG << 1;\n\tdestREG = tmp;\n}\n\n:RRCF srcFREG, D\t\t\tis op7=0x0c & D & srcFREG & destREG\t\t{\n\t# 0001 100d ffff ffff\n\tlocal tmpC = C << 7;\n\ttmp:1 = srcFREG;\n\tC = (tmp & 1) != 0;\n\ttmp = (tmp >> 1) | tmpC;\n\tdestREG = tmp;\n}\n\n:RRNCF srcFREG, D\t\t\tis op7=0x10 & D & srcFREG & destREG\t\t{\n\t# 0010 000d ffff ffff\n\ttmp:1 = srcFREG >> 1;\n\tdestREG = tmp;\n}\n\n:SETF destFREG, S\t\t\tis op7=0x15 & s=0 & S & destFREG\t\t{\n\t# 0010 1010 ffff ffff\n\tdestFREG = 0xff;\n\tWREG = 0xff;\n}\n\n:SETF destFREG, S\t\t\tis op7=0x15 & s=1 & S & destFREG\t\t{\n\t# 0010 1011 ffff ffff\n\tdestFREG = 0xff;\n}\n\n:SETF fALUSTA, S\t\tis op7=0x15 & s=0 & S & fALUSTA\t\t\t\t\t{\n\t# 0010 1010 0000 0100\n\tC = 1;\n\tDC = 1;\n\tZ = 1;\n\tOV = 1;\n\tFS10 = 0x3;\n\tFS32 = 0x3;\n\tWREG = 0xff;\n}\n\n:SETF fALUSTA, S\t\tis op7=0x15 & s=1 & S & fALUSTA\t\t\t\t\t{\n\t# 0010 1011 0000 0100\n\tC = 1;\n\tDC = 1;\n\tZ = 1;\n\tOV = 1;\n\tFS10 = 0x3;\n\tFS32 = 0x3;\n}\n\n:SLEEP\t\t\t\t\t\tis op16=0x0003\t\t{\n\t# 0000 0000 0000 0011\n\tsleep();\n}\n\n:SUBLW imm8\t\t\t\t\tis op8=0xb2 & imm8\t\t{\n\t# 1011 0010 kkkk kkkk\n\ttmp:1 = imm8;\n\ttmpW:1 = WREG;\n\tsetSubtractFlags(tmp, tmpW); \n\ttmp = tmp - tmpW;\n\tWREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SUBWF srcFREG, D\t\tis op7=0x02 & D & srcFREG & destREG\t\t{\n\t# 0000 010d ffff ffff\n\ttmp:1 = srcFREG;\n\ttmpW:1 = WREG;\n\tsetSubtractFlags(tmp, tmpW); \n\ttmp = tmp - tmpW;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SUBWFB srcFREG, D\t\tis op7=0x01 & D & srcFREG & destREG\t\t{\n\t# 0000 001d ffff ffff\n\tlocal notC = ~(C & 1);\n\ttmp:1 = srcFREG;\n\ttmpW:1 = WREG;\n\tsetSubtractCFlags(tmp, tmpW); \n\ttmp = tmp - tmpW - notC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SWAPF srcFREG, D\t\tis op7=0x0e & D & srcFREG & destREG\t\t{\n\t# 0001 110d ffff ffff\n\ttmp:1 = srcFREG;\n\tdestREG = (tmp << 4) | (tmp >> 4);\n}\n\n:TABLRD T, I, destFREG\t\tis op6=0x2a & T & I & i & destFREG\t\t\t{\n\t# 1010 10ti ffff ffff\n\tdestFREG = T;\n\tptr:2 = TBLPTR;\n\tTBLAT = *[CODE]:2 ptr;\n\tTBLPTR = ptr + i;\n}\n\n:TABLWT T, I, srcFREG\t\tis op6=0x2b & T & I & i & srcFREG\t\t\t{\n\t# 1010 11ti ffff ffff\n\tT = srcFREG;\n\tptr:2 = TBLPTR;\n\t*[CODE]:2 ptr = TBLAT;\n\tTBLPTR = ptr + i;\n}\n\n:TLRD T, destFREG\t\t\tis op6=0x28 & T & destFREG\t\t\t{\n\t# 1010 00tx ffff ffff\n\tdestFREG = T;\n}\n\n:TLWT T, srcFREG\t\t\tis op6=0x29 & T & srcFREG\t\t\t{\n\t# 1010 01tx ffff ffff\n\tT = srcFREG;\n}\n\n:TSTFSZ srcFREG\t\t\t\tis op8=0x33 & srcFREG & skipInst\t{\n\t# 0011 0011 ffff ffff\n\tif (srcFREG == 0) goto skipInst;\n} \n\n:XORLW imm8\t\t\t\t\tis op8=0xb4 & imm8\t\t\t{\n\t# 1011 0100 kkkk kkkk\n\ttmp:1 = WREG ^ imm8;\n\tWREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:XORWF srcFREG, D\t\t\tis op7=0x06 & D & srcFREG & destREG\t\t{\n\t# 0000 110d ffff ffff\n\ttmp:1 = WREG ^ srcFREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n" }, { "path": "pypcode/processors/PIC/data/languages/pic18.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic18.ldefs", "content": "\n\n\n \n PIC-18\n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic18.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PIC/data/languages/pic18.sinc", "content": "#\n# PIC-18 Main Section\n# includes constants, memory space and common register space definitions\n#\n\n@define SFR_BASE 0x0F80\n@define BANK15_BASE 0x0F00\n\n# STATUS bit definitions\n@define STATUS_N_BIT\t4\n@define STATUS_OV_BIT\t3\n@define STATUS_Z_BIT\t2\n@define STATUS_DC_BIT\t1\n@define STATUS_C_BIT\t0\n\n# STATUS bit masks used for clearing\n@define STATUS_N_CLEARMASK\t0xEF\n@define STATUS_OV_CLEARMASK\t0xF7\n@define STATUS_Z_CLEARMASK\t0xFB\n@define STATUS_DC_CLEARMASK\t0xFD\n@define STATUS_C_CLEARMASK\t0xFE\n\n@define STATUS_N_Z_MASK 0x14\n\n# STACK bit defintions\n@define STKPTR_STKFUL_BIT\t7\n@define STKPTR_STKUNF_BIT\t6\n\n# STACK bit masks\n@define STKPTR_SP_MASK\t\t0x1F\n@define STKPTR_NOT_SP_MASK\t0xE0\n@define STKPTR_STKFUL_MASK\t0x80\n@define STKPTR_STKUNF_MASK\t0x40\n\ndefine endian=little;\ndefine alignment=2;\n\n# Instruction Memory (ROM-based)\ndefine space CODE type=ram_space size=3 default;\n\n# General Purpose Register Memory consists of 16-banks of 255-bytes each\ndefine space DATA type=ram_space size=2; \n\n# The HWSTACK consists of a 31_word by 21_bit RAM and a corresponding 8_bit STKPTR register.\n# The real STKPTR register format is:\n# bit 7: Stack Full Flag (STKFUL) - See Note below\n# bit 6: Stack Underflow Flag (STKUNF) - See Note below\n# bit 5: \n# bit 4_0: stack pointer location within the 31_word by 21_bit \n# Each stack entry generally contains a 21_bit Program Counter value. \n# The top_of_stack entry (last push) may be accessed via the SFR registers TOSU, TOSH, and TOSL:\n# bit 20_16: TOSU\n# bit 15_8: TOSH\n# bit 7_0: TOSL\n# When accessing these top_of_stack registers, the global interrupts should/must be disabled. \n#\n# NOTE: This PIC-18 pcode implementation does not implement the STKFUL and STKUNF bits.\n# The entire STKPTR register is treated as an address offset into the stack space for simplification.\n# STKPTR value must be multiplied.\n#\ndefine space HWSTACK type=ram_space size=1; # implemented as independently addressable bytes (each location is 4-bytes wide)\n \ndefine space register type=register_space size=2; \n\n# Program Counter\ndefine register offset=0x0000 size=3 [ PC ];\n\n# Bad Register (needed only for attach usage)\ndefine register offset=0x0003 size=1 [ BAD ];\n\n# Stack Pointer\ndefine register offset=0x0004 size=1 [ STKPTR ];\n\n# Status bit registers (these do not really exist and must get reflected into the STATUS byte register)\ndefine register offset=0x0005 size=1 [ N OV Z DC C ];\n\n# Shadow registers (not visible)\ndefine register offset=0x000a size=1 [ WS STATUSS BSRS ];\n" }, { "path": "pypcode/processors/PIC/data/languages/pic18.slaspec", "content": "@define PROCESSOR \"PIC_18\"\n\n@include \"pic18.sinc\"\n\n#\n# NOTES\t-\n# 1. If a specific PIC-18 has a different register set, this file and the pic18.pspec file may be copied/renamed and\n# slightly modified to specify a the correct Register File Map. The following register definitions must be preserved: \n#\t STATUS, STKPTR, PCLAT (PCL, PCLATH, PCLATU), TOS (TOSL, TOSH, TOSU), FSR0 (FSR0L, FSR0H), FSR1 (FSR1L, FSR1H), FSR2 (FSR2L, FSR2H),\n# PROD (PRODL, PRODH)\n#\n\ndefine DATA offset=0x0f60 size=1 [\n\tsfrF60\tsfrF61\tsfrF62\tsfrF63\tsfrF64\tsfrF65\tsfrF66\tsfrF67\tsfrF68\tsfrF69 sfrF6A\tRCSTA2\tTXSTA2\tTXREG2\tRCREG2\tSPBREG2\n\tCCP5CON\tCCP5RL\tCCPR5H\tCCP4CON\tCCPR4L\tCCPR4H\tT4CON\tPR4\t\tTMR4\tsfrF79\tsfrF7A\tsfrF7B\tsfrF7C\tsfrF7D\tsfrF7E\tsfrF7F\n\tPORTA\tPORTB\tPORTC\tPORTD\tPORTE\tPORTF\tPORTG\tPORTH\tPORTJ\tLATA\tLATB\tLATC\tLATD\tLATE\tLATF\tLATG\n\tLATH\tLATJ\tTRISA\tTRISB\tTRISC\tTRISD\tTRISE\tTRISF\tTRISG\tTRISH\tTRISJ\tsfrF9B\tMEMCON\tPIE1\tPIR1\tIPR1\n\tPIE2\tPIR2\tIPR2\tPIE3\tPIR3\tIPR3\tEECON1\tEECON2\tEEDATA\tEEADR\tEEADRH\tRCSTA1\tTXSTA1\tTXREG1\tRCREG1\tSPBRG1\n\tPSPCON\tT3CON\tTMR3L\tTMR3H\tCMCON\tCVRCON\tsfrFB6\tCCP3CON\tCCP3RL\tCCP3RH\tCCP2CON\tCCPR2L\tCCPR2H\tCCP1CON\tCCPR1L\tCCPR1H\n\tADCON2\tADCON1\tADCON0\tADRESL\tADRESH\tSSPCON2\tSSPCON1\tSSPSTAT\tSSPADD\tSSPBUF\tT2CON\tPR2\t\tTMR2\tT1CON\tTMR1L\tTMR1H\n\tRCON\tWDTCON\tLVDCON\tOSCCON\tsfrFD4\tT0CON\tTMR0L\tTMR0H\tSTATUS\tFSR2L\tFSR2H\tPLUSW2\tPREINC2\tPOSTDEC2 POSTINC2 INDF2\n\tBSR\t\tFSR1L\tFSR1H\tPLUSW1\tPREINC1\tPOSTDEC1 POSTINC1 INDF1\tWREG\tFSR0L\tFSR0H\tPLUSW0\tPREINC0\tPOSTDEC0 POSTINC0 INDF0\n\tINTCON3\tINTCON2\tINTCON\tPRODL\tPRODH\tTABLAT\tTBLPTRL\tTBLPTRH\tTBLPTRU\tPCL\t\tPCLATH\tPCLATU\t.STKPTR\tTOSL\tTOSH\tTOSU \n];\n\ndefine DATA offset=0x0fbb size=2 [ CCPR2 ];\ndefine DATA offset=0x0fbe size=2 [ CCPR1 ];\ndefine DATA offset=0x0fc3 size=2 [ ADRES ];\ndefine DATA offset=0x0fce size=2 [ TMR1 ];\ndefine DATA offset=0x0fd6 size=2 [ TMR0 ];\ndefine DATA offset=0x0fd9 size=2 [ FSR2 ];\ndefine DATA offset=0x0fe1 size=2 [ FSR1 ];\ndefine DATA offset=0x0fe9 size=2 [ FSR0 ];\ndefine DATA offset=0x0ff3 size=2 [ PROD ];\n\ndefine DATA offset=0x0ff6 size=3 [ TBLPTR ];\ndefine DATA offset=0x0ff9 size=3 [ PCLAT ];\ndefine DATA offset=0x0ffd size=3 [ TOS ];\n\n@include \"pic18_instructions.sinc\"\n" }, { "path": "pypcode/processors/PIC/data/languages/pic18_instructions.sinc", "content": "#\n# PIC-18 Instruction Section\n# includes token definitions, macros, sub-constructors and instruction definitions\n#\n\n# The bytes are imported from the file in a 16-bit little-endian word format. This, combined\n# with the little-endian mode used by this language results in an unusual instruction format.\n# The 16-bit instruction token uses what appears to be big endian bit numbering, whereas the \n# 32-bit instruction token uses somewhat of a hybrid bit numbering (see below).\n\n# 16-bit instruction token uses big-endian bit numbering which agrees with\n# instruction bit numbering with PIC documentation.\n# \t15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0 \ndefine token instr16(16)\n\top4 =\t(12,15)\n\top5 =\t(11,15)\n\top6 =\t(10,15)\n\top8 =\t(8,15)\n\top12 =\t(4,15)\n\top16 =\t(0,15)\n\td =\t\t(9,9)\n\ta =\t\t(8,8)\n\t_xfsr =\t(6,7)\n\txfsr =\t(6,7)\n\tf8_57 =\t(5,7)\n\tf8 =\t(0,7)\n\tfreg =\t(0,7)\n\tb3 =\t(9,11)\n\tk8 =\t(0,7)\n\tk6 =\t(0,5)\n\tn11 =\t(0,10) signed\n\tn8 =\t(0,7) signed\n\ts_0 =\t(0,0)\n;\n\n# 32-bit instruction token uses a hybrid bit numbering:\n# Natural bit numbering (used by documentation):\n#\t\t31-30-29-28-27-26-25-24-23-22-21-20-19-18-17-16-15-14-13-12-11-10-09-08-07-06-05-04-03-02-01-00\n#\tHybrid bit nubering used by token:\n#\t\t15-14-13-12-11-10-09-08-07-06-05-04-03-02-01-00-31-30-29-28-27-26-25-24-23-22-21-20-19-18-17-16\ndefine token instr32(32)\n\tlop4 =\t(12,15)\n\tlop5 =\t(11,15)\n\tlop7 =\t(9,15)\n\tlop8 =\t(8,15)\n\tlop9 =\t(7,15)\n\tlop10 =\t(6,15)\n\t_fsr =\t(4,5)\n\tfsr =\t(4,5)\n\tkh =\t(0,3)\n\ts_8 =\t(8,8)\n\tn20_l =\t(0,7)\t# low order 8 bits of n20\n\tzs =\t(0,6)\n\tfs_h =\t(8,11)\n\tfs_57 =\t(5,7)\n\tfs =\t(0,11)\n\tfsreg =\t(0,7)\n\tqual4 =\t(28,31)\n\tqual8 =\t(24,31)\n\tfd_h =\t(24,27)\n\tfd_57 =\t(21,23)\n\tfd =\t(16,27)\n\tfdreg =\t(16,23)\n\tkl =\t(16,23)\n\tn20_h =\t(16,27) # high order 12 bits of n20\n\tzd =\t(16,22)\n;\n\nattach variables [ freg fsreg fdreg ] [\n\tBAD\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\t\t_\n\tsfrF60\tsfrF61\tsfrF62\tsfrF63\tsfrF64\tsfrF65\tsfrF66\tsfrF67\tsfrF68\tsfrF69\tsfrF6A\tRCSTA2\tTXSTA2\tTXREG2\tRCREG2\tSPBREG2\n\tCCP5CON\tCCP5RL\tCCPR5H\tCCP4CON\tCCPR4L\tCCPR4H\tT4CON\tPR4\t\tTMR4\tsfrF79\tsfrF7A\tsfrF7B\tsfrF7C\tsfrF7D\tsfrF7E\tsfrF7F\n\tPORTA\tPORTB\tPORTC\tPORTD\tPORTE\tPORTF\tPORTG\tPORTH\tPORTJ\tLATA\tLATB\tLATC\tLATD\tLATE\tLATF\tLATG\n\tLATH\tLATJ\tTRISA\tTRISB\tTRISC\tTRISD\tTRISE\tTRISF\tTRISG\tTRISH\tTRISJ\tsfrF9B\tMEMCON\tPIE1\tPIR1\tIPR1\n\tPIE2\tPIR2\tIPR2\tPIE3\tPIR3\tIPR3\tEECON1\tEECON2\tEEDATA\tEEADR\tEEADRH\tRCSTA1\tTXSTA1\tTXREG1\tRCREG1\tSPBRG1\n\tPSPCON\tT3CON\tTMR3L\tTMR3H\tCMCON\tCVRCON\tsfrFB6\tCCP3CON\tCCP3RL\tCCP3RH\tCCP2CON\tCCPR2L\tCCPR2H\tCCP1CON\tCCPR1L\tCCPR1H\n\tADCON2\tADCON1\tADCON0\tADRESL\tADRESH\tSSPCON2\tSSPCON1\tSSPSTAT\tSSPADD\tSSPBUF\tT2CON\tPR2\t\tTMR2\tT1CON\tTMR1L\tTMR1H\n\tRCON\tWDTCON\tLVDCON\tOSCCON\tsfrFD4\tT0CON\tTMR0L\tTMR0H\tSTATUS\tFSR2L\tFSR2H\tPLUSW2\tPREINC2\tPOSTDEC2 POSTINC2 INDF2\n\tBSR\t\tFSR1L\tFSR1H\tPLUSW1\tPREINC1\tPOSTDEC1 POSTINC1 INDF1\tWREG\tFSR0L\tFSR0H\tPLUSW0\tPREINC0\tPOSTDEC0 POSTINC0 INDF0\n\tINTCON3\tINTCON2\tINTCON\tPRODL\tPRODH\tTABLAT\tTBLPTRL\tTBLPTRH\tTBLPTRU\tPCL\t\tPCLATH\tPCLATU\tSTKPTR\tTOSL\tTOSH\tTOSU \n];\n\n# attach variables [ _fsr _xfsr ] [ FSR0 FSR1 FSR2 _ ];\n\n#\n# Special PIC-18 Operations\n#\n\n# If stack is full (SP==0x1F) STKFUL gets set, if STVREN is set the processor will reset\n#define pcodeop CheckStackFull;\n\n# If stack is empty (SP==0) STKUNF gets set, if STVREN is set the processor will reset\n#define pcodeop CheckStackUnderflow;\n\n# Return a decimal adjusted value for the value provided (see DAW instruction)\ndefine pcodeop decimalAdjust;\n\n# Perform a Master Clear Reset\ndefine pcodeop reset;\n\ndefine pcodeop clearWatchDogTimer;\n\ndefine pcodeop sleep;\n\n#\n# MACROS\n#\n\nmacro setResultFlags(result) {\n\tN = (result s< 0);\n\tZ = (result == 0);\n}\n\nmacro setAddCOverflowFlag(op1,op2) {\n\tlocal tmpC = C & 1;\n\tOV = scarry(op1,tmpC) || scarry(op2,op1 + tmpC);\n}\n\nmacro setAddCCarryFlag(op1,op2) {\n\tlocal tmpC = C & 1;\n\tC = carry(op1,tmpC) || carry(op2,op1 + tmpC);\n}\n\nmacro setAddCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tmpDC = DC & 1;\n\tDC = carry(tmp1,tmpDC) || carry(tmp2,tmp1 + tmpDC);\n}\n\nmacro setAddCFlags(op1,op2) {\n\tsetAddCCarryFlag(op1,op2);\n\tsetAddCDigitCarryFlag(op1,op2);\n\tsetAddCOverflowFlag(op1,op2);\n}\n\nmacro setAddFlags(op1,op2) {\n\tC = carry(op1,op2);\n\tDC = carry(op1<<4,op2<<4);\n\tOV = scarry(op1,op2);\n}\n\nmacro setSubtractCOverflowFlag(op1,op2) {\n\tlocal notC = ~(C & 1);\n\tOV = sborrow(op1,notC) || sborrow(op2,op1 - notC);\n}\n\nmacro setSubtractCCarryFlag(op1,op2) {\n\tlocal notC = ~(C & 1);\n\tC = (op1 < notC) || (op2 < (op1 - notC));\n}\n\nmacro setSubtractCDigitCarryFlag(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\tlocal notDC = ~(DC & 1);\n\tlocal tmp1 = op1 << 4;\n\tlocal tmp2 = op2 << 4;\n\tlocal tmp3 = (tmp1 - notDC) << 4;\n\tDC = (tmp1 < notDC) || (tmp2 < tmp3);\n}\n\nmacro setSubtractCFlags(op1,op2) {\n\tsetSubtractCCarryFlag(op1,op2);\n\tsetSubtractCDigitCarryFlag(op1,op2);\n\tsetSubtractCOverflowFlag(op1,op2);\n}\n\nmacro setSubtractFlags(op1,op2) {\n\t# op1 and op2 are assumed to be 8-bit values\n\t# NOTE: carry flag is SET if there is NO borrow\n\tC = (op1 >= op2);\n\tDC = ((op1<<4) < (op2<<4));\n\tOV = sborrow(op1,op2);\n}\n\nmacro push(val) {\t# TODO: Uncertain about this !!\n#\tCheckStackFull();\n\t*[HWSTACK]:4 STKPTR = val;\n\tSTKPTR = STKPTR + 4;\n}\n\nmacro pop(rval) {\t# TODO: Uncertain about this !!\n#\tCheckStackUnderflow();\n\tSTKPTR = STKPTR - 4;\n\trval = *[HWSTACK]:4 STKPTR;\n}\n\n#\n# SUB-CONSTRUCTORS\n#\n\n# PC register write - instruction must set PCLATH/PCL and perform branch operation\npcl: \"PC\" \t\t\tis a=0 & f8=0xf9\t\t\t\t{ export PCL; }\n\n# STATUS register\nstatus: freg \t\tis a=0 & f8=0xd8 & freg\t\t\t\t{ export STATUS; }\n\n# File Register specified by an 8-bit file register offset within Bank specified by BSR\nfREGLoc: f8\tis a=1 & f8\t\t\t\t\t\t\t\t\t{ # (Banked mode) \n\taddr:2 = (zext(BSR) << 8) + f8; \n\texport *[DATA]:1 addr; \n}\n\n# File Register specified by an 8-bit offset within \"Access Bank\"\n# The partitioning of the access bank may differ between specific PIC18 chips.\n# Some partition at 0x80 (i.e., PIC18Cxx2), while more advanced PIC18 chips partition at 0x60 (i.e., PIC18Fxx20).\n# This implementation partitions the access bank mode at 0x60.\n#\n# TODO: Need to add another language PIC18C that has the SFR start at 0xf80\n#\nfREGLoc: f8\t\t\tis a=0 & f8_57=0x0 & f8\t\t\t\t\t{ export *[DATA]:1 f8; } # 0x00-0x1f (Access mode)\nfREGLoc: f8\t\t\tis a=0 & f8_57=0x1 & f8\t\t\t\t\t{ export *[DATA]:1 f8; } # 0x20-0x3f (Access mode)\nfREGLoc: f8\t\t\tis a=0 & f8_57=0x2 & f8\t\t\t\t\t{ export *[DATA]:1 f8; } # 0x40-0x5f (Access mode)\nfREGLoc: freg\t\tis a=0 & freg\t\t\t\t\t\t\t{ export freg; }\t\t # 0xf60-0xfff (Access mode)\n\n# TOSL - access mirrored into stack space using STKPTR\nfREGLoc: freg\t\t\tis a=0 & f8=0xfd & freg\t\t\t\t{\n\taddr:1 = STKPTR + 1;\n\texport *[HWSTACK]:1 addr;\n}\n\n# TOSH - access mirrored into stack space using STKPTR\nfREGLoc: freg\t\t\tis a=0 & f8=0xfe & freg\t\t\t\t{\n\taddr:1 = STKPTR + 2;\n\texport *[HWSTACK]:1 addr;\n}\n\n# TOSU - access mirrored into stack space using STKPTR\nfREGLoc: freg\t\t\tis a=0 & f8=0xff & freg\t\t\t\t{\n\taddr:1 = STKPTR + 3;\n\texport *[HWSTACK]:1 addr;\n}\n\n# Indirect File Register access - INDF0\nfREGLoc: freg\t\tis a=0 & f8=0xef & freg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF1\nfREGLoc: freg\t\tis a=0 & f8=0xe7 & freg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF2\nfREGLoc: freg\t\tis a=0 & f8=0xdf & freg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC0\nfREGLoc: freg\t\tis a=0 & f8=0xee & freg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\tFSR0 = FSR0 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC1\nfREGLoc: freg\t\tis a=0 & f8=0xe6 & freg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\tFSR1 = FSR1 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC2\nfREGLoc: freg\t\tis a=0 & f8=0xde & freg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\tFSR2 = FSR2 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC0\nfREGLoc: freg\t\tis a=0 & f8=0xed & freg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\tFSR0 = FSR0 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC1\nfREGLoc: freg\t\tis a=0 & f8=0xe5 & freg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\tFSR1 = FSR1 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC2\nfREGLoc: freg\t\tis a=0 & f8=0xdd & freg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\tFSR2 = FSR2 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC0\nfREGLoc: freg\t\tis a=0 & f8=0xec & freg\t\t\t\t\t{ \n\tFSR0 = FSR0 + 1;\n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC1\nfREGLoc: freg\t\tis a=0 & f8=0xe4 & freg\t\t\t\t\t{\n\tFSR1 = FSR1 + 1;\n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC2\nfREGLoc: freg\t\tis a=0 & f8=0xdc & freg\t\t\t\t\t{ \n\tFSR2 = FSR2 + 1;\n\taddr:2 = FSR2;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW0\nfREGLoc: freg\t\tis a=0 & f8=0xeb & freg\t\t\t\t\t{ \n\tFSR0 = FSR0 + 1;\n\taddr:2 = FSR0 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW1\nfREGLoc: freg\t\tis a=0 & f8=0xe3 & freg\t\t\t\t\t{\n\tFSR1 = FSR1 + 1;\n\taddr:2 = FSR1 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW2\nfREGLoc: freg\t\tis a=0 & f8=0xdb & freg\t\t\t\t\t{ \n\tFSR2 = FSR2 + 1;\n\taddr:2 = FSR2 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Direct File register data\nsrcREG: fREGLoc\t\tis fREGLoc\t\t\t\t\t\t\t\t\t{ export fREGLoc; }\n\n# PCL read - latch PC into PCL, PCLATH, and PCLATU\nsrcREG: \"PC\"\t\tis a=0 & f8=0xf9\t\t\t\t\t\t{\n\tPCLAT = inst_start;\n\texport PCL; \n}\n\n# Destination register (either srcREG or WREG)\ndestREG: \"0\"\tis d=0\t\t\t\t\t\t\t\t\t\t\t{ export WREG; }\ndestREG: \"1\"\tis d=1 & srcREG\t\t\t\t\t\t\t\t\t{ export srcREG; }\n#destREG: \"1\"\tis d=1 & f8=0xf9\t\t\t\t\t\t{ \n#\t# Storing to PCL must write the PC using both the stored PCL (PC<7:0>), PCLATH (PC<15:8>) and PCLATU (PC<21:16>)\n#\t# The ADDWF and MOVWF definitions below have a specific case to handle this write to PCL\n#\texport PCL; \n#}\n\n# Destination operand representation (w: W register is destination; f: specified fREG is destination)\nD: \"w\"\t\tis d=0\t\t\t\t\t\t\t\t\t\t{ }\nD: \"f\"\t\tis d=1\t\t\t\t\t\t\t\t\t\t{ }\n\n# Source File Registers specified by a 12-bit absolute offsets within 32-bit instriction\nsrcREG32: fs\tis fs\t\t\t\t\t\t\t\t\t\t\t{ export *[DATA]:1 fs; } # 0x000-0xeff\nsrcREG32: fs\tis fs_h=0xf & fs_57=0 & fs\t\t\t\t\t\t{ export *[DATA]:1 fs; } # 0xf00-0xf1f\nsrcREG32: fs\tis fs_h=0xf & fs_57=1 & fs\t\t\t\t\t\t{ export *[DATA]:1 fs; } # 0xf20-0xf3f\nsrcREG32: fs\tis fs_h=0xf & fs_57=2 & fs\t\t\t\t\t\t{ export *[DATA]:1 fs; } # 0xf40-0xf5f\nsrcREG32: fsreg\tis fs_h=0xf & fsreg\t\t\t\t\t\t\t\t{ export fsreg; } \t\t # 0xf60-0xfff\n\n# PCL read - latch PC into PCL, PCLATH, and PCLATU\nsrcREG32: \"PC\" is fs=0xff9\t\t\t\t\t\t\t\t\t\t{\n\tPCLAT = inst_start;\n\texport PCL; \n}\n\n# TOSL - access mirrored into stack space using STKPTR\nsrcREG32: fsreg\t\t\tis fs=0xffd & fsreg\t\t\t\t{\n\taddr:1 = STKPTR + 1;\n\texport *[HWSTACK]:1 addr;\n}\n\n# TOSH - access mirrored into stack space using STKPTR\nsrcREG32: fsreg\t\t\tis fs=0xffe & fsreg\t\t\t\t{\n\taddr:1 = STKPTR + 2;\n\texport *[HWSTACK]:1 addr;\n}\n\n# TOSU - access mirrored into stack space using STKPTR\nsrcREG32: fsreg\t\t\tis fs=0xfff & fsreg\t\t\t\t{\n\taddr:1 = STKPTR + 3;\n\texport *[HWSTACK]:1 addr;\n}\n\n# Indirect File Register access - INDF0\nsrcREG32: fsreg\t\tis fs=0xfef & fsreg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF1\nsrcREG32: fsreg\t\tis fs=0xfe7 & fsreg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF2\nsrcREG32: fsreg\t\tis fs=0xfdf & fsreg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC0\nsrcREG32: fsreg\t\tis fs=0xfee & fsreg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\tFSR0 = FSR0 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC1\nsrcREG32: fsreg\t\tis fs=0xfe6 & fsreg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\tFSR1 = FSR1 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC2\nsrcREG32: fsreg\t\tis fs=0xfde & fsreg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\tFSR2 = FSR2 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC0\nsrcREG32: fsreg\t\tis fs=0xfed & fsreg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\tFSR0 = FSR0 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC1\nsrcREG32: fsreg\t\tis fs=0xfe5 & fsreg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\tFSR1 = FSR1 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC2\nsrcREG32: fsreg\t\tis fs=0xfdd & fsreg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\tFSR2 = FSR2 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC0\nsrcREG32: fsreg\t\tis fs=0xfec & fsreg\t\t\t\t\t{ \n\tFSR0 = FSR0 + 1;\n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC1\nsrcREG32: fsreg\t\tis fs=0xfe4 & fsreg\t\t\t\t\t{\n\tFSR1 = FSR1 + 1;\n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC2\nsrcREG32: fsreg\t\tis fs=0xfdc & fsreg\t\t\t\t\t{ \n\tFSR2 = FSR2 + 1;\n\taddr:2 = FSR2;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW0\nsrcREG32: fsreg\t\tis fs=0xfeb & fsreg\t\t\t\t\t{ \n\tFSR0 = FSR0 + 1;\n\taddr:2 = FSR0 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW1\nsrcREG32: fsreg\t\tis fs=0xfe3 & fsreg\t\t\t\t\t{\n\tFSR1 = FSR1 + 1;\n\taddr:2 = FSR1 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW2\nsrcREG32: fsreg\t\tis fs=0xfdb & fsreg\t\t\t\t\t{ \n\tFSR2 = FSR2 + 1;\n\taddr:2 = FSR2 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Destination File Registers specified by a 12-bit absolute offsets within 32-bit instriction\ndestREG32: fd\tis fd\t\t\t\t\t\t\t\t\t\t\t{ export *[DATA]:1 fd; } # 0x000-0xeff\ndestREG32: fd\tis fd_h=0xf & fd_57=0 & fd\t\t\t\t\t\t{ export *[DATA]:1 fd; } # 0xf00-0xf1f\ndestREG32: fd\tis fd_h=0xf & fd_57=1 & fd\t\t\t\t\t\t{ export *[DATA]:1 fd; } # 0xf20-0xf3f\ndestREG32: fd\tis fd_h=0xf & fd_57=2 & fd\t\t\t\t\t\t{ export *[DATA]:1 fd; } # 0xf40-0xf5f\ndestREG32: fdreg is fd_h=0xf & fdreg\t\t\t\t\t\t\t{ export fdreg; } \t\t # 0xf60-0xfff\n\n#destREG32: \"PCL\"\tis fd=0xff9\t\t\t\t\t\t{ \n#\t# Storing to PCL must write the PC using both the stored PCL (PC<7:0>), PCLATH (PC<15:8>) and PCLATU (PC<21:16>)\n#\t# The MOVFF and MOVSF definitions below have a specific case to handle this write to PCL\n#\texport PCL; \n#}\n\n# TOSL - access mirrored into stack space using STKPTR\ndestREG32: fdreg\t\t\tis fd=0xffd & fdreg\t\t\t\t{\n\taddr:1 = STKPTR + 1;\n\texport *[HWSTACK]:1 addr;\n}\n\n# TOSH - access mirrored into stack space using STKPTR\ndestREG32: fdreg\t\t\tis fd=0xffe & fdreg\t\t\t\t{\n\taddr:1 = STKPTR + 2;\n\texport *[HWSTACK]:1 addr;\n}\n\n# TOSU - access mirrored into stack space using STKPTR\ndestREG32: fdreg\t\t\tis fd=0xfff & fdreg\t\t\t\t{\n\taddr:1 = STKPTR + 3;\n\texport *[HWSTACK]:1 addr;\n}\n\n# Indirect File Register access - INDF0\ndestREG32: fdreg\t\tis fd=0xfef & fdreg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF1\ndestREG32: fdreg\t\tis fd=0xfe7 & fdreg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n\n# Indirect File Register access - INDF2\ndestREG32: fdreg\t\tis fd=0xfdf & fdreg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC0\ndestREG32: fdreg\t\tis fd=0xfee & fdreg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\tFSR0 = FSR0 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC1\ndestREG32: fdreg\t\tis fd=0xfe6 & fdreg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\tFSR1 = FSR1 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-increment File Register access - POSTINC2\ndestREG32: fdreg\t\tis fd=0xfde & fdreg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\tFSR2 = FSR2 + 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC0\ndestREG32: fdreg\t\tis fd=0xfed & fdreg\t\t\t\t\t{ \n\taddr:2 = FSR0;\n\tFSR0 = FSR0 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC1\ndestREG32: fdreg\t\tis fd=0xfe5 & fdreg\t\t\t\t\t{\n\taddr:2 = FSR1;\n\tFSR1 = FSR1 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Post-decrement File Register access - POSTDEC2\ndestREG32: fdreg\t\tis fd=0xfdd & fdreg\t\t\t\t\t{ \n\taddr:2 = FSR2;\n\tFSR2 = FSR2 - 1;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC0\ndestREG32: fdreg\t\tis fd=0xfec & fdreg\t\t\t\t\t{ \n\tFSR0 = FSR0 + 1;\n\taddr:2 = FSR0;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC1\ndestREG32: fdreg\t\tis fd=0xfe4 & fdreg\t\t\t\t\t{\n\tFSR1 = FSR1 + 1;\n\taddr:2 = FSR1;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment File Register access - PREINC2\ndestREG32: fdreg\t\tis fd=0xfdc & fdreg\t\t\t\t\t{ \n\tFSR2 = FSR2 + 1;\n\taddr:2 = FSR2;\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW0\ndestREG32: fdreg\t\tis fd=0xfeb & fdreg\t\t\t\t\t{ \n\tFSR0 = FSR0 + 1;\n\taddr:2 = FSR0 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW1\ndestREG32: fdreg\t\tis fd=0xfe3 & fdreg\t\t\t\t\t{\n\tFSR1 = FSR1 + 1;\n\taddr:2 = FSR1 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Pre-increment w/WREG-Offset File Register access - PLUSW2\ndestREG32: fdreg\t\tis fd=0xfdb & fdreg\t\t\t\t\t{ \n\tFSR2 = FSR2 + 1;\n\taddr:2 = FSR2 + sext(WREG);\n\texport *[DATA]:1 addr; \n}\n\n# Absolute 20-bit instruction location constructed from nl:8 and nh:12\nabsAddr21: nLoc\tis n20_h & n20_l \t[ nLoc = (n20_h << 9) + (n20_l << 1); ] { export *[CODE]:2 nLoc; }\n\n# Relative 8-bit and 11-bit instruction offsets\nrelAddr8: nLoc\tis n8\t\t\t\t[ nLoc = inst_next + (n8 << 1); ] \t{ export *[CODE]:2 nLoc; }\nrelAddr11: nLoc is n11\t\t\t\t[ nLoc = inst_next + (n11 << 1); ] \t{ export *[CODE]:2 nLoc; }\n\n# Skip instruction address (could jump into middle of 32-bit instruction which appears as NOP)\nskipInst: inst_skip\tis op16\t[ inst_skip = inst_next + 2; ]\t\t{export *[CODE]:2 inst_skip; }\n\n# Immediate Data (Literal operation)\nimm6: \"#\"k6\t\tis k6\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k6; }\nimm8: \"#\"k8\t\tis k8\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 k8; }\nimm12: \"#\"kVal\tis kl & kh\t[ kVal = (kh << 8) + kl; ]\t\t\t{ export *[const]:2 kVal; }\n\n# Bit identifier\nbit: \"#\"b3\t\tis b3\t\t\t\t\t\t\t\t\t\t\t{ export *[const]:1 b3; }\n\n# FSR Register (see LFSR)\nFSRn: \"FSR0\"\tis fsr=0 & _fsr\t\t\t\t\t\t\t\t\t{ export FSR0; }\nFSRn: \"FSR1\"\tis fsr=1 & _fsr\t\t\t\t\t\t\t\t\t{ export FSR1; }\nFSRn: \"FSR2\"\tis fsr=2 & _fsr\t\t\t\t\t\t\t\t\t{ export FSR2; }\n\n# FSR Register (see Extended Instructions)\nxFSRn: \"FSR0\"\tis xfsr=0 & _xfsr\t\t\t\t\t\t\t\t{ export FSR0; }\nxFSRn: \"FSR1\"\tis xfsr=1 & _xfsr\t\t\t\t\t\t\t\t{ export FSR1; }\nxFSRn: \"FSR2\"\tis xfsr=2 & _xfsr\t\t\t\t\t\t\t\t{ export FSR2; }\n\n# Source and Destination FSR2 Indexed Operand\nZS: zs\"[FSR2]\"\t\tis zs\t\t\t\t\t\t\t\t\t\t{ fsLoc:2 = FSR2 + zs; export *[DATA]:1 fsLoc; }\nZD: zd\"[FSR2]\"\t\tis zd\t\t\t\t\t\t\t\t\t\t{ fdLoc:2 = FSR2 + zd; export *[DATA]:1 fdLoc; }\n\n# Access Bank mode\nA: \"ACCESS\"\t\t\tis a=0\t\t\t\t\t\t\t\t\t\t{ }\nA: \"BANKED\"\t\t\tis a=1\t\t\t\t\t\t\t\t\t\t{ }\n\n#\n# BYTE-ORIENTED FILE REGISTER OPERATIONS\n#\n\n:ADDWF srcREG, D, A\t\tis op6=0x09 & srcREG & A & destREG & D\t{\n\t# 0010 01da ffff ffff\n\t# 0010 0100 0000 0000 -> ADDWF DAT_DATA_0000, w, ACCESS\n\t# 0010 0101 0000 0000 -> ADDWF REG0x0, w, BANKED\n\t# 0010 0100 1101 1000 -> ADDWF STATUS, w, ACCESS\n\t# 0010 0101 1101 1000 -> ADDWF REG0xD8, w, BANKED\n\t# 0010 0110 0000 0000 -> ADDWF DAT_DATA_0000, f, ACCESS\n\t# 0010 0111 0000 0000 -> ADDWF REG0x0, f, BANKED\n\t# 0010 0110 1101 1000 -> ADDWF STATUS, f, ACCESS\n\t# 0010 0111 1101 1000 -> ADDWF REG0xD8, f, BANKED\n\t# 0010 0100 1111 1001\t->\tADDWF PC, w, ACCESS\n\ttmp:1 = srcREG; # read only once!\n\tsetAddFlags(tmp, WREG); \n\ttmp = tmp + WREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ADDWF pcl, D, A\t\tis op6=0x09 & A & D & d=1 & pcl\t{\n\t# 0010 01da ffff ffff\n\t# 0010 0110 1111 1001 -> ADDWF PC, f, ACCESS\n\taddr:3 = inst_start;\n\tPCLAT = addr;\n\taddrHi:2 = addr(1);\n\taddrLo:1 = addr:1;\n\ttmpW:1 = WREG;\n\tsetAddFlags(addrLo, tmpW);\n\taddrLo = addrLo + tmpW;\n\taddr = (zext(addrHi) << 8) + zext(addrLo);\n\tsetResultFlags(addrLo);\n\tgoto [addr];\n}\n\n:ADDWFC srcREG, D, A \t\tis op6=0x08 & srcREG & destREG & D & A\t{ \n\t# 0010 00da ffff ffff\n\t# 0010 0000 0000 0000 -> ADDWFC DAT_DATA_0000, w, ACCESS\n\t# 0010 0001 0000 0000 -> ADDWFC REG0x0, w, BANKED\n\t# 0010 0000 1101 1000 -> ADDWFC STATUS, w, ACCESS\n\t# 0010 0001 1101 1000 -> ADDWFC REG0xD8, w, BANKED\n\t# 0010 0010 0000 0000 -> ADDWFC DAT_DATA_0000, f, ACCESS\n\t# 0010 0011 0000 0000 -> ADDWFC REG0x0, f, BANKED\n\t# 0010 0010 1101 1000 -> ADDWFC STATUS, f, ACCESS\n\t# 0010 0011 1101 1000 -> ADDWFC REG0xD8, f, BANKED\n\tlocal tmpC = C & 1;\n\ttmp:1 = srcREG;\n\tsetAddCFlags(tmp, WREG); \n\ttmp = tmp + WREG + tmpC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:ANDWF srcREG, D, A \t\tis op6=0x05 & srcREG & destREG & D & A\t{ \n\t# 0001 01da ffff ffff\n\t# 0001 0100 0000 0000 ->\tANDWF DAT_DATA_0000, w, ACCESS\n\t# 0001 0101 0000 0000 ->\tANDWF REG0x0, w, BANKED\n\t# 0001 0100 1101 1000 ->\tANDWF STATUS, w, ACCESS\n\t# 0001 0101 1101 1000 ->\tANDWF REG0xD8, w, BANKED\n\t# 0001 0110 0000 0000 ->\tANDWF DAT_DATA_0000, f, ACCESS\n\t# 0001 0111 0000 0000 ->\tANDWF REG0x0, f, BANKED\n\t# 0001 0110 1101 1000 ->\tANDWF STATUS, f, ACCESS\n\t# 0001 0111 1101 1000 ->\tANDWF REG0xD8, f, BANKED\n\ttmp:1 = srcREG & WREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:CLRF srcREG, A\t\t\tis op6=0x1a & d=1\t& srcREG & A\t{ \n\t# 0110 101a ffff ffff\n\t# 0110 1010 0000 0000 ->\tCLRF DAT_DATA_0000, 0\n\t# 0110 1011 0000 0000 ->\tCLRF REG0x0, 1\n\t# 0110 1010 1101 1000 ->\tCLRF STATUS, 0\n\t# 0110 1011 1101 1000 ->\tCLRF REG0xD8, 1\n\tsrcREG = 0;\n\tZ = 1;\n}\n\n:COMF srcREG, D, A\t\tis op6=0x07 & srcREG & destREG & D & A\t\t{ \n\t# 0001 11da ffff ffff\n\t# 0001 1100 0000 0000 ->\tCOMF DAT_DATA_0000, w, ACCESS\n\t# 0001 1101 0000 0000 ->\tCOMF REG0x0, w, BANKED\n\t# 0001 1100 1101 1000 ->\tCOMF STATUS, w, ACCESS\n\t# 0001 1101 1101 1000 ->\tCOMF REG0xD8, w, BANKED\n\t# 0001 1110 0000 0000 ->\tCOMF DAT_DATA_0000, f, ACCESS\n\t# 0001 1111 0000 0000 ->\tCOMF REG0x0, f, BANKED\n\t# 0001 1110 1101 1000 ->\tCOMF STATUS, f, ACCESS\n\t# 0001 1111 1101 1000 ->\tCOMF REG0xD8, f, BANKED\n\ttmp:1 = ~srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:CPFSEQ srcREG, A\t\t\tis op6=0x18 & d=1 & srcREG & A & skipInst\t{ \n\t# 0110 001a ffff ffff\n\t# 0110 0010 0000 0000 ->\tCPFSEQ DAT_DATA_0000, 0\n\t# 0110 0011 0000 0000 ->\tCPFSEQ REG0x0, 1\n\t# 0110 0010 1101 1000 ->\tCPFSEQ STATUS, 0\n\t# 0110 0011 1101 1000 ->\tCPFSEQ REG0xD8, 1\n\tif (srcREG == WREG) goto skipInst;\n}\n\n:CPFSGT srcREG, A\t\t\tis op6=0x19 & d=0 & srcREG & A & skipInst\t{ \n\t# 0110 010a ffff ffff\n\t# 0110 0100 0000 0000 ->\tCPFSGT DAT_DATA_0000, 0\n\t# 0110 0101 0000 0000 ->\tCPFSGT REG0x0, 1\n\t# 0110 0100 1101 1000 ->\tCPFSGT STATUS, 0\n\t# 0110 0101 1101 1000 ->\tCPFSGT REG0xD8, 1\n\tif (srcREG > WREG) goto skipInst;\n}\n\n:CPFSLT srcREG, A\t\t\tis op6=0x18 & d=0 & srcREG & A & skipInst\t{ \n\t# 0110 000a ffff ffff\n\t# 0110 0000 0000 0000 ->\tCPFSLT DAT_DATA_0000, 0\n\t# 0110 0001 0000 0000 ->\tCPFSLT REG0x0, 1\n\t# 0110 0000 1101 1000 ->\tCPFSLT STATUS, 0\n\t# 0110 0001 1101 1000 ->\tCPFSLT REG0xD8, 1\n\tif (srcREG < WREG) goto skipInst;\n}\n\n:DECF srcREG, D, A\t\tis op6=0x01 & srcREG & destREG & D & A\t{ \n\t# 0000 01da ffff ffff\n\t# 0000 0100 0000 0000 -> DECF DAT_DATA_0000, w, ACCESS\n\t# 0000 0101 0000 0000 -> DECF REG0x0, w, BANKED\n\t# 0000 0100 1101 1000 -> DECF STATUS, w, ACCESS\n\t# 0000 0101 1101 1000 -> DECF REG0xD8, w, BANKED\n\t# 0000 0110 0000 0000 -> DECF DAT_DATA_0000, f, ACCESS\n\t# 0000 0111 0000 0000 -> DECF REG0x0, f, BANKED\n\t# 0000 0110 1101 1000 -> DECF STATUS, f, ACCESS\n\t# 0000 0111 1101 1000 -> DECF REG0xD8, f, BANKED\n\ttmp:1 = srcREG;\n\tsetSubtractFlags(tmp, 1); \n\ttmp = tmp - 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:DECFSZ srcREG, D, A\t\tis op6=0x0b & srcREG & destREG & D & A & skipInst\t{ \n\t# 0010 11da ffff ffff\n\t# 0010 1100 0000 0000 -> DECFSZ DAT_DATA_0000, w, ACCESS\n\t# 0010 1101 0000 0000 -> DECFSZ REG0x0, w, BANKED\n\t# 0010 1100 1101 1000 -> DECFSZ STATUS, w, ACCESS\n\t# 0010 1101 1101 1000 -> DECFSZ REG0xD8, w, BANKED\n\t# 0010 1110 0000 0000 -> DECFSZ DAT_DATA_0000, f, ACCESS\n\t# 0010 1111 0000 0000 -> DECFSZ REG0x0, f, BANKED\n\t# 0010 1110 1101 1000 -> DECFSZ STATUS, f, ACCESS\n\t# 0010 1111 1101 1000 -> DECFSZ REG0xD8, f, BANKED\n\ttmp:1 = srcREG - 1;\n\tdestREG = tmp;\n\tif (tmp == 0) goto skipInst;\n}\n\n:DCFSNZ srcREG, D, A\t\tis op6=0x13 & srcREG & destREG & D & A & skipInst\t{ \n\t# 0100 11da ffff ffff\n\t# 0100 1100 0000 0000 -> DCFSNZ DAT_DATA_0000, w, ACCESS\n\t# 0100 1101 0000 0000 -> DCFSNZ REG0x0, w, BANKED\n\t# 0100 1100 1101 1000 -> DCFSNZ STATUS, w, ACCESS\n\t# 0100 1101 1101 1000 -> DCFSNZ REG0xD8, w, BANKED\n\t# 0100 1110 0000 0000 -> DCFSNZ DAT_DATA_0000, f, ACCESS\n\t# 0100 1111 0000 0000 -> DCFSNZ REG0x0, f, BANKED\n\t# 0100 1110 1101 1000 -> DCFSNZ STATUS, f, ACCESS\n\t# 0100 1111 1101 1000 -> DCFSNZ REG0xD8, f, BANKED\n\ttmp:1 = srcREG - 1;\n\tdestREG = tmp;\n\tif (tmp != 0) goto skipInst;\n}\n\n:INCF srcREG, D, A\t\tis op6=0x0a & srcREG & destREG & D & A\t{ \n\t# 0010 10da ffff ffff\n\t# 0010 1000 0000 0000 -> INCF DAT_DATA_0000, w, ACCESS\n\t# 0010 1001 0000 0000 -> INCF REG0x0, w, BANKED\n\t# 0010 1000 1101 1000 -> INCF STATUS, w, ACCESS\n\t# 0010 1001 1101 1000 -> INCF REG0xD8, w, BANKED\n\t# 0010 1010 0000 0000 -> INCF DAT_DATA_0000, f, ACCESS\n\t# 0010 1011 0000 0000 -> INCF REG0x0, f, BANKED\n\t# 0010 1010 1101 1000 -> INCF STATUS, f, ACCESS\n\t# 0010 1011 1101 1000 -> INCF REG0xD8, f, BANKED\n\ttmp:1 = srcREG; # read once only!\n\tsetAddFlags(tmp, 1); \n\ttmp = tmp + 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:INCFSZ srcREG, D, A\tis op6=0x0f & srcREG & destREG & D & A & skipInst\t{ \n\t# 0011 11da ffff ffff\n\t# 0011 1100 0000 0000 -> INCFSZ DAT_DATA_0000, w, ACCESS\n\t# 0011 1101 0000 0000 -> INCFSZ REG0x0, w, BANKED\n\t# 0011 1100 1101 1000 -> INCFSZ STATUS, w, ACCESS\n\t# 0011 1101 1101 1000 -> INCFSZ REG0xD8, w, BANKED\n\t# 0011 1110 0000 0000 -> INCFSZ DAT_DATA_0000, f, ACCESS\n\t# 0011 1111 0000 0000 -> INCFSZ REG0x0, f, BANKED\n\t# 0011 1110 1101 1000 -> INCFSZ STATUS, f, ACCESS\n\t# 0011 1111 1101 1000 -> INCFSZ REG0xD8, f, BANKED\n\ttmp:1 = srcREG + 1;\n\tdestREG = tmp;\n\tif (tmp == 0) goto skipInst;\n}\n\n:INFSNZ srcREG, D, A\t\tis op6=0x12 & srcREG & destREG & D & A & skipInst\t\t{ \n\t# 0100 10da ffff ffff\n\t# 0100 1000 0000 0000 -> INFSNZ DAT_DATA_0000, w, ACCESS\n\t# 0100 1001 0000 0000 -> INFSNZ REG0x0, w, BANKED\n\t# 0100 1000 1101 1000 -> INFSNZ STATUS, w, ACCESS\n\t# 0100 1001 1101 1000 -> INFSNZ REG0xD8, w, BANKED\n\t# 0100 1010 0000 0000 -> INFSNZ DAT_DATA_0000, f, ACCESS\n\t# 0100 1011 0000 0000 -> INFSNZ REG0x0, f, BANKED\n\t# 0100 1010 1101 1000 -> INFSNZ STATUS, f, ACCESS\n\t# 0100 1011 1101 1000 -> INFSNZ REG0xD8, f, BANKED\n\ttmp:1 = srcREG + 1;\n\tdestREG = tmp;\n\tif (tmp != 0) goto skipInst;\n}\n\n:IORWF srcREG, D, A\t\tis op6=0x04\t& srcREG & destREG & D & A\t\t{ \n\t# 0001 00da ffff ffff\n\t# 0001 0000 0000 0000 ->\tIORWF DAT_DATA_0000, w, ACCESS\n\t# 0001 0001 0000 0000 ->\tIORWF REG0x0, w, BANKED\n\t# 0001 0000 1101 1000 ->\tIORWF STATUS, w, ACCESS\n\t# 0001 0001 1101 1000 ->\tIORWF REG0xD8, w, BANKED\n\t# 0001 0010 0000 0000 ->\tIORWF DAT_DATA_0000, f, ACCESS\n\t# 0001 0011 0000 0000 ->\tIORWF REG0x0, f, BANKED\n\t# 0001 0010 1101 1000 ->\tIORWF STATUS, f, ACCESS\n\t# 0001 0011 1101 1000 ->\tIORWF REG0xD8, f, BANKED\n\ttmp:1 = srcREG | WREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:MOVF srcREG, D, A\t\tis op6=0x14\t& srcREG & destREG & D & A\t\t{ \n\t# 0101 00da ffff ffff\n\t# 0101 0000 0000 0000 ->\tMOVF DAT_DATA_0000, w, ACCESS\n\t# 0101 0001 0000 0000 ->\tMOVF REG0x0, w, BANKED\n\t# 0101 0000 1101 1000 ->\tMOVF STATUS, w, ACCESS\n\t# 0101 0001 1101 1000 ->\tMOVF REG0xD8, w, BANKED\n\t# 0101 0010 0000 0000 ->\tMOVF DAT_DATA_0000, f, ACCESS\n\t# 0101 0011 0000 0000 ->\tMOVF REG0x0, f, BANKED\n\t# 0101 0010 1101 1000 ->\tMOVF STATUS, f, ACCESS\n\t# 0101 0011 1101 1000 ->\tMOVF REG0xD8, f, BANKED\n\t\n\t# 0101 0000 1110 1111 ->\tMOVF INDF0, w, ACCESS\n\t# 0101 0000 1110 0111 ->\tMOVF INDF1, w, ACCESS\n\t# 0101 0000 1101 1111 ->\tMOVF INDF2, w, ACCESS\n\t\n\ttmp:1 = srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:MOVFF srcREG32, destREG32\tis lop4=0x0c & srcREG32 & qual4=0x0f & destREG32\t{ \n\t# 1100 ssss ssss ssss 1111 dddd dddd dddd\n\t# 1100 0000 0000 0000 1111 1111 1101 1000 -> MOVFF DAT_DATA_0000, STATUS\n\tdestREG32 = srcREG32;\n}\n\n:MOVFF srcREG32, destREG32\tis lop4=0x0c & srcREG32 & qual4=0x0f & destREG32 & fd=0xff9\t{ \n\t# 1100 ssss ssss ssss 1111 dddd dddd dddd\n\t# 1100 0000 0000 0000 1111 1111 1111 1001 -> MOVFF DAT_DATA_0000, PCL\n\taddr:3 = (zext(PCLATU) << 16) + (zext(PCLATH) << 8) + zext(srcREG32);\n\tgoto [addr];\n}\n\n:MOVWF srcREG, A\t\t\tis op6=0x1b & d=0x1\t& srcREG & A\t{ \n\t# 0110 111a ffff ffff\n\t# 0110 1110 0000 0000 ->\tMOVWF DAT_DATA_0000, 0\n\t# 0110 1111 0000 0000 ->\tMOVWF REG0x0, 1\n\t# 0110 1110 1101 1000 ->\tMOVWF STATUS, 0\n\t# 0110 1111 1101 1000 ->\tMOVWF REG0xD8, 1\n\tsrcREG = WREG;\n}\n\n:MOVWF pcl, A\t\t\tis op6=0x1b & A & pcl\t{ \n\t# 0110 111a ffff ffff\n\t# 0110 1110 1111 1001 ->\tMOVWF PCL, 0\n\taddr:3 = (zext(PCLATU) << 16) + (zext(PCLATH) << 8) + zext(WREG);\n\tgoto [addr];\n}\n\n:MULWF srcREG, A\t\t\tis op6=0x00 & d=0x1\t& srcREG & A\t{ \n\t# 0000 001a ffff ffff\n\t# 0000 0010 0000 0000 ->\tMULWF DAT_DATA_0000, 0\n\t# 0000 0011 0000 0000 ->\tMULWF REG0x0, 1\n\t# 0000 0010 1101 1000 ->\tMULWF STATUS, 0\n\t# 0000 0011 1101 1000 ->\tMULWF REG0xD8, 1\n\ttmp1:2 = zext(srcREG);\n\ttmp2:2 = zext(WREG);\n\tPROD = tmp1 * tmp2;\n}\n\n:NEGF srcREG, A\t\t\tis op6=0x1b & d=0x0\t& srcREG & A\t{ \n\t# 0110 110a ffff ffff\n\t# 0110 1100 0000 0000 ->\tNEGF DAT_DATA_0000, 0\n\t# 0110 1101 0000 0000 ->\tNEGF REG0x0, 1\n\t# 0110 1100 1101 1000 ->\tNEGF STATUS, 0\n\t# 0110 1101 1101 1000 ->\tNEGF REG0xD8, 1\n\ttmp:1 = -srcREG;\n\tsrcREG = tmp;\n\tC = (tmp s> 0);\n\tOV = sborrow(0,tmp);\n\tsetResultFlags(tmp);\n}\n\n:RLCF srcREG, D, A\t\tis op6=0x0d\t& srcREG & destREG & D & A\t\t{ \n\t# 0011 01da ffff ffff\n\t# 0011 0100 0000 0000 ->\tRLCF DAT_DATA_0000, w, ACCESS\n\t# 0011 0101 0000 0000 ->\tRLCF REG0x0, w, BANKED\n\t# 0011 0100 1101 1000 ->\tRLCF STATUS, w, ACCESS\n\t# 0011 0101 1101 1000 ->\tRLCF REG0xD8, w, BANKED\n\t# 0011 0110 0000 0000 ->\tRLCF DAT_DATA_0000, f, ACCESS\n\t# 0011 0111 0000 0000 ->\tRLCF REG0x0, f, BANKED\n\t# 0011 0110 1101 1000 ->\tRLCF STATUS, f, ACCESS\n\t# 0011 0111 1101 1000 ->\tRLCF REG0xD8, f, BANKED\n\tlocal tmpC = C & 1;\n\ttmp:1 = srcREG;\n\tC = (tmp s< 0);\n\ttmp = (tmp << 1) | tmpC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:RLNCF srcREG, D, A\t\tis op6=0x11\t& srcREG & destREG & D & A\t\t{ \n\t# 0100 01da ffff ffff\n\t# 0100 0100 0000 0000 ->\tRLNCF DAT_DATA_0000, w, ACCESS\n\t# 0100 0101 0000 0000 ->\tRLNCF REG0x0, w, BANKED\n\t# 0100 0100 1101 1000 ->\tRLNCF STATUS, w, ACCESS\n\t# 0100 0101 1101 1000 ->\tRLNCF REG0xD8, w, BANKED\n\t# 0100 0110 0000 0000 ->\tRLNCF DAT_DATA_0000, f, ACCESS\n\t# 0100 0111 0000 0000 ->\tRLNCF REG0x0, f, BANKED\n\t# 0100 0110 1101 1000 ->\tRLNCF STATUS, f, ACCESS\n\t# 0100 0111 1101 1000 ->\tRLNCF REG0xD8, f, BANKED\n\ttmp:1 = srcREG << 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:RRCF srcREG, D, A\t\tis op6=0x0c\t& srcREG & destREG & D & A\t\t{ \n\t# 0011 00da ffff ffff\n\t# 0011 0000 0000 0000 ->\tRRCF DAT_DATA_0000, w, ACCESS\n\t# 0011 0001 0000 0000 ->\tRRCF REG0x0, w, BANKED\n\t# 0011 0000 1101 1000 ->\tRRCF STATUS, w, ACCESS\n\t# 0011 0001 1101 1000 ->\tRRCF REG0xD8, w, BANKED\n\t# 0011 0010 0000 0000 ->\tRRCF DAT_DATA_0000, f, ACCESS\n\t# 0011 0011 0000 0000 ->\tRRCF REG0x0, f, BANKED\n\t# 0011 0010 1101 1000 ->\tRRCF STATUS, f, ACCESS\n\t# 0011 0011 1101 1000 ->\tRRCF REG0xD8, f, BANKED\n\tlocal tmpC = C << 7;\n\ttmp:1 = srcREG;\n\tC = (tmp & 1);\n\ttmp = (tmp >> 1) | tmpC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:RRNCF srcREG, D, A\t\tis op6=0x10\t& srcREG & destREG & D & A\t\t{ \n\t# 0100 00da ffff ffff\n\t# 0100 0000 0000 0000 ->\tRRNCF DAT_DATA_0000, w, ACCESS\n\t# 0100 0001 0000 0000 ->\tRRNCF REG0x0, w, BANKED\n\t# 0100 0000 1101 1000 ->\tRRNCF STATUS, w, ACCESS\n\t# 0100 0001 1101 1000 ->\tRRNCF REG0xD8, w, BANKED\n\t# 0100 0010 0000 0000 ->\tRRNCF DAT_DATA_0000, f, ACCESS\n\t# 0100 0011 0000 0000 ->\tRRNCF REG0x0, f, BANKED\n\t# 0100 0010 1101 1000 ->\tRRNCF STATUS, f, ACCESS\n\t# 0100 0011 1101 1000 ->\tRRNCF REG0xD8, f, BANKED\n\ttmp:1 = srcREG >> 1;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SETF srcREG, A\t\t\tis op6=0x1a & d=0x0\t& srcREG & A\t{ \n\t# 0110 100a ffff ffff\n\t# 0110 1000 0000 0000 ->\tSETF DAT_DATA_0000, 0\n\t# 0110 1001 0000 0000 ->\tSETF REG0x0, 1\n\t# 0110 1000 1101 1000 ->\tSETF STATUS, 0\n\t# 0110 1001 1101 1000 ->\tSETF REG0xD8, 1\n\tsrcREG = 0xff;\n}\n\n:SUBFWB srcREG, D, A\t\tis op6=0x15\t& srcREG & destREG & D & A\t\t{ \n\t# 0101 01da ffff ffff\n\t# 0101 0100 0000 0000 ->\tSUBFWB DAT_DATA_0000, w, ACCESS\n\t# 0101 0101 0000 0000 ->\tSUBFWB REG0x0, w, BANKED\n\t# 0101 0100 1101 1000 ->\tSUBFWB STATUS, w, ACCESS\n\t# 0101 0101 1101 1000 ->\tSUBFWB REG0xD8, w, BANKED\n\t# 0101 0110 0000 0000 ->\tSUBFWB DAT_DATA_0000, f, ACCESS\n\t# 0101 0111 0000 0000 ->\tSUBFWB REG0x0, f, BANKED\n\t# 0101 0110 1101 1000 ->\tSUBFWB STATUS, f, ACCESS\n\t# 0101 0111 1101 1000 ->\tSUBFWB REG0xD8, f, BANKED\n\tlocal notC = ~(C & 1);\n\ttmp:1 = srcREG;\n\tsetSubtractCFlags(WREG, tmp); \n\ttmp = WREG - tmp - notC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SUBWF srcREG, D, A\t\tis op6=0x17\t& srcREG & destREG & D & A\t\t{ \n\t# 0101 11da ffff ffff\n\t# 0101 1100 0000 0000 ->\tSUBWF DAT_DATA_0000, w, ACCESS\n\t# 0101 1101 0000 0000 ->\tSUBWF REG0x0, w, BANKED\n\t# 0101 1100 1101 1000 ->\tSUBWF STATUS, w, ACCESS\n\t# 0101 1101 1101 1000 ->\tSUBWF REG0xD8, w, BANKED\n\t# 0101 1110 0000 0000 ->\tSUBWF DAT_DATA_0000, f, ACCESS\n\t# 0101 1111 0000 0000 ->\tSUBWF REG0x0, f, BANKED\n\t# 0101 1110 1101 1000 ->\tSUBWF STATUS, f, ACCESS\n\t# 0101 1111 1101 1000 ->\tSUBWF REG0xD8, f, BANKED\n\ttmp:1 = srcREG;\n\tsetSubtractFlags(tmp, WREG); \n\ttmp = tmp - WREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SUBWFB srcREG, D, A\t\tis op6=0x16\t& srcREG & destREG & D & A\t\t{ \n\t# 0101 10da ffff ffff\n\t# 0101 1000 0000 0000 ->\tSUBWFB DAT_DATA_0000, w, ACCESS\n\t# 0101 1001 0000 0000 ->\tSUBWFB REG0x0, w, BANKED\n\t# 0101 1000 1101 1000 ->\tSUBWFB STATUS, w, ACCESS\n\t# 0101 1001 1101 1000 ->\tSUBWFB REG0xD8, w, BANKED\n\t# 0101 1010 0000 0000 ->\tSUBWFB DAT_DATA_0000, f, ACCESS\n\t# 0101 1011 0000 0000 ->\tSUBWFB REG0x0, f, BANKED\n\t# 0101 1010 1101 1000 ->\tSUBWFB STATUS, f, ACCESS\n\t# 0101 1011 1101 1000 ->\tSUBWFB REG0xD8, f, BANKED\n\tlocal notC = ~(C & 1);\n\ttmp:1 = srcREG;\n\tsetSubtractCFlags(tmp, WREG); \n\ttmp = tmp - WREG - notC;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:SWAPF srcREG, D, A\t\tis op6=0x0e\t& srcREG & destREG & D & A\t\t{ \n\t# 0011 10da ffff ffff\n\t# 0011 1000 0000 0000 ->\tSWAPF DAT_DATA_0000, w, ACCESS\n\t# 0011 1001 0000 0000 ->\tSWAPF REG0x0, w, BANKED\n\t# 0011 1000 1101 1000 ->\tSWAPF STATUS, w, ACCESS\n\t# 0011 1001 1101 1000 ->\tSWAPF REG0xD8, w, BANKED\n\t# 0011 1010 0000 0000 ->\tSWAPF DAT_DATA_0000, f, ACCESS\n\t# 0011 1011 0000 0000 ->\tSWAPF REG0x0, f, BANKED\n\t# 0011 1010 1101 1000 ->\tSWAPF STATUS, f, ACCESS\n\t# 0011 1011 1101 1000 ->\tSWAPF REG0xD8, f, BANKED\n\ttmp:1 = srcREG;\n\tdestREG = (tmp << 4) | (tmp >> 4);\t\n}\n\n:TSTFSZ srcREG, A\t\t\tis op6=0x19 & d=0x1\t& srcREG & A & skipInst\t{ \n\t# 0110 011a ffff ffff\n\t# 0110 0110 0000 0000 ->\tTSTFSZ DAT_DATA_0000, 0\n\t# 0110 0111 0000 0000 ->\tTSTFSZ REG0x0, 1\n\t# 0110 0110 1101 1000 ->\tTSTFSZ STATUS, 0\n\t# 0110 0111 1101 1000 ->\tTSTFSZ REG0xD8, 1\n\tif (srcREG == 0) goto skipInst;\n}\n\n:XORWF srcREG, D, A\t\tis op6=0x06\t& srcREG & destREG & D & A\t\t{ \n\t# 0001 10da ffff ffff\n\t# 0001 1000 0000 0000 ->\tXORWF DAT_DATA_0000, w, ACCESS\n\t# 0001 1001 0000 0000 ->\tXORWF REG0x0, w, BANKED\n\t# 0001 1000 1101 1000 ->\tXORWF STATUS, w, ACCESS\n\t# 0001 1001 1101 1000 ->\tXORWF REG0xD8, w, BANKED\n\t# 0001 1010 0000 0000 ->\tXORWF DAT_DATA_0000, f, ACCESS\n\t# 0001 1011 0000 0000 ->\tXORWF REG0x0, f, BANKED\n\t# 0001 1010 1101 1000 ->\tXORWF STATUS, f, ACCESS\n\t# 0001 1011 1101 1000 ->\tXORWF REG0xD8, f, BANKED\n\ttmp:1 = WREG ^ srcREG;\n\tdestREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n\n#\n# BIT-ORIENTED FILE REGISTER OPERATIONS\n#\n\n:BCF srcREG, bit, A\t\t\tis op4=0x09\t& srcREG & bit & A\t{ \n\t# 1001 bbba ffff ffff\n\t# 1001 0010 0000 0000\t->\tBCF DAT_DATA_0000, #0x1, 0\n\t# 1001 0101 0000 0000 ->\tBCF REG0x0, #0x2, 1\n\t# 1001 0010 1101 1000 ->\tBCF STATUS, #0x1, 0\n\t# 1001 0101 1101 1000 ->\tBCF REG0xD8, #0x2, 1\n\tlocal bitmask = ~(1 << bit);\n\tsrcREG = srcREG & bitmask;\n}\n\n:BCF status, bit, A\t\t\tis op4=0x09\t& status & b3=0 & bit & A\t{ \n\t# 1001 bbba ffff ffff\n\t# 1001 0000 1101 1000 ->\tBCF STATUS, #C, 0\n\tC = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit, A\t\t\tis op4=0x09\t& status & b3=1 & bit & A\t{ \n\t# 1001 bbba ffff ffff\n\t# 1001 0010 1101 1000 ->\tBCF STATUS, #DC, 0\n\tDC = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit, A\t\t\tis op4=0x09\t& status & b3=2 & bit & A\t{ \n\t# 1001 bbba ffff ffff\n\t# 1001 0100 1101 1000 ->\tBCF STATUS, #Z, 0\n\tZ = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit, A\t\t\tis op4=0x09\t& status & b3=3 & bit & A\t{ \n\t# 1001 bbba ffff ffff\n\t# 1001 0110 1101 1000 ->\tBCF STATUS, #OV, 0\n\tOV = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BCF status, bit, A\t\t\tis op4=0x09\t& status & b3=4 & bit & A\t{ \n\t# 1001 bbba ffff ffff\n\t# 1001 1000 1101 1000 ->\tBCF STATUS, #N, 0\n\tN = 0;\n\tlocal bitmask = ~(1 << bit);\n\tSTATUS = STATUS & bitmask;\n}\n\n:BSF srcREG, bit, A\t\t\tis op4=0x08\t& srcREG & bit & A\t{ \n\t# 1000 bbba ffff ffff\n\t# 1000 0010 0000 0000\t->\tBSF DAT_DATA_0000, #0x1, 0\n\t# 1000 0101 0000 0000 ->\tBSF REG0x0, #0x2, 1\n\t# 1000 0010 1101 1000 ->\tBSF STATUS, #0x1, 0\n\t# 1000 0101 1101 1000 ->\tBSF REG0xD8, #0x2, 1\t\n\tlocal bitmask = 1 << bit;\n\tsrcREG = srcREG | bitmask;\n}\n\n:BSF status, bit, A\t\t\tis op4=0x08\t& status & b3=0 & bit & A\t{ \n\t# 1000 bbba ffff ffff\n\t# 1000 0000 1101 1000 ->\tBSF STATUS, #C, 0\n\tC = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit, A\t\t\tis op4=0x08\t& status & b3=1 & bit & A\t{ \n\t# 1000 bbba ffff ffff\n\t# 1000 0010 1101 1000 ->\tBSF STATUS, #DC, 0\n\tDC = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit, A\t\t\tis op4=0x08\t& status & b3=2 & bit & A\t{ \n\t# 1000 bbba ffff ffff\n\t# 1000 0100 1101 1000 ->\tBSF STATUS, #Z, 0\n\tZ = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit, A\t\t\tis op4=0x08\t& status & b3=3 & bit & A\t{ \n\t# 1000 bbba ffff ffff\n\t# 1000 0110 1101 1000 ->\tBSF STATUS, #OV, 0\n\tOV = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BSF status, bit, A\t\t\tis op4=0x08\t& status & b3=4 & bit & A\t{ \n\t# 1000 bbba ffff ffff\n\t# 1000 1000 1101 1000 ->\tBSF STATUS, #N, 0\n\tN = 1;\n\tlocal bitmask = 1 << bit;\n\tSTATUS = STATUS | bitmask;\n}\n\n:BTFSC srcREG, bit, A\t\tis op4=0x0b\t& srcREG & bit & A & skipInst\t{ \n\t# 1011 bbba ffff ffff\n\t# 1011 0010 0000 0000\t->\tBTFSC DAT_DATA_0000, #0x1, 0\n\t# 1011 0101 0000 0000 ->\tBTFSC REG0x0, #0x2, 1\n\t# 1011 0010 1101 1000 ->\tBTFSC STATUS, #0x1, 0\n\t# 1011 0101 1101 1000 ->\tBTFSC REG0xD8, #0x2, 1\t\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcREG & bitmask;\n\tif (tmp == 0) goto skipInst;\n}\n\n:BTFSC status, bit, A\t\tis op4=0x0b & b3=0 & bit & status & A & skipInst\t\t\t\t{\n\t# 1011 bbba ffff ffff\n\t# 1011 0000 1101 1000 ->\tBTFSC STATUS, #C, 0\n\tif ((C & 1) == 0) goto skipInst;\n}\n\n:BTFSC status, bit, A\t\tis op4=0x0b & b3=1 & bit & status & A & skipInst\t\t\t\t{\n\t# 1011 bbba ffff ffff\n\t# 1011 0000 1101 1000\t->\tBTFSC STATUS, #DC, 0\n\tif ((DC & 1) == 0) goto skipInst;\n}\n\n:BTFSC status, bit, A\t\tis op4=0x0b & b3=2 & bit & status & A & skipInst\t\t\t\t{\n\t# 1011 bbba ffff ffff\n\t# 1011 0000 1101 1000\t->\tBTFSC STATUS, #Z, 0\n\tif ((Z & 1) == 0) goto skipInst;\n}\n\n:BTFSC status, bit, A\t\tis op4=0x0b & b3=3 & bit & status & A & skipInst\t\t\t\t{\n\t# 1011 bbba ffff ffff\n\t# 1011 0110 1101 1000\t->\tBTFSC STATUS, #OV, 0\n\tif ((OV & 1) == 0) goto skipInst;\n}\n\n:BTFSC status, bit, A\t\tis op4=0x0b & b3=4 & bit & status & A & skipInst\t\t\t\t{\n\t# 1011 bbba ffff ffff\n\t# 1011 1000 1101 1000\t->\tBTFSC STATUS, #N, 0\n\tif ((N & 1) == 0) goto skipInst;\n}\n\n:BTFSS srcREG, bit, A\t\tis op4=0x0a\t& srcREG & bit & A & skipInst\t{ \n\t# 1010 bbba ffff ffff\n\t# 1010 0010 0000 0000\t->\tBTFSS DAT_DATA_0000, #0x1, 0\n\t# 1010 0101 0000 0000 ->\tBTFSS REG0x0, #0x2, 1\n\t# 1010 0010 1101 1000 ->\tBTFSS STATUS, #0x1, 0\n\t# 1010 0101 1101 1000 ->\tBTFSS REG0xD8, #0x2, 1\t\n\tlocal bitmask = 1 << bit;\n\tlocal tmp = srcREG & bitmask;\n\tif (tmp != 0) goto skipInst;\n}\n\n:BTFSS status, bit, A\t\tis op4=0x0a\t& b3=0 & bit & status & A & skipInst\t{ \n\t# 1010 bbba ffff ffff\n\t# 1010 0000 1101 1000 ->\tBTFSS STATUS, #C, 0\t\n\tif ((C & 1) != 0) goto skipInst;\n}\n\n:BTFSS status, bit, A\t\tis op4=0x0a\t& b3=1 & bit & status & A & skipInst\t{ \n\t# 1010 bbba ffff ffff\n\t# 1010 0010 1101 1000 ->\tBTFSS STATUS, #DC, 0\t\n\tif ((DC & 1) != 0) goto skipInst;\n}\n\n:BTFSS status, bit, A\t\tis op4=0x0a\t& b3=2 & bit & status & A & skipInst\t{ \n\t# 1010 bbba ffff ffff\n\t# 1010 0100 1101 1000 ->\tBTFSS STATUS, #Z, 0\t\n\tif ((Z & 1) != 0) goto skipInst;\n}\n\n:BTFSS status, bit, A\t\tis op4=0x0a\t& b3=3 & bit & status & A & skipInst\t{ \n\t# 1010 bbba ffff ffff\n\t# 1010 0110 1101 1000 ->\tBTFSS STATUS, #OV, 0\t\n\tif ((OV & 1) != 0) goto skipInst;\n}\n\n:BTFSS status, bit, A\t\tis op4=0x0a\t& b3=4 & bit & status & A & skipInst\t{ \n\t# 1010 bbba ffff ffff\n\t# 1010 1000 1101 1000 ->\tBTFSS STATUS, #N, 0\t\n\tif ((N & 1) != 0) goto skipInst;\n}\n\n:BTG srcREG, bit, A\t\t\tis op4=0x07\t& srcREG & bit & A\t{ \n\t# 0111 bbba ffff ffff\n\t# 0111 0010 0000 0000\t->\tBTG DAT_DATA_0000, #0x1, 0\n\t# 0111 0101 0000 0000 ->\tBTG REG0x0, #0x2, 1\n\t# 0111 0010 1101 1000 ->\tBTG STATUS, #0x1, 0\n\t# 0111 0101 1101 1000 ->\tBTG REG0xD8, #0x2, 1\t\n\tlocal bitmask = 1 << bit;\n\ttmp:1 = srcREG;\n\tsrcREG = ~(tmp & bitmask) | (tmp & ~bitmask);\n}\n\n#\n# CONTROL OPERATIONS\n#\n\n:BC relAddr8\t\t\tis op8=0xe2\t& relAddr8\t\t{ \n\t# 1110 0010 nnnn nnnn\n\t# 1110 0010 0001 0000\t->\tBC LAB_CODE_XXXX\n\tif ((C & 1) != 0) goto relAddr8;\n}\n\n:BN relAddr8\t\t\tis op8=0xe6\t& relAddr8\t\t{ \n\t# 1110 0110 nnnn nnnn\n\t# 1110 0110 0001 0000\t->\tBN LAB_CODE_XXXX\n\tif ((N & 1) != 0) goto relAddr8;\n}\n\n:BNC relAddr8\t\t\tis op8=0xe3\t& relAddr8\t\t{ \n\t# 1110 0011 nnnn nnnn\n\t# 1110 0011 0001 0000\t->\tBNC LAB_CODE_XXXX\n\tif ((C & 1) == 0) goto relAddr8;\n}\n\n:BNN relAddr8\t\t\tis op8=0xe7\t& relAddr8\t\t{ \n\t# 1110 0111 nnnn nnnn\n\t# 1110 0111 0001 0000\t->\tBNN LAB_CODE_XXXX\n\tif ((N & 1) == 0) goto relAddr8;\n}\n\n:BNOV relAddr8\t\t\tis op8=0xe5\t& relAddr8\t\t{ \n\t# 1110 0101 nnnn nnnn\n\t# 1110 0101 0001 0000\t->\tBNOV LAB_CODE_XXXX\n\tif ((OV & 1) == 0) goto relAddr8;\n}\n\n:BNZ relAddr8\t\t\tis op8=0xe1\t& relAddr8\t\t{ \n\t# 1110 0001 nnnn nnnn\n\t# 1110 0001 0001 0000\t->\tBNZ LAB_CODE_XXXX\n\tif ((Z & 1) == 0) goto relAddr8;\n}\n\n:BOV relAddr8\t\t\tis op8=0xe4\t& relAddr8\t\t{ \n\t# 1110 0100 nnnn nnnn\n\t# 1110 0100 0001 0000\t->\tBOV LAB_CODE_XXXX\n\tif ((OV & 1) != 0) goto relAddr8;\n}\n\n:BRA relAddr11\t\t\tis op5=0x1a\t& relAddr11\t\t{ \n\t# 1101 0nnn nnnn nnnn\n\t# 1101 0001 0001 0000\t->\tBRA LAB_CODE_XXXX (inst_next+0x220)\n\tgoto relAddr11;\t\n}\n\n:BZ relAddr8\t\t\tis op8=0xe0 & relAddr8\t\t{ \n\t# 1110 0000 nnnn nnnn\n\t# 1110 0000 0001 0000\t->\tBZ LAB_CODE_XXXX\n\tif ((Z & 1) != 0) goto relAddr8;\n}\n\n:CALL absAddr21, s_8\t\tis lop8=0xec & absAddr21 & s_8\t{ \n\t# 1110 110s kkkk kkkk 1111 kkkk kkkk kkkk\n\t# 1110 1100 0100 0101 1111 0001 0010 0011\t->\tCALL SUB_CODE_02468a, 0\n\tpush(&:3 inst_next);\n\tcall absAddr21;\n}\n\n:CALL absAddr21, s_8\t\tis lop8=0xed & absAddr21 & s_8\t{ \n\t# 1110 110s kkkk kkkk 1111 kkkk kkkk kkkk\n\t# 1110 1101 0100 0101 1111 0001 0010 0011\t->\tCALL SUB_CODE_02468a, 1\n\tWS = WREG;\n\tSTATUSS = STATUS;\n\tBSRS = BSR;\n\tpush(&:3 inst_next);\n\tcall absAddr21;\n} \n\n:CLRWDT\t\t\t\t\tis op16=0x0004\t\t\t\t{\n\t# 0000 0000 0000 0100\n\tclearWatchDogTimer();\n}\n\n:DAW\t\t\t\t\tis op16=0x0007\t\t\t\t{ \n\t# 0000 0000 0000 0111\n\ttmp:1 = decimalAdjust(WREG);\n\tWREG = tmp;\n\tsetResultFlags(tmp);\n}\n\n:GOTO absAddr21\t\t\tis lop8=0xef & absAddr21 \t{ \n\t# 1110 1111 kkkk kkkk 1111 kkkk kkkk kkkk\n\t# 1110 1111 0100 0101 1111 0001 0010 0011\t->\tGOTO LAB_CODE_02468a\n\tgoto absAddr21;\n} \n\n:NOP\t\t\t\t\tis op16=0x0000\t\t\t\t{ }\n\n:NOP\t\t\t\t\tis op4=0x0f\t\t\t\t\t{ }\n\n:POP\t\t\t\t\tis op16=0x0006\t\t\t\t{ \n\t# 0000 0000 0000 0110\n\ttmp:4 = 0;\n\tpop(tmp);\n}\n\n:PUSH\t\t\t\t\tis op16=0x0005\t\t\t\t{ \n\t# 0000 0000 0000 0101\n\tpush(&:3 inst_next);\n}\n\n:RCALL relAddr11\t\tis op5=0x1b\t& relAddr11\t\t{ \n\t# 1101 1nnn nnnn nnnn\n\t# 1101 1001 0000 0000\t->\tCALL SUB_CODE_XXXX\n\tpush(&:3 inst_next);\n\tcall relAddr11;\n}\n\n:RESET\t\t\t\t\tis op16=0x00ff\t\t\t\t{ \n\t# 0000 0000 1111 1111\n\treset();\n}\n\n:RETFIE s_0\t\t\t\tis op16=0x0010 & s_0\t\t\t{ # TODO: Set GIE/GIEH and/or PEIE/GIEL\n\t# 0000 0000 0001 0000\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETFIE s_0\t\t\tis op16=0x0011 & s_0\t\t\t\t{ # TODO: Set GIE/GIEH and/or PEIE/GIEL\n\t# 0000 0000 0001 0001\n\tWREG = WS;\n\tSTATUS = STATUSS;\n\tBSR = BSRS;\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETURN s_0\t\t\t\tis op16=0x0012 & s_0\t\t\t\t{ \n\t# 0000 0000 0001 0010\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:RETURN s_0\t\t\t\tis op16=0x0013 & s_0\t\t\t\t{ \n\t# 0000 0000 0001 0011\n\tWREG = WS;\n\tSTATUS = STATUSS;\n\tBSR = BSRS;\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:SLEEP\t\t\t\t\tis op16=0x0003\t\t\t\t{ \n\t# 0000 0000 0000 0011\n\tsleep();\n}\n\n#\n# LITERAL OPERATIONS\n#\n\n:ADDLW imm8\t\t\t\tis op8=0x0f & imm8\t\t\t{ \n\t# 0000 1111 kkkk kkkk\n\t# 0000 1111 0001 0010\t->\tADDLW #0x12\n\tsetAddFlags(imm8, WREG); \n\tWREG = WREG + imm8;\n\tsetResultFlags(WREG);\n}\n\n:ANDLW imm8\t\t\t\tis op8=0xb & imm8\t\t\t{ \n\t# 0000 1011 kkkk kkkk\n\t# 0000 1011 0001 0010\t->\tANDLW #0x12\n\tWREG = WREG & imm8;\n\tsetResultFlags(WREG);\n}\n\n:IORLW imm8\t\t\t\tis op8=0x9 & imm8\t\t\t{ \n\t# 0000 1001 kkkk kkkk\n\t# 0000 1001 0001 0010\t->\tIORLW #0x12\n\tWREG = WREG | imm8;\n\tsetResultFlags(WREG);\n}\n\n:LFSR FSRn, imm12\t\tis lop10=0x3b8 & fsr<3 & FSRn & imm12\t{ \n\t# 1110 1110 00ff kkkk 1111 0000 kkkk kkkk\n\t# 1110 1110 0001 0001 1111 0000 0010 0011\t->\tLFSR FSR1, 0x123\n\tFSRn = imm12;\n}\n\n:MOVLB imm8\t\t\t\tis op8=0x01 & imm8\t\t{ # Manual is inconsistent imm4 vs. imm8\n\t# 0000 0001 kkkk kkkk\n\t# 0000 0001 0001 0010\t->\tMOVLB #0x12\n\tBSR = imm8;\n}\n\n:MOVLW imm8\t\t\t\tis op8=0x0e & imm8\t\t\t{ \n\t# 0000 1110 kkkk kkkk\n\t# 0000 1110 0001 0010\t->\tMOVLW #0x12\n\tWREG = imm8;\n}\n\n:MULLW imm8\t\t\t\tis op8=0x0d & imm8\t\t\t{ \n\t# 0000 1101 kkkk kkkk\n\t# 0000 1101 0001 0010\t->\tMULLW #0x12\n\ttmp1:2 = zext(imm8);\n\ttmp2:2 = zext(WREG);\n\tPROD = tmp1 * tmp2;\n}\n\n:RETLW imm8\t\t\t\tis op8=0x0c & imm8\t\t\t{ \n\t# 0000 1100 kkkk kkkk\n\t# 0000 1100 0001 0010\t->\tRETLW #0x12\n\tWREG = imm8;\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\treturn [retAddr];\n}\n\n:SUBLW imm8\t\t\t\tis op8=0x08 & imm8\t\t\t{ \n\t# 0000 1000 kkkk kkkk\n\t# 0000 1000 0001 0010\t->\tSUBLW #0x12\n\tsetSubtractFlags(imm8, WREG); \n\tWREG = imm8 - WREG;\n\tsetResultFlags(WREG);\n}\n\n:XORLW imm8\t\t\t\tis op8=0x0a & imm8\t\t\t{ \n\t# 0000 1010 kkkk kkkk\n\t# 0000 1010 0001 0010\t->\tXORLW #0x12\n\tWREG = WREG ^ imm8;\n\tsetResultFlags(WREG);\n}\n\n#\n# DATA MEMORY <-> PROGRAM MEMORY OPERATIONS\n#\n\n:TBLRD*\t\t\t\t\tis op16=0x0008\t\t\t\t{\n\t# 0000 0000 0000 1000 \n\tptr:3 = TBLPTR;\n\tTABLAT = *[CODE] ptr;\n}\n\n:TBLRD*+\t\t\t\tis op16=0x0009\t\t\t\t{ \n\t# 0000 0000 0000 1001 \n\tptr:3 = TBLPTR;\n\tTABLAT = *[CODE] ptr;\n\tptr = ptr + 1;\n\tTBLPTR = ptr;\n}\n\n:TBLRD*-\t\t\t\tis op16=0x000a\t\t\t\t{ \n\t# 0000 0000 0000 1010 \n\tptr:3 = TBLPTR;\n\tTABLAT = *[CODE] ptr;\n\tptr = ptr - 1;\n\tTBLPTR = ptr;\n}\n\n:TBLRD+*\t\t\t\tis op16=0x000b\t\t\t\t{ \n\t# 0000 0000 0000 1011\n\tptr:3 = TBLPTR;\n\tptr = ptr + 1;\n\tTBLPTR = ptr;\n\tTABLAT = *[CODE] ptr;\n}\n\n:TBLWT*\t\t\t\t\tis op16=0x000c\t\t\t\t{ \n\t# 0000 0000 0000 1100\n\tptr:3 = TBLPTR;\n\t*[CODE] ptr = TABLAT;\n}\n\n:TBLWT*+\t\t\t\tis op16=0x000d\t\t\t\t{ \n\t# 0000 0000 0000 1101\n\tptr:3 = TBLPTR;\n\t*[CODE] ptr = TABLAT;\n\tTBLPTR = ptr + 1;\n}\n\n:TBLWT*-\t\t\t\tis op16=0x000e\t\t\t\t{ \n\t# 0000 0000 0000 1110\n\tptr:3 = TBLPTR;\n\t*[CODE] ptr = TABLAT;\n\tTBLPTR = ptr - 1;\n}\n\n:TBLWT+*\t\t\t\tis op16=0x000f\t\t\t\t{ \n\t# 0000 0000 0000 1111\n\tptr:3 = TBLPTR;\n\tptr = ptr + 1;\n\tTBLPTR = ptr;\n\t*[CODE] ptr = TABLAT;\n}\n\n#\n# EXTENDED INSTRUCTION SET\n#\n\n:ADDFSR xFSRn, imm6\tis op8=0xe8 & xfsr<3 & xFSRn & imm6\t{ \n\t# 1110 1000 ffkk kkkk\n\t# 1110 1000 1001 0010\t->\tADDFSR FSR2, #0x12\n\txFSRn = xFSRn + zext(imm6);\n}\n\n:ADDULNK imm6\t\tis op8=0xe8 & xfsr=3 & imm6\t{ \n\t# 1110 1000 11kk kkkk\n\t# 1110 1000 1101 0010\t->\tADDULNK #0x12\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\tFSR2 = FSR2 + zext(imm6);\n\treturn [retAddr];\n}\n\n:CALLW\t\t\t\tis op16=0x0014\t\t\t\t{ \n\t# 0000 0000 0001 0100\n\tloc:3 = (zext(PCLATU) << 16) | (zext(PCLATH) << 8) | zext(WREG);\n\tpush(&:3 inst_next);\n\tcall [loc];\n}\n\n:MOVSF ZS, destREG32\tis lop9=0x1d6 & ZS & qual4=0xf & destREG32\t{ \n\t# 1110 1011 0zzz zzzz 1111 ffff ffff ffff\n\t# 1110 1011 0001 0010 1111 0001 0010 0011\t->\tMOVSF 0x12[FSR2], DAT_DATA_0123\n\tdestREG32 = ZS;\n}\n\n:MOVSF ZS, destREG32\tis lop9=0x1d6 & ZS & qual4=0xf & destREG32 & fd=0xff9\t{ \n\t# 1110 1011 0zzz zzzz 1111 ffff ffff ffff\n\t# 1110 1011 0001 0010 1111 1111 1111 1001\t->\tMOVSF 0x12[FSR2], PCL\n\taddr:3 = (zext(PCLATU) << 16) + (zext(PCLATH) << 8) + zext(ZS);\n\tgoto [addr];\n}\n\n:MOVSS ZS, ZD\t\tis lop9=0x1d7 & ZS & ZD\t\t{\n\t# 1110 1011 1sss ssss 1111 xxxx xddd dddd\n\t# s: corresponds to zs\n\t# d: corresponds to zd\n\t# x: appear to be unused bits (don't care)\n\t# 1110 1011 1001 0010 1111 1111 1100 0101\t->\tMOVSS 0x12[FSR2], 0x45[FSR2] \t\n\tZD = ZS;\n}\n\n:PUSHL imm8\t\t\tis op8=0xfa & imm8\t\t\t{ \n\t# 1111 1010 kkkk kkkk\n\t# 1111 1010 0001 0010\t->\tPUSHL #0x12\n\tlocal loc = FSR2;\n\t*[DATA]:1 loc = imm8;\n\tFSR2 = loc - 1;\n}\n\n:SUBFSR xFSRn, imm6\tis op8=0xe9 & xfsr<3 & xFSRn & imm6\t{ \n\t# 1110 1001 ffkk kkkk\n\t# 1110 1001 0101 0010\t-> SUBFSR FSR1, 0x12\n\txFSRn = xFSRn - zext(imm6);\n}\n\n:SUBULNK imm6\t\tis op8=0xe9 & xfsr=3 & imm6\t{ \n\t# 1110 1001 11kk kkkk\n\t# 1110 1001 1101 0010\t->\tSUBULNK #0x12\n\tretAddr:4 = 0;\n\tpop(retAddr);\n\tFSR2 = FSR2 - zext(imm6);\n\treturn [retAddr];\n}\n" }, { "path": "pypcode/processors/PIC/data/manuals/PIC-12.idx", "content": "@PIC12_40139e.pdf [PIC12C5XX 8-Pin, 8-Bit CMOS Microcontrollers (DS40139E)]\nADDWF\t,\t49\nANDLW\t,\t49\nANDWF\t,\t49\nBCF\t\t,\t49\nBSF\t\t,\t50\nBTFSC\t,\t50\nBTFSS\t,\t50\nCALL\t,\t51\nCLRF\t,\t51\nCLRW\t,\t51\nCLRWDT\t,\t51\nCOMF\t,\t52\nDECF\t,\t52\nDECFSZ\t,\t52\nGOTO\t,\t52\nINCF\t,\t53\nINCFSZ\t,\t53\nIORLW\t,\t53\nIORWF\t,\t53\nMOVLW\t,\t54\nMOVF\t,\t54\nMOVWF\t,\t54\nNOP\t\t,\t54\nOPTION\t,\t55\nRETLW\t,\t55\nRLF\t\t,\t55\nRRF\t\t,\t55\nSLEEP\t,\t56\nSUBWF\t,\t56\nSWAPF\t,\t57\nTRIS\t,\t57\nXORLW\t,\t57\nXORWF\t,\t57\n" }, { "path": "pypcode/processors/PIC/data/manuals/PIC-16.idx", "content": "@PIC16_33023a.pdf [PICmicro� Mid-Range MCU Family Reference Manual, December 1997 (DS33023A)]\nADDLW\t,\t530\nADDWF\t,\t531\nANDLW\t,\t532\nANDWF\t,\t533\nBCF\t\t,\t534\nBSF\t\t,\t535\nBTFSC\t,\t536\nBTFSS\t,\t537\nCALL\t,\t538\nCLRF\t,\t539\nCLRW\t,\t540\nCLRWDT\t,\t541\nCOMF\t,\t542\nDECF\t,\t543\nDECFSZ\t,\t544\nGOTO\t,\t545\nINCF\t,\t546\nINCFSZ\t,\t547\nIORLW\t,\t548\nIORWF\t,\t549\nMOVLW\t,\t550\nMOVF\t,\t551\nMOVWF\t,\t552\nNOP\t\t,\t553\nOPTION\t,\t554\nRETFIE\t,\t555\nRETLW\t,\t556\nRETURN\t,\t557\nRLF\t\t,\t558\nRRF\t\t,\t559\nSLEEP\t,\t560\nSUBLW\t,\t561\nSUBWF\t,\t562\nSWAPF\t,\t563\nTRIS\t,\t564\nXORLW\t,\t565\nXORWF\t,\t566\n" }, { "path": "pypcode/processors/PIC/data/manuals/PIC-16F.idx", "content": "@PIC16F_40001761E.pdf [Microchip PIC16LF1554/1559 (DS40001761E)]\nADDFSR\t,\t273\nADDLW\t,\t273\nADDWF\t,\t273\nADDWFC\t,\t273\nANDLW\t,\t273\nANDWF\t,\t273\nASRF\t,\t273\nBCF\t\t,\t274\nBRA\t\t,\t274\nBRW\t,\t274\nBSF\t\t,\t274\nBTFSC\t,\t274\nBTFSS\t,\t274\nCALL\t,\t275\nCALLW\t,\t275\nCLRF\t,\t275\nCLRW\t,\t275\nCLRWDT\t,\t275\nCOMF\t,\t275\nDECF\t,\t275\nDECFSZ\t,\t276\nGOTO\t,\t276\nINCF\t,\t276\nINCFSZ\t,\t276\nIORLW\t,\t276\nIORWF\t,\t276\nLSLF\t,\t277\nLSRF\t,\t277\nMOVF\t,\t277\nMOVIW\t,\t278\nMOVLB\t,\t278\nMOVLP\t,\t278\nMOVLW\t,\t278\nMOVWF\t,\t278\nMOVWI\t,\t279\nNOP\t,\t279\nOPTION\t,\t279\nRESET\t,\t279\nRETFIE\t,\t280\nRETLW\t,\t280\nRETURN\t,\t280\nRLF\t\t,\t280\nRRF\t\t,\t281\nSLEEP\t,\t281\nSUBLW\t,\t281\nSUBWF\t,\t281\nSUBWFB\t,\t281\nSWAPF\t,\t282\nTRIS\t,\t282\nXORLW\t,\t282\nXORWF\t,\t282\n" }, { "path": "pypcode/processors/PIC/data/manuals/PIC-17.idx", "content": "@PIC17_30289b.pdf [High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D, 2000 (DS30289B)]\nADDLW\t,\t202\nADDWF\t,\t202\nADDWFC\t,\t203\nANDLW\t,\t203\nANDWF\t,\t204\nBCF\t\t,\t204\nBSF\t\t,\t205\nBTFSC\t,\t205\nBTFSS\t,\t206\nBTG\t\t,\t206\nCALL\t,\t207\nCLRF\t,\t207\nCLRWDT\t,\t208\nCOMF\t,\t208\nCPFSEQ\t,\t209\nCPFSGT\t,\t209\nCPFSLT\t,\t210\nDAW\t\t,\t210\nDECF\t,\t211\nDECFSZ\t,\t211\nDCFSNZ\t,\t212\nGOTO\t,\t212\nINCF\t,\t213\nINCFSZ\t,\t213\nINFSNZ\t,\t214\nIORLW\t,\t214\nIORWF\t,\t215\nLCALL\t,\t215\nMOVFP\t,\t216\nMOVLB\t,\t216\nMOVLR\t,\t217\nMOVLW\t,\t217\nMOVPF\t,\t218\nMOVWF\t,\t218\nMULLW\t,\t219\nMULWF\t,\t219\nNEGW\t,\t220\nNOP\t\t,\t220\nRETFIE\t,\t221\nRETLW\t,\t221\nRETURN\t,\t222\nRLCF\t,\t222\nRLNCF\t,\t223\nRRCF\t,\t223\nRRNCF\t,\t224\nSETF\t,\t224\nSLEEP\t,\t225\nSUBLW\t,\t225\nSUBWF\t,\t226\nSUBWFB\t,\t226\nSWAPF\t,\t227\nTABLRD\t,\t227\nTABLWT\t,\t228\nTLRD\t,\t229\nTLWT\t,\t230\nTSTFSZ\t,\t230\nXORLW\t,\t231\nXORWF\t,\t231\n" }, { "path": "pypcode/processors/PIC/data/manuals/PIC-18.idx", "content": "@PIC18_14702.pdf [PIC18CXX2 High-Performance Microcontrollers with 10-Bit A/D, 7/99 (DS39026B)]\nADDLW\t,\t197\nADDWF\t,\t197\nADDWFC\t,\t198\nANDLW\t,\t198\nANDWF\t,\t199\nBC\t\t,\t199\nBCF\t\t,\t200\nBN\t\t,\t200\nBNC\t\t,\t201\nBNN\t\t,\t201\nBNOV\t,\t202\nBNZ\t\t,\t202\nBRA\t\t,\t203\nBSF\t\t,\t203\nBTFSC\t,\t204\nBTFSS\t,\t204\nBTG\t\t,\t205\nBOV\t\t,\t205\nBZ\t\t,\t206\nCALL\t,\t206\nCLRF\t,\t207\nCLRWDT\t,\t207\nCOMF\t,\t208\nCPFSEQ\t,\t208\nCPFSGT\t,\t209\nCPFSLT\t,\t209\nDAW\t\t,\t210\nDECF\t,\t210\nDECFSZ\t,\t211\nDCFSNZ\t,\t211\nGOTO\t,\t212\nINCF\t,\t212\nINCFSZ\t,\t213\nINFSNZ\t,\t213\nIORLW\t,\t214\nIORWF\t,\t214\nLFSR\t,\t215\nMOVF\t,\t215\nMOVFF\t,\t216\nMOVLB\t,\t216\nMOVLW\t,\t217\nMOVWF\t,\t217\nMULLW\t,\t218\nMULWF\t,\t218\nNEGF\t,\t219\nNOP\t\t,\t219\nPOP\t\t,\t220\nPUSH\t,\t220\nRCALL\t,\t221\nRESET\t,\t221\nRETFIE\t,\t222\nRETLW\t,\t222\nRETURN\t,\t223\nRLCF\t,\t223\nRLNCF\t,\t224\nRRCF\t,\t224\nRRNCF\t,\t225\nSETF\t,\t225\nSLEEP\t,\t226\nSUBWFB\t,\t226\nSUBLW\t,\t227\nSUBWF\t,\t228\nSUBWFB\t,\t229\nSWAPF\t,\t230\nTBLRD\t,\t231\nTBLWT\t,\t232\nTSTFSZ\t,\t233\nXORLW\t,\t233\nXORWF\t,\t234\n" }, { "path": "pypcode/processors/PIC/data/manuals/PIC24.idx", "content": "@70000157g.pdf[16-bit MCU and DSC Programmer's Reference Manual - DS70000157G]\nadd, 102\naddc, 110\nand, 116\nasr, 121\nbclr, 127\nbfext, 130\nbfins, 132\nbootswp, 135\nbra, 136\nbset, 160\nbsw, 163\nbtg, 165\nbtsc, 168\nbtss, 172\nbtst, 175\nbtsts, 180\ncall, 183\ncall.l, 191\nclr, 192\nclrwdt, 196\ncom, 197\ncp, 200\ncp0, 204\ncpb, 206\ncpbeq, 211\ncpbgt, 212\ncpblt, 213\ncpbne, 214\ncpseq, 215\ncpsgt, 217\ncpslt, 219\ncpsne, 221\nctxswp, 223\ndaw.b, 225\ndec, 226\ndec.2, 229\ndisi, 232\ndiv.s, 233\ndiv.u, 235\ndivf, 236\ndivf2, 238\ndiv2.s, 240\ndiv2.u, 241\ndo, 242\ned, 250\nedac, 252\nexch, 254\nfbcl, 255\nff1l, 257\nff1r, 259\nflim, 261\nflim.v, 262\ngoto, 263\ngoto.l, 266\ninc, 267\ninc2, 269\nior, 271\nlac, 276\nlac.d, 278\nldslv, 279\nlnk, 280\nlsr, 282\nmac, 288\nmax, 292\nmax.v, 293\nmin, 294\nmin.v, 295\nminz, 296\nminz.v, 297\nmov, 299\nmov.b, 303\nmov.d, 309\nmovpag, 311\nmovsac, 313\nmpy, 315\nmpy.n, 319\nmsc, 321\nmul, 323\nmul.ss, 325\nmul.su, 328\nmul.us, 333\nmul.uu, 336\nmulw.ss, 341\nmulw.su, 343\nmulw.us, 346\nmulw.uu, 348\nneg, 350\nnop, 354\nnopr, 355\nnorm, 356\npop, 357\npop.d, 359\npop.s, 360\npush, 361\npush.d, 364\npush.s, 365\npwrsav, 366\nrcall, 367\nrepeat, 375\nreset, 379\nretfie, 380\nretlw, 382\nreturn, 386\nrlc, 388\nrlnc, 391\nrrc, 394\nrrnc, 398\nsac, 401\nsac.d, 403\nsac.r, 404\nse, 406\nsetm, 408\nsftac, 410\nsl, 412\nsub, 418\nsubb, 424\nsubbr, 430\nswap, 439\ntblrdh, 440\ntblrdl, 442\ntblwth, 444\ntblwtl, 446\nulnk, 448\nvfslv, 450\nxor, 451\nze, 456\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/4xx.sinc", "content": "#dcread r0,0,r0 0x7c 00 03 cc\n:dcread S,RA_OR_ZERO,B is OP=31 & S & B & (XOP_1_10=486 | XOP_1_10=326) & BIT_0=0 & RA_OR_ZERO\n{\n # ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n S = dataCacheRead(RA_OR_ZERO,B);\n}\n\n# ========================================================================\n\n# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]\n# CMT: Determine Leftmost Zero Byte\n# FORM: X-form\n# binutils: 476.d: 1a4: 7c 83 28 9c dlmzb r3,r4,r5\n# binutils: titan.d: 158: 7c 22 00 9c dlmzb r2,r1,r0\ndefine pcodeop DetermineLeftmostZeroByte;\n:dlmzb S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=0 \n{\n # search from left for the first occurrence of null byte\n\n # low 32 bits of RS concatenated with low 32 bits of RB\n@ifdef BIT_64\n tmpD:8 = zext( S:4 );\n@else\n tmpD:8 = zext( S );\n@endif\n\n tmpD = tmpD << 32;\n\n@ifdef BIT_64\n tmpD = tmpD | zext( B:4 );\n@else\n tmpD = tmpD | zext( B );\n@endif\n\n tmpX:8 = 0;\n\n \n\n if ( tmpX == 8 ) goto ;\n tmpX = tmpX + 1;\n\n if ( ( ( tmpD << ( (tmpX-1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto ;\n\n \n\n # place byte number in register A and low 7 bits of XER\n@ifdef BIT_64\n A = tmpX;\n XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;\n@else\n A = tmpX:4;\n XER = ( XER & 0xFFFFFF80 ) | tmpX:4;\n@endif\n\n}\n\n# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]\n# CMT: Determine Leftmost Zero Byte\n# FORM: X-form\n# binutils: 476.d: 1a8: 7c 83 28 9d dlmzb\\. r3,r4,r5\n# binutils: titan.d: 15c: 7c 22 00 9d dlmzb\\. r2,r1,r0\ndefine pcodeop DetermineLeftmostZeroByte1;\n:dlmzb. S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=1 \n{\n # search from left for the first occurrence of null byte\n\n # low 32 bits of RS concatenated with low 32 bits of RB\n@ifdef BIT_64\n tmpD:8 = zext( S:4 );\n@else\n tmpD:8 = zext( S );\n@endif\n\n tmpD = tmpD << 32;\n\n@ifdef BIT_64\n tmpD = tmpD | zext( B:4 );\n@else\n tmpD = tmpD | zext( B );\n@endif\n\n tmpX:8 = 0;\n tmpY:8 = 0;\n\n \n\n if ( tmpX == 8 ) goto ;\n tmpX = tmpX + 1;\n\n if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto ;\n\n # matched\n tmpY = 1;\n\n \n\n # place byte number in register A and low 7 bits of XER\n@ifdef BIT_64\n A = tmpX;\n XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;\n@else\n A = tmpX:4;\n XER = ( XER & 0xFFFFFF80 ) | tmpX:4;\n@endif\n\n # Rc section\n\n # Set bit 35 of CR to SO\n cr0 = (cr0 & 0xe) | zext( xer_so & 1);\n\n\n # Set bits 32:34 of CR\n if ( tmpY != 1 ) goto ;\n\n if ( tmpX >= 5 ) goto ;\n cr0 = ( cr0 & 0x1 ) | 4;\n goto ;\n\n \n cr0 = ( cr0 & 0x1 ) | 8;\n goto ;\n\n \n cr0 = ( cr0 & 0x1 ) | 2;\n \n}\n\n#icread 0,r0 0x7c 00 07 cc\n:icread RA_OR_ZERO,B\t\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=998 & BIT_0=0 & RA_OR_ZERO\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tinstructionCacheRead(ea);\t\n}" }, { "path": "pypcode/processors/PowerPC/data/languages/FPRC.sinc", "content": "\nperiod: \"\" is Rc=0 { setSummaryFPSCR(); }\nperiod: \".\" is Rc=1 { setSummaryFPSCR(); cr1flags(); }\n\n# Floating Convert To Integer Doubleword Unsigned\n\n:fctidu^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=942 & period\n{\n\t# src is rounded to integer\n\n\tfT = trunc(round(fB));\n\n\t# if src is Nan, result is 0 and VXSNAN is set to 1\n\n\tfT = fT * zext(nan(fB) == 0);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n\n\t# if src > 2^64 - 1, result is 0xffff_ffff_ffff_ffff and VXCVI is set to 1\n\n\tbigi:16 = 0xffffffffffffffff;\n\tbigf:8 = int2float(bigi);\n\tfT = fT - (0xffffffffffffffff + fT) * zext(fB f> bigf);\n\tfp_vxcvi = fp_vxcvi | (fB f> bigf);\n\n\t# if rounded value < 0, result is 0 and VXCVI is set to 1\n\n\tfp_vxcvi = fp_vxcvi | (fT s< 0);\n\tfT = fT * zext(fT s> 0);\n\n\tbuild period;\n}\n\n# Floating Convert To Integer Doubleword Unsigned with round toward Zero\n\n:fctiduz^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=943 & period\n{\n\t# src is rounded to integer\n\n\tfT = trunc(fB);\n\n\t# if src is Nan, result is 0 and VXSNAN is set to 1\n\n\tfT = fT * zext(nan(fB) == 0);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n\n\t# if src > 2^64 - 1, result is 0xffff_ffff_ffff_ffff and VXCVI is set to 1\n\n\tbigi:16 = 0xffffffffffffffff;\n\tbigf:8 = int2float(bigi);\n\tfT = fT - (0xffffffffffffffff + fT) * zext(fB f> bigf);\n\tfp_vxcvi = fp_vxcvi | (fB f> bigf);\n\n\t# if rounded value < 0, result is 0 and VXCVI is set to 1\n\n\tfp_vxcvi = fp_vxcvi | (fT s< 0);\n\tfT = fT * zext(fT s> 0);\n\n\tbuild period;\n}\n\n# Floating Convert To Integer Word Unsigned\n\n:fctiwu^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=142 & period\n{\n\t# src is rounded to integer\n\n\tfT = trunc(round(fB));\n\n\t# if src is NaN then result is 0 and VXSNAN is set to 1\n\n\tfT = fT * zext(nan(fB) == 0);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n\n\t# if src > 2^32 - 1, result is 0xffff_ffff and VXCVI is set to 1\n\n\tbigi:16 = 0xffffffff;\n\tbigf:8 = int2float(bigi);\n\tfT = fT - (0xffffffff + fT) * zext(fB f> bigf);\n\tfp_vxcvi = fp_vxcvi | (fB f> bigf);\n\n\t# if rounded value < 0, result is 0 and VXCVI is set to 1\n\n\tfp_vxcvi = fp_vxcvi | (fT s< 0);\n\tfT = fT * zext(fT s> 0);\n\n\tbuild period;\n}\n\n# Floating Convert To Integer Word Unsigned with round toward Zero\n\n:fctiwuz^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=143 & period\n{\n\t# src is rounded to integer\n\n\tfT = trunc(fB);\n\n\t# if src is NaN then result is 0 and VXNAN is set to 1\n\n\tfT = fT * zext(nan(fB) == 0);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n\n\t# if src > 2^32 - 1, result is 0xffff_ffff and VXCVI is set to 1\n\n\tbigi:16 = 0xffffffff;\n\tbigf:8 = int2float(bigi);\n\tfT = fT - (0xffffffff + fT) * zext(fB f> bigf);\n\tfp_vxcvi = fp_vxcvi | (fB f> bigf);\n\n\t# if rounded value < 0, result is 0 and VXCVI is set to 1\n\n\tfp_vxcvi = fp_vxcvi | (fT s< 0);\n\tfT = fT * zext(fT s> 0);\n\n\tbuild period;\n}\n\n# Floating Convert From Integer Doubleword Unsigned X-form\n\n:fcfidu^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=974 & period\n{\n\t# convert source to unsigned int by extension\n\n\tlocal tmpI:8 = zext(fB);\n\n\t# src is converted to floating point\n\n\tfT = int2float(tmpI);\n\n\t# FPSCR is class and sign of result\n\n\tsetFPRF(fT);\n\n\tbuild period;\n}\n\n# Floating Convert From Integer Doubleword Single X-form\n\n:fcfids^period fT,fB is $(NOTVLE) & OP=59 & fT & BITS_16_20=0 & fB & XOP_1_10=846 & period\n{\n\t# src is converted to single-precision floating point\n\n\tlocal tmpF:4 = int2float(fB);\n\n\t# convert the result to double-precision\n\n\tfT = float2float(tmpF);\n\n\t# FPSCR is class and sign of result\n\n\tsetFPRF(fT);\n\n\tbuild period;\n}\n\n# fcfidus fT,fB\n# Floating Convert From Integer Doubleword Unsigned Single\n\n:fcfidus^period fT,fB is $(NOTVLE) & OP=59 & fT & BITS_16_20=0 & fB & XOP_1_10=974 & period\n{\n\t# convert source to unsigned int by extension\n\n\tlocal tmpI:8 = zext(fB);\n\n\t# src is converted to single-precision floating point\n\n\tlocal tmpF:4 = int2float(tmpI);\n\n\t# src is converted to double-precision\n\n\tfT = float2float(tmpF);\n\n\t# FPSCR is class and sign of result\n\n\tsetFPRF(fT);\n\n\tbuild period;\n}\n\n# Floating Test for software Divide\n\n:ftdiv CRFD,fA,fB is $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & fA & fB & XOP_1_10=128 & BIT_0=0\n{\n\tzero:8 = int2float(0:1);\n\n\t# fe if fA or fB is Nan or infinity, or if fB is 0\n\t# and other conditions on the exponents\n\n\tfe_flag:1 = nan(fA) | nan(fB) | (fB f== zero);\n\n\t# fg if fA or fB are infinite, or fB is NaN or denomrmalized or zero\n\n\tfg_flag:1 = nan(fB) | (fB f== zero);\n\tCRFD = (fg_flag << 2) | (fe_flag << 1);\n}\n\n# Floating Test for software Square Root\n\n:ftsqrt CRFD,fB is $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & BITS_16_20=0 & fB & XOP_1_10=160 & BIT_0=0\n{\n\tzero:8 = int2float(0:1);\n\n\t# fe if fB is zero, NAN, infinity, or negative\n\n\tfe_flag:1 = nan(fB) | (fB f< zero);\n\n\t# fg if fB is zero, infinity, or denormalized\n\n\tfg_flag:1 = nan(fB) | (fB f== zero);\n\tCRFD = (fg_flag << 2) | (fe_flag << 1);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/PowerPC.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/SPEF_SCR.sinc", "content": "# Based on \"PowerISA Version 2.06 Revision B\" document dated July 23, 2010\n# Category: SPE.Embedded Float Vector Instructions\n\n# version 1.0\n\ndefine register offset=0x600 size=1 [\n\tspef_sovh spef_ovh spef_fgh spef_fxh spef_finvh spef_fdbzh spef_funfh spef_fovfh \n\tspef_reserved1 spef_reserved2\n\tspef_finxs spef_finvs spef_fdbzs spef_funfs spef_fovfs\n\tspef_reserved3\n\tspef_sov spef_ov spef_fg spef_fx spef_finv spef_fdbz spef_funf spef_fovf\n\tspef_reserved4\n\tspef_finxe spef_finve spef_fdbze spef_funfe spef_fovfe spef_frmc0 spef_frmc1 \n];\n\n\nmacro setSPEFSCR_L(result) {\n\tspef_finv = nan(result);\n\tspef_finvs = spef_finvs | spef_finv;\n}\n\n\nmacro setSPEFSCR_H(result) {\n\tspef_finvh = nan(result);\n\tspef_finvs = spef_finvs | spef_finvh;\n}\n\n\nmacro setSummarySPEFSCR() {\n spef_sov = spef_sov | spef_ov;\n\n spef_sovh = spef_sovh | spef_ovh;\n\n\tspef_finxs = spef_finxs | spef_fx | spef_fxh;\n\tspef_finvs = spef_finvs | spef_finv | spef_finvh;\n\tspef_fdbzs = spef_fdbzs | spef_fdbz | spef_fdbzh;\n\tspef_funfs = spef_funfs | spef_funf | spef_funfh;\n\tspef_fovfs = spef_fovfs | spef_fovf | spef_fovfh;\n}\n\n\nmacro setSPEFSCRAddFlags_L(op1, op2, result) {\n\tsetSPEFSCR_L(result);\n\tspef_fx = spef_fx | nan(op1) | nan(op2);\n\tspef_finv = spef_fx;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRAddFlags_H(op1, op2, result) {\n\tsetSPEFSCR_H(result);\n\tspef_fxh = spef_fxh | nan(op1) | nan(op2);\n\tspef_finvh = spef_fxh;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRDivFlags_L(op1, op2, result) {\n\tsetSPEFSCR_L(result);\n\tspef_fdbz = spef_fdbz | (op2 f== 0);\n\tspef_fx = spef_fx | nan(op1) | nan(op2);\n\tspef_finv = spef_fx;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRDivFlags_H(op1, op2, result) {\n\tsetSPEFSCR_H(result);\n\tspef_fdbzh = spef_fdbzh | (op2 f== 0);\n\tspef_fxh = spef_fxh | nan(op1) | nan(op2);\n\tspef_finvh = spef_fxh;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRMulFlags_L(op1, op2, result) {\n\tsetSPEFSCR_L(result);\n\tspef_fx = spef_fx | nan(op1) | nan(op2);\n\tspef_finv = spef_fx;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRMulFlags_H(op1, op2, result) {\n\tsetSPEFSCR_H(result);\n\tspef_fxh = spef_fxh | nan(op1) | nan(op2);\n\tspef_finvh = spef_fxh;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRSubFlags_L(op1, op2, result) {\n\tsetSPEFSCR_L(result);\n\tspef_fx = spef_fx | nan(op1) | nan(op2);\n\tspef_finv = spef_fx;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro setSPEFSCRSubFlags_H(op1, op2, result) {\n\tsetSPEFSCR_H(result);\n\tspef_fxh = spef_fxh | nan(op1) | nan(op2);\n\tspef_finvh = spef_fxh;\n\tsetSummarySPEFSCR();\n}\n\n\nmacro packSPEFSCR(tmp) {\n\tpackbits(tmp,\n\t\tspef_sovh, spef_ovh, spef_fgh, spef_fxh, spef_finvh, spef_fdbzh, spef_funfh, spef_fovfh, \n\t\tspef_reserved1, spef_reserved2,\n\t\tspef_finxs, spef_finvs, spef_fdbzs, spef_funfs, spef_fovfs,\n\t\tspef_reserved3,\n\t\tspef_sov, spef_ov, spef_fg, spef_fx, spef_finv, spef_fdbz, spef_funf, spef_fovf,\n\t\tspef_reserved4,\n\t\tspef_finxe, spef_finve, spef_fdbze, spef_funfe, spef_fovfe, spef_frmc0, spef_frmc1 );\n}\n\n\nmacro unpackSPEFSCR(tmp) {\n\tunpackbits(tmp,\n\t\tspef_sovh, spef_ovh, spef_fgh, spef_fxh, spef_finvh, spef_fdbzh, spef_funfh, spef_fovfh, \n\t\tspef_reserved1, spef_reserved2,\n\t\tspef_finxs, spef_finvs, spef_fdbzs, spef_funfs, spef_fovfs,\n\t\tspef_reserved3,\n\t\tspef_sov, spef_ov, spef_fg, spef_fx, spef_finv, spef_fdbz, spef_funf, spef_fovf,\n\t\tspef_reserved4,\n\t\tspef_finxe, spef_finve, spef_fdbze, spef_funfe, spef_fovfe, spef_frmc0, spef_frmc1 );\n}\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/SPE_APU.sinc", "content": "# Based on \"EREF: A Reference for Motorola Book E and e500 Core\" document version 01/2004 Rev2\n# Instructions that are specific to the (PowerPC) e500 core are implemented as auxiliary processing units (APUs)\n# Signal Processing Engine APU (SPE APU)\n\n@ifdef BIT_64\n@define MEMMASK \"0xFFFFFFFFFFFFFFFF\"\n@else\n@define MEMMASK \"0xFFFFFFFF\"\n@endif\n\n\n# There are three versions of e500 core, namely e500v1, the e500v2, and the e500mc.\n# A 64-bit evolution of the e500mc core is called e5500 core.\n# All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores.\n\n# The SPE, and embedded SPFP functionality is implemented in\n# the MPC8540, the MPC8560 and in their derivatives (that is, in\n# all PowerQUICC III devices). However, these instructions will\n# not be supported in devices subsequent to PowerQUICC III.\n\n# version 1.0\n\n# SPEFSCR.OVH Integer Overflow High bit 33\n# SPEFSCR.OV Integer Overflow bit 49\n# SPEFSCR.SOVH Summary Integer Overflow High bit 32\n# SPEFSCR.SOV Summary Integer Overflow bit 48\n\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl\n\n# The SPE requires a GPR register file with thirty-two\n# 64-bit registers. For 32-bit implementations, instructions\n# that normally operate on a 32-bit register file\n# access and change only the least significant 32-bits of\n# the GPRs leaving the most significant 32-bits\n# unchanged. For 64-bit implementations, operation of\n# these instructions is unchanged, i.e. those instructions\n# continue to operate on the 64-bit registers as they\n# would if the SPE was not implemented. Most SPE\n# instructions view the 64-bit register as being composed\n# of a vector of two elements, each of which is 32 bits\n# wide (some instructions read or write 16-bit elements).\n# The most significant 32-bits are called the upper word,\n# high word or even word. The least significant 32-bits\n# are called the lower word, low word or odd word.\n# Unless otherwise specified, SPE instructions write all\n# 64-bits of the destination register.\n\n# Key to some symbols used in descriptions\n# RT.l => low part of RT 0-31 bits\n# RT.h => high part of RT 32-63 bits\n# RT.t => total RT 0-63 bits\n# temp.b31 => bit 31 of temp\n# temp.B1 => byte 1 of temp\n# temp.S0 => first 2 bytes\n# ABS()\n# EXTZ() => Result of extending x on the left with sign bits\n# SATURATE() => \n# ONESCOMP() => one's complement\n# CR.bsub(..:..)=> bit range\n# >u => unsigned greaterthan\n# EQUIV => Equivalence logical operators = (a ^ (ONESCOMP(B)))\n# *si Signed-integer multiplication\n# *ui Unsigned-integer multiplication\n\n# *gsf \n# Guarded signed fractional multiplication.\n# Result of multiplying 2 signed fractional\n# quantities having bit length 16 taking the\n# least significant 31 bits of the sign\n# extended product and concatenating a 0\n# to the least significant bit forming a\n# guarded signed fractional result of 64 bits.\n# Since guarded signed fractional multiplication\n# produces a 64-bit result, fractional\n# input quantities of -1 and -1 can produce\n# +1 in the intermediate product. Two 16-bit\n# fractional quantities, a and b are multiplied,\n# as shown below:\n# ea0:31 = EXTS(a)\n# eb0:31 = EXTS(b)\n# prod0:63 = ea X eb\n# eprod0:63 = EXTS(prod32:63)\n# result0:63 = eprod1:63 || 0b0\n\ndefine pcodeop GuardedSignedFractionalMultiplication;\n\n# *sf\n# Signed fractional multiplication. Result of\n# multiplying 2 signed fractional quantities\n# having bit length n taking the least significant\n# 2n-1 bits of the sign extended product\n# and concatenating a 0 to the least significant\n# bit forming a signed fractional result\n# of 2n bits. Two 16-bit signed fractional\n# quantities, a and b are multiplied, as\n# shown below:\n# ea0:31 = EXTS(a)\n# eb0:31 = EXTS(b)\n# prod0:63 = ea X eb\n# prod0:63 = EXTS(prod32:63)\n# result0:31 = eprod33:63 || 0b0\n\ndefine pcodeop SignedFractionalMultiplication;\n\n# ==================================================================\n\n# =======================================================================\n# Page D-10\n\n# evabs RT,RA\n# ISA-cmt: Vector Absolute Value\n# evabs rD,rA 010 0000 1000 SPE_APU_Vector_Instructions\n:evabs D,A is OP=4 & D & A & XOP_0_10=0x208 & BITS_11_15=0 {\n # RT.l = ABS(RA.l);\n # RT.h = ABS(RA.h);\n\n temp:8 = zext(A); \n lo:8 = (( temp & (0x00000000FFFFFFFF) ) ); \n lo = zext( ((lo:4 + (lo:4 >> 32)) ^ (lo:4 >> 32)) ); \n hi:8 = (( temp & (0xFFFFFFFF00000000) ) >> 32); \n hi = zext( ((hi:4 + (hi:4 >> 32)) ^ (hi:4 >> 32)) ); \n D = (( zext(hi) << 32) | zext(lo) ); \n}\n\n# evaddiw RT,RB,UI\n# ISA-cmt: Vector Add Immediate Word\n# evaddiw rD,BU_UIMM,rB 010 0000 0010 SPE_APU_Vector_Instructions\n:evaddiw D,B,BU_UIMM is OP=4 & D & BU_UIMM & B & XOP_0_10=0x202 {\n # RT.l = RB.l + EXTZ(UI);\n # RT.h = RB.h + EXTZ(UI);\n\n tmp:8 = BU_UIMM;\n lo:8 = (( B & (0x00000000FFFFFFFF) ) ) + (tmp & 0xFFFF);\n hi:8 = (( B & (0xFFFFFFFF00000000) ) >> 32) + (tmp & 0xFFFF);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evaddsmiaaw RT,RA\n# ISA-cmt: Vector Add Signed, Modulo, Integer to Accumulator Word\n# evaddsmiaaw rD,rA 100 1100 1001 SPE_APU_Vector_Instructions\n:evaddsmiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C9 & BITS_11_15=0 {\n # RT.l = ACC.l + RA.l;\n # RT.h = ACC.h + RA.h;\n # ACC.t = RT.t;\n\n lo:8 = (( ACC & (0x00000000FFFFFFFF) ) ) + (( A & (0x00000000FFFFFFFF) ) );\n hi:8 = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + (( A & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# macro SATURATE(ov,carry, sat_ovn, sat_ov, val) {\n# sat = (ov * carray)*sat_ovn + (ov * !carray)*sat_ov + (! ov) * val;\n# }\n\n# evaddssiaaw RT,RA\n# ISA-cmt: Vector Add Signed, Saturate, Integer to Accumulator Word\n# evaddssiaaw rD,rA 100 1100 0001 SPE_APU_Vector_Instructions\ndefine pcodeop VectorAddSignedSaturateIntgerToAccumulatorWord1;\ndefine pcodeop VectorAddSignedSaturateIntgerToAccumulatorWord2;\n:evaddssiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C1 & BITS_11_15=0 {\n # TODO definition complicated SATURATE()\n # temp.t = EXTS(ACC.l) + EXTS(RA.l);\n # ovh = temp.b31 ^ temp.b32;\n # RT.l = SATURATE(ovh, temp.b31, 0x8000_0000, 0x7FFF_FFFF, temp.h);\n # temp.t = EXTS(ACC.h) + EXTS(RA.h);\n # ovl = temp.31 ^ temp.32;\n # RT.h = SATURATE(ovl, temp.b31, 0x8000_0000, 0x7FFF_FFFF, temp.h);\n # ACC.t = RT.t;\n # SPEFSCR.ovh = ovh;\n # SPEFSCR.ov = ov;\n # SPEFSCR.sovh = SPEFSCR.sovh | ovh;\n # SPEFSCR.sov = SPEFSCR.sov | ovh;\n\n# temp:8 = sext( extrBytes(ACC,8,4,0) ) + sext( extrBytes(A,8,4,0) );\n# ovh = getBits(temp,31,31,8) ^ getBits(temp,32,32,8);\n# SATURATE(ovh, getBits(temp,31,31,8), 0x80000000,0x7FFFFFFF, temp);\n# lo = sat;\n \n D = VectorAddSignedSaturateIntgerToAccumulatorWord1(ACC, A);\n spr200 = VectorAddSignedSaturateIntgerToAccumulatorWord2(ACC, A);\n}\n\n# evaddumiaaw RT,RA\n# ISA-cmt: Vector Add Unsigned, Modulo, Integer to Accumulator Word\n# evaddumiaaw rD,rA 100 1100 1000 SPE_APU_Vector_Instructions\n:evaddumiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C8 & BITS_11_15=0 {\n # RT.l = ACC.l + RA.l;\n # RT.h = ACC.h + RA.h;\n # ACC.t = RT.t;\n\n lo:8 = (( ACC & (0x00000000FFFFFFFF) ) ) + (( A & (0x00000000FFFFFFFF) ) );\n hi:8 = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + (( A & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evaddusiaaw RT,RA\n# ISA-cmt: Vector Add Unsigned, Saturate, Integer to Accumulator Word\n# evaddusiaaw rD,rA 100 1100 0000\ndefine pcodeop VectorAddUnsignedSaturateIntegerToAccumulatorWord1;\ndefine pcodeop VectorAddUnsignedSaturateIntegerToAccumulatorWord2;\n:evaddusiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C0 & BITS_11_15=0 {\n # TODO definition complicated SATURATE()\n # temp.t = EXTZ(ACC.l) + EXTZ(RA.l);\n # ovh = temp.b31;\n # RT.l = SATURATE(ovh, temp.31, 0xFFFF_FFFF, 0xFFFF_FFFF, temp.h);\n # ovl = temp.b31\n # RT.h = SATURATE(ovl, temp.31, 0xFFFF_FFFF, 0xFFFF_FFFF, temp.h);\n # ACC.t = RT.t;\n # SPEFSCR.ovh = ovh;\n # SPEFSCR.ov = SPESCR.sovh | ovh;\n # SPEFSCR.sovh = SPESCR.sov | ovl;\n\n D = VectorAddUnsignedSaturateIntegerToAccumulatorWord1(ACC, A);\n spr200 = VectorAddUnsignedSaturateIntegerToAccumulatorWord2(ACC, A);\n}\n\n# evaddw RT,RA,RB\n# ISA-cmt: Vector Add Word\n# evaddw rD,rA,rB 010 0000 0000\n:evaddw D,A,B is OP=4 & D & A & B & XOP_0_10=0x200 {\n # RT.l = RA.l + RB.l;\n # RT.h = RA.h + RB.h;\n\n lo:8 = (( A & (0x00000000FFFFFFFF) ) ) + (( B & (0x00000000FFFFFFFF) ) );\n hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) + (( B & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evand RT,RA,RB\n# ISA-cmt: Vector AND\n# evand rD,rA,rB 010 0001 0001\n:evand D,A,B is OP=4 & D & A & B& XOP_0_10=0x211 {\n # RT.l = RA.l & RB.l;\n # RT.h = RA.h & RB.h;\n\n lo:8 = (( A & (0x00000000FFFFFFFF) ) ) & (( B & (0x00000000FFFFFFFF) ) );\n hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) & (( B & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evandc RT,RA,RB\n# ISA-cmt: Vector AND with Complement\n# evandc rD,rA,rB 010 0001 0010\n:evandc D,A,B is OP=4 & D & A & B & XOP_0_10=0x212 {\n # RT.l = RA.l & (ONESCOMP(RB.l));\n # RT.h = RA.h & (ONESCOMP(RB.h));\n\n lo:8 = (( A & (0x00000000FFFFFFFF) ) ) & (~ (( B & (0x00000000FFFFFFFF) ) ));\n hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) & (~ (( B & (0xFFFFFFFF00000000) ) >> 32));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evcmpeq BF,RA,RB\n# ISA-cmt: Vector Compare Equal\n# evcmpeq crfD,rA,rB 010 0011 0100\n:evcmpeq crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x234 & BITS_21_22=0 {\n # ah = RA.l\n # al = RA.h\n # bh = RB.l\n # bl = RB.h\n # if (ah == bh) { \n # ch = 1; \n # } else {\n # ch = 0;\n # }\n # if (al == bl) {\n # cl = 1;\n # } else {\n # cl = 0;\n # }\n # CR.bsub(4xBF+32:4xBF+35) = ch || cl || (ch | cl) || (ch & cl);\n \n lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF);\n hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32);\n b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);\n b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);\n\n if (hi == b_hi) goto ;\n ch:1 = 0;\n \n ch = 1;\n if (lo == b_lo) goto ;\n cl:1 = 0;\n \n ch = 1;\n crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3));\n}\n\n# evcmpgts BF,RA,RB\n# ISA-cmt: Vector Compare Greater Than Signed\n# evcmpgts crfD,rA,rB 010 0011 0001\n:evcmpgts crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x231 & BITS_21_22=0 {\n # ah = RA.l;\n # al = RA.h;\n # bh = RB.l;\n # bl = RB.h;\n # if (ah > bh) {\n # ch = 1;\n # } else {\n # ch = 0;\n # }\n # if (al > bl) {\n # cl = 1;\n # } else {\n # ch = 0;\n # }\n # CR.bsub(4xBF+32:4xBF+35) = ch || cl || (ch | cl) || (ch & cl);\n\n lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF);\n hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32);\n b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);\n b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);\n\n if (hi s> b_hi) goto ;\n ch:1 = 0;\n \n ch = 1;\n\n if (lo s> b_lo) goto ;\n cl:1 = 0;\n \n cl = 1;\n crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3));\n}\n\n# evcmpgtu BF,RA,RB\n# ISA-cmt: Vector Compare Greater Than Unsigned\n# evcmpgtu crfD,rA,rB 010 0011 0000\n:evcmpgtu crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x230 & BITS_21_22=0 {\n # ah = RA.l;\n # al = RA.h;\n # bh = RB.l;\n # bl = RB.h;\n # if (ah >u bh) {\n # ch = 1;\n # } else {\n # ch = 0;\n # } \n # if (al >u bl) {\n # cl = 1;\n # } else {\n # cl = 0;\n # }\n # CR.bsub(4xBF+32:4xBF+35) = ch || cl || (ch | cl) || (ch & cl);\n\n lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF);\n hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32);\n b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);\n b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);\n\n if (hi > b_hi) goto ;\n ch:1 = 0;\n \n ch = 1;\n\n if (lo > b_lo) goto ;\n cl:1 = 0;\n \n cl = 1;\n\n crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3));\n}\n\n# evcmplts BF,RA,RB\n# ISA-cmt: Vector Compare Less Than Signed\n# evcmplts crfD,rA,rB 010 0011 0011\n:evcmplts crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x233 & BITS_21_22=0 {\n # ah = RA.l;\n # al = RA.h;\n # bh = RB.l;\n # bl = RB.h;\n # if (ah < bh) {\n # ch = 1;\n # } else {\n # ch = 0;\n # } \n # if (al < bl) {\n # cl = 1;\n # } else {\n # cl = 0;\n # }\n # CR.bsub(4xBF+32:4xBF+35) = ch || ch || (ch | cl) || (ch & cl);\n\n lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF);\n hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32);\n b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);\n b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);\n\n if (hi s< b_hi) goto ;\n ch:1 = 0;\n \n ch = 1;\n\n if (lo s< b_lo) goto ;\n cl:1 = 0;\n \n cl = 1;\n\n crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3));\n}\n\n# evcmpltu BF,RA,RB\n# ISA-cmt: Vector Compare Less Than Unsigned\n# evcmpltu crfD,rA,rB 010 0011 0010\n:evcmpltu crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x232 & BITS_21_22=0 {\n # ah = RA.l;\n # al = RA.h;\n # bh = RB.l;\n # bl = RB.h;\n # if (ah > 32);\n b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);\n b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);\n\n if (hi < b_hi) goto ;\n ch:1 = 0;\n \n ch = 1;\n\n if (lo < b_lo) goto ;\n cl:1 = 0;\n \n cl = 1;\n\n crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3));\n}\n\n# evcntlsw RT,RA\n# ISA-cmt: Vector Count Leading Signed Bits Word\n# evcntlsw rD,rA 010 0000 1110\ndefine pcodeop VectorCountLeadingSignBitsWord;\n:evcntlsw D,A is OP=4 & D & A & XOP_0_10=0x20E & BITS_11_15=0 { \n # TODO definition complicated\n # n = 0;\n # s = RA.b(n);\n # do while (n < 32) {\n # if (RA.b(n) != s) {\n # leave;\n # } else {\n # n = n + 1;\n # }\n # RT.l = n;\n # n = 0;\n # s = RA.b(n+32);\n # do while (n < 32) {\n # if (RA.b(n+32) != s) {\n # leave;\n # } \n # n = n + 1;\n # }\n # RT.h = n;\n # }\n\n D = VectorCountLeadingSignBitsWord(A); \n}\n\n# evcntlzw RT,RA\n# ISA-cmt: Vector Count Leading Zeros Word\n# evcntlzw rD,rA 010 0000 1101\ndefine pcodeop VectorCountLeadingZerosWord;\n:evcntlzw D,A is OP=4 & D & A & XOP_0_10=0x20D & BITS_11_15=0 { \n # TODO definition\n # n = 0;\n # do while (n < 32) {\n # if (RA.b(n) = 1) {\n # leave;\n # } else {\n # n = n + 1;\n # }\n # } \n # RT.l = n;\n # n = 0;\n # do while (n < 32) {\n # if (RA.b(n+32) == 1) {\n # leave;\n # } else {\n # n = n + 1;\n # }\n # }\n # RT.h = n;\n\n D = VectorCountLeadingZerosWord(A); \n}\n\n# evdivws RT,RA,RB\n# ISA-cmt: Vector Divide Word Signed\n# evdivws rD,rA,rB 100 1100 0110\ndefine pcodeop VectorDivideWordSigned1;\ndefine pcodeop VectorDivideWordSigned2;\n:evdivws D,A,B is OP=4 & D & A & B & XOP_0_10=0x4C6 {\n # TODO definition complicated\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n\n D = VectorDivideWordSigned1(A,B);\n flags:8 = VectorDivideWordSigned2(A,B); \n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evdivwu RT,RA,RB\n# ISA-cmt: Vector Divide Word Unsigned\n# evdivwu rD,rA,rB 100 1100 0111\ndefine pcodeop VectorDivideWordUnsigned1;\ndefine pcodeop VectorDivideWordUnsigned2;\n:evdivwu D,A,B is OP=4 & D & A & B & XOP_0_10=0x4C7 {\n # TODO definition complicated\n# SPEFSCR.OV = ovl\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl\n\n D = VectorDivideWordUnsigned1(A,B);\n flags:8 = VectorDivideWordUnsigned2(A,B); \n\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n\n# eveqv RT,RA,RB\n# ISA-cmt: Vector Equivalent\n# eveqv rD,rA,rB 010 0001 1001\n:eveqv D,A,B is OP=4 & D & A & B & XOP_0_10=0x219 {\n # RT.l = EQUIV(RA.l, RB.l);\n # RT.h = EQUIV(RA.h, RB.h);\n\n lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF);\n hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32);\n b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF);\n b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32);\n\n lo = lo ^ b_lo; # TODO check\n hi = hi ^ b_hi;\n\n D = ((hi << 32) | lo);\n}\n\n# evextsb RT,RA\n# ISA-cmt: Vector Extend Sign Byte\n# evextsb rD,rA 010 0000 1010\n:evextsb D,A is OP=4 & D & A & XOP_0_10=0x20A & BITS_11_15=0 {\n # RT.l = EXTS(RA.B3);\n # RT.h = EXTS(RA.B7);\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FF000000) ) >> 24);\n hi:$(REGISTER_SIZE) = (( A & (0xFF00000000000000) ) >> 56);\n lo = sext(lo:1);\n hi = sext(hi:1);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evextsh RT,RA\n# ISA-cmt: Vector Extend Sign Halfword\n# evextsh rD,rA, 010 0000 1011\n:evextsh D,A is OP=4 & D & A & XOP_0_10=0x20B & BITS_11_15=0 { \n # RT.l = EXTS(RA.S1);\n # RT.h = EXTS(RA.S3);\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48);\n lo = sext(lo:2);\n hi = sext(hi:2);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# =======================================================================\n# Page D-11\n\n# evldd RT,D(RA)\n# ISA-cmt: Vector Load Double Word into Double Word\n# evldd rD,d(rA)\n:evldd RT,dUI16PlusRAOrZeroAddress is OP=4 & RT & dUI16PlusRAOrZeroAddress & XOP_0_10=769\n{\n ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;\n RT = *:8 ($(EATRUNC));\n}\n\n# evlddx RT,RA,RB\n# ISA-cmt: Vector Load Double Word into Double Word Indexed\n# evlddx\n:evlddx RT,RA_OR_ZERO,RB is OP=4 & RT & RA_OR_ZERO & RB & XOP_0_10=768\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;\n RT = *:8 ($(EATRUNC));\n}\n\n# evldh RT,D(RA)\n# ISA-cmt: Vector Load Double into Four Halfwords\n# evldh rD,rA 011 0000 0101\n\n\n:evldh RT,EVUIMM_8_RAt is OP=4 & RT & EVUIMM_8_RAt & XOP_0_10=0x305 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*8);\n# RT.S0 = MEM(EA, 2);\n# RT.S1 = MEM(EA+2, 2);\n# RT.S2 = MEM(EA+4, 2);\n# RT.S3 = MEM(EA+6, 2);\n\n EA:8 = EVUIMM_8_RAt;\n *:2 (RT) = *:2 ((EA) & $(MEMMASK));\n *:2 (RT+2) = *:2 ((EA+2) & $(MEMMASK));\n *:2 (RT+4) = *:2 ((EA+4) & $(MEMMASK));\n *:2 (RT+6) = *:2 ((EA+6) & $(MEMMASK));\n}\n\n# evldhx RT,RA,RB\n# ISA-cmt: Vector Load Double into Four Halfwords Indexed\n# evldhx rD,rA,rB 011 0000 0100\n\n:evldhx D,A,B is OP=4 & A & D & B & XOP_0_10=0x304 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.S0 = MEM(EA, 2);\n# RT.S1 = MEM(EA+2, 2);\n# RT.S2 = MEM(EA+4, 2);\n# RT.S3 = MEM(EA+6, 2);\n\n EA:8 = A + B;\n *:2 (D) = *:2 ((EA) & $(MEMMASK));\n *:2 (D+2) = *:2 ((EA+2) & $(MEMMASK));\n *:2 (D+4) = *:2 ((EA+4) & $(MEMMASK));\n *:2 (D+6) = *:2 ((EA+6) & $(MEMMASK));\n}\n\n# evldw RT,D(RA)\n# ISA-cmt: Vector Load Double into Two Words\n# evldw rD,rA 011 0000 0011\n:evldw RT,EVUIMM_8_RAt is OP=4 & RT & EVUIMM_8_RAt & XOP_0_10=0x303 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*8);\n# RT.l = MEM(EA, 4);\n# RT.h = MEM(EA+4, 4);\n\n EA:$(REGISTER_SIZE) = EVUIMM_8_RAt;\n *:4 (RT) = *:4 ((EA) & $(MEMMASK));\n *:4 (RT+4) = *:4 ((EA+4) & $(MEMMASK));\n}\n\n# evldwx RT,RA,RB\n# ISA-cmt: Vector Load Double into Two Words Indexed\n# evldwx rD,rA,rB 011 0000 0010\n:evldwx D,A,B is OP=4 & A & B & D & XOP_0_10=0x302 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.l = MEM(EA, 4);\n# RT.h = MEM(EA+4, 4);\n \n EA:$(REGISTER_SIZE) = A + B;\n *:4 (D) = *:4 ((EA) & $(MEMMASK));\n *:4 (D+4) = *:4 ((EA+4) & $(MEMMASK));\n}\n\n# evlhhesplat RT,D(RA)\n# ISA-cmt: Vector Load Halfword into Halfwords Even and Splat\n# evlhhesplat rD,rA 011 0000 1001\n:evlhhesplat RT,EVUIMM_2_RAt is OP=4 & RT & EVUIMM_2_RAt & XOP_0_10=0x309 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*2);\n# RT.S0 = MEM(EA,2);\n# RT.S1 = 0x0000;\n# RT.S2 = MEM(EA,2);\n# RT.S3 = 0x0000;\n\n EA:$(REGISTER_SIZE) = EVUIMM_2_RAt;\n *:2 (RT) = *:2 ((EA) & $(MEMMASK));\n *:2 (RT+2) = 0x0000;\n *:2 (RT+4) = *:2 ((EA) & $(MEMMASK));\n *:2 (RT+6) = 0x0000;\n}\n\n# evlhhesplatx RT,RA,RB\n# ISA-cmt: Vector Load Halfword into Halfwords Even and Splat Indexed\n# evlhhesplatx rD,rA,rB 011 0000 1000\n:evlhhesplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x308 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.S0 = MEM(EA, 2);\n# RT.S1 = 0x0000;\n# RT.S2 = MEM(EA, 2);\n# RT.S3 = 0x0000;\n \n EA:$(REGISTER_SIZE) = A + B;\n *:2 (D) = *:2 ((EA) & $(MEMMASK));\n *:2 (D+2) = 0x0000;\n *:2 (D+4) = *:2 ((EA) & $(MEMMASK));\n *:2 (D+6) = 0x0000;\n}\n\n# evlhhossplat RT,D(RA)\n# ISA-cmt: Vector Load Halfword into Halfword Odd Signed and Splat\n# evlhhossplat rD,rA 011 0000 1111\n:evlhhossplat RT,EVUIMM_2_RAt is OP=4 & RT & EVUIMM_2_RAt & XOP_0_10=0x30F { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*2);\n# RT.l = EXTS(MEM(EA, 2));\n# RT.h = EXTS(MEM(EA, 2));\n\n EA:$(REGISTER_SIZE) = EVUIMM_2_RAt;\n *:4 (RT) = sext( *:2 (((EA) & $(MEMMASK))));\n *:4 (RT+4) = sext( *:2 (((EA) & $(MEMMASK))));\n}\n\n# evlhhossplatx RT,RA,RB\n# ISA-cmt: Vector Load Halfword into Halfword Odd Signed and Splat Indexed\n# evlhhossplatx rD,rA,rB 011 0000 1110\n:evlhhossplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x30E { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.l = EXTS(MEM(EA, 2));\n# RT.h = EXTS(MEM(EA, 2));\n\n EA:$(REGISTER_SIZE) = A + B;\n *:4 (D) = sext( *:2 (((EA) & $(MEMMASK))));\n *:4 (D+4) = sext( *:2 (((EA) & $(MEMMASK))));\n}\n\n# evlhhousplat RT,D(RA)\n# ISA-cmt: Vector Load Halfword into Halfword Odd Unsigned and Splat\n# evlhhousplat rD,rA 011 0000 1101\n:evlhhousplat RT,EVUIMM_2_RAt is OP=4 & RT & EVUIMM_2_RAt & XOP_0_10=0x30D { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*2);\n# RT.l = EXTZ(MEM(EA, 2));\n# RT.h = EXTZ(MEM(EA, 2));\n\n EA:$(REGISTER_SIZE) = EVUIMM_2_RAt;\n *:4 (RT) = zext( *:2 (((EA) & $(MEMMASK))));\n *:4 (RT+4) = zext( *:2 (((EA) & $(MEMMASK))));\n}\n\n# evlhhousplatx RT,RA,RB\n# ISA-cmt: Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed\n# evlhhousplatx rD,rA,rB 011 0000 1100\n:evlhhousplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x30C { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.l = EXTZ(MEM(EA, 2));\n# RT.h = EXTZ(MEM(EA, 2));\n\n EA:$(REGISTER_SIZE) = A + B;\n *:4 (D) = zext( *:2 (((EA) & $(MEMMASK))));\n *:4 (D) = zext( *:2 (((EA) & $(MEMMASK))));\n}\n\n# evlwhe RT,D(RA)\n# ISA-cmt: Vector Load Word into Two Halfwords Even\n# evlwhe rD,rA 011 0001 0001\n# evlwhe confict with mullhwu.\n# define pcodeop VectorLoadWordIntoTwoHalfWordsEven;\n# :evlwhe D,A is OP=4 & A & EVUIMM_4 & D & XOP_0_10=0x311 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# RT.S0 = MEM(EA, 2);\n# RT.S1 = 0x0000;\n# RT.S2 = MEM(EA+2, 2);\n# RT.S3 = 0x0000;\n\n# VectorLoadWordIntoTwoHalfWordsEven(D,A); \n# }\n\n# =================================================================\n# Page D-12\n\n# evlwhex RT,RA,RB\n# ISA-cmt: Vector Load Word into Two Halfwords Even Indexed\n# evlwhex rD,rA 011 0001 0000\n# evlwhex confict with mullhwu\n# define pcodeop VectorLoadWordIntoTwoHalfWordsEvenIndexed;\n# :evlwhex D,A is OP=4 & B & A & D & XOP_0_10=0x310 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b+ RB;\n# RT.S0 = MEM(EA, 2);\n# RT.S1 = 0x0000;\n# RT.S2 = MEM(EA + 2, 2);\n# RT.S3 = 0x0000;\n\n# VectorLoadWordIntoTwoHalfWordsEvenIndexed(D,A); \n# }\n\n# evlwhos RT,D(RA)\n# ISA-cmt: Vector Load Word into Two Halfwords Odd Signed (with sign extension)\n# evlwhos rD,rA 011 0001 0111\n:evlwhos RT,EVUIMM_4_RAt is OP=4 & EVUIMM_4_RAt & RT & XOP_0_10=0x317 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# RT.l = EXTS(MEM(EA, 2));\n# RT.h = EXTS(MEM(EA+2, 2));\n\n EA:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:4 (RT) = sext( *:2 (((EA) & $(MEMMASK))));\n *:4 (RT+4) = sext( *:2 (((EA+2) & $(MEMMASK))));\n}\n\n# evlwhosx RT,RA,RB\n# ISA-cmt: Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension)\n# evlwhosx rD,rA,rB 011 0001 0110\n:evlwhosx D,A,B is OP=4 & A & B & D & XOP_0_10=0x316 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.l = EXTS(MEM(EA,2));\n# RT.h = EXTS(MEM(EA+2, 2));\n\n EA:$(REGISTER_SIZE) = A + B;\n *:4 (D) = sext( *:2 (((EA) & $(MEMMASK))));\n *:4 (D+4) = sext( *:2 (((EA+2) & $(MEMMASK))));\n}\n\n# evlwhou RT,D(RA)\n# ISA-cmt: Vector Load Word into Two Halfwords Odd Unsigned (zero-extended)\n# evlwhou rD,rA 011 0001 0101\n:evlwhou RT,EVUIMM_4_RAt is OP=4 & EVUIMM_4_RAt & RT & XOP_0_10=0x315 { \n# if (RA == 0) { \n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# RT.l = EXTZ(MEM(EA, 2));\n# RT.h = EXTZ(MEM(EA+2, 2));\n\n EA:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:4 (RT) = zext( *:2 (((EA) & $(MEMMASK))));\n *:4 (RT+4) = zext( *:2 (((EA+2) & $(MEMMASK))));\n}\n\n# evlwhoux RT,RA,RB\n# ISA-cmt: Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended)\n# evlwhoux rD,rA,rB 011 0001 0100\n:evlwhoux D,A,B is OP=4 & A & B & D & XOP_0_10=0x314 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.l = EXTZ(MEM(EA,2));\n# RT.h = EXTZ(MEM(EA+2,2));\n\n EA:$(REGISTER_SIZE) = A + B;\n *:4 (D) = zext( *:2 (((EA) & $(MEMMASK))));\n *:4 (D+4) = zext( *:2 (((EA+2) & $(MEMMASK))));\n}\n\n# evlwhsplat RT,D(RA)\n# ISA-cmt: Vector Load Word into Two Halfwords and Splat\n# evlwhsplat rD,rA 011 0001 1101\n:evlwhsplat RS,EVUIMM_4_RAt is OP=4 & XOP_0_10=0x31D & EVUIMM_4_RAt & RS { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# RT.S0 = MEM(EA,2);\n# RT.S1 = MEM(EA,2);\n# RT.S2 = MEM(EA+2,2);\n# RT.S3 = MEM(EA+2,2);\n\n EA:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:2 (RS) = *:2 ((EA) & $(MEMMASK));\n *:2 (RS+2) = *:2 ((EA) & $(MEMMASK));\n *:2 (RS+4) = *:2 ((EA+2) & $(MEMMASK));\n *:2 (RS+6) = *:2 ((EA+2) & $(MEMMASK));\n}\n\n# evlwhsplatx RT,RA,RB\n# ISA-cmt: Vector Load Word into Two Halfwords and Splat Indexed\n# evlwhsplatx rD,rA,rB 011 0001 1100\n:evlwhsplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x31C { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.S0 = MEM(EA,2);\n# RT.S1 = MEM(EA,2);\n# RT.S2 = MEM(EA+2,2);\n# RT.S3 = MEM(EA+2,2);\n\n EA:$(REGISTER_SIZE) = A + B;\n *:2 (D) = *:2 ((EA) & $(MEMMASK));\n *:2 (D+2) = *:2 ((EA) & $(MEMMASK));\n *:2 (D+4) = *:2 ((EA+2) & $(MEMMASK));\n *:2 (D+6) = *:2 ((EA+2) & $(MEMMASK));\n}\n\n# evlwwsplat RT,D(RA)\n# ISA-cmt: Vector Load Word into Word and Splat\n# evlwwsplat rD,rA 011 0001 1001\n# define pcodeop VectorLoadWordIntoWordAndSplat;\n# evlwwsplat conficts with maclhwu.\n# :evlwwsplat RT,EVUIMM_4_RAt is OP=4 & A & D & EVUIMM_4_RAt & RT & XOP_0_10=0x319 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# RT.l = MEM(EA,4);\n# RT.h = MEM(EA,4);\n\n# VectorLoadWordIntoWordAndSplat(D,A); \n# }\n\n# evlwwsplatx RT,RA,RB\n# ISA-cmt: Vector Load Word into Word and Splat Indexed\n# evlwwsplatx rD,rA,rB 011 0001 1000\n# define pcodeop VectorLoadWordIntoWordAndSplatIndexed;\n# evlwwsplatx conficts with maclhwu\n# :evlwwsplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x318 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# RT.l = MEM(EA,4);\n# RT.h = MEM(EA,4);\n\n# VectorLoadWordIntoWordAndSplatIndexed(D,A,B); \n# }\n\n# evmergehi RT,RA,RB\n# ISA-cmt: Vector Merge High\n# evmergehi rD,rA,rB 010 0010 1100\n@if REGISTER_SIZE==\"8\"\n:evmergehi S,A,B is OP=4 & S & A & B & XOP_0_10=556\n{\n\tS[32,32] = A[32,32];\n\tS[ 0,32] = B[32,32];\n}\n\n# evmergehilo RT,RA,RB\n# ISA-cmt: Vector Merge High/Low\n# evmergehilo rD,rA,rB 010 0010 1110\n:evmergehilo S,A,B is OP=4 & S & A & B & XOP_0_10=558 {\n\tS[32,32] = A[32,32];\n\tS[ 0,32] = B[ 0,32];\n}\n\n# evmergelo RT,RA,RB\n# ISA-cmt: Vector Merge Low\n# evmergelo rD,rA,rB 010 0010 1101\n:evmergelo S,A,B is OP=4 & S & A & B & XOP_0_10=557\n{\n\tS[32,32] = A[0,32];\n\tS[ 0,32] = B[0,32];\n}\n\n# evmergelohi RT,RA,RB\n# ISA-cmt: Vector Merge Low/High\n# evmergelohi rD,rA,rB 010 0010 1111\n:evmergelohi S,A,B is OP=4 & S & A & B & XOP_0_10=559 {\n \tS[32,32] = A[ 0,32];\n\tS[ 0,32] = B[32,32];\n}\n@endif\n\n# evmhegsmfaa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate\n# evmhegsmfaa rD,rA,rB 101 0010 1011\n:evmhegsmfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52B {\n# u64 temp;\n# temp = RA.S2 *gsf RB.S2;\n# RT = ACC + temp;\n# ACC = RT;\n\n D = ACC + GuardedSignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) );\n ACC = D;\n}\n\n# evmhegsmfan RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative\n# evmhegsmfan rD,rA,rB 101 1010 1011\n:evmhegsmfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AB {\n# u64 temp;\n# temp = RA.S2 *gsf RB.S2;\n# RT = ACC - temp;\n# ACC = RT;\n\n D = ACC - GuardedSignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) );\n ACC = D;\n}\n\n# evmhegsmiaa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate\n# evmhegsmiaa rD,rA,rB 101 0010 1001\n:evmhegsmiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x529 {\n# u64 temp;\n# temp.l = RA.l2 *si RB.l2;\n# temp.h = EXTS(temp.l);\n# RT = ACC + temp;\n# ACC = RT;\n\n lo:8 = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32);\n hi:8 = sext(lo:2);\n lo = (( zext(hi) << 32) | zext(lo) );\n D = ACC + lo;\n ACC = D;\n}\n\n\n# evmhegsmian RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative\n# evmhegsmian rD,rA,rB 101 1010 1001\n:evmhegsmian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5A9 {\n# u64 temp;\n# temp.l = RA.S2 *si RB.S2;\n# temp = EXTS(temp.l);\n# RT = ACC - temp;\n# ACC = RT;\n\n lo:8 = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32);\n hi:8 = sext(lo:2);\n lo = (( zext(hi) << 32) | zext(lo) );\n D = ACC - lo;\n ACC = D;\n}\n\n# evmhegumiaa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate\n# evmhegumiaa rD,rA,rB 101 0010 1000\n:evmhegumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x528 {\n# u64 temp;\n# temp.l = RA.S2 *ui RB.S2;\n# temp = EXTZ(temp.l);\n# RT = ACC + temp;\n# ACC = RT;\n\n temp:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32);\n temp = zext(temp:4);\n D = ACC + temp;\n ACC = D;\n}\n\n# evmhegumian RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative\n# evmhegumian rD,rA,rB 101 1010 1000\n:evmhegumian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5A8 {\n# u64 temp;\n# temp.l = RA.S2 *ui RB.S2;\n# temp = EXTZ(temp);\n# RT = ACC - temp;\n# ACC = RT;\n\n temp:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32);\n temp = zext(temp:4);\n D = ACC - temp;\n ACC = D;\n}\n\n# evmhesmf RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional\n# evmhesmf rD,rA,rB 100 0000 1011\n:evmhesmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x40B {\n# RT = RA.S0 *sf RB.S0;\n# RT.S2 = RA.S2 *sf RB.S2;\n\n D = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) );\n D = (D & 0xFFFF) | ( (SignedFractionalMultiplication((( A & (0x0000FFFFFFFF0000) ) >> 16),(( B & (0x0000FFFFFFFF0000) ) >> 16)) ) << 16);\n}\n\n# evmhesmfa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator\n# evmhesmfa rD,rA,rB 100 0010 1011\n:evmhesmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x42B {\n# RT.l = RA.S0 *sf RB.S0;\n# RT.h = RA.S2 *sf RB.S2;\n# ACC = RT;\n\n D = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) );\n D = (D & 0xFFFF) | ( (SignedFractionalMultiplication((( A & (0x0000FFFFFFFF0000) ) >> 16),(( B & (0x0000FFFFFFFF0000) ) >> 16)) ) << 16);\n ACC = D;\n}\n\n# evmhesmfaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words\n# evmhesmfaaw rD,rA,rB 101 0000 1011\n:evmhesmfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50B {\n# u64 temp;\n# temp = RA.S0 *sf RB.S0;\n# RT.l = ACC.l + temp.l;\n# temp.l = RA.S2 *sf RB.S2;\n# RT = ACC.h + temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) );\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) );\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhesmfanw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words\n# evmhesmfanw rD,rA,rB 101 1000 1011\n:evmhesmfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58B {\n# u64 temp;\n# temp.l = RA.S0 *sf RB.S0;\n# RT.l = ACC.l - temp.l;\n# temp.l = RA.S2 *sf RB.S2;\n# RT.h = ACC.h - temp;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) );\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) );\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhesmi RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer\n# evmhesmi rD,rA,rB 100 0000 1001\n:evmhesmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x409 {\n# RT.l = RA.S0 *si RB.S0;\n# RT.h = RA.S2 *si RB.S2;\n\n lo:$(REGISTER_SIZE) = (( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) );\n hi:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmhesmia RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator\n# evmhesmia rD,rA,rB 100 0010 1001\n:evmhesmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x429 {\n# RT.l = RA.S0 *si RB.S0;\n# RT.h = RA.S2 *si RB.s2;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) );\n hi:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhesmiaaw rD,rA,rB 101 0000 1001\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words\n:evmhesmiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x509 {\n# u64 temp;\n# temp.l = RA.S0 *si RB.S0;\n# RT.l = ACC.l + temp.l;\n# temp.l = RA.S2 *si RB.S2;\n# RT.h = ACC.h + temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) + ((( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) ));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhesmianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words\n# evmhesmianw rD,rA,rB 101 1000 1001\n:evmhesmianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x589 {\n# u64 temp;\n# temp.l = RA.S0 *si RB.S0;\n# RT.l = ACC.l - temp.l;\n# temp.l = RA.S2 *si RB.S2;\n# RT.S2 = ACC.S2 - temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) - ((( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) ));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhessf RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional\n# evmhessf rD,rA,rB 100 0000 0011\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractional1;\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractional2;\n:evmhessf D,A,B is OP=4 & A & B & D & XOP_0_10=0x403 {\n # TODO definition complicated\n# SPEFSCR.OVH = movh;\n# SPEFSCR.OV = movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | movl;\n\n D = VectorMultiplyHalfWordsEvenSignedSaturateFractional1(A,B);\n flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractional2(A,B);\n \n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000)); \n}\n\n# evmhessfa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator\n# evmhessfa rD,rA,rB 100 0010 0011\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate1;\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate2;\n:evmhessfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x423 {\n# SPEFSCR.OVH = movh;\n# SPEFSCR.OV = movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | movl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate1(A,B);\n ACC = D;\n flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate2(A,B);\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhessfaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words\n# evmhessfaaw rD,rA,rB 101 0000 0011\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords2;\n:evmhessfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x503 {\n# SPEFSCR.OVH = ovh | movh\n# SPEFSCR.OV = ovl| movl\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl\n # TODO definition complicated\n D = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhessfanw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words\n# evmhessfanw rD,rA,rB 101 1000 0011\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords2;\n:evmhessfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x583 {\n# SPEFSCR.OVH = ovh | movh;\n# SPEFSCR.OV = ovl| movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhessiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words\n# evmhessiaaw rD,rA,rB 101 0000 0001\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords2;\n:evmhessiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x501 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhessianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words\n# evmhessianw rD,rA,rB 101 1000 0001\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords2;\n:evmhessianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x581 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n# TODO definition complicated\n D = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords2(A,B,ACC,spr200);\n ACC = D;\n \n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# =================================================================\n# Page D-13\n\n# evmheumi RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer\n# evmheumi rD,rA,rB 100 0000 1000\n:evmheumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x408 {\n# RT.l = RA.S0 *ui RB.S0;\n# RT.h = RA.S2 *ui RB.S2;\n\n lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmheumia RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator\n# evmheumia rD,rA,rB 100 0010 1000\n:evmheumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x428 {\n# RT.l = RA.S0 *ui RB.S0;\n# RT.h = RA.S2 *ui RB.S2;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmheumiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words\n# evmheumiaaw rD,rA,rB 101 0000 1000\n:evmheumiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x508 {\n# u64 temp;\n# temp.l = RA.S0 *ui RB.S0;\n# RT.l = ACC.l + temp.l;\n# temp.l = RA.S2 *ui RB.S2;\n# RT.h = ACC.h + temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmheumianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words\n# evmheumianw rD,rA,rB 101 1000 1000\n:evmheumianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x588 {\n# u64 temp;\n# temp.l = RA.S0 *ui RB.S0;\n# RT.l = ACC.l - temp.l;\n# temp.l = RA.S2 *ui RB.S2;\n# RT.h = ACC.h - temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmheusiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words\n# evmheusiaaw rD,rA,rB 101 0000 0000\ndefine pcodeop VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords2;\n:evmheusiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x500 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmheusianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words\n# evmheusianw rD,rA,rB 101 1000 0000\ndefine pcodeop evmheusianwOP1;\ndefine pcodeop evmheusianwOP2;\n:evmheusianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x580 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = evmheusianwOP1(A,B,ACC,spr200);\n flags:8 = evmheusianwOP2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhogsmfaa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate\n# evmhogsmfaa rD,rA,rB 101 0010 1111\n:evmhogsmfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52F {\n# u64 temp;\n# temp = RA.S3 *gsf RB.S3;\n# RT = ACC + temp;\n# ACC = RT;\n\n D = ACC + GuardedSignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) );\n ACC = D;\n}\n\n# evmhogsmfan RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative\n# evmhogsmfan rD,rA,rB 101 1010 1111\n:evmhogsmfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AF {\n# u64 temp;\n# temp = RA.S3 *gsf RB.S3;\n# RT = ACC - temp;\n# ACC = RT;\n\n D = ACC - GuardedSignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) );\n ACC = D;\n}\n\n# evmhogsmiaa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate\n# evmhogsmiaa rD,rA,rB 101 0010 1101\n:evmhogsmiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52D {\n# u64 temp;\n# temp.l = RA.S3 *si RB.S3;\n# temp = EXTS(temp.l);\n# RT = ACC + temp;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48);\n lo = sext(lo:2);\n D = ACC + lo;\n ACC = D;\n}\n\n# evmhogsmian RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative\n# evmhogsmian rD,rA,rB 101 1010 1101\n:evmhogsmian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AD {\n# u64 temp;\n# temp.l = RA.S3 *si RB.S3;\n# temp = EXTS(temp);\n# RT = ACC - temp;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48);\n lo = sext(lo:2);\n D = ACC - lo;\n ACC = D;\n}\n\n# evmhogumiaa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate\n# evmhogumiaa rD,rA,rB 101 0010 1100\n:evmhogumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52C {\n# u64 temp;\n# tempo.l = RA.S3 *ui RB.S3;\n# temp = EXTZ(temp.l);\n# RT = ACC + temp;\n# ACC = RT;\n\n temp:8 = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16);\n temp = zext( (( temp & (0x0000000000000000) ) >> 32) );\n D = ACC + temp;\n ACC = D;\n}\n\n# evmhogumian RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative\n# evmhogumian rD,rA,rB 101 1010 1100\n:evmhogumian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AC {\n# u64 temp;\n# temp.l = RA.S3 *ui RB.S3;\n# temp = EXTZ(temp.l);\n# RT = ACC - temp;\n# ACC = RT;\n\n temp:8 = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16);\n temp = zext( (( temp & (0x0000000000000000) ) >> 32) );\n D = ACC - temp;\n ACC = D;\n}\n\n# evmhosmf RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional\n# evmhosmf rD,rA,rB 100 0000 1111\n:evmhosmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x40F {\n# RT.l = RA.S1 *sf RB.S1;\n# RT.h = RA.S3 *sf RB.S3;\n\n lo:8 = SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) );\n hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) );\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmhosmfa RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator\n# evmhosmfa rD,rA,rB 100 0010 1111\n:evmhosmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x42F {\n# RT.l = RA.S1 *sf RB.S1;\n# RT.h = RA.S3 *sf RB.S3;\n# ACC = RT;\n\n lo:8 = SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) );\n hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) );\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhosmfaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words\n# evmhosmfaaw rD,rA,rB 101 0000 1111\n:evmhosmfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50F {\n# u64 temp;\n# temp.l = RA.S1 *sf RB.S1;\n# RT.l = ACC.l + temp.l;\n# temp.l = RA.S3 *sf RB.S3;\n# RT.h = ACC.h + temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) );\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) );\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhosmfanw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words\n# evmhosmfanw rD,rA,rB 101 1000 1111\n:evmhosmfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58F {\n# u64 temp;\n# temp.l = RA.S1 *sf RB.S1;\n# RT.l = ACC.l - temp.l;\n# temp.l = RA.S3 *sf RB.S3;\n# RT.h = ACC.h - temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) );\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) );\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhosmi RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer\n# evmhosmi rD,rA,rB 100 0000 1101\n:evmhosmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x40D {\n# RT.l = RA.S1 *si RB.S1;\n# RT.h = RA.S3 *si RB.S3;\n \n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmhosmia RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator\n# evmhosmia rD,rA,rB 100 0010 1101\n:evmhosmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x42D {\n# RT.l = RA.S1 *si RB.S1;\n# RT.h = RA.S3 *si RB.S3;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhosmiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words\n# evmhosmiaaw rD,rA,rB 101 0000 1101\n:evmhosmiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50D {\n# u64 temp;\n# temp.l = RA.S1 *si RB.S1;\n# RT.l = ACC.l + temp.l;\n# temp.l = RA.S3 *si RB.S3;\n# RT.h = ACC.h + temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) + ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48));\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmhosmianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words\n# evmhosmianw rD,rA,rB 101 1000 1101\n:evmhosmianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58D {\n# u64 temp;\n# temp.l = RA.S1 *si RB.S1;\n# RT.l = ACC.l - temp.l;\n# temp.l = RA.S3 *si RB.SI;\n# RT.h = ACC.h - temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) - ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48));\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmhossf RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional\n# evmhossf rD,rA,rB 100 0000 0111\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator1;\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2;\n:evmhossf D,A,B is OP=4 & A & B & D & XOP_0_10=0x407 {\n# SPEFSCR.OVH = movh;\n# SPEFSCR.OV = movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | movl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator1(A,B);\n flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2(A,B);\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhossfa rD,rA,rB 100 0010 0111\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2a;\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2b;\n:evmhossfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x427 {\n# SPEFSCR.OVH = movh;\n# SPEFSCR.OV = movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | movl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2a(A,B);\n flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2b(A,B);\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhossfaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words\n# evmhossfaaw rD,rA,rB 101 0000 0111\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords2;\n:evmhossfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x507 {\n# SPEFSCR.OVH = ovh | movh;\n# SPEFSCR.OV = ovl| movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhossfanw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words\n# evmhossfanw rD,rA,rB 101 1000 0111\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords2;\n:evmhossfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x587 {\n# SPEFSCR.OVH = ovh | movh;\n# SPEFSCR.OV = ovl| movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhossiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words\n# evmhossiaaw rD,rA,rB 101 0000 0101\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords2;\n:evmhossiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x505 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200);\n ACC = D;\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhossianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words\n# evmhossianw rD,rA,rB 101 1000 0101\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords2;\n:evmhossianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x585 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords1(A,B,ACC,spr200);\n ACC = D;\n flags:8 = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords2(A,B,ACC,spr200); \n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhoumi RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer\n# evmhoumi rD,rA,rB 100 0000 1100\n:evmhoumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x40C {\n# RT.l = RA.S1 *ui RB.S1;\n# RT.h = RA.S3 *ui RB.S3;\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmhoumia RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator\n# evmhoumia rD,rA,rB 100 0010 1100\n:evmhoumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x42C {\n# RT.l = RA.S1 *ui RB.S1;\n# RT.h = RA.S3 *ui RB.S3;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhoumiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words\n# evmhoumiaaw rD,rA,rB 101 0000 1100\n:evmhoumiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50C {\n# u64 temp;\n# temp = RA.S1 *ui RB.S1;\n# RT.l = ACC.l + temp.l;\n# temp.l = RA.S3 *ui RB.S3;\n# RT.h = ACC.h + temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhoumianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words\n# evmhoumianw rD,rA,rB 101 1000 1100\n:evmhoumianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58C {\n# u64 temp;\n# temp = RA.S1 *ui RB.S1;\n# RT.l = ACC.l - temp.l;\n# temp.l = RA.S3 *ui RB.S3;\n# RT.h = ACC.h - temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmhousiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words\n# evmhousiaaw rD,rA,rB 101 0000 0100\ndefine pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords2;\n:evmhousiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x504 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200);\n ACC = D;\n flags:8 = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200);\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmhousianw RT,RA,RB\n# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words\n# evmhousianw rD,rA,rB 101 1000 0100\ndefine pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords1;\ndefine pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords2;\n:evmhousianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x584 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords1(A,B,ACC,spr200);\n ACC = D;\n flags:8 = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords2(A,B,ACC,spr200);\n\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# =================================================================\n# Page D-14\n\n# evmra RT,RA\n# ISA-cmt: Initialize Accumulator\n# evmra rD,rA 100 1100 0100\n:evmra RT,RA is OP=4 & RT & RA & BITS_11_15=0 & XOP_0_10=1220\n{\n\tACC = zext(RA);\n\tRT = RA;\n}\n\n# evmwhsmf RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Signed, Modulo, Fractional\n# evmwhsmf rD,rA,rB 100 0100 1111\n:evmwhsmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x44F {\n# u64 temp;\n# temp = RA.l *sf RB.l;\n# RT.l = temp.l;\n# temp = RA.h *sf RB.h;\n# RT.h = temp.l;\n\n lo:8 = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 32) , (( B & (0x0000000000000000) ) >> 32) );\n hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) );\n D = (( zext(hi) << 32) | zext(lo) );\n} \n\n# evmwhsmfa RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Signed, Modulo, Fractional to Accumulator\n# evmwhsmfa rD,rA,rB 100 0110 1111\n:evmwhsmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x46F {\n# u64 temp;\n# temp = RA.l *sf RB.l;\n# RT.l = temp.l;\n# temp = RA.h *sf RB.h;\n# RT.h = temp.l;\n# ACC = RT;\n\n lo:8 = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 32) , (( B & (0x0000000000000000) ) >> 32) );\n hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) );\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmwhsmi RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Signed, Modulo, Integer\n# evmwhsmi rD,rA,rB 100 0100 1101\n:evmwhsmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x44D {\n# u64 temp;\n# temp = RA.l *si RB.l;\n# RT.l = temp.l;\n# temp = RA.h *si RB.h;\n# RT.h = temp.l;\n\n lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) * (( B & (0x00000000FFFFFFFF) ) )) & 0xFFFFFFFF;\n hi:$(REGISTER_SIZE) = ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32)) & 0xFFFFFFFF;\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmwhsmia RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Signed, Modulo, Integer to Accumulator\n# evmwhsmia rD,rA,rB 100 0110 1101\n:evmwhsmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x46D {\n# u64 temp;\n# temp = RA.l *si RB.l;\n# RT.l = temp.l;\n# temp = RA.h *si RB.h;\n# RT.h = temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) * (( B & (0x00000000FFFFFFFF) ) )) & 0xFFFFFFFF;\n hi:$(REGISTER_SIZE) = ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32)) & 0xFFFFFFFF;\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmwhssf RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Signed, Saturate, Fractional\n# evmwhssf rD,rA,rB 100 0100 0111\ndefine pcodeop VectorMultiplyWordHighSignedSaturateFractional1;\ndefine pcodeop VectorMultiplyWordHighSignedSaturateFractional2;\n:evmwhssf D,A,B is OP=4 & A & B & D & XOP_0_10=0x447 {\n# SPEFSCR.OVH = movh;\n# SPEFSCR.OV = movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | movl;\n # TODO definition complicated\n D = VectorMultiplyWordHighSignedSaturateFractional1(A,B);\n flags:8 = VectorMultiplyWordHighSignedSaturateFractional2(A,B);\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwhssfa RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Signed, Saturate, Fractional to Accumulator\n# evmwhssfa rD,rA,rB 100 0110 0111\ndefine pcodeop VectorMultiplyWordHighSignedSaturateFractionalToAccumulator1;\ndefine pcodeop VectorMultiplyWordHighSignedSaturateFractionalToAccumulator2;\n:evmwhssfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x467 { \n# SPEFSCR.OVH = movh;\n# SPEFSCR.OV = movl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | movh;\n# SPEFSCR.SOV = SPEFSCR.SOV | movl;\n # TODO definition complicated\n D = VectorMultiplyWordHighSignedSaturateFractionalToAccumulator1(A,B); \n ACC = D;\n flags:8 = VectorMultiplyWordHighSignedSaturateFractionalToAccumulator2(A,B); \n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwhumi RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Unsigned, Modulo, Integer\n# evmwhumi rD,rA,rB 100 0100 1100\n:evmwhumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x44C {\n# u64 temp;\n# temp = RA.l *ui RB.l;\n# RT.l = temp.l;\n# temp = RA.h *ui RB.h;\n# RT.h = temp.l;\n\n lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32);\n lo = zext(lo:4);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32);\n hi = zext(hi:4);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmwhumia RT,RA,RB\n# ISA-cmt: Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator\n# evmwhumia rD,rA,rB 100 0110 1100\n:evmwhumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x46C {\n# u64 temp;\n# temp = RA.l *ui RB.l;\n# RT.l = temp.l;\n# temp = RA.h *ui RB.h;\n# RT.h = temp.l;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32);\n lo = zext(lo:4);\n hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32);\n hi = zext(hi:4);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmwlsmi rD,rA,rB\n# ISA-cmt: Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words\n# define VectorMultiplyWordLowUnsigned,ModuloInteger;\n# YYY No definition in manual\n\n# evmwhusiaaw rD,rA,rB 101 0100 0100\n# TODO Not in PowerISA Version 2.06 manual?\ndefine pcodeop evmwhusiaawOP;\n:evmwhusiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x544 { evmwhusiaawOP(D,A,B); }\n\n# evmwhusianw rD,rA,rB 101 1100 0100\n# TODO Not in PowerISA Version 2.06 manual?\ndefine pcodeop evmwhusianwOP;\n:evmwhusianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x5C4 {\n evmwhusianwOP(D,A,B,ACC);\n}\n\n# evmwlsmiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words\n# evmwlsmiaaw ??\n# u64 temp;\n# temp = RA.l *si RB.l;\n# RT.l = ACC.l + temp.h;\n# temp = RA.h *si RB.h;\n# RT.h = ACC.h + temp.h;\n# ACC = RT;\n\n# evmwlsmianw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words\n# evmwlsmianw ??\n# u64 temp;\n# temp = RA.l *si RB.l;\n# RT.l = ACC.l - temp.h;\n# temp = RA.h *si RB.h;\n# RT.h = ACC.h - temp.h;\n# ACC = RT;\n\n# evmwlssiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Signed, aturate, Integer and Accumulate into Words\n# evmwlssiaaw rD,rA,rB 101 0100 0001\ndefine pcodeop VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords1;\ndefine pcodeop VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords2;\n:evmwlssiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x541 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords1(A,B,ACC,spr200);\n ACC = D;\n flags:8 = VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords2(A,B,ACC,spr200); \n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwlumi RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer\n# evmwlumi rD,rA,rB 100 0100 1000\n:evmwlumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x448 {\n# u64 temp;\n# temp = RA.l *ui RB.l;\n# RT.l = temp.h;\n# temp = RA.h *ui RB.h;\n# RT.h = temp.h;\n\n lo:8 = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32);\n lo = (( lo & (0xFFFFFFFF00000000) ) >> 32);\n hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32);\n lo = (( hi & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evmwlumia RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator\n# evmwlumia rD,rA,rB 100 0110 1000\n:evmwlumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x468 {\n# u64 temp;\n# temp = RA.l *ui RB.l;\n# RT.l = temp.h;\n# temp = RA.h *ui RB.h;\n# RT.h = temp.h;\n# ACC = RT;\n\n lo:8 = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32);\n lo = (( lo & (0xFFFFFFFF00000000) ) >> 32);\n hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32);\n lo = (( hi & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmwlumiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words\n# evmwlumiaaw rD,rA,rB 101 0100 1000\n:evmwlumiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x548 {\n# u64 temp;\n# temp = RA.l *ui RB.l;\n# RT.l = ACC.l + temp.h;\n# temp = RA.h *ui RB.h;\n# RT.h = ACC.h + temp.h;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + ((( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmwlumianw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words\n# evmwlumianw rD,rA,rB 101 1100 1000\n:evmwlumianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x5C8 {\n# u64 temp;\n# temp = RA.l *ui RB.l;\n# RT.l = ACC.l - temp.h;\n# temp = RA.h *ui RB.h;\n# RT.h = ACC.h - temp.h;\n# ACC = RT;\n \n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - ((( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32));\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32));\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evmwlusiaaw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words\n# evmwlusiaaw rD,rA,rB 101 0100 0000\ndefine pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords1;\ndefine pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords2;\n:evmwlusiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x540 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords1(A,B,ACC,spr200);\n ACC = D;\n flags:8 = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords2(A,B,ACC,spr200);\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwlusianw RT,RA,RB\n# ISA-cmt: Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words\n# evmwlusianw rD,rA,rB 101 1100 0000\ndefine pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords1;\ndefine pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords2;\n:evmwlusianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x5C0 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords1(D,A,B,ACC,spr200);\n ACC = D;\n flags:8 = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords2(D,A,B,ACC,spr200);\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwsmf RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional\n# evmwsmf rD,rA,rB 100 0101 1011\n:evmwsmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x45B {\n# RT = RA.h *sf RB.h;\n\n D = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) );\n}\n\n# evmwsmfa RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional to Accumulator\n# evmwsmfa rD,rA,rB 100 0111 1011\n:evmwsmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x47B {\n# RT = RA.h *sf RB.h;\n# ACC = RT;\n\n D = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) );\n ACC = D;\n}\n\n# evmwsmfaa RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional and Accumulate\n# evmwsmfaa rD,rA,rB 101 0101 1011 101 0101 1011\n:evmwsmfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x55B {\n# u64 temp;\n# temp = RA.h *sf RB.h;\n# RT = ACC + temp;\n# ACC = RT;\n\n D = ACC + ( SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ) );\n ACC = D;\n}\n\n# evmwsmfan RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative\n# evmwsmfan rD,rA,rB 101 1101 1011\n:evmwsmfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5DB {\n# u64 temp;\n# temp = RA.h *sf RB.h;\n# RT = ACC - temp;\n# ACC = RT;\n\n D = ACC - ( SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ) );\n ACC = D;\n}\n\n# evmwsmi RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer\n# evmwsmi rD,rA,rB 100 0101 1001\n# evmwsmi confict with machhwo.\n# :evmwsmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x459 {\n# RT = RA.h *si RB.h;\n\n# }\n\n# evmwsmia RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer to Accumulator\n# evmwsmia rD,rA,rB 100 0111 1001\n:evmwsmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x479 {\n# RT = RA.h *si RB.h;\n# ACC = RT;\n\n D = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32);\n ACC = D;\n}\n\n# evmwsmiaa RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer and Accumulate\n# evmwsmiaa rD,rA,rB 101 0101 1001\n# YYY duplicate???\n# define pcodeop VectorMultiplyWordSignedModuloIntegerAndAccumulate2;\n# u64 temp;\n# temp = RA.h *si RB.h;\n# RT = ACC + temp;\n# ACC = RT;\n\n# :evmwsmiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x559 {\n# u64 temp;\n# temp = RA.h *si RB.h;\n# RT = ACC + temp;\n# ACC = RT;\n#}\n\n# evmwsmian RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative\n# evmwsmian rD,rA,rB 101 1101 1001\n# evmwsmian confict with macchwso.\n# ppc_instructions.sinc :macchwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1\n# define pcodeop VectorMultiplyWordSignedModuloIntegerAndAccumulateNegative;\n# :evmwsmian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5D9 {\n# u64 temp;\n# temp = RA.h *si RB.h;\n# RT = ACC - temp;\n# ACC = RT;\n# }\n\n# evmwssf RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional\n# evmwssf rD,rA,rB 100 0101 0011\ndefine pcodeop VectorMultiplyWordSignedSaturateFractional1;\ndefine pcodeop VectorMultiplyWordSignedSaturateFractional2;\n:evmwssf D,A,B is OP=4 & A & B & D & XOP_0_10=0x453 {\n# SPEFSCR.OVH = 0;\n# SPEFSCR.OV = mov;\n# SPEFSCR.SOV = SPEFSCR.SOV | mov;\n # TODO definition \n D = VectorMultiplyWordSignedSaturateFractional1(D,A,B,ACC);\n ACC = D;\n flags:8 = VectorMultiplyWordSignedSaturateFractional2(D,A,B,ACC); \n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwssfa RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional to Accumulator\n# evmwssfa rD,rA,rB 100 0111 0011\ndefine pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate1a;\ndefine pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate1b;\n:evmwssfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x473 {\n# SPEFSCR.OVH = 0;\n# SPEFSCR.OV = mov;\n# SPEFSCR.SOV = SPEFSCR.SOV | mov;\n # TODO definition \n D = VectorMultiplyWordSignedSaturateFractionalAndAccumulate1a(D,A,B,ACC);\n ACC = D;\n flags:8 = VectorMultiplyWordSignedSaturateFractionalAndAccumulate1b(D,A,B,ACC); \n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwssfaa RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional and Accumulate\n# evmwssfaa rD,rA,rB 101 0101 0011\ndefine pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate2a;\ndefine pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate2b;\n:evmwssfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x553 {\n# SPEFSCR.OVH = 0;\n# SPEFSCR.OV = ov | mov;\n# SPEFSCR.SOV = SPEFSCR.SOV | ov | mov;\n # TODO definition \n D = VectorMultiplyWordSignedSaturateFractionalAndAccumulate2a(A,B,ACC);\n flags:8 = VectorMultiplyWordSignedSaturateFractionalAndAccumulate2b(A,B,ACC);\n ACC = D;\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evmwssfan RT,RA,RB\n# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative\n# evmwssfan rD,rA,rB 101 1101 0011\ndefine pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative1;\ndefine pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative2;\n:evmwssfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5D3 {\n# SPEFSCR.OVH = 0;\n# SPEFSCR.OV = ov | mov;\n# SPEFSCR.SOV = SPEFSCR.SOV | ov | mov;\n # TODO definition \n D = VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative1(A,B,ACC,spr200);\n flags:8 = VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative2(A,B,ACC,spr200);\n ACC = D;\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# =================================================================\n# Page D-15\n\n# evnand RT,RA,RB\n# ISA-cmt: Vector NAND\n# evnand rD,rA,rB 010 0001 1110\n:evnand D,A,B is OP=4 & A & B & D & XOP_0_10=0x21E { \n# RT.l = ONESCOMP(RA.l & RB.l);\n# RT.h = ONESCOMP(RA.h & RB.h);\n\n lo:$(REGISTER_SIZE) = ~ ( (( A & (0x00000000FFFFFFFF) ) ) & (( B & (0x00000000FFFFFFFF) ) ) );\n hi:$(REGISTER_SIZE) = ~ ( (( A & (0xFFFFFFFF00000000) ) >> 32) & (( B & (0xFFFFFFFF00000000) ) >> 32) );\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evneg RT,RA\n# ISA-cmt: Vector Negate\n# evneg rD,rA 010 0000 1001\n:evneg D,A is OP=4 & A & D & XOP_0_10=0x209 & BITS_11_15=0 { \n# RT.l = NEG(RA.l);\n# RT.h = NEG(RA.h);\n\n lo:$(REGISTER_SIZE) = - (( A & (0x00000000FFFFFFFF) ) );\n hi:$(REGISTER_SIZE) = - (( A & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evnor RT,RA,RB\n# ISA-cmt: Vector NOR\n# evnor rD,rA,rB 010 0001 1000\n:evnor D,A,B is OP=4 & A & B & D & XOP_0_10=0x218 { \n# RT.l = ONESCOMP(RA.l | RB.l);\n# RT.h = ONESCOMP(RA.h | RB.h);\n\n lo:$(REGISTER_SIZE) = ~ ( (( A & (0x00000000FFFFFFFF) ) ) | (( B & (0x00000000FFFFFFFF) ) ) );\n hi:$(REGISTER_SIZE) = ~ ( (( A & (0xFFFFFFFF00000000) ) >> 32) | (( B & (0xFFFFFFFF00000000) ) >> 32) );\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evnot => evnor\n\n# evor RT,RA,RB\n# ISA-cmt: Vector OR\n# evor rD,rA,rB 010 0001 0111\n:evor D,A,B is OP=4 & A & B & D & XOP_0_10=0x217 { \n# RT.l = RA.l | RB.l;\n# RT.h = RA.h | RB.h;\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFFFFFF) ) ) | (( B & (0x00000000FFFFFFFF) ) );\n hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) | (( B & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evorc RT,RA,RB\n# ISA-cmt: Vector OR with Complement\n# evorc rD,rA,rB 010 0001 1011\n:evorc D,A,B is OP=4 & A & B & D & XOP_0_10=0x21B { \n# RT.l = RA.l | ONESCOMP(RB.l);\n# RT.h = RA.h | ONESCOMP(RB.h);\n\n lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFFFFFF) ) ) | (~ (( B & (0x00000000FFFFFFFF) ) ));\n hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) | (~ (( B & (0xFFFFFFFF00000000) ) >> 32));\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\ndefine pcodeop ROTL64;\n\n# evrlw RT,RA,RB\n# ISA-cmt: Vector Rotate Left Word\n# evrlw rD,rA,rB 010 0010 1000\n:evrlw D,A,B is OP=4 & A & B & D & XOP_0_10=0x228 { \n# nh = RB.bsub(27:31);\n# nl = RB.bsub(59:63);\n# RT.l = ROTL(RA.l, nh);\n# RT.h = ROTL(RA.h, nl);\n\n nh:$(REGISTER_SIZE) = ((B & 0x00000000f8000000) >> 27);\n nl:$(REGISTER_SIZE) = ((B & 0xf800000000000000) >> 59);\n lo:8 = ROTL64( (( A & (0x00000000FFFFFFFF) ) ) ,nh);\n hi:8 = ROTL64( (( A & (0xFFFFFFFF00000000) ) >> 32) ,nl);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evrlwi RT,RA,UI\n# ISA-cmt: Vector Rotate Left Word Immediate\n# evrlwi rD,rA,EVUIMM 010 0010 1010\n:evrlwi D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x22A { \n# n = UI;\n# RT.l = ROTL(RA.l, n);\n# RT.h = ROTL(RA.h, n);\n\n n:8 = EVUIMM;\n lo:8 = ROTL64( (( A & (0x00000000FFFFFFFF) ) ) ,n);\n hi:8 = ROTL64( (( A & (0xFFFFFFFF00000000) ) >> 32) ,n);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evrndw RT,RA\n# ISA-cmt: Vector Round Word\n# evrndw rD,rA 010 0000 1100\n:evrndw D,A is OP=4 & A & D & UIMM & XOP_0_10=0x20C { \n# RT.l = (RA.l + 0x00008000) & 0xFFFF0000;\n# RT.h = (RA.h + 0x00008000) & 0xFFFF0000;\n\n lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) + 0x00008000) & 0xFFFF0000;\n hi:$(REGISTER_SIZE) = ((( A & (0x00FFFFFFFF00000000) ) >> 32) + 0x00008000) & 0xFFFF0000;\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# SPECIAL ** YYY\n# evsel RT,RA,RB,BFA\n# ISA-cmt: Vector Select\n# evsel rD,rA,rB,crS 0100 1111\n# define pcodeop VectorSelect;\n# :evsel D,A,B,crS is OP=4 & A & B & D & crS & XOP_3_10=0x4F { \n # TODO definition complicated\n# VectorSelect(D,A,B,crS); \n# }\n\n# evslw RT,RA,RB\n# ISA-cmt: Vector Shift Left Word\n# evslw rD,rA,rB 010 0010 0100\n:evslw D,A,B is OP=4 & A & B & D & XOP_0_10=0x224 { \n# nh = RB.bsub(26:31);\n# nl = RB.bsub(58:63);\n# RT.l = SL(RA.l,nh);\n# RT.h = SL(RA.h,nl);\n\n nh:$(REGISTER_SIZE) = ((B & 0x00000000fc000000) >> 26);\n nl:$(REGISTER_SIZE) = ((B & 0xfc00000000000000) >> 58);\n lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) << nh);\n hi:$(REGISTER_SIZE) = ((( A & (0xFFFFFFFF00000000) ) >> 32) << nl);\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# c RT,RA,UI\n# ISA-cmt: Vector Shift Left Word Immediate\n# evslwi rD,rA,EVUIMM 010 0010 0110\n:evslwi D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x226 { \n# n = UI;\n# RT.l = SL(RA.l, n);\n# RT.h = SL(RA.h, n);\n\n n:8 = EVUIMM;\n lo:8 = (( A & (0x00000000FFFFFFFF) ) ) << n;\n hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) << n;\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evsplatfi RT,SI\n# ISA-cmt: Vector Splat Fractional Immediate\n# evsplatfi rD,BU_SIMM 010 0010 1011\ndefine pcodeop VectorSplatFractionalImmediate;\n:evsplatfi D,BU_SIMM is OP=4 & D & BU_SIMM & XOP_0_10=0x22B { \n # TODO definition\n# RT0:31 = SI || 270\n# RT32:63 = SI || 270\n# The value specified by SI is padded with trailing zeros\n# and placed in both elements of RT. The SI ends up in\n# bit positions RT0:4 and RT32:36.\n\n D = VectorSplatFractionalImmediate(); \n}\n\n\n# BU_SIMMt: is BU_SIMM [ val = BU_SIMM; ] { tmp:8 = sext(BU_SIMM); export tmp; }\n\n# evsplati RT,SI\n# ISA-cmt: Vector Splat Immediate\n# evsplati rD,BU_SIMM 010 0010 1001\ndefine pcodeop VectorSplatImmediate;\n:evsplati D,BU_SIMM is OP=4 & D & BU_SIMM & XOP_0_10=0x229 { \n# RT.l = EXTS(SI);\n# RT.h = EXTS(SI);\n\n# lo:8 = BU_SIMMt; # sign or zext\n# hi:8 = BU_SIMM;\n# D = 64From2_32(hi,lo);\n \n D = VectorSplatImmediate();\n}\n\n# evsrwis RT,RA,UI\n# ISA-cmt: Vector Shift Right Word Immediate Signed\n# evsrwis rD,rA,EVUIMM 010 0010 0011\ndefine pcodeop VectorShiftRightWordImmediateSigned;\n:evsrwis D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x223 { \n # TODO definition\n# n = UI\n# RT0:31 = EXTS((RA)0:31-n)\n# RT32:63 = EXTS((RA)32:63-n)\n# Both high and low elements of RA are shifted right by\n# the 5-bit UI value. Bits in the most significant positions\n# vacated by the shift are filled with a copy of the sign bit.\n\n D = VectorShiftRightWordImmediateSigned(A); \n}\n\n# evsrwiu RT,RA,UI\n# ISA-cmt: Vector Shift Right Word Immediate Unsigned\n# evsrwiu rD,rA,EVUIMM 010 0010 0010\ndefine pcodeop VectorShiftRightWordImmediateUnsigned;\n:evsrwiu D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x222 { \n # TODO definition\n# n = UI\n# RT0:31 = EXTZ((RA)0:31-n)\n# RT32:63 = EXTZ((RA)32:63-n)\n# Both high and low elements of RA are shifted right by\n# the 5-bit UI value; zeros are shifted into the most significant\n# position.\n D = VectorShiftRightWordImmediateUnsigned(A); \n}\n\n@if REGISTER_SIZE==\"8\"\n:evsrws S,A,B is OP=4 & S & A & B & XOP_0_10=545\n{\n\tlocal low:4 = A[0,32];\n\tlocal high:4 = A[32,32];\n\tlocal low_shift:1 = B[0,5];\n\tlocal high_shift:1 = B[32,5];\n\tS[0,32] = low s>> zext(low_shift);\n\tS[32,32] = high s>> zext(high_shift);\n}\n\n:evsrwu S,A,B is OP=4 & S & A & B & XOP_0_10=544\n{\n\tlocal low:4 = A[0,32];\n\tlocal high:4 = A[32,32];\n\tlocal low_shift:1 = B[0,5];\n\tlocal high_shift:1 = B[32,5];\n\tS[0,32] = low >> zext(low_shift);\n\tS[32,32] = high >> zext(high_shift);\n}\n@endif\n\n\n# evstdd RS,D(RA)\n# ISA-cmt: Vector Store Double of Double\n# evstdd rD,rA,EVUIMM_8 011 0010 0001\n:evstdd RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=801 \n{\n ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;\n *:8 ($(EATRUNC)) = RS;\n}\n\n# evstddx RS,RA,RB\n# ISA-cmt: Vector Store Double of Double Indexed\n# evstddx rS,rA,rB 011 0010 0000\n:evstddx RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=800\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;\n *:8 ($(EATRUNC)) = RS;\n}\n\n\n# evstdh RS,D(RA)\n# ISA-cmt: Vector Store Double of Four Halfwords\n# evstdh rS,rA,EVUIMM_8 011 0010 0101\n:evstdh S,EVUIMM_8_RAt is OP=4 & S & EVUIMM_8_RAt & XOP_0_10=0x325 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*8);\n# MEM(EA,2) = RS.S0;\n# MEM(EA+2,2) = RS.S1;\n# MEM(EA+4,2) = RS.S2;\n# MEM(EA+6,2) = RS.S3;\n\n EA:$(REGISTER_SIZE) = EVUIMM_8_RAt;\n *:2 (EA) = *:2 ((S) & $(MEMMASK));\n *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK));\n *:2 (EA+4) = *:2 ((S+4) & $(MEMMASK));\n *:2 (EA+6) = *:2 ((S+4) & $(MEMMASK));\n}\n\n# evstdhx RS,RA,RB\n# ISA-cmt: Vector Store Double of Four Halfwords Indexed\n# evstdhx rS,rA,rB 011 0010 0100\n:evstdhx S,A,B is OP=4 & A & B & S & XOP_0_10=0x324 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# MEM(EA,2) = RS.S0;\n# MEM(EA+2,2) = RS.S1;\n# MEM(EA+4,2) = RS.S2;\n# MEM(EA+6,2) = RS.S3;\n\n EA:$(REGISTER_SIZE) = A + B;\n *:2 (EA) = *:2 ((S) & $(MEMMASK));\n *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK));\n *:2 (EA+4) = *:2 ((S+4) & $(MEMMASK));\n *:2 (EA+6) = *:2 ((S+6) & $(MEMMASK));\n}\n\n# evstdw RS,D(RA)\n# ISA-cmt: Vector Store Double of Two Words\n# evstdw rS,rA,EVUIMM_8 011 0010 0011\n:evstdw S,EVUIMM_8_RAt is OP=4 & S & EVUIMM_8_RAt & XOP_0_10=0x323 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*8);\n# MEM(EA,4) = RS.l;\n# MEM(EA+4,4) = RS.h;\n\n EA:$(REGISTER_SIZE) = EVUIMM_8_RAt;\n *:4 (EA) = *:4 ((S) & $(MEMMASK));\n *:4 (EA+4) = *:4 ((S+4) & $(MEMMASK));\n}\n\n# evstdwx RS,RA,RB\n# ISA-cmt: Vector Store Double of Two Words Indexed\n# evstdwx rS,rA,rB 011 0010 0010\n:evstdwx S,A,B is OP=4 & A & B & S & XOP_0_10=0x322 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# MEM(EA,4) = RS.l;\n# MEM(EA+4,4) = RS.h;\n\n EA:$(REGISTER_SIZE) = A + B;\n *:4 (EA) = *:4 ((S) & $(MEMMASK));\n *:4 (EA+4) = *:4 ((S+4) & $(MEMMASK));\n}\n\n# evstwhe RS,D(RA)\n# ISA-cmt: Vector Store Word of Two Halfwords from Even\n# evstwhe rS,rA,EVUIMM_4 011 0011 0001\n:evstwhe S,EVUIMM_4_RAt is OP=4 & S & EVUIMM_4_RAt & XOP_0_10=0x331 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# MEM(EA,2) = RS.S0;\n# MEM(EA+2,2) = RS.S2;\n\n EA:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:2 (EA) = *:2 ((S) & $(MEMMASK));\n *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK));\n}\n\n# evstwhex RS,RA,RB\n# ISA-cmt: Vector Store Word of Two Halfwords from Even Indexed\n# evstwhex rS,rA,rB 011 0011 0000\n:evstwhex S,A,B is OP=4 & A & B & S & XOP_0_10=0x330 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# MEM(EA,2) = RS.S0;\n# MEM(EA+2,2) = RS.S2;\n\n EA:$(REGISTER_SIZE) = A + B;\n *:2 (EA) = *:2 ((S) & $(MEMMASK));\n *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK));\n}\n\n# evstwho RS,D(RA)\n# ISA-cmt: Vector Store Word of Two Halfwords from Odd\n# evstwho rS,rA,EVUIMM_4 011 0011 0101\n:evstwho S,EVUIMM_4_RAt is OP=4 & S & EVUIMM_4_RAt & XOP_0_10=0x335 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# MEM(EA,2) = RS.S1;\n# MEM(EA+2,2) = RS.S3;\n\n EA:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:2 (EA) = *:2 ((S+2) & $(MEMMASK));\n *:2 (EA+2) = *:2 ((S+6) & $(MEMMASK));\n}\n\n# evstwhox RS,RA,RB\n# ISA-cmt: Vector Store Word of Two Halfwords from Odd Indexed\n# evstwhox rS,rA,rB 011 0011 0100\n:evstwhox S,RA_OR_ZERO,B is OP=4 & RA_OR_ZERO & B & S & XOP_0_10=0x334 { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# MEM(EA,2) = RS.S1;\n# MEM(EA+2,2) = RS.S3;\n \n EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n *:2 (EA) = *:2 ((S+2) & $(MEMMASK));\n *:2 (EA+2) = *:2 ((S+6) & $(MEMMASK));\n}\n\n# evstwwe RS,D(RA)\n# ISA-cmt: Vector Store Word of Word from Even\n# evstwwe rS,rA,UIMM 011 0011 1001\n:evstwwe S,EVUIMM_4_RAt is OP=4 & S & EVUIMM_4_RAt & UI & XOP_0_10=0x339\n{\n ea:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:4 ($(EATRUNC)) = S:4;\n}\n\n# evstwwex RS,RA,RB\n# ISA-cmt: Vector Store Word of Word from Even Indexed\n# evstwwex rS,rA,rB 011 0011 1000\n:evstwwex S,RA_OR_ZERO,RB is OP=4 & S & RA_OR_ZERO & RB & XOP_0_10=0x338\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;\n *:4 ($(EATRUNC)) = S:4;\n}\n\n# evstwwo RS,D(RA)\n# ISA-cmt: Vector Store Word of Word from Odd\n# evstwwo rS,rA,EVUIMM_4 011 0011 1101\n:evstwwo S,EVUIMM_4_RAt is OP=4 & S & EVUIMM_4_RAt & UI & XOP_0_10=0x33D { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + EXTZ(UI*4);\n# MEM(EA,4) = RS.h;\n\n EA:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n *:4 (EA) = *:4 ((S+4) & $(MEMMASK));\n}\n\n# evstwwox RS,RA,RB\n# ISA-cmt: Vector Store Word of Word from Odd Indexed\n# evstwwox rS,rA,rB 011 0011 1100\n:evstwwox S,A,B is OP=4 & A & B & S & XOP_0_10=0x33C { \n# if (RA == 0) {\n# b = 0;\n# } else {\n# b = RA;\n# }\n# EA = b + RB;\n# MEM(EA,4) = RS.h;\n\n EA:$(REGISTER_SIZE) = A + B;\n *:4 (EA) = *:4 ((S+4) & $(MEMMASK));\n}\n\n# evsubfsmiaaw RT,RA\n# ISA-cmt: Vector Subtract Signed, Modulo, Integer to Accumulator Word\n# evsubfsmiaaw rD,rA 100 0011 1011\n:evsubfsmiaaw D,A is OP=4 & A & D & XOP_0_10=0x4CB & BITS_11_15=0 {\n# RT.l = ACC.l - RA.l;\n# RT.h = ACC.h - RA.h;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) - (( A & (0x00000000FFFFFFFF) ) );\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# =================================================================\n# Page D-16\n\n# evsubfssiaaw RT,RA\n# ISA-cmt: Vector Subtract Signed, Saturate, Integer to Accumulator Word\n# evsubfssiaaw rD,rA 100 1100 0011\ndefine pcodeop VectorSubtractSignedSaturateIntegerToAccumulatorWord1;\ndefine pcodeop VectorSubtractSignedSaturateIntegerToAccumulatorWord2;\n:evsubfssiaaw D,A is OP=4 & A & D & XOP_0_10=0x4C3 & BITS_11_15=0 {\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n # TODO definition complicated\n D = VectorSubtractSignedSaturateIntegerToAccumulatorWord1(A,ACC);\n flags:8 = VectorSubtractSignedSaturateIntegerToAccumulatorWord2(A,ACC,spr200);\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evsubfumiaaw RT,RA\n# ISA-cmt: Vector Subtract Unsigned, Modulo, Integer to Accumulator Word\n# evsubfumiaaw rD,rA 100 1100 1010\n:evsubfumiaaw D,A is OP=4 & A & D & XOP_0_10=0x4CA & BITS_11_15=0 {\n# RT.l = ACC.l - RA.l;\n# RT.h = ACC.h - RA.h;\n# ACC = RT;\n\n lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - (( A & (0x0000000000000000) ) >> 32);\n hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evsubfusiaaw RT,RA\n# ISA-cmt: Vector Subtract Unsigned, Saturate, Integer to Accumulator Word\n# evsubfusiaaw rD,rA 100 1100 0010\ndefine pcodeop VectorSubtractUnsignedSaturateIntegerToAccumulatorWord1;\ndefine pcodeop VectorSubtractUnsignedSaturateIntegerToAccumulatorWord2;\n# SPEFSCR.OVH = ovh;\n# SPEFSCR.OV = ovl;\n# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh;\n# SPEFSCR.SOV = SPEFSCR.SOV | ovl;\n:evsubfusiaaw D,A is OP=4 & A & D & XOP_0_10=0x4C2 & BITS_11_15=0 {\n # TODO definition complicated\n VectorSubtractUnsignedSaturateIntegerToAccumulatorWord1(D,A,ACC,spr200);\n flags:8 = VectorSubtractUnsignedSaturateIntegerToAccumulatorWord2(D,A,ACC,spr200);\n spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000));\n spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000));\n spr200 = spr200 | (flags & (0x100000000));\n spr200 = spr200 | (flags & (0x1000000000000));\n}\n\n# evsubfw RT,RA,RB\n# ISA-cmt: Vector Subtract from Word\n# evsubfw rD,rA,rB 010 0000 0100\n:evsubfw D,A,B is OP=4 & A & B & D & XOP_0_10=0x204 { \n# RT.l = RB.l - RA.l;\n# RT.h = RB.h - RA.h;\n\n lo:$(REGISTER_SIZE) = (( B & (0x00000000FFFFFFFF) ) ) - (( A & (0x00000000FFFFFFFF) ) );\n hi:$(REGISTER_SIZE) = (( B & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0xFFFFFFFF00000000) ) >> 32);\n D = (( zext(hi) << 32) | zext(lo) );\n ACC = D;\n}\n\n# evsubifw RT,UI,RB\n# ISA-cmt: Vector Subtract Immediate from Word\n# evsubifw rD,UIMM,rB 010 0000 0110\n:evsubifw D,BITS_16_20,B is OP=4 & D & BITS_16_20 & B & XOP_0_10=0x206 { \n# RT.l = RB.l - EXTZ(UI);\n# RT.h = RB.h - EXTZ(UI);\n\n tmp:8 = BITS_16_20*1;\n lo:$(REGISTER_SIZE) = (( B & (0x0000000000000000) ) >> 32) - tmp;\n hi:$(REGISTER_SIZE) = (( B & (0xFFFFFFFF00000000) ) >> 32) - tmp;\n D = (( zext(hi) << 32) | zext(lo) );\n}\n\n# evsubiw => evsubifw\n\n# evsubw => evsubfw\n\n# evxor RT,RA,RB\n# ISA-cmt: Vector XOR\n# evxor rD,rA,rB 010 0001 0110\n:evxor vrD_64_0,vrA_64_0,vrB_64_0 is OP=4 & vrD_64_0 & vrA_64_0 & vrB_64_0 & XOP_0_10=534\n{\n vrD_64_0 = vrA_64_0 ^ vrB_64_0;\n}\n\n# TODO evmwlssianw RT,RA,RB\n# TODO complicated\n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/SPE_EFSD.sinc", "content": "# Based on \"PowerISA Version 2.06 Revision B\" document dated July 23, 2010\n# Category: SPE.Embedded Float Scalar Double\n\n# version 1.0\n\n# =================================================================\n# Page 576\n\n# efdabs rT,rA\n# ISA-cmt: efdabs - Floating-Point Double-Precision Absolute Value\n# ISA-info: efdabs - Form \"EVX\" Page 576 Category \"SP.FD\"\n# binutils: e500.d: 34:\t10 a4 02 e4 \tefdabs r5,r4\n:efdabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=740\n{\n D = abs( A );\n}\n \n# =================================================================\n# Page 577\n\n# efdadd rT,rA,rB\n# ISA-cmt: efdadd - Floating-Point Double-Precision Add\n# ISA-info: efdadd - Form \"EVX\" Page 577 Category \"SP.FD\"\n# binutils: e500.d: 40:\t10 a4 1a e0 \tefdadd r5,r4,r3\n:efdadd D,A,B is OP=4 & D & A & B & XOP_0_10=736\n{\n D = A f+ B;\n setSPEFSCRAddFlags_L( A, B, D );\n}\n\n\n# =================================================================\n# Page 582\n\n# efdcfs rT,rB\n# ISA-cmt: efdcfs - Floating-Point Double-Precision Convert from Single-Precision\n# ISA-info: efdcfs - Form \"EVX\" Page 582 Category \"SP.FD\"\n# binutils: e500.d: a4:\t10 a0 22 ef \tefdcfs r5,r4\n:efdcfs D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=751\n{\n D = float2float( B:4 );\n setSPEFSCR_L( D );\n setSummarySPEFSCR();\n}\n\n\n# =================================================================\n# Page 580\n\n# efdcfsf rT,rB\n# ISA-cmt: efdcfsf - Convert Floating-Point Double-Precision from Signed Fraction\n# ISA-info: efdcfsf - Form \"EVX\" Page 580 Category \"SP.FD\"\n# binutils: e500.d: 7c:\t10 a0 22 f3 \tefdcfsf r5,r4\n:efdcfsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=755\n{\n # load fractional divisor as a float\n tmpA:4 = 0x80000000;\n tmpA = int2float( tmpA );\n setSPEFSCR_L( tmpA );\n\n # check if negative\n if ( ( B:4 & 0x80000000 ) != 0 ) goto ;\n\n # float the fractional portion of register B\n tmpB:4 = int2float( B:4 );\n setSPEFSCR_L( tmpB );\n tmpB = tmpB f/ tmpA;\n setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB );\n\n goto ;\n\n \n\n # float the fractional portion of register B, 2's complement negate\n tmpB = int2float( -( B:4 ) );\n setSPEFSCR_L( tmpB );\n tmpB = tmpB f/ tmpA;\n setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB );\n\n # negate the float\n tmpB = f-( tmpB );\n setSPEFSCR_L( tmpB );\n \n \n\n tmpC:8 = float2float( tmpB );\n setSPEFSCR_L( tmpC );\n\n setSummarySPEFSCR();\n\n D = tmpC;\n}\n\n\n# =================================================================\n# Page 579\n\n# efdcfsi rT,rB\n# ISA-cmt: efdcfsi - Convert Floating-Point Double-Precision from Signed Integer\n# ISA-info: efdcfsi - Form \"EVX\" Page 579 Category \"SP.FD\"\n# binutils: e500.d: 6c:\t10 a0 22 f1 \tefdcfsi r5,r4\n:efdcfsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=753 \n{\n # check if negative\n if ( ( B:4 & 0x80000000 ) != 0 ) goto ;\n\n # float the integer portion of register B\n tmpB:8 = int2float( B:4 );\n setSPEFSCR_L( tmpB );\n\n goto ;\n\n \n\n # float the integer portion of register B, 2's complement negate\n tmpB = int2float( -( B:4 ) );\n setSPEFSCR_L( tmpB );\n\n # negate the float\n tmpB = f-( tmpB );\n setSPEFSCR_L( tmpB );\n \n \n\n setSummarySPEFSCR();\n\n D = tmpB;\n}\n\n\n# =================================================================\n# Page 580\n\n# efdcfsid rT,rB\n# ISA-cmt: efdcfsid - Convert Floating-Point Double-Precision from Signed Integer Doubleword\n# ISA-info: efdcfsid - Form \"EVX\" Page 580 Category \"SP.FD\"\n# binutils: e500.d: 70:\t10 a0 22 e3 \tefdcfsid r5,r4\n:efdcfsid D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=739 \n{\n # check if negative\n if ( ( B & 0x8000000000000000 ) != 0 ) goto ;\n\n # float the integer portion of register B\n tmpB:8 = int2float( B );\n setSPEFSCR_L( tmpB );\n\n goto ;\n\n \n\n # float the integer portion of register B, 2's complement negate\n tmpB = int2float( -( B ) );\n setSPEFSCR_L( tmpB );\n\n # negate the float\n tmpB = f-( tmpB );\n setSPEFSCR_L( tmpB );\n \n \n\n setSummarySPEFSCR();\n\n D = tmpB;\n}\n\n\n# =================================================================\n# Page 580\n\n# efdcfuf rT,rB\n# ISA-cmt: efdcfuf - Convert Floating-Point Double-Precision from Unsigned Fraction\n# ISA-info: efdcfuf - Form \"EVX\" Page 580 Category \"SP.FD\"\n# binutils: e500.d: 80:\t10 a0 22 f2 \tefdcfuf r5,r4\n:efdcfuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=754\n{\n # load fractional divisor as a float\n tmpA:8 = 0x0000000100000000;\n tmpA = int2float( tmpA );\n setSPEFSCR_L( tmpA );\n\n # float the fractional portion of register B\n tmpB:8 = int2float( B:4 );\n setSPEFSCR_L( tmpB );\n tmpB = tmpB f/ tmpA;\n setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB );\n\n D = tmpB;\n}\n\n\n# =================================================================\n# Page 579\n\n#efdcfui rT,rB\n# ISA-cmt: efdcfui - Convert Floating-Point Double-Precision from Unsigned Integer\n# ISA-info: efdcfui - Form \"EVX\" Page 579 Category \"SP.FD\"\n# binutils: e500.d: 74:\t10 a0 22 f0 \tefdcfui r5,r4\n:efdcfui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=752\n{\n tmp:8 = int2float( B:4 );\n setSPEFSCR_L( tmp );\n\n setSummarySPEFSCR();\n\n D = tmp;\n}\n\n\n# =================================================================\n# Page 580\n\n#efdcfuid rT,rB\n# ISA-cmt: efdcfuid - Convert Floating-Point Double-Precision from Unsigned Integer Doubleword\n# ISA-info: efdcfuid - Form \"EVX\" Page 580 Category \"SP.FD\"\n# binutils: e500.d: 78:\t10 a0 22 e2 \tefdcfuid r5,r4\n:efdcfuid D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=738\n{\n tmp:8 = int2float( B );\n setSPEFSCR_L( tmp );\n\n setSummarySPEFSCR();\n\n D = tmp;\n}\n\n\n# =================================================================\n# Page 578\n\n# efdcmpeq CRFD,rA,rB\n# ISA-cmt: efdcmpeq - Floating-Point Double-Precision Compare Equal\n# ISA-info: efdcmpeq - Form \"EVX\" Page 578 Category \"SP.FD\"\n# binutils: e500.d: 58:\t12 84 1a ee \tefdcmpeq cr5,r4,r3\n:efdcmpeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=750\n{\n CRFD = A f== B;\n}\n\n\n# =================================================================\n# Page 578\n\n# efdcmpgt CRFD,rA,rB\n# ISA-cmt: efdcmpgt - Floating-Point Double-Precision Compare Greater Than\n# ISA-info: efdcmpgt - Form \"EVX\" Page 578 Category \"SP.FD\"\n# binutils: e500.d: 50:\t12 84 1a ec \tefdcmpgt cr5,r4,r3\n:efdcmpgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=748\n{\n CRFD = A f> B;\n}\n\n\n# =================================================================\n# Page 578\n\n# efdcmplt CRFD,rA,rB\n# ISA-cmt: efdcmplt - Floating-Point Double-Precision Compare Less Than\n# ISA-info: efdcmplt - Form \"EVX\" Page 578 Category \"SP.FD\"\n# binutils: e500.d: 54:\t12 84 1a ed \tefdcmplt cr5,r4,r3\n:efdcmplt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=749\n{\n CRFD = A f< B;\n}\n\n\n# =================================================================\n# Page 578\n\n# efdctsf rT,rB\n# ISA-cmt: efdctsf - Convert Floating-Point Double-Precision to Signed Fraction\n# ISA-info: efdctsf - Form \"EVX\" Page 582 Category \"SP.FD\"\n# binutils: e500.d: 9c:\t10 a0 22 f7 \tefdctsf r5,r4\n:efdctsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=759\n{\n # multiply by 0x8000 0000 0000 0000 to scale the fraction up to integer range\n\n # load fractional multiplier as a float\n tmpM:8 = 0x8000000000000000;\n tmpM = int2float( tmpM );\n setSPEFSCR_L( tmpM );\n\n # load saturation limit as a float\n tmpL:8 = 0x8000000000000000 - 1;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # scale the saturation limit to a fractional float\n tmpL = tmpL f/ tmpM;\n setSPEFSCRDivFlags_L( tmpL, tmpM, tmpL );\n\n tmpB:8 = B;\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpL ) goto ;\n\n # set to positive saturation\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n goto ;\n\n \n\n # check if greater than or equal to negative saturation limit\n tmpL = f-( tmpL );\n if ( tmpB f>= tmpL ) goto ;\n\n # set to negative saturation\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB );\n\n # truncate back to signed fraction format\n tmpC:8 = trunc( tmpB );\n setSPEFSCR_L( tmpB );\n\n setSummarySPEFSCR();\n\n D = tmpC;\n}\n\n\n# =================================================================\n# Page 580\n\n# efdctsi rT,rB\n# ISA-cmt: efdctsi - Convert Floating-Point Double-Precision to Signed Integer\n# ISA-info: efdctsi - Form \"EVX\" Page 580 Category \"SP.FD\"\n# binutils: e500.d: 84:\t10 a0 22 f5 \tefdctsi r5,r4\n:efdctsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=757\n{\n # create zero float constant\n tmpA:8 = 0;\n tmpA = int2float( tmpA );\n\n # check if negative\n if ( B f< tmpA ) goto ;\n\n tmpB:8 = round( B );\n setSPEFSCR_L( tmpB );\n\n # limit to positive saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n goto ;\n\n \n\n # negate the float\n tmpB = round( f-( B ) );\n setSPEFSCR_L( tmpB );\n\n # limit to negative saturation\n if ( tmpB <= 0x0000000080000000 ) goto ;\n tmpB = 0x0000000080000000;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # negate the signed int\n tmpB = -( tmpB );\n\n \n\n setSummarySPEFSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n\n# =================================================================\n# Page 581\n\n# efdctsidz rT,rB\n# ISA-cmt: efdctsidz - Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero\n# ISA-info: efdctsidz - Form \"EVX\" Page 581 Category \"SP.FD\"\n# binutils: e500.d: 88:\t10 a0 22 eb \tefdctsidz r5,r4\n# Note: This may not work correctly as the number approaches saturation; too little (16 digits) precision in mantissa\n:efdctsidz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=747\n{\n # create zero float constant\n tmpA:8 = 0;\n tmpA = int2float( tmpA );\n\n tmpB:8 = B;\n\n # check if negative\n if ( tmpB f< tmpA ) goto ;\n\n # load saturation limit as a float\n tmpL:8 = 0x8000000000000000 - 1;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # limit to saturation\n if ( tmpB <= tmpL ) goto ;\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpB = trunc( tmpB );\n setSPEFSCR_L( tmpB );\n\n goto ;\n\n \n\n # load saturation limit as a float\n tmpL = 0x8000000000000000;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # negate float (make positive)\n tmpB = f-( tmpB );\n\n # limit to saturation\n if ( tmpB <= tmpL ) goto ;\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpB = trunc( tmpB );\n setSPEFSCR_L( tmpB );\n\n # negate the signed int\n tmpB = -( tmpB );\n\n \n\n setSummarySPEFSCR();\n\n D = tmpB;\n}\n\n\n# =================================================================\n# Page 582\n\n# efdctsiz rT,rB\n# ISA-cmt: efdctsiz - Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero\n# ISA-info: efdctsiz - Form \"EVX\" Page 582 Category \"SP.FD\"\n# binutils: e500.d: 8c:\t10 a0 22 fa \tefdctsiz r5,r4\n:efdctsiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=762\n{\n # create zero float constant\n tmpA:8 = 0;\n tmpA = int2float( tmpA );\n\n # check if negative\n if ( B f< tmpA ) goto ;\n\n tmpB:8 = trunc( B );\n setSPEFSCR_L( tmpB );\n\n # limit to positive saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n goto ;\n\n \n\n # negate the float\n tmpB = trunc( f-( B ) );\n setSPEFSCR_L( tmpB );\n\n # limit to negative saturation\n if ( tmpB <= 0x0000000080000000 ) goto ;\n tmpB = 0x0000000080000000;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # negate the signed int\n tmpB = -( tmpB );\n\n \n\n setSummarySPEFSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n\n# =================================================================\n# Page 582\n\n# efdctuf rT,rB\n# ISA-cmt: efdctuf - Convert Floating-Point Double-Precision to Unsigned Fraction\n# ISA-info: efdctuf - Form \"EVX\" Page 582 Category \"SP.FD\"\n# binutils: e500.d: a0:\t10 a0 22 f6 \tefdctuf r5,r4\n:efdctuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=758\n{\n # multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range\n\n # load fractional multiplier as a float\n tmpM:8 = 0x0000000100000000;\n tmpM = int2float( tmpM );\n setSPEFSCR_L( tmpM );\n\n # load saturation limit as a float\n tmpL:8 = 0x0000000100000000 - 1;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # scale the saturation limit to a fractional float\n tmpL = tmpL f/ tmpM;\n setSPEFSCRDivFlags_L( tmpL, tmpM, tmpL );\n\n # get B float up to 64 bit width\n tmpB:8 = B;\n setSPEFSCR_L( tmpB );\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpL ) goto ;\n\n # set to saturation\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB );\n\n # truncate back to integer\n tmpC:4 = trunc( tmpB );\n setSPEFSCR_L( tmpC );\n\n setSummarySPEFSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );\n}\n\n\n# =================================================================\n# Page 580\n\n# efdctui rT,rB\n# ISA-cmt: efdctui - Convert Floating-Point Double-Precision to Unsigned Integer\n# ISA-info: efdctui - Form \"EVX\" Page 580 Category \"SP.FD\"\n# binutils: e500.d: 90:\t10 a0 22 f4 \tefdctui r5,r4\n:efdctui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=756\n{\n tmpB:8 = B;\n\n # load saturation limit as a float\n tmpL:8 = 0x00000000FFFFFFFF;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # limit to saturation\n if ( tmpB f<= tmpL ) goto ;\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # round back to integer\n tmpC:4 = trunc(round( tmpB ));\n setSPEFSCR_L( tmpB );\n\n setSummarySPEFSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );\n}\n\n\n# =================================================================\n# Page 581\n\n# efdctuidz rT,rB\n# ISA-cmt: efdctuidz - Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero\n# ISA-info: efdctuidz - Form \"EVX\" Page 581 Category \"SP.FD\"\n# binutils: e500.d: 94:\t10 a0 22 ea \tefdctuidz r5,r4\n:efdctuidz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=746\n{\n tmpB:8 = B;\n\n # load saturation limit as a float\n tmpL:8 = 0xFFFFFFFFFFFFFFFF;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # limit to saturation\n if ( tmpB f<= tmpL ) goto ;\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpB = trunc( tmpB );\n\n setSummarySPEFSCR();\n\n D = tmpB;\n}\n\n\n# =================================================================\n# Page 582\n\n# efdctuiz rT,rB\n# ISA-cmt: efdctuiz - Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero\n# ISA-info: efdctuiz - Form \"EVX\" Page 582 Category \"SP.FD\"\n# binutils: e500.d: 98:\t10 a0 22 f8 \tefdctuiz r5,r4\n:efdctuiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=760\n{\n tmpB:8 = B;\n\n # load saturation limit as a float\n tmpL:8 = 0x00000000FFFFFFFF;\n tmpL = int2float( tmpL );\n setSPEFSCR_L( tmpL );\n\n # limit to saturation\n if ( tmpB f<= tmpL ) goto ;\n tmpB = tmpL;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpB = trunc( tmpB );\n\n setSummarySPEFSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n\n# =================================================================\n# Page 577\n\n# efddiv rT,rA,rB\n# ISA-cmt: efddiv - Floating-Point Double-Precision Divide\n# ISA-info: efddiv - Form \"EVX\" Page 577 Category \"SP.FD\"\n# binutils: e500.d: 4c:\t10 a4 1a e9 \tefddiv r5,r4,r3\n:efddiv D,A,B is OP=4 & D & A & B & XOP_0_10=745\n{\n D = A f/ B;\n setSPEFSCRDivFlags_L( A, B, D );\n}\n\n\n# =================================================================\n# Page 577\n\n# efdmul rT,rA,rB\n# ISA-cmt: efdmul - Floating-Point Double-Precision Multiply\n# ISA-info: efdmul - Form \"EVX\" Page 577 Category \"SP.FD\"\n# binutils: e500.d: 48:\t10 a4 1a e8 \tefdmul r5,r4,r3\n:efdmul D,A,B is OP=4 & D & A & B & XOP_0_10=744\n{\n D = A f* B;\n setSPEFSCRMulFlags_L( A, B, D );\n}\n\n\n# =================================================================\n# Page 576\n\n# efdnabs rT,rA\n# ISA-cmt: efdnabs - Floating-Point Double-Precision Negative Absolute Value\n# ISA-info: efdnabs - Form \"EVX\" Page 576 Category \"SP.FD\"\n# binutils: e500.d: 38:\t10 a4 02 e5 \tefdnabs r5,r4\n:efdnabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=741\n{\n D = f- ( abs( A ) );\n}\n\n\n# =================================================================\n# Page 577\n\n# efdneg rT,rA\n# ISA-cmt: efdneg - Floating-Point Double-Precision Negate\n# ISA-info: efdneg - Form \"EVX\" Page 576 Category \"SP.FD\"\n# binutils: e500.d: 3c:\t10 a4 02 e6 \tefdneg r5,r4\n:efdneg D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=742\n{\n D = f-( A );\n}\n\n\n# =================================================================\n# Page 577\n\n# efdsub rT,rA,rB\n# ISA-cmt: efdsub - Floating-Point Double-Precision Subtract\n# ISA-info: efdsub - Form \"EVX\" Page 577 Category \"SP.FD\"\n# binutils: e500.d: 44:\t10 a4 1a e1 \tefdsub r5,r4,r3\n:efdsub D,A,B is OP=4 & D & A & B & XOP_0_10=737\n{\n D = A f- B;\n setSPEFSCRSubFlags_L( A, B, D );\n}\n\n\n# =================================================================\n# Page 579\n\n# efdtsteq CRFD,rA,rB\n# ISA-cmt: efdtsteq - Floating-Point Double-Precision Test Equal\n# ISA-info: efdtsteq - Form \"EVX\" Page 579 Category \"SP.FD\"\n# binutils: e500.d: 68:\t12 84 1a fe \tefdtsteq cr5,r4,r3\n:efdtsteq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=766\n{\n CRFD = A f== B;\n}\n\n\n# =================================================================\n# Page 578\n\n# efdtstgt CRFD,rA,rB\n# ISA-cmt: efdtstgt - Floating-Point Double-Precision Test Greater Than\n# ISA-info: efdtstgt - Form \"EVX\" Page 578 Category \"SP.FD\"\n# binutils: e500.d: 5c:\t12 84 1a fc \tefdtstgt cr5,r4,r3\n# binutils: e500.d: 60:\t12 84 1a fc \tefdtstgt cr5,r4,r3\n:efdtstgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=764\n{\n CRFD = A f> B;\n}\n\n\n# =================================================================\n# Page 579\n\n# efdtstlt CRFD,rA,rB\n# ISA-cmt: efdtstlt - Floating-Point Double-Precision Test Less Than\n# ISA-info: efdtstlt - Form \"EVX\" Page 579 Category \"SP.FD\"\n# binutils: e500.d: 64:\t12 84 1a fd \tefdtstlt cr5,r4,r3\n:efdtstlt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=765\n{\n CRFD = A f< B;\n}\n\n\n# =================================================================\n# Page 583\n\n# efscfd rT,rB\n# ISA-cmt: efscfd - Floating-Point Single-Precision Convert from Double-Precision\n# ISA-info: efscfd - Form \"EVX\" Page 583 Category \"SP.FD\"\n# binutils: e500.d: 30:\t10 a0 22 cf \tefscfd r5,r4\n:efscfd D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=719\n{\n tmpB:4 = float2float( B );\n setSPEFSCR_L( tmpB );\n setSummarySPEFSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB );\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/SPE_EFV.sinc", "content": "# Based on \"PowerISA Version 2.06 Revision B\" document dated July 23, 2010\n# Category: SPE.Embedded Float Vector Instructions\n\n\n# =================================================================\n# Page 561\n\n# evfsabs rT,rA\n# ISA-cmt: evfsabs - Vector Floating-Point Single-Precision Absolute Value\n# ISA-info: evfsabs - Form \"EVX\" Page 561 Category \"SP.FV\"\n# binutils: mytest.d: 1e0:\t10 22 02 84 \tevfsabs r1,r2\n:evfsabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=644\n{\n #\n # low section\n #\n tmpA:4 = abs( A:4 );\n\n #\n # high section\n #\n tmpB:4 = abs( A(4) );\n\n # move results into upper and lower words\n tmpC:8 = zext( tmpB );\n tmpC = ( tmpC << 32 ) | zext( tmpA );\n\n D = tmpC;\n}\n \n# =================================================================\n# Page 562\n\n# evfsadd rT,rA,rB\n# ISA-cmt: evfsadd - Vector Floating-Point Single-Precision Add\n# ISA-info: evfsadd - Form \"EVX\" Page 562 Category \"SP.FV\"\n# binutils: mytest.d: 1d8:\t10 22 1a 80 \tevfsadd r1,r2,r3\n:evfsadd D,A,B is OP=4 & D & A & B & XOP_0_10=640\n{\n #\n # low section\n #\n tmpA:4 = A:4 f+ B:4;\n setSPEFSCRAddFlags_L( A:4, B:4, tmpA );\n\n #\n # high section\n #\n tmpB:4 = A(4) f+ B(4);\n\n # SLEIGH had a problem with using A(4) and B(4) directly here\n tmpD:4 = A(4);\n tmpE:4 = B(4);\n setSPEFSCRAddFlags_H( tmpD, tmpE, tmpB );\n\n # move results into upper and lower words\n tmpC:8 = zext( tmpB );\n tmpC = ( tmpC << 32 ) | zext( tmpA );\n\n D = tmpC;\n}\n\n\n# =================================================================\n# Page 566\n\n# evfscfsf rT,rB\n# ISA-cmt: evfscfsf - Vector Convert Floating-Point Single-Precision from Signed Fraction\n# ISA-info: evfscfsf - Form \"EVX\" Page 566 Category \"SP.FV\"\n# binutils: mytest.d: 20c:\t10 20 12 93 \tevfscfsf r1,r2\n:evfscfsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=659\n{\n # load fractional divisor as a float\n tmpA:4 = 0x80000000;\n tmpA = int2float( tmpA );\n setSPEFSCR_L( tmpA );\n\n #\n # low section\n #\n tmpE:4 = B:4;\n\n # check if negative\n if ( ( tmpE & 0x80000000 ) != 0 ) goto ;\n\n # float the fractional portion of register B\n tmpB:4 = int2float( tmpE );\n setSPEFSCR_L( tmpB );\n tmpC:4 = tmpB f/ tmpA;\n setSPEFSCRDivFlags_L( tmpB, tmpA, tmpC );\n\n goto ;\n\n \n\n # float the fractional portion of register B, 2's complement negate\n tmpB = int2float( -( tmpE ) );\n setSPEFSCR_L( tmpB );\n tmpC = tmpB f/ tmpA;\n setSPEFSCRDivFlags_L( tmpB, tmpA, tmpC );\n\n # negate the float\n tmpC = f-( tmpC );\n setSPEFSCR_L( tmpC );\n \n \n\n setSummarySPEFSCR();\n\n #\n # high section\n #\n tmpE = B(4);\n\n # check if negative\n if ( ( tmpE & 0x80000000 ) != 0 ) goto ;\n\n # float the fractional portion of register B\n tmpB = int2float( tmpE );\n setSPEFSCR_H( tmpB );\n tmpD:4 = tmpB f/ tmpA;\n setSPEFSCRDivFlags_H( tmpB, tmpA, tmpD );\n\n goto ;\n\n \n\n # float the fractional portion of register B, 2's complement negate\n tmpB = int2float( -( tmpE ) );\n setSPEFSCR_H( tmpB );\n tmpD = tmpB f/ tmpA;\n setSPEFSCRDivFlags_H( tmpB, tmpA, tmpD );\n\n # negate the float\n tmpD = f-( tmpD );\n setSPEFSCR_H( tmpD );\n \n \n\n setSummarySPEFSCR();\n\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpD );\n tmpZ = ( tmpZ << 32 ) | zext( tmpC );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 566\n\n# evfscfsi rT,rB\n# ISA-cmt: evfscfsi - Vector Convert Floating-Point Single-Precision from Signed Integer\n# ISA-info: evfscfsi - Form \"EVX\" Page 566 Category \"SP.FV\"\n# binutils: mytest.d: 204:\t10 20 12 91 \tevfscfsi r1,r2\n:evfscfsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=657 \n{\n #\n # low section\n #\n tmpE:4 = B:4;\n\n # check if negative\n if ( ( tmpE & 0x80000000 ) != 0 ) goto ;\n\n # float the integer portion of register B\n tmpB:4 = int2float( tmpE );\n setSPEFSCR_L( tmpB );\n\n goto ;\n\n \n\n # float the integer portion of register B, 2's complement negate\n tmpB = int2float( -( tmpE ) );\n setSPEFSCR_L( tmpB );\n\n # negate the float\n tmpB = f-( tmpB );\n setSPEFSCR_L( tmpB );\n \n \n\n setSummarySPEFSCR();\n\n\n #\n # high section\n #\n tmpE = B(4);\n\n # check if negative\n if ( ( tmpE & 0x80000000 ) != 0 ) goto ;\n\n # float the integer portion of register B\n tmpC:4 = int2float( tmpE );\n setSPEFSCR_H( tmpC );\n\n goto ;\n\n \n\n # float the integer portion of register B, 2's complement negate\n tmpC = int2float( -( tmpE ) );\n setSPEFSCR_H( tmpC );\n\n # negate the float\n tmpC = f-( tmpC );\n setSPEFSCR_H( tmpC );\n \n \n\n setSummarySPEFSCR();\n\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpC );\n tmpZ = ( tmpZ << 32 ) | zext( tmpB );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 566\n\n# evfscfuf rT,rB\n# ISA-cmt: evfscfuf - Vector Convert Floating-Point Single-Precision from Unsigned Fraction\n# ISA-info: evfscfuf - Form \"EVX\" Page 566 Category \"SP.FV\"\n# binutils: mytest.d: 208:\t10 20 12 92 \tevfscfuf r1,r2\n:evfscfuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=658\n{\n # load fractional divisor as a float\n tmpA:8 = 0x0000000100000000;\n tmpF:4 = int2float( tmpA );\n setSPEFSCR_L( tmpF );\n\n #\n # low section\n #\n tmpE:4 = B:4;\n\n # float the fractional portion of register B\n tmpB:4 = int2float( tmpE );\n setSPEFSCR_L( tmpB );\n tmpC:4 = tmpB f/ tmpF;\n setSPEFSCRDivFlags_L( tmpB, tmpF, tmpC );\n\n #\n # high section\n #\n tmpE = B(4);\n\n # float the fractional portion of register B\n tmpB = int2float( tmpE );\n setSPEFSCR_H( tmpB );\n tmpD:4 = tmpB f/ tmpF;\n setSPEFSCRDivFlags_H( tmpB, tmpF, tmpD );\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpD );\n tmpZ = ( tmpZ << 32 ) | zext( tmpC );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 566\n\n#evfscfui rT,rB\n# ISA-cmt: evfscfui - Vector Convert Floating-Point Single-Precision from Unsigned Integer\n# ISA-info: evfscfui - Form \"EVX\" Page 566 Category \"SP.FV\"\n# binutils: mytest.d: 200:\t10 20 12 90 \tevfscfui r1,r2\n:evfscfui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=656\n{\n #\n # low section\n #\n tmpE:4 = B:4;\n\n tmpC:4 = int2float( tmpE );\n setSPEFSCR_L( tmpC );\n\n #\n # high section\n #\n tmpE = B(4);\n\n tmpD:4 = int2float( tmpE );\n setSPEFSCR_H( tmpD );\n\n setSummarySPEFSCR();\n\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpD );\n tmpZ = ( tmpZ << 32 ) | zext( tmpC );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 564\n\n# evfscmpeq CRFD,rA,rB\n# ISA-cmt: evfscmpeq - Vector Floating-Point Single-Precision Compare Equal\n# ISA-info: evfscmpeq - Form \"EVX\" Page 564 Category \"SP.FV\"\n# binutils: mytest.d: 1fc:\t10 82 1a 8e \tevfscmpeq cr1,r2,r3\n:evfscmpeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=654\n{\n tmpA:4 = A:4;\n tmpB:4 = B:4;\n tmpC:4 = A(4);\n tmpD:4 = B(4);\n\n tmpL:1 = tmpA f== tmpB;\n tmpH:1 = tmpC f== tmpD;\n\n CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL);\n}\n\n\n# =================================================================\n# Page 563\n\n# evfscmpgt CRFD,rA,rB\n# ISA-cmt: evfscmpgt - Vector Floating-Point Single-Precision Compare Greater Than\n# ISA-info: evfscmpgt - Form \"EVX\" Page 563 Category \"SP.FV\"\n# binutils: mytest.d: 1f4:\t10 82 1a 8c \tevfscmpgt cr1,r2,r3\n:evfscmpgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=652\n{\n tmpA:4 = A:4;\n tmpB:4 = B:4;\n tmpC:4 = A(4);\n tmpD:4 = B(4);\n\n tmpL:1 = tmpA f> tmpB;\n tmpH:1 = tmpC f> tmpD;\n\n CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL);\n}\n\n\n# =================================================================\n# Page 563\n\n# evfscmplt CRFD,rA,rB\n# ISA-cmt: evfscmplt - Vector Floating-Point Single-Precision Compare Less Than\n# ISA-info: evfscmplt - Form \"EVX\" Page 563 Category \"SP.FV\"\n# binutils: mytest.d: 1f8:\t10 82 1a 8d \tevfscmplt cr1,r2,r3\n:evfscmplt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=653\n{\n tmpA:4 = A:4;\n tmpB:4 = B:4;\n tmpC:4 = A(4);\n tmpD:4 = B(4);\n\n tmpL:1 = tmpA f< tmpB;\n tmpH:1 = tmpC f< tmpD;\n\n CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL);\n}\n\n\n# =================================================================\n# Page 568\n\n# evfsctsf rT,rB\n# ISA-cmt: evfsctsf - Vector Convert Floating-Point Single-Precision to Signed Fraction\n# ISA-info: evfsctsf - Form \"EVX\" Page 568 Category \"SP.FV\"\n# binutils: mytest.d: 21c:\t10 20 12 97 \tevfsctsf r1,r2\n:evfsctsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=663\n{\n # multiply by 0x8000 0000 to scale the fraction up to integer range\n\n # load fractional multiplier as a float\n tmpM:4 = 0x80000000;\n tmpM = int2float( tmpM );\n setSPEFSCR_L( tmpM );\n\n # load saturation limit as a float\n tmpS:4 = 0x80000000 - 1;\n tmpS = int2float( tmpS );\n setSPEFSCR_L( tmpS );\n\n # scale the saturation limit to a fractional float\n tmpS = tmpS f/ tmpM;\n setSPEFSCRDivFlags_L( tmpS, tmpM, tmpS );\n\n # form negative saturation limit\n tmpN:4 = f-( tmpS );\n\n #\n # low section\n #\n tmpB:4 = B:4;\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpS ) goto ;\n\n # set to positive saturation\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n goto ;\n\n \n\n # check if greater than or equal to negative saturation limit\n if ( tmpB f>= tmpN ) goto ;\n\n # set to negative saturation\n tmpB = tmpN;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB );\n\n # truncate back to signed fraction format\n tmpL:4 = trunc( tmpB );\n setSPEFSCR_L( tmpL );\n\n setSummarySPEFSCR();\n\n\n #\n # high section\n #\n tmpB = B(4);\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpS ) goto ;\n\n # set to positive saturation\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n goto ;\n\n \n\n # check if greater than or equal to negative saturation limit\n if ( tmpB f>= tmpN ) goto ;\n\n # set to negative saturation\n tmpB = tmpN;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setSPEFSCRMulFlags_H( tmpB, tmpM, tmpB );\n\n # truncate back to signed fraction format\n tmpH:4 = trunc( tmpB );\n setSPEFSCR_H( tmpH );\n\n setSummarySPEFSCR();\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 567\n\n# evfsctsi rT,rB\n# ISA-cmt: evfsctsi - Vector Convert Floating-Point Single-Precision to Signed Integer\n# ISA-info: evfsctsi - Form \"EVX\" Page 567 Category \"SP.FV\"\n# binutils: mytest.d: 214:\t10 20 12 95 \tevfsctsi r1,r2\n:evfsctsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=661\n{\n # create zero float constant\n tmpA:4 = 0;\n tmpA = int2float( tmpA );\n\n #\n # low section\n #\n tmpB:4 = B:4;\n\n # check if negative\n if ( tmpB f< tmpA ) goto ;\n\n tmpB = round( tmpB );\n setSPEFSCR_L( tmpB );\n\n # limit to positive saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpL:4 = tmpB;\n\n goto ;\n\n \n\n # negate the float\n tmpB = round( f-( tmpB ) );\n setSPEFSCR_L( tmpB );\n\n # limit to negative saturation\n if ( tmpB <= 0x0000000080000000 ) goto ;\n tmpB = 0x0000000080000000;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # negate the signed int\n tmpL = -( tmpB );\n\n \n\n setSummarySPEFSCR();\n\n #\n # high section\n #\n tmpB = B(4);\n\n # check if negative\n if ( tmpB f< tmpA ) goto ;\n\n tmpB = round( tmpB );\n setSPEFSCR_H( tmpB );\n\n # limit to positive saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpH:4 = tmpB;\n\n goto ;\n\n \n\n # negate the float\n tmpB = round( f-( tmpB ) );\n setSPEFSCR_H( tmpB );\n\n # limit to negative saturation\n if ( tmpB <= 0x0000000080000000 ) goto ;\n tmpB = 0x0000000080000000;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # negate the signed int\n tmpH = -( tmpB );\n\n \n\n setSummarySPEFSCR();\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 567\n\n# evfsctsiz rT,rB\n# ISA-cmt: evfsctsiz - Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero\n# ISA-info: evfsctsiz - Form \"EVX\" Page 567 Category \"SP.FV\"\n# binutils: mytest.d: 224:\t10 20 12 9a \tevfsctsiz r1,r2\n:evfsctsiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=666\n{\n # create zero float constant\n tmpA:8 = 0;\n tmpA = int2float( tmpA );\n\n # create positive saturation float constant\n tmpS:8 = 0x000000007FFFFFFF;\n tmpS = int2float( tmpS );\n\n # create negative saturation float constant\n tmpN:8 = 0x0000000080000000;\n tmpN = int2float( tmpN );\n\n #\n # low section\n #\n tmpB:8 = float2float( B:4 );\n\n # check if negative\n if ( tmpB f< tmpA ) goto ;\n\n # limit to positive saturation\n if ( tmpB f<= tmpS ) goto ;\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpL:4 = trunc( tmpB );\n setSPEFSCR_L( tmpL );\n\n goto ;\n\n\n \n\n # negate the float\n tmpB = f-( tmpB );\n\n # limit to negative saturation\n if ( tmpB f<= tmpN ) goto ;\n tmpB = tmpN;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # negate the signed int\n tmpL = -( trunc( tmpB ) );\n setSPEFSCR_L( tmpL );\n\n \n\n setSummarySPEFSCR();\n\n #\n # high section\n #\n tmpE:4 = B(4);\n tmpB = float2float( tmpE );\n\n # check if negative\n if ( tmpB f< tmpA ) goto ;\n\n # limit to positive saturation\n if ( tmpB f<= tmpS ) goto ;\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpH:4 = trunc( tmpB );\n setSPEFSCR_H( tmpH );\n\n goto ;\n\n\n \n\n # negate the float\n tmpB = f-( tmpB );\n\n # limit to negative saturation\n if ( tmpB f<= tmpN ) goto ;\n tmpB = tmpN;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # negate the signed int\n tmpH = -( trunc( tmpB ) );\n setSPEFSCR_H( tmpH );\n\n \n\n setSummarySPEFSCR();\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 568\n\n# evfsctuf rT,rB\n# ISA-cmt: evfsctuf - Vector Convert Floating-Point Single-Precision to Unsigned Fraction\n# ISA-info: evfsctuf - Form \"EVX\" Page 568 Category \"SP.FV\"\n# binutils: mytest.d: 218:\t10 20 12 96 \tevfsctuf r1,r2\n:evfsctuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=662\n{\n # multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range\n\n # load fractional multiplier as a float\n tmpM:8 = 0x0000000100000000;\n tmpM = int2float( tmpM );\n setSPEFSCR_L( tmpM );\n\n # load saturation limit as a float\n tmpS:8 = 0x0000000100000000 - 1;\n tmpS = int2float( tmpS );\n setSPEFSCR_L( tmpS );\n\n # scale the saturation limit to a fractional float\n tmpS = tmpS f/ tmpM;\n setSPEFSCRDivFlags_L( tmpS, tmpM, tmpS );\n\n #\n # low section\n #\n # get B float up to 64 bit width\n tmpE:4 = B:4;\n tmpB:8 = float2float( tmpE );\n setSPEFSCR_L( tmpB );\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpS ) goto ;\n\n # set to saturation\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB );\n\n # truncate back to integer\n tmpL:4 = trunc( tmpB );\n setSPEFSCR_L( tmpL );\n\n setSummarySPEFSCR();\n\n #\n # high section\n #\n # get B float up to 64 bit width\n tmpE = B(4);\n tmpB = float2float( tmpE );\n setSPEFSCR_H( tmpB );\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpS ) goto ;\n\n # set to saturation\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setSPEFSCRMulFlags_H( tmpB, tmpM, tmpB );\n\n # truncate back to integer\n tmpH:4 = trunc( tmpB );\n setSPEFSCR_H( tmpH );\n\n setSummarySPEFSCR();\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 567\n\n# evfsctui rT,rB\n# ISA-cmt: evfsctui - Vector Convert Floating-Point Single-Precision to Unsigned Integer\n# ISA-info: evfsctui - Form \"EVX\" Page 567 Category \"SP.FV\"\n# binutils: mytest.d: 210:\t10 20 12 94 \tevfsctui r1,r2\n:evfsctui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=660\n{\n # load saturation limit as a float\n tmpS:8 = 0x00000000FFFFFFFF;\n tmpS = int2float( tmpS );\n setSPEFSCR_L( tmpS );\n\n #\n # low section\n #\n tmpE:4 = B:4;\n tmpB:8 = float2float( tmpE );\n\n # limit to saturation\n if ( tmpB f<= tmpS ) goto ;\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # round back to integer\n tmpL:4 = trunc(round( tmpB ));\n setSPEFSCR_L( tmpL );\n\n setSummarySPEFSCR();\n\n #\n # high section\n #\n tmpE = B(4);\n tmpB = float2float( tmpE );\n\n # limit to saturation\n if ( tmpB f<= tmpS ) goto ;\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n # round back to integer\n tmpH:4 = trunc(round( tmpB ));\n setSPEFSCR_H( tmpH );\n\n setSummarySPEFSCR();\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 567\n\n# evfsctuiz rT,rB\n# ISA-cmt: evfsctuiz - Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero\n# ISA-info: evfsctuiz - Form \"EVX\" Page 567 Category \"SP.FV\"\n# binutils: mytest.d: 220:\t10 20 12 98 \tevfsctuiz r1,r2\n:evfsctuiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=664\n{\n # load saturation limit as a float\n tmpS:8 = 0x00000000FFFFFFFF;\n tmpS = int2float( tmpS );\n setSPEFSCR_L( tmpS );\n\n #\n # low section\n #\n tmpE:4 = B:4;\n tmpB:8 = float2float( tmpE );\n\n # limit to saturation\n if ( tmpB f<= tmpS ) goto ;\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpL:4 = trunc( tmpB );\n\n setSummarySPEFSCR();\n\n #\n # high section\n #\n tmpE = B(4);\n tmpB = float2float( tmpE );\n\n # limit to saturation\n if ( tmpB f<= tmpS ) goto ;\n tmpB = tmpS;\n spef_fx = 1;\n spef_finxs = 1;\n spef_fg = 1;\n\n \n\n tmpH:4 = trunc( tmpB );\n\n setSummarySPEFSCR();\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 562\n\n# evfsdiv rT,rA,rB\n# ISA-cmt: evfsdiv - Vector Floating-Point Single-Precision Divide\n# ISA-info: evfsdiv - Form \"EVX\" Page 562 Category \"SP.FV\"\n# binutils: mytest.d: 1f0:\t10 22 1a 89 \tevfsdiv r1,r2,r3\n:evfsdiv D,A,B is OP=4 & D & A & B & XOP_0_10=649\n{\n tmpAL:4 = A:4;\n tmpAH:4 = A(4);\n tmpBL:4 = B:4;\n tmpBH:4 = B(4);\n\n tmpL:4 = tmpAL f/ tmpBL;\n setSPEFSCRDivFlags_L( tmpAL, tmpBL, tmpL );\n\n tmpH:4 = tmpAH f/ tmpBH;\n setSPEFSCRDivFlags_H( tmpAH, tmpBH, tmpH );\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 562\n\n# evfsmul rT,rA,rB\n# ISA-cmt: evfsmul - Vector Floating-Point Single-Precision Multiply\n# ISA-info: evfsmul - Form \"EVX\" Page 562 Category \"SP.FV\"\n# binutils: mytest.d: 1ec:\t10 22 1a 88 \tevfsmul r1,r2,r3\n:evfsmul D,A,B is OP=4 & D & A & B & XOP_0_10=648\n{\n tmpAL:4 = A:4;\n tmpAH:4 = A(4);\n tmpBL:4 = B:4;\n tmpBH:4 = B(4);\n\n tmpL:4 = tmpAL f* tmpBL;\n setSPEFSCRMulFlags_L( tmpAL, tmpBL, tmpL );\n\n tmpH:4 = tmpAH f* tmpBH;\n setSPEFSCRMulFlags_H( tmpAH, tmpBH, tmpH );\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 561\n\n# evfsnabs rT,rA\n# ISA-cmt: evfsnabs - Vector Floating-Point Single-Precision Negative Absolute Value\n# ISA-info: evfsnabs - Form \"EVX\" Page 561 Category \"SP.FV\"\n# binutils: mytest.d: 1e4:\t10 22 02 85 \tevfsnabs r1,r2\n:evfsnabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=645\n{\n tmpAL:4 = A:4;\n tmpAH:4 = A(4);\n\n tmpL:4 = f- ( abs( tmpAL ) );\n\n tmpH:4 = f- ( abs( tmpAH ) );\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 561\n\n# evfsneg rT,rA\n# ISA-cmt: evfsneg - Vector Floating-Point Single-Precision Negate\n# ISA-info: evfsneg - Form \"EVX\" Page 561 Category \"SP.FV\"\n# binutils: mytest.d: 1e8:\t10 22 02 86 \tevfsneg r1,r2\n:evfsneg D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=646\n{\n tmpAL:4 = A:4;\n tmpAH:4 = A(4);\n\n tmpL:4 = f-( tmpAL );\n\n tmpH:4 = f-( tmpAH );\n\n # move results into upper and lower words\n tmpZ:8 = zext( tmpH );\n tmpZ = ( tmpZ << 32 ) | zext( tmpL );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 562\n\n# evfssub rT,rA,rB\n# ISA-cmt: evfssub - Vector Floating-Point Single-Precision Subtract\n# ISA-info: evfssub - Form \"EVX\" Page 562 Category \"SP.FV\"\n# binutils: mytest.d: 1dc:\t10 22 1a 81 \tevfssub r1,r2,r3\n:evfssub D,A,B is OP=4 & D & A & B & XOP_0_10=641\n{\n tmpAL:4 = A:4;\n tmpAH:4 = A(4);\n tmpBL:4 = B:4;\n tmpBH:4 = B(4);\n\n tmpL:4 = tmpAL f- tmpBL;\n setSPEFSCRSubFlags_L( tmpAL, tmpBL, tmpL );\n\n tmpH:4 = tmpAH f- tmpBH;\n setSPEFSCRSubFlags_H( tmpAH, tmpBH, tmpH );\n\n}\n\n\n# =================================================================\n# Page 565\n\n# evfststeq CRFD,rA,rB\n# ISA-cmt: evfststeq - Vector Floating-Point Single-Precision Test Equal\n# ISA-info: evfststeq - Form \"EVX\" Page 565 Category \"SP.FV\"\n# binutils: mytest.d: 230:\t10 82 1a 9e \tevfststeq cr1,r2,r3\n:evfststeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=670\n{\n tmpA:4 = A:4;\n tmpB:4 = B:4;\n tmpC:4 = A(4);\n tmpD:4 = B(4);\n\n tmpL:1 = tmpA f== tmpB;\n tmpH:1 = tmpC f== tmpD;\n\n CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL);\n}\n\n\n# =================================================================\n# Page 564\n\n# evfststgt CRFD,rA,rB\n# ISA-cmt: evfststgt - Vector Floating-Point Single-Precision Test Greater Than\n# ISA-info: evfststgt - Form \"EVX\" Page 564 Category \"SP.FV\"\n# binutils: mytest.d: 228:\t10 82 1a 9c \tevfststgt cr1,r2,r3\n:evfststgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=668\n{\n tmpA:4 = A:4;\n tmpB:4 = B:4;\n tmpC:4 = A(4);\n tmpD:4 = B(4);\n\n tmpL:1 = tmpA f> tmpB;\n tmpH:1 = tmpC f> tmpD;\n\n CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL);\n}\n\n\n# =================================================================\n# Page 565\n\n# evfststlt CRFD,rA,rB\n# ISA-cmt: evfststlt - Vector Floating-Point Single-Precision Test Less Than\n# ISA-info: evfststlt - Form \"EVX\" Page 565 Category \"SP.FV\"\n# binutils: mytest.d: 22c:\t10 82 1a 9d \tevfststlt cr1,r2,r3\n:evfststlt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=669\n{\n tmpA:4 = A:4;\n tmpB:4 = B:4;\n tmpC:4 = A(4);\n tmpD:4 = B(4);\n\n tmpL:1 = tmpA f< tmpB;\n tmpH:1 = tmpC f< tmpD;\n\n CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL);\n}\n\n\n# =================================================================\n# Page 915\n\n# evlddepx rT,rA,rB\n# Note: context is not supported\n:evlddepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=799 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n D = *:8(ea);\n}\n\n\n\n# =================================================================\n# Page 519\n\n# evlwhe RT,D(RA)\n# evlwhe rT,rA,UI\n:evlwhe D,EVUIMM_4_RAt is OP=4 & D & EVUIMM_4_RAt & XOP_0_10=785\n{\n ea:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n\n # move results into upper and lower words\n tmpZ:8 = zext( *:2(ea + 2) );\n tmpZ = ( tmpZ << 32 ) | zext( *:2(ea) );\n\n D = tmpZ;\n}\n\n\n\n# =================================================================\n# Page 519\n\n# evlwhex rT,rA,rB\n# ISA-cmt: evlwhex - Vector Load Word into Two Halfwords Even Indexed\n# ISA-info: evlwhex - Form \"EVX\" Page 519 Category \"SP\"\n# binutils: mytest.d: 238:\t10 22 1b 10 \tevlwhex r1,r2,r3\n:evlwhex D,RA_OR_ZERO,B is OP=4 & D & RA_OR_ZERO & B & XOP_0_10=784\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\n # move results into upper and lower words\n tmpZ:8 = zext( *:2(ea + 2) );\n tmpZ = ( tmpZ << 32 ) | zext( *:2(ea) );\n\n D = tmpZ;\n}\n\n\n\n# =================================================================\n# Page 521\n\n# evlwwsplat RT,D(RA)\n# evlwwsplat rT,rA,UI\n# ISA-cmt: evlwwsplat - Vector Load Word into Word and Splat\n# ISA-info: evlwwsplat - Form \"EVX\" Page 521 Category \"SP\"\n# binutils: NO-EXAMPLE - evlwwsplat\n# collides with maclhwu\n:evlwwsplat D,EVUIMM_4_RAt is OP=4 & D & EVUIMM_4_RAt & XOP_0_10=793\n{\n ea:$(REGISTER_SIZE) = EVUIMM_4_RAt;\n\n # move results into upper and lower words\n tmpZ:8 = zext( *:4(ea) );\n tmpZ = ( tmpZ << 32 ) | zext( *:4(ea) );\n\n D = tmpZ;\n}\n\n\n\n# =================================================================\n# Page 521\n\n# evlwwsplatx rT,rA,rB\n# ISA-cmt: evlwwsplatx - Vector Load Word into Word and Splat Indexed\n# ISA-info: evlwwsplatx - Form \"EVX\" Page 521 Category \"SP\"\n# binutils: mytest.d: 23c:\t10 22 1b 18 \tevlwwsplatx r1,r2,r3\n# collides with maclhwu\n:evlwwsplatx D,RA_OR_ZERO,B is OP=4 & D & RA_OR_ZERO & B & XOP_0_10=792\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\n # move results into upper and lower words\n tmpZ:8 = zext( *:4(ea) );\n tmpZ = ( tmpZ << 32 ) | zext( *:4(ea) );\n\n D = tmpZ;\n}\n\n\n# =================================================================\n# Page 541\n\n# evmwlsmiaaw rT,rA,rB\n# ISA-cmt: evmwlsmiaaw - Vector Multiply Word Low Signed\n# ISA-info: evmwlsmiaaw - Form \"EVX\" Page 541 Category \"SP\"\n# binutils: mytest.d: 248:\t10 22 1d 49 \tevmwlsmiaaw r1,r2,r3\n:evmwlsmiaaw D,A,B is OP=4 & D & A & B & XOP_0_10=1353\n{\n tmpACCL:4 = ACC:4;\n tmpACCH:4 = ACC(4);\n\n tmpAL:8 = zext( A:4 );\n tmp:4 = A(4);\n tmpAH:8 = zext( tmp );\n tmpBL:8 = zext( B:4 );\n tmp = B(4);\n tmpBH:8 = zext( tmp );\n\n temp:8 = tmpAH * tmpBH;\n tmpD:4 = tmpACCH + temp:4;\n D = ( zext( tmpD ) ) << 32;\n temp = tmpAL * tmpBL;\n tmpDL:4 = tmpACCL + temp:4;\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpDL );\n ACC = D;\n}\n\n\n# =================================================================\n# Page 541\n\n# evmwlsmianw rT,rA,rB\n# ISA-cmt: evmwlsmianw - Vector Multiply Word Low Signed\n# ISA-info: evmwlsmianw - Form \"EVX\" Page 541 Category \"SP\"\n# binutils: mytest.d: 254:\t10 22 1d c9 \tevmwlsmianw r1,r2,r3\n:evmwlsmianw D,A,B is OP=4 & D & A & B & XOP_0_10=1481\n{\n tmpACCL:4 = ACC:4;\n tmpACCH:4 = ACC(4);\n\n tmpAL:8 = zext( A:4 );\n tmp:4 = A(4);\n tmpAH:8 = zext( tmp );\n tmpBL:8 = zext( B:4 );\n tmp = B(4);\n tmpBH:8 = zext( tmp );\n\n temp:8 = tmpAH * tmpBH;\n tmpD:4 = tmpACCH - temp:4;\n D = ( zext( tmpD ) ) << 32;\n temp = tmpAL * tmpBL;\n tmpDL:4 = tmpACCL - temp:4;\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpDL );\n ACC = D;\n}\n\n\n# =================================================================\n# Page 541\n\n# evmwlssianw rT,rA,rB\n# ISA-cmt: evmwlssianw - Vector Multiply Word Low Signed\n# ISA-info: evmwlssianw - Form \"EVX\" Page 541 Category \"SP\"\n# binutils: mytest.d: 250:\t10 22 1d c1 \tevmwlssianw r1,r2,r3\n:evmwlssianw D,A,B is OP=4 & D & A & B & XOP_0_10=1473\n{\n tmpACCL:4 = ACC:4;\n tmpACCH:4 = ACC(4);\n\n tmpAL:8 = zext( A:4 );\n tmp:4 = A(4);\n tmpAH:8 = zext( tmp );\n tmpBL:8 = zext( B:4 );\n tmp = B(4);\n tmpBH:8 = zext( tmp );\n\n temp:8 = tmpAH * tmpBH;\n temp = sext( tmpACCH ) - sext( temp:4 );\n tmpOVH:1 = temp[32,1] ^ temp[31,1];\n\n # check for saturation\n if ( tmpOVH == 0 ) goto ;\n\n if ( temp[32,1] == 1 ) goto ;\n D = ( D & 0x00000000FFFFFFFF ) | 0x7FFFFFFF00000000;\n goto ;\n\n \n D = ( D & 0x00000000FFFFFFFF ) | 0x8000000000000000;\n goto ;\n\n \n D = ( D & 0x00000000FFFFFFFF ) | ( zext( temp:4 ) << 32 );\n\n \n\n\n temp = tmpAL * tmpBL;\n temp = sext( tmpACCL ) - sext( temp:4 );\n tmpOVL:1 = temp[32,1] ^ temp[31,1];\n\n # check for saturation\n if ( tmpOVL == 0 ) goto ;\n\n if ( temp[32,1] == 1 ) goto ;\n D = ( D & 0xFFFFFFFF00000000 ) | 0x000000007FFFFFFF;\n goto ;\n\n \n D = ( D & 0xFFFFFFFF00000000 ) | 0x0000000080000000;\n goto ;\n\n \n D = ( D & 0xFFFFFFFF00000000 ) | zext( temp:4 );\n\n \n\n\n ACC = D;\n\n spef_ovh = tmpOVH;\n spef_ov = tmpOVL;\n spef_sovh = spef_sovh | tmpOVH;\n spef_sov = spef_sov | tmpOVL;\n}\n\n\n\n# =================================================================\n# Page 544\n\n# evmwsmi rT,rA,rB\n# ISA-cmt: evmwsmi - Vector Multiply Word Signed\n# ISA-info: evmwsmi - Form \"EVX\" Page 544 Category \"SP\"\n# binutils: mytest.d: 244:\t10 22 1c 59 \tevmwsmi r1,r2,r3\n# collides with machhwo\n:evmwsmi D,A,B is OP=4 & D & A & B & XOP_0_10=1113\n{\n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n D = tmpAL * tmpBL;\n}\n\n\n\n# =================================================================\n# Page 544\n\n# evmwsmiaa rT,rA,rB\n# ISA-cmt: evmwsmiaa - Vector Multiply Word Signed\n# ISA-info: evmwsmiaa - Form \"EVX\" Page 544 Category \"SP\"\n# binutils: mytest.d: 24c:\t10 22 1d 59 \tevmwsmiaa r1,r2,r3\n# collides with macchwo.\n:evmwsmiaa D,A,B is OP=4 & D & A & B & XOP_0_10=1369\n{\n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n temp:8 = tmpAL * tmpBL;\n D = ACC + temp;\n ACC = D;\n}\n\n\n\n\n# =================================================================\n# Page 544\n\n# evmwsmian rT,rA,rB\n# ISA-cmt: evmwsmian - Vector Multiply Word Signed\n# ISA-info: evmwsmian - Form \"EVX\" Page 544 Category \"SP\"\n# binutils: mytest.d: 25c:\t10 22 1d d9 \tevmwsmian r1,r2,r3\n# collides with macchwso.\n:evmwsmian D,A,B is OP=4 & D & A & B & XOP_0_10=1497\n{\n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n temp:8 = tmpAL * tmpBL;\n D = ACC - temp;\n ACC = D;\n}\n\n\n\n# =================================================================\n# Page 546\n\n# evmwumi rT,rA,rB\n# ISA-cmt: evmwumi - Vector Multiply Word Unsigned\n# ISA-info: evmwumi - Form \"EVX\" Page 546 Category \"SP\"\n# binutils: mytest.d: 240:\t10 22 1c 58 \tevmwumi r1,r2,r3\n# collides with machhwo\n:evmwumi D,A,B is OP=4 & D & A & B & XOP_0_10=1112\n{\n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n temp:8 = tmpAL * tmpBL;\n D = temp;\n}\n\n# evmwumia RT,RA,RB\n# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer to Accumulator\n# evmwumia rD,rA,rB 100 01A1 1000 A=1\n:evmwumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x478 {\n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n temp:8 = tmpAL * tmpBL;\n D = temp;\n ACC = D;\n}\n\n# evmwumiaa RT,RA,RB\n# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer and Accumulate\n# evmwumiaa rD,rA,rB 101 0101 1000\n# evmwumiaa confict with macchwo\n:evmwumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x558 { \n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n temp:8 = tmpAL * tmpBL;\n D = ACC + temp;\n ACC = D;\n}\n\n# =================================================================\n# Page 547\n\n# evmwumian rT,rA,rB\n# ISA-cmt: evmwumian - Vector Multiply Word Unsigned\n# ISA-info: evmwumian - Form \"EVX\" Page 547 Category \"SP\"\n# binutils: mytest.d: 258:\t10 22 1d d8 \tevmwumian r1,r2,r3\n# collides with macchwso\n:evmwumian D,A,B is OP=4 & D & A & B & XOP_0_10=1496\n{\n tmpAL:8 = zext( A:4 );\n tmpBL:8 = zext( B:4 );\n\n temp:8 = tmpAL * tmpBL;\n D = ACC - temp;\n ACC = D;\n}\n\n\n# =================================================================\n# Page 549\n\n# evsel rT,rA,rB\n# ISA-cmt: evsel - Vector Select\n# ISA-info: evsel - Form \"EVS\" Page 549 Category \"SP\"\n# binutils: mytest.d: 1d4:\t10 22 1a 7c \tevsel r1,r2,r3,cr4\n:evsel D,A,B,BFA is OP=4 & D & A & B & XOP_3_10=79 & BFA\n{\n\n tmpAL:8 = zext( A:4 );\n tmp:4 = A(4);\n tmpAH:8 = zext( tmp );\n tmpBL:8 = zext( B:4 );\n tmp = B(4);\n tmpBH:8 = zext( tmp );\n\n tmpBFA:1 = BFA;\n\n if ( tmpBFA[3,1] == 0 ) goto ;\n D = ( D & 0x00000000FFFFFFFF ) | ( tmpAH << 32 );\n goto ;\n\n \n D = ( D & 0x00000000FFFFFFFF ) | ( tmpBH << 32 );\n\n \n\n if ( tmpBFA[2,1] == 0 ) goto ;\n D = ( D & 0xFFFFFFFF00000000 ) | tmpAL;\n goto ;\n\n \n D = ( D & 0xFFFFFFFF00000000 ) | tmpBL;\n\n \n}\n\n\n# =================================================================\n# Page 915\n\n# evstddepx rT,rA,rB\n# Note: context is not supported\n:evstddepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=927 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n *:8(ea) = D;\n}\n\n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/SPE_FloatMulAdd.sinc", "content": "\n# Additional SPE Instructions for Devices that Support VLE\n# Freescale engineering bulletin EB689\n# https://www.nxp.com/docs/en/engineering-bulletin/EB689.pdf\n\n# additional SPE instructions that are implemented on devices with an e200z3 or e200z6 core that supports VLE\n# - Vector Floating-Point Single-Precision Multiply-Add\n# - Vector Floating-Point Single-Precision Multiply-Substract\n# - Vector Floating-Point Single-Precision Negative Multiply-Add\n# - Vector Floating-Point Single-Precision Negative Multiply-Substract\n# - Floating-Point Single-Precision Multiply-Add\n# - Floating-Point Single-Precision Multiply-Substract\n# - Floating-Point Single-Precision Negative Multiply-Add\n# - Floating-Point Single-Precision Negative Multiply-Substract\n\n\n\n# evfsmadd rD,rA,rB\n# Vector Floating-Point Single-Precision Multiply-Add\n:evfsmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x282\n{\n\tlocal tmpAL:4 = A:4; local tmpAH:4 = A(4);\n\tlocal tmpBL:4 = B:4; local tmpBH:4 = B(4);\n\tlocal tmpDL:4 = D:4; local tmpDH:4 = D(4);\n\n\ttmpDL = ((tmpAL f* tmpBL) f+ tmpDL);\n\ttmpDH = ((tmpAH f* tmpBH) f+ tmpDH);\n\tD = (zext(tmpDH) << 32) | zext(tmpDL);\n}\n\n# evfsmsub rD,rA,rB\n# Vector Floating-Point Single-Precision Multiply-Substract\n:evfsmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x283\n{\n\tlocal tmpAL:4 = A:4; local tmpAH:4 = A(4);\n\tlocal tmpBL:4 = B:4; local tmpBH:4 = B(4);\n\tlocal tmpDL:4 = D:4; local tmpDH:4 = D(4);\n\n\ttmpDL = ((tmpAL f* tmpBL) f- tmpDL);\n\ttmpDH = ((tmpAH f* tmpBH) f- tmpDH);\n\tD = (zext(tmpDH) << 32) | zext(tmpDL);\n}\n\n# evfsnmadd\n# Vector Floating-Point Single-Precision Negative Multiply-Add\n:evfsnmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x28A\n{\n\tlocal tmpAL:4 = A:4; local tmpAH:4 = A(4);\n\tlocal tmpBL:4 = B:4; local tmpBH:4 = B(4);\n\tlocal tmpDL:4 = D:4; local tmpDH:4 = D(4);\n\n\ttmpDL = f- ((tmpAL f* tmpBL) f+ tmpDL);\n\ttmpDH = f- ((tmpAH f* tmpBH) f+ tmpDH);\n\tD = (zext(tmpDH) << 32) | zext(tmpDL);\n}\n\n# evfsnmsub\n# Vector Floating-Point Single-Precision Negative Multiply-Substract\n:evfsnmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x28B\n{\n\tlocal tmpAL:4 = A:4; local tmpAH:4 = A(4);\n\tlocal tmpBL:4 = B:4; local tmpBH:4 = B(4);\n\tlocal tmpDL:4 = D:4; local tmpDH:4 = D(4);\n\n\ttmpDL = f- ((tmpAL f* tmpBL) f- tmpDL);\n\ttmpDH = f- ((tmpAH f* tmpBH) f- tmpDH);\n\tD = (zext(tmpDH) << 32) | zext(tmpDL);\n}\n\n# efsmadd rD,rA,rB\n# Floating-Point Single-Precision Multiply-Add\n:efsmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C2\n{\n\tlocal lo:4 = (A:4 f* B:4) f+ D:4;\n\tD = (D & 0xFFFFFFFF00000000) | zext(lo);\n}\n\n# efsmsub rD,rA,rB\n# Floating-Point Single-Precision Multiply-Substract\n:efsmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C3\n{\n\tlocal lo:4 = (A:4 f* B:4) f- D:4;\n\tD = (D & 0xFFFFFFFF00000000) | zext(lo);\n}\n\n# efsnmadd rD,rA,rB\n# Floating-Point Single-Precision Negative Multiply-Add\n:efsnmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x2CA\n{\n\tlocal lo:4 = f- ((A:4 f* B:4) f+ D:4);\n\tD = (D & 0xFFFFFFFF00000000) | zext(lo);\n}\n\n# efsnmsub rD,rA,rB\n# Floating-Point Single-Precision Negative Multiply-Substract\n:efsnmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x2CB\n{\n\tlocal lo:4 = f- ((A:4 f* B:4) f- D:4);\n\tD = (D & 0xFFFFFFFF00000000) | zext(lo);\n}\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/Scalar_SPFP.sinc", "content": "# Based on \"EREF: A Reference for Freescale Book E and e500 Core\" document version 01/2004 Rev 2.0\n# Instructions that are specific to the (PowerPC) e500 core are implemented as auxiliary processing units (APUs)\n# Embedded Vector and Scalar Single-Precision Floating-Point APUs (SPFP APU)\n\n# There are three versions of e500 core, namely e500v1, the e500v2, and the e500mc.\n# A 64-bit evolution of the e500mc core is called e5500 core.\n# All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores.\n\n\n# =================================================================\n# Page 408\n\n# efsabs rT,rA 010 1100 0100\n#define pcodeop FloatingPointAbsoluteValue;\n:efsabs D,A is OP=4 & D & A & XOP_0_10=0x2C4 & BITS_11_15=0\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( abs( A:4 ) );\n}\n\n# efsadd rT,rA,rB 010 1100 0000\n#define pcodeop FloatingPointAdd;\n:efsadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C0\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f+ B:4 );\n setFPAddFlags( A:4, B:4, D:4 );\n}\n\n# =================================================================\n# Page 410\n\n# efscfsf rT,rB 010 1101 0011\n#define pcodeop ConvertFloatingPointFromSignedFraction;\n:efscfsf D,B is OP=4 & D & B & XOP_0_10=0x2D3 & BITS_16_20=0\n{\n # load fractional divisor as a float\n tmpA:4 = 0x80000000;\n tmpA = int2float( tmpA );\n setFPRF( tmpA );\n\n # check if negative\n if ( ( B:4 & 0x80000000 ) != 0 ) goto ;\n\n # float the fractional portion of register B\n tmpB:4 = int2float( B:4 );\n setFPRF( tmpB );\n tmpB = tmpB f/ tmpA;\n setFPDivFlags( tmpB, tmpA, tmpB );\n\n goto ;\n\n \n\n # float the fractional portion of register B, 2's complement negate\n tmpB = int2float( -( B:4 ) );\n setFPRF( tmpB );\n tmpB = tmpB f/ tmpA;\n setFPDivFlags( tmpB, tmpA, tmpB );\n\n # negate the float\n tmpB = f-( tmpB );\n setFPRF( tmpB );\n \n \n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB );\n}\n\n# efscfsi rT,rB 010 1101 0001\n#define pcodeop ConvertFloatingPointFromSignedInteger;\n:efscfsi D,B is OP=4 & D & B & XOP_0_10=0x2D1 & BITS_16_20=0\n{\n # check if negative\n if ( ( B:4 & 0x80000000 ) != 0 ) goto ;\n\n # float the integer portion of register B\n tmpB:4 = int2float( B:4 );\n setFPRF( tmpB );\n\n goto ;\n\n \n\n # float the integer portion of register B, 2's complement negate\n tmpB = int2float( -( B:4 ) );\n setFPRF( tmpB );\n\n # negate the float\n tmpB = f-( tmpB );\n setFPRF( tmpB );\n \n \n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB );\n}\n\n# efscfuf rT,rB 010 1101 0010\ndefine pcodeop ConvertFloatingPointFromUnsignedFraction;\n:efscfuf D,B is OP=4 & D & B & XOP_0_10=0x2D2 & BITS_16_20=0\n{\n # load fractional divisor as a float\n tmpA:8 = 0x0000000100000000;\n tmpA = int2float( tmpA );\n setFPRF( tmpA );\n\n # float the fractional portion of register B\n tmpB:8 = int2float( B:4 );\n setFPRF( tmpB );\n tmpB = tmpB f/ tmpA;\n setFPDivFlags( tmpB, tmpA, tmpB );\n\n tmpC:4 = float2float( tmpB );\n setFPRF( tmpC );\n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );\n}\n\n# rT,rB 010 1101 0000\n#define pcodeop ConvertFloatingPointFromUnsignedInteger;\n:efscfui D,B is OP=4 & D & B & XOP_0_10=0x2D0 & BITS_16_20=0\n{\n tmp:4 = int2float( B:4 );\n setFPRF( tmp );\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmp );\n setSummaryFPSCR();\n}\n\n# efscmpeq CRFD,rA,rB 010 1100 1110\n:efscmpeq CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2CE & BITS_21_22=0\n{\n CRFD[2,1] = A:4 f== B:4;\n}\n\n# =================================================================\n# Page 415\n\n# efscmpgt CRFD,rA,rB 010 1100 1100\n:efscmpgt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2CC & BITS_21_22=0\n{\n CRFD[2,1] = A:4 f> B:4;\n}\n\n# efscmplt CRFD,rA,rB 010 1100 1101\n:efscmplt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2CD & BITS_21_22=0\n{\n CRFD[2,1] = A:4 f< B:4;\n}\n\n# efsctsf rT,rB 010 1101 0111\n#define pcodeop ConvertFloatingPointToSignedFraction;\n:efsctsf D,B is OP=4 & D & B & XOP_0_10=0x2D7 & BITS_16_20=0\n{\n # multiply by 0x0000 0000 8000 0000 to scale the fraction up to integer range\n\n # load fractional multiplier as a float\n tmpM:8 = 0x0000000080000000;\n tmpM = int2float( tmpM );\n setFPRF( tmpM );\n\n # load saturation limit as a float\n tmpL:8 = 0x0000000080000000 - 1;\n tmpL = int2float( tmpL );\n setFPRF( tmpL );\n\n # scale the saturation limit to a fractional float\n tmpL = tmpL f/ tmpM;\n setFPDivFlags( tmpL, tmpM, tmpL );\n\n # get B float up to 64 bit width\n tmpB:8 = float2float( B:4 );\n setFPRF( tmpB );\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpL ) goto ;\n\n # set to positive saturation\n tmpB = tmpL;\n\n goto ;\n\n \n\n # check if greater than or equal to negative saturation limit\n tmpL = f-( tmpL );\n if ( tmpB f>= tmpL ) goto ;\n\n # set to negative saturation\n tmpB = tmpL;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setFPMulFlags( tmpB, tmpM, tmpB );\n\n # truncate back to signed fraction format\n tmpC:4 = trunc( tmpB );\n setFPRF( tmpB );\n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );\n}\n\n\n# efsctsi rT,rB 010 1101 0101\n#define pcodeop ConvertFloatingPointToSignedInteger;\n:efsctsi D,B is OP=4 & D & B & XOP_0_10=0x2D5 & BITS_16_20=0\n{\n # create zero float constant\n tmpA:4 = 0;\n tmpA = int2float( tmpA );\n\n # check if negative\n if ( B:4 f< tmpA ) goto ;\n\n tmpB:8 = trunc(round( B:4 ));\n setFPRF( tmpB );\n\n # limit to positive saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n\n \n\n goto ;\n\n \n\n # negate the float\n tmpB = trunc(round( f-( B:4 ) ));\n setFPRF( tmpB );\n\n # limit to negative saturation\n if ( tmpB <= 0x0000000080000000 ) goto ;\n tmpB = 0x0000000080000000;\n\n \n\n # negate the signed int\n tmpB = -( tmpB );\n\n \n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n# efsctsiz rT,rB 010 1101 1010\n#define pcodeop ConvertFloatingPointToSignedIntegerWithRoundTowardZero;\n:efsctsiz D,B is OP=4 & D & B & XOP_0_10=0x2DA & BITS_16_20=0\n{\n # create zero float constant\n tmpA:4 = 0;\n tmpA = int2float( tmpA );\n\n # check if negative\n if ( B:4 f< tmpA ) goto ;\n\n tmpB:8 = trunc( B:4 );\n setFPRF( tmpB );\n\n # limit to saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n\n \n\n goto ;\n\n \n\n # negate the float\n tmpB = trunc( f-( B:4 ) );\n setFPRF( tmpB );\n\n # limit to saturation\n if ( tmpB <= 0x0000000080000000 ) goto ;\n tmpB = 0x0000000080000000;\n\n \n\n # negate the signed int\n tmpB = -( tmpB );\n\n \n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n# =================================================================\n# Page 420\n\n# efsctuf rT,rB 010 1101 0110\n#define pcodeop ConvertFloatingPointToUnsignedFraction;\n:efsctuf D,B is OP=4 & D & B & XOP_0_10=0x2D6 & BITS_16_20=0\n{\n # multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range\n\n # load fractional multiplier as a float\n tmpM:8 = 0x0000000100000000;\n tmpM = int2float( tmpM );\n setFPRF( tmpM );\n\n # load saturation limit as a float\n tmpL:8 = 0x0000000100000000 - 1;\n tmpL = int2float( tmpL );\n setFPRF( tmpL );\n\n # scale the saturation limit to a fractional float\n tmpL = tmpL f/ tmpM;\n setFPDivFlags( tmpL, tmpM, tmpL );\n\n # get B float up to 64 bit width\n tmpB:8 = float2float( B:4 );\n setFPRF( tmpB );\n\n # check if less than or equal to positive saturation limit\n if ( tmpB f<= tmpL ) goto ;\n\n # set to saturation\n tmpB = tmpL;\n\n \n\n # scale the fractional portion up to integer side of mantissa\n tmpB = tmpB f* tmpM;\n setFPMulFlags( tmpB, tmpM, tmpB );\n\n # truncate back to integer\n tmpC:4 = trunc( tmpB );\n setFPRF( tmpC );\n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );\n}\n\n# efsctui rT,rB 010 1101 0100\n#define pcodeop ConvertFloatingPointToUnsignedInteger;\n:efsctui D,B is OP=4 & D & B & XOP_0_10=0x2D4 & BITS_16_20=0\n{\n tmpB:8 = trunc(round( B:4 ));\n setFPRF( tmpB );\n\n # limit to saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n\n \n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n# efsctuiz rT,rB 010 1101 1000\n#define pcodeop ConvertFloatingPointToUnsignedIntegerWithRoundTowardZero;\n:efsctuiz D,B is OP=4 & D & B & XOP_0_10=0x2D8 & BITS_16_20=0\n{\n tmpB:8 = trunc( B:4 );\n setFPRF( tmpB );\n\n # limit to saturation\n if ( tmpB <= 0x000000007FFFFFFF ) goto ;\n tmpB = 0x000000007FFFFFFF;\n\n \n\n setSummaryFPSCR();\n\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );\n}\n\n# efsdiv rT,rA,rB 010 1100 1001\n#define pcodeop FloatingPointDivide;\n:efsdiv D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C9\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f/ B:4 );\n setFPDivFlags( A:4, B:4, D:4 );\n}\n\n# efsmul rT,rA,rB 010 1100 1000\n#define pcodeop FloatingPointMultiply;\n:efsmul D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C8\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f* B:4 );\n setFPMulFlags( A:4, B:4, D:4 );\n}\n\n# =================================================================\n# Page 425\n\n# efsnabs rT,rA 010 1100 0101\n#define pcodeop FloatingPointNegativeAbsoluteValue;\n:efsnabs D,A is OP=4 & D & A & XOP_0_10=0x2C5 & BITS_11_15=0\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( f- ( abs( A:4 ) ) );\n setFPRF( D:4 );\n setSummaryFPSCR();\n}\n\n# efsneg rT,rA 010 1100 0110\n#define pcodeop FloatingPointNegate;\n:efsneg D,A is OP=4 & D & A & XOP_0_10=0x2C6 & BITS_11_15=0\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( f-( A:4 ) );\n setFPRF( D:4 );\n setSummaryFPSCR();\n}\n\n# efssub rT,rA,rB 010 1100 0001\n#define pcodeop FloatingPointSubtract;\n:efssub D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C1\n{\n # assign to lower word of D\n D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f- B:4 );\n setFPSubFlags( A:4, B:4, D:4 );\n setSummaryFPSCR();\n}\n\n# efststeq CRFD,rA,rB 010 1101 1110\n#define pcodeop FloatingPointTestEqual;\n:efststeq CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2DE & BITS_21_22=0\n{\n CRFD[2,1] = A:4 f== B:4;\n}\n\n# efststgt CRFD,rA,rB 010 1101 1100\n#define pcodeop FloatingPointTestGreaterThan;\n:efststgt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2DC & BITS_21_22=0\n{\n CRFD[2,1] = A:4 f> B:4;\n}\n\n# =================================================================\n# Page 430\n\n# efststlt CRFD,rA,rB 010 1101 1101\n#define pcodeop FloatingPointTestLessThan;\n:efststlt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2DD & BITS_21_22=0\n{\n CRFD[2,1] = A:4 f< B:4;\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/altivec.sinc", "content": "# altivec pcodes are stubbed out with pseudocode calls\ndefine pcodeop dataStreamStop;\ndefine pcodeop dataStreamStopAll;\ndefine pcodeop dataStreamTouch;\ndefine pcodeop dataStreamTouchSoon;\ndefine pcodeop dataStreamTouchForStore;\ndefine pcodeop dataStreamTouchForStoreTransient;\ndefine pcodeop loadVectorElementByteIndexed;\ndefine pcodeop loadVectorElementHalfWordIndexed;\ndefine pcodeop loadVectorElementWordIndexed;\ndefine pcodeop loadVectorForShiftLeft;\ndefine pcodeop loadVectorForShiftRight;\ndefine pcodeop loadVectorIndexed;\ndefine pcodeop loadVectorIndexedLRU;\ndefine pcodeop moveFromVectorStatusAndControlRegister;\ndefine pcodeop moveToVectorStatusAndControlRegister;\ndefine pcodeop storeVectorElementByteIndexed;\ndefine pcodeop storeVectorElementHalfWordIndexed;\ndefine pcodeop storeVectorElementWordIndexed;\ndefine pcodeop storeVectorIndexed;\ndefine pcodeop storeVectorIndexedLRU;\ndefine pcodeop vectorAddCarryoutUnsignedWord;\ndefine pcodeop vectorAddFloatingPoint;\ndefine pcodeop vectorAddSignedByteSaturate;\ndefine pcodeop vectorAddSignedHalfWordSaturate;\ndefine pcodeop vectorAddSignedWordSaturate;\ndefine pcodeop vectorAddUnsignedByteSaturate;\ndefine pcodeop vectorAddUnsignedHalfWordModulo;\ndefine pcodeop vectorAddUnsignedHalfWordSaturate;\ndefine pcodeop vectorAddUnsignedWordSaturate;\ndefine pcodeop vectorLogicalAnd;\ndefine pcodeop vectorLogicalAndWithComplement;\ndefine pcodeop vectorAverageSignedByte;\ndefine pcodeop vectorAverageSignedHalfWord;\ndefine pcodeop vectorAverageSignedWord;\ndefine pcodeop vectorAverageUnsignedByte;\ndefine pcodeop vectorAverageUnsignedHalfWord;\ndefine pcodeop vectorAverageUnsignedWord;\ndefine pcodeop vectorConvertFromSignedFixedPointWord;\ndefine pcodeop vectorConvertFromUnsignedFixedPointWord;\ndefine pcodeop vectorCompareBoundsFloatingPoint;\ndefine pcodeop vectorCompareEqualToFloatingPoint;\ndefine pcodeop vectorCompareEqualToUnsignedByte;\ndefine pcodeop vectorCompareEqualToUnsignedHalfWord;\ndefine pcodeop vectorCompareEqualToUnsignedWord;\ndefine pcodeop vectorCompareGreaterThanOrEqualToFloatingPoint;\ndefine pcodeop vectorCompareGreaterThanFloatingPoint;\ndefine pcodeop vectorCompareGreaterThanSignedByte;\ndefine pcodeop vectorCompareGreaterThanConditionRegisterSignedHalfWord;\ndefine pcodeop vectorCompareGreaterThanSignedWord;\ndefine pcodeop vectorCompareGreaterThanUnsignedByte;\ndefine pcodeop vectorCompareGreaterThanUnsignedHalfWord;\ndefine pcodeop vectorCompareGreaterThanUnsignedWord;\ndefine pcodeop vectorConvertToSignedFixedPointWordSaturate;\ndefine pcodeop vectorConvertToUnsignedFixedPointWordSaturate;\ndefine pcodeop vector2RaisedToTheExponentEstimateFloatingPoint;\ndefine pcodeop vectorLog2EstimateFloatingPoint;\ndefine pcodeop vectorMultiplyAddFloatingPoint;\ndefine pcodeop vectorMaximumFloatingPoint;\ndefine pcodeop vectorMaximumSignedByte;\ndefine pcodeop vectorMaximumSignedHalfWord;\ndefine pcodeop vectorMaximumSignedWord;\ndefine pcodeop vectorMaximumUnsignedByte;\ndefine pcodeop vectorMaximumUnsignedHalfWord;\ndefine pcodeop vectorMaximumUnsignedWord;\ndefine pcodeop vectorMultiplyHighAndAddSignedHalfWordSaturate;\ndefine pcodeop vectorMultiplyHighRoundAndAddSignedHalfWordSaturate;\ndefine pcodeop vectorMinimumFloatingPoint;\ndefine pcodeop vectorMinimumSignedByte;\ndefine pcodeop vectorMinimumSignedHalfWord;\ndefine pcodeop vectorMinimumSignedWord;\ndefine pcodeop vectorMinimumUnsignedByte;\ndefine pcodeop vectorMinimumUnsignedHalfWord;\ndefine pcodeop vectorMinimumUnsignedWord;\ndefine pcodeop vectorMultiplyLowAndAddUnsignedHalfWordModulo;\ndefine pcodeop vectorMergeHighByte;\ndefine pcodeop vectorMergeHighHalfWord;\ndefine pcodeop vectorMergeHighWord;\ndefine pcodeop vectorMergeLowByte;\ndefine pcodeop vectorMergeLowHalfWord;\ndefine pcodeop vectorMergeLowWord;\ndefine pcodeop vectorMultiplySumMixedSignByteModulo;\ndefine pcodeop vectorMultiplySumSignedHalfWordModulo;\ndefine pcodeop vectorMultiplySumSignedHalfWordSaturate;\ndefine pcodeop vectorMultiplySumUnsignedByteModulo;\ndefine pcodeop vectorMultiplySumUnsignedHalfWordModulo;\ndefine pcodeop vectorMultiplySumUnsignedHalfWordSaturate;\ndefine pcodeop vectorMultiplyEvenSignedByte;\ndefine pcodeop vectorMultiplyEvenSignedHalfWord;\ndefine pcodeop vectorMultiplyEvenUnsignedByte;\ndefine pcodeop vectorMultiplyEvenUnsignedHalfWord;\ndefine pcodeop vectorMultiplyOddSignedByte;\ndefine pcodeop vectorMultiplyOddSignedHalfWord;\ndefine pcodeop vectorMultiplyOddUnsignedByte;\ndefine pcodeop vectorMultiplyOddUnsignedHalfWord;\ndefine pcodeop vectorNegativeMultiplySubtractFloatingPoint;\ndefine pcodeop vectorLogicalNOR;\ndefine pcodeop vectorLogicalOR;\ndefine pcodeop vectorPackPixel32;\ndefine pcodeop vectorPackSignedHalfWordSignedSaturate;\ndefine pcodeop vectorPackSignedHalfWordUnsignedSaturate;\ndefine pcodeop vectorPackSignedWordSignedSaturate;\ndefine pcodeop vectorPackSignedWordUnsignedSaturate;\ndefine pcodeop vectorPackUnsignedHalfWordUnsignedModulo;\ndefine pcodeop vectorPackUnsignedHalfWordUnsignedSaturate;\ndefine pcodeop vectorPackUnsignedWordUnsignedModulo;\ndefine pcodeop vectorPackUnsignedWordUnsignedSaturate;\ndefine pcodeop vectorReciprocalEstimateFloatingPoint;\ndefine pcodeop vectorRoundToFloatingPointIntegerTowardMinusInfinity;\ndefine pcodeop vectorRoundToFloatingPointIntegerNearest;\ndefine pcodeop vectorRoundToFloatingPointIntegerTowardPluInfinity;\ndefine pcodeop vectorRoundToFloatingPointIntegerTowardZero;\ndefine pcodeop vectorRotateLeftIntegerByte;\ndefine pcodeop vectorRotateLeftIntegerHalfWord;\ndefine pcodeop vectorRotateLeftIntegerWord;\ndefine pcodeop vectorReciprocalSquareRootEstimateFloatingPoint;\ndefine pcodeop vectorConditionalSelect;\ndefine pcodeop vectorShiftLeft;\ndefine pcodeop vectorShiftLeftIntegerByte;\ndefine pcodeop vectorShiftLeftDoubleByOctetImmediate;\ndefine pcodeop vectorShiftLeftIntegerHalfWord;\ndefine pcodeop vectorShiftLeftByOctet;\ndefine pcodeop vectorShiftLeftIntegerWord;\ndefine pcodeop vectorSplatByte;\ndefine pcodeop vectorSplatHalfWord;\ndefine pcodeop vectorSplatImmediateSignedByte;\ndefine pcodeop vectorSplatImmediateSignedHalfWord;\ndefine pcodeop vectorSplatImmediateSignedWord;\ndefine pcodeop vectorSplatWord;\ndefine pcodeop vectorShiftRight;\ndefine pcodeop vectorShiftRightAlgebraicByte;\ndefine pcodeop vectorShiftRightAlgebraicHalfWord;\ndefine pcodeop vectorShiftRightAlgebraicWord;\ndefine pcodeop vectorShiftRightByte;\ndefine pcodeop vectorShiftRightHalfWord;\ndefine pcodeop vectorShiftRightByOctet;\ndefine pcodeop vectorShiftRightWord;\ndefine pcodeop vectorSubtractCarryoutUnsignedWord;\ndefine pcodeop vectorSubtractFloatingPoint;\ndefine pcodeop vectorSubtractSignedByteSaturate;\ndefine pcodeop vectorSubtractSignedHalfWordSaturate;\ndefine pcodeop vectorSubtractSignedWordSaturate;\ndefine pcodeop vectorSubtractUnsignedByteModulo;\ndefine pcodeop vectorSubtractUnsignedByteSaturate;\ndefine pcodeop vectorSubtractUnsignedHalfWordSaturate;\ndefine pcodeop vectorSubtractUnsignedWordModulo;\ndefine pcodeop vectorSubtractUnsignedWordSaturate;\ndefine pcodeop vectorSumAcrossSignedWordSaturate;\ndefine pcodeop vectorSumAcrossPartialSignedWordSaturate;\ndefine pcodeop vectorSumAcrossPartialSignedByteSaturate;\ndefine pcodeop vectorSumAcrossPartialSignedHalfWordSaturate;\ndefine pcodeop vectorSumAcrossPartialUnsignedByteSaturate;\ndefine pcodeop vectorUnpackHighPixel16;\ndefine pcodeop vectorUnpackHighSignedByte;\ndefine pcodeop vectorUnpackHighSignedHalfWord;\ndefine pcodeop vectorUnpackLowPixel16;\ndefine pcodeop vectorUnpackLowSignedByte;\ndefine pcodeop vectorUnpackLowSignedHalfWord;\n\n# dss\n:dss STRM\t\t\tis $(NOTVLE) & OP=31 & BIT_25=0 & BITS_23_24=0 & STRM & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=822 & Rc=0\n{\n\tdataStreamStop(STRM:1);\n}\n\n# dssall\n:dssall\tSTRM\t\tis $(NOTVLE) & OP=31 & BIT_25=1 & BITS_23_24=0 & STRM & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=822 & Rc=0\n{\n\tdataStreamStopAll(STRM:1);\n}\n\n:dst A,B,STRM\t\tis $(NOTVLE) & OP=31 & BIT_25=0 & BITS_23_24=0 & STRM & A & B & XOP_1_10=342 & Rc=0\n{\n\tdataStreamTouch(A,B,STRM:1);\n}\n\n:dstt A,B,STRM\t\tis $(NOTVLE) & OP=31 & BIT_25=1 & BITS_23_24=0 & STRM & A & B & XOP_1_10=342 & Rc=0\n{\n\tdataStreamTouchSoon(A,B,STRM:1);\n}\n\n:dstst A,B,STRM\t\tis $(NOTVLE) & OP=31 & BIT_25=0 & BITS_23_24=0 & STRM & A & B & XOP_1_10=374 & Rc=0\n{\n\tdataStreamTouchForStore(A,B,STRM:1);\n}\n\n:dststt A,B,STRM\tis $(NOTVLE) & OP=31 & BIT_25=1 & BITS_23_24=0 & STRM & A & B & XOP_1_10=374 & Rc=0\n{\n\tdataStreamTouchForStoreTransient(A,B,STRM:1);\n}\n\n:lvebx vrD,RA_OR_ZERO,B\t\tis OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=7 & Rc=0\n{\t\n\ttmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B);\n\ttmpb:1 = *[ram]:1 tmp;\n\teb:1 = tmp[0,4];\n# This looks backwards from what the manual says, but it's ok since byte 0 in the manual is MSB\n# where as for us byte 0 is LSB\t\n@if ENDIAN == \"big\"\n\teb = 0xF - eb;\n@endif\n\teb = eb * 8;\n\tvrD = (zext(tmpb) << eb);\t\n\t#vrD = loadVectorElementByteIndexed(A,B);\n}\n\n:lvehx vrD,A,B\t\tis OP=31 & vrD & A & B & XOP_1_10=39 & Rc=0\n{\t# TODO defintion\n\tvrD = loadVectorElementHalfWordIndexed(A,B);\n}\n\n:lvewx vrD,A,B\t\tis OP=31 & vrD & A & B & XOP_1_10=71 & Rc=0\n{\t# TODO definition\n\tvrD = loadVectorElementWordIndexed(A,B);\n}\n\n:lvsl vrD,A,B\t\tis OP=31 & vrD & A & B & XOP_1_10=6 & Rc=0\n{ # TODO definition\n\tvrD = loadVectorForShiftLeft(A,B);\n}\n\n:lvsr vrD,RA_OR_ZERO,B\t\tis OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=38 & Rc=0\n{ \n\ttmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B);\n\teb:1 = tmp[0,4];\n\teb = eb * 8;\n\tsrca:32=0x0001020304050607;\n\tsrcb:32=0x08090a0b0c0d0e0f;\n\tsrcc:32=0x1011121314151617;\n\tsrcd:32=0x18191a1b1c1d1e1f;\n\tsrc:32 = (srca << 192) | (srcb << 128) | (srcc << 64) | srcd;\n\tsrc = src >> eb;\n\tvrD = src:16;\n}\n\n:lvx vrD,RA_OR_ZERO,B\t\tis OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=103 & Rc=0\n{ \n#\tvrD = loadVectorIndexed(A,B);\n\tbuild RA_OR_ZERO;\n\ttmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffff0;\n\tvrD = *[ram]:16 tmp; \n}\n\n:lvxl vrD,A,B\t\tis OP=31 & vrD & A & B & XOP_1_10=359 & Rc=0\n{ # TODO definition\n\tvrD = loadVectorIndexedLRU(A,B);\n}\n\n:mfvscr vrD\t\t\tis OP=4 & vrD & vrAR=0 & vrBR=0 & XOP_1_10=770 & Rc=0\n{ # TODO definition\n\tvrD = moveFromVectorStatusAndControlRegister();\n}\n\n:mtvscr vrB\t\t\tis OP=4 & vrDR=0 & vrAR=0 & vrB & XOP_1_10=802 & Rc=0\n{ # TODO definition\n\tmoveToVectorStatusAndControlRegister(vrB);\n}\n\n:stvebx vrS,RA_OR_ZERO,B\t\tis OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=135 & Rc=0\n{ # TODO definition\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:1 EA = storeVectorElementByteIndexed(vrS,RA_OR_ZERO,B);\n}\n\n:stvehx vrS,RA_OR_ZERO,B\t\tis OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=167 & Rc=0\n{ # TODO definition\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:2 EA = storeVectorElementHalfWordIndexed(vrS,RA_OR_ZERO,B);\n}\n\n:stvewx vrS,RA_OR_ZERO,B\t\tis OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=199 & Rc=0\n{ # TODO definition\n\tEA:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffffc;\n\t*[ram]:4 EA = storeVectorElementWordIndexed(vrS,RA_OR_ZERO,B);\n}\n\n:stvx vrS,RA_OR_ZERO,B\t\tis OP=31 & vrS & B & RA_OR_ZERO & XOP_1_10=231 & Rc=0\n{\n\ttmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffff0;\n\t*[ram]:16 tmp = vrS; \n}\n\n:stvxl vrS,RA_OR_ZERO,B\t\tis OP=31 & vrS & B & RA_OR_ZERO & XOP_1_10=487 & Rc=0\n{ # TODO definition \n\ttmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffff0;\n\t*[ram]:16 tmp = vrS;\n\t# mark_as_not_likely_to_be_needed_again_anytime_soon(tmp);\n}\n\n:vaddcuw vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=384\n{ # TODO definition\n\tvrD = vectorAddCarryoutUnsignedWord(vrA,vrB);\n}\n\n:vaddfp vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=10\n{ # TODO definition\n\tvrD = vectorAddFloatingPoint(vrA,vrB);\n}\n\n:vaddsbs vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=768\n{ # TODO definition\n\tvrD = vectorAddSignedByteSaturate(vrA,vrB);\n}\n\n:vaddshs vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=832\n{ # TODO definition\n\tvrD = vectorAddSignedHalfWordSaturate(vrA,vrB);\n}\n\n:vaddsws vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=896\n{ # TODO definition\n\tvrD = vectorAddSignedWordSaturate(vrA,vrB);\n}\n\nvaddubm_part1: is vrA_8_0 & vrA_8_1 & vrA_8_2 & vrA_8_3 & vrA_8_4 & vrA_8_5 & vrA_8_6 & vrA_8_7 \n & vrB_8_0 & vrB_8_1 & vrB_8_2 & vrB_8_3 & vrB_8_4 & vrB_8_5 & vrB_8_6 & vrB_8_7\n & vrD_8_0 & vrD_8_1 & vrD_8_2 & vrD_8_3 & vrD_8_4 & vrD_8_5 & vrD_8_6 & vrD_8_7\n{\n vrD_8_0 = vrA_8_0 + vrB_8_0;\n vrD_8_1 = vrA_8_1 + vrB_8_1;\n vrD_8_2 = vrA_8_2 + vrB_8_2;\n vrD_8_3 = vrA_8_3 + vrB_8_3;\n vrD_8_4 = vrA_8_4 + vrB_8_4;\n vrD_8_5 = vrA_8_5 + vrB_8_5;\n vrD_8_6 = vrA_8_6 + vrB_8_6;\n vrD_8_7 = vrA_8_7 + vrB_8_7;\n}\n\nvaddubm_part2: is vrA_8_8 & vrA_8_9 & vrA_8_10 & vrA_8_11 & vrA_8_12 & vrA_8_13 & vrA_8_14 & vrA_8_15 \n & vrB_8_8 & vrB_8_9 & vrB_8_10 & vrB_8_11 & vrB_8_12 & vrB_8_13 & vrB_8_14 & vrB_8_15 \n & vrD_8_8 & vrD_8_9 & vrD_8_10 & vrD_8_11 & vrD_8_12 & vrD_8_13 & vrD_8_14 & vrD_8_15 \n{\n vrD_8_8 = vrA_8_8 + vrB_8_8;\n vrD_8_9 = vrA_8_9 + vrB_8_9;\n vrD_8_10 = vrA_8_10 + vrB_8_10;\n vrD_8_11 = vrA_8_11 + vrB_8_11;\n vrD_8_12 = vrA_8_12 + vrB_8_12;\n vrD_8_13 = vrA_8_13 + vrB_8_13;\n vrD_8_14 = vrA_8_14 + vrB_8_14;\n vrD_8_15 = vrA_8_15 + vrB_8_15;\n}\n\n# A bug in sleigh compiler forces us to keep the number of imported symbols less than 35 (it slows to a halt pass there), that is why we have vaddubm_part1 & vaddubm_part2\n:vaddubm vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=0 & vaddubm_part1 & vaddubm_part2\n{ \n}\n\n:vaddubs vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=512\n{ # TODO definition\n\tvrD = vectorAddUnsignedByteSaturate(vrA,vrB);\n}\n\n:vadduhm vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=64 \n & vrA_16_0 & vrA_16_1 & vrA_16_2 & vrA_16_3 & vrA_16_4 & vrA_16_5 & vrA_16_6 & vrA_16_7 \n & vrB_16_0 & vrB_16_1 & vrB_16_2 & vrB_16_3 & vrB_16_4 & vrB_16_5 & vrB_16_6 & vrB_16_7 \n & vrD_16_0 & vrD_16_1 & vrD_16_2 & vrD_16_3 & vrD_16_4 & vrD_16_5 & vrD_16_6 & vrD_16_7 \n{ \n vrD_16_0 = vrA_16_0 + vrB_16_0;\n vrD_16_1 = vrA_16_1 + vrB_16_1;\n vrD_16_2 = vrA_16_2 + vrB_16_2;\n vrD_16_3 = vrA_16_3 + vrB_16_3;\n vrD_16_4 = vrA_16_4 + vrB_16_4;\n vrD_16_5 = vrA_16_5 + vrB_16_5;\n vrD_16_6 = vrA_16_6 + vrB_16_6;\n vrD_16_7 = vrA_16_7 + vrB_16_7;\n}\n\n:vadduhs vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=576\n{ # TODO definition\n\tvrD = vectorAddUnsignedHalfWordSaturate(vrA,vrB);\n}\n\n:vadduwm vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=128\n & vrA_32_0 & vrA_32_1 & vrA_32_2 & vrA_32_3 \n & vrB_32_0 & vrB_32_1 & vrB_32_2 & vrB_32_3 \n & vrD_32_0 & vrD_32_1 & vrD_32_2 & vrD_32_3 \n{ \n vrD_32_0 = vrA_32_0 + vrB_32_0;\n vrD_32_1 = vrA_32_1 + vrB_32_1;\n vrD_32_2 = vrA_32_2 + vrB_32_2;\n vrD_32_3 = vrA_32_3 + vrB_32_3;\n}\n\n# Collides with vadduws\n# :vadduws vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=640\n# { # TODO definition\n# \tvrD = vectorAddUnsignedWordSaturate(vrA,vrB);\n# }\n\n:vand vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1028\n{ # TODO definition\n\tvrD = vectorLogicalAnd(vrA,vrB);\n}\n\n:vandc vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1092\n{ # TODO definition\n\tvrD = vectorLogicalAndWithComplement(vrA,vrB);\n}\n\n:vavgsb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1282\n{ # TODO definition\n\tvrD = vectorAverageSignedByte(vrA,vrB);\n}\n\n:vavgsh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1346\n{ # TODO definition\n\tvrD = vectorAverageSignedHalfWord(vrA,vrB);\n}\n\n:vavgsw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1410\n{ # TODO definition\n\tvrD = vectorAverageSignedWord(vrA,vrB);\n}\n\n:vavgub vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1026\n{ # TODO definition\n\tvrD = vectorAverageUnsignedByte(vrA,vrB);\n}\n\n:vavguh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1090\n{ # TODO definition\n\tvrD = vectorAverageUnsignedHalfWord(vrA,vrB);\n}\n\n:vavguw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1154\n{ # TODO definition\n\tvrD = vectorAverageUnsignedWord(vrA,vrB);\n}\n\n:vcfsx vrD,vrB,A_BITS\tis OP=4 & vrD & A_BITS & vrB & XOP_0_10=842\n{ # TODO definition\n\tvrD = vectorConvertFromSignedFixedPointWord(vrB,A_BITS:1);\n}\n\n:vcfux vrD,vrB,A_BITS\tis OP=4 & vrD & A_BITS & vrB & XOP_0_10=778\n{ # TODO definition\n\tvrD = vectorConvertFromUnsignedFixedPointWord(vrB,A_BITS:1);\n}\n\n:vcmpbfp vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=966\n{ # TODO definition\n\tvrD = vectorCompareBoundsFloatingPoint(vrA,vrB);\n}\n\n:vcmpbfp. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=966\n{ # TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareBoundsFloatingPoint(vrA,vrB);\n}\n\n:vcmpeqfp vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=198\n{ # TODO definition\n # TODO change CR6\n\tvrD = vectorCompareEqualToFloatingPoint(vrA,vrB);\n}\n\n:vcmpeqfp. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=198\n{ # TODO definition\n\tvrD = vectorCompareEqualToFloatingPoint(vrA,vrB);\n}\n\n:vcmpequb vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=6\n{ # TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareEqualToUnsignedByte(vrA,vrB);\n}\n\n:vcmpequb. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=6\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareEqualToUnsignedByte(vrA,vrB);\n}\n\n:vcmpequh vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=70\n{ # TODO definition \n\t# TODO change CR6\n\tvrD = vectorCompareEqualToUnsignedHalfWord(vrA,vrB);\n}\n\n:vcmpequh. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=70\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareEqualToUnsignedHalfWord(vrA,vrB);\n}\n\n:vcmpequw vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=134\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareEqualToUnsignedWord(vrA,vrB);\n}\n\n:vcmpequw. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=134\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareEqualToUnsignedWord(vrA,vrB);\n}\n\n:vcmpgefp vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=454\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanOrEqualToFloatingPoint(vrA,vrB);\n}\n\n:vcmpgefp. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=454\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanOrEqualToFloatingPoint(vrA,vrB);\n}\n\n:vcmpgtfp vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=710\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanFloatingPoint(vrA,vrB);\n}\n\n:vcmpgtfp. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=710\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanFloatingPoint(vrA,vrB);\n}\n\n:vcmpgtsb vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=774\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanSignedByte(vrA,vrB);\n}\n\n:vcmpgtsb. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=774\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanSignedByte(vrA,vrB);\n}\n\n:vcmpgtsh vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=838\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanConditionRegisterSignedHalfWord(vrA,vrB);\n}\n\n:vcmpgtsh. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=838\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanConditionRegisterSignedHalfWord(vrA,vrB);\n}\n\n:vcmpgtsw vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=902\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanSignedWord(vrA,vrB);\n}\n\n:vcmpgtsw. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=902\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanSignedWord(vrA,vrB);\n}\n\n:vcmpgtub vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=518\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanUnsignedByte(vrA,vrB);\n}\n\n:vcmpgtub. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=518\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanUnsignedByte(vrA,vrB);\n}\n\n:vcmpgtuh vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=582\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanUnsignedHalfWord(vrA,vrB);\n}\n\n:vcmpgtuh. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=582\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanUnsignedHalfWord(vrA,vrB);\n}\n\n:vcmpgtuw vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=646\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanUnsignedWord(vrA,vrB);\n}\n\n:vcmpgtuw. vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=646\n{\t# TODO definition\n\t# TODO change CR6\n\tvrD = vectorCompareGreaterThanUnsignedWord(vrA,vrB);\n}\n\n:vctsxs vrD,vrB,A_BITS\tis OP=4 & vrD & A_BITS & vrB & XOP_0_10=970\n{\t# TODO definition\n\tvrD = vectorConvertToSignedFixedPointWordSaturate(vrB,A_BITS:1);\n}\n\n:vctuxs vrD,vrB,A_BITS\tis OP=4 & vrD & A_BITS & vrB & XOP_0_10=906\n{\t# TODO definition\n\tvrD = vectorConvertToUnsignedFixedPointWordSaturate(vrB,A_BITS:1);\n}\n\n:vexptefp vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=394\n{\t# TODO definition\n\tvrD = vector2RaisedToTheExponentEstimateFloatingPoint(vrB);\n}\n\n:vlogefp vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=458\n{\t# TODO definition\n\tvrD = vectorLog2EstimateFloatingPoint(vrB);\n}\n\n:vmaddfp vrD,vrA,vrC,vrB\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=46\n{\t# TODO definition\n\tvrD = vectorMultiplyAddFloatingPoint(vrA,vrC,vrB);\n}\n\n:vmaxfp vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1034\n{\t# TODO definition\n\tvrD = vectorMaximumFloatingPoint(vrA,vrB);\n}\n\n:vmaxsb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=258\n{\t# TODO definition\n\tvrD = vectorMaximumSignedByte(vrA,vrB);\n}\n\n:vmaxsh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=322\n{\t# TODO definition\n\tvrD = vectorMaximumSignedHalfWord(vrA,vrB);\n}\n\n:vmaxsw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=386\n{\t# TODO definition\n\tvrD = vectorMaximumSignedWord(vrA,vrB);\n}\n\n:vmaxub vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=2\n{\t# TODO definition\n\tvrD = vectorMaximumUnsignedByte(vrA,vrB);\n}\n\n:vmaxuh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=66\n{\t# TODO definition\n\tvrD = vectorMaximumUnsignedHalfWord(vrA,vrB);\n}\n\n:vmaxuw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=130\n{\t# TODO definition\n\tvrD = vectorMaximumUnsignedWord(vrA,vrB);\n}\n\n:vmhaddshs vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=32\n{\t# TODO definition\n\tvrD = vectorMultiplyHighAndAddSignedHalfWordSaturate(vrA,vrB,vrC);\n}\n\n:vmhraddshs vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=33\n{\t# TODO definition\n\tvrD = vectorMultiplyHighRoundAndAddSignedHalfWordSaturate(vrA,vrB,vrC);\n}\n\n:vminfp vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1098\n{\t# TODO definition\n\tvrD = vectorMinimumFloatingPoint(vrA,vrB);\n}\n\n:vminsb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=770\n{\t# TODO definition\n\tvrD = vectorMinimumSignedByte(vrA,vrB);\n}\n\n:vminsh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=834\n{\t# TODO definition\n\tvrD = vectorMinimumSignedHalfWord(vrA,vrB);\n}\n\n:vminsw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=898\n{\t# TODO definition\n\tvrD = vectorMinimumSignedWord(vrA,vrB);\n}\n\n:vminub vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=514\n{\t# TODO definition\n\tvrD = vectorMinimumUnsignedByte(vrA,vrB);\n}\n\n:vminuh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=578\n{\t# TODO definition\n\tvrD = vectorMinimumUnsignedHalfWord(vrA,vrB);\n}\n\n:vminuw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=642\n{\t# TODO definition\n\tvrD = vectorMinimumUnsignedWord(vrA,vrB);\n}\n\n:vmladduhm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=34\n{\t# TODO definition\n\tvrD = vectorMultiplyLowAndAddUnsignedHalfWordModulo(vrA,vrB,vrC);\n}\n\n:vmrghb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=12\n{\t# TODO definition\n\tvrD = vectorMergeHighByte(vrA,vrB);\n}\n\n:vmrghh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=76\n{\t# TODO definition\n\tvrD = vectorMergeHighHalfWord(vrA,vrB);\n}\n\n:vmrghw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=140\n{\t# TODO definition\n\tvrD = vectorMergeHighWord(vrA,vrB);\n}\n\n:vmrglb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=268\n{\t# TODO definition\n\tvrD = vectorMergeLowByte(vrA,vrB);\n}\n\n:vmrglh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=332\n{\t# TODO definition\n\tvrD = vectorMergeLowHalfWord(vrA,vrB);\n}\n\n:vmrglw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=396\n{\t# TODO definition\n\tvrD = vectorMergeLowWord(vrA,vrB);\n}\n\n:vmsummbm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=37\n{\t# TODO definition\n\tvrD = vectorMultiplySumMixedSignByteModulo(vrA,vrB,vrC);\n}\n\n:vmsumshm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=40\n{\t# TODO definition\n\tvrD = vectorMultiplySumSignedHalfWordModulo(vrA,vrB,vrC);\n}\n\n:vmsumshs vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=41\n{\t# TODO definition\n\tvrD = vectorMultiplySumSignedHalfWordSaturate(vrA,vrB,vrC);\n}\n\n:vmsumubm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=36\n{\t# TODO definition\n\tvrD = vectorMultiplySumUnsignedByteModulo(vrA,vrB,vrC);\n}\n\n:vmsumuhm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=38\n{\t# TODO definition\n\tvrD = vectorMultiplySumUnsignedHalfWordModulo(vrA,vrB,vrC);\n}\n\n:vmsumuhs vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=39\n{\t# TODO definition\n\tvrD = vectorMultiplySumUnsignedHalfWordSaturate(vrA,vrB,vrC);\n}\n\n:vmulesb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=776\n{\t# TODO definition\n\tvrD = vectorMultiplyEvenSignedByte(vrA,vrB);\n}\n\n:vmulesh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=840\n{\t# TODO definition\n\tvrD = vectorMultiplyEvenSignedHalfWord(vrA,vrB);\n}\n\n:vmuleub vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=520\n{\t# TODO definition\n\tvrD = vectorMultiplyEvenUnsignedByte(vrA,vrB);\n}\n\n:vmuleuh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=584\n{\t# TODO definition\n\tvrD = vectorMultiplyEvenUnsignedHalfWord(vrA,vrB);\n}\n\n:vmulosb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=264\n{\t# TODO definition\n\tvrD = vectorMultiplyOddSignedByte(vrA,vrB);\t\n}\n\n:vmulosh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=328\n{\t# TODO definition\n\tvrD = vectorMultiplyOddSignedHalfWord(vrA,vrB);\n}\n\n:vmuloub vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=8\n{\t# TODO definition\n\tvrD = vectorMultiplyOddUnsignedByte(vrA,vrB);\n}\n\n:vmulouh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=72\n{\t# TODO definition\n\tvrD = vectorMultiplyOddUnsignedHalfWord(vrA,vrB);\n}\n\n:vnmsubfp vrD,vrA,vrC,vrB\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=47\n{\t# TODO definition\n\tvrD = vectorNegativeMultiplySubtractFloatingPoint(vrA,vrC,vrB);\n}\n\n:vnor vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1284\n{\t\n\tvrD = ~(vrA | vrB);\n}\n\n:vor vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1156\n{\t\n\tvrD = vrA | vrB;\n}\n\n:vperm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=43\n{\t\n#\ttmp:32 = (zext(vrA) << 128) | zext(vrB);\n#\ttmp2:16 = 0;\n#\ttmp3:32 = 0;\n#\tcnt:1 = 15;\n#\t\n#\ttmp2 = (vrC >> (cnt * 8)) & 0x1F;\n#\ttmp3 = tmp >> ((31 - tmp2) * 8);\n#\tvrD = vrD << 8;\n#\tvrD[0,8] = tmp3[0,8];\n#\tif (cnt == 0) goto ;\n#\tcnt = cnt - 1;\n#\tgoto ;\n#\t\n\tvrD = vectorPermute(vrA,vrB,vrC);\n}\n\n:vpkpx vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=782\n{\t# TODO definition\n\tvrD = vectorPackPixel32(vrA,vrB);\n}\n\n:vpkshss vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=398\n{\t# TODO definition\n\tvrD = vectorPackSignedHalfWordSignedSaturate(vrA,vrB);\n}\n\n:vpkshus vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=270\n{\t# TODO definition\n\tvrD = vectorPackSignedHalfWordUnsignedSaturate(vrA,vrB);\n}\n\n:vpkswss vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=462\n{\t# TODO definition\n\tvrD = vectorPackSignedWordSignedSaturate(vrA,vrB);\n}\n\n:vpkswus vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=334\n{\t# TODO definition\n\tvrD = vectorPackSignedWordUnsignedSaturate(vrA,vrB);\n}\n\n:vpkuhum vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=14\n{\t# TODO definition\n\tvrD = vectorPackUnsignedHalfWordUnsignedModulo(vrA,vrB);\n}\n\n:vpkuhus vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=142\n{\t# TODO definitionXTF = \n\tvrD = vectorPackUnsignedHalfWordUnsignedSaturate(vrA,vrB);\n}\n\n:vpkuwum vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=78\n{\t# TODO definition\n\tvrD = vectorPackUnsignedWordUnsignedModulo(vrA,vrB);\n}\n\n:vpkuwus vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=206\n{\t# TODO definition\n\tvrD = vectorPackUnsignedWordUnsignedSaturate(vrA,vrB);\n}\n\n:vrefp vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=266\n{\t# TODO definition\n\tvrD = vectorReciprocalEstimateFloatingPoint(vrB);\n}\n\n:vrfim vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=714\n{\t# TODO definition\n\tvrD = vectorRoundToFloatingPointIntegerTowardMinusInfinity(vrB);\n}\n\n:vrfin vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=522\n{\t# TODO definition\n\tvrD = vectorRoundToFloatingPointIntegerNearest(vrB);\n}\n\n:vrfip vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=650\n{\t# TODO definition\n\tvrD = vectorRoundToFloatingPointIntegerTowardPluInfinity(vrB);\n}\n\n:vrfiz vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=586\n{\t# TODO definition\n\tvrD = vectorRoundToFloatingPointIntegerTowardZero(vrB);\n}\n\n:vrlb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=4\n{\t# TODO definition\n\tvrD = vectorRotateLeftIntegerByte(vrA,vrB);\n}\n\n:vrlh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=68\n{\t# TODO definition\n\tvrD = vectorRotateLeftIntegerHalfWord(vrA,vrB);\n}\n\n:vrlw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=132\n{\t# TODO definition\n\tvrD = vectorRotateLeftIntegerWord(vrA,vrB);\n}\n\n:vrsqrtefp vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=330\n{\t# TODO definition\n\tvrD = vectorReciprocalSquareRootEstimateFloatingPoint(vrB);\n}\n\n:vsel vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=42\n{\t# TODO definition\n\tvrD = vectorConditionalSelect(vrA,vrB,vrC);\n}\n\n:vsl vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=452\n{\t# TODO definition\n\tvrD = vectorShiftLeft(vrA,vrB);\n}\n\n:vslb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=260\n{\t# TODO definition\n\tvrD = vectorShiftLeftIntegerByte(vrA,vrB);\n}\n\n:vsldoi vrD,vrA,vrB,SHB\t\tis OP=4 & vrD & vrA & vrB & BIT_10=0 & SHB & XOP_0_5=44\n{\n\ttmp:32 = (zext(vrA) << 128) | zext(vrB);\n\ttmp = tmp << (SHB:1 * 8);\n\tvrD = tmp[128,128];\n}\n\n:vslh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=324\n{\t# TODO definition\n\tvrD = vectorShiftLeftIntegerHalfWord(vrA,vrB);\n}\n\n:vslo vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1036\n{\t# TODO definition\n\tvrD = vectorShiftLeftByOctet(vrA,vrB);\n}\n\n:vslw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=388\n{\t# TODO definition\n\tvrD = vectorShiftLeftIntegerWord(vrA,vrB);\n}\n\n:vspltb vrD,vrB,UIMB\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=524\n{\n\ttmp:1 = (0xF - UIMB) * 8;\n\ttmpa:16 = (vrB >> tmp) & 0xFF;\n\tvrD = tmpa | (tmpa << 8) | (tmpa << 16) | (tmpa << 24) | (tmpa << 32) | (tmpa << 40) | (tmpa << 48) | (tmpa << 56);\n\tvrD = vrD | (tmpa << 64) | (tmpa << 72) | (tmpa << 80) | (tmpa << 88) | (tmpa << 96) | (tmpa << 104) | (tmpa << 112) | (tmpa << 120);\t\n}\n\n:vsplth vrD,vrB,UIMH\tis OP=4 & vrD & BITS_19_20=0 & UIMH & vrB & XOP_0_10=588\n{\t# TODO definition\n\tvrD = vectorSplatHalfWord(vrB,UIMH:1);\n}\n\n:vspltisb vrD,A_BITSS\tis OP=4 & vrD & A_BITSS & B_BITS=0 & XOP_0_10=780\n{\t# TODO definition\n\tvrD = vectorSplatImmediateSignedByte(A_BITSS:1);\n}\n\n:vspltish vrD,A_BITSS\tis OP=4 & vrD & A_BITSS & B_BITS=0 & XOP_0_10=844\n{\t# TODO definition\n\tvrD = vectorSplatImmediateSignedHalfWord(A_BITSS:1);\n}\n\n:vspltisw vrD,A_BITSS\tis OP=4 & vrD & A_BITSS & B_BITS=0 & XOP_0_10=908\n{\n\ttmpw:4 = sext(A_BITSS:1);\n\ttmp:16 = zext(tmpw);\n\tvrD = (tmp) | (tmp << 32) | (tmp << 64) | (tmp << 96);\n}\n\n# A better way to do this would be to make a subtable to interpret\n# UIMW into the corresponding subword, then assign the subregisters of vrD\n# to that value.\n:vspltw vrD,vrB,UIMW\tis OP=4 & vrD & vrB & BITS_18_20=0 & UIMW & XOP_0_10=652\n{\n\tlocal b = (3 - UIMW) * 32;\n\tlocal tmp:16 = (vrB >> b) & 0xffffffff;\n\tvrD = (tmp) | (tmp << 32) | (tmp << 64) | (tmp << 96);\n}\n\n:vsr vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=708\n{\t# TODO definition\n\tvrD = vectorShiftRight(vrA,vrB);\n}\n\n:vsrab vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=772\n{\t# TODO definition\n\tvrD = vectorShiftRightAlgebraicByte(vrA,vrB);\n}\n\n:vsrah vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=836\n{\t# TODO definition\n\tvrD = vectorShiftRightAlgebraicHalfWord(vrA,vrB);\n}\n\n:vsraw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=900\n{\t# TODO definition\n\tvrD = vectorShiftRightAlgebraicWord(vrA,vrB);\n}\n\n:vsrb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=516\n{\t# TODO definition\n\tvrD = vectorShiftRightByte(vrA,vrB);\n}\n\n:vsrh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=580\n{\t# TODO definition\n\tvrD = vectorShiftRightHalfWord(vrA,vrB);\n}\n\n:vsro vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1100\n{\t# TODO definition\n\tvrD = vectorShiftRightByOctet(vrA,vrB);\n}\n\n:vsrw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=644\n{\t# TODO definition\n\tvrD = vectorShiftRightWord(vrA,vrB);\n}\n\n:vsubcuw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1408\n{\t# TODO definition\n\tvrD = vectorSubtractCarryoutUnsignedWord(vrA,vrB);\n}\n\n:vsubfp vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=74\n{\t# TODO definition\n\tvrD = vectorSubtractFloatingPoint(vrA,vrB);\n}\n\n:vsubsbs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1792\n{\t# TODO definition\n\tvrD = vectorSubtractSignedByteSaturate(vrA,vrB);\n}\n\n:vsubshs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1856\n{\t# TODO definition\n\tvrD = vectorSubtractSignedHalfWordSaturate(vrA,vrB);\n}\n\n:vsubsws vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1920\n{\t# TODO definition\n\tvrD = vectorSubtractSignedWordSaturate(vrA,vrB);\n}\n\n:vsububm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1024\n{\t# TODO definition\n\tvrD = vectorSubtractUnsignedByteModulo(vrA,vrB);\n}\n\n:vsububs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1536\n{\t# TODO definition\n\tvrD = vectorSubtractUnsignedByteSaturate(vrA,vrB);\n}\n\n:vsubuhm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1088 \n & vrA_16_0 & vrA_16_1 & vrA_16_2 & vrA_16_3 & vrA_16_4 & vrA_16_5 & vrA_16_6 & vrA_16_7 \n & vrB_16_0 & vrB_16_1 & vrB_16_2 & vrB_16_3 & vrB_16_4 & vrB_16_5 & vrB_16_6 & vrB_16_7 \n & vrD_16_0 & vrD_16_1 & vrD_16_2 & vrD_16_3 & vrD_16_4 & vrD_16_5 & vrD_16_6 & vrD_16_7 \n{\t\n vrD_16_0 = vrA_16_0 - vrB_16_0;\n vrD_16_1 = vrA_16_1 - vrB_16_1;\n vrD_16_2 = vrA_16_2 - vrB_16_2;\n vrD_16_3 = vrA_16_3 - vrB_16_3;\n vrD_16_4 = vrA_16_4 - vrB_16_4;\n vrD_16_5 = vrA_16_5 - vrB_16_5;\n vrD_16_6 = vrA_16_6 - vrB_16_6;\n vrD_16_7 = vrA_16_7 - vrB_16_7;\n}\n\n:vsubuhs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1600\n{\t# TODO definition\n\tvrD = vectorSubtractUnsignedHalfWordSaturate(vrA,vrB);\n}\n\n:vsubuwm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1152\n{\t# TODO definition\n\tvrD = vectorSubtractUnsignedWordModulo(vrA,vrB);\n}\n\n:vsubuws vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1664\n{\t# TODO definition\n\tvrD = vectorSubtractUnsignedWordSaturate(vrA,vrB);\n}\n\n:vsumsws vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1928\n{\t# TODO definition\n\tvrD = vectorSumAcrossSignedWordSaturate(vrA,vrB);\n}\n\n:vsum2sws vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1672\n{\t# TODO definition\n\tvrD = vectorSumAcrossPartialSignedWordSaturate(vrA,vrB);\n}\n\n:vsum4sbs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1800\n{\t# TODO definition\n\tvrD = vectorSumAcrossPartialSignedByteSaturate(vrA,vrB);\t\n}\n\n:vsum4shs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1608\n{\t# TODO definition\n\tvrD = vectorSumAcrossPartialSignedHalfWordSaturate(vrA,vrB);\t\n}\n\n:vsum4ubs vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1544\n{\t# TODO definition\n\tvrD = vectorSumAcrossPartialUnsignedByteSaturate(vrA,vrB);\t\n}\n\n:vupkhpx vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=846\n{\t# TODO definition\n\tvrD = vectorUnpackHighPixel16(vrB);\n}\n\n:vupkhsb vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=526\n{\t# TODO definition\n\tvrD = vectorUnpackHighSignedByte(vrB);\n}\n\n:vupkhsh vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=590\n{\t# TODO definition\n\tvrD = vectorUnpackHighSignedHalfWord(vrB);\n}\n\n:vupklpx vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=974\n{\t# TODO definition\n\tvrD = vectorUnpackLowPixel16(vrB);\n}\n\n:vupklsb vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=654\n{\t# TODO definition\n\tvrD = vectorUnpackLowSignedByte(vrB);\n}\n\n:vupklsh vrD,vrB\t\tis OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=718\n{\t# TODO definition\n\tvrD = vectorUnpackLowSignedHalfWord(vrB);\n}\n\n:vxor vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1220\n{\t\n\tvrD = vrA ^ vrB;\n}\n\n\ndefine pcodeop altv207_1;\ndefine pcodeop altv207_2;\ndefine pcodeop altv207_3;\ndefine pcodeop altv207_4;\ndefine pcodeop altv207_5;\ndefine pcodeop altv207_6;\ndefine pcodeop altv207_7;\ndefine pcodeop altv207_8;\ndefine pcodeop altv207_9;\ndefine pcodeop altv207_10;\ndefine pcodeop altv207_11;\ndefine pcodeop altv207_12;\ndefine pcodeop altv207_13;\ndefine pcodeop altv207_14;\ndefine pcodeop altv207_15;\ndefine pcodeop altv207_16;\ndefine pcodeop altv207_17;\ndefine pcodeop altv207_18;\ndefine pcodeop altv207_19;\ndefine pcodeop altv207_20;\ndefine pcodeop altv207_21;\ndefine pcodeop altv207_22;\ndefine pcodeop altv207_23;\ndefine pcodeop altv207_24;\ndefine pcodeop altv207_25;\ndefine pcodeop altv207_26;\ndefine pcodeop altv207_27;\ndefine pcodeop altv207_28;\ndefine pcodeop altv207_29;\ndefine pcodeop altv207_30;\ndefine pcodeop altv207_31;\ndefine pcodeop altv207_32;\ndefine pcodeop altv207_33;\ndefine pcodeop altv207_34;\ndefine pcodeop altv207_35;\ndefine pcodeop altv207_36;\ndefine pcodeop altv207_37;\ndefine pcodeop altv207_38;\ndefine pcodeop altv207_39;\ndefine pcodeop altv207_40;\ndefine pcodeop altv207_41;\ndefine pcodeop altv207_42;\ndefine pcodeop altv207_43;\ndefine pcodeop altv207_44;\ndefine pcodeop altv207_45;\ndefine pcodeop altv207_46;\ndefine pcodeop altv207_47;\ndefine pcodeop altv207_48;\ndefine pcodeop altv207_49;\ndefine pcodeop altv207_50;\ndefine pcodeop altv207_51;\ndefine pcodeop altv207_52;\ndefine pcodeop altv207_53;\ndefine pcodeop altv207_54;\ndefine pcodeop altv207_55;\ndefine pcodeop altv207_56;\ndefine pcodeop altv207_57;\ndefine pcodeop altv207_58;\ndefine pcodeop altv207_59;\ndefine pcodeop altv207_60;\ndefine pcodeop altv207_61;\ndefine pcodeop altv207_62;\ndefine pcodeop altv207_63;\ndefine pcodeop altv207_64;\ndefine pcodeop altv207_65;\n\ndefine pcodeop altv300_1;\ndefine pcodeop altv300_2;\ndefine pcodeop altv300_3;\ndefine pcodeop altv300_4;\ndefine pcodeop altv300_5;\ndefine pcodeop altv300_6;\ndefine pcodeop altv300_7;\ndefine pcodeop altv300_8;\ndefine pcodeop altv300_9;\ndefine pcodeop altv300_10;\ndefine pcodeop altv300_11;\ndefine pcodeop altv300_12;\ndefine pcodeop altv300_13;\ndefine pcodeop altv300_14;\ndefine pcodeop altv300_15;\ndefine pcodeop altv300_16;\ndefine pcodeop altv300_17;\ndefine pcodeop altv300_18;\ndefine pcodeop altv300_19;\ndefine pcodeop altv300_20;\ndefine pcodeop altv300_21;\ndefine pcodeop altv300_22;\ndefine pcodeop altv300_23;\ndefine pcodeop altv300_24;\ndefine pcodeop altv300_25;\ndefine pcodeop altv300_26;\ndefine pcodeop altv300_27;\ndefine pcodeop altv300_28;\ndefine pcodeop altv300_29;\ndefine pcodeop altv300_30;\ndefine pcodeop altv300_31;\ndefine pcodeop altv300_32;\ndefine pcodeop altv300_33;\ndefine pcodeop altv300_34;\ndefine pcodeop altv300_35;\ndefine pcodeop altv300_36;\ndefine pcodeop altv300_41;\ndefine pcodeop altv300_42;\ndefine pcodeop altv300_43;\ndefine pcodeop altv300_44;\ndefine pcodeop altv300_45;\ndefine pcodeop altv300_46;\ndefine pcodeop altv300_47;\ndefine pcodeop altv300_48;\ndefine pcodeop altv300_49;\ndefine pcodeop altv300_50;\ndefine pcodeop altv300_51;\ndefine pcodeop altv300_52;\ndefine pcodeop altv300_53;\ndefine pcodeop altv300_54;\ndefine pcodeop altv300_55;\ndefine pcodeop altv300_56;\ndefine pcodeop altv300_57;\ndefine pcodeop altv300_58;\ndefine pcodeop altv300_59;\ndefine pcodeop altv300_60;\ndefine pcodeop altv300_61;\ndefine pcodeop altv300_62;\ndefine pcodeop altv300_63;\ndefine pcodeop altv300_64;\ndefine pcodeop altv300_65;\ndefine pcodeop altv300_66;\ndefine pcodeop altv300_67;\ndefine pcodeop altv300_68;\ndefine pcodeop altv300_69;\ndefine pcodeop altv300_70;\ndefine pcodeop altv300_71;\n\n#################\n# 2.07 additions\n:bcdadd. vrD,vrA,vrB,PS\t\tis OP=4 & BIT_10=1 & XOP_0_8=1 & vrA & vrB & vrD & PS {\n\tvrD = altv207_64(vrA,vrB,PS:1);\n}\n\n:bcdsub. vrD,vrA,vrB,PS\t\tis OP=4 & BIT_10=1 & XOP_0_8=65 & vrA & vrB & vrD & PS {\n\tvrD = altv207_65(vrA,vrB,PS:1);\t\n}\n\n\n:vaddcuq vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=320 {\n\tvrD = altv207_1(vrA,vrB);\n}\n\n:vaddecuq vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=61 {\n\tvrD = altv207_2(vrA,vrB,vrC);\n}\n\n:vaddeuqm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=60 {\n\tvrD = altv207_3(vrA,vrB,vrC);\n}\n\n:vaddudm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=192 {\n\tvrD = altv207_4(vrA,vrB);\n}\n\n:vadduqm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=256 {\n\tvrD = altv207_5(vrA,vrB);\n}\n\n:vbpermq vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1356 {\n\tvrD = altv207_6(vrA,vrB);\n}\n\n:vcipher vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1288 {\n\tvrD = altv207_7(vrA,vrB);\n}\n\n:vcipherlast vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1289 {\n\tvrD = altv207_8(vrA,vrB);\n}\n\n:vclzb vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1794 {\n\tvrD = altv207_9(vrB);\n}\n\n:vclzd vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1986 {\n\tvrD = altv207_10(vrB);\n}\n\n:vclzh vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1858 {\n\tvrD = altv207_11(vrB);\n}\n\n:vclzw vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1922 {\n\tvrD = altv207_12(vrB);\n}\n\n:vcmpequd vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=199 {\n\tvrD = altv207_13(vrA,vrB);\n}\n\n:vcmpequd. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=199 {\n\tvrD = altv207_14(vrA,vrB);\n}\n\n:vcmpgtsd vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=967 {\n\tvrD = altv207_15(vrA,vrB);\n}\n\n:vcmpgtsd. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=967 {\n\tvrD = altv207_16(vrA,vrB);\n}\n\n:vcmpgtud vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=711 {\n\tvrD = altv207_17(vrA,vrB);\n}\n\n:vcmpgtud. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=711 {\n\tvrD = altv207_18(vrA,vrB);\n}\n\n:veqv vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1668 {\n\tvrD = altv207_19(vrA,vrB);\n}\n\n:vgbbd vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1292 {\n\tvrD = altv207_20(vrB);\n}\n\n:vmaxsd vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=450 {\n\tvrD = altv207_21(vrA,vrB);\n}\n\n:vmaxud vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=194 {\n\tvrD = altv207_22(vrA,vrB);\n}\n\n:vminsd vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=962 {\n\tvrD = altv207_23(vrA,vrB);\n}\n\n:vminud vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=706 {\n\taltv207_24(vrA,vrB);\n}\n\n:vmrgew vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1932 {\n\tvrD = altv207_25(vrA,vrB);\n}\n\n:vmrgow vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1676 {\n\tvrD = altv207_26(vrA,vrB);\n}\n\n:vmulesw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=904 {\n\tvrD = altv207_27(vrA,vrB);\n}\n\n:vmuleuw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=648 {\n\tvrD = altv207_28(vrA,vrB);\n}\n\n:vmulosw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=392 {\n\tvrD = altv207_29(vrA,vrB);\n}\n\n:vmulouw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=136 {\n\tvrD = altv207_30(vrA,vrB);\n}\n\n:vmuluwm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=137 {\n\tvrD = altv207_31(vrA,vrB);\n}\n\n:vnand vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1412 {\n\tvrD = altv207_32(vrA,vrB);\n}\n\n:vncipher vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1352 {\n\tvrD = altv207_33(vrA,vrB);\n}\n\n:vncipherlast vrD,vrA,vrB\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1353 {\n\tvrD = altv207_34(vrA,vrB);\n}\n\n:vorc vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1348 {\n\tvrD = altv207_35(vrA,vrB);\n}\n\n:vpermxor vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=45 {\n\tvrD = altv207_36(vrA,vrB,vrC);\n}\n\n:vpksdss vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1486 {\n\tvrD = altv207_37(vrA,vrB);\n}\n\n:vpksdus vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1358 {\n\tvrD = altv207_38(vrA,vrB);\n}\n\n:vpkudum vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1102 {\n\tvrD = altv207_39(vrA,vrB);\n}\n\n:vpkudus vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1230 {\n\tvrD = altv207_41(vrA,vrB);\n}\n\n:vpmsumb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1032 {\n\tvrD = altv207_42(vrA,vrB);\n}\n\n:vpmsumd vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1224 {\n\tvrD = altv207_43(vrA,vrB);\n}\n\n:vpmsumh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1096 {\n\tvrD = altv207_44(vrA,vrB);\n}\n\n:vpmsumw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1160 {\n\tvrD = altv207_45(vrA,vrB);\n}\n\n:vpopcntb vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1795 {\n\tvrD = altv207_46(vrB);\n}\n\n:vpopcntd vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1987 {\n\tvrD = altv207_47(vrB);\n}\n\n:vpopcnth vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1859 {\n\tvrD = altv207_48(vrB);\n}\n\n:vpopcntw vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1923 {\n\tvrD = altv207_49(vrB);\n}\n\n:vrld vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=196 {\n\tvrD = altv207_50(vrA,vrB);\n}\n\n:vsbox vrD,vrA\t\t\t\tis OP=4 & vrD & vrA & BITS_11_15=0 & XOP_0_10=1480 {\n\tvrD = altv207_51(vrA);\n}\n\n:vshasigmad vrD,vrA,ST,SIX\tis OP=4 & vrD & vrA & ST & SIX & XOP_0_10=1730 {\n\tvrD = altv207_52(vrA,ST:1,SIX:1);\n}\n\n:vshasigmaw vrD,vrA,ST,SIX\tis OP=4 & vrD & vrA & ST & SIX & XOP_0_10=1666 {\n\tvrD = altv207_53(vrA,ST:1,SIX:1);\n}\n\n:vsld vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1476 {\n\tvrD = altv207_54(vrA,vrB);\n}\n\n:vsrad vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=964 {\n\tvrD = altv207_55(vrA,vrB);\n}\n\n:vsrd vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1732 {\n\tvrD = altv207_56(vrA,vrB);\n}\n\n:vsubcuq vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1344 {\n\tvrD = altv207_57(vrA,vrB);\n}\n\n:vsubecuq vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=63 {\n\tvrD = altv207_58(vrA,vrB,vrC);\n}\n\n:vsubeuqm vrD,vrA,vrB,vrC\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=62 {\n\tvrD = altv207_59(vrA,vrB,vrC);\n}\n\n:vsubudm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1216 {\n\tvrD = altv207_60(vrA,vrB);\n}\n\n:vsubuqm vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1280 {\n\tvrD = altv207_61(vrA,vrB);\n}\n\n:vupkhsw vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1614 {\n\tvrD = altv207_62(vrB);\n}\n\n:vupklsw vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1742 {\n\tvrD = altv207_63(vrB);\n}\n\n###################\n# v3.0\n\n:bcdcfn. vrD,vrB,PS\t\t\tis OP=4 & vrD & vrB & BITS_16_20=7 & XOP_0_8=385 & BIT_10=1 & PS {\n\tvrD = altv300_1(vrB,PS:1);\n}\n\n:bcdcfsq. vrD,vrB,PS\t\tis OP=4 & vrD & vrB & BITS_16_20=2 & XOP_0_8=385 & BIT_10=1 & PS {\n\tvrD = altv300_2(vrB,PS:1);\n}\n\n:bcdcfz. vrD,vrB,PS\t\t\tis OP=4 & vrD & vrB & BITS_16_20=6 & XOP_0_8=385 & BIT_10=1 & PS {\n\tvrD = altv300_3(vrB,PS:1);\n}\n\n:bcdcpsgn. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=833 {\n\tvrD = altv300_4(vrA,vrB);\n}\n\n:bcdctn. vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=5 & XOP_0_8=385 & BIT_10=1 & BIT_9=0 {\n\tvrD = altv300_5(vrB);\n}\n\n:bcdctsq. vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_8=385 & BIT_10=1 & BIT_9=0 {\n\tvrD = altv300_6(vrB);\n}\n\n:bcdctz. vrD,vrB,PS\t\t\tis OP=4 & vrD & vrB & BITS_16_20=4 & XOP_0_8=385 & BIT_10=1 & PS {\n\tvrD = altv300_7(vrB,PS:1);\n}\n\n:bcds. vrD,vrA,vrB,PS\t\tis OP=4 & vrD & vrA & vrB & XOP_0_8=193 & BIT_10=1 & PS {\n\tvrD = altv300_8(vrA,vrB,PS:1);\n}\n\n:bcdsetsgn. vrD,vrB,PS\t\tis OP=4 & vrD & vrB & BITS_16_20=31 & XOP_0_8=385 & BIT_10=1 & PS {\n\tvrD = altv300_9(vrB,PS:1);\n}\n\n:bcdsr. vrD,vrA,vrB,PS\t\tis OP=4 & vrD & vrA & vrB & XOP_0_8=449 & BIT_10=1 & PS {\n\tvrD = altv300_10(vrA,vrB,PS:1);\n}\n\n:bcdtrunc. vrD,vrA,vrB,PS\tis OP=4 & vrD & vrA & vrB & XOP_0_8=257 & BIT_10=1 & PS {\n\tvrD = altv300_12(vrA,vrB,PS:1);\n}\n\n:bcdus. vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_8=129 & BIT_10=1 {\n\tvrD = altv300_13(vrA,vrB);\n}\n\n:bcdutrunc. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_8=321 & BIT_10=1 {\n\tvrD = altv300_14(vrA,vrB);\n}\n\n:vabsdub vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1027 {\n\tvrD = altv300_15(vrA,vrB);\n}\n\n:vabsduh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1091 {\n\tvrD = altv300_16(vrA,vrB);\n}\n\n:vabsduw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1155 {\n\tvrD = altv300_17(vrA,vrB);\n}\n\n:vbpermd vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1484 {\n\tvrD = altv300_18(vrA,vrB);\n}\n\n:vclzlsbb vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1538 {\n\tvrD = altv300_19(vrB);\n}\n\n:vcmpneb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=7 {\n\tvrD = altv300_20(vrA,vrB);\n}\n\n:vcmpneb. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=7 {\n\tvrD = altv300_21(vrA,vrB);\n}\n\n:vcmpneh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=71 {\n\tvrD = altv300_22(vrA,vrB);\n}\n\n:vcmpneh. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=71 {\n\tvrD = altv300_23(vrA,vrB);\n}\n\n:vcmpnew vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=135 {\n\tvrD = altv300_24(vrA,vrB);\n}\n\n:vcmpnew. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=135 {\n\tvrD = altv300_25(vrA,vrB);\n}\n\n:vcmpnezb vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=263 {\n\tvrD = altv300_26(vrA,vrB);\n}\n\n:vcmpnezb. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=263 {\n\tvrD = altv300_27(vrA,vrB);\n}\n\n:vcmpnezh vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=327 {\n\tvrD = altv300_28(vrA,vrB);\n}\n\n:vcmpnezh. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=327 {\n\tvrD = altv300_29(vrA,vrB);\n}\n\n:vcmpnezw vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=391 {\n\tvrD = altv300_30(vrA,vrB);\n}\n\n:vcmpnezw. vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=391 {\n\tvrD = altv300_31(vrA,vrB);\n}\n\n:vctzb vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=28 & XOP_0_10=1538 {\n\tvrD = altv300_32(vrB);\n}\n\n:vctzh vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=29 & XOP_0_10=1538 {\n\tvrD = altv300_33(vrB);\n}\n\n:vctzd vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=31 & XOP_0_10=1538 {\n\tvrD = altv300_34(vrB);\n}\n\n:vctzlsbb vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=1 & XOP_0_10=1538 {\n\tvrD = altv300_35(vrB);\n}\n\n:vctzw vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=30 & XOP_0_10=1538 {\n\tvrD = altv300_36(vrB);\n}\n\n:vextractd vrD,vrB,UIMB\t\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=717 {\n\t# if UIMB > 8 the result is undefined\n\tvrD = (vrB >> (8 * (8 - UIMB))) & 0xffffffffffffffff;\n}\n\n:vextractub vrD,vrB,UIMB\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=525 {\n\t# if UIMB > 15 the result is undefined\n\tvrD = (vrB >> (16 * (15 - UIMB))) & 0xff;\n}\n\n:vextractuh vrD,vrB,UIMB\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=589 {\n\t# if UIMB > 14 the result is undefined\n\tvrD = (vrB >> (16 * (14 - UIMB))) & 0xffff;\n}\n\n:vextractuw vrD,vrB,UIMB\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=653 {\n\t# if UIMB > 12 the result is undefined\n\tvrD = (vrB >> (16 * (12 - UIMB))) & 0xffffffff;\n}\n\n:vextsb2d vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=24 & XOP_0_10=1538 {\n\tvrD = altv300_41(vrB);\n}\n\n:vextsb2w vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=16 & XOP_0_10=1538 {\n\tvrD = altv300_42(vrB);\n}\n\n:vextsh2d vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=25 & XOP_0_10=1538 {\n\tvrD = altv300_43(vrB);\n}\n\n:vextsh2w vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=17 & XOP_0_10=1538 {\n\tvrD = altv300_44(vrB);\n}\n\n:vextsw2d vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=26 & XOP_0_10=1538 {\n\tvrD = altv300_45(vrB);\n}\n\n:vextublx D,A,vrB\t\t\tis OP=4 & D & A & vrB & XOP_0_10=1549 {\n\tD = altv300_46(A,vrB);\n}\n\n:vextubrx D,A,vrB\t\t\tis OP=4 & D & A & vrB & XOP_0_10=1805 {\n\tD = altv300_47(A,vrB);\n}\n\n:vextuhlx D,A,vrB\t\t\tis OP=4 & D & A & vrB & XOP_0_10=1613 {\n\tD = altv300_48(A,vrB);\n}\n\n:vextuhrx D,A,vrB\t\t\tis OP=4 & D & A & vrB & XOP_0_10=1869 {\n\tD = altv300_49(A,vrB);\n}\n\n# beware the backwards bit/byte ordering in the manual\n:vextuwlx D,A,vrB\t\t\tis OP=4 & D & A & vrB & XOP_0_10=1677\n{\n\tlocal offs:2 = (12 - zext(A[0,4])) * 8;\n\tlocal out:16 = (vrB >> offs) & 0xffffffff;\n\t# No need for zext, as mask is already applied\n\tD = out:$(REGISTER_SIZE);\n}\n\n:vextuwrx D,A,vrB\t\t\tis OP=4 & D & A & vrB & XOP_0_10=1933 {\n\tD = altv300_51(A,vrB);\n}\n\n:vinsertb vrD,vrB,UIMB\t\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=781 {\n\tvrD = altv300_52(vrB,UIMB:1);\n}\n\n:vinsertd vrD,vrB,UIMB\t\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=973 {\n\tvrD = altv300_53(vrB,UIMB:1);\n}\n\n:vinserth vrD,vrB,UIMB\t\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=845 {\n\tvrD = altv300_54(vrB,UIMB:1);\n}\n\n:vinsertw vrD,vrB,UIMB\t\tis OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=909 {\n\tvrD = altv300_55(vrB,UIMB:1);\n}\n\n:vmul10cuq vrD,vrA\t\t\tis OP=4 & vrD & vrA & BITS_11_15=0 & XOP_0_10=1 {\n\tvrD = altv300_56(vrA);\n}\n\n:vmul10ecuq vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=65 {\n\tvrD = altv300_57(vrA,vrB);\n}\n\n:vmul10euq vrD,vrA,vrB\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=577 {\n\tvrD = altv300_58(vrA,vrB);\n}\n\n:vmul10uq vrD,vrA\t\t\tis OP=4 & vrD & vrA & BITS_11_15=0 & XOP_0_10=513 {\n\tvrD = altv300_59(vrA);\n}\n\n:vnegd vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=7 & XOP_0_10=1538 {\n\tvrD = altv300_60(vrB);\n}\n\n:vnegw vrD,vrB\t\t\t\tis OP=4 & vrD & vrB & BITS_16_20=6 & XOP_0_10=1538 {\n\tvrD = altv300_61(vrB);\n}\n\n:vpermr vrD,vrA,vrB,vrC\t\tis OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=59 {\n\tvrD = altv300_62(vrA,vrB,vrC);\n}\n\n:vprtybd vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=9 & XOP_0_10=1538 {\n\tvrD = altv300_63(vrB);\n}\n\n:vprtybq vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=10 & XOP_0_10=1538 {\n\tvrD = altv300_64(vrB);\n}\n\n:vprtybw vrD,vrB\t\t\tis OP=4 & vrD & vrB & BITS_16_20=8 & XOP_0_10=1538 {\n\tvrD = altv300_65(vrB);\n}\n\n:vrldmi vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=197 {\n\tvrD = altv300_66(vrA,vrB);\n}\n\n:vrldnm vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=453 {\n\tvrD = altv300_67(vrA,vrB);\n}\n\n:vrlwmi vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=133 {\n\tvrD = altv300_68(vrA,vrB);\n}\n\n:vrlwnm vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=389 {\n\tvrD = altv300_69(vrA,vrB);\n}\n\n:vslv vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1860 {\n\tvrD = altv300_70(vrA,vrB);\n}\n\n:vsrv vrD,vrA,vrB\t\t\tis OP=4 & vrD & vrA & vrB & XOP_0_10=1796 {\n\tvrD = altv300_71(vrA,vrB);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/evx.sinc", "content": "\n@include \"Scalar_SPFP.sinc\"\n@ifdef IS_ISA\n@include \"SPE_APU.sinc\"\n@endif\n\n:lvx vrD, RA_OR_ZERO, RB is OP=31 & vrD & RA_OR_ZERO & RB & XOP_1_10=103 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;\n vrD = *:16 ($(EATRUNC));\n}\n\n:stvx vrS, RA_OR_ZERO, RB is OP=31 & vrS & RA_OR_ZERO & RB & XOP_1_10=231 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;\n *:16 ($(EATRUNC)) = vrS;\n}\n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/g2.sinc", "content": "\ndefine pcodeop tlbli;\ndefine pcodeop tlbld;\n\n:tlbld B\t\t\tis $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=978 & BIT_0=0\n{\n\ttlbld(B);\n}\n\n:tlbli B\t\t\tis $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=1010 & BIT_0=0\n{\n\ttlbli(B);\n}\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/lmwInstructions.sinc", "content": "LDMR0:\t\tis lsmul=1 {}\nLDMR0:\t\tis epsilon { loadReg(r0); }\n\nLDMR1:\t\tis lsmul=2 {}\nLDMR1:\t\tis LDMR0 { build LDMR0; loadReg(r1); }\n\nLDMR2:\t\tis lsmul=3 {}\nLDMR2:\t\tis LDMR1 { build LDMR1; loadReg(r2); }\n\nLDMR3:\t\tis lsmul=4 {}\nLDMR3:\t\tis LDMR2 { build LDMR2; loadReg(r3); }\n\nLDMR4:\t\tis lsmul=5 {}\nLDMR4:\t\tis LDMR3 { build LDMR3; loadReg(r4); }\n\nLDMR5:\t\tis lsmul=6 {}\nLDMR5:\t\tis LDMR4 { build LDMR4; loadReg(r5); }\n\nLDMR6:\t\tis lsmul=7 {}\nLDMR6:\t\tis LDMR5 { build LDMR5; loadReg(r6); }\n\nLDMR7:\t\tis lsmul=8 {}\nLDMR7:\t\tis LDMR6 { build LDMR6; loadReg(r7); }\n\nLDMR8:\t\tis lsmul=9 {}\nLDMR8:\t\tis LDMR7 { build LDMR7; loadReg(r8); }\n\nLDMR9:\t\tis lsmul=10 {}\nLDMR9:\t\tis LDMR8 { build LDMR8; loadReg(r9); }\n\nLDMR10:\t\tis lsmul=11 {}\nLDMR10:\t\tis LDMR9 { build LDMR9; loadReg(r10); }\n\nLDMR11:\t\tis lsmul=12 {}\nLDMR11:\t\tis LDMR10 { build LDMR10; loadReg(r11); }\n\nLDMR12:\t\tis lsmul=13 {}\nLDMR12:\t\tis LDMR11 { build LDMR11; loadReg(r12); }\n\nLDMR13:\t\tis lsmul=14 {}\nLDMR13:\t\tis LDMR12 { build LDMR12; loadReg(r13); }\n\nLDMR14:\t\tis lsmul=15 {}\nLDMR14:\t\tis LDMR13 { build LDMR13; loadReg(r14); }\n\nLDMR15:\t\tis lsmul=16 {}\nLDMR15:\t\tis LDMR14 { build LDMR14; loadReg(r15); }\n\nLDMR16:\t\tis lsmul=17 {}\nLDMR16:\t\tis LDMR15 { build LDMR15; loadReg(r16); }\n\nLDMR17:\t\tis lsmul=18 {}\nLDMR17:\t\tis LDMR16 { build LDMR16; loadReg(r17); }\n\nLDMR18:\t\tis lsmul=19 {}\nLDMR18:\t\tis LDMR17 { build LDMR17; loadReg(r18); }\n\nLDMR19:\t\tis lsmul=20 {}\nLDMR19:\t\tis LDMR18 { build LDMR18; loadReg(r19); }\n\nLDMR20:\t\tis lsmul=21 {}\nLDMR20:\t\tis LDMR19 { build LDMR19; loadReg(r20); }\n\nLDMR21:\t\tis lsmul=22 {}\nLDMR21:\t\tis LDMR20 { build LDMR20; loadReg(r21); }\n\nLDMR22:\t\tis lsmul=23 {}\nLDMR22:\t\tis LDMR21 { build LDMR21; loadReg(r22); }\n\nLDMR23:\t\tis lsmul=24 {}\nLDMR23:\t\tis LDMR22 { build LDMR22; loadReg(r23); }\n\nLDMR24:\t\tis lsmul=25 {}\nLDMR24:\t\tis LDMR23 { build LDMR23; loadReg(r24); }\n\nLDMR25:\t\tis lsmul=26 {}\nLDMR25:\t\tis LDMR24 { build LDMR24; loadReg(r25); }\n\nLDMR26:\t\tis lsmul=27 {}\nLDMR26:\t\tis LDMR25 { build LDMR25; loadReg(r26); }\n\nLDMR27:\t\tis lsmul=28 {}\nLDMR27:\t\tis LDMR26 { build LDMR26; loadReg(r27); }\n\nLDMR28:\t\tis lsmul=29 {}\nLDMR28:\t\tis LDMR27 { build LDMR27; loadReg(r28); }\n\nLDMR29:\t\tis lsmul=30 {}\nLDMR29:\t\tis LDMR28 { build LDMR28; loadReg(r29); }\n\nLDMR30:\t\tis lsmul=31 {}\nLDMR30:\t\tis LDMR29 { build LDMR29; loadReg(r30); }\n\nLDMR31:\t\tis LDMR30 { build LDMR30; loadReg(r31); }\n\n:lmw\tD,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=46 & D & BITS_21_25 & dPlusRaOrZeroAddress & LDMR31 [ lsmul = BITS_21_25; ]\n{\t\n\ttea = dPlusRaOrZeroAddress;\n\tbuild LDMR31;\n}\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/lswInstructions.sinc", "content": "#lswi\tr0,0,7\t\t0x7c 00 3c aa\n#lswi\tr0,r2,7\t\t0x7c 02 3c aa\n\nDYN_D1: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 1)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_D2: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 2)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_D3: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 3)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_D4: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 4)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_D5: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 5)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_D6: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 6)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_D7: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 7)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=0 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 & DYN_D7\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n loadRegister(DYN_D5,ea);\n loadRegister(DYN_D6,ea);\n loadRegister(DYN_D7,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=0 & BH & XOP_1_10=597 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n sa:1 = BH;\n loadRegisterPartial(D,ea,sa);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=1 & BH=0 & XOP_1_10=597 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=1 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D1,ea,sa);\n}\n\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=2 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=2 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D2,ea,sa);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=3 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=3 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D3,ea,sa);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=4 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=4 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D4,ea,sa);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=5 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=5 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D5,ea,sa);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=6 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n loadRegister(DYN_D5,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=6 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n loadRegister(DYN_D5,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D6,ea,sa);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=7 & BH=0 & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n loadRegister(DYN_D5,ea);\n loadRegister(DYN_D6,ea);\n}\n\n:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=7 & BH & XOP_1_10=597 & BIT_0=0\n & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 & DYN_D7\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n loadRegister(D,ea);\n loadRegister(DYN_D1,ea);\n loadRegister(DYN_D2,ea);\n loadRegister(DYN_D3,ea);\n loadRegister(DYN_D4,ea);\n loadRegister(DYN_D5,ea);\n loadRegister(DYN_D6,ea);\n sa:1 = BH;\n loadRegisterPartial(DYN_D7,ea,sa);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/mulhwInstructions.sinc", "content": "#macchw r0,r0,r0\t0x10 00 01 58\n:macchw D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=0\n{\n D = macchw(D, A, B);\n}\n\n#macchw. r0,r0,r0\t0x10 00 01 59\n:macchw. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=1\n{\n D = macchw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchwo r0,r0,r0\t0x10 00 05 58\n:macchwo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=0\n{\n D = macchw(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#macchwo. r0,r0,r0\t0x10 00 05 59\n:macchwo. D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=1\n{\n D = macchw(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchws r0,r0,r0\t0x10 00 01 d8\n:macchws D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=0\n{\n D = macchws(D, A, B);\n}\n\n#macchws. r0,r0,r0\t0x10 00 01 d9\n:macchws. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=1\n{\n D = macchws(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchwso r0,r0,r0\t0x10 00 05 d8\n:macchwso D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=0\n{\n D = macchws(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#macchwso. r0,r0,r0\t0x10 00 05 d9\n:macchwso. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1\n{\n D = macchws(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchwsu r0,r0,r0\t0x10 00 01 98\n:macchwsu D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=0\n{\n D = macchwsu(D, A, B);\n}\n\n#macchwsu. r0,r0,r0\t0x10 00 01 99\n:macchwsu. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=1\n{\n D = macchwsu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchwsuo r0,r0,r0\t0x10 00 05 98\n:macchwsuo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=0\n{\n D = macchwsu(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#macchwsuo. r0,r0,r0\t0x10 00 05 99\n:macchwsuo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=1\n{\n D = macchwsu(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchwu r0,r0,r0\t0x10 00 01 18\n:macchwu D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=0\n{\n D = macchwu(D, A, B);\n}\n\n#macchwu. r0,r0,r0\t0x10 00 01 19\n:macchwu. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=1\n{\n D = macchwu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#macchwuo r0,r0,r0\t0x10 00 05 18\n:macchwuo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=0\n{\n D = macchwu(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#macchwuo. r0,r0,r0\t0x10 00 05 19\n:macchwuo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=1\n{\n D = macchwu(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n\n#machhw r0,r0,r0\t0x10 00 00 58\n:machhw D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=0\n{\n D = machhw(D, A, B);\n}\n\n#machhw. r0,r0,r0\t0x10 00 00 59\n:machhw. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=1\n{\n D = machhw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhwo r0,r0,r0\t0x10 00 04 58\n:machhwo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=0\n{\n D = machhw(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#machhwo. r0,r0,r0\t0x10 00 04 59\n:machhwo. D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=1\n{\n D = machhw(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhws r0,r0,r0\t0x10 00 00 d8\n:machhws D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=0\n{\n D = machhws(D, A, B);\n}\n\n#machhws. r0,r0,r0\t0x10 00 00 d9\n:machhws. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=1\n{\n D = machhws(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhwso r0,r0,r0\t0x10 00 04 d8\n:machhwso D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=0\n{\n D = machhws(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#machhwso. r0,r0,r0\t0x10 00 04 d9\n:machhwso. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=1\n{\n D = machhws(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhwsu r0,r0,r0\t0x10 00 00 98\n:machhwsu D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=0\n{\n D = machhwsu(D, A, B);\n}\n\n#machhwsu. r0,r0,r0\t0x10 00 00 99\n:machhwsu. D,A,B\tis OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=1\n{\n D = machhwsu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhwsuo r0,r0,r0\t0x10 00 04 98\n:machhwsuo D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=0\n{\n D = machhwsu(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#machhwsuo. r0,r0,r0\t0x10 00 04 99\n:machhwsuo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=1\n{\n D = machhwsu(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhwu r0,r0,r0\t0x10 00 00 18\n:machhwu D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=0\n{\n D = machhwu(D, A, B);\n}\n\n#machhwu. r0,r0,r0\t0x10 00 00 19\n:machhwu. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=1\n{\n D = machhwu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#machhwuo r0,r0,r0\t0x10 00 04 18\n:machhwuo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=0\n{\n D = machhwu(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#machhwuo. r0,r0,r0\t0x10 00 04 19\n:machhwuo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=1\n{\n D = machhwu(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n\n#maclhw r0,r0,r0\t0x10 00 03 58\n:maclhw D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=0\n{\n D = maclhw(D, A, B);\n}\n\n#maclhw. r0,r0,r0\t0x10 00 03 59\n:maclhw. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=1\n{\n D = maclhw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhwo r0,r0,r0\t0x10 00 07 58\n:maclhwo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=0\n{\n D = maclhw(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#maclhwo. r0,r0,r0\t0x10 00 07 59\n:maclhwo. D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=1\n{\n D = maclhw(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhws r0,r0,r0\t0x10 00 03 d8\n:maclhws D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=0\n{\n D = maclhws(D, A, B);\n}\n\n#maclhws. r0,r0,r0\t0x10 00 03 d9\n:maclhws. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=1\n{\n D = maclhws(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhwso r0,r0,r0\t0x10 00 07 d8\n:maclhwso D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=0\n{\n D = maclhws(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#maclhwso. r0,r0,r0\t0x10 00 07 d9\n:maclhwso. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=1\n{\n D = maclhws(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhwsu r0,r0,r0\t0x10 00 03 98\n:maclhwsu D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=0\n{\n D = maclhwsu(D, A, B);\n}\n\n#maclhwsu. r0,r0,r0\t0x10 00 03 99\n:maclhwsu. D,A,B\tis OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=1\n{\n D = maclhwsu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhwsuo r0,r0,r0\t0x10 00 07 98\n:maclhwsuo D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=0\n{\n D = maclhwsu(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#maclhwsuo. r0,r0,r0\t0x10 00 07 99\n:maclhwsuo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=1\n{\n D = maclhwsu(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhwu r0,r0,r0\t0x10 00 03 18\n:maclhwu D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=0\n{\n D = maclhwu(D, A, B);\n}\n\n#maclhwu. r0,r0,r0\t0x10 00 03 19\n:maclhwu. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=1\n{\n D = maclhwu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#maclhwuo r0,r0,r0\t0x10 00 07 18\n:maclhwuo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=0\n{\n D = maclhwu(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#maclhwuo. r0,r0,r0\t0x10 00 07 19\n:maclhwuo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=1\n{\n D = maclhwu(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#mulchw r0,r0,r0\t0x10 00 01 50\n:mulchw D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=168 & Rc=0\n{\n D = mulchw(D, A, B);\n}\n\n#mulchw. r0,r0,r0\t0x10 00 01 51\n:mulchw. D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=168 & Rc=1\n{\n D = mulchw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#mulchwu r0,r0,r0\t0x10 00 01 10\n:mulchwu D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=136 & Rc=0\n{\n D = mulchwu(D, A, B);\n}\n\n#mulchwu. r0,r0,r0\t0x10 00 01 11\n:mulchwu. D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=136 & Rc=1\n{\n D = mulchwu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#mulhhw r0,r0,r0\t0x10 00 00 50\n:mulhhw D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=40 & Rc=0\n{\n D = mulhhw(D, A, B);\n}\n\n#mulhhw. r0,r0,r0\t0x10 00 00 51\n:mulhhw. D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=40 & Rc=1\n{\n D = mulhhw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#mulhhwu r0,r0,r0\t0x10 00 00 10\n:mulhhwu D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=8 & Rc=0\n{\n D = mulhhwu(D, A, B);\n}\n\n#mulhhwu. r0,r0,r0\t0x10 00 00 11\n:mulhhwu. D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=8 & Rc=1\n{\n D = mulhhwu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#mullhw r0,r0,r0\t0x10 00 03 50\n:mullhw D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=424 & Rc=0\n{\n D = mullhw(D, A, B);\n}\n\n#mullhw. r0,r0,r0\t0x10 00 03 51\n:mullhw. D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=424 & Rc=1\n{\n D = mullhw(D, A, B);\n\tcr0flags(D);\t\n}\n\n# mulhwu r0,r0,r0\t0x10 00 03 10\n:mullhwu D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=392 & Rc=0\n{\n\t\tD = mullhwu(D, A, B);\n}\n\n#mullhwu. r0,r0,r0\t0x10 00 03 11\n:mullhwu. D,A,B\t\tis OP=4 & D & A & B & XOP_1_10=392 & Rc=1\n{\n D = mullhwu(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmacchw r0,r0,r0\t0x10 00 01 5c\n:nmacchw D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=0\n{\n D = nmacchw(D, A, B);\n}\n\n#nmacchw. r0,r0,r0\t0x10 00 01 5d\n:nmacchw. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=1\n{\n D = nmacchw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmacchwo r0,r0,r0\t0x10 00 05 5c\n:nmacchwo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=0\n{\n D = nmacchw(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#nmacchwo. r0,r0,r0\t0x10 00 05 5d\n:nmacchwo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=1\n{\n D = nmacchw(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmacchws r0,r0,r0\t0x10 00 01 dc\n:nmacchws D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=0\n{\n D = nmacchws(D, A, B);\n}\n\n#nmacchws. r0,r0,r0\t0x10 00 01 dd\n:nmacchws. D,A,B\tis OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=1\n{\n D = nmacchws(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmacchwso r0,r0,r0\t0x10 00 05 dc\n:nmacchwso D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=0\n{\n D = nmacchws(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#nmacchwso. r0,r0,r0\t0x10 00 05 dd\n:nmacchwso. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=1\n{\n D = nmacchws(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmachhw r0,r0,r0\t0x10 00 00 5c\n:nmachhw D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=0\n{\n D = nmachhw(D, A, B);\n}\n\n#nmachhw. r0,r0,r0\t0x10 00 00 5d\n:nmachhw. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=1\n{\n D = nmachhw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmachhwo r0,r0,r0\t0x10 00 04 5c\n:nmachhwo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=0\n{\n D = nmachhw(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#nmachhwo. r0,r0,r0\t0x10 00 04 5d\n:nmachhwo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=1\n{\n D = nmachhw(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmachhws r0,r0,r0\t0x10 00 00 dc\n:nmachhws D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=0\n{\n D = nmachhws(D, A, B);\n}\n\n#nmachhws. r0,r0,r0\t0x10 00 00 dd\n:nmachhws. D,A,B\tis OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=1\n{\n D = nmachhws(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmachhwso r0,r0,r0\t0x10 00 04 dc\n:nmachhwso D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=0\n{\n D = nmachhws(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#nmachhwso. r0,r0,r0\t0x10 00 04 dd\n:nmachhwso. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=1\n{\n D = nmachhws(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmaclhw r0,r0,r0\t0x10 00 03 5c\n:nmaclhw D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=0\n{\n D = nmaclhw(D, A, B);\n}\n\n#nmaclhw. r0,r0,r0\t0x10 00 03 5d\n:nmaclhw. D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=1\n{\n D = nmaclhw(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmaclhwo r0,r0,r0\t0x10 00 07 5c\n:nmaclhwo D,A,B\t\tis OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=0\n{\n D = nmaclhw(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#nmaclhwo. r0,r0,r0\t0x10 00 07 5d\n:nmaclhwo. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=1\n{\n D = nmaclhw(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmaclhws r0,r0,r0\t0x10 00 03 dc\n:nmaclhws D,A,B\t\tis OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=0\n{\n D = nmaclhws(D, A, B);\n}\n\n#nmaclhws. r0,r0,r0\t0x10 00 03 dd\n:nmaclhws. D,A,B\tis OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=1\n{\n D = nmaclhws(D, A, B);\n\tcr0flags(D);\t\n}\n\n#nmaclhwso r0,r0,r0\t0x10 00 07 dc\n:nmaclhwso D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=0\n{\n D = nmaclhws(D, A, B);\n xer_mac_update(D, A, B);\n}\n\n#nmaclhwso. r0,r0,r0\t0x10 00 07 dd\n:nmaclhwso. D,A,B\tis OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=1\n{\n D = nmaclhws(D, A, B);\n xer_mac_update(D, A, B);\n\tcr0flags(D);\t\n}" }, { "path": "pypcode/processors/PowerPC/data/languages/old/oldPPC.lang", "content": "\n\n \n PowerPC:BE:32:DEPRECATED\n PowerPC\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/old/oldPPC.trans", "content": "\n\n Sleigh-PowerPC 32-bit\n PowerPC:BE:32:default\n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc.dwarf", "content": "\n\t\n\t\t\n\t\t\n\t\t \n\t\t \n\t\t \n\t\t\n\t\t \n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc.ldefs", "content": "\n\n\n \n PowerPC 32-bit big endian w/Altivec, G2\n \n \n \n \n \n \n \n \n \n PowerPC 32-bit little endian w/Altivec, G2\n \n \n \n \n \n \n \n PowerPC 64-bit big endian w/Altivec, G2\n \n \n \n \n \n \n \n \n \n PowerPC 64-bit big endian w/Altivec and 32 bit addressing, G2\n \n \n \n \n \n \n \n \n \n PowerPC 64-bit little endian w/Altivec and 32 bit addressing, G2\n \n \n \n\t\n\t\n \n \n \n PowerPC 64-bit little endian w/Altivec, G2\n \n \n \n \n \n \n \n \n PowerPC 4xx 32-bit big endian embedded core\n \n\t\n\t\n \n \n \n \n \n PowerPC 4xx 32-bit little endian embedded core\n \n \n\t\n\t\n \n \n \n Freescale MPC8280 32-bit big endian family (PowerQUICC-III)\n \n \n \n \n \n \n \n \n PowerQUICC-III 32-bit big endian family\n \n\t\n\t\n \n \n \n \n \n PowerQUICC-III 32-bit little endian family\n \n \n\t\n\t\n \n \n \n Power ISA e200 32-bit big-endian embedded core w/VLE\n \n \n \n \n \n \n \n PowerQUICC-III e500 32-bit big-endian family\n \n \n \n \n \n \n \n \n \n PowerQUICC-III e500 32-bit little-endian family\n \n \n \n \n \n \n \n PowerQUICC-III e500mc 32-bit big-endian family\n \n \n \n \n \n \n \n \n PowerQUICC-III e500mc 32-bit little-endian family\n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/EVX and 32-bit Addressing\n \n \n \n \n \n \n \n \n \n Power ISA 3.0 Little Endian w/EVX and 32-bit Addressing\n \n \n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/Altivec and 32-bit Addressing\n \n \n \n \n \n \n \n \n \n Power ISA 3.0 Little Endian w/Altivec and 32-bit Addressing\n \n \n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/Altivec\n \n\t\n\t\n \n \n \n \n \n Power ISA 3.0 Little Endian w/Altivec\n \n \n\t\n \n \n \n \n \n Power ISA 3.0 Big Endian w/VLE, EVX and 32-bit Addressing \n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/VLE, Altivec and 32-bit Addressing\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig", "content": "\n\n\n \n PowerPC 32-bit big endian w/Altivec, G2\n \n \n \n \n \n \n \n \n \n PowerPC 32-bit little endian w/Altivec, G2\n \n \n \n \n \n \n \n PowerPC 64-bit big endian w/Altivec, G2\n \n \n \n \n \n \n \n \n \n PowerPC 64-bit big endian w/Altivec and 32 bit addressing, G2\n \n \n \n \n \n \n \n \n \n PowerPC 64-bit little endian w/Altivec and 32 bit addressing, G2\n \n \n \n\t\n\t\n \n \n \n PowerPC 64-bit little endian w/Altivec, G2\n \n \n \n \n \n \n \n \n PowerPC 4xx 32-bit big endian embedded core\n \n\t\n\t\n \n \n \n \n \n PowerPC 4xx 32-bit little endian embedded core\n \n \n\t\n\t\n \n \n \n Freescale MPC8280 32-bit big endian family (PowerQUICC-III)\n \n \n \n \n \n \n \n \n PowerQUICC-III 32-bit big endian family\n \n\t\n\t\n \n \n \n \n \n PowerQUICC-III 32-bit little endian family\n \n \n\t\n\t\n \n \n \n PowerQUICC-III e500 32-bit big-endian family\n \n \n \n \n \n \n \n \n \n PowerQUICC-III e500 32-bit little-endian family\n \n \n \n \n \n \n \n PowerQUICC-III e500mc 32-bit big-endian family\n \n \n \n \n \n \n \n \n PowerQUICC-III e500mc 32-bit little-endian family\n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/EVX and 32-bit Addressing\n \n \n \n \n \n \n \n \n \n Power ISA 3.0 Little Endian w/EVX and 32-bit Addressing\n \n \n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/Altivec and 32-bit Addressing\n \n \n \n \n \n \n \n \n \n Power ISA 3.0 Little Endian w/Altivec and 32-bit Addressing\n \n \n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/Altivec\n \n\t\n\t\n \n \n \n \n \n Power ISA 3.0 Little Endian w/Altivec\n \n \n\t\n \n \n \n \n \n Power ISA 3.0 Big Endian w/VLE, EVX and 32-bit Addressing \n \n \n \n \n \n \n Power ISA 3.0 Big Endian w/VLE, Altivec and 32-bit Addressing\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n \t\n\t\n\t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_4xx_be.slaspec", "content": "# SLA specification file for IBM PowerPC 4xx series core\n\n@define ENDIAN \"big\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"4xx.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_4xx_le.slaspec", "content": "# SLA specification file for IBM PowerPC 4xx series core\n\n@define ENDIAN \"little\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"4xx.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_be.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_be.slaspec", "content": "# SLA specification file for PowerPC 32-bit big endian\n\n@define ENDIAN \"big\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"altivec.sinc\"\n@include \"g2.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_be_Mac.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n * (r1 + 0x14) = r2;\n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e200.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e200.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n \t\n\t\n\t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e200.slaspec", "content": "# SLA specification file for IBM PowerPC e200 series core\n# Note: e200 series use VLE, with exception of e200z7 which supports both VLE and non-VLE\n\n@define E200\n@define ENDIAN \"big\"\n@define REGISTER_SIZE \"4\"\n@define EATRUNC \"ea\"\n@define CTR_OFFSET \"32\"\n@define NoLegacyIntegerMultiplyAccumulate\n\n@include \"ppc_common.sinc\"\n@include \"ppc_vle.sinc\"\n@include \"evx.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500_be.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500_be.slaspec", "content": "# SLA specification file for IBM PowerPC e500 series core\n\n# NOTE: This language variant includes some registers and instructions not supported\n# by the actual processor (e.g., floating pointer registers and associated instructions).\n# The actual processor only supports a subset of the registers and instructions implemented.\n\n@define E500 \"1\"\n\n@define ENDIAN \"big\"\n\n# Although a 32-bit architecture, 64-bit general purpose registers are supported. \n# Language has been modeled using a 64-bit implementation with a 32-bit truncated \n# memory space (see ldefs).\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@include \"ppc_common.sinc\"\n@include \"quicciii.sinc\"\n@include \"SPE_APU.sinc\"\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n@include \"SPE_EFSD.sinc\"\n@include \"SPE_EFV.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500_le.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500_le.slaspec", "content": "# SLA specification file for IBM PowerPC e500 series core\n\n# NOTE: This language variant includes some registers and instructions not supported\n# by the actual processor (e.g., floating pointer registers and associated instructions).\n# The actual processor only supports a subset of the registers and instructions implemented.\n\n@define E500 \"1\"\n\n@define ENDIAN \"little\"\n\n# Although a 32-bit architecture, 64-bit general purpose registers are supported. \n# Language has been modeled using a 64-bit implementation with a 32-bit truncated \n# memory space (see ldefs).\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@include \"ppc_common.sinc\"\n@include \"quicciii.sinc\"\n@include \"SPE_APU.sinc\"\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n@include \"SPE_EFSD.sinc\"\n@include \"SPE_EFV.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec", "content": "# SLA specification file for IBM PowerPC e500 series core\n\n# NOTE: This language variant includes some registers and instructions not supported\n# by the actual processor (e.g., floating pointer registers and associated instructions).\n# The actual processor only supports a subset of the registers and instructions implemented.\n\n@define ENDIAN \"big\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n# e500mc has 32 bit registers\n#\n@define CTR_OFFSET \"32\"\n\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@include \"ppc_common.sinc\"\n@include \"quicciii.sinc\"\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec", "content": "# SLA specification file for IBM PowerPC e500 series core\n\n#@define E500\n\n@define ENDIAN \"little\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n# e500mc has 32 bit registers\n#\n@define CTR_OFFSET \"32\"\n\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@include \"ppc_common.sinc\"\n@include \"quicciii.sinc\"\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_le.slaspec", "content": "# SLA specification file for PowerPC 32-bit little endian\n\n@define ENDIAN \"little\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n@include \"ppc_common.sinc\"\n@include \"altivec.sinc\"\n@include \"g2.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_mpc8270.pspec", "content": "\n\n\n\n \n \n \n \n \n \n\n\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_quicciii_be.slaspec", "content": "# SLA specification file for IBM PowerPC 4xx series core\n\n@define ENDIAN \"big\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"quicciii.sinc\"\n@include \"evx.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_32_quicciii_le.slaspec", "content": "# SLA specification file for IBM PowerPC 4xx series core\n\n@define ENDIAN \"little\"\n\n@define REGISTER_SIZE \"4\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"quicciii.sinc\"\n@include \"evx.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64.pspec", "content": "\n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n \t\n\t\n\t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\n\t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_32.cspec", "content": "\n\n\n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_be.cspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\t# Inject pcode when returning from a function call to place the r2Save\n \t\t# value into 0x28(r1) which should be restored by the \"ld r2,0x28(r1)\" \n \t\t# which immediately follows calls which comply with the PPC64 ABI spec.\n \t\tlocal saveR2ptr = r1 + 0x28;\n \t\t*:8 saveR2ptr = r2Save; \n \t\n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_be.slaspec", "content": "# SLA specification file for PowerPC 64-bit big endian\n\n@define ENDIAN \"big\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n@define EATRUNC \"ea:4\"\n\n@include \"ppc_common.sinc\"\n@include \"altivec.sinc\"\n@include \"g2.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_be_Mac.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_isa_altivec_be.slaspec", "content": "# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) \n# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM.\n\n@define ENDIAN \"big\"\n\n@define IS_ISA \"1\"\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"ppc_isa.sinc\"\n\n@include \"ppc_a2.sinc\"\n@include \"quicciii.sinc\"\n@include \"FPRC.sinc\"\n\n# A given processor can be compliant with the PowerISA spec by including EITHER\n# the embedded vector instructions (EVX) OR the AltiVec instructions\n# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support\n# both at the same time. We have two language variants for PowerISA\n# that specify which of these two vector specs is supported.\n#@include \"evx.sinc\"\n#@include \"SPEF_SCR.sinc\"\n#@include \"SPE_EFSD.sinc\"\n#@include \"SPE_EFV.sinc\"\n## OR\n@include \"altivec.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_isa_altivec_le.slaspec", "content": "# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) \n# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM.\n\n@define ENDIAN \"little\"\n\n@define IS_ISA \"1\"\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"ppc_isa.sinc\"\n\n@include \"ppc_a2.sinc\"\n@include \"quicciii.sinc\"\n@include \"FPRC.sinc\"\n\n# A given processor can be compliant with the PowerISA spec by including EITHER\n# the embedded vector instructions (EVX) OR the AltiVec instructions\n# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support\n# both at the same time. We have two language variants for PowerISA\n# that specify which of these two vector specs is supported.\n#@include \"evx.sinc\"\n#@include \"SPEF_SCR.sinc\"\n#@include \"SPE_EFSD.sinc\"\n#@include \"SPE_EFV.sinc\"\n# OR\n@include \"altivec.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_isa_altivec_vle_be.slaspec", "content": "# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) \n# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM.\n\n@define ENDIAN \"big\"\n\n@define IS_ISA \"1\"\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"ppc_isa.sinc\"\n\n@include \"ppc_a2.sinc\"\n@include \"quicciii.sinc\"\n@include \"FPRC.sinc\"\n\n@include \"ppc_vle.sinc\"\n\n# A given processor can be compliant with the PowerISA spec by including EITHER\n# the embedded vector instructions (EVX) OR the AltiVec instructions\n# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support\n# both at the same time. We have two language variants for PowerISA\n# that specify which of these two vector specs is supported.\n#@include \"evx.sinc\"\n#@include \"SPEF_SCR.sinc\"\n#@include \"SPE_EFSD.sinc\"\n#@include \"SPE_EFV.sinc\"\n## OR\n@include \"altivec.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_isa_be.slaspec", "content": "# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) \n# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM.\n\n@define ENDIAN \"big\"\n\n@define IS_ISA \"1\"\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"ppc_isa.sinc\"\n\n@include \"quicciii.sinc\"\n@include \"FPRC.sinc\"\n\n# A given processor can be compliant with the PowerISA spec by including EITHER\n# the embedded vector instructions (EVX) OR the AltiVec instructions\n# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support\n# both at the same time. We have two language variants for PowerISA\n# that specify which of these two vector specs is supported.\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n@include \"SPE_EFSD.sinc\"\n@include \"SPE_EFV.sinc\"\n# OR\n#@include \"altivec.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_isa_le.slaspec", "content": "# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) \n# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM.\n\n@define ENDIAN \"little\"\n\n@define IS_ISA \"1\"\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"ppc_isa.sinc\"\n\n@include \"quicciii.sinc\"\n@include \"FPRC.sinc\"\n\n# A given processor can be compliant with the PowerISA spec by including EITHER\n# the embedded vector instructions (EVX) OR the AltiVec instructions\n# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support\n# both at the same time. We have two language variants for PowerISA\n# that specify which of these two vector specs is supported.\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n@include \"SPE_EFSD.sinc\"\n@include \"SPE_EFV.sinc\"\n# OR\n#@include \"altivec.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec", "content": "# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) \n# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM.\n\n@define ENDIAN \"big\"\n\n@define IS_ISA \"1\"\n@define NoLegacyIntegerMultiplyAccumulate \"1\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n\n@define EATRUNC \"ea\"\n\n@define CTR_OFFSET \"32\"\n\n@include \"ppc_common.sinc\"\n@include \"ppc_isa.sinc\"\n\n@include \"quicciii.sinc\"\n@include \"FPRC.sinc\"\n\n@include \"ppc_vle.sinc\"\n\n# A given processor can be compliant with the PowerISA spec by including EITHER\n# the embedded vector instructions (EVX) OR the AltiVec instructions\n# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support\n# both at the same time. We have two language variants for PowerISA\n# that specify which of these two vector specs is supported.\n@include \"evx.sinc\"\n@include \"SPEF_SCR.sinc\"\n@include \"SPE_EFSD.sinc\"\n@include \"SPE_EFV.sinc\"\n@include \"SPE_FloatMulAdd.sinc\"\n# OR\n#@include \"altivec.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_le.cspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\t# Inject pcode when returning from a function call to place the r2Save\n \t\t# value into 0x28(r1) which should be restored by the \"ld r2,0x28(r1)\" \n \t\t# which immediately follows calls which comply with the PPC64 ABI spec.\n \t\tlocal saveR2ptr = r1 + 0x28;\n \t\t*:8 saveR2ptr = r2Save; \n \t\n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_64_le.slaspec", "content": "# SLA specification file for PowerPC 64-bit little endian\n\n@define ENDIAN \"little\"\n\n@define REGISTER_SIZE \"8\"\n@define BIT_64 \"64\"\n@define EATRUNC \"ea:4\"\n\n@include \"ppc_common.sinc\"\n@include \"altivec.sinc\"\n@include \"g2.sinc\"\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_a2.sinc", "content": "\n# binutils: a2.d 88: 00 00 02 00 attn\n# binutils: power4_32.d 28: 00 00 02 00 attn\n# binutils: power4.d +64: 00 00 02 00 attn\n# binutils: power6.d 54: 00 00 02 00 attn\n# \"attn\",\tX(0,256),\tX_MASK, POWER4|PPCA2,\tPPC476,\t\t{0}\ndefine pcodeop attnOp;\n:attn is $(NOTVLE) & OP=0 & XOP_1_10=256 & BITS_11_25=0 { attnOp(); } \n\n# binutils: a2.d 214: 7d 4b 01 a6 eratwe r10,r11,0\n# binutils: a2.d 218: 7d 4b 19 a6 eratwe r10,r11,3\n# {\"eratwe\", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},\n# WS=> { 0x7, 11, NULL, NULL, 0 },\ndefine pcodeop eratweOp;\n:eratwe S,A is $(NOTVLE) & OP=31 & XOP_1_10=211 & S & A & BITS_11_13 & BITS_14_15 & BIT_0=0 { eratweOp(S,A); }\n\n# binutils: a2.d 200: 7d 4b 66 66 erativax r10,r11,r12\n# \"erativax\",\tX(31,819),\tX_MASK,\t PPCA2,\tPPCNONE,\t{RS, RA0, RB}\ndefine pcodeop erativaxOp;\n:erativax S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=819 & S & A & B { erativaxOp(S,A,B); } \n\n# binutils: a2.d 1f4: 7c 0a 58 66 eratilx 0,r10,r11\n# binutils: a2.d 1f8: 7c 2a 58 66 eratilx 1,r10,r11\n# binutils: a2.d 1fc: 7c ea 58 66 eratilx 7,r10,r11\n# \"eratilx\",\tX(31,51),\tX_MASK,\t PPCA2,\tPPCNONE,\t{ERAT_T, RA, RB}\ndefine pcodeop eratilxOp;\n:eratilx BITS_21_23,A,B is $(NOTVLE) & OP=31 & XOP_1_10=51 & BITS_21_23 & A & B { eratilxOp(A,B); } \n\n# binutils: a2.d 210: 7d 4b 61 26 eratsx r10,r11,r12\n# \"eratsx\",\tXRC(31,147,0),\tX_MASK,\t PPCA2,\tPPCNONE,\t{RT, RA0, RB}\ndefine pcodeop eratsxOp;\n:eratsx TH,A,B is $(NOTVLE) & OP=31 & XOP_1_10=147 & Rc=0 & TH & A & B { eratsxOp(TH,A,B); } \n\n# binutils: a2.d 20c: 7d 4b 61 27 eratsx\\. r10,r11,r12\n# \"eratsx.\",\tXRC(31,147,1),\tX_MASK,\t PPCA2,\tPPCNONE,\t{RT, RA0, RB}\ndefine pcodeop eratsxXOp;\n:eratsx. TH,A,B is $(NOTVLE) & OP=31 & XOP_1_10=147 & Rc=1 & TH & A & B { eratsxXOp(TH,A,B); } \n\n# \"eratre\",\tX(31,179),\t# binutils: a2.d 204: 7d 4b 01 66 eratre r10,r11,0\n# binutils: a2.d 208: 7d 4b 19 66 eratre r10,r11,3 \ndefine pcodeop eratreOp;\n:eratre TH,A,BITS_11_13 is $(NOTVLE) & OP=31 & XOP_1_10=179 & TH & A & BITS_11_13 { eratreOp(TH,A); } \n\n# binutils: a2.d 3e0: 7d 4b 63 2c icswx r10,r11,r12\n# \"icswx\",\tXRC(31,406,0),\tX_MASK, POWER7|PPCA2,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop icswxOp;\n:icswx S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=406 & Rc=0 & S & A & B { icswxOp(S,A,B); } \n\n# binutils: a2.d 3dc: 7d 4b 63 2d icswx\\. r10,r11,r12\n# \"icswx.\",\tXRC(31,406,1),\tX_MASK, POWER7|PPCA2,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop icswxDotOp;\n:icswx. S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=406 & Rc=1 & S & A & B { icswxDotOp(S,A,B); } \n\n# binutils: 476.d 49c: 7c 85 02 06 mfdcrx r4,r5\n# binutils: a2.d 520: 7d 4b 02 06 mfdcrx r10,r11\n# binutils: booke.d 28: 7c 85 02 06 mfdcrx r4,r5\n# binutils: booke_xcoff.d 24: 7c 85 02 06 mfdcrx r4,r5\n# \"mfdcrx\",\tX(31,259),\tX_MASK, BOOKE|PPCA2|PPC476, TITAN,\t{S, A}\ndefine pcodeop mfdcrxOp;\n# :mfdcrx S,A is $(NOTVLE) & OP=31 & XOP_1_10=259 & S & A & BITS_11_15=0 { mfdcrxOp(S,A); } \n\n# binutils: a2.d 51c: 7d 4b 02 07 mfdcrx\\. r10,r11\n# \"mfdcrx\",\tX(31,259),\tX_MASK, BOOKE|PPCA2|PPC476, TITAN,\t{RS, RA}\ndefine pcodeop mfdcrxDotOp;\n:mfdcrx. S,A is $(NOTVLE) & OP=31 & XOP_1_10=259 & Rc=1 & S & A & BITS_11_15=0 { mfdcrxDotOp(S,A); } \n\n# binutils: a2.d 564: 7d 6a 03 07 mtdcrx\\. r10,r11\ndefine pcodeop mtdcrxDotOp;\n:mtdcrx. A,S is $(NOTVLE) & OP=31 & XOP_1_10=387 & A & S & Rc=1 { mtdcrxDotOp(A,S); } \n\n# binutils: a2.d 884: 7c 00 01 6c wchkall \n# binutils: a2.d 888: 7c 00 01 6c wchkall \n# binutils: a2.d 88c: 7d 80 01 6c wchkall cr3\n# \"wchkall\",\tX(31,182),\tX_MASK, PPCA2,\tPPCNONE,\t{OBF}\ndefine pcodeop wchkallOp;\n:wchkall BITS_23_25 is $(NOTVLE) & OP=31 & XOP_1_10=182 & BITS_23_25 { wchkallOp(); } \n\n# binutils: a2.d 894: 7c 20 07 4c wclrall 1\n# \"wclrall\",\tX(31,934),\tXRARB_MASK, PPCA2,\tPPCNONE,\t{L}\ndefine pcodeop wclrallOp;\n:wclrall L is $(NOTVLE) & OP=31 & XOP_1_10=934 & L { wclrallOp(); } \n\n# binutils: a2.d 890: 7c 2a 5f 4c wclr 1,r10,r11\n# \"wclr\",\tX(31,934),\tX_MASK,\t PPCA2,\tPPCNONE,\t{L, RA0, RB}\ndefine pcodeop wclrOp;\n# :wclr L,A,B is $(NOTVLE) & OP=31 & XOP_1_10=934 & L & A & B { wclrOp(); } \n\n# binutils: a2.d: 514: 7d 4a 3a 87 mfdcr\\. r10,234\n:mfdcr. D, DCRN\t\tis $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=1\n{\n\tD = DCRN;\n}\n\n# binutils: a2.d: 55c: 7d 4a 3b 87 mtdcr\\. 234,r10\n:mtdcr. DCRN, D\t\tis $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=451 & BIT_0=1\n{\n\tDCRN = D;\n}\n\n# binutils: a2.d: 188: 7d 4b 61 fe dcbtstep r10,r11,r12\n# binutils: e500mc.d: a0: 7c 64 29 fe dcbtstep r3,r4,r5\ndefine pcodeop DataCacheBlockTouchForStoreByExternalPID;\n:dcbtstep TH,A,B is OP=31 & TH & A & B & XOP_1_10=255 & BIT_0=0 {\n\tDataCacheBlockTouchForStoreByExternalPID(TH,A,B);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_common.sinc", "content": "# PowerPC assembly SLA spec (size agnostic)\n\n# version 1.0\n\ndefine endian=$(ENDIAN);\n\ndefine alignment=2;\n\n# -size: How many bytes make up an address\ndefine space ram type=ram_space size=$(REGISTER_SIZE) default;\n\n# -size: How many bytes do we need for register addressing \ndefine space register type=register_space size=4;\n\n# General registers (some pcode that follows depends on these registers being at\n# offset 0\n\ndefine register offset=0 size=$(REGISTER_SIZE) [ \n\tr0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15\n\tr16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ];\n\t\n@ifdef E500\n# Define 4-byte general purpose sub-registers (LSB) to be used by E500 compiler specification\n# which must restrict parameter/return passing to low 4-bytes of the 8-byte general purpose registers.\n@if ENDIAN == \"big\"\ndefine register offset=0 size=4 [ \n\t_\t_r0\t\t_\t_r1\t\t_\t_r2\t\t_\t_r3\t\t_\t_r4\t\t_\t_r5\t\t_\t_r6\t\t_\t_r7\t\t\n\t_\t_r8\t\t_\t_r9\t\t_\t_r10\t_\t_r11\t_\t_r12\t_\t_r13\t_\t_r14\t_\t_r15\n\t_ \t_r16 \t_ \t_r17 \t_ \t_r18 \t_ \t_r19 \t_ \t_r20 \t_ \t_r21 \t_ \t_r22 \t_ \t_r23 \n\t_ \t_r24 \t_ \t_r25 \t_ \t_r26 \t_ \t_r27 \t_ \t_r28 \t_ \t_r29 \t_ \t_r30 \t_ \t_r31 ];\n@else\ndefine register offset=0 size=4 [ \n\t_r0\t\t_\t_r1\t\t_\t_r2\t\t_\t_r3\t\t_\t_r4\t\t_\t_r5\t\t_\t_r6\t\t_\t_r7\t\t_\n\t_r8\t\t_\t_r9\t\t_\t_r10\t_\t_r11\t_\t_r12\t_\t_r13\t_\t_r14\t_\t_r15\t_\n\t_r16 \t_ \t_r17 \t_ \t_r18 \t_ \t_r19 \t_ \t_r20 \t_ \t_r21 \t_ \t_r22 \t_ \t_r23 \t_\n\t_r24 \t_ \t_r25 \t_ \t_r26 \t_ \t_r27 \t_ \t_r28 \t_ \t_r29 \t_ \t_r30 \t_ \t_r31 \t_ ];\n@endif\n@endif\n\n# XER flags\ndefine register offset=0x400 size=1 [ xer_so xer_ov xer_ov32 xer_ca xer_ca32 xer_count ];\n\t\ndefine register offset=0x500 size=1 [ fp_fx fp_fex fp_vx fp_ox\n\t\t\t\t fp_ux fp_zx fp_xx fp_vxsnan\n\t\t\t\t fp_vxisi fp_vxidi fp_vxzdz fp_vximz\n\t\t\t\t fp_vxvc fp_fr fp_fi fp_c\n\t\t\t\t fp_cc0 fp_cc1 fp_cc2 fp_cc3\n\t\t\t\t fp_reserve1 fp_vxsoft fp_vxsqrt fp_vxcvi\n\t\t\t\t fp_ve fp_oe fp_ue fp_ze\n\t\t\t\t fp_xe fp_ni fp_rn0 fp_rn1 ];\n\ndefine register offset = 0x700 size =$(REGISTER_SIZE) [MSR];\ndefine register offset = 0x720\tsize=$(REGISTER_SIZE) [RESERVE_ADDRESS];\ndefine register offset = 0x728 size=1 [RESERVE];\ndefine register offset = 0x730 size=1 [RESERVE_LENGTH];\n\n# Program Counter register: This register is not actually visible in the\n# API for powerpc but it is needed to create a consistent model for the debugger\ndefine register offset=0x780 size=$(REGISTER_SIZE) pc;\n\n@define SEG_REGISTER_BASE \"0x800\"\n# Segment Registers\ndefine register offset=$(SEG_REGISTER_BASE) size=4 [ sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 sr8 sr9 sr10 sr11 sr12 sr13 sr14 sr15 ];\n\n# Condition register flags\ndefine register offset=0x900 size=1 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 ];\ndefine register offset=0x900 size=8 [ crall ];\n\ndefine register offset=0x980 size=$(REGISTER_SIZE) [ tea ];\n\n# Fake storage used to help preserve r2 across function calls within the decompiler (see appropriate cspec)\ndefine register offset=0x988 size=$(REGISTER_SIZE) [ r2Save ];\n\n# Special Purpose Registers are defined with generic names with the exception of XER, LR, CTR, SRR0, SRR1, TBL(r/w), TBU(r/w)\n# These names may be replaced within register_data section within a PPC variant's pspec file\ndefine register offset=0x1000 size=$(REGISTER_SIZE) \n\t[ spr000 XER spr002 spr003 spr004 spr005 spr006 spr007 LR CTR spr00a spr00b spr00c spr00d spr00e spr00f \n\t spr010 spr011 spr012 spr013 spr014 spr015 spr016 spr017 spr018 spr019 SRR0 SRR1 spr01c spr01d spr01e spr01f \n\t spr020 spr021 spr022 spr023 spr024 spr025 spr026 spr027 spr028 spr029 spr02a spr02b spr02c spr02d spr02e spr02f\n\t spr030 spr031 spr032 spr033 spr034 spr035 spr036 spr037 spr038 spr039 CSRR0 CSRR1 spr03c spr03d spr03e spr03f\n\t spr040 spr041 spr042 spr043 spr044 spr045 spr046 spr047 spr048 spr049 spr04a spr04b spr04c spr04d spr04e spr04f\n\t spr050 spr051 spr052 spr053 spr054 spr055 spr056 spr057 spr058 spr059 spr05a spr05b spr05c spr05d spr05e spr05f\n\t spr060 spr061 spr062 spr063 spr064 spr065 spr066 spr067 spr068 spr069 spr06a spr06b spr06c spr06d spr06e spr06f\n\t spr070 spr071 spr072 spr073 spr074 spr075 spr076 spr077 spr078 spr079 spr07a spr07b spr07c spr07d spr07e spr07f\n\t spr080 spr081 spr082 spr083 spr084 spr085 spr086 spr087 spr088 spr089 spr08a spr08b spr08c spr08d spr08e spr08f\n\t spr090 spr091 spr092 spr093 spr094 spr095 spr096 spr097 spr098 spr099 spr09a spr09b spr09c spr09d spr09e spr09f\n\t spr0a0 spr0a1 spr0a2 spr0a3 spr0a4 spr0a5 spr0a6 spr0a7 spr0a8 spr0a9 spr0aa spr0ab spr0ac spr0ad spr0ae spr0af\n\t spr0b0 spr0b1 spr0b2 spr0b3 spr0b4 spr0b5 spr0b6 spr0b7 spr0b8 spr0b9 spr0ba spr0bb spr0bc spr0bd spr0be spr0bf\n\t spr0c0 spr0c1 spr0c2 spr0c3 spr0c4 spr0c5 spr0c6 spr0c7 spr0c8 spr0c9 spr0ca spr0cb spr0cc spr0cd spr0ce spr0cf\n\t spr0d0 spr0d1 spr0d2 spr0d3 spr0d4 spr0d5 spr0d6 spr0d7 spr0d8 spr0d9 spr0da spr0db spr0dc spr0dd spr0de spr0df\n\t spr0e0 spr0e1 spr0e2 spr0e3 spr0e4 spr0e5 spr0e6 spr0e7 spr0e8 spr0e9 spr0ea spr0eb spr0ec spr0ed spr0ee spr0ef\n\t spr0f0 spr0f1 spr0f2 spr0f3 spr0f4 spr0f5 spr0f6 spr0f7 spr0f8 spr0f9 spr0fa spr0fb spr0fc spr0fd spr0fe spr0ff\n\t spr100 spr101 spr102 spr103 spr104 spr105 spr106 spr107 spr108 spr109 spr10a spr10b TBLr TBUr spr10e spr10f\n\t spr110 spr111 spr112 spr113 spr114 spr115 spr116 spr117 spr118 spr119 spr11a spr11b TBLw TBUw\tspr11e spr11f \n\t spr120 spr121 spr122 spr123 spr124 spr125 spr126 spr127 spr128 spr129 spr12a spr12b spr12c spr12d spr12e spr12f\n\t spr130 spr131 spr132 spr133 spr134 spr135 spr136 spr137 spr138 spr139 spr13a spr13b spr13c spr13d spr13e spr13f\n\t spr140 spr141 spr142 spr143 spr144 spr145 spr146 spr147 spr148 spr149 spr14a spr14b spr14c spr14d spr14e spr14f\n\t spr150 spr151 spr152 spr153 spr154 spr155 spr156 spr157 spr158 spr159 spr15a spr15b spr15c spr15d spr15e spr15f\n\t spr160 spr161 spr162 spr163 spr164 spr165 spr166 spr167 spr168 spr169 spr16a spr16b spr16c spr16d spr16e spr16f\n\t spr170 spr171 spr172 spr173 spr174 spr175 spr176 spr177 spr178 spr179 spr17a spr17b spr17c spr17d spr17e spr17f\n\t spr180 spr181 spr182 spr183 spr184 spr185 spr186 spr187 spr188 spr189 spr18a spr18b spr18c spr18d spr18e spr18f\n\t spr190 spr191 spr192 spr193 spr194 spr195 spr196 spr197 spr198 spr199 spr19a spr19b spr19c spr19d spr19e spr19f\n\t spr1a0 spr1a1 spr1a2 spr1a3 spr1a4 spr1a5 spr1a6 spr1a7 spr1a8 spr1a9 spr1aa spr1ab spr1ac spr1ad spr1ae spr1af\n\t spr1b0 spr1b1 spr1b2 spr1b3 spr1b4 spr1b5 spr1b6 spr1b7 spr1b8 spr1b9 spr1ba spr1bb spr1bc spr1bd spr1be spr1bf\n\t spr1c0 spr1c1 spr1c2 spr1c3 spr1c4 spr1c5 spr1c6 spr1c7 spr1c8 spr1c9 spr1ca spr1cb spr1cc spr1cd spr1ce spr1cf\n\t spr1d0 spr1d1 spr1d2 spr1d3 spr1d4 spr1d5 spr1d6 spr1d7 spr1d8 spr1d9 spr1da spr1db spr1dc spr1dd spr1de spr1df\n\t spr1e0 spr1e1 spr1e2 spr1e3 spr1e4 spr1e5 spr1e6 spr1e7 spr1e8 spr1e9 spr1ea spr1eb spr1ec spr1ed spr1ee spr1ef\n\t spr1f0 spr1f1 spr1f2 spr1f3 spr1f4 spr1f5 spr1f6 spr1f7 spr1f8 spr1f9 spr1fa spr1fb spr1fc spr1fd spr1fe spr1ff\n\t spr200 spr201 spr202 spr203 spr204 spr205 spr206 spr207 spr208 spr209 spr20a spr20b spr20c spr20d spr20e spr20f\n\t spr210 spr211 spr212 spr213 spr214 spr215 spr216 spr217 spr218 spr219 spr21a spr21b spr21c spr21d spr21e spr21f\n\t spr220 spr221 spr222 spr223 spr224 spr225 spr226 spr227 spr228 spr229 spr22a spr22b spr22c spr22d spr22e spr22f\n\t spr230 spr231 spr232 spr233 spr234 spr235 spr236 spr237 spr238 spr239 spr23a spr23b spr23c spr23d spr23e spr23f \n\t spr240 spr241 spr242 spr243 spr244 spr245 spr246 spr247 spr248 spr249 spr24a spr24b spr24c spr24d spr24e spr24f\n\t spr250 spr251 spr252 spr253 spr254 spr255 spr256 spr257 spr258 spr259 spr25a spr25b spr25c spr25d spr25e spr25f\n\t spr260 spr261 spr262 spr263 spr264 spr265 spr266 spr267 spr268 spr269 spr26a spr26b spr26c spr26d spr26e spr26f\n\t spr270 spr271 spr272 spr273 spr274 spr275 spr276 spr277 spr278 spr279 spr27a spr27b spr27c spr27d spr27e spr27f\n\t spr280 spr281 spr282 spr283 spr284 spr285 spr286 spr287 spr288 spr289 spr28a spr28b spr28c spr28d spr28e spr28f\n\t spr290 spr291 spr292 spr293 spr294 spr295 spr296 spr297 spr298 spr299 spr29a spr29b spr29c spr29d spr29e spr29f\n\t spr2a0 spr2a1 spr2a2 spr2a3 spr2a4 spr2a5 spr2a6 spr2a7 spr2a8 spr2a9 spr2aa spr2ab spr2ac spr2ad spr2ae spr2af\n\t spr2b0 spr2b1 spr2b2 spr2b3 spr2b4 spr2b5 spr2b6 spr2b7 spr2b8 spr2b9 spr2ba spr2bb spr2bc spr2bd spr2be spr2bf\n\t spr2c0 spr2c1 spr2c2 spr2c3 spr2c4 spr2c5 spr2c6 spr2c7 spr2c8 spr2c9 spr2ca spr2cb spr2cc spr2cd spr2ce spr2cf\n\t spr2d0 spr2d1 spr2d2 spr2d3 spr2d4 spr2d5 spr2d6 spr2d7 spr2d8 spr2d9 spr2da spr2db spr2dc spr2dd spr2de spr2df\n\t spr2e0 spr2e1 spr2e2 spr2e3 spr2e4 spr2e5 spr2e6 spr2e7 spr2e8 spr2e9 spr2ea spr2eb spr2ec spr2ed spr2ee spr2ef\n\t spr2f0 spr2f1 spr2f2 spr2f3 spr2f4 spr2f5 spr2f6 spr2f7 spr2f8 spr2f9 spr2fa spr2fb spr2fc spr2fd spr2fe spr2ff\n\t spr300 spr301 spr302 spr303 spr304 spr305 spr306 spr307 spr308 spr309 spr30a spr30b spr30c spr30d spr30e spr30f\n\t spr310 spr311 spr312 spr313 spr314 spr315 spr316 spr317 spr318 spr319 spr31a spr31b spr31c spr31d spr31e spr31f\n\t spr320 spr321 spr322 spr323 spr324 spr325 spr326 spr327 spr328 spr329 spr32a spr32b spr32c spr32d spr32e TAR\n\t spr330 spr331 spr332 spr333 spr334 spr335 spr336 spr337 spr338 spr339 spr33a spr33b spr33c spr33d spr33e spr33f\n\t spr340 spr341 spr342 spr343 spr344 spr345 spr346 spr347 spr348 spr349 spr34a spr34b spr34c spr34d spr34e spr34f\n\t spr350 spr351 spr352 spr353 spr354 spr355 spr356 spr357 spr358 spr359 spr35a spr35b spr35c spr35d spr35e spr35f\n\t spr360 spr361 spr362 spr363 spr364 spr365 spr366 spr367 spr368 spr369 spr36a spr36b spr36c spr36d spr36e spr36f\n\t spr370 spr371 spr372 spr373 spr374 spr375 spr376 spr377 spr378 spr379 spr37a spr37b spr37c spr37d spr37e spr37f\n\t spr380 spr381 spr382 spr383 spr384 spr385 spr386 spr387 spr388 spr389 spr38a spr38b spr38c spr38d spr38e spr38f\n\t spr390 spr391 spr392 spr393 spr394 spr395 spr396 spr397 spr398 spr399 spr39a spr39b spr39c spr39d spr39e spr39f\n\t spr3a0 spr3a1 spr3a2 spr3a3 spr3a4 spr3a5 spr3a6 spr3a7 spr3a8 spr3a9 spr3aa spr3ab spr3ac spr3ad spr3ae spr3af\n\t spr3b0 spr3b1 spr3b2 spr3b3 spr3b4 spr3b5 spr3b6 spr3b7 spr3b8 spr3b9 spr3ba spr3bb spr3bc spr3bd spr3be spr3bf\n\t spr3c0 spr3c1 spr3c2 spr3c3 spr3c4 spr3c5 spr3c6 spr3c7 spr3c8 spr3c9 spr3ca spr3cb spr3cc spr3cd spr3ce spr3cf\n\t spr3d0 spr3d1 spr3d2 spr3d3 spr3d4 spr3d5 spr3d6 spr3d7 spr3d8 spr3d9 spr3da spr3db spr3dc spr3dd spr3de spr3df\n\t spr3e0 spr3e1 spr3e2 spr3e3 spr3e4 spr3e5 spr3e6 spr3e7 spr3e8 spr3e9 spr3ea spr3eb spr3ec spr3ed spr3ee spr3ef\n\t spr3f0 spr3f1 spr3f2 spr3f3 spr3f4 spr3f5 spr3f6 spr3f7 spr3f8 spr3f9 spr3fa spr3fb spr3fc spr3fd spr3fe spr3ff\n\t];\n\n\n# The floating point registers and the altivec vector registers OVERLAP to VSX registers\n# This was not done correctly before and has now been fixed. Book 1, Chapter 7.2 has a\n# very good diagram. \n\n# Support for Vector-Scalar Extension - i.e \"VSX\"\n\ndefine register offset=0x4000 size=16 \n\t[ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15 \n vs16 vs17 vs18 vs19 vs20 vs21 vs22 vs23 vs24 vs25 vs26 vs27 vs28 vs29 vs30 vs31 \n vs32 vs33 vs34 vs35 vs36 vs37 vs38 vs39 vs40 vs41 vs42 vs43 vs44 vs45 vs46 vs47 \n vs48 vs49 vs50 vs51 vs52 vs53 vs54 vs55 vs56 vs57 vs58 vs59 vs60 vs61 vs62 vs63 \n ];\n# Floating point registers\t\n# These overlay the first 32 vsx regs with the gaps as indicated so fr0 is in vs0, fr1 is in vs1, etc.\n# This also means we have to have 2 defs of this due to endian stuff.\n@if ENDIAN == \"big\"\ndefine register offset=0x4000 size=8 [ \n\tf0 _ f1 _ f2 _ f3 _ f4 _ f5 _ f6 _ f7 _ f8 _ f9 _ f10 _ f11 _ f12 _ f13 _ f14 _ f15 _\n\tf16 _ f17 _ f18 _ f19 _ f20 _ f21 _ f22 _ f23 _ f24 _ f25 _ f26 _ f27 _ f28 _ f29 _ f30 _ f31 _ ];\n\t\n@else\ndefine register offset=0x4000 size=8 [ \n\t_ f0 _ f1 _ f2 _ f3 _ f4 _ f5 _ f6 _ f7 _ f8 _ f9 _ f10 _ f11 _ f12 _ f13 _ f14 _ f15 \n\t_ f16 _ f17 _ f18 _ f19 _ f20 _ f21 _ f22 _ f23 _ f24 _ f25 _ f26 _ f27 _ f28 _ f29 _ f30 _ f31 ];\n@endif\n\n# All the altivec regs need to start at offset 0x4200\n# Sleigh does not allow registers of the same size to overlay. This presents some issues as the normal\n# Altivec registers overlay the top 32 VSX registers. What we have to do is use a sub-table to display\n# the Altivec name, but export the matching VSX register. The original vrD, etc. tokens are now sub-tables.\n\n# Altivec vector registers (accessed by vrD vrA vrB vrS vrC)\n# Altivec vector registers\n#define register offset=0x4200 size=16 [ \n#\tv0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n#\tv16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];\n\n@if ENDIAN == \"big\"\n\n# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 8 byte subregisters\ndefine register offset=0x4200 size=8 [ # 64 bit access to vrN registers (psydo-registers) (accessed by vrD_64_N vrA_64_N vrB_64_N vrS_64_N vrC_64_N)\nvr0_64_0 vr0_64_1 \nvr1_64_0 vr1_64_1 \nvr2_64_0 vr2_64_1 \nvr3_64_0 vr3_64_1 \nvr4_64_0 vr4_64_1 \nvr5_64_0 vr5_64_1 \nvr6_64_0 vr6_64_1 \nvr7_64_0 vr7_64_1 \nvr8_64_0 vr8_64_1 \nvr9_64_0 vr9_64_1 \nvr10_64_0 vr10_64_1 \nvr11_64_0 vr11_64_1 \nvr12_64_0 vr12_64_1 \nvr13_64_0 vr13_64_1 \nvr14_64_0 vr14_64_1 \nvr15_64_0 vr15_64_1 \nvr16_64_0 vr16_64_1 \nvr17_64_0 vr17_64_1 \nvr18_64_0 vr18_64_1 \nvr19_64_0 vr19_64_1 \nvr20_64_0 vr20_64_1 \nvr21_64_0 vr21_64_1 \nvr22_64_0 vr22_64_1 \nvr23_64_0 vr23_64_1 \nvr24_64_0 vr24_64_1 \nvr25_64_0 vr25_64_1 \nvr26_64_0 vr26_64_1 \nvr27_64_0 vr27_64_1 \nvr28_64_0 vr28_64_1 \nvr29_64_0 vr29_64_1 \nvr30_64_0 vr30_64_1 \nvr31_64_0 vr31_64_1 \n];\n\n# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 4 byte subregisters\ndefine register offset=0x4200 size=4 [ # 32 bit access to vrN registers (psydo-registers) (accessed by vrD_32_N vrA_32_N vrB_32_N vrS_32_N vrC_32_N)\nvr0_32_0 vr0_32_1 vr0_32_2 vr0_32_3 \nvr1_32_0 vr1_32_1 vr1_32_2 vr1_32_3 \nvr2_32_0 vr2_32_1 vr2_32_2 vr2_32_3 \nvr3_32_0 vr3_32_1 vr3_32_2 vr3_32_3 \nvr4_32_0 vr4_32_1 vr4_32_2 vr4_32_3 \nvr5_32_0 vr5_32_1 vr5_32_2 vr5_32_3 \nvr6_32_0 vr6_32_1 vr6_32_2 vr6_32_3 \nvr7_32_0 vr7_32_1 vr7_32_2 vr7_32_3 \nvr8_32_0 vr8_32_1 vr8_32_2 vr8_32_3 \nvr9_32_0 vr9_32_1 vr9_32_2 vr9_32_3 \nvr10_32_0 vr10_32_1 vr10_32_2 vr10_32_3 \nvr11_32_0 vr11_32_1 vr11_32_2 vr11_32_3 \nvr12_32_0 vr12_32_1 vr12_32_2 vr12_32_3 \nvr13_32_0 vr13_32_1 vr13_32_2 vr13_32_3 \nvr14_32_0 vr14_32_1 vr14_32_2 vr14_32_3 \nvr15_32_0 vr15_32_1 vr15_32_2 vr15_32_3 \nvr16_32_0 vr16_32_1 vr16_32_2 vr16_32_3 \nvr17_32_0 vr17_32_1 vr17_32_2 vr17_32_3 \nvr18_32_0 vr18_32_1 vr18_32_2 vr18_32_3 \nvr19_32_0 vr19_32_1 vr19_32_2 vr19_32_3 \nvr20_32_0 vr20_32_1 vr20_32_2 vr20_32_3 \nvr21_32_0 vr21_32_1 vr21_32_2 vr21_32_3 \nvr22_32_0 vr22_32_1 vr22_32_2 vr22_32_3 \nvr23_32_0 vr23_32_1 vr23_32_2 vr23_32_3 \nvr24_32_0 vr24_32_1 vr24_32_2 vr24_32_3 \nvr25_32_0 vr25_32_1 vr25_32_2 vr25_32_3 \nvr26_32_0 vr26_32_1 vr26_32_2 vr26_32_3 \nvr27_32_0 vr27_32_1 vr27_32_2 vr27_32_3 \nvr28_32_0 vr28_32_1 vr28_32_2 vr28_32_3 \nvr29_32_0 vr29_32_1 vr29_32_2 vr29_32_3 \nvr30_32_0 vr30_32_1 vr30_32_2 vr30_32_3 \nvr31_32_0 vr31_32_1 vr31_32_2 vr31_32_3 \n];\n\n# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 2 byte subregisters\ndefine register offset=0x4200 size=2 [ # 16 bit access to vrN registers (psydo-registers) (accessed by vrD_16_N vrA_16_N vrB_16_N vrS_16_N vrC_16_N)\nvr0_16_0 vr0_16_1 vr0_16_2 vr0_16_3 vr0_16_4 vr0_16_5 vr0_16_6 vr0_16_7 \nvr1_16_0 vr1_16_1 vr1_16_2 vr1_16_3 vr1_16_4 vr1_16_5 vr1_16_6 vr1_16_7\t\nvr2_16_0 vr2_16_1 vr2_16_2 vr2_16_3 vr2_16_4 vr2_16_5 vr2_16_6 vr2_16_7 \nvr3_16_0 vr3_16_1 vr3_16_2 vr3_16_3 vr3_16_4 vr3_16_5 vr3_16_6 vr3_16_7 \nvr4_16_0 vr4_16_1 vr4_16_2 vr4_16_3 vr4_16_4 vr4_16_5 vr4_16_6 vr4_16_7 \nvr5_16_0 vr5_16_1 vr5_16_2 vr5_16_3 vr5_16_4 vr5_16_5 vr5_16_6 vr5_16_7 \nvr6_16_0 vr6_16_1 vr6_16_2 vr6_16_3 vr6_16_4 vr6_16_5 vr6_16_6 vr6_16_7 \nvr7_16_0 vr7_16_1 vr7_16_2 vr7_16_3 vr7_16_4 vr7_16_5 vr7_16_6 vr7_16_7 \nvr8_16_0 vr8_16_1 vr8_16_2 vr8_16_3 vr8_16_4 vr8_16_5 vr8_16_6 vr8_16_7 \nvr9_16_0 vr9_16_1 vr9_16_2 vr9_16_3 vr9_16_4 vr9_16_5 vr9_16_6 vr9_16_7 \nvr10_16_0 vr10_16_1 vr10_16_2 vr10_16_3 vr10_16_4 vr10_16_5 vr10_16_6 vr10_16_7 \nvr11_16_0 vr11_16_1 vr11_16_2 vr11_16_3 vr11_16_4 vr11_16_5 vr11_16_6 vr11_16_7 \nvr12_16_0 vr12_16_1 vr12_16_2 vr12_16_3 vr12_16_4 vr12_16_5 vr12_16_6 vr12_16_7 \nvr13_16_0 vr13_16_1 vr13_16_2 vr13_16_3 vr13_16_4 vr13_16_5 vr13_16_6 vr13_16_7 \nvr14_16_0 vr14_16_1 vr14_16_2 vr14_16_3 vr14_16_4 vr14_16_5 vr14_16_6 vr14_16_7 \nvr15_16_0 vr15_16_1 vr15_16_2 vr15_16_3 vr15_16_4 vr15_16_5 vr15_16_6 vr15_16_7 \nvr16_16_0 vr16_16_1 vr16_16_2 vr16_16_3 vr16_16_4 vr16_16_5 vr16_16_6 vr16_16_7 \nvr17_16_0 vr17_16_1 vr17_16_2 vr17_16_3 vr17_16_4 vr17_16_5 vr17_16_6 vr17_16_7 \nvr18_16_0 vr18_16_1 vr18_16_2 vr18_16_3 vr18_16_4 vr18_16_5 vr18_16_6 vr18_16_7 \nvr19_16_0 vr19_16_1 vr19_16_2 vr19_16_3 vr19_16_4 vr19_16_5 vr19_16_6 vr19_16_7 \nvr20_16_0 vr20_16_1 vr20_16_2 vr20_16_3 vr20_16_4 vr20_16_5 vr20_16_6 vr20_16_7 \nvr21_16_0 vr21_16_1 vr21_16_2 vr21_16_3 vr21_16_4 vr21_16_5 vr21_16_6 vr21_16_7 \nvr22_16_0 vr22_16_1 vr22_16_2 vr22_16_3 vr22_16_4 vr22_16_5 vr22_16_6 vr22_16_7 \nvr23_16_0 vr23_16_1 vr23_16_2 vr23_16_3 vr23_16_4 vr23_16_5 vr23_16_6 vr23_16_7 \nvr24_16_0 vr24_16_1 vr24_16_2 vr24_16_3 vr24_16_4 vr24_16_5 vr24_16_6 vr24_16_7 \nvr25_16_0 vr25_16_1 vr25_16_2 vr25_16_3 vr25_16_4 vr25_16_5 vr25_16_6 vr25_16_7 \nvr26_16_0 vr26_16_1 vr26_16_2 vr26_16_3 vr26_16_4 vr26_16_5 vr26_16_6 vr26_16_7 \nvr27_16_0 vr27_16_1 vr27_16_2 vr27_16_3 vr27_16_4 vr27_16_5 vr27_16_6 vr27_16_7 \nvr28_16_0 vr28_16_1 vr28_16_2 vr28_16_3 vr28_16_4 vr28_16_5 vr28_16_6 vr28_16_7 \nvr29_16_0 vr29_16_1 vr29_16_2 vr29_16_3 vr29_16_4 vr29_16_5 vr29_16_6 vr29_16_7 \nvr30_16_0 vr30_16_1 vr30_16_2 vr30_16_3 vr30_16_4 vr30_16_5 vr30_16_6 vr30_16_7 \nvr31_16_0 vr31_16_1 vr31_16_2 vr31_16_3 vr31_16_4 vr31_16_5 vr31_16_6 vr31_16_7 \n];\n\n# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 1 byte subregisters\ndefine register offset=0x4200 size=1 [ # 8 bit access to vrN registers (psydo-registers) (accessed by vrD_8_N vrA_8_N vrB_8_N vrS_8_N vrC_8_N)\nvr0_8_0 vr0_8_1 vr0_8_2 vr0_8_3 vr0_8_4 vr0_8_5 vr0_8_6 vr0_8_7 vr0_8_8 vr0_8_9 vr0_8_10 vr0_8_11 vr0_8_12 vr0_8_13 vr0_8_14 vr0_8_15 \nvr1_8_0 vr1_8_1 vr1_8_2 vr1_8_3 vr1_8_4 vr1_8_5 vr1_8_6 vr1_8_7 vr1_8_8 vr1_8_9 vr1_8_10 vr1_8_11 vr1_8_12 vr1_8_13 vr1_8_14 vr1_8_15 \nvr2_8_0 vr2_8_1 vr2_8_2 vr2_8_3 vr2_8_4 vr2_8_5 vr2_8_6 vr2_8_7 vr2_8_8 vr2_8_9 vr2_8_10 vr2_8_11 vr2_8_12 vr2_8_13 vr2_8_14 vr2_8_15 \nvr3_8_0 vr3_8_1 vr3_8_2 vr3_8_3 vr3_8_4 vr3_8_5 vr3_8_6 vr3_8_7 vr3_8_8 vr3_8_9 vr3_8_10 vr3_8_11 vr3_8_12 vr3_8_13 vr3_8_14 vr3_8_15 \nvr4_8_0 vr4_8_1 vr4_8_2 vr4_8_3 vr4_8_4 vr4_8_5 vr4_8_6 vr4_8_7 vr4_8_8 vr4_8_9 vr4_8_10 vr4_8_11 vr4_8_12 vr4_8_13 vr4_8_14 vr4_8_15 \nvr5_8_0 vr5_8_1 vr5_8_2 vr5_8_3 vr5_8_4 vr5_8_5 vr5_8_6 vr5_8_7 vr5_8_8 vr5_8_9 vr5_8_10 vr5_8_11 vr5_8_12 vr5_8_13 vr5_8_14 vr5_8_15 \nvr6_8_0 vr6_8_1 vr6_8_2 vr6_8_3 vr6_8_4 vr6_8_5 vr6_8_6 vr6_8_7 vr6_8_8 vr6_8_9 vr6_8_10 vr6_8_11 vr6_8_12 vr6_8_13 vr6_8_14 vr6_8_15 \nvr7_8_0 vr7_8_1 vr7_8_2 vr7_8_3 vr7_8_4 vr7_8_5 vr7_8_6 vr7_8_7 vr7_8_8 vr7_8_9 vr7_8_10 vr7_8_11 vr7_8_12 vr7_8_13 vr7_8_14 vr7_8_15 \nvr8_8_0 vr8_8_1 vr8_8_2 vr8_8_3 vr8_8_4 vr8_8_5 vr8_8_6 vr8_8_7 vr8_8_8 vr8_8_9 vr8_8_10 vr8_8_11 vr8_8_12 vr8_8_13 vr8_8_14 vr8_8_15 \nvr9_8_0 vr9_8_1 vr9_8_2 vr9_8_3 vr9_8_4 vr9_8_5 vr9_8_6 vr9_8_7 vr9_8_8 vr9_8_9 vr9_8_10 vr9_8_11 vr9_8_12 vr9_8_13 vr9_8_14 vr9_8_15 \nvr10_8_0 vr10_8_1 vr10_8_2 vr10_8_3 vr10_8_4 vr10_8_5 vr10_8_6 vr10_8_7 vr10_8_8 vr10_8_9 vr10_8_10 vr10_8_11 vr10_8_12 vr10_8_13 vr10_8_14 vr10_8_15 \nvr11_8_0 vr11_8_1 vr11_8_2 vr11_8_3 vr11_8_4 vr11_8_5 vr11_8_6 vr11_8_7 vr11_8_8 vr11_8_9 vr11_8_10 vr11_8_11 vr11_8_12 vr11_8_13 vr11_8_14 vr11_8_15 \nvr12_8_0 vr12_8_1 vr12_8_2 vr12_8_3 vr12_8_4 vr12_8_5 vr12_8_6 vr12_8_7 vr12_8_8 vr12_8_9 vr12_8_10 vr12_8_11 vr12_8_12 vr12_8_13 vr12_8_14 vr12_8_15 \nvr13_8_0 vr13_8_1 vr13_8_2 vr13_8_3 vr13_8_4 vr13_8_5 vr13_8_6 vr13_8_7 vr13_8_8 vr13_8_9 vr13_8_10 vr13_8_11 vr13_8_12 vr13_8_13 vr13_8_14 vr13_8_15 \nvr14_8_0 vr14_8_1 vr14_8_2 vr14_8_3 vr14_8_4 vr14_8_5 vr14_8_6 vr14_8_7 vr14_8_8 vr14_8_9 vr14_8_10 vr14_8_11 vr14_8_12 vr14_8_13 vr14_8_14 vr14_8_15 \nvr15_8_0 vr15_8_1 vr15_8_2 vr15_8_3 vr15_8_4 vr15_8_5 vr15_8_6 vr15_8_7 vr15_8_8 vr15_8_9 vr15_8_10 vr15_8_11 vr15_8_12 vr15_8_13 vr15_8_14 vr15_8_15 \nvr16_8_0 vr16_8_1 vr16_8_2 vr16_8_3 vr16_8_4 vr16_8_5 vr16_8_6 vr16_8_7 vr16_8_8 vr16_8_9 vr16_8_10 vr16_8_11 vr16_8_12 vr16_8_13 vr16_8_14 vr16_8_15 \nvr17_8_0 vr17_8_1 vr17_8_2 vr17_8_3 vr17_8_4 vr17_8_5 vr17_8_6 vr17_8_7 vr17_8_8 vr17_8_9 vr17_8_10 vr17_8_11 vr17_8_12 vr17_8_13 vr17_8_14 vr17_8_15 \nvr18_8_0 vr18_8_1 vr18_8_2 vr18_8_3 vr18_8_4 vr18_8_5 vr18_8_6 vr18_8_7 vr18_8_8 vr18_8_9 vr18_8_10 vr18_8_11 vr18_8_12 vr18_8_13 vr18_8_14 vr18_8_15 \nvr19_8_0 vr19_8_1 vr19_8_2 vr19_8_3 vr19_8_4 vr19_8_5 vr19_8_6 vr19_8_7 vr19_8_8 vr19_8_9 vr19_8_10 vr19_8_11 vr19_8_12 vr19_8_13 vr19_8_14 vr19_8_15 \nvr20_8_0 vr20_8_1 vr20_8_2 vr20_8_3 vr20_8_4 vr20_8_5 vr20_8_6 vr20_8_7 vr20_8_8 vr20_8_9 vr20_8_10 vr20_8_11 vr20_8_12 vr20_8_13 vr20_8_14 vr20_8_15 \nvr21_8_0 vr21_8_1 vr21_8_2 vr21_8_3 vr21_8_4 vr21_8_5 vr21_8_6 vr21_8_7 vr21_8_8 vr21_8_9 vr21_8_10 vr21_8_11 vr21_8_12 vr21_8_13 vr21_8_14 vr21_8_15 \nvr22_8_0 vr22_8_1 vr22_8_2 vr22_8_3 vr22_8_4 vr22_8_5 vr22_8_6 vr22_8_7 vr22_8_8 vr22_8_9 vr22_8_10 vr22_8_11 vr22_8_12 vr22_8_13 vr22_8_14 vr22_8_15 \nvr23_8_0 vr23_8_1 vr23_8_2 vr23_8_3 vr23_8_4 vr23_8_5 vr23_8_6 vr23_8_7 vr23_8_8 vr23_8_9 vr23_8_10 vr23_8_11 vr23_8_12 vr23_8_13 vr23_8_14 vr23_8_15 \nvr24_8_0 vr24_8_1 vr24_8_2 vr24_8_3 vr24_8_4 vr24_8_5 vr24_8_6 vr24_8_7 vr24_8_8 vr24_8_9 vr24_8_10 vr24_8_11 vr24_8_12 vr24_8_13 vr24_8_14 vr24_8_15 \nvr25_8_0 vr25_8_1 vr25_8_2 vr25_8_3 vr25_8_4 vr25_8_5 vr25_8_6 vr25_8_7 vr25_8_8 vr25_8_9 vr25_8_10 vr25_8_11 vr25_8_12 vr25_8_13 vr25_8_14 vr25_8_15 \nvr26_8_0 vr26_8_1 vr26_8_2 vr26_8_3 vr26_8_4 vr26_8_5 vr26_8_6 vr26_8_7 vr26_8_8 vr26_8_9 vr26_8_10 vr26_8_11 vr26_8_12 vr26_8_13 vr26_8_14 vr26_8_15 \nvr27_8_0 vr27_8_1 vr27_8_2 vr27_8_3 vr27_8_4 vr27_8_5 vr27_8_6 vr27_8_7 vr27_8_8 vr27_8_9 vr27_8_10 vr27_8_11 vr27_8_12 vr27_8_13 vr27_8_14 vr27_8_15 \nvr28_8_0 vr28_8_1 vr28_8_2 vr28_8_3 vr28_8_4 vr28_8_5 vr28_8_6 vr28_8_7 vr28_8_8 vr28_8_9 vr28_8_10 vr28_8_11 vr28_8_12 vr28_8_13 vr28_8_14 vr28_8_15 \nvr29_8_0 vr29_8_1 vr29_8_2 vr29_8_3 vr29_8_4 vr29_8_5 vr29_8_6 vr29_8_7 vr29_8_8 vr29_8_9 vr29_8_10 vr29_8_11 vr29_8_12 vr29_8_13 vr29_8_14 vr29_8_15 \nvr30_8_0 vr30_8_1 vr30_8_2 vr30_8_3 vr30_8_4 vr30_8_5 vr30_8_6 vr30_8_7 vr30_8_8 vr30_8_9 vr30_8_10 vr30_8_11 vr30_8_12 vr30_8_13 vr30_8_14 vr30_8_15 \nvr31_8_0 vr31_8_1 vr31_8_2 vr31_8_3 vr31_8_4 vr31_8_5 vr31_8_6 vr31_8_7 vr31_8_8 vr31_8_9 vr31_8_10 vr31_8_11 vr31_8_12 vr31_8_13 vr31_8_14 vr31_8_15 \n];\n@else\ndefine register offset=0x4200 size=8 [ # 64 bit access to vrN registers (psydo-registers) (accessed by vrD_64_N vrA_64_N vrB_64_N vrS_64_N vrC_64_N)\nvr0_64_1 vr0_64_0 \nvr1_64_1 vr1_64_0 \nvr2_64_1 vr2_64_0 \nvr3_64_1 vr3_64_0 \nvr4_64_1 vr4_64_0 \nvr5_64_1 vr5_64_0 \nvr6_64_1 vr6_64_0 \nvr7_64_1 vr7_64_0 \nvr8_64_1 vr8_64_0 \nvr9_64_1 vr9_64_0 \nvr10_64_1 vr10_64_0 \nvr11_64_1 vr11_64_0 \nvr12_64_1 vr12_64_0 \nvr13_64_1 vr13_64_0 \nvr14_64_1 vr14_64_0 \nvr15_64_1 vr15_64_0 \nvr16_64_1 vr16_64_0 \nvr17_64_1 vr17_64_0 \nvr18_64_1 vr18_64_0 \nvr19_64_1 vr19_64_0 \nvr20_64_1 vr20_64_0 \nvr21_64_1 vr21_64_0 \nvr22_64_1 vr22_64_0 \nvr23_64_1 vr23_64_0 \nvr24_64_1 vr24_64_0 \nvr25_64_1 vr25_64_0 \nvr26_64_1 vr26_64_0 \nvr27_64_1 vr27_64_0 \nvr28_64_1 vr28_64_0 \nvr29_64_1 vr29_64_0 \nvr30_64_1 vr30_64_0 \nvr31_64_1 vr31_64_0 \n];\n\ndefine register offset=0x4200 size=4 [ # 32 bit access to vrN registers (psydo-registers) (accessed by vrD_32_N vrA_32_N vrB_32_N vrS_32_N vrC_32_N)\nvr0_32_3 vr0_32_2 vr0_32_1 vr0_32_0 \nvr1_32_3 vr1_32_2 vr1_32_1 vr1_32_0 \nvr2_32_3 vr2_32_2 vr2_32_1 vr2_32_0 \nvr3_32_3 vr3_32_2 vr3_32_1 vr3_32_0 \nvr4_32_3 vr4_32_2 vr4_32_1 vr4_32_0 \nvr5_32_3 vr5_32_2 vr5_32_1 vr5_32_0 \nvr6_32_3 vr6_32_2 vr6_32_1 vr6_32_0 \nvr7_32_3 vr7_32_2 vr7_32_1 vr7_32_0 \nvr8_32_3 vr8_32_2 vr8_32_1 vr8_32_0 \nvr9_32_3 vr9_32_2 vr9_32_1 vr9_32_0 \nvr10_32_3 vr10_32_2 vr10_32_1 vr10_32_0 \nvr11_32_3 vr11_32_2 vr11_32_1 vr11_32_0 \nvr12_32_3 vr12_32_2 vr12_32_1 vr12_32_0 \nvr13_32_3 vr13_32_2 vr13_32_1 vr13_32_0 \nvr14_32_3 vr14_32_2 vr14_32_1 vr14_32_0 \nvr15_32_3 vr15_32_2 vr15_32_1 vr15_32_0 \nvr16_32_3 vr16_32_2 vr16_32_1 vr16_32_0 \nvr17_32_3 vr17_32_2 vr17_32_1 vr17_32_0 \nvr18_32_3 vr18_32_2 vr18_32_1 vr18_32_0 \nvr19_32_3 vr19_32_2 vr19_32_1 vr19_32_0 \nvr20_32_3 vr20_32_2 vr20_32_1 vr20_32_0 \nvr21_32_3 vr21_32_2 vr21_32_1 vr21_32_0 \nvr22_32_3 vr22_32_2 vr22_32_1 vr22_32_0 \nvr23_32_3 vr23_32_2 vr23_32_1 vr23_32_0 \nvr24_32_3 vr24_32_2 vr24_32_1 vr24_32_0 \nvr25_32_3 vr25_32_2 vr25_32_1 vr25_32_0 \nvr26_32_3 vr26_32_2 vr26_32_1 vr26_32_0 \nvr27_32_3 vr27_32_2 vr27_32_1 vr27_32_0 \nvr28_32_3 vr28_32_2 vr28_32_1 vr28_32_0 \nvr29_32_3 vr29_32_2 vr29_32_1 vr29_32_0 \nvr30_32_3 vr30_32_2 vr30_32_1 vr30_32_0 \nvr31_32_3 vr31_32_2 vr31_32_1 vr31_32_0 \n];\n\n# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 2 byte subregisters\ndefine register offset=0x4200 size=2 [ # 16 bit access to vrN registers (psydo-registers) (accessed by vrD_16_N vrA_16_N vrB_16_N vrS_16_N vrC_16_N)\nvr0_16_7 vr0_16_6 vr0_16_5 vr0_16_4 vr0_16_3 vr0_16_2 vr0_16_1 vr0_16_0 \nvr1_16_7 vr1_16_6 vr1_16_5 vr1_16_4 vr1_16_3 vr1_16_2 vr1_16_1 vr1_16_0\t\nvr2_16_7 vr2_16_6 vr2_16_5 vr2_16_4 vr2_16_3 vr2_16_2 vr2_16_1 vr2_16_0 \nvr3_16_7 vr3_16_6 vr3_16_5 vr3_16_4 vr3_16_3 vr3_16_2 vr3_16_1 vr3_16_0 \nvr4_16_7 vr4_16_6 vr4_16_5 vr4_16_4 vr4_16_3 vr4_16_2 vr4_16_1 vr4_16_0 \nvr5_16_7 vr5_16_6 vr5_16_5 vr5_16_4 vr5_16_3 vr5_16_2 vr5_16_1 vr5_16_0 \nvr6_16_7 vr6_16_6 vr6_16_5 vr6_16_4 vr6_16_3 vr6_16_2 vr6_16_1 vr6_16_0 \nvr7_16_7 vr7_16_6 vr7_16_5 vr7_16_4 vr7_16_3 vr7_16_2 vr7_16_1 vr7_16_0 \nvr8_16_7 vr8_16_6 vr8_16_5 vr8_16_4 vr8_16_3 vr8_16_2 vr8_16_1 vr8_16_0 \nvr9_16_7 vr9_16_6 vr9_16_5 vr9_16_4 vr9_16_3 vr9_16_2 vr9_16_1 vr9_16_0 \nvr10_16_7 vr10_16_6 vr10_16_5 vr10_16_4 vr10_16_3 vr10_16_2 vr10_16_1 vr10_16_0 \nvr11_16_7 vr11_16_6 vr11_16_5 vr11_16_4 vr11_16_3 vr11_16_2 vr11_16_1 vr11_16_0 \nvr12_16_7 vr12_16_6 vr12_16_5 vr12_16_4 vr12_16_3 vr12_16_2 vr12_16_1 vr12_16_0 \nvr13_16_7 vr13_16_6 vr13_16_5 vr13_16_4 vr13_16_3 vr13_16_2 vr13_16_1 vr13_16_0 \nvr14_16_7 vr14_16_6 vr14_16_5 vr14_16_4 vr14_16_3 vr14_16_2 vr14_16_1 vr14_16_0 \nvr15_16_7 vr15_16_6 vr15_16_5 vr15_16_4 vr15_16_3 vr15_16_2 vr15_16_1 vr15_16_0 \nvr16_16_7 vr16_16_6 vr16_16_5 vr16_16_4 vr16_16_3 vr16_16_2 vr16_16_1 vr16_16_0 \nvr17_16_7 vr17_16_6 vr17_16_5 vr17_16_4 vr17_16_3 vr17_16_2 vr17_16_1 vr17_16_0 \nvr18_16_7 vr18_16_6 vr18_16_5 vr18_16_4 vr18_16_3 vr18_16_2 vr18_16_1 vr18_16_0 \nvr19_16_7 vr19_16_6 vr19_16_5 vr19_16_4 vr19_16_3 vr19_16_2 vr19_16_1 vr19_16_0 \nvr20_16_7 vr20_16_6 vr20_16_5 vr20_16_4 vr20_16_3 vr20_16_2 vr20_16_1 vr20_16_0 \nvr21_16_7 vr21_16_6 vr21_16_5 vr21_16_4 vr21_16_3 vr21_16_2 vr21_16_1 vr21_16_0 \nvr22_16_7 vr22_16_6 vr22_16_5 vr22_16_4 vr22_16_3 vr22_16_2 vr22_16_1 vr22_16_0 \nvr23_16_7 vr23_16_6 vr23_16_5 vr23_16_4 vr23_16_3 vr23_16_2 vr23_16_1 vr23_16_0 \nvr24_16_7 vr24_16_6 vr24_16_5 vr24_16_4 vr24_16_3 vr24_16_2 vr24_16_1 vr24_16_0 \nvr25_16_7 vr25_16_6 vr25_16_5 vr25_16_4 vr25_16_3 vr25_16_2 vr25_16_1 vr25_16_0 \nvr26_16_7 vr26_16_6 vr26_16_5 vr26_16_4 vr26_16_3 vr26_16_2 vr26_16_1 vr26_16_0 \nvr27_16_7 vr27_16_6 vr27_16_5 vr27_16_4 vr27_16_3 vr27_16_2 vr27_16_1 vr27_16_0 \nvr28_16_7 vr28_16_6 vr28_16_5 vr28_16_4 vr28_16_3 vr28_16_2 vr28_16_1 vr28_16_0 \nvr29_16_7 vr29_16_6 vr29_16_5 vr29_16_4 vr29_16_3 vr29_16_2 vr29_16_1 vr29_16_0 \nvr30_16_7 vr30_16_6 vr30_16_5 vr30_16_4 vr30_16_3 vr30_16_2 vr30_16_1 vr30_16_0 \nvr31_16_7 vr31_16_6 vr31_16_5 vr31_16_4 vr31_16_3 vr31_16_2 vr31_16_1 vr31_16_0 \n];\n\n# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 1 byte subregisters\ndefine register offset=0x4200 size=1 [ # 8 bit access to vrN registers (psydo-registers) (accessed by vrD_8_N vrA_8_N vrB_8_N vrS_8_N vrC_8_N)\nvr0_8_15 vr0_8_14 vr0_8_13 vr0_8_12 vr0_8_11 vr0_8_10 vr0_8_9 vr0_8_8 vr0_8_7 vr0_8_6 vr0_8_5 vr0_8_4 vr0_8_3 vr0_8_2 vr0_8_1 vr0_8_0 \nvr1_8_15 vr1_8_14 vr1_8_13 vr1_8_12 vr1_8_11 vr1_8_10 vr1_8_9 vr1_8_8 vr1_8_7 vr1_8_6 vr1_8_5 vr1_8_4 vr1_8_3 vr1_8_2 vr1_8_1 vr1_8_0 \nvr2_8_15 vr2_8_14 vr2_8_13 vr2_8_12 vr2_8_11 vr2_8_10 vr2_8_9 vr2_8_8 vr2_8_7 vr2_8_6 vr2_8_5 vr2_8_4 vr2_8_3 vr2_8_2 vr2_8_1 vr2_8_0 \nvr3_8_15 vr3_8_14 vr3_8_13 vr3_8_12 vr3_8_11 vr3_8_10 vr3_8_9 vr3_8_8 vr3_8_7 vr3_8_6 vr3_8_5 vr3_8_4 vr3_8_3 vr3_8_2 vr3_8_1 vr3_8_0 \nvr4_8_15 vr4_8_14 vr4_8_13 vr4_8_12 vr4_8_11 vr4_8_10 vr4_8_9 vr4_8_8 vr4_8_7 vr4_8_6 vr4_8_5 vr4_8_4 vr4_8_3 vr4_8_2 vr4_8_1 vr4_8_0 \nvr5_8_15 vr5_8_14 vr5_8_13 vr5_8_12 vr5_8_11 vr5_8_10 vr5_8_9 vr5_8_8 vr5_8_7 vr5_8_6 vr5_8_5 vr5_8_4 vr5_8_3 vr5_8_2 vr5_8_1 vr5_8_0 \nvr6_8_15 vr6_8_14 vr6_8_13 vr6_8_12 vr6_8_11 vr6_8_10 vr6_8_9 vr6_8_8 vr6_8_7 vr6_8_6 vr6_8_5 vr6_8_4 vr6_8_3 vr6_8_2 vr6_8_1 vr6_8_0 \nvr7_8_15 vr7_8_14 vr7_8_13 vr7_8_12 vr7_8_11 vr7_8_10 vr7_8_9 vr7_8_8 vr7_8_7 vr7_8_6 vr7_8_5 vr7_8_4 vr7_8_3 vr7_8_2 vr7_8_1 vr7_8_0 \nvr8_8_15 vr8_8_14 vr8_8_13 vr8_8_12 vr8_8_11 vr8_8_10 vr8_8_9 vr8_8_8 vr8_8_7 vr8_8_6 vr8_8_5 vr8_8_4 vr8_8_3 vr8_8_2 vr8_8_1 vr8_8_0 \nvr9_8_15 vr9_8_14 vr9_8_13 vr9_8_12 vr9_8_11 vr9_8_10 vr9_8_9 vr9_8_8 vr9_8_7 vr9_8_6 vr9_8_5 vr9_8_4 vr9_8_3 vr9_8_2 vr9_8_1 vr9_8_0 \nvr10_8_15 vr10_8_14 vr10_8_13 vr10_8_12 vr10_8_11 vr10_8_10 vr10_8_9 vr10_8_8 vr10_8_7 vr10_8_6 vr10_8_5 vr10_8_4 vr10_8_3 vr10_8_2 vr10_8_1 vr10_8_0 \nvr11_8_15 vr11_8_14 vr11_8_13 vr11_8_12 vr11_8_11 vr11_8_10 vr11_8_9 vr11_8_8 vr11_8_7 vr11_8_6 vr11_8_5 vr11_8_4 vr11_8_3 vr11_8_2 vr11_8_1 vr11_8_0 \nvr12_8_15 vr12_8_14 vr12_8_13 vr12_8_12 vr12_8_11 vr12_8_10 vr12_8_9 vr12_8_8 vr12_8_7 vr12_8_6 vr12_8_5 vr12_8_4 vr12_8_3 vr12_8_2 vr12_8_1 vr12_8_0 \nvr13_8_15 vr13_8_14 vr13_8_13 vr13_8_12 vr13_8_11 vr13_8_10 vr13_8_9 vr13_8_8 vr13_8_7 vr13_8_6 vr13_8_5 vr13_8_4 vr13_8_3 vr13_8_2 vr13_8_1 vr13_8_0 \nvr14_8_15 vr14_8_14 vr14_8_13 vr14_8_12 vr14_8_11 vr14_8_10 vr14_8_9 vr14_8_8 vr14_8_7 vr14_8_6 vr14_8_5 vr14_8_4 vr14_8_3 vr14_8_2 vr14_8_1 vr14_8_0 \nvr15_8_15 vr15_8_14 vr15_8_13 vr15_8_12 vr15_8_11 vr15_8_10 vr15_8_9 vr15_8_8 vr15_8_7 vr15_8_6 vr15_8_5 vr15_8_4 vr15_8_3 vr15_8_2 vr15_8_1 vr15_8_0 \nvr16_8_15 vr16_8_14 vr16_8_13 vr16_8_12 vr16_8_11 vr16_8_10 vr16_8_9 vr16_8_8 vr16_8_7 vr16_8_6 vr16_8_5 vr16_8_4 vr16_8_3 vr16_8_2 vr16_8_1 vr16_8_0 \nvr17_8_15 vr17_8_14 vr17_8_13 vr17_8_12 vr17_8_11 vr17_8_10 vr17_8_9 vr17_8_8 vr17_8_7 vr17_8_6 vr17_8_5 vr17_8_4 vr17_8_3 vr17_8_2 vr17_8_1 vr17_8_0 \nvr18_8_15 vr18_8_14 vr18_8_13 vr18_8_12 vr18_8_11 vr18_8_10 vr18_8_9 vr18_8_8 vr18_8_7 vr18_8_6 vr18_8_5 vr18_8_4 vr18_8_3 vr18_8_2 vr18_8_1 vr18_8_0 \nvr19_8_15 vr19_8_14 vr19_8_13 vr19_8_12 vr19_8_11 vr19_8_10 vr19_8_9 vr19_8_8 vr19_8_7 vr19_8_6 vr19_8_5 vr19_8_4 vr19_8_3 vr19_8_2 vr19_8_1 vr19_8_0 \nvr20_8_15 vr20_8_14 vr20_8_13 vr20_8_12 vr20_8_11 vr20_8_10 vr20_8_9 vr20_8_8 vr20_8_7 vr20_8_6 vr20_8_5 vr20_8_4 vr20_8_3 vr20_8_2 vr20_8_1 vr20_8_0 \nvr21_8_15 vr21_8_14 vr21_8_13 vr21_8_12 vr21_8_11 vr21_8_10 vr21_8_9 vr21_8_8 vr21_8_7 vr21_8_6 vr21_8_5 vr21_8_4 vr21_8_3 vr21_8_2 vr21_8_1 vr21_8_0 \nvr22_8_15 vr22_8_14 vr22_8_13 vr22_8_12 vr22_8_11 vr22_8_10 vr22_8_9 vr22_8_8 vr22_8_7 vr22_8_6 vr22_8_5 vr22_8_4 vr22_8_3 vr22_8_2 vr22_8_1 vr22_8_0 \nvr23_8_15 vr23_8_14 vr23_8_13 vr23_8_12 vr23_8_11 vr23_8_10 vr23_8_9 vr23_8_8 vr23_8_7 vr23_8_6 vr23_8_5 vr23_8_4 vr23_8_3 vr23_8_2 vr23_8_1 vr23_8_0 \nvr24_8_15 vr24_8_14 vr24_8_13 vr24_8_12 vr24_8_11 vr24_8_10 vr24_8_9 vr24_8_8 vr24_8_7 vr24_8_6 vr24_8_5 vr24_8_4 vr24_8_3 vr24_8_2 vr24_8_1 vr24_8_0 \nvr25_8_15 vr25_8_14 vr25_8_13 vr25_8_12 vr25_8_11 vr25_8_10 vr25_8_9 vr25_8_8 vr25_8_7 vr25_8_6 vr25_8_5 vr25_8_4 vr25_8_3 vr25_8_2 vr25_8_1 vr25_8_0 \nvr26_8_15 vr26_8_14 vr26_8_13 vr26_8_12 vr26_8_11 vr26_8_10 vr26_8_9 vr26_8_8 vr26_8_7 vr26_8_6 vr26_8_5 vr26_8_4 vr26_8_3 vr26_8_2 vr26_8_1 vr26_8_0 \nvr27_8_15 vr27_8_14 vr27_8_13 vr27_8_12 vr27_8_11 vr27_8_10 vr27_8_9 vr27_8_8 vr27_8_7 vr27_8_6 vr27_8_5 vr27_8_4 vr27_8_3 vr27_8_2 vr27_8_1 vr27_8_0 \nvr28_8_15 vr28_8_14 vr28_8_13 vr28_8_12 vr28_8_11 vr28_8_10 vr28_8_9 vr28_8_8 vr28_8_7 vr28_8_6 vr28_8_5 vr28_8_4 vr28_8_3 vr28_8_2 vr28_8_1 vr28_8_0 \nvr29_8_15 vr29_8_14 vr29_8_13 vr29_8_12 vr29_8_11 vr29_8_10 vr29_8_9 vr29_8_8 vr29_8_7 vr29_8_6 vr29_8_5 vr29_8_4 vr29_8_3 vr29_8_2 vr29_8_1 vr29_8_0 \nvr30_8_15 vr30_8_14 vr30_8_13 vr30_8_12 vr30_8_11 vr30_8_10 vr30_8_9 vr30_8_8 vr30_8_7 vr30_8_6 vr30_8_5 vr30_8_4 vr30_8_3 vr30_8_2 vr30_8_1 vr30_8_0 \nvr31_8_15 vr31_8_14 vr31_8_13 vr31_8_12 vr31_8_11 vr31_8_10 vr31_8_9 vr31_8_8 vr31_8_7 vr31_8_6 vr31_8_5 vr31_8_4 vr31_8_3 vr31_8_2 vr31_8_1 vr31_8_0 \n];\n\n@endif\n# Define context bits\ndefine register offset=0x6000 size=4 contextreg;\ndefine context contextreg\n linkreg=(0,1) # 0 - no LR set, 1 - LR set (used to flag branch instructions to be treated as calls)\n vle=(2,2) \t\t # Used to control inclusion/disassembly of vle instructions. '1' means use vle see NOTVLE/ISVLE @define below \n # FIXME! while allowing vle context to flow is incorrect, the PowerPC disassembly action will not work at all without it\n # and could easily flow the incorrect context when traversing between VLE and non-VLE sections.\n \n # transient context\n lsmul=(3,7) noflow\t # Used for Load/store multiple parsing\n regp=(8,12) noflow\t # Used in powerISA quad word instructions\n regpset=(8,12) noflow\t # Used in powerISA quad word instructions\n;\n\n@define NOTVLE \"vle=0\"\n@define ISVLE \"vle=1\"\n\n# Define Device Control Registers (specific to IBM PowerPC Embedded Controller, see instructions mfdcr/mtdcr)\n# Device Control Registers are defined with generic names\n# These names may be replaced within register_data section within a PPC variant's pspec file\ndefine register offset=0x7000 size=$(REGISTER_SIZE) \n\t[ dcr000 dcr001 dcr002 dcr003 dcr004 dcr005 dcr006 dcr007 dcr008 dcr009 dcr00a dcr00b dcr00c dcr00d dcr00e dcr00f \n\t dcr010 dcr011 dcr012 dcr013 dcr014 dcr015 dcr016 dcr017 dcr018 dcr019 dcr01a dcr01b dcr01c dcr01d dcr01e dcr01f \n\t dcr020 dcr021 dcr022 dcr023 dcr024 dcr025 dcr026 dcr027 dcr028 dcr029 dcr02a dcr02b dcr02c dcr02d dcr02e dcr02f\n\t dcr030 dcr031 dcr032 dcr033 dcr034 dcr035 dcr036 dcr037 dcr038 dcr039 dcr03a dcr03b dcr03c dcr03d dcr03e dcr03f\n\t dcr040 dcr041 dcr042 dcr043 dcr044 dcr045 dcr046 dcr047 dcr048 dcr049 dcr04a dcr04b dcr04c dcr04d dcr04e dcr04f\n\t dcr050 dcr051 dcr052 dcr053 dcr054 dcr055 dcr056 dcr057 dcr058 dcr059 dcr05a dcr05b dcr05c dcr05d dcr05e dcr05f\n\t dcr060 dcr061 dcr062 dcr063 dcr064 dcr065 dcr066 dcr067 dcr068 dcr069 dcr06a dcr06b dcr06c dcr06d dcr06e dcr06f\n\t dcr070 dcr071 dcr072 dcr073 dcr074 dcr075 dcr076 dcr077 dcr078 dcr079 dcr07a dcr07b dcr07c dcr07d dcr07e dcr07f\n\t dcr080 dcr081 dcr082 dcr083 dcr084 dcr085 dcr086 dcr087 dcr088 dcr089 dcr08a dcr08b dcr08c dcr08d dcr08e dcr08f\n\t dcr090 dcr091 dcr092 dcr093 dcr094 dcr095 dcr096 dcr097 dcr098 dcr099 dcr09a dcr09b dcr09c dcr09d dcr09e dcr09f\n\t dcr0a0 dcr0a1 dcr0a2 dcr0a3 dcr0a4 dcr0a5 dcr0a6 dcr0a7 dcr0a8 dcr0a9 dcr0aa dcr0ab dcr0ac dcr0ad dcr0ae dcr0af\n\t dcr0b0 dcr0b1 dcr0b2 dcr0b3 dcr0b4 dcr0b5 dcr0b6 dcr0b7 dcr0b8 dcr0b9 dcr0ba dcr0bb dcr0bc dcr0bd dcr0be dcr0bf\n\t dcr0c0 dcr0c1 dcr0c2 dcr0c3 dcr0c4 dcr0c5 dcr0c6 dcr0c7 dcr0c8 dcr0c9 dcr0ca dcr0cb dcr0cc dcr0cd dcr0ce dcr0cf\n\t dcr0d0 dcr0d1 dcr0d2 dcr0d3 dcr0d4 dcr0d5 dcr0d6 dcr0d7 dcr0d8 dcr0d9 dcr0da dcr0db dcr0dc dcr0dd dcr0de dcr0df\n\t dcr0e0 dcr0e1 dcr0e2 dcr0e3 dcr0e4 dcr0e5 dcr0e6 dcr0e7 dcr0e8 dcr0e9 dcr0ea dcr0eb dcr0ec dcr0ed dcr0ee dcr0ef\n\t dcr0f0 dcr0f1 dcr0f2 dcr0f3 dcr0f4 dcr0f5 dcr0f6 dcr0f7 dcr0f8 dcr0f9 dcr0fa dcr0fb dcr0fc dcr0fd dcr0fe dcr0ff\n\t dcr100 dcr101 dcr102 dcr103 dcr104 dcr105 dcr106 dcr107 dcr108 dcr109 dcr10a dcr10b dcr10c dcr10d dcr10e dcr10f\n\t dcr110 dcr111 dcr112 dcr113 dcr114 dcr115 dcr116 dcr117 dcr118 dcr119 dcr11a dcr11b dcr11c dcr11d\tdcr11e dcr11f \n\t dcr120 dcr121 dcr122 dcr123 dcr124 dcr125 dcr126 dcr127 dcr128 dcr129 dcr12a dcr12b dcr12c dcr12d dcr12e dcr12f\n\t dcr130 dcr131 dcr132 dcr133 dcr134 dcr135 dcr136 dcr137 dcr138 dcr139 dcr13a dcr13b dcr13c dcr13d dcr13e dcr13f\n\t dcr140 dcr141 dcr142 dcr143 dcr144 dcr145 dcr146 dcr147 dcr148 dcr149 dcr14a dcr14b dcr14c dcr14d dcr14e dcr14f\n\t dcr150 dcr151 dcr152 dcr153 dcr154 dcr155 dcr156 dcr157 dcr158 dcr159 dcr15a dcr15b dcr15c dcr15d dcr15e dcr15f\n\t dcr160 dcr161 dcr162 dcr163 dcr164 dcr165 dcr166 dcr167 dcr168 dcr169 dcr16a dcr16b dcr16c dcr16d dcr16e dcr16f\n\t dcr170 dcr171 dcr172 dcr173 dcr174 dcr175 dcr176 dcr177 dcr178 dcr179 dcr17a dcr17b dcr17c dcr17d dcr17e dcr17f\n\t dcr180 dcr181 dcr182 dcr183 dcr184 dcr185 dcr186 dcr187 dcr188 dcr189 dcr18a dcr18b dcr18c dcr18d dcr18e dcr18f\n\t dcr190 dcr191 dcr192 dcr193 dcr194 dcr195 dcr196 dcr197 dcr198 dcr199 dcr19a dcr19b dcr19c dcr19d dcr19e dcr19f\n\t dcr1a0 dcr1a1 dcr1a2 dcr1a3 dcr1a4 dcr1a5 dcr1a6 dcr1a7 dcr1a8 dcr1a9 dcr1aa dcr1ab dcr1ac dcr1ad dcr1ae dcr1af\n\t dcr1b0 dcr1b1 dcr1b2 dcr1b3 dcr1b4 dcr1b5 dcr1b6 dcr1b7 dcr1b8 dcr1b9 dcr1ba dcr1bb dcr1bc dcr1bd dcr1be dcr1bf\n\t dcr1c0 dcr1c1 dcr1c2 dcr1c3 dcr1c4 dcr1c5 dcr1c6 dcr1c7 dcr1c8 dcr1c9 dcr1ca dcr1cb dcr1cc dcr1cd dcr1ce dcr1cf\n\t dcr1d0 dcr1d1 dcr1d2 dcr1d3 dcr1d4 dcr1d5 dcr1d6 dcr1d7 dcr1d8 dcr1d9 dcr1da dcr1db dcr1dc dcr1dd dcr1de dcr1df\n\t dcr1e0 dcr1e1 dcr1e2 dcr1e3 dcr1e4 dcr1e5 dcr1e6 dcr1e7 dcr1e8 dcr1e9 dcr1ea dcr1eb dcr1ec dcr1ed dcr1ee dcr1ef\n\t dcr1f0 dcr1f1 dcr1f2 dcr1f3 dcr1f4 dcr1f5 dcr1f6 dcr1f7 dcr1f8 dcr1f9 dcr1fa dcr1fb dcr1fc dcr1fd dcr1fe dcr1ff\n\t dcr200 dcr201 dcr202 dcr203 dcr204 dcr205 dcr206 dcr207 dcr208 dcr209 dcr20a dcr20b dcr20c dcr20d dcr20e dcr20f\n\t dcr210 dcr211 dcr212 dcr213 dcr214 dcr215 dcr216 dcr217 dcr218 dcr219 dcr21a dcr21b dcr21c dcr21d dcr21e dcr21f\n\t dcr220 dcr221 dcr222 dcr223 dcr224 dcr225 dcr226 dcr227 dcr228 dcr229 dcr22a dcr22b dcr22c dcr22d dcr22e dcr22f\n\t dcr230 dcr231 dcr232 dcr233 dcr234 dcr235 dcr236 dcr237 dcr238 dcr239 dcr23a dcr23b dcr23c dcr23d dcr23e dcr23f\n\t dcr240 dcr241 dcr242 dcr243 dcr244 dcr245 dcr246 dcr247 dcr248 dcr249 dcr24a dcr24b dcr24c dcr24d dcr24e dcr24f\n\t dcr250 dcr251 dcr252 dcr253 dcr254 dcr255 dcr256 dcr257 dcr258 dcr259 dcr25a dcr25b dcr25c dcr25d dcr25e dcr25f\n\t dcr260 dcr261 dcr262 dcr263 dcr264 dcr265 dcr266 dcr267 dcr268 dcr269 dcr26a dcr26b dcr26c dcr26d dcr26e dcr26f\n\t dcr270 dcr271 dcr272 dcr273 dcr274 dcr275 dcr276 dcr277 dcr278 dcr279 dcr27a dcr27b dcr27c dcr27d dcr27e dcr27f\n\t dcr280 dcr281 dcr282 dcr283 dcr284 dcr285 dcr286 dcr287 dcr288 dcr289 dcr28a dcr28b dcr28c dcr28d dcr28e dcr28f\n\t dcr290 dcr291 dcr292 dcr293 dcr294 dcr295 dcr296 dcr297 dcr298 dcr299 dcr29a dcr29b dcr29c dcr29d dcr29e dcr29f\n\t dcr2a0 dcr2a1 dcr2a2 dcr2a3 dcr2a4 dcr2a5 dcr2a6 dcr2a7 dcr2a8 dcr2a9 dcr2aa dcr2ab dcr2ac dcr2ad dcr2ae dcr2af\n\t dcr2b0 dcr2b1 dcr2b2 dcr2b3 dcr2b4 dcr2b5 dcr2b6 dcr2b7 dcr2b8 dcr2b9 dcr2ba dcr2bb dcr2bc dcr2bd dcr2be dcr2bf\n\t dcr2c0 dcr2c1 dcr2c2 dcr2c3 dcr2c4 dcr2c5 dcr2c6 dcr2c7 dcr2c8 dcr2c9 dcr2ca dcr2cb dcr2cc dcr2cd dcr2ce dcr2cf\n\t dcr2d0 dcr2d1 dcr2d2 dcr2d3 dcr2d4 dcr2d5 dcr2d6 dcr2d7 dcr2d8 dcr2d9 dcr2da dcr2db dcr2dc dcr2dd dcr2de dcr2df\n\t dcr2e0 dcr2e1 dcr2e2 dcr2e3 dcr2e4 dcr2e5 dcr2e6 dcr2e7 dcr2e8 dcr2e9 dcr2ea dcr2eb dcr2ec dcr2ed dcr2ee dcr2ef\n\t dcr2f0 dcr2f1 dcr2f2 dcr2f3 dcr2f4 dcr2f5 dcr2f6 dcr2f7 dcr2f8 dcr2f9 dcr2fa dcr2fb dcr2fc dcr2fd dcr2fe dcr2ff\n\t dcr300 dcr301 dcr302 dcr303 dcr304 dcr305 dcr306 dcr307 dcr308 dcr309 dcr30a dcr30b dcr30c dcr30d dcr30e dcr30f\n\t dcr310 dcr311 dcr312 dcr313 dcr314 dcr315 dcr316 dcr317 dcr318 dcr319 dcr31a dcr31b dcr31c dcr31d dcr31e dcr31f\n\t dcr320 dcr321 dcr322 dcr323 dcr324 dcr325 dcr326 dcr327 dcr328 dcr329 dcr32a dcr32b dcr32c dcr32d dcr32e dcr32f\n\t dcr330 dcr331 dcr332 dcr333 dcr334 dcr335 dcr336 dcr337 dcr338 dcr339 dcr33a dcr33b dcr33c dcr33d dcr33e dcr33f\n\t dcr340 dcr341 dcr342 dcr343 dcr344 dcr345 dcr346 dcr347 dcr348 dcr349 dcr34a dcr34b dcr34c dcr34d dcr34e dcr34f\n\t dcr350 dcr351 dcr352 dcr353 dcr354 dcr355 dcr356 dcr357 dcr358 dcr359 dcr35a dcr35b dcr35c dcr35d dcr35e dcr35f\n\t dcr360 dcr361 dcr362 dcr363 dcr364 dcr365 dcr366 dcr367 dcr368 dcr369 dcr36a dcr36b dcr36c dcr36d dcr36e dcr36f\n\t dcr370 dcr371 dcr372 dcr373 dcr374 dcr375 dcr376 dcr377 dcr378 dcr379 dcr37a dcr37b dcr37c dcr37d dcr37e dcr37f\n\t dcr380 dcr381 dcr382 dcr383 dcr384 dcr385 dcr386 dcr387 dcr388 dcr389 dcr38a dcr38b dcr38c dcr38d dcr38e dcr38f\n\t dcr390 dcr391 dcr392 dcr393 dcr394 dcr395 dcr396 dcr397 dcr398 dcr399 dcr39a dcr39b dcr39c dcr39d dcr39e dcr39f\n\t dcr3a0 dcr3a1 dcr3a2 dcr3a3 dcr3a4 dcr3a5 dcr3a6 dcr3a7 dcr3a8 dcr3a9 dcr3aa dcr3ab dcr3ac dcr3ad dcr3ae dcr3af\n\t dcr3b0 dcr3b1 dcr3b2 dcr3b3 dcr3b4 dcr3b5 dcr3b6 dcr3b7 dcr3b8 dcr3b9 dcr3ba dcr3bb dcr3bc dcr3bd dcr3be dcr3bf\n\t dcr3c0 dcr3c1 dcr3c2 dcr3c3 dcr3c4 dcr3c5 dcr3c6 dcr3c7 dcr3c8 dcr3c9 dcr3ca dcr3cb dcr3cc dcr3cd dcr3ce dcr3cf\n\t dcr3d0 dcr3d1 dcr3d2 dcr3d3 dcr3d4 dcr3d5 dcr3d6 dcr3d7 dcr3d8 dcr3d9 dcr3da dcr3db dcr3dc dcr3dd dcr3de dcr3df\n\t dcr3e0 dcr3e1 dcr3e2 dcr3e3 dcr3e4 dcr3e5 dcr3e6 dcr3e7 dcr3e8 dcr3e9 dcr3ea dcr3eb dcr3ec dcr3ed dcr3ee dcr3ef\n\t dcr3f0 dcr3f1 dcr3f2 dcr3f3 dcr3f4 dcr3f5 dcr3f6 dcr3f7 dcr3f8 dcr3f9 dcr3fa dcr3fb dcr3fc dcr3fd dcr3fe dcr3ff\n\t];\n\n# ACC and SPEFSCR are part of the \"EREF: A Reference for Motorola Book E and e500 Core\" spec \n# SPEFSCR is a reperposed spr200\ndefine register offset=0x10000 size=8 [ACC];\n\n# OP=17 & BITS_21_25=0 & BITS_16_20=0(ok) & BITS_5_11=LEV & BITS_2_4=0 & BIT_1=1 & BIT_0=0\n\ndefine token instr(32)\n\tA=(16,20)\n\tAA=(1,1)\n\tA_BITS=(16,20)\n\tA_BITSS=(16,20) signed\n\tAX=(2,2)\n\tB=(11,15)\n\tB_BITS=(11,15)\n\tBD=(2,15) signed\n\tBF=(17,24)\n\tBFA=(0,2)\n\tBFA2=(18,20)\n\tBF2=(23,25)\n\tBH=(11,12)\n\tBH_BITS=(11,12)\n\tBH_RBE=(11,20)\n\tBH_RET=(11,11)\n\tBI_BITS=(16,20)\t\n\tBI_CC=(16,17)\n\tBI_CR=(18,20)\n\tBIT_A=(25,25)\n\tBIT_L=(21,21)\n\tBIT_R=(21,21)\n\tBIT_0=(0,0)\n\tBIT_10=(10,10)\n\tBIT_1=(1,1)\n\tBIT_11=(11,11)\n\tBIT_15=(15,15)\n\tBIT_16=(16,16)\n\tBIT_17=(17,17)\n\tBIT_18=(18,18)\n\tBIT_20=(20,20)\n\tBIT_22=(22,22)\n\tBIT_25=(25,25)\n\tBIT_9=(9,9)\n\tBIT_6=(6,6)\n\tBITS_0_1=(0,1)\n\tBITS_0_17=(0,17)\n\tBITS_0_2=(0,2)\n\tBITS_0_3=(0,3)\n\tBITS_1_10=(1,10)\n\tBITS_11_13=(11,13)\n\tBITS_11_15=(11,15)\n\tBITS_11_17=(11,17)\n\tBITS_11_20=(11,20)\n\tBITS_11_22=(11,22)\n\tBITS_11_24=(11,24)\n\tBITS_11_25=(11,25)\n\tBITS_12_15=(12,15)\n\tBITS_12_19=(12,19) \n\tBITS_12_25=(12,25)\n\tBITS_13_15=(13,15)\n\tBITS_14_15=(14,15)\n\tBITS_16_17=(12,15)\n\tBITS_16_18=(16,18)\n\tBITS_16_19=(16,19)\n\tBITS_16_20=(16,20)\n\tBITS_16_22=(16,22)\n\tBITS_16_25=(16,25)\n\tBITS_17_20=(17,20)\n\tBITS_17_24=(17,24)\n\tBITS_18_19=(18,19)\n\tBITS_18_20=(18,20)\n\tBITS_1_9=(1,9)\n\tBITS_19_20=(19,20)\n\tBITS_20_20=(20,20)\n\tBITS_21_22=(21,22)\n\tBITS_21_23=(21,23)\n\tBITS_21_24=(7,10)\n\tBITS_21_25=(21,25)\n\tBITS_21_28=(21,28)\n\tBITS_22_24=(22,24)\n\tBITS_22_25=(22,25)\n\tBITS_22_26=(22,26)\n\tBITS_2_25=(2,25)\n\tBITS_23_24=(23,24)\n\tBITS_23_25=(23,25)\n\tBITS_2_4=(2,4)\n\tBITS_24_25=(24,25)\n\tBITS_3_7=(3,7)\n\tBITS_4_5=(4,5)\n\tBITS_6_10=(6,10)\n\tBO_0=(25,25)\n\tBO_1=(24,24)\n\tBO=(21,25)\n\tBO_2=(23,23)\n\tBO_3=(22, 22)\n\tBO_BITS=(21,25)\n\tBX=(1,1)\n\tC=(6,10)\n\tCOND_BRANCH_CTRL=(22,25)\n\tCR_A=(18,20)\n\tCR_A_CC=(16,17)\n\tCR_B=(13,15)\n\tCR_B_CC=(11,12)\n\tCRBD=(21,25)\n\tCRBR=(6,10)\n\tCR_D=(23,25)\n\tCR_D_CC=(21,22)\n\tcrfD=(23,25)\n\tCRFD=(23,25)\n\tCRFS=(18,20)\n\tCRM0=(19,19)\n\tCRM1=(18,18)\n\tCRM=(12,19)\n\tCRM2=(17,17)\n\tCRM3=(16,16)\n\tCRM4=(15,15)\n\tCRM5=(14,14)\n\tCRM6=(13,13)\n\tCRM7=(12,12)\n\tCR_X=(8,10)\n\tCR_X_CC=(6,7)\n\tCT=(21,25) \n\tCT2=(21,24) \n\tCX=(3,3)\n\tD0=(6,15) signed\n\tD1=(16,20)\n\tD2=(0,0)\n\tD=(21,25)\n\tDp=(21,25)\n\tDC6=(6,6)\n\tDCM=(10,15)\n\tDCMX=(16,22)\n\tDCRN=(11,20)\n\tDGM=(10,15)\n\tDM=(8,9)\n\tDM2=(2,2)\n\tDQ=(4,15)\n\tDQs=(4,15) signed\n\tDS=(2,15)\n\tDSs=(2,15) signed\n\tDX=(16,20)\n\tDUI=(21,25)\n\tDUIS=(11,20)\n\tEX=(0,0)\n\tfA=(16,20)\n\tfB=(11,15)\n\tfC=(6,10)\n\tfD=(21,25)\n\tFM0=(24,24)\n\tFM1=(23,23)\n\tFM=(17,24)\n\tFM2=(22,22)\n\tFM3=(21,21)\n\tFM4=(20,20)\n\tFM5=(19,19)\n\tFM6=(18,18)\n\tFM7=(17,17)\n\tFNC=(11,15)\n\tfS=(21,25)\n\tfT=(21,25)\n\tIMM=(11,15)\n\n\tEVUIMM=(11,15)\n\tBU_UIMM=(16,20)\n\tBU_SIMM=(16,20)\n\tEVUIMM_8=(11,15)\n\tEVUIMM_4=(11,15)\n\tEVUIMM_2=(11,15)\n\n\tL= (21,22)\n\tL2=(21,21)\n\tL16=(16,17)\n\tLEV=(5,11)\n\tLI=(2,25) signed\n\tLK=(0,0)\n\tMBH=(5,5) \n\tMBL=(6,10)\n\tME=(1,5)\n\tMO=(21,25)\n\tMSR_L=(16,16)\n\tNB= (11,15)\n\tO=(9,9)\n\tOE=(10,10) \n\tOP=(26,31)\n\tPS=(9,9)\n\tRc=(0,0)\n\tRc2=(10,10)\n\tRMC=(9,10)\n\t\n RA=(16,20)\n\tRB=(11,15)\n\tRS=(21,25)\n\tRT=(21,25)\n\tR0=(0,0)\n\tR16=(16,16)\n\t\n\tS=(21,25)\n\tSBE=(11,11)\n\tSH16=(10,15)\n\tSHB=(6,9)\n\tSHH=(1,1)\n\tSHL=(11,15)\n\tSHW=(8,9)\n\tS8IMM=(0,7) signed\n\tS5IMM=(11,15) signed\n\tSIMM=(0,15) signed\n\tSIMM_DS=(2,15) signed\n\tSIMM_SIGN=(15,15)\n\tSIX=(11,14)\n\tSP=(19,20)\n\tSPRVAL=(11,20)\n\tSR=(16,19)\n\tST=(15,15)\n\tSTRM=(21,22)\n\tSX=(0,0)\n\tSX3=(3,3)\n\tT=(21,25)\n\tTOA=(21,25)\n\tTBR=(11,20)\n\tTH=(21,25)\n\tTMP_6_10=(21,25)\n\tTO=(21,25)\n\tTX=(0,0)\n\tTX3=(3,3)\n\tUI=(11,15)\n\tUI_11_s8=(16,20)\n\tUI_16_s8=(11,15)\n\tUI_16_s16=(0,15)\n\tUIMM8=(11,18)\n\tUIMM=(0,15)\n\tUIM=(16,17)\n\tUIMB=(16,19)\n\tUIMH=(16,18)\n\tUIMW=(16,17)\n\tUIMT=(16,21)\n\n\tvrAR=(16,20) # AltVect Vector register vrN selector (128 bit)\n\tvrAD=(16,20)\n\n\tvrA_64_0=(16,20) # AltVect Vector register vrN selector (64 bit)\n\tvrA_64_1=(16,20)\n\n\tvrA_32_0=(16,20) # AltVect Vector register vrN selector (32 bit)\n\tvrA_32_1=(16,20)\n\tvrA_32_2=(16,20)\n\tvrA_32_3=(16,20)\n\n vrA_16_0=(16,20) # AltVect Vector register vrN selector (16 bit)\n vrA_16_1=(16,20)\n vrA_16_2=(16,20)\n vrA_16_3=(16,20)\n vrA_16_4=(16,20)\n vrA_16_5=(16,20)\n vrA_16_6=(16,20)\n vrA_16_7=(16,20)\n\n vrA_8_0=(16,20) # AltVect Vector register vrN selector (8 bit)\n vrA_8_1=(16,20)\n vrA_8_2=(16,20)\n vrA_8_3=(16,20)\n vrA_8_4=(16,20)\n vrA_8_5=(16,20)\n vrA_8_6=(16,20)\n vrA_8_7=(16,20)\n vrA_8_8=(16,20)\n vrA_8_9=(16,20)\n vrA_8_10=(16,20)\n vrA_8_11=(16,20)\n vrA_8_12=(16,20)\n vrA_8_13=(16,20)\n vrA_8_14=(16,20)\n vrA_8_15=(16,20)\n\n\tvrBR=(11,15) # AltVect Vector register vrN selector (128 bit)\n\tvrBD=(11,15)\n\n\tvrB_64_0=(11,15) # AltVect Vector register vrN selector (64 bit)\n\tvrB_64_1=(11,15)\n\n\tvrB_32_0=(11,15) # AltVect Vector register vrN selector (32 bit)\n\tvrB_32_1=(11,15)\n\tvrB_32_2=(11,15)\n\tvrB_32_3=(11,15)\n\n vrB_16_0=(11,15) # AltVect Vector register vrN selector (16 bit)\n vrB_16_1=(11,15)\n vrB_16_2=(11,15)\n vrB_16_3=(11,15)\n vrB_16_4=(11,15)\n vrB_16_5=(11,15)\n vrB_16_6=(11,15)\n vrB_16_7=(11,15)\n\n vrB_8_0=(11,15) # AltVect Vector register vrN selector (8 bit)\n vrB_8_1=(11,15)\n vrB_8_2=(11,15)\n vrB_8_3=(11,15)\n vrB_8_4=(11,15)\n vrB_8_5=(11,15)\n vrB_8_6=(11,15)\n vrB_8_7=(11,15)\n vrB_8_8=(11,15)\n vrB_8_9=(11,15)\n vrB_8_10=(11,15)\n vrB_8_11=(11,15)\n vrB_8_12=(11,15)\n vrB_8_13=(11,15)\n vrB_8_14=(11,15)\n vrB_8_15=(11,15)\n\n\n\tvrCR=(6,10) # AltVect Vector register vrN selector (128 bit)\n\tvrCD=(6,10)\n\n\tvrC_64_0=(6,10) # AltVect Vector register vrN selector (64 bit)\n\tvrC_64_1=(6,10)\n\n\tvrC_32_0=(6,10) # AltVect Vector register vrN selector (32 bit)\n\tvrC_32_1=(6,10)\n\tvrC_32_2=(6,10)\n\tvrC_32_3=(6,10)\n\n vrC_16_0=(6,10) # AltVect Vector register vrN selector (16 bit)\n vrC_16_1=(6,10)\n vrC_16_2=(6,10)\n vrC_16_3=(6,10)\n vrC_16_4=(6,10)\n vrC_16_5=(6,10)\n vrC_16_6=(6,10)\n vrC_16_7=(6,10)\n\n\n vrC_8_0=(6,10) # AltVect Vector register vrN selector (8 bit)\n vrC_8_1=(6,10)\n vrC_8_2=(6,10)\n vrC_8_3=(6,10)\n vrC_8_4=(6,10)\n vrC_8_5=(6,10)\n vrC_8_6=(6,10)\n vrC_8_7=(6,10)\n vrC_8_8=(6,10)\n vrC_8_9=(6,10)\n vrC_8_10=(6,10)\n vrC_8_11=(6,10)\n vrC_8_12=(6,10)\n vrC_8_13=(6,10)\n vrC_8_14=(6,10)\n vrC_8_15=(6,10)\n\n\n\tvrDR=(21,25) # AltVect Vector register vrN selector (128 bit)\n\tvrDD=(21,25)\n\n\tvrD_64_0=(21,25) # AltVect Vector register vrN selector (64 bit)\n\tvrD_64_1=(21,25)\n\n\tvrD_32_0=(21,25) # AltVect Vector register vrN selector (32 bit)\n\tvrD_32_1=(21,25)\n\tvrD_32_2=(21,25)\n\tvrD_32_3=(21,25)\n\n vrD_16_0=(21,25) # AltVect Vector register vrN selector (16 bit)\n vrD_16_1=(21,25)\n vrD_16_2=(21,25)\n vrD_16_3=(21,25)\n vrD_16_4=(21,25)\n vrD_16_5=(21,25)\n vrD_16_6=(21,25)\n vrD_16_7=(21,25)\n\n vrD_8_0=(21,25) # AltVect Vector register vrN selector (8 bit)\n vrD_8_1=(21,25)\n vrD_8_2=(21,25)\n vrD_8_3=(21,25)\n vrD_8_4=(21,25)\n vrD_8_5=(21,25)\n vrD_8_6=(21,25)\n vrD_8_7=(21,25)\n vrD_8_8=(21,25)\n vrD_8_9=(21,25)\n vrD_8_10=(21,25)\n vrD_8_11=(21,25)\n vrD_8_12=(21,25)\n vrD_8_13=(21,25)\n vrD_8_14=(21,25)\n vrD_8_15=(21,25)\n\n\n\tvrSR=(21,25) # AltVect Vector register vrN selector (128 bit)\n\tvrSD=(21,25)\n\n\tvrS_64_0=(21,25) # AltVect Vector register vrN selector (64 bit)\n\tvrS_64_1=(21,25)\n\n\tvrS_32_0=(21,25) # AltVect Vector register vrN selector (32 bit)\n\tvrS_32_1=(21,25)\n\tvrS_32_2=(21,25)\n\tvrS_32_3=(21,25)\n\n vrS_16_0=(21,25) # AltVect Vector register vrN selector (16 bit)\n vrS_16_1=(21,25)\n vrS_16_2=(21,25)\n vrS_16_3=(21,25)\n vrS_16_4=(21,25)\n vrS_16_5=(21,25)\n vrS_16_6=(21,25)\n vrS_16_7=(21,25)\n\n vrS_8_0=(21,25) # AltVect Vector register vrN selector (8 bit)\n vrS_8_1=(21,25)\n vrS_8_2=(21,25)\n vrS_8_3=(21,25)\n vrS_8_4=(21,25)\n vrS_8_5=(21,25)\n vrS_8_6=(21,25)\n vrS_8_7=(21,25)\n vrS_8_8=(21,25)\n vrS_8_9=(21,25)\n vrS_8_10=(21,25)\n vrS_8_11=(21,25)\n vrS_8_12=(21,25)\n vrS_8_13=(21,25)\n vrS_8_14=(21,25)\n vrS_8_15=(21,25)\n\n\tWC=(21,22)\n\t\n\tXOP_0_10=(0,10)\n\tXOP_0_5=(0,5)\n\tXOP_0_8=(0,8)\n\tXOP_0_9=(0,9)\n\tXOP_1_10=(1,10)\n\tXOP_1_4=(1,4)\n\tXOP_1_5=(1,5)\n\tXOP_1_8=(1,8)\n\tXOP_1_9=(1,9)\n\tXOP_2_10=(2,10)\n\tXOP_2_4=(2,4)\n\tXOP_3_5=(3,5)\n\tXOP_3_10=(3,10)\n\tXOP_3_9=(3,9)\n\tXOP_7_10=(7,10)\n# support VSX args\n\tAvsa=(16,20)\n\tAvsb=(16,20)\n\tBvsa=(11,15)\n\tBvsb=(11,15)\n\tCvsa=(6,10)\n\tCvsb=(6,10)\n\tSvsa=(21,25)\n\tSvsb=(21,25)\n\tSvsbx=(21,25)\n\tTvsa=(21,25)\n\tTvsb=(21,25)\n\tTvsbx=(21,25)\n\t\n\tBD15_VLE=(1,15) signed\n\tBD24_VLE=(1,24) signed\n\tBF_VLE=(21,22)\n\tBI_CC_VLE=(16,17)\n\tBI_CR_VLE=(18,19)\n\tBO_VLE=(20,21)\n\t\n\tIMM8=(0,7)\n\tIMM_0_10_VLE=(0,10) \n\tIMM_11_15_VLE=(11,14)\n\tIMM_16_20_VLE=(16,20)\n\tIMM_21_25_VLE=(21,25) \n\tSIMM_11_14_VLE=(11,14) signed\n\tSIMM_21_25_VLE=(21,25) signed\n\tSCL_VLE=(8,9)\n\t\n\tLEV_VLE=(11,15)\n\tXOP_8_VLE=(8,15)\n\tXOP_11_VLE=(11,15)\n\tXOP_12_VLE=(12,15)\n\t\n\tXOP_VLE=(22,25)\n;\t\n\ndefine token instrvle(16)\n\tOP4_VLE=(12,15)\n\tOP5_VLE=(11,15)\n\tOP6_VLE=(10,15)\n\tOP15_VLE=(1,15)\n\tOP16_VLE=(0,15)\n\n\tOIM5_VLE=(4,8)\n\tOIM7_VLE=(4,10)\n\tSD4_VLE=(8,11)\n\tUI7_VLE=(4,10)\n\tUI5_VLE=(4,8)\n\tXORR_VLE=(8,9)\n\tXOR_VLE=(4,9)\n\t\n\tARX_VLE=(0,3)\n\tARY_VLE=(4,7)\n\tRY_VLE=(4,7)\n\tRZ_VLE=(4,7)\n\tRX_VLE=(0,3)\n\n\tBO16_VLE=(10,10)\n\tBIT9_VLE=(9,9)\n\tBIT8_VLE=(8,8)\n\tBI16_VLE=(8,9)\n\tBITS_8_9=(8,9)\n\tBD8_VLE=(0,7) signed\n\t\n\tLK8_VLE=(8,8)\n\tLK0_VLE=(0,0)\n;\n\nEVUIMM_2_RAt: val^\"(\"^RA^\")\"\t is RA & A & EVUIMM_2\t[ val = EVUIMM_2*2; ]\t{ tmp:$(REGISTER_SIZE) = RA+zext(val:4); export tmp; }\nEVUIMM_2_RAt: val^\"(\"^RA^\")\"\t is RA & A=0 & EVUIMM_2\t[ val = EVUIMM_2*2; ]\t{ tmp:$(REGISTER_SIZE) = zext(val:4); export tmp; }\n\nEVUIMM_4_RAt: val^\"(\"^RA^\")\"\t is RA & A & EVUIMM_4\t[ val = EVUIMM_4*4; ]\t{ tmp:$(REGISTER_SIZE) = RA+zext(val:4); export tmp; }\nEVUIMM_4_RAt: val^\"(\"^RA^\")\"\t is RA & A=0 & EVUIMM_4\t[ val = EVUIMM_4*4; ]\t{ tmp:$(REGISTER_SIZE) = zext(val:4); export tmp; }\n\nEVUIMM_8_RAt: val^\"(\"^RA^\")\"\t is RA & A & EVUIMM_8\t[ val = EVUIMM_8*8; ]\t{ tmp:$(REGISTER_SIZE) = RA+zext(val:4); export tmp; }\nEVUIMM_8_RAt: val^\"(\"^RA^\")\"\t is RA & A=0 & EVUIMM_8\t[ val = EVUIMM_8*8; ]\t{ tmp:$(REGISTER_SIZE) = zext(val:4); export tmp; }\n\nattach variables [ T ]\n\t[ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15 \n vs16 vs17 vs18 vs19 vs20 vs21 vs22 vs23 vs24 vs25 vs26 vs27 vs28 vs29 vs30 vs31 \n ];\n\nattach variables [ RX_VLE RY_VLE RZ_VLE]\n\t[ r0 r1 r2 r3 r4 r5 r6 r7 r24 r25 r26 r27 r28 r29 r30 r31];\n\nattach variables [ ARX_VLE ARY_VLE]\n\t[ r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23];\n\nattach variables [ D A B C S TH RA RB RS RT regp]\n [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15\n r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ];\n\nattach variables [ BFA BI_CR CRFD CRFS CR_A CR_B CR_D CR_X ]\n\t[cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7] ;\n\nattach variables [ BI_CR_VLE BF_VLE ]\n\t[cr0 cr1 cr2 cr3 ] ;\n\nattach variables [ fD fB fA fC fS fT ]\n [ f0 f1 f2 f3 f4 f5 f6 f7\n f8 f9 f10 f11 f12 f13 f14 f15\n f16 f17 f18 f19 f20 f21 f22 f23\n f24 f25 f26 f27 f28 f29 f30 f31 ];\n\nattach variables [ CRBD CRBR ]\n [ fp_fx \t\tfp_fex \t\tfp_vx \t\tfp_ox\n\t\t fp_ux \t\tfp_zx \t\tfp_xx \t\tfp_vxsnan\n\t\t fp_vxisi \tfp_vxidi \tfp_vxzdz \tfp_vximz\n\t\t fp_vxvc \t\tfp_fr \t\tfp_fi \t\tfp_c\n\t\t fp_cc0 \t\tfp_cc1 \t\tfp_cc2\t\tfp_cc3\n\t\t fp_reserve1 \tfp_vxsoft \tfp_vxsqrt \tfp_vxcvi\n\t\t fp_ve \t\tfp_oe \t\tfp_ue \t\tfp_ze\n\t\t fp_xe \t\tfp_ni \t\tfp_rn0 \t\tfp_rn1 \n\t\t ];\n\nattach variables SR [\n\t\t\tsr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 sr8 sr9 sr10 sr11 sr12 sr13 sr14 sr15 ];\n\n##\n## Attach the spr register to the token SPRVAL made up of the bits sprL/sprH\n## the low bits are shifted up, so the table is inverted and indexed by sprH,sprL\n## This could have been done by computing sprVal = sprH * 32 + sprL but it would\n## have resulted in multiple instructions instead of the original single prototype.\n## Thus this massive inverted table.\nattach variables SPRVAL [\n\tspr000\tspr020\tspr040\tspr060\tspr080\tspr0a0\tspr0c0\tspr0e0\tspr100\tspr120\tspr140\tspr160\tspr180\tspr1a0\tspr1c0\tspr1e0\tspr200\tspr220\tspr240\tspr260\tspr280\tspr2a0\tspr2c0\tspr2e0\tspr300\tspr320\tspr340\tspr360\tspr380\tspr3a0\tspr3c0\tspr3e0\n\tXER spr021\tspr041\tspr061\tspr081\tspr0a1\tspr0c1\tspr0e1\tspr101\tspr121\tspr141\tspr161\tspr181\tspr1a1\tspr1c1\tspr1e1\tspr201\tspr221\tspr241\tspr261\tspr281\tspr2a1\tspr2c1\tspr2e1\tspr301\tspr321\tspr341\tspr361\tspr381\tspr3a1\tspr3c1\tspr3e1\n\tspr002\tspr022\tspr042\tspr062\tspr082\tspr0a2\tspr0c2\tspr0e2\tspr102\tspr122\tspr142\tspr162\tspr182\tspr1a2\tspr1c2\tspr1e2\tspr202\tspr222\tspr242\tspr262\tspr282\tspr2a2\tspr2c2\tspr2e2\tspr302\tspr322\tspr342\tspr362\tspr382\tspr3a2\tspr3c2\tspr3e2\n\tspr003\tspr023\tspr043\tspr063\tspr083\tspr0a3\tspr0c3\tspr0e3\tspr103\tspr123\tspr143\tspr163\tspr183\tspr1a3\tspr1c3\tspr1e3\tspr203\tspr223\tspr243\tspr263\tspr283\tspr2a3\tspr2c3\tspr2e3\tspr303\tspr323\tspr343\tspr363\tspr383\tspr3a3\tspr3c3\tspr3e3\n\tspr004\tspr024\tspr044\tspr064\tspr084\tspr0a4\tspr0c4\tspr0e4\tspr104\tspr124\tspr144\tspr164\tspr184\tspr1a4\tspr1c4\tspr1e4\tspr204\tspr224\tspr244\tspr264\tspr284\tspr2a4\tspr2c4\tspr2e4\tspr304\tspr324\tspr344\tspr364\tspr384\tspr3a4\tspr3c4\tspr3e4\n\tspr005\tspr025\tspr045\tspr065\tspr085\tspr0a5\tspr0c5\tspr0e5\tspr105\tspr125\tspr145\tspr165\tspr185\tspr1a5\tspr1c5\tspr1e5\tspr205\tspr225\tspr245\tspr265\tspr285\tspr2a5\tspr2c5\tspr2e5\tspr305\tspr325\tspr345\tspr365\tspr385\tspr3a5\tspr3c5\tspr3e5\n\tspr006\tspr026\tspr046\tspr066\tspr086\tspr0a6\tspr0c6\tspr0e6\tspr106\tspr126\tspr146\tspr166\tspr186\tspr1a6\tspr1c6\tspr1e6\tspr206\tspr226\tspr246\tspr266\tspr286\tspr2a6\tspr2c6\tspr2e6\tspr306\tspr326\tspr346\tspr366\tspr386\tspr3a6\tspr3c6\tspr3e6\n\tspr007\tspr027\tspr047\tspr067\tspr087\tspr0a7\tspr0c7\tspr0e7\tspr107\tspr127\tspr147\tspr167\tspr187\tspr1a7\tspr1c7\tspr1e7\tspr207\tspr227\tspr247\tspr267\tspr287\tspr2a7\tspr2c7\tspr2e7\tspr307\tspr327\tspr347\tspr367\tspr387\tspr3a7\tspr3c7\tspr3e7\n\tLR \tspr028\tspr048\tspr068\tspr088\tspr0a8\tspr0c8\tspr0e8\tspr108\tspr128\tspr148\tspr168\tspr188\tspr1a8\tspr1c8\tspr1e8\tspr208\tspr228\tspr248\tspr268\tspr288\tspr2a8\tspr2c8\tspr2e8\tspr308\tspr328\tspr348\tspr368\tspr388\tspr3a8\tspr3c8\tspr3e8\n\tCTR \tspr029\tspr049\tspr069\tspr089\tspr0a9\tspr0c9\tspr0e9\tspr109\tspr129\tspr149\tspr169\tspr189\tspr1a9\tspr1c9\tspr1e9\tspr209\tspr229\tspr249\tspr269\tspr289\tspr2a9\tspr2c9\tspr2e9\tspr309\tspr329\tspr349\tspr369\tspr389\tspr3a9\tspr3c9\tspr3e9\n\tspr00a\tspr02a\tspr04a\tspr06a\tspr08a\tspr0aa\tspr0ca\tspr0ea\tspr10a\tspr12a\tspr14a\tspr16a\tspr18a\tspr1aa\tspr1ca\tspr1ea\tspr20a\tspr22a\tspr24a\tspr26a\tspr28a\tspr2aa\tspr2ca\tspr2ea\tspr30a\tspr32a\tspr34a\tspr36a\tspr38a\tspr3aa\tspr3ca\tspr3ea\n\tspr00b\tspr02b\tspr04b\tspr06b\tspr08b\tspr0ab\tspr0cb\tspr0eb\tspr10b\tspr12b\tspr14b\tspr16b\tspr18b\tspr1ab\tspr1cb\tspr1eb\tspr20b\tspr22b\tspr24b\tspr26b\tspr28b\tspr2ab\tspr2cb\tspr2eb\tspr30b\tspr32b\tspr34b\tspr36b\tspr38b\tspr3ab\tspr3cb\tspr3eb\n\tspr00c\tspr02c\tspr04c\tspr06c\tspr08c\tspr0ac\tspr0cc\tspr0ec\tTBLr\tspr12c\tspr14c\tspr16c\tspr18c\tspr1ac\tspr1cc\tspr1ec\tspr20c\tspr22c\tspr24c\tspr26c\tspr28c\tspr2ac\tspr2cc\tspr2ec\tspr30c spr32c\tspr34c\tspr36c\tspr38c\tspr3ac\tspr3cc\tspr3ec\n\tspr00d\tspr02d\tspr04d\tspr06d\tspr08d\tspr0ad\tspr0cd\tspr0ed\tTBUr\tspr12d\tspr14d\tspr16d\tspr18d\tspr1ad\tspr1cd\tspr1ed\tspr20d\tspr22d\tspr24d\tspr26d\tspr28d\tspr2ad\tspr2cd\tspr2ed\tspr30d spr32d\tspr34d\tspr36d\tspr38d\tspr3ad\tspr3cd\tspr3ed\n\tspr00e\tspr02e\tspr04e\tspr06e\tspr08e\tspr0ae\tspr0ce\tspr0ee\tspr10e\tspr12e\tspr14e\tspr16e\tspr18e\tspr1ae\tspr1ce\tspr1ee\tspr20e\tspr22e\tspr24e\tspr26e\tspr28e\tspr2ae\tspr2ce\tspr2ee\tspr30e\tspr32e\tspr34e\tspr36e\tspr38e\tspr3ae\tspr3ce\tspr3ee\n\tspr00f\tspr02f\tspr04f\tspr06f\tspr08f\tspr0af\tspr0cf\tspr0ef\tspr10f\tspr12f\tspr14f\tspr16f\tspr18f\tspr1af\tspr1cf\tspr1ef\tspr20f\tspr22f\tspr24f\tspr26f\tspr28f\tspr2af\tspr2cf\tspr2ef\tspr30f\tTAR\t \tspr34f\tspr36f\tspr38f\tspr3af\tspr3cf\tspr3ef\n\tspr010\tspr030\tspr050 spr070\tspr090\tspr0b0\tspr0d0\tspr0f0\tspr110\tspr130\tspr150\tspr170\tspr190\tspr1b0\tspr1d0\tspr1f0\tspr210\tspr230\tspr250\tspr270\tspr290\tspr2b0\tspr2d0\tspr2f0\tspr310\tspr330\tspr350\tspr370\tspr390\tspr3b0 \tspr3d0\tspr3f0\n\tspr011\tspr031\tspr051 spr071\tspr091\tspr0b1\tspr0d1\tspr0f1\tspr111\tspr131\tspr151\tspr171\tspr191\tspr1b1\tspr1d1\tspr1f1\tspr211\tspr231\tspr251\tspr271\tspr291\tspr2b1\tspr2d1\tspr2f1\tspr311\tspr331\tspr351\tspr371\tspr391\tspr3b1 \tspr3d1\tspr3f1\n\tspr012\tspr032\tspr052 spr072\tspr092\tspr0b2\tspr0d2\tspr0f2\tspr112\tspr132\tspr152\tspr172\tspr192\tspr1b2\tspr1d2\tspr1f2\tspr212\tspr232\tspr252\tspr272\tspr292\tspr2b2\tspr2d2\tspr2f2\tspr312\tspr332\tspr352\tspr372\tspr392\tspr3b2\tspr3d2\tspr3f2\n\tspr013\tspr033\tspr053\tspr073\tspr093\tspr0b3\tspr0d3\tspr0f3\tspr113\tspr133\tspr153\tspr173\tspr193\tspr1b3\tspr1d3\tspr1f3\tspr213\tspr233\tspr253\tspr273\tspr293\tspr2b3\tspr2d3\tspr2f3\tspr313\tspr333\tspr353\tspr373\tspr393\tspr3b3\tspr3d3\tspr3f3\n\tspr014\tspr034\tspr054\tspr074\tspr094 spr0b4\tspr0d4\tspr0f4\tspr114\tspr134\tspr154\tspr174\tspr194\tspr1b4\tspr1d4\tspr1f4\tspr214\tspr234\tspr254\tspr274\tspr294\tspr2b4\tspr2d4\tspr2f4\tspr314\tspr334\tspr354\tspr374\tspr394\tspr3b4\tspr3d4 \tspr3f4\n\tspr015\tspr035\tspr055\tspr075\tspr095 spr0b5\tspr0d5\tspr0f5\tspr115\tspr135\tspr155\tspr175\tspr195\tspr1b5\tspr1d5\tspr1f5\tspr215\tspr235\tspr255\tspr275\tspr295\tspr2b5\tspr2d5\tspr2f5\tspr315\tspr335\tspr355\tspr375\tspr395\tspr3b5\tspr3d5\tspr3f5\n\tspr016\tspr036\tspr056\tspr076\tspr096\tspr0b6\tspr0d6\tspr0f6\tspr116\tspr136\tspr156\tspr176\tspr196\tspr1b6\tspr1d6\tspr1f6\tspr216\tspr236\tspr256\tspr276\tspr296\tspr2b6\tspr2d6\tspr2f6\tspr316\tspr336\tspr356\tspr376\tspr396\tspr3b6\tspr3d6\tspr3f6\n\tspr017\tspr037\tspr057\tspr077\tspr097\tspr0b7\tspr0d7\tspr0f7\tspr117\tspr137\tspr157\tspr177\tspr197\tspr1b7\tspr1d7\tspr1f7\tspr217\tspr237\tspr257\tspr277\tspr297\tspr2b7\tspr2d7\tspr2f7\tspr317\tspr337\tspr357\tspr377\tspr397\tspr3b7\tspr3d7\tspr3f7\n\tspr018\tspr038\tspr058\tspr078\tspr098\tspr0b8\tspr0d8\tspr0f8\tspr118 spr138\tspr158\tspr178\tspr198\tspr1b8\tspr1d8\tspr1f8\tspr218\tspr238\tspr258\tspr278\tspr298\tspr2b8\tspr2d8\tspr2f8\tspr318\tspr338\tspr358\tspr378\tspr398\tspr3b8 spr3d8 \tspr3f8\n spr019\tspr039\tspr059\tspr079\tspr099\tspr0b9\tspr0d9\tspr0f9\tspr119\tspr139\tspr159\tspr179\tspr199\tspr1b9\tspr1d9\tspr1f9\tspr219\tspr239\tspr259\tspr279\tspr299\tspr2b9\tspr2d9\tspr2f9\tspr319\tspr339\tspr359\tspr379\tspr399\tspr3b9 spr3d9\tspr3f9\n\tSRR0 \tCSRR0\tspr05a\tspr07a\tspr09a\tspr0ba\tspr0da\tspr0fa\tspr11a spr13a\tspr15a\tspr17a\tspr19a\tspr1ba\tspr1da\tspr1fa\tspr21a\tspr23a\tspr25a\tspr27a\tspr29a\tspr2ba\tspr2da\tspr2fa\tspr31a\tspr33a\tspr35a\tspr37a\tspr39a\tspr3ba\tspr3da \tspr3fa\n\tSRR1\tCSRR1\tspr05b\tspr07b\tspr09b\tspr0bb\tspr0db\tspr0fb\tspr11b\tspr13b\tspr15b\tspr17b\tspr19b\tspr1bb\tspr1db\tspr1fb\tspr21b\tspr23b\tspr25b\tspr27b\tspr29b\tspr2bb\tspr2db\tspr2fb\tspr31b\tspr33b\tspr35b\tspr37b\tspr39b\tspr3bb\tspr3db \tspr3fb\n\tspr01c\tspr03c\tspr05c\tspr07c\tspr09c\tspr0bc\tspr0dc\tspr0fc\tTBLw spr13c\tspr15c\tspr17c\tspr19c\tspr1bc\tspr1dc\tspr1fc\tspr21c\tspr23c\tspr25c\tspr27c\tspr29c\tspr2bc\tspr2dc\tspr2fc\tspr31c\tspr33c\tspr35c\tspr37c\tspr39c\tspr3bc\tspr3dc\tspr3fc\n\tspr01d\tspr03d\tspr05d\tspr07d\tspr09d\tspr0bd\tspr0dd\tspr0fd\tTBUw spr13d\tspr15d\tspr17d\tspr19d\tspr1bd\tspr1dd\tspr1fd\tspr21d\tspr23d\tspr25d\tspr27d\tspr29d\tspr2bd\tspr2dd\tspr2fd\tspr31d\tspr33d\tspr35d\tspr37d\tspr39d\tspr3bd\tspr3dd\tspr3fd\n\tspr01e\tspr03e\tspr05e\tspr07e\tspr09e spr0be\tspr0de\tspr0fe\tspr11e\tspr13e\tspr15e\tspr17e\tspr19e\tspr1be\tspr1de\tspr1fe\tspr21e\tspr23e\tspr25e\tspr27e\tspr29e\tspr2be\tspr2de\tspr2fe\tspr31e\tspr33e\tspr35e\tspr37e\tspr39e\tspr3be\tspr3de\tspr3fe\n\tspr01f\tspr03f\tspr05f\tspr07f\tspr09f\tspr0bf\tspr0df\tspr0ff\tspr11f spr13f\tspr15f\tspr17f\tspr19f\tspr1bf\tspr1df\tspr1ff\tspr21f\tspr23f\tspr25f\tspr27f\tspr29f\tspr2bf\tspr2df\tspr2ff\tspr31f\tspr33f\tspr35f\tspr37f\tspr39f\tspr3bf\tspr3df\tspr3ff\n];\n\n##\n## Attach the dcr register to the token DCRN made up of the bits dcrnL/dcrnH\n## the low bits are shifted up, so the table is inverted and indexed by dcrnH,dcrnL\n## This could have been done by computing DCRN = dcrnH * 32 + dcrnL but it would\n## have resulted in multiple instructions instead of the original single prototype.\n## Thus this massive inverted table.\nattach variables DCRN [\n\tdcr000\tdcr020\tdcr040\tdcr060\tdcr080\tdcr0a0\tdcr0c0\tdcr0e0\tdcr100\tdcr120\tdcr140\tdcr160\tdcr180\tdcr1a0\tdcr1c0\tdcr1e0\tdcr200\tdcr220\tdcr240\tdcr260\tdcr280\tdcr2a0\tdcr2c0\tdcr2e0\tdcr300\tdcr320\tdcr340\tdcr360\tdcr380\tdcr3a0\tdcr3c0\tdcr3e0\n\tdcr001 dcr021\tdcr041\tdcr061\tdcr081\tdcr0a1\tdcr0c1\tdcr0e1\tdcr101\tdcr121\tdcr141\tdcr161\tdcr181\tdcr1a1\tdcr1c1\tdcr1e1\tdcr201\tdcr221\tdcr241\tdcr261\tdcr281\tdcr2a1\tdcr2c1\tdcr2e1\tdcr301\tdcr321\tdcr341\tdcr361\tdcr381\tdcr3a1\tdcr3c1\tdcr3e1\n\tdcr002\tdcr022\tdcr042\tdcr062\tdcr082\tdcr0a2\tdcr0c2\tdcr0e2\tdcr102\tdcr122\tdcr142\tdcr162\tdcr182\tdcr1a2\tdcr1c2\tdcr1e2\tdcr202\tdcr222\tdcr242\tdcr262\tdcr282\tdcr2a2\tdcr2c2\tdcr2e2\tdcr302\tdcr322\tdcr342\tdcr362\tdcr382\tdcr3a2\tdcr3c2\tdcr3e2\n\tdcr003\tdcr023\tdcr043\tdcr063\tdcr083\tdcr0a3\tdcr0c3\tdcr0e3\tdcr103\tdcr123\tdcr143\tdcr163\tdcr183\tdcr1a3\tdcr1c3\tdcr1e3\tdcr203\tdcr223\tdcr243\tdcr263\tdcr283\tdcr2a3\tdcr2c3\tdcr2e3\tdcr303\tdcr323\tdcr343\tdcr363\tdcr383\tdcr3a3\tdcr3c3\tdcr3e3\n\tdcr004\tdcr024\tdcr044\tdcr064\tdcr084\tdcr0a4\tdcr0c4\tdcr0e4\tdcr104\tdcr124\tdcr144\tdcr164\tdcr184\tdcr1a4\tdcr1c4\tdcr1e4\tdcr204\tdcr224\tdcr244\tdcr264\tdcr284\tdcr2a4\tdcr2c4\tdcr2e4\tdcr304\tdcr324\tdcr344\tdcr364\tdcr384\tdcr3a4\tdcr3c4\tdcr3e4\n\tdcr005\tdcr025\tdcr045\tdcr065\tdcr085\tdcr0a5\tdcr0c5\tdcr0e5\tdcr105\tdcr125\tdcr145\tdcr165\tdcr185\tdcr1a5\tdcr1c5\tdcr1e5\tdcr205\tdcr225\tdcr245\tdcr265\tdcr285\tdcr2a5\tdcr2c5\tdcr2e5\tdcr305\tdcr325\tdcr345\tdcr365\tdcr385\tdcr3a5\tdcr3c5\tdcr3e5\n\tdcr006\tdcr026\tdcr046\tdcr066\tdcr086\tdcr0a6\tdcr0c6\tdcr0e6\tdcr106\tdcr126\tdcr146\tdcr166\tdcr186\tdcr1a6\tdcr1c6\tdcr1e6\tdcr206\tdcr226\tdcr246\tdcr266\tdcr286\tdcr2a6\tdcr2c6\tdcr2e6\tdcr306\tdcr326\tdcr346\tdcr366\tdcr386\tdcr3a6\tdcr3c6\tdcr3e6\n\tdcr007\tdcr027\tdcr047\tdcr067\tdcr087\tdcr0a7\tdcr0c7\tdcr0e7\tdcr107\tdcr127\tdcr147\tdcr167\tdcr187\tdcr1a7\tdcr1c7\tdcr1e7\tdcr207\tdcr227\tdcr247\tdcr267\tdcr287\tdcr2a7\tdcr2c7\tdcr2e7\tdcr307\tdcr327\tdcr347\tdcr367\tdcr387\tdcr3a7\tdcr3c7\tdcr3e7\n\tdcr008 \tdcr028\tdcr048\tdcr068\tdcr088\tdcr0a8\tdcr0c8\tdcr0e8\tdcr108\tdcr128\tdcr148\tdcr168\tdcr188\tdcr1a8\tdcr1c8\tdcr1e8\tdcr208\tdcr228\tdcr248\tdcr268\tdcr288\tdcr2a8\tdcr2c8\tdcr2e8\tdcr308\tdcr328\tdcr348\tdcr368\tdcr388\tdcr3a8\tdcr3c8\tdcr3e8\n\tdcr009\tdcr029\tdcr049\tdcr069\tdcr089\tdcr0a9\tdcr0c9\tdcr0e9\tdcr109\tdcr129\tdcr149\tdcr169\tdcr189\tdcr1a9\tdcr1c9\tdcr1e9\tdcr209\tdcr229\tdcr249\tdcr269\tdcr289\tdcr2a9\tdcr2c9\tdcr2e9\tdcr309\tdcr329\tdcr349\tdcr369\tdcr389\tdcr3a9\tdcr3c9\tdcr3e9\n\tdcr00a\tdcr02a\tdcr04a\tdcr06a\tdcr08a\tdcr0aa\tdcr0ca\tdcr0ea\tdcr10a\tdcr12a\tdcr14a\tdcr16a\tdcr18a\tdcr1aa\tdcr1ca\tdcr1ea\tdcr20a\tdcr22a\tdcr24a\tdcr26a\tdcr28a\tdcr2aa\tdcr2ca\tdcr2ea\tdcr30a\tdcr32a\tdcr34a\tdcr36a\tdcr38a\tdcr3aa\tdcr3ca\tdcr3ea\n\tdcr00b\tdcr02b\tdcr04b\tdcr06b\tdcr08b\tdcr0ab\tdcr0cb\tdcr0eb\tdcr10b\tdcr12b\tdcr14b\tdcr16b\tdcr18b\tdcr1ab\tdcr1cb\tdcr1eb\tdcr20b\tdcr22b\tdcr24b\tdcr26b\tdcr28b\tdcr2ab\tdcr2cb\tdcr2eb\tdcr30b\tdcr32b\tdcr34b\tdcr36b\tdcr38b\tdcr3ab\tdcr3cb\tdcr3eb\n\tdcr00c\tdcr02c\tdcr04c\tdcr06c\tdcr08c\tdcr0ac\tdcr0cc\tdcr0ec\tdcr10c\tdcr12c\tdcr14c\tdcr16c\tdcr18c\tdcr1ac\tdcr1cc\tdcr1ec\tdcr20c\tdcr22c\tdcr24c\tdcr26c\tdcr28c\tdcr2ac\tdcr2cc\tdcr2ec\tdcr30c dcr32c\tdcr34c\tdcr36c\tdcr38c\tdcr3ac\tdcr3cc\tdcr3ec\n\tdcr00d\tdcr02d\tdcr04d\tdcr06d\tdcr08d\tdcr0ad\tdcr0cd\tdcr0ed\tdcr10d\tdcr12d\tdcr14d\tdcr16d\tdcr18d\tdcr1ad\tdcr1cd\tdcr1ed\tdcr20d\tdcr22d\tdcr24d\tdcr26d\tdcr28d\tdcr2ad\tdcr2cd\tdcr2ed\tdcr30d dcr32d\tdcr34d\tdcr36d\tdcr38d\tdcr3ad\tdcr3cd\tdcr3ed\n\tdcr00e\tdcr02e\tdcr04e\tdcr06e\tdcr08e\tdcr0ae\tdcr0ce\tdcr0ee\tdcr10e\tdcr12e\tdcr14e\tdcr16e\tdcr18e\tdcr1ae\tdcr1ce\tdcr1ee\tdcr20e\tdcr22e\tdcr24e\tdcr26e\tdcr28e\tdcr2ae\tdcr2ce\tdcr2ee\tdcr30e\tdcr32e\tdcr34e\tdcr36e\tdcr38e\tdcr3ae\tdcr3ce\tdcr3ee\n\tdcr00f\tdcr02f\tdcr04f\tdcr06f\tdcr08f\tdcr0af\tdcr0cf\tdcr0ef\tdcr10f\tdcr12f\tdcr14f\tdcr16f\tdcr18f\tdcr1af\tdcr1cf\tdcr1ef\tdcr20f\tdcr22f\tdcr24f\tdcr26f\tdcr28f\tdcr2af\tdcr2cf\tdcr2ef\tdcr30f\tdcr32f\tdcr34f\tdcr36f\tdcr38f\tdcr3af\tdcr3cf\tdcr3ef\n\tdcr010\tdcr030\tdcr050 dcr070\tdcr090\tdcr0b0\tdcr0d0\tdcr0f0\tdcr110\tdcr130\tdcr150\tdcr170\tdcr190\tdcr1b0\tdcr1d0\tdcr1f0\tdcr210\tdcr230\tdcr250\tdcr270\tdcr290\tdcr2b0\tdcr2d0\tdcr2f0\tdcr310\tdcr330\tdcr350\tdcr370\tdcr390\tdcr3b0 \tdcr3d0\tdcr3f0\n\tdcr011\tdcr031\tdcr051 dcr071\tdcr091\tdcr0b1\tdcr0d1\tdcr0f1\tdcr111\tdcr131\tdcr151\tdcr171\tdcr191\tdcr1b1\tdcr1d1\tdcr1f1\tdcr211\tdcr231\tdcr251\tdcr271\tdcr291\tdcr2b1\tdcr2d1\tdcr2f1\tdcr311\tdcr331\tdcr351\tdcr371\tdcr391\tdcr3b1 \tdcr3d1\tdcr3f1\n\tdcr012\tdcr032\tdcr052 dcr072\tdcr092\tdcr0b2\tdcr0d2\tdcr0f2\tdcr112\tdcr132\tdcr152\tdcr172\tdcr192\tdcr1b2\tdcr1d2\tdcr1f2\tdcr212\tdcr232\tdcr252\tdcr272\tdcr292\tdcr2b2\tdcr2d2\tdcr2f2\tdcr312\tdcr332\tdcr352\tdcr372\tdcr392\tdcr3b2\tdcr3d2\tdcr3f2\n\tdcr013\tdcr033\tdcr053\tdcr073\tdcr093\tdcr0b3\tdcr0d3\tdcr0f3\tdcr113\tdcr133\tdcr153\tdcr173\tdcr193\tdcr1b3\tdcr1d3\tdcr1f3\tdcr213\tdcr233\tdcr253\tdcr273\tdcr293\tdcr2b3\tdcr2d3\tdcr2f3\tdcr313\tdcr333\tdcr353\tdcr373\tdcr393\tdcr3b3\tdcr3d3\tdcr3f3\n\tdcr014\tdcr034\tdcr054\tdcr074\tdcr094 dcr0b4\tdcr0d4\tdcr0f4\tdcr114\tdcr134\tdcr154\tdcr174\tdcr194\tdcr1b4\tdcr1d4\tdcr1f4\tdcr214\tdcr234\tdcr254\tdcr274\tdcr294\tdcr2b4\tdcr2d4\tdcr2f4\tdcr314\tdcr334\tdcr354\tdcr374\tdcr394\tdcr3b4\tdcr3d4 \tdcr3f4\n\tdcr015\tdcr035\tdcr055\tdcr075\tdcr095 dcr0b5\tdcr0d5\tdcr0f5\tdcr115\tdcr135\tdcr155\tdcr175\tdcr195\tdcr1b5\tdcr1d5\tdcr1f5\tdcr215\tdcr235\tdcr255\tdcr275\tdcr295\tdcr2b5\tdcr2d5\tdcr2f5\tdcr315\tdcr335\tdcr355\tdcr375\tdcr395\tdcr3b5\tdcr3d5\tdcr3f5\n\tdcr016\tdcr036\tdcr056\tdcr076\tdcr096\tdcr0b6\tdcr0d6\tdcr0f6\tdcr116\tdcr136\tdcr156\tdcr176\tdcr196\tdcr1b6\tdcr1d6\tdcr1f6\tdcr216\tdcr236\tdcr256\tdcr276\tdcr296\tdcr2b6\tdcr2d6\tdcr2f6\tdcr316\tdcr336\tdcr356\tdcr376\tdcr396\tdcr3b6\tdcr3d6\tdcr3f6\n\tdcr017\tdcr037\tdcr057\tdcr077\tdcr097\tdcr0b7\tdcr0d7\tdcr0f7\tdcr117\tdcr137\tdcr157\tdcr177\tdcr197\tdcr1b7\tdcr1d7\tdcr1f7\tdcr217\tdcr237\tdcr257\tdcr277\tdcr297\tdcr2b7\tdcr2d7\tdcr2f7\tdcr317\tdcr337\tdcr357\tdcr377\tdcr397\tdcr3b7\tdcr3d7\tdcr3f7\n\tdcr018\tdcr038\tdcr058\tdcr078\tdcr098\tdcr0b8\tdcr0d8\tdcr0f8\tdcr118 dcr138\tdcr158\tdcr178\tdcr198\tdcr1b8\tdcr1d8\tdcr1f8\tdcr218\tdcr238\tdcr258\tdcr278\tdcr298\tdcr2b8\tdcr2d8\tdcr2f8\tdcr318\tdcr338\tdcr358\tdcr378\tdcr398\tdcr3b8 dcr3d8 \tdcr3f8\n dcr019\tdcr039\tdcr059\tdcr079\tdcr099\tdcr0b9\tdcr0d9\tdcr0f9\tdcr119\tdcr139\tdcr159\tdcr179\tdcr199\tdcr1b9\tdcr1d9\tdcr1f9\tdcr219\tdcr239\tdcr259\tdcr279\tdcr299\tdcr2b9\tdcr2d9\tdcr2f9\tdcr319\tdcr339\tdcr359\tdcr379\tdcr399\tdcr3b9 dcr3d9\tdcr3f9\n\tdcr01a \tdcr03a\tdcr05a\tdcr07a\tdcr09a\tdcr0ba\tdcr0da\tdcr0fa\tdcr11a dcr13a\tdcr15a\tdcr17a\tdcr19a\tdcr1ba\tdcr1da\tdcr1fa\tdcr21a\tdcr23a\tdcr25a\tdcr27a\tdcr29a\tdcr2ba\tdcr2da\tdcr2fa\tdcr31a\tdcr33a\tdcr35a\tdcr37a\tdcr39a\tdcr3ba\tdcr3da \tdcr3fa\n\tdcr01b\tdcr03b\tdcr05b\tdcr07b\tdcr09b\tdcr0bb\tdcr0db\tdcr0fb\tdcr11b\tdcr13b\tdcr15b\tdcr17b\tdcr19b\tdcr1bb\tdcr1db\tdcr1fb\tdcr21b\tdcr23b\tdcr25b\tdcr27b\tdcr29b\tdcr2bb\tdcr2db\tdcr2fb\tdcr31b\tdcr33b\tdcr35b\tdcr37b\tdcr39b\tdcr3bb\tdcr3db \tdcr3fb\n\tdcr01c\tdcr03c\tdcr05c\tdcr07c\tdcr09c\tdcr0bc\tdcr0dc\tdcr0fc\tdcr11c dcr13c\tdcr15c\tdcr17c\tdcr19c\tdcr1bc\tdcr1dc\tdcr1fc\tdcr21c\tdcr23c\tdcr25c\tdcr27c\tdcr29c\tdcr2bc\tdcr2dc\tdcr2fc\tdcr31c\tdcr33c\tdcr35c\tdcr37c\tdcr39c\tdcr3bc\tdcr3dc\tdcr3fc\n\tdcr01d\tdcr03d\tdcr05d\tdcr07d\tdcr09d\tdcr0bd\tdcr0dd\tdcr0fd\tdcr11d dcr13d\tdcr15d\tdcr17d\tdcr19d\tdcr1bd\tdcr1dd\tdcr1fd\tdcr21d\tdcr23d\tdcr25d\tdcr27d\tdcr29d\tdcr2bd\tdcr2dd\tdcr2fd\tdcr31d\tdcr33d\tdcr35d\tdcr37d\tdcr39d\tdcr3bd\tdcr3dd\tdcr3fd\n\tdcr01e\tdcr03e\tdcr05e\tdcr07e\tdcr09e dcr0be\tdcr0de\tdcr0fe\tdcr11e\tdcr13e\tdcr15e\tdcr17e\tdcr19e\tdcr1be\tdcr1de\tdcr1fe\tdcr21e\tdcr23e\tdcr25e\tdcr27e\tdcr29e\tdcr2be\tdcr2de\tdcr2fe\tdcr31e\tdcr33e\tdcr35e\tdcr37e\tdcr39e\tdcr3be\tdcr3de\tdcr3fe\n\tdcr01f\tdcr03f\tdcr05f\tdcr07f\tdcr09f\tdcr0bf\tdcr0df\tdcr0ff\tdcr11f dcr13f\tdcr15f\tdcr17f\tdcr19f\tdcr1bf\tdcr1df\tdcr1ff\tdcr21f\tdcr23f\tdcr25f\tdcr27f\tdcr29f\tdcr2bf\tdcr2df\tdcr2ff\tdcr31f\tdcr33f\tdcr35f\tdcr37f\tdcr39f\tdcr3bf\tdcr3df\tdcr3ff\n];\n\nattach variables [vrDR vrAR vrBR vrSR vrCR]\n\t[ vs32 vs33 vs34 vs35 vs36 vs37 vs38 vs39 vs40 vs41 vs42 vs43 vs44 vs45 vs46 vs47 \n vs48 vs49 vs50 vs51 vs52 vs53 vs54 vs55 vs56 vs57 vs58 vs59 vs60 vs61 vs62 vs63 ];\n \n## These attaches are for the Altivec instructions\nattach names [ vrDD vrAD vrBD vrSD vrCD]\n [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];\n \nvrD: vrDD\tis vrDD & vrDR { export vrDR; } \nvrA: vrAD\tis vrAD & vrAR { export vrAR; } \nvrB: vrBD\tis vrBD & vrBR { export vrBR; } \nvrC: vrCD\tis vrCD & vrCR { export vrCR; } \nvrS: vrSD\tis vrSD & vrSR { export vrSR; } \n\n# AltVect Vector vrD sub-piece selectors \n\n# AltVect Vector vrD sub-piece selectors for size 64\nattach variables vrD_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ];\nattach variables vrD_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ];\n\n# AltVect Vector vrD sub-piece selectors for size 32\nattach variables vrD_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ];\nattach variables vrD_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ];\nattach variables vrD_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ];\nattach variables vrD_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ];\n\n# AltVect Vector vrD sub-piece selectors for size 16\nattach variables vrD_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ];\nattach variables vrD_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ];\nattach variables vrD_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ];\nattach variables vrD_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ];\nattach variables vrD_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ];\nattach variables vrD_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ];\nattach variables vrD_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ];\nattach variables vrD_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ];\n\n# AltVect Vector vrD sub-piece selectors for size 8\nattach variables vrD_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ];\nattach variables vrD_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ];\nattach variables vrD_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ];\nattach variables vrD_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ];\nattach variables vrD_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ];\nattach variables vrD_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ];\nattach variables vrD_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ];\nattach variables vrD_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ];\nattach variables vrD_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ];\nattach variables vrD_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ];\nattach variables vrD_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ];\nattach variables vrD_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ];\nattach variables vrD_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ];\nattach variables vrD_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ];\nattach variables vrD_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ];\nattach variables vrD_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ];\n\n\n# AltVect Vector vrA sub-piece selectors \n\n# AltVect Vector vrA sub-piece selectors for size 64\nattach variables vrA_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ];\nattach variables vrA_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ];\n\n# AltVect Vector vrA sub-piece selectors for size 32\nattach variables vrA_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ];\nattach variables vrA_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ];\nattach variables vrA_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ];\nattach variables vrA_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ];\n\n# AltVect Vector vrA sub-piece selectors for size 16\nattach variables vrA_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ];\nattach variables vrA_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ];\nattach variables vrA_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ];\nattach variables vrA_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ];\nattach variables vrA_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ];\nattach variables vrA_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ];\nattach variables vrA_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ];\nattach variables vrA_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ];\n\n# AltVect Vector vrA sub-piece selectors for size 8\nattach variables vrA_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ];\nattach variables vrA_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ];\nattach variables vrA_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ];\nattach variables vrA_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ];\nattach variables vrA_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ];\nattach variables vrA_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ];\nattach variables vrA_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ];\nattach variables vrA_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ];\nattach variables vrA_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ];\nattach variables vrA_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ];\nattach variables vrA_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ];\nattach variables vrA_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ];\nattach variables vrA_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ];\nattach variables vrA_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ];\nattach variables vrA_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ];\nattach variables vrA_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ];\n\n\n# AltVect Vector vrB sub-piece selectors \n\n# AltVect Vector vrB sub-piece selectors for size 64\nattach variables vrB_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ];\nattach variables vrB_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ];\n\n# AltVect Vector vrB sub-piece selectors for size 32\nattach variables vrB_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ];\nattach variables vrB_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ];\nattach variables vrB_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ];\nattach variables vrB_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ];\n\n# AltVect Vector vrB sub-piece selectors for size 16\nattach variables vrB_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ];\nattach variables vrB_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ];\nattach variables vrB_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ];\nattach variables vrB_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ];\nattach variables vrB_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ];\nattach variables vrB_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ];\nattach variables vrB_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ];\nattach variables vrB_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ];\n\n# AltVect Vector vrB sub-piece selectors for size 8\nattach variables vrB_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ];\nattach variables vrB_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ];\nattach variables vrB_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ];\nattach variables vrB_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ];\nattach variables vrB_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ];\nattach variables vrB_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ];\nattach variables vrB_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ];\nattach variables vrB_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ];\nattach variables vrB_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ];\nattach variables vrB_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ];\nattach variables vrB_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ];\nattach variables vrB_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ];\nattach variables vrB_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ];\nattach variables vrB_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ];\nattach variables vrB_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ];\nattach variables vrB_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ];\n\n\n# AltVect Vector vrS sub-piece selectors \n\n# AltVect Vector vrS sub-piece selectors for size 64\nattach variables vrS_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ];\nattach variables vrS_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ];\n\n# AltVect Vector vrS sub-piece selectors for size 32\nattach variables vrS_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ];\nattach variables vrS_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ];\nattach variables vrS_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ];\nattach variables vrS_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ];\n\n# AltVect Vector vrS sub-piece selectors for size 16\nattach variables vrS_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ];\nattach variables vrS_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ];\nattach variables vrS_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ];\nattach variables vrS_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ];\nattach variables vrS_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ];\nattach variables vrS_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ];\nattach variables vrS_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ];\nattach variables vrS_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ];\n\n# AltVect Vector vrS sub-piece selectors for size 8\nattach variables vrS_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ];\nattach variables vrS_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ];\nattach variables vrS_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ];\nattach variables vrS_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ];\nattach variables vrS_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ];\nattach variables vrS_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ];\nattach variables vrS_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ];\nattach variables vrS_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ];\nattach variables vrS_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ];\nattach variables vrS_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ];\nattach variables vrS_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ];\nattach variables vrS_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ];\nattach variables vrS_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ];\nattach variables vrS_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ];\nattach variables vrS_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ];\nattach variables vrS_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ];\n\n\n# AltVect Vector vrC sub-piece selectors \n\n# AltVect Vector vrC sub-piece selectors for size 64\nattach variables vrC_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ];\nattach variables vrC_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ];\n\n# AltVect Vector vrC sub-piece selectors for size 32\nattach variables vrC_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ];\nattach variables vrC_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ];\nattach variables vrC_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ];\nattach variables vrC_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ];\n\n# AltVect Vector vrC sub-piece selectors for size 16\nattach variables vrC_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ];\nattach variables vrC_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ];\nattach variables vrC_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ];\nattach variables vrC_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ];\nattach variables vrC_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ];\nattach variables vrC_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ];\nattach variables vrC_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ];\nattach variables vrC_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ];\n\n# AltVect Vector vrC sub-piece selectors for size 8\nattach variables vrC_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ];\nattach variables vrC_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ];\nattach variables vrC_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ];\nattach variables vrC_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ];\nattach variables vrC_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ];\nattach variables vrC_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ];\nattach variables vrC_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ];\nattach variables vrC_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ];\nattach variables vrC_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ];\nattach variables vrC_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ];\nattach variables vrC_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ];\nattach variables vrC_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ];\nattach variables vrC_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ];\nattach variables vrC_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ];\nattach variables vrC_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ];\nattach variables vrC_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ];\n\n################################################################\n# Pseudo Instructions\n################################################################\n\ndefine pcodeop clearHistory;\ndefine pcodeop countTrailingZeros;\ndefine pcodeop dataCacheBlockAllocate;\ndefine pcodeop dataCacheBlockFlush;\ndefine pcodeop dataCacheBlockInvalidate;\ndefine pcodeop dataCacheBlockStore;\ndefine pcodeop dataCacheBlockTouch;\ndefine pcodeop dataCacheBlockTouchForStore;\ndefine pcodeop dataCacheBlockClearToZero;\ndefine pcodeop dataCacheCongruenceClassInvalidate;\ndefine pcodeop dataCacheRead;\ndefine pcodeop externalControlIn;\ndefine pcodeop externalControlOut;\ndefine pcodeop enforceInOrderExecutionIO;\ndefine pcodeop instructionCacheBlockInvalidate;\ndefine pcodeop instructionCacheBlockTouch;\ndefine pcodeop instructionCacheCongruenceClassInvalidate;\ndefine pcodeop instructionCacheRead;\ndefine pcodeop instructionSynchronize;\n\n\ndefine pcodeop floatAddOverflow;\ndefine pcodeop floatDivOverflow;\ndefine pcodeop floatAddRoundedUp;\ndefine pcodeop floatDivRoundedUp;\ndefine pcodeop floatAddInexact;\ndefine pcodeop floatDivInexact;\ndefine pcodeop floatAddUnderflow;\ndefine pcodeop floatDivUnderflow;\ndefine pcodeop floatInfinityAdd;\ndefine pcodeop intToFloatRoundedUp;\ndefine pcodeop intToFloatInexact;\ndefine pcodeop invalidFloatToInt;\ndefine pcodeop floatToIntRoundedUp;\ndefine pcodeop floatToIntInexact;\ndefine pcodeop floatInfinityDivide;\ndefine pcodeop floatMaddInexact;\ndefine pcodeop floatMaddRoundedUp;\ndefine pcodeop floatMaddOverflow;\ndefine pcodeop floatMaddUnderflow;\ndefine pcodeop floatInfinityMulZero;\n\ndefine pcodeop floatMsubInexact;\ndefine pcodeop floatMsubRoundedUp;\ndefine pcodeop floatMsubOverflow;\ndefine pcodeop floatMsubUnderflow;\ndefine pcodeop floatInfinitySub;\n\ndefine pcodeop floatSubRoundedUp;\ndefine pcodeop floatSubInexact;\ndefine pcodeop floatSubOverflow;\ndefine pcodeop floatSubUnderflow;\n\ndefine pcodeop floatMulRoundedUp;\ndefine pcodeop floatMulOverflow;\ndefine pcodeop floatMulUnderflow;\ndefine pcodeop floatMulInexact;\ndefine pcodeop sqrtInvalid;\ndefine pcodeop floatSqrtRoundedUp;\ndefine pcodeop floatSqrtInexact;\n\ndefine pcodeop eventInterrupt;\ndefine pcodeop illegal;\ndefine pcodeop message;\ndefine pcodeop movebuffer;\ndefine pcodeop stopT;\ndefine pcodeop waitT;\n\ndefine pcodeop mematom;\n\ndefine pcodeop random;\ndefine pcodeop returnFromInterrupt;\ndefine pcodeop returnFromCriticalInterrupt;\ndefine pcodeop returnFromDebugInterrupt;\ndefine pcodeop returnFromGuestInterrupt;\ndefine pcodeop returnFromMachineCheckInterrupt;\ndefine pcodeop syscall;\ndefine pcodeop slbInvalidateAll;\ndefine pcodeop slbInvalidateEntry;\ndefine pcodeop slbMoveFromEntryESID;\ndefine pcodeop slbMoveFromEntryVSID;\ndefine pcodeop slbMoveToEntry;\ndefine pcodeop storeDoubleWordConditionalIndexed;\ndefine pcodeop storeWordConditionalIndexed;\ndefine pcodeop trapWord;\ndefine pcodeop trapDoubleWordImmediate;\ndefine pcodeop trapDoubleWord;\ndefine pcodeop sync;\ndefine pcodeop loadString;\ndefine pcodeop storeString;\n\ndefine pcodeop xer_mac_update;\n\ndefine pcodeop macchw;\ndefine pcodeop macchws;\ndefine pcodeop macchwsu;\ndefine pcodeop macchwu;\n\ndefine pcodeop machhw;\ndefine pcodeop machhws;\ndefine pcodeop machhwsu;\ndefine pcodeop machhwu;\n\ndefine pcodeop maclhw;\ndefine pcodeop maclhws;\ndefine pcodeop maclhwsu;\ndefine pcodeop maclhwu;\n\ndefine pcodeop mulchw;\ndefine pcodeop mulchwu;\n\ndefine pcodeop mulhhw;\ndefine pcodeop mulhhwu;\n\ndefine pcodeop mullhw;\ndefine pcodeop mullhwu;\n\ndefine pcodeop nmacchw;\ndefine pcodeop nmacchws;\n\ndefine pcodeop nmachhw;\ndefine pcodeop nmachhws;\n\ndefine pcodeop nmaclhw;\ndefine pcodeop nmaclhws;\n\ndefine pcodeop copytrans;\ndefine pcodeop pastetrans;\ndefine pcodeop transaction;\ndefine pcodeop TLBRead;\ndefine pcodeop TLBSearchIndexed;\ndefine pcodeop TLBWrite;\ndefine pcodeop WriteExternalEnable;\ndefine pcodeop WriteExternalEnableImmediate;\n\n# This is really used in the altivec version, but since it's a registered pcode op\n# and due to the way things get @included, this needs to be here\ndefine pcodeop vectorPermute;\n\n\n################################################################\n# Macros\n################################################################\n\nmacro shiftCarry(value, sa)\n{\n\tlocal mask = value; # force mask to have same size as value (may vary)\n\tmask = (1 << sa) - 1;\n\txer_ca = (value s< 0) && ((value & mask)!=0);\n}\nmacro getCrBit(crReg, bitIndex, result) \n{\n\ttmp:1 = crReg >> (3-bitIndex);\n\tresult = tmp & 1;\n}\nmacro setCrBit(crReg, bitIndex, bit)\n{\n\tshift:1 = 3-bitIndex;\n\tmask:1 = ~(1< 0)); # 0b010\n\tsetCrBit(cr0, 2, (result == 0)); # 0b001\n\tsetCrBit(cr0, 3, (xer_so & 1));\n}\n\nmacro addOverflow(a,b) {\n\txer_ov = scarry(a,b);\n\txer_so = xer_so || xer_ov;\n}\n\nmacro subOverflow(a,b) {\n\txer_ov = sborrow(a,b);\n\txer_so = xer_so || xer_ov;\n}\n\nmacro addExtendedCarry(op1,op2){\n\tlocal carryIn:$(REGISTER_SIZE) = zext(xer_ca);\n\ttmp:$(REGISTER_SIZE) = op2 + carryIn;\n\txer_ca = carry(op2, carryIn) || carry(op1, tmp);\n}\n\nmacro addExtendedOverflow(op1, op2) {\n\tlocal carryIn:$(REGISTER_SIZE) = zext(xer_ca);\n\ttmp:$(REGISTER_SIZE) = op1 + op2;\n\txer_ov = scarry(op1,op2) ^^ scarry(tmp, carryIn);\n\txer_so = xer_so || xer_ov;\n}\n\nmacro subExtendedCarry(op1,op2){\n\tlocal carryIn = zext(!xer_ca);\n\tlocal CYa = op1 < op2;\n\tlocal result = op1 - op2;\n\txer_ca = !(CYa || (result < carryIn) );\n}\n\nmacro subExtendedOverflow(op1, op2) {\n\tlocal carryIn = zext(!xer_ca);\n\tlocal result = op1 - op2;\n\txer_ov = sborrow( op1, op2 ) ^^ sborrow( result, carryIn );\n\txer_so = xer_so || xer_ov;\n}\n\n# check b=0 or (a=0x80000000 and b=-1)\nmacro divOverflow(a,b) {\n\txer_ov = (b==0) || ((b==-1) && (a==0x80000000));\n\txer_so = xer_so || xer_ov;\n}\nmacro divZero(b) {\n\txer_ov = (b==0);\n\txer_so = xer_so || xer_ov;\n}\n\nmacro mulOverflow64(result) {\n\tlocal tmp:4 = result(0);\n\tlocal sext_tmp:8 = sext(tmp);\n\txer_ov = (sext_tmp != result);\n\txer_so = xer_so || xer_ov;\n}\n\nmacro mulOverflow128(result) {\n\tlocal tmp:8 = result(0);\n\tlocal sext_tmp:16 = sext(tmp);\n\txer_ov = (sext_tmp != result);\n\txer_so = xer_so || xer_ov;\n}\n\nmacro cr1flags() {\n\tsetCrBit(cr1, 0, fp_fx);\n\tsetCrBit(cr1, 1, fp_fex);\n\tsetCrBit(cr1, 2, fp_vx);\n\tsetCrBit(cr3, 2, fp_ox);\n}\nmacro setFPRF(result) {\n\tfp_cc0 = result f< 0;\n\tfp_cc1 = result f> 0;\n\tfp_cc2 = result f== 0;\n\tfp_cc3 = nan(result);\n}\n\nmacro setSummaryFPSCR() {\n\tfp_vx = fp_vxsnan | fp_vxisi | fp_vxidi | fp_vxzdz | fp_vximz | fp_vxvc | fp_vxsoft | fp_vxsqrt | fp_vxcvi;\n\tfp_fx = fp_fx | fp_ox | fp_ux | fp_zx | fp_xx;\n\tfp_fex = (fp_vx & fp_ve) ^ (fp_ox & fp_oe) ^ (fp_ux & fp_ue) ^ (fp_zx & fp_ze) ^ (fp_xx & fp_xe);\n}\n\nmacro setFPAddFlags(op1, op2, result) {\n\tsetFPRF(result);\n#\tfp_fr = floatAddRoundedUp(op1, op2);\n#\tfp_fi = floatAddInexact(op1, op2);\n#\tfp_ox = fp_ox | floatAddOverflow(op1, op2);\n#\tfp_ux = fp_ux | floatAddUnderflow(op1, op2);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(op1) | nan(op2);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(op1, op2);\n\tsetSummaryFPSCR();\n}\nmacro setFPDivFlags(op1, op2, result) {\n\tsetFPRF(result);\n#\tfp_fr = floatDivRoundedUp(op1, op2);\n#\tfp_fi = floatDivInexact(op1, op2);\n#\tfp_ox = fp_ox | floatDivOverflow(op1, op2);\n#\tfp_ux = fp_ux | floatDivUnderflow(op1, op2);\n\tfp_zx = fp_zx | (op2 f== 0);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(op1) | nan(op2);\n#\tfp_vxidi = fp_vxidi | floatInfinityDivide(op1, op2);\n\tfp_vxzdz = fp_vxzdz | ((op1 f== 0) && (op2 f== 0));\n\tsetSummaryFPSCR();\n}\nmacro setFPMulFlags(op1, op2, result) {\n\tsetFPRF(result);\n#\tfp_fr = floatMulRoundedUp(op1, op2);\n#\tfp_fi = floatMulInexact(op1, op2);\n#\tfp_ox = fp_ox | floatMulOverflow(op1, op2);\n#\tfp_ux = fp_ux | floatMulUnderflow(op1, op2);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(op1) | nan(op2);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(op1, op2);\n\tsetSummaryFPSCR();\n}\nmacro setFPSubFlags(op1, op2, result) {\n\tsetFPRF(result);\n#\tfp_fr = floatSubRoundedUp(op1, op2);\n#\tfp_fi = floatSubInexact(op1, op2);\n#\tfp_ox = fp_ox | floatSubOverflow(op1, op2);\n#\tfp_ux = fp_ux | floatSubUnderflow(op1, op2);\n#\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(op1) | nan(op2);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(op1, op2);\n\tsetSummaryFPSCR();\n}\n\nmacro loadRegister(reg, ea) {\n@ifdef BIT_64\n\treg = zext(*:4(ea));\n@else\n\treg = *:4(ea);\n@endif\n\tea = ea+4;\n}\n\nmacro loadReg(reg) {\n@ifdef BIT_64\n\treg = zext(*:4(tea));\n@else\n\treg = *:4(tea);\n@endif\n\ttea = tea+4;\n}\n\nmacro loadRegisterPartial(reg, ea, sa) {\n\tmask:$(REGISTER_SIZE) = 0xffffffff;\n\tsa = ((4-sa) & 3) * 8;\n\tmask = mask << sa;\n@ifdef BIT_64\n\treg = zext(*:4(ea));\n@else\n\treg = *:4(ea);\n@endif\n reg = reg & mask;\n ea = ea + 4;\n}\n\nmacro storeRegister(reg, ea) {\n@ifdef BIT_64\n tmp:8 = reg; # workaround\n\t*:4(ea) = tmp:4;\n@else\n\t*:4(ea) = reg;\n@endif\n\tea = ea+4;\n}\t\n\nmacro storeReg(reg) {\n@ifdef BIT_64\n\ttmp:8 = reg; # workaround\n\t*:4(tea) = tmp:4;\n@else\n\t*:4(tea) = reg;\n@endif\n\ttea = tea+4;\n}\t\n\nmacro storeRegisterPartial(reg, ea, sa) {\n@ifdef BIT_64\n tmp:8 = reg; # workaround\n *:4(ea) = tmp:4;\n@else\n *:4(ea) = reg;\n@endif\n ea = ea + 4;\n}\n\n\nmacro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,\n a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) {\n D = zext(a31) & 1;\n D=D|(zext(a0)&1)<<31; D=D|(zext(a1)&1)<<30; D=D|(zext(a2)&1)<<29; D=D|(zext(a3)&1)<<28;\n D=D|(zext(a4)&1)<<27; D=D|(zext(a5)&1)<<26; D=D|(zext(a6)&1)<<25; D=D|(zext(a7)&1)<<24;\n D=D|(zext(a8)&1)<<23; D=D|(zext(a9)&1)<<22; D=D|(zext(a10)&1)<<21; D=D|(zext(a11)&1)<<20;\n D=D|(zext(a12)&1)<<19; D=D|(zext(a13)&1)<<18; D=D|(zext(a14)&1)<<17; D=D|(zext(a15)&1)<<16;\n D=D|(zext(a16)&1)<<15; D=D|(zext(a17)&1)<<14; D=D|(zext(a18)&1)<<13; D=D|(zext(a19)&1)<<12;\n D=D|(zext(a20)&1)<<11; D=D|(zext(a21)&1)<<10; D=D|(zext(a22)&1)<<9; D=D|(zext(a23)&1)<<8;\n D=D|(zext(a24)&1)<<7; D=D|(zext(a25)&1)<<6; D=D|(zext(a26)&1)<<5; D=D|(zext(a27)&1)<<4;\n D=D|(zext(a28)&1)<<3; D=D|(zext(a29)&1)<<2; D=D|(zext(a30)&1)<<1;\n }\n\nmacro unpackbits(D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,\n a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) {\n a0=(D&0x80000000)!=0; a1=(D&0x40000000)!=0; a2=(D&0x20000000)!=0; a3=(D&0x10000000)!=0;\n a4=(D&0x8000000)!=0; a5=(D&0x4000000)!=0; a6=(D&0x2000000)!=0; a7=(D&0x1000000)!=0;\n a8=(D&0x800000)!=0; a9=(D&0x400000)!=0; a10=(D&0x200000)!=0; a11=(D&0x100000)!=0;\n a12=(D&0x80000)!=0; a13=(D&0x40000)!=0; a14=(D&0x20000)!=0; a15=(D&0x10000)!=0;\n a16=(D&0x8000)!=0; a17=(D&0x4000)!=0; a18=(D&0x2000)!=0; a19=(D&0x1000)!=0;\n a20=(D&0x800)!=0; a21=(D&0x400)!=0; a22=(D&0x200)!=0; a23=(D&0x100)!=0;\n a24=(D&0x80)!=0; a25=(D&0x40)!=0; a26=(D&0x20)!=0; a27=(D&0x10)!=0;\n a28=(D&0x8)!=0; a29=(D&0x4)!=0; a30=(D&0x2)!=0; a31=(D&0x1)!=0; }\n\nmacro packFPSCR(tmp) {\n\tpackbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, fp_ux, fp_zx, fp_xx, fp_vxsnan,\n\tfp_vxisi, fp_vxidi, fp_vxzdz, fp_vximz, fp_vxvc, fp_fr, fp_fi, fp_c,\n\tfp_cc0, fp_cc1, fp_cc2, fp_cc3, fp_reserve1, fp_vxsoft, fp_vxsqrt,\n\tfp_vxcvi, fp_ve, fp_oe, fp_ue, fp_ze, fp_xe, fp_ni, fp_rn0, fp_rn1);\n}\nmacro unpackFPSCR(tmp) {\n unpackbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox,\n\t\t fp_ux, fp_zx, fp_xx, fp_vxsnan,\n\t\t fp_vxisi, fp_vxidi, fp_vxzdz, fp_vximz,\n\t\t fp_vxvc, fp_fr, fp_fi, fp_c,\n\t\t fp_cc0, fp_cc1, fp_cc2, fp_cc3,\n\t\t fp_reserve1, fp_vxsoft, fp_vxsqrt, fp_vxcvi,\n\t\t fp_ve, fp_oe, fp_ue, fp_ze,\n\t\t fp_xe, fp_ni, fp_rn0, fp_rn1); \n}\n\n\n################################################################\n# Sub-Constructors\n################################################################\nREL_ABS: \"a\"\tis AA = 1 {}\nREL_ABS:\t\t\tis AA = 0 {}\n\naddressLI: reloc\t\tis LI & AA=0 \t[ reloc = inst_start + LI*4;] \t{ export *[ram]:4 reloc; }\naddressLI: reloc \tis LI & AA=1\t\t[ reloc = LI*4; ]\t\t\t\t{ export *[ram]:4 reloc; }\naddressBD: reloc\t\tis BD & AA=0\t\t[ reloc = inst_start + BD*4; ]\t{ export *[ram]:4 reloc; }\naddressBD: reloc\t\tis BD & AA=1\t\t[ reloc = BD*4; ]\t\t\t\t{ export *[ram]:4 reloc; }\n\nOFF16SH: val\t\tis D0 & D1 & D2 [ val = ((D0 << 6) | (D1 << 1) | D2) << 16; ] { export *[const]:4 val;}\n\n# X 00-------------------------------06 07-07 08-----------10 11-----------13 14------15 16----------------------------------------------------------------------------31 \n# X -----------------?-----------------|BO_1=1|-------?-------|-----BI_CR-----|--BI_CC---|---------------------------------------?----------------------------------------|\nCC: \"lt\"\t\tis BI_CC=0 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC: \"le\"\t\tis BI_CC=1 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; }\nCC: \"eq\"\t\tis BI_CC=2 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC: \"ge\"\t\tis BI_CC=0 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; }\nCC: \"gt\"\t\tis BI_CC=1 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC: \"ne\"\t\tis BI_CC=2 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; }\nCC: \"so\"\t\tis BI_CC=3 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC: \"ns\"\t\tis BI_CC=3 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; }\n\nTOm: \"lt\"\t\tis TO=16 { }\nTOm: \"le\"\t\tis TO=20 { }\nTOm: \"eq\"\t\tis TO=4 { }\nTOm: \"ge\"\t\tis TO=12 { }\nTOm: \"gt\"\t\tis TO=8 { }\nTOm: \"ne\"\t\tis TO=24 { }\nTOm: \"llt\"\t\tis TO=2 { }\nTOm: \"lle\"\t\tis TO=6 { }\nTOm: \"lge\"\t\tis TO=5 { }\nTOm: \"lgt\"\t\tis TO=1 { }\nTOm: \"\"\t\t\tis TO { }\n\nCTR_DEC: \"z\"\tis BO_3=1 \t{CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; }\nCTR_DEC: \"nz\"\tis BO_3=0 \t{CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; }\n\nCC_TF: \"t\"\t\tis BO_1=1\t{ tmp:1 = 1; export tmp; }\nCC_TF: \"f\"\t\tis BO_1=0\t{ tmp:1 = 0; export tmp; }\n\n# OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0\n\n\n# X 00---------------------------------------------------10 11-----------13 14------15 16----------------------------------------------------------------------------31 \n# X ---------------------------?---------------------------|----BI_CR=0----|--BI_CC---|---------------------------------------?----------------------------------------|\nCC_OP: \"lt\"\t\t\t\t\tis BI_CC=0 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; }\nCC_OP: \"eq\"\t\t\t\t\tis BI_CC=2 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; }\nCC_OP: \"gt\"\t\t\t\t\tis BI_CC=1 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; }\nCC_OP: \"so\"\t\t\t\t\tis BI_CC=3 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; }\nCC_OP: \"4*\"^BI_CR^\"+lt\"\t\tis BI_CC=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC_OP: \"4*\"^BI_CR^\"+eq\"\t\tis BI_CC=2 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC_OP: \"4*\"^BI_CR^\"+gt\"\t\tis BI_CC=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\nCC_OP: \"4*\"^BI_CR^\"+so\"\t\tis BI_CC=3 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; }\n\n# X 00----------------------------------------------------------------------------15 16-----------18 19------20 21---------------------------------------------------31 \n# X ---------------------------------------?----------------------------------------|----CR_B=0-----|-CR_B_CC--|---------------------------?---------------------------|\nCC_B_OP: \"lt\"\t\t\t\t\tis CR_B_CC=0 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"eq\"\t\t\t\t\tis CR_B_CC=2 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"gt\"\t\t\t\t\tis CR_B_CC=1 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"so\"\t\t\t\t\tis CR_B_CC=3 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"4*\"^CR_B^\"+lt\"\t\tis CR_B_CC=0 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"4*\"^CR_B^\"+eq\"\t\tis CR_B_CC=2 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"4*\"^CR_B^\"+gt\"\t\tis CR_B_CC=1 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; }\nCC_B_OP: \"4*\"^CR_B^\"+so\"\t\tis CR_B_CC=3 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; }\n\n# X 00-----------------------------------------------------------------------------------------------------20 21-----------23 24------25 26--------------------------31 \n# X ----------------------------------------------------?----------------------------------------------------|----CR_X=0-----|-CR_X_CC--|--------------?---------------|\nCC_X_OP: cr0\t\t\t\t\tis CR_X_CC=0 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; }\nCC_X_OP: cr0\t\t\t\t\tis CR_X_CC=1 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; }\nCC_X_OP: cr0\t\t\t\t\tis CR_X_CC=2 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; }\nCC_X_OP: cr0\t\t\t\t\tis CR_X_CC=3 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; }\nCC_X_OP: CR_X\t\t\t\t\tis CR_X_CC=0 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; }\nCC_X_OP: CR_X\t\t\t\t\tis CR_X_CC=1 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; }\nCC_X_OP: CR_X\t\t\t\t\tis CR_X_CC=2 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; }\nCC_X_OP: CR_X\t\t\t\t\tis CR_X_CC=3 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; }\n\nCC_X_OPm: \"lt\"\t\t\t\t\tis CR_X_CC=0 & CR_X=0 & CR_X_CC { }\nCC_X_OPm: \"gt\"\t\t\t\t\tis CR_X_CC=1 & CR_X=0 & CR_X_CC { }\nCC_X_OPm: \"eq\"\t\t\t\t\tis CR_X_CC=2 & CR_X=0 & CR_X_CC { }\nCC_X_OPm: \"so\"\t\t\t\t\tis CR_X_CC=3 & CR_X=0 & CR_X_CC { }\nCC_X_OPm: \"lt\"\t\t\t\t\tis CR_X_CC=0 & CR_X & CR_X_CC { }\nCC_X_OPm: \"gt\"\t\t\t\t\tis CR_X_CC=1 & CR_X & CR_X_CC { }\nCC_X_OPm: \"eq\"\t\t\t\t\tis CR_X_CC=2 & CR_X & CR_X_CC { }\nCC_X_OPm: \"so\"\t\t\t\t\tis CR_X_CC=3 & CR_X & CR_X_CC { }\n\n# X 00--------------------------05 06-----------08 09------10 11-----------------------------------------------------------------------------------------------------31 \n# X --------------?---------------|----CR_D=0-----|-CR_D_CC--|----------------------------------------------------?----------------------------------------------------|\nCC_D_OP: \"lt\"\t\t\t\t\tis CR_D_CC=0 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"eq\"\t\t\t\t\tis CR_D_CC=2 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"gt\"\t\t\t\t\tis CR_D_CC=1 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"so\"\t\t\t\t\tis CR_D_CC=3 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"4*\"^CR_D^\"+lt\"\t\tis CR_D_CC=0 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"4*\"^CR_D^\"+eq\"\t\tis CR_D_CC=2 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"4*\"^CR_D^\"+gt\"\t\tis CR_D_CC=1 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; }\nCC_D_OP: \"4*\"^CR_D^\"+so\"\t\tis CR_D_CC=3 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; }\n\nRA_OR_ZERO:\tA \tis A\t\t\t{ export A; }\nRA_OR_ZERO: 0 is A=0\t\t{ export 0:$(REGISTER_SIZE); }\n\nRB_OR_ZERO:\tB \tis B\t\t\t{ export B; }\nRB_OR_ZERO: 0 is B=0\t\t{ export 0:$(REGISTER_SIZE); }\n\nRS_OR_ZERO:\tS \tis S\t\t\t{ export S; }\nRS_OR_ZERO: 0 is S=0\t\t{ export 0:$(REGISTER_SIZE); }\n\n@ifdef BIT_64\nMB: mbValue is MBH & MBL \t[ mbValue=(MBH<<5)|MBL; ]\t{ export *[const]:4 mbValue; }\nSH: shValue is SHH & SHL \t[ shValue=(SHH<<5)|SHL; ]\t{ export *[const]:4 shValue; }\n\nrotmask: mask is MBL & ME [mask = ((((ME-MBL)>>8) $and 1)*0xffffffffffffffff) $xor (0x7fffffff>>ME) $xor (0xffffffff>>MBL); ] { export *[const]:8 mask; }\n\nrotmask_SH: masksh, mbValue, shValue is MBL & MBH & SHL & SHH\n\t[ mbValue= (MBH<<5)|MBL;\n\t shValue= (SHH<<5)|SHL;\n\t masksh = ((((shValue-mbValue)>>8) $and 1)*0xffffffffffffffff) $xor ((0x7fffffffffffffff >> shValue) $xor (0xffffffffffffffff >> mbValue));\n\t]\n{\n\tlocal start:4 = mbValue;\n\tlocal stop:4 = 63-shValue;\n\tmask_tmp:8 = (zext(start > stop) * 0xffffffffffffffff) ^ (0x7fffffffffffffff>>stop) ^ (0xffffffffffffffff>>start);\n\texport *[const]:8 mask_tmp;\n}\n\nrotmask_Z: mask, mbValue is MBL & MBH [mbValue= (MBH<<5)|MBL; mask = ~(0xffffffffffffffff >> (mbValue+1)); ]\n{ mask_tmp:8 = ~(0xffffffffffffffff >> (mbValue+1)); export *[const]:8 mask_tmp; }\n\n@else\nrotmask: mask is MBL & ME [ mask = ((((ME-MBL)>>8) $and 1)*0xffffffff) $xor (0x7fffffff>>ME) $xor (0xffffffff>>MBL); ] { export *[const]:4 mask; }\n@endif\n\nDSIZE: \"w\"\t\tis L {} # L is a don't care bit in 32-bit languages although it should always be 0\n@ifdef BIT_64\t\t\t\t\t# L can only be 1 when in 64 bit language\nDSIZE: \"d\"\t\tis L=1 {}\n@endif\n\n@ifdef BIT_64\nREG_A: \t\t\tis L=0 & A {tmp:8 = sext(A:4); export tmp; }\nREG_A:\t\t\tis L=1 & A {export A; }\nREG_B: \t\t\tis L=0 & B {tmp:8 = sext(B:4); export tmp; }\nREG_B:\t\t\tis L=1 & B {export B; }\n@else # L is a don't care bit in 32-bit languages although it should always be 0\nREG_A:\t\t\tis A { export A; }\nREG_B:\t\t\tis B { export B; }\n@endif\n\n@ifdef BIT_64\nUREG_A: \t\t\tis L=0 & A {tmp:8 = zext(A:4); export tmp; }\nUREG_A:\t\t\tis L=1 & A {export A; }\nUREG_B: \t\t\tis L=0 & B {tmp:8 = zext(B:4); export tmp; }\nUREG_B:\t\t\tis L=1 & B {export B; }\n@else # L is a don't care bit in 32-bit languages although it should always be 0\nUREG_A:\t\t\tis A { export A; }\nUREG_B:\t\t\tis B { export B; }\n@endif\n\ndPlusRaOrZeroAddress: SIMM(RA_OR_ZERO)\tis SIMM & RA_OR_ZERO\t{ tmp:$(REGISTER_SIZE) = RA_OR_ZERO+SIMM; export tmp; }\ndPlusRaAddress: SIMM(A)\t\t\t\t\tis SIMM & A\t\t\t\t{tmp:$(REGISTER_SIZE) = A+SIMM; export tmp; }\n\ndUI16PlusRAOrZeroAddress: val^\"(\"^RA_OR_ZERO^\")\" is RA_OR_ZERO & UI_16_s8 [ val = UI_16_s8 << 3; ] { ea:$(REGISTER_SIZE) = RA_OR_ZERO + val; export ea; }\n\n@ifdef BIT_64\ndsPlusRaAddress: simm_ds(A)\tis SIMM_DS & A [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + A;export tmp;} \ndsPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO)\tis SIMM_DS & RA_OR_ZERO [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} \n@endif\n\n\nFPSCR_CRFS:\t\tis CRFS=0\t{tmp:1 = fp_fx<<3 | fp_fex<<2 | fp_vx<<1 | fp_ox; fp_fx=0; fp_ox=0; export tmp;}\nFPSCR_CRFS:\t\tis CRFS=1\t{tmp:1 = fp_ux<<3 | fp_zx<<2 | fp_xx<<1 | fp_vxsnan; fp_ux=0; fp_zx=0; fp_xx=0; fp_ux=0;export tmp;}\nFPSCR_CRFS:\t\tis CRFS=2\t{tmp:1 = fp_vxisi<<3 | fp_vxidi<<2 | fp_vxzdz<<1 | fp_vximz; fp_vxisi=0; fp_vxidi=0; fp_vxzdz=0; fp_vximz=0; export tmp;}\nFPSCR_CRFS:\t\tis CRFS=3\t{tmp:1 = fp_vxvc<<3 | fp_fr<<2 | fp_fi<<1 | fp_c; fp_vxvc=0; export tmp;}\nFPSCR_CRFS:\t\tis CRFS=4\t{tmp:1 = fp_cc0<<3 | fp_cc1<<2 | fp_cc2<<1 | fp_cc3; export tmp;}\nFPSCR_CRFS:\t\tis CRFS=5\t{tmp:1 = fp_vxsoft<<2 | fp_vxsqrt<<1 | fp_vxcvi; fp_vxsoft=0; fp_vxsqrt=0; fp_vxcvi=0; export tmp;}\nFPSCR_CRFS:\t\tis CRFS=6\t{tmp:1 = fp_ve<<3 | fp_oe <<2 | fp_ue<<1 | fp_ze; export tmp;}\nFPSCR_CRFS:\t\tis CRFS=7\t{tmp:1 = fp_xe<<3 | fp_ni<<2 | fp_rn0<<1 | fp_rn1; export tmp;}\n\nCRM_CR:\tcr7\t\tis CRM=1 & cr7\t{tmp:4 = zext(cr7);export tmp;}\nCRM_CR:\tcr6\t\tis CRM=2 & cr6\t{tmp:4 = zext(cr6) << 4;export tmp;}\nCRM_CR:\tcr5\t\tis CRM=4 & cr5\t{tmp:4 = zext(cr5) << 8;export tmp;}\nCRM_CR:\tcr4\t\tis CRM=8 & cr4\t{tmp:4 = zext(cr4) << 12;export tmp;}\nCRM_CR:\tcr3\t\tis CRM=16 & cr3\t{tmp:4 = zext(cr3) << 16;export tmp;}\nCRM_CR:\tcr2\t\tis CRM=32 & cr2\t{tmp:4 = zext(cr2) << 20;export tmp;}\nCRM_CR:\tcr1\t\tis CRM=64 & cr1\t{tmp:4 = zext(cr1) << 24;export tmp;}\nCRM_CR:\tcr0\t\tis CRM=128 & cr0\t{tmp:4 = zext(cr0) << 28;export tmp;}\n\n\n################################################################\n# Instructions\n################################################################\n\n\n@include \"ppc_instructions.sinc\"\n@include \"ppc_embedded.sinc\"\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_embedded.sinc", "content": "# these are identified as part of the PowerPC Embedded Architecture\n\n#dcba 0,r0\t\t0x7c 00 05 ec\n:dcba RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=758 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockAllocate(ea);\n}\n\n#dcbf 0,r0\t\t0x7c 00 00 ac\n:dcbf RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=86 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockFlush(ea);\n}\n\n#dcbi 0,r0\t\t0x7c 00 03 ac\n:dcbi RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=470 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockInvalidate(ea);\n}\n\n#dcbst 0,r0\t\t0x7c 00 00 6c\n:dcbst RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=54 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockStore(ea);\n}\n\n#dcbt 0,r0\t\t0x7c 00 02 2c\n:dcbt RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=278 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockTouch(ea);\n}\n\n#dcbtst 0,r0\t\t0x7c 00 01 ec\n:dcbtst RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=246 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockTouchForStore(ea);\n}\n\n#dcbz 0,r0\t\t0x7c 00 07 ec\n:dcbz RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=1014 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockClearToZero(ea);\n}\n\n#dcbzl 0,r0\t\t0x7c 20 07 ec\n:dcbzl RA_OR_ZERO,B\tis OP=31 & BITS_21_25=1 & B & XOP_1_10=1014 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockClearToZero(ea);\n}\n\ndefine pcodeop memoryBarrier;\n#mbar 0 7c 00 06 ac\n:mbar MO is OP=31 & MO & XOP_1_10=854\n{\n\tmemoryBarrier(MO:1);\n}\n\n#icbi r0,r0\t\t0x7c 00 07 ac\n:icbi RA_OR_ZERO,B\t\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tinstructionCacheBlockInvalidate(ea);\t\n}\n\n#icbt 0,r0\t\t0x7c 00 02 0c\n:icbt BITS_21_24,RA_OR_ZERO,B\t\tis OP=31 & BIT_25=0 & BITS_21_24 & RA_OR_ZERO & B & XOP_1_10=22 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tinstructionCacheBlockTouch(ea);\t\n}\n\n#isync\t\t0x4c 00 01 2c\n:isync\t\tis $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=150 & BIT_0=0\n{\n\tinstructionSynchronize();\n}\n\n#mfdcr r0,DCRN\t0x7c 00 02 86\n:mfdcr D, DCRN\t\tis OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=0\n{\n\tD = DCRN;\n}\n\n#mfmsr r0\t0x7c 00 00 a6\n:mfmsr D\t\tis OP=31 & D & BITS_11_20=0 & XOP_1_10=83 & BIT_0=0\n{\n\tD = MSR;\n}\n\n#mfspr r0\t0x7c 00 02 a6\n:mfspr D,SPRVAL\t\tis OP=31 & D & SPRVAL & XOP_1_10=339 & BIT_0=0\n{\n\tD = SPRVAL;\n}\n\n#mftb r0,TBLr\t0x7c 0c 42 e6\n:mftb D,TBLr\t\tis $(NOTVLE) & OP=31 & D & TBR=392 & TBLr & XOP_1_10=371 & BIT_0=0\n{\n\tD = TBLr;\n}\n#mftb r0,TBUr\t0x7c 0d 42 e6\n:mftb D,TBUr\t\tis $(NOTVLE) & OP=31 & D & TBR=424 & TBUr & XOP_1_10=371 & BIT_0=0\n{\n\tD = TBUr;\n}\n\n#mtdcr DCRN,r0\t0x7c 00 03 86\n:mtdcr DCRN, D\t\tis OP=31 & D & DCRN & XOP_1_10=451 & BIT_0=0\n{\n\tDCRN = D;\n}\n\n# mtmsr varies from processor to processor. This version is consistent with PowerISA v2.07B\n#mtmsr r0,0\t\t0x7c 00 01 24\n:mtmsr S,0\t\tis OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0\n{\n\n\tbit59:$(REGISTER_SIZE) = (S >> 4) & 1;\t#bit 59\n\tbit58:$(REGISTER_SIZE) = (S >> 5) & 1;\t#bit 58\n\tbit49:$(REGISTER_SIZE) = (S >> 14) & 1;\t#bit 49\n\tbit48:$(REGISTER_SIZE) = (S >> 15) & 1;\t#bit 48\n\n\tlocal mask:$(REGISTER_SIZE) = 0xffff6fcf; # preserves bits 32:47 49:50 52:57 60:62\n\tlocal tmp:$(REGISTER_SIZE) = S & mask; # 1111 1111 1111 1111 0110 1111 1100 1111\n\n\ttmp = tmp | ((bit48 | bit49) << 15); # MSR 48 <- (RS) 48 | (RS) 49\n\ttmp = tmp | ((bit58 | bit49) << 5); # MSR 58 <- (RS) 58 | (RS) 49\n\ttmp = tmp | ((bit59 | bit49) << 4); # MSR 59 <- (RS) 59 | (RS) 49\n\tMSR = (MSR & ~mask) | tmp;\n}\n\n#mtmsr r0,1\t\t0x7c 01 01 24\n:mtmsr S,1\t\tis OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0 \n{\n\tmask:$(REGISTER_SIZE) = 0x8002; #preserves bits 48 and 62\n\tMSR = (MSR & ~mask) | (S & mask);\n}\n\n\n#mtspr spr000,r0\t0x7c 00 02 a6\n:mtspr SPRVAL,S\t\tis OP=31 & SPRVAL & S & XOP_1_10=467 & BIT_0=0\n{\n\tSPRVAL = S;\n}\n\n:mtspr SPRVAL,S\t\tis OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0\n [ linkreg=1; globalset(inst_next,linkreg); ]\n{\n\tSPRVAL = S;\n}\n\n:mtspr SPRVAL,S\t\tis linkreg=1 & OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0\n [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tSPRVAL = S;\n}\n\n:rfci\t\t\t\tis $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=51 & BIT_0=0\n{\n\tMSR = returnFromCriticalInterrupt(MSR, CSRR1);\n\tlocal ra = CSRR0;\n\treturn[ra];\n\n}\n\n#rfi\t0x4c 00 00 64 \n:rfi\t\tis $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=50 & BIT_0=0\t\n{ \n\tMSR = returnFromInterrupt(MSR, SRR1);\n\tlocal ra = SRR0;\n\treturn[ra];\n}\n\n\n#tlbre 0x7c 00 07 64\n:tlbre\tis OP=31 & XOP_1_10=946\n{\n\tTLBRead();\n}\n\n#tlbsx r0,r0,r0\t\t0x7c 00 07 24\n:tlbsx D,RA_OR_ZERO,B\tis OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tD = TLBSearchIndexed(D,ea);\n}\n\n#tlbsx. r0,r0,r0\t0x7c 00 07 25\n:tlbsx. D,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=1\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tD = TLBSearchIndexed(D,ea);\n\tcr0flags(D);\n}\n\n#tlbwe 0x7c 00 07 a4\n:tlbwe D,A,B_BITS is OP=31 & D & A & B_BITS & XOP_1_10=978\n{\n D = TLBWrite(D,A,B_BITS:1);\n}\n\n\n#wrtee r0 0x7c 00 01 06\n:wrtee S\tis OP=31 & S & XOP_1_10=131\n{\n\tWriteExternalEnable(S);\n}\n\n#wrteei 0 0x7c 00 01 46\n:wrteei BIT_15\tis OP=31 & BIT_15 & XOP_1_10=163\n{\n\tWriteExternalEnableImmediate(BIT_15:1);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc", "content": "#===========================================================\n# ADD\n#===========================================================\n\n#add r1,r2,r3 0x7c 22 1a 14\n:add D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=266 & Rc=0\n{\n\t D = A + B;\n}\n\n#add. r1,r2,r3 0x7c 22 1a 15\n:add. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=266 & Rc=1\t\n{ \t\n\tD = A + B;\n\tcr0flags(D);\n}\n\n#addo r1,r2,r3 0x7c 22 1e 14\n:addo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=266 & Rc=0\n{\n\taddOverflow(A,B);\n\tD = A + B;\n}\n\n#addo. r1,r2,r3 0x7c 22 1e 15\n:addo. D,A,B\tis OP=31 & D & A & B & OE=1 & XOP_1_9=266 & Rc=1\n{\n\taddOverflow(A,B);\n\tD = A + B;\t \n\tcr0flags(D);\n}\n\n#addc r1,r2,r3 0x7c 22 18 14\n:addc D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=10 & Rc=0\n{\t\n\txer_ca = carry(A,B);\n\tD = A + B;\n}\n\n#addc. r1,r2,r3 0x7c 22 18 15\n:addc. D,A,B\tis OP=31 & D & A & B & OE=0 & XOP_1_9=10 & Rc=1\t\n{ \t\n\txer_ca = carry(A,B);\n\tD = A + B;\n\tcr0flags(D);\n}\n\n#addco r1,r2,r3 0x7c 22 1c 14\n:addco D,A,B\tis OP=31 & D & A & B & OE=1 & XOP_1_9=10 & Rc=0\n{ \n\txer_ca = carry(A,B); \t\n\taddOverflow( A, B );\n\tD = A + B;\n}\n\n#addco. r1,r2,r3 0x7c 22 1c 15\n:addco. D,A,B\tis OP=31 & D & A & B & OE=1 & XOP_1_9=10 & Rc=1\n{ \t\n\txer_ca = carry(A,B);\n\taddOverflow( A, B );\n\tD = A + B;\t \n\tcr0flags(D);\n}\n\n#adde r1,r2,r3 0x7c 22 19 14\n:adde D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=138 & Rc=0\n{\t\n\tzextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n\taddExtendedCarry(A,B);\n\tD=A + B + zextCarry;\n}\n\n#adde. r1,r2,r3 0x7c 22 19 15\n:adde. D,A,B\tis OP=31 & D & A & B & OE=0 & XOP_1_9=138 & Rc=1\t\n{ \t\n\tzextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n\taddExtendedCarry(A,B);\n\tD=A + B + zextCarry;\n\tcr0flags(D);\n}\n\n#addeo r1,r2,r3 0x7c 22 1d 14\n:addeo D,A,B\tis OP=31 & D & A & B & OE=1 & XOP_1_9=138 & Rc=0\n{ \n\tzextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n \taddExtendedOverflow(A,B);\n\taddExtendedCarry(A,B);\n\tD=A + B + zextCarry;\n}\n\n#addeo. r1,r2,r3 0x7c 22 1d 15\n:addeo. D,A,B\tis OP=31 & D & A & B & OE=1 & XOP_1_9=138 & Rc=1\n{ \t\n\tzextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n \taddExtendedOverflow(A,B);\n\taddExtendedCarry(A,B);\n\tD=A + B + zextCarry;\n\tcr0flags(D);\n}\n\n#addi r0,0x7fff\t\t0x38 00 7f ff\n#addi r0,1 0x38 01 00 01\n:addi D,A,SIMM \t\tis $(NOTVLE) & OP=14 & D & A & SIMM_SIGN=0 & SIMM\n{\n\tD = A + SIMM;\n}\n\n#li r0,1 0x38 00 00 01 \t# addi simplified mnemonic\n:li D,SIMM\t\t\tis $(NOTVLE) & OP=14 & D & A=0 & SIMM_SIGN=1 & SIMM\n{\n\tD = SIMM;\n}\n\n#li r0,-0x1 0x38 00 FF FF\t\t\t# addi simplified mnemonic\n:li D,SIMM\t\t\tis $(NOTVLE) & OP=14 & D & A=0 & SIMM_SIGN=0 & SIMM\n{\n\tD = SIMM;\n}\n\n#subi r0,r1,1 0x38 01 FF FF \t# addi simplified mnemonic\n:subi D,A,tmp\t\tis $(NOTVLE) & OP=14 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ]\n{\n\tD = A + SIMM;\n}\n\n#addic r0,r0,2 0x30 00 00 02\n:addic D,A,SIMM\t\tis $(NOTVLE) & OP=12 & D & A & SIMM_SIGN=0 & SIMM\n{\n\txer_ca=carry(A,SIMM);\n\tD = A + SIMM;\n}\n\n#subic r0,r0,2 0x30 00 FF FE\t# addi simplified mnemonic\n:subic D,A,tmp\t\tis $(NOTVLE) & OP=12 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ]\n{\n\txer_ca=carry(A,SIMM);\n\tD = A + SIMM;\n}\n\n#addic. r0,r0,5 0x34 00 00 05\n:addic. D,A,SIMM\tis $(NOTVLE) & OP=13 & D & A & SIMM_SIGN=0 & SIMM\n{\n\txer_ca = carry(A,SIMM);\n\tD = A + SIMM;\n\tcr0flags( D );\n}\n\n#subic. r0,r0,1 0x34 00 FF FF\t# addic. simplified mnemonic\n:subic. D,A,tmp\t\tis $(NOTVLE) & OP=13 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ]\n{\n\txer_ca=carry(A,SIMM);\n\tD = A + SIMM;\n\tcr0flags( D );\n}\n\n#addis r0,r1,1 0x3c 01 00 01 \n:addis D,A,SIMM\t\tis $(NOTVLE) & OP=15 & D & A & SIMM_SIGN=0 & SIMM \n{\n\tD = A + (SIMM:$(REGISTER_SIZE) << 16);\n}\n\n#lis r0,1 0x3c 00 00 01 \t# addis simplified mnemonic\n:lis D,SIMM\t\t\tis $(NOTVLE) & OP=15 & D & A=0 & SIMM_SIGN=1 & SIMM\n{\n\tD = SIMM:$(REGISTER_SIZE) << 16;\n}\n\n#lis r0,-1 0x3c 00 FF FF\t\t\t# addis simplified mnemonic\n:lis D,SIMM\t\t\tis $(NOTVLE) & OP=15 & D & A=0 & SIMM_SIGN=0 & SIMM\n{\n\tD = SIMM:$(REGISTER_SIZE) << 16;\n}\n\n#subis r0,r1,1 0x3c 01 FF FF \t# addis simplified mnemonic\n:subis D,A,tmp\t\tis $(NOTVLE) & OP=15 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ]\n{\n\tD = A + (SIMM:$(REGISTER_SIZE) << 16);\n}\n\n#addme r0,r0 0x7c 00 01 D4\n:addme D,A\t\t\tis OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=234 & Rc=0\n{\n\tlocal zextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n\tlocal BVal:$(REGISTER_SIZE) = ~(0);\n\taddExtendedCarry(A,BVal);\n\tD=A + BVal + zextCarry;\n}\n\n#addme. r0,r0 0x7c 00 01 D5\n:addme. D,A\t\t\tis OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=234 & Rc=1\n{\n\tlocal zextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n\tlocal BVal:$(REGISTER_SIZE) = ~(0);\n\taddExtendedCarry(A,BVal);\n\tD=A + BVal + zextCarry;\n\tcr0flags(D);\n}\n\n#addmeo r0,r0 0x7C 00 05 D4\n:addmeo D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=234 & Rc=0\n{\n\tlocal zextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n\tlocal BVal:$(REGISTER_SIZE) = ~(0);\n\taddExtendedOverflow(A,BVal);\n\taddExtendedCarry(A,BVal);\n\tD=A + BVal + zextCarry;\n}\n\n#addmeo. r0,r0 0x7C 00 05 D5\n:addmeo. D,A \tis OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=234 & Rc=1\n{\n\tlocal zextCarry:$(REGISTER_SIZE) = zext(xer_ca);\n\tlocal BVal:$(REGISTER_SIZE) = ~(0);\n\taddExtendedOverflow(A,BVal);\n\taddExtendedCarry(A,BVal);\n\tD=A + BVal + zextCarry;\n\tcr0flags(D);\n}\n\n#addze r0,r0 0x7C 00 01 94\n:addze D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=202 & Rc=0\n{\n\tzextedCarry:$(REGISTER_SIZE) = zext( xer_ca );\n\txer_ca = carry(A,zextedCarry);\n\tD = A + zextedCarry;\n} \n\n#addze. r0,r0 0x7C 00 01 95\n:addze. D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=202 & Rc=1\n{\n\tzextedCarry:$(REGISTER_SIZE) = zext( xer_ca );\n\txer_ca=carry(A,zextedCarry);\n\tD = A + zextedCarry;\n\tcr0flags( D );\n}\n\n#addzeo r0,r0 0x7C 00 05 94\n:addzeo D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=202 & Rc=0\n{\n\tzextedCarry:$(REGISTER_SIZE) = zext( xer_ca );\n\txer_ca=carry(A,zextedCarry);\n\taddOverflow(A,zextedCarry);\n\tD = A + zextedCarry;\n} \n\n#addzeo. r0,r0 0x7C 00 05 95\n:addzeo. D,A\tis OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=202 & Rc=1\n{\n\tzextedCarry:$(REGISTER_SIZE) = zext( xer_ca );\n\txer_ca=carry(A,zextedCarry);\n\taddOverflow(A,zextedCarry);\n\tD = A + zextedCarry;\n\tcr0flags( D );\n}\n\n#===========================================================\n# AND\n#===========================================================\n\n#and r0,r0,r0 0x7C 00 00 38\n:and A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=28 & Rc=0\n{\n\tA = S & B;\n}\n\n#and. r0,r0,r0 0x7C 00 00 39\n:and. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=28 & Rc=1\n{\n\tA = S & B;\n\tcr0flags( A );\n}\n\n#andc r0,r0,r0 0x7C 00 00 78\n:andc A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=60 & Rc=0\n{\n\tA = S & ~B;\n}\n\n#andc. r0,r0,r0 0x7C 00 00 79\n:andc. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=60 & Rc=1\n{\n\tA = S & ~B;\n\tcr0flags( A );\n}\n\n#andi. r0,r0,0xffff 0x70 00 ff ff\n:andi. A,S,UIMM\t\tis $(NOTVLE) & OP=28 & S & A & UIMM\n{\n\tA = S & UIMM:$(REGISTER_SIZE);\n\tcr0flags( A );\n}\n\n#andis. r0,r0,1 0x74 00 00 01\n:andis. A,S,UIMM\tis $(NOTVLE) & OP=29 & A & S & UIMM \n{\n\tA = S & (UIMM:$(REGISTER_SIZE) << 16);\n\tcr0flags( A );\n}\n\n#===========================================================\n# Branch (op=18)\n#===========================================================\n\n#b 1008 0x48 00 00 08 (assuming a starting address of 1000)\n#ba LAB_00000158\t\t0x48 00 01 5a\n:b^REL_ABS addressLI\t\tis $(NOTVLE) & OP=18 & REL_ABS & addressLI & LK=0\n{\n\tgoto addressLI;\n}\n\n:b^REL_ABS addressLI\t\tis linkreg=1 & OP=18 & REL_ABS & addressLI & LK=0\n [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n # don't do this anymore, detect another way\n\t# call addressLI;\n\t# return [LR];\n\tgoto addressLI;\n}\n\n#bl 0x48 00 00 09\n#bla 0x48 00 10 0f\n:bl^REL_ABS addressLI\tis $(NOTVLE) & OP=18 & REL_ABS & addressLI & LK=1\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tr2Save = r2; # Save r2 (needed for branch to ppc64 call stub)\n\tLR = inst_next;\n\tcall addressLI;\n}\n\n# special case when branch is to fall-through instruction, just loading the link register\n#bl 0x48 00 00 05\t\n:bl addressLI\tis $(NOTVLE) & OP=18 & REL_ABS & AA=0 & addressLI & LK=1 & LI=1\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tgoto addressLI;\n}\n\n#===========================================================\n# Branch Conditional (op=16)\n#===========================================================\n\n#b sameAddr\t\t0x42 80 00 00\n#ba LAB_0000\t\t0x42 80 00 02\n:b^REL_ABS addressBD \t\tis $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & LK=0\n{\n\tgoto addressBD;\n}\n\n:b^REL_ABS addressBD \t\tis linkreg=1 & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & LK=0\n [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n # don't do this anymore, detect another way\n\t# call addressBD;\n\t# return [LR];\n\tgoto addressBD;\n}\n\n#bl LAB_0000\t\t0x42 80 00 01\n#bla LAB_0000\t\t0x42 80 00 03\n:bl^REL_ABS addressBD \t\tis $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & LK=1\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tcall addressBD;\n}\n\n# special case when branch is to fall-through instruction, just loading the link register\n#bl (Load LR) \n:bl addressBD \t\tis $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & BD=1 & LK=1\n{\n\tLR = inst_next;\n\tgoto addressBD;\n}\n\n\n\n#blt LAB_0000\t\t0x41 80 00 00\n:b^CC^REL_ABS addressBD \tis $(NOTVLE) & OP=16 & CC & addressBD & BO_0=0 & BO_2=1 & BI_CR= 0 &\n\t\t\t\t\t\t\t\t REL_ABS & LK=0\n\t\t\t\t\t\t\t\t [ linkreg=0; globalset(inst_start,linkreg); ] # affects both flows, but not at this instruction\n{\n\tif (CC) goto addressBD;\n}\n## do a special linkreg setting only if linkreg is set, since this happens all over the code\n:b^CC^REL_ABS addressBD \tis linkreg=1 & OP=16 & CC & addressBD & BO_0=0 & BO_2=1 & BI_CR= 0 &\n\t\t\t\t\t\t\t\t REL_ABS & LK=0\n\t\t\t\t\t\t\t\t [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (CC) goto addressBD;\n}\n\n#bltl LAB_0000\t\t0x41 80 00 01\n:b^CC^\"l\"^REL_ABS addressBD \tis $(NOTVLE) & OP=16 & CC & addressBD & BO_0=0 & BO_2=1 & BI_CR= 0 &\n\t\t\t\t\t\t\t\t REL_ABS & LK=1\n\t\t\t\t\t\t\t\t [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall addressBD;\n}\n\n#bne cr2,LAB_xxxx\t\t0x40 8a 00 00\n:b^CC^REL_ABS BI_CR,addressBD \t\tis $(NOTVLE) & OP=16 & CC & BI_CR & addressBD & BO_0=0 & BO_2=1 & \n\t\t\t\t\t\t\t\t\t\tREL_ABS & LK=0\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (CC) goto addressBD;\n}\n\n#bnel cr2,LAB_xxxx\t\t0x40 8a 00 01\n:b^CC^\"l\"^REL_ABS BI_CR,addressBD \t\tis $(NOTVLE) & OP=16 & CC & BI_CR & addressBD & BO_0=0 & BO_2=1 & \n\t\t\t\t\t\t\t\t\t\tREL_ABS & LK=1\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall addressBD;\n}\n\n#bdnz LAB_0000\t\t0x42 00 00 00 \n:bd^CTR_DEC^REL_ABS addressBD \t\tis $(NOTVLE) & OP=16 & CTR_DEC & REL_ABS & addressBD & BO_0=1 & BO_2=0 & LK=0\n{\n\tif (CTR_DEC) goto addressBD;\n}\n\n#bdnzl FUN_0xxx\t\t0x42 00 00 01\n#bdzla FUN_0000\t\t0x42 40 00 03\n:bd^CTR_DEC^\"l\"^REL_ABS addressBD \t\tis $(NOTVLE) & OP=16 & CTR_DEC & REL_ABS & addressBD & BO_0=1 & BO_2=0 & LK=1\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CTR_DEC) goto inst_next;\n\tcall addressBD;\n}\n\n#bdnzf lt,LAB_0000\t\t\t\t0x40 00 00 00\n#bdnzf 4*cr2+eq,LAB_0000\t\t0x40 0a 00 00\n:bd^CTR_DEC^CC_TF^REL_ABS CC_OP,addressBD \t\tis $(NOTVLE) & OP=16 & CC_TF & REL_ABS & CTR_DEC & CC_OP & addressBD & BO_0=0 & BO_2=0 & LK=0\n{\n\tif (CTR_DEC && (CC_OP == CC_TF)) goto addressBD;\n}\n\n#bdzfl lt,FUN_0000\t\t\t\t0x40 00 00 01\n#bdnzfl 4*cr2+eq,FUN_0000\t\t0x40 0a 00 01\n:bd^CTR_DEC^CC_TF^\"l\"^REL_ABS CC_OP,addressBD \t\tis $(NOTVLE) & OP=16 & CC_TF & CTR_DEC & REL_ABS & CC_OP & addressBD & BO_0=0 & BO_2=0 & LK=1\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next;\n\tcall addressBD;\n}\n\n\n#===========================================================\n# Branch Conditional CTR(op=19, xop=528)\n#===========================================================\n\n\n#bctr\t\t0x4E 80 04 20\n:bctr \t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=528\n{\n\tgoto [CTR];\n}\n\n:bctr \t\tis $(NOTVLE) & linkreg=1 & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=528\n [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n # don't do this anymore, detect another way\n\t# call [CTR];\n\t# return [LR];\n\tgoto [CTR];\n}\n\n:bctr BH \t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH & XOP_1_10=528\n{\n\tgoto [CTR];\n}\n\n#bctrl\t\t0x4e 80 04 21\n:bctrl\t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH=0 & XOP_1_10=528\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tcall [CTR];\n}\n:bctrl BH\t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH & XOP_1_10=528\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tcall [CTR];\n}\n\n#bgectr\t\t0x4c 80 04 20\n:b^CC^\"ctr\" \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528\n{\n\tif (!CC) goto inst_next;\n\tgoto [CTR];\n}\n:b^CC^\"ctr\" BH \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528\n{\n\tif (!CC) goto inst_next;\n\tgoto [CTR];\n}\n\n#bgectrl\t\t0x4c 80 04 21\n:b^CC^\"ctrl\" \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [CTR];\n}\n:b^CC^\"ctrl\" BH \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [CTR];\n}\n\n#bgectr cr3\t\t0x4c 8c 04 20\n:b^CC^\"ctr\" BI_CR \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528\n{\n\tif (!CC) goto inst_next;\n\tgoto [CTR];\n}\n\n#bnectr cr2,#0x3 0x4c 8c 1c 20\n:b^CC^\"ctr\" BI_CR,BH \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=528\n{\n\tif (!CC) goto inst_next;\n\tgoto [CTR];\n}\n\n#bgectrl cr2,LAB_xxxx\t\t0x4c 8c 04 21\n:b^CC^\"ctrl\" BI_CR \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [CTR];\n}\n\n#bnectr cr2,#0x3 0x4c 8c 1c 21\n:b^CC^\"ctrl\" BI_CR,BH \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=1 & BITS_13_15=0 & XOP_1_10=528\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [CTR];\n}\n\n#===========================================================\n# Branch Conditional to Link Register (op=19, XOP=16)\n#===========================================================\n\n#bclr\t\t0x4E 80 00 20\n:blr \t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=16\n{\n\treturn [LR];\n}\n:blr BH \t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH & XOP_1_10=16\n{\n\tgoto [LR];\n}\n\n#blrl\t\t0x4e 80 00 21\n:blrl\t\t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tcall [tmp];\n}\n:blrl BH\t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tcall [tmp];\n}\n\n#bgelr\t\t0x4c 80 00 20\n:b^CC^\"lr\" \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next;\n\treturn [LR];\n}\n:b^CC^\"lr\" BH \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next;\n\tgoto [LR];\n}\n\n#bgelrl\t\t0x4c 80 00 21\n:b^CC^\"lrl\" \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [tmp];\n}\n:b^CC^\"lrl\" BH \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH & BH_BITS!=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [tmp];\n}\n\n#bgelr cr2\t\t0x4c 88 00 20\n:b^CC^\"lr\" BI_CR \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next;\n\treturn [LR];\n}\n\n#bnelr cr2,#0x3 0x4c 8c 18 20\n:b^CC^\"lr\" BI_CR,BH \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next;\n\tgoto [LR];\n}\n\n#bgelrl cr3\t\t0x4c 8c 00 21\n:b^CC^\"lrl\" BI_CR \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [tmp];\n}\n\n#bnelr cr2,#0x3 0x4c 8c 18 21\n:b^CC^\"lrl\" BI_CR,BH \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!CC) goto inst_next;\n\tcall [tmp];\n}\n\n######\n\n#bdnzlr\t\t0x4e 00 00 20 \n:bd^CTR_DEC^\"lr\" \t\tis $(NOTVLE) & OP=19 & BH=0 & CTR_DEC & BO_0=1 & BO_2=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CTR_DEC) goto inst_next;\n\tgoto [LR];\n}\n:bd^CTR_DEC^\"lr\" BH \t\tis $(NOTVLE) & OP=19 & BH & CTR_DEC & BO_0=1 & BO_2=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CTR_DEC) goto inst_next;\n\tgoto [LR];\n}\n\n#bdnzlrl\t\t0x4e 00 00 21\n:bd^CTR_DEC^\"lrl\" \t\tis $(NOTVLE) & OP=19 & CTR_DEC & BH=0 & BO_0=1 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!CTR_DEC) goto inst_next;\n\tcall [tmp];\n}\n:bd^CTR_DEC^\"lrl\" BH \t\tis $(NOTVLE) & OP=19 & CTR_DEC & BH & BO_0=1 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!CTR_DEC) goto inst_next;\n\tcall [tmp];\n}\n\n#bdnzflr lt\t\t\t\t0x4c 00 00 20\n#bdnzflr 4*cr2+eq\t\t0x4c 0a 00 20\n:bd^CTR_DEC^CC_TF^\"lr\" CC_OP \t\tis $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BO_0=0 & BO_2=0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 \n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next;\n\tgoto [LR];\n}\n\n#bdnzflr ge\t\t\t\t0x4c 00 18 20\n#bdnzflr 4*cr2+eq\t\t0x4c 0a 18 20\n:bd^CTR_DEC^CC_TF^\"lr\" CC_OP,BH \t\tis $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BO_0=0 & BO_2=0 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=16 \n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next;\n\tgoto [LR];\n}\n\n#bdzflrl lt\t\t\t\t0x4c 00 00 21\n#bdnzflrl 4*cr2+eq\t\t0x4c 0a 00 21\n:bd^CTR_DEC^CC_TF^\"lrl\" CC_OP \t\tis $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BH=0 & BO_0=0 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next;\n\tcall [tmp];\n}\n\n#bdzflrl lt\t\t\t\t0x4c 00 18 21\n#bdnzflrl 4*cr2+eq\t\t0x4c 0a 18 21\n:bd^CTR_DEC^CC_TF^\"lrl\" CC_OP,BH \t\tis $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BH & BO_0=0 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\ttmp:$(REGISTER_SIZE) = LR;\n\tLR = inst_next;\n\tif (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next;\n\tcall [tmp];\n}\n\n\n#===========================================================\n# CMP\n#===========================================================\n\n#cmpw r0,r1\t\t0x7c 00 08 00\n#cmpd r0,r1\t\t0x7c 20 08 00 (64 bit mode)\n:cmp^DSIZE \tA,B\t\t\tis OP=31 & CRFD=0 & BIT_22=0 & DSIZE & A & B & REG_A & REG_B & XOP_1_10=0 & BIT_0=0 \n{\n\ttmpA:$(REGISTER_SIZE) = REG_A;\n\ttmpB:$(REGISTER_SIZE) = REG_B;\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n\t\n}\n\n#cmpw cr2,r0,r1 0x7d 00 08 00\n#cmpd cr2,r0,r1 0x7d 20 08 00 (64 bit mode)\n:cmp^DSIZE \tCRFD,A,B\tis OP=31 & CRFD & BIT_22=0 & DSIZE & A & B & REG_A & REG_B & XOP_1_10=0 & BIT_0=0 \n{\n\ttmpA:$(REGISTER_SIZE) = REG_A;\n\ttmpB:$(REGISTER_SIZE) = REG_B;\n\tCRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n\n###############################\n#cmpwi r0,0x00\t\t0x2c 00 00 00\n#cmpdi r0,0x00\t\t0x2c 20 00 00 (64 bit mode)\n:cmp^DSIZE^\"i\" \tA,SIMM\t\t\tis $(NOTVLE) & OP=11 & CRFD=0 & BIT_22=0 & DSIZE & A & REG_A & SIMM \n{\n\ttmpA:$(REGISTER_SIZE) = REG_A;\n\ttmpB:$(REGISTER_SIZE) = SIMM;\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n\t\n}\n\n#cmpwi cr2,r0,0x00 0x2d 00 00 00\n#cmpwi cr2,r0,0x00 0x2d 20 00 00 (64 bit mode)\n:cmp^DSIZE^\"i\" \tCRFD,A,SIMM\tis $(NOTVLE) & OP=11 & CRFD & BIT_22=0 & DSIZE & A & B & REG_A & SIMM \n{\n\ttmpA:$(REGISTER_SIZE) = REG_A;\n\ttmpB:$(REGISTER_SIZE) = SIMM;\n\tCRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n\n############################\n#cmplw r0,r1\t\t0x7c 00 08 40\n#cmpld r0,r1\t\t0x7c 20 08 40 (64 bit mode)\n:cmpl^DSIZE \tA,B\t\t\tis OP=31 & CRFD=0 & BIT_22=0 & DSIZE & A & B & UREG_A & UREG_B & XOP_1_10=32 & BIT_0=0 \n{\n\ttmpA:$(REGISTER_SIZE) = UREG_A;\n\ttmpB:$(REGISTER_SIZE) = UREG_B;\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n\t\n}\n\n#cmplw cr2,r0,r1 0x7d 00 08 40\n#cmplw cr2,r0,r1 0x7d 20 08 40 (64 bit mode)\n:cmpl^DSIZE \tCRFD,A,B\tis OP=31 & CRFD & BIT_22=0 & DSIZE & A & B & UREG_A & UREG_B & XOP_1_10=32 & BIT_0=0 \n{\n\ttmpA:$(REGISTER_SIZE) = UREG_A;\n\ttmpB:$(REGISTER_SIZE) = UREG_B;\n\tCRFD = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n\n###############################\n#cmplwi r0,0x00\t\t0x28 00 00 00\n#cmpldi r0,0x00\t\t0x28 20 00 00 (64 bit mode)\n:cmpl^DSIZE^\"i\" \tA,UIMM\t\t\tis $(NOTVLE) & OP=10 & CRFD=0 & BIT_22=0 & DSIZE & A & UREG_A & UIMM \n{\n\ttmpA:$(REGISTER_SIZE) = UREG_A;\n\ttmpB:$(REGISTER_SIZE) = UIMM;\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n\t\n}\n\n#cmplwi cr2,r0,0x00 0x29 00 00 00\n#cmplwi cr2,r0,0x00 0x29 20 00 00 (64 bit mode)\n:cmpl^DSIZE^\"i\" \tCRFD,A,UIMM\tis $(NOTVLE) & OP=10 & CRFD & BIT_22=0 & DSIZE & A & B & UREG_A & UIMM \n{\n\ttmpA:$(REGISTER_SIZE) = UREG_A;\n\ttmpB:$(REGISTER_SIZE) = UIMM;\n\tCRFD = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n#===========================================================\n# CNTLZx\n#===========================================================\n\n@ifdef BIT_64\n#cntlzd r0,r0 \t\t0x7c 00 00 74\n:cntlzd A,S\t\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=58 & Rc=0\n{\n\tA = lzcount(S);\n}\n\n#cntlzd. r0,r0\t\t0x7c 00 00 75\n:cntlzd. A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=58 & Rc=1\n{\n\tA = lzcount(S);\n\tcr0flags(A);\n}\n@endif\n\n#cntlzw r0,r0 \t\t0x7c 00 00 34\n:cntlzw A,S\t\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=26 & Rc=0\n{\n\tA = lzcount(S:4);\n}\n\n#cntlzw. r0,r0\t\t0x7c 00 00 35\n:cntlzw. A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=26 & Rc=1\n{\n\tA = lzcount(S:4);\n\tcr0flags(A);\n}\n#===========================================================\n# CRxxx\n#===========================================================\n#crand\tlt,lt,lt\t\t\t\t\t\t0x4c 00 02 02\n#crand\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t0x4c 89 72 02\n:crand\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=257 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,CC_OP & CC_B_OP);\n}\n\n#crandc lt,lt,lt\t\t\t\t\t\t0x4c 00 01 02\n#crandc\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t0x4c 89 71 02\n:crandc\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0\n{\n\ttmp1:1 = !CC_B_OP;\n\tsetCrBit(CR_D,CR_D_CC,CC_OP & tmp1);\n}\n\n#creqv lt,lt,lt\t\t\t\t\t\t\t0x4c 00 02 42\n#creqv\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t0x4c 89 72 42\n:creqv\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=289 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,CC_B_OP == CC_OP);\n}\n\n#crnand lt,lt,lt\t\t\t\t\t\t\t0x4c 00 01 c2\n#crnand\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t\t0x4c 89 71 c2\n:crnand\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=225 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,!(CC_B_OP & CC_OP));\n}\n\n#crnor lt,lt,lt\t\t\t\t\t\t\t\t0x4c 00 00 42\n#crnor\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t\t0x4c 89 70 42\n:crnor\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=33 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,!(CC_B_OP | CC_OP));\n}\n\n#cror lt,lt,lt\t\t\t\t\t\t\t\t0x4c 00 03 82\n#cror\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t\t0x4c 89 73 82\n:cror\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=449 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,(CC_B_OP | CC_OP));\n}\n\n#crorc lt,lt,lt\t\t\t\t\t\t\t\t0x4c 00 03 42\n#crorc\t4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t\t0x4c 89 73 42\n:crorc\tCC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=417 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,((!CC_B_OP) | CC_OP));\n}\n\n#crxor lt,lt,lt\t\t\t\t\t\t\t\t0x4c 00 01 82\n#crxor 4*cr1+lt,4*cr2+gt,4*cr3+eq\t\t\t0x4c 89 71 82\n:crxor CC_D_OP,CC_OP,CC_B_OP\tis $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=193 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,(CC_B_OP ^ CC_OP));\n}\n\n@ifndef IS_ISA\n# replace with dci command in ISA\n#dccci 0,r0 0x7c 00 03 8c\n:dccci RA_OR_ZERO,B\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=454 & BIT_0=0 & RA_OR_ZERO\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheCongruenceClassInvalidate(ea);\n}\n@endif\n\n#===========================================================\n# DIVxx\n#===========================================================\n\n@ifdef BIT_64\n#divd r0,r0,r0\t\t0x7c 00 03 d2\n:divd D,A,B\t\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=489 & Rc=0\n{\n\tD = A s/ B;\n}\n\n#divd. r0,r0,r0\t\t0x7c 00 03 d3\n:divd. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=489 & Rc=1\n{\n\tD = A s/ B;\n\tcr0flags(D);\n}\n\n#divdo r0,r0,r0\t\t0x7c 00 07 d2\n:divdo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=489 & Rc=0\n{\n\tdivOverflow(A,B);\n\tD = A s/ B;\n}\n\n#divdo. r0,r0,r0\t0x7c 00 07 d3\n:divdo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=489 & Rc=1\n{\n\tdivOverflow(A,B);\n\tD = A s/ B;\n\tcr0flags(D);\n}\n\n######################\n#divdu r0,r0,r0\t\t0x7c 00 03 92\n:divdu D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=457 & Rc=0\n{\n\tD = A / B;\n}\n\n#divdu. r0,r0,r0\t\t0x7c 00 03 93\n:divdu. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=457 & Rc=1\n{\n\tD = A / B;\n\tcr0flags(D);\n}\n\n#divduo r0,r0,r0\t\t0x7c 00 07 92\n:divduo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=457 & Rc=0\n{\n\tdivZero(B);\n\tD = A / B;\n}\n\n#divduo. r0,r0,r0\t0x7c 00 07 93\n:divduo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=457 & Rc=1\n{\n\tdivZero(B);\n\tD = A / B;\n\tcr0flags(D);\n}\n@endif\n\n#############################3\n#divw r0,r0,r0\t\t0x7c 00 03 d6\n:divw D,A,B\t\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=491 & Rc=0\n{\n@ifdef BIT_64\n\tD = sext(A:4 s/ B:4);\n@else\n\tD = A s/ B;\n@endif\n}\n\n#divw. r0,r0,r0\t\t0x7c 00 03 d7\n:divw. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=491 & Rc=1\n{\n@ifdef BIT_64\n\tdivOverflow(A:4,B:4);\n\tD = sext(A:4 s/ B:4);\n\tcr0flags(D:4);\n@else\n\tdivOverflow(A,B);\n\tD = A s/ B;\n\tcr0flags(D);\n@endif\n}\n\n#divwo r0,r0,r0\t\t0x7c 00 07 d6\n:divwo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=491 & Rc=0\n{\n@ifdef BIT_64\n\tdivOverflow(A:4,B:4);\n\tD = sext(A:4 s/ B:4);\n@else\n\tdivOverflow(A,B);\n\tD = A s/ B;\n@endif\n}\n\n#divwo. r0,r0,r0\t0x7c 00 07 d7\n:divwo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=491 & Rc=1\n{\n@ifdef BIT_64\n\tdivOverflow(A:4,B:4);\n\tD = sext(A:4 s/ B:4);\n\tcr0flags(D:4);\n@else\n\tdivOverflow(A,B);\n\tD = A s/ B;\n\tcr0flags(D);\n@endif\n}\n\n#########################\n#divwu r0,r0,r0\t\t0x7c 00 03 96\n:divwu D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=459 & Rc=0\n{\n@ifdef BIT_64\n\tD = zext(A:4) / zext(B:4);\n@else\n\tD = A / B;\n@endif\n}\n\n#divwu. r0,r0,r0\t\t0x7c 00 03 97\n:divwu. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=459 & Rc=1\n{\n@ifdef BIT_64\n\tD = zext(A:4) / zext(B:4);\n\tcr0flags(D:4);\n@else\n\tD = A / B;\n\tcr0flags(D);\n@endif\n}\n\n#divwuo r0,r0,r0\t\t0x7c 00 07 96\n:divwuo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=459 & Rc=0\n{\n@ifdef BIT_64\n\tdivZero(B:4);\n\tD = zext(A:4) / zext(B:4);\n@else\n\tdivZero(B);\n\tD = A / B;\n@endif\n}\n\n#divwuo. r0,r0,r0\t0x7c 00 07 97\n:divwuo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=459 & Rc=1\n{\n@ifdef BIT_64\n\tdivZero(B:4);\n\tD = zext(A:4) / zext(B:4);\n\tcr0flags(D:4);\n@else\n\tdivZero(B);\n\tD = A / B;\n\tcr0flags(D);\n@endif\n}\n\n#===========================================================\n# ECxxx,EIxxx\n#===========================================================\n#eciwx r0,r0,r0\t\t0x7c 00 02 6c\n:eciwx D,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & D & B & RA_OR_ZERO & XOP_1_10=310 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tD = externalControlIn(ea);\n}\n\n#ecowx r0,r0,r0\t\t0x7c 00 03 6c\n:ecowx S,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & S & B & RA_OR_ZERO & XOP_1_10=438 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\texternalControlOut(ea, S);\n}\n\n#===========================================================\n# EIEIO\n#===========================================================\n# binutils-descr: \"eieio\",\tX(31,854),\t0xffffffff, PPC, BOOKE|PPCA2|PPC476,\t{0}\n# binutils: mytest.d: 20:\t7c 00 06 ac \teieio\n:eieio is OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { enforceInOrderExecutionIO(); }\n\n#===========================================================\n# EQVx\n#===========================================================\n#eqv r0,r0,r0\t0x7c 00 02 38\n:eqv A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=284 & Rc=0\n{\n\tA = ~(S ^ B);\n}\n\n#eqv. r0,r0,r0\t0x7c 00 02 39\n:eqv. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=284 & Rc=1\n{\n\tA = ~(S ^ B);\n\tcr0flags(A);\n}\n\n#===========================================================\n# EXTSBx\n#===========================================================\n#extsb r0,r0\t0x7c 00 07 74\n:extsb A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=954 & Rc=0\n{\n\tA = sext(S:1);\n}\n\n#extsb. r0,r0\t0x7c 00 07 75\n:extsb. A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=954 & Rc=1\n{\n\tA = sext(S:1);\n\tcr0flags(A);\n}\n\n#===========================================================\n# EXTSHx\n#===========================================================\n#extsh r0,r0\t0x7c 00 07 34\n:extsh A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=922 & Rc=0\n{\n\tA = sext(S:2);\n}\n\n#extsh. r0,r0\t0x7c 00 07 35\n:extsh. A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=922 & Rc=1\n{\n\tA = sext(S:2);\n\tcr0flags(A);\n}\n\n@ifdef BIT_64\n#extsw r0,r0\t0x7c 00 07 b4\n:extsw A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=986 & Rc=0\n{\n\tA = sext(S:4);\n}\n\n#extsw. r0,r0\t0x7c 00 07 b5\n:extsw. A,S\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=986 & Rc=1\n{\n\tA = sext(S:4);\n\tcr0flags(A);\n}\n@endif\n\n#===========================================================\n# FABSx\n#===========================================================\n#fabs fr,f1r\t\t0xfc 00 02 10\n:fabs fD,fB\t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=264 & Rc=0\n{\n \tfD = abs(fB);\n}\n\n#fabs. fr0,fr1\t\t0xfc 00 02 11\n:fabs. fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=264 & Rc=1\n{\n\tfD = abs(fB);\n\tcr1flags();\n}\n#fadd fr0,fr0,fr0\t0xfc 00 00 2a\n:fadd fD,fA,fB\tis $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tfD = fA f+ fB;\n\tsetFPAddFlags(tmpfA,tmpfB,fD);\n}\n\n#fadd. fr0,fr0,fr0\t0xfc 00 00 2b\n:fadd. fD,fA,fB\tis $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tfD = fA f+ fB;\n\tsetFPAddFlags(tmpfA,tmpfB,fD);\n\tcr1flags();\n}\n\n#fadds fr0,fr0,fr0\t0xec 00 00 2a\n:fadds fD,fA,fB\tis $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(fA f+ fB);\n\tfD = float2float(tmp);\n\tsetFPAddFlags(tmpfA,tmpfB,fD);\n\t\n}\n\n#fadds. fr0,fr0,fr0\t0xec 00 00 2b\n:fadds. fD,fA,fB\tis $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(fA f+ fB);\n\tfD = float2float(tmp);\n\tsetFPAddFlags(tmpfA,tmpfB,fD);\n\tcr1flags();\n}\n\n#===========================================================\n# FCFIDx\n#===========================================================\n#fcfid fr0,fr0\t\t0xfc 00 06 9c\n:fcfid fD,fB\t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=846 & Rc=0\n{\n\tfD = int2float(fB);\n}\n\n#fcfid. fr0,fr0\t\t0xfc 00 06 9d\n:fcfid. fD,fB\t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=846 & Rc=1\n{\n\tfD = int2float(fB);\n\tsetFPRF(fD);\n#\tfp_fr = intToFloatRoundedUp(fB);\n#\tfp_fi = intToFloatInexact(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#===========================================================\n# FCMPO\n#===========================================================\n#fcmpo fr0,fr0,fr0\t\t0xfc 00 00 40\n:fcmpo CRFD,fA,fB\t\tis $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & fA & fB & XOP_1_10=32 & BIT_0=0\n{\n\ttmp:1 = nan(fA) | nan(fB);\n\tfp_cc0 = (fA f< fB);\n\tfp_cc1 = (fA f> fB);\n\tfp_cc2 = (fA f== fB);\n\tCRFD = (fp_cc0 << 3) | (fp_cc1 << 2) | (fp_cc2 << 1) | tmp;\t\n}\n#fcmpu fr0,fr0,fr0\t\t0xfc 00 00 00\n:fcmpu CRFD,fA,fB\t\tis $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & fA & fB & XOP_1_10=0 & BIT_0=0\n{\n\ttmp:1 = nan(fA) | nan(fB);\n\tfp_cc0 = (fA f< fB);\n\tfp_cc1 = (fA f> fB);\n\tfp_cc2 = (fA f== fB);\n\tCRFD = (fp_cc0 << 3) | (fp_cc1 << 2) | (fp_cc2 << 1) | tmp;\t\n}\n\n#fctid fr0,fr0\t0xfc 00 06 5c\n:fctid fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=814 & Rc=0\n{\n#\tfp_fr = floatToIntRoundedUp(fB);\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n#\tfp_xx = fp_xx | fp_fi;\n\tfD = trunc(fB);\n}\n#fctid. fr0,fr0\t0xfc 00 06 5d\n:fctid. fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=814 & Rc=1\n{\n#\tfp_fr = floatToIntRoundedUp(fB);\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_xx = fp_xx | fp_fi;\n#\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tsetSummaryFPSCR();\n\tcr1flags();\n\tfD = trunc(fB);\n}\n#fctidz fr0,fr0\t0xfc 00 06 5e\n:fctidz fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=815 & Rc=0\n{\n\tfp_fr = 0;\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tfD = trunc(fB);\n}\n#fctidz. fr0,fr0\t0xfc 00 06 5f\n:fctidz. fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=815 & Rc=1\n{\n\tfp_fr = 0;\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tsetSummaryFPSCR();\n\tcr1flags();\n\tfD = trunc(fB);\n}\n\n#fctiw fr0,fr0\t0xfc 00 00 1c\n:fctiw fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=14 & Rc=0\n{\n#\tfp_fr = floatToIntRoundedUp(fB);\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tlocal intres:4;\n\tintres = trunc(fB);\n\tfD = sext(intres);\n}\n#fctiw. fr0,fr0\t0xfc 00 00 1d\n:fctiw. fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=14 & Rc=1\n{\n#\tfp_fr = floatToIntRoundedUp(fB);\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tsetSummaryFPSCR();\n\tcr1flags();\n\tlocal intres:4;\n\tintres = trunc(fB);\n\tfD = sext(intres);\n}\n#fctiwz fr0,fr0\t0xfc 00 00 1e\n:fctiwz fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=15 & Rc=0\n{\n\tfp_fr = 0;\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tlocal intres:4;\n\tintres = trunc(fB);\n\tfD = sext(intres);\n}\n#fctiwz. fr0,fr0\t0xfc 00 00 1f\n:fctiwz. fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=15 & Rc=1\n{\n\tfp_fr = 0;\n#\tfp_fi = floatToIntInexact(fB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(fB);\n#\tfp_vxcvi = fp_vxcvi | invalidFloatToInt(fB);\n\tsetSummaryFPSCR();\n\tcr1flags();\n\tlocal intres:4;\n\tintres = trunc(fB);\n\tfD = sext(intres);\n}\n\n#fdiv fr0,fr0,fr0 0xfc 00 00 24\n:fdiv fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tfD = fA f/ fB;\n\tsetFPDivFlags(tmpfA,tmpfB,fD);\n}\n#fdiv. fr0,fr0,fr0 0xfc 00 00 25\n:fdiv. fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tfD = fA f/ fB;\n\tsetFPDivFlags(tmpfA,tmpfB,fD);\n\tcr1flags();\n}\n\n#fdivs fr0,fr0,fr0 0xec 00 00 24\n:fdivs fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(fA f/ fB);\n\tfD = float2float(tmp);\n\tsetFPDivFlags(tmpfA,tmpfB,fD);\n}\n#fdivs. fr0,fr0,fr0 0xec 00 00 25\n:fdivs. fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(fA f/ fB);\n\tfD = float2float(tmp);\n\tsetFPDivFlags(tmpfA,tmpfB,fD);\n\tcr1flags();\n}\n\n#fmadd fr0,fr0,fr0,fr0\t0xfc 00 00 3a\n:fmadd fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=29 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\tfD = tmp f+ fB;\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fmadd. fr0,fr0,fr0,fr0\t0xfc 00 00 3b\n:fmadd. fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=29 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\tfD = tmp f+ fB;\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fmadds fr0,fr0,fr0,fr0\t0xec 00 00 3a\n:fmadds fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=29 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f+ fB);\n\tfD = float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tm[fC);\n\tsetSummaryFPSCR();\n}\n\n#fmadds. fr0,fr0,fr0,fr0\t0xec 00 00 3b\n:fmadds. fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=29 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f+ fB);\n\tfD = float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fmr fr0,fr0\t0xfc 00 00 90\n:fmr fD,fB \t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=72 & Rc=0\n{\n\tfD = fB;\n}\n#fmr. fr0,fr0\t0xfc 00 00 91\n:fmr. fD,fB \t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=72 & Rc=1\n{\n\tfD = fB;\n\tcr1flags();\n}\n#fmsub fr0,fr0,fr0,fr0\t0xfc 00 00 38\n:fmsub fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=28 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\tfD = tmp f- fB;\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fmsub. fr0,fr0,fr0,fr0\t0xfc 00 00 39\n:fmsub. fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=28 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f- fB);\n\tfD = float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fmsubs fr0,fr0,fr0,fr0\t0xec 00 00 38\n:fmsubs fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=28 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f- fB);\n\tfD = float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fmsubs. fr0,fr0,fr0,fr0\t0xfc 00 00 39\n:fmsubs. fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=28 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f- fB);\n\tfD = float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fmul fr0,fr0,fr0\t0xfc 00 00 32\n:fmul fD,fA,fC\tis $(NOTVLE) & OP=63 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfC = fC;\n\tfD = fA f* fC;\n\tsetFPMulFlags(tmpfA,tmpfC,fD);\n}\n#fmul. fr0,fr0,fr0\t0xfc 00 00 33\n:fmul. fD,fA,fC\tis $(NOTVLE) & OP=63 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfC = fC;\n\tfD = fA f* fC;\n\tsetFPMulFlags(tmpfA,tmpfC,fD);\n\tcr1flags();\n}\n\n#fmuls fr0,fr0,fr0\t0xec 00 00 32\n:fmuls fD,fA,fC\tis $(NOTVLE) & OP=59 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfC = fC;\n\ttmp:4 = float2float(fA f* fC);\n\tfD = float2float(tmp);\n\tsetFPMulFlags(tmpfA,tmpfC,fD);\n}\n\n#fmuls. fr0,fr0,fr0\t0xec 00 00 33\n:fmuls. fD,fA,fC\tis $(NOTVLE) & OP=59 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfC = fC;\n\ttmp:4 = float2float(fA f* fC);\n\tfD = float2float(tmp);\n\tsetFPMulFlags(tmpfA,tmpfC,fD);\n\tcr1flags();\n}\n\n#fnabs fr0,fr0\t0xfc 00 01 10\n:fnabs fD,fB\tis $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=136 & Rc=0\n{\n\tfD = fB | 0x8000000000000000;\n}\n\n#fnabs. fr0,fr0\t0xfc 00 01 11\n:fnabs. fD,fB\tis $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=136 & Rc=1\n{\n\tfD = fB | 0x8000000000000000;\n\tcr1flags();\n}\n\n#fneg fr0,fr0\t0xfc 00 00 50\n:fneg fD,fB\tis $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=40 & Rc=0\n{\n\tfD = f- fB;\n}\n\n#fneg. fr0,fr0\t0xfc 00 00 51\n:fneg. fD,fB\tis $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=40 & Rc=1\n{\n\tfD = f- fB;\n\tcr1flags();\n}\n\n#fnmadd fr0,fr0,fr0,fr0\t0xfc 00 00 3e\n:fnmadd fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=31 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\tfD = f- (tmp f+ fB);\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fnmadd. fr0,fr0,fr0,fr0\t0xfc 00 00 3f\n:fnmadd. fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=31 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\tfD = f- (tmp f+ fB);\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fnmadds fr0,fr0,fr0,fr0\t0xec 00 00 3e\n:fnmadds fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=31 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f+ fB);\n\tfD = f- float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fnmadds. fr0,fr0,fr0,fr0\t0xec 00 00 3f\n:fnmadds. fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=31 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f+ fB);\n\tfD = f- float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fnmsub fr0,fr0,fr0,fr0\t0xfc 00 00 3c\n:fnmsub fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=30 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\tfD = f- (tmp f- fB);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fnmsub. fr0,fr0,fr0,fr0\t0xfc 00 00 3d\n:fnmsub. fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=30 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f- fB);\n\tfD = f- float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fnmsubs fr0,fr0,fr0,fr0\t0xec 00 00 3c\n:fnmsubs fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=30 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f- fB);\n\tfD = f- float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n}\n\n#fnmsubs. fr0,fr0,fr0,fr0\t0xfc 00 00 3d\n:fnmsubs. fD,fA,fC,fB\tis $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=30 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tlocal tmpfC = fC;\n\ttmp:8 = fA f* fC;\n\ttmp2:4 = float2float(tmp f- fB);\n\tfD = f- float2float(tmp2);\n\tsetFPRF(fD);\n#\tfp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB);\n#\tfp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB);\n#\tfp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB);\n#\tfp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB);\n#\tfp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB);\n#\tfp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#fres fr0,fr0\t\t0xec 00 00 30\n:fres fD,fB\tis $(NOTVLE) & OP=59 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=0 \n{\n\tlocal tmpfB = fB;\n\tone:8 = 1;\n\tfloatOne:8 = int2float(one);\n\ttmp:4 = float2float(floatOne f/ fB);\n\tfD = float2float(tmp);\n\tsetFPRF(fD);\n#\tfp_fr = floatDivRoundedUp(floatOne, tmpfB);\n#\tfp_fi = floatDivInexact(floatOne, tmpfB);\n#\tfp_ox = fp_ox | floatDivOverflow(floatOne, tmpfB);\n#\tfp_ux = fp_ux | floatDivUnderflow(floatOne, tmpfB);\n\tfp_zx = fp_zx | (fB f== 0);\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n\tsetSummaryFPSCR();\t\n}\n\n#fres. fr0,fr0\t\t0xec 00 00 31\n:fres. fD,fB\tis $(NOTVLE) & OP=59 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=1\n{\n\tlocal tmpfB = fB;\n\tone:8 = 1;\n\tfloatOne:8 = int2float(one);\n\ttmp:4 = float2float(floatOne f/ fB);\n\tfD = float2float(tmp);\n\tsetFPRF(fD);\n#\tfp_fr = floatDivRoundedUp(floatOne, tmpfB);\n#\tfp_fi = floatDivInexact(floatOne, tmpfB);\n#\tfp_ox = fp_ox | floatDivOverflow(floatOne, tmpfB);\n#\tfp_ux = fp_ux | floatDivUnderflow(floatOne, tmpfB);\n\tfp_zx = fp_zx | (fB f== 0);\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#frsp fr0,fr0\t\t0xfc 00 00 18\n:frsp fD,fB\t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=12 & Rc=0\n{\n\tlocal tmpfB = fB;\n\t#zero:8 = 0;\n\t#floatZero:8 = int2float(zero);\n\ttmp:4 = float2float(fB);\n\tfD = float2float(tmp);\n\tsetFPRF(fD);\n#\tfp_fr = floatAddRoundedUp(floatZero, tmpfB);\n#\tfp_fi = floatAddInexact(floatZero, tmpfB);\n#\tfp_ox = fp_ox | floatAddOverflow(floatZero, tmpfB);\n#\tfp_ux = fp_ux | floatAddUnderflow(floatZero, tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n\tsetSummaryFPSCR();\n}\n\n#frsp. fr0,fr0\t\t0xfc 00 00 19\n:frsp. fD,fB\t\tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=12 & Rc=1\n{\n\tlocal tmpfB = fB;\n\t#zero:8 = 0;\n\t#floatZero:8 = int2float(zero);\n\ttmp:4 = float2float(fB);\n\tfD = float2float(tmp);\n\tsetFPRF(fD);\n#\tfp_fr = floatAddRoundedUp(floatZero, tmpfB);\n#\tfp_fi = floatAddInexact(floatZero, tmpfB);\n#\tfp_ox = fp_ox | floatAddOverflow(floatZero, tmpfB);\n#\tfp_ux = fp_ux | floatAddUnderflow(floatZero, tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n\tsetSummaryFPSCR();\n\tcr1flags();\n}\n\n#frsqrte fr0,fr0\t\t0xfc 00 00 34\n:frsqrte fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=26 & Rc=0 \n{\n\tlocal tmpfB = fB;\n\tone:8 = 1;\n\tfloatOne:8 = int2float(one);\n\ttmpSqrt:8 = sqrt(fB);\n\tfD = (floatOne f/ tmpSqrt);\n\tsetFPRF(fD);\n#\tfp_fr = floatDivRoundedUp(floatOne, tmpSqrt);\n#\tfp_fi = floatDivInexact(floatOne, tmpSqrt);\n#\tfp_ox = fp_ox | floatDivOverflow(floatOne, tmpSqrt);\n#\tfp_ux = fp_ux | floatDivUnderflow(floatOne, tmpSqrt);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n\tsetSummaryFPSCR();\t\n}\n\n#frsqrte. fr0,fr0\t\t0xfc 00 00 35\n:frsqrte. fD,fB\tis $(NOTVLE) & OP=63 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=26 & Rc=1\n{\n\tlocal tmpfB = fB;\n\tone:8 = 1;\n\tfloatOne:8 = int2float(one);\n\ttmpSqrt:8 = sqrt(fB);\n\tfD = (floatOne f/ tmpSqrt);\n\tsetFPRF(fD);\n#\tfp_fr = floatDivRoundedUp(floatOne, tmpSqrt);\n#\tfp_fi = floatDivInexact(floatOne, tmpSqrt);\n#\tfp_ox = fp_ox | floatDivOverflow(floatOne, tmpSqrt);\n#\tfp_ux = fp_ux | floatDivUnderflow(floatOne, tmpSqrt);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n\tfp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB);\n\tsetSummaryFPSCR();\t\n\tcr1flags();\n}\n\n#fsel f0r,fr0,fr0,fr0\t0xfc 00 00 2e\n:fsel fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fB & fC & XOP_1_5=23 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tzero:4=0;\n\tfD=fC;\n\tif (tmpfA f>= int2float(zero)) goto inst_next;\n\tfD=tmpfB;\n}\n\n#fsel. fr0,fr0,fr0,fr0\t0xfc 00 00 2f\n:fsel. fD,fA,fC,fB\tis $(NOTVLE) & OP=63 & fD & fA & fB & fC & XOP_1_5=23 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tzero:4=0;\n\tfD=fC;\n\tif (tmpfA f>= int2float(zero)) goto ;\n\tfD=tmpfB;\n\n\tcr1flags();\n}\n\n#fsqrt f0r,fr0\t0xfc 00 00 2c\n:fsqrt fD,fB \tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=0\n{\n\tlocal tmpfB = fB;\n\tfD = sqrt(fB);\n\tsetFPRF(fD);\n#\tfp_fr = floatSqrtRoundedUp(tmpfB);\n#\tfp_fi = floatSqrtInexact(tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n#\tfp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB);\n\tsetSummaryFPSCR();\t\n}\n \n#fsqrt. fr0,fr0\t0xfc 00 00 2d\n:fsqrt. fD,fB \tis $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=1\n{\n\tlocal tmpfB = fB;\n\tfD = sqrt(fB);\n\tsetFPRF(fD);\n#\tfp_fr = floatSqrtRoundedUp(tmpfB);\n#\tfp_fi = floatSqrtInexact(tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n#\tfp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB);\n\tsetSummaryFPSCR();\t\n\tcr1flags();\n} \n\n#fsqrts fr0,fr0\t0xec 00 00 2c\n:fsqrts fD,fB \tis $(NOTVLE) & OP=59 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=0\n{\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(sqrt(fB));\n\tfD = float2float(tmp);\n\tsetFPRF(fD);\n#\tfp_fr = floatSqrtRoundedUp(tmpfB);\n#\tfp_fi = floatSqrtInexact(tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n#\tfp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB);\n\tsetSummaryFPSCR();\t\n}\n \n#fsqrts. fr0,fr0\t0xec 00 00 2d\n:fsqrts. fD,fB \tis $(NOTVLE) & OP=59 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=1\n{\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(sqrt(fB));\n\tfD = float2float(tmp);\n\tsetFPRF(fD);\n#\tfp_fr = floatSqrtRoundedUp(tmpfB);\n#\tfp_fi = floatSqrtInexact(tmpfB);\n\tfp_xx = fp_xx | fp_fi;\n\tfp_vxsnan = fp_vxsnan | nan(tmpfB);\n#\tfp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB);\n\tsetSummaryFPSCR();\t\n\tcr1flags();\n} \n\n#fsub fr0,fr0,fr0\t0xfc 00 00 28\n:fsub fD,fA,fB\tis $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tfD = fA f- fB;\n\tsetFPSubFlags(tmpfA,tmpfB,fD);\n}\n\n#fsub. fr0,fr0,fr0\t0xfc 00 00 29\n:fsub. fD,fA,fB\tis $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\tfD = fA f- fB;\n\tsetFPSubFlags(tmpfA,tmpfB,fD);\n\tcr1flags();\n}\n\n#fsubs fr0,fr0,fr0\t0xec 00 00 28\n:fsubs fD,fA,fB\tis $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=0\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(fA f- fB);\n\tfD = float2float(tmp);\n\tsetFPSubFlags(tmpfA,tmpfB,fD);\n\t\n}\n\n#fsubs. fr0,fr0,fr0\t0xec 00 00 29\n:fsubs. fD,fA,fB\tis $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=1\n{\n\tlocal tmpfA = fA;\n\tlocal tmpfB = fB;\n\ttmp:4 = float2float(fA f- fB);\n\tfD = float2float(tmp);\n\tsetFPSubFlags(tmpfA,tmpfB,fD);\n\tcr1flags();\n}\n\n@ifndef IS_ISA\n# iccci is just a special form of ici\n#iccci 0,r0 0x7c 00 07 8c\n:iccci RA_OR_ZERO,B\t\tis OP=31 & BITS_21_25=0 & B & XOP_1_10=966 & BIT_0=0 & RA_OR_ZERO\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tinstructionCacheCongruenceClassInvalidate(ea);\t\n}\n@endif\n\n#lbz\tr0,3(0)\t\t0x88 00 00 03\n#lbz\tr0,3(r2)\t0x88 02 00 03\n:lbz\tD,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=34 & D & dPlusRaOrZeroAddress\n{\n\tD = zext(*:1(dPlusRaOrZeroAddress));\n\t\n}\n\n#lbzu\tr0,3(r2)\t0x8c 02 00 03\n:lbzu\tD,dPlusRaAddress\tis $(NOTVLE) & OP=35 & D & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n\tD = zext(*:1(ea));\n\tA = ea;\n}\n\n#lbzux\tr0,r2,r0\t0x7c 02 00 ee\n:lbzux\tD,A,B\t\t\t\tis OP=31 & D & A & B & XOP_1_10=119 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tD = zext(*:1(ea));\n\tA = ea;\n}\n\n#lbzx\tr0,r2,r0\t0x7c 02 00 ae\n:lbzx\tD,RA_OR_ZERO,B\t\tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=87 & BIT_0=0\n{\n\ttmp:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = zext(*:1(tmp));\n}\n\n@ifdef BIT_64\n#ld r0,8(r2)\t0xe8 02 00 08\t\n:ld\tD,dPlusRaOrZeroAddress \tis $(NOTVLE) & OP=58 & D & dPlusRaOrZeroAddress & BITS_0_1=0\n{\n\tD = *:8(dPlusRaOrZeroAddress);\n}\n\n##ldarx r0,r0,r0\t 0x7c 00 00 a8\n#:ldarx T,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & T & RA_OR_ZERO & B & XOP_1_10=84 & TX\n#{\n#\tea = RA_OR_ZERO+B;\n#\tRESERVE = 1;\n#\tRESERVE_ADDRSS = ea;\n#\tT = *:8(ea);\n#}\n\n#ldu\tr0,8(r2)\t0xe8 02 00 09\n:ldu\tD,dsPlusRaAddress\tis $(NOTVLE) & OP=58 & D & dsPlusRaAddress & A & BITS_0_1=1\n{\n\tea:$(REGISTER_SIZE) = dsPlusRaAddress;\n\tD = *:8(ea);\n\tA = ea;\n}\n\n#ldux\tr0,r2,r0\t0x7c 02 00 6a\n:ldux\tD,A,B\t\t\tis OP=31 & D & A & B & XOP_1_10=53 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tD = *:8(ea);\n\tA = ea;\n}\n\n@ifndef IS_ISA\n#ldarx r0,r2,r0\t 0x7c 02 00 2a\n:ldarx D,RA_OR_ZERO,B\tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=21 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = *:8(ea);\n}\n@endif\n@endif\n\n#lfd fr0,8(r2)\t0xc8 02 00 08\t\n:lfd\tfD,dPlusRaOrZeroAddress \tis $(NOTVLE) & OP=50 & fD & dPlusRaOrZeroAddress\n{\n\tfD = *:8(dPlusRaOrZeroAddress);\n}\n\n#lfdu fr0,8(r2)\t0xcc 02 00 08\t\n:lfdu\tfD,dPlusRaAddress \tis $(NOTVLE) & OP=51 & fD & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n\tfD = *:8(ea);\n\tA = ea;\n}\n#lfdux fr0,r2,r0\t0x7c 02 04 ee\t\n:lfdux\tfD,A,B \tis $(NOTVLE) & OP=31 & fD & A & B & XOP_1_10=631 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tfD = *:8(ea);\n\tA = ea;\n}\n#lfdx fr0,r2,r0\t0x7c 02 04 ae\t\n:lfdx\tfD,RA_OR_ZERO,B \tis $(NOTVLE) & OP=31 & fD & RA_OR_ZERO & B & XOP_1_10=599 & BIT_0=0\n{\n\tfD = *:8(RA_OR_ZERO+B);\n}\n\n#lfs fr0,8(r2)\t0xc0 02 00 08\t\n:lfs\tfD,dPlusRaOrZeroAddress \tis $(NOTVLE) & OP=48 & fD & dPlusRaOrZeroAddress\n{\n\tfD = float2float(*:4(dPlusRaOrZeroAddress));\n}\n#lfsu fr0,8(r2)\t0xc0 02 00 08\t\n:lfsu\tfD,dPlusRaAddress \tis $(NOTVLE) & OP=49 & fD & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n\tfD = float2float(*:4(ea));\n\tA = ea;\n}\n\n#lfsux fr0,r2,r0\t0x7c 02 04 6e\t\n:lfsux\tfD,A,B \tis $(NOTVLE) & OP=31 & fD & A & B & XOP_1_10=567 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tfD = float2float(*:4(ea));\n\tA = ea;\n}\n#lfsx fr0,r2,r0\t0x7c 02 04 2e\t\n:lfsx\tfD,RA_OR_ZERO,B \tis $(NOTVLE) & OP=31 & fD & RA_OR_ZERO & B & XOP_1_10=535 & BIT_0=0\n{\n\tfD = float2float(*:4(RA_OR_ZERO+B));\n}\n#lha\tr0,4(0)\t\t0xa8 00 00 04\n#lha\tr0,4(r2)\t0xa8 02 00 04\n:lha\tD,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=42 & D & dPlusRaOrZeroAddress\n{\n\tD = sext(*:2(dPlusRaOrZeroAddress));\n\t\n}\n#lhau r0,8(r2)\t0xac 02 00 08\t\n:lhau D,dPlusRaAddress \tis $(NOTVLE) & OP=43 & D & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n\tD = sext(*:2(ea));\n\tA = ea;\n}\n#lhaux r0,r2,r0\t0x7c 02 02 ee\t\n:lhaux D,A,B \t\t\tis OP=31 & D & A & B & XOP_1_10=375 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tD = sext(*:2(ea));\n\tA = ea;\n}\n#lhax r0,r2,r0\t0x7c 02 02 ae\t\n:lhax D,RA_OR_ZERO,B \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=343 & BIT_0=0\n{\n\tD = sext(*:2(RA_OR_ZERO+B));\n}\n\n#lhbrx r0,r2,r0\t0x7c 02 06 2c\t\n:lhbrx D,RA_OR_ZERO,B \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=790 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\ttmp:$(REGISTER_SIZE) = zext(*:1(ea+1)) << 8;\n\tD = tmp | zext(*:1(ea));\n}\n\n#lhz\tr0,4(0)\t\t0xa0 00 00 04\n#lhz\tr0,4(r2)\t0xa0 02 00 04\n:lhz\tD,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=40 & D & dPlusRaOrZeroAddress\n{\n\tD = zext(*:2(dPlusRaOrZeroAddress));\n\t\n}\n\n#lhzu\tr0,4(r2)\t0xa4 02 00 04\n:lhzu\tD,dPlusRaAddress\tis $(NOTVLE) & OP=41 & D & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n\tD = zext(*:2(ea));\n\tA = ea;\n}\n\n#lhzux r0,r2,r0\t0x7c 02 02 6e\t\n:lhzux D,A,B \t\t\tis OP=31 & D & A & B & XOP_1_10=311 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tD = zext(*:2(ea));\n\tA = ea;\n}\n#lhzx r0,r2,r0\t0x7c 02 02 2e\t\n:lhzx D,RA_OR_ZERO,B \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=279 & BIT_0=0\n{\n\tD = zext(*:2(RA_OR_ZERO+B));\n}\n\n# big stuffs\n@include \"lmwInstructions.sinc\"\n\n@include \"lswInstructions.sinc\"\n\n#lswx\tr0,0,r0\t\t\t0x7c 00 3c 2a\n#lswx\tr0,r2,40\t\t0x7c 02 3c 2a\ndefine pcodeop lswxOp;\n:lswx\tD,RA_OR_ZERO,B\tis OP=31 & D & RA_OR_ZERO & NB & BITS_21_25 & B & XOP_1_10=533 & BIT_0=0\n{\n\tD = lswxOp(D,RA_OR_ZERO,B);\n}\n@ifdef BIT_64\n#lwa\tr0,8(r2)\t0xe8 02 00 0a\n:lwa\tD,dsPlusRaOrZeroAddress\tis $(NOTVLE) & OP=58 & D & dsPlusRaOrZeroAddress & BITS_0_1=2\n{\n\tD = sext(*:4(dsPlusRaOrZeroAddress));\n}\n@endif\n\n#lwarx r0,r0,r0\t 0x7c 00 00 28\n:lwarx D,RA_OR_ZERO,B\tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=20 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\t#RESERVE = 1;\n\t#RESERVE_ADDRSS:$(REGISTER_SIZE) = ea;\n@ifdef BIT_64\n\tD = zext(*:4(ea));\n@else\n\tD = *:4(ea);\n@endif\n}\n\n@ifdef BIT_64\n#lwaux r0,r2,r0\t0x7c 02 02 ea\t\n:lwaux D,A,B \t\t\tis OP=31 & D & A & B & XOP_1_10=373 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\tD = sext(*:4(ea));\n\tA = ea;\n}\n#lwax r0,r2,r0\t0x7c 02 02 aa\t\n:lwax D,RA_OR_ZERO,B \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=341 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = sext(*:4(ea));\n}\n@endif\n\n#lwbrx r0,r2,r0\t0x7c 02 04 2c\t\n:lwbrx D,RA_OR_ZERO,B \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=534 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\ttmp1:$(REGISTER_SIZE) = zext(*:1(ea+3)) << 24;\n\ttmp2:$(REGISTER_SIZE) = zext(*:1(ea+2)) << 16;\n\ttmp3:$(REGISTER_SIZE) = zext(*:1(ea+1)) << 8;\n\tD = tmp1 | tmp2 | tmp3 | zext(*:1(ea));\n}\n#lwz\tr0,4(0)\t\t0x80 00 00 04\n#lwz\tr0,4(r2)\t0x80 02 00 04\n:lwz\tD,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=32 & D & dPlusRaOrZeroAddress\n{\n@ifdef BIT_64\n\tD = zext(*:4(dPlusRaOrZeroAddress));\n@else\n\tD = *:4(dPlusRaOrZeroAddress);\n@endif\n}\n\n#lwzu\tr0,4(r2)\t0x84 02 00 04\n:lwzu\tD,dPlusRaAddress\tis $(NOTVLE) & OP=33 & D & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n@ifdef BIT_64\n\tD = zext(*:4(ea));\n@else\n\tD = *:4(ea);\n@endif\n\tA = ea;\n}\n\n#lwzux r0,r2,r0\t0x7c 02 00 6e\t\n:lwzux D,A,B \t\t\tis OP=31 & D & A & B & XOP_1_10=55 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n@ifdef BIT_64\n\tD = zext(*:4(ea));\n@else\n\tD = *:4(ea);\n@endif\n\tA = ea;\n\n}\n#lwzx r0,r2,r0\t0x7c 02 00 2e\t\n:lwzx D,RA_OR_ZERO,B \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=23 & BIT_0=0\n{\n@ifdef BIT_64\n\tD = zext(*:4(RA_OR_ZERO+B));\n@else\n\tD = *:4(RA_OR_ZERO+B);\n@endif\n}\n\n\n@ifndef NoLegacyIntegerMultiplyAccumulate\n@include \"mulhwInstructions.sinc\"\n@endif\n\n#mcrf cr0,cr0\t0x4c 00 00 00\n:mcrf CRFD,CRFS\t\tis $(NOTVLE) & OP=19 & CRFD & BITS_21_22=0 & CRFS & BITS_0_17=0 \n{\n\tCRFD = CRFS;\n}\n\n#mcrfs cr0,cr0\t0xfc 00 00 80\n:mcrfs CRFD,CRFS\tis $(NOTVLE) & OP=63 & CRFD & FPSCR_CRFS & BITS_21_22=0 & CRFS & BITS_11_17=0 & XOP_1_10=64 & BIT_0=0\n{\n\tCRFD = FPSCR_CRFS;\n}\n\n#mcrxr cr0\t0x7c 00 04 00\n:mcrxr CRFD\t\tis OP=31 & CRFD & BITS_11_22=0 & XOP_1_10=512 & BIT_0=0\n{\n\tCRFD = (xer_so & 1) << 3 | (xer_ov & 1) << 2 | (xer_ca & 1) << 1;\n\txer_so = 0;\n\txer_ov = 0;\n\txer_ca = 0;\n}\n\n#mfcr r0 \t0x7c 00 00 26\n:mfcr D\t\tis OP=31 & D & BITS_11_20=0 & XOP_1_10=19 & BIT_0=0\n{\n\ttmp:4 = zext(cr0 & 0xf) << 28 |\n\t\t\tzext(cr1 & 0xf) << 24 |\n\t\t\tzext(cr2 & 0xf) << 20 |\n\t\t\tzext(cr3 & 0xf) << 16 |\n\t\t\tzext(cr4 & 0xf) << 12 |\n\t\t\tzext(cr5 & 0xf) << 8 |\n\t\t\tzext(cr6 & 0xf) << 4 |\n\t\t\tzext(cr7 & 0xf);\n@ifdef BIT_64\n\tD = zext(tmp);\n@else\n\tD = tmp;\n@endif\n}\n\n#mfocrf D,cr1 0x7c 31 00 26\n:mfocrf D,CRM_CR\tis OP=31 & D & BIT_20=1 & CRM_CR & BIT_11 & XOP_1_10=19 & BIT_0=0\n{\n@ifdef BIT_64\n\tD = zext(CRM_CR);\n@else\n\tD = CRM_CR;\n@endif\n}\n\n#mffs fD\t0xfc 00 04 8e\n:mffs fD\t\tis $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=0\n{\n\ttmp:4 = 0;\n\tpackFPSCR(tmp);\n\tfD = zext(tmp);\n}\n\n#mffs. fD\t0xfc 00 04 8f\n:mffs. fD\t\tis $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=1\n{\n\ttmp:4 = 0;\n\tpackFPSCR(tmp);\n\tfD = zext(tmp);\n\tcr1flags();\n}\n\n### is this pcode correct on 64-bit bridge?\n#mfsr r0,r0\t0x7c 00 04 a6\n:mfsr D,B\t\tis $(NOTVLE) & OP=31 & D & SR & BIT_20=0 & B & BITS_11_15=0 & XOP_1_10=595 & BIT_0=0\n{\n@ifdef BIT_64\n\tD = zext(SR);\n@else\n\tD = SR;\n@endif\n}\n#mfsrin r0,r0\t0x7c 00 05 26\n:mfsrin D,B\t\tis $(NOTVLE) & OP=31 & D & BITS_16_20=0 & B & XOP_1_10=659 & BIT_0=0\n{\n@ifdef BIT_64\n\ttmp:4 = (B:4 >> 28);\n@else\n\ttmp:$(REGISTER_SIZE) = (B >> 28);\n@endif\n\tD = *[register]:4 ($(SEG_REGISTER_BASE)+tmp);\n}\n\n#mtcrf 10,r0\t\t0x7c 01 01 20\n:mtcrf CRM,S\tis OP=31 & S & BIT_20=0 & CRM & CRM0 & CRM1 & CRM2 & CRM3 & CRM4 & CRM5 & CRM6 & CRM7 & BIT_11=0 & XOP_1_10=144 & BIT_0=0 \n{\n\ttmp:$(REGISTER_SIZE) = (S >> 28) & 0xf;\n\tcr0 = (cr0 * (CRM0:1 == 0)) | (tmp:1 * (CRM0:1 == 1));\n\n\ttmp = (S >> 24) & 0xf;\n\tcr1 = (cr1 * (CRM1:1 == 0)) | (tmp:1 * (CRM1:1 == 1));\n\n\ttmp = (S >> 20) & 0xf;\n\tcr2 = (cr2 * (CRM2:1 == 0)) | (tmp:1 * (CRM2:1 == 1));\n\n\ttmp = (S >> 16) & 0xf;\n\tcr3 = (cr3 * (CRM3:1 == 0)) | (tmp:1 * (CRM3:1 == 1));\n\n\ttmp = (S >> 12) & 0xf;\n\tcr4 = (cr4 * (CRM4:1 == 0)) | (tmp:1 * (CRM4:1 == 1));\n\n\ttmp = (S >> 8) & 0xf;\n\tcr5 = (cr5 * (CRM5:1 == 0)) | (tmp:1 * (CRM5:1 == 1));\n\n\ttmp = (S >> 4) & 0xf;\n\tcr6 = (cr6 * (CRM6:1 == 0)) | (tmp:1 * (CRM6:1 == 1));\n\n\ttmp = S & 0xf;\n\tcr7 = (cr7 * (CRM7:1 == 0)) | (tmp:1 * (CRM7:1 == 1));\n}\n\n#mtfsb0 fp_ux\t\t0xfc 80 00 8c\n:mtfsb0 CRBD\tis $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=70 & Rc=0\n{\n\tCRBD = 0;\n}\n#mtfsb0. fp_ux\t\t0xfc 80 00 8d\n:mtfsb0. CRBD\tis $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=70 & Rc=1\n{\n\tCRBD = 0;\n\tcr1flags();\n}\n#mtfsb1 fp_ux\t\t0xfc 80 00 4c\n:mtfsb1 CRBD\tis $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=38 & Rc=0\n{\n\tCRBD = 1;\n}\n#mtfsb1. fp_ux\t\t0xfc 80 00 4d\n:mtfsb1. CRBD\tis $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=38 & Rc=1\n{\n\tCRBD = 1;\n}\n\n#mtfsf 10,fr0\t\t0xfc 00 05 8e\n:mtfsf FM,fB\tis $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=0\n{\n\ttmp:4 = 0;\n\tpackFPSCR(tmp);\n\t\n\tmask0:4 = zext((FM0:1 == 1)* 0xf) << 28;\n\tmask1:4 = zext((FM1:1 == 1)* 0xf) << 24;\n\tmask2:4 = zext((FM2:1 == 1)* 0xf) << 20;\n\tmask3:4 = zext((FM3:1 == 1)* 0xf) << 16;\n\tmask4:4 = zext((FM4:1 == 1)* 0xf) << 12;\n\tmask5:4 = zext((FM5:1 == 1)* 0xf) << 8;\n\tmask6:4 = zext((FM6:1 == 1)* 0xf) << 4;\n\tmask7:4 = zext((FM7:1 == 1)* 0xf);\n\t\n\tmask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7;\n\t\n\ttmp1:4 = fB:4;\n\ttmp2:4 = (tmp & ~mask) | (tmp1 & mask);\n\tunpackFPSCR(tmp2);\n}\n\n#mtfsf. 10,fr0\t\t0xfc 00 05 8f\n:mtfsf. FM,fB\tis $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=1\n{\n\ttmp:4 = 0;\n\tpackFPSCR(tmp);\n\t\n\tmask0:4 = zext((FM0:1 == 1)* 0xf) << 28;\n\tmask1:4 = zext((FM1:1 == 1)* 0xf) << 24;\n\tmask2:4 = zext((FM2:1 == 1)* 0xf) << 20;\n\tmask3:4 = zext((FM3:1 == 1)* 0xf) << 16;\n\tmask4:4 = zext((FM4:1 == 1)* 0xf) << 12;\n\tmask5:4 = zext((FM5:1 == 1)* 0xf) << 8;\n\tmask6:4 = zext((FM6:1 == 1)* 0xf) << 4;\n\tmask7:4 = zext((FM7:1 == 1)* 0xf);\n\t\n\tmask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7;\n\t\n\ttmp1:4 = fB:4;\n\ttmp2:4 = (tmp & ~mask) | (tmp1 & mask);\n\tunpackFPSCR(tmp2);\n\tcr1flags();\n}\n\n#mtfsfi 10,3\t\t0xfc 00 01 0c\n:mtfsfi crfD,IMM\tis $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=0 \n{\n\ttmp:4 = 0;\n\tpackFPSCR(tmp);\n\tshift:1 = 28-(crfD*4);\n\tmask:4 = 0xf << shift;\n\ttmp1:4 = IMM << shift;\n\ttmp2:4 = (tmp & ~mask) | tmp1;\n\tunpackFPSCR(tmp2);\n}\n\n#mtfsfi. 10,3\t\t0xfc 00 01 0d\n:mtfsfi. crfD,IMM\tis $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=1\n{\n\ttmp:4 = 0;\n\tpackFPSCR(tmp);\n\tshift:1 = 28-(crfD*4);\n\tmask:4 = 0xf << shift;\n\ttmp1:4 = IMM << shift;\n\ttmp2:4 = (tmp & ~mask) | tmp1;\n\tunpackFPSCR(tmp2);\n\tcr1flags();\n}\n\n# This instruction is not exclusive to 64 bit processors, per page 1405 of the PowerISA manual.\n# Prior to the Power ISA introduction, PowerPC architecture had 32-bit versions of the MSR in 32-bit implementations.\n# Since this instruction requires 64-bit processsors, it is currently restricted to 64 bit machines.\n# mtmsrd varies from processor to processor. This version is consistent with PowerISA v2.07B\n@ifdef BIT_64\n#mtmsrd r0,0\t\t0x7c 00 01 64\n:mtmsrd S,0\t\tis $(NOTVLE) & OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=178 & BIT_0=0\n{\n\tlocal bit59:$(REGISTER_SIZE) = (S >> 4) & 1;\t#bit 59\n\tlocal bit58:$(REGISTER_SIZE) = (S >> 5) & 1;\t#bit 58\n\tlocal bit49:$(REGISTER_SIZE) = (S >> 14) & 1;\t#bit 49\n\tlocal bit48:$(REGISTER_SIZE) = (S >> 15) & 1;\t#bit 48\n\t\n\tlocal bits2931:$(REGISTER_SIZE) = zext(S[32,3]); #bits 29-31\n\tlocal mbits2931:$(REGISTER_SIZE) = zext(MSR[32,3]); #bits 29-31\n\tlocal cond = (mbits2931 != 0x2)|(bits2931 != 0);\n\tbits2931 = (zext(cond) * bits2931) + (zext(!cond) * mbits2931);\n\tlocal mask:$(REGISTER_SIZE) =0xeffffff8ffff6fce;\n\ttmp:8 = S & mask; #preserves (RS) 0:2 4:40 42:47 49:50 52:57 60:62\n\n\ttmp = tmp | (bits2931) << 32;\n\ttmp = tmp | ((bit48 | bit49) << 15); # MSR 48 <- (RS) 48 | (RS) 49\n\ttmp = tmp | ((bit58 | bit49) << 5); # MSR 58 <- (RS) 58 | (RS) 49\n\ttmp = tmp | ((bit59 | bit49) << 4); # MSR 59 <- (RS) 59 | (RS) 49\n\tMSR = (MSR & ~mask) | tmp;\n}\n\n#mtmsrd r0,1\t\t0x7c 01 01 64\n:mtmsrd S,1\t\tis $(NOTVLE) & OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=178 & BIT_0=0 \n{\n\tmask:$(REGISTER_SIZE) = 0x8002;\n\tMSR = (MSR & ~mask) | (S & mask);\n}\n@endif\n\nCRM_val: crmval is CRM [crmval = CRM+0;] {export *[const]:1 crmval;}\n#mtocrf 10,r0\t\t0x7c 21 01 20\n:mtocrf CRM_val,S\tis OP=31 & S & BIT_20=1 & CRM_val & CRM0 & CRM1 & CRM2 & CRM3 & CRM4 & CRM5 & CRM6 & CRM7 & BIT_11=0 & XOP_1_10=144 & BIT_0=0 \n{\n\ttmp:$(REGISTER_SIZE) = (S >> 28) & 0xf;\n\tcr0 = (cr0 * (CRM_val != 128)) | (tmp:1 * (CRM_val == 128));\n\n\ttmp = (S >> 24) & 0xf;\n\tcr1 = (cr1 * (CRM_val != 64)) | (tmp:1 * (CRM_val == 64));\n\n\ttmp = (S >> 20) & 0xf;\n\tcr2 = (cr2 * (CRM_val != 32)) | (tmp:1 * (CRM_val == 32));\n\n\ttmp = (S >> 16) & 0xf;\n\tcr3 = (cr3 * (CRM_val != 16)) | (tmp:1 * (CRM_val == 16));\n\n\ttmp = (S >> 12) & 0xf;\n\tcr4 = (cr4 * (CRM_val != 8)) | (tmp:1 * (CRM_val == 8));\n\n\ttmp = (S >> 8) & 0xf;\n\tcr5 = (cr5 * (CRM_val != 4)) | (tmp:1 * (CRM_val == 4));\n\n\ttmp = (S >> 4) & 0xf;\n\tcr6 = (cr6 * (CRM_val != 2)) | (tmp:1 * (CRM_val == 2));\n\n\ttmp = S & 0xf;\n\tcr7 = (cr7 * (CRM_val != 1)) | (tmp:1 * (CRM_val == 1));\n}\n\n### is this pcode correct on 64-bit bridge?\n#mtsr sr0,r0\t0x7c 00 01 a4\n:mtsr SR,S\t\tis $(NOTVLE) & OP=31 & S & SR & BIT_20=0 & B & BITS_11_15=0 & XOP_1_10=210 & BIT_0=0\n{\n@ifdef BIT_64\n\tSR = S:4;\n@else\n\tSR = S;\n@endif\n}\n\n#mtsrd sr0,r0\t0x7c 00 0 a4\n:mtsrd SR,S\tis $(NOTVLE) & OP=31 & S & BIT_20=0 & SR & BITS_11_15=0 & XOP_1_10=82 & BIT_0=0\n{\n\tSR = S:4;\n}\n\n#mtsrdin r0,r0\t0x7c 00 00 e4\n:mtsrdin S,B\t\tis $(NOTVLE) & OP=31 & S & BITS_16_20=0 & B & XOP_1_10=114 & BIT_0=0\n{\n\tlocal tmp = (B >> 28) & 0xf;\n\t*[register]:4 ($(SEG_REGISTER_BASE)+tmp:4) = S:4;\n}\n\n### is this pcode correct on 64-bit bridge?\n#mtsrin r0,r0\t0x7c 00 01 e4\n:mtsrin S,B\t\tis $(NOTVLE) & OP=31 & S & BITS_16_20=0 & B & XOP_1_10=242 & BIT_0=0\n{\n@ifdef BIT_64\n\ttmp:4 = (B:4 >> 28);\n@else\n\ttmp:$(REGISTER_SIZE) = (B >> 28);\n@endif\n\t*[register]:4 ($(SEG_REGISTER_BASE)+tmp) = S;\n}\n\n@ifdef BIT_64\n#mulhd r0,r0\t0x7c 00 00 92\n:mulhd D,A,B\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=73 & Rc=0\n{\n\ttmp:16 = sext(A) * sext(B);\n\tD = tmp(8);\n}\n#mulhd. r0,r0\t0x7c 00 00 93\n:mulhd. D,A,B\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=73 & Rc=1\n{\n\ttmp:16 = sext(A) * sext(B);\n\tD = tmp(8);\n\tcr0flags(D);\n}\n\n#mulhdu r0,r0\t0x7c 00 00 12\n:mulhdu D,A,B\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=9 & Rc=0\n{\n\ttmp:16 = zext(A) * zext(B);\n\tD = tmp(8);\n}\n#mulhdu. r0,r0\t0x7c 00 00 13\n:mulhdu. D,A,B\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=9 & Rc=1\n{\n\ttmp:16 = zext(A) * zext(B);\n\tD = tmp(8);\n\tcr0flags(D);\n}\n\n@endif\n\n#mulhw\tr0,r0,r0\t0x7c 00 00 96\n:mulhw D,A,B\t\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=75 & Rc=0\n{\n@ifdef BIT_64\n\ttmp:8 = sext(A:4) * sext(B:4);\n\ttmp2:4 = tmp(4);\n\tD = zext(tmp2);\n@else\n\ttmp:8 = sext(A) * sext(B);\n\tD = tmp(4);\n@endif\n}\n\n#mulhw.\tr0,r0,r0\t0x7c 00 00 97\n:mulhw. D,A,B\t\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=75 & Rc=1\n{\n@ifdef BIT_64\n\ttmp:8 = sext(A:4) * sext(B:4);\n\ttmp2:4 = tmp(4);\n\tD = zext(tmp2);\n@else\n\ttmp:8 = sext(A) * sext(B);\n\tD = tmp(4);\n@endif\n\tcr0flags(D);\n}\n\n#mulhwu\tr0,r0,r0\t0x7c 00 00 16\n:mulhwu D,A,B\t\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=11 & Rc=0\t\n{ \n@ifdef BIT_64\n\ttmp:8 = zext(A:4) * zext(B:4);\n\ttmp2:4 = tmp(4);\n\tD=zext(tmp2);\n@else\n\ttmp:8 = zext(A) * zext(B);\n\tD = tmp(4);\n@endif \n}\n#mulhwu.\tr0,r0,r0\t0x7c 00 00 17\n:mulhwu. D,A,B\t\tis OP=31 & D & A & B & BIT_10=0 & XOP_1_9=11 & Rc=1\t\n{ \n@ifdef BIT_64\n\ttmp:8 = zext(A:4) * zext(B:4);\n\ttmp2:4 = tmp(4);\n\tD=zext(tmp2);\n@else\n\ttmp:8 = zext(A) * zext(B);\n\tD = tmp(4);\n@endif \n\tcr0flags(D);\n}\n\n@ifdef BIT_64\n#mulld r0, r0, r0\t0x7C 00 01 D2\n:mulld D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=233 & Rc=0\n{\n\ttmp:16 = sext(A) * sext(B);\n\tD = tmp:8;\n} \n\n#mulld. r0, r0, r0\t0x7C 00 01 D3\n:mulld. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=233 & Rc=1\n{\n\ttmp:16 = sext(A) * sext(B);\n\tD = tmp:8;\n\tcr0flags(D);\n}\n\n#mulldo r0, r0, r0\t0x7C 00 05 D2\n:mulldo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=233 & Rc=0\n{\n\ttmp:16 = sext(A) * sext(B);\n\tD = tmp:8;\n\tmulOverflow128(tmp);\n}\n\n#mulldo. r0, r0, r0\t0x7C 00 05 D3\n:mulldo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=233 & Rc=1\n{\n\ttmp:16 = sext(A) * sext(B);\n\tD = tmp:8;\n\tmulOverflow128(tmp);\n\tcr0flags(D);\n}\n\n@endif\n\n#mulli r0,r0,r0\t\t0x1C 00 00 00\n:mulli D,A,SIMM\t\tis $(NOTVLE) & OP=7 & D & A & SIMM\t\t\t\t\n{\n \tD = A * SIMM;\n}\n\n#mullw r0,r0,r0\t\t0x7C 00 01 D6\n:mullw D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=235 & Rc=0\t\n{\n@ifdef BIT_64\n\tD = sext(A:4) * sext(B:4);\n@else\n\tD = A*B;\n@endif\n}\n\n#mullw. r0,r0,r0\t\t0x7C 00 01 D7\n:mullw. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=235 & Rc=1\t\n{ \n@ifdef BIT_64\n\tD = sext(A:4) * sext(B:4);\n@else\n\tD = A*B;\n@endif\n\tcr0flags(D);\n}\n\n#mullwo r0,r0,r0\t\t0x7C 00 05 D6\n:mullwo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=235 & Rc=0\t\n{ \t\n@ifdef BIT_64\n\tD = sext(A:4) * sext(B:4);\n\tmulOverflow64(D);\n@else\n\ttmp:8 = sext(A) * sext(B);\n\tmulOverflow64(tmp);\n\tD = tmp:4;\n@endif\t\n}\n\n#mullwo. r0,r0,r0\t\t0x7C 00 05 D7\n:mullwo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=235 & Rc=1\t\n{\n@ifdef BIT_64\n\tD = sext(A:4) * sext(B:4);\n\tmulOverflow64(D);\n@else\n\ttmp:8 = sext(A) * sext(B);\n\tmulOverflow64(tmp);\n\tD = tmp:4;\n@endif\n\tcr0flags(D);\n}\n\n#nand r0,r0,r0 0x7C 00 03 B8\n:nand A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=476 & Rc=0\n{\n\tA = ~(S & B);\n}\n\n#nand. r0,r0,r0 0x7C 00 03 B9\n:nand. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=476 & Rc=1\n{\n\tA = ~(S & B);\n\tcr0flags( A );\n}\n\n#neg r0,r0\t\t0x7C 00 00 D0\n:neg D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=104 & Rc=0\n{\n\tD = -A;\n}\n\n#neg. r0,r0\t\t0x7C 00 00 D1\n:neg. D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=104 & Rc=1\n{\n\tD = -A;\n\tcr0flags( D );\n}\n\n#nego r0,r0\t\t0x7C 00 04 D0\n:nego D,A\t\tis $(NOTVLE) & OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=104 & Rc=0\n{\n\tsubOverflow(A,1);\n\tD = -A;\n}\n\n#nego. r0,r0\t\t0x7C 00 04 D1\n:nego. D,A\t\tis OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=104 & Rc=1\n{\t\n\tsubOverflow(A,1);\n\tD = -A;\n\tcr0flags( D );\n}\n\n#nor r0,r0,r0\t\t0x7C 00 00 F8\n:nor A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=124 & Rc=0\n{\n\tA = ~(S | B);\n}\n\n#nor. r0,r0,r0\t\t0x7C 00 00 F9\n:nor. A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=124 & Rc=1\n{\n\tA = ~(S | B);\n\tcr0flags(A);\n}\n\n#or r0,r0,r0\t\t0x7C 00 03 78\n:or A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=444 & Rc=0\n{\n\tA = (S | B);\n}\n\n#or. r0,r0,r0\t\t0x7C 00 03 79\n:or. A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=444 & Rc=1\n{\n\tA = (S | B);\n\tcr0flags(A);\n}\n\n#orc r0,r0,r0\t\t0x7C 00 03 38\n:orc A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=412 & Rc=0\n{\n\tA = S | ~B;\n}\n\n#orc. r0,r0,r0\t\t0x7C 00 03 39\n:orc. A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=412 & Rc=1\n{\n\tA = S | ~B;\n\tcr0flags(A);\n}\n\n#ori r0,r0,r0\t\t0x60 00 00 00\n:ori A,S,UIMM\tis $(NOTVLE) & OP=24 & A & S & UIMM\n{\n\tA = S | UIMM;\n}\n\n#oris r0,r0,r0\t\t0x64 00 00 00\n:oris A,S,UIMM\tis $(NOTVLE) & OP=25 & A & S & UIMM\n{\n\tA = S | (UIMM << 16);\n}\n\n#rfid\t0x4c 00 00 24 \n:rfid\t\tis $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=18 & BIT_0=0\t\n{ \n\tMSR = returnFromInterrupt(MSR, SRR1);\n\tlocal ra = SRR0;\n\treturn[ra];\n}\n\n@ifdef BIT_64\n#rldcl r0,r0,r0,0\t0x78 00 00 10\n:rldcl A,S,B,MB\tis $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=8 & Rc=0\n{ \n\tshift:$(REGISTER_SIZE) = B & 0x3f;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & (0xffffffffffffffff >> MB);\n}\n#rldcl. r0,r0,r0,0\t0x78 00 00 11\n:rldcl. A,S,B,MB\tis $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=8 & Rc=1\n{ \n\tshift:$(REGISTER_SIZE) = B & 0x3f;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & (0xffffffffffffffff >> MB);\n\tcr0flags(A);\n}\n#rldcr r0,r0,r0,0\t0x78 00 00 12\n:rldcr A,S,B,MB\tis $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=9 & Rc=0 & rotmask_Z\n{ \n\tshift:$(REGISTER_SIZE) = B & 0x3f;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & rotmask_Z;\n}\n#rldcr. r0,r0,r0,0\t0x78 00 00 13\n:rldcr. A,S,B,MB\tis $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=9 & Rc=1 & rotmask_Z\n{ \n\tshift:$(REGISTER_SIZE) = B & 0x3f;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & rotmask_Z; \n\tcr0flags(A);\n}\n\n#rldic r0,r0,r0,0\t0x78 00 00 08\n:rldic A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=2 & Rc=0 & rotmask_SH\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & rotmask_SH;\n}\n#rldic. r0,r0,r0,0\t0x78 00 00 09\n:rldic. A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=2 & Rc=1 & rotmask_SH\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & rotmask_SH;\n\tcr0flags(A);\n}\n\n#rldicl r0,r0,r0,0\t0x78 00 00 00\n:rldicl A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=0 & Rc=0\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & (0xffffffffffffffff >> MB);\n}\n#rldicl. r0,r0,r0,0\t0x78 00 00 01\n:rldicl. A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=0 & Rc=1\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & (0xffffffffffffffff >> MB);\n\tcr0flags(A);\n}\n#rldicr r0,r0,r0,0\t0x78 00 00 04\n:rldicr A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=1 & Rc=0\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & (0xffffffffffffffff << (63-MB));\n}\n#rldicr. r0,r0,r0,0\t0x78 00 00 05\n:rldicr. A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=1 & Rc=1\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = tmp & (0xffffffffffffffff << (63-MB));\n\tcr0flags(A);\n}\n#rldimi r0,r0,r0,0\t0x78 00 00 0c\n:rldimi A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=3 & Rc=0 & rotmask_SH\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = (tmp & rotmask_SH) | (A & ~rotmask_SH);\n}\n#rldimi. r0,r0,r0,0\t0x78 00 00 0d\n:rldimi. A,S,SH,MB\tis $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=3 & Rc=1 & rotmask_SH\n{ \n\tshift:4 = SH;\n\ttmp:$(REGISTER_SIZE)=(S<>(64-shift));\n\tA = (tmp & rotmask_SH) | (A & ~rotmask_SH);\n\tcr0flags(A);\n}\n@endif\n\n\n\n#rlwimi r0,r0,0,0,0\t\t0x50 00 00 00\n:rlwimi A,S,SHL,MBL,ME\tis $(NOTVLE) & OP=20 & S & A & SHL & MBL & ME & Rc=0 & rotmask \n{ \n\tshift:1 = SHL;\n@ifdef BIT_64\n\ttmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff);\n\ttmp2:$(REGISTER_SIZE) = (tmp<>(64-shift));\n\tA = (tmp2 & rotmask) | (A & ~(rotmask));\n@else\n\ttmp = (S<>(32-shift));\n\tA = (tmp & rotmask) | (A & ~rotmask);\n@endif\n}\n\n#rlwimi. r0,r0,0,0,0\t\t0x50 00 00 01\n:rlwimi. A,S,SHL,MBL,ME is $(NOTVLE) & OP=20 & S & A & SHL & MBL & ME & Rc=1 & rotmask\n{ \n\tshift:1 = SHL;\n@ifdef BIT_64\n\ttmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff);\n\ttmp2:$(REGISTER_SIZE) = (tmp<>(64-shift));\n\tA = (tmp2 & rotmask) | (A & ~(rotmask));\n@else\n\ttmp = (S<>(32-shift));\n\tA = (tmp & rotmask) | (A & ~rotmask);\n@endif\n\tcr0flags(A);\n}\n\n#rlwinm r0,r0,0,0,0\t\t0x54 00 00 00\n:rlwinm A,S,SHL,MBL,ME\tis $(NOTVLE) & OP=21 & S & A & SHL & MBL & ME & Rc=0 & rotmask\n{ \n\tshift:1 = SHL;\n@ifdef BIT_64\n\ttmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff);\n\ttmp2:$(REGISTER_SIZE) = (tmp<>(64-shift));\n\tA = tmp2 & rotmask;\n@else\n\ttmp = (S<>(32-shift));\n\tA = (tmp & rotmask);\n@endif\n}\n\n#rlwinm. r0,r0,0,0,0\t\t0x54 00 00 01\n:rlwinm. A,S,SHL,MBL,ME is $(NOTVLE) & OP=21 & S & A & SHL & MBL & ME & Rc=1 & rotmask\n{ \n\tshift:1 = SHL;\n@ifdef BIT_64\n\ttmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff);\n\ttmp2:$(REGISTER_SIZE) = (tmp<>(64-shift));\n\tA = tmp2 & rotmask;\n@else\n\ttmp = (S<>(32-shift));\n\tA = (tmp & rotmask);\n@endif\n\tcr0flags(A);\n}\n\n#rlwnm r0,r0,0,0,0\t\t0x5C 00 00 00\n:rlwnm A,S,B,MBL,ME\tis $(NOTVLE) & OP=23 & S & A & B & MBL & ME & Rc=0 & rotmask\n{ \t\n\tshift:$(REGISTER_SIZE) = B & 0x1f;\n@ifdef BIT_64\n\ttmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff);\n\ttmp2:$(REGISTER_SIZE) = (tmp<>(64-shift));\n\tA = tmp2 & rotmask;\n@else\n\ttmp = (S<>(32-shift));\n\tA = (tmp & rotmask);\n@endif\n}\n\n#rlwnm. r0,r0,0,0,0\t\t0x5C 00 00 01\n:rlwnm. A,S,B,MBL,ME\tis $(NOTVLE) & OP=23 & S & A & B & MBL & ME & Rc=1 & rotmask\n{ \n\tshift:$(REGISTER_SIZE) = B & 0x1f;\n@ifdef BIT_64\n\ttmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff);\n\ttmp2:$(REGISTER_SIZE) = (tmp<>(64-shift));\n\tA = tmp2 & rotmask;\n@else\n\ttmp = (S<>(32-shift));\n\tA = (tmp & rotmask);\n@endif\n\tcr0flags(A);\n}\n\n#sc \t\t0x44 00 00 02\n:sc\tLEV\t\t\t\tis $(NOTVLE) & OP=17 & BITS_12_25=0 & LEV & BITS_2_4=0 & BIT_1=1 & BIT_0=0\n{\n\tsyscall();\n}\n\n#slbia\t\t0x7C 00 03 E4\n:slbia\t\t\t\tis $(NOTVLE) & OP=31 & BITS_11_25=0 & XOP_1_10=498 & BIT_0=0\n{\n\tslbInvalidateAll();\n}\n\n#slbie r0\t0x7C 00 03 64\n:slbie\tB\t\t\tis $(NOTVLE) & OP=31 & BITS_16_20=0 & B & XOP_1_10=434 & BIT_0=0\n{\n\tslbInvalidateEntry();\n}\n\n#slbmfee r0,r0\t0x7C 00 07 26\n:slbmfee D,B\t\tis $(NOTVLE) & OP=31 & D & BITS_16_20=0 & B & XOP_1_10=915 & BIT_0=0\n{\n\tslbMoveFromEntryESID();\n}\n\n#slbmfev r0,r0\t0x7C 00 06 A6\n:slbmfev D,B\t\tis $(NOTVLE) & OP=31 & D & BITS_16_20=0 & B & XOP_1_10=851 & BIT_0=0\n{\n\tslbMoveFromEntryVSID();\n}\n\n#slbmte r0,r0 \t0x7C 00 03 24\n:slbmte S,B\t\tis $(NOTVLE) & OP=31 & S & BITS_16_20=0 & B & XOP_1_10=402 & BIT_0=0\n{\n\tslbMoveToEntry();\n}\n\n@ifdef BIT_64\n#sld r0,r0,r0 \t\t0x7C 00 00 36\n:sld A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=27 & Rc=0\n{\n\tA = S << (B & 0x7f);\n}\n\n#sld. \t\t0x7C 00 00 37\n:sld. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=27 & Rc=1\n{\n\tA = S << (B & 0x7f);\n\tcr0flags(A);\n}\n@endif\n\n#slw r0,r0,r0 \t0x7C 00 00 30\n:slw A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=24 & Rc=0\n{\n@ifdef BIT_64\n\tshift:4 = B:4 & 0x3f;\n\ttmp:4 = S:4 << shift;\n\tA = zext(tmp);\n@else\n\tshift = B & 0x3f;\n\tA = S << shift;\n@endif\n}\n\n\n#slw. r0,r0,r0 \t0x7C 00 00 31\n:slw. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=24 & Rc=1\n{\n@ifdef BIT_64\n\tshift:4 = B:4 & 0x3f;\n\ttmp:4 = S:4 << shift;\n\tA = zext(tmp);\n@else\n\tshift = B & 0x3f;\n\tA = S << shift;\n@endif\n\tcr0flags(A);\n}\n\n@ifdef BIT_64\n#srad r0,r0,r0\t0x7C 00 06 34\n:srad A,S,B\t\t\tis OP=31 & A & S & B & XOP_1_10=794 & Rc=0\n{\n\ttmp:$(REGISTER_SIZE) = B & 0x7f;\n\tshiftCarry(S,tmp);\n\tA = S s>> tmp;\n}\n\n#srad. r0,r0,r0\t0x7C 00 06 35\n:srad. A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=794 & Rc=1\n{\n\ttmp:$(REGISTER_SIZE) = B & 0x7f;\n\tshiftCarry(S,tmp);\n\tA = S s>> tmp;\n\tcr0flags(A);\n}\n\n#sradi r0,r0,r0\t0x7C 00 06 74\n:sradi A,S,SH\t\tis OP=31 & A & S & SH & XOP_2_10=413 & Rc=0\n{\n\tshiftCarry(S,SH);\n\tA = S s>> SH;\n}\n\n#sradi. r0,r0,r0\t0x7C 00 06 75\n:sradi. A,S,SH\t\tis OP=31 & A & S & SH & XOP_2_10=413 & Rc=1\n{\n\tshiftCarry(S,SH);\n\tA = S s>> SH;\n}\n\n@endif\n\n\n#sraw r0,r0,r0\t0x7C 00 06 30\n:sraw A,S,B\t\t\tis OP=31 & A & S & B & XOP_1_10=792 & Rc=0\n{\n@ifdef BIT_64\n\tshift:4 = B:4 & 0x3f;\n\tshiftCarry(S:4,shift);\n\ttmp2:4 = S:4 s>> shift;\n\tA = sext(tmp2);\n@else\n\tshift = B & 0x3f;\n\tshiftCarry(S,shift);\n\tA = S s>> shift;\n@endif\n}\n#sraw. r0,r0,r0\t0x7C 00 06 31\n:sraw. A,S,B\t\tis OP=31 & A & S & B & XOP_1_10=792 & Rc=1\n{\n@ifdef BIT_64\n\tshift:4 = B:4 & 0x3f;\n\tshiftCarry(S:4,shift);\n\ttmp2:4 = S:4 s>> shift;\n\tA = sext(tmp2);\n@else\n\tshift = B & 0x3f;\n\tshiftCarry(S,shift);\n\tA = S s>> shift;\n@endif\n\tcr0flags(A);\n}\n\n#srawi r0,r0,r0\t0x7C 00 06 70\n:srawi A,S,SHL\t\tis OP=31 & A & S & SHL & XOP_1_10=824 & Rc=0\n{\n@ifdef BIT_64\n\tshift:4 = SHL;\n\tshiftCarry(S:4,shift);\n\ttmp2:4 = S:4 s>> shift;\n\tA = sext(tmp2);\n@else\n\tshiftCarry(S,SHL);\n\tA = S s>> SHL;\n@endif\n}\n#srawi. r0,r0,r0\t0x7C 00 06 71\n:srawi. A,S,SHL\t\tis OP=31 & A & S & SHL & XOP_1_10=824 & Rc=1\n{\n@ifdef BIT_64\n\tshift:4 = SHL;\n\tshiftCarry(S:4,shift);\n\ttmp2:4 = S:4 s>> shift;\n\tA = sext(tmp2);\n@else\n\tshiftCarry(S,SHL);\n\tA = S s>> SHL;\n@endif\n\tcr0flags(A);\n}\n\n@ifdef BIT_64\n#srd r0,r0,r0 \t\t0x7C 00 04 36\n:srd A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=539 & Rc=0\n{\n\tA = S >> (B & 0x7f);\n}\n\n#srd. \t\t0x7C 00 04 37\n:srd. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=539 & Rc=1\n{\n\tA = S >> (B & 0x7f);\n\tcr0flags(A);\n}\n@endif\n\n#srw r0,r0,r0 \t0x7C 00 04 30\n:srw A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=536 & Rc=0\n{\n@ifdef BIT_64\n\tshift:4 = B:4 & 0x3f;\n\ttmp:4 = S:4 >> shift;\n\tA = zext(tmp);\n@else\n\tshift = B & 0x3f;\n\tA = S >> shift;\n@endif\n}\n\n\n#srw. r0,r0,r0 \t0x7C 00 04 31\n:srw. A,S,B\t\tis OP=31 & S & A & B & XOP_1_10=536 & Rc=1\n{\n@ifdef BIT_64\n\tshift:4 = B:4 & 0x3f;\n\ttmp:4 = S:4 >> shift;\n\tA = zext(tmp);\n@else\n\tshift = B & 0x3f;\n\tA = S >> shift;\n@endif\n\tcr0flags(A);\n}\n\n\n\n#stb\tr0,3(0)\t\t0x98 00 00 00\n#stb\tr0,3(r2)\t0x98 02 00 00\n:stb\tS,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=38 & S & dPlusRaOrZeroAddress\n{\n\t*:1(dPlusRaOrZeroAddress) = S:1;\n}\n\n#stbu\tr0,3(0)\t\t0x9c 00 00 00\n#stbu\tr0,3(r2)\t0x9c 02 00 00\n:stbu\tS,dPlusRaAddress\tis $(NOTVLE) & OP=39 & S & dPlusRaAddress & A\n{\n\t*:1(dPlusRaAddress) = S:1;\n\tA = dPlusRaAddress;\n}\n\n#stbux\tr0,r2,r0\t0x7c 00 01 ee\t\t### WARNING the B in this definition is different from manual - I think the manual is wrong\n:stbux\tS,A,B\t\t\tis OP=31 & S & A & B & XOP_1_10=247 & BIT_0=0\n{\n\ttmp:$(REGISTER_SIZE) = A+B; # S may be same register as A\n\t*tmp = S:1; # So do store before updating A\n\tA = tmp;\n}\n\n#stbx\tr0,r2,r0\t0x7c 00 01 ae\t\t### WARNING the B in this definition is different from manual - I think the manual is wrong\n:stbx\tS,RA_OR_ZERO,B\tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=215 & BIT_0=0\n{\n\t*(RA_OR_ZERO+B) = S:1;\n}\n\n@ifdef BIT_64\n#std r0,8(0)\t0xf8 00 00 08\t\n#std r0,8(r2)\t0xf8 02 00 08\t\n:std S,dsPlusRaOrZeroAddress \tis $(NOTVLE) & OP=62 & S & dsPlusRaOrZeroAddress & BITS_0_1=0\n{\n\t*:8(dsPlusRaOrZeroAddress) = S;\n}\n\n#Special case when saving r2 to stack prior to function call (for inline call stub case)\n#std r2,0x28(r1)\t\n:std r2,dsPlusRaOrZeroAddress \tis $(NOTVLE) & OP=62 & S=2 & r2 & A=1 & SIMM_DS=0xa & dsPlusRaOrZeroAddress & BITS_0_1=0\n{\n\tr2Save = r2;\n\t*:8(dsPlusRaOrZeroAddress) = r2;\n}\n\n#stdcx. r0,8(0)\t0x7c 00 01 AD\t\n:stdcx. S,RA_OR_ZERO,B \tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=214 & BIT_0=1\n{\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tif (RESERVE == 0) goto inst_next;\n\t*[ram]:8 EA = storeDoubleWordConditionalIndexed(S,RA_OR_ZERO,B);\n\t# set when a stwcx. or stdcx. successfully completes\n\tcr0flags(0:$(REGISTER_SIZE));\n}\n\n#stdu r0,8(0)\t0xf8 00 00 01\t\n#stdu r0,8(r2)\t0xf8 02 00 01\t\n:stdu S,dsPlusRaAddress \tis $(NOTVLE) & OP=62 & S & A & dsPlusRaAddress & BITS_0_1=1\n{\n\t*:8(dsPlusRaAddress) = S;\n\tA = dsPlusRaAddress;\n}\n\n#stdux\tr0,r2,r0\t0x7c 00 01 6a\n:stdux\tS,A,B\tis OP=31 & S & A & B & XOP_1_10=181 & BIT_0=0\n{\n\tlocal ea:$(REGISTER_SIZE) = A+B;\n\t*:8(ea) = S;\n\tA = ea;\n}\n\n#stdx\tr0,r2,r0\t0x7c 00 01 2a\n:stdx\tS,RA_OR_ZERO,B\tis OP=31 & S & B & RA_OR_ZERO & XOP_1_10=149 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\t*:8(ea) = S;\n}\n\n@endif\n\n#stfd fr0,8(0)\t0xD8 00 00 08\t\n#stfd fr0,8(r2)\t0xD8 02 00 08\n:stfd fS,dPlusRaOrZeroAddress\t\tis $(NOTVLE) & OP=54 & fS & dPlusRaOrZeroAddress\n{\n\t*:8(dPlusRaOrZeroAddress) = fS;\n}\n\n#stfdu fr0,8(0)\t0xDC 00 00 08\t\n#stfdu fr0,8(r2)\t0xDC 02 00 08\n:stfdu fS,dPlusRaAddress \tis $(NOTVLE) & OP=55 & fS & dPlusRaAddress & A\n{\n\tea:$(REGISTER_SIZE) = dPlusRaAddress;\n\t*:8(ea) = fS;\n\tA = ea;\n}\n\n#stfdux\tfr0,r2,r0\t0x7C 00 05 EE\n:stfdux\tfS,A,B\tis $(NOTVLE) & OP=31 & fS & A & B & XOP_1_10=759 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A+B;\n\t*:8(ea) = fS;\n\tA = ea;\n}\n\n#stfdx fr0,r0,r0\t0x7C 00 05 AE\n:stfdx fS,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=727 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\t*:8(ea) = fS;\n}\n\n#stfiwx fr0,r0,r0\t0x7C 00 07 AE\n:stfiwx fS,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=983 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\t*:4(ea) = fS:4;\n}\n\n#stfs fr0,8(0)\t0xD0 00 00 08\n#stfs fr0,8(r2)\t0xD0 02 00 08\n:stfs fS,dPlusRaOrZeroAddress\t\tis $(NOTVLE) & OP=52 & fS & dPlusRaOrZeroAddress\n{\n\ttmp:4 = float2float(fS);\t\n\t*:4(dPlusRaOrZeroAddress) = tmp;\n}\n\n#stfsu fr0,8(0) \t0xD4 00 00 08\n#stfsu fr0,8(r2)\t0xD4 02 00 08\n:stfsu fS,dPlusRaAddress\t\t\tis $(NOTVLE) & OP=53 & fS & dPlusRaAddress & A\n{\n\ttmp:4 = float2float(fS);\t\n\t*:4(dPlusRaAddress) = tmp;\n\tA = dPlusRaAddress;\n}\n\n#stfsux fr0,r0,r0\t0x7C 00 05 6E\n:stfsux fS,A,B\tis $(NOTVLE) & OP=31 & fS & B & A & XOP_1_10=695 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A + B;\n\ttmp:4 = float2float(fS);\n\t*:4(ea) = tmp;\n\tA = ea;\n}\n\n#stfsx fr0,r0,r0\t0x7C 00 05 2E\n:stfsx fS,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=663 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\ttmp:4 = float2float(fS);\n\t*:4(ea) = tmp;\n}\n\n#sth r0,r0\t\t\t0xB0 00 00 00\n:sth S,dPlusRaOrZeroAddress\t\tis $(NOTVLE) & OP=44 & S & dPlusRaOrZeroAddress\n{\n\t*:2(dPlusRaOrZeroAddress) = S:2;\n}\n\n#sthbrx r0,r0,r0\t0x7C 00 07 2C\n:sthbrx S,RA_OR_ZERO,B\t\t\tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=918 & BIT_0=0\n{\n\ttmp:2 = zext(S:1) <<8;\n\ttmp2:2 = S:2 >>8;\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*:2(ea) = tmp2 | tmp;\n}\n\n#sthu r0,r0\t\t\t0xB4 00 00 00\n:sthu S,dPlusRaAddress\t\tis $(NOTVLE) & OP=45 & S & A & dPlusRaAddress\n{\n\t*:2(dPlusRaAddress) = S:2;\n\tA = dPlusRaAddress;\n}\n\n#sthux r0,r0,r0\t\t0x7C 00 03 6E\n:sthux S,A,B\t\t\t\tis OP=31 & S & A & B & XOP_1_10=439 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A + B;\n\t*:2(ea) = S:2;\n\tA = ea;\n}\n\n#sthx r0,r0,r0\t\t0x7C 00 03 2E\n:sthx S,RA_OR_ZERO,B\t\tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=407 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*:2(ea) = S:2;\n}\n\n#### \n#stm instruction\n@include \"stmwInstructions.sinc\"\n\n@include \"stswiInstructions.sinc\"\n#stswi r0,r0,0 \t\t0x7c 00 05 aa\n#:stswi S,A,NB\t\tis $(NOTVLE) & OP=31 & S & A & NB & XOP_1_10=725 & BIT_0=0\n#{\n#\ttmp:1 = NB;\n#\tstoreString(S,A,tmp);\n#}\n\n#stswx r0,r0,0\t\t0x7c 00 05 2a\ndefine pcodeop stswxOp;\n:stswx S,RA_OR_ZERO,B\t\tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=661 & BIT_0=0\n{\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:1 EA = stswxOp(S,RA_OR_ZERO,B);\n}\n\n#stw r0,r0,0\t\t0x90 00 00 00\n:stw S,dPlusRaOrZeroAddress\t\tis $(NOTVLE) & OP=36 & S & dPlusRaOrZeroAddress\n{\n@ifdef BIT_64\n\t*:4(dPlusRaOrZeroAddress) = S:4;\n@else\n\t*:4(dPlusRaOrZeroAddress) = S;\n@endif\n}\n\n#stwbrx r0,r0,0\t\t0x7c 00 05 2c\n:stwbrx S,RA_OR_ZERO,B\t\tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=662 & BIT_0=0\n{\n@ifdef BIT_64\n\tvalue:4 = S:4;\n@else\n\tvalue:$(REGISTER_SIZE) = S;\n@endif\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\ttmp1:4 = value << 24;\n\ttmp2:4 = (value << 8) & 0xff0000;\n\ttmp3:4 = (value >> 8) & 0x00ff00;\n\ttmp4:4 = value >> 24;\n\t*:4(ea) = tmp1 | tmp2 | tmp3 | tmp4;\t\n}\n\n#stwcx. r0,8(0)\t0x7c 00 01 2D\t\n:stwcx. S,RA_OR_ZERO,B \tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=150 & BIT_0=1\n{\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tif (RESERVE == 0) goto inst_next;\n\t*[ram]:4 EA = storeWordConditionalIndexed(S,RA_OR_ZERO,B);\n\t# set when a stwcx. or stdcx. successfully completes\n\tcr0flags(0:$(REGISTER_SIZE));\n}\n\n#stwu r0,r0\t\t\t0x94 00 00 00\n:stwu S,dPlusRaAddress\t\tis $(NOTVLE) & OP=37 & S & A & dPlusRaAddress\n{\n@ifdef BIT_64\n\t*:4(dPlusRaAddress) = S:4;\n@else\n\t*:4(dPlusRaAddress) = S;\n@endif\n\tA = dPlusRaAddress;\n}\n\n#stwux r0,r0,r0\t\t0x7C 00 01 6E\n:stwux S,A,B\t\t\t\tis OP=31 & S & A & B & XOP_1_10=183 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = A + B;\n@ifdef BIT_64\n\t*:4(ea) = S:4;\n@else\n\t*:4(ea) = S;\n@endif\n\tA = ea;\n}\n\n#stwx r0,r0,r0\t\t0x7C 00 01 2E\n:stwx S,RA_OR_ZERO,B\t\tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=151 & BIT_0=0\n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n@ifdef BIT_64\n\t*:4(ea) = S:4;\n@else\n\t*:4(ea) = S;\n@endif\n}\n\n\n#subf r0,r0,r0 0x7c 00 00 50\n:subf D,A,B\t\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=40 & Rc=0\n{\n\tD = B - A;\n}\n\n#subf. r0,r0,r0 0x7c 00 00 51 \n:subf. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=40 & Rc=1\t\n{ \t\n\tD = B - A;\n\tcr0flags(D);\n}\n\n#subfo r1,r2,r3 0x7c 00 04 50\n:subfo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=40 & Rc=0\n{\n\tsubOverflow(B,A);\n\tD = B - A;\n}\n\n#subfo. r1,r2,r3 0x7c 00 04 51\n:subfo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=40 & Rc=1\n{ \t\n\tsubOverflow(B,A);\n\tD = B - A;\n\tcr0flags(D);\n}\n\n#subfc r0,r0,r0 0x7c 00 00 10\n:subfc D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=8 & Rc=0\n{\t\n\txer_ca = (A <= B);\n\tD = B - A;\n}\n\n#subfc. r0,r0,r0 0x7c 00 00 11\n:subfc. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=8 & Rc=1\t\n{ \t\n\txer_ca = (A <= B);\n\tD = B - A;\n\tcr0flags(D);\n}\n\n#subfco r0,r0,r0 0x7c 00 04 10\n:subfco D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=8 & Rc=0\n{ \n\txer_ca = (A <= B);\n\tsubOverflow(B,A);\n\tD = B - A;\n}\n\n#subfco. r0,r0,r0 0x7c 00 04 11\n:subfco. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=8 & Rc=1\n{ \t\n\txer_ca = (A <= B);\n\tsubOverflow( B, A );\n\tD = B - A;\n\tcr0flags(D);\n}\n\n#subfe r0,r0,r0 0x7c 00 01 10\n:subfe D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=136 & Rc=0\n{\t\n\ttmp:$(REGISTER_SIZE) = A + zext(!xer_ca);\n\tsubExtendedCarry(B,A);\n\tD = B - tmp;\n}\n\n#subfe. r0,r0,r0 0x7c 00 01 11\n:subfe. D,A,B\t\tis OP=31 & D & A & B & OE=0 & XOP_1_9=136 & Rc=1\t\n{ \t\n\ttmp:$(REGISTER_SIZE) = A + zext(!xer_ca);\n\tsubExtendedCarry(B,A);\n\tD = B - tmp;\n\tcr0flags(D);\n}\n\n#subfeo r0,r0,r0 0x7c 00 05 10\n:subfeo D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=136 & Rc=0\n{ \n\ttmp:$(REGISTER_SIZE) = zext(!xer_ca)+A;\n\tsubExtendedOverflow(B,A);\n\tsubExtendedCarry(B,A);\n\tD = B - tmp;\n}\n\n#subfeo. r0,r0,r0 0x7c 00 05 11\n:subfeo. D,A,B\t\tis OP=31 & D & A & B & OE=1 & XOP_1_9=136 & Rc=1\n{ \t\n\ttmp:$(REGISTER_SIZE) = zext(!xer_ca)+A;\n\tsubExtendedOverflow(B,A);\n\tsubExtendedCarry(B,A);\n\tD = B - tmp;\n\tcr0flags(D);\n}\n\n#subfic r0,r0,2 0x20 00 00 02\n:subfic D,A,SIMM\t\tis $(NOTVLE) & OP=8 & D & A & SIMM\n{\n\txer_ca = !(SIMM\n b = (63 - (i*8+7));\n tmp = (S >> (63 - (i*8+7))); b = tmp & 1; # GetBit\n s = s ^ b;\n \t i = i + 1;\n if (i < 8) goto ;\n A = s;\n} \n\n# PowerISA II: 3.3.12 Fixed-Point Logical Instructions\n# CMT: Compare Bytes\n# FORM: X-form\n# binutils: 476.d: dc: 7c 83 2b f8 cmpb r3,r4,r5\n# binutils: 476.d: e0: 7c 83 2b f8 cmpb r3,r4,r5\n# binutils: a2.d: 104: 7d 6a 63 f8 cmpb r10,r11,r12\n# binutils: power6.d: 20: 7c 83 2b f8 cmpb r3,r4,r5\n# binutils: power7.d: 90: 7c 83 2b f8 cmpb r3,r4,r5\n# name\t cmpb\t code\t 7c0003f8\t mask\t ff0700fc00000000\t flags\t @POWER6 @476 @A2 \t operands\t31\t 3b\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:cmpb S,A,B is $(NOTVLE) & OP=31 & S & A & B & XOP_1_10=508 &\t\tBIT_0=0 { # PCODE-YES\n tmpS:8 = 0;\n tmpB:8 = 0;\n val:8 = 0;\n zero:8 = 0;\n ones:8 = 0xff;\n \n # Unrolled the loop\n\ttmpS = (S >> 56) & 0xFF; # get next S byte\n\ttmpB = (B >> 56) & 0xFF; # get next B byte\n\tval = (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = (S >> 48) & 0xFF; # get next S byte\n\ttmpB = (B >> 48) & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = (S >> 40) & 0xFF; # get next S byte\n\ttmpB = (B >> 40) & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = (S >> 32) & 0xFF; # get next S byte\n\ttmpB = (B >> 32) & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = (S >> 24) & 0xFF; # get next S byte\n\ttmpB = (B >> 24) & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = (S >> 16) & 0xFF; # get next S byte\n\ttmpB = (B >> 16) & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = (S >> 8) & 0xFF; # get next S byte\n\ttmpB = (B >> 8) & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n\ttmpS = S & 0xFF; # get next S byte\n\ttmpB = B & 0xFF; # get next B byte\n\tval = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero);\n A = val;\n} \n# PowerISA II: 3.3.12 Fixed-Point Logical Instructions\n# CMT: Bit Permute Doubleword [Category: Embedded.Phased-in, Server]\n# FORM: X-form\n# binutils: a2.d: fc: 7d 6a 61 f8 bpermd r10,r11,r12\n# binutils: power7.d: d8: 7e 27 d9 f8 bpermd r7,r17,r27\n# name\t bpermd\t code\t 7c0001f8\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t31\t 3b\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop BitPermuteDoubleword;\n:bpermd A,S,B is $(NOTVLE) & OP=31 & S & A & B & XOP_1_10=252 & BIT_0=0 { \n\tBitPermuteDoubleword(A,S,B);\n} \n\n# PowerISA II: 3.3.12 Fixed-Point Logical Instructions\n# CMT: Population Count Words [Category: Server] [Category: Embedded.Phased-In]\n# FORM: X-form\n# binutils: a2.d: 64c: 7d 6a 02 f4 popcntw r10,r11\n# binutils: power7.d: dc: 7e 8a 02 f4 popcntw r10,r20\n# name\t popcntw\t code\t 7c0002f4\t mask\t ffff00fc00000000\t flags\t @POWER7 @A2 \t operands\t31\t 3b\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:popcntw A,S is $(NOTVLE) & OP=31 & S & A & XOP_1_10=378 & Rc & BITS_11_15=0 {\n\tlocal tmp1:4 = S(0);\n\ttmp1 = popcount(tmp1);\n\tlocal tmp2:4 = S(4);\n\ttmp2 = popcount(tmp2);\n\tA = (zext(tmp2) << 32) + zext(tmp1);\n} \n\n# PowerISA II: 3.3.12 Fixed-Point Logical Instructions\n# CMT: Population Count Bytes\n# FORM: X-form\n# binutils: 476.d: 618: 7c 83 00 f4 popcntb r3,r4\n# binutils: a2.d: 644: 7d 6a 00 f4 popcntb r10,r11\n# name\t popcntb\t code\t 7c0000f4\t mask\t ffff00fc00000000\t flags\t @POWER5 \t operands\t31\t 3b\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:popcntb A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=122 & BIT_0=0 { \n\tlocal i:8 = 0;\n\tlocal tmp:8 = 0;\n\tlocal tmpb:1 = 0;\n\tlocal mask:8 = 0xff;\n\t\n\t\ttmp = (S >> (i*8));\n\t\ttmpb = tmp(0);\n\t\ttmpb = popcount(tmpb);\n\t\tA = (A & ~(mask)) + (zext(tmpb) << (i*8));\n\t\tmask = mask << 8;\n \ti = i + 1;\n\tif (i < 8) goto ;\n} \n\n\n# PowerISA II: 3.3.12 Fixed-Point Logical Instructions\n# CMT: Parity Word\n# FORM: X-form\n# binutils: 476.d: 61c: 7c 83 01 34 prtyw r3,r4\n# binutils: a2.d: 654: 7d 6a 01 34 prtyw r10,r11\n# binutils: power6.d: 10: 7c 83 01 34 prtyw r3,r4\n# binutils: power7.d: 80: 7c 83 01 34 prtyw r3,r4\n# name\t prtyw\t code\t 7c000134\t mask\t ffff00fc00000000\t flags\t @POWER6 @476 @A2 \t operands\t31\t 3b\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:prtyw A,S is $(NOTVLE) & OP=31 & S & A & BITS_11_15=0 & XOP_1_10=154 & BIT_0=0 { \n\tlocal temp:8 = S;\n\tA[0,32] = zext(((popcount(temp & 0x01010101:8)) & 1:8) == 1:8);\n\tA[32,32] = zext(((popcount(temp & 0x0101010100000000:8)) & 1:8) == 1:8);\n} \n\n# =======================================================================\n\n# PowerISA II: 4.4.1 Fixed-Point Load and Store Caching Inhibited Instructions\n# CMT: Load Word and Zero Caching Inhibited Indexed\n# binutils: power6.d: 2c: 7d 4b 66 2a lwzcix r10,r11,r12\n# binutils: power7.d: 94: 7d 4b 66 2a lwzcix r10,r11,r12\n# name\t lwzcix\t code\t 7c00062a\t mask\t ff0700fc00000000\t flags\t @POWER6 \t operands\t 3b\t32\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop LoadWordAndZeroCachingInhibited;\n:lwzcix TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & XOP_1_10=789 & \tBIT_0=0 { # PCODE-YES\n tmp:8 = *(A + B);\n tmp = tmp << 32;\n TH = tmp;\n}\n\n# =======================================================================\n\n# PowerISA II: 3.3.14 Binary Coded Decimal (BCD) Assist Instructions [Category: Embedded.Phased-in, Server]\n# CMT: Convert Declets To Binary Coded Decimal\n# FORM: X-form\n# binutils: power6.d: f0: 7d 6a 02 34 cdtbcd r10,r11\n# name\t cdtbcd\t code\t 7c000234\t mask\t ffff00fc00000000\t flags\t @POWER6 \t operands\t31\t 3b\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop ConvertDecletsToBinaryCodedDecimal;\n:cdtbcd A,S is $(NOTVLE) & OP=31 & S & A & XOP_1_10=282 & \t\tBITS_11_15=0 & BIT_0=0 { ConvertDecletsToBinaryCodedDecimal(S,A); } \n\n# PowerISA II: 3.3.14 Binary Coded Decimal (BCD) Assist Instructions [Category: Embedded.Phased-in, Server]\n# CMT: Add and Generate Sixes\n# FORM: XO-form\n# binutils: power6.d: f4: 7d 4b 60 94 addg6s r10,r11,r12\n# name\t addg6s\t code\t 7c000094\t mask\t ff0700fc00000000\t flags\t @POWER6 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop AddAndGenerateSixes;\n:addg6s TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & XOP_1_9=74 &\t\t\tBIT_10=0 & BIT_0=0 { # PCODE-YES\n\tAddAndGenerateSixes(TH,A,B);\n}\n\n# ==========================================================================\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: b8: 7d 4b 63 56 divwe r10,r11,r12\n# name\t divwe\t code\t 7c000356\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divwe TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & XOP_1_9=427 & Rc=0 {\n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a s/ b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n TH = tmp;\n}\n\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: bc: 7d 6c 6b 57 divwe. r11,r12,r13\n# name\t divwe.\t code\t 7c000357\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divwe. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & XOP_1_9=427 & Rc=1 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a s/ b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n TH = tmp;\n\n cr0flags(TH);\n}\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: c0: 7d 8d 77 56 divweo r12,r13,r14\n# name\t divweo\t code\t 7c000756\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divweo TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & XOP_1_9=427 & Rc=0 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a s/ b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n divOverflow(A,B);\n TH = tmp;\n}\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: c4: 7d ae 7f 57 divweo. r13,r14,r15\n# name\t divweo.\t code\t 7c000757\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop DivideWordExtended4;\n:divweo. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & XOP_1_9=427 & Rc=1 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a s/ b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n divOverflow(A,B);\n TH = tmp;\n\n cr0flags(TH);\n}\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: c8: 7d 4b 63 16 divweu r10,r11,r12\n# name\t divweu\t code\t 7c000316\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divweu TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & Rc=0 & XOP_1_9=395 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a / b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n TH = tmp;\n}\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: cc: 7d 6c 6b 17 divweu. r11,r12,r13\n# name\t divweu.\t code\t 7c000317\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divweu. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & Rc=1 & XOP_1_9=395 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a / b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n TH = tmp;\n\n cr0flags(TH);\n}\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended Unsigned [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: d0: 7d 8d 77 16 divweuo r12,r13,r14\n# name\t divweuo\t code\t 7c000716\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divweuo TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & Rc=0 & XOP_1_9=395 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a / b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n divOverflow(A,B);\n TH = tmp;\n}\n\n# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions\n# CMT: Divide Word Extended Unsigned [Category: Server] [Category: Embedded.Phased-In]\n# FORM: XO-form\n# binutils: power7.d: d4: 7d ae 7f 17 divweuo. r13,r14,r15\n# name\t divweuo.\t code\t 7c000717\t mask\t ff0700fc00000000\t flags\t @POWER7 @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:divweuo. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & Rc=1 & XOP_1_9=395 { \n tmp:8 = 0;\n\n\t# A high 4 bytes to a\n\ttmp = tmp >> 32;\n\ta:4 = tmp:4;\n\n # B high 4 bytes to b\n\ttmp = tmp >> 32;\n\tb:4 = tmp:4;\n\n # C \n c:4 = (a / b);\n\n # C low 4 bytes to TH high 4 bytes\n tmp = zext(c);\n tmp = tmp << 32;\n divOverflow(A,B);\n TH = tmp;\n\n cr0flags(TH);\n}\n\n# =======================================================================\n\n# PowerISA II: 3.3.12.1 64-bit Fixed-Point Logical Instructions [Category: 64-Bit]\n# CMT: Population Count Doubleword [Category: Server.64-bit] [Category: Embedded.64-bit.Phased-In]\n# FORM: X-form\n# binutils: a2.d: 648: 7d 6a 03 f4 popcntd r10,r11\n# binutils: power7.d: e0: 7e 8a 03 f4 popcntd r10,r20\n# name\t popcntd\t code\t 7c0003f4\t mask\t ffff00fc00000000\t flags\t @POWER7 @A2 \t operands\t31\t 3b\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:popcntd A,S is $(NOTVLE) & OP=31 & S & A & XOP_1_10=506 & Rc & BITS_11_15=0 { \n\tA = popcount(S);\n} \n\n# =======================================================================\n\n# PowerISA II: 3.3.4.1 64-Bit Load and Store with Byte Reversal Instructions [Category: 64-bit]\n# CMT: Load Doubleword Byte-Reverse Indexed\n# FORM: X-form\n# Category: 64\n# binutils: a2.d: 418: 7d 4b 64 28 ldbrx r10,r11,r12\n# binutils: cell.d: 40: 7c 00 0c 28 ldbrx r0,0,r1\n# binutils: cell.d: 44: 7c 01 14 28 ldbrx r0,r1,r2\n# binutils: power7.d: e4: 7e 95 b4 28 ldbrx r20,r21,r22\n# name\t ldbrx\t code\t 7c000428\t mask\t ff0700fc00000000\t flags\t @POWER7 @CELL @A2 \t operands\t 3b\t32\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop LoadDoublewordByteReverseIndexed;\n:ldbrx D,A,B is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=532 & Rc { D = LoadDoublewordByteReverseIndexed(D,A,B); }\n\n# ======================================================================\n\n# PowerISA II: 4.4.2 Load and Reserve and Store Conditional Instructions\n# CMT: Store Byte Conditional Indexed\n# FORM: X-form\n# binutils: power7.d: 164: 7d 4b 65 6d stbcx. r10,r11,r12\n# name\t stbcx.\t code\t 7c00056d\t mask\t ff0700fc00000000\t flags\t @POWER7 \t operands\t 3b\t32\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop StoreByteConditionalIndexed;\n:stbcx. S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=694 & Rc=1 { \n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:1 EA = StoreByteConditionalIndexed(S,RA_OR_ZERO,B);\n\tsetCrBit(cr0, 2, 1);\t\t\n}\n\n# ======================================================================\n\n# PowerISA II: 5.4.1 Move To/From System Register Instructions\n# CMT: Move From Device Control Register Indexed [Category: Embedded.Device Control]\n# FORM: X-form\n# binutils: 476.d: 49c: 7c 85 02 06 mfdcrx r4,r5\n# binutils: a2.d: 520: 7d 4b 02 06 mfdcrx r10,r11\n# binutils: booke.d: 28: 7c 85 02 06 mfdcrx r4,r5\n# binutils: booke_xcoff.d: 24: 7c 85 02 06 mfdcrx r4,r5\n# name\t mfdcrx\t code\t 7c000206\t mask\t ff0700fc00000000\t flags\t @476 @BOOKE @A2 \t operands\t 3b\t31\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop MoveFromDeviceControlRegisterIndexed;\n:mfdcrx D,A is OP=31 & D & A & XOP_1_9=259 & Rc=0 { # \n\tMoveFromDeviceControlRegisterIndexed(D,A);\n}\n\n\n# PowerISA II: 5.4.1 Move To/From System Register Instructions\n# CMT: Move To Device Control Register Indexed [Category: Embedded.Device Control]\n# FORM: X-form\n# binutils: 476.d: 4cc: 7c e6 03 06 mtdcrx r6,r7\n# binutils: a2.d: 568: 7d 6a 03 06 mtdcrx r10,r11\n# binutils: booke.d: 30: 7c e6 03 06 mtdcrx r6,r7\n# binutils: booke_xcoff.d: 2c: 7c e6 03 06 mtdcrx r6,r7\n# binutils: 4cc:\t7c e6 03 06 \tmtdcrx r6,r7\n# name\t mtdcrx\t code\t 7c000306\t mask\t ff0700fc00000000\t flags\t @476 @BOOKE @A2 \t operands\t31\t 3b\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop MoveToDeviceControlRegisterIndexed;\n:mtdcrx A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=387 & BIT_0=0 { MoveToDeviceControlRegisterIndexed(S,A); } # \n\n# ========================================================================\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Data Cache Block Flush by External PID\n# FORM: X-form\n# binutils: a2.d: 154: 7c 0a 58 fe dcbfep r10,r11\n# binutils: e500mc.d: 9c: 7c 01 10 fe dcbfep r1,r2\n# name\t dcbfep\t code\t 7c0000fe\t mask\t ff07e0ff00000000\t flags\t @E500MC @A2 \t operands\t31\t38\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop DataCacheBlockFlushByExternalPID;\n:dcbfep A,B is OP=31 & A & B & XOP_1_10=127 & BIT_0=0 & BITS_21_25=0 { # \n\tDataCacheBlockFlushByExternalPID(A,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Data Cache Block Store by External PID\n# FORM: X-form\n# binutils: a2.d: 168: 7c 0a 58 7e dcbstep r10,r11\n# binutils: e500mc.d: 98: 7c 1f 00 7e dcbstep r31,r0\n# name\t dcbstep\t code\t 7c00007e\t mask\t ff07e0ff00000000\t flags\t @E500MC @A2 \t operands\t31\t38\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop DataCacheBlockStoreByExternalPID;\n:dcbstep A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=63 & BIT_0=0 { # \n\tDataCacheBlockStoreByExternalPID(A,B);\n}\n\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Data Cache Block set to Zero by External PID\n# FORM: X-form\n# binutils: a2.d: 198: 7c 0a 5f fe dcbzep r10,r11\n# binutils: e500mc.d: a8: 7c 0b 67 fe dcbzep r11,r12\n# name\t dcbzep\t code\t 7c0007fe\t mask\t ff07e0ff00000000\t flags\t @E500MC @A2 \t operands\t31\t38\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop DataCacheBlockSetToZeroByExternalPID;\n:dcbzep A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=1023 & BIT_0=0 { \n\tDataCacheBlockSetToZeroByExternalPID(A,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Instruction Cache Block Invalidate by External PID\n# FORM: X-form\n# binutils: a2.d: 3b8: 7c 0a 5f be icbiep r10,r11\n# binutils: e500mc.d: 10: 7c 09 57 be icbiep r9,r10\n# name\t icbiep\t code\t 7c0007be\t mask\t ff07e0ff00000000\t flags\t @E500MC @A2 \t operands\t31\t38\t0\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop InstructionCacheBlockInvalidateByExternalPID;\n:icbiep A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=991 & BIT_0=0 { \n\tInstructionCacheBlockInvalidateByExternalPID(A,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Load Floating-Point Double by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 438: 7e 8a 5c be lfdepx f20,r10,r11\n# binutils: e500mc.d: 50: 7d ae 7c be lfdepx f13,r14,r15\n# name\t lfdepx\t code\t 7c0004be\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t22\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:lfdepx fT,RA_OR_ZERO,B is OP=31 & fT & B & RA_OR_ZERO & XOP_1_10=607 & BIT_0=0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tfT = *:8(ea);\n}\n\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Store Byte by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 700: 7d 4b 61 be stbepx r10,r11,r12\n# binutils: e500mc.d: 54: 7e 11 91 be stbepx r16,r17,r18\n# name\t stbepx\t code\t 7c0001be\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop StoreByteByExternalProcessIDIndexed;\n:stbepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=223 & BIT_0=0 { # \n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:1 EA = StoreByteByExternalProcessIDIndexed(S,RA_OR_ZERO,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Store Halfword by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 784: 7d 4b 63 3e sthepx r10,r11,r12\n# binutils: e500mc.d: 58: 7e 74 ab 3e sthepx r19,r20,r21\n# name\t sthepx\t code\t 7c00033e\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop StoreHalfwordByExternalProcessIDIndexed;\n:sthepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=415 & BIT_0=0 { # \n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:2 EA = StoreHalfwordByExternalProcessIDIndexed(S,RA_OR_ZERO,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Store Word by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 7b0: 7d 4b 61 3e stwepx r10,r11,r12\n# binutils: e500mc.d: 5c: 7e d7 c1 3e stwepx r22,r23,r24\n# name\t stwepx\t code\t 7c00013e\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop StoreWordByExternalProcessIDIndexed;\n:stwepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=159 & BIT_0=0 { # \n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:4 EA = StoreWordByExternalProcessIDIndexed(S,RA_OR_ZERO,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Store Doubleword Byte-Reverse Indexed\n# FORM: X-form\n# binutils: a2.d: 71c: 7d 4b 65 28 stdbrx r10,r11,r12\n# binutils: cell.d: 48: 7c 00 0d 28 stdbrx r0,0,r1\n# binutils: cell.d: 4c: 7c 01 15 28 stdbrx r0,r1,r2\n# binutils: power7.d: e8: 7e 95 b5 28 stdbrx r20,r21,r22\n# name\t stdbrx\t code\t 7c000528\t mask\t ff0700fc00000000\t flags\t @POWER7 @CELL @A2 \t operands\t 3b\t32\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop StoreDoublewordByteReverseIndexed;\n:stdbrx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=660 & BIT_0=0 { # \n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:8 EA = StoreDoublewordByteReverseIndexed(S,RA_OR_ZERO,B);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Store Doubleword Byte-Reverse Indexed\n# FORM: X-form\n# binutils: a2.d: 724: 7d 4b 61 3a stdepx r10,r11,r12\n# binutils: e500mc.d: 60: 7f 3a d9 3a stdepx r25,r26,r27\n# name\t stdepx\t code\t 7c00013a\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\ndefine pcodeop StoreDoublewordByteReverseIndexed1;\n:stdepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=157 & BIT_0=0 { # \n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:8 EA = StoreDoublewordByteReverseIndexed1(S,RA_OR_ZERO,B);\n}\n\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Load Byte by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d 3ec: 7d 4b 60 be lbepx r10,r11,r12\n# binutils: e500mc.d 40: 7c 22 18 be lbepx r1,r2,r3\n# name\t lbepx\t code\t 7c0000be\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n# Note: no support for context modeling here\n:lbepx\tD,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=95 & BIT_0=0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = zext(*:1(ea));\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Data Cache Block Touch by External PID\n# FORM: X-form\n# binutils: a2.d: 174: 7d 4b 62 7e dcbtep r10,r11,r12\n# binutils: e500mc.d: a4: 7c c7 42 7e dcbtep r6,r7,r8\n# NOTE: BITS_21_25 => TH (register)\n# name\t dcbtep\t code\t 7c00027e\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n# No PCODE necessary\ndefine pcodeop DataCacheBlockTouchByExternalPID2;\n:dcbtep TH,RA_OR_ZERO,B is OP=31 & TH & RA_OR_ZERO & B & XOP_1_10=319 & BIT_0=0 { \n\tDataCacheBlockTouchByExternalPID2(TH,RA_OR_ZERO,B);\n}\n\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Load Doubleword by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 41c: 7d 4b 60 3a ldepx r10,r11,r12\n# binutils: e500mc.d: 4c: 7d 4b 60 3a ldepx r10,r11,r12\n# name\t ldepx\t code\t 7c00003a\t mask\t ff0700fc00000000\t flags\t @E500MC @A2 \t operands\t 3b\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n# Note: no support for context modeling here\n:ldepx\tD,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=29 & BIT_0=0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = *:8(ea);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Load Word by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 4c8: 7d 4b 60 3e lwepx r10,r11,r12\n# binutils: e500mc.d: 48: 7c e8 48 3e lwepx r7,r8,r9\n# Note: no support for context modeling here\n:lwepx\tD,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=31 & BIT_0=0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = *:4(ea);\n}\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Store Floating-Point Double by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 740: 7e 8a 5d be stfdepx f20,r10,r11\n# binutils: e500mc.d: 64: 7f 9d f5 be stfdepx f28,r29,r30\n# NOTE: BITS_21_25 => FRS (float register) => fS\n# Note: no support for context modeling here\n:stfdepx fS,RA_OR_ZERO,B is OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=735 & BIT_0=0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\t*:8(ea) = fS;\n}\n\n\n# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID]\n# CMT: Load Halfword by External Process ID Indexed\n# FORM: X-form\n# binutils: a2.d: 480: 7d 4b 62 3e lhepx r10,r11,r12\n# binutils: e500mc.d: 44: 7c 85 32 3e lhepx r4,r5,r6\n# Note: no support for context modeling here\n:lhepx\tD,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=287 & BIT_0=0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tD = zext(*:2(ea));\n}\n\n# ========================================================================\n\n# PowerISA II: 3.3.15.2 Move To/From System Registers [Category: Embedded]\n# CMT: Move From Device Control Register User-mode Indexed [Category: Embedded.Device Control]\n# FORM: X-form\n# binutils: 476.d: 498: 7c 64 02 46 mfdcrux r3,r4\ndefine pcodeop MoveFromDeviceControlRegisterUserModeIndexed;\n:mfdcrux RT,A is OP=31 & RT & A & BITS_11_15=0 & XOP_1_10=291 & BIT_0=0 \n{\n\n@ifdef BIT_64\n\ttmp:8 = dcr000 + (A * $(REGISTER_SIZE));\n\tRT = *[register]:8 (tmp:4);\n@else\n\ttmp = dcr000 + (A * $(REGISTER_SIZE));\n\tRT = *[register]:4 (tmp);\n@endif\n\n}\n\n# PowerISA II: 3.3.15.2 Move To/From System Registers [Category: Embedded]\n# CMT: Move To Device Control Register User-mode Indexed [Category: Embedded.Device Control]\n# FORM: X-form\n# binutils: 476.d: 4c8: 7c 83 03 46 mtdcrux r3,r4\n:mtdcrux S,A is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=419 & BIT_0=0 \n{ \n@ifdef BIT_64\n\ttmp:8 = dcr000 + (A * $(REGISTER_SIZE));\n\t*[register]:8 (tmp:4) = S;\n@else\n\ttmp = dcr000 + (A * $(REGISTER_SIZE));\n\t*[register]:4 (tmp) = S;\n@endif\n\n}\n\n\n# ========================================================================\n\n# PowerISA II: 4.6.5 Floating-Point Move Instructions\n# CMT: Floating Copy Sign\n# FORM: X-form\n# binutils: 476.d: 1f0: fd 4b 60 10 fcpsgn f10,f11,f12\n# binutils: a2.d: 268: fe 95 b0 10 fcpsgn f20,f21,f22\n:fcpsgn fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=8 & Rc=0 \n{\n fT = ( fB & 0x7FFFFFFFFFFFFFFF ) | ( fA & 0x8000000000000000 );\n}\n\n# PowerISA II: 4.6.5 Floating-Point Move Instructions\n# CMT: Floating Copy Sign\n# FORM: X-form\n# binutils: 476.d: 1f4: fd 4b 60 11 fcpsgn\\. f10,f11,f12\n# binutils: a2.d: 264: fe 95 b0 11 fcpsgn\\. f20,f21,f22\n:fcpsgn. fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=8 & Rc=1 \n{\n fT = ( fB & 0x7FFFFFFFFFFFFFFF ) | ( fA & 0x8000000000000000 );\n cr1flags();\n}\n# ========================================================================\n\n# PowerISA II: 4.6.2 Floating-Point Load Instructions\n# CMT: Load Floating-Point as Integer Word Algebraic Indexed \n# FORM: X-form\n# binutils: 476.d: 350: 7d 43 26 ae lfiwax f10,r3,r4\n# binutils: a2.d: 44c: 7e 8a 5e ae lfiwax f20,r10,r11\ndefine pcodeop LoadFloatingPointAsIntegerWordAlgebraicIndexed;\n:lfiwax fT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fT & RA_OR_ZERO & B & XOP_1_10=855 & BIT_0=0 \n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n fT = sext( *:4(ea) );\n}\n\n# PowerISA II: 4.6.2 Floating-Point Load Instructions\n# CMT: Load Floating-Point as Integer Word and Zero Indexed [Category: Floating-Point.Phased-in]\n# FORM: X-form\n# bintutils: a2.d: 450: 7e 8a 5e ee lfiwzx f20,r10,r11\n# bintutils: power7.d: ec: 7d 40 56 ee lfiwzx f10,0,r10\n# bintutils: power7.d: f0: 7d 49 56 ee lfiwzx f10,r9,r10\ndefine pcodeop LoadFloatingPointAsIntegerWordAndZeroIndexed;\n:lfiwzx fT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fT & RA_OR_ZERO & B & XOP_1_10=887 & BIT_0=0 \n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n fT = zext( *:4(ea) );\n}\n\n# =======================================================================\n\n# PowerISA II: A.1 Embedded Cache Initialization [Category: Embedded.Cache Initialization]\n# CMT: Instruction Cache Invalidate\n# FORM: X-form\n# binutils: 476.d: 31c: 7c 20 07 8c ici 1\n# binutils: a2.d: 3d8: 7d 40 07 8c ici 10\n# Note: Using CT, but limited to 4 bits, not 5 (PPC bit 6 is 0 and is a don't care anyhow as CT is unused)\n# No PCODE for this function\ndefine pcodeop InstructionCacheInvalidate;\n:ici CT is OP=31 & CT & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=966 & BIT_0=0 \n{\n InstructionCacheInvalidate();\n}\n\n# PowerISA II: A.1 Embedded Cache Initialization [Category: Embedded.Cache Initialization]\n# CMT: Data Cache Invalidate\n# FORM: X-form\n# Note: Using CT, but limited to 4 bits, not 5 (PPC bit 6 is 0 and is a don't care anyhow as CT is unused)\n# No PCODE for this function\n# binutils: 476.d: 180: 7c 20 03 8c dci 1\n# binutils: a2.d: 1a8: 7d 40 03 8c dci 10\ndefine pcodeop DataCacheInvalidate;\n:dci CT is OP=31 & CT & BITS_11_20=0 & BITS_11_15=0 & XOP_1_10=454 & BIT_0=0 \n{\n DataCacheInvalidate();\n}\n\n# =======================================================================\n\n# PowerISA II: 4.3.1 Instruction Cache Instructions\n# CMT: Instruction Cache Block Touch [Category: Embedded]\n# FORM: X-form\n# binutils: 476.d: 308: 7c a8 48 2c icbt 5,r8,r9\n# binutils: a2.d: 3bc: 7c 0a 58 2c icbt r10,r11\n# binutils: a2.d: 3c0: 7c ea 58 2c icbt 7,r10,r11\n# binutils: booke.d: 0: 7c a8 48 2c icbt 5,r8,r9\n# binutils: booke_xcoff.d: 8: 7c a8 48 2c icbt 5,r8,r9\n# Note: Using CT, but limited to 4 bits, not 5 (PPC bit 6 is 0 and is a don't care anyhow as CT is unused)\n# No PCODE for this function\ndefine pcodeop InstructionCacheBlockTouch;\n:icbt CT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & CT & RA_OR_ZERO & B & XOP_1_10=22 & BIT_0=0 \n{\n InstructionCacheBlockTouch(RA_OR_ZERO,B);\n}\n\n# ======================================================================\n\n# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions\n# CMT: Floating Reciprocal Square Root Estimate [Single]\n# FORM: A-form\n# binutils: 476.d: 2d0: ed c0 78 34 frsqrtes f14,f15\n# binutils: a2.d: 374: ee 80 a8 34 frsqrtes f20,f21\n# binutils: a2.d: 37c: ee 80 a8 34 frsqrtes f20,f21\n# binutils: a2.d: 384: ee 81 a8 34 frsqrtes f20,f21,1\n# binutils: power7.d: 184: ed c0 78 34 frsqrtes f14,f15\n# NOTE: binutils allows BITS_16_20=1 but manual says BITS_16_20=0. We take the manuals side. (pg 136)\n:frsqrtes fT,fB is $(NOTVLE) & OP=59 & fT & fB & BITS_16_20=0 & BITS_6_10=0 & XOP_1_5=26 & Rc=0 \n{\n # divide 1 by square root of fB to create reciprocal\n tmp1:8 = 0x3FF0000000000000;\n fT = tmp1 f/ sqrt( fB );\n setFPDivFlags(tmp1,fB,fT);\n}\n\n# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions\n# CMT: Floating Reciprocal Square Root Estimate [Single]\n# FORM: A-form\n# binutils: 476.d: 2d4: ed c0 78 35 frsqrtes. f14,f15\n# binutils: a2.d: 378: ee 80 a8 35 frsqrtes. f20,f21\n# binutils: a2.d: 380: ee 80 a8 35 frsqrtes. f20,f21\n# binutils: a2.d: 388: ee 81 a8 35 frsqrtes. f20,f21,1\n# binutils: power7.d: 188: ed c0 78 35 frsqrtes. f14,f15\n# NOTE: binutils allows BITS_16_20=1 but manual says BITS_16_20=0. We take the manuals side. (pg 136)\ndefine pcodeop FloatingReciprocalSquareRootEstimate1;\n:frsqrtes. fT,fB is $(NOTVLE) & OP=59 & fT & fB & BITS_16_20=0 & BITS_6_10=0 & XOP_1_5=26 & Rc=1 \n{\n # divide 1 by square root of fB to create reciprocal \n tmp1:8 = 0x3FF0000000000000;\n fT = tmp1 f/ sqrt( fB );\n setFPDivFlags(tmp1,fB,fT);\n cr1flags();\n}\n\n# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions\n# CMT: Floating Reciprocal Estimate [Single]\n# FORM: A-form\n# binutils: 476.d: 290: fd c0 78 30 fre f14,f15\n# binutils: a2.d: 308: fe 80 a8 30 fre f20,f21\n# binutils: a2.d: 310: fe 80 a8 30 fre f20,f21\n# binutils: a2.d: 318: fe 81 a8 30 fre f20,f21,1\n# binutils: power7.d: 16c: fd c0 78 30 fre f14,f15\n# NOTE: binutils allows BITS_16_20!=0 but manual says BITS_16_20=0. We take the manuals side. (pg 135)\n:fre fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=0 \n{\n # divide 1 by fB to create reciprocal\n tmp1:8 = 0x3FF0000000000000;\n fT = tmp1 f/ fB;\n setFPDivFlags(tmp1,fB,fT);\n}\n\n# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions\n# CMT: Floating Reciprocal Estimate [Single]\n# FORM: A-form\n# binutils: 476.d: 294: fd c0 78 31 fre. f14,f15\n# binutils: a2.d: 304: fe 80 a8 31 fre. f20,f21\n# binutils: a2.d: 30c: fe 80 a8 31 fre. f20,f21\n# binutils: a2.d: 314: fe 81 a8 31 fre. f20,f21,1\n# binutils: power7.d: 170: fd c0 78 31 fre. f14,f15\n# NOTE: binutils allows BITS_16_20!=0 but manual says BITS_16_20=0. We take the manuals side. (pg 135)\n:fre. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=1 \n{\n # divide 1 by fB to create reciprocal\n tmp1:8 = 0x3FF0000000000000;\n fT = tmp1 f/ fB;\n setFPDivFlags(tmp1,fB,fT);\n cr1flags();\n}\n# ======================================================================\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Minus\n# FORM: X-form\n# binutils: 476.d: 2a0: fd 40 5b d0 frim f10,f11\n# binutils: a2.d: 338: fe 80 ab d0 frim f20,f21\n:frim fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=488 & Rc=0 \n{\n fT = floor( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Minus\n# FORM: X-form\n# binutils: 476.d: 2a4: fd 40 5b d1 frim. f10,f11\n# binutils: a2.d: 334: fe 80 ab d1 frim. f20,f21\n:frim. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=488 & Rc=1 \n{\n fT = floor( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n cr1flags();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Nearest\n# FORM: X-form\n# binutils: 476.d: 2a8: fd 40 5b 10 frin f10,f11\n# binutils: a2.d: 340: fe 80 ab 10 frin f20,f21\n:frin fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=392 & Rc=0 \n{\n fT = round( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Nearest\n# FORM: X-form\n# binutils: 476.d: 2ac: fd 40 5b 11 frin. f10,f11\n# binutils: a2.d: 33c: fe 80 ab 11 frin. f20,f21\n:frin. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=392 & Rc=1 \n{\n fT = round( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n cr1flags();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Plus\n# FORM: X-form\n# binutils: 476.d: 2b0: fd 40 5b 90 frip f10,f11\n# binutils: a2.d: 348: fe 80 ab 90 frip f20,f21\n:frip fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=456 & Rc=0 \n{\n fT = ceil( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Plus\n# FORM: X-form\n# binutils: 476.d: 2b4: fd 40 5b 91 frip. f10,f11\n# binutils: a2.d: 344: fe 80 ab 91 frip. f20,f21\n:frip. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=456 & Rc=1 \n{\n fT = ceil( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n cr1flags();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Toward Zero\n# FORM: X-form\n# binutils: 476.d: 2b8: fd 40 5b 50 friz f10,f11\n# binutils: a2.d: 350: fe 80 ab 50 friz f20,f21\n:friz fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=424 & Rc=0 \n{\n fT = trunc( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n}\n\n# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions\n# CMT: Floating Round to Integer Toward Zero\n# FORM: X-form\n# binutils: 476.d: 2bc: fd 40 5b 51 friz. f10,f11\n# binutils: a2.d: 34c: fe 80 ab 51 friz. f20,f21\ndefine pcodeop FloatingRoundToIntegerTowardZero1;\n:friz. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=424 & Rc=1 \n{\n fT = trunc( fB );\n setFPRF(fT);\n setSummaryFPSCR();\n cr1flags();\n}\n\n# =======================================================================\n\n# PowerISA II: 4.4.4 Wait Instruction\n# CMT: Wait\n# FORM: X-form\n# binutils: a2.d: 86c: 7c 00 00 7c wait \n# binutils: a2.d: 870: 7c 00 00 7c wait \n# binutils: e500mc.d: 1c: 7c 00 00 7c wait \n# binutils: e500mc.d: 20: 7c 00 00 7c wait \n# binutils: power7.d: 58: 7c 00 00 7c wait \n# binutils: power7.d: 5c: 7c 00 00 7c wait \ndefine pcodeop waitOp;\n:wait BITS_21_22 is OP=31 & crfD=0 & BITS_21_22 & BITS_11_20=0 & XOP_1_10=62 & BIT_0=0 { waitOp(); }\n\n# =======================================================================\n\n# PowerISA II: 4.3.1 System Linkage Instructions\n# CMT: Return From Guest Interrupt [Category:Embedded.Hypervisor]\n# FORM: XL-form\n# binutils: e500mc.d: 0: 4c 00 00 4e rfdi\ndefine pcodeop ReturnFromGuestInterrupt;\n:rfgi is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=102 & BIT_0=0 {\n\tMSR = returnFromGuestInterrupt(MSR, spr17b); #GSRR1\n\treturn[spr17a]; #GSRR0\n}\n\n# =======================================================================\n\n# PowerISA II: 4.4.2.1 64-Bit Load and Reserve and Store Conditional Instructions [Category: 64-Bit]\n# CMT: Load Doubleword And Reserve Indexed\n# FORM: X-form\n# binutils: a2.d: 410: 7d 4b 60 a8 ldarx r10,r11,r12\n# binutils: a2.d: 414: 7d 4b 60 a9 ldarx r10,r11,r12,1\n:ldarx TH,RA_OR_ZERO,B,BIT_0 is OP=31 & TH & RA_OR_ZERO & B & XOP_1_10=84 & BIT_0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tRESERVE = 1;\n\tRESERVE_LENGTH = 8;\n\tRESERVE_ADDRESS = ea;\n\tTH = *:8 (ea);\n}\n\n# =======================================================================\n\n# PowerISA II: 4.4.1 Instruction Synchronize Instruction\n# CMT: Load Word And Reserve Indexed\n# FORM: X-form\n# binutils: 476.d: 394: 7c 64 28 28 lwarx r3,r4,r5\n# binutils: 476.d: 398: 7c 64 28 28 lwarx r3,r4,r5\n# binutils: 476.d: 39c: 7c 64 28 29 lwarx r3,r4,r5,1\n# binutils: a2.d: 4b4: 7d 4b 60 28 lwarx r10,r11,r12\n# binutils: a2.d: 4b8: 7d 4b 60 29 lwarx r10,r11,r12,1\n:lwarx TH,RA_OR_ZERO,B,BIT_0 is OP=31 & TH & RA_OR_ZERO & B & XOP_1_10=20 & BIT_0 \n{\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO+B;\n\tRESERVE = 1;\n\tRESERVE_LENGTH = 4;\n\tRESERVE_ADDRESS = ea;\n\tTH = zext( *:4 (ea) );\n}\n\n# =======================================================================\n\n# PowerISA II: 11.3 Processor Control Instructions\n# CMT: Message Clear\n# FORM: X-form\n# binutils: a2.d: 544: 7c 00 51 dc msgclr r10\n# binutils: e500mc.d: 14: 7c 00 69 dc msgclr r13\ndefine pcodeop MessageClear;\n:msgclr B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=238 & BIT_0=0 { MessageClear(B); }\n\n# PowerISA II: 11.3 Processor Control Instructions\n# CMT: Message Send\n# FORM: X-form\n# binutils: a2.d: 548: 7c 00 51 9c msgsnd r10\n# binutils: e500mc.d: 18: 7c 00 71 9c msgsnd r14\ndefine pcodeop MessageSend;\n:msgsnd B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=206 & BIT_0=0 { MessageSend(); }\n\n# =======================================================================\n\n\n# PowerISA III: TLB Management Instructions (expanded by ISA 3.0)\n# CMT: TLB Invalidate Entry (expands on form in ppc_instructions.sinc)\n# FORM: X-form\n:tlbie RB_OR_ZERO,RS_OR_ZERO,\"2\",BIT_17,BIT_16 is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & BITS_18_19=2 & BIT_17 & BIT_16 & XOP_1_10=306 & BIT_0=0 { # RIC=2\n\t# RIC = 2\n\t# PRS = BIT_17\n\t# R = BIT_16\t\n\tTLBInvalidateEntry(RB_OR_ZERO,RS_OR_ZERO,2:1,BIT_17:1,BIT_16:1);\n}\n:tlbie RB_OR_ZERO,RS_OR_ZERO,BIT_18,BIT_17,\"1\" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & (BITS_18_19=0 | BITS_18_19=1) & BIT_18 & BIT_17 & BIT_16=1 & XOP_1_10=306 & BIT_0=0 { # RIC=0|1 & R=1\n\t# RIC = BITS_18_19 (0 or 1)\n\t# PRS = BIT_17\n\t# R = 1\n\tTLBInvalidateEntry(RB_OR_ZERO,RS_OR_ZERO,BIT_18:1,BIT_17:1,1:1);\n}\n:tlbie RB_OR_ZERO,RS_OR_ZERO,\"3\",\"0\",\"0\" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & BITS_18_19=3 & BIT_17=0 & BIT_16=0 & XOP_1_10=306 & BIT_0=0 { # RIC=3 & PRS=0 & R=0\n\t# RIC = 3\n\t# PRS = 0\n\t# R = 0\n\tTLBInvalidateEntry(RB_OR_ZERO,RS_OR_ZERO,3:1,0:1,0:1);\n}\n\n# PowerISA III: TLB Management Instructions (expanded by ISA 3.0)\n# CMT: TLB Invalidate Entry Local (expands on form in ppc_instructions.sinc)\n# FORM: X-form\n:tlbiel RB_OR_ZERO,RS_OR_ZERO,\"0\",\"0\",\"0\" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BITS_16_20=0 & XOP_1_10=274 & BIT_0=0 { # RIC=0 & PRS=0 & R=0\n\t# RIC = 0\n\t# PRS = 0\n\t# R = 0\t\n\tTLBInvalidateEntryLocal(RB_OR_ZERO,RS_OR_ZERO,0:1,0:1,0:1);\n}\n:tlbiel RB_OR_ZERO,RS_OR_ZERO,\"2\",BIT_17,BIT_16 is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & BITS_18_19=2 & BIT_17 & BIT_16 & XOP_1_10=274 & BIT_0=0 { # RIC=2\n\t# RIC = 2\n\t# PRS = BIT_17\n\t# R = BIT_16\t\n\tTLBInvalidateEntryLocal(RB_OR_ZERO,RS_OR_ZERO,2:1,BIT_17:1,BIT_16:1);\n}\n:tlbiel RB_OR_ZERO,RS_OR_ZERO,BIT_18,BIT_17,\"1\" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & (BITS_18_19=0 | BITS_18_19=1) & BIT_18 & BIT_17 & BIT_16=1 & XOP_1_10=274 & BIT_0=0 { # RIC=0|1 & R=1\n\t# RIC = BITS_18_19 (0 or 1)\n\t# PRS = BIT_17\n\t# R = 1\n\tTLBInvalidateEntryLocal(RB_OR_ZERO,RS_OR_ZERO,BIT_18:1,BIT_17:1,1:1);\n}\n\n\n# PowerISA II: 6.11.4.9 TLB Management Instructions\n# CMT: TLB Search and Reserve Indexed Category: Embedded.TLB Write Conditional]\n# FORM: X-form\n# binutils: a2.d: 848: 7c 0a 5e a5 tlbsrx\\. r10,r11\ndefine pcodeop TLBSearchAndReserveIndexedCategory;\n:tlbsrx. A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=850 & BIT_0=1 { TLBSearchAndReserveIndexedCategory(A,B,cr0); }\n\n# =======================================================================\n\n# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions\n# CMT: Move To FPSCR Fields\n# FORM: X-form\n# binutils: 476.d: 4e0: fc 0c 55 8e mtfsf 6,f10\n# binutils: 476.d: 4e4: fc 0c 55 8e mtfsf 6,f10\n# binutils: 476.d: 4e8: fc 0d 55 8e mtfsf 6,f10,0,1\n# binutils: 476.d: 4ec: fe 0c 55 8e mtfsf 6,f10,1,0\n# binutils: a2.d: 580: fc 0c a5 8e mtfsf 6,f20\n# binutils: a2.d: 588: fc 0c a5 8e mtfsf 6,f20\n# binutils: a2.d: 590: fe 0d a5 8e mtfsf 6,f20,1,1\n# binutils: common.d: 210: fc 0c 55 8e mtfsf 6,f10\n# binutils: power6.d: b4: fc 0c 55 8e mtfsf 6,f10\n# binutils: power6.d: bc: fc 0c 55 8e mtfsf 6,f10\n# binutils: power6.d: c4: fc 0d 55 8e mtfsf 6,f10,0,1\n# binutils: power6.d: cc: fe 0c 55 8e mtfsf 6,f10,1,0\ndefine pcodeop MoveToFPSCRFields;\n:mtfsf BITS_17_24,fB,BIT_25,BIT_16 is $(NOTVLE) & OP=63 & BIT_25 & BITS_17_24 & BIT_16 & fB & XOP_1_10=711 & Rc=0 { # PCODE\n\tMoveToFPSCRFields(fB); \n}\n\n# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions\n# CMT: Move To FPSCR Fields\n# FORM: X-form\n# binutils: 476.d: 4f0: fc 0c 5d 8f mtfsf. 6,f11\n# binutils: 476.d: 4f4: fc 0c 5d 8f mtfsf. 6,f11\n# binutils: 476.d: 4f8: fc 0d 5d 8f mtfsf. 6,f11,0,1\n# binutils: 476.d: 4fc: fe 0c 5d 8f mtfsf. 6,f11,1,0\n# binutils: a2.d: 57c: fc 0c a5 8f mtfsf. 6,f20\n# binutils: a2.d: 584: fc 0c a5 8f mtfsf. 6,f20\n# binutils: a2.d: 58c: fe 0d a5 8f mtfsf. 6,f20,1,1\ndefine pcodeop MoveToFPSCRFields1;\n:mtfsf. BITS_17_24,fB,BIT_25,BIT_16 is $(NOTVLE) & OP=63 & BIT_25 & BITS_17_24 & BIT_16 & fB & XOP_1_10=711 & Rc=1 { # PCODE\n\tMoveToFPSCRFields1(fB); \n}\n\n# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions\n# CMT: Move To FPSCR Field Immediate\n# FORM: X-form\n# binutils: 476.d: 500: ff 00 01 0c mtfsfi 6,0\n# binutils: 476.d: 504: ff 00 01 0c mtfsfi 6,0\n# binutils: 476.d: 508: ff 00 01 0c mtfsfi 6,0\n# binutils: 476.d: 50c: ff 01 01 0c mtfsfi 6,0,1\n# binutils: a2.d: 598: ff 00 01 0c mtfsfi 6,0\n# binutils: a2.d: 5a0: ff 00 d1 0c mtfsfi 6,13\n# binutils: a2.d: 5a8: ff 01 d1 0c mtfsfi 6,13,1\n# binutils: common.d: 218: ff 00 01 0c mtfsfi 6,0\n# binutils: power6.d: d4: ff 00 01 0c mtfsfi 6,0\n# binutils: power6.d: dc: ff 00 01 0c mtfsfi 6,0\n# binutils: power6.d: e4: ff 01 01 0c mtfsfi 6,0,1\ndefine pcodeop MoveToFPSCRFieldImmediate;\n:mtfsfi BF2,BITS_12_15,BIT_16 is $(NOTVLE) & OP=63 & BF2 & BITS_21_22=0 & BITS_17_20=0 & BIT_16 & BITS_12_15 & BIT_11=0 & XOP_1_10=134 & Rc=0 { \n\tMoveToFPSCRFieldImmediate(); \n}\n\n# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions\n# CMT: Move To FPSCR Field Immediate\n# FORM: X-form\n# binutils: 476.d: 510: ff 00 f1 0d mtfsfi. 6,15\n# binutils: 476.d: 514: ff 00 f1 0d mtfsfi. 6,15\n# binutils: 476.d: 518: ff 00 f1 0d mtfsfi. 6,15\n# binutils: 476.d: 51c: ff 01 f1 0d mtfsfi. 6,15,1\n# binutils: a2.d: 594: ff 00 01 0d mtfsfi. 6,0\n# binutils: a2.d: 59c: ff 00 d1 0d mtfsfi. 6,13\n# binutils: a2.d: 5a4: ff 01 d1 0d mtfsfi. 6,13,1\ndefine pcodeop MoveToFPSCRFieldImmediate1;\n:mtfsfi. BITS_23_25,BITS_12_15,BIT_16 is $(NOTVLE) & OP=63 & BITS_23_25 & BITS_21_22=0 & BITS_17_20=0 & BIT_16 & BITS_12_15 & BIT_11=0 & XOP_1_10=134 & Rc=1 { \n\tMoveToFPSCRFieldImmediate1(); \n}\n\n# =======================================================================\n\n# PowerISA II: 3.3.15 Move To/From System Register Instructions\n# CMT: Move To Condition Register Fields\n# FORM: XFX-form\n# binutils: 476.d: 48c: 7c 60 00 26 mfcr r3\ndefine pcodeop mfcrOp;\n:mfcr TO is OP=31 & TO & BIT_20=0 & BITS_12_19=0 & XOP_1_10=190 & BIT_0=0 { mfcrOp(); }\n\n# =======================================================================\n\n# PowerISA II: 5.6.1 DFP Arithmetic Instructions\n# CMT: DFP Add [Quad]\n# FORM: X-form\n# binutils: power6.d: 38: fe 96 c0 04 daddq f20,f22,f24\n# binutils: power7.d: 9c: fe 96 c0 04 daddq f20,f22,f24\ndefine pcodeop daddqOp;\n:daddq fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=2 & Rc=0 { daddqOp(fA,fB); }\n\n# PowerISA II: 5.6.1 DFP Arithmetic Instructions\n# CMT: DFP Add [Quad]\n# FORM: X-form\ndefine pcodeop daddqDotOp;\n:daddq. fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=2 & Rc=1 { daddqDotOp(fA); }\n\n# =======================================================================\n\n# =======================================================================\n# binutils: 476.d: 30c: 7d ae 7b cc icbtls 13,r14,r15\n# binutils: a2.d: 3c4: 7c 0a 5b cc icbtls r10,r11\n# binutils: a2.d: 3c8: 7c ea 5b cc icbtls 7,r10,r11\n# binutils: e500.d: 10: 7d ae 7b cc icbtls 13,r14,r15\n# binutils: titan.d: 198: 7c 02 0b cc icbtls r2,r1\n# binutils: titan.d: 19c: 7c 02 0b cc icbtls r2,r1\n# binutils: titan.d: 1a0: 7c 22 0b cc icbtls 1,r2,r1\n# :icbtls BITS_21_24,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & BIT_25=0 & BITS_21_24 & B & XOP_1_10=486 & BIT_0=0 & RA_OR_ZERO\n# {\n# ea = RA_OR_ZERO + B;\n# \t# prefetchInstructionCacheBlockLockSetX(ea);\n# }\n# Source for information on instructions:\n# PowerISA_V2.06B_PUBLIC.pdf (dated: July 23, 2010)\n# and binutils-2.21.1\n# Have test case for about 200 of these instructions\n\n# Extended Mnemonic\n# xvmovdp XT,XB\t\t=>\t\txvcpsgndp XT,XB,XB\n# xvmovsp XT,XB \t=>\t\txvcpsgnsp XT,XB,XB\n# xxmrghd T,A,B \t=> \t\txxpermdi T,A,B,0b00\n# xxmrgld T,A,B \t=>\t\txxpermdi T,A,B,0b11\n# xxspltd T,A,0 \t=>\t\txxpermdi T,A,A,0b00\n# xxswapd T,A \t\t=>\t\txxpermdi T,A,A,0b10\n\n@include \"vsx.sinc\"\n\n# binutils-descr: \"brinc\",\tVX (4, 527),\tVX_MASK, PPCSPE,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop brincOp;\n# ISA-cmt: brinc - Bit Reversed Increment\n# ISA-info: brinc - Form \"EVX\" Page 510 Category \"SP\"\n# binutils: mytest.d: 1d0:\t10 22 1a 0f \tbrinc r1,r2,r3\n:brinc S,A,B is OP=4 & XOP_0_10=527 & S & A & B { brincOp(S,A,B); } \n\n# binutils-descr: \"hrfid\",\tXL(19,274),\t0xffffffff, POWER5|CELL, PPC476,\t{0}\ndefine pcodeop hrfidOp;\n# ISA-info: hrfid - Form \"XL\" Page 739 Category \"S\"\n# binutils: mytest.d: 0:\t4c 00 02 24 \thrfid\n:hrfid is $(NOTVLE) & OP=19 & XOP_1_10=274 & BITS_11_25=0 & BIT_0=0 { hrfidOp(); } \n\ndefine pcodeop bcctrOp;\n# ZZZ NO-PARSE XLLK - \"bcctr\", XLLK(19,528,0),\t\tXLBH_MASK, PPCCOM,\t PPCNONE,\t{BO, BI, BH}\n:bcctr BO,BI_BITS,BH is $(NOTVLE) & OP=19 & BO & BI_BITS & BITS_13_15=0 & BH & XOP_1_10=528 & LK=0 { bcctrOp(); }\n\ndefine pcodeop bcctrlOp;\n# ZZZ NO-PARSE XLLK - \"bcctrl\", XLLK(19,528,1),\t\tXLBH_MASK, PPCCOM,\t PPCNONE,\t{BO, BI, BH}\n:bcctrl BO,BI_BITS,BH is $(NOTVLE) & OP=19 & BO & BI_BITS & BITS_13_15=0 & BH & XOP_1_10=528 & LK=1 { bcctrlOp(); }\n\n# binutils-descr: \"lbarx\",\tX(31,52),\tXEH_MASK, POWER7,\tPPCNONE,\t{RT, RA0, RB, EH}\ndefine pcodeop lbarxOp;\n# ISA-cmt: lbarx - Load Byte and Reserve Indexed\n# ISA-info: lbarx - Form \"X\" Page 689 Category \"B\"\n# binutils: power7.d: 14c:\t7d 4b 60 68 \tlbarx r10,r11,r12\n# binutils: power7.d: 150:\t7d 4b 60 68 \tlbarx r10,r11,r12\n# binutils: power7.d: 154:\t7d 4b 60 69 \tlbarx r10,r11,r12,1\n:lbarx RT,A,B,BIT_0 is OP=31 & XOP_1_10=52 & RT & A & B & BIT_0 { \n\tA = A + B;\n\tRT = *:1 A;\n} \n\n# binutils-descr: \"lharx\",\tX(31,116),\tXEH_MASK, POWER7,\tPPCNONE,\t{RT, RA0, RB, EH}\ndefine pcodeop lharxOp;\n# ISA-cmt: lharx - Load Halfword and Reserve Indexed\n# ISA-info: lharx - Form \"X\" Page 690 Category \"B\"\n# binutils: power7.d: 158:\t7e 95 b0 e8 \tlharx r20,r21,r22\n# binutils: power7.d: 15c:\t7e 95 b0 e8 \tlharx r20,r21,r22\n# binutils: power7.d: 160:\t7e 95 b0 e9 \tlharx r20,r21,r22,1\n:lharx RT,A,B,BIT_0 is OP=31 & XOP_1_10=116 & RT & A & B & BIT_0 { \n\tA = A + B;\n\tRT = *:2 A;\n} \n\n# binutils-descr: \"ehpriv\",\tX(31,270),\t0xffffffff, E500MC|PPCA2, PPCNONE,\t{0}\ndefine pcodeop ehprivOp;\n# ISA-info: ehpriv - Form \"XL\" Page 889 Category \"E.HV\"\n# binutils: NO-EXAMPLE - ehpriv\n:ehpriv BITS_11_25 is OP=31 & BITS_11_25 & XOP_1_10=270 & BIT_0=0 { ehprivOp(); } \n\n# binutils-descr: \"cbcdtd\",\tX(31,314),\tXRB_MASK, POWER6,\tPPCNONE,\t{RA, RS}\ndefine pcodeop cbcdtdOp;\n# ISA-info: cbcdtd - Form \"X\" Page 97 Category \"BCDA\"\n# binutils: power6.d: ec:\t7d 6a 02 74 \tcbcdtd r10,r11\n:cbcdtd S,A is $(NOTVLE) & OP=31 & S & A & BITS_11_15=0 & XOP_1_10=314 & BIT_0=0 { cbcdtdOp(S,A); } \n\n# binutils-descr: \"divdeu\",\tXO(31,393,0,0),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeuOp;\n# binutils: mytest.d: 4:\t7c 64 2b 12 \tdivdeu r3,r4,r5\n:divdeu RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=0 & Rc=0 & RT & A & B { \n\tRT = A/B;\n} \n\n# binutils-descr: \"divdeu.\",\tXO(31,393,0,1),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeuDotOp;\n# binutils: mytest.d: 8:\t7c 64 2b 13 \tdivdeu. r3,r4,r5\n:divdeu. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=0 & Rc=1 & RT & A & B { \n\tRT = A/B;\n\tcr0flags(RT);\n} \n\n# binutils-descr: \"divde\",\tXO(31,425,0,0),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeOp;\n# binutils: mytest.d: c:\t7c 64 2b 52 \tdivde r3,r4,r5\n:divde RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=0 & Rc=0 & RT & A & B { \n\tRT = A s/ B;\n} \n\n# binutils-descr: \"divde.\",\tXO(31,425,0,1),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeDotOp;\n# binutils: mytest.d: 10:\t7c 64 2b 53 \tdivde. r3,r4,r5\n:divde. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=0 & Rc=1 & RT & A & B { \n\tRT = A s/ B;\n\tcr0flags(RT);\n} \n\n# binutils-descr: \"dsn\", \tX(31,483),\tXRT_MASK, E500MC,\tPPCNONE,\t{RA, RB}\ndefine pcodeop dsnOp;\n# ISA-info: dsn - Form \"X\" Page 710 Category \"DS\"\n# binutils: e500mc.d: 3c:\t7c 18 cb c6 \tdsn r24,r25\n:dsn A,B is OP=31 & XOP_1_10=483 & A & B & BITS_21_25=0 & BIT_0=0 { dsnOp(A,B); } \n\n# binutils-descr: \"lbdx\",\tX(31,515),\tX_MASK, E500MC,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop lbdxOp;\n# ISA-info: lbdx - Form \"X\" Page 708 Category \"DS\"\n# binutils: e500mc.d: 68:\t7c 01 14 06 \tlbdx r0,r1,r2\n:lbdx RT,A,B is OP=31 & XOP_1_10=515 & RT & A & B & BIT_0=0 { RT = lbdxOp(RT,A,B); } \n\n# binutils-descr: \"lhdx\",\tX(31,547),\tX_MASK, E500MC,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop lhdxOp;\n# ISA-info: lhdx - Form \"X\" Page 708 Category \"DS\"\n# binutils: e500mc.d: 6c:\t7d 8d 74 46 \tlhdx r12,r13,r14\n:lhdx RT,A,B is OP=31 & XOP_1_10=547 & RT & A & B & BIT_0=0 { RT = lhdxOp(RT,A,B); } \n\n# binutils-descr: \"lwdx\",\tX(31,579),\tX_MASK, E500MC,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop lwdxOp;\n# ISA-info: lwdx - Form \"X\" Page 708 Category \"DS\"\n# binutils: e500mc.d: 70:\t7c 64 2c 86 \tlwdx r3,r4,r5\n:lwdx RT,A,B is OP=31 & XOP_1_10=579 & RT & A & B & BIT_0=0 { RT = lwdxOp(RT,A,B); } \n\n# binutils-descr: \"lddx\",\tX(31,611),\tX_MASK, E500MC,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop lddxOp;\n# ISA-info: lddx - Form \"X\" Page 708 Category \"DS\"\n# binutils: e500mc.d: 78:\t7d f0 8c c6 \tlddx r15,r16,r17\n:lddx RT,A,B is OP=31 & XOP_1_10=611 & RT & A & B & BIT_0=0 { RT = lddxOp(RT,A,B); } \n\n# ISA-info: lddx - Form \"X\" Page 50 Category \"DS\"\n:ldx RT,RA_OR_ZERO,B is OP=31 & XOP_1_10=21 & RT & RA_OR_ZERO & B & BIT_0=0 { \n\tRT = *:8 (RA_OR_ZERO + B);\n} \n\n# binutils-descr: \"stbdx\",\tX(31,643),\tX_MASK, E500MC,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop stbdxOp;\n# ISA-info: stbdx - Form \"X\" Page 709 Category \"DS\"\n# binutils: e500mc.d: 7c:\t7c c7 45 06 \tstbdx r6,r7,r8\n:stbdx S,A,B is OP=31 & XOP_1_10=643 & S & A & B & BIT_0=0 { *[ram]:1 B =stbdxOp(S,A,B); } \n\n# binutils-descr: \"sthdx\",\tX(31,675),\tX_MASK, E500MC,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop sthdxOp;\n# ISA-info: sthdx - Form \"X\" Page 709 Category \"DS\"\n# binutils: e500mc.d: 80:\t7e 53 a5 46 \tsthdx r18,r19,r20\n:sthdx S,A,B is OP=31 & XOP_1_10=675 & S & A & B & BIT_0=0 { *[ram]:2 B = sthdxOp(S,A,B); } \n\n# binutils-descr: \"stwdx\",\tX(31,707),\tX_MASK, E500MC,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop stwdxOp;\n# ISA-info: stwdx - Form \"X\" Page 709 Category \"DS\"\n# binutils: e500mc.d: 84:\t7d 2a 5d 86 \tstwdx r9,r10,r11\n:stwdx S,A,B is OP=31 & XOP_1_10=707 & S & A & B & BIT_0=0 { *[ram]:4 B = stwdxOp(S,A,B); } \n\n# binutils-descr: \"sthcx.\",\tXRC(31,726,1),\tX_MASK, POWER7,\tPPCNONE,\t{RS, RA0, RB}\ndefine pcodeop sthcxDotOp;\n# ISA-info: sthcx. - Form \"X\" Page 692 Category \"B\"\n# binutils: mytest.d: 14:\t7c 64 2d ad \tsthcx. r3,r4,r5\n:sthcx. S,RA_OR_ZERO,B is OP=31 & XOP_1_10=726 & Rc=1 & S & RA_OR_ZERO & B {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:2 EA = sthcxDotOp(S,RA_OR_ZERO,B);\n\tsetCrBit(cr0, 2, 1);\t\t\n}\n\n# binutils-descr: \"stddx\",\tX(31,739),\tX_MASK, E500MC,\tPPCNONE,\t{RS, RA, RB}\ndefine pcodeop stddxOp;\n# ISA-cmt: stddx - Store Doubleword with Decoration Indexed\n# ISA-info: stddx - Form \"X\" Page 709 Category \"DS\"\n# binutils: e500mc.d: 8c:\t7e b6 bd c6 \tstddx r21,r22,r23\n:stddx S,A,B is OP=31 & XOP_1_10=739 & S & A & B & BIT_0=0 { *[ram]:8 B = stddxOp(S,A,B); } \n\n# binutils-descr: \"lfdpx\",\tX(31,791),\tX_MASK, POWER6,\tPOWER7,\t\t{FRT, RA, RB}\ndefine pcodeop lfdpxOp;\n# ISA-cmt: lfdpx - Load Floating-Point Double Pair Indexed\n# ISA-info: lfdpx - Form \"X\" Page 131 Category \"FP.out\"\n# binutils: power6.d: 30:\t7d ae 7e 2e \tlfdpx f13,r14,r15\n:lfdpx fT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=791 & fT & A & B & BIT_0=0 { fT = lfdpxOp(fT,A,B); } \n\n# binutils-descr: \"lfddx\",\tX(31,803),\tX_MASK, E500MC,\tPPCNONE,\t{FRT, RA, RB}\ndefine pcodeop lfddxOp;\n# ISA-cmt: lfddx - Load Floating Doubleword with Decoration Indexed\n# ISA-info: lfddx - Form \"X\" Page 708 Category \"DS\"\n# binutils: e500mc.d: 74:\t7f 5b e6 46 \tlfddx f26,r27,r28\n:lfddx fT,A,B is OP=31 & XOP_1_10=803 & fT & A & B & BIT_0=0 { fT = lfddxOp(fT,A,B); } \n\n# binutils-descr: \"lhzcix\",\tX(31,821),\tX_MASK, POWER6,\tPPCNONE,\t{RT, RA0, RB}\ndefine pcodeop lhzcixOp;\n# ISA-cmt: lhzcix - Load Halfword and Zero Caching Inhibited Indexed\n# ISA-info: lhzcix - Form \"X\" Page 749 Category \"S\"\n# binutils: mytest.d: 18:\t7c 64 2e 6a \tlhzcix r3,r4,r5\n:lhzcix RT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=821 & RT & A & B & BIT_0=0 { \n\tA = A + B;\n\tRT = *:2 A;\n} \n\n# binutils-descr: \"lbzcix\",\tX(31,853),\tX_MASK, POWER6,\tPPCNONE,\t{RT, RA0, RB}\ndefine pcodeop lbzcixOp;\n# ISA-cmt: lbzcix - Load Byte and Zero Caching Inhibited Indexed\n# ISA-info: lbzcix - Form \"X\" Page 749 Category \"S\"\n# binutils: mytest.d: 1c:\t7c 64 2e aa \tlbzcix r3,r4,r5\n:lbzcix RT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=853 & RT & A & B & BIT_0=0 { \n\tA = A + B;\n\tRT = *:1 A;\n} \n\n# binutils-descr: \"ldcix\",\tX(31,885),\tX_MASK, POWER6,\tPPCNONE,\t{RT, RA0, RB}\n# ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed\n# ISA-info: ldcix - Form \"X\" Page 749 Category \"S\"\n# binutils: mytest.d: 24:\t7c 64 2e ea \tldcix r3,r4,r5\n:ldcix RT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=885 & RT & A & B & BIT_0=0 { \n\tA = A + B;\n\tRT = *:8 A;\n} \n\n# binutils-descr: \"divdeuo\",\tXO(31,393,1,0),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\n# binutils: mytest.d: 28:\t7c 64 2f 12 \tdivdeuo r3,r4,r5\n:divdeuo RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=1 & Rc=0 & RT & A & B { \n\tdivOverflow(A,B);\n\tRT = A/B;\n} \n\n# binutils-descr: \"divdeuo.\",\tXO(31,393,1,1),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeuoDotOp;\n# binutils: mytest.d: 2c:\t7c 64 2f 13 \tdivdeuo. r3,r4,r5\n:divdeuo. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=1 & Rc=1 & RT & A & B { \n\tdivOverflow(A,B);\n\tRT = A/B;\n\tcr0flags(RT);\n} \n\n# binutils-descr: \"stwcix\",\tX(31,917),\tX_MASK, POWER6,\tPPCNONE,\t{RS, RA0, RB}\ndefine pcodeop stwcixOp;\n# ISA-cmt: stwcix - Store Word Caching Inhibited Indexed\n# ISA-info: stwcix - Form \"X\" Page 750 Category \"S\"\n# binutils: mytest.d: 30:\t7c 64 2f 2a \tstwcix r3,r4,r5\n:stwcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=917 & S & A & B & BIT_0=0 { \n\tA = A + B;\n\t*:4 A = S;\n} \n\n# binutils-descr: \"stfdpx\",\tX(31,919),\tX_MASK, POWER6,\tPPCNONE,\t{FRS, RA, RB}\ndefine pcodeop stfdpxOp;\n# ISA-cmt: stfdpx - Store Floating-Point Double Pair Indexed\n# ISA-info: stfdpx - Form \"X\" Page 131 Category \"FP.out\"\n# binutils: mytest.d: 34:\t7c 64 2f 2e \tstfdpx f3,r4,r5\n:stfdpx fS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XOP_1_10=919 & fS & RA_OR_ZERO & B & BIT_0=0 {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:8 EA = stfdpxOp(fS,RA_OR_ZERO,B);\n} \n\n# binutils-descr: \"stfddx\",\tX(31,931),\tX_MASK, E500MC,\tPPCNONE,\t{FRS, RA, RB}\ndefine pcodeop stfddxOp;\n# ISA-info: stfddx - Form \"X\" Page 709 Category \"DS\"\n# binutils: e500mc.d: 88:\t7f be ff 46 \tstfddx f29,r30,r31\n:stfddx fS,A,B is OP=31 & XOP_1_10=931 & fS & A & B & BIT_0=0 { *[ram]:8 B = stfddxOp(fS,A,B); } \n\n# binutils-descr: \"divdeo\",\tXO(31,425,1,0),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeoOp;\n# binutils: mytest.d: 38:\t7c 64 2f 52 \tdivdeo r3,r4,r5\n:divdeo RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=1 & Rc=0 & RT & A & B { \n\tdivOverflow(A,B);\n\tRT = A s/ B;\n} \n\n# binutils-descr: \"divdeo.\",\tXO(31,425,1,1),\tXO_MASK, POWER7|PPCA2,\tPPCNONE,\t{RT, RA, RB}\ndefine pcodeop divdeoDotOp;\n# binutils: mytest.d: 3c:\t7c 64 2f 53 \tdivdeo. r3,r4,r5\n:divdeo. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=1 & Rc=1 & RT & A & B { \n\tdivOverflow(A,B);\n\tRT = A s/ B;\n\tcr0flags(RT);\n} \n\n# binutils-descr: \"sthcix\",\tX(31,949),\tX_MASK, POWER6,\tPPCNONE,\t{RS, RA0, RB}\ndefine pcodeop sthcixOp;\n# ISA-info: sthcix - Form \"X\" Page 750 Category \"S\"\n# binutils: mytest.d: 40:\t7c 64 2f 6a \tsthcix r3,r4,r5\n:sthcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=949 & S & A & B & BIT_0=0 { \n\tA = A + B;\n\t*:2 A = S;\n} \n\ndefine pcodeop slbfeeDotOp;\n# ISA-info: slbfee - Form \"X\" Page 794 Category \"?\"\n:slbfee. RT,B is $(NOTVLE) & OP=31 & RT & BITS_16_20=0 & B & XOP_1_10=979 & BIT_0=1 { slbfeeDotOp(RT,B); }\n\n# binutils-descr: \"stbcix\",\tX(31,981),\tX_MASK, POWER6,\tPPCNONE,\t{RS, RA0, RB}\ndefine pcodeop stbcixOp;\n# ISA-info: stbcix - Form \"X\" Page 750 Category \"S\"\n# binutils: mytest.d: 44:\t7c 64 2f aa \tstbcix r3,r4,r5\n:stbcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=981 & S & A & B & BIT_0=0 { \n\tA = A + B;\n\t*:1 A = A;\n} \n\n# binutils-descr: \"stdcix\",\tX(31,1013),\tX_MASK, POWER6,\tPPCNONE,\t{RS, RA0, RB}\ndefine pcodeop stdcixOp;\n# ISA-info: stdcix - Form \"X\" Page 750 Category \"S\"\n# binutils: mytest.d: 48:\t7c 64 2f ea \tstdcix r3,r4,r5\n:stdcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=1013 & S & A & B & BIT_0=0 { \n\tA = A + B;\n\t*:8 A = S;\n} \n\n# binutils-descr: \"lq\",\t\tOP(56),\t\tOP_MASK, POWER4,\tPPC476,\t\t{RTQ, DQ, RAQ}\n# ISA-cmt: lq - Load Quadword\n# ISA-info: lq - Form \"DQ\" Page 751 Category \"LSQ\"\n# binutils: power4.d: +0:\te0 83 00 00 \tlq r4,0\\(r3\\)\n# binutils: power4.d: +4:\te0 83 00 00 \tlq r4,0\\(r3\\)\n:lq RT,A,DQ is $(NOTVLE) & OP=56 & RT & Dp & A & DQ & BITS_0_3=0 & regp [regpset = Dp+1;] { \n\tea:$(REGISTER_SIZE) = A + sext(DQ:2 << 4);\n@if ENDIAN == \"big\"\n\tRT = *:$(REGISTER_SIZE) ea;\n\tregp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE));\n@else\n\tRT = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE));\n\tregp = *:$(REGISTER_SIZE) ea;\n@endif\n} \n\ndefine pcodeop lvepxOp;\n:lvepx RT,A,B is OP=31 & RT & A & B & XOP_1_10=295 & BIT_0=0 { RT = lvepxOp(RT,A,B); } \n\ndefine pcodeop lvepxlOp;\n:lvepxl RT,A,B is OP=31 & RT & A & B & XOP_1_10=263 & BIT_0=0 { RT = lvepxlOp(RT,A,B); } \n\n# binutils-descr: \"lfdp\",\tOP(57),\t\tOP_MASK, POWER6,\tPOWER7,\t\t{FRT, D, RA0}\ndefine pcodeop lfdpOp;\n# ISA-cmt: lfdp - Load Floating-Point Double Pair\n# ISA-info: lfdp - Form \"DS\" Page 131 Category \"FP.out\"\n# binutils: NO-EXAMPLE - lfdp\n:lfdp fT,A,DS is $(NOTVLE) & OP=57 & fT & A & DS & BITS_0_1=0 { fT = lfdpOp(fT,A,DS:2); } \n\n# binutils-descr: \"dadd\",\tXRC(59,2,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop daddOp;\n# ISA-cmt: dadd - DFP Add\n# binutils: power6.d: 34:\tee 11 90 04 \tdadd f16,f17,f18\n# binutils: power7.d: 98:\tee 11 90 04 \tdadd f16,f17,f18\n:dadd fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=2 & Rc=0 & fT & fA & fB { daddOp(fT,fA,fB); } \n\n# binutils-descr: \"dadd.\",\tXRC(59,2,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop daddDotOp;\n# ISA-cmt: dadd. - DFP Add Rc\n# binutils: mytest.d: 50:\tec 43 20 05 \tdadd. f2,f3,f4\n:dadd. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=2 & Rc=1 & fT & fA & fB { daddDotOp(fT,fA,fB); } \n\n# binutils-descr: \"dqua\",\tZRC(59,3,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT,FRA,FRB,RMC}\ndefine pcodeop dquaOp;\n# ISA-cmt: dqua - DFP Quantize\n# binutils: mytest.d: 54:\tec 22 18 06 \tdqua f1,f2,f3,0\n:dqua fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=3 & Rc=0 & fT & fA & fB & RMC { dquaOp(fT,fA,fB); } \n\n# binutils-descr: \"dqua.\",\tZRC(59,3,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT,FRA,FRB,RMC}\ndefine pcodeop dquaDotOp;\n# ISA-cmt: dqua. - DFP Quantize Rc\n# binutils: mytest.d: 58:\tec 22 18 07 \tdqua. f1,f2,f3,0\n:dqua. fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=3 & Rc=1 & fT & fA & fB & RMC { dquaDotOp(fT,fA,fB); } \n\n# binutils-descr: \"dmul\",\tXRC(59,34,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dmulOp;\n# ISA-cmt: dmul - DFP Multiply\n# binutils: mytest.d: 5c:\tec 43 20 44 \tdmul f2,f3,f4\n:dmul fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=34 & Rc=0 & fT & fA & fB { dmulOp(fT,fA,fB); } \n\n# binutils-descr: \"dmul.\",\tXRC(59,34,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dmulDotOp;\n# ISA-cmt: dmul. - DFP Multiply Rc\n# binutils: mytest.d: 60:\tec 43 20 45 \tdmul. f2,f3,f4\n:dmul. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=34 & Rc=1 & fT & fA & fB { dmulDotOp(fT,fA,fB); } \n\n# binutils-descr: \"drrnd\",\tZRC(59,35,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB, RMC}\ndefine pcodeop drrndOp;\n# ISA-cmt: drrnd - DFP Reround\n# binutils: mytest.d: 64:\tec 43 20 46 \tdrrnd f2,f3,f4,0\n:drrnd fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=35 & Rc=0 & fT & fA & fB & RMC { drrndOp(fT,fA,fB); } \n\n# binutils-descr: \"drrnd.\",\tZRC(59,35,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB, RMC}\ndefine pcodeop drrndDotOp;\n# ISA-cmt: drrnd. - DFP Reround Rc\n# binutils: mytest.d: 68:\tec 43 20 47 \tdrrnd. f2,f3,f4,0\n:drrnd. fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=35 & Rc=1 & fT & fA & fB & RMC { drrndDotOp(fT,fA,fB); } \n\n# binutils-descr: \"dscli\",\tZRC(59,66,0),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscliOp;\n# ISA-cmt: dscli - DFP Shift Significand Left Immediate\n# binutils: mytest.d: 6c:\tec 43 10 84 \tdscli f2,f3,4\n# Y {OP 0 5 {}} {fT 6 10 {}} {fA 11 15 {}} {SH16 16 21 {}} {XOP_1_9 22 30 {}} {Rc 31 31 {}}\n# X 00--------------------------05 06---------------------10 11---------------------15 16--------------------------21 22-----------------------------------------30 31-31 \n# X --------OP=111011(59)---------|-----------fT------------|-----------fA------------|-------------SH16-------------|-------------XOP_1_9=1000010(66)-------------|Rc=0-|\n:dscli fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=66 & Rc=0 & fT & fA & SH16 { dscliOp(fT,fA); } \n\n# binutils-descr: \"dscli.\",\tZRC(59,66,1),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscliDotOp;\n# ISA-cmt: dscli. - DFP Shift Significand Left Immediate Rc\n# binutils: mytest.d: 70:\tec 43 10 85 \tdscli. f2,f3,4\n:dscli. fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=66 & Rc=1 & fT & fA & SH16 { dscliDotOp(fT,fA); } \n\n# binutils-descr: \"dquai\",\tZRC(59,67,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{TE, FRT,FRB,RMC}\ndefine pcodeop dquaiOp;\n# ISA-cmt: dquai - DFP Quantize Immediate\n# binutils: mytest.d: 74:\tec 62 20 86 \tdquai 2,f3,f4,0\n:dquai fT,BITS_16_20,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_16_20 & fB & RMC & XOP_1_8=67 & Rc=0 { dquaiOp(fT,fB); } \n\n# binutils-descr: \"dquai.\",\tZRC(59,67,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{TE, FRT,FRB,RMC}\ndefine pcodeop dquaiDotOp;\n# ISA-cmt: dquai. - DFP Quantize Immediate Rc\n# binutils: mytest.d: 78:\tec 62 20 87 \tdquai. 2,f3,f4,0\n:dquai. fT,BITS_16_20,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_16_20 & fB & RMC & XOP_1_8=67 & Rc=1 { dquaiDotOp(fT,fB); } \n\n# binutils-descr: \"dscri\",\tZRC(59,98,0),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscriOp;\n# ISA-cmt: dscri - DFP Shift Significand Right Immediate\n# binutils: mytest.d: 7c:\tec 43 10 c4 \tdscri f2,f3,4\n:dscri fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=98 & Rc=0 & fT & fA & SH16 { dscriOp(fT,fA); } \n\n# binutils-descr: \"dscri.\",\tZRC(59,98,1),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscriDotOp;\n# ISA-cmt: dscri. - DFP Shift Significand Right Immediate Rc\n# binutils: mytest.d: 80:\tec 43 10 c5 \tdscri. f2,f3,4\n:dscri. fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=98 & Rc=1 & fT & fA & SH16 { dscriDotOp(fT,fA); } \n\n# binutils-descr: \"drintx\",\tZRC(59,99,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintxOp;\n# ISA-cmt: drintx - DFP Round To FP Integer With Inexact\n# binutils: mytest.d: 84:\tec 61 20 c6 \tdrintx 1,f3,f4,0\n:drintx fT,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=0 { drintxOp(fT,fB); } \n\n# binutils-descr: \"drintx.\",\tZRC(59,99,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintxDotOp;\n# ISA-cmt: drintx - DFP Round To FP Integer With Inexact\n# binutils: mytest.d: 84:\tec 61 20 c6 \tdrintx 1,f3,f4,0\n:drintx. fT,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=1 { drintxDotOp(fT,fB); } \n\n# binutils-descr: \"dcmpo\",\tX(59,130),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dcmpoOp;\n# ISA-cmt: dcmpo - DFP Compare Ordered\n# ISA-info: dcmpo - Form \"X\" Page 179 Category \"DFP\"\n# binutils: mytest.d: 8c:\ted 03 21 04 \tdcmpo cr2,f3,f4\n:dcmpo CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=130 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpoOp(CRFD,fA,fB); } \n\n# binutils-descr: \"dtstex\",\tX(59,162),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dtstexOp;\n# ISA-cmt: dtstex - DFP Test Exponent\n# ISA-info: dtstex - Form \"X\" Page 181 Category \"DFP\"\n# binutils: mytest.d: 90:\ted 03 21 44 \tdtstex cr2,f3,f4\n:dtstex CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=162 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstexOp(CRFD,fA,fB); } \n\n# binutils-descr: \"dtstdc\",\tZ(59,194),\tZ_MASK, POWER6,\tPPCNONE,\t{BF, FRA, DCM}\ndefine pcodeop dtstdcOp;\n# ISA-cmt: dtstdc - DFP Test Data Class\n# ISA-info: dtstdc - Form \"Z23\" Page 180 Category \"DFP\"\n# binutils: mytest.d: 94:\ted 03 11 84 \tdtstdc cr2,f3,4\n:dtstdc CRFD,fA,DCM is $(NOTVLE) & OP=59 & XOP_1_9=194 & CRFD & fA & DCM & BITS_21_22=0 & BIT_0=0 { dtstdcOp(CRFD,fA); } \n\n# binutils-descr: \"dtstdg\",\tZ(59,226),\tZ_MASK, POWER6,\tPPCNONE,\t{BF, FRA, DGM}\ndefine pcodeop dtstdgOp;\n# ISA-cmt: dtstdg - DFP Test Data Group\n# ISA-info: dtstdg - Form \"Z23\" Page 180 Category \"DFP\"\n# binutils: mytest.d: 98:\ted 03 11 c4 \tdtstdg cr2,f3,4\n:dtstdg CRFD,fA,DGM is $(NOTVLE) & OP=59 & XOP_1_9=226 & CRFD & fA & DGM & BITS_21_22=0 & BIT_0=0 { dtstdgOp(CRFD,fA); } \n\n# binutils-descr: \"drintn\",\tZRC(59,227,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintnOp;\n# ISA-cmt: drintn - DFP Round To FP Integer Without Inexact\n# binutils: mytest.d: 9c:\tec 61 21 c6 \tdrintn 1,f3,f4,0\n:drintn fT,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=227 & Rc=0 & BIT_16 & fT & fB & RMC & BITS_17_20=0 { drintnOp(fT,fB); } \n\n# binutils-descr: \"drintn.\",\tZRC(59,227,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintnDotOp;\n# ISA-cmt: drintn. - DFP Round To FP Integer Without Inexact Rc\n# binutils: mytest.d: a0:\tec 61 21 c7 \tdrintn. 1,f3,f4,0\n:drintn. fT,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=227 & Rc=1 & BIT_16 & fT & fB & RMC & BITS_17_20=0 { drintnDotOp(fT,fB); } \n\n# binutils-descr: \"dctdp\",\tXRC(59,258,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctdpOp;\n# ISA-cmt: dctdp - DFP Convert To DFP Long\n# binutils: mytest.d: a4:\tec 40 1a 04 \tdctdp f2,f3\n:dctdp fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=258 & Rc=0 & fT & fB & BITS_16_20=0 { dctdpOp(fT,fB); } \n\n# binutils-descr: \"dctdp.\",\tXRC(59,258,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctdpDotOp;\n# ISA-cmt: dctdp. - DFP Convert To DFP Long Rc\n# binutils: mytest.d: a8:\tec 40 1a 05 \tdctdp. f2,f3\n:dctdp. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=258 & Rc=1 & fT & fB & BITS_16_20=0 { dctdpDotOp(fT,fB); } \n\n# binutils-descr: \"dctfix\",\tXRC(59,290,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctfixOp;\n# ISA-cmt: dctfix - DFP Convert To Fixed\n# binutils: mytest.d: ac:\tec 40 1a 44 \tdctfix f2,f3\n:dctfix fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=290 & Rc=0 & fT & fB & BITS_16_20=0 { dctfixOp(fT,fB); } \n\n# binutils-descr: \"dctfix.\",\tXRC(59,290,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctfixDotOp;\n# ISA-cmt: dctfix. - DFP Convert To Fixed Rc\n# binutils: mytest.d: b0:\tec 40 1a 45 \tdctfix. f2,f3\n:dctfix. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=290 & Rc=1 & fT & fB & BITS_16_20=0 { dctfixDotOp(fT,fB); } \n\n# binutils-descr: \"ddedpd\",\tXRC(59,322,0),\tX_MASK, POWER6,\tPPCNONE,\t{SP, FRT, FRB}\ndefine pcodeop ddedpdOp;\n# ISA-cmt: ddedpd - DFP Decode DPD To BCD\n# binutils: mytest.d: b4:\tec 70 22 84 \tddedpd 2,f3,f4\n:ddedpd fT,SP,fB is $(NOTVLE) & OP=59 & fT & SP & BITS_16_18=0 & fB & XOP_1_10=322 & Rc=0 { ddedpdOp(fT,fB); } # & BITS_16_18=0\n\n# binutils-descr: \"ddedpd.\",\tXRC(59,322,1),\tX_MASK, POWER6,\tPPCNONE,\t{SP, FRT, FRB}\ndefine pcodeop ddedpdDotOp;\n# ISA-cmt: ddedpd. - DFP Decode DPD To BCD Rc\n# binutils: mytest.d: b8:\tec 70 22 85 \tddedpd. 2,f3,f4\n:ddedpd. fT,SP,fB is $(NOTVLE) & OP=59 & fT & SP & BITS_16_18=0 & fB & XOP_1_10=322 & Rc=1 { ddedpdDotOp(fT,fB); } # & BITS_16_18=0\n\n# binutils-descr: \"dxex\",\tXRC(59,354,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dxexOp;\n# ISA-cmt: dxex - DFP Extract Biased Exponent\n# binutils: mytest.d: bc:\tec 40 1a c4 \tdxex f2,f3\n:dxex fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=354 & Rc=0 & fT & fB & BITS_16_20=0 { dxexOp(fT,fB); } \n\n# binutils-descr: \"dxex.\",\tXRC(59,354,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dxexDotOp;\n# ISA-cmt: dxex. - DFP Extract Biased Exponent Rc\n# binutils: mytest.d: c0:\tec 40 1a c5 \tdxex. f2,f3\n:dxex. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=354 & Rc=1 & fT & fB & BITS_16_20=0 { dxexDotOp(fT,fB); } \n\n# binutils-descr: \"dsub\",\tXRC(59,514,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dsubOp;\n# ISA-cmt: dsub - DFP Subtract\n# binutils: mytest.d: c4:\tec 43 24 04 \tdsub f2,f3,f4\n:dsub fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=514 & Rc=0 & fT & fA & fB { dsubOp(fT,fA,fB); } \n\n# binutils-descr: \"dsub.\",\tXRC(59,514,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dsubDotOp;\n# ISA-cmt: dsub. - DFP Subtract Rc\n# binutils: mytest.d: c8:\tec 43 24 05 \tdsub. f2,f3,f4\n:dsub. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=514 & Rc=1 & fT & fA & fB { dsubDotOp(fT,fA,fB); } \n\n# binutils-descr: \"ddiv\",\tXRC(59,546,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop ddivOp;\n# ISA-cmt: ddiv - DFP Divide\n# binutils: mytest.d: cc:\tec 43 24 44 \tddiv f2,f3,f4\n:ddiv fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=546 & Rc=0 & fT & fA & fB { ddivOp(fT,fA,fB); } \n\n# binutils-descr: \"ddiv.\",\tXRC(59,546,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop ddivDotOp;\n# ISA-cmt: ddiv. - DFP Divide Rc\n# binutils: mytest.d: d0:\tec 43 24 45 \tddiv. f2,f3,f4\n:ddiv. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=546 & Rc=1 & fT & fA & fB { ddivDotOp(fT,fA,fB); } \n\n# binutils-descr: \"dcmpu\",\tX(59,642),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dcmpuOp;\n# ISA-cmt: dcmpu - DFP Compare Unordered\n# ISA-info: dcmpu - Form \"X\" Page 178 Category \"DFP\"\n# binutils: mytest.d: d4:\ted 03 25 04 \tdcmpu cr2,f3,f4\n:dcmpu CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=642 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpuOp(CRFD,fA,fB); } \n\n# binutils-descr: \"dtstsf\",\tX(59,674),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dtstsfOp;\n# ISA-cmt: dtstsf - DFP Test Significance\n# ISA-info: dtstsf - Form \"X\" Page 182 Category \"DFP\"\n# binutils: mytest.d: d8:\ted 03 25 44 \tdtstsf cr2,f3,f4\n:dtstsf CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=674 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstsfOp(CRFD,fA,fB); } \n\n# binutils-descr: \"drsp\",\tXRC(59,770,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop drspOp;\n# ISA-cmt: drsp - DFP Round To DFP Short\n# binutils: mytest.d: dc:\tec 40 1e 04 \tdrsp f2,f3\n:drsp fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=770 & Rc=0 & fT & fB & BITS_16_20=0 { drspOp(fT,fB); } \n\n# binutils-descr: \"drsp.\",\tXRC(59,770,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop drspDotOp;\n# ISA-cmt: drsp. - DFP Round To DFP Short Rc\n# binutils: mytest.d: e0:\tec 40 1e 05 \tdrsp. f2,f3\n:drsp. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=770 & Rc=1 & fT & fB & BITS_16_20=0 { drspDotOp(fT,fB); } \n\n# binutils-descr: \"dcffix\",\tXRC(59,802,0), X_MASK|FRA_MASK, POWER7,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dcffixOp;\n# ISA-cmt: dcffix - DFP Convert From Fixed\n# binutils: power7.d: 144:\ted 40 66 44 \tdcffix f10,f12\n:dcffix fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=802 & Rc=0 & fT & fB & BITS_16_20=0 { dcffixOp(fT,fB); } \n\n# binutils-descr: \"dcffix.\",\tXRC(59,802,1), X_MASK|FRA_MASK, POWER7,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dcffixDotOp;\n# ISA-cmt: dcffix. - DFP Convert From Fixed Rc\n# binutils: mytest.d: e4:\tec 40 1e 45 \tdcffix. f2,f3\n:dcffix. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=802 & Rc=1 & fT & fB & BITS_16_20=0 { dcffixDotOp(fT,fB); } \n\n# binutils-descr: \"denbcd\",\tXRC(59,834,0),\tX_MASK, POWER6,\tPPCNONE,\t{S, FRT, FRB}\ndefine pcodeop denbcdOp;\n# ISA-cmt: denbcd - DFP Encode BCD To DPD\n# binutils: mytest.d: e8:\tec 70 26 84 \tdenbcd 1,f3,f4\n:denbcd fT,fB is $(NOTVLE) & OP=59 & fT & BIT_20 & BITS_16_19=0 & fB & XOP_1_10=834 & Rc=0 { denbcdOp(fT,fB); } # & BITS_16_19=0 \n\n# binutils-descr: \"denbcd.\",\tXRC(59,834,1),\tX_MASK, POWER6,\tPPCNONE,\t{S, FRT, FRB}\ndefine pcodeop denbcdDotOp;\n# ISA-cmt: denbcd. - DFP Encode BCD To DPD Rc\n# binutils: mytest.d: ec:\tec 70 26 85 \tdenbcd. 1,f3,f4\n:denbcd. fT,fB is $(NOTVLE) & OP=59 & fT & BIT_20 & BITS_16_19=0 & fB & XOP_1_10=834 & Rc=1 { denbcdDotOp(fT,fB); } # & BITS_16_19=0\n\n# binutils-descr: \"diex\",\tXRC(59,866,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop diexOp;\n# ISA-cmt: diex - DFP Insert Biased Exponent\n# binutils: mytest.d: f4:\tec 43 26 c4 \tdiex f2,f3,f4\n:diex fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=866 & Rc=0 & fT & fA & fB { diexOp(fT,fA,fB); } \n\n# binutils-descr: \"diex.\",\tXRC(59,866,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop diexDotOp;\n# ISA-cmt: diex. - DFP Insert Biased Exponent Rc\n# binutils: mytest.d: f8:\tec 43 26 c5 \tdiex. f2,f3,f4\n:diex. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=866 & Rc=1 & fT & fA & fB { diexDotOp(fT,fA,fB); } \n\n# binutils-descr: \"stfdp\",\tOP(61),\t\tOP_MASK, POWER6,\tPPCNONE,\t{FRT, D, RA0}\ndefine pcodeop stfdpOp;\n# ISA-cmt: stfdp - Store Floating-Point Double Pair\n# ISA-info: stfdp - Form \"DS\" Page 131 Category \"FP.out\"\n# binutils: NO-EXAMPLE - stfdp\n:stfdp fS,RA_OR_ZERO,DS is $(NOTVLE) & OP=61 & fS & RA_OR_ZERO & DS & BITS_0_1=0 {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + sext(DS:2 << 2);\n\t*[ram]:8 EA = stfdpOp(fS,RA_OR_ZERO,DS:2);\n} \n\n# binutils-descr: \"stq\",\t\tDSO(62,2),\tDS_MASK, POWER4,\tPPC476,\t\t{RSQ, DS, RA0}\n# ISA-cmt: stq - Store Quadword\n# ISA-info: stq - Form \"DS\" Page 751 Category \"LSQ\"\n# binutils: power4.d: +50:\tf8 c7 00 02 \tstq r6,0\\(r7\\)\n# binutils: power4.d: +54:\tf8 c7 00 12 \tstq r6,16\\(r7\\)\n# binutils: power4.d: +58:\tf8 c7 ff f2 \tstq r6,-16\\(r7\\)\n# binutils: power4.d: +5c:\tf8 c7 80 02 \tstq r6,-32768\\(r7\\)\n# binutils: power4.d: +60:\tf8 c7 7f f2 \tstq r6,32752\\(r7\\)\n:stq RS,RA_OR_ZERO,DS is $(NOTVLE) & OP=62 & RS & Dp & RA_OR_ZERO & DS & BITS_0_1=2 & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + sext(DS:2 << 2);\n@if ENDIAN == \"big\"\n\t*:$(REGISTER_SIZE) ea = RS;\n\t*:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = regp;\n@else\n\t*:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = RS;\n\t*:$(REGISTER_SIZE) ea = regp;\n@endif\n} \n\ndefine pcodeop stvepxOp;\n:stvepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=807 & BIT_0=0 {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:16 EA = stvepxOp(S, RA_OR_ZERO, B);\n} \n\ndefine pcodeop stvepxlOp;\n:stvepxl S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=775 & BIT_0=0 {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:16 EA = stvepxlOp(S, RA_OR_ZERO, B);\n} \n\n# binutils-descr: \"dquaq\",\tZRC(63,3,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB, RMC}\ndefine pcodeop dquaqOp;\n# ISA-cmt: dquaq - DFP Quantize Quad\n# binutils: mytest.d: 100:\tfc 43 24 06 \tdquaq f2,f3,f4,2\n:dquaq fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=3 & Rc=0 { dquaqOp(); } \n\n# binutils-descr: \"dquaq.\",\tZRC(63,3,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB, RMC}\ndefine pcodeop dquaqDotOp;\n# ISA-cmt: dquaq. - DFP Quantize Quad Rc\n# binutils: mytest.d: 104:\tfc 43 24 07 \tdquaq. f2,f3,f4,2\n:dquaq. fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=3 & Rc=1 { dquaqDotOp(); } \n\n# binutils-descr: \"dmulq\",\tXRC(63,34,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dmulqOp;\n# ISA-cmt: dmulq - DFP Multiply Quad\n# binutils: mytest.d: 108:\tfc 43 20 44 \tdmulq f2,f3,f4\n:dmulq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=34 & Rc=0 & fT & fA & fB { dmulqOp(fT,fA,fB); } \n\n# binutils-descr: \"dmulq.\",\tXRC(63,34,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dmulqDotOp;\n# ISA-cmt: dmulq. - DFP Multiply Quad Rc\n# binutils: mytest.d: 10c:\tfc 43 20 45 \tdmulq. f2,f3,f4\n:dmulq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=34 & Rc=1 & fT & fA & fB { dmulqDotOp(fT,fA,fB); } \n\n# binutils-descr: \"drrndq\",\tZRC(63,35,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB, RMC}\ndefine pcodeop drrndqOp;\n# ISA-cmt: drrndq - DFP Reround Quad\n# binutils: mytest.d: 110:\tfc 43 22 46 \tdrrndq f2,f3,f4,1\n:drrndq fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=35 & Rc=0 { drrndqOp(fT,fA,fB); } \n\n# binutils-descr: \"drrndq.\",\tZRC(63,35,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB, RMC}\ndefine pcodeop drrndqDotOp;\n# ISA-cmt: drrndq - DFP Reround Quad\n# binutils: mytest.d: 110:\tfc 43 22 46 \tdrrndq f2,f3,f4,1\n:drrndq. fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=35 & Rc=1 { drrndqDotOp(fT,fA,fB); } \n\n\n# binutils-descr: \"dscliq\",\tZRC(63,66,0),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscliqOp;\n# ISA-cmt: dscliq - DFP Shift Significand Left Immediate Quad\n# binutils: mytest.d: 118:\tfc 43 10 84 \tdscliq f2,f3,4\n:dscliq fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=66 & Rc=0 { dscliqOp(fT,fA); } \n\n# binutils-descr: \"dscliq.\",\tZRC(63,66,1),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscliqDotOp;\n# ISA-cmt: dscliq. - DFP Shift Significand Left Immediate Quad Rc\n# binutils: mytest.d: 11c:\tfc 43 10 85 \tdscliq. f2,f3,4\n:dscliq. fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=66 & Rc=1 { dscliqDotOp(fT,fA); } \n\n# binutils-descr: \"dquaiq\",\tZRC(63,67,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{TE, FRT, FRB, RMC}\ndefine pcodeop dquaiqOp;\n# ISA-cmt: dquaiq - DFP Quantize Immediate Quad\n# binutils: mytest.d: 120:\tfc 62 24 86 \tdquaiq 2,f3,f4,2\n:dquaiq fT,A_BITS,fB,RMC is $(NOTVLE) & OP=63 & fT & A_BITS & fB & RMC & XOP_1_8=67 & Rc=0 { dquaiqOp(fT,fB); } \n\n# binutils-descr: \"dquaiq.\",\tZRC(63,67,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{TE, FRT, FRB, RMC}\ndefine pcodeop dquaiqDotOp;\n# ISA-cmt: dquaiq. - DFP Quantize Immediate Quad Rc\n# binutils: mytest.d: 124:\tfc 62 24 87 \tdquaiq. 2,f3,f4,2\n:dquaiq. fT,A_BITS,fB,RMC is $(NOTVLE) & OP=63 & fT & A_BITS & fB & RMC & XOP_1_8=67 & Rc=1 { dquaiqDotOp(fT,fB); } \n\n# binutils-descr: \"dscriq\",\tZRC(63,98,0),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscriqOp;\n# ISA-cmt: dscriq - DFP Shift Significand Right Immediate Quad\n# binutils: mytest.d: 128:\tfc 43 10 c4 \tdscriq f2,f3,4\n:dscriq fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=98 & Rc=0 { dscriqOp(); } \n\n# binutils-descr: \"dscriq.\",\tZRC(63,98,1),\tZ_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, SH16}\ndefine pcodeop dscriqDotOp;\n# ISA-cmt: dscriq. - DFP Shift Significand Right Immediate Quad Rc\n# binutils: mytest.d: 12c:\tfc 43 10 c5 \tdscriq. f2,f3,4\n:dscriq. fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=98 & Rc=1 { dscriqDotOp(); } \n\n# binutils-descr: \"drintxq\",\tZRC(63,99,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintxqOp;\n# ISA-cmt: drintxq - DFP Round To FP Integer With Inexact Quad\n# binutils: mytest.d: 130:\tfc 61 22 c6 \tdrintxq 1,f3,f4,1\n:drintxq fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=0 { drintxqOp(); } \n\n# binutils-descr: \"drintxq.\",\tZRC(63,99,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintxqDotOp;\n# ISA-cmt: drintxq. - DFP Round To FP Integer With Inexact Quad Rc\n# binutils: mytest.d: 134:\tfc 61 22 c7 \tdrintxq. 1,f3,f4,1\n:drintxq. fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=1 { drintxqDotOp(); } \n\n# binutils-descr: \"dcmpoq\",\tX(63,130),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dcmpoqOp;\n# ISA-cmt: dcmpoq - DFP Compare Ordered Quad\n# ISA-info: dcmpoq - Form \"X\" Page 179 Category \"DFP\"\n# binutils: mytest.d: 138:\tfd 03 21 04 \tdcmpoq cr2,f3,f4\n:dcmpoq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=130 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpoqOp(CRFD,fA,fB); } \n\n# binutils-descr: \"dtstexq\",\tX(63,162),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dtstexqOp;\n# ISA-cmt: dtstexq - DFP Test Exponent Quad\n# ISA-info: dtstexq - Form \"X\" Page 181 Category \"DFP\"\n# binutils: mytest.d: 144:\tfd 03 21 44 \tdtstexq cr2,f3,f4\n:dtstexq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=162 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstexqOp(CRFD,fA,fB); } \n\n# binutils-descr: \"dtstdcq\",\tZ(63,194),\tZ_MASK, POWER6,\tPPCNONE,\t{BF, FRA, DCM}\ndefine pcodeop dtstdcqOp;\n# ISA-cmt: dtstdcq - DFP Test Data Class Quad\n# ISA-info: dtstdcq - Form \"Z22\" Page 180 Category \"DFP\"\n# binutils: mytest.d: 26c:\tfc 82 0d 84 \tdtstdcq cr1,f2,3\n:dtstdcq BF2,fA,DCM is $(NOTVLE) & OP=63 & BF2 & BITS_21_22=0 & fA & DCM & XOP_1_9=194 & BIT_0=0 { dtstdcqOp(fA); } \n\n\n# binutils-descr: \"dtstdgq\",\tZ(63,226),\tZ_MASK, POWER6,\tPPCNONE,\t{BF, FRA, DGM}\ndefine pcodeop dtstdgqOp;\n# ISA-cmt: dtstdgq - DFP Test Data Group Quad\n# ISA-info: dtstdgq - Form \"Z22\" Page 180 Category \"DFP\"\n# binutils: mytest.d: 148:\tfd 03 11 c4 \tdtstdgq cr2,f3,4\n:dtstdgq BF2,fA,DGM is $(NOTVLE) & OP=63 & BF2 & BITS_21_22=0 & fA & DGM & XOP_1_9=226 & BIT_0=0 { dtstdgqOp(); } \n\n# binutils-descr: \"drintnq\",\tZRC(63,227,0),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintnqOp;\n# ISA-cmt: drintnq - DFP Round To FP Integer Without Inexact Quad\n# binutils: mytest.d: 14c:\tfc 61 23 c6 \tdrintnq 1,f3,f4,1\n:drintnq fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & MSR_L & fB & RMC & XOP_1_8=227 & Rc=0 { drintnqOp(); } \n\n# binutils-descr: \"drintnq.\",\tZRC(63,227,1),\tZ2_MASK, POWER6,\tPPCNONE,\t{R, FRT, FRB, RMC}\ndefine pcodeop drintnqDotOp;\n# ISA-cmt: drintnq. - DFP Round To FP Integer Without Inexact Quad Rc\n# binutils: mytest.d: 150:\tfc 61 23 c7 \tdrintnq. 1,f3,f4,1\n:drintnq. fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & MSR_L & fB & RMC & XOP_1_8=227 & Rc=1 { drintnqDotOp(); } \n\n# binutils-descr: \"dctqpq\",\tXRC(63,258,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctqpqOp;\n# ISA-cmt: dctqpq - DFP Convert To DFP Extended\n# binutils: mytest.d: 154:\tfc 40 1a 04 \tdctqpq f2,f3\n:dctqpq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=258 & Rc=0 & fT & fB & BITS_16_20=0 { dctqpqOp(fT,fB); } \n\n# binutils-descr: \"dctqpq.\",\tXRC(63,258,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctqpqDotOp;\n# ISA-cmt: dctqpq. - DFP Convert To DFP Extended Rc\n# binutils: mytest.d: 158:\tfc 40 1a 05 \tdctqpq. f2,f3\n:dctqpq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=258 & Rc=1 & fT & fB & BITS_16_20=0 { dctqpqDotOp(fT,fB); } \n\n# binutils-descr: \"dctfixq\",\tXRC(63,290,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctfixqOp;\n# ISA-cmt: dctfixq - DFP Convert To Fixed Quad\n# binutils: mytest.d: 15c:\tfc 40 1a 44 \tdctfixq f2,f3\n:dctfixq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=290 & Rc=0 & fT & fB & BITS_16_20=0 { dctfixqOp(fT,fB); } \n\n# binutils-descr: \"dctfixq.\",\tXRC(63,290,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dctfixqDotOp;\n# ISA-cmt: dctfixq. - DFP Convert To Fixed Quad Rc\n# binutils: mytest.d: 160:\tfc 40 1a 45 \tdctfixq. f2,f3\n:dctfixq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=290 & Rc=1 & fT & fB & BITS_16_20=0 { dctfixqDotOp(fT,fB); } \n\n# binutils-descr: \"ddedpdq\",\tXRC(63,322,0),\tX_MASK, POWER6,\tPPCNONE,\t{SP, FRT, FRB}\ndefine pcodeop ddedpdqOp;\n# ISA-cmt: ddedpdq - DFP Decode DPD To BCD Quad\n# binutils: mytest.d: 164:\tfc 70 22 84 \tddedpdq 2,f3,f4\n:ddedpdq fT,SP,fB is $(NOTVLE) & OP=63 & XOP_1_10=322 & Rc=0 & fT & fB & SP & BITS_16_18=0 { ddedpdqOp(fT,fB); } \n\n# binutils-descr: \"ddedpdq.\",\tXRC(63,322,1),\tX_MASK, POWER6,\tPPCNONE,\t{SP, FRT, FRB}\ndefine pcodeop ddedpdqDotOp;\n# ISA-cmt: ddedpdq. - DFP Decode DPD To BCD Quad Rc\n# binutils: mytest.d: 168:\tfc 70 22 85 \tddedpdq. 2,f3,f4\n:ddedpdq. fT,SP,fB is $(NOTVLE) & OP=63 & XOP_1_10=322 & Rc=1 & fT & fB & SP & BITS_16_18=0 { ddedpdqDotOp(fT,fB); } \n\n# binutils-descr: \"dxexq\",\tXRC(63,354,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dxexqOp;\n# ISA-cmt: dxexq - DFP Extract Biased Exponent Quad\n# binutils: mytest.d: 16c:\tfc 40 1a c4 \tdxexq f2,f3\n:dxexq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=354 & Rc=0 & fT & fB & BITS_16_20=0 { dxexqOp(fT,fB); } \n\n# binutils-descr: \"dxexq.\",\tXRC(63,354,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dxexqDotOp;\n# ISA-cmt: dxexq. - DFP Extract Biased Exponent Quad Rc\n# binutils: mytest.d: 170:\tfc 40 1a c5 \tdxexq. f2,f3\n:dxexq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=354 & Rc=1 & fT & fB & BITS_16_20=0 { dxexqDotOp(fT,fB); } \n\n# binutils-descr: \"dsubq\",\tXRC(63,514,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dsubqOp;\n# ISA-cmt: dsubq - DFP Subtract Quad\n# binutils: mytest.d: 174:\tfc 43 24 04 \tdsubq f2,f3,f4\n:dsubq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=514 & Rc=0 & fT & fA & fB { dsubqOp(fT,fA,fB); } \n\n# binutils-descr: \"dsubq.\",\tXRC(63,514,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop dsubqDotOp;\n# ISA-cmt: dsubq. - DFP Subtract Quad Rc\n# binutils: mytest.d: 178:\tfc 43 24 05 \tdsubq. f2,f3,f4\n:dsubq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=514 & Rc=1 & fT & fA & fB { dsubqDotOp(fT,fA,fB); } \n\n# binutils-descr: \"ddivq\",\tXRC(63,546,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop ddivqOp;\n# ISA-cmt: ddivq - DFP Divide Quad\n# binutils: mytest.d: 17c:\tfc 43 24 44 \tddivq f2,f3,f4\n:ddivq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=546 & Rc=0 & fT & fA & fB { ddivqOp(fT,fA,fB); } \n\n# binutils-descr: \"ddivq.\",\tXRC(63,546,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop ddivqDotOp;\n# ISA-cmt: ddivq. - DFP Divide Quad Rc\n# binutils: mytest.d: 180:\tfc 43 24 45 \tddivq. f2,f3,f4\n:ddivq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=546 & Rc=1 & fT & fA & fB { ddivqDotOp(fT,fA,fB); } \n\n# binutils-descr: \"dcmpuq\",\tX(63,642),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dcmpuqOp;\n# ISA-cmt: dcmpuq - DFP Compare Unordered Quad\n# ISA-info: dcmpuq - Form \"X\" Page 179 Category \"DFP\"\n# binutils: mytest.d: 184:\tfd 03 25 04 \tdcmpuq cr2,f3,f4\n:dcmpuq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=642 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpuqOp(CRFD,fA,fB); } \n\n# binutils-descr: \"dtstsfq\",\tX(63,674),\tX_MASK, POWER6,\tPPCNONE,\t{BF, FRA, FRB}\ndefine pcodeop dtstsfqOp;\n# ISA-cmt: dtstsfq - DFP Test Significance Quad\n# ISA-info: dtstsfq - Form \"X\" Page 182 Category \"DFP\"\n# binutils: mytest.d: 188:\tfd 03 25 44 \tdtstsfq cr2,f3,f4\n:dtstsfq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=674 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstsfqOp(CRFD,fA,fB); } \n\n# binutils-descr: \"drdpq\",\tXRC(63,770,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop drdpqOp;\n# ISA-cmt: drdpq - DFP Round To DFP Long\n# binutils: mytest.d: 18c:\tfc 40 1e 04 \tdrdpq f2,f3\n:drdpq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=770 & Rc=0 & fT & fB & BITS_16_20=0 { drdpqOp(fT,fB); } \n\n# binutils-descr: \"drdpq.\",\tXRC(63,770,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop drdpqDotOp;\n# ISA-cmt: drdpq. - DFP Round To DFP Long Rc\n# binutils: mytest.d: 190:\tfc 40 1e 05 \tdrdpq. f2,f3\n:drdpq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=770 & Rc=1 & fT & fB & BITS_16_20=0 { drdpqDotOp(fT,fB); } \n\n# binutils-descr: \"dcffixq\",\tXRC(63,802,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dcffixqOp;\n# ISA-cmt: dcffixq - DFP Convert From Fixed Quad\n# binutils: mytest.d: 194:\tfc 40 1e 44 \tdcffixq f2,f3\n:dcffixq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=802 & Rc=0 & fT & fB & BITS_16_20=0 { dcffixqOp(fT,fB); } \n\n# binutils-descr: \"dcffixq.\",\tXRC(63,802,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRB}\ndefine pcodeop dcffixqDotOp;\n# ISA-cmt: dcffixq. - DFP Convert From Fixed Quad Rc\n# binutils: mytest.d: 198:\tfc 40 1e 45 \tdcffixq. f2,f3\n:dcffixq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=802 & Rc=1 & fT & fB & BITS_16_20=0 { dcffixqDotOp(fT,fB); } \n\n# binutils-descr: \"denbcdq\",\tXRC(63,834,0),\tX_MASK, POWER6,\tPPCNONE,\t{S, FRT, FRB}\ndefine pcodeop denbcdqOp;\n# ISA-cmt: denbcdq - DFP Encode BCD To DPD Quad\n# binutils: mytest.d: 19c:\tfc 70 26 84 \tdenbcdq 1,f3,f4\n:denbcdq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=834 & Rc=0 & BIT_20 & fT & fB & SR=0 { denbcdqOp(fT,fB); } \n\n# binutils-descr: \"denbcdq.\",\tXRC(63,834,1),\tX_MASK, POWER6,\tPPCNONE,\t{S, FRT, FRB}\ndefine pcodeop denbcdqDotOp;\n# ISA-cmt: denbcdq. - DFP Encode BCD To DPD Quad Rc\n# binutils: mytest.d: 1a0:\tfc 70 26 85 \tdenbcdq. 1,f3,f4\n:denbcdq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=834 & Rc=1 & BIT_20 & fT & fB & SR=0 { denbcdqDotOp(fT,fB); } \n\n# binutils-descr: \"diexq\",\tXRC(63,866,0),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop diexqOp;\n# ISA-cmt: diexq - DFP Insert Biased Exponent Quad\n# binutils: mytest.d: 1a4:\tfc 43 26 c4 \tdiexq f2,f3,f4\n:diexq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=866 & Rc=0 & fT & fA & fB { diexqOp(fT,fA,fB); } \n\n# binutils-descr: \"diexq.\",\tXRC(63,866,1),\tX_MASK, POWER6,\tPPCNONE,\t{FRT, FRA, FRB}\ndefine pcodeop diexqDotOp;\n# ISA-cmt: diexq. - DFP Insert Biased Exponent Quad Rc\n# binutils: mytest.d: 1a8:\tfc 43 26 c5 \tdiexq. f2,f3,f4\n:diexq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=866 & Rc=1 & fT & fA & fB { diexqDotOp(fT,fA,fB); } \n\n# icbtls ct,ra,rb\n# 31 / CT RA RB 486 /\n# 0 6 7 11 16 21 31\n# 31 25 24 20 15 10 0\n#define pcodeop icbtlsOp;\n#:icbtls CT2,A,B is $(NOTVLE) & OP=31 & BIT_25=0 & CT2 & A & B & XOP_1_10=486 & BIT_0=0 { icbtlsOp(A,B); }\ndefine pcodeop InstructionCacheBlockLockSetX;\n:icbtls CT,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & BIT_25=0 & CT & RA_OR_ZERO & B & XOP_1_10=486 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tInstructionCacheBlockLockSetX(ea);\n}\n\n######################################\n# v2.07 non vsx additions. \n\n#===========================================================\n# Branch Conditional TAR(op=19, xop=560)\n#===========================================================\n\n\n:bctar \t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=560\n{\n\tgoto [TAR];\n}\n\n:bctar \t\tis linkreg=1 & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=560\n [ linkreg=0; globalset(inst_start,linkreg); ]\n{\n # don't do this anymore, detect another way\n\t# call [CTR];\n\t# return [LR];\n\tgoto [TAR];\n}\n\n:bctar BH \t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH & XOP_1_10=560\n{\n\tgoto [TAR];\n}\n\n:bctarl\t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH=0 & XOP_1_10=560\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tcall [TAR];\n}\n:bctarl BH\t\tis $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH & XOP_1_10=560\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tLR = inst_next;\n\tcall [TAR];\n}\n\n:b^CC^\"ctar\" \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560\n{\n\tif (!CC) goto inst_next; \n\tgoto [TAR];\n}\n:b^CC^\"ctar\" BH \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560\n{\n\tif (!CC) goto inst_next; \n\tgoto [TAR];\n}\n\n:b^CC^\"ctarl\" \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next; \n\tLR = inst_next;\n\tcall [TAR];\n}\n:b^CC^\"ctarl\" BH \tis $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next; \n\tLR = inst_next;\n\tcall [TAR];\n}\n\n:b^CC^\"ctar\" BI_CR \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560\n{\n\tif (!CC) goto inst_next; \n\tgoto [TAR];\n}\n\n:b^CC^\"ctar\" BI_CR,BH \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=560\n{\n\tif (!CC) goto inst_next; \n\tgoto [TAR];\n}\n\n:b^CC^\"ctarl\" BI_CR \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next; \n\tLR = inst_next;\n\tcall [TAR];\n}\n\n:b^CC^\"ctarl\" BI_CR,BH \t\tis $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=1 & BITS_13_15=0 & XOP_1_10=560\n\t\t\t\t\t\t\t\t\t\t[ linkreg=0; globalset(inst_start,linkreg); ]\n{\n\tif (!CC) goto inst_next; \n\tLR = inst_next;\n\tcall [TAR];\n}\n\n:clrbhrb\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=430 & BITS_11_25=0 & BIT_0=0 {\n\tclearHistory();\t\n}\n\n:fmrgew fT,fA,fB \t\tis $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=966 & Rc=0 {\n\tfT[0,32] = fA:4;\n\tfT[32,32] = fB:4;\n}\n\n:fmrgow fT,fA,fB \t\tis $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=838 & Rc=0 {\n\tfT[0,32] = fA(4);\n\tfT[32,32] = fB(4);\t\n}\n\n:lqarx D,RA_OR_ZERO,B,EX \tis OP=31 & D & RA_OR_ZERO & B & XOP_1_10=276 & EX & Dp & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n@if ENDIAN == \"big\"\n\tD = *:$(REGISTER_SIZE) ea;\n\tregp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE));\n@else\n\tD = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE));\n\tregp = *:$(REGISTER_SIZE) ea;\n@endif\t\n}\n\n:mfbhrbe D,BH_RBE\t\tis $(NOTVLE) & OP=31 & XOP_1_10=302 & BIT_0=0 & D & BH_RBE {\n\tD = movebuffer(BH_RBE:2);\n}\n\n:msgclrp B\t\t\t\tis OP=31 & XOP_1_10=174 & BITS_16_25=0 & BIT_0=0 & B {\n\tmessage(B);\n}\n\n:msgsndp B\t\t\t\tis OP=31 & XOP_1_10=142 & BITS_16_25=0 & BIT_0=0 & B {\n\tmessage(B);\n}\n\n:rfebb SBE\t\t\t\tis $(NOTVLE) & OP=19 & XOP_1_10=146 & BITS_12_25=0 & BIT_0=0 & SBE {\n\teventInterrupt(SBE:1);\n}\n\n:stqcx. S,RA_OR_ZERO,B \tis OP=31 & S & RA_OR_ZERO & B & XOP_1_10=182 & BIT_0=1 & Dp & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n@if ENDIAN == \"big\"\n\t*:$(REGISTER_SIZE) ea = S;\n\t*:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = regp;\n@else\n\t*:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = S;\n\t*:$(REGISTER_SIZE) ea = regp;\n@endif\n\tsetCrBit(cr0, 2, 1);\t\t\n}\n\n:tabort. A \t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=910 & BIT_0=1 & BITS_11_15=0 & BITS_21_25=0 & A {\n\ttransaction(A);\n} \n\n:tabortdc. TOA,A,B \t\tis $(NOTVLE) & OP=31 & XOP_1_10=814 & BIT_0=1 & A & B & TOA {\n\ttransaction(TOA:1,A,B);\n} \n\n:tabortdci. TOA,A,S5IMM is $(NOTVLE) & OP=31 & XOP_1_10=878 & BIT_0=1 & A & S5IMM & TOA {\n\ttransaction(TOA:1,A,S5IMM:1);\t\n} \n\n:tabortwc. TOA,A,B \t\tis $(NOTVLE) & OP=31 & XOP_1_10=782 & BIT_0=1 & A & B & TOA {\n\ttransaction(TOA:1,A,B);\t\n} \n\n:tabortwci. TOA,A,S5IMM is $(NOTVLE) & OP=31 & XOP_1_10=846 & BIT_0=1 & A & S5IMM & TOA {\n\ttransaction(TOA:1,A,S5IMM:1);\t\t\n} \n\n:tbegin. BIT_R \t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=654 & BIT_0=1 & BITS_11_20=0 & BITS_22_24=0 & BIT_R {\n\ttransaction(BIT_R:1);\t\t\n} \n\n:tcheck BF2 \t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=718 & BIT_0=0 & BITS_11_22=0 & BF2 {\n\ttransaction(BF2:1);\t\t\t\n} \n\n:tend. BIT_A \t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=686 & BIT_0=1 & BITS_11_24=0 & BIT_A {\n\ttransaction(BIT_A:1);\t\t\t\n} \n\n:trechkpt. \t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=1006 & BIT_0=1 & BITS_11_25=0 {\n\ttransaction();\t\t\t\n} \n\n:treclaim. A \t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=942 & BIT_0=1 & BITS_11_15=0 & BITS_21_25=0 & A {\n\ttransaction(A);\t\t\t\n} \n\n:tsr. BIT_L \t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=750 & BIT_0=1 & BITS_11_20=0 & BITS_22_25=0 & BIT_L {\n\ttransaction(BIT_L:1);\t\t\t\t\n} \n\n#######################\n# v3.0\n\n:addpcis D,OFF16SH\t\tis $(NOTVLE) & OP=19 & XOP_1_5=2 & D & OFF16SH {\n\tD = inst_next + sext(OFF16SH);\n}\n\n:cmpeqb CRFD,A,B\t\t\tis $(NOTVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=224 & A & B & CRFD {\n\ttmpa:1 = A:1;\n\tmatch:1 = (tmpa == B[0,8]) | (tmpa == B[8,8]) | (tmpa == B[16,8]) | (tmpa == B[24,8]);\n@if REGISTER_SIZE == \"8\"\n\tmatch = match | (tmpa == B[32,8]) | (tmpa == B[40,8]) | (tmpa == B[48,8]) | (tmpa == B[56,8]);\n@endif\n\t# 0b0 | match | 0b0 | 0b0\n\tCRFD = (match & 1) << 2;\n}\n\n:cmprb CRFD,L2,A,B\t\tis $(NOTVLE) & OP=31 & BIT_22=0 & BIT_0=0 & XOP_1_10=192 & A & B & CRFD & L2 {\n\ttmpin:1 = A:1;\n\ttmp1lo:1 = B[16,8];\n\ttmp1hi:1 = B[24,8];\n\ttmp2lo:1 = B[0,8];\n\ttmp2hi:1 = B[8,8];\n\tin_range:1 = ((tmpin >= tmp2lo) & (tmpin <= tmp2hi)) | (((tmpin >= tmp1lo) & (tmpin <= tmp1hi)) * L2:1);\n\t# 0b0 | in_range | 0b0 | 0b0\n\tCRFD = (in_range & 1) << 2;\n}\n\n:cnttzw A,S\t\t\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=0 {\n\tA = countTrailingZeros(S);\t\n}\n\n:cnttzw. A,S\t\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=1 {\n\tA = countTrailingZeros(S);\t\n\tcr0flags(A); \t\t\t\t\t\n}\n\n:cnttzd A,S\t\t\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=0 {\n\tA = countTrailingZeros(S);\t\t\n}\n\n:cnttzd. A,S\t\t\tis OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=1 {\n\tA = countTrailingZeros(S);\t\n\tcr0flags(A); \t\t\t\t\t\t\n}\n\n:copy RA_OR_ZERO,B,L2\tis $(NOTVLE) & OP=31 & BITS_22_25=0 & BIT_0=0 & XOP_1_10=774 & RA_OR_ZERO & B & L2 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tcopytrans(ea,L2:1);\n}\n\n:cp_abort \t\t\t\tis $(NOTVLE) & OP=31 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=838{\n\tcopytrans();\n}\n\n:darn D,L16\t\t\t\tis $(NOTVLE) & OP=31 & BITS_18_20=0 & BITS_11_15=0 & BIT_0=0 & XOP_1_10=755 & D & L16 {\n\tD = random(L16:1);\n}\n\n:dtstsfi CRFD,UIMT,fB \tis $(NOTVLE) & OP=59 & XOP_1_10=675 & CRFD & UIMT & fB & BIT_22=0 & BIT_0=0 {\n\tdtstsfOp(CRFD,UIMT:1,fB);\t\n} \n\n:dtstsfiq CRFD,UIMT,fB \tis $(NOTVLE) & OP=63 & XOP_1_10=675 & CRFD & UIMT & fB & BIT_22=0 & BIT_0=0 {\n\tdtstsfOp(CRFD,UIMT:1,fB);\t\t\n}\n\n:extswsli A,S,SH\t\tis OP=31 & A & S & SH & XOP_2_10=445 & Rc=0 {\n\ttmp:8 = sext(S:4);\n\tA = tmp << SH;\n}\n\n:extswsli. A,S,SH\t\tis OP=31 & A & S & SH & XOP_2_10=445 & Rc=1 {\n\ttmp:8 = sext(S:4);\n\tA = tmp << SH;\n\tcr0flags(A); \t\t\t\t\t\t\t\n}\n\n:ldat D,RA_OR_ZERO,FNC\tis $(NOTVLE) & OP=31 & D & RA_OR_ZERO & FNC & XOP_1_10=614 & BIT_0=0 & Dp & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO;\n\ttmp:$(REGISTER_SIZE) = *:8 ea;\n\tmematom(ea,tmp,D,regp,FNC:1);\n\tD = tmp;\t\n}\n\n:ldmx D,RA_OR_ZERO,B\tis $(NOTVLE) & OP=31 & D & RA_OR_ZERO & B & XOP_1_10=309 & BIT_0=0 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tD = *:8 ea;\n}\n\n:lwat D,RA_OR_ZERO,FNC\tis $(NOTVLE) & OP=31 & D & RA_OR_ZERO & FNC & XOP_1_10=582 & BIT_0=0 & Dp & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO;\n\ttmp:$(REGISTER_SIZE) = zext(*:4 ea);\n\tmematom(ea,tmp,D,regp,FNC:1);\n\tD = tmp;\n}\n\n:maddhd D,A,B,C\t\t\tis $(NOTVLE) & OP=4 & D & A & B & C & XOP_0_5=48 {\n\ttmpa:16 = sext(A);\n\ttmpb:16 = sext(B);\n\ttmpc:16 = sext(C);\n\ttmpp:16 = (tmpa * tmpb) + tmpc;\n\tD = tmpp(8);\n}\n\n:maddhdu D,A,B,C\t\tis $(NOTVLE) & OP=4 & D & A & B & C & XOP_0_5=49 {\n\ttmpa:16 = zext(A);\n\ttmpb:16 = zext(B);\n\ttmpc:16 = zext(C);\n\ttmpp:16 = (tmpa * tmpb) + tmpc;\n\tD = tmpp(8);\t\n}\n\n:maddld D,A,B,C\t\t\tis $(NOTVLE) & OP=4 & D & A & B & C & XOP_0_5=51 {\n\ttmpa:16 = sext(A);\n\ttmpb:16 = sext(B);\n\ttmpc:16 = sext(C);\n\ttmpp:16 = (tmpa * tmpb) + tmpc;\n\tD = tmpp:8;\n}\n\n:mcrxrx CRFD\t\t\tis $(NOTVLE) & OP=31 & BITS_11_22=0 & BIT_0=0 & XOP_1_10=576 & CRFD {\n\tCRFD = (xer_ov << 3) | (xer_ov32 << 2) | (xer_ca << 1) | (xer_ca32);\n}\n\n:modsd D,A,B\t\t\tis $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=777 & BIT_0=0 {\n\ttmpa:16 = sext(A);\n\ttmpb:16 = sext(B);\n\ttmpd:16 = tmpa s% tmpb;\n\tD = tmpd:$(REGISTER_SIZE);\n}\n\n:modsw D,A,B\t\t\tis $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=779 & BIT_0=0 {\n\ttmpa:16 = sext(A:4);\n\ttmpb:16 = sext(B:4);\n\ttmpd:16 = tmpa s% tmpb;\n\tD = tmpd:$(REGISTER_SIZE);\t\n}\n\n:modud D,A,B\t\t\tis $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=265 & BIT_0=0 {\n\ttmpa:16 = zext(A);\n\ttmpb:16 = zext(B);\n\ttmpd:16 = tmpa % tmpb;\n\tD = tmpd:$(REGISTER_SIZE);\t\n}\n\n:moduw D,A,B\t\t\tis $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=267 & BIT_0=0 {\n\ttmpa:4 = zext(A:4);\n\ttmpb:4 = zext(B:4);\n\ttmpd:4 = tmpa % tmpb;\n\tD = zext(tmpd);\t\t\n}\n\n:msgsync \t\t\t\tis $(NOTVLE) & OP=31 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=886 {\n\tmessage();\n}\n\n:paste RA_OR_ZERO,B,0\tis $(NOTVLE) & OP=31 & BITS_22_25=0 & XOP_1_10=902 & RA_OR_ZERO & B & L2=0 & Rc=0 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tpastetrans(ea);\n}\n\n:paste. RA_OR_ZERO,B,1\tis $(NOTVLE) & OP=31 & BITS_22_25=0 & XOP_1_10=902 & RA_OR_ZERO & B & L2=1 & Rc=1 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tpastetrans(ea);\n\tsetCrBit(cr0, 2, 1);\t\t\n}\n\n:setb D,BFA\t\t\t\tis $(NOTVLE) & OP=31 & BITS_11_17=0 & BIT_0=0 & XOP_1_10=128 & D & BFA {\n\ttmpcr:8 = 1 << (8 * BFA:1);\n\ttmpr0:1 = (BFA & 0x8) != 0;\n\ttmpr1:1 = (BFA & 0x4) != 0;\n\tD = (-1 * zext(tmpr0)) + (1 * zext(tmpr0 == 0) * zext(tmpr1));\n}\n\n:slbieg S,B\t\t\t\tis $(NOTVLE) & OP=31 & BITS_16_20=0 & BIT_0=0 & XOP_1_10=466 & S & B {\n\tslbInvalidateEntry(S,B);\n}\n\n:slbsync \t\t\t\tis $(NOTVLE) & OP=31 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=338 {\n\tsync();\n}\n\n:stdat S,RA_OR_ZERO,FNC\tis $(NOTVLE) & OP=31 & S & RA_OR_ZERO & FNC & XOP_1_10=742 & BIT_0=0 & Dp & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO;\n\ttmp:$(REGISTER_SIZE) = *:8 ea;\n\tmematom(ea,tmp,S,regp,FNC:1);\n}\n\n:stop \t\t\t\t\tis $(NOTVLE) & OP=19 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=370 {\n\tstopT();\n}\n\n:stwat S,RA_OR_ZERO,FNC\tis $(NOTVLE) & OP=31 & S & RA_OR_ZERO & FNC & XOP_1_10=710 & BIT_0=0 & Dp & regp [regpset = Dp+1;] {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO;\n\ttmp:$(REGISTER_SIZE) = zext(*:4 ea);\n\tmematom(ea,tmp,S,regp,FNC:1);\t\n}\n\n:wait WC\t\t\t\tis $(NOTVLE) & OP=31 & BITS_23_25=0 & BITS_11_20=0 & BIT_0=0 & XOP_1_10=30 & WC {\n\twaitT(WC:1);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/ppc_vle.sinc", "content": "\nCC16: \"lt\"\t\tis BI16_VLE=0 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; }\nCC16: \"le\"\t\tis BI16_VLE=1 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; }\nCC16: \"eq\"\t\tis BI16_VLE=2 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; }\nCC16: \"ge\"\t\tis BI16_VLE=0 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; }\nCC16: \"gt\"\t\tis BI16_VLE=1 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; }\nCC16: \"ne\"\t\tis BI16_VLE=2 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; }\nCC16: \"so\"\t\tis BI16_VLE=3 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; }\nCC16: \"ns\"\t\tis BI16_VLE=3 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; }\n\n\nCC32: \"lt\"\t\tis BI_CC_VLE=0 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; }\nCC32: \"le\"\t\tis BI_CC_VLE=1 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; }\nCC32: \"eq\"\t\tis BI_CC_VLE=2 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; }\nCC32: \"ge\"\t\tis BI_CC_VLE=0 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; }\nCC32: \"gt\"\t\tis BI_CC_VLE=1 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; }\nCC32: \"ne\"\t\tis BI_CC_VLE=2 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; }\nCC32: \"so\"\t\tis BI_CC_VLE=3 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; }\nCC32: \"ns\"\t\tis BI_CC_VLE=3 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; }\nCC32: \"dnz\"\t\tis BO_VLE=2 {CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; }\nCC32: \"dz\"\t\tis BO_VLE=3 {CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; }\n\naddrBD8: reloc\tis BD8_VLE \t\t[ reloc = inst_start + (BD8_VLE << 1);] \t{ export *[ram]:4 reloc; }\naddrBD15: reloc\tis BD15_VLE\t\t[ reloc = inst_start + (BD15_VLE << 1);] \t{ export *[ram]:4 reloc; }\naddrBD24: reloc\tis BD24_VLE \t[ reloc = inst_start + (BD24_VLE << 1);] \t{ export *[ram]:4 reloc; }\n\nd8PlusRaAddress: S8IMM(A)\t\t\t\t\tis S8IMM & A\t\t\t{tmp:$(REGISTER_SIZE) = A+S8IMM; export tmp; }\nd8PlusRaOrZeroAddress: S8IMM(RA_OR_ZERO)\tis S8IMM & RA_OR_ZERO\t{tmp:$(REGISTER_SIZE) = RA_OR_ZERO+S8IMM; export tmp; }\n\nsd4PlusRxAddr: SD4_VLE(RX_VLE)\tis SD4_VLE & RX_VLE\t\t\t\t{tmp:$(REGISTER_SIZE) = RX_VLE+SD4_VLE; export tmp; }\nsd4HPlusRxAddr: SD4_OFF(RX_VLE)\tis SD4_VLE & RX_VLE\t\t[SD4_OFF = SD4_VLE << 1;] {tmp:$(REGISTER_SIZE) = RX_VLE+SD4_OFF; export tmp; }\nsd4WPlusRxAddr: SD4_OFF(RX_VLE)\tis SD4_VLE & RX_VLE\t\t[SD4_OFF = SD4_VLE << 2;] {tmp:$(REGISTER_SIZE) = RX_VLE+SD4_OFF; export tmp; }\n\nOIMM: val\t\t\t\t\t\tis UI5_VLE [ val = UI5_VLE+1; ] { export *[const]:$(REGISTER_SIZE) val; }\n\n@if REGISTER_SIZE == \"4\"\nSCALE: val\t\t\t\t\t\tis BIT_10=1 & SCL_VLE & IMM8 [ val = (0xFFFFFFFF) & ~((0xFF-IMM8) << (SCL_VLE*8)); ] { export *[const]:4 val;}\nSCALE: val\t\t\t\t\t\tis BIT_10=0 & SCL_VLE & IMM8 [ val = (IMM8 << (SCL_VLE*8)); ] { export *[const]:4 val;}\n@else\nSCALE: val\t\t\t\t\t\tis BIT_10=1 & SCL_VLE & IMM8 [ val = (0xFFFFFFFFFFFFFFFF) & ~((0xFF-IMM8) << (SCL_VLE*8)); ] { export *[const]:8 val;}\nSCALE: val\t\t\t\t\t\tis BIT_10=0 & SCL_VLE & IMM8 [ val = IMM8 << (SCL_VLE*8); ] { export *[const]:8 val;}\n@endif\n\nSIMM16: val\t\t\t\t\t\tis IMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }\nSIMM20: val\t\t\t\t\t\tis IMM_0_10_VLE & IMM_16_20_VLE & SIMM_11_14_VLE [ val = (SIMM_11_14_VLE << 16 ) | (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:4 val; }\nIMM16: val\t\t\t\t\t\tis IMM_0_10_VLE & IMM_21_25_VLE [ val = (IMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }\nIMM16B: val\t\t\t\t\t\tis IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }\n\n:e_b addrBD24\t\t\t\t\tis $(ISVLE) & OP=30 & BIT_25=0 & LK=0 & addrBD24 {\n\tgoto addrBD24;\n}\n\n:e_bl addrBD24\t\t\t\t\tis $(ISVLE) & OP=30 & BIT_25=0 & LK=1 & addrBD24 {\n\tLR = inst_next;\n\tcall addrBD24;\n}\n\n:se_b addrBD8\t\t\t\t\tis $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=0 & addrBD8 {\n\tgoto addrBD8;\n}\n\n:se_bl addrBD8\t\t\t\t\tis $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=1 & addrBD8 {\n\tLR = inst_next;\n\tcall addrBD8;\n}\n\n# NOTE: For the conditional branches, the \"official\" mnemonics have just bc and bcl.\n# We use extended mnemonics so the display is understandable without having to cross-\n# reference multiple tables.\n:e_b^CC32 BI_CR_VLE, addrBD15\t\t\t\tis $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & BIT_L=0 & BI_CR_VLE & CC32 {\n\tif (CC32 == 0) goto inst_next;\n\tgoto addrBD15;\n}\n\n:e_b^CC32^\"l\" BI_CR_VLE, addrBD15\t\t\tis $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & BIT_L=0 & BI_CR_VLE & CC32 {\n\tif (CC32 == 0) goto inst_next;\n\tLR= inst_next;\n\tcall [addrBD15];\n}\n\n:e_b^CC32 addrBD15\t\t\t\tis $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & BIT_L=1 & CC32 {\n\tif (CC32 == 0) goto inst_next;\n\tgoto addrBD15;\n}\n\n:e_b^CC32^\"l\" addrBD15\t\t\tis $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & BIT_L=1 & CC32 {\n\tif (CC32 == 0) goto inst_next;\n\tLR= inst_next;\n\tcall [addrBD15];\n}\n\n:se_b^CC16 cr0, addrBD8\t\t\t\tis $(ISVLE) & OP5_VLE=28 & addrBD8 & cr0 & CC16 {\n\tif (CC16 == 0) goto inst_next;\n\tgoto addrBD8;\n}\n#######\n\n:se_bctr\t\t\t\t\t\tis $(ISVLE) & OP15_VLE=3 & LK0_VLE=0 {\n\ttmp:$(REGISTER_SIZE) = CTR & ~1;\n\tgoto [tmp];\t\n}\n\n:se_bctrl\t\t\t\t\t\tis $(ISVLE) & OP15_VLE=3 & LK0_VLE=1 {\n\tLR = inst_next;\t\n\ttmp:$(REGISTER_SIZE) = CTR & ~1;\n\tcall [tmp];\t\n}\n\n:se_blr\t\t\t\t\t\t\tis $(ISVLE) & OP15_VLE=2 & LK0_VLE=0 {\n\ttmp:$(REGISTER_SIZE) = LR & ~1;\n\treturn [tmp];\t\t\t\n}\n\n:se_blrl\t\t\t\t\t\tis $(ISVLE) & OP15_VLE=2 & LK0_VLE=1 {\t\n\ttmp:$(REGISTER_SIZE) = LR & ~1;\n\tLR = inst_next;\n\tcall [tmp];\t\t\t\n}\n\n:se_sc\t\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=2 {\n\ttmp:1 = 0;\n\tsyscall(tmp);\n}\n\n:e_sc LEV_VLE\t\t\t\t\tis $(ISVLE) & OP=31 & XOP_1_10=36 & BIT_0=0 & BITS_16_20=0 & BITS_21_25=0 & LEV_VLE {\n\ttmp:1 = LEV_VLE;\n\tsyscall(tmp);\n}\n\n:e_sc \t\t\t\t\t\t\tis $(ISVLE) & OP=31 & XOP_1_10=36 & BIT_0=0 & BITS_16_20=0 & BITS_21_25=0 & LEV_VLE=0 {\n\ttmp:1 = 0;\n\tsyscall(tmp);\n}\n\n:se_illegal\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=0 {\n\tillegal();\n}\n\n:se_rfmci\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=11 {\n\tMSR = returnFromMachineCheckInterrupt(MSR, spr23b); #MCSRR1\n\tlocal ra = spr23a; #MCSRR0\n\treturn[ra];\n}\n\n:se_rfci\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=9 {\n\tMSR = returnFromCriticalInterrupt(MSR, CSRR1);\n\tlocal ra = CSRR0;\n\treturn[ra];\n}\n\n:se_rfi\t\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=8 {\n\tMSR = returnFromInterrupt(MSR, SRR1);\n\tlocal ra = SRR0;\n\treturn[ra];\n}\n\n:se_rfdi\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=10 {\n\tMSR = returnFromDebugInterrupt(MSR, spr23f); #DSRR1\n\tlocal ra = spr23e; #DSRR0\n\treturn[ra];\n}\n\n:se_rfgi\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=12 {\n\tMSR = returnFromGuestInterrupt(MSR, spr17b); #GSRR1\n\tlocal ra = spr17a; #GSRR0\n\treturn[ra];\n}\n\n:e_crand CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=257 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,CC_OP & CC_B_OP);\n}\n\n:e_crandc CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0\n{\n\ttmp1:1 = !CC_B_OP;\n\tsetCrBit(CR_D,CR_D_CC,CC_OP & tmp1);\n}\n\n:e_creqv CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=289 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,CC_B_OP == CC_OP);\n}\n\n:e_crnand CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=225 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,!(CC_B_OP & CC_OP));\n}\n\n:e_crnor CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=33 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,!(CC_B_OP | CC_OP));\n}\n\n:e_cror\tCC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=449 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,(CC_B_OP | CC_OP));\n}\n\n:e_crorc CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=417 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,(CC_B_OP | (!CC_OP)));\n}\n\n:e_crxor CC_D_OP,CC_OP,CC_B_OP\tis $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=193 & BIT_0=0\n{\n\tsetCrBit(CR_D,CR_D_CC,(CC_B_OP ^ CC_OP));\n}\n\n:e_mcrf CRFD,CRFS\t\t\t\tis $(ISVLE) & OP=31 & CRFD & BITS_21_22=0 & CRFS & BITS_11_17=0 & XOP_1_10=16 & BIT_0=0 \n{\n\tCRFD = CRFS;\n}\n\n:e_lbz\tD,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=12 & D & dPlusRaOrZeroAddress\n{\n\tD = zext(*:1(dPlusRaOrZeroAddress));\t\n}\n\n:se_lbz RZ_VLE,sd4PlusRxAddr\tis $(ISVLE) & OP4_VLE=8 & RZ_VLE & sd4PlusRxAddr {\n\tRZ_VLE = zext(*:1(sd4PlusRxAddr));\t\n}\n\n:e_lbzu\tD,d8PlusRaAddress\t\tis $(ISVLE) & OP=6 & D & A & XOP_8_VLE=0 & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n\tD = zext(*:1(ea));\n\tA = ea;\n}\n\n# e_ldmvcsrrw 6 (0b0001_10) 0b00101 RA 0b0001_0000 D8\n:e_ldmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=5\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tloadReg(CSRR0);\n\tloadReg(CSRR1);\n}\n\n# e_ldmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0000 D8\n:e_ldmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=6\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tloadReg(spr23e); #DSRR0\n\tloadReg(spr23f); #DSRR1\n}\n\n# e_ldmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0000 D8\n:e_ldmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=0\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tloadReg(r0);\n\tloadReg(r3);\n\tloadReg(r4);\n\tloadReg(r5);\n\tloadReg(r6);\n\tloadReg(r7);\n\tloadReg(r8);\n\tloadReg(r9);\n\tloadReg(r10);\n\tloadReg(r11);\n\tloadReg(r12);\n}\n\n# e_ldmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0000 D8\n:e_ldmvsprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=1\n{\n\ttea = d8PlusRaOrZeroAddress;\n\t#TODO is there a better way to handle this, CR are 4 bit\n\t# so crall can't be used. And not much code accesses\n\t# CR in this way, also CRM_CR seems backwards?\n\t# loadReg(CR);\n\tlocal tmpCR:4 = *:4 tea;\n\tcr0 = zext(tmpCR[0,4]);\n\tcr1 = zext(tmpCR[4,4]);\n\tcr2 = zext(tmpCR[8,4]);\n\tcr3 = zext(tmpCR[12,4]);\n\tcr4 = zext(tmpCR[16,4]);\n\tcr5 = zext(tmpCR[20,4]);\n\tcr6 = zext(tmpCR[24,4]);\n\tcr7 = zext(tmpCR[28,4]);\n\ttea = tea + 4;\n\tloadReg(LR);\n\tloadReg(CTR);\n\tloadReg(XER);\n}\n\n# e_ldmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0000 D8\n:e_ldmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=4\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tloadReg(SRR0);\n\tloadReg(SRR1);\n}\n\n:e_lha\tD,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=14 & D & dPlusRaOrZeroAddress\n{\n\tD = sext(*:2(dPlusRaOrZeroAddress));\t\n}\n\n:e_lhz\tD,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=22 & D & dPlusRaOrZeroAddress\n{\n\tD = zext(*:2(dPlusRaOrZeroAddress));\t\n}\n\n:se_lhz RZ_VLE,sd4HPlusRxAddr\tis $(ISVLE) & OP4_VLE=10 & RZ_VLE & sd4HPlusRxAddr {\t\n\tRZ_VLE = zext(*:2(sd4HPlusRxAddr));\t\n}\n\n:e_lhau\tD,d8PlusRaAddress\t\tis $(ISVLE) & OP=6 & D & A & XOP_8_VLE=3 & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n\tD = sext(*:2(ea));\n\tA = ea;\n}\n\n:e_lhzu\tD,d8PlusRaAddress\t\tis $(ISVLE) & OP=6 & D & A & XOP_8_VLE=1 & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n\tD = zext(*:2(ea));\n\tA = ea;\n}\n\n:e_lwz\tD,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=20 & D & dPlusRaOrZeroAddress\n{\n\tD = zext(*:4(dPlusRaOrZeroAddress));\t\n}\n\n:se_lwz RZ_VLE,sd4WPlusRxAddr\tis $(ISVLE) & OP4_VLE=12 & RZ_VLE & sd4WPlusRxAddr {\t\n\tRZ_VLE = zext(*:4(sd4WPlusRxAddr));\t\n}\n\n:e_lwzu\tD,d8PlusRaAddress\t\tis $(ISVLE) & OP=6 & D & A & XOP_8_VLE=2 & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n\tD = zext(*:4(ea));\n\tA = ea;\n}\n\n:e_stb\tS,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=13 & S & dPlusRaOrZeroAddress\n{\n\t*:1(dPlusRaOrZeroAddress) = S:1;\n}\n\n:se_stb RZ_VLE,sd4PlusRxAddr\tis $(ISVLE) & OP4_VLE=9 & RZ_VLE & sd4PlusRxAddr {\t\n\t*:1(sd4PlusRxAddr) = RZ_VLE:1;\t\n}\n\n:e_stbu\tS,d8PlusRaAddress\t\tis $(ISVLE) & OP=6 & XOP_8_VLE=4 & S & A & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n\t*:1(ea) = S:1;\n\tA = ea;\n}\n\n:e_sth S,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=23 & S & dPlusRaOrZeroAddress\n{\n\t*:2(dPlusRaOrZeroAddress) = S:2;\n}\n\n:se_sth RZ_VLE,sd4HPlusRxAddr\tis $(ISVLE) & OP4_VLE=11 & RZ_VLE & sd4HPlusRxAddr {\t\n\t*:2(sd4HPlusRxAddr) = RZ_VLE:2;\t\n}\n\n:e_sthu S,d8PlusRaAddress\t\t\tis $(ISVLE) & OP=6 & XOP_8_VLE=5 & S & A & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n\t*:2(ea) = S:2;\n\tA = ea;\n}\n\n# e_stmvcsrrw 6 (0b0001_10) 0b00101 RA 0b0001_0001 D8\n:e_stmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=5\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tstoreReg(CSRR0);\n\tstoreReg(CSRR1);\n}\n\n# e_stmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0001 D8\n:e_stmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=6\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tstoreReg(spr23e); #DSRR0\n\tstoreReg(spr23f); #DSRR1\n}\n\n# e_stmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0001 D8\n:e_stmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=0\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tstoreReg(r0);\n\tstoreReg(r3);\n\tstoreReg(r4);\n\tstoreReg(r5);\n\tstoreReg(r6);\n\tstoreReg(r7);\n\tstoreReg(r8);\n\tstoreReg(r9);\n\tstoreReg(r10);\n\tstoreReg(r11);\n\tstoreReg(r12);\n}\n\n# e_stmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0001 D8\n:e_stmvsprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=1\n{\n\ttea = d8PlusRaOrZeroAddress;\n\t#TODO SEE TODO in e_ldmvsprw\n\t# storeReg(CR);\n\tlocal tmpCR:4 = 0;\n\ttmpCR = tmpCR | (zext(cr0 & 0xf) << 0);\n\ttmpCR = tmpCR | (zext(cr1 & 0xf) << 4);\n\ttmpCR = tmpCR | (zext(cr2 & 0xf) << 8);\n\ttmpCR = tmpCR | (zext(cr3 & 0xf) << 12);\n\ttmpCR = tmpCR | (zext(cr4 & 0xf) << 16);\n\ttmpCR = tmpCR | (zext(cr5 & 0xf) << 20);\n\ttmpCR = tmpCR | (zext(cr6 & 0xf) << 24);\n\ttmpCR = tmpCR | (zext(cr7 & 0xf) << 28);\n\t*:4 tea = tmpCR;\n\ttea = tea + 4;\n\tstoreReg(LR);\n\tstoreReg(CTR);\n\tstoreReg(XER);\n}\n\n# e_stmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0001 D8\n:e_stmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=4\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tstoreReg(SRR0);\n\tstoreReg(SRR1);\n}\n\n:e_stw S,dPlusRaOrZeroAddress\tis $(ISVLE) & OP=21 & S & dPlusRaOrZeroAddress\n{\n@ifdef BIT_64\n\t*:4(dPlusRaOrZeroAddress) = S:4;\n@else\n\t*:4(dPlusRaOrZeroAddress) = S;\n@endif\n}\n\n:se_stw RZ_VLE,sd4WPlusRxAddr\tis $(ISVLE) & OP4_VLE=13 & RZ_VLE & sd4WPlusRxAddr {\t\n@ifdef BIT_64\n\t*:4(sd4WPlusRxAddr) = RZ_VLE:4;\t\n@else\n\t*:4(sd4WPlusRxAddr) = RZ_VLE;\t\n@endif\n}\n\n:e_stwu S,d8PlusRaAddress\t\tis $(ISVLE) & OP=6 & XOP_8_VLE=6 & S & A & d8PlusRaAddress\n{\n\tea:$(REGISTER_SIZE) = d8PlusRaAddress;\n@ifdef BIT_64\n\t*:4(ea) = S:4;\n@else\n\t*:4(ea) = S;\n@endif\n\tA = ea;\n}\n\n:e_lmw\tD,d8PlusRaOrZeroAddress\tis $(ISVLE) & OP=6 & XOP_8_VLE=8 & D & BITS_21_25 & d8PlusRaOrZeroAddress & LDMR31 [ lsmul = BITS_21_25; ]\n{\t\n\ttea = d8PlusRaOrZeroAddress;\n\tbuild LDMR31;\n}\n\n:e_stmw\tS,d8PlusRaOrZeroAddress\tis $(ISVLE) & OP=6 & XOP_8_VLE=9 & S & BITS_21_25 & d8PlusRaOrZeroAddress & STMR31 [ lsmul = BITS_21_25; ]\n{\n\ttea = d8PlusRaOrZeroAddress;\n\tbuild STMR31;\n}\n\n:se_add RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=1 & BITS_8_9=0 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE + RY_VLE;\n}\n\n:e_add16i D,A,SIMM\t\t\t\tis $(ISVLE) & OP=7 & A & D & SIMM {\n\ttmp:2 = SIMM;\n\tD = A + sext(tmp);\n}\n\n:e_add2i. A,SIMM16\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=17 & A & SIMM16 {\n\tA = A + sext(SIMM16);\n\tcr0flags(A); \n}\n\n:e_add2is A,SIMM16\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=18 & A & SIMM16 {\n\ttmp:$(REGISTER_SIZE) = sext(SIMM16);\n\ttmp = tmp << 16;\n\tA = A + tmp;\n}\n\n:e_addi D,A,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=8 & BIT_11=0 & D & A & SCALE {\n\tD = A + SCALE;\n}\n\n:e_addi. D,A,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=8 & BIT_11=1 & D & A & SCALE {\n\tD = A + SCALE;\n\tcr0flags(D); \n}\n\n:se_addi RX_VLE,OIMM\t\t\tis $(ISVLE) & OP6_VLE=8 & BIT9_VLE=0 & RX_VLE & OIMM {\n\tRX_VLE = RX_VLE + OIMM;\n}\n\n:e_addic D,A,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=9 & BIT_11=0 & D & A & SCALE {\n\txer_ca = carry(A,SCALE);\n\tD = A + SCALE;\n}\n\n:e_addic. D,A,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=9 & BIT_11=1 & D & A & SCALE {\n\txer_ca = carry(A,SCALE);\n\tD = A + SCALE;\n\tcr0flags(D); \n}\n\n:se_sub RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=1 & BITS_8_9=2 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE - RY_VLE;\n}\n\n:se_subf RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=1 & BITS_8_9=3 & RX_VLE & RY_VLE {\n\tRX_VLE = RY_VLE - RX_VLE;\n}\n\n:e_subfic D,A,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=11 & BIT_11=0 & D & A & SCALE {\n\txer_ca = (A <= SCALE);\n\tD = SCALE - A;\t\n}\n\n:e_subfic. D,A,SCALE\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=11 & BIT_11=1 & D & A & SCALE {\n\txer_ca = (A <= SCALE);\n\tD = SCALE - A;\t\n\tcr0flags(D); \t\n}\n\n:se_subi RX_VLE,OIMM\t\t\tis $(ISVLE) & OP6_VLE=9 & BIT9_VLE=0 & RX_VLE & OIMM {\n\tRX_VLE = RX_VLE - OIMM;\n}\n\n:se_subi. RX_VLE,OIMM\t\t\tis $(ISVLE) & OP6_VLE=9 & BIT9_VLE=1 & RX_VLE & OIMM {\n\tRX_VLE = RX_VLE - OIMM;\n\tcr0flags(RX_VLE); \t\t\n}\n\n:e_mulli D,A,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_11_VLE=20 & D & A & SCALE {\n\ttmp1:16 = sext(A);\n\ttmp2:16 = sext(SCALE);\n\ttmpP:16 = tmp1 * tmp2;\n\tD = tmpP:$(REGISTER_SIZE);\n}\n\n:e_mull2i. A,SIMM16\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=20 & A & SIMM16 {\n\ttmp1:16 = sext(A);\n\ttmp2:16 = sext(SIMM16);\n\ttmpP:16 = tmp1 * tmp2;\n\tA = tmpP:$(REGISTER_SIZE);\n}\n\n:se_mullw RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=1 & BITS_8_9=1 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE * RY_VLE;\n}\n\n:se_neg RX_VLE\t\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=3 & RX_VLE {\n\tRX_VLE = ~RX_VLE + 1;\n}\n\n:se_btsti RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=25 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {\n\ttmp:$(REGISTER_SIZE) = (RX_VLE >> (0x1F - OIM5_VLE)) & 0x1;\n\tcr0flags(tmp);\n}\n\n:e_cmp16i. A,SIMM16\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=19 & A & SIMM16 {\n\ttmpA:4 = A:4;\n\ttmpB:4 = sext(SIMM16);\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n\n\n:e_cmpi BF_VLE,A,SCALE\t\t\tis $(ISVLE) & OP=6 & XOP_11_VLE=21 & BITS_23_25=0 & A & BF_VLE & SCALE {\n\ttmpA:4 = A:4;\n\ttmpB:4 = SCALE:4;\n\tBF_VLE = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n\n:se_cmp RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=3 & BITS_8_9=0 & RX_VLE & RY_VLE {\n\ttmpA:4 = RX_VLE:4;\n\ttmpB:4 = RY_VLE:4;\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\n}\n\n:se_cmpi RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=10 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {\n\ttmpA:4 = RX_VLE:4;\n\ttmpB:4 = OIM5_VLE;\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\n}\n\n:e_cmpl16i. A,IMM16\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=21 & A & IMM16 {\n\ttmpA:4 = A:4;\n\ttmpB:4 = zext(IMM16);\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\n}\n\n:e_cmpli BF_VLE,A,SCALE\t\t\tis $(ISVLE) & OP=6 & XOP_11_VLE=21 & BITS_23_25=1 & A & BF_VLE & SCALE {\n\ttmpA:4 = A:4;\n\ttmpB:4 = SCALE:4;\n\tBF_VLE = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\n}\n\n:se_cmpl RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=3 & BITS_8_9=1 & RX_VLE & RY_VLE {\n\ttmpA:4 = RX_VLE:4;\n\ttmpB:4 = RY_VLE:4;\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\n}\n\n:se_cmpli RX_VLE,OIMM\t\tis $(ISVLE) & OP6_VLE=8 & BIT9_VLE=1 & RX_VLE & OIMM {\n\ttmpA:4 = RX_VLE:4;\n\ttmpB:4 = OIMM:4;\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\t\n}\n\n:e_cmph CRFD,A,B\t\t\t\t\tis $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=14 & A & B & CRFD {\n\ttmpA:2 = A:2;\n\ttmpB:2 = B:2;\n\tCRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\t\n}\n\n:se_cmph RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=3 & BITS_8_9=2 & RX_VLE & RY_VLE {\n\ttmpA:2 = RX_VLE:2;\n\ttmpB:2 = RY_VLE:2;\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\n}\n\n:e_cmph16i. A,SIMM16\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=22 & A & SIMM16 {\n\ttmpA:2 = A:2;\n\ttmpB:2 = SIMM16;\n\tcr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\n}\n\n:e_cmphl CRFD,A,B\t\t\t\tis $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=46 & A & B & CRFD {\n\ttmpA:2 = A:2;\n\ttmpB:2 = B:2;\n\ttmpC:1 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\n\tCRFD = tmpC;\t\t\n}\n\n:se_cmphl RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=3 & BITS_8_9=3 & RX_VLE & RY_VLE {\n\ttmpA:2 = RX_VLE:2;\n\ttmpB:2 = RY_VLE:2;\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\t\n}\n\n:e_cmphl16i. A,IMM16\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=23 & A & IMM16 {\n\ttmpA:2 = A:2;\n\ttmpB:2 = IMM16;\n\tcr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);\t\t\t\n}\n\n:e_and2i. D,IMM16B\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=25 & D & IMM16B {\n\tD = D & zext(IMM16B);\n\tcr0flags(D); \t\t\n}\n\n:e_and2is. D,IMM16B\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=29 & D & IMM16B {\n\ttmp:$(REGISTER_SIZE) = zext(IMM16B);\n\ttmp = tmp << 16;\n\tD = D & tmp;\n\tcr0flags(D); \t\t\n}\n\n:e_andi A,S,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=12 & BIT_11=0 & S & A & SCALE {\n\tA = S & SCALE;\n}\n\n:e_andi. A,S,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=12 & BIT_11=1 & S & A & SCALE {\n\tA = S & SCALE;\n\tcr0flags(A); \t\t\t\n}\n\n:se_andi RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=11 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {\n\ttmp:1 = OIM5_VLE;\n\tRX_VLE = RX_VLE & zext(tmp);\n}\n\n:e_or2i D,IMM16B\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=24 & D & IMM16B {\n\tD = D | zext(IMM16B);\n}\n\n:e_or2is D,IMM16B\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=26 & D & IMM16B {\n\ttmp:$(REGISTER_SIZE) = zext(IMM16B);\n\ttmp = tmp << 16;\n\tD = D | tmp;\t\n}\n\n:e_nop\t\t\t\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=13 & BITS_1_10=0 & BIT_0=0 & S=0 & A=0 {\n\t\n}\n\n:e_ori A,S,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=13 & BIT_11=0 & S & A & SCALE {\n\tA = S | SCALE;\n}\n\n\n:e_ori. A,S,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=13 & BIT_11=1 & S & A & SCALE {\n\tA = S | SCALE;\n\tcr0flags(A); \t\t\t\t\n}\n\n:e_xori A,S,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=14 & BIT_11=0 & S & A & SCALE {\n\tA = S ^ SCALE;\t\n}\n\n:e_xori. A,S,SCALE\t\t\t\tis $(ISVLE) & OP=6 & XOP_12_VLE=14 & BIT_11=1 & S & A & SCALE {\n\tA = S ^ SCALE;\t\n\tcr0flags(A); \t\t\t\t\t\n}\n\n:se_and RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=17 & BIT9_VLE=1 & BIT8_VLE=0 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE & RY_VLE;\n}\n\n:se_and. RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=17 & BIT9_VLE=1 & BIT8_VLE=1 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE & RY_VLE;\t\n\tcr0flags(RX_VLE); \t\t\t\t\t\n}\n\n:se_andc RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=17 & BITS_8_9=1 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE & ~RY_VLE;\t\n}\n\n:se_nop\t\t\t\t\t\t\tis $(ISVLE) & OP6_VLE=17 & BITS_8_9=0 & RX_VLE=0 & RY_VLE=0 {\n\n}\n\n:se_or RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=17 & BITS_8_9=0 & RX_VLE & RY_VLE {\n\tRX_VLE = RX_VLE | RY_VLE;\t\n}\n\n:se_not RX_VLE\t\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=2 & RX_VLE {\n\tRX_VLE = ~RX_VLE;\n}\n\n:se_bclri RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=24 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {\n\ttmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE;\n\ttmp = ~tmp;\n\tRX_VLE = RX_VLE & tmp;\n}\n\n:se_bgeni RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=24 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {\n\tRX_VLE = 0x80000000 >> OIM5_VLE;\n}\n\n:se_bmaski RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=11 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {\n\tRX_VLE = ~0;\n\tsa:4 = (8 * $(REGISTER_SIZE) - OIM5_VLE) * zext( OIM5_VLE != 0:1 );\n\tRX_VLE = RX_VLE >> sa;\n}\n\n:se_bseti RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=25 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {\n\ttmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE;\n\tRX_VLE = RX_VLE | tmp;\t\n}\n\n:se_extsb RX_VLE\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=13 & RX_VLE {\n\tRX_VLE = sext(RX_VLE:1);\n}\n\n:se_extsh RX_VLE\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=15 & RX_VLE {\n\tRX_VLE = sext(RX_VLE:2);\t\n}\n\n:se_extzb RX_VLE\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=12 & RX_VLE {\n\tRX_VLE = zext(RX_VLE:1);\t\n}\n\n:se_extzh RX_VLE\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=14 & RX_VLE {\n\tRX_VLE = zext(RX_VLE:2);\t\n}\n\n:e_li D,SIMM20\t\t\t\t\tis $(ISVLE) & OP=28 & BIT_15=0 & D & SIMM20 {\n\tD = sext(SIMM20);\n}\n\n:se_li RX_VLE,OIM7_VLE\t\t\tis $(ISVLE) & OP5_VLE=9 & RX_VLE & OIM7_VLE {\n\tRX_VLE = OIM7_VLE;\n}\n\n:e_lis D,IMM16B\t\t\t\t\tis $(ISVLE) & OP=28 & XOP_11_VLE=28 & D & IMM16B {\n\ttmp:$(REGISTER_SIZE) = zext(IMM16B);\n\tD = tmp << 16;\n}\n\n:se_mfar RX_VLE,ARY_VLE\t\t\tis $(ISVLE) & OP6_VLE=0 & BITS_8_9=3 & RX_VLE & ARY_VLE {\n\tRX_VLE = ARY_VLE;\n}\n\n:se_mr RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=0 & BITS_8_9=1 & RX_VLE & RY_VLE {\n\tRX_VLE = RY_VLE;\n}\n\n:se_mtar ARX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=0 & BITS_8_9=2 & ARX_VLE & RY_VLE {\n\tARX_VLE = RY_VLE;\n}\n\n:e_rlw A,S,B\t\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=280 & A & B & S {\n\ttmpB:1 = B[0,5];\n\ttmpS:4 = S:4;\n\ttmpA:4 = (tmpS << tmpB) | (tmpS >> (32 - tmpB));\n\tA = zext(tmpA);\n}\n\n:e_rlw. A,S,B\t\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=280 & A & B & S {\n\ttmpB:1 = B[0,5];\n\ttmpS:4 = S:4;\n\ttmpA:4 = (tmpS << tmpB) | (tmpS >> (32 - tmpB));\n\tA = zext(tmpA);\n\tcr0flags(A); \t\t\t\t\t\t\n}\n\n:e_rlwi A,S,SHL\t\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=312 & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL));\n\tA = zext(tmpA);\t\n}\n\n:e_rlwi. A,S,SHL\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=312 & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL));\n\tA = zext(tmpA);\t\n\tcr0flags(A); \t\t\t\t\t\t\t\n}\n\n# The manual uses MB instead of MBL here, but because the \"MB\" symbol is already taken, MBL it is\n:e_rlwimi A,S,SHL,MBL,ME\t\t\tis $(ISVLE) & OP=29 & BIT_0=0 & MBL & ME & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL));\n\n\ttmpM1:4 = (~0:4) << MBL;\n\ttmpM1 = tmpM1 >> ((31-ME) + MBL);\n\ttmpM1 = tmpM1 << (31-ME);\n\n\ttmpM2:4 = (~0:4) << ME;\n\ttmpM2 = tmpM2 >> ((31-MBL) + ME);\n\ttmpM2 = tmpM2 << (31-MBL);\n\ttmpM2 = ~tmpM2;\n\n\tlocal invert = (ME:1 < MBL:1);\n\ttmpM:4 = (zext(invert == 0)*tmpM1) + (zext(invert == 1)*tmpM2);\n\tA = zext(tmpA & tmpM) | (A & zext(~tmpM));\t\n}\n\n:e_rlwinm A,S,SHL,MBL,ME\t\t\tis $(ISVLE) & OP=29 & BIT_0=1 & MBL & ME & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL));\n\n\ttmpM1:4 = (~0:4) << MBL;\n\ttmpM1 = tmpM1 >> ((31-ME) + MBL);\n\ttmpM1 = tmpM1 << (31-ME);\n\n\ttmpM2:4 = (~0:4) << ME;\n\ttmpM2 = tmpM2 >> ((31-MBL) + ME);\n\ttmpM2 = tmpM2 << (31-MBL);\n\ttmpM2 = ~tmpM2;\n\n\tlocal invert = (ME:1 < MBL:1);\n\ttmpM:4 = (zext(invert == 0)*tmpM1) + (zext(invert == 1)*tmpM2);\n\tA = zext(tmpA & tmpM);\t\t\n}\n\n:e_slwi A,S,SHL\t\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=56 & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpS = tmpS << SHL;\n\tA = zext(tmpS);\t\n}\n\n:e_slwi. A,S,SHL\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=56 & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpS = tmpS << SHL;\n\tA = zext(tmpS);\t\n\tcr0flags(A); \t\t\t\t\n}\n\n:se_slwi RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=27 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {\n\ttmpX:4 = RX_VLE:4;\n\ttmpX = tmpX << OIM5_VLE;\n\tRX_VLE = zext(tmpX);\n}\n\n:se_slw RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=16 & BITS_8_9=2 & RX_VLE & RY_VLE {\n\ttmpX:4 = RX_VLE:4;\n\ttmpS:1 = RY_VLE[0,6];\n\ttmpX = tmpX << tmpS;\n\tRX_VLE = zext(tmpX);\n}\n\n:se_srawi RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=26 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {\n\ttmpX:4 = RX_VLE:4;\n\ttmpX = tmpX s>> OIM5_VLE;\n\tRX_VLE = sext(tmpX);\n\txer_ca = (RX_VLE s< 0) & (OIM5_VLE:1 != 0);\n}\n\n:se_sraw RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=16 & BITS_8_9=1 & RX_VLE & RY_VLE {\n\ttmpX:4 = RX_VLE:4;\n\ttmpS:1 = RY_VLE[0,5];\n\ttmpX = tmpX s>> tmpS;\n\tRX_VLE = sext(tmpX);\n\txer_ca = (RX_VLE s< 0) & (tmpS != 0);\n}\n\n:e_srwi A,S,SHL\t\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=568 & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpS = tmpS >> SHL;\n\tA = zext(tmpS);\t\t\n}\n\n:e_srwi. A,S,SHL\t\t\t\tis $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=568 & A & SHL & S {\n\ttmpS:4 = S:4;\n\ttmpS = tmpS >> SHL;\n\tA = zext(tmpS);\t\t\t\n\tcr0flags(A); \t\t\t\t\n}\n\n:se_srwi RX_VLE,OIM5_VLE\t\tis $(ISVLE) & OP6_VLE=26 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {\n\ttmpX:4 = RX_VLE:4;\n\ttmpX = tmpX >> OIM5_VLE;\n\tRX_VLE = zext(tmpX);\n}\n\n:se_srw RX_VLE,RY_VLE\t\t\tis $(ISVLE) & OP6_VLE=16 & BITS_8_9=0 & RX_VLE & RY_VLE {\n\ttmpX:4 = RX_VLE:4;\n\ttmpS:1 = RY_VLE[0,5];\n\ttmpX = tmpX >> tmpS;\n\tRX_VLE = zext(tmpX);\t\n}\n\n:se_mfctr RX_VLE\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=10 & RX_VLE {\n\tRX_VLE = CTR;\n}\n\n:se_mtctr RX_VLE\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=11 & RX_VLE {\n\tCTR = RX_VLE;\n}\n\n:se_mflr RX_VLE\t\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=8 & RX_VLE {\n\tRX_VLE = LR;\n}\n\n:se_mtlr RX_VLE\t\t\t\t\tis $(ISVLE) & OP6_VLE=0 & XOR_VLE=9 & RX_VLE {\n\tLR = RX_VLE;\n}\n\n:se_isync\t\t\t\t\t\tis $(ISVLE) & OP16_VLE=1 {\n\tinstructionSynchronize();\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/quicciii.sinc", "content": "# These instructions show up in the Freescale PowerQUICC III instruction manual\n# (not present elsewhere)\n \ndefine pcodeop dataCacheBlockClearLock;\ndefine pcodeop prefetchDataCacheBlockLockSet;\ndefine pcodeop prefetchDataCacheBlockLockSetX;\ndefine pcodeop debuggerNotifyHalt;\ndefine pcodeop instructionCacheBlockClearLock;\ndefine pcodeop queryInstructionCacheBlockLock;\ndefine pcodeop prefetchInstructionCacheBlockLockSetX;\ndefine pcodeop moveFromAPIDIndirect;\ndefine pcodeop moveFromPerformanceMonitorRegister;\ndefine pcodeop moveToPerformanceMonitorRegister;\ndefine pcodeop invalidateTLB;\n\n#dcblc 0,0,r0\t\t#FIXME\n:dcblc CT,RA_OR_ZERO,B\tis OP=31 & CT & B & XOP_1_10=390 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tdataCacheBlockClearLock(ea);\n}\n\n#dcbtls 0,0,r0\t\t#FIXME\n:dcbtls CT,RA_OR_ZERO,B\tis OP=31 & CT & B & XOP_1_10=166 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tprefetchDataCacheBlockLockSet(ea);\n}\n\n#dcbtstls 0,0,r0\t\t#FIXME\n:dcbtstls CT,RA_OR_ZERO,B\tis OP=31 & CT & B & XOP_1_10=134 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tprefetchDataCacheBlockLockSetX(ea);\n}\n\n#dnh 0,0\t\t#FIXME\n:dnh DUI,DUIS\tis $(NOTVLE) & OP=19 & DUI & DUIS & XOP_1_10=198 & BIT_0=0\n{\n\tdebuggerNotifyHalt(DUI:1,DUIS:2);\n}\n\n#icblc 0,0,r0\t\t#FIXME\n:icblc CT,RA_OR_ZERO,B\tis OP=31 & CT & B & XOP_1_10=230 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tinstructionCacheBlockClearLock(CT:1,ea);\n}\n\n:icblq CT,RA_OR_ZERO,B\tis OP=31 & CT & B & XOP_1_10=198 & BIT_0=1 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tcr0 = queryInstructionCacheBlockLock(CT:1,ea);\n}\n\n#icbtls 0,0,r0\t\t#FIXME\n:icbtls CT,RA_OR_ZERO,B\tis OP=31 & CT & B & XOP_1_10=486 & BIT_0=0 & RA_OR_ZERO\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tprefetchInstructionCacheBlockLockSetX(ea);\n}\n\n:isel^CC_X_OPm D,RA_OR_ZERO,B,CC_X_OP is OP=31 & D & RA_OR_ZERO & B & CC_X_OP & CC_X_OPm & XOP_1_5=15\n{\n\tlocal tmp:$(REGISTER_SIZE) = RA_OR_ZERO;\n\tD = B;\n\tif (!CC_X_OP) goto inst_next;\n\tD = tmp;\n# D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B);\n}\n\n#mfapidi r0,r1 #FIXME\n:mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275\n{ \n\tD = moveFromAPIDIndirect(A);\n}\n\npmrn: pmr is BITS_16_20 & BITS_11_15 [ pmr = BITS_11_15 << 5 | BITS_16_20; ] { tmp:2 = pmr; export tmp; }\n\n#mfpmr r0,? #FIXME\n:mfpmr D,pmrn is OP=31 & D & pmrn & XOP_1_10=334 & BIT_0=0\n{ \n\tD = moveFromPerformanceMonitorRegister(pmrn);\n}\n\n#mtpmr r0,? #FIXME\n:mtpmr pmrn,S is OP=31 & S & pmrn & XOP_1_10=462 & BIT_0=0\n{ \n\tmoveToPerformanceMonitorRegister(pmrn, S);\n}\n\n#rfdi #FIXME\n:rfdi is $(NOTVLE) & OP=19 & XOP_1_10=39\n{ \n\tMSR = returnFromDebugInterrupt(MSR, spr23f); #DSRR1\n\tlocal ra = spr23e; #DSRR0\n\treturn[ra];\n}\n\n#rfmci #FIXME\n:rfmci is $(NOTVLE) & OP=19 & XOP_0_10=76\n{ \n\tMSR = returnFromMachineCheckInterrupt(MSR, spr23b); #MCSRR1\n\tlocal ra = spr23a; #MCSRR0\n\treturn[ra];\n}\n\n\n# PowerISA II: 6.11.4.9 TLB Management Instructions\n# CMT: TLB Invalidate Local Indexed [Category: Embedded.Phased In]]\n# FORM: X-form\ndefine pcodeop TLBInvalidateLocalIndexed; # Outputs/affect TBD\n:tlbilx BITS_21_22,RA_OR_ZERO,RB_OR_ZERO is $(NOTVLE) & OP=31 & CRFD=0 & BITS_21_22 & RA_OR_ZERO & RB_OR_ZERO & XOP_1_10=18 & BIT_0=0 { \n\tTLBInvalidateLocalIndexed(BITS_21_22:1,RA_OR_ZERO,RB_OR_ZERO);\n}\n\n#tlbivax 0,r0 #FIXME\n:tlbivax RA_OR_ZERO,B\tis OP=31 & RA_OR_ZERO & B & XOP_1_10=786\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tinvalidateTLB(ea);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/stmwInstructions.sinc", "content": "STMR0:\t\tis lsmul=1 {}\nSTMR0:\t\tis epsilon { storeReg(r0); }\n\nSTMR1:\t\tis lsmul=2 {}\nSTMR1:\t\tis STMR0 { build STMR0; storeReg(r1); }\n\nSTMR2:\t\tis lsmul=3 {}\nSTMR2:\t\tis STMR1 { build STMR1; storeReg(r2); }\n\nSTMR3:\t\tis lsmul=4 {}\nSTMR3:\t\tis STMR2 { build STMR2; storeReg(r3); }\n\nSTMR4:\t\tis lsmul=5 {}\nSTMR4:\t\tis STMR3 { build STMR3; storeReg(r4); }\n\nSTMR5:\t\tis lsmul=6 {}\nSTMR5:\t\tis STMR4 { build STMR4; storeReg(r5); }\n\nSTMR6:\t\tis lsmul=7 {}\nSTMR6:\t\tis STMR5 { build STMR5; storeReg(r6); }\n\nSTMR7:\t\tis lsmul=8 {}\nSTMR7:\t\tis STMR6 { build STMR6; storeReg(r7); }\n\nSTMR8:\t\tis lsmul=9 {}\nSTMR8:\t\tis STMR7 { build STMR7; storeReg(r8); }\n\nSTMR9:\t\tis lsmul=10 {}\nSTMR9:\t\tis STMR8 { build STMR8; storeReg(r9); }\n\nSTMR10:\t\tis lsmul=11 {}\nSTMR10:\t\tis STMR9 { build STMR9; storeReg(r10); }\n\nSTMR11:\t\tis lsmul=12 {}\nSTMR11:\t\tis STMR10 { build STMR10; storeReg(r11); }\n\nSTMR12:\t\tis lsmul=13 {}\nSTMR12:\t\tis STMR11 { build STMR11; storeReg(r12); }\n\nSTMR13:\t\tis lsmul=14 {}\nSTMR13:\t\tis STMR12 { build STMR12; storeReg(r13); }\n\nSTMR14:\t\tis lsmul=15 {}\nSTMR14:\t\tis STMR13 { build STMR13; storeReg(r14); }\n\nSTMR15:\t\tis lsmul=16 {}\nSTMR15:\t\tis STMR14 { build STMR14; storeReg(r15); }\n\nSTMR16:\t\tis lsmul=17 {}\nSTMR16:\t\tis STMR15 { build STMR15; storeReg(r16); }\n\nSTMR17:\t\tis lsmul=18 {}\nSTMR17:\t\tis STMR16 { build STMR16; storeReg(r17); }\n\nSTMR18:\t\tis lsmul=19 {}\nSTMR18:\t\tis STMR17 { build STMR17; storeReg(r18); }\n\nSTMR19:\t\tis lsmul=20 {}\nSTMR19:\t\tis STMR18 { build STMR18; storeReg(r19); }\n\nSTMR20:\t\tis lsmul=21 {}\nSTMR20:\t\tis STMR19 { build STMR19; storeReg(r20); }\n\nSTMR21:\t\tis lsmul=22 {}\nSTMR21:\t\tis STMR20 { build STMR20; storeReg(r21); }\n\nSTMR22:\t\tis lsmul=23 {}\nSTMR22:\t\tis STMR21 { build STMR21; storeReg(r22); }\n\nSTMR23:\t\tis lsmul=24 {}\nSTMR23:\t\tis STMR22 { build STMR22; storeReg(r23); }\n\nSTMR24:\t\tis lsmul=25 {}\nSTMR24:\t\tis STMR23 { build STMR23; storeReg(r24); }\n\nSTMR25:\t\tis lsmul=26 {}\nSTMR25:\t\tis STMR24 { build STMR24; storeReg(r25); }\n\nSTMR26:\t\tis lsmul=27 {}\nSTMR26:\t\tis STMR25 { build STMR25; storeReg(r26); }\n\nSTMR27:\t\tis lsmul=28 {}\nSTMR27:\t\tis STMR26 { build STMR26; storeReg(r27); }\n\nSTMR28:\t\tis lsmul=29 {}\nSTMR28:\t\tis STMR27 { build STMR27; storeReg(r28); }\n\nSTMR29:\t\tis lsmul=30 {}\nSTMR29:\t\tis STMR28 { build STMR28; storeReg(r29); }\n\nSTMR30:\t\tis lsmul=31 {}\nSTMR30:\t\tis STMR29 { build STMR29; storeReg(r30); }\n\nSTMR31:\t\tis STMR30 { build STMR30; storeReg(r31); }\n\n:stmw\tS,dPlusRaOrZeroAddress\tis $(NOTVLE) & OP=47 & S & BITS_21_25 & dPlusRaOrZeroAddress & STMR31 [ lsmul = BITS_21_25; ]\n{\n\ttea = dPlusRaOrZeroAddress;\n\tbuild STMR31;\n}\n\n" }, { "path": "pypcode/processors/PowerPC/data/languages/stswiInstructions.sinc", "content": "#stswi\tr5,r3,0x02 7c a4 14 aa\n#stswi r5,r4,0x08 7c a4 44 aa\n\n\nDYN_S1: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 1)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_S2: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 2)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_S3: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 3)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_S4: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 4)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_S5: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 5)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_S6: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 6)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\nDYN_S7: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 7)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=0 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 & DYN_S7\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n storeRegister(DYN_S5,ea);\n storeRegister(DYN_S6,ea);\n storeRegister(DYN_S7,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=0 & BH & XOP_1_10=725 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n sa:1 = BH;\n storeRegisterPartial(S,ea,sa);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=1 & BH=0 & XOP_1_10=725 & BIT_0=0\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=1 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S1,ea,sa);\n}\n\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=2 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=2 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S2,ea,sa);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=3 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=3 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S3,ea,sa);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=4 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=4 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S4,ea,sa);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=5 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=5 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S5,ea,sa);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=6 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n storeRegister(DYN_S5,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=6 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n storeRegister(DYN_S5,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S6,ea,sa);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=7 & BH=0 & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n storeRegister(DYN_S5,ea);\n storeRegister(DYN_S6,ea);\n}\n\n:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=7 & BH & XOP_1_10=725 & BIT_0=0\n & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 & DYN_S7\n{\n ea:$(REGISTER_SIZE) = RA_OR_ZERO;\n storeRegister(S,ea);\n storeRegister(DYN_S1,ea);\n storeRegister(DYN_S2,ea);\n storeRegister(DYN_S3,ea);\n storeRegister(DYN_S4,ea);\n storeRegister(DYN_S5,ea);\n storeRegister(DYN_S6,ea);\n sa:1 = BH;\n storeRegisterPartial(DYN_S7,ea,sa);\n}\n" }, { "path": "pypcode/processors/PowerPC/data/languages/vsx.sinc", "content": "# Source for information on instructions:\n# PowerISA_V2.06B_PUBLIC.pdf (dated: July 23, 2010)\n# and binutils-2.21.1\n\n# version 1.0\n\n# ==========================================================================================================\n# VSX use of XA,XB,XC,XT\n# ==========================================================================================================\n# PowerPC VSX allows for VSX registers values to come from a combination of 2 different fields \n# XA is the value of A and AX concatenated. (A has 5 bits and AX 1 so allows for 6 bits or 64 registers).\n# XB is the value of B and BX concatenated. (B has 5 bits and BX 1 so allows for 6 bits or 64 registers).\n# XC is the value of C and CX concatenated. (C has 5 bits and CX 1 so allows for 6 bits or 64 registers).\n# XT is the value of T and TX concatenated. (T has 5 bits and TX 1 so allows for 6 bits or 64 registers).\n#\n# NOTE: A,B,C,T are all 5 bits long and AX,BX,CX,TX are all 1 bit long.\n# \n# In order to print the registers defined in XA,XB,XC,XT we need to play some tricks.\n# Normally you use a \"attach variables [ field ...] [ name1 ... ]; to attach names to fields but because\n# we need to attach names to 2 fields and that is not directly supported in sleigh.\n# \n# We attach the low registers (0 to 31) to fields that overlap the normal A,B,C,T named Avsa, Bvsa, Bvsa, Bvsa.\n# We attach the high registers (31 to 63) to fields that overlap the normal A,B,C,T named Avsb, Bvsb, Bvsb, Bvsb.\n#\n# Then we make constructors dependent on the AX,BX,CX,TX values to switch between them as needed. \n#define token instr(32)\n#...\n# support VSX args\n#\tAvsa=(16,20)\n#\tAvsb=(16,20)\n#\tBvsa=(11,15)\n#\tBvsb=(11,15)\n#\tCvsa=(6,10)\n#\tCvsb=(6,10)\n#\tTvsa=(21,25)\n#\tTvsb=(21,25)\n#...\n#;\n# Attach low VSX registers \nattach variables [ Avsa Bvsa Cvsa Svsa Tvsa ]\n\t[ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15 \n vs16 vs17 vs18 vs19 vs20 vs21 vs22 vs23 vs24 vs25 vs26 vs27 vs28 vs29 vs30 vs31 \n ];\n# Attach hi VSX registers\nattach variables [ Avsb Bvsb Cvsb Svsb Tvsb ]\n\t[ vs32 vs33 vs34 vs35 vs36 vs37 vs38 vs39 vs40 vs41 vs42 vs43 vs44 vs45 vs46 vs47\n vs48 vs49 vs50 vs51 vs52 vs53 vs54 vs55 vs56 vs57 vs58 vs59 vs60 vs61 vs62 vs63 \n ];\n \nattach variables [ Svsbx Tvsbx ]\n\t[ vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 \n\t vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0\n vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 \n vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 \t\n\t];\nXA: Avsa is Avsa & AX=0 { export Avsa; } # Low register version of XA (i.e A and AX fields)\nXA: Avsb is Avsb & AX=1 { export Avsb; } # Hi register version of XA (i.e A and AX fields)\nXB: Bvsa is Bvsa & BX=0 { export Bvsa; } # Low register version of XB (i.e B and BX fields)\nXB: Bvsb is Bvsb & BX=1 { export Bvsb; } # Hi register version of XB (i.e B and BX fields)\nXC: Cvsa is Cvsa & CX=0 { export Cvsa; } # Low register version of XC (i.e C and CX fields)\nXC: Cvsb is Cvsb & CX=1 { export Cvsb; } # Hi register version of XC (i.e C and CX fields)\nXS: Svsa is Svsa & SX=0 { export Svsa; }\nXS: Svsb is Svsb & SX=1 { export Svsb; }\nXS3: Svsa is Svsa & SX3=0 { export Svsa; }\nXS3: Svsb is Svsb & SX3=1 { export Svsb; }\nXT: Tvsa is Tvsa & TX=0 { export Tvsa; } # Low register version of XT (i.e T and AT fields)\nXT: Tvsb is Tvsb & TX=1 { export Tvsb; } # Hi register version of XT (i.e T and AT fields)\nXT3: Tvsa is Tvsa & TX3=0 { export Tvsa; } # Low register version of XT (i.e T and AT fields)\nXT3: Tvsb is Tvsb & TX3=1 { export Tvsb; } # Hi register version of XT (i.e T and AT fields)\n\nXSF: fS is fS & SX=0 { export fS; }\nXSF: Svsbx is Svsbx & SX=1 { export Svsbx; }\nXTF: fT is fT & TX=0 { export fT; } \nXTF: Tvsbx is Tvsbx & TX=1 { export Tvsbx; } \n\n\nDBUILD: val\t\tis DX & DM2 & DC6 [ val = (DC6 << 6) | (DM2 << 5) | DX; ] { export *[const]:1 val; }\n# ==========================================================================================================\n# ==========================================================================================================\n\ndefine pcodeop lxvdsxOp;\n# ISA-info: lxvdsx - Form \"XX1\" Page 339 Category \"VSX\"\n# binutils: vsx.d: 8:\t7d 0a a2 99 \tlxvdsx vs40,r10,r20\n:lxvdsx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=332 & TX { XT = lxvdsxOp(A,B); } \n\n# lxsdx XT,RA,RB\n# ISA-info: lxsdx - Form \"XX1\" Page 338 Category \"VSX\"\n# binutils: vsx.d: 0:\t7d 0a a4 99 \tlxsdx vs40,r10,r20\n:lxsdx XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=588 & TX {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tXT[0,64] = *:8 ea;\n}\n\n# name\t lxvd2x\t code\t 7c000698\t mask\t fe0700fc00000000\t flags\t @VSX \t operands\t69\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:lxvd2x XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=844 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tXT[64,64] = *:8 ea;\n\tXT[0,64] = *:8 (ea+8);\n}\n\ndefine pcodeop stxsdxOp;\n# ISA-info: stxsdx - Form \"XX1\" Page 340 Category \"VSX\"\n# binutils: vsx.d: 10:\t7d 0a a5 99 \tstxsdx vs40,r10,r20\n:stxsdx XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=716 & TX {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:8 EA = stxsdxOp(RA_OR_ZERO,B);\n} \n\n# name\t stxvd2x\t code\t 7c000798\t mask\t fe0700fc00000000\t flags\t @VSX \t operands\t69\t31\t38\t0\t0\t0\t0\t0\t \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n:stxvd2x XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=972 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*:8 ea = XS(8);\n\t*:8 (ea+8) = XS:8;\n} \n\n# ISA-cmt: lxvw4x - Load VSR Vector Word*4 Indexed\n# ISA-info: lxvw4x - Form \"XX1\" Page 339 Category \"VSX\"\n# binutils: vsx.d: c:\t7d 0a a6 19 \tlxvw4x vs40,r10,r20\n:lxvw4x XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=780 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tXT[96,32] = *:4 ea;\n\tXT[64,32] = *:4 (ea + 4); \n\tXT[32,32] = *:4 (ea + 8); \n\tXT[0,32] = *:4 (ea + 12); \n} \n\n# ISA-cmt: stxvw4x - Store VSR Vector Word*4 Indexed\n# ISA-info: stxvw4x - Form \"XX1\" Page 341 Category \"VSX\"\n# binutils: vsx.d: 18:\t7d 0a a7 19 \tstxvw4x vs40,r10,r20\n:stxvw4x XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=908 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*:16 ea = XS;\n} \n\n# ISA-cmt: xxsldwi - VSX Shift Left Double by Word Immediate\n# ISA-info: xxsldwi - Form \"XX3\" Page 501 Category \"VSX\"\n# binutils: vsx.d: 270:\tf1 12 e2 17 \txxsldwi vs40,vs50,vs60,2\n:xxsldwi XT,XA,XB,SHW is $(NOTVLE) & OP=60 & BIT_10 & SHW & BITS_3_7=2 & XA & XB & XT {\n\ttmp:32 = (zext(XA) << 128) | zext(XB);\n\ttmp = tmp >> ((7 - (SHW+3)) * 32);\n\tXT = tmp:16;\n}\n\ndefine pcodeop xxselOp;\n# ISA-cmt: xxsel - VSX Select\n# ISA-info: xxsel - Form \"XX4\" Page 500 Category \"VSX\"\n# binutils: vsx.d: 26c:\tf1 12 e7 bf \txxsel vs40,vs50,vs60,vs62\n:xxsel XT,XA,XB,XC is $(NOTVLE) & OP=60 & XT & XA & XB & XC & BITS_4_5=3 { xxselOp(XA,XB,XC); }\n\ndefine pcodeop xxpermdiOp;\n# :xxpermdi BITS_21_25,TX,A,AX,B,BX,DM is $(NOTVLE) & OP=60 & XOP_3_10=10 & BITS_21_25 & TX & A & AX & B & BX & DM { xxpermdiOp(A,B); } \n# ISA-cmt: xxpermdi - VSX Permute Doubleword Immediate\n# ISA-info: xxpermdi - Form \"XX3\" Page 500 Category \"VSX\"\n# binutils: power7.d: 30:\tf0 64 29 50 \txxpermdi vs3,vs4,vs5,1\n# binutils: power7.d: 34:\tf1 6c 69 57 \txxpermdi vs43,vs44,vs45,1\n# binutils: power7.d: 38:\tf0 64 2a 50 \txxpermdi vs3,vs4,vs5,2\n# binutils: power7.d: 3c:\tf1 6c 6a 57 \txxpermdi vs43,vs44,vs45,2\n# binutils: vsx.d: 23c:\tf1 12 e1 57 \txxpermdi vs40,vs50,vs60,1\n# binutils: vsx.d: 240:\tf1 12 e2 57 \txxpermdi vs40,vs50,vs60,2\n:xxpermdi XT,XA,XB,DM is $(NOTVLE) & OP=60 & OE & DM & BITS_3_7=10 & XA & XB & XT { xxpermdiOp(XA,XB,XT); }\n\ndefine pcodeop xxmrghwOp;\n# ISA-cmt: xxmrghw - VSX Merge High Word\n# ISA-info: xxmrghw - Form \"XX3\" Page 499 Category \"VSX\"\n# binutils: vsx.d: 230:\tf1 12 e0 97 \txxmrghw vs40,vs50,vs60\n:xxmrghw XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=18 & XA & XB & XT { xxmrghwOp(XA,XB,XT); }\n\ndefine pcodeop xsadddpOp;\n# ISA-cmt: xsadddp - VSX Scalar Add Double-Precision\n# ISA-info: xsadddp - Form \"XX3\" Page 342 Category \"VSX\"\n# binutils: vsx.d: 20:\tf1 12 e1 07 \txsadddp vs40,vs50,vs60\n:xsadddp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=32 & XA & XB & XT\n{\n\tsrc1:8 = XA:8;\n\tsrc2:8 = XB:8;\n\tlocal src = src1 f+ src2;\n\tXT[0,64] = src;\n}\n\ndefine pcodeop xsmaddadpOp;\n# ISA-cmt: xsmaddadp - VSX Scalar Multiply-Add Type-A Double-Precision\n# ISA-info: xsmaddadp - Form \"XX3\" Page 365 Category \"VSX\"\n# binutils: vsx.d: 54:\tf1 12 e1 0f \txsmaddadp vs40,vs50,vs60\n:xsmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=33 & XA & XB & XT { xsmaddadpOp(XA,XB,XT); }\n\ndefine pcodeop xscmpudpOp;\n# ISA-cmt: xscmpudp - VSX Scalar Compare Unordered Double-Precision\n# ISA-info: xscmpudp - Form \"XX3\" Page 349 Category \"VSX\"\n# binutils: vsx.d: 28:\tf0 92 e1 1e \txscmpudp cr1,vs50,vs60\n:xscmpudp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=35 & CRFD & BITS_21_22=0 & BIT_0=0 & XA & XB { xscmpudpOp(CRFD,XA,XB); }\n\ndefine pcodeop xssubdpOp;\n# ISA-cmt: xssubdp - VSX Scalar Subtract Double-Precision\n# ISA-info: xssubdp - Form \"XX3\" Page 393 Category \"VSX\"\n# binutils: vsx.d: a8:\tf1 12 e1 47 \txssubdp vs40,vs50,vs60\n:xssubdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=40 & XA & XB & XT { xssubdpOp(XA,XB,XT); }\n\ndefine pcodeop xsmaddmdpOp;\n# ISA-cmt: xsmaddmdp - VSX Scalar Multiply-Add Type-M Double-Precision\n# ISA-info: xsmaddmdp - Form \"XX3\" Page 365 Category \"VSX\"\n# binutils: vsx.d: 58:\tf1 12 e1 4f \txsmaddmdp vs40,vs50,vs60\n:xsmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=41 & XA & XB & XT { xsmaddmdpOp(XA,XB,XT); }\n\ndefine pcodeop xscmpodpOp;\n# ISA-cmt: xscmpodp - VSX Scalar Compare Ordered Double-Precision\n# ISA-info: xscmpodp - Form \"XX3\" Page 347 Category \"VSX\"\n# binutils: vsx.d: 24:\tf0 92 e1 5e \txscmpodp cr1,vs50,vs60\n:xscmpodp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=43 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xscmpodpOp(CRFD,XA,XB); }\n\ndefine pcodeop xsmuldpOp;\n# ISA-cmt: xsmuldp - VSX Scalar Multiply Double-Precision\n# ISA-info: xsmuldp - Form \"XX3\" Page 375 Category \"VSX\"\n# binutils: vsx.d: 6c:\tf1 12 e1 87 \txsmuldp vs40,vs50,vs60\n:xsmuldp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=48 & XA & XB & XT { xsmuldpOp(XA,XB,XT); }\n\ndefine pcodeop xsmsubadpOp;\n# ISA-cmt: xsmsubadp - VSX Scalar Multiply-Subtract Type-A Double-Precision\n# ISA-info: xsmsubadp - Form \"XX3\" Page 372 Category \"VSX\"\n# binutils: vsx.d: 64:\tf1 12 e1 8f \txsmsubadp vs40,vs50,vs60\n:xsmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=49 & XA & XB & XT { xsmsubadpOp(XA,XB,XT); }\n\ndefine pcodeop xxmrglwOp;\n# ISA-cmt: xxmrglw - VSX Merge Low Word\n# ISA-info: xxmrglw - Form \"XX3\" Page 499 Category \"VSX\"\n# binutils: vsx.d: 234:\tf1 12 e1 97 \txxmrglw vs40,vs50,vs60\n:xxmrglw XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=50 & XA & XB & XT { xxmrglwOp(XA,XB,XT); }\n\ndefine pcodeop xsdivdpOp;\n# ISA-cmt: xsdivdp - VSX Scalar Divide Double-Precision\n# ISA-info: xsdivdp - Form \"XX3\" Page 363 Category \"VSX\"\n# binutils: vsx.d: 50:\tf1 12 e1 c7 \txsdivdp vs40,vs50,vs60\n:xsdivdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=56 & XA & XB & XT { xsdivdpOp(XA,XB,XT); }\n\ndefine pcodeop xsmsubmdpOp;\n# ISA-cmt: xsmsubmdp - VSX Scalar Multiply-Subtract Type-M Double-Precision\n# ISA-info: xsmsubmdp - Form \"XX3\" Page 372 Category \"VSX\"\n# binutils: vsx.d: 68:\tf1 12 e1 cf \txsmsubmdp vs40,vs50,vs60\n:xsmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=57 & XA & XB & XT { xsmsubmdpOp(XA,XB,XT); }\n\ndefine pcodeop xstdivdpOp;\n# ISA-cmt: xstdivdp - VSX Scalar Test for software Divide Double-Precision\n# ISA-info: xstdivdp - Form \"XX3\" Page 395 Category \"VSX\"\n# binutils: vsx.d: ac:\tf0 92 e1 ee \txstdivdp cr1,vs50,vs60\n:xstdivdp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=61 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xstdivdpOp(CRFD,XA,XB); }\n\ndefine pcodeop xvaddspOp;\n# ISA-cmt: xvaddsp - VSX Vector Add Single-Precision\n# ISA-info: xvaddsp - Form \"XX3\" Page 402 Category \"VSX\"\n# binutils: vsx.d: c0:\tf1 12 e2 07 \txvaddsp vs40,vs50,vs60\n:xvaddsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=64 & XA & XB & XT { xvaddspOp(XA,XB,XT); }\n\ndefine pcodeop xvmaddaspOp;\n# ISA-cmt: xvmaddasp - VSX Vector Multiply-Add Type-A Single-Precision\n# ISA-info: xvmaddasp - Form \"XX3\" Page 437 Category \"VSX\"\n# binutils: vsx.d: 164:\tf1 12 e2 0f \txvmaddasp vs40,vs50,vs60\n:xvmaddasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=65 & XA & XB & XT { xvmaddaspOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpeqspOp;\n# ISA-cmt: xvcmpeqsp - VSX Vector Compare Equal To Single-Precision\n# ISA-info: xvcmpeqsp - Form \"XX3\" Page 405 Category \"VSX\"\n# binutils: vsx.d: cc:\tf1 12 e2 1f \txvcmpeqsp vs40,vs50,vs60\n:xvcmpeqsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=67 & BIT_10=0 & XA & XB & XT { xvcmpeqspOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpeqspDotOp;\n# ISA-cmt: xvcmpeqsp. - VSX Vector Compare Equal To Single-Precision & Record\n# ISA-info: xvcmpeqsp. - Form \"XX3\" Page 405 Category \"VSX\"\n# binutils: mytest.d: 1b8:\tf0 43 26 18 \txvcmpeqsp. vs2,vs3,vs4\n:xvcmpeqsp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=67 & BIT_10=1 & XA & XB & XT { xvcmpeqspDotOp(XA,XB,XT); }\n\ndefine pcodeop xvsubspOp;\n# ISA-cmt: xvsubsp - VSX Vector Subtract Single-Precision\n# ISA-info: xvsubsp - Form \"XX3\" Page 491 Category \"VSX\"\n# binutils: vsx.d: 208:\tf1 12 e2 47 \txvsubsp vs40,vs50,vs60\n:xvsubsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=72 & XA & XB & XT { xvsubspOp(XA,XB,XT); }\n\ndefine pcodeop xscvdpuxwsOp;\n# ISA-cmt: xscvdpuxws - VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Word format with Saturate\n# ISA-info: xscvdpuxws - Form \"XX2\" Page 359 Category \"VSX\"\n# binutils: vsx.d: 40:\tf1 00 e1 23 \txscvdpuxws vs40,vs60\n:xscvdpuxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=72 & BITS_16_20=0 & XB & XT { xscvdpuxwsOp(XB,XT); }\n\ndefine pcodeop xvmaddmspOp;\n# ISA-cmt: xvmaddmsp - VSX Vector Multiply-Add Type-M Single-Precision\n# ISA-info: xvmaddmsp - Form \"XX3\" Page 440 Category \"VSX\"\n# binutils: vsx.d: 168:\tf1 12 e2 4f \txvmaddmsp vs40,vs50,vs60\n:xvmaddmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=73 & XA & XB & XT { xvmaddmspOp(XA,XB,XT); }\n\ndefine pcodeop xsrdpiOp;\n# ISA-cmt: xsrdpi - VSX Scalar Round to Double-Precision Integer\n# ISA-info: xsrdpi - Form \"XX2\" Page 386 Category \"VSX\"\n# binutils: vsx.d: 88:\tf1 00 e1 27 \txsrdpi vs40,vs60\n:xsrdpi XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=73 & BITS_16_20=0 & XB & XT { xsrdpiOp(XB,XT); }\n\ndefine pcodeop xsrsqrtedpOp;\n# ISA-cmt: xsrsqrtedp - VSX Scalar Reciprocal Square Root Estimate Double-Precision\n# ISA-info: xsrsqrtedp - Form \"XX2\" Page 391 Category \"VSX\"\n# binutils: vsx.d: a0:\tf1 00 e1 2b \txsrsqrtedp vs40,vs60\n:xsrsqrtedp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=74 & BITS_16_20=0 & XB & XT { xsrsqrtedpOp(XB,XT); }\n\ndefine pcodeop xssqrtdpOp;\n# ISA-cmt: xssqrtdp - VSX Scalar Square Root Double-Precision\n# ISA-info: xssqrtdp - Form \"XX2\" Page 392 Category \"VSX\"\n# binutils: vsx.d: a4:\tf1 00 e1 2f \txssqrtdp vs40,vs60\n:xssqrtdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=75 & BITS_16_20=0 & XB & XT { xssqrtdpOp(XB,XT); }\n\ndefine pcodeop xvcmpgtspOp;\n# ISA-cmt: xvcmpgtsp - VSX Vector Compare Greater Than Single-Precision\n# ISA-info: xvcmpgtsp - Form \"XX3\" Page 409 Category \"VSX\"\n# binutils: vsx.d: ec:\tf1 12 e2 5f \txvcmpgtsp vs40,vs50,vs60\n:xvcmpgtsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=75 & BIT_10=0 & XA & XB & XT { xvcmpgtspOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpgtspDotOp;\n# ISA-cmt: xvcmpgtsp. - VSX Vector Compare Greater Than Single-Precision & Record\n# ISA-info: xvcmpgtsp. - Form \"XX3\" Page 409 Category \"VSX\"\n# binutils: mytest.d: 1bc:\tf0 43 26 58 \txvcmpgtsp. vs2,vs3,vs4\n:xvcmpgtsp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=75 & BIT_10=1 & XA & XB & XT { xvcmpgtspDotOp(XA,XB,XT); }\n\ndefine pcodeop xvmulspOp;\n# ISA-cmt: xvmulsp - VSX Vector Multiply Single-Precision\n# ISA-info: xvmulsp - Form \"XX3\" Page 459 Category \"VSX\"\n# binutils: vsx.d: 190:\tf1 12 e2 87 \txvmulsp vs40,vs50,vs60\n:xvmulsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=80 & XA & XB & XT { xvmulspOp(XA,XB,XT); }\n\ndefine pcodeop xvmsubaspOp;\n# ISA-cmt: xvmsubasp - VSX Vector Multiply-Subtract Type-A Single-Precision\n# ISA-info: xvmsubasp - Form \"XX3\" Page 451 Category \"VSX\"\n# binutils: vsx.d: 184:\tf1 12 e2 8f \txvmsubasp vs40,vs50,vs60\n:xvmsubasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=81 & XA & XB & XT { xvmsubaspOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpgespOp;\n# ISA-cmt: xvcmpgesp - VSX Vector Compare Greater Than or Equal To Single-Precision\n# ISA-info: xvcmpgesp - Form \"XX3\" Page 407 Category \"VSX\"\n# binutils: vsx.d: dc:\tf1 12 e2 9f \txvcmpgesp vs40,vs50,vs60\n:xvcmpgesp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=83 & BIT_10=0 & XA & XB & XT { xvcmpgespOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpgespDotOp;\n# ISA-cmt: xvcmpgesp. - VSX Vector Compare Greater Than or Equal To Single-Precision & Record\n# ISA-info: xvcmpgesp. - Form \"XX3\" Page 407 Category \"VSX\"\n# binutils: mytest.d: 1c0:\tf0 43 26 98 \txvcmpgesp. vs2,vs3,vs4\n:xvcmpgesp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=83 & BIT_10=1 & XA & XB & XT { xvcmpgespDotOp(XA,XB,XT); }\n\ndefine pcodeop xvdivspOp;\n# ISA-cmt: xvdivsp - VSX Vector Divide Single-Precision\n# ISA-info: xvdivsp - Form \"XX3\" Page 435 Category \"VSX\"\n# binutils: vsx.d: 158:\tf1 12 e2 c7 \txvdivsp vs40,vs50,vs60\n:xvdivsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=88 & XA & XB & XT { xvdivspOp(XA,XB,XT); }\n\ndefine pcodeop xscvdpsxwsOp;\n# ISA-cmt: xscvdpsxws - VSX Scalar truncate Double-Precision to integer and Convert to Signed Fixed-Point Word format with Saturate\n# ISA-info: xscvdpsxws - Form \"XX2\" Page 355 Category \"VSX\"\n# binutils: vsx.d: 38:\tf1 00 e1 63 \txscvdpsxws vs40,vs60\n:xscvdpsxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=88 & BITS_16_20=0 & XB & XT { xscvdpsxwsOp(XB,XT); }\n\ndefine pcodeop xvmsubmspOp;\n# ISA-cmt: xvmsubmsp - VSX Vector Multiply-Subtract Type-M Single-Precision\n# ISA-info: xvmsubmsp - Form \"XX3\" Page 454 Category \"VSX\"\n# binutils: vsx.d: 188:\tf1 12 e2 cf \txvmsubmsp vs40,vs50,vs60\n:xvmsubmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=89 & XA & XB & XT { xvmsubmspOp(XA,XB,XT); }\n\ndefine pcodeop xsrdpizOp;\n# ISA-cmt: xsrdpiz - VSX Scalar Round to Double-Precision Integer toward Zero\n# ISA-info: xsrdpiz - Form \"XX2\" Page 389 Category \"VSX\"\n# binutils: vsx.d: 98:\tf1 00 e1 67 \txsrdpiz vs40,vs60\n:xsrdpiz XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=89 & BITS_16_20=0 & XB & XT { xsrdpizOp(XB,XT); }\n\ndefine pcodeop xsredpOp;\n# ISA-cmt: xsredp - VSX Scalar Reciprocal Estimate Double-Precision\n# ISA-info: xsredp - Form \"XX2\" Page 390 Category \"VSX\"\n# binutils: vsx.d: 9c:\tf1 00 e1 6b \txsredp vs40,vs60\n:xsredp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=90 & BITS_16_20=0 & XB & XT { xsredpOp(XB,XT); }\n\ndefine pcodeop xvtdivspOp;\n# ISA-cmt: xvtdivsp - VSX Vector Test for software Divide Single-Precision\n# ISA-info: xvtdivsp - Form \"XX3\" Page 494 Category \"VSX\"\n# binutils: vsx.d: 210:\tf0 92 e2 ee \txvtdivsp cr1,vs50,vs60\n:xvtdivsp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=93 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xvtdivspOp(CRFD,XA,XB); }\n\ndefine pcodeop xvadddpOp;\n# ISA-cmt: xvadddp - VSX Vector Add Double-Precision\n# ISA-info: xvadddp - Form \"XX3\" Page 398 Category \"VSX\"\n# binutils: vsx.d: bc:\tf1 12 e3 07 \txvadddp vs40,vs50,vs60\n:xvadddp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=96 & XA & XB & XT { xvadddpOp(XA,XB,XT); }\n\ndefine pcodeop xvmaddadpOp;\n# ISA-cmt: xvmaddadp - VSX Vector Multiply-Add Type-A Double-Precision\n# ISA-info: xvmaddadp - Form \"XX3\" Page 437 Category \"VSX\"\n# binutils: vsx.d: 15c:\tf1 12 e3 0f \txvmaddadp vs40,vs50,vs60\n:xvmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=97 & XA & XB & XT { xvmaddadpOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpeqdpOp;\n# ISA-cmt: xvcmpeqdp - VSX Vector Compare Equal To Double-Precision\n# ISA-info: xvcmpeqdp - Form \"XX3\" Page 404 Category \"VSX\"\n# binutils: vsx.d: c4:\tf1 12 e3 1f \txvcmpeqdp vs40,vs50,vs60\n:xvcmpeqdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=99 & BIT_10=0 & XA & XB & XT { xvcmpeqdpOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpeqdpDotOp;\n# ISA-cmt: xvcmpeqdp. - VSX Vector Compare Equal To Double-Precision & Record\n# ISA-info: xvcmpeqdp. - Form \"XX3\" Page 404 Category \"VSX\"\n# binutils: mytest.d: 1c4:\tf0 43 27 18 \txvcmpeqdp. vs2,vs3,vs4\n:xvcmpeqdp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=99 & BIT_10=1 & XA & XB & XT { xvcmpeqdpDotOp(XA,XB,XT); }\n\ndefine pcodeop xvsubdpOp;\n# ISA-cmt: xvsubdp - VSX Vector Subtract Double-Precision\n# ISA-info: xvsubdp - Form \"XX3\" Page 489 Category \"VSX\"\n# binutils: vsx.d: 204:\tf1 12 e3 47 \txvsubdp vs40,vs50,vs60\n:xvsubdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=104 & XA & XB & XT { xvsubdpOp(XA,XB,XT); }\n\ndefine pcodeop xvmaddmdpOp;\n# ISA-cmt: xvmaddmdp - VSX Vector Multiply-Add Type-M Double-Precision\n# ISA-info: xvmaddmdp - Form \"XX3\" Page 440 Category \"VSX\"\n# binutils: vsx.d: 160:\tf1 12 e3 4f \txvmaddmdp vs40,vs50,vs60\n:xvmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=105 & XA & XB & XT { xvmaddmdpOp(XA,XB,XT); }\n\ndefine pcodeop xsrdpipOp;\n# ISA-cmt: xsrdpip - VSX Scalar Round to Double-Precision Integer toward +Infinity\n# ISA-info: xsrdpip - Form \"XX2\" Page 388 Category \"VSX\"\n# binutils: vsx.d: 94:\tf1 00 e1 a7 \txsrdpip vs40,vs60\n:xsrdpip XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=105 & BITS_16_20=0 & XB & XT { xsrdpipOp(XB,XT); }\n\ndefine pcodeop xstsqrtdpOp;\n# ISA-cmt: xstsqrtdp - VSX Scalar Test for software Square Root Double-Precision\n# ISA-info: xstsqrtdp - Form \"XX2\" Page 396 Category \"VSX\"\n# binutils: vsx.d: b0:\tf0 80 e1 aa \txstsqrtdp cr1,vs60\n:xstsqrtdp CRFD,XB is $(NOTVLE) & OP=60 & XOP_2_10=106 & CRFD & BIT_0=0 & BITS_21_22=0 & BITS_16_20=0 & XB { xstsqrtdpOp(CRFD,XB); }\n\ndefine pcodeop xsrdpicOp;\n# ISA-cmt: xsrdpic - VSX Scalar Round to Double-Precision Integer using Current rounding mode\n# ISA-info: xsrdpic - Form \"XX2\" Page 387 Category \"VSX\"\n# binutils: vsx.d: 8c:\tf1 00 e1 af \txsrdpic vs40,vs60\n:xsrdpic XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=107 & BITS_16_20=0 & XB & XT { xsrdpicOp(XB,XT); }\n\ndefine pcodeop xvcmpgtdpOp;\n# ISA-cmt: xvcmpgtdp - VSX Vector Compare Greater Than Double-Precision\n# ISA-info: xvcmpgtdp - Form \"XX3\" Page 408 Category \"VSX\"\n# binutils: vsx.d: e4:\tf1 12 e3 5f \txvcmpgtdp vs40,vs50,vs60\n:xvcmpgtdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=107 & BIT_10=0 & XA & XB & XT { xvcmpgtdpOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpgtdpDotOp;\n# ISA-cmt: xvcmpgtdp. - VSX Vector Compare Greater Than Double-Precision & Record\n# ISA-info: xvcmpgtdp. - Form \"XX3\" Page 408 Category \"VSX\"\n# binutils: mytest.d: 1c8:\tf0 43 27 58 \txvcmpgtdp. vs2,vs3,vs4\n:xvcmpgtdp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=107 & BIT_10=1 & XA & XB & XT { xvcmpgtdpDotOp(XA,XB,XT); }\n\ndefine pcodeop xvmuldpOp;\n# ISA-cmt: xvmuldp - VSX Vector Multiply Double-Precision\n# ISA-info: xvmuldp - Form \"XX3\" Page 457 Category \"VSX\"\n# binutils: vsx.d: 18c:\tf1 12 e3 87 \txvmuldp vs40,vs50,vs60\n:xvmuldp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=112 & XA & XB & XT { xvmuldpOp(XA,XB,XT); }\n\ndefine pcodeop xvmsubadpOp;\n# ISA-cmt: xvmsubadp - VSX Vector Multiply-Subtract Type-A Double-Precision\n# ISA-info: xvmsubadp - Form \"XX3\" Page 451 Category \"VSX\"\n# binutils: vsx.d: 17c:\tf1 12 e3 8f \txvmsubadp vs40,vs50,vs60\n:xvmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=113 & XA & XB & XT { xvmsubadpOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpgedpOp;\n# ISA-cmt: xvcmpgedp - VSX Vector Compare Greater Than or Equal To Double-Precision\n# ISA-info: xvcmpgedp - Form \"XX3\" Page 406 Category \"VSX\"\n# binutils: vsx.d: d4:\tf1 12 e3 9f \txvcmpgedp vs40,vs50,vs60\n:xvcmpgedp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=115 & BIT_10=0 & XA & XB & XT { xvcmpgedpOp(XA,XB,XT); }\n\ndefine pcodeop xvcmpgedpDotOp;\n# ISA-cmt: xvcmpgedp. - VSX Vector Compare Greater Than or Equal To Double-Precision & Record\n# ISA-info: xvcmpgedp. - Form \"XX3\" Page 406 Category \"VSX\"\n# binutils: mytest.d: 1cc:\tf0 43 27 98 \txvcmpgedp. vs2,vs3,vs4\n:xvcmpgedp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=115 & BIT_10=1 & XA & XB & XT { xvcmpgedpDotOp(XA,XB,XT); }\n\ndefine pcodeop xvdivdpOp;\n# ISA-cmt: xvdivdp - VSX Vector Divide Double-Precision\n# ISA-info: xvdivdp - Form \"XX3\" Page 433 Category \"VSX\"\n# binutils: vsx.d: 154:\tf1 12 e3 c7 \txvdivdp vs40,vs50,vs60\n:xvdivdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=120 & XA & XB & XT { xvdivdpOp(XA,XB,XT); }\n\ndefine pcodeop xvmsubmdpOp;\n# ISA-cmt: xvmsubmdp - VSX Vector Multiply-Subtract Type-M Double-Precision\n# ISA-info: xvmsubmdp - Form \"XX3\" Page 454 Category \"VSX\"\n# binutils: vsx.d: 180:\tf1 12 e3 cf \txvmsubmdp vs40,vs50,vs60\n:xvmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=121 & XA & XB & XT { xvmsubmdpOp(XA,XB,XT); }\n\ndefine pcodeop xsrdpimOp;\n# ISA-cmt: xsrdpim - VSX Scalar Round to Double-Precision Integer toward -Infinity\n# ISA-info: xsrdpim - Form \"XX2\" Page 388 Category \"VSX\"\n# binutils: vsx.d: 90:\tf1 00 e1 e7 \txsrdpim vs40,vs60\n:xsrdpim XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=121 & BITS_16_20=0 & XB & XT { xsrdpimOp(XB,XT); }\n\ndefine pcodeop xvtdivdpOp;\n# ISA-cmt: xvtdivdp - VSX Vector Test for software Divide Double-Precision\n# ISA-info: xvtdivdp - Form \"XX3\" Page 493 Category \"VSX\"\n# binutils: vsx.d: 20c:\tf0 92 e3 ee \txvtdivdp cr1,vs50,vs60\n:xvtdivdp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=125 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xvtdivdpOp(CRFD,XA,XB); }\n\n# ISA-cmt: xxland - VSX Logical AND\n# ISA-info: xxland - Form \"XX3\" Page 496 Category \"VSX\"\n# binutils: vsx.d: 21c:\tf1 12 e4 17 \txxland vs40,vs50,vs60\n:xxland XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=130 & XA & XB & XT {\n\tXT = XA & XB;\n}\n\ndefine pcodeop xvcvspuxwsOp;\n# ISA-cmt: xvcvspuxws - VSX Vector truncate Single-Precision to integer and Convert to Unsigned Fixed-Point Word Saturate\n# ISA-info: xvcvspuxws - Form \"XX2\" Page 427 Category \"VSX\"\n# binutils: vsx.d: 130:\tf1 00 e2 23 \txvcvspuxws vs40,vs60\n:xvcvspuxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=136 & BI_BITS=0 & XB & XT { xvcvspuxwsOp(XB,XT); }\n\ndefine pcodeop xvrspiOp;\n# ISA-cmt: xvrspi - VSX Vector Round to Single-Precision Integer\n# ISA-info: xvrspi - Form \"XX2\" Page 482 Category \"VSX\"\n# binutils: vsx.d: 1e0:\tf1 00 e2 27 \txvrspi vs40,vs60\n:xvrspi XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=137 & BI_BITS=0 & XB & XT { xvrspiOp(XB,XT); }\n\n# ISA-cmt: xxlandc - VSX Logical AND with Complement\n# ISA-info: xxlandc - Form \"XX3\" Page 496 Category \"VSX\"\n# binutils: vsx.d: 220:\tf1 12 e4 57 \txxlandc vs40,vs50,vs60\n:xxlandc XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=138 & XA & XB & XT {\n\tXT = XA & (~XB);\n}\n\ndefine pcodeop xvrsqrtespOp;\n# ISA-cmt: xvrsqrtesp - VSX Vector Reciprocal Square Root Estimate Single-Precision\n# ISA-info: xvrsqrtesp - Form \"XX2\" Page 486 Category \"VSX\"\n# binutils: vsx.d: 1f8:\tf1 00 e2 2b \txvrsqrtesp vs40,vs60\n:xvrsqrtesp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=138 & BI_BITS=0 & XB & XT { xvrsqrtespOp(XB,XT); }\n\ndefine pcodeop xvsqrtspOp;\n# ISA-cmt: xvsqrtsp - VSX Vector Square Root Single-Precision\n# ISA-info: xvsqrtsp - Form \"XX2\" Page 488 Category \"VSX\"\n# binutils: vsx.d: 200:\tf1 00 e2 2f \txvsqrtsp vs40,vs60\n:xvsqrtsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=139 & BI_BITS=0 & XB & XT { xvsqrtspOp(XB,XT); }\n\n# ISA-cmt: xxlor - VSX Logical OR\n# ISA-info: xxlor - Form \"XX3\" Page 497 Category \"VSX\"\n# binutils: vsx.d: 228:\tf1 12 e4 97 \txxlor vs40,vs50,vs60\n:xxlor XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=146 & XA & XB & XT {\n\tXT = XA | XB;\n}\n\ndefine pcodeop xvcvspsxwsOp;\n# ISA-cmt: xvcvspsxws - VSX Vector truncate Single-Precision to integer and Convert to Signed Fixed-Point Word format with Saturate\n# ISA-info: xvcvspsxws - Form \"XX2\" Page 423 Category \"VSX\"\n# binutils: vsx.d: 128:\tf1 00 e2 63 \txvcvspsxws vs40,vs60\n:xvcvspsxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=152 & BI_BITS=0 & XB & XT { xvcvspsxwsOp(XB,XT); }\n\ndefine pcodeop xvrspizOp;\n# ISA-cmt: xvrspiz - VSX Vector Round to Single-Precision Integer toward Zero\n# ISA-info: xvrspiz - Form \"XX2\" Page 484 Category \"VSX\"\n# binutils: vsx.d: 1f0:\tf1 00 e2 67 \txvrspiz vs40,vs60\n:xvrspiz XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=153 & BI_BITS=0 & XB & XT { xvrspizOp(XB,XT); }\n\n# ISA-cmt: xxlxor - VSX Logical XOR\n# ISA-info: xxlxor - Form \"XX3\" Page 498 Category \"VSX\"\n# binutils: vsx.d: 22c:\tf1 12 e4 d7 \txxlxor vs40,vs50,vs60\n:xxlxor XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=154 & XA & XB & XT {\n\tXT = XA ^ XB;\n}\n\ndefine pcodeop xvrespOp;\n# ISA-cmt: xvresp - VSX Vector Reciprocal Estimate Single-Precision\n# ISA-info: xvresp - Form \"XX2\" Page 481 Category \"VSX\"\n# binutils: vsx.d: 1dc:\tf1 00 e2 6b \txvresp vs40,vs60\n:xvresp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=154 & BI_BITS=0 & XB & XT { xvrespOp(XB,XT); }\n\ndefine pcodeop xsmaxdpOp;\n# ISA-cmt: xsmaxdp - VSX Scalar Maximum Double-Precision\n# ISA-info: xsmaxdp - Form \"XX3\" Page 368 Category \"VSX\"\n# binutils: vsx.d: 5c:\tf1 12 e5 07 \txsmaxdp vs40,vs50,vs60\n:xsmaxdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=160 & XA & XB & XT { xsmaxdpOp(XA,XB,XT); }\n\ndefine pcodeop xsnmaddadpOp;\n# ISA-cmt: xsnmaddadp - VSX Scalar Negative Multiply-Add Type-A Double-Precision\n# ISA-info: xsnmaddadp - Form \"XX3\" Page 378 Category \"VSX\"\n# binutils: vsx.d: 78:\tf1 12 e5 0f \txsnmaddadp vs40,vs50,vs60\n:xsnmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=161 & XA & XB & XT { xsnmaddadpOp(XA,XB); }\n\ndefine pcodeop xxlnorOp;\n# ISA-cmt: xxlnor - VSX Logical NOR\n# ISA-info: xxlnor - Form \"XX3\" Page 497 Category \"VSX\"\n# binutils: vsx.d: 224:\tf1 12 e5 17 \txxlnor vs40,vs50,vs60\n:xxlnor XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=162 & XA & XB & XT {\n\tXT = ~(XA | XB);\n}\n\ndefine pcodeop xxspltwOp;\n# ISA-cmt: xxspltw - VSX Splat Word\n# ISA-info: xxspltw - Form \"XX2\" Page 501 Category \"VSX\"\n# binutils: vsx.d: 274:\tf1 02 e2 93 \txxspltw vs40,vs60,2\n:xxspltw XT,XB,UIM is $(NOTVLE) & OP=60 & XOP_2_10=164 & BITS_18_20=0 & UIM & XB & XT { xxspltwOp(XB,XT); }\n\ndefine pcodeop xsmindpOp;\n# ISA-cmt: xsmindp - VSX Scalar Minimum Double-Precision\n# ISA-info: xsmindp - Form \"XX3\" Page 370 Category \"VSX\"\n# binutils: vsx.d: 60:\tf1 12 e5 47 \txsmindp vs40,vs50,vs60\n:xsmindp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=168 & XA & XB & XT { xsmindpOp(XA,XB,XT); }\n\ndefine pcodeop xvcvuxwspOp;\n# ISA-cmt: xvcvuxwsp - VSX Vector Convert and round Unsigned Fixed-Point Word to Single-Precision format\n# ISA-info: xvcvuxwsp - Form \"XX2\" Page 432 Category \"VSX\"\n# binutils: vsx.d: 150:\tf1 00 e2 a3 \txvcvuxwsp vs40,vs60\n:xvcvuxwsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=168 & BI_BITS=0 & XB & XT { xvcvuxwspOp(XB,XT); }\n\ndefine pcodeop xsnmaddmdpOp;\n# ISA-cmt: xsnmaddmdp - VSX Scalar Negative Multiply-Add Type-M Double-Precision\n# ISA-info: xsnmaddmdp - Form \"XX3\" Page 378 Category \"VSX\"\n# binutils: vsx.d: 7c:\tf1 12 e5 4f \txsnmaddmdp vs40,vs50,vs60\n:xsnmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=169 & XA & XB & XT { xsnmaddmdpOp(XA,XB,XT); }\n\ndefine pcodeop xvrspipOp;\n# ISA-cmt: xvrspip - VSX Vector Round to Single-Precision Integer toward +Infinity\n# ISA-info: xvrspip - Form \"XX2\" Page 483 Category \"VSX\"\n# binutils: vsx.d: 1ec:\tf1 00 e2 a7 \txvrspip vs40,vs60\n:xvrspip XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=169 & BI_BITS=0 & XB & XT { xvrspipOp(XB,XT); }\n\ndefine pcodeop xvtsqrtspOp;\n# ISA-cmt: xvtsqrtsp - VSX Vector Test for software Square Root Single-Precision\n# ISA-info: xvtsqrtsp - Form \"XX2\" Page 495 Category \"VSX\"\n# binutils: vsx.d: 218:\tf0 80 e2 aa \txvtsqrtsp cr1,vs60\n:xvtsqrtsp CRFD,XB is $(NOTVLE) & OP=60 & XOP_2_10=170 & CRFD & BITS_21_22=0 & BITS_16_20=0 & BIT_0=0 & XB { xvtsqrtspOp(CRFD,XB); }\n\ndefine pcodeop xvrspicOp;\n# ISA-cmt: xvrspic - VSX Vector Round to Single-Precision Integer using Current rounding mode\n# ISA-info: xvrspic - Form \"XX2\" Page 482 Category \"VSX\"\n# binutils: vsx.d: 1e4:\tf1 00 e2 af \txvrspic vs40,vs60\n:xvrspic XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=171 & BITS_16_20=0 & XB & XT { xvrspicOp(XB,XT); }\n\ndefine pcodeop xscpsgndpOp;\n# ISA-cmt: xscpsgndp - VSX Scalar Copy Sign Double-Precision\n# ISA-info: xscpsgndp - Form \"XX3\" Page 351 Category \"VSX\"\n# binutils: vsx.d: 2c:\tf1 12 e5 87 \txscpsgndp vs40,vs50,vs60\n:xscpsgndp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=176 & XA & XB & XT { xscpsgndpOp(XA,XB,XT); }\n\ndefine pcodeop xsnmsubadpOp;\n# ISA-cmt: xsnmsubadp - VSX Scalar Negative Multiply-Subtract Type-A Double-Precision\n# ISA-info: xsnmsubadp - Form \"XX3\" Page 383 Category \"VSX\"\n# binutils: vsx.d: 80:\tf1 12 e5 8f \txsnmsubadp vs40,vs50,vs60\n:xsnmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=177 & XA & XB & XT { xsnmsubadpOp(XA,XB,XT); }\n\ndefine pcodeop xvcvsxwspOp;\n# ISA-cmt: xvcvsxwsp - VSX Vector Convert and round Signed Fixed-Point Word to Single-Precision format\n# ISA-info: xvcvsxwsp - Form \"XX2\" Page 430 Category \"VSX\"\n# binutils: vsx.d: 140:\tf1 00 e2 e3 \txvcvsxwsp vs40,vs60\n:xvcvsxwsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=184 & BITS_16_20=0 & XB & XT { xvcvsxwspOp(XB,XT); }\n\ndefine pcodeop xsnmsubmdpOp;\n# ISA-cmt: xsnmsubmdp - VSX Scalar Negative Multiply-Subtract Type-M Double-Precision\n# ISA-info: xsnmsubmdp - Form \"XX3\" Page 383 Category \"VSX\"\n# binutils: vsx.d: 84:\tf1 12 e5 cf \txsnmsubmdp vs40,vs50,vs60\n:xsnmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=185 & XA & XB & XT { xsnmsubmdpOp(XA,XB,XT); }\n\ndefine pcodeop xvrspimOp;\n# ISA-cmt: xvrspim - VSX Vector Round to Single-Precision Integer toward -Infinity\n# ISA-info: xvrspim - Form \"XX2\" Page 483 Category \"VSX\"\n# binutils: vsx.d: 1e8:\tf1 00 e2 e7 \txvrspim vs40,vs60\n:xvrspim XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=185 & BITS_16_20=0 & XB & XT { xvrspimOp(XB,XT); }\n\ndefine pcodeop xvmaxspOp;\n# ISA-cmt: xvmaxsp - VSX Vector Maximum Single-Precision\n# ISA-info: xvmaxsp - Form \"XX3\" Page 445 Category \"VSX\"\n# binutils: vsx.d: 170:\tf1 12 e6 07 \txvmaxsp vs40,vs50,vs60\n:xvmaxsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=192 & XA & XB & XT { xvmaxspOp(XA,XB,XT); }\n\ndefine pcodeop xvnmaddaspOp;\n# ISA-cmt: xvnmaddasp - VSX Vector Negative Multiply-Add Type-A Single-Precision\n# ISA-info: xvnmaddasp - Form \"XX3\" Page 463 Category \"VSX\"\n# binutils: vsx.d: 1ac:\tf1 12 e6 0f \txvnmaddasp vs40,vs50,vs60\n:xvnmaddasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=193 & XA & XB & XT { xvnmaddaspOp(XA,XB,XT); }\n\ndefine pcodeop xvminspOp;\n# ISA-cmt: xvminsp - VSX Vector Minimum Single-Precision\n# ISA-info: xvminsp - Form \"XX3\" Page 449 Category \"VSX\"\n# binutils: vsx.d: 178:\tf1 12 e6 47 \txvminsp vs40,vs50,vs60\n:xvminsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=200 & XA & XB & XT { xvminspOp(XA,XB,XT); }\n\ndefine pcodeop xvcvdpuxwsOp;\n# ISA-cmt: xvcvdpuxws - VSX Vector truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Word format with Saturate\n# ISA-info: xvcvdpuxws - Form \"XX2\" Page 418 Category \"VSX\"\n# binutils: vsx.d: 11c:\tf1 00 e3 23 \txvcvdpuxws vs40,vs60\n:xvcvdpuxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=200 & BITS_16_20=0 & XB & XT { xvcvdpuxwsOp(XB,XT); }\n\ndefine pcodeop xvnmaddmspOp;\n# ISA-cmt: xvnmaddmsp - VSX Vector Negative Multiply-Add Type-M Single-Precision\n# ISA-info: xvnmaddmsp - Form \"XX3\" Page 468 Category \"VSX\"\n# binutils: vsx.d: 1b0:\tf1 12 e6 4f \txvnmaddmsp vs40,vs50,vs60\n:xvnmaddmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=201 & XA & XB & XT { xvnmaddmspOp(XA,XB,XT); }\n\ndefine pcodeop xvrdpiOp;\n# ISA-cmt: xvrdpi - VSX Vector Round to Double-Precision Integer\n# ISA-info: xvrdpi - Form \"XX2\" Page 477 Category \"VSX\"\n# binutils: vsx.d: 1c4:\tf1 00 e3 27 \txvrdpi vs40,vs60\n:xvrdpi XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=201 & BITS_16_20=0 & XB & XT { xvrdpiOp(XB,XT); }\n\ndefine pcodeop xvrsqrtedpOp;\n# ISA-cmt: xvrsqrtedp - VSX Vector Reciprocal Square Root Estimate Double-Precision\n# ISA-info: xvrsqrtedp - Form \"XX2\" Page 485 Category \"VSX\"\n# binutils: vsx.d: 1f4:\tf1 00 e3 2b \txvrsqrtedp vs40,vs60\n:xvrsqrtedp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=202 & BITS_16_20=0 & XB & XT { xvrsqrtedpOp(XB,XT); }\n\ndefine pcodeop xvsqrtdpOp;\n# ISA-cmt: xvsqrtdp - VSX Vector Square Root Double-Precision\n# ISA-info: xvsqrtdp - Form \"XX2\" Page 487 Category \"VSX\"\n# binutils: vsx.d: 1fc:\tf1 00 e3 2f \txvsqrtdp vs40,vs60\n:xvsqrtdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=203 & BITS_16_20=0 & XB & XT { xvsqrtdpOp(XB,XT); }\n\ndefine pcodeop xvcpsgnspOp;\n# ISA-cmt: xvcpsgnsp - VSX Vector Copy Sign Single-Precision\n# ISA-info: xvcpsgnsp - Form \"XX3\" Page 410 Category \"VSX\"\n# binutils: vsx.d: 100:\tf1 12 e6 87 \txvcpsgnsp vs40,vs50,vs60\n:xvcpsgnsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=208 & XA & XB & XT { xvcpsgnspOp(XA,XB,XT); }\n\ndefine pcodeop xvnmsubaspOp;\n# ISA-cmt: xvnmsubasp - VSX Vector Negative Multiply-Subtract Type-A Single-Precision\n# ISA-info: xvnmsubasp - Form \"XX3\" Page 471 Category \"VSX\"\n# binutils: vsx.d: 1bc:\tf1 12 e6 8f \txvnmsubasp vs40,vs50,vs60\n:xvnmsubasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=209 & XA & XB & XT { xvnmsubaspOp(XA,XB,XT); }\n\ndefine pcodeop xvcvdpsxwsOp;\n# ISA-cmt: xvcvdpsxws - VSX Vector truncate Double-Precision to integer and Convert to Signed Fixed-Point Word Saturate\n# ISA-info: xvcvdpsxws - Form \"XX2\" Page 414 Category \"VSX\"\n# binutils: vsx.d: 114:\tf1 00 e3 63 \txvcvdpsxws vs40,vs60\n:xvcvdpsxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=216 & BITS_16_20=0 & XB & XT { xvcvdpsxwsOp(XB,XT); }\n\ndefine pcodeop xvnmsubmspOp;\n# ISA-cmt: xvnmsubmsp - VSX Vector Negative Multiply-Subtract Type-M Single-Precision\n# ISA-info: xvnmsubmsp - Form \"XX3\" Page 474 Category \"VSX\"\n# binutils: vsx.d: 1c0:\tf1 12 e6 cf \txvnmsubmsp vs40,vs50,vs60\n:xvnmsubmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=217 & XA & XB & XT { xvnmsubmspOp(XA,XB,XT); }\n\ndefine pcodeop xvrdpizOp;\n# ISA-cmt: xvrdpiz - VSX Vector Round to Double-Precision Integer toward Zero\n# ISA-info: xvrdpiz - Form \"XX2\" Page 479 Category \"VSX\"\n# binutils: vsx.d: 1d4:\tf1 00 e3 67 \txvrdpiz vs40,vs60\n:xvrdpiz XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=217 & BITS_16_20=0 & XB & XT { xvrdpizOp(XB,XT); }\n\ndefine pcodeop xvredpOp;\n# ISA-cmt: xvredp - VSX Vector Reciprocal Estimate Double-Precision\n# ISA-info: xvredp - Form \"XX2\" Page 480 Category \"VSX\"\n# binutils: vsx.d: 1d8:\tf1 00 e3 6b \txvredp vs40,vs60\n:xvredp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=218 & BITS_16_20=0 & XB & XT { xvredpOp(XB,XT); }\n\ndefine pcodeop xvmaxdpOp;\n# ISA-cmt: xvmaxdp - VSX Vector Maximum Double-Precision\n# ISA-info: xvmaxdp - Form \"XX3\" Page 443 Category \"VSX\"\n# binutils: vsx.d: 16c:\tf1 12 e7 07 \txvmaxdp vs40,vs50,vs60\n:xvmaxdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=224 & XA & XB & XT { xvmaxdpOp(XA,XB,XT); }\n\ndefine pcodeop xvnmaddadpOp;\n# ISA-cmt: xvnmaddadp - VSX Vector Negative Multiply-Add Type-A Double-Precision\n# ISA-info: xvnmaddadp - Form \"XX3\" Page 463 Category \"VSX\"\n# binutils: vsx.d: 1a4:\tf1 12 e7 0f \txvnmaddadp vs40,vs50,vs60\n:xvnmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=225 & XA & XB & XT { xvnmaddadpOp(XA,XB,XT); }\n\ndefine pcodeop xvmindpOp;\n# ISA-cmt: xvmindp - VSX Vector Minimum Double-Precision\n# ISA-info: xvmindp - Form \"XX3\" Page 447 Category \"VSX\"\n# binutils: vsx.d: 174:\tf1 12 e7 47 \txvmindp vs40,vs50,vs60\n:xvmindp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=232 & XA & XB & XT { xvmindpOp(XA,XB,XT); }\n\ndefine pcodeop xvnmaddmdpOp;\n# ISA-cmt: xvnmaddmdp - VSX Vector Negative Multiply-Add Type-M Double-Precision\n# ISA-info: xvnmaddmdp - Form \"XX3\" Page 468 Category \"VSX\"\n# binutils: vsx.d: 1a8:\tf1 12 e7 4f \txvnmaddmdp vs40,vs50,vs60\n:xvnmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=233 & XA & XB & XT { xvnmaddmdpOp(XA,XB,XT); }\n\ndefine pcodeop xvcvuxwdpOp;\n# ISA-cmt: xvcvuxwdp - VSX Vector Convert Unsigned Fixed-Point Word to Double-Precision format\n# ISA-info: xvcvuxwdp - Form \"XX2\" Page 432 Category \"VSX\"\n# binutils: vsx.d: 14c:\tf1 00 e3 a3 \txvcvuxwdp vs40,vs60\n:xvcvuxwdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=232 & BITS_16_20=0 & XB & XT { xvcvuxwdpOp(XB,XT); }\n\ndefine pcodeop xvrdpipOp;\n# ISA-cmt: xvrdpip - VSX Vector Round to Double-Precision Integer toward +Infinity\n# ISA-info: xvrdpip - Form \"XX2\" Page 479 Category \"VSX\"\n# binutils: vsx.d: 1d0:\tf1 00 e3 a7 \txvrdpip vs40,vs60\n:xvrdpip XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=233 & BITS_16_20=0 & XB & XT { xvrdpipOp(XB,XT); }\n\ndefine pcodeop xvtsqrtdpOp;\n# ISA-cmt: xvtsqrtdp - VSX Vector Test for software Square Root Double-Precision\n# ISA-info: xvtsqrtdp - Form \"XX2\" Page 495 Category \"VSX\"\n# binutils: vsx.d: 214:\tf0 80 e3 aa \txvtsqrtdp cr1,vs60\n:xvtsqrtdp CRFD,XB is $(NOTVLE) & OP=60 & XOP_2_10=234 & CRFD & BITS_16_20=0 & BIT_0=0 & BITS_21_22=0 & XB { xvtsqrtdpOp(CRFD,XB); }\n\ndefine pcodeop xvrdpicOp;\n# ISA-cmt: xvrdpic - VSX Vector Round to Double-Precision Integer using Current rounding mode\n# ISA-info: xvrdpic - Form \"XX2\" Page 478 Category \"VSX\"\n# binutils: vsx.d: 1c8:\tf1 00 e3 af \txvrdpic vs40,vs60\n:xvrdpic XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=235 & BITS_16_20=0 & XB & XT { xvrdpicOp(XB,XT); }\n\ndefine pcodeop xvcpsgndpOp;\n# ISA-cmt: xvcpsgndp - VSX Vector Copy Sign Double-Precision\n# ISA-info: xvcpsgndp - Form \"XX3\" Page 410 Category \"VSX\"\n# binutils: power7.d: 50:\tf0 64 2f 80 \txvcpsgndp vs3,vs4,vs5\n# binutils: power7.d: 54:\tf1 6c 6f 87 \txvcpsgndp vs43,vs44,vs45\n# binutils: vsx.d: f4:\tf1 12 e7 87 \txvcpsgndp vs40,vs50,vs60\n:xvcpsgndp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=240 & XA & XB & XT { xvcpsgndpOp(XA,XB,XT); }\n\ndefine pcodeop xvnmsubadpOp;\n# ISA-cmt: xvnmsubadp - VSX Vector Negative Multiply-Subtract Type-A Double-Precision\n# ISA-info: xvnmsubadp - Form \"XX3\" Page 471 Category \"VSX\"\n# binutils: vsx.d: 1b4:\tf1 12 e7 8f \txvnmsubadp vs40,vs50,vs60\n:xvnmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=241 & XA & XB & XT { xvnmsubadpOp(XA,XB,XT); }\n\ndefine pcodeop xvcvsxwdpOp;\n# ISA-cmt: xvcvsxwdp - VSX Vector Convert Signed Fixed-Point Word to Double-Precision format\n# ISA-info: xvcvsxwdp - Form \"XX2\" Page 430 Category \"VSX\"\n# binutils: vsx.d: 13c:\tf1 00 e3 e3 \txvcvsxwdp vs40,vs60\n:xvcvsxwdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=248 & BI_BITS=0 & XB & XT { xvcvsxwdpOp(XB,XT); }\n\ndefine pcodeop xvnmsubmdpOp;\n# ISA-cmt: xvnmsubmdp - VSX Vector Negative Multiply-Subtract Type-M Double-Precision\n# ISA-info: xvnmsubmdp - Form \"XX3\" Page 474 Category \"VSX\"\n# binutils: vsx.d: 1b8:\tf1 12 e7 cf \txvnmsubmdp vs40,vs50,vs60\n:xvnmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=249 & XA & XB & XT { xvnmsubmdpOp(XA,XB,XT); }\n\ndefine pcodeop xvrdpimOp;\n# ISA-cmt: xvrdpim - VSX Vector Round to Double-Precision Integer toward -Infinity\n# ISA-info: xvrdpim - Form \"XX2\" Page 478 Category \"VSX\"\n# binutils: vsx.d: 1cc:\tf1 00 e3 e7 \txvrdpim vs40,vs60\n:xvrdpim XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=249 & BITS_16_20=0 & XB & XT { xvrdpimOp(XB,XT); }\n\ndefine pcodeop xscvdpspOp;\n# ISA-cmt: xscvdpsp - VSX Scalar Convert Double-Precision to Single-Precision\n# ISA-info: xscvdpsp - Form \"XX2\" Page 352 Category \"VSX\"\n# binutils: vsx.d: 30:\tf1 00 e4 27 \txscvdpsp vs40,vs60\n:xscvdpsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=265 & BITS_16_20=0 & XB & XT { xscvdpspOp(XB,XT); }\n\ndefine pcodeop xscvdpuxdsOp;\n# ISA-cmt: xscvdpuxds - VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Doubleword format with Saturate\n# ISA-info: xscvdpuxds - Form \"XX2\" Page 357 Category \"VSX\"\n# binutils: vsx.d: 3c:\tf1 00 e5 23 \txscvdpuxds vs40,vs60\n:xscvdpuxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=328 & BITS_16_20=0 & XB & XT { xscvdpuxdsOp(XB,XT); }\n\ndefine pcodeop xscvspdpOp;\n# ISA-cmt: xscvspdp - VSX Scalar Convert Single-Precision to Double-Precision format\n# binutils: vsx.d: 44:\tf1 00 e5 27 \txscvspdp vs40,vs60\n:xscvspdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=329 & BITS_16_20=0 & XB & XT { xscvspdpOp(XB,XT); }\n\ndefine pcodeop xscvdpsxdsOp;\n# ISA-cmt: xscvdpsxds - VSX Scalar truncate Double-Precision to integer and Convert to Signed Fixed-Point Doubleword format with Saturate\n# ISA-info: xscvdpsxds - Form \"XX2\" Page 353 Category \"VSX\"\n# binutils: vsx.d: 34:\tf1 00 e5 63 \txscvdpsxds vs40,vs60\n:xscvdpsxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=344 & BITS_16_20=0 & XB & XT { xscvdpsxdsOp(XB,XT); }\n\ndefine pcodeop xsabsdpOp;\n# ISA-cmt: xsabsdp - VSX Scalar Absolute Value Double-Precision\n# ISA-info: xsabsdp - Form \"XX2\" Page 341 Category \"VSX\"\n# binutils: vsx.d: 1c:\tf1 00 e5 67 \txsabsdp vs40,vs60\n:xsabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=345 & XT & BITS_16_20=0 & XB { xsabsdpOp(XB,XT); }\n\ndefine pcodeop xscvuxddpOp;\n# ISA-cmt: xscvuxddp - VSX Scalar Convert and round Unsigned Fixed-Point Doubleword to Double-Precision format\n# binutils: vsx.d: 4c:\tf1 00 e5 a3 \txscvuxddp vs40,vs60\n:xscvuxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=360 & BITS_16_20=0 & XB & XT { xscvuxddpOp(XB,XT); }\n\ndefine pcodeop xsnabsdpOp;\n# ISA-cmt: xsnabsdp - VSX Scalar Negative Absolute Value Double-Precision\n# ISA-info: xsnabsdp - Form \"XX2\" Page 377 Category \"VSX\"\n# binutils: vsx.d: 70:\tf1 00 e5 a7 \txsnabsdp vs40,vs60\n:xsnabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=361 & BITS_16_20=0 & XB & XT { xsnabsdpOp(XB,XT); }\n\ndefine pcodeop xscvsxddpOp;\n# ISA-cmt: xscvsxddp - VSX Scalar Convert and round Signed Fixed-Point Doubleword to Double-Precision format\n# ISA-info: xscvsxddp - Form \"XX2\" Page 361 Category \"VSX\"\n# binutils: vsx.d: 48:\tf1 00 e5 e3 \txscvsxddp vs40,vs60\n:xscvsxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=376 & BITS_16_20=0 & XB & XT { xscvsxddpOp(XB,XT); }\n\ndefine pcodeop xsnegdpOp;\n# ISA-cmt: xsnegdp - VSX Scalar Negate Double-Precision\n# ISA-info: xsnegdp - Form \"XX2\" Page 377 Category \"VSX\"\n# binutils: vsx.d: 74:\tf1 00 e5 e7 \txsnegdp vs40,vs60\n:xsnegdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=377 & BITS_16_20=0 & XB & XT { xsnegdpOp(XB,XT); }\n\ndefine pcodeop xvcvspuxdsOp;\n# ISA-cmt: xvcvspuxds - VSX Vector truncate Single-Precision to integer and Convert to Unsigned Fixed-Point Doubleword format with Saturate\n# ISA-info: xvcvspuxds - Form \"XX2\" Page 425 Category \"VSX\"\n# binutils: vsx.d: 12c:\tf1 00 e6 23 \txvcvspuxds vs40,vs60\n:xvcvspuxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=392 & BITS_16_20=0 & XB & XT { xvcvspuxdsOp(XB,XT); }\n\ndefine pcodeop xvcvdpspOp;\n# ISA-cmt: xvcvdpsp - VSX Vector round and Convert Double-Precision to Single-Precision format\n# ISA-info: xvcvdpsp - Form \"XX2\" Page 411 Category \"VSX\"\n# binutils: vsx.d: 10c:\tf1 00 e6 27 \txvcvdpsp vs40,vs60\n:xvcvdpsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=393 & BITS_16_20=0 & XB & XT { xvcvdpspOp(XB,XT); }\n\ndefine pcodeop xvcvspsxdsOp;\n# ISA-cmt: xvcvspsxds - VSX Vector truncate Single-Precision to integer and Convert to Signed Fixed-Point Doubleword format with Saturate\n# ISA-info: xvcvspsxds - Form \"XX2\" Page 421 Category \"VSX\"\n# binutils: vsx.d: 124:\tf1 00 e6 63 \txvcvspsxds vs40,vs60\n:xvcvspsxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=408 & BITS_16_20=0 & XB & XT { xvcvspsxdsOp(XB,XT); }\n\ndefine pcodeop xvabsspOp;\n# ISA-cmt: xvabssp - VSX Vector Absolute Value Single-Precision\n# ISA-info: xvabssp - Form \"XX2\" Page 397 Category \"VSX\"\n# binutils: vsx.d: b8:\tf1 00 e6 67 \txvabssp vs40,vs60\n:xvabssp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=409 & BITS_16_20=0 & XB & XT { xvabsspOp(XB,XT); }\n\ndefine pcodeop xvcvuxdspOp;\n# ISA-cmt: xvcvuxdsp - VSX Vector Convert and round Unsigned Fixed-Point Doubleword to Single-Precision format\n# ISA-info: xvcvuxdsp - Form \"XX2\" Page 431 Category \"VSX\"\n# binutils: vsx.d: 148:\tf1 00 e6 a3 \txvcvuxdsp vs40,vs60\n:xvcvuxdsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=424 & BITS_16_20=0 & XB & XT { xvcvuxdspOp(XB,XT); }\n\ndefine pcodeop xvnabsspOp;\n# ISA-cmt: xvnabssp - VSX Vector Negative Absolute Value Single-Precision\n# ISA-info: xvnabssp - Form \"XX2\" Page 461 Category \"VSX\"\n# binutils: vsx.d: 198:\tf1 00 e6 a7 \txvnabssp vs40,vs60\n:xvnabssp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=425 & BITS_16_20=0 & XB & XT { xvnabsspOp(XB,XT); }\n\ndefine pcodeop xvcvsxdspOp;\n# ISA-cmt: xvcvsxdsp - VSX Vector Convert and round Signed Fixed-Point Doubleword to Single-Precision format\n# ISA-info: xvcvsxdsp - Form \"XX2\" Page 429 Category \"VSX\"\n# binutils: vsx.d: 138:\tf1 00 e6 e3 \txvcvsxdsp vs40,vs60\n:xvcvsxdsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=440 & BITS_16_20=0 & XB & XT { xvcvsxdspOp(XB,XT); }\n\ndefine pcodeop xvnegspOp;\n# ISA-cmt: xvnegsp - VSX Vector Negate Single-Precision\n# ISA-info: xvnegsp - Form \"XX2\" Page 462 Category \"VSX\"\n# binutils: vsx.d: 1a0:\tf1 00 e6 e7 \txvnegsp vs40,vs60\n:xvnegsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=441 & BITS_16_20=0 & XB & XT { xvnegspOp(XB,XT); }\n\ndefine pcodeop xvcvdpuxdsOp;\n# ISA-cmt: xvcvdpuxds - VSX Vector truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Doubleword format with Saturate\n# ISA-info: xvcvdpuxds - Form \"XX2\" Page 416 Category \"VSX\"\n# binutils: vsx.d: 118:\tf1 00 e7 23 \txvcvdpuxds vs40,vs60\n:xvcvdpuxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=456 & BITS_16_20=0 & XB & XT { xvcvdpuxdsOp(XB,XT); }\n\ndefine pcodeop xvcvspdpOp;\n# ISA-cmt: xvcvspdp - VSX Vector Convert Single-Precision to Double-Precision\n# ISA-info: xvcvspdp - Form \"XX2\" Page 420 Category \"VSX\"\n# binutils: vsx.d: 120:\tf1 00 e7 27 \txvcvspdp vs40,vs60\n:xvcvspdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=457 & BITS_16_20=0 & XB & XT { xvcvspdpOp(XB,XT); }\n\ndefine pcodeop xvcvdpsxdsOp;\n# ISA-cmt: xvcvdpsxds - VSX Vector truncate Double-Precision to integer and Convert to Signed Fixed-Point Doubleword Saturate\n# ISA-info: xvcvdpsxds - Form \"XX2\" Page 412 Category \"VSX\"\n# binutils: vsx.d: 110:\tf1 00 e7 63 \txvcvdpsxds vs40,vs60\n:xvcvdpsxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=472 & BITS_16_20=0 & XB & XT { xvcvdpsxdsOp(XB,XT); }\n\ndefine pcodeop xvabsdpOp;\n# ISA-cmt: xvabsdp - VSX Vector Absolute Value Double-Precision\n# ISA-info: xvabsdp - Form \"XX2\" Page 397 Category \"VSX\"\n# binutils: vsx.d: b4:\tf1 00 e7 67 \txvabsdp vs40,vs60\n:xvabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=473 & BITS_16_20=0 & XB & XT { xvabsdpOp(XB,XT); }\n\ndefine pcodeop xvcvuxddpOp;\n# ISA-cmt: xvcvuxddp - VSX Vector Convert and round Unsigned Fixed-Point Doubleword to Double-Precision format\n# ISA-info: xvcvuxddp - Form \"XX2\" Page 431 Category \"VSX\"\n# binutils: vsx.d: 144:\tf1 00 e7 a3 \txvcvuxddp vs40,vs60\n:xvcvuxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=488 & BITS_16_20=0 & XB & XT { xvcvuxddpOp(XB,XT); }\n\ndefine pcodeop xvnabsdpOp;\n# ISA-cmt: xvnabsdp - VSX Vector Negative Absolute Value Double-Precision\n# ISA-info: xvnabsdp - Form \"XX2\" Page 461 Category \"VSX\"\n# binutils: vsx.d: 194:\tf1 00 e7 a7 \txvnabsdp vs40,vs60\n:xvnabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=489 & BITS_16_20=0 & XB & XT { xvnabsdpOp(XB,XT); }\n\ndefine pcodeop xvcvsxddpOp;\n# ISA-cmt: xvcvsxddp - VSX Vector Convert and round Signed Fixed-Point Doubleword to Double-Precision format\n# ISA-info: xvcvsxddp - Form \"XX2\" Page 429 Category \"VSX\"\n# binutils: vsx.d: 134:\tf1 00 e7 e3 \txvcvsxddp vs40,vs60\n:xvcvsxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=504 & BITS_16_20=0 & XB & XT { xvcvsxddpOp(XB,XT); }\n\ndefine pcodeop xvnegdpOp;\n# ISA-cmt: xvnegdp - VSX Vector Negate Double-Precision\n# ISA-info: xvnegdp - Form \"XX2\" Page 462 Category \"VSX\"\n# binutils: vsx.d: 19c:\tf1 00 e7 e7 \txvnegdp vs40,vs60\n:xvnegdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=505 & BITS_16_20=0 & XB & XT { xvnegdpOp(XB,XT); }\n\ndefine pcodeop vsx207_1;\ndefine pcodeop vsx207_2;\ndefine pcodeop vsx207_3;\ndefine pcodeop vsx207_5;\ndefine pcodeop vsx207_8;\ndefine pcodeop vsx207_9;\ndefine pcodeop vsx207_10;\ndefine pcodeop vsx207_11;\ndefine pcodeop vsx207_12;\ndefine pcodeop vsx207_13;\ndefine pcodeop vsx207_14;\ndefine pcodeop vsx207_15;\ndefine pcodeop vsx207_16;\ndefine pcodeop vsx207_17;\ndefine pcodeop vsx207_18;\ndefine pcodeop vsx207_19;\ndefine pcodeop vsx207_20;\ndefine pcodeop vsx207_21;\ndefine pcodeop vsx207_22;\ndefine pcodeop vsx207_23;\ndefine pcodeop vsx207_24;\ndefine pcodeop vsx207_25;\ndefine pcodeop vsx207_26;\ndefine pcodeop vsx207_27;\ndefine pcodeop vsx207_28;\ndefine pcodeop vsx207_29;\ndefine pcodeop vsx207_30;\n\ndefine pcodeop vsx300_1;\ndefine pcodeop vsx300_2;\ndefine pcodeop vsx300_3;\ndefine pcodeop vsx300_4;\ndefine pcodeop vsx300_5;\ndefine pcodeop vsx300_7;\ndefine pcodeop vsx300_8;\ndefine pcodeop vsx300_9;\ndefine pcodeop vsx300_10;\ndefine pcodeop vsx300_11;\ndefine pcodeop vsx300_12;\ndefine pcodeop vsx300_13;\ndefine pcodeop vsx300_14;\ndefine pcodeop vsx300_15;\ndefine pcodeop vsx300_16;\ndefine pcodeop vsx300_17;\ndefine pcodeop vsx300_18;\ndefine pcodeop vsx300_19;\ndefine pcodeop vsx300_20;\ndefine pcodeop vsx300_21;\ndefine pcodeop vsx300_22;\ndefine pcodeop vsx300_23;\ndefine pcodeop vsx300_25;\ndefine pcodeop vsx300_26;\ndefine pcodeop vsx300_27;\ndefine pcodeop vsx300_28;\ndefine pcodeop vsx300_29;\ndefine pcodeop vsx300_30;\ndefine pcodeop vsx300_31;\ndefine pcodeop vsx300_32;\ndefine pcodeop vsx300_33;\ndefine pcodeop vsx300_34;\ndefine pcodeop vsx300_35;\ndefine pcodeop vsx300_36;\ndefine pcodeop vsx300_37;\ndefine pcodeop vsx300_38;\ndefine pcodeop vsx300_39;\ndefine pcodeop vsx300_40;\ndefine pcodeop vsx300_41;\ndefine pcodeop vsx300_42;\ndefine pcodeop vsx300_43;\ndefine pcodeop vsx300_44;\ndefine pcodeop vsx300_45;\ndefine pcodeop vsx300_46;\ndefine pcodeop vsx300_47;\ndefine pcodeop vsx300_48;\ndefine pcodeop vsx300_49;\ndefine pcodeop vsx300_50;\ndefine pcodeop vsx300_51;\ndefine pcodeop vsx300_52;\ndefine pcodeop vsx300_53;\ndefine pcodeop vsx300_54;\ndefine pcodeop vsx300_55;\ndefine pcodeop vsx300_56;\ndefine pcodeop vsx300_57;\ndefine pcodeop vsx300_58;\ndefine pcodeop vsx300_59;\ndefine pcodeop vsx300_60;\ndefine pcodeop vsx300_61;\ndefine pcodeop vsx300_62;\ndefine pcodeop vsx300_63;\ndefine pcodeop vsx300_64;\ndefine pcodeop vsx300_65;\ndefine pcodeop vsx300_66;\ndefine pcodeop vsx300_67;\ndefine pcodeop vsx300_68;\ndefine pcodeop vsx300_69;\ndefine pcodeop vsx300_70;\ndefine pcodeop vsx300_71;\ndefine pcodeop vsx300_72;\ndefine pcodeop vsx300_73;\ndefine pcodeop vsx300_74;\ndefine pcodeop vsx300_75;\ndefine pcodeop vsx300_76;\ndefine pcodeop vsx300_77;\ndefine pcodeop vsx300_78;\ndefine pcodeop vsx300_79;\ndefine pcodeop vsx300_80;\ndefine pcodeop vsx300_81;\ndefine pcodeop vsx300_82;\ndefine pcodeop vsx300_83;\ndefine pcodeop vsx300_84;\ndefine pcodeop vsx300_85;\ndefine pcodeop vsx300_86;\ndefine pcodeop vsx300_87;\ndefine pcodeop vsx300_88;\ndefine pcodeop vsx300_89;\ndefine pcodeop vsx300_90;\ndefine pcodeop vsx300_91;\ndefine pcodeop vsx300_92;\ndefine pcodeop vsx300_93;\ndefine pcodeop vsx300_94;\ndefine pcodeop vsx300_95;\ndefine pcodeop vsx300_96;\ndefine pcodeop vsx300_97;\ndefine pcodeop vsx300_98;\ndefine pcodeop vsx300_99;\ndefine pcodeop vsx300_100;\ndefine pcodeop vsx300_101;\ndefine pcodeop vsx300_102;\ndefine pcodeop vsx300_103;\n\n#################\n# v2.07 additions\n:lxsiwax XT,A,B \t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=76 {\n\tXT = vsx207_1(A,B);\n} \n\n:lxsiwzx XT,A,B \t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=12 {\n\tXT = vsx207_2(A,B);\n} \n\n:lxsspx XT,A,B \t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=524 {\n\tXT = vsx207_3(A,B);\t\n} \n\n:mfvsrd A,XSF\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=51 & BITS_11_15=0 & XSF & A {\n\tA = XSF;\t\n}\n\n:mfvsrwz A,XSF\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=115 & BITS_11_15=0 & XSF & A {\n\tA[0,32] = XSF[0,32];\n\tA[32,32] = 0;\n}\n\n:mtvsrd XTF,A\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=179 & BITS_11_15=0 & XTF & A {\n\tXTF = A;\t\t\t\n}\n\n:mtvsrwa XTF,A\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=211 & BITS_11_15=0 & XTF & A {\n\tXTF = sext(A:4);\t\t\t\t\n}\n\n:mtvsrwz XTF,A\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=243 & BITS_11_15=0 & XTF & A {\n\tXTF = zext(A:4);\t\n}\n\n:stxsiwx XS,RA_OR_ZERO,B \tis $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=140 {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:4 EA = vsx207_9(XS,RA_OR_ZERO,B);\t\t\t\t\n}\n\n:stxsspx XS,RA_OR_ZERO,B \tis $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=652 {\n\tEA:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*[ram]:4 EA = vsx207_10(XS,RA_OR_ZERO,B);\t\t\t\t\n}\n\n:xsaddsp XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=0 & XA & XB & XT {\n\tXT = vsx207_11(XA,XB);\t\t\n}\n\n:xscvdpspn XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=267 & XB & XT\n{\n\tsrc:4 = float2float(XB:8);\n\tXT[0,32] = src;\n}\n\n:xscvspdpn XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=331 & XB & XT {\n\tXT = vsx207_13(XB);\t\t\t\t\n}\n\n:xscvsxdsp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=312 & XB & XT {\n\tXT = vsx207_14(XB);\t\t\t\n}\n\n:xscvuxdsp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=296 & XB & XT {\n\tXT = vsx207_15(XB);\t\t\t\t\n}\n\n:xsdivsp XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=24 & XA & XB & XT {\n\tXT = vsx207_16(XA,XB);\t\t\t\n}\n\n:xsmaddasp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=1 & XA & XB & XT {\n\tXT = vsx207_17(XA,XB);\t\t\t\t\n}\n\n:xsmaddmsp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=9 & XA & XB & XT {\n\tXT = vsx207_18(XA,XB);\t\t\t\t\n}\n\n:xsmsubasp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=17 & XA & XB & XT {\n\tXT = vsx207_19(XA,XB);\t\n}\n\n:xsmsubmsp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=25 & XA & XB & XT {\n\tXT = vsx207_20(XA,XB);\t\t\t\t\n}\n\n:xsmulsp XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=16 & XA & XB & XT {\n\tXT = vsx207_21(XA,XB);\t\t\t\t\n}\n\n:xsnmaddasp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=129 & XA & XB & XT {\n\tXT = vsx207_22(XA,XB);\t\t\t\t\n}\n\n:xsnmaddmsp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=137 & XA & XB & XT {\n\tXT = vsx207_23(XA,XB);\t\t\t\t\n}\n\n:xsnmsubasp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=145 & XA & XB & XT {\n\tXT = vsx207_24(XA,XB);\t\t\t\t\n}\n\n:xsnmsubmsp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=153 & XA & XB & XT {\n\tXT = vsx207_25(XA,XB);\t\t\t\t\n}\n\n:xsresp XT,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=26 & XB & XT {\n\tXT = vsx207_26(XB);\t\t\t\t\t\n}\n\n:xsrsp XT,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=281 & XB & XT {\n\tXT = vsx207_27(XB);\t\t\t\t\t\n}\n\n:xsrsqrtesp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=10 & XB & XT {\n\tXT = vsx207_28(XB);\t\t\t\t\t\n}\n\n:xssqrtsp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=11 & XB & XT {\n\tXT = vsx207_29(XB);\t\t\t\t\t\n}\n\n:xssubsp XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=8 & XA & XB & XT {\n\tXT = vsx207_30(XA,XB);\t\t\t\t\t\n}\n\n:xxleqv XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=186 & XA & XB & XT {\n\tXT = ~(XA ^ XB);\t\t\t\t\t\t\n}\n\n:xxlnand XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=178 & XA & XB & XT {\n\tXT = ~(XA & XB);\t\t\t\t\t\t\n}\n\n:xxlorc XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=170 & XA & XB & XT {\n\tXT = XA | (~XB);\t\t\t\t\t\t\n}\n\n#######################\n# v3.0\n\n# The endian behavior of the storage has not been modelled\n:lxsd vrD,DSs(RA_OR_ZERO) \tis $(NOTVLE) & OP=57 & vrD & RA_OR_ZERO & BITS_0_1=2 & DSs {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + (DSs << 2);\n\tvrD[0,64] = *:8 ea;\n}\n\n:lxsibzx XT,A,B \t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=781 {\n\tXT = vsx300_2(A,B);\n} \n\n:lxsihzx XT,A,B \t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=813 {\n\tXT = vsx300_3(A,B);\t\n} \n\n:lxssp vrD,DSs(RA_OR_ZERO) is $(NOTVLE) & OP=57 & vrD & RA_OR_ZERO & BITS_0_1=3 & DSs {\n\tvrD = vsx300_4(DSs:2,RA_OR_ZERO);\t\n}\n\n# The endian behavior of the storage has not been modelled\n:lxv XT3,DQs(RA_OR_ZERO) \tis $(NOTVLE) & OP=61 & XT3 & RA_OR_ZERO & BITS_0_2=1 & DQs {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + (DQs << 4);\n\tXT3 = *:16 ea;\n}\n\n:lxvx XT,RA_OR_ZERO,B \t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_5=12 & BIT_6=0 & XOP_7_10=4 & RA_OR_ZERO & B & XT {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\tXT = *:16 ea;\n}\n\n:lxvb16x XT,A,B \t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=876 {\n\tXT = vsx300_7(A,B);\t\n} \n\n:lxvh8x XT,A,B \t\t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=812 {\n\tXT = vsx300_8(A,B);\t\n} \n\n:lxvl XT,A,B \t\t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=269 {\n\tXT = vsx300_9(A,B);\t\t\n} \n\n:lxvll XT,A,B \t\t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=301 {\n\tXT = vsx300_10(A,B);\t\n} \n\n:lxvwsx XT,A,B \t\t\t\tis $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=364 {\n\tXT = vsx300_11(A,B);\t\n} \n\n:mfvsrld A,XSF\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=307 & BITS_11_15=0 & XSF & A {\n\tA = vsx300_12(XSF);\t\n}\n\n:mtvsrdd XTF,A,B \t\t\tis $(NOTVLE) & OP=31 & XTF & A & B & XOP_1_10=435 {\n\tXTF = vsx300_13(A,B);\t\n} \n\n:mtvsrws XTF,A\t\t\t\tis $(NOTVLE) & OP=31 & XOP_1_10=403 & BITS_11_15=0 & XTF & A {\n\tXTF = vsx300_14(A);\t\n}\n\n:stxsd vrS,DSs(RA_OR_ZERO) is $(NOTVLE) & OP=61 & vrS & RA_OR_ZERO & BITS_0_1=2 & DSs {\n\tvsx300_15(vrS,DSs:2,RA_OR_ZERO);\t\n}\n\n:stxsibx XS,A,B \t\t\tis $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=909 {\n\tvsx300_16(XS,A,B);\t\n} \n\n:stxsihx XS,A,B \t\t\tis $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=941 {\n\tvsx300_17(XS,A,B);\t\n} \n\n:stxssp vrS,DSs(RA_OR_ZERO)\tis $(NOTVLE) & OP=61 & vrS & RA_OR_ZERO & BITS_0_1=3 & DSs {\n\tvsx300_18(vrS,DSs:2,RA_OR_ZERO);\t\n}\n\n# The endian behavior of the storage has not been modelled\n:stxv XS3,DQs(RA_OR_ZERO) \tis $(NOTVLE) & OP=61 & XS3 & RA_OR_ZERO & BITS_0_2=5 & DQs {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + (DQs << 4);\n\t*:16 ea = XS3;\n}\n\n:stxvb16x XS,A,B \t\t\tis $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=1004 {\n\tvsx300_20(XS,A,B);\t\n} \n\n:stxvh8x XS,A,B \t\t\tis $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=940 {\n\tvsx300_21(XS,A,B);\n} \n\n:stxvl XS,A,B \t\t\t\tis $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=397 {\n\tvsx300_22(XS,A,B);\t\n} \n\n:stxvll XS,A,B \t\t\t\tis $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=429 {\n\tvsx300_23(XS,A,B);\t\n} \n\n:stxvx XS,RA_OR_ZERO,B \t\t\t\tis $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=396 {\n\tea:$(REGISTER_SIZE) = RA_OR_ZERO + B;\n\t*:16 ea = XS;\n} \n\n:xsabsqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=0 & BIT_0=0 & XOP_1_10=804 & vrD & vrB {\n\tvrD = vsx300_25(vrB);\t\n}\n\n:xsaddqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=4 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_26(vrA,vrB);\t\t\n}\n\n:xsaddqpo vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=4 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_27(vrA,vrB);\t\t\t\n}\n\n:xscmpeqdp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=3 & XA & XB & XT {\n\tXT = vsx300_28(XA,XB);\t\t\n}\n\n:xscmpexpdp BF2,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=59 & BITS_21_22=0 & BIT_0=0 & XA & XB & BF2 {\n\tvsx300_29(BF2:1,XA,XB);\t\t\t\n}\n\n:xscmpexpqp BF2,vrA,vrB \tis $(NOTVLE) & OP=63 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=164 & R0=0 & BF2 & vrA & vrB {\n\tvsx300_30(BF2:1,vrA,vrB);\t\t\t\t\n}\n\n:xscmpgedp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=19 & XA & XB & XT {\n\tXT = vsx300_31(XA,XB);\t\t\t\n}\n\n:xscmpgtdp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=11 & XA & XB & XT {\n\tXT = vsx300_32(XA,XB);\t\t\t\n}\n\n:xscmpnedp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=27 & XA & XB & XT {\n\tXT = vsx300_33(XA,XB);\t\t\t\n}\n\n:xscmpoqp BF2,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=132 & BITS_21_22=0 & BIT_0=0 & vrA & vrB & BF2 {\n\tvsx300_34(BF2:1,vrA,vrB);\t\t\t\t\n}\n\n:xscmpuqp BF2,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=644 & BITS_21_22=0 & BIT_0=0 & vrA & vrB & BF2 {\n\tvsx300_35(BF2:1,vrA,vrB);\t\t\t\t\n}\n\n:xscpsgnqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & BIT_0=0 & XOP_1_10=100 & vrD & vrA & vrB {\n\tvrD = vsx300_36(vrA,vrB);\t\t\n}\n\n:xscvdphp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=17 & XOP_2_10=347 & XB & XT {\n\tXT = vsx300_37(XB);\t\t\t\n}\n\n:xscvdpqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=22 & BIT_0=0 & XOP_1_10=836 & vrD & vrB {\n\tvrD = vsx300_38(vrB);\t\n}\n\n:xscvhpdp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=16 & XOP_2_10=347 & XB & XT {\n\tXT = vsx300_39(XB);\t\t\t\n}\n\n:xscvqpdp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=20 & XOP_1_10=836 & R0=0 & vrD & vrB {\n\tvrD = vsx300_40(vrB);\t\n}\n\n:xscvqpdpo vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=20 & XOP_1_10=836 & R0=1 & vrD & vrB {\n\tvrD = vsx300_41(vrB);\t\n}\n\n:xscvqpsdz vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=25 & XOP_1_10=836 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_42(vrB);\t\n}\n\n:xscvqpswz vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=9 & XOP_1_10=836 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_43(vrB);\t\n}\n\n:xscvqpudz vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=17 & XOP_1_10=836 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_44(vrB);\t\n}\n\n:xscvqpuwz vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=1 & XOP_1_10=836 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_45(vrB);\t\n}\n\n:xscvsdqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=10 & XOP_1_10=836 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_46(vrB);\t\n}\n\n:xscvudqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=2 & XOP_1_10=836 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_47(vrB);\t\n}\n\n:xsdivqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=548 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_47(vrA,vrB);\t\n}\n\n:xsdivqpo vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=548 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_48(vrA,vrB);\t\n}\n\n:xsiexpdp XT,A,B \t\t\tis $(NOTVLE) & OP=60 & XT & A & B & XOP_1_10=918 {\n\tvsx300_49(A,B);\t\n} \n\n:xsiexpqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & BIT_0=0 & XOP_1_10=868 & vrD & vrA & vrB {\n\tvrD = vsx300_50(vrA,vrB);\t\n}\n\n:xsmaddqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=388 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_51(vrA,vrB);\t\n}\n\n:xsmaddqpo vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=388 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_52(vrA,vrB);\t\n}\n\n:xsmaxcdp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=128 & XA & XB & XT {\n\tXT = vsx300_53(XA,XB);\t\t\n}\n\n:xsmaxjdp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=144 & XA & XB & XT {\n\tXT = vsx300_54(XA,XB);\t\t\n}\n\n:xsmincdp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=136 & XA & XB & XT {\n\tXT = vsx300_55(XA,XB);\t\t\n}\n\n:xsminjdp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_10=152 & XA & XB & XT {\n\tXT = vsx300_56(XA,XB);\t\t\n}\n\n:xsmsubqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=420 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_57(vrA,vrB);\t\n}\n\n:xsmsubqpo vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=420 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_58(vrA,vrB);\t\n}\n\n:xsmulqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=36 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_59(vrA,vrB);\t\n}\n\n:xsmulqpo vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=36 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_60(vrA,vrB);\t\n}\n\n:xsnabsqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=8 & XOP_1_10=804 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_61(vrB);\t\n}\n\n:xsnegqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=16 & XOP_1_10=804 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_62(vrB);\t\n}\n\n:xsnmaddqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=452 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_63(vrA,vrB);\t\n}\n\n:xsnmaddqpo vrD,vrA,vrB \tis $(NOTVLE) & OP=63 & XOP_1_10=452 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_64(vrA,vrB);\t\n}\n\n:xsnmsubqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=484 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_65(vrA,vrB);\t\n}\n\n:xsnmsubqpo vrD,vrA,vrB \tis $(NOTVLE) & OP=63 & XOP_1_10=484 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_66(vrA,vrB);\t\n}\n\n:xsrqpi R16,vrD,vrB,RMC\t\tis $(NOTVLE) & OP=63 & BITS_17_20=0 & XOP_1_8=5 & EX=0 & vrD & vrB & R16 & RMC {\n\tvrD = vsx300_67(vrB,RMC:1,R16:1);\t\n}\n\n:xsrqpix R16,vrD,vrB,RMC\tis $(NOTVLE) & OP=63 & BITS_17_20=0 & XOP_1_8=5 & EX=1 & vrD & vrB & R16 & RMC {\n\tvrD = vsx300_68(vrB,RMC:1,R16:1);\t\n}\n\n:xsrqpxp R16,vrD,vrB,RMC\tis $(NOTVLE) & OP=63 & BITS_17_20=0 & XOP_1_8=37 & BIT_0=0 & vrD & vrB & R16 & RMC {\n\tvrD = vsx300_69(vrB,RMC:1,R16:1);\t\n}\n\n:xssqrtqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=27 & XOP_1_10=804 & R0=0 & vrD & vrB {\n\tvrD = vsx300_70(vrB);\t\n}\n\n:xssqrtqpo vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=27 & XOP_1_10=804 & R0=1 & vrD & vrB {\n\tvrD = vsx300_71(vrB);\t\n}\n\n:xssubqp vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=516 & R0=0 & vrD & vrA & vrB {\n\tvrD = vsx300_72(vrA,vrB);\t\n}\n\n:xssubqpo vrD,vrA,vrB \t\tis $(NOTVLE) & OP=63 & XOP_1_10=516 & R0=1 & vrD & vrA & vrB {\n\tvrD = vsx300_73(vrA,vrB);\t\n}\n\n:xststdcdp BF2,XB,DCMX \t\tis $(NOTVLE) & OP=60 & BIT_0=0 & XOP_2_10=362 & XB & BF2 & DCMX {\n\tvsx300_74(XB,BF2:1,DCMX:1);\t\t\n}\n\n:xststdcqp BF2,vrB,DCMX \tis $(NOTVLE) & OP=63 & XOP_1_10=708 & BIT_0=0 & vrB & BF2 & DCMX {\n\tvsx300_75(vrB,BF2:1,DCMX:1);\t\t\n}\n\n:xststdcsp BF2,XB,DCMX \t\tis $(NOTVLE) & OP=60 & BIT_0=0 & XOP_2_10=298 & XB & BF2 & DCMX {\n\tvsx300_76(XB,BF2:1,DCMX:1);\t\t\n}\n\n:xsxexpdp D,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & BIT_0=0 & XOP_2_10=347 & XB & D {\n\tD = vsx300_77(XB);\t\t\n}\n\n:xsxexpqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=2 & XOP_1_10=804 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_78(vrB);\t\n}\n\n:xsxsigdp D,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=1 & BIT_0=0 & XOP_2_10=347 & XB & D {\n\tD = vsx300_79(XB);\t\t\n}\n\n:xsxsigqp vrD,vrB \t\t\tis $(NOTVLE) & OP=63 & BITS_16_20=18 & XOP_1_10=804 & BIT_0=0 & vrD & vrB {\n\tvrD = vsx300_80(vrB);\t\n}\n\n:xvcmpnedp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_9=123 & Rc2=0 & XA & XB & XT {\n\tXT = vsx300_81(XA,XB);\t\n}\n\n:xvcmpnedp. XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_9=123 & Rc2=1 & XA & XB & XT {\n\tXT = vsx300_82(XA,XB);\t\n}\n\n:xvcmpnesp XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_9=91 & Rc2=0 & XA & XB & XT {\n\tXT = vsx300_83(XA,XB);\t\n}\n\n:xvcmpnesp. XT,XA,XB \t\tis $(NOTVLE) & OP=60 & XOP_3_9=91 & Rc2=1 & XA & XB & XT {\n\tXT = vsx300_84(XA,XB);\t\n}\n\n:xvcvhpsp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=24 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_85(XB);\t\n}\n\n:xvcvsphp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=25 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_86(XB);\t\n}\n\n:xviexpdp XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=248 & XA & XB & XT {\n\tXT = vsx300_87(XA,XB);\t\n}\n\n:xviexpsp XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=216 & XA & XB & XT {\n\tXT = vsx300_88(XA,XB);\t\n}\n\n:xvtstdcdp XT,XB,DBUILD\t\tis $(NOTVLE) & OP=60 & XOP_3_5=5 & XOP_7_10=15 & XA & XB & XT & DBUILD {\n\tXT = vsx300_89(XB,DBUILD);\t\n}\n\n:xvtstdcsp XT,XB,DBUILD\t\tis $(NOTVLE) & OP=60 & XOP_3_5=5 & XOP_7_10=13 & XA & XB & XT & DBUILD {\n\tXT = vsx300_90(XB,DBUILD);\t\n}\n\n:xvxexpdp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_91(XB);\t\n}\n\n:xvxexpsp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=8 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_92(XB);\t\n}\n\n:xvxsigdp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=1 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_93(XB);\t\n}\n\n:xvxsigsp XT,XB \t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=9 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_94(XB);\t\n}\n\n:xxbrd XT,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=23 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_95(XB);\t\n}\n\n:xxbrh XT,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=7 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_96(XB);\t\n}\n\n:xxbrq XT,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=31 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_97(XB);\t\n}\n\n:xxbrw XT,XB \t\t\t\tis $(NOTVLE) & OP=60 & BITS_16_20=15 & XOP_2_10=475 & XB & XT {\n\tXT = vsx300_98(XB);\t\n}\n\n:xxextractuw XT,XB,UIMB \tis $(NOTVLE) & OP=60 & BIT_20=0 & XOP_2_10=165 & XB & XT & UIMB {\n\tXT = vsx300_99(XB,UIMB:1);\t\n}\n\n:xxinsertw XT,XB,UIMB \t\tis $(NOTVLE) & OP=60 & BIT_20=0 & XOP_2_10=181 & XB & XT & UIMB {\n\tXT = vsx300_100(XB,UIMB:1);\t\n}\n\n:xxperm XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=26 & XA & XB & XT {\n\tXT = vsx300_101(XA,XB);\t\n}\n\n:xxpermr XT,XA,XB \t\t\tis $(NOTVLE) & OP=60 & XOP_3_10=58 & XA & XB & XT {\n\tXT = vsx300_102(XA,XB);\t\n}\n\n:xxspltib XT,UIMM8 \t\t\tis $(NOTVLE) & OP=60 & BITS_19_20=0 & XOP_1_10=360 & XT & UIMM8 {\n\ttmpa:16 = zext(UIMM8:1);\n\ttmpa = tmpa | (tmpa << 8);\n\ttmpa = tmpa | (tmpa << 16);\n\ttmpa = tmpa | (tmpa << 32);\n\ttmpa = tmpa | (tmpa << 64);\n\tXT = tmpa;\n}\n" }, { "path": "pypcode/processors/PowerPC/data/manuals/PowerISA.idx", "content": "@OPF_PowerISA_v3.1.pdf [OpenPower Power ISA, Version 3.1, May 1, 2020]\nadd., 103\nadd, 103\naddc., 104\naddc, 104\naddco., 104\naddco, 104\nadde., 104\nadde, 104\naddeo., 104\naddeo, 104\naddex, 106\naddg6s, 144\naddi, 102\naddic, 103\naddic., 103\naddis, 102\naddme., 105\naddme, 105\naddmeo., 105\naddmeo, 105\naddo., 103\naddo, 103\naddpcis, 102\naddze., 105\naddze, 105\naddzeo., 105\naddzeo, 105\nand., 126\nand, 126\nandc., 127\nandc, 127\nandi., 125\nandis., 125\nb, 67\nba, 67\nbl, 67\nbla, 67\nbc, 67\nbca, 67\nbcl, 67\nbcla, 67\nbcctr, 68\nbcctrl, 68\nbcdadd., 504\nbcdcfn., 506\nbcdcfsq., 511\nbcdcfz., 507\nbcdcpsgn., 515\nbcdctn., 509\nbcdctsq., 512\nbcdctz., 510\nbcds., 517\nbcdsetsgn., 516\nbcdsr., 519\nbcdsub., 504\nbcdtrunc., 520\nbcdus., 518\nbcdutrunc., 521\nbclr, 68\nbclrl, 68\nbctar, 69\nbctarl, 69\nbpermd, 131\nbrd, 145\nbrh, 145\nbrw, 145\ncbcdtd, 143\ncdtbcd, 143\ncfuged, 132\nclrbhrb, 1129\ncmp, 119\ncmpb, 128\ncmpeqb, 121\ncmpi, 119\ncmpl, 119\ncmpli, 119\ncmprb, 120\ncntlzd., 130\ncntlzd, 130\ncntlzdm, 131\ncntlzw., 128\ncntlzw, 128\ncnttzd, 130\ncnttzd., 130\ncnttzdm, 131\ncnttzw, 128\ncnttzw., 128\ncopy, 1094\ncp_abort, 1095\ncrand, 70\ncrandc, 71\ncreqv, 71\ncrnand, 70\ncrnor, 71\ncror, 70\ncrorc, 71\ncrxor, 70\ndadd., 232\ndadd, 232\ndaddq., 232\ndaddq, 232\ndarn, 112\ndcbf, 1090\ndcbst, 1089\ndcbt, 1087\ndcbtst, 1088\ndcbz, 1089\ndcffix., 257\ndcffix, 257\ndcffixq., 257\ndcffixq, 257\ndcffixqq, 258\ndcmpo, 238\ndcmpoq, 238\ndcmpu, 237\ndcmpuq, 237\ndctdp., 255\ndctdp, 255\ndctfix.,259\ndctfix,259\ndctfixq.,259\ndctfixq,259\ndctfixqq,259\ndctqpq., 255\ndctqpq, 255\nddedpd., 261\nddedpd, 261\nddedpdq., 261\nddedpdq, 261\nddiv., 235\nddiv, 235\nddivq., 235\nddivq, 235\ndenbcd., 261\ndenbcd, 261\ndenbcdq., 261\ndenbcdq, 261\ndiex., 262\ndiex, 262\ndiexq., 262\ndiexq, 262\ndivd., 115\ndivd, 115\ndivde., 116\ndivde, 116\ndivdeo., 116\ndivdeo, 116\ndivdeu., 116\ndivdeu, 116\ndivdeuo., 116\ndivdeuo, 116\ndivdo., 115\ndivdo, 115\ndivdu., 115\ndivdu, 115\ndivduo., 115\ndivduo, 115\ndivw., 108\ndivw, 108\ndivwe., 109\ndivwe, 109\ndivweo., 109\ndivweo, 109\ndivweu., 109\ndivweu, 109\ndivweuo., 109\ndivweuo, 109\ndivwo., 108\ndivwo, 108\ndivwu., 108\ndivwu, 108\ndivwuo., 108\ndivwuo, 108\ndmul., 234\ndmul, 234\ndmulq., 234\ndmulq, 234\ndqua., 245\ndqua, 245\ndquai., 243\ndquai, 243\ndquaiq., 243\ndquaiq, 243\ndquaq., 245\ndquaq, 245\ndrdpq., 256\ndrdpq, 256\ndrintn., 252\ndrintn, 252\ndrintnq., 252\ndrintnq, 252\ndrintx., 250\ndrintx, 250\ndrintxq., 250\ndrintxq, 250\ndrrnd., 247\ndrrnd, 247\ndrrndq., 247\ndrrndq, 247\ndrsp., 256\ndrsp, 256\ndscli., 264\ndscli, 264\ndscliq., 264\ndscliq, 264\ndscri., 264\ndscri, 264\ndscriq., 264\ndscriq, 264\ndsub., 232\ndsub, 232\ndsubq., 232\ndsubq, 232\ndtstdc, 239\ndtstdcq, 239\ndtstdg, 239\ndtstdgq, 239\ndtstex, 240\ndtstexq, 240\ndtstsf, 241\ndtstsfi, 242 \ndtstsfiq, 242 \ndtstsfq, 241\ndxex., 262\ndxex, 262\ndxexq., 262\ndxexq, 262\neieio, 1114 \neqv., 127\neqv, 127\nextsb., 128\nextsb, 128\nextsh., 128\nextsh, 128\nextsw., 130\nextsw, 130\nextswsli., 142\nextswsli, 142\nfabs., 187\nfabs, 187\nfadd., 189\nfadd, 189\nfadds., 189\nfadds, 189\nfcfid., 200\nfcfid, 200\nfcfids., 201\nfcfids, 201\nfcfidu., 201\nfcfidu, 201\nfcfidus., 202\nfcfidus, 202\nfcmpo, 205\nfcmpu, 205\nfcpsgn., 187\nfcpsgn, 187\nfctid., 196\nfctid, 196\nfctidu., 197\nfctidu, 197\nfctiduz., 198\nfctiduz, 198\nfctidz., 197\nfctidz, 197\nfctiw., 198\nfctiw, 198\nfctiwu., 199\nfctiwu, 199\nfctiwuz., 200\nfctiwuz, 200\nfctiwz., 199\nfctiwz, 199\nfdiv., 190\nfdiv, 190\nfdivs., 190\nfdivs, 190\nfmadd., 194\nfmadd, 194\nfmadds., 194\nfmadds, 194\nfmr., 187\nfmr, 187\nfmrgew, 188\nfmrgow, 188\nfmsub., 194\nfmsub, 194\nfmsubs., 194\nfmsubs, 194\nfmul., 190\nfmul, 190\nfmuls., 190\nfmuls, 190\nfnabs., 187\nfnabs, 187\nfneg., 187\nfneg, 187\nfnmadd., 195\nfnmadd, 195\nfnmadds., 195\nfnmadds, 195\nfnmsub., 195\nfnmsub, 195\nfnmsubs., 195\nfnmsubs, 195\nfre., 191\nfre, 191\nfres., 191\nfres, 191\nfrim., 204\nfrim, 204\nfrin.,204\nfrin, 204\nfrip., 204\nfrip, 204\nfriz., 204\nfriz, 204\nfrsp., 196\nfrsp, 196\nfrsqrte., 192\nfrsqrte, 192\nfrsqrtes., 192\nfrsqrtes, 192\nfsel., 206\nfsel, 206\nfsqrt., 191\nfsqrt, 191\nfsqrts., 191\nfsqrts, 191\nfsub., 189\nfsub, 189\nfsubs., 189\nfsubs, 189\nftdiv, 192\nftsqrt, 193\nhrfid, 1178\nicbi, 1078\nicbt, 1078\nisel, 124\nisync, 1102\nlbarx, 1103\nlbz, 78\nlbzcix, 1190\nlbzu, 78\nlbzux, 78\nlbzx, 78\nld, 83\nldarx, 1108\nldat, 1099\nldbrx, 95\nldcix, 1190\nldu, 83\nldux, 83\nldx, 83\nlfd, 178\nlfdp, 185\nlfdpx, 185\nlfdu, 178\nlfdux, 178\nlfdx, 178\nlfiwax, 179\nlfiwzx, 179\nlfs, 176\nlfsu, 176\nlfsux, 177\nlfsx, 176\nlha, 80\nlharx, 1104\nlhau, 80\nlhaux, 80\nlhax, 80\nlhbrx, 93\nlhz, 79\nlhzcix, 1190\nlhzu, 79\nlhzux, 79\nlhzx, 79\nlmw, 96\nlq, 91\nlqarx, 1110\nlswi, 98\nlswx, 98\nlvebx, 294\nlvehx, 295\nlvewx, 296\nlvsl, 303\nlvsr, 303\nlvx, 297\nlvxl, 297\nlwa, 82\nlwarx, 1104\nlwat, 1099\nlwaux, 82\nlwax, 82\nlwbrx, 94\nlwz, 81\nlwzcix, 1190\nlwzu, 81\nlwzux, 81\nlwzx, 81\nlxsd, 636\nlxsdx, 637\nlxsibzx, 638\nlxsihzx, 638\nlxsiwax, 639\nlxsiwzx, 640\nlxssp, 641\nlxsspx, 642\nlxv, 643\nlxvb16x, 644\nlxvd2x, 645\nlxvdsx, 659\nlxvh8x, 660\nlxvkq, 646\nlxvl, 647\nlxvll, 649\nlxvp, 651 \nlxvpx, 652\nlxvrbx, 653\nlxvrdx, 654\nlxvrhx, 655\nlxvrwx, 656\nlxvw4x, 661\nlxvwsx, 662\nlxvx, 657\nmaddhd, 114\nmaddhdu, 114\nmaddld, 114\nmcrf, 72\nmcrfs, 210\nmcrxrx, 153\nmfbhrbe, 1129\nmfcr, 154\nmffs., 208\nmffs, 208\nmffscdrn, 208\nmffscdrni, 209\nmffsce, 208\nmffscrn, 209\nmffscrni, 209\nmffsl, 209\nmfmsr, 1202\nmfocrf, 154\nmfspr, 152\nmftb, 1120\nmfvscr, 522\nmfvsrd, 146\nmfvsrld, 146\nmfvsrwz, 147\nmodsd, 117\nmodsw, 111\nmodud, 117\nmoduw, 111\nmsgclr, 1355\nmsgclrp, 1357\nmsgclru, 1354\nmsgsnd, 1354\nmsgsndp, 1356\nmsgsndu, 1353\nmsgsync, 1357\nmtcrf, 153\nmtfsb0., 211\nmtfsb0, 211\nmtfsb1., 211\nmtfsb1, 211\nmtfsf., 210\nmtfsf, 210\nmtfsfi., 210\nmtfsfi, 210\nmtmsr, 1200\nmtmsrd, 1201\nmtocrf, 153\nmtspr, 150\nmtvscr, 522\nmtvsrbm, 489\nmtvsrbmi, 491\nmtvsrd, 147\nmtvsrdd, 149\nmtvsrdm, 490\nmtvsrhm, 489\nmtvsrqm, 491\nmtvsrwa, 148\nmtvsrwm, 490\nmtvsrws, 149\nmtvsrwz, 148\nmulhd., 113\nmulhd, 113\nmulhdu., 113\nmulhdu, 113\nmulhw., 107\nmulhw, 107\nmulhwu., 107\nmulhwu, 107\nmulld., 113\nmulld, 113\nmulldo., 113\nmulldo, 113\nmulli, 107\nmullw., 107\nmullw, 107\nmullwo., 107\nmullwo, 107\nnand., 126\nnand, 126\nneg., 106\nneg, 106\nnego., 106\nnego, 106\nnor.,127\nnor, 127\nor., 127\nor, 127\norc., 127\norc, 127\nori, 125\noris, 126\npaddi, 102\npaste., 1094\npaste, 1094\npdepd, 132\npextd, 132\nplbz, 78\npld, 83\nplfd, 178\nplfs, 176\nplha, 80\nplhz, 79\nplq, 91\nplwa, 82\nplwz, 81\nplxsd, 636\nplxssp, 641\nplxv, 643\nplxvp, 651\npmxvbf16ger2, 853\npmxvbf16ger2nn, 853\npmxvbf16ger2np, 853\npmxvbf16ger2pn, 853\npmxvbf16ger2pp, 853\npmxvf16ger2 , 897\npmxvf16ger2nn, 897\npmxvf16ger2np, 897\npmxvf16ger2pn, 897\npmxvf16ger2pp, 897\npmxvf32ger, 901\npmxvf32gernn, 901\npmxvf32gernp, 901\npmxvf32gerpn, 901\npmxvf32gerpp, 901\npmxvf64ger, 905\npmxvf64gernn, 905\npmxvf64gernp, 905\npmxvf64gerpn, 905\npmxvf64gerpp, 905\npmxvi16ger2, 917\npmxvi16ger2pp, 917\npmxvi16ger2s, 919\npmxvi16ger2spp, 919\npmxvi4ger8, 909\npmxvi4ger8pp, 909\npmxvi8ger4, 912\npmxvi8ger4pp, 912\npmxvi8ger4spp, 915\npnop, 156\npopcntb, 129\npopcntd, 130\npopcntw, 129\nprtyd, 130\nprtyw, 129\npstb, 85\npstd, 88\npstfd, 183\npstfs, 181\npsth, 86\npstq, 92\npstw, 87\npstxsd, 664\npstxssp, 668\npstxv, 670\npstxvp, 680\nrfebb, 1126\nrfid, 1178\nrfscv, 1177\nrldcl., 137\nrldcl, 137\nrldcr., 138\nrldcr, 138\nrldic., 137\nrldic, 137\nrldicl., 136\nrldicl, 136\nrldicr., 136\nrldicr, 136\nrldimi., 138\nrldimi, 138\nrlwimi., 134\nrlwimi, 134\nrlwinm., 133\nrlwinm, 133\nrlwnm., 134\nrlwnm, 134\nsc, 73\nscv, 73\nsetb, 155\nsetbc, 155\nsetbcr, 155\nsetnbc, 155\nsetnbcr, 155\nslbfee., 1255\nslbia, 1251\nslbiag, 1252\nslbie, 1247\nslbieg, 1249\nslbmfee, 1255\nslbmfev, 1254\nslbmte, 1253\nslbsync, 1256\nsld., 141\nsld, 141\nslw., 139\nslw, 139\nsrad., 141\nsrad, 141\nsradi., 141\nsradi, 141\nsraw., 140\nsraw, 140\nsrawi., 140\nsrawi, 140\nsrd., 141\nsrd, 141\nsrw., 139\nsrw, 139\nstb, 85\nstbcix, 1191\nstbcx., 1105\nstbu, 85\nstbux, 85\nstbx, 85\nstd, 88\nstdat, 1101\nstdbrx, 95\nstdcix, 1191\nstdcx., 1108\nstdu, 88\nstdux, 89\nstdx, 88\nstfd, 183\nstfdp, 186\nstfdpx, 186\nstfdu, 183\nstfdux, 184\nstfdx, 183\nstfiwx, 184\nstfs, 181\nstfsu, 181\nstfsux, 182\nstfsx, 181\nsth, 86\nsthbrx, 93\nsthcix, 1191\nsthcx., 1106\nsthu, 86\nsthux, 86\nsthx, 86\nstmw, 96\nstop, 1181\nstq, 92\nstqcx., 894\nstswi, 99\nstswx, 99\nstvebx, 298\nstvehx, 299\nstvewx, 300\nstvx, 301\nstvxl, 301\nstw, 87\nstwat, 1101\nstwbrx, 94\nstwcix, 1191\nstwcx., 1107\nstwu, 87\nstwux, 87\nstwx, 87\nstxsd, 664\nstxsdx, 665\nstxsibx, 666\nstxsihx, 666\nstxsiwx, 667\nstxssp, 668\nstxsspx, 669\nstxv, 670\nstxvb16x, 671\nstxvd2x, 672\nstxvh8x, 673\nstxvl, 674\nstxvll, 676\nstxvp, 680\nstxvpx, 681\nstxvrbx, 677\nstxvrdx, 677\nstxvrhx, 678\nstxvrwx, 678\nstxvw4x, 679\nstxvx, 682\nsubf., 103\nsubf, 103\nsubfc., 104\nsubfc, 104\nsubfco., 104\nsubfco, 104\nsubfe., 104\nsubfe, 104\nsubfeo., 104\nsubfeo, 104\nsubfic, 103\nsubfme, 105\nsubfme., 105\nsubfmeo, 105\nsubfmeo., 105\nsubfo., 103\nsubfo, 103\nsubfze., 105\nsubfze, 105\nsubfzeo., 105\nsubfzeo, 105\nsync, 1112\ntd, 124\ntdi, 124\ntlbie, 1257\ntlbiel, 1262\ntlbsync, 1266\ntw, 123\ntwi, 123\nurfid, 1179\nvabsdub, 404\nvabsduh, 404\nvabsduw, 405\nvaddcuq, 356\nvaddcuw, 349\nvaddecuq, 356\nvaddeuqm, 355\nvaddfp, 448\nvaddsbs, 349\nvaddshs, 350\nvaddsws, 350\nvaddubm, 351\nvaddubs, 353\nvaddudm, 352 \nvadduhm, 351\nvadduhs, 353\nvadduqm, 355\nvadduwm, 352\nvadduws, 354\nvand, 428\nvandc, 428\nvavgsb, 401\nvavgsh, 402\nvavgsw, 403\nvavgub, 401\nvavguh, 402\nvavguw, 403\nvbpermd, 487\nvbpermq, 488\nvcfsx, 452\nvcfuged, 482\nvcfux, 452\nvcipher, 461\nvcipherlast, 461\nvclrlb, 502\nvclrrb, 502\nvclzb, 473\nvclzd, 475\nvclzdm, 475\nvclzh, 473\nvclzlsbb, 479 \nvclzw, 474\nvcmpbfp., 455\nvcmpbfp, 455\nvcmpeqfp., 456\nvcmpeqfp, 456\nvcmpequb., 414\nvcmpequb, 414\nvcmpequd, 417\nvcmpequd., 417\nvcmpequh., 415\nvcmpequh, 415\nvcmpequq., 418\nvcmpequq, 418\nvcmpequw., 416\nvcmpequw, 416\nvcmpgefp., 456\nvcmpgefp, 456\nvcmpgtfp., 457\nvcmpgtfp, 457\nvcmpgtsb., 419\nvcmpgtsb, 419\nvcmpgtsd, 422\nvcmpgtsd., 422\nvcmpgtsh., 420\nvcmpgtsh, 420\nvcmpgtsq., 423\nvcmpgtsq, 423\nvcmpgtsw., 421\nvcmpgtsw, 421\nvcmpgtub., 419\nvcmpgtub, 419\nvcmpgtud, 422\nvcmpgtud., 422\nvcmpgtuh., 420\nvcmpgtuh, 420\nvcmpgtuq., 423\nvcmpgtuq, 423\nvcmpgtuw., 421\nvcmpgtuw, 421\nvcmpneb, 424\nvcmpneb., 424\nvcmpneh, 425\nvcmpneh., 425\nvcmpnew, 426\nvcmpnew., 425\nvcmpnezb, 424\nvcmpnezb., 424\nvcmpnezh, 425\nvcmpnezh., 425\nvcmpnezw, 426\nvcmpnezw., 426\nvcmpsq, 427\nvcmpuq, 427\nvcntmbb, 495\nvcntmbd 496\nvcntmbh, 495\nvcntmbw, 496\nvctsxs, 451\nvctuxs, 451\nvctzb, 476\nvctzd, 478\nvctzdm, 478\nvctzh, 476\nvctzlsbb, 479\nvctzw, 477\nvdivesd, 387\nvdivesq, 389\nvdivesw, 385\nvdiveud, 387\nvdiveuq, 389\nvdiveuw, 385\nvdivsd, 386\nvdivsq, 388\nvdivsw, 384\nvdivud, 386\nvdivuq, 388\nvdivuw, 384\nveqv, 429\nvexpandbm, 492\nvexpanddm, 493\nvexpandhm, 492\nvexpandqm, 494\nvexpandwm, 493\nvexptefp, 458\nvextddvlx, 338\nvextddvrx, 338\nvextdubvlx, 335\nvextdubvrx, 335\nvextduhvlx, 336\nvextduhvrx, 336\nvextduwvlx, 337\nvextduwvrx, 337\nvextractbm, 497\nvextractd, 331\nvextractdm, 498\nvextracthm, 497\nvextractqm, 499\nvextractub, 330\nvextractuh, 330\nvextractuw, 331\nvextractwm, 498\nvextsb2d, 399\nvextsb2w, 398\nvextsd2q, 400\nvextsh2d, 399\nvextsh2w, 398\nvextsw2d, 400\nvextublx, 332\nvextubrx, 332\nvextuhlx, 333\nvextuhrx, 333\nvextuwlx, 334\nvextuwrx, 334\nvgbbd, 471\nvgnb, 472\nvinsblx, 341\nvinsbrx, 341\nvinsbvlx, 346\nvinsbvrx, 346\nvinsd, 345\nvinsdlx, 344\nvinsdrx, 344\nvinsertb, 339\nvinsertd, 340\nvinserth, 339\nvinsertw, 340\nvinshlx, 342\nvinshrx, 342\nvinshvlx, 347\nvinshvrx, 347\nvinsw, 345\nvinswlx, 343\nvinswrx, 343\nvinswvlx, 348\nvinswvrx, 348\nvlogefp, 459\nvmaddfp, 449\nvmaxfp, 450\nvmaxsb, 406\nvmaxsd, 409\nvmaxsh, 407 \nvmaxsw, 408 \nvmaxub, 406\nvmaxud, 409\nvmaxuh, 407\nvmaxuw, 408\nvmhaddshs, 377\nvmhraddshs, 377 \nvminfp, 450 \nvminsb, 410\nvminsd, 413\nvminsh, 411\nvminsw, 412\nvminub, 410 \nvminud, 413\nvminuh, 411\nvminuw, 412 \nvmladduhm, 378 \nvmodsd, 391\nvmodsq, 392\nvmodsw, 390\nvmodud, 391\nvmoduq, 392\nvmoduw, 390\nvmrgew, 318\nvmrghb, 315 \nvmrghh, 316\nvmrghw, 317 \nvmrglb, 315\nvmrglh, 316\nvmrglw, 317\nvmrgow, 318\nvmsumcud, 383\nvmsummbm, 379 \nvmsumshm, 379 \nvmsumshs, 380 \nvmsumubm, 378 \nvmsumudm, 382 \nvmsumuhm, 380 \nvmsumuhs, 381 \nvmul10cuq, 513\nvmul10ecuq, 514\nvmul10euq, 514\nvmul10uq, 513\nvmulesb, 365 \nvmulesd, 372\nvmulesh, 367 \nvmulesw, 369\nvmuleub, 366 \nvmuleud, 371\nvmuleuh, 368 \nvmuleuw, 370\nvmulhsd, 375\nvmulhsw, 373\nvmulhud, 375\nvmulhuw, 374\nvmulld, 376\nvmulosb, 365\nvmulosd, 372\nvmulosh, 367\nvmulosw, 369\nvmuloub, 366\nvmuloud, 371\nvmulouh, 368\nvmulouw, 370\nvmuluwm, 373\nvnand, 429\nvncipher, 462\nvncipherlast, 462\nvnegd, 397\nvnegw, 397\nvnmsubfp, 449 \nvnor, 429 \nvor, 429 \nvorc, 429\nvpdepd, 480\nvperm, 322 \nvpermr, 322\nvpermxor, 470\nvpextd, 481\nvpkpx, 304\nvpksdss, 307\nvpksdus, 307\nvpkshss, 305\nvpkshus, 305\nvpkswss, 306\nvpkswus, 306\nvpkudum, 310\nvpkudus, 310\nvpkuhum, 308\nvpkuhus, 308\nvpkuwum, 309\nvpkuwus, 309\nvpmsumb, 466\nvpmsumd, 469\nvpmsumh, 467\nvpmsumw, 468\nvpopcntb, 483\nvpopcntd, 484\nvpopcnth, 483\nvpopcntw, 484\nvprtybd, 485\nvprtybq, 486\nvprtybw, 485\nvrefp, 460\nvrfim, 453\nvrfin, 453\nvrfip, 454\nvrfiz, 454\nvrlb, 430\nvrld, 431\nvrldmi, 437\nvrldnm, 434\nvrlh, 430\nvrlq, 432\nvrlqmi, 438\nvrlqnm, 435\nvrlw, 431 \nvrlwmi, 436\nvrlwnm, 433\nvrsqrtefp, 460 \nvsbox, 463\nvsel, 323 \nvshasigmad, 464\nvshasigmaw, 465\nvsl, 326 \nvslb, 439 \nvsld, 440\nvsldbi, 324\nvsldoi, 324\nvslh, 439\nvslo, 327 \nvslq, 441\nvslv, 328\nvslw, 440\nvspltb, 319\nvsplth, 319\nvspltisb, 321\nvspltish, 321\nvspltisw, 321\nvspltw, 320\nvsr, 326\nvsrab, 445\nvsrad, 446\nvsrah, 445\nvsraq, 447\nvsraw, 446\nvsrb, 442\nvsrd, 443\nvsrdbi, 325\nvsrh, 443\nvsro, 327\nvsrq, 444\nvsrv, 328\nvsrw, 443\nvstribl., 500\nvstribl, 500\nvstribr., 500\nvstribr, 500\nvstrihl., 501\nvstrihl, 501\nvstrihr., 501\nvstrihr, 501\nvsubcuq, 364\nvsubcuw, 357\nvsubecuq, 364\nvsubeuqm, 363\nvsubfp, 448\nvsubsbs, 357\nvsubshs, 358\nvsubsws, 358\nvsububm, 359\nvsububs, 361\nvsubudm, 360\nvsubuhm, 359\nvsubuhs, 361\nvsubuqm, 363\nvsubuwm, 360\nvsubuws, 362\nvsum2sws, 394\nvsum4sbs, 395\nvsum4shs, 395\nvsum4ubs, 396\nvsumsws, 393\nvupkhpx, 314\nvupkhsb, 311\nvupkhsh, 312\nvupkhsw, 313\nvupklpx, 314\nvupklsb, 311\nvupklsh, 312\nvupklsw, 313\nvxor, 429\nwait, 1116\nxor., 126\nxor, 126\nxori, 126\nxoris, 126\nxsabsdp, 684\nxsabsqp, 684\nxsadddp, 685\nxsaddqp, 692\nxsaddqpo, 692\nxsaddsp, 690\nxscmpeqdp, 696\nxscmpeqqp, 697\nxscmpexpdp, 694\nxscmpexpqp, 695\nxscmpgedp, 698\nxscmpgeqp, 699\nxscmpgtdp, 700\nxscmpgtqp, 701\nxscmpodp, 702\nxscmpoqp, 704\nxscmpudp, 705\nxscmpuqp, 707\nxscpsgndp, 708\nxscpsgnqp, 708\nxscvdphp, 709\nxscvdpqp, 710\nxscvdpsp, 711\nxscvdpspn, 712\nxscvdpsxds, 713\nxscvdpsxws, 715\nxscvdpuxds, 717\nxscvdpuxws, 719\nxscvhpdp, 721\nxscvqpdp, 722\nxscvqpdpo, 722\nxscvqpsdz, 723\nxscvqpsqz, 725\nxscvqpswz, 727\nxscvqpudz, 729\nxscvqpuqz, 731\nxscvqpuwz, 733\nxscvsdqp, 740\nxscvspdp, 735\nxscvspdpn, 736\nxscvsqqp, 737\nxscvsxddp, 738\nxscvsxdsp, 739\nxscvudqp, 740\nxscvuqqp, 741\nxscvuxddp, 741\nxscvuxdsp, 742\nxsdivdp, 743\nxsdivqp, 745\nxsdivqpo, 745\nxsdivsp, 747\nxsiexpdp, 749\nxsiexpqp, 750\nxsmaddadp, 751\nxsmaddasp, 754\nxsmaddmdp, 751\nxsmaddmsp, 754\nxsmaddqp, 757\nxsmaddqpo, 757\nxsmaxcdp, 762\nxsmaxcqp, 764\nxsmaxdp, 760\nxsmaxjdp, 765\nxsmincdp, 769\nxsmincqp, 771\nxsmindp, 767\nxsminjdp, 772\nxsmsubadp, 774\nxsmsubasp, 777\nxsmsubmdp, 774\nxsmsubmsp, 777\nxsmsubqp, 780\nxsmsubqpo, 780\nxsmuldp, 783\nxsmulqp, 785\nxsmulqpo, 785\nxsmulsp, 878\nxsnabsdp, 789\nxsnabsqp, 789\nxsnegdp, 790\nxsnegqp, 790\nxsnmaddadp, 791\nxsnmaddasp, 796\nxsnmaddmdp, 791\nxsnmaddmsp, 796\nxsnmaddqp, 799\nxsnmaddqpo, 799\nxsnmsubadp, 802\nxsnmsubasp, 805\nxsnmsubmdp, 802\nxsnmsubmsp, 805\nxsnmsubqp, 808\nxsnmsubqpo, 808\nxsrdpi, 811\nxsrdpic, 812\nxsrdpim, 813\nxsrdpip, 814\nxsrdpiz, 815\nxsredp, 816\nxsresp, 817\nxsrqpi, 819\nxsrqpix, 819\nxsrqpxp, 821\nxsrsp, 823\nxsrsqrtedp, 824\nxsrsqrtesp, 825\nxssqrtdp, 827\nxssqrtqp, 829\nxssqrtqpo, 829\nxssqrtsp, 831\nxssubdp, 833\nxssubqp, 835\nxssubqpo, 835\nxssubsp, 837\nxstdivdp, 839\nxstsqrtdp, 840\nxststdcdp, 841\nxststdcqp, 842\nxststdcsp, 843\nxsxexpdp, 844\nxsxexpqp, 844\nxsxsigdp, 845\nxsxsigqp, 845\nxvabsdp, 846\nxvabssp, 846\nxvaddd, 847\nxvaddsp, 851\nxvbf16ger2, 853\nxvbf16ger2nn, 853\nxvbf16ger2np, 853\nxvbf16ger2pn, 853\nxvbf16ger2pp, 853\nxvcmpeqdp, 858\nxvcmpeqdp., 858\nxvcmpeqsp, 859\nxvcmpeqsp., 859\nxvcmpgedp, 860\nxvcmpgedp., 860\nxvcmpgesp, 861\nxvcmpgesp., 861\nxvcmpgtdp, 862\nxvcmpgtdp., 862\nxvcmpgtsp, 863\nxvcmpgtsp., 863\nxvcpsgndp, 864\nxvcpsgnsp, 864\nxvcvbf16sp, 865\nxvcvdpsp, 866\nxvcvdpsxds, 867\nxvcvdpsxws, 869\nxvcvdpuxds, 871\nxvcvdpuxws, 873\nxvcvhpsp, 875\nxvcvspbf16, 876\nxvcvspdp, 877\nxvcvsphp, 878\nxvcvspsxds, 879\nxvcvspsxws, 881\nxvcvspuxds, 883\nxvcvspuxws, 885\nxvcvsxddp, 887\nxvcvsxdsp, 888\nxvcvsxwdp, 889\nxvcvsxwsp, 889\nxvcvuxddp, 890\nxvcvuxdsp, 891\nxvcvuxwdp, 892\nxvcvuxwsp, 892\nxvdivdp, 893\nxvdivsp, 895\nxvf16ger2, 897\nxvf16ger2nn, 897\nxvf16ger2np, 897\nxvf16ger2pn, 897\nxvf16ger2pp, 897\nxvf32ger, 901\nxvf32gernn, 901\nxvf32gernp, 901\nxvf32gerpn, 901\nxvf32gerpp, 901\nxvf64ger, 905\nxvf64gernn, 905\nxvf64gernp, 905\nxvf64gerpn, 905\nxvf64gerpp, 905\nxvi16ger2, 917\nxvi16ger2pp, 917\nxvi16ger2s, 919\nxvi16ger2spp, 919\nxvi4ger8, 909\nxvi4ger8pp, 909\nxvi8ger4, 912\nxvi8ger4pp, 912\nxvi8ger4spp, 915\nxviexpdp, 922\nxviexpsp, 922\nxvmaddadp, 923\nxvmaddasp, 926\nxvmaddmdp, 923\nxvmaddmsp, 926\nxvmaxdp, 929\nxvmaxsp, 931\nxvmindp, 933\nxvminsp, 935\nxvmsubadp, 937\nxvmsubasp, 940\nxvmsubmdp, 937\nxvmsubmsp, 940\nxvmuldp, 943\nxvmulsp, 945\nxvnabsdp, 947\nxvnabssp, 947\nxvnegdp, 948\nxvnegsp, 948\nxvnmaddadp, 949\nxvnmaddasp, 953\nxvnmaddmdp, 949\nxvnmaddmsp, 953\nxvnmsubadp, 956\nxvnmsubasp, 959\nxvnmsubmdp, 956\nxvnmsubmsp, 959\nxvrdpi, 962\nxvrdpic, 963\nxvrdpim, 964\nxvrdpip, 965\nxvrdpiz, 965\nxvredp, 966\nxvresp, 967\nxvrspi, 968\nxvrspic, 969\nxvrspim, 970\nxvrspip, 971\nxvrspiz, 971\nxvrsqrtedp, 972\nxvrsqrtesp, 973\nxvsqrtdp, 974\nxvsqrtsp, 975\nxvsubdp, 976\nxvsubsp, 978\nxvtdivdp, 980\nxvtdivsp, 981\nxvtlsbb, 985\nxvtsqrtdp, 982\nxvtsqrtsp, 982\nxvtstdcdp, 983\nxvtstdcsp, 984\nxvxexpdp, 986\nxvxexpsp, 986\nxvxsigdp, 987\nxvxsigsp, 987\nxxblendvb, 988\nxxblendvd, 989\nxxblendvh, 988\nxxblendvw, 989\nxxbrd, 990\nxxbrh, 991\nxxbrq, 992\nxxbrw, 993\nxxeval, 993\nxxextractuw, 995\nxxgenpcvbm, 996\nxxgenpcvdm, 1002\nxxgenpcvhm, 998\nxxgenpcvwm, 1000\nxxinsertw, 995\nxxland, 1004\nxxlandc, 1004\nxxleqv, 1005\nxxlnand, 1005\nxxlnor, 1006\nxxlor, 1007\nxxlorc, 1006\nxxlxor, 1007\nxxmfacc, 1009\nxxmrghw, 1008\nxxmrglw, 1008\nxxmtacc, 1009\nxxperm, 1011\nxxpermdi, 1012\nxxpermr, 1011\nxxpermx, 1013\nxxsel, 1014\nxxsetaccz, 1015\nxxsldwi, 1016\nxxsplti32dx, 1018\nxxspltib, 1017\nxxspltidp, 1017\nxxspltiw, 1018\nxxspltw, 1019\n\n@PowerISA_V3.0.pdf [Power ISA Version 3.0 Novomber 30, 2015]\nldmx,72 \nxscmpnedp, 546\nxvcmpnedp, 691 \nxvcmpnedp., 691\nxvcmpnesp, 692\nxvcmpnesp., 692\n\n@PowerISA_V2.07B.pdf [Power ISA Version 2.07 B April 9, 2015]\nbrinc, 625\ndcba, 801\ndcbfep, 1095\ndcbi, 1149\ndcblc, 1154\ndcbstep, 1094\ndcbtep, 1094\ndcbtls, 1153\ndcbtstep, 1097\ndcbtstls, 1153\ndcbzep, 1098\ndci, 1270\ndcread, 1273\ndlmzb., 704\ndlmzb, 704\ndnh, 1259 \ndoze, 898\ndsn, 855\neciwx, 857\necowx, 857\nefdabs, 691\nefdadd, 692\nefdcfs, 697\nefdcfsf, 695\nefdcfsi, 694\nefdcfsid, 695\nefdcfuf, 695\nefdcfui, 694\nefdcfuid, 695\nefdcmpeq, 693\nefdcmpgt, 693\nefdcmplt, 693\nefdctsf, 697\nefdctsi, 695\nefdctsidz, 696\nefdctsiz, 697\nefdctuf, 697\nefdctui, 695\nefdctuidz, 696\nefdctuiz, 697\nefddiv, 692\nefdmul, 692\nefdnabs, 691\nefdneg, 691\nefdsub, 692\nefdtsteq, 694\nefdtstgt, 693\nefdtstlt, 694\nefsabs, 684\nefsadd, 685\nefscfd, 698\nefscfsf, 689\nefscfsi, 689\nefscfuf, 689\nefscfui, 689\nefscmpeq, 687\nefscmpgt, 686\nefscmplt, 686\nefsctsf, 690\nefsctsi, 689\nefsctsiz, 690\nefsctuf, 690\nefsctui, 689\nefsctuiz, 690\nefsdiv, 685\nefsmul, 685\nefsnabs, 684\nefsneg, 684\nefssub, 685\nefststeq, 688\nefststgt, 687\nefststlt, 688\nehpriv, 1074\nevabs, 625\nevaddiw, 625\nevaddsmiaaw, 625\nevaddssiaaw, 626\nevaddumiaaw, 626\nevaddusiaaw, 626\nevaddw, 626\nevand, 627\nevandc, 627\nevcmpeq, 627\nevcmpgts, 627\nevcmpgtu, 628\nevcmplts, 628\nevcmpltu, 628\nevcntlsw, 629\nevcntlzw, 629\nevdivws, 629\nevdivwu, 630\neveqv, 630\nevextsb, 630\nevextsh, 630\nevfsabs, 676\nevfsadd, 677\nevfscfsf, 681\nevfscfsi, 681\nevfscfuf, 681\nevfscfui, 681\nevfscmpeq, 679\nevfscmpgt, 678\nevfscmplt, 678\nevfsctsf, 683\nevfsctsi, 682\nevfsctsiz, 682\nevfsctuf, 683\nevfsctui, 682\nevfsctuiz, 682\nevfsdiv, 677\nevfsmul, 677\nevfsnabs, 676\nevfsneg, 676\nevfssub, 677\nevfststeq, 680\nevfststgt, 679\nevfststlt, 680\nevldd, 631\nevlddepx, 1100\nevlddx, 631\nevldh, 631\nevldhx, 631\nevldw, 632\nevldwx, 632\nevlhhesplat, 632\nevlhhesplatx, 632\nevlhhossplat, 633\nevlhhossplatx, 633\nevlhhousplat, 633\nevlhhousplatx, 633\nevlwhe, 634\nevlwhex, 634\nevlwhos, 634\nevlwhosx, 634\nevlwhou, 635\nevlwhoux, 635\nevlwhsplat, 635\nevlwhsplatx, 635\nevlwwsplat, 636\nevlwwsplatx, 636\nevmergehi, 636\nevmergehilo, 637\nevmergelo, 636\nevmergelohi, 637\nevmhegsmfaa, 637\nevmhegsmfan, 637\nevmhegsmiaa, 638\nevmhegsmian, 638\nevmhegumiaa, 638\nevmhegumian, 638\nevmhesmf, 639\nevmhesmfa, 639\nevmhesmfaaw, 639\nevmhesmfanw, 639\nevmhesmi, 640\nevmhesmia, 640\nevmhesmiaaw, 640\nevmhesmianw, 640\nevmhessf, 641\nevmhessfa, 641\nevmhessfaaw, 642\nevmhessfanw, 642\nevmhessiaaw, 643\nevmhessianw, 643\nevmheumi, 644\nevmheumia, 644\nevmheumiaaw, 644\nevmheumianw, 644\nevmheusiaaw, 645\nevmheusianw, 645\nevmhogsmfaa, 646\nevmhogsmfan, 646\nevmhogsmiaa, 646\nevmhogsmian, 646\nevmhogumiaa, 647\nevmhogumian, 647\nevmhosmf, 647\nevmhosmfa, 647\nevmhosmfaaw, 648\nevmhosmfanw, 648\nevmhosmi, 648\nevmhosmia, 648\nevmhosmiaaw, 649\nevmhosmianw, 649\nevmhossf, 650\nevmhossfa, 650\nevmhossfaaw, 651\nevmhossfanw, 651\nevmhossiaaw, 652\nevmhossianw, 652\nevmhoumi, 652\nevmhoumia, 652\nevmhoumiaaw, 653\nevmhoumianw, 653\nevmhousiaaw, 653\nevmhousianw, 653\nevmra, 654\nevmwhsmf, 654\nevmwhsmfa, 654\nevmwhsmi, 654\nevmwhsmia, 654\nevmwhssf, 655\nevmwhssfa, 655\nevmwhumi, 655\nevmwhumia, 655\nevmwlsmiaaw, 656\nevmwlsmianw, 656\nevmwlssiaaw, 656\nevmwlssianw, 656\nevmwlumi, 657\nevmwlumia, 657\nevmwlumiaaw, 657\nevmwlumianw, 657\nevmwlusiaaw, 658\nevmwlusianw, 658\nevmwsmf, 658\nevmwsmfa, 658\nevmwsmfaa, 659\nevmwsmfan, 659\nevmwsmi, 659\nevmwsmia, 659\nevmwsmiaa, 659\nevmwsmian, 659\nevmwssf, 660\nevmwssfa, 660\nevmwssfaa, 661\nevmwssfan, 661\nevmwumi, 661\nevmwumia, 661\nevmwumiaa, 662\nevmwumian, 662\nevnand, 662\nevneg, 662\nevnor, 663\nevor, 663\nevorc, 663\nevrlw, 663\nevrlwi, 664\nevrndw, 664\nevsel, 664\nevslw, 665\nevslwi, 665\nevsplatfi, 665\nevsplati, 665\nevsrwis, 665\nevsrwiu, 665\nevsrws, 666\nevsrwu, 666\nevstdd, 666\nevstddepx, 1100\nevstddx, 666\nevstdh, 667\nevstdhx, 667\nevstdw, 667\nevstdwx, 667\nevstwhe, 668\nevstwhex, 668\nevstwho, 668\nevstwhox, 668\nevstwwe, 668\nevstwwex, 668\nevstwwo, 669\nevstwwox, 669\nevsubfsmiaaw, 669\nevsubfssiaaw, 669\nevsubfumiaaw, 670\nevsubfusiaaw, 670\nevsubfw, 670\nevsubifw, 670\nevxor, 670\nicbiep, 1098\nicblc, 1154\nicbtls, 1154\nici, 1270\nicread, 1274\nlbdx, 853\nlbepx, 1090\nlddx, 853\nldepx, 1091\nlfddx, 853\nlfdepx, 1099\nlhdx, 853\nlhepx, 1090\nlvepx, 1101\nlvepxl, 1101\nlwdx, 853\nlwepx, 1091\nmacchwo., 706\nmacchwo, 706\nmacchw., 706\nmacchw, 706\nmacchwso., 706\nmacchwso, 706\nmacchws., 706\nmacchws, 706\nmacchwsuo., 707\nmacchwsuo, 707\nmacchwsu., 707\nmacchwsu, 707\nmacchwuo., 707\nmacchwuo, 707\nmacchwu., 707\nmacchwu, 707\nmachhwo., 708\nmachhwo, 708\nmachhw., 708\nmachhw, 708\nmachhwso., 708\nmachhwso, 708\nmachhws., 708\nmachhws, 708\nmachhwsuo., 709\nmachhwsuo, 709\nmachhwsu., 709\nmachhwsu, 709\nmachhwuo., 709\nmachhwuo, 709\nmachhwu., 709\nmachhwu, 709\nmaclhwo., 710\nmaclhwo, 710\nmaclhw., 710\nmaclhw, 710\nmaclhwso., 710\nmaclhwso, 710\nmaclhws., 710\nmaclhws, 710\nmaclhwsuo., 711\nmaclhwsuo, 711\nmaclhwsu., 711\nmaclhwsu, 711\nmaclhwuo., 711\nmaclhwuo, 711\nmaclhwu., 711\nmaclhwu, 711\nmbar, 821\nmcrxr, 143\nmfpmr, 1288\nmfsr, 958\nmfsrin, 958\nmtdcr, 1085\nmtdcrux, 143\nmtdcrx, 1085\nmtpmr, 1288\nmtsr, 957\nmtsrin, 957 \nmulchw., 711\nmulchw, 711\nmulchwu., 711\nmulchwu, 711\nmulhhw., 712\nmulhhw, 712\nmulhhwu., 712\nmulhhwu, 712\nmullhw., 712\nmullhw, 712\nmullhwu., 712\nmullhwu, 712\nnap, 898\nnmacchwo., 713\nnmacchwo, 713\nnmacchw., 713\nnmacchw, 713\nnmacchwso., 713\nnmacchwso, 713\nnmacchws., 713\nnmacchws, 713\nnmachhwo., 714\nnmachhwo, 714\nnmachhw., 714\nnmachhw, 714\nnmachhwso., 714\nnmachhwso, 714\nnmachhws., 714\nnmachhws, 714\nnmaclhwo., 715\nnmaclhwo, 715\nnmaclhw., 715\nnmaclhw, 715\nnmaclhwso., 715\nnmaclhwso, 715\nnmaclhws., 715\nnmaclhws, 715\nrfci, 1072\nrfdi, 1073\nrfgi, 1074\nrfi, 1072\nrfmci, 1073\nrvwinkle, 899\nsleep, 899\nstbdx, 854\nstbepx, 1092\nstddx, 854\nstdepx, 1093\nstfddx, 854\nstfdepx, 1099\nsthdx, 854\nsthepx, 1092\nstvepx, 1102\nstvepxl, 1102\nstwdx, 854\nstwepx, 1093\nsubfic, 100\nsubfme., 101\nsubfme, 101\nsubfmeo., 101\nsubfmeo, 101\ntabort., 839\ntabortdc., 841\ntabortdci., 841\ntabortwc., 840\ntabortwci., 840\ntbegin., 837\ntcheck, 842\ntend., 838\ntlbia, 963\ntlbilx, 1165\ntlbivax, 1163\ntlbre, 1170\ntlbsrx., 1138\ntlbsx, 1136\ntlbwe, 1141\ntrechkpt., 911\ntreclaim., 910\ntsr., 841\nwrtee, 1056\nwrteei, 1057\ne_b, 1307\ne_bl, 1307\nse_b, 1307 \t\nse_bl, 1307 \ne_bc, 1307\ne_bcl, 1307\nse_bc, 1307\nse_bctr, 1308\t\t\t\nse_bctrl, 1308\t\t\t\nse_blr, 1308\t\t\t\nse_blrl, 1308\t\t\t\nse_sc, 1309\t\t\t\t\ne_sc, 1309\t\t\t\nse_illegal, 1310\t\t\nse_rfmci, 1310\t\t\t\nse_rfci, 1311\t\nse_rfi, 1311\t\t\nse_rfdi, 1312\t\t\nse_rfgi, 1312\ne_crand, 1313\ne_crandc, 1313\ne_creqv, 1313\ne_crnand, 1313\ne_crnor, 1314\ne_cror, 1314\ne_crorc, 1314\ne_crxor, 1314\ne_mcrf, 1314\ne_lbz, 1317\nse_lbz, 1317\ne_lbzu, 1317\ne_lha, 1317\ne_lhz, 1317\nse_lhz, 1317\ne_lhau, 1318\ne_lhzu, 1318\ne_lwz, 1318\nse_lwz, 1318\ne_lwzu, 1319\ne_stb, 1320\nse_stb, 1320\ne_stbu, 1321\t\ne_sth, 1321\nse_sth, 1321\ne_sthu, 1321 \ne_stw, 1322\nse_stw, 1322\ne_stwu, 1322\ne_lmw, 1323\ne_stmw, 1323\nse_add, 1325\ne_add16i, 1325\ne_add2i., 1325\ne_add2is, 1325\ne_addi, 1325\ne_addi., 1325\nse_addi, 1325\ne_addic, 1326\ne_addic., 1326\nse_sub, 1326\nse_subf, 1326\ne_subfic, 1326\ne_subfic., 1326\nse_subi, 1326\nse_subi., 1326\ne_mulli, 1327\ne_mull2i., 1327\nse_mullw, 1327\nse_neg, 1327\nse_btsti, 1328\ne_cmp16i., 1328\ne_cmpi, 1329\nse_cmp, 1329\nse_cmpi, 1329\ne_cmpl16i., 1329\ne_cmpli, 1330\nse_cmpl, 1330\nse_cmpli, 1330\ne_cmph, 1330\nse_cmph, 1331\ne_cmph16i., 1331\ne_cmphl, 1331\nse_cmphl, 1331 \ne_cmphl16i., 1332\ne_and2i., 1333\ne_and2is., 1333\ne_andi, 1333\ne_andi., 1333\nse_andi, 1333\ne_or2i, 1334\ne_or2is, 1334\ne_ori, 1334\ne_ori., 1334\ne_xori, 1334\ne_xori., 1334\nse_and, 1334\nse_and., 1334\nse_andc, 1334\nse_or, 1335\nse_not, 1335\nse_bclri, 1335\nse_bgeni, 1335\nse_bmaski, 1335\nse_bseti, 1335\nse_extsb, 1336\nse_extsh, 1336\nse_extzb, 1336\nse_extzh, 1336\ne_li, 1336\nse_li, 1336\ne_lis, 1336\nse_mfar, 1337\nse_mr, 1337\nse_mtar, 1337\ne_rlw, 1338\ne_rlw., 1338\ne_rlwi, 1338\ne_rlwi., 1338\ne_rlwimi, 1338\ne_rlwinm, 1338\ne_slwi, 1339\ne_slwi., 1339\nse_slwi, 1339\nse_slw, 1339\nse_srawi, 1339\nse_sraw, 1340\ne_srwi, 1340\ne_srwi., 1340\nse_srwi, 1340\nse_srw, 1340\nse_mfctr, 1341\nse_mtctr, 1341\nse_mflr, 1341\nse_mtlr, 1341\nse_isync, 1342\n\n@PowerISA_V2.06_PUBLIC.pdf [Power ISA Version 2.06 January 30, 2009]\nlxsdux, 366\nlxvd2ux, 366\nlxvw4ux, 367\nstxsdux, 368\nstxvd2ux, 368\nstxvw4ux, 369" }, { "path": "pypcode/processors/PowerPC/data/manuals/PowerPC.idx", "content": "@powerpc.pdf[PowerPC� Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors, Version 2.3, March 31, 2005]\nadd\t, 353\nadd.\t, 353\naddo\t, 353\naddo.\t, 353\naddc\t, 355\naddc.\t, 355\naddco\t, 355\naddco.\t, 355\nadde\t, 356\nadde.\t, 356\naddeo\t, 356\naddeo.\t, 356\naddi\t, 357\naddic\t, 358\naddic.\t, 358\naddis\t, 360\naddme\t, 361\naddme.\t, 361\naddmeo\t, 361\naddmeo.\t, 361\naddze\t, 362\naddze.\t, 362\naddzeo\t, 362\naddzeo.\t, 362\nand\t, 363\nand.\t, 363\nandc\t, 364\nandc.\t, 364\nandi.\t, 365\nandis.\t, 366\nb\t, 367\nba\t, 367\nbl\t, 367\nble, 367\nbla\t, 367\nbc\t, 368\nbca\t, 368\nbcl\t, 368\nbcla\t, 368\nbcctr\t, 369\nbcctrl\t, 369\nbclr\t, 370\nbclrl\t, 370\nbdnzlr , 370\nbltctr , 369\nbltlr , 370\nbnectr , 369\nbnelr , 370\nclrldi , 534\nclrlsldi , 533\nclrlslwi , 538\nclrlwi , 538\nclrrdi , 535\nclrrwi , 538\ncmp\t, 371\ncmpd , 371\ncmpdi , 372\ncmpi\t, 372\ncmpl\t, 373\ncmpld , 373\ncmpldi , 374\ncmpli\t, 374\ncmplw , 373\ncmplwi , 374\ncmpw , 371\ncmpwi , 372\ncntlzd , 375\ncntlzd. , 375\ncntlzw\t, 376\ncntlzw.\t, 376\ncrand\t, 377\ncrandc\t, 378\ncrclr , 384\ncreqv\t, 379\ncrmove , 382\ncrnand\t, 380\ncrnor\t, 381\ncrnot , 381\ncror\t, 382\ncrorc\t, 383\ncrset , 379\ncrxor\t, 384\ndcba\t, 721\ndcbf\t, 385\ndcbi\t, 386\ndcbst\t, 387\ndcbt\t, 388\ndcbtst\t, 390\ndcbz\t, 391\ndivd , 393\ndivd. , 393\ndivdo , 393\ndivdo. , 393\ndivdu , 394\ndivdu. , 394\ndivduo , 394\ndivduo. , 394\ndivw\t, 395\ndivw.\t, 395\ndivwo\t, 395\ndivwo.\t, 395\ndivwu\t, 396\ndivwu.\t, 396\ndivwuo\t, 396\ndivwuo.\t, 396\neciwx\t, 397\necowx\t, 398\neieio\t, 399\neqv\t, 401\neqv.\t, 401\nextldi , 535\nextlwi , 538\nextrdi , 534\nextrwi , 538\nextsb\t, 402\nextsb.\t, 402\nextsh\t, 403\nextsh.\t, 403\nextsw , 404\nextsw. , 404\nfabs\t, 405\nfabs.\t, 405\nfadd\t, 406\nfadd.\t, 406\nfadds\t, 407\nfadds.\t, 407\nfcfid , 408\nfcfid. , 408\nfcmpo\t, 409\nfcmpu\t, 410\nfctid , 411\nfctid. , 411\nfctidz , 412\nfctidz. , 412\nfctiw\t, 413\nfctiw.\t, 413\nfctiwz\t, 414\nfctiwz.\t, 414\nfdiv\t, 415\nfdiv.\t, 415\nfdivs\t, 416\nfdivs.\t, 416\nfmadd\t, 417\nfmadd.\t, 417\nfmadds\t, 418\nfmadds.\t, 418\nfmr\t, 419\nfmr.\t, 419\nfmsub\t, 420\nfmsub.\t, 420\nfmsubs\t, 421\nfmsubs.\t, 421\nfmul\t, 422\nfmul.\t, 422\nfmuls\t, 423\nfmuls.\t, 423\nfnabs\t, 424\nfnabs.\t, 424\nfneg\t, 425\nfneg.\t, 425\nfnmadd\t, 426\nfnmadd.\t, 426\nfnmadds\t, 427\nfnmadds., 427\nfnmsub\t, 428\nfnmsub.\t, 428\nfnmsubs\t, 429\nfnmsubs., 429\nfres\t, 430\nfres.\t, 430\nfrsp\t, 432\nfrsp.\t, 432\nfrsqrte\t, 433\nfrsqrte., 433\nfsel\t, 435\nfsel.\t, 435\nfsqrt\t, 436\nfsqrt.\t, 436\nfsqrts\t, 437\nfsqrts.\t, 437\nfsub\t, 438\nfsub.\t, 438\nfsubs\t, 439\nfsubs.\t, 439\nicbi\t, 440\ninslwi , 537\ninsrdi , 536\ninsrwi , 537\nisync\t, 441\nla , 357\nlbz\t, 442\nlbzu\t, 443\nlbzux\t, 444\nlbzx\t, 445\nld , 446\nldarx , 447\nldu , 448\nldux , 449\nldx , 450\nlfd\t, 451\nlfdu\t, 452\nlfdux\t, 453\nlfdx\t, 454\nlfs\t, 455\nlfsu\t, 456\nlfsux\t, 457\nlfsx\t, 458\nlha\t, 459\nlhau\t, 460\nlhaux\t, 461\nlhax\t, 462\nlhbrx\t, 463\nlhz\t, 464\nlhzu\t, 465\nlhzux\t, 466\nlhzx\t, 467\nli , 357\nlis, 360\nlmw\t, 468\nlswi\t, 469\nlswx\t, 471\nlwa , 763\nlwarx\t, 474\nlwaux , 475\nlwax , 476\nlwbrx\t, 477\nlwz\t, 478\nlwzu\t, 479\nlwzux\t, 480\nlwzx\t, 481\nmcrf\t, 482\nmcrfs\t, 483\nmcrxr\t, 484\nmfcr\t, 485\nmfctr , 489\nmffs\t, 487\nmffs.\t, 487\nmflr , 489\nmfmsr\t, 488\nmfocrf , 486\nmfspr\t, 489\nmfsr\t, 492\nmfsrin\t, 494\nmftb\t, 496\nmftbu , 497\nmfxer , 489\nmr , 525\nmtcr , 498\nmtcrf\t, 498\nmtctr , 507\nmtfsb0\t, 499\nmtfsb0.\t, 499\nmtfsb1\t, 500\nmtfsb1.\t, 500\nmtfsf\t, 501\nmtfsf.\t, 501\nmtfsfi\t, 502\nmtfsfi.\t, 502\nmtlr , 507\nmtmsr\t, 503\nmtmsrd , 505\nmtocrf , 506\nmtspr\t, 507\nmtsr\t, 511\nmtsrd , 512\nmtsrdin , 513\nmtsrin\t, 514\nmtxer , 507\nmulhd , 515\nmulhd. , 515\nmulhdu , 516\nmulhdu. , 516\nmulhw\t, 517\nmulhw.\t, 517\nmulhwu\t, 518\nmulhwu.\t, 518\nmulld , 519\nmulld. , 519\nmulldo , 519\nmulldo. , 519\nmulli\t, 520\nmullw\t, 521\nmullw.\t, 521\nmullwo\t, 521\nmullwo.\t, 521\nnand\t, 522\nnand.\t, 522\nneg\t, 523\nneg.\t, 523\nnego\t, 523\nnego.\t, 523\nnop , 527\nnor\t, 524\nnor.\t, 524\nnot , 524\nor\t, 525\nor.\t, 525\norc\t, 526\norc.\t, 526\nori\t, 527\noris\t, 528\nrfi\t, 529\nrfid , 530\nrldcl , 531\nrldcl. , 531\nrldcr , 532\nrldcr. , 532\nrldic , 533\nrldic. , 533\nrldicl , 534\nrldicl. , 534\nrldicr , 535\nrldicr. , 535\nrldimi , 536\nrldimi. , 536\nrlwimi\t, 537\nrlwimi.\t, 537\nrlwinm\t, 538\nrlwinm.\t, 538\nrlwnm\t, 540\nrlwnm.\t, 540\nrotld , 531\nrotldi , 534\nrotlw , 540\nrotlwi , 538\nrotrdi , 534\nrotrwi , 538\nsc\t, 541\nslbia , 542\nslbie , 543\nslbmfee , 544\nslbmfev , 545\nslbmte , 546\nsld , 547\nsld. , 547\nsldi , 535\nslw\t, 548\nslw.\t, 548\nslwi , 538\nsrad , 549\nsrad. , 549\nsradi , 550\nsradi. , 550\nsraw\t, 551\nsraw.\t, 551\nsrawi\t, 552\nsrawi.\t, 552\nsrd , 553\nsrd. , 553\nsrdi , 534\nsrw\t, 554\nsrw.\t, 554\nsrwi , 538\nstb\t, 555\nstbu\t, 556\nstbux\t, 557\nstbx\t, 558\nstd , 559\nstdcx. , 560\nstdu , 562\nstdux , 563\nstdx , 564\nstfd\t, 565\nstfdu\t, 566\nstfdux\t, 567\nstfdx\t, 568\nstfiwx\t, 569\nstfs\t, 570\nstfsu\t, 571\nstfsux\t, 572\nstfsx\t, 573\nsth\t, 574\nsthbrx\t, 575\nsthu\t, 576\nsthux\t, 577\nsthx\t, 578\nstmw\t, 579\nstswi\t, 580\nstswx\t, 581\nstw\t, 582\nstwbrx\t, 583\nstwcx.\t, 584\nstwu\t, 586\nstwux\t, 587\nstwx\t, 588\nsub , 589\nsubc , 590\nsubf\t, 589\nsubf.\t, 589\nsubfo\t, 589\nsubfo.\t, 589\nsubfc\t, 590\nsubfc.\t, 590\nsubfco\t, 590\nsubfco.\t, 590\nsubfe\t, 591\nsubfe.\t, 591\nsubfeo\t, 591\nsubfeo.\t, 591\nsubfic\t, 592\nsubfme\t, 593\nsubfme.\t, 593\nsubfmeo\t, 593\nsubfmeo., 593\nsubfze\t, 594\nsubfze.\t, 594\nsubfzeo\t, 594\nsubfzeo., 594\nsubi , 357\nsubic , 358\nsubic. , 359\nsubis , 360\nsync\t, 595\ntd , 597\ntdge , 597\ntdi , 598\ntdlnl , 597\ntdlti , 598\ntdnei , 598\ntlbia\t, 599\ntlbie\t, 600\ntlbiel , 601\ntlbsync\t, 603\ntrap , 604\ntw\t, 604\ntweq , 604\ntwgti , 605\ntwi\t, 605\ntwlge , 604\ntwllei , 605\nxor\t, 606\nxor.\t, 606\nxori\t, 607\nxoris\t, 608\n\n\n@altivecpem.pdf [AltiVec Technology Programming Environments Manual, Rev.0.1 11/1998 (ALTIVECPEM/D)]\n\n\ndss\t\t\t, 131\ndssall\t\t, 131\ndst\t\t\t, 132\ndstt\t\t, 132\ndstst\t\t, 134\ndststt\t\t, 134\nlvebx\t\t, 136\nlvehx\t\t, 138\nlvewx\t\t, 139\nlvsl\t\t, 140\nlvsr\t\t, 142\nlvx\t\t\t, 144\nlvxl\t\t, 145\nmfvscr\t\t, 146\nmtvscr\t\t, 147\nstvebx\t\t, 148\nstvehx\t\t, 149\nstvewx\t\t, 150\nstvx\t\t, 151\nstvxl\t\t, 152\nvaddcuw\t\t, 153\nvaddfp\t\t, 154\nvaddsbs\t\t, 155\nvaddshs\t\t, 156\nvaddsws\t\t, 157\nvaddubm\t\t, 158\nvaddubs\t\t, 159\nvadduhm\t\t, 160\nvadduhs\t\t, 161\nvadduwm\t\t, 162\nvadduws\t\t, 163\nvand\t\t, 164\nvandc\t\t, 165\nvavgsb\t\t, 166\nvavgsh\t\t, 167\nvavgsw\t\t, 168\nvavgub\t\t, 169\nvavguh\t\t, 170\nvavguw\t\t, 171\nvcfsx\t\t, 172\nvcfux\t\t, 173\nvcmpbfp\t\t, 174\nvcmpbfp.\t, 174\nvcmpeqfp\t, 176\nvcmpeqfp.\t, 176\nvcmpequb\t, 177\nvcmpequb.\t, 177\nvcmpequh\t, 178\nvcmpequh.\t, 178\nvcmpequw\t, 179\nvcmpequw.\t, 179\nvcmpgefp\t, 180\nvcmpgefp.\t, 180\nvcmpgtfp\t, 181\nvcmpgtfp.\t, 181\nvcmpgtsb\t, 182\nvcmpgtsb.\t, 182\nvcmpgtsh\t, 183\nvcmpgtsh.\t, 183\nvcmpgtsw\t, 184\nvcmpgtsw.\t, 184\nvcmpgtub\t, 185\nvcmpgtub.\t, 185\nvcmpgtuh\t, 186\nvcmpgtuh.\t, 186\nvcmpgtuw\t, 187\nvcmpgtuw.\t, 187\nvctsxs\t\t, 188\nvctuxs\t\t, 189\nvexptefp\t, 190\nvlogefp\t\t, 192\nvmaddfp\t\t, 194\nvmaxfp\t\t, 195\nvmaxsb\t\t, 196\nvmaxsh\t\t, 197\nvmaxsw\t\t, 198\nvmaxub\t\t, 199\nvmaxuh\t\t, 200\nvmaxuw\t\t, 201\nvmhaddshs\t, 202\nvmhraddshs\t, 203\nvminfp\t\t, 204\nvminsb\t\t, 205\nvminsh\t\t, 206\nvminsw\t\t, 207\nvminub\t\t, 208\nvminuh\t\t, 209\nvminuw\t\t, 210\nvmladduhm\t, 211\nvmrghb\t\t, 212\nvmrghh\t\t, 213\nvmrghw\t\t, 214\nvmrglb\t\t, 215\nvmrglh\t\t, 216\nvmrglw\t\t, 217\nvmsummbm\t, 218\nvmsumshm\t, 219\nvmsumshs\t, 220\nvmsumubm\t, 221\nvmsumuhm\t, 222\nvmsumuhs\t, 223\nvmulesb\t\t, 224\nvmulesh\t\t, 225\nvmuleub\t\t, 226\nvmuleuh\t\t, 227\nvmulosb\t\t, 228\nvmulosh\t\t, 229\nvmuloub\t\t, 230\nvmulouh\t\t, 231\nvnmsubfp\t, 232\nvnor\t\t, 233\nvor\t\t\t, 234\nvperm\t\t, 235\nvpkpx\t\t, 236\nvpkshss\t\t, 237\nvpkshus\t\t, 238\nvpkswss\t\t, 239\nvpkswus\t\t, 240\nvpkuhum\t\t, 241\nvpkuhus\t\t, 242\nvpkuwum\t\t, 243\nvpkuwus\t\t, 244\nvrefp\t\t, 245\nvrfim\t\t, 247\nvrfin\t\t, 248\nvrfip\t\t, 249\nvrfiz\t\t, 250\nvrlb\t\t, 251\nvrlh\t\t, 252\nvrlw\t\t, 253\nvrsqrtefp\t, 254\nvsel\t\t, 256\nvsl\t\t\t, 257\nvslb\t\t, 258\nvsldoi\t\t, 259\nvslh\t\t, 260\nvslo\t\t, 261\nvslw\t\t, 262\nvspltb\t\t, 263\nvsplth\t\t, 264\nvspltisb\t, 265\nvspltish\t, 266\nvspltisw\t, 267\nvspltw\t\t, 268\nvsr\t\t\t, 269\nvsrab\t\t, 271\nvsrah\t\t, 272\nvsraw\t\t, 273\nvsrb\t\t, 274\nvsrh\t\t, 275\nvsro\t\t, 276\nvsrw\t\t, 277\nvsubcuw\t\t, 278\nvsubfp\t\t, 279\nvsubsbs\t\t, 280\nvsubshs\t\t, 281\nvsubsws\t\t, 282\nvsububm\t\t, 283\nvsububs\t\t, 284\nvsubuhm\t\t, 285\nvsubuhs\t\t, 286\nvsubuwm\t\t, 287\nvsubuws\t\t, 288\nvsumsws\t\t, 289\nvsum2sws\t, 290\nvsum4sbs\t, 291\nvsum4shs\t, 292\nvsum4ubs\t, 293\nvupkhpx\t\t, 294\nvupkhsb\t\t, 295\nvupkhsh\t\t, 296\nvupklpx\t\t, 297\nvupklsb\t\t, 298\nvupklsh\t\t, 299\nvxor\t\t, 300\n" }, { "path": "pypcode/processors/PowerPC/data/patterns/PPC_BE_patterns.xml", "content": "\n \n \n 0x4e800020 \n 010010.. 0x.. 0x.. ......00 \n \n \n 10010100 00100001 11...... .....000 \n 011111.. ...01000 00000010 10100110 \n 0x7c2c0b78 0x38 0x21 ........ ........ 0x91810000 \n \n \n \n \n \n \n 010010.. 0x.. 0x.. ......00 \n \n \n 10010100 00100001 11...... .....000 011111.. ...01000 00000010 10100110 \n 011111.. ...01000 00000010 10100110 10010100 00100001 11...... .....000 \n 10010100 00100001 11...... .....000 0x........ 011111.. ...01000 00000010 10100110 \n 011111.. ...01000 00000010 10100110 0x........ 10010100 00100001 11...... .....000 \n 10010100 00100001 11...... .....000 0x........ 0x........ 011111.. ...01000 00000010 10100110 \n 011111.. ...01000 00000010 10100110 0x........ 0x........ 10010100 00100001 11...... .....000 \n 0x7c2c0b78 0x38 0x21 ........ ........ 0x91810000 \n \n \n \n \n \n \n 10010100 00100001 11...... .....000 011111.. ...01000 00000010 10100110 \n \n \n \n \n \n 011111.. ...01000 00000010 10100110 10010100 00100001 11...... .....000 \n \n \n \n \n \n 0x4e 0x80 0x00 0x21 \n \n \n \n \n \n\t 0xf8410028 \n 001111.. ...00010 0xff 0xff \n\t 0xe9 ........ ........ ........ \n\t 0x7d 0x.9 0x03 0xa6 \n\t 0xe8 010..... ........ ........ \n\t 0x28220000 \n\t 0x4c 1..00010 0x04 0x20 \n\t 010010.. ........ ........ ......00 \n \n \n \n\n \n \n \t\t0xf8410028 \n 0xe9 ........ ........ ........ \n 0x7d 0x.9 0x03 0xa6 \n 0xe8 010..... ........ ........ \n 0x28220000 \n 0x4c 1..00010 0x04 0x20 \n 010010.. ........ ........ ......00 \n \n \n \n \n \n \n \t\t011111.. ...01000 0x02 0xa6 \n 0x42 1....... 0x00 0x05 \n 011111.. ...01000 0x02 0xa6 \n 001111.. ........ 0x.. 0x.. \n 001110.. ........ 0x.. 0x.. \n 011111.. ...01000 0x03 0xa6 \n 011111.. ...01001 0x03 0xa6 \n 0x4e 10000... 0x04 0x20 \n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/patterns/PPC_BE_prepatterns.xml", "content": " \n \n \n \n\t 0xf8410028 \n 001111.. ...00010 0xff 0xff \n\t 0xe9 ........ ........ ........ \n\t 0x7d 0x.9 0x03 0xa6 \n\t 0xe8 010..... ........ ........ \n\t 0x28220000 \n\t 0x4c 1..00010 0x04 0x20 \n\t 010010.. ........ ........ ......00 \n \n \n \n\n \n \n \t\t0xf8410028 \n 0xe9 ........ ........ ........ \n 0x7d 0x.9 0x03 0xa6 \n 0xe8 010..... ........ ........ \n 0x28220000 \n 0x4c 1..00010 0x04 0x20 \n 010010.. ........ ........ ......00 \n \n \n \n \n \n \n \t\t011111.. ...01000 0x02 0xa6 \n 0x42 1....... 0x00 0x05 \n 011111.. ...01000 0x02 0xa6 \n 001111.. ........ 0x.. 0x.. \n 001110.. ........ 0x.. 0x.. \n 011111.. ...01000 0x03 0xa6 \n 011111.. ...01001 0x03 0xa6 \n 0x4e 10000... 0x04 0x20 \n \n \n \n\n \n \n \n \t0x....823d\t# addis\tr12,r2,0x####\n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....6ce9 # ld\t\tr11,0x####(r12)\n \t0xa603697d # mtspr\tCTR,r11\n \t0x....4ce8 # ld\t\tr2,0x####(r12)\n \t0x....6ce9 # ld\t\tr11,0x####(r12)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....62e9 # ld\t\tr11,0x####(r2)\n \t0xa603697d # mtspr\tCTR,r11\n \t0x....62e9 # ld\t\tr11,0x####(r2)\n \t0x....42e8 # ld\t\tr2,0x####(r2)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....82e9\t# ld\t\tr12,0x####(r2)\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x2004804e\t# bctr\n \n \n \n \n \n \n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0x....6b39\t# addi\tr11,r11,0x####\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x....6be9\t# ld\t\tr11,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x7862827d\t# xor\tr2,r12,r12\n \t0x14126b7d\t# add\tr11,r11,r2\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0x....6b39\t# addi\tr11,r11,0x####\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x7862827d\t# xor\tr2,r12,r12\n \t0x14126b7d\t# add\tr11,r11,r2\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x....6be9\t# ld\t\tr11,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0x....6b39\t# addi\tr11,r11,0x####\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x....6be9\t# ld\t\tr11,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x7862827d\t# xor\tr2,r12,r12\n \t0x14126b7d\t# add\tr11,r11,r2\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x..0041f8 # std\tr2,0x##(r1)\n \t0x....623d\t# addis\tr11,r2,0x####\n \t0x....8be9\t# ld\t\tr12,0x####(r11)\n \t0x....6b39\t# addi\tr11,r11,0x####\n \t0xa603897d\t# mtspr\tCTR,r12\n \t0x7862827d\t# xor\tr2,r12,r12\n \t0x14126b7d\t# add\tr11,r11,r2\n \t0x....4be8\t# ld\t\tr2,0x####(r11)\n \t0x....6be9\t# ld\t\tr11,0x####(r11)\n \t0x2004804e\t# bctr\n \n \n \n \n \n \n\t \t0x0000823d\t# addis r12,r2,0x####\n\t \t0x00008ce9\t# ld\t\tr12,0x####(r12)\n\t \t0xa603897d\t# mtspr\tCTR,r12\n\t \t0x2004804e\t# bctr\n \n \n \n \n \n \t0x000041f8\t# std r2,0x####(r1) \n\t \t0x0000823d\t# addis r12,r2,0x####\n\t \t0x00008ce9\t# ld\t\tr12,0x####(r12)\n\t \t0xa603897d\t# mtspr\tCTR,r12\n\t \t0x2004804e\t# bctr\n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/patterns/PPC_LE_patterns.xml", "content": "\n \n \n 0x2000804e \n ......00 0x.. 0x.. 010010.. \n \n \n .....000 11...... 00100001 10010100 \n 10100110 00000010 ...01000 011111.. \n 0x780b2c7c ........ ........ 0x21 0x38 0x00008191 \n \n \n \n \n \n \n ......00 0x.. 0x.. 010010.. \n \n \n .....000 11...... 00100001 10010100 10100110 00000010 ...01000 011111.. \n 10100110 00000010 ...01000 011111.. .....000 11...... 00100001 10010100 \n .....000 11...... 00100001 10010100 0x........ 10100110 00000010 ...01000 011111.. \n 10100110 00000010 ...01000 011111.. 0x........ .....000 11...... 00100001 10010100 \n .....000 11...... 00100001 10010100 0x........ 0x........ 10100110 00000010 ...01000 011111.. \n 10100110 00000010 ...01000 011111.. 0x........ 0x........ .....000 11...... 00100001 10010100 \n 0x780b2c7c ........ ........ 0x21 0x38 0x00008191 \n \n \n \n \n \n \n .....000 11...... 00100001 10010100 10100110 00000010 ...01000 011111.. \n \n \n \n\n \n 10100110 00000010 ...01000 011111.. .....000 11...... 00100001 10010100 \n \n \n \n \n \n 0x21 0x00 0x80 0x4e \n \n \n\n \n \n\t 0x280041f8 \n\t 0xff 0xff ...00010 001111.. \n\t ........ ........ ........ 0xe9 \n\t 0xa6 0x03 0x.9 0x7d \n\t ........ ........ 010..... 0xe8 \n\t 0x00002228 \n\t 0x20 0x04 1..00010 0x4c \n\t ......00 ........ ........ 010010.. \n \n \n \n\n \n \n\t 0x280041f8 \n\t ........ ........ ........ 0xe9 \n\t 0xa6 0x03 0x.9 0x7d \n\t ........ ........ 010..... 0xe8 \n\t 0x00002228 \n\t 0x20 0x04 1..00010 0x4c \n\t ......00 ........ ........ 010010.. \n \n \n \n \n \n \n \t\t0xa6 0x02 ...01000 011111.. \n 0x05 0x00 1....... 0x42 \n 0xa6 0x02 ...01000 011111.. \n 0x.. 0x.. ........ 001111.. \n 0x.. 0x.. ........ 001110.. \n 0xa6 0x03 ...01000 011111.. \n 0xa6 0x03 ...01001 011111.. \n 0x20 0x04 10000... 0x4e \n \n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/patterns/PPC_LE_prepatterns.xml", "content": " \n \n \n \n\t 0x280041f8 \n\t 0xff 0xff ...00010 001111.. \n\t ........ ........ ........ 0xe9 \n\t 0xa6 0x03 0x.9 0x7d \n\t ........ ........ 010..... 0xe8 \n\t 0x00002228 \n\t 0x20 0x04 1..00010 0x4c \n\t ......00 ........ ........ 010010.. \n \n \n \n\n \n \n\t 0x280041f8 \n\t ........ ........ ........ 0xe9 \n\t 0xa6 0x03 0x.9 0x7d \n\t ........ ........ 010..... 0xe8 \n\t 0x00002228 \n\t 0x20 0x04 1..00010 0x4c \n\t ......00 ........ ........ 010010.. \n \n \n \n \n \n \n \t\t0xa6 0x02 ...01000 011111.. \n 0x05 0x00 1....... 0x42 \n 0xa6 0x02 ...01000 011111.. \n 0x.. 0x.. ........ 001111.. \n 0x.. 0x.. ........ 001110.. \n 0xa6 0x03 ...01000 011111.. \n 0xa6 0x03 ...01001 011111.. \n 0x20 0x04 10000... 0x4e \n \n \n \n\n \n \n \n \t0x3d82....\t# addis\tr12,r2,0x####\n \t0xf84100.. # std\tr2,0x##(r1)\n \t0xe96c.... # ld\t\tr11,0x####(r12)\n \t0x7d6903a6 # mtspr\tCTR,r11\n \t0xe84c.... # ld\t\tr2,0x####(r12)\n \t0xe96c.... # ld\t\tr11,0x####(r12)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf84100.. # std\tr2,0x##(r1)\n \t0xe962.... # ld\t\tr11,0x####(r2)\n \t0x7d6903a6 # mtspr\tCTR,r11\n \t0xe962.... # ld\t\tr11,0x####(r2)\n \t0xe842.... # ld\t\tr2,0x####(r2)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf84100.. # std\tr2,0x##(r1)\n \t0xe982....\t# ld\t\tr12,0x####(r2)\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0x4e800420\t# bctr\n \n \n \n \n \n \n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x396b....\t# addi\tr11,r11,0x####\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0xe96b....\t# ld\t\tr11,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0x7d826278\t# xor\tr2,r12,r12\n \t0x7d6b1214\t# add\tr11,r11,r2\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x396b....\t# addi\tr11,r11,0x####\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0x7d826278\t# xor\tr2,r12,r12\n \t0x7d6b1214\t# add\tr11,r11,r2\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0xe96b....\t# ld\t\tr11,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf84100.. # std\tr2,0x##(r1)\n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf84100.. # std\tr2,0x##(r1)\n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x396b....\t# addi\tr11,r11,0x####\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0xe96b....\t# ld\t\tr11,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf84100.. # std\tr2,0x##(r1)\n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0x7d826278\t# xor\tr2,r12,r12\n \t0x7d6b1214\t# add\tr11,r11,r2\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf84100.. # std\tr2,0x##(r1)\n \t0x3d62....\t# addis\tr11,r2,0x####\n \t0xe98b....\t# ld\t\tr12,0x####(r11)\n \t0x396b....\t# addi\tr11,r11,0x####\n \t0x7d8903a6\t# mtspr\tCTR,r12\n \t0x7d826278\t# xor\tr2,r12,r12\n \t0x7d6b1214\t# add\tr11,r11,r2\n \t0xe84b....\t# ld\t\tr2,0x####(r11)\n \t0xe96b....\t# ld\t\tr11,0x####(r11)\n \t0x4e800420\t# bctr\n \n \n \n \n \n \n\t \t0x3d820000\t# addis r12,r2,0x####\n\t \t0xe98c0000\t# ld\t\tr12,0x####(r12)\n\t \t0x7d8903a6\t# mtspr\tCTR,r12\n\t \t0x4e800420\t# bctr\n \n \n \n \n \n \t0xf8410000\t# std r2,0x####(r1) \n\t \t0x3d820000\t# addis r12,r2,0x####\n\t \t0xe98c0000\t# ld\t\tr12,0x####(r12)\n\t \t0x7d8903a6\t# mtspr\tCTR,r12\n\t \t0x4e800420\t# bctr\n \n \n \n\n" }, { "path": "pypcode/processors/PowerPC/data/patterns/patternconstraints.xml", "content": "\n \n PPC_BE_patterns.xml\n \n \n PPC_LE_patterns.xml\n \n" }, { "path": "pypcode/processors/PowerPC/data/patterns/prepatternconstraints.xml", "content": "\n \n PPC_BE_prepatterns.xml\n \n \n PPC_LE_prepatterns.xml\n \n" }, { "path": "pypcode/processors/RISCV/data/languages/RV32.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n\n\n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n\n\n \n\n\n \n \n \n\n\n \n \n \n \n \n\n\n \n\n\n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n\n\n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n\n \n\n\n \n\n\n \n\n\n \n \n \n \n\n \n\n \n \n \n \n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n\n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/RV64.pspec", "content": "\n\n\n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n\n\n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n\n\n \n\n\n \n \n \n\n\n \n \n \n \n \n\n\n \n\n\n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n \n\n\n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n\n \n\n\n \n\n\n \n\n\n \n \n \n \n\n \n\n \n \n \n \n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n\n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n\n \n\n\n \n \n \n \n\n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/andestar_v5.instr.sinc", "content": "#\n# AndeStar V5 extensions to base RISC-V architecture\n#\n\n#\n# ExecTable is loaded/overlayed on the memory segment\n# That is indexed by the E\ndefine space ExecTable type=ram_space size=2;\n\n@define CUSTOM0 \"op0006=0b0001011\"\n@define CUSTOM1 \"op0006=0b0101011\"\n@define CUSTOM2 \"op0006=0b1011011\"\n@define CUSTOM4 \"op0006=0b1010111\"\n\nsimm18_lb: val is sop3131 & op1516 & op1719 & op2020 & op2130 & op1414 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2130<<1) | op1414; ] {\n\texport *[const]:$(XLEN) val;\n}\n\nsimm18_lh: val is sop3131 & op1516 & op1719 & op2020 & op2130 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2130<<1); ] {\n\texport *[const]:$(XLEN) val;\n}\n\n#simm18_lw: val is sop3131 & op1516 & op1719 & op2020 & op2130 [ val = (sop3131<<18) | (op1516<<16) | (op1719<<13) | (op2020<<12) | (op2130<<2); ] {\nsimm18_lw: val is sop3131 & op2121 & op1516 & op1719 & op2020 & op2230 [ val = (sop3131<<18) | (op2121 << 17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2230<<2); ] {\n\texport *[const]:$(XLEN) val;\n}\n\nsimm18_ld: val is sop3131 & op1516 & op1719 & op2020 & op2122 & op2330 [ val = (sop3131<<19) | (op2122<<17) | (op1516<<15) | (op1719<<12) | (op2330<<3); ] {\n\texport *[const]:$(XLEN) val;\n}\n\nsimm18_sb: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0811 & op1414 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0811<<1) | op1414; ] {\n\texport *[const]:$(XLEN) val;\n}\n\nsimm18_sh: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0811 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0811<<1); ] {\n\texport *[const]:$(XLEN) val;\n}\n\nsimm18_sw: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0808 & op0911 [ val = (sop3131<<18) | (op0808<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0911<<2); ] {\n\texport *[const]:$(XLEN) val;\n}\n\nsimm18_sd: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0809 & op1011 [ val = (sop3131<<19) | (op0809<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op1011<<3); ] {\n\texport *[const]:$(XLEN) val;\n}\n\ncimm: \"#\"^val is op2024 & op0707 [ val = op0707<<5 | op2024; ] {\n\t# Note on 32-bit op0707 must be 0\n\texport *[const]:$(XLEN) val;\n}\n\ncimm7: \"#\"^val is op3030 & op2024 & op0707 [ val = op3030<<6 | op0707<<5 | op2024; ] {\n\texport *[const]:$(XLEN) val;\n}\n\nra_imm10: dest is sop3131 & op2529 & op0811 [ dest = inst_start + (sop3131 << 10 | op2529<<5 | op0811<<1); ] {\n\texport *[ram]:$(XLEN) dest;\n}\n\n\n:addigp rd,simm18_lb is simm18_lb & rd & op1213=1 & $(CUSTOM0)\n{\n\trd = gp + simm18_lb;\n}\n\n:bbc rs1,cimm,ra_imm10 is rs1 & cimm & ra_imm10 & op3030=0 & op1214=0b111 & op0707=0 & $(CUSTOM2)\n{\n\ttst:1 = (rs1 & (1 << cimm)) == 0;\n\tif (tst) goto ra_imm10;\n}\n\n:bbs rs1,cimm,ra_imm10 is rs1 & cimm & ra_imm10 & op3030=1 & op1214=0b111 & op0707=0 & $(CUSTOM2)\n{\n\ttst:1 = (rs1 & (1 << cimm)) == 1;\n\tif (tst) goto ra_imm10;\n}\n\n:beqc rs1,cimm7,ra_imm10 is rs1 & cimm7 & ra_imm10 & op1214=0b101 & $(CUSTOM2)\n{\n\ttst:1 = rs1 == cimm7;\n\tif (tst) goto ra_imm10;\n}\n\n:bnec rs1,cimm7,ra_imm10 is rs1 & cimm7 & ra_imm10 & op1214=0b110 & $(CUSTOM2)\n{\n\ttst:1 = rs1 != cimm7;\n\tif (tst) goto ra_imm10;\n}\n\nmsb: \"#\"^op2631 is op2631 { export *[const]:$(XLEN) op2631; }\nlsb: \"#\"^op2025 is op2025 { export *[const]:$(XLEN) op2025; }\n\n:bfos rd,rs1,msb,lsb is rd & rs1 & op2631=0 & msb & lsb & op1214=0b011 & $(CUSTOM2)\n{\n\t# msb==0 Rd[LSB] = sext(Rs1[0])\n\tshift:$(XLEN) = ($(XLEN)*8-1);\n\tval:$(XLEN) = (rs1 & 1 << shift) s>> (shift);\n\tval = val << lsb;\n\trd = val;\n}\n\n:bfos rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 > op2631) & (op2631 != 0) & op1214=0b011 & $(CUSTOM2)\n{\n\t# msb < lsb Rd[LSB:MSB] = sext(Rs1[len-1:0])\n\tlen:$(XLEN) = lsb-msb+1;\n\tshift:$(XLEN) = ($(XLEN)*8 - len);\n\tval:$(XLEN) = (rs1 << shift) s>> shift;\n\tval = val << msb;\n\trd = val;\n}\n\n:bfos rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 <= op2631) & (op2631 != 0) & op1214=0b011 & $(CUSTOM2)\n{\n\t# msb >= lsb Rd[len-1:0] = sext(Rs1[MSB:LSB])\n\tlen:$(XLEN) = msb-lsb+1;\n\tshift:$(XLEN) = ($(XLEN)*8 - msb - 1);\n\tval:$(XLEN) = (rs1 << shift) s>> ($(XLEN)*8 - len);\n\trd = val;\n}\n\n:bfoz rd,rs1,msb,lsb is rd & rs1 & op2631=0 & msb & lsb & op1214=0b010 & $(CUSTOM2)\n{\n\t# msb==0 Rd[LSB] = zext(Rs1[0])\n\tval:$(XLEN) = rs1 & 1;\n\tval = val << lsb;\n\trd = val;\n}\n\n:bfoz rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 > op2631) & (op2631 != 0) & op1214=0b010 & $(CUSTOM2)\n{\n\t# msb < lsb Rd[LSB:MSB] = zext(Rs1[len-1:0])\n\tlen:$(XLEN) = lsb-msb+1;\n\tmask:$(XLEN) = ((-1) >> ($(XLEN)*8 -len));\n\tval:$(XLEN) = rs1 & mask;\n\tval = val << msb;\n\trd = val;\n}\n\n:bfoz rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 <= op2631) & op1214=0b010 & $(CUSTOM2)\n{\n\t# msb >= lsb Rd[len-1:0] = zext(Rs1[MSB:LSB])\n\tlen:$(XLEN) = msb-lsb+1;\n\tmask:$(XLEN) = ((-1) >> ($(XLEN)*8 -len)) << lsb;\n\tval:$(XLEN) = rs1 & mask;\n\tval = val >> lsb;\n\trd = val;\n}\n\n\n\n:lea.h rd,rs1,rs2 is op2531=0b0000101 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + rs2 * 2;\n\trd = ea;\n}\n\n:lea.w rd,rs1,rs2 is op2531=0b0000110 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + rs2 * 4;\n\trd = ea;\n}\n\n:lea.d rd,rs1,rs2 is op2531=0b0000111 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + rs2 * 8;\n\trd = ea;\n}\n\n:lea.b.ze rd,rs1,rs2 is op2531=0b0001000 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + zext(rs2:4);\n\trd = ea;\n}\n\n:lea.h.ze rd,rs1,rs2 is op2531=0b0001001 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + zext(rs2:4) * 2;\n\trd = ea;\n}\n\n:lea.w.ze rd,rs1,rs2 is op2531=0b0001010 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + zext(rs2:4) * 4;\n\trd = ea;\n}\n\n:lea.d.ze rd,rs1,rs2 is op2531=0b0001011 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)\n{\n\tlocal ea:$(XLEN) = rs1 + zext(rs2:4) * 8;\n\trd = ea;\n}\n\n:lbgp rd,\"[\"^simm18_lb^\"]\" is simm18_lb & rd & op1213=0 & $(CUSTOM0)\n{\n\tlocal ea:$(XLEN) = gp + simm18_lb;\n\trd = sext(*[ram]:1 ea);\n}\n\n:lbugp rd,\"[\"^simm18_lb^\"]\" is simm18_lb & rd & op1213=2 & $(CUSTOM0)\n{\n\tlocal ea:$(XLEN) = gp + simm18_lb;\n\trd = zext(*[ram]:1 ea);\n}\n\n:lhgp rd,\"[\"^simm18_lh^\"]\" is simm18_lh & rd & op1214=1 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_lh;\n\trd = sext(*[ram]:2 ea);\n}\n\n:lhugp rd,\"[\"^simm18_lh^\"]\" is simm18_lh & rd & op1214=5 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_lh;\n\trd = zext(*[ram]:2 ea);\n}\n\n:lwgp rd,\"[\"^simm18_lw^\"]\" is simm18_lw & rd & op1214=2 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_lw;\n\trd = sext(*[ram]:4 ea);\n}\n\n:lwugp rd,\"[\"^simm18_lw^\"]\" is simm18_lw & rd & op1214=6 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_lw;\n\trd = zext(*[ram]:4 ea);\n}\n\n:ldgp rd,\"[\"^simm18_ld^\"]\" is simm18_ld & rd & op1214=3 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_ld;\n\trd = *[ram]:8 ea;\n}\n\n:sbgp rs2,\"[\"^simm18_sb^\"]\" is simm18_sb & rs2 & op1213=3 & $(CUSTOM0)\n{\n\tlocal ea:$(XLEN) = gp + simm18_sb;\n\t*[ram]:1 ea = rs2[0,8];\n}\n\n:shgp rs2,\"[\"^simm18_sh^\"]\" is simm18_sh & rs2 & op1214=0 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_sh;\n\t*[ram]:2 ea = rs2[0,16];\n}\n\n:swgp rs2,\"[\"^simm18_sw^\"]\" is simm18_sw & rs2 & op1214=4 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_sw;\n\t*[ram]:4 ea = rs2[0,32];\n}\n\n:sdgp rs2,\"[\"^simm18_sd^\"]\" is simm18_sd & rs2 & op1214=7 & $(CUSTOM1)\n{\n\tlocal ea:$(XLEN) = gp + simm18_sd;\n\t*[ram]:8 ea = rs2;\n}\n\n\n:ffb rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010000 & op1214=0 & $(CUSTOM2) {\n@if XLEN == \"4\"\n\tm1:1 = (rs1[0,8] == rs2[0,8]);\n\tm2:1 = (rs1[8,8] == rs2[0,8]);\n\tm3:1 = (rs1[16,8] == rs2[0,8]);\n\tm4:1 = (rs1[24,8] == rs2[0,8]);\n\trd = -4;\n\tif (m1) goto inst_next;\n\trd = -3;\n\tif (m2) goto inst_next;\n\trd = -2;\n\tif (m3) goto inst_next;\n\trd = -1;\n\tif (m4) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n@else\n \tm1:1 = (rs1[0,8] == rs2[0,8]);\n\tm2:1 = (rs1[8,8] == rs2[0,8]);\n\tm3:1 = (rs1[16,8] == rs2[0,8]);\n\tm4:1 = (rs1[24,8] == rs2[0,8]);\n\tm5:1 = (rs1[32,8] == rs2[0,8]);\n\tm6:1 = (rs1[40,8] == rs2[0,8]);\n\tm7:1 = (rs1[48,8] == rs2[0,8]);\n\tm8:1 = (rs1[56,8] == rs2[0,8]);\n\trd = -8;\n\tif (m1) goto inst_next;\n\trd = -7;\n\tif (m2) goto inst_next;\n\trd = -6;\n\tif (m3) goto inst_next;\n\trd = -5;\n\tif (m4) goto inst_next;\n\trd = -4;\n\tif (m5) goto inst_next;\n\trd = -3;\n\tif (m6) goto inst_next;\n\trd = -2;\n\tif (m7) goto inst_next;\n\trd = -1;\n\tif (m8) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);\n@endif\n}\n\n:ffzmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010001 & op1214=0 & $(CUSTOM2) {\n@if XLEN == \"4\"\n\tm1:1 = (rs1[0,8]==0) | (rs1[0,8] == rs2[0,8]);\n\tm2:1 = (rs1[8,8]==0) | (rs1[8,8] == rs2[8,8]);\n\tm3:1 = (rs1[16,8]==0) | (rs1[16,8] == rs2[16,8]);\n\tm4:1 = (rs1[24,8]==0) | (rs1[24,8] == rs2[24,8]);\n\trd = -4;\n\tif (m1) goto inst_next;\n\trd = -3;\n\tif (m2) goto inst_next;\n\trd = -2;\n\tif (m3) goto inst_next;\n\trd = -1;\n\tif (m4) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n@else\n \tm1:1 = (rs1[0,8]==0) | (rs1[0,8] == rs2[0,8]);\n\tm2:1 = (rs1[8,8]==0) | (rs1[8,8] == rs2[8,8]);\n\tm3:1 = (rs1[16,8]==0) | (rs1[16,8] == rs2[16,8]);\n\tm4:1 = (rs1[24,8]==0) | (rs1[24,8] == rs2[24,8]);\n\tm5:1 = (rs1[32,8]==0) | (rs1[32,8] == rs2[32,8]);\n\tm6:1 = (rs1[40,8]==0) | (rs1[40,8] == rs2[40,8]);\n\tm7:1 = (rs1[48,8]==0) | (rs1[48,8] == rs2[48,8]);\n\tm8:1 = (rs1[56,8]==0) | (rs1[56,8] == rs2[56,8]);\n\trd = -8;\n\tif (m1) goto inst_next;\n\trd = -7;\n\tif (m2) goto inst_next;\n\trd = -6;\n\tif (m3) goto inst_next;\n\trd = -5;\n\tif (m4) goto inst_next;\n\trd = -4;\n\tif (m5) goto inst_next;\n\trd = -3;\n\tif (m6) goto inst_next;\n\trd = -2;\n\tif (m7) goto inst_next;\n\trd = -1;\n\tif (m8) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);\n@endif\n}\n\n:ffmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010010 & op1214=0 & $(CUSTOM2) {\n@if XLEN == \"4\"\n\tm1:1 = (rs1[0,8] != rs2[0,8]);\n\tm2:1 = (rs1[8,8] != rs2[8,8]);\n\tm3:1 = (rs1[16,8] != rs2[16,8]);\n\tm4:1 = (rs1[24,8] != rs2[24,8]);\n\trd = -4;\n\tif (m1) goto inst_next;\n\trd = -3;\n\tif (m2) goto inst_next;\n\trd = -2;\n\tif (m3) goto inst_next;\n\trd = -1;\n\tif (m4) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n@else\n \tm1:1 = (rs1[0,8] != rs2[0,8]);\n\tm2:1 = (rs1[8,8] != rs2[8,8]);\n\tm3:1 = (rs1[16,8] != rs2[16,8]);\n\tm4:1 = (rs1[24,8] != rs2[24,8]);\n\tm5:1 = (rs1[32,8] != rs2[32,8]);\n\tm6:1 = (rs1[40,8] != rs2[40,8]);\n\tm7:1 = (rs1[48,8] != rs2[48,8]);\n\tm8:1 = (rs1[56,8] != rs2[56,8]);\n\trd = -8;\n\tif (m1) goto inst_next;\n\trd = -7;\n\tif (m2) goto inst_next;\n\trd = -6;\n\tif (m3) goto inst_next;\n\trd = -5;\n\tif (m4) goto inst_next;\n\trd = -4;\n\tif (m5) goto inst_next;\n\trd = -3;\n\tif (m6) goto inst_next;\n\trd = -2;\n\tif (m7) goto inst_next;\n\trd = -1;\n\tif (m8) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);\n@endif\n}\n\n:flmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010011 & op1214=0 & $(CUSTOM2) {\n@if XLEN == \"4\"\n\tm1:1 = (rs1[0,8] != rs2[0,8]);\n\tm2:1 = (rs1[8,8] != rs2[8,8]);\n\tm3:1 = (rs1[16,8] != rs2[16,8]);\n\tm4:1 = (rs1[24,8] != rs2[24,8]);\n\trd = -1;\n\tif (m4) goto inst_next;\n\trd = -2;\n\tif (m3) goto inst_next;\n\trd = -3;\n\tif (m2) goto inst_next;\n\trd = -4;\n\tif (m1) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);\n@else\n \tm1:1 = (rs1[0,8] != rs2[0,8]);\n\tm2:1 = (rs1[8,8] != rs2[8,8]);\n\tm3:1 = (rs1[16,8] != rs2[16,8]);\n\tm4:1 = (rs1[24,8] != rs2[24,8]);\n\tm5:1 = (rs1[32,8] != rs2[32,8]);\n\tm6:1 = (rs1[40,8] != rs2[40,8]);\n\tm7:1 = (rs1[48,8] != rs2[48,8]);\n\tm8:1 = (rs1[56,8] != rs2[56,8]);\n\trd = -1;\n\tif (m8) goto inst_next;\n\trd = -2;\n\tif (m7) goto inst_next;\n\trd = -3;\n\tif (m6) goto inst_next;\n\trd = -4;\n\tif (m5) goto inst_next;\n\trd = -5;\n\tif (m4) goto inst_next;\n\trd = -6;\n\tif (m3) goto inst_next;\n\trd = -7;\n\tif (m2) goto inst_next;\n\trd = -8;\n\tif (m1) goto inst_next;\n\trd = 0;\n\t# choosery method\n\t# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);\n@endif\n}\n\nimm11_exec: val is cop1212 & cop1011 & cop0909 & cop0808 & cop0506 & cop0404 & cop0303 & cop0202\n [ val = (cop0808<<11)|(cop1212<<10)|(cop0303<<9)|(cop0909<<8)|(cop0506<<6)|(cop0202<<5)|(cop1011<<3)|(cop0404<<2); ] {\n \texport *[ExecTable]:2 val;\n}\n\n#\n# Code Dense (CoDense) extension\n\n\n#100 imm[10|4:3|8] imm[11] 0 imm[7:6|2|9|5] 00\n:exec.it imm11_exec is ecdv=0 & cop1315=4 & imm11_exec & cop0707=0 & cop0001=0 {\n\tExecRetAddr = inst_next;\n\tgoto imm11_exec;\n}\n\n:ex9.it imm11_exec is ecdv=0 & cop1315=4 & imm11_exec & cop0708=0 & cop0001=0 {\n\tExecRetAddr = inst_next;\n\tgoto imm11_exec;\n}\n\n#\n# alternate version of EXEC.IT when mmsc_cfb.ECDV=1\n#\nimm11_nexec: val is cop1011 & cop0909 & cop0808 & cop0707 & cop0506 & cop0404 & cop0303 & cop0202\n [ val = (cop0808<<11)|(cop0707<<10)|(cop0303<<9)|(cop0909<<8)|(cop0506<<6)|(cop0202<<5)|(cop1011<<3)|(cop0404<<2); ] {\n \texport *[ExecTable]:2 val;\n}\n\n# 100 1 imm[4:3|8] imm[11] imm[10] imm[7:6|2|9|5] 00\n:nexec.it imm11_nexec is ecdv=1 & cop1315=4 & cop1212=1 & imm11_nexec & cop0001=0 {\n\tExecRetAddr = inst_next;\n\tgoto imm11_nexec;\n}\n\n#\n# INT4 vector load extension\n#\ndefine pcodeop vln8;\n\n:vln8.v vd,(rs1)^vm is vd & rs1 & op2631=0b000001 & vm & op2024=0b00010 & op1214=0b100 & $(CUSTOM2) {\n\t# TODO load 32 4bit values, possibly sext by vm into 32 8-bit vector registers\n\tval:$(VLEN) = *[ram]:$(VLEN) rs1;\n\tvd = vln8(val);\n\tbuild vm;\n}\n\n:vlnu8.v vd,(rs1)^vm is vd & rs1 & op2631=0b000001 & vm & op2024=0b00011 & op1214=0b100 & $(CUSTOM2) {\n\t# TODO load 32 4bit values, possibly zext by vm into 32 8-bit vector registers\n\tval:$(VLEN) = *[ram]:$(VLEN) rs1;\n\tvd = vln8(val);\n\tbuild vm;\n}\n\n\n#\n# bfloat16 conversion extension\n#\ndefine pcodeop fcvt.s.bf16;\n\n:fcvt.s.bf16 frd,frs2 is frd & frs2 & op2531=0 & op1519=0b00010 & op1214=0b100 & $(CUSTOM2) {\n\tfrd = fcvt.s.bf16(frs2);\n}\n\ndefine pcodeop fcvt.bf16.s;\n\n:fcvt.bf16.s frd,frs2 is frd & frs2 & op2531=0 & op1519=0b00011 & op1214=0b100 & $(CUSTOM2) {\n\tfrd = fcvt.bf16.s(frs2);\n}\n\n#\n# Vector BFloat16 conversion extension\n#\n\ndefine pcodeop vfwcvt.s.bf16;\n\n:vfwcvt.s.bf16 vd,vs2 is vd & vs2 & op2631=0b000000 & op1519=0b00000 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfwcvt.s.bf16(vs2);\n}\n\ndefine pcodeop vfncvt.bf16.s;\n\n:vfncvt.bf16.s vd,vs2 is vd & vs2 & op2631=0b000000 & op1519=0b00001 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfncvt.bf16.s(vs2);\n}\n\ndefine pcodeop vfpmadt.vf;\n\n:vfpmadt.vf vd,rs1,vs2^vm is vd & rs1 & vs2 & vm & op2631=0b000010 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfpmadt.vf(rs1,vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vfpmadb.vf;\n\n:vfpmadb.vf vd,rs1,vs2^vm is vd & rs1 & vs2 & vm & op2631=0b000011 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfpmadb.vf(rs1,vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vd4dots.vv;\n\n:vd4dots.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000100 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vd4dots.vv(vs1,vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vd4dotu.vv;\n\n:vd4dotu.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000111 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vd4dotu.vv(vs1,vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vd4dotsu.vv;\n\n:vd4dotsu.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000101 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vd4dotsu.vv(vs1,vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vle4.v;\n\n:vle4.v vd,(rs1) is vd & rs1 & op2631=0b000001 & op2525=1 & op2024=0b00000 & op1214=0b100 & $(CUSTOM2) {\n\tval:$(VLEN) = *[ram]:$(VLEN) rs1;\n\tvd = vle4.v(val);\n}\n\ndefine pcodeop vfwcvt.f.n.v;\n\n:vfwcvt.f.n.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00100 & op1214=0b100 & $(CUSTOM2) {\n vd = vfwcvt.f.n.v(vs2);\n build vm;\n}\n\ndefine pcodeop vfwcvt.f.nu.v;\n\n:vfwcvt.f.nu.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00101 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfwcvt.f.nu.v(vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vfwcvt.f.b.v;\n\n:vfwcvt.f.b.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00110 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfwcvt.f.b.v(vs2);\n\tbuild vm;\n}\n\ndefine pcodeop vfwcvt.f.bu.v;\n\n:vfwcvt.f.bu.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00111 & op1214=0b100 & $(CUSTOM2) {\n\tvd = vfwcvt.f.bu.v(vs2);\n\tbuild vm;\n}\n\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/andestar_v5.ldefs", "content": "\n\n\n\n \n AndeStar v5 RISC-V based 32 little default\n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/andestar_v5.slaspec", "content": "define endian=little;\n\n@define XLEN 4\n@define XLEN2 8\n@define FLEN 8\n@define CONTEXTLEN 8\n\n@define ADDRSIZE \"32\"\n@define FPSIZE \"64\"\n\n@include \"riscv.reg.sinc\"\n\ndefine context CONTEXT\n isExecInstr=(32,32)\n phase=(33,33)\n ecdv=(34,34)\n;\n\n@include \"riscv.table.sinc\"\n\n\n# artificial return register\n\ndefine register offset=0x6000 size=4 [ ExecRetAddr ];\n\nDest: is epsilon { export *[ram]:1 ExecRetAddr; }\n\n:^instruction is phase=0 & isExecInstr=1 & instruction [ phase=1; ] { build instruction; local dest:$(XLEN) = ExecRetAddr; goto [dest]; }\n:^instruction is phase=0 & isExecInstr=0 & instruction [ phase=1; ] { build instruction; }\n\nwith : phase=1 {\n@include \"riscv.instr.sinc\"\n\n@include \"andestar_v5.instr.sinc\"\n\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/old/riscv_deprecated.ldefs", "content": "\n\n\n\n \n RISC-V 64 little base\n \n \n \n \n \n \n \n RISC-V 64 little base compressed\n \n \n \n \n \n \n \n RISC-V 64 little general purpose\n \n \n \n \n \n \n \n RISC-V 64 little general purpose compressed\n \n \n \n \n \n \n \n RISC-V 32 little base\n \n \n \n \n \n \n \n RISC-V 32 little base compressed\n \n \n \n \n \n \n \n RISC-V 32 little base compressed\n \n \n \n \n \n \n \n RISC-V 32 little general purpose\n \n \n \n \n \n \n \n RISC-V 32 little general purpose compressed\n \n \n \n \n \n \n \n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.csr.sinc", "content": "# RV32/RV64 Zicsr Standard Extension\n\n\n# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) \n:csrc csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711=0\n{\n\tlocal tmprs1:$(XLEN) = rs1;\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal newcsr:$(XLEN) = oldcsr & ~tmprs1;\n\tcsr = newcsr;\n}\n\n# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) \n:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711\n{\n\tlocal tmprs1:$(XLEN) = rs1;\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal newcsr:$(XLEN) = oldcsr & ~tmprs1;\n\tcsr = newcsr;\n\trdDst = oldcsr;\n}\n\n# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) \n:csrci csr,op1519 is op1519 & op0711=0 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal tmp:$(XLEN) = op1519;\n\tcsr = oldcsr & ~tmp;\n}\n\n\n# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) \n:csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal tmp:$(XLEN) = op1519;\n\tcsr = oldcsr & ~tmp;\n\trdDst = oldcsr;\n}\n\n\n# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) \n:csrr rdDst,csr is csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711\n{\n\trdDst = csr:$(XLEN);\n}\n\n# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) \n:csrs csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711=0\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tcsr = oldcsr | rs1;\n}\n\n# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) \n:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tcsr = oldcsr | rs1;\n\trdDst = oldcsr;\n}\n\n# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) \n:csrsi csr,op1519 is op1519 & csr & op0711=0 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal tmp:$(XLEN) = op1519;\n\tcsr = oldcsr | tmp;\n}\n\n# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) \n:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal tmp:$(XLEN) = op1519;\n\tcsr = oldcsr | tmp;\n\trdDst = oldcsr;\n}\n\n# csrw d,E,s 00001073 0000707f SIMPLE (0, 0) \n:csrw csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & r0711=0\n{\n\tcsr = rs1;\n}\n\n# csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) \n:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1\n{\n\tlocal tmprs1:$(XLEN) = rs1;\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tcsr = tmprs1;\n\trdDst = oldcsr;\n}\n\n# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) \n:csrwi csr,op1519 is op1519 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711=0\n{\n\tlocal val:$(XLEN) = op1519;\n\tcsr = val;\n}\n\n# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) \n:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711\n{\n\tlocal oldcsr:$(XLEN) = csr:$(XLEN);\n\tlocal val:$(XLEN) = op1519;\n\tcsr = val;\n\trdDst = oldcsr;\n}\n\n\n# frcsr d 00302073 fffff07f SIMPLE (0, 0) \n:frcsr rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60\n{\n\trdDst = fcsr;\n}\n\n# frflags d 00102073 fffff07f SIMPLE (0, 0) \n:frflags rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20\n{\n\trdDst = zext(fflags[0,5]);\n}\n\n# frrm d 00202073 fffff07f SIMPLE (0, 0) \n:frrm rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40\n{\n\trdDst = frm;\n}\n\n# fscsr s 00301073 fff07fff SIMPLE (0, 0) \n:fscsr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3\n{\n\tzero = fcsr;\n\tfcsr = rs1;\n}\n\n# fscsr d,s 00301073 fff0707f SIMPLE (0, 0) \n:fscsr rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3\n{\n\trdDst = fcsr;\n\tfcsr = rs1;\n}\n\n\n# fsflags s 00101073 fff07fff SIMPLE (0, 0) \n:fsflags rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x1\n{\n\tzero = zext(fflags[0,5]);\n\tfflags[0,5] = rs1[0,5];\n}\n\n# fsflags d,s 00101073 fff0707f SIMPLE (0, 0) \n:fsflags rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1\n{\n\trdDst = zext(fflags[0,5]);\n\tfflags[0,5] = rs1[0,5];\n}\n\n# fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0) \n:fsflagsi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1\n{\n\trdDst = zext(fflags[0,5]);\n\tlocal tmp:1 = op1519:1;\n\tfflags[0,5] = tmp[0,5];\n}\n\n# fsflagsi Z 00105073 fff07fff SIMPLE (0, 0) \n:fsflagsi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x1\n{\n\tzero = zext(fflags[0,5]);\n\tlocal tmp:1 = op1519:1;\n\tfflags[0,5] = tmp[0,5];\n}\n\n# fsrm s 00201073 fff07fff SIMPLE (0, 0) \n:fsrm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x2\n{\n\tzero = zext(frm[0,3]);\n\tfrm[0,3] = rs1[0,3];\n}\n\n# fsrm d,s 00201073 fff0707f SIMPLE (0, 0) \n:fsrm rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2\n{\n\trdDst = zext(frm[0,3]);\n\tfrm[0,3] = rs1[0,3];\n}\n\n# fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0) \n:fsrmi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2\n{\n\trdDst = zext(frm[0,3]);\n\tlocal tmp:1 = op1519:1;\n\tfrm[0,3] = tmp[0,3];\n}\n\n# fsrmi Z 00205073 fff07fff SIMPLE (0, 0) \n:fsrmi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x2\n{\n\tzero = zext(frm[0,3]);\n\tlocal tmp:1 = op1519:1;\n\tfrm[0,3] = tmp[0,3];\n}\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.custom.sinc", "content": "# custom\n\ndefine pcodeop custom0;\ndefine pcodeop custom0.rs1;\ndefine pcodeop custom0.rs1.rs2;\ndefine pcodeop custom0.rd;\ndefine pcodeop custom0.rd.rs1;\ndefine pcodeop custom0.rd.rs1.rs2;\n\ndefine pcodeop custom1;\ndefine pcodeop custom1.rs1;\ndefine pcodeop custom1.rs1.rs2;\ndefine pcodeop custom1.rd;\ndefine pcodeop custom1.rd.rs1;\ndefine pcodeop custom1.rd.rs1.rs2;\n\ndefine pcodeop custom2;\ndefine pcodeop custom2.rs1;\ndefine pcodeop custom2.rs1.rs2;\ndefine pcodeop custom2.rd;\ndefine pcodeop custom2.rd.rs1;\ndefine pcodeop custom2.rd.rs1.rs2;\n\ndefine pcodeop custom3;\ndefine pcodeop custom3.rs1;\ndefine pcodeop custom3.rs1.rs2;\ndefine pcodeop custom3.rd;\ndefine pcodeop custom3.rd.rs1;\ndefine pcodeop custom3.rd.rs1.rs2;\n\n:custom0 is op0001=0x3 & op0204=0x2 & op0506=0x0 & (op1214=0x0 | op1214=0x1 | op1214=0x5)\n{\n\tcustom0();\n}\n\n:custom0.rs1 rs1 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x2 & rs1\n{\n\tcustom0.rs1(rs1);\n}\n\n:custom0.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x3 & rs1 & rs2\n{\n\tcustom0.rs1.rs2(rs1, rs2);\n}\n\n:custom0.rd rd is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x4 & rd\n{\n\trd = custom0.rd();\n}\n\n:custom0.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x6 & rd & rs1\n{\n\trd = custom0.rd.rs1(rs1);\n}\n\n:custom0.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x7 & rd & rs1 & rs2\n{\n\trd = custom0.rd.rs1.rs2(rs1, rs2);\n}\n\n\n:custom1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & (op1214=0x0 | op1214=0x1 | op1214=0x5)\n{\n\tcustom1();\n}\n\n:custom1.rs1 rs1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x2 & rs1\n{\n\tcustom1.rs1(rs1);\n}\n\n:custom1.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x3 & rs1 & rs2\n{\n\tcustom1.rs1.rs2(rs1, rs2);\n}\n\n:custom1.rd rd is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x4 & rd\n{\n\trd = custom1.rd();\n}\n\n:custom1.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x6 & rd & rs1\n{\n\trd = custom1.rd.rs1(rs1);\n}\n\n:custom1.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x7 & rd & rs1 & rs2\n{\n\trd = custom1.rd.rs1.rs2(rs1, rs2);\n}\n\n\n#TODO handle RV128 for custom-2/custom-3\n\n:custom2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & (op1214=0x0 | op1214=0x1 | op1214=0x5)\n{\n\tcustom2();\n}\n\n:custom2.rs1 rs1 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x2 & rs1\n{\n\tcustom2.rs1(rs1);\n}\n\n:custom2.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x3 & rs1 & rs2\n{\n\tcustom2.rs1.rs2(rs1, rs2);\n}\n\n:custom2.rd rd is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x4 & rd\n{\n\trd = custom2.rd();\n}\n\n:custom2.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x6 & rd & rs1\n{\n\trd = custom2.rd.rs1(rs1);\n}\n\n:custom2.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x7 & rd & rs1 & rs2\n{\n\trd = custom2.rd.rs1.rs2(rs1, rs2);\n}\n\n\n:custom3 is op0001=0x3 & op0204=0x6 & op0506=0x3 & (op1214=0x0 | op1214=0x1 | op1214=0x5)\n{\n\tcustom3();\n}\n\n:custom3.rs1 rs1 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x2 & rs1\n{\n\tcustom3.rs1(rs1);\n}\n\n:custom3.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x3 & rs1 & rs2\n{\n\tcustom3.rs1.rs2(rs1, rs2);\n}\n\n:custom3.rd rd is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x4 & rd\n{\n\trd = custom3.rd();\n}\n\n:custom3.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x6 & rd & rs1\n{\n\trd = custom3.rd.rs1(rs1);\n}\n\n:custom3.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x7 & rd & rs1 & rs2\n{\n\trd = custom3.rd.rs1.rs2(rs1, rs2);\n}\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.ilp32d.slaspec", "content": "define endian=little;\n\n@define XLEN 4\n@define XLEN2 8\n@define FLEN 8\n\n@define CONTEXTLEN 4\n\n@define ADDRSIZE \"32\"\n@define FPSIZE \"64\"\n\n@include \"riscv.reg.sinc\"\n@include \"riscv.table.sinc\"\n@include \"riscv.instr.sinc\"\n\n# include placeholder decode for *some* custom instructions\n@include \"riscv.custom.sinc\"\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.instr.sinc", "content": "# This is just a top level to include the standards\n\n@if ADDRSIZE == \"32\" || ADDRSIZE == \"64\" || ADDRSIZE == \"128\"\n@include \"riscv.rv32i.sinc\"\n@include \"riscv.rv32a.sinc\"\n@include \"riscv.rv32m.sinc\"\n@include \"riscv.rv32b.sinc\"\n@include \"riscv.rv32p.sinc\"\n@include \"riscv.rv32k.sinc\"\n\n@if FPSIZE == \"32\" || FPSIZE == \"64\" || FPSIZE == \"128\"\n@include \"riscv.rv32f.sinc\"\n@endif\n\n@if FPSIZE == \"64\" || FPSIZE == \"128\"\n@include \"riscv.rv32d.sinc\"\n@endif\n\n@if FPSIZE == \"128\"\n@include \"riscv.rv32q.sinc\"\n@endif\n@endif\n\n@if ADDRSIZE == \"64\" || ADDRSIZE == \"128\"\n@include \"riscv.rv64i.sinc\"\n@include \"riscv.rv64a.sinc\"\n@include \"riscv.rv64m.sinc\"\n@include \"riscv.rv64b.sinc\"\n@include \"riscv.rv64p.sinc\"\n\n@if FPSIZE == \"32\" || FPSIZE == \"64\" || FPSIZE == \"128\"\n@include \"riscv.rv64f.sinc\"\n@endif\n\n@if FPSIZE == \"64\" || FPSIZE == \"128\"\n@include \"riscv.rv64d.sinc\"\n@endif\n\n@if FPSIZE == \"128\"\n@include \"riscv.rv64q.sinc\"\n@endif\n@endif\n\n@include \"riscv.csr.sinc\"\n@include \"riscv.priv.sinc\"\n@include \"riscv.rvc.sinc\"\n@include \"riscv.rvv.sinc\"\n@include \"riscv.zi.sinc\"\n\n# todos that may be possible, mostly just artifacts from my\n# script to generate the initial SELIGH\n\n\n#TODO ALIAS\n# add d,CU,CV 00009002 0000f003 ALIAS (0, 0) \n#:add crd,crs1,crs2 is crd & crs2 & crs1 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1\n#{\n#}\n\n#TODO ALIAS\n# add d,CV,CU 00009002 0000f003 ALIAS (0, 0) \n#:add crd,crs2,crs1 is crd & crs1 & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1\n#{\n#}\n\n#TODO ALIAS\n# add d,CU,Co 00000001 0000e003 ALIAS (0, 0) \n#:add crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x0\n#{\n#}\n\n#TODO ALIAS\n# add Ct,Cc,CK 00000000 0000e003 ALIAS (0, 0) \n#:add cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0\n#{\n#}\n\n#TODO ALIAS\n# add Cc,Cc,CL 00006101 0000ef83 ALIAS (0, 0) \n#TODO sp,sp,caddi16spimm caddi16spimm & sp & cop0001=0x1 & cop1315=0x3\n#:add sp,sp,caddi16spimm is caddi16spimm & sp & cop0001=0x1 & cop1315=0x3\n#{\n#}\n\n#TODO ALIAS\n# add d,s,j 00000013 0000707f ALIAS (0, 0) \n#:add rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0\n#{\n#}\n\n#TODO ALIAS\n# addi Ct,Cc,CK 00000000 0000e003 ALIAS (0, 0) \n#:addi cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0\n#{\n#}\n\n#TODO ALIAS\n# addi d,CU,Cj 00000001 0000e003 ALIAS (0, 0) \n#:addi crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x0\n#{\n#}\n\n#TODO ALIAS\n# addi d,CU,z 00000001 0000f07f ALIAS (0, 0) \n#:addi crd,crs1,zero is crd & zero & crs1 & cop0001=0x1 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0\n#{\n#}\n\n#TODO ALIAS\n# addi Cc,Cc,CL 00006101 0000ef83 ALIAS (0, 0) \n#TODO sp,sp,caddi16spimm caddi16spimm & sp & cop0001=0x1 & cop1315=0x3\n#:addi sp,sp,caddi16spimm is caddi16spimm & sp & cop0001=0x1 & cop1315=0x3\n#{\n#}\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# addiw d,CU,Co 00002001 0000e003 ALIAS (64, 0) \n#TODO 32 64\n#:addiw crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# addw Cs,Cw,Ct 00009c21 0000fc63 ALIAS (64, 0) \n#:addw cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# addw Cs,Ct,Cw 00009c21 0000fc63 ALIAS (64, 0) \n#:addw cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# addw d,CU,Co 00002001 0000e003 ALIAS (64, 0) \n#TODO crd,crs1,cimmI crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1\n#:addw crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# addw d,s,j 0000001b 0000707f ALIAS (64, 0) \n#:addw rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# and Cs,Cw,Ct 00008c61 0000fc63 ALIAS (0, 0) \n#:and cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3\n#{\n#}\n\n#TODO ALIAS\n# and Cs,Ct,Cw 00008c61 0000fc63 ALIAS (0, 0) \n#:and cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3\n#{\n#}\n\n#TODO ALIAS\n# and Cs,Cw,Co 00008801 0000ec03 ALIAS (0, 0) \n#:and cr0709s,cd0709s,cimmI is cd0709s & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2\n#{\n#}\n\n#TODO ALIAS\n# and d,s,j 00007013 0000707f ALIAS (0, 0) \n#:and rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7\n#{\n#}\n\n#TODO ALIAS\n# andi Cs,Cw,Co 00008801 0000ec03 ALIAS (0, 0) \n#:andi cr0709s,cd0709s,cimmI is cd0709s & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2\n#{\n#}\n\n#TODO ALIAS\n# beq Cs,Cz,Cp 0000c001 0000e003 CONDBRANCH|ALIAS (0, 0) \n#:beq cr0709s,zero,cbimm is cop0206=0 & cbimm & zero & cr0709s & cop0001=0x1 & cop1315=0x6\n#{\n#}\n\n#TODO ALIAS\n# beqz Cs,Cp 0000c001 0000e003 CONDBRANCH|ALIAS (0, 0) \n#:beqz cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x6\n#{\n#}\n\n#TODO ALIAS\n# beqz s,p 00000063 01f0707f CONDBRANCH|ALIAS (0, 0) \n#:beqz rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0 & op2024=0x0\n#{\n#}\n\n#TODO ALIAS\n# bgez s,p 00005063 01f0707f CONDBRANCH|ALIAS (0, 0) \n#:bgez rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 & op2024=0x0\n#{\n#}\n\n#TODO ALIAS\n# bgt t,s,p 00004063 0000707f CONDBRANCH|ALIAS (0, 0) \n#:bgt rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4\n#{\n#}\n\n#TODO ALIAS\n# bgtu t,s,p 00006063 0000707f CONDBRANCH|ALIAS (0, 0) \n#:bgtu rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6\n#{\n#}\n\n#TODO ALIAS\n# bgtz t,p 00004063 000ff07f CONDBRANCH|ALIAS (0, 0) \n#:bgtz rs2,immSB is immSB & rs2 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 & op1519=0x0\n#{\n#}\n\n#TODO ALIAS\n# ble t,s,p 00005063 0000707f CONDBRANCH|ALIAS (0, 0) \n#:ble rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5\n#{\n#}\n\n#TODO ALIAS\n# bleu t,s,p 00007063 0000707f CONDBRANCH|ALIAS (0, 0) \n#:bleu rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7\n#{\n#}\n\n#TODO ALIAS\n# blez t,p 00005063 000ff07f CONDBRANCH|ALIAS (0, 0) \n#:blez rs2,immSB is immSB & rs2 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 & op1519=0x0\n#{\n#}\n\n#TODO ALIAS\n# bltz s,p 00004063 01f0707f CONDBRANCH|ALIAS (0, 0) \n#:bltz rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 & op2024=0x0\n#{\n#}\n\n#TODO ALIAS\n# bne Cs,Cz,Cp 0000e001 0000e003 CONDBRANCH|ALIAS (0, 0) \n#:bne cr0709s,zero,cbimm is cop0206=0 & cbimm & zero & cr0709s & cop0001=0x1 & cop1315=0x7\n#{\n#}\n\n#TODO ALIAS\n# bnez Cs,Cp 0000e001 0000e003 CONDBRANCH|ALIAS (0, 0) \n#:bnez cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x7\n#{\n#}\n\n#TODO ALIAS\n# bnez s,p 00001063 01f0707f CONDBRANCH|ALIAS (0, 0) \n#:bnez rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1 & op2024=0x0\n#{\n#}\n\n\n#@if defined(RISCV128I)\n#TODO 128\n#:c.lq\n#@endif\n\n#TODO ALIAS\n# c.nop 00000001 0000ffff ALIAS (0, 0) \n#:c.nop is cop0001=0x1 & cop1315=0x0 & cop0212=0x0\n#{\n#}\n\n#TODO ALIAS\n# c.nop Cj 00000001 0000ef83 ALIAS (0, 0) \n#:c.nop cimmI is cimmI & cop0001=0x1 & cop1315=0x0 & cop0711=0x0\n#{\n#}\n\n#TODO MACRO\n# call d,c 00030000 00000015 MACRO (0, 64) \n\n#TODO MACRO\n# call c 00008080 00000015 MACRO (0, 64) \n\n#TODO ALIAS\n# csrc E,s 00003073 00007fff ALIAS (0, 0) \n#:csrc csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrc E,Z 00007073 00007fff ALIAS (0, 0) \n#:csrc csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrci E,Z 00007073 00007fff ALIAS (0, 0) \n#:csrci csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrr d,E 00002073 000ff07f ALIAS (0, 0) \n#:csrr rd,csr is csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrrc d,E,Z 00007073 0000707f ALIAS (0, 0) \n#:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7\n#{\n#}\n\n#TODO ALIAS\n# csrrs d,E,Z 00006073 0000707f ALIAS (0, 0) \n#:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6\n#{\n#}\n\n#TODO ALIAS\n# csrrw d,E,Z 00005073 0000707f ALIAS (0, 0) \n#:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5\n#{\n#}\n\n#TODO ALIAS\n# csrs E,s 00002073 00007fff ALIAS (0, 0) \n#:csrs csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrs E,Z 00006073 00007fff ALIAS (0, 0) \n#:csrs csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrsi E,Z 00006073 00007fff ALIAS (0, 0) \n#:csrsi csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrw E,s 00001073 00007fff ALIAS (0, 0) \n#:csrw csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrw E,Z 00005073 00007fff ALIAS (0, 0) \n#:csrw csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0\n#{\n#}\n\n#TODO ALIAS\n# csrwi E,Z 00005073 00007fff ALIAS (0, 0) \n#:csrwi csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0\n#{\n#}\n\n\n\n#TODO ALIAS\n# ebreak 00009002 0000ffff ALIAS (0, 0) \n#:ebreak is cop0001=0x2 & cop1315=0x4 & cop0212=0x400\n#{\n#}\n\n#TODO ALIAS\n# fabs.q D,U 26002053 fe00707f ALIAS (0, 0) \n#:fabs.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13 & op2024=0x0\n#{\n#}\n\n#TODO ALIAS\n# fence 0ff0000f ffffffff ALIAS (0, 0) \n#:fence is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1527=0x1fe0\n#{\n#}\n\n#TODO ALIAS\n# fence.tso 8330000f ffffffff ALIAS (0, 0) \n#:fence.tso is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x8 & op0711=0x0 & op1527=0x660\n#{\n#}\n\n#TODO SEE fle.d\n# fge.d d,T,S a2000053 fe00707f SIMPLE (0, 0) \n# :fge.d rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51\n# {\n# }\n\n#TODO SEE fle.q\n# fge.q d,T,S a6000053 fe00707f SIMPLE (0, 0) \n# :fge.q rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53\n# {\n# }\n\n#TODO SEE fle.s\n# fge.s d,T,S a0000053 fe00707f SIMPLE (0, 0) \n# :fge.s rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50\n# {\n# }\n\n#TODO SEE flt.d\n# fgt.d d,T,S a2001053 fe00707f SIMPLE (0, 0) \n# :fgt.d rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51\n# {\n# }\n\n#TODO SEE flt.q\n# fgt.q d,T,S a6001053 fe00707f SIMPLE (0, 0) \n# :fgt.q rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53\n# {\n# }\n\n#TODO SEE flt.s\n# fgt.s d,T,S a0001053 fe00707f SIMPLE (0, 0) \n# :fgt.s rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50\n# {\n# }\n\n#TODO ALIAS\n# fld D,Cn(Cc) 00002002 0000e003 QWORD|DREF|ALIAS (0, 8) \n#TODO cfr0711,cldspimm(sp) cldspimm & cfr0711 & sp & cop0001=0x2 & cop1315=0x1\n#:fld cfr0711,cldspimm(sp) is cldspimm & cfr0711 & sp & cop0001=0x2 & cop1315=0x1\n#{\n#}\n\n#TODO ALIAS\n# fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF|ALIAS (0, 8) \n#TODO 32 64\n#:fld cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm\n#{\n#}\n\n#TODO MACRO\n# fld D,A,s 00000000 00000010 MACRO (0, 64) \n\n#TODO MACRO\n# flq D,A,s 00000000 00000011 MACRO (0, 64) \n\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# flw D,Cm(Cc) 00006002 0000e003 DWORD|DREF|ALIAD (32, 4) \n#TODO cfr0711,clwspimm(sp) cfr0711 & clwspimm & sp & cop0001=0x2 & cop1315=0x3\n#:flw cfr0711,clwspimm(sp) is cfr0711 & clwspimm & sp & cop0001=0x2 & cop1315=0x3\n#{\n#}\n#@endif\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF|ALIAD (32, 4) \n#:flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm\n#{\n#}\n#@endif\n\n#TODO MACRO\n# flw D,A,s 00000000 0000000f MACRO (0, 64) \n\n#TODO ALIAS\n# fmv.q D,U 26000053 fe00707f ALIAS (0, 0) \n#:fmv.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13 & op2024=0x0\n#{\n#}\n\n\n#TODO SEE fmv.w.x\n# fmv.s.x D,s f0000053 fff0707f SIMPLE (0, 0) \n# :fmv.s.x fr0711,rs1 is fr0711 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0\n# {\n# }\n\n#TODO SEE fmv.x.w\n# fmv.x.s d,S e0000053 fff0707f SIMPLE (0, 0) \n# :fmv.x.s rd,fr1519 is fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0\n# {\n# }\n\n\n#TODO ALIAS\n# fneg.q D,U 26001053 fe00707f ALIAS (0, 0) \n#:fneg.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13 & op2024=0x0\n#{\n#}\n\n#TODO SEE frcsr\n# frsr d 00302073 fffff07f SIMPLE (0, 0) \n# :frsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60\n# {\n# }\n\n#TODO ALIAS\n# fsd CT,CN(Cc) 0000a002 0000e003 QWORD|DREF|ALIAS (0, 8) \n#TODO cfr0206,csdspimm(sp) csdspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x5\n#:fsd cfr0206,csdspimm(sp) is csdspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x5\n#{\n#}\n\n#TODO ALIAS\n# fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF|ALIAS (0, 8) \n#TODO 32 64\n#:fsd cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm\n#{\n#}\n\n#TODO MACRO\n# fsd T,A,s 00000000 00000013 MACRO (0, 64) \n\n#TODO MACRO\n# fsq T,A,s 00000000 00000014 MACRO (0, 64) \n\n#TODO SEE fscsr\n# fssr s 00301073 fff07fff SIMPLE (0, 0) \n# :fssr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3\n# {\n# }\n\n#TODO SEE fscsr\n# fssr d,s 00301073 fff0707f SIMPLE (0, 0) \n# :fssr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3\n# {\n# }\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# fsw CT,CM(Cc) 0000e002 0000e003 DWORD|DREF|ALIAD (32, 4) \n#TODO cfr0206,cswspimm(sp) cswspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x7\n#:fsw cfr0206,cswspimm(sp) is cswspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x7\n#{\n#}\n#@endif\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF|ALIAD (32, 4) \n#:fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm\n#{\n#}\n#@endif\n\n#TODO MACRO\n# fsw T,A,s 00000000 00000012 MACRO (0, 64) \n\n\n#TODO ALIAS\n# j Ca 0000a001 0000e003 BRANCH|ALIAS (0, 0) \n#:j cjimm is cjimm & cop0001=0x1 & cop1315=0x5\n#{\n#}\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# jal Ca 00002001 0000e003 JSR|ALIAS (32, 0) \n#:jal cjimm is cjimm & cop0001=0x1 & cop1315=0x1\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# jal a 000000ef 00000fff JSR|ALIAS (0, 0) \n#:jal immUJ is immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x1\n#{\n#}\n\n#TODO ALIAS\n# jalr d 00009002 0000f07f JSR|ALIAS (0, 0) \n#:jalr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1\n#{\n#}\n\n#TODO ALIAS\n# jalr s 000000e7 fff07fff JSR|ALIAS (0, 0) \n#:jalr rs1 is rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 & op2031=0x0\n#{\n#}\n\n#TODO ALIAS\n# jalr o(s) 000000e7 00007fff JSR|ALIAS (0, 0) \n#:jalr immI(rs1) is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1\n#{\n#}\n\n#TODO ALIAS\n# jalr s,j 000000e7 00007fff JSR|ALIAS (0, 0) \n#:jalr rs1,immI is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1\n#{\n#}\n\n#TODO ALIAS\n# jalr d,s 00000067 fff0707f JSR|ALIAS (0, 0) \n#:jalr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op2031=0x0\n#{\n#}\n\n#TODO SEE jalr\n# jalr d,o(s) 00000067 0000707f JSR (0, 0) \n# :jalr rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0\n# {\n# }\n\n#TODO ALIAS\n# jr d 00008002 0000f07f BRANCH|ALIAS (0, 0) \n#:jr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0\n#{\n#}\n\n#TODO ALIAS\n# jr s,j 00000067 00007fff BRANCH|ALIAS (0, 0) \n#:jr rs1,immI is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0\n#{\n#}\n\n#TODO MACRO\n# jump c,s 00000000 00000015 MACRO (0, 64) \n\n#TODO MACRO\n# la d,B 00000000 00000000 MACRO (0, 64) \n\n#TODO MACRO\n# la.tls.gd d,A 00000000 00000002 MACRO (0, 64) \n\n#TODO MACRO\n# la.tls.ie d,A 00000000 00000003 MACRO (0, 64) \n\n#TODO MACRO\n# lb d,A 00000000 00000004 MACRO (0, 64) \n\n#TODO MACRO\n# lbu d,A 00000000 00000005 MACRO (0, 64) \n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# ld d,Cn(Cc) 00006002 0000e003 QWORD|DREF|ALIAS (64, 8) \n#TODO crd,cldspimm(sp) crd & cldspimm & sp & cop0001=0x2 & cop1315=0x3\n#:ld crd,cldspimm(sp) is crd & cldspimm & sp & cop0001=0x2 & cop1315=0x3\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF|ALIAS (64, 8) \n#TODO 64 128\n#:ld cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO MACRO\n# ld d,A 00000000 0000000a MACRO (64, 64) \n#@endif\n\n#TODO MACRO\n# lh d,A 00000000 00000006 MACRO (0, 64) \n\n#TODO MACRO\n# lhu d,A 00000000 00000007 MACRO (0, 64) \n\n#TODO ALIAS\n# li d,Cv 00006001 0000e003 ALIAS (0, 0) \n#TODO crd,cbigimm crd & cbigimm & cop0001=0x1 & cop1315=0x3\n#:li crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3\n#{\n#}\n\n#TODO ALIAS\n# li d,Co 00004001 0000e003 ALIAS (0, 0) \n#:li crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x2\n#{\n#}\n\n#TODO MACRO\n# li d,I 00000000 00000017 MACRO (0, 64) \n\n#TODO MACRO\n# lla d,B 00000000 00000001 MACRO (0, 64) \n\n#TODO ALIAS\n# lui d,Cu 00006001 0000e003 ALIAS (0, 0) \n#:lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3\n#{\n#}\n\n#TODO ALIAS\n# lw d,Cm(Cc) 00004002 0000e003 DWORD|DREF|ALIAD (0, 4) \n#:lw crd,clwspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm\n#{\n#}\n\n#TODO ALIAS\n# lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF|ALIAD (0, 4) \n#:lw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm\n#{\n#}\n\n#TODO MACRO\n# lw d,A 00000000 00000008 MACRO (0, 64) \n\n#@if defined(RISCV64I)\n#TODO MACRO\n# lwu d,A 00000000 00000009 MACRO (64, 64) \n#@endif\n\n#TODO ALIAS\n# move d,CV 00008002 0000f003 ALIAS (0, 0) \n#TODO crd,crs2 crd & crs2 & cop0001=0x2 & cop1315=0x4\n#:move crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0\n#{\n#}\n\n#TODO ALIAS\n# move d,s 00000013 fff0707f ALIAS (0, 0) \n#:move rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0\n#{\n#}\n\n#TODO ALIAS\n# mv d,CV 00008002 0000f003 ALIAS (0, 0) \n#:mv crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0\n#{\n#}\n\n#TODO ALIAS\n# nop 00000001 0000ffff ALIAS (0, 0) \n#:nop is cop0001=0x1 & cop1315=0x0 & cop0212=0x0\n#{\n#}\n\n#TODO ALIAS\n# or Cs,Cw,Ct 00008c41 0000fc63 ALIAS (0, 0) \n#:or cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3\n#{\n#}\n\n#TODO ALIAS\n# or Cs,Ct,Cw 00008c41 0000fc63 ALIAS (0, 0) \n#:or cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3\n#{\n#}\n\n#TODO ALIAS\n# or d,s,j 00006013 0000707f ALIAS (0, 0) \n#:or rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6\n#{\n#}\n\n#TODO ALIAS\n# rdcycle d c0002073 fffff07f ALIAS (0, 0) \n#:rdcycle rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18000\n#{\n#}\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# rdcycleh d c8002073 fffff07f ALIAS (32, 0) \n#:rdcycleh rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19000\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# rdinstret d c0202073 fffff07f ALIAS (0, 0) \n#:rdinstret rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18040\n#{\n#}\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# rdinstreth d c8202073 fffff07f ALIAS (32, 0) \n#:rdinstreth rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19040\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# rdtime d c0102073 fffff07f ALIAS (0, 0) \n#:rdtime rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18020\n#{\n#}\n\n#@if defined(RISCV32I)\n#TODO ALIAS\n# rdtimeh d c8102073 fffff07f ALIAS (32, 0) \n#:rdtimeh rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19020\n#{\n#}\n#@endif\n\n#TODO MACRO\n# sb t,A,s 00000000 0000000b MACRO (0, 64) \n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# sd CV,CN(Cc) 0000e002 0000e003 QWORD|DREF|ALIAS (64, 8) \n#TODO crs2,csdspimm(sp) csdspimm & crs2 & sp & cop0001=0x2 & cop1315=0x7\n#:sd crs2,csdspimm(sp) is csdspimm & crs2 & sp & cop0001=0x2 & cop1315=0x7\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF|ALIAS (64, 8) \n#TODO 64 128\n#:sd cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO MACRO\n# sd t,A,s 00000000 0000000e MACRO (64, 64) \n#@endif\n\n#TODO ALIAS\n# seqz d,s 00103013 fff0707f ALIAS (0, 0) \n#:seqz rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 & op2031=0x1\n#{\n#}\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# sext.w d,CU 00002001 0000f07f ALIAS (64, 0) \n#TODO crd,crs1 crd & crs1 & cop0001=0x1 & cop1315=0x1\n#:sext.w crd,crs1 is crd & crs1 & cop0001=0x1 & cop1315=0x1 & cop0206=0x0 & cop1212=0x0\n#{\n#}\n#@endif\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# sext.w d,s 0000001b fff0707f ALIAS (64, 0) \n#:sext.w rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0x0\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# sfence.vma 12000073 ffffffff ALIAS (0, 0) \n#:sfence.vma is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2400\n#{\n#}\n\n#TODO ALIAS\n# sfence.vma s 12000073 fff07fff ALIAS (0, 0) \n#:sfence.vma rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x120\n#{\n#}\n\n#TODO ALIAS\n# sgt d,t,s 00002033 fe00707f ALIAS (0, 0) \n#:sgt rd,rs2,rs1 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0\n#{\n#}\n\n#TODO ALIAS\n# sgtu d,t,s 00003033 fe00707f ALIAS (0, 0) \n#:sgtu rd,rs2,rs1 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0\n#{\n#}\n\n#TODO ALIAS\n# sgtz d,t 00002033 fe0ff07f ALIAS (0, 0) \n#:sgtz rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 & op1519=0x0\n#{\n#}\n\n#TODO MACRO\n# sh t,A,s 00000000 0000000c MACRO (0, 64) \n\n#TODO ALIAS\n# sll d,CU,C> 00000002 0000e003 ALIAS (0, 0) \n#:sll crd,crs1,c6imm is crd & c6imm & crs1 & cop0001=0x2 & cop1315=0x0\n#{\n#}\n\n#TODO ALIAS\n# sll d,s,> 00001013 fc00707f ALIAS (0, 0) \n#:sll rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0\n#{\n#}\n\n#TODO ALIAS\n# slli d,CU,C> 00000002 0000e003 ALIAS (0, 0) \n#:slli crd,crs1,c6imm is crd & c6imm & crs1 & cop0001=0x2 & cop1315=0x0\n#{\n#}\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# sllw d,s,< 0000101b fe00707f ALIAS (64, 0) \n#:sllw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# slt d,s,j 00002013 0000707f ALIAS (0, 0) \n#:slt rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2\n#{\n#}\n\n#TODO ALIAS\n# sltu d,s,j 00003013 0000707f ALIAS (0, 0) \n#:sltu rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3\n#{\n#}\n\n#TODO ALIAS\n# sltz d,s 00002033 fff0707f ALIAS (0, 0) \n#:sltz rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 & op2024=0x0\n#{\n#}\n\n#TODO ALIAS\n# snez d,t 00003033 fe0ff07f ALIAS (0, 0) \n#:snez rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 & op1519=0x0\n#{\n#}\n\n#TODO ALIAS\n# sra Cs,Cw,C> 00008401 0000ec03 ALIAS (0, 0) \n#:sra cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1\n#{\n#}\n\n#TODO ALIAS\n# sra d,s,> 40005013 fc00707f ALIAS (0, 0) \n#:sra rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10\n#{\n#}\n\n#TODO ALIAS\n# srai Cs,Cw,C> 00008401 0000ec03 ALIAS (0, 0) \n#:srai cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1\n#{\n#}\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# sraw d,s,< 4000501b fe00707f ALIAS (64, 0) \n#:sraw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20\n#{\n#}\n#@endif\n\n\n#TODO ALIAS\n# srl Cs,Cw,C> 00008001 0000ec03 ALIAS (0, 0) \n#:srl cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0\n#{\n#}\n\n#TODO ALIAS\n# srl d,s,> 00005013 fc00707f ALIAS (0, 0) \n#:srl rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0\n#{\n#}\n\n#TODO ALIAS\n# srli Cs,Cw,C> 00008001 0000ec03 ALIAS (0, 0) \n#:srli cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0\n#{\n#}\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# srlw d,s,< 0000501b fe00707f ALIAS (64, 0) \n#:srlw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# sub Cs,Cw,Ct 00008c01 0000fc63 ALIAS (0, 0) \n#:sub cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3\n#{\n#}\n\n#@if defined(RISCV64I)\n#TODO ALIAS\n# subw Cs,Cw,Ct 00009c01 0000fc63 ALIAS (64, 0) \n#:subw cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7\n#{\n#}\n#@endif\n\n#TODO ALIAS\n# sw CV,CM(Cc) 0000c002 0000e003 DWORD|DREF|ALIAD (0, 4) \n#:sw crs2,cswspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm\n#{\n#}\n\n#TODO ALIAS\n# sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF|ALIAD (0, 4) \n#:sw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm\n#{\n#}\n\n#TODO MACRO\n# sw t,A,s 00000000 0000000d MACRO (0, 64) \n\n#TODO MACRO\n# tail c 00030000 00000015 MACRO (0, 64) \n\n#TODO ALIAS\n# unimp 00000000 0000ffff ALIAS (0, 0) \n#:unimp is cop0001=0x0 & cop1315=0x0 & cop0212=0x0\n#{\n#}\n\n\n#TODO ALIAS\n# xor Cs,Cw,Ct 00008c21 0000fc63 ALIAS (0, 0) \n#:xor cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3\n#{\n#}\n\n#TODO ALIAS\n# xor Cs,Ct,Cw 00008c21 0000fc63 ALIAS (0, 0) \n#:xor cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3\n#{\n#}\n\n#TODO ALIAS\n# xor d,s,j 00004013 0000707f ALIAS (0, 0) \n#:xor rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4\n#{\n#}\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.ldefs", "content": "\n\n\n\n \n RISC-V 64 little default\n \n \n \n \n \n \n \n \n RISC-V 32 little default\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.lp64d.slaspec", "content": "define endian=little;\n\n@define XLEN 8\n@define XLEN2 16\n@define FLEN 8\n\n@define CONTEXTLEN 4\n\n@define ADDRSIZE \"64\"\n@define FPSIZE \"64\"\n\n@include \"riscv.reg.sinc\"\n@include \"riscv.table.sinc\"\n@include \"riscv.instr.sinc\"\n\n@include \"riscv.rv64k.sinc\" # current encoding is in custom space\n@include \"riscv.custom.sinc\"\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.priv.sinc", "content": "# RISC-V Privileged Instructions\n\ndefine pcodeop wfi;\ndefine pcodeop sfence.vm;\ndefine pcodeop sfence.vma;\n\n# Trap-Return\n\n\n# dret 7b200073 ffffffff SIMPLE (0, 0) \n:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640\n{\n\treturn [dpc];\n}\n\n# hret 20200073 ffffffff SIMPLE (0, 0)\n# deprecated instruction in latest spec\n#:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040\n\n# mret 30200073 ffffffff SIMPLE (0, 0) \n:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040\n{\n\treturn [mepc];\n}\n\n# sret 10200073 ffffffff SIMPLE (0, 0) \n:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040\n{\n\treturn [sepc];\n}\n\n\n# uret 00200073 ffffffff SIMPLE (0, 0) \n:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40\n{\n\treturn [uepc];\n}\n\n\n# Interrupt-Management\n\n# wfi 10500073 ffffffff SIMPLE (0, 0) \n:wfi is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20a0\n{\n\twfi();\n}\n\n\n# Supervisor Memory-Management\n\n# sfence.vm 10400073 ffffffff SIMPLE (0, 0) \n:sfence.vm is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2080\n{\n\tsfence.vm();\n}\n\n# sfence.vm s 10400073 fff07fff SIMPLE (0, 0) \n:sfence.vm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x104\n{\n\tsfence.vm(rs1);\n}\n\n# sfence.vma s,t 12000073 fe007fff SIMPLE (0, 0) \n:sfence.vma rs1,rs2 is rs2 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2531=0x9\n{\n\tsfence.vma(rs1, rs2);\n}\n\n\n\n\n# Hypervisor Memory-Management\n#TODO move to rv32h and rv64h?\n\n:hlv.b rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x0\n{\n\trd = sext(*[ram]:1 rs1);\n}\n\n:hlv.bu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x1\n{\n\trd = zext(*[ram]:1 rs1);\n}\n\n:hlv.h rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x0\n{\n\trd = sext(*[ram]:2 rs1);\n}\n\n:hlv.hu rd,rs1, is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x1\n{\n\trd = zext(*[ram]:2 rs1);\n}\n\n:hlvx.hu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x3\n{\n\trd = zext(*[ram]:2 rs1);\n}\n\n:hlv.w rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x0\n{\n\tassignW(rd, *[ram]:4 rs1);\n}\n\n:hlvx.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x3\n{\n\tzassignW(rd, *[ram]:4 rs1);\n}\n\n:hsv.b rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x31 & op0711=0x0 & rs1 & rs2\n{\n\t*[ram]:1 rs1 = rs2:1;\n}\n\n:hsv.h rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x33 & op0711=0x0 & rs1 & rs2\n{\n\t*[ram]:2 rs1 = rs2:2;\n}\n\n:hsv.w rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x35 & op0711=0x0 & rs1 & rs2\n{\n\t*[ram]:4 rs1 = rs2:4;\n}\n\n@if ADDRSIZE == \"64\"\n\n:hlv.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x1\n{\n\trd = zext(*[ram]:4 rs1);\n}\n\n:hlv.d rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x36 & rs1 & rd & op2024=0x0\n{\n\trd = *[ram]:8 rs1;\n}\n\n:hsv.d rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x37 & op0711=0x0 & rs1 & rs2\n{\n\t*[ram]:8 rs1 = rs2;\n}\n\n@endif\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.reg.sinc", "content": "\ndefine alignment=2;\n\ndefine space ram type=ram_space size=$(XLEN) default;\ndefine space register type=register_space size=4;\n\ndefine space csreg type=ram_space size=2 wordsize=$(XLEN); # really 12bit space, for 4096 registers\n\ndefine register offset=0x100 size=$(CONTEXTLEN) [ CONTEXT ];\n\ndefine register offset=0x1000 size=$(XLEN) [ pc ];\n\n\n# 08-31 reserved\n# 05-07 frm\n# 000 - RNE - round to nearest, ties to even\n# 001 - RTZ - round towards zero\n# 010 - RDN - round down (towards -inf)\n# 011 - RUP - round up (towards +inf)\n# 100 - RMM - round to nearest, ties to max magnitude\n# 101 - invalid\n# 110 - invalid\n# 111 - DYN - in rm field, selects dynamic rounding mode\n# in rounding mode register, invalid\n# 04 NV - invalid operation\n# 03 DZ - divide by zero\n# 02 OF - overflow\n# 01 UF - underflow\n# 00 NX - inexact\n#define register offset=0x1008 size=4 [ fcsr ];\n\n#TODO FIXME\n#TODO This is really broken\n#NOTE This is stolen from ppc_common, so it has something similar\ndefine register offset=0x1010 size=$(XLEN) [ RESERVE_ADDRESS ];\ndefine register offset=0x1018 size=1 [ RESERVE ];\ndefine register offset=0x101C size=1 [ RESERVE_LENGTH ];\n#TODO FIXME\n\n#ATTN RV32E is the same instruction-set encoding, but only defines x0-x15\n# x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15\n# z ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5\n# x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31\n# a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6\n# register numbers 0x1000-0x101f\ndefine register offset=0x2000 size=$(XLEN) [ zero ra sp gp tp t0 t1 t2\n \t\t\t \t \t s0 s1 a0 a1 a2 a3 a4 a5\n\t\t\t\t \t a6 a7 s2 s3 s4 s5 s6 s7\n\t\t\t\t \t s8 s9 s10 s11 t3 t4 t5 t6 ];\n\n# register numbers 0x1020-0x103f\ndefine register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7\n \t\t\t \t \t fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5\n\t\t\t\t \t fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7\n\t\t\t\t \t fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];\n\n#TODO fix\n@define VLEN \"32\"\ndefine register offset=0x4000 size=$(VLEN) [ v0 v1 v2 v3 v4 v5 v6 v7\n \t\t\t \t\t v8 v9 v10 v11 v12 v13 v14 v15\n\t\t\t\t\t v16 v17 v18 v19 v20 v21 v22 v23\n\t\t\t\t\t v24 v25 v26 v27 v28 v29 v30 v31 ];\n\n \n # SEE 3.1.1 Machine ISA Register misa\n# (MXLEN-1, MXLEN-2) MXL - Machine XLEN {1: 32, 2: 64, 3: 128}\n# Bit Character Description\n# 0 A Atomic extension\n# 1 B Tentatively reserved for Bit-Manipulation extension\n# 2 C Compressed extension\n# 3 D Double-precision floating-point extension\n# 4 E RV32E base ISA\n# 5 F Single-precision floating-point extension\n# 6 G Additional standard extensions present\n# 7 H Hypervisor extension\n# 8 I RV32I/64I/128I base ISA\n# 9 J Tentatively reserved for Dynamically Translated Languages extension\n# 10 K Reserved\n# 11 L Tentatively reserved for Decimal Floating-Point extension\n# 12 M Integer Multiply/Divide extension\n# 13 N User-level interrupts supported\n# 14 O Reserved\n# 15 P Tentatively reserved for Packed-SIMD extension\n# 16 Q Quad-precision floating-point extension\n# 17 R Reserved\n# 18 S Supervisor mode implemented\n# 19 T Tentatively reserved for Transactional Memory extension\n# 20 U User mode implemented\n# 21 V Tentatively reserved for Vector extension\n# 22 W Reserved\n# 23 X Non-standard extensions present\n# 24 Y Reserved\n# 25 Z Reserved\n\n\n# Moved most CSR registers to .pspec file. Doing so will:\n# - Allow new registers to be named in the .pspec file\n# - Processor variants differing only in CSR registers can just use a variant.pspec\n# - Read/Write references to registers not defined in sleigh\n# - Registers defined here will not get references to them\n# - Allow rename and comment by end user\n\n#\n# Control registers reserved 0x0000-0x0fff\n@define CSR_REG_START \"0x0000\"\n\n## CSR definitions is done as a big table with undefined holes so that\n## the 32-bit and 64-bit tables can be defined with the same code.\n## Otherwise the byte offset of the address of each register\n## would need to be calculated and would be different for XLEN of 32 or 64 bit.\ndefine csreg offset=$(CSR_REG_START) size=$(XLEN) [\n# 0x000\n _ fflags frm fcsr _ _ _ _ \n# 0x008\n _ _ _ _ _ _ _ _ \n# 0x010\n _ _ _ _ _ _ _ _ \n# 0x018\n _ _ _ _ _ _ _ _ \n# 0x020\n _ _ _ _ _ _ _ _ \n# 0x028\n _ _ _ _ _ _ _ _ \n# 0x030\n _ _ _ _ _ _ _ _ \n# 0x038\n _ _ _ _ _ _ _ _ \n# 0x040\n _ uepc _ _ _ _ _ _ \n# 0x048\n _ _ _ _ _ _ _ _ \n# 0x050\n _ _ _ _ _ _ _ _ \n# 0x058\n _ _ _ _ _ _ _ _ \n# 0x060\n _ _ _ _ _ _ _ _ \n# 0x068\n _ _ _ _ _ _ _ _ \n# 0x070\n _ _ _ _ _ _ _ _ \n# 0x078\n _ _ _ _ _ _ _ _ \n# 0x080\n _ _ _ _ _ _ _ _ \n# 0x088\n _ _ _ _ _ _ _ _ \n# 0x090\n _ _ _ _ _ _ _ _ \n# 0x098\n _ _ _ _ _ _ _ _ \n# 0x0a0\n _ _ _ _ _ _ _ _ \n# 0x0a8\n _ _ _ _ _ _ _ _ \n# 0x0b0\n _ _ _ _ _ _ _ _ \n# 0x0b8\n _ _ _ _ _ _ _ _ \n# 0x0c0\n _ _ _ _ _ _ _ _ \n# 0x0c8\n _ _ _ _ _ _ _ _ \n# 0x0d0\n _ _ _ _ _ _ _ _ \n# 0x0d8\n _ _ _ _ _ _ _ _ \n# 0x0e0\n _ _ _ _ _ _ _ _ \n# 0x0e8\n _ _ _ _ _ _ _ _ \n# 0x0f0\n _ _ _ _ _ _ _ _ \n# 0x0f8\n _ _ _ _ _ _ _ _ \n# 0x100\n _ _ _ _ _ _ _ _ \n# 0x108\n _ _ _ _ _ _ _ _ \n# 0x110\n _ _ _ _ _ _ _ _ \n# 0x118\n _ _ _ _ _ _ _ _ \n# 0x120\n _ _ _ _ _ _ _ _ \n# 0x128\n _ _ _ _ _ _ _ _ \n# 0x130\n _ _ _ _ _ _ _ _ \n# 0x138\n _ _ _ _ _ _ _ _ \n# 0x140\n _ sepc _ _ _ _ _ _ \n# 0x148\n _ _ _ _ _ _ _ _ \n# 0x150\n _ _ _ _ _ _ _ _ \n# 0x158\n _ _ _ _ _ _ _ _ \n# 0x160\n _ _ _ _ _ _ _ _ \n# 0x168\n _ _ _ _ _ _ _ _ \n# 0x170\n _ _ _ _ _ _ _ _ \n# 0x178\n _ _ _ _ _ _ _ _ \n# 0x180 \n _ _ _ _ _ _ _ _ \n# 0x188\n _ _ _ _ _ _ _ _ \n# 0x190\n _ _ _ _ _ _ _ _ \n# 0x198\n _ _ _ _ _ _ _ _ \n# 0x1a0\n _ _ _ _ _ _ _ _ \n# 0x1a8\n _ _ _ _ _ _ _ _ \n# 0x1b0\n _ _ _ _ _ _ _ _ \n# 0x1b8\n _ _ _ _ _ _ _ _ \n# 0x1c0\n _ _ _ _ _ _ _ _ \n# 0x1c8\n _ _ _ _ _ _ _ _ \n# 0x1d0\n _ _ _ _ _ _ _ _ \n# 0x1d8\n _ _ _ _ _ _ _ _ \n# 0x1e0\n _ _ _ _ _ _ _ _ \n# 0x1e8\n _ _ _ _ _ _ _ _ \n# 0x1f0\n _ _ _ _ _ _ _ _ \n# 0x1f8\n _ _ _ _ _ _ _ _ \n# 0x200\n _ _ _ _ _ _ _ _ \n# 0x208\n _ _ _ _ _ _ _ _ \n# 0x210\n _ _ _ _ _ _ _ _ \n# 0x218\n _ _ _ _ _ _ _ _ \n# 0x220\n _ _ _ _ _ _ _ _ \n# 0x228\n _ _ _ _ _ _ _ _ \n# 0x230\n _ _ _ _ _ _ _ _ \n# 0x238\n _ _ _ _ _ _ _ _ \n# 0x240 \n _ _ _ _ _ _ _ _ \n# 0x248\n _ _ _ _ _ _ _ _ \n# 0x250\n _ _ _ _ _ _ _ _ \n# 0x258\n _ _ _ _ _ _ _ _ \n# 0x260\n _ _ _ _ _ _ _ _ \n# 0x268\n _ _ _ _ _ _ _ _ \n# 0x270\n _ _ _ _ _ _ _ _ \n# 0x278\n _ _ _ _ _ _ _ _ \n# 0x280\n _ _ _ _ _ _ _ _ \n# 0x288\n _ _ _ _ _ _ _ _ \n# 0x290\n _ _ _ _ _ _ _ _ \n# 0x298\n _ _ _ _ _ _ _ _ \n# 0x2a0\n _ _ _ _ _ _ _ _ \n# 0x2a8\n _ _ _ _ _ _ _ _ \n# 0x2b0\n _ _ _ _ _ _ _ _ \n# 0x2b8\n _ _ _ _ _ _ _ _ \n# 0x2c0\n _ _ _ _ _ _ _ _ \n# 0x2c8\n _ _ _ _ _ _ _ _ \n# 0x2d0\n _ _ _ _ _ _ _ _ \n# 0x2d8\n _ _ _ _ _ _ _ _ \n# 0x2e0\n _ _ _ _ _ _ _ _ \n# 0x2e8\n _ _ _ _ _ _ _ _ \n# 0x2f0\n _ _ _ _ _ _ _ _ \n# 0x2f8\n _ _ _ _ _ _ _ _ \n# 0x310 \n _ _ _ _ _ _ _ _ \n# 0x308\n _ _ _ _ _ _ _ _ \n# 0x310 \n _ _ _ _ _ _ _ _ \n# 0x318\n _ _ _ _ _ _ _ _ \n# 0x320\n _ _ _ _ _ _ _ _ \n# 0x328\n _ _ _ _ _ _ _ _ \n# 0x330\n _ _ _ _ _ _ _ _ \n# 0x338\n _ _ _ _ _ _ _ _ \n# 0x318\n _ mepc _ _ _ _ _ _ \n# 0x348\n _ _ _ _ _ _ _ _ \n# 0x350\n _ _ _ _ _ _ _ _ \n# 0x358\n _ _ _ _ _ _ _ _ \n# 0x360\n _ _ _ _ _ _ _ _ \n# 0x368\n _ _ _ _ _ _ _ _ \n# 0x370\n _ _ _ _ _ _ _ _ \n# 0x378\n _ _ _ _ _ _ _ _ \n# 0x380\n _ _ _ _ _ _ _ _ \n# 0x388\n _ _ _ _ _ _ _ _ \n# 0x390\n _ _ _ _ _ _ _ _ \n# 0x398\n _ _ _ _ _ _ _ _ \n# 0x3a0\n _ _ _ _ _ _ _ _ \n# 0x3a8\n _ _ _ _ _ _ _ _ \n# 0x3b0\n _ _ _ _ _ _ _ _ \n# 0x3b8\n _ _ _ _ _ _ _ _ \n# 0x3c0\n _ _ _ _ _ _ _ _ \n# 0x3c8\n _ _ _ _ _ _ _ _ \n# 0x3d0\n _ _ _ _ _ _ _ _ \n# 0x3d8\n _ _ _ _ _ _ _ _ \n# 0x3e0\n _ _ _ _ _ _ _ _ \n# 0x3e8\n _ _ _ _ _ _ _ _ \n# 0x3f0\n _ _ _ _ _ _ _ _ \n# 0x3f8\n _ _ _ _ _ _ _ _ \n# 0x400\n _ _ _ _ _ _ _ _ \n# 0x408\n _ _ _ _ _ _ _ _ \n# 0x410\n _ _ _ _ _ _ _ _ \n# 0x418\n _ _ _ _ _ _ _ _ \n# 0x420\n _ _ _ _ _ _ _ _ \n# 0x428\n _ _ _ _ _ _ _ _ \n# 0x430\n _ _ _ _ _ _ _ _ \n# 0x438\n _ _ _ _ _ _ _ _ \n# 0x440\n _ _ _ _ _ _ _ _ \n# 0x448\n _ _ _ _ _ _ _ _ \n# 0x450\n _ _ _ _ _ _ _ _ \n# 0x458\n _ _ _ _ _ _ _ _ \n# 0x460\n _ _ _ _ _ _ _ _ \n# 0x468\n _ _ _ _ _ _ _ _ \n# 0x470\n _ _ _ _ _ _ _ _ \n# 0x478\n _ _ _ _ _ _ _ _ \n# 0x480\n _ _ _ _ _ _ _ _ \n# 0x488\n _ _ _ _ _ _ _ _ \n# 0x490\n _ _ _ _ _ _ _ _ \n# 0x498\n _ _ _ _ _ _ _ _ \n# 0x4a0\n _ _ _ _ _ _ _ _ \n# 0x4a8\n _ _ _ _ _ _ _ _ \n# 0x4b0\n _ _ _ _ _ _ _ _ \n# 0x4b8\n _ _ _ _ _ _ _ _ \n# 0x4c0\n _ _ _ _ _ _ _ _ \n# 0x4c8\n _ _ _ _ _ _ _ _ \n# 0x4d0\n _ _ _ _ _ _ _ _ \n# 0x4d8\n _ _ _ _ _ _ _ _ \n# 0x4e0\n _ _ _ _ _ _ _ _ \n# 0x4e8\n _ _ _ _ _ _ _ _ \n# 0x4f0\n _ _ _ _ _ _ _ _ \n# 0x4f8\n _ _ _ _ _ _ _ _ \n# 0x500\n _ _ _ _ _ _ _ _ \n# 0x508\n _ _ _ _ _ _ _ _ \n# 0x510\n _ _ _ _ _ _ _ _ \n# 0x518\n _ _ _ _ _ _ _ _ \n# 0x520\n _ _ _ _ _ _ _ _ \n# 0x528\n _ _ _ _ _ _ _ _ \n# 0x530\n _ _ _ _ _ _ _ _ \n# 0x538\n _ _ _ _ _ _ _ _ \n# 0x540\n _ _ _ _ _ _ _ _ \n# 0x548\n _ _ _ _ _ _ _ _ \n# 0x550\n _ _ _ _ _ _ _ _ \n# 0x558\n _ _ _ _ _ _ _ _ \n# 0x560\n _ _ _ _ _ _ _ _ \n# 0x568\n _ _ _ _ _ _ _ _ \n# 0x570\n _ _ _ _ _ _ _ _ \n# 0x578\n _ _ _ _ _ _ _ _ \n# 0x580\n _ _ _ _ _ _ _ _ \n# 0x588\n _ _ _ _ _ _ _ _ \n# 0x590\n _ _ _ _ _ _ _ _ \n# 0x598\n _ _ _ _ _ _ _ _ \n# 0x5a0\n _ _ _ _ _ _ _ _ \n# 0x5a8 \n _ _ _ _ _ _ _ _ \n# 0x5b0\n _ _ _ _ _ _ _ _ \n# 0x5b8\n _ _ _ _ _ _ _ _ \n# 0x5c0\n _ _ _ _ _ _ _ _ \n# 0x5c8\n _ _ _ _ _ _ _ _ \n# 0x5d0\n _ _ _ _ _ _ _ _ \n# 0x5d8\n _ _ _ _ _ _ _ _ \n# 0x5e0\n _ _ _ _ _ _ _ _ \n# 0x5e8\n _ _ _ _ _ _ _ _ \n# 0x5f0\n _ _ _ _ _ _ _ _ \n# 0x5f8\n _ _ _ _ _ _ _ _ \n# 0x600 \n _ _ _ _ _ _ _ _ \n# 0x608\n _ _ _ _ _ _ _ _ \n# 0x610\n _ _ _ _ _ _ _ _ \n# 0x618\n _ _ _ _ _ _ _ _ \n# 0x620\n _ _ _ _ _ _ _ _ \n# 0x628\n _ _ _ _ _ _ _ _ \n# 0x630\n _ _ _ _ _ _ _ _ \n# 0x638\n _ _ _ _ _ _ _ _ \n# 0x640\n _ _ _ _ _ _ _ _ \n# 0x648\n _ _ _ _ _ _ _ _ \n# 0x650\n _ _ _ _ _ _ _ _ \n# 0x658\n _ _ _ _ _ _ _ _ \n# 0x660\n _ _ _ _ _ _ _ _ \n# 0x668\n _ _ _ _ _ _ _ _ \n# 0x670\n _ _ _ _ _ _ _ _ \n# 0x678\n _ _ _ _ _ _ _ _ \n# 0x680 \n _ _ _ _ _ _ _ _ \n# 0x688\n _ _ _ _ _ _ _ _ \n# 0x690\n _ _ _ _ _ _ _ _ \n# 0x698\n _ _ _ _ _ _ _ _ \n# 0x6a0\n _ _ _ _ _ _ _ _ \n# 0x6a8 \n _ _ _ _ _ _ _ _ \n# 0x6b0\n _ _ _ _ _ _ _ _ \n# 0x6b8\n _ _ _ _ _ _ _ _ \n# 0x6c0\n _ _ _ _ _ _ _ _ \n# 0x6c8\n _ _ _ _ _ _ _ _ \n# 0x6d0\n _ _ _ _ _ _ _ _ \n# 0x6d8\n _ _ _ _ _ _ _ _ \n# 0x6e0\n _ _ _ _ _ _ _ _ \n# 0x6e8\n _ _ _ _ _ _ _ _ \n# 0x6f0\n _ _ _ _ _ _ _ _ \n# 0x6f8\n _ _ _ _ _ _ _ _ \n# 0x700\n _ _ _ _ _ _ _ _ \n# 0x708\n _ _ _ _ _ _ _ _ \n# 0x710\n _ _ _ _ _ _ _ _ \n# 0x718\n _ _ _ _ _ _ _ _ \n# 0x720\n _ _ _ _ _ _ _ _ \n# 0x728\n _ _ _ _ _ _ _ _ \n# 0x730\n _ _ _ _ _ _ _ _ \n# 0x738\n _ _ _ _ _ _ _ _ \n# 0x740\n _ _ _ _ _ _ _ _ \n# 0x748\n _ _ _ _ _ _ _ _ \n# 0x750\n _ _ _ _ _ _ _ _ \n# 0x758\n _ _ _ _ _ _ _ _ \n# 0x760\n _ _ _ _ _ _ _ _ \n# 0x768\n _ _ _ _ _ _ _ _ \n# 0x770\n _ _ _ _ _ _ _ _ \n# 0x778\n _ _ _ _ _ _ _ _ \n# 0x780\n _ _ _ _ _ _ _ _ \n# 0x788\n _ _ _ _ _ _ _ _ \n# 0x790\n _ _ _ _ _ _ _ _ \n# 0x798\n _ _ _ _ _ _ _ _ \n# 0x7a0\n _ _ _ _ _ _ _ _ \n# 0x7a8\n _ _ _ _ _ _ _ _ \n# 0x7b0\n dcsr dpc dscratch0 dscratch1 _ _ _ _ \n# 0x7b8\n _ _ _ _ _ _ _ _ \n# 0x7c0\n _ _ _ _ _ _ _ _ \n# 0x7c8\n _ _ _ _ _ _ _ _ \n# 0x7d0\n _ _ _ _ _ _ _ _ \n# 0x7d8\n _ _ _ _ _ _ _ _ \n# 0x7e0\n _ _ _ _ _ _ _ _ \n# 0x7e8\n _ _ _ _ _ _ _ _ \n# 0x7f0\n _ _ _ _ _ _ _ _ \n# 0x7f8\n _ _ _ _ _ _ _ _ \n# 0x800\n _ _ _ _ _ _ _ _ \n# 0x808\n _ _ _ _ _ _ _ _ \n# 0x810\n _ _ _ _ _ _ _ _ \n# 0x818\n _ _ _ _ _ _ _ _ \n# 0x820\n _ _ _ _ _ _ _ _ \n# 0x828\n _ _ _ _ _ _ _ _ \n# 0x830\n _ _ _ _ _ _ _ _ \n# 0x838\n _ _ _ _ _ _ _ _ \n# 0x840\n _ _ _ _ _ _ _ _ \n# 0x848\n _ _ _ _ _ _ _ _ \n# 0x850\n _ _ _ _ _ _ _ _ \n# 0x858\n _ _ _ _ _ _ _ _ \n# 0x860\n _ _ _ _ _ _ _ _ \n# 0x868\n _ _ _ _ _ _ _ _ \n# 0x870\n _ _ _ _ _ _ _ _ \n# 0x878\n _ _ _ _ _ _ _ _ \n# 0x880\n _ _ _ _ _ _ _ _ \n# 0x888\n _ _ _ _ _ _ _ _ \n# 0x890\n _ _ _ _ _ _ _ _ \n# 0x898\n _ _ _ _ _ _ _ _ \n# 0x8a0\n _ _ _ _ _ _ _ _ \n# 0x8a8\n _ _ _ _ _ _ _ _ \n# 0x8b0\n _ _ _ _ _ _ _ _ \n# 0x8b8\n _ _ _ _ _ _ _ _ \n# 0x8c0\n _ _ _ _ _ _ _ _ \n# 0x8c8\n _ _ _ _ _ _ _ _ \n# 0x8d0\n _ _ _ _ _ _ _ _ \n# 0x8d8\n _ _ _ _ _ _ _ _ \n# 0x8e0\n _ _ _ _ _ _ _ _ \n# 0x8e8\n _ _ _ _ _ _ _ _ \n# 0x8f0\n _ _ _ _ _ _ _ _ \n# 0x8f8\n _ _ _ _ _ _ _ _ \n# 0x900\n _ _ _ _ _ _ _ _ \n# 0x908\n _ _ _ _ _ _ _ _ \n# 0x910\n _ _ _ _ _ _ _ _ \n# 0x918\n _ _ _ _ _ _ _ _ \n# 0x920\n _ _ _ _ _ _ _ _ \n# 0x928\n _ _ _ _ _ _ _ _ \n# 0x930\n _ _ _ _ _ _ _ _ \n# 0x938\n _ _ _ _ _ _ _ _ \n# 0x940\n _ _ _ _ _ _ _ _ \n# 0x948\n _ _ _ _ _ _ _ _ \n# 0x950\n _ _ _ _ _ _ _ _ \n# 0x958\n _ _ _ _ _ _ _ _ \n# 0x960\n _ _ _ _ _ _ _ _ \n# 0x968\n _ _ _ _ _ _ _ _ \n# 0x970\n _ _ _ _ _ _ _ _ \n# 0x978\n _ _ _ _ _ _ _ _ \n# 0x980\n _ _ _ _ _ _ _ _ \n# 0x988\n _ _ _ _ _ _ _ _ \n# 0x990\n _ _ _ _ _ _ _ _ \n# 0x998\n _ _ _ _ _ _ _ _ \n# 0x9a0\n _ _ _ _ _ _ _ _ \n# 0x9a8\n _ _ _ _ _ _ _ _ \n# 0x9b0\n _ _ _ _ _ _ _ _ \n# 0x9b8\n _ _ _ _ _ _ _ _ \n# 0x9c0\n _ _ _ _ _ _ _ _ \n# 0x9c8\n _ _ _ _ _ _ _ _ \n# 0x9d0\n _ _ _ _ _ _ _ _ \n# 0x9d8\n _ _ _ _ _ _ _ _ \n# 0x9e0\n _ _ _ _ _ _ _ _ \n# 0x9e8\n _ _ _ _ _ _ _ _ \n# 0x9f0\n _ _ _ _ _ _ _ _ \n# 0x9f8\n _ _ _ _ _ _ _ _ \n# 0xa00\n _ _ _ _ _ _ _ _ \n# 0xa08\n _ _ _ _ _ _ _ _ \n# 0xa10\n _ _ _ _ _ _ _ _ \n# 0xa18\n _ _ _ _ _ _ _ _ \n# 0xa20\n _ _ _ _ _ _ _ _ \n# 0xa28\n _ _ _ _ _ _ _ _ \n# 0xa30\n _ _ _ _ _ _ _ _ \n# 0xa38\n _ _ _ _ _ _ _ _ \n# 0xa40\n _ _ _ _ _ _ _ _ \n# 0xa48\n _ _ _ _ _ _ _ _ \n# 0xa50\n _ _ _ _ _ _ _ _ \n# 0xa58\n _ _ _ _ _ _ _ _ \n# 0xa60\n _ _ _ _ _ _ _ _ \n# 0xa68\n _ _ _ _ _ _ _ _ \n# 0xa70\n _ _ _ _ _ _ _ _ \n# 0xa78\n _ _ _ _ _ _ _ _ \n# 0xa80\n _ _ _ _ _ _ _ _ \n# 0xa88\n _ _ _ _ _ _ _ _ \n# 0xa90\n _ _ _ _ _ _ _ _ \n# 0xa98\n _ _ _ _ _ _ _ _ \n# 0xaa0\n _ _ _ _ _ _ _ _ \n# 0xaa8\n _ _ _ _ _ _ _ _ \n# 0xab0\n _ _ _ _ _ _ _ _ \n# 0xab8\n _ _ _ _ _ _ _ _ \n# 0xac0\n _ _ _ _ _ _ _ _ \n# 0xac8\n _ _ _ _ _ _ _ _ \n# 0xad0\n _ _ _ _ _ _ _ _ \n# 0xad8\n _ _ _ _ _ _ _ _ \n# 0xae0\n _ _ _ _ _ _ _ _ \n# 0xae8\n _ _ _ _ _ _ _ _ \n# 0xaf0\n _ _ _ _ _ _ _ _ \n# 0xaf8\n _ _ _ _ _ _ _ _ \n# 0xa00\n _ _ _ _ _ _ _ _ \n# 0xa08\n _ _ _ _ _ _ _ _ \n# 0xa10\n _ _ _ _ _ _ _ _ \n# 0xa18\n _ _ _ _ _ _ _ _ \n# 0xb20\n _ _ _ _ _ _ _ _ \n# 0xb28\n _ _ _ _ _ _ _ _ \n# 0xb30\n _ _ _ _ _ _ _ _ \n# 0xb38\n _ _ _ _ _ _ _ _ \n# 0xb40\n _ _ _ _ _ _ _ _ \n# 0xb48\n _ _ _ _ _ _ _ _ \n# 0xb50\n _ _ _ _ _ _ _ _ \n# 0xb58\n _ _ _ _ _ _ _ _ \n# 0xb60\n _ _ _ _ _ _ _ _ \n# 0xb68\n _ _ _ _ _ _ _ _ \n# 0xb70\n _ _ _ _ _ _ _ _ \n# 0xb78\n _ _ _ _ _ _ _ _ \n# 0xb80\n _ _ _ _ _ _ _ _ \n# 0xb88\n _ _ _ _ _ _ _ _ \n# 0xb90\n _ _ _ _ _ _ _ _ \n# 0xb98\n _ _ _ _ _ _ _ _ \n# 0xba0\n _ _ _ _ _ _ _ _ \n# 0xba8\n _ _ _ _ _ _ _ _ \n# 0xbb0\n _ _ _ _ _ _ _ _ \n# 0xbb8\n _ _ _ _ _ _ _ _ \n# 0xbc0\n _ _ _ _ _ _ _ _ \n# 0xbc8\n _ _ _ _ _ _ _ _ \n# 0xbd0\n _ _ _ _ _ _ _ _ \n# 0xbd8\n _ _ _ _ _ _ _ _ \n# 0xbe0\n _ _ _ _ _ _ _ _ \n# 0xbe8\n _ _ _ _ _ _ _ _ \n# 0xbf0\n _ _ _ _ _ _ _ _ \n# 0xbf8\n _ _ _ _ _ _ _ _ \n# 0xc00\n _ _ _ _ _ _ _ _\n# 0xc08\n _ _ _ _ _ _ _ _\n# 0xc10\n _ _ _ _ _ _ _ _\n# 0xc18\n _ _ _ _ _ _ _ _\n# 0xc20\n _ _ _ _ _ _ _ _\n# 0xc28\n _ _ _ _ _ _ _ _ \n# 0xc30\n _ _ _ _ _ _ _ _ \n# 0xc38\n _ _ _ _ _ _ _ _ \n# 0xc40\n _ _ _ _ _ _ _ _ \n# 0xc48\n _ _ _ _ _ _ _ _ \n# 0xc50\n _ _ _ _ _ _ _ _ \n# 0xc58\n _ _ _ _ _ _ _ _ \n# 0xc60\n _ _ _ _ _ _ _ _ \n# 0xc68\n _ _ _ _ _ _ _ _ \n# 0xc70\n _ _ _ _ _ _ _ _ \n# 0xc78\n _ _ _ _ _ _ _ _ \n# 0xc80\n _ _ _ _ _ _ _ _ \n# 0xc88\n _ _ _ _ _ _ _ _ \n# 0xc90\n _ _ _ _ _ _ _ _ \n# 0xc98\n _ _ _ _ _ _ _ _ \n# 0xca0\n _ _ _ _ _ _ _ _ \n# 0xca8\n _ _ _ _ _ _ _ _ \n# 0xcb0\n _ _ _ _ _ _ _ _ \n# 0xcb8\n _ _ _ _ _ _ _ _ \n# 0xcc0\n _ _ _ _ _ _ _ _ \n# 0xcc8\n _ _ _ _ _ _ _ _ \n# 0xcd0\n _ _ _ _ _ _ _ _ \n# 0xcd8\n _ _ _ _ _ _ _ _ \n# 0xce0\n _ _ _ _ _ _ _ _ \n# 0xce8\n _ _ _ _ _ _ _ _ \n# 0xcf0\n _ _ _ _ _ _ _ _ \n# 0xcf8\n _ _ _ _ _ _ _ _ \n# 0xd00\n _ _ _ _ _ _ _ _ \n# 0xd08\n _ _ _ _ _ _ _ _ \n# 0xd10\n _ _ _ _ _ _ _ _ \n# 0xd18\n _ _ _ _ _ _ _ _ \n# 0xd20\n _ _ _ _ _ _ _ _ \n# 0xd28\n _ _ _ _ _ _ _ _ \n# 0xd30\n _ _ _ _ _ _ _ _ \n# 0xd38\n _ _ _ _ _ _ _ _ \n# 0xd40\n _ _ _ _ _ _ _ _ \n# 0xd48\n _ _ _ _ _ _ _ _ \n# 0xd50\n _ _ _ _ _ _ _ _ \n# 0xd58\n _ _ _ _ _ _ _ _ \n# 0xd60\n _ _ _ _ _ _ _ _ \n# 0xd68\n _ _ _ _ _ _ _ _ \n# 0xd70\n _ _ _ _ _ _ _ _ \n# 0xd78\n _ _ _ _ _ _ _ _ \n# 0xd80\n _ _ _ _ _ _ _ _ \n# 0xd88\n _ _ _ _ _ _ _ _ \n# 0xd90\n _ _ _ _ _ _ _ _ \n# 0xd98\n _ _ _ _ _ _ _ _ \n# 0xda0\n _ _ _ _ _ _ _ _ \n# 0xda8\n _ _ _ _ _ _ _ _ \n# 0xdb0\n _ _ _ _ _ _ _ _ \n# 0xdb8\n _ _ _ _ _ _ _ _ \n# 0xdc0\n _ _ _ _ _ _ _ _ \n# 0xdc8\n _ _ _ _ _ _ _ _ \n# 0xdd0\n _ _ _ _ _ _ _ _ \n# 0xdd8\n _ _ _ _ _ _ _ _ \n# 0xde0\n _ _ _ _ _ _ _ _ \n# 0xde8\n _ _ _ _ _ _ _ _ \n# 0xdf0\n _ _ _ _ _ _ _ _ \n# 0xdf8\n _ _ _ _ _ _ _ _ \n# 0xe00\n _ _ _ _ _ _ _ _ \n# 0xe08\n _ _ _ _ _ _ _ _ \n# 0xe10\n _ _ _ _ _ _ _ _ \n# 0xe18\n _ _ _ _ _ _ _ _ \n# 0xe20\n _ _ _ _ _ _ _ _ \n# 0xe28\n _ _ _ _ _ _ _ _ \n# 0xe30\n _ _ _ _ _ _ _ _ \n# 0xe38\n _ _ _ _ _ _ _ _ \n# 0xe40\n _ _ _ _ _ _ _ _ \n# 0xe48\n _ _ _ _ _ _ _ _ \n# 0xe50\n _ _ _ _ _ _ _ _ \n# 0xe58\n _ _ _ _ _ _ _ _ \n# 0xe60\n _ _ _ _ _ _ _ _ \n# 0xe68\n _ _ _ _ _ _ _ _ \n# 0xe70\n _ _ _ _ _ _ _ _ \n# 0xe78\n _ _ _ _ _ _ _ _ \n# 0xe80\n _ _ _ _ _ _ _ _ \n# 0xe88\n _ _ _ _ _ _ _ _ \n# 0xe90\n _ _ _ _ _ _ _ _ \n# 0xe98\n _ _ _ _ _ _ _ _ \n# 0xea0\n _ _ _ _ _ _ _ _ \n# 0xea8\n _ _ _ _ _ _ _ _ \n# 0xeb0\n _ _ _ _ _ _ _ _ \n# 0xeb8\n _ _ _ _ _ _ _ _ \n# 0xec0\n _ _ _ _ _ _ _ _ \n# 0xec8\n _ _ _ _ _ _ _ _ \n# 0xed0\n _ _ _ _ _ _ _ _ \n# 0xed8\n _ _ _ _ _ _ _ _ \n# 0xee0\n _ _ _ _ _ _ _ _ \n# 0xee8\n _ _ _ _ _ _ _ _ \n# 0xef0\n _ _ _ _ _ _ _ _ \n# 0xef8\n _ _ _ _ _ _ _ _ \n# 0xf00\n _ _ _ _ _ _ _ _ \n# 0xf08\n _ _ _ _ _ _ _ _ \n# 0xf10\n _ _ _ _ _ _ _ _ \n# 0xf18\n _ _ _ _ _ _ _ _ \n# 0xf20\n _ _ _ _ _ _ _ _ \n# 0xf28\n _ _ _ _ _ _ _ _ \n# 0xf30\n _ _ _ _ _ _ _ _ \n# 0xf38\n _ _ _ _ _ _ _ _ \n# 0xf40\n _ _ _ _ _ _ _ _ \n# 0xf48\n _ _ _ _ _ _ _ _ \n# 0xf50\n _ _ _ _ _ _ _ _ \n# 0xf58\n _ _ _ _ _ _ _ _ \n# 0xf60\n _ _ _ _ _ _ _ _ \n# 0xf68\n _ _ _ _ _ _ _ _ \n# 0xf70\n _ _ _ _ _ _ _ _ \n# 0xf78\n _ _ _ _ _ _ _ _ \n# 0xf80\n _ _ _ _ _ _ _ _ \n# 0xf88\n _ _ _ _ _ _ _ _ \n# 0xf90\n _ _ _ _ _ _ _ _ \n# 0xf98\n _ _ _ _ _ _ _ _ \n# 0xfa0\n _ _ _ _ _ _ _ _ \n# 0xfa8\n _ _ _ _ _ _ _ _ \n# 0xfb0\n _ _ _ _ _ _ _ _ \n# 0xfb8\n _ _ _ _ _ _ _ _ \n# 0xfc0\n _ _ _ _ _ _ _ _ \n# 0xfc8\n _ _ _ _ _ _ _ _ \n# 0xfd0\n _ _ _ _ _ _ _ _ \n# 0xfd8\n _ _ _ _ _ _ _ _ \n# 0xfe0\n _ _ _ _ _ _ _ _ \n# 0xfe8\n _ _ _ _ _ _ _ _ \n# 0xff0\n _ _ _ _ _ _ _ _ \n# 0xff8\n _ _ _ _ _ _ _ _ \n];\n\n\n\n\ndefine context CONTEXT\n reserved=(0,3)\n MXL=(4,5) # MXL - Machine XLEN {1: 32, 2: 64, 3: 128}\n;\n\n\ndefine token instr (32)\n op0001=(0,1)\n op0006=(0,6)\n op0204=(2,4)\n op0506=(5,6)\n op0707=(7,7)\n op0711=(7,11)\n r0711=(7,11)\n fr0711=(7,11)\n v0711=(7,11)\n op0808=(8,8)\n op0809=(8,9)\n op0811=(8,11)\n op0911=(9,11)\n op1011=(10,11)\n op1213=(12,13)\n op1214=(12,14)\n funct3=(12,14)\n op1219=(12,19)\n op1231=(12,31)\n sop1231=(12,31) signed\n op1414=(14,14)\n op1516=(15,16)\n op1519=(15,19)\n sop1519=(15,19) signed\n subf5=(15,19)\n r1519=(15,19)\n fr1519=(15,19)\n v1519=(15,19)\n op1527=(15,27)\n op1531=(15,31)\n op1719=(17,19)\n op2020=(20,20)\n op2022=(20,22)\n succ=(20,23)\n op2023=(20,23)\n op2024=(20,24)\n r2024=(20,24)\n fr2024=(20,24)\n v2024=(20,24)\n op2025=(20,25)\n op2026=(20,26)\n csr_0=(20,27)\n csr_1=(20,27)\n csr_2=(20,27)\n csr_3=(20,27)\n csr_4=(20,27)\n csr_50=(20,26)\n csr_58=(20,25)\n csr_5C=(20,25)\n csr_60=(20,26)\n csr_68=(20,25)\n csr_6C=(20,25)\n csr_70=(20,26)\n csr_78=(20,24)\n csr_7A=(20,23)\n csr_7B=(20,23)\n csr_7C=(20,25)\n csr_8=(20,27)\n csr_90=(20,26)\n csr_98=(20,25)\n csr_9C=(20,25)\n csr_A0=(20,26)\n csr_A8=(20,25)\n csr_AC=(20,25)\n csr_B0=(20,26)\n csr_B8=(20,25)\n csr_BC=(20,25)\n csr_C0=(20,26)\n csr_C8=(20,25)\n csr_CC=(20,25)\n csr_D0=(20,26)\n csr_D8=(20,25)\n csr_DC=(20,25)\n csr_E0=(20,26)\n csr_E8=(20,25)\n csr_EC=(20,25)\n csr_F0=(20,26)\n csr_F8=(20,25)\n csr_FC=(20,25)\n op2030=(20,30)\n op2031=(20,31)\n sop2031=(20,31) signed\n op2121=(21,21)\n op2122=(21,22)\n op2130=(21,30)\n op2222=(22,22)\n op2230=(22,30)\n op2323=(23,23)\n op2324=(23,24)\n op2330=(23,30)\n op2424=(24,24)\n op2427=(24,27)\n pred=(24,27)\n op2525=(25,25)\n op2526=(25,26)\n op2527=(25,27)\n op2529=(25,29)\n op2530=(25,30)\n op2531=(25,31)\n sop2531=(25,31) signed\n funct7=(25,31)\n wd=(26,26)\n op2626=(26,26)\n op2627=(26,27)\n op2631=(26,31)\n op2731=(27,31)\n amoop=(27,31)\n funct5=(27,31)\n op2727=(27,27)\n r2731=(27,31)\n fr2731=(27,31)\n op2828=(28,28)\n op2829=(28,29)\n fm=(28,31)\n op2931=(29,31)\n op3030=(30,30)\n op3031=(30,31)\n op3131=(31,31)\n sop3131=(31,31) signed\n;\n\ndefine token cinstr (16)\n cop0001=(0,1)\n cop0202=(2,2)\n cop0203=(2,3)\n cop0204=(2,4)\n cr0204s=(2,4)\n cfr0204s=(2,4)\n cop0205=(2,5)\n cop0206=(2,6)\n cr0206=(2,6)\n cfr0206=(2,6)\n cop0212=(2,12)\n cop0303=(3,3)\n cop0304=(3,4)\n cop0305=(3,5)\n cop0404=(4,4)\n cop0406=(4,6)\n cop0505=(5,5)\n cop0506=(5,6)\n cop0512=(5,12)\n cop0606=(6,6)\n cop0707=(7,7)\n cop0708=(7,8)\n cop0709=(7,9)\n cr0709s=(7,9)\n cd0709s=(7,9)\n cfr0709s=(7,9)\n cop0710=(7,10)\n cop0711=(7,11)\n cr0711=(7,11)\n cd0711NoSp=(7,11)\n cd0711=(7,11) \n cfr0711=(7,11)\n cop0712=(7,12)\n cop0808=(8,8)\n cop0909=(9,9)\n cop0910=(9,10)\n cop0912=(9,12)\n cop1010=(10,10)\n cop1011=(10,11)\n cop1012=(10,12)\n cop1111=(11,11)\n cop1112=(11,12)\n cop1212=(12,12)\n scop1212=(12,12) signed\n cop1315=(13,15)\n;\n\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32a.sinc", "content": "# RV32A Standard Extension\n\n# amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4) \n:amoadd.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\ttmp = tmp + tmprs2;\n\t*[ram]:4 tmprs1 = tmp;\n}\n\n\n# amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4) \n:amoand.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\ttmp = tmp & tmprs2;\n\t*[ram]:4 tmprs1 = tmp;\n}\n\n\n# amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4) \n:amomax.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\tif (tmprs2 s<= tmp) goto inst_next;\n\t*[ram]:4 tmprs1 = tmprs2;\n}\n\n\n# amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4) \n:amomaxu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\tif (tmprs2 <= tmp) goto inst_next;\n\t*[ram]:4 tmprs1 = tmprs2;\n}\n\n\n# amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4) \n:amomin.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp); \n\tif (tmprs2 s>= tmp) goto inst_next;\n\t*[ram]:4 tmprs1 = tmprs2;\n}\n\n\n# amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4) \n:amominu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\tif (tmprs2 >= tmp) goto inst_next;\n\t*[ram]:4 tmprs1 = tmprs2;\n}\n\n\n# amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4) \n:amoor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\ttmp = tmp | tmprs2;\n\t*[ram]:4 tmprs1 = tmp;\n}\n\n\n# amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4) \n:amoswap.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\t*[ram]:4 tmprs1 = tmprs2;\n}\n\n\n# amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4) \n:amoxor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2W;\n\tlocal tmp:4 = *[ram]:4 tmprs1;\n\tassignW(rd, tmp);\n\ttmp = tmp ^ tmprs2;\n\t*[ram]:4 tmprs1 = tmp;\n}\n\n\n# lr.w d,0(s) 1000202f fff0707f DWORD|DREF (0, 4) \n:lr.w^aqrl rd,(rs1) is rs1 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x2 & op2024=0x0 & aqrl\n{\n\tRESERVE_ADDRESS = rs1;\n\tRESERVE = 1;\n\tRESERVE_LENGTH = 4;\n\tassignW(rd, *[ram]:4 rs1);\n}\n\n\n# sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4) \n:sc.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl\n{\n\tlocal tmprs2 = rs2W;\n\tlocal tmprs1 = rs1;\n\trd = 1;\n\tif ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 4)) goto inst_next;\n\t*[ram]:4 tmprs1 = tmprs2;\n\trd = 0;\n\tRESERVE_ADDRESS = 0;\n\tRESERVE = 0;\n\tRESERVE_LENGTH = 0;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32b.sinc", "content": "# RV32 Bitmanip Extension\n\n:andn rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x20 & rd & rs1 & rs2 unimpl\n\n:bdep rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:bext rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:bfp rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:clmul rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:clmulh rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:clmulr rd, rs1, rs2 is op0006=0x33 & op1214=0x2 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:clz rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x0 & op2531=0x30 & rd & rs1 unimpl\n\n:cmix rd, rs2, rs1, rs3 is op0006=0x33 & op1214=0x1 & op2526=0x3 & rd & rs1 & rs2 & rs3 unimpl\n\n:cmov rd, rs2, rs1, rs3 is op0006=0x33 & op1214=0x5 & op2526=0x3 & rd & rs1 & rs2 & rs3 unimpl\n\n:crc32.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x10 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x11 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32.w rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x12 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32c.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x18 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32c.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x19 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32c.w rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1a & op2531=0x30 & rd & rs1 unimpl\n\n:ctz rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1 & op2531=0x30 & rd & rs1 unimpl\n\n:fsl rd, rs1, rs3, rs2 is op0006=0x33 & op1214=0x1 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl\n\n:fsr rd, rs1, rs3, rs2 is op0006=0x33 & op1214=0x5 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl\n\n#TODO fix op2025\n#TODO this looks like a typo in 0.92\n:fsri rd, rs1, rs3, op2025 is op0006=0x33 & op1214=0x5 & op2626=0x1 & op2025 & rd & rs1 & rs3 unimpl\n\n:gorc rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x14 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:gorci rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x5 & op2026 & rd & rs1 unimpl\n\n:grev rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x34 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:grevi rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0xd & op2026 & rd & rs1 unimpl\n\n:max rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:maxu rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:min rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:minu rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:orn rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x20 & rd & rs1 & rs2 unimpl\n\n:pack rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:packh rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:packu rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:pcnt rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x2 & op2531=0x30 & rd & rs1 unimpl\n\n:rol rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x30 & rd & rs1 & rs2 unimpl\n\n:ror rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x30 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:rori rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0xc & op2026 & rd & rs1 unimpl\n\n:sbclr rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:sbclri rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x9 & op2026 & rd & rs1 unimpl\n\n:sbext rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:sbexti rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x9 & op2026 & rd & rs1 unimpl\n\n:sbinv rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x34 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:sbinvi rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0xd & op2026 & rd & rs1 unimpl\n\n:sbset rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x14 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:sbseti rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x5 & op2026 & rd & rs1 unimpl\n\n:sext.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x4 & op2531=0x30 & rd & rs1 unimpl\n\n:sext.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x5 & op2531=0x30 & rd & rs1 unimpl\n\n:sh1add rd, rs1, rs2 is op0006=0x33 & op1214=0x2 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:sh2add rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:sh3add rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:shfl rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2025\n:shfli rd, rs1, op2025 is op0006=0x13 & op1214=0x1 & op2631=0x2 & op2025 & rd & rs1 unimpl\n\n:slo rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:sloi rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x4 & op2026 & rd & rs1 unimpl\n\n:sro rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:sroi rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x4 & op2026 & rd & rs1 unimpl\n\n:unshfl rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2025\n:unshfli rd, rs1, op2025 is op0006=0x13 & op1214=0x5 & op2631=0x2 & op2025 & rd & rs1 unimpl\n\n:xnor rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x20 & rd & rs1 & rs2 unimpl\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32d.sinc", "content": "# RV32D Standard Extension\n\n\n# fadd.d D,S,T,m 02000053 fe00007f SIMPLE (0, 0) \n:fadd.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1\n{\n\tfrd = frs1D f+ frs2D;\n}\n\n\n# fclass.d d,S e2001053 fff0707f SIMPLE (0, 0) \n:fclass.d rd,frs1D is frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x71 & op2024=0x0\n{\n\t#TODO\n\t# rd = 0;\n\t# rd[0, 1] = 0; #TODO - inf\n\t# rd[1, 1] = 0; #TODO - norm num\n\t# rd[2, 1] = 0; #TODO - subnorm num\n\t# rd[3, 1] = 0; #TODO - 0\n\t# rd[4, 1] = 0; #TODO + 0\n\t# rd[5, 1] = 0; #TODO + norm num\n\t# rd[6, 1] = 0; #TODO + subnorm num\n\t# rd[7, 1] = 0; #TODO + inf\n\t# rd[8, 1] = 0; #TODO snan\n\t# rd[9, 1] = 0; #TODO qnan\n}\n\n\n# fcvt.d.s D,S 42000053 fff0707f SIMPLE (0, 0) \n:fcvt.d.s frd,frs1S is frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x21 & op2024=0x0\n{\n\tlocal tmp:8 = float2float(frs1S);\n\tfrd = tmp;\n}\n\n\n# fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0) \n:fcvt.d.w frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0\n{\n\tlocal tmp:8 = int2float(rs1W);\n\tfrd = tmp;\n}\n\n\n# fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0) \n:fcvt.d.wu frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1\n{\n\t#ATTN unsigned can be an issue here\n\tlocal u32:$(XLEN2) = zext(rs1W);\n\tlocal tmp:8 = int2float(u32);\n\tfrd = tmp;\n}\n\n\n# fcvt.s.d D,S,m 40100053 fff0007f SIMPLE (0, 0) \n:fcvt.s.d frd,frs1D,FRM is frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1\n{\n\tlocal tmp:4 = float2float(frs1D);\n\tfrd = zext(tmp);\n}\n\n\n# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0) \n:fcvt.w.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0\n{\n\trdW = trunc(frs1D);\n}\n\n\n# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0) \n:fcvt.wu.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1\n{\n\t#TODO unsigned\n\trdW = trunc(frs1D);\n}\n\n\n# fdiv.d D,S,T,m 1a000053 fe00007f SIMPLE (0, 0) \n:fdiv.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd\n{\n\tfrd = frs1D f/ frs2D;\n}\n\n\n# feq.d d,S,T a2002053 fe00707f SIMPLE (0, 0) \n:feq.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x51\n{\n\trd = zext(frs1D f== frs2D);\n}\n\n\n# fld D,o(s) 00003007 0000707f QWORD|DREF (0, 8) \n:fld frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x3\n{\n\tlocal ea:$(XLEN) = immI + rs1;\n\tfrd = *[ram]:$(DFLEN) ea;\n}\n\n\n# fle.d d,S,T a2000053 fe00707f SIMPLE (0, 0) \n:fle.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51\n{\n\trd = zext(frs1D f<= frs2D);\n}\n\n\n# flt.d d,S,T a2001053 fe00707f SIMPLE (0, 0) \n:flt.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51\n{\n\trd = zext(frs1D f< frs2D);\n}\n#endif\n\n\n# fmadd.d D,S,T,R,m 02000043 0600007f SIMPLE (0, 0) \n:fmadd.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1\n{\n\tfrd = (frs1D f* frs2D) f+ frs3D;\n}\n\n\n# fmax.d D,S,T 2a001053 fe00707f SIMPLE (0, 0) \n:fmax.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x15\n{\n\t#TODO redo this\n\tlocal tmpfrs1 = frs1D;\n\tlocal tmpfrs2 = frs2D;\n\tfrd = tmpfrs1;\n\tif (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;\n\tif (nan(tmpfrs2)) goto inst_next;\n\tfrd = tmpfrs2;\n\tif (nan(tmpfrs1)) goto inst_next;\n\tif (tmpfrs2 f> tmpfrs1) goto inst_next;\n\tfrd = tmpfrs1;\n}\n\n\n# fmin.d D,S,T 2a000053 fe00707f SIMPLE (0, 0) \n:fmin.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x15\n{\n\t#TODO redo this\n\tlocal tmpfrs1 = frs1D;\n\tlocal tmpfrs2 = frs2D;\n\tfrd = tmpfrs1;\n\tif (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;\n\tif (nan(tmpfrs2)) goto inst_next;\n\tfrd = tmpfrs2;\n\tif (nan(tmpfrs1)) goto inst_next;\n\tif (tmpfrs2 f<= tmpfrs1) goto inst_next;\n\tfrd = tmpfrs1;\n}\n\n\n# fmsub.d D,S,T,R,m 02000047 0600007f SIMPLE (0, 0) \n:fmsub.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1\n{\n\tfrd = (frs1D f* frs2D) f- frs3D;\n}\n\n\n# fmul.d D,S,T,m 12000053 fe00007f SIMPLE (0, 0) \n:fmul.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9\n{\n\tfrd = frs1D f* frs2D;\n}\n\n\n# fnmadd.d D,S,T,R,m 0200004f 0600007f SIMPLE (0, 0) \n:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1\n{\n\tfrd = (f- (frs1D f* frs2D)) f- frs3D;\n}\n\n\n# fnmsub.d D,S,T,R,m 0200004b 0600007f SIMPLE (0, 0) \n:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1\n{\n\tfrd = (f- (frs1D f* frs2D)) f+ frs3D;\n}\n\n\n# fsd T,q(s) 00003027 0000707f QWORD|DREF (0, 8) \n:fsd frs2D,immS(rs1) is frs2D & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x3\n{\n\tlocal ea:$(XLEN) = immS + rs1;\n\t*[ram]:$(DFLEN) ea = frs2D;\n}\n\n\n# fsgnj.d D,S,T 22000053 fe00707f SIMPLE (0, 0) \n:fsgnj.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11\n{\n\tlocal tmp:$(DFLEN) = frs1D;\n\ttmp[63,1] = frs2D[63,1];\n\tfrd = tmp;\n}\n\n# fmv.d D,U 22000053 fe00707f ALIAS (0, 0)\n:fmv.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519=op2024\n{\n\tfrd = frs1D;\n}\n\n\n# fsgnjn.d D,S,T 22001053 fe00707f SIMPLE (0, 0) \n:fsgnjn.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11\n{\n\tlocal tmp:$(DFLEN) = frs1D;\n\ttmp[63,1] = !frs2D[63,1];\n\tfrd = tmp;\n}\n\n# fneg.d D,U 22001053 fe00707f ALIAS (0, 0)\n:fneg.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519=op2024\n{\n\tfrd = f- frs1D;\n}\n\n\n# fsgnjx.d D,S,T 22002053 fe00707f SIMPLE (0, 0) \n:fsgnjx.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11\n{\n\tlocal tmp:$(DFLEN) = frs1D;\n\ttmp[63,1] = tmp[63,1] ^ frs2D[63,1];\n\tfrd = tmp;\n}\n\n# fabs.d D,U 22002053 fe00707f ALIAS (0, 0)\n:fabs.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519=op2024\n{\n\tfrd = abs(frs1D);\n}\n\n\n# fsqrt.d D,S,m 5a000053 fff0007f SIMPLE (0, 0) \n:fsqrt.d frd,frs1D,FRM is frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0\n{\n\tfrd = sqrt(frs1D);\n}\n\n\n# fsub.d D,S,T,m 0a000053 fe00007f SIMPLE (0, 0) \n:fsub.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5\n{\n\tfrd = frs1D f- frs2D;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32f.sinc", "content": "# RV32F Standard Extension\n\n# fadd.s D,S,T,m 00000053 fe00007f SIMPLE (0, 0) \n:fadd.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0\n{\n\tlocal tmp:4 = frs1S f+ frs2S;\n\tfassignS(frd, tmp);\n}\n\n\n# fclass.s d,S e0001053 fff0707f SIMPLE (0, 0) \n:fclass.s rd,frs1S is frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x70 & op2024=0x0\n{\n\t#TODO\n\t# rd = 0;\n\t# rd[0, 1] = 0; #TODO - inf\n\t# rd[1, 1] = 0; #TODO - norm num\n\t# rd[2, 1] = 0; #TODO - subnorm num\n\t# rd[3, 1] = 0; #TODO - 0\n\t# rd[4, 1] = 0; #TODO + 0\n\t# rd[5, 1] = 0; #TODO + norm num\n\t# rd[6, 1] = 0; #TODO + subnorm num\n\t# rd[7, 1] = 0; #TODO + inf\n\t# rd[8, 1] = 0; #TODO snan\n\t# rd[9, 1] = 0; #TODO qnan\n}\n\n\n# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0) \n:fcvt.s.w frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0\n{\n\tlocal tmp:4 = int2float(rs1W);\n\tfassignS(frd, tmp);\n}\n\n\n# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0) \n:fcvt.s.wu frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1\n{\n\t#ATTN unsigned can be an issue here\n\tlocal u32:$(XLEN2) = zext(rs1W);\n\tlocal tmp:4 = int2float(u32);\n\tfassignS(frd, tmp);\n}\n\n\n# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0) \n:fcvt.w.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0\n{\n\trdW = trunc(frs1S);\n}\n\n\n# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0) \n:fcvt.wu.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1\n{\n\t#TODO unsigned\n\trdW = trunc(frs1S);\n}\n\n\n# fdiv.s D,S,T,m 18000053 fe00007f SIMPLE (0, 0) \n:fdiv.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc\n{\n\tlocal tmp:4 = frs1S f/ frs2S;\n\tfassignS(frd, tmp);\n}\n\n\n# feq.s d,S,T a0002053 fe00707f SIMPLE (0, 0) \n:feq.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x50\n{\n\trd = zext(frs1S f== frs2S);\n}\n\n\n# fle.s d,S,T a0000053 fe00707f SIMPLE (0, 0) \n:fle.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50\n{\n\trd = zext(frs1S f<= frs2S);\n}\n\n\n# flt.s d,S,T a0001053 fe00707f SIMPLE (0, 0) \n:flt.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50\n{\n\trd = zext(frs1S f< frs2S);\n}\n\n\n# flw D,o(s) 00002007 0000707f DWORD|DREF (0, 4) \n:flw frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x2\n{\n\tlocal ea:$(XLEN) = immI + rs1;\n\tfassignS(frd, *[ram]:4 ea);\n}\n\n\n# fmadd.s D,S,T,R,m 00000043 0600007f SIMPLE (0, 0) \n:fmadd.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0\n{\n\tlocal tmp:4 = (frs1S f* frs2S) f+ frs3S;\n\tfassignS(frd, tmp);\n}\n\n\n# fmax.s D,S,T 28001053 fe00707f SIMPLE (0, 0) \n:fmax.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x14\n{\n\t#TODO redo this\n\tlocal tmpfrs1 = frs1S;\n\tlocal tmpfrs2 = frs2S;\n\tfassignS(frd, tmpfrs1);\n\tif (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;\n\tif (nan(tmpfrs2)) goto inst_next;\n\tfassignS(frd, tmpfrs2);\n\tif (nan(tmpfrs1)) goto inst_next;\n\tif (tmpfrs2 f>= tmpfrs1) goto inst_next;\n\tfassignS(frd, tmpfrs1);\n}\n\n\n# fmin.s D,S,T 28000053 fe00707f SIMPLE (0, 0) \n:fmin.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x14\n{\n\t#TODO redo this\n\tlocal tmpfrs1 = frs1S;\n\tlocal tmpfrs2 = frs2S;\n\tfassignS(frd, tmpfrs1);\n\tif (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;\n\tif (nan(tmpfrs2)) goto inst_next;\n\tfassignS(frd, tmpfrs2);\n\tif (nan(tmpfrs1)) goto inst_next;\n\tif (tmpfrs2 f<= tmpfrs1) goto inst_next;\n\tfassignS(frd, tmpfrs1);\n}\n\n\n# fmsub.s D,S,T,R,m 00000047 0600007f SIMPLE (0, 0) \n:fmsub.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0\n{\n\tlocal tmp:4 = (frs1S f* frs2S) f- frs3S;\n\tfassignS(frd, tmp);\n}\n\n\n# fmul.s D,S,T,m 10000053 fe00007f SIMPLE (0, 0) \n:fmul.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8\n{\n\tlocal tmp:4 = frs1S f* frs2S;\n\tfassignS(frd, tmp);\n}\n\n\n# fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0) \n:fmv.w.x frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0\n{\n\tfassignS(frd, rs1W);\n}\n\n# fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0) \n:fmv.x.w rdW,frs1S is frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0\n{\n\tlocal tmpreg:4 = &frs1S;\n\tlocal tmp:4 = *[register]:4 tmpreg;\n\trdW = tmp;\n}\n\n\n# fnmadd.s D,S,T,R,m 0000004f 0600007f SIMPLE (0, 0) \n:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0\n{\n\tlocal tmp:4 = (f- (frs1S f* frs2S)) f- frs3S;\n\tfassignS(frd, tmp);\n}\n\n\n# fnmsub.s D,S,T,R,m 0000004b 0600007f SIMPLE (0, 0) \n:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0\n{\n\tlocal tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S;\n\tfassignS(frd, tmp);\n}\n\n\n# fsgnj.s D,S,T 20000053 fe00707f SIMPLE (0, 0) \n:fsgnj.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10\n{\n\tlocal tmp:$(SFLEN) = frs1S;\n\ttmp[31,1] = frs2S[31,1];\n\tfassignS(frd, tmp);\n}\n\n# fmv.s D,U 20000053 fe00707f ALIAS (0, 0)\n:fmv.s frd,frs1S is frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519=op2024\n{\n\tfassignS(frd, frs1S);\n}\n\n\n# fsgnjn.s D,S,T 20001053 fe00707f SIMPLE (0, 0) \n:fsgnjn.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10\n{\n\tlocal tmp:$(SFLEN) = frs1S;\n\ttmp[31,1] = !frs2S[31,1];\n\tfassignS(frd, tmp);\n}\n\n# fneg.s D,U 20001053 fe00707f ALIAS (0, 0)\n:fneg.s frd,frs1S is frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519=op2024\n{\n\tlocal tmp:4 = f- frs1S;\n\tfassignS(frd, tmp);\n}\n\n\n# fsgnjx.s D,S,T 20002053 fe00707f SIMPLE (0, 0) \n:fsgnjx.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10\n{\n\tlocal tmp:$(SFLEN) = frs1S;\n\ttmp[31,1] = tmp[31,1] ^ frs2S[31,1];\n\tfassignS(frd, tmp);\n}\n\n# fabs.s D,U 20002053 fe00707f ALIAS (0, 0)\n:fabs.s frd,frs1S is frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519=op2024\n{\n\tlocal tmp:4 = abs(frs1S);\n\tfassignS(frd, tmp);\n}\n\n\n# fsqrt.s D,S,m 58000053 fff0007f SIMPLE (0, 0) \n:fsqrt.s frd,frs1S,FRM is frs1S & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0\n{\n\tlocal tmp:4 = sqrt(frs1S);\n\tfassignS(frd, tmp);\n}\n\n\n# fsub.s D,S,T,m 08000053 fe00007f SIMPLE (0, 0) \n:fsub.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4\n{\n\tlocal tmp:4 = frs1S f- frs2S;\n\tfassignS(frd, tmp);\n}\n\n\n# fsw T,q(s) 00002027 0000707f DWORD|DREF (0, 4) \n:fsw frs2S,immS(rs1) is frs2S & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x2\n{\n\tlocal ea:$(XLEN) = immS + rs1;\n\t*[ram]:$(SFLEN) ea = frs2S;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32i.sinc", "content": "# RV32I Base Instruction Set\n\n# add d,s,t 00000033 fe00707f SIMPLE (0, 0) \n:add rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x0\n{\n\trd = rs1 + rs2;\n}\n\n\n# addi d,s,j 00000013 0000707f SIMPLE (0, 0) \n:addi rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0\n{\n\trd = rs1 + immI;\n}\n\n# nop 00000013 ffffffff ALIAS (0, 0)\n:nop is op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op0711=0x0 & op1531=0x0\n{\n\tlocal NOP:1 = 0;\n\tNOP = NOP;\n}\n\n# mv d,s 00000013 fff0707f ALIAS (0, 0)\n:mv rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0\n{\n\trd = rs1;\n}\n\n# li d,j 00000013 000ff07f ALIAS (0, 0)\n:li rd,immI is immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0\n{\n\t#TODO alias of addi rd,zero,0x0 is an issue\n\trd = immI;\n}\n\n# Resolve conflict between: mv rd,zero and li rd,0x0\n# ATTN this implementation uses mv rd,zero\n:mv rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1531=0x0\n{\n\trd = rs1;\n}\n\n\n# and d,s,t 00007033 fe00707f SIMPLE (0, 0) \n:and rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0\n{\n\trd = rs1 & rs2;\n}\n\n\n# andi d,s,j 00007013 0000707f SIMPLE (0, 0) \n:andi rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7\n{\n\trd = rs1 & immI;\n}\n\n\n# auipc d,u 00000017 0000007f SIMPLE (0, 0) \n:auipc rd,immU is immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x0\n{\n\trd = immU + inst_start;\n}\n\n\n# beq s,t,p 00000063 0000707f CONDBRANCH (0, 0) \n:beq rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0\n{\n\tif (rs1 == rs2) goto immSB;\n}\n\n\n# bge s,t,p 00005063 0000707f CONDBRANCH (0, 0) \n:bge rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5\n{\n\tif (rs1 s>= rs2) goto immSB;\n}\n\n\n# bgeu s,t,p 00007063 0000707f CONDBRANCH (0, 0) \n:bgeu rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7\n{\n\tif (rs1 >= rs2) goto immSB;\n}\n\n\n# blt s,t,p 00004063 0000707f CONDBRANCH (0, 0) \n:blt rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4\n{\n\tif (rs1 s< rs2) goto immSB;\n}\n\n\n# bltu s,t,p 00006063 0000707f CONDBRANCH (0, 0) \n:bltu rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6\n{\n\tif (rs1 < rs2) goto immSB;\n}\n\n\n# bne s,t,p 00001063 0000707f CONDBRANCH (0, 0) \n:bne rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1\n{\n\tif (rs1 != rs2) goto immSB;\n}\n\n# ebreak 00100073 ffffffff SIMPLE (0, 0) \n:ebreak is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20\n{\n\tebreak();\n}\n\n# ecall 00000073 ffffffff SIMPLE (0, 0) \n:ecall is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x0\n{\n\tecall();\n}\n\n\n# fence P,Q 0000000f f00fffff SIMPLE (0, 0) \n:fence pred,succ is pred & succ & op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1519=0x0\n{\n\tfence();\n}\n\n# jal d,a 0000006f 0000007f JSR (0, 0) \n# call for rd = RA|T0 set to inst_next\n:jal rd,immUJ is immUJ & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x3 & op0506=0x3\n{\n\trd = inst_next;\n\tcall immUJ;\n}\n\n# goto for all other rd set to inst_next\n:jal rd,immUJ is immUJ & rd & r0711 & op0001=0x3 & op0204=0x3 & op0506=0x3\n{\n\trd = inst_next;\n\tgoto immUJ;\n}\n\n# j a 0000006f 00000fff BRANCH|ALIAS (0, 0)\n:j immUJ is immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x0\n{\n\tgoto immUJ;\n}\n\n# jalr d,s,j 00000067 0000707f JSR (0, 0)\n# call for rd = RA|T0 set to inst_next\n:jalr rd,rs1,immI is rs1 & immI & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0\n{\n\tlocal ea:$(XLEN) = (rs1 + immI) & ~1;\n\trd = inst_next;\n\tcall [ea];\n}\n\n# goto for all other rd set to inst_next\n:jalr rd,rs1,immI is rs1 & immI & rd & r0711 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0\n{\n\tlocal ea:$(XLEN) = (rs1 + immI) & ~1;\n\trd = inst_next;\n\tgoto [ea];\n}\n\n# jr o(s) 00000067 00007fff BRANCH|ALIAS (0, 0)\n:jr immI(rs1) is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0\n{\n\tlocal ea:$(XLEN) = (rs1 + immI) & ~1;\n\tgoto [ea];\n}\n\n# jr s 00000067 fff07fff BRANCH|ALIAS (0, 0)\n:jr rs1 is rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0\n{\n\tlocal ea:$(XLEN) = rs1 & ~1;\n\tgoto [ea];\n}\n\n# ret 00008067 ffffffff BRANCH|ALIAS (0, 0)\n:ret is op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519=1\n{\n\tlocal ea:$(XLEN) = ra & ~1;\n\treturn [ea];\n}\n\n\n# lb d,o(s) 00000003 0000707f BYTE|DREF (0, 1) \n:lb rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x0\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\trd = sext(*[ram]:1 ea);\n}\n\n\n# lbu d,o(s) 00004003 0000707f BYTE|DREF (0, 1) \n:lbu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x4\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\trd = zext(*[ram]:1 ea);\n}\n\n\n# lh d,o(s) 00001003 0000707f WORD|DREF (0, 2) \n:lh rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x1\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\trd = sext(*[ram]:2 ea);\n}\n\n\n# lhu d,o(s) 00005003 0000707f WORD|DREF (0, 2) \n:lhu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x5\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\trd = zext(*[ram]:2 ea);\n}\n\n\n# lui d,u 00000037 0000007f SIMPLE (0, 0) \n:lui rd,immU is immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x1\n{\n\trd = immU;\n}\n\n\n# lw d,o(s) 00002003 0000707f DWORD|DREF (0, 4) \n:lw rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x2\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\tassignW(rd, *[ram]:4 ea);\n}\n\n\n# or d,s,t 00006033 fe00707f SIMPLE (0, 0) \n:or rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x0\n{\n\trd = rs1 | rs2;\n}\n\n\n# ori d,s,j 00006013 0000707f SIMPLE (0, 0) \n:ori rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6\n{\n\trd = rs1 | immI;\n}\n\n\n# sb t,q(s) 00000023 0000707f BYTE|DREF (0, 1) \n:sb rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x0\n{\n\tlocal ea:$(XLEN) = rs1 + immS;\n\t*[ram]:1 ea = rs2:1;\n}\n\n\n# sh t,q(s) 00001023 0000707f WORD|DREF (0, 2) \n:sh rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x1\n{\n\tlocal ea:$(XLEN) = rs1 + immS;\n\t*[ram]:2 ea = rs2:2; \n}\n\n\n# sll d,s,t 00001033 fe00707f SIMPLE (0, 0) \n:sll rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x0\n{\n\tlocal shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1);\n\trd = rs1 << shift;\n}\n\n\n# slli d,s,> 00001013 fc00707f SIMPLE (0, 0) \n:slli rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0\n{\n\trd = rs1 << shamt6;\n}\n\n\n# slt d,s,t 00002033 fe00707f SIMPLE (0, 0) \n:slt rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0\n{\n\trd = zext(rs1 s< rs2);\n}\n\n\n# slti d,s,j 00002013 0000707f SIMPLE (0, 0) \n:slti rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2\n{\n\trd = zext(rs1 s< immI);\n}\n\n\n# sltiu d,s,j 00003013 0000707f SIMPLE (0, 0) \n:sltiu rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3\n{\n\trd = zext(rs1 < immI);\n}\n\n\n# sltu d,s,t 00003033 fe00707f SIMPLE (0, 0) \n:sltu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0\n{\n\trd = zext(rs1 < rs2);\n}\n\n\n# sra d,s,t 40005033 fe00707f SIMPLE (0, 0) \n:sra rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x20\n{\n\tlocal shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1);\n\trd = rs1 s>> shift;\n}\n\n\n# srai d,s,> 40005013 fc00707f SIMPLE (0, 0) \n:srai rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10\n{\n\trd = rs1 s>> shamt6;\n}\n\n\n# srl d,s,t 00005033 fe00707f SIMPLE (0, 0) \n:srl rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x0\n{\n\tlocal shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1);\n\trd = rs1 >> shift;\n}\n\n\n# srli d,s,> 00005013 fc00707f SIMPLE (0, 0) \n:srli rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0\n{\n\trd = rs1 >> shamt6;\n}\n\n\n# sub d,s,t 40000033 fe00707f SIMPLE (0, 0) \n:sub rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20\n{\n\trd = rs1 - rs2;\n}\n\n# neg d,t 40000033 fe0ff07f ALIAS (0, 0)\n:neg rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0\n{\n\trd = -rs2;\n}\n\n\n# sw t,q(s) 00002023 0000707f DWORD|DREF (0, 4) \n:sw rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x2\n{\n\tlocal ea:$(XLEN) = rs1 + immS;\n\t*[ram]:4 ea = rs2:4;\n}\n\n\n# unimp c0001073 ffffffff SIMPLE (0, 0) \n:unimp is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000\n{\n local excaddr:$(XLEN) = inst_start;\n local target:$(XLEN) = unimp(excaddr);\n goto [target];\n}\n\n\n# xor d,s,t 00004033 fe00707f SIMPLE (0, 0) \n:xor rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x0\n{\n\trd = rs1 ^ rs2;\n}\n\n\n# xori d,s,j 00004013 0000707f SIMPLE (0, 0) \n:xori rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4\n{\n\trd = rs1 ^ immI;\n}\n\n# not d,s fff04013 fff0707f ALIAS (0, 0)\n:not rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031=0xfff\n{\n\trd = ~rs1;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32k.sinc", "content": "# RV32 Crypto Extension\n# NOTE 0.6.2\n\n# bs 00001 rs2 rs1 010 rd 0101011 saes32.encs\n:saes32.encs rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x1 unimpl\n\n# bs 00000 rs2 rs1 010 rd 0101011 saes32.encsm\n:saes32.encsm rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x0 unimpl\n\n# bs 00011 rs2 rs1 010 rd 0101011 saes32.decs\n:saes32.decs rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x3 unimpl\n\n# bs 00010 rs2 rs1 010 rd 0101011 saes32.decsm\n:saes32.decsm rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x2 unimpl\n\n# 0000111 00000 rs1 111 rd 0101011 ssha256.sig0\n:ssha256.sig0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x00 & op2531=0x07 unimpl\n\n# 0000111 00001 rs1 111 rd 0101011 ssha256.sig1\n:ssha256.sig1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x01 & op2531=0x07 unimpl\n\n# 0000111 00010 rs1 111 rd 0101011 ssha256.sum0\n:ssha256.sum0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x02 & op2531=0x07 unimpl\n\n# 0000111 00011 rs1 111 rd 0101011 ssha256.sum1\n:ssha256.sum1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x03 & op2531=0x07 unimpl\n\n# 0001100 rs2 rs1 111 rd 0101011 ssha512.sum0r\n:ssha512.sum0r rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0c unimpl\n\n# 0001101 rs2 rs1 111 rd 0101011 ssha512.sum1r\n:ssha512.sum1r rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0d unimpl\n\n# 0001000 rs2 rs1 111 rd 0101011 ssha512.sig0l\n:ssha512.sig0l rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x08 unimpl\n\n# 0001001 rs2 rs1 111 rd 0101011 ssha512.sig0h\n:ssha512.sig0h rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x09 unimpl\n\n# 0001010 rs2 rs1 111 rd 0101011 ssha512.sig1l\n:ssha512.sig1l rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0a unimpl\n\n# 0001011 rs2 rs1 111 rd 0101011 ssha512.sig1h\n:ssha512.sig1h rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0b unimpl\n\n# 0000111 01000 rs1 111 rd 0101011 ssm3.p0\n:ssm3.p0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x08 & op2531=0x07 unimpl\n\n# 0000111 01001 rs1 111 rd 0101011 ssm3.p1\n:ssm3.p1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x09 & op2531=0x07 unimpl\n\n# bs 00100 rs2 rs1 011 rd 0101011 ssm4.ed\n:ssm4.ed rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x3 & op2529=0x4 unimpl\n\n# bs 00101 rs2 rs1 011 rd 0101011 ssm4.ks\n:ssm4.ks rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x3 & op2529=0x5 unimpl\n\n# 0000111 shamtw 01010 111 rd 0101011 pollentropy\n:pollentropy rd, shamtw is rd & shamtw & op0006=0x2b & op1214=0x7 & op1519=0x0a & op2531=0x07 unimpl" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32m.sinc", "content": "# RV32M Standard Extension\n\n# div d,s,t 02004033 fe00707f SIMPLE (0, 0) \n:div rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1\n{\n\trd = rs1 s/ rs2;\n}\n\n\n# divu d,s,t 02005033 fe00707f SIMPLE (0, 0) \n:divu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1\n{\n\trd = rs1 / rs2;\n}\n\n\n# mul d,s,t 02000033 fe00707f SIMPLE (0, 0) \n:mul rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x1\n{\n\trd = rs1 * rs2;\n}\n\n\n# mulh d,s,t 02001033 fe00707f SIMPLE (0, 0) \n:mulh rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x1\n{\n\tlocal trs1:$(XLEN2) = sext(rs1);\n\tlocal trs2:$(XLEN2) = sext(rs2);\n\tlocal tmp:$(XLEN2) = trs1 * trs2;\n\trd = tmp($(XLEN));\n}\n\n\n# mulhsu d,s,t 02002033 fe00707f SIMPLE (0, 0) \n:mulhsu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x1\n{\n\tlocal trs1:$(XLEN2) = sext(rs1);\n\tlocal trs2:$(XLEN2) = zext(rs2);\n\tlocal tmp:$(XLEN2) = trs1 * trs2;\n\trd = tmp($(XLEN));\n}\n\n\n# mulhu d,s,t 02003033 fe00707f SIMPLE (0, 0) \n:mulhu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x1\n{\n\tlocal trs1:$(XLEN2) = zext(rs1);\n\tlocal trs2:$(XLEN2) = zext(rs2);\n\tlocal tmp:$(XLEN2) = trs1 * trs2;\n\trd = tmp($(XLEN));\n}\n\n\n# rem d,s,t 02006033 fe00707f SIMPLE (0, 0) \n:rem rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1\n{\n\trd = rs1 s% rs2;\n}\n\n\n# remu d,s,t 02007033 fe00707f SIMPLE (0, 0) \n:remu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1\n{\n\trd = rs1 % rs2;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32p.sinc", "content": "# RV32 P Extension\n\n\n# add16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] + rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:add16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x20\n{\n\tlocal tmp1:$(XLEN) = rs1;\n\tlocal tmp2:$(XLEN) = rs2;\n\trd[ 0,16] = tmp1[ 0,16] + tmp2[ 0,16];\n\trd[16,16] = tmp1[16,16] + tmp2[16,16];\n@if ADDRSIZE == \"64\"\n\trd[32,16] = tmp1[32,16] + tmp2[32,16];\n\trd[48,16] = tmp1[48,16] + tmp2[48,16];\n@endif\n}\n\n\n# add64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = a64 + b64; + ; + ; r[tU].r[tL] = t64;\n:add64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x60\n{\n@if ADDRSIZE == \"32\"\n\tlocal dst:$(XLEN) = &rd;\n\tlocal src1:$(XLEN) = &rs1;\n\tlocal src2:$(XLEN) = &rs2;\n \t*[register]:8 dst = *[register]:8 src1 + *[register]:8 src2;\n@else\n\trd = rs1 + rs2;\n@endif\n}\n\n\n# add8 rt, ra, rb \t ; rt.B[_x_] = ra.B[_x_] + rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:add8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x24\n{\n\tlocal tmp1:$(XLEN) = rs1;\n\tlocal tmp2:$(XLEN) = rs2;\n\trd[ 0,8] = tmp1[ 0,8] + tmp2[ 0,8];\n\trd[ 8,8] = tmp1[ 8,8] + tmp2[ 8,8];\n\trd[16,8] = tmp1[16,8] + tmp2[16,8];\n\trd[24,8] = tmp1[24,8] + tmp2[24,8];\n@if ADDRSIZE == \"64\"\n\trd[32,8] = tmp1[32,8] + tmp2[32,8];\n\trd[40,8] = tmp1[40,8] + tmp2[40,8];\n\trd[48,8] = tmp1[48,8] + tmp2[48,8];\n\trd[56,8] = tmp1[56,8] + tmp2[56,8];\n@endif\n}\n\n\n# ave rt, ra, rb \t\n:ave rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x70\n{\n\tlocal tmp:$(XLEN) = rs1 + rs2;\n\trd = (tmp / 2) + (tmp & 1);\n}\n\n\n# bitrev rt, ra, rb \t ; msb = rb[4:0]; // RV32 ; msb = rb[5:0]; // RV64 ; rev[0:msb] = ra[msb:0]; ; rt = ZE(rev[msb:0]);\n:bitrev rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x73 unimpl\n\n\n# bitrevi rt, ra, imm5u \t ; msb = imm5u; // RV32 ; msb = imm6u; // RV64 ; rev[0:msb] = ra[msb:0]; ; rt = ZE(rev[msb:0]);\n:bitrevi rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x74 unimpl\n\n\n# bpick rt, ra, rb, rc \t ; rt[_i_] = rc[_i_]? ra[_i_] : rb[_i_]; + ; (RV32: __i__=31..0, RV64: __i__=63..0)\n:bpick rd,rs1,rs2,rs3 is op0006=0x3f & rd & rs1 & rs2 & rs3 & funct3=0x3 & funct7=0x00 unimpl\n\n\n# bpick rt, ra, rb, rc \t ; rt[_i_] = rc[_i_]? ra[_i_] : rb[_i_]; + ; (RV32: __i__=31..0, RV64: __i__=63..0)\n:bpick rd,rs1,rs2,rs3 is op0006=0x3f & rd & rs1 & rs2 & rs3 & funct3=0x3 & funct7=0x04 unimpl\n\n\n# clo16 rt, ra \t\n:clo16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x0a unimpl\n\n\n# clo32 rt, ra \t ; rt.W[_x_] = CLO(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0)\n:clo32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x12 unimpl\n\n\n# clo8 rt, ra \t\n:clo8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x02 unimpl\n\n\n# clrs16 rt, ra \t\n:clrs16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x08 unimpl\n\n\n# clrs32 rt, ra \t ; rt.W[_x_] = CLRS(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0)\n:clrs32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x10 unimpl\n\n\n# clrs8 rt, ra \t\n:clrs8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x00 unimpl\n\n\n# clz16 rt, ra \t\n:clz16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x09 unimpl\n\n\n# clz32 rt, ra \t ; rt.W[_x_] = CLZ(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0)\n:clz32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x11 unimpl\n\n\n# clz8 rt, ra \t\n:clz8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x01 unimpl\n\n\n# cmpeq16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] == rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:cmpeq16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x26 unimpl\n\n\n# cmpeq8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] == rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:cmpeq8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x27 unimpl\n\n\n# cras16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] + rb.H[_x-1_]; + ; rt.H[_x-1_] = ra.H[_x-1_] – rb.H[_x_]; ; (RV32: __x__=1, RV64: __x__=1,3)\n:cras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x22 unimpl\n\n\n# crsa16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] - rb.H[_x-1_]; + ; rt.H[_x-1_] = ra.H[_x-1_] + rb.H[_x_]; ; (RV32: __x__=1, RV64: __x__=1,3)\n:crsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x23 unimpl\n\n\n# insb rt, ra, imm3u \t ; byte_idx = imm2u; // RV32 ; byte_idx = imm3u; // RV64 ; rt.B[byte_idx] = ra.B[0];\n:insb rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x00 unimpl\n\n\n# kabs16 rt, ra \t ; rt.H[_x_] = SAT.Q15(ABS(ra.H[_x_])); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:kabs16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x11 unimpl\n\n\n# kabs32 rt, ra \t ; rt.W[_x_] = SAT.Q31(ABS(ra.W[_x_])); ; (RV64: __x__=1..0)\n:kabs32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x12 unimpl\n\n\n# kabs8 rt, ra \t ; rt.B[_x_] = SAT.Q7(ABS(ra.B[_x_])); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:kabs8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x10 unimpl\n\n\n# kabsw rt, ra \t ; rt = SAT.Q31(ABS(ra)); // RV32 ; rt = SE(SAT.Q31(ABS(ra.W[_0_]))); // RV64\n:kabsw rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x14 unimpl\n\n\n# kadd16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:kadd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x08 unimpl\n\n\n# kadd64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.Q63(a64 + b64); + ; + ; r[tU].r[tL] = t64;\n:kadd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x48 unimpl\n\n\n# kadd8 rt, ra, rb \t ; rt.B[_x_] = SAT.Q7(ra.B[_x_] + rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:kadd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0c unimpl\n\n\n:kaddh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x02 unimpl\n\n\n:kaddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x00 unimpl\n\n\n# kcras16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] – rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:kcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0a unimpl\n\n\n# kcrsa16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] + rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:kcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0b unimpl\n\n\n:kdmabb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x69 unimpl\n\n\n:kdmabb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6b unimpl\n\n\n:kdmabt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x71 unimpl\n\n\n:kdmabt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x74 unimpl\n\n\n:kdmatt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x79 unimpl\n\n\n:kdmatt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7c unimpl\n\n\n:kdmbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x05 unimpl\n\n\n:kdmbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6c unimpl\n\n\n:kdmbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0d unimpl\n\n\n:kdmbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x75 unimpl\n\n\n:kdmtt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x15 unimpl\n\n\n:kdmtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7d unimpl\n\n\n# khm16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15((ra.H[_x_] s* rb.H[_x_]) >> 15); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:khm16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x43 unimpl\n\n\n# khm8 rt, ra, rb \t ; rt.B[_x_] = SAT.Q7((ra.B[_x_] s* rb.B[_x_]) >> 7); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:khm8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x47 unimpl\n\n\n:khmbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x06 unimpl\n\n\n:khmbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6d unimpl\n\n\n:khmbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0e unimpl\n\n\n:khmbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x76 unimpl\n\n\n:khmtt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x16 unimpl\n\n\n:khmtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7e unimpl\n\n\n# khmx16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15((ra.H[_x_] s* rb.H[_y_]) >> 15); ; (RV32: (_x,y_)=(1,0), (0,1), + ; RV64: (_x,y_)=(3,2),(2,3),(1,0), (0,1))\n:khmx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4b unimpl\n\n\n# khmx8 rt, ra, rb \t ; rt.B[_x_] = SAT.Q7((ra.B[_x_] s* rb.B[_y_]) >> 7); ; (RV32: (_x,y_)=(3,2),(2,3),(1,0), (0,1), + ; RV64: (_x,y_)=(7,6),(6,7),(5,4), (4,5), (3,2), (2,3), (1,0), (0,1))\n:khmx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4f unimpl\n\n\n# kmabb rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmabb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2d unimpl\n\n\n# kmabt rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmabt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x35 unimpl\n\n\n# kmada rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmada rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x24 unimpl\n\n\n# kmadrs rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[0] - ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmadrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x36 unimpl\n\n\n# kmads rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1] - ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmads rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2e unimpl\n\n\n# kmar64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.Q63(c64 + ra*rb); + ; + ; r[tU].r[tL] = t64;\n:kmar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4a unimpl\n\n\n# kmatt rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmatt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3d unimpl\n\n\n# kmaxda rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[0] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmaxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x25 unimpl\n\n\n# kmaxds rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[0] - ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmaxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3e unimpl\n\n\n# kmda rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_].H[1]*rb.W[_x_].H[1] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1c unimpl\n\n\n# kmmac rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_])[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmac rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x30 unimpl\n\n\n:kmmac.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x38 unimpl\n\n\n# kmmawb rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_].H[0])[47:16]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmawb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x23 unimpl\n\n\n:kmmawb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2b unimpl\n\n\n# kmmawb2 rt, ra, rb \t ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].L==0x8000)) \\{ ; t[_x_]=0x7fffffff; OV=1;} else \\{ ; t[_x_]= ((a[_x_]*b[_x_].L)<<1)[47:16]; ; } ; rt.W[_x_] = SAT.Q31(rt.W[x] + t[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmawb2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x67 unimpl\n\n\n:kmmawb2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6e unimpl\n\n\n# kmmawt rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_].H[1])[47:16]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmawt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x33 unimpl\n\n\n:kmmawt.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3b unimpl\n\n\n# kmmsb rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - (ra.W[_x_]*rb.W[_x_])[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmsb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x21 unimpl\n\n\n:kmmsb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x29 unimpl\n\n\n# kmmwb2 rt, ra, rb \t ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].L==0x8000)) \\{ ; t[_x_]=0x7fffffff; OV=1;} else \\{ ; t[_x_]= ((a[_x_]*b[_x_].L)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmwb2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x47 unimpl\n\n\n:kmmwb2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4f unimpl\n\n\n# kmmwt2 rt, ra, rb \t ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].H==0x8000)) \\{ ; t[_x_]=0x7fffffff; OV=1;} else \\{ ; t[_x_]= ((a[_x_]*b[_x_].H)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmwt2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x57 unimpl\n\n\n# kmmwt2 rt, ra, rb \t ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].H==0x8000)) \\{ ; t[_x_]=0x7fffffff; OV=1;} else \\{ ; t[_x_]= ((a[_x_]*b[_x_].H)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmmwt2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x77 unimpl\n\n\n:kmmwt2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5f unimpl\n\n\n:kmmwt2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7f unimpl\n\n\n# kmsda rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - ra.W[_x_].H[1]*rb.W[_x_].H[1] - ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmsda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x26 unimpl\n\n\n# kmsr64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.Q63(c64 – ra*rb); + ; + ; r[tU].r[tL] = t64;\n:kmsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4b unimpl\n\n\n# kmsxda rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - ra.W[_x_].H[1]*rb.W[_x_].H[0] - ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmsxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x27 unimpl\n\n\n# kmxda rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_].H[1]*rb.W[_x_].H[0] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kmxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1d unimpl\n\n\n:ksll rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x13 unimpl\n\n\n# ksll16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] << im4u); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:ksll16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x32 unimpl\n\n\n# ksll8 rt, ra, rb \t ; rt.B[_x_] = SAT.Q7(ra.B[_x_] << rb[2:0]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:ksll8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x36 unimpl\n\n\n:kslli rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1b unimpl\n\n\n# kslra16 rt, ra, rb \t ; if (rb[4:0] < 0) + ; rt.H[_x_] = ra.H[_x_] s>> -rb[4:0]; ; if (rb[4:0] > 0) + ; rt.H[_x_] = SAT.Q15(ra.H[_x_] << rb[4:0]); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:kslra16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2b unimpl\n\n\n:kslra16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x33 unimpl\n\n\n# kslra8 rt, ra, rb \t ; if (rb[3:0] < 0) + ; rt.B[_x_] = ra.B[_x_] s>> -rb[3:0]; ; if (rb[3:0] > 0) + ; rt.B[_x_] = SAT.Q7(ra.B[_x_] << rb[3:0]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:kslra8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2f unimpl\n\n\n:kslra8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x37 unimpl\n\n\n:kslraw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x37 unimpl\n\n\n:kslraw.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3f unimpl\n\n\n# ksub16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:ksub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x09 unimpl\n\n\n# ksub64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.Q63(a64 - b64); + ; + ; r[tU].r[tL] = t64;\n:ksub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x49 unimpl\n\n\n# ksub8 rt, ra, rb \t ; rt.B[_x_] = SAT.Q7(ra.B[_x_] - rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:ksub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0d unimpl\n\n\n:ksubh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x03 unimpl\n\n\n:ksubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x01 unimpl\n\n\n# kwmmul rt, ra, rb \t ; rt.W[_x_] = SAT.Q31((ra.W[_x_]*rb.W[_x_] << 1)[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:kwmmul rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x31 unimpl\n\n\n:kwmmul.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x39 unimpl\n\n\n# maddr32 rt, ra, tb \t ; 11\n:maddr32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x62 unimpl\n\n\n# maxw rt, ra, rb \t ; if (ra.W[0] >= rb.W[0]) \\{ ; rt = SE(ra.W[0]); ; else \\{ ; rt = SE(rb.W[0]); ; }\n:maxw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x79 unimpl\n\n\n# minw rt, ra, rb \t ; if (ra.W[0] >= rb.W[0]) \\{ ; rt = SE(rb.W[0]); ; else \\{ ; rt = SE(ra.W[0]); ; }\n:minw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x78 unimpl\n\n\n# msubr32 rt, ra, tb \t ; === ; <<< ; === RV64 Only Instructions ; The following tables list instructions that are only present in RV64. ; There are 30 SIMD 32-bit addition or subtraction instructions. ; .(RV64 Only) SIMD 32-bit Add/Subtract Instructions ; [cols=\"^.^1,<.^2,<.^2,<.^4\",options=\"header\",]\n:msubr32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x63 unimpl\n\n\n:mtlbi rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7c unimpl\n\n\n:mtlei rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7d unimpl\n\n\n# mulr64 rt, ra, rb \t ; RV32: ; mres[63:0] = ra u* rb; ; r[tU] = mres.W[1]; ; r[tL] = mres.W[0]; ; RV64: ; rt = ra.W[0] u* rb.W[0];\n:mulr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x78 unimpl\n\n\n# mulsr64 rt, ra, rb \t ; RV32: ; mres[63:0] = ra s* rb; ; r[tU] = mres.W[1]; ; r[tL] = mres.W[0]; ; RV64: ; rt = ra.W[0] s* rb.W[0];\n:mulsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x70 unimpl\n\n\n:oneop rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x56 unimpl\n\n\n:oneop2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x57 unimpl\n\n\n# pbsad rt, ra, rb \t ; absdiff[_x_] = ABS(ra.B[_x_] – rb.B[_x_]); ; rt = SUM(absdiff[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:pbsad rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7e unimpl\n\n\n# pbsada rt, ra, rb \t ; absdiff[_x_] = ABS(ra.B[_x_] – rb.B[_x_]); ; rt = rt + SUM(absdiff[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:pbsada rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7f unimpl\n\n\n# pkbb16 rt, ra, rb \t ; rt.W[_x_] = CONCAT(ra.W[_x_].H[0], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:pkbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x07 unimpl\n\n\n# pkbt16 rt, ra, rb \t ; rt.W[_x_] = CONCAT(ra.W[_x_].H[0], rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:pkbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0f unimpl\n\n\n# pktb16 rt, ra, rb \t ; rt.W[_x_] = CONCAT(ra.W[_x_].H[1], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:pktb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1f unimpl\n\n\n# pktt16 rt, ra, rb \t ; rt.W[_x_] = CONCAT(ra.W[_x_].H[1], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:pktt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x17 unimpl\n\n\n# radd16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x_]) s>> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:radd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x00 unimpl\n\n\n# radd64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (a64 + b64) s>>1; + ; + ; r[tU].r[tL] = t64;\n:radd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x40 unimpl\n\n\n# radd8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] + rb.B[_x_]) s>> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:radd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x04 unimpl\n\n\n# raddw rt, ra, rb \t ; res = (ra.W[0] + rb.W[0]) s>> 1; ; rt = SE(res);\n:raddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x10 unimpl\n\n\n# rcras16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x-1_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] – rb.H[_x_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:rcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x02 unimpl\n\n\n# rcrsa16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x-1_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] + rb.H[_x_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:rcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x03 unimpl\n\n\n# rsub16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x_]) s>> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:rsub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x01 unimpl\n\n\n# rsub64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (a64 - b64) s>>1; + ; + ; r[tU].r[tL] = t64;\n:rsub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x41 unimpl\n\n\n# rsub8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] - rb.B[_x_]) s>> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:rsub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x05 unimpl\n\n\n# rsubw rt, ra, rb \t ; res = (ra.W[0] - rb.W[0]) s>> 1; ; rt = SE(res);\n:rsubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x11 unimpl\n\n\n:sclip16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x42 unimpl\n\n:uclip16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x42 unimpl\n\n\n# sclip32 rt, ra, imm5u \t ; n = imm5u; + ; rt = SAT.Qn(ra.W[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:sclip32 rd,rs1,imm5u is op0006=0x3f & rd & rs1 & imm5u & funct3=0x0 & funct7=0x72 unimpl\n\n\n:sclip8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x46 unimpl\n\n:uclip8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=2 & funct3=0x0 & funct7=0x46 unimpl\n\n\n# scmple16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] {le} rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:scmple16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0e unimpl\n\n\n# scmple8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] {le} rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:scmple8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0f unimpl\n\n\n# scmplt16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] < rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:scmplt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x06 unimpl\n\n\n# scmplt8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] < rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:scmplt8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x07 unimpl\n\n\n# sll16 rt, ra, rb \t ; rt.H[_x_] = ra.H__x__ << rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:sll16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2a unimpl\n\n\n# sll8 rt, ra, rb \t ; rt.B[_x_] = ra.B[_x_] << rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:sll8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2e unimpl\n\n\n:slli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x3a unimpl\n\n\n:kslli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x3a unimpl\n\n\n:slli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3e unimpl\n\n\n:kslli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3e unimpl\n\n\n# smal rt, ra, rb \t ; RV32: ; a64 = r[aU].r[aL]; + ; t64 = a64 + rb.W[_0_].H[1]*rb.W[_0_].H[0]; + ; r[tU].r[tL] = t64; ; RV64: ; a64 = ra; + ; rt = a64 + rb.W[_1_].H[1]*rb.W[_1_].H[0] + rb.W[_0_].H[1]*rb.W[_0_].H[0];\n:smal rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2f unimpl\n\n\n# smalbb rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;\n:smalbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x44 unimpl\n\n\n# smalbt rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;\n:smalbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4c unimpl\n\n\n# smalda rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H + ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;\n:smalda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x46 unimpl\n\n\n# smaldrs rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.L - ra.H*rb.H; + ; + ; r[tU].r[tL] = t64;\n:smaldrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4d unimpl\n\n\n# smalds rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H - ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;\n:smalds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x45 unimpl\n\n\n# smaltt rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H; + ; + ; r[tU].r[tL] = t64;\n:smaltt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x54 unimpl\n\n\n# smalxda rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.L + ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;\n:smalxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4e unimpl\n\n\n# smalxds rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.L - ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;\n:smalxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x55 unimpl\n\n\n# smaqa rt, ra, rb \t ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] ; + ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra and rb are signed numbers.\n:smaqa rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x64 unimpl\n\n\n# smaqa.su rt, ra, rb \t ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] + ; ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra are signed numbers. ; Elements of rb are unsigned numbers.\n:smaqa.su rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x65 unimpl\n\n\n# smar64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra*rb; // signed + ; + ; r[tU].r[tL] = t64;\n:smar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x42 unimpl\n\n\n# smax16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] > rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:smax16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x41 unimpl\n\n\n# smax8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] > rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:smax8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x45 unimpl\n\n\n# smbb16 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_].H[0]*rb.W[_x_].H[0]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:smbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x04 unimpl\n\n\n# smbt16 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_].H[0]*rb.W[_x_].H[1]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:smbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0c unimpl\n\n\n# smdrs rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_].H[0]*rb.W[_x_].H[0]) - (ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:smdrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x34 unimpl\n\n\n# smds rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_].H[1]*rb.W[_x_].H[1]) - (ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:smds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2c unimpl\n\n\n# smin16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] < rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:smin16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x40 unimpl\n\n\n# smin8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] < rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:smin8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x44 unimpl\n\n\n# smmul rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_])[63:32]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:smmul rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x20 unimpl\n\n\n:smmul.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x28 unimpl\n\n\n# smmwb rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_].H[0])[47:16]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:smmwb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x22 unimpl\n\n\n:smmwb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2a unimpl\n\n\n# smmwt rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_].H[1])[47:16]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:smmwt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x32 unimpl\n\n\n:smmwt.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3a unimpl\n\n\n# smslda rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra.H*rb.H - ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;\n:smslda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x56 unimpl\n\n\n# smslxda rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra.H*rb.L - ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;\n:smslxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5e unimpl\n\n\n# smsr64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra*rb; // signed + ; + ; r[tU].r[tL] = t64;\n:smsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x43 unimpl\n\n\n# smtt16 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_].H[1]*rb.W[_x_].H[1]; ; (RV32: __x__=0, RV64: __x__=1..0)\n:smtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x14 unimpl\n\n\n# smul16 rt, ra, rb \t ; RV32: ; r[tL] = ra.H[_0_] s* rb.H[_0_]; ; r[tH] = ra.H[_1_] s* rb.H[_1_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] s* rb.H[_0_]; ; rt.W[_1_] = ra.H[_1_] s* rb.H[_1_];\n:smul16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x50 unimpl\n\n\n:smul16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x60 unimpl\n\n\n# smul8 rt, ra, rb \t ; RV32: ; r[tL].H[_0_] = ra.B[_0_] s* rb.B[_0_]; ; r[tL].H[_1_] = ra.B[_1_] s* rb.B[_1_]; ; r[tH].H[_0_] = ra.B[_2_] s* rb.B[_2_]; ; r[tH].H[_1_] = ra.B[_3_] s* rb.B[_3_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] s* rb.B[_0_]; ; rt.H[_1_] = ra.B[_1_] s* rb.B[_1_]; ; rt.H[_2_] = ra.B[_2_] s* rb.B[_2_]; ; rt.H[_3_] = ra.B[_3_] s* rb.B[_3_];\n:smul8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x54 unimpl\n\n\n# smulx16 rt, ra, rb \t ; RV32: ; r[tL] = ra.H[_0_] s* rb.H[_1_]; ; r[tH] = ra.H[_1_] s* rb.H[_0_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] s* rb.H[_1_]; ; rt.W[_1_] = ra.H[_1_] s* rb.H[_0_];\n:smulx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x51 unimpl\n\n\n:smulx16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x61 unimpl\n\n\n# smulx8 rt, ra, rb \t ; RV32: ; r[tL].H[_0_] = ra.B[_0_] s* rb.B[_1_]; ; r[tL].H[_1_] = ra.B[_1_] s* rb.B[_0_]; ; r[tH].H[_0_] = ra.B[_2_] s* rb.B[_3_]; ; r[tH].H[_1_] = ra.B[_3_] s* rb.B[_2_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] s* rb.B[_1_]; ; rt.H[_1_] = ra.B[_1_] s* rb.B[_0_]; ; rt.H[_2_] = ra.B[_2_] s* rb.B[_3_]; ; rt.H[_3_] = ra.B[_3_] s* rb.B[_2_];\n:smulx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x55 unimpl\n\n\n# smxds rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_].H[1]*rb.W[_x_].H[0]) - (ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:smxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3c unimpl\n\n\n:sra.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x12 unimpl\n\n\n# sra16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] s>> rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:sra16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x28 unimpl\n\n\n:sra16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x30 unimpl\n\n\n# sra8 rt, ra, rb \t ; rt.B[_x_] = ra.B[_x_] s>> rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:sra8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2c unimpl\n\n\n:sra8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x34 unimpl\n\n\n:srai.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6a unimpl\n\n\n:srai16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x38 unimpl\n\n\n:srai16.u rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x38 unimpl\n\n\n:srai8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3c unimpl\n\n\n:srai8.u rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3c unimpl\n\n\n:sraiw.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1a unimpl\n\n\n# srl16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] u>> rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:srl16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x29 unimpl\n\n\n:srl16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x31 unimpl\n\n\n# srl8 rt, ra, rb \t ; rt.B[_x_] = ra.B[_x_] u>> rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:srl8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2d unimpl\n\n\n:srl8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x35 unimpl\n\n\n:srli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x39 unimpl\n\n\n:srli16.u rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x39 unimpl\n\n\n:srli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3d unimpl\n\n\n:srli8.u rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3d unimpl\n\n\n# sub16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] - rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:sub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x21 unimpl\n\n\n# sub64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = a64 - b64; + ; + ; r[tU].r[tL] = t64;\n:sub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x61 unimpl\n\n\n# sub8 rt, ra, rb \t ; rt.B[_x_] = ra.B[_x_] - rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:sub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x25 unimpl\n\n\n# sunpkd810 rt, ra \t ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,1), (0,0) ; RV64: (_x,y_) = (3,5),(2,4),(1,1), (0,0)\n:sunpkd810 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x08 unimpl\n\n\n# sunpkd820 rt, ra \t ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,2), (0,0) ; RV64: (_x,y_) = (3,6),(2,4),(1,2), (0,0)\n:sunpkd820 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x09 unimpl\n\n\n# sunpkd830 rt, ra \t ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,0) ; RV64: (_x,y_) = (3,7),(2,4),(1,3), (0,0)\n:sunpkd830 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0a unimpl\n\n\n# sunpkd831 rt, ra \t ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,1) ; RV64: (_x,y_) = (3,7),(2,5),(1,3), (0,1)\n:sunpkd831 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0b unimpl\n\n\n# sunpkd832 rt, ra \t ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,2) ; RV64: (_x,y_) = (3,7),(2,6),(1,3), (0,2)\n:sunpkd832 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x13 unimpl\n\n\n# swap16 rt, ra \t ; === ; <<< ; ==== 8-bit Misc Instructions ; There are 11 instructions here. ; .SIMD 8-bit Miscellaneous Instructions ; [cols=\"^.^1,<.^2,<.^2,<.^4\",options=\"header\",]\n:swap16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x19 unimpl\n\n\n# swap8 rt, ra \t ; === ; <<< ; ==== 8-bit Unpacking Instructions ; There are 8 instructions here. ; .8-bit Unpacking Instructions ; [cols=\"^.^1,<.^2,<.^2,<.^4\",options=\"header\",]\n:swap8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x18 unimpl\n\n\n# uclip32 rt, ra, imm5u \t ; m = imm5u; + ; rt = SAT.Um(ra.W[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0)\n:uclip32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7a unimpl\n\n\n# ucmple16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] u{le} rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:ucmple16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1e unimpl\n\n\n# ucmple8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] u{le} rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:ucmple8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1f unimpl\n\n\n# ucmplt16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] u< rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:ucmplt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x16 unimpl\n\n\n# ucmplt8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] u< rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:ucmplt8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x17 unimpl\n\n\n# ukadd16 rt, ra, rb \t ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:ukadd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x18 unimpl\n\n\n# ukadd64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.U64(a64 + b64); + ; + ; r[tU].r[tL] = t64;\n:ukadd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x58 unimpl\n\n\n# ukadd8 rt, ra, rb \t ; rt.B[_x_] = SAT.U8(ra.B[_x_] + rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:ukadd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1c unimpl\n\n\n:ukaddh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0a unimpl\n\n\n:ukaddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x08 unimpl\n\n\n# ukcras16 rt, ra, rb \t ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] – rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:ukcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1a unimpl\n\n\n# ukcrsa16 rt, ra, rb \t ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] + rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:ukcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1b unimpl\n\n\n# ukmar64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.U64(c64 + ra*rb); + ; + ; r[tU].r[tL] = t64;\n:ukmar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5a unimpl\n\n\n# ukmsr64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.U64(c64 - ra*rb); + ; + ; r[tU].r[tL] = t64;\n:ukmsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5b unimpl\n\n\n# uksub16 rt, ra, rb \t ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:uksub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x19 unimpl\n\n\n# uksub64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.U64(a64 - b64); + ; + ; r[tU].r[tL] = t64;\n:uksub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x59 unimpl\n\n\n# uksub8 rt, ra, rb \t ; rt.B[_x_] = SAT.U8(ra.B[_x_] - rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:uksub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1d unimpl\n\n\n:uksubh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0b unimpl\n\n\n:uksubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x09 unimpl\n\n\n# umaqa rt, ra, rb \t ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] ; + ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra and rb are unsigned numbers.\n:umaqa rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x66 unimpl\n\n\n# umar64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra*rb; // unsigned + ; + ; r[tU].r[tL] = t64;\n:umar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x52 unimpl\n\n\n# umax16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] u> rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:umax16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x49 unimpl\n\n\n# umax8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] u> rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:umax8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4d unimpl\n\n\n# umin16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] u< rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:umin16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x48 unimpl\n\n\n# umin8 rt, ra, rb \t ; rt.B[_x_] = (ra.B[_x_] u< rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:umin8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4c unimpl\n\n\n# umsr64 rt, ra, rb \t ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra*rb; // unsigned + ; + ; r[tU].r[tL] = t64;\n:umsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x53 unimpl\n\n\n# umul16 rt, ra, rb \t ; RV32: ; r[tL] = ra.H[_0_] u* rb.H[_0_]; ; r[tH] = ra.H[_1_] u* rb.H[_1_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] u* rb.H[_0_]; ; rt.W[_1_] = ra.H[_1_] u* rb.H[_1_];\n:umul16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x58 unimpl\n\n\n:umul16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x68 unimpl\n\n\n# umul8 rt, ra, rb \t ; RV32: ; r[tL].H[_0_] = ra.B[_0_] u* rb.B[_0_]; ; r[tL].H[_1_] = ra.B[_1_] u* rb.B[_1_]; ; r[tH].H[_0_] = ra.B[_2_] u* rb.B[_2_]; ; r[tH].H[_1_] = ra.B[_3_] u* rb.B[_3_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] u* rb.B[_0_]; ; rt.H[_1_] = ra.B[_1_] u* rb.B[_1_]; ; rt.H[_2_] = ra.B[_2_] u* rb.B[_2_]; ; rt.H[_3_] = ra.B[_3_] u* rb.B[_3_];\n:umul8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x5c unimpl\n\n\n# umulx16 rt, ra, rb \t ; RV32: ; r[tL] = ra.H[_0_] u* rb.H[_1_]; ; r[tH] = ra.H[_1_] u* rb.H[_0_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] u* rb.H[_1_]; ; rt.W[_1_] = ra.H[_1_] u* rb.H[_0_];\n:umulx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x59 unimpl\n\n\n:umulx16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x69 unimpl\n\n\n# umulx8 rt, ra, rb \t ; RV32: ; r[tL].H[_0_] = ra.B[_0_] u* rb.B[_1_]; ; r[tL].H[_1_] = ra.B[_1_] u* rb.B[_0_]; ; r[tH].H[_0_] = ra.B[_2_] u* rb.B[_3_]; ; r[tH].H[_1_] = ra.B[_3_] u* rb.B[_2_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] u* rb.B[_1_]; ; rt.H[_1_] = ra.B[_1_] u* rb.B[_0_]; ; rt.H[_2_] = ra.B[_2_] u* rb.B[_3_]; ; rt.H[_3_] = ra.B[_3_] u* rb.B[_2_];\n:umulx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x5d unimpl\n\n\n# uradd16 rt, ra, rb \t ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:uradd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x10 unimpl\n\n\n# uradd64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (CONCAT(1'b0,a64) + CONCAT(1'b0,b64)) >>1; + ; + ; r[tU].r[tL] = t64;\n:uradd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x50 unimpl\n\n\n# uradd8 rt, ra, rb \t ; rt.B[_x_] = (CONCAT(1'b0,ra.B[_x_]) + CONCAT(1'b0,rb.B[_x_])) >> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:uradd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x14 unimpl\n\n\n# uraddw rt, ra, rb \t ; res = (CONCAT(1'b0,ra.W[0]) + CONCAT(1'b0,rb.W[0])) >> 1; ; rt = SE(res);\n:uraddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x18 unimpl\n\n\n# urcras16 rt, ra, rb \t ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x-1_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) – CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:urcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x12 unimpl\n\n\n# urcrsa16 rt, ra, rb \t ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x-1_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:urcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x13 unimpl\n\n\n# ursub16 rt, ra, rb \t ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)\n:ursub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x11 unimpl\n\n\n# ursub64 rt, ra, rb \t ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (CONCAT(1'b0,a64) - CONCAT(1'b0,b64)) >>1; + ; + ; r[tU].r[tL] = t64;\n:ursub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x51 unimpl\n\n\n# ursub8 rt, ra, rb \t ; rt.B[_x_] = (CONCAT(1'b0,ra.B[_x_]) - CONCAT(1'b0,rb.B[_x_])) >> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)\n:ursub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x15 unimpl\n\n\n# ursubw rt, ra, rb \t ; res = (CONCAT(1'b0,ra.W[0]) - CONCAT(1'b0,rb.W[0])) >> 1; ; rt = SE(res);\n:ursubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x19 unimpl\n\n\n# wext rt, ra, rb \t ; a64 = r[aU].r[aL]; // RV32 ; a64 = ra; // RV64 ; lsb = rb[4:0]; ; exword = a64[(31+lsb):lsb]; ; rt = SE(exword);\n:wext rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x67 unimpl\n\n\n# wexti rt, ra, imm5u \t ; a64 = r[aU].r[aL]; // RV32 ; a64 = ra; // RV64 ; lsb = imm5u; ; exword = a64[(31+lsb):lsb]; ; rt = SE(exword);\n:wexti rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x6f unimpl\n\n\n# zunpkd810 rt, ra \t ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,1), (0,0) ; RV64: (_x,y_) = (3,5),(2,4),(1,1), (0,0)\n:zunpkd810 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0c unimpl\n\n\n# zunpkd820 rt, ra \t ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,2), (0,0) ; RV64: (_x,y_) = (3,6),(2,4),(1,2), (0,0)\n:zunpkd820 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0d unimpl\n\n\n# zunpkd830 rt, ra \t ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,0) ; RV64: (_x,y_) = (3,7),(2,4),(1,3), (0,0)\n:zunpkd830 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0e unimpl\n\n\n# zunpkd831 rt, ra \t ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,1) ; RV64: (_x,y_) = (3,7),(2,5),(1,3), (0,1)\n:zunpkd831 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0f unimpl\n\n\n# zunpkd832 rt, ra \t ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,2) ; RV64: (_x,y_) = (3,7),(2,6),(1,3), (0,2)\n:zunpkd832 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x17 unimpl\n\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv32q.sinc", "content": "# RV32Q Standard Extension\n\n# fadd.q D,S,T,m 06000053 fe00007f SIMPLE (0, 0) \n:fadd.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3\n{\n\tfrd = frs1 f+ frs2;\n}\n\n# fclass.q d,S e6001053 fff0707f SIMPLE (0, 0) \n:fclass.q rd,frs1 is frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x73 & op2024=0x0\n{\n\t#TODO\n\t# rd = 0;\n\t# rd[0, 1] = 0; #TODO - inf\n\t# rd[1, 1] = 0; #TODO - norm num\n\t# rd[2, 1] = 0; #TODO - subnorm num\n\t# rd[3, 1] = 0; #TODO - 0\n\t# rd[4, 1] = 0; #TODO + 0\n\t# rd[5, 1] = 0; #TODO + norm num\n\t# rd[6, 1] = 0; #TODO + subnorm num\n\t# rd[7, 1] = 0; #TODO + inf\n\t# rd[8, 1] = 0; #TODO snan\n\t# rd[9, 1] = 0; #TODO qnan\n}\n\n\n\n# fcvt.d.q D,S,m 42300053 fff0007f SIMPLE (0, 0) \n:fcvt.d.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3\n{\n\t#TODO double to quad\n}\n\n# fcvt.q.d D,S 46100053 fff0707f SIMPLE (0, 0) \n:fcvt.q.d frd,frs1 is frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x1\n{\n\tfrd = float2float(frs1);\n}\n\n# fcvt.q.s D,S 46000053 fff0707f SIMPLE (0, 0) \n:fcvt.q.s frd,frs1 is frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x0\n{\n\tfrd = float2float(frs1);\n}\n\n# fcvt.q.w D,s d6000053 fff0707f SIMPLE (0, 0) \n:fcvt.q.w frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x0\n{\n\tfrd = int2float(rs1);\n}\n\n# fcvt.q.wu D,s d6100053 fff0707f SIMPLE (0, 0) \n:fcvt.q.wu frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x1\n{\n\tfrd = int2float(rs1);\n}\n\n# fcvt.s.q D,S,m 40300053 fff0007f SIMPLE (0, 0) \n:fcvt.s.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3\n{\n\tfrd = float2float(frs1);\n}\n\n# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0) \n:fcvt.w.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0\n{\n\trd = trunc(frs1);\n}\n\n# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0) \n:fcvt.wu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1\n{\n\trd = trunc(frs1);\n}\n\n\n# fdiv.q D,S,T,m 1e000053 fe00007f SIMPLE (0, 0) \n:fdiv.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf\n{\n\tlocal tfrs1:$(QFLEN) = frs1;\n\tlocal tfrs2:$(QFLEN) = frs2;\n\tlocal result:$(QFLEN) = tfrs1 f/ tfrs2;\n\tfrd = result;\n}\n\n\n# feq.q d,S,T a6002053 fe00707f SIMPLE (0, 0) \n:feq.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x53\n{\n\trd = zext(frs1 f== frs2);\n}\n\n\n# fle.q d,S,T a6000053 fe00707f SIMPLE (0, 0) \n:fle.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53\n{\n\trd = zext(frs1 f<= frs2);\n}\n\n# flq D,o(s) 00004007 0000707f OWORD|DREF (0, 16) \n:flq frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x4\n{\n\tlocal ea:$(XLEN) = immI + rs1;\n\tfrd = *[ram]:16 ea;\n}\n\n\n# flt.q d,S,T a6001053 fe00707f SIMPLE (0, 0) \n:flt.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53\n{\n\trd = zext(frs1 f< frs2);\n}\n\n\n\n# fmadd.q D,S,T,R,m 06000043 0600007f SIMPLE (0, 0) \n:fmadd.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3\n{\n\tfrd = (frs1 f* frs2) f+ frs3;\n}\n\n# fmax.q D,S,T 2e001053 fe00707f SIMPLE (0, 0) \n:fmax.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x17\n{\n\tlocal tmpfrs1 = frs1;\n\tlocal tmpfrs2 = frs2;\n\tfrd = tmpfrs1;\n\tif (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;\n\tif (nan(tmpfrs2)) goto inst_next;\n\tfrd = tmpfrs2;\n\tif (nan(tmpfrs1)) goto inst_next;\n\tif (tmpfrs2 f> tmpfrs1) goto inst_next;\n\tfrd = tmpfrs1;\n}\n\n# fmin.q D,S,T 2e000053 fe00707f SIMPLE (0, 0) \n:fmin.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x17\n{\n\tlocal tmpfrs1 = frs1;\n\tlocal tmpfrs2 = frs2;\n\tfrd = tmpfrs1;\n\tif (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next;\n\tif (nan(tmpfrs2)) goto inst_next;\n\tfrd = tmpfrs2;\n\tif (nan(tmpfrs1)) goto inst_next;\n\tif (tmpfrs2 f<= tmpfrs1) goto inst_next;\n\tfrd = tmpfrs1;\n}\n\n# fmsub.q D,S,T,R,m 06000047 0600007f SIMPLE (0, 0) \n:fmsub.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3\n{\n\tfrd = (frs1 f* frs2) f- frs3;\n}\n\n# fmul.q D,S,T,m 16000053 fe00007f SIMPLE (0, 0) \n:fmul.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb\n{\n\tfrd = frs1 f* frs2;\n}\n\n\n# fmv.q.x D,s f6000053 fff0707f SIMPLE (64, 0) \n:fmv.q.x frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x7b & op2024=0x0\n{\n\tfrd = int2float(rs1);\n}\n\n\n# fmv.x.q d,S e6000053 fff0707f SIMPLE (64, 0) \n:fmv.x.q rd,frs1 is frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x73 & op2024=0x0\n{\n\tlocal tmpreg:4 = &frs1;\n\tlocal tmp:4 = *[register]:4 tmpreg;\n\tassignW(rd, tmp);\n}\n\n\n# fnmadd.q D,S,T,R,m 0600004f 0600007f SIMPLE (0, 0) \n:fnmadd.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3\n{\n\tfrd = (f- (frs1 f* frs2)) f- frs3;\n}\n\n# fnmsub.q D,S,T,R,m 0600004b 0600007f SIMPLE (0, 0) \n:fnmsub.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3\n{\n\tfrd = (f- (frs1 f* frs2)) f+ frs3;\n}\n\n\n# fsgnj.q D,S,T 26000053 fe00707f SIMPLE (0, 0) \n:fsgnj.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13\n{\tlocal tmp = frs1;\n\ttmp[127,1] = frs2[127,1];\n\tfrd = tmp;\n}\n\n\n# fsgnjn.q D,S,T 26001053 fe00707f SIMPLE (0, 0) \n:fsgnjn.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13\n{\n\tlocal tmp = frs1;\n\ttmp[127,1] = !frs2[127,1];\n\tfrd = tmp;\n}\n\n\n# fsgnjx.q D,S,T 26002053 fe00707f SIMPLE (0, 0) \n:fsgnjx.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13\n{\n\tlocal tmp = frs1;\n\ttmp[127,1] = tmp[127,1] ^ frs2[127,1];\n\tfrd = tmp;\n}\n\n\n:fsq frs2,immS(rs1) is frs2 & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x4\n{\n\tlocal ea:$(XLEN) = immS + rs1;\n\t*[ram]:$(QFLEN) ea = frs2;\t\n}\n\n\n# fsqrt.q D,S,m 5e000053 fff0007f SIMPLE (0, 0) \n:fsqrt.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0\n{\n\tfrd = sqrt(frs1);\n}\n\n\n# fsub.q D,S,T,m 0e000053 fe00007f SIMPLE (0, 0) \n:fsub.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7\n{\n\tfrd = frs1 f- frs2;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64a.sinc", "content": "# RV64A Standard Extension (in addition to RV32A)\n\n# amoadd.d d,t,0(s) 0000302f fe00707f QWORD|DREF (64, 8) \n:amoadd.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x0 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\ttmp = tmp + tmprs2;\n\t*[ram]:8 tmprs1 = tmp;\n}\n\n\n# amoand.d d,t,0(s) 6000302f fe00707f QWORD|DREF (64, 8) \n:amoand.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0xc & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\ttmp = tmp & tmprs2;\n\t*[ram]:8 tmprs1 = tmp;\n}\n\n\n# amomax.d d,t,0(s) a000302f fe00707f QWORD|DREF (64, 8) \n:amomax.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x14 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\tif (tmprs2 s<= tmp) goto inst_next;\n\t*[ram]:8 tmprs1 = tmprs2;\n}\n\n\n# amomaxu.d d,t,0(s) e000302f fe00707f QWORD|DREF (64, 8) \n:amomaxu.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1c & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\tif (tmprs2 <= tmp) goto inst_next;\n\t*[ram]:8 tmprs1 = tmprs2;\n}\n\n\n# amomin.d d,t,0(s) 8000302f fe00707f QWORD|DREF (64, 8) \n:amomin.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x10 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\tif (tmprs2 s>= tmp) goto inst_next;\n\t*[ram]:8 tmprs1 = tmprs2;\n}\n\n\n# amominu.d d,t,0(s) c000302f fe00707f QWORD|DREF (64, 8) \n:amominu.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x18 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\tif (tmprs2 >= tmp) goto inst_next;\n\t*[ram]:8 tmprs1 = tmprs2;\n}\n\n\n# amoor.d d,t,0(s) 4000302f fe00707f QWORD|DREF (64, 8) \n:amoor.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x8 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\ttmp = tmp | tmprs2;\n\t*[ram]:8 tmprs1 = tmp;\n}\n\n\n# amoswap.d d,t,0(s) 0800302f fe00707f QWORD|DREF (64, 8) \n:amoswap.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\t*[ram]:8 tmprs1 = tmprs2;\n}\n\n\n# amoxor.d d,t,0(s) 2000302f fe00707f QWORD|DREF (64, 8) \n:amoxor.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x4 & aqrl\n{\n\tlocal tmprs1 = rs1;\n\tlocal tmprs2 = rs2L;\n\tlocal tmp:8 = *[ram]:8 tmprs1;\n\trdL = tmp;\n\ttmp = tmp ^ tmprs2;\n\t*[ram]:8 tmprs1 = tmp;\n}\n\n\n# lr.d d,0(s) 1000302f fff0707f QWORD|DREF (64, 8) \n:lr.d^aqrl rdL,(rs1) is rs1 & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x2 & op2024=0x0 & aqrl\n{\n\tRESERVE_ADDRESS = rs1;\n\tRESERVE = 1;\n\tRESERVE_LENGTH = 8;\n\trdL = *[ram]:8 rs1;\n}\n\n\n# sc.d d,t,0(s) 1800302f fe00707f QWORD|DREF (64, 8) \n:sc.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x3 & aqrl\n{\n\tlocal tmprs2 = rs2L;\n\tlocal tmprs1 = rs1;\n\trdL = 1;\n\tif ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 8)) goto inst_next;\n\t*[ram]:8 tmprs1 = tmprs2;\n\trdL = 0;\n\tRESERVE_ADDRESS = 0;\n\tRESERVE = 0;\n\tRESERVE_LENGTH = 0;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64b.sinc", "content": "# RV64 Bitmanip Extension\n\n#TODO fix op2031\n:addiwu rd, rs1, op2031 is op0006=0x1b & op1214=0x4 & rd & op2031 & rs1 unimpl\n\n:addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:addwu rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:bdepw rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:bextw rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:bfpw rd, rs1, rs2 is op0006=0x3b & op1214=0x7 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:bmatflip rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x3 & op2531=0x30 & rd & rs1 unimpl\n\n:bmator rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:bmatxor rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:clmulhw rd, rs1, rs2 is op0006=0x3b & op1214=0x3 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:clmulrw rd, rs1, rs2 is op0006=0x3b & op1214=0x2 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:clmulw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x5 & rd & rs1 & rs2 unimpl\n\n:clzw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x0 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32.d rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x13 & op2531=0x30 & rd & rs1 unimpl\n\n:crc32c.d rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1b & op2531=0x30 & rd & rs1 unimpl\n\n:ctzw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x1 & op2531=0x30 & rd & rs1 unimpl\n\n:fslw rd, rs1, rs3, rs2 is op0006=0x3b & op1214=0x1 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl\n\n#TODO fix op2024\n:fsriw rd, rs1, rs3, op2024 is op0006=0x1b & op1214=0x5 & op2526=0x2 & op2024 & rd & rs1 & rs3 unimpl\n\n:fsrw rd, rs1, rs3, rs2 is op0006=0x3b & op1214=0x5 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl\n\n#TODO fix op2024\n:gorciw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x14 & op2024 & rd & rs1 unimpl\n\n:gorcw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x14 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2024\n:greviw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x34 & op2024 & rd & rs1 unimpl\n\n:grevw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x34 & rd & rs1 & rs2 unimpl\n\n:packuw rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:packw rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n:pcntw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x2 & op2531=0x30 & rd & rs1 unimpl\n\n:rolw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x30 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2024\n:roriw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x30 & op2024 & rd & rs1 unimpl\n\n:rorw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x30 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2024\n:sbclriw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x24 & op2024 & rd & rs1 unimpl\n\n:sbclrw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:sbextw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2024\n:sbinviw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x34 & op2024 & rd & rs1 unimpl\n\n:sbinvw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x34 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2024\n:sbsetiw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x14 & op2024 & rd & rs1 unimpl\n\n:sbsetw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x14 & rd & rs1 & rs2 unimpl\n\n:sh1addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x2 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:sh2addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:sh3addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:shflw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2026\n:slliu.w rd, rs1, op2026 is op0006=0x1b & op1214=0x1 & op2731=0x1 & op2026 & rd & rs1 unimpl\n\n#TODO fix op2024\n:sloiw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x10 & op2024 & rd & rs1 unimpl\n\n:slow rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n#TODO fix op2024\n:sroiw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x10 & op2024 & rd & rs1 unimpl\n\n:srow rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x10 & rd & rs1 & rs2 unimpl\n\n:subu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x24 & rd & rs1 & rs2 unimpl\n\n:subwu rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x25 & rd & rs1 & rs2 unimpl\n\n:unshflw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x4 & rd & rs1 & rs2 unimpl\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64d.sinc", "content": "# RV64D Standard Extension (in addition to RV32D)\n\n# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0) \n:fcvt.d.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2\n{\n\tlocal tmp:8 = int2float(rs1L);\n\tfrd = tmp;\n}\n\n\n# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0) \n:fcvt.d.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3\n{\n\t#ATTN unsigned can be an issue here\n\tlocal u64:$(XLEN2) = zext(rs1L);\n\tlocal tmp:8 = int2float(u64);\n\tfrd = tmp;\n}\n\n\n# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0) \n:fcvt.l.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2\n{\n\trdL = trunc(frs1D);\n}\n\n\n# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0) \n:fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3\n{\n\t#TODO unsigned\n\trdL = trunc(frs1D);\n}\n\n\n# fmv.d.x D,s f2000053 fff0707f SIMPLE (64, 0) \n:fmv.d.x frd,rs1L is frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0\n{\n\tfrd = rs1L;\n}\n\n:fmv.x.d rdL,frs1D is frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0\n{\n\tlocal tmpreg:4 = &frs1D;\n\tlocal tmp:8 = *[register]:8 tmpreg;\n\trdL = tmp;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64f.sinc", "content": "# RV64F Standard Extension (in addition to RV32F)\n\n# fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0) \n:fcvt.l.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2\n{\n\trdL = trunc(frs1S);\n}\n\n\n# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0) \n:fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3\n{\n\t#TODO unsigned\n\trdL = trunc(frs1S);\n}\n\n\n# fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0) \n:fcvt.s.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2\n{\n\tlocal tmp:4 = int2float(rs1L);\n\tfassignS(frd, tmp);\n}\n\n\n# fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0) \n:fcvt.s.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3\n{\n\t#ATTN unsigned can be an issue here\n\tlocal u64:$(XLEN2) = zext(rs1L);\n\tlocal tmp:4 = int2float(u64);\n\tfassignS(frd, tmp);\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64i.sinc", "content": "# RV64I Base Instruction Set (in addition to RV32I)\n\n# addiw d,s,j 0000001b 0000707f SIMPLE (64, 0) \n:addiw rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0\n{\n\tlocal result = rs1 + immI;\n\trd = sext(result:4);\n}\n\n:sext.w rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0\n{\n\tlocal result = rs1;\n\trd = sext(result:4);\n}\n\n\n\n# addw d,s,t 0000003b fe00707f SIMPLE (64, 0) \n:addw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x0\n{\n\tlocal tmpr1:4 = rs1:4;\n\tlocal tmpr2:4 = rs2:4;\n\tlocal result:4 = tmpr1 + tmpr2;\n\trd = sext(result);\n}\n\n\n# ld d,o(s) 00003003 0000707f QWORD|DREF (64, 8) \n:ld rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x3\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\trd = *[ram]:8 ea;\n}\n\n\n# lwu d,o(s) 00006003 0000707f DWORD|DREF (64, 4) \n:lwu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x6\n{\n\tlocal ea:$(XLEN) = rs1 + immI;\n\trd = zext(*[ram]:4 ea);\n}\n\n\n# sd t,q(s) 00003023 0000707f QWORD|DREF (64, 8) \n:sd rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x3\n{\n\tlocal ea:$(XLEN) = rs1 + immS;\n\t*[ram]:8 ea = rs2;\n}\n\n\n# slliw d,s,< 0000101b fe00707f SIMPLE (64, 0) \n:slliw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0\n{\n\tlocal tmp:4 = rs1:4;\n\ttmp = tmp << shamt5;\n\trd = sext(tmp);\n}\n\n\n# sllw d,s,t 0000103b fe00707f SIMPLE (64, 0) \n:sllw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x1 & funct7=0x0\n{\n\tlocal shift:$(XLEN) = rs2 & 0x1f;\n\tlocal tmp:4 = rs1:4;\n\ttmp = tmp << shift;\n\trd = sext(tmp);\n}\n\n\n# sraiw d,s,< 4000501b fe00707f SIMPLE (64, 0) \n:sraiw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20\n{\n\tlocal tmp:4 = rs1:4;\n\ttmp = tmp s>> shamt5;\n\trd = sext(tmp);\n}\n\n\n# sraw d,s,t 4000503b fe00707f SIMPLE (64, 0) \n:sraw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x20\n{\n\tlocal shift:$(XLEN) = rs2 & 0x1f;\n\tlocal tmp:4 = rs1:4;\n\ttmp = tmp s>> shift;\n\trd = sext(tmp);\n}\n\n\n# srliw d,s,< 0000501b fe00707f SIMPLE (64, 0) \n:srliw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0\n{\n\tlocal tmp:4 = rs1:4;\n\ttmp = tmp >> shamt5;\n\trd = sext(tmp);\n}\n\n\n# srlw d,s,t 0000503b fe00707f SIMPLE (64, 0) \n:srlw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x0\n{\n\tlocal shift:$(XLEN) = rs2 & 0x1f;\n\tlocal tmp:4 = rs1:4;\n\ttmp = tmp >> shift;\n\trd = sext(tmp);\n}\n\n\n# subw d,s,t 4000003b fe00707f SIMPLE (64, 0) \n:subw rd,rs1W,rs2W is rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20\n{\n\tlocal result = rs1W - rs2W;\n\trd = sext(result);\n}\n\n# negw d,t 4000003b fe0ff07f ALIAS (64, 0)\n:negw rd,rs2W is rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0\n{\n\tlocal tmp = -rs2W;\n\trd = sext(tmp);\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64k.sinc", "content": "# RV64 Crypto Extension\n# NOTE 0.6.2\n\n# 0001010 rs2 rs1 010 rd 0101011 saes64.decs\n:saes64.decs rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x0a unimpl\n\n# 0001001 rs2 rs1 010 rd 0101011 saes64.decsm\n:saes64.decsm rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x09 unimpl\n\n# 0001000 rs2 rs1 010 rd 0101011 saes64.encs\n:saes64.encs rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x08 unimpl\n\n# 0000111 rs2 rs1 010 rd 0101011 saes64.encsm\n:saes64.encsm rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x07 unimpl\n\n# 0000110 00001 rs1 010 rd 0101011 saes64.imix\n:saes64.imix rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x2 & op2024=0x01 & op2531=0x06 unimpl\n\n# 0000100 0 rcon rs1 010 rd 0101011 saes64.ks1\n:saes64.ks1 rd, rs1, rcon is rd & rs1 & rcon & op0006=0x5b & op1214=0x2 & op2424=0x0 & op2531=0x04 unimpl\n\n# 0000101 rs2 rs1 010 rd 0101011 saes64.ks2\n:saes64.ks2 rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x05 unimpl\n\n# 0000111 00100 rs1 111 rd 0101011 ssha512.sig0\n:ssha512.sig0 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x04 & op2531=0x07 unimpl\n\n# 0000111 00101 rs1 111 rd 0101011 ssha512.sig1\n:ssha512.sig1 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x05 & op2531=0x07 unimpl\n\n# 0000111 00110 rs1 111 rd 0101011 ssha512.sum0\n:ssha512.sum0 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x06 & op2531=0x07 unimpl\n\n# 0000111 00111 rs1 111 rd 0101011 ssha512.sum1\n:ssha512.sum1 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x07 & op2531=0x07 unimpl\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64m.sinc", "content": "# RV64M Standard Exention (in addition to RV32M)\n\n# divuw d,s,t 0200503b fe00707f SIMPLE (64, 0) \n:divuw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x1\n{\n\tlocal tmpr1:4 = rs1:4;\n\tlocal tmpr2:4 = rs2:4;\n\trd = sext(tmpr1 / tmpr2);\n}\n\n\n# divw d,s,t 0200403b fe00707f SIMPLE (64, 0) \n:divw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x4 & funct7=0x1\n{\n\tlocal tmpr1:4 = rs1:4;\n\tlocal tmpr2:4 = rs2:4;\n\trd = sext(tmpr1 s/ tmpr2);\n}\n\n\n# mulw d,s,t 0200003b fe00707f SIMPLE (64, 0) \n:mulw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x1\n{\n\tlocal tmp:4 = rs1:4 * rs2:4;\n\trd = sext(tmp);\n}\n\n\n# remuw d,s,t 0200703b fe00707f SIMPLE (64, 0) \n:remuw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x7 & funct7=0x1\n{\n\tlocal tmpr1:4 = rs1:4;\n\tlocal tmpr2:4 = rs2:4;\n\trd = sext(tmpr1 % tmpr2);\n}\n\n\n# remw d,s,t 0200603b fe00707f SIMPLE (64, 0) \n:remw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x6 & funct7=0x1\n{\n\tlocal tmpr1:4 = rs1:4;\n\tlocal tmpr2:4 = rs2:4;\n\trd = sext(tmpr1 s% tmpr2);\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64p.sinc", "content": "# RV64 P Extension\n\n\n# add32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] + rb.W[_x_]; ; (RV64: __x__=1..0)\n:add32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x20 unimpl\n\n\n# cras32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] + rb.W[_x-1_]; + ; rt.W[_x-1_] = ra.W[_x-1_] – rb.W[_x_]; ; (RV64: __x__=1)\n:cras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x22 unimpl\n\n\n# crsa32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] - rb.W[_x-1_]; + ; rt.W[_x-1_] = ra.W[_x-1_] + rb.W[_x_]; ; (RV64: __x__=1)\n:crsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x23 unimpl\n\n\n# kadd32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x_]); ; (RV64: __x__=1..0)\n:kadd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x08 unimpl\n\n\n# kcras32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] – rb.W[_x_]); ; (RV64: __x__=1)\n:kcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0a unimpl\n\n\n# kcrsa32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] + rb.W[_x_]); ; (RV64: __x__=1)\n:kcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0b unimpl\n\n\n:kmabb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2d unimpl\n\n\n:kmabt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x35 unimpl\n\n\n:kmadrs32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x36 unimpl\n\n\n:kmads32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2e unimpl\n\n\n:kmatt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3d unimpl\n\n\n:kmaxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x25 unimpl\n\n\n:kmaxds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3e unimpl\n\n\n:kmda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1c unimpl\n\n\n:kmsda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x26 unimpl\n\n\n:kmsxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x27 unimpl\n\n\n:kmxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1d unimpl\n\n\n# ksll32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << rb[4:0]); ; (RV64: __x__=1..0)\n:ksll32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x32 unimpl\n\n\n# kslli32 rt, ra, im5u \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << im5u); ; (RV64: __x__=1..0)\n:kslli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x42 unimpl\n\n\n# kslra32 rt, ra, rb \t ; if (rb[5:0] < 0) + ; rt.W[_x_] = ra.W[_x_] s>> -rb[5:0]; ; if (rb[5:0] > 0) + ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << rb[5:0]); ; (RV64: __x__=1..0)\n:kslra32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2b unimpl\n\n\n:kslra32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x33 unimpl\n\n\n# kstas16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] – rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:kstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x62 unimpl\n\n\n# kstas32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] – rb.W[_x-1_]); ; (RV64: __x__=1)\n:kstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x60 unimpl\n\n\n# kstsa16 rt, ra, rb \t ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] + rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:kstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x63 unimpl\n\n\n# kstsa32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] + rb.W[_x-1_]); ; (RV64: __x__=1)\n:kstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x61 unimpl\n\n\n# ksub32 rt, ra, rb \t ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x_]); ; (RV64: __x__=1..0)\n:ksub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x09 unimpl\n\n\n# pkbb32 rt, ra, rb \t ; rt = CONCAT(ra.W[_0_], rb.W[_0_]);\n:pkbb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x07 unimpl\n\n\n# pkbt32 rt, ra, rb \t ; rt = CONCAT(ra.W[_0_], rb.W[_1_]);\n:pkbt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0f unimpl\n\n\n# pktb32 rt, ra, rb \t ; rt = CONCAT(ra.W[_1_], rb.W[_0_]);\n:pktb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1f unimpl\n\n\n# pktt32 rt, ra, rb \t ; rt = CONCAT(ra.W[_1_], rb.W[_1_]);\n:pktt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x17 unimpl\n\n\n# radd32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x_]) s>> 1; ; (RV64: __x__=1..0)\n:radd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x00 unimpl\n\n\n# rcras32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x-1_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] – rb.W[_x_]) s>> 1; ; (RV64: __x__=1)\n:rcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x02 unimpl\n\n\n# rcrsa32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x-1_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] + rb.W[_x_]) s>> 1; ; (RV64: __x__=1)\n:rcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x03 unimpl\n\n\n# rstas16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] – rb.H[_x-1_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:rstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x5a unimpl\n\n\n# rstas32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] – rb.W[_x-1_]) s>> 1; ; (RV64: __x__=1)\n:rstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x58 unimpl\n\n\n# rstsa16 rt, ra, rb \t ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] + rb.H[_x-1_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:rstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x5b unimpl\n\n\n# rstsa32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] + rb.W[_x-1_]) s>> 1; ; (RV64: __x__=1)\n:rstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x59 unimpl\n\n\n# rsub32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x_]) s>> 1; ; (RV64: __x__=1..0)\n:rsub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x01 unimpl\n\n\n# sll32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] << rb[4:0]; ; (RV64: __x__=1..0)\n:sll32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2a unimpl\n\n\n# slli32 rt, ra, im5u \t ; rt.W[_x_] = ra.W[_x_] << im5u; ; (RV64: __x__=1..0)\n:slli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3a unimpl\n\n\n# smax32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] > rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)\n:smax32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x49 unimpl\n\n\n:smbt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0c unimpl\n\n\n:smdrs32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x34 unimpl\n\n\n:smds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2c unimpl\n\n\n# smin32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] < rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)\n:smin32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x48 unimpl\n\n\n:smtt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x14 unimpl\n\n\n:smxds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3c unimpl\n\n\n# sra32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] s>> rb[4:0]; ; (RV64: __x__=1..0)\n:sra32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x28 unimpl\n\n\n:sra32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x30 unimpl\n\n\n# srai32 rt, ra, im5u \t ; rt.W[_x_] = ra.W[_x_] s>> im5u; ; (RV64: __x__=1..0)\n:srai32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x38 unimpl\n\n\n:srai32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x40 unimpl\n\n\n# srl32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] u>> rb[4:0]; ; (RV64: __x__=1..0)\n:srl32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x29 unimpl\n\n\n:srl32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x31 unimpl\n\n\n# srli32 rt, ra, im5u \t ; rt.W[_x_] = ra.W[_x_] u>> im5u; ; (RV64: __x__=1..0)\n:srli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x39 unimpl\n\n\n:srli32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x41 unimpl\n\n\n# stas16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] + rb.H[_x_]; + ; rt.H[_x-1_] = ra.H[_x-1_] – rb.H[_x-1_]; ; (RV32: __x__=1, RV64: __x__=1,3)\n:stas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x7a unimpl\n\n\n# stas32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] + rb.W[_x_]; + ; rt.W[_x-1_] = ra.W[_x-1_] – rb.W[_x-1_]; ; (RV64: __x__=1)\n:stas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x78 unimpl\n\n\n# stsa16 rt, ra, rb \t ; rt.H[_x_] = ra.H[_x_] - rb.H[_x_]; + ; rt.H[_x-1_] = ra.H[_x-1_] + rb.H[_x-1_]; ; (RV32: __x__=1, RV64: __x__=1,3)\n:stsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x7b unimpl\n\n\n# stsa32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] - rb.W[_x_]; + ; rt.W[_x-1_] = ra.W[_x-1_] + rb.W[_x-1_]; ; (RV64: __x__=1)\n:stsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x79 unimpl\n\n\n# sub32 rt, ra, rb \t ; rt.W[_x_] = ra.W[_x_] - rb.W[_x_]; ; (RV64: __x__=1..0)\n:sub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x21 unimpl\n\n\n# ukadd32 rt, ra, rb \t ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x_]; ; (RV64: __x__=1..0)\n:ukadd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x18 unimpl\n\n\n# ukcras32 rt, ra, rb \t ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] – rb.W[_x_]); ; (RV64: __x__=1)\n:ukcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1a unimpl\n\n\n# ukcrsa32 rt, ra, rb \t ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] + rb.W[_x_]); ; (RV64: __x__=1)\n:ukcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1b unimpl\n\n\n# ukstas16 rt, ra, rb \t ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] – rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:ukstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x72 unimpl\n\n\n# ukstas32 rt, ra, rb \t ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] – rb.W[_x-1_]); ; (RV64: __x__=1)\n:ukstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x70 unimpl\n\n\n# ukstsa16 rt, ra, rb \t ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] + rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)\n:ukstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x73 unimpl\n\n\n# ukstsa32 rt, ra, rb \t ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] + rb.W[_x-1_]); ; (RV64: __x__=1)\n:ukstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x71 unimpl\n\n\n# uksub32 rt, ra, rb \t ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x_]); ; (RV64: __x__=1..0)\n:uksub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x19 unimpl\n\n\n# umax32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] u> rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)\n:umax32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x51 unimpl\n\n\n# umin32 rt, ra, rb \t ; rt.W[_x_] = (ra.W[_x_] u< rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)\n:umin32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x50 unimpl\n\n\n# uradd32 rt, ra, rb \t ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1..0)\n:uradd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x10 unimpl\n\n\n# urcras32 rt, ra, rb \t ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x-1_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) – CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1)\n:urcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x12 unimpl\n\n\n# urcrsa32 rt, ra, rb \t ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x-1_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1)\n:urcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x13 unimpl\n\n\n# urstas16 rt, ra, rb \t ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) – CONCAT(1'b0,rb.H[_x-1_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:urstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x6a unimpl\n\n\n# urstas32 rt, ra, rb \t ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) – CONCAT(1'b0,rb.W[_x-1_])) >> 1; ; (RV64: __x__=1)\n:urstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x68 unimpl\n\n\n# urstsa16 rt, ra, rb \t ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) + CONCAT(1'b0,rb.H[_x-1_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)\n:urstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x6b unimpl\n\n\n# urstsa32 rt, ra, rb \t ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) + CONCAT(1'b0,rb.W[_x-1_])) >> 1; ; (RV64: __x__=1)\n:urstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x69 unimpl\n\n\n# ursub32 rt, ra, rb \t ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1..0)\n:ursub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x11 unimpl\n\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rv64q.sinc", "content": "# RV64Q Standard Extension (in addition to RV32Q)\n\n# fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0) \n:fcvt.l.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2\n{\n\trd = trunc(frs1);\n}\n\n\n# fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0) \n:fcvt.lu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3\n{\n\trd = trunc(frs1);\n}\n\n\n# fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0) \n:fcvt.q.l frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2\n{\n\tfrd = int2float(rs1);\n}\n\n\n# fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0) \n:fcvt.q.lu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3\n{\n\tfrd = int2float(rs1);\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rvc.sinc", "content": "# RVC Standard Extension for Compressed Instructions\n\n# c.add d,CV 00009002 0000f003 SIMPLE (0, 0) \n:c.add crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1\n{\n\tcrd = crd + crs2;\n}\n\n# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0)\n# There may be other nop forms here if (cop0711=0) or (cop1212=0 & cop0206=0)\n:c.addi crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x0\n{\n\tcrd = crd + cimmI;\n}\n\n:c.nop is cop0001=0x1 & cop1315=0x0 & cop0711=0 & cop1212=0 & cop0206=0\n{\n\tlocal NOP:1 = 0;\n\tNOP = NOP;\n}\n\n# c.addi16sp Cc,CL 00006101 0000ef83 SIMPLE (0, 0) \n:c.addi16sp sp,caddi16spimm is cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3\n{\n\tsp = sp + caddi16spimm;\n}\n\n# c.addi4spn Ct,Cc,CK 00000000 0000e003 SIMPLE (0, 0) \n:c.addi4spn cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0\n{\n\tcr0204s = sp + caddi4spnimm;\n}\n\n@if (ADDRSIZE == \"64\") || (ADDRSIZE == \"128\")\n# c.addiw d,Co 00002001 0000e003 SIMPLE (64, 0) \n:c.addiw crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x1\n{\n\tlocal tmp:$(XLEN) = crd + cimmI;\n\tcrd = sext(tmp:$(WXLEN));\n}\n@endif\n\n@if (ADDRSIZE == \"64\") || (ADDRSIZE == \"128\")\n# c.addw Cs,Ct 00009c21 0000fc63 SIMPLE (64, 0) \n:c.addw cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7\n{\n\tlocal tmp:4 = cr0709s:4 + cr0204s:4;\n\tcr0709s = sext(tmp);\n}\n@endif\n\n# c.and Cs,Ct 00008c61 0000fc63 SIMPLE (0, 0) \n:c.and cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3\n{\n\tcr0709s = cr0709s & cr0204s;\n}\n\n# c.andi Cs,Co 00008801 0000ec03 SIMPLE (0, 0) \n:c.andi cr0709s,cimmI is cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2\n{\n\tcr0709s = cr0709s & cimmI;\n}\n\n# c.beqz Cs,Cp 0000c001 0000e003 CONDBRANCH (0, 0) \n:c.beqz cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x6\n{\n\tif (cr0709s == 0) goto cbimm;\n}\n\n# c.bnez Cs,Cp 0000e001 0000e003 CONDBRANCH (0, 0) \n:c.bnez cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x7\n{\n\tif (cr0709s != 0) goto cbimm;\n}\n\n# c.ebreak 00009002 0000ffff SIMPLE (0, 0) \n:c.ebreak is cop0001=0x2 & cop1315=0x4 & cop0212=0x400\n{\n\tebreak();\n}\n\n@if ADDRSIZE == \"32\" || ADDRSIZE == \"64\"\n@if FPSIZE == \"64\"\n# c.fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF (0, 8) \n:c.fld cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm\n{\n\tlocal ea:$(XLEN) = cldimm:$(XLEN) + cr0709s;\n\tcfr0204s = *[ram]:$(DFLEN) ea;\n}\n\n\n# c.fldsp D,Cn(Cc) 00002002 0000e003 QWORD|DREF (0, 8) \n:c.fldsp cfrd,cldspimm(sp) is cfrd & sp & cop0001=0x2 & cop1315=0x1 & cldspimm\n{\n\tlocal ea:$(XLEN) = cldspimm:$(XLEN) + sp;\n\tcfrd = *[ram]:$(DFLEN) ea;\n}\n@endif\n@endif\n\n@if ADDRSIZE == \"32\"\n# c.flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF (32, 4) \n:c.flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm\n{\n\tlocal ea:$(XLEN) = clwimm:$(XLEN) + cr0709s;\n\tcfr0204s = *[ram]:$(SFLEN) ea;\n}\n\n\n# c.flwsp D,Cm(Cc) 00006002 0000e003 DWORD|DREF (32, 4) \n:c.flwsp cfrd,clwspimm(sp) is cfrd & sp & cop0001=0x2 & cop1315=0x3 & clwspimm\n{\n\tlocal ea:$(XLEN) = clwspimm:$(XLEN) + sp;\n\tcfrd = *[ram]:$(SFLEN) ea;\n}\n@endif\n\n@if ADDRSIZE == \"32\" || ADDRSIZE == \"64\"\n@if FPSIZE == \"64\"\n# c.fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF (0, 8) \n:c.fsd cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm\n{\n\tlocal ea:$(XLEN) = cldimm + cr0709s;\n\t*[ram]:8 ea = cfr0204s;\n}\n\n# c.fsdsp CT,CN(Cc) 0000a002 0000e003 QWORD|DREF (0, 8) \n:c.fsdsp cfr0206,csdspimm(sp) is cfr0206 & sp & cop0001=0x2 & cop1315=0x5 & csdspimm\n{\n\tlocal ea:$(XLEN) = csdspimm + sp;\n\t*[ram]:8 ea = cfr0206;\n}\n@endif\n@endif\n\n@if ADDRSIZE == \"32\"\n@if FPSIZE == \"32\" || FPSIZE == \"64\"\n# c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4) \n:c.fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm\n{\n\tlocal ea:$(XLEN) = clwimm + cr0709s;\n\t*[ram]:4 ea = cfr0204s;\n}\n\n# c.fswsp CT,CM(Cc) 0000e002 0000e003 DWORD|DREF (32, 4) \n:c.fswsp cfr0206,cswspimm(sp) is cfr0206 & sp & cop0001=0x2 & cop1315=0x7 & cswspimm\n{\n\tlocal ea:$(XLEN) = cswspimm + sp;\n\t*[ram]:4 ea = cfr0206:4;\n}\n@endif\n@endif\n\n# c.j Ca 0000a001 0000e003 BRANCH (0, 0) \n:c.j cjimm is cjimm & cop0001=0x1 & cop1315=0x5\n{\n\tgoto cjimm;\n}\n\n@if ADDRSIZE == \"32\"\n# c.jal Ca 00002001 0000e003 JSR (32, 0) \n:c.jal cjimm is cjimm & cop0001=0x1 & cop1315=0x1\n{\n\tra = inst_next;\n\tcall cjimm;\n}\n@endif\n\n# c.jalr d 00009002 0000f07f JSR (0, 0) \n:c.jalr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1\n{\n\tra = inst_next;\n\tcall [crd];\n}\n\n# c.jr d 00008002 0000f07f BRANCH (0, 0) \n:c.jr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0\n{\n\tgoto [crd];\n}\n\n# ret 00008082 0000ffff BRANCH|ALIAS (0, 0)\n:ret is cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711=1\n{\n\treturn [ra];\n}\n\n@if (ADDRSIZE == \"64\") || (ADDRSIZE == \"128\")\n# c.ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF (64, 8) \n:c.ld cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm\n{\n\tlocal ea:$(XLEN) = cldimm:$(XLEN) + cr0709s;\n\tassignD(cr0204s, *[ram]:$(DXLEN) ea);\n}\n@endif\n\n@if ADDRSIZE == \"128\"\n:c.lq cr0204s,clqimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clqimm\n{\n\tlocal ea:$(XLEN) = clqimm:$(XLEN) + cr0709s;\n\tcr0204s = *[ram]:$(QXLEN) ea;\n}\n@endif\n\n@if (ADDRSIZE == \"64\") || (ADDRSIZE == \"128\")\n# c.ldsp d,Cn(Cc) 00006002 0000e003 QWORD|DREF (64, 8) \n:c.ldsp crd,cldspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm\n{\n\tlocal ea:$(XLEN) = cldspimm + sp;\n\tassignD(crd, *[ram]:$(DXLEN) ea);\n}\n@endif\n\n@if ADDRSIZE == \"128\"\n:c.lqsp crd,clqspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x1 & clqspimm\n{\n\tlocal ea:$(XLEN) = clqspimm + sp;\n\tcrd = *[ram]:$(QXLEN) ea;\n}\n@endif\n\n# c.li d,Co 00004001 0000e003 SIMPLE (0, 0) \n:c.li crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x2\n{\n\tcrd = cimmI;\n}\n\n# c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0) \n:c.lui cd0711NoSp,cbigimm is cd0711NoSp & cbigimm & cop0001=0x1 & cop1315=0x3\n{\n\tcd0711NoSp = cbigimm;\n}\n\n# c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4) \n:c.lw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm\n{\n\tlocal ea:$(XLEN) = clwimm + cr0709s;\n\tassignW(cr0204s, *[ram]:4 ea);\n}\n\n# c.lwsp d,Cm(Cc) 00004002 0000e003 SIMPLE (0, 0) \n:c.lwsp crd,clwspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm\n{\n\tlocal ea:$(XLEN) = clwspimm + sp;\n\tassignW(crd, *[ram]:4 ea);\n}\n\n# c.mv d,CV 00008002 0000f003 SIMPLE (0, 0) \n:c.mv crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0\n{\n\tcrd = crs2;\n}\n\n# c.or Cs,Ct 00008c41 0000fc63 SIMPLE (0, 0) \n:c.or cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3\n{\n\tcr0709s = cr0709s | cr0204s;\n}\n\n@if (ADDRSIZE == \"64\") || (ADDRSIZE == \"128\")\n# c.sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF (64, 8) \n:c.sd cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm\n{\n\tlocal ea:$(XLEN) = cldimm:$(XLEN) + cr0709s;\n\t*[ram]:$(DXLEN) ea = cr0204s:$(DXLEN);\n}\n\n# c.sdsp CV,CN(Cc) 0000e002 0000e003 QWORD|DREF (64, 8) \n:c.sdsp crs2,csdspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x7 & csdspimm\n{\n\tlocal ea:$(XLEN) = csdspimm:$(XLEN) + sp;\n\t*[ram]:$(DXLEN) ea = crs2:$(DXLEN);\n}\n@endif\n\n# c.slli d,C> 00000002 0000e003 SIMPLE (0, 0) \n:c.slli crd,c6imm is crd & c6imm & cop0001=0x2 & cop1315=0x0\n{\n\tcrd = crd << c6imm;\n}\n\n#TODO hint?\n# c.slli64 d 00000002 0000f07f SIMPLE (0, 0) \n:c.slli64 crd is crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0\n{\n\tcrd = crd << 0;\n}\n\n# c.srai Cs,C> 00008401 0000ec03 SIMPLE (0, 0) \n:c.srai cr0709s,c6imm is c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1\n{\n\tcr0709s = cr0709s s>> c6imm;\n}\n\n#TODO hint?\n# c.srai64 Cs 00008401 0000fc7f SIMPLE (0, 0) \n:c.srai64 cr0709s is cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x1\n{\n\tcr0709s = cr0709s s>> 0;\n}\n\n# c.srli Cs,C> 00008001 0000ec03 SIMPLE (0, 0) \n:c.srli cr0709s,c6imm is c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0\n{\n\tcr0709s = cr0709s >> c6imm;\n}\n\n#TODO hint?\n# c.srli64 Cs 00008001 0000fc7f SIMPLE (0, 0) \n:c.srli64 cr0709s is cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x0\n{\n\tcr0709s = cr0709s >> 0;\n}\n\n# c.sub Cs,Ct 00008c01 0000fc63 SIMPLE (0, 0) \n:c.sub cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3\n{\n\tcr0709s = cr0709s - cr0204s;\n}\n\n@if (ADDRSIZE == \"64\") || (ADDRSIZE == \"128\")\n# c.subw Cs,Ct 00009c01 0000fc63 SIMPLE (64, 0) \n:c.subw cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7\n{\n\tlocal tmp:4 = cr0709s:4 - cr0204s:4;\n\tcr0709s = sext(tmp);\n}\n@endif\n\n# c.sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF (0, 4) \n:c.sw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm\n{\n\tlocal ea:$(XLEN) = clwimm + cr0709s;\n\t*[ram]:4 ea = cr0204s:4;\n}\n\n@if ADDRSIZE == \"128\"\n:c.sq cr0204s,clqimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clqimm\n{\n\tlocal ea:$(XLEN) = clqimm + cr0709s;\n\t*[ram]:16 ea = cr0204s;\n}\n\n:c.sqsp crs2,csqspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x5 & csqspimm\n{\n\tlocal ea:$(XLEN) = csqspimm + sp;\n\t*[ram]:16 ea = crs2;\n}\n@endif\n\n# c.swsp CV,CM(Cc) 0000c002 0000e003 DWORD|DREF (0, 4) \n:c.swsp crs2,cswspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm\n{\n\tlocal ea:$(XLEN) = cswspimm + sp;\n\t*[ram]:4 ea = crs2:4;\n}\n\n# c.unimp 00000000 0000ffff SIMPLE (0, 0)\n# would be better not to decode as it is used as padding\n#\n# :c.unimp is cop0001=0x0 & cop1315=0x0 & cop0212=0x0\n#{\n#\ttrap();\n#}\n\n# c.xor Cs,Ct 00008c21 0000fc63 SIMPLE (0, 0) \n:c.xor cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3\n{\n\tcr0709s = cr0709s ^ cr0204s;\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.rvv.sinc", "content": "# Vector\n\n# sew: \"e8\" is vsew=0 {}\n# sew: \"e16\" is vsew=1 {}\n# sew: \"e32\" is vsew=2 {}\n# sew: \"e64\" is vsew=3 {}\n# sew: \"e128\" is vsew=4 {}\n# sew: \"e256\" is vsew=5 {}\n# sew: \"e512\" is vsew=6 {}\n# sew: \"e1024\" is vsew=7 {}\n\n# vmul: \"m1\" is vlmul=0 {}\n# vmul: \"m2\" is vlmul=1 {}\n# vmul: \"m4\" is vlmul=2 {}\n# vmul: \"m8\" is vlmul=3 {}\n# vmul: \"mf8\" is vlmul=5 {}\n# vmul: \"mf4\" is vlmul=6 {}\n# vmul: \"mf2\" is vlmul=7 {}\n\n# vmask: \"mu\" is vma=0 {}\n# vmask: \"ma\" is vma=1 {}\n# vtail: \"tu\" is vta=0 {}\n# vtail: \"ta\" is vta=1 {}\n\n#TODO possible tables\n# mop=0 unit-stride VLE\n# mop=2 strided VLSE\n# mop=3 indexed VLXEI\n# mop=0 unit-stride VSE\n# mop=1 indexed-unordered VSUXEI\n# mop=2 strided VSSE\n# mop=3 indexed-ordered VSXEI\n# lumop=0 unit-stride\n# lumop=8 unit-stride,whole registers\n# lumop=16 unit-stride fault-only-first\n# sumop=0 unit-stride\n# sumop=8 unit-stride,whole registers\n# sumop=16 unit-stride fault-only-first\n# nfields imm is nf [ imm = nf + 1; ] { export *[const]:1 imm; }\n\n\n# vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1)\n:vaadd.vv vd, vs2, vs1^ vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1)\n:vaadd.vx vd, vs2, rs1^ vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1)\n:vaaddu.vv vd, vs2, vs1^ vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1)\n:vaaddu.vx vd, vs2, rs1^ vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vadc.vim vd, vs2, simm5, v0 # Vector-immediate\n:vadc.vim vd, vs2, simm5, v0 is op2631=0x10 & op2525=0x0 & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl\n\n# vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vadc.vvm vd, vs2, vs1, v0 # Vector-vector\n:vadc.vvm vd, vs2, vs1, v0 is op2631=0x10 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl\n\n# vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vadc.vxm vd, vs2, rs1, v0 # Vector-scalar\n:vadc.vxm vd, vs2, rs1, v0 is op2631=0x10 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl\n\n# vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vadd.vi vd, vs2, simm5, vm # vector-immediate\n:vadd.vi vd, vs2, simm5^ vm is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vadd.vv vd, vs2, vs1, vm # Vector-vector\n:vadd.vv vd, vs2, vs1^ vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vadd.vx vd, vs2, rs1, vm # vector-scalar\n:vadd.vx vd, vs2, rs1^ vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoaddei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoaddei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoaddei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoaddei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoaddei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoaddei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoaddei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoaddei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoaddei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoaddei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoaddei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoaddei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoaddei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoaddei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoaddei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoaddei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoandei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoandei16.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoandei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoandei16.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoandei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoandei32.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoandei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoandei32.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoandei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoandei64.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoandei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoandei64.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoandei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoandei8.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoandei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoandei8.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamomaxei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamomaxei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamomaxei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamomaxei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamomaxei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamomaxei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamomaxei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamomaxei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamomaxuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxuei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamomaxuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxuei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamomaxuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxuei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamomaxuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxuei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamomaxuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxuei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamomaxuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxuei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamomaxuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamomaxuei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamomaxuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamomaxuei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamominei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamominei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamominei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamominei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamominei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamominei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamominei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamominei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamominuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominuei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamominuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominuei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamominuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominuei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamominuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominuei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamominuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominuei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamominuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominuei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamominuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamominuei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamominuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamominuei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoorei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoorei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoorei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoorei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoorei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoorei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoorei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoorei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoswapei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoswapei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoswapei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoswapei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoswapei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoswapei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoswapei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoswapei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoswapei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoswapei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoswapei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoswapei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoswapei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoswapei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoswapei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoswapei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoxorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoxorei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f\n# vamoxorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoxorei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoxorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoxorei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f\n# vamoxorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoxorei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoxorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoxorei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f\n# vamoxorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoxorei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl\n\n# vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoxorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1\n:vamoxorei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl\n\n# vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f\n# vamoxorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0\n:vamoxorei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl\n\n# vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vand.vi vd, vs2, simm5, vm # vector-immediate\n:vand.vi vd, vs2, simm5^ vm is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vand.vv vd, vs2, vs1, vm # Vector-vector\n:vand.vv vd, vs2, vs1^ vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vand.vx vd, vs2, rs1, vm # vector-scalar\n:vand.vx vd, vs2, rs1^ vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1)\n:vasub.vv vd, vs2, vs1^ vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1)\n:vasub.vx vd, vs2, rs1^ vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1)\n:vasubu.vv vd, vs2, vs1^ vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1)\n:vasubu.vx vd, vs2, rs1^ vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled\n:vcompress.vm vd, vs2, vs1 is op2631=0x17 & op2525=0x1 & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vdiv.vv vd, vs2, vs1, vm # Vector-vector\n:vdiv.vv vd, vs2, vs1^ vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vdiv.vx vd, vs2, rs1, vm # vector-scalar\n:vdiv.vx vd, vs2, rs1^ vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vdivu.vv vd, vs2, vs1, vm # Vector-vector\n:vdivu.vv vd, vs2, vs1^ vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vdivu.vx vd, vs2, rs1, vm # vector-scalar\n:vdivu.vx vd, vs2, rs1^ vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vdot.vv vd, vs2, vs1, vm # Vector-vector\n:vdot.vv vd, vs2, vs1^ vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vdotu.vv 31..26=0x38 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vdotu.vv vd, vs2, vs1, vm # Vector-vector\n:vdotu.vv vd, vs2, vs1^ vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfadd.vf vd, vs2, rs1, vm # vector-scalar\n:vfadd.vf vd, vs2, rs1^ vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfadd.vv vd, vs2, vs1, vm # Vector-vector\n:vfadd.vv vd, vs2, vs1^ vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57\n# vfclass.v vd, vs2, vm # Vector-vector\n:vfclass.v vd, vs2^ vm is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57\n# vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.\n:vfcvt.f.x.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57\n# vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float.\n:vfcvt.f.xu.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57\n# vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating.\n:vfcvt.rtz.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57\n# vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating.\n:vfcvt.rtz.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57\n# vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer.\n:vfcvt.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57\n# vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer.\n:vfcvt.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfdiv.vf vd, vs2, rs1, vm # vector-scalar\n:vfdiv.vf vd, vs2, rs1^ vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfdiv.vv vd, vs2, vs1, vm # Vector-vector\n:vfdiv.vv vd, vs2, vs1^ vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfdot.vv vd, vs2, vs1, vm # Vector-vector\n:vfdot.vv vd, vs2, vs1^ vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57\n# vfirst.m rd, vs2, vm\n:vfirst.m rd, vs2^ vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57 unimpl\n\n# vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i]\n:vfmacc.vf vd, rs1, vs2^ vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vfmacc.vv vd, vs1, vs2^ vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i]\n:vfmadd.vf vd, rs1, vs2^ vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i]\n:vfmadd.vv vd, vs1, vs2^ vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmax.vf vd, vs2, rs1, vm # vector-scalar\n:vfmax.vf vd, vs2, rs1^ vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmax.vv vd, vs2, vs1, vm # Vector-vector\n:vfmax.vv vd, vs2, vs1^ vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i]\n:vfmerge.vfm vd, vs2, rs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & rs1 & op1214=0x5 & v0 & vd & op0006=0x57 unimpl\n\n# vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmin.vf vd, vs2, rs1, vm # vector-scalar\n:vfmin.vf vd, vs2, rs1^ vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmin.vv vd, vs2, vs1, vm # Vector-vector\n:vfmin.vv vd, vs2, vs1^ vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i]\n:vfmsac.vf vd, rs1, vs2^ vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i]\n:vfmsac.vv vd, vs1, vs2^ vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i]\n:vfmsub.vf vd, rs1, vs2^ vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i]\n:vfmsub.vv vd, vs1, vs2^ vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfmul.vf vd, vs2, rs1, vm # vector-scalar\n:vfmul.vf vd, vs2, rs1^ vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfmul.vv vd, vs2, vs1, vm # Vector-vector\n:vfmul.vv vd, vs2, vs1^ vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57\n# vfmv.f.s rd, vs2 # f[rd] = vs2[0] (rs1=0)\n:vfmv.f.s rd, vs2 is op2631=0x10 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x1 & rd & op0006=0x57 unimpl\n\n# vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57\n# vfmv.s.f vd, rs1 # vd[0] = f[rs1] (vs2=0)\n:vfmv.s.f vd, rs1 is op2631=0x10 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57\n# vfmv.v.f vd, rs1 # vd[i] = f[rs1]\n:vfmv.v.f vd, rs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57\n# vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float.\n:vfncvt.f.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57\n# vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float.\n:vfncvt.f.x.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57\n# vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float.\n:vfncvt.f.xu.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57\n# vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float,\n:vfncvt.rod.f.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57\n# vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating.\n:vfncvt.rtz.x.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57\n# vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating.\n:vfncvt.rtz.xu.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57\n# vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer.\n:vfncvt.x.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57\n# vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer.\n:vfncvt.xu.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i]\n:vfnmacc.vf vd, rs1, vs2^ vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i]\n:vfnmacc.vv vd, vs1, vs2^ vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i]\n:vfnmadd.vf vd, rs1, vs2^ vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i]\n:vfnmadd.vv vd, vs1, vs2^ vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]\n:vfnmsac.vf vd, rs1, vs2^ vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i]\n:vfnmsac.vv vd, vs1, vs2^ vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i]\n:vfnmsub.vf vd, rs1, vs2^ vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i]\n:vfnmsub.vv vd, vs1, vs2^ vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i]\n:vfrdiv.vf vd, vs2, rs1^ vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfredmax.vs vd, vs2, vs1, vm # Maximum value\n:vfredmax.vs vd, vs2, vs1^ vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfredmin.vs vd, vs2, vs1, vm # Minimum value\n:vfredmin.vs vd, vs2, vs1^ vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfredosum.vs vd, vs2, vs1, vm # Ordered sum\n:vfredosum.vs vd, vs2, vs1^ vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfredsum.vs vd, vs2, vs1, vm # Unordered sum\n:vfredsum.vs vd, vs2, vs1^ vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i]\n:vfrsub.vf vd, vs2, rs1^ vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfsgnj.vf vd, vs2, rs1, vm # vector-scalar\n:vfsgnj.vf vd, vs2, rs1^ vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfsgnj.vv vd, vs2, vs1, vm # Vector-vector\n:vfsgnj.vv vd, vs2, vs1^ vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar\n:vfsgnjn.vf vd, vs2, rs1^ vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector\n:vfsgnjn.vv vd, vs2, vs1^ vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar\n:vfsgnjx.vf vd, vs2, rs1^ vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector\n:vfsgnjx.vv vd, vs2, vs1^ vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]\n:vfslide1down.vf vd, vs2, rs1^ vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i]\n:vfslide1up.vf vd, vs2, rs1^ vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57\n# vfsqrt.v vd, vs2, vm # Vector-vector square root\n:vfsqrt.v vd, vs2^ vm is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1]\n:vfsub.vf vd, vs2, rs1^ vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfsub.vv vd, vs2, vs1, vm # Vector-vector\n:vfsub.vv vd, vs2, vs1^ vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwadd.vf vd, vs2, rs1, vm # vector-scalar\n:vfwadd.vf vd, vs2, rs1^ vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwadd.vv vd, vs2, vs1, vm # vector-vector\n:vfwadd.vv vd, vs2, vs1^ vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwadd.wf vd, vs2, rs1, vm # vector-scalar\n:vfwadd.wf vd, vs2, rs1^ vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwadd.wv vd, vs2, vs1, vm # vector-vector\n:vfwadd.wv vd, vs2, vs1^ vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57\n# vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.\n:vfwcvt.f.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57\n# vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float.\n:vfwcvt.f.x.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57\n# vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float.\n:vfwcvt.f.xu.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57\n# vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating.\n:vfwcvt.rtz.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57\n# vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating.\n:vfwcvt.rtz.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57\n# vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer.\n:vfwcvt.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57\n# vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.\n:vfwcvt.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i]\n:vfwmacc.vf vd, rs1, vs2^ vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vfwmacc.vv vd, vs1, vs2^ vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i]\n:vfwmsac.vf vd, rs1, vs2^ vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i]\n:vfwmsac.vv vd, vs1, vs2^ vm is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwmul.vf vd, vs2, rs1, vm # vector-scalar\n:vfwmul.vf vd, vs2, rs1^ vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwmul.vv vd, vs2, vs1, vm # vector-vector\n:vfwmul.vv vd, vs2, vs1^ vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i]\n:vfwnmacc.vf vd, rs1, vs2^ vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i]\n:vfwnmacc.vv vd, vs1, vs2^ vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]\n:vfwnmsac.vf vd, rs1, vs2^ vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i]\n:vfwnmsac.vv vd, vs1, vs2^ vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwredosum.vs vd, vs2, vs1, vm # Ordered sum\n:vfwredosum.vs vd, vs2, vs1^ vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwredsum.vs vd, vs2, vs1, vm # Unordered sum\n:vfwredsum.vs vd, vs2, vs1^ vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwsub.vf vd, vs2, rs1, vm # vector-scalar\n:vfwsub.vf vd, vs2, rs1^ vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwsub.vv vd, vs2, vs1, vm # vector-vector\n:vfwsub.vv vd, vs2, vs1^ vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vfwsub.wf vd, vs2, rs1, vm # vector-scalar\n:vfwsub.wf vd, vs2, rs1^ vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vfwsub.wv vd, vs2, vs1, vm # vector-vector\n:vfwsub.wv vd, vs2, vs1^ vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57\n# vid.v vd, vm # Write element ID to destination.\n:vid.v vd^ vm is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57\n# viota.m vd, vs2, vm\n:viota.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07\n# vl1re16.v vd, (rs1)\n:vl1re16.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07\n# vl1re32.v vd, (rs1)\n:vl1re32.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07\n# vl1re64.v vd, (rs1)\n:vl1re64.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07\n# vl1re8.v vd, (rs1)\n:vl1re8.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07\n# vl2re16.v vd, (rs1)\n:vl2re16.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07\n# vl2re32.v vd, (rs1)\n:vl2re32.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07\n# vl2re64.v vd, (rs1)\n:vl2re64.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07\n# vl2re8.v vd, (rs1)\n:vl2re8.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07\n# vl4re16.v vd, (rs1)\n:vl4re16.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07\n# vl4re32.v vd, (rs1)\n:vl4re32.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07\n# vl4re64.v vd, (rs1)\n:vl4re64.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07\n# vl4re8.v vd, (rs1)\n:vl4re8.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07\n# vl8re16.v vd, (rs1)\n:vl8re16.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07\n# vl8re32.v vd, (rs1)\n:vl8re32.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07\n# vl8re64.v vd, (rs1)\n:vl8re64.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07\n# vl8re8.v vd, (rs1)\n:vl8re8.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07\n# vle1024.v vd, (rs1), vm # 1024-bit unit-stride load\n:vle1024.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07\n# vle1024ff.v vd, (rs1), vm # 1024-bit unit-stride fault-only-first load\n:vle1024ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07\n# vle128.v vd, (rs1), vm # 128-bit unit-stride load\n:vle128.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07\n# vle128ff.v vd, (rs1), vm # 128-bit unit-stride fault-only-first load\n:vle128ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07\n# vle16.v vd, (rs1), vm # 16-bit unit-stride load\n:vle16.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07\n# vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load\n:vle16ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07\n# vle256.v vd, (rs1), vm # 256-bit unit-stride load\n:vle256.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07\n# vle256ff.v vd, (rs1), vm # 256-bit unit-stride fault-only-first load\n:vle256ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07\n# vle32.v vd, (rs1), vm # 32-bit unit-stride load\n:vle32.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07\n# vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load\n:vle32ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07\n# vle512.v vd, (rs1), vm # 512-bit unit-stride load\n:vle512.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07\n# vle512ff.v vd, (rs1), vm # 512-bit unit-stride fault-only-first load\n:vle512ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07\n# vle64.v vd, (rs1), vm # 64-bit unit-stride load\n:vle64.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07\n# vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load\n:vle64ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07\n# vle8.v vd, (rs1), vm # 8-bit unit-stride load\n:vle8.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07\n# vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load\n:vle8ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07\n# vlse1024.v vd, (rs1), rs2, vm # 1024-bit strided load\n:vlse1024.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07\n# vlse128.v vd, (rs1), rs2, vm # 128-bit strided load\n:vlse128.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07\n# vlse16.v vd, (rs1), rs2, vm # 16-bit strided load\n:vlse16.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07\n# vlse256.v vd, (rs1), rs2, vm # 256-bit strided load\n:vlse256.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07\n# vlse32.v vd, (rs1), rs2, vm # 32-bit strided load\n:vlse32.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07\n# vlse512.v vd, (rs1), rs2, vm # 512-bit strided load\n:vlse512.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07\n# vlse64.v vd, (rs1), rs2, vm # 64-bit strided load\n:vlse64.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07\n# vlse8.v vd, (rs1), rs2, vm # 8-bit strided load\n:vlse8.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vlxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07\n# vlxei1024.v vd, (rs1), vs2, vm # 1024-bit indexed load of SEW data\n:vlxei1024.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vlxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07\n# vlxei128.v vd, (rs1), vs2, vm # 128-bit indexed load of SEW data\n:vlxei128.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vlxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07\n# vlxei16.v vd, (rs1), vs2, vm # 16-bit indexed load of SEW data\n:vlxei16.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vlxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07\n# vlxei256.v vd, (rs1), vs2, vm # 256-bit indexed load of SEW data\n:vlxei256.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl\n\n# vlxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07\n# vlxei32.v vd, (rs1), vs2, vm # 32-bit indexed load of SEW data\n:vlxei32.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vlxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07\n# vlxei512.v vd, (rs1), vs2, vm # 512-bit indexed load of SEW data\n:vlxei512.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl\n\n# vlxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07\n# vlxei64.v vd, (rs1), vs2, vm # 64-bit indexed load of SEW data\n:vlxei64.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl\n\n# vlxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07\n# vlxei8.v vd, (rs1), vs2, vm # 8-bit indexed load of SEW data\n:vlxei8.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl\n\n# vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vmacc.vv vd, vs1, vs2^ vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]\n:vmacc.vx vd, rs1, vs2^ vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmadc.vim 31..26=0x11 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmadc.vim vd, vs2, simm5, v0 # Vector-immediate\n:vmadc.vim vd, vs2, simm5, v0 is op2631=0x11 & vm & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl\n\n# vmadc.vvm 31..26=0x11 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmadc.vvm vd, vs2, vs1, v0 # Vector-vector\n:vmadc.vvm vd, vs2, vs1, v0 is op2631=0x11 & vm & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl\n\n# vmadc.vxm 31..26=0x11 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar\n:vmadc.vxm vd, vs2, rs1, v0 is op2631=0x11 & vm & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl\n\n# vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i]\n:vmadd.vv vd, vs1, vs2^ vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i]\n:vmadd.vx vd, rs1, vs2^ vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmand.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && vs1.mask[i]\n:vmand.mm vd, vs2, vs1 is op2631=0x19 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmandnot.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && !vs1.mask[i]\n:vmandnot.mm vd, vs2, vs1 is op2631=0x18 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmax.vv vd, vs2, vs1, vm # Vector-vector\n:vmax.vv vd, vs2, vs1^ vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmax.vx vd, vs2, rs1, vm # vector-scalar\n:vmax.vx vd, vs2, rs1^ vm is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmaxu.vv vd, vs2, vs1, vm # Vector-vector\n:vmaxu.vv vd, vs2, vs1^ vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmaxu.vx vd, vs2, rs1, vm # vector-scalar\n:vmaxu.vx vd, vs2, rs1^ vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmerge.vim vd, vs2, simm5, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]\n:vmerge.vim vd, vs2, simm5, v0 is op2631=0x17 & op2525=0x0 & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl\n\n# vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i]\n:vmerge.vvm vd, vs2, vs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl\n\n# vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i]\n:vmerge.vxm vd, vs2, rs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl\n\n# vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vmfeq.vf vd, vs2, rs1, vm # vector-scalar\n:vmfeq.vf vd, vs2, rs1^ vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vmfeq.vv vd, vs2, vs1, vm # Vector-vector\n:vmfeq.vv vd, vs2, vs1^ vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vmfge.vf vd, vs2, rs1, vm # vector-scalar\n:vmfge.vf vd, vs2, rs1^ vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vmfgt.vf vd, vs2, rs1, vm # vector-scalar\n:vmfgt.vf vd, vs2, rs1^ vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vmfle.vf vd, vs2, rs1, vm # vector-scalar\n:vmfle.vf vd, vs2, rs1^ vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vmfle.vv vd, vs2, vs1, vm # Vector-vector\n:vmfle.vv vd, vs2, vs1^ vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vmflt.vf vd, vs2, rs1, vm # vector-scalar\n:vmflt.vf vd, vs2, rs1^ vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vmflt.vv vd, vs2, vs1, vm # Vector-vector\n:vmflt.vv vd, vs2, vs1^ vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57\n# vmfne.vf vd, vs2, rs1, vm # vector-scalar\n:vmfne.vf vd, vs2, rs1^ vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl\n\n# vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57\n# vmfne.vv vd, vs2, vs1, vm # Vector-vector\n:vmfne.vv vd, vs2, vs1^ vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl\n\n# vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmin.vv vd, vs2, vs1, vm # Vector-vector\n:vmin.vv vd, vs2, vs1^ vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmin.vx vd, vs2, rs1, vm # vector-scalar\n:vmin.vx vd, vs2, rs1^ vm is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vminu.vv vd, vs2, vs1, vm # Vector-vector\n:vminu.vv vd, vs2, vs1^ vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vminu.vx vd, vs2, rs1, vm # vector-scalar\n:vminu.vx vd, vs2, rs1^ vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmnand.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] && vs1.mask[i])\n:vmnand.mm vd, vs2, vs1 is op2631=0x1d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmnor.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] || vs1.mask[i])\n:vmnor.mm vd, vs2, vs1 is op2631=0x1e & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmor.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] || vs1.mask[i]\n:vmor.mm vd, vs2, vs1 is op2631=0x1a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmornot.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] || !vs1.mask[i]\n:vmornot.mm vd, vs2, vs1 is op2631=0x1c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmsbc.vvm 31..26=0x13 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector\n:vmsbc.vvm vd, vs2, vs1, v0 is op2631=0x13 & vm & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl\n\n# vmsbc.vxm 31..26=0x13 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar\n:vmsbc.vxm vd, vs2, rs1, v0 is op2631=0x13 & vm & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl\n\n# vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57\n# vmsbf.m vd, vs2, vm\n:vmsbf.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmseq.vi vd, vs2, simm5, vm # vector-immediate\n:vmseq.vi vd, vs2, simm5^ vm is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmseq.vv vd, vs2, vs1, vm # Vector-vector\n:vmseq.vv vd, vs2, vs1^ vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmseq.vx vd, vs2, rs1, vm # vector-scalar\n:vmseq.vx vd, vs2, rs1^ vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmsgt.vi vd, vs2, simm5, vm # Vector-immediate\n:vmsgt.vi vd, vs2, simm5^ vm is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsgt.vx vd, vs2, rs1, vm # Vector-scalar\n:vmsgt.vx vd, vs2, rs1^ vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmsgtu.vi vd, vs2, simm5, vm # Vector-immediate\n:vmsgtu.vi vd, vs2, simm5^ vm is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar\n:vmsgtu.vx vd, vs2, rs1^ vm is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57\n# vmsif.m vd, vs2, vm\n:vmsif.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmsle.vi vd, vs2, simm5, vm # vector-immediate\n:vmsle.vi vd, vs2, simm5^ vm is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmsle.vv vd, vs2, vs1, vm # Vector-vector\n:vmsle.vv vd, vs2, vs1^ vm is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsle.vx vd, vs2, rs1, vm # vector-scalar\n:vmsle.vx vd, vs2, rs1^ vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmsleu.vi vd, vs2, simm5, vm # Vector-immediate\n:vmsleu.vi vd, vs2, simm5^ vm is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmsleu.vv vd, vs2, vs1, vm # Vector-vector\n:vmsleu.vv vd, vs2, vs1^ vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsleu.vx vd, vs2, rs1, vm # vector-scalar\n:vmsleu.vx vd, vs2, rs1^ vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmslt.vv vd, vs2, vs1, vm # Vector-vector\n:vmslt.vv vd, vs2, vs1^ vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmslt.vx vd, vs2, rs1, vm # vector-scalar\n:vmslt.vx vd, vs2, rs1^ vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmsltu.vv vd, vs2, vs1, vm # Vector-vector\n:vmsltu.vv vd, vs2, vs1^ vm is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsltu.vx vd, vs2, rs1, vm # Vector-scalar\n:vmsltu.vx vd, vs2, rs1^ vm is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vmsne.vi vd, vs2, simm5, vm # vector-immediate\n:vmsne.vi vd, vs2, simm5^ vm is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vmsne.vv vd, vs2, vs1, vm # Vector-vector\n:vmsne.vv vd, vs2, vs1^ vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vmsne.vx vd, vs2, rs1, vm # vector-scalar\n:vmsne.vx vd, vs2, rs1^ vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57\n# vmsof.m vd, vs2, vm\n:vmsof.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmul.vv vd, vs2, vs1, vm # Vector-vector\n:vmul.vv vd, vs2, vs1^ vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vmul.vx vd, vs2, rs1, vm # vector-scalar\n:vmul.vx vd, vs2, rs1^ vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmulh.vv vd, vs2, vs1, vm # Vector-vector\n:vmulh.vv vd, vs2, vs1^ vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vmulh.vx vd, vs2, rs1, vm # vector-scalar\n:vmulh.vx vd, vs2, rs1^ vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmulhsu.vv vd, vs2, vs1, vm # Vector-vector\n:vmulhsu.vv vd, vs2, vs1^ vm is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vmulhsu.vx vd, vs2, rs1, vm # vector-scalar\n:vmulhsu.vx vd, vs2, rs1^ vm is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmulhu.vv vd, vs2, vs1, vm # Vector-vector\n:vmulhu.vv vd, vs2, vs1^ vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vmulhu.vx vd, vs2, rs1, vm # vector-scalar\n:vmulhu.vx vd, vs2, rs1^ vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57\n# vmv.s.x vd, rs1 # vd[0] = x[rs1] (vs2=0)\n:vmv.s.x vd, rs1 is op2631=0x10 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57\n# vmv.v.i vd, simm5 # vd[i] = imm\n:vmv.v.i vd, simm5 is op2631=0x17 & op2525=0x1 & op2024=0x0 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57\n# vmv.v.v vd, vs1 # vd[i] = vs1[i]\n:vmv.v.v vd, vs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57\n# vmv.v.x vd, rs1 # vd[i] = rs1\n:vmv.v.x vd, rs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 vd 6..0=0x57\n# vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0)\n:vmv.x.s rd, vs2 is op2631=0x10 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x2 & rd & vd & op0006=0x57 unimpl\n\n# vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57\n# vmv1r.v vd, vs2\n:vmv1r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57\n# vmv2r.v vd, vs2\n:vmv2r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x1 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57\n# vmv4r.v vd, vs2\n:vmv4r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x3 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57\n# vmv8r.v vd, vs2\n:vmv8r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x7 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmxnor.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] ^^ vs1.mask[i])\n:vmxnor.mm vd, vs2, vs1 is op2631=0x1f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vmxor.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] ^^ vs1.mask[i]\n:vmxor.mm vd, vs2, vs1 is op2631=0x1b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vnclip.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm5))\n:vnclip.wi vd, vs2, simm5^ vm is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i]))\n:vnclip.wv vd, vs2, vs1^ vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1]))\n:vnclip.wx vd, vs2, rs1^ vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vnclipu.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5))\n:vnclipu.wi vd, vs2, simm5^ vm is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i]))\n:vnclipu.wv vd, vs2, vs1^ vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1]))\n:vnclipu.wx vd, vs2, rs1^ vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i]\n:vnmsac.vv vd, vs1, vs2^ vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i]\n:vnmsac.vx vd, rs1, vs2^ vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i]\n:vnmsub.vv vd, vs1, vs2^ vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]\n:vnmsub.vx vd, rs1, vs2^ vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vnsra.wi vd, vs2, simm5, vm # vector-immediate\n:vnsra.wi vd, vs2, simm5^ vm is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vnsra.wv vd, vs2, vs1, vm # vector-vector\n:vnsra.wv vd, vs2, vs1^ vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vnsra.wx vd, vs2, rs1, vm # vector-scalar\n:vnsra.wx vd, vs2, rs1^ vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vnsrl.wi vd, vs2, simm5, vm # vector-immediate\n:vnsrl.wi vd, vs2, simm5^ vm is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vnsrl.wv vd, vs2, vs1, vm # vector-vector\n:vnsrl.wv vd, vs2, vs1^ vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vnsrl.wx vd, vs2, rs1, vm # vector-scalar\n:vnsrl.wx vd, vs2, rs1^ vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vor.vi vd, vs2, simm5, vm # vector-immediate\n:vor.vi vd, vs2, simm5^ vm is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vor.vv vd, vs2, vs1, vm # Vector-vector\n:vor.vv vd, vs2, vs1^ vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vor.vx vd, vs2, rs1, vm # vector-scalar\n:vor.vx vd, vs2, rs1^ vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57\n# vpopc.m rd, vs2, vm # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] )\n:vpopc.m rd, vs2^ vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57 unimpl\n\n# vqmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vqmacc.vv vd, vs1, vs2^ vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vqmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]\n:vqmacc.vx vd, rs1, vs2^ vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vqmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i]\n:vqmaccsu.vv vd, vs1, vs2^ vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vqmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i]\n:vqmaccsu.vx vd, rs1, vs2^ vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vqmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vqmaccu.vv vd, vs1, vs2^ vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vqmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]\n:vqmaccu.vx vd, rs1, vs2^ vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vqmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]\n:vqmaccus.vx vd, rs1, vs2^ vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] )\n:vredand.vs vd, vs2, vs1^ vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] )\n:vredmax.vs vd, vs2, vs1^ vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] )\n:vredmaxu.vs vd, vs2, vs1^ vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] )\n:vredmin.vs vd, vs2, vs1^ vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] )\n:vredminu.vs vd, vs2, vs1^ vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] )\n:vredor.vs vd, vs2, vs1^ vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] )\n:vredsum.vs vd, vs2, vs1^ vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] )\n:vredxor.vs vd, vs2, vs1^ vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vrem.vv vd, vs2, vs1, vm # Vector-vector\n:vrem.vv vd, vs2, vs1^ vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vrem.vx vd, vs2, rs1, vm # vector-scalar\n:vrem.vx vd, vs2, rs1^ vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vremu.vv vd, vs2, vs1, vm # Vector-vector\n:vremu.vv vd, vs2, vs1^ vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vremu.vx vd, vs2, rs1, vm # vector-scalar\n:vremu.vx vd, vs2, rs1^ vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vrgather.vi vd, vs2, simm5, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]\n:vrgather.vi vd, vs2, simm5^ vm is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];\n:vrgather.vv vd, vs2, vs1^ vm is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]]\n:vrgather.vx vd, vs2, rs1^ vm is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];\n:vrgatherei16.vv vd, vs2, vs1^ vm is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vrsub.vi vd, vs2, simm5, vm # vd[i] = imm - vs2[i]\n:vrsub.vi vd, vs2, simm5^ vm is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i]\n:vrsub.vx vd, vs2, rs1^ vm is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27\n# vs1r.v vs3, (rs1)\n:vs1r.v vs3, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27\n# vs2r.v vs3, (rs1)\n:vs2r.v vs3, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27\n# vs4r.v vs3, (rs1)\n:vs4r.v vs3, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27\n# vs8r.v vs3, (rs1)\n:vs8r.v vs3, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vsadd.vi vd, vs2, simm5, vm # vector-immediate\n:vsadd.vi vd, vs2, simm5^ vm is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsadd.vv vd, vs2, vs1, vm # Vector-vector\n:vsadd.vv vd, vs2, vs1^ vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsadd.vx vd, vs2, rs1, vm # vector-scalar\n:vsadd.vx vd, vs2, rs1^ vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vsaddu.vi vd, vs2, simm5, vm # vector-immediate\n:vsaddu.vi vd, vs2, simm5^ vm is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsaddu.vv vd, vs2, vs1, vm # Vector-vector\n:vsaddu.vv vd, vs2, vs1^ vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsaddu.vx vd, vs2, rs1, vm # vector-scalar\n:vsaddu.vx vd, vs2, rs1^ vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsbc.vvm vd, vs2, vs1, v0 # Vector-vector\n:vsbc.vvm vd, vs2, vs1, v0 is op2631=0x12 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl\n\n# vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar\n:vsbc.vxm vd, vs2, rs1, v0 is op2631=0x12 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl\n\n# vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27\n# vse1024.v vs3, (rs1), vm # 1024-bit unit-stride store\n:vse1024.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27\n# vse128.v vs3, (rs1), vm # 128-bit unit-stride store\n:vse128.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27\n# vse16.v vs3, (rs1), vm # 16-bit unit-stride store\n:vse16.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27\n# vse256.v vs3, (rs1), vm # 256-bit unit-stride store\n:vse256.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27\n# vse32.v vs3, (rs1), vm # 32-bit unit-stride store\n:vse32.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27\n# vse512.v vs3, (rs1), vm # 512-bit unit-stride store\n:vse512.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27\n# vse64.v vs3, (rs1), vm # 64-bit unit-stride store\n:vse64.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27\n# vse8.v vs3, (rs1), vm # 8-bit unit-stride store\n:vse8.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57\n# vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value\n:vsetvl rd, rs1, rs2 is op3131=0x1 & op2530=0x0 & rs2 & rs1 & op1214=0x7 & rd & op0006=0x57 unimpl\n\n#TODO huh\n# vsetvli 31=0 vtypei rs1 14..12=0x7 rd 6..0=0x57\n# vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting\n:vsetvli rd, rs1, vtypei is op3131=0x0 & vtypei & rs1 & op1214=0x7 & rd & op0006=0x57 unimpl\n\n# vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57\n# vsext.vf2 vd, vs2, vm # Sign-extend SEW/2 source to SEW destination\n:vsext.vf2 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57\n# vsext.vf4 vd, vs2, vm # Sign-extend SEW/4 source to SEW destination\n:vsext.vf4 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57\n# vsext.vf8 vd, vs2, vm # Sign-extend SEW/8 source to SEW destination\n:vsext.vf8 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]\n:vslide1down.vx vd, vs2, rs1^ vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i]\n:vslide1up.vx vd, vs2, rs1^ vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vslidedown.vi vd, vs2, simm5[4:0], vm # vd[i] = vs2[i+uimm]\n:vslidedown.vi vd, vs2, simm5[4:0]^ vm is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1]\n:vslidedown.vx vd, vs2, rs1^ vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vslideup.vi vd, vs2, simm5[4:0], vm # vd[i+uimm] = vs2[i]\n:vslideup.vi vd, vs2, simm5[4:0]^ vm is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i]\n:vslideup.vx vd, vs2, rs1^ vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vsll.vi vd, vs2, simm5, vm # vector-immediate\n:vsll.vi vd, vs2, simm5^ vm is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsll.vv vd, vs2, vs1, vm # Vector-vector\n:vsll.vv vd, vs2, vs1^ vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsll.vx vd, vs2, rs1, vm # vector-scalar\n:vsll.vx vd, vs2, rs1^ vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1))\n:vsmul.vv vd, vs2, vs1^ vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))\n:vsmul.vx vd, vs2, rs1^ vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#OTOD this is broken\n# vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vsra.vi vd, vs2, simm5, vm # vector-immediate\n:vsra.vi vd, vs2, simm5^ vm is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsra.vv vd, vs2, vs1, vm # Vector-vector\n:vsra.vv vd, vs2, vs1^ vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsra.vx vd, vs2, rs1, vm # vector-scalar\n:vsra.vx vd, vs2, rs1^ vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vsrl.vi vd, vs2, simm5, vm # vector-immediate\n:vsrl.vi vd, vs2, simm5^ vm is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsrl.vv vd, vs2, vs1, vm # Vector-vector\n:vsrl.vv vd, vs2, vs1^ vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsrl.vx vd, vs2, rs1, vm # vector-scalar\n:vsrl.vx vd, vs2, rs1^ vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27\n# vsse1024.v vs3, (rs1), rs2, vm # 1024-bit strided store\n:vsse1024.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27\n# vsse128.v vs3, (rs1), rs2, vm # 128-bit strided store\n:vsse128.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27\n# vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store\n:vsse16.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27\n# vsse256.v vs3, (rs1), rs2, vm # 256-bit strided store\n:vsse256.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27\n# vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store\n:vsse32.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27\n# vsse512.v vs3, (rs1), rs2, vm # 512-bit strided store\n:vsse512.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27\n# vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store\n:vsse64.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27\n# vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store\n:vsse8.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n#TODO this is broken\n# vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vssra.vi vd, vs2, simm5, vm # vd[i] = roundoff_signed(vs2[i], uimm)\n:vssra.vi vd, vs2, simm5^ vm is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i])\n:vssra.vv vd, vs2, vs1^ vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1])\n:vssra.vx vd, vs2, rs1^ vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n#TODO this is broken\n# vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vssrl.vi vd, vs2, simm5, vm # vd[i] = roundoff_unsigned(vs2[i], uimm)\n:vssrl.vi vd, vs2, simm5^ vm is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i])\n:vssrl.vv vd, vs2, vs1^ vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1])\n:vssrl.vx vd, vs2, rs1^ vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vssub.vv vd, vs2, vs1, vm # Vector-vector\n:vssub.vv vd, vs2, vs1^ vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vssub.vx vd, vs2, rs1, vm # vector-scalar\n:vssub.vx vd, vs2, rs1^ vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vssubu.vv vd, vs2, vs1, vm # Vector-vector\n:vssubu.vv vd, vs2, vs1^ vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vssubu.vx vd, vs2, rs1, vm # vector-scalar\n:vssubu.vx vd, vs2, rs1^ vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vsub.vv vd, vs2, vs1, vm # Vector-vector\n:vsub.vv vd, vs2, vs1^ vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vsub.vx vd, vs2, rs1, vm # vector-scalar\n:vsub.vx vd, vs2, rs1^ vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27\n# vsuxei1024.v vs3, (rs1), vs2, vm # unordered 1024-bit indexed store of SEW data\n:vsuxei1024.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27\n# vsuxei128.v vs3, (rs1), vs2, vm # unordered 128-bit indexed store of SEW data\n:vsuxei128.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27\n# vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data\n:vsuxei16.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27\n# vsuxei256.v vs3, (rs1), vs2, vm # unordered 256-bit indexed store of SEW data\n:vsuxei256.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27\n# vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data\n:vsuxei32.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27\n# vsuxei512.v vs3, (rs1), vs2, vm # unordered 512-bit indexed store of SEW data\n:vsuxei512.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27\n# vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data\n:vsuxei64.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27\n# vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data\n:vsuxei8.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vsxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27\n# vsxei1024.v vs3, (rs1), vs2, vm # ordered 1024-bit indexed store of SEW data\n:vsxei1024.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vsxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27\n# vsxei128.v vs3, (rs1), vs2, vm # ordered 128-bit indexed store of SEW data\n:vsxei128.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vsxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27\n# vsxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data\n:vsxei16.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vsxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27\n# vsxei256.v vs3, (rs1), vs2, vm # ordered 256-bit indexed store of SEW data\n:vsxei256.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl\n\n# vsxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27\n# vsxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data\n:vsxei32.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vsxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27\n# vsxei512.v vs3, (rs1), vs2, vm # ordered 512-bit indexed store of SEW data\n:vsxei512.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl\n\n# vsxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27\n# vsxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data\n:vsxei64.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl\n\n# vsxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27\n# vsxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data\n:vsxei8.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl\n\n# vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwadd.vv vd, vs2, vs1, vm # vector-vector\n:vwadd.vv vd, vs2, vs1^ vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwadd.vx vd, vs2, rs1, vm # vector-scalar\n:vwadd.vx vd, vs2, rs1^ vm is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwadd.wv vd, vs2, vs1, vm # vector-vector\n:vwadd.wv vd, vs2, vs1^ vm is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwadd.wx vd, vs2, rs1, vm # vector-scalar\n:vwadd.wx vd, vs2, rs1^ vm is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwaddu.vv vd, vs2, vs1, vm # vector-vector\n:vwaddu.vv vd, vs2, vs1^ vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwaddu.vx vd, vs2, rs1, vm # vector-scalar\n:vwaddu.vx vd, vs2, rs1^ vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwaddu.wv vd, vs2, vs1, vm # vector-vector\n:vwaddu.wv vd, vs2, vs1^ vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwaddu.wx vd, vs2, rs1, vm # vector-scalar\n:vwaddu.wx vd, vs2, rs1^ vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vwmacc.vv vd, vs1, vs2^ vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]\n:vwmacc.vx vd, rs1, vs2^ vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i]\n:vwmaccsu.vv vd, vs1, vs2^ vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i]\n:vwmaccsu.vx vd, rs1, vs2^ vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]\n:vwmaccu.vv vd, vs1, vs2^ vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]\n:vwmaccu.vx vd, rs1, vs2^ vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]\n:vwmaccus.vx vd, rs1, vs2^ vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwmul.vv vd, vs2, vs1, vm# vector-vector\n:vwmul.vv vd, vs2, vs1^ vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmul.vx vd, vs2, rs1, vm # vector-scalar\n:vwmul.vx vd, vs2, rs1^ vm is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwmulsu.vv vd, vs2, vs1, vm # vector-vector\n:vwmulsu.vv vd, vs2, vs1^ vm is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmulsu.vx vd, vs2, rs1, vm # vector-scalar\n:vwmulsu.vx vd, vs2, rs1^ vm is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwmulu.vv vd, vs2, vs1, vm # vector-vector\n:vwmulu.vv vd, vs2, vs1^ vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwmulu.vx vd, vs2, rs1, vm # vector-scalar\n:vwmulu.vx vd, vs2, rs1^ vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW))\n:vwredsum.vs vd, vs2, vs1^ vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW))\n:vwredsumu.vs vd, vs2, vs1^ vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwsub.vv vd, vs2, vs1, vm # vector-vector\n:vwsub.vv vd, vs2, vs1^ vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwsub.vx vd, vs2, rs1, vm # vector-scalar\n:vwsub.vx vd, vs2, rs1^ vm is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwsub.wv vd, vs2, vs1, vm # vector-vector\n:vwsub.wv vd, vs2, vs1^ vm is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwsub.wx vd, vs2, rs1, vm # vector-scalar\n:vwsub.wx vd, vs2, rs1^ vm is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwsubu.vv vd, vs2, vs1, vm # vector-vector\n:vwsubu.vv vd, vs2, vs1^ vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwsubu.vx vd, vs2, rs1, vm # vector-scalar\n:vwsubu.vx vd, vs2, rs1^ vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57\n# vwsubu.wv vd, vs2, vs1, vm # vector-vector\n:vwsubu.wv vd, vs2, vs1^ vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57\n# vwsubu.wx vd, vs2, rs1, vm # vector-scalar\n:vwsubu.wx vd, vs2, rs1^ vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl\n\n# vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57\n# vxor.vi vd, vs2, simm5, vm # vector-immediate\n:vxor.vi vd, vs2, simm5^ vm is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl\n\n# vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57\n# vxor.vv vd, vs2, vs1, vm # Vector-vector\n:vxor.vv vd, vs2, vs1^ vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl\n\n# vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57\n# vxor.vx vd, vs2, rs1, vm # vector-scalar\n:vxor.vx vd, vs2, rs1^ vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl\n\n# vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57\n# vzext.vf2 vd, vs2, vm # Zero-extend SEW/2 source to SEW destination\n:vzext.vf2 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57\n# vzext.vf4 vd, vs2, vm # Zero-extend SEW/4 source to SEW destination\n:vzext.vf4 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n# vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57\n# vzext.vf8 vd, vs2, vm # Zero-extend SEW/8 source to SEW destination\n:vzext.vf8 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl\n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.table.sinc", "content": "attach variables [ r0711 r1519 r2024 r2731 ]\n \t\t [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5\n\t\t a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];\n\nattach variables [ cd0711NoSp ]\n \t\t [ zero ra _ gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5\n\t\t a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];\t \n\t\t \n\nattach variables [ cr0206 cr0711 cd0711 ]\n \t\t [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5\n\t\t a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];\n\nattach variables [ cr0204s cr0709s cd0709s ]\n \t\t [ s0 s1 a0 a1 a2 a3 a4 a5 ];\n\n\nattach variables [ fr0711 fr1519 fr2024 fr2731 ]\n \t\t [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5\n\t\t fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];\n\nattach variables [ cfr0206 cfr0711 ]\n \t\t [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5\n\t\t fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];\n\nattach variables [ cfr0204s cfr0709s ]\n \t\t [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ];\n\n\nattach variables [ v0711 v1519 v2024 ]\n \t\t [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15\n\t\t v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];\n\n#attach variables [ csr_0 ]\n# [ ustatus fflags frm fcsr uie utvec csr006 csr007\n# vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr\n# csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017\n# csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f\n# csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027\n# csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f\n# csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037\n# csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f\n# uscratch uepc ucause utval uip csr045 csr046 csr047\n# csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f\n# csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057\n# csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f\n# csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067\n# csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f\n# csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077\n# csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f\n# csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087\n# csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f\n# csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097\n# csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f\n# csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7\n# csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af\n# csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7\n# csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf\n# csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7\n# csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf\n# csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7\n# csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df\n# csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7\n# csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef\n# csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7\n# csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ];\n#attach variables [ csr_1 ]\n# [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107\n# csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f\n# csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117\n# csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f\n# csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127\n# csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f\n# csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137\n# csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f\n# sscratch sepc scause stval sip csr145 csr146 csr147\n# csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f\n# csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157\n# csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f\n# csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167\n# csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f\n# csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177\n# csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f\n# satp csr181 csr182 csr183 csr184 csr185 csr186 csr187\n# csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f\n# csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197\n# csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f\n# csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7\n# csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af\n# csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7\n# csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf\n# csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7\n# csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf\n# csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7\n# csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df\n# csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7\n# csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef\n# csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7\n# csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ];\n#attach variables [ csr_2 ]\n# [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207\n# csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f\n# csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217\n# csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f\n# csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227\n# csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f\n# csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237\n# csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f\n# vsscratch vsepc vscause vstval vsip csr245 csr246 csr247\n# csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f\n# csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257\n# csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f\n# csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267\n# csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f\n# csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277\n# csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f\n# vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287\n# csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f\n# csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297\n# csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f\n# csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7\n# csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af\n# csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7\n# csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf\n# csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7\n# csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf\n# csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7\n# csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df\n# csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7\n# csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef\n# csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7\n# csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ];\n#attach variables [ csr_3 ]\n# [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307\n# csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f\n# mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317\n# csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f\n# mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7\n# mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15\n# mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23\n# mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31\n# mscratch mepc mcause mtval mip csr345 csr346 csr347\n# csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f\n# csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357\n# csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f\n# csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367\n# csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f\n# csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377\n# csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f\n# mbase mbound mibase mibound mdbase mdbound csr386 csr387\n# csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f\n# csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397\n# csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f\n# pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7\n# pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15\n# pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7\n# pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15\n# pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23\n# pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31\n# pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39\n# pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47\n# pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55\n# pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63\n# csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7\n# csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ];\n#attach variables [ csr_4 ]\n# [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407\n# csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f\n# csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417\n# csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f\n# csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427\n# csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f\n# csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437\n# csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f\n# csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447\n# csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f\n# csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457\n# csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f\n# csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467\n# csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f\n# csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477\n# csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f\n# csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487\n# csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f\n# csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497\n# csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f\n# csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7\n# csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af\n# csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7\n# csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf\n# csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7\n# csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf\n# csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7\n# csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df\n# csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7\n# csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef\n# csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7\n# csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ];\n#attach variables [ csr_50 ]\n# [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507\n# csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f\n# csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517\n# csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f\n# csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527\n# csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f\n# csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537\n# csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f\n# csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547\n# csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f\n# csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557\n# csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f\n# csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567\n# csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f\n# csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577\n# csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ];\n#attach variables [ csr_58 ]\n# [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587\n# csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f\n# csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597\n# csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f\n# csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7\n# scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af\n# csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7\n# csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ];\n#attach variables [ csr_5C ]\n# [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7\n# csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf\n# csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7\n# csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df\n# csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7\n# csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef\n# csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7\n# csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ];\n#attach variables [ csr_60 ]\n# [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie\n# csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f\n# csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617\n# csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f\n# csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627\n# csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f\n# csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637\n# csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f\n# csr640 csr641 csr642 htval hip hvip csr646 csr647\n# csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f\n# csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657\n# csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f\n# csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667\n# csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f\n# csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677\n# csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ];\n#attach variables [ csr_68 ]\n# [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687\n# csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f\n# csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697\n# csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f\n# csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7\n# hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af\n# csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7\n# csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ];\n#attach variables [ csr_6C ]\n# [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7\n# csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf\n# csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7\n# csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df\n# csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7\n# csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef\n# csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7\n# csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ];\n#attach variables [ csr_70 ]\n# [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707\n# csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f\n# csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717\n# csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f\n# csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727\n# csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f\n# csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737\n# csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f\n# csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747\n# csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f\n# csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757\n# csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f\n# csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767\n# csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f\n# csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777\n# csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ];\n#attach variables [ csr_78 ]\n# [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787\n# csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f\n# csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797\n# csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ];\n#attach variables [ csr_7A ]\n# [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7\n# mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ];\n#attach variables [ csr_7B ]\n# [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7\n# csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ];\n#attach variables [ csr_7C ]\n# [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7\n# csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf\n# csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7\n# csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df\n# csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7\n# csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef\n# csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7\n# csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ];\n#attach variables [ csr_8 ]\n# [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807\n# csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f\n# csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817\n# csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f\n# csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827\n# csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f\n# csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837\n# csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f\n# csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847\n# csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f\n# csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857\n# csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f\n# csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867\n# csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f\n# csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877\n# csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f\n# csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887\n# csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f\n# csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897\n# csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f\n# csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7\n# csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af\n# csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7\n# csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf\n# csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7\n# csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf\n# csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7\n# csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df\n# csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7\n# csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef\n# csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7\n# csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ];\n#attach variables [ csr_90 ]\n# [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907\n# csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f\n# csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917\n# csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f\n# csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927\n# csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f\n# csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937\n# csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f\n# csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947\n# csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f\n# csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957\n# csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f\n# csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967\n# csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f\n# csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977\n# csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ];\n#attach variables [ csr_98 ]\n# [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987\n# csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f\n# csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997\n# csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f\n# csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7\n# csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af\n# csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7\n# csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ];\n#attach variables [ csr_9C ]\n# [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7\n# csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf\n# csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7\n# csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df\n# csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7\n# csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef\n# csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7\n# csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ];\n#attach variables [ csr_A0 ]\n# [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07\n# csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f\n# csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17\n# csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f\n# csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27\n# csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f\n# csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37\n# csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f\n# csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47\n# csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f\n# csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57\n# csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f\n# csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67\n# csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f\n# csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77\n# csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ];\n#attach variables [ csr_A8 ]\n# [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87\n# csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f\n# csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97\n# csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f\n# csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7\n# csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf\n# csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7\n# csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ];\n#attach variables [ csr_AC ]\n# [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7\n# csrac8 csrac9 csraca csracb csracc csracd csrace csracf\n# csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7\n# csrad8 csrad9 csrada csradb csradc csradd csrade csradf\n# csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7\n# csrae8 csrae9 csraea csraeb csraec csraed csraee csraef\n# csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7\n# csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ];\n#attach variables [ csr_B0 ]\n# [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7\n# mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15\n# mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23\n# mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31\n# csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27\n#\t\t csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f\n#\t\t csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37\n#\t\t csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f\n# csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47\n# csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f\n# csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57\n# csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f\n# csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67\n# csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f\n# csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77\n# csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ];\n#attach variables [ csr_B8 ]\n# [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h\n# mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h\n# mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h\n# mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h\n# csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7\n# csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf\n# csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7\n# csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ];\n#attach variables [ csr_BC ]\n# [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7\n# csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf\n# csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7\n# csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf\n# csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7\n# csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef\n# csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7\n# csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ];\n#attach variables [ csr_C0 ]\n# [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7\n# hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15\n# hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23\n# hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31\n# vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27\n# csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f\n# csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37\n# csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f\n# csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47\n# csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f\n# csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57\n# csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f\n# csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67\n# csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f\n# csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77\n# csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ];\n#attach variables [ csr_C8 ]\n# [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h\n# hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h\n# hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h\n# hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h\n# csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7\n# csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf\n# csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7\n# csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ];\n#attach variables [ csr_CC ]\n# [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7\n# csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf\n# csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7\n# csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf\n# csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7\n# csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef\n# csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7\n# csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ];\n#attach variables [ csr_D0 ]\n# [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07\n# csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f\n# csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17\n# csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f\n# csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27\n# csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f\n# csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37\n# csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f\n# csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47\n# csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f\n# csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57\n# csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f\n# csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67\n# csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f\n# csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77\n# csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ];\n#attach variables [ csr_D8 ]\n# [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87\n# csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f\n# csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97\n# csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f\n# csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7\n# csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf\n# csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7\n# csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ];\n#attach variables [ csr_DC ]\n# [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7\n# csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf\n# csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7\n# csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf\n# csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7\n# csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef\n# csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7\n# csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ];\n#attach variables [ csr_E0 ]\n# [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07\n# csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f\n# csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17\n# csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f\n# csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27\n# csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f\n# csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37\n# csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f\n# csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47\n# csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f\n# csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57\n# csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f\n# csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67\n# csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f\n# csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77\n# csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ];\n#attach variables [ csr_E8 ]\n# [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87\n# csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f\n# csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97\n# csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f\n# csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7\n# csrea8 csrea9 csreaa csreab csreac csread csreae csreaf\n# csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7\n# csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ];\n#attach variables [ csr_EC ]\n# [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7\n# csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf\n# csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7\n# csred8 csred9 csreda csredb csredc csredd csrede csredf\n# csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7\n# csree8 csree9 csreea csreeb csreec csreed csreee csreef\n# csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7\n# csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ];\n#attach variables [ csr_F0 ]\n# [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07\n# csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f\n# csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17\n# csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f\n# csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27\n# csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f\n# csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37\n# csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f\n# csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47\n# csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f\n# csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57\n# csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f\n# csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67\n# csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f\n# csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77\n# csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ];\n#attach variables [ csr_F8 ]\n# [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87\n# csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f\n# csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97\n# csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f\n# csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7\n# csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf\n# csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7\n# csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ];\n#attach variables [ csr_FC ]\n# [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7\n# csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf\n# csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7\n# csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf\n# csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7\n# csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef\n# csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7\n# csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ];\n\n\n#TODO these names are madeup. do real ones exist?\n#TODO go through and use these instead of numbers\n@define HFLEN 2\n@define SFLEN 4\n@define DFLEN 8\n@define QFLEN 16\n\n@define HXLEN 2\n@define WXLEN 4\n@define DXLEN 8\n@define QXLEN 16\n\n\ndefine pcodeop unimp;\ndefine pcodeop trap;\ndefine pcodeop ebreak;\ndefine pcodeop ecall;\ndefine pcodeop fence;\ndefine pcodeop fence.i;\n\n\n# possible tokens: r0711 r1519 r2024 r2731 cr0206 cr0711 cd0711\nrs1: r1519 is r1519 { export r1519; }\nrs1: zero is zero & op1519=0 { export 0:$(XLEN); }\n\nrs2: r2024 is r2024 { export r2024; }\nrs2: zero is zero & op2024=0 { export 0:$(XLEN); }\n\nrs3: r2731 is r2731 { export r2731; }\nrs3: zero is zero & op2731=0 { export 0:$(XLEN); }\n\nrd: r0711 is r0711 { export r0711; }\nrd: zero is r0711 & zero & op0711=0 { local tempZero:$(XLEN) = 0; export tempZero; }\nrdDst: r0711 is r0711 { export r0711; }\n\n\nrs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; }\nrs1W: zero is r1519 & zero & op1519=0 { export 0:$(WXLEN); }\n\nrs2W: r2024 is r2024 { local tmp:$(WXLEN) = r2024:$(WXLEN); export tmp; }\nrs2W: zero is r2024 & zero & op2024=0 { export 0:$(WXLEN); }\n\n#TODO dest may be bad, might need an assign macro\nrdW: r0711 is r0711 { local tmp:$(WXLEN) = r0711:$(WXLEN); export tmp; }\nrdW: zero is r0711 & zero & op0711=0 { export 0:$(WXLEN); }\n\n\n\n#TODO does this need to be in an if/endif\n@if ADDRSIZE == \"64\"\nrs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; }\nrs1L: zero is r1519 & zero & op1519=0 { export 0:8; }\n\nrs2L: r2024 is r2024 { local tmp:8 = r2024:8; export tmp; }\nrs2L: zero is r2024 & zero & op2024=0 { export 0:8; }\n\n#TODO dest may be bad, might need an assign macro\nrdL: r0711 is r0711 { export r0711; }\nrdL: zero is r0711 & zero & op0711=0 { export 0:8; }\n@endif\n\n\n#TODO eh not sure if this is usable\n# would only make sense to use this if the float operation\n# tables for frd,frs1,frs2 could be different sizes or\n# if the cast could use this export, but they have to export\n# the same size and you cant 'local tmp:fmt'\n# # 32-bit single-precision $(SFLEN)\n# fmt: \".s\" is op2526=0 { export $(SFLEN):1; }\n# # 64-bit double-precision $(DFLEN)\n# fmt: \".d\" is op2526=1 { export $(DFLEN):1; }\n# # 16-bit half-precision $(HFLEN)\n# fmt: \".h\" is op2526=2 { export $(HFLEN):1; }\n# # 128-bit quad-precision $(QFLEN)\n# fmt: \".q\" is op2526=3 { export $(QFLEN):1; }\n\n\nfrd: fr0711 is fr0711 { export fr0711; }\nfrs1: fr1519 is fr1519 { export fr1519; }\nfrs2: fr2024 is fr2024 { export fr2024; }\nfrs3: fr2731 is fr2731 { export fr2731; }\n\n#TODO dest may be bad, might need an assign macro\n#frdS: fr0711 is fr0711 { local tmp = fr0711:$(SFLEN); export tmp; }\nfrs1S: fr1519 is fr1519 { local tmp = fr1519:$(SFLEN); export tmp; }\nfrs2S: fr2024 is fr2024 { local tmp = fr2024:$(SFLEN); export tmp; }\nfrs3S: fr2731 is fr2731 { local tmp = fr2731:$(SFLEN); export tmp; }\n\n@if ((FPSIZE == \"64\") || (FPSIZE == \"128\"))\n#TODO dest may be bad, might need an assign macro\n#frdD: fr0711 is fr0711 { local tmp = fr0711:$(DFLEN); export tmp; }\nfrs1D: fr1519 is fr1519 { local tmp = fr1519:$(DFLEN); export tmp; }\nfrs2D: fr2024 is fr2024 { local tmp = fr2024:$(DFLEN); export tmp; }\nfrs3D: fr2731 is fr2731 { local tmp = fr2731:$(DFLEN); export tmp; }\n@endif\n\nmacro fassignS(dest, src) {\n@if FPSIZE == \"32\"\n\tdest = src;\n@else\n\tdest = zext(src);\n@endif\n}\n\n\nmacro assignW(dest, src) {\n@if ADDRSIZE == \"32\"\n\tdest = src;\n@else\n\tdest = sext(src);\n@endif\n}\n\nmacro zassignW(dest, src) {\n@if ADDRSIZE == \"32\"\n\tdest = src;\n@else\n\tdest = zext(src);\n@endif\n}\n\nmacro zassignD(dest, src) {\n@if ADDRSIZE == \"128\"\n\tdest = zext(src);\n@else\n\tdest = src;\n@endif\n}\n\nmacro assignD(dest, src) {\n@if ADDRSIZE == \"128\"\n\tdest = sext(src);\n@else\n\tdest = src;\n@endif\n}\n\n\nimmI: sop2031 is sop2031 { local tmp:$(XLEN) = sop2031; export tmp; }\n\nimmS: imm is op0711 & sop2531 [ imm = (sop2531 << 5) | op0711; ] { local tmp:$(XLEN) = imm; export tmp; }\n\n# used for goto\nimmSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export *[ram]:$(XLEN) reloc; }\n#immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export reloc; }\n\nimmU: op1231 is op1231 & sop1231 { local tmp:$(XLEN) = sop1231 << 12; export tmp; }\n\n# used for goto\nimmUJ: reloc is op1219 & op2020 & op2130 & sop3131 [ reloc = inst_start + ((sop3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12)); ] { export *[ram]:$(XLEN) reloc; }\n\n@if ADDRSIZE == \"32\"\nshamt6: op2024 is op2024 & op2525=0 { local tmp:$(XLEN) = op2024; export tmp; }\n@else\nshamt5: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; }\nshamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:$(XLEN) = imm; export tmp; }\n@endif\n\nFRM: \"rne\" is op1214=0 { local tmp:1 = 0; export tmp; }\nFRM: \"rtz\" is op1214=1 { local tmp:1 = 1; export tmp; }\nFRM: \"rdn\" is op1214=2 { local tmp:1 = 2; export tmp; }\nFRM: \"rup\" is op1214=3 { local tmp:1 = 3; export tmp; }\nFRM: \"rmm\" is op1214=4 { local tmp:1 = 4; export tmp; }\n# 5 Invalid. Reserved for future use\n# 6 Invalid. Reserved for future use\nFRM: \"dyn\" is op1214=7 { local tmp:1 = 7; export tmp; }\n\n# used to specify additional memory ordering constraints\naqrl: \"\" is op2526=0 { export 0:$(XLEN); }\naqrl: \".rl\" is op2526=1 { export 1:$(XLEN); }\naqrl: \".aq\" is op2526=2 { export 2:$(XLEN); }\naqrl: \".aqrl\" is op2526=3 { export 3:$(XLEN); }\n\n\n\ncrs1: cr0711 is cr0711 { export cr0711; }\ncrs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); }\n\ncrdNoSp: cd0711NoSp is cd0711NoSp { export cd0711NoSp; }\ncrdNoSp: zero is zero & cop0711=0 { export 0:$(XLEN); }\n\ncrd: cd0711 is cd0711 { export cd0711; }\ncrd: zero is zero & cop0711=0 { export 0:$(XLEN); }\n\ncrs2: cr0206 is cr0206 { export cr0206; }\ncrs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); }\n\ncfrs1: cfr0711 is cfr0711 { export cfr0711; }\n\ncfrd: cfr0711 is cfr0711 { export cfr0711; }\n\ncfrs2: cfr0206 is cfr0206 { export cfr0206; }\n\n#ATTN Not doing tables for the RVC registers since there is no\n# zero register to worry about\n\n\n\ncimmI: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; }\n\n# used for goto\ncbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export *[ram]:$(XLEN) reloc; }\n#cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export reloc; }\n\n# used for goto\ncjimm: reloc is scop1212 & cop1111 & cop0910 & cop0808 & cop0707 & cop0606 & cop0305 & cop0202 [ reloc = inst_start + ((scop1212 << 11) | (cop1111 << 4) | (cop0910 << 8) | (cop0808 << 10) | (cop0707 << 6) | (cop0606 << 7) | (cop0305 << 1) | (cop0202 << 5)); ] { export *[ram]:$(XLEN) reloc; }\n\n\nnzuimm5: is cop0606=1 | cop0505=1 | cop0404=1 | cop0303 = 1 | cop0202=1 {}\nnzuimm6: is cop1212=1 | cop0606=1 | cop0505=1 | cop0404=1 | cop0303 = 1 | cop0202=1 {}\n\n@if ADDRSIZE == \"32\"\nc6imm: uimm is cop1212=0 & cop0206 & nzuimm5 [ uimm = (cop0206 + 0); ] { local tmp:$(XLEN) = uimm; export tmp; }\n@elif ADDRSIZE == \"64\"\nc6imm: uimm is cop1212 & cop0206 & nzuimm6 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm; export tmp; }\n@elif ADDRSIZE == \"128\"\nc6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm + (64 * (uimm == 0)); export tmp; }\n@endif\n\ncbigimm: uimm is cop1212 & scop1212 & cop0206 & nzuimm6 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = (scop1212 << 17) | (cop0206 << 12); export tmp; }\n\nnzcaddi4: is cop1212=1 | cop1111=1 | cop1010=1 | cop0909=1 | cop0808=1 | cop0707=1 | cop0606=1 | cop0505=1 {}\n\ncaddi4spnimm: uimm is nzcaddi4 & cop1112 & cop0710 & cop0606 & cop0505 [ uimm = (cop0710 << 6) | (cop1112 << 4) | (cop0505 << 3) | (cop0606 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\ncaddi16spimm: imm is scop1212 & cop0606 & cop0505 & cop0304 & cop0202 & nzuimm6 [ imm = (scop1212 << 9) | (cop0304 << 7) | (cop0505 << 6) | (cop0202 << 5) | (cop0606 << 4); ] { local tmp:$(XLEN) = imm; export tmp; }\n\n\nclwimm: uimm is cop1012 & cop0606 & cop0505 [ uimm = (cop1012 << 3) | (cop0606 << 2) | (cop0505 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\nclwspimm: uimm is cop1212 & cop0406 & cop0203 [ uimm = (cop1212 << 5) | (cop0406 << 2) | (cop0203 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\ncswspimm: uimm is cop0708 & cop0912 [ uimm = (cop0708 << 6) | (cop0912 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\ncldimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\ncldspimm: uimm is cop1212 & cop0506 & cop0204 [ uimm = (cop1212 << 5) | (cop0506 << 3) | (cop0204 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\ncsdspimm: uimm is cop0709 & cop1012 [ uimm = (cop0709 << 6) | (cop1012 << 3); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\n@if ADDRSIZE == \"128\"\nclqimm: uimm is cop1112 & cop1010 & cop0506 [ uimm = (cop1112 << 4) | (cop1010 << 8) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\nclqspimm: uimm is cop1212 & cop0606 & cop0205 [ uimm = (cop1212 << 5) | (cop0606 << 4) | (cop0205 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }\n\ncsqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ] { local tmp:$(XLEN) = uimm; export tmp; }\n@endif\n\n\n\n\n\n# SEE riscv-privileged.pdf Section 'CSR Listing' for description\n# This implementation aligns with the table breakdown\n\n# csr[11:10] - read/write (00, 01, 10) or read-only (11)\n# csr[9:8] - lowest privilege that can access the CSR\n\n## 0x000-0x0ff\n#with csr: op3031=0 & op2829=0 {\n#\t: csr_0 is csr_0 { export csr_0; } # user, standard read/write\n#}\n#\n## 0x100-0x1ff\n#with csr: op3031=0 & op2829=1 {\n#\t: csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write\n#}\n#\n## 0x200-0x2ff\n#with csr: op3031=0 & op2829=2 {\n#\t: csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write\n#}\n#\n## 0x300-0x3ff\n#with csr: op3031=0 & op2829=3 {\n#\t: csr_3 is csr_3 { export csr_3; } # machine, standard read/write\n#}\n#\n## 0x400-0x4ff\n#with csr: op3031=1 & op2829=0 {\n#\t: csr_4 is csr_4 { export csr_4; } # user, standard read/write\n#}\n#\n## 0x500-0x5ff\n#with csr: op3031=1 & op2829=1 {\n#\t: csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write\n#\t: csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write\n#\t: csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write\n#}\n#\n## 0x600-0x6ff\n#with csr: op3031=1 & op2829=2 {\n#\t: csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write\n#\t: csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write\n#\t: csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write\n#}\n#\n## 0x700-0x7ff\n#with csr: op3031=1 & op2829=3 {\n#\t: csr_70 is csr_70 & op2727=0 { export csr_70; } # machine, standard read/write\n#\t: csr_78 is csr_78 & op2527=4 { export csr_78; } # machine, standard read/write\n#\t: csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug\n#\t: csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only\n#\t: csr_7C is csr_7C & op2627=3 { export csr_7C; } # machine, custom read/write\n#}\n#\n## 0x800-0x8ff\n#with csr: op3031=2 & op2829=0 {\n#\t: csr_8 is csr_8 { export csr_8; } # user, custom read/write\n#}\n#\n## 0x900-0x9ff\n#with csr: op3031=2 & op2829=1 {\n#\t: csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write\n#\t: csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write\n#\t: csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write\n#}\n#\n## 0xa00-0xaff\n#with csr: op3031=2 & op2829=2 {\n#\t: csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write\n#\t: csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write\n#\t: csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write\n#}\n#\n## 0xb00-0xbff\n#with csr: op3031=2 & op2829=3 {\n#\t: csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write\n#\t: csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write\n#\t: csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write\n#}\n#\n## 0xc00-0xcff\n#with csr: op3031=3 & op2829=0 {\n#\t: csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only\n#\t: csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only\n#\t: csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only\n#}\n#\n## 0xd00-0xdff\n#with csr: op3031=3 & op2829=1 {\n#\t: csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only\n#\t: csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only\n#\t: csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only\n#}\n#\n## 0xe00-0xeff\n#with csr: op3031=3 & op2829=2 {\n#\t: csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only\n#\t: csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only\n#\t: csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only\n#}\n#\n## 0xf00-0xfff\n#with csr: op3031=3 & op2829=3 {\n#\t: csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only\n#\t: csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only\n#\t: csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only\n#}\n#\n\ncsr: csr_reg is op2031 [ csr_reg = $(CSR_REG_START) + op2031; ] { export *[csreg]:$(XLEN) csr_reg; }\n\n\nvs1: v1519 is v1519 { export v1519; }\nvs2: v2024 is v2024 { export v2024; }\nvs3: v0711 is v0711 { export v0711; }\nvd: v0711 is v0711 { export v0711; }\n\nvm: ,v0^\".t\" is op2525=0 & v0 & vd { vd = vd & v0; }\nvm: \"\" is op2525=1 { }\n\nsimm5: sop1519 is sop1519 { local tmp:$(XLEN) = sop1519; export tmp; }\n# zimm: op1519 is op1519 { local tmp:$(XLEN) = op1519; export tmp; }\n\nnf: op2931 is op2931 { local tmp:$(XLEN) = op2931; export tmp; }\n\nvtypei: op2030 is op2030 { local tmp:$(XLEN) = op2030; export tmp; }\n\n\nbs: op3031 is op3031 { local tmp:$(XLEN) = op3031; export tmp; }\nrcon: op2023 is op2023 { local tmp:$(XLEN) = op2023; export tmp; }\n\n# imm=0 for baseline operation, nonzero values are reserved\nshamtw: 0 is op2024=0 { local tmp:$(XLEN) = 0; export tmp; }\n\nimm3u: op2022 is op2022 { local tmp:$(XLEN) = op2022; export tmp; }\nimm4u: op2023 is op2023 { local tmp:$(XLEN) = op2023; export tmp; }\nimm5u: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; }\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv.zi.sinc", "content": "# RV32/RV64 Zifencei Standard Extension\n\n# fence.i 0000100f ffffffff SIMPLE (0, 0) \n:fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0\n{\n\tfence.i();\n}\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv32-fp.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n \n\t \n\t \n \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv32.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv32.dwarf", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv64-fp.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n \n\t \n\t \n \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\n \n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv64.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n \n\t \n\t \n\t \n \n \n \n \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/RISCV/data/languages/riscv64.dwarf", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n" }, { "path": "pypcode/processors/RISCV/data/patterns/patternconstraints.xml", "content": "\n \n riscv_gc_patterns.xml\n \n\n" }, { "path": "pypcode/processors/RISCV/data/patterns/riscv_gc_patterns.xml", "content": "\n\n \n \n \n 10000010 10000000 \n 10000010 10000000 00000000 00000000 \n \n \n 0.....01 01110001 \n 0.....01 00010001 \n 00010011 00000001 ....0001 1....... \n \n \n \n \n \n \n \n 01101111 ....0000 ........ ........ \n ......01 101..... \n ......01 101..... 00000000 00000000 \n \n \n 0.....01 01110001 \n 0.....01 00010001 \n 00010011 00000001 ....0001 1....... \n \n \n \n \n \n \n \n 10000010 10000000 \n 10000010 10000000 00000000 00000000 \n ......01 101..... 00000000 00000000 \n 01101111 ....0000 ........ ........ \n \n \n .0010111 ........ ........ ........ \n \n \n \n" }, { "path": "pypcode/processors/RISCV/scripts/binutil.py", "content": "#!/usr/bin/env python3\n## ###\n# IP: GHIDRA\n# \n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n# \n# http://www.apache.org/licenses/LICENSE-2.0\n# \n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n##\n\"\"\"Script to generate base RISC-V SLEIGH for Ghidra module\n\nJust an artifact to keep around for the development at this point as a lot of\ncleanup and reorganization was done after generating the intial SLEIGH.\n\nData was copied from various files in binutils, a lot of it unused.\n\"\"\"\n\n\nMATCH_SLLI_RV32=0x1013\nMASK_SLLI_RV32=0xfe00707f\nMATCH_SRLI_RV32=0x5013\nMASK_SRLI_RV32=0xfe00707f\nMATCH_SRAI_RV32=0x40005013\nMASK_SRAI_RV32=0xfe00707f\nMATCH_FRFLAGS=0x102073\nMASK_FRFLAGS=0xfffff07f\nMATCH_FSFLAGS=0x101073\nMASK_FSFLAGS=0xfff0707f\nMATCH_FSFLAGSI=0x105073\nMASK_FSFLAGSI=0xfff0707f\nMATCH_FRRM=0x202073\nMASK_FRRM=0xfffff07f\nMATCH_FSRM=0x201073\nMASK_FSRM=0xfff0707f\nMATCH_FSRMI=0x205073\nMASK_FSRMI=0xfff0707f\nMATCH_FSCSR=0x301073\nMASK_FSCSR=0xfff0707f\nMATCH_FRCSR=0x302073\nMASK_FRCSR=0xfffff07f\nMATCH_RDCYCLE=0xc0002073\nMASK_RDCYCLE=0xfffff07f\nMATCH_RDTIME=0xc0102073\nMASK_RDTIME=0xfffff07f\nMATCH_RDINSTRET=0xc0202073\nMASK_RDINSTRET=0xfffff07f\nMATCH_RDCYCLEH=0xc8002073\nMASK_RDCYCLEH=0xfffff07f\nMATCH_RDTIMEH=0xc8102073\nMASK_RDTIMEH=0xfffff07f\nMATCH_RDINSTRETH=0xc8202073\nMASK_RDINSTRETH=0xfffff07f\nMATCH_SCALL=0x73\nMASK_SCALL=0xffffffff\nMATCH_SBREAK=0x100073\nMASK_SBREAK=0xffffffff\nMATCH_BEQ=0x63\nMASK_BEQ=0x707f\nMATCH_BNE=0x1063\nMASK_BNE=0x707f\nMATCH_BLT=0x4063\nMASK_BLT=0x707f\nMATCH_BGE=0x5063\nMASK_BGE=0x707f\nMATCH_BLTU=0x6063\nMASK_BLTU=0x707f\nMATCH_BGEU=0x7063\nMASK_BGEU=0x707f\nMATCH_JALR=0x67\nMASK_JALR=0x707f\nMATCH_JAL=0x6f\nMASK_JAL=0x7f\nMATCH_LUI=0x37\nMASK_LUI=0x7f\nMATCH_AUIPC=0x17\nMASK_AUIPC=0x7f\nMATCH_ADDI=0x13\nMASK_ADDI=0x707f\nMATCH_SLLI=0x1013\nMASK_SLLI=0xfc00707f\nMATCH_SLTI=0x2013\nMASK_SLTI=0x707f\nMATCH_SLTIU=0x3013\nMASK_SLTIU=0x707f\nMATCH_XORI=0x4013\nMASK_XORI=0x707f\nMATCH_SRLI=0x5013\nMASK_SRLI=0xfc00707f\nMATCH_SRAI=0x40005013\nMASK_SRAI=0xfc00707f\nMATCH_ORI=0x6013\nMASK_ORI=0x707f\nMATCH_ANDI=0x7013\nMASK_ANDI=0x707f\nMATCH_ADD=0x33\nMASK_ADD=0xfe00707f\nMATCH_SUB=0x40000033\nMASK_SUB=0xfe00707f\nMATCH_SLL=0x1033\nMASK_SLL=0xfe00707f\nMATCH_SLT=0x2033\nMASK_SLT=0xfe00707f\nMATCH_SLTU=0x3033\nMASK_SLTU=0xfe00707f\nMATCH_XOR=0x4033\nMASK_XOR=0xfe00707f\nMATCH_SRL=0x5033\nMASK_SRL=0xfe00707f\nMATCH_SRA=0x40005033\nMASK_SRA=0xfe00707f\nMATCH_OR=0x6033\nMASK_OR=0xfe00707f\nMATCH_AND=0x7033\nMASK_AND=0xfe00707f\nMATCH_ADDIW=0x1b\nMASK_ADDIW=0x707f\nMATCH_SLLIW=0x101b\nMASK_SLLIW=0xfe00707f\nMATCH_SRLIW=0x501b\nMASK_SRLIW=0xfe00707f\nMATCH_SRAIW=0x4000501b\nMASK_SRAIW=0xfe00707f\nMATCH_ADDW=0x3b\nMASK_ADDW=0xfe00707f\nMATCH_SUBW=0x4000003b\nMASK_SUBW=0xfe00707f\nMATCH_SLLW=0x103b\nMASK_SLLW=0xfe00707f\nMATCH_SRLW=0x503b\nMASK_SRLW=0xfe00707f\nMATCH_SRAW=0x4000503b\nMASK_SRAW=0xfe00707f\nMATCH_LB=0x3\nMASK_LB=0x707f\nMATCH_LH=0x1003\nMASK_LH=0x707f\nMATCH_LW=0x2003\nMASK_LW=0x707f\nMATCH_LD=0x3003\nMASK_LD=0x707f\nMATCH_LBU=0x4003\nMASK_LBU=0x707f\nMATCH_LHU=0x5003\nMASK_LHU=0x707f\nMATCH_LWU=0x6003\nMASK_LWU=0x707f\nMATCH_SB=0x23\nMASK_SB=0x707f\nMATCH_SH=0x1023\nMASK_SH=0x707f\nMATCH_SW=0x2023\nMASK_SW=0x707f\nMATCH_SD=0x3023\nMASK_SD=0x707f\nMATCH_FENCE=0xf\nMASK_FENCE=0x707f\nMATCH_FENCE_I=0x100f\nMASK_FENCE_I=0x707f\nMATCH_FENCE_TSO=0x8330000f\nMASK_FENCE_TSO=0xfff0707f\nMATCH_MUL=0x2000033\nMASK_MUL=0xfe00707f\nMATCH_MULH=0x2001033\nMASK_MULH=0xfe00707f\nMATCH_MULHSU=0x2002033\nMASK_MULHSU=0xfe00707f\nMATCH_MULHU=0x2003033\nMASK_MULHU=0xfe00707f\nMATCH_DIV=0x2004033\nMASK_DIV=0xfe00707f\nMATCH_DIVU=0x2005033\nMASK_DIVU=0xfe00707f\nMATCH_REM=0x2006033\nMASK_REM=0xfe00707f\nMATCH_REMU=0x2007033\nMASK_REMU=0xfe00707f\nMATCH_MULW=0x200003b\nMASK_MULW=0xfe00707f\nMATCH_DIVW=0x200403b\nMASK_DIVW=0xfe00707f\nMATCH_DIVUW=0x200503b\nMASK_DIVUW=0xfe00707f\nMATCH_REMW=0x200603b\nMASK_REMW=0xfe00707f\nMATCH_REMUW=0x200703b\nMASK_REMUW=0xfe00707f\nMATCH_AMOADD_W=0x202f\nMASK_AMOADD_W=0xf800707f\nMATCH_AMOXOR_W=0x2000202f\nMASK_AMOXOR_W=0xf800707f\nMATCH_AMOOR_W=0x4000202f\nMASK_AMOOR_W=0xf800707f\nMATCH_AMOAND_W=0x6000202f\nMASK_AMOAND_W=0xf800707f\nMATCH_AMOMIN_W=0x8000202f\nMASK_AMOMIN_W=0xf800707f\nMATCH_AMOMAX_W=0xa000202f\nMASK_AMOMAX_W=0xf800707f\nMATCH_AMOMINU_W=0xc000202f\nMASK_AMOMINU_W=0xf800707f\nMATCH_AMOMAXU_W=0xe000202f\nMASK_AMOMAXU_W=0xf800707f\nMATCH_AMOSWAP_W=0x800202f\nMASK_AMOSWAP_W=0xf800707f\nMATCH_LR_W=0x1000202f\nMASK_LR_W=0xf9f0707f\nMATCH_SC_W=0x1800202f\nMASK_SC_W=0xf800707f\nMATCH_AMOADD_D=0x302f\nMASK_AMOADD_D=0xf800707f\nMATCH_AMOXOR_D=0x2000302f\nMASK_AMOXOR_D=0xf800707f\nMATCH_AMOOR_D=0x4000302f\nMASK_AMOOR_D=0xf800707f\nMATCH_AMOAND_D=0x6000302f\nMASK_AMOAND_D=0xf800707f\nMATCH_AMOMIN_D=0x8000302f\nMASK_AMOMIN_D=0xf800707f\nMATCH_AMOMAX_D=0xa000302f\nMASK_AMOMAX_D=0xf800707f\nMATCH_AMOMINU_D=0xc000302f\nMASK_AMOMINU_D=0xf800707f\nMATCH_AMOMAXU_D=0xe000302f\nMASK_AMOMAXU_D=0xf800707f\nMATCH_AMOSWAP_D=0x800302f\nMASK_AMOSWAP_D=0xf800707f\nMATCH_LR_D=0x1000302f\nMASK_LR_D=0xf9f0707f\nMATCH_SC_D=0x1800302f\nMASK_SC_D=0xf800707f\nMATCH_ECALL=0x73\nMASK_ECALL=0xffffffff\nMATCH_EBREAK=0x100073\nMASK_EBREAK=0xffffffff\nMATCH_URET=0x200073\nMASK_URET=0xffffffff\nMATCH_SRET=0x10200073\nMASK_SRET=0xffffffff\nMATCH_HRET=0x20200073\nMASK_HRET=0xffffffff\nMATCH_MRET=0x30200073\nMASK_MRET=0xffffffff\nMATCH_DRET=0x7b200073\nMASK_DRET=0xffffffff\nMATCH_SFENCE_VM=0x10400073\nMASK_SFENCE_VM=0xfff07fff\nMATCH_SFENCE_VMA=0x12000073\nMASK_SFENCE_VMA=0xfe007fff\nMATCH_WFI=0x10500073\nMASK_WFI=0xffffffff\nMATCH_CSRRW=0x1073\nMASK_CSRRW=0x707f\nMATCH_CSRRS=0x2073\nMASK_CSRRS=0x707f\nMATCH_CSRRC=0x3073\nMASK_CSRRC=0x707f\nMATCH_CSRRWI=0x5073\nMASK_CSRRWI=0x707f\nMATCH_CSRRSI=0x6073\nMASK_CSRRSI=0x707f\nMATCH_CSRRCI=0x7073\nMASK_CSRRCI=0x707f\nMATCH_FADD_S=0x53\nMASK_FADD_S=0xfe00007f\nMATCH_FSUB_S=0x8000053\nMASK_FSUB_S=0xfe00007f\nMATCH_FMUL_S=0x10000053\nMASK_FMUL_S=0xfe00007f\nMATCH_FDIV_S=0x18000053\nMASK_FDIV_S=0xfe00007f\nMATCH_FSGNJ_S=0x20000053\nMASK_FSGNJ_S=0xfe00707f\nMATCH_FSGNJN_S=0x20001053\nMASK_FSGNJN_S=0xfe00707f\nMATCH_FSGNJX_S=0x20002053\nMASK_FSGNJX_S=0xfe00707f\nMATCH_FMIN_S=0x28000053\nMASK_FMIN_S=0xfe00707f\nMATCH_FMAX_S=0x28001053\nMASK_FMAX_S=0xfe00707f\nMATCH_FSQRT_S=0x58000053\nMASK_FSQRT_S=0xfff0007f\nMATCH_FADD_D=0x2000053\nMASK_FADD_D=0xfe00007f\nMATCH_FSUB_D=0xa000053\nMASK_FSUB_D=0xfe00007f\nMATCH_FMUL_D=0x12000053\nMASK_FMUL_D=0xfe00007f\nMATCH_FDIV_D=0x1a000053\nMASK_FDIV_D=0xfe00007f\nMATCH_FSGNJ_D=0x22000053\nMASK_FSGNJ_D=0xfe00707f\nMATCH_FSGNJN_D=0x22001053\nMASK_FSGNJN_D=0xfe00707f\nMATCH_FSGNJX_D=0x22002053\nMASK_FSGNJX_D=0xfe00707f\nMATCH_FMIN_D=0x2a000053\nMASK_FMIN_D=0xfe00707f\nMATCH_FMAX_D=0x2a001053\nMASK_FMAX_D=0xfe00707f\nMATCH_FCVT_S_D=0x40100053\nMASK_FCVT_S_D=0xfff0007f\nMATCH_FCVT_D_S=0x42000053\nMASK_FCVT_D_S=0xfff0007f\nMATCH_FSQRT_D=0x5a000053\nMASK_FSQRT_D=0xfff0007f\nMATCH_FADD_Q=0x6000053\nMASK_FADD_Q=0xfe00007f\nMATCH_FSUB_Q=0xe000053\nMASK_FSUB_Q=0xfe00007f\nMATCH_FMUL_Q=0x16000053\nMASK_FMUL_Q=0xfe00007f\nMATCH_FDIV_Q=0x1e000053\nMASK_FDIV_Q=0xfe00007f\nMATCH_FSGNJ_Q=0x26000053\nMASK_FSGNJ_Q=0xfe00707f\nMATCH_FSGNJN_Q=0x26001053\nMASK_FSGNJN_Q=0xfe00707f\nMATCH_FSGNJX_Q=0x26002053\nMASK_FSGNJX_Q=0xfe00707f\nMATCH_FMIN_Q=0x2e000053\nMASK_FMIN_Q=0xfe00707f\nMATCH_FMAX_Q=0x2e001053\nMASK_FMAX_Q=0xfe00707f\nMATCH_FCVT_S_Q=0x40300053\nMASK_FCVT_S_Q=0xfff0007f\nMATCH_FCVT_Q_S=0x46000053\nMASK_FCVT_Q_S=0xfff0007f\nMATCH_FCVT_D_Q=0x42300053\nMASK_FCVT_D_Q=0xfff0007f\nMATCH_FCVT_Q_D=0x46100053\nMASK_FCVT_Q_D=0xfff0007f\nMATCH_FSQRT_Q=0x5e000053\nMASK_FSQRT_Q=0xfff0007f\nMATCH_FLE_S=0xa0000053\nMASK_FLE_S=0xfe00707f\nMATCH_FLT_S=0xa0001053\nMASK_FLT_S=0xfe00707f\nMATCH_FEQ_S=0xa0002053\nMASK_FEQ_S=0xfe00707f\nMATCH_FLE_D=0xa2000053\nMASK_FLE_D=0xfe00707f\nMATCH_FLT_D=0xa2001053\nMASK_FLT_D=0xfe00707f\nMATCH_FEQ_D=0xa2002053\nMASK_FEQ_D=0xfe00707f\nMATCH_FLE_Q=0xa6000053\nMASK_FLE_Q=0xfe00707f\nMATCH_FLT_Q=0xa6001053\nMASK_FLT_Q=0xfe00707f\nMATCH_FEQ_Q=0xa6002053\nMASK_FEQ_Q=0xfe00707f\nMATCH_FCVT_W_S=0xc0000053\nMASK_FCVT_W_S=0xfff0007f\nMATCH_FCVT_WU_S=0xc0100053\nMASK_FCVT_WU_S=0xfff0007f\nMATCH_FCVT_L_S=0xc0200053\nMASK_FCVT_L_S=0xfff0007f\nMATCH_FCVT_LU_S=0xc0300053\nMASK_FCVT_LU_S=0xfff0007f\nMATCH_FMV_X_S=0xe0000053\nMASK_FMV_X_S=0xfff0707f\nMATCH_FCLASS_S=0xe0001053\nMASK_FCLASS_S=0xfff0707f\nMATCH_FCVT_W_D=0xc2000053\nMASK_FCVT_W_D=0xfff0007f\nMATCH_FCVT_WU_D=0xc2100053\nMASK_FCVT_WU_D=0xfff0007f\nMATCH_FCVT_L_D=0xc2200053\nMASK_FCVT_L_D=0xfff0007f\nMATCH_FCVT_LU_D=0xc2300053\nMASK_FCVT_LU_D=0xfff0007f\nMATCH_FMV_X_D=0xe2000053\nMASK_FMV_X_D=0xfff0707f\nMATCH_FCLASS_D=0xe2001053\nMASK_FCLASS_D=0xfff0707f\nMATCH_FCVT_W_Q=0xc6000053\nMASK_FCVT_W_Q=0xfff0007f\nMATCH_FCVT_WU_Q=0xc6100053\nMASK_FCVT_WU_Q=0xfff0007f\nMATCH_FCVT_L_Q=0xc6200053\nMASK_FCVT_L_Q=0xfff0007f\nMATCH_FCVT_LU_Q=0xc6300053\nMASK_FCVT_LU_Q=0xfff0007f\nMATCH_FMV_X_Q=0xe6000053\nMASK_FMV_X_Q=0xfff0707f\nMATCH_FCLASS_Q=0xe6001053\nMASK_FCLASS_Q=0xfff0707f\nMATCH_FCVT_S_W=0xd0000053\nMASK_FCVT_S_W=0xfff0007f\nMATCH_FCVT_S_WU=0xd0100053\nMASK_FCVT_S_WU=0xfff0007f\nMATCH_FCVT_S_L=0xd0200053\nMASK_FCVT_S_L=0xfff0007f\nMATCH_FCVT_S_LU=0xd0300053\nMASK_FCVT_S_LU=0xfff0007f\nMATCH_FMV_S_X=0xf0000053\nMASK_FMV_S_X=0xfff0707f\nMATCH_FCVT_D_W=0xd2000053\nMASK_FCVT_D_W=0xfff0007f\nMATCH_FCVT_D_WU=0xd2100053\nMASK_FCVT_D_WU=0xfff0007f\nMATCH_FCVT_D_L=0xd2200053\nMASK_FCVT_D_L=0xfff0007f\nMATCH_FCVT_D_LU=0xd2300053\nMASK_FCVT_D_LU=0xfff0007f\nMATCH_FMV_D_X=0xf2000053\nMASK_FMV_D_X=0xfff0707f\nMATCH_FCVT_Q_W=0xd6000053\nMASK_FCVT_Q_W=0xfff0007f\nMATCH_FCVT_Q_WU=0xd6100053\nMASK_FCVT_Q_WU=0xfff0007f\nMATCH_FCVT_Q_L=0xd6200053\nMASK_FCVT_Q_L=0xfff0007f\nMATCH_FCVT_Q_LU=0xd6300053\nMASK_FCVT_Q_LU=0xfff0007f\nMATCH_FMV_Q_X=0xf6000053\nMASK_FMV_Q_X=0xfff0707f\nMATCH_FLW=0x2007\nMASK_FLW=0x707f\nMATCH_FLD=0x3007\nMASK_FLD=0x707f\nMATCH_FLQ=0x4007\nMASK_FLQ=0x707f\nMATCH_FSW=0x2027\nMASK_FSW=0x707f\nMATCH_FSD=0x3027\nMASK_FSD=0x707f\nMATCH_FSQ=0x4027\nMASK_FSQ=0x707f\nMATCH_FMADD_S=0x43\nMASK_FMADD_S=0x600007f\nMATCH_FMSUB_S=0x47\nMASK_FMSUB_S=0x600007f\nMATCH_FNMSUB_S=0x4b\nMASK_FNMSUB_S=0x600007f\nMATCH_FNMADD_S=0x4f\nMASK_FNMADD_S=0x600007f\nMATCH_FMADD_D=0x2000043\nMASK_FMADD_D=0x600007f\nMATCH_FMSUB_D=0x2000047\nMASK_FMSUB_D=0x600007f\nMATCH_FNMSUB_D=0x200004b\nMASK_FNMSUB_D=0x600007f\nMATCH_FNMADD_D=0x200004f\nMASK_FNMADD_D=0x600007f\nMATCH_FMADD_Q=0x6000043\nMASK_FMADD_Q=0x600007f\nMATCH_FMSUB_Q=0x6000047\nMASK_FMSUB_Q=0x600007f\nMATCH_FNMSUB_Q=0x600004b\nMASK_FNMSUB_Q=0x600007f\nMATCH_FNMADD_Q=0x600004f\nMASK_FNMADD_Q=0x600007f\nMATCH_C_ADDI4SPN=0x0\nMASK_C_ADDI4SPN=0xe003\nMATCH_C_FLD=0x2000\nMASK_C_FLD=0xe003\nMATCH_C_LW=0x4000\nMASK_C_LW=0xe003\nMATCH_C_FLW=0x6000\nMASK_C_FLW=0xe003\nMATCH_C_FSD=0xa000\nMASK_C_FSD=0xe003\nMATCH_C_SW=0xc000\nMASK_C_SW=0xe003\nMATCH_C_FSW=0xe000\nMASK_C_FSW=0xe003\nMATCH_C_ADDI=0x1\nMASK_C_ADDI=0xe003\nMATCH_C_JAL=0x2001\nMASK_C_JAL=0xe003\nMATCH_C_LI=0x4001\nMASK_C_LI=0xe003\nMATCH_C_LUI=0x6001\nMASK_C_LUI=0xe003\nMATCH_C_SRLI=0x8001\nMASK_C_SRLI=0xec03\nMATCH_C_SRLI64=0x8001\nMASK_C_SRLI64=0xfc7f\nMATCH_C_SRAI=0x8401\nMASK_C_SRAI=0xec03\nMATCH_C_SRAI64=0x8401\nMASK_C_SRAI64=0xfc7f\nMATCH_C_ANDI=0x8801\nMASK_C_ANDI=0xec03\nMATCH_C_SUB=0x8c01\nMASK_C_SUB=0xfc63\nMATCH_C_XOR=0x8c21\nMASK_C_XOR=0xfc63\nMATCH_C_OR=0x8c41\nMASK_C_OR=0xfc63\nMATCH_C_AND=0x8c61\nMASK_C_AND=0xfc63\nMATCH_C_SUBW=0x9c01\nMASK_C_SUBW=0xfc63\nMATCH_C_ADDW=0x9c21\nMASK_C_ADDW=0xfc63\nMATCH_C_J=0xa001\nMASK_C_J=0xe003\nMATCH_C_BEQZ=0xc001\nMASK_C_BEQZ=0xe003\nMATCH_C_BNEZ=0xe001\nMASK_C_BNEZ=0xe003\nMATCH_C_SLLI=0x2\nMASK_C_SLLI=0xe003\nMATCH_C_SLLI64=0x2\nMASK_C_SLLI64=0xf07f\nMATCH_C_FLDSP=0x2002\nMASK_C_FLDSP=0xe003\nMATCH_C_LWSP=0x4002\nMASK_C_LWSP=0xe003\nMATCH_C_FLWSP=0x6002\nMASK_C_FLWSP=0xe003\nMATCH_C_MV=0x8002\nMASK_C_MV=0xf003\nMATCH_C_ADD=0x9002\nMASK_C_ADD=0xf003\nMATCH_C_FSDSP=0xa002\nMASK_C_FSDSP=0xe003\nMATCH_C_SWSP=0xc002\nMASK_C_SWSP=0xe003\nMATCH_C_FSWSP=0xe002\nMASK_C_FSWSP=0xe003\nMATCH_C_NOP=0x1\nMASK_C_NOP=0xffff\nMATCH_C_ADDI16SP=0x6101\nMASK_C_ADDI16SP=0xef83\nMATCH_C_JR=0x8002\nMASK_C_JR=0xf07f\nMATCH_C_JALR=0x9002\nMASK_C_JALR=0xf07f\nMATCH_C_EBREAK=0x9002\nMASK_C_EBREAK=0xffff\nMATCH_C_LD=0x6000\nMASK_C_LD=0xe003\nMATCH_C_SD=0xe000\nMASK_C_SD=0xe003\nMATCH_C_ADDIW=0x2001\nMASK_C_ADDIW=0xe003\nMATCH_C_LDSP=0x6002\nMASK_C_LDSP=0xe003\nMATCH_C_SDSP=0xe002\nMASK_C_SDSP=0xe003\nMATCH_CUSTOM0=0xb\nMASK_CUSTOM0=0x707f\nMATCH_CUSTOM0_RS1=0x200b\nMASK_CUSTOM0_RS1=0x707f\nMATCH_CUSTOM0_RS1_RS2=0x300b\nMASK_CUSTOM0_RS1_RS2=0x707f\nMATCH_CUSTOM0_RD=0x400b\nMASK_CUSTOM0_RD=0x707f\nMATCH_CUSTOM0_RD_RS1=0x600b\nMASK_CUSTOM0_RD_RS1=0x707f\nMATCH_CUSTOM0_RD_RS1_RS2=0x700b\nMASK_CUSTOM0_RD_RS1_RS2=0x707f\nMATCH_CUSTOM1=0x2b\nMASK_CUSTOM1=0x707f\nMATCH_CUSTOM1_RS1=0x202b\nMASK_CUSTOM1_RS1=0x707f\nMATCH_CUSTOM1_RS1_RS2=0x302b\nMASK_CUSTOM1_RS1_RS2=0x707f\nMATCH_CUSTOM1_RD=0x402b\nMASK_CUSTOM1_RD=0x707f\nMATCH_CUSTOM1_RD_RS1=0x602b\nMASK_CUSTOM1_RD_RS1=0x707f\nMATCH_CUSTOM1_RD_RS1_RS2=0x702b\nMASK_CUSTOM1_RD_RS1_RS2=0x707f\nMATCH_CUSTOM2=0x5b\nMASK_CUSTOM2=0x707f\nMATCH_CUSTOM2_RS1=0x205b\nMASK_CUSTOM2_RS1=0x707f\nMATCH_CUSTOM2_RS1_RS2=0x305b\nMASK_CUSTOM2_RS1_RS2=0x707f\nMATCH_CUSTOM2_RD=0x405b\nMASK_CUSTOM2_RD=0x707f\nMATCH_CUSTOM2_RD_RS1=0x605b\nMASK_CUSTOM2_RD_RS1=0x707f\nMATCH_CUSTOM2_RD_RS1_RS2=0x705b\nMASK_CUSTOM2_RD_RS1_RS2=0x707f\nMATCH_CUSTOM3=0x7b\nMASK_CUSTOM3=0x707f\nMATCH_CUSTOM3_RS1=0x207b\nMASK_CUSTOM3_RS1=0x707f\nMATCH_CUSTOM3_RS1_RS2=0x307b\nMASK_CUSTOM3_RS1_RS2=0x707f\nMATCH_CUSTOM3_RD=0x407b\nMASK_CUSTOM3_RD=0x707f\nMATCH_CUSTOM3_RD_RS1=0x607b\nMASK_CUSTOM3_RD_RS1=0x707f\nMATCH_CUSTOM3_RD_RS1_RS2=0x707b\nMASK_CUSTOM3_RD_RS1_RS2=0x707f\nCSR_USTATUS=0x0\nCSR_UIE=0x4\nCSR_UTVEC=0x5\nCSR_USCRATCH=0x40\nCSR_UEPC=0x41\nCSR_UCAUSE=0x42\nCSR_UTVAL=0x43\nCSR_UIP=0x44\nCSR_FFLAGS=0x1\nCSR_FRM=0x2\nCSR_FCSR=0x3\nCSR_CYCLE=0xc00\nCSR_TIME=0xc01\nCSR_INSTRET=0xc02\nCSR_HPMCOUNTER3=0xc03\nCSR_HPMCOUNTER4=0xc04\nCSR_HPMCOUNTER5=0xc05\nCSR_HPMCOUNTER6=0xc06\nCSR_HPMCOUNTER7=0xc07\nCSR_HPMCOUNTER8=0xc08\nCSR_HPMCOUNTER9=0xc09\nCSR_HPMCOUNTER10=0xc0a\nCSR_HPMCOUNTER11=0xc0b\nCSR_HPMCOUNTER12=0xc0c\nCSR_HPMCOUNTER13=0xc0d\nCSR_HPMCOUNTER14=0xc0e\nCSR_HPMCOUNTER15=0xc0f\nCSR_HPMCOUNTER16=0xc10\nCSR_HPMCOUNTER17=0xc11\nCSR_HPMCOUNTER18=0xc12\nCSR_HPMCOUNTER19=0xc13\nCSR_HPMCOUNTER20=0xc14\nCSR_HPMCOUNTER21=0xc15\nCSR_HPMCOUNTER22=0xc16\nCSR_HPMCOUNTER23=0xc17\nCSR_HPMCOUNTER24=0xc18\nCSR_HPMCOUNTER25=0xc19\nCSR_HPMCOUNTER26=0xc1a\nCSR_HPMCOUNTER27=0xc1b\nCSR_HPMCOUNTER28=0xc1c\nCSR_HPMCOUNTER29=0xc1d\nCSR_HPMCOUNTER30=0xc1e\nCSR_HPMCOUNTER31=0xc1f\nCSR_CYCLEH=0xc80\nCSR_TIMEH=0xc81\nCSR_INSTRETH=0xc82\nCSR_HPMCOUNTER3H=0xc83\nCSR_HPMCOUNTER4H=0xc84\nCSR_HPMCOUNTER5H=0xc85\nCSR_HPMCOUNTER6H=0xc86\nCSR_HPMCOUNTER7H=0xc87\nCSR_HPMCOUNTER8H=0xc88\nCSR_HPMCOUNTER9H=0xc89\nCSR_HPMCOUNTER10H=0xc8a\nCSR_HPMCOUNTER11H=0xc8b\nCSR_HPMCOUNTER12H=0xc8c\nCSR_HPMCOUNTER13H=0xc8d\nCSR_HPMCOUNTER14H=0xc8e\nCSR_HPMCOUNTER15H=0xc8f\nCSR_HPMCOUNTER16H=0xc90\nCSR_HPMCOUNTER17H=0xc91\nCSR_HPMCOUNTER18H=0xc92\nCSR_HPMCOUNTER19H=0xc93\nCSR_HPMCOUNTER20H=0xc94\nCSR_HPMCOUNTER21H=0xc95\nCSR_HPMCOUNTER22H=0xc96\nCSR_HPMCOUNTER23H=0xc97\nCSR_HPMCOUNTER24H=0xc98\nCSR_HPMCOUNTER25H=0xc99\nCSR_HPMCOUNTER26H=0xc9a\nCSR_HPMCOUNTER27H=0xc9b\nCSR_HPMCOUNTER28H=0xc9c\nCSR_HPMCOUNTER29H=0xc9d\nCSR_HPMCOUNTER30H=0xc9e\nCSR_HPMCOUNTER31H=0xc9f\nCSR_SSTATUS=0x100\nCSR_SEDELEG=0x102\nCSR_SIDELEG=0x103\nCSR_SIE=0x104\nCSR_STVEC=0x105\nCSR_SCOUNTEREN=0x106\nCSR_SSCRATCH=0x140\nCSR_SEPC=0x141\nCSR_SCAUSE=0x142\nCSR_STVAL=0x143\nCSR_SIP=0x144\nCSR_SATP=0x180\nCSR_MVENDORID=0xf11\nCSR_MARCHID=0xf12\nCSR_MIMPID=0xf13\nCSR_MHARTID=0xf14\nCSR_MSTATUS=0x300\nCSR_MISA=0x301\nCSR_MEDELEG=0x302\nCSR_MIDELEG=0x303\nCSR_MIE=0x304\nCSR_MTVEC=0x305\nCSR_MCOUNTEREN=0x306\nCSR_MSCRATCH=0x340\nCSR_MEPC=0x341\nCSR_MCAUSE=0x342\nCSR_MTVAL=0x343\nCSR_MIP=0x344\nCSR_PMPCFG0=0x3a0\nCSR_PMPCFG1=0x3a1\nCSR_PMPCFG2=0x3a2\nCSR_PMPCFG3=0x3a3\nCSR_PMPADDR0=0x3b0\nCSR_PMPADDR1=0x3b1\nCSR_PMPADDR2=0x3b2\nCSR_PMPADDR3=0x3b3\nCSR_PMPADDR4=0x3b4\nCSR_PMPADDR5=0x3b5\nCSR_PMPADDR6=0x3b6\nCSR_PMPADDR7=0x3b7\nCSR_PMPADDR8=0x3b8\nCSR_PMPADDR9=0x3b9\nCSR_PMPADDR10=0x3ba\nCSR_PMPADDR11=0x3bb\nCSR_PMPADDR12=0x3bc\nCSR_PMPADDR13=0x3bd\nCSR_PMPADDR14=0x3be\nCSR_PMPADDR15=0x3bf\nCSR_MCYCLE=0xb00\nCSR_MINSTRET=0xb02\nCSR_MHPMCOUNTER3=0xb03\nCSR_MHPMCOUNTER4=0xb04\nCSR_MHPMCOUNTER5=0xb05\nCSR_MHPMCOUNTER6=0xb06\nCSR_MHPMCOUNTER7=0xb07\nCSR_MHPMCOUNTER8=0xb08\nCSR_MHPMCOUNTER9=0xb09\nCSR_MHPMCOUNTER10=0xb0a\nCSR_MHPMCOUNTER11=0xb0b\nCSR_MHPMCOUNTER12=0xb0c\nCSR_MHPMCOUNTER13=0xb0d\nCSR_MHPMCOUNTER14=0xb0e\nCSR_MHPMCOUNTER15=0xb0f\nCSR_MHPMCOUNTER16=0xb10\nCSR_MHPMCOUNTER17=0xb11\nCSR_MHPMCOUNTER18=0xb12\nCSR_MHPMCOUNTER19=0xb13\nCSR_MHPMCOUNTER20=0xb14\nCSR_MHPMCOUNTER21=0xb15\nCSR_MHPMCOUNTER22=0xb16\nCSR_MHPMCOUNTER23=0xb17\nCSR_MHPMCOUNTER24=0xb18\nCSR_MHPMCOUNTER25=0xb19\nCSR_MHPMCOUNTER26=0xb1a\nCSR_MHPMCOUNTER27=0xb1b\nCSR_MHPMCOUNTER28=0xb1c\nCSR_MHPMCOUNTER29=0xb1d\nCSR_MHPMCOUNTER30=0xb1e\nCSR_MHPMCOUNTER31=0xb1f\nCSR_MCYCLEH=0xb80\nCSR_MINSTRETH=0xb82\nCSR_MHPMCOUNTER3H=0xb83\nCSR_MHPMCOUNTER4H=0xb84\nCSR_MHPMCOUNTER5H=0xb85\nCSR_MHPMCOUNTER6H=0xb86\nCSR_MHPMCOUNTER7H=0xb87\nCSR_MHPMCOUNTER8H=0xb88\nCSR_MHPMCOUNTER9H=0xb89\nCSR_MHPMCOUNTER10H=0xb8a\nCSR_MHPMCOUNTER11H=0xb8b\nCSR_MHPMCOUNTER12H=0xb8c\nCSR_MHPMCOUNTER13H=0xb8d\nCSR_MHPMCOUNTER14H=0xb8e\nCSR_MHPMCOUNTER15H=0xb8f\nCSR_MHPMCOUNTER16H=0xb90\nCSR_MHPMCOUNTER17H=0xb91\nCSR_MHPMCOUNTER18H=0xb92\nCSR_MHPMCOUNTER19H=0xb93\nCSR_MHPMCOUNTER20H=0xb94\nCSR_MHPMCOUNTER21H=0xb95\nCSR_MHPMCOUNTER22H=0xb96\nCSR_MHPMCOUNTER23H=0xb97\nCSR_MHPMCOUNTER24H=0xb98\nCSR_MHPMCOUNTER25H=0xb99\nCSR_MHPMCOUNTER26H=0xb9a\nCSR_MHPMCOUNTER27H=0xb9b\nCSR_MHPMCOUNTER28H=0xb9c\nCSR_MHPMCOUNTER29H=0xb9d\nCSR_MHPMCOUNTER30H=0xb9e\nCSR_MHPMCOUNTER31H=0xb9f\nCSR_MHPMEVENT3=0x323\nCSR_MHPMEVENT4=0x324\nCSR_MHPMEVENT5=0x325\nCSR_MHPMEVENT6=0x326\nCSR_MHPMEVENT7=0x327\nCSR_MHPMEVENT8=0x328\nCSR_MHPMEVENT9=0x329\nCSR_MHPMEVENT10=0x32a\nCSR_MHPMEVENT11=0x32b\nCSR_MHPMEVENT12=0x32c\nCSR_MHPMEVENT13=0x32d\nCSR_MHPMEVENT14=0x32e\nCSR_MHPMEVENT15=0x32f\nCSR_MHPMEVENT16=0x330\nCSR_MHPMEVENT17=0x331\nCSR_MHPMEVENT18=0x332\nCSR_MHPMEVENT19=0x333\nCSR_MHPMEVENT20=0x334\nCSR_MHPMEVENT21=0x335\nCSR_MHPMEVENT22=0x336\nCSR_MHPMEVENT23=0x337\nCSR_MHPMEVENT24=0x338\nCSR_MHPMEVENT25=0x339\nCSR_MHPMEVENT26=0x33a\nCSR_MHPMEVENT27=0x33b\nCSR_MHPMEVENT28=0x33c\nCSR_MHPMEVENT29=0x33d\nCSR_MHPMEVENT30=0x33e\nCSR_MHPMEVENT31=0x33f\nCSR_TSELECT=0x7a0\nCSR_TDATA1=0x7a1\nCSR_TDATA2=0x7a2\nCSR_TDATA3=0x7a3\nCSR_DCSR=0x7b0\nCSR_DPC=0x7b1\nCSR_DSCRATCH=0x7b2\nCSR_HSTATUS=0x200\nCSR_HEDELEG=0x202\nCSR_HIDELEG=0x203\nCSR_HIE=0x204\nCSR_HTVEC=0x205\nCSR_HSCRATCH=0x240\nCSR_HEPC=0x241\nCSR_HCAUSE=0x242\nCSR_HBADADDR=0x243\nCSR_HIP=0x244\nCSR_MBASE=0x380\nCSR_MBOUND=0x381\nCSR_MIBASE=0x382\nCSR_MIBOUND=0x383\nCSR_MDBASE=0x384\nCSR_MDBOUND=0x385\nCSR_MUCOUNTEREN=0x320\nCSR_MSCOUNTEREN=0x321\nCSR_MHCOUNTEREN=0x322\nCAUSE_MISALIGNED_FETCH=0x0\nCAUSE_FAULT_FETCH=0x1\nCAUSE_ILLEGAL_INSTRUCTION=0x2\nCAUSE_BREAKPOINT=0x3\nCAUSE_MISALIGNED_LOAD=0x4\nCAUSE_FAULT_LOAD=0x5\nCAUSE_MISALIGNED_STORE=0x6\nCAUSE_FAULT_STORE=0x7\nCAUSE_USER_ECALL=0x8\nCAUSE_SUPERVISOR_ECALL=0x9\nCAUSE_HYPERVISOR_ECALL=0xa\nCAUSE_MACHINE_ECALL=0xb\n\nMASK_RD=0x1f\n\nOP_MASK_OP=0x7f\nOP_SH_OP=0\nOP_MASK_RS2=0x1f\nOP_SH_RS2=20\nOP_MASK_RS1=0x1f\nOP_SH_RS1=15\nOP_MASK_RS3=0x1f\nOP_SH_RS3=27\nOP_MASK_RD=0x1f\nOP_SH_RD=7\nOP_MASK_SHAMT=0x3f\nOP_SH_SHAMT=20\nOP_MASK_SHAMTW=0x1f\nOP_SH_SHAMTW=20\nOP_MASK_RM=0x7\nOP_SH_RM=12\nOP_MASK_PRED=0xf\nOP_SH_PRED=24\nOP_MASK_SUCC=0xf\nOP_SH_SUCC=20\nOP_MASK_AQ=0x1\nOP_SH_AQ=26\nOP_MASK_RL=0x1\nOP_SH_RL=25\nOP_MASK_CUSTOM_IMM=0x7f\nOP_SH_CUSTOM_IMM=25\nOP_MASK_CSR=0xfff\nOP_SH_CSR=20\nOP_MASK_FUNCT3=0x7\nOP_SH_FUNCT3=12\nOP_MASK_FUNCT7=0x7f\nOP_SH_FUNCT7=25\nOP_MASK_FUNCT2=0x3\nOP_SH_FUNCT2=25\nOP_MASK_OP2=0x3\nOP_SH_OP2=0\n\nOP_MASK_CRS2=0x1f\nOP_SH_CRS2=2\nOP_MASK_CRS1S=0x7\nOP_SH_CRS1S=7\nOP_MASK_CRS2S=0x7\nOP_SH_CRS2S=2\n\nOP_MASK_CFUNCT6=0x3f\nOP_SH_CFUNCT6=10\nOP_MASK_CFUNCT4=0xf\nOP_SH_CFUNCT4=12\nOP_MASK_CFUNCT3=0x7\nOP_SH_CFUNCT3=13\nOP_MASK_CFUNCT2=0x3\nOP_SH_CFUNCT2=5\n\nM_LA=0\nM_LLA=1\nM_LA_TLS_GD=2\nM_LA_TLS_IE=3\nM_LB=4\nM_LBU=5\nM_LH=6\nM_LHU=7\nM_LW=8\nM_LWU=9\nM_LD=10\nM_SB=11\nM_SH=12\nM_SW=13\nM_SD=14\nM_FLW=15\nM_FLD=16\nM_FLQ=17\nM_FSW=18\nM_FSD=19\nM_FSQ=20\nM_CALL=21\nM_J=22\nM_LI=23\nM_NUM_MACROS=24\n\n\n\nX_RA=1\nX_SP=2\nX_GP=3\nX_TP=4\nX_T0=5\nX_T1=6\nX_T2=7\nX_T3=28\n\nNGPR=32\nNFPR=32\n\n\n\n\nISAC = 1\nISAI = 2\nISAA = 3\nISAM = 4\nISAF = 5\nISAFC = 6\nISADC = 7\nISAD = 8\nISAQ = 9\n\nINSN_TYPE=0x0000000e\nINSN_MACRO=0xffffffff\nINSN_ALIAS=0x00000001\nINSN_BRANCH=0x00000002\nINSN_CONDBRANCH=0x00000004\nINSN_JSR=0x00000006\nINSN_DREF=0x00000008\n\n\nINSN_DATA_SIZE=0x00000070\nINSN_DATA_SIZE_SHIFT=4\nINSN_1_BYTE=0x00000010\nINSN_2_BYTE=0x00000020\nINSN_4_BYTE=0x00000030\nINSN_8_BYTE=0x00000040\nINSN_16_BYTE=0x0000050\n\n\n\n\ndef RV_X(x, s, n):\n return (((x) >> (s)) & ((1 << (n)) - 1))\n\ndef RV_IMM_SIGN(x):\n return (-(((x) >> 31) & 1))\n\ndef EXTRACT_ITYPE_IMM(x):\n return (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))\ndef EXTRACT_STYPE_IMM(x):\n return (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))\ndef EXTRACT_SBTYPE_IMM(x):\n return ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))\ndef EXTRACT_UTYPE_IMM(x):\n return ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))\ndef EXTRACT_UJTYPE_IMM(x):\n return ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))\ndef EXTRACT_RVC_IMM(x):\n return (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))\ndef EXTRACT_RVC_LUI_IMM(x):\n return (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)\ndef EXTRACT_RVC_SIMM3(x):\n return (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))\ndef EXTRACT_RVC_UIMM8(x):\n return (RV_X(x, 5, 8))\ndef EXTRACT_RVC_ADDI4SPN_IMM(x):\n return ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))\ndef EXTRACT_RVC_ADDI16SP_IMM(x):\n return ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))\ndef EXTRACT_RVC_LW_IMM(x):\n return ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))\ndef EXTRACT_RVC_LD_IMM(x):\n return ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))\ndef EXTRACT_RVC_LWSP_IMM(x):\n return ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))\ndef EXTRACT_RVC_LDSP_IMM(x):\n return ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))\ndef EXTRACT_RVC_SWSP_IMM(x):\n return ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))\ndef EXTRACT_RVC_SDSP_IMM(x):\n return ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))\ndef EXTRACT_RVC_B_IMM(x):\n return ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))\ndef EXTRACT_RVC_J_IMM(x):\n return ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))\n\ndef ENCODE_ITYPE_IMM(x):\n return (RV_X(x, 0, 12) << 20)\ndef ENCODE_STYPE_IMM(x):\n return ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))\ndef ENCODE_SBTYPE_IMM(x):\n return ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))\ndef ENCODE_UTYPE_IMM(x):\n return (RV_X(x, 12, 20) << 12)\ndef ENCODE_UJTYPE_IMM(x):\n return ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))\ndef ENCODE_RVC_IMM(x):\n return ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))\ndef ENCODE_RVC_LUI_IMM(x):\n return ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)\ndef ENCODE_RVC_SIMM3(x):\n return (RV_X(x, 0, 3) << 10)\ndef ENCODE_RVC_UIMM8(x):\n return (RV_X(x, 0, 8) << 5)\ndef ENCODE_RVC_ADDI4SPN_IMM(x):\n return ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))\ndef ENCODE_RVC_ADDI16SP_IMM(x):\n return ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))\ndef ENCODE_RVC_LW_IMM(x):\n return ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))\ndef ENCODE_RVC_LD_IMM(x):\n return ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))\ndef ENCODE_RVC_LWSP_IMM(x):\n return ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))\ndef ENCODE_RVC_LDSP_IMM(x):\n return ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))\ndef ENCODE_RVC_SWSP_IMM(x):\n return ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))\ndef ENCODE_RVC_SDSP_IMM(x):\n return ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))\ndef ENCODE_RVC_B_IMM(x):\n return ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))\ndef ENCODE_RVC_J_IMM(x):\n return ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))\n\n\n\nMASK_RS1= (OP_MASK_RS1 << OP_SH_RS1)\nMASK_RS2= (OP_MASK_RS2 << OP_SH_RS2)\nMASK_RD= (OP_MASK_RD << OP_SH_RD)\nMASK_CRS2= (OP_MASK_CRS2 << OP_SH_CRS2)\nMASK_IMM= ENCODE_ITYPE_IMM(-1)\nMASK_RVC_IMM= ENCODE_RVC_IMM(-1)\nMASK_UIMM= ENCODE_UTYPE_IMM(-1)\nMASK_RM= (OP_MASK_RM << OP_SH_RM)\nMASK_PRED= (OP_MASK_PRED << OP_SH_PRED)\nMASK_SUCC= (OP_MASK_SUCC << OP_SH_SUCC)\nMASK_AQ= (OP_MASK_AQ << OP_SH_AQ)\nMASK_RL= (OP_MASK_RL << OP_SH_RL)\nMASK_AQRL= (MASK_AQ | MASK_RL)\n\n\ndef match_opcode(op, insn):\n print(\"match_opcode: %08x %08x %08x %08x %08x\" % (op.match, op.mask, insn, insn ^ op.match, (insn ^ op.match) & op.mask))\n return ((insn ^ op.match) & op.mask) == 0\n\ndef match_never(op, insn):\n return False\n\ndef match_rs1_eq_rs2(op, insn):\n rs1 = (insn & MASK_RS1) >> OP_SH_RS1\n rs2 = (insn & MASK_RS2) >> OP_SH_RS2\n return match_opcode(op, insn) and rs1 == rs2\n\ndef match_rd_nonzero(op, insn):\n return match_opcode(op, insn) and ((insn & MASK_RD) != 0)\n\ndef match_c_add(op, insn):\n return match_rd_nonzero(op, insn) and ((insn & MASK_CRS2) != 0)\n\ndef match_c_add_with_hint(op, insn):\n return match_opcode(op, insn) and ((insn & MASK_CRS2) != 0)\n\ndef match_c_nop(op, insn):\n return match_opcode(op, insn) and (((insn & MASK_RD) >> OP_SH_RD) == 0)\n\ndef match_c_add16sp(op, insn):\n return match_opcode(op, insn) and (((insn & MASK_RD) >> OP_SH_RD) == 2)\n\ndef match_c_lui(op, insn):\n return False\n\ndef match_c_addi4spn(op, insn):\n return False\n\ndef match_c_addi16sp(op, insn):\n return False\n\ndef match_slli_as_c_slli(op, insn):\n return False\n\ndef match_srxi_as_c_srxi(op, insn):\n return False\n\ndef match_c_lui_with_hint(op, insn):\n return False\n\ndef match_c_slli(op, insn):\n return False\n\ndef match_c_slli64(op, insn):\n return False\n\n\n\nclass OpCode:\n def __init__(self, op):\n self.name = op[0]\n self.xlen = op[1]\n self.isa = op[2]\n self.operands = op[3]\n self.match = op[4]\n self.mask = op[5]\n self.func = op[6]\n self.pinfo = op[7]\n self.size = 0\n if self.pinfo & INSN_DATA_SIZE:\n self.size = ((self.pinfo & INSN_DATA_SIZE) >> INSN_DATA_SIZE_SHIFT)\n self.size = 1 << (self.size - 1)\n def __str__(self):\n return \"%s %s %08x %08x %08x (%d, %d) \" % (self.name, self.operands, self.match, self.mask, self.pinfo, self.xlen, self.size)\n def __eq__(self, other):\n if other is None:\n return False\n if self.name != other.name:\n return False\n if self.mask != other.mask:\n return False\n if self.match != other.match:\n return False\n if self.operands != other.operands:\n return False\n if self.pinfo != other.pinfo:\n return False\n if self.xlen != other.xlen:\n return False\n return True\n\n# name, xlen, isa, operands, match, mask, match_func, pinfo\nopcodes = [\n (\"unimp\", 0, ISAC, \"\", 0, 0xffff, match_opcode, INSN_ALIAS ),\n (\"unimp\", 0, ISAI, \"\", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffff, match_opcode, 0 ), #/* csrw cycle, x0 */\n (\"ebreak\", 0, ISAC, \"\", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS ),\n (\"ebreak\", 0, ISAI, \"\", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 ),\n #(\"sbreak\", 0, ISAC, \"\", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS ),\n #(\"sbreak\", 0, ISAI, \"\", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS ),\n (\"ret\", 0, ISAC, \"\", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"ret\", 0, ISAI, \"\", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"jr\", 0, ISAC, \"d\", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH ),\n (\"jr\", 0, ISAI, \"s\", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"jr\", 0, ISAI, \"o(s)\", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"jr\", 0, ISAI, \"s,j\", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"jalr\", 0, ISAC, \"d\", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR ),\n (\"jalr\", 0, ISAI, \"s\", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR ),\n (\"jalr\", 0, ISAI, \"o(s)\", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR ),\n (\"jalr\", 0, ISAI, \"s,j\", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR ),\n (\"jalr\", 0, ISAI, \"d,s\", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR ),\n (\"jalr\", 0, ISAI, \"d,o(s)\", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR ),\n (\"jalr\", 0, ISAI, \"d,s,j\", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR ),\n (\"j\", 0, ISAC, \"Ca\", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"j\", 0, ISAI, \"a\", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ),\n (\"jal\", 0, ISAI, \"d,a\", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR ),\n (\"jal\", 32, ISAC, \"Ca\", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR ),\n (\"jal\", 0, ISAI, \"a\", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR ),\n (\"call\", 0, ISAI, \"d,c\", (X_T1 << OP_SH_RS1), M_CALL, match_never, INSN_MACRO ),\n (\"call\", 0, ISAI, \"c\", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), M_CALL, match_never, INSN_MACRO ),\n (\"tail\", 0, ISAI, \"c\", (X_T1 << OP_SH_RS1), M_CALL, match_never, INSN_MACRO ),\n (\"jump\", 0, ISAI, \"c,s\", 0, M_CALL, match_never, INSN_MACRO ),\n (\"nop\", 0, ISAC, \"\", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS ),\n (\"nop\", 0, ISAI, \"\", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"lui\", 0, ISAC, \"d,Cu\", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS ),\n (\"lui\", 0, ISAI, \"d,u\", MATCH_LUI, MASK_LUI, match_opcode, 0 ),\n (\"li\", 0, ISAC, \"d,Cv\", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS ),\n (\"li\", 0, ISAC, \"d,Co\", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS ),\n (\"li\", 0, ISAI, \"d,j\", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS ), #/* addi */\n (\"li\", 0, ISAI, \"d,I\", 0, M_LI, match_never, INSN_MACRO ),\n (\"mv\", 0, ISAC, \"d,CV\", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS ),\n (\"mv\", 0, ISAI, \"d,s\", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"move\", 0, ISAC, \"d,CV\", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS ),\n (\"move\", 0, ISAI, \"d,s\", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"andi\", 0, ISAC, \"Cs,Cw,Co\", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS ),\n (\"andi\", 0, ISAI, \"d,s,j\", MATCH_ANDI, MASK_ANDI, match_opcode, 0 ),\n (\"and\", 0, ISAC, \"Cs,Cw,Ct\", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS ),\n (\"and\", 0, ISAC, \"Cs,Ct,Cw\", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS ),\n (\"and\", 0, ISAC, \"Cs,Cw,Co\", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS ),\n (\"and\", 0, ISAI, \"d,s,t\", MATCH_AND, MASK_AND, match_opcode, 0 ),\n (\"and\", 0, ISAI, \"d,s,j\", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS ),\n (\"beqz\", 0, ISAC, \"Cs,Cp\", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"beqz\", 0, ISAI, \"s,p\", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"beq\", 0, ISAC, \"Cs,Cz,Cp\", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"beq\", 0, ISAI, \"s,t,p\", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH ),\n (\"blez\", 0, ISAI, \"t,p\", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bgez\", 0, ISAI, \"s,p\", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bge\", 0, ISAI, \"s,t,p\", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH ),\n (\"bgeu\", 0, ISAI, \"s,t,p\", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_CONDBRANCH ),\n (\"ble\", 0, ISAI, \"t,s,p\", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bleu\", 0, ISAI, \"t,s,p\", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bltz\", 0, ISAI, \"s,p\", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bgtz\", 0, ISAI, \"t,p\", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"blt\", 0, ISAI, \"s,t,p\", MATCH_BLT, MASK_BLT, match_opcode, INSN_CONDBRANCH ),\n (\"bltu\", 0, ISAI, \"s,t,p\", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_CONDBRANCH ),\n (\"bgt\", 0, ISAI, \"t,s,p\", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bgtu\", 0, ISAI, \"t,s,p\", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bnez\", 0, ISAC, \"Cs,Cp\", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bnez\", 0, ISAI, \"s,p\", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bne\", 0, ISAC, \"Cs,Cz,Cp\", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ),\n (\"bne\", 0, ISAI, \"s,t,p\", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH ),\n (\"addi\", 0, ISAC, \"Ct,Cc,CK\", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS ),\n (\"addi\", 0, ISAC, \"d,CU,Cj\", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS ),\n (\"addi\", 0, ISAC, \"d,CU,z\", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS ),\n (\"addi\", 0, ISAC, \"Cc,Cc,CL\", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS ),\n (\"addi\", 0, ISAI, \"d,s,j\", MATCH_ADDI, MASK_ADDI, match_opcode, 0 ),\n (\"add\", 0, ISAC, \"d,CU,CV\", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS ),\n (\"add\", 0, ISAC, \"d,CV,CU\", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS ),\n (\"add\", 0, ISAC, \"d,CU,Co\", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS ),\n (\"add\", 0, ISAC, \"Ct,Cc,CK\", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS ),\n (\"add\", 0, ISAC, \"Cc,Cc,CL\", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS ),\n (\"add\", 0, ISAI, \"d,s,t\", MATCH_ADD, MASK_ADD, match_opcode, 0 ),\n #/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc\n #applied to an add instruction, for relaxation to use. */\n #(\"add\", 0, ISAI, \"d,s,t,1\",MATCH_ADD, MASK_ADD, match_opcode, 0 ),\n (\"add\", 0, ISAI, \"d,s,j\", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS ),\n (\"la\", 0, ISAI, \"d,B\", 0, M_LA, match_never, INSN_MACRO ),\n (\"lla\", 0, ISAI, \"d,B\", 0, M_LLA, match_never, INSN_MACRO ),\n (\"la.tls.gd\", 0, ISAI, \"d,A\", 0, M_LA_TLS_GD, match_never, INSN_MACRO ),\n (\"la.tls.ie\", 0, ISAI, \"d,A\", 0, M_LA_TLS_IE, match_never, INSN_MACRO ),\n (\"neg\", 0, ISAI, \"d,t\", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS ), #/* sub 0 */\n (\"slli\", 0, ISAC, \"d,CU,C>\", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS ),\n (\"slli\", 0, ISAI, \"d,s,>\", MATCH_SLLI, MASK_SLLI, match_opcode, 0 ),\n (\"sll\", 0, ISAC, \"d,CU,C>\", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS ),\n (\"sll\", 0, ISAI, \"d,s,t\", MATCH_SLL, MASK_SLL, match_opcode, 0 ),\n (\"sll\", 0, ISAI, \"d,s,>\", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS ),\n (\"srli\", 0, ISAC, \"Cs,Cw,C>\", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS ),\n (\"srli\", 0, ISAI, \"d,s,>\", MATCH_SRLI, MASK_SRLI, match_opcode, 0 ),\n (\"srl\", 0, ISAC, \"Cs,Cw,C>\", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS ),\n (\"srl\", 0, ISAI, \"d,s,t\", MATCH_SRL, MASK_SRL, match_opcode, 0 ),\n (\"srl\", 0, ISAI, \"d,s,>\", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS ),\n (\"srai\", 0, ISAC, \"Cs,Cw,C>\", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS ),\n (\"srai\", 0, ISAI, \"d,s,>\", MATCH_SRAI, MASK_SRAI, match_opcode, 0 ),\n (\"sra\", 0, ISAC, \"Cs,Cw,C>\", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS ),\n (\"sra\", 0, ISAI, \"d,s,t\", MATCH_SRA, MASK_SRA, match_opcode, 0 ),\n (\"sra\", 0, ISAI, \"d,s,>\", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS ),\n (\"sub\", 0, ISAC, \"Cs,Cw,Ct\", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS ),\n (\"sub\", 0, ISAI, \"d,s,t\", MATCH_SUB, MASK_SUB, match_opcode, 0 ),\n (\"lb\", 0, ISAI, \"d,o(s)\", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE ),\n (\"lb\", 0, ISAI, \"d,A\", 0, M_LB, match_never, INSN_MACRO ),\n (\"lbu\", 0, ISAI, \"d,o(s)\", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE ),\n (\"lbu\", 0, ISAI, \"d,A\", 0, M_LBU, match_never, INSN_MACRO ),\n (\"lh\", 0, ISAI, \"d,o(s)\", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE ),\n (\"lh\", 0, ISAI, \"d,A\", 0, M_LH, match_never, INSN_MACRO ),\n (\"lhu\", 0, ISAI, \"d,o(s)\", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE ),\n (\"lhu\", 0, ISAI, \"d,A\", 0, M_LHU, match_never, INSN_MACRO ),\n (\"lw\", 0, ISAC, \"d,Cm(Cc)\", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"lw\", 0, ISAC, \"Ct,Ck(Cs)\", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"lw\", 0, ISAI, \"d,o(s)\", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"lw\", 0, ISAI, \"d,A\", 0, M_LW, match_never, INSN_MACRO ),\n (\"not\", 0, ISAI, \"d,s\", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"ori\", 0, ISAI, \"d,s,j\", MATCH_ORI, MASK_ORI, match_opcode, 0 ),\n (\"or\", 0, ISAC, \"Cs,Cw,Ct\", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS ),\n (\"or\", 0, ISAC, \"Cs,Ct,Cw\", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS ),\n (\"or\", 0, ISAI, \"d,s,t\", MATCH_OR, MASK_OR, match_opcode, 0 ),\n (\"or\", 0, ISAI, \"d,s,j\", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS ),\n (\"auipc\", 0, ISAI, \"d,u\", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 ),\n (\"seqz\", 0, ISAI, \"d,s\", MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"snez\", 0, ISAI, \"d,t\", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS ),\n (\"sltz\", 0, ISAI, \"d,s\", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS ),\n (\"sgtz\", 0, ISAI, \"d,t\", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS ),\n (\"slti\", 0, ISAI, \"d,s,j\", MATCH_SLTI, MASK_SLTI, match_opcode, 0 ),\n (\"slt\", 0, ISAI, \"d,s,t\", MATCH_SLT, MASK_SLT, match_opcode, 0 ),\n (\"slt\", 0, ISAI, \"d,s,j\", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS ),\n (\"sltiu\", 0, ISAI, \"d,s,j\", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 ),\n (\"sltu\", 0, ISAI, \"d,s,t\", MATCH_SLTU, MASK_SLTU, match_opcode, 0 ),\n (\"sltu\", 0, ISAI, \"d,s,j\", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS ),\n (\"sgt\", 0, ISAI, \"d,t,s\", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS ),\n (\"sgtu\", 0, ISAI, \"d,t,s\", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS ),\n (\"sb\", 0, ISAI, \"t,q(s)\", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE ),\n (\"sb\", 0, ISAI, \"t,A,s\", 0, M_SB, match_never, INSN_MACRO ),\n (\"sh\", 0, ISAI, \"t,q(s)\", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE ),\n (\"sh\", 0, ISAI, \"t,A,s\", 0, M_SH, match_never, INSN_MACRO ),\n (\"sw\", 0, ISAC, \"CV,CM(Cc)\", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"sw\", 0, ISAC, \"Ct,Ck(Cs)\", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"sw\", 0, ISAI, \"t,q(s)\", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"sw\", 0, ISAI, \"t,A,s\", 0, M_SW, match_never, INSN_MACRO ),\n (\"fence\", 0, ISAI, \"\", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"fence\", 0, ISAI, \"P,Q\", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 ),\n (\"fence.i\", 0, ISAI, \"\", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 ),\n (\"fence.tso\", 0, ISAI, \"\", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS ),\n (\"rdcycle\", 0, ISAI, \"d\", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS ),\n (\"rdinstret\", 0, ISAI, \"d\", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS ),\n (\"rdtime\", 0, ISAI, \"d\", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS ),\n (\"rdcycleh\", 32, ISAI, \"d\", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS ),\n (\"rdinstreth\", 32, ISAI, \"d\", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS ),\n (\"rdtimeh\", 32, ISAI, \"d\", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS ),\n (\"ecall\", 0, ISAI, \"\", MATCH_SCALL, MASK_SCALL, match_opcode, 0 ),\n #(\"scall\", 0, ISAI, \"\", MATCH_SCALL, MASK_SCALL, match_opcode, 0 ),\n (\"xori\", 0, ISAI, \"d,s,j\", MATCH_XORI, MASK_XORI, match_opcode, 0 ),\n (\"xor\", 0, ISAC, \"Cs,Cw,Ct\", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS ),\n (\"xor\", 0, ISAC, \"Cs,Ct,Cw\", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS ),\n (\"xor\", 0, ISAI, \"d,s,t\", MATCH_XOR, MASK_XOR, match_opcode, 0 ),\n (\"xor\", 0, ISAI, \"d,s,j\", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS ),\n (\"lwu\", 64, ISAI, \"d,o(s)\", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"lwu\", 64, ISAI, \"d,A\", 0, M_LWU, match_never, INSN_MACRO ),\n (\"ld\", 64, ISAC, \"d,Cn(Cc)\", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"ld\", 64, ISAC, \"Ct,Cl(Cs)\", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"ld\", 64, ISAI, \"d,o(s)\", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"ld\", 64, ISAI, \"d,A\", 0, M_LD, match_never, INSN_MACRO ),\n (\"sd\", 64, ISAC, \"CV,CN(Cc)\", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"sd\", 64, ISAC, \"Ct,Cl(Cs)\", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"sd\", 64, ISAI, \"t,q(s)\", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"sd\", 64, ISAI, \"t,A,s\", 0, M_SD, match_never, INSN_MACRO ),\n (\"sext.w\", 64, ISAC, \"d,CU\", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS ),\n (\"sext.w\", 64, ISAI, \"d,s\", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS ),\n (\"addiw\", 64, ISAC, \"d,CU,Co\", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS ),\n (\"addiw\", 64, ISAI, \"d,s,j\", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 ),\n (\"addw\", 64, ISAC, \"Cs,Cw,Ct\", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS ),\n (\"addw\", 64, ISAC, \"Cs,Ct,Cw\", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS ),\n (\"addw\", 64, ISAC, \"d,CU,Co\", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS ),\n (\"addw\", 64, ISAI, \"d,s,t\", MATCH_ADDW, MASK_ADDW, match_opcode, 0 ),\n (\"addw\", 64, ISAI, \"d,s,j\", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS ),\n (\"negw\", 64, ISAI, \"d,t\", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS ), #/* sub 0 */\n (\"slliw\", 64, ISAI, \"d,s,<\", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 ),\n (\"sllw\", 64, ISAI, \"d,s,t\", MATCH_SLLW, MASK_SLLW, match_opcode, 0 ),\n (\"sllw\", 64, ISAI, \"d,s,<\", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS ),\n (\"srliw\", 64, ISAI, \"d,s,<\", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 ),\n (\"srlw\", 64, ISAI, \"d,s,t\", MATCH_SRLW, MASK_SRLW, match_opcode, 0 ),\n (\"srlw\", 64, ISAI, \"d,s,<\", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS ),\n (\"sraiw\", 64, ISAI, \"d,s,<\", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 ),\n (\"sraw\", 64, ISAI, \"d,s,t\", MATCH_SRAW, MASK_SRAW, match_opcode, 0 ),\n (\"sraw\", 64, ISAI, \"d,s,<\", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS ),\n (\"subw\", 64, ISAC, \"Cs,Cw,Ct\", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS ),\n (\"subw\", 64, ISAI, \"d,s,t\", MATCH_SUBW, MASK_SUBW, match_opcode, 0 ),\n\n#/* Atomic memory operation instruction subset */\n (\"lr.w\", 0, ISAA, \"d,0(s)\", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"sc.w\", 0, ISAA, \"d,t,0(s)\", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoadd.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoswap.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoand.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoor.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoxor.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomax.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomaxu.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomin.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amominu.w\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"lr.w.aq\", 0, ISAA, \"d,0(s)\", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"sc.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoadd.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoswap.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoand.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoor.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoxor.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomax.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomaxu.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomin.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amominu.w.aq\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"lr.w.rl\", 0, ISAA, \"d,0(s)\", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"sc.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoadd.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoswap.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoand.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoor.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoxor.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomax.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomaxu.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomin.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amominu.w.rl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"lr.w.aqrl\", 0, ISAA, \"d,0(s)\", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"sc.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoadd.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoswap.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoand.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoor.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amoxor.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomax.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomaxu.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amomin.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"amominu.w.aqrl\", 0, ISAA, \"d,t,0(s)\", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"lr.d\", 64, ISAA , \"d,0(s)\", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"sc.d\", 64, ISAA , \"d,t,0(s)\", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoadd.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoswap.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoand.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoor.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoxor.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomax.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomaxu.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomin.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amominu.d\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"lr.d.aq\", 64, ISAA , \"d,0(s)\", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"sc.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoadd.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoswap.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoand.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoor.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoxor.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomax.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomaxu.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomin.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amominu.d.aq\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"lr.d.rl\", 64, ISAA , \"d,0(s)\", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"sc.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoadd.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoswap.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoand.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoor.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoxor.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomax.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomaxu.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomin.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amominu.d.rl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"lr.d.aqrl\", 64, ISAA , \"d,0(s)\", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"sc.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoadd.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoswap.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoand.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoor.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amoxor.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomax.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomaxu.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amomin.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"amominu.d.aqrl\", 64, ISAA , \"d,t,0(s)\", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ),\n\n#/* Multiply/Divide instruction subset */\n (\"mul\", 0, ISAM, \"d,s,t\", MATCH_MUL, MASK_MUL, match_opcode, 0 ),\n (\"mulh\", 0, ISAM, \"d,s,t\", MATCH_MULH, MASK_MULH, match_opcode, 0 ),\n (\"mulhu\", 0, ISAM, \"d,s,t\", MATCH_MULHU, MASK_MULHU, match_opcode, 0 ),\n (\"mulhsu\", 0, ISAM, \"d,s,t\", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 ),\n (\"div\", 0, ISAM, \"d,s,t\", MATCH_DIV, MASK_DIV, match_opcode, 0 ),\n (\"divu\", 0, ISAM, \"d,s,t\", MATCH_DIVU, MASK_DIVU, match_opcode, 0 ),\n (\"rem\", 0, ISAM, \"d,s,t\", MATCH_REM, MASK_REM, match_opcode, 0 ),\n (\"remu\", 0, ISAM, \"d,s,t\", MATCH_REMU, MASK_REMU, match_opcode, 0 ),\n (\"mulw\", 64, ISAM, \"d,s,t\", MATCH_MULW, MASK_MULW, match_opcode, 0 ),\n (\"divw\", 64, ISAM, \"d,s,t\", MATCH_DIVW, MASK_DIVW, match_opcode, 0 ),\n (\"divuw\", 64, ISAM, \"d,s,t\", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 ),\n (\"remw\", 64, ISAM, \"d,s,t\", MATCH_REMW, MASK_REMW, match_opcode, 0 ),\n (\"remuw\", 64, ISAM, \"d,s,t\", MATCH_REMUW, MASK_REMUW, match_opcode, 0 ),\n\n#/* Single-precision floating-point instruction subset */\n (\"frsr\", 0, ISAF, \"d\", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 ),\n (\"fssr\", 0, ISAF, \"s\", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 ),\n (\"fssr\", 0, ISAF, \"d,s\", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 ),\n (\"frcsr\", 0, ISAF, \"d\", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 ),\n (\"fscsr\", 0, ISAF, \"s\", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 ),\n (\"fscsr\", 0, ISAF, \"d,s\", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 ),\n (\"frrm\", 0, ISAF, \"d\", MATCH_FRRM, MASK_FRRM, match_opcode, 0 ),\n (\"fsrm\", 0, ISAF, \"s\", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 ),\n (\"fsrm\", 0, ISAF, \"d,s\", MATCH_FSRM, MASK_FSRM, match_opcode, 0 ),\n (\"fsrmi\", 0, ISAF, \"d,Z\", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 ),\n (\"fsrmi\", 0, ISAF, \"Z\", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 ),\n (\"frflags\", 0, ISAF, \"d\", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 ),\n (\"fsflags\", 0, ISAF, \"s\", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 ),\n (\"fsflags\", 0, ISAF, \"d,s\", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 ),\n (\"fsflagsi\", 0, ISAF, \"d,Z\", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 ),\n (\"fsflagsi\", 0, ISAF, \"Z\", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 ),\n (\"flw\", 32, ISAFC, \"D,Cm(Cc)\", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"flw\", 32, ISAFC, \"CD,Ck(Cs)\", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"flw\", 0, ISAF, \"D,o(s)\", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"flw\", 0, ISAF, \"D,A,s\", 0, M_FLW, match_never, INSN_MACRO ),\n (\"fsw\", 32, ISAFC, \"CT,CM(Cc)\", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"fsw\", 32, ISAFC, \"CD,Ck(Cs)\", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ),\n (\"fsw\", 0, ISAF, \"T,q(s)\", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"fsw\", 0, ISAF, \"T,A,s\", 0, M_FSW, match_never, INSN_MACRO ),\n\n (\"fmv.x.w\", 0, ISAF, \"d,S\", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 ),\n (\"fmv.w.x\", 0, ISAF, \"D,s\", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 ),\n\n (\"fmv.x.s\", 0, ISAF, \"d,S\", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 ),\n (\"fmv.s.x\", 0, ISAF, \"D,s\", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 ),\n\n (\"fmv.s\", 0, ISAF, \"D,U\", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fneg.s\", 0, ISAF, \"D,U\", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fabs.s\", 0, ISAF, \"D,U\", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fsgnj.s\", 0, ISAF, \"D,S,T\", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 ),\n (\"fsgnjn.s\", 0, ISAF, \"D,S,T\", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 ),\n (\"fsgnjx.s\", 0, ISAF, \"D,S,T\", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 ),\n (\"fadd.s\", 0, ISAF, \"D,S,T\", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 ),\n (\"fadd.s\", 0, ISAF, \"D,S,T,m\", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 ),\n (\"fsub.s\", 0, ISAF, \"D,S,T\", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 ),\n (\"fsub.s\", 0, ISAF, \"D,S,T,m\", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 ),\n (\"fmul.s\", 0, ISAF, \"D,S,T\", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 ),\n (\"fmul.s\", 0, ISAF, \"D,S,T,m\", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 ),\n (\"fdiv.s\", 0, ISAF, \"D,S,T\", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 ),\n (\"fdiv.s\", 0, ISAF, \"D,S,T,m\", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 ),\n (\"fsqrt.s\", 0, ISAF, \"D,S\", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 ),\n (\"fsqrt.s\", 0, ISAF, \"D,S,m\", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 ),\n (\"fmin.s\", 0, ISAF, \"D,S,T\", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 ),\n (\"fmax.s\", 0, ISAF, \"D,S,T\", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 ),\n (\"fmadd.s\", 0, ISAF, \"D,S,T,R\", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 ),\n (\"fmadd.s\", 0, ISAF, \"D,S,T,R,m\", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 ),\n (\"fnmadd.s\", 0, ISAF, \"D,S,T,R\", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 ),\n (\"fnmadd.s\", 0, ISAF, \"D,S,T,R,m\", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 ),\n (\"fmsub.s\", 0, ISAF, \"D,S,T,R\", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 ),\n (\"fmsub.s\", 0, ISAF, \"D,S,T,R,m\", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 ),\n (\"fnmsub.s\", 0, ISAF, \"D,S,T,R\", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 ),\n (\"fnmsub.s\", 0, ISAF, \"D,S,T,R,m\", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 ),\n (\"fcvt.w.s\", 0, ISAF, \"d,S\", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 ),\n (\"fcvt.w.s\", 0, ISAF, \"d,S,m\", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 ),\n (\"fcvt.wu.s\", 0, ISAF, \"d,S\", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 ),\n (\"fcvt.wu.s\", 0, ISAF, \"d,S,m\", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 ),\n (\"fcvt.s.w\", 0, ISAF, \"D,s\", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.w\", 0, ISAF, \"D,s,m\", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 ),\n (\"fcvt.s.wu\", 0, ISAF, \"D,s\", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.wu\", 0, ISAF, \"D,s,m\", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 ),\n (\"fclass.s\", 0, ISAF, \"d,S\", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 ),\n (\"feq.s\", 0, ISAF, \"d,S,T\", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 ),\n (\"flt.s\", 0, ISAF, \"d,S,T\", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 ),\n (\"fle.s\", 0, ISAF, \"d,S,T\", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 ),\n (\"fgt.s\", 0, ISAF, \"d,T,S\", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 ),\n (\"fge.s\", 0, ISAF, \"d,T,S\", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 ),\n (\"fcvt.l.s\", 64, ISAF, \"d,S\", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 ),\n (\"fcvt.l.s\", 64, ISAF, \"d,S,m\", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 ),\n (\"fcvt.lu.s\", 64, ISAF, \"d,S\", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 ),\n (\"fcvt.lu.s\", 64, ISAF, \"d,S,m\", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 ),\n (\"fcvt.s.l\", 64, ISAF, \"D,s\", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.l\", 64, ISAF, \"D,s,m\", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 ),\n (\"fcvt.s.lu\", 64, ISAF, \"D,s\", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.lu\", 64, ISAF, \"D,s,m\", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 ),\n\n#/* Double-precision floating-point instruction subset */\n (\"fld\", 0, ISADC, \"D,Cn(Cc)\", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"fld\", 0, ISADC, \"CD,Cl(Cs)\", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"fld\", 0, ISAD, \"D,o(s)\", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"fld\", 0, ISAD, \"D,A,s\", 0, M_FLD, match_never, INSN_MACRO ),\n (\"fsd\", 0, ISADC, \"CT,CN(Cc)\", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"fsd\", 0, ISADC, \"CD,Cl(Cs)\", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ),\n (\"fsd\", 0, ISAD, \"T,q(s)\", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"fsd\", 0, ISAD, \"T,A,s\", 0, M_FSD, match_never, INSN_MACRO ),\n (\"fmv.d\", 0, ISAD, \"D,U\", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fneg.d\", 0, ISAD, \"D,U\", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fabs.d\", 0, ISAD, \"D,U\", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fsgnj.d\", 0, ISAD, \"D,S,T\", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 ),\n (\"fsgnjn.d\", 0, ISAD, \"D,S,T\", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 ),\n (\"fsgnjx.d\", 0, ISAD, \"D,S,T\", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 ),\n (\"fadd.d\", 0, ISAD, \"D,S,T\", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 ),\n (\"fadd.d\", 0, ISAD, \"D,S,T,m\", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 ),\n (\"fsub.d\", 0, ISAD, \"D,S,T\", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 ),\n (\"fsub.d\", 0, ISAD, \"D,S,T,m\", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 ),\n (\"fmul.d\", 0, ISAD, \"D,S,T\", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 ),\n (\"fmul.d\", 0, ISAD, \"D,S,T,m\", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 ),\n (\"fdiv.d\", 0, ISAD, \"D,S,T\", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 ),\n (\"fdiv.d\", 0, ISAD, \"D,S,T,m\", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 ),\n (\"fsqrt.d\", 0, ISAD, \"D,S\", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 ),\n (\"fsqrt.d\", 0, ISAD, \"D,S,m\", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 ),\n (\"fmin.d\", 0, ISAD, \"D,S,T\", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 ),\n (\"fmax.d\", 0, ISAD, \"D,S,T\", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 ),\n (\"fmadd.d\", 0, ISAD, \"D,S,T,R\", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 ),\n (\"fmadd.d\", 0, ISAD, \"D,S,T,R,m\", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 ),\n (\"fnmadd.d\", 0, ISAD, \"D,S,T,R\", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 ),\n (\"fnmadd.d\", 0, ISAD, \"D,S,T,R,m\", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 ),\n (\"fmsub.d\", 0, ISAD, \"D,S,T,R\", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 ),\n (\"fmsub.d\", 0, ISAD, \"D,S,T,R,m\", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 ),\n (\"fnmsub.d\", 0, ISAD, \"D,S,T,R\", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 ),\n (\"fnmsub.d\", 0, ISAD, \"D,S,T,R,m\", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 ),\n (\"fcvt.w.d\", 0, ISAD, \"d,S\", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 ),\n (\"fcvt.w.d\", 0, ISAD, \"d,S,m\", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 ),\n (\"fcvt.wu.d\", 0, ISAD, \"d,S\", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 ),\n (\"fcvt.wu.d\", 0, ISAD, \"d,S,m\", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 ),\n (\"fcvt.d.w\", 0, ISAD, \"D,s\", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 ),\n (\"fcvt.d.wu\", 0, ISAD, \"D,s\", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 ),\n (\"fcvt.d.s\", 0, ISAD, \"D,S\", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.d\", 0, ISAD, \"D,S\", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.d\", 0, ISAD, \"D,S,m\", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 ),\n (\"fclass.d\", 0, ISAD, \"d,S\", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 ),\n (\"feq.d\", 0, ISAD, \"d,S,T\", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 ),\n (\"flt.d\", 0, ISAD, \"d,S,T\", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 ),\n (\"fle.d\", 0, ISAD, \"d,S,T\", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 ),\n (\"fgt.d\", 0, ISAD, \"d,T,S\", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 ),\n (\"fge.d\", 0, ISAD, \"d,T,S\", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 ),\n (\"fmv.x.d\", 64, ISAD, \"d,S\", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 ),\n (\"fmv.d.x\", 64, ISAD, \"D,s\", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 ),\n (\"fcvt.l.d\", 64, ISAD, \"d,S\", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 ),\n (\"fcvt.l.d\", 64, ISAD, \"d,S,m\", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 ),\n (\"fcvt.lu.d\", 64, ISAD, \"d,S\", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 ),\n (\"fcvt.lu.d\", 64, ISAD, \"d,S,m\", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 ),\n (\"fcvt.d.l\", 64, ISAD, \"D,s\", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 ),\n (\"fcvt.d.l\", 64, ISAD, \"D,s,m\", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 ),\n (\"fcvt.d.lu\", 64, ISAD, \"D,s\", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 ),\n (\"fcvt.d.lu\", 64, ISAD, \"D,s,m\", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 ),\n\n#/* Quad-precision floating-point instruction subset */\n (\"flq\", 0, ISAQ, \"D,o(s)\", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE ),\n (\"flq\", 0, ISAQ, \"D,A,s\", 0, M_FLQ, match_never, INSN_MACRO ),\n (\"fsq\", 0, ISAQ, \"T,q(s)\", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE ),\n (\"fsq\", 0, ISAQ, \"T,A,s\", 0, M_FSQ, match_never, INSN_MACRO ),\n (\"fmv.q\", 0, ISAQ, \"D,U\", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fneg.q\", 0, ISAQ, \"D,U\", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fabs.q\", 0, ISAQ, \"D,U\", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS ),\n (\"fsgnj.q\", 0, ISAQ, \"D,S,T\", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 ),\n (\"fsgnjn.q\", 0, ISAQ, \"D,S,T\", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 ),\n (\"fsgnjx.q\", 0, ISAQ, \"D,S,T\", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 ),\n (\"fadd.q\", 0, ISAQ, \"D,S,T\", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 ),\n (\"fadd.q\", 0, ISAQ, \"D,S,T,m\", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 ),\n (\"fsub.q\", 0, ISAQ, \"D,S,T\", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 ),\n (\"fsub.q\", 0, ISAQ, \"D,S,T,m\", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 ),\n (\"fmul.q\", 0, ISAQ, \"D,S,T\", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 ),\n (\"fmul.q\", 0, ISAQ, \"D,S,T,m\", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 ),\n (\"fdiv.q\", 0, ISAQ, \"D,S,T\", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 ),\n (\"fdiv.q\", 0, ISAQ, \"D,S,T,m\", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 ),\n (\"fsqrt.q\", 0, ISAQ, \"D,S\", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 ),\n (\"fsqrt.q\", 0, ISAQ, \"D,S,m\", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 ),\n (\"fmin.q\", 0, ISAQ, \"D,S,T\", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 ),\n (\"fmax.q\", 0, ISAQ, \"D,S,T\", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 ),\n (\"fmadd.q\", 0, ISAQ, \"D,S,T,R\", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 ),\n (\"fmadd.q\", 0, ISAQ, \"D,S,T,R,m\", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 ),\n (\"fnmadd.q\", 0, ISAQ, \"D,S,T,R\", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 ),\n (\"fnmadd.q\", 0, ISAQ, \"D,S,T,R,m\", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 ),\n (\"fmsub.q\", 0, ISAQ, \"D,S,T,R\", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 ),\n (\"fmsub.q\", 0, ISAQ, \"D,S,T,R,m\", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 ),\n (\"fnmsub.q\", 0, ISAQ, \"D,S,T,R\", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 ),\n (\"fnmsub.q\", 0, ISAQ, \"D,S,T,R,m\", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 ),\n (\"fcvt.w.q\", 0, ISAQ, \"d,S\", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 ),\n (\"fcvt.w.q\", 0, ISAQ, \"d,S,m\", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 ),\n (\"fcvt.wu.q\", 0, ISAQ, \"d,S\", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 ),\n (\"fcvt.wu.q\", 0, ISAQ, \"d,S,m\", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 ),\n (\"fcvt.q.w\", 0, ISAQ, \"D,s\", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 ),\n (\"fcvt.q.wu\", 0, ISAQ, \"D,s\", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 ),\n (\"fcvt.q.s\", 0, ISAQ, \"D,S\", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 ),\n (\"fcvt.q.d\", 0, ISAQ, \"D,S\", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.q\", 0, ISAQ, \"D,S\", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 ),\n (\"fcvt.s.q\", 0, ISAQ, \"D,S,m\", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 ),\n (\"fcvt.d.q\", 0, ISAQ, \"D,S\", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 ),\n (\"fcvt.d.q\", 0, ISAQ, \"D,S,m\", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 ),\n (\"fclass.q\", 0, ISAQ, \"d,S\", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 ),\n (\"feq.q\", 0, ISAQ, \"d,S,T\", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 ),\n (\"flt.q\", 0, ISAQ, \"d,S,T\", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 ),\n (\"fle.q\", 0, ISAQ, \"d,S,T\", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 ),\n (\"fgt.q\", 0, ISAQ, \"d,T,S\", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 ),\n (\"fge.q\", 0, ISAQ, \"d,T,S\", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 ),\n (\"fmv.x.q\", 64, ISAQ, \"d,S\", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 ),\n (\"fmv.q.x\", 64, ISAQ, \"D,s\", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 ),\n (\"fcvt.l.q\", 64, ISAQ, \"d,S\", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 ),\n (\"fcvt.l.q\", 64, ISAQ, \"d,S,m\", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 ),\n (\"fcvt.lu.q\", 64, ISAQ, \"d,S\", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 ),\n (\"fcvt.lu.q\", 64, ISAQ, \"d,S,m\", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 ),\n (\"fcvt.q.l\", 64, ISAQ, \"D,s\", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 ),\n (\"fcvt.q.l\", 64, ISAQ, \"D,s,m\", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 ),\n (\"fcvt.q.lu\", 64, ISAQ, \"D,s\", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 ),\n (\"fcvt.q.lu\", 64, ISAQ, \"D,s,m\", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 ),\n\n#/* Compressed instructions. */\n (\"c.unimp\", 0, ISAC, \"\", 0, 0xffff, match_opcode, 0 ),\n (\"c.ebreak\", 0, ISAC, \"\", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 ),\n (\"c.jr\", 0, ISAC, \"d\", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH ),\n (\"c.jalr\", 0, ISAC, \"d\", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR ),\n (\"c.j\", 0, ISAC, \"Ca\", MATCH_C_J, MASK_C_J, match_opcode, INSN_BRANCH ),\n (\"c.jal\", 32, ISAC, \"Ca\", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_JSR ),\n (\"c.beqz\", 0, ISAC, \"Cs,Cp\", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_CONDBRANCH ),\n (\"c.bnez\", 0, ISAC, \"Cs,Cp\", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_CONDBRANCH ),\n (\"c.lwsp\", 0, ISAC, \"d,Cm(Cc)\", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 ),\n (\"c.lw\", 0, ISAC, \"Ct,Ck(Cs)\", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"c.swsp\", 0, ISAC, \"CV,CM(Cc)\", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"c.sw\", 0, ISAC, \"Ct,Ck(Cs)\", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"c.nop\", 0, ISAC, \"\", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS ),\n (\"c.nop\", 0, ISAC, \"Cj\", MATCH_C_ADDI, MASK_C_ADDI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"c.mv\", 0, ISAC, \"d,CV\", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 ),\n (\"c.lui\", 0, ISAC, \"d,Cu\", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 ),\n (\"c.li\", 0, ISAC, \"d,Co\", MATCH_C_LI, MASK_C_LI, match_opcode, 0 ),\n (\"c.addi4spn\", 0, ISAC, \"Ct,Cc,CK\", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 ),\n (\"c.addi16sp\", 0, ISAC, \"Cc,CL\", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 ),\n (\"c.addi\", 0, ISAC, \"d,Co\", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 ),\n (\"c.add\", 0, ISAC, \"d,CV\", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 ),\n (\"c.sub\", 0, ISAC, \"Cs,Ct\", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 ),\n (\"c.and\", 0, ISAC, \"Cs,Ct\", MATCH_C_AND, MASK_C_AND, match_opcode, 0 ),\n (\"c.or\", 0, ISAC, \"Cs,Ct\", MATCH_C_OR, MASK_C_OR, match_opcode, 0 ),\n (\"c.xor\", 0, ISAC, \"Cs,Ct\", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 ),\n (\"c.slli\", 0, ISAC, \"d,C>\", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 ),\n (\"c.srli\", 0, ISAC, \"Cs,C>\", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 ),\n (\"c.srai\", 0, ISAC, \"Cs,C>\", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 ),\n (\"c.slli64\", 0, ISAC, \"d\", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 ),\n (\"c.srli64\", 0, ISAC, \"Cs\", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 ),\n (\"c.srai64\", 0, ISAC, \"Cs\", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 ),\n (\"c.andi\", 0, ISAC, \"Cs,Co\", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 ),\n (\"c.addiw\", 64, ISAC, \"d,Co\", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 ),\n (\"c.addw\", 64, ISAC, \"Cs,Ct\", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 ),\n (\"c.subw\", 64, ISAC, \"Cs,Ct\", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 ),\n (\"c.ldsp\", 64, ISAC, \"d,Cn(Cc)\", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE ),\n (\"c.ld\", 64, ISAC, \"Ct,Cl(Cs)\", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.sdsp\", 64, ISAC, \"CV,CN(Cc)\", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.sd\", 64, ISAC, \"Ct,Cl(Cs)\", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.fldsp\", 0, ISADC, \"D,Cn(Cc)\", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.fld\", 0, ISADC, \"CD,Cl(Cs)\", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.fsdsp\", 0, ISADC, \"CT,CN(Cc)\", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.fsd\", 0, ISADC, \"CD,Cl(Cs)\", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE ),\n (\"c.flwsp\", 32, ISAFC, \"D,Cm(Cc)\", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"c.flw\", 32, ISAFC, \"CD,Ck(Cs)\", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"c.fswsp\", 32, ISAFC, \"CT,CM(Cc)\", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE ),\n (\"c.fsw\", 32, ISAFC, \"CD,Ck(Cs)\", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE ),\n\n#/* Supervisor instructions */\n (\"csrr\", 0, ISAI, \"d,E\", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS ),\n (\"csrwi\", 0, ISAI, \"E,Z\", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrsi\", 0, ISAI, \"E,Z\", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrci\", 0, ISAI, \"E,Z\", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrw\", 0, ISAI, \"E,s\", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrw\", 0, ISAI, \"E,Z\", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrs\", 0, ISAI, \"E,s\", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrs\", 0, ISAI, \"E,Z\", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrc\", 0, ISAI, \"E,s\", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrc\", 0, ISAI, \"E,Z\", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS ),\n (\"csrrwi\", 0, ISAI, \"d,E,Z\", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 ),\n (\"csrrsi\", 0, ISAI, \"d,E,Z\", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 ),\n (\"csrrci\", 0, ISAI, \"d,E,Z\", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 ),\n (\"csrrw\", 0, ISAI, \"d,E,s\", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 ),\n (\"csrrw\", 0, ISAI, \"d,E,Z\", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS ),\n (\"csrrs\", 0, ISAI, \"d,E,s\", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 ),\n (\"csrrs\", 0, ISAI, \"d,E,Z\", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS ),\n (\"csrrc\", 0, ISAI, \"d,E,s\", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 ),\n (\"csrrc\", 0, ISAI, \"d,E,Z\", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS ),\n (\"uret\", 0, ISAI, \"\", MATCH_URET, MASK_URET, match_opcode, 0 ),\n (\"sret\", 0, ISAI, \"\", MATCH_SRET, MASK_SRET, match_opcode, 0 ),\n (\"hret\", 0, ISAI, \"\", MATCH_HRET, MASK_HRET, match_opcode, 0 ),\n (\"mret\", 0, ISAI, \"\", MATCH_MRET, MASK_MRET, match_opcode, 0 ),\n (\"dret\", 0, ISAI, \"\", MATCH_DRET, MASK_DRET, match_opcode, 0 ),\n (\"sfence.vm\", 0, ISAI, \"\", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 ),\n (\"sfence.vm\", 0, ISAI, \"s\", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 ),\n (\"sfence.vma\", 0, ISAI, \"\", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS ),\n (\"sfence.vma\", 0, ISAI, \"s\", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS ),\n (\"sfence.vma\", 0, ISAI, \"s,t\", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 ),\n (\"wfi\", 0, ISAI, \"\", MATCH_WFI, MASK_WFI, match_opcode, 0 )]\n\n\n\n# expanded\n# 16 xxxxxxxxxxxxxxaa != 11\n# 32 xxxxxxxxxxxbbb11 != 111\n# 48 xxxxxxxxxx011111\n# 64 xxxxxxxxx0111111\n# 80 xnnnxxxxx1111111 != 111\n# 192 x111xxxxx1111111\n\n# print(\"immI: op2031 is op2031 { local tmp:4 = op2031; export tmp; }\")\n# print(\"immS: imm is op0711 & op2531 [ imm = (op2531 << 5) | op0711; ] { local tmp:4 = zext(imm); export tmp; }\")\n# print(\"immSB: imm is op0707 & op0811 & op2530 & op3131 [ imm = (op3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11); ] { local tmp:4 = zext(imm); export tmp; }\")\n# print(\"immU: imm is op1231 [ imm = (op1231 << 12); ] { local tmp:4 = zext(imm); export tmp; }\")\n# print(\"immUJ: imm is op1219 & op2020 & op2130 & op3131 [ imm = (op3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12); ] { local tmp:4 = zext(imm); export tmp; }\")\n\n# print(\"shamt5: op2024 is op2024 { local tmp:4 = op2024; export tmp; }\")\n# print(\"shamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:4 = imm; export tmp; }\")\n\n# print(\"fmt: \\\".s\\\" is op2526=0 {}\")\n# print(\"fmt: \\\".d\\\" is op2526=1 {}\")\n# print(\"fmt: \\\".h\\\" is op2526=2 {}\")\n# print(\"fmt: \\\".q\\\" is op2526=3 {}\")\n\n\n\ndef parse_operand(op):\n dis = op.operands\n is16 = op.match & 3 != 3\n x = 0\n out = \"\"\n cons=[]\n while x < len(dis):\n if dis[x] == 'C':\n x += 1\n if dis[x] == 'a':\n out += \"cjimm\"\n cons.append(\"cjimm\")\n elif dis[x] == 'c':\n out += \"sp\"\n cons.append(\"cop0711=2\")\n cons.append(\"sp\")\n elif dis[x] == 'i':\n out += \"csimm3\"\n cons.append(\"csimm3\")\n elif dis[x] == 'o' or dis[x] == 'j':\n out += \"cimmI\"\n cons.append(\"cimmI\")\n elif dis[x] == 'k':\n out += \"clwimm\"\n cons.append(\"clwimm\")\n elif dis[x] == 'l':\n out += \"cldimm\"\n cons.append(\"cldimm\")\n elif dis[x] == 'm':\n out += \"clwspimm\"\n cons.append(\"clwspimm\")\n elif dis[x] == 'n':\n out += \"cldspimm\"\n cons.append(\"cldspimm\")\n elif dis[x] == 'p':\n out += \"cbimm\"\n cons.append(\"cbimm\")\n elif dis[x] == 's':\n out += \"cr0709s\"\n cons.append(\"cr0709s\")\n elif dis[x] == 't':\n out += \"cr0204s\"\n cons.append(\"cr0204s\")\n elif dis[x] == 'w':\n out += \"cd0709s\"\n cons.append(\"cd0709s\")\n elif dis[x] == 'x':\n out += \"cr0204s\"\n cons.append(\"cr0204s\")\n elif dis[x] == 'u' or dis[x] == 'v':\n out += \"cbigimm\"\n cons.append(\"cbigimm\")\n elif dis[x] == 'z':\n out += \"zero\"\n cons.append(\"cop0206=0\")\n cons.append(\"zero\")\n elif dis[x] == 'U':\n out += \"cr0711\"\n cons.append(\"cr0711\")\n elif dis[x] == 'V':\n out += \"cr0206\"\n cons.append(\"cr0206\")\n elif dis[x] == 'K':\n out += \"caddi4spnimm\"\n cons.append(\"caddi4spnimm\")\n elif dis[x] == 'L':\n out += \"caddi16spimm\"\n cons.append(\"caddi16spimm\")\n elif dis[x] == 'M':\n out += \"cswspimm\"\n cons.append(\"cswspimm\")\n elif dis[x] == 'N':\n out += \"csdspimm\"\n cons.append(\"csdspimm\")\n elif dis[x] == '>':\n out += \"c6imm\"\n cons.append(\"c6imm\")\n elif dis[x] == '<':\n out += \"c5imm\"\n cons.append(\"c5imm\")\n elif dis[x] == 'T':\n out += \"cfr0206\"\n cons.append(\"cfr0206\")\n elif dis[x] == 'D':\n out += \"cfr0204s\"\n cons.append(\"cfr0204s\")\n else:\n print(\"BAD C case %c\" % (dis[x]))\n print(op)\n exit(1)\n elif dis[x] in [',', '(', ')', '[', ']']:\n out += dis[x]\n elif dis[x] == '0':\n if x+1 == len(dis):\n out += \"0\"\n elif dis[x] == 'b' or dis[x] == 's':\n if is16:\n out += \"cr1519\"\n cons.append(\"cr1519\")\n else:\n out += \"r1519\"\n cons.append(\"r1519\")\n elif dis[x] == 't':\n if is16:\n out += \"cr2024\"\n cons.append(\"cr2024\")\n else:\n out += \"r2024\"\n cons.append(\"r2024\")\n elif dis[x] == 'u':\n out += \"immU\"\n cons.append(\"immU\")\n elif dis[x] == 'm':\n out += \"frm\"\n cons.append(\"frm\")\n elif dis[x] == 'P':\n out += \"pred\"\n cons.append(\"pred\")\n elif dis[x] == 'Q':\n out += \"succ\"\n cons.append(\"succ\")\n elif dis[x] == 'o':\n out += \"immI\"\n cons.append(\"immI\")\n elif dis[x] == 'j':\n out += \"immI\"\n cons.append(\"immI\")\n elif dis[x] == 'q':\n out += \"immS\"\n cons.append(\"immS\")\n elif dis[x] == 'a':\n out += \"immUJ\"\n cons.append(\"immUJ\")\n elif dis[x] == 'p':\n out += \"immSB\"\n cons.append(\"immSB\")\n elif dis[x] == 'd':\n if is16:\n out += \"cd0711\"\n cons.append(\"cd0711\")\n else:\n out += \"r0711\"\n cons.append(\"r0711\")\n elif dis[x] == 'z':\n out += \"zero\"\n cons.append(\"zero\")\n elif dis[x] == '>':\n out += \"shamt6\"\n cons.append(\"shamt6\")\n elif dis[x] == '<':\n out += \"shamt5\"\n cons.append(\"shamt5\")\n elif dis[x] == 'S' or dis[x] == 'U':\n if is16:\n out += \"cfr1519\"\n cons.append(\"cfr1519\")\n else:\n out += \"fr1519\"\n cons.append(\"fr1519\")\n elif dis[x] == 'T':\n if is16:\n out += \"cfr2024\"\n cons.append(\"cfr2024\")\n else:\n out += \"fr2024\"\n cons.append(\"fr2024\")\n elif dis[x] == 'D':\n if is16:\n out += \"cfr0711\"\n cons.append(\"cfr0711\")\n else:\n out += \"fr0711\"\n cons.append(\"fr0711\")\n elif dis[x] == 'R':\n if is16:\n out += \"cfr2731\"\n cons.append(\"cfr2731\")\n else:\n out += \"fr2731\"\n cons.append(\"fr2731\")\n elif dis[x] == 'E':\n out += \"csr\"\n cons.append(\"csr\")\n elif dis[x] == 'Z':\n if is16:\n out += \"cr1519\"\n cons.append(\"cr1519\")\n else:\n out += \"r1519\"\n cons.append(\"r1519\")\n else:\n print(\"BAD top case %c\" % (dis[x]))\n print(op)\n exit(1)\n x += 1\n # print(\"DISPLAY: %s\" % out)\n return (out, cons)\n\ndef parse_r(op):\n funct3 = (op.match >> 12) & ((1<<3) - 1)\n funct7 = (op.match >> 25) & ((1<<7) - 1)\n op.bitpattern.append(\"funct3=0x%x\" % funct3)\n op.bitpattern.append(\"funct7=0x%x\" % funct7)\n return\n\ndef parse_i(op):\n funct3 = (op.match >> 12) & ((1<<3) - 1)\n op.bitpattern.append(\"funct3=0x%x\" % funct3)\n return\n\ndef parse_s(op):\n funct3 = (op.match >> 12) & ((1<<3) - 1)\n op.bitpattern.append(\"funct3=0x%x\" % funct3)\n return\n\ndef parse_u(op):\n return\n\ndef parse_b(op):\n funct3 = (op.match >> 12) & ((1<<3) - 1)\n op.bitpattern.append(\"funct3=0x%x\" % funct3)\n return\n\ndef parse_j(op):\n return\n\ndef parse_misc_mem(op):\n fm = (op.match >> 28) & ((1<<4) - 1)\n funct3 = (op.match >> 12) & ((1<<3) - 1)\n op.bitpattern.append(\"funct3=0x%x\" % funct3)\n op.bitpattern.append(\"fm=0x%x\" % fm)\n return\n\n\ndef parse_CR(op, rv):\n return\n\ndef parse_CI(op, rv):\n x = (op.match >> 13) & 7\n if op.bitpattern.count(\"clwspimm\") == 1:\n op.bitpattern.remove(\"clwspimm\")\n if x == 2 or (x == 3 and rv == 32):\n op.display = op.display.replace(\"clwspimm\", \"clwspimm54276\")\n op.bitpattern.append(\"clwspimm54276\")\n elif x == 1 and rv == 128:\n op.display = op.display.replace(\"clwspimm\", \"clwspimm5496\")\n op.bitpattern.append(\"clwspimm5496\")\n elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)):\n op.display = op.display.replace(\"clwspimm\", \"clwspimm54386\")\n op.bitpattern.append(\"clwspimm54386\")\n if op.bitpattern.count(\"cldspimm\") == 1:\n op.bitpattern.remove(\"cldspimm\")\n if x == 2 or (x == 3 and rv == 32):\n op.display = op.display.replace(\"cldspimm\", \"cldspimm54276\")\n op.bitpattern.append(\"cldspimm54276\")\n elif x == 1 and rv == 128:\n op.display = op.display.replace(\"cldspimm\", \"cldspimm5496\")\n op.bitpattern.append(\"cldspimm5496\")\n elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)):\n op.display = op.display.replace(\"cldspimm\", \"cldspimm54386\")\n op.bitpattern.append(\"cldspimm54386\")\n return\n\ndef parse_CSS(op, rv):\n x = (op.match >> 13) & 7\n if op.bitpattern.count(\"cswspimm\") == 1:\n op.bitpattern.remove(\"cswspimm\")\n if (x == 5 and (rv == 32 or rv == 64)) or (x == 7 and (rv == 128 or rv == 64)):\n op.display = op.display.replace(\"cswspimm\", \"cswspimm5386\")\n op.bitpattern.append(\"cswspimm5386\")\n elif (x == 5 and rv == 128):\n op.display = op.display.replace(\"cswspimm\", \"cswspimm5496\")\n op.bitpattern.append(\"cswspimm5496\")\n elif (x == 7 and rv == 32) or (x == 6):\n op.display = op.display.replace(\"cswspimm\", \"cswspimm5276\")\n op.bitpattern.append(\"cswspimm5276\")\n if op.bitpattern.count(\"csdspimm\") == 1:\n op.bitpattern.remove(\"csdspimm\")\n if (x == 5 and (rv == 32 or rv == 64)) or (x == 7 and (rv == 128 or rv == 64)):\n op.display = op.display.replace(\"csdspimm\", \"csdspimm5386\")\n op.bitpattern.append(\"csdspimm5386\")\n elif (x == 5 and rv == 128):\n op.display = op.display.replace(\"csdspimm\", \"csdspimm5496\")\n op.bitpattern.append(\"csdspimm5496\")\n elif (x == 7 and rv == 32) or (x == 6):\n op.display = op.display.replace(\"csdspimm\", \"csdspimm5276\")\n op.bitpattern.append(\"csdspimm5276\")\n return\n\ndef parse_CIW(op, rv):\n return\n\ndef parse_CL(op, rv):\n x = (op.match >> 13) & 7\n if op.bitpattern.count(\"cldspimm\") == 1:\n op.bitpattern.remove(\"cldspimm\")\n if x == 2 or (x == 3 and rv == 32):\n op.display = op.display.replace(\"cldspimm\", \"cldspimm54276\")\n op.bitpattern.append(\"cldspimm54276\")\n elif x == 1 and rv == 128:\n op.display = op.display.replace(\"cldspimm\", \"cldspimm5496\")\n op.bitpattern.append(\"cldspimm5496\")\n elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)):\n op.display = op.display.replace(\"cldspimm\", \"cldspimm54386\")\n op.bitpattern.append(\"cldspimm54386\")\n if op.bitpattern.count(\"clwspimm\") == 1:\n op.bitpattern.remove(\"clwspimm\")\n if x == 2 or (x == 3 and rv == 32):\n op.display = op.display.replace(\"clwspimm\", \"clwspimm54276\")\n op.bitpattern.append(\"clwspimm54276\")\n elif x == 1 and rv == 128:\n op.display = op.display.replace(\"clwspimm\", \"clwspimm5496\")\n op.bitpattern.append(\"clwspimm5496\")\n elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)):\n op.display = op.display.replace(\"clwspimm\", \"clwspimm54386\")\n op.bitpattern.append(\"clwspimm54386\")\n if op.bitpattern.count(\"cldimm\") == 1:\n op.bitpattern.remove(\"cldimm\")\n if None == rv:\n op.display = op.display.replace(\"cldimm\", \"cldimm5326\")\n op.bitpattern.append(\"cldimm5326\")\n elif 32 == rv and (x == 3 or x == 7):\n op.display = op.display.replace(\"cldimm\", \"cldimm5326\")\n op.bitpattern.append(\"cldimm5326\")\n elif (32 == rv or 64 == rv) and (x == 1 or x == 5):\n op.display = op.display.replace(\"cldimm\", \"cldimm5376\")\n op.bitpattern.append(\"cldimm5376\")\n elif (128 == rv or 64 == rv) and (x == 3 or x == 7):\n op.display = op.display.replace(\"cldimm\", \"cldimm5376\")\n op.bitpattern.append(\"cldimm5376\")\n elif 128 == rv and (x == 1 or x == 7):\n op.display = op.display.replace(\"cldimm\", \"cldimm54876\")\n op.bitpattern.append(\"cldimm54876\")\n else:\n print(\"BAD CL rv %r\" % (rv))\n exit(1)\n if op.bitpattern.count(\"clwimm\") == 1:\n op.bitpattern.remove(\"clwimm\")\n if None == rv:\n op.display = op.display.replace(\"clwimm\", \"clwimm5326\")\n op.bitpattern.append(\"clwimm5326\")\n elif 32 == rv and (x == 3 or x == 7):\n op.display = op.display.replace(\"clwimm\", \"clwimm5326\")\n op.bitpattern.append(\"clwimm5326\")\n elif (32 == rv or 64 == rv) and (x == 1 or x == 5):\n op.display = op.display.replace(\"clwimm\", \"clwimm5376\")\n op.bitpattern.append(\"clwimm5376\")\n elif (128 == rv or 64 == rv) and (x == 3 or x == 7):\n op.display = op.display.replace(\"clwimm\", \"clwimm5376\")\n op.bitpattern.append(\"clwimm5376\")\n elif 128 == rv and (x == 1 or x == 7):\n op.display = op.display.replace(\"clwimm\", \"clwimm54876\")\n op.bitpattern.append(\"clwimm54876\")\n else:\n print(\"BAD CL rv %r\" % (rv))\n exit(1)\n return\n\ndef parse_CS(op, rv):\n x = (op.match >> 13) & 7\n if op.bitpattern.count(\"clwimm\") == 1:\n op.bitpattern.remove(\"clwimm\")\n if None == rv:\n op.display = op.display.replace(\"clwimm\", \"clwimm5326\")\n op.bitpattern.append(\"clwimm5326\")\n elif 32 == rv and (x == 3 or x == 7):\n op.display = op.display.replace(\"clwimm\", \"clwimm5326\")\n op.bitpattern.append(\"clwimm5326\")\n elif (32 == rv or 64 == rv) and (x == 1 or x == 5):\n op.display = op.display.replace(\"clwimm\", \"clwimm5376\")\n op.bitpattern.append(\"clwimm5376\")\n elif (128 == rv or 64 == rv) and (x == 3 or x == 7):\n op.display = op.display.replace(\"clwimm\", \"clwimm5376\")\n op.bitpattern.append(\"clwimm5376\")\n elif 128 == rv and (x == 1 or x == 7):\n op.display = op.display.replace(\"clwimm\", \"clwimm54876\")\n op.bitpattern.append(\"clwimm54876\")\n else:\n print(\"BAD CL rv %r\" % (rv))\n exit(1)\n if op.bitpattern.count(\"cldimm\") == 1:\n op.bitpattern.remove(\"cldimm\")\n if None == rv:\n op.display = op.display.replace(\"cldimm\", \"cldimm5326\")\n op.bitpattern.append(\"cldimm5326\")\n elif 32 == rv and (x == 3 or x == 7):\n op.display = op.display.replace(\"cldimm\", \"cldimm5326\")\n op.bitpattern.append(\"cldimm5326\")\n elif (32 == rv or 64 == rv) and (x == 1 or x == 5):\n op.display = op.display.replace(\"cldimm\", \"cldimm5376\")\n op.bitpattern.append(\"cldimm5376\")\n elif (128 == rv or 64 == rv) and (x == 3 or x == 7):\n op.display = op.display.replace(\"cldimm\", \"cldimm5376\")\n op.bitpattern.append(\"cldimm5376\")\n elif 128 == rv and (x == 1 or x == 7):\n op.display = op.display.replace(\"cldimm\", \"cldimm54876\")\n op.bitpattern.append(\"cldimm54876\")\n else:\n print(\"BAD CL rv %r\" % (rv))\n exit(1)\n return\n\ndef parse_CA(op, rv):\n return\n\ndef parse_CB(op, rv):\n return\n\ndef parse_CJ(op, rv):\n return\n\n\ndef opcode_map_c(op):\n '''\n CR |funct4 | cr0711 | cr0206 | op |\n CI |funct3 | cop1212 | cr0711 | cop0206 | op |\n CSS |funct3 | cop0712 | cr0206 | op |\n CIW |funct3 | cop0512 | cr0204s | op |\n CL |funct3 | cop1012 | cs0709s | cop0506 | cr0204s | op |\n CS |funct3 | cop1012 | cr0709s | cop0506 | cr0204s | op |\n CA |funct6 | cr0709s | funct2 | cr0204s | op |\n CB |funct3 | off1012 | cr0709s | off0206 | op |\n CJ |funct3 | target | op |\n '''\n x = (op.match >> 13) & 7\n y = op.match & 3\n op.bitpattern.append(\"cop0001=0x%x\" % y)\n op.bitpattern.append(\"cop1315=0x%x\" % x)\n # print(\"CMAP: RV32, RV64, RV128\")\n if x == 0 and y == 0:\n # ADDI4SPN\n parse_CIW(op, None)\n elif x == 0 and y == 1:\n # ADDI\n parse_CI(op, None)\n elif x == 0 and y == 2:\n # SLLI\n parse_CI(op, None)\n elif x == 1 and y == 0:\n # FLD FLD LQ\n # print(\"CMAP: FLD FLD LQ\")\n if op.name.find(\"fld\") >= 0:\n print(\"#TODO 32 64\")\n parse_CL(op, 32)\n parse_CL(op, 64)\n elif op.name.find(\"lq\") >= 0: parse_CL(op, 128)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 1 and y == 1:\n # JAL ADDIW ADDIW\n # print(\"CMAP: JAL ADDIW ADDIW\")\n if op.name.find(\"jal\") >= 0: parse_CJ(op, 32)\n elif op.name.find(\"addiw\") >= 0:\n print(\"#TODO 32 64\")\n parse_CI(op, 64)\n parse_CI(op, 128)\n elif op.name == \"sext.w\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"addw\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 1 and y == 2:\n # LW LI LWSP\n # print(\"CMAP: FLDSP FLDSP LQSP\")\n if op.name.find(\"fldsp\") >= 0:\n print(\"#TODO 32 64\")\n parse_CI(op, 32)\n parse_CI(op, 64)\n elif op.name.find(\"lqsp\") >= 0: parse_CI(op, 128)\n elif op.name == \"fld\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 2 and y == 0:\n # FW\n parse_CL(op, None)\n elif x == 2 and y == 1:\n # LI\n # print(\"CMAP: LI\")\n if op.name.find(\"li\") >= 0: parse_CI(op, None)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 2 and y == 2:\n # LWSP\n parse_CI(op, None)\n elif x == 3 and y == 0:\n # FLW LD LD\n # print(\"CMAP: FLW LD LD\")\n if op.name.find(\"flw\") >= 0: parse_CL(op, 32)\n elif op.name.find(\"ld\") >= 0:\n print(\"#TODO 64 128\")\n parse_CL(op, 64)\n parse_CL(op, 128)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 3 and y == 1:\n # LUI ADDI16SP\n # print(\"CMAP: LUI ADDI16SP\")\n if op.name.find(\"lui\") >= 0: parse_CI(op, None)\n elif op.name.find(\"addi16sp\") >= 0: parse_CJ(op, None)\n elif op.name == \"li\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"addi\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"add\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 3 and y == 2:\n # FLWSP LDSP LDSP\n # print(\"CMAP: FLWSP LDSP LDSP\")\n if op.name.find(\"flwsp\") >= 0: parse_CI(op, 32)\n elif op.name.find(\"ldsp\") >= 0:\n print(\"#TODO 64 128\")\n parse_CI(op, 64)\n parse_CI(op, 128)\n elif op.name == \"ld\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"flw\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 4 and y == 0:\n # RESERVED\n # print(\"CMAP: RESERVED C 3 0\")\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif x == 4 and y == 1:\n # MISC-ALU\n # print(\"CMAP: MISC-ALU\")\n if (op.match >> 10) & 3 == 3:\n parse_CA(op, None)\n else:\n parse_CB(op, None)\n pass\n elif x == 4 and y == 2:\n # JR JALR MV ADD\n # print(\"CMAP: JR JALR MV ADD\")\n if op.name.find(\"jr\") >= 0: parse_CI(op, None)\n elif op.name.find(\"jalr\") >= 0: parse_CI(op, None)\n elif op.name.find(\"mv\") >= 0: parse_CR(op, None)\n elif op.name.find(\"add\") >= 0: parse_CR(op, None)\n elif op.name == \"ebreak\": parse_CJ(op, None)\n elif op.name == \"c.ebreak\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"ret\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"move\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 5 and y == 0:\n # FSD FSD SQ\n # print(\"CMAP: FSD FSD SQ\")\n if op.name.find(\"fsd\") >= 0:\n print(\"#TODO 32 64\")\n parse_CS(op, 32)\n parse_CS(op, 64)\n elif op.name.find(\"sq\") >= 0: parse_CS(op, 128)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 5 and y == 1:\n # J\n # print(\"CMAP: J\")\n if op.name.find(\"j\") >= 0: parse_CJ(op, None)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 5 and y == 2:\n # FSDSP FSDSP SQSP\n # print(\"CMAP: FSDSP FSDSP SQSP\")\n if op.name.find(\"fsdsp\") >= 0:\n print(\"#TODO 32 64\")\n parse_CSS(op, 32)\n parse_CSS(op, 64)\n elif op.name.find(\"sqsp\") >= 0: parse_CSS(op, 128)\n elif op.name == \"fsd\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 6 and y == 0:\n # SW\n # print(\"CMAP: SW\")\n if op.name.find(\"sw\") >= 0: parse_CS(op, None)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 6 and y == 1:\n # BEQZ\n parse_CB(op, None)\n elif x == 6 and y == 2:\n # SWSP\n parse_CSS(op, None)\n elif x == 7 and y == 0:\n # FSW SD SD\n # print(\"CMAP: FSW SD SD\")\n if op.name.find(\"fsw\") >= 0: parse_CS(op, 32)\n elif op.name.find(\"sd\") >= 0:\n print(\"#TODO 64 128\")\n parse_CS(op, 64)\n parse_CS(op, 128)\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n elif x == 7 and y == 1:\n # BNEZ\n parse_CB(op, None)\n elif x == 7 and y == 2:\n # \n # print(\"CMAP: FSWSP SDSP SDSP\")\n if op.name.find(\"fswsp\") >= 0: parse_CSS(op, 32)\n elif op.name.find(\"sdsp\") >= 0:\n print(\"#TODO 64 128\")\n parse_CSS(op, 64)\n parse_CSS(op, 128)\n elif op.name == \"sd\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n elif op.name == \"fsw\":\n print(\"#TODO %s %s\" % (op.display, ' & '.join(op.bitpattern)))\n pass\n else:\n print(\"CMAP -- %s\" % (op.name))\n print(op)\n exit(1)\n pass\n else:\n print(\"CBAD X %x Y %x\" % (x, y))\n print(op)\n exit(1)\n\n\ndef opcode_map(op):\n x = (op.match >> 2) & 7\n y = (op.match >> 5) & 3\n op.bitpattern.append(\"op0001=0x3\")\n op.bitpattern.append(\"op0204=0x%x\" % x)\n op.bitpattern.append(\"op0506=0x%x\" % y)\n if x == 0:\n if y == 0:\n # LOAD\n # print(\"MAP: LOAD\")\n parse_i(op)\n pass\n elif y == 1:\n # STORE\n # print(\"MAP: STORE\")\n parse_s(op)\n pass\n elif y == 2:\n # MADD\n # print(\"MAP: MADD\")\n parse_r(op)\n pass\n elif y == 3:\n # BRANCH\n # print(\"MAP: BRANCH\")\n parse_b(op)\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n elif x == 1:\n if y == 0:\n # LOAD-FP\n # print(\"MAP: LOAD-FP\")\n parse_i(op)\n pass\n elif y == 1:\n # STORE-FP\n # print(\"MAP: STORE-FP\")\n parse_s(op)\n pass\n elif y == 2:\n # MSUB\n # print(\"MAP: MSUB\")\n parse_r(op)\n pass\n elif y == 3:\n # JALR\n # print(\"MAP: JALR\")\n parse_i(op)\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n elif x == 2:\n if y == 0:\n # CUSTOM0\n print(\"MAP: CUSTOM0\")\n pass\n elif y == 1:\n # CUSTOM1\n print(\"MAP: CUSTOM1\")\n pass\n elif y == 2:\n # NMSUB\n # print(\"MAP: NMSUB\")\n parse_r(op)\n pass\n elif y == 3:\n # RESERVED\n print(\"MAP: RESERVED 2 3\")\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n elif x == 3:\n if y == 0:\n # MISC-MEM\n # print(\"MAP: MISC-MEM\")\n parse_misc_mem(op)\n pass\n elif y == 1:\n # AMO\n # print(\"MAP: AMO\")\n parse_r(op)\n pass\n elif y == 2:\n # NMADD\n # print(\"MAP: NMADD\")\n parse_r(op)\n pass\n elif y == 3:\n # JAL\n # print(\"MAP: JAL\")\n parse_j(op)\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n elif x == 4:\n if y == 0:\n # OP-IMM\n # print(\"MAP: OP-IMM\")\n parse_i(op)\n elif y == 1:\n # OP\n # print(\"MAP: OP\")\n parse_r(op)\n pass\n elif y == 2:\n # OP-FP\n # print(\"MAP: OP-FP\")\n parse_r(op)\n pass\n elif y == 3:\n # SYSTEM\n # print(\"MAP: SYSTEM\")\n parse_i(op)\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n elif x == 5:\n if y == 0:\n # AUIPC\n # print(\"MAP: AUIPC\")\n parse_u(op)\n pass\n elif y == 1:\n # LUI\n # print(\"MAP: LUI\")\n parse_u(op)\n pass\n elif y == 2:\n # RESERVED\n print(\"MAP: RESERVED 5 2\")\n pass\n elif y == 3:\n # RESERVED\n print(\"MAP: RESERVED 5 3\")\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n elif x == 6:\n if y == 0:\n # OP-IMM-32\n # print(\"MAP: OP-IMM-32\")\n parse_i(op)\n pass\n elif y == 1:\n # OP-32\n # print(\"MAP: OP-32\")\n parse_r(op)\n pass\n elif y == 2:\n # CUSTOM2\n print(\"MAP: CUSTOM2\")\n pass\n elif y == 3:\n # CUSTOM3\n print(\"MAP: CUSTOM3\")\n pass\n else:\n print(\"BAD Y %x X %x\" % (y,x))\n print(op)\n exit(1)\n else:\n print(\"BAD X %x\" % (x))\n print(op)\n exit(1)\n\n\n\ndef find_gaps(op):\n \"\"\"Account for all the bits in the pattern\n dummy style just added as they got added\"\"\"\n gap = {\n 'op0001': (0,1),\n 'op0204': (2,4),\n 'op0506': (5,6),\n 'op0707': (7,7),\n 'op0711': (7,11),\n 'r0711': (7,11),\n 'fr0711': (7,11),\n 'op0811': (8,11),\n 'op1214': (12,14),\n 'funct3': (12,14),\n 'op1219': (12,19),\n 'op1231': (12,31),\n 'sop1231': (12,31),\n 'r1519': (15,19),\n 'fr1519': (15,19),\n 'fd1519': (15,19),\n 'op1527': (15,27),\n 'op1531': (15,31),\n 'op2020': (20,20),\n 'succ': (20,23),\n 'op2024': (20,24),\n 'r2024': (20,24),\n 'fr2024': (20,24),\n 'op2031': (20,31),\n 'sop2031': (20,31),\n 'op2130': (21,30),\n 'pred': (24,27),\n 'op2525': (25,25),\n 'op2526': (25,26),\n 'op2530': (25,30),\n 'op2531': (25,31),\n 'sop2531': (25,31),\n 'op2631': (26,31),\n 'funct7': (25,31),\n 'op2731': (27,31),\n 'r2731': (27,31),\n 'fr2731': (27,31),\n 'fm': (28,31),\n 'sop3131': (31,31),\n 'cop0001': (0,1),\n 'cop0202': (2,2),\n 'cop0203': (2,3),\n 'cop0204': (2,4),\n 'cr0204s': (2,4),\n 'cfr0204s': (2,4),\n 'cop0205': (2,5),\n 'cop0206': (2,6),\n 'cr0206': (2,6),\n 'cfr0206': (2,6),\n 'cop0212': (2,12),\n 'cop0304': (3,4),\n 'cop0305': (3,5),\n 'cop0406': (4,6),\n 'cop0505': (5,5),\n 'cop0506': (5,6),\n 'cop0512': (5,12),\n 'cop0606': (6,6),\n 'cop0707': (7,7),\n 'cop0708': (7,8),\n 'cop0709': (7,9),\n 'cr0709s': (7,9),\n 'cd0709s': (7,9),\n 'cfr0709s': (7,9),\n 'cop0710': (7,10),\n 'cop0711': (7,11),\n 'cr0711': (7,11),\n 'cd0711': (7,11),\n 'cfr0711': (7,11),\n 'cop0712': (7,12),\n 'cop0808': (8,8),\n 'cop0910': (9,10),\n 'cop0912': (9,12),\n 'cop1010': (10,10),\n 'cop1011': (10,11),\n 'cop1012': (10,12),\n 'cop1111': (11,11),\n 'cop1112': (11,12),\n 'cop1212': (12,12),\n 'scop1212': (12,12),\n 'cop1315': (13,15),\n 'immI': \"sop2031\",\n 'immS': \"op0711 & sop2531\",\n 'immSB': \"op0707 & op0811 & op2530 & sop3131\",\n 'immU': \"sop1231\",\n 'immUJ': \"op1219 & op2020 & op2130 & sop3131\",\n 'shamt5': \"op2024\",\n 'shamt6': \"op2024 & op2525\",\n 'frm': \"op1214=0\",\n 'frm': \"op1214=1\",\n 'frm': \"op1214=2\",\n 'frm': \"op1214=3\",\n 'frm': \"op1214=4\",\n 'frm': \"op1214=7\",\n 'fmt': \"op2526=0\",\n 'fmt': \"op2526=1\",\n 'fmt': \"op2526=2\",\n 'fmt': \"op2526=3\",\n 'csr1': \"op2031\",\n 'csr2': \"op2031\",\n 'csr4': \"op2031\",\n 'csr8': \"op2031\",\n 'csr': \"op2031\",\n 'cimmI': \"cop1212 & cop0204 & cop0506\",\n 'cbimm': \"scop1212 & cop1011 & cop0506 & cop0304 & cop0202\",\n 'cjimm': \"scop1212 & cop1111 & cop0910 & cop0808 & cop0707 & cop0606 & cop0305 & cop0202\",\n 'c6imm': \"cop1212 & cop0206\",\n 'cbigimm': \"scop1212 & cop0206\",\n 'caddi4spnimm': \"cop1112 & cop0710 & cop0606 & cop0505\",\n 'caddi16spimm': \"scop1212 & cop0606 & cop0505 & cop0304 & cop0202\",\n 'cldimm': \"cop1012 & cop0506\",\n 'cldimm5376': \"cop1012 & cop0506\",\n 'cldimm54876': \"cop1112 & cop1010 & cop0506\",\n 'cldimm5326': \"cop1012 & cop0606 & cop0505\",\n 'clwimm': \"cop1012 & cop0506\",\n 'clwimm5376': \"cop1012 & cop0506\",\n 'clwimm54876': \"cop1112 & cop1010 & cop0506\",\n 'clwimm5326': \"cop1012 & cop0606 & cop0505\",\n 'cldspimm': \"cop1212 & cop0506 & cop0204\",\n 'cldspimm54386': \"cop1212 & cop0506 & cop0204\",\n 'cldspimm5496': \"cop1212 & cop0606 & cop0205\",\n 'cldspimm54276': \"cop1212 & cop0406 & cop0203\",\n 'clwspimm': \"cop1212 & cop0506 & cop0204\",\n 'clwspimm54386': \"cop1212 & cop0506 & cop0204\",\n 'clwspimm5496': \"cop1212 & cop0606 & cop0205\",\n 'clwspimm54276': \"cop1212 & cop0406 & cop0203\",\n 'csdspimm': \"cop0709 & cop1012\",\n 'csdspimm5386': \"cop0709 & cop1012\",\n 'csdspimm5496': \"cop0710 & cop1112\",\n 'csdspimm5276': \"cop0708 & cop0912\",\n 'cswspimm': \"cop0709 & cop1012\",\n 'cswspimm5386': \"cop0709 & cop1012\",\n 'cswspimm5496': \"cop0710 & cop1112\",\n 'cswspimm5276': \"cop0708 & cop0912\",\n 'sp': None,\n 'zero': None\n }\n pattern = 0x0\n for x in op.bitpattern:\n x = x.split('=')[0]\n if x not in gap.keys():\n print(\"GAP: %r\" % x)\n exit(1)\n x = gap[x]\n if isinstance(x, str):\n y = x.split('&')\n for _ in y:\n w = gap[_.strip().split('=')[0]]\n pattern |= (((1 << (w[1] - w[0] + 1)) - 1) << w[0])\n if isinstance(x, tuple):\n pattern |= (((1 << (x[1] - x[0] + 1)) - 1) << x[0])\n # print(\"# %s 10987654321098765432109876543210\" % (op.name))\n # print(\"# %s %s\" % (op.name, '{:032b}'.format(pattern)))\n z = '{:032b}'.format(pattern)[::-1]\n z0 = '{:032b}'.format(op.match)[::-1]\n z1 = '{:032b}'.format(op.mask)[::-1]\n # print(\"# %s %s\" % (op.name, '{:032b}'.format(op.match)))\n # print(\"# %s %s\" % (op.name, '{:032b}'.format(op.mask)))\n x = 0\n y = 32 if op.match & 3 == 3 else 16\n while x < y:\n start = z.find('0', x)\n if start > 0 and start < y:\n # print(\"# START %d %d %d\" % (x, start, y))\n end = z.find('1', start)\n if end < 0:\n end = y\n # print(\"# chunk %d - %d (%d) \" % (start, end - 1, x))\n t0 = z1[start:end]\n # print(\"# THING %s %s\" % (t0, z1))\n if t0.find('0') > 0:\n print(\"damnit %s\" % (z1[start:end]))\n exit(1)\n t0 = int(z0[start:end][::-1], 2)\n t1 = int(z1[start:end][::-1], 2)\n # print(\"# %d %d\" % (t0, t1))\n if 16 == y:\n bp = \"cop%02d%02d=0x%x\" % (start, end - 1, t0 & t1)\n else:\n bp = \"op%02d%02d=0x%x\" % (start, end - 1, t0 & t1)\n # print(\"# BP = %s \" % bp)\n op.bitpattern.append(bp)\n x = end + 1\n \n else:\n # print(\"#END 1\")\n break\n \n\ndef parse():\n sorted_opcodes = sorted(opcodes, key=lambda x: x[0])\n for op in sorted_opcodes:\n size = 0\n op = OpCode(op)\n if op.xlen:\n print(\"@if defined(RISCV%d)\" % (op.xlen))\n if INSN_MACRO == op.pinfo:\n print(\"#TODO MACRO\")\n print(\"# %s\" % op)\n if op.xlen:\n print(\"@endif\")\n print(\"\")\n continue\n if INSN_ALIAS & op.pinfo != 0:\n print(\"#TODO ALIAS\")\n print(\"# %s\" % op)\n op.display, op.bitpattern = parse_operand(op)\n op.bitpattern = list(set(op.bitpattern))\n if op.match & 3 == 3:\n opcode_map(op)\n else:\n opcode_map_c(op)\n find_gaps(op)\n if INSN_ALIAS & op.pinfo != 0:\n print(\"#:%s %s is %s\\n#{\\n#}\" % (op.name, op.display, ' & '.join(op.bitpattern)))\n else:\n print(\":%s %s is %s\\n{\\n}\" % (op.name, op.display, ' & '.join(op.bitpattern)))\n if op.xlen:\n print(\"@endif\")\n print(\"\")\n return\n\n\ndef make_unique():\n sorted_opcodes = sorted(opcodes, key=lambda x: x[0])\n for opX in sorted_opcodes:\n print(\"-------------------------\")\n opX = OpCode(opX)\n print(\"X: %s\" % (opX))\n for opY in sorted_opcodes:\n opY = OpCode(opY)\n if opY == opX:\n continue\n if opX.mask != opY.mask:\n continue\n if opX.match != opY.match:\n continue\n if opX.xlen != opY.xlen:\n continue\n print(\"Y: %s\" % (opY))\n\nif __name__ == \"__main__\":\n parse()\n # make_unique()\n\n" }, { "path": "pypcode/processors/Sparc/data/languages/Sparc.dwarf", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Sparc/data/languages/Sparc.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9.ldefs", "content": "\n\n\n \n Sparc V9 32-bit\n \n \n \n \n \n \n \n Sparc V9 64-bit\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9.sinc", "content": "# SLA specification file for SPARC/64\n\ndefine endian=big;\n\ndefine alignment=4;\n\ndefine space ram type=ram_space size=$(SIZE) default;\ndefine space register type=register_space size=4;\n\ndefine register offset=0 size=$(SIZE) [\n\tg0 g1 g2 g3 g4 g5 g6 g7\n\to0 o1 o2 o3 o4 o5 sp o7\n\tl0 l1 l2 l3 l4 l5 l6 l7\n\ti0 i1 i2 i3 i4 i5 fp i7\n]; \n\n# these are save locations for implementing register windows\n#\ndefine register offset=0x500 size=$(SIZE) [\n\ts_l0 s_l1 s_l2 s_l3 s_l4 s_l5 s_l6 s_l7\n\ts_i0 s_i1 s_i2 s_i3 s_i4 s_i5 s_fp s_i7\n];\n\ndefine register offset=0x1000 size=$(SIZE) [ PC nPC _ TICK Y CCR _ PCR PIC GSR SOFTINT_SET SOFTINT_CLR SOFTINT TICK_CMPR STICK STICK_CMPR ];\n\ndefine register offset=0x1100 size=$(SIZE) [\n\tasr7 asr8 asr9 asr10 asr11 asr12 asr13 asr14 asr15\n\tasr16 asr17 asr18 asr19 asr20 asr21 asr22 asr23\n\tasr24 asr25 asr26 asr27 asr28 asr29 asr30 asr31\n];\n \ndefine register offset=0x3000 size=1 [ x_nf x_zf x_vf x_cf i_nf i_zf i_vf i_cf ];\n\ndefine register offset=0x4000 size=1 [ ASI ];\ndefine register offset=0x4008 size=1 [ FPRS ];\n\ndefine register offset=0x5000 size=$(SIZE) [ fsr ];\n#fcc0 is bits 10 and 11 of fsr\n#fcc1 is bits 32 and 33 of fsr (64 bit only)\n#fcc2 is bits 34 and 35 of fsr (64 bit only)\n#fcc3 is bits 36 and 37 of fsr (64 bit only)\n#model these as separate 1-byte varnodes\ndefine register offset=0x5008 size=1 [ fcc0 fcc1 fcc2 fcc3 ];\ndefine register offset=0x5010 size=1 [ didrestore ];\ndefine register offset=0x5020 size=1 [ DECOMPILE_MODE ]; # Fake register\n\n\ndefine register offset=0x6000 size=$(SIZE) [\n\tTPC1 TPC2 TPC3 TPC4\n\tTNPC1 TNPC2 TNPC3 TNPC4\n\tTSTATE1 TSTATE2 TSTATE3 TSTATE4\n\tTT1 TT2 TT3 TT4\n\tTCK TBA PSTATE TL\n\tPIL CWP CANSAVE CANRESTORE CLEANWIN\n\tOTHERWIN WSTATE FQ VER GL\n];\n\ndefine register offset=0x7000 size=$(SIZE) [\n\tHPSTATE1 HPSTATE2 HPSTATE3 HPSTATE4\n\tHTSTATE1 HTSTATE2 HTSTATE3 HTSTATE4\n\tRESV2_1 RESV2_2 RESV2_3 RESV2_4\n\tHINTP1 HINTP2 HINTP3 HINTP4\n\tRESV4_1 RESV4_2 RESV4_3 RESV4_4\n\tHTBA1 HTBA2 HTBA3 HTBA4\n\tHVER1 HVER2 HVER3 HVER4\n# TODO: actually RESV 6 - 29 registers...\n\tRESV30_1 RESV30_2 RESV30_3 RESV30_4\n\tHSTICK_CMPR1 HSTICK_CMPR2 HSTICK_CMPR3 HSTICK_CMPR4\n];\n\n# A window is 24 registers (96 or 192 bytes), most processors have 7 or 8. (g0->g7,o0->o7,l0->o7,i0->i7)\n# When the window is overflowed the data must be purged to some backup memory, via user \n# supplied function attached to a signal handler.\n# When the window is underflowed the data must be read from some backup memory, via user\n# supplied function attached to a signal handler.\n\n# There are 2 basic strategies we figured for this.\n# One, create a bank of register space and read and write to it in a way that simulates \n# how the sparc would really work, but the symbolic names become indexes.\n# Two, save and restore logic does all the work.\n\n# window index is ((CWP+1)%NWINDOWS)\n# CWP is an index from 0 to N of the windows.\n# Size of CWP is implementation dependent (must be > 5 bits).\n\n# inputs i0 i1 i2 i3 i4 i5 fp i7\n# locals l0 l1 l2 l3 l4 l5 l6 l7\n# output o0 o1 o2 o3 o4 o5 sp o7\n\n# fp w016 w036 w126 w236 w316 w336 w416 w436 w516 w536\n# sp w036 w126 w236 w316 w336 w416 w436 w616 w536\n# i7 w017 w037 w127 w217 w237 w327 w417 \n# o7 w037 w127 w217 w237 w327 w417 \n\ndefine register offset=0x8000 size=$(SIZE) [\n\tw010 w011 w012 w013 w014 w015 w016 w017\n\tw020 w021 w022 w023 w024 w025 w026 w027\n\tw030 w031 w032 w033 w034 w035 w036 w037\n\tw110 w111 w112 w113 w114 w115 w116 w117\n\tw120 w121 w122 w123 w124 w125 w126 w127\n\tw130 w131 w132 w133 w134 w135 w136 w137\n\tw210 w211 w212 w213 w214 w215 w216 w217\n\tw220 w221 w222 w223 w224 w225 w226 w227\n\tw230 w231 w232 w233 w234 w235 w236 w237\n\tw310 w311 w312 w313 w314 w315 w316 w317\n\tw320 w321 w322 w323 w324 w325 w326 w327\n\tw330 w331 w332 w333 w334 w335 w336 w337\n\tw410 w411 w412 w413 w414 w415 w416 w417\n\tw420 w421 w422 w423 w424 w425 w426 w427\n\tw430 w431 w432 w433 w434 w435 w436 w437\n\tw510 w511 w512 w513 w514 w515 w516 w517\n\tw520 w521 w522 w523 w524 w525 w526 w527\n\tw530 w531 w532 w533 w534 w535 w536 w537\n\tw610 w611 w612 w613 w614 w615 w616 w617\n\tw620 w621 w622 w623 w624 w625 w626 w627\n\tw630 w631 w632 w633 w634 w635 w636 w637\n\tw710 w711 w712 w713 w714 w715 w716 w717\n\tw720 w721 w722 w723 w724 w725 w726 w727\n\tw730 w731 w732 w733 w734 w735 w736 w737\n];\n\n# Floating-point registers\ndefine register offset=0x2000 size=4 [\n\tfs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7\n fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15\n fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23\n fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31\n];\n \ndefine register offset=0x2000 size=8 [\n\tfd0 fd2 fd4 fd6 fd8 fd10 fd12 fd14\n fd16 fd18 fd20 fd22 fd24 fd26 fd28 fd30\n fd32 fd34 fd36 fd38 fd40 fd42 fd44 fd46\n fd48 fd50 fd52 fd54 fd56 fd58 fd60 fd62\n];\n \ndefine register offset=0x2000 size=16 [\n\tfq0 fq4 fq8 fq12 fq16 fq20 fq24 fq28\n fq32 fq36 fq40 fq44 fq48 fq52 fq56 fq60\n];\n \n\n\ndefine pcodeop segment;\ndefine pcodeop sw_trap;\ndefine pcodeop reset;\n\ndefine token instr(32)\n\top = (30,31)\n\tdisp30 = ( 0,29) signed\n\tudisp22 = ( 0,21)\n\tdisp22 = ( 0,21) signed\n\tdisp19 = ( 0,18) signed\n\td16lo = ( 0,13)\n\td16hi = (20,21) signed\n\top2 = (22,24)\n\ta = (29,29)\n\tfpc = (27,29)\n\tcond = (25,28)\n\tcond4 = (14,17)\n\trcond2 = (25,27)\n\tcc0 = (20,20)\n\tcc1 = (21,21)\n\tfccn = (20,21)\n\tfccn2 = (25,26)\n\tcc0_3 = (25,25)\n\tcc1_3 = (26,26)\n\tcc0_4 = (11,11)\n\tcc1_4 = (12,12)\n\tfccn_4 = (11,12)\n\tcc2_4 = (18,18)\n\tp = (19,19)\n\trd = (25,29)\n\trd_d = (25,29)\n\trd_asr = (25,29)\n\trd_zero = (25,29)\n\tfsrd = (25,29)\n\tfdrd = (25,29)\n\tfqrd = (25,29)\n\tprd = (25,29)\n\top3 = (19,24)\n\trs1 = (14,18)\n\trs1_zero = (14,18)\n\trs_asr = (14,18)\n\tprs1 = (14,18)\n\tfsrs1 = (14,18)\n\tfdrs1 = (14,18)\n\tfqrs1 = (14,18)\n\ti = (13,13)\n\tx = (12,12)\n\trcond3 = (10,12)\n\trs2 = ( 0, 4)\n\trs2_zero = ( 0, 4)\n\tfsrs2 = ( 0, 4)\n\tfdrs2 = ( 0, 4)\n\tfqrs2 = ( 0, 4)\n\tshcnt32 = ( 0, 4)\n\tshcnt64 = ( 0, 5)\n\tsimm13 = ( 0,12) signed\n\tsimm11 = ( 0,10) signed\n\tsimm10 = ( 0, 9) signed\n\timm_asi = ( 5,12)\n\tcmask = ( 4, 6)\n\tmmask = ( 0, 3)\n\topf = ( 5,13)\n\topf5 = ( 5, 9)\n\topf6 = ( 5,10)\n\topf_cc = (11,13)\n\topf_low = ( 5,10)\n\topf_low_5_9 = ( 5,9)\n\tfcn = (25,29)\n\tswtrap = ( 0, 6)\n\tbit28 = (28,28)\n\tconst22 = ( 0,21)\n\tbit13 = (13,13)\n\tbit18 = (18,18)\n;\n\nattach variables [ rd rs1 rs2 ] [ g0 g1 g2 g3 g4 g5 g6 g7\n o0 o1 o2 o3 o4 o5 sp o7\n l0 l1 l2 l3 l4 l5 l6 l7\n i0 i1 i2 i3 i4 i5 fp i7 ];\n\n@if SIZE==\"4\"\n# The ldd, ldda, std, and stda insns access a pair of regs\ndefine register offset=0 size=8 [\n\tg0_1 g2_3 g4_5 g6_7\n\to0_1 o2_3 o4_5 sp_7\n\tl0_1 l2_3 l4_5 l6_7\n\ti0_1 i2_3 i4_5 fp_7\n];\n\nattach variables [ rd_d ] [\n g0_1 _ g2_3 _ g4_5 _ g6_7 _\n o0_1 _ o2_3 _ o4_5 _ sp_7 _\n l0_1 _ l2_3 _ l4_5 _ l6_7 _\n i0_1 _ i2_3 _ i4_5 _ fp_7 _\n ];\n\n@endif\n\nattach variables [ fccn fccn2 fccn_4 ] [ fcc0 fcc1 fcc2 fcc3 ];\n\n#attach names [ rd rs1 rs2 ] [ \"%g0\" \"%g1\" \"%g2\" \"%g3\" \"%g4\" \"%g5\" \"%g6\" \"%g7\"\n# \"%o0\" \"%o1\" \"%o2\" \"%o3\" \"%o4\" \"%o5\" \"%sp\" \"%o7\"\n# \"%l0\" \"%l1\" \"%l2\" \"%l3\" \"%l4\" \"%l5\" \"%l6\" \"%l7\"\n# \"%i0\" \"%i1\" \"%i2\" \"%i3\" \"%i4\" \"%i5\" \"%fp\" \"%i7\" ];\n# Window register table accessors ===================================\n@define NUMREGWINS 8\n@define REGWINSZ 16\n@define LOCALOFF 8\n@define OUTOFF 16\n\n# copy oN to iN\n# CWP++\nmacro save() { \n\nif (DECOMPILE_MODE) goto ;\n\t# Save inputs \n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+0)*$(SIZE)) = i0;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+1)*$(SIZE)) = i1;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+2)*$(SIZE)) = i2;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+3)*$(SIZE)) = i3;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+4)*$(SIZE)) = i4;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+5)*$(SIZE)) = i5;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+6)*$(SIZE)) = fp;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+7)*$(SIZE)) = i7;\n\n\t# Save local\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)) = l0;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)) = l1;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)) = l3;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)) = l3;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)) = l4;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)) = l5;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)) = l6;\n\t*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+7+$(LOCALOFF))*$(SIZE)) = l7;\n\n\n\t# what was outputs become inputs\n\ti0 = o0;\n\ti1 = o1;\n\ti2 = o2;\n\ti3 = o3;\n\ti4 = o4;\n\ti5 = o5;\n\tfp = sp;\n\ti7 = o7;\n\n\t# zero out locals \n\tl0 = 0;\n\tl1 = 0;\n\tl2 = 0;\n\tl3 = 0;\n\tl4 = 0;\n\tl5 = 0;\n\tl6 = 0;\n\tl7 = 0;\n\n\tCWP = CWP + 1;\n}\n\n# copy iN ot oN\n# CWP--\nmacro restore() {\n\tCWP = CWP - 1;\n\n\t# inputs once again become outputs\n\to0 = i0; # API return value\n\to1 = i1;\n\to2 = i2;\n\to3 = i3;\n\to4 = i4;\n\to5 = i5;\n\tsp = fp;\n\to7 = i7; # address of CALLer address\n\nif (DECOMPILE_MODE) goto ;\t\n\t# restore original inputs\n\ti0 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+0)*$(SIZE)));\n\ti1 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+1)*$(SIZE)));\n\ti2 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+2)*$(SIZE)));\n\ti3 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+3)*$(SIZE)));\n\ti4 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+4)*$(SIZE)));\n\ti5 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+5)*$(SIZE)));\n\tfp = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6)*$(SIZE)));\n\ti7 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+7)*$(SIZE))); # address of CALLer address\n\t# restore original locals\n\tl0 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)));\n\tl1 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)));\n\tl2 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)));\n\tl3 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)));\n\tl4 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)));\n\tl5 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)));\n\tl6 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)));\n\tl7 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)));\n\n\n}\n\n#Register g0 in Sparc is always 0\n\n#There are special cases for source operands RS1 and RS2 which just return the constant 0 when the\n#specified register is g0\nRS1: rs1 is rs1 & rs1_zero=0 { export 0:$(SIZE); }\nRS1: rs1 is rs1 { export rs1; }\n\nRS2: rs2 is rs2 & rs2_zero=0 { export 0:$(SIZE); }\nRS2: rs2 is rs2 { export rs2; }\n\n#For the destination operand RD, we export a temporary varnode with value 0.\n#This is because writes to g0 are allowed, but they have no visible effect (see the Sparc manual).\n#This way the value of g0 won't appear to change when using the pcode emulator.\n#\nRD: rd is rd & rd_zero=0 { local tmp:$(SIZE) = 0; export tmp; }\n# didrestore is picked up by call instruction only\n# this will cause any instruction that assigns to the o7 return address register\n# in the delay slot of a call instruction to turn the call into a call/return\n#\nRD: rd is rd & rd_d=15 { didrestore = 1; export rd; }\nRD: rd is rd { export rd; }\n\nregorimm: RS2 is i=0 & RS2 { export RS2; }\nregorimm: simm13 is i=1 & simm13 { export *[const]:$(SIZE) simm13; }\n\nregorimm10: RS2 is i=0 & RS2 { export RS2; }\nregorimm10: simm10 is i=1 & simm10 { export *[const]:$(SIZE) simm10; }\n\nregorimm11: RS2 is i=0 & RS2 { export RS2; }\nregorimm11: simm11 is i=1 & simm11 { export *[const]:$(SIZE) simm11; }\n\nreg_or_shcnt: RS2 is i=0 & RS2 & rs2=0 { export 0:1; }\nreg_or_shcnt: RS2 is i=0 & x=0 & RS2 { tmp:1=RS2:1; tmp = tmp & 0x1f; export tmp; }\nreg_or_shcnt: RS2 is i=0 & x=1 & RS2 { tmp:1=RS2:1; tmp = tmp & 0x3f; export tmp; }\n\nreg_or_shcnt: shcnt32 is i=1 & x=0 & shcnt32 { export *[const]:1 shcnt32; }\nreg_or_shcnt: shcnt64 is i=1 & x=1 & shcnt64 { export *[const]:1 shcnt64; }\n\nea: [regorimm] is rs1=0 & regorimm { export regorimm; } # special case g0=zero\nea: [RS1+regorimm] is RS1 & regorimm { local tmp = RS1+regorimm; export tmp; }\nea: [RS1] is RS1 & i=1 & simm13=0x0 { export RS1; } #special case when adding zero\n\nretea: regorimm is rs1=0 & i=0 & regorimm { local tmp = regorimm; export tmp; }\nretea: regorimm is rs1=0 & i=1 & regorimm { export *:$(SIZE) regorimm; } \nretea: RS1+regorimm is RS1 & regorimm { local tmp = RS1+regorimm; export tmp; }\nretea: RS1 is RS1 & i=1 & simm13=0x0 { local tmp = RS1; export tmp; } #special case when adding zero\nretea: is rs1 & rs1_zero=31 & i=1 & simm13=0x8 { local tmp = rs1 + 0x8; export tmp; } # typical return from CALL instruction (suppress display)\n\nea_alt: [RS1+RS2] imm_asi is i=0 & RS1 & RS2 & imm_asi { local tmp1:1 = imm_asi; local tmp = RS1+RS2+segment(tmp1); export tmp; }\nea_alt: [RS1+simm13] %ASI is i=1 & RS1 & simm13 & ASI { local tmp = RS1+simm13+segment(ASI); export tmp; }\nea_alt: [RS1] %ASI is i=1 & RS1 & simm13=0x0 & ASI { local tmp = RS1+segment(ASI); export tmp; } #special case when adding zero\n\nmacro addflags(op1,op2) {\n\tx_cf = carry(op1,op2);\n\tx_vf = scarry(op1,op2);\n\n\tlocal tmp1 = op1:4;\n\tlocal tmp2 = op2:4;\n\n\ti_cf = carry(tmp1,tmp2);\n\ti_vf = scarry(tmp1,tmp2);\n}\n\nmacro taddflags(op1,op2) {\n\taddflags(op1,op2);\n\ti_vf = i_vf || ((op1 & 0x3) != 0) || ((op2 & 0x3) != 0);\n}\n\nmacro addflags32(op1,op2) {\n\ti_cf = carry(op1,op2);\n\ti_vf = scarry(op1,op2);\n}\n\nmacro addCarryFlags ( op1, op2 ) {\n\tlocal op1_low_32:4 = op1:4;\n\tlocal op2_low_32:4 = op2:4;\n local CFcopy_4:4 = zext(i_cf);\n\tlocal CFcopy:$(SIZE) = zext(i_cf);\n\tlocal result:$(SIZE) = op1 + op2;\n\tlocal result_low_32:4 = op1_low_32 + op2_low_32;\n\ti_cf = carry( op1_low_32, op2_low_32) || carry( result_low_32, CFcopy_4 );\n\tx_cf = carry(op1,op2) || carry(result,CFcopy);\n\ti_vf = scarry( op1_low_32, op2_low_32) ^^ scarry( result_low_32, CFcopy_4 );\n\tx_vf = scarry(op1, op2) ^^ scarry(result,CFcopy);\n}\n\nmacro subCarryFlags ( op1, op2 ) {\n\tlocal op1_low_32:4 = op1:4;\n\tlocal op2_low_32:4 = op2:4;\n local CFcopy_4:4 = zext(i_cf);\n\tlocal CFcopy:$(SIZE) = zext(i_cf);\n\tlocal result:$(SIZE) = op1 - op2;\n\tlocal result_low_32:4 = op1_low_32 - op2_low_32;\n\ti_cf = (op1_low_32 < op2_low_32) || (result_low_32 < CFcopy_4);\n\tx_cf = (op1 < op2) || (result < CFcopy);\n\ti_vf = sborrow( op1_low_32, op2_low_32) ^^ sborrow( result_low_32, CFcopy_4);\n\tx_vf = sborrow(op1, op2) ^^ sborrow(result,CFcopy);\t\n}\n\nmacro logicflags() {\n\tx_cf = 0;\n\tx_vf = 0;\n\n\ti_cf = 0;\n\ti_vf = 0;\n}\n\nmacro subflags(op1,op2) {\n\tx_cf = op1 < op2;\n\tx_vf = sborrow(op1,op2);\n\n\tlocal tmp1 = op1:4;\n\tlocal tmp2 = op2:4;\n\n\ti_cf = tmp1 < tmp2;\n\ti_vf = sborrow(tmp1,tmp2);\n}\n\nmacro tsubflags(op1,op2){\n\tsubflags(op1,op2);\n\ti_vf = i_vf || ((op1 & 0x3) != 0) || ((op2 & 0x3) != 0);\n}\n\nmacro zeroflags(op1) {\n\tx_zf = (op1 == 0);\n\tx_nf = (op1 s< 0);\n\n\tlocal tmp1 = op1:4;\n\n\ti_zf = (tmp1 == 0);\n\ti_nf = (tmp1 s< 0);\n}\n\nmacro packflags(ccr) {\n\tccr = zext((x_nf << 7) | (x_zf << 6) | (x_vf << 5) | (x_cf << 4) | (i_nf << 3) | (i_zf << 2) | (i_vf << 1) | (i_cf << 0));\n}\n\nmacro unpackflags(ccr) {\n\tx_nf = (ccr & 0x80)!=0;\n\tx_zf = (ccr & 0x40)!=0;\n\tx_vf = (ccr & 0x20)!=0;\n\tx_cf = (ccr & 0x10)!=0;\n\ti_nf = (ccr & 0x8)!=0;\n\ti_zf = (ccr & 0x4)!=0;\n\ti_vf = (ccr & 0x2)!=0;\n\ti_cf = (ccr & 0x1)!=0;\n}\n\n# ---------------\n:add RS1,regorimm,RD is op=2 & RD & op3=0x0 & RS1 & regorimm {RD = RS1 + regorimm;}\n\n:addcc RS1,regorimm,RD is op=2 & RD & op3=0x10 & RS1 & regorimm \n{\n\taddflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 + regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n\n:addc RS1,regorimm,RD is op=2 & RD & op3=0x8 & RS1 & regorimm {RD = RS1 + regorimm + zext(i_cf);}\n\n:addccc RS1,regorimm,RD is op=2 & RD & op3=0x18 & RS1 & regorimm \n{\n\tlocal original_i_cf:$(SIZE) = zext(i_cf);\n\taddCarryFlags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 + regorimm + original_i_cf;\n\tzeroflags(res);\n\tRD = res;\n}\n#-----------------------\n:and RS1,regorimm,RD is op=2 & RD & op3=0x1 & RS1 & regorimm {RD = RS1 & regorimm;}\n\n:andcc RS1,regorimm,RD is op=2 & RD & op3=0x11 & RS1 & regorimm \n{ \n\tlogicflags();\n\tlocal res:$(SIZE) = RS1 & regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n:andn RS1,regorimm,RD is op=2 & RD & op3=0x5 & RS1 & regorimm {RD = RS1 & ~regorimm;}\n\n:andncc RS1,regorimm,RD is op=2 & RD & op3=0x15 & RS1 & regorimm \n{ \n\tlogicflags();\n\tlocal res:$(SIZE) = RS1 & ~regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n\n:or RS1,regorimm,RD is op=2 & RD & op3=0x2 & RS1 & regorimm {RD = RS1 | regorimm;}\n\n:orcc RS1,regorimm,RD is op=2 & RD & op3=0x12 & RS1 & regorimm \n{\n\tlogicflags();\n\tlocal res:$(SIZE) = RS1 | regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n:orn RS1,regorimm,RD is op=2 & RD & op3=0x6 & RS1 & regorimm {RD = RS1 | ~regorimm;}\n\n:orncc RS1,regorimm,RD is op=2 & RD & op3=0x16 & RS1 & regorimm \n{\n\tlogicflags();\n\tlocal res:$(SIZE) = RS1 | ~regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n:xor RS1,regorimm,RD is op=2 & RD & op3=0x3 & RS1 & regorimm {RD = RS1 ^ regorimm;}\n\n:xorcc RS1,regorimm,RD is op=2 & RD & op3=0x13 & RS1 & regorimm \n{\n\tlogicflags();\n\tlocal res:$(SIZE) = RS1 ^ regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n\n:xnor RS1,regorimm,RD is op=2 & RD & op3=0x7 & RS1 & regorimm {RD = RS1 ^ ~regorimm;}\n\n:xnorcc RS1,regorimm,RD is op=2 & RD & op3=0x17 & RS1 & regorimm \n{\n\tlogicflags();\n\tlocal res:$(SIZE) = RS1 ^ ~regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n\n# ---------------\n:ldsb ea,RD is op=3 & RD & op3=0x09 & ea { RD = sext(*:1 ea); }\n:ldsh ea,RD is op=3 & RD & op3=0x0A & ea { RD = sext(*:2 ea); }\n:ldsw ea,RD is op=3 & RD & op3=0x08 & ea { RD = sext(*:4 ea); }\n:ldub ea,RD is op=3 & RD & op3=0x01 & ea { RD = zext(*:1 ea); }\n:lduh ea,RD is op=3 & RD & op3=0x02 & ea { RD = zext(*:2 ea); }\n:lduw ea,RD is op=3 & RD & op3=0x00 & ea { RD = zext(*:4 ea); }\n:ldx ea,RD is op=3 & RD & op3=0x0b & ea { RD = *:$(SIZE) ea; }\n\n@if SIZE==\"8\"\n:ldd ea,RD is op=3 & RD & op3=0x03 & ea { RD = *:$(SIZE) ea; }\n@else\n:ldd ea,RD is op=3 & RD & rd_d & op3=0x03 & ea { rd_d = *:8 ea; }\n\n@endif\n\n:ldsba ea_alt,RD is op=3 & RD & op3=0x19 & ea_alt { RD = sext(*:1 ea_alt); }\n:ldsha ea_alt,RD is op=3 & RD & op3=0x1a & ea_alt { RD = sext(*:2 ea_alt); }\n:ldswa ea_alt,RD is op=3 & RD & op3=0x18 & ea_alt { RD = sext(*:4 ea_alt); }\n:lduba ea_alt,RD is op=3 & RD & op3=0x11 & ea_alt { RD = zext(*:1 ea_alt); }\n:lduha ea_alt,RD is op=3 & RD & op3=0x12 & ea_alt { RD = zext(*:2 ea_alt); }\n:lduwa ea_alt,RD is op=3 & RD & op3=0x10 & ea_alt { RD = zext(*:4 ea_alt); }\n\n:ldxa ea_alt,RD is op=3 & RD & op3=0x1b & ea_alt { RD = *:$(SIZE) ea_alt; }\n:ldda ea_alt,RD is op=3 & RD & op3=0x13 & ea_alt { RD = *:$(SIZE) ea_alt; }\n\n#-----------------\n:stb RD,ea is op=3 & RD & op3=0x05 & ea { *ea = RD:1; } \n:sth RD,ea is op=3 & RD & op3=0x06 & ea { *ea = RD:2; } \n:stw RD,ea is op=3 & RD & op3=0x04 & ea { *ea = RD:4; }\n\n@if SIZE==\"8\"\n:stx RD,ea is op=3 & RD & op3=0x0e & ea { *ea = RD; }\n:std RD,ea is op=3 & RD & op3=0x07 & ea { *ea = RD; }\n@else\n# size = 4, but this extended store instruction needs to write 8 bytes\n:stx RD,ea is op=3 & RD & rd_d & op3=0x0e & ea { *ea = rd_d; }\n:std RD,ea is op=3 & RD & rd_d & op3=0x07 & ea { *ea = rd_d; }\n@endif\n\n:clrx ea is op=3 & rd=0 & op3=0x0e & ea { *ea = 0:8; }\n:clrd ea is op=3 & rd=0 & op3=0x07 & ea { *ea = 0:8; }\n\n:stba RD,ea_alt is op=3 & RD & op3=0x15 & ea_alt { *ea_alt = RD:1; } \n:stha RD,ea_alt is op=3 & RD & op3=0x16 & ea_alt { *ea_alt = RD:2; } \n:stwa RD,ea_alt is op=3 & RD & op3=0x14 & ea_alt { *ea_alt = RD:4; } \n:stxa RD,ea_alt is op=3 & RD & op3=0x1e & ea_alt { *ea_alt = RD; } \n:stda RD,ea_alt is op=3 & RD & op3=0x17 & ea_alt { *ea_alt = RD; } \n# ---------------\n\n:sub RS1,regorimm,RD is op=2 & RD & op3=0x4 & RS1 & regorimm \n{\n\tRD = RS1 - regorimm;\n}\n\n:subcc RS1,regorimm,RD is op=2 & RD & op3=0x14 & RS1 & regorimm \n{\n\tsubflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 - regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n\n:subc RS1,regorimm,RD is op=2 & RD & op3=0xc & RS1 & regorimm \n{\n\tRD = RS1 - regorimm - zext(i_cf);\n}\n\n:subccc RS1,regorimm,RD is op=2 & RD & op3=0x1c & RS1 & regorimm \n{\n\tlocal original_cf:$(SIZE) = zext(i_cf);\n\tsubCarryFlags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 - regorimm - original_cf;\n\tzeroflags(res);\n\tRD = res;\n}\n\n# ---------------\n\n:nop is op=0x0 & rd=0x0 & op2=0x4 & disp22=0x0 { }\n\n# ---------------COMPARES\n\n:cmp RS1,regorimm is op=0x2 & rd=0x0 & op3=0x14 & RS1 & regorimm \n{\n\tsubflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 - regorimm;\n\tzeroflags(res);\n}\n\n\n# ---------------MOVES\n\n:mov regorimm,RD is op=2 & RD & op3=0x2 & rs1=0 & regorimm {RD = regorimm;}\n\n# This will not work until the rs1 field in a token can be used without being\n# part of the display portion below\nRCOND: \"z\" is rcond3=1 & RS1 { tmp:1 = (RS1 == 0); export tmp; }\nRCOND: \"lez\" is rcond3=2 & RS1 { tmp:1 = (RS1 s<= 0); export tmp; }\nRCOND: \"lz\" is rcond3=3 & RS1 { tmp:1 = (RS1 s< 0); export tmp; }\nRCOND: \"nz\" is rcond3=5 & RS1 { tmp:1 = (RS1 != 0); export tmp; }\nRCOND: \"gz\" is rcond3=6 & RS1 { tmp:1 = (RS1 s> 0); export tmp; }\nRCOND: \"gez\" is rcond3=7 & RS1 { tmp:1 = (RS1 s>= 0); export tmp; }\n\n:movr^RCOND RS1,regorimm10,RD is op=0x2 & RD & op3=0x2f & RCOND & regorimm10 & RS1 \n{\n\tif !RCOND goto ;\n\tRD = regorimm10;\n\t\n}\n\n#:movrz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=1 & regorimm10 { if (RS1 == 0) goto inst_next; rd = regorimm10; }\n#:movrlez RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=2 & regorimm10 { if (RS1 s<= 0) goto inst_next; rd = regorimm10; }\n#:movrlz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=3 & regorimm10 { if (RS1 s< 0) goto inst_next; rd = regorimm10; }\n#:movrnz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=5 & regorimm10 { if (RS1 != 0) goto inst_next; rd = regorimm10; }\n#:movrgz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=6 & regorimm10 { if (RS1 s> 0) goto inst_next; rd = regorimm10; }\n#:movrgez RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=7 & regorimm10 { if (RS1 s>= 0) goto inst_next; rd = regorimm10; }\nm_icc: \"a\" is cond4=0x8 { tmp:1=1; export tmp; }\nm_icc: \"n\" is cond4=0x0 { tmp:1=0; export tmp; }\nm_icc: \"ne\" is cond4=0x9 { tmp:1=!i_zf; export tmp; }\nm_icc: \"e\" is cond4=0x1 { tmp:1=i_zf; export tmp; }\nm_icc: \"g\" is cond4=0xa { tmp:1=!(i_zf || (i_nf ^^ i_vf)); export tmp; }\nm_icc: \"le\" is cond4=0x2 { tmp:1=(i_zf || (i_nf ^^ i_vf)); export tmp; }\nm_icc: \"ge\" is cond4=0xb { tmp:1=!(i_nf ^^ i_vf); export tmp; }\nm_icc: \"l\" is cond4=0x3 { tmp:1=(i_nf ^^ i_vf); export tmp; }\nm_icc: \"gu\" is cond4=0xc { tmp:1=!(i_cf || i_zf); export tmp; }\nm_icc: \"leu\" is cond4=0x4 { tmp:1=(i_cf || i_zf); export tmp; }\nm_icc: \"cc\" is cond4=0xd { tmp:1=!(i_cf); export tmp; }\nm_icc: \"cs\" is cond4=0x5 { export i_cf; }\nm_icc: \"pos\" is cond4=0xe { tmp:1=!(i_nf); export tmp; }\nm_icc: \"neg\" is cond4=0x6 { export i_nf; }\nm_icc: \"vc\" is cond4=0xf { tmp:1=!(i_vf); export tmp; }\nm_icc: \"vs\" is cond4=0x7 { export i_vf; }\n\nm_xcc: \"a\" is cond4=0x8 { tmp:1=1; export tmp; }\nm_xcc: \"n\" is cond4=0x0 { tmp:1=0; export tmp; }\nm_xcc: \"ne\" is cond4=0x9 { tmp:1=!x_zf; export tmp; }\nm_xcc: \"e\" is cond4=0x1 { tmp:1=x_zf; export tmp; }\nm_xcc: \"g\" is cond4=0xa { tmp:1=!(x_zf || (x_nf ^^ x_vf)); export tmp; }\nm_xcc: \"le\" is cond4=0x2 { tmp:1=(x_zf || (x_nf ^^ x_vf)); export tmp; }\nm_xcc: \"ge\" is cond4=0xb { tmp:1=!(x_nf ^^ x_vf); export tmp; }\nm_xcc: \"l\" is cond4=0x3 { tmp:1=(x_nf ^^ x_vf); export tmp; }\nm_xcc: \"gu\" is cond4=0xc { tmp:1=!(x_cf || x_zf); export tmp; }\nm_xcc: \"leu\" is cond4=0x4 { tmp:1=(x_cf || x_zf); export tmp; }\nm_xcc: \"cc\" is cond4=0xd { tmp:1=!(x_cf); export tmp; }\nm_xcc: \"cs\" is cond4=0x5 { export x_cf; }\nm_xcc: \"pos\" is cond4=0xe { tmp:1=!(x_nf); export tmp; }\nm_xcc: \"neg\" is cond4=0x6 { export x_nf; }\nm_xcc: \"vc\" is cond4=0xf { tmp:1=!(x_vf); export tmp; }\nm_xcc: \"vs\" is cond4=0x7 { export x_vf; }\n\nm_cc:m_icc is cc2_4=1 & cc1_4=0 & cc0_4=0 & m_icc { export m_icc; }\nm_cc:m_xcc is cc2_4=1 & cc1_4=1 & cc0_4=0 & m_xcc { export m_xcc; }\n\nMICC: \"%icc\" is cc2_4=1 &cc1_4=0 { }\nMICC: \"%xcc\" is cc2_4=1 &cc1_4=1 { }\n\n#conditional integer moves with floating-point conditions defined in constructor :mov^fmfcc\n:mov^m_cc MICC,regorimm11,RD is op=0x2 & RD & op3=0x2c & bit18=1 & m_cc & MICC & regorimm11 \n{\n\tif (!m_cc) goto ;\n\tRD = regorimm11;\n\t\n}\n\n# ---------------BRANCHES\nicc: \"a\" is cond=0x8 { tmp:1=1; export tmp; }\nicc: \"ne\" is cond=0x9 { tmp:1=!i_zf; export tmp; }\nicc: \"e\" is cond=0x1 { tmp:1=i_zf; export tmp; }\nicc: \"g\" is cond=0xa { tmp:1=!(i_zf || (i_nf ^^ i_vf)); export tmp; }\nicc: \"le\" is cond=0x2 { tmp:1=(i_zf || (i_nf ^^ i_vf)); export tmp; }\nicc: \"ge\" is cond=0xb { tmp:1=!(i_nf ^^ i_vf); export tmp; }\nicc: \"l\" is cond=0x3 { tmp:1=(i_nf ^^ i_vf); export tmp; }\nicc: \"gu\" is cond=0xc { tmp:1=!(i_cf || i_zf); export tmp; }\nicc: \"leu\" is cond=0x4 { tmp:1=(i_cf || i_zf); export tmp; }\nicc: \"cc\" is cond=0xd { tmp:1=!(i_cf); export tmp; }\nicc: \"cs\" is cond=0x5 { export i_cf; }\nicc: \"pos\" is cond=0xe { tmp:1=!(i_nf); export tmp; }\nicc: \"neg\" is cond=0x6 { export i_nf; }\nicc: \"vc\" is cond=0xf { tmp:1=!(i_vf); export tmp; }\nicc: \"vs\" is cond=0x7 { export i_vf; }\n\nxcc: \"a\" is cond=0x8 { tmp:1=1; export tmp; }\nxcc: \"ne\" is cond=0x9 { tmp:1=!x_zf; export tmp; }\nxcc: \"e\" is cond=0x1 { tmp:1=x_zf; export tmp; }\nxcc: \"g\" is cond=0xa { tmp:1=!(x_zf || (x_nf ^^ x_vf)); export tmp; }\nxcc: \"le\" is cond=0x2 { tmp:1=(x_zf || (x_nf ^^ x_vf)); export tmp; }\nxcc: \"ge\" is cond=0xb { tmp:1=!(x_nf ^^ x_vf); export tmp; }\nxcc: \"l\" is cond=0x3 { tmp:1=(x_nf ^^ x_vf); export tmp; }\nxcc: \"gu\" is cond=0xc { tmp:1=!(x_cf || x_zf); export tmp; }\nxcc: \"leu\" is cond=0x4 { tmp:1=(x_cf || x_zf); export tmp; }\nxcc: \"cc\" is cond=0xd { tmp:1=!(x_cf); export tmp; }\nxcc: \"cs\" is cond=0x5 { export x_cf; }\nxcc: \"pos\" is cond=0xe { tmp:1=!(x_nf); export tmp; }\nxcc: \"neg\" is cond=0x6 { export x_nf; }\nxcc: \"vc\" is cond=0xf { tmp:1=!(x_vf); export tmp; }\nxcc: \"vs\" is cond=0x7 { export x_vf; }\n\ncc: icc is cc1=0 & cc0=0 & icc { export icc; }\ncc: xcc is cc1=1 & cc0=0 & xcc { export xcc; }\n\nd16off: reloc is d16hi & d16lo [reloc = inst_start+4*((d16hi<<14) | d16lo);] { export *:$(SIZE) reloc; }\n\npredict: \",pt\" is p=1 { }\npredict: \",pn\" is p=0 { }\n\n:brz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x1 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 == 0) goto d16off;}\n:brlez^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x2 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s<= 0) goto d16off;}\n:brlz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x3 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s< 0) goto d16off;}\n:brnz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x5 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 != 0) goto d16off;}\n:brgz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x6 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s> 0) goto d16off;}\n:brgez^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x7 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s>= 0) goto d16off;}\n\n:brz^\",a\"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x1 & op2=0x3 & RS1 & d16off & predict { if (RS1 != 0) goto inst_next; delayslot(1); goto d16off;}\n:brlez^\",a\"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x2 & op2=0x3 & RS1 & d16off & predict { if (RS1 s> 0) goto inst_next; delayslot(1); goto d16off;}\n:brlz^\",a\"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x3 & op2=0x3 & RS1 & d16off & predict { if (RS1 s>= 0) goto inst_next; delayslot(1); goto d16off;}\n:brnz^\",a\"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x5 & op2=0x3 & RS1 & d16off & predict { if (RS1 == 0) goto inst_next; delayslot(1); goto d16off;}\n:brgz^\",a\"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x6 & op2=0x3 & RS1 & d16off & predict { if (RS1 s<= 0) goto inst_next; delayslot(1); goto d16off;}\n:brgez^\",a\"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x7 & op2=0x3 & RS1 & d16off & predict { if (RS1 s< 0) goto inst_next; delayslot(1); goto d16off;}\n\nBCC: \"%icc\" is cc0=0 & cc1=0 { }\nBCC: \"%xcc\" is cc0=0 & cc1=1 { }\n\nreloff: reloc is disp22 [reloc=inst_start+(4*disp22);] { export *:$(SIZE) reloc; }\nreloff64: reloc is disp19 [reloc=inst_start+(4*disp19);] { export *:$(SIZE) reloc; }\n\nskip: reloc is epsilon [reloc=inst_start+8;] { export *:$(SIZE) reloc; }\n\n:ba reloff is op=0x0 & op2=0x2 & a=0x0 & cond=0x8 & reloff { delayslot(1); goto reloff; }\n:\"ba,a\" reloff is op=0x0 & op2=0x2 & a=0x1 & cond=0x8 & reloff { goto reloff; }\n\n:bn reloff is op=0x0 & op2=0x2 & a=0x0 & cond=0x0 & reloff { }\n:\"bn,a\" reloff,skip is op=0x0 & op2=0x2 & a=0x1 & cond=0x0 & reloff & skip { goto skip; }\n\n:b^icc reloff is op=0x0 & op2=0x2 & a=0x0 & icc & reloff { delayslot(1); if (icc) goto reloff; }\n:b^icc^\",a\" reloff is op=0x0 & op2=0x2 & a=0x1 & icc & reloff { if (!icc) goto inst_next; delayslot(1); goto reloff; }\n\n:bpa^predict reloff64 is op=0x0 & op2=0x1 & a=0x0 & cond=0x8 & reloff64 & predict { delayslot(1); goto reloff64; }\n:\"bpa,a\"^predict reloff64 is op=0x0 & op2=0x1 & a=0x1 & cond=0x8 & reloff64 & predict { goto reloff64; }\n\n:bpn^predict reloff64 is op=0x0 & op2=0x1 & a=0x0 & cond=0x0 & reloff64 & predict { }\n:\"bpn,a\"^predict reloff64,skip is op=0x0 & op2=0x1 & a=0x1 & cond=0x0 & reloff64 & predict & skip { goto skip; }\n\n:bp^cc^predict BCC,reloff64 is op=0x0 & op2=0x1 & a=0x0 & cond & cc & reloff64 & predict & BCC { delayslot(1); if (cc) goto reloff64; }\n:bp^cc^\",a\"^predict BCC,reloff64 is op=0x0 & op2=0x1 & a=0x1 & cond & cc & reloff64 & predict & BCC { if (!cc) goto inst_next; delayslot(1); goto reloff64; }\n\n#:br^cc^predict reloff64 is op=0x0 & a=0x0 & op2=0x3 & cc & reloff64 & predict { delayslot(1); if (cc) goto reloff64; }\n#:br^cc^\",a\"^predict reloff64 is op=0x0 & a=0x1 & op2=0x3 & cc & reloff64 & predict { if (!cc) goto inst_next; delayslot(1); goto reloff64; }\n#---------------CALL\ncallreloff: reloc is disp30 [reloc=inst_start+4*disp30;] { export *:$(SIZE) reloc; }\n\n:call callreloff is op=0x1 & callreloff {\n\to7=inst_start; didrestore=0; delayslot(1); call callreloff; if (didrestore==0) goto inst_next; return [o7];\n}\n\n# changing to jump for PIC call if destination is right below this one.\n:call callreloff is op=0x1 & disp30=2 & callreloff {\n\to7=inst_start; delayslot(1); goto callreloff;\n}\n\n#----------------RET\n\n#----------------MULTIPLY AND DIVIDE 64 bit\n\n:mulx RS1,regorimm,RD is op=2 & RD & op3=0x09 & RS1 & regorimm {RD = RS1 * regorimm;}\n:sdivx RS1,regorimm,RD is op=2 & RD & op3=0x2d & RS1 & regorimm {RD = RS1 s/ regorimm;}\n:udivx RS1,regorimm,RD is op=2 & RD & op3=0x0d & RS1 & regorimm {RD = RS1 / regorimm;}\n\n#----------------MULTIPLY 32 bit\n\n:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm\n{\n\tlocal res:8 = zext(RS1:4) * zext(regorimm:4);\n\tY = zext(res[32,32]);\n@if SIZE==\"4\"\n\tRD = res:4; # 32 bit only gets lower 4 bytes\n@else\n\tRD = res; # 64 bit gets full product\n@endif\n}\n\n:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm\n{\n\tlocal res:8 = sext(RS1:4) * sext(regorimm:4);\n\tY = zext(res[32,32]);\n@if SIZE==\"4\"\n\tRD = res:4; # 32 bit only gets lower 4 bytes\n@else\n\tRD = res; # 64 bit gets full product\n@endif\n}\n\n:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm\n{\n\tlocal res:8 = zext(RS1:4) * zext(regorimm:4);\n\tY = zext(res[32,32]);\n\tzeroflags(res:4);\n@if SIZE==\"4\"\n\tRD = res:4; # 32 bit only gets lower 4 bytes\n@else\n\tRD = res; # 64 bit gets full product\n@endif\n\tlogicflags();\n}\n:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm\n{\n\tlocal res:8 = sext(RS1:4) * sext(regorimm:4);\n\tY = zext(res[32,32]);\n\tzeroflags(res:4);\n@if SIZE==\"4\"\n\tRD = res:4; # 32 bit only gets lower 4 bytes\n@else\n\tRD = res; # 64 bit gets full product\n@endif\n\tlogicflags();\n}\n\n#----------------MULTIPLY Step\n\n:mulscc RS1,regorimm,RD is op=2 & RD & op3=0x24 & RS1 & regorimm\n{\n\tlocal ccr:4 = zext(i_nf ^^ i_vf);\n\tccr = ccr << 31;\n\tlocal shifted:4 = RS1:4 >> 1;\n\tshifted = shifted | ccr;\n\tlocal addend:4 = 0:4;\n\tif ((Y & 0x1) == 0) goto ;\n\taddend = regorimm:4;\n\n\tlocal sum:4 = addend + shifted;\n\taddflags32(addend,shifted);\n\t#upper 32 bits of RD are undefined according to the manual\n\tlocal tbit:4 = (RS1:4 & 0x1:4) << 31;\n\tlocal res:$(SIZE) = zext(sum);\n\tzeroflags(res);\n\tRD = res;\n\t#Y is 64 bits in Sparc 9 but the high 32 are fixed to 0\n\tY = zext((Y:4 >> 1:4) | tbit);\n}\n\n#----------------DIVIDE (64-bit / 32-bit)\n\n# NB- Beware, the plus + operator has higher precedence than shift <<\n# (These are Java rules. C rules have shift and + at the same level, so left to right)\n\n:udiv RS1,regorimm,RD is op=2 & RD & op3=0x0e & RS1 & regorimm\n{\n\tnumerator:8 = (zext(Y) << 32) + zext(RS1:4);\n\tdenom:8 = zext(regorimm:4);\n\tlocal res:8 = numerator / denom;\n\tRD = zext(res:4);\n}\n:sdiv RS1,regorimm,RD is op=2 & RD & op3=0x0f & RS1 & regorimm\n{\n\tnumerator:8 = (sext(Y) << 32) + zext(RS1:4);\n\tdenom:8 = sext(regorimm:4);\n\tlocal res:8 = numerator s/ denom;\n\tRD = sext(res:4);\n}\n\n:udivcc RS1,regorimm,RD is op=2 & RD & op3=0x1e & RS1 & regorimm\n{\n\tnumerator:8 = (zext(Y) << 32) + zext(RS1:4);\n\tdenom:8 = zext(regorimm:4);\n\tlocal res:8 = numerator / denom;\n\tzeroflags(res:4);\n\tRD = zext(res:4);\n\ti_vf = res > 0xffffffff;\n\ti_cf = 0;\n\tx_vf = 0;\n\tx_cf = 0;\n}\n:sdivcc RS1,regorimm,RD is op=2 & RD & op3=0x1f & RS1 & regorimm\n{\n\tnumerator:8 = (sext(Y) << 32) + (zext(RS1) & 0xffffffff);\n\tdenom:8 = sext(regorimm:4);\n\tlocal res:8 = numerator s/ denom;\n\tzeroflags(res:4);\n\tRD = sext(res:4);\n\ti_vf = (res s>= 0x80000000) || (res s<= -0x7ffffffff);\n\ti_cf = 0;\n\tx_vf = 0;\n\tx_cf = 0;\n}\n\n#---------------SHIFT\n\n:sll RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x25 & x=0 & RS1 & reg_or_shcnt { RD=RS1<>reg_or_shcnt; }\n\n:sllx RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x25 & x=1 & RS1 & reg_or_shcnt { RD=RS1<>reg_or_shcnt; }\n\n:sra RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x27 & x=0 & RS1 & reg_or_shcnt { tmp:4=RS1:4; RD=sext(tmp s>> reg_or_shcnt); }\n:srax RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x27 & x=1 & RS1 & reg_or_shcnt { RD=RS1 s>> reg_or_shcnt; }\n\n# ASR read registers (some ASR #s not permitted for rd: 1, 7..15, other #s handled by rd: 3, 5, 6) \nattach variables [ rs_asr ] [ Y _ CCR _ TICK _ _ _\n _ _ _ _ _ _ _ _\n PCR PIC asr18 GSR SOFTINT_SET SOFTINT_CLR SOFTINT TICK_CMPR\n STICK STICK_CMPR asr26 asr27 asr28 asr29 asr30 asr31 ];\n \n# ASR read registers\nrsASR: \"%\"^ASI \tis rs_asr=3 & ASI\t{ tmp:$(SIZE) = zext(ASI); export tmp; }\nrsASR: \"%\"^PC\t\tis rs_asr=5 & PC \t{ tmp:$(SIZE) = inst_start; export tmp; }\nrsASR: \"%\"^FPRS \tis rs_asr=6 & FPRS\t{ tmp:$(SIZE) = zext(FPRS); export tmp; }\nrsASR: \"%\"^rs_asr\tis rs_asr \t{ export rs_asr; }\n\n#---------------RD ASR special register (STBAR instruction must be defined after this instruction)\n:rd rsASR,RD is op=0x2 & RD & op3=0x28 & rsASR & i=0 { RD = rsASR; }\n:rd rsASR,RD is op=0x2 & RD & op3=0x28 & rs_asr=2 & rsASR & i=0 { packflags(RD); } # packed CCR register displayed\n\n# ASR write registers (some ASR #s not permitted for wr: 1, 4, 5, 7..15, other #s handled by wr: 2, 3, 6) \nattach variables [ rd_asr ] [ Y _ _ _ _ _ _ _\n _ _ _ _ _ _ _ _\n PCR PIC asr18 GSR SOFTINT_SET SOFTINT_CLR SOFTINT TICK_CMPR\n STICK STICK_CMPR asr26 asr27 asr28 asr29 asr30 asr31 ];\n \n# ASR write registers\nwrY: \"%\"^Y is rd_asr=0 & Y {export Y;}\nwrCCR: \"%\"^CCR\t\tis rd_asr=2 & CCR { export CCR; } # packed CCR register displayed\nwrASI: \"%\"^ASI\t\tis rd_asr=3 & ASI { export ASI; }\nwrFPRS: \"%\"^FPRS\tis rd_asr=6 & FPRS { export FPRS; }\nwrASR: \"%\"^rd_asr\tis rd_asr { export rd_asr; }\n\n#---------------WR ASR special register (SIR instruction must be defined after this instruction)\n# NOTE: the following ASR register numbers are not allowed: 1, 4, 5, 7..14\n:wr RS1,regorimm,wrCCR is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=2 & wrCCR { local tmp = RS1 ^ regorimm; unpackflags(tmp); }\n:wr RS1,regorimm,wrASI is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=3 & wrASI { local tmp = RS1 ^ regorimm; wrASI = tmp:1; }\n:wr RS1,regorimm,wrFPRS is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=6 & wrFPRS { local tmp = RS1 ^ regorimm; FPRS = tmp:1; }\n:wr RS1,regorimm,wrY is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=0 & wrY { Y = zext(RS1:4 ^ regorimm:4); }\n:wr RS1,regorimm,wrASR is op=0x2 & RS1 & regorimm & op3=0x30 & wrASR { wrASR = RS1 ^ regorimm; }\n\n#---------------MISC\nsethidisp: \"%hi(\"^hi^\")\" is udisp22 [hi=udisp22<<10;] { export *[const]:$(SIZE) hi; }\n\n:sethi sethidisp,RD is RD & op=0x0 & op2=0x4 & sethidisp { RD=sethidisp; }\n\n:popc regorimm, RD is op=0x2 & RD & op3=0x2e & rs1=0 & regorimm { RD = popcount(regorimm); }\n\n:save RS1,regorimm,RD is op=0x2 & RD & op3=0x3c & RS1 & regorimm { local tmp = RS1 + regorimm; save(); RD = tmp; }\n\n:restore RS1,regorimm,RD is op=0x2 & RD & op3=0x3d & RS1 & regorimm { local tmp = RS1 + regorimm; restore(); didrestore=1; RD = tmp; }\n:restore is op=0x2 & rd=0 & op3=0x3d { restore(); didrestore=1; }\n\n# FIXME 'jmpl' can have 'return' in the delayslot to return from a user trap handler\n# @see PR #6285\n\n:return retea is op=0x2 & op3=0x39 & retea { build retea; restore(); delayslot(1); didrestore=1; return [retea]; }\n\n:jmpl retea,RD is op=0x2 & RD & op3=0x38 & retea { build retea; RD = inst_start; delayslot(1); goto [retea]; }\n\n# special case where link register is loaded with return address; functions as indirect call\n:jmpl retea,RD is op=0x2 & RD & prd=15 & op3=0x38 & retea { build retea; RD = inst_start; delayslot(1); call [retea]; }\n:jmpl retea is op=0x2 & rd=0 & op3=0x38 & retea { build retea; delayslot(1); goto [retea]; }\n\n# special case: when returning a structure, some software inserts unimpl instruction after every caller\n# jumps to linkRegister(o7)+12, instead of normal linkregister(o7)+8\n:jmpl retea is op=0x2 & rd=0 & rs1=31 & op3=0x38 & i=1 & simm13=12 & retea { build retea; delayslot(1); return [retea]; }\n:jmpl retea is op=0x2 & rd=0 & rs1=15 & op3=0x38 & i=1 & simm13=12 & retea { build retea; delayslot(1); return [retea]; }\n\n# really jmpl instruction using linkRegister(o7)+8\n:ret is op=0x2 & rd=0 & rs1=31 & op3=0x38 & i=1 & simm13=8 & retea { build retea; delayslot(1); return [retea]; }\n:retl is op=0x2 & rd=0 & rs1=15 & op3=0x38 & i=1 & simm13=8 & retea { build retea; delayslot(1); return [retea]; }\n\ncasa_ea: [RS1]imm_asi is i=0 & RS1 & imm_asi { local tmp1:1 = imm_asi; local tmp = RS1+segment(tmp1); export tmp; }\ncasa_ea: [RS1]%ASI is i=1 & RS1 & ASI { local tmp = RS1+segment(ASI); export tmp; }\n\n:casa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3c & casa_ea & RS2\n{\n\tlocal tmp:4=RD:4;\n\tlocal tmp2:$(SIZE) = RS2;\n\tlocal tmp_ea:$(SIZE) = casa_ea;\n\tRD=zext(*:4 tmp_ea);\n\tif ((tmp2 & 0xFFFFFFFF)!=RD) goto ;\n\t*:4 tmp_ea=tmp;\n\n}\n:casxa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3e & casa_ea & RS2\n{\n\tlocal tmp=RD;\n\tlocal tmp2:$(SIZE) = RS2;\n\tlocal tmp_ea:$(SIZE) = casa_ea;\n\tRD=*:$(SIZE) tmp_ea;\n\tif (tmp2!=RD) goto ;\n\t*:$(SIZE) tmp_ea=tmp;\n\n}\n\n:impdef1 is op=0x2 & op3=0x36 unimpl\n:impdef2 is op=0x2 & op3=0x37 unimpl\n\n:ldstub ea,RD is op=0x3 & RD & op3=0xd & ea\n{\n\tlocal tmp_ea:$(SIZE) = ea;\n\tRD = zext(*:1 tmp_ea);\n\t*:1 tmp_ea = 0xFF;\n}\n:ldstuba ea_alt,RD is op=0x3 & RD & op3=0x1d & ea_alt\n{\n\tlocal tmp_ea:$(SIZE) = ea_alt;\n\tRD = zext(*:1 tmp_ea);\n\t*:1 tmp_ea = 0xFF;\n}\n\n:swap ea,RD is op=0x3 & RD & op3=0xF & ea { local tmp_ea:$(SIZE) = ea; tmp:4=RD:4; RD = zext(*:4 tmp_ea); *:4 tmp_ea = tmp; }\n:swapa ea_alt,RD is op=0x3 & RD & op3=0x1F & ea_alt { local tmp_ea:$(SIZE) = ea_alt; tmp:4=RD:4; RD = zext(*:4 tmp_ea); *:4 tmp_ea = tmp; }\n\n:taddcc RS1,regorimm,RD is op=2 & RD & op3=0x20 & RS1 & regorimm\n{\n\ttaddflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 + regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n:taddcctv RS1,regorimm,RD is op=2 & RD & op3=0x22 & RS1 & regorimm\n{\n\ttaddflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 + regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n:tsubcc RS1,regorimm,RD is op=2 & RD & op3=0x21 & RS1 & regorimm\n{\n\ttsubflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 - regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n:tsubcctv RS1,regorimm,RD is op=2 & RD & op3=0x23 & RS1 & regorimm\n{\n\ttsubflags(RS1,regorimm);\n\tlocal res:$(SIZE) = RS1 - regorimm;\n\tzeroflags(res);\n\tRD = res;\n}\n\ntcc: icc is cc1_4=0 & cc0_4=0 & icc { export icc; }\ntcc: xcc is cc1_4=1 & cc0_4=0 & xcc { export xcc; }\n\nTICC: \"%icc\" is cc1_4=0 &cc0_4=0 { }\nTICC: \"%xcc\" is cc1_4=1 &cc0_4=0 { }\n\ntrap: RS1+RS2 is i=0 & RS1 & RS2 { local tmp = ((RS1 + RS2) & 0x7F); export tmp; }\ntrap: RS1+swtrap is i=1 & RS1 & swtrap { local tmp = ((RS1 + swtrap) & 0x7F); export tmp; }\n\n:t^tcc TICC, trap is op=0x2 & op3=0x3a & tcc & TICC & trap\n{\n\tif (!tcc) goto inst_next;\n\tlocal dest:$(SIZE) = sw_trap(trap);\n\t# trap should fall thru by default, can be over-ridden to a branch/call-return\n\tcall [dest];\n}\n\nmembar_mask: is cmask & mmask { tmp:1 = (cmask << 4) | mmask; export tmp; }\n\n:membar membar_mask is op=0x2 & rd=0 & op3=0x28 & rs1=0xF & i=1 & membar_mask {}\n\n:stbar is op=0x2 & rd=0 & op3=0x28 & rs1=0xF & i=0 {}\n\n:sir simm13 is op=0x2 & rd=0xF & op3=0x30 & rs1=0x0 & i=1 & simm13 { reset(); }\n\nattach variables [ prs1 prd ] [ TPC1 TNPC1 TSTATE1 TT1 TCK TBA PSTATE TL \n \t PIL CWP CANSAVE CANRESTORE CLEANWIN OTHERWIN WSTATE FQ\n GL _ _ _ _ _ _ _ _ _ _ _ _ _ _ VER ];\n\ntnpc: \"%tnpc\" is fcn { local reloc = zext(TL == 1)*&TNPC1 + zext(TL == 2)*&TNPC2 + zext(TL == 3)*&TNPC3 + zext(TL ==4)*&TNPC4; export reloc; }\n\ntpc: \"%tpc\" is fcn { local reloc = zext(TL == 1)*&TPC1 + zext(TL == 2)*&TPC2 + zext(TL == 3)*&TPC3 + zext(TL ==4)*&TPC4; export reloc; }\n\ntt: \"%tt\" is fcn { local tmp = zext(TL == 1)* &TT1 + zext(TL == 2)*&TT2 + zext(TL == 3)*&TT3 + zext(TL ==4)*&TT4; export tmp; }\n\ntstate: \"%tstate\" is fcn { local tmp = zext(TL == 1)* &TSTATE1 + zext(TL == 2)* &TSTATE2 + zext(TL == 3)* &TSTATE3 + zext(TL==4)* &TSTATE4; export tmp; }\n\n# prs1 is same bits as rs1\n# prd is same bits as rd\n:rdpr prs1,RD is op=0x2 & RD & op3=0x2A & prs1 {RD = prs1; }\n:rdpr tpc,RD is op=0x2 & prs1 = 0 & RD & op3=0x2A & tpc { RD = *[register]:$(SIZE) tpc; }\n:rdpr tnpc,RD is op=0x2 & prs1 = 1 & RD & op3=0x2A & tnpc {RD = *[register]:$(SIZE) tnpc; }\n:rdpr tt,RD is op=0x2 & prs1 = 2 & RD & op3=0x2A & tt { RD = *[register]:$(SIZE) tt; }\n:rdpr tstate,RD is op=0x2 & prs1 = 3 & RD & op3=0x2A & tstate {RD = *[register]:$(SIZE) tstate;}\n\n:wrpr RS1,regorimm,prd is op=0x2 & prd & op3=0x32 & RS1 & regorimm {prd = RS1^regorimm; }\n:wrpr RS1,regorimm,tpc is op=0x2 & prd = 0 & op3=0x32 & RS1 & regorimm & tpc { *[register]:$(SIZE) tpc = RS1^regorimm; }\n:wrpr RS1,regorimm,tnpc is op=0x2 & prd = 1 & op3=0x32 & RS1 & regorimm & tnpc { *[register]:$(SIZE) tnpc = RS1^regorimm; }\n:wrpr RS1,regorimm,tstate is op=0x2 & prd = 2 & op3=0x32 & RS1 & regorimm & tstate { *[register]:$(SIZE) tstate = RS1^regorimm; }\n:wrpr RS1,regorimm,tt is op=0x2 & prd = 3 & op3=0x32 & RS1 & regorimm & tt { *[register]:$(SIZE) tt = RS1^regorimm; }\n\nhpstate: \"%hpstate\" is fcn { local reloc = zext(TL == 1)*&HPSTATE1 + zext(TL == 2)*&HPSTATE2 + zext(TL == 3)*&HPSTATE3 + zext(TL ==4)*&HPSTATE4; export reloc; }\n\nhtstate: \"%htstate\" is fcn { local reloc = zext(TL == 1)*&HTSTATE1 + zext(TL == 2)*&HTSTATE2 + zext(TL == 3)*&HTSTATE3 + zext(TL ==4)*&HTSTATE4; export reloc; }\n\nhintp: \"%hintp\" is fcn { local reloc = zext(TL == 1)*&HINTP1 + zext(TL == 2)*&HINTP2 + zext(TL == 3)*&HINTP3 + zext(TL ==4)*&HINTP4; export reloc; }\n\nhtba: \"%htba\" is fcn { local reloc = zext(TL == 1)*&HTBA1 + zext(TL == 2)*&HTBA2 + zext(TL == 3)*&HTBA3 + zext(TL ==4)*&HTBA4; export reloc; }\n\nhver: \"%hver\" is fcn { local reloc = zext(TL == 1)*&HVER1 + zext(TL == 2)*&HVER2 + zext(TL == 3)*&HVER3 + zext(TL ==4)*&HVER4; export reloc; }\n\nhsys_tick_cmpr: \"%hstick_cmpr\" is fcn { local reloc = zext(TL == 1)*&HSTICK_CMPR1 + zext(TL == 2)*&HSTICK_CMPR2 + zext(TL == 3)*&HSTICK_CMPR3 + zext(TL ==4)*&HSTICK_CMPR4; export reloc; }\n\nresv30: \"%resv30\" is fcn { local reloc = zext(TL == 1)*&RESV30_1 + zext(TL == 2)*&RESV30_2 + zext(TL == 3)*&RESV30_3 + zext(TL ==4)*&RESV30_4; export reloc; }\n\n:rdhpr hpstate,RD is op=0x2 & prs1 = 0 & RD & op3=0x29 & hpstate { RD = *[register]:$(SIZE) hpstate; }\n:rdhpr htstate,RD is op=0x2 & prs1 = 1 & RD & op3=0x29 & htstate { RD = *[register]:$(SIZE) htstate; }\n:rdhpr hintp,RD is op=0x2 & prs1 = 3 & RD & op3=0x29 & hintp { RD = *[register]:$(SIZE) hintp; }\n:rdhpr htba,RD is op=0x2 & prs1 = 5 & RD & op3=0x29 & htba { RD = *[register]:$(SIZE) htba; }\n:rdhpr hver,RD is op=0x2 & prs1 = 6 & RD & op3=0x29 & hver { RD = *[register]:$(SIZE) hver; }\n:rdhpr hsys_tick_cmpr,RD is op=0x2 & prs1 = 31 & RD & op3=0x29 & hsys_tick_cmpr { RD = *[register]:$(SIZE) hsys_tick_cmpr; }\n:rdhpr resv30,RD is op=0x2 & prs1 = 30 & RD & op3=0x29 & resv30 { RD = *[register]:$(SIZE) resv30; }\n\n:wrhpr RS1,regorimm,hpstate is op=0x2 & prd = 0 & op3=0x33 & RS1 & regorimm & hpstate { *[register]:$(SIZE) hpstate = RS1^regorimm; }\n:wrhpr RS1,regorimm,htstate is op=0x2 & prd = 1 & op3=0x33 & RS1 & regorimm & htstate { *[register]:$(SIZE) htstate = RS1^regorimm; }\n:wrhpr RS1,regorimm,hintp is op=0x2 & prd = 3 & op3=0x33 & RS1 & regorimm & hintp { *[register]:$(SIZE) hintp = RS1^regorimm; }\n:wrhpr RS1,regorimm,htba is op=0x2 & prd = 5 & op3=0x33 & RS1 & regorimm & htba { *[register]:$(SIZE) htba = RS1^regorimm; }\n:wrhpr RS1,regorimm,hsys_tick_cmpr is op=0x2 & prd = 31 & op3=0x33 & RS1 & regorimm & hsys_tick_cmpr { *[register]:$(SIZE) hsys_tick_cmpr = RS1^regorimm; }\n:wrhpr RS1,regorimm,resv30 is op=0x2 & prd = 30 & op3=0x33 & RS1 & regorimm & resv30 { *[register]:$(SIZE) resv30 = RS1^regorimm; }\n\n\n\n:done is op = 2 & fcn = 0 & op3 = 0x3e & tnpc {TL=TL-1;return [tnpc]; }\n:retry is op = 2 & fcn = 1 & op3 = 0x3e & tpc {TL=TL-1;return [tpc]; }\n\n:flush ea is op = 2 & op3 = 0x3b & ea {}\n:flushw is op = 2 & op3 = 0x2b & i = 0 {}\n\ndefine pcodeop IllegalInstructionTrap;\n\n:illtrap const22 is op = 0 & op2 = 0 & const22 {\n\tlocal dest:$(SIZE) = IllegalInstructionTrap(const22:4);\n\t# trap should not fall thru by default, can be over-ridden to a call\n\tgoto [dest];\n}\n\n:prefetch ea,fcn is op=3 & fcn & op3 = 0x2d & ea {}\n:prefetcha ea_alt,fcn is op=3 & fcn & op3 = 0x3d & ea_alt {}\n:restored is op = 2 & fcn=1 & op3 = 0x31 {}\n:saved is op = 2 & fcn = 0 & op3 = 0x31 {}\n\nattach variables [fsrd fsrs1 fsrs2 ] [ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7\n fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15\n fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23\n fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31 ];\n \nattach variables [fdrd fdrs1 fdrs2 ] [ fd0 fd32 fd2 fd34 fd4 fd36 fd6 fd38\n fd8 fd40 fd10 fd42 fd12 fd44 fd14 fd46\n fd16 fd48 fd18 fd50 fd20 fd52 fd22 fd54\n fd24 fd56 fd26 fd58 fd28 fd60 fd30 fd62 ];\n \nattach variables [fqrd fqrs1 fqrs2 ] [ fq0 _ fq32 _ fq4 _ fq36 _ fq8 _ fq40 _ fq12 _ fq44\n _ fq16 _ fq48 _ fq20 _ fq52 _ fq24 _ fq56 _ fq28 _ fq60 _];\n\ndefine pcodeop ld;\ndefine pcodeop ldd;\ndefine pcodeop ldq;\ndefine pcodeop ldx;\ndefine pcodeop lda;\ndefine pcodeop ldda;\ndefine pcodeop ldqa;\ndefine pcodeop ld_fsr;\ndefine pcodeop ldx_fsr;\n\ndefine pcodeop st;\ndefine pcodeop std;\ndefine pcodeop stq;\ndefine pcodeop stx;\ndefine pcodeop st_fsr;\ndefine pcodeop stx_fsr;\n\ndefine pcodeop sta;\ndefine pcodeop stda;\ndefine pcodeop stqa;\n\n:fabss fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x9 & fsrs2 { fsrd = abs(fsrs2); }\n:fabsd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xa & fdrs2 { fdrd = abs(fdrs2); }\n:fabsq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xb & fqrs2 { fqrd = abs(fqrs2); }\n\n:fadds fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x41 & fsrs2 { fsrd = fsrs1 f+ fsrs2; }\n:faddd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x42 & fdrs2 { fdrd = fdrs1 f+ fdrs2; }\n:faddq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x43 & fqrs2 { fqrd = fqrs1 f+ fqrs2; }\n\n:fdivs fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x4d & fsrs2 { fsrd = fsrs1 f/ fsrs2; }\n:fdivd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x4e & fdrs2 { fdrd = fdrs1 f/ fdrs2; }\n:fdivq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x4f & fqrs2 { fqrd = fqrs1 f/ fqrs2; }\n\n:fdmulq fdrs1,fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fdrs1 & opf=0x6e & fdrs2 {\n\ttmp1:16 = float2float(fdrs1);\n\ttmp2:16 = float2float(fdrs2);\n\tfqrd = tmp1 f* tmp2;\n}\n:fsmuld fsrs1,fsrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fsrs1 & opf=0x69 & fsrs2 {\n\ttmp1:8 = float2float(fsrs1);\n\ttmp2:8 = float2float(fsrs2);\n\tfdrd = tmp1 f* tmp2;\n}\n\n:fitos fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xc4 & fsrs2 { fsrd = int2float(fsrs2); }\n:fitod fsrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xc8 & fsrs2 { fdrd = int2float(fsrs2); }\n:fitoq fsrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xcc & fsrs2 { fqrd = int2float(fsrs2); }\n\n:fmovs fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x1 & fsrs2 { fsrd = fsrs2; }\n:fmovd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x2 & fdrs2 { fdrd = fdrs2; }\n:fmovq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x3 & fqrs2 { fqrd = fqrs2; }\n\n:fmuls fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x49 & fsrs2 { fsrd = fsrs1 f* fsrs2; }\n:fmuld fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x4a & fdrs2 { fdrd = fdrs1 f* fdrs2; }\n:fmulq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x4b & fqrs2 { fqrd = fqrs1 f* fqrs2; }\n\n:fnegs fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x5 & fsrs2 { fsrd = f- fsrs2; }\n:fnegd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x6 & fdrs2 { fdrd = f- fdrs2; }\n:fnegq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x7 & fqrs2 { fqrd = f- fqrs2; }\n\n:fsubs fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x45 & fsrs2 { fsrd = fsrs1 f- fsrs2; }\n:fsubd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x46 & fdrs2 { fdrd = fdrs1 f- fdrs2; }\n:fsubq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x47 & fqrs2 { fqrd = fqrs1 f- fqrs2; }\n\n:fxtos fdrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x84 & fdrs2 { fsrd = int2float(fdrs2); }\n:fxtod fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x88 & fdrs2 { fdrd = int2float(fdrs2); }\n:fxtoq fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x8c & fdrs2 { fqrd = int2float(fdrs2); }\n\n:fstoi fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xd1 & fsrs2 { fsrd = trunc(fsrs2); }\n:fdtoi fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xd2 & fdrs2 { fdrd = trunc(fdrs2); }\n:fqtoi fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xd3 & fqrs2 { fqrd = trunc(fqrs2); }\n\n:fstox fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x81 & fsrs2 { fsrd = trunc(fsrs2); }\n:fdtox fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x82 & fdrs2 { fdrd = trunc(fdrs2); }\n:fqtox fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x83 & fqrs2 { fqrd = trunc(fqrs2); }\n\n:fstod fsrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xc9 & fsrs2 { fdrd = float2float(fsrs2); }\n:fstoq fsrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xcd & fsrs2 { fqrd = float2float(fsrs2); }\n\n:fdtos fdrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xc6 & fdrs2 { fsrd = float2float(fdrs2); }\n:fdtoq fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xce & fdrs2 { fqrd = float2float(fdrs2); }\n\n:fqtos fdrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xc7 & fdrs2 { fsrd = float2float(fdrs2); }\n:fqtod fqrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xcb & fqrs2 { fdrd = float2float(fqrs2); }\n\n:fsqrts fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x29 & fsrs2 { fsrd = sqrt(fsrs2); }\n:fsqrtd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x2a & fdrs2 { fdrd = sqrt(fdrs2); }\n:fsqrtq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x2b & fqrs2 { fqrd = sqrt(fqrs2); }\n\n:ld ea,fsrd is op=3 & fsrd & op3=0x20 & ea { fsrd = *:4 ea; }\n:ldd ea,fdrd is op=3 & fdrd & op3=0x23 & ea { fdrd = *:8 ea; }\n:ldq ea,fqrd is op=3 & fqrd & op3=0x22 & ea { fqrd = *:16 ea; }\n:ld ea,\"%fsr\" is op=3 & op3=0x21 & rd=0 & ea { fsr = *:2 ea; }\n:ldx ea,\"%fsr\" is op=3 & op3=0x21 & rd=1 & ea { fsr = *:2 ea; }\n\n:lda ea_alt,fsrd is op=3 & fsrd & op3=0x30 & ea_alt { fsrd = *:4 ea_alt; }\n:ldda ea_alt,fdrd is op=3 & fdrd & op3=0x33 & ea_alt { fdrd = *:8 ea_alt; }\n:ldqa ea_alt,fqrd is op=3 & fqrd & op3=0x32 & ea_alt { fqrd = *:16 ea_alt; }\n\n:st fsrd,ea is op=3 & fsrd & op3=0x24 & ea { *ea = fsrd:4; }\n:std fdrd,ea is op=3 & fdrd & op3=0x27 & ea { *ea = fdrd:8; }\n:stq fqrd,ea is op=3 & fqrd & op3=0x26 & ea { *ea = fqrd:16; }\n:st \"%fsr\",ea is op=3 & op3=0x25 & rd=0 & ea { *ea = fsr; }\n:stx \"%fsr\",ea is op=3 & op3=0x25 & rd=1 & ea { *ea = fsr; }\n\n:sta fsrd,ea_alt is op=3 & fsrd & op3=0x34 & ea_alt { *ea_alt = fsrd:4; }\n:stda fdrd,ea_alt is op=3 & fdrd & op3=0x37 & ea_alt { *ea_alt = fdrd:8; }\n:stqa fqrd,ea_alt is op=3 & fqrd & op3=0x36 & ea_alt { *ea_alt = fqrd:16; }\n\nfcc0_or_fccn: is op2=6 { export fcc0; }\nfcc0_or_fccn: is op2=5 & fccn { export fccn; }\n\nfcc: \"u\" is cond=0x7 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 3); export tmp; }\nfcc: \"g\" is cond=0x6 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 2); export tmp; }\nfcc: \"ug\" is cond=0x5 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 2 || fcc0_or_fccn == 3); export tmp; }\nfcc: \"l\" is cond=0x4 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1); export tmp; }\nfcc: \"ul\" is cond=0x3 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1 || fcc0_or_fccn ==3); export tmp; }\nfcc: \"lg\" is cond=0x2 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1 || fcc0_or_fccn ==2); export tmp; }\nfcc: \"ne\" is cond=0x1 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1 || fcc0_or_fccn == 2 || fcc0_or_fccn ==3); export tmp; }\nfcc: \"e\" is cond=0x9 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0); export tmp; }\nfcc: \"ue\" is cond=0xa & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 3); export tmp; }\nfcc: \"ge\" is cond=0xb & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 2); export tmp; }\nfcc: \"uge\" is cond=0xc & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 2 || fcc0_or_fccn == 3); export tmp; }\nfcc: \"le\" is cond=0xd & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 1); export tmp; }\nfcc: \"ule\" is cond=0xe & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 1 || fcc0_or_fccn ==3); export tmp; }\nfcc: \"o\" is cond=0xf & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 1 || fcc0_or_fccn ==2); export tmp; }\n\n:fba reloff is op=0x0 & op2=0x6 & a=0x0 & cond=0x8 & reloff { delayslot(1); goto reloff; }\n:\"fba,a\" reloff is op=0x0 & op2=0x6 & a=0x1 & cond=0x8 & reloff { goto reloff; }\n\n:fbn reloff is op=0x0 & op2=0x6 & a=0x0 & cond=0x0 & reloff { }\n:\"fbn,a\" reloff,skip is op=0x0 & op2=0x6 & a=0x1 & cond=0x0 & reloff & skip { goto skip; }\n\n:fb^fcc reloff is op=0x0 & op2=0x6 & a=0x0 & fcc & reloff { delayslot(1); if (fcc) goto reloff; }\n:fb^fcc^\",a\" reloff is op=0x0 & op2=0x6 & a=0x1 & fcc & reloff { if (!fcc) goto inst_next; delayslot(1); goto reloff; }\n\n:fb^fcc^predict \"%\"fccn,reloff64 is op=0x0 & op2=0x5 & a=0x0 & fcc & reloff64 & predict & fccn { delayslot(1); if (fcc) goto reloff64; }\n:fb^fcc^\",a\"^predict \"%\"^fccn,reloff64 is op=0x0 & op2=0x5 & a=0x1 & fcc & reloff64 & predict & fccn { if (!fcc) goto inst_next; delayslot(1); goto reloff64; }\n\nmacro fcmp(f1, f2, fccn) {\n\t# fcc value | relation\n\t# 0 | f1 = f2\n\t# 1 | f1 < f2\n\t# 2 | f1 > f2\n\t# 3 | f1 or f2 NaN\n\tfccn = (1*(f1 f< f2)) + (2*(f1 f> f2)) + (3*(nan(f1) || nan(f2)));\n}\n\n:fcmps %fccn2,fsrs1,fsrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x51 & fsrs1 & fsrs2 { fcmp(fsrs1, fsrs2, fccn2); }\n:fcmpd %fccn2,fdrs1,fdrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x52 & fdrs1 & fdrs2 { fcmp(fdrs1, fdrs2, fccn2); }\n:fcmpq %fccn2,fqrs1,fqrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x53 & fqrs1 & fqrs2 { fcmp(fqrs1, fqrs2, fccn2); }\n\n:fcmpes %fccn2,fsrs1,fsrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x55 & fsrs1 & fsrs2 { fcmp(fsrs1, fsrs2, fccn2); }\n:fcmped %fccn2,fdrs1,fdrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x56 & fdrs1 & fdrs2 { fcmp(fdrs1, fdrs2, fccn2); }\n:fcmpeq %fccn2,fqrs1,fqrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x57 & fqrs1 & fqrs2 { fcmp(fqrs1, fqrs2, fccn2); }\n\nZ: is opf_cc=4 { export i_zf; }\nZ: is opf_cc=6 { export x_zf; }\n\nC: is opf_cc=4 { export i_cf; }\nC: is opf_cc=6 { export x_cf; }\n\nN: is opf_cc=4 { export i_nf; }\nN: is opf_cc=6 { export x_nf; }\n\nV: is opf_cc=4 { export i_vf; }\nV: is opf_cc=6 { export x_vf; }\n\n# floating-point move with integer condition codes\nfmicc: \"a\" is cond4=0x8 { tmp:1=1; export tmp; }\nfmicc: \"n\" is cond4=0x0 { tmp:1=0; export tmp; }\nfmicc: \"ne\" is cond4=0x9 & Z { tmp:1=!Z; export tmp; }\nfmicc: \"e\" is cond4=0x1 & Z { export Z; }\nfmicc: \"g\" is cond4=0xa & Z & N & V { tmp:1=!(Z|(N^V)); export tmp; }\nfmicc: \"le\" is cond4=0x2 & Z & N & V { tmp:1= (Z|(N^V)); export tmp; }\nfmicc: \"ge\" is cond4=0xb & N & V { tmp:1=!(N^V); export tmp; }\nfmicc: \"l\" is cond4=0x3 & N & V { tmp:1= (N^V); export tmp; }\nfmicc: \"gu\" is cond4=0xc & C & Z { tmp:1=!(C|Z); export tmp; }\nfmicc: \"leu\" is cond4=0x4 & C & Z { tmp:1= (C|Z); export tmp; }\nfmicc: \"cc\" is cond4=0xd & C { tmp:1=!C; export tmp; }\nfmicc: \"cs\" is cond4=0x5 & C { tmp:1=C; export tmp; }\nfmicc: \"pos\" is cond4=0xe & N { tmp:1=!N; export tmp; }\nfmicc: \"neg\" is cond4=0x6 & N { tmp:1=N; export tmp; }\nfmicc: \"vc\" is cond4=0xf & V { tmp:1=!V; export tmp; }\nfmicc: \"vs\" is cond4=0x7 & V { tmp:1=V; export tmp; }\n\n# floating-point move with floating-point condition codes\nfmfcc: \"a\" is cond4=0x8 & fccn_4 { tmp:1=1:1; export tmp; }\nfmfcc: \"n\" is cond4=0x0 & fccn_4 { tmp:1=0:1; export tmp; }\nfmfcc: \"u\" is cond4=0x7 & fccn_4 { tmp:1=(fccn_4 == 3); export tmp; }\nfmfcc: \"g\" is cond4=0x6 & fccn_4 { tmp:1=(fccn_4 == 2); export tmp; }\nfmfcc: \"ug\" is cond4=0x5 & fccn_4 { tmp:1=(fccn_4 == 2 || fccn_4 == 3); export tmp; }\nfmfcc: \"l\" is cond4=0x4 & fccn_4 { tmp:1=(fccn_4 == 1); export tmp; }\nfmfcc: \"ul\" is cond4=0x3 & fccn_4 { tmp:1=(fccn_4 == 1 || fccn_4 ==3); export tmp; }\nfmfcc: \"lg\" is cond4=0x2 & fccn_4 { tmp:1=(fccn_4 == 1 || fccn_4 ==2); export tmp; }\nfmfcc: \"ne\" is cond4=0x1 & fccn_4 { tmp:1=(fccn_4 == 1 || fccn_4 == 2 || fccn_4 ==3); export tmp; }\nfmfcc: \"e\" is cond4=0x9 & fccn_4 { tmp:1=(fccn_4 == 0); export tmp; }\nfmfcc: \"ue\" is cond4=0xa & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 3); export tmp; }\nfmfcc: \"ge\" is cond4=0xb & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 2); export tmp; }\nfmfcc: \"uge\" is cond4=0xc & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 2 || fccn_4 == 3); export tmp; }\nfmfcc: \"le\" is cond4=0xd & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 1); export tmp; }\nfmfcc: \"ule\" is cond4=0xe & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 1 || fccn_4 ==3); export tmp; }\nfmfcc: \"o\" is cond4=0xf & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 1 || fccn_4 ==2); export tmp; }\n\nfmfcc_or_fmicc: fmfcc is bit13=0 & fmfcc { export fmfcc; }\nfmfcc_or_fmicc: fmicc is bit13=1 & fmicc { export fmicc; }\n\nfcc_icc_xcc: \"%\"^fccn_4 is bit13=0 & fccn_4 { }\nfcc_icc_xcc: \"%icc\" is bit13=1 & opf_cc=4 { }\nfcc_icc_xcc: \"%xcc\" is bit13=1 & opf_cc=6 { }\n\n:fmovs^fmfcc_or_fmicc fcc_icc_xcc,fsrs2,fsrd is op=2 & op3=0x35 & bit18=0 & fmfcc_or_fmicc & fcc_icc_xcc & opf_low=1 & fsrs2 & fsrd\n { if !(fmfcc_or_fmicc) goto ; fsrd = fsrs2; }\n:fmovd^fmfcc_or_fmicc fcc_icc_xcc,fdrs2,fdrd is op=2 & op3=0x35 & bit18=0 & fmfcc_or_fmicc & fcc_icc_xcc & opf_low=2 & fdrs2 & fdrd\n { if !(fmfcc_or_fmicc) goto ; fdrd = fdrs2; }\n:fmovq^fmfcc_or_fmicc fcc_icc_xcc,fqrs2,fqrd is op=2 & op3=0x35 & bit18=0 & fmfcc_or_fmicc & fcc_icc_xcc & opf_low=3 & fqrs2 & fqrd\n { if !(fmfcc_or_fmicc) goto ; fqrd = fqrs2; }\n\n#conditional integer moves with integer conditions defined in constructor :mov^m_cc \n:mov^fmfcc \" %\"^fccn_4,regorimm11,RD is op=2 & RD & op3=0x2c & bit18=0 & fmfcc & fccn_4 & regorimm11\n{ \n\tif !(fmfcc) goto ; \n\tRD = regorimm11; \n\n}\n\nfmovrcc: \"z\" is rcond3=0x1 & RS1 { tmp:1 = (RS1 == 0); export tmp; }\nfmovrcc: \"lez\" is rcond3=0x2 & RS1 { tmp:1 = (RS1 s<= 0); export tmp; }\nfmovrcc: \"lz\" is rcond3=0x3 & RS1 { tmp:1 = (RS1 s< 0); export tmp; }\nfmovrcc: \"nz\" is rcond3=0x5 & RS1 { tmp:1 = (RS1 != 0); export tmp; }\nfmovrcc: \"gz\" is rcond3=0x6 & RS1 { tmp:1 = (RS1 s> 0); export tmp; }\nfmovrcc: \"gez\" is rcond3=0x7 & RS1 { tmp:1 = (RS1 s>= 0); export tmp; }\n\n:fmovrs^fmovrcc RS1,fsrs2,fsrd is op=2 & fsrd & op3=0x35 & bit13=0 & RS1 & fmovrcc & opf_low_5_9=0x5 & fsrs2\n { if !(fmovrcc) goto ; fsrd = fsrs2; }\n:fmovrd^fmovrcc RS1,fdrs2,fdrd is op=2 & fdrd & op3=0x35 & bit13=0 & RS1 & fmovrcc & opf_low_5_9=0x6 & fdrs2\n { if !(fmovrcc) goto ; fdrd = fdrs2; }\n:fmovrq^fmovrcc RS1,fqrs2,fqrd is op=2 & fqrd & op3=0x35 & bit13=0 & RS1 & fmovrcc & opf_low_5_9=0x7 & fqrs2\n { if !(fmovrcc) goto ; fqrd = fqrs2; }\n\n# Include support for the VIS1 vector instructions\n@include \"SparcVIS.sinc\"\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9_32.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t \n\t \n\t\n\t\n\t \n\t \n\t\n\t\n\t \n\t \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t \n\t \n\t\n\t\n\t \n\t \n\t\n\t\n\t \n\t \n\t\n\t\n\t \n\t \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9_32.slaspec", "content": "\n@define SIZE \"4\"\n\n@include \"SparcV9.sinc\"\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9_64.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n\t\t \n\t\t \n\t\t\n\t\t\n \n \n \n \n\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcV9_64.slaspec", "content": "@define SIZE \"8\"\n\n@include \"SparcV9.sinc\"\n\n\n\n" }, { "path": "pypcode/processors/Sparc/data/languages/SparcVIS.sinc", "content": "# The Sparc VIS1 vector instruction set\n# The opcodes below that have their pcodeop uncommented have been checked to make sure\n# that the register width is correct. If the call to the pcodeop is still commented out\n# that means that the register width may be incorrect. For example, a call to a 64 bit\n# floating point register may really use a 32 bit register.\n# VIS2 or VIS2+ instructions are not included in this file.\n\ndefine pcodeop alignaddr;\n:alignaddr RS1,RS2,rd is opf = 0x18 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = alignaddr(RS1,RS2);\n}\n\ndefine pcodeop alignaddrl;\n:alignaddrl RS1,RS2,rd is opf = 0x1a & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = alignaddrl(RS1,RS2);\n}\n\ndefine pcodeop array16;\n:array16 RS1,RS2,rd is opf = 0x12 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = array16(RS1,RS2);\n}\n\ndefine pcodeop array32;\n:array32 RS1,RS2,rd is opf = 0x14 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = array32(RS1,RS2);\n}\n\ndefine pcodeop array8;\n:array8 RS1,RS2,rd is opf = 0x10 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = array8(RS1,RS2);\n}\n\ndefine pcodeop edge16cc;\n:edge16cc RS1,RS2,rd is opf = 0x4 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = edge16cc(RS1,RS2);\n}\n\ndefine pcodeop edge16lcc;\n:edge16lcc RS1,RS2,rd is opf = 0x6 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = edge16lcc(RS1,RS2);\n}\n\ndefine pcodeop edge32cc;\n:edge32cc RS1,RS2,rd is opf = 0x8 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = edge32cc(RS1,RS2);\n}\n\ndefine pcodeop edge32lcc;\n:edge32lcc RS1,RS2,rd is opf = 0xa & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = edge32lcc(RS1,RS2);\n}\n\ndefine pcodeop edge8cc;\n:edge8cc RS1,RS2,rd is opf = 0x0 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = edge8cc(RS1,RS2);\n}\n\ndefine pcodeop edge8lcc;\n:edge8lcc RS1,RS2,rd is opf = 0x2 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd\n{\n\trd = edge8lcc(RS1,RS2);\n}\n\ndefine pcodeop faligndata;\n:faligndata fdrs1,fdrs2,fdrd is opf = 0x48 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = faligndata(fdrs1,fdrs2);\n}\n\ndefine pcodeop fandd;\n:fandd fdrs1,fdrs2,fdrd is opf = 0x70 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fandd(fdrs1,fdrs2);\n}\n\ndefine pcodeop fandnot1d;\n:fandnot1d fdrs1,fdrs2,fdrd is opf = 0x68 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fandnot1d(fdrs1,fdrs2);\n}\n\ndefine pcodeop fandnot1s;\n:fandnot1s fdrs1,fdrs2,fdrd is opf = 0x69 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fandnot1s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fandnot2d;\n:fandnot2d fdrs1,fdrs2,fdrd is opf = 0x64 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fandnot2d(fdrs1,fdrs2);\n}\n\ndefine pcodeop fandnot2s;\n:fandnot2s fdrs1,fdrs2,fdrd is opf = 0x65 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fandnot2s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fands;\n:fands fdrs1,fdrs2,fdrd is opf = 0x71 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fands(fdrs1,fdrs2);\n}\n\ndefine pcodeop fexpand;\n:fexpand fsrs2,fdrd is opf = 0x4d & op3 = 0x36 & op = 0x2 & fsrs2 & fdrd\n{\n\tfdrd = fexpand(fsrs2);\n}\n\ndefine pcodeop fmul8sux16;\n:fmul8sux16 fdrs1,fdrs2,fdrd is opf = 0x36 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmul8sux16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fmul8ulx16;\n:fmul8ulx16 fdrs1,fdrs2,fdrd is opf = 0x37 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmul8ulx16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fmul8x16;\n:fmul8x16 fdrs1,fdrs2,fdrd is opf = 0x31 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmul8x16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fmul8x16al;\n:fmul8x16al fdrs1,fdrs2,fdrd is opf = 0x35 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmul8x16al(fdrs1,fdrs2);\n}\n\ndefine pcodeop fmul8x16au;\n:fmul8x16au fdrs1,fdrs2,fdrd is opf = 0x33 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmul8x16au(fdrs1,fdrs2);\n}\n\ndefine pcodeop fmuld8sux16;\n:fmuld8sux16 fdrs1,fdrs2,fdrd is opf = 0x38 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmuld8sux16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fmuld8ulx16;\n:fmuld8ulx16 fdrs1,fdrs2,fdrd is opf = 0x39 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fmuld8ulx16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fnandd;\n:fnandd fdrs1,fdrs2,fdrd is opf = 0x6e & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fnandd(fdrs1,fdrs2);\n}\n\ndefine pcodeop fnands;\n:fnands fdrs1,fdrs2,fdrd is opf = 0x6f & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fnands(fdrs1,fdrs2);\n}\n\ndefine pcodeop fnord;\n:fnord fdrs1,fdrs2,fdrd is opf = 0x62 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fnord(fdrs1,fdrs2);\n}\n\ndefine pcodeop fnors;\n:fnors fdrs1,fdrs2,fdrd is opf = 0x63 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fnors(fdrs1,fdrs2);\n}\n\ndefine pcodeop fnot1d;\n:fnot1d fdrs1,fdrd is opf = 0x6a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd\n{\n\tfdrd = fnot1d(fdrs1);\n}\n\ndefine pcodeop fnot1s;\n:fnot1s fdrs1,fdrd is opf = 0x6b & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd\n{\n\tfdrd = fnot1s(fdrs1);\n}\n\ndefine pcodeop fnot2d;\n:fnot2d fdrs2,fdrd is opf = 0x66 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd\n{\n\tfdrd = fnot2d(fdrs2);\n}\n\ndefine pcodeop fnot2s;\n:fnot2s fdrs2,fdrd is opf = 0x67 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd\n{\n\tfdrd = fnot2s(fdrs2);\n}\n\ndefine pcodeop foned;\n:foned fdrd is opf = 0x7e & op3 = 0x36 & op = 0x2 & fdrd\n{\n\tfdrd = foned();\n}\n\ndefine pcodeop fones;\n:fones fsrd is opf = 0x7f & op3 = 0x36 & op = 0x2 & fsrd\n{\n\tfsrd = fones();\n}\n\ndefine pcodeop ford;\n:ford fdrs1,fdrs2,fdrd is opf = 0x7c & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = ford(fdrs1,fdrs2);\n}\n\ndefine pcodeop fornot1d;\n:fornot1d fdrs1,fdrs2,fdrd is opf = 0x7a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fornot1d(fdrs1,fdrs2);\n}\n\ndefine pcodeop fornot1s;\n:fornot1s fdrs1,fdrs2,fdrd is opf = 0x7b & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fornot1s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fornot2d;\n:fornot2d fdrs1,fdrs2,fdrd is opf = 0x76 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fornot2d(fdrs1,fdrs2);\n}\n\ndefine pcodeop fornot2s;\n:fornot2s fdrs1,fdrs2,fdrd is opf = 0x77 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fornot2s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fors;\n:fors fdrs1,fdrs2,fdrd is opf = 0x7d & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fors(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpack16;\n:fpack16 fdrs2,fsrd is opf = 0x3b & op3=0x36 & op = 0x2 & fdrs2 & fsrd\n{\n\tfsrd = fpack16(fdrs2);\n}\n\ndefine pcodeop fpack32;\n:fpack32 fdrs1,fdrs2,fdrd is opf = 0x3a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpack32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpackfix;\n:fpackfix fdrs2,fsrd is opf = 0x3d & op3 = 0x36 & op = 0x2 & fdrs2 & fsrd\n{\n\tfsrd = fpackfix(fdrs2);\n}\n\ndefine pcodeop fpadd16;\n:fpadd16 fdrs1,fdrs2,fdrd is opf = 0x50 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpadd16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpadd16s;\n:fpadd16s fdrs1,fdrs2,fdrd is opf = 0x51 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpadd16s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpadd32;\n:fpadd32 fdrs1,fdrs2,fdrd is opf = 0x52 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpadd32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpadd32s;\n:fpadd32s fdrs1,fdrs2,fdrd is opf = 0x53 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpadd32s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmpeq16;\n:fpcmpeq16 fdrs1,fdrs2,rd is opf = 0x2a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmpeq16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmpeq32;\n:fpcmpeq32 fdrs1,fdrs2,rd is opf = 0x2e & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmpeq32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmpgt16;\n:fpcmpgt16 fdrs1,fdrs2,rd is opf = 0x28 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmpgt16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmpgt32;\n:fpcmpgt32 fdrs1,fdrs2,rd is opf = 0x2c & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmpgt32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmple16;\n:fpcmple16 fdrs1,fdrs2,rd is opf = 0x20 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmple16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmple32;\n:fpcmple32 fdrs1,fdrs2,rd is opf = 0x24 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmple32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmpne16;\n:fpcmpne16 fdrs1,fdrs2,rd is opf = 0x22 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmpne16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpcmpne32;\n:fpcmpne32 fdrs1,fdrs2,rd is opf = 0x26 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd\n{\n\trd = fpcmpne32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpmerge;\n:fpmerge fdrs1,fdrs2,fdrd is opf = 0x4b & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpmerge(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpsub16;\n:fpsub16 fdrs1,fdrs2,fdrd is opf = 0x54 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpsub16(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpsub16s;\n:fpsub16s fdrs1,fdrs2,fdrd is opf = 0x55 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpsub16s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpsub32;\n:fpsub32 fdrs1,fdrs2,fdrd is opf = 0x56 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpsub32(fdrs1,fdrs2);\n}\n\ndefine pcodeop fpsub32s;\n:fpsub32s fdrs1,fdrs2,fdrd is opf = 0x57 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fpsub32s(fdrs1,fdrs2);\n}\n\ndefine pcodeop fsrc1d;\n:fsrc1d fdrs1,fdrd is opf = 0x74 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd\n{\n\tfdrd = fsrc1d(fdrs1);\n}\n\ndefine pcodeop fsrc1s;\n:fsrc1s fdrs1,fdrd is opf = 0x75 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd\n{\n\tfdrd = fsrc1s(fdrs1);\n}\n\ndefine pcodeop fsrc2d;\n:fsrc2d fdrs2,fdrd is opf = 0x78 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd\n{\n\tfdrd = fsrc2d(fdrs2);\n}\n\ndefine pcodeop fsrc2s;\n:fsrc2s fdrs2,fdrd is opf = 0x79 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd\n{\n\tfdrd = fsrc2s(fdrs2);\n}\n\ndefine pcodeop fxnord;\n:fxnord fdrs1,fdrs2,fdrd is opf = 0x72 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fxnord(fdrs1,fdrs2);\n}\n\ndefine pcodeop fxnors;\n:fxnors fdrs1,fdrs2,fdrd is opf = 0x73 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fxnors(fdrs1,fdrs2);\n}\n\ndefine pcodeop fxord;\n:fxord fdrs1,fdrs2,fdrd is opf = 0x6c & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fxord(fdrs1,fdrs2);\n}\n\ndefine pcodeop fxors;\n:fxors fdrs1,fdrs2,fdrd is opf = 0x6d & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = fxors(fdrs1,fdrs2);\n}\n\ndefine pcodeop fzerod;\n:fzerod fdrd is opf = 0x60 & op3 = 0x36 & op = 0x2 & fdrd\n{\n\tfdrd = fzerod();\n}\n\ndefine pcodeop fzeros;\n:fzeros fsrd is opf = 0x61 & op3 = 0x36 & op = 0x2 & fsrd\n{\n\tfsrd = fzeros();\n}\n\ndefine pcodeop pdist;\n:pdist fdrs1,fdrs2,fdrd is opf = 0x3e & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd\n{\n\tfdrd = pdist(fdrs1,fdrs2);\n}\n\n" }, { "path": "pypcode/processors/Sparc/data/manuals/Sparc.idx", "content": "@SPARCV9.pdf[The SPARC Architecture Manual, Version 9 (SAV09R1459912)]\nADD,160\nADDcc,160\nADDC,160\nADDCcc,160\nAND,208\nANDcc,208\nANDN,208\nANDNcc,208\nBPcc,172\nBicc,169\nBA,169\nBN,169\nBNE,169\nBE,169\nBG,169\nBLE,169\nBGE,169\nBL,169\nBGU,169\nBLEU,169\nBCC,169\nBCS,169\nBPOS,169\nBNEG,169\nBVC,169\nBVS,169\nBPA,172\nBPN,172\nBPNE,172\nBPE,172\nBPG,172\nBPLE,172\nBPGE,172\nBPL,172\nBPGU,172\nBPEU,172\nBPCC,172\nBPCS,172\nBPPOS,172\nBPNEG,172\nBPVC,172\nBPVS,172\nBPr,161\nBRZ,161\nBRLEZ,161\nBRLZ,161\nBRNZ,161\nBRGZ,161\nBRGEZ,161\nCALL,175\nCASA,176\nCASXA,176\nDONE,181\nFABSs,188\nFABSd,188\nFABSq,188\nFADDs,182\nFADDd,182\nFADDq,182\nFBA,163\nFBN,163\nFBU,163\nFBG,163\nFBUG,163\nFBL,163\nFBUL,163\nFBLG,163\nFBNE,163\nFBE,163\nFBUE,163\nFBGE,163\nFBUGE,163\nFBLE,163\nFBULE,163\nFBO,163\nFBfcc,163\nFBPA,166\nFBPN,166\nFBPU,166\nFBPG,166\nFBPUG,166\nFBPL,166\nFBPUL,166\nFBPLG,166\nFBPNE,166\nFBPE,166\nFBPUE,166\nFBPGE,166\nFBPUGE,166\nFBPLE,166\nFBPULE,166\nFBPO,166\nFBPfcc,166\nFCMPs,183\nFCMPd,183\nFCMPq,183\nFCMPEs,183\nFCMPEd,183\nFCMPEq,183\nFDIVs,189\nFDIVd,189\nFDIVq,189\nFdMULq,189\nFiTOs,187\nFiTOd,187\nFiTOq,187\nFLUSH,191\nFLUSHW,193\nFMOVA,213\nFMOVN,213\nFMOVNE,213\nFMOVE,213\nFMOVG,213\nFMOVLE,213\nFMOVGE,213\nFMOVL,213\nFMOVGU,213\nFMOVLEU,213\nFMOVCC,213\nFMOVCS,213\nFMOVPOS,213\nFMOVNEG,213\nFMOVVC,213\nFMOVVS,213\nFMOVFA,213\nFMOVFN,213\nFMOVFU,213\nFMOVFG,213\nFMOVFUG,213\nFMOVFL,213\nFMOVFUL,213\nFMOVFLG,213\nFMOVFNE,213\nFMOVFE,213\nFMOVFUE,213\nFMOVFGE,213\nFMOVFUGE,213\nFMOVFLE,213\nFMOVFULE,213\nFMOVFO,213\nFMOVr,217\nFMOVRZ,217\nFMOVRLEZ,217\nFMOVRLZ,217\nFMOVRNZ,217\nFMOVRGZ,217\nFMOVRGEZ,217\nFMOVs,188\nFMOVd,188\nFMOVq,188\nFMOVscc,213\nFMOVdcc,213\nFMOVqcc,213\nFMOVsr,217\nFMOVdr,217\nFMOVqr,217\nFMULs,189\nFMULd,189\nFMULq,189\nFNEGs,188\nFNEGd,188\nFNEGq,188\nFsMULd,189\nFSQRTs,190\nFSQRTd,190\nFSQRTq,190\nFsTOi,185\nFdTOi,185\nFqTOi,185\nFsTOd,186\nFsTOq,186\nFdTOs,186\nFdTOq,186\nFqTOs,186\nFqTOd,186\nFsTOx,185\nFdTOx,185\nFqTOx,185\nFSUBs,182\nFSUBd,182\nFSUBq,182\nFxTOs,187\nFxTOd,187\nFxTOq,187\nILLTRAP,194\nIMPDEP1,195\nIMPDEP2,195\nJMPL,196\nLDD,201\nLDDA,203\nLDDF,197\nLDDFA,199\nLDDQFA,199\nLDDFAPASI,199\nLDF,197\nLDFA,199\nLDFAPASI,199\nLDFSR,197\nLDQF,197\nLDQFAPASI,199\nLDSB,201\nLDSBAPASI,203\nLDSH,201\nLDSHAPASI,203\nLDSTUB,206\nLDSTUBA,207\nLDSW,201\nLDSWA,203\nLDUB,201\nLDUBA,203\nLDUH,201\nLDUHA,203\nLDUW,201\nLDUWA,203\nLDX,201\nLDXA,203\nLDXFSR,197\nMEMBAR,210\nMOVA,219\nMOVN,219\nMOVNE,219\nMOVE,219\nMOVG,219\nMOVLE,219\nMOVGE,219\nMOVL,219\nMOVGU,219\nMOVLEU,219\nMOVCC,219\nMOVCS,219\nMOVPOS,219\nMOVNEG,219\nMOVVC,219\nMOVVS,219\nMOVFA,219\nMOVFN,219\nMOVFU,219\nMOVFG,219\nMOVFUG,219\nMOVFFL,219\nMOVFUL,219\nMOVFLG,219\nMOVFNE,219\nMOVFE,219\nMOVFUE,219\nMOVFGE,219\nMOVFUGE,219\nMOVFLE,219\nMOVFULE,219\nMOVFO,219\nMOVr,223\nMOVRZ,223\nMOVRLEZ,223\nMOVRLZ,223\nMOVRNZ,223\nMOVRGZ,223\nMOVRGEZ,223\nMULScc,228\nMULX,225\nNOP,230\nOR,208\nORcc,208\nORN,208\nORNcc,208\nPOPC,231\nPREFETCH,232\nPREFETCHA,232\nRDASI,241\nRDASRPASR,241\nRDCCR,241\nRDFPRS,241\nRDPC,241\nRDPR,238\nRDTICKPNPT,241\nRDY,241\nRDCCR,241\nRDASI,241\nRDTICK,241\nRDPC,241\nRDFPRS,241\nRDASR,241\nRESTORE,245\nRESTORED,247\nRETRY,181\nRETURN,243\nSAVE,245\nSAVED,247\nSDIV,178\nSDIVcc,178\nSDIVX,225\nSETHI,248\nSIR,251\nSLL,249\nSLLX,249\nSMUL,226\nSMULcc,226\nSRA,249\nSRAX,249\nSRL,249\nSRLX,249\nSTB,257\nSTBA,259\nSTBAR,252\nSTD,257\nSTDA,259\nSTDF,253\nSTDFA,255\nSTF,253\nSTFA,255\nSTFSR,253\nSTH,257\nSTHA,259\nSTQF,253\nSTQFA,255\nSTW,257\nSTWA,259\nSTX,257\nSTXA,259\nSTXFSR,253\nSUB,261\nSUBcc,261\nSUBC,261\nSUBCcc,261\nSWAP,262\nSWAPA,264\nTADDcc,266\nTADDccTV,266\nTA,270\nTN,270\nTNE,270\nTE,270\nTG,270\nTLE,270\nTGE,270\nTL,270\nTGU,270\nTLEU,270\nTCC,270\nTCS,270\nTPOS,270\nTNEG,270\nTVC,270\nTVS,270\nTSUBcc,268\nTSUBccTV,268\nUDIV,178\nUDIVcc,178\nUDIVX,225\nUMUL,226\nUMULcc,226\nWRASI,275\nWRASRPASR,275\nWRCCR,275\nWRFPRS,275\nWRPR,273\nWRY,275\nWRCCR,275\nWRASI,275\nWRASR,275\nWRFPRS,275\nWRY,275\nXNOR,208\nXNORcc,208\nXOR,208\nXORcc,208\n" }, { "path": "pypcode/processors/Sparc/data/patterns/SPARC_patterns.xml", "content": "\n \n \n 0x81f00000 \n 0x81c7e008 0x........ \n 0x81c7e008 0x........ 0000000. 0x000000 \n 0x81c3e008 0x........ \n 0x81c3e008 0x........ 0000000. 0x000000 \n 0x81cfe008 0x........ \n 0x81cfe008 0x........ 0000000. 0x000000 \n 0x10 101..... 0x.... 0x........ \n 0x10 101..... 0x.... 0x........ 0000000. 0x000000 \n 0x30 101..... 0x.... \n 0x30 101..... 0x.... 0000000. 0x000000 \n 01...... 0x...... 10.....1 11101... 0x.... \n 01...... 0x...... 10.....1 11101... 0x.... 0000000. 0x000000 \n 01...... 0x...... 0x9E 00010... 0x.... \n 01...... 0x...... 0x9E 00010... 0x.... 0000000. 0x000000 \n 0000000. 0x000000 0000000. 0x000000 \n \n \n 10011101 11100011 10111... ........ \n \n \n \n \n \n 0x81 0xc3 0xe0 0x08 0xae 0x03 0xc0 0x17 \n \n \n \n \n 0x81 0xc3 0xe0 0x08 0x82 0x03 0xc0 0x01 \n \n \n \n \n 0x81 0xc3 0xe0 0x08 0x90 0x02 0x00 0x0f \n \n \n \n" }, { "path": "pypcode/processors/Sparc/data/patterns/patternconstraints.xml", "content": "\n \n SPARC_patterns.xml\n \n\n" }, { "path": "pypcode/processors/SuperH/data/languages/sh-1.slaspec", "content": "\n@define SH_VERSION \"1\"\n\n@include \"superh.sinc\"\n" }, { "path": "pypcode/processors/SuperH/data/languages/sh-2.slaspec", "content": "@define SH_VERSION \"2\"\n\n@include \"superh.sinc\"\n" }, { "path": "pypcode/processors/SuperH/data/languages/sh-2a.slaspec", "content": "@define SH_VERSION \"2A\"\n@define FPU \"1\"\n\n@include \"superh.sinc\"\n" }, { "path": "pypcode/processors/SuperH/data/languages/superh.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH/data/languages/superh.ldefs", "content": "\n\n\n \n SuperH SH-2A processor 32-bit big-endian\n \n \n \n SuperH SH-2 processor 32-bit big-endian\n \n \n \n SuperH SH-1 processor 32-bit big-endian\n \n \n\n" }, { "path": "pypcode/processors/SuperH/data/languages/superh.pspec", "content": "\n\n\n \n\n" }, { "path": "pypcode/processors/SuperH/data/languages/superh.sinc", "content": "# All assembly defintions taken from: http://www.shared-ptr.com/sh_insns.html\n\ndefine endian=big;\n\ndefine alignment=1;\n\ndefine space ram type=ram_space size=4 wordsize=1 default;\ndefine space register type=register_space size=4;\n\ndefine register offset=0 size=4\n[r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15];\n\ndefine register offset=0x100 size=4 [sr gbr vbr mach macl pr pc];\n\n\n@if SH_VERSION == \"2A\"\ndefine register offset=0x180 size=4 [tbr];\n@endif\n\n# SR Flags\n@define T_FLAG \"sr[0,1]\"\n@define S_FLAG \"sr[1,1]\"\n@define I0_FLAG \"sr[4,1]\"\n@define I1_FLAG \"sr[5,1]\"\n@define I2_FLAG \"sr[6,1]\"\n@define I3_FLAG \"sr[7,1]\"\n@define Q_FLAG \"sr[8,1]\"\n@define M_FLAG \"sr[9,1]\"\n@define CS_FLAG \"sr[13,1]\"\n@define BO_FLAG \"sr[14,1]\"\n\n@if defined(FPU)\n\n# Floating-Point Registers\ndefine register offset=0x200 size=4 [ fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 ];\ndefine register offset=0x200 size=8 [ dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 ];\n\n# Floating-Point System Registers\ndefine register offset=0x300 size=4 [fpscr fpul];\n\n# FPSCR Flags (initial value = H'0004 0001)\n@define FP_RM \"fpscr[0,2]\"\n@define FP_FLAG \"fpscr[2,5]\"\n@define FP_ENABLE \"fpscr[7,5]\"\n@define FP_CAUSE \"fpscr[12,6]\"\n@define FP_DN \"fpscr[18,1]\"\n@define FP_PR \"fpscr[19,1]\"\n@define FP_SZ \"fpscr[20,1]\"\n@define FP_QIS \"fpscr[22,1]\"\n\n@endif\n\n@if SH_VERSION == \"2A\"\n# The register banks space is defined below, there are 512 banks, each is 80 bytes long\ndefine register offset=0x10000 size=40960 [ resbank_base ];\n@endif\n\ndefine token instr16(16)\n disp_00_03 = (0, 3) \n sdisp_00_03 = (0, 3) signed\n disp_00_07 = (0, 7) \n sdisp_00_07 = (0, 7) signed\n disp_00_11 = (0, 11)\n sdisp_00_11 = (0, 11) signed\n imm3_00_02 = (0, 2)\n imm_00_07 = (0, 7)\n simm_00_07 = (0, 7) signed\n opcode_00_03 = (0, 3)\n opcode_00_07 = (0, 7)\n opcode_00_15 = (0, 15)\n opcode_03_03 = (3, 3)\n opcode_04_07 = (4, 7)\n opcode_08_11 = (8, 11)\n opcode_08_15 = (8, 15)\n opcode_12_15 = (12, 15)\n rm_04_07 = (4, 7)\n rm_08_11 = (8, 11)\n rn_04_07 = (4, 7)\n rn_08_11 = (8, 11)\n rm_imm_08_11 = (8, 11)\n rn_imm_08_11 = (8, 11)\n;\n\n@if SH_VERSION == \"2A\"\ndefine token instr32(32)\n l_disp_00_11 = (0, 11)\n l_opcode_12_15 = (12, 15)\n l_opcode_16_19 = (16, 19)\n l_opcode_23_23 = (23, 23)\n l_opcode_24_31 = (24, 31)\n l_rm_20_23 = (20, 23)\n l_rn_24_27 = (24, 27)\n l_opcode_28_31 = (28, 31)\n l_imm20_00_15 = (0, 15)\n l_simm20_20_23 = (20, 23) signed\n l_imm3_20_22 = (20, 22)\n;\n\nattach variables [ l_rn_24_27 l_rm_20_23 ] [\n r0 r1 r2 r3 r4 r5 r6 r7\n r8 r9 r10 r11 r12 r13 r14 r15\n];\n\n@endif\n\nattach variables [ rm_04_07 rm_08_11 rn_04_07 rn_08_11 ] [\n r0 r1 r2 r3 r4 r5 r6 r7\n r8 r9 r10 r11 r12 r13 r14 r15\n];\n\nattach names [ rm_imm_08_11 rn_imm_08_11 ] [\n r0 r1 r2 r3 r4 r5 r6 r7\n r8 r9 r10 r11 r12 r13 r14 pr\n];\n\n@if defined(FPU)\n\ndefine token finstr16(16)\n fop_00_07 = (0, 7)\n fop_00_03 = (0, 3)\n fop_04_07 = (4, 7)\n fop_12_15 = (12, 15)\n fop_08_08 = (8, 8)\n fop_04_04 = (4, 4)\n fop_00_15 = (0, 15)\n\n ffrn_08_11 = (8, 11)\n ffrm_08_11 = (8, 11)\n ffrn_04_07 = (4, 7)\n ffrm_04_07 = (4, 7)\n f_rm_04_07 = (4, 7)\n f_rn_08_11 = (8, 11)\n\n fdrn_09_11 = (9, 11)\n fdrm_09_11 = (9, 11)\n fdrn_05_07 = (5, 7)\n fdrm_05_07 = (5, 7)\n;\n\n\ndefine token finstr32(32)\n lfdisp_00_11 = (0, 11)\n lfop_28_31 = (28, 31)\n lfop_12_19 = (12, 19)\n lffrm_24_27 = (24, 27)\n lffrn_24_27 = (24, 27)\n lffrm_20_23 = (20, 23)\n lf_rm_20_23 = (20, 23)\n lf_rn_24_27 = (24, 27)\n lffrn_20_23 = (20, 23)\n;\n\nattach variables [ ffrn_08_11 ffrm_08_11 ffrn_04_07 ffrm_04_07 lffrm_24_27 lffrn_24_27 lffrm_20_23 lffrn_20_23 ]\n[fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15];\n\nattach variables [ f_rm_04_07 f_rn_08_11 lf_rm_20_23 lf_rn_24_27 ]\n[r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15];\n\nattach variables [ fdrn_09_11 fdrm_09_11 fdrn_05_07 fdrm_05_07 ]\n[dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14];\n\n@endif\n\n\n# helpers for branch\ntarget00_07: target is sdisp_00_07 [ target = (sdisp_00_07 << 1) + inst_start + 4; ] {\n export *:4 target;\n}\n\ntarget00_11: target is sdisp_00_11 [ target = (sdisp_00_11 << 1) + inst_start + 4; ] {\n export *:4 target;\n}\n\n\n#\n# Data Transfer Instructions\n#\n\n:mov rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0011 \n{\n rn_08_11 = rm_04_07;\n}\n\nimm8: \"#\"^simm_00_07 is simm_00_07 { export *[const]:4 simm_00_07; }\n \n:mov imm8,rn_08_11 is opcode_12_15=0b1110 & rn_08_11 & imm8 \n{\n rn_08_11 = imm8;\n}\n\ndisppc4: @(disp,pc) is disp_00_07 & pc\n [ disp = (disp_00_07 << 2) + ((inst_start + 4) & 0xfffffffc); ]\n { local tmp:4 = disp; export tmp; }\n\ndisppc2: @(disp,pc) is disp_00_07 & pc\n [ disp = (disp_00_07 << 1) + (inst_start + 4); ]\n { local tmp:4 = disp; export tmp; }\n\n:mova disppc4,r0 is r0 & opcode_08_15=0b11000111 & disppc4\n{\n r0 = disppc4;\n}\n\n:mov.w disppc2,rn_08_11 is opcode_12_15=0b1001 & rn_08_11 & disppc2\n{\n rn_08_11 = sext(*:2 disppc2);\n}\n\n:mov.l disppc4,rn_08_11 is opcode_12_15=0b1101 & rn_08_11 & disppc4\n{\n rn_08_11 = *:4 disppc4;\n}\n\n:mov.b @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 \n{\n rn_08_11 = sext(*:1 rm_04_07);\n}\n\n:mov.w @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001 \n{\n rn_08_11 = sext(*:2 rm_04_07);\n}\n\n:mov.l @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 \n{\n rn_08_11 = *:4 rm_04_07;\n}\n\n:mov.b rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 \n{\n *:1 rn_08_11 = rm_04_07:1;\n}\n\n:mov.w rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001 \n{\n *:2 rn_08_11 = rm_04_07:2;\n}\n\n:mov.l rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 \n{\n *:4 rn_08_11 = rm_04_07;\n}\n\n# the following two instructions share the same opcodes but differ if rm == rn\n:mov.b @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 & opcode_04_07=opcode_08_11\n{\n rn_08_11 = sext(*:1 rm_04_07);\n}\n\n:mov.b @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100\n{\n rn_08_11 = sext(*:1 rm_04_07);\n rm_04_07 = rm_04_07 + 1;\n}\n\n# the following two instructions share the same opcodes but differ if rm == rn\n:mov.w @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 & opcode_04_07=opcode_08_11\n{\n rn_08_11 = sext(*:2 rm_04_07);\n}\n\n:mov.w @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101\n{\n rn_08_11 = sext(*:2 rm_04_07);\n rm_04_07 = rm_04_07 + 2;\n}\n\n# the following two instructions share the same opcodes but differ if rm == rn\n:mov.l @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 & opcode_04_07=opcode_08_11\n{\n rn_08_11 = *:4 rm_04_07;\n}\n\n:mov.l @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110\n{\n rn_08_11 = *:4 rm_04_07;\n rm_04_07 = rm_04_07 + 4;\n}\n\n:mov.b rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 \n{\n rn_08_11 = rn_08_11 -1;\n *:1 rn_08_11 = rm_04_07:1;\n}\n\n:mov.w rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 \n{\n rn_08_11 = rn_08_11 -2;\n *:2 rn_08_11 = rm_04_07:2;\n}\n\n:mov.l rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 \n{\n rn_08_11 = rn_08_11 -4;\n *:4 rn_08_11 = rm_04_07;\n}\n\n:mov.b @(disp_00_03,rm_04_07),r0 is r0 & opcode_08_15=0b10000100 & rm_04_07 & disp_00_03 \n{\n r0 = sext(*:1 (disp_00_03 + rm_04_07));\n}\n\n:mov.w @(disp,rm_04_07),r0 is r0 & opcode_08_15=0b10000101 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ]\n{\n r0 = sext(*:2 (disp + rm_04_07));\n}\n\n:mov.l @(disp,rm_04_07),rn_08_11 is opcode_12_15=0b0101 & rn_08_11 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 2; ]\n{\n rn_08_11 = *:4 (disp + rm_04_07);\n}\n\n:mov.b r0,@(disp_00_03,rn_04_07) is r0 & opcode_08_15=0b10000000 & rn_04_07 & disp_00_03 \n{\n *:1 (rn_04_07 + disp_00_03) = r0:1;\n}\n\n:mov.w r0,@(disp,rn_04_07) is r0 & opcode_08_15=0b10000001 & rn_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ]\n{\n *:2 (rn_04_07 + disp) = r0:2;\n}\n\n:mov.l rm_04_07,@(disp,rn_08_11) is opcode_12_15=0b0001 & rn_08_11 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 2; ]\n{\n *:4 (rn_08_11 + disp) = rm_04_07;\n}\n\n:mov.b @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 \n{\n rn_08_11 = sext(*:1 (rm_04_07 + r0));\n}\n\n:mov.w @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 \n{\n rn_08_11 = sext(*:2 (rm_04_07 + r0));\n}\n\n:mov.l @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 \n{\n rn_08_11 = *:4 (rm_04_07 + r0);\n}\n\n:mov.b rm_04_07,@(r0,rn_08_11) is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 \n{\n *:1 (rn_08_11 + r0) = rm_04_07:1;\n}\n\n:mov.w rm_04_07,@(r0,rn_08_11) is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 \n{\n *:2 (rn_08_11 + r0) = rm_04_07:2;\n}\n\n:mov.l rm_04_07,@(r0,rn_08_11) is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 \n{\n *:4 (rn_08_11 + r0) = rm_04_07:4;\n}\n\n:mov.b @(disp_00_07,gbr),r0 is gbr & r0 & opcode_08_15=0b11000100 & disp_00_07 \n{\n r0 = sext(*:1 (gbr + disp_00_07));\n}\n\n:mov.w @(disp,gbr),r0 is gbr & r0 & opcode_08_15=0b11000101 & disp_00_07 [disp = (disp_00_07 << 1); ]\n{\n r0 = sext(*:2 (gbr + disp));\n}\n\n:mov.l @(disp,gbr),r0 is gbr & r0 & opcode_08_15=0b11000110 & disp_00_07 [disp = (disp_00_07 << 2); ]\n{\n r0 = *:4 (gbr + disp);\n}\n\n:mov.b r0,@(disp_00_07,gbr) is r0 & gbr & opcode_08_15=0b11000000 & disp_00_07 \n{\n *:1 (gbr + disp_00_07) = r0:1;\n}\n\n:mov.w r0,@(disp,gbr) is r0 & gbr & opcode_08_15=0b11000001 & disp_00_07 [disp = (disp_00_07 << 1); ]\n{\n *:2 (gbr + disp) = r0:2;\n}\n\n:mov.l r0,@(disp,gbr) is r0 & gbr & opcode_08_15=0b11000010 & disp_00_07 [disp = (disp_00_07 << 2); ]\n{\n *:4 (gbr + disp) = r0:4;\n}\n\n:movt rn_08_11 is opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00101001 \n{\n rn_08_11 = zext($(T_FLAG));\n}\n\n@if SH_VERSION == \"2A\"\n\n# MOV.B R0, @Rn+ 0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn\n:mov.b r0, @rn_08_11+\n is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10001011\n{\n *:1 (rn_08_11) = r0:1;\n rn_08_11 = rn_08_11 + 1;\n}\n\n# MOV.W R0, @Rn+ 0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn\n:mov.w r0, @rn_08_11+\n is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10011011\n{\n *:2 (rn_08_11) = r0:2;\n rn_08_11 = rn_08_11 + 2;\n}\n\n# MOV.L R0, @Rn+ 0100nnnn10101011 R0 → (Rn), Rn + 4 → Rn\n:mov.l r0, @rn_08_11+\n is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10101011\n{\n *:4 (rn_08_11) = r0;\n rn_08_11 = rn_08_11 + 4;\n}\n\n# MOV.B @-Rm, R0 0100mmmm11001011 Rm - 1 → Rm, (Rm) → sign extension → R0\n:mov.b @-rm_08_11, r0\n is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11001011\n{\n rm_08_11 = rm_08_11 - 1;\n r0 = sext(*:1 (rm_08_11));\n}\n\n# MOV.W @-Rm, R0 0100mmmm11011011 Rm - 2 → Rm, (Rm) → sign extension → R0\n:mov.w @-rm_08_11, r0\n is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11011011\n{\n rm_08_11 = rm_08_11 - 2;\n r0 = sext(*:2 (rm_08_11));\n}\n\n# MOV.L @-Rm, R0 0100mmmm11101011 Rm - 4 → Rm, (Rm) → R0\n:mov.l @-rm_08_11, r0\n is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11101011\n{\n rm_08_11 = rm_08_11 - 4;\n r0 = *:4 (rm_08_11);\n}\n\n# MOV.B Rm, @(disp12, Rn) 0011nnnnmmmm0001 0000dddddddddddd Rm -> (disp+Rn)\n:mov.b l_rm_20_23, @(l_disp_00_11, l_rn_24_27) is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0000 & l_disp_00_11\n{\n *:1 (l_rn_24_27 + l_disp_00_11) = l_rm_20_23:1;\n}\n\n# MOV.W Rm, @(disp12, Rn) 0011nnnnmmmm0001 0001dddddddddddd Rm → (disp×2+Rn)\n:mov.w l_rm_20_23, @(disp, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0001 & l_disp_00_11\n [ disp = 2*l_disp_00_11; ]\n{\n *:2 (l_rn_24_27 + disp) = l_rm_20_23:2;\n}\n\n# MOV.L Rm, @(disp12, Rn) 0011nnnnmmmm0001 0010dddddddddddd Rm → (disp×4+Rn)\n:mov.l l_rm_20_23, @(disp, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0010 & l_disp_00_11\n [ disp = 4*l_disp_00_11; ]\n{\n *:4 (l_rn_24_27 + disp) = l_rm_20_23;\n}\n\n# MOV.B @(disp12, Rm), Rn 0011nnnnmmmm0001 0100dddddddddddd (disp+Rm) → sign extension → Rn\n:mov.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27 is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0100 & l_disp_00_11\n{\n l_rn_24_27 = sext(*:1 (l_rm_20_23 + l_disp_00_11));\n}\n\n# MOV.W @(disp12, Rm), Rn 0011nnnnmmmm0001 0101dddddddddddd (disp×2+Rm) → sign extension → Rn\n:mov.w @(disp, l_rm_20_23), l_rn_24_27\n is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0101 & l_disp_00_11\n [ disp = 2*l_disp_00_11; ]\n{\n l_rn_24_27 = sext(*:2 (l_rm_20_23 + disp));\n}\n\n# MOV.L @(disp12, Rm), Rn 0011nnnnmmmm0001 0110dddddddddddd (disp×4+Rm) → Rn\n:mov.l @(disp, l_rm_20_23), l_rn_24_27\n is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0110 & l_disp_00_11\n [ disp = (4*l_disp_00_11); ]\n{\n l_rn_24_27 = *:4 (l_rm_20_23 + disp);\n}\n\n# MOVU.B @(disp12,Rm), Rn 0011nnnnmmmm0001 1000dddddddddddd (disp+Rm) → zero extension → Rn\n:movu.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1000 & l_disp_00_11\n{\n l_rn_24_27 = zext(*:1 (l_disp_00_11 + l_rm_20_23));\n}\n\n# MOVU.W @(disp12,Rm), Rn 0011nnnnmmmm0001 1001dddddddddddd (disp×2+Rm) → zero extension → Rn\n:movu.w @(disp, l_rm_20_23), l_rn_24_27\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1001 & l_disp_00_11\n [ disp = l_disp_00_11 * 2; ]\n{\n l_rn_24_27 = zext(*:2 (disp + l_rm_20_23));\n}\n\nsimm20: \"#\"value is l_simm20_20_23 & l_imm20_00_15\n [ value = ((l_simm20_20_23 << 16) | l_imm20_00_15); ]\n { export *[const]:4 value; }\n\nsimm20s: \"#\"value is l_simm20_20_23 & l_imm20_00_15\n [ value = ((l_simm20_20_23 << 16) | l_imm20_00_15) << 8; ]\n { export *[const]:4 value; }\n\n\n# MOVI20 #imm20, Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii imm → sign extension → Rn\n:movi20 simm20, l_rn_24_27\n is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0000 & simm20\n{\n l_rn_24_27 = simm20;\n}\n\n# MOVI20S #imm20, Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii imm<<8 → sign extension → Rn\n:movi20s simm20s, l_rn_24_27\n is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0001 & simm20s\n{\n l_rn_24_27 = simm20s;\n}\n\n#\n# movm* instuctions are only in SH2A. They don't collide, but could be ifdef'ed for 2A only\n#\n\nmacro loadRegister(reg, ea) {\n\treg = *:4(ea);\n\tea = ea+4;\n}\n\nmacro storeRegister(reg, ea) {\n\tea = ea-4;\n\t*:4(ea) = reg;\n}\n\nMovMLReg1_0:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { storeRegister(r0,r15); }\nMovMLReg1_0store:\t is rm_imm_08_11 { storeRegister(r0,r15); }\n\nMovMLReg1_1:\tMovMLReg1_0 \tis MovMLReg1_0 { r0 = r0; }\nMovMLReg1_1:\trm_imm_08_11 is MovMLReg1_0store & rm_imm_08_11 & rm_08_11=1 { storeRegister(r1,r15); build MovMLReg1_0store; }\nMovMLReg1_1store:\t is MovMLReg1_0store & rm_imm_08_11 { storeRegister(r1,r15); build MovMLReg1_0store; }\n\nMovMLReg1_2:\tMovMLReg1_1 \tis MovMLReg1_1 { r0 = r0; }\nMovMLReg1_2:\trm_imm_08_11 is MovMLReg1_1store & rm_imm_08_11 & rm_08_11=2 { storeRegister(r2,r15); build MovMLReg1_1store; }\nMovMLReg1_2store:\t is MovMLReg1_1store & rm_imm_08_11 { storeRegister(r2,r15); build MovMLReg1_1store; }\n\nMovMLReg1_3:\tMovMLReg1_2 \tis MovMLReg1_2 { r0 = r0; }\nMovMLReg1_3:\trm_imm_08_11 is MovMLReg1_2store & rm_imm_08_11 & rm_08_11=3 { storeRegister(r3,r15); build MovMLReg1_2store; }\nMovMLReg1_3store:\t is MovMLReg1_2store & rm_imm_08_11 { storeRegister(r3,r15); build MovMLReg1_2store; }\n\nMovMLReg1_4:\tMovMLReg1_3 \tis MovMLReg1_3 { r0 = r0; }\nMovMLReg1_4:\trm_imm_08_11 is MovMLReg1_3store & rm_imm_08_11 & rm_08_11=4 { storeRegister(r4,r15); build MovMLReg1_3store; }\nMovMLReg1_4store:\t is MovMLReg1_3store & rm_imm_08_11 { storeRegister(r4,r15); build MovMLReg1_3store; }\n\nMovMLReg1_5:\tMovMLReg1_4 \tis MovMLReg1_4 { r0 = r0; }\nMovMLReg1_5:\trm_imm_08_11 is MovMLReg1_4store & rm_imm_08_11 & rm_08_11=5 { storeRegister(r5,r15); build MovMLReg1_4store; }\nMovMLReg1_5store:\t is MovMLReg1_4store & rm_imm_08_11 { storeRegister(r5,r15); build MovMLReg1_4store; }\n\nMovMLReg1_6:\tMovMLReg1_5 \tis MovMLReg1_5 { r0 = r0; }\nMovMLReg1_6:\trm_imm_08_11 is MovMLReg1_5store & rm_imm_08_11 & rm_08_11=6 { storeRegister(r6,r15); build MovMLReg1_5store; }\nMovMLReg1_6store:\t is MovMLReg1_5store & rm_imm_08_11 { storeRegister(r6,r15); build MovMLReg1_5store; }\n\nMovMLReg1_7:\tMovMLReg1_6 \tis MovMLReg1_6 { r0 = r0; }\nMovMLReg1_7:\trm_imm_08_11 is MovMLReg1_6store & rm_imm_08_11 & rm_08_11=7 { storeRegister(r7,r15); build MovMLReg1_6store; }\nMovMLReg1_7store:\t is MovMLReg1_6store & rm_imm_08_11 { storeRegister(r7,r15); build MovMLReg1_6store; }\n\nMovMLReg1_8:\tMovMLReg1_7 \tis MovMLReg1_7 { r0 = r0; }\nMovMLReg1_8:\trm_imm_08_11 is MovMLReg1_7store & rm_imm_08_11 & rm_08_11=8 { storeRegister(r8,r15); build MovMLReg1_7store; }\nMovMLReg1_8store:\t is MovMLReg1_7store & rm_imm_08_11 { storeRegister(r8,r15); build MovMLReg1_7store; }\n\nMovMLReg1_9:\tMovMLReg1_8 \tis MovMLReg1_8 { r0 = r0; }\nMovMLReg1_9:\trm_imm_08_11 is MovMLReg1_8store & rm_imm_08_11 & rm_08_11=9 { storeRegister(r9,r15); build MovMLReg1_8store; }\nMovMLReg1_9store:\t is MovMLReg1_8store & rm_imm_08_11 { storeRegister(r9,r15); build MovMLReg1_8store; }\n\nMovMLReg1_10:\tMovMLReg1_9 \tis MovMLReg1_9 { r0 = r0; }\nMovMLReg1_10:\trm_imm_08_11 is MovMLReg1_9store & rm_imm_08_11 & rm_08_11=10 { storeRegister(r10,r15); build MovMLReg1_9store; }\nMovMLReg1_10store:\t is MovMLReg1_9store & rm_imm_08_11 { storeRegister(r10,r15); build MovMLReg1_9store; }\n\nMovMLReg1_11:\tMovMLReg1_10 \tis MovMLReg1_10 { r0 = r0; }\nMovMLReg1_11:\trm_imm_08_11 is MovMLReg1_10store & rm_imm_08_11 & rm_08_11=11 { storeRegister(r11,r15); build MovMLReg1_10store; }\nMovMLReg1_11store:\t is MovMLReg1_10store & rm_imm_08_11 { storeRegister(r11,r15); build MovMLReg1_10store; }\n\nMovMLReg1_12:\tMovMLReg1_11 \tis MovMLReg1_11 { r0 = r0; }\nMovMLReg1_12:\trm_imm_08_11 is MovMLReg1_11store & rm_imm_08_11 & rm_08_11=12 { storeRegister(r12,r15); build MovMLReg1_11store; }\nMovMLReg1_12store:\t is MovMLReg1_11store & rm_imm_08_11 { storeRegister(r12,r15); build MovMLReg1_11store; }\n\nMovMLReg1_13:\tMovMLReg1_12\tis MovMLReg1_12 { r0 = r0; }\nMovMLReg1_13:\trm_imm_08_11 is MovMLReg1_12store & rm_imm_08_11 & rm_08_11=13 { storeRegister(r13,r15); build MovMLReg1_12store; }\nMovMLReg1_13store:\t is MovMLReg1_12store & rm_imm_08_11 { storeRegister(r13,r15); build MovMLReg1_12store; }\n\nMovMLReg1_14:\tMovMLReg1_13\tis MovMLReg1_13 { r0 = r0; }\nMovMLReg1_14: rm_imm_08_11\t is MovMLReg1_13store & rm_imm_08_11 & rm_08_11=14 { storeRegister(r14,r15); build MovMLReg1_13store; }\nMovMLReg1_14store: \tis MovMLReg1_13store & rm_imm_08_11 { storeRegister(r14,r15); build MovMLReg1_13store; }\n\nMovMLReg1_15:\tMovMLReg1_14\tis MovMLReg1_14 { r0 = r0; }\nMovMLReg1_15:\trm_imm_08_11 is MovMLReg1_14store & rm_imm_08_11 & rm_08_11=15 { storeRegister(pr,r15); build MovMLReg1_14store; }\n\nMovMLReg1: MovMLReg1_15 is MovMLReg1_15 {\n\tbuild MovMLReg1_15;\n}\n\n# MOVML.L Rm, @-R15 0100mmmm11110001\n:movml.l MovMLReg1, @-r15\n is r15 & opcode_12_15=0b0100 & rm_imm_08_11 & opcode_00_07=0b11110001 & MovMLReg1\n{\n build MovMLReg1;\n}\n\n\nMovMLReg2_0:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { loadRegister(r0,r15); }\n\nMovMLReg2_0load: is rm_imm_08_11 { loadRegister(r0,r15); }\n\nMovMLReg2_1:\tMovMLReg2_0 is MovMLReg2_0 { r0 = r0; }\nMovMLReg2_1:\trm_imm_08_11 is MovMLReg2_0load & rm_imm_08_11 & rm_08_11=1 { build MovMLReg2_0load; loadRegister(r1,r15); }\nMovMLReg2_1load: is MovMLReg2_0load & rm_imm_08_11 { build MovMLReg2_0load; loadRegister(r1,r15); }\n\nMovMLReg2_2:\tMovMLReg2_1 is MovMLReg2_1 { r0 = r0; }\nMovMLReg2_2:\trm_imm_08_11 is MovMLReg2_1load & rm_imm_08_11 & rm_08_11=2 { build MovMLReg2_1load; loadRegister(r2,r15); }\nMovMLReg2_2load: is MovMLReg2_1load & rm_imm_08_11 { build MovMLReg2_1load; loadRegister(r2,r15); }\n\nMovMLReg2_3:\tMovMLReg2_2 is MovMLReg2_2 { r0 = r0; }\nMovMLReg2_3:\trm_imm_08_11 is MovMLReg2_2load & rm_imm_08_11 & rm_08_11=3 { build MovMLReg2_2load; loadRegister(r3,r15); }\nMovMLReg2_3load: is MovMLReg2_2load & rm_imm_08_11 { build MovMLReg2_2load; loadRegister(r3,r15); }\n\nMovMLReg2_4:\tMovMLReg2_3 is MovMLReg2_3 { r0 = r0; }\nMovMLReg2_4:\trm_imm_08_11 is MovMLReg2_3load & rm_imm_08_11 & rm_08_11=4 { build MovMLReg2_3load; loadRegister(r4,r15); }\n\nMovMLReg2_4load: is MovMLReg2_3load & rm_imm_08_11 { build MovMLReg2_3load; loadRegister(r4,r15); }\n\nMovMLReg2_5:\tMovMLReg2_4 is MovMLReg2_4 { r0 = r0; }\nMovMLReg2_5:\trm_imm_08_11 is MovMLReg2_4load & rm_imm_08_11 & rm_08_11=5 { build MovMLReg2_4load; loadRegister(r5,r15); }\n\nMovMLReg2_5load: is MovMLReg2_4load & rm_imm_08_11 { build MovMLReg2_4load; loadRegister(r5,r15); }\n\nMovMLReg2_6:\tMovMLReg2_5 is MovMLReg2_5 { r0 = r0; }\nMovMLReg2_6:\trm_imm_08_11 is MovMLReg2_5load & rm_imm_08_11 & rm_08_11=6 { build MovMLReg2_5load; loadRegister(r6,r15); }\n\nMovMLReg2_6load: is MovMLReg2_5load & rm_imm_08_11 { build MovMLReg2_5load; loadRegister(r6,r15); }\n\nMovMLReg2_7:\tMovMLReg2_6 is MovMLReg2_6 { r0 = r0; }\nMovMLReg2_7:\trm_imm_08_11 is MovMLReg2_6load & rm_imm_08_11 & rm_08_11=7 { build MovMLReg2_6load; loadRegister(r7,r15); }\n\nMovMLReg2_7load: is MovMLReg2_6load & rm_imm_08_11 { build MovMLReg2_6load; loadRegister(r7,r15); }\n\nMovMLReg2_8:\tMovMLReg2_7 is MovMLReg2_7 { r0 = r0; }\nMovMLReg2_8:\trm_imm_08_11 is MovMLReg2_7load & rm_imm_08_11 & rm_08_11=8 { build MovMLReg2_7load; loadRegister(r8,r15); }\n\nMovMLReg2_8load: is MovMLReg2_7load & rm_imm_08_11 { build MovMLReg2_7load; loadRegister(r8,r15); }\n\nMovMLReg2_9:\tMovMLReg2_8 is MovMLReg2_8 { r0 = r0; }\nMovMLReg2_9:\trm_imm_08_11 is MovMLReg2_8load & rm_imm_08_11 & rm_08_11=9 { build MovMLReg2_8load; loadRegister(r9,r15); }\n\nMovMLReg2_9load: is MovMLReg2_8load & rm_imm_08_11 { build MovMLReg2_8load; loadRegister(r9,r15); }\n\nMovMLReg2_10:\tMovMLReg2_9 is MovMLReg2_9 { r0 = r0; }\nMovMLReg2_10:\trm_imm_08_11 is MovMLReg2_9load & rm_imm_08_11 & rm_08_11=10 { build MovMLReg2_9load; loadRegister(r10,r15); }\n\nMovMLReg2_10load: is MovMLReg2_9load & rm_imm_08_11 { build MovMLReg2_9load; loadRegister(r10,r15); }\n\nMovMLReg2_11:\tMovMLReg2_10 is MovMLReg2_10 { r0 = r0; }\nMovMLReg2_11:\trm_imm_08_11 is MovMLReg2_10load & rm_imm_08_11 & rm_08_11=11 { build MovMLReg2_10load; loadRegister(r11,r15); }\nMovMLReg2_11load: is MovMLReg2_10load & rm_imm_08_11 { build MovMLReg2_10load; loadRegister(r11,r15); }\n\nMovMLReg2_12:\tMovMLReg2_11 is MovMLReg2_11 { r0 = r0; }\nMovMLReg2_12:\trm_imm_08_11 is MovMLReg2_11load & rm_imm_08_11 & rm_08_11=12 { build MovMLReg2_11load; loadRegister(r12,r15); }\n\nMovMLReg2_12load: is MovMLReg2_11load & rm_imm_08_11 { build MovMLReg2_11load; loadRegister(r12,r15); }\n\nMovMLReg2_13:\tMovMLReg2_12 is MovMLReg2_12 { r0 = r0; }\nMovMLReg2_13:\trm_imm_08_11 is MovMLReg2_12load & rm_imm_08_11 & rm_08_11=13 { build MovMLReg2_12load; loadRegister(r13,r15); }\n\nMovMLReg2_13load: is MovMLReg2_12load & rm_imm_08_11 { build MovMLReg2_12load; loadRegister(r13,r15); }\n\nMovMLReg2_14:\tMovMLReg2_13 is MovMLReg2_13 { r0 = r0; }\nMovMLReg2_14: rm_imm_08_11 is MovMLReg2_13load & rm_imm_08_11 & rm_08_11=14 { build MovMLReg2_13load; loadRegister(r14,r15); }\n\nMovMLReg2_14load: is MovMLReg2_13load & rm_imm_08_11 { build MovMLReg2_13load; loadRegister(r14,r15); }\n\nMovMLReg2_15:\tMovMLReg2_14 is MovMLReg2_14 { r0 = r0; }\nMovMLReg2_15:\trm_imm_08_11 is MovMLReg2_14load & rm_imm_08_11 & rm_08_11=15 { build MovMLReg2_14load; loadRegister(pr,r15); }\n\nMovMLReg2: MovMLReg2_15 is MovMLReg2_15 {\n\tbuild MovMLReg2_15;\n}\n\n# MOVML.L @R15+, Rn 0100nnnn11110101 \n:movml.l @r15+, MovMLReg2\n is r15 & opcode_12_15=0b0100 & rn_imm_08_11 & opcode_00_07=0b11110101 & MovMLReg2 {\n\tbuild MovMLReg2;\n}\n\n\nMovMUReg1_0:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { storeRegister(r0,r15); }\n\nMovMUReg1_1:\tMovMUReg1_0 \tis MovMUReg1_0 { storeRegister(r1,r15); build MovMUReg1_0; }\nMovMUReg1_1:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=1 { storeRegister(r1,r15); }\n\nMovMUReg1_2:\tMovMUReg1_1 \tis MovMUReg1_1 { storeRegister(r2,r15); build MovMUReg1_1; }\nMovMUReg1_2:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=2 { storeRegister(r2,r15); }\n\nMovMUReg1_3:\tMovMUReg1_2 \tis MovMUReg1_2 { storeRegister(r3,r15); build MovMUReg1_2; }\nMovMUReg1_3:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=3 { storeRegister(r3,r15); }\n\nMovMUReg1_4:\tMovMUReg1_3 \tis MovMUReg1_3 { storeRegister(r4,r15); build MovMUReg1_3; }\nMovMUReg1_4:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=4 { storeRegister(r4,r15); }\n\nMovMUReg1_5:\tMovMUReg1_4 \tis MovMUReg1_4 { storeRegister(r5,r15); build MovMUReg1_4; }\nMovMUReg1_5:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=5 { storeRegister(r5,r15); }\n\nMovMUReg1_6:\tMovMUReg1_5 \tis MovMUReg1_5 { storeRegister(r6,r15); build MovMUReg1_5; }\nMovMUReg1_6:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=6 { storeRegister(r6,r15); }\n\nMovMUReg1_7:\tMovMUReg1_6 \tis MovMUReg1_6 { storeRegister(r7,r15); build MovMUReg1_6; }\nMovMUReg1_7:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=7 { storeRegister(r7,r15); }\n\nMovMUReg1_8:\tMovMUReg1_7 \tis MovMUReg1_7 { storeRegister(r8,r15); build MovMUReg1_7; }\nMovMUReg1_8:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=8 { storeRegister(r8,r15); }\n\nMovMUReg1_9:\tMovMUReg1_8 \tis MovMUReg1_8 { storeRegister(r9,r15); build MovMUReg1_8; }\nMovMUReg1_9:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=9 { storeRegister(r9,r15); }\n\nMovMUReg1_10:\tMovMUReg1_9 \tis MovMUReg1_9 { storeRegister(r10,r15); build MovMUReg1_9; }\nMovMUReg1_10:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=10 { storeRegister(r10,r15); }\n\nMovMUReg1_11:\tMovMUReg1_10 \tis MovMUReg1_10 { storeRegister(r11,r15); build MovMUReg1_10; }\nMovMUReg1_11:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=11 { storeRegister(r11,r15); }\n\nMovMUReg1_12:\tMovMUReg1_11 \tis MovMUReg1_11 { storeRegister(r12,r15); build MovMUReg1_11; }\nMovMUReg1_12:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=12 { storeRegister(r12,r15); }\n\nMovMUReg1_13:\tMovMUReg1_12\tis MovMUReg1_12 { storeRegister(r13,r15); build MovMUReg1_12; }\nMovMUReg1_13:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=13 { storeRegister(r13,r15); }\n\nMovMUReg1_14:\tMovMUReg1_13\tis MovMUReg1_13 { storeRegister(r14,r15); build MovMUReg1_13; }\nMovMUReg1_14:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=14 { storeRegister(r14,r15); }\n\nMovMUReg1_15:\tMovMUReg1_14\tis MovMUReg1_14 { storeRegister(pr,r15); build MovMUReg1_14; }\nMovMUReg1_15:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=15 { storeRegister(pr,r15); }\n\nMovMUReg1: MovMUReg1_15 is MovMUReg1_15 {\n\tbuild MovMUReg1_15;\n}\n\n# MOVMU.L Rm, @-R15 0100mmmm11110000\n:movmu.l MovMUReg1, @-r15\n is r15 & opcode_12_15=0b0100 & rm_imm_08_11 & opcode_00_07=0b11110000 & MovMUReg1\n{\n build MovMUReg1;\n}\n\nMovMUReg2_0:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { loadRegister(r0,r15); }\n\nMovMUReg2_1:\tMovMUReg2_0 \tis MovMUReg2_0 { build MovMUReg2_0; loadRegister(r1,r15); }\nMovMUReg2_1:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=1 { loadRegister(r1,r15); }\n\nMovMUReg2_2:\tMovMUReg2_1 \tis MovMUReg2_1 { build MovMUReg2_1; loadRegister(r2,r15); }\nMovMUReg2_2:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=2 { loadRegister(r2,r15); }\n\nMovMUReg2_3:\tMovMUReg2_2 \tis MovMUReg2_2 { build MovMUReg2_2; loadRegister(r3,r15); }\nMovMUReg2_3:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=3 { loadRegister(r3,r15); }\n\nMovMUReg2_4:\tMovMUReg2_3 \tis MovMUReg2_3 { build MovMUReg2_3; loadRegister(r4,r15); }\nMovMUReg2_4:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=4 { loadRegister(r4,r15); }\n\nMovMUReg2_5:\tMovMUReg2_4 \tis MovMUReg2_4 { build MovMUReg2_4; loadRegister(r5,r15); }\nMovMUReg2_5:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=5 { loadRegister(r5,r15); }\n\nMovMUReg2_6:\tMovMUReg2_5 \tis MovMUReg2_5 { build MovMUReg2_5; loadRegister(r6,r15); }\nMovMUReg2_6:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=6 { loadRegister(r6,r15); }\n\nMovMUReg2_7:\tMovMUReg2_6 \tis MovMUReg2_6 { build MovMUReg2_6; loadRegister(r7,r15); }\nMovMUReg2_7:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=7 { loadRegister(r7,r15); }\n\nMovMUReg2_8:\tMovMUReg2_7 \tis MovMUReg2_7 { build MovMUReg2_7; loadRegister(r8,r15); }\nMovMUReg2_8:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=8 { loadRegister(r8,r15); }\n\nMovMUReg2_9:\tMovMUReg2_8 \tis MovMUReg2_8 { build MovMUReg2_8; loadRegister(r9,r15); }\nMovMUReg2_9:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=9 { loadRegister(r9,r15); }\n\nMovMUReg2_10:\tMovMUReg2_9 \tis MovMUReg2_9 { build MovMUReg2_9; loadRegister(r10,r15); }\nMovMUReg2_10:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=10 { loadRegister(r10,r15); }\n\nMovMUReg2_11:\tMovMUReg2_10 \tis MovMUReg2_10 { build MovMUReg2_10; loadRegister(r11,r15); }\nMovMUReg2_11:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=11 { loadRegister(r11,r15); }\n\nMovMUReg2_12:\tMovMUReg2_11 \tis MovMUReg2_11 { build MovMUReg2_11; loadRegister(r12,r15); }\nMovMUReg2_12:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=12 { loadRegister(r12,r15); }\n\nMovMUReg2_13:\tMovMUReg2_12\tis MovMUReg2_12 { build MovMUReg2_12; loadRegister(r13,r15); }\nMovMUReg2_13:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=13 { loadRegister(r13,r15); }\n\nMovMUReg2_14:\tMovMUReg2_13\tis MovMUReg2_13 { build MovMUReg2_13; loadRegister(r14,r15); }\nMovMUReg2_14:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=14 { loadRegister(r14,r15); }\n\nMovMUReg2_15:\tMovMUReg2_14\tis MovMUReg2_14 { build MovMUReg2_14; loadRegister(pr,r15); }\nMovMUReg2_15:\trm_imm_08_11 is rm_imm_08_11 & rm_08_11=15 { loadRegister(pr,r15); }\n\nMovMUReg2: MovMUReg2_15 is MovMUReg2_15 {\n\tbuild MovMUReg2_15;\n}\n\n# MOVMU.L @R15+, Rn 0100nnnn11110100\n:movmu.l @r15+, MovMUReg2\n is r15 & opcode_12_15=0b0100 & rn_imm_08_11 & opcode_00_07=0b11110100 & MovMUReg2\n{\n\tbuild MovMUReg2;\n}\n\n\n# MOVRT Rn 0000nnnn00111001 ~ T → Rn\n:movrt rn_08_11 is opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00111001\n{\n rn_08_11 = zext($(T_FLAG) == 0);\n}\n\n# NOTT 0000000001101000 ~ T → T\n:nott is opcode_00_15=0b0000000001101000\n{\n $(T_FLAG) = ~$(T_FLAG);\n}\n\n@endif\n\n:swap.b rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1000 \n{\n local temp0;\n local temp1;\n \n temp0 = rm_04_07 & 0xFFFF0000;\n temp1 = (rm_04_07 & 0x000000FF) << 8;\n \n rn_08_11 = (rm_04_07 & 0x0000FF00) >> 8;\n rn_08_11 = rn_08_11 | temp1 | temp0;\n}\n\n:swap.w rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1001 \n{\n local temp;\n \n temp = (rm_04_07 >> 16) & 0x0000FFFF;\n \n rn_08_11 = rm_04_07 << 16;\n rn_08_11 = rn_08_11 | temp;\n}\n\n:xtrct rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 \n{\n local high;\n local low;\n \n high = (rm_04_07 << 16) & 0xFFFF0000;\n low = (rn_08_11 >> 16) & 0x0000FFFF;\n rn_08_11 = high | low;\n}\n\n#\n# Arithmetic Operation Instructions\n#\n:add rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 \n{\n rn_08_11 = rn_08_11 + rm_04_07;\n}\n\n:add simm_00_07,rn_08_11 is opcode_12_15=0b0111 & rn_08_11 & simm_00_07\n{\n rn_08_11 = rn_08_11 + simm_00_07;\n}\n\n:addc rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 \n{\n local temp0;\n local temp1;\n \n temp1 = rn_08_11 + rm_04_07;\n temp0 = rn_08_11;\n\n rn_08_11 = temp1 + zext($(T_FLAG)); \n \n $(T_FLAG) = (temp0 > temp1) | (temp1 > rn_08_11);\n}\n\n:addv rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 \n{\n local dest:1;\n local src:1;\n local ans:1;\n \n dest = (rn_08_11 s< 0);\n src = (rm_04_07 s< 0);\n \n src = src + dest;\n rn_08_11 = rn_08_11 + rm_04_07;\n \n ans = (rn_08_11 s< 0);\n \n ans = ans + dest;\n\n $(T_FLAG) = (src == 0 || src == 2) && (ans == 1); \n}\n\n:cmp\"/eq\" simm_00_07,r0 is r0 & opcode_08_15=0b10001000 & simm_00_07\n{\n $(T_FLAG) = (r0 == simm_00_07);\n}\n\n:cmp\"/eq\" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 \n{\n $(T_FLAG) = (rn_08_11 == rm_04_07);\n}\n\n:cmp\"/hs\" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 \n{ \n $(T_FLAG) = (rn_08_11 >= rm_04_07);\n}\n\n:cmp\"/ge\" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0011 \n{ \n $(T_FLAG) = (rn_08_11 s>= rm_04_07); \n}\n\n:cmp\"/hi\" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 \n{\n $(T_FLAG) = (rn_08_11 > rm_04_07); \n}\n\n:cmp\"/gt\" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 \n{\n $(T_FLAG) = (rn_08_11 s> rm_04_07);\n}\n\n:cmp\"/pl\" rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010101 \n{\n $(T_FLAG) = (rn_08_11 s> 0);\n}\n\n:cmp\"/pz\" rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010001 \n{\n $(T_FLAG) = (rn_08_11 s>= 0);\n}\n\n:cmp\"/str\" rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 \n{\n local tmp0:1 = (rm_04_07[0,8] == rn_08_11[0,8]);\n local tmp1:1 = (rm_04_07[8,8] == rn_08_11[8,8]);\n local tmp2:1 = (rm_04_07[16,8] == rn_08_11[16,8]);\n local tmp3:1 = (rm_04_07[24,8] == rn_08_11[24,8]);\n \n $(T_FLAG) = tmp0 || tmp1 || tmp2 || tmp3;\n}\n\n@if SH_VERSION == \"2A\"\n\n# The pseudo code for clips in the super-h manual looks incorrect,\n# this solution was contributed by @mumbel\n:clips.b rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10010001\n{\n local uppercheck = (rn_08_11 s> 0x7f);\n local lowercheck = (rn_08_11 s< -0x80);\n if (!(uppercheck || lowercheck)) goto inst_next;\n rn_08_11 = (0x0000007f * zext(uppercheck)) + (0xffffff80 * zext(lowercheck));\n $(CS_FLAG)=1;\n}\n\n:clips.w rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10010101\n{\n local uppercheck = (rn_08_11 s> 0x7fff);\n local lowercheck = (rn_08_11 s< -0x8000);\n if (!(uppercheck || lowercheck)) goto inst_next;\n rn_08_11 = (0x00007fff * zext(uppercheck)) + (0xffff8000 * zext(lowercheck));\n $(CS_FLAG)=1;\n}\n\n:clipu.b rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000001\n{\n if (rn_08_11 <= 0x000000ff) goto ;\n rn_08_11 = 0x000000ff;\n $(CS_FLAG) = 1;\n\n}\n\n:clipu.w rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000101\n{\n if (rn_08_11 <= 0x0000ffff) goto ;\n rn_08_11 = 0x0000ffff;\n $(CS_FLAG) = 1;\n\n}\n\n@endif\n\n:div0s rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 \n{\n $(Q_FLAG) = rn_08_11 s< 0;\n $(M_FLAG) = rm_04_07 s< 0;\n \n $(T_FLAG) = !($(M_FLAG) == $(Q_FLAG));\n}\n\n:div0u is opcode_00_15=0b0000000000011001 \n{\n $(M_FLAG) = 0;\n $(Q_FLAG) = 0;\n $(T_FLAG) = 0;\n}\n\n:div1 rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 \n{\n local tmp0:4;\n local tmp1:1;\n local tmp2:4;\n local old_q:1;\n local old_q_eq_m:1;\n local m_eq_q:1;\n \n old_q = $(Q_FLAG);\n $(Q_FLAG) = (0x80000000 & rn_08_11) != 0;\n tmp2 = rm_04_07;\n rn_08_11 = rn_08_11 << 1;\n rn_08_11 = rn_08_11 | zext($(T_FLAG));\n old_q_eq_m = old_q == $(M_FLAG);\n m_eq_q = $(M_FLAG) == $(Q_FLAG);\n \n tmp0 = rn_08_11;\n # rn_08_11 = old_q_eq_m ? rn_08_11 - tmp2 : rn_08_11 + tmp2;\n rn_08_11 = (zext(old_q_eq_m) * (rn_08_11 - tmp2)) + (zext(!old_q_eq_m) * (rn_08_11 + tmp2));\n # tmp1 = old_q_eq_m ? rn_08_11 > tmp0 : rn_08_11 < tmp0;\n tmp1 = (old_q_eq_m * (rn_08_11 > tmp0)) + (!old_q_eq_m * (rn_08_11 < tmp0));\n # $(Q_FLAG) = m_eq_q ? tmp1 : tmp1 == 0;\n $(Q_FLAG) = (m_eq_q * tmp1) + (!m_eq_q & (tmp1 == 0));\n \n $(T_FLAG) = $(Q_FLAG) == $(M_FLAG);\n}\n\n@if SH_VERSION == \"2A\"\n\n:divs r0, rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10010100\n{\n rn_08_11 = rn_08_11 s/ r0;\n}\n\n:divu r0, rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000100\n{\n rn_08_11 = rn_08_11 / r0;\n}\n\n@endif\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:dmuls.l rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 \n{\n local a:8 = sext(rn_08_11);\n local b:8 = sext(rm_04_07);\n local result:8 = a * b;\n\n mach = result(4);\n macl = result:4;\n}\n\n:dmulu.l rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 \n{\n local a:8 = zext(rn_08_11);\n local b:8 = zext(rm_04_07);\n local result:8 = a * b;\n\n mach = result(4);\n macl = result:4;\n}\n\n:dt rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010000 \n{\n rn_08_11 = rn_08_11 - 1;\n $(T_FLAG) = (rn_08_11 == 0);\n}\n@endif\n\n:exts.b rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 \n{\n local temp:1 = rm_04_07:1;\n rn_08_11 = sext(temp);\n}\n\n:exts.w rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 \n{\n local temp:2 = rm_04_07:2;\n rn_08_11 = sext(temp);\n}\n\n:extu.b rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 \n{\n local temp:1 = rm_04_07:1;\n rn_08_11 = zext(temp);\n}\n\n:extu.w rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 \n{\n local temp:2 = rm_04_07:2;\n rn_08_11 = zext(temp);\n}\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:mac.l @rm_04_07+,@rn_08_11+ is opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 \n{\n # FIXME: review this instruction\n \n local RnL;\n local RnH;\n local RmL;\n local RmH;\n local Res0;\n local Res1:4;\n local Res2:4;\n \n local temp0;\n local temp1:4;\n local temp2:4;\n local temp3;\n \n local tempm:4;\n local tempn:4;\n local fnLmL:4;\n \n tempn = *:4 rn_08_11;\n rn_08_11 = rn_08_11 + 4;\n tempm = *:4 rm_04_07;\n rm_04_07 = rm_04_07 + 4;\n\n fnLmL = -1 * zext((tempn ^ tempm) s<0);\n \n if( tempn s>= 0) goto ;\n tempn = 0 - tempn;\n \n \n if( tempm s>= 0) goto ;\n tempm = 0 - tempm;\n \n \n \n temp1 = tempn;\n temp2 = tempm;\n \n RnL = temp1 & 0x0000FFFF;\n RnH = (temp1 >> 16) & 0x0000FFFF;\n RmL = temp2 & 0x0000FFFF;\n RmH = (temp2 >> 16) & 0x0000FFFF;\n temp0 = RmL * RnL;\n temp1 = RmH * RnL;\n temp2 = RmL * RnH;\n temp3 = RmH * RnH;\n\n Res2 = 0;\n Res1 = temp1 + temp2;\n \n if(Res2 >= temp1) goto ;\n Res2 = Res2 + 0x00010000; \n \n \n temp1 = (Res1 << 16) & 0xFFFF0000;\n\n Res0 = temp0 + temp1; \n Res2 = Res2 + zext(Res0 < temp0);\n \n Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;\n\n if(fnLmL s>= 0) goto ;\n Res2 = ~Res2;\n \n if(Res0 == 0) goto ;\n Res0 = (~Res0) + 1;\n goto ;\n \n \n Res2 = Res2 + 1;\n \n \n \n if($(S_FLAG) != 1) goto ;\n \n Res0 = macl + Res0;\n Res2 = Res2 + zext(macl > Res0);\n \n Res2 = Res2 + (mach & 0x0000FFFF);\n \n if((Res2 s>= 0) || Res2 >= 0xFFFF8000) goto ;\n Res2 = 0xFFFF8000;\n Res0 = 0x00000000;\n \n \n if((Res2 s<= 0) || Res2 <= 0x00007FFF) goto ;\n Res2 = 0x00007FFF;\n Res0 = 0xFFFFFFFF;\n \n \n mach = (Res2 & 0x0000FFFF) | (mach & 0xFFFF0000);\n macl = Res0;\n \n goto ;\n \n \n Res0 = macl + Res0;\n Res2 = Res2 + zext(macl > Res0);\n \n Res2 = Res2 + mach;\n mach = Res2;\n macl = Res0;\n \n \n}\n@endif\n\n:mac.w @rm_04_07+,@rn_08_11+ is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 \n{\n # FIXME: review this instruction\n \n local tempm:4;\n local tempn:4;\n local dest;\n local src:4; \n local ans;\n local templ:4;\n \n tempn = *:2 rn_08_11;\n rn_08_11 = rn_08_11 + 2; \n tempm = *:2 rm_04_07;\n rm_04_07 = rm_04_07 + 2;\n \n templ = macl;\n tempm = sext(tempn:2) * sext(tempm:2);\n \n dest = (macl s< 0);\n \n src = zext(1*(tempm s>= 0));\n tempn = sext(-1*(tempm s>= 0));\n\n src = src + zext(dest);\n macl = macl + tempm; \n \n ans = (macl s< 0);\n \n ans = ans + dest; \n \n # if (S == 1)\n if($(S_FLAG) != 1) goto ;\n \n if(ans != 1) goto ;\n \n@if SH_VERSION == \"1\"\n if(src != 0 && src != 2) goto ;\n mach = mach | 0x00000001; \n \n@endif\n\n if(src == 0) goto ;\n if(src == 2) goto ;\n goto ;\n \n \n macl = 0x7FFFFFFF;\n goto ;\n \n \n macl = 0x80000000;\n goto ;\n \n # if (S != 1)\n \n \n mach = mach + tempn;\n\n macl = macl + zext(1*(templ s> macl));\n \n@if SH_VERSION == \"1\"\n if((mach & 0x00000200) == 0) goto ;\n mach = mach | 0xFFFFFC00;\n goto ;\n \n mach = mach & 0x000003FF;\n@endif\n\n \n}\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:mul.l rm_04_07,rn_08_11 is opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 \n{\n macl = rn_08_11 * rm_04_07;\n}\n@endif\n\n@if SH_VERSION == \"2A\"\n:mulr r0, rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000000\n{\n rn_08_11 = r0 * rn_08_11;\n}\n@endif\n\n:muls.w rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 \n{\n macl = sext(rn_08_11:2) * sext(rm_04_07:2);\n}\n\n:mulu.w rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 \n{\n macl = zext(rn_08_11:2) * zext(rm_04_07:2);\n}\n\n:neg rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1011 \n{\n rn_08_11 = -rm_04_07;\n}\n\n:negc rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1010 \n{\n local temp:4 = -rm_04_07;\n rn_08_11 = temp - zext($(T_FLAG));\n \n $(T_FLAG) = (0 != temp) || (temp < rn_08_11);\n}\n\n:sub rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1000 \n{\n rn_08_11 = rn_08_11 - rm_04_07;\n}\n\n:subc rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1010 \n{\n local temp0;\n local temp1;\n \n temp1 = rn_08_11 - rm_04_07;\n temp0 = rn_08_11;\n \n rn_08_11 = temp1 - zext($(T_FLAG));\n \n $(T_FLAG) = (temp0 < temp1 || temp1 < rn_08_11);\n}\n\n:subv rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1011 \n{\n local dest;\n local src;\n local ans;\n\n dest = (rn_08_11 s< 0);\n src = (rm_04_07 s< 0);\n\n src = src + dest; \n rn_08_11 = rn_08_11 - rm_04_07;\n\n ans = (rn_08_11 s< 0);\n ans = ans + dest;\n\n $(T_FLAG) = (src == 1) && (ans == 1);\n}\n\n#\n# Logic Operation Instructions\n#\n:and rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1001 \n{\n rn_08_11 = rn_08_11 & rm_04_07;\n}\n\n:and imm_00_07,r0 is r0 & opcode_08_15=0b11001001 & imm_00_07 \n{\n r0 = (r0 & zext(imm_00_07:1));\n}\n\n:and.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001101 & imm_00_07 \n{\n local temp:1 = *:1 (gbr + r0);\n temp = temp & imm_00_07:1;\n \n *:1 (gbr + r0) = temp;\n}\n\n:not rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 \n{\n rn_08_11 = ~rm_04_07;\n}\n\n:or rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1011 \n{\n rn_08_11 = rn_08_11 | rm_04_07;\n}\n\n:or imm_00_07,r0 is r0 & opcode_08_15=0b11001011 & imm_00_07 \n{\n r0 = r0 | imm_00_07:4;\n}\n\n:or.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001111 & imm_00_07 \n{\n local temp:1 = *:1 (gbr + r0);\n temp = temp | imm_00_07:1;\n\n *:1 (gbr + r0) = temp;\n}\n\n:tas.b @rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00011011 \n{\n local temp = *:1 rn_08_11;\n \n $(T_FLAG) = (temp == 0);\n \n temp = temp | 0x80;\n \n *:1 rn_08_11 = temp;\n}\n\n:tst rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1000 \n{\n $(T_FLAG) = ((rm_04_07 & rn_08_11) == 0);\n}\n\n:tst imm_00_07,r0 is r0 & opcode_08_15=0b11001000 & imm_00_07 \n{\n local temp = r0 & (imm_00_07 & 0x000000FF);\n \n $(T_FLAG) = (temp == 0);\n}\n\n:tst.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001100 & imm_00_07 \n{\n local temp = *:1 (gbr + r0);\n temp = temp & (imm_00_07 & 0x000000FF);\n \n $(T_FLAG) = (temp == 0);\n}\n\n:xor rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1010 \n{\n rn_08_11 = rn_08_11 ^ rm_04_07;\n}\n\n:xor imm_00_07,r0 is r0 & opcode_08_15=0b11001010 & imm_00_07 \n{\n r0 = r0 ^ (imm_00_07 & 0x000000FF);\n}\n\n:xor.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001110 & imm_00_07 \n{\n local temp = *:1 (gbr + r0);\n temp = temp & (imm_00_07 & 0x000000FF);\n \n *:1 (gbr + r0) = temp;\n}\n\n#\n#Shift Instructions\n#\n:rotcl rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100100\n{\n local temp:1;\n \n temp = ((rn_08_11 & 0x80000000) != 0);\n \n rn_08_11 = (rn_08_11 << 1) | zext($(T_FLAG));\n \n $(T_FLAG) = temp;\n}\n\n:rotcr rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100101 \n{\n local temp:1;\n \n temp = !((rn_08_11 & 1) == 0);\n \n rn_08_11= (rn_08_11 >> 1) | (0x80000000 * zext($(T_FLAG)));\n\n $(T_FLAG) = temp;\n}\n\n:rotl rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000100 \n{\n $(T_FLAG) = ((rn_08_11 & 0x80000000) != 0);\n \n rn_08_11 = (rn_08_11 << 1) | zext($(T_FLAG));\n}\n\n:rotr rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000101 \n{\n $(T_FLAG) = ((rn_08_11 & 0x1) != 0);\n \n rn_08_11 = (rn_08_11 >> 1) | (rn_08_11 << 31);\n}\n\n@if SH_VERSION == \"2A\"\n:shad rm_04_07, rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100\n{\n if (rm_04_07 s> 0) goto ;\n if (rm_04_07 s<= -32) goto ;\n # shift right\n rn_08_11 = rn_08_11 s>> -rm_04_07;\n goto ;\n\n rn_08_11 = rn_08_11 << (rm_04_07 & 0x0000001F);\n goto ;\n\n rn_08_11 = -1 * zext(rn_08_11 s< 0);\n\n}\n@endif\n\n:shal rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100000 \n{\n # clear or set T\n $(T_FLAG) = ((rn_08_11 & 0x80000000) != 0);\n \n rn_08_11 = rn_08_11 << 1;\n}\n\n:shar rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100001 \n{\n $(T_FLAG) = ((rn_08_11 & 1) == 1);\n \n rn_08_11 = rn_08_11 s>> 1;\n}\n\n@if SH_VERSION == \"2A\"\n:shld rm_04_07, rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101\n{\n if (rm_04_07 s> 0) goto ;\n if (rm_04_07 s<= -32) goto ;\n # shift right\n rn_08_11 = rn_08_11 >> -rm_04_07;\n goto ;\n\n rn_08_11 = rn_08_11 << (rm_04_07 & 0x0000001F);\n goto ;\n\n rn_08_11 = 0;\n\n}\n@endif\n\n:shll rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000000 \n{\n # clear or set T\n $(T_FLAG) = ((rn_08_11 & 0x80000000) != 0);\n \n rn_08_11 = rn_08_11 << 1;\n}\n\n:shll2 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00001000 \n{\n rn_08_11 = rn_08_11 << 2;\n}\n\n:shll8 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00011000 \n{\n rn_08_11 = rn_08_11 << 8;\n}\n\n:shll16 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00101000 \n{\n rn_08_11 = rn_08_11 << 16;\n}\n\n:shlr rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000001 \n{\n # clear or set T\n $(T_FLAG) = (rn_08_11 & 1) == 1;\n \n rn_08_11 = rn_08_11 >> 1; \n}\n\n:shlr2 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00001001 \n{\n rn_08_11 = rn_08_11 >> 2;\n}\n\n:shlr8 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00011001 \n{\n rn_08_11 = rn_08_11 >> 8;\n}\n\n:shlr16 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00101001 \n{\n rn_08_11 = rn_08_11 >> 16;\n}\n\n#\n# Branch Instructions\n#\n:bf target00_07 is opcode_08_15=0b10001011 & target00_07\n{\n if ($(T_FLAG) == 0) goto target00_07;\n}\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:bf\"/s\" target00_07 is opcode_08_15=0b10001111 & target00_07 \n{\n local cond = $(T_FLAG);\n delayslot(1);\n if (cond==0) goto target00_07;\n}\n@endif\n\n:bt target00_07 is opcode_08_15=0b10001001 & target00_07 \n{\n if ($(T_FLAG) == 1) goto target00_07;\n}\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:bt\"/s\" target00_07 is opcode_08_15=0b10001101 & target00_07\n{\n local cond = $(T_FLAG);\n delayslot(1);\n if (cond==1) goto target00_07;\n}\n@endif\n\n:bra target00_11 is opcode_12_15=0b1010 & target00_11 \n{\n delayslot(1);\n goto target00_11;\n}\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:braf rm_08_11 is opcode_12_15=0b0000 & rm_08_11 & opcode_00_07=0b00100011 \n{\n local dest:4 = inst_start + 4 + rm_08_11;\n delayslot(1);\n goto [dest];\n}\n@endif\n\n:bsr target00_11 is opcode_12_15=0b1011 & target00_11 \n{\n local _pr:4 = inst_start + 4;\n\n delayslot(1);\n\n pr = _pr;\n call target00_11;\n}\n\n@if (SH_VERSION == \"2\") || (SH_VERSION == \"2A\")\n:bsrf rm_08_11 is opcode_12_15=0b0000 & rm_08_11 & opcode_00_07=0b00000011 \n{\n local _pr = inst_start + 4;\n local dest = rm_08_11 + inst_start + 4;\n\n delayslot(1);\n\n pr = _pr;\n call [dest];\n}\n@endif\n\n:jmp @rm_08_11 is opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00101011 \n{\n local _pc:4 = rm_08_11;\n delayslot(1);\n pc = _pc;\n goto [pc];\n}\n\n:jsr @rm_08_11 is opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00001011 \n{\n local _pr:4 = inst_start + 4;\n local _pc:4 = rm_08_11;\n\n delayslot(1);\n\n pr = _pr;\n pc = _pc;\n call [_pc];\n}\n\n:rts is opcode_00_15=0b0000000000001011 \n{\n local _pc = pr;\n delayslot(1);\n pc = _pc;\n return [pc];\n}\n\n@if SH_VERSION == \"2A\"\n\n# JSR/N @Rm 0100mmmm01001011 PC - 2 → PR, Rm → PC\n:jsr\"/n\" @rm_08_11\n is opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01001011\n{\n pr = inst_next;\n call [rm_08_11];\n}\n\n# JSR/N @@(disp8, TBR) 10000011dddddddd PC - 2 → PR, (disp×4+TBR) → PC\n:jsr\"/n\" @@(disp, tbr)\n is tbr & opcode_08_15=0b10000011 & disp_00_07\n [ disp = disp_00_07*4; ]\n{\n pr = inst_next;\n call [tbr + disp*4];\n}\n\n# RTS/N 0000000001101011 PR → PC\n:rts\"/n\"\n is opcode_00_15=0b0000000001101011\n{\n return [pr];\n}\n\n:rtv\"/n\" rm_08_11 is opcode_12_15=0b0000 & rm_08_11 & opcode_00_07=0b01111011\n{\n r0 = rm_08_11;\n return [pr];\n}\n\n@endif\n\n\n#\n# System Control Instructions\n#\n:clrmac is opcode_00_15=0b0000000000101000 \n{\n mach = 0;\n macl = 0;\n}\n\n:clrt is opcode_00_15=0b0000000000001000 \n{\n $(T_FLAG) = 0;\n}\n\n@if SH_VERSION == \"2A\"\n:ldbank @rm_08_11, r0 is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11100101\n{\n local cnt = *:4 (rm_08_11);\n local bn = (cnt & 0x0000FF80) >> 7;\n local en = (cnt & 0x0000007C) >> 2;\n local off = (bn * 80) + en * 4;\n\n local rb = &resbank_base + off;\n\n r0 = *[register]:4 (rb);\n}\n\n:stbank r0, @rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b11100001\n{\n local cnt = *:4 (rn_08_11);\n local bn = (cnt & 0x0000FF80) >> 7;\n local en = (cnt & 0x0000007C) >> 2;\n local off = (bn * 80) + en * 4;\n\n local rb = &resbank_base + off;\n\n *[register]:4 (rb) = r0;\n}\n\n:resbank is opcode_00_15=0b0000000001011011\n{\n # This can be left as NOP, as it's used for saving/restoring context on interrupts\n r0 = r0;\n}\n\n@endif\n\n:ldc rm_08_11,sr is sr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00001110 \n{\n sr = rm_08_11 & 0x0FFF0FFF;\n}\n\n:ldc.l @rm_08_11+,sr is sr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00000111 \n{\n sr = *rm_08_11 & 0x0FFF0FFF;\n rm_08_11 = rm_08_11 + 4;\n \n}\n\n:ldc rm_08_11,gbr is gbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00011110 \n{\n gbr = rm_08_11;\n}\n\n@if SH_VERSION == \"2A\"\n:ldc rm_08_11, tbr is tbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01001010\n{\n tbr = rm_08_11;\n}\n@endif\n\n:ldc.l @rm_08_11+,gbr is gbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00010111 \n{\n gbr = *rm_08_11;\n rm_08_11 = rm_08_11 + 4;\n}\n\n:ldc rm_08_11,vbr is vbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00101110 \n{\n vbr = rm_08_11;\n}\n\n:ldc.l @rm_08_11+,vbr is vbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00100111 \n{\n vbr = *rm_08_11;\n rm_08_11 = rm_08_11 + 4;\n}\n\n:lds rm_08_11,mach is mach & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00001010 \n{\n mach = rm_08_11;\n\n@if SH_VERSION == \"1\"\n # sign extend 10 bit signed value from rm\n mach = (mach << (32-10)) s>> (32-10);\n@endif\n}\n\n:lds.l @rm_08_11+,mach is mach & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00000110 \n{\n mach = *rm_08_11;\n \n@if SH_VERSION == \"1\"\n # sign extend 10 bit signed value from rm\n mach = (mach << (32-10)) s>> (32-10);\n@endif\n \n rm_08_11 = rm_08_11 + 4;\n}\n\n:lds rm_08_11,macl is macl & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00011010 \n{\n macl = rm_08_11;\n}\n\n:lds.l @rm_08_11+,macl is macl & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00010110 \n{\n macl = *rm_08_11;\n rm_08_11 = rm_08_11 + 4;\n}\n\n:lds rm_08_11,pr is pr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00101010 \n{\n pr = rm_08_11;\n}\n\n:lds.l @rm_08_11+,pr is pr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00100110 \n{\n pr = *rm_08_11;\n rm_08_11 = rm_08_11 + 4;\n}\n\n:nop is opcode_00_15=0b0000000000001001 \n{\n # FIXME: intentional nop\n r0 = r0; # do this to suppress warning\n}\n\n:rte is opcode_00_15=0b0000000000101011 \n{ \n _pc:4 = *r15;\n r15 = r15 + 4;\n \n _sr:4 = *r15 & 0x000063F3;\n r15 = r15 + 4;\n \n delayslot(1);\n \n pc = _pc;\n sr = _sr;\n \n return [pc];\n}\n\n:sett is opcode_00_15=0b0000000000011000 \n{\n $(T_FLAG) = 1;\n}\n\ndefine pcodeop Sleep_Standby;\n\n:sleep is opcode_00_15=0b0000000000011011 \n{\n Sleep_Standby();\n}\n\n:stc sr,rn_08_11 is sr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00000010 \n{\n rn_08_11 = sr;\n}\n\n:stc.l sr,@-rn_08_11 is sr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000011 \n{\n rn_08_11 = rn_08_11 -4;\n *rn_08_11 = sr;\n}\n\n:stc gbr,rn_08_11 is gbr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00010010 \n{\n rn_08_11 = gbr;\n}\n\n@if SH_VERSION == \"2A\"\n:stc tbr,rn_08_11 is tbr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01001010 \n{\n rn_08_11 = tbr;\n}\n@endif\n\n:stc.l gbr,@-rn_08_11 is gbr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010011 \n{\n rn_08_11 = rn_08_11 -4;\n *rn_08_11 = gbr;\n}\n\n:stc vbr,rn_08_11 is vbr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00100010 \n{\n rn_08_11 = vbr;\n}\n\n:stc.l vbr,@-rn_08_11 is vbr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100011\n{\n rn_08_11 = rn_08_11 -4;\n *rn_08_11 = vbr;\n}\n\n:sts mach,rn_08_11 is mach & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00001010 \n{\n rn_08_11 = mach;\n \n@if SH_VERSION == \"1\"\n # sign extend 10 bit signed value from rm\n rn_08_11 = (rn_08_11 << (32-10)) s>> (32-10);\n@endif\n}\n\n:sts.l mach,@-rn_08_11 is mach & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000010 \n{\n rn_08_11 = rn_08_11 - 4;\n \n local temp = mach;\n\n@if SH_VERSION == \"1\"\n # sign extend 10 bit signed value from rm\n temp = (temp << (32-10)) s>> (32-10);\n@endif\n\n *rn_08_11 = temp;\n}\n\n:sts macl,rn_08_11 is macl & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00011010 \n{\n rn_08_11 = macl;\n}\n\n:sts.l macl,@-rn_08_11 is macl & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010010 \n{\n rn_08_11 = rn_08_11 -4;\n *rn_08_11 = macl;\n}\n\n:sts pr,rn_08_11 is pr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00101010 \n{\n rn_08_11 = pr;\n}\n\n:sts.l pr,@-rn_08_11 is pr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100010 \n{\n rn_08_11 = rn_08_11 -4;\n *rn_08_11 = pr;\n}\n\n:trapa imm_00_07 is opcode_08_15=0b11000011 & imm_00_07\n{\n r15 = r15 - 4;\n *r15 = sr;\n\n r15 = r15 - 4;\n dest:4 = inst_next;\n *r15 = dest;\n\n dest = *(vbr + (imm_00_07 * 4));\n call [dest];\n}\n\n@if defined(FPU)\n\n#\n# Floating-Point Instructions\n#\n\n# FABS FRn 1111nnnn01011101 |FRn| → FRn\n:fabs ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01011101\n{\n ffrn_08_11 = abs(ffrn_08_11);\n}\n\n# TODO: FABS DRn 1111nnn001011101 |DRn| → DRn\n\n# FADD FRm, FRn 1111nnnnmmmm0000 FRn + FRm → FRn\n:fadd ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0000\n{\n ffrn_08_11 = ffrn_08_11 f+ ffrm_04_07;\n}\n\n# TODO: FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm → DRn\n\n# FCMP/EQ FRm, FRn 1111nnnnmmmm0100 (FRn=FRm)? 1:0 → T\n:fcmp\"/eq\" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0100\n{\n $(T_FLAG) = (ffrn_08_11 f== ffrm_04_07);\n}\n\n# TODO: FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn=DRm)? 1:0 → T\n\n# FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn>FRm)? 1:0 → T\n:fcmp\"/gt\" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0101\n{\n $(T_FLAG) = (ffrn_08_11 f> ffrm_04_07);\n}\n\n# TODO: FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn>DRm)? 1:0 → T\n\n# FCNVDS DRm, FPUL 1111mmm010111101 (float) DRm → FPUL\n:fcnvds fdrm_09_11, fpul is fpul & fop_12_15=0b1111 & fdrm_09_11 & fop_08_08=0b0 & fop_00_07=0b10111101\n{\n fpul = float2float(fdrm_09_11);\n}\n\n# FCNVSD FPUL, DRn 1111nnn010101101 (double) FPUL → DRn\n:fcnvsd fpul, fdrn_09_11 is fpul & fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b10101101\n{\n fdrn_09_11 = float2float(fpul);\n}\n\n# FDIV FRm, FRn 1111nnnnmmmm0011 FRn/FRm → FRn\n:fdiv ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0011\n{\n ffrn_08_11 = ffrn_08_11 f/ ffrm_04_07;\n}\n\n# TODO: FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm → DRn\n\n# FLDI0 FRn 1111nnnn10001101 0 × 00000000 → FRn\n:fldi0 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10001101\n{\n ffrn_08_11 = 0x00000000;\n}\n\n# FLDI1 FRn 1111nnnn10011101 0 × 3F800000 → FRn\n:fldi1 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10011101\n{\n ffrn_08_11 = 0x3F800000;\n}\n\n\n# FLDS FRm, FPUL 1111mmmm00011101 FRm → FPUL\n:flds ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00011101\n{\n fpul = ffrm_08_11;\n}\n\n# FLOAT FPUL,FRn 1111nnnn00101101 (float) FPUL → FRn\n:float fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00101101\n{\n ffrn_08_11 = int2float(fpul);\n}\n\n# TODO: FLOAT FPUL,DRn 1111nnn000101101 (double) FPUL → DRn\n\n# FMAC FR0, FRm, FRn 1111nnnnmmmm1110 FR0 × FRm + FRn → FRn\n:fmac fr0, ffrm_04_07, ffrn_08_11 is fr0 & fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1110\n{\n ffrn_08_11 = ffrn_08_11 f+ (ffrm_04_07 f* fr0);\n}\n\n# FMOV FRm, FRn 1111nnnnmmmm1100 FRm → FRn\n:fmov ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1100\n{\n ffrn_08_11 = ffrm_04_07;\n}\n\n# TODO: FMOV DRm, DRn 1111nnn0mmm01100 DRm → DRn\n\n# FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 (R0+Rm) → FRn\n:fmov.s @(r0, f_rm_04_07), ffrn_08_11 is r0 & fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b0110\n{\n ffrn_08_11 = *:4 (r0 + f_rm_04_07);\n}\n\n# TODO: FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0+Rm) → DRn\n\n# FMOV.S @Rm+, FRn 1111nnnnmmmm1001 (Rm) → FRn, Rm+ = 4\n:fmov.s @f_rm_04_07+, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1001\n{\n ffrn_08_11 = *:4 (f_rm_04_07);\n f_rm_04_07 = f_rm_04_07 + 4;\n}\n\n# TODO: FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm) → DRn, Rm+ = 8\n\n# FMOV.S @Rm, FRn 1111nnnnmmmm1000 (Rm) → FRn\n:fmov.s @f_rm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1000\n{\n ffrn_08_11 = *:4 (f_rm_04_07);\n}\n\n# TODO: FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm) → DRn\n\n# FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd (disp×4+Rm) → FRn\n:fmov.s @(disp12, lf_rm_20_23), lffrn_24_27\n is lfop_28_31=0b0011 & lffrn_24_27 & lf_rm_20_23 & lfop_12_19=0b00010111 & lfdisp_00_11\n [ disp12 = lfdisp_00_11 * 4; ]\n{\n lffrn_24_27 = *:4 (disp12 + lf_rm_20_23);\n}\n\n# TODO: FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd (disp×8+Rm) → DRn\n\n# FMOV.S FRm, @( R0,Rn ) 1111nnnnmmmm0111 FRm → (R0+Rn)\n:fmov.s ffrm_04_07, @( r0, f_rn_08_11 ) is r0 & fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b0111\n{\n *:4 (f_rn_08_11 + r0) = ffrm_04_07;\n}\n\n# TODO: FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 DRm → (R0+Rn)\n\n# FMOV.S FRm, @-Rn 1111nnnnmmmm1011 Rn- = 4, FRm → (Rn)\n:fmov.s ffrm_04_07, @-f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1011\n{\n f_rn_08_11 = f_rn_08_11 - 4;\n *:4 (f_rn_08_11) = ffrm_04_07;\n}\n\n# TODO: FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn- = 8, DRm → (Rn)\n\n# FMOV.S FRm, @Rn 1111nnnnmmmm1010 FRm → (Rn)\n:fmov.s ffrm_04_07, @f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1010\n{\n *:4 (f_rn_08_11) = ffrm_04_07;\n}\n\n# TODO: FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm → (Rn)\n\n# FMOV.S FRm, @(disp12,Rn) 0011nnnnmmmm0001 0011dddddddddddd FRm → (disp×4+Rn)\n:fmov.s lffrm_20_23, @(disp12, lf_rn_24_27)\n is lfop_28_31=0b0011 & lf_rn_24_27 & lffrm_20_23 & lfop_12_19=0b00010011 & lfdisp_00_11\n [ disp12 = lfdisp_00_11 * 4; ]\n{\n *:4 (disp12 + lf_rn_24_27) = lffrm_20_23;\n}\n\n\n# TODO: FMOV.D DRm, @(disp12,Rn) 0011nnnnmmm000010 011dddddddddddd DRm → (disp×8+Rn)\n\n# FMUL FRm, FRn 1111nnnnmmmm0010 FRn × FRm → FRn\n:fmul ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0010\n{\n ffrn_08_11 = ffrn_08_11 f* ffrm_04_07;\n}\n\n# TODO: FMUL DRm, DRn 1111nnn0mmm00010 DRn × DRm → DRn\n# FNEG FRn 1111nnnn01001101 -FRn → FRn\n:fneg ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01001101\n{\n ffrn_08_11 = f- ffrn_08_11;\n}\n\n# TODO: FNEG DRn 1111nnn001001101 -DRn → DRn\n# FSCHG 1111001111111101 FPSCR.SZ = ~ FPSCR.SZ\n:fschg is fop_00_15=0b1111001111111101\n{\n $(FP_SZ) = ~ $(FP_SZ);\n}\n\n# FSQRT FRn 1111nnnn01101101 √FRn → FRn\n:fsqrt ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01101101\n{\n ffrn_08_11 = sqrt(ffrn_08_11);\n}\n\n# TODO: FSQRT DRn 1111nnn001101101 √DRn → DRn\n# FSTS FPUL, FRn 1111nnnn00001101 FPUL → FRn\n:fsts fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00001101\n{\n ffrn_08_11 = fpul;\n}\n\n# FSUB FRm, FRn 1111nnnnmmmm0001 FRn - FRm → FRn\n:fsub ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0001\n{\n ffrn_08_11 = ffrn_08_11 f- ffrm_04_07;\n}\n\n# TODO: FSUB DRm, DRn 1111nnn0mmm00001 DRn - DRm → DRn\n\n# FTRC FRm, FPUL 1111mmmm00111101 (long) FRm → FPUL\n:ftrc ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00111101\n{\n fpul = trunc(ffrm_08_11);\n}\n\n# FTRC DRm, FPUL 1111mmm000111101 (long) DRm → FPUL\n\n@endif\n\n\n@if defined(FPU)\n\n#\n# FPU-related CPU Instructions\n#\n\n# LDS Rm,FPSCR 0100mmmm01101010 Rm → FPSCR\n:lds rm_08_11, fpscr is fpscr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01101010\n{\n fpscr = rm_08_11;\n}\n\n# LDS Rm,FPUL 0100mmmm01011010 Rm → FPUL\n:lds rm_08_11, fpul is fpul & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01011010\n{\n fpul = rm_08_11;\n}\n\n# LDS.L @Rm+, FPSCR 0100mmmm01100110 (Rm) → FPSCR, Rm+ = 4\n:lds.l @rm_08_11+, fpscr is fpscr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01100110\n{\n fpscr = *:4 (rm_08_11);\n rm_08_11 = rm_08_11 + 4;\n}\n\n# LDS.L @Rm+, FPUL 0100mmmm01010110 (Rm) → FPUL, Rm+ = 4\n:lds.l @rm_08_11+, fpul is fpul & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01010110\n{\n fpul = *:4 (rm_08_11);\n rm_08_11 = rm_08_11 + 4;\n}\n\n# STS FPSCR, Rn 0000nnnn01101010 FPSCR → Rn\n:sts fpscr, rn_08_11 is fpscr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01101010\n{\n rn_08_11 = fpscr;\n}\n\n# STS FPUL,Rn 0000nnnn01011010 FPUL → Rn\n:sts fpul, rn_08_11 is fpul & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01011010\n{\n rn_08_11 = fpul;\n}\n\n# STS.L FPSCR,@-Rn 0100nnnn01100010 Rn- = 4, fpscr → (Rn)\n:sts.l fpscr, @-rn_08_11 is fpscr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b01100010\n{\n rn_08_11 = rn_08_11 - 4;\n *:4 (rn_08_11) = fpscr;\n}\n\n# STS.L FPUL,@-Rn 0100nnnn01010010 Rn- = 4, FPUL → (Rn)\n:sts.l fpul, @-rn_08_11 is fpul & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b01010010\n{\n rn_08_11 = rn_08_11 - 4;\n *:4 (rn_08_11) = fpul;\n}\n\n# @if defined(FPU)\n@endif\n\n\n@if SH_VERSION == \"2A\"\n\n#\n# Bit Manipulation Instructions\n#\n# The BAND.B, BOR.B, and BXOR.B instructions perform logical operations between a bit in\n# memory and the T bit, and store the result in the T bit. The BCLR.B and BSET.B instructions\n# manipulate a bit in memory. The BST.B and BLD.B instructions execute a transfer between a bit\n# in memory and the T bit. The BANDNOT.B and BORNOT.B instructions perform logical\n# operations between the value resulting from inverting a bit in memory and the T bit, and store the\n# result in the T bit. The BLDNOT.B instruction inverts a bit in memory and stores the result in the\n# T bit. Bits other than the specified bit are not affected.\n#\n\n# BAND.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0100dddddddddddd (imm of (disp+Rn)) & T → T\n:band.b \"#\"l_imm3_20_22 @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0100 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n $(T_FLAG) = ((b & (1 << l_imm3_20_22)) & $(T_FLAG) != 0);\n}\n\n# BANDNOT.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 1100dddddddddddd ~ (imm of (disp+Rn)) & T → T\n:bandnot.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b1100 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n $(T_FLAG) = ((~ (b & (1 << l_imm3_20_22)) & $(T_FLAG)) != 0);\n}\n\n# BCLR.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0000dddddddddddd 0 → (imm of (disp+Rn))\n:bclr.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0000 & l_disp_00_11\n{\n local addr = l_disp_00_11 + l_rn_24_27;\n local b = *:1 (addr);\n *:1 (addr) = b & (~(1 << l_imm3_20_22));\n} \n\n# BCLR #imm3, Rn 10000110nnnn0iii 0 → imm of Rn\n:bclr \"#\"imm3_00_02, rn_04_07\n is opcode_08_15=0b10000110 & rn_04_07 & opcode_03_03=0b0 & imm3_00_02\n{\n rn_04_07 = rn_04_07 & (~(1 << imm3_00_02));\n}\n\n# BLD.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0011dddddddddddd (imm of (disp+Rn)) → T \n:bld.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0011 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n $(T_FLAG) = ((b & (1 << l_imm3_20_22)) != 0);\n}\n\n# BLD #imm3, Rn 10000111nnnn1iii imm of Rn → T\n:bld \"#\"imm3_00_02, rn_04_07\n is opcode_08_15=0b10000111 & rn_04_07 & opcode_03_03=0b1 & imm3_00_02\n{\n local b = rn_04_07;\n $(T_FLAG) = ((b & (1 << imm3_00_02)) != 0);\n}\n\n# BLDNOT.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 1011dddddddddddd ~ (imm of (disp+Rn)) → T\n:bldnot.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b1011 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n $(T_FLAG) = ((b & (1 << l_imm3_20_22)) == 0);\n}\n\n# BOR.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0101dddddddddddd (imm of (disp+ Rn)) | T → T\n:bor.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0101 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n local abit = b & (1 << l_imm3_20_22);\n $(T_FLAG) = $(T_FLAG) | (abit != 0);\n}\n\n# BORNOT.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 1101dddddddddddd ~ (imm of (disp+ Rn)) | T → T\n:bornot.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b1101 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n local abit = b & (1 << l_imm3_20_22);\n $(T_FLAG) = $(T_FLAG) | (abit == 0);\n}\n\n# BSET.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0001dddddddddddd 1 → (imm of (disp+Rn))\n:bset.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0001 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n local newb = b | (1 << l_imm3_20_22);\n *:1 (l_disp_00_11 + l_rn_24_27) = newb;\n}\n\n# BSET #imm3, Rn 10000110nnnn1iii 1 → imm of Rn\n:bset \"#\"imm3_00_02, rn_04_07\n is opcode_08_15=0b10000110 & rn_04_07 & opcode_03_03=0b1 & imm3_00_02\n{\n rn_04_07 = rn_04_07 | (1 << imm3_00_02);\n}\n\n# BST.B #imm3 ,@(disp12,Rn) 0011nnnn0iii1001 0010dddddddddddd T → (imm of (disp+Rn))\n:bst.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0010 & l_disp_00_11\n{\n local b = *:1 (l_disp_00_11 + l_rn_24_27);\n local ibit = 1 << l_imm3_20_22;\n b = (b | ibit) * ($(T_FLAG) != 0) + (b & (~ibit)) * ($(T_FLAG) == 0);\n *:1 (l_disp_00_11 + l_rn_24_27) = b;\n}\n\n# BST #imm3, Rn 10000111nnnn0iii T → imm of Rn\n:bst \"#\"imm3_00_02, rn_04_07\n is opcode_08_15=0b10000111 & rn_04_07 & opcode_03_03=0b0 & imm3_00_02\n{\n local ibit = 1 << imm3_00_02;\n rn_04_07 = (rn_04_07 | ibit) * zext($(T_FLAG) != 0) + (rn_04_07 & (~ibit)) * zext($(T_FLAG) == 0);\n}\n\n# BXOR.B #imm3, @(disp12, Rn) 0011nnnn0iii1001 0110dddddddddddd (imm of (disp+ Rn)) ^ T → T\n:bxor.b \"#\"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27)\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0110 & l_disp_00_11\n{\n\t# extract bit to test\n local b = *:1 (l_rn_24_27 + l_disp_00_11);\n local abit = (b >> l_imm3_20_22) & 1;\n \n $(T_FLAG) = $(T_FLAG) ^ abit;\n}\n\n@endif\n" }, { "path": "pypcode/processors/SuperH/data/languages/superh2a.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4.ldefs", "content": "\n\n\n \n SuperH-4(a) (SH4) big endian\n \n \n \n \n \n \n \n SuperH-4(a) (SH4) little endian\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4.opinion", "content": "\n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4.sinc", "content": "# This module defines SuperH version 4, but should work against versions 1,2, and 3. \n# There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable\n# with this.\n\n# Based on \"Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf)\n\n# Here's a nice webpage with all the insns clearly shown\n# http://shared-ptr.com/sh_insns.html\n\n# Address Space:\n# SuperH 4A has a 29-bit and a 32-bit address space mode,\n# and can do 32-bit addressing in 29-bit mode with virtual addressing.\n# The SH4 has a 29-bit physical address space, but can do 32-bit with virtual addressing.\n#\n# WARNING:\n# WARNING:\n# WARNING: Currently set up for 29-bit only for computed jumps/calls. This needs to be configurable.\n# WARNING:\n\n# NOTE: SuperH 4 and floating point disassembly and decompiling precision.\n# Many of the floating point instructions can do either single or double precision calculations depending \n# on a flag FPSCR_PR at runtime. This means at disassembly stage we don't have all the information required\n# determine the arguments to some floating point instructions.\n\n# NOTE: SuperH 4 and floating point disassembly and decompiling (fmov lengths).\n# Some of the instructions can read and write floating point values in 4 or 8 byte values depending on the\n# flag FPSCR_SZ. This means at disassembly stage we don't have all the information required to determine the\n# arguments to some floating point instructions.\n# Note that the FPSCR_PR flag is never examined during any of the fmov insns.\n\n# NOTE: SuperH and banking\n# When the RB flag is not set R1->R7 come from bank0 and when RB is set R1->R7 come from bank1. The RB mode is\n# set in privileged mode. We don't currently simulate this behavior.\n\n# NOTE: SuperH and floating point banking\n# When the flag FPSCR_FR is not set fr0->fr15 come from bank0 and when FPSCR.FR is set fr0->fr15 come from bank1.\n# We don't currently simulate this behavior.\n\n# NOTE: SuperH and memory map registers\n# There are 7 32bit control registers (SR, GBR, SSR, SPC, SGR, DBR, VBR) these are mapped to 2 different memory\n# areas 0x1C000000 and 0xFC000000. We don't currently simulate this behavior.\n\n# NOTE: SuperH/Renesas return value convention.\n# Renesas and gcc return most values from a function in r0 but floats are return in fr0 and doubles in dr0. \n# Ghidra calling spec has no way of specifying this behavior so such return values are not handled correctly.\n\n# NOTE: SuperH/Renesas calling convention\n# Renesas and gcc pass most values to a function via r4-r7 but floats are passed by fr4-fr7 and doubles in\n# dr4, dr6, dr8, and dr10. \n\n# NOTE: floating point errors\n# In implementing the floating point pcode we ignored many of the possible error conditions floating point\n# could cause. This allows us to produce much better looking decompiled code.\n\n# NOTE: SuperH 4 Memory model\n# SuperH 4 has a Memory Management Unit (i.e. MMU). Which means that depending on mode the memory can\n# look very different. We don't model this behavior. We also don't simulate the MMU address translation, \n# so all addresses are raw.\n\n\n# Basic ================================================================================\n\ndefine endian=$(ENDIAN); # Defined in file that includes this file\n\ndefine alignment=2;\n\ndefine space ram \t type=ram_space \t size=4 default;\ndefine space register type=register_space size=4;\n\n# Registers ============================================================================\n# TODO deal with the 2 banks of registers\n# TODO move os corret memory address\ndefine register offset=0 size=4 [\n\tr0 r1 r2 r3 r4 r5 r6 r7\n\tr8 r9 r10 r11 r12 r13 r14 r15\n\tR0_BANK R1_BANK R2_BANK R3_BANK R4_BANK R5_BANK R6_BANK R7_BANK\n];\n\n# This is where \"BANK0\" is with RB=0 (normal), causes duplicate pair error in SLEIGH\n#define register offset=0 size=4 [\n# R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0\n#];\n# This is where \"BANK1\" is with RB=1 (privileged), causes duplicate pair error in SLEIGH\n#define register offset=0 size=4 [\n# R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1\n#];\n@if ENDIAN == \"big\"\ndefine register offset=512 size=4 [\n\tfr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15\n\txf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15\n];\n\n@endif\n\n@if ENDIAN == \"little\"\ndefine register offset=512 size=4 [\n\tfr1 fr0 fr3 fr2 fr5 fr4 fr7 fr6 fr9 fr8 fr11 fr10 fr13 fr12 fr15 fr14\n\txf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15\n];\n\n@endif\n\ndefine register offset=512 size=8 [\n\tdr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14\n\txd0 xd2 xd4 xd6 xd8 xd10 xd12 xd14\n];\n\ndefine register offset=512 size=16 [\n\tfv0 fv4 fv8 fv12\n];\n\n# Control registers\ndefine register offset=1024 size=4 [\n\tGBR SR SSR SPC VBR SGR DBR\n];\n\n# SR component register fields (pseudo)\ndefine register offset=1536 size=1 [\n\tMD RB BL FD M Q IMASK S T\n];\n\n# System registers\ndefine register offset=2048 size=4 [\n\tMACH MACL PR PC FPSCR FPUL\n];\n\n# FPSCR component register fields (pseudo)\ndefine register offset=2560 size=1 [\n\tFPSCR_RM\n\tFPSCR_FLAG\n\tFPSCR_ENABLE\n\tFPSCR_CAUSE\n\tFPSCR_DN\n\tFPSCR_PR\n\tFPSCR_SZ\n\tFPSCR_FR\n];\n\n@define T_FLAG \"T\"\n@define S_FLAG \"S\"\n@define IMASK \"IMASK\"\n@define Q_FLAG \"Q\"\n@define M_FLAG \"M\"\n@define FD_FLAG \"FD\"\n@define BL_FLAG \"BL\"\n@define RB_FLAG \"RB\"\n@define MD_FLAG \"MD\"\n\n@define FPSCR_RM \"FPSCR_RM\"\n@define FPSCR_FLAG \"FPSCR_FLAG\"\n@define FPSCR_ENABLE \"FPSCR_ENABLE\"\n@define FPSCR_CAUSE \"FPSCR_CAUSE\"\n@define FPSCR_DN \"FPSCR_DN\"\n@define FPSCR_PR \"FPSCR_PR\"\n@define FPSCR_SZ \"FPSCR_SZ\"\n@define FPSCR_FR \"FPSCR_FR\"\n\n#\n# SR pack and unpack support\n#\n\n# 0000 0000 0000 0000 0000 0000 0000 0001\n@define T_MASK \"0x00000001\"\n\n# 0000 0000 0000 0000 0000 0000 0000 0010\n@define S_MASK \"0x00000002\"\n\n# 0000 0000 0000 0000 0000 0000 1111 0000\n@define IMASK_MASK \"0x000000F0\"\n\n# 0000 0000 0000 0000 0000 0001 0000 0000\n@define Q_MASK \"0x00000100\"\n\n# 0000 0000 0000 0000 0000 0010 0000 0000\n@define M_MASK \"0x00000200\"\n\n# 0000 0000 0000 0000 1000 0000 0000 0000\n@define FD_MASK \"0x00008000\"\n\n# 0001 0000 0000 0000 0000 0000 0000 0000\n@define BL_MASK \"0x10000000\"\n\n# 0010 0000 0000 0000 0000 0000 0000 0000\n@define RB_MASK \"0x20000000\"\n\n# 0100 0000 0000 0000 0000 0000 0000 0000\n@define MD_MASK \"0x40000000\"\n\n@define T_SHIFT \" 0\"\n@define S_SHIFT \" 1\"\n@define IMASK_SHIFT \" 4\"\n@define Q_SHIFT \" 8\"\n@define M_SHIFT \" 9\"\n@define FD_SHIFT \"15\"\n@define BL_SHIFT \"28\"\n@define RB_SHIFT \"29\"\n@define MD_SHIFT \"30\"\n\nmacro genSRregister() {\n\n\tSR = \t\n (zext(T) << $(T_SHIFT)) |\n (zext(S) << $(S_SHIFT)) |\n (zext(IMASK) << $(IMASK_SHIFT)) |\n (zext(Q) << $(Q_SHIFT)) |\n (zext(M) << $(M_SHIFT)) |\n (zext(FD) << $(FD_SHIFT)) |\n (zext(BL) << $(BL_SHIFT)) |\n (zext(RB) << $(RB_SHIFT)) |\n (zext(MD) << $(MD_SHIFT));\n}\n\nmacro splitSRregister() {\n\n\tsplitTemp:4 = (SR & $(T_MASK)) >> $(T_SHIFT);\n\tT = splitTemp:1;\n\n\tsplitTemp = (SR & $(S_MASK)) >> $(S_SHIFT);\n\tS = splitTemp:1;\n\n\tsplitTemp = (SR & $(IMASK_MASK)) >> $(IMASK_SHIFT);\n\tIMASK = splitTemp:1;\n\n\tsplitTemp = (SR & $(Q_MASK)) >> $(Q_SHIFT);\n\tQ = splitTemp:1;\n\n\tsplitTemp = (SR & $(M_MASK)) >> $(M_SHIFT);\n\tM = splitTemp:1;\n\n\tsplitTemp = (SR & $(FD_MASK)) >> $(FD_SHIFT);\n\tFD = splitTemp:1;\n\n\tsplitTemp = (SR & $(BL_MASK)) >> $(BL_SHIFT);\n\tBL = splitTemp:1;\n\n\tsplitTemp = (SR & $(RB_MASK)) >> $(RB_SHIFT);\n\tRB = splitTemp:1;\n\n\tsplitTemp = (SR & $(MD_MASK)) >> $(MD_SHIFT);\n\tMD = splitTemp:1;\n}\n\n#\n# FPSCR pack and unpack support\n#\n@define FPSCR_RM_SHIFT \" 0\"\n@define FPSCR_FLAG_SHIFT \" 2\"\n@define FPSCR_ENABLE_SHIFT \" 7\"\n@define FPSCR_CAUSE_SHIFT \"12\"\n@define FPSCR_DN_SHIFT \"18\"\n@define FPSCR_PR_SHIFT \"19\"\n@define FPSCR_SZ_SHIFT \"20\"\n@define FPSCR_FR_SHIFT \"21\"\n\n\n# 0000 0000 0000 0000 0000 0000 0000 0011\n@define FPSCR_RM_MASK \"0x00000003\"\n\n# 0000 0000 0000 0000 0000 0000 0111 1100\n@define FPSCR_FLAG_MASK \"0x0000007C\"\n\n# 0000 0000 0000 0000 0000 1111 1000 0000\n@define FPSCR_ENABLE_MASK \"0x00000F80\"\n\n# 0000 0000 0000 0011 1111 0000 0000 0000\n@define FPSCR_CAUSE_MASK \"0x0003F000\"\n\n# 0000 0000 0000 0100 0000 0000 0000 0000\n@define FPSCR_DN_MASK \"0x00040000\"\n\n# 0000 0000 0000 1000 0000 0000 0000 0000\n@define FPSCR_PR_MASK \"0x00080000\"\n\n# 0000 0000 0001 0000 0000 0000 0000 0000\n@define FPSCR_SZ_MASK \"0x00100000\"\n\n# 0000 0000 0010 0000 0000 0000 0000 0000\n@define FPSCR_FR_MASK \"0x00200000\"\n\n# Bits 22-31 are not used\n\nmacro genFPSCRregister() {\n\n\tFPSCR = \t\n (zext(FPSCR_RM) << $(FPSCR_RM_SHIFT)) |\n (zext(FPSCR_FLAG) << $(FPSCR_FLAG_SHIFT)) |\n (zext(FPSCR_ENABLE) << $(FPSCR_ENABLE_SHIFT)) |\n (zext(FPSCR_CAUSE) << $(FPSCR_CAUSE_SHIFT)) |\n (zext(FPSCR_DN) << $(FPSCR_DN_SHIFT)) |\n (zext(FPSCR_PR) << $(FPSCR_PR_SHIFT)) |\n (zext(FPSCR_SZ) << $(FPSCR_SZ_SHIFT)) |\n (zext(FPSCR_FR) << $(FPSCR_FR_SHIFT));\n}\n\nmacro splitFPSCRregister() {\n\n\tsplitTemp:4 = (FPSCR & $(FPSCR_RM_MASK)) >> $(FPSCR_RM_SHIFT);\n\tFPSCR_RM = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_FLAG_MASK)) >> $(FPSCR_FLAG_SHIFT);\n\tFPSCR_FLAG = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_ENABLE_MASK)) >> $(FPSCR_ENABLE_SHIFT);\n\tFPSCR_ENABLE = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_CAUSE_MASK)) >> $(FPSCR_CAUSE_SHIFT);\n\tFPSCR_CAUSE = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_DN_MASK)) >> $(FPSCR_DN_SHIFT);\n\tFPSCR_DN = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_PR_MASK)) >> $(FPSCR_PR_SHIFT);\n\tFPSCR_PR = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_SZ_MASK)) >> $(FPSCR_SZ_SHIFT);\n\tFPSCR_SZ = splitTemp:1;\n\n\tsplitTemp = (FPSCR & $(FPSCR_FR_MASK)) >> $(FPSCR_FR_SHIFT);\n\tFPSCR_FR = splitTemp:1;\n}\n\n# Fields =================================================================================\ndefine token instr(16)\n\tOP_0 = (12,15)\n\tOP_1 = ( 0, 3)\n\tOP_2 = ( 8,15)\n\tOP_3 = ( 0,15)\n\tOP_4 = ( 0, 7)\n\tOP_5 = ( 0, 8)\n\tOP_6 = ( 8, 8)\n\tOP_7 = ( 0, 4)\n\tOP_8 = ( 0, 9)\n\tOP_9 = ( 7, 7)\n\tOP_10 = ( 4, 4)\n\n\tBANK = ( 4, 6) # bank register id\n\tM_0 = ( 4, 7) # register id\n\tM_1 = ( 5, 7) # register id\n\tM_2 = ( 8, 9) # register id\n\tFRM_0 = ( 4, 7) # float register id\n\tDRM_1 = ( 5, 7) # double register id\n\tXDM_1 = ( 5, 7) # double register id\n\tXDRM = ( 4, 7) # double register id\n\tFVM_2 = ( 8, 9) # fv register id\n\tN_0 = ( 8,11) # register id\n\tN_1 = ( 9,11) # register id\n\tN_2 = (10,11) # register id\n\tFRN_0 = ( 8,11) # float register id\n\tFRN_1 = ( 9,11) # float register id\n\tFRN_2 = ( 9,11) # float register id\n\tDRN_0 = ( 9,11) # double register id\n\tDRN_1 = ( 9,11) # double register id\n\tXDN_1 = ( 9,11) # double register id\n\tXDRN = ( 8,11) # float register id\n\tFVN_2 = (10,11) # fv register id\n\tI_0 = ( 0, 7) signed # immediate\n\tI_1 = ( 0,11) signed # immediate\n\tI_2 = ( 0, 3) signed # immediate\n\tU_0 = ( 0, 7) # immediate\n\tU_1 = ( 0,11) # immediate\n\tU_2 = ( 0, 3) # immediate\n;\n\n# Context variables ====================================================\n# Attach variables =====================================================\n# attach normal registers \nattach variables [ N_0 M_0 ] [\n r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15\n];\n\n# attach float registers \nattach variables [ FRN_0 FRM_0] [\n fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15\n];\n\nattach variables [ FRN_1 ] [\n fr0 fr2 fr4 fr6 fr8 fr10 fr12 fr14\n];\n\nattach variables [ FRN_2 ] [\n fr1 fr3 fr5 fr7 fr9 fr11 fr13 fr15\n];\n\n# attach double registers\nattach variables [ DRN_1 DRM_1 ] [\n dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14\n];\n\n# attach double registers\nattach variables [ DRN_0 ] [\n dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14\n];\n\n# attach extended double registers\nattach variables [ XDN_1 XDM_1 ] [\n xd0 xd2 xd4 xd6 xd8 xd10 xd12 xd14\n];\n\nattach variables [ XDRN XDRM ] [\n dr0 xd0 dr2 xd2 dr4 xd4 dr6 xd6 dr8 xd8 dr10 xd10 dr12 xd12 dr14 xd14\n];\n\n# attach vf registers\nattach variables [ FVN_2 FVM_2 ] [\n fv0 fv4 fv8 fv12\n];\n\nattach variables [ BANK ] [\n R0_BANK R1_BANK R2_BANK R3_BANK R4_BANK R5_BANK R6_BANK R7_BANK\n];\n\n# Tables ================================================================\n# Addressing Modes\n#\n# Register direct\n# Rn\t\t\tEA is Rn.\n# \n# Register indirect\n# @Rn\t\t\tRn contains EA\n# \n# Register indirect with postincrement\n# @Rn+\t\t\tRn contains EA\n# After EA calculation:\n#\t\t\t\tincrement Rn by 1 for byte, 2 for word, 4 for long word, 8 quadword operand\n# \n# Register indirect with predecrement\n# @-Rn\t\t\tRn contains EA,\n# Before EA calculation:\n#\t\t\t\tincrement Rn by 1 for byte, 2 for word, 4 for long word, 8 quadword operand\n# \n# Register indirect with displacement\n# @(disp:4, Rn)\tEA is Rn + 4-bit displacement disp added. disp is zero extended,\n# then multiplied by 1 for byte, 2 for word, 4 for long word operand size\n# \n# Indexed register indirect\n# @(R0, Rn)\t\tEA is Rn + R0\n# \n# GBR indirect with displacement\n# @(disp:8,GBR)\tEA is GBR contents with 8-bit displacement added.\n#\t\t\t\t8-bit displacement disp added. disp is zero extended,\n# then multiplied by 1 for byte, 2 for word, 4 for long word operand size\n# \n# Indexed GBR indirect\n# @(R0, GBR)\tEA is GBR + R0\n# \n# PC-relative with displacement\n# @(disp:8, PC)\tEA is PC+4 + 8bit displacement. disp is zero extended,\n# then multiplied by 1 for byte, 2 for word, 4 for long word operand size\n# \n# PC-relative\n# disp:8\t\tEA is PC+4 + 8-bit displacement.\n#\t\t\t\tdisp is sign-extended and multiplied by 2.\n# \n# PC-relative\n# disp:12\t\tEA is PC+4 + 12-bit displacement.\n#\t\t\t\tdisp is sign-extended and multiplied by 2.\n# \n# Rn\t\t\tEA is PC+4 + Rn.\n# \nM_0t: M_0 is M_0 { export M_0; }\n\nN_0t: N_0 is N_0 { export N_0; }\n\nN_0tjmp: @^N_0 is N_0 { export N_0; }\n\nI_0t: \"#\"^I_0 is I_0 { tmp:4 = I_0; export tmp; }\n\nU_0t: \"#\"^U_0 is U_0 { tmp:4 = U_0; export tmp; }\nU_0t1: \"#\"^U_0^\",@(\"^r0^\",\"^GBR^\")\" is U_0 & r0 & GBR { tmp:1 = U_0; export tmp; }\n\nI_0t_r0: \"#\"I_0^\",\"^r0 is I_0 & r0 { tmp:4 = I_0; export tmp; }\n\nU_0t_r0: \"#\"U_0^\",\"^r0 is U_0 & r0 { tmp:4 = U_0; export tmp; }\n\nI_0tbranch: dest is I_0 [ dest = inst_start + I_0*2 + 4; ] { export *:4 dest; }\n\nI_1tbranch: dest is I_1 [ dest = inst_start + I_1*2 + 4; ] { export *:4 dest; }\n\nsr_N_0t: SR^\",\"^N_0 is N_0 & SR { export N_0; }\n\ngbr_N_0t: GBR^\",\"^N_0 is N_0 & GBR { export N_0; }\n\nvbr_N_0t: VBR^\",\"^N_0 is N_0 & VBR { export N_0; }\n\nssr_N_0t: SSR^\",\"^N_0 is N_0 & SSR { export N_0; }\n\nspc_N_0t: SPC^\",\"^N_0 is N_0 & SPC { export N_0; }\n\nsgr_N_0t: SGR^\",\"^N_0 is N_0 & SGR { export N_0; }\n\ndbr_N_0t: DBR^\",\"^N_0 is N_0 & DBR { export N_0; }\n\nsr_t: SR is OP_0 & SR { x:4 = 0; export x; } # dummy export, just looking for the display\n\ngbr_t: GBR is OP_0 & GBR { x:4 = 0; export x; } # dummy export, just looking for the display\n\nvbr_t: VBR is OP_0 & VBR { x:4 = 0; export x; } # dummy export, just looking for the display\n\nssr_t: SSR is OP_0 & SSR { x:4 = 0; export x; } # dummy export, just looking for the display\n\nspc_t: SPC is OP_0 & SPC { x:4 = 0; export x; } # dummy export, just looking for the display\n\nsgr_t: SGR is OP_0 & SGR { x:4 = 0; export x; } # dummy export, just looking for the display\n\ndbr_t: DBR is OP_0 & DBR { x:4 = 0; export x; } # dummy export, just looking for the display\n\nN_0t_sr: N_0^\",\"^SR is N_0 & SR { export N_0; }\n\nN_0t_gbr: N_0^\",\"^GBR is N_0 & GBR { export N_0; }\n\nN_0t_vbr: N_0^\",\"^VBR is N_0 & VBR { export N_0; }\n\nN_0t_ssr: N_0^\",\"^SSR is N_0 & SSR { export N_0; }\n\nN_0t_spc: N_0^\",\"^SPC is N_0 & SPC { export N_0; }\n\n# N_0t_sgr: N_0^\",\"^SGR is N_0 & SGR { export N_0; }\nN_0t_dbr: N_0^\",\"^DBR is N_0 & DBR { export N_0; }\n\nN_0t_bank: N_0 is N_0 { export N_0; }\n\nN_0t_sr1: @^N_0^\"+,\"^SR is N_0 & SR { export N_0; }\n\nN_0t_gbr1: @^N_0^\"+,\"^GBR is N_0 & GBR { export N_0; }\n\nN_0t_vbr1: @^N_0^\"+,\"^VBR is N_0 & VBR { export N_0; }\n\nN_0t_ssr1: @^N_0^\"+,\"^SSR is N_0 & SSR { export N_0; }\n\nN_0t_spc1: @^N_0^\"+,\"^SPC is N_0 & SPC { export N_0; }\n\n# N_0t_sgr1: @^N_0^\"+,\"^SGR is N_0 & SGR { export N_0;}\nN_0t_dbr1: @^N_0^\"+,\"^DBR is N_0 & DBR { export N_0; }\n\nN_0t_bank1: @^N_0^\"+\" is N_0 { export N_0; }\n\nFR0_t: fr0 is OP_0 & fr0 { export fr0; }\n\nXMTRX_t: \"xmtrx\" is OP_0 { x:4 = 0; export x; } # dummy export, just looking for the display\n\nmach_t: MACH is OP_0 & MACH { export MACH; }\n\nmacl_t: MACL is OP_0 & MACL { export MACL; }\n\nfpul_t: FPUL is OP_0 & FPUL { export FPUL; }\n\nfpscr_t: \"FPSCR\" is OP_0 { x:4 = 0; export x; } # dummy export, just looking for the display\n\nmach_N_0t: MACH^\",\"^N_0 is N_0 & MACH { export N_0; }\n\nmacl_N_0t: MACL^\",\"^N_0 is N_0 & MACL { export N_0; }\n\npr_N_0t: PR^\",\"^N_0 is N_0 & PR { export N_0; }\n\nfpul_N_0t: FPUL^\",\"N_0 is N_0 & FPUL { export N_0; }\n\nfpscr_N_0t: \"FPSCR\"^\",\"N_0 is N_0 { export N_0; }\n\nN_0t_mach: N_0^\",\"^MACH is N_0 & MACH { export N_0; }\n\nN_0t_macl: N_0^\",\"^MACL is N_0 & MACL { export N_0; }\n\nN_0t_pr: N_0^\",\"^PR is N_0 & PR { export N_0; }\n\nN_0t_fpul: N_0^\",\"^FPUL is N_0 & FPUL { export N_0; }\n\nN_0t_fpscr: N_0^\",fpscr\" is N_0 { export N_0; }\n\nN_0t_mach1: @^N_0^\"+,\"^MACH is N_0 & MACH { export N_0; }\n\nN_0t_macl1: @^N_0^\"+,\"^MACL is N_0 & MACL { export N_0; }\n\nN_0t_pr1: @^N_0^\"+,\"^PR is N_0 & PR { export N_0; }\n\nN_0t_fpul1: @^N_0^\"+,\"^FPUL is N_0 & FPUL { export N_0; }\n\nN_0t_fpscr1: @^N_0^\"+,fpscr\" is N_0 { export N_0; }\n\nM_0t_at1: @^M_0 is M_0 { export M_0; }\n\nN_0t_at1: @^N_0 is N_0 { export N_0; }\n\nM_0t_at: @^M_0^+ is M_0 { export M_0; }\n\nN_0t_at: @^N_0^+ is N_0 { export N_0; }\n\nFRM_0t: FRM_0 is FRM_0 { export FRM_0; }\n\nFRN_0t: FRN_0 is FRN_0 { export FRN_0; }\n\nDRM_1t: DRM_1 is DRM_1 { export DRM_1; }\n\nDRN_1t: DRN_1 is DRN_1 { export DRN_1; }\n\nFVM_2t: FVM_2 is FVM_2 { export FVM_2; }\n\nFVN_2t: FVN_2 is FVN_2 { export FVN_2; }\n\nN_0t_at_with_r0: \"@(\"^r0^\",\"^N_0^\")\" is N_0 & r0 { export N_0; }\n\nM_0t_at_with_r0: \"@(\"^r0^\",\"^M_0^\")\" is M_0 & r0 { export M_0; }\n\nN_0t_at_neg: \"@-\"^N_0 is N_0 { export N_0; }\n\nU_2t_M0_dispr01: \"@(\"^disp^\",\"^M_0^\")\" is U_2 & M_0 [ disp = U_2 * 1; ] { tmp4:4 = disp; export tmp4; }\nU_2t_M0_dispr02: \"@(\"^disp^\",\"^M_0^\")\" is U_2 & M_0 [ disp = U_2 * 2; ] { tmp4:4 = disp; export tmp4; }\nU_2t_M0_dispr04: \"@(\"^disp^\",\"^M_0^\")\" is U_2 & M_0 [ disp = U_2 * 4; ] { tmp4:4 = disp; export tmp4; }\n\nU_2t_N0_dispr04: \"@(\"^disp^\",\"^N_0^\")\" is U_2 & N_0 [ disp = U_2 * 4; ] { tmp4:4 = disp; export tmp4; }\n\n# Bug in SLEIGH, needed \"* 1\"\nU_0t_gbr_at_1: \"@(\"^disp,GBR^\")\" is U_0 & GBR [ disp = U_0 * 1; ] { tmp4:4 = disp + GBR; export tmp4; }\nU_0t_gbr_at_2: \"@(\"^disp,GBR^\")\" is U_0 & GBR [ disp = U_0 * 2; ] { tmp4:4 = disp + GBR; export tmp4; }\nU_0t_gbr_at_4: \"@(\"^disp,GBR^\")\" is U_0 & GBR [ disp = U_0 * 4; ] { tmp4:4 = disp + GBR; export tmp4; }\n\n# Note: The 4 byte (MOVA) case needs the masking of the PC bottom 2 bits, page 345, paragraph 1:\n# \"a value with the lower 2 bits adjusted to B00 is used in address calculation.\"\n# Note: Only the 4 byte case needs the masking of the PC bottom 2 bits, page 336, paragraph 3:\n# \"A value with the lower 2 bits adjusted to B00 is used in address calculation.\"\n# (The 2 byte case always has the PC LSBit at 0 because all instructions are 2 byte aligned.)\nU_0t_2pc: dest is U_0 [ dest = inst_start + U_0*2 + 4; ] { export *:2 dest; }\n\nU_0t_4pc: dest is U_0 [ dest = ( inst_start & 0xfffffffc ) + U_0*4 + 4; ] { export *:4 dest; }\n\nBANKt: BANK is BANK { export BANK; }\n\nN_0txx: r0\",@\"^N_0 is r0 & N_0 { tmp:4 = N_0; export tmp; }\n\n# Constructors =======================================================================\n# Binary Addition\n# pattern 0011nnnnmmmm1100\n# text add ,\n# arch arch_sh_up\n:add M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xc {\n\n\tN_0t = N_0t + M_0t;\n}\n\n\n# Binary Addition\n# pattern 0111nnnniiiiiiii\n# text add #,\n# arch arch_sh_up\n:add I_0t,N_0t is OP_0=0x7 & N_0t & I_0t {\n\n\tN_0t = I_0t + N_0t; # NOTE I_0t already signed extended\n}\n\n\n# Binary Addition with Carry\n# pattern 0011nnnnmmmm1110\n# text addc ,\n# arch arch_sh_up\n:addc M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xe {\n\tlocal Tcopy:4 = zext($(T_FLAG));\n\t$(T_FLAG) = carry( N_0t, M_0t );\n\tlocal result:4 = N_0t + M_0t;\n\t$(T_FLAG) = $(T_FLAG) || carry( result, Tcopy );\n\tN_0t = result + Tcopy;\t\n}\n\n\n# Binary Addition with Overflow Check\n# pattern 0011nnnnmmmm1111\n# text addv ,\n# arch arch_sh_up\n:addv M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xf {\n\n\t$(T_FLAG) = scarry(N_0t,M_0t);\n\tN_0t = N_0t + M_0t;\n}\n\n\n# Logical AND\n# pattern 0010nnnnmmmm1001\n# text and ,\n# arch arch_sh_up\n:and M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0x9 {\n\n\tN_0t = N_0t & M_0t;\n}\n\n# Logical AND\n# pattern 11001001iiiiiiii\n# text and #,R0\n# arch arch_sh_up\n:and U_0t_r0 is OP_2=0xc9 & U_0t_r0 {\n\n\tr0 = r0 & U_0t_r0;\n}\n\n# Logical AND\n# pattern 11001101iiiiiiii\n# text and.b #,@(R0,GBR)\n# arch arch_sh_up\n:and.b U_0t1 is OP_2=0xcd & U_0t1 {\n\n\t*:1 (GBR + r0) = (*:1 (GBR + r0)) & U_0t1;\n}\n\n\n# Conditional Branch\n# pattern 10001011iiiiiiii\n# text bf \n# arch arch_sh_up\n:bf I_0tbranch is OP_2=0x8b & I_0tbranch {\n\n\tif ( $(T_FLAG) == 0 ) goto I_0tbranch;\n}\n\n\n# Conditional Branch with Delay\n# pattern 10001111iiiiiiii\n# text bf/s \n# arch arch_sh2_up\n:bf^\"/s\" I_0tbranch is OP_2=0x8f & I_0tbranch {\n\n\tlocal cond = $(T_FLAG);\n\tdelayslot(1);\n\tif ( cond == 0 ) goto I_0tbranch;\n} \n\n\n# Unconditional Branch\n# pattern 1010iiiiiiiiiiii\n# text bra \n# arch arch_sh_up\n:bra I_1tbranch is OP_0=0xa & I_1tbranch {\n\n\tdelayslot(1);\n\tgoto I_1tbranch;\n}\n\n\n# Unconditional Branch\n# pattern 0000nnnn00100011\n# text braf \n# arch arch_sh2_up\n:braf N_0 is OP_0=0x0 & N_0 & OP_4=0x23 {\n\n\tlocal dest = N_0 + inst_next;\n\tdelayslot(1);\n\tgoto [dest];\n}\n\n\n# Branch to Subroutine Procedure\n# pattern 1011iiiiiiiiiiii\n# text bsr \n# arch arch_sh_up\n:bsr I_1tbranch is OP_0=0xb & I_1tbranch {\n\n\tdelayslot(1);\n\tcall I_1tbranch;\n}\n\n\n# Branch to Subroutine Procedure\n# pattern 0000nnnn00000011\n# text bsrf \n# arch arch_sh2_up\n:bsrf N_0 is OP_0=0x0 & N_0 & OP_4=0x3 {\n\n\tPR = inst_next;\n\tlocal dest = N_0 + inst_next;\n\tdelayslot(1);\n\tcall [dest];\n}\n\n\n# Conditional Branch\n# pattern 10001001iiiiiiii\n# text bt \n# arch arch_sh_up\n:bt I_0tbranch is OP_2=0x89 & I_0tbranch {\n\n\tif ( $(T_FLAG) == 1 ) goto I_0tbranch;\n}\n\n\n# Conditional Branch with Delay\n# pattern 10001101iiiiiiii\n# text bt/s \n# arch arch_sh2_up\n:bt^\"/s\" I_0tbranch is OP_2=0x8d & I_0tbranch {\n\tlocal cond = $(T_FLAG);\n\tdelayslot(1);\n\tif ( cond == 1 ) goto I_0tbranch;\n}\n\n\n# MAC Register Clear\n# pattern 0000000000101000\n# text clrmac\n# arch arch_sh_up\n:clrmac is OP_3=0x28 {\n\n\tMACH = 0;\n\tMACL = 0;\n}\n\n\n# S Bit Clear\n# pattern 0000000001001000\n# text clrs\n# arch arch_sh_up\n:clrs is OP_3=0x48 {\n\n\t$(S_FLAG) = 0;\n}\n\n\n# T Bit Clear\n# pattern 0000000000001000\n# text clrt\n# arch arch_sh_up\n:clrt is OP_3=0x8 {\n\n\t$(T_FLAG) = 0;\n}\n\n\n# Compare\n# pattern 0011nnnnmmmm0000\n# text cmp/eq ,\n# arch arch_sh_up\n:cmp^\"/eq\" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x0 {\n\n\t$(T_FLAG) = ( N_0t == M_0t );\n} \n\n\n# Compare\n# pattern 0011nnnnmmmm0011\n# text cmp/ge ,\n# arch arch_sh_up\n:cmp^\"/ge\" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x3 {\n\n\t$(T_FLAG) = ( N_0t s>= M_0t );\n}\n\n# Compare\n# pattern 0011nnnnmmmm0111\n# text cmp/gt ,\n# arch arch_sh_up\n:cmp^\"/gt\" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x7 {\n\n\t$(T_FLAG) = ( N_0t s> M_0t);\n} \n\n\n# Compare\n# pattern 0011nnnnmmmm0110\n# text cmp/hi ,\n# arch arch_sh_up\n:cmp^\"/hi\" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x6 {\n\n\t$(T_FLAG) = ( N_0t > M_0t );\n}\n\n\n# Compare\n# pattern 0011nnnnmmmm0010\n# text cmp/hs ,\n# arch arch_sh_up\n:cmp^\"/hs\" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x2 {\n\n\t$(T_FLAG) = ( N_0t >= M_0t );\n}\n\n\n# Compare\n# pattern 0100nnnn00010101\n# text cmp/pl \n# arch arch_sh_up\n:cmp^\"/pl\" N_0t is OP_0=0x4 & N_0t & OP_4=0x15 {\n\n\t$(T_FLAG) = ( N_0t s> 0 );\n}\n\n# Compare\n# pattern 0100nnnn00010001\n# text cmp/pz \n# arch arch_sh_up\n:cmp^\"/pz\" N_0t is OP_0=0x4 & N_0t & OP_4=0x11 {\n\n\t$(T_FLAG) = ( N_0t s>= 0 );\n}\n\n\n# Compare\n# pattern 0010nnnnmmmm1100\n# text cmp/str ,\n# arch arch_sh_up\n:cmp^\"/str\" M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xc {\n\n\ttemp:4 = M_0t ^ N_0t;\n\tHH:4 = (temp & 0xFF000000) >> 24;\n\tHL:4 = (temp & 0x00FF0000) >> 16;\n\tLH:4 = (temp & 0x0000FF00) >> 8;\n\tLL:4 = temp & 0x000000FF;\n\t$(T_FLAG) = (HH == 0) || (HL == 0 ) || (LH == 0) || (LL == 0);\n}\n\n\n# Compare\n# pattern 10001111iiiiiiii\n# pattern 10001000iiiiiiii\n# text cmp/eq #,R0\n# arch arch_sh_up\n:cmp^\"/eq\" I_0t_r0 is OP_2=0x88 & I_0t_r0 {\n\n\t$(T_FLAG) = ( r0 == I_0t_r0 );\n}\n\n\n# Initialization for Signed Division\n# pattern 0010nnnnmmmm0111\n# text div0s ,\n# arch arch_sh_up\n:div0s M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0x7 {\n\n\t$(Q_FLAG) = ( (N_0t & 0x80000000) != 0 );\n\t$(M_FLAG) = ( (M_0t & 0x80000000) != 0 );\n\t$(T_FLAG) = ( $(M_FLAG) != $(Q_FLAG) );\n}\n\n\n# Initialization for Unsigned Division\n# pattern 0000000000011001\n# text div0u\n# arch arch_sh_up\n:div0u is OP_3=0x19 {\n\n\t$(M_FLAG) = 0;\n\t$(Q_FLAG) = 0;\n\t$(T_FLAG) = 0;\n}\n\n\n# Division\n# pattern 0011nnnnmmmm0100\n# text div1 ,\n# arch arch_sh_up\n:div1 M_0t,N_0t is OP_0=0x3 & OP_1=0x4 & M_0t & N_0t {\n\n#@ifdef DIV1_ORIGINAL_IS_BROKEN\n#\ttmp2:4 = M_0t;\n#\tN_0t = N_0t << 1;\n#\tN_0t = N_0t | zext($(T_FLAG)); # ???\n# tmp0:4 = N_0t;\n#\tN_0t = N_0t - zext((($(Q_FLAG)+$(M_FLAG))!=1))*tmp2 + zext(($(Q_FLAG)+$(M_FLAG))==1)*tmp2;\n#\ttmp1:1 = ( (($(Q_FLAG)+$(M_FLAG))!=1)*(N_0t > tmp0) + (($(Q_FLAG)+$(M_FLAG))==1)*(N_0t < tmp0));\n#\t$(Q_FLAG) = ((0x80000000 & N_0t)!=0);\n#\tQ1:1 = tmp1*($(Q_FLAG)!=0) + (tmp1==0)*($(Q_FLAG)==0);\n#\tQ2:1 = tmp1*($(Q_FLAG)==0) + (tmp1==0)*($(Q_FLAG)!=0);\n#\t$(Q_FLAG) = (($(M_FLAG)==1)*Q1 + ($(M_FLAG)!=1)*Q2);\n#\t$(T_FLAG) = ($(Q_FLAG)==$(M_FLAG));\n#@endif # DIV1_ORIGINAL_IS_BROKEN\n# DIV1_WITH_FORWARD_BRANCHES_WORKS_OK\n\tlocal Rm:4 = M_0t;\n\tlocal Rn:4 = N_0t;\n\tlocal old_Q:1 = $(Q_FLAG);\n\t$(Q_FLAG) = ((0x80000000 & Rn)!=0);\n\tlocal tmp2:4 = Rm;\n\tRn = Rn << 1;\n\tRn = Rn | zext($(T_FLAG));\n\tlocal tmp0:4 = Rn;\n\tlocal tmp1:1 = 0;\n\n\tif (old_Q == 0) && ($(M_FLAG) == 0) goto ;\n\tif (old_Q == 0) && ($(M_FLAG) == 1) goto ;\n\tif (old_Q == 1) && ($(M_FLAG) == 0) goto ;\n# if (old_Q == 1) && ($(M_FLAG) == 1) ...\n\tRn = Rn - tmp2;\n\ttmp1 = Rn > tmp0;\n\tif ($(Q_FLAG) == 0) goto ;\n# ($(Q_FLAG) == 1)\n\t$(Q_FLAG) = tmp1;\n\tgoto ;\n\n\t$(Q_FLAG) = tmp1 == 0;\n\tgoto ;\n\n # (old_Q == 1) && ($(M_FLAG) == 0)\n\tRn = Rn + tmp2;\n\ttmp1 = Rn < tmp0;\n\tif ($(Q_FLAG) == 0) goto ;\n# ($(Q_FLAG) == 1)\n\t$(Q_FLAG) = tmp1 == 0;\n\tgoto ;\n\n\t$(Q_FLAG) = tmp1;\n\tgoto ;\n\n # (old_Q == 0) && ($(M_FLAG) == 1)\n\tRn = Rn + tmp2;\n\ttmp1 = Rn < tmp0;\n\tif ($(Q_FLAG) == 0) goto ;\n# ($(Q_FLAG) == 1)\n\t$(Q_FLAG) = tmp1;\n\tgoto ;\n\n\t$(Q_FLAG) = tmp1 == 0;\n\tgoto ;\n\n # (old_Q == 0) && ($(M_FLAG) == 0)\n\tRn = Rn - tmp2;\n\ttmp1 = Rn > tmp0;\n\tif ($(Q_FLAG) == 0) goto ;\n# ($(Q_FLAG) == 1)\n\t$(Q_FLAG) = tmp1 == 0;\n\tgoto ;\n\n\t$(Q_FLAG) = tmp1;\n\n\n\t$(T_FLAG) = $(Q_FLAG) == $(M_FLAG);\n\tN_0t = Rn;\n\n# DIV1_WITH_GOTOs_WORKS_OK\n\n# TODO: the following is currently broken, it should be fixed to eliminate gotos in the code above\n\n#@ifdef DIV1_STRAIGHT_CODE # BROKEN\n#\tRm:4 = M_0t;\n#\tRn:4 = N_0t;\n#\told_Q:1 = $(Q_FLAG);\n#\t$(Q_FLAG) = ((0x80000000 & Rn)!=0);\n#\ttmp2:4 = Rm;\n#\tRn = Rn << 1;\n#\tRn = Rn | zext($(T_FLAG));\n#\ttmp0:4 = Rn;\n#\n#\toldQM_10_01_bool:1 = ( ( (old_Q == 1) && ($(M_FLAG) == 0) ) || ( (old_Q == 1) && ($(M_FLAG) == 0) ) );\n#\toldQM_10_01:4 = zext(oldQM_10_01_bool) * 0xffffffff;\n#\n#\toldQM_11_00_bool:1 = ( (old_Q == 1) && ($(M_FLAG) == 1) ) || ( (old_Q == 0) && ($(M_FLAG) == 0) );\n#\toldQM_11_00:4 = zext(oldQM_11_00_bool) * 0xffffffff;\n\n#\tRn = (oldQM_10_01 & (Rn + tmp2)) | (oldQM_11_00 & (Rn - tmp2));\n\n#\ttmp1:1 = ( (oldQM_11_00 != 0) && (Rn > tmp0) ) | ( (oldQM_10_01 != 0) && (Rn < tmp0) );\n\n#\tQM_10_01:1 = ( ( ($(Q_FLAG) == 1) && ($(M_FLAG) == 0) ) || ( ($(Q_FLAG) == 1) && ($(M_FLAG) == 0) ) ) * 0xff;\n#\tQM_11_00:1 = ( ( ($(Q_FLAG) == 1) && ($(M_FLAG) == 1) ) || ( ($(Q_FLAG) == 0) && ($(M_FLAG) == 0) ) ) * 0xff;\n\n#\t$(Q_FLAG) = (QM_10_01 & tmp1) || (QM_11_00 & (tmp1 == 0));\n\n#\t$(T_FLAG) = $(Q_FLAG) == $(M_FLAG);\n#\tN_0t = Rn;\n#@endif # DIV1_STRAIGHT_CODE\n}\n\n# Signed Double-Length Multiplication\n# pattern 0011nnnnmmmm1101\n# text dmuls.l ,\n# arch arch_sh2_up\n:dmuls.l M_0t,N_0t is OP_0=0x3 & OP_1=0xd & M_0t & N_0t \n{\n\tlocal temp:8 = sext(M_0t) * sext(N_0t);\n\tMACL = temp[0,32];\n\tMACH = temp[32,32];\n}\n\n# Unsigned Double-Length Multiplication\n# pattern 0011nnnnmmmm0101\n# text dmulu.l ,\n# arch arch_sh2_up\n:dmulu.l M_0t,N_0t is OP_0=0x3 & OP_1=0x5 & M_0t & N_0t {\n\tlocal temp:8 = zext(M_0t) * zext(N_0t);\n\tMACL = temp[0,32];\n\tMACH = temp[32,32];\n}\n\n# Decrement and Test\n# pattern 0100nnnn00010000\n# text dt \n# arch arch_sh2_up\n:dt N_0t is OP_0=0x4 & N_0t & OP_4=0x10 {\n\n\tN_0t = N_0t - 1;\n\t$(T_FLAG) = ( N_0t == 0 );\n}\n\n\n# Sign Extension\n# pattern 0110nnnnmmmm1110\n# text exts.b ,\n# arch arch_sh_up\n:exts.b M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xe {\n\n\tN_0t = sext(M_0t:1);\n}\n\n# Sign Extension\n# pattern 0110nnnnmmmm1111\n# text exts.w ,\n# arch arch_sh_up\n:exts.w M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xf {\n\n\tN_0t = sext(M_0t:2);\n}\n\n\n# Zero Extension\n# pattern 0110nnnnmmmm1100\n# text extu.b ,\n# arch arch_sh_up\n:extu.b M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xc {\n\n\tN_0t = zext(M_0t:1);\n}\n\n\n# Zero Extension\n# pattern 0110nnnnmmmm1101\n# text extu.w ,\n# arch arch_sh_up\n:extu.w M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xd {\n\n\tN_0t = zext(M_0t:2);\n}\n\n\n# Floating-Point Absolute Value\n# pattern 1111nnnn01011101\n# text fabs \n# arch arch_sh2e_up\n:fabs FRN_0 is\n OP_0=0xf & FRN_0 & DRN_1 & OP_4=0x5d {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0 = abs(FRN_0);\n\tgoto ;\n\t\n\tDRN_1 = abs(DRN_1);\n\t\n}\n\n# Floating-Point Addition\n# pattern 1111nnnnmmmm0000\n# text fadd ,\n# arch arch_sh2a_or_sh4_up\n:fadd FRM_0,FRN_0 is\n OP_0=0xf & FRN_0 & DRN_1 & FRM_0 & DRM_1 & OP_1=0x0 {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0 = FRN_0 f+ FRM_0;\n\tgoto ;\n\t\n\tDRN_1 = DRN_1 f+ DRM_1;\n\t\n}\n\n# Floating-Point Comparison\n# pattern 1111nnnnmmmm0100\n# text fcmp/eq ,\n# arch arch_sh2e_up\n:fcmp^\"/eq\" FRM_0t,FRN_0t is\n OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_6 & OP_10 & OP_1=0x4 {\n\tif (!( $(FPSCR_PR) == 0 ) ) && (OP_6:1 == 0) && (OP_10:1 == 0) goto ;\n\t$(T_FLAG) = ( FRN_0t f== FRM_0t );\n\tgoto ;\n\t\n\t$(T_FLAG) = ( DRN_1t f== DRM_1t );\n\t\n}\n\n# Floating-Point Comparison\n# pattern 1111nnnnmmmm0101\n# text fcmp/gt ,\n# arch arch_sh2e_up\n:fcmp^\"/gt\" FRM_0t,FRN_0t is\n OP_0=0xf & FRM_0t & DRM_1t & FRN_0t & DRN_1t & OP_1=0x5 {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\t$(T_FLAG) = ( FRN_0t f> FRM_0t );\n\tgoto ;\n\t\n\t$(T_FLAG) = ( DRN_1t f> DRM_1t );\n\t\n}\n\n\n# Double-Precision to Single-Precision Conversion\n# pattern 1111nnn010111101\n# text fcnvds ,FPUL\n# even though reserved to DblPrec, should decode, may not know at the time.\n# if this instruction shows up, it is most likely in DblPrec mode but not set\n# arch arch_sh2a_or_sh4_up\n:fcnvds DRN_1t,FPUL is OP_0=0xf & DRN_1t & OP_5=0x0bd & FPUL {\n\n\t# note: this instruction is undefined if not running in DblPrec mode.\n\tFPUL = float2float( DRN_1t );\n}\n\n\n# Single-Precision to Double-Precision Conversion\n# pattern 1111nnn010101101\n# text fcnvsd FPUL,\n# even though reserved to DblPrec, should decode, may not know at the time.\n# if this instruction shows up, it is most likely in DblPrec mode but not set\n# arch arch_sh2a_or_sh4_up\n:fcnvsd FPUL,DRN_1t is OP_0=0xf & DRN_1t & OP_5=0xad & FPUL {\n\n\t# note: this instruction is undefined if not running in DblPrec mode.\n\tDRN_1t = float2float( FPUL );\n}\n\n\n# Floating-Point Division\n# pattern 1111nnnnmmmm0011\n# text fdiv ,\n# arch arch_sh2e_up\n:fdiv FRM_0t,FRN_0t is\n OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_1=0x3 {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0t = ( FRN_0t f/ FRM_0t );\n\tgoto ;\n\t\n\tDRN_1t = ( DRN_1t f/ DRM_1t );\n\t\n}\n\n# Floating-Point Inner Product\n# pattern 1111nnmm11101101\n# text fipr ,\n# even though reserved to DblPrec, should decode, may not know at the time.\n# if this instruction shows up, it is most likely in DblPrec mode but not set\n# arch arch_sh4_up\n:fipr FVM_2t,FVN_2t is OP_0=0xf & FVN_2t & FVM_2t & OP_4=0xed {\n\n\t# note: this instruction is undefined if not running in SinglePrec mode.\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\t# FVn dot FVm\n\ttemp1:4 = ( *[register]:4 (&:4 FVN_2t + 0) f* *[register]:4 (&:4 FVM_2t + 0) );\n\ttemp1 = temp1 f+ ( *[register]:4 (&:4 FVN_2t + 4) f* *[register]:4 (&:4 FVM_2t + 4) );\n\ttemp1 = temp1 f+ ( *[register]:4 (&:4 FVN_2t + 8) f* *[register]:4 (&:4 FVM_2t + 8) );\n\ttemp1 = temp1 f+ ( *[register]:4 (&:4 FVN_2t + 12) f* *[register]:4 (&:4 FVM_2t + 12) );\n\n\t# summation goes to FR[n + 3]\n\t*[register]:4 (&:4 FVN_2t + 12) = temp1;\n\t\n}\n\n# 0.0 Load\n# pattern 1111nnnn10001101\n# text fldi0 \n# arch arch_sh2e_up\n#\n# Note- The manual says this applies only to single float destination regs\n#\n:fldi0 FRN_0t is OP_0=0xf & DRN_1t & FRN_0t & OP_4=0x8d {\n\ttmp1:4 = 0;\n\tFRN_0t = int2float(tmp1);\n}\n\n# 1.0 Load\n# pattern 1111nnnn10011101\n# text fldi1 \n# arch arch_sh2e_up\n#\n# Note- the manual says FPSCR_PR applies only to single float regs, not to doubles.\n# Manual also says FPSCR_PR should be 0, but gcc generates code where it's set to 1.\n#\n:fldi1 FRN_0t is OP_0=0xf & FRN_0t & DRN_1t & OP_4=0x9d {\n\ttmp1:4 = 1;\n\tFRN_0t = int2float(tmp1);\n}\n\n# Transfer to System Register\n# pattern 1111nnnn00011101\n# text flds ,FPUL\n# arch # arch_sh2e_up\n# Note: Field usage indicates FR[n], not FR[m].\n:flds FRN_0t,FPUL is OP_0=0xf & FRN_0t & OP_4=0x1d & FPUL {\n\n\tFPUL = FRN_0t;\n}\n\n# Integer to Floating-Point Conversion\n# pattern 1111nnnn00101101\n# text float FPUL,\n# arch # arch_sh2e_up\n:float FPUL,FRN_0t is\n OP_0=0xf & OP_6 & FRN_0t & DRN_1t & OP_4=0x2d & FPUL {\n\t# If bit 6 is set, this is an odd FP register number, so need to do single float operation.\n\t# This is not in the manual but this seems to be the correct behavior.\n\tif (!( $(FPSCR_PR) == 0 ) ) && (OP_6:1 == 0x0) goto ;\n\tFRN_0t = int2float( FPUL );\n\tgoto ;\n\t\n\tDRN_1t = int2float( FPUL );\n\t\n}\n\n# Floating-Point Multiply and Accumulate\n# pattern 1111nnnnmmmm1110\n# text fmac FR0,,\n# arch arch_sh2e_up\n:fmac FR0_t,FRM_0t,FRN_0t is OP_0=0xf & FRN_0t & FRM_0t & OP_1=0xe & FR0_t {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0t = ( FR0_t f* FRM_0t ) f+ FRN_0t;\n\t\n}\n\n# Floating-Point Transfer #1-4\n# pattern 1111nnnnmmmm1100\n# text fmov ,\n# arch arch_sh2e_up\n#\n# Note- The manual says all the fmov insns should only look at the FPSCR_SZ flag\n# to determine if this is a single or double float move. Ie, don't reference FPSCR_PR.\n#\n:fmov FRM_0,FRN_0 is\n OP_0=0xf & FRN_0 & XDRN & FRM_0 & XDRM & OP_1=0xc {\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\tFRN_0 = FRM_0;\n\tgoto ;\n\t\n\tXDRN = XDRM;\n\t\n}\n\n# Floating-Point Transfer #5-6\n# pattern 1111nnn0mmmm1000\n# text fmov @,\n# arch arch_sh2e_up\n:fmov.s M_0t_at1,FRN_0 is\n OP_0=0xf & XDRN & FRN_0 & M_0t_at1 & OP_1=0x8 {\n\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\tFRN_0 = *:4 M_0t_at1;\n\tgoto ;\n\t\n\tXDRN = *:8 M_0t_at1;\n\t\n}\n\n# Floating-Point Transfer #7-8\n# pattern 1111nnnnmmmm1010\n# text fmov ,@\n# arch arch_sh2e_up\n#\n# Note- Manual says to ignore FPSCR_PR but FPSCR_SZ must = 0\n#\n:fmov.s FRM_0,N_0t_at1 is\n\n OP_0=0xf & N_0t_at1 & FRM_0 & XDRM & OP_1=0xa {\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\t*:4 N_0t_at1 = FRM_0;\n\tgoto ;\n\t\n\t*:8 N_0t_at1 = XDRM;\n\t\n}\n\n# Floating-Point Transfer #9-10\n# pattern 1111nnnnmmmm1001\n# text fmov @+,\n# arch arch_sh2e_up\n:fmov.s M_0t_at,FRN_0 is\n OP_0=0xf & XDRN & FRN_0 & M_0t_at & OP_1=0x9 {\n\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\tFRN_0 = *:4 M_0t_at;\n\tM_0t_at = M_0t_at + 4;\n\tgoto ;\n\t\n\tXDRN = *:8 M_0t_at;\n\tM_0t_at = M_0t_at + 8;\n\t\n}\n\n# Floating-Point Transfer #11-12\n# pattern 1111nnnnmmm01011\n# text fmov ,@-\n# arch arch_sh2e_up\n:fmov.s FRM_0,N_0t_at_neg is\n OP_0=0xf & N_0t_at_neg & XDRM & FRM_0 & OP_1=0xb {\n\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 N_0t_at_neg = FRM_0;\n\tgoto ;\n\t\n\tN_0t_at_neg = N_0t_at_neg - 8;\n\t*:8 N_0t_at_neg = XDRM;\n\t\n}\n\n# Floating-Point Transfer #13-14\n# pattern 1111nnnnmmmm0110\n# text fmov @(R0,),\n# arch arch_sh2e_up\n:fmov.s M_0t_at_with_r0,FRN_0 is\n OP_0=0xf & XDRN & FRN_0 & M_0t_at_with_r0 & OP_1=0x6 {\n\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\tFRN_0 = *:4 (r0 + M_0t_at_with_r0);\n\tgoto ;\n\t\n\tXDRN = *:8 (r0 + M_0t_at_with_r0);\n\t\n}\n\n# Floating-Point Transfer #15-16\n# pattern 1111nnnnmmmm0111\n# text fmov @(R0,),\n# arch arch_sh2e_up\n:fmov FRM_0,N_0t_at_with_r0 is\n OP_0=0xf & N_0t_at_with_r0 & XDRM & FRM_0 & OP_1=0x7 {\n\n\tif (!( $(FPSCR_SZ) == 0 )) goto ;\n\t*:4 (r0 + N_0t_at_with_r0) = FRM_0;\n\tgoto ;\n\t\n\t*:8 (r0 + N_0t_at_with_r0) = XDRM;\n\t\n}\n\n# Floating-Point Multiplication\n# pattern 1111nnnnmmmm0010\n# text fmul ,\n# arch arch_sh2e_up\n:fmul FRM_0t,FRN_0t is\n OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_1=0x2 {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0t = FRN_0t f* FRM_0t;\n\tgoto ;\n\t\n\tDRN_1t = DRN_1t f* DRM_1t;\n\t\n}\n\n# Floating-Point Sign Inversion\n# pattern 1111nnnn01001101\n# text fneg \n# arch arch_sh2e_up\n:fneg FRN_0t is\n OP_0=0xf & FRN_0t & DRN_1t & OP_6 & OP_4=0x4d {\n\n\tif (!( $(FPSCR_PR) == 0 )) && (OP_6:1 == 0) goto ;\n\tFRN_0t = f- FRN_0t;\n\tgoto ;\n\t\n\tDRN_1t = f- DRN_1t;\n\t\n}\n\n# FR Bit Inversion\n# pattern 1111101111111101\n# text frchg\n# arch # arch_sh4_up\n:frchg is\n OP_3=0xfbfd {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\t$(FPSCR_FR) = !$(FPSCR_FR);\n\tFPSCR = FPSCR ^ 0x00200000;\n\t\n}\n\n\n# SZ Bit Inversion\n# pattern 1111001111111101\n# text fschg\n# arch arch_sh2a_or_sh4a_up (not in sh4)\n:fschg is \n OP_3=0xf3fd {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFPSCR = FPSCR ^ 0x00100000;\n\t\n}\n\n# PR Bit Inversion\n# pattern 1111011111111101\n# text fpchg\n# arch arch_sh2a_or_sh4_up\n:fpchg is\n OP_3=0xf7fd {\n\tFPSCR = FPSCR ^ 0x00080000;\n}\n\n# Floating-Point Square Root\n# pattern 1111nnnn01101101\n# text fsqrt \n# arch # arch_sh2a_or_sh3e_up\n:fsqrt FRN_0t is\n OP_0=0xf & FRN_0t & DRN_1t & OP_4=0x6d {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0t = sqrt( FRN_0t );\n\tgoto ;\n\t\n\tDRN_1t = sqrt( DRN_1t );\n\t\n}\n\n# Floating Point Square Reciprocal Approximate\n# pattern 1111nnnn01111101\t\t\t\n# text\t fsrra \n# arch # arch_sh2a_or_sh3e_up\n:fsrra FRN_0\tis\n\tOP_0=0xF & FRN_0 & OP_4=0x7D {\n\tif (( $(FPSCR_PR) != 0 )) goto inst_next; \n\tFRN_0 = int2float(1 :4) f/ sqrt( FRN_0 );\n}\n\ndefine pcodeop sin;\ndefine pcodeop cos;\n\n# Floating Point Sine And Cosine Approximate\n# pattern 1111nnn011111101\n# text\t fsca FPUL,\n# arch # arch_sh2a_or_sh3e_up\n:fsca FPUL,DRN_0 is\n\tOP_0=0xF & FPUL & DRN_0 & FRN_1 & FRN_2 & OP_4=0xFD {\n\tif (( $(FPSCR_PR) != 0 )) goto inst_next; \n\t\n\tangle:4 = int2float(0 :4); \t\t\t# float\n fraction:4 = 0x0000FFFF;\t\t\t# long\n\t\n\tfraction = fraction & FPUL;\t\t\t# extract sub-rotation\n\tangle \t = int2float(fraction);\t\t\t# convert to float\n\t\n\ttwo_pi:4 = 0x40c90fdb;\t\t\t\t# 6.2831855.. as 32-bit float\n angle = (two_pi f* angle) f/ int2float(65536 :4); # convert to radian\n \n\tlocal _sin:4 = sin(angle);\t\t\t# call fake sin & cos\n\tlocal _cos:4 = cos(angle);\n\t\n\tFRN_1 = float2float(_sin);\t\t\t# _sin goes to FR[n]\n\tFRN_2 = float2float(_cos); \t\t# _cos goes to FR[n+1]\n}\n\n# Transfer from System Register\n# pattern 1111nnnn00001101\n# text fsts FPUL,\n# arch arch_sh2e_up\n:fsts FPUL,FRN_0t is OP_0=0xf & FRN_0t & OP_4=0xd & FPUL {\n\n\tFRN_0t = FPUL;\n}\n\n# Floating-Point Subtraction\n# pattern 1111nnnnmmmm0001\n# text fsub ,\n# arch arch_sh2e_up\n:fsub FRM_0t,FRN_0t is\n OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_1=0x1 {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFRN_0t = FRN_0t f- FRM_0t;\n\tgoto ;\n\t\n\tDRN_1t = DRN_1t f- DRM_1t;\n\t\n}\n\n# Conversion to Integer\n# pattern 1111nnnn00111101\n# text ftrc ,FPUL\n# # arch arch_sh2e_up\n# Note: Field usage indicates FR[n], not FR[m].\n:ftrc FRN_0t,FPUL is\n OP_0=0xf & FRN_0t & DRN_1t & OP_4=0x3d & FPUL {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\tFPUL = trunc( FRN_0t );\n\tgoto ;\n\t\n\tFPUL = trunc( DRN_1t );\n\t\n}\n\n# Vector Transformation\n# pattern 1111nn0111111101\n# text ftrv XMTRX_M4,\n# arch # arch_sh4_up\n:ftrv XMTRX_t,FVN_2t is OP_0=0xf & FVN_2t & OP_8=0x1fd & XMTRX_t {\n\n\tif (!( $(FPSCR_PR) == 0 )) goto ;\n\ttemp1:4 = ( xf0 f* *[register]:4 (&:4 FVN_2t + 0) );\n\ttemp1 = temp1 f+ ( xf4 f* *[register]:4 (&:4 FVN_2t + 4) );\n\ttemp1 = temp1 f+ ( xf8 f* *[register]:4 (&:4 FVN_2t + 8) );\n\ttemp1 = temp1 f+ ( xf12 f* *[register]:4 (&:4 FVN_2t + 12) );\n\n\ttemp2:4 = ( xf1 f* *[register]:4 (&:4 FVN_2t + 0) );\n\ttemp2 = temp2 f+ ( xf5 f* *[register]:4 (&:4 FVN_2t + 4) );\n\ttemp2 = temp2 f+ ( xf9 f* *[register]:4 (&:4 FVN_2t + 8) );\n\ttemp2 = temp2 f+ ( xf13 f* *[register]:4 (&:4 FVN_2t + 12) );\n\n\ttemp3:4 = ( xf2 f* *[register]:4 (&:4 FVN_2t + 0) );\n\ttemp3 = temp3 f+ ( xf6 f* *[register]:4 (&:4 FVN_2t + 4) );\n\ttemp3 = temp3 f+ ( xf10 f* *[register]:4 (&:4 FVN_2t + 8) );\n\ttemp3 = temp3 f+ ( xf14 f* *[register]:4 (&:4 FVN_2t + 12) );\n\n\ttemp4:4 = ( xf3 f* *[register]:4 (&:4 FVN_2t + 0) );\n\ttemp4 = temp4 f+ ( xf7 f* *[register]:4 (&:4 FVN_2t + 4) );\n\ttemp4 = temp4 f+ ( xf11 f* *[register]:4 (&:4 FVN_2t + 8) );\n\ttemp4 = temp4 f+ ( xf15 f* *[register]:4 (&:4 FVN_2t + 12) );\n\n\t# summation goes to FR[n + 0] through FR[n + 3]\n\t*[register]:4 (&:4 FVN_2t + 0) = temp1;\n\t*[register]:4 (&:4 FVN_2t + 4) = temp2;\n\t*[register]:4 (&:4 FVN_2t + 8) = temp3;\n\t*[register]:4 (&:4 FVN_2t + 12) = temp4;\n\t\n}\n\n# Invalidate Instruction Cache block\n# pattern 0000nnnn11100011\n# text icib @\n# arch arch_sh_up\ndefine pcodeop InvalidateCacheBlock;\n\n:icbi N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xe3 {\n\ttmp:4 = N_0t_at1;\n\tInvalidateCacheBlock(tmp);\n}\n\n# Unconditional Branch\n# pattern 0100nnnn00101011\n# text jmp @\n# arch arch_sh_up\n:jmp N_0tjmp is OP_0=0x4 & N_0tjmp & OP_4=0x2b {\n\n\tPC = N_0tjmp;\n\ttmp:4 = PC;\n\tdelayslot(1);\n\tgoto [tmp];\n}\n\n\n# Branch to Subroutine Procedure\n# pattern 0100nnnn00001011\n# text jsr @\n# arch arch_sh_up\n:jsr N_0tjmp is OP_0=0x4 & N_0tjmp & OP_4=0xb {\n\n\tPR = inst_next;\n\tPC = N_0tjmp;\n\ttmp:4 = PC;\n\tdelayslot(1);\n\tcall [tmp];\n}\n\n\n# Load to Control Register\n# pattern 0100nnnn00001110\n# text ldc ,SR\n# arch arch_sh_up\n:ldc N_0t_sr is OP_0=0x4 & N_0t_sr & OP_4=0xe {\n\n\tsplitSRregister();\n\tSR = (N_0t_sr & 0x700083f3);\n}\n\n\n# Load to Control Register\n# pattern 0100nnnn00011110\n# text ldc ,GBR\n# arch arch_sh_up\n:ldc N_0t_gbr is OP_0=0x4 & N_0t_gbr & OP_4=0x1e {\n\n\tGBR = N_0t_gbr;\n}\n\n\n# Load to Control Register\n# pattern 0100nnnn00101110\n# text ldc ,VBR\n# arch arch_sh_up\n:ldc N_0t_vbr is OP_0=0x4 & N_0t_vbr & OP_4=0x2e {\n\n\tVBR = N_0t_vbr;\n}\n\n\n# pattern 0100nnnn00111110\n# text ldc ,SSR\n# arch arch_sh3_nommu_up\n:ldc N_0t_ssr is OP_0=0x4 & N_0t_ssr & OP_4=0x3e {\n\n\tSSR = N_0t_ssr;\n}\n\n\n# pattern 0100nnnn01001110\n# text ldc ,SPC\n# arch arch_sh3_nommu_up\n:ldc N_0t_spc is OP_0=0x4 & N_0t_spc & OP_4=0x4e {\n\n\tSPC = N_0t_spc;\n}\n\n\n# pattern 0100nnnn11111010\n# text ldc ,DBR\n# arch arch_sh4_nommu_nofpu_up\n:ldc N_0t_dbr is OP_0=0x4 & N_0t_dbr & OP_4=0xfa {\n\n\tDBR = N_0t_dbr;\n}\n\n# pattern 0100nnnn1xxx1110\n# text ldc ,Rn_BANK\n# arch arch_sh3_nommu_up\n:ldc N_0t_bank,BANKt is OP_0=0x4 & N_0t_bank & OP_9=0x1 & BANKt & OP_1=0xe {\n\n\tBANKt = N_0t_bank;\n}\n\n\n# Load to Control Register\n# pattern 0100nnnn00000111\n# text ldc.l @+,SR\n# arch arch_sh_up\n:ldc.l N_0t_sr1 is OP_0=0x4 & N_0t_sr1 & OP_4=0x7 {\n\n\tSR = (*:4 ( N_0t_sr1 )) & 0x700083F3;\n\tsplitSRregister();\n\tN_0t_sr1 = N_0t_sr1 + 4;\n}\n\n\n# Load to Control Register\n# pattern 0100nnnn00010111\n# text ldc.l @+,GBR\n# arch arch_sh_up\n:ldc.l N_0t_gbr1 is OP_0=0x4 & N_0t_gbr1 & OP_4=0x17 {\n\n\tGBR = *:4 ( N_0t_gbr1 );\n\tN_0t_gbr1 = N_0t_gbr1 + 4;\n}\n\n\n# Load to Control Register\n# pattern 0100nnnn00100111\n# text ldc.l @+,VBR\n# arch arch_sh_up\n:ldc.l N_0t_vbr1 is OP_0=0x4 & N_0t_vbr1 & OP_4=0x27 {\n\n\tVBR = *:4 ( N_0t_vbr1 );\n\tN_0t_vbr1 = N_0t_vbr1 + 4;\n}\n\n\n# pattern 0100nnnn00110111\n# text ldc.l @+,SSR\n# arch arch_sh3_nommu_up\n:ldc.l N_0t_ssr1 is OP_0=0x4 & N_0t_ssr1 & OP_4=0x37 {\n\n\tSSR = *:4 ( N_0t_ssr1 );\n\tN_0t_ssr1 = N_0t_ssr1 + 4;\n}\n\n\n# pattern 0100nnnn01000111\n# text ldc.l @+,SPC\n# arch arch_sh3_nommu_up\n:ldc.l N_0t_spc1 is OP_0=0x4 & N_0t_spc1 & OP_4=0x47 {\n\n\tSPC = *:4 ( N_0t_spc1 );\n\tN_0t_spc1 = N_0t_spc1 + 4;\n}\n\n\n# pattern 0100nnnn11110110\n# text ldc.l @+,DBR\n# arch arch_sh4_nommu_nofpu_up\n:ldc.l N_0t_dbr1 is OP_0=0x4 & N_0t_dbr1 & OP_4=0xf6 {\n\n\tDBR = *:4 ( N_0t_dbr1 );\n\tN_0t_dbr1 = N_0t_dbr1 + 4;\n}\n\n\n# pattern 0100nnnn1xxx0111\n# text ldc.l @+,Rn_BANK\n# arch arch_sh3_nommu_up\n:ldc.l N_0t_bank1,BANKt is OP_0=0x4 & N_0t_bank1 & OP_9=0x1 & BANKt & OP_1=0x7 {\n\n\tBANKt = *:4 ( N_0t_bank1 );\n\tN_0t_bank1 = N_0t_bank1 + 4;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn01011010\n# text lds ,FPUL\n# arch arch_sh2e_up\n:lds N_0t_fpul is OP_0=0x4 & N_0t_fpul & OP_4=0x5a {\n\n\tFPUL = N_0t_fpul;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn01010110\n# text lds.l @+,FPUL\n# arch arch_sh2e_up\n:lds.l N_0t_fpul1 is OP_0=0x4 & N_0t_fpul1 & OP_4=0x56 {\n\n\tFPUL = *:4 ( N_0t_fpul1 );\n\tN_0t_fpul1 = N_0t_fpul1 + 4;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn01101010\n# text lds ,FPSCR\n# arch arch_sh2e_up\n# Note: FPSCR context cannot be supported from this instruction; contents of N_0 not known at disassembly time.\n:lds N_0t_fpscr is OP_0=0x4 & N_0t_fpscr & OP_4=0x6a {\n\n\tFPSCR = N_0t_fpscr & 0x003FFFFF;\n\tsplitFPSCRregister();\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn01100110\n# text lds.l @+,FPSCR\n# arch arch_sh2e_up\n# Note: FPSCR context cannot be supported from this instruction; contents of N_0 not known at disassembly time.\n:lds.l N_0t_fpscr1 is OP_0=0x4 & N_0t_fpscr1 & OP_4=0x66 {\n\n\tFPSCR = (*:4 ( N_0t_fpscr1 )) & 0x003FFFFF;\n\tsplitFPSCRregister();\n\tN_0t_fpscr1 = N_0t_fpscr1 + 4;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn00001010\n# text lds ,MACH\n# arch arch_sh_up\n:lds N_0t_mach is OP_0=0x4 & N_0t_mach & OP_4=0xa {\n\n\tMACH = N_0t_mach;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn00011010\n# text lds ,MACL\n# arch arch_sh_up\n:lds N_0t_macl is OP_0=0x4 & N_0t_macl & OP_4=0x1a {\n\n\tMACL = N_0t_macl;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn00101010\n# text lds ,PR\n# arch arch_sh_up\n:lds N_0t_pr is OP_0=0x4 & N_0t_pr & OP_4=0x2a {\n\n\tPR = N_0t_pr;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn00000110\n# text lds.l @+,MACH\n# arch arch_sh_up\n:lds.l N_0t_mach1 is OP_0=0x4 & N_0t_mach1 & OP_4=0x6 {\n\n\tMACH = *:4 ( N_0t_mach1 );\n\tN_0t_mach1 = N_0t_mach1 + 4;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn00010110\n# text lds.l @+,MACL\n# arch arch_sh_up\n:lds.l N_0t_macl1 is OP_0=0x4 & N_0t_macl1 & OP_4=0x16 {\n\n\tMACL = *:4 ( N_0t_macl1 );\n\tN_0t_macl1 = N_0t_macl1 + 4;\n}\n\n\n# Load to FPU System Register\n# pattern 0100nnnn00100110\n# text lds.l @+,PR\n# arch arch_sh_up\n:lds.l N_0t_pr1 is OP_0=0x4 & N_0t_pr1 & OP_4=0x26 {\n\n\tPR = *:4 ( N_0t_pr1 );\n\tN_0t_pr1 = N_0t_pr1 + 4;\n}\n\ndefine pcodeop LoadTranslationLookasideBuffer;\n\n# Load to TLB\n# pattern 0000000000111000\n# text ldtlb\n# arch arch_sh3_up\n:ldtlb is OP_3=0x38 { LoadTranslationLookasideBuffer(); }\n\n# Double-Precision Multiply-and-Accumulate Operation\n# pattern 0000nnnnmmmm1111\n# text mac.l @+,@+\n# arch arch_sh2_up\ndefine pcodeop mac_lOp;\n:mac.l M_0t_at,N_0t_at is OP_0=0x0 & OP_1=0xf & M_0t_at & N_0t_at {\n\tlocal tmpM:8 = sext(*:4 M_0t_at);\n\tlocal tmpN:8 = sext(*:4 N_0t_at);\n\tlocal mac:8 = zext(MACL) + (zext(MACH) << 32);\n\tlocal product:8 = tmpM * tmpN;\n\tif ($(S_FLAG) == 0) goto ;\n\tmac = mac_lOp(mac,product);\n\tgoto ;\n\n mac = mac + product;\n\n\tMACL = mac[0,32];\n\tMACH = mac[32,32];\n\tM_0t_at = M_0t_at + 4;\n\tN_0t_at = N_0t_at + 4;\n}\n\n# Single-Precision Multiply-and-Accumulate Operation\n# pattern 0100nnnnmmmm1111\n# text mac.w @+,@+\n# arch arch_sh_up\ndefine pcodeop mac_wOp;\n:mac.w M_0t_at,N_0t_at is OP_0=0x4 & OP_1=0xf & M_0t_at & N_0t_at {\n\tlocal tmpM:4 = sext(*:2 M_0t_at);\n\tlocal tmpN:4 = sext(*:2 N_0t_at);\n\tlocal mac:8 = zext(MACL) + (zext(MACH) << 32);\n\tlocal product:4 = tmpN * tmpN;\n\tif ($(S_FLAG) == 0) goto ;\n\tmac = mac_wOp(mac,product);\n goto ;\n\n mac = mac + sext(product);\n\n\tMACL = mac[0,32];\n\tMACH = mac[32,32];\n\tM_0t_at = M_0t_at + 2;\n\tN_0t_at = N_0t_at + 2;\n}\n\n# Data Transfer\n# pattern 0110nnnnmmmm0011\n# text mov ,\n# arch arch_sh_up\n:mov M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x3 {\n\n\tN_0t = M_0t;\n}\n\n\n# Data Transfer\n# pattern 0010nnnnmmmm0000\n# text mov.b ,@\n# arch arch_sh_up\n:mov.b M_0t,N_0t_at1 is OP_0=0x2 & N_0t_at1 & M_0t & OP_1=0x0 {\n\n\t*:1 ( N_0t_at1 ) = M_0t:1;\n}\n\n\n# Data Transfer\n# pattern 0010nnnnmmmm0001\n# text mov.w ,@\n# arch arch_sh_up\n:mov.w M_0t,N_0t_at1 is OP_0=0x2 & N_0t_at1 & M_0t & OP_1=0x1 {\n\n\t*:2 ( N_0t_at1 ) = M_0t:2;\n}\n\n\n# Data Transfer\n# pattern 0010nnnnmmmm0010\n# text mov.l ,@\n# arch arch_sh_up\n:mov.l M_0t,N_0t_at1 is OP_0=0x2 & N_0t_at1 & M_0t & OP_1=0x2 {\n\n\t*:4 ( N_0t_at1 ) = M_0t;\n}\n\n\n# Data Transfer\n# pattern 0110nnnnmmmm0000\n# text mov.b @,\n# arch arch_sh_up\n:mov.b M_0t_at1,N_0t is OP_0=0x6 & N_0t & M_0t_at1 & OP_1=0x0 {\n\n\tN_0t = sext( *:1 ( M_0t_at1 ) );\n}\n\n\n# Data Transfer\n# pattern 0110nnnnmmmm0001\n# text mov.w @,\n# arch arch_sh_up\n:mov.w M_0t_at1,N_0t is OP_0=0x6 & N_0t & M_0t_at1 & OP_1=0x1 {\n\n\tN_0t = sext( *:2 ( M_0t_at1 ) );\n}\n\n\n# Data Transfer\n# pattern 0110nnnnmmmm0010\n# text mov.l @,\n# arch arch_sh_up\n:mov.l M_0t_at1,N_0t is OP_0=0x6 & N_0t & M_0t_at1 & OP_1=0x2 {\n\n\tN_0t = *:4 ( M_0t_at1 );\n}\n\n\n# Data Transfer\n# pattern 0010nnnnmmmm0100\n# text mov.b ,@-\n# arch arch_sh_up\n:mov.b M_0t,N_0t_at_neg is OP_0=0x2 & N_0t_at_neg & M_0t & OP_1=0x4 {\n\n\tN_0t_at_neg = N_0t_at_neg - 1;\n\t*:1 ( N_0t_at_neg ) = M_0t:1;\n}\n\n\n# Data Transfer\n# pattern 0010nnnnmmmm0101\n# text mov.w ,@-\n# arch arch_sh_up\n:mov.w M_0t,N_0t_at_neg is OP_0=0x2 & N_0t_at_neg & M_0t & OP_1=0x5 {\n\n\tN_0t_at_neg = N_0t_at_neg - 2;\n\t*:2 ( N_0t_at_neg ) = M_0t:2;\n}\n\n\n# Data Transfer\n# pattern 0010nnnnmmmm0110\n# text mov.l ,@-\n# arch arch_sh_up\n:mov.l M_0t,N_0t_at_neg is OP_0=0x2 & N_0t_at_neg & M_0t & OP_1=0x6 {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = M_0t;\n}\n\n\n# Data Transfer\n# pattern 0110nnnnmmmm0100\n# text mov.b @+,\n# arch arch_sh_up\n:mov.b M_0t_at,N_0t is OP_0=0x6 & N_0t & M_0t_at & OP_1=0x4 {\n\n\tN_0t = sext( *:1 ( M_0t_at ) );\n\tM_0t_at = M_0t_at + 1;\n}\n\n\n# Data Transfer\n# pattern 0110nnnnmmmm0101\n# text mov.w @+,\n# arch arch_sh_up\n:mov.w M_0t_at,N_0t is OP_0=0x6 & N_0t & M_0t_at & OP_1=0x5 {\n\n\tN_0t = sext( *:2 ( M_0t_at ) );\n\tM_0t_at = M_0t_at + 2;\n}\n\n\n# Data Transfer\n# pattern 0110nnnnmmmm0110\n# text mov.l @+,\n# arch arch_sh_up\n:mov.l M_0t_at,N_0t is OP_0=0x6 & N_0t & M_0t_at & OP_1=0x6 {\n\n\tN_0t = *:4 ( M_0t_at );\n\tM_0t_at = M_0t_at + 4;\n}\n\n\n# Data Transfer\n# pattern 0000nnnnmmmm0100\n# text mov.b ,@(R0,)\n# arch arch_sh_up\n:mov.b M_0t,N_0t_at_with_r0 is OP_0=0x0 & N_0t_at_with_r0 & M_0t & OP_1=0x4 {\n\n\t*:1 ( r0 + N_0t_at_with_r0 ) = M_0t:1;\n}\n\n\n# Data Transfer\n# pattern 0000nnnnmmmm0101\n# text mov.w ,@(R0,)\n# arch arch_sh_up\n:mov.w M_0t,N_0t_at_with_r0 is OP_0=0x0 & N_0t_at_with_r0 & M_0t & OP_1=0x5 {\n\n\t*:2 ( r0 + N_0t_at_with_r0 ) = M_0t:2;\n}\n\n\n# Data Transfer\n# pattern 0000nnnnmmmm0110\n# text mov.l ,@(R0,)\n# arch arch_sh_up\n:mov.l M_0t,N_0t_at_with_r0 is OP_0=0x0 & N_0t_at_with_r0 & M_0t & OP_1=0x6 {\n\n\t*:4 ( r0 + N_0t_at_with_r0 ) = M_0t;\n}\n\n\n# Data Transfer\n# pattern 0000nnnnmmmm1100\n# text mov.b @(R0,),\n# arch arch_sh_up\n:mov.b M_0t_at_with_r0,N_0t is OP_0=0x0 & N_0t & M_0t_at_with_r0 & OP_1=0xc {\n\n\tN_0t = sext( *:1 ( r0 + M_0t_at_with_r0 ) );\n}\n\n\n# Data Transfer\n# pattern 0000nnnnmmmm1101\n# text mov.w @(R0,),\n# arch arch_sh_up\n:mov.w M_0t_at_with_r0,N_0t is OP_0=0x0 & N_0t & M_0t_at_with_r0 & OP_1=0xd {\n\n\tN_0t = sext( *:2 ( r0 + M_0t_at_with_r0 ) );\n}\n\n\n# Data Transfer\n# pattern 0000nnnnmmmm1110\n# text mov.l @(R0,),\n# arch arch_sh_up\n:mov.l M_0t_at_with_r0,N_0t is OP_0=0x0 & N_0t & M_0t_at_with_r0 & OP_1=0xe {\n\n\tN_0t = *:4 ( r0 + M_0t_at_with_r0 );\n}\n\n\n# Data Transfer\n# pattern 1110nnnniiiiiiii\n# text mov #,\n# arch arch_sh_up\n:mov I_0t,N_0t is OP_0=0xe & N_0t & I_0t {\n\n\tN_0t = I_0t; # NOTE I_0t already signed extended\n}\n\n\n# Data Transfer\n# pattern 1001nnnndddddddd\n# text mov.w @(,PC),\n# arch arch_sh_up\n:mov.w U_0t_2pc,N_0t is OP_0=0x9 & N_0t & U_0t_2pc {\n\n\tN_0t = sext( U_0t_2pc ); # NOTE U_0t_2pc units is bytes\n}\n\n\n# Data Transfer\n# pattern 1101nnnndddddddd\n# text mov.l @(,PC),\n# arch arch_sh_up\n:mov.l U_0t_4pc,N_0t is OP_0=0xd & N_0t & U_0t_4pc {\n\n\tN_0t = U_0t_4pc; # NOTE U_0t_4pc units is bytes\n}\n\n\n# Data Transfer\n# pattern 11000100dddddddd\n# text mov.b @(,GBR),R0\n# arch arch_sh_up\n:mov.b U_0t_gbr_at_1,r0 is OP_2=0xc4 & U_0t_gbr_at_1 & r0 {\n\n\tr0 = sext( *:1 ( U_0t_gbr_at_1 ) );\n}\n\n\n# Data Transfer\n# pattern 11000101dddddddd\n# text mov.w @(,GBR),R0\n# arch arch_sh_up\n:mov.w U_0t_gbr_at_2,r0 is OP_2=0xc5 & U_0t_gbr_at_2 & r0 {\n\n\tr0 = sext( *:2 ( U_0t_gbr_at_2 ) ); # NOTE U_0t_gbr_at_2 units is bytes\n}\n\n\n# Data Transfer\n# pattern 11000110dddddddd\n# text mov.l @(,GBR),R0\n# arch arch_sh_up\n:mov.l U_0t_gbr_at_4,r0 is OP_2=0xc6 & U_0t_gbr_at_4 & r0 {\n\n\tr0 = *:4 ( U_0t_gbr_at_4 ); # NOTE U_0t_gbr_at_4 units is bytes\n}\n\n\n# Data Transfer\n# pattern 11000000dddddddd\n# text mov.b R0,@(,GBR)\n# arch arch_sh_up\n:mov.b r0,U_0t_gbr_at_1 is OP_2=0xc0 & U_0t_gbr_at_1 & r0 {\n\n\t*:1 ( U_0t_gbr_at_1 ) = r0:1;\n}\n\n\n# Data Transfer\n# pattern 11000001dddddddd\n# text mov.w R0,@(,GBR)\n# arch arch_sh_up\n:mov.w r0,U_0t_gbr_at_2 is OP_2=0xc1 & U_0t_gbr_at_2 & r0 {\n\n\t*:2 ( U_0t_gbr_at_2 ) = r0:2; # NOTE U_0t_gbr_at_2 units is bytes\n}\n\n\n# Data Transfer\n# pattern 11000010dddddddd\n# text mov.l R0,@(,GBR)\n# arch arch_sh_up\n:mov.l r0, U_0t_gbr_at_4 is OP_2=0xc2 & U_0t_gbr_at_4 & r0 {\n\n\t*:4 ( U_0t_gbr_at_4 ) = r0; # NOTE U_0t_4_at_gbr_r0_1 units is bytes\n}\n\n\n# Data Transfer\n# pattern 10000000mmmmdddd\n# text mov.b R0,@(,)\n# arch arch_sh_up\n:mov.b r0,U_2t_M0_dispr01 is OP_2=0x80 & M_0t & U_2t_M0_dispr01 & r0 {\n\n\t*:1 ( U_2t_M0_dispr01 + M_0t ) = r0:1;\n}\n\n\n# Data Transfer\n# pattern 10000001mmmmdddd\n# text mov.w R0,@(,)\n# arch arch_sh_up\n:mov.w r0,U_2t_M0_dispr02 is OP_2=0x81 & M_0t & U_2t_M0_dispr02 & r0 {\n\n\t*:2 ( U_2t_M0_dispr02 + M_0t ) = r0:2; # NOTE U_2t_M0_dispr02 units is bytes\n}\n\n\n# Data Transfer\n# pattern 0001nnnnmmmmdddd\n# text mov.l ,@(,)\n# arch arch_sh_up\n:mov.l M_0t,U_2t_N0_dispr04 is OP_0=0x1 & M_0t & N_0t & U_2t_N0_dispr04 {\n\n\t*:4 ( U_2t_N0_dispr04 + N_0t ) = M_0t; # NOTE U_2t_N0_dispr04 units is bytes \n}\n\n\n# Data Transfer\n# pattern 10000100mmmmdddd\n# text mov.b @(,),R0\n# arch arch_sh_up\n:mov.b U_2t_M0_dispr01,r0 is OP_2=0x84 & M_0t & U_2t_M0_dispr01 & r0 {\n\n\tr0 = sext( *:1 ( U_2t_M0_dispr01 + M_0t ) );\n}\n\n\n# Data Transfer\n# pattern 10000101mmmmdddd\n# text mov.w @(,),R0\n# arch arch_sh_up\n:mov.w U_2t_M0_dispr02,r0 is OP_2=0x85 & U_2t_M0_dispr02 & M_0t & r0 {\n\n\tr0 = sext( *:2 ( U_2t_M0_dispr02 + M_0t ) ); # NOTE U_2t_M0_dispr02 units is bytes\n}\n\n\n# Data Transfer\n# pattern 0101nnnnmmmmdddd\n# text mov.l @(,),\n# arch arch_sh_up\n:mov.l U_2t_M0_dispr04,N_0t is OP_0=0x5 & N_0t & M_0t & U_2t_M0_dispr04 {\n\n\tN_0t = *:4 ( U_2t_M0_dispr04 + M_0t ); # NOTE U_2t_M0_dispr04 units is bytes\n}\n\n\n# Effective Address Transfer\n# pattern 11000111iiiiiiii\n# text mova @(,PC),R0\n# arch arch_sh_up\n:mova U_0t_4pc,r0 is OP_2=0xc7 & U_0t_4pc & r0 {\n\n\tr0 = &U_0t_4pc; # NOTE U_0t_4pc units is bytes\n}\n\n\n# MOVe with Cache block Allocation\n# pattern 0000nnnn11000011\n# text movca.l R0,@\n# arch arch_sh4_nommu_nofpu_up\n:movca.l N_0txx is OP_0=0x0 & N_0txx & OP_4=0xc3 {\n\n\t*:4 ( N_0txx ) = r0; # NOTE ignore cache issues\n}\n\n# T Bit Transfer\n# pattern 0000nnnn00101001\n# text movt \n# arch \n:movt N_0t is OP_0=0x0 & N_0t & OP_4=0x29 {\n\n\tN_0t = zext($(T_FLAG));\n}\n\n# Move Unaligned Long\n# pattern 0100mmmm10101001\n# text movua.l @,R0\n# arch \n:movua.l N_0t_at,r0 is OP_0=0x4 & N_0t_at & r0 & OP_4=0xA9 {\n\tr0 = (*:4 ( N_0t_at )); \n}\n\n# Move Unaligned Long Pointer\n# pattern 0100mmmm11101001\n# text movua.l @+,R0\n# arch \n:movua.l N_0t_at,r0 is OP_0=0x4 & N_0t_at & r0 & OP_4=0xE9 {\n\tr0 = (*:4 ( N_0t_at ));\n\tN_0t_at = N_0t_at + 4;\n}\n\n:movua.l N_0t_at,r0 is OP_0=0x4 & N_0t_at & N_0=0 & r0 & OP_4=0xE9 {\n\tr0 = (*:4 ( N_0t_at ));\n}\n\n# Double-Precision Multiplication\n# pattern 0000nnnnmmmm0111\n# text mul.l ,\n# arch \n:mul.l M_0t,N_0t is OP_0=0x0 & N_0t & M_0t & OP_1=0x7 {\n\n\tMACL = N_0t * M_0t;\n}\n\n\n# Signed Multiplication\n# pattern 0010nnnnmmmm1111\n# text muls.w ,\n# arch \n:muls.w M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xf {\n\n\tMACL = sext(N_0t:2) * sext(M_0t:2);\n}\n\n\n# Unsigned Multiplication\n# pattern 0010nnnnmmmm1110\n# text mulu.w ,\n# arch \n:mulu.w M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xe {\n\n\tMACL = zext(N_0t:2) * zext(M_0t:2);\n}\n\n\n# Sign Inversion\n# pattern 0110nnnnmmmm1011\n# text neg ,\n# arch \n:neg M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xb {\n\n\tN_0t = -M_0t;\n}\n\n\n# Sign Inversion with Borrow\n# pattern 0110nnnnmmmm1010\n# text negc ,\n# arch \n:negc M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xa {\n\tlocal Tcopy:4 = zext($(T_FLAG));\n\t$(T_FLAG) = 0 != M_0t;\n\tlocal result:4 = - M_0t;\n\t$(T_FLAG) = $(T_FLAG) || (result < Tcopy);\n\tN_0t = result - Tcopy;\n}\n\n\n# No Operation\n# pattern 0000000000001001\n# text nop\n# arch \n:nop is OP_3=0x9 { } # Empty on purpose\n\n\n# Bit Inversion\n# pattern 0110nnnnmmmm0111\n# text not ,\n# arch \n:not M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x7 {\n\n\tN_0t = ~M_0t;\n}\n\ndefine pcodeop CacheBlockInvalidate;\n\n# Operand Cache Block Invalidate \n# pattern 0000nnnn10010011\n# text ocbi @\n# arch \n:ocbi N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0x93 { CacheBlockInvalidate(N_0t_at1); }\n\ndefine pcodeop CacheBlockPurge;\n\n# Cache Block Purge\n# pattern 0000nnnn10100011\n# text ocbp @\n# arch \n:ocbp N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xa3 { CacheBlockPurge(N_0t_at1); }\n\ndefine pcodeop CacheBlockWriteBack;\n\n# TODO ocbwb \n# Cache Block Write-Back\n# pattern 0000nnnn10110011\n# text ocbwb @\n# arch \n:ocbwb N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xb3 { CacheBlockWriteBack(N_0t_at1); }\n\n\n# Logical OR\n# pattern 0010nnnnmmmm1011\n# text or ,\n# arch \n:or M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xb {\n\n\tN_0t = N_0t | M_0t;\n}\n\n\n# Logical OR\n# pattern 11001011iiiiiiii\n# text or #,R0\n# arch \n:or U_0t_r0 is OP_2=0xcb & U_0t_r0 {\n\n\tr0 = r0 | U_0t_r0;\n}\n\n\n# Logical OR\n# pattern 11001111iiiiiiii\n# text or.b #,@(R0,GBR)\n# arch \n:or.b U_0t1 is OP_2=0xcf & U_0t1 {\n\n\t*:1 (GBR + r0) = ( *:1 (GBR + r0) ) | U_0t1;\n}\n\n\n# Prefetch to Data Cache\n# pattern 0000nnnn10000011\n# text pref @\n# arch \n:pref N_0tjmp is OP_0=0x0 & N_0tjmp & OP_4=0x83 { } # Empty on purpose\n\n\n# One-Bit Left Rotation through T Bit\n# pattern 0100nnnn00100100\n# text rotcl \n# arch \n:rotcl N_0t is OP_0=0x4 & N_0t & OP_4=0x24 {\n\n\ttemp:1 = ( (N_0t & 0x80000000) != 0 );\n\tN_0t = (N_0t << 1) | zext($(T_FLAG));\n\t$(T_FLAG) = temp;\n}\n\n# One-Bit Right Rotation through T Bit\n# pattern 0100nnnn00100101\n# text rotcr \n# arch \n:rotcr N_0t is OP_0=0x4 & N_0t & OP_4=0x25 {\n\n\ttemp:1 = ( (N_0t & 0x00000001) != 0 );\n\tN_0t = ( N_0t >> 1 ) | ( zext($(T_FLAG)) << 31 );\n\t$(T_FLAG) = temp;\n}\n\n\n# One-Bit Left Rotation\n# pattern 0100nnnn00000100\n# text rotl \n# arch \n:rotl N_0t is OP_0=0x4 & N_0t & OP_4=0x4 {\n\n\t$(T_FLAG) = ( (N_0t & 0x80000000) != 0 );\n\tN_0t = (N_0t << 1) | zext($(T_FLAG));\n}\n\n\n# One-Bit Right Rotation\n# pattern 0100nnnn00000101\n# text rotr \n# arch \n:rotr N_0t is OP_0=0x4 & N_0t & OP_4=0x5 {\n\n\t$(T_FLAG) = ( (N_0t & 0x00000001) != 0 );\n\tN_0t = ( N_0t >> 1 ) | ( zext($(T_FLAG)) << 31 );\n}\n\n\n# Return from Exception Handling\n# pattern 0000000000101011\n# text rte\n# arch \n:rte is OP_3=0x2b {\n\n\tSR = SSR;\n\tsplitSRregister();\n\tPC = SPC;\n\tdelayslot(1);\n\treturn [PC];\n}\n\n\n# Return from Subroutine Procedure\n# pattern 0000000000001011\n# text rts\n# arch \n:rts is OP_3=0xb {\n\n\tPC = PR;\n\tdelayslot(1);\n\treturn [PC];\n}\n\n\n# S Bit Setting\n# pattern 0000000001011000\n# text sets\n# arch \n:sets is OP_3=0x58 {\n\n\t$(S_FLAG) = 1;\n}\n\n\n# T Bit Setting\n# pattern 0000000000011000\n# text sett\n# arch \n:sett is OP_3=0x18 {\n\n\t$(T_FLAG) = 1;\n}\n\n\n# Note: this constructor follows the description on page 393 precisely, though simpler,\n# it should produce identical results to the pseudo-code above\n:shad M_0t,N_0t is OP_0=0x4 & N_0t & M_0t & OP_1=0xc {\n\n\tif ( M_0t s< 0 ) goto ;\n\tN_0t = N_0t << ( M_0t & 0x1f );\n\tgoto ;\n\n\t\n\tN_0t = N_0t s>> ( ( ~M_0t & 0x1f ) + 1 );\n\t\n}\n\n\n# One-Bit Left Arithmetic Shift\n# pattern 0100nnnn00100000\n# text shal \n# arch \n:shal N_0t is OP_0=0x4 & N_0t & OP_4=0x20 {\n\n\t$(T_FLAG) = ( ( N_0t & 0x80000000 ) != 0 );\n\tN_0t = N_0t << 1;\n}\n\n\n# One-Bit Right Arithmetic Shift\n# pattern 0100nnnn00100001\n# text shar \n# arch \n:shar N_0t is OP_0=0x4 & N_0t & OP_4=0x21 {\n\n\t$(T_FLAG) = ( ( N_0t & 0x00000001 ) != 0 );\n\tN_0t = N_0t s>> 1;\n}\n\n\n# Note: this constructor follows the description on page 397 precisely, though simpler,\n# it should produce identical results to the pseudo-code above\n:shld M_0t,N_0t is OP_0=0x4 & N_0t & M_0t & OP_1=0xd {\n\n\tif ( M_0t s< 0 ) goto ;\n\tN_0t = N_0t << ( M_0t & 0x1f );\n\tgoto ;\n\n\t\n\tN_0t = N_0t >> ( ( ~M_0t & 0x1f ) + 1 );\n\t\n}\n\n\n# n-Bit Left Logical Shift\n# One-Bit Left Logical Shift\n# pattern 0100nnnn00000000\n# text shll \n# arch \n:shll N_0t is OP_0=0x4 & N_0t & OP_4=0x0 {\n\n\t$(T_FLAG) = ( ( N_0t & 0x80000000 ) != 0 );\n\tN_0t = N_0t << 1;\n}\n\n\n# n-Bit Left Logical Shift\n# pattern 0100nnnn00001000\n# text shll2 \n# arch \n:shll2 N_0t is OP_0=0x4 & N_0t & OP_4=0x8 {\n\n\tN_0t = ( N_0t << 2 );\n}\n\n\n# n-Bit Left Logical Shift\n# pattern 0100nnnn00011000\n# text shll8 \n# arch \n:shll8 N_0t is OP_0=0x4 & N_0t & OP_4=0x18 {\n\n\tN_0t = ( N_0t << 8 );\n}\n\n\n# pattern 0100nnnn00101000\n# text shll16 \n# arch \n:shll16 N_0t is OP_0=0x4 & N_0t & OP_4=0x28 {\n\n\tN_0t = ( N_0t << 16 );\n}\n\n\n# One-Bit Right Logical Shift\n# pattern 0100nnnn00000001\n# text shlr \n# arch \n:shlr N_0t is OP_0=0x4 & N_0t & OP_4=0x1 {\n\n\t$(T_FLAG) = ( ( N_0t & 0x00000001 ) != 0 );\n\tN_0t = N_0t >> 1;\n}\n\n\n# n-Bit Left Logical Shift\n# pattern 0100nnnn00001001\n# text shlr2 \n# arch \n:shlr2 N_0t is OP_0=0x4 & N_0t & OP_4=0x9 {\n\n\tN_0t = N_0t >> 2;\n}\n\n\n# n-Bit Left Logical Shift\n# pattern 0100nnnn00011001\n# text shlr8 \n# arch \n:shlr8 N_0t is OP_0=0x4 & N_0t & OP_4=0x19 {\n\n\tN_0t = N_0t >> 8;\n}\n\n\n# n-Bit Left Logical Shift\n# pattern 0100nnnn00101001\n# text shlr16 \n# arch \n:shlr16 N_0t is OP_0=0x4 & N_0t & OP_4=0x29 {\n\n\tN_0t = N_0t >> 16;\n}\n\n\n# Transition to Power-Down Mode\n# pattern 0000000000011011\n# text sleep\n# arch \n:sleep is OP_3=0x1b { } # empty on purpose\n\n\n# Store from Control Register\n# pattern 0000nnnn00000010\n# text stc SR,\n# arch arch_sh_up\n:stc sr_N_0t is OP_0=0x0 & sr_N_0t & OP_4=0x2 {\n\n\tgenSRregister();\n\tsr_N_0t = SR;\n}\n\n\n# Store from Control Register\n# pattern 0000nnnn00010010\n# text stc GBR,\n# arch \n:stc gbr_N_0t is OP_0=0x0 & gbr_N_0t & OP_4=0x12 {\n\n\tgbr_N_0t = GBR;\n}\n\n\n# Store from Control Register\n# pattern 0000nnnn00100010\n# text stc VBR,\n# arch arch_sh_up\n:stc vbr_N_0t is OP_0=0x0 & vbr_N_0t & OP_4=0x22 {\n\n\tvbr_N_0t = VBR;\n}\n\n\n# pattern 0000nnnn00110010\n# text stc SSR,\n# arch arch_sh3_nommu_up\n:stc ssr_N_0t is OP_0=0x0 & ssr_N_0t & OP_4=0x32 {\n\n\tssr_N_0t = SSR;\n}\n\n\n# pattern 0000nnnn01000010\n# text stc SPC,\n# arch arch_sh3_nommu_up\n#\n:stc spc_N_0t is OP_0=0x0 & spc_N_0t & OP_4=0x42 {\n\n\tspc_N_0t = SPC;\n}\n\n\n# pattern 0000nnnn00111010\n# text stc SGR,\n# arch arch_sh4_nommu_nofpu_up\n:stc sgr_N_0t is OP_0=0x0 & sgr_N_0t & OP_4=0x3a {\n\n\tsgr_N_0t = SGR;\n}\n\n\n# pattern 0000nnnn11111010\n# text stc DBR,\n# arch arch_sh4_nommu_nofpu_up\n:stc dbr_N_0t is OP_0=0x0 & dbr_N_0t & OP_4=0xfa {\n\n\tdbr_N_0t = DBR;\n}\n\n\n# pattern 0000nnnn1xxx0010\n# text stc Rn_BANK,\n# arch arch_sh3_nommu_up\n:stc BANKt,N_0t_bank is OP_0=0x0 & N_0t_bank & OP_9=0x1 & BANKt & OP_1=0x2 {\n\n\tN_0t_bank = BANKt;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn00000011\n# text stc.l SR,@-\n# arch arch_sh_up\n:stc.l sr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x3 & sr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\tgenSRregister();\n\t*:4 ( N_0t_at_neg ) = SR;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn00010011\n# text stc.l GBR,@-\n# arch arch_sh_up\n:stc.l gbr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x13 & gbr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = GBR;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn00100011\n# text stc.l VBR,@-\n# arch arch_sh_up\n:stc.l vbr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x23 & vbr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = VBR;\n}\n\n\n# pattern 0100nnnn00110011\n# text stc.l SSR,@-\n# arch arch_sh3_nommu_up\n:stc.l ssr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x33 & ssr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = SSR;\n}\n\n\n# pattern 0100nnnn01000011\n# text stc.l SPC,@-\n# arch arch_sh3_nommu_up\n:stc.l spc_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x43 & spc_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = SPC;\n}\n\n\n# pattern 0100nnnn00110010\n# text stc.l SGR,@-\n# arch arch_sh4_nommu_nofpu_up\n:stc.l sgr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x32 & sgr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = SGR;\n}\n\n\n# pattern 0100nnnn11110010\n# text stc.l DBR,@-\n# arch arch_sh4_nommu_nofpu_up\n:stc.l dbr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0xf2 & dbr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = DBR;\n}\n\n\n# pattern 0100nnnn1xxx0011\n# text stc.l Rn_BANK,@-\n# arch arch_sh3_nommu_up\n:stc.l BANKt,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_9=0x1 & BANKt & OP_1=0x3 {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = BANKt;\n}\n\n\n# Store from System Register\n# pattern 0000nnnn00001010\n# text sts MACH,\n# arch arch_sh_up\n:sts mach_N_0t is OP_0=0x0 & mach_N_0t & OP_4=0xa {\n\n\tmach_N_0t = MACH;\n}\n\n\n# Store from System Register\n# pattern 0000nnnn00011010\n# text sts MACL,\n# arch arch_sh_up\n:sts macl_N_0t is OP_0=0x0 & macl_N_0t & OP_4=0x1a {\n\n\tmacl_N_0t = MACL;\n}\n\n\n# Store from System Register\n# pattern 0000nnnn00101010\n# text sts PR,\n# arch arch_sh_up\n:sts pr_N_0t is OP_0=0x0 & pr_N_0t & OP_4=0x2a {\n\n\tpr_N_0t = PR;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn00000010\n# text sts.l MACH,@-\n# arch arch_sh_up\n:sts.l mach_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x2 & mach_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = MACH;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn00010010\n# text sts.l MACL,@-\n# arch arch_sh_up\n:sts.l macl_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x12 & macl_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = MACL;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn00100010\n# text sts.l PR,@-\n# arch arch_sh_up\n:sts.l PR,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x22 & PR {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = PR;\n}\n\n\n# Store from System Register\n# pattern 0000nnnn01011010\n# text sts FPUL,\n# arch arch_sh2e_up\n:sts fpul_N_0t is OP_0=0x0 & fpul_N_0t & OP_4=0x5a {\n\n\tfpul_N_0t = FPUL;\n}\n\n\n# Store from System Register\n# pattern 0000nnnn01101010\n# text sts FPSCR,\n# arch arch_sh2e_up\n:sts fpscr_N_0t is OP_0=0x0 & fpscr_N_0t & OP_4=0x6a {\n\n\tgenFPSCRregister();\n\tfpscr_N_0t = FPSCR;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn01010010\n# text sts.l FPUL,@-\n# arch arch_sh2e_up\n:sts.l fpul_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x52 & fpul_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\t*:4 ( N_0t_at_neg ) = FPUL;\n}\n\n\n# Store from Control Register\n# pattern 0100nnnn01100010\n# text sts.l FPSCR,@-\n# arch arch_sh2e_up\n:sts.l fpscr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x62 & fpscr_t {\n\n\tN_0t_at_neg = N_0t_at_neg - 4;\n\tgenFPSCRregister();\n\t*:4 ( N_0t_at_neg ) = FPSCR;\n}\n\n\n# Binary Subtraction\n# pattern 0011nnnnmmmm1000\n# text sub ,\n# arch arch_sh_up\n:sub M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x8 {\n\n\tN_0t = N_0t - M_0t;\n}\n\n\n# Binary Subtraction with Borrow\n# pattern 0011nnnnmmmm1010\n# text subc ,\n# arch arch_sh_up\n:subc M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xa {\n\tlocal Tcopy:4 = zext($(T_FLAG));\n\t$(T_FLAG) = N_0t < M_0t;\n\tlocal result:4 = N_0t - M_0t;\n\t$(T_FLAG) = $(T_FLAG) || (result < Tcopy);\n\tN_0t = result - Tcopy;\n}\n\n\n# Binary Subtraction with Underflow Check\n# pattern 0011nnnnmmmm1011\n# text subv ,\n# arch arch_sh_up\n:subv M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xb {\n\t$(T_FLAG) = sborrow(N_0t, M_0t);\n\tN_0t = N_0t - M_0t;\n}\n\n\n# Upper-/Lower-Half Swap\n# pattern 0110nnnnmmmm1000\n# text swap.b ,\n# arch arch_sh_up\n:swap.b M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x8 {\n\n\tN_0t = ( M_0t & 0xFFFF0000 ) |\n ( ( M_0t & 0x000000FF ) << 8 ) |\n ( ( M_0t & 0x0000FF00 ) >> 8 );\n}\n\n\n# Upper-/Lower-Half Swap\n# pattern 0110nnnnmmmm1001\n# text swap.w ,\n# arch arch_sh_up\n:swap.w M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x9 {\n\n\tN_0t = ( M_0t << 16 ) | ( M_0t >> 16 );\n}\n\n# Synchronize Data Operation\n# pattern 0000000010101011\n# text synco\n# arch arch_sh4a_up\ndefine pcodeop SynchronizeDataOperation;\n\n:synco is OP_3=0x00ab {\n\tSynchronizeDataOperation();\n}\n\n\n# Memory Test and Bit Setting\n# pattern 0100nnnn00011011\n# text tas.b @\n# arch arch_sh_up\n:tas.b N_0t_at1 is OP_0=0x4 & N_0t_at1 & OP_4=0x1b {\n\n\ttemp:1 = *:1 ( N_0t_at1 );\n\t$(T_FLAG) = ( temp == 0 );\n\ttemp = temp | 0x80;\n\t*:1 ( N_0t_at1 ) = temp;\n}\n\ndefine pcodeop TrapAlways;\n\n# Trap Exception Handling\n# pattern 11000011iiiiiiii\n# text trapa #\n# arch arch_sh_up\n:trapa U_0t is OP_2=0xc3 & U_0t { TrapAlways(U_0t); }\n\n\n# AND Operation T Bit Setting\n# pattern 0010nnnnmmmm1000\n# text tst ,\n# arch arch_sh_up\n:tst M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0x8 {\n\n\t$(T_FLAG) = ( (N_0t & M_0t) == 0 );\n}\n\n\n# AND Operation T Bit Setting\n# pattern 11001000iiiiiiii\n# text tst #,R0\n# arch arch_sh_up\n:tst U_0t_r0 is OP_2=0xc8 & U_0t_r0 {\n\n\t$(T_FLAG) = ( ( r0 & U_0t_r0 ) == 0 );\n}\n\n\n# AND Operation T Bit Setting\n# pattern 11001100iiiiiiii\n# text tst.b #,@(R0,GBR)\n# arch arch_sh_up\n:tst.b U_0t1 is OP_2=0xcc & U_0t1 {\n\n\t$(T_FLAG) = ( ( (*:1 ( GBR + r0 )) & U_0t1 ) == 0 );\n}\n\n\n# pattern 0010nnnnmmmm1010\n# text xor ,\n# arch arch_sh_up\n:xor M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xa {\n\n\tN_0t = N_0t ^ M_0t;\n}\n\n\n# Exclusive Logical OR\n# pattern 11001010iiiiiiii\n# text xor #,R0\n# arch arch_sh_up\n:xor U_0t_r0 is OP_2=0xca & U_0t_r0 {\n\n\tr0 = r0 ^ U_0t_r0;\n}\n\n\n# Exclusive Logical OR\n# pattern 11001110iiiiiiii\n# text xor.b #,@(R0,GBR)\n# arch arch_sh_up\n:xor.b U_0t1 is OP_2=0xce & U_0t1 {\n\n\t*:1 (GBR + r0) = ( *:1 (GBR + r0) ) ^ U_0t1;\n}\n\n\n# Middle Extraction from Linked Registers\n# pattern 0010nnnnmmmm1101\n# text xtrct ,\n# arch arch_sh_up\n:xtrct M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xd {\n\n\tN_0t = (M_0t << 16) | (N_0t >> 16);\n}\n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4_be.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4_be.slaspec", "content": "# This module defines SuperH version 4a, but should work against versions 1,2, and 3.\n# DSP Extensions are not yet added\n\n# Based on \"Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf)\n\n@define ENDIAN \"big\"\n\n@include \"SuperH4.sinc\"\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4_le.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/SuperH4_le.slaspec", "content": "# This module defines SuperH version 4, but should work against versions 1,2, and 3. \n# There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable\n# with this.\n\n# Based on \"Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf)\n\n@define ENDIAN \"little\"\n\n@include \"SuperH4.sinc\"\n" }, { "path": "pypcode/processors/SuperH4/data/languages/old/SuperH4-BE-16.lang", "content": "\n\n \n SuperH4:BE:16:default\n SuperH4\n default\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/old/SuperH4-BE-16.trans", "content": "\n\n SuperH4:BE:16:default\n SuperH4:BE:32:default\n \n\n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/old/SuperH4-LE-16.lang", "content": "\n\n \n SuperH4:LE:16:default\n SuperH4\n default\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/SuperH4/data/languages/old/SuperH4-LE-16.trans", "content": "\n\n SuperH4:LE:16:default\n SuperH4:LE:32:default\n \n\n\n" }, { "path": "pypcode/processors/SuperH4/data/manuals/superh4.idx", "content": "@ rej09b0318_sh_4sm.pdf[SH-4 Software Manual Rev 6.00 2006.09]\nadd, 229\naddc, 231\naddv, 232\nand, 234\nand.b, 234\nbf, 236\nbf/s, 238\nbra, 240\nbraf, 242\nbsr, 244\nbsrf, 246\nbt, 248\nbt/s, 250\nclrmac, 252\nclrs, 253\nclrt, 254\ncmp/eq, 255\ncmp/ge, 255\ncmp/gt, 255\ncmp/hi, 255\ncmp/hs, 255\ncmp/pl, 255\ncmp/pz, 255\ncmp/str, 255\ncmp/eq, 255\ncmp/str, 255\ndiv0s, 259\ndiv0u, 260\ndiv1, 261\ndmuls.l, 266\ndmulu.l, 268\ndt, 270\nexts.b, 271\nexts.w, 271\nextu.b, 273\nextu.w, 273\njmp, 331\njsr, 332\nldc, 334\nldc.l, 334\nlds, 339\nlds.l, 339\nldtlb, 343\nmac.l, 345\nmac, 349\nmac.w, 349\nmov, 352\nmov.b, 352\nmov.w, 352\nmov.l, 352\nmova, 367\nmovca.l, 368\nmovt, 369\nmul.l, 370\nmuls.w, 371\nmuls, 371\nmulu.w, 372\nmulu, 372\nneg, 373\nnegc, 374\nnop, 375\nnot, 376\nocbi, 377\nocbp, 378\nocbwb, 379\nor, 380\nor.b, 380\npref, 382\nrotcl, 383\nrotcr, 384\nrotl, 385\nrotr, 386\nrte, 387\nrts, 389\nsets, 391\nsett, 392\nshad, 393\nshal, 395\nshar, 396\nshld, 397\nshll, 399\nshll2, 400\nshll8, 400\nshll16, 400\nshlr, 402\nshlr2, 403\nshlr8, 403\nshlr16, 403\nsleep, 405\nstc, 406\nstc.l, 406\nsts, 411\nsts.l, 411\nsub, 416\nsubc, 417\nsubv, 418\nswap.b, 420\nswap.w, 420\ntas.b, 422\ntrapa, 424\ntst, 426\ntst.b, 426\nxor, 428\nxor.b, 428\nxtrct, 430\nfabs, 275\nfadd, 276\nfcmp/eq, 279\nfcmp/gt, 279\nfcnvds, 283\nfcnvsd, 286\nfdiv, 288\nfipr, 292\nfldi0, 294\nfldi1, 295\nflds, 296\nfloat, 297\nfmac, 299\nfmov, 305\nfmov.s, 305\nfmul, 312\nfneg, 315\nfrchg, 316\nfschg, 317\nfsqrt, 318\nfsts, 321\nfsub, 322\nftrc, 325\nftrv, 328\n\n\n" }, { "path": "pypcode/processors/SuperH4/data/patterns/SuperH4_patterns.xml", "content": "\n \n \n 0x0b 0x00 0x09 0x00 \t\t\t\t\t\t\n 0x0b 0x00 0xf6 0x6. \t\t\t\t\t\t\n 0x0b 0x00 0x09 0x00 0x00 0x00 \t\t\t\n 0x0b 0x00 0x.. 0x7f \t\t\t\t\t\t\n \n \n 10011101 11100011 10111... ........\t\t\n 0x22 0x4f \t\t\t\t\t\t\t\t\n 0x22 0x4f 1....... 0x7f \t\t\t\t\n 1....... 0x7f \t\t\t\t\t\t\t\n \n \n \n \n" }, { "path": "pypcode/processors/SuperH4/data/patterns/patternconstraints.xml", "content": "\n \n SuperH4_patterns.xml\n \n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI430Common.sinc", "content": "#\n# TI MSP430 \n#\n# Texas Instruments microcontroller 16-bit CPU\n\n\n#\n# \tMemory Architecture\n# \n\ndefine endian=$(ENDIAN);\ndefine alignment=2;\ndefine space RAM type=ram_space size=$(REG_SIZE) default;\ndefine space register type=register_space size=2;\n\n#\n#\tGeneral Registers\n#\ndefine register offset=0x0000 size=$(REG_SIZE) [\n\tPC # R0 # Program Counter\n\tSP # R1 # Stack Pointer\n\tSR # R2 # Status Register \n\tR3 # R3 # Constant Generator\n\t\t\n\t#Available for general use:\n\tR4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15\n\t\n\t#None:\n\tNone\n];\n\n@if REG_SIZE == \"4\"\n\ndefine register offset=0x0000 size=2 [\n\tPC_16 _ SP_16 _ SR_16 _ R3_16 _ R4_16 _ R5_16 _ R6_16 _ R7_16 _\n\tR8_16 _ R9_16 _ R10_16 _ R11_16 _ R12_16 _ R13_16 _ R14_16 _ R15_16 _\n\t\n];\n\ndefine register offset=0x0000 size=1 [\n\tPC_lo PC_hi _ _ # R0 # Program Counter\n\tSP_lo SP_hi _ _ # R1 # Stack Pointer\n\tSR_lo SR_hi _ _ # R2 # Status Register \n\tR3_lo R3_hi _ _ # R3 # Constant Generator\n\t\t\n\t#Available for general use:\n\tR4_lo R4_hi _ _\n R5_lo R5_hi _ _\n R6_lo R6_hi _ _\n R7_lo R7_hi _ _\n R8_lo R8_hi _ _\n R9_lo R9_hi _ _\n R10_lo R10_hi _ _\n R11_lo R11_hi _ _\n R12_lo R12_hi _ _\n R13_lo R13_hi _ _\n R14_lo R14_hi _ _\n R15_lo R15_hi _ _\n\t\n\t#None:\n\tNone_lo None_hi _ _\n];\n@else\n\ndefine register offset=0x0000 size=1 [\n\tPC_lo PC_hi # R0 # Program Counter\n\tSP_lo SP_hi # R1 # Stack Pointer\n\tSR_lo SR_hi # R2 # Status Register \n\tR3_lo R3_hi # R3 # Constant Generator\n\t\t\n\t#Available for general use:\n\tR4_lo R4_hi\n R5_lo R5_hi\n R6_lo R6_hi\n R7_lo R7_hi\n R8_lo R8_hi\n R9_lo R9_hi\n R10_lo R10_hi\n R11_lo R11_hi\n R12_lo R12_hi\n R13_lo R13_hi\n R14_lo R14_hi\n R15_lo R15_hi\n\t\n\t#None:\n\tNone_lo None_hi\n];\n\n@endif\n\ndefine register offset=0x1000 size=4 contextreg;\ndefine context contextreg\n# NOTE: Only instructions that don't use immediates (except ones from constant generator) can\n# use the repeat feature.\n# NOTE: The POPM/PUSM have a starting register & # of register to pop/push. We need to track\n# that info in context for the subtables that do the work.\n ctx_isHi=(0,0) noflow\t\t\t\t\t# Used in pspec to flag msp430 instruction > 64k\n ctx_al=(1,1) noflow\t\t\t\t\t# extension word al field\n ctx_ctregdest=(2,5) noflow\t\t\t# extension word dest register/immediate field\n ctx_ctregdests=(2,5) signed noflow\t# signed version of above\n ctx_repreg=(2,5) noflow\t\t\t\t# register repeat count comes from. \n ctx_regsrc=(6,9) noflow\t\t\t\t# extension word src register/immediate field\n ctx_regsrcs=(6,9) signed noflow\t\t# signed version of above\n ctx_zc=(10,10) noflow\t\t\t\t\t# extension word zero carry field\n ctx_num=(11,11) noflow\t\t\t\t# is repetition field a # or register\n ctx_haveext=(12,14) noflow\t\t\t# used to track type of extension word used\n ctx_popreg_set=(15,18) noflow\t\t\t# used to set register for POPM/PUSHM instructions\n ctx_popreg=(15,18) noflow\t\t\t\t# display register, linked for POPM/PUSHM instructions\n ctx_count=(19,22) noflow\t\t\t\t# tracks count of registers for POPM/PUSHM\n ctx_mreg=(23,26) noflow\t\t\t\t# register being accessed in POPM/PUSHM\n;\n\ndefine register offset=0x2000 size=1 [ CNT ];\n\n#\n# \tTokens\n#\ndefine token instr16(16)\n\top16_0_8\t= (0, 7)\n\top16_4_4\t= (4, 7)\n\top16_0_4 \t= (0, 3)\n\top16_7_9\t= (7, 15)\n\top16_8_4\t= (8, 11)\n\top16_8_8\t= (8, 15)\n\top16_12_4\t= (12, 15)\n\topext_11_5\t= (11, 15)\n\top16_7_1 \t= (7, 7)\n\top16_13_3 \t= (13, 15)\n\t\n\tsrc\t\t= (0, 3)\n\tdest\t= (0, 3)\n\t\n\tas\t= (4, 5)\n\tbow\t= (6, 6)\n\tinsid = (4, 7)\n\tinsidbig \t\t\t= (4, 9)\n\treg16_0_4\t\t\t= (0, 3)\n\tdest_0_4\t\t\t= (0, 3)\n\timm_0_4\t\t\t\t= (0, 4)\n\treg_Direct16_0_4\t= (0, 3)\n\treg_Direct16_0_4W\t= (0, 3)\n\treg_Indexed16_0_4\t= (0, 3)\n\treg_InDirect16_0_4\t= (0, 3)\n\tdest_Direct16_0_4\t= (0, 3)\n\tdest_Indexed16_0_4 \t= (0, 3)\n\tdest_Direct_lo\t\t= (0, 3)\n\tdest_Direct_hi\t\t= (0, 3)\n\t\n\tcondition\t= (10, 12)\n\t\n\toff16 = (0, 9) signed\n\toff16_8_2\t= (8, 9)\n\toff16_4_4\t= (4, 7)\n\toff16_0_4 \t= (0, 3)\n\n\tzc\t= (8, 8)\t\n\tad\t= (7, 7)\n\tal\t= (6, 6)\n\timm_4_4\t\t= (4, 7)\n\timm_8_4\t\t= (8, 11)\n\tsrc_8_4\t\t= (8, 11)\n\tsrc16_8_4\t= (8, 11)\n\tsrc_Direct16_8_4\t= (8, 11)\n\treg_Direct16_8_4W\t= (8, 11)\n\tsrc_InDirect16_8_4\t= (8, 11)\n\tsrc_Indexed16_8_4\t= (8, 11)\n\tsrc_Direct_lo\t\t= (8, 11)\n\tsrc_Direct_hi\t\t= (8, 11)\n\tsrc_ext\t\t\t\t= (7, 10)\n\trrn\t\t\t\t\t= (10, 11)\n\t\n\timm_0_16\t\t\t= (0, 15)\n\timms_0_16\t\t\t= (0, 15) signed\n\tindexExtWord16_0_16 = (0, 15)\n\tindexExtWord16_0_16s = (0, 15) signed\n\tindexExt2Word16_0_16 = (0, 15)\n\tindexExt2Word16_0_16s = (0, 15) signed\n;\n\n\n#\n#\tAttach(s)\n#\nattach variables [ \tsrc_8_4\n\t\t\t\t\tdest_0_4\n\t\t\t\t\treg_Direct16_0_4 \n\t\t\t\t\tsrc_Direct16_8_4 \n\t\t\t\t\tdest_Direct16_0_4\n\t\t\t\t\tctx_popreg\n\t\t\t\t\tctx_repreg ] [ PC SP SR R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 ];\n\t\t\t\t\t\nattach variables [ dest_Direct_lo src_Direct_lo] [ PC_lo SP_lo SR_lo _ R4_lo R5_lo R6_lo R7_lo\n \t\t\tR8_lo R9_lo R10_lo R11_lo R12_lo R13_lo R14_lo R15_lo ];\nattach variables [ dest_Direct_hi src_Direct_hi] [ PC_hi SP_hi SR_hi _ R4_hi R5_hi R6_hi R7_hi\n \t\t\tR8_hi R9_hi R10_hi R11_hi R12_hi R13_hi R14_hi R15_hi ];\n \t\t\t\t\t \nattach variables [ \treg_Indexed16_0_4 \n\t\t\t\t\tsrc_Indexed16_8_4 \n\t\t\t\t\tdest_Indexed16_0_4 ] [ None SP _ _ R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 ];\n\nattach variables [ \treg_InDirect16_0_4 \n\t\t\t\t\tsrc_InDirect16_8_4 ] [ PC SP _ _ R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 ];\n\n@if REG_SIZE == \"4\"\nattach variables [reg_Direct16_0_4W reg_Direct16_8_4W] [PC_16 SP_16 SR_16 _ R4_16 R5_16 R6_16 R7_16 R8_16 R9_16 R10_16 R11_16 R12_16 R13_16 R14_16 R15_16];\n@else\nattach variables [reg_Direct16_0_4W reg_Direct16_8_4W] [PC SP SR _ R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15];\n@endif\n\nSRC16_8_4: src_Direct16_8_4\t\tis src_Direct16_8_4 & reg_Direct16_8_4W {export reg_Direct16_8_4W;}\nDST16_0_4: dest_Direct16_0_4\t\tis dest_Direct16_0_4 & reg_Direct16_0_4W {export reg_Direct16_0_4W;}\nSRC8_8_4: src_Direct16_8_4\t\tis src_Direct16_8_4 & src_Direct_lo {export src_Direct_lo;}\nDST8_0_4: reg_Direct16_0_4\t\tis reg_Direct16_0_4 & dest_Direct_lo {export dest_Direct_lo;}\n\n####################################\n# Status Register (SR) Map\n####################################\n# b15-b9:\tReserved\n# b8:\t\tV (overflow bit)\n# b7:\t\tSCG1 (System Clock generator 1)\n# b6:\t\tSCG0 (System Clock generator 0)\n# b5: \t\tOSCOFF (Oscillator Off)\n# b4:\t\tCPUOFF (CPU off)\n# b3:\t\tGIE\t(General Interrupt Enable)\n# b2:\t\tN\t(Negative Bit) (Word = bit 15, Byte = bit 7)(sign bit)\n# b1:\t\tZ\t(Zero Bit)\n# b0:\t\tC\t(Carry Bit)\n####################################\n\n@define CARRY\t\"SR[0,1]\"\n@define ZERO\t\"SR[1,1]\"\n@define SIGN\t\"SR[2,1]\"\n@define OVERFLOW \"SR[8,1]\"\n@define GIE\t\t\"SR[3,1]\"\n\n#\n#\tSub Constructors\n#\n#-----------------------------------------------\n# B/W: \tByte or Word operation\n#\t\t0: Word Operation\n#\t\t1: Byte Operation\n#-----------------------------------------------\n\n@if REG_SIZE == \"4\"\nAMASK: val\tis ctx_isHi=1 [ val = 0xFFFF; ] { export *[const]:4 val; }\nAMASK: val\tis ctx_isHi=0 [ val = 0xFFFFF; ] { export *[const]:4 val; }\n@else\nAMASK: val\tis bow=0 [ val = 0xFFFE; ] { export *[const]:2 val; } # Memory accesses for unaligned (odd) word addresses round down for alignment.\nAMASK: val\tis bow=1 [ val = 0xFFFF; ] { export *[const]:2 val; }\n@endif\n\n#-----------------------------------------------\n#\n#\tREGISTER (REG)\n#\n# The REG modes are used for the 1 operand form instructions\n#\n#-----------------------------------------------\nREG_W_AS: DST16_0_4 \t\t\t \t\t is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn):\nREG_W_AS: DST16_0_4 \t\t\t \t\t is DST16_0_4 & reg16_0_4=0 & as=0x0 & bow=0x0 {DST16_0_4 = inst_next & 0xFFFE; export DST16_0_4;} # PC register accesses point to next instruction\nREG_W_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (reg_Indexed16_0_4 + indexExtWord16_0_16s) & AMASK; export *:2 tmp;}\nREG_W_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 & AMASK & reg_Indexed16_0_4=1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (reg_Indexed16_0_4 + indexExtWord16_0_16s - 0x2) & AMASK; export *:2 tmp;} # PUSH, CALL X(SP) - addressing includes SP decrement\nREG_W_AS: \"@\"^reg_InDirect16_0_4 \t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 & AMASK {tmp:$(REG_SIZE) = reg_InDirect16_0_4 & AMASK; export *:2 tmp;} # Word/Register Indirect (@Rn):\nREG_W_AS: \"@\"^reg_InDirect16_0_4^\"+\" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 & AMASK {tmp:$(REG_SIZE) = reg_InDirect16_0_4 & AMASK; export *:2 tmp;} # Word/Register Indirect Autoincrement (@Rn+):\nREG_W_AS: labelCalc \t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x0 & AMASK; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic\nREG_W_AS: \"#\"^indexExtWord16_0_16 \t is reg16_0_4=0x0 & as=0x3 & bow=0x0 ; indexExtWord16_0_16 {export *[const]:2 indexExtWord16_0_16; } # Immediate\nREG_W_AS: \"&\"^indexExtWord16_0_16 \t is reg16_0_4=0x2 & as=0x1 & bow=0x0 & AMASK; indexExtWord16_0_16 {tmp:$(REG_SIZE) = indexExtWord16_0_16 & AMASK; export *:2 tmp; } # Absolute\nREG_W_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x0 { export 4:2;}\t\t# Constant\nREG_W_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x0 { export 8:2;}\t\t# Constant\nREG_W_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x0 { export 0:2;}\t\t# Constant\nREG_W_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x0 { export 1:2;}\t\t# Constant\nREG_W_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x0 { export 2:2;}\t\t# Constant\nREG_W_AS: \"#-1\" \t\t\t\t\t is\treg16_0_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2;} \t # Constant\n\nREG_W_AS_DEST: DST16_0_4 \t\t\t is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn):\nREG_W_AS_DEST: DST16_0_4 \t\t\t is DST16_0_4 & reg16_0_4=0 & as=0x0 & bow=0x0 {DST16_0_4 = inst_next & 0xFFFE; export DST16_0_4;} # PC register accesses point to next instruction\nREG_W_AS_DEST: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (reg_Indexed16_0_4 + indexExtWord16_0_16s) & AMASK; export *:2 tmp;}\nREG_W_AS_DEST: \"@\"^reg_InDirect16_0_4 \t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 & AMASK {tmp:$(REG_SIZE) = reg_InDirect16_0_4 & AMASK; export *:2 tmp;} # Word/Register Indirect (@Rn):\nREG_W_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 & AMASK {tmp:$(REG_SIZE) = reg_InDirect16_0_4 & AMASK; export *:2 tmp;} # Word/Register Indirect Autoincrement (@Rn+):\nREG_W_AS_DEST: labelCalc \t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic\nREG_W_AS_DEST: \"#\"^indexExtWord16_0_16 \t is reg16_0_4=0x0 & as=0x3 & bow=0x0 & AMASK ; indexExtWord16_0_16 {export *:2 inst_next; } # Immediate - Undocumented behaviour\nREG_W_AS_DEST: \"&\"^indexExtWord16_0_16 \t is reg16_0_4=0x2 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16 {tmp:$(REG_SIZE) = indexExtWord16_0_16 & AMASK; export *:2 tmp; } # Absolute\n\n#-----------------------------------------------\nREG_B_AS: DST8_0_4 \t\t\t \t\t is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn):\nREG_B_AS: DST8_0_4 \t\t\t \t\t is DST8_0_4 & reg16_0_4=0 & as=0x0 & bow=0x1 {tmp:$(REG_SIZE) = inst_next; DST8_0_4 = tmp:1 & 0xFF; export DST8_0_4;} # PC register accesses point to next instruction - must return register for resulting stores\nREG_B_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (reg_Indexed16_0_4 + indexExtWord16_0_16s) & AMASK; export *:1 tmp;}\nREG_B_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 & AMASK & reg_Indexed16_0_4=1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (reg_Indexed16_0_4 + indexExtWord16_0_16s - 0x2) & AMASK; export *:1 tmp;} # PUSH.B X(SP) - includes SP decrement\nREG_B_AS: \"@\"^reg_InDirect16_0_4 \t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nREG_B_AS: \"@\"^reg_InDirect16_0_4^\"+\" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nREG_B_AS: labelCalc \t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic\nREG_B_AS: \"#\"^indexExtWord16_0_16 \t is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 { export *[const]:1 indexExtWord16_0_16; } # Immediate\nREG_B_AS: \"&\"^indexExtWord16_0_16 \t is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute\nREG_B_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;}\t\t# Constant\nREG_B_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;}\t\t# Constant\nREG_B_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:1;}\t\t# Constant\nREG_B_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:1;}\t\t# Constant\nREG_B_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:1;}\t\t# Constant\nREG_B_AS: \"#-1\" \t\t\t\t\t is\treg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1;} \t# Constant\t\n\nREG_B_AS_DEST: DST8_0_4 \t\t\t \t is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn):\nREG_B_AS_DEST: DST8_0_4 \t\t\t \t is DST8_0_4 & reg16_0_4=0 & as=0x0 & bow=0x1 {tmp:$(REG_SIZE) = inst_next; DST8_0_4 = tmp:1 & 0xFF; export DST8_0_4;} # PC register accesses point to next instruction\nREG_B_AS_DEST: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (reg_Indexed16_0_4 + indexExtWord16_0_16s) & AMASK; export *:1 tmp;}\nREG_B_AS_DEST: \"@\"^reg_InDirect16_0_4 \t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nREG_B_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nREG_B_AS_DEST: labelCalc \t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic\nREG_B_AS_DEST: \"#\"^indexExtWord16_0_16 \t is reg16_0_4=0x0 & as=0x3 & bow=0x1 & AMASK ; indexExtWord16_0_16 {export *:1 inst_next; } # Undocumented behaviour\nREG_B_AS_DEST: \"&\"^indexExtWord16_0_16 \t is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute\n\n#-----------------------------------------------\n#\n# SOURCE (SRC)\n#\n#-----------------------------------------------\nSRC_W_AS: SRC16_8_4 \t\t\t \t\t is SRC16_8_4 & as=0x0 & bow=0x0 {export SRC16_8_4;} # Word/Register Direct (Rn):\nSRC_W_AS: SRC16_8_4 \t\t\t \t\t is SRC16_8_4 & src16_8_4=0 & as=0x0 & bow=0x0 {tmp:2 = inst_next; export tmp;} # PC register accesses point to next instruction (PC-relative addresses already covered by Immediate/Symbolic modes)\nSRC_W_AS: indexExtWord16_0_16s^\"(\"^src_Indexed16_8_4^\")\" is src_Indexed16_8_4 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (src_Indexed16_8_4 + indexExtWord16_0_16s) & AMASK; export *:2 tmp;}\nSRC_W_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x0 & AMASK {tmp:$(REG_SIZE) = src_InDirect16_8_4 & AMASK; export *:2 tmp;} # Word/Register Indirect (@Rn):\nSRC_W_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x0 & AMASK {tmp:$(REG_SIZE) = src_InDirect16_8_4 & AMASK; export *:2 tmp;} # Word/Register Indirect Autoincrement (@Rn+):\nSRC_W_AS: labelCalc \t\t\t\t is src16_8_4=0x0 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic\nSRC_W_AS: \"#\"^indexExtWord16_0_16 \t is src16_8_4=0x0 & as=0x3 & bow=0x0 ; indexExtWord16_0_16 {export *[const]:2 indexExtWord16_0_16; } # Immediate\nSRC_W_AS: \"&\"^indexExtWord16_0_16 \t is src16_8_4=0x2 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16 {tmp:$(REG_SIZE) = indexExtWord16_0_16 & AMASK; export *:2 tmp; } # Absolute\nSRC_W_AS: \"#4\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x0 { export 4:2; }\t\t# Constant\nSRC_W_AS: \"#8\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x0 { export 8:2; }\t\t# Constant\nSRC_W_AS: \"#0\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x0 { export 0:2; }\t\t# Constant\nSRC_W_AS: \"#1\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x0 { export 1:2; }\t\t# Constant\nSRC_W_AS: \"#2\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x0 { export 2:2; }\t\t# Constant\nSRC_W_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2; } \t# Constant\t\n#-----------------------------------------------\nSRC_B_AS: SRC8_8_4 \t\t\t \t\t is SRC8_8_4 & as=0x0 & bow=0x1 { export SRC8_8_4;} # Word/Register Direct (Rn):\nSRC_B_AS: SRC8_8_4 \t\t\t \t\t is SRC8_8_4 & src16_8_4=0 & as=0x0 & bow=0x1 {tmp:$(REG_SIZE) = inst_next; tmp2:1 = tmp:1; export tmp2;} # PC register accesses point to next instruction.\nSRC_B_AS: indexExtWord16_0_16s^\"(\"^src_Indexed16_8_4^\")\" is src_Indexed16_8_4 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = (src_Indexed16_8_4 + indexExtWord16_0_16s) & AMASK; export *:1 tmp;}\nSRC_B_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nSRC_B_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nSRC_B_AS: labelCalc \t\t\t\t is src16_8_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic\nSRC_B_AS: \"#\"^indexExtWord16_0_16 \t is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate\nSRC_B_AS: \"&\"^indexExtWord16_0_16 \t is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute\nSRC_B_AS: \"#4\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; }\t\t# Constant\nSRC_B_AS: \"#8\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; }\t\t# Constant\nSRC_B_AS: \"#0\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:1; }\t\t# Constant\nSRC_B_AS: \"#1\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:1; }\t\t# Constant\nSRC_B_AS: \"#2\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:1; }\t\t# Constant\nSRC_B_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1; } \t# Constant\n\n#-----------------------------------------------\n#\n#\tDESTINATION (DEST)\n#\n#-----------------------------------------------\nDEST_W_AD: DST16_0_4 \t\t \t\t is DST16_0_4 & ad=0x0 & bow=0x0\n {export DST16_0_4;} # Word/Register Direct (Rn):\nDEST_W_AD: DST16_0_4 \t\t\t \t\t is DST16_0_4 & dest_0_4=0 & ad=0x0 & bow=0x0 {DST16_0_4 = inst_next; export DST16_0_4;} # PC register accesses point to next instruction.\n\n# Register relative destinations for R1, R4-R15\nDEST_W_AD: indexExtWord16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s\n {tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + indexExtWord16_0_16s) & AMASK; export *:2 tmp;}\n#---Depends on SRC ---#\n# Source is register-relative and involves 'embedded' immediate\nDEST_W_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n {tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + indexExt2Word16_0_16s) & AMASK; export *:2 tmp;}\n# Source is an 'embedded' immediate implemented by @PC+\nDEST_W_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n {tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + indexExt2Word16_0_16s) & AMASK; export *:2 tmp;}\n# Source is involves a register increment (@reg+) that applies to the destination (of same register, but not PC, SR, R3)\nDEST_W_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK & as=0x3 & src16_8_4=dest_0_4 & (src16_8_4 = 1 | src16_8_4 >= 4) ; indexExt2Word16_0_16s\n {tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + 2 + indexExt2Word16_0_16s) & AMASK; export *:2 tmp;}\n#---End of Depend ----#\n\n# PC-relative destinations\nDEST_W_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s [labelCalc = inst_start + 2 + indexExtWord16_0_16s; ]\n {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic\n#---Depends on SRC ---#\nDEST_W_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x0 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ]\n {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic\nDEST_W_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x0 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ]\n {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic\n#---End of Depend ----#\n\n# SR-relative (absolute value) destinations\nDEST_W_AD: \"&\"^indexExtWord16_0_16 \t is dest=0x2 & ad=0x1 & bow=0x0 & AMASK; indexExtWord16_0_16\n {tmp:$(REG_SIZE) = indexExtWord16_0_16 & AMASK; export *:2 tmp;} # Absolute\n#---Depends on SRC ---#\nDEST_W_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {tmp:$(REG_SIZE) = indexExt2Word16_0_16 & AMASK; export *:2 tmp;} # Absolute\nDEST_W_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {tmp:$(REG_SIZE) = indexExt2Word16_0_16 & AMASK; export *:2 tmp; } # Absolute\n#---End of Depend ----#\n\n#-----------------------------------------------\nDEST_B_AD: DST8_0_4 \t\t \t\t\t is DST8_0_4 & dest_Direct_lo & ad=0x0 & bow=0x1\n { export DST8_0_4; } # Word/Register Direct (Rn):\nDEST_B_AD: DST8_0_4 \t\t\t \t\t is DST8_0_4 & dest_Direct_lo & dest_0_4=0 & ad=0x0 & bow=0x1 {tmp:$(REG_SIZE) = inst_next; DST8_0_4 = tmp:1 & 0xFF; export DST8_0_4;} # PC register accesses point to next instruction\n\nDEST_B_AD: indexExtWord16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s\n { tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + indexExtWord16_0_16s) & AMASK; export *:1 tmp;}\n#---Depends on SRC ---#\nDEST_B_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n { tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + indexExt2Word16_0_16s) & AMASK; export *:1 tmp;}\nDEST_B_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n { tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + indexExt2Word16_0_16s) & AMASK; export *:1 tmp;}\n# Source includes a register increment (@reg+) that applies to the destination (use of same register in source and dest, but not PC, SR, R3)\nDEST_B_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK & as=0x3 & src16_8_4=dest_0_4 & (src16_8_4 = 1 | src16_8_4 >= 4) ; indexExt2Word16_0_16s\n {tmp:$(REG_SIZE) = (dest_Indexed16_0_4 + 2 + indexExt2Word16_0_16s) & AMASK; export *:1 tmp;}\n#---End of Depend ----#\n\nDEST_B_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s [labelCalc = inst_start + 2 + indexExtWord16_0_16s; ]\n {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:1 tmp; } # Symbolic\n#---Depends on SRC ---#\nDEST_B_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ]\n {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic\nDEST_B_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ]\n {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic\n#---End of Depend ----#\n\nDEST_B_AD: \"&\"^indexExtWord16_0_16 \t is dest=0x2 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16\n {export *:1 indexExtWord16_0_16; } # Absolute\n#---Depends on SRC ---#\nDEST_B_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {export *:1 indexExt2Word16_0_16; } # Absolute\nDEST_B_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {export *:1 indexExt2Word16_0_16; } # Absolute\n#---End of Depend ----#\n\n\n# For handling constant operands in CALL and BR instructions.\nDirectAddr: \"#\"^label is indexExtWord16_0_16 [label = indexExtWord16_0_16 & 0xFFFE;] {export *:$(REG_SIZE) label; } # Align value to show and jump to actual target\n\n# Following is only valid for double operand instructions, whose dest uses ad\ntbl_bzero:\t\t\tis ad=0 & reg_Direct16_0_4 & dest_Direct_lo {ztmp:1 = dest_Direct_lo; reg_Direct16_0_4 = 0; dest_Direct_lo = ztmp; }\ntbl_bzero:\t\t\tis epsilon {}\n\n# Following is valid for single operand instructions whose dest uses as\ntbl_bzero_singleop:\t\t\tis as=0 & reg_Direct16_0_4 & dest_Direct_lo {ztmp:1 = dest_Direct_lo; reg_Direct16_0_4 = 0; dest_Direct_lo = ztmp; }\ntbl_bzero_singleop:\t\t\tis epsilon {}\n\n\n@if REG_SIZE == \"4\"\ntbl_wzero:\t\t\tis ad=0 & reg_Direct16_0_4 & reg_Direct16_0_4W {ztmp:2 = reg_Direct16_0_4W; reg_Direct16_0_4 = 0; reg_Direct16_0_4W = ztmp; }\n@endif\ntbl_wzero:\t\t\tis epsilon {}\n\n#\n# Post Processing\n# does correct increment of source register\n# Also catches when PC is being stored to and does the correct branching\n#\npostRegIncrement: is as=0x3 & dest_0_4 & bow=0x0 & reg_InDirect16_0_4 { reg_InDirect16_0_4 = reg_InDirect16_0_4 + 2; }\npostRegIncrement: is as=0x3 & dest_0_4=1 & bow=0x0 & reg_InDirect16_0_4 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0) { } # PUSH.W SP, SP modification covered by PUSH\npostRegIncrement: is as=0x3 & dest_0_4 & bow=0x1 & reg_InDirect16_0_4 { reg_InDirect16_0_4 = reg_InDirect16_0_4 + 1; }\npostRegIncrement: \tis as=0x3 & dest_0_4=1 & bow=0x1 & reg_InDirect16_0_4 { reg_InDirect16_0_4 = reg_InDirect16_0_4 + 2; }\npostRegIncrement: \tis as=0x3 & dest_0_4=1 & bow=0x1 & reg_InDirect16_0_4 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0) { } # PUSH.B @SP+, SP modification covered by PUSH\npostRegIncrement: is as=0x3 & dest_0_4=0 & bow=0x0 & reg_InDirect16_0_4 { } # PC is incremented by 2, but that is just to skip over the value\npostRegIncrement: is as=0x3 & dest_0_4=0 & bow=0x1 & reg_InDirect16_0_4 { } # PC is incremented by 2, but that is just to skip over the value\npostRegIncrement: is as=0x3 & dest_0_4=2 & bow=0x1 { }\npostRegIncrement: is as=0x3 & dest_0_4=3 & bow=0x1 { }\npostRegIncrement: is as=0x3 & dest_0_4=2 & bow=0x0 { }\npostRegIncrement: is as=0x3 & dest_0_4=3 & bow=0x0 { }\npostRegIncrement: is as=0x0 & dest_0_4=0 & bow=0x0 & (op16_12_4!=0x1 | op16_8_4!=0x2 | op16_7_1!=0x0) { PC = PC & 0xFFFE; goto [PC]; } # If PC is modified, alter flow (except for PUSH instructions)\npostRegIncrement: is as=0x0 & dest_0_4=0 & bow=0x1 & (op16_12_4!=0x1 | op16_8_4!=0x2 | op16_7_1!=0x0) { PC = PC & 0xFE; goto [PC]; } # If PC is modified, alter flow (except for PUSH instructions)\npostRegIncrement: is as & bow { }\n\n# R2 and R3 are constant generators - post-increment not supported\npostIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=2 & bow=0x0 & ctx_al=0\n{ }\npostIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=2 & bow=0x1 & ctx_al=0\n{ }\npostIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=3 & bow=0x0 & ctx_al=0\n{ }\npostIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=3 & bow=0x1 & ctx_al=0\n{ }\npostIncrement: is as=0x3 & src16_8_4=2 & bow=0x0\n{ }\npostIncrement: is as=0x3 & src16_8_4=2 & bow=0x1\n{ }\npostIncrement: is as=0x3 & src16_8_4=3 & bow=0x0\n{ }\npostIncrement: is as=0x3 & src16_8_4=3 & bow=0x1\n{ }\n\npostIncrement: \t\t\t is as=0x3 & src16_8_4=0 & bow=0x1 & src_InDirect16_8_4\n{ } # PC is incremented by 2, but that is just to skip over the value\npostIncrement: \t\t\t is as=0x3 & src16_8_4=0 & bow=0x0 & src_InDirect16_8_4\n{ } # PC is incremented by 2, but that is just to skip over the value\n\npostIncrement: \t\t\t is as=0x3 & src16_8_4 & bow=0x0 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 2; }\n\npostIncrement: \t\t\t is as=0x3 & src16_8_4 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 4; }\npostIncrement: \t\t\t is as=0x3 & src16_8_4=1 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 4; }\n\npostIncrement: \t\t\t is as=0x3 & src16_8_4 & bow=0x1 & ctx_al=1 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 1; }\npostIncrement: \t\t\t is as=0x3 & src16_8_4=1 & bow=0x1 & ctx_al=1 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 2; }\n\npostIncrement: \t\t\t is as=0x3 & ctx_haveext=0 & src16_8_4 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 1; }\npostIncrement: \t\t\t is as=0x3 & ctx_haveext=0 & src16_8_4=1 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4\n{ src_InDirect16_8_4 = src_InDirect16_8_4 + 2; }\n\npostIncrement: is as & src16_8_4 & bow\n{ }\n\n\n#\n# Zero Extends if the store is byte oriented, and a register is being stored to\nzeroExtend: is dest_Direct_lo & dest_Direct16_0_4\n{ dest_Direct16_0_4 = zext(dest_Direct_lo); }\n\n#\n# Post processing when destination is the PC - for byte operations\n#\npostIncrementStore: \t\t\t is postIncrement & ad=0x0 & src_InDirect16_8_4 & as=0x3 & src16_8_4=1 & dest_Direct16_0_4=0x0 & bow=0x1 & ctx_al=1 & zeroExtend\n{ build zeroExtend; build postIncrement; return [PC]; }\npostIncrementStore: \t\t\t is postIncrement & ad=0x0 & dest_Direct16_0_4=0x0 & bow=0x1 & ctx_al=1 & zeroExtend\n{ build zeroExtend; build postIncrement; PC = PC & 0xFFFFFE; goto [PC];} # Writes to PC are rounded to alignment\npostIncrementStore: is postIncrement & ad=0x0 & bow=0x1 & ctx_al=1 & zeroExtend\n{ build zeroExtend; build postIncrement; }\n\npostIncrementStore: \t\t\t is postIncrement & ctx_haveext=0 & ad=0x0 & src_InDirect16_8_4 & as=0x3 & src16_8_4=1 & dest_Direct16_0_4=0x0 & bow=0x1 & zeroExtend \n{ build zeroExtend; build postIncrement; return [PC]; }\npostIncrementStore: \t\t\t is postIncrement & ctx_haveext=0 & ad=0x0 & dest_Direct16_0_4=0x0 & bow=0x1 & zeroExtend # MOV.B any,PC\n{ build zeroExtend; build postIncrement; PC = PC & 0xFE; goto [PC];} # Writes to PC are rounded to alignment\npostIncrementStore: is postIncrement & ctx_haveext=0 & ad=0x0 & bow=0x1 & zeroExtend\n{ build zeroExtend; build postIncrement; }\n\npostIncrementStore: \t\t\t is postIncrement & ad=0x0 & src_InDirect16_8_4 & as=0x3 & src16_8_4=1 & dest_Direct16_0_4=0x0\n{ build postIncrement; return [PC]; }\npostIncrementStore: \t\t\t is postIncrement & ad=0x0 & dest_Direct16_0_4=0x0\n{ build postIncrement; PC = PC & 0xFFFE; goto [PC];} # Writes to PC are rounded to alignment\npostIncrementStore: is postIncrement & ad & bow\n{ build postIncrement; }\n\n#-----------------------------------------------\n#\n#\tJUMP CONDITION (JCND)\n#\n#-----------------------------------------------\n\nJCND: \"NE\"\tis condition=0x0 {cndTst:1 = !$(ZERO); export cndTst;} # Not Equal/Zero (cleared)\nJCND: \"EQ\"\tis condition=0x1 {cndTst:1 = $(ZERO); export cndTst;} # Equal/Zero\t (set)\nJCND: \"NC\"\tis condition=0x2 {cndTst:1 = !$(CARRY); export cndTst;} # No Carry/Lower (cleared)\nJCND: \"C\"\tis condition=0x3 {cndTst:1 = $(CARRY); export cndTst;} # Carry/Higher or same (set)\nJCND: \"N\"\tis condition=0x4 {cndTst:1 = $(SIGN); export cndTst;} # Negative (set)\nJCND: \"GE\"\tis condition=0x5 {cndTst:1 = ($(SIGN) == $(OVERFLOW)); export cndTst;} # Greater or equal (>=)\nJCND: \"L\"\tis condition=0x6 {cndTst:1 = ($(SIGN) != $(OVERFLOW)); export cndTst;} # Less (<)\nJCND: \"MP\"\tis condition=0x7 {cndTst:1 = 0x1; export cndTst;} # Unconditional\n\n#-----------------------------------------------\n#\n#\t10 BIT OFFSET\n#\n#-----------------------------------------------\n\nOFFSET_10BIT: offset10 is off16 [offset10 = inst_start + 2 + off16 * 2; ]\n\t{ export *:2 offset10;}\n\t\n\t\n###################################################################################\n#\n#\tSingle-operand arithmetic\n#\t\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | opcode | B/W | As | register |\n# ------------------------------------------------------------------------------\n###################################################################################\n\n###################################################################################\n#\n#\tRRC: Rotate right through carry\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 000 | B/W | As | register | \n:RRC^\".W\" REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x0 & tbl_wzero & postRegIncrement) ... & REG_W_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0;\t# V Flag is reset\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = REG_W_AS_DEST[0,1];\n\tREG_W_AS_DEST = ((zext(tmp) << 0xF) | (REG_W_AS_DEST >> 0x1));\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (REG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (REG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n\n:RRC^\".B\" REG_B_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x1 & tbl_bzero_singleop & postRegIncrement) ... & REG_B_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0;\t# V Flag is reset\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = (REG_B_AS_DEST & 0x1);\n\tREG_B_AS_DEST = ((tmp << 0x7) | (REG_B_AS_DEST >> 0x1));\n\tbuild tbl_bzero_singleop;\n\t# Result Flags...\n\t$(SIGN) = (REG_B_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (REG_B_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n\n###################################################################################\n#\n#\tSWPB: Swap bytes\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 001 | 0 | As | register | \n:SWPB REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & bow=0x0 & tbl_wzero & postRegIncrement) ... & REG_W_AS_DEST {\n\tlowByte:1 = REG_W_AS_DEST[0,8];\n\thighByte:1 = REG_W_AS_DEST[8,8];\n\tREG_W_AS_DEST = (((zext(lowByte)) << 0x8) | zext(highByte));\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n}\n\n\n\n###################################################################################\n#\n#\tRRA: Rotate right arithmetic\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 010 | B/W | As | register | \n:RRA^\".W\" REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x0 & tbl_wzero & postRegIncrement) ... & REG_W_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\t$(CARRY) = REG_W_AS_DEST[0,1];\n\tMSB:2 = REG_W_AS_DEST >> 0xF;\n\tREG_W_AS_DEST = ((MSB << 0xF) | (REG_W_AS_DEST >> 0x1));\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (REG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (REG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n\n:RRA^\".B\" REG_B_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x1 & tbl_bzero_singleop & postRegIncrement) ... & REG_B_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\t$(CARRY) = (REG_B_AS_DEST & 0x1);\n\tMSB:1 = REG_B_AS_DEST >> 0x7;\n\tREG_B_AS_DEST = ((MSB << 0x7) | (REG_B_AS_DEST >> 0x1));\n\tbuild tbl_bzero_singleop;\n\t# Result Flags...\n\t$(SIGN) = (REG_B_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (REG_B_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n\n###################################################################################\n#\n#\tSXT: Sign extend byte to word\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 011 | 0 | As | register | \n:SXT REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & bow=0x0 & tbl_wzero & postRegIncrement) ... & REG_W_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t\t# V Flag\n\t# Operation...\t\n\tbyteVal:1 = REG_W_AS_DEST[0,8];\n\tREG_W_AS_DEST = sext(byteVal);\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (REG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (REG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (REG_W_AS_DEST != 0x0);\t\t\t# C Flag\n\tbuild postRegIncrement;\n}\n\n\n###################################################################################\n#\n#\tPUSH: Push value onto stack\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 100 | B/W | As | register | \n:PUSH^\".W\" REG_W_AS is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x0 & postRegIncrement & AMASK) ... & REG_W_AS {\n\t*:2 ((SP - 0x2) & AMASK) = REG_W_AS; # Mask for possible unaligned SP\n\tSP = SP - 0x2; # Actual behaviour, in conflict with documentation\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n}\n\n:PUSH^\".B\" REG_B_AS is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & REG_B_AS {\n\t*:1 (SP - 0x2) = REG_B_AS;\n\tSP = SP - 0x2; # Actual behaviour, in conflict with documentation\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n}\t\n\n\n###################################################################################\n#\n#\tCALL: Subroutine call; push PC and move source to PC\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 101 | 0 | As | register | \n:CALL REG_W_AS is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x1 & bow=0x0 & postRegIncrement & AMASK) ... & REG_W_AS {\n PC = zext(REG_W_AS) & 0xFFFFFFFE:$(REG_SIZE); # PC assignment before SP modification (relevant for CALL SP). Behaviour differs from documentation\n SP = SP - 0x2;\n *:2 (SP & AMASK) = inst_next;\n build postRegIncrement;\n call [PC];\n #Status bits are not affected\n}\n\n:CALL DirectAddr is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x1 & reg16_0_4=0x0 & as=0x3 & bow=0x0 & postRegIncrement & AMASK); DirectAddr {\n PC = &DirectAddr; # PC assignment before SP modification (relevant for CALL SP). Behaviour differs from documentation\n SP = SP - 0x2;\n *:2 (SP & AMASK) = inst_next;\n build postRegIncrement;\n call DirectAddr;\n #Status bits are not affected\n}\n\n\n\n###################################################################################\n#\n#\tRETI: Return from interrupt; pop SR then pop PC\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 0 | 1 | 0 | 0 | 110 | 0 | 00 | 0000 | \n:RETI is ctx_haveext=0 & op16_12_4=0x1 & op16_8_4=0x3 & op16_7_1=0x0 & as=0x0 & bow=0x0 & op16_0_4=0x0 & op16_4_4=0x0 & AMASK {\n@if REG_SIZE == \"2\"\n\tSR = *:2 (SP & AMASK);\n\tSP = SP + 0x2;\n\tPC = (*:2 (SP & AMASK)) & AMASK;\n@else\n\ttmp:$(REG_SIZE) = zext(*:2 SP);\n\tSR = zext(tmp[0,12]);\n\tSP = SP + 0x2;\n\tPC = zext(*:2 SP) | ((tmp & 0xF000) << 4);\n@endif\t\n\tSP = SP + 0x2;\n\treturn [PC];\n\t#Status bits are restored from system stack\n}\n\n###################################################################################\n#\n#\tConditional jump; PC = PC + 2*offset\n#\t\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 1 | condition | \t\t\t10-bit signed offset\t\t |\n# ------------------------------------------------------------------------------\n###################################################################################\n\n###################################################################################\n#\n#\tJ^JumpCondition 10-bit_signed_offset\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 | 0 | 1 | condition | \t\t\t10-bit signed offset\t\t | \n:J^JCND OFFSET_10BIT is ctx_haveext=0 & op16_13_3=0x1 & JCND & OFFSET_10BIT {\n\tif (JCND) goto OFFSET_10BIT;\n\t#Status bits are not affected\n}\n\n:JMP OFFSET_10BIT is ctx_haveext=0 & op16_13_3=0x1 & condition=0x7 & OFFSET_10BIT {\n\tgoto OFFSET_10BIT;\n\t#Status bits are not affected\n}\n\n###################################################################################\n#\n#\tTwo-operand arithmetic\n#\t\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| opcode | source | Ad | B/W | As | destination |\n# ------------------------------------------------------------------------------\n###################################################################################\n\n###################################################################################\n#\n#\tMOV: Move source to destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 1 0 0 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Branch\n:BR SRC_W_AS is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & ad=0x0 & dest_Direct16_0_4=0x0 & postIncrement) ... & SRC_W_AS ... {\n\tPC = zext(SRC_W_AS) & 0xFFFFFFFE:$(REG_SIZE);\n\tbuild postIncrement; # needed before branch\n\tgoto [PC];\n\t#Status bits are not affected\n}\n\n# Branch to an immediate value\n:BR DirectAddr is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & ad=0x0 & dest_Direct16_0_4=0x0 & src_Direct16_8_4=0x0 & as=0x3); DirectAddr {\n\tPC = &DirectAddr;\n goto DirectAddr;\n #Status bits are not affected\n}\n\n# No operation\n:NOP is ctx_haveext=0 & op16_12_4=0x4 & bow=0x0 & ad=0x0 & as=0x0 & dest_Direct16_0_4=0x3 & src_Direct16_8_4=0x3 & postIncrement {\n\t#Status bits are not affected\n\tbuild postIncrement;\n}\n\n# Pop word from stack\n:POP^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & (ad=0x1 | dest_Direct16_0_4) & as=0x3 & src_Direct16_8_4=0x1 & tbl_wzero & AMASK) ... & DEST_W_AD ... {\n\tDEST_W_AD = *:2 (SP & AMASK);\n\tbuild tbl_wzero;\n\tSP = SP + 0x2;\n\t#Status bits are not affected\n}\n\n# Pop byte from stack\n:POP^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & (ad=0x1 | dest_Direct16_0_4) & as=0x3 & src_Direct16_8_4=0x1 & tbl_bzero) ... & DEST_B_AD ... {\n\tDEST_B_AD = *:1 SP;\n\tbuild tbl_bzero;\n\tSP = SP + 0x2;\n\t#Status bits are not affected\n}\n\n# POP.W SP - increment occurs after read but before write, and is therefore lost\n:POP^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & ad=0x0 & dest_Direct16_0_4 & as=0x3 & src_Direct16_8_4=0x1 & dest_Direct16_0_4=0x1 & tbl_wzero & AMASK) ... & DEST_W_AD ... {\n\tDEST_W_AD = *:2 (SP & AMASK); # Unaligned word memory accesses round down\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n}\n\n# POP.B SP - increment occurs after read but before write, and is therefore lost\n:POP^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & ad=0x0 & dest_Direct16_0_4 & as=0x3 & src_Direct16_8_4=0x1 & dest_Direct16_0_4=0x1 & tbl_bzero) ... & DEST_B_AD ... {\n\tDEST_B_AD = *:1 SP;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n}\n\n# POP.B PC - writes to PC are rounded down, but base instruction does not use postIncrementStore to handle this case\n:POP^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & ad=0x0 & dest_Direct16_0_4 & as=0x3 & src_Direct16_8_4=0x1 & dest_Direct16_0_4=0x0 & tbl_bzero) ... & DEST_B_AD ... {\n\tDEST_B_AD = *:1 SP;\n\tbuild tbl_bzero;\n\tSP = SP + 0x2;\n\tPC = PC & 0xFFFFFFFE:$(REG_SIZE);\n\tgoto [PC];\n\t#Status bits are not affected\n}\n\n# Return from subroutine\n:RET is ctx_haveext=0 & op16_12_4=0x4 & bow=0x0 & ad=0x0 & as=0x3 & dest_Direct16_0_4=0x0 & src_Direct16_8_4=0x1 & AMASK {\n\tPC = zext(*:2 (SP & AMASK)) & AMASK; # Stack pointer can be misaligned, and subsequent write to PC rounds to alignment\n\tSP = SP + 0x2;\n\treturn [PC];\n\t#Status bits are not affected\n}\n\n#------------------\n#\tSRC Word\n#------------------\n:MOV^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\tDEST_W_AD = SRC_W_AS;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n# SRC Byte\n#------------------\n:MOV^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\tDEST_B_AD = SRC_B_AS;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tADD: Add source to destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 1 0 1 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Increment word\n:INC^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(DEST_W_AD,1); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DEST_W_AD,1); \t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD + 0x1;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Increment byte\n:INC^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(DEST_B_AD,1); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DEST_B_AD,1); \t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD + 0x1;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Double increment word\n:INCD^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(DEST_W_AD,2); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DEST_W_AD,2); \t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD + 0x2;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Double increment byte\n:INCD^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(DEST_B_AD,2); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DEST_B_AD,2); \t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD + 0x2;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Rotate left arithmetic (left shift once) word\n:RLA^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(DEST_W_AD, DEST_W_AD); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DEST_W_AD, DEST_W_AD); \t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD + DEST_W_AD;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Rotate left arithmetic (left shift once) byte\n:RLA^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(DEST_B_AD, DEST_B_AD); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DEST_B_AD, DEST_B_AD); \t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD + DEST_B_AD;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:ADD^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = carry(SRC_W_AS, DEST_W_AD); \t \t# C Flag\n\ttmp_overflow:1 = scarry(SRC_W_AS, DEST_W_AD); \t# V Flag\n\t# Operation...\n\tDEST_W_AD = SRC_W_AS + DEST_W_AD;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:ADD^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = carry(SRC_B_AS, DEST_B_AD); \t \t# C Flag\n\ttmp_overflow:1 = scarry(SRC_B_AS, DEST_B_AD); \t# V Flag\n\t# Operation...\n\tDEST_B_AD = SRC_B_AS + DEST_B_AD;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tADDC: Add source and carry to destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 1 1 0 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Add carry to word\n:ADC^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = carry(DEST_W_AD,zext($(CARRY)));\t\t #C Flag\n \ttmp_overflow:1 = scarry(DEST_W_AD, zext($(CARRY))); #V Flag\n \t# Operation...\n\tDEST_W_AD = DEST_W_AD + zext($(CARRY));\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\tbuild postIncrementStore;\n}\n\n# Add carry to byte\n:ADC^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = carry(DEST_B_AD,$(CARRY));\t\t #C Flag\n \ttmp_overflow:1 = scarry(DEST_B_AD,$(CARRY)); #V Flag\n \t# Operation...\n\tDEST_B_AD = DEST_B_AD + $(CARRY);\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\tbuild postIncrementStore;\n}\n\n# Rotate word left through carry\n:RLC^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(DEST_W_AD,zext($(CARRY))) || carry(DEST_W_AD,DEST_W_AD + zext($(CARRY))));\t\t #C Flag\n \ttmp_overflow:1 = (scarry(DEST_W_AD,zext($(CARRY))) || scarry(DEST_W_AD,DEST_W_AD + zext($(CARRY)))); #V Flag\n \t# Operation...\n\tDEST_W_AD = DEST_W_AD + DEST_W_AD + zext($(CARRY));\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Rotate byte left through carry\n:RLC^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(DEST_B_AD, $(CARRY)) || carry(DEST_B_AD,DEST_B_AD + $(CARRY)));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(DEST_B_AD, $(CARRY)) || scarry(DEST_B_AD,DEST_B_AD + $(CARRY))); #V Flag\n \t# Operation...\n\tDEST_B_AD = DEST_B_AD + DEST_B_AD + $(CARRY);\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\nmacro addWithCarry(src, dest){\n local incoming_carry = zext($(CARRY));\n local sum_without_carry = src + dest;\n \n local tmp_carry:1 = carry(src, dest);\n tmp_carry = tmp_carry || carry(sum_without_carry, incoming_carry);\n \n local tmp_overflow:1 = scarry(src, dest);\n tmp_overflow = tmp_overflow ^^ scarry(sum_without_carry, incoming_carry);\n \n dest = sum_without_carry + incoming_carry;\n $(CARRY) = tmp_carry;\n $(OVERFLOW) = tmp_overflow;\n }\n\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:ADDC^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x6 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\taddWithCarry(SRC_W_AS,DEST_W_AD);\n\tbuild tbl_wzero;\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:ADDC^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x6 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\taddWithCarry(SRC_B_AS, DEST_B_AD);\n\tbuild tbl_bzero;\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tSUBC: Subtract source from destination (with carry)\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 0 1 1 1 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Subtract borrow from word\n:SBC^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x7 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\tbrw:2 = 1 - zext( $(CARRY) );\n\t$(CARRY) = (brw <= DEST_W_AD);\t\t# Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DEST_W_AD, brw);\t\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD - brw;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Subtract borrow from byte\n:SBC^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x7 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\tbrw:1 = 1 - $(CARRY);\n $(CARRY) = (brw <= DEST_B_AD); # Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DEST_B_AD, brw);\t\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD - brw;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\nmacro subtractWithCarry(dest, src){\n local incoming_carry = zext($(CARRY));\n local not_incoming_carry = zext(!($(CARRY)));\n local diff_without_carry = dest - src;\n \n local tmp_carry:1 = dest > src;\n tmp_carry = tmp_carry || (diff_without_carry < incoming_carry);\n \n local tmp_overflow:1 = sborrow(dest, src);\n tmp_overflow = tmp_overflow ^^ sborrow(diff_without_carry, not_incoming_carry);\n \n dest = diff_without_carry - not_incoming_carry;\n $(CARRY) = tmp_carry;\n $(OVERFLOW) = tmp_overflow;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:SUBC^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x7 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\tsubtractWithCarry(DEST_W_AD,SRC_W_AS);\n\tbuild tbl_wzero;\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:SUBC^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x7 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\tsubtractWithCarry(DEST_B_AD,SRC_B_AS);\n\tbuild tbl_bzero;\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tSUB: Subtract source from destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 0 0 0 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Decrement word\n:DEC^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (0x0 != DEST_W_AD);\t\t\t# C Flag\n\t$(OVERFLOW) = (0x8000 == DEST_W_AD);\t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD - 0x1;\t\t\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Decrement byte\n:DEC^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (0x0 != DEST_B_AD);\t\t\t# C Flag\n\t$(OVERFLOW) = (0x80 == DEST_B_AD);\t\t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD - 0x1;\t\t\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Double decrement word\n:DECD^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = ((0x0 != DEST_W_AD) && (0x1 != DEST_W_AD));\t\t\t# C Flag\n\t$(OVERFLOW) = ((0x8000 == DEST_W_AD) || (0x8001 == DEST_W_AD));\t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD - 0x2;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Double decrement byte\n:DECD^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = ((0x0 != DEST_B_AD) && (0x1 != DEST_B_AD));\t\t\t# C Flag\n\t$(OVERFLOW) = ((0x80 == DEST_B_AD) || (0x81 == DEST_B_AD));\t\t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD - 0x2;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:SUB^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x8 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (SRC_W_AS <= DEST_W_AD);\t\t# Carry is NOT set if there is a borrow\n\ttmp_overflow:1 = sborrow(DEST_W_AD, SRC_W_AS);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD - SRC_W_AS;\t\t\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:SUB^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x8 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (SRC_B_AS <= DEST_B_AD);\t\t# Carry is NOT set if there is a borrow\n\ttmp_overflow:1 = sborrow(DEST_B_AD, SRC_B_AS);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD - SRC_B_AS;\t\t\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tCMP: Compare (pretend to subtract) source from destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 0 0 1 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Test word\n:TST^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x9 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & postIncrement) ... & DEST_W_AD ... {\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\t# Operation Flags...\n\t$(CARRY) = 1;\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = 0;\t# V Flag\n\tbuild postIncrement;\n}\n\n# Test byte\n:TST^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x9 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & postIncrement) ... & DEST_B_AD ... {\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\t# Operation Flags...\n\t$(CARRY) = 1;\t\t\n\t$(OVERFLOW) = 0;\t\n\tbuild postIncrement;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:CMP^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x9 & bow=0x0 & postIncrement) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (SRC_W_AS <= DEST_W_AD);\t\t# Carry is NOT set if there is a borrow\n\ttmp_overflow:1 = sborrow(DEST_W_AD, SRC_W_AS);\t# V Flag\n\t# Operation...\n\tresult:2 = (DEST_W_AD - SRC_W_AS);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:CMP^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x9 & bow=0x1 & postIncrement) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (SRC_B_AS <= DEST_B_AD);\t\t# Carry is NOT set if there is a borrow\n\ttmp_overflow:1 = sborrow(DEST_B_AD, SRC_B_AS);\t# V Flag\n\t# Operation...\n\tresult:1 = (DEST_B_AD - SRC_B_AS);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n\n###################################################################################\n#\n#\tDADD: Decimal add source to destination (with carry)\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 0 1 0 | source | Ad | B/W | As | destination | \n#----------------------------------------------------------------------------------------------------------------\n# These decimal add instructions appear to lack supporting BCD p-code operations to easily handle the operation and flags.\n#----------------------------------------------------------------------------------------------------------------\n#-----------------------\n# Emulated instructions\n#-----------------------\n# Decimal add carry to word\n:DADC^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xA & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation...\n\tdst_nibble0:2 = DEST_W_AD & 0xf;\n\tdst_nibble1:2 = (DEST_W_AD >> 4) & 0xf;\n\tdst_nibble2:2 = (DEST_W_AD >> 8) & 0xf;\n\tdst_nibble3:2 = (DEST_W_AD >> 12) & 0xf;\n\n\tres_nibble0:2 = dst_nibble0 + zext($(CARRY));\n\tcarry_nibble0:2 = zext(res_nibble0 > 9);\n\tres_nibble0 = (res_nibble0 - carry_nibble0 * 10) & 0xf;\n\n\tres_nibble1:2 = dst_nibble1 + carry_nibble0;\n\tcarry_nibble1:2 = zext(res_nibble1 > 9);\n\tres_nibble1 = (res_nibble1 - carry_nibble1 * 10) & 0xf;\n\n\tres_nibble2:2 = dst_nibble2 + carry_nibble1;\n\tcarry_nibble2:2 = zext(res_nibble2 > 9);\n\tres_nibble2 = (res_nibble2 - carry_nibble2 * 10) & 0xf;\n\n\tres_nibble3:2 = dst_nibble3 + carry_nibble2;\n\ttmp_carry:1 = res_nibble3 > 9;\n\tcarry_nibble3:2 = zext(res_nibble3 > 9);\n\tres_nibble3 = (res_nibble3 - carry_nibble3 * 10) & 0xf;\n\n\ttmp_res:2 = (res_nibble3 << 12) + (res_nibble2 << 8) + (res_nibble1 << 4) + res_nibble0;\n\tDEST_W_AD = tmp_res;\n\n\tbuild tbl_wzero;\n\t# Operation Flags...\n\t$(CARRY) = tmp_carry;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n# Decimal add carry to byte\n:DADC^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xA & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation...\n\tdst_nibble0:1 = DEST_B_AD & 0xf;\n\tdst_nibble1:1 = (DEST_B_AD >> 4) & 0xf;\n\n\tres_nibble0:1 = dst_nibble0 + zext($(CARRY));\n\tcarry_nibble0:1 = zext(res_nibble0 > 9);\n\tres_nibble0 = (res_nibble0 - carry_nibble0 * 10) & 0xf;\n\n\tres_nibble1:1 = dst_nibble1 + carry_nibble0;\n\ttmp_carry:1 = res_nibble1 > 9;\n\tcarry_nibble1:1 = zext(res_nibble1 > 9);\n\tres_nibble1 = (res_nibble1 - carry_nibble1 * 10) & 0xf;\n\n\ttmp_res:1 = (res_nibble1 << 4) + res_nibble0;\n\tDEST_B_AD = tmp_res;\n\n\tbuild tbl_bzero;\n\t# Operation Flags...\n\t$(CARRY) = tmp_carry;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:DADD^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xA & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation...\n\tsrc_nibble0:2 = SRC_W_AS & 0xf;\n\tsrc_nibble1:2 = (SRC_W_AS >> 4) & 0xf;\n\tsrc_nibble2:2 = (SRC_W_AS >> 8) & 0xf;\n\tsrc_nibble3:2 = (SRC_W_AS >> 12) & 0xf;\n\tdst_nibble0:2 = DEST_W_AD & 0xf;\n\tdst_nibble1:2 = (DEST_W_AD >> 4) & 0xf;\n\tdst_nibble2:2 = (DEST_W_AD >> 8) & 0xf;\n\tdst_nibble3:2 = (DEST_W_AD >> 12) & 0xf;\n\n\tres_nibble0:2 = src_nibble0 + dst_nibble0 + zext($(CARRY));\n\tcarry_nibble0:2 = zext(res_nibble0 > 9);\n\tres_nibble0 = (res_nibble0 - carry_nibble0 * 10) & 0xf;\n\n\tres_nibble1:2 = src_nibble1 + dst_nibble1 + carry_nibble0;\n\tcarry_nibble1:2 = zext(res_nibble1 > 9);\n\tres_nibble1 = (res_nibble1 - carry_nibble1 * 10) & 0xf;\n\n\tres_nibble2:2 = src_nibble2 + dst_nibble2 + carry_nibble1;\n\tcarry_nibble2:2 = zext(res_nibble2 > 9);\n\tres_nibble2 = (res_nibble2 - carry_nibble2 * 10) & 0xf;\n\n\tres_nibble3:2 = src_nibble3 + dst_nibble3 + carry_nibble2;\n\ttmp_carry:1 = res_nibble3 > 9;\n\tcarry_nibble3:2 = zext(res_nibble3 > 9);\n\tres_nibble3 = (res_nibble3 - carry_nibble3 * 10) & 0xf;\n\n\ttmp_res:2 = (res_nibble3 << 12) + (res_nibble2 << 8) + (res_nibble1 << 4) + res_nibble0;\n\tDEST_W_AD = tmp_res;\n\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:DADD^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xA & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation...\n\tsrc_nibble0:1 = SRC_B_AS & 0xf;\n\tsrc_nibble1:1 = (SRC_B_AS >> 4) & 0xf;\n\tdst_nibble0:1 = DEST_B_AD & 0xf;\n\tdst_nibble1:1 = (DEST_B_AD >> 4) & 0xf;\n\n\tres_nibble0:1 = src_nibble0 + dst_nibble0 + zext($(CARRY));\n\tcarry_nibble0:1 = zext(res_nibble0 > 9);\n\tres_nibble0 = (res_nibble0 - carry_nibble0 * 10) & 0xf;\n\n\tres_nibble1:1 = src_nibble1 + dst_nibble1 + carry_nibble0;\n\ttmp_carry:1 = res_nibble1 > 9;\n\tcarry_nibble1:1 = zext(res_nibble1 > 9);\n\tres_nibble1 = (res_nibble1 - carry_nibble1 * 10) & 0xf;\n\n\ttmp_res:1 = (res_nibble1 << 4) + res_nibble0;\n\tDEST_B_AD = tmp_res;\n\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (tmp_res s< 0x0);\t\t# S Flag\n\t$(ZERO) = (tmp_res == 0x0);\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tBIT: Test bits of source AND destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 0 1 1 | source | Ad | B/W | As | destination | \n#------------------\n#\t16 bit SRC Word\n#------------------\n:BIT^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xB & bow=0x0 & postIncrement) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation...\n\tresult:2 = DEST_W_AD & SRC_W_AS;\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Result Flags...\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:BIT^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xB & bow=0x1 & postIncrement) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation...\n\tresult:1 = DEST_B_AD & SRC_B_AS;\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Result Flags...\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n\n###################################################################################\n#\n#\tBIC: Bit clear (dest &= ~src)\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 1 0 0 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Clear carry bit\n:CLRC\tis ctx_haveext=0 & op16_12_4=0xC & as=0x1 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore {\n\t$(CARRY) = 0;\n\tbuild postIncrementStore;\n}\n\n# Clear sign bit\n:CLRN\tis ctx_haveext=0 & op16_12_4=0xC & as=0x2 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore {\n\t$(SIGN) = 0;\n\tbuild postIncrementStore;\n}\n\n# Clear zero bit\n:CLRZ\tis ctx_haveext=0 & op16_12_4=0xC & as=0x2 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore {\n\t$(ZERO) = 0;\n\tbuild postIncrementStore;\n}\n\n# Disable interrupts\n:DINT\tis ctx_haveext=0 & op16_12_4=0xC & as=0x3 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & postIncrementStore {\n\t$(GIE) = 0;\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:BIC^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xC & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\tDEST_W_AD = (~SRC_W_AS) & DEST_W_AD;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:BIC^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xC & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\tDEST_B_AD = (~SRC_B_AS) & DEST_B_AD;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tBIS: Bit set (logical OR)\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 1 0 1 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Enable interrupts\n:EINT\tis ctx_haveext=0 & op16_12_4=0xD & as=0x3 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & postIncrementStore {\n\t$(GIE) = 1;\n\tbuild postIncrementStore;\n}\n\n# Set carry bit\n:SETC \tis ctx_haveext=0 & (op16_12_4=0xD & as=0x1 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore) {\n\t$(CARRY) = 1;\n\tbuild postIncrementStore;\n}\n\n# Set sign bit\n:SETN \tis ctx_haveext=0 & (op16_12_4=0xD & as=0x2 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore) {\n\t$(SIGN) = 1;\n\tbuild postIncrementStore;\n}\n\n# Set zero bit\n:SETZ \tis ctx_haveext=0 & (op16_12_4=0xD & as=0x2 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore) {\n\t$(ZERO) = 1;\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:BIS^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xD & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\tDEST_W_AD = SRC_W_AS | DEST_W_AD;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:BIS^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xD & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\tDEST_B_AD = SRC_B_AS | DEST_B_AD;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n\n\n###################################################################################\n#\n#\tXOR: Exclusive or source with destination\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 1 1 0 | source | Ad | B/W | As | destination | \n#-----------------------\n# Emulated instructions\n#-----------------------\n# Invert word\n:INV^\".W\" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xE & as=0x3 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = (DEST_W_AD s< 0x0);\t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD ^ 0xFFFF;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DEST_W_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n# Invert byte\n:INV^\".B\" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xE & as=0x3 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = (DEST_B_AD s< 0x0);\t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD ^ 0xFF;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DEST_B_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Word\n#------------------\n:XOR^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xE & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_overflow:1 = ((DEST_W_AD s< 0x0) && (SRC_W_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tDEST_W_AD = DEST_W_AD ^ SRC_W_AS;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (DEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_W_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DEST_W_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:XOR^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xE & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_overflow:1 = ((DEST_B_AD s< 0x0) && (SRC_B_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tDEST_B_AD = DEST_B_AD ^ SRC_B_AS;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(OVERFLOW) = tmp_overflow;\n\t$(SIGN) = (DEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DEST_B_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DEST_B_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n\n###################################################################################\n#\n#\tAND: Logical AND source with destination (dest &= src)\n# ------------------------------------------------------------------------------\n#\t| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |\n#\t------------------------------------------------------------------------------\n#\t| 1 1 1 1 | source | Ad | B/W | As | destination | \n#------------------\n#\t16 bit SRC Word\n#------------------\n:AND^\".W\" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xF & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {\n\t# Operation...\n\tresult:2 = DEST_W_AD & SRC_W_AS;\n\tDEST_W_AD = result;\n\tbuild tbl_wzero;\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n\n#------------------\n#\t16 bit SRC Byte\n#------------------\n:AND^\".B\" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xF & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {\n\t# Operation...\n\tresult:1 = DEST_B_AD & SRC_B_AS;\n\tDEST_B_AD = result;\n\tbuild tbl_bzero;\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI430X.sinc", "content": "###################################################################################\n#\n#\t20bit Address Instructions\n#\n# The original way of using sub-tables to breakout the addressing modes does not\n# work for these instructions\n\n#constructor recognizing the presence of an extension word\n:^instruction\t\t\t\t\t\t\tis opext_11_5=0x3 & ctx_haveext=0 & dest_0_4 & src_ext & al & zc & ad; instruction [ ctx_haveext=1; ctx_ctregdest=dest_0_4; ctx_regsrc=src_ext; ctx_al=al; ctx_num=ad; ctx_zc=zc;] { build instruction;}\n\n\n#:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & as=1 & src_8_4=3 [ctx_haveext=2;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & as=1 & src_8_4=3 [ctx_haveext=7;] {build instruction;} #replacment substituting second of haveext=2. NOTE: as=1 precludes first \n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & as=1 [ctx_haveext=7;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & as=3 & src_8_4=0 [ctx_haveext=7;] {build instruction;}\n#:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction [ctx_haveext=2;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & as=0 & ad=0 [ctx_haveext=3;] {build instruction;} #replacement substituting first of haveext=2\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction [ctx_haveext=7;] {build instruction;} #replacement substituting second of haveext=2\n\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & op16_7_9=0x23 & as=0 [ctx_haveext=3;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & op16_7_9=0x21 & as=0 [ctx_haveext=3;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & op16_12_4=0x1 & as=1 & reg16_0_4=3 [ctx_haveext=3;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & op16_12_4=0x1 & as=1 [ctx_haveext=7;] {build instruction;}\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=1 & instruction & op16_12_4=0x1 & as=3 & reg16_0_4=0 [ctx_haveext=7;] {build instruction;}\n\n# removed haveext=2\n#:^instruction\t\t\t\t\t\t\tis ctx_haveext=2 & instruction & as=0 & ad=0 [ctx_haveext=3;] {build instruction;}\n#:^instruction\t\t\t\t\t\t\tis ctx_haveext=2 & instruction [ctx_haveext=7;] {build instruction;}\n\n\n\n:^instruction\t\t\t\t\t\t\tis ctx_haveext=3 & instruction & ctx_num=0 & ctx_ctregdest=0 [ctx_haveext=4;] { CNT = 0;build instruction; }\n:\"RPT #\"^val^\" { \"^instruction\t\t\tis ctx_haveext=3 & instruction & ctx_num=0 & ctx_ctregdest [ctx_haveext=4; val = ctx_ctregdest+1;] { CNT = ctx_ctregdest;build instruction;}\n:\"RPT \"^ctx_repreg^\" { \"^instruction\tis ctx_haveext=3 & instruction & ctx_num=1 & ctx_repreg [ctx_haveext=4;] { CNT = zext(ctx_repreg[0,4]); build instruction;}\n\n\n# 20bit address mode sub tables\nAbs20: val\t\t\t\t\t\tis ctx_ctregdest & imm_0_16 [ val=(ctx_ctregdest << 16) | imm_0_16;] {export *[const]:3 val;}\nAbs20s: val\t\t\t\t\t\tis ctx_ctregdests & imm_0_16 [ val=(ctx_ctregdests << 16) | imm_0_16;] {export *[const]:3 val;}\nAbs20add: val\t\t\t\t\tis ctx_ctregdest & imm_0_16 [ val=(ctx_ctregdest << 16) | imm_0_16;] {export *:4 val;}\n\nIMM4: val\t\t\t\t\tis imm_4_4 [val = imm_4_4+1;] {export *[const]:1 val;}\nNUM2: val\t\t\t\t\tis rrn [ val = rrn+1;] {export *[const]:1 val;}\n\nXREG_B_AS: DST8_0_4 \t\t\t \t\t is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn):\nXREG_B_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:1 tmp;}\nXREG_B_AS: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_B_AS: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_B_AS: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic\nXREG_B_AS: \"#\"^indexExtWord16_0_16 \t\t is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16; } # Immediate\nXREG_B_AS: \"&\"^indexExtWord16_0_16 \t\t is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute\nXREG_B_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;}\t\t# Constant\nXREG_B_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;}\t\t# Constant\nXREG_B_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:1;}\t\t# Constant\nXREG_B_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:1;}\t\t# Constant\nXREG_B_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:1;}\t\t# Constant\nXREG_B_AS: \"#-1\" \t\t\t\t\t\t is\treg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1;} \t# Constant\t\n\nXRREG_B_AS: DST8_0_4 \t\t\t \t\t is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn):\nXRREG_B_AS: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_B_AS: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXRREG_B_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;}\t\t# Constant\nXRREG_B_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;}\t\t# Constant\nXRREG_B_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:1;}\t\t# Constant\nXRREG_B_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:1;}\t\t# Constant\nXRREG_B_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:1;}\t\t# Constant\nXRREG_B_AS: \"#-1\" \t\t\t\t\t\t is\treg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1;} \t# Constant\t\n\nXREG_W_AS: DST16_0_4 \t\t\t \t\t is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn):\nXREG_W_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:2 tmp;}\nXREG_W_AS: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_W_AS: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_W_AS: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:2 labelCalc; } # Symbolic\nXREG_W_AS: \"#\"^indexExtWord16_0_16 \t\t is reg16_0_4=0x0 & as=0x3 & bow=0x0 ; indexExtWord16_0_16 {export *[const]:2 indexExtWord16_0_16; } # Immediate\nXREG_W_AS: \"&\"^indexExtWord16_0_16 \t\t is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 {export *:2 indexExtWord16_0_16; } # Absolute\nXREG_W_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x0 { export 4:2;}\t\t# Constant\nXREG_W_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x0 { export 8:2;}\t\t# Constant\nXREG_W_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x0 { export 0:2;}\t\t# Constant\nXREG_W_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x0 { export 1:2;}\t\t# Constant\nXREG_W_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x0 { export 2:2;}\t\t# Constant\nXREG_W_AS: \"#-1\" \t\t\t\t\t \t is\treg16_0_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2;} \t # Constant\n\nXRREG_W_AS: DST16_0_4 \t\t\t \t\t is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn):\nXRREG_W_AS: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_W_AS: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXRREG_W_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x0 { export 4:2;}\t\t# Constant\nXRREG_W_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x0 { export 8:2;}\t\t# Constant\nXRREG_W_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x0 { export 0:2;}\t\t# Constant\nXRREG_W_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x0 { export 1:2;}\t\t# Constant\nXRREG_W_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x0 { export 2:2;}\t\t# Constant\nXRREG_W_AS: \"#-1\" \t\t\t\t\t \t is\treg16_0_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2;} \t # Constant\n\nXREG_A_AS: dest_0_4\t\t\t\t\t\t is dest_0_4 & as=0 & bow=0x1 {export dest_0_4;}\nXREG_A_AS: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:$(REG_SIZE) tmp;}\nXREG_A_AS: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_A_AS: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_A_AS: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | indexExtWord16_0_16); ] {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXREG_A_AS: \"#\"^val \t\t\t\t\t\t is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_ctregdests << 16) | indexExtWord16_0_16; ] {export *[const]:$(REG_SIZE) val; } # Immediate\nXREG_A_AS: \"&\"^val \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_ctregdest << 16) | indexExtWord16_0_16; ] {export *:$(REG_SIZE) val; } # Absolute\nXREG_A_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE);}\t\t# Constant\nXREG_A_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE);}\t\t# Constant\nXREG_A_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE);}\t\t# Constant\nXREG_A_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE);}\t\t# Constant\nXREG_A_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE);}\t\t# Constant\nXREG_A_AS: \"#-1\" \t\t\t\t\t\t is\treg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE);} \t# Constant\t\n\nXRREG_A_AS: dest_0_4\t\t\t\t\t\t is dest_0_4 & as=0 & bow=0x1 {export dest_0_4;}\nXRREG_A_AS: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_A_AS: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXRREG_A_AS: \"#4\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE);}\t\t# Constant\nXRREG_A_AS: \"#8\" \t\t\t\t\t\t is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE);}\t\t# Constant\nXRREG_A_AS: \"#0\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE);}\t\t# Constant\nXRREG_A_AS: \"#1\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE);}\t\t# Constant\nXRREG_A_AS: \"#2\" \t\t\t\t\t\t is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE);}\t\t# Constant\nXRREG_A_AS: \"#-1\" \t\t\t\t\t\t is\treg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE);} \t# Constant\t\n\nXREG_B_AS_DEST: DST8_0_4 \t\t\t \t is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn):\nXREG_B_AS_DEST: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:1 tmp;}\nXREG_B_AS_DEST: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_B_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_B_AS_DEST: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic\nXREG_B_AS_DEST: \"&\"^indexExtWord16_0_16 \t is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute\n\nXRREG_B_AS_DEST: DST8_0_4 \t\t\t \t is DST8_0_4 & as=0x0 & reg_Direct16_0_4 & bow=0x1 { ztmp:1 = DST8_0_4; reg_Direct16_0_4=0; DST8_0_4 = ztmp; export DST8_0_4;} # Word/Register Direct (Rn):\nXRREG_B_AS_DEST: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_B_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\n\nXREG_W_AS_DEST: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:2 tmp;}\nXREG_W_AS_DEST: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_W_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_W_AS_DEST: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:2 labelCalc; } # Symbolic\nXREG_W_AS_DEST: \"&\"^indexExtWord16_0_16 \t is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 {export *:2 indexExtWord16_0_16; } # Absolute\n\nXRREG_W_AS_DEST: DST16_0_4 \t\t\t is DST16_0_4 & as=0x0 & reg_Direct16_0_4 & bow=0x0 {ztmp:2 = DST16_0_4; reg_Direct16_0_4=0; DST16_0_4 = ztmp;export DST16_0_4;} # Word/Register Direct (Rn):\nXRREG_W_AS_DEST: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_W_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\n\nXREG_A_AS_DEST: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:$(REG_SIZE) tmp;}\nXREG_A_AS_DEST: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_A_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_A_AS_DEST: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | indexExtWord16_0_16); ] {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXREG_A_AS_DEST: \"&\"^val \t\t\t\t\t is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_ctregdest << 16) | indexExtWord16_0_16; ] {export *:$(REG_SIZE) val; } # Absolute\n\nXRREG_A_AS_DEST: dest_0_4\t\t\t\t\t\t is dest_0_4 & as=0 & bow=0x1 {export dest_0_4;}\nXRREG_A_AS_DEST: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_A_AS_DEST: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\n\nXREG_A_AS_DEST2: indexExtWord16_0_16s^\"(\"^reg_Indexed16_0_4^\")\" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + indexExtWord16_0_16s; export *:$(REG_SIZE) tmp;}\nXREG_A_AS_DEST2: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXREG_A_AS_DEST2: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXREG_A_AS_DEST2: labelCalc \t\t\t\t\t is reg16_0_4=0x0 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 [labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | indexExtWord16_0_16); ] {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXREG_A_AS_DEST2: \"&\"^val \t\t\t\t\t is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 [val=(ctx_ctregdest << 16) | indexExtWord16_0_16; ] {export *:$(REG_SIZE) val; } # Absolute\n\nXRREG_A_AS_DEST2: dest_0_4\t\t\t\t\t\t is dest_0_4 & as=0 & bow=0x0 {export dest_0_4;}\nXRREG_A_AS_DEST2: \"@\"^reg_InDirect16_0_4 \t\t is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):\nXRREG_A_AS_DEST2: \"@\"^reg_InDirect16_0_4^\"+\"\t is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\n\nXSRC_B_AS: SRC8_8_4 \t\t\t \t\t is SRC8_8_4 & as=0x0 & bow=0x1 { export SRC8_8_4;} # Word/Register Direct (Rn):\nXSRC_B_AS: indexExtWord16_0_16s^\"(\"^src_Indexed16_8_4^\")\" is src_Indexed16_8_4 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = src_Indexed16_8_4 + indexExtWord16_0_16s; export *:1 tmp;}\nXSRC_B_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nXSRC_B_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXSRC_B_AS: labelCalc \t\t\t\t is src16_8_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic\nXSRC_B_AS: \"#\"^indexExtWord16_0_16 \t is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate\nXSRC_B_AS: \"&\"^indexExtWord16_0_16 \t is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute\nXSRC_B_AS: \"#4\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; }\t\t# Constant\nXSRC_B_AS: \"#8\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; }\t\t# Constant\nXSRC_B_AS: \"#0\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:1; }\t\t# Constant\nXSRC_B_AS: \"#1\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:1; }\t\t# Constant\nXSRC_B_AS: \"#2\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:1; }\t\t# Constant\nXSRC_B_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1; } \t# Constant\n\nXRSRC_B_AS: SRC8_8_4 \t\t\t \t\t is SRC8_8_4 & as=0x0 & bow=0x1 { export SRC8_8_4;} # Word/Register Direct (Rn):\nXRSRC_B_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nXRSRC_B_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXRSRC_B_AS: \"#4\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; }\t\t# Constant\nXRSRC_B_AS: \"#8\" \t\t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; }\t\t# Constant\nXRSRC_B_AS: \"#0\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:1; }\t\t# Constant\nXRSRC_B_AS: \"#1\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:1; }\t\t# Constant\nXRSRC_B_AS: \"#2\" \t\t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:1; }\t\t# Constant\nXRSRC_B_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1; } \t# Constant\n\n\nXSRC_W_AS: SRC16_8_4 \t\t\t \t is SRC16_8_4 & as=0x0 & bow=0x0 {export SRC16_8_4;} # Word/Register Direct (Rn):\nXSRC_W_AS: indexExtWord16_0_16s^\"(\"^src_Indexed16_8_4^\")\" is src_Indexed16_8_4 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s {tmp:$(REG_SIZE) = src_Indexed16_8_4 + indexExtWord16_0_16s; export *:2 tmp;}\nXSRC_W_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nXSRC_W_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXSRC_W_AS: labelCalc \t\t\t\t is src16_8_4=0x0 & as=0x1 & bow=0x0 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:2 labelCalc; } # Symbolic\nXSRC_W_AS: \"#\"^indexExtWord16_0_16 \t is src16_8_4=0x0 & as=0x3 & bow=0x0 ; indexExtWord16_0_16 {export *[const]:2 indexExtWord16_0_16; } # Immediate\nXSRC_W_AS: \"&\"^indexExtWord16_0_16 \t is src16_8_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 {export *:2 indexExtWord16_0_16; } # Absolute\nXSRC_W_AS: \"#4\" \t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x0 { export 4:2; }\t\t# Constant\nXSRC_W_AS: \"#8\" \t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x0 { export 8:2; }\t\t# Constant\nXSRC_W_AS: \"#0\" \t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x0 { export 0:2; }\t\t# Constant\nXSRC_W_AS: \"#1\" \t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x0 { export 1:2; }\t\t# Constant\nXSRC_W_AS: \"#2\" \t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x0 { export 2:2; }\t\t# Constant\nXSRC_W_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2; } \t# Constant\t\n\nXRSRC_W_AS: SRC16_8_4 \t\t\t \t is SRC16_8_4 & as=0x0 & bow=0x0 {export SRC16_8_4;} # Word/Register Direct (Rn):\nXRSRC_W_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nXRSRC_W_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXRSRC_W_AS: \"#4\" \t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x0 { export 4:2; }\t\t# Constant\nXRSRC_W_AS: \"#8\" \t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x0 { export 8:2; }\t\t# Constant\nXRSRC_W_AS: \"#0\" \t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x0 { export 0:2; }\t\t# Constant\nXRSRC_W_AS: \"#1\" \t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x0 { export 1:2; }\t\t# Constant\nXRSRC_W_AS: \"#2\" \t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x0 { export 2:2; }\t\t# Constant\nXRSRC_W_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2; } \t# Constant\t\n\nXSRC_A_AS: src_8_4 \t\t\t \t\t is src_8_4 & as=0x0 & bow=0x1 { export src_8_4;} # Word/Register Direct (Rn):\nXSRC_A_AS: val^\"(\"^src_Indexed16_8_4^\")\" is src_Indexed16_8_4 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_regsrcs << 16) | indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = src_Indexed16_8_4 + val; export *:$(REG_SIZE) tmp;}\nXSRC_A_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nXSRC_A_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXSRC_A_AS: labelCalc \t\t\t\t is src16_8_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [labelCalc = inst_start + 4 + ((ctx_regsrcs << 16) | indexExtWord16_0_16); ] {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXSRC_A_AS: \"#\"^val \t \t\t\t\t is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_regsrcs << 16) | indexExtWord16_0_16; ] {export *[const]:$(REG_SIZE) val; } # Immediate\nXSRC_A_AS: \"&\"^val \t \t\t\t\t is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_regsrc << 16) | indexExtWord16_0_16; ] {export *:$(REG_SIZE) val; } # Absolute\nXSRC_A_AS: \"#4\" \t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE); }\t\t# Constant\nXSRC_A_AS: \"#8\" \t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE); }\t\t# Constant\nXSRC_A_AS: \"#0\" \t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE); }\t\t# Constant\nXSRC_A_AS: \"#1\" \t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE); }\t\t# Constant\nXSRC_A_AS: \"#2\" \t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE); }\t\t# Constant\nXSRC_A_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE); } \t# Constant\t\n\nXRSRC_A_AS: src_8_4 \t\t\t \t\t is src_8_4 & as=0x0 & bow=0x1 { export src_8_4;} # Word/Register Direct (Rn):\nXRSRC_A_AS: \"@\"^src_InDirect16_8_4 \t is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect (@Rn):\nXRSRC_A_AS: \"@\"^src_InDirect16_8_4^\"+\" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):\t\nXRSRC_A_AS: \"#4\" \t\t\t\t\t is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE); }\t\t# Constant\nXRSRC_A_AS: \"#8\" \t\t\t\t\t is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE); }\t\t# Constant\nXRSRC_A_AS: \"#0\" \t\t\t\t\t is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE); }\t\t# Constant\nXRSRC_A_AS: \"#1\" \t\t\t\t\t is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE); }\t\t# Constant\nXRSRC_A_AS: \"#2\" \t\t\t\t\t is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE); }\t\t# Constant\nXRSRC_A_AS: \"#-1\" \t\t\t\t\t is\tsrc16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE); } \t# Constant\t\n\nXDEST_B_AD: DST8_0_4 \t\t \t\t is DST8_0_4 & ad=0x0 & bow=0x1\n { export DST8_0_4; } # Word/Register Direct (Rn):\nXDEST_B_AD: indexExtWord16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16s\n { tmp:$(REG_SIZE) = dest_Indexed16_0_4 + indexExtWord16_0_16s; export *:1 tmp;}\nXDEST_B_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n { tmp:$(REG_SIZE) = dest_Indexed16_0_4 + indexExt2Word16_0_16s; export *:1 tmp;}\nXDEST_B_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n { tmp:$(REG_SIZE) = dest_Indexed16_0_4 + indexExt2Word16_0_16s; export *:1 tmp;}\nXDEST_B_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ]\n { export *:1 labelCalc; } # Symbolic\nXDEST_B_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 6 + indexExt2Word16_0_16s; ]\n {export *:1 labelCalc; } # Symbolic\nXDEST_B_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 6 + indexExt2Word16_0_16s; ]\n {export *:1 labelCalc; } # Symbolic\nXDEST_B_AD: \"&\"^indexExtWord16_0_16 \t is dest=0x2 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16\n {export *:1 indexExtWord16_0_16; } # Absolute\nXDEST_B_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {export *:1 indexExt2Word16_0_16; } # Absolute\nXDEST_B_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {export *:1 indexExt2Word16_0_16; } # Absolute\n\n\nXDEST_W_AD: DST16_0_4 \t\t \t\t is DST16_0_4 & ad=0x0 & bow=0x0\n {export DST16_0_4;} # Word/Register Direct (Rn):\nXDEST_W_AD: indexExtWord16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 ; indexExtWord16_0_16s\n {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + indexExtWord16_0_16s; export *:2 tmp;}\nXDEST_W_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + indexExt2Word16_0_16s; export *:2 tmp;}\nXDEST_W_AD: indexExt2Word16_0_16s^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s\n {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + indexExt2Word16_0_16s; export *:2 tmp;}\nXDEST_W_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x0 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ]\n {export *:2 labelCalc; } # Symbolic\nXDEST_W_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 6 + indexExt2Word16_0_16s; ]\n {export *:2 labelCalc; } # Symbolic\nXDEST_W_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 6 + indexExt2Word16_0_16s; ]\n {export *:2 labelCalc; } # Symbolic\nXDEST_W_AD: \"&\"^indexExtWord16_0_16 \t is dest=0x2 & ad=0x1 & bow=0x0 ; indexExtWord16_0_16\n {export *:2 indexExtWord16_0_16; } # Absolute\nXDEST_W_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {export *:2 indexExt2Word16_0_16; } # Absolute\nXDEST_W_AD: \"&\"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16\n {export *:2 indexExt2Word16_0_16; } # Absolute\n\nXDEST_A_AD: dest_0_4 \t\t \t\t is dest_0_4 & ad=0x0 & bow=0x1\n { export dest_0_4; } # Word/Register Direct (Rn):\nXDEST_A_AD: val^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_ctregdests << 16) | indexExtWord16_0_16; ]\n {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + val; export *:$(REG_SIZE) tmp;}\nXDEST_A_AD: val^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16 [val=(ctx_ctregdests << 16) | indexExt2Word16_0_16; ]\n {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + val; export *:$(REG_SIZE) tmp;}\nXDEST_A_AD: val^\"(\"^dest_Indexed16_0_4^\")\" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16 [val=(ctx_ctregdests << 16) | indexExt2Word16_0_16; ]\n {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + val; export *:$(REG_SIZE) tmp;}\nXDEST_A_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16 [labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | indexExtWord16_0_16); ]\n {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXDEST_A_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16 [labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | indexExt2Word16_0_16); ]\n {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXDEST_A_AD: labelCalc \t\t\t\t is dest=0x0 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16 [labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | indexExt2Word16_0_16); ]\n {export *:$(REG_SIZE) labelCalc; } # Symbolic\nXDEST_A_AD: \"&\"^val \t \t\t\t is dest=0x2 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16 [val=(ctx_ctregdest << 16) | indexExtWord16_0_16; ]\n {export *:$(REG_SIZE) val; } # Absolute\nXDEST_A_AD: \"&\"^val \t\t\t\t is dest=0x2 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16 [val=(ctx_ctregdest << 16) | indexExt2Word16_0_16; ]\n {export *:$(REG_SIZE) val; } # Absolute\nXDEST_A_AD: \"&\"^val \t\t\t\t is dest=0x2 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16 [val=(ctx_ctregdest << 16) | indexExt2Word16_0_16; ]\n {export *:$(REG_SIZE) val; } # Absolute\n\n#Use repeat_carry with a build directive at the beginning of a RPT loop\n\n#use existing value of carry bit\nrepeat_carry: is ctx_zc = 0 {} \n\n#in this case the repeated instruction uses 0 as the value of the carry bit\n#after repeated instruction executes, value of carry bit is defined by the result of\n#last operation, so building this constructor at the beginning of RPT loop can accurately\n#model the semantics\nrepeat_carry: is ctx_zc = 1 {$(CARRY) = 0;} \n\nmacro setaddflags(ans, in1, in2)\n{\n\ttmp1:$(REG_SIZE) = zext(in1[0,20]);\n\ttmp2:$(REG_SIZE) = zext(in2[0,20]);\n\ttmp1 = tmp1 + tmp2;\n\t$(CARRY) = tmp1 > 0xFFFFF;\n\t$(OVERFLOW) = ((in1 s>= 0) & (in2 s>= 0) & (ans s< 0)) | ((in1 s< 0) & (in2 s< 0) & (ans s>= 0));\n\t$(SIGN) = (ans s< 0);\n\t$(ZERO) = (ans == 0);\n}\n\nmacro setsubflags(ans, in1, in2)\n{\n\ttmp1:$(REG_SIZE) = zext(in1[0,20]);\n\ttmp2:$(REG_SIZE) = zext(in2[0,20]);\n\t$(CARRY) = tmp1 > tmp2;\n\t$(OVERFLOW) = ((in1 s< 0) & (in2 s>= 0) & (ans s< 0)) | ((in1 s>= 0) & (in2 s< 0) & (ans s>= 0));\n\t$(SIGN) = (ans s< 0);\n\t$(ZERO) = (ans == 0);\n}\n\n#################\n#\n# Subtables for the pushm/popm variants.\n# In memory, the 20 bit regs take up 4 bytes with all the uppers being 0.\n# However, to get some of the math to work, the 20bit regs are sign extended when reading from mem.\n\nPUSHAR0:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR0:\t\t\t\t\tis ctx_mreg=0x0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = inst_start & 0xFFFFF;\n}\n\nPUSHAR1:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR1:\t\t\t\t\tis PUSHAR0 {build PUSHAR0;}\nPUSHAR1:\t\t\t\t\tis ctx_mreg=0x1 & PUSHAR0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = SP & 0xFFFF;\n\tbuild PUSHAR0;\n}\n\nPUSHAR2:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR2:\t\t\t\t\tis PUSHAR1 {build PUSHAR1;}\nPUSHAR2:\t\t\t\t\tis ctx_mreg=0x2 & PUSHAR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = SR & 0xFFFF;\n\tbuild PUSHAR1;\n}\n\nPUSHAR3:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR3:\t\t\t\t\tis PUSHAR2 {build PUSHAR2;}\nPUSHAR3:\t\t\t\t\tis ctx_mreg=0x3 & PUSHAR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R3 & 0xFFFFF;\n\tbuild PUSHAR2;\n}\n\nPUSHAR4:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR4:\t\t\t\t\tis PUSHAR3 {build PUSHAR3;}\nPUSHAR4:\t\t\t\t\tis ctx_mreg=0x4 & PUSHAR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R4 & 0xFFFFF;\n\tbuild PUSHAR3;\n}\n\nPUSHAR5:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR5:\t\t\t\t\tis PUSHAR4 {build PUSHAR4;}\nPUSHAR5:\t\t\t\t\tis ctx_mreg=0x5 & PUSHAR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R5 & 0xFFFFF;\n\tbuild PUSHAR4;\n}\n\nPUSHAR6:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR6:\t\t\t\t\tis PUSHAR5 {build PUSHAR5;}\nPUSHAR6:\t\t\t\t\tis ctx_mreg=0x6 & PUSHAR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R6 & 0xFFFFF;\n\tbuild PUSHAR5;\n}\n\nPUSHAR7:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR7:\t\t\t\t\tis PUSHAR6 {build PUSHAR6;}\nPUSHAR7:\t\t\t\t\tis ctx_mreg=0x7 & PUSHAR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R7 & 0xFFFFF;\n\tbuild PUSHAR6;\n}\n\nPUSHAR8:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR8:\t\t\t\t\tis PUSHAR7 {build PUSHAR7;}\nPUSHAR8:\t\t\t\t\tis ctx_mreg=0x8 & PUSHAR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R8 & 0xFFFFF;\n\tbuild PUSHAR7;\n}\n\nPUSHAR9:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR9:\t\t\t\t\tis PUSHAR8 {build PUSHAR8;}\nPUSHAR9:\t\t\t\t\tis ctx_mreg=0x9 & PUSHAR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R9 & 0xFFFFF;\n\tbuild PUSHAR8;\n}\n\nPUSHAR10:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR10:\t\t\t\t\tis PUSHAR9 {build PUSHAR9;}\nPUSHAR10:\t\t\t\t\tis ctx_mreg=0xA & PUSHAR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R10 & 0xFFFFF;\n\tbuild PUSHAR9;\n}\n\nPUSHAR11:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR11:\t\t\t\t\tis PUSHAR10 {build PUSHAR10;}\nPUSHAR11:\t\t\t\t\tis ctx_mreg=0xB & PUSHAR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R11 & 0xFFFFF;\n\tbuild PUSHAR10;\n}\n\nPUSHAR12:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR12:\t\t\t\t\tis PUSHAR11 {build PUSHAR11;}\nPUSHAR12:\t\t\t\t\tis ctx_mreg=0xC & PUSHAR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R12 & 0xFFFFF;\n\tbuild PUSHAR11;\n}\n\nPUSHAR13:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR13:\t\t\t\t\tis PUSHAR12 {build PUSHAR12;}\nPUSHAR13:\t\t\t\t\tis ctx_mreg=0xD & PUSHAR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R13 & 0xFFFFF;\n\tbuild PUSHAR12;\n}\n\nPUSHAR14:\t\t\t\t\tis ctx_count=0 {}\nPUSHAR14:\t\t\t\t\tis PUSHAR13 {build PUSHAR13;}\nPUSHAR14:\t\t\t\t\tis ctx_mreg=0xE & PUSHAR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R14 & 0xFFFFF;\n\tbuild PUSHAR13;\n}\n\nPUSHAR15:\t\t\t\t\tis PUSHAR14 {build PUSHAR14;}\nPUSHAR15:\t\t\t\t\tis ctx_mreg=0xF & PUSHAR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 4;\n\t*[RAM]:4 SP = R15 & 0xFFFFF;\n\tbuild PUSHAR14;\n}\n\nPUSHWR0:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR0:\t\t\t\t\tis ctx_mreg=0x0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = inst_start & 0xFFFF;\n}\n\nPUSHWR1:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR1:\t\t\t\t\tis PUSHWR0 {build PUSHWR0;}\nPUSHWR1:\t\t\t\t\tis ctx_mreg=0x1 & PUSHWR0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = SP:2;\n\tbuild PUSHWR0;\n}\n\nPUSHWR2:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR2:\t\t\t\t\tis PUSHWR1 {build PUSHWR1;}\nPUSHWR2:\t\t\t\t\tis ctx_mreg=0x2 & PUSHWR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = SR:2;\n\tbuild PUSHWR1;\n}\n\nPUSHWR3:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR3:\t\t\t\t\tis PUSHWR2 {build PUSHWR2;}\nPUSHWR3:\t\t\t\t\tis ctx_mreg=0x3 & PUSHWR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R3:2;\n\tbuild PUSHWR2;\n}\n\nPUSHWR4:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR4:\t\t\t\t\tis PUSHWR3 {build PUSHWR3;}\nPUSHWR4:\t\t\t\t\tis ctx_mreg=0x4 & PUSHWR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R4:2;\n\tbuild PUSHWR3;\n}\n\nPUSHWR5:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR5:\t\t\t\t\tis PUSHWR4 {build PUSHWR4;}\nPUSHWR5:\t\t\t\t\tis ctx_mreg=0x5 & PUSHWR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R5:2;\n\tbuild PUSHWR4;\n}\n\nPUSHWR6:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR6:\t\t\t\t\tis PUSHWR5 {build PUSHWR5;}\nPUSHWR6:\t\t\t\t\tis ctx_mreg=0x6 & PUSHWR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R6:2;\n\tbuild PUSHWR5;\n}\n\nPUSHWR7:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR7:\t\t\t\t\tis PUSHWR6 {build PUSHWR6;}\nPUSHWR7:\t\t\t\t\tis ctx_mreg=0x7 & PUSHWR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R7:2;\n\tbuild PUSHWR6;\n}\n\nPUSHWR8:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR8:\t\t\t\t\tis PUSHWR7 {build PUSHWR7;}\nPUSHWR8:\t\t\t\t\tis ctx_mreg=0x8 & PUSHWR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R8:2;\n\tbuild PUSHWR7;\n}\n\nPUSHWR9:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR9:\t\t\t\t\tis PUSHWR8 {build PUSHWR8;}\nPUSHWR9:\t\t\t\t\tis ctx_mreg=0x9 & PUSHWR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R9:2;\n\tbuild PUSHWR8;\n}\n\nPUSHWR10:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR10:\t\t\t\t\tis PUSHWR9 {build PUSHWR9;}\nPUSHWR10:\t\t\t\t\tis ctx_mreg=0xA & PUSHWR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R10:2;\n\tbuild PUSHWR9;\n}\n\nPUSHWR11:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR11:\t\t\t\t\tis PUSHWR10 {build PUSHWR10;}\nPUSHWR11:\t\t\t\t\tis ctx_mreg=0xB & PUSHWR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R11:2;\n\tbuild PUSHWR10;\n}\n\nPUSHWR12:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR12:\t\t\t\t\tis PUSHWR11 {build PUSHWR11;}\nPUSHWR12:\t\t\t\t\tis ctx_mreg=0xC & PUSHWR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R12:2;\n\tbuild PUSHWR11;\n}\n\nPUSHWR13:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR13:\t\t\t\t\tis PUSHWR12 {build PUSHWR12;}\nPUSHWR13:\t\t\t\t\tis ctx_mreg=0xD & PUSHWR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R13:2;\n\tbuild PUSHWR12;\n}\n\nPUSHWR14:\t\t\t\t\tis ctx_count=0 {}\nPUSHWR14:\t\t\t\t\tis PUSHWR13 {build PUSHWR13;}\nPUSHWR14:\t\t\t\t\tis ctx_mreg=0xE & PUSHWR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R14:2;\n\tbuild PUSHWR13;\n}\n\nPUSHWR15:\t\t\t\t\tis PUSHWR14 {build PUSHWR14;}\nPUSHWR15:\t\t\t\t\tis ctx_mreg=0xF & PUSHWR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] {\n\tSP = SP - 2;\n\t*[RAM]:2 SP = R15:2;\n\tbuild PUSHWR14;\n}\n\nPOPAR15:\t\t\t\t\tis ctx_count=0 {}\nPOPAR15:\t\t\t\t\tis ctx_mreg=0xF {\n\tR15 = *[RAM]:4 SP;\n\tR15 = sext(R15[0,20]);\n\tSP = SP + 4;\t\n}\n\nPOPAR14:\t\t\t\t\tis ctx_count=0 {}\nPOPAR14:\t\t\t\t\tis POPAR15 {build POPAR15;}\nPOPAR14:\t\t\t\t\tis ctx_mreg=0xE & POPAR15 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\t\n\tR14 = *[RAM]:4 SP;\n\tR14 = sext(R14[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR15;\n}\n\nPOPAR13:\t\t\t\t\tis ctx_count=0 {}\nPOPAR13:\t\t\t\t\tis POPAR14 {build POPAR14;}\nPOPAR13:\t\t\t\t\tis ctx_mreg=0xD & POPAR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR13 = *[RAM]:4 SP;\n\tR13 = sext(R13[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR14;\n}\n\nPOPAR12:\t\t\t\t\tis ctx_count=0 {}\nPOPAR12:\t\t\t\t\tis POPAR13 {build POPAR13;}\nPOPAR12:\t\t\t\t\tis ctx_mreg=0xC & POPAR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR12 = *[RAM]:4 SP;\n\tR12 = sext(R12[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR13;\n}\n\nPOPAR11:\t\t\t\t\tis ctx_count=0 {}\nPOPAR11:\t\t\t\t\tis POPAR12 {build POPAR12;}\nPOPAR11:\t\t\t\t\tis ctx_mreg=0xB & POPAR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR11 = *[RAM]:4 SP;\n\tR11 = sext(R11[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR12;\n}\n\nPOPAR10:\t\t\t\t\tis ctx_count=0 {}\nPOPAR10:\t\t\t\t\tis POPAR11 {build POPAR11;}\nPOPAR10:\t\t\t\t\tis ctx_mreg=0xA & POPAR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR10 = *[RAM]:4 SP;\n\tR10 = sext(R10[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR11;\n}\n\nPOPAR9:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR9:\t\t\t\t\t\tis POPAR10 {build POPAR10;}\nPOPAR9:\t\t\t\t\t\tis ctx_mreg=0x9 & POPAR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR9 = *[RAM]:4 SP;\n\tR9 = sext(R9[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR10;\n}\n\nPOPAR8:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR8:\t\t\t\t\t\tis POPAR9 {build POPAR9;}\nPOPAR8:\t\t\t\t\t\tis ctx_mreg=0x8 & POPAR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR8 = *[RAM]:4 SP;\n\tR8 = sext(R8[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR9;\n}\n\nPOPAR7:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR7:\t\t\t\t\t\tis POPAR8 {build POPAR8;}\nPOPAR7:\t\t\t\t\t\tis ctx_mreg=0x7 & POPAR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR7 = *[RAM]:4 SP;\n\tR7 = sext(R7[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR8;\n}\n\nPOPAR6:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR6:\t\t\t\t\t\tis POPAR7 {build POPAR7;}\nPOPAR6:\t\t\t\t\t\tis ctx_mreg=0x6 & POPAR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR6 = *[RAM]:4 SP;\n\tR6 = sext(R6[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR7;\n}\n\nPOPAR5:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR5:\t\t\t\t\t\tis POPAR6 {build POPAR6;}\nPOPAR5:\t\t\t\t\t\tis ctx_mreg=0x5 & POPAR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR5 = *[RAM]:4 SP;\n\tR5 = sext(R5[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR6;\n}\n\nPOPAR4:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR4:\t\t\t\t\t\tis POPAR5 {build POPAR5;}\nPOPAR4:\t\t\t\t\t\tis ctx_mreg=0x4 & POPAR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR4 = *[RAM]:4 SP;\n\tR4 = sext(R4[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR5;\n}\n\nPOPAR3:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR3:\t\t\t\t\t\tis POPAR4 {build POPAR4;}\nPOPAR3:\t\t\t\t\t\tis ctx_mreg=0x3 & POPAR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR3 = *[RAM]:4 SP;\n\tR3 = sext(R3[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR4;\n}\n\nPOPAR2:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR2:\t\t\t\t\t\tis POPAR3 {build POPAR3;}\nPOPAR2:\t\t\t\t\t\tis ctx_mreg=0x2 & POPAR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tSR = *[RAM]:4 SP;\n\tSP = SP + 4;\n\tbuild POPAR3;\n}\n\nPOPAR1:\t\t\t\t\t\tis ctx_count=0 {}\nPOPAR1:\t\t\t\t\t\tis POPAR2 {build POPAR2;}\nPOPAR1:\t\t\t\t\t\tis ctx_mreg=0x1 & POPAR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tSP = *[RAM]:4 SP;\n\tSP = sext(SP[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR2;\n}\n\nPOPAR0:\t\t\t\t\t\tis POPAR1 {build POPAR1;}\nPOPAR0:\t\t\t\t\t\tis ctx_mreg=0x0 & POPAR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tPC = *[RAM]:4 SP;\n\tPC = sext(PC[0,20]);\n\tSP = SP + 4;\n\tbuild POPAR1;\n\tgoto [PC];\n}\n\nPOPWR15:\t\t\t\t\tis ctx_count=0 {}\nPOPWR15:\t\t\t\t\tis ctx_mreg=0xF {\n\tR15 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\t\n}\n\nPOPWR14:\t\t\t\t\tis ctx_count=0 {}\nPOPWR14:\t\t\t\t\tis POPWR15 {build POPWR15;}\nPOPWR14:\t\t\t\t\tis ctx_mreg=0xE & POPWR15 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\t\n\tR14 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR15;\n}\n\nPOPWR13:\t\t\t\t\tis ctx_count=0 {}\nPOPWR13:\t\t\t\t\tis POPWR14 {build POPWR14;}\nPOPWR13:\t\t\t\t\tis ctx_mreg=0xD & POPWR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR13 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR14;\n}\n\nPOPWR12:\t\t\t\t\tis ctx_count=0 {}\nPOPWR12:\t\t\t\t\tis POPWR13 {build POPWR13;}\nPOPWR12:\t\t\t\t\tis ctx_mreg=0xC & POPWR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR12 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR13;\n}\n\nPOPWR11:\t\t\t\t\tis ctx_count=0 {}\nPOPWR11:\t\t\t\t\tis POPWR12 {build POPWR12;}\nPOPWR11:\t\t\t\t\tis ctx_mreg=0xB & POPWR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR11 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR12;\n}\n\nPOPWR10:\t\t\t\t\tis ctx_count=0 {}\nPOPWR10:\t\t\t\t\tis POPWR11 {build POPWR11;}\nPOPWR10:\t\t\t\t\tis ctx_mreg=0xA & POPWR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR10 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR11;\n}\n\nPOPWR9:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR9:\t\t\t\t\t\tis POPWR10 {build POPWR10;}\nPOPWR9:\t\t\t\t\t\tis ctx_mreg=0x9 & POPWR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR9 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR10;\n}\n\nPOPWR8:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR8:\t\t\t\t\t\tis POPWR9 {build POPWR9;}\nPOPWR8:\t\t\t\t\t\tis ctx_mreg=0x8 & POPWR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR8 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR9;\n}\n\nPOPWR7:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR7:\t\t\t\t\t\tis POPWR8 {build POPWR8;}\nPOPWR7:\t\t\t\t\t\tis ctx_mreg=0x7 & POPWR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR7 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR8;\n}\n\nPOPWR6:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR6:\t\t\t\t\t\tis POPWR7 {build POPWR7;}\nPOPWR6:\t\t\t\t\t\tis ctx_mreg=0x6 & POPWR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR6 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR7;\n}\n\nPOPWR5:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR5:\t\t\t\t\t\tis POPWR6 {build POPWR6;}\nPOPWR5:\t\t\t\t\t\tis ctx_mreg=0x5 & POPWR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR5 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR6;\n}\n\nPOPWR4:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR4:\t\t\t\t\t\tis POPWR5 {build POPWR5;}\nPOPWR4:\t\t\t\t\t\tis ctx_mreg=0x4 & POPWR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR4 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR5;\n}\n\nPOPWR3:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR3:\t\t\t\t\t\tis POPWR4 {build POPWR4;}\nPOPWR3:\t\t\t\t\t\tis ctx_mreg=0x3 & POPWR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tR3 = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR4;\n}\n\nPOPWR2:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR2:\t\t\t\t\t\tis POPWR3 {build POPWR3;}\nPOPWR2:\t\t\t\t\t\tis ctx_mreg=0x2 & POPWR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tSR = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR3;\n}\n\nPOPWR1:\t\t\t\t\t\tis ctx_count=0 {}\nPOPWR1:\t\t\t\t\t\tis POPWR2 {build POPWR2;}\nPOPWR1:\t\t\t\t\t\tis ctx_mreg=0x1 & POPWR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tSP = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR2;\n}\n\nPOPWR0:\t\t\t\t\t\tis POPWR1 {build POPWR1;}\nPOPWR0:\t\t\t\t\t\tis ctx_mreg=0x0 & POPWR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] {\n\tPC = zext(*[RAM]:2 SP);\n\tSP = SP + 2;\n\tbuild POPWR1;\n\tgoto [PC];\n}\n\n:ADDA src_8_4, dest_0_4\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4 & dest_0_4 {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = src_8_4 + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,src_8_4,tmpd);\n}\n\n:ADDA src_8_4, dest_0_4\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4 & dest_0_4 & dest_0_4=0x0 {\n\ttmpd:$(REG_SIZE) = inst_start + 2;\n\ttmp:$(REG_SIZE) = src_8_4 + tmpd;\n\tPC = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,src_8_4,tmpd);\n\tgoto [PC];\n}\n\n:ADDA src_8_4, dest_0_4\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4 & src_8_4=0x0 & dest_0_4 {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = inst_start + 2;\n\ttmp:$(REG_SIZE) = tmps + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmps,tmpd);\n}\n\n:ADDA \"#\"^Abs20s, dest_0_4\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xA & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = sext(Abs20s);\n\ttmp:$(REG_SIZE) = tmpd + tmps;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmps,tmpd);\n}\n\n:ADDA \"#\"^Abs20s, dest_0_4\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xA & imm_8_4 & dest_0_4 & dest_0_4=0x0; Abs20s [ctx_ctregdest=imm_8_4;] {\n\ttmpd:$(REG_SIZE) = inst_start + 2;\n\ttmps:$(REG_SIZE) = sext(Abs20s);\n\ttmp:$(REG_SIZE) = tmpd + tmps;\n\tPC = sext(tmp[0,20]);\n\t\n\tsetaddflags(PC,tmps,tmpd);\n\tgoto [PC];\n}\n\n:CMPA src_8_4, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xD & src_8_4 & dest_0_4 {\n\ttmp:$(REG_SIZE) = dest_0_4 - src_8_4;\n\ttmpd:$(REG_SIZE) = sext(tmp[0,20]);\n\tsetsubflags(tmpd,src_8_4,dest_0_4);\n}\n\n:CMPA \"#\"^Abs20s, dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x9 & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] {\n\ttmps:$(REG_SIZE) = sext(Abs20s);\n\ttmp:$(REG_SIZE) = dest_0_4 - tmps;\n\ttmpd:$(REG_SIZE) = sext(tmp[0,20]);\n\tsetsubflags(tmpd,tmps,dest_0_4);\n}\n\n:MOVA \"@\"^src_8_4, dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x0 & src_8_4 & dest_0_4 {\n\tdest_0_4 = *[RAM]:$(REG_SIZE) src_8_4;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n}\n\n:MOVA \"@\"^src_8_4^\"+\", dest_0_4\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x1 & src_8_4 & dest_0_4 {\n\tdest_0_4 = *[RAM]:$(REG_SIZE) src_8_4;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\tsrc_8_4 = src_8_4 + 4;\n}\n\n:MOVA \"&\"^Abs20, dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x2 & imm_8_4 & dest_0_4 ; Abs20 [ctx_ctregdest=imm_8_4;] {\n\ttmp:$(REG_SIZE) = zext(Abs20);\n\tdest_0_4 = *[RAM]:$(REG_SIZE) tmp;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n}\n\n:MOVA imms_0_16^\"(\"^src_8_4^\")\", dest_0_4\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x3 & src_8_4 & dest_0_4 ; imms_0_16 {\n\ttmp:$(REG_SIZE) = src_8_4 + sext(imms_0_16:2);\n\tdest_0_4 = *[RAM]:$(REG_SIZE) tmp;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n}\n\n:MOVA src_8_4, \"&\"^Abs20\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x6 & imm_0_4 & src_8_4 ; Abs20 [ctx_ctregdest=imm_0_4;] {\n\ttmp:$(REG_SIZE) = zext(Abs20);\n\t*[RAM]:$(REG_SIZE) tmp = src_8_4 & 0xFFFFF;\n}\n\n:MOVA src_8_4, imms_0_16^\"(\"^dest_0_4^\")\"\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x7 & src_8_4 & dest_0_4 ; imms_0_16 {\n\ttmp:$(REG_SIZE) = dest_0_4 + sext(imms_0_16:2);\n\t*[RAM]:$(REG_SIZE) tmp = src_8_4 & 0xFFFFF;\n}\n\n:MOVA \"#\"^Abs20s, dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x8 & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] {\n\tdest_0_4 = sext(Abs20s);\n}\n\n:MOVA src_8_4, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xC & src_8_4 & dest_0_4 {\n\tdest_0_4 = src_8_4;\n}\n\n:SUBA src_8_4, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4 & dest_0_4 {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = dest_0_4 - src_8_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,src_8_4,tmpd);\n}\n\n:SUBA src_8_4, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4 & dest_0_4 & dest_0_4=0x0 {\n\ttmpd:$(REG_SIZE) = inst_start + 2;\n\ttmp:$(REG_SIZE) = tmpd - src_8_4;\n\tPC = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,src_8_4,tmpd);\n\tgoto [PC];\n}\n\n:SUBA src_8_4, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4 & src_8_4=0x0 & dest_0_4 {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = inst_start + 2;\n\ttmp:$(REG_SIZE) = dest_0_4 - tmps;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,tmps,tmpd);\n}\n\n:SUBA \"#\"^Abs20s, dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xB & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = sext(Abs20s);\n\ttmp:$(REG_SIZE) = dest_0_4 - tmps;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,tmps,tmpd);\n}\n\n:SUBA \"#\"^Abs20s, dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xB & imm_8_4 & dest_0_4 & dest_0_4=0x0; Abs20s [ctx_ctregdest=imm_8_4;] {\n\ttmpd:$(REG_SIZE) = inst_start + 2;\n\ttmps:$(REG_SIZE) = sext(Abs20s);\n\ttmp:$(REG_SIZE) = tmpd - tmps;\n\tPC = sext(tmp[0,20]);\n\t\n\tsetsubflags(PC,tmps,tmpd);\n\tgoto [PC];\n}\n\n##################\n#\n# Special cases of renamed MOVA where PC is involved\n\n# This first case doesn't make any sense, but I saw it in the cunits. The instruction word is all 0.\n# The toolchain comes back with a 'beq', but that doesn't make sense either as there is no beq instruction\n# anywhere in the manual. One toolchain allows BRA @PC, another one doesn't. I did find reference to gvv\n# assembler extension regarding @rN being treated as 0(rN) and vice versa. That would effectively turn\n# this into a branch to following instruction. What I think may be happening is a compiler bug where in\n# some cases an immediate gets output even though the constant generator is used.\n:BRA \"@\"^src_8_4 \t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x0 & src_8_4 & src_8_4=0 & dest_0_4=0x0 {\n}\n\n:BRA \"@\"^src_8_4 \t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x0 & src_8_4 & dest_0_4=0x0 {\n\tPC = *[RAM]:$(REG_SIZE) src_8_4;\n\tPC = sext(PC[0,20]);\n\tgoto [PC];\n}\n\n:BRA \"@\"^src_8_4^\"+\" \t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x1 & src_8_4 & dest_0_4=0x0 {\n\tPC = *[RAM]:$(REG_SIZE) src_8_4;\n\tPC = sext(PC[0,20]);\n\tsrc_8_4 = src_8_4 + 4;\n\tgoto [PC];\n}\n\n:BRA \"&\"^Abs20\t\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x2 & imm_8_4 & dest_0_4=0x0; Abs20 [ctx_ctregdest=imm_8_4;] {\n\ttmp:$(REG_SIZE) = zext(Abs20);\n\tPC = *[RAM]:$(REG_SIZE) tmp;\n\tPC = sext(PC[0,20]);\n\tgoto [PC];\n}\n\n:BRA imms_0_16^\"(\"^src_8_4^\")\"\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x3 & src_8_4 & dest_0_4=0x0; imms_0_16 {\n\ttmp:$(REG_SIZE) = src_8_4 + sext(imms_0_16:2);\n\tPC = *[RAM]:$(REG_SIZE) tmp;\n\tPC = sext(PC[0,20]);\n\tgoto [PC];\n}\n\n:BRA \"#\"^Abs20add\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x8 & imm_8_4 & dest_0_4=0x0; Abs20add [ctx_ctregdest=imm_8_4;] {\n#\tPC = Abs20add;\n\tgoto Abs20add;\n}\n\n:BRA src_8_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xC & src_8_4 & dest_0_4=0x0 {\n\tPC = src_8_4;\n\tgoto [PC];\n}\n\n:RETA \"@\"^src_8_4^\"+\"\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x1 & src_8_4 & src_8_4=0x1 & dest_0_4=0x0 {\n\tPC = *[RAM]:$(REG_SIZE) src_8_4;\n\tPC = sext(PC[0,20]);\n\tSP = SP + 4;\n\treturn [PC];\n}\n#\n################\n#\n# Special cases of SUBA/ADDA/CMPA/MOVA\n:DECDA dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xB & imm_8_4=0x0 & dest_0_4 ; imm_0_16=0x0002 {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = 2;\n\tdest_0_4 = dest_0_4 - 2;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t\n\tsetsubflags(dest_0_4,tmps,tmpd);\n}\n\n:INCDA dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0xA & imm_8_4=0x0 & dest_0_4 ; imm_0_16=0x0002 {\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = 2;\n\tdest_0_4 = dest_0_4 + 2;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmps,tmpd);\n}\n\n:TSTA dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x9 & imm_8_4=0x0 & dest_0_4 ; imm_0_16=0x0000 {\n\t$(CARRY) = 1;\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (dest_0_4 s< 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:CLRA dest_0_4\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insid=0x8 & imm_8_4=0 & dest_0_4 ; imm_0_16=0 {\n\tdest_0_4 = 0;\n}\n\n#\n################\n#\n# Other 20 bit address instructions\n:CALLA dest_0_4\t\t\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x4 & dest_0_4 {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\tPC = dest_0_4;\n\tcall [PC];\n}\n\n:CALLA imms_0_16^\"(\"^dest_0_4^\")\"\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x5 & dest_0_4 ; imms_0_16 {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\ttmp:$(REG_SIZE) = dest_0_4 + sext(imms_0_16:2);\n\tPC = *[RAM]:$(REG_SIZE) tmp;\n\tPC = sext(PC[0,20]);\n\tcall [PC];\n}\n\n:CALLA \"@\"^dest_0_4\t\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x6 & dest_0_4 {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\tPC = *[RAM]:$(REG_SIZE) dest_0_4;\n\tPC = sext(PC[0,20]);\n\tcall [PC];\n}\n\n:CALLA \"@\"^dest_0_4^\"+\"\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x7 & dest_0_4 {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\tPC = *[RAM]:$(REG_SIZE) dest_0_4;\n\tPC = sext(PC[0,20]);\n\tdest_0_4 = dest_0_4 + 4;\n\tcall [PC];\n}\n\n:CALLA \"&\"^Abs20\t\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x8 & imm_0_4; Abs20 [ctx_ctregdest=imm_0_4;] {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\ttmp:$(REG_SIZE) = zext(Abs20);\n\tPC = *[RAM]:$(REG_SIZE) tmp;\n\tPC = sext(PC[0,20]);\n\tcall [PC];\n}\n\n:CALLA imms_0_16^\"(PC)\"\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x9 ; imms_0_16 {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\ttmp:$(REG_SIZE) = inst_start + sext(imms_0_16:2);\n\tPC = *[RAM]:$(REG_SIZE) tmp;\n\tPC = sext(PC[0,20]);\n\tcall [PC];\n}\n\n:CALLA \"#\"^Abs20add\t\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0xB & imm_0_4; Abs20add [ctx_ctregdest = imm_0_4;] {\n\tSP = SP - 0x4;\n\t*:4 SP = inst_next;\n\tPC = &Abs20add;\n\tcall Abs20add;\n}\n\n\n:PUSHM.A IMM4,dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x14 & IMM4 & dest_0_4 & imm_4_4 & PUSHAR15 [ctx_count=imm_4_4+1; ctx_mreg=dest_0_4;] {\n\tbuild IMM4;\n\tbuild PUSHAR15;\n}\n\n:PUSHM.W IMM4,dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x15 & IMM4 & dest_0_4 & imm_4_4 & PUSHWR15 [ctx_count=imm_4_4+1; ctx_mreg=dest_0_4;] {\n\tbuild IMM4;\n\tbuild PUSHWR15;\n}\n\n:POPM.A IMM4,ctx_popreg\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x16 & IMM4 & ctx_popreg & imm_0_4 & imm_4_4 & POPAR0 [ctx_popreg_set=imm_0_4+imm_4_4; ctx_count=imm_4_4+1; ctx_mreg=imm_0_4;] {\n\tbuild IMM4;\n\tbuild POPAR0;\n}\n\n:POPM.W IMM4,ctx_popreg\t\t\t\t\tis ctx_haveext=0 & op16_8_8=0x17 & IMM4 & ctx_popreg & imm_0_4 & imm_4_4 & POPWR0 [ctx_popreg_set=imm_0_4+imm_4_4; ctx_count=imm_4_4+1; ctx_mreg=imm_0_4;] {\n\tbuild IMM4;\n\tbuild POPWR0;\n}\n\n:RRCM.A\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x04 & NUM2 & dest_0_4 & rrn {\n\ttmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1;\n\ttmpc:$(REG_SIZE) = zext($(CARRY));\n\ttmpc = tmpc << (20-NUM2);\n\tdest_0_4 = (dest_0_4 >> NUM2) | (dest_0_4 << (20-rrn));\n\tdest_0_4 = ((dest_0_4 & (~tmpc)) | tmpc) & 0xFFFFF;\n\t$(CARRY) = (tmph != 0);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (dest_0_4[19,1] != 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RRAM.A\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x14 & NUM2 & dest_0_4 & rrn {\n\ttmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1;\n\tdest_0_4 = (dest_0_4 s>> NUM2);\n\t$(CARRY) = (tmph != 0);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (dest_0_4[19,1] != 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RLAM.A\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x24 & NUM2 & dest_0_4 {\n\ttmph:$(REG_SIZE) = (dest_0_4 >> (20 - NUM2)) & 0x1;\n\tdest_0_4 = (dest_0_4 << NUM2);\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t$(CARRY) = (tmph != 0);\n\t$(SIGN) = (dest_0_4[19,1] != 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RRUM.A\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x34 & NUM2 & dest_0_4 & rrn {\n\ttmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1;\n\tdest_0_4 = (dest_0_4 >> NUM2) & 0xFFFFF;\n\t$(CARRY) = (tmph != 0);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = 0;\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RRCM.W\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x05 & NUM2 & dest_0_4 & rrn {\n\ttmpr:2 = dest_0_4:2;\n\ttmph:2 = (tmpr >> rrn) & 0x1;\n\ttmpc:2 = zext($(CARRY));\n\ttmpc = tmpc << (16-NUM2);\n\ttmpr = (tmpr >> NUM2) | (tmpr << (16-rrn));\n\tdest_0_4 = zext((tmpr & (~tmpc)) | tmpc);\n\t$(CARRY) = (tmph != 0);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (dest_0_4[15,1] != 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RRAM.W\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x15 & NUM2 & dest_0_4 & rrn {\n\ttmpr:2 = dest_0_4:2;\n\ttmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1;\n\tdest_0_4 = zext(tmpr s>> NUM2);\n\t$(CARRY) = (tmph != 0);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (dest_0_4[19,1] != 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RLAM.W\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x25 & NUM2 & dest_0_4 {\n\ttmph:$(REG_SIZE) = (dest_0_4 >> (16 - NUM2)) & 0x1;\n\tdest_0_4 = (dest_0_4 << NUM2);\n\tdest_0_4 = zext(dest_0_4:2);\n\t$(CARRY) = (tmph != 0);\n\t$(SIGN) = (dest_0_4[19,1] != 0);\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\n:RRUM.W\tNUM2, dest_0_4\t\t\t\t\tis ctx_haveext=0 & op16_12_4=0 & insidbig=0x35 & NUM2 & dest_0_4 & rrn {\n\ttmpr:2 = dest_0_4:2;\n\ttmph:2 = (tmpr >> rrn) & 0x1;\n\tdest_0_4 = zext(tmpr >> NUM2);\n\t$(CARRY) = (tmph != 0);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = 0;\n\t$(ZERO) = (dest_0_4 == 0);\n}\n\nmacro bzero(full, byte)\n{\n\tztmp:1 = byte;\n\tfull = 0;\n\tbyte = ztmp;\n}\n\nmacro wzero(full, word)\n{\n\tztmp:2 = word;\n\tfull = 0;\n\tword = ztmp;\n}\n\n##############################\n#\n# Extention word instructions\n#\n# The base msp430 handles all the addressing modes in subtables.\n# The reg/reg mode for the 'X' instruction has repetition so we\n# break that mode out separately. Because of that, we need to use\n# separate subtables for the address modes since the base ones\n# will hit on the reg/reg mode.\n#\n# There are also two groups for the extended instructions:\n# double and single operand. The double operand ones come\n# first. A lot of the singles are covered under the address\n# extensions as they don't have the extension word.\n#\n# The manual talks about RRUX extended instructions. However,\n# I've determined they don't really exist. First off, the base\n# RRU is not mentioned in the manual and is not in the toolchain.\n# The toolchain does take rrux instructions, but what I've figured\n# out is that for the W and A versions, it substitutes RRUM with \n# the 'n' argument being 1. For the B version, it uses rra.b\n# followed by a bic.b instruction.\n#############################\n#\n# Double Operand\n#\n#############################\n# Repeat enabled\n:ADCX.B DST8_0_4\t\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\ttmp_carry:1 = carry(DST8_0_4,$(CARRY));\t\t #C Flag\n \t$(OVERFLOW) = scarry(DST8_0_4,$(CARRY)); #V Flag\n \t# Operation...\n\tDST8_0_4 = DST8_0_4 + $(CARRY);\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADCX.W DST16_0_4\t\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\ttmp_carry:1 = carry(DST16_0_4,zext($(CARRY)));\t\t #C Flag\n \t$(OVERFLOW) = scarry(DST16_0_4,zext($(CARRY))); #V Flag\n \t# Operation...\n\tDST16_0_4 = DST16_0_4 + zext($(CARRY));\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADCX.A dest_0_4\t\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmpc:$(REG_SIZE) = zext($(CARRY));\n\ttmp:$(REG_SIZE) = tmpc + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmpc,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADDX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(XRSRC_B_AS, DST8_0_4); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XRSRC_B_AS, DST8_0_4); \t# V Flag\n\t# Operation...\n\tDST8_0_4 = XRSRC_B_AS + DST8_0_4;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADDX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(XRSRC_W_AS, DST16_0_4); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XRSRC_W_AS, DST16_0_4); \t# V Flag\n\t# Operation...\n\tDST16_0_4 = XRSRC_W_AS + DST16_0_4;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADDX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = XRSRC_A_AS + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,XRSRC_A_AS,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADDCX.B XRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(XRSRC_B_AS, $(CARRY)) || carry(DST8_0_4,XRSRC_B_AS + $(CARRY)));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(XRSRC_B_AS, $(CARRY)) || scarry(DST8_0_4,XRSRC_B_AS + $(CARRY))); #V Flag\n \t# Operation...\n\tDST8_0_4 = XRSRC_B_AS + DST8_0_4 + $(CARRY);\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADDCX.W XRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(XRSRC_W_AS,zext($(CARRY))) || carry(DST16_0_4,XRSRC_W_AS + zext($(CARRY))));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(XRSRC_W_AS,zext($(CARRY))) || scarry(DST16_0_4,XRSRC_W_AS + zext($(CARRY)))); #V Flag\n \t# Operation...\n\tDST16_0_4 = XRSRC_W_AS + DST16_0_4 + zext($(CARRY));\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ADDCX.A XRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = XRSRC_A_AS + zext($(CARRY));\n\ttmp:$(REG_SIZE) = tmps + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmps,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ANDX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xF & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 & XRSRC_B_AS;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DST8_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ANDX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0xF & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 & XRSRC_W_AS;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DST16_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:ANDX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xF & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Operation...\n\tdest_0_4 = dest_0_4 & XRSRC_A_AS;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (dest_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (dest_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (dest_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BICX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xC & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\tDST8_0_4 = (~XRSRC_B_AS) & DST8_0_4;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BICX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0xC & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\tDST16_0_4 = (~XRSRC_W_AS) & DST16_0_4;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BICX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xC & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\tdest_0_4 = (~XRSRC_A_AS) & dest_0_4;\n\tdest_0_4 = zext(dest_0_4[0,20]);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BISX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xD & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\tDST8_0_4 = XRSRC_B_AS | DST8_0_4;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BISX.W\tXRSRC_W_AS, DST16_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xD & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\tDST16_0_4 = XRSRC_W_AS | DST16_0_4;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t#Status bits are not affected\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BISX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xD & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\tdest_0_4 = XRSRC_A_AS | dest_0_4;\n\t#Status bits are not affected\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BITX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xB & bow=1 & ctx_al=1 & postIncrement & XRSRC_B_AS & DST8_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\tresult:1 = DST8_0_4 & XRSRC_B_AS;\n\t# Result Flags...\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BITX.W\tXRSRC_W_AS, DST16_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xB & bow=0 & ctx_al=1 & postIncrement & XRSRC_W_AS & DST16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\tresult:2 = DST16_0_4 & XRSRC_W_AS;\n\t# Result Flags...\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:BITX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xB & bow=1 & ctx_al=0 & postIncrement & XRSRC_A_AS & dest_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\tresult:$(REG_SIZE) = dest_0_4 & XRSRC_A_AS;\n\t# Result Flags...\n\tresult = sext(result[0,20]);\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:CLRX.B\tDST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\tDST8_0_4 = 0;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:CLRX.W\tDST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\tDST16_0_4 = 0;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:CLRX.A\tdest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 {\n\t\n\tdest_0_4 = 0;\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:CMPX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=1 & postIncrement & XRSRC_B_AS & DST8_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (XRSRC_B_AS <= DST8_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST8_0_4, XRSRC_B_AS);\t# V Flag\n\t# Operation...\n\tresult:1 = (DST8_0_4 - XRSRC_B_AS);\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:CMPX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0x9 & bow=0 & ctx_al=1 & postIncrement & XRSRC_W_AS & DST16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (XRSRC_W_AS <= DST16_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST16_0_4, XRSRC_W_AS);\t# V Flag\n\t# Operation...\n\tresult:2 = (DST16_0_4 - XRSRC_W_AS);\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:CMPX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=0 & postIncrement & XRSRC_A_AS & dest_0_4 {\n\t\n\ttmp:$(REG_SIZE) = dest_0_4 - XRSRC_A_AS;\n\ttmpd:$(REG_SIZE) = sext(tmp[0,20]);\n\tsetsubflags(tmpd,XRSRC_A_AS,dest_0_4);\n\tbuild postIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\ndefine pcodeop bcd_add;\n\n:DADCX.B DST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tlocal temp:4 = zext(DST8_0_4);\n\tDST8_0_4 = bcd_add(temp, $(CARRY));\n\t$(CARRY) = temp >= 0x99;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DADCX.W DST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tlocal temp:4 = zext(DST16_0_4);\n\tDST16_0_4 = bcd_add(temp, $(CARRY));\n\t$(CARRY) = temp >= 0x9999;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DADCX.A dest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tlocal temp:4 = zext(dest_0_4);\n\tdest_0_4 = bcd_add(temp, $(CARRY));\n\t$(CARRY) = temp >= 0x99999;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (dest_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (dest_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DADDX.B XRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xA & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tlocal temp_src:4 = zext(XRSRC_B_AS);\n\tlocal temp_dest:4 = zext(DST8_0_4);\n\tlocal temp_carry:4 = zext($(CARRY));\n\tDST8_0_4 = bcd_add(temp_src,temp_dest, temp_carry);\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t# Z Flag\n\t$(CARRY) = (temp_src + temp_dest + temp_carry) > 0x99;\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DADDX.W XRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0xA & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tlocal temp_src:4 = zext(XRSRC_W_AS);\n\tlocal temp_dest:4 = zext(DST16_0_4);\n\tlocal temp_carry:4 = zext($(CARRY));\n\tDST16_0_4 = bcd_add(temp_src, temp_dest, temp_carry);\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (temp_src + temp_dest + temp_carry) > 0x9999;\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DADDX.A XRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xA & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tlocal temp_src:4 = zext(XRSRC_A_AS);\n\tlocal temp_dest:4 = zext(dest_0_4);\n\tlocal temp_carry:4 = zext($(CARRY));\n\tdest_0_4 = bcd_add(temp_src, temp_dest, temp_carry);\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (dest_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (dest_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (temp_src + temp_dest + temp_carry) > 0x99999;\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DECX.B\tDST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (1 <= DST8_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST8_0_4, 1:1);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 - 1;\t\t\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DECX.W\tDST16_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (1 <= DST16_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST16_0_4, 1:2);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 - 1;\t\t\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DECX.A\tdest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = dest_0_4 - 1;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,1:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DECDX.B DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (2 <= DST8_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST8_0_4, 2:1);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 - 2;\t\t\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DECDX.W DST16_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (2 <= DST16_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST16_0_4, 2:2);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 - 2;\t\t\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:DECDX.A dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = dest_0_4 - 2;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,2:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INCX.B\tDST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(DST8_0_4,1); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DST8_0_4,1); \t# V Flag\n\t# Operation...\n\tDST8_0_4 = 1 + DST8_0_4;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INCX.W\tDST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(DST16_0_4,1); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DST16_0_4,1); \t# V Flag\n\t# Operation...\n\tDST16_0_4 = 1:2 + DST16_0_4;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INCX.A\tdest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = 1 + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,1:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INCDX.B DST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(DST8_0_4,2); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DST8_0_4,2); \t# V Flag\n\t# Operation...\n\tDST8_0_4 = 2 + DST8_0_4;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INCDX.W DST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(DST16_0_4,2); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DST16_0_4,2); \t# V Flag\n\t# Operation...\n\tDST16_0_4 = 2:2 + DST16_0_4;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INCDX.A dest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = 2 + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,2:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INVX.B\tDST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = DST8_0_4 s< 0x0;\t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 ^ -1;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DST8_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INVX.W\tDST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = DST16_0_4 s< 0x0 ;\t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 ^ -1;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DST16_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:INVX.A\tdest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = dest_0_4 s< 0x0;\t# V Flag\n\t# Operation...\n\tdest_0_4 = dest_0_4 ^ -1;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (dest_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (dest_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (dest_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:MOVX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\tDST8_0_4 = XRSRC_B_AS;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:MOVX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\tDST16_0_4 = XRSRC_W_AS;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:MOVX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\tdest_0_4 = XRSRC_A_AS;\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:POPX.B\tDST8_0_4\t\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & ctx_al=1 & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\tDST8_0_4 = *:1 SP;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\tSP = SP + 0x2;\n\t#Status bits are not affected\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:POPX.W\tDST16_0_4\t\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=0 & ctx_al=1 & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\tDST16_0_4 = *:2 SP;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\tSP = SP + 0x2;\n\t#Status bits are not affected\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:POPX.A\tdest_0_4\t\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & ctx_al=0 & XRSRC_A_AS & dest_0_4 {\n\t\n\tdest_0_4 = *:4 SP;\n\tSP = SP + 0x4;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RLAX.B\tDST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & bow=1 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(DST8_0_4, DST8_0_4); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DST8_0_4, DST8_0_4); \t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 + DST8_0_4;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RLAX.W\tDST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & bow=0 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = carry(DST16_0_4, DST16_0_4); \t \t# C Flag\n\t$(OVERFLOW) = scarry(DST16_0_4, DST16_0_4); \t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 + DST16_0_4;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RLAX.A\tdest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x5 & bow=1 & src_Direct16_8_4=dest_Direct16_0_4 & ctx_al=0 & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = dest_0_4 + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmpd,tmpd);\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RLCX.B DST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(DST8_0_4, $(CARRY)) || carry(DST8_0_4,DST8_0_4 + $(CARRY)));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(DST8_0_4, $(CARRY)) || scarry(DST8_0_4,DST8_0_4 + $(CARRY))); #V Flag\n \t# Operation...\n\tDST8_0_4 = DST8_0_4 + DST8_0_4 + $(CARRY);\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RLCX.W DST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & bow=0 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(DST16_0_4,zext($(CARRY))) || carry(DST16_0_4,DST16_0_4 + zext($(CARRY))));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(DST16_0_4,zext($(CARRY))) || scarry(DST16_0_4,DST16_0_4 + zext($(CARRY)))); #V Flag\n \t# Operation...\n\tDST16_0_4 = DST16_0_4 + DST16_0_4 + zext($(CARRY));\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RLCX.A dest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=0 & src_Direct16_8_4=dest_Direct16_0_4 & postIncrementStore & XRSRC_A_AS & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = dest_0_4 + zext($(CARRY));\n\ttmp:$(REG_SIZE) = tmps + dest_0_4;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetaddflags(dest_0_4,tmps,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SBCX.B DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\tbrw:1 = 1 - $(CARRY);\n $(CARRY) = (brw <= DST8_0_4); # Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST8_0_4, brw);\t\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 - brw;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SBCX.W DST16_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x7 & bow=0 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\tbrw:2 = 1 - zext( $(CARRY) );\n\t$(CARRY) = (brw <= DST16_0_4);\t\t# Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST16_0_4, brw);\t\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 - brw;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SBCX.A dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=0 & src16_8_4=0x3 & as=0x0 & postIncrementStore & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tbrw:$(REG_SIZE) = 1 - zext( $(CARRY) );\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = dest_0_4 - brw;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,brw,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SUBCX.B XRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\tbrw:1 = 1 - $(CARRY);\n $(CARRY) = ((brw + XRSRC_B_AS) <= DST8_0_4); # Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST8_0_4, XRSRC_B_AS + brw);\t\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 - XRSRC_B_AS - brw;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SUBCX.W XRSRC_W_AS, DST16_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x7 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\tbrw:2 = 1 - zext( $(CARRY) );\n\t$(CARRY) = ((brw + XRSRC_W_AS) <= DST16_0_4);\t\t# Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST16_0_4, XRSRC_W_AS + brw);\t\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 - XRSRC_W_AS - brw;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SUBCX.A XRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 & repeat_carry {\n\t\n\tbuild repeat_carry;\n\tbrw:$(REG_SIZE) = 1 - zext( $(CARRY) );\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmps:$(REG_SIZE) = XRSRC_A_AS + brw;\n\ttmp:$(REG_SIZE) = dest_0_4 - tmps;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,tmps,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SUBX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (XRSRC_B_AS <= DST8_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST8_0_4, XRSRC_B_AS);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 - XRSRC_B_AS;\t\t\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SUBX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = (XRSRC_W_AS <= DST16_0_4);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(DST16_0_4, XRSRC_W_AS);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 - XRSRC_W_AS;\t\t\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SUBX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0x8 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\ttmpd:$(REG_SIZE) = dest_0_4;\n\ttmp:$(REG_SIZE) = dest_0_4 - XRSRC_A_AS;\n\tdest_0_4 = sext(tmp[0,20]);\n\t\n\tsetsubflags(dest_0_4,XRSRC_A_AS,tmpd);\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:TSTX.B\tDST8_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & DST8_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = 1;\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = 0;\t# V Flag\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:TSTX.W\tDST16_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x9 & bow=0 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & DST16_0_4 {\n\t\n\t# Operation Flags...\n\t$(CARRY) = 1;\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = 0;\t# V Flag\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:TSTX.A\tdest_0_4\t\t\t\t\t\tis ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=0 & src16_8_4=0x3 & as=0x0 & dest_0_4 {\n\t\n\tsetsubflags(dest_0_4,0:$(REG_SIZE),dest_0_4);\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:XORX.B\tXRSRC_B_AS, DST8_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xE & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = ((DST8_0_4 s< 0x0) && (XRSRC_B_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tDST8_0_4 = DST8_0_4 ^ XRSRC_B_AS;\n\tbzero(reg_Direct16_0_4,DST8_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST8_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST8_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DST8_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:XORX.W\tXRSRC_W_AS, DST16_0_4\t\t\tis ctx_haveext=4 & op16_12_4=0xE & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = ((DST16_0_4 s< 0x0) && (XRSRC_W_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tDST16_0_4 = DST16_0_4 ^ XRSRC_W_AS;\n\twzero(reg_Direct16_0_4,DST16_0_4);\n\t# Result Flags...\n\t$(SIGN) = (DST16_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (DST16_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (DST16_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:XORX.A\tXRSRC_A_AS, dest_0_4\t\t\t\tis ctx_haveext=4 & op16_12_4=0xE & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = ((dest_0_4 s< 0x0) && (XRSRC_A_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tdest_0_4 = dest_0_4 ^ XRSRC_A_AS;\n\tdest_0_4 = sext(dest_0_4[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (dest_0_4 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (dest_0_4 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (dest_0_4 != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n#############################\n# No Repeat\n:ADCX.B XDEST_B_AD\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = carry(XDEST_B_AD,$(CARRY));\t\t #C Flag\n \t$(OVERFLOW) = scarry(XDEST_B_AD,$(CARRY)); #V Flag\n \t# Operation...\n\tXDEST_B_AD = XDEST_B_AD + $(CARRY);\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:ADCX.W XDEST_W_AD\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = carry(XDEST_W_AD,zext($(CARRY)));\t\t #C Flag\n \t$(OVERFLOW) = scarry(XDEST_W_AD,zext($(CARRY))); #V Flag\n \t# Operation...\n\tXDEST_W_AD = XDEST_W_AD + zext($(CARRY));\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:ADCX.A XDEST_A_AD\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmpc:$(REG_SIZE) = zext($(CARRY));\n\ttmp:$(REG_SIZE) = tmpc + XDEST_A_AD;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetaddflags(XDEST_A_AD,tmpc,tmpd);\n\tbuild postIncrementStore;\n}\n\n:ADDX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(XSRC_B_AS, XDEST_B_AD); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XSRC_B_AS, XDEST_B_AD); \t# V Flag\n\t# Operation...\n\tXDEST_B_AD = XSRC_B_AS + XDEST_B_AD;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:ADDX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(XSRC_W_AS, XDEST_W_AD); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XSRC_W_AS, XDEST_W_AD); \t# V Flag\n\t# Operation...\n\tXDEST_W_AD = XSRC_W_AS + XDEST_W_AD;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:ADDX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x5 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmp:$(REG_SIZE) = XSRC_A_AS + XDEST_A_AD;\n\t\n\tXDEST_A_AD = sext(tmp[0,20]);\n\tsetaddflags(XDEST_A_AD,XSRC_A_AS,tmpd);\n\tbuild postIncrementStore;\n}\n\n:ADDCX.B XSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(XSRC_B_AS, $(CARRY)) || carry(XDEST_B_AD,XSRC_B_AS + $(CARRY)));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(XSRC_B_AS, $(CARRY)) || scarry(XDEST_B_AD,XSRC_B_AS + $(CARRY))); #V Flag\n \t# Operation...\n\tXDEST_B_AD = XSRC_B_AS + XDEST_B_AD + $(CARRY);\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:ADDCX.W XSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\ttmp_carry:1 = (carry(XSRC_W_AS,zext($(CARRY))) || carry(XDEST_W_AD,XSRC_W_AS + zext($(CARRY))));\t\t #C Flag\n \t$(OVERFLOW) = (scarry(XSRC_W_AS,zext($(CARRY))) || scarry(XDEST_W_AD,XSRC_W_AS + zext($(CARRY)))); #V Flag\n \t# Operation...\n\tXDEST_W_AD = XSRC_W_AS + XDEST_W_AD + zext($(CARRY));\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(CARRY) = tmp_carry;\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:ADDCX.A XSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x6 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmps:$(REG_SIZE) = XSRC_A_AS + zext($(CARRY));\n\ttmp:$(REG_SIZE) = tmps + XDEST_A_AD;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetaddflags(XDEST_A_AD,tmps,tmpd);\n\tbuild postIncrementStore;\n}\n\n:ANDX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xF & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Operation...\n\tresult:1 = XDEST_B_AD & XSRC_B_AS;\n\tXDEST_B_AD = result;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:ANDX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xF & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Operation...\n\tresult:2 = XDEST_W_AD & XSRC_W_AS;\n\tXDEST_W_AD = result;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:ANDX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xF & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_A_AD = XDEST_A_AD & XSRC_A_AS;\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XDEST_A_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_A_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_A_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:BICX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xC & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\tXDEST_B_AD = (~XSRC_B_AS) & XDEST_B_AD;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:BICX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xC & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\tXDEST_W_AD = (~XSRC_W_AS) & XDEST_W_AD;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:BICX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xC & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\tXDEST_A_AD = (~XSRC_A_AS) & XDEST_A_AD;\n\t#Status bits are not affected\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\tbuild postIncrementStore;\n}\n\n:BISX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xD & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\tXDEST_B_AD = XSRC_B_AS | XDEST_B_AD;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:BISX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xD & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\tXDEST_W_AD = XSRC_W_AS | XDEST_W_AD;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:BISX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xD & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\tXDEST_A_AD = XSRC_A_AS | XDEST_A_AD;\n\t#Status bits are not affected\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\tbuild postIncrementStore;\n}\n\n:BITX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xB & bow=1 & postIncrement) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\tresult:1 = XDEST_B_AD & XSRC_B_AS;\n\t# Result Flags...\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:BITX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xB & bow=0 & postIncrement) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\tresult:2 = XDEST_W_AD & XSRC_W_AS;\n\t# Result Flags...\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:BITX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xB & bow=1 & postIncrement) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\tresult:$(REG_SIZE) = XDEST_A_AD & XSRC_A_AS;\n\t# Result Flags...\n\tresult = sext(result[0,20]);\n\t$(CARRY) = (result != 0x0);\t\t\t# C Flag\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:CLRX.B\tXDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\tXDEST_B_AD = 0;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:CLRX.W\tXDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\tXDEST_W_AD = 0;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:CLRX.A\tXDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\tXDEST_A_AD = 0;\n\tbuild postIncrementStore;\n}\n\n:CMPX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=1 & postIncrement) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (XSRC_B_AS <= XDEST_B_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_B_AD, XSRC_B_AS);\t# V Flag\n\t# Operation...\n\tresult:1 = (XDEST_B_AD - XSRC_B_AS);\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:CMPX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=0 & postIncrement) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (XSRC_W_AS <= XDEST_W_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_W_AD, XSRC_W_AS);\t# V Flag\n\t# Operation...\n\tresult:2 = (XDEST_W_AD - XSRC_W_AS);\n\t# Result Flags...\n\t$(SIGN) = (result s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (result == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:CMPX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x9 & bow=1 & postIncrement) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\ttmp:$(REG_SIZE) = XDEST_A_AD - XSRC_A_AS;\n\ttmpd:$(REG_SIZE) = sext(tmp[0,20]);\n\tsetsubflags(tmpd,XSRC_A_AS,XDEST_A_AD);\n\tbuild postIncrement;\n}\n\n:DADCX.B XDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 0;\t\t\t\t# This should be overflow\n\t# Operation...\n\tXDEST_B_AD = bcd_add(XDEST_B_AD);\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DADCX.W XDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 0;\t\t\t\t\t# Don't currently have BCD overflow op\n\t# Operation...\n\tXDEST_W_AD = bcd_add(XDEST_W_AD);\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DADCX.A XDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 0;\t\t\t\t\t# Don't currently have BCD overflow op\n\t# Operation...\n\tXDEST_A_AD = bcd_add(XDEST_A_AD);\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XDEST_A_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_A_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DADDX.B XSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 0;\t\t\t\t# This should be overflow\n\t# Operation...\n\tXDEST_B_AD = bcd_add(XSRC_B_AS,XDEST_B_AD);\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DADDX.W XSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 0;\t\t\t\t\t# Don't currently have BCD overflow op\n\t# Operation...\n\tXDEST_W_AD = bcd_add(XSRC_W_AS ,XDEST_W_AD);\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DADDX.A XSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xA & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 0;\t\t\t\t\t# Don't currently have BCD overflow op\n\t# Operation...\n\tXDEST_A_AD = bcd_add(XSRC_A_AS ,XDEST_A_AD);\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XDEST_A_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_A_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DECX.B\tXDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (1 <= XDEST_B_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_B_AD, 1:1);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD - 1;\t\t\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DECX.W\tXDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (1 <= XDEST_W_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_W_AD, 1:2);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD - 1:2;\t\t\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DECX.A\tXDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmp:$(REG_SIZE) = XDEST_A_AD - 1:$(REG_SIZE);\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetsubflags(XDEST_A_AD,1:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n}\n\n:DECDX.B XDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (1 <= XDEST_B_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_B_AD, 2:1);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD - 2;\t\t\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DECDX.W XDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (1 <= XDEST_W_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_W_AD, 2:2);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD - 2:2;\t\t\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:DECDX.A XDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmp:$(REG_SIZE) = XDEST_A_AD - 2:$(REG_SIZE);\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetsubflags(XDEST_A_AD,2:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n}\n\n:INCX.B\tXDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(XDEST_B_AD,1); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XDEST_B_AD,1); \t# V Flag\n\t# Operation...\n\tXDEST_B_AD = 1 + XDEST_B_AD;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:INCX.W\tXDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(XDEST_W_AD,1); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XDEST_W_AD,1); \t# V Flag\n\t# Operation...\n\tXDEST_W_AD = 1 + XDEST_W_AD;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:INCX.A\tXDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmp:$(REG_SIZE) = 1 + XDEST_A_AD;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetaddflags(XDEST_A_AD,1:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n}\n\n:INCDX.B XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(XDEST_B_AD,2); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XDEST_B_AD,2); \t# V Flag\n\t# Operation...\n\tXDEST_B_AD = 2 + XDEST_B_AD;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:INCDX.W XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = carry(XDEST_W_AD,2); \t \t# C Flag\n\t$(OVERFLOW) = scarry(XDEST_W_AD,2); \t# V Flag\n\t# Operation...\n\tXDEST_W_AD = 2 + XDEST_W_AD;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:INCDX.A XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmp:$(REG_SIZE) = 2 + XDEST_A_AD;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetaddflags(XDEST_A_AD,1:$(REG_SIZE),tmpd);\n\tbuild postIncrementStore;\n}\n\n:INVX.B\tXDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = XDEST_B_AD s< 0x0;\t# V Flag\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD ^ -1;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_B_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:INVX.W\tXDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = XDEST_W_AD s< 0x0;\t# V Flag\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD ^ -1;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_W_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:INVX.A\tXDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = XDEST_A_AD s< 0x0;\t# V Flag\n\t# Operation...\n\tXDEST_A_AD = XDEST_A_AD ^ -1;\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XDEST_A_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_A_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_A_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:MOVX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\tXDEST_B_AD = XSRC_B_AS;\n\tbuild tbl_bzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:MOVX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\tXDEST_W_AD = XSRC_W_AS;\n\tbuild tbl_wzero;\n\t#Status bits are not affected\n\tbuild postIncrementStore;\n}\n\n:MOVX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\tXDEST_A_AD = XSRC_A_AS;\n\tbuild postIncrementStore;\n}\n\n:POPX.B\tXDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & tbl_bzero) ... & XDEST_B_AD ... {\n\tXDEST_B_AD = *:1 SP;\n\tbuild tbl_bzero;\n\tSP = SP + 0x2;\n\t#Status bits are not affected\n}\n\n:POPX.W\tXDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=0 & tbl_wzero) ... & XDEST_W_AD ... {\n\tXDEST_W_AD = *:2 SP;\n\tbuild tbl_wzero;\n\tSP = SP + 0x2;\n\t#Status bits are not affected\n}\n\n:POPX.A\tXDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1) ... & XDEST_A_AD ... {\n\tXDEST_A_AD = *:4 SP;\n\tSP = SP + 0x4;\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n}\n\n:SBCX.B XDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=1 & src16_8_4=0x3 & as=0x0 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\tbrw:1 = 1 - $(CARRY);\n $(CARRY) = (brw <= XDEST_B_AD); # Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_B_AD, brw);\t\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD - brw;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:SBCX.W XDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=0 & src16_8_4=0x3 & as=0x0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\tbrw:2 = 1 - zext( $(CARRY) );\n\t$(CARRY) = (brw <= XDEST_W_AD);\t\t# Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_W_AD, brw);\t\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD - brw;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:SBCX.A XDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x7 & bow=1 & src16_8_4=0x3 & as=0x0 & postIncrementStore) ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\tbrw:$(REG_SIZE) = 1 - zext( $(CARRY) ); \n\ttmp:$(REG_SIZE) = XDEST_A_AD - brw;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetsubflags(XDEST_A_AD,brw,tmpd);\n\tbuild postIncrementStore;\n}\n\n:SUBCX.B XSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\tbrw:1 = 1 - $(CARRY);\n $(CARRY) = ((brw + XSRC_B_AS) <= XDEST_B_AD); # Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_B_AD, XSRC_B_AS + brw);\t\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD - XSRC_B_AS - brw;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:SUBCX.W XSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\tbrw:2 = 1 - zext( $(CARRY) );\n\t$(CARRY) = ((brw + XSRC_W_AS) <= XDEST_W_AD);\t\t# Carry flag is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_W_AD, XSRC_W_AS + brw);\t\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD - XSRC_W_AS - brw;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:SUBCX.A XSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x7 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\tbrw:$(REG_SIZE) = 1 - zext( $(CARRY) ); \n\ttmps:$(REG_SIZE) = XSRC_A_AS + brw;\n\ttmp:$(REG_SIZE) = XDEST_A_AD - tmps;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetsubflags(XDEST_A_AD,tmps,tmpd);\n\tbuild postIncrementStore;\n}\n\n:SUBX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (XSRC_B_AS <= XDEST_B_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_B_AD, XSRC_B_AS);\t\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD - XSRC_B_AS;\t\t\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:SUBX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = (XSRC_W_AS <= XDEST_W_AD);\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = sborrow(XDEST_W_AD, XSRC_W_AS);\t\t\t\t\t\t\t\t# V Flag\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD - XSRC_W_AS;\t\t\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrementStore;\n}\n\n:SUBX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x8 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\ttmpd:$(REG_SIZE) = XDEST_A_AD;\n\ttmp:$(REG_SIZE) = XDEST_A_AD - XSRC_A_AS;\n\tXDEST_A_AD = sext(tmp[0,20]);\n\t\n\tsetsubflags(XDEST_A_AD,XSRC_A_AS,tmpd);\n\tbuild postIncrementStore;\n}\n\n:TSTX.B\tXDEST_B_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=1 & src16_8_4=0x3 & as=0x0 & postIncrement) ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 1;\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = 0;\t# V Flag\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:TSTX.W\tXDEST_W_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=0 & src16_8_4=0x3 & as=0x0 & postIncrement) ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(CARRY) = 1;\t\t# Carry is NOT set if there is a borrow\n\t$(OVERFLOW) = 0;\t# V Flag\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\tbuild postIncrement;\n}\n\n:TSTX.A\tXDEST_A_AD\t\t\t\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x9 & bow=1 & src16_8_4=0x3 & as=0x0 & postIncrement) ... & XDEST_A_AD ... {\n\tsetsubflags(XDEST_A_AD,0:$(REG_SIZE),XDEST_A_AD);\n\tbuild postIncrement;\n}\n\n:XORX.B\tXSRC_B_AS, XDEST_B_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XDEST_B_AD s< 0x0) && (XSRC_B_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tXDEST_B_AD = XDEST_B_AD ^ XSRC_B_AS;\n\tbuild tbl_bzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_B_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_B_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_B_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:XORX.W\tXSRC_W_AS, XDEST_W_AD\t\t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XDEST_W_AD s< 0x0) && (XSRC_W_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tXDEST_W_AD = XDEST_W_AD ^ XSRC_W_AS;\n\tbuild tbl_wzero;\n\t# Result Flags...\n\t$(SIGN) = (XDEST_W_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_W_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_W_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n:XORX.A\tXSRC_A_AS, XDEST_A_AD\t\t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xE & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XDEST_A_AD s< 0x0) && (XSRC_A_AS s< 0x0)) ;\t# V Flag\n\t# Operation...\n\tXDEST_A_AD = XDEST_A_AD ^ XSRC_A_AS;\n\tXDEST_A_AD = sext(XDEST_A_AD[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XDEST_A_AD s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XDEST_A_AD == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XDEST_A_AD != 0x0);\t\t\t# C Flag\n\tbuild postIncrementStore;\n}\n\n\n#############################\n#\n# Single Operand\n#\n#############################\n# Repeat enabled\n\n# Note: The manual says PUSHX doesn't use extension word. The manual is *WRONG*\n:PUSHX.B XRREG_B_AS \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x2 & bow=0x1 & postRegIncrement & XRREG_B_AS {\n\t\n\tSP = SP - 0x2;\n\t*:1 SP = XRREG_B_AS;\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\t\n\n:PUSHX.W XRREG_W_AS \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x2 & bow=0x0 & postRegIncrement & XRREG_W_AS {\n\t\n\tSP = SP - 0x2;\n\t*:2 SP = XRREG_W_AS;\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:PUSHX.A XRREG_A_AS \t\tis ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x2 & bow=0x1 & postRegIncrement & XRREG_A_AS {\n\t\n\tSP = SP - 0x4;\n\t*:$(REG_SIZE) SP = XRREG_A_AS;\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\t\n\n:RRAX.B XRREG_B_AS_DEST \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x1 & bow=0x1 & postRegIncrement & XRREG_B_AS_DEST {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\t$(CARRY) = (XRREG_B_AS_DEST & 0x1);\n\tXRREG_B_AS_DEST = XRREG_B_AS_DEST s>> 1;\n\t# Result Flags...\n\t$(SIGN) = (XRREG_B_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_B_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RRAX.W XRREG_W_AS_DEST \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x1 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\t$(CARRY) = XRREG_W_AS_DEST[0,1];\n\tXRREG_W_AS_DEST = XRREG_W_AS_DEST s>> 1; \n\t# Result Flags...\n\t$(SIGN) = (XRREG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RRAX.A XRREG_A_AS_DEST \t\tis ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x1 & bow=0x1 & postRegIncrement & XRREG_A_AS_DEST {\n\t\n\t$(CARRY) = XRREG_A_AS_DEST[0,1];\n\tXRREG_A_AS_DEST = (XRREG_A_AS_DEST s>> 1);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (XRREG_A_AS_DEST[19,1] != 0);\n\t$(ZERO) = (XRREG_A_AS_DEST == 0);\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RRCX.B XRREG_B_AS_DEST \t\tis ctx_haveext=4 & ctx_al=1 & ctx_zc & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x1 & postRegIncrement & XRREG_B_AS_DEST & repeat_carry {\n\t\n\t# Operation Flags...\n\tbuild repeat_carry;\n\t$(OVERFLOW) = ((XRREG_B_AS_DEST != 0x0) && ($(CARRY) == 0x1));\t# V Flag\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = (XRREG_B_AS_DEST & 0x1);\n\tXRREG_B_AS_DEST = ((tmp << 0x7) | (XRREG_B_AS_DEST >> 0x1));\n\t# Result Flags...\n\t$(SIGN) = (XRREG_B_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_B_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RRCX.W XRREG_W_AS_DEST \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XRREG_W_AS_DEST != 0x0) && ($(CARRY) == 0x1));\t# V Flag\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = XRREG_W_AS_DEST[0,1];\n\tXRREG_W_AS_DEST = ((zext(tmp) << 0xF) | (XRREG_W_AS_DEST >> 0x1));\n\t# Result Flags...\n\t$(SIGN) = (XRREG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:RRCX.A XRREG_A_AS_DEST \t\tis ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x1 & postRegIncrement & XRREG_A_AS_DEST & repeat_carry {\n\t\n\tbuild repeat_carry;\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XRREG_A_AS_DEST != 0x0) && ($(CARRY) == 0x1));\t# V Flag\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = XRREG_A_AS_DEST[0,1];\n\tXRREG_A_AS_DEST = ((zext(tmp) << 0x13) | ((XRREG_A_AS_DEST >> 0x1) & 0xEFFFF));\n\tXRREG_A_AS_DEST = sext(XRREG_A_AS_DEST[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XRREG_A_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_A_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SWPBX.W XRREG_W_AS_DEST \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST {\n\t\n\tlowByte:1 = XRREG_W_AS_DEST[0,8];\n\thighByte:1 = XRREG_W_AS_DEST[8,8];\n\tXRREG_W_AS_DEST = (((zext(lowByte)) << 0x8) | zext(highByte));\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SWPBX.A XRREG_A_AS_DEST2 \t\tis ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_A_AS_DEST2 {\n\t\n\tlowByte:1 = XRREG_A_AS_DEST2[0,8];\n\thighByte:1 = XRREG_A_AS_DEST2[8,8];\n\tXRREG_A_AS_DEST2[8,8] = lowByte;\n\tXRREG_A_AS_DEST2[0,8] = highByte;\n\tXRREG_A_AS_DEST2 = zext(XRREG_A_AS_DEST2[0,20]);\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SXTX.W XRREG_W_AS_DEST \t\tis ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t\t# V Flag\n\t# Operation...\t\n\tXRREG_W_AS_DEST = sext(XRREG_W_AS_DEST:1);\n\t# Result Flags...\n\t$(SIGN) = (XRREG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XRREG_W_AS_DEST != 0x0);\t\t\t# C Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n:SXTX.A XRREG_A_AS_DEST2\t\tis ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_A_AS_DEST2 {\n\t\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t\t# V Flag\n\t# Operation...\t\n\tXRREG_A_AS_DEST2 = sext(XRREG_A_AS_DEST2:1);\n\t# Result Flags...\n\t$(SIGN) = (XRREG_A_AS_DEST2 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XRREG_A_AS_DEST2 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XRREG_A_AS_DEST2 != 0x0);\t\t\t# C Flag\n\tbuild postRegIncrement;\n\tif (CNT == 0) goto inst_next;\n\tCNT = CNT - 1;\n\tgoto ;\n}\n\n#############################\n# No Repeat\n:PUSHX.B XREG_B_AS \t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_B_AS {\n\tSP = SP - 0x2;\n\t*:1 SP = XREG_B_AS;\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n}\t\n\n:PUSHX.W XREG_W_AS \t\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & XREG_W_AS {\n\tSP = SP - 0x2;\n\t*:2 SP = XREG_W_AS;\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n}\n\n:PUSHX.A XREG_A_AS \t\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_A_AS {\n\tSP = SP - 0x4;\n\t*:$(REG_SIZE) SP = XREG_A_AS;\n\tbuild postRegIncrement;\n}\t\n\n:RRAX.B XREG_B_AS_DEST \tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_B_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\t$(CARRY) = (XREG_B_AS_DEST & 0x1);\n\tXREG_B_AS_DEST = XREG_B_AS_DEST s>> 1;\n\t# Result Flags...\n\t$(SIGN) = (XREG_B_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_B_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n:RRAX.W XREG_W_AS_DEST \tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t# V Flag (reset)\n\t# Operation...\n\t$(CARRY) = XREG_W_AS_DEST[0,1];\n\tXREG_W_AS_DEST = XREG_W_AS_DEST s>> 1;\n\t# Result Flags...\n\t$(SIGN) = (XREG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n:RRAX.A XREG_A_AS_DEST \tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_A_AS_DEST {\n\t$(CARRY) = XREG_A_AS_DEST[0,1];\n\tXREG_A_AS_DEST = (XREG_A_AS_DEST s>> 1);\n\t$(OVERFLOW) = 0;\n\t$(SIGN) = (XREG_A_AS_DEST[19,1] != 0);\n\t$(ZERO) = (XREG_A_AS_DEST == 0);\n\tbuild postRegIncrement;\n}\n\n:RRCX.B XREG_B_AS_DEST \tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_B_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XREG_B_AS_DEST != 0x0) && ($(CARRY) == 0x1));\t# V Flag\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = (XREG_B_AS_DEST & 0x1);\n\tXREG_B_AS_DEST = ((tmp << 0x7) | (XREG_B_AS_DEST >> 0x1));\n\t# Result Flags...\n\t$(SIGN) = (XREG_B_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_B_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n:RRCX.W XREG_W_AS_DEST\tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XREG_W_AS_DEST != 0x0) && ($(CARRY) == 0x1));\t# V Flag\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = XREG_W_AS_DEST[0,1];\n\tXREG_W_AS_DEST = ((zext(tmp) << 0xF) | (XREG_W_AS_DEST >> 0x1));\n\t# Result Flags...\n\t$(SIGN) = (XREG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n:RRCX.A XREG_A_AS_DEST \tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_A_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = ((XREG_A_AS_DEST != 0x0) && ($(CARRY) == 0x1));\t# V Flag\n\t# Operation...\n\ttmp:1 = $(CARRY);\n\t$(CARRY) = XREG_A_AS_DEST[0,1];\n\tXREG_A_AS_DEST = ((zext(tmp) << 0x13) | ((XREG_A_AS_DEST >> 0x1) & 0xEFFFF));\n\tXREG_A_AS_DEST = sext(XREG_A_AS_DEST[0,20]);\n\t# Result Flags...\n\t$(SIGN) = (XREG_A_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_A_AS_DEST == 0x0);\t\t\t# Z Flag\n\tbuild postRegIncrement;\n}\n\n:SWPBX.W XREG_W_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST {\n\tlowByte:1 = XREG_W_AS_DEST[0,8];\n\thighByte:1 = XREG_W_AS_DEST[8,8];\n\tXREG_W_AS_DEST = (((zext(lowByte)) << 0x8) | zext(highByte));\n\t#Status bits are not affected\n\tbuild postRegIncrement;\n}\n\n# Yes, for SXTX and SWPB, the normal width selectors are different. Hence, for the A versions, we have a different dest reg subtable.\n:SWPBX.A XREG_A_AS_DEST2 is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_A_AS_DEST2 {\n\tlowByte:1 = XREG_A_AS_DEST2[0,8];\n\thighByte:1 = XREG_A_AS_DEST2[8,8];\n\tXREG_A_AS_DEST2[8,8] = lowByte;\n\tXREG_A_AS_DEST2[0,8] = highByte;\n\tXREG_A_AS_DEST2 = zext(XREG_A_AS_DEST2[0,20]);\n\tbuild postRegIncrement;\n}\n\n:SXTX.W XREG_W_AS_DEST \tis ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t\t# V Flag\n\t# Operation...\t\n\tXREG_W_AS_DEST = sext(XREG_W_AS_DEST:1);\n\t# Result Flags...\n\t$(SIGN) = (XREG_W_AS_DEST s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_W_AS_DEST == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XREG_W_AS_DEST != 0x0);\t\t\t# C Flag\n\tbuild postRegIncrement;\n}\n\n# Yes, for SXTX and SWPB, the normal width selectors are different. Hence, for the A versions, we have a different dest reg subtable.\n:SXTX.A XREG_A_AS_DEST2\tis ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_A_AS_DEST2 {\n\t# Operation Flags...\n\t$(OVERFLOW) = 0x0;\t\t\t\t\t\t# V Flag\n\t# Operation...\t\n\tXREG_A_AS_DEST2 = sext(XREG_A_AS_DEST2:1);\n\t# Result Flags...\n\t$(SIGN) = (XREG_A_AS_DEST2 s< 0x0);\t\t\t# S Flag\n\t$(ZERO) = (XREG_A_AS_DEST2 == 0x0);\t\t\t# Z Flag\n\t$(CARRY) = (XREG_A_AS_DEST2 != 0x0);\t\t\t# C Flag\n\tbuild postRegIncrement;\n}\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n \n \n \n \t\t\n \n\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t\n \n \n \n \n \n \n \n \n \n \n \t\n \n \n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430.dwarf", "content": "\n\t\n \n \n \n\t\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430.ldefs", "content": "\n\n\n \n TI MSP430 16-Bit MicroController\n \n \n \n \n \n \n TI MSP430X 20-Bit MicroController\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430.pspec", "content": "\n\n\n \n \n \n\n \n\n \n \n 64K\"/>\n \n \n \n \n \n \n \n \n \n \n\n\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n \t\n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430.slaspec", "content": "@define ENDIAN \"little\"\n@define REG_SIZE \"2\"\n\n@include \"TI430Common.sinc\"\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430X.cspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\t\n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t\n \n \n \n\t\n\t\n\t\n\t\n\t\n\t\n \n \n \n \n \n \n \n \n \n \n \t\n \n \n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430X.dwarf", "content": "\n\t\n \n \n \n\t\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/TI_MSP430X.slaspec", "content": "@define ENDIAN \"little\"\n@define REG_SIZE \"4\"\n\n@include \"TI430Common.sinc\"\n@include \"TI430X.sinc\"\n" }, { "path": "pypcode/processors/TI_MSP430/data/languages/ti_msp430.opinion", "content": "\n\t\n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/TI_MSP430/data/manuals/MSP430.idx", "content": "@MSP430.pdf[TI MSP430x2xx Family User's Guide, 2008, SLAU144E]\nADC, 177\nADD, 178\nADDC, 179\nAND, 180\nBIC, 181\nBIS, 182\nBIT, 183\nBR, 184\nBRANCH, 184\nCALL, 185\nCLR, 186\nCLRC, 187\nCLRN, 188\nCLRZ, 189\nCMP, 190\nDADC, 191\nDADD, 192\nDEC, 193\nDECD, 194\nDINT, 195\nEINT, 196\nINC, 197\nINCD, 198\nINV, 199\nJC, 200\nJHS, 200\nJEQ, 201\nJZ, 201\nJGE, 202\nJL, 203\nJMP, 204\nJN, 205\nJNC, 206\nJLO, 206\nJNZ, 207\nJNE, 207\nMOV, 208\nNOP, 209\nPOP, 210\nPUSH, 211\nRET, 212\nRETI, 213\nRLA, 214\nRLC, 215\nRRA, 216\nRRC, 217\nSBC, 218\nSETC, 219\nSETN, 220\nSETZ, 221\nSUB, 222\nSUBC, 223\nSWPB, 224\nSXT, 225\nTST, 226\nXOR, 227\nADCX, 229\nADDX, 230\nADDCX, 231\nANDX, 232\nBICX, 233\nBISX, 234\nBITX, 235\nCLRX, 236\nCMPX, 237\nDADCX, 238\nDADDX, 239\nDECX, 240\nDECDX, 241\nINCX, 242\nINCDX, 243\nINVX, 244\nMOVX, 245\nPOPM, 247\nPUSHM, 248\nPOPX, 249\nPUSHX, 250\nRLAM, 251\nRLAX, 252\nRLCX, 253\nRRAM, 254\nRRAX, 255\nRRCM, 257\nRRCX, 258\nRRUM, 260\nRRUX, 261\nSBCX, 262\nSUBX, 263\nSUBCX, 264\nSWPBX, 265\nSXTX, 267\nTSTX, 269\nXORX, 270\nADDA, 272\nBRA, 273\nCALLA, 275\nCLRA, 277\nCMPA, 278\nDECDA, 279\nINCDA, 280\nMOVA, 281\nRETA, 283\nTSTA, 284\nSUBA, 285\n" }, { "path": "pypcode/processors/Toy/data/languages/old/ToyV00BE64.lang", "content": "\n\n \n \n Toy:BE:64:default\n Toy\n default\n 64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/ToyV0BE64.trans", "content": "\n\n Toy:BE:64:default\n Toy:BE:64:default\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/ToyV0LE64.lang", "content": "\n\n \n \n Toy:LE:64:default\n Toy\n default\n 64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/ToyV0LE64.trans", "content": "\n\n Toy:LE:64:default\n Toy:LE:64:default\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/v01stuff/toy.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/v01stuff/toy.ldefs_v01", "content": "\n\n\n \n Toy (test) processor 64-bit big-endian\n \n \n \n Toy (test) processor 64-bit little-endian\n \n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/v01stuff/toy.sinc", "content": "# Main slaspec must define endianness and alignment\n\n@ifndef WORDSIZE\n@define WORDSIZE \"1\"\n@endif\n\ndefine space ROM type=ram_space size=$(SIZE) wordsize=$(WORDSIZE) default;\n\ndefine space register type=register_space size=2;\n\ndefine register offset=0x1000 size=$(SIZE) [\n a0 a1 a2 a3 a4 a5 a6 a7\n a8 a9 a10 a11 a12 sp lr pc\n];\n\n# STATUS REGISTER MAP: (LOW)\n# C - CARRY\n# Z - ZERO\n# N - NEGATIVE\n# V - OVERFLOW\n\ndefine register offset=0x1100 size=1 [\n C Z N V\n];\n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/v01stuff/toy64.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/old/v01stuff/toyInstructions.sinc", "content": "#### immediates\n# 0iii dddd iiii iiii # imm rd, i load 11-bit unsigned int into rd\n# 10nn dddd nnnn nnnn # simm rd, n load 10-bit signed int into rd\n# \n#### arithmetic\n# 1100 0000 ssss tttt # add rs, rt rs = rs + rt\n# 1100 0001 ssss tttt # sub rs, rt rs = rs - rt\n# 1100 0010 ssss tttt # rsub rs, rt rs = rt - rs\n# 1100 0011 ssss tttt # mul rs, rt rs = rs * rt\n# 1100 0100 ssss tttt # div rs, rt rs = rs / rt\n# 1100 0101 ssss tttt # mod rs, rt rs = rs % rt\n# 1100 0110 ssss tttt # cmp rs, rt (set status only based on signed compare (rs - rt))\n# 1100 0111 ssss tttt # ucmp rs, rt (set status only based on unsigned compare (rs - rt))\n# \n# 1100 1000 ssss nnnn # add rs, n rs = rs + n\n# 1100 1001 ssss nnnn # sub rs, n rs = rs - n\n# 1100 1010 ssss nnnn # rsub rs, n rs = n - rs\n# 1100 1011 ssss nnnn # mul rs, n rs = rs * n\n# 1100 1100 ssss nnnn # div rs, n rs = rs / n\n# 1100 1101 ssss iiii # mod rs, i rs = rs % i\n# 1100 1110 ssss nnnn # cmp rs, n (set status only based on signed compare (rs - n))\n# 1100 1111 ssss iiii # ucmp rs, i (set status only based on unsigned compare (rs - i))\n# \n#### logic\n# 1101 0000 ssss tttt # and rs, rt rs = rs & rt\n# 1101 0001 ssss tttt # or rs, rt rs = rs | rt\n# 1101 0010 ssss tttt # xor rs, rt rs = rs ^ rt\n# 1101 0011 ssss tttt # lsr rs, rt rs = rs >> rt\n# 1101 0100 ssss tttt # asr rs, rt rs = rs s>> rt\n# 1101 0101 ssss tttt # lsl rs, rt rs = rs << rt\n# 1101 1000 ssss tttt # saa rs, rt rs = (rs << 11) | rt\n# \n# 1101 1011 ssss iiii # lsr rs, i rs = rs >> i\n# 1101 1100 ssss iiii # asr rs, i rs = rs s>> i\n# 1101 1101 ssss iiii # lsl rs, i rs = rs << i\n# 1101 1110 ssss 0000 # inv rs rs = ~rs\n# 1101 1110 ssss 0001 # neg rs rs = -rs\n# \n#### memory\n# 1101 0110 ssss tttt # load rs, [rt] rs = [rt]\n# 1101 0111 ssss tttt # store [rs], rt [rs] = rt\n# 1101 1111 ssss tttt # mov rs, rt rs = rt\n# \n#### flow\n# 1110 nnnn nnnn 0ccc # brcc n if ccc goto pc + n\n# 1110 nnnn nnnn 1ccc # brdscc n if ccc goto pc + n with delay slot\n# 1111 0000 ssss 0ccc # brcc rs if ccc goto rs & ~1\n# 1111 0001 ssss 0ccc # brdscc rs if ccc goto rs & ~1 with delay slot\n# 1111 0010 ssss 0000 # push rs push rs\n# 1111 0011 ssss 0000 # pop rs pop rs\n# 1111 0100 0000 0000 # ret return\n# 1111 0101 nnnn nnnn # callds n call n with delay slot\n# 1111 0110 ssss 0000 # call rs call rs\n# 1111 1nnn nnnn nnnn # call n call n\n#\n#### RESERVED\n# 1101 1001 xxxx xxxx # RESERVED BANK\n# 1101 1010 xxxx xxxx # RESERVED BANK\n# 1111 0111 xxxx xxxx # RESERVED BANK\n\n\ndefine token instr(16)\n\top1515 = (15, 15)\n\top1415 = (14, 15)\n\top1215 = (12, 15)\n\top1111 = (11, 11)\n\top0811 = (8, 11)\n\top0007 = (0, 7)\n\top0003 = (0, 3)\n\top0303 = (3, 3)\n\trd = (8, 11)\n\trs = (4, 7)\n\trt = (0, 3)\n\timm1214 = (12, 14)\n\timm0007 = (0, 7)\n\timm0003 = (0, 3)\n\tsimm1213 = (12, 13) signed\n\tsimm0010 = (0, 10) signed\n\tsimm0411 = (4, 11) signed\n\tsimm0007 = (0, 7) signed\n\tsimm0003 = (0, 3) signed\n\tcc0911 = (9, 11)\n\tcc0002 = (0, 2)\n;\n\nattach variables [ rd rs rt ] [\n a0 a1 a2 a3 a4 a5 a6 a7\n a8 a9 a10 a11 a12 sp lr pc\n];\n\n# addressing mode subs\n\nSimm4: \"#\"^simm0003 is simm0003 { export *[const]:$(SIZE) simm0003; }\nSimm10: \"#\"^computed is simm1213 & imm0007 [ computed = (simm1213 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; }\n\nImm4: \"#\"^imm0003 is imm0003 { export *[const]:$(SIZE) imm0003; }\nImm11: \"#\"^computed is imm1214 & imm0007 [ computed = (imm1214 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; }\n\nRel8: addr is simm0007 [ addr = inst_start + simm0007; ] { export *:$(SIZE) addr; }\nRel82: addr is simm0411 [ addr = inst_start + simm0411; ] { export *:$(SIZE) addr; }\nRel11: addr is simm0010 [ addr = inst_start + simm0010; ] { export *:$(SIZE) addr; }\n\nRS: [rs] is rs { export *[ROM]:$(SIZE) rs; }\nRT: [rt] is rt { export *[ROM]:$(SIZE) rt; }\n\nCC: \"eq\" is cc0002=0x0 { export Z; }\nCC: \"ne\" is cc0002=0x1 { tmp = !Z; export tmp; }\nCC: \"lt\" is cc0002=0x2 { tmp = N != V; export tmp; }\nCC: \"le\" is cc0002=0x3 { tmp = Z || (N != V); export tmp; }\nCC: \"lo\" is cc0002=0x4 { export C; }\nCC: \"mi\" is cc0002=0x5 { export N; }\nCC: \"vs\" is cc0002=0x6 { export V; }\nCC: \"\" is cc0002=0x7 { export 1:1; }\n\nCOND: CC is CC { if (!CC) goto inst_next; }\nCOND: CC is CC & cc0002=0x7 { } # unconditional\n\nmacro resultflags(result) {\n\tN = result s< 0;\n\tZ = result == 0;\n}\nmacro addflags(a, b) {\n\tC = carry(a, b);\n\tV = scarry(a, b);\n}\nmacro subflags(a, b) {\n\tC = a s< b;\n\tV = sborrow(a, b);\n}\nmacro logicflags() {\n\tC = 0;\n\tV = 0;\n}\n\n# operations\n\n:imm rd, Imm11 is $(INSTR_PHASE) op1515=0x0 & rd & Imm11 { logicflags(); rd = Imm11; resultflags(rd); }\n:simm rd, Simm10 is $(INSTR_PHASE) op1415=0x2 & rd & Simm10 { logicflags(); rd = Simm10; resultflags(rd); }\n\n:add rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x0 & rs & rt { addflags(rs, rt); rs = rs + rt; resultflags(rs); }\n:sub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x1 & rs & rt { subflags(rs, rt); rs = rs - rt; resultflags(rs); }\n:rsub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x2 & rs & rt { subflags(rt, rs); rs = rt - rs; resultflags(rs); }\n:mul rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x3 & rs & rt { rs = rs * rt; resultflags(rs); } # fix C & V\n:div rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x4 & rs & rt { rs = rs / rt; resultflags(rs); } # fix C & V\n:mod rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x5 & rs & rt { rs = rs % rt; resultflags(rs); } # fix C & V\n:cmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x6 & rs & rt { subflags(rs, rt); tmp:$(SIZE) = rs - rt; resultflags(tmp); }\n:ucmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x7 & rs & rt { logicflags(); N = rs < rt; Z = rs == rt; }\n\n:add rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x8 & rs & Simm4 { addflags(rs, Simm4); rs = rs + Simm4; resultflags(rs); }\n:sub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x9 & rs & Simm4 { subflags(rs, Simm4); rs = rs - Simm4; resultflags(rs); }\n:rsub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xa & rs & Simm4 { subflags(Simm4, rs); rs = Simm4 - rs; resultflags(rs); }\n:mul rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xb & rs & Simm4 { rs = rs * Simm4; resultflags(rs); } # fix C & V\n:div rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xc & rs & Simm4 { rs = rs / Simm4; resultflags(rs); } # fix C & V\n:mod rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xd & rs & Imm4 { rs = rs % Imm4; resultflags(rs); } # fix C & V\n:cmp rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xe & rs & Simm4 { subflags(rs, Simm4); tmp:$(SIZE) = rs - Simm4; resultflags(tmp); }\n:ucmp rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xf & rs & Imm4 { logicflags(); N = rs < Imm4; Z = rs == Imm4; }\n\n:and rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x0 & rs & rt { logicflags(); rs = rs & rt; resultflags(rs); }\n:or rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x1 & rs & rt { logicflags(); rs = rs | rt; resultflags(rs); }\n:xor rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x2 & rs & rt { logicflags(); rs = rs ^ rt; resultflags(rs); }\n:lsr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x3 & rs & rt { logicflags(); rs = rs >> rt; resultflags(rs); }\n:asr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x4 & rs & rt { logicflags(); rs = rs s>> rt; resultflags(rs); }\n:lsl rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x5 & rs & rt { logicflags(); rs = rs << rt; resultflags(rs); }\n\n# saa == shift and accumulate; very useful for building up a 32 bit or 64 bit value in pieces, like:\n# imm r12, #32b\n# imm r11, #7d7\n# saa r12, r11\n# imm r11, #2be\n# saa r12, r11\n#\n# now r12 contains '0xcafebabe' (decompiler reconstitutes the pieces seamlessly)\n\n:saa rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x8 & rs & rt { logicflags(); rs = (rs << 11) | rt; resultflags(rs); }\n\n:lsr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xb & rs & Imm4 { logicflags(); rs = rs >> Imm4; resultflags(rs); }\n:asr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xc & rs & Imm4 { logicflags(); rs = rs s>> Imm4; resultflags(rs); }\n:lsl rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xd & rs & Imm4 { logicflags(); rs = rs << Imm4; resultflags(rs); } # fix C & V\n:inv rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x0 { logicflags(); rs = ~rs; resultflags(rs); }\n:neg rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x1 { logicflags(); rs = -rs; resultflags(rs); }\n\n:load rs, RT is $(INSTR_PHASE) op1215=0xd & op0811=0x6 & rs & RT { rs = RT; logicflags(); resultflags(rs); }\n:store RS, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x7 & RS & rt { RS = rt; logicflags(); resultflags(rt); }\n:mov rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0xf & rs & rt { rs = rt; logicflags(); resultflags(rs); }\n\n:br^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x0 & COND & Rel82 { build COND; goto Rel82; }\n:brds^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x1 & COND & Rel82 { build COND; delayslot(1); goto Rel82; }\n:br^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x0 & COND & rs & op0303=0x0 { build COND; goto [rs]; }\n:brds^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x1 & COND & rs & op0303=0x0 { build COND; delayslot(1); goto [rs]; }\n@ifdef POS_STACK\n:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ROM]:$(SIZE) sp = rs; sp = sp + $(SIZE); logicflags(); resultflags(rs); }\n:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp - $(SIZE); rs = *[ROM]:$(SIZE) sp; logicflags(); resultflags(rs); }\n@else\n:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ROM]:$(SIZE) sp = rs; sp = sp - $(SIZE); logicflags(); resultflags(rs); }\n:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp + $(SIZE); rs = *[ROM]:$(SIZE) sp; logicflags(); resultflags(rs); }\n@endif\n:ret is $(INSTR_PHASE) op1215=0xf & op0811=0x4 & op0007=0x0 { return [lr]; }\n:callds Rel8 is $(INSTR_PHASE) op1215=0xf & op0811=0x5 & Rel8 { delayslot(1); lr = inst_next; call Rel8; }\n:call rs is $(INSTR_PHASE) op1215=0xf & op0811=0x6 & rs & op0003=0x0 { lr = inst_next; call [rs]; }\n:call Rel11 is $(INSTR_PHASE) op1215=0xf & op1111=0x1 & Rel11 { lr = inst_next; call Rel11; }\n" }, { "path": "pypcode/processors/Toy/data/languages/old/v01stuff/toyPosStack.cspec", "content": "\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy.cspec", "content": "\n\n\n \n\t \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy.ldefs", "content": "\n\n\n \n Toy (test) processor 32-bit big-endian\n \n \n \n Toy (test) processor 32-bit big-endian\n \n \n \n Toy (test) processor 32-bit little-endian\n \n \n \n Toy (test) processor 32-bit big-endian (wordsize=2)\n \n \n \n Toy (test) processor 32-bit little-endian (wordsize=2)\n \n \n \n Toy (test) processor 64-bit big-endian\n \n \n \n \n Toy (test) processor 64-bit big-endian Harvard\n \n \n \n Toy (test) processor 64-bit big-endian Harvard\n \n \n \n Toy (test) processor 64-bit little-endian\n \n \n \n Toy (test-builder) processor 32-bit big-endian\n \n \n \n Toy (test-builder) processor 32-bit little-endian\n \n \n \n Toy (test-builder) processor 32-bit big-endian word-aligned\n \n \n \n Toy (test-builder) processor 32-bit little-endian word-aligned\n \n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy.sinc", "content": "# Main slaspec must define ENDIAN and ALIGN\n\n@ifndef WORDSIZE\n@define WORDSIZE \"1\"\n@endif\n\n@ifndef ALIGN\n@define ALIGN \"1\"\n@endif\n\n@ifndef ALREADY_ENDIAN_ALIGN\ndefine endian=$(ENDIAN);\ndefine alignment=$(ALIGN);\n@endif\n\ndefine space ram type=ram_space size=$(SIZE) wordsize=$(WORDSIZE) default;\n\ndefine space register type=register_space size=2;\n\ndefine register offset=0x1000 size=$(SIZE) [\n r0 r1 r2 r3 r4 r5 r6 r7\n r8 r9 r10 r11 r12 sp lr pc\n];\n\ndefine ram offset=0x0 size=$(SIZE) [\n mmr0\n];\n\n# STATUS REGISTER MAP: (LOW)\n# C - CARRY\n# Z - ZERO\n# N - NEGATIVE\n# V - OVERFLOW\n\ndefine register offset=0x1100 size=1 [\n C Z N V\n];\n\n\n@if SIZE == \"4\"\n@define HALFSIZE \"2\"\n@endif\n@if SIZE == \"8\"\n@define HALFSIZE \"4\"\n@endif\n\n@if ENDIAN == \"little\"\ndefine register offset=0x1000 size=$(HALFSIZE) [\n r0l r0h r1l r1h r2l r2h r3l r3h r4l r4h r5l r5h r6l r6h r7l r7h\n r8l r8h r9l r9h r10l r10h r11l r11h r12l r12h spl sph lrl lrh pcl pch\n];\n@else # ENDIAN == \"big\"\ndefine register offset=0x1000 size=$(HALFSIZE) [\n r0h r0l r1h r1l r2h r2l r3h r3l r4h r4l r5h r5l r6h r6l r7h r7l\n r8h r8l r9h r9l r10h r10l r11h r11l r12h r12l sph spl lrh lrl pch pcl\n];\n@endif # ENDIAN\n" }, { "path": "pypcode/processors/Toy/data/languages/toy64-long8.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy64.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy64_be.slaspec", "content": "@define ENDIAN \"big\"\n@define SIZE \"8\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy64_be_harvard.slaspec", "content": "@define ENDIAN \"big\"\n@define SIZE \"8\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"data\"\n\n@include \"toy.sinc\"\n\ndefine space data type=ram_space size=$(SIZE) wordsize=$(WORDSIZE);\n\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy64_be_harvard_rev.slaspec", "content": "@define ENDIAN \"big\"\n@define SIZE \"8\"\n@define WORDSIZE \"1\"\n@define ALIGN \"1\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"data\"\n\n@define ALREADY_ENDIAN_ALIGN\ndefine endian=$(ENDIAN);\ndefine alignment=$(ALIGN);\ndefine space data type=ram_space size=$(SIZE) wordsize=$(WORDSIZE);\n\n@include \"toy.sinc\"\n\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy64_le.slaspec", "content": "@define ENDIAN \"little\"\n@define SIZE \"8\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toyInstructions.sinc", "content": "#### load immediate 0000 000x xxxx xxxx\n# 00ii dddd iiii iiii # imm rd, i load 10-bit unsigned int into rd\n# 01nn dddd nnnn nnnn # simm rd, n load 10-bit signed int into rd\n#\n#### misc 100x xxxx xxxx xxxx\n# 1000 0000 0000 0ccc # skcc\t\t\t\t if ccc goto inst_next2 (conditional skip instruction)\n#\n#### arithmetic 1100 xxxx\n# 1100 0000 ssss tttt # add rs, rt rs = rs + rt\n# 1100 0001 ssss tttt # sub rs, rt rs = rs - rt\n# 1100 0010 ssss tttt # rsub rs, rt rs = rt - rs\n# 1100 0011 ssss tttt # mul rs, rt rs = rs * rt\n# 1100 0100 ssss tttt # div rs, rt rs = rs / rt\n# 1100 0101 ssss tttt # mod rs, rt rs = rs % rt\n# 1100 0110 ssss tttt # cmp rs, rt (set status only based on signed compare (rs - rt))\n# 1100 0111 ssss tttt # ucmp rs, rt (set status only based on unsigned compare (rs - rt))\n# \n# 1100 1000 ssss nnnn # add rs, n rs = rs + n\n# 1100 1001 ssss nnnn # sub rs, n rs = rs - n\n# 1100 1010 ssss nnnn # rsub rs, n rs = n - rs\n# 1100 1011 ssss nnnn # mul rs, n rs = rs * n\n# 1100 1100 ssss nnnn # div rs, n rs = rs / n\n# 1100 1101 ssss iiii # mod rs, i rs = rs % i\n# 1100 1110 ssss nnnn # cmp rs, n (set status only based on signed compare (rs - n))\n# 1100 1111 ssss iiii # ucmp rs, i (set status only based on unsigned compare (rs - i))\n# \n#### logic\n# 1101 0000 ssss tttt # and rs, rt rs = rs & rt\n# 1101 0001 ssss tttt # or rs, rt rs = rs | rt\n# 1101 0010 ssss tttt # xor rs, rt rs = rs ^ rt\n# 1101 0011 ssss tttt # lsr rs, rt rs = rs >> rt\n# 1101 0100 ssss tttt # asr rs, rt rs = rs s>> rt\n# 1101 0101 ssss tttt # lsl rs, rt rs = rs << rt\n# 1101 1000 ssss tttt # saa rs, rt rs = (rs << 11) | rt\n# \n# 1101 1011 ssss iiii # lsr rs, i rs = rs >> i\n# 1101 1100 ssss iiii # asr rs, i rs = rs s>> i\n# 1101 1101 ssss iiii # lsl rs, i rs = rs << i\n# 1101 1110 ssss 0000 # inv rs rs = ~rs\n# 1101 1110 ssss 0001 # neg rs rs = -rs\n# \n#### memory\n# 1101 0110 ssss tttt # load rs, [rt] rs = [rt]\n# 1101 0111 ssss tttt # store [rs], rt [rs] = rt\n# 1101 1111 ssss tttt # mov rs, rt rs = rt\n\n#### flow\n# 1110 nnnn nnnn 0ccc # brcc n if ccc goto pc + n\n# 1110 nnnn nnnn 1ccc # brdscc n if ccc goto pc + n with delay slot\n# 1111 0000 ssss 0ccc # brcc rs if ccc goto rs & ~1\n# 1111 0001 ssss 0ccc # brdscc rs if ccc goto rs & ~1 with delay slot\n# 1111 0010 ssss 0000 # push rs push rs\n# 1111 0011 ssss 0000 # pop rs pop rs\n# 1111 0100 0000 0000 # ret return\n# 1111 0101 nnnn nnnn # callds n call n with delay slot\n# 1111 0110 ssss 0000 # call rs call rs\n# 1111 0110 ssss 1ccc # call rs if ccc call rs\n# 1111 1nnn nnnn nnnn # call n call n\n#\n#### user-defined 1010 xxxx\n# 1010 0010 ssss 0000 # user_one rs user_one rs\n# 1010 0010 ssss 0000 # user_two rs user_two rs\n# 1010 0011 0000 0000 # user_three user_three \n# 1010 0100 ssss tttt # user_four rs rt user_four rs rt \n# 1010 0101 nnnn nnnn # user_five n user_five n \n# 1010 0110 ssss 0000 # user_six rs user_six rs\n# 1010 1000 0000 0000 # unimpl\n#\n#### RESERVED / UNUSED\n# 1011 xxxx xxxx xxxx # UNUSED\n# 1101 1001 xxxx xxxx # RESERVED BANK (consumed by toy_builder.sinc)\n# 1101 1010 xxxx xxxx # RESERVED BANK (consumed by toy_builder.sinc)\n# 1111 0111 xxxx xxxx # RESERVED BANK (consumed by toy_builder.sinc)\n\ndefine token instr(16)\n\top1515 = (15, 15)\n\top1415 = (14, 15)\n\top1215 = (12, 15)\n\top1111 = (11, 11)\n\top0811 = (8, 11)\n\top0407 = (4, 7)\n\top0007 = (0, 7)\n\top0003 = (0, 3)\n\top0303 = (3, 3)\n\trd = (8, 11)\n\trs = (4, 7)\n\trt = (0, 3)\n\timm1213 = (12, 13)\n\timm0007 = (0, 7)\n\timm0003 = (0, 3)\n\tsimm1213 = (12, 13) signed\n\tsimm0010 = (0, 10) signed\n\tsimm0411 = (4, 11) signed\n\tsimm0007 = (0, 7) signed\n\tsimm0003 = (0, 3) signed\n\tcc0911 = (9, 11)\n\tcc0002 = (0, 2)\n;\n\nattach variables [ rd rs rt ] [\n r0 r1 r2 r3 r4 r5 r6 r7\n r8 r9 r10 r11 r12 sp lr pc\n];\n\n# addressing mode subs\n\nSimm4: \"#\"^simm0003 is simm0003 { export *[const]:$(SIZE) simm0003; }\nSimm10: \"#\"^computed is simm1213 & imm0007 [ computed = (simm1213 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; }\n\nImm4: \"#\"^imm0003 is imm0003 { export *[const]:$(SIZE) imm0003; }\nImm10: \"#\"^computed is imm1213 & imm0007 [ computed = (imm1213 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; }\n\nRel8: addr is simm0007 [ addr = inst_start + simm0007; ] { export *:$(SIZE) addr; }\nRel82: addr is simm0411 [ addr = inst_start + simm0411; ] { export *:$(SIZE) addr; }\nRel11: addr is simm0010 [ addr = inst_start + simm0010; ] { export *:$(SIZE) addr; }\n\nRS: [rs] is rs { export *[$(DATA_SPACE)]:$(SIZE) rs; }\nRT: [rt] is rt { export *[$(DATA_SPACE)]:$(SIZE) rt; }\n\nCC: \"eq\" is cc0002=0x0 { export Z; }\nCC: \"ne\" is cc0002=0x1 { tmp = !Z; export tmp; }\nCC: \"lt\" is cc0002=0x2 { tmp = N != V; export tmp; }\nCC: \"le\" is cc0002=0x3 { tmp = Z || (N != V); export tmp; }\nCC: \"lo\" is cc0002=0x4 { export C; }\nCC: \"mi\" is cc0002=0x5 { export N; }\nCC: \"vs\" is cc0002=0x6 { export V; }\nCC: \"\" is cc0002=0x7 { export 1:1; }\n\nCOND: CC is CC { if (!CC) goto inst_next; }\nCOND: CC is CC & cc0002=0x7 { } # unconditional\n\nmacro resultflags(result) {\n\tN = result s< 0;\n\tZ = result == 0;\n}\nmacro addflags(a, b) {\n\tC = carry(a, b);\n\tV = scarry(a, b);\n}\nmacro subflags(a, b) {\n\tC = a s< b;\n\tV = sborrow(a, b);\n}\nmacro logicflags() {\n\tC = 0;\n\tV = 0;\n}\n\ndefine pcodeop pcodeop_one;\ndefine pcodeop pcodeop_two;\ndefine pcodeop pcodeop_three;\n\n# operations\n\n:imm rd, Imm10 is $(INSTR_PHASE) op1515=0x0 & rd & Imm10 { logicflags(); rd = Imm10; resultflags(rd); }\n:simm rd, Simm10 is $(INSTR_PHASE) op1415=0x2 & rd & Simm10 { logicflags(); rd = Simm10; resultflags(rd); }\n\n:add rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x0 & rs & rt { addflags(rs, rt); rs = rs + rt; resultflags(rs); }\n:sub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x1 & rs & rt { subflags(rs, rt); rs = rs - rt; resultflags(rs); }\n:rsub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x2 & rs & rt { subflags(rt, rs); rs = rt - rs; resultflags(rs); }\n:mul rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x3 & rs & rt { rs = rs * rt; resultflags(rs); } # fix C & V\n:div rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x4 & rs & rt { rs = rs / rt; resultflags(rs); } # fix C & V\n:mod rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x5 & rs & rt { rs = rs % rt; resultflags(rs); } # fix C & V\n:cmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x6 & rs & rt { subflags(rs, rt); tmp:$(SIZE) = rs - rt; resultflags(tmp); }\n:ucmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x7 & rs & rt { logicflags(); N = rs < rt; Z = rs == rt; }\n\n:add rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x8 & rs & Simm4 { addflags(rs, Simm4); rs = rs + Simm4; resultflags(rs); }\n:sub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x9 & rs & Simm4 { subflags(rs, Simm4); rs = rs - Simm4; resultflags(rs); }\n:rsub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xa & rs & Simm4 { subflags(Simm4, rs); rs = Simm4 - rs; resultflags(rs); }\n:mul rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xb & rs & Simm4 { rs = rs * Simm4; resultflags(rs); } # fix C & V\n:div rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xc & rs & Simm4 { rs = rs / Simm4; resultflags(rs); } # fix C & V\n:mod rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xd & rs & Imm4 { rs = rs % Imm4; resultflags(rs); } # fix C & V\n:cmp rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xe & rs & Simm4 { subflags(rs, Simm4); tmp:$(SIZE) = rs - Simm4; resultflags(tmp); }\n:ucmp rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xf & rs & Imm4 { logicflags(); N = rs < Imm4; Z = rs == Imm4; }\n\n:and rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x0 & rs & rt { logicflags(); rs = rs & rt; resultflags(rs); }\n:or rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x1 & rs & rt { logicflags(); rs = rs | rt; resultflags(rs); }\n:xor rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x2 & rs & rt { logicflags(); rs = rs ^ rt; resultflags(rs); }\n:lsr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x3 & rs & rt { logicflags(); rs = rs >> rt; resultflags(rs); }\n:asr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x4 & rs & rt { logicflags(); rs = rs s>> rt; resultflags(rs); }\n:lsl rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x5 & rs & rt { logicflags(); rs = rs << rt; resultflags(rs); }\n\n# saa == shift and accumulate; very useful for building up a 32 bit or 64 bit value in pieces, like:\n# imm r12, #32b\n# imm r11, #7d7\n# saa r12, r11\n# imm r11, #2be\n# saa r12, r11\n#\n# now r12 contains '0xcafebabe' (decompiler reconstitutes the pieces seamlessly)\n\n:saa rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x8 & rs & rt { logicflags(); rs = (rs << 11) | rt; resultflags(rs); }\n\n:lsr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xb & rs & Imm4 { logicflags(); rs = rs >> Imm4; resultflags(rs); }\n:asr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xc & rs & Imm4 { logicflags(); rs = rs s>> Imm4; resultflags(rs); }\n:lsl rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xd & rs & Imm4 { logicflags(); rs = rs << Imm4; resultflags(rs); } # fix C & V\n:inv rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x0 { logicflags(); rs = ~rs; resultflags(rs); }\n:neg rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x1 { logicflags(); rs = -rs; resultflags(rs); }\n\n:load rs, RT is $(INSTR_PHASE) op1215=0xd & op0811=0x6 & rs & RT { rs = RT; logicflags(); resultflags(rs); }\n:store RS, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x7 & RS & rt { RS = rt; logicflags(); resultflags(rt); }\n:mov rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0xf & rs & rt { rs = rt; logicflags(); resultflags(rs); }\n\n:sk^CC is $(INSTR_PHASE) op1215=0x8 & op0811=0x0 & op0407=0x0 & op0303=0x0 & CC & Rel82 { if (CC) goto inst_next2; }\n\n:br^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x0 & COND & Rel82 { build COND; goto Rel82; }\n:brds^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x1 & COND & Rel82 { build COND; delayslot(1); goto Rel82; }\n:br^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x0 & COND & rs & op0303=0x0 { build COND; goto [rs]; }\n:brds^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x1 & COND & rs & op0303=0x0 { build COND; temp:$(SIZE) = rs; delayslot(1); goto [temp]; }\n@ifdef POS_STACK\n:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ram]:$(SIZE) sp = rs; sp = sp + $(SIZE); logicflags(); resultflags(rs); }\n:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp - $(SIZE); rs = *[ram]:$(SIZE) sp; logicflags(); resultflags(rs); }\n@else\n:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ram]:$(SIZE) sp = rs; sp = sp - $(SIZE); logicflags(); resultflags(rs); }\n:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp + $(SIZE); rs = *[ram]:$(SIZE) sp; logicflags(); resultflags(rs); }\n@endif\n:ret is $(INSTR_PHASE) op1215=0xf & op0811=0x4 & op0007=0x0 { return [lr]; }\n:callds Rel8 is $(INSTR_PHASE) op1215=0xf & op0811=0x5 & Rel8 { delayslot(1); lr = inst_next; call Rel8; }\n:call rs is $(INSTR_PHASE) op1215=0xf & op0811=0x6 & rs & op0003=0x0 { lr = inst_next; call [rs]; }\n:call Rel11 is $(INSTR_PHASE) op1215=0xf & op1111=0x1 & Rel11 { lr = inst_next; call Rel11; }\n\n# 1111 0110 ssss 1ccc # call rs if ccc call rs\n:call^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x6 & rs & op0303=0x1 & COND { build COND; lr = inst_next; call [rs]; }\n\n:user_one rs is $(INSTR_PHASE) op1215=0xa & op0811=0x01 & rs & op0003=0x0 { pcodeop_one(rs);}\n:user_two rs is $(INSTR_PHASE) op1215=0xa & op0811=0x02 & rs & op0003=0x0 { pcodeop_two(rs); pcodeop_three();}\n:user_three is $(INSTR_PHASE) op1215=0xa & op0811=0x03 & op0007=0x0 { pcodeop_three();}\n:user_four rs rt is $(INSTR_PHASE) op1215=0xa & op0811=0x04 & rs & rt { pcodeop_one(rs); call [rt]; pcodeop_three();} \n:user_five Rel8 is $(INSTR_PHASE) op1215=0xa & op0811=0x05 & Rel8 { lr = inst_next; call Rel8; pcodeop_three();} \n:user_six rs is $(INSTR_PHASE) op1215=0xa & op0811=0x06 & rs & op0003=0x0 { r1 = pcodeop_one(rs); call [r1];}\n\n:unimpl is $(INSTR_PHASE) op1215=0xa & op0811=0x08 & op0007=0 unimpl\n" }, { "path": "pypcode/processors/Toy/data/languages/toyPosStack.cspec", "content": "\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t\n\t\n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_be.slaspec", "content": "@define ENDIAN \"big\"\n@define SIZE \"4\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_be_posStack.slaspec", "content": "@define ENDIAN \"big\"\n@define SIZE \"4\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define POS_STACK \"true\" # enables switch in instructions for push/pop to work in positive direction\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_builder.sinc", "content": "\n\n@include \"toy.sinc\"\n\n# Define context bits\ndefine register offset=0x2000 size=8 contextreg;\n\ndefine context contextreg\n\t# stored context\n\tfctx\t= (0,3) # flowing context\n\tnfctx = (4,7) noflow # single address context\n\t# transient context (never stored, aids disassembly)\n\tphase = (8,9) # parse phase - used for complex scenarios\n\tcounter = (10,13) # parse count-down\n;\n\ndefine token instr8(8)\n\t op8 = (0, 7)\n;\n\ndefine token extra16(16)\n xsimm8 = (0, 7) signed\n;\n\ndefine token extra8(8)\n\t nnnn = (0, 3)\n;\n\n# ^instruction - manage parse phases (only required for complex languages)\n\n:^instruction\tis phase=0 & instruction [ phase=1; ] { build instruction; }\n\n@define INSTR_PHASE \"phase=1 &\" # parse instructions during phase 1\n\n@include \"toyInstructions.sinc\"\n\n# additional forms added to toy language, taken from all three reserved banks:\n# 1101 1001 xxxx xxxx # RESERVED BANK\n# 1101 1010 xxxx xxxx # RESERVED BANK\n# 1111 0111 xxxx xxxx # RESERVED BANK\n\n# fctx i 1101 1001 0000 iiii # set flow context (fctx) on next instr \n# nfctx i 1101 1001 0001 iiii # set noflow context (nfctx) on next instr\n# nfctx rel,i 1101 1001 0010 iiii; 0000 0000 iiii iiii # set noflow context on rel instr\n\n# cop# s 1101 1010 ssss 0000 # coprocessor # determined by nfctx val (1-3) \n\n# nop #1 1111 0111\n# nop # 1101 1001 0011 nnnn; ... # nop where nnnn indicates number of additional bytes consumed \n\n\n# operations\n\n:fctx Imm4 is phase=1 & op1215=0xd & op0811=0x9 & rs=0x0 & imm0003 & Imm4 [ fctx=imm0003; globalset(inst_next,fctx); ] { }\n\nnfctxSetAddr: addr is Imm4 & imm0003; xsimm8 [ addr = inst_start + xsimm8; nfctx=imm0003; globalset(addr, nfctx); ] { export *:$(SIZE) addr; }\n\n:nfctx nfctxSetAddr,Imm4 is (phase=1 & op1215=0xd & op0811=0x9 & rs=0x2 & Imm4) ... & nfctxSetAddr { }\n:nfctx Imm4 is phase=1 & op1215=0xd & op0811=0x9 & rs=0x1 & imm0003 & Imm4 [ nfctx=imm0003; globalset(inst_next,nfctx); ] { }\n\ndefine pcodeop cop1;\ndefine pcodeop cop2;\ndefine pcodeop cop3;\n\n:cop1 rs is phase=1 & op1215=0xd & op0811=0xa & op0003=0 & nfctx=1 & rs { cop1(rs); }\n:cop2 rs is phase=1 & op1215=0xd & op0811=0xa & op0003=0 & nfctx=2 & rs { cop2(rs); }\n:cop3 rs is phase=1 & op1215=0xd & op0811=0xa & op0003=0 & nfctx=3 & rs { cop3(rs); }\n\nNopCnt: \"#\"^cnt is imm0003 [ cnt = imm0003 + 2; ] { export *[const]:1 cnt; }\n\nNopByte: is counter=0 { }\nNopByte: is epsilon; nnnn; NopByte [ counter=counter-1; ] { }\n\nOne: \"#\"^cnt is epsilon [ cnt = 1; ] { export *[const]:1 cnt; }\n\n:nop One is phase=1 & op8=0xf7 & One { }\n:nop NopCnt is phase=1 & op1215=0xd & op0811=0x9 & rs=0x3 & imm0003 & NopCnt; NopByte ... [ counter=imm0003; ] { }\n\n\n\n\n\n\n\n\n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_builder_be.slaspec", "content": "@define ENDIAN \"big\"\n@define SIZE \"4\"\n@define DATA_SPACE \"ram\"\n\n@include \"toy_builder.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_builder_be_align2.slaspec", "content": "@define ENDIAN \"big\"\n@define ALIGN \"2\"\n@define SIZE \"4\"\n@define DATA_SPACE \"ram\"\n\n@include \"toy_builder.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_builder_le.slaspec", "content": "@define ENDIAN \"little\"\n@define SIZE \"4\"\n@define DATA_SPACE \"ram\"\n\n@include \"toy_builder.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_builder_le_align2.slaspec", "content": "@define ENDIAN \"little\"\n@define ALIGN \"2\"\n@define SIZE \"4\"\n@define DATA_SPACE \"ram\"\n\n@include \"toy_builder.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_harvard.pspec", "content": "\n\n\n \n \n\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_le.slaspec", "content": "@define ENDIAN \"little\"\n@define SIZE \"4\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_wsz_be.slaspec", "content": "@define ENDIAN \"big\"\n@define ALIGN \"2\"\n@define SIZE \"4\"\n@define WORDSIZE \"2\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/Toy/data/languages/toy_wsz_le.slaspec", "content": "@define ENDIAN \"little\"\n@define ALIGN \"2\"\n@define SIZE \"4\"\n@define WORDSIZE \"2\"\n\n@define INSTR_PHASE \"\" # not used by basic toy language\n@define DATA_SPACE \"ram\"\n\n@include \"toy.sinc\"\n@include \"toyInstructions.sinc\"\n" }, { "path": "pypcode/processors/V850/data/languages/Helpers/Conditions.sinc", "content": "#####################################################\n#####\t\t Conditions\t\t\t#####\n#####################################################\n\n\nc0003: \"v\"\tis op0003=0x0\t{ tmp:1 = ($(OV)) == 1; \t\texport tmp; }\nc0003: \"nv\"\tis op0003=0x8\t{ tmp:1 = ($(OV)) == 0; \t\texport tmp; }\nc0003: \"c\"\tis op0003=0x1\t{ tmp:1 = ($(CY)) == 1; \t\texport tmp; }\nc0003: \"nc\"\tis op0003=0x9\t{ tmp:1 = ($(CY)) == 0; \t\texport tmp; }\nc0003: \"e\"\tis op0003=0x2\t{ tmp:1 = ($(Z)) == 1; \t\t\texport tmp; }\nc0003: \"ne\"\tis op0003=0xA\t{ tmp:1 = ($(Z)) == 0; \t\t\texport tmp; }\nc0003: \"nh\"\tis op0003=0x3\t{ tmp:1 = ($(CY) || $(Z)) == 1; \texport tmp; }\nc0003: \"h\"\tis op0003=0xB\t{ tmp:1 = ($(CY) || $(Z)) == 0; \texport tmp; }\nc0003: \"n\"\tis op0003=0x4\t{ tmp:1 = ($(S)) == 1; \t\t\texport tmp; }\nc0003: \"p\"\tis op0003=0xC\t{ tmp:1 = ($(S)) == 0; \t\t\texport tmp; }\nc0003: \"t\"\tis op0003=0x5\t{ tmp:1 = 1; \t\t\t\texport tmp; }\nc0003: \"sa\"\tis op0003=0xD\t{ tmp:1 = ($(SAT)) == 1; \t\texport tmp; }\nc0003: \"lt\"\tis op0003=0x6\t{ tmp:1 = ($(S) ^^ $(OV)) == 1; \texport tmp; }\nc0003: \"ge\"\tis op0003=0xE\t{ tmp:1 = ($(S) ^^ $(OV)) == 0; \texport tmp; }\nc0003: \"le\"\tis op0003=0x7\t{ tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }\nc0003: \"gt\"\tis op0003=0xF\t{ tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }\n\nc1720: \"v\"\tis op1720=0x0\t{ tmp:1 = ($(OV)) == 1; \t\texport tmp; }\nc1720: \"nv\"\tis op1720=0x8\t{ tmp:1 = ($(OV)) == 0; \t\texport tmp; }\nc1720: \"c\"\tis op1720=0x1\t{ tmp:1 = ($(CY)) == 1; \t\texport tmp; }\nc1720: \"nc\"\tis op1720=0x9\t{ tmp:1 = ($(CY)) == 0; \t\texport tmp; }\nc1720: \"e\"\tis op1720=0x2\t{ tmp:1 = ($(Z)) == 1; \t\t\texport tmp; }\nc1720: \"ne\"\tis op1720=0xA\t{ tmp:1 = ($(Z)) == 0; \t\t\texport tmp; }\nc1720: \"nh\"\tis op1720=0x3\t{ tmp:1 = ($(CY) || $(Z)) == 1; \texport tmp; }\nc1720: \"h\"\tis op1720=0xB\t{ tmp:1 = ($(CY) || $(Z)) == 0; \texport tmp; }\nc1720: \"n\"\tis op1720=0x4\t{ tmp:1 = ($(S)) == 1; \t\t\texport tmp; }\nc1720: \"p\"\tis op1720=0xC\t{ tmp:1 = ($(S)) == 0; \t\t\texport tmp; }\nc1720: \"t\"\tis op1720=0x5\t{ tmp:1 = 1; \t\t\t\texport tmp; }\nc1720: \"sa\"\tis op1720=0xD\t{ tmp:1 = ($(SAT)) == 1; \t\texport tmp; }\nc1720: \"lt\"\tis op1720=0x6\t{ tmp:1 = ($(S) ^^ $(OV)) == 1; \texport tmp; }\nc1720: \"ge\"\tis op1720=0xE\t{ tmp:1 = ($(S) ^^ $(OV)) == 0; \texport tmp; }\nc1720: \"le\"\tis op1720=0x7\t{ tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }\nc1720: \"gt\"\tis op1720=0xF\t{ tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }\n" }, { "path": "pypcode/processors/V850/data/languages/Helpers/Extras.sinc", "content": "#####################################################\n#####\t\t \tExtras\t\t\t#####\n#####################################################\n\n\n# read r0 always return zero\nR0004: _R0004 is _R0004 & _R0004=0\t{ local x:4=0; \texport x;\t}\nR0004: _R0004 is _R0004\t\t\t{\t\texport _R0004;\t}\n\nR1115: _R1115 is _R1115 & _R1115=0\t{ local\tx:4=0; \texport x;\t}\nR1115: _R1115 is _R1115\t\t\t{ \t\texport _R1115;\t}\n\nR2731: _R2731 is _R2731 & _R2731=0\t{ local x:4=0; \texport x;\t}\nR2731: _R2731 is _R2731\t\t\t{\t\texport _R2731;\t}\n\n\nadr9: res is op0406 & s1115\n[ res = ((s1115 << 4) | (op0406 << 1)) + inst_start; ] \n{ \n\texport *:4 res; \n}\n\nadr22: res is s0005; op1631 & op1616=0\n[ res = ((s0005 << 16) | op1631) + inst_start; ] \n{ \n\texport *:4 res;\n}\n\nadr32: res is op1631 & op1616=0; op3247\n[ res = ((op3247 << 16) | op1631) + inst_start; ]\n{\n\texport *:4 res;\n}\n\nadr32i: res is op1631 & op1616=0; op3247\n[ res = ((op3247 << 16) | op1631); ]\n{\n\texport *[const]:4 res;\n}\n\nreg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; }\nreg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; }\n\n\n\n##### Prep/Disp Loop #####\n\nPrepList20: r20\t\t\tis prep27=1 & r20\t\t\t\t\t{ push(r20); }\nPrepList20:\t\t\tis prep27=0\t\t\t\t\t\t{ }\n\nPrepList21: r21\t\t\tis prep26=1 & prep27=0 & r21\t\t\t\t{ push(r21); }\nPrepList21: PrepList20,r21\tis prep26=1 & PrepList20 & r21\t\t\t\t{ push(r21); }\nPrepList21: PrepList20\t\tis prep26=0 & PrepList20\t\t \t\t{ }\n\nPrepList22: r22\t\t\tis prep25=1 & prep2627=0 & r22\t\t\t\t{ push(r22); }\nPrepList22: PrepList21,r22\tis prep25=1 & PrepList21 & r22\t\t\t\t{ push(r22); }\nPrepList22: PrepList21\t\tis prep25=0 & PrepList21\t\t \t\t{ }\n\nPrepList23: r23\t\t\tis prep24=1 & prep2527=0 & r23\t\t\t\t{ push(r23); }\nPrepList23: PrepList22,r23\tis prep24=1 & PrepList22 & r23\t\t\t\t{ push(r23); }\nPrepList23: PrepList22\t\tis prep24=0 & PrepList22\t\t \t\t{ }\n\nPrepList24: r24\t\t\tis prep31=1 & prep2427=0 & r24\t\t\t\t{ push(r24); }\nPrepList24: PrepList23,r24\tis prep31=1 & PrepList23 & r24\t\t\t\t{ push(r24); }\nPrepList24: PrepList23\t\tis prep31=0 & PrepList23\t\t \t\t{ }\n\nPrepList25: r25\t\t\tis prep30=1 & prep2427=0 & prep31=0 & r25\t\t{ push(r25); }\nPrepList25: PrepList24,r25\tis prep30=1 & PrepList24 & r25\t\t\t\t{ push(r25); }\nPrepList25: PrepList24\t\tis prep30=0 & PrepList24\t\t\t\t{ }\n\nPrepList26: r26\t\t\tis prep29=1 & prep2427=0 & prep3031=0 & r26\t\t{ push(r26); }\nPrepList26: PrepList25,r26\tis prep29=1 & PrepList25 & r26\t\t\t\t{ push(r26); }\nPrepList26: PrepList25\t\tis prep29=0 & PrepList25\t\t\t\t{ }\n\nPrepList27: r27\t\t\tis prep28=1 & prep2427=0 & prep2931=0 & r27\t\t{ push(r27); }\nPrepList27: PrepList26,r27\tis prep28=1 & PrepList26 & r27\t\t\t\t{ push(r27); }\nPrepList27: PrepList26\t\tis prep28=0 & PrepList26\t\t\t\t{ }\n\nPrepList28: r28\t\t\tis prep23=1 & prep2431=0 & r28\t\t\t\t{ push(r28); }\nPrepList28: PrepList27,r28\tis prep23=1 & PrepList27 & r28\t\t\t\t{ push(r28); }\nPrepList28: PrepList27\t\tis prep23=0 & PrepList27\t\t\t\t{ }\n\nPrepList29: r29\t\t\tis prep22=1 & prep2431=0 & prep23=0 & r29\t\t{ push(r29); }\nPrepList29: PrepList28,r29\tis prep22=1 & PrepList28 & r29\t\t\t\t{ push(r29); }\nPrepList29: PrepList28\t\tis prep22=0 & PrepList28\t\t\t\t{ }\n\nPrepList30: ep\t\t\tis prep00=1 & prep2431=0 & prep2223=0 & ep\t\t{ push(ep); }\nPrepList30: PrepList29,ep\tis prep00=1 & PrepList29 & ep\t\t\t\t{ push(ep); }\nPrepList30: PrepList29\t\tis prep00=0 & PrepList29\t\t \t\t{ }\n\nPrepList: { lp }\t\tis prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp\t{ push(lp); }\nPrepList: { PrepList30,lp }\tis prep21=1 & PrepList30 & lp\t\t\t\t{ push(lp); }\nPrepList: { PrepList30 }\tis prep21=0 & PrepList30\t\t\t\t{ }\n\n\n\nDispList31: lp\t\t\tis prep21=1 & lp\t\t\t\t\t{ pop(lp); }\nDispList31:\t\t\tis prep21=0\t\t\t\t\t\t{ }\n\nDispList30: ep,DispList31\tis DispList31 & prep00=1 & ep\t\t\t\t{ pop(ep); }\nDispList30: DispList31\t\tis DispList31 & prep00=0\t\t\t\t{ }\n\nDispList29: r29,DispList30\tis DispList30 & prep22=1 & r29\t\t\t\t{ pop(r29); }\nDispList29: DispList30\t\tis DispList30 & prep22=0\t\t\t\t{ }\n\nDispList28: r28,DispList29\tis DispList29 & prep23=1 & r28\t\t\t\t{ pop(r28); }\nDispList28: DispList29\t\tis DispList29 & prep23=0\t\t\t\t{ }\n\nDispList27: r27,DispList28\tis DispList28 & prep28=1 & r27\t\t\t\t{ pop(r27); }\nDispList27: DispList28\t\tis DispList28 & prep28=0\t\t\t\t{ }\n\nDispList26: r26,DispList27\tis DispList27 & prep29=1 & r26\t\t\t\t{ pop(r26); }\nDispList26: DispList27\t\tis DispList27 & prep29=0\t\t\t\t{ }\n\nDispList25: r25,DispList26\tis DispList26 & prep30=1 & r25\t\t\t\t{ pop(r25); }\nDispList25: DispList26\t\tis DispList26 & prep30=0\t\t\t\t{ }\n\nDispList24: r24,DispList25\tis DispList25 & prep31=1 & r24\t\t\t\t{ pop(r24); }\nDispList24: DispList25\t\tis DispList25 & prep31=0\t\t\t\t{ }\n\nDispList23: r23,DispList24\tis DispList24 & prep24=1 & r23\t\t\t\t{ pop(r23); }\nDispList23: DispList24\t\tis DispList24 & prep24=0\t\t\t\t{ }\n\nDispList22: r22,DispList23\tis DispList23 & prep25=1 & r22\t\t\t\t{ pop(r22); }\nDispList22: DispList23\t\tis DispList23 & prep25=0\t\t\t\t{ }\n\nDispList21: r21,DispList22\tis DispList22 & prep26=1 & r21\t\t\t\t{ pop(r21); }\nDispList21: DispList22\t\tis DispList22 & prep26=0\t\t\t\t{ }\n\nDispList: { r20,DispList21 }\tis DispList21 & prep27=1 & r20\t\t\t\t{ pop(r20); }\nDispList: { DispList21 }\tis DispList21 & prep27=0\t\t\t\t{ }\n" }, { "path": "pypcode/processors/V850/data/languages/Helpers/Macros.sinc", "content": "#####################################################\n#####\t\t \tMacros\t\t\t#####\n#####################################################\n\n\n##### CARRY-Flag #####\n\nmacro set_CY_pos(var1, var2)\n{\n\t$(CY) = carry(var1, var2);\n}\n\nmacro set_CY_pos2(var1, var2, var3)\n{\n\tlocal var12 = var1 + var2;\n\t$(CY) = carry(var1, var2) || carry(var12, var3);\n}\n\nmacro set_CY_neg(var1, var2)\n{\n\t$(CY) = var1 < var2;\n}\n\nmacro set_CY_neg2(var1, var2, var3)\n{\n\tlocal var23 = var2 + var3;\n\t$(CY) = (var1 < var23);\n}\n\n\n\n##### Overflow-Flag #####\n\nmacro set_OV_pos(var1, var2)\n{\n\t$(OV) = scarry(var1, var2);\n}\n\nmacro set_OV_pos2(var1, var2, var3)\n{\n\tlocal var12 = var1 + var2;\n\t$(OV) = scarry(var1, var2) || scarry(var12, var3);\n}\n\nmacro set_OV_neg(var1, var2)\n{\t\n\tlocal A:4 = var1;\n\tlocal B:4 = var2;\n\tlocal R = A - B;\n\n\tlocal A1 = A[31,1];\n\tlocal B1 = B[31,1];\n\tlocal R1 = R[31,1];\n\n\t$(OV) = (A1 != B1) && (B1 == R1);\n\n\t#OV = 1 if:\n\t#pos - neg = neg\n\t#neg - pos = pos\n}\n\nmacro set_OV_neg2(var1, var2, var3)\n{\n\tlocal A:4 = var1;\n\tlocal B:4 = var2;\n\tlocal C:4 = var3;\n\tlocal R = A - B - C;\n\n\tlocal A1 = A[31,1];\n\tlocal B1 = B[31,1];\n\tlocal R1 = R[31,1];\n\n\t$(OV) = (A1 != B1) && (B1 == R1);\n}\n\n\n\n##### S/Z-Flags #####\n\nmacro set_S(flag)\n{\n\t$(S) = flag s< 0;\n}\n\nmacro set_Z(var)\n{\n\t$(Z) = var == 0;\n}\n\n\n\n##### General-Flag-Macros #####\n\nmacro set_general_flags_pos(var1, var2)\n{\n\tlocal res = var1 + var2;\n\tset_CY_pos(var1, var2);\n\tset_OV_pos(var1, var2);\n\tset_S(res);\n\tset_Z(res);\n}\n\nmacro set_general_flags_neg(var1, var2)\n{\n\tlocal res = var1 - var2;\n\tset_CY_neg(var1, var2);\n\tset_OV_neg(var1, var2);\n\tset_S(res);\n\tset_Z(res);\n}\n\nmacro set_OV0_S_Z(var)\n{\n\t$(OV) = 0;\n\tset_S(var);\n\tset_Z(var);\n}\n\n\n\n##### General-Macros #####\n\n# if condition is != 0\nmacro either_or(res, cond, true, false)\t\n{\n\tres = (true * zext(cond != 0)) + (false * zext(cond == 0));\n}\n\n# if condition is == 1\nmacro either_or1(res, cond, true, false)\n{\n\tres = (true * zext(cond == 1)) + (false * zext(cond != 1));\n}\n\nmacro shift_right_logic(res, var, shift_)\n{\n\tlocal shift = shift_ & 0x1f;\n\tlocal mask = (zext(shift != 0) * var) & (1 << (shift - 1));\n\tres = var >> shift;\n\tset_OV0_S_Z(res);\n\t$(CY) = ((mask != 0) && (shift != 0));\n}\n\nmacro shift_right_arith(res, var, shift_)\n{\n\tlocal shift = shift_ & 0x1f;\n\tlocal mask = (zext(shift != 0) * var) & (1 << (shift - 1));\n\tres = var s>> shift;\n\tset_OV0_S_Z(res);\n\t$(CY) = ((mask != 0) && (shift != 0));\n}\n\nmacro shift_left_logic(res, var, shift_) \n{\n\tlocal shift = shift_ & 0x1f;\n\tlocal mask = (zext(shift != 0) * var) & (1 << (32 - shift));\n\tres = var << shift;\n\tset_OV0_S_Z(res);\n\t$(CY) = ((mask != 0) && (shift != 0));\n}\n\n\n\n##### Prep/Disp Macros #####\n\nmacro push(reg)\n{\n\tsp = sp - 4;\n\t*:4 sp = reg;\n}\n\nmacro pop(reg)\n{\n\treg = *:4 sp;\n\tsp = sp + 4;\n}\n\n\n\n##### Search Macros #####\n\nmacro SearchRight(res, var, char)\n{\n\tlocal var_:4 = var;\n\tres = 0;\n\n\t\n\tif ((var_ & 0x1) == char)\n\t\tgoto ;\n\n\tvar_ = var_ >> 1;\n\tres = res + 1;\n\n\tif (res < 32)\n\t\tgoto ;\n\t\n\tres = 0;\n\n\t\n}\n\nmacro SearchLeft(res, var, char)\n{\n\tlocal var_:4 = var;\n\tres = 0;\n\n\t\n\tif ((var_ >> 31) == char) \n\t\tgoto ;\n\n\tvar_ = var_ << 1;\n\tres = res + 1;\n\n\tif (res < 32) \n\t\tgoto ;\n\n\tres = 0;\n\n\t\n}\n\n# macro saturate(var) \n# {\n# \tif (var s> 0x7FFFFFFF) \n# \tgoto ;\n \n# \tif (var s< -0x80000000) \n# \tgoto ;\n\n# \tgoto ;\n\n# \t \n# var = 0x7FFFFFFF; \n# goto ;\n\n# \t \n# var = -0x80000000; \n# goto ;\n\t\n# \n# }\n\n\n##### Float-Macros #####\n\nmacro compare_float(res, fcond, reg1, reg2)\n{\n\tlocal un = ((fcond & 1) == 1)\t& (nan(reg2) || nan(reg1));\n\tlocal eq = ((fcond & 2) == 2) & (!(nan(reg2) || nan(reg1))) & (reg2 f== reg1);\n\tlocal le = ((fcond & 4) == 4)\t& (!(nan(reg2) || nan(reg1))) & (reg2 f< reg1);\n\t#local ex = (fcond & 8)\t\t& ((nan(reg2) || nan(reg1)));\n\t\n\tres = zext(un|eq|le);\n}\n" }, { "path": "pypcode/processors/V850/data/languages/Helpers/Register.sinc", "content": "#####################################################\n#####\t \t\tRegister\t\t#####\n#####################################################\n\n\n##### General-purpose registers (r0 to r31) #####\n\ndefine register offset=0x0 size=0x4 # offset = 0 because it's the start\n[\n r0 r1 r2 sp gp tp r6 r7 r8 r9 \n r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 \n r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 \n ep lp\n];\n\n\n\n##### Control/Special registers #####\n\ndefine register offset=0x80 size=0x4 # offset = 0x80(128) = PreOffset+PreRegister*Size = 0+32*4 = 128\n[\n EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC \n FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW \n CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR \n DBWR BSEL\n];\n\ndefine register offset=0x0 size=0x8 \n[ \n r0r1 r2sp r4r5 r6r7 r8r9 \n r10r11 r12r13 r14r15 r16r17 r18r19\n r20r21 r22r23 r24r25 r26r27 r28r29 \n eplp\n];\n\ndefine register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256\n" }, { "path": "pypcode/processors/V850/data/languages/Helpers/Tokens.sinc", "content": "#####################################################\n#####\t \t\tTokens\t\t\t#####\n#####################################################\n\n\ndefine token instr(16)\n\top0000 \t = (0,0)\n\top0003 \t = (0,3)\n\top0004 \t = (0,4)\n\t_R0004 \t = (0,4)\n\tSR0004 \t = (0,4)\n\tR0004x2 = (0,4)\n\ts0004 \t = (0,4) \tsigned\n\ts0005 \t = (0,5) \tsigned\n\top0005 \t = (0,5)\n\top0006 \t = (0,6)\n\top0010 \t = (0,10)\n\top0015 \t = (0,15)\n\top0106 \t = (1,6)\n\top0406 \t = (4,6)\n\top0410 \t = (4,10)\n\top0505\t = (5,5)\n\top0510\t = (5,10)\n\top0515 \t = (5,15)\n\top0610 \t = (6,10)\n\top0615 \t = (6,15)\n\top0710 \t = (7,10)\n\top1113 \t = (11,13)\n\top1114 \t = (11,14)\n\top1115 \t = (11,15)\n\t_R1115 \t = (11,15)\n\tSR1115 \t = (11,15)\n\tR1115x2 = (11,15)\n\ts1115 \t = (11,15)\tsigned\n\top1415 \t = (14,15)\n\top1515 \t = (15,15)\n;\n\ndefine token instr2(16)\n\top1616 \t = (0,0)\n\top1617 \t = (0,1)\n\top1619 \t = (0,3)\n\top1620 \t = (0,4)\n\tR1620 \t = (0,4)\n\tR1620x2 = (0,4)\n\top1626\t = (0,10)\n\top1631 \t = (0,15)\n\ts1631 \t = (0,15)\tsigned\n\tfcbit1719 = (1,3)\n\top1720 \t = (1,4)\n\top0_1720 = (1,4)\n\top1_1720 = (1,4)\n\ts1731 \t = (1,15) \tsigned\n\top1821 \t = (2,5)\n\ts1821 \t = (2,5) \tsigned\n\top2020 \t = (4,4)\n\top2026 \t = (4,10)\n\top2122 \t = (5,6)\n\top2126 \t = (5,10)\n\top2226 \t = (6,10)\n\top2323 \t = (7,7)\n\top2426 \t = (8,10)\n\top2729 \t = (11,13)\n\tfcond2730 = (11,14)\n\top2731 \t = (11,15)\n\t_R2731 \t = (11,15)\n\tR2731x2 = (11,15)\n\top3031 \t = (14,15)\n\top3131 \t = (15,15)\n;\n\ndefine token instr3(16)\n\top3247 \t = (0,15)\n\ts3247 \t = (0,15)\tsigned\n;\n\ndefine token instr4(16)\n\top4863 \t = (0,15)\n;\n\n# used in PREPARE/DISPOSE instructions\ndefine token prep(32)\n\tprep00 \t = (0,0)\n\tprep0105 = (1,5)\n\tprep0615 = (6,15)\n\tprep1620 = (16,20)\n\tprep21 \t = (21,21)\n\tprep22 \t = (22,22)\n\tprep2223 = (22,31)\n\tprep23 \t = (23,23)\n\tprep24 \t = (24,24)\n\tprep2431 = (24,31)\n\tprep25 \t = (25,25)\n\tprep26 \t = (26,26)\n\tprep27 \t = (27,27)\n\tprep28 \t = (28,28)\n\tprep29 \t = (29,29)\n\tprep2931 = (29,31)\n\tprep3031 = (30,31)\n\tprep2427 = (24,27)\n\tprep2527 = (25,27)\n\tprep2627 = (26,27)\n\tprep30 \t = (30,30)\n\tprep31 \t = (31,31)\n;\n" }, { "path": "pypcode/processors/V850/data/languages/Helpers/Variables.sinc", "content": "#####################################################\n#####\t \t\tVariables\t\t#####\n#####################################################\n\n\nattach variables [ _R0004 _R1115 _R2731 R1620 prep1620]\n[ \n r0 r1 r2 sp gp tp r6 r7 r8 r9 \n r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 \n r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 \n ep lp \n];\n\nattach variables [ R0004x2 R1115x2 R1620x2 R2731x2 ]\n[ \n r0r1 \t _ r2sp _ r4r5 _ r6r7 _ r8r9 _ \n r10r11 _ r12r13 _ r14r15 _ r16r17 _ r18r19 _ \n r20r21 _ r22r23 _ r24r25 _ r26r27 _ r28r29 _ \n eplp \t _ \n];\n\nattach variables [ SR0004 SR1115 ]\n[\n EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC \n FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW \n CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR \n DBWR BSEL\n];\n\n\nattach variables [op0_1720] [r0 r2 gp r6 r8 r10 r12 r14 r16 r18 r20 r22 r24 r26 r28 ep];\nattach variables [op1_1720] [r1 sp tp r7 r9 r11 r13 r15 r17 r19 r21 r23 r25 r27 r29 lp];\n\n\nattach names [fcond2730]\n[\"f\" \"un\" \"eq\" \"ueq\" \"olt\" \"ult\" \"ole\" \"ule\" \"sd\" \"ngle\" \"seq\" \"ngl\" \"lt\" \"nge\" \"le\" \"ngt\"];\n\n\n@define NP \t\"PSW[7,1]\"\n@define EP \t\"PSW[6,1]\"\n@define ID \t\"PSW[5,1]\"\n@define SAT \t\"PSW[4,1]\"\n@define CY \t\"PSW[3,1]\"\n@define OV \t\"PSW[2,1]\"\n@define S \t\"PSW[1,1]\"\n@define Z \t\"PSW[0,1]\"\n\n@define EICC \t\"ECR[0,16]\"\n@define FECC \t\"ECR[16,16]\"\n" }, { "path": "pypcode/processors/V850/data/languages/Instructions/Arithmetic.sinc", "content": "# (3) Multiply instructions\n# (4) Multiply-accumulate instructions\n# (5) Arithmetic instructions\n# (7) Saturated operation instructions\n# (11) Divide instructions\n# (12) High-speed divide instructions\n\n\n\n#####################################################\n#####\t\t Multiply\t\t\t#####\n#####################################################\n\n\n# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000\n:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731\n{\n\tlocal res:8 = sext(R1115) * sext(R0004);\n\tR1115 = res:4;\n\tR2731 = res[32,32];\n}\n\n# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00\n:mul imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731 \n[ imm9 = (s1821 << 5) | op0004; ] \n{\n\tlocal res:8 = sext(R1115) * imm9;\n\tR1115 = res:4;\n\tR2731 = res[32,32];\n}\n\n# MULH reg1, reg2 - rrrrr000111RRRRR\n:mulh R0004, R1115 is op0510=0x07 & R0004 & R1115 & op1115!=0\n{\n\tR1115 = sext(R1115:2) * sext(R0004:2);\n}\n\n# MULH imm5, reg2 - rrrrr010111iiiii\n:mulh s0004, R1115 is op0510=0x17 & s0004 & R1115\n{\n\tR1115 = sext(R1115:2) * s0004;\n}\n\n# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii\n:mulhi s1631, R0004, R1115 is op0510=0x37 & R1115 & R0004; s1631\n{\n\tR1115 = R0004 * s1631;\n}\n\n# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010\n:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731\n{\n\tlocal res:8 = zext(R1115) * zext(R0004);\n\tR1115 = res:4;\n\tR2731 = res[32,32];\n}\n\n# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10\n:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731 \n[ imm9 = (op1821 << 5) | op0004; ]\n{\n\tlocal res:8 = zext(R1115) * imm9;\n\tR1115 = res:4;\n\tR2731 = res[32,32];\n}\n\n\n\n#####################################################\n#####\t\t MultiplyAccumulate\t\t#####\n#####################################################\n\n\n# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0\n:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2 \n{\n\tR1620x2 = sext(R1115) * sext(R0004) + R2731x2;\n}\n\n# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0\n:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2\n{\n\tR1620x2 = zext(R1115) * zext(R0004) + R2731x2;\n}\n\n\n\n#####################################################\n##### \t\t Arithmetic\t\t\t#####\n#####################################################\n\n\n# ADD reg1, reg2 - rrrrr001110RRRRR\n:add R0004, R1115 is op0510=0x0E & R0004 & R1115 \n{\n\tset_general_flags_pos(R0004, R1115);\n\tR1115 = R1115 + R0004;\n}\n\n# ADD imm5, reg2 - rrrrr010010iiiii\n:add s0004, R1115 is op0510=0x12 & s0004 & R1115 \n{\n\tset_general_flags_pos(s0004, R1115);\n\tR1115 = R1115 + s0004;\n}\n\n# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii\n:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631\n{\n\tset_general_flags_pos(R0004, s1631);\n\tR1115 = R0004 + s1631;\n}\n\n# CMP reg1, reg2 - rrrrr001111RRRRR\n:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115\n{\n\tset_general_flags_neg(R1115, R0004);\n}\n\n# CMP imm5, reg2 - rrrrr010011iiiii\n:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115\n{\n\tset_general_flags_neg(R1115, s0004);\n}\n\n# MOV reg1, reg2 - rrrrr000000RRRRR\n:mov R0004, R1115 is op0510=0x00 & R0004 & R1115\n{\n\tR1115 = R0004;\n}\n\n# MOV imm5, reg2 - rrrrr010000iiiii\n:mov s0004, R1115 is op0510=0x10 & s0004 & R1115 & op1115!=0\n{\n\tR1115 = s0004;\n}\n\n# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII\n:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247\n[ imm32 = (op3247 << 16) | op1631; ] \n{\n\tR0004 = imm32;\n}\n\n# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii\n:movea s1631, R0004, R1115 is op0510=0x31 & op1115!=0 & R0004 & R1115; s1631\n{\n\tR1115 = R0004 + s1631;\n}\n\n# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii\n:movhi s1631, R0004, R1115 is op0510=0x32 & op1115!=0 & R0004 & R1115; s1631\n{\n\tR1115 = R0004 + (s1631 << 16);\n}\n\n# SUB reg1, reg2 - rrrrr001101RRRRR\n:sub R0004, R1115 is op0510=0x0D & R0004 & R1115 \n{\n\tset_general_flags_neg(R1115, R0004);\n\tR1115 = R1115 - R0004;\n}\n\n# SUBR reg1, reg2 - rrrrr001100RRRRR\n:subr R0004, R1115 is op0510=0x0C & R0004 & R1115\n{\n\tset_general_flags_neg(R0004, R1115);\n\tR1115 = R0004 - R1115;\n}\n\n\n\n#####################################################\n#####\t\t Saturated\t\t#####\n#####################################################\n\n\ndefine pcodeop __saturate;\n\n# SATADD reg1, reg2 - rrrrr000110RRRRR\n:satadd R0004, R1115 is op0510=0x06 & R0004 & R1115 & op1115!=0\n{\n\tset_general_flags_pos(R1115, R0004);\n\t$(SAT) = $(SAT) || $(OV);\n\tR1115 = R1115 + R0004;\n\t__saturate(R1115);\n}\n\n#SATADD imm5, reg2 - rrrrr010001iiiii\n:satadd s0004, R1115 is op0510=0x11 & s0004 & R1115 & op1115!=0\n{\n\tset_general_flags_pos(R1115, s0004);\n\t$(SAT) = $(SAT) || $(OV);\n\tR1115 = R1115 + s0004;\n\t__saturate(R1115);\n}\n\n# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010\n:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731\n{\n\tset_general_flags_pos(R1115, R0004);\n\t$(SAT) = $(SAT) || $(OV);\n\tR2731 = R1115 + R0004;\n\t__saturate(R2731);\n}\n\n# SATSUB reg1, reg2 - rrrrr000101RRRRR\n:satsub R0004, R1115 is op0510=0x05 & R0004 & R1115 & op1115!=0 \n{\n\tset_general_flags_neg(R1115, R0004);\n\t$(SAT) = $(SAT) || $(OV);\n\tR1115 = R1115 - R0004;\n\t__saturate(R1115);\n}\n\n# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010\n:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731\n{\n\tset_general_flags_neg(R1115, R0004);\n\t$(SAT) = $(SAT) || $(OV);\n\tR2731 = R1115 - R0004;\n\t__saturate(R2731);\n}\n\n# SATSUBI imm16, reg1, reg2\n:satsubi s1631, R0004, R1115 is op0510=0x33 & op1115!=0 & R0004 & R1115; s1631\n{\n\tset_general_flags_neg(R0004, s1631);\n\t$(SAT) = $(SAT) || $(OV);\n\tR1115 = R0004 - s1631;\n\t__saturate(R1115);\n}\n\n# SATSUBR reg1, reg2\n:satsubr R0004, R1115 is op0510=0x04 & R0004 & R1115 & op1115!=0\n{\n\tset_general_flags_neg(R0004, R1115);\n\t$(SAT) = $(SAT) || $(OV);\n\tR1115 = R0004 - R1115;\n\t__saturate(R1115);\n}\n\n\n\n#####################################################\n##### Divide\t\t\t#####\n#####################################################\n\n\n# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000\n:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731\n{\n\tlocal quot:4 = R1115 s/ R0004;\n\tlocal mod:4 = R1115 s% R0004;\n\t$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);\n\tset_Z(R1115);\n\tset_S(R1115);\n\tR1115 = quot;\n \tR2731 = mod;\n}\n\n# DIVH reg1, reg2 - rrrrr000010RRRRR\n:divh R0004, R1115 is op0510=0x02 & R0004 & R1115\n{\n\t$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);\n\tR1115 = R1115 / R0004;\n\tset_Z(R1115);\n\tset_S(R1115);\n}\n\n# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000\n:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731\n{\n\tlocal quot:4 = R1115 s/ sext(R0004:2);\n\tlocal mod:4 = R1115 s% sext(R0004:2);\n\t$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);\n\tset_Z(R1115);\n\tset_S(R1115);\n\tR1115 = quot;\n\tR2731 = mod;\n}\n\n# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010\n:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731\n{\n\tlocal quot:4 = R1115 / sext(R0004:2);\n\tlocal mod:4 = R1115 % sext(R0004:2);\n\t$(OV) = (R0004 == 0);\n\tset_Z(R1115);\n\tset_S(R1115);\n\tR1115 = quot;\n\tR2731 = mod;\n}\n\n# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010\n:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731\n{\n\tlocal quot:4 = R1115 / R0004;\n\tlocal mod:4 = R1115 % R0004;\n\t$(OV) = (R0004 == 0);\n\tset_Z(R1115);\n\tset_S(R1115);\n\tR1115 = quot;\n\tR2731 = mod;\n}\n\n\n\n#####################################################\n#####\t\t HighSpeedDivide\t\t#####\n#####################################################\n\n\n# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100\n:divq R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731\n{\n\tlocal quot:4 = R1115 s/ R0004;\n\tlocal mod:4 = R1115 s% R0004;\n\t$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);\n\tset_Z(R1115);\n\tset_S(R1115);\n\tR2731 = mod;\n\tR1115 = quot;\n}\n\n# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110\n:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731\n{\n\tlocal quot:4 = R1115 / R0004;\n\tlocal mod:4 = R1115 % R0004;\n\t$(OV) = (R0004 == 0);\n\tset_Z(R1115);\n\tset_S(R1115);\n\tR2731 = mod;\n\tR1115 = quot;\n}\n" }, { "path": "pypcode/processors/V850/data/languages/Instructions/Float.sinc", "content": "#####################################################\n#####\t\t Float\t\t\t#####\n#####################################################\n\n\n# ABSF.D reg2, reg3 - rrrr011111100000|wwww010001011000\n:absf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11000\n{\n\tR2731x2 = abs(R1115x2);\n}\n\n# ABSF.S reg2, reg3 - rrrrr11111100000|wwwww10001001000\n:absf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01000\n{\n\tR2731 = abs(R1115);\n}\n\n# ADDF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110000\n:addf.d R0004x2, R1115x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2 ; R2731x2 & op2126=0b100011 & op1620=0b10000\n{\n\tR2731x2 = R1115x2 f+ R0004x2;\n}\n\n# ADDF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100000\n:addf.s R0004, R1115, R2731 is R1115 & op0510=0x3F & R0004 ; R2731 & op2126=0b100011 & op1620=0b00000\n{\n\tR2731 = R1115 f+ R0004;\n}\n\n# CEILF.DL reg2, reg3 - rrrr011111100010|wwww010001010100\n:ceilf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tlocal var:8 = ceil(float2float(R1115x2));\n\tR2731x2 = trunc(var);\n}\n\n# CEILF.DUL reg2, reg3 - rrrr011111110010|wwww010001010100\n:ceilf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tlocal var:8 = ceil(float2float(R1115x2));\n\tR2731x2 = trunc(var);\n}\n\n# CEILF.DUW reg2, reg3 - rrrrr11111110010|wwwww10001010000\n:ceilf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(ceil(R1115x2));\n}\n\n# CEILF.DW reg2, reg3 - rrrrr11111100010|wwwww10001010000\n:ceilf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(ceil(R1115x2));\n}\n\n# CEILF.SL reg2, reg3 - rrrrr11111100010|wwww010001000100\n:ceilf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tlocal var:8 = ceil(float2float(R1115));\n\tR2731x2 = trunc(var);\n}\n\n# CEILF.SUL reg2, reg3 - rrrrr11111110010|wwwww10001000100\n:ceilf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tlocal var:8 = ceil(float2float(R1115));\n\tR2731x2 = trunc(var);\n}\n\n# CEILF.SUW reg2, reg3 - rrrrr11111110010|wwwww10001000000\n:ceilf.sul R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(ceil(R1115));\n}\n\n# CEILF.SW reg2, reg3 - rrrrr11111100010|wwwww10001000000\n:ceilf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(ceil(R1115));\n}\n\n# CMOVF.D fcbit, reg1, reg2, reg3 - rrrr0111111RRRR0|wwww01000001fff0\n:cmovf.d fcbit1719, R1115x2, R0004x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2; R2731x2 & op2126=0b100000 & op2020=1 & fcbit1719 & op1616=0\n{\n\t#CC0 = Bit 24\n\tlocal bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1;\n\teither_or1(R2731x2, bit, R0004x2, R1115x2);\n}\n\n# CMOVF.S fcbit, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww1000000fff0\n:cmovf.s fcbit1719, R1115, R0004, R2731 is R1115 & op0510=0x3F & R0004; R2731 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0\n{\n\tlocal bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1;\n\teither_or1(R2731, bit, R0004, R1115);\n}\n\n# CMPF.D fcond, reg2, reg1, fcbit - rrrr0111111RRRRR|0FFFF1000011fff0\n:cmpf.d fcond2730, R1115x2, R0004x2, fcbit1719 is R1115x2 & op0510=0x3F & R0004x2; op3131=0 & fcond2730 & op2126=0b100001 & op2020=1 & fcbit1719 & op1616=0\n{\n\t#0 = Unordered\n\t#1 = Equal to\n\t#2 = Less than\n\t#3 = Exeption\n\t#bits = ex le eq un \n\n\tlocal bit:4 = 0;\n\tcompare_float(bit, fcond2730:1, R0004x2, R1115x2);\n\n\tlocal pos:4 = bit << (fcbit1719 + 24);\t#find position of the calculated bit\n\tlocal mask:4 = 1 << (fcbit1719 + 24);\t#create mask to clean old bit in FPSR register\n\tFPSR = (FPSR & ~mask) | pos;\t\t\t#set the new bit at the right position\n}\n\n# CMPF.S fcond, reg2, reg1, fcbit - rrrrr111111RRRRR|0FFFF1000010fff0\n:cmpf.s fcond2730, R1115, R0004, fcbit1719 is R1115 & op0510=0x3F & R0004; op3131=0 & fcond2730 & op2126=0b100001 & op2020=0 & fcbit1719 & op1616=0\n{\n\tlocal bit:4 = 0;\n\tcompare_float(bit, fcond2730:1, R0004, R1115);\n\n\tlocal pos:4 = bit << (fcbit1719 + 24);\t#find position of the calculated bit\n\tlocal mask:4 = 1 << (fcbit1719 + 24);\t#create mask to clean old bit in FPSR register\n\tFPSR = (FPSR & ~mask) | pos;\t\t\t#set the new bit at the right position\n}\n\n# CVTF.DL reg2, reg3 - rrrr011111100100|wwww010001010100\n:cvtf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tR2731x2 = int2float(R1115x2);\n}\n\n# CVTF.DS reg2, reg3 - rrrr011111100011|wwww010001010010\n:cvtf.ds R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10010\n{\n\tR2731 = float2float(R1115x2);\n}\n\n# CVTF.DUL reg2, reg3 - rrrr011111110100|wwww010001010100\n:cvtf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tR2731x2 = trunc(R1115x2);\n}\n\n# CVTF.DUW reg2, reg3 - rrrrr11111110100|wwwww10001010000\n:cvtf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(R1115x2);\n}\n\n# CVTF.DW reg2, reg3 - rrrrr11111100100|wwwww10001010000\n:cvtf.sw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(R1115x2);\n}\n\n# CVTF.LD reg2, reg3 - rrrr011111100001|wwww010001010010\n:cvtf.ls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10010\n{\n\tR2731x2 = int2float(R1115x2);\n}\n\n# CVTF.LS reg2, reg3 - rrrr011111100001|wwwww10001000010\n:cvtf.ls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00010\n{\n\tR2731 = int2float(R1115x2);\n}\n\n# CVTF.SD reg2, reg3 - rrrrr11111100010|wwww010001010010\n:cvtf.sd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10010\n{\n\tR2731x2 = float2float(R1115);\n}\n\n# CVTF.SL reg2, reg3 - rrrrr11111100100|wwwww10001000100\n:cvtf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tR2731x2 = trunc(R1115);\n}\n\n# CVTF.SUL reg2, reg3 - rrrrr11111110100|wwwww10001000100\n:cvtf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tR2731x2 = trunc(R1115);\n}\n\n# CVTF.SUW reg2, reg3 - rrrrr11111110100|wwwww10001000000\n:cvtf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(R1115);\n}\n\n# CVTF.SW reg2, reg3 - rrrrr11111100100|wwwww10001000000\n:cvtf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(R1115);\n}\n\n# CVTF.ULD reg2, reg3 - rrrr011111100001|wwww010001010010\n:cvtf.uls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10010\n{\n\tR2731x2 = int2float(R1115x2);\n}\n\n# CVTF.ULS reg2, reg3 - rrrr011111110001|wwwww10001000010\n:cvtf.uls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00010\n{\n\tR2731 = int2float(R1115x2);\n}\n\n# CVTF.UWD reg2, reg3 - rrrrr11111110000|wwwww10001010010\n:cvtf.uwd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10000; R2731x2 & op2126=0b100010 & op1620=0b10010\n{\n\tR2731x2 = int2float(R1115);\n}\n\n# CVTF.UWS reg2, reg3 - rrrrr11111110000|wwwww10001000010\n:cvtf.uws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10000; R2731 & op2126=0b100010 & op1620=0b00010\n{\n\tR2731 = int2float(R1115);\n}\n\n# CVTF.WD reg2, reg3 - rrrrr11111100000|wwwww10001010010\n:cvtf.wd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b10010\n{\n\tR2731x2 = int2float(R1115);\n}\n\n# CVTF.WS reg2, reg3 - rrrrr11111100000|wwwww10001000010\n:cvtf.ws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b00010\n{\n\tR2731 = int2float(R1115);\n}\n\n# DIVF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111110\n:divf.s R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11110\n{\n\tR2731x2 = R1115x2 f/ R0004x2;\n}\n\n# DIVF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101110\n:divf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01110\n{\n\tR2731 = R1115 f/ R0004;\n}\n\n# FLOORF.DL reg2, reg3 - rrrr011111100011|wwww010001010100\n:floorf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tlocal var:8 = floor(float2float(R1115x2));\n\tR2731x2 = trunc(var);\n}\n\n# FLOORF.DUL reg2, reg3 - rrrr011111110011|wwww010001010100\n:floorf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tlocal var:8 = floor(float2float(R1115x2));\n\tR2731x2 = trunc(var);\n}\n\n# FLOORF.DUW reg2, reg3 - rrrrr11111110011|wwwww10001010000\n:floorf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(floor(R1115x2));\n}\n\n# FLOORF.DW reg2, reg3 - rrrrr11111100011|wwwww10001010000\n:floorf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(floor(R1115x2));\n}\n\n# FLOORF.SL reg2, reg3 - rrrrr11111100011|wwww010001000100\n:floorf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tlocal var:8 = floor(float2float(R1115));\n\tR2731x2 = trunc(var);\n}\n\n# FLOORF.SUL reg2, reg3 - rrrrr11111110011|wwwww10001000100\n:floorf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tlocal var:8 = floor(float2float(R1115));\n\tR2731x2 = trunc(var);\n}\n\n# FLOORF.SUW reg2, reg3 - rrrrr11111110011|wwwww10001000000\n:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(floor(R1115));\n}\n\n# FLOORF.SW reg2, reg3 - rrrrr11111100011|wwwww10001000000\n:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(floor(R1115));\n}\n\n# FMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100000\n:fmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00000\n{\n\tR2731 = (R1115 f* R0004) f+ R2731;\n}\n\n# FMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100010\n:fmsf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00010\n{\n\tR2731 = (R1115 f* R0004) f- R2731;\n}\n\n# FNMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100100\n:fnmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00100\n{\n\tR2731 = -1 f* ((R1115 f* R0004) f+ R2731);\n}\n\n# FNMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100110\n:fnmfs.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00110\n{\n\tR2731 = -1 f* ((R1115 f* R0004) f- R2731);\n}\n\n# MADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W00WWWW0\n:maddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b00 & op1616=0 & reg4\n{\n\treg4 = (R1115 f* R0004) f+ R2731;\n}\n\n# MAXF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111000\n:maxf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11000\n{\n\tlocal bigger:1 = R1115x2 f> R0004x2;\n\teither_or(R2731x2, bigger, R1115x2, R0004x2);\n}\n\n# MAXF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101000\n:maxf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01000\n{\n\tlocal bigger:1 = R1115 f> R0004;\n\teither_or(R2731, bigger, R1115, R0004);\n}\n\n# MINF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111010\n:minf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11010\n{\n\tlocal bigger:1 = R1115x2 f< R0004x2;\n\teither_or(R2731x2, bigger, R1115x2, R0004x2);\n}\n\n# MINF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001101010\n:minf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01010\n{\n\tlocal bigger:1 = R1115 f< R0004;\n\teither_or(R2731, bigger, R1115, R0004);\n}\n\n# MSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W01WWWW0\n:msubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b01 & op1616=0 & reg4\n{\n\treg4 = (R1115 f* R0004) f- R2731;\n}\n\n# MULF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110100\n:mulf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10100\n{\n\tR2731x2 = R1115x2 f* R0004x2;\n}\n\n# MULF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001100100\n:mulf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00100\n{\n\tR2731 = R1115 f* R0004;\n}\n\n# NEGF.D reg2, reg3 - rrrr011111100001|wwww010001011000\n:negf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11000\n{\n\tR2731x2 = f- R1115x2;\n}\n\n# NEGF.S reg2, reg3 - rrrrr11111100001|wwwww10001001000\n:negf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01000\n{\n\tR2731 = f- R1115;\n}\n\n# NMADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W10WWWW0\n:nmaddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b10 & op1616=0 & reg4\n{\n\treg4 = f-((R1115 f* R0004) f+ R2731);\n}\n\n# NMSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W11WWWW0\n:nmsubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b11 & op1616=0 & reg4\n{\n\treg4 = f-((R1115 f* R0004) f- R2731);\n}\n\n# RECIPF.D reg2, reg3 - rrrr011111100001|wwww010001011110\n:recipf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11110\n{\n\tR2731x2 = 1 f/ R1115x2;\n}\n\n# RECIPF.S reg2, reg3 - rrrrr11111100001|wwwww10001001110\n:recipf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01110\n{\n\tR2731 = 1 f/ R1115;\n}\n\n# RSQRTF.D reg2, reg3 - rrrr011111100010|wwwww10001011110\n:rsqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b11110\n{\n\tR2731x2 = 1 f/ sqrt(R1115x2);\n}\n\n# RSQRTF.S reg2, reg3 - rrrrr11111100010|wwwww10001001110\n:rsqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b01110\n{\n\tR2731 = 1 f/ sqrt(R1115);\n}\n\n# SQRTF.D reg2, reg3 - rrrr011111100000|wwww010001011110\n:sqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11110\n{\n\tR2731x2 = sqrt(R1115x2);\n}\n\n# SQRTF.S reg2, reg3 - rrrrr11111100000|wwwww10001001110\n:sqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01110\n{\n\tR2731 = sqrt(R1115);\n}\n\n# SUBF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110010\n:subf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10010\n{\n\tR2731x2 = R1115x2 f- R0004x2;\n}\n\n# SUBF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100010\n:subf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00010\n{\n\tR2731 = R1115 f- R0004;\n}\n\n# TRFSR fcbit - 0000011111100000|000001000000fff0\n:trfsr fcbit1719 is op1115=0 & op0510=0x3F & op0004=0; op2731=0 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0\n{\n\tlocal var:4 = FPSR & (1 << (fcbit1719 + 24));\n\t$(Z) = (var != 0);\n}\n\n# TRNCF.DL reg2, reg3 - rrrr011111100001|wwww010001010100\n:trncf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tR2731x2 = trunc(R1115x2);\n}\n\n# TRNCF.DUL reg2, reg3 - rrrr011111110001|wwww010001010100\n:trncf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10100\n{\n\tR2731x2 = trunc(R1115x2);\n}\n\n# TRNCF.DUW reg2, reg3 - rrrrr11111110001|wwwww10001010000\n:trncf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(R1115x2);\n}\n\n# TRNCF.DW reg2, reg3 - rrrrr11111100001|wwwww10001010000\n:trncf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b10000\n{\n\tR2731 = trunc(R1115x2);\n}\n\n# TRNCF.SL reg2, reg3 - rrrrr11111100001|wwww010001000100\n:trncf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tR2731x2 = trunc(R1115);\n}\n\n# TRNCF.SUL reg2, reg3 - rrrrr11111110001|wwww010001000100\n:trncf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b00100\n{\n\tR2731x2 = trunc(R1115);\n}\n\n# TRNCF.SUW reg2, reg3 - rrrrr11111110001|wwwww10001000000\n:trncf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(R1115);\n}\n\n# TRNCF.SW reg2, reg3 - rrrrr11111100001|wwwww10001000000\n:trncf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00000\n{\n\tR2731 = trunc(R1115);\n}\n" }, { "path": "pypcode/processors/V850/data/languages/Instructions/Load_Store.sinc", "content": "# (1) Load instructions\n# (2) Store instructions\n# (9) Data manipulation instructions\n\n\n\n#####################################################\n#####\t\t \tLoad\t\t\t#####\n#####################################################\n\n\n# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd\n:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631\n{\n\tlocal adr:4 = R0004 + s1631;\n\tR1115 = sext(*:1 adr);\n}\n\n# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD\n:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247\n[ disp23 = (s3247 << 7) | op2026; ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tR2731 = sext(*:1 adr);\n}\n\n# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1\n:ld.bu disp16[R0004], R1115 is op0610=0x1E & R0004 & R1115 & op0505; op1616=0x1 & s1731 \n[ disp16 = (s1731 << 1) | op0505; ]\n{\n\tlocal adr:4 = R0004 + disp16;\n\tR1115 = zext(*:1 adr);\n}\n\n# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD\n:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247\n[ disp23 = (s3247 << 7) | op2026; ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tR2731 = zext(*:1 adr);\n}\n\n# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0\n:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0\n{\n\tlocal adr:4 = R0004 + s1631;\n\tR1115 = sext(*:2 adr);\n}\n\n# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD\n:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247\n[ disp23 = (s3247 << 7) | (op2126 << 1); ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tR2731 = sext(*:2 adr);\n}\n\n# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1\n:ld.hu disp16[R0004], R1115 is op0510=0x3F & R0004 & R1115; op1616=0x1 & s1731 \n[ disp16 = s1731 << 1; ]\n{\n\tlocal adr:4 = R0004 + disp16;\n\tR1115 = zext(*:2 adr);\n}\n\n# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD\n:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247\n[ disp23 = (s3247 << 7) | op2026; ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tR2731 = zext(*:2 adr);\n}\n\n# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1\n:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1 \n[ disp16 = s1731 * 2; ]\n{\n\tlocal adr:4 = R0004 + disp16;\n\tR1115 = *:4 adr;\n}\n\n# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD\n:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247\n[ disp23 = (s3247 << 7) | (op2126 << 1); ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tR2731 = *:4 adr;\n}\n\n# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd\n:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep\n{\n\tlocal adr:4 = ep + op0006;\n\tR1115 = sext(*:1 adr);\n}\n\n# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd\n:sld.bu op0003[ep], R1115 is op0410=0x06 & R1115 & op0003 & ep\n{\n\tlocal adr:4 = ep + op0003;\n\tR1115 = zext(*:1 adr);\n}\n\n# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd\n:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep\n[ disp8 = op0006 * 2; ]\n{\n\tlocal adr:4 = ep + disp8;\n\tR1115 = sext(*:2 adr);\n}\n\n# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd\n:sld.hu disp5[ep], R1115 is op0410=0x07 & R1115 & op0003 & ep\n[ disp5 = op0003 * 2; ]\n{\n\tlocal adr:4 = ep + disp5;\n\tR1115 = zext(*:2 adr);\n}\n\n# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0\n:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep\n[ disp8 = op0106 * 4; ]\n{\n\tlocal adr:4 = ep + disp8;\n\tR1115 = *:4 adr;\n}\n\n\n\n#####################################################\n#####\t\t \tStore\t\t\t#####\n#####################################################\n\n\n# SST.B reg2, disp7[ep] - rrrrr0111ddddddd\n:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep\n{\n\tlocal adr:4 = ep + op0006;\n\tlocal tmp:4 = R1115;\n\t*:1 adr = tmp:1;\n}\n\n# SST.H reg2, disp8[ep] - rrrrr1001ddddddd\n:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep\n[ disp8 = op0006 * 2; ]\n{\n\tlocal adr:4 = ep + disp8;\n\tlocal tmp:4 = R1115;\n\t*:2 adr = tmp:2;\n}\n\n# SST.W reg2, disp8[ep] - rrrrr1010dddddd1\n:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep\n[ disp8 = op0106 * 4; ]\n{\n\tlocal adr:4 = ep + disp8;\n\tlocal tmp:4 = R1115;\n\t*:4 adr = tmp;\n}\n\n# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd\n:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631\n{\n\tlocal adr:4 = R0004 + s1631;\n\tlocal tmp:4 = R1115;\n\t*:1 adr = tmp:1;\n}\n\n# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd\n:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247\n[ disp23 = (s3247 << 7) | op2026; ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tlocal tmp:4 = R2731;\n\t*:1 adr = tmp:1;\n}\n\n# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0\n:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0\n{\n\tlocal adr:4 = R0004 + s1631;\n\tlocal tmp:4 = R1115;\n\t*:2 adr = tmp:2;\n}\n\n# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD\n:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247\n[ disp23 = (s3247 << 7) | (op2126 << 1); ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tlocal tmp:4 = R2731;\n\t*:2 adr = tmp:2;\n}\n\n# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1\n:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1 \n[ disp16 = s1731 * 2; ]\n{\n\tlocal adr:4 = R0004 + disp16;\n\tlocal tmp:4 = R1115;\n\t*:4 adr = tmp;\n}\n\n# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD\n:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247\n[ disp23 = (s3247 << 7) | (op2126 << 1); ]\n{\n\tlocal adr:4 = R0004 + disp23;\n\tlocal tmp:4 = R2731;\n\t*:2 adr = tmp:2;\n}\n\n\n\n#####################################################\n#####\t\t DataManipulation\t\t#####\n#####################################################\n\n\n# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010\n:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731\n{\n\tlocal x1 = R1115[0,8];\n\tlocal x2 = R1115[8,8];\n\tlocal x3 = R1115[16,8];\n\tlocal x4 = R1115[24,8];\n\tR2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2);\n\tset_S(R2731);\n\t$(OV) = 0;\n\t$(Z) = (x1 == 0) && (x2 == 0);\n\t$(CY) = (x1 == 0) || (x2 == 0);\n}\n\n# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000\n:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731\n{\n\tlocal x1 = R1115[0,8];\n\tlocal x2 = R1115[8,8];\n\tlocal x3 = R1115[16,8];\n\tlocal x4 = R1115[24,8];\n\tR2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4);\n\tset_OV0_S_Z(R2731);\n\t$(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0);\n}\n\n# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0\n:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731\n{\n\tlocal result:4 = zext(c1720);\n\tR2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0);\n}\n\n# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0\n:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731\n{\n\tlocal result:4 = zext(c1720);\n\tR2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0);\n}\n\n# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110\n:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731\n{\n\tR2731 = R1115;\n\tset_S(R2731);\n\t$(OV) = 0;\n\t$(Z) = (R2731:2 == 0);\n\t$(CY) = $(Z);\n}\n\n# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100\n:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731\n{\n\tlocal x1 = R1115:2;\n\tlocal x2 = R1115[16,16];\n\tR2731 = zext(x1 << 16) | zext(x2);\n\tset_OV0_S_Z(R2731);\n\t$(CY) = (x1 == 0) || (x2 == 0);\n}\n\n# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000\n:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0\n{\n\tshift_right_arith(R1115, R1115, R0004);\n}\n\n# SAR imm5, reg2 - rrrrr010101iiiii\n:sar op0004, R1115 is op0510=0x15 & op0004 & R1115\n{\n\tshift_right_arith(R1115, R1115, op0004:5);\n}\n\n# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010\n:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731\n{\n\tshift_right_arith(R2731, R1115, R0004);\n}\n\n# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000\n:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200\n{\n\tR1115 = (R1115 << 1) | zext(c0003);\n}\n\n# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000\n:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0\n{\n\tR1115 = zext(c0003);\n}\n\n# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000\n:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0\n{\n\tshift_left_logic(R1115, R1115, R0004);\n}\n\n# SHL imm5, reg2 - rrrrr010110iiiii\n:shl op0004, R1115 is op0510=0x16 & op0004 & R1115\n{\n\tshift_left_logic(R1115, R1115, op0004:5);\n}\n\n# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010\n:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731\n{\n\tshift_left_logic(R2731, R1115, R0004);\n}\n\n# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000\n:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80\n{\n\tshift_right_logic(R1115, R1115, R0004);\n}\n\n# SHR imm5, reg2 - rrrrr010100iiiii\n:shr op0004, R1115 is op0510=0x14 & op0004 & R1115\n{\n\tshift_right_logic(R1115, R1115, op0004:5);\n}\n\n# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010\n:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731\n{\n\tshift_right_logic(R2731, R1115, R0004);\n}\n\n# SXB reg1 - 00000000101RRRRR\n:sxb R0004 is op0515=0x05 & R0004\n{\n\tR0004 = sext(R0004:1);\n}\n\n# SXH reg1 - 00000000111RRRRR\n:sxh R0004 is op0515=0x07 & R0004\n{\n\tR0004 = sext(R0004:2);\n}\n\n# ZXB reg1 - 00000000100RRRRR\n:zxb R0004 is op0515=0x004 & R0004\n{\n\tR0004 = zext(R0004:1);\n}\n\n# ZXH reg1 - 00000000110RRRRR\n:zxh R0004 is op0515=0x006 & R0004\n{\n\tR0004 = zext(R0004:2);\n}\n" }, { "path": "pypcode/processors/V850/data/languages/Instructions/Logic.sinc", "content": "# (6) Conditional arithmetic instructions\n# (8) Logical instructions\n# (14) Bit manipulation instructions\n\n\n\n#####################################################\n#####\t Conditional\t\t#####\n#####################################################\n\n\n# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0\n:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731\n{\n\tlocal cond = zext(c1720);\n\tset_OV_pos2(R1115, R0004, cond);\n\tset_CY_pos2(R1115, R0004, cond);\n\tR2731 = R1115 + R0004 + cond;\n\tset_S(R2731);\n\tset_Z(R2731);\n}\n\n# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0\n:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731\n{\n\tlocal cond = zext(c1720);\n\tset_OV_neg2(R1115, R0004, cond);\n\tset_CY_neg2(R1115, R0004, cond);\n\tR2731 = R1115 - R0004 - cond;\n\tset_S(R2731);\n\tset_Z(R2731);\n}\n\n\n\n#####################################################\n#####\t\t \tLogic\t\t\t#####\n#####################################################\n\n\n# AND reg1, reg2 - rrrrr001010RRRRR\n:and R0004, R1115 is op0510=0x0A & R0004 & R1115\n{\n\tR1115 = R1115 & R0004;\n\tset_OV0_S_Z(R1115);\n}\n\n# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii\n:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631\n{\n\tR1115 = R0004 & op1631;\n\tset_OV0_S_Z(R1115);\n}\n\n# NOT reg1, reg2 - rrrrr000001RRRRR\n:not R0004, R1115 is op0510=0x01 & R0004 & R1115\n{\n\tR1115 = ~R0004;\n\tset_OV0_S_Z(R1115);\n}\n\n# OR reg1, reg2 - rrrrr001000RRRRR\n:or R0004, R1115 is op0510=0x08 & R0004 & R1115\n{\n\tR1115 = R1115 | R0004;\n\tset_OV0_S_Z(R1115);\n}\n\n# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii\n:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631\n{\n\tR1115 = R0004 | op1631;\n\tset_OV0_S_Z(R1115);\n}\n\n# TST reg1, reg2 - rrrrr001011RRRRR\n:tst R0004, R1115 is op0510=0x0B & R0004 & R1115\n{\n\tset_OV0_S_Z(R1115 & R0004);\n}\n\n# XOR reg1, reg2 - rrrrr001001RRRRR\n:xor R0004, R1115 is op0510=0x09 & R0004 & R1115\n{\n\tR1115 = R1115 ^ R0004;\n\tset_OV0_S_Z(R1115);\n}\n\n# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii\n:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631\n{\n\tR1115 = R0004 ^ op1631;\n\tset_OV0_S_Z(R1115);\n}\n\n\n\n#####################################################\n#####\t\t BitManipulation\t\t#####\n#####################################################\n\n\n# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd\n:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631\n{\n\tlocal adr:4 = R0004 + s1631;\n\tlocal tkn = *:1 adr;\n\t*:1 adr = tkn & ~(1 << op1113);\n\tset_Z(tkn & (1 << op1113));\n}\n\n# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100\n:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4\n{\n\tlocal tkn = *:1 R0004;\n\t*:1 R0004 = tkn & ~(1 << R1115);\n\tset_Z(tkn & (1 << R1115));\n}\n\n# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd\n:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631\n{\n\tlocal adr:4 = R0004 + s1631;\n\tlocal tkn = *:1 adr;\n\t*:1 adr = tkn ^ (1 << op1113);\n\tset_Z(tkn & (1 << op1113));\n}\n\n# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010\n:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2\n{\n\tlocal tkn = *:1 R0004;\n\t*:1 R0004 = tkn ^ (1 << R1115);\n\tset_Z(tkn & (1 << R1115));\n}\n\n# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd\n:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631\n{\n\tlocal adr:4 = R0004 + s1631;\n\tlocal tkn = *:1 adr;\n\t*:1 adr = tkn | (1 << op1113);\n\tset_Z(tkn & (1 << op1113));\n}\n\n# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000\n:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0\n{\n\tlocal tkn = *:1 R0004;\n\t*:1 R0004 = tkn | (1 << R1115);\n\tset_Z(tkn & (1 << R1115));\n}\n\n# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd\n:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631\n{\n\tlocal adr:4 = R0004 + s1631;\n\tlocal tkn = *:1 adr;\n\tset_Z(tkn & (1 << op1113));\n}\n\n# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110\n:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6\n{\n\tlocal tkn = *:1 R0004;\n\tset_Z(tkn & (1 << R1115));\n}\n" }, { "path": "pypcode/processors/V850/data/languages/Instructions/Special.sinc", "content": "# (10) Bit search instructions\n# (13) Branch instructions\n# (15) Special instructions\n\n\n\n#####################################################\n#####\t\t BitSearch\t\t\t#####\n#####################################################\n\n\n# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100\n:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731\n{\n\tSearchLeft(R2731, R1115, 0);\n\t$(CY) = (R1115 != 0xFFFFFFFF);\t\t# zero bit found\n\t$(Z) = (R1115 == 0xFFFFFFFF);\t\t# zero bit not found\n}\n\n# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000\n:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731\n{\n\tSearchRight(R2731, R1115, 0);\n\t$(CY) = (R1115 != 0xFFFFFFFF);\t\t# zero bit found\n\t$(Z) = (R1115 == 0xFFFFFFFF);\t\t# zero bit not found\n}\n\n# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110\n:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731\n{\n\tSearchLeft(R2731, R1115, 1);\n\t$(CY) = (R1115 != 0x0);\t\t# one bit found\n\t$(Z) = (R1115 == 0x0);\t\t# one bit not found\n}\n\n# SCH1R reg2, reg3\n:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731\n{\n\tSearchRight(R2731, R1115, 1);\n\t$(CY) = (R1115 != 0x0);\t\t# one bit found\n\t$(Z) = (R1115 == 0x0);\t\t# one bit not found\n}\n\n\n\n#####################################################\n#####\t\t Branch\t\t\t#####\n#####################################################\n\n\n#Bcond adr9 - ddddd1011dddcccc\n:b^c0003 adr9 is op0710=0xB & c0003 & adr9\n{\n\tif (c0003) \n\t\tgoto adr9;\n}\n:br adr9 is op0710=0xB & op0003=0x5 & adr9\n{\n\tgoto adr9;\n}\n\n# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0\n:jarl adr22, R1115 is (op0610=0x1E & R1115) ... & adr22\n{\n\tR1115 = inst_next;\n\tcall adr22;\n}\n\n# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD\n:jarl adr32, R0004 is op0515=0x017 & R0004; adr32\n{\n\tR0004 = inst_next;\n\tcall adr32;\n}\n\n# JMP [reg1] - 00000000011RRRRR\n:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F\n{\n\treturn [R0004];\n}\n:jmp [R0004] is op0515=0x03 & R0004 & op0004!=0x1F\n{\n\tcall [R0004];\n}\n\n# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD\n:jmp adr32i[R0004] is op0515=0x037 & R0004; adr32i\n{\n\tlocal adr = adr32i + R0004;\n\tgoto [adr];\n}\n\n# JR disp22 - 00000111110ddddd|ddddddddddddddd0\n:jr adr22 is op0615=0x1E ... & adr22\n{\n\tgoto adr22;\n}\n\n# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD\n:jr adr32 is op0015=0x2E0; adr32\n{\n\tgoto adr32;\n}\n\n\n\n#####################################################\n#####\t\t Special\t\t\t#####\n#####################################################\n\n\n# CALLT imm6 - 0000001000iiiiii\n:callt op0005 is op0615=0x8 & op0005 \n{\n\tCTPC = inst_next;\n\tCTPSW = PSW;\n\tlocal adr:4 = CTBP + (op0005 << 1);\n\tPC = CTBP + zext(*:2 adr);\n\tcall [PC];\n}\n\n# CAXI [reg1], reg2, reg3 - rrrrr111111RRRRR|wwwww00011101110\n:caxi [R0004], R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xEE & R2731\n{\n\tlocal tkn = *:4 (R0004 & ~(0x3));\n\tlocal result = R1115 - tkn;\n\t*:4 R0004 = tkn * zext(result != 0) + R2731 * zext(result == 0);\n\tR2731 = tkn;\n\tset_general_flags_neg(R1115, tkn);\n}\n\n# CTRET - 0000011111100000|0000000101000100\n:ctret is op0515=0x3F; op1631=0x144\n{\n\tPC = CTPC;\n\tPSW = CTPSW;\n\treturn [PC];\n}\n\n# DI - 0000011111100000|0000000101100000\ndefine pcodeop __disable_irq;\n:di is op0015=0x7E0; op1631=0x160\n{\n\t$(ID) = 1;\n\t__disable_irq();\n}\n\n# DISPOSE imm5, list12 - 0000011001iiiiiL|LLLLLLLLLLL00000\n:dispose prep0105, DispList is prep0615=0x19 & prep1620=0x0 & prep0105 & DispList\n{\n\tsp = sp + (prep0105 << 2);\n\tbuild DispList;\n}\n\n# DISPOSE imm5, list12, [reg1] - 0000011001iiiiiL|LLLLLLLLLLLRRRRR\n:dispose prep0105, DispList, [prep1620] is prep0615=0x19 & prep1620 & prep0105 & DispList\n{\n\tsp = sp + (prep0105 << 2);\n\tbuild DispList;\n\tPC = prep1620;\n\treturn [PC];\n}\n\n# EI - 1000011111100000|0000000101100000\ndefine pcodeop __enable_irq;\n:ei is op0015=0x87E0; op1631=0x160\n{\n\t$(ID) = 0;\n\t__enable_irq();\n}\n\n# EIRET - 0000011111100000|0000000101001000\n:eiret is op0515=0x3F; op1631=0x148\n{\n\tPC = EIPC;\n\tPSW = EIPSW;\n\treturn [PC];\n}\n\n# FERET - 0000011111100000|0000000101001010\n:feret is op0515=0x3F; op1631=0x14A\n{\n\tPC = FEPC;\n\tPSW = FEPSW;\n\treturn [PC];\n}\n\n# FETRAP vector4 - 0vvvv00001000000\n:fetrap op1114 is op0010=0x40 & op1515=0 & op1114 & op1115!=0\n{\n\tFEPC = inst_next;\n\tFEPSW = PSW;\n\t$(FECC) = op1114 + 0x30;\t# exception code 0x30..0x3F\n\tFEIC = op1114 + 0x30;\t\t# exception code 0x30..0x3F\n\t$(EP) = 1;\n\t$(ID) = 1;\n\t$(NP) = 1;\n\tPC = 0x30;\n\tgoto [PC];\n}\n\n# HALT - 0000011111100000|0000000100100000\ndefine pcodeop __halt;\n:halt is op0015=0x7E0; op1631=0x120\n{\n\t__halt();\n}\n\n# LDSR reg2, regID - rrrrr111111RRRRR|0000000000100000\n:ldsr R0004, SR1115 is op0510=0x3F & SR1115 & R0004; op1631=0x20\n{\n\tSR1115 = R0004;\n}\n\n# NOP - 0000000000000000\n:nop is op0015=0x0\n{\n\tPC = inst_next;\n}\n\n# PREPARE list12, imm5 - 0000011110iiiiiL|LLLLLLLLLLL00001\n:prepare PrepList, prep0105 is prep0615=0x1E & prep0105 & prep1620=0x1 & PrepList\n{\n\tbuild PrepList;\n\tsp = sp - (prep0105 << 2);\n}\n\n# PREPARE list12, imm5, sp - 0000011110iiiiiL|LLLLLLLLLLL00011\n:prepare PrepList, prep0105, sp is prep0615=0x1E & prep0105 & prep1620=0x3 & PrepList & sp\n{\n\tbuild PrepList;\n\tsp = sp - (prep0105 << 2);\n\tep = sp;\n}\n\n# PREPARE list12, imm5, imm16 (low) - 0000011110iiiiiL|LLLLLLLLLLL01011|iiiiiiiiiiiiiiii\n:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0xB & PrepList; s3247\n{\n\tbuild PrepList;\n\tsp = sp - (prep0105 << 2);\n\tep = s3247;\n}\n\n# PREPARE list12, imm5, imm16 (high) - 0000011110iiiiiL|LLLLLLLLLLL10011|iiiiiiiiiiiiiiii\n:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0x13 & PrepList; s3247\n{\n\tbuild PrepList;\n\tsp = sp - (prep0105 << 2);\n\tep = s3247 << 16;\n}\n\n# PREPARE list12, imm5, imm32 - 0000011110iiiiiL|LLLLLLLLLLL11011|iiiiiiiiiiiiiiii|iiiiiiiiiiiiiiii\n:prepare PrepList, prep0105, imm32 is prep0615=0x1E & prep0105 & prep1620=0x1B & PrepList; op3247; op4863\n[ imm32 = (op4863 << 16) | op3247; ]\n{\n\tbuild PrepList;\n\tsp = sp - (prep0105 << 2);\n\tep = imm32;\n}\n\n# RETI - 0000011111100000|0000000101000000\n:reti is op0515=0x3F; op1631=0x140\n{\n\tif($(EP)!=1)\n\t\tgoto ;\n\n\tPC = EIPC;\n\tPSW = EIPSW;\n\tgoto ;\n\n\t\n\tif($(NP)!=1)\n\t\tgoto ;\n\n\tPC = FEPC;\n\tPSW = FEPSW;\n\tgoto ;\n\n\t\n\tPC = EIPC;\n\tPSW = EIPSW;\n\n\t\n\treturn[PC];\n}\n\n# RIE - 0000000001000000\n:rie is op0015=0x40 \n{\n\tFEPC = PC;\n\tFEPSW = PSW;\n\t$(NP) = 1;\n\t$(EP) = 1;\n\t$(ID) = 1;\n\tPC = 0x30;\n\tgoto [PC];\n}\n\n# RIE imm5, imm4 - iiiii1111111IIII|0000000000000000\n:rie op1115, op0003 is op0410=0x7F & op1115 & op0003; op1631=0x0\n{\n\tFEPC = PC;\n\tFEPSW = PSW;\n\t$(NP) = 1;\n\t$(EP) = 1;\n\t$(ID) = 1;\n\tPC = 0x30;\n\tgoto [PC];\n}\n\n# STSR regID, reg2 - rrrrr111111RRRRR|0000000001000000\n:stsr SR0004, R1115 is op0510=0x3F & R1115 & SR0004; op1631=0x40\n{\n\tR1115 = SR0004;\n}\n\n# SWITCH reg1 - 00000000010RRRRR\n:switch R0004 is op0515=0x2 & R0004\n{\n\tlocal adr:4 = inst_next + (R0004 << 1);\n\tPC = inst_next + (sext(*:2 adr) << 1);\n\tgoto [PC];\n}\n\n# SYNCE - 0000000000011101\ndefine pcodeop __synchronize;\n:synce is op0015=0x1D \n{\n\t__synchronize();\n}\n\n# SYNCM - 0000000000011110\n:syncm is op0015=0x1E\n{\n\t__synchronize();\n}\n\n# SYNCP - 0000000000011111\n:syncp is op0015=0x1F\n{\n\t__synchronize();\n}\n\n# SYSCALL vector8 - 11010111111vvvvv|00VVV00101100000\n:syscall vector8 is op0515=0x6BF & op0004; op3031=0 & op2729 & op1626=0x160 \n[ vector8 = (op2729 << 5) | op0004; ]\n{\n\tEIPC = inst_next;\n\tEIPSW = PSW;\n\tEIIC = vector8 + 0x8000;\t\t# exception code 0x8000..0x80FF\n\t$(EICC) = vector8 + 0x8000;\t\t# exception code 0x8000..0x80FF\n\t$(EP) = 1;\n\t$(ID) = 1;\n\tlocal adr:4;\n\teither_or(adr, (vector8 <= SCCFG), SCBP + (vector8 << 2), SCBP);\n\tPC = SCBP + (*:4 adr);\n\tcall [PC];\n}\n\n# TRAP imm5 - 00000111111vvvvv|0000000100000000\n:trap op0004 is op0515=0x3F & op0004; op1631=0x100\n{\n\tlocal vector5:4 = op0004;\n\tEIPC = inst_next;\n\tEIPSW = PSW;\n\tEIIC = vector5 + 0x40;\t\t\t# exception code 0x40..0x5F\n\t$(EICC) = vector5:2 + 0x40;\t\t# exception code 0x40..0x5F\n\t$(EP) = 1;\n\t$(ID) = 1;\n\teither_or(PC, (vector5 <= 15), 0x40, 0x50);\n\tcall [PC];\n}\n" }, { "path": "pypcode/processors/V850/data/languages/V850.cspec", "content": "\n\n\n\n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/V850/data/languages/V850.ldefs", "content": "\n\n\n \n Renesas V850 family\n \n \n\n" }, { "path": "pypcode/processors/V850/data/languages/V850.opinion", "content": "\n \n \n \n \n" }, { "path": "pypcode/processors/V850/data/languages/V850.pspec", "content": "\n\n\n\n \n\n \n\n \n \n \n\n\n" }, { "path": "pypcode/processors/V850/data/languages/V850.slaspec", "content": "#####################################################\n#####\t\t\t\t\t\t#####\n#####\t V850E2M SLEIGH specification \t#####\n#####\t\t\t\t\t\t#####\n#####################################################\n\ndefine endian = little;\ndefine alignment = 2;\n\n# Size & default are required\ndefine space ram type=ram_space size=4 default;\ndefine space register type=register_space size=4;\n\n\n\n#####################################################\n#####\t \t\tHelpers \t\t#####\n#####################################################\n\n@include \"./Helpers/Register.sinc\"\n@include \"./Helpers/Tokens.sinc\"\n@include \"./Helpers/Variables.sinc\"\n@include \"./Helpers/Conditions.sinc\"\n@include \"./Helpers/Macros.sinc\"\n@include \"./Helpers/Extras.sinc\"\n\n\n\n#####################################################\n#####\t \t Instructions\t\t#####\n#####################################################\n\n@include \"./Instructions/Arithmetic.sinc\"\n@include \"./Instructions/Float.sinc\"\n@include \"./Instructions/Load_Store.sinc\"\n@include \"./Instructions/Logic.sinc\"\n@include \"./Instructions/Special.sinc\"\n" }, { "path": "pypcode/processors/V850/data/manuals/v850.idx", "content": "@r01us0001ej0100_v850e2m.pdf [V850E2M Users Manual: Architecture RENESAS MCU V850E2M Microprocessor Core]\n\nADD, 71\nADDI, 72\nADF, 73\nAND, 74\nANDI, 75\nBcond, 76\nBSH, 78\nBSW, 79\nCALLT, 80\nCAXI, 81\nCLR1, 82\nCMOV, 84\nCMP, 86\nCTRET, 87\nDI, 88\nDISPOSE, 89\nDIV, 91\nDIVH, 92\nDIVHU, 94\nDIVQ, 95\nDIVQU, 96\nDIVU, 97\nEI, 98\nEIRET, 99\nFERET, 100\nFETRAP, 101\nHALT, 102\nHSH, 103\nHSW, 104\nJARL, 105\nJMP, 107\nJR, 108\nLD.B, 109\nLD.BU, 110\nLD.H, 111\nLD.HU, 112\nLD.W, 113\nLDSR, 114\nMAC, 115\nMACU, 116\nMOV, 117\nMOVEA, 118\nMOVHI, 119\nMUL, 120\nMULH, 121\nMULHI, 122\nMULU, 123\nNOP, 124\nNOT, 125\nNOT1, 126\nOR, 128\nORI, 129\nPREPARE, 130\nRETI, 132\nRIE, 134\nSAR, 135\nSASF, 137\nSATADD, 138\nSATSUB, 140\nSATSUBI, 141\nSATSUBR, 142\nSBF, 143\nSCH0L, 144\nSCH0R, 145\nSCH1L, 146\nSCH1R, 147\nSET1, 148\nSETF, 150\nSHL, 152\nSHR, 154\nSLD.B, 156\nSLD.BU, 157\nSLD.H, 158\nSLD.HU, 159\nSLD.W, 160\nSST.B, 161\nSST.H, 162\nSST.W, 163\nST.B, 164\nST.H, 165\nST.W, 166\nSTSR, 167\nSUB, 168\nSUBR, 169\nSWITCH, 170\nSXB, 171\nSXH, 172\nSYNCE, 173\nSYNCM, 174\nSYNCP, 175\nSYSCALL, 176\nTRAP, 178\nTST, 179\nTST1, 180\nXOR, 181\nXORI, 182\nZXB, 183\nZXH, 184\n\nABSF.D, 326\nABSF.S, 327\nADDF.D, 328\nADDF.S, 329\nCEILF.DL, 330\nCEILF.DUL, 331\nCEILF.DUW, 332\nCEILF.DW, 333\nCEILF.SL, 334\nCEILF.SUL, 335\nCEILF.SUW, 336\nCEILF.SW, 337\nCMOVF.D, 338\nCMOVF.S, 339\nCMPF.D, 340\nCMPF.S, 343\nCVTF.DL, 346\nCVTF.DS, 347\nCVTF.DUL, 348\nCVTF.DUW, 349\nCVTF.DW, 350\nCVTF.LD, 351\nCVTF.LS, 352\nCVTF.SD, 353\nCVTF.SL, 354\nCVTF.SUL, 355\nCVTF.SUW, 356\nCVTF.SW, 357\nCVTF.ULD, 358\nCVTF.ULS, 359\nCVTF.UWD, 360\nCVTF.UWS, 361\nCVTF.WD, 362\nCVTF.WS, 363\nDIVF.D, 364\nDIVF.S, 365\nFLOORF.DL, 366\nFLOORF.DUL, 367\nFLOORF.DUW, 368\nFLOORF.DW, 369\nFLOORF.SL, 370\nFLOORF.SUL, 371\nFLOORF.SUW, 372\nFLOORF.SW, 373\nMADDF.S, 374\nMAXF.D, 376\nMAXF.S, 377\nMINF.D, 378\nMINF.S, 379\nMSUBF.S, 380\nMULF.D, 382\nMULF.S, 383\nNEGF.D, 384\nNEGF.S, 385\nNMADDF.S, 386\nNMSUBF.S, 388\nRECIPF.D, 390\nRECIPF.S, 391\nRSQRTF.D, 392\nRSQRTF.S, 393\nSQRTF.D, 394\nSQRTF.S, 395\nSUBF.D, 396\nSUBF.S, 397\nTRFSR, 398\nTRNCF.DL, 399\nTRNCF.DUL, 400\nTRNCF.DUW, 401\nTRNCF.DW, 402\nTRNCF.SL, 403\nTRNCF.SUL, 404\nTRNCF.SUW, 405\nTRNCF.SW, 406\n" }, { "path": "pypcode/processors/V850/data/patterns/V850_patterns.xml", "content": "\n \n \n \n \n 01111111 00000000 \n \n \n 10...... 00000111 ...00001 ........ \n 10...... 00000111 ...00011 ........ \n 00000011 00011110 ........ ........ \n 10...... 00000111 ...01011 ........ ........ ........ \n 10...... 00000111 ...10011 ........ ........ ........ \n 10...... 00000111 ...11011 ........ ........ ........ ........ ........ \n \n \n \n \n \n \n 01...... 00000110 ........ ........ \n 11100000 00000111 01001010 00000001 \n 11100000 00000111 01001000 00000001 \n 11100000 00000111 01000100 00000001 \n \n \n 10...... 00000111 ...00001 ........ \n 10...... 00000111 ...00011 ........ \n 00000011 00011110 ........ ........ \n 10...... 00000111 ...11011 ........ ........ ........ ........ ........ \n 10...... 00000111 ...01011 ........ ........ ........ \n 10...... 00000111 ...10011 ........ ........ ........ \n \n \n \n \n\n" }, { "path": "pypcode/processors/V850/data/patterns/patternconstraints.xml", "content": "\n \n V850_patterns.xml\n \n\n" }, { "path": "pypcode/processors/Xtensa/data/languages/cust.sinc", "content": "# Per the manual:\n# CUST0 and CUST1 opcode encodings shown in Table 7–193 are permanently reserved\n# for designer-defined opcodes. In the future, customers who use these spaces\n# exclusively for their own designer-defined opcodes will be able to add new\n# Tensilica-defined options without changing their opcodes or binary executables.\n\ndefine pcodeop cust0;\n\n:cust0 \"{op2=\"^op2^\", r=\"^ar^\", s=\"^as^\", t=\"^at^\"}\" is op0=0x0 & op1=0x6 & op2 & ar & as & at {\n\tcust0();\n}\n\ndefine pcodeop cust1;\n\n:cust1 \"{op2=\"^op2^\", r=\"^ar^\", s=\"^as^\", t=\"^at^\"}\" is op0=0x0 & op1=0x7 & op2 & ar & as & at {\n\tcust1();\n}" }, { "path": "pypcode/processors/Xtensa/data/languages/flix.sinc", "content": "\n# FLIX (Flexible Length Instruction eXtension) is a Xtensa processor extension\n# that allows for variable-length, multi-op instructions with support from 4\n# 16 bytes. Customizable, if found they should be flagged.\n\ndefine pcodeop flix;\n:FLIX u_4_23 is op0=0xe & u_4_23 {\n\tflix();\n}" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa.dwarf", "content": "\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa.ldefs", "content": "\n\n\n \n Tensilica Xtensa 32-bit little-endian\n \n \n \n \n \n \n \n Tensilica Xtensa 32-bit big-endian\n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa.opinion", "content": "\n \n \n \n \n\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensaArch.sinc", "content": "define endian=$(ENDIAN);\ndefine alignment=1;\n\ndefine space ram type=ram_space size=4 default;\ndefine space register type=register_space size=4;\n\n# Address registers (AR).\ndefine register offset=0x0000 size=4 [\n a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15\n];\n\n# Temporary Address registers (facilitates simplified CALL register swapping used by decompiler)\ndefine register offset=0x0080 size=4 [\n t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11\n];\n\n# Floating Point registers\ndefine register offset=0x0100 size=4 [\n f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15\n];\n\n# Boolean registers (BR)\ndefine register offset=0x0200 size=1 [\n b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15\n];\n\ndefine register offset=0x0400 size=4 [\nuser0\t\tuser1\t\tuser2\t\tuser3\t\tuser4\t\tuser5\t\tuser6\t\tuser7\t\tuser8\t\tuser9\t\tuser10\t\tuser11\t\tuser12\t\tuser13\t\tuser14\t\tuser15\nuser16\t\tuser17\t\tuser18\t\tuser19\t\tuser20\t\tuser21\t\tuser22\t\tuser23\t\tuser24\t\tuser25\t\tuser26\t\tuser27\t\tuser28\t\tuser29\t\tuser30\t\tuser31\nuser32\t\tuser33\t\tuser34\t\tuser35\t\tuser36\t\tuser37\t\tuser38\t\tuser39\t\tuser40\t\tuser41\t\tuser42\t\tuser43\t\tuser44\t\tuser45\t\tuser46\t\tuser47\nuser48\t\tuser49\t\tuser50\t\tuser51\t\tuser52\t\tuser53\t\tuser54\t\tuser55\t\tuser56\t\tuser57\t\tuser58\t\tuser59\t\tuser60\t\tuser61\t\tuser62\t\tuser63\nuser64\t\tuser65\t\tuser66\t\tuser67\t\tuser68\t\tuser69\t\tuser70\t\tuser71\t\tuser72\t\tuser73\t\tuser74\t\tuser75\t\tuser76\t\tuser77\t\tuser78\t\tuser79\nuser80\t\tuser81\t\tuser82\t\tuser83\t\tuser84\t\tuser85\t\tuser86\t\tuser87\t\tuser88\t\tuser89\t\tuser90\t\tuser91\t\tuser92\t\tuser93\t\tuser94\t\tuser95\nuser96\t\tuser97\t\tuser98\t\tuser99\t\tuser100\t\tuser101\t\tuser102\t\tuser103\t\tuser104\t\tuser105\t\tuser106\t\tuser107\t\tuser108\t\tuser109\t\tuser110\t\tuser111\nuser112\t\tuser113\t\tuser114\t\tuser115\t\tuser116\t\tuser117\t\tuser118\t\tuser119\t\tuser120\t\tuser121\t\tuser122\t\tuser123\t\tuser124\t\tuser125\t\tuser126\t\tuser127\nuser128\t\tuser129\t\tuser130\t\tuser131\t\tuser132\t\tuser133\t\tuser134\t\tuser135\t\tuser136\t\tuser137\t\tuser138\t\tuser139\t\tuser140\t\tuser141\t\tuser142\t\tuser143\nuser144\t\tuser145\t\tuser146\t\tuser147\t\tuser148\t\tuser149\t\tuser150\t\tuser151\t\tuser152\t\tuser153\t\tuser154\t\tuser155\t\tuser156\t\tuser157\t\tuser158\t\tuser159\nuser160\t\tuser161\t\tuser162\t\tuser163\t\tuser164\t\tuser165\t\tuser166\t\tuser167\t\tuser168\t\tuser169\t\tuser170\t\tuser171\t\tuser172\t\tuser173\t\tuser174\t\tuser175\nuser176\t\tuser177\t\tuser178\t\tuser179\t\tuser180\t\tuser181\t\tuser182\t\tuser183\t\tuser184\t\tuser185\t\tuser186\t\tuser187\t\tuser188\t\tuser189\t\tuser190\t\tuser191\nuser192\t\tuser193\t\tuser194\t\tuser195\t\tuser196\t\tuser197\t\tuser198\t\tuser199\t\tuser200\t\tuser201\t\tuser202\t\tuser203\t\tuser204\t\tuser205\t\tuser206\t\tuser207\nuser208\t\tuser209\t\tuser210\t\tuser211\t\tuser212\t\tuser213\t\tuser214\t\tuser215\t\tuser216\t\tuser217\t\tuser218\t\tuser219\t\tuser220\t\tuser221\t\tuser222\t\tuser223\nuser224\t\tuser225\t\tuser226\t\tuser227\t\tuser228\t\tuser229\t\tuser230\t\tTHREADPTR\tFCR\t\t\tFSR\t\t\tuser234\t\tuser235\t\tuser236\t\tuser237\t\tuser238\t\tuser239\nuser240\t\tuser241\t\tuser242\t\tuser243\t\tuser244\t\tuser245\t\tuser246\t\tuser247\t\tuser248\t\tuser249\t\tuser250\t\tuser251\t\tuser252\t\tuser253\t\tuser254\t\tuser255\n];\n\n# Program counter.\ndefine register offset=0x1000 size=4 [ pc ];\n\ndefine register offset=0x2000 size=4 [\n\tLBEG\tLEND\tLCOUNT\tSAR\t\tBR\tLITBASE\tsr6\t\tsr7\t\tsr8\t\tsr9\t\tsr10\tsr11\tSCOMPARE1\tsr13\tsr14\tsr15\n@if ENDIAN == \"big\"\nACCHI\tACCLO\n@else\nACCLO\tACCHI\n@endif\n\tsr18\tsr19\tsr20\tsr21\tsr22\tsr23\tsr24\tsr25\tsr26\tsr27\tsr28\tsr29\tsr30\tsr31\n\tM0\t\tM1\t\tM2\t\tM3\t\tsr36\tsr37\tsr38\tsr39\tsr40\tsr41\tsr42\tsr43\tsr44\tsr45\tsr46\tsr47\n\tsr48\tsr49\tsr50\tsr51\tsr52\tsr53\tsr54\tsr55\tsr56\tsr57\tsr58\tsr59\tsr60\tsr61\tsr62\tsr63\n\tsr64\tsr65\tsr66\tsr67\tsr68\tsr69\tsr70\tsr71\tWindowBase\tWindowStart\tsr74\tsr75\tsr76\tsr77\tsr78\tsr79\n\tsr80\tsr81\tsr82\tPTEVADDR\tsr84\tsr85\tsr86\tsr87\tsr88\tMMID\tRASID\tITLBCFG\tDTLBCFG\tsr93\tsr94\tsr95\n\tIBREAKENABLE\tMEMCTL\tCACHEATTR\tATOMCTL\tsr100\tsr101\tsr102\tsr103\tDDR\tsr105\tMEPC\tMEPS\tMESAVE\tMESR\tMECR\tMEVADDR\n\tsr112\t\tsr113\t\tsr114\tsr115\tsr116\tsr117\tsr118\tsr119\tsr120\tsr121\tsr122\tsr123\tsr124\tsr125\tsr126\tsr127\n\tIBREAKA0\tIBREAKA1\tsr130\tsr131\tsr132\tsr133\tsr134\tsr135\tsr136\tsr137\tsr138\tsr139\tsr140\tsr141\tsr142\tsr143\n\tDBREAKA0\tDBREAKA1\tsr146\tsr147\tsr148\tsr149\tsr150\tsr151\tsr152\tsr153\tsr154\tsr155\tsr156\tsr157\tsr158\tsr159\n\tDBREAKC0\tDBREAKC1\tsr162\tsr163\tsr164\tsr165\tsr166\tsr167\tsr168\tsr169\tsr170\tsr171\tsr172\tsr173\tsr174\tsr175\n\tsr176\t\tEPC1\t\tEPC2\tEPC3\tEPC4\tEPC5\tEPC6\tEPC7\tsr184\tsr185\tsr186\tsr187\tsr188\tsr189\tsr190\tsr191\n\tDEPC\t\tsr193\t\tEPS2\tEPS3\tEPS4\tEPS5\tEPS6\tEPS7\tsr200\tsr201\tsr202\tsr203\tsr204\tsr205\tsr206\tsr207\n\tsr208\tEXCSAVE1\tEXCSAVE2\tEXCSAVE3\tEXCSAVE4\tEXCSAVE5\tEXCSAVE6\tEXCSAVE7\tsr216\tsr217\tsr218\tsr219\tsr220\tsr221\tsr222\tsr223\n#TODO: REVIEW NEEDED! - INTSET / INTERRUPT placement/address (also review related attach)\n\tCPENABLE\tINTERRUPT\tINTSET\tINTCLEAR\tINTENABLE\tsr229\tPS\tVECBASE\tEXCCAUSE\tDEBUGCAUSE\tCCOUNT\tPRID\tICOUNT\tICOUNTLEVEL\tEXCVADDR\tsr239\n\tCCOMPARE0\tCCOMPARE1\tCCOMPARE2\tsr243\tMISC0\tMISC1\tMISC2\tMISC3\tsr248\tsr249\tsr250\tsr251\tsr252\tsr253\tsr254\tsr255\n];\n\ndefine register offset=0x2040 size=8 [ ACC ];\n\n@define EPC_BASE\t\"0x22c0\" #address of EPCn = $(EPC_BASE) + (n * 4)\n@define EPS_BASE\t\"0x2300\" #address of EPSn = $(EPS_BASE) + (n * 4)\n\n@define PS_INTLEVEL \"PS[0,4]\"\n@define PS_EXCM\t\t\"PS[4,1]\"\n@define PS_UM\t\t\"PS[5,1]\"\n@define\tPS_RING\t\t\"PS[6,2]\"\n@define PS_OWB\t\t\"PS[8,4]\"\n@define PS_CALLINC\t\"PS[12,2]\"\n@define\tPS_WOE\t\t\"PS[14,1]\"\n\n\ndefine register offset=0xf000 size=4 contextreg;\ndefine context contextreg\n\tloopMode=(0,0)\n\tloopEnd=(1,1) noflow\n\t\n\t#transient bits\n\tphase=(31,31)\n;\n\n@if ENDIAN == \"big\"\n\n# little-endian -> big-endian 24-bit conversion chart\n#|00|01|02|03|04|05|06|07|08|09|10|11|12|13|14|15|16|17|18|19|20|21|22|23|\n#|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|\n\n# Regular 24-bit instruction.\ndefine token insn(24)\n # Named opcode/register fields.\n op2 = (0,3)\n op1 = (4,7)\n ar = (8,11)\n fr = (8,11)\n br = (8,11)\n as = (12,15)\n fs = (12,15)\n bs = (12,15)\n sr = (8,15)\n at = (16,19)\n ft = (16,19)\n bt = (16,19)\n op0 = (20,23)\n\n # Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the\n # least and most significant bit of the immediate in the instruction word, and N the length\n # (i.e. M-L+1).\n u3_21_23 = (1,3)\n u4_20_23 = (0,3)\n s8_16_23 = (0,7) signed\n u8_16_23 = (0,7)\n u12_12_23 = (0,11)\n s12_12_23 = (0,11) signed\n u16_8_23 = (0,15)\n s8_6_23 = (0,17) signed\n u1_20 = (0,0)\n u2_18_19 = (4,5)\n u3_17_19 = (5,7)\n u2_16_17 = (6,7)\n u1_16 = (4,4)\n u1_15_15 = (11,11)\n u2_14_15 = (10,11)\n u3_13_15 = (9,11)\n u4_12_15 = (8,11)\n m0m1_14_14 = (10,10)\n u2_12_13 = (8,9)\n mw_12_13 = (8,9)\n u1_12 = (8,8)\n u4_8_11 = (12,15)\n u8_4_11 = (12,19)\n s4_8_11 = (12,15) signed\n u1_7_7 = (19,19)\n u2_6_7 = (16,17)\n u3_5_7 = (17,19)\n u4_4_7 = (16,19)\n s4_4_7 = (16,19)\n m2m3_6_6 = (18,18)\n u_4_23 = (0,19)\n t2_4_5 = (16,17)\n u2_4_5 = (18,19)\n u1_4 = (16,16)\n;\n\n# little-endian -> big-endian 16-bit conversion chart\n#|00|01|02|03|04|05|06|07|08|09|10|11|12|13|14|15|\n#|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|\n\n# Narrow 16-bit instructions; fields are always prefixed with n_.\ndefine token narrowinsn(16)\n n_ar = (0,3)\n n_as = (4,7)\n n_at = (8,11)\n n_op0 = (12,15)\n\n n_u4_12_15 = (0,3)\n n_s4_12_15 = (0,3) signed\n n_u4_8_11 = (4,7)\n n_u1_7 = (11,11)\n n_u2_6_7 = (10,11)\n n_u4_4_7 = (8,11)\n n_s3_4_6 = (8,10)\n n_u2_4_5 = (8,9)\n;\n\n@else\n# Regular 24-bit instruction.\ndefine token insn(24)\n # Named opcode/register fields.\n op2 = (20,23)\n ar = (12,15)\n fr = (12,15)\n br = (12,15)\n as = (8,11)\n fs = (8,11)\n bs = (8,11)\n sr = (8,15)\n at = (4,7)\n ft = (4,7)\n bt = (4,7)\n op1 = (16,19)\n op0 = (0,3)\n\n # Signed and unsigned immediates. Named [us]N_L_M, where u and s denote signedness, L and M the\n # least and most significant bit of the immediate in the instruction word, and N the length\n # (i.e. M-L+1).\n u3_21_23 = (21,23)\n u4_20_23 = (20,23)\n s8_16_23 = (16,23) signed\n u8_16_23 = (16,23)\n u12_12_23 = (12,23)\n s12_12_23 = (12,23) signed\n u16_8_23 = (8,23)\n s8_6_23 = (6,23) signed\n u1_20 = (20,20)\n u2_18_19 = (18,19)\n u3_17_19 = (17,19)\n u2_16_17 = (16,17)\n u1_16 = (16,16)\n u1_15_15 = (15,15)\n u2_14_15 = (14,15)\n u3_13_15 = (13,15)\n u4_12_15 = (12,15)\n m0m1_14_14 = (14,14)\n u2_12_13 = (12,13)\n mw_12_13 = (12,13)\n u1_12 = (12,12)\n u4_8_11 = (8,11)\n u8_4_11 = (4,11)\n s4_8_11 = (8,11) signed\n u1_7_7 = (7,7)\n u2_6_7 = (6,7)\n u3_5_7 = (5,7)\n u4_4_7 = (4,7)\n s4_4_7 = (4,7)\n m2m3_6_6 = (6,6)\n u_4_23 = (4,23)\n t2_4_5 = (4,5)\n u2_4_5 = (4,5)\n u1_4 = (4,4)\n;\n\n# Narrow 16-bit instructions; fields are always prefixed with n_.\ndefine token narrowinsn(16)\n n_ar = (12,15)\n n_as = (8,11)\n n_at = (4,7)\n n_op0 = (0, 3)\n\n n_u4_12_15 = (12,15)\n n_s4_12_15 = (12,15) signed\n n_u4_8_11 = (8,11)\n n_u1_7 = (7,7)\n n_u2_6_7 = (6,7)\n n_u4_4_7 = (4,7)\n n_s3_4_6 = (4,6)\n n_u2_4_5 = (4,5)\n;\n\n@endif\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc", "content": "\n\n# ABS - Absolute Value (RRR), pg. 246.\n:abs ar, at is op2 = 0b0110 & op1 = 0 & ar & as = 0b0001 & at & op0 = 0 {\n\tar = at;\n\tif (ar s> 0)\n\t goto inst_next;\n\tar = -ar;\n}\n\n# ABS.S - Absolute Single Value (RRR), pg. 247.\n:abs.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0b0001 & op0 = 0b0000 {\n\tfr = abs(fs);\n}\n\n# ADD - Add (RRR), pg. 248.\n:add ar, as, at is op2 = 0b1000 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = as + at;\n}\n\n# ADD.N - Narrow Add (RRRN), pg. 249.\n:add.n n_ar, n_as, n_at is n_ar & n_as & n_at & n_op0 = 0b1010 {\n\tn_ar = n_as + n_at;\n}\n\n# ADD.S - Add Single (RRR), pg. 250.\n:add.s fr, fs, ft is op2 = 0 & op1 = 0b1010 & fr & fs & ft & op0 = 0 {\n\tfr = fs f+ ft;\n}\n\n# ADDI - Add Immediate (RRI8), pg. 251.\n:addi at, as, s8_16_23 is s8_16_23 & ar = 0b1100 & as & at & op0 = 0b0010 {\n\tat = as + s8_16_23;\n}\n\n# ADDI.N - Narrow Add Immediate (RRRN), pg. 252.\n:addi.n n_ar, n_as, n_s4_4_7_nozero is n_ar & n_as & n_s4_4_7_nozero & n_op0 = 0b1011 {\n\tn_ar = n_as + n_s4_4_7_nozero;\n}\n\n# ADDMI - Add Immediate with Shift by 8, pg. 253.\n:addmi at, as, s16_16_23_sb8 is s16_16_23_sb8 & ar = 0b1101 & as & at & op0 = 0b0010 {\n\tat = as + s16_16_23_sb8;\n}\n\n# ADDX2 - Add with Shift by 1, pg. 254.\n:addx2 ar, as, at is op2 = 0b1001 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = (as << 1) + at;\n}\n\n# ADDX4 - Add with Shift by 2, pg. 255.\n:addx4 ar, as, at is op2 = 0b1010 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = (as << 2) + at;\n}\n\n# ADDX8 - Add with Shift by 4, pg. 256.\n:addx8 ar, as, at is op2 = 0b1011 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = (as << 3) + at;\n}\n\n# ALL4 - All 4 Booleans True, pg. 257.\n:all4 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1001 & bs & bt & op0 = 0 {\n\tlocal b = *[register]:1 &:4 bs+1;\n\tlocal c = *[register]:1 &:4 bs+2;\n\tlocal d = *[register]:1 &:4 bs+3;\n\tbt = bs && b && c && d;\n}\n\n# ALL8 - All 8 Booleans True, pg. 258.\n:all8 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1011 & bs & bt & op0 = 0 {\n\tlocal b = *[register]:1 &:4 bs+1;\n\tlocal c = *[register]:1 &:4 bs+2;\n\tlocal d = *[register]:1 &:4 bs+3;\n\tlocal e = *[register]:1 &:4 bs+4;\n\tlocal f = *[register]:1 &:4 bs+5;\n\tlocal g = *[register]:1 &:4 bs+6;\n\tlocal h = *[register]:1 &:4 bs+7;\n\tbt = bs && b && c && d && e && f && g && h;\n}\n\n# AND - Bitwise Logical And, pg. 259.\n:and ar, as, at is op2 = 0b0001 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = as & at;\n}\n\n# ANDB - Boolean And, pg. 260.\n:andb br, bs, bt is op2 = 0 & op1 = 0b0010 & br & bs & bt & op0 = 0 {\n\tbr = bs && bt;\n}\n\n# ANDBC - Boolean And with Complement, pg. 261.\n:andbc br, bs, bt is op2 = 0b0001 & op1 = 0b0010 & br & bs & bt & op0 = 0 {\n\tbr = bs && !bt;\n}\n\n# ANY4 - Any 4 Booleans True, pg. 262.\n:any4 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1000 & bs & bt & op0 = 0 {\n\tlocal b = *[register]:1 &:4 bs+1;\n\tlocal c = *[register]:1 &:4 bs+2;\n\tlocal d = *[register]:1 &:4 bs+3;\n\tbt = bs || b || c || d;\n}\n\n# ANY8 - Any 8 Booleans True, pg. 263.\n:any8 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1010 & bs & bt & op0 = 0 {\n\tlocal b = *[register]:1 &:4 bs+1;\n\tlocal c = *[register]:1 &:4 bs+2;\n\tlocal d = *[register]:1 &:4 bs+3;\n\tlocal e = *[register]:1 &:4 bs+4;\n\tlocal f = *[register]:1 &:4 bs+5;\n\tlocal g = *[register]:1 &:4 bs+6;\n\tlocal h = *[register]:1 &:4 bs+7;\n\tbt = bs || b || c || d || e || f || g || h;\n}\n\n# BALL - Branch if All Bits Set, pg. 264.\n:ball srel_16_23, as, at is srel_16_23 & ar = 0b0100 & as & at & op0 = 0b0111 {\n\tlocal test:4 = ~as & at;\n\tif (test == 0)\tgoto srel_16_23;\n}\n\n# BANY - Branch if Any Bit Set, pg. 265.\n:bany srel_16_23, as, at, is srel_16_23 & ar = 0b1000 & as & at & op0 = 0b0111 {\n\tlocal test:4 = as & at;\n\tif (test != 0)\tgoto srel_16_23;\n}\n\nmacro extract_bit(bit, result) {\n@if ENDIAN == \"big\"\n\tresult = 0x80000000 >> bit;\n@else\n\tresult = 0x1 << bit;\n@endif\n}\n\n# BBC - Branch if Bit Clear, pg. 266.\n:bbc as, at, srel_16_23 is srel_16_23 & ar = 0b0101 & as & at & op0 = 0b0111 {\n\tlocal bval:4 = 0;\n\textract_bit(at[0,5], bval);\n\tbval = as & bval;\n\tif (bval == 0)\n\t\tgoto srel_16_23;\n}\n\n# BBCI - Branch if Bit Clear immediate, pg. 267\n:bbci as, u5_4_7_12, srel_16_23 is srel_16_23 & u3_13_15 = 0b011 & as & u5_4_7_12 & op0 = 0b0111 {\n\tlocal bval;\n\textract_bit(u5_4_7_12, bval);\n\tbval = as & bval;\n\tif (bval == 0)\n\t\tgoto srel_16_23;\n}\n\n# BBS - Branch if Bit Set, pg. 269.\n:bbs as, at, srel_16_23 is srel_16_23 & ar = 0b1101 & as & at & op0 = 0b0111 {\n\tlocal bval;\n\textract_bit(at[0,5], bval);\n\tbval = as & bval;\n\tif (bval != 0)\n\t\tgoto srel_16_23;\n}\n\n# BBSI - Branch if Bit Set immediate, pg. 270.\n:bbsi as, u5_4_7_12, srel_16_23 is srel_16_23 & u3_13_15 = 0b111 & as & u5_4_7_12 & op0 = 0b0111 {\n\tlocal bval;\n\textract_bit(u5_4_7_12, bval);\n\tbval = as & bval;\n\tif (bval != 0)\n\t\tgoto srel_16_23;\n}\n\n# BEQ - Branch if Equal, pg. 272.\n:beq as, at, srel_16_23 is srel_16_23 & ar = 0b0001 & as & at & op0 = 0b0111 {\n if (as == at)\n goto srel_16_23;\n}\n\n# BEQI - Branch if Equal Immediate, pg. 273.\n:beqi as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0 & u2_4_5 = 0b10 & op0 = 0b0110 {\n if (as == r_b4const)\n goto srel_16_23;\n}\n\n# BEQZ - Branch if Equal Zero, pg. 274.\n:beqz as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0 & u2_4_5 = 0b01 & op0 = 0b0110 {\n if (as == 0)\n goto srel_12_23;\n}\n\n# BEQZ.N - Narrow Branch if Equal Zero, pg. 275.\n:beqz.n n_as, urel_12_15_4_5 is urel_12_15_4_5 & n_as & n_u2_6_7 = 0b10 & n_op0 = 0b1100 {\n if (n_as == 0)\n goto urel_12_15_4_5;\n}\n\n# BF - Branch if False, pg. 276.\n:bf bs, srel_16_23 is srel_16_23 & ar = 0 & bs & at = 0b0111 & op0 = 0b0110 {\n if (!bs)\n goto srel_16_23;\n}\n\n# BGE - Branch if Greater Than or Equal, pg. 277.\n:bge as, at, srel_16_23 is srel_16_23 & ar = 0b1010 & as & at & op0 = 0b0111 {\n if (as s>= at)\n goto srel_16_23;\n}\n\n# BGEI - Branch if Greater Than or Equal Immediate, pg. 278.\n:bgei as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b11 & u2_4_5 = 0b10 & op0 = 0b0110 {\n if (as s>= r_b4const)\n goto srel_16_23;\n}\n\n# BGEU - Branch if Greater Than or Equal Unsigned, pg. 279.\n:bgeu as, at, srel_16_23 is srel_16_23 & ar = 0b1011 & as & at & op0 = 0b0111 {\n if (as >= at)\n goto srel_16_23;\n}\n\n# BGEUI - Branch if Greater Than or Equal Unsigned Immediate, pg. 280.\n:bgeui as, r_b4constu, srel_16_23 is srel_16_23 & r_b4constu & as & u2_6_7 = 0b11 & u2_4_5 = 0b11 & op0 = 0b0110 {\n if (as >= r_b4constu)\n goto srel_16_23;\n}\n\n# BGEZ - Branch if Greater Than or Equal Zero, pg. 281.\n:bgez as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b11 & u2_4_5 = 0b01 & op0 = 0b0110 {\n if (as s>= 0)\n goto srel_12_23;\n}\n\n# BLT - Branch if Less Than, pg. 282.\n:blt as, at, srel_16_23 is srel_16_23 & ar = 0b0010 & as & at & op0 = 0b0111 {\n if (as s< at)\n goto srel_16_23;\n}\n\n# BLTI - Branch if Less Than Immediate, pg. 283.\n:blti as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0b0110 {\n if (as s< r_b4const)\n goto srel_16_23;\n}\n\n# BLTU - Branch if Less Than Unsigned, pg. 284.\n:bltu as, at, srel_16_23 is srel_16_23 & ar = 0b0011 & as & at & op0 = 0b0111 {\n if (as < at)\n goto srel_16_23;\n}\n\n# BLTUI - Branch if Less Than Unsigned Immediate, pg. 285.\n:bltui as, r_b4constu, srel_16_23 is srel_16_23 & r_b4constu & as & u2_6_7 = 0b10 & u2_4_5 = 0b11 & op0 = 0b0110 {\n if (as < r_b4constu)\n goto srel_16_23;\n}\n\n# BLTZ - Branch if Less Than Zero, pg. 286.\n:bltz as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b10 & u2_4_5 = 0b01 & op0 = 0b0110 {\n if (as s< 0)\n goto srel_12_23;\n}\n\n# BNALL - Branch if Not-All Bits Set, pg. 287.\n:bnall srel_16_23, as, at is srel_16_23 & ar = 0b1100 & as & at & op0 = 0b0111 {\n if ((~as & at) != 0)\n goto srel_16_23;\n}\n\n# BNE - Branch if Not Equal, pg. 288.\n:bne as, at, srel_16_23 is srel_16_23 & ar = 0b1001 & as & at & op0 = 0b0111 {\n if (as != at)\n goto srel_16_23;\n}\n\n# BNEI - Branch if Not EquaL Immediate, pg. 289.\n:bnei as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b01 & u2_4_5 = 0b10 & op0 = 0b0110 {\n if (as != r_b4const)\n goto srel_16_23;\n}\n\n# BNEZ - Branch if Not Equal Zero, pg. 290.\n:bnez as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b01 & u2_4_5 = 0b01 & op0 = 0b0110 {\n if (as != 0)\n goto srel_12_23;\n}\n\n# BNEZ.N - Narrow Branch if Not Equal Zero, pg. 291.\n:bnez.n n_as, urel_12_15_4_5 is urel_12_15_4_5 & n_as & n_u2_6_7 = 0b11 & n_op0 = 0b1100 {\n if (n_as != 0)\n goto urel_12_15_4_5;\n}\n\n# BNONE - Branch if No Bit Set, pg. 292.\n:bnone srel_16_23, as, at, is srel_16_23 & ar = 0 & as & at & op0 = 0b0111 {\n if ((as & at) == 0)\n goto srel_16_23;\n}\n\n# BREAK - Breakpoint, pg. 293.\n:break u4_8_11, u4_4_7 is op2 = 0 & op1 = 0 & ar = 0b0100 & u4_8_11 & u4_4_7 & op0 = 0 {\n\tbreak_inst:4 = inst_start;\n\tbreakpoint(0x001000:4, break_inst, u4_8_11:1, u4_4_7:1);\n}\n\n# BREAK.N - Narrow Breakpoint, pg. 295.\n:break.n n_u4_8_11 is n_ar = 0b1111 & n_u4_8_11 & n_at = 0b0010 & n_op0 = 0b1101 {\n\tbreak_inst:4 = inst_start;\n\tbreakpoint(0x010000:4, break_inst, n_u4_8_11:1, 0:1);\n}\n\n# BT - Branch if True, pg. 296.\n:bt bs, srel_16_23 is srel_16_23 & ar = 0b0001 & bs & at = 0b0111 & op0 = 0b0110 {\n if (bs)\n goto srel_16_23;\n}\n\n# CALL0 - Non-windowed Call, pg. 297.\n:call0 srel_6_23_sb2 is srel_6_23_sb2 & u2_4_5 = 0 & op0 = 0b0101 {\n\t$(PS_CALLINC) = 0;\n\ta0 = inst_next;\n\tcall srel_6_23_sb2;\n}\n\n# CALL4 - Call PC-relative, Rotate Window by 4, pg. 298.\n:call4 srel_6_23_sb2 is srel_6_23_sb2 & Ret4 & u2_4_5 = 0b01 & op0 = 0b0101 {\n\t$(PS_CALLINC) = 1;\n\ta4 = Ret4;\n\tswap4();\n\tcall srel_6_23_sb2;\n\trestore4();\n}\n\n# CALL8 - Call PC-relative, Rotate Window by 8, pg. 300.\n:call8 srel_6_23_sb2 is srel_6_23_sb2 & Ret8 & u2_4_5 = 0b10 & op0 = 0b0101 {\n\t$(PS_CALLINC) = 2;\n\ta8 = Ret8;\n\tswap8();\n\tcall srel_6_23_sb2;\n\trestore8();\n}\n\n# CALL12 - Call PC-relative, Rotate Window by 12, pg. 302.\n:call12 srel_6_23_sb2 is srel_6_23_sb2 & Ret12 & u2_4_5 = 0b11 & op0 = 0b0101 {\n\t$(PS_CALLINC) = 3;\n\ta12 = Ret12;\n\tswap12();\n\tcall srel_6_23_sb2;\n\trestore12();\n}\n\n# CALLX0 - Non-windowed Call Register, pg. 304.\n:callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6_7 = 0b11 & u2_4_5 = 0 & op0 = 0 {\n\t$(PS_CALLINC) = 0;\n\tlocal dst = as;\n\ta0 = inst_next;\n\tcall [dst];\n}\n\n# CALLX4 - Call Register, Rotate Window by 4, pg. 305.\n:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret4 & u2_6_7 = 0b11 & u2_4_5 = 0b01 & op0 = 0 {\n\t$(PS_CALLINC) = 1;\n\tdest:4 = as;\n\ta4 = Ret4;\n\tswap4();\n\tcall [dest];\n\trestore4();\n}\n\n# CALLX8 - Call Register, Rotate Window by 8, pg. 307.\n:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret8 & u2_6_7 = 0b11 & u2_4_5 = 0b10 & op0 = 0 {\n\t$(PS_CALLINC) = 2;\n\tdest:4 = as;\n\ta8 = Ret8;\n\tswap8();\n\tcall [dest];\n\trestore8();\n}\n\n# CALLX12 - Call Register, Rotate Window by 12, pg. 308.\n:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret12 & u2_6_7 = 0b11 & u2_4_5 = 0b11 & op0 = 0 {\n\t$(PS_CALLINC) = 3;\n\tdest:4 = as;\n\ta12 = Ret12;\n\tswap12();\n\tcall [dest];\n\trestore12();\n}\n\n# CEIL.S - Ceiling Single to Fixed, pg. 311.\n:ceil.s ar, fs, u4_4_7 is op2 = 0b1011 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 {\n\tlocal scale:4 = 1 << u4_4_7;\n\tar = ceil(fs f* int2float(scale));\n}\n\n# CLAMPS - Signed Clamp, pg. 312.\n:clamps ar, as, u5_4_7_plus7 is op2 = 0b0011 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 {\n\t# ar min(max(as, -2^{u5_4_7_plus7}), 2^{u5_4_7_plus7}-1)\n\tlocal x:4 = as;\n\tlocal clamp:4 = 1 << u5_4_7_plus7;\n\tlocal mt:1 = (x s> (-clamp));\n\tlocal max:4 = (zext(mt) * x) + (zext(!mt) * (-clamp));\n\tmt = (x s< (clamp-1));\n\tar = (zext(mt) * max) + (zext(!mt) * (clamp-1));\n}\n\n# DHI - Data Cache Hit Invalidate, pg. 313.\n:dhi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0110 & op0 = 0b0010 {\n\tdhi(as + u10_16_23_sb2);\n}\n\n# DHU - Data Cache Hit Unlock, pg. 315.\n:dhu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0010 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 {\n\tdhu(as + u8_20_23_sb4);\n}\n\n# DHWB - Data Cache Hit Writeback, pg. 317.\n:dhwb as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0100 & op0 = 0b0010 {\n\tdhwb(as + u10_16_23_sb2);\n}\n\n# DHWBI - Data Cache Hit Writeback Invalidate, pg. 319.\n:dhwbi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0101 & op0 = 0b0010 {\n\tdhwbi(as + u10_16_23_sb2);\n}\n\n# DII - Data Cache Index Invalidate, pg. 321.\n:dii as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0111 & op0 = 0b0010 {\n\tdii(as + u10_16_23_sb2);\n}\n\n# DIU - Data Cache Index Unlock, pg. 323.\n:diu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0011 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 {\n\tdiu(as + u8_20_23_sb4);\n}\n\n# DIWB - Data Cache Index Write Back, pg. 325.\n:diwb as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0100 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 {\n\tdiwb(as + u8_20_23_sb4);\n}\n\n# DIWBI - Data Cache Index Write Back Invalidate, pg. 327.\n:diwbi as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0101 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 {\n\tdiwbi(as + u8_20_23_sb4);\n}\n\n# DPFL - Data Cache Prefetch and Lock, pg. 329.\n:dpfl as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 {\n\tdpfl(as + u8_20_23_sb4);\n}\n\n# DPFR - Data Cache Prefetch for Read, pg. 331.\n:dpfr as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0 & op0 = 0b0010 {\n dpfr(as + u10_16_23_sb2);\n}\n\n# DPFRO - Data Cache Prefetch for Read Once, pg. 333.\n:dpfro as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0010 & op0 = 0b0010 {\n dpfro(as + u10_16_23_sb2);\n}\n\n# DPFW - Data Cache Prefetch for Write, pg. 335.\n:dpfw as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0001 & op0 = 0b0010 {\n dpfw(as + u10_16_23_sb2);\n}\n\n# DPFWO - Data Cache Prefetch for Write Once, pg. 337.\n:dpfwo as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0011 & op0 = 0b0010 {\n dpfwo(as + u10_16_23_sb2);\n}\n\n# DSYNC - Load/Store Synchronize, pg. 339.\n:dsync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0011 & op0 = 0 {\n\tdsync();\n}\n\n# ENTRY - Subroutine Entry, pg. 340.\n:entry as, u15_12_23_sb3 is u15_12_23_sb3 & as & u2_6_7 = 0b00 & u2_4_5 = 0b11 & op0 = 0b0110 {\n\tlocal callSP = a1;\n\tcallinc:1 = $(PS_CALLINC);\n\trotateRegWindow(callinc);\n\tas = callSP - zext(u15_12_23_sb3);\n}\n\n# ESYNC - Execute Synchronize, pg. 342.\n:esync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0010 & op0 = 0 {\n\tesync();\n}\n\n# EXCW - Exception Wait, pg. 343.\n:excw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1000 & op0 = 0 {\n\texcw();\n}\n\n# EXTUI - Extract Unsigned Immediate, pg. 344.\n:extui ar, at, u5_8_11_16, u5_20_23_plus1 is u5_20_23_plus1 & u3_17_19 = 0b010 & u5_8_11_16 & ar & at & op0 = 0 {\n local shifted:4 = at >> u5_8_11_16;\n local mask:4 = (1:4 << (u5_20_23_plus1))-1;\n ar = shifted & mask;\n}\n\n# EXTW - External Wait, pg. 345.\n:extw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1101 & op0 = 0 {\n\textw();\n}\n\n# FLOAT.S - Convert Fixed to Single, pg. 346.\n:float.s fr, as, u4_4_7 is op2 = 0b1100 & op1 = 0b1010 & fr & as & u4_4_7 & op0 = 0 {\n\tlocal scale:4 = 1 << u4_4_7;\n\tfr = int2float(as) f/ int2float(scale);\n}\n\n# FLOOR.S - Floor Single to Fixed, pg. 347.\n:floor.s ar, fs, u4_4_7 is op2 = 0b1010 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 {\n\tlocal scale:4 = 1 << u4_4_7;\n\tar = floor(fs f* int2float(scale));\n}\n\n# IDTLB - Invalidate Data TLB Entry, pg. 348.\n:idtlb as is op2 = 0b0101 & op1 = 0 & ar = 0b1100 & as & at = 0 & op0 = 0 {\n\tidtlb();\n}\n\n# IHI - Instruction Cache Hit Invalidate, pg. 349.\n:ihi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1110 & op0 = 0b0010 {\n ihi(as + u10_16_23_sb2);\n}\n\n# IHU - Instruction Cache Hit Unlock, pg. 351.\n:ihu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0010 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 {\n\tihu(as + u8_20_23_sb4);\n}\n\n# III - Instruction Cache Index Invalidate, pg. 353.\n:iii as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1111 & op0 = 0b0010 {\n iii(as + u10_16_23_sb2);\n}\n\n# IITLB - Invalidate Instruction TLB Entry, pg. 355.\n:iitlb as is op2 = 0b0101 & op1 = 0 & ar = 0b0100 & as & at = 0 & op0 = 0 {\n\tiitlb(as);\n}\n\n# IIU - Instruction Cache Index Unlock, pg. 356.\n:iiu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0011 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 {\n\tiiu(as + u8_20_23_sb4);\n}\n\n# ILL - Illegal Instruction, pg. 358.\n:ill is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & at = 0 & op0 = 0 {\n\till();\n\tgoto inst_start;\n}\n\n# ILL.N - Narrow Illegal Instruction, pg. 359.\n:ill.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0110 & n_op0 = 0b1101 {\n\till();\n\tgoto inst_start;\n}\n\n# IPF - Instruction Cache Prefetch, pg. 360.\n:ipf as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1100 & op0 = 0b0010 {\n ipf(as + u10_16_23_sb2);\n}\n\n# IPFL - Instruction Cache Prefetch and Lock, pg. 362.\n:ipfl as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 {\n\tipfl(as + u8_20_23_sb4);\n}\n\n# ISYNC - Instruction Fetch Synchronize, pg. 364.\n:isync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0 & op0 = 0 {\n\tisync();\n}\n\n# J - Unconditional Jump, pg. 366.\n:j srel_6_23 is srel_6_23 & u2_4_5 = 0 & op0 = 0b0110 {\n goto srel_6_23;\n}\n\n# J.L is a macro.\n\n# RET (JX A0) - Non-Windowed Return, pg. 478.\n:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0 {\n return [a0];\n}\n\n# The manual suggests that RET is equivalent to JX A0, yet RET has bit 5 unset, JX doesn’t.\n:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b00 & op0 = 0 {\n\treturn [a0];\n}\n\n# JX - Uncoditional Jump Register, pg. 368.\n:jx as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0 {\n goto [as];\n}\n\n# L8UI - Load 8-bit Unsigned, pg. 369.\n:l8ui at, as, u8_16_23 is u8_16_23 & ar = 0 & as & at & op0 = 0b0010 {\n local addr:4 = as + zext(u8_16_23:1);\n at = zext(*:1 addr);\n}\n\n# L16SI - Load 16-bit Signed, pg. 370.\n:l16si at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b1001 & as & at & op0 = 0b0010 {\n local addr:4 = as + u9_16_23_sb1;\n at = sext(*:2 addr);\n}\n\n# L16UI - Load 16-bit Unsigned, pg. 372.\n:l16ui at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b001 & as & at & op0 = 0b0010 {\n local addr:4 = as + u9_16_23_sb1;\n at = zext(*:2 addr);\n}\n\n# L32AI - Load 32-bit Acquire, pg. 374.\n:l32ai at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1011 & as & at & op0 = 0b0010 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\tat = *:4 addr;\n\tacquire(addr);\n}\n\n# L32E - Load 32-bit for Window Exceptions, pg. 376.\n:l32e at, as, s5_12_15_oex is op2 = 0 & op1 = 0b1001 & s5_12_15_oex & as & at & op0 = 0 {\n\tptr:4 = as + sext(s5_12_15_oex);\n\tat = *:4 ptr;\n}\n\n# L32I - Load 32-bit, pg. 378.\n:l32i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0010 & as & at & op0 = 0b0010 {\n local addr:4 = as + u10_16_23_sb2;\n at = *:4 addr;\n}\n\n# L32I.N - Narrow Load 32-bit, pg. 380.\n:l32i.n n_at, n_as, n_u6_12_15_sb2 is n_u6_12_15_sb2 & n_as & n_at & n_op0 = 0b1000 {\n local addr:4 = n_as + n_u6_12_15_sb2;\n n_at = *:4 addr;\n}\n\n# L32R - Load 32-bit PC-relative, pg. 382.\n:l32r at, srel_8_23_oex_sb2 is srel_8_23_oex_sb2 & at & op0 = 0b0001 {\n at = srel_8_23_oex_sb2;\n}\n\n# LDCT - Load Data Cache Tag, pg. 384.\n:ldct at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1000 & as & at & op0 = 0 {\n\tat = ldct(as);\n}\n\n# LICT - Load Instruction Cache Tag, pg. 388.\n:lict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0 & as & at & op0 = 0 {\n\tat = lict(as);\n}\n\n# LICW - Load Instruction Cache Word, pg. 390.\n:licw at, as is op2 = 0b1111 & op1 = 0b0010 & ar = 0 & as & at & op0 = 0 {\n\tat = licw(as);\n}\n\n# LSI - Load Single Immediate, pg. 398.\n:lsi ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0 & as & ft & op0 = 0b0011 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\tft = *:4 addr;\n}\n\n# LSIU - Load Single Immediate with Update, pg. 400.\n:lsiu ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1000 & as & ft & op0 = 0b0011 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\tft = *:4 addr;\n\tas = addr;\n}\n\n# LSX - Load Single Indexed, pg. 402.\n:lsx fr, as, at is op2 = 0 & op1 = 0b1000 & fr & as & at & op0 = 0 {\n\tlocal addr:4 = as+at;\n\tfr = *:4 addr;\n}\n\n# LSXU - Load Single Indexed with Update, pg. 404.\n:lsxu fr, as, at is op2 = 0b0001 & op1 = 0b1000 & fr & as & at & op0 = 0 {\n\tlocal addr:4 = as+at;\n\tfr = *:4 addr;\n\tas = addr;\n}\n\n# MADD.S - Multiply and Add Single, pg. 406.\n:madd.s fr, fs, ft is op2 = 0b0100 & op1 = 0b1010 & fr & fs & ft & op0 = 0 {\n\tfr = fr f+ (fs f* ft);\n}\n\n# MAX - Maximum Value, pg. 407.\n:max ar, as, at is op2 = 0b0101 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\ttest:1 = as s< at;\n\tar = (zext(test) * at) + (zext(!test) * as);\n}\n\n# MAXU - Maximum Value Unsigned, pg. 408.\n:maxu ar, as, at is op2 = 0b0111 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\ttest:1 = as < at;\n\tar = (zext(test) * at) + (zext(!test) * as);\n}\n\n# MEMW - Memory Wait, pg. 409.\n:memw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1100 & op0 = 0 {\n\tmemw();\n}\n\n# MIN - Minimum Value, pg. 410.\n:min ar, as, at is op2 = 0b0100 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\ttest:1 = as s< at;\n\tar = (zext(test) * as) + (zext(!test) * at);\n}\n\n# MINU - Minimum Value Unsigned, pg. 411.\n:minu ar, as, at is op2 = 0b0110 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\ttest:1 = as < at;\n\tar = (zext(test) * as) + (zext(!test) * at);\n}\n\n# MOV.N - Narrow Move, pg. 413.\n:mov.n n_at, n_as is n_ar = 0 & n_as & n_at & n_op0 = 0b1101 {\n\tn_at = n_as;\n}\n\n# MOV.S - Move Single, pg. 414.\n:mov.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0 & op0 = 0 {\n\tfr = fs;\n}\n\n# MOVEQZ - Move if Equal to Zero, pg. 415.\n:moveqz ar, as, at is op2 = 0b1000 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\tif (at != 0) goto ;\n\tar = as;\n\t\n}\n\n# MOVEQZ.S - Move Single if Equal to Zero, pg. 416.\n:moveqz.s fr, fs, at is op2 = 0b1000 & op1 = 0b1011 & fr & fs & at & op0 = 0 {\n\tif (at != 0) goto ;\n\tfr = fs;\n\t\n}\n\n# MOVF - Move if False, pg. 417.\n:movf ar, as, bt is op2 = 0b1100 & op1 = 0b0011 & ar & as & bt & op0 = 0 {\n\tif (bt) goto ;\n\tar = as;\n\t\n}\n\n# MOVF.S - Move Single if False, pg. 418.\n:movf.s fr, fs, bt is op2 = 0b1100 & op1 = 0b1011 & fr & fs & bt & op0 = 0 {\n\tif (bt)goto ;\n\tfr = fs;\n\t\n}\n\n# MOVGEZ - Move if Greater Than or Equal to Zero, pg. 419.\n:movgez ar, as, at is op2 = 0b1011 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\tif (at s< 0) goto ;\n\tar = as;\n\t\n}\n\n# MOVGEZ.S - Move Single if Greater Than or Equal to Zero, pg. 420.\n:movgez.s fr, fs, at is op2 = 0b1011 & op1 = 0b1011 & fr & fs & at & op0 = 0 {\n\tif (at s< 0) goto ;\n\tfr = fs;\n\t\n}\n\n# MOVI - Move Immediate, pg. 421.\n:movi at, s16_16_23_8_11 is s16_16_23_8_11 & ar = 0b1010 & at & op0 = 0b0010 {\n local val:4 = sext(s16_16_23_8_11);\n at = val;\n}\n\n# MOVI.N - Narrow Move Immediate, pg. 422.\n:movi.n n_as, n_s8_12_15_4_6_asymm is n_s8_12_15_4_6_asymm & n_as & n_u1_7 = 0 & n_op0 = 0b1100 {\n local val:4 = sext(n_s8_12_15_4_6_asymm);\n n_as = val;\n}\n\n# MOVLTZ - Move if Less Than Zero, pg. 423.\n:movltz ar, as, at is op2 = 0b1010 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\tif (at s>= 0) goto ;\n\tar = as;\n\t\n}\n\n# MOVLTZ.S - Move Single if Less Than Zero, pg. 424.\n:movltz.s fr, fs, at is op2 = 0b1010 & op1 = 0b1011 & fr & fs & at & op0 = 0 {\n\tif (at s>= 0) goto ;\n\tfr = fs;\n\t\n}\n\n# MOVNEZ - Move if Not Equal to Zero, pg. 425.\n:movnez ar, as, at is op2 = 0b1001 & op1 = 0b0011 & ar & as & at & op0 = 0 {\n\tif (at == 0) goto ;\n\tar = as;\n\t\n}\n\n# MOVNEZ.S - Move Single if Not Equal to Zero, pg. 426.\n:movnez.s fr, fs, at is op2 = 0b1001 & op1 = 0b1011 & fr & fs & at & op0 = 0 {\n\tif (at == 0) goto ;\n\tfr = fs;\n\t\n}\n\n# MOVSP - Move to Stack Pointer, pg. 427.\n:movsp at, as is op2 = 0 & op1 = 0 & ar = 0b0001 & as & at & op0 = 0 {\n\tat = (zext(WindowStart == 0) * at) + (zext(WindowStart != 0) * as);\n}\n\n# MOVT - Move if True, pg. 428.\n:movt ar, as, bt is op2 = 0b1101 & op1 = 0b0011 & ar & as & bt & op0 = 0 {\n\tif (!bt) goto ;\n\tar = as;\n\t\n}\n\n# MOVT.S - Move Single if True, pg. 429.\n:movt.s fr, fs, bt is op2 = 0b1101 & op1 = 0b1011 & fr & fs & bt & op0 = 0 {\n\tif (!bt) goto ;\n\tfr = fs;\n\t\n}\n\n# MSUB.S - Multiply and Subtract Single, pg. 430.\n:msub.s fr, fs, ft is op2 = 0b0101 & op1 = 0b1010 & fr & fs & ft & op0 = 0 {\n\tfr = fr f- (fs f* ft);\n}\n\n# MUL.S - Multiply Single, pg. 435.\n:mul.s fr, fs, ft is op2 = 0b0010 & op1 = 0b1010 & fr & fs & ft & op0 = 0 {\n\tfr = fs f* ft;\n}\n\n# MUL16S - Multiply 16-bit Signed, pg. 436.\n:mul16s ar, as, at is op2 = 0b1101 & op1 = 0b0001 & ar & as & at & op0 = 0 {\n\tar = sext(as:2) * sext(at:2);\n}\n\n# MUL16U - Multiply 16-bit Unsigned, pg. 437.\n:mul16u ar, as, at is op2 = 0b1100 & op1 = 0b0001 & ar & as & at & op0 = 0 {\n\tar = zext(as:2) * zext(at:2);\n}\n\n# MULL - Multiply Low, pg. 450.\n:mull ar, as, at is op2 = 0b1000 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tar = as * at;\n}\n\n# MULSH - Multiply Signed High, pg. 455.\n:mulsh ar, as, at is op2 = 0b1011 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tlocal s64:8 = sext(as);\n\tlocal t64:8 = sext(at);\n\tlocal p:8 = (s64 * t64);\n\tar = p(4);\n}\n\n# MULUH - Multiply Unsigned High, pg. 456.\n:muluh ar, as, at is op2 = 0b1010 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tlocal s64:8 = zext(as);\n\tlocal t64:8 = zext(at);\n\tlocal p:8 = (s64 * t64);\n\tar = p(4);\n}\n\n# NEG - Negate, pg. 457.\n:neg ar, at is op2 = 0b0110 & op1 = 0 & ar & as = 0 & at & op0 = 0 {\n\tar = -at;\n}\n\n# NEG.S - Negate Single, pg. 458.\n:neg.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0b0110 & op0 = 0 {\n\tfr = 0 f- fs;\n}\n\n# NOP - No Operation, pg. 459.\n:nop is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1111 & op0 = 0 { }\n\n# NOP.N - Narrow No Operation, pg. 460.\n:nop.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0011 & n_op0 = 0b1101 { }\n\n# NSA - Normalization Shift Amount, pg. 461.\n:nsa at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1110 & as & at & op0 = 0 {\n at = lzcount(~as);\n}\n\n# NSAU - Normalization Shift Amount Unsigned, pg. 462. (Count leading zeros)\n:nsau at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 {\n at = lzcount(as);\n}\n\n# OEQ.S - Compare Single Equal, pg. 463.\n:oeq.s br, fs, ft is op2 = 0b0010 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = !nan(fs) && !nan(ft) && fs f== ft;\n}\n\n# OLE.S - Compare Single Ordered and Less Than or Equal, pg. 464\n:ole.s br, fs, ft is op2 = 0b0110 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = !nan(fs) && !nan(ft) && fs f<= ft;\n}\n\n# OLT.S - Compare Single Ordered and Less Than, pg. 465.\n:olt.s br, fs, ft is op2 = 0b0100 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = !nan(fs) && !nan(ft) && fs f< ft;\n}\n\n# MOV - Move, pg. 412. Special case of OR as, at, at.\n:mov ar, as is op2 = 0b0010 & op1 = 0 & ar & as & as = at & op0 = 0 {\n\tar = as;\n}\n\n# OR - Bitwise Logical Or, pg. 466.\n:or ar, as, at is op2 = 0b0010 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = as | at;\n}\n\n# ORB - Boolean Or, pg. 467.\n:orb br, bs, bt is op2 = 0b0010 & op1 = 0b0010 & br & bs & bt & op0 = 0 {\n\tbr = bs || bt;\n}\n\n# ORBC - Boolean Or with Complement, pg. 468.\n:orbc br, bs, bt is op2 = 0b0011 & op1 = 0b0010 & br & bs & bt & op0 = 0 {\n\tbr = bs || !bt;\n}\n\n# PDTLB - Probe Data TLB, pg. 469.\n:pdtlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1101 & as & at & op0 = 0 {\n\tat = pdtlb(as);\n}\n\n# PITLB - Probe Instruction TLB, pg. 470.\n:pitlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0101 & as & at & op0 = 0 {\n\tat = pitlb(as);\n}\n\n# QUOS - Quotient Signed, pg. 471.\n:quos ar, as, at is op2 = 0b1101 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tar = as s/ at;\n}\n\n# QUOU - Quotient Unsigned, pg. 472.\n:quou ar, as, at is op2 = 0b1100 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tar = as / at;\n}\n\n# RDTLB0 - Read Data TLB Virtual Entry, pg. 473.\n:rdtlb0 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1011 & as & at & op0 = 0 {\n\tat = rdtlb0(as);\n}\n\n# RDTLB1 - Read Data TLB Entry Translation, pg. 474.\n:rdtlb1 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 {\n\tat = rdtlb1(as);\n}\n\n# REMS - Remainder Signed, pg. 475.\n:rems ar, as, at, is op2 = 0b1111 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tar = as s% at;\n}\n\n# REMU - Remainder Unsigned, pg. 476.\n:remu ar, as, at, is op2 = 0b1110 & op1 = 0b0010 & ar & as & at & op0 = 0 {\n\tar = as % at;\n}\n\n# RER - Read External Register, pg. 477.\n:rer as, at is op2 = 0b0100 & op1 = 0 & ar = 0b0110 & as & at & op0 = 0 {\n\tas = rer(at);\n}\n\n# RET.N - Narrow Non-Windowed Return, pg. 479.\n:ret.n is n_ar = 0b1111 & n_as = 0 & n_at = 0 & n_op0 = 0b1101 {\n return [a0];\n}\n\n# RETW - Windowed Return, pg. 480.\n:retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b01 & op0 = 0 {\n\tlocal addr:4 = (a0 & 0x3fffffff) | (inst_start & 0xc0000000);\n\trestoreRegWindow();\n\treturn [addr];\n}\n\n# RETW.N - Narrow Windowed Return, pg. 482.\n:retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 {\n\tlocal addr:4 = (a0 & 0x3fffffff) | (inst_start & 0xc0000000);\n\trestoreRegWindow();\n\treturn [addr];\n}\n\n# RFDD - Return from Debug and Dispatch, pg. 484.\n:rfdd is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1110 & (as = 0b0000 | as = 0b0001) & at = 0b0001 & op0 = 0 {\n local tmp:4 = rfdd();\n return [tmp];\n}\n\n# RFDE _ Return From Double Exception, pg. 485.\n:rfde is op2 = 0 & op1 = 0 & ar = 0b0011 & as =0b0010 & at = 0 & op0 = 0 {\n local tmp:4 = rfde();\n return [tmp];\n}\n\n# RFDO - Return from Debug Operation, pg. 486.\n:rfdo is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1110 & as = 0 & at = 0 & op0 = 0 {\n local tmp:4 = rfdo();\n return [tmp];\n}\n\n# RFE - Return From Exception, pg. 487.\n:rfe is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0 & at = 0 & op0 = 0 {\n local tmp:4 = rfe();\n return [tmp];\n}\n\nrfi_epc: ptr is u4_8_11\t[ ptr = $(EPC_BASE) + (4 * u4_8_11); ] { export *[register]:4 ptr; }\nrfi_eps: ptr is u4_8_11\t[ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[register]:4 ptr; }\n\n# RFI - Return from High-Priority Interrupt, pg. 488.\n:rfi u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0011 & u4_8_11 & at = 0b0001 & op0 = 0 & rfi_epc & rfi_eps {\n\tPS = rfi_eps;\n\treturn [rfi_epc];\n}\n\n# RFME - Return from Memory Error, pg. 489.\n:rfme is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0 & at = 0b0010 & op0 = 0 {\n\tPS = MEPS;\n\tMESR[0,1] = 0;\n\treturn [MEPC];\n}\n\n# RFR - Move FR to AR, pg. 490.\n:rfr ar, fs is op2 = 0b1111 & op1 = 0b1010 & ar & fs & at = 0b0100 & op0 = 0 {\n\tar = fs;\n}\n\n# RFUE - Return from User-Mode Exception, pg. 491.\n:rfue is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0001 & at = 0 & op0 = 0 {\n local tmp:4 = rfue();\n return [tmp];\n}\n\n# RFWO - Return from Window Overflow, pg. 492.\n:rfwo is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0100 & at = 0 & op0 = 0 {\n\t$(PS_EXCM) = 0;\n\trfwo();\n\treturn [EPC1];\n}\n\n# RFWU - Return from Window Underflow, pg. 493.\n:rfwu is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0101 & at = 0 & op0 = 0 {\n\t$(PS_EXCM) = 0;\n\trfwu();\n\treturn [EPC1];\n}\n\n# RITLB0 - Read Instruction TLB Virtual Entry, pg. 494.\n:ritlb0 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0011 & as & at & op0 = 0 {\n\tat = ritlb0(as);\n}\n\n# RITLB1 - Read Instruction TLB Entry Translation, pg. 495.\n:ritlb1 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0111 & as & at & op0 = 0 {\n\tat = ritlb1(as);\n}\n\n# ROTW - Rotate Window, pg. 496.\n:rotw s4_4_7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4_7 & op0 = 0 {\n WindowBase = WindowBase + s4_4_7;\n}\n\n# ROUND.S - Round Single to Fixed, pg. 497.\n:round.s ar, fs, u4_4_7 is op2 = 0b1000 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 {\n\tlocal scale:4 = 1 << u4_4_7;\n\tlocal result = fs f* int2float(scale);\n\tisNan:1 = nan(result);\n\tif (isNan) goto ;\n\tar = round(fs f* scale);\n\tgoto ;\n\t\n\tar = 0x80000000;\n\tif (fs f< 0) goto ;\n\tar = 0x7fffffff;\n\t\n}\n\n# RSIL - Read and Set Interrupt Level, pg. 498.\n:rsil at, u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0110 & u4_8_11 & at & op0 = 0 {\n at = rsil(u4_8_11:1);\n}\n\n# RSR - Read Special Register, pg. 500.\n:rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 {\n\tat = rsr(sr:1);\n}\n\n# RSYNC - Register Read Synchronize, pg. 502.\n:rsync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0001 & op0 = 0 {\n\trsync();\n}\n\n\n# RUR - Read User Register, pg. 503.\n:rur ar, u8_4_11 is op2 = 0b1110 & op1 = 0b0011 & ar & u8_4_11 & op0 = 0 {\n ar = rur(u8_4_11:1);\n}\n# S8I - Store 8-bit, pg. 504.\n:s8i at, as, u8_16_23 is u8_16_23 & ar = 0b0100 & as & at & op0 = 0b0010 {\n local addr:4 = as + zext(u8_16_23:1);\n *:1 addr = at:1;\n}\n\n# S16I - Store 16-bit, pg. 505.\n:s16i at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b0101 & as & at & op0 = 0b0010 {\n local addr:4 = as + u9_16_23_sb1;\n *:2 addr = at:2;\n}\n\n# S32C1I - Store 32-bit Compare Conditional, pg. 506\n:s32c1i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1110 & as & at & op0 = 0b0010 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\told:4 = *:4 addr;\n\tif (old != SCOMPARE1) goto ;\n\t*:4 addr = at;\n\t\n\tat = old;\n}\n\n# S32E - Store 32-bit for Window Exceptions, pg. 508.\n:s32e at, as, s5_12_15_oex is op2 = 0b0100 & op1 = 0b1001 & s5_12_15_oex & as & at & op0 = 0 {\n\tptr:4 = as + sext(s5_12_15_oex);\n\t*:4 ptr = at;\n}\n\n# S32I - Store 32-bit, pg. 510.\n:s32i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0110 & as & at & op0 = 0b0010 {\n local addr:4 = as + u10_16_23_sb2;\n *:4 addr = at;\n}\n\n# S32I.N - Narrow Store 32-bit, pg. 512.\n:s32i.n n_at, n_as, n_u6_12_15_sb2 is n_u6_12_15_sb2 & n_as & n_at & n_op0 = 0b1001 {\n local addr:4 = n_as + n_u6_12_15_sb2;\n *:4 addr = n_at;\n}\n\n# S32RI - Store 32-bit Release, pg. 514.\n:s32ri at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1111 & as & at & op0 = 0b0010 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\trelease(addr);\n\t*:4 addr = at;\n}\n\n# SDCT - Store Data Cache Tag, pg. 516.\n:sdct at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1001 & as & at & op0 = 0 {\n\tsdct(as, at);\n}\n\n# SEXT - Sign Extend, pg. 518.\n:sext ar, as, u5_4_7_plus7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 {\n local shift:4 = 31 - u5_4_7_plus7;\n\tlocal tmp:4 = as << shift;\n\tar = tmp s>> shift;\n}\n:sext ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 0 & op0 = 0 {\n ar = sext(as:1);\n}\n:sext ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 8 & op0 = 0 {\n ar = sext(as:2);\n}\n\n# SICT - Store Instruction Cache Tag, pg. 519.\n:sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 {\n\tsict(as, at);\n}\n\n# SICW - Store Instruction Cache word, pg. 521.\n:sicw at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0011 & as & at & op0 = 0 {\n\tsicw(as, at);\n}\n\n# SIMCALL - Simulator Call, pg. 523.\n:simcall is op2 = 0 & op1 = 0 & ar = 0b0101 & as = 0b0001 & at = 0 & op0 = 0 {\n\tsimcall();\n}\n\n# SLL - Shift Left Logical, pg. 524.\n:sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 {\n\tlocal sa:4 = 32 - SAR;\n\tar = as << sa;\n}\n\n# SLLI - Shift Left Logical Immediate, pg. 525.\n:slli ar, as, u5_4_7_20 is u3_21_23 = 0 & u5_4_7_20 & op1 = 0b0001 & ar & as & op0 = 0 {\n\tar = as << u5_4_7_20;\n}\n\n# SRA - Shift Right Arithmetic, pg. 526.\n:sra ar, at is op2 = 0b1011 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 {\n ar = at s>> SAR;\n}\n\n# SRAI - Shift Right Arithmetic Immediate, pg. 527.\n:srai ar, at, u5_8_11_20 is u3_21_23 = 0b001 & u5_8_11_20 & op1 = 0b0001 & ar & at & op0 = 0 {\n ar = at s>> u5_8_11_20;\n}\n\n# SRC - Shift Right Combined, pg. 528.\n:src ar, as, at is op2 = 0b1000 & op1 = 0b0001 & ar & as & at & op0 = 0 {\n local s64:8 = zext(as);\n local t64:8 = zext(at);\n local combined:8 = (s64 << 32) | t64;\n local shifted:8 = combined >> SAR;\n ar = shifted:4;\n}\n\n# SRL - Shift Right Logical, pg. 529.\n:srl ar, at is op2 = 0b1001 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 {\n ar = at >> SAR;\n}\n\n# SRLI - Shift Right Logical Immediate, pg. 530.\n:srli ar, at, u4_8_11 is op2 = 0b0100 & op1 = 0b0001 & ar & u4_8_11 & at & op0 = 0 {\n ar = at >> u4_8_11;\n}\n\n# SSA8B - Set Shift Amount for BE Byte Shift, pg. 531.\n:ssa8b as is op2 = 0b0100 & op1 = 0 & ar = 0b0011 & as & at = 0 & op0 = 0 {\n local lsa:4 = (as&3)*8;\n SAR = 32 - lsa;\n}\n\n# SSA8L - Set Shift Amount for LE Byte Shift, pg. 532.\n:ssa8l as is op2 = 0b0100 & op1 = 0 & ar = 0b0010 & as & at = 0 & op0 = 0 {\n\tlocal rsa:4 = (as & 3)*8;\n\tSAR = rsa;\n}\n\n# SSAI - Set Shift Amount Immediate, pg. 533.\n:ssai u5_8_11_4 is op2 = 0b0100 & op1 = 0 & ar = 0b0100 & u5_8_11_4 & u3_5_7 = 0 & op0 = 0 {\n\tSAR = u5_8_11_4;\n}\n\n# SSI - Store Single Immediate, pg. 534.\n:ssi ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0100 & as & ft & op0 = 0b0011 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\t*:4 addr = ft;\n}\n\n# SSIU - Store Single Immediate with Update, pg. 536.\n:ssiu ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1100 & as & ft & op0 = 0b0011 {\n\tlocal addr:4 = as + u10_16_23_sb2;\n\t*:4 addr = ft;\n\tas = addr;\n}\n\n# SSL - Set Shift Amount for Left Shift, pg. 538.\n:ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 {\n SAR = 32 - (as & 0x1f);\n}\n\n# SSR - Set Shift Amount for Right Shift, pg. 539.\n:ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 {\n SAR = (as & 0x1f);\n}\n\n# SSX - Store Single Indexed, pg. 540.\n:ssx fr, as, at is op2 = 0b0100 & op1 = 0b1000 & fr & as & at & op0 = 0 {\n\tlocal addr:4 = as+at;\n\t*:4 addr = fr;\n}\n\n# SSXU - Store Single Indexed with Update, pg. 541.\n:ssxu fr, as, at is op2 = 0b0101 & op1 = 0b1000 & fr & as & at & op0 = 0 {\n\tlocal addr:4 = as+at;\n\t*:4 addr = fr;\n\tas = addr;\n}\n\n# SUB - Subtract, pg. 542.\n:sub ar, as, at is op2 = 0b1100 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = as - at;\n}\n\n# SUB.S - Subtract Single, pg. 543.\n:sub.s fr, fs, ft is op2 = 0b0001 & op1 = 0b1010 & fr & fs & ft & op0 = 0 {\n\tfr = fs f- ft;\n}\n\n# SUBX2 - Subtract with Shift by 1, pg. 544.\n:subx2 ar, as, at is op2 = 0b1101 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = (as << 1) - at;\n}\n\n# SUBX4 - Subtract with Shift by 2, pg. 545.\n:subx4 ar, as, at is op2 = 0b1110 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = (as << 2) - at;\n}\n\n# SUBX8 - Subtract with Shift by 3, pg. 546.\n:subx8 ar, as, at is op2 = 0b1111 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = (as << 3) - at;\n}\n\n# SYSCALL - System Call, pg. 547.\n:syscall is op2 = 0 & op1 = 0 & ar = 0b0101 & as = 0 & at = 0 & op0 = 0 {\n\tsyscall();\n}\n\n# TRUNC.S - Truncate Single to Fixed, pg. 548\n:trunc.s ar, fs, u4_4_7 is op2 = 0b1001 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 {\n\tlocal scale:4 = 1 << u4_4_7;\n\tlocal result = fs f* int2float(scale);\n\tisNan:1 = nan(result);\n\tif (isNan) goto ;\n\tar = trunc(fs f* scale);\n\tgoto ;\n\t\n\tar = 0x80000000;\n\tif (fs f< 0) goto ;\n\tar = 0x7fffffff;\n\t\n}\n\n# UEQ.S - Compare Single Unordered or Equal, pg. 549.\n:ueq.s br, fs, ft is op2 = 0b0011 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = nan(fs) || nan(ft) || fs f== ft;\n}\n\n# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550.\n:ufloat.s fr, as, u4_4_7 is op2 = 0b1101 & op1 = 0b1010 & fr & as & u4_4_7 & op0 = 0 {\n\tlocal tmp:8 = zext(as);\n\tlocal scale:4 = 1 << u4_4_7;\n\tfr = int2float(tmp) f/ int2float(scale);\n}\n\n# ULE.S - Compare Single Unordered or Less Than or Equal, pg. 551.\n:ule.s br, fs, ft is op2 = 0b0111 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = nan(fs) || nan(ft) || fs f<= ft;\n}\n\n# ULT.S - Compare Single Unordered or Less Than, pg. 552.\n:ult.s br, fs, ft is op2 = 0b0101 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = nan(fs) || nan(ft) || fs f< ft;\n}\n\n# UN.S - Compare Single Unordered, pg. 554.\n:un.s br, fs, ft is op2 = 0b0001 & op1 = 0b1011 & br & fs & ft & op0 = 0 {\n\tbr = nan(fs) || nan(ft);\n}\n\n# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555.\n:utrunc.s ar, fs, u4_4_7 is op2 = 0b1110 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 {\n local scale:4 = int2float(1:2 << u4_4_7:2);\n local tmp:8 = trunc(fs f* scale);\n local posof = nan(fs) || (tmp >> 16) != 0;\n local negof = tmp s< 0;\n local noof = !posof && !negof;\n ar = zext(posof)*0xffffffff + zext(negof)*0x80000000 + zext(noof)*tmp:4;\n}\n\n# WAITI - Wait Interrupt, pg. 556.\n:waiti u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0111 & u4_8_11 & at = 0 & op0 = 0 {\n waiti(u4_8_11:4);\n}\n\n# WDTLB - Write Data TLB Entry, pg. 557.\n:wdtlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1110 & as & at & op0 = 0 {\n\twdtlb(as, at);\n}\n\n# WER - Write External Register, pg. 558.\n:wer as, at is op2 = 0b0100 & op1 = 0 & ar = 0b0111 & as & at & op0 = 0 {\n\twer(as, at);\n}\n\n# WFR - Move AR to FR, pg. 559.\n:wfr fr, as is op2 = 0b1111 & op1 = 0b1010 & fr & as & at = 0b0101 & op0 = 0 {\n\tfr = as;\n}\n\n# WITLB - Write Instruction TLB Entry, pg. 560.\n:witlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0110 & as & at & op0 = 0 {\n\twitlb(as, at);\n}\n\n# WSR - Write Special Register, pg. 561.\n:wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 {\n\twsr(sr:1, at);\n}\n\n# WUR - Write User Register, pg. 563.\n:wur at, sr is op2 = 0b1111 & op1 = 0b0011 & sr & at & op0 = 0 {\n wur(sr:1, at);\n}\n\n# XOR - Bitwise Exclusive Or, pg. 564.\n:xor ar, as, at is op2 = 0b0011 & op1 = 0 & ar & as & at & op0 = 0 {\n\tar = as ^ at;\n}\n\n# XORB - Boolean Exclusive Or, pg. 565.\n:xorb br, bs, bt is op2 = 0b0100 & op1 = 0b0010 & br & bs & bt & op0 = 0 {\n\tbr = bs ^^ bt;\n}\n\n# XSR - Exchange Special Register, pg. 566.\n:xsr at, sr is op2 = 0b0110 & op1 = 0b0001 & sr & at & op0 = 0 {\n at = xsr(sr:1, at);\n}\n\n## MAC16 option ##\n\n# LDDEC - Load with Autodecrement, pg. 386.\n:lddec \"MAC16_REGS[\" mw_12_13 \"]\", as is op2 = 0b1001 & op1 = 0 & u2_14_15 = 0 & mw_12_13 & as & at = 0 & op0 = 0b0100 {\n\tlocal ptr:4 = as - 4;\n\tmw_12_13 = *:4 ptr;\n\tas = ptr;\n}\n\n# LDINC - Load with Autoincrement, pg. 387.\n:ldinc \"MAC16_REGS[\" mw_12_13 \"]\", as is op2 = 0b1000 & op1 = 0 & u2_14_15 = 0 & mw_12_13 & as & at = 0 & op0 = 0b0100 {\n\tlocal ptr:4 = as + 4;\n\tmw_12_13 = *:4 ptr;\n\tas = ptr;\n}\n\n# MUL.AA.* - Signed Multiply, pg. 431.\n:mul.aa.ll as, at is op2 = 0x7 & op1 = 0x4 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n:mul.aa.hl as, at is op2 = 0x7 & op1 = 0x5 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.aa.lh as, at is op2 = 0x7 & op1 = 0x6 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.aa.hh as, at is op2 = 0x7 & op1 = 0x7 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n# MUL.AD.* - Signed Multiply, pg. 432.\n:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n# MUL.AD.* - Signed Multiply, pg. 433.\n:mul.da.ll m0m1_14_14, at is op2 = 0x6 & at & op1 = 0x4 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.da.hl m0m1_14_14, at is op2 = 0x6 & op1 = 0x5 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.da.lh m0m1_14_14, at is op2 = 0x6 & op1 = 0x6 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.da.hh m0m1_14_14, at is op2 = 0x6 & op1 = 0x7 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n# MUL.AD.* - Signed Multiply, pg. 434.\n:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = sext(M1:2) * sext(M2:2);\n}\n\n# MULA.AA.* - Signed Multiply, pg. 431.\n:mula.aa.ll as, at is op2 = 0x7 & op1 = 0x8 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n:mula.aa.hl as, at is op2 = 0x7 & op1 = 0x9 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.aa.lh as, at is op2 = 0x7 & op1 = 0xa & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.aa.hh as, at is op2 = 0x7 & op1 = 0xb & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.da.ll m0m1_14_14, at is op2 = 0x6 & at & op1 = 0x8 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.da.hl m0m1_14_14, at is op2 = 0x6 & op1 = 0x9 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.da.lh m0m1_14_14, at is op2 = 0x6 & op1 = 0xa & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.da.hh m0m1_14_14, at is op2 = 0x6 & op1 = 0xb & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n}\n\n# Signed Mult/Accum, Ld/Autodec MULA.DA.*.LDDEC, pg. 441.\n:mula.da.ll.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & at & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.hl.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.lh.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.hh.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n# Signed Mult/Accum, Ld/Autoinc MULA.DA.*.LDINC, pg. 443.\n:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & at & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n# Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC, pg. 446.\n:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as - 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n# Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC, pg. 448.\n:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14:2;\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 {\n\tlocal vaddr:4 = as + 4;\n\ttm1:2 = m0m1_14_14(2);\n\ttm2:2 = m2m3_6_6(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = ACC + (sext(M1:2) * sext(M2:2));\n\tas = vaddr;\n\tmw_12_13 = *:4 vaddr;\n}\n\n# UMUL.AA.* - Unsigned Multiply, pg. 553.\n:umul.aa.ll as, at is op2 = 0x7 & op1 = 0x0 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = zext(M1:2) * zext(M2:2);\n}\n:umul.aa.hl as, at is op2 = 0x7 & op1 = 0x1 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = at:2;\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = zext(M1:2) * zext(M2:2);\n}\n\n:umul.aa.lh as, at is op2 = 0x7 & op1 = 0x2 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as:2;\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = zext(M1:2) * zext(M2:2);\n}\n\n:umul.aa.hh as, at is op2 = 0x7 & op1 = 0x3 & ar = 0 & as & at & op0 = 0x4 {\n\ttm1:2 = as(2);\n\ttm2:2 = at(2);\n\tM1 = zext(tm1);\n\tM2 = zext(tm2);\n\tACC = zext(M1:2) * zext(M2:2);\n}\n\n## Loop Option ##\n\nLoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 loc; }\n\n# LOOP - Loop, pg. 392.\n:loop as, LoopOffset8 is LoopOffset8 & ar = 8 & as & at = 0b0111 & op0 = 6\n\t[ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] {\n\tLCOUNT = as - 1;\n\tLBEG = inst_next;\n\tLEND = &LoopOffset8;\n}\n\n# LOOPGTZ - Loop if Greater Than Zero, pg. 394.\n:loopgtz as, LoopOffset8 is LoopOffset8 & ar = 0b1010 & as & at = 0b0111 & op0 = 0b0110\n\t[ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] {\n\tLCOUNT = as - 1;\n\tLBEG = inst_next;\n\tLEND = &LoopOffset8;\n\tif (as s<= 0) goto LoopOffset8;\n}\n\n# LOOPNEZ - Loop if Not Equal Zero, pg. 396.\n:loopnez as, LoopOffset8 is LoopOffset8 & ar = 0b1001 & as & at = 0b0111 & op0 = 0b0110\n\t[ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] {\n\tLCOUNT = as - 1;\n\tLBEG = inst_next;\n\tLEND = &LoopOffset8;\n\tif (as == 0) goto LoopOffset8;\n}\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensaMain.sinc", "content": "\nattach variables [ sr ] [\n# 0x...0 0x...4 0x...8 0x...c\n LBEG LEND LCOUNT SAR # 0x0_\n BR LITBASE _ _ # 0x1_\n _ _ _ _ # 0x2_\n SCOMPARE1 _ _ _ # 0x3_\n ACCLO ACCHI _ _ # 0x4_\n _ _ _ _ # 0x5_\n _ _ _ _ # 0x6_\n _ _ _ _ # 0x7_\n M0 M1 M2 M3 # 0x8_\n _ _ _ _ # 0x9_\n _ _ _ _ # 0xa_\n _ _ _ _ # 0xb_\n _ _ _ _ # 0xc_\n _ _ _ _ # 0xd_\n _ _ _ _ # 0xe_\n _ _ _ _ # 0xf_\n# 0x...0 0x...4 0x...8 0x...c\n _ _ _ _ # 0x10_\n _ _ _ _ # 0x11_\n WindowBase WindowStart _ _ # 0x12_\n _ _ _ _ # 0x13_\n _ _ _ PTEVADDR # 0x14_\n _ _ _ _ # 0x15_\n _ MMID RASID ITLBCFG # 0x16_\n DTLBCFG _ _ _ # 0x17_\n IBREAKENABLE MEMCTL CACHEATTR ATOMCTL # 0x18_\n _ _ _ _ # 0x19_\n DDR _ MEPC MEPS # 0x1a_\n MESAVE MESR MECR MEVADDR # 0x1b_\n _ _ _ _ # 0x1c_\n _ _ _ _ # 0x1d_\n _ _ _ _ # 0x1e_\n _ _ _ _ # 0x1f_\n# 0x...0 0x...4 0x...8 0x...c\n IBREAKA0 IBREAKA1 _ _ # 0x20_\n _ _ _ _ # 0x21_\n _ _ _ _ # 0x22_\n _ _ _ _ # 0x23_\n DBREAKA0 DBREAKA1 _ _ # 0x24_\n _ _ _ _ # 0x25_\n _ _ _ _ # 0x26_\n _ _ _ _ # 0x27_\n DBREAKC0 DBREAKC1 _ _ # 0x28_\n _ _ _ _ # 0x29_\n _ _ _ _ # 0x2a_\n _ _ _ _ # 0x2b_\n _ EPC1 EPC2 EPC3 # 0x2c_\n EPC4 EPC5 EPC6 EPC7 # 0x2d_\n _ _ _ _ # 0x2e_\n _ _ _ _ # 0x2f_\n# 0x...0 0x...4 0x...8 0x...c\n DEPC _ EPS2 EPS3 # 0x30_\n EPS4 EPS5 EPS6 EPS7 # 0x31_\n _ _ _ _ # 0x32_\n _ _ _ _ # 0x33_\n _ EXCSAVE1 EXCSAVE2 EXCSAVE3 # 0x34_\n EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 # 0x35_\n _ _ _ _ # 0x36_\n _ _ _ _ # 0x37_\n CPENABLE INTERRUPT INTSET INTCLEAR # 0x38_\n INTENABLE _ PS VECBASE # 0x39_\n EXCCAUSE DEBUGCAUSE CCOUNT PRID # 0x3a_\n ICOUNT ICOUNTLEVEL EXCVADDR _ # 0x3b_\n CCOMPARE0 CCOMPARE1 CCOMPARE2 _ # 0x3c_\n MISC0 MISC1 MISC2 MISC3 # 0x3d_\n _ _ _ _ # 0x3e_\n _ _ _ _ # 0x3f_\n# 0x...0 0x...4 0x...8 0x...c\n];\n\nattach variables [ ar as at n_ar n_as n_at ] [\n a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15\n];\n\nattach variables [ fr fs ft ] [\n f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15\n];\n\nattach variables [ br bs bt ] [\n b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15\n];\n\n# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive\n# bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least\n# singificant operand half, LM the most significant bits of the least significant operand half, etc.\n\nattach variables [ mw_12_13 ] [\n\tM0 M1 M2 M3\n];\n\nattach variables [ m2m3_6_6 ] [\n\tM2 M3\n];\n\nattach variables [ m0m1_14_14 ] [\n\tM0 M1\n];\n\n\n#implemented pcodeops\ndefine pcodeop breakpoint;\ndefine pcodeop dhi;\ndefine pcodeop dhu;\ndefine pcodeop dhwb;\ndefine pcodeop dhwbi;\ndefine pcodeop dii;\ndefine pcodeop diu;\ndefine pcodeop diwb;\ndefine pcodeop diwbi;\ndefine pcodeop dpfl;\ndefine pcodeop dpfr;\ndefine pcodeop dpfro;\ndefine pcodeop dpfw;\ndefine pcodeop dpfwo;\ndefine pcodeop dsync;\ndefine pcodeop esync;\ndefine pcodeop excw;\ndefine pcodeop extw;\ndefine pcodeop idtlb;\ndefine pcodeop ihi;\ndefine pcodeop ihu;\ndefine pcodeop iii;\ndefine pcodeop iitlb;\ndefine pcodeop iiu;\ndefine pcodeop ill;\ndefine pcodeop ipf;\ndefine pcodeop ipfl;\ndefine pcodeop isync;\ndefine pcodeop acquire;\ndefine pcodeop ldct;\ndefine pcodeop lict;\ndefine pcodeop licw;\ndefine pcodeop memw;\ndefine pcodeop nsa;\ndefine pcodeop nsau;\ndefine pcodeop pdtlb;\ndefine pcodeop pitlb;\ndefine pcodeop rdtlb0;\ndefine pcodeop rdtlb1;\ndefine pcodeop rer;\ndefine pcodeop restore4;\ndefine pcodeop restore8;\ndefine pcodeop restore12;\ndefine pcodeop rfdd;\ndefine pcodeop rfde;\ndefine pcodeop rfdo;\ndefine pcodeop rfe;\ndefine pcodeop rfi;\ndefine pcodeop rfme;\ndefine pcodeop rfue;\ndefine pcodeop rfwo;\ndefine pcodeop rfwu;\ndefine pcodeop ritlb0;\ndefine pcodeop ritlb1;\ndefine pcodeop rsil;\ndefine pcodeop rsr;\ndefine pcodeop rsync;\ndefine pcodeop rur;\ndefine pcodeop s32c1i;\ndefine pcodeop release;\ndefine pcodeop restoreRegWindow;\ndefine pcodeop rotateRegWindow;\ndefine pcodeop sdct;\ndefine pcodeop sict;\ndefine pcodeop sicw;\ndefine pcodeop simcall;\ndefine pcodeop syscall;\ndefine pcodeop swap4;\ndefine pcodeop swap8;\ndefine pcodeop swap12;\ndefine pcodeop waiti;\ndefine pcodeop wdtlb;\ndefine pcodeop wer;\ndefine pcodeop witlb;\ndefine pcodeop wsr;\ndefine pcodeop wur;\ndefine pcodeop xsr;\n\n\n# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive\n# bits are named foo_LL_LM_ML_MM, where LL is the least significant bits of the least\n# singificant operand half, LM the most significant bits of the least significant operand half, etc.\n\nsrel_16_23: rel is s8_16_23 [ rel = inst_start + s8_16_23 + 4; ] { export *:4 rel; }\n\nsrel_12_23: rel is s12_12_23 [ rel = inst_start + s12_12_23 + 4; ] { export *:4 rel; }\n\nsrel_6_23: rel is s8_6_23 [ rel = inst_start + s8_6_23 + 4; ] { export *:4 rel; }\n\nurel_12_15_4_5: rel is n_u2_4_5 & n_u4_12_15 [\n rel = inst_start + ((n_u2_4_5 << 4) | n_u4_12_15) + 4;\n] { export *:4 rel; }\n\nsrel_6_23_sb2: rel is s8_6_23 [\n rel = (inst_start & ~3) + ( s8_6_23 << 2 ) + 4;\n] { export *:4 rel; }\n\nsrel_8_23_oex_sb2: rel is u16_8_23 [\n rel = ((inst_start + 3) & ~3) + ((u16_8_23 | 0xffff0000) << 2);\n] { export *:4 rel; }\n\n# Immediates split across the instruction.\nu5_8_11_20: tmp is u1_20 & u4_8_11 [ tmp = (u1_20 << 4) | u4_8_11; ] { export *[const]:4 tmp; }\nu5_4_7_20: tmp is u1_20 & u4_4_7 [ tmp = 32 - ((u1_20 << 4) | u4_4_7); ] { export *[const]:4 tmp; }\nu5_8_11_16: tmp is u1_16 & u4_8_11 [ tmp = (u1_16 << 4) | u4_8_11; ] { export *[const]:4 tmp; }\nu5_4_7_12: tmp is u1_12 & u4_4_7 [ tmp = (u1_12 << 4) | u4_4_7; ] { export *[const]:4 tmp; }\nu5_8_11_4: tmp is u1_4 & u4_8_11 [ tmp = (u1_4 << 4) | u4_8_11; ] { export *[const]:4 tmp; }\n\n# Signed 12-bit (extended to 16) immediate, used by MOVI.\ns16_16_23_8_11: tmp is s4_8_11 & u8_16_23 [\n tmp = (s4_8_11 << 8) | u8_16_23;\n] { export *[const]:2 tmp; }\n\n# An “asymmetric” immediate from -32..95, used by MOVI.N.\nn_s8_12_15_4_6_asymm: tmp is n_s3_4_6 & n_s4_12_15 [\n tmp = ((((n_s3_4_6 & 7) << 4) | (n_s4_12_15 & 15)) |\n ((((n_s3_4_6 >> 2) & 1) & ((n_s3_4_6 >> 1) & 1)) << 7));\n] { export *[const]:1 tmp; }\n\n# Immediates shifted or with offset.\ns16_16_23_sb8: tmp is s8_16_23 [ tmp = s8_16_23 << 8; ] { export *[const]:4 tmp; }\nu15_12_23_sb3: tmp is u12_12_23 [ tmp = u12_12_23 << 3; ] { export *[const]:4 tmp; }\nu10_16_23_sb2: tmp is u8_16_23 [ tmp = u8_16_23 << 2; ] { export *[const]:4 tmp; }\nu9_16_23_sb1: tmp is u8_16_23 [ tmp = u8_16_23 << 1; ] { export *[const]:4 tmp; }\nu5_20_23_plus1: tmp is u4_20_23 [ tmp = u4_20_23 + 1; ] { export *[const]:4 tmp; }\nu8_20_23_sb4: tmp is u4_20_23 [ tmp = u4_20_23 << 4; ] { export *[const]:4 tmp; }\nu5_4_7_plus7: tmp is u4_4_7 [ tmp = u4_4_7 + 7; ] { export *[const]:4 tmp; }\n\nn_u6_12_15_sb2: tmp is n_u4_12_15 [ tmp = n_u4_12_15 << 2; ] { export *[const]:4 tmp; }\n\n# One-extended. FIXME: Verify this. Only used by [LS]32E (window extension), which aren’t yet\n# implemented.\ns5_12_15_oex: tmp is u4_12_15 [ tmp = (u4_12_15 << 2) - 64; ] { export *[const]:2 tmp; }\n\n# Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action.\n\n# n_u4_4_7 with 0 being -1, used by ADDI.N.\nn_s4_4_7_nozero: tmp is n_u4_4_7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; }\nn_s4_4_7_nozero: tmp is n_u4_4_7 [ tmp = n_u4_4_7+0; ] { export *[const]:4 tmp; }\n\n# B4CONST(ar) (Branch Immediate) encodings, pg. 41 f.\nr_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 1 [ tmp = 0x1; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 2 [ tmp = 0x2; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 3 [ tmp = 0x3; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 4 [ tmp = 0x4; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 5 [ tmp = 0x5; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 6 [ tmp = 0x6; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 7 [ tmp = 0x7; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 8 [ tmp = 0x8; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 9 [ tmp = 0xa; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 10 [ tmp = 0xc; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 11 [ tmp = 0x10; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 12 [ tmp = 0x20; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 13 [ tmp = 0x40; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 14 [ tmp = 0x80; ] { export *[const]:4 tmp; }\nr_b4const: tmp is ar = 15 [ tmp = 0x100; ] { export *[const]:4 tmp; }\n\n# B4CONSTU(ar) (Branch Unsigned Immediate) encodings, pg. 42.\nr_b4constu: tmp is ar = 0 [ tmp = 0x8000; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 1 [ tmp = 0x1000; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 2 [ tmp = 0x2; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 3 [ tmp = 0x3; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 4 [ tmp = 0x4; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 5 [ tmp = 0x5; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 6 [ tmp = 0x6; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 7 [ tmp = 0x7; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 8 [ tmp = 0x8; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 9 [ tmp = 0xa; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 10 [ tmp = 0xc; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 11 [ tmp = 0x10; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 12 [ tmp = 0x20; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 13 [ tmp = 0x40; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 14 [ tmp = 0x80; ] { export *[const]:4 tmp; }\nr_b4constu: tmp is ar = 15 [ tmp = 0x100; ] { export *[const]:4 tmp; }\n\nRet4: loc\tis epsilon\t[loc = ((inst_start + 3) & 0x0fffffff) | 0x40000000; ] { ret:4 = loc; export ret; }\nRet8: loc\tis epsilon\t[loc = ((inst_start + 3) & 0x0fffffff) | 0x80000000; ] { ret:4 = loc; export ret; }\nRet12: loc\tis epsilon\t[loc = ((inst_start + 3) & 0x0fffffff) | 0xc0000000; ] { ret:4 = loc; export ret; }\n\n:^instruction is phase=0 & loopMode=1 & instruction [ phase=1; ] {\n\tbuild instruction;\n\tif (LCOUNT == 0 || $(PS_EXCM)) goto inst_next;\n\tLCOUNT = LCOUNT - 1;\n\tgoto [LBEG];\n}\n:^instruction is phase=0 & loopMode=1 & loopEnd=1 & instruction\n\t[ loopMode=0; phase=1; ] {\n\tbuild instruction;\n}\n\n:^instruction is phase=0 & loopMode=0 & instruction\n\t[ phase=1; ] {\n\tbuild instruction;\n}\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa_be.slaspec", "content": "@define ENDIAN \"big\"\n@include \"xtensaArch.sinc\"\n@include \"xtensaMain.sinc\"\n\nwith : phase=1 {\n\n@include \"xtensaInstructions.sinc\"\n#@include \"xtensa_depbits.sinc\" #uncomment this to use depbits instruction, collides with floating point\n@include \"cust.sinc\"\n@include \"flix.sinc\"\n\n}" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa_depbits.sinc", "content": "# Xtensa Deposit Bits instruction\n# This is broken out because it collides with the floating point instructions. It is not included by default\n\n# DEPBITS - Add (RRR), pg. 394.\nshiftimm: simm is u4_20_23 & u1_16 [ simm = u1_16 << 4 + u4_20_23; ] { export *[const]:4 simm; }\n:depbits as, at, shiftimm, u4_12_15 is u3_17_19=0x5 & u4_12_15 & as & at & op0 = 0 & shiftimm {\n\tmask:4 = (1 << u4_12_15) - 1;\n\tbits:4 = (as & mask) << shiftimm;\n\tmask = mask << shiftimm;\n\tat = (~mask & at) | bits;\n}\n" }, { "path": "pypcode/processors/Xtensa/data/languages/xtensa_le.slaspec", "content": "@define ENDIAN \"little\"\n@include \"xtensaArch.sinc\"\n@include \"xtensaMain.sinc\"\n\nwith : phase=1 {\n\n@include \"xtensaInstructions.sinc\"\n#@include \"xtensa_depbits.sinc\" #uncomment this to use depbits instruction, collides with floating point\n@include \"cust.sinc\"\n@include \"flix.sinc\"\n\n}\n" }, { "path": "pypcode/processors/Xtensa/data/manuals/xtensa.idx", "content": "@isa_summary.pdf[Xtensa® Instruction Set Architecture Summary, For all Xtensa LX Processors April 2022]\n\nABS,\t324\nABS.D,\t324\nABS.S,\t325\nADD,\t326\nADD.N,\t326\nADD.D,\t327\nADD.S,\t328\nADDEXP.D,\t329\nADDEXP.S,\t329\nADDEXPM.D,\t330\nADDEXPM.S,\t331\nADDI,\t332\nADDI.N,\t333\nADDMI,\t334\nADDX2,\t335\nADDX4,\t336\nADDX8,\t336\nALL4,\t337\nALL8,\t338\nAND,\t339\nANDB,\t339\nANDBC,\t340\nANY4,\t341\nANY8,\t341\nBALL,\t342\nBANY,\t343\nBBC,\t344\nBBCI,\t345\nBBCI.L,\t346\nBBS,\t347\nBBSI,\t348\nBBSI.L,\t349\nBEQ,\t349\nBEQI,\t350\nBEQZ,\t351\nBEQZ.N,\t352\nBF,\t353\nBGE,\t354\nBGEI,\t355\nixBGEU,\t356\nBGEUI,\t357\nBGEZ,\t358\nBLT,\t359\nBLTI,\t360\nBLTU,\t361\nBLTUI,\t361\nBLTZ,\t362\nBNALL,\t363\nBNE,\t364\nBNEI,\t365\nBNEZ,\t366\nBNEZ.N,\t367\nBNONE,\t368\nBREAK,\t369\nBREAK.N,\t370\nBT,\t371\nCALL0,\t372\nCALL4 373\nCALL8,\t375\nCALL12,\t376\nCALLX0,\t377\nCALLX4,\t378\nCALLX8,\t379\nCALLX12,\t380\nCEIL.D,\t382\nCEIL.S,\t383\nCLAMPS,\t383\nCLREX,\t384\nCONST.D,\t385\nCONST.S,\t386\nCONST16,\t387\nCVTD.S,\t388\nCVTS.D,\t389\nDCI,\t389\nDCWB,\t391\nDCWBI,\t392\nDEPBITS,\t394\nDHI,\t395\nDHI.B,\t396\nDHU,\t397\nDHWB,\t398\nDHWB.B,\t400\nDHWBI,\t400\nDHWBI.B,\t402\nxDII,\t403\nDIU,\t404\nDIV0.D,\t406\nDIV0.S,\t406\nDIVN.D,\t407\nDIVN.S,\t408\nDIWB,\t409\nDIWBI,\t410\nDIWBUI.P,\t412\nDPFL,\t413\nDPFM.B,\t415\nDPFM.BF,\t416\nDPFR,\t416\nDPFR.B,\t418\nDPFR.BF,\t419\nDPFRO,\t419\nDPFW,\t421\nDPFW.B,\t422\nDPFW.BF,\t423\nDPFWO,\t424\nDSYNC,\t425\nENTRY,\t426\nESYNC,\t427\nEXCW,\t428\nEXTUI,\t429\nEXTW,\t430\nFLOAT.D,\t431\nFLOAT.S,\t431\nFLOOR.D,\t432\nFLOOR.S,\t433\nFSYNC,\t434\nGETEX,\t434\nIDTLB,\t435\nIHI,\t436\nIHU,\t438\nIII,\t439\nIITLB,\t441\nIIU,\t442\nILL,\t443\nILL.N,\t444\nIPF,\t444\nIPFL,\t446\nISYNC,\t447\nJ,\t449\nJ.L,\t449\nJX,\t450\nL8UI,\t450\nL16SI,\t451\nL16UI,\t453\nL32AI,\t454\nL32E,\t455\nL32EX,\t457\nL32I,\t458\nL32I.N,\t459\nL32R,\t461\nLDCT,\t463\nLDCW,\t464\nLDDEC,\t465\nLDDR32.P,\t467\nLDI,\t467\nLDINC,\t468\nLDIP,\t469\nLDX,\t471\nLDXP,\t472\nLOOP,\t473\nLOOPGTZ,\t475\nLOOPNEZ,\t476\nLSI,\t478\nLSIP,\t480\nLSIU,\t481\nLSX,\t482\nLSXP,\t483\nLSXU,\t484\nMADD.D,\t486\nMADD.S,\t486\nMADDN.D,\t487\nMADDN.S,\t488\nMAX,\t489\nMAXU,\t489\nMEMW,\t490\nMIN,\t491\nMINU,\t491\nMKDADJ.D,\t492\nMKDADJ.S,\t493\nMKSADJ.D,\t494\nMKSADJ.S,\t494\nMOV,\t495\nMOV.D,\t496\nMOV.N,\t497\nMOV.S,\t498\nMOVEQZ,\t499\nMOVEQZ.D,\t499\nMOVEQZ.S,\t500\nMOVF,\t501\nMOVF.D,\t502\nMOVF.S,\t503\nMOVGEZ,\t504\nMOVGEZ.D,\t504\nMOVGEZ.S,\t505\nMOVI,\t506\nMOVI.N,\t507\nMOVLTZ,\t508\nMOVLTZ.D,\t509\nMOVLTZ.S,\t510\nMOVNEZ,\t510\nMOVNEZ.D,\t511\nMOVNEZ.S,\t512\nMOVSP,\t513\nMOVT,\t514\nMOVT.D,\t515\nMOVT.S,\t516\nMSUB.D,\t517\nMSUB.S,\t517\nMUL.AA.*,\t518\nMUL.AD.*,\t519\nMUL.DA.*,\t520\nMUL.DD.*,\t521\nMUL.D,\t522\nMUL.S,\t522\nMUL16S,\t523\nMUL16U,\t524\nMULA.AA.*,\t524\nMULA.AD.*,\t525\nMULA.DA.*,\t526\nMULA.DA.*.LDDEC,\t527\nMULA.DA.*.LDINC,\t528\nMULA.DD.*,\t530\nMULA.DD.*.LDDEC 531\nMULA.DD.*.LDINC 532\nMULL,\t534\nMULS.AA.*,\t535\nMULS.AD.*,\t535\nMULS.DA.*,\t536\nMULS.DD.*,\t537\nMULSH,\t538\nMULUH,\t539\nNEG,\t540\nNEG.D,\t540\nNEG.S,\t541\nNEXP01.D,\t541\nNEXP01.S,\t542\nNOP,\t543\nNOP.N,\t544\nNSA,\t545\nNSAU,\t546\nOEQ.D,\t547\nOEQ.S,\t547\nOLE.D,\t548\nOLE.S,\t549\nOLT.D,\t550\nOLT.S,\t551\nOR,\t551\nORB,\t552\nORBC,\t553\nTLB,\t553\nPITLB,\t554\nPPTLB,\t555\nQUOS,\t556\nQUOU,\t557\nRDTLB0,\t558\nRDTLB1,\t559\nRECIP0.D,\t560\nRECIP0.S,\t560\nREMS,\t561\nREMU,\t562\nRER,\t563\nRET,\t564\nRET.N,\t564\nRETW,\t565\nRETW.N,\t567\nRFDD,\t568\nRFDE,\t569\nRFDO,\t570\nRFE,\t570\nRFI,\t571\nRFME,\t572\nRFR,\t573\nRFRD,\t573\nRFUE,\t574\nRFWO,\t575\nRFWU,\t576\nRITLB0,\t576\nRITLB1,\t577\nROTW,\t578\nROUND.D,\t579\nROUND.S,\t580\nRPTLB0,\t580\nRPTLB1,\t581\nRSIL,\t582\nRSQRT0.D,\t583\nRSQRT0.S,\t584\nRSR.*,\t585\nRSYNC,\t586\nRUR.*,\t586\nS8I,\t587\nS16I,\t588\nS32C1I,\t589\nS32E,\t591\nS32EX,\t592\nS32I,\t594\nS32I.N,\t595\nS32NB,\t596\nS32RI,\t597\nSALT,\t599\nSALTU,\t600\nSDDR32.P,\t600\nSDI,\t601\nSDIP,\t602\nSDX,\t603\nSDXP,\t604\nSEXT,\t605\nSICT,\t606\nSICW,\t607\nSIMCALL,\t609\nSLL,\t609\nSLLI,\t610\nSQRT0.D,\t611\nSQRT0.S,\t612\nSRA,\t613\nSRAI,\t613\nSRC,\t614\nSRL,\t615\nSRLI,\t616\nSSA8B,\t616\nSSA8L,\t617\nSSAI,\t618\nSSI,\t619\nSSIP,\t620\nSSIU,\t621\nSSL,\t622\nSSR,\t623\nSSX,\t624\nSSXP,\t625\nSSXU,\t626\nSUB,\t627\nSUB.D,\t627\nSUB.S,\t628\nSUBX2,\t629\nSUBX4,\t629\nSUBX8,\t630\nSYSCALL,\t631\nTRUNC.D,\t632\nTRUNC.S,\t632\nUEQ.D,\t633\nUEQ.S,\t634\nUFLOAT.D,\t635\nUFLOAT.S,\t636\nULE.D,\t636\nULE.S,\t637\nULT.D,\t638\nULT.S,\t639\nUMUL.AA.*,\t639\nUN.D,\t640\nUN.S,\t641\nUTRUNC.D,\t642\nUTRUNC.S,\t642\nWAITI,\t643\nWDTLB,\t644\nWER,\t645\nWFR,\t646\nWFRD,\t647\nWITLB,\t648\nWPTLB,\t649\nWSR.*,\t650\nWUR.*,\t651\nXOR,\t652\nXORB,\t652\nXSR.*,\t653\n" }, { "path": "pypcode/processors/Xtensa/data/patterns/patternconstraints.xml", "content": "\n \n \t\n \t xtensa_patterns.xml\n \t\n \n" }, { "path": "pypcode/processors/Xtensa/data/patterns/xtensa_patterns.xml", "content": "\n\n \n \n \n 0x0d 0xf0 \n 0x0d 0xf0 0x00 \n 0x0d 0xf0 0x00 0x00 \n 0x0d 0xf0 0x00 0x00 0x00 \n \n 0x80 0x00 0x00 \n 0x80 0x00 0x00 0x00 \n 0x80 0x00 0x00 0x00 0x00 \n 0x80 0x00 0x00 0x00 0x00 0x00 \n \n \n 00010010 11000001 1...0000 \n ....0010 10100... ........ ....0000 00010001 11000000 \n \n \n \n \n \n \n \n 0x1d 0xf0 \n 0x1d 0xf0 0x00 \n 0x1d 0xf0 0x00 0x00 \n 0x1d 0xf0 0x00 0x00 0x00 \n \n \n 0x36 ...00001 0x00 \n \n \n \n \n \n \n 00010010 11000001 0...0000 00001101 11110000 \n 00010010 11000001 0...0000 00001101 11110000 00000000 \n 00010010 11000001 0...0000 00001101 11110000 00000000 00000000 \n 00010010 11000001 0...0000 00001101 11110000 00000000 00000000 00000000 \n \n ....1010 00010001 00001101 11110000 \n ....1010 00010001 00001101 11110000 00000000 \n ....1010 00010001 00001101 11110000 00000000 00000000 \n ....1010 00010001 00001101 11110000 00000000 00000000 00000000 \n \n \n 00010010 11000001 1...0000 \n ....0010 10100... ........ ....0000 00010001 11000000 \n \n \n \n \n \n \n \n ..000110 ........ 1....... \n ..000110 ........ 1....... 00000000 \n ..000110 ........ 1....... 00000000 00000000 \n ..000110 ........ 1....... 00000000 00000000 00000000 \n \n \n ....0010 10100... ........ ....0000 00010001 11000000 \n 00010010 11000001 1...0000 \n \n \n \n \n \n \n ....0010 10100... ........ ....0000 00010001 11000000 \n \n \n \n \n \n 00010010 11000001 1...0000 \n \n \n \n \n \n 0x12 0xc1 0xf0 0x09 0x01 ..000101 ........ ........ 0x08 0x01 0x12 0xc1 0x10 0x0d 0xf0\n \n \n \n \n\n\n" }, { "path": "pypcode/processors/Z80/data/languages/z180.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n\n \n \n \n\n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Z80/data/languages/z180.slaspec", "content": "@define Z180 \"\"\n\n@include \"z80.slaspec\"\n" }, { "path": "pypcode/processors/Z80/data/languages/z182.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n\n \n\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Z80/data/languages/z80.cspec", "content": "\n\n\n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/Z80/data/languages/z80.ldefs", "content": "\n\n\n \n Zilog Z80\n \n \n \n \n \n Zilog Z8401x (IPC) microcontroller\n \n \n \n \n \n Zilog Z180\n \n \n \n \n Zilog Z182\n \n \n\n" }, { "path": "pypcode/processors/Z80/data/languages/z80.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n\n" }, { "path": "pypcode/processors/Z80/data/languages/z80.slaspec", "content": "# sleigh specification file for Zilog Z80\n\n# TODO: Improve Flag bit implementation so that bit operations on F register work properly\n\ndefine endian=little;\ndefine alignment=1;\n@if defined(Z180)\ndefine space ram type=ram_space size=2 default;\n@define PTRSIZE \"2\"\n@else\ndefine space ram type=ram_space size=2 default;\n@define PTRSIZE \"2\"\n@endif\n\ndefine space io type=ram_space size=2;\ndefine space register type=register_space size=1;\n\ndefine register offset=0x00 size=1 [ F A C B E D L H I R ];\ndefine register offset=0x00 size=2 [ AF BC DE HL ];\ndefine register offset=0x20 size=1 [ F_ A_ C_ B_ E_ D_ L_ H_ ]; # Alternate registers\ndefine register offset=0x20 size=2 [ AF_ BC_ DE_ HL_ ]; # Alternate registers\ndefine register offset=0x40 size=2 [ _ PC SP IX IY ];\ndefine register offset=0x46 size=1 [ IXL IXH IYL IYH ]; # Undocumented registers\ndefine register offset=0x50 size=1 [ rCBAR rCBR rBBR ];\n\n# Fake Registers used for pcode control\ndefine register offset=0x60 size=1 [\n\tDECOMPILE_MODE\n];\n\n# Define context bits\ndefine register offset=0xf0 size=4 contextreg;\n\tdefine context contextreg\n assume8bitIOSpace =(0,0) # only applies to Z180\n\t;\n# Flag bits (?? manual is very confusing - could be typos!)\n@define C_flag \"F[0,1]\" # C: Carry\n@define N_flag \"F[1,1]\" # N: Add/Subtract - used by DAA to distinguish between ADD and SUB instructions (0=ADD,1=SUB)\n@define PV_flag \"F[2,1]\" # PV: Parity/Overflow\n@define H_flag \"F[4,1]\" # H: Half Carry\n@define Z_flag \"F[6,1]\" # Z: Zero\n@define S_flag \"F[7,1]\" # S: Sign\n\ndefine token opbyte (8)\n\top0_8 = (0,7)\n\top6_2 = (6,7)\n\tdRegPair4_2 = (4,5)\n\tpRegPair4_2 = (4,5)\n\tsRegPair4_2 = (4,5)\n\tqRegPair4_2 = (4,5)\n\trRegPair4_2 = (4,5)\n\treg3_3 = (3,5)\n\tbits3_3 = (3,5)\n\tbits0_4 = (0,3)\n\treg0_3 = (0,2)\n\tbits0_3 = (0,2)\n;\n\ndefine token data8 (8)\n\timm8 = (0,7)\n\tsign8 = (7,7)\n\tsimm8 = (0,7) signed\n;\n\ndefine token data16 (16)\n\ttimm4 = (12,15)\n\timm16 = ( 0,15)\n\tsign16 = (15,15)\n\tsimm16 = ( 0,15) signed\n;\n\nattach variables [ reg0_3 reg3_3 ] [ B C D E H L _ A ];\n\nattach variables [ sRegPair4_2 dRegPair4_2 ] [ BC DE HL SP ];\n\nattach variables [ qRegPair4_2 ] [ BC DE HL AF ];\n\nattach variables [ pRegPair4_2 ] [ BC DE IX SP ];\nattach variables [ rRegPair4_2 ] [ BC DE IY SP ];\n################################################################\n# Pseudo Instructions\n################################################################\ndefine pcodeop segment; # Define special pcodeop that calculates the RAM address\n# given the segment selector and offset as input\n\ndefine pcodeop BCDadjust;\ndefine pcodeop BCDadjustCarry;\n\ndefine pcodeop hasEvenParity;\ndefine pcodeop disableMaskableInterrupts;\ndefine pcodeop enableMaskableInterrupts;\ndefine pcodeop setInterruptMode;\ndefine pcodeop parity;\ndefine pcodeop sleep;\ndefine pcodeop halt;\n\n################################################################\n# Macros\n################################################################\n\nmacro setResultFlags(result) {\n\t$(Z_flag) = (result == 0);\n\t$(S_flag) = (result s< 0);\n}\n\nmacro additionFlags(operand1, operand2) {\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;\n\t$(PV_flag) = scarry(operand1, operand2);\n\t$(N_flag) = 0;\n\t$(C_flag) = carry(operand1, operand2);\n}\n\nmacro additionFlagsNoC(operand1, operand2) {\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;\n\t$(PV_flag) = scarry(operand1, operand2);\n\t$(N_flag) = 0;\n#\t$(C_flag) is not affected\n}\n\nmacro additionFlagsNoPV(operand1, operand2) {\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;\n#\t$(PV_flag) is not affected\n\t$(N_flag) = 0;\n\t$(C_flag) = carry(operand1, operand2);\n}\n\nmacro additionWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C_flag));\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0;\n\t$(PV_flag) = scarry(operand1, operand2);\n\t$(N_flag) = 0;\n\t$(C_flag) = carry(operand1, operand2);\n\tlocal tempResult = operand1 + operand2;\n\t$(C_flag) = $(C_flag) || carry(tempResult, Ccopy);\n\t$(PV_flag) = $(PV_flag) ^^ scarry(tempResult, Ccopy);\n\tresult = tempResult + Ccopy;\n}\n\nmacro subtractionFlags(operand1, operand2) {\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) - (operand2 & AFmask)) & (AFmask + 1)) != 0;\n\t$(PV_flag) = sborrow(operand1, operand2);\n\t$(N_flag) = 1;\n\t$(C_flag) = operand1 < operand2;\n}\n\nmacro subtractionFlagsNoC(operand1, operand2) {\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) - (operand2 & AFmask)) & (AFmask + 1)) != 0;\n\t$(PV_flag) = sborrow(operand1, operand2);\n\t$(N_flag) = 1;\n#\t$(C_flag) is not affected\n}\n\nmacro subtractionWithCarry(operand1, operand2, result) {\n\tlocal Ccopy = zext($(C_flag));\n\tlocal AFmask = -1 >> 4;\n\t$(H_flag) = (((operand1 & AFmask) - (operand2 & AFmask) - Ccopy) & (AFmask + 1)) != 0;\n\t$(PV_flag) = sborrow(operand1, operand2);\n\t$(N_flag) = 1;\n\t$(C_flag) = operand1 < operand2;\n\tlocal tempResult = operand1 - operand2;\n\t$(C_flag) = $(C_flag) || (tempResult < Ccopy);\n\t$(PV_flag) = $(PV_flag) ^^ sborrow(tempResult, Ccopy);\n\tresult = tempResult - Ccopy;\n}\n\nmacro setSubtractFlags(op1,op2) {\n\t$(C_flag) = (op1 < op2);\n}\n\n# places the parity bit of the given byte in out_parity_bit\n# the upper 7 bits of out_parity_bit are cleared\nmacro setParity(in_byte) {\n\tlocal tmp = in_byte ^ (in_byte >> 1);\n\ttmp = tmp ^ (tmp >> 2);\n\ttmp = (tmp ^ (tmp >> 4)) & 1;\n\t$(PV_flag) = (tmp == 0);\n\t\n# $(PV_flag) = hasEvenParity(in_byte);\n}\n\nmacro ioWrite(addr,val) {\n *[io]:1 addr = val;\n}\n\nmacro ioRead(addr,dest) {\n dest = *[io]:1 addr;\n}\n@if defined(Z180_SEGMENTED)\n\nmacro push16(val16) {\n\tSP = SP - 2;\n\tptr:$(PTRSIZE) = segment(rBBR,SP);\n\t*:2 ptr = val16; \n}\n\nmacro pop16(ret16) {\n ptr:$(PTRSIZE) = segment(rBBR,SP);\n\tret16 = *:2 ptr;\n\tSP = SP + 2; \n}\n\nmacro push8(val8) {\n\tSP = SP - 1;\n\tptr:$(PTRSIZE) = segment(rBBR,SP);\n\t*:1 ptr = val8; \n}\n\nmacro pop8(ret8) {\n ptr:$(PTRSIZE) = segment(rBBR,SP);\n\tret8 = *:1 ptr;\n\tSP = SP + 1; \n}\n\nmacro swap(val16) {\n\tptr:$(PTRSIZE) = segment(rBBR,SP);\n\ttmp:2 = *:2 ptr;\n\t*:2 ptr = val16;\n\tval16 = tmp;\n}\n\nmacro MemRead(dest,off) {\n \tptr:$(PTRSIZE) = segment(rBBR,off);\n\tdest = *:1 ptr;\n}\n\nmacro MemStore(off,val) {\n \tptr:$(PTRSIZE) = segment(rBBR,off);\n\t*:1 ptr = val;\n}\n\nmacro JumpToLoc(off) {\n\tptr:$(PTRSIZE) = segment(rBBR,off);\n\tgoto [ptr];\n}\n\n@else\n\nmacro push16(val16) {\n\tSP = SP - 2;\n\t*:2 SP = val16; \n}\n\nmacro pop16(ret16) {\n\tret16 = *:2 SP;\n\tSP = SP + 2; \n}\n\nmacro push8(val8) {\n\tSP = SP - 1;\n\tptr:$(PTRSIZE) = SP;\n\t*:1 ptr = val8; \n}\n\nmacro pop8(ret8) {\n ptr:$(PTRSIZE) = SP;\n\tret8 = *:1 ptr;\n\tSP = SP + 1; \n}\n\nmacro swap(val16) {\n\tptr:$(PTRSIZE) = SP;\n\ttmp:2 = *:2 ptr;\n\t*:2 ptr = val16;\n\tval16 = tmp;\n}\n\nmacro MemRead(dest,off) {\n \tptr:$(PTRSIZE) = off;\n\tdest = *:1 ptr;\n}\n\nmacro MemStore(off,val) {\n \tptr:$(PTRSIZE) = off;\n\t*:1 ptr = val;\n}\n\nmacro JumpToLoc(off) {\n\tptr:$(PTRSIZE) = off;\n\tgoto [ptr];\n}\n\n@endif\n################################################################\n@if defined(Z180)\n\nFlag: \"Flag\" is reg0_3 { }\n\n@endif\n@if defined(Z180_SEGMENTED)\n\nhlMem8: (HL) is HL { ptr:$(PTRSIZE) = segment(rBBR,HL); export *:1 ptr; }\n\nixMem8: (IX+simm8) is IX & simm8 {\n\toff:2 = IX + simm8;\n\tptr:$(PTRSIZE) = segment(rBBR,off); export *:1 ptr;\n}\nixMem8: (IX-val) is IX & simm8 & sign8=1\t[ val = -simm8; ] {\n\toff:2 = IX + simm8;\n\tptr:$(PTRSIZE) = segment(rBBR,off); export *:1 ptr;\n}\n\niyMem8: (IY+simm8) is IY & simm8 {\n\toff:$(PTRSIZE) = simm8;\n\tptr:$(PTRSIZE) = segment(rBBR,IY);\n\tptr = ptr + off; export *:1 ptr;\n}\niyMem8: (IY-val) is IY & simm8 & sign8=1\t[ val = -simm8; ] {\n\toff:$(PTRSIZE) = simm8;\n\tptr:$(PTRSIZE) = segment(rBBR,IY);\n\tptr = ptr + off; export *:1 ptr;\n}\n\n@else # if Z180_SEGMENTED\n@if defined(Z180)\n\nhlMem8: (HL) is HL { ptr:$(PTRSIZE) = HL; export *:1 ptr; }\n@endif\n\nixMem8: (IX+simm8) is IX & simm8 { ptr:$(PTRSIZE) = IX + simm8; export *:1 ptr; }\nixMem8: (IX-val) is IX & simm8 & sign8=1\t[ val = -simm8; ] { ptr:$(PTRSIZE) = IX + simm8; export *:1 ptr; }\n\niyMem8: (IY+simm8) is IY & simm8 { ptr:$(PTRSIZE) = IY + simm8; export *:1 ptr; }\niyMem8: (IY-val) is IY & simm8 & sign8=1\t[ val = -simm8; ] { ptr:$(PTRSIZE) = IY + simm8; export *:1 ptr; }\n\n@endif # end !Z180_SEGMENTED\n@if defined(Z180)\n\nAddr16: imm16 is imm16 { export *:1 imm16; }\n\nMem8: (imm16) is imm16 { export *:1 imm16; }\n\nMem16: (imm16) is imm16 { export *:2 imm16; }\n\n@else\n\nAddr16: imm16 is imm16 { export *:1 imm16; }\n\nMem8: (imm16) is imm16 { export *:1 imm16; }\n\nMem16: (imm16) is imm16 { export *:2 imm16; }\n\n@endif\n\nRelAddr8: loc is simm8 [ loc = inst_next + simm8; ] { export *:1 loc; }\n\nRstAddr: loc is bits3_3 [ loc = bits3_3 << 3; ] { export *:1 loc; }\n@if defined(Z180)\n\nIOAddr8: (imm8) is imm8 { export *[const]:2 imm8; }\n\nIOAddr8a: (imm8) is assume8bitIOSpace=0 & imm8 { ptr:2 = (zext(A) << 8) + imm8; export ptr; }\nIOAddr8a: (imm8) is assume8bitIOSpace=1 & imm8 { export *[const]:2 imm8; }\n\nIOAddrC: (C) is assume8bitIOSpace=0 & C { ptr:2 = (zext(B) << 8) + zext(C); export ptr; }\nIOAddrC: (C) is assume8bitIOSpace=1 & C { ptr:2 = zext(C); export ptr; }\n@else\n\nIOAddr8a: (imm8) is imm8 { export *[const]:2 imm8; }\n\nIOAddrC: (C) is C { ptr:2 = zext(C); export ptr; }\n@endif\n\ncc: \"NZ\" is bits3_3=0x0 { c:1 = ($(Z_flag) == 0); export c; }\ncc: \"Z\" is bits3_3=0x1 { c:1 = $(Z_flag); export c; }\ncc: \"NC\" is bits3_3=0x2 { c:1 = ($(C_flag) == 0); export c; }\ncc: \"C\" is bits3_3=0x3 { c:1 = $(C_flag); export c; }\ncc: \"PO\" is bits3_3=0x4 { c:1 = ($(PV_flag) == 0); export c; }\ncc: \"PE\" is bits3_3=0x5 { c:1 = $(PV_flag); export c; }\ncc: \"P\" is bits3_3=0x6 { c:1 = ($(S_flag) == 0); export c; }\ncc: \"M\" is bits3_3=0x7 { c:1 = $(S_flag); export c; }\n\ncc2: \"NZ\" is bits3_3=0x4 { c:1 = ($(Z_flag) == 0); export c; }\ncc2: \"Z\" is bits3_3=0x5 { c:1 = $(Z_flag); export c; }\ncc2: \"NC\" is bits3_3=0x6 { c:1 = ($(C_flag) == 0); export c; }\ncc2: \"C\" is bits3_3=0x7 { c:1 = $(C_flag); export c; }\n\n################################################################\n:LD reg3_3,reg0_3 is op6_2=0x1 & reg3_3 & reg0_3 {\n\treg3_3 = reg0_3;\n}\n\n:LD reg3_3,imm8 is op6_2=0x0 & reg3_3 & bits0_3=0x6; imm8 {\n\treg3_3 = imm8;\n}\n\n:LD reg3_3,(HL) is op6_2=0x1 & reg3_3 & bits0_3=0x6 & HL {\n\tMemRead(reg3_3,HL);\n}\n\n:LD reg3_3,ixMem8 is op0_8=0xdd; op6_2=0x1 & reg3_3 & bits3_3!=0x6 & bits0_3=0x6; ixMem8 {\n\treg3_3 = ixMem8; \n}\n\n:LD reg3_3,iyMem8 is op0_8=0xfd; op6_2=0x1 & reg3_3 & bits3_3!=0x6 & bits0_3=0x6; iyMem8 {\n\treg3_3 = iyMem8; \n}\n\n:LD (HL),reg0_3 is op6_2=0x1 & bits3_3=0x6 & reg0_3 & HL {\n\tMemStore(HL,reg0_3);\n}\n\n:LD ixMem8,reg0_3 is op0_8=0xdd; op6_2=0x1 & bits3_3=0x6 & reg0_3 & bits0_3!=0x6; ixMem8 {\n\tixMem8 = reg0_3;\n}\n\n:LD iyMem8,reg0_3 is op0_8=0xfd; op6_2=0x1 & bits3_3=0x6 & reg0_3 & bits0_3!=0x6; iyMem8 {\n\tiyMem8 = reg0_3;\n}\n\n:LD (HL),imm8 is op0_8=0x36 & HL; imm8 {\n\ttmp:1 = imm8;\n\tMemStore(HL,tmp);\n}\n\n:LD ixMem8,imm8 is op0_8=0xdd; op6_2=0x0 & bits3_3=0x6 & bits0_3=0x6; ixMem8; imm8 {\n\tixMem8 = imm8;\n}\n\n:LD iyMem8,imm8 is op0_8=0xfd; op6_2=0x0 & bits3_3=0x6 & bits0_3=0x6; iyMem8; imm8 {\n\tiyMem8 = imm8;\n}\n\n:LD A,(BC) is op0_8=0x0a & A & BC {\n\tMemRead(A,BC);\n}\n\n:LD A,(DE) is op0_8=0x1a & A & DE {\n\tMemRead(A,DE);\n}\n\n:LD A,Mem8 is op0_8=0x3a & A; Mem8 {\n\tA = Mem8;\n}\n\n:LD (BC),A is op0_8=0x2 & BC & A {\n\tMemStore(BC,A);\n}\n\n:LD (DE),A is op0_8=0x12 & DE & A {\n\tMemStore(DE,A);\n}\n\n:LD Mem8,A is op0_8=0x32 & A; Mem8 {\n\tMem8 = A;\n}\n\n:LD A,I is op0_8=0xed & A & I; op0_8=0x57 {\n\tlocal val = I;\n\tA = val;\n\tsetResultFlags(val);\n\t$(H_flag) = 0;\n#\t$(PV_flag) = IFF2;\n\t$(N_flag) = 0;\n}\n\n:LD A,R is op0_8=0xed & A & R; op0_8=0x5f {\n\tlocal val = R;\n\tA = val;\n\tsetResultFlags(val);\n\t$(H_flag) = 0;\n#\t$(PV_flag) = IFF2;\n\t$(N_flag) = 0;\n}\n\n:LD I,A is op0_8=0xed & A & I; op0_8=0x47 {\n\tI = A;\n}\n\n:LD R,A is op0_8=0xed & A & R; op0_8=0x4f {\n\tR = A;\n}\n\n:LD dRegPair4_2,imm16 is op6_2=0x0 & dRegPair4_2 & bits0_4=0x1; imm16 {\n\tdRegPair4_2 = imm16;\n}\n\n:LD IX,imm16 is op0_8=0xdd & IX; op0_8=0x21; imm16 {\n\tIX = imm16;\n}\n\n:LD IY,imm16 is op0_8=0xfd & IY; op0_8=0x21; imm16 {\n\tIY = imm16;\n}\n\n:LD HL,Mem16 is op0_8=0x2a & HL; Mem16 {\n\tHL = Mem16;\n}\n\n:LD dRegPair4_2,Mem16 is op0_8=0xed; op6_2=0x1 & dRegPair4_2 & bits0_4=0xb; Mem16 {\n\tdRegPair4_2 = Mem16;\n}\n\n:LD IX,Mem16 is op0_8=0xdd & IX; op0_8=0x2a; Mem16 {\n\tIX = Mem16;\n}\n\n:LD IY,Mem16 is op0_8=0xfd & IY; op0_8=0x2a; Mem16 {\n\tIY = Mem16;\n}\n\n:LD Mem16,HL is op0_8=0x22 & HL; Mem16 {\n\tMem16 = HL;\n}\n\n:LD Mem16,dRegPair4_2 is op0_8=0xed; op6_2=0x1 & dRegPair4_2 & bits0_4=0x3; Mem16 {\n\tMem16 = dRegPair4_2;\n}\n\n:LD Mem16,IX is op0_8=0xdd & IX; op0_8=0x22; Mem16 {\n\tMem16 = IX;\n}\n\n:LD Mem16,IY is op0_8=0xfd & IY; op0_8=0x22; Mem16 {\n\tMem16 = IY;\n}\n\n:LD SP,HL is op0_8=0xf9 & SP & HL {\n\tSP = HL;\n}\n\n:LD SP,IX is op0_8=0xdd & SP & IX; op0_8=0xf9 {\n\tSP = IX;\n}\n\n:LD SP,IY is op0_8=0xfd & SP & IY; op0_8=0xf9 {\n\tSP = IY;\n}\n\n:PUSH qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x5 {\n\tpush16(qRegPair4_2);\n}\n\n:PUSH IX is op0_8=0xdd & IX; op0_8=0xe5 {\n\tpush16(IX);\n}\n\n:PUSH IY is op0_8=0xfd & IY; op0_8=0xe5 {\n\tpush16(IY);\n}\n\n:POP qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x1 {\n\tpop16(qRegPair4_2);\n}\n\n:POP IX is op0_8=0xdd & IX; op0_8=0xe1 {\n\tpop16(IX);\n}\n\n# ?? Manual appears to have incorrect encoding\n:POP IY is op0_8=0xfd & IY; op0_8=0xe1 {\n\tpop16(IY);\n}\n\n:EX DE,HL is op0_8=0xeb & DE & HL {\n\ttmp:2 = DE;\n\tDE = HL;\n\tHL = tmp;\t\n}\n\n:EX AF, AF_ is op0_8=0x08 & AF & AF_ {\n\ttmp:2 = AF;\n\tAF = AF_;\n\tAF_ = tmp;\n}\n\n:EXX is op0_8=0xd9 {\n\ttmp:2 = BC;\n\tBC = BC_;\n\tBC_ = tmp;\n\ttmp = DE;\n\tDE = DE_;\n\tDE_ = tmp;\n\ttmp = HL;\n\tHL = HL_;\n\tHL_ = tmp;\n}\n\n:EX (SP),HL is op0_8=0xe3 & SP & HL {\n\tswap(HL);\n}\n\n:EX (SP),IX is op0_8=0xdd & SP & IX; op0_8=0xe3 {\n\tswap(IX);\n}\n\n:EX (SP),IY is op0_8=0xfd & SP & IY; op0_8=0xe3 {\n\tswap(IY);\n}\n\n:LDI is op0_8=0xed; op0_8=0xa0 {\n\tval:1 = 0;\n\tlocal inloc = HL;\n\tlocal outloc = DE;\n\tMemRead(val,inloc);\n\tMemStore(outloc,val);\n\t\n\tDE = outloc + 1;\n\tHL = inloc + 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\t\n\t$(H_flag) = 0;\n\t$(PV_flag) = (test != 0);\n\t$(N_flag) = 0;\n}\n\n:LDIR is op0_8=0xed; op0_8=0xb0 {\n\tval:1 = 0;\n\tlocal inloc = HL;\n\tlocal outloc = DE;\n\tMemRead(val,inloc);\n\tMemStore(outloc,val);\n\t\n\tDE = outloc + 1;\n\tHL = inloc + 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\t\n\tif (test != 0) goto inst_start;\n\t\n\t$(H_flag) = 0;\n\t$(PV_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:LDD is op0_8=0xed; op0_8=0xa8 {\n\tval:1 = 0;\n\tlocal inloc = HL;\n\tlocal outloc = DE;\n\tMemRead(val,inloc);\n\tMemStore(outloc,val);\n\t\n\tDE = outloc - 1;\n\tHL = inloc - 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\t\n\t$(H_flag) = 0;\n\t$(PV_flag) = (test != 0);\n\t$(N_flag) = 0;\n}\n\n:LDDR is op0_8=0xed; op0_8=0xb8 {\n\tval:1 = 0;\n\tlocal inloc = HL;\n\tlocal outloc = DE;\n\tMemRead(val,inloc);\n\tMemStore(outloc,val);\n\t\n\tDE = outloc - 1;\n\tHL = inloc - 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\t\n\tif (test != 0) goto inst_start;\n\t\n\t$(H_flag) = 0;\n\t$(PV_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:CPI is op0_8=0xed; op0_8=0xa1 {\n\tval:1 = 0;\n\tlocal loc = HL;\n\tMemRead(val,loc);\n\tlocal a_temp = A;\n\t\n\tcmp:1 = a_temp - val;\n\tsetResultFlags(cmp);\n\tHL = loc + 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\n\tcarries:1 = (~a_temp & val) | (val & cmp) | (cmp & ~a_temp);\n\t$(H_flag) = (carries & 0b00001000) != 0;\n\t$(PV_flag) = (test != 0);\n\t$(N_flag) = 1;\n}\n\n:CPIR is op0_8=0xed; op0_8=0xb1 {\n\tval:1 = 0;\n\tlocal loc = HL;\n\tMemRead(val,loc);\n\tlocal a_temp = A;\n\t\n\tcmp:1 = a_temp - val;\n\tsetResultFlags(cmp);\n\tHL = loc + 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\t\n\tif (cmp != 0 || test != 0) goto inst_start;\n\n\tcarries:1 = (~a_temp & val) | (val & cmp) | (cmp & ~a_temp);\n\t$(H_flag) = (carries & 0b00001000) != 0;\n\t$(PV_flag) = (test != 0);\n\t$(N_flag) = 1;\n}\n\n:CPD is op0_8=0xed; op0_8=0xa9 {\n\tval:1 = 0;\n\tlocal loc = HL;\n\tMemRead(val,loc);\n\tlocal a_temp = A;\n\t\n\tcmp:1 = a_temp - val;\n\tsetResultFlags(cmp);\n\tHL = loc - 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\n\tcarries:1 = (~a_temp & val) | (val & cmp) | (cmp & ~a_temp);\n\t$(H_flag) = (carries & 0b00001000) != 0;\n\t$(PV_flag) = (test != 0);\n\t$(N_flag) = 1;\n}\n\n:CPDR is op0_8=0xed; op0_8=0xb9 {\n\tval:1 = 0;\n\tlocal loc = HL;\n\tMemRead(val,loc);\n\tlocal a_temp = A;\n\t\n\tcmp:1 = a_temp - val;\n\tsetResultFlags(cmp);\n\tHL = loc - 1;\n\tlocal test = BC - 1;\n\tBC = test;\n\t\n\tif (cmp != 0 || test != 0) goto inst_start;\n\n\tcarries:1 = (~a_temp & val) | (val & cmp) | (cmp & ~a_temp);\n\t$(H_flag) = (carries & 0b00001000) != 0;\n\t$(PV_flag) = (test != 0);\n\t$(N_flag) = 1;\n}\n\n:ADD A, reg0_3 is op6_2=0x2 & bits3_3=0x0 & reg0_3 & A {\n\tlocal a_temp = A;\n\tlocal reg_temp = reg0_3;\n\t\n\tadditionFlags(a_temp, reg_temp);\n\ta_temp= a_temp + reg0_3;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADD A, imm8 is op0_8=0xc6; imm8 & A {\n\tlocal a_temp = A;\n\t\n\tadditionFlags(a_temp, imm8);\n\ta_temp = a_temp + imm8;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADD A, (HL) is op0_8=0x86 & HL & A {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t\n\tadditionFlags(a_temp, val);\n\ta_temp = a_temp + val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADD A, ixMem8 is op0_8=0xdd; op0_8=0x86; ixMem8 & A {\n\tval:1 = ixMem8;\n\tlocal a_temp = A;\n\t\n\tadditionFlags(a_temp, val);\n\ta_temp = a_temp + val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADD A, iyMem8 is op0_8=0xfd; op0_8=0x86; iyMem8 & A {\n\tval:1 = iyMem8;\n\tlocal a_temp = A;\n\t\n\tadditionFlags(a_temp, val);\n\ta_temp = a_temp + val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, reg0_3 is op6_2=0x2 & bits3_3=0x1 & reg0_3 & A {\n\tlocal a_temp = A;\n\tlocal r_temp = reg0_3;\n\t\n\tadditionWithCarry(a_temp, r_temp, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, imm8 is op0_8=0xce; imm8 & A {\n\tval:1 = imm8;\n\tlocal a_temp = A;\n\t\n\tadditionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, (HL) is op0_8=0x8e & HL & A {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\n\tadditionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, ixMem8 is op0_8=0xdd; op0_8=0x8e; ixMem8 & A{\n\tval:1 = ixMem8;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t\n\tadditionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, iyMem8 is op0_8=0xfd; op0_8=0x8e; iyMem8 & A {\n\n\tval:1 = iyMem8;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t\n\tadditionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB reg0_3 is op6_2=0x2 & bits3_3=0x2 & reg0_3 {\n\tlocal a_temp = A;\n\tlocal r_temp = reg0_3;\n\t\n\tsubtractionFlags(a_temp, r_temp);\n\ta_temp = a_temp - r_temp;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB imm8 is op0_8=0xd6; imm8 {\n\tlocal a_temp = A;\n\t\n\tsubtractionFlags(a_temp, imm8);\n\ta_temp = a_temp - imm8;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB (HL) is op0_8=0x96 & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t\n\tsubtractionFlags(a_temp, val);\n\ta_temp = a_temp - val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB ixMem8 is op0_8=0xdd; op0_8=0x96; ixMem8 {\n\tval:1 = ixMem8;\n\tlocal a_temp = A;\n\t\n\tsubtractionFlags(a_temp, val);\n\ta_temp = a_temp - val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB iyMem8 is op0_8=0xfd; op0_8=0x96; iyMem8 {\n\tval:1 = iyMem8;\n\tlocal a_temp = A;\n\t\n\tsubtractionFlags(a_temp, val);\n\ta_temp = a_temp - val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SBC A, reg0_3 is op6_2=0x2 & bits3_3=0x3 & reg0_3 & A {\n\tlocal a_temp = A;\n\tlocal r_temp = reg0_3;\n\t\n\tsubtractionWithCarry(a_temp, r_temp, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SBC A, imm8 is op0_8=0xde; imm8 & A {\n\tlocal a_temp = A;\n\t\n\tsubtractionWithCarry(a_temp, imm8, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SBC A, (HL) is op0_8=0x9e & HL & A {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\n\tsubtractionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SBC A, ixMem8 is op0_8=0xdd; op0_8=0x9e; ixMem8 & A {\n\tval:1 = ixMem8;\n\tlocal a_temp = A;\n\n\tsubtractionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SBC A, iyMem8 is op0_8=0xfd; op0_8=0x9e; iyMem8 & A {\n\tval:1 = iyMem8;\n\tlocal a_temp = A;\n\n\tsubtractionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:AND reg0_3 is op6_2=0x2 & bits3_3=0x4 & reg0_3 {\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp & reg0_3;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:AND imm8 is op0_8=0xe6; imm8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp & imm8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:AND (HL) is op0_8=0xa6 & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\n\ta_temp = a_temp & val;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:AND ixMem8 is op0_8=0xdd; op0_8=0xa6; ixMem8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp & ixMem8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:AND iyMem8 is op0_8=0xfd; op0_8=0xa6; iyMem8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp & iyMem8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR reg0_3 is op6_2=0x2 & bits3_3=0x6 & reg0_3 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | reg0_3;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR imm8 is op0_8=0xf6; imm8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | imm8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR (HL) is op0_8=0xb6 & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | val;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR ixMem8 is op0_8=0xdd; op0_8=0xb6; ixMem8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | ixMem8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR iyMem8 is op0_8=0xfd; op0_8=0xb6; iyMem8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | iyMem8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR reg0_3 is op6_2=0x2 & bits3_3=0x5 & reg0_3 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp ^ reg0_3;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR imm8 is op0_8=0xee; imm8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp ^ imm8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR (HL) is op0_8=0xae & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\t\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\t\n\ta_temp = a_temp ^ val;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR ixMem8 is op0_8=0xdd; op0_8=0xae; ixMem8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp ^ ixMem8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR iyMem8 is op0_8=0xfd; op0_8=0xae; iyMem8 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp ^ iyMem8;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:CP reg0_3 is op6_2=0x2 & bits3_3=0x7 & reg0_3 {\n\tlocal a_temp = A;\n\tlocal r_temp = reg0_3;\n\tcmp:1 = a_temp - r_temp;\n\tsubtractionFlags(a_temp, r_temp);\n\tsetResultFlags(cmp);\n}\n\n:CP imm8 is op0_8=0xfe; imm8 {\n\tlocal a_temp = A;\n\tcmp:1 = a_temp - imm8;\n\tsubtractionFlags(a_temp, imm8);\n\tsetResultFlags(cmp);\n}\n\n:CP (HL) is op0_8=0xbe & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\n\tcmp:1 = a_temp - val;\n\tsubtractionFlags(a_temp, val);\n\tsetResultFlags(cmp);\n}\n\n:CP ixMem8 is op0_8=0xdd; op0_8=0xbe; ixMem8 {\n\tval:1 = ixMem8;\n\tlocal a_temp = A;\n\t\n\tcmp:1 = a_temp - val;\n\tsubtractionFlags(a_temp, val);\n\tsetResultFlags(cmp);\n}\n\n:CP iyMem8 is op0_8=0xfd; op0_8=0xbe; iyMem8 {\n\tval:1 = iyMem8;\nlocal a_temp = A;\n\t\n\tcmp:1 = a_temp - val;\n\tsubtractionFlags(a_temp, val);\n\tsetResultFlags(cmp);\n}\n\n:INC reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 {\n\tlocal r_temp = reg3_3;\n\tadditionFlags(r_temp, 1);\n\tr_temp = r_temp + 1;\n\treg3_3 = r_temp;\n\tsetResultFlags(r_temp);\n}\n\n:INC (HL) is op0_8=0x34 & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tval_temp:1 = val;\n\n\tval = val + 1;\n\tMemStore(HL,val);\n\tsetResultFlags(val);\n\tadditionFlagsNoC(val_temp, 1);\n}\n\n:INC ixMem8 is op0_8=0xdd; op0_8=0x34; ixMem8 {\n\tval:1 = ixMem8;\n\tval_temp:1 = val;\n\n\tval = val + 1;\n\tixMem8 = val;\n\tsetResultFlags(val);\n\tadditionFlagsNoC(val_temp, 1);\n}\n\n:INC iyMem8 is op0_8=0xfd; op0_8=0x34; iyMem8 {\n\tval:1 = iyMem8;\n\tval_temp:1 = val;\n\n\tval = val + 1;\n\tiyMem8 = val;\n\tsetResultFlags(val);\n\tadditionFlagsNoC(val_temp, 1);\n}\n\n:DEC reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x5 {\n\tlocal r_temp = reg3_3;\n\tsubtractionFlagsNoC(r_temp, 1);\n\tr_temp = r_temp - 1;\n\treg3_3 = r_temp;\n\tsetResultFlags(r_temp);\n}\n\n:DEC (HL) is op0_8=0x35 & HL {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tval_temp:1 = val;\n\n\tval = val - 1;\n\tMemStore(HL,val);\n\tsubtractionFlagsNoC(val_temp, 1);\n\tsetResultFlags(val);\n}\n\n:DEC ixMem8 is op0_8=0xdd; op0_8=0x35; ixMem8 {\n\tval:1 = ixMem8;\n\tval_temp:1 = val;\n\n\tval = val - 1;\n\tixMem8 = val;\n\tsubtractionFlagsNoC(val_temp, 1);\n\tsetResultFlags(val);\n}\n\n:DEC iyMem8 is op0_8=0xfd; op0_8=0x35; iyMem8 {\n\tval:1 = iyMem8;\n\tval_temp:1 = val;\n\n\tval = val - 1;\n\tiyMem8 = val;\n\tsubtractionFlagsNoC(val_temp, 1);\n\tsetResultFlags(val);\n}\n\n:DAA is op0_8=0x27 {\n\tlocal a_temp = A;\nif (DECOMPILE_MODE) goto ;\n\t\n\tHN:1 = a_temp >> 4; # high nibble\n\tLN:1 = a_temp & 0xF; # low nibbble\n\t#\n\t# If (C and H are both 0, and both nibbles are in range[0,9] no\n\t# adjustment is needed.\n\t#\n\tif (($(C_flag) == 0) & ($(H_flag) == 0) & (HN <= 0x9) & (LN <= 0x9)) goto ;\n\t\n\tif ($(N_flag) == 1) goto ;\n\n\t\t#, in effect\n if ($(C_flag) == 0 & $(H_flag) == 0 & HN <= 0x8 & LN >= 0xA & LN <= 0xF) goto ;\n if ($(C_flag) == 0 & $(H_flag) == 1 & HN <= 0x9 & LN <= 0x3) goto ;\n if ($(C_flag) == 0 & $(H_flag) == 0 & HN >= 0xA & HN <= 0xF & LN <= 0x9) goto ;\n if ($(C_flag) == 0 & $(H_flag) == 0 & HN >= 0x9 & HN <= 0xF & LN >= 0xA & LN <= 0xF) goto ;\n if ($(C_flag) == 0 & $(H_flag) == 1 & HN >= 0xA & HN <= 0xF & LN <= 0x3) goto ;\n if ($(C_flag) == 1 & $(H_flag) == 0 & HN <= 0x2 & LN <= 0x9) goto ;\n if ($(C_flag) == 1 & $(H_flag) == 0 & HN <= 0x2 & LN >= 0xA & LN <= 0xF) goto ;\n if ($(C_flag) == 1 & $(H_flag) == 1 & HN <= 0x3 & LN <= 0x3) goto ;\n goto ; \n\n\t\t# Cases for addition\n #\n # Isn't used\n \n a_temp = a_temp + 0x06;\n goto ; \n \n a_temp = a_temp + 0x06;\n goto ; \n \n a_temp = a_temp + 0x60;\n $(C_flag) = 1;\n goto ; \n \n a_temp = a_temp + 0x66;\n $(C_flag) = 1;\n goto ; \n \n a_temp = a_temp + 0x66;\n $(C_flag) = 1;\n goto ; \n \n a_temp = a_temp + 0x60;\n goto ; \n \n a_temp = a_temp + 0x66;\n goto ; \n \n a_temp = a_temp + 0x66;\n\tgoto ;\n\t\t\n \t\n\t# Cases for subtraction\n #if ($(C_flag) == 0 & $(H_flag) == 0 & HN >= 0x0 & HN <= 0x9 & LN >= 0x0 & LN <= 0x9) goto ;\n if ($(C_flag) == 0 & $(H_flag) == 1 & HN <= 0x8 & LN >= 0x6 & LN <= 0xF) goto ;\n if ($(C_flag) == 1 & $(H_flag) == 0 & HN >= 0x7 & HN <= 0xF & LN <= 0x9) goto ;\n if ($(C_flag) == 1 & $(H_flag) == 1 & HN >= 0x6 & HN <= 0xF & LN >= 0x6 & LN <= 0xF) goto ;\n goto ;\n\n # \n # Isn't used\n \n a_temp = a_temp + 0xFA;\n goto ; \n \n a_temp = a_temp + 0xA0;\n goto ; \n \n a_temp = a_temp + 0x9A;\n\n \t\t\n \n setResultFlags(a_temp);\n setParity(a_temp);\n \n A = a_temp;\n goto ;\n \n\n\n \n \n a_temp = BCDadjust(a_temp, $(C_flag), $(H_flag));\n $(C_flag) = BCDadjustCarry(a_temp, $(C_flag), $(H_flag));\n \n setResultFlags(a_temp);\n $(PV_flag) = hasEvenParity(a_temp);\n A = a_temp;\n\n\n}\n\n:CPL is op0_8=0x2f {\n\tA = ~A;\t\n\t$(H_flag) = 1;\n\t$(N_flag) = 1;\n}\n\n:NEG is op0_8=0xed; op0_8=0x44 {\n\tlocal a_temp = A;\t\n\tsubtractionFlags(0, a_temp);\n\ta_temp = -a_temp;\n\tA = a_temp;\n\tsetResultFlags(a_temp);\n}\n\n:CCF is op0_8=0x3f {\n\t$(C_flag) = !$(C_flag);\n\t$(N_flag) = 0;\n}\n\n:SCF is op0_8=0x37 {\n\t$(C_flag) = 1;\n\t$(H_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:NOP is op0_8=0x0 {\n}\n\n:HALT is op0_8=0x76 {\n\thalt();\n}\n\n:DI is op0_8=0xf3 {\n#\tIFF1 = 0;\n#\tIFF2 = 0;\n\tdisableMaskableInterrupts();\n}\n\n:EI is op0_8=0xfb {\n#\tIFF1 = 1;\n#\tIFF2 = 1;\n\tenableMaskableInterrupts();\n}\n\n:IM 0 is op0_8=0xed; op0_8=0x46 {\n\tsetInterruptMode(0:1);\n}\n\n:IM 1 is op0_8=0xed; op0_8=0x56 {\n\tsetInterruptMode(1:1);\n}\n\n:IM 2 is op0_8=0xed; op0_8=0x5e {\n\tsetInterruptMode(2:1);\n}\n\n:ADD HL,sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x9 & HL {\n\tlocal HL_temp = HL;\n\tlocal Reg_temp = sRegPair4_2;\n\n\tadditionFlagsNoPV(HL_temp, Reg_temp);\n\tHL = HL_temp + Reg_temp;\n}\n\n:ADC HL,sRegPair4_2 is op0_8=0xed & HL; op6_2=0x1 & sRegPair4_2 & bits0_4=0xa {\n\tlocal HL_temp = HL;\n\tlocal Reg_temp = sRegPair4_2;\n\n\tadditionFlagsNoPV(HL_temp, Reg_temp);\n\tHL_temp = HL_temp + Reg_temp + zext($(C_flag));\n\tsetResultFlags(HL_temp);\n\tHL = HL_temp;\n}\n\n:SBC HL,sRegPair4_2 is op0_8=0xed & HL; op6_2=0x1 & sRegPair4_2 & bits0_4=0x2 {\n\tlocal HL_temp = HL;\n\tlocal Reg_temp = sRegPair4_2;\n\t\n\tsubtractionWithCarry(HL_temp, sRegPair4_2, HL_temp);\n\tsetResultFlags(HL_temp);\n\tHL = HL_temp;\n}\n\n:ADD IX,pRegPair4_2 is op0_8=0xdd & IX; op6_2=0x0 & pRegPair4_2 & bits0_4=0x9 {\n\tlocal IX_temp = IX;\n\tlocal Reg_temp = pRegPair4_2;\n\n\tadditionFlagsNoPV(IX_temp, Reg_temp);\n\tIX = IX_temp + pRegPair4_2;\n}\n\n:ADD IY,pRegPair4_2 is op0_8=0xfd & IY; op6_2=0x0 & pRegPair4_2 & bits0_4=0x9 {\n\tlocal IY_temp = IY;\n\tlocal Reg_temp = pRegPair4_2;\n\n\tadditionFlagsNoPV(IY_temp, Reg_temp);\n\tIY = IY_temp + Reg_temp;\n}\n\n:INC sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x3 {\n\tsRegPair4_2 = sRegPair4_2 + 1;\n}\n\n:INC IX is op0_8=0xdd & IX; op0_8=0x23 {\n\tIX = IX + 1;\n}\n\n:INC IY is op0_8=0xfd & IY; op0_8=0x23 {\n\tIY = IY + 1;\n}\n\n:DEC sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0xb {\n\tsRegPair4_2 = sRegPair4_2 - 1;\n}\n\n:DEC IX is op0_8=0xdd & IX; op0_8=0x2b {\n\tIX = IX - 1;\n}\n\n:DEC IY is op0_8=0xfd & IY; op0_8=0x2b {\n\tIY = IY - 1;\n}\n\n:RLCA is op0_8=0x07 {\n\tlocal a_temp = A;\n\t$(C_flag) = (a_temp >> 7);\n\tA = (a_temp << 1) | $(C_flag);\n\t$(H_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:RLA is op0_8=0x17 {\n\tlocal a_temp = A;\n\tnextC:1 = (a_temp >> 7);\n\tA = (a_temp << 1) | $(C_flag);\n\t$(C_flag) = nextC;\n\t$(H_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:RRCA is op0_8=0x0f {\n\tlocal a_temp = A;\n\t$(C_flag) = (a_temp & 1);\n\tA = (a_temp >> 1) | ($(C_flag) << 7);\n\t$(H_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:RRA is op0_8=0x1f {\n\tlocal a_temp = A;\n\tnextC:1 = (a_temp & 1);\n\tA = (a_temp >> 1) | ($(C_flag) << 7);\n\t$(C_flag) = nextC;\n\t$(H_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:RLC reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x0 & reg0_3 {\n\tlocal val = reg0_3;\n\t$(C_flag) = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\treg0_3 = val;\n\tsetResultFlags(val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RLC (HL) is op0_8=0x0cb & HL; op0_8=0x06 {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(C_flag) = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RLC ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x06 {\n\tval:1 = ixMem8;\n\t$(C_flag) = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\t$(N_flag) = 0;\n}\n\n:RLC iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x06 {\n\tval:1 = iyMem8;\n\t$(C_flag) = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RL reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x2 & reg0_3 {\n\tlocal r_temp = reg0_3;\n\tnextC:1 = (r_temp >> 7);\n\tr_temp = (r_temp << 1) | $(C_flag);\n\treg0_3 = r_temp;\n\t$(C_flag) = nextC;\n\tsetResultFlags(r_temp);\n\t$(H_flag) = 0;\n\tsetParity(r_temp);\n\t$(N_flag) = 0;\n}\n\n:RL (HL) is op0_8=0x0cb & HL; op0_8=0x16 {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tnextC:1 = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\t$(C_flag) = nextC;\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RL ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x16 {\n\tval:1 = ixMem8;\n\tnextC:1 = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\t$(C_flag) = nextC;\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RL iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x16 {\n\tval:1 = iyMem8;\n\tnextC:1 = (val >> 7);\n\tval = (val << 1) | $(C_flag);\n\t$(C_flag) = nextC;\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RRC reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x1 & reg0_3 {\n\tlocal r_temp = reg0_3;\n\t$(C_flag) = (r_temp & 1);\n\tr_temp = (r_temp >> 1) | ($(C_flag) << 7);\n\treg0_3 = r_temp;\n\tsetResultFlags(r_temp);\n\t$(H_flag) = 0;\n\tsetParity(r_temp);\n\t$(N_flag) = 0;\n}\n\n:RRC (HL) is op0_8=0x0cb & HL; op0_8=0x0e {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(C_flag) = (val & 1);\n\tval = (val >> 1) | ($(C_flag) << 7);\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RRC ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x0e {\n\tval:1 = ixMem8;\n\t$(C_flag) = (val & 1);\n\tval = (val >> 1) | ($(C_flag) << 7);\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RRC iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x0e {\n\tval:1 = iyMem8;\n\t$(C_flag) = (val & 1);\n\tval = (val >> 1) | ($(C_flag) << 7);\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RR reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x3 & reg0_3 {\n\tlocal r_temp = reg0_3;\n\tnextC:1 = (r_temp & 1);\n\tr_temp = (r_temp >> 1) | ($(C_flag) << 7);\n\treg0_3 = r_temp;\n\t$(C_flag) = nextC;\n\tsetResultFlags(r_temp);\n\t$(H_flag) = 0;\n\tsetParity(r_temp);\n\t$(N_flag) = 0;\n}\n\n:RR (HL) is op0_8=0x0cb & HL; op0_8=0x1e {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tnextC:1 = (val & 1);\n\tval = (val >> 1) | ($(C_flag) << 7);\n\t$(C_flag) = nextC;\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RR ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x1e {\n\tval:1 = ixMem8;\n\tnextC:1 = (val & 1);\n\tval = (val >> 1) | ($(C_flag) << 7);\n\t$(C_flag) = nextC;\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RR iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x1e {\n\tval:1 = iyMem8;\n\tnextC:1 = (val & 1);\n\tval = (val >> 1) | ($(C_flag) << 7);\n\t$(C_flag) = nextC;\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SLA reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x4 & reg0_3 {\n\tlocal r_temp = reg0_3;\n\t$(C_flag) = (r_temp >> 7);\n\tr_temp = r_temp << 1;\n\treg0_3 = r_temp;\n\tsetResultFlags(r_temp);\n\t$(H_flag) = 0;\n\tsetParity(r_temp);\n\t$(N_flag) = 0;\n}\n\n:SLA (HL) is op0_8=0x0cb & HL; op0_8=0x26 {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(C_flag) = (val >> 7);\n\tval = val << 1;\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SLA ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x26 {\n\tval:1 = ixMem8;\n\t$(C_flag) = (val >> 7);\n\tval = val << 1;\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SLA iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x26 {\n\tval:1 = iyMem8;\n\t$(C_flag) = (val >> 7);\n\tval = val << 1;\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRA reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x5 & reg0_3 {\n\tlocal _val = reg0_3;\n\t$(C_flag) = (_val & 1);\n\t_val = _val s>> 1;\n\treg0_3 = _val;\n\tsetResultFlags(_val);\n\t$(H_flag) = 0;\n\tsetParity(_val);\n\t$(N_flag) = 0;\n}\n\n:SRA (HL) is op0_8=0x0cb & HL; op0_8=0x2e {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(C_flag) = (val & 1);\n\tval = val s>> 1;\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRA ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x2e {\n\tval:1 = ixMem8;\n\t$(C_flag) = (val & 1);\n\tval = val s>> 1;\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRA iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x2e {\n\tval:1 = iyMem8;\n\t$(C_flag) = (val & 1);\n\tval = val s>> 1;\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRL reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x7 & reg0_3 {\n\tlocal val = reg0_3;\n\t$(C_flag) = (val & 1);\n\tval = val >> 1;\n\treg0_3 = val;\n\tsetResultFlags(val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRL (HL) is op0_8=0x0cb & HL; op0_8=0x3e {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(C_flag) = (val & 1);\n\tval = val >> 1;\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRL ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x3e {\n\tval:1 = ixMem8;\n\t$(C_flag) = (val & 1);\n\tval = val >> 1;\n\tsetResultFlags(val);\n\tixMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:SRL iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x3e {\n\tval:1 = iyMem8;\n\t$(C_flag) = (val & 1);\n\tval = val >> 1;\n\tsetResultFlags(val);\n\tiyMem8 = val;\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:RLD is op0_8=0xed; op0_8=0x6f {\n\tval:1 = 0;\n\tlocal a_temp = A;\n\tMemRead(val,HL);\n\tnibA:1 = a_temp & 0x0f;\n\tnibM:1 = val >> 4;\n\tval = (val << 4) | nibA;\n\ta_temp = (a_temp & 0xf0) | nibM;\n\tA = a_temp;\n\tMemStore(HL,val);\n@if defined(Z180)\n\tsetResultFlags(val);\n@else\n\tsetResultFlags(a_temp);\n@endif\n\t$(H_flag) = 0;\n\tsetParity(a_temp);\n\t$(N_flag) = 0;\n}\n\n:RRD is op0_8=0xed; op0_8=0x67 {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tlocal a_temp = A;\n\tnibA:1 = a_temp & 0x0f;\n\tnibM:1 = val & 0x0f;\n\tval = (val >> 4) | (nibA << 4);\n\ta_temp = (a_temp & 0xf0) | nibM;\n\tA = a_temp;\n\tMemStore(HL,val);\n@if defined(Z180)\n\tsetResultFlags(val);\n@else\n\tsetResultFlags(a_temp);\n@endif\n\t$(H_flag) = 0;\n\tsetParity(a_temp);\n\t$(N_flag) = 0;\n}\n\n:BIT bits3_3,reg0_3 is op0_8=0xcb; op6_2=0x1 & bits3_3 & reg0_3 {\n\tmask:1 = (1 << bits3_3);\n\t$(Z_flag) = ((reg0_3 & mask) == 0);\n\t$(H_flag) = 1;\n\t$(N_flag) = 0;\n}\n\n:BIT bits3_3,(HL) is op0_8=0xcb & HL; op6_2=0x1 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = (1 << bits3_3);\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(Z_flag) = ((val & mask) == 0);\n\t$(H_flag) = 1;\n\t$(N_flag) = 0;\n}\n\n:BIT bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x1 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = (1 << bits3_3);\n\tval:1 = ixMem8;\n\t$(Z_flag) = ((val & mask) == 0);\n\t$(H_flag) = 1;\n\t$(N_flag) = 0;\n}\n\n:BIT bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x1 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = (1 << bits3_3);\n\tval:1 = iyMem8;\n\t$(Z_flag) = ((val & mask) == 0);\n\t$(H_flag) = 1;\n\t$(N_flag) = 0;\n}\n\n:SET bits3_3,reg0_3 is op0_8=0xcb; op6_2=0x3 & bits3_3 & reg0_3 {\n\tmask:1 = (1 << bits3_3);\n\treg0_3 = reg0_3 | mask;\n}\n\n:SET bits3_3,(HL) is op0_8=0xcb & HL; op6_2=0x3 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = (1 << bits3_3);\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tval = val | mask;\n\tMemStore(HL,val);\n}\n\n:SET bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x3 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = (1 << bits3_3);\n\tval:1 = ixMem8;\n\tixMem8 = val | mask;\n}\n\n:SET bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x3 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = (1 << bits3_3);\n\tval:1 = iyMem8;\n\tiyMem8 = val | mask;\n}\n\n:RES bits3_3,reg0_3 is op0_8=0xcb; op6_2=0x2 & bits3_3 & reg0_3 {\n\tmask:1 = ~(1 << bits3_3);\n\treg0_3 = reg0_3 & mask;\n}\n\n:RES bits3_3,(HL) is op0_8=0xcb & HL; op6_2=0x2 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = ~(1 << bits3_3);\n\tval:1 = 0;\n\tMemRead(val,HL);\n\tval = val & mask;\n\tMemStore(HL,val);\n}\n\n:RES bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x2 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = ~(1 << bits3_3);\n\tval:1 = ixMem8;\n\tixMem8 = val & mask;\n}\n\n:RES bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x2 & bits3_3 & bits0_3=0x6 {\n\tmask:1 = ~(1 << bits3_3);\n\tval:1 = iyMem8;\n\tiyMem8 = val & mask;\n}\n\n:JP Addr16 is op0_8=0xc3; Addr16 {\n\tgoto Addr16;\t\n}\n\n:JP cc,Addr16 is op6_2=0x3 & cc & bits0_3=0x2; Addr16 {\n\tif (cc) goto Addr16;\n}\n\n:JR RelAddr8 is op0_8=0x18; RelAddr8 {\n\tgoto RelAddr8;\n}\n\n:JR cc2,RelAddr8 is op6_2=0x0 & cc2 & bits0_3=0x0; RelAddr8 {\n\tif (cc2) goto RelAddr8;\n}\n\n:JP (HL) is op0_8=0xe9 & HL {\n\toff:2 = (zext(H) << 8) | zext(L);\n\t\n\tJumpToLoc(off);\n\n}\n\n:JP (IX) is op0_8=0xdd & IX; op0_8=0xe9 {\n\t\n\tJumpToLoc(IX);\n}\n\n:JP (IY) is op0_8=0xfd & IY; op0_8=0xe9 {\n\t\n\tJumpToLoc(IY);\n}\n\n:DJNZ RelAddr8 is op0_8=0x10; RelAddr8 {\n\tB = B - 1;\n\tif (B != 0) goto RelAddr8;\n}\n\n:CALL Addr16 is op0_8=0xcd; Addr16 {\n push16(&:2 inst_next);\n\tcall Addr16;\n}\n\n:CALL cc,Addr16 is op6_2=0x3 & cc & bits0_3=0x4; Addr16 {\n\tif (!cc) goto inst_next;\n push16(&:2 inst_next);\n\tcall Addr16;\n}\n\n:RET is op0_8=0xc9 {\n\tpop16(PC);\n\tptr:$(PTRSIZE) = PC;\n\treturn [ptr];\n}\n\n:RET cc is op6_2=0x3 & cc & bits0_3=0x0 {\n\tif (!cc) goto inst_next;\n\tpop16(PC);\n\tptr:$(PTRSIZE) = PC;\n\treturn [ptr];\n}\n\n:RETI is op0_8=0xed; op0_8=0x4d {\n\tpop16(PC);\n\tptr:$(PTRSIZE) = PC;\n\treturn [ptr];\n}\n\n:RETN is op0_8=0xed; op0_8=0x45 {\n\t# IFF1 = IFF2;\n\tpop16(PC);\n\tptr:$(PTRSIZE) = PC;\n\treturn [ptr];\n}\n\n:RST RstAddr is op6_2=0x3 & RstAddr & bits0_3=0x7 {\n push16(&:2 inst_next);\n\tcall RstAddr;\n}\n\n:IN A,IOAddr8a is op0_8=0xdb & A; IOAddr8a {\n\tioRead(IOAddr8a, A);\n}\n\n:IN reg3_3,IOAddrC is op0_8=0xed & IOAddrC; op6_2=0x1 & reg3_3 & bits0_3=0x0 {\n\tval:1 = 0;\n\tioRead(IOAddrC, val);\n\treg3_3 = val;\n\tsetResultFlags(val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n:INI is op0_8=0xed & IOAddrC; op0_8=0xa2 {\n\tval:1 = 0;\n\tioRead(IOAddrC, val);\n\tMemStore(HL,val);\n\tB = B - 1;\n\tHL = HL + 1;\n\t$(Z_flag) = (B == 0);\n\t$(N_flag) = (B s< 0);\n}\n\n:INIR is op0_8=0xed & IOAddrC; op0_8=0xb2 {\n\tval:1 = 0;\n\tioRead(IOAddrC, val);\n\tMemStore(HL,val);\n\tB = B - 1;\n\tHL = HL + 1;\n\tif (B != 0) goto inst_start;\n\t$(Z_flag) = 1;\n\t$(N_flag) = 1;\n}\n\n:IND is op0_8=0xed & IOAddrC; op0_8=0xaa {\n\tval:1 = 0;\n\tioRead(IOAddrC, val);\n\tMemStore(HL,val);\n\tB = B - 1;\n\tHL = HL - 1;\n\t$(Z_flag) = (B == 0);\n\t$(N_flag) = (B s< 0);\n}\n\n:INDR is op0_8=0xed & IOAddrC; op0_8=0xba {\n\tval:1 = 0;\n\tioRead(IOAddrC, val);\n\tMemStore(HL,val);\n\tB = B - 1;\n\tHL = HL - 1;\n\tif (B != 0) goto inst_start;\n\t$(Z_flag) = 1;\n\t$(N_flag) = 1;\n}\n\n:OUT IOAddr8a,A is op0_8=0xd3 & A; IOAddr8a {\n\tioWrite(IOAddr8a, A);\n}\n\n:OUT IOAddrC,reg3_3 is op0_8=0xed & IOAddrC; op6_2=0x1 & reg3_3 & bits0_3=0x1 {\n\tioWrite(IOAddrC, reg3_3);\n}\n\n:OUTI is op0_8=0xed & IOAddrC; op0_8=0xa3 {\n\tlocal test = B - 1;\n\tB = test;\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t\n\tioWrite(IOAddrC, val);\n\tHL = HL + 1;\n\t$(Z_flag) = (test == 0);\n\t$(N_flag) = (test s< 0);\n}\n\n:OTIR is op0_8=0xed & IOAddrC; op0_8=0xb3 {\n\tB = B - 1;\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t\n\tioWrite(IOAddrC, val);\n\tHL = HL + 1;\n\t\n\tif (B != 0) goto inst_start;\n\t\n\t$(Z_flag) = 1;\n\t$(N_flag) = 1;\n}\n\n:OUTD is op0_8=0xed & IOAddrC; op0_8=0xab {\n\tlocal test = B - 1;\n\tB = test;\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t\n\tioWrite(IOAddrC, val);\n\tHL = HL - 1;\n\t$(Z_flag) = (test == 0);\n\t$(N_flag) = (test s< 0);\n}\n\n:OTDR is op0_8=0xed & IOAddrC; op0_8=0xbb {\n\tB = B - 1;\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t\n\tioWrite(IOAddrC, val);\n\tHL = HL - 1;\n\t\n\tif (B != 0) goto inst_start;\n\t\n\t$(Z_flag) = 1;\n\t$(N_flag) = 1;\n}\n@if defined(Z180)\n\n:MLT qRegPair4_2 is op0_8=0xed; op6_2=0x1 & qRegPair4_2 & bits0_4=0xc {\n\tlocal pair = qRegPair4_2;\n\thi:2 = pair >> 8;\n\tlo:2 = pair & 0xff;\n\tqRegPair4_2 = hi * lo;\n}\n\n:TST reg3_3 is op0_8=0xed; op6_2=0x0 & reg3_3 & bits0_3=0x4 {\n\tlocal result = reg3_3 & A;\n\tsetResultFlags(result);\n\t$(H_flag)=1;\n\tsetParity(result);\n\t$(N_flag)=0;\n\t$(C_flag)=0;\n}\n\n:TST hlMem8 is op0_8=0xed; op0_8=0x34 & hlMem8 {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t\n\tlocal result = val & A;\n\tsetResultFlags(result);\n\t$(H_flag)=1;\n\tsetParity(result);\n\t$(N_flag)=0;\n\t$(C_flag)=0;\n}\n\n:TST imm8 is op0_8=0xed; op0_8=0x64; imm8 { \n\tval:1 = imm8 & A;\n\tsetResultFlags(val);\n\t$(H_flag)=1;\n\tsetParity(val);\n\t$(N_flag)=0;\n\t$(C_flag)=0;\n}\n\n:IN0 Flag,IOAddr8 is op0_8=0xed; op6_2=0x0 & bits3_3=0x6 & Flag & bits0_3=0x0; IOAddr8 {\n\tval:1 = 0;\n\tioRead(IOAddr8,val); # read input location\n\tsetResultFlags(val);\n\t$(H_flag)=0;\n\tsetParity(val);\n\t$(N_flag)=0;\t\n}\n\n:IN0 reg3_3,IOAddr8 is op0_8=0xed; op6_2=0x0 & reg3_3 & bits0_3=0x0; IOAddr8 {\n\tlocal r_temp = reg3_3;\n\tioRead(IOAddr8,r_temp); # read input location\n\treg3_3 = r_temp;\n\tsetResultFlags(r_temp); \n\t$(H_flag)=0;\n\tsetParity(r_temp);\n\t$(N_flag)=0;\t\n}\n\n:OUT0 IOAddr8,reg3_3 is op0_8=0xed; op6_2=0x0 & reg3_3 & bits0_3=0x1; IOAddr8 {\n\tioWrite(IOAddr8, reg3_3);\n}\n\n:OTDM is op0_8=0xed; op0_8=0x8b & hlMem8 & IOAddrC {\n\tval:1 = hlMem8;\n\tioWrite(IOAddrC, val);\n\tHL = HL - 1;\n\tC = C - 1;\n\tlocal test = B;\n\tsetSubtractFlags(test,1); # ?? sets $(C_flag) based upon B-1 ??\n\ttest = test - 1;\n\tB = test;\n\tsetResultFlags(test);\n\t# P_flag = parity(r);\n\t$(PV_flag) = (val s< 0);\n}\n\n:OTDMR is op0_8=0xed; op0_8=0x9b & hlMem8 & IOAddrC {\n\tlocal test = B - 1;\n\tB = test;\n\tval:1 = hlMem8;\n\tioWrite(IOAddrC, val);\n\tHL = HL - 1;\n\tC = C - 1;\n\t\n\tif (test != 0) goto inst_start;\n\t\n\t$(S_flag)=0;\n\t$(Z_flag)=1;\n\t$(H_flag) = 0;\n#\t$(PV_flag)=1;\n\t$(PV_flag) = (val s< 0); # based upon last output byte\n\t$(C_flag)=0;\t\n}\n\n:TSTIO IOAddr8 is op0_8=0xed; op0_8=0x74; IOAddr8 {\n\tval:1 = 0;\n\tioRead(IOAddr8,val);\n\tlocal result = A & val;\n\tsetResultFlags(result);\n\t$(H_flag) = 1;\n\t# P_flag = parity(v);\n\t$(N_flag) = 0;\n\t$(C_flag)=0;\n}\n\n:OTIM is op0_8=0xed; op0_8=0x83 & hlMem8 & IOAddrC {\n\tval:1 = hlMem8;\n\tioWrite(IOAddrC, val);\n\tHL = HL + 1;\n\tC = C + 1;\n\tlocal test = B;\n\tsetSubtractFlags(test,1); # ?? sets $(C_flag) based upon B-1 ??\n\ttest = test - 1;\n\tB = test;\n\tsetResultFlags(test);\n\t$(H_flag) = 1;\n\t# P_flag = parity(r);\n\t$(PV_flag) = (val s< 0);\n\t$(N_flag) = 0;\n\t$(C_flag)=0;\n}\n\n:OTIMR is op0_8=0xed; op0_8=0x93 & hlMem8 & IOAddrC {\n\tval:1 = hlMem8;\n\tlocal test = B - 1;\n\tB = test;\n\tioWrite(IOAddrC, val);\n\tHL = HL - 1;\n\tC = C + 1;\n\t\n\tif (test != 0) goto inst_start;\n\t\n\t$(S_flag)=0;\n\t$(Z_flag)=1;\n\t$(H_flag) = 0;\n#\t$(PV_flag)=1;\n\t$(PV_flag) = (val s< 0); # based upon last output byte\n\t$(C_flag)=0;\t\n}\n\n:SLP is op0_8=0xed; op0_8=0x76 {\n\tsleep();\n}\n\n@endif\n\n# Undocumented instructions\n# information taken from https://clrhome.org/table \n\n@ifndef Z180\n\n# Bad support on Z180\n\n\n:IM 0 is op0_8=0xed; op0_8=0x4e {\n\tsetInterruptMode(0:1);\n}\n\n:IM 1 is op0_8=0xed; op0_8=0x6e {\n\tsetInterruptMode(1:1);\n}\n\n\n# CB range\n\n:SLL reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x6 & reg0_3 {\n\tlocal r_temp = reg0_3;\n\t$(C_flag) = (r_temp >> 7);\n\tr_temp = (r_temp << 1) | 0x01;\n\treg0_3 = r_temp;\n\tsetResultFlags(r_temp);\n\t$(H_flag) = 0;\n\tsetParity(r_temp);\n\t$(N_flag) = 0;\n}\n\n:SLL (HL) is op0_8=0x0cb & HL; op0_8=0x36 {\n\tval:1 = 0;\n\tMemRead(val,HL);\n\t$(C_flag) = (val >> 7);\n\tval = val << 1 | 0x01;\n\tsetResultFlags(val);\n\tMemStore(HL,val);\n\t$(H_flag) = 0;\n\tsetParity(val);\n\t$(N_flag) = 0;\n}\n\n## DD range\n\nixh_iyh: IXH is op0_8=0xdd & IXH { export IXH; }\nixh_iyh: IYH is op0_8=0xfd & IYH { export IYH; }\nixl_iyl: IXL is op0_8=0xdd & IXL { export IXL; }\nixl_iyl: IYL is op0_8=0xfd & IYL { export IYL; }\n\n:INC ixh_iyh is ixh_iyh; op0_8=0x24 {\n\tlocal val = ixh_iyh;\n\tadditionFlags(val, 1);\n\tval = val + 1;\n\tixh_iyh = val;\n\tsetResultFlags(val);\n}\n\n:DEC ixh_iyh is ixh_iyh; op0_8=0x25 {\n\tlocal val = ixh_iyh;\n\tsubtractionFlagsNoC(val, 1);\n\tval = val - 1;\n\tixh_iyh = val ;\n\tsetResultFlags(val);\n}\n\n:INC ixl_iyl is ixl_iyl; op0_8=0x2c {\n\tlocal val = ixl_iyl;\n\tadditionFlags(val, 1);\n\tval = val + 1;\n\tixl_iyl = val;\n\tsetResultFlags(val);\n}\n\n:DEC ixl_iyl is ixl_iyl; op0_8=0x2d {\n local val = ixl_iyl;\n\tsubtractionFlagsNoC(val, 1);\n\tval = val - 1;\n\tixl_iyl = val;\n\tsetResultFlags(val);\n}\n\n:LD ixh_iyh,imm8 is ixh_iyh; op0_8=0x26; imm8 {\n\tixh_iyh = imm8;\n}\n\n:LD ixl_iyl,imm8 is ixl_iyl; op0_8=0x2e; imm8 {\n\tixl_iyl = imm8;\n}\n\n:LD B,ixh_iyh is ixh_iyh & B; op0_8=0x44 {\n\tB = ixh_iyh;\n}\n\n:LD B,ixl_iyl is ixl_iyl & B; op0_8=0x45 {\n\tB = ixl_iyl;\n}\n\n:LD C,ixh_iyh is ixh_iyh & C; op0_8=0x4c {\n\tC = ixh_iyh;\n}\n\n:LD C,ixl_iyl is ixl_iyl & C; op0_8=0x4d {\n\tC = ixl_iyl;\n}\n\n:LD D,ixh_iyh is ixh_iyh & D; op0_8=0x54 {\n\tD = ixh_iyh;\n}\n\n:LD D,ixl_iyl is ixl_iyl & D; op0_8=0x55 {\n\tD = ixl_iyl;\n}\n\n:LD E,ixh_iyh is ixh_iyh & E; op0_8=0x5c {\n\tE = ixh_iyh;\n}\n\n:LD E,ixl_iyl is ixl_iyl & E; op0_8=0x5d {\n\tE = ixl_iyl;\n}\n\n:LD ixh_iyh,reg0_3 is ixh_iyh; op6_2=0x1 & bits3_3=0x4 & reg0_3{\n\tixh_iyh = reg0_3;\n}\n\n:LD ixl_iyl,reg0_3 is ixl_iyl; op6_2=0x1 & bits3_3=0x5 & reg0_3 {\n\tixl_iyl = reg0_3;\n}\n\n:LD ixh_iyh,ixl_iyl is ixh_iyh & ixl_iyl; op0_8=0x65 {\n\tixh_iyh = ixl_iyl;\n}\n\n:LD ixh_iyh,A is ixh_iyh; op0_8=0x67 & A {\n\tixh_iyh = A;\n}\n\n:LD ixl_iyl,ixh_iyh is ixl_iyl & ixh_iyh; op0_8=0x6c {\n\tixl_iyl = ixh_iyh;\n}\n\n:LD ixl_iyl,A is ixl_iyl; op0_8=0x6f & A {\n\tixl_iyl = A;\n}\n\n:LD A,ixh_iyh is ixh_iyh; op0_8=0x7c & A {\n\tA = ixh_iyh;\n}\n\n:LD A,ixl_iyl is ixl_iyl; op0_8=0x7d & A {\n\tA = ixl_iyl;\n}\n\n:ADD A, ixh_iyh is ixh_iyh; op0_8=0x84 & A {\n\tlocal a_temp = A;\n\tlocal val = ixh_iyh;\n\t\n\tadditionFlags(a_temp, val);\n\ta_temp = a_temp + val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADD A, ixl_iyl is ixl_iyl; op0_8=0x85 & A {\n\tlocal a_temp = A;\n\tlocal val = ixl_iyl;\n\t\n\tadditionFlags(a_temp, val);\n\ta_temp = a_temp + val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, ixh_iyh is ixh_iyh; op0_8=0x8c & A {\n\tlocal a_temp = A;\n\tlocal val = ixh_iyh;\n\t\n\tadditionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:ADC A, ixl_iyl is ixl_iyl; op0_8=0x8d & A {\n\tlocal a_temp = A;\n\tlocal val = ixl_iyl;\n\t\n\tadditionWithCarry(a_temp, val, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB ixh_iyh is ixh_iyh; op0_8=0x94 {\n\tlocal a_temp = A;\n\tlocal val = ixh_iyh;\n\t\n\tsubtractionFlags(a_temp, val);\n\ta_temp = a_temp - val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SUB ixl_iyl is ixl_iyl; op0_8=0x95 {\n\tlocal a_temp = A;\n\tlocal val = ixl_iyl;\n\t\n\tsubtractionFlags(a_temp, val);\n\ta_temp = a_temp - val;\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:SBC A, ixh_iyh is ixh_iyh; op0_8=0x9c & A {\n\tlocal a_temp = A;\n\tsubtractionWithCarry(a_temp, ixh_iyh, a_temp);\n\tsetResultFlags(A);\n\tA = a_temp;\n}\n\n:SBC A, ixl_iyl is ixl_iyl; op0_8=0x9d & A {\n\tlocal a_temp = A;\n\tsubtractionWithCarry(a_temp, ixl_iyl, a_temp);\n\tsetResultFlags(a_temp);\n\tA = a_temp;\n}\n\n:AND ixh_iyh is ixh_iyh; op0_8=0xa4 {\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp & ixh_iyh;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:AND ixl_iyl is ixl_iyl; op0_8=0xa5 {\n\tlocal a_temp = A;\n\t$(H_flag) = 1;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp & ixl_iyl;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR ixh_iyh is ixh_iyh; op0_8=0xac {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp ^ ixh_iyh;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:XOR ixl_iyl is ixl_iyl; op0_8=0xad {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp ^ ixl_iyl;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR ixh_iyh is ixh_iyh; op0_8=0xb4 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | ixh_iyh;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:OR ixl_iyl is ixl_iyl; op0_8=0xb5 {\n\tlocal a_temp = A;\n\t$(H_flag) = 0;\n\t$(C_flag) = 0;\n\t$(N_flag) = 0;\n\ta_temp = a_temp | ixl_iyl;\n\tsetResultFlags(a_temp);\n\tsetParity(a_temp);\n\tA = a_temp;\n}\n\n:CP ixh_iyh is ixh_iyh; op0_8=0xbc {\n\tlocal a_temp = A;\n\tlocal r_temp = ixh_iyh;\n\t\n\tcmp:1 = a_temp - r_temp;\n\tsubtractionFlags(a_temp, r_temp);\n\tsetResultFlags(cmp);\n}\n\n:CP ixl_iyl is ixl_iyl; op0_8=0xbd {\n\tlocal a_temp = A;\n\tlocal r_temp = ixl_iyl;\n\t\n\tcmp:1 = a_temp - r_temp;\n\tsubtractionFlags(a_temp, r_temp);\n\tsetResultFlags(cmp);\n}\n\n@endif\n" }, { "path": "pypcode/processors/Z80/data/languages/z8401x.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n" }, { "path": "pypcode/processors/Z80/data/manuals/Z180.idx", "content": "@um0050.pdf [Z8018x Family MPU User Manual (UM005003-0703)]\nADD, 227\nADC, 227\nAND, 228\nCP, 228\nCPL, 228\nDEC, 229\nINC, 229\nMLT, 229\nNEG, 229\nOR, 230\nSUB, 230\nSBC, 231\nTST, 231\nXOR, 231\nRL, 232\nRLC, 232\nRLD, 233\nRRA, 233\nRR, 234\nRRCA, 233\nRRC, 233\nRRD, 234\nSLA, 234\nSRA, 234\nSRL, 234\nSET, 235\nRES, 235\nBIT, 236\nLDA, 238\nLD, 238\nCPD, 241\nCPDR, 241\nCPI, 242\nCPIR, 242\nLDD, 242\nLDDR, 242\nLDI, 242\nLDIR, 242\nPUSH, 243\nPOP, 243\nEX, 244\nCALL, 245\nDJNZ, 245\nJP, 245\nJR, 245\nRET, 246\nRETI, 246\nRETN, 246\nRST, 246\nIN, 247\nIN0, 247\nIND, 247\nINDR, 247\nINI, 247\nINIR, 248\nOUT, 248\nOUT0, 248\nOTDM, 248\nOTDMR, 248\nOTDR, 249\nOUTI, 249\nOTIR, 249\nTSTIO, 249\nOTIM, 249\nOTIMR, 250\nOUTD, 250\nDAA, 251\nCCF, 251\nSCF, 251\nDI, 251\nEI, 251\nHALT, 251\nIM0, 251\nIM1, 251\nIM2, 251\nNOP, 251\nSLP, 251\n\n\n" }, { "path": "pypcode/processors/Z80/data/manuals/Z80.idx", "content": "@UM0080.pdf [Z80 FamilyCPU User Manual, Aug 2016 (UM008011-0816)]\nLD, 85\nPUSH, 129\nPOP, 133\nEX, 138\nEXX, 140\nLDI, 144\nLDIR, 146\nLDD, 148\nLDDR, 150\nCPI, 152\nCPIR, 153\nCPD, 155\nCPDR, 156\nADD, 159\nADC, 165\nSUB, 167\nSBC, 169\nAND, 171\nOR, 173\nXOR, 175\nCP, 177\nINC, 179\nDEC, 184\nDAA, 187\nCPL, 189\nNEG, 190\nCCF, 192\nSCF, 193\nNOP, 194\nHALT, 195\nDI, 196\nEI, 197\nIM, 198\nRLCA, 219\nRLA, 221\nRRCA, 223\nRRA, 225\nRLC, 227\nRL, 235\nRRC, 238\nRR, 241\nSLA, 244\nSRA, 247\nSRL, 250\nRLD, 252\nRRD, 254\nBIT, 257\nSET, 265\nRES, 273\nJP, 276\nJR, 279\nDJNZ, 292\nCALL, 295\nRET, 299\nRETI, 302\nRETN, 304\nRST, 306\nIN, 309\nINI, 312\nINIR, 314\nIND, 316\nINDR, 318\nOUT, 320\nOUTI, 323\nOTIR, 325\nOUTD, 327\nOTDR, 329\n" }, { "path": "pypcode/processors/Z80/temp/z8401x.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF.cspec", "content": "\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t \n \n \n\t\t \t\n \n \n \n \n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF.dwarf", "content": "\n \t\t\t\t\t\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF.ldefs", "content": "\n\n \n eBPF processor 64-bit big-endian\n \n \n \n \n eBPF processor 64-bit little-endian\n \n \n \n\n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF.opinion", "content": "\n \n \n \n \n\n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF.pspec", "content": "\n\n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n\n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF.sinc", "content": "###############################################################################\n# eBPF Processor Specification for Ghidra\n###############################################################################\n\ndefine endian=$(ENDIAN);\n\n#eBPF is a RISC register machine with a total of 11 64-bit registers, a program counter and a 512 byte fixed-size stack. \n#9 registers are general purpose read-write, one is a read-only stack pointer and the program counter is implicit,\n#i.e. we can only jump to a certain offset from it. The eBPF registers are always 64-bit wide.\n\ndefine space ram type=ram_space size=8 default;\ndefine space register type=register_space size=4;\ndefine space syscall type=ram_space size=4;\n\ndefine register offset=0 size=8 [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 PC ];\n\n# Instruction encoding: Insop:8, dst_reg:4, src_reg:4, off:16, imm:32 - from lsb to msb\n@if ENDIAN == \"little\"\ndefine token instr(64)\n llvm_imm_callx_zero=(36, 63)\n imm=(32, 63) signed\n llvm_reg_callx=(32, 35) # special encoding for callx instruction emitted by LLVM\n off=(16, 31) signed\n src=(12, 15)\n dst=(8, 11)\n op_alu_jmp_opcode=(4, 7)\n op_alu_jmp_source=(3, 3)\n op_ld_st_mode=(5, 7)\n op_ld_st_size=(3, 4)\n op_insn_class=(0, 2)\n;\n\n#We'll need this token to operate with LDDW instruction, which has 64 bit imm value\ndefine token immtoken(64)\n imm2=(32, 63)\n;\n@else # ENDIAN == \"big\"\ndefine token instr(64)\n imm=(0, 31) signed\n llvm_reg_callx=(0, 3) # special encoding for callx instruction emitted by LLVM\n llvm_imm_callx_zero=(4, 31)\n off=(32, 47) signed\n src=(48, 51)\n dst=(52, 55)\n op_insn_class=(56, 58)\n op_ld_st_size=(59, 60)\n op_ld_st_mode=(61, 63)\n op_alu_jmp_source=(59, 59)\n op_alu_jmp_opcode=(60, 63)\n;\n\ndefine token immtoken(64)\n imm2=(0, 31)\n;\n@endif # ENDIAN = \"big\"\n\n#To operate with registers\nattach variables [ src dst llvm_reg_callx ] [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 _ _ _ _ _ ];\n\n#Arithmetic instructions\n#BPF_ALU64\n###############################################################################\n\nSRC8: src is src & op_alu_jmp_source=1 { export src; }\nSRC8: imm is imm & op_alu_jmp_source=0 { export *[const]:8 imm; }\n\nSRC4: src is src & op_alu_jmp_source=1 { local tmp:4 = src:4; export tmp; }\nSRC4: imm is imm & op_alu_jmp_source=0 { export *[const]:4 imm; }\n\nDST4: dst is dst { local tmp:4 = dst:4; export tmp; }\n\n:MOV dst, SRC8 is SRC8 & dst & off=0 & op_alu_jmp_opcode=0xb & op_insn_class=0x7 { dst = SRC8; }\n:MOVSB dst, src is src & dst & off=8 & op_alu_jmp_opcode=0xb & op_alu_jmp_source=1 & op_insn_class=0x7 { dst = sext(src:1); }\n:MOVSH dst, src is src & dst & off=16 & op_alu_jmp_opcode=0xb & op_alu_jmp_source=1 & op_insn_class=0x7 { dst = sext(src:2); }\n:MOVSW dst, src is src & dst & off=32 & op_alu_jmp_opcode=0xb & op_alu_jmp_source=1 & op_insn_class=0x7 { dst = sext(src:4); }\n\n:ADD dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x0 & op_insn_class=0x7 { dst = dst + SRC8; }\n\n:SUB dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x1 & op_insn_class=0x7 { dst = dst - SRC8; }\n\n:MUL dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x2 & op_insn_class=0x7 { dst = dst * SRC8; }\n\n:DIV dst, SRC8 is SRC8 & dst & off=0 & op_alu_jmp_opcode=0x3 & op_insn_class=0x7 { dst = dst / SRC8; }\n:SDIV dst, SRC8 is SRC8 & dst & off=1 & op_alu_jmp_opcode=0x3 & op_insn_class=0x7 { dst = dst s/ SRC8; }\n\n:OR dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x4 & op_insn_class=0x7 { dst = dst | SRC8; }\n\n:AND dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x5 & op_insn_class=0x7 { dst = dst & SRC8; }\n\n:LSH dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x6 & op_insn_class=0x7 { dst = dst << SRC8; }\n\n:RSH dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0x7 & op_insn_class=0x7 { dst = dst >> SRC8; }\n\n:NEG dst is dst & op_alu_jmp_opcode=0x8 & op_alu_jmp_source=0 & op_insn_class=0x7 { dst = -dst; }\n\n:MOD dst, SRC8 is SRC8 & dst & off=0 & op_alu_jmp_opcode=0x9 & op_insn_class=0x7 { dst = dst % SRC8; }\n:SMOD dst, SRC8 is SRC8 & dst & off=1 & op_alu_jmp_opcode=0x9 & op_insn_class=0x7 { dst = dst s% SRC8; }\n\n:XOR dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0xa & op_insn_class=0x7 { dst = dst ^ SRC8; }\n\n:ARSH dst, SRC8 is SRC8 & dst & op_alu_jmp_opcode=0xc & op_insn_class=0x7 { dst = dst s>> SRC8; }\n\n\n#BPF_ALU\n###############################################################################\n\n:MOV dst, SRC4 is SRC4 & dst & off=0 & op_alu_jmp_opcode=0xb & op_insn_class=0x4 { dst = zext(SRC4); }\n:MOVSB dst, src is src & dst & off=8 & op_alu_jmp_opcode=0xb & op_alu_jmp_source=1 & op_insn_class=0x4 { local tmp:4 = sext(src:1); dst = zext(tmp); }\n:MOVSH dst, src is src & dst & off=16 & op_alu_jmp_opcode=0xb & op_alu_jmp_source=1 & op_insn_class=0x4 { local tmp:4 = sext(src:2); dst = zext(tmp); }\n\n:ADD dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x0 & op_insn_class=0x4 { dst = zext(dst:4 + SRC4); }\n\n:SUB dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x1 & op_insn_class=0x4 { dst = zext(dst:4 - SRC4); }\n\n:MUL dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x2 & op_insn_class=0x4 { dst = zext(dst:4 * SRC4); }\n\n:DIV dst, SRC4 is SRC4 & dst & off=0 & op_alu_jmp_opcode=0x3 & op_insn_class=0x4 { dst = zext(dst:4 / SRC4); }\n:SDIV dst, SRC4 is SRC4 & dst & off=1 & op_alu_jmp_opcode=0x3 & op_insn_class=0x4 { dst = zext(dst:4 s/ SRC4); }\n\n:OR dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x4 & op_insn_class=0x4 { dst = zext(dst:4 | SRC4); }\n\n:AND dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x5 & op_insn_class=0x4 { dst = zext(dst:4 & SRC4); }\n\n:LSH dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x6 & op_insn_class=0x4 { dst = zext(dst:4 << SRC4); }\n\n:RSH dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0x7 & op_insn_class=0x4 { dst = zext(dst:4 >> SRC4); }\n\n:NEG dst is dst & op_alu_jmp_opcode=0x8 & op_alu_jmp_source=0 & op_insn_class=0x4 { dst = zext(-dst:4); }\n\n:MOD dst, SRC4 is SRC4 & dst & off=0 & op_alu_jmp_opcode=0x9 & op_insn_class=0x4 { dst = zext(dst:4 % SRC4); }\n:SMOD dst, SRC4 is SRC4 & dst & off=1 & op_alu_jmp_opcode=0x9 & op_insn_class=0x4 { dst = zext(dst:4 s% SRC4); }\n\n:XOR dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0xa & op_insn_class=0x4 { dst = zext(dst:4 ^ SRC4); }\n\n:ARSH dst, SRC4 is SRC4 & dst & op_alu_jmp_opcode=0xc & op_insn_class=0x4 { dst = zext(dst:4 s>> SRC4); }\n\n\n#Bytewasp instructions\n###############################################################################\n\n@if ENDIAN == \"little\"\n# BPF_ALU | BPF_K | BPF_END\n:LE16 dst is imm=0x10 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x4 { dst = zext(dst:2); }\n:LE32 dst is imm=0x20 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x4 { dst = zext(dst:4); }\n:LE64 dst is imm=0x40 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x4 {}\n\n# BPF_ALU | BPF_X | BPF_END\n:BE16 dst is imm=0x10 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=1 & op_insn_class=0x4 {\n dst = ((dst & 0xff00) >> 8) | ((dst & 0x00ff) << 8);\n}\n:BE32 dst is imm=0x20 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=1 & op_insn_class=0x4 {\n dst = ((dst & 0xff000000) >> 24) | (((dst) & 0x00ff0000) >> 8) | (((dst) & 0x0000ff00) << 8) | ((dst & 0x000000ff) << 24);\n}\n:BE64 dst is imm=0x40 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=1 & op_insn_class=0x4 {\n dst = ((dst << 56) & 0xff00000000000000) |\n ((dst << 40) & 0x00ff000000000000) |\n ((dst << 24) & 0x0000ff0000000000) |\n ((dst << 8) & 0x000000ff00000000) |\n ((dst >> 8) & 0x00000000ff000000) |\n ((dst >> 24) & 0x0000000000ff0000) |\n ((dst >> 40) & 0x000000000000ff00) |\n ((dst >> 56) & 0x00000000000000ff);\n}\n@else # ENDIAN == \"big\"\n# BPF_ALU | BPF_K | BPF_END\n:LE16 dst is imm=0x10 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x4 {\n dst = ((dst & 0xff00) >> 8) | ((dst & 0x00ff) << 8);\n}\n:LE32 dst is imm=0x20 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x4 {\n dst = ((dst & 0xff000000) >> 24) | (((dst) & 0x00ff0000) >> 8) | (((dst) & 0x0000ff00) << 8) | ((dst & 0x000000ff) << 24);\n}\n:LE64 dst is imm=0x40 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x4 {\n dst = ((dst << 56) & 0xff00000000000000) |\n ((dst << 40) & 0x00ff000000000000) |\n ((dst << 24) & 0x0000ff0000000000) |\n ((dst << 8) & 0x000000ff00000000) |\n ((dst >> 8) & 0x00000000ff000000) |\n ((dst >> 24) & 0x0000000000ff0000) |\n ((dst >> 40) & 0x000000000000ff00) |\n ((dst >> 56) & 0x00000000000000ff);\n}\n\n# BPF_ALU | BPF_X | BPF_END\n:BE16 dst is imm=0x10 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=1 & op_insn_class=0x4 { dst = zext(dst:2); }\n:BE32 dst is imm=0x20 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=1 & op_insn_class=0x4 { dst = zext(dst:4); }\n:BE64 dst is imm=0x40 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=1 & op_insn_class=0x4 {}\n@endif # ENDIAN = \"big\"\n\n# BPF_ALU64 | BPF_K | BPF_END\n:BSWAP16 dst is imm=0x10 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x7 {\n dst = ((dst & 0xff00) >> 8) | ((dst & 0x00ff) << 8);\n}\n:BSWAP32 dst is imm=0x20 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x7 {\n dst = ((dst & 0xff000000) >> 24) | (((dst) & 0x00ff0000) >> 8) | (((dst) & 0x0000ff00) << 8) | ((dst & 0x000000ff) << 24);\n}\n:BSWAP64 dst is imm=0x40 & dst & op_alu_jmp_opcode=0xd & op_alu_jmp_source=0 & op_insn_class=0x7 {\n dst = ((dst << 56) & 0xff00000000000000) |\n ((dst << 40) & 0x00ff000000000000) |\n ((dst << 24) & 0x0000ff0000000000) |\n ((dst << 8) & 0x000000ff00000000) |\n ((dst >> 8) & 0x00000000ff000000) |\n ((dst >> 24) & 0x0000000000ff0000) |\n ((dst >> 40) & 0x000000000000ff00) |\n ((dst >> 56) & 0x00000000000000ff);\n}\n\n#Memory instructions - Load and Store\n###############################################################################\n\n#LDDW is the only 16-byte eBPF instruction which consists of two consecutive 8-byte blocks ('struct bpf_insn') \n#and interpreted as single instruction which loads 64-bit imm value into dst. Encoding of LDDW:\n#LSR MSR\n# opcode src dst offset Low 8-byte imm zero-block High 8-byte imm\n#bits 8 4 4 16 32 32 32\n# So, imm64 consists of concatination of high 8-byte imm and low 8-byte imm.\n\n:LDDW dst, concat is imm & dst & op_ld_st_mode=0x0 & op_ld_st_size=0x3 & op_insn_class=0x0; imm2 [ concat= (imm2 << 32) | ((imm) & 0xFFFFFFFF); ] { dst = concat; }\n\n#BPF_LD_MAP_FD(DST, MAP_FD) -> second LDDW = pseudo LDDW insn used to refer to process-local map_fd \n#For each instruction which needs relocation, it inject corresponding file descriptor to imm field. \n#As a part of protocol, src_reg is set to BPF_PSEUDO_MAP_FD (which defined as 1) to notify kernel this is a map loading instruction.\n\n:LDDW dst, imm is imm & src=1 & dst & op_ld_st_mode=0x0 & op_ld_st_size=0x3 & op_insn_class=0x0; imm2 { dst = *:8 imm:8; }\n\n:LDABSW dst, imm is imm & dst & op_ld_st_mode=0x1 & op_ld_st_size=0x0 & op_insn_class=0x0 { dst = zext(*:4 imm:8); }\n\n:LDABSH dst, imm is imm & dst & op_ld_st_mode=0x1 & op_ld_st_size=0x1 & op_insn_class=0x0 { dst = zext(*:2 imm:8); }\n\n:LDABSB dst, imm is imm & dst & op_ld_st_mode=0x1 & op_ld_st_size=0x2 & op_insn_class=0x0 { dst = zext(*:1 imm:8); }\n\n:LDABSDW dst, imm is imm & dst & op_ld_st_mode=0x1 & op_ld_st_size=0x3 & op_insn_class=0x0 { dst = *:8 imm:8; }\n\n:LDINDW src, dst, imm is imm & src & dst & op_ld_st_mode=0x2 & op_ld_st_size=0x0 & op_insn_class=0x0 { dst = zext(*:4 (src + imm)); }\n\n:LDINDH src, dst, imm is imm & src & dst & op_ld_st_mode=0x2 & op_ld_st_size=0x1 & op_insn_class=0x0 { dst = zext(*:2 (src + imm)); }\n\n:LDINDB src, dst, imm is imm & src & dst & op_ld_st_mode=0x2 & op_ld_st_size=0x2 & op_insn_class=0x0 { dst = zext(*:1 (src + imm)); }\n\n:LDINDDW src, dst, imm is imm & src & dst & op_ld_st_mode=0x2 & op_ld_st_size=0x3 & op_insn_class=0x0 { dst = *:8 (src + imm); }\n\n:LDXW dst, [src + off] is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x1 { dst = zext(*:4 (src + off)); }\n\n:LDXH dst, [src + off] is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x1 { dst = zext(*:2 (src + off)); }\n\n:LDXB dst, [src + off] is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x1 { dst = zext(*:1 (src + off)); }\n\n:LDXDW dst, [src + off] is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x3 & op_insn_class=0x1 { dst = *:8 (src + off); }\n\n:STW [dst + off], imm is imm & off & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x2 { *:4 (dst + off)=imm:4; }\n\n:STH [dst + off], imm is imm & off & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x2 { *:2 (dst + off)=imm:2; }\n\n:STB [dst + off], imm is imm & off & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x2 { *:1 (dst + off)=imm:1; }\n\n:STDW [dst + off], imm is imm & off & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x3 & op_insn_class=0x2 { *:8 (dst + off)=imm:8; }\n\n:STXW [dst + off], src is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off)=src:4; }\n\n:STXH [dst + off], src is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x1 & op_insn_class=0x3 { *:2 (dst + off)=src:2; }\n\n:STXB [dst + off], src is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x2 & op_insn_class=0x3 { *:1 (dst + off)=src:1; }\n\n:STXDW [dst + off], src is off & src & dst & op_ld_st_mode=0x3 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off)=src:8; }\n\n:LDSXW dst, [src + off] is off & src & dst & op_ld_st_mode=0x4 & op_ld_st_size=0x0 & op_insn_class=0x1 { dst = sext(*:4 (src + off)); }\n\n:LDSXH dst, [src + off] is off & src & dst & op_ld_st_mode=0x4 & op_ld_st_size=0x1 & op_insn_class=0x1 { dst = sext(*:2 (src + off)); }\n\n:LDSXB dst, [src + off] is off & src & dst & op_ld_st_mode=0x4 & op_ld_st_size=0x2 & op_insn_class=0x1 { dst = sext(*:1 (src + off)); }\n\n# BPF_ATOMIC\n# BPF_ADD:\n\n# BPF_STX | BPF_ATOMIC | BPF_W\n:STXXADDW [dst + off], src is imm=0x0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) + src:4; }\n\n# BPF_STX | BPF_ATOMIC | BPF_DW\n:STXXADDDW [dst + off], src is imm=0x0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) + src; }\n\n# BPF_OR:\n\n:STXXADDW [dst + off], src is imm=0x40 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) | src:4; }\n\n:STXXADDDW [dst + off], src is imm=0x40 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) | src; }\n\n# BPF_AND:\n\n:STXXADDW [dst + off], src is imm=0x50 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) & src:4; }\n\n:STXXADDDW [dst + off], src is imm=0x50 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) & src; }\n\n# BPF_XOR:\n\n:STXXADDW [dst + off], src is imm=0xa0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) ^ src:4; }\n\n:STXXADDDW [dst + off], src is imm=0xa0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) ^ src; }\n\n# BPF_ADD | BPF_FETCH -> src = atomic_fetch_add(dst + off, src):\n\n:STXXADDW [dst + off], src is imm=0x1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { \n local tmp:4 = *:4 (dst + off);\n *:4 (dst + off) = *:4 (dst + off) + src:4;\n src = zext(tmp);\n}\n\n:STXXADDDW [dst + off], src is imm=0x1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { \n local tmp:8 = *:8 (dst + off);\n *:8 (dst + off) = *:8 (dst + off) + src; \n src = tmp;\n}\n\n# BPF_OR | BPF_FETCH -> src = atomic_fetch_or(dst + off, src):\n\n:STXXADDW [dst + off], src is imm=0x41 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { \n local tmp:4 = *:4 (dst + off);\n *:4 (dst + off) = *:4 (dst + off) | src:4;\n src = zext(tmp);\n}\n\n:STXXADDDW [dst + off], src is imm=0x41 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { \n local tmp:8 = *:8 (dst + off);\n *:8 (dst + off) = *:8 (dst + off) | src; \n src = tmp;\n}\n\n# BPF_AND | BPF_FETCH -> src = atomic_fetch_and(dst + off, src):\n\n:STXXADDW [dst + off], src is imm=0x51 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { \n local tmp:4 = *:4 (dst + off);\n *:4 (dst + off) = *:4 (dst + off) & src:4;\n src = zext(tmp);\n}\n\n:STXXADDDW [dst + off], src is imm=0x51 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { \n local tmp:8 = *:8 (dst + off);\n *:8 (dst + off) = *:8 (dst + off) & src; \n src = tmp;\n}\n\n# BPF_XOR | BPF_FETCH -> src = atomic_fetch_xor(dst + off, src):\n\n:STXXADDW [dst + off], src is imm=0xa1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { \n local tmp:4 = *:4 (dst + off);\n *:4 (dst + off) = *:4 (dst + off) ^ src:4;\n src = zext(tmp);\n}\n\n:STXXADDDW [dst + off], src is imm=0xa1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { \n local tmp:8 = *:8 (dst + off);\n *:8 (dst + off) = *:8 (dst + off) ^ src; \n src = tmp;\n}\n\n# BPF_XCHG -> src_reg = atomic_xchg(dst + off, src):\n\n:STXXADDW [dst + off], src is imm=0xe1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { \n local tmp:4 = *:4 (dst + off);\n *:4 (dst + off) = src:4;\n src = zext(tmp);\n}\n\n:STXXADDDW [dst + off], src is imm=0xe1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { \n local tmp:8 = *:8 (dst + off);\n *:8 (dst + off) = src;\n src = tmp;\n}\n\n# BPF_CMPXCHG -> R0 = atomic_cmpxchg(dst + off, R0, src):\n\n:STXXADDW [dst + off], src is imm=0xf1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { \n local tmp:4 = *:4 (dst + off);\n if (R0:4 == tmp) goto ;\n R0 = zext(tmp); \n\n *:4 (dst + off) = src:4;\n}\n\n:STXXADDDW [dst + off], src is imm=0xf1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { \n local tmp:8 = *:8 (dst + off);\n if (R0 == tmp) goto ;\n R0 = tmp; \n\n *:8 (dst + off) = src; \n}\n\n#Jump instructions (BPF_JMP, BPF_JMP32)\n###############################################################################\n\njoff: reloc is off [ reloc = inst_next + off * 8; ] { export *:8 reloc; }\njimm: reloc is imm [ reloc = inst_next + imm * 8; ] { export *:8 reloc; }\n\ncond: \"EQ\" is op_alu_jmp_opcode=0x1 & op_insn_class=0x5 & dst & SRC8 { local cmp = dst == SRC8; export cmp; }\ncond: \"EQ\" is op_alu_jmp_opcode=0x1 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 == SRC4; export cmp; }\ncond: \"GT\" is op_alu_jmp_opcode=0x2 & op_insn_class=0x5 & dst & SRC8 { local cmp = dst > SRC8; export cmp; }\ncond: \"GT\" is op_alu_jmp_opcode=0x2 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 > SRC4; export cmp; }\ncond: \"GE\" is op_alu_jmp_opcode=0x3 & op_insn_class=0x5 & dst & SRC8 { local cmp = dst >= SRC8; export cmp; }\ncond: \"GE\" is op_alu_jmp_opcode=0x3 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 >= SRC4; export cmp; }\ncond: \"LT\" is op_alu_jmp_opcode=0xa & op_insn_class=0x5 & dst & SRC8 { local cmp = dst < SRC8; export cmp; }\ncond: \"LT\" is op_alu_jmp_opcode=0xa & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 < SRC4; export cmp; }\ncond: \"LE\" is op_alu_jmp_opcode=0xb & op_insn_class=0x5 & dst & SRC8 { local cmp = dst <= SRC8; export cmp; }\ncond: \"LE\" is op_alu_jmp_opcode=0xb & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 <= SRC4; export cmp; }\ncond: \"NE\" is op_alu_jmp_opcode=0x5 & op_insn_class=0x5 & dst & SRC8 { local cmp = dst != SRC8; export cmp; }\ncond: \"NE\" is op_alu_jmp_opcode=0x5 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 != SRC4; export cmp; }\ncond: \"SET\" is op_alu_jmp_opcode=0x4 & op_insn_class=0x5 & dst & SRC8 { local cmp = (dst & SRC8) != 0; export cmp; }\ncond: \"SET\" is op_alu_jmp_opcode=0x4 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = (DST4 & SRC4) != 0; export cmp; }\n\ncond: \"SGT\" is op_alu_jmp_opcode=0x6 & op_insn_class=0x5 & dst & SRC8 { local cmp = dst s> SRC8; export cmp; }\ncond: \"SGT\" is op_alu_jmp_opcode=0x6 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 s> SRC4; export cmp; }\ncond: \"SGE\" is op_alu_jmp_opcode=0x7 & op_insn_class=0x5 & dst & SRC8 { local cmp = dst s>= SRC8; export cmp; }\ncond: \"SGE\" is op_alu_jmp_opcode=0x7 & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 s>= SRC4; export cmp; }\ncond: \"SLT\" is op_alu_jmp_opcode=0xc & op_insn_class=0x5 & dst & SRC8 { local cmp = dst s< SRC8; export cmp; }\ncond: \"SLT\" is op_alu_jmp_opcode=0xc & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 s< SRC4; export cmp; }\ncond: \"SLE\" is op_alu_jmp_opcode=0xd & op_insn_class=0x5 & dst & SRC8 { local cmp = dst s<= SRC8; export cmp; }\ncond: \"SLE\" is op_alu_jmp_opcode=0xd & op_insn_class=0x6 & DST4 & SRC4 { local cmp = DST4 s<= SRC4; export cmp; }\n\n\n:JA joff is joff & op_alu_jmp_opcode=0x0 & op_alu_jmp_source=0 & op_insn_class=0x5 {\n goto joff;\n}\n\n:JA jimm is jimm & op_alu_jmp_opcode=0x0 & op_alu_jmp_source=0 & op_insn_class=0x6 {\n goto jimm;\n}\n\n:J^cond dst, SRC8, joff is joff & SRC8 & dst & cond {\n if (cond) goto joff;\n}\n\n\nSysCall: imm is imm { export *[syscall]:1 imm; }\n\n:CALL SysCall is imm & src=0 & op_alu_jmp_opcode=0x8 & op_alu_jmp_source=0 & op_insn_class=0x5 & SysCall {\n call SysCall;\n}\n\ndisp32: reloc is imm [ reloc = inst_next + imm * 8; ] { export *:4 reloc; }\n\n:CALL disp32 is imm & src=1 & op_alu_jmp_opcode=0x8 & op_alu_jmp_source=0 & op_insn_class=0x5 & disp32 {\n call disp32;\n}\n\n# GCC encoding and LLVM 19.1+ encoding\n:CALLX dst is op_alu_jmp_opcode=0x8 & op_alu_jmp_source=1 & op_insn_class=0x5 & src=0 & imm=0 & dst {\n call [dst];\n}\n\n# LLVM encoding used until LLVM 19.1\n# Introduced in https://github.com/llvm/llvm-project/commit/9a67245d881f4cf89fd8f897ae2cd0bccec49496\n# Modified in https://github.com/llvm/llvm-project/commit/c43ad6c0fddac0bbed5e881801dd2bc2f9eeba2d\n:CALLX llvm_reg_callx is op_alu_jmp_opcode=0x8 & op_alu_jmp_source=1 & op_insn_class=0x5 & dst=0 & src=0 & llvm_imm_callx_zero=0 & llvm_reg_callx {\n call [llvm_reg_callx];\n}\n# Both CALLX encodings are matched when both dst and imm are zero\n:CALLX R0 is op_alu_jmp_opcode=0x8 & op_alu_jmp_source=1 & op_insn_class=0x5 & dst=0 & src=0 & imm=0 & R0 {\n call [R0];\n}\n\n:EXIT is op_alu_jmp_opcode=0x9 & op_alu_jmp_source=0 & op_insn_class=0x5 { return [*:8 R10]; }\n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF_be.slaspec", "content": "@define ENDIAN \"big\"\n\n@include \"eBPF.sinc\"\n" }, { "path": "pypcode/processors/eBPF/data/languages/eBPF_le.slaspec", "content": "@define ENDIAN \"little\"\n\n@include \"eBPF.sinc\"\n" }, { "path": "pypcode/processors/tricore/data/languages/tc172x.pspec", "content": "\n\n\n \n \n \n\n \n \n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n\n 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\n\n" }, { "path": "pypcode/processors/tricore/data/languages/tc176x.pspec", "content": "\n\n\n \n \n \n\n \n \n \n \n \n\t\n\t\n\t\n \n\t\n \t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/tricore/data/languages/tc29x.pspec", "content": "\n\n\n \n \n \n \n \n \n\t\t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.cspec", "content": "\n\n\n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.dwarf", "content": "\n\t\n\t\t \n\t\t \n\t\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n\t\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.ldefs", "content": "\n\n\n \n \n Siemens Tricore Embedded Processor\n \n \n \n \n Siemens Tricore Embedded Processor TC29x\n \n \n \n \n Siemens Tricore Embedded Processor TC1724/TC1728\n \n \n \n \n Siemens Tricore Embedded Processor TC1762/TC1766\n \n \n \n\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.opinion", "content": "\n \n \n \n\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.pcp.sinc", "content": "\n\n# R0 - Accumulator\n# R1 -\n# R2 - Return Address\n# R3 -\n# R4 - SRC\n# R5 - DST\n# R6 - CPPN/SRPN/TOS/CNT1\n# R7 - DPTR/Flags\ndefine register offset=0xf0043F00 size=4 [ R0 R1 R2 R3 R4 R5 R6 R7 ];\n@define CPPN \"R6[24,8]\"\n@define SRPN \"R6[16,8]\"\n@define TOS \"R6[14,2]\"\n@define CNT1 \"R6[0,12]\"\n\n@define DPTR \"R7[8,8]\"\n@define CEN \"R7[6,1]\"\n@define IEN \"R7[5,1]\"\n@define CNZ \"R7[4,1]\"\n@define V \"R7[3,1]\"\n@define C \"R7[2,1]\"\n@define N \"R7[1,1]\"\n@define Z \"R7[0,1]\"\n\ndefine token pcpinstr (16)\n pcp_op0000=(0,0)\n pcp_op0001=(0,1)\n pcp_op0002=(0,2)\n ccAB=(0,3)\n ccA=(0,2)\n pcp_op0004=(0,4)\n pcp_op0005=(0,5)\n pcp_op0009=(0,9)\n pcp_op0010=(0,10)\n pcp_op0101=(1,1)\n pcp_op0202=(2,2)\n pcp_op0203=(2,3)\n pcp_op0204=(2,4)\n pcp_op0303=(3,3)\n R0305=(3,5)\n pcp_op0404=(4,4)\n pcp_op0405=(4,5)\n pcp_op0406=(4,6)\n pcp_op0505=(5,5)\n pcp_op0506=(5,6)\n R0608=(6,8)\n ccB=(6,9)\n pcp_op0707=(7,7)\n pcp_op0708=(7,8)\n pcp_op0808=(8,8)\n pcp_op0909=(9,9)\n pcp_op0910=(9,10)\n pcp_op0912=(9,12)\n pcp_op1010=(10,10)\n pcp_op1012=(10,12)\n pcp_op1111=(11,11)\n pcp_op1212=(12,12)\n addrmode=(13,15)\n;\n\ndefine token pcpinstr2 (16)\n pcp_op1631=(0,15)\n;\n\nattach variables [ R0305 R0608 ] [ R0 R1 R2 R3 R4 R5 R6 R7 ];\n\n\nCONDCA: \"cc_UC\" is PCPMode=1 & ccA=0x0 { local tmp:1 = 1; export tmp; }\nCONDCA: \"cc_Z\" is PCPMode=1 & ccA=0x1 { local tmp:1 = ($(Z)==1); export tmp; }\nCONDCA: \"cc_NZ\" is PCPMode=1 & ccA=0x2 { local tmp:1 = ($(Z)==0); export tmp; }\nCONDCA: \"cc_V\" is PCPMode=1 & ccA=0x3 { local tmp:1 = ($(V)==1); export tmp; }\nCONDCA: \"cc_ULT\" is PCPMode=1 & ccA=0x4 { local tmp:1 = ($(C)==1); export tmp; }\nCONDCA: \"cc_UGT\" is PCPMode=1 & ccA=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; }\nCONDCA: \"cc_SLT\" is PCPMode=1 & ccA=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; }\nCONDCA: \"cc_SGT\" is PCPMode=1 & ccA=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; }\n\nCONDCB: \"cc_UC\" is PCPMode=1 & ccB=0x0 { local tmp:1 = 1; export tmp; }\nCONDCB: \"cc_Z\" is PCPMode=1 & ccB=0x1 { local tmp:1 = ($(Z)==1); export tmp; }\nCONDCB: \"cc_NZ\" is PCPMode=1 & ccB=0x2 { local tmp:1 = ($(Z)==0); export tmp; }\nCONDCB: \"cc_V\" is PCPMode=1 & ccB=0x3 { local tmp:1 = ($(V)==1); export tmp; }\nCONDCB: \"cc_ULT\" is PCPMode=1 & ccB=0x4 { local tmp:1 = ($(C)==1); export tmp; }\nCONDCB: \"cc_UGT\" is PCPMode=1 & ccB=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; }\nCONDCB: \"cc_SLT\" is PCPMode=1 & ccB=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; }\nCONDCB: \"cc_SGT\" is PCPMode=1 & ccB=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; }\nCONDCB: \"cc_N\" is PCPMode=1 & ccB=0x8 { local tmp:1 = ($(N)==1); export tmp; }\nCONDCB: \"cc_NN\" is PCPMode=1 & ccB=0x9 { local tmp:1 = ($(N)==0); export tmp; }\nCONDCB: \"cc_NV\" is PCPMode=1 & ccB=0xA { local tmp:1 = ($(V)==0); export tmp; }\nCONDCB: \"cc_UGE\" is PCPMode=1 & ccB=0xB { local tmp:1 = ($(C)==0); export tmp; }\nCONDCB: \"cc_SGE\" is PCPMode=1 & ccB=0xC { local tmp:1 = (($(N)^$(V))==0); export tmp; }\nCONDCB: \"cc_SLE\" is PCPMode=1 & ccB=0xD { local tmp:1 = ((($(N)^$(V))|$(Z))==1); export tmp; }\nCONDCB: \"cc_CNZ\" is PCPMode=1 & ccB=0xE { local tmp:1 = ($(CNZ)==1); export tmp; }\nCONDCB: \"cc_CNN\" is PCPMode=1 & ccB=0xF { local tmp:1 = ($(CNZ)==0); export tmp; }\n\n#TODO\nCONDCAB: \"cc_UC\" is PCPMode=1 & ccAB=0x0 { local tmp:1 = 1; export tmp; }\nCONDCAB: \"cc_Z\" is PCPMode=1 & ccAB=0x1 { local tmp:1 = ($(Z)==1); export tmp; }\nCONDCAB: \"cc_NZ\" is PCPMode=1 & ccAB=0x2 { local tmp:1 = ($(Z)==0); export tmp; }\nCONDCAB: \"cc_V\" is PCPMode=1 & ccAB=0x3 { local tmp:1 = ($(V)==1); export tmp; }\nCONDCAB: \"cc_ULT\" is PCPMode=1 & ccAB=0x4 { local tmp:1 = ($(C)==1); export tmp; }\nCONDCAB: \"cc_UGT\" is PCPMode=1 & ccAB=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; }\nCONDCAB: \"cc_SLT\" is PCPMode=1 & ccAB=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; }\nCONDCAB: \"cc_SGT\" is PCPMode=1 & ccAB=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; }\nCONDCAB: \"cc_N\" is PCPMode=1 & ccAB=0x8 { local tmp:1 = ($(N)==1); export tmp; }\nCONDCAB: \"cc_NN\" is PCPMode=1 & ccAB=0x9 { local tmp:1 = ($(N)==0); export tmp; }\nCONDCAB: \"cc_NV\" is PCPMode=1 & ccAB=0xA { local tmp:1 = ($(V)==0); export tmp; }\nCONDCAB: \"cc_UGE\" is PCPMode=1 & ccAB=0xB { local tmp:1 = ($(C)==0); export tmp; }\nCONDCAB: \"cc_SGE\" is PCPMode=1 & ccAB=0xC { local tmp:1 = (($(N)^$(V))==0); export tmp; }\nCONDCAB: \"cc_SLE\" is PCPMode=1 & ccAB=0xD { local tmp:1 = ((($(N)^$(V))|$(Z))==1); export tmp; }\nCONDCAB: \"cc_CNZ\" is PCPMode=1 & ccAB=0xE { local tmp:1 = ($(CNZ)==1); export tmp; }\nCONDCAB: \"cc_CNN\" is PCPMode=1 & ccAB=0xF { local tmp:1 = ($(CNZ)==0); export tmp; }\n\nimm5: \"#\"^pcp_op0004 is pcp_op0004 { local tmp:4 = pcp_op0004; export tmp; }\nimm6: \"#\"^pcp_op0005 is pcp_op0005 { local tmp:4 = pcp_op0005; export tmp; }\n#imm10: \"#\"^pcp_op0009 is pcp_op0009 { local tmp:4 = pcp_op0009; export tmp; }\nimm16: \"#\"^pcp_op1631 is pcp_op1631 { local tmp:4 = pcp_op1631; export tmp; }\noffset6: \"[#\"^pcp_op0005^\"]\" is pcp_op0005 { local tmp:4 = (zext($(DPTR)) << 6) + pcp_op0005; export *[ram]:4 tmp; }\n\noffset6W: R0608, \"[#\"^pcp_op0005^\"]\" is pcp_op0005 & R0608 { local tmp:4 = (zext($(DPTR)) << 6) + pcp_op0005; *[ram]:4 tmp = R0608; }\noffset6RW: R0608, \"[#\"^pcp_op0005^\"]\" is pcp_op0005 & R0608 { local tmp:4 = R0608; local ea:4 = (zext($(DPTR)) << 6) + pcp_op0005; R0608 = *[ram]:4 ea; *[ram]:4 ea = tmp; }\n\nSRC: R4 is PCPMode=1 & pcp_op0708=0 & R4 { local tmp:4 = 0; export tmp; }\nSRC: R4+ is PCPMode=1 & pcp_op0708=1 & R4 { local tmp:4 = 1; export tmp; }\nSRC: R4- is PCPMode=1 & pcp_op0708=2 & R4 { local tmp:4 = -1; export tmp; }\n\nDST: R5 is PCPMode=1 & pcp_op0910=0 & R5 { local tmp:4 = 0; export tmp; }\nDST: R5+ is PCPMode=1 & pcp_op0910=1 & R5 { local tmp:4 = 1; export tmp; }\nDST: R5- is PCPMode=1 & pcp_op0910=2 & R5 { local tmp:4 = -1; export tmp; }\n\nSIZE0: \"8\" is PCPMode=1 & pcp_op0001=0 { local tmp:4 = zext(*[ram]:1 R4); export tmp;}\nSIZE0: \"16\" is PCPMode=1 & pcp_op0001=1 { local tmp:4 = zext(*[ram]:2 R4); export tmp;}\nSIZE0: \"32\" is PCPMode=1 & pcp_op0001=2 { local tmp:4 = *[ram]:4 R4; export tmp;}\n\nSIZE1: [R0305], \"8\" is PCPMode=1 & pcp_op0001=0 & R0305 { local tmp:4 = zext(*[ram]:1 R0305); export tmp;}\nSIZE1: [R0305], \"16\" is PCPMode=1 & pcp_op0001=1 & R0305 { local tmp:4 = zext(*[ram]:2 R0305); export tmp;}\nSIZE1: [R0305], \"32\" is PCPMode=1 & pcp_op0001=2 & R0305 { local tmp:4 = *[ram]:4 R0305; export tmp;}\n\nSIZE1W: R0608, [R0305], \"8\" is PCPMode=1 & pcp_op0001=0 & R0305 & R0608 { *[ram]:1 R0305 = R0608[0,8]; }\nSIZE1W: R0608, [R0305], \"16\" is PCPMode=1 & pcp_op0001=1 & R0305 & R0608 { *[ram]:2 R0305 = R0608[0,16]; }\nSIZE1W: R0608, [R0305], \"32\" is PCPMode=1 & pcp_op0001=2 & R0305 & R0608 { *[ram]:4 R0305 = R0608; }\n\nSIZE1RW: R0608, [R0305], \"8\" is PCPMode=1 & pcp_op0001=0 & R0305 & R0608 { local tmp:1 = R0608[0,8]; R0608 = zext(*[ram]:1 R0305); *[ram]:1 R0305 = tmp; }\nSIZE1RW: R0608, [R0305], \"16\" is PCPMode=1 & pcp_op0001=1 & R0305 & R0608 { local tmp:2 = R0608[0,16]; R0608 = zext(*[ram]:2 R0305); *[ram]:2 R0305 = tmp; }\nSIZE1RW: R0608, [R0305], \"32\" is PCPMode=1 & pcp_op0001=2 & R0305 & R0608 { local tmp:4 = R0608; R0608 = *[ram]:4 R0305; *[ram]:4 R0305 = tmp; }\n\nSIZE5: \"8\" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=0 & R0608 { local tmp:4 = zext(*[ram]:1 R0608); export tmp;}\nSIZE5: \"16\" is PCPMode=1 & pcp_op0505=1 & pcp_op0909=0 & R0608 { local tmp:4 = zext(*[ram]:2 R0608); export tmp;}\nSIZE5: \"32\" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=1 & R0608 { local tmp:4 = *[ram]:4 R0608; export tmp;}\n\nSIZE5W: [R0608], imm5, \"8\" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=0 & imm5 & R0608 { *[ram]:1 (R0608 + imm5) = R0[0,8]; }\nSIZE5W: [R0608], imm5, \"16\" is PCPMode=1 & pcp_op0505=1 & pcp_op0909=0 & imm5 & R0608 { *[ram]:2 (R0608 + imm5) = R0[0,16]; }\nSIZE5W: [R0608], imm5, \"32\" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=1 & imm5 & R0608 { *[ram]:4 (R0608 + imm5) = R0; }\n\n# Counter Control\n# 00 = perform xfer by CNT0 ; goto next\n# 01 = perform xfer by CNT0 ; dec CNT1 ; goto next\n# 10 = perform xfer by CNT0 ; dec CNT1 ; repeat dec ; goto next\nCNC: pcp_op0506 is PCPMode=1 & pcp_op0506 { local tmp:4 = pcp_op0506; export tmp; }\n\n# Counter Reload Value (COPY)\n# 001..111 = perform 1..7 xfer\nCNT03: pcp_op0204 is PCPMode=1 & pcp_op0204 { local tmp:4 = pcp_op0204; export tmp; }\n\n# Counter Reload Value Block Size (BCOPY)\n# 00 = block size 8 words\n# 10 = block size 2 words\n# 11 = block size 4 words\nCNT02: pcp_op0203 is PCPMode=1 & pcp_op0203 { local tmp:4 = pcp_op0203; export tmp; }\n\nEC: pcp_op0707 is PCPMode=1 & pcp_op0707 { local tmp:1 = pcp_op0707; export tmp; }\nEP: pcp_op0808 is PCPMode=1 & pcp_op0808 { local tmp:1 = pcp_op0808; export tmp; }\nINT: pcp_op0909 is PCPMode=1 & pcp_op0909 { local tmp:1 = pcp_op0909; export tmp; }\nST: pcp_op1010 is PCPMode=1 & pcp_op1010 { local tmp:1 = pcp_op1010; export tmp; }\n\nSETCLR: \"SET\" is PCPMode=1 & pcp_op0505=1 { local tmp:1 = 1; export tmp; }\nSETCLR: \"CLR\" is PCPMode=1 & pcp_op0505=0 { local tmp:1 = 0; export tmp; }\n\nSDB: pcp_op0000 is PCPMode=1 & pcp_op0000 { local tmp:1 = pcp_op0000; export tmp; }\nEDA: pcp_op0101 is PCPMode=1 & pcp_op0101 { local tmp:1 = pcp_op0101; export tmp; }\nRTA: pcp_op0202 is PCPMode=1 & pcp_op0202 { local tmp:1 = pcp_op0202; export tmp; }\nDAC: pcp_op0303 is PCPMode=1 & pcp_op0303 { local tmp:1 = pcp_op0303; export tmp; }\n\n# Addressing Modes:\n# 0 - control\n# 1 - FPI\n# 2 - PRAM\n# 3 - Arithmetic\n# 4 - Immediate\n# 5 - FPI Immediate\n# 6 - Complex Maths\n# 7 - Jump\n\n\n# 3: 16-bit 6000|0b110000000000000 9e00|0b1001111000000000\n# ADD Rb, Ra, cc_A\n:add R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x0 & R0608 & R0305 & CONDCA\n{\n\t#TODO flags N,Z,V,C\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = R0608 + R0305;\n}\n\n\n# 1: 16-bit 2000|0b10000000000000 de04|0b1101111000000100\n# ADD.F Rb, [Ra], Size\n:add.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x0 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\t#TODO flags N,Z,V,C\n\tbuild SIZE1;\n\tR0608 = R0608 + SIZE1;\n}\n\n\n# 4: 16-bit 8000|0b1000000000000000 7e00|0b111111000000000\n# ADD.I Ra, #imm6\n:add.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x0 & imm6\n{\n\t#TODO flags N,Z,V,C\n\tR0608 = R0608 + imm6;\n}\n\n\n# 2: 16-bit 4000|0b100000000000000 be00|0b1011111000000000\n# ADD.PI Ra, [#offset6]\n:add.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x0 & R0608 & offset6\n{\n\t#TODO flags N,Z,V,C\n\tbuild offset6;\n\tR0608 = R0608 + offset6; \n}\n\n\n# 3: 16-bit 6a00|0b110101000000000 9400|0b1001010000000000\n# AND Rb, Ra, cc_A\n:and R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x5 & R0608 & R0305 & CONDCA\n{\n\t#TODO flags N,Z\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = R0608 & R0305;\n}\n\n\n# 1: 16-bit 2a00|0b10101000000000 d404|0b1101010000000100\n# AND.F Rb, [Ra], Size\n:and.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x5 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\t#TODO flags N,Z\n\tbuild SIZE1;\n\tR0608 = R0608 & SIZE1;\n}\n\n\n# 2: 16-bit 4a00|0b100101000000000 b400|0b1011010000000000\n# AND.PI Ra, [#offset6]\n:and.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x5 & R0608 & offset6\n{\n\t#TODO flags N,Z\n\tbuild offset6;\n\tR0608 = R0608 & offset6;\n}\n\n\n# 0: 16-bit 1800|0b1100000000000 e013|0b1110000000010011\n#\n:bcopy DST, SRC, CNC, CNT02 is PCPMode=1 & addrmode=0 & pcp_op1212=0x1 & pcp_op1111=0x1 & DST & SRC & CNC & CNT02 & pcp_op0404=0x0 & pcp_op0001=0x0\n{\n}\n\n\n# 4: 16-bit 9c00|0b1001110000000000 6200|0b110001000000000\n# CHKB Ra, #imm5, S/C\n:chkb R0608, imm5, SETCLR is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xe & SETCLR & imm5\n{\n\t$(C) = (R0608 & (1 << imm5)) != 0;\n}\n\n\n# 4: 16-bit 9600|0b1001011000000000 6820|0b110100000100000\n# CLR Ra, #imm5\n:clr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xb & pcp_op0505=0x0 & imm5\n{\n\tR0608 = R0608 & ~(1 << imm5);\n}\n\n\n# 5: 16-bit b000|0b1011000000000000 4c00|0b100110000000000\n# CLR.F [Ra], #imm5, Size\n:clr.f [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x4 & R0608 & imm5 & SIZE5\n{\n\tbuild SIZE5;\n\t*[ram]:4 R0608 = SIZE5 & ~(1 << imm5);\n}\n\n\n#TODO the manual does not specify\n# N negative\n# Z zero\n# V overflow\n# C carry\nmacro Flags(r0, r1) {\n local val:4 = r0 - r1;\n $(N) = val s< 0;\n $(Z) = r0 == r1;\n $(V) = r0[31,1] | r1[31,1];\n\t$(C) = r0 < r1;\n}\n\n# 3: 16-bit 6400|0b110010000000000 9a00|0b1001101000000000\n# COMP Rb, Ra, cc_A\n:comp R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x2 & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tFlags(R0608, R0305);\n}\n\n\n# 1: 16-bit 2400|0b10010000000000 da04|0b1101101000000100\n# COMP.F Rb, [Ra], Size\n:comp.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x2 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\tbuild SIZE1;\n\tFlags(R0608, SIZE1);\n}\n\n\n# 4: 16-bit 8400|0b1000010000000000 7a00|0b111101000000000\n# COMP.I Ra, #imm6\n:comp.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x2 & imm6\n{\n\tFlags(R0608, imm6);\t\n}\n\n\n# 2: 16-bit 4400|0b100010000000000 ba00|0b1011101000000000\n# COMP.PI Ra, [#offset6]\n:comp.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x2 & R0608 & offset6\n{\n\tbuild offset6;\n\tFlags(R0608, offset6);\n}\n\n\n# 0: 16-bit 0800|0b100000000000 f000|0b1111000000000000\n#\n:copy DST, SRC, CNC, CNT03, SIZE0 is PCPMode=1 & addrmode=0 & pcp_op1212=0x0 & pcp_op1111=0x1 & DST & SRC & CNC & CNT03 & SIZE0\n{\n}\n\n#TODO DEBUG SLEIGH instead\ndefine pcodeop pcpdebug;\n\n# 7: 16-bit fc00|0b1111110000000000 0030|0b110000\n# DEBUG EDA, DAC, RTA, SDB, cc_B\n:debug DAC, RTA, EDA, SDB, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x7 & DAC & RTA & EDA & SDB & CONDCB & pcp_op0405=0x0\n{\n\tif (CONDCB == 0) goto inst_next;\n\tpcpdebug();\t\n}\n\n\n# 6: 16-bit c000|0b1100000000000000 3e07|0b11111000000111\n# DINIT , Rb, Ra\n:dinit \"<\"^R0^\">\", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x0 & R0 & R0608 & R0305 & pcp_op0002=0x0\n{\n\tR0 = 0;\n\t$(V) = R0305 == 0;\n\t$(Z) = (R0608 == 0) && (R0305 != 0);\n}\n\n\n# 6: 16-bit c200|0b1100001000000000 3c07|0b11110000000111\n# DSTEP , Rb, Ra\n:dstep \"<\"^R0^\">\", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x1 & R0 & R0608 & R0305 & pcp_op0002=0x0\n{\n\t#TODO flags Z not sure\n\tR0 = (R0 << 8) + (R0608 >> 24);\n\tR0608 = (R0608 << 8) + (R0 / R0305);\n\tR0 = R0 % R0305;\n\t$(Z) = R0 == 0;\n}\n\n\n# 0: 16-bit 1000|0b1000000000000 e870|0b1110100001110000\n#\n:exit ST, EC, INT, EP, CONDCAB is PCPMode=1 & addrmode=0 & pcp_op1212=0x1 & pcp_op1111=0x0 & ST & EC & INT & EP & CONDCAB & pcp_op0406=0x0\n{\n}\n\n\n# 3: 16-bit 7a00|0b111101000000000 8400|0b1000010000000000\n# INB Rb, Ra, cc_A\n:inb R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xd & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = (R0608 & ~(1 << R0305[0,5])) | zext($(C) << R0305[0,5]);\n}\n\n\n# 4: 16-bit 9a00|0b1001101000000000 6420|0b110010000100000\n# INB.I Ra, #imm5\n:inb.i R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xd & pcp_op0505=0x0 & imm5\n{\n\tR0608 = (R0608 & ~(1 << imm5)) | zext($(C) << imm5);\n}\n\nimm6pc: reloc is PCPMode=1 & pcp_op0005 [ reloc = inst_start + pcp_op0005; ] { export *[ram]:4 reloc; }\nimm10pc: reloc is PCPMode=1 & pcp_op0009 [ reloc = inst_start + pcp_op0009; ] { export *[ram]:4 reloc; }\nimm16abs: pcp_op1631 is PCPMode=1 & pcp_op1631 { export *[ram]:4 pcp_op1631; }\n\n# 7: 16-bit e400|0b1110010000000000 1800|0b1100000000000\n# JC offset6, cc_B\n:jc imm6pc, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x1 & imm6pc & CONDCB\n{\n\tif (CONDCB == 0) goto inst_next;\n\tgoto imm6pc;\n}\n\n\n# 7: 32-bit e800|0b1110100000000000 143f|0b1010000111111\n# JC.A #address16, cc_B\n:jc.a imm16abs, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x2 & CONDCB & pcp_op0005=0 ; imm16abs\n{\n\tif (CONDCB == 0) goto inst_next;\n\tgoto imm16abs;\n}\n\n\n# 7: 16-bit f000|0b1111000000000000 0c07|0b110000000111\n# JC.I Ra, cc_B\n:jc.i [R0305], CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x4 & R0305 & CONDCB & pcp_op0002=0x0\n{\n\tif (CONDCB == 0) goto inst_next;\n\tlocal tmp:4 = inst_start + zext(R0305[0,16]);\n\tgoto [tmp];\n}\n\n\n# 7: 16-bit f400|0b1111010000000000 0807|0b100000000111\n# JC.IA Ra, cc_B\n:jc.ia [R0305], CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x5 & R0305 & CONDCB & pcp_op0002=0x0\n{\n\tif (CONDCB == 0) goto inst_next;\n\tlocal tmp:4 = zext(R0305[0,16]);\n\tgoto [tmp];\n}\n\n\n# 7: 16-bit e000|0b1110000000000000 1c00|0b1110000000000\n# JL offset10\n:jl imm10pc is PCPMode=1 & addrmode=7 & pcp_op1012=0x0 & imm10pc\n{\n\tgoto imm10pc;\n}\n\n\n# 1: 16-bit 3200|0b11001000000000 cc04|0b1100110000000100\n# LD.F Rb, [Ra], Size\n:ld.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x9 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\tR0608 = SIZE1;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 4: 16-bit 9800|0b1001100000000000 6600|0b110011000000000\n# LD.I Ra, #imm6\n:ld.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xc & imm6\n{\n\tR0608 = imm6;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 5: 16-bit b400|0b1011010000000000 4800|0b100100000000000\n# LD.IF [Ra], #offset5, Size\n:ld.if [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x5 & R0608 & imm5 & SIZE5\n{\n\tR0608 = SIZE5 + imm5;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 3: 16-bit 7200|0b111001000000000 8c00|0b1000110000000000\n# LD.P Rb, [Ra], cc_A\n:ld.p R0608, [R0305], CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x9 & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tlocal tmp:4 = zext($(DPTR) << 6) + zext(R0305[0,6]);\n\tR0608 = *[ram]:4 tmp;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 2: 16-bit 5200|0b101001000000000 ac00|0b1010110000000000\n# LD.PI Ra, [#offset6]\n:ld.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x9 & R0608 & offset6\n{\n\tR0608 = offset6;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 4: 32-bit 9200|0b1001001000000000 6c3f|0b110110000111111\n# LDL.IL Ra, #imm16\n:ldl.il R0608, imm16 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x9 & pcp_op0005=0x0 ; imm16\n{\n\t#TODO are flags correct\n\tR0608[0,16] = imm16[0,16];\n\t$(N) = R0608[0,16] s< 0;\n\t$(Z) = R0608[0,16] == 0;\t\n}\n\n\n# 4: 32-bit 9000|0b1001000000000000 6e3f|0b110111000111111\n#\n:ldl.iu R0608, imm16 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x8 & pcp_op0005=0x0 ; imm16\n{\n\t#TODO are flags correct\n\tR0608[16,16] = imm16[0,16];\n\t$(N) = R0608[16,16] s< 0;\n\t$(Z) = R0608[16,16] == 0;\t\n}\n\n\n# 2: 16-bit 4800|0b100100000000000 b600|0b1011011000000000\n# MCLR.PI Ra, [#offset6]\n:mclr.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0005 & pcp_op0912=0x4 & R0608 & offset6\n{\n\tR0608 = R0608 & offset6;\n\tlocal tmp:4 = zext($(DPTR) << 6) + pcp_op0005;\n\t*[ram]:4 tmp = R0608;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\t\n}\n\n\n# 6: 16-bit c400|0b1100010000000000 3a07|0b11101000000111\n# MINIT , Rb, Ra\n:minit \"<\"^R0^\">\", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x2 & R0 & R0608 & R0305 & pcp_op0002=0x0\n{\n\tR0 = 0;\n\t$(Z) = (R0608 == 0) || (R0305 == 0);\n}\n\n\n# 3: 16-bit 7800|0b111100000000000 8600|0b1000011000000000\n# MOV Rb, Ra, cc_A\n:mov R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xc & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = R0305;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\t\n}\n\n\n# 2: 16-bit 4c00|0b100110000000000 b200|0b1011001000000000\n# MSET.PI Ra, [#offset6]\n:mset.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0005 & pcp_op0912=0x6 & R0608 & offset6\n{\n\tR0608 = R0608 | offset6;\n\tlocal tmp:4 = zext($(DPTR) << 6) + pcp_op0005;\n\t*[ram]:4 tmp = R0608;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\t\n}\n\n\n# 6: 16-bit c600|0b1100011000000000 3807|0b11100000000111\n#\n:mstep.l R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x3 & R0608 & R0305 & pcp_op0002=0x0\n{\n}\n\n\n# 6: 16-bit c800|0b1100100000000000 3607|0b11011000000111\n#\n:mstep.u R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x4 & R0608 & R0305 & pcp_op0002=0x0\n{\n}\n\n\n# 3: 16-bit 6600|0b110011000000000 9800|0b1001100000000000\n# NEG Rb, Ra, cc_A\n:neg R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x3 & R0608 & R0305 & CONDCA\n{\n\t#TODO flags\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = -R0305;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n\t$(V) = R0608[31,1];\n\t$(C) = R0305[31,1];\n}\n\n\n# 0: 16-bit 0000|0b0 ffff|0b1111111111111111\n# NOP\n:nop is PCPMode=1 & addrmode=0 & pcp_op1212=0x0 & pcp_op1111=0x0 & pcp_op0010=0x0\n{\n\tlocal NOP:1 = 0;\n\tNOP = NOP;\n}\n\n\n# 3: 16-bit 6800|0b110100000000000 9600|0b1001011000000000\n# NOT Rb, Ra, cc_A\n:not R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x4 & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = ~R0305;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 3: 16-bit 6e00|0b110111000000000 9000|0b1001000000000000\n# OR Rb, Ra, cc_A\n:or R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x7 & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = R0608 | R0305;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 1: 16-bit 2e00|0b10111000000000 d004|0b1101000000000100\n# OR.F Rb, [Ra], Size\n:or.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x7 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\tR0608 = R0608 | SIZE1;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 2: 16-bit 4e00|0b100111000000000 b000|0b1011000000000000\n# OR.PI Ra, [#offset6]\n:or.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x7 & R0608 & offset6\n{\n\tR0608 = R0608 | offset6;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 3: 16-bit 7c00|0b111110000000000 8200|0b1000001000000000\n# PRI Rb, Ra, cc_A\n:pri R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xe & R0608 & R0305 & CONDCA\n{\n\t#TODO pcodeop or this? also double check\n\tif (CONDCA == 0) goto inst_next;\n\tlocal index:4 = 0;\n\tlocal tmp:4 = R0305;\n\tif (tmp == 0) goto ;\n \n tmp = tmp >> 2;\n\tindex = index + 1;\n\tif (tmp != 0) goto ;\n \n R0608 = zext(0x20 * (index == 0)) + (index * zext(index != 0));\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 4: 16-bit 8e00|0b1000111000000000 7020|0b111000000100000\n# RL Ra, #imm5\n:rl R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x7 & pcp_op0505=0x0 & imm5\n{\n\t#TODO double check\n\tlocal tmp:4 = R0608;\n\tR0608 = R0608 << imm5;\n\t$(C) = (tmp & (1 << (32 - imm5))) != 0;\n\ttmp = tmp >> (32 - imm5);\n\tR0608 = tmp | R0608;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 4: 16-bit 8c00|0b1000110000000000 7220|0b111001000100000\n# RR Ra, #imm5\n:rr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x6 & pcp_op0505=0x0 & imm5\n{\n\t#TODO double check\n\tlocal tmp:4 = R0608;\n\tR0608 = R0608 >> imm5;\n\ttmp = tmp << (32 - imm5);\n\tR0608 = tmp | R0608;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 4: 16-bit 9400|0b1001010000000000 6a20|0b110101000100000\n# SET Ra, #imm5\n:set R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xa & pcp_op0505=0x0 & imm5\n{\n\tR0608 = R0608 | (1 << imm5);\n}\n\n\n# 5: 16-bit ac00|0b1010110000000000 5000|0b101000000000000\n# SET.F [Ra], #imm5, Size\n:set.f [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x3 & R0608 & imm5 & SIZE5\n{\n\tbuild SIZE5;\n\t*[ram]:4 R0608 = SIZE5 | (1 << imm5);\n}\n\n\n# 4: 16-bit 8a00|0b1000101000000000 7420|0b111010000100000\n# SHL Ra, #imm5\n:shl R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x5 & pcp_op0505=0x0 & imm5\n{\n\t$(C) = (R0608 & (1 << (32 - imm5))) != 0;\n\tR0608 = R0608 << imm5;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 4: 16-bit 8800|0b1000100000000000 7620|0b111011000100000\n# SHR Ra, #imm5\n:shr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x4 & pcp_op0505=0x0 & imm5\n{\n\tR0608 = R0608 >> imm5;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 1: 16-bit 3400|0b11010000000000 ca04|0b1100101000000100\n# ST.F Rb, [Ra], Size\n:st.f SIZE1W is PCPMode=1 & addrmode=0x1 & pcp_op0912=0xa & pcp_op0202=0x0 & SIZE1W\n{\n\tbuild SIZE1W;\n}\n\n\n# 5: 16-bit b800|0b1011100000000000 4400|0b100010000000000\n# ST.IF [Ra], #offset5, Size\n:st.if SIZE5W is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x6 & SIZE5W\n{\n\tbuild SIZE5W;\n}\n\n\n# 3: 16-bit 7400|0b111010000000000 8a00|0b1000101000000000\n# ST.P Rb, [Ra], cc_A\n:st.p R0608, [R0305], CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xa & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tlocal tmp:4 = zext($(DPTR) << 6) + zext(R0305[0,6]);\n\t*[ram]:4 tmp = R0608;\t\n}\n\n\n# 2: 16-bit 5400|0b101010000000000 aa00|0b1010101000000000\n# ST.PI Rb, [#offset6]\n:st.pi offset6W is PCPMode=1 & addrmode=2 & pcp_op0912=0xa & offset6W\n{\n\tbuild offset6W;\n}\n\n\n# 3: 16-bit 6200|0b110001000000000 9c00|0b1001110000000000\n# SUB Rb, Ra, cc_A\n:sub R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x1 & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = R0608 - R0305;\n\tFlags(R0608, R0305);\n}\n\n\n# 1: 16-bit 2200|0b10001000000000 dc04|0b1101110000000100\n# SUB.F Rb, [Ra], Size\n:sub.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x1 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\tbuild SIZE1;\n\tlocal tmp:4 = SIZE1;\n\tFlags(R0608, tmp);\n\tR0608 = R0608 - tmp;\n}\n\n\n# 4: 16-bit 8200|0b1000001000000000 7c00|0b111110000000000\n# SUB.I Ra, #imm6\n:sub.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x1 & imm6\n{\n\tFlags(R0608, imm6);\n\tR0608 = R0608 - imm6;\n}\n\n\n# 2: 16-bit 4200|0b100001000000000 bc00|0b1011110000000000\n# SUB.PI Ra, [#offset6]\n:sub.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x1 & R0608 & offset6\n{\n\tFlags(R0608, offset6);\n\tR0608 = R0608 - offset6;\n}\n\n\n# 1: 16-bit 3600|0b11011000000000 c804|0b1100100000000100\n# XCH.F Rb, [Ra], Size\n:xch.f SIZE1RW is PCPMode=1 & addrmode=0x1 & pcp_op0912=0xb & pcp_op0202=0x0 & R0608 & SIZE1RW\n{\n\tbuild SIZE1RW;\t\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 2: 16-bit 5600|0b101011000000000 a800|0b1010100000000000\n# XCH.PI Ra, [#offset6]\n:xch.pi offset6RW is PCPMode=1 & addrmode=2 & pcp_op0912=0xb & R0608 & offset6RW\n{\n\tbuild offset6RW;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 3: 16-bit 7000|0b111000000000000 8e00|0b1000111000000000\n# XOR Rb, Ra, cc_A\n:xor R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x8 & R0608 & R0305 & CONDCA\n{\n\tif (CONDCA == 0) goto inst_next;\n\tR0608 = R0608 ^ R0305;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 1: 16-bit 3000|0b11000000000000 ce04|0b1100111000000100\n# XOR.F Rb, [Ra], Size\n:xor.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x8 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1\n{\n\tR0608 = R0608 ^ SIZE1;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n\n\n# 2: 16-bit 5000|0b101000000000000 ae00|0b1010111000000000\n# XOR.PI Ra, [#offset6]\n:xor.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x8 & R0608 & offset6\n{\n\tR0608 = R0608 ^ offset6;\n\t$(N) = R0608 s< 0;\n\t$(Z) = R0608 == 0;\n}\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.pspec", "content": "\n\n\n \n \n \n \n \n\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.sinc", "content": "\ndefine alignment=2;\ndefine space ram type=ram_space size=4 default;\ndefine space register type=register_space size=4;\n\n#TODO This is probably in the spec\ndefine register offset=0x00 size=4 contextreg;\ndefine context contextreg\n PCPMode=(0,0)\n;\n\n# Data General Purpose Registers\ndefine register offset=0xFF00 size=8 [ e0 e2 e4 e6 e8 e10 e12 e14 ];\ndefine register offset=0xFF00 size=4 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];\n\n# Address General Purpose Registers\ndefine register offset=0xFF80 size=8 [ p0 p2 p4 p6 p8 p10 p12 p14 ];\ndefine register offset=0xFF80 size=4 [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ];\n\n# Program Counter\ndefine register offset=0xFE08 size=4 [ PC ];\n\n# Program Status Word Register\ndefine register offset=0xFE04 size=4 [ PSW ];\n\n#TODO bitrange vs define vs context\n# define bitrange PSW_USB=PSW[24,8]\n# PSW_C=PSW[31,1]\n# PSW_V=PSW[30,1]\n# PSW_SV=PSW[29,1]\n# PSW_AV=PSW[28,1]\n# PSW_SAV=PSW[27,1]\n# PSW_S=PSW[14,1]\n# PSW_PRS=PSW[12,2]\n# PSW_IO=PSW[10,2]\n# PSW_IS=PSW[9,1]\n# PSW_GW=PSW[8,1]\n# PSW_CDE=PSW[7,1]\n# PSW_CDC=PSW[0,7];\n@define PSW_USB \"PSW[24,8]\"\n@define PSW_C \"PSW[31,1]\"\n@define PSW_FS \"PSW[31,1]\"\n@define PSW_V \"PSW[30,1]\"\n@define PSW_FI \"PSW[30,1]\"\n@define PSW_SV \"PSW[29,1]\"\n@define PSW_FV \"PSW[29,1]\"\n@define PSW_AV \"PSW[28,1]\"\n@define PSW_FZ \"PSW[28,1]\"\n@define PSW_SAV \"PSW[27,1]\"\n@define PSW_FU \"PSW[27,1]\"\n@define PSW_FX \"PSW[26,1]\"\n@define PSW_RM \"PSW[24,2]\"\n@define PSW_S \"PSW[14,1]\"\n@define PSW_PRS \"PSW[12,2]\"\n@define PSW_IO \"PSW[10,2]\"\n@define PSW_IS \"PSW[9,1]\"\n@define PSW_GW \"PSW[8,1]\"\n@define PSW_CDE \"PSW[7,1]\"\n@define PSW_CDC \"PSW[0,7]\"\n\n# Previous Context Information and Pointer Register\ndefine register offset=0xFE00 size=4 [ PCXI ];\n# define context PCXI\n# PCXO=(0,15)\n# PCXS=(16,19)\n# UL=(20,20)\n# PIE=(21,21)\n# PCPN=(22,29)\n# ;\n\n# Interrupt Stack Pointer Register\ndefine register offset=0xFE28 size=4 [ ISP ];\n\n# System Control Register\ndefine register offset=0xFE14 size=4 [ SYSCON ];\n# define context SYSCON\n# FCDSF=(0,0)\n# PROTEN=(1,1)\n# TPROTEN=(2,2)\n# IS=(3,3)\n# TS=(4,4)\n# U1_IED=(16,16)\n# U1_IOS=(17,17)\n# ;\n\n# CPU Identification Register\ndefine register offset=0xFE18 size=4 [ CPU_ID ];\n# define context CPU_ID\n# MOD_REV=(0,7)\n# MOD_32B=(8,15)\n# MOD=(16,31)\n# ;\n\n# Core Identification Register\ndefine register offset=0xFE1C size=4 [ CORE_ID ];\n\n\n# Compatibility Mode Register\ndefine register offset=0x9400 size=4 [ COMPAT ];\n\n# SIST Mode Access Control Register\ndefine register offset=0x900C size=4 [ SMACON ];\n\n# Free CSA List Head Pointer Register\ndefine register offset=0xFE38 size=4 [ FCX ];\n# define context FCX\n# FCXO=(0,15)\n# FCXS=(16,19)\n# ;\n\n# Free CSA List Limit Pointer Register\ndefine register offset=0xFE3C size=4 [ LCX ];\n# define context LCX\n# LCXO=(0,15)\n# LCXS=(16,19)\n# ;\n\n# ICU Interrupt Control Register\ndefine register offset=0xFE2C size=4 [ ICR ];\ndefine register offset=0xFE2E size=1 [ PIPN ];\n# define context ICR\n# CCPN=(0,7)\n# IE=(15,15)\n# PIPN=(16,23)\n# ;\n@define ICR_PIPN \"ICR[16,8]\"\n@define ICR_IE \"ICR[15,1]\"\n@define ICR_CCPN \"ICR[0,8]\"\n\n# Base Interrupt Vector Table Pointer\ndefine register offset=0xFE20 size=4 [ BIV ];\n# define context BIV\n# VSS=(0,0)\n# ;\n\n# Base Trap Vector Table Pointer\ndefine register offset=0xFE24 size=4 [ BTV ];\n\n# Program Synchronous Error Trap Register\ndefine register offset=0x9200 size=4 [ PSTR ];\n\n# Data Synchronous Error Trap Register\ndefine register offset=0x9010 size=4 [ DSTR ];\n\n# Data Asynchronous Error Trap Register\ndefine register offset=0x9018 size=4 [ DATR ];\n\n# Data Error Address Register\ndefine register offset=0x901C size=4 [ DEADD ];\n\n# Program Integrity Error Trap Register\ndefine register offset=0x9214 size=4 [ PIETR ];\n\n# Program Integrity Error Address Register\ndefine register offset=0x9210 size=4 [ PIEAR ];\n\n# Data Integrity Error Trap Register\ndefine register offset=0x9024 size=4 [ DIETR ];\n\n# Data Integrity Error Address Register\ndefine register offset=0x9020 size=4 [ DIEAR ];\n\n# Programmable Memory Access Register\ndefine register offset=0x8100 size=4 [ PMA0 PMA1 PMA2 ];\n\n# Program Memory Configuration Registers\ndefine register offset=0x9204 size=4 [ PCON1 PCON2 PCON0 ];\n\n# Data Memory Configuration Registers\ndefine register offset=0x9040 size=4 [ DCON0 ];\ndefine register offset=0x9008 size=4 [ DCON1 ];\ndefine register offset=0x9000 size=4 [ DCON2 ];\n\n# Data Protection Range Register Lower & Upper Bound\ndefine register offset=0xC000 size=4 [ DPR0_L DPR0_U DPR1_L DPR1_U DPR2_L DPR2_U DPR3_L DPR3_U DPR4_L DPR4_U DPR5_L DPR5_U DPR6_L DPR6_U DPR7_L DPR7_U DPR8_L DPR8_U DPR9_L DPR9_U DPR10_L DPR10_U DPR11_L DPR11_U DPR12_L DPR12_U DPR13_L DPR13_U DPR14_L DPR14_U DPR15_L DPR15_U ];\n\n# Code Protection Range Register Lower & Upper Bound\ndefine register offset=0xD000 size=4 [ CPR0_L CPR0_U CPR1_L CPR1_U CPR2_L CPR2_U CPR3_L CPR3_U CPR4_L CPR4_U CPR5_L CPR5_U CPR6_L CPR6_U CPR7_L CPR7_U CPR8_L CPR8_U CPR9_L CPR9_U CPR10_L CPR10_U CPR11_L CPR11_U CPR12_L CPR12_U CPR13_L CPR13_U CPR14_L CPR14_U CPR15_L CPR15_U ];\n\n# Data Protection Read Enable Set Configuration Register\ndefine register offset=0xE010 size=4 [ DPRE_0 DPRE_1 DPRE_2 DPRE_3 ];\n\n# Data Protection Write Enable Set Configuration Register\ndefine register offset=0xE020 size=4 [ DPWE_0 DPWE_1 DPWE_2 DPWE_3 ];\n\n# Code Protection Execute Enable Set Configuration Register\ndefine register offset=0xE000 size=4 [ CPXE_0 CPXE_1 CPXE_2 CPXE_3 ];\n\n# Temporal Protect System (TPS) Timer Register\ndefine register offset=0xE404 size=4 [ TPS_TIMER0 TPS_TIMER1 TPS_TIMER2 ];\n\n# TPS Control Register\ndefine register offset=0xE400 size=4 [ TPS_CON ];\n# define context TPS_CON\n# TEXP0=(0,0)\n# TEXP1=(1,1)\n# TEXP2=(2,2)\n# TTRAP=(16,16)\n# ;\n\n# FPU Trap Control Register\ndefine register offset=0xA000 size=4 [ FPU_TRAP_CON ];\n# define context FPU_TRAP_CON\n# TST=(0,0)\n# TCL=(1,1)\n# RM=(8,9)\n# FXE=(18,18)\n# FUE=(19,19)\n# FZE=(20,20)\n# FVE=(21,21)\n# FIE=(22,22)\n# FX=(26,26)\n# FU=(27,27)\n# FZ=(28,28)\n# FV=(29,29)\n# FI=(30,30)\n# ;\n\n# FPU Trapping Instruction Program Counter\ndefine register offset=0xA004 size=4 [ FPU_TRAP_PC ];\n\n# FPU Trapping Instruction Opcode Register\ndefine register offset=0xA008 size=4 [ FPU_TRAP_OPC ];\n# define context FPU_TRAP_OPC\n# OPC=(0,7)\n# FMT=(8,8)\n# DREG=(16,19)\n# ;\n\n# FPU Trapping Instruction Operand SRC1 Register\ndefine register offset=0xA010 size=4 [ FPU_TRAP_SRC1 FPU_TRAP_SRC2 FPU_TRAP_SRC3 ];\n\n\n\n# Core Debug Controller (CDC) Registers\n# Debug Status Register\ndefine register offset=0xFD00 size=4 [ DBGSR ];\n# define context DBGSR\n# DE=(0,0)\n# HALT=(1,2)\n# SIH=(3,3)\n# SUSP=(4,4)\n# PREVSUSP=(6,6)\n# PEVT=(7,7)\n# EVTSRC=(8,12)\n# ;\n@define DBGSR_EVTSRC \"DBGSR[8,5]\"\n@define DBGSR_PEVT \"DBGSR[7,1]\"\n@define DBGSR_PREVSUSP \"DBGSR[6,1]\"\n@define DBGSR_SUSP \"DBGSR[4,1]\"\n@define DBGSR_SIH \"DBGSR[3,1]\"\n@define DBGSR_HALT \"DBGSR[1,2]\"\n@define DBGSR_DE \"DBGSR[0,1]\"\n\n# External Event Register\ndefine register offset=0xFD08 size=4 [ EXEVT ];\n# define context EXEVT\n# EVTA=(0,2)\n# BBM=(3,3)\n# BOD=(4,4)\n# SUSP=(5,5)\n# CNT=(6,7)\n# ;\n\n# Core Register Access Event Register\ndefine register offset=0xFD0C size=4 [ CREVT ];\n# define context CREVT\n# CREVT_EVTA=(0,2)\n# CREVT_BBM=(3,3)\n# CREVT_BOD=(4,4)\n# CREVT_SUSP=(5,5)\n# CREVT_CNT=(6,7)\n# ;\n\n# Software Debug Event Register\ndefine register offset=0xFD10 size=4 [ SWEVT ];\n# define context SWEVT\n# SWEVT_EVTA=(0,2)\n# SWEVT_BBM=(3,3)\n# SWEVT_BOD=(4,4)\n# SWEVT_SUSP=(5,5)\n# SWEVT_CNT=(6,7)\n# ;\n\n# Trigger Accumulator Register\ndefine register offset=0xFD30 size=4 [ TRIG_ACC ];\n# define context TRIC_ACC\n# T0=(0,0)\n# T1=(1,1)\n# T2=(2,2)\n# T3=(3,3)\n# T4=(4,4)\n# T5=(5,5)\n# T6=(6,6)\n# T7=(7,7)\n# ;\n\n# Debug Monitor Start Address Register\ndefine register offset=0xFD40 size=4 [ DMS ];\n\n# Debug Context Save Area Pointer Register\ndefine register offset=0xFD44 size=4 [ DCX ];\n\n# Debug Trap Control Register\ndefine register offset=0xFD48 size=4 [ DBGTCR ];\n\n# Application Space Identifier Register\ndefine register offset=0x8004 size=4 [ TASK_ASI ];\n\n# Software Breakpoint Service Request Control\n#define register offset=0xFFB0 size=4 [ SBSRC3 SBSRC2 SBSRC1 SBSRC0 ];\n\n# Trigger Event Configuration / Address Register\ndefine register offset=0xF000 size=4 [ TR0EVT TR0ADR TR1EVT TR1ADR TR2EVT TRA2DR TR3EVT TR3ADR TR4EVT TR4ADR TR5EVT TR5ADR TR6EVT TR6ADR TR7EVT TR7ADR ];\n# define context TRxEVT\n# EVTA=(0,2)\n# BBM=(3,3)\n# BOD=(4,4)\n# SUSP=(5,5)\n# CNT=(6,7)\n# TYP=(12,12)\n# RNG=(13,13)\n# ASI_EN=(15,15)\n# ASI=(16,20)\n# AST=(27,27)\n# ALD=(28,28)\n# ;\n\n\n# Counter Control Register\ndefine register offset=0xFC00 size=4 [ CCTRL ];\n# define context CCTRL\n# CM=(0,0)\n# CE=(1,1)\n# M1=(2,4)\n# M2=(5,7)\n# M3=(8,10)\n# ;\n\n# CPU Clock Cycle Count Register\ndefine register offset=0xFC04 size=4 [ CCNT ];\n\n# Instruction Count Register\ndefine register offset=0xFC08 size=4 [ ICNT ];\n\n# Mult-Count Register\ndefine register offset=0xFC0C size=4 [ M1CNT M2CNT M3CNT ];\n\n\n\n\n\ndefine token instr (16)\n op0003=(0, 3)\n op0005=(0, 5)\n op0006=(0, 6)\n op0007=(0, 7)\n op0404=(4, 4)\n op0405=(4, 5)\n op0407=(4, 7)\n op0606=(6, 6)\n op0607=(6, 7)\n op0707=(7, 7)\n op0810=(8, 10)\n Rd0811=(8, 11)\n Ra0811=(8, 11)\n Re0811=(8, 11)\n Ree0811=(8, 11)\n Reo0811=(8, 11)\n ReN0811=(8, 11)\n op0811=(8, 11)\n Rp0811=(8, 11)\n Rpe0811=(8, 11)\n Rpo0811=(8, 11)\n op0815=(8, 15)\n sop0815=(8, 15) signed\n op1111=(11, 11)\n Rd1215=(12, 15)\n op1215=(12, 15)\n sop1215=(12, 15) signed\n Ra1215=(12, 15)\n Rpe1215=(12, 15)\n Rpo1215=(12, 15)\n op1515=(15, 15)\n;\n\ndefine token instr2 (16)\n op1617=(0, 1)\n op1620=(0, 4)\n sop1620=(0, 4) signed\n op1621=(0, 5)\n op1622=(0, 6)\n op1623=(0, 7)\n op1627=(0, 11)\n sop1627=(0, 11) signed\n sop1630=(0, 14) signed\n op1631=(0, 15)\n op1819=(2, 3)\n op1823=(2, 7)\n op1827=(2, 11)\n op2020=(4, 4)\n op2023=(4, 7)\n op2027=(4, 11)\n op2122=(5, 6)\n op2123=(5, 7)\n op2127=(5, 11)\n op2131=(5, 15)\n op2225=(6, 9)\n op2227=(6, 11)\n sop2227=(6, 11) signed\n op2327=(7, 11)\n Rd2427=(8, 11)\n Re2427=(8, 11)\n Ree2427=(8, 11)\n Reo2427=(8, 11)\n op2627=(10, 11)\n Rd2831=(12, 15)\n Ra2831=(12, 15)\n Re2831=(12, 15)\n Ree2831=(12, 15)\n Reo2831=(12, 15)\n op2831=(12, 15)\n sop2831=(12, 15) signed\n op3131=(15, 15)\n;\n\n\n\nattach variables [ Rd0811 Rd1215 Rd2427 Rd2831 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];\nattach variables [ Re0811 Re2427 Re2831 ] [ e0 _ e2 _ e4 _ e6 _ e8 _ e10 _ e12 _ e14 _ ];\nattach variables [ ReN0811 ] [ e2 _ e4 _ e6 _ e8 _ e10 _ e12 _ e14 _ e0 _ ];\nattach variables [ Ree0811 Ree2427 Ree2831 ] [ d0 _ d2 _ d4 _ d6 _ d8 _ d10 _ d12 _ d14 _];\nattach variables [ Reo0811 Reo2427 Reo2831 ] [ d1 _ d3 _ d5 _ d7 _ d9 _ d11 _ d13 _ d15 _];\n\nattach variables [ Ra0811 Ra1215 Ra2831 ] [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ];\nattach variables [ Rp0811 ] [ p0 _ p2 _ p4 _ p6 _ p8 _ p10 _ p12 _ p14 _ ];\nattach variables [ Rpe0811 Rpe1215 ] [ a0 _ a2 _ a4 _ a6 _ a8 _ a10 _ a12 _ a14 _];\nattach variables [ Rpo0811 Rpo1215 ] [ a1 _ a3 _ a5 _ a7 _ a9 _ a11 _ a13 _ a15 _];\n\n\n\n\n# 0 MMU\n# * 0 VAF\n# * 1 VAP\n# 1 Internal Protection Traps\n# * 1 PRIV\n# * 2 MPR\n# * 3 MPW\n# * 4 MPX\n# * 5 MPP\n# * 6 MPN\n# * 7 GRWP\n# 2 Instruction Errors\n# * 1 IOPC\n# * 2 UOPC\n# * 3 OPD\n# * 4 ALN\n# * 5 MEM\n# 3 Context Management\n# * 1 FCD\n# * 2 CDO\n# * 3 CDU\n# * 4 FCU\n# * 5 CSU\n# * 6 CTYP\n# * 7 NEST\n# 4 System Bus and Peripheral Errors\n# * 1 PSE\n# * 2 DSE\n# * 3 DAE\n# * 4 CAE\n# * 5 PIE\n# * 6 DIE\n# * 7 TAE\n# 5 Assertion Traps\n# * 1 OVF\n# * 2 SOVF\n# 6 System Call\n# * 0-255 SYS\n# 7 Non-Maskable Interrupt\n# * 0 NMI\ndefine pcodeop trap;\n\n\ndefine pcodeop cache_address_ivld;\ndefine pcodeop cache_address_wb;\ndefine pcodeop cache_address_wi;\ndefine pcodeop cache_index_ivld;\ndefine pcodeop cache_index_wb;\ndefine pcodeop cache_index_wi;\ndefine pcodeop round16;\ndefine pcodeop crc32;\n\n# float\ndefine pcodeop denorm_to_zero;\ndefine pcodeop ieee754_round;\ndefine pcodeop ieee754_32bit_format;\n\ndefine pcodeop coprocessor;\n\ndefine pcodeop debug;\ndefine pcodeop dsync;\ndefine pcodeop isync;\ndefine pcodeop tlbdemap;\ndefine pcodeop tlbflusha;\ndefine pcodeop tlbflushb;\ndefine pcodeop tlbmap;\ndefine pcodeop tlbprobea;\ndefine pcodeop tlbprobei;\ndefine pcodeop wait;\n\n\n@if defined(TRICORE_VERBOSE)\n@else\ndefine pcodeop bmerge;\ndefine pcodeop bsplit;\ndefine pcodeop load_lower_context;\ndefine pcodeop load_upper_context;\ndefine pcodeop store_lower_context;\ndefine pcodeop store_upper_context;\n@endif\n\n\n\n#TODO \ndefine pcodeop reverse16;\n# macro reverse16(src, dst) {\n# dst[0,1]=src[15,1];\n# dst[1,1]=src[14,1];\n# dst[2,1]=src[13,1];\n# dst[3,1]=src[12,1];\n# dst[4,1]=src[11,1];\n# dst[5,1]=src[10,1];\n# dst[6,1]=src[9,1];\n# dst[7,1]=src[8,1];\n# dst[8,1]=src[7,1];\n# dst[9,1]=src[6,1];\n# dst[10,1]=src[5,1];\n# dst[11,1]=src[4,1];\n# dst[12,1]=src[3,1];\n# dst[13,1]=src[2,1];\n# dst[14,1]=src[1,1];\n# dst[15,1]=src[0,1];\n# }\n\nmacro overflowflagsd(r) {\n $(PSW_V) = r[63,1];\n $(PSW_SV) = $(PSW_V) | $(PSW_SV);\n $(PSW_AV) = r[63,1] ^ r[62,1];\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\nmacro overflowflagsww(r1, r0) {\n $(PSW_V) = r1[31,1] | r0[31,1];\n $(PSW_SV) = $(PSW_V) | $(PSW_SV);\n $(PSW_AV) = (r1[31,1] ^ r1[30,1]) | (r0[31,1] ^ r0[30,1]);\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\nmacro advoverflowflagsww(r1, r0) {\n $(PSW_V) = 0;\n $(PSW_AV) = (r1[31,1] ^ r1[30,1]) | (r0[31,1] ^ r0[30,1]);\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\nmacro advoverflowflags(r) {\n $(PSW_V) = 0;\n $(PSW_AV) = r[31,1] ^ r[30,1];\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\nmacro overflowflags(r) {\n $(PSW_V) = r[31,1];\n $(PSW_SV) = $(PSW_V) | $(PSW_SV);\n $(PSW_AV) = r[31,1] ^ r[30,1];\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\nmacro overflowflagsh(r1, r0) {\n $(PSW_V) = r1[15,1] | r0[15,1];\n $(PSW_SV) = $(PSW_V) | $(PSW_SV);\n $(PSW_AV) = (r1[15,1] ^ r1[14,1]) | (r0[15,1] ^ r0[14,1]);\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\nmacro overflowflagsb(r3, r2, r1, r0) {\n $(PSW_V) = r3[7,1] | r2[7,1] | r1[7,1] | r0[7,1];\n $(PSW_SV) = $(PSW_V) | $(PSW_SV);\n $(PSW_AV) = (r3[7,1] ^ r3[6,1]) | (r2[7,1] ^ r2[6,1]) | (r1[7,1] ^ r1[6,1]) | (r0[7,1] ^ r0[6,1]);\n $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV);\n}\n\n\n#define pcodeop ssov;\nmacro ssov(res,x,y) {\n local max_pos = (1 << (y - 1)) - 1;\n local max_neg = -(1 << (y - 1));\n\tlocal sc1 = x s> max_pos;\n\tlocal sc2 = x s< max_neg;\n\tres = (max_pos * zext(sc1 != 0)) + (max_neg * zext(sc1 == 0 && sc2 != 0)) + (x * zext(sc1 == 0 && sc2 == 0));\n}\n\n#define pcodeop suov;\nmacro suov(res,x,y) {\n local max_pos = (1 << y) - 1;\n\tlocal sc1 = x s> max_pos;\n\tlocal sc2 = x s< 0;\n\tres = (max_pos * zext(sc1 != 0)) + (x * zext(sc1 == 0 && sc2 == 0));\n}\n\nmacro int_abs(res, val) {\n local acond = val s< 0;\n res = (val * zext(acond == 0)) + (-val * zext(acond != 0));\n}\nmacro int_abs1(res, val) {\n local acond = val s< 0;\n res = (val * (acond == 0)) + (-val * (acond != 0));\n}\n\nmacro ternary(res, cond, avar, bvar) {\n\tres = (avar * zext(cond != 0)) + (bvar * zext(cond == 0));\n}\n\n@if defined(TRICORE_VERBOSE)\nmacro load_lower_context(EA) {\n # dummy = *[ram]:4 EA ;\n EA = EA + 4;\n # dummy = *[ram]:4 EA ;\n EA = EA + 4;\n a2 = *[ram]:4 EA ; EA = EA + 4;\n a3 = *[ram]:4 EA ; EA = EA + 4;\n d0 = *[ram]:4 EA ; EA = EA + 4;\n d1 = *[ram]:4 EA ; EA = EA + 4;\n d2 = *[ram]:4 EA ; EA = EA + 4;\n d3 = *[ram]:4 EA ; EA = EA + 4;\n a4 = *[ram]:4 EA ; EA = EA + 4;\n a5 = *[ram]:4 EA ; EA = EA + 4;\n a6 = *[ram]:4 EA ; EA = EA + 4;\n a7 = *[ram]:4 EA ; EA = EA + 4;\n d4 = *[ram]:4 EA ; EA = EA + 4;\n d5 = *[ram]:4 EA ; EA = EA + 4;\n d6 = *[ram]:4 EA ; EA = EA + 4;\n d7 = *[ram]:4 EA ; EA = EA + 4;\n}\n@endif\n\n@if defined(TRICORE_VERBOSE)\nmacro store_lower_context(EA) {\n\t*[ram]:4 EA = PCXI; EA = EA + 4;\n\t*[ram]:4 EA = a11; EA = EA + 4;\n\t*[ram]:4 EA = a2; EA = EA + 4;\n\t*[ram]:4 EA = a3; EA = EA + 4;\n\t*[ram]:4 EA = d0; EA = EA + 4;\n\t*[ram]:4 EA = d1; EA = EA + 4;\n\t*[ram]:4 EA = d2; EA = EA + 4;\n\t*[ram]:4 EA = d3; EA = EA + 4;\n\t*[ram]:4 EA = a4; EA = EA + 4;\n\t*[ram]:4 EA = a5; EA = EA + 4;\n\t*[ram]:4 EA = a6; EA = EA + 4;\n\t*[ram]:4 EA = a7; EA = EA + 4;\n\t*[ram]:4 EA = d4; EA = EA + 4;\n\t*[ram]:4 EA = d5; EA = EA + 4;\n\t*[ram]:4 EA = d6; EA = EA + 4;\n\t*[ram]:4 EA = d7; EA = EA + 4;\n}\n@endif\n\nmacro _restore_upper_context(EA) {\n\ta10 = *[ram]:4 EA; EA = EA + 4;\n\ta11 = *[ram]:4 EA; EA = EA + 4;\n\td8 = *[ram]:4 EA; EA = EA + 4;\n\td9 = *[ram]:4 EA; EA = EA + 4;\n\td10 = *[ram]:4 EA; EA = EA + 4;\n\td11 = *[ram]:4 EA; EA = EA + 4;\n\ta12 = *[ram]:4 EA; EA = EA + 4;\n\ta13 = *[ram]:4 EA; EA = EA + 4;\n\ta14 = *[ram]:4 EA; EA = EA + 4;\n\ta15 = *[ram]:4 EA; EA = EA + 4;\n\td12 = *[ram]:4 EA; EA = EA + 4;\n\td13 = *[ram]:4 EA; EA = EA + 4;\n\td14 = *[ram]:4 EA; EA = EA + 4;\n\td15 = *[ram]:4 EA; EA = EA + 4;\n}\n\n@if defined(TRICORE_VERBOSE)\nmacro restore_upper_context(EA) {\n\tPCXI = *[ram]:4 EA; EA = EA + 4;\n\tPSW = *[ram]:4 EA; EA = EA + 4;\n\t_restore_upper_context(EA);\n}\n@endif\n\n\ndefine pcodeop saveCallerState;\ndefine pcodeop restoreCallerState;\n\n\n@if defined(TRICORE_VERBOSE)\nmacro restore_debug_context(EA) {\n\tPCXI = *[ram]:4 EA; EA = EA + 4;\n\tPSW = *[ram]:4 EA; EA = EA + 4;\n\ta10 = *[ram]:4 EA; EA = EA + 4;\n\ta11 = *[ram]:4 EA; EA = EA + 4;\n}\n@else\ndefine pcodeop restore_debug_context;\n@endif\n\n@if defined(TRICORE_VERBOSE)\nmacro load_upper_context(EA) {\n # dummy = *[ram]:4 EA;\n EA = EA + 4;\n # dummy = *[ram]:4 EA;\n EA = EA + 4;\n _restore_upper_context(EA);\n}\n@endif\n\n@if defined(TRICORE_VERBOSE)\nmacro store_upper_context(EA) {\n *[ram]:4 EA = PCXI; EA = EA + 4;\n *[ram]:4 EA = PSW; EA = EA + 4;\n *[ram]:4 EA = a10; EA = EA + 4;\n *[ram]:4 EA = a11; EA = EA + 4;\n *[ram]:4 EA = d8; EA = EA + 4;\n *[ram]:4 EA = d9; EA = EA + 4;\n *[ram]:4 EA = d10; EA = EA + 4;\n *[ram]:4 EA = d11; EA = EA + 4;\n *[ram]:4 EA = a12; EA = EA + 4;\n *[ram]:4 EA = a13; EA = EA + 4;\n *[ram]:4 EA = a14; EA = EA + 4;\n *[ram]:4 EA = a15; EA = EA + 4;\n *[ram]:4 EA = d12; EA = EA + 4;\n *[ram]:4 EA = d13; EA = EA + 4;\n *[ram]:4 EA = d14; EA = EA + 4;\n *[ram]:4 EA = d15; EA = EA + 4;\n}\n@endif\n\nmacro BitReverseAddressingMode(rege, rego, EA) {\n local index:2 = rego[0,16];\n local incr:2 = rego[16,16];\n EA = rege + zext(index);\n local rindex:2 = reverse16(index);\n local rincr:2 = reverse16(incr);\n local new_index:2 = reverse16(rindex + rincr);\n rego[0,16] = new_index;\n}\n\nmacro CircularAddressingMode(rege, rego, EA0, off10) {\n local index:2 = rego[0,16];\n local length:2 = rego[16,16];\n EA0 = rege + zext(index);\n local new_index:2 = index + off10[0,10];\n ternary(new_index, new_index s< 0, new_index + length, new_index % length);\n rego[0,16] = new_index;\n}\n\nmacro CircularAddressingMode2(rege, rego, EA0, EA1, off10, circsize) {\n local index:2 = rego[0,16];\n local length:2 = rego[16,16];\n EA0 = rege + zext(index);\n EA1 = rege + zext((index + circsize) % length);\n local new_index:2 = index + off10[0,10];\n ternary(new_index, new_index s< 0, new_index + length, new_index % length);\n rego[0,16] = new_index;\n}\n\nmacro CircularAddressingMode4(rege, rego, EA0, EA1, EA2, EA3, off10, circsize) {\n local index:2 = rego[0,16];\n local length:2 = rego[16,16];\n EA0 = rege + zext(index);\n EA1 = rege + zext((index + circsize) % length);\n EA2 = rege + zext((index + circsize + circsize) % length);\n EA3 = rege + zext((index + circsize + circsize + circsize) % length);\n local new_index:2 = index + off10[0,10];\n ternary(new_index, new_index s< 0, new_index + length, new_index % length);\n rego[0,16] = new_index;\n}\n\n#TODO Should probably just delete this and any \"+i\" until referencing a\n# T2 manual instead of DSP/compiler guide\nmacro IndexAddressingMode(rege, rego, EA) {\n local index:2 = rego[0,16];\n local modifier:2 = rego[16,16];\n EA = rege + zext(index);\n rego[0,16] = index + modifier;\n}\n\noff10: reloc is PCPMode=0 & op1621 & sop2831 [ reloc = op1621 | (sop2831 << 6); ] { local tmp:4 = reloc; export tmp; }\n\noff16: reloc is PCPMode=0 & op1621 & sop2227 & op2831 [ reloc = op1621 | (op2831 << 6) | (sop2227 << 10); ] { local tmp:4 = reloc; export tmp; }\n\noff18: reloc is PCPMode=0 & op1215 ; op1621 & op2225 & op2831 [ reloc = (op1215 << 28) | (op2225 << 10) | (op2831 << 6) | op1621; ] { local tmp:4 = reloc; export tmp; }\n\noff24pc: reloc is PCPMode=0 & sop0815 ; op1631 [ reloc = inst_start + ((op1631 | (sop0815 << 16)) * 2); ] { export *[ram]:4 reloc; }\n\noff24abs: reloc is PCPMode=0 & op0811 & op1215 ; op1631 [ reloc = (op1631 << 1) | (op0811 << 17) | (op1215 << 28); ] { export *[ram]:4 reloc; }\n\noff0811pc4o: reloc is PCPMode=0 & op0811 [ reloc = inst_start + (0xffffffe0 | (op0811 << 1)); ] { export *[ram]:4 reloc; }\n\noff0811pc4z: reloc is PCPMode=0 & op0811 [ reloc = inst_start + (op0811 * 2); ] { export *[ram]:4 reloc; }\n\noff0815pc8s: reloc is PCPMode=0 & sop0815 [ reloc = inst_start + (sop0815 * 2); ] { export *[ram]:4 reloc; }\n\noff1630pc15s: reloc is PCPMode=0 & sop1630 [ reloc = inst_start + (sop1630 * 2); ] { export *[ram]:4 reloc; }\n\n@if defined(TRICORE_V2)\noff0811pc4z16: reloc is PCPMode=0 & op0811 [ reloc = inst_start + ((op0811 + 16) * 2); ] { export *[ram]:4 reloc; }\n@endif\n\nconst0607Z: \"#\"^op0607 is PCPMode=0 & op0607 { local tmp:4 = op0607; export tmp; }\n\nconst0810Z: \"#\"^op0810 is PCPMode=0 & op0810 { local tmp:4 = op0810; export tmp; }\n\nconst0811Z6zz: \"#\"^reloc is PCPMode=0 & op0811 [ reloc = op0811 << 2; ] { local tmp:4 = reloc; export tmp; }\n\nconst0811Z: \"#\"^op0811 is PCPMode=0 & op0811 { local tmp:4 = op0811; export tmp; }\n\nconst0811Z5z: \"#\"^reloc is PCPMode=0 & op0811 [ reloc = op0811 << 1; ] { local tmp:4 = reloc; export tmp; }\n\nconst0815Z: \"#\"^op0815 is PCPMode=0 & op0815 { local tmp:4 = op0815; export tmp; }\n\nconst0815Z10zz: \"#\"^reloc is PCPMode=0 & op0815 [ reloc = op0815 << 2; ] { local tmp:4 = reloc; export tmp; }\n\nconst1111Z: \"#\"^op1111 is PCPMode=0 & op1111 { local tmp:4 = op1111; export tmp; }\n\nconst1215S: \"#\"^sop1215 is PCPMode=0 & sop1215 { local tmp:4 = sop1215; export tmp; }\n\nconst1215Z: \"#\"^op1215 is PCPMode=0 & op1215 { local tmp:4 = op1215; export tmp; }\n\nconst1215Z6zz: \"#\"^reloc is PCPMode=0 & op1215 [ reloc = op1215 << 2; ] { local tmp:4 = reloc; export tmp; }\n\nconst1215Z5z: \"#\"^reloc is PCPMode=0 & op1215 [ reloc = op1215 << 1; ] { local tmp:4 = reloc; export tmp; }\n\nconst1220S: \"#\"^reloc is PCPMode=0 & op1215 ; sop1620 [ reloc = (sop1620 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; }\n\nconst1220Z: \"#\"^reloc is PCPMode=0 & op1215 ; op1620 [ reloc = (op1620 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; }\n\nconst1227S: \"#\"^reloc is PCPMode=0 & op1215 ; sop1627 [ reloc = (sop1627 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; }\n\nconst1227Z: \"#\"^reloc is PCPMode=0 & op1215 ; op1627 [ reloc = (op1627 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; }\n\nconst1617Z: \"#\"^op1617 is PCPMode=0 & op1617 { local tmp:4 = op1617; export tmp; }\n\nconst1620Z: \"#\"^op1620 is PCPMode=0 & op1620 { local tmp:4 = op1620; export tmp; }\n\nconst2327Z: \"#\"^op2327 is PCPMode=0 & op2327 { local tmp:4 = op2327; export tmp; }\n\nNbit: \"#\"^reloc is PCPMode=0 & op0707 & op1215 [ reloc = (op0707 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; }\n\n\n\n#TODO circular is seems too compilcated to do this way\n#BO: [Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0003=9 & op0405=2 ; off10 & op2627=1 { local EA:4; CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); export EA; }\n\n\nBO: [Rpe1215/Rpo1215^\"+r\"^] is PCPMode=0 & Rpe1215 & Rpo1215 & op0003=9 & op0405=2 ; op1621=0x0 & op2627=0 & op2831=0x0 { local EA:4; BitReverseAddressingMode(Rpe1215, Rpo1215, EA); export EA; }\n\nBO: [Rpe1215/Rpo1215^\"+i\"^] is PCPMode=0 & Rpe1215 & Rpo1215 & op0003=9 & op0405=2 ; op1621=0x0 & op2627=2 & op2831=0x0 { local EA:4; IndexAddressingMode(Rpe1215, Rpo1215, EA); export EA; }\n\nBO: [Ra1215]off10 is PCPMode=0 & Ra1215 & op0003=9 & op0405=0 ; off10 & op2627=2 { local EA = Ra1215 + off10; export EA; }\n\nBO: [Ra1215+]off10 is PCPMode=0 & Ra1215 & op0003=9 & op0405=0 ; off10 & op2627=0 { local EA = Ra1215; Ra1215 = Ra1215 + off10; export EA; }\n\nBO: [+Ra1215]off10 is PCPMode=0 & Ra1215 & op0003=9 & op0405=0 ; off10 & op2627=1 { Ra1215 = Ra1215 + off10; local EA = Ra1215; export EA; }\n\n\nBOL: [Ra1215]off16 is PCPMode=0 & Ra1215 ; off16 { local EA = Ra1215 + off16; export EA; }\n\n\nSSR: [Ra1215] is PCPMode=0 & Ra1215 & op0003=4 & op0405=3 { local EA = Ra1215; export EA; }\n\nSSR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=2 & op0606=1 { local EA = Ra1215; Ra1215 = Ra1215 + 4; export EA; }\n\nSSR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=2 & op0606=0 & op0707=1 { local EA = Ra1215; Ra1215 = Ra1215 + 2; export EA; }\n\nSSR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=2 & op0606=0 & op0707=0 { local EA = Ra1215; Ra1215 = Ra1215 + 1; export EA; }\n\n\nSLR: [Ra1215] is PCPMode=0 & Ra1215 & op0003=4 & op0405=1 { local EA = Ra1215; export EA; }\n\nSLR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=0 & op0606=1 { local EA = Ra1215; Ra1215 = Ra1215 + 4; export EA; }\n\nSLR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=0 & op0606=0 & op0707=1 { local EA = Ra1215; Ra1215 = Ra1215 + 2; export EA; }\n\nSLR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=0 & op0606=0 & op0707=0 { local EA = Ra1215; Ra1215 = Ra1215 + 1; export EA; }\n\n\nSRO: [Ra1215]const0811Z is PCPMode=0 & Ra1215 & const0811Z & op0003=0xc & op0404=0 & op0607=0 { local EA = Ra1215 + const0811Z; export EA; }\n\nSRO: [Ra1215]const0811Z5z is PCPMode=0 & Ra1215 & const0811Z5z & op0003=0xc & op0404=0 & op0607=2 { local EA = Ra1215 + const0811Z5z; export EA; }\n\nSRO: [Ra1215]const0811Z6zz is PCPMode=0 & Ra1215 & const0811Z6zz & op0003=0xc & op0404=0 & op0606=1 { local EA = Ra1215 + const0811Z6zz; export EA; }\n\n\nSLRO: [a15]const1215Z is PCPMode=0 & a15 & const1215Z & op0003=8 & op0405=0 & op0607=0 { local EA = a15 + const1215Z; export EA; }\n\nSLRO: [a15]const1215Z5z is PCPMode=0 & a15 & const1215Z5z & op0003=8 & op0405=0 & op0607=2 { local EA = a15 + const1215Z5z; export EA; }\n\nSLRO: [a15]const1215Z6zz is PCPMode=0 & a15 & const1215Z6zz & op0003=8 & op0405=0 & op0606=1 { local EA = a15 + const1215Z6zz; export EA; }\n\n\nSSRO: [a15]const1215Z is PCPMode=0 & a15 & const1215Z & op0003=8 & op0405=2 & op0607=0 { local EA = a15 + const1215Z; export EA; }\n\nSSRO: [a15]const1215Z5z is PCPMode=0 & a15 & const1215Z5z & op0003=8 & op0405=2 & op0607=2 { local EA = a15 + const1215Z5z; export EA; }\n\nSSRO: [a15]const1215Z6zz is PCPMode=0 & a15 & const1215Z6zz & op0003=8 & op0405=2 & op0606=1 { local EA = a15 + const1215Z6zz; export EA; }\n\n\nSC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=1 & op0606=1 { local EA = a10 + const0815Z10zz; export EA; }\n\n\n\n# ABS D[c], D[b] (RR)\n:abs Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x1c0\n{\n\tint_abs(Rd2831, Rd1215);\n\toverflowflags(Rd2831);\n}\n\n# ABS.B D[c], D[b] (RR)\n:abs.b Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x5c0\n{\n\tlocal result3:1; int_abs1(result3, Rd1215[24,8]);\n\tlocal result2:1; int_abs1(result2, Rd1215[16,8]);\n\tlocal result1:1; int_abs1(result1, Rd1215[8,8]);\n\tlocal result0:1; int_abs1(result0, Rd1215[0,8]);\n\toverflowflagsb(result3, result2, result1, result0);\n\tRd2831[24,8] = result3;\n\tRd2831[16,8] = result2;\n\tRd2831[8,8] = result1;\n\tRd2831[0,8] = result0;\n}\n\n# ABS.H D[c], D[b] (RR)\n:abs.h Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x7c0\n{\n\tlocal result1:2; int_abs(result1, Rd1215[16,16]);\n\tlocal result0:2; int_abs(result0, Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tRd2831[16,16] = result1;\n\tRd2831[0,16] = result0;\n}\n\n# ABSDIF D[c], D[a], D[b] (RR)\n:absdif Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xe0\n{\n\tint_abs(Rd2831, Rd0811 - Rd1215);\n\toverflowflags(Rd2831);\n}\n\n# ABSDIF D[c], D[a], const9 (RC)\n:absdif Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xe ) & const1220S\n{\n\tint_abs(Rd2831, Rd0811 - const1220S);\n\toverflowflags(Rd2831);\n}\n\n# ABSDIF.B D[c], D[a], D[b] (RR)\n:absdif.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x4e0\n{\n\tlocal result3:1; int_abs1(result3, (Rd0811[24,8] - Rd1215[24,8]));\n\tlocal result2:1; int_abs1(result2, (Rd0811[16,8] - Rd1215[16,8]));\n\tlocal result1:1; int_abs1(result1, (Rd0811[8,8] - Rd1215[8,8]));\n\tlocal result0:1; int_abs1(result0, (Rd0811[0,8] - Rd1215[0,8]));\n\toverflowflagsb(result3, result2, result1, result0);\n\tRd2831[24,8] = result3;\n\tRd2831[16,8] = result2;\n\tRd2831[8,8] = result1;\n\tRd2831[0,8] = result0;\n}\n\n# ABSDIF.H D[c], D[a], D[b] (RR)\n:absdif.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6e0\n{\n\tlocal result1:2; int_abs(result1, (Rd0811[16,16] - Rd1215[16,16]));\n\tlocal result0:2; int_abs(result0, (Rd0811[0,16] - Rd1215[16,16]));\n\toverflowflagsh(result1, result0);\n\tRd2831[16,16] = result1;\n\tRd2831[0,16] = result0;\n}\n\n# ABSDIFS D[c], D[a], D[b] (RR)\n:absdifs Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xf0\n{\n\tlocal result:4; int_abs(result, (Rd0811 - Rd1215));\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# ABSDIFS D[c], D[a], const9 (RC)\n:absdifs Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xf ) & const1220S\n{\n\tlocal result:4; int_abs(result, (Rd0811 - const1220S));\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# ABSDIFS.H D[c], D[a], D[b] (RR)\n:absdifs.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6f0\n{\n\tlocal result1:2; int_abs(result1, (Rd0811[16,16] - Rd1215[16,16]));\n\tlocal result0:2; int_abs(result0, (Rd0811[0,16] - Rd1215[16,16]));\n\toverflowflagsh(result1, result0);\n\tssov(Rd2831[16,16], result1, 16);\n\tssov(Rd2831[0,16], result0, 16);\n}\n\n# ABSS D[c], D[b] (RR)\n:abss Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x1d0\n{\n\tlocal result:4; int_abs(result, Rd1215);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# ABSS.H D[c], D[b] (RR)\n:abss.h Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x7d0\n{\n\tlocal result1:2; int_abs(result1, Rd1215[16,16]);\n\tlocal result0:2; int_abs(result0, Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tssov(Rd2831[16,16], result1, 16);\n\tssov(Rd2831[0,16], result0, 16);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADD D[a], D[15], D[b] (SRR)\n:add Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x12\n{\n\tRd0811 = d15 + Rd1215;\n\toverflowflags(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADD D[a], D[15], const4 (SRC)\n:add Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0x92\n{\n\tRd0811 = d15 + const1215S;\n\toverflowflags(Rd0811);\n}\n@endif\n\n# ADD D[15], D[a], D[b] (SRR)\n:add d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x1a\n{\n\td15 = Rd0811 + Rd1215;\n\toverflowflags(d15);\n}\n\n# ADD D[a], D[b] (SRR)\n:add Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x42\n{\n\tRd0811 = Rd0811 + Rd1215;\n\toverflowflags(Rd0811);\n}\n\n# ADD D[15], D[a], const4 (SRC)\n:add d15,Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0x9a\n{\n\td15 = Rd0811 + const1215S;\n\toverflowflags(d15);\n}\n\n# ADD D[a], const4 (SRC)\n:add Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0xc2\n{\n\tRd0811 = Rd0811 + const1215S;\n\toverflowflags(Rd0811);\n}\n\n# ADD D[c], D[a], D[b] (RR)\n:add Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x0\n{\n\tRd2831 = Rd0811 + Rd1215;\n\toverflowflags(Rd2831);\n}\n\n# ADD D[c], D[a], const9 (RC)\n:add Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x0 ) & const1220S\n{\n\tRd2831 = Rd0811 + const1220S;\n\toverflowflags(Rd2831);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADD.A A[a], A[b] (SRR)\n:add.a Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x30\n{\n\tRa0811 = Ra0811 + Ra1215;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADD.A A[a], const4 (SRC)\n:add.a Ra0811,const1215S is PCPMode=0 & Ra0811 & const1215S & op0007=0xb0\n{\n\tRa0811 = Ra0811 + const1215S;\n}\n@endif\n\n# ADD.A A[c], A[a], A[b] (RR)\n:add.a Ra2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Ra2831 & op1627=0x10\n{\n\tRa2831 = Ra0811 + Ra1215;\n}\n\n# ADD.B D[c], D[a], D[b] (RR)\n:add.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x400\n{\n\tlocal result3:4 = zext(Rd0811[24,8] + Rd1215[24,8]);\n\tlocal result2:4 = zext(Rd0811[16,8] + Rd1215[16,8]);\n\tlocal result1:4 = zext(Rd0811[8,8] + Rd1215[8,8]);\n\tlocal result0:4 = zext(Rd0811[0,8] + Rd1215[0,8]);\n\toverflowflagsb(result3, result2, result1, result0);\n\tRd2831[24,8] = result3[0,8];\n\tRd2831[16,8] = result2[0,8];\n\tRd2831[8,8] = result1[0,8];\n\tRd2831[0,8] = result0[0,8];\n}\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADD.F D[c], D[d], D[a] (RRR)\n:add.f Rd2831,Rd2427,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x6b & op1215=0x0 ; Rd2427 & Rd2831 & op1623=0x21\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = Rd2427 f+ Rd0811;\n}\n@endif\n\n# ADD.H D[c], D[a], D[b] (RR)\n:add.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x600\n{\n\tlocal result1:4 = zext(Rd0811[16,16] + Rd1215[16,16]);\n\tlocal result0:4 = zext(Rd0811[0,16] + Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tRd2831[16,16] = result1[0,16];\n\tRd2831[0,16] = result0[0,16];\n}\n\n# ADDC D[c], D[a], D[b] (RR)\n:addc Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x50\n{\n\tlocal tmp:5 = zext(Rd0811) + zext(Rd1215) + zext($(PSW_C));\n\tRd2831 = tmp[0,32];\n\t$(PSW_C) = tmp[32,1];\n\toverflowflags(Rd2831);\n}\n\n# ADDC D[c], D[a], const9 (RC)\n:addc Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x5 ) & const1220S\n{\n\tlocal tmp:5 = zext(Rd0811) + zext(const1220S) + zext($(PSW_C));\n\tRd2831 = tmp[0,32];\n\t$(PSW_C) = tmp[32,1];\n\toverflowflags(Rd2831);\n}\n\n# ADDI D[c], D[a], const16 (RLC)\n:addi Rd2831,Rd0811,const1227S is PCPMode=0 & ( Rd0811 & op0007=0x1b ; Rd2831 ) & const1227S\n{\n\tRd2831 = Rd0811 + const1227S;\n\toverflowflags(Rd2831);\n}\n\n# ADDIH D[c], D[a], const16 (RLC)\n:addih Rd2831,Rd0811,const1227Z is PCPMode=0 & ( Rd0811 & op0007=0x9b ; Rd2831 ) & const1227Z\n{\n\tRd2831 = Rd0811 + (const1227Z << 16);\n\toverflowflags(Rd2831);\n}\n\n# ADDIH.A A[c], A[a], const16 (RLC)\n:addih.a Ra2831,Ra0811,const1227Z is PCPMode=0 & ( Ra0811 & op0007=0x11 ; Ra2831 ) & const1227Z\n{\n\tRa2831 = Ra0811 + (const1227Z << 16);\n}\n\n# ADDS D[a], D[b], (SRR)\n:adds Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x22\n{\n\tlocal result:4 = Rd0811 + Rd1215;\n\toverflowflags(result);\n\tssov(Rd0811, result, 32);\n}\n\n# ADDS D[c], D[a], D[b] (RR)\n:adds Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x20\n{\n\tlocal result:4 = Rd0811 + Rd1215;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# ADDS D[c], D[a], const9 (RC)\n:adds Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2 ) & const1220S\n{\n\tlocal result:4 = Rd0811 + const1220S;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# ADDS.H D[c], D[a], D[b] (RR)\n:adds.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x620\n{\n\tlocal result1:4 = sext(Rd0811[16,16] + Rd1215[16,16]);\n\tlocal result0:4 = sext(Rd0811[0,16] + Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tssov(Rd2831[16,16], result1[0,16], 16);\n\tssov(Rd2831[0,16], result0[0,16], 16);\n}\n\n# ADDS.HU D[c], D[a], D[b] (RR)\n:adds.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x630\n{\n\tlocal result1:4 = sext(Rd0811[16,16] + Rd1215[16,16]);\n\tlocal result0:4 = sext(Rd0811[0,16] + Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tsuov(Rd2831[16,16], result1[0,16], 16);\n\tsuov(Rd2831[0,16], result0[0,16], 16);\n}\n\n# ADDS.U D[c], D[a], D[b] (RR)\n:adds.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x30\n{\n\tlocal result:4 = Rd0811 + Rd1215;\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n# ADDS.U D[c], D[a], const9 (RC)\n:adds.u Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3 ) & const1220S\n{\n\tlocal result:4 = Rd0811 + const1220S;\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADDSC.A A[a], A[b], D[15], n (SRRS)\n:addsc.a Ra0811,Ra1215,d15,const0607Z is PCPMode=0 & Ra0811 & Ra1215 & const0607Z & d15 & op0005=0x10\n{\n\tRa0811 = Ra1215 + (d15 << const0607Z);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADDSC.A A[c], A[b], D[a], n (RR)\n:addsc.a Ra2831,Ra1215,Rd0811,const1617Z is PCPMode=0 & Ra1215 & Rd0811 & op0007=0x1 ; Ra2831 & const1617Z & op1827=0x180\n{\n\tRa2831 = Ra1215 + (Rd0811 << const1617Z);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ADDSC.AT A[c], A[b], D[a] (RR)\n:addsc.at Ra2831,Ra1215,Rd0811 is PCPMode=0 & Ra1215 & Rd0811 & op0007=0x1 ; Ra2831 & op1627=0x620\n{\n\tRa2831 = (Ra1215 + (Rd0811 >> 3)) & 0xFFFFFFFC;\n}\n@endif\n\n# ADDX D[c], D[a], D[b] (RR)\n:addx Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x40\n{\n\tlocal result:4 = Rd0811 + Rd1215;\n\t$(PSW_C) = carry(Rd0811, Rd1215);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n# ADDX D[c], D[a], const9 (RC)\n:addx Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x4 ) & const1220S\n{\n\tlocal result:4 = Rd0811 + const1220S;\n\t$(PSW_C) = carry(Rd0811, const1220S);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# AND D[a], D[b] (SRR)\n:and Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x26\n{\n\tRd0811 = Rd0811 & Rd1215;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# AND D[15], const8 (SC)\n:and d15,const0815Z is PCPMode=0 & const0815Z & d15 & op0007=0x16\n{\n\td15 = d15 & const0815Z;\n}\n@endif\n\n# AND D[c], D[a], D[b] (RR)\n:and Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x80\n{\n\tRd2831 = Rd0811 & Rd1215;\n}\n\n# AND D[c], D[a], const9 (RC)\n:and Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x8 ) & const1220Z\n{\n\tRd2831 = Rd0811 & const1220Z;\n}\n\n# AND.AND.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:and.and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831[0,1] = Rd2831[0,1] & (tmpa[0,1] & tmpb[0,1]);\n}\n\n# AND.ANDN.T D[c], D[a,] pos1, D[b], pos2 (BIT)\n:and.andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831[0,1] = Rd2831[0,1] & (tmpa[0,1] & ~tmpb[0,1]);\n}\n\n# AND.EQ D[c], D[a], D[b] (RR)\n:and.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x200\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 == Rd1215);\n}\n\n# AND.EQ D[c], D[a], const9 (RC)\n:and.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x20 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 == const1220S);\n}\n\n# AND.GE D[c], D[a], D[b] (RR)\n:and.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x240\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 s>= Rd1215);\n}\n\n# AND.GE D[c], D[a], const9 (RC)\n:and.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x24 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 s>= const1220S);\n}\n\n# AND.GE.U D[c], D[a], D[b] (RR)\n:and.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x250\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 >= Rd1215);\n}\n\n# AND.GE.U D[c], D[a], const9 (RC)\n:and.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x25 ) & const1220Z\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 >= const1220Z);\n}\n\n# AND.LT D[c], D[a], D[b] (RR)\n:and.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x220\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 s< Rd1215);\n}\n\n# AND.LT D[c], D[a], const9 (RC)\n:and.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x22 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 s< const1220S);\n}\n\n# AND.LT.U D[c], D[a], D[b] (RR)\n:and.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x230\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 < Rd1215);\n}\n\n# AND.LT.U D[c], D[a], const9 (RC)\n:and.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x23 ) & const1220Z\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 < const1220Z);\n}\n\n# AND.NE D[c], D[a], D[b] (RR)\n:and.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x210\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 != Rd1215);\n}\n\n# AND.NE D[c], D[a], const9 (RC)\n:and.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x21 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] & (Rd0811 != const1220S);\n}\n\n# AND.NOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:and.nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831[0,1] = Rd2831[0,1] & !(tmpa[0,1] | tmpb[0,1]);\n}\n\n# AND.OR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:and.or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831[0,1] = Rd2831[0,1] & (tmpa[0,1] | tmpb[0,1]);\n}\n\n# AND.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831 = zext(tmpa[0,1] & tmpb[0,1]);\n}\n\n# ANDN D[c], D[a], D[b] (RR)\n:andn Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xe0\n{\n\tRd2831 = Rd0811 & ~Rd1215;\n}\n\n# ANDN D[c], D[a], const9 (RC)\n:andn Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xe ) & const1220Z\n{\n\tRd2831 = Rd0811 & ~const1220Z;\n}\n\n# ANDN.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831 = zext(tmpa[0,1] & !tmpb[0,1]);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# BISR const8 (SC)\n:bisr const0815Z is PCPMode=0 & const0815Z & op0007=0xe0\n{\n\t#TODO isr\n\t# tmp_FCX = FCX;\n\t# if (FCX == 0) trap(FCU);\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA,16 * word) = {PCXI, a11, a2, a3, d0, d1, d2, d3, a4, a5, a6, a7, d4, d5, d6, d7};\n\t# PCXI.PCPN = ICR.CCPN;\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 0;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# ICR.IE = 1;\n\t# ICR.CCPN = const8;\n\t# if (tmp_FCX == LCX) trap(FCD);\n}\n@endif\n\n# BISR const9 (RC)\n:bisr const1220Z is PCPMode=0 & ( op0007=0xad & op0811=0x0 ; op2131=0x0 ) & const1220Z\n{\n\t#TODO isr\n\t# if (FCX == 0) trap(FCU);\n\t# tmp_FCX = FCX;\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA,16 * word) = {PCXI, a11, a2, a3, d0, d1, d2, d3, a4, a5, a6, a7, d4, d5, d6, d7};\n\t# PCXI.PCPN = ICR.CCPN;\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 0;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# ICR.IE = 1;\n\t# ICR.CCPN = const9[7:0];\n\t# if (tmp_FCX == LCX) trap(FCD);\n}\n\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# BMERGE D[c], D[a], D[b] (RR)\n:bmerge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x10\n{\n@if defined(TRICORE_VERBOSE)\n\tRd2831[31,1] = Rd0811[15,1];\n\tRd2831[30,1] = Rd1215[15,1];\n\tRd2831[29,1] = Rd0811[14,1];\n\tRd2831[28,1] = Rd1215[14,1];\n\tRd2831[27,1] = Rd0811[13,1];\n\tRd2831[26,1] = Rd1215[13,1];\n\tRd2831[25,1] = Rd0811[12,1];\n\tRd2831[24,1] = Rd1215[12,1];\n\tRd2831[23,1] = Rd0811[11,1];\n\tRd2831[22,1] = Rd1215[11,1];\n\tRd2831[21,1] = Rd0811[10,1];\n\tRd2831[20,1] = Rd1215[10,1];\n\tRd2831[19,1] = Rd0811[9,1];\n\tRd2831[18,1] = Rd1215[9,1];\n\tRd2831[17,1] = Rd0811[8,1];\n\tRd2831[16,1] = Rd1215[8,1];\n\tRd2831[15,1] = Rd0811[7,1];\n\tRd2831[14,1] = Rd1215[7,1];\n\tRd2831[13,1] = Rd0811[6,1];\n\tRd2831[12,1] = Rd1215[6,1];\n\tRd2831[11,1] = Rd0811[5,1];\n\tRd2831[10,1] = Rd1215[5,1];\n\tRd2831[9,1] = Rd0811[4,1];\n\tRd2831[8,1] = Rd1215[4,1];\n\tRd2831[7,1] = Rd0811[3,1];\n\tRd2831[6,1] = Rd1215[3,1];\n\tRd2831[5,1] = Rd0811[2,1];\n\tRd2831[4,1] = Rd1215[2,1];\n\tRd2831[3,1] = Rd0811[1,1];\n\tRd2831[2,1] = Rd1215[1,1];\n\tRd2831[1,1] = Rd0811[0,1];\n\tRd2831[0,1] = Rd1215[0,1];\n@else\n\tbmerge(Rd2831,Rd0811,Rd1215);\n@endif\n}\n@endif\n\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# BSPLIT E[c], D[a] (RR)\n:bsplit Re2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Re2831 & op1627=0x90\n{\n@if defined(TRICORE_VERBOSE)\n\tRe2831[48,16] = 0;\n\tRe2831[47,1] = Rd0811[31,1];\n\tRe2831[46,1] = Rd0811[29,1];\n\tRe2831[45,1] = Rd0811[27,1];\n\tRe2831[44,1] = Rd0811[25,1];\n\tRe2831[43,1] = Rd0811[23,1];\n\tRe2831[42,1] = Rd0811[21,1];\n\tRe2831[41,1] = Rd0811[19,1];\n\tRe2831[40,1] = Rd0811[17,1];\n\tRe2831[39,1] = Rd0811[15,1];\n\tRe2831[38,1] = Rd0811[13,1];\n\tRe2831[37,1] = Rd0811[11,1];\n\tRe2831[36,1] = Rd0811[9,1];\n\tRe2831[35,1] = Rd0811[7,1];\n\tRe2831[34,1] = Rd0811[5,1];\n\tRe2831[33,1] = Rd0811[3,1];\n\tRe2831[32,1] = Rd0811[1,1];\n\tRe2831[16,16] = 0;\n\tRe2831[15,1] = Rd0811[30,1];\n\tRe2831[14,1] = Rd0811[28,1];\n\tRe2831[13,1] = Rd0811[26,1];\n\tRe2831[12,1] = Rd0811[24,1];\n\tRe2831[11,1] = Rd0811[22,1];\n\tRe2831[10,1] = Rd0811[20,1];\n\tRe2831[9,1] = Rd0811[18,1];\n\tRe2831[8,1] = Rd0811[16,1];\n\tRe2831[7,1] = Rd0811[14,1];\n\tRe2831[6,1] = Rd0811[12,1];\n\tRe2831[5,1] = Rd0811[10,1];\n\tRe2831[4,1] = Rd0811[8,1];\n\tRe2831[3,1] = Rd0811[6,1];\n\tRe2831[2,1] = Rd0811[4,1];\n\tRe2831[1,1] = Rd0811[2,1];\n\tRe2831[0,1] = Rd0811[0,1];\n@else\n\tbsplit(Re2831,Rd0811);\n@endif\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# CACHEA.I A[b], off10 (BO) (Post-increment Addressing Mode)\n# CACHEA.I P[b] (BO) (Bit Reverse Addressing Mode)\n# CACHEA.I A[b], off10 (BO) (Pre-increment Addressing Mode)\n# CACHEA.I A[b], off10 (BO) (Base + Short Offset Addressing Mode)\n# CACHEA.I P[b] (BO) (Index Addressing Mode)\n:cachea.i BO is PCPMode=0 & ( op0607=0x2 & op0811=0x0 ; op2225=0xe ) & BO\n{\n\tbuild BO;\n\tcache_address_ivld(BO);\n}\n\n# CACHEA.I P[b], off10 (BO) (Circular Addressing Mode)\n#:cachea.i BO is PCPMode=0 & ( op0007=0xa9 & op0811=0x0 ; op2227=0x1e ) & BO\n:cachea.i [Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0007=0xa9 & op0811=0x0 ; off10 & op2227=0x1e\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tcache_address_ivld(EA);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# CACHEA.W A[b], off10 (BO) (Post-increment Addressing Mode)\n# CACHEA.W P[b] (BO) (Bit-reverse Addressing Mode)\n# CACHEA.W A[b], off10 (BO) (Pre-increment Addressing Mode)\n# CACHEA.W A[b], off10 (BO) (Base + Short Offset Addressing Mode)\n# CACHEA.W P[b] (BO) (Index Addressing Mode)\n:cachea.w BO is PCPMode=0 & ( op0607=0x2 & op0811=0x0 ; op2225=0xc ) & BO\n{\n\tbuild BO;\n\tcache_address_wb(BO);\n}\n\n# CACHEA.W P[b], off10 (BO)(Circular Addressing Mode)\n#:cachea.w BO is PCPMode=0 & ( op0007=0xa9 & op0811=0x0 ; op2227=0x1c ) & BO\n:cachea.w [Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0007=0xa9 & op0811=0x0 ; off10 & op2227=0x1c\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tcache_address_wb(EA);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# CACHEA.WI A[b], off10 (BO)(Post-increment Addressing Mode)\n# CACHEA.WI P[b] (BO)(Bit-reverse Addressing Mode)\n# CACHEA.WI A[b], off10 (BO)(Pre-increment Addressing Mode)\n# CACHEA.WI A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# CACHEA.WI P[b] (BO)(Index Addressing Mode)\n:cachea.wi BO is PCPMode=0 & ( op0607=0x2 & op0811=0x0 ; op2225=0xd ) & BO\n{\n\tbuild BO;\n\tcache_address_wi(BO);\n}\n\n# CACHEA.WI P[b], off10 (BO) (Circular Addressing Mode)\n#:cachea.wi BO is PCPMode=0 & ( op0007=0xa9 & op0811=0x0 ; op2227=0x1d ) & BO\n:cachea.wi [Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0007=0xa9 & op0811=0x0 ; off10 & op2227=0x1d\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tcache_address_wi(EA);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# CACHEI.I A[b], off10 (BO)(Post-increment Addressing Mode)\n# CACHEI.I A[b], off10 (BO)(Pre-increment Addressing Mode)\n# CACHEI.I A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n:cachei.i BO is PCPMode=0 & ( op0407=0x8 & op0811=0x0 ; op2225=0xa ) & BO\n{\n\tbuild BO;\n\tcache_index_ivld(BO);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# CACHEI.W A[b], off10 (BO)(Post-increment Addressing Mode)\n# CACHEI.W A[b], off10 (BO)(Pre-increment Addressing Mode)\n# CACHEI.W A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n:cachei.w BO is PCPMode=0 & ( op0407=0x8 & op0811=0x0 ; op2225=0xb ) & BO\n{\n\tbuild BO;\n\tcache_index_wb(BO);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# CACHEI.WI A[b], off10 (BO)(Post-increment Addressing Mode)\n# CACHEI.WI A[b], off10 (BO)(Pre-increment Addressing Mode)\n# CACHEI.WI A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n:cachei.wi BO is PCPMode=0 & ( op0407=0x8 & op0811=0x0 ; op2225=0xf ) & BO\n{\n\tbuild BO;\n\tcache_index_wi(BO);\n}\n@endif\n\n# CADD D[a], D[15], const4 (SRC)\n:cadd Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0x8a\n{\n\tlocal result:4;\n\tternary(result, d15 != 0, Rd0811 + const1215S, Rd0811);\n\toverflowflags(result);\n\tRd0811 = result;\n}\n\n# CADD D[c], D[d], D[a], D[b] (RRR)\n:cadd Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x0\n{\n\tlocal result:4;\n\tternary(result, Rd2427 != 0, Rd0811 + Rd1215, Rd0811);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n# CADD D[c], D[d], D[a], const9 (RCR)\n:cadd Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x0 ) & const1220S\n{\n\tlocal result:4;\n\tternary(result, Rd2427 != 0, Rd0811 + const1220S, Rd0811);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n# CADDN D[a], D[15], const4 (SRC)\n:caddn Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xca\n{\n\tlocal result:4;\n\tternary(result, d15 == 0, Rd0811 + const1215S, Rd0811);\n\toverflowflags(result);\n\tRd0811 = result;\n}\n\n# CADDN D[c], D[d], D[a], D[b] (RRR)\n:caddn Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x10\n{\n\tlocal result:4;\n\tternary(result, Rd2427 == 0, Rd0811 + Rd1215, Rd0811);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n# CADDN D[c], D[d], D[a], const9 (RCR)\n:caddn Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x1 ) & const1220S\n{\n\tlocal result:4;\n\tternary(result, Rd2427 == 0, Rd0811 + const1220S, Rd0811);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# CALL disp8 (SB)\n:call off0815pc8s is PCPMode=0 & off0815pc8s & op0007=0x5c\n{\n\t#TODO call\n\t# if (FCX == 0) trap(FCU);\n\t# if (PSW.CDE) then if(cdc_increment()) then trap(CDO);\n\t# PSW.CDE = 1;\n\t# ret_addr = PC + 2 ;\n\t# tmp_FCX = FCX;\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15};\n\t# PCXI.PCPN = ICR.CCPN;\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 1;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# PC = PC + sign_ext(2 * disp8);\n\t# A[11] = ret_addr[31:0];\n\t# if (tmp_FCX == LCX) trap(FCD);\n\n\tsaveCallerState(FCX, LCX, PCXI);\n\ta11 = inst_next;\n\tcall off0815pc8s;\n}\n@endif\n\n# CALL disp24 (B)\n:call off24pc is PCPMode=0 & ( op0007=0x6d ) ... & off24pc\n{\n\t#TODO call\n\t# if (FCX == 0) trap(FCU);\n\t# if (PSW.CDE) then if (cdc_increment()) then trap(CDO);\n\t# PSW.CDE = 1;\n\t# ret_addr = PC + 4;\n\t# tmp_FCX = FCX;\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15};\n\t# PCXI.PCPN = ICR.CCPN;\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 1;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# PC = PC + sign_ext(2 * disp24);\n\t# A[11] = ret_addr[31:0];\n\t# if (tmp_FCX == LCX) trap(FCD);\n\n\tsaveCallerState(FCX, LCX, PCXI);\n\ta11 = inst_next;\n\tcall off24pc;\n}\n\n# CALLA disp24 (B)\n:calla off24abs is PCPMode=0 & ( op0007=0xed ) ... & off24abs\n{\n\t#TODO call\n\t# if (FCX == 0) trap(FCU);\n\t# if (PSW.CDE) then if (cdc_increment()) then trap(CDO);\n\t# PSW.CDE = 1;\n\t# ret_addr = PC + 4;\n\t# tmp_FCX = FCX;\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15};\n\t# PCXI.PCPN = ICR.CCPN;\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 1;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# PC = {disp24[23:20], 7'b0, disp24[19:0], 1'b0};\n\t# A[11] = ret_addr[31:0];\n\t# if (tmp_FCX == LCX) trap(FCD);\n\n\tsaveCallerState(FCX, LCX, PCXI);\n\ta11 = inst_next;\n\tcall off24abs;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# CALLI A[a] (RR)\n:calli Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x0\n{\n\t#TODO call\n\t# if (FCX == 0) trap(FCU);\n\t# if (PSW.CDE) then if(cdc_increment()) then trap(CDO);\n\t# PSW.CDE = 1;\n\t# ret_addr = PC + 4;\n\t# tmp_FCX = FCX;\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15};\n\t# PCXI.PCPN = ICR.CCPN;\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 1;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# PC = {A[a][31:1], 1'b0};\n\t# A[11] = ret_addr[31:0];\n\t# if (tmp_FCX == LCX) trap(FCD);\n\n\tsaveCallerState(FCX, LCX, PCXI);\n\ta11 = inst_next;\n\tlocal tmp:4 = Ra0811 & 0xFFFFFFFE;\n\tcall [tmp];\n}\n@endif\n\n# CLO D[c], D[a] (RR)\n:clo Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x1c0\n{\n\tRd2831 = lzcount(~Rd0811);\n}\n\n# CLO.H D[c], D[a] (RR)\n:clo.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x7d0\n{\n\tlocal tmp1:2 = Rd0811[16,16];\n\tlocal tmp0:2 = Rd0811[0,16];\n\tRd2831[16,16] = lzcount(~tmp1);\n\tRd2831[0,16] = lzcount(~tmp0);\n}\n\n# CLS D[c], D[a] (RR)\n:cls Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x1d0\n{\n\tlocal tmp:4 = (Rd0811 ^ (Rd0811<<1))|0x1;\n\n\tRd2831 = lzcount(tmp);\n}\n\n# CLS.H D[c], D[a] (RR)\n:cls.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x7e0\n{\n\tlocal tmp1:2 = (Rd0811[16,16] ^ (Rd0811[16,16]<<1))|0x1;\n\tlocal tmp0:2 = (Rd0811[0,16] ^ (Rd0811[0,16]<<1))|0x1;\n\tRd2831[16,16] = lzcount(tmp1);\n\tRd2831[0,16] = lzcount(tmp0);\n}\n\n# CLZ D[c], D[a] (RR)\n:clz Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x1b0\n{\n\tRd2831 = lzcount(Rd0811);\n}\n\n# CLZ.H D[c], D[a] (RR)\n:clz.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x7c0\n{\n\tlocal result:4 = (lzcount(Rd0811[16,16]) << 16) | lzcount(Rd0811[0,16]);\n\tRd2831 = result;\n}\n\n# CMOV D[a], D[15], D[b] (SRR)\n:cmov Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x2a\n{\n\tternary(Rd0811, d15 != 0, Rd1215, Rd0811);\n}\n\n# CMOV D[a], D[15], const4 (SRC)\n:cmov Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xaa\n{\n\tternary(Rd0811, d15 != 0, const1215S, Rd0811);\n}\n\n# CMOVN D[a], D[15], D[b] (SRR)\n:cmovn Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x6a\n{\n\tternary(Rd0811, d15 == 0, Rd1215, Rd0811);\n}\n\n# CMOVN D[a], D[15], const4 (SRC)\n:cmovn Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xea\n{\n\tternary(Rd0811, d15 == 0, const1215S, Rd0811);\n}\n\n@if defined(TRICORE_V2)\n# CMPSWAP.W A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)\n# CMPSWAP.W P[b], E[a] (BO)(Bit-reverse Addressing Mode)\n# CMPSWAP.W A[b], off10, E[a] (BO)(Post-increment Addressing Mode)\n# CMPSWAP.W A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)\n# CMPSWAP.W P[b], E[a] (BO)(Index Addressing Mode)\n:cmpswap.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0607=0x1 ; op2225=0x3 ) & BO\n{\n\tbuild BO;\n\tlocal tmp:4 = *[ram]:4 BO;\n\tRee0811 = tmp;\n\tternary(tmp, tmp == Reo0811, Ree0811, tmp);\n\t*[ram]:4 BO = tmp;\n}\n@endif\n\n@if defined(TRICORE_V2)\n# CMPSWAP.W P[b], off10, E[a] (BO)(Circular Addressing Mode)\n#:cmpswap.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0x69 ; op2227=0x13 ) & BO\n:cmpswap.w [Rpe1215/Rpo1215^\"+c\"^]off10,Ree0811/Reo0811 is PCPMode=0 & Ree0811 & Reo0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x13\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tlocal tmp:4 = *[ram]:4 EA;\n\tRee0811 = tmp;\n\tternary(tmp, tmp == Reo0811, Ree0811, tmp);\n\t*[ram]:4 EA = tmp;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# CMP.F D[c], D[a], D[b] (RR)\n:cmp.f Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x1\n{\n\t#TODO float\n\t#TODO flags\n\tlocal tmpDa = Rd0811;\n\tlocal tmpDb = Rd1215;\n\tRd2831 = 0;\n\tRd2831[0,1] = tmpDa f< tmpDb;\n\tRd2831[1,1] = tmpDa f== tmpDb;\n\tRd2831[2,1] = tmpDa f> tmpDb;\n\tRd2831[3,1] = nan(tmpDa) || nan(tmpDb);\n\tRd2831[4,1] = tmpDa[23,8] == 0 && tmpDa[0,23] != 0;\n\tRd2831[5,1] = tmpDb[23,8] == 0 && tmpDb[0,23] != 0;\n}\n@endif\n\n:cop op2027[op1617],Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; op1617 & op2027 & Rd2831 & op1819=0x0\n{\n\t# Rd2831 = op2027[op1617](Rd0811,Rd1215);\n\tlocal op2:4 = op2027;\n\tlocal proc:4 = op1617;\n\tRd2831 = coprocessor(op2, proc, Rd0811, Rd1215);\n}\n\n:cop op2023[op1617],Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x6b ; op1617 & op2023 & Rd2427 & Rd2831 & op1819=0x0\n{\n\t# Rd2831 = op2023[op1617](Rd2427,Rd0811,Rd1215);\n\tlocal op2:4 = op2023;\n\tlocal proc:4 = op1617;\n\tRd2831 = coprocessor(op2, proc, Rd2427, Rd0811, Rd1215);\n}\n\n@if defined(TRICORE_V2)\n# CRC32 D[c], D[b], D[a] (RR)\n:crc32 Rd2831,Rd1215,Rd0811 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x30\n{\n\t#TODO crc of Rd0811 and the inverse of Rd1215 into Rd2831\n\t# crc is crc32, initial value of Rd1215 should be zero\n\tRd2831 = crc32(Rd1215, Rd0811);\n}\n@endif\n\n# CSUB D[c], D[d], D[a], D[b] (RRR)\n:csub Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x20\n{\n\tlocal result:4;\n\tternary(result, Rd2427 != 0, Rd0811 - Rd1215, Rd0811);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n# CSUBN D[c], D[d], D[a], D[b] (RRR)\n:csubn Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x30\n{\n\tlocal result:4;\n\tternary(result, Rd2427 != 0, Rd0811, Rd1215);\n\toverflowflags(result);\n\tRd2831 = result;\n}\n\n# DEBUG (SR)\n:debug is PCPMode=0 & op0007=0x0 & op0815=0xa0\n{\n\tif ($(DBGSR_DE) == 0) goto inst_next;\n\tdebug();\n}\n\n# DEBUG (SYS)\n:debug is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x100\n{\n\tif ($(DBGSR_DE) == 0) goto inst_next;\n\tdebug();\n}\n\n# DEXTR D[c], D[a], D[b], pos (RRPW)\n:dextr Rd2831,Rd0811,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x77 ; Rd2831 & const2327Z & op1622=0x0\n{\n\tlocal shift = const2327Z;\n\tRd2831 = (Rd0811 << shift) | (Rd1215 >> (32 - shift));\n}\n\n# DEXTR D[c], D[a], D[b], D[d] (RRRR)\n:dextr Rd2831,Rd0811,Rd1215,Rd2427 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x17 ; Rd2427 & Rd2831 & op1623=0x80\n{\n\tlocal shift = Rd2427[0,5];\n\tRd2831 = (Rd0811 << shift) | (Rd1215 >> (32 - shift));\n}\n\n# DISABLE (SYS)\n:disable is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x340\n{\n\t$(ICR_IE) = 0;\n}\n\n@if defined(TRICORE_V2)\n# DISABLE D[a] (SYS)\n:disable Rd0811 is PCPMode=0 & Rd0811 & op0007=0xd & op1215=0x0 ; op1631=0x3c0\n{\n\tRd0811 = zext($(ICR_IE));\n\t$(ICR_IE) = 0;\n}\n@endif\n\n# DIV E[c], D[a], D[b] (RR)\n:div Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x201\n{\n\t#TODO divide\n\t#TODO flags\n\tlocal divres = Rd0811 s/ Rd1215;\n\tlocal divmod = Rd0811 s% Rd1215;\n\tRee2831 = divres;\n\tReo2831 = divmod;\n}\n\n# DIV.U E[c], D[a], D[b] (RR)\n:div.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x211\n{\n\t#TODO divide\n\t#TODO flags\n\tlocal divres = Rd0811 / Rd1215;\n\tlocal divmod = Rd0811 % Rd1215;\n\tRee2831 = divres;\n\tReo2831 = divmod;\n}\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DIV.F D[c], D[a], D[b] (RR)\n:div.f Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x51\n{\n\t#TODO float\n\t#TODO divide\n\t#TODO flags\n\tRd2831 = Rd0811 f/ Rd1215;\n}\n@endif\n\n# DSYNC (SYS)\n:dsync is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x480\n{\n\tdsync();\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVADJ E[c], E[d], D[b] (RRR)\n:dvadj Ree2831/Reo2831,Ree2427/Reo2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & op1623=0xd0\n{\n\t#TODO divide sequence\n\tlocal q_sign = Reo2427[31,1] ^ Rd1215[31,1];\n\tlocal x_sign = Reo2427[31,1];\n\tlocal eq_pos = x_sign & (Reo2427 == Rd1215);\n\tlocal eq_neg = x_sign & (Reo2427 == -Rd1215);\n\tlocal quotient:4;\n\tternary(quotient, ((q_sign & ~eq_neg) | eq_pos), Ree2427 + 1, Ree2427);\n\tlocal remainder:4;\n\tternary(remainder, (eq_pos | eq_neg), 0, Reo2427);\n\tlocal absReo2427:4; int_abs(absReo2427, Reo2427);\n\tlocal absRd1215:4; int_abs(absRd1215, Rd1215);\n\tlocal _gt = absReo2427 > absRd1215;\n\tlocal _eq = !x_sign && (absReo2427 == absRd1215);\n\tternary(Reo2831, (_eq | _gt) != 0, 0, remainder);\n\tternary(Ree2831, (_eq | _gt) != 0, 0, quotient);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVINIT E[c], D[a], D[b] (RR)\n:dvinit Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x1a0\n{\n\t#TODO divide sequence\n\tlocal dividend:4 = Rd0811;\n\tlocal divisor:4 = Rd1215;\n\n\tRee2831 = dividend;\n\tReo2831 = 0xFFFFFFFF * zext(dividend[31,1]);\n\n\t$(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0x80000000)));\n\t$(PSW_SV) = $(PSW_V) | $(PSW_SV);\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVINIT.B E[c], D[a], D[b] (RR)\n:dvinit.b Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x5a0\n{\n\t#TODO divide sequence\n\tlocal dividend:4 = Rd0811;\n\tlocal divisor:4 = Rd1215;\n\tlocal quotient_sign = !(dividend[31,1] == divisor[31,1]);\n\tRee2831 = (dividend << 24) | (0xFFFFFF * zext(quotient_sign));\n\tReo2831 = dividend s>> 8;\n\t$(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFFFF80)));\n\t$(PSW_SV) = $(PSW_V) | $(PSW_SV);\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVINIT.BU E[c], D[a], D[b] (RR)\n:dvinit.bu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x4a0\n{\n\t#TODO divide sequence\n\tlocal dividend:4 = Rd0811;\t\t# D[a]\n\tlocal divisor:4 = Rd1215;\t\t# D[b]\n\n\tRee2831 = dividend << 24;\n\tReo2831 = dividend >> 8;\n\t$(PSW_V) = (divisor == 0);\n\t$(PSW_SV) = $(PSW_V) | $(PSW_SV);\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVINIT.H E[c], D[a], D[b] (RR)\n:dvinit.h Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x3a0\n{\n\t#TODO divide sequence\n\tlocal dividend:4 = Rd0811;\t\t# D[a]\n\tlocal divisor:4 = Rd1215;\t\t# D[b]\n\tlocal quotient_sign = !(dividend[31,1] == divisor[31,1]);\n\n\tRee2831 = (dividend << 16) | (zext(quotient_sign) * 0xFFFF);\n\tReo2831 = dividend s>> 16;\n\t$(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFF8000)));\n\t$(PSW_SV) = $(PSW_V) | $(PSW_SV);\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVINIT.HU E[c], D[a], D[b] (RR)\n:dvinit.hu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x2a0\n{\n\t#TODO divide sequence\n\tlocal dividend:4 = Rd0811;\t\t# D[a]\n\tlocal divisor:4 = Rd1215;\t\t# D[b]\n\n\tRee2831 = dividend << 16;\n\tReo2831 = dividend >> 16;\n\t$(PSW_V) = (divisor == 0);\n\t$(PSW_SV) = $(PSW_V) | $(PSW_SV);\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVINIT.U E[c], D[a], D[b] (RR)\n:dvinit.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0xa0\n{\n\t#TODO divide sequence\n\tlocal dividend:4 = Rd0811;\t\t# D[a]\n\tlocal divisor:4 = Rd1215;\t\t# D[b]\n\n\tRee2831 = dividend;\n\tReo2831 = 0;\n\t$(PSW_V) = (divisor == 0);\n\t$(PSW_SV) = $(PSW_V) | $(PSW_SV);\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVSTEP E[c], E[d], D[b] (RRR)\n:dvstep Ree2831/Reo2831,Ree2427/Reo2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & op1623=0xf0\n{\n\t#TODO divide sequence\n\tlocal dividend_sign = Reo2427[31,1] == 1;\n\tlocal divisor_sign = Rd1215[31,1] == 1;\n\tlocal quotient_sign = dividend_sign != divisor_sign;\n\tlocal addend:4;\n\tternary(addend, quotient_sign != 0, Rd1215, 0 - Rd1215);\n\tlocal dividend_quotient:4 = Ree2427;\n\tlocal remainder:4 = Reo2427;\n\tlocal temp:4 = 0;\n\tlocal index:1 = 0;\n \n\tremainder = (remainder << 1) | zext(dividend_quotient[31,1]);\n\tdividend_quotient = dividend_quotient << 1;\n\ttemp = remainder + addend;\n\tternary(remainder, (temp s< 0) == dividend_sign, temp, remainder);\n\tternary(temp, (temp s< 0) == dividend_sign, zext(!quotient_sign), zext(quotient_sign));\n\tdividend_quotient = dividend_quotient | temp;\n\tindex = index + 1;\n\tif (index < 8) goto ;\n\tReo2831 = remainder;\n\tRee2831 = dividend_quotient;\n}\n@endif\n\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# DVSTEP.U E[c], E[d], D[b] (RRR)\n:dvstep.u Ree2831/Reo2831,Ree2427/Reo2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & op1623=0xe0\n{\n\t#TODO divide sequence\n\tlocal divisor = Rd1215;\n\tlocal dividend_quotient = Ree2427;\n\tlocal remainder = Reo2427;\n\tlocal temp:4 = 0;\n\tlocal index:1 = 0;\n \n\tremainder = (remainder << 1) | zext(dividend_quotient[31,1]);\n\tdividend_quotient = dividend_quotient << 1;\n\ttemp = remainder - divisor;\n\tternary(remainder, temp s< 0, remainder, temp);\n\tdividend_quotient = dividend_quotient | zext(!(temp s< 0));\n\tindex = index + 1;\n\tif (index < 8) goto ;\n\tReo2427 = remainder;\n\tRee2427 = dividend_quotient;\n}\n@endif\n\n# ENABLE (SYS)\n:enable is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x300\n{\n\t$(ICR_IE) = 1;\n}\n\n# EQ D[15], D[a], D[b] (SRR)\n:eq d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x3a\n{\n\td15 = zext(Rd0811 == Rd1215);\n}\n\n# EQ D[15], D[a], const4 (SRC)\n:eq d15,Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xba\n{\n\td15 = zext(Rd0811 == const1215S);\n}\n\n# EQ D[c], D[a], D[b] (RR)\n:eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x100\n{\n\tRd2831 = zext(Rd0811 == Rd1215);\n}\n\n# EQ D[c], D[a], const9 (RC)\n:eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x10 ) & const1220S\n{\n\tRd2831 = zext(Rd0811 == const1220S);\n}\n\n# EQ.A D[c], A[a], A[b] (RR)\n:eq.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x400\n{\n\tRd2831 = zext(Ra0811 == Ra1215);\n}\n\n# EQ.B D[c], D[a], D[b] (RR)\n:eq.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x500\n{\n\tlocal result3:4 = 0xff * zext(Rd0811[24,8] == Rd1215[24,8]);\n\tlocal result2:4 = 0xff * zext(Rd0811[16,8] == Rd1215[16,8]);\n\tlocal result1:4 = 0xff * zext(Rd0811[8,8] == Rd1215[8,8]);\n\tlocal result0:4 = 0xff * zext(Rd0811[0,8] == Rd1215[0,8]);\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# EQ.H D[c], D[a], D[b] (RR)\n:eq.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x700\n{\n\tlocal result1:4 = 0xffff * zext(Rd0811[16,16] == Rd1215[16,16]);\n\tlocal result0:4 = 0xffff * zext(Rd0811[0,16] == Rd1215[0,16]);\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# EQ.W D[c], D[a], D[b] (RR)\n:eq.w Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x900\n{\n\tRd2831 = 0xffffffff * zext(Rd0811 == Rd1215);\n}\n\n# EQANY.B D[c], D[a], D[b] (RR)\n:eqany.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x560\n{\n\tlocal result3 = Rd0811[24,8] == Rd1215[24,8];\n\tlocal result2 = Rd0811[16,8] == Rd1215[16,8];\n\tlocal result1 = Rd0811[8,8] == Rd1215[8,8];\n\tlocal result0 = Rd0811[0,8] == Rd1215[0,8];\n\tRd2831 = zext(result3 | result2 | result1 | result0);\n}\n\n# EQANY.B D[c], D[a], const9 (RC)\n:eqany.b Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x56 ) & const1220S\n{\n\tlocal result3 = Rd0811[24,8] == const1220S[24,8];\n\tlocal result2 = Rd0811[16,8] == const1220S[16,8];\n\tlocal result1 = Rd0811[8,8] == const1220S[8,8];\n\tlocal result0 = Rd0811[0,8] == const1220S[0,8];\n\tRd2831 = zext(result3 | result2 | result1 | result0);\n}\n\n# EQANY.H D[c], D[a], D[b] (RR)\n:eqany.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x760\n{\n\tlocal result1 = Rd0811[16,16] == Rd1215[16,16];\n\tlocal result0 = Rd0811[0,16] == Rd1215[0,16];\n\tRd2831 = zext(result1 | result0);\n}\n\n# EQANY.H D[c], D[a], const9 (RC)\n:eqany.h Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x76 ) & const1220S\n{\n\tlocal result1 = Rd0811[16,16] == const1220S[16,16];\n\tlocal result0 = Rd0811[0,16] == const1220S[0,16];\n\tRd2831 = zext(result1 | result0);\n}\n\n# EQZ.A D[c], A[a] (RR)\n:eqz.a Rd2831,Ra0811 is PCPMode=0 & Ra0811 & op0007=0x1 & op1215=0x0 ; Rd2831 & op1627=0x480\n{\n\tRd2831 = zext(Ra0811 == 0);\n}\n\n# EXTR D[c], D[a], E[d] (RRRR)\n:extr Rd2831,Rd0811,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & op0007=0x17 & op1215=0x0 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x40\n{\n\tlocal shift:4 = zext(Ree2427[0,5]);\n\tlocal tmp:4 = (Rd0811 << (32 - shift - zext(Reo2427[0,5]))) s>> (32 - zext(Reo2427[0,5]));\n\tRd2831 = tmp;\n}\n\n# EXTR D[c], D[a], pos, width (RRPW)\n:extr Rd2831,Rd0811,const2327Z,const1620Z is PCPMode=0 & Rd0811 & op0007=0x37 & op1215=0x0 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal shift:4 = const2327Z;\n\tlocal tmp:4 = (Rd0811 << (32 - shift - const1620Z)) s>> (32 - const1620Z);\n\tRd2831 = tmp;\n}\n\n# EXTR D[c], D[a], D[d], width (RRRW)\n:extr Rd2831,Rd0811,Rd2427,const1620Z is PCPMode=0 & Rd0811 & op0007=0x57 & op1215=0x0 ; Rd2427 & Rd2831 & const1620Z & op2123=0x2\n{\n\tlocal shift:4 = zext(Rd2427[0,5]);\n\tlocal tmp:4 = (Rd0811 << (32 - shift - const1620Z)) s>> (32 - const1620Z);\n\tRd2831 = tmp;\n}\n\n# EXTR.U D[c], D[a], E[d] (RRRR)\n:extr.u Rd2831,Rd0811,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & op0007=0x17 & op1215=0x0 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x60\n{\n\tlocal tmp:4 = Rd0811 >> Ree2427[0,5];\n\tlocal mask:4 = (1 << Reo2427[0,5]) - 1;\n\tRd2831 = tmp & mask;\n}\n\n# EXTR.U D[c], D[a], pos, width (RRPW)\n:extr.u Rd2831,Rd0811,const2327Z,const1620Z is PCPMode=0 & Rd0811 & op0007=0x37 & op1215=0x0 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal tmp:4 = Rd0811 >> const2327Z;\n\tlocal mask:4 = (1 << const1620Z) - 1;\n\tRd2831 = tmp & mask;\n}\n\n# EXTR.U D[c], D[a], D[d], width (RRRW)\n:extr.u Rd2831,Rd0811,Rd2427,const1620Z is PCPMode=0 & Rd0811 & op0007=0x57 & op1215=0x0 ; Rd2427 & Rd2831 & const1620Z & op2123=0x3\n{\n\tlocal tmp:4 = Rd0811 >> Rd2427[0,5];\n\tlocal mask:4 = (1 << const1620Z) - 1;\n\tRd2831 = tmp & mask;\n}\n\n@if defined(TRICORE_V2)\n# FCALL disp24 (B)\n:fcall off24pc is PCPMode=0 & ( op0007=0x61 ) ... & off24pc\n{\n\t#TODO call\n\ta10 = a10 - 4;\n\t*[ram]:4 a10 = a11;\n\ta11 = inst_next;\n\tcall off24pc;\n}\n@endif\n\n@if defined(TRICORE_V2)\n# CALLA disp24 (B)\n:fcalla off24abs is PCPMode=0 & ( op0007=0xe1 ) ... & off24abs\n{\n\t#TODO call\n\ta10 = a10 - 4;\n\t*[ram]:4 a10 = a11;\n\ta11 = inst_next;\n\tcall off24abs;\n}\n@endif\n\n@if defined(TRICORE_V2)\n# FCALLI A[a] (RR)\n:fcalli Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x10\n{\n\t#TODO call\n\ta10 = a10 - 4;\n\t*[ram]:4 a10 = a11;\n\ta11 = inst_next;\n\tlocal tmp:4 = Ra0811 & 0xFFFFFFFE;\n\tcall [tmp];\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FRET (SR)\n:fret is PCPMode=0 & op0007=0x0 & op0811=0x0 & op1215=0x7\n{\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\ta11 = *[ram]:4 a10;\n\ta10 = a10 + 4;\n\treturn [tmp];\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FRET (SYS)\n:fret is PCPMode=0 & op0007=0x0d & op0815=0x0 ; op1621=0x0 & op2227=0x3 & op2831=0x0\n{\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\ta11 = *[ram]:4 a10;\n\ta10 = a10 + 4;\n\treturn [tmp];\n}\n@endif\n\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FTOI D[c], D[a] (RR)\n:ftoi Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x101\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = trunc(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FTOIZ D[c], D[a] (RR)\n:ftoiz Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x131\n{\n\t#TODO float\n\t#TODO flags\n\t#TODO round\n\tRd2831 = floor(trunc(Rd0811));\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FTOQ31 D[c], D[a], D[b] (RR)\n:ftoq31 Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x111\n{\n\t#TODO float\n\t#TODO flags\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FTOQ31Z D[c], D[a], D[b] (RR)\n:ftoq31z Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x181\n{\n\t#TODO float\n\t#TODO flags\n\t#TODO round\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FTOU D[c], D[a] (RR)\n:ftou Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x121\n{\n\t#TODO float\n\t#TODO flags\n\t#TODO unsigned\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# FTOUZ D[c], D[a] (RR)\n:ftouz Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x171\n{\n\t#TODO float\n\t#TODO flags\n\t#TODO unsigned\n\t#TODO round\n}\n@endif\n\n# GE D[c], D[a], D[b] (RR)\n:ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x140\n{\n\tRd2831 = zext(Rd0811 s>= Rd1215);\n}\n\n# GE D[c], D[a], const9 (RC)\n:ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x14 ) & const1220S\n{\n\tRd2831 = zext(Rd0811 s>= const1220S);\n}\n\n# GE.A D[c], A[a], A[b] (RR)\n:ge.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x430\n{\n\tRd2831 = zext(Ra0811 >= Ra1215);\n}\n\n# GE.U D[c], D[a], D[b] (RR)\n:ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x150\n{\n\tRd2831 = zext(Rd0811 >= Rd1215);\n}\n\n# GE.U D[c], D[a], const9 (RC)\n:ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x15 ) & const1220Z\n{\n\tRd2831 = zext(Rd0811 >= const1220Z);\n}\n\n# IMASK E[c], D[b], pos, width (RRPW)\n:imask Ree2831/Reo2831,Rd1215,const2327Z,const1620Z is PCPMode=0 & Rd1215 & op0007=0x37 & op0811=0x0 ; Ree2831 & Reo2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp:4 = 1;\n\tlocal tmp2:4 = Rd1215;\n\ttmp = (tmp << const1620Z) - 1;\n\tReo2831 = tmp << const2327Z;\n\tRee2831 = tmp2 << const2327Z;\n}\n\n# IMASK E[c], D[b], D[d], width (RRRW)\n:imask Ree2831/Reo2831,Rd1215,Rd2427,const1620Z is PCPMode=0 & Rd1215 & op0007=0x57 & op0811=0x0 ; Rd2427 & Ree2831 & Reo2831 & const1620Z & op2123=0x1\n{\n\tlocal tmp:4 = 1;\n\tlocal tmp2:4 = Rd1215;\n\tlocal tmp3:4 = Rd2427;\n\ttmp = (tmp << const1620Z) - 1;\n\tReo2831 = tmp << tmp3[0,5];\n\tRee2831 = tmp2 << tmp3[0,5];\n}\n\n# IMASK E[c], const4, pos, width (RCPW)\n:imask Ree2831/Reo2831,const1215Z,const2327Z,const1620Z is PCPMode=0 & const1215Z & op0007=0xb7 & op0811=0x0 ; Ree2831 & Reo2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << const1620Z) - 1;\n\tReo2831 = tmp << const2327Z;\n\tRee2831 = const1215Z << const2327Z;\n}\n\n# IMASK E[c], const4, D[d], width (RCRW)\n:imask Ree2831/Reo2831,const1215Z,Rd2427,const1620Z is PCPMode=0 & const1215Z & op0007=0xd7 & op0811=0x0 ; Rd2427 & Ree2831 & Reo2831 & const1620Z & op2123=0x1\n{\n\tlocal tmp:4 = 1;\n\tlocal tmp2:4 = Rd2427;\n\ttmp = (tmp << const1620Z) - 1;\n\tReo2831 = tmp << tmp2[0,5];\n\tRee2831 = const1215Z << tmp2[0,5];\n}\n\n# INS.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:ins.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x67 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmp:4 = Rd0811 & ~(1 << const1620Z);\n\tRd2831 = tmp | (((Rd1215 >> const2327Z) & 1) << const1620Z);\n}\n\n# INSERT D[c], D[a], D[b], E[d] (RRRR)\n:insert Rd2831,Rd0811,Rd1215,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x17 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x0\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << Reo2427) - 1;\n\ttmp = tmp << Ree2427[0,5];\n\tRd2831 = (Rd0811 & ~tmp) | ((Rd1215 << Ree2427[0,5]) & tmp);\n}\n\n# INSERT D[c], D[a], D[b], pos, width (RRPW)\n:insert Rd2831,Rd0811,Rd1215,const2327Z,const1620Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x37 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << const1620Z) - 1;\n\ttmp = tmp << const2327Z;\n\tRd2831 = (Rd0811 & ~tmp) | ((Rd1215 << const2327Z) & tmp);\n}\n\n# INSERT D[c], D[a], D[b], D[d], width (RRRW)\n:insert Rd2831,Rd0811,Rd1215,Rd2427,const1620Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x57 ; Rd2427 & Rd2831 & const1620Z & op2123=0x0\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << const1620Z) - 1;\n\ttmp = tmp << Rd2427[0,5];\n\tRd2831 = (Rd0811 & ~tmp) | ((Rd1215 << Rd2427[0,5]) & tmp);\n}\n\n# INSERT D[c], D[a], const4, E[d] (RCRR)\n:insert Rd2831,Rd0811,const1215Z,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & const1215Z & op0007=0x97 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x0\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << Reo2427) - 1;\n\ttmp = tmp << Ree2427[0,5];\n\tRd2831 = (Rd0811 & ~tmp) | ((const1215Z << Ree2427[0,5]) & tmp);\n}\n\n# INSERT D[c], D[a], const4, pos, width (RCPW)\n:insert Rd2831,Rd0811,const1215Z,const2327Z,const1620Z is PCPMode=0 & Rd0811 & const1215Z & op0007=0xb7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << const1620Z) - 1;\n\ttmp = tmp << const2327Z;\n\tRd2831 = (Rd0811 & ~tmp) | ((const1215Z << const2327Z) & tmp);\n}\n\n# INSERT D[c], D[a], const4, D[d], width (RCRW)\n:insert Rd2831,Rd0811,const1215Z,Rd2427,const1620Z is PCPMode=0 & Rd0811 & const1215Z & op0007=0xd7 ; Rd2427 & Rd2831 & const1620Z & op2123=0x0\n{\n\tlocal tmp:4 = 1;\n\ttmp = (tmp << const1620Z) - 1;\n\ttmp = tmp << Rd2427[0,5];\n\tRd2831 = (Rd0811 & ~tmp) | ((const1215Z << Rd2427[0,5]) & tmp);\n}\n\n# INSN.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:insn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x67 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp:4 = Rd0811 & ~(1 << const1620Z);\n\tRd2831 = tmp | (((~Rd1215 >> const2327Z) & 1) << const1620Z);\n}\n\n# ISYNC (SYS)\n:isync is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x4c0\n{\n\tisync();\n}\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ITOF D[c], D[a] (RR)\n:itof Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x141\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = int2float(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# IXMAX E[c], E[d], D[b] (RRR)\n:ixmax Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0xa0\n{\n\tlocal tmp:8 = Re2427;\n\tlocal tmp2:4 = Rd1215;\n\tRe2831[0,16] = tmp[0,16] + 2;\n\tRe2831[48,16] = 0;\n\tlocal cond1 = (tmp2[0,16] s>= tmp2[16,16]) && (tmp2[0,16] s> tmp[32,16]);\n\tif (cond1) goto <_first>;\n\tlocal cond2 = (tmp2[16,16] s> tmp2[0,16]) && (tmp2[16,16] s> tmp[32,16]);\n\tif (cond2) goto <_second>;\n\tRe2831[32,16] = tmp[32,16];\n\tRe2831[16,16] = tmp[16,16];\n\tgoto inst_next;\n <_first>\n\tRe2831[32,16] = tmp2[0,16];\n\tRe2831[16,16] = tmp[0,16];\n\tgoto inst_next;\n <_second>\n\tRe2831[32,16] = tmp2[16,16];\n\tRe2831[16,16] = tmp[0,16] + 1;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# IXMAX.U E[c], E[d], D[b] (RRR)\n:ixmax.u Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0xb0\n{\n\tlocal tmp:8 = Re2427;\n\tlocal tmp2:4 = Rd1215;\n\tRe2831[0,16] = tmp[0,16] + 2;\n\tRe2831[48,16] = 0;\n\tlocal cond1 = (tmp2[0,16] >= tmp2[16,16]) && (tmp2[0,16] > tmp[32,16]);\n\tif (cond1) goto <_first>;\n\tlocal cond2 = (tmp2[16,16] > tmp2[0,16]) && (tmp2[16,16] > tmp[32,16]);\n\tif (cond2) goto <_second>;\n\tRe2831[32,16] = tmp[32,16];\n\tRe2831[16,16] = tmp[16,16];\n\tgoto inst_next;\n <_first>\n\tRe2831[32,16] = tmp2[0,16];\n\tRe2831[16,16] = tmp[0,16];\n\tgoto inst_next;\n <_second>\n\tRe2831[32,16] = tmp2[16,16];\n\tRe2831[16,16] = tmp[0,16] + 1;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# IXMIN E[c], E[d], D[b] (RRR)\n:ixmin Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0x80\n{\n\tlocal tmp:8 = Re2427;\n\tlocal tmp2:4 = Rd1215;\n\tRe2831[0,16] = tmp[0,16] + 2;\n\tRe2831[48,16] = 0;\n\tlocal cond1 = (tmp2[0,16] s<= tmp2[16,16]) && (tmp2[0,16] s< tmp[32,16]);\n\tif (cond1) goto <_first>;\n\tlocal cond2 = (tmp2[16,16] s< tmp2[0,16]) && (tmp2[16,16] s< tmp[32,16]);\n\tif (cond2) goto <_second>;\n\tRe2831[32,16] = tmp[32,16];\n\tRe2831[16,16] = tmp[16,16];\n\tgoto inst_next;\n <_first>\n\tRe2831[32,16] = tmp2[0,16];\n\tRe2831[16,16] = tmp[0,16];\n\tgoto inst_next;\n <_second>\n\tRe2831[32,16] = tmp2[16,16];\n\tRe2831[16,16] = tmp[0,16] + 1;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# IXMIN.U E[c], E[d], D[b] (RRR)\n:ixmin.u Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0x90\n{\n\tlocal tmp:8 = Re2427;\n\tlocal tmp2:4 = Rd1215;\n\tRe2831[0,16] = tmp[0,16] + 2;\n\tRe2831[48,16] = 0;\n\tlocal cond1 = (tmp2[0,16] <= tmp2[16,16]) && (tmp2[0,16] < tmp[32,16]);\n\tif (cond1) goto <_first>;\n\tlocal cond2 = (tmp2[16,16] < tmp2[0,16]) && (tmp2[16,16] < tmp[32,16]);\n\tif (cond2) goto <_second>;\n\tRe2831[32,16] = tmp[32,16];\n\tRe2831[16,16] = tmp[16,16];\n\tgoto inst_next;\n <_first>\n\tRe2831[32,16] = tmp2[0,16];\n\tRe2831[16,16] = tmp[0,16];\n\tgoto inst_next;\n <_second>\n\tRe2831[32,16] = tmp2[16,16];\n\tRe2831[16,16] = tmp[0,16] + 1;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# J disp8 (SB)\n:j off0815pc8s is PCPMode=0 & off0815pc8s & op0007=0x3c\n{\n\tgoto off0815pc8s;\n}\n@endif\n\n# J disp24 (B)\n:j off24pc is PCPMode=0 & ( op0007=0x1d ) ... & off24pc\n{\n\tgoto off24pc;\n}\n\n# JA disp24 (B)\n:ja off24abs is PCPMode=0 & ( op0007=0x9d ) ... & off24abs\n{\n\tgoto off24abs;\n}\n\n@if defined(TRICORE_V2)\n# JEQ D[15], D[b], disp4 (SBR)\n:jeq d15,Rd1215,off0811pc4z16 is PCPMode=0 & Rd1215 & d15 & off0811pc4z16 & op0007=0xbe\n{\n\tif (d15 == Rd1215) goto off0811pc4z16;\n}\n@endif\n\n@if defined(TRICORE_V2)\n# JEQ D[15], const4, disp4 (SBC)\n:jeq d15,const1215S,off0811pc4z16 is PCPMode=0 & const1215S & d15 & off0811pc4z16 & op0007=0x9e\n{\n\tif (d15 == const1215S) goto off0811pc4z16;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JEQ D[15], D[b], disp4 (SBR)\n:jeq d15,Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & d15 & off0811pc4z & op0007=0x3e\n{\n\tif (d15 == Rd1215) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JEQ D[15], const4, disp4 (SBC)\n:jeq d15,const1215S,off0811pc4z is PCPMode=0 & const1215S & d15 & off0811pc4z & op0007=0x1e\n{\n\tif (d15 == const1215S) goto off0811pc4z;\n}\n@endif\n\n# JEQ D[a], D[b], disp15 (BRR)\n:jeq Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x5f ; off1630pc15s & op3131=0x0\n{\n\tif (Rd0811 == Rd1215) goto off1630pc15s;\n}\n\n# JEQ D[a], const4, disp15 (BRC)\n:jeq Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xdf ; off1630pc15s & op3131=0x0\n{\n\tif (Rd0811 == const1215S) goto off1630pc15s;\n}\n\n# JEQ.A A[a], A[b], disp15 (BRR)\n:jeq.a Ra0811,Ra1215,off1630pc15s is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x7d ; off1630pc15s & op3131=0x0\n{\n\tif (Ra0811 == Ra1215) goto off1630pc15s;\n}\n\n# JGE D[a], D[b], disp15 (BRR)\n:jge Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7f ; off1630pc15s & op3131=0x0\n{\n\tif (Rd0811 s>= Rd1215) goto off1630pc15s;\n}\n\n# JGE D[a], const4, disp15 (BRC)\n:jge Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xff ; off1630pc15s & op3131=0x0\n{\n\tif (Rd0811 s>= const1215S) goto off1630pc15s;\n}\n\n# JGE.U D[a], D[b], disp15 (BRR)\n:jge.u Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7f ; off1630pc15s & op3131=0x1\n{\n\tif (Rd0811 >= Rd1215) goto off1630pc15s;\n}\n\n# JGE.U D[a], const4, disp15 (BRC)\n:jge.u Rd0811,const1215Z,off1630pc15s is PCPMode=0 & Rd0811 & const1215Z & op0007=0xff ; off1630pc15s & op3131=0x1\n{\n\tif (Rd0811 >= const1215Z) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JGEZ D[b], disp4 (SBR)\n:jgez Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0xce\n{\n\tif (Rd1215 s>= 0) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2)\n# JGTZ D[b], disp4 (SBR)\n:jgtz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0x4e\n{\n\tif (Rd1215 s> 0) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JI A[a] (SR)\n:ji Ra0811 is PCPMode=0 & Ra0811 & op0007=0xdc & op1215=0x0\n{\n\tlocal tmp:4 = Ra0811;\n\ttmp[0,1] = 0;\n\tgoto [tmp];\n}\n:ji a11 is PCPMode=0 & op0811=11 & op0007=0xdc & op1215=0x0 & a11\n{\n\treturn [a11];\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JI A[a] (RR)\n:ji Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x30\n{\n\tlocal tmp:4 = Ra0811;\n\ttmp[0,1] = 0;\n\tgoto [tmp];\n}\n:ji a11 is PCPMode=0 & op0811=11 & op0007=0x2d & op1215=0x0 & a11; op1631=0x30\n{\n\treturn [a11];\n}\n@endif\n\n# JL disp24 (B)\n:jl off24pc is PCPMode=0 & ( op0007=0x5d ) ... & off24pc\n{\n\t#TODO is this just a call w/o context switching?\n\ta11 = inst_next;\n\tcall off24pc;\n}\n\n# JLA disp24 (B)\n:jla off24abs is PCPMode=0 & ( op0007=0xdd ) ... & off24abs\n{\n\t#TODO is this just a call w/o context switching?\n\ta11 = inst_next;\n\tcall off24abs;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JLEZ D[b], disp4 (SBR)\n:jlez Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0x8e\n{\n\tif (Rd1215 s<= 0) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JLI A[a] (RR)\n:jli Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x20\n{\n\ta11 = inst_start + 4;\n\tlocal tmp:4 = Ra0811 & 0xFFFFFFFE;\n\tcall [tmp];\n}\n@endif\n\n# JLT D[a], D[b], disp15 (BRR)\n:jlt Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3f ; off1630pc15s & op3131=0x0\n{\n\tif (Rd0811 s< Rd1215) goto off1630pc15s;\n}\n\n# JLT D[a], const4, disp15 (BRC)\n:jlt Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xbf ; off1630pc15s & op3131=0x0\n{\n\tif (Rd0811 s< const1215S) goto off1630pc15s;\n}\n\n# JLT.U D[a], D[b], disp15 (BRR)\n:jlt.u Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3f ; off1630pc15s & op3131=0x1\n{\n\tif (Rd0811 < Rd1215) goto off1630pc15s;\n}\n\n# JLT.U D[a], const4, disp15 (BRC)\n:jlt.u Rd0811,const1215Z,off1630pc15s is PCPMode=0 & Rd0811 & const1215Z & op0007=0xbf ; off1630pc15s & op3131=0x1\n{\n\tif (Rd0811 < const1215Z) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2)\n# JLTZ D[b], disp4 (SBR)\n:jltz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0xe\n{\n\tif (Rd1215 s< 0) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_V2)\n# JNE D[15], D[b], disp4 (SBR)\n:jne d15,Rd1215,off0811pc4z16 is PCPMode=0 & Rd1215 & d15 & off0811pc4z16 & op0007=0xfe\n{\n\tif (d15 != Rd1215) goto off0811pc4z16;\n}\n@endif\n\n@if defined(TRICORE_V2)\n# JNE D[15], const4, disp4 (SBC)\n:jne d15,const1215S,off0811pc4z16 is PCPMode=0 & const1215S & d15 & off0811pc4z16 & op0007=0xde\n{\n\tif (d15 != const1215S) goto off0811pc4z16;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JNE D[15], D[b], disp4 (SBR)\n:jne d15,Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & d15 & off0811pc4z & op0007=0x7e\n{\n\tif (d15 != Rd1215) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JNE D[15], const4, disp4 (SBC)\n:jne d15,const1215S,off0811pc4z is PCPMode=0 & const1215S & d15 & off0811pc4z & op0007=0x5e\n{\n\tif (d15 != const1215S) goto off0811pc4z;\n}\n@endif\n\n# JNE D[a], D[b], disp15 (BRR)\n:jne Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x5f ; off1630pc15s & op3131=0x1\n{\n\tif (Rd0811 != Rd1215) goto off1630pc15s;\n}\n\n# JNE D[a], const4, disp15 (BRC)\n:jne Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xdf ; off1630pc15s & op3131=0x1\n{\n\tif (Rd0811 != const1215S) goto off1630pc15s;\n}\n\n# JNE.A A[a], A[b], disp15 (BRR)\n:jne.a Ra0811,Ra1215,off1630pc15s is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x7d ; off1630pc15s & op3131=0x1\n{\n\tif (Ra0811 != Ra1215) goto off1630pc15s;\n}\n\n# JNED D[a], D[b], disp15 (BRR)\n:jned Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x1f ; off1630pc15s & op3131=0x1\n{\n\tlocal tmp = Rd0811;\n\tRd0811 = Rd0811 - 1;\n\tif (tmp != Rd1215) goto off1630pc15s;\n}\n\n# JNED D[a], const4, disp15 (BRC)\n:jned Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0x9f ; off1630pc15s & op3131=0x1\n{\n\tlocal tmp = Rd0811;\n\tRd0811 = Rd0811 - 1;\n\tif (tmp != const1215S) goto off1630pc15s;\n}\n\n# JNEI D[a], D[b], disp15 (BRR)\n:jnei Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x1f ; off1630pc15s & op3131=0x0\n{\n\tlocal tmp = Rd0811;\n\tRd0811 = Rd0811 + 1;\n\tif (tmp != Rd1215) goto off1630pc15s;\n}\n\n# JNEI D[a], const4, disp15 (BRC)\n:jnei Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0x9f ; off1630pc15s & op3131=0x0\n{\n\tlocal tmp = Rd0811;\n\tRd0811 = Rd0811 - 1;\n\tif (tmp != const1215S) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JNZ D[15], disp8 (SB)\n:jnz d15,off0815pc8s is PCPMode=0 & d15 & off0815pc8s & op0007=0xee\n{\n\tif (d15 != 0) goto off0815pc8s;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JNZ D[b], disp4 (SBR)\n:jnz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0xf6\n{\n\tif (Rd1215 != 0) goto off0811pc4z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2)\n# JNZ.A A[b], disp4 (SBR)\n:jnz.a Ra1215,off0811pc4z is PCPMode=0 & Ra1215 & off0811pc4z & op0007=0x7c\n{\n\tif (Ra1215 != 0) goto off0811pc4z;\n}\n@endif\n\n# JNZ.A A[a], disp15 (BRR)\n:jnz.a Ra0811,off1630pc15s is PCPMode=0 & Ra0811 & op0007=0xbd & op1215=0x0 ; off1630pc15s & op3131=0x1\n{\n\tif (Ra0811 != 0) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JNZ.T D[15], n, disp4 (SBRN)\n:jnz.t d15,const1215Z,off0811pc4z is PCPMode=0 & const1215Z & d15 & off0811pc4z & op0007=0xae\n{\n\tlocal tmp = d15 & (1 << const1215Z);\n\tif (tmp != 0) goto off0811pc4z;\n}\n@endif\n\n# JNZ.T D[a], n, disp15 (BRN)\n:jnz.t Rd0811,Nbit,off1630pc15s is PCPMode=0 & Nbit & Rd0811 & op0006=0x6f ; off1630pc15s & op3131=0x1\n{\n\tlocal tmp = Rd0811 & (1 << Nbit);\n\tif (tmp != 0) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JZ D[15], disp8 (SB)\n:jz d15,off0815pc8s is PCPMode=0 & d15 & off0815pc8s & op0007=0x6e\n{\n\tif (d15 == 0) goto off0815pc8s;\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2)\n# JZ D[b], disp4 (SBR)\n:jz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0x76\n{\n\tif (Rd1215 == 0) goto off0811pc4z;\n}\n@endif\n\n# JZ.A A[b], disp4 (SBR)\n:jz.a Ra1215,off0811pc4z is PCPMode=0 & Ra1215 & off0811pc4z & op0007=0xbc\n{\n\tif (Ra1215 == 0) goto off0811pc4z;\n}\n\n# JZ.A A[a], disp15 (BRR)\n:jz.a Ra0811,off1630pc15s is PCPMode=0 & Ra0811 & op0007=0xbd & op1215=0x0 ; off1630pc15s & op3131=0x0\n{\n\tif (Ra0811 == 0) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# JZ.T D[15], n, disp4 (SBRN)\n:jz.t d15,const1215Z,off0811pc4z is PCPMode=0 & const1215Z & d15 & off0811pc4z & op0007=0x2e\n{\n\tlocal tmp = d15 & (1 << const1215Z);\n\tif (tmp == 0) goto off0811pc4z;\n}\n@endif\n\n# JZ.T D[a], n, disp15 (BRN)\n:jz.t Rd0811,Nbit,off1630pc15s is PCPMode=0 & Nbit & Rd0811 & op0006=0x6f ; off1630pc15s & op3131=0x0\n{\n\tlocal tmp = Rd0811 & (1 << Nbit);\n\tif (tmp == 0) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.A A[15], A[10], const8 (SC)\n:ld.a a15,SC is PCPMode=0 & a15 & op0007=0xd8 & SC\n{\n\tbuild SC;\n\ta15 = *[ram]:4 SC;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.A A[c], A[15], off4 (SLRO)\n:ld.a Ra0811,SLRO is PCPMode=0 & Ra0811 & op0007=0xc8 & SLRO\n{\n\tbuild SLRO;\n\tRa0811 = *[ram]:4 SLRO;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.A A[15], A[b], off4 (SRO)\n:ld.a a15,SRO is PCPMode=0 & a15 & op0007=0xcc & SRO\n{\n\tbuild SRO;\n\ta15 = *[ram]:4 SRO;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.A A[c], A[b] (SLR)(Post-increment Addressing Mode)\n# LD.A A[c], A[b] (SLR)\n:ld.a Ra0811,SLR is PCPMode=0 & Ra0811 & op0607=0x3 & SLR\n{\n\tbuild SLR;\n\tRa0811 = *[ram]:4 SLR;\n}\n@endif\n\n# LD.A A[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:ld.a Ra0811,BOL is PCPMode=0 & ( Ra0811 & op0007=0x99 ) ... & BOL\n{\n\tbuild BOL;\n\tRa0811 = *[ram]:4 BOL;\n}\n\n# LD.A A[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.A A[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.A A[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.A A[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.A A[a], P[b] (BO)(Index Addressing Mode)\n:ld.a Ra0811,BO is PCPMode=0 & ( Ra0811 & op0607=0x0 ; op2225=0x6 ) & BO\n{\n\tbuild BO;\n\tRa0811 = *[ram]:4 BO;\n}\n\n# LD.A A[a], P[b], off10 (BO)(Circular Addressing Mode)\n#:ld.a Ra0811,BO is PCPMode=0 & ( Ra0811 & op0007=0x29 ; op2227=0x16 ) & BO\n:ld.a Ra0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Ra0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x16\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tRa0811 = *[ram]:4 EA;\n}\n\n# LD.A A[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.a Ra0811,off18 is PCPMode=0 & ( Ra0811 & op0007=0x85 ; op2627=0x2 ) & off18\n{\n\tRa0811 = *[ram]:4 off18;\n}\n\n# LD.B D[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.b Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x0 ) & off18\n{\n\tRd0811 = sext(*[ram]:1 off18);\n}\n\n# LD.B D[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.B D[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.B D[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.B D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.B D[a], P[b] (BO)(Index Addressing Mode)\n:ld.b Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x0 ) & BO\n{\n\tbuild BO;\n\tRd0811 = sext(*[ram]:1 BO);\n}\n\n# LD.B D[a], P[b], off10 (BO)(Circular Addressing Mode)\n#:ld.b Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x10 ) & BO\n:ld.b Rd0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x10\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tRd0811 = sext(*[ram]:1 EA);\n}\n\n# LD.B D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:ld.b Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0x79 ) ... & BOL\n{\n\tbuild BOL;\n\tRd0811 = sext(*[ram]:1 BOL);\n}\n\n# LD.BU D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:ld.bu Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0x39 ) ... & BOL\n{\n\tbuild BOL;\n\tRd0811 = zext(*[ram]:1 BOL);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.BU D[c], A[b] (SLR)\n# LD.BU D[c], A[b] (SLR)(Post-increment Addressing Mode)\n:ld.bu Rd0811,SLR is PCPMode=0 & Rd0811 & op0607=0x0 & SLR\n{\n\tbuild SLR;\n\tRd0811 = zext(*[ram]:1 SLR);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.BU D[15], A[b], off4 (SRO)\n:ld.bu d15,SRO is PCPMode=0 & d15 & op0007=0xc & SRO\n{\n\tbuild SRO;\n\td15 = zext(*[ram]:1 SRO);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.BU D[c], A[15], off4 (SLRO)\n:ld.bu Rd0811,SLRO is PCPMode=0 & Rd0811 & op0007=0x8 & SLRO\n{\n\tbuild SLRO;\n\tRd0811 = zext(*[ram]:1 SLRO);\n}\n@endif\n\n# LD.BU D[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.BU D[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.BU D[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.BU D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.BU D[a], P[b] (BO)(Index Addressing Mode)\n:ld.bu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x1 ) & BO\n{\n\tbuild BO;\n\tRd0811 = zext(*[ram]:1 BO);\n}\n\n# LD.BU D[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.bu Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x1 ) & off18\n{\n\tRd0811 = zext(*[ram]:1 off18);\n}\n\n# LD.BU D[a], P[b], off10 (BO)(Circular Addressing Mode)\n#:ld.bu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x11 ) & BO\n:ld.bu Rd0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x11\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tRd0811 = zext(*[ram]:1 EA);\n}\n\n# LD.D E[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.D E[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.D E[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.D E[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.D E[a], P[b] (BO)(Index Addressing Mode)\n:ld.d Re0811,BO is PCPMode=0 & ( Re0811 & op0607=0x0 ; op2225=0x5 ) & BO\n{\n\tbuild BO;\n\tRe0811 = *[ram]:8 BO;\n}\n\n# LD.D E[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.d Re0811,off18 is PCPMode=0 & ( Re0811 & op0007=0x85 ; op2627=0x1 ) & off18\n{\n\tRe0811 = *[ram]:8 off18;\n}\n\n# LD.D E[a], P[b], off10 (BO)(Circular Addressing Mode)\n#:ld.d Re0811,BO is PCPMode=0 & ( Re0811 & op0007=0x29 ; op2227=0x15 ) & BO\n:ld.d Re0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Re0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x15\n{\n\tlocal EA0:4;\n\tlocal EA2:4;\n\tlocal EA4:4;\n\tlocal EA6:4;\n\tCircularAddressingMode4(Rpe1215, Rpo1215, EA0, EA2, EA4, EA6, off10, 2);\n\tRe0811[48,16] = *[ram]:2 EA6;\n\tRe0811[32,16] = *[ram]:2 EA4;\n\tRe0811[16,16] = *[ram]:2 EA2;\n\tRe0811[0,16] = *[ram]:2 EA0;\n}\n\n# LD.DA P[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.DA P[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.DA P[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.DA P[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.DA P[a], P[b] (BO)(Index Addressing Mode)\n:ld.da Rp0811,BO is PCPMode=0 & ( Rp0811 & op0607=0x0 ; op2225=0x7 ) & BO\n{\n\tbuild BO;\n\tRp0811 = *[ram]:8 BO;\n}\n\n# LD.DA P[a], P[b], off10 (BO)(Circular Addressing Mode)\n#:ld.da Rpe0811/Rpo0811,BO is PCPMode=0 & ( Rpe0811 & Rpo0811 & op0007=0x29 ; op2227=0x17 ) & BO\n:ld.da Rpe0811/Rpo0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rpe0811 & Rpo0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x17\n{\n\tlocal EA0:4;\n\tlocal EA4:4;\n\tCircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA4, off10, 4);\n\tRpo0811 = *[ram]:4 EA4;\n\tRpe0811 = *[ram]:4 EA0;\n}\n\n# LD.DA P[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.da Rp0811,off18 is PCPMode=0 & ( Rp0811 & op0007=0x85 ; op2627=0x3 ) & off18\n{\n\tRp0811 = *[ram]:8 off18;\n}\n\n@if defined(TRICORE_V2)\n:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x9 ; op2227=0x9 ) & BO\n{\n\tbuild BO;\n\tRe0811 = *[ram]:8 BO;\n\tReN0811 = *[ram]:8 BO+8;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x29 ; op1621=0x0 & op2227=0x09 & op2831=0x0 ) & BO\n{\n\tbuild BO;\n\tRe0811 = *[ram]:8 BO;\n\tReN0811 = *[ram]:8 BO+8;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x9 ; op2227=0x19 ) & BO\n{\n\tbuild BO;\n\tRe0811 = *[ram]:8 BO;\n\tReN0811 = *[ram]:8 BO+8;\n}\n@endif\n\n@if defined(TRICORE_V2)\n#:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x29 ; op2227=0x19 ) & BO\n:ld.dd Re0811/ReN0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Re0811 & ReN0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x19\n{\n\tlocal EA0:4;\n\tlocal EA8:4;\n\tCircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA8, off10, 8);\n\tRe0811 = *[ram]:8 EA0;\n\tReN0811 = *[ram]:8 EA8;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x9 ; op2227=0x29 ) & BO\n{\n\tbuild BO;\n\tRe0811 = *[ram]:8 BO;\n\tReN0811 = *[ram]:8 BO+8;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x29 ; op1621=0x0 & op2227=0x29 & op2831=0x0 ) & BO\n{\n\tbuild BO;\n\tRe0811 = *[ram]:8 BO;\n\tReN0811 = *[ram]:8 BO+8;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.H D[c], A[b] (SLR)(Post-increment Addressing Mode)\n# LD.H D[c], A[b] (SLR)\n:ld.h Rd0811,SLR is PCPMode=0 & Rd0811 & op0607=0x2 & SLR\n{\n\tbuild SLR;\n\tRd0811 = sext(*[ram]:2 SLR);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.H D[15], A[b], off4 (SRO)\n:ld.h d15,SRO is PCPMode=0 & d15 & op0007=0x8c & SRO\n{\n\tbuild SRO;\n\td15 = sext(*[ram]:2 SRO);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.H D[c], A[15], off4 (SLRO)\n:ld.h Rd0811,SLRO is PCPMode=0 & Rd0811 & op0007=0x88 & SLRO\n{\n\tbuild SLRO;\n\tRd0811 = sext(*[ram]:2 SLRO);\n}\n@endif\n\n# LD.H D[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.H D[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.H D[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.H D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.H D[a], P[b] (BO)(Index Addressing Mode)\n:ld.h Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x2 ) & BO\n{\n\tbuild BO;\n\tRd0811 = sext(*[ram]:2 BO);\n}\n\n# LD.H D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:ld.h Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0xc9 ) ... & BOL\n{\n\tbuild BOL;\n\tRd0811 = sext(*[ram]:2 BOL);\n}\n\n#:ld.h Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x12 ) & BO\n:ld.h Rd0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x12\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tRd0811 = sext(*[ram]:2 EA);\n}\n\n# LD.H D[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.h Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x2 ) & off18\n{\n\tRd0811 = sext(*[ram]:2 off18);\n}\n\n# LD.HU D[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.HU D[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.HU D[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.HU D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.HU D[a], P[b] (BO)(Index Addressing Mode)\n:ld.hu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x3 ) & BO\n{\n\tbuild BO;\n\tRd0811 = zext(*[ram]:2 BO);\n}\n\n#:ld.hu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x13 ) & BO\n:ld.hu Rd0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x13\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tRd0811 = zext(*[ram]:2 EA);\n}\n\n# LD.HU D[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.hu Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x3 ) & off18\n{\n\tRd0811 = zext(*[ram]:2 off18);\n}\n\n# LD.HU D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:ld.hu Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0xb9 ) ... & BOL\n{\n\tbuild BOL;\n\tRd0811 = zext(*[ram]:2 BOL);\n}\n\n# LD.Q D[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.q Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x45 ; op2627=0x0 ) & off18\n{\n\tRd0811 = zext(*[ram]:2 off18) << 16;\n}\n\n# LD.Q D[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.Q D[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.Q D[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.Q D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.Q D[a], P[b] (BO)(Index Addressing Mode)\n:ld.q Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x8 ) & BO\n{\n\tbuild BO;\n\tRd0811 = zext(*[ram]:2 BO) << 16;\n}\n\n# LD.Q D[a], P[b], off10 (BO)(Circular Addressing Mode)\n#:ld.q Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x18 ) & BO\n:ld.q Rd0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x18\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tRd0811 = zext(*[ram]:2 EA) << 16;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.W D[15], A[10], const8 (SC)\n:ld.w d15,SC is PCPMode=0 & d15 & op0007=0x58 & SC\n{\n\tbuild SC;\n\td15 = *[ram]:4 SC;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.W D[c], A[b] (SLR)\n# LD.W D[c], A[b] (SLR)(Post-increment Addressing Mode)\n:ld.w Rd0811,SLR is PCPMode=0 & Rd0811 & op0607=0x1 & SLR\n{\n\tbuild SLR;\n\tRd0811 = *[ram]:4 SLR;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.W D[15], A[b], off4 (SRO)\n:ld.w d15,SRO is PCPMode=0 & d15 & op0007=0x4c & SRO\n{\n\tbuild SRO;\n\td15 = *[ram]:4 SRO;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LD.W D[c], A[15], off4 (SLRO)\n:ld.w Rd0811,SLRO is PCPMode=0 & Rd0811 & op0007=0x48 & SLRO\n{\n\tbuild SLRO;\n\tRd0811 = *[ram]:4 SLRO;\n}\n@endif\n\n# LD.W D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:ld.w Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0x19 ) ... & BOL\n{\n\tbuild BOL;\n\tRd0811 = *[ram]:4 BOL;\n}\n\n# LD.W D[a], off18 (ABS)(Absolute Addressing Mode)\n:ld.w Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x85 ; op2627=0x0 ) & off18\n{\n\tRd0811 = *[ram]:4 off18;\n}\n\n# LD.W D[a], A[b], off10 (BO)(Post-increment Addressing Mode)\n# LD.W D[a], P[b] (BO)(Bit-reverse Addressing Mode)\n# LD.W D[a], A[b], off10 (BO)(Pre-increment Addressing Mode)\n# LD.W D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n# LD.W D[a], P[b] (BO)(Index Addressing Mode)\n:ld.w Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x4 ) & BO\n{\n\tbuild BO;\n\tRd0811 = *[ram]:4 BO;\n}\n\n#:ld.w Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x14 ) & BO\n:ld.w Rd0811,[Rpe1215/Rpo1215^\"+c\"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x14\n{\n\tlocal EA0:4;\n\tlocal EA2:4;\n\tCircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA2, off10, 2);\n\tRd0811[16,16] = *[ram]:2 EA2;\n\tRd0811[0,16] = *[ram]:2 EA0;\n}\n\n# LDLCX off18 (ABS)(Absolute Addressing Mode)\n:ldlcx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x2 ) & off18\n{\n\t#TODO context\n\tload_lower_context(off18);\n}\n\n# LDLCX A[b], off10 (BO) (Base + Short Index Addressing Mode)\n:ldlcx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; off10 & op2227=0x24 ) & BO\n{\n\t#TODO context\n\tbuild BO;\n\tload_lower_context(BO);\n}\n\n# LDMST A[b], off10, E[a] (BO)(Post-increment Addressing Mode)\n# LDMST P[b], E[a] (BO)(Bit-reverse Addressing Mode)\n# LDMST A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)\n# LDMST A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)\n# LDMST P[b], E[a] (BO)(Index Addressing Mode)\n:ldmst BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0607=0x1 ; op2225=0x1 ) & BO\n{\n\tbuild BO;\n\tlocal tmp:4 = *[ram]:4 BO;\n\t*[ram]:4 BO = (tmp & ~Reo0811) | (Ree0811 & Reo0811);\n}\n\n# LDMST off18, E[a] (ABS)(Absolute Addressing Mode)\n:ldmst off18,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0xe5 ; op2627=0x1 ) & off18\n{\n\tlocal tmp:4 = *[ram]:4 off18;\n\t*[ram]:4 off18 = (tmp & ~Reo0811) | (Ree0811 & Reo0811);\n}\n\n# LDMST P[b], off10, E[a] (BO)(Circular Addressing Mode)\n#:ldmst BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0x69 ; op2227=0x11 ) & BO\n:ldmst [Rpe1215/Rpo1215^\"+c\"^]off10,Ree0811/Reo0811 is PCPMode=0 & Ree0811 & Reo0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x11\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\t*[ram]:4 EA = (*[ram]:4 EA & ~Reo0811) | (Ree0811 & Reo0811);\n}\n\n# LDUCX A[b], off10 (BO)(Base + Short Index Addressing Mode)\n:lducx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; off10 & op2227=0x25 ) & BO\n{\n\t#TODO context\n\tbuild BO;\n\tload_upper_context(BO);\n}\n\n# LDUCX off18 (ABS)(Absolute Addressing Mode)\n:lducx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x3 ) & off18\n{\n\t#TODO context\n\tload_upper_context(off18);\n}\n\n# LEA A[a], off18 (ABS)(Absolute Addressing Mode)\n:lea Ra0811,off18 is PCPMode=0 & ( Ra0811 & op0007=0xc5 ; op2627=0x0 ) & off18\n{\n\tRa0811 = off18;\n}\n\n# LEA A[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)\n:lea Ra0811,BOL is PCPMode=0 & ( Ra0811 & op0007=0xd9 ) ... & BOL\n{\n\tbuild BOL;\n\tRa0811 = BOL;\n}\n\n# LEA A[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)\n:lea Ra0811,BO is PCPMode=0 & ( Ra0811 & op0007=0x49 ; op2227=0x28 ) & BO\n{\n\tbuild BO;\n\tRa0811 = BO;\n}\n\n# LOOP A[b], disp4 (SBR)\n:loop Ra1215,off0811pc4o is PCPMode=0 & Ra1215 & off0811pc4o & op0007=0xfc\n{\n\tlocal tmp:4 = Ra1215;\n\tRa1215 = Ra1215 - 1;\n\tif (tmp != 0) goto off0811pc4o;\n}\n\n# LOOP A[b], disp15 (BRR)\n:loop Ra1215,off1630pc15s is PCPMode=0 & Ra1215 & op0007=0xfd & op0811=0x0 ; off1630pc15s & op3131=0x0\n{\n\tlocal tmp:4 = Ra1215;\n\tRa1215 = Ra1215 - 1;\n\tif (tmp != 0) goto off1630pc15s;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# LOOPU disp15 (BRR)\n:loopu off1630pc15s is PCPMode=0 & op0007=0xfd & op0815=0x0 ; off1630pc15s & op3131=0x1\n{\n\tgoto off1630pc15s;\n}\n@endif\n\n# LT D[15], D[a], D[b] (SRR)\n:lt d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x7a\n{\n\td15 = zext(Rd0811 s< Rd1215);\n}\n\n# LT D[15], D[a], const4 (SRC)\n:lt d15,Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xfa\n{\n\td15 = zext(Rd0811 s< const1215S);\n}\n\n# LT D[c], D[a], D[b] (RR)\n:lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x120\n{\n\tRd2831 = zext(Rd0811 s< Rd1215);\n}\n\n# LT D[c], D[a], const9 (RC)\n:lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x12 ) & const1220S\n{\n\tRd2831 = zext(Rd0811 s< const1220S);\n}\n\n# LT.A D[c], A[a], A[b] (RR)\n:lt.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x420\n{\n\tRd2831 = zext(Ra0811 s< Ra1215);\n}\n\n# LT.B D[c], D[a], D[b] (RR)\n:lt.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x520\n{\n\tlocal result3:4 = 0xff * zext(Rd0811[24,8] s< Rd1215[24,8]);\n\tlocal result2:4 = 0xff * zext(Rd0811[16,8] s< Rd1215[16,8]);\n\tlocal result1:4 = 0xff * zext(Rd0811[8,8] s< Rd1215[8,8]);\n\tlocal result0:4 = 0xff * zext(Rd0811[0,8] s< Rd1215[0,8]);\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# LT.BU D[c], D[a], D[b] (RR)\n:lt.bu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x530\n{\n\tlocal result3:4 = 0xff * zext(Rd0811[24,8] < Rd1215[24,8]);\n\tlocal result2:4 = 0xff * zext(Rd0811[16,8] < Rd1215[16,8]);\n\tlocal result1:4 = 0xff * zext(Rd0811[8,8] < Rd1215[8,8]);\n\tlocal result0:4 = 0xff * zext(Rd0811[0,8] < Rd1215[0,8]);\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# LT.H D[c], D[a], D[b] (RR)\n:lt.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x720\n{\n\tresult1:4 = 0xffff * zext(Rd0811[16,16] s< Rd1215[16,16]);\n\tresult0:4 = 0xffff * zext(Rd0811[0,16] s< Rd1215[0,16]);\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# LT.HU D[c], D[a], D[b] (RR)\n:lt.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x730\n{\n\tlocal result1:4 = 0xffff * zext(Rd0811[16,16] < Rd1215[16,16]);\n\tlocal result0:4 = 0xffff * zext(Rd0811[0,16] < Rd1215[0,16]);\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# LT.U D[c], D[a], D[b] (RR)\n:lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x130\n{\n\tRd2831 = zext(Rd0811 < Rd1215);\n}\n\n# LT.U D[c], D[a], const9 (RC)\n:lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x13 ) & const1220Z\n{\n\tRd2831 = zext(Rd0811 < const1220Z);\n}\n\n# LT.W D[c], D[a], D[b] (RR)\n:lt.w Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x920\n{\n\tRd2831 = 0xFFFFFFFF * zext(Rd0811 s< Rd1215);\n}\n\n# LT.WU D[c], D[a], D[b] (RR)\n:lt.wu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x930\n{\n\tRd2831 = 0xFFFFFFFF * zext(Rd0811 < Rd1215);\n}\n\n# MADD D[c], D[d], D[a], D[b] (RRR2)\n:madd Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Rd2427 & Rd2831 & op1623=0xa\n{\n\tRd2831 = Rd2427 + (Rd0811 * Rd1215);\n\toverflowflags(Rd2831);\n}\n\n# MADD D[c], D[d], D[a], const9 (RCR)\n:madd Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Rd2427 & Rd2831 & op2123=0x1 ) & const1220S\n{\n\tRd2831 = Rd2427 + (Rd0811 * const1220S);\n\toverflowflags(Rd2831);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD E[c], E[d], D[a], const9 (RCR)\n:madd Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x3 ) & const1220S\n{\n\tRe2831 = Re2427 + sext(Rd0811 * const1220S);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD E[c], E[d], D[a], D[b] (RRR2)\n:madd Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0x6a\n{\n\tRe2831 = Re2427 + sext(Rd0811 * Rd1215);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.F D[c], D[d], D[a], D[b] (RRR)\n:madd.f Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x6b ; Rd2427 & Rd2831 & op1623=0x61\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = Rd2427 f+ (Rd0811 f* Rd1215);\n}\n@endif\n\nmacro packed_multiply_ul(mres1, mres0, rega, regb, n) {\n\tlocal sc1 = (rega[16,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1);\n\tlocal sc0 = (rega[0,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1);\n\tternary(mres1, sc1, 0x7FFFFFFF, sext((rega[16,16] * regb[16,16]) << n));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[0,16]) << n));\n}\n\nmacro packed_multiply_lu(mres1, mres0, rega, regb, n) {\n\tlocal sc1 = (rega[16,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1);\n\tlocal sc0 = (rega[0,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1);\n\tternary(mres1, sc1, 0x7FFFFFFF, sext((rega[16,16] * regb[0,16]) << n));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[16,16]) << n));\n}\n\nmacro packed_multiply_ll(mres1, mres0, rega, regb, n) {\n\tlocal sc1 = (rega[16,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1);\n\tlocal sc0 = (rega[0,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1);\n\tternary(mres1, sc1, 0x7FFFFFFF, sext((rega[16,16] * regb[0,16]) << n));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[0,16]) << n));\n}\n\nmacro packed_multiply_uu(mres1, mres0, rega, regb, n) {\n\tlocal sc1 = (rega[0,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1);\n\tlocal sc0 = (rega[16,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1);\n\tternary(mres1, sc1, 0x7FFFFFFF, sext((rega[0,16] * regb[16,16]) << n));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext((rega[16,16] * regb[16,16]) << n));\n}\n\n\nmacro multiply_l_l(mres0, rega, regb, n) {\n\tlocal sc0 = (rega[0,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1);\n\tternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[0,16]) << n));\n}\n\nmacro multiply_u_u(mres0, rega, regb, n) {\n\tlocal sc0 = (rega[16,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1);\n\tternary(mres0, sc0, 0x7FFFFFFF, sext((rega[16,16] * regb[16,16]) << n));\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:madd.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x4\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tRd2831 = Rd2427 + mres;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q D[c], D[d], D[a], D[b] U, n (RRR1)\n:madd.q Rd2831,Rd2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x0\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[16,16]));\n\ttmp = (tmp << const1617Z) s>> 16;\n\tRd2831 = Rd2427 + tmp[0,32];\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q D[c], D[d], D[a], D[b] L, n (RRR1)\n:madd.q Rd2831,Rd2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x1\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[0,16]));\n\ttmp = (tmp << const1617Z) s>> 16;\n\tRd2831 = Rd2427 + tmp[0,32];\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q D[c], D[d], D[a], D[b], n (RRR1)\n:madd.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2\n{\n\tlocal tmp:8 = sext(Rd0811 * Rd1215);\n\ttmp = (tmp << const1617Z) s>> 32;\n\tRd2831 = Rd2427 + tmp[0,32];\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:madd.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x5\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tRd2831 = Rd2427 + mres;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q E[c], E[d], D[a], D[b] U, n (RRR1)\n:madd.q Re2831,Re2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x18\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[16,16]));\n\tRe2831 = Re2427 + (tmp << const1617Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q E[c], E[d], D[a], D[b] L, n (RRR1)\n:madd.q Re2831,Re2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x19\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[0,16]));\n\tRe2831 = Re2427 + (tmp << const1617Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q E[c], E[d], D[a], D[b], n (RRR1)\n:madd.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x1b\n{\n\tlocal tmp:8 = sext(Rd0811 * Rd1215);\n\tRe2831 = Re2427 + (tmp << const1617Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q E[c], E[d], D[a] U, D[b] U, n (RRR1)\n:madd.q Re2831,Re2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x1c\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext(mres << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.Q E[c], E[d], D[a] L, D[b] L, n (RRR1)\n:madd.q Re2831,Re2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x1d\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + (sext(mres) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.U E[c], E[d], D[a], const9 (RCR)\n:madd.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x2 ) & const1220Z\n{\n\tRe2831 = Re2427 + zext(Rd0811 * const1220Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADD.U E[c], E[d], D[a], D[b] (RRR2)\n:madd.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0x68\n{\n\tRe2831 = Re2427 + zext(Rd0811 * Rd1215);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDM.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddm.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 + mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDM.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:maddm.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 + mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDM.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:maddm.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 + mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDM.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:maddm.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 + mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDMS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddms.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 + mres0) << 16);\n\tssov(Re2831, result, 64);\n\toverflowflagsd(result);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDMS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:maddms.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 + mres0) << 16);\n\tssov(Re2831, result, 64);\n\toverflowflagsd(result);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDMS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:maddms.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 + mres0) << 16);\n\tssov(Re2831, result, 64);\n\toverflowflagsd(result);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDMS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:maddms.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 + mres0) << 16);\n\tssov(Re2831, result, 64);\n\toverflowflagsd(result);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.H D[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddr.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 + mres1 + 0x8000;\n\tlocal res0:4 = Ree2427 + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:maddr.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x6\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 + mres + 0x8000;\n\tRd2831 = zext(res[16,16]) << 16;\n\toverflowflags(res);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDR.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:maddr.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x7\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 + mres + 0x8000;\n\tRd2831 = zext(res[16,16]) << 16;\n\toverflowflags(res);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.H D[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddrs.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x3e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 + mres1 + 0x8000;\n\tlocal res0:4 = Ree2427 + mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = mres1 + 0x8000;\n\tlocal res0:4 = mres0 + 0x8000;\n\tres1[16,16] = res1[16,16] + Rd2427[16,16];\n\tres0[16,16] = res0[16,16] + Rd2427[0,16];\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = mres1 + 0x8000;\n\tlocal res0:4 = mres0 + 0x8000;\n\tres1[16,16] = res1[16,16] + Rd2427[16,16];\n\tres0[16,16] = res0[16,16] + Rd2427[0,16];\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = mres1 + 0x8000;\n\tlocal res0:4 = mres0 + 0x8000;\n\tres1[16,16] = res1[16,16] + Rd2427[16,16];\n\tres0[16,16] = res0[16,16] + Rd2427[0,16];\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = mres1 + 0x8000;\n\tlocal res0:4 = mres0 + 0x8000;\n\tres1[16,16] = res1[16,16] + Rd2427[16,16];\n\tres0[16,16] = res0[16,16] + Rd2427[0,16];\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:maddrs.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x26\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 + mres + 0x8000;\n\toverflowflags(res);\n\tssov(res, res, 32);\n\tRd2831 = zext(res[16,16]) << 16;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDRS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:maddrs.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x27\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 + mres + 0x8000;\n\toverflowflags(res);\n\tssov(res, res, 32);\n\tRd2831 = zext(res[16,16]) << 16;\n}\n@endif\n\n# MADDS D[c], D[d], D[a], D[b] (RRR2)\n:madds Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Rd2427 & Rd2831 & op1623=0x8a\n{\n\tlocal result:4 = Rd2427 + (Rd0811 * Rd1215);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# MADDS D[c], D[d], D[a], const9 (RCR)\n:madds Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Rd2427 & Rd2831 & op2123=0x5 ) & const1220S\n{\n\tlocal result:4 = Rd2427 + (Rd0811 * const1220S);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS E[c], E[d], D[a], const9 (RCR)\n:madds Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x7 ) & const1220S\n{\n\tlocal result:8 = Re2427 + sext(Rd0811 * const1220S);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS E[c], E[d], D[a], D[b] (RRR2)\n:madds Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0xea\n{\n\tlocal result:8 = Re2427 + sext(Rd0811 * Rd1215);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 + mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:madds.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x24\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal result:4 = Rd2427 + mres;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q D[c], D[d], D[a], D[b] U, n (RRR1)\n:madds.q Rd2831,Rd2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x20\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[16,16]));\n\ttmp = (tmp << const1617Z) s>> 16;\n\tlocal result:4 = Rd2427 + tmp[0,32];\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q D[c], D[d], D[a], D[b] L, n (RRR1)\n:madds.q Rd2831,Rd2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x21\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[0,16]));\n\ttmp = (tmp << const1617Z) s>> 16;\n\tlocal result:4 = Rd2427 + tmp[0,32];\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q D[c], D[d], D[a], D[b], n (RRR1)\n:madds.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x22\n{\n\tlocal tmp:8 = sext(Rd0811 * Rd1215);\n\ttmp = (tmp << const1617Z) s>> 32;\n\tlocal result:4 = Rd2427 + tmp[0,32];\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:madds.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x25\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal result:4 = Rd2427 + mres;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.QE[c], E[d], D[a], D[b] U, n (RRR1)\n:madds.q Re2831,Re2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x38\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[16,16]));\n\tlocal result:8 = Re2427 + (tmp << const1617Z);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q E[c], E[d], D[a], D[b] L, n (RRR1)\n:madds.q Re2831,Re2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x39\n{\n\tlocal tmp:8 = sext(Rd0811 * sext(Rd1215[0,16]));\n\tlocal result:8 = Re2427 + (tmp << const1617Z);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q E[c], E[d], D[a], D[b], n (RRR1)\n:madds.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x3b\n{\n\tlocal tmp:8 = sext(Rd0811 * Rd1215);\n\ttmp = tmp << const1617Z;\n\tlocal result:8 = Re2427 + tmp;\n\toverflowflags(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q E[c], E[d], D[a] U, D[b] U, n (RRR1)\n:madds.q Re2831,Re2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x3c\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext(mres << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.Q E[c], E[d], D[a] L, D[b] L, n (RRR1)\n:madds.q Re2831,Re2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x3d\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext(mres << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n# MADDS.U D[c], D[d], D[a], const9 (RCR)\n:madds.u Rd2831,Rd2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Rd2427 & Rd2831 & op2123=0x4 ) & const1220Z\n{\n\tlocal result:4 = Rd2427 + (Rd0811 * const1220Z);\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n# MADDS.U D[c], D[d], D[a], D[b] (RRR2)\n:madds.u Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Rd2427 & Rd2831 & op1623=0x88\n{\n\tlocal result:4 = Rd2427 + (Rd0811 * Rd1215);\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.U E[c], E[d], D[a], const9 (RCR)\n:madds.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x6 ) & const1220Z\n{\n\tlocal result:8 = Re2427 + zext(Rd0811 * const1220Z);\n\toverflowflagsd(result);\n\tsuov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDS.U E[c], E[d], D[a], D[b] (RRR2)\n:madds.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0xe8\n{\n\tlocal result:8 = Re2427 + zext(Rd0811 * Rd1215);\n\toverflowflags(result);\n\tsuov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSU.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSU.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSU.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSU.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUM.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddsum.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUM.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:maddsum.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUM.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:maddsum.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUM.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:maddsum.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUMS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddsums.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUMS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:maddsums.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUMS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:maddsums.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUMS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:maddsums.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 + sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUR.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUR.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUR.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUR.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSURS.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSURS.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSURS.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSURS.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tssov(Reo2831, Reo2427 + mres1, 32);\n\tssov(Ree2831, Ree2427 - mres0, 32);\n\toverflowflagsww(Reo2427 + mres1, Ree2427 - mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MADDSUS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 + mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tssov(Reo2831, result1, 32);\n\tssov(Ree2831, result0, 32);\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n# MAX D[c], D[a], D[b] (RR)\n:max Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x1a0\n{\n\tternary(Rd2831, Rd0811 s> Rd1215, Rd0811, Rd1215);\n}\n\n# MAX D[c], D[a], const9 (RC)\n:max Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x1a ) & const1220S\n{\n\tternary(Rd2831, Rd0811 s> const1220S, Rd0811, const1220S);\n}\n\n# MAX.B D[c], D[a], D[b] (RR)\n:max.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x5a0\n{\n\tlocal result3:4;\n\tlocal result2:4;\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result3, (Rd0811[24,8] s> Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8]));\n\tternary(result2, (Rd0811[16,8] s> Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8]));\n\tternary(result1, (Rd0811[8,8] s> Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8]));\n\tternary(result0, (Rd0811[0,8] s> Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8]));\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# MAX.BU D[c], D[a], D[b] (RR)\n:max.bu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x5b0\n{\n\tlocal result3:4;\n\tlocal result2:4;\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result3, (Rd0811[24,8] > Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8]));\n\tternary(result2, (Rd0811[16,8] > Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8]));\n\tternary(result1, (Rd0811[8,8] > Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8]));\n\tternary(result0, (Rd0811[0,8] > Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8]));\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# MAX.H D[c], D[a], D[b] (RR)\n:max.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x7a0\n{\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result1, (Rd0811[16,16] s> Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16]));\n\tternary(result0, (Rd0811[0,16] s> Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16]));\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# MAX.HU D[c], D[a], D[b] (RR)\n:max.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x7b0\n{\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result1, (Rd0811[16,16] > Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16]));\n\tternary(result0, (Rd0811[0,16] > Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16]));\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# MAX.U D[c], D[a], D[b] (RR)\n:max.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x1b0\n{\n\tternary(Rd2831, Rd0811 > Rd1215, Rd0811, Rd1215);\n}\n\n# MAX.U D[c], D[a], const9 (RC)\n:max.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x1b ) & const1220Z\n{\n\tternary(Rd2831, Rd0811 > const1220Z, Rd0811, const1220Z);\n}\n\n# MFCR D[c], const16 (RLC)\n:mfcr Rd2831,const1227Z is PCPMode=0 & ( op0007=0x4d & op0811=0x0 ; Rd2831 ) & const1227Z\n{\n\tRd2831 = *[register]:4 const1227Z;\n}\n\n@if defined(TRICORE_V2)\n:mffr Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x1d1\n{\n\tRd2831 = *[register]:4 Rd0811;\n}\n@endif\n\n# MIN D[c], D[a], D[b] (RR)\n:min Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x180\n{\n\tternary(Rd2831, Rd0811 s< Rd1215, Rd0811, Rd1215);\n}\n\n# MIN D[c], D[a], const9 (RC)\n:min Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x18 ) & const1220S\n{\n\tternary(Rd2831, Rd0811 s< const1220S, Rd0811, const1220S);\n}\n\n# MIN.B D[c], D[a], D[b] (RR)\n:min.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x580\n{\n\tlocal result3:4;\n\tlocal result2:4;\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result3, (Rd0811[24,8] s< Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8]));\n\tternary(result2, (Rd0811[16,8] s< Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8]));\n\tternary(result1, (Rd0811[8,8] s< Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8]));\n\tternary(result0, (Rd0811[0,8] s< Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8]));\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# MIN.BU D[c], D[a], D[b] (RR)\n:min.bu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x590\n{\n\tlocal result3:4;\n\tlocal result2:4;\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result3, (Rd0811[24,8] < Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8]));\n\tternary(result2, (Rd0811[16,8] < Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8]));\n\tternary(result1, (Rd0811[8,8] < Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8]));\n\tternary(result0, (Rd0811[0,8] < Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8]));\n\tRd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0);\n}\n\n# MIN.H D[c], D[a], D[b] (RR)\n:min.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x780\n{\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result1, (Rd0811[16,16] s< Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16]));\n\tternary(result0, (Rd0811[0,16] s< Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16]));\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# MIN.HU D[c], D[a], D[b] (RR)\n:min.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x790\n{\n\tlocal result1:4;\n\tlocal result0:4;\n\tternary(result1, (Rd0811[16,16] < Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16]));\n\tternary(result0, (Rd0811[0,16] < Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16]));\n\tRd2831 = (result1 << 16) | (result0);\n}\n\n# MIN.U D[c], D[a], D[b] (RR)\n:min.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x190\n{\n\tternary(Rd2831, Rd0811 < Rd1215, Rd0811, Rd1215);\n}\n\n# MIN.U D[c], D[a], const9 (RC)\n:min.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x19 ) & const1220Z\n{\n\tternary(Rd2831, Rd0811 < const1220Z, Rd0811, const1220Z);\n}\n\n# MOV D[a], D[b] (SRR)\n:mov Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2\n{\n\tRd0811 = Rd1215;\n}\n\n# MOV D[a], const4 (SRC)\n:mov Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x82\n{\n\tRd0811 = const1215S;\n}\n\n@if defined(TRICORE_V2)\n# MOV E[a], const4 (SRC)\n:mov Re0811,const1215S is PCPMode=0 & Re0811 & const1215S & op0007=0xd2\n{\n\tRe0811 = sext(const1215S);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MOV D[15], const8 (SC)\n:mov d15,const0815Z is PCPMode=0 & const0815Z & d15 & op0007=0xda\n{\n\td15 = const0815Z;\n}\n@endif\n\n# MOV D[c], const16 (RLC)\n:mov Rd2831,const1227S is PCPMode=0 & ( op0007=0x3b & op0811=0x0 ; Rd2831 ) & const1227S\n{\n\tRd2831 = const1227S;\n}\n\n# MOV D[c], D[b] (RR)\n:mov Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x1f0\n{\n\tRd2831 = Rd1215;\n}\n\n@if defined(TRICORE_V2)\n# MOV E[c], const16 (RLC)\n:mov Re2831,const1227S is PCPMode=0 & ( op0007=0xfb & op0811=0x0 ; Re2831 ) & const1227S\n{\n\tRe2831 = sext(const1227S);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# MOV E[c], D[b] (RR)\n:mov Re2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Re2831 & op1627=0x800\n{\n\tRe2831 = sext(Rd1215);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# MOV E[c], D[a], D[b] (RR)\n:mov Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Ree2831 & Reo2831 & op1627=0x810\n{\n\tlocal tmp1 = Rd0811;\n\tlocal tmp0 = Rd1215;\n\tReo2831 = tmp1;\n\tRee2831 = tmp0;\n}\n@endif\n\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MOV.A A[a], const4 (SRC)\n:mov.a Ra0811,const1215Z is PCPMode=0 & Ra0811 & const1215Z & op0007=0xa0\n{\n\tRa0811 = const1215Z;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MOV.A A[a], D[b] (SRR)\n:mov.a Ra0811,Rd1215 is PCPMode=0 & Ra0811 & Rd1215 & op0007=0x60\n{\n\tRa0811 = Rd1215;\n}\n@endif\n\n# MOV.A A[c], D[b] (RR)\n:mov.a Ra2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x1 & op0811=0x0 ; Ra2831 & op1627=0x630\n{\n\tRa2831 = Rd1215;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MOV.AA A[a], A[b] (SRR)\n:mov.aa Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x40\n{\n\tRa0811 = Ra1215;\n}\n@endif\n\n# MOV.AA A[c], A[b] (RR)\n:mov.aa Ra2831,Ra1215 is PCPMode=0 & Ra1215 & op0007=0x1 & op0811=0x0 ; Ra2831 & op1627=0x0\n{\n\tRa2831 = Ra1215;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MOV.D D[a], A[b] (SRR)\n:mov.d Rd0811,Ra1215 is PCPMode=0 & Ra1215 & Rd0811 & op0007=0x80\n{\n\tRd0811 = Ra1215;\n}\n@endif\n\n# MOV.D D[c], A[b] (RR)\n:mov.d Rd2831,Ra1215 is PCPMode=0 & Ra1215 & op0007=0x1 & op0811=0x0 ; Rd2831 & op1627=0x4c0\n{\n\tRd2831 = Ra1215;\n}\n\n# MOV.U D[c], const16 (RLC)\n:mov.u Rd2831,const1227Z is PCPMode=0 & ( op0007=0xbb & op0811=0x0 ; Rd2831 ) & const1227Z\n{\n\tRd2831 = const1227Z;\n}\n\n# MOVH D[c], const16 (RLC)\n:movh Rd2831,const1227Z is PCPMode=0 & ( op0007=0x7b & op0811=0x0 ; Rd2831 ) & const1227Z\n{\n\tRd2831 = const1227Z << 16;\n}\n\n# MOVH.A A[c], const16 (RLC)\n:movh.a Ra2831,const1227Z is PCPMode=0 & ( op0007=0x91 & op0811=0x0 ; Ra2831 ) & const1227Z\n{\n\tRa2831 = const1227Z << 16;\n}\n\n#MSUB D[c], D[d], D[a], D[b] (RRR2)\n:msub Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Rd2427 & Rd2831 & op1623=0xa\n{\n\tRd2831 = Rd2427 - (Rd0811 * Rd1215);\n\toverflowflags(Rd2831);\n}\n\n# MSUB D[c], D[d], D[a], const9 (RCR)\n:msub Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Rd2427 & Rd2831 & op2123=0x1 ) & const1220S\n{\n\tRd2831 = Rd2427 - (Rd0811 * const1220S);\n\toverflowflags(Rd2831);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB E[c], E[d], D[a], const9 (RCR)\n:msub Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x3 ) & const1220S\n{\n\tRe2831 = Re2427 - sext(Rd0811 * const1220S);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB E[c], E[d], D[a], D[b] (RRR2)\n:msub Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0x6a\n{\n\tRe2831 = Re2427 - sext(Rd0811 * Rd1215);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.F D[c], D[d], D[a], D[b] (RRR)\n:msub.f Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x6b ; Rd2427 & Rd2831 & op1623=0x71\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = Rd2427 f- (Rd0811 f* Rd1215);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 - mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 - mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 - mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result1:4 = Reo2427 - mres1;\n\tlocal result0:4 = Ree2427 - mres0;\n\tReo2831 = result1;\n\tRee2831 = result0;\n\toverflowflagsww(result1, result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:msub.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x4\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tRd2831 = Rd2427 - mres;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q D[c], D[d], D[a], D[b] U, n (RRR1)\n:msub.q Rd2831,Rd2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x0\n{\n\tRd2831 = Rd2427 - (((Rd0811 * sext(Rd1215[16,16])) << const1617Z) s>> 16);\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q D[c], D[d], D[a], D[b] L, n (RRR1)\n:msub.q Rd2831,Rd2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x1\n{\n\tRd2831 = Rd2427 - (((Rd0811 * sext(Rd1215[0,16])) << const1617Z) s>> 16);\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q D[c], D[d], D[a], D[b], n (RRR1)\n:msub.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2\n{\n\tRd2831 = Rd2427 - (((Rd0811 * Rd1215) << const1617Z) s>> 32);\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:msub.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x5\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tRd2831 = Rd2427 - mres;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q E[c], E[d], D[a], D[b] U, n (RRR1)\n:msub.q Re2831,Re2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x18\n{\n\tRe2831 = Re2427 - sext((Rd0811 * sext(Rd1215[16,16])) << const1617Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q E[c], E[d], D[a], D[b] L, n (RRR1)\n:msub.q Re2831,Re2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x19\n{\n\tRe2831 = Re2427 - sext((Rd0811 * sext(Rd1215[0,16])) << const1617Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q E[c], E[d], D[a], D[b], n (RRR1)\n:msub.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x1b\n{\n\tRe2831 = Re2427 - sext((Rd0811 * Rd1215) << const1617Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.Q E[c], E[d], D[a] U, D[b] U, n (RRR1)\n:msub.q Re2831,Re2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x1c\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 - sext(mres << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SUB.Q E[c], E[d], D[a] L, D[b] L, n (RRR1)\n:msub.q Re2831,Re2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x1d\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 - sext(mres << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.U E[c], E[d], D[a], const9 (RCR)\n:msub.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x2 ) & const1220Z\n{\n\tRe2831 = Re2427 - zext(Rd0811 * const1220Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUB.U E[c], E[d], D[a], D[b] (RRR2)\n:msub.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0x68\n{\n\tRe2831 = Re2427 - zext(Rd0811 * Rd1215);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBAD.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\tReo2831 = res1;\n\tRee2831 = res0;\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBAD.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\tReo2831 = res1;\n\tRee2831 = res0;\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBAD.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\tReo2831 = res1;\n\tRee2831 = res0;\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBAD.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\tReo2831 = res1;\n\tRee2831 = res0;\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADM.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubadm.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADM.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubadm.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADM.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubadm.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADM.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubadm.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADMS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubadms.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADMS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubadms.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADMS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubadms.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADMS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubadms.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal result:8 = Re2427 - sext((mres1 - mres0) << 16);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADR.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADR.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADR.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n\toverflowflagsww(res1, res0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADRS.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADRS.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADRS.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADRS.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000;\n\toverflowflagsww(res1, res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBADS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 + mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBM.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubm.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tRe2831 = res;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBM.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubm.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tRe2831 = res;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBM.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubm.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tRe2831 = res;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBM.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubm.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tRe2831 = res;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBMS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubms.h Re2831,Re2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tssov(Re2427, res, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBMS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubms.h Re2831,Re2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tssov(Re2427, res, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBMS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubms.h Re2831,Re2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tssov(Re2427, res, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBMS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubms.h Re2831,Re2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - (sext(mres1 + mres0) << 16);\n\toverflowflagsd(res);\n\tssov(Re2427, res, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.H D[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubr.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1 + 0x8000;\n\tlocal res0:4 = Ree2427 - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:msubr.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x6\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 - mres + 0x8000;\n\toverflowflags(res);\n\tRd2831 = zext(res[16,16]) << 16;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBR.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:msubr.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x7\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 - mres + 0x8000;\n\toverflowflags(res);\n\tRd2831 = zext(res[16,16]) << 16;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.H D[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubrs.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x3e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1 + 0x8000;\n\tlocal res0:4 = Ree2427 - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.H D[c], D[d], D[a], D[b] UL, n (RRR1)\n:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.H D[c], D[d], D[a], D[b] LU, n (RRR1)\n:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.H D[c], D[d], D[a], D[b] LL, n (RRR1)\n:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.H D[c], D[d], D[a], D[b] UU, n (RRR1)\n:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000;\n\tlocal res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000;\n\toverflowflagsww(res1,res0);\n\tssov(res1, res1, 32);\n\tssov(res0, res0, 32);\n\tRd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:msubrs.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x26\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 - mres + 0x8000;\n\toverflowflags(res);\n\tssov(res, res, 32);\n\tRd2831 = zext(res[16,16]) << 16;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBRS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:msubrs.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x27\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 - mres + 0x8000;\n\toverflowflags(res);\n\tssov(res, res, 32);\n\tRd2831 = zext(res[16,16]) << 16;\n}\n@endif\n\n# MSUBS D[c], D[d], D[a], D[b] (RRR2)\n:msubs Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Rd2427 & Rd2831 & op1623=0x8a\n{\n\tRd2831 = Rd2427 - (Rd0811 - Rd1215);\n\toverflowflags(Rd2831);\n\tssov(Rd2831, Rd2831, 32);\n}\n\n# MSUBS D[c], D[d], D[a], const9 (RCR)\n:msubs Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Rd2427 & Rd2831 & op2123=0x5 ) & const1220S\n{\n\tlocal result:4 = Rd2427 - (Rd0811 - const1220S);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS E[c], E[d], D[a], const9 (RCR)\n:msubs Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x7 ) & const1220S\n{\n\tlocal result:8 = Re2427 - sext(Rd0811 - const1220S);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS E[c], E[d], D[a], D[b] (RRR2)\n:msubs Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0xea\n{\n\tlocal result:8 = Re2427 - sext(Rd0811 - Rd1215);\n\toverflowflags(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.H E[c], E[d], D[a], D[b] UL, n (RRR1)\n:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 - mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.H E[c], E[d], D[a], D[b] LU, n (RRR1)\n:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 - mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.H E[c], E[d], D[a], D[b] LL, n (RRR1)\n:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 - mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.H E[c], E[d], D[a], D[b] UU, n (RRR1)\n:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tlocal res1:4 = Reo2427 - mres1;\n\tlocal res0:4 = Ree2427 - mres0;\n\toverflowflagsww(res1, res0);\n\tssov(Reo2831, res1, 32);\n\tssov(Ree2831, res0, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1)\n:msubs.q Rd2831,Rd2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x24\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 - mres;\n\toverflowflags(res);\n\tssov(Rd2831, res, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q D[c], D[d], D[a], D[b] U, n (RRR1)\n:msubs.q Rd2831,Rd2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x20\n{\n\tlocal result:4 = Rd2427 - (((Rd0811 * sext(Rd1215[16,16])) << const1617Z) s>> 16);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q D[c], D[d], D[a], D[b] L, n (RRR1)\n:msubs.q Rd2831,Rd2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x21\n{\n\tlocal result:4 = Rd2427 - (((Rd0811 * sext(Rd1215[0,16])) << const1617Z) s>> 16);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q D[c], D[d], D[a], D[b], n (RRR1)\n:msubs.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x22\n{\n\tlocal result:4 = Rd2427 - (((Rd0811 * Rd1215) << const1617Z) s>> 32);\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1)\n:msubs.q Rd2831,Rd2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x25\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:4 = Rd2427 - mres;\n\toverflowflags(res);\n\tssov(Rd2831, res, 32);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q E[c], E[d], D[a], D[b] U, n (RRR1)\n:msubs.q Re2831,Re2427,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x38\n{\n\tlocal result:8 = Re2427 - sext((Rd0811 * sext(Rd1215[16,16])) << const1617Z);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q E[c], E[d], D[a], D[b] L, n (RRR1)\n:msubs.q Re2831,Re2427,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x39\n{\n\tlocal result:8 = Re2427 - sext((Rd0811 * sext(Rd1215[0,16])) << const1617Z);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q E[c], E[d], D[a], D[b], n (RRR1)\n:msubs.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x3b\n{\n\tlocal result:8 = Re2427 - sext((Rd0811 * Rd1215) << const1617Z);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q E[c], E[d], D[a] U, D[b] U, n (RRR1)\n:msubs.q Re2831,Re2427,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x3c\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - sext(mres << 16);\n\toverflowflagsd(res);\n\tssov(Re2831, res, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.Q E[c], E[d], D[a] L, D[b] L, n (RRR1)\n:msubs.q Re2831,Re2427,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x3d\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\tlocal res:8 = Re2427 - sext(mres << 16);\n\toverflowflagsd(res);\n\tssov(Re2831, res, 64);\n}\n@endif\n\n# MSUBS.U D[c], D[d], D[a], const9 (RCR)\n:msubs.u Rd2831,Rd2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Rd2427 & Rd2831 & op2123=0x4 ) & const1220Z\n{\n\tlocal result:4 = Rd2427 - (Rd0811 - const1220Z);\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n# MSUBS.U D[c], D[d], D[a], D[b] (RRR2)\n:msubs.u Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Rd2427 & Rd2831 & op1623=0x88\n{\n\tlocal result:4 = Rd2427 - (Rd0811 - Rd1215);\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.U E[c], E[d], D[a], const9 (RCR)\n:msubs.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x6 ) & const1220Z\n{\n\tlocal result:8 = Re2427 - zext(Rd0811 - const1220Z);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MSUBS.U E[c], E[d], D[a], D[b] (RRR2)\n:msubs.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0xe8\n{\n\tlocal result:8 = Re2427 - zext(Rd0811 - Rd1215);\n\toverflowflagsd(result);\n\tssov(Re2831, result, 64);\n}\n@endif\n\n# MTCR const16, D[a] (RLC)\n:mtcr const1227Z,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xcd ; op2831=0x0 ) & const1227Z\n{\n\t*[register]:4 const1227Z = Rd0811;\n}\n\n@if defined(TRICORE_V2)\n:mtfr Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; op1631=0x1c1\n{\n\t*[register]:4 Rd1215 = Rd0811;\n}\n@endif\n\n# MUL D[a], D[b] (SRR)\n:mul Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe2\n{\n\tRd0811 = Rd0811 * Rd1215;\n\toverflowflags(Rd0811);\n}\n\n# MUL D[c], D[a], const9 (RC)\n:mul Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Rd2831 & op2127=0x1 ) & const1220S\n{\n\tRd2831 = Rd0811 * const1220S;\n\toverflowflags(Rd2831);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL D[c], D[a], D[b] (RR2)\n:mul Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Rd2831 & op1627=0xa\n{\n\tRd2831 = Rd0811 * Rd1215;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL E[c], D[a], const9 (RC)\n:mul Re2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Re2831 & op2127=0x3 ) & const1220S\n{\n\tRe2831 = sext(Rd0811 * const1220S);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL E[c], D[a], D[b] (RR2)\n:mul Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Re2831 & op1627=0x6a\n{\n\tRe2831 = sext(Rd0811 * Rd1215);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.F D[c], D[a], D[b] (RR)\n:mul.f Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x41\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = Rd0811 f* Rd1215;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.H E[c], D[a], D[b] UL, n (RR1)\n:mul.h Ree2831/Reo2831,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x18\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tReo2831 = mres1;\n\tRee2831 = mres0;\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.H E[c], D[a], D[b] LU, n (RR1)\n:mul.h Ree2831/Reo2831,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x19\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tReo2831 = mres1;\n\tRee2831 = mres0;\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.H E[c], D[a], D[b] LL, n (RR1)\n:mul.h Ree2831/Reo2831,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x1a\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tReo2831 = mres1;\n\tRee2831 = mres0;\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.H E[c], D[a], D[b] UU, n (RR1)\n:mul.h Ree2831/Reo2831,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x1b\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tReo2831 = mres1;\n\tRee2831 = mres0;\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q D[c], D[a], D[b] U, n (RR1)\n:mul.q Rd2831,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x0\n{\n\tRd2831 = ((Rd0811 * sext(Rd1215[16,16])) << const1617Z) s>> 16;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q D[c], D[a], D[b] L, n (RR1)\n:mul.q Rd2831,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x1\n{\n\tRd2831 = ((Rd0811 * sext(Rd1215[0,16])) << const1617Z) s>> 16;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q D[c], D[a], D[b], n (RR1)\n:mul.q Rd2831,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x2\n{\n\tRd2831 = ((Rd0811 * Rd1215) << const1617Z) s>> 32;\n\toverflowflags(Rd2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q D[c], D[a] U, D[b] U, n (RR1)\n:mul.q Rd2831,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x4\n{\n\tlocal mres:4;\n\tmultiply_u_u(mres, Rd0811, Rd1215, const1617Z);\n\toverflowflags(mres);\n\tRd2831 = mres;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q D[c], D[a] L, D[b] L, n (RR1)\n:mul.q Rd2831,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x5\n{\n\tlocal mres:4;\n\tmultiply_l_l(mres, Rd0811, Rd1215, const1617Z);\n\toverflowflags(mres);\n\tRd2831 = mres;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q E[c], D[a], D[b] U, n (RR1)\n:mul.q Re2831,Rd0811,Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Re2831 & const1617Z & op1827=0x18\n{\n\tRe2831 = sext(Rd0811 * sext(Rd1215[16,16])) << const1617Z;\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q E[c], D[a], D[b] L, n (RR1)\n:mul.q Re2831,Rd0811,Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Re2831 & const1617Z & op1827=0x19\n{\n\tRe2831 = sext(Rd0811 * sext(Rd1215[0,16])) << const1617Z;\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.Q E[c], D[a], D[b], n (RR1)\n:mul.q Re2831,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Re2831 & const1617Z & op1827=0x1b\n{\n\tRe2831 = sext(Rd0811 * Rd1215) << const1617Z;\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.U E[c], D[a], const9 (RC)\n:mul.u Re2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Re2831 & op2127=0x2 ) & const1220Z\n{\n\tRe2831 = zext(Rd0811 * const1220Z);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MUL.U E[c], D[a], D[b] (RR2)\n:mul.u Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Re2831 & op1627=0x68\n{\n\tRe2831 = zext(Rd0811 * Rd1215);\n\toverflowflagsd(Re2831);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULM.H E[c], D[a], D[b] UL, n (RR1)\n:mulm.h Re2831,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1c\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = sext(mres1 + mres0) << 16;\n\t$(PSW_V) = 0;\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULM.H E[c], D[a], D[b] LU, n (RR1)\n:mulm.h Re2831,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1d\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = sext(mres1 + mres0) << 16;\n\t$(PSW_V) = 0;\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULM.H E[c], D[a], D[b] LL, n (RR1)\n:mulm.h Re2831,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1e\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = sext(mres1 + mres0) << 16;\n\t$(PSW_V) = 0;\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULM.H E[c], D[a], D[b] UU, n (RR1)\n:mulm.h Re2831,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1f\n{\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tpacked_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z);\n\tRe2831 = sext(mres1 + mres0) << 16;\n\t$(PSW_V) = 0;\n\t$(PSW_AV) = 0;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULR.H D[c], D[a], D[b] UL, n (RR1)\n:mulr.h Rd2831,Rd0811,Rd1215^\"ul\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xc\n{\n\tlocal sc1 = (Rd0811[16,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1);\n\tlocal sc0 = (Rd0811[0,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1);\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[16,16]) << const1617Z) + 0x8000));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[0,16]) << const1617Z) + 0x8000));\n\tRd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]);\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULR.H D[c], D[a], D[b] LU, n (RR1)\n:mulr.h Rd2831,Rd0811,Rd1215^\"lu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xd\n{\n\tlocal sc1 = (Rd0811[16,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1);\n\tlocal sc0 = (Rd0811[0,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1);\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[0,16]) << const1617Z) + 0x8000));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[16,16]) << const1617Z) + 0x8000));\n\tRd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]);\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# # MULR.H D[c], D[a], D[b] LL, n (RR1)\n:mulr.h Rd2831,Rd0811,Rd1215^\"ll\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xe\n{\n\tlocal sc1 = (Rd0811[16,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1);\n\tlocal sc0 = (Rd0811[0,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1);\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[0,16]) << const1617Z) + 0x8000));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[0,16]) << const1617Z) + 0x8000));\n\tRd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]);\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULR.H D[c], D[a], D[b] UU, n (RR1)\n:mulr.h Rd2831,Rd0811,Rd1215^\"uu\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xf\n{\n\tlocal sc1 = (Rd0811[0,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1);\n\tlocal sc0 = (Rd0811[16,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1);\n\tlocal mres1:4;\n\tlocal mres0:4;\n\tternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[16,16]) << const1617Z) + 0x8000));\n\tternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[16,16]) << const1617Z) + 0x8000));\n\tRd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]);\n\tadvoverflowflagsww(mres1, mres0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULR.Q D[c], D[a] U, D[b] U, n (RR1)\n:mulr.q Rd2831,Rd0811^\"u\",Rd1215^\"u\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x6\n{\n\tlocal sc = (Rd0811[16,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1);\n\tlocal res:4;\n\tternary(res, sc, 0x7FFFFFFF, ((sext(Rd0811[16,16] * Rd1215[16,16]) << const1617Z) + 0x8000));\n\tRd2831 = zext(res[16,16] << 16);\n\tadvoverflowflags(res);\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULR.Q D[c], D[a] L, D[b] L, n (RR1)\n:mulr.q Rd2831,Rd0811^\"l\",Rd1215^\"l\",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x7\n{\n\tlocal sc = (Rd0811[0,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1);\n\tlocal res:4;\n\tternary(res, sc, 0x7FFFFFFF, ((sext(Rd0811[0,16] * Rd1215[0,16]) << const1617Z) + 0x8000));\n\tRd2831 = zext(res[16,16] << 16);\n\tadvoverflowflags(res);\n}\n@endif\n\n# MULS D[c], D[a], const9 (RC)\n:muls Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Rd2831 & op2127=0x5 ) & const1220S\n{\n\tlocal result:4 = Rd0811 * const1220S;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULS D[c], D[a], D[b] (RR2)\n:muls Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Rd2831 & op1627=0x8a\n{\n\tlocal result:4 = Rd0811 * Rd1215;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n@endif\n\n# MULS.U D[c], D[a], const9 (RC)\n:muls.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Rd2831 & op2127=0x4 ) & const1220Z\n{\n\tlocal result:4 = Rd0811 * const1220Z;\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# MULS.U D[c], D[a], D[b] (RR2)\n:muls.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Rd2831 & op1627=0x88\n{\n\tlocal result:4 = Rd0811 * Rd1215;\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n@endif\n\n# NAND D[c], D[a], D[b] (RR)\n:nand Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x90\n{\n\tRd2831 = ~(Rd0811 & Rd1215);\n}\n\n# NAND D[c], D[a], const9 (RC)\n:nand Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x9 ) & const1220Z\n{\n\tRd2831 = ~(Rd0811 & const1220Z);\n}\n\n# NAND.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:nand.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmp1:4 = (Rd0811 >> const1620Z) & 1;\n\tlocal tmp2:4 = (Rd1215 >> const2327Z) & 1;\n\tRd2831 = zext(!(tmp1[0,1] & tmp2[0,1]));\n}\n\n# NE D[c], D[a], D[b] (RR)\n:ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x110\n{\n\tRd2831 = zext(Rd0811 != Rd1215);\n}\n\n# NE D[c], D[a], const9 (RC)\n:ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x11 ) & const1220S\n{\n\tRd2831 = zext(Rd0811 != const1220S);\n}\n\n# NE.A D[c], A[a], A[b] (RR)\n:ne.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x410\n{\n\tRd2831 = zext(Ra0811 != Ra1215);\n}\n\n# NEZ.A D[c], A[a] (RR)\n:nez.a Rd2831,Ra0811 is PCPMode=0 & Ra0811 & op0007=0x1 & op1215=0x0 ; Rd2831 & op1627=0x490\n{\n\tRd2831 = zext(Ra0811 != 0);\n}\n\n# NOP (SR)\n:nop is PCPMode=0 & op0007=0x0 & op0815=0x0\n{\n\tlocal NOP:1 = 0:1;\n\tNOP = NOP;\n}\n\n# NOP (SYS)\n:nop is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x0\n{\n\tlocal NOP:1 = 0:1;\n\tNOP = NOP;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# NOT D[a] (SR)\n:not Rd0811 is PCPMode=0 & Rd0811 & op0007=0x46 & op1215=0x0\n{\n\tRd0811 = ~Rd0811;\n}\n@endif\n\n# NOR D[c], D[a], D[b] (RR)\n:nor Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xb0\n{\n\tRd2831 = ~(Rd0811 | Rd1215);\n}\n\n# NOR D[c], D[a], const9 (RC)\n:nor Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xb ) & const1220Z\n{\n\tRd2831 = ~(Rd0811 | const1220Z);\n}\n\n# NOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal tmp = Rd0811 >> const1620Z;\n\tlocal tmp2 = Rd1215 >> const2327Z;\n\tRd2831 = ~(tmp | tmp2) & 1;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# OR D[a], D[b] (SRR)\n:or Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa6\n{\n\tRd0811 = Rd0811 | Rd1215;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# OR D[15], const8 (SC)\n:or d15,const0815Z is PCPMode=0 & const0815Z & d15 & op0007=0x96\n{\n\td15 = d15 | const0815Z;\n}\n@endif\n\n# OR D[c], D[a], D[b] (RR)\n:or Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xa0\n{\n\tRd2831 = Rd0811 | Rd1215;\n}\n\n# OR D[c], D[a], const9 (RC)\n:or Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xa ) & const1220Z\n{\n\tRd2831 = Rd0811 | const1220Z;\n}\n\n# OR.AND.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:or.and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmp = (Rd0811 >> const1620Z) & 1;\n\tlocal tmp2 = (Rd1215 >> const2327Z) & 1;\n\tlocal tmp3 = zext(Rd2831[0,1]);\n\ttmp3 = tmp3 | (tmp & tmp2);\n\tRd2831[0,1] = tmp3[0,1];\n}\n\n# OR.ANDN.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:or.andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal tmp = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp2 = ((Rd1215 >> const2327Z) & 1) == 0;\n\tlocal tmp3 = (Rd2831 & 1) == 1;\n\ttmp3 = tmp3 | (tmp & tmp2);\n\tRd2831[0,1] = tmp3;\n}\n\n# OR.EQ D[c], D[a], D[b] (RR)\n:or.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x270\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 == Rd1215);\n}\n\n# OR.EQ D[c], D[a], const9 (RC)\n:or.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x27 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 == const1220S);\n}\n\n# OR.GE D[c], D[a], D[b] (RR)\n:or.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2b0\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 s>= Rd0811);\n}\n\n# OR.GE D[c], D[a], const9 (RC)\n:or.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2b ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 s>= const1220S);\n}\n\n# OR.GE.U D[c], D[a], D[b] (RR)\n:or.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2c0\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 >= Rd1215);\n}\n\n# OR.GE.U D[c], D[a], const9 (RC)\n:or.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2c ) & const1220Z\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 >= const1220Z);\n}\n\n# OR.LT D[c], D[a], D[b] (RR)\n:or.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x290\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 s< Rd0811);\n}\n\n# OR.LT D[c], D[a], const9 (RC)\n:or.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x29 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 s< const1220S);\n}\n\n# OR.LT.U D[c], D[a], D[b] (RR)\n:or.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2a0\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 < Rd0811);\n}\n\n# OR.LT.U D[c], D[a], const9 (RC)\n:or.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2a ) & const1220Z\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 < const1220Z);\n}\n\n# OR.NE D[c], D[a], D[b] (RR)\n:or.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x280\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 != Rd0811);\n}\n\n# OR.NE D[c], D[a], const9 (RC)\n:or.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x28 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] | (Rd0811 != const1220S);\n}\n\n# OR.NOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:or.nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal tmp = (Rd0811 >> const1620Z) & 1;\n\tlocal tmp2 = (Rd1215 >> const2327Z) & 1;\n\tlocal tmp3 = zext(Rd2831[0,1]);\n\ttmp3 = tmp3 | ~(tmp | tmp2);\n\tRd2831[0,1] = tmp3[0,1];\n}\n\n# OR.OR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:or.or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp = (Rd0811 >> const1620Z) & 1;\n\tlocal tmp2 = (Rd1215 >> const2327Z) & 1;\n\tlocal tmp3 = zext(Rd2831[0,1]);\n\ttmp3 = tmp3 | (tmp | tmp2);\n\tRd2831[0,1] = tmp3[0,1];\n}\n\n# OR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp = (Rd0811 >> const1620Z) & 1;\n\tlocal tmp2 = (Rd1215 >> const2327Z) & 1;\n\tRd2831 = tmp | tmp2;\n}\n\n# ORN D[c], D[a], D[b] (RR)\n:orn Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xf0\n{\n\tRd2831 = Rd0811 | ~Rd1215;\n}\n\n# ORN D[c], D[a], const9 (RC)\n:orn Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xf ) & const1220Z\n{\n\tRd2831 = Rd0811 | ~const1220Z;\n}\n\n# ORN.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:orn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp2 = ((Rd1215 >> const2327Z) & 1) == 0;\n\tRd2831 = zext(tmp | tmp2);\n}\n\n# PACK D[c], E[d], D[a] (RRR)\n:pack Rd2831,Ree2427/Reo2427,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x6b & op1215=0x0 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x0\n{\n\t#TODO o=exp e=mantissa D[a][31]=sign\n\t# int_exp = E[d][63:32];\n\t# int_mant = E[d][31:0];\n\t# flag_rnd = int_mant[7] AND (int_mant[8] OR int_mant[6:0] OR PSW.C);\n\t# if ((int_mant[31] == 0) AND (int_exp == +255)) then {\n\t# // Infinity or NaN\n\t# fp_exp = +255;\n\t# fp_frac = int_mant[30:8];\n\t# } else if ((int_mant[31] == 1) AND (int_exp >= +127)) then {\n\t# // Overflow ? Infinity.\n\t# fp_exp = +255;\n\t# fp_frac = 0;\n\t# } else if ((int_mant[31] == 1) AND (int_exp <= -128)) then {\n\t# // Underflow ? Zero\n\t# fp_exp = 0;\n\t# fp_frac = 0;\n\t# } else if (int_mant == 0) then {\n\t# // Zero\n\t# fp_exp = 0;\n\t# fp_frac = 0;\n\t# } else {\n\t# if (int_mant[31] == 0) then {\n\t# // Denormal\n\t# temp_exp = 0;\n\t# } else {\n\t# // Normal\n\t# temp_exp = int_exp + 128;\n\t# }\n\t# fp_exp_frac[30:0] = {tmp_exp[7:0], int_mant[30:8]} + flag_rnd;\n\t# fp_exp = fp_exp_frac[30:23];\n\t# fp_frac = fp_exp_frac[22:0];\n\t# }\n\t# D[c][31] = D[a][31];\n\t# D[c][30:23] = fp_exp;\n\t# D[c][22:0] = fp_frac;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# PARITY D[c], D[a] (RR)\n:parity Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x20\n{\n\tlocal result3:1 = Rd0811[24,1] ^ Rd0811[25,1] ^ Rd0811[26,1] ^ Rd0811[27,1] ^ Rd0811[28,1] ^ Rd0811[29,1] ^Rd0811[30,1] ^ Rd0811[31,1];\n\tlocal result2:1 = Rd0811[16,1] ^ Rd0811[17,1] ^ Rd0811[18,1] ^ Rd0811[19,1] ^ Rd0811[20,1] ^ Rd0811[21,1] ^Rd0811[22,1] ^ Rd0811[23,1];\n\tlocal result1:1 = Rd0811[8,1] ^ Rd0811[9,1] ^ Rd0811[10,1] ^ Rd0811[11,1] ^ Rd0811[12,1] ^ Rd0811[13,1] ^Rd0811[14,1] ^ Rd0811[15,1];\n\tlocal result0:1 = Rd0811[0,1] ^ Rd0811[1,1] ^ Rd0811[2,1] ^ Rd0811[3,1] ^ Rd0811[4,1] ^ Rd0811[5,1] ^ Rd0811[6,1] ^ Rd0811[7,1];\n\tRd2831 = zext(result3 << 24) | zext(result2 << 16) | zext(result1 << 8) | zext(result0);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# Q31TOF D[c], D[a], D[b] (RR)\n:q31tof Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x151\n{\n\t#TODO float\n\t#TODO flags\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# QSEED.F D[c], D[a] (RR)\n:qseed.f Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x191\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = 1 f/ sqrt(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# RESTORE D[a] (SYS)\n:restore Rd0811 is PCPMode=0 & Rd0811 & op0007=0xd & op1215=0x0 ; op1631=0x380\n{\n\t$(ICR_IE) = Rd0811[0,1];\n}\n@endif\n\n# RET (SR)\n:ret is PCPMode=0 & op0007=0x0 & op0815=0x90\n{\n\t#TODO ret\n\t# if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);\n\t# if (PCXI[19:0] == 0) then trap(CSU);\n\t# if (PCXI.UL == 0) then trap(CTYP);\n\t# PC = {A[11] [31:1], 1’b0};\n\t# EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};\n\t# {new_PCXI, new_PSW, a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15} = M(EA, 16 * word);\n\t# M(EA, word) = FCX;\n\t# FCX[19:0] = PCXI[19:0];\n\t# PCXI = new_PCXI;\n\t# PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]};\n\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\trestoreCallerState(FCX, LCX, PCXI);\n\treturn [tmp];\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# RET (SYS)\n:ret is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x180\n{\n\t#TODO ret\n\t# if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);\n\t# if (PCXI[19:0] == 0) then trap(CSU);\n\t# if (PCXI.UL == 0) then trap(CTYP);\n\t# PC = {A[11] [31:1], 1’b0};\n\t# EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};\n\t# {new_PCXI, new_PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15} = M(EA, 16 * word);\n\t# M(EA, word) = FCX;\n\t# FCX[19:0] = PCXI[19:0];\n\t# PCXI = new_PCXI;\n\t# PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]};\n\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\trestoreCallerState(FCX, LCX, PCXI);\n\treturn [tmp];\n}\n@endif\n\n# RFE (SR)\n:rfe is PCPMode=0 & op0007=0x0 & op0815=0x80\n{\n\t#TODO ret\n\t# if (PCXI[19:0] == 0) then trap(CSU);\n\t# if (PCXI.UL == 0) then trap(CTYP);\n\t# if (!cdc_zero() AND PSW.CDE) then trap(NEST);\n\t# PC = {A[11] [31:1], 1’b0};\n\t# ICR.IE = PCXI.PIE;\n\t# ICR.CCPN = PCXI.PCPN;\n\t# EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};\n\t# {new_PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}=M(EA,16*word);\n\t# M(EA, word) = FCX;\n\t# FCX[19:0] = PCXI[19:0];\n\t# PCXI = new_PCXI;\n\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\trestoreCallerState(FCX, LCX, PCXI);\n\treturn [tmp];\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# RFE (SYS)\n:rfe is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x1c0\n{\n\t#TODO ret\n\t# if (PCXI[19:0] == 0) then trap(CSU);\n\t# if (PCXI.UL == 0) then trap(CTYP);\n\t# if (!cdc_zero() AND PSW.CDE) then trap(NEST);\n\t# PC = {A[11] [31:1], 1’b0};\n\t# ICR.IE = PCXI.PIE;\n\t# ICR.CCPN = PCXI.PCPN;\n\t# EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};\n\t# {new_PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}=M(EA,16*word);\n\t# M(EA, word) = FCX;\n\t# FCX[19:0] = PCXI[19:0];\n\t# PCXI = new_PCXI;\n\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\trestoreCallerState(FCX, LCX, PCXI);\n\treturn [tmp];\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# RFM (SYS)\n:rfm is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x140\n{\n\t#TODO ret\n\t# if (PSW.IO != 2’b10) then trap (PRIV);\n\t# if (DBGSR.DE) then{\n\t# PC = {A[11] [31:1], 1’b0};\n\t# ICR.IE = PCXI.IE;\n\t# ICR.CCPN = PCXI.PCPN;\n\t# EA = DCX;\n\t# {PCXI, PSW, A[10], A[11]} = M(EA, 4 * word);\n\t# DBGTCR.DTA = 0;\n\t# }else{\n\t# NOP\n\t# }\n\n\tlocal tmp:4 = a11 & 0xFFFFFFFE;\n\trestoreCallerState(FCX, LCX, PCXI);\n\treturn [tmp];\n}\n@endif\n\n# RSLCX (SYS)\n:rslcx is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x240\n{\n\t#TODO context\n\t# if(PCXI[19:0] == 0) then trap(CSU);\n\t# if(PCXI.UL == 1) then trap(CTYP);\n\t# EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};\n\t# {new_PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4], A[5], A[6], A[7], D[4], D[5], D[6], D[7]} = M(EA, 16*word);\n\t# M(EA, word) = FCX;\n\t# FCX[19:0] = PCXI[19:0];\n\t# PCXI = new_PCXI;\n}\n\n# RSTV (SYS)\n:rstv is PCPMode=0 & op0007=0x2f & op0815=0x0 ; op1631=0x0\n{\n $(PSW_V) = 0;\n $(PSW_SV) = 0;\n $(PSW_AV) = 0;\n $(PSW_SAV) = 0;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# RSUB D[a] (SR)\n:rsub Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x5\n{\n\tRd0811 = 0 - Rd0811;\n\toverflowflags(Rd0811);\n}\n@endif\n\n# RSUB D[c], D[a], const9 (RC)\n:rsub Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x8 ) & const1220S\n{\n\tRd2831 = const1220S - Rd0811;\n\toverflowflags(Rd2831);\n}\n\n# RSUBS D[c], D[a], const9 (RC)\n:rsubs Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xa ) & const1220S\n{\n\tlocal result:4 = const1220S - Rd0811;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# RSUBS.U D[c], D[a], const9 (RC)\n:rsubs.u Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xb ) & const1220S\n{\n\tlocal result:4 = const1220S - Rd0811;\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SAT.B D[a] (SR)\n:sat.b Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x0\n{\n\tlocal sat_neg:4;\n\tternary(sat_neg, Rd0811 s< -0x80, -0x80, Rd0811);\n\tternary(Rd0811, sat_neg s> 0x7f, 0x7f, sat_neg);\n}\n@endif\n\n# SAT.B D[c], D[a] (RR)\n:sat.b Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x5e0\n{\n\tlocal sat_neg:4;\n\tternary(sat_neg, Rd0811 s< -0x80, -0x80, Rd0811);\n\tternary(Rd2831, sat_neg s> 0x7f, 0x7f, sat_neg);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SAT.BU D[a] (SR)\n:sat.bu Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x1\n{\n\tternary(Rd0811, Rd0811 > 0xff, 0xff, Rd0811);\n}\n@endif\n\n# SAT.BU D[c], D[a] (RR)\n:sat.bu Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x5f0\n{\n\tternary(Rd2831, Rd0811 > 0xff, 0xff, Rd0811);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SAT.H D[a] (SR)\n:sat.h Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x2\n{\n\tlocal sat_neg:4;\n\tternary(sat_neg, Rd0811 s< -0x8000, -0x8000, Rd0811);\n\tternary(Rd0811, sat_neg s> 0x7fff, 0x7fff, sat_neg);\n}\n@endif\n\n# SAT.H D[c], D[a] (RR)\n:sat.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x7e0\n{\n\tlocal sat_neg:4;\n\tternary(sat_neg, Rd0811 s< -0x8000, -0x8000, Rd0811);\n\tternary(Rd2831, sat_neg s> 0x7fff, 0x7fff, sat_neg);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SAT.HU D[a] (SR)\n:sat.hu Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x3\n{\n\tternary(Rd0811, Rd0811 > 0xffff, 0xffff, Rd0811);\n}\n@endif\n\n# SAT.HU D[c], D[a] (RR)\n:sat.hu Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x7f0\n{\n\tternary(Rd2831, Rd0811 > 0xffff, 0xffff, Rd0811);\n}\n\n# SEL D[c], D[d], D[a], D[b] (RRR)\n:sel Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x40\n{\n\tternary(Rd2831, Rd2427 != 0, Rd0811, Rd1215);\n}\n\n# SEL D[c], D[d], D[a], const9 (RCR)\n:sel Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x4 ) & const1220S\n{\n\tternary(Rd2831, Rd2427 != 0, Rd0811, const1220S);\n}\n\n# SELN D[c], D[d], D[a], D[b] (RRR)\n:seln Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x50\n{\n\tternary(Rd2831, Rd2427 == 0, Rd0811, Rd1215);\n}\n\n# SELN D[c], D[d], D[a], const9 (RCR)\n:seln Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x5 ) & const1220S\n{\n\tternary(Rd2831, Rd2427 == 0, Rd0811, const1220S);\n}\n\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SH D[a], const4 (SRC)\n:sh Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x6 & op1515=1\n{\n\tlocal tmp = -const1215S;\n\tRd0811 = Rd0811 >> tmp;\n}\n\n# SH D[a], const4 (SRC)\n:sh Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x6 & op1515=0\n{\n\tRd0811 = Rd0811 << const1215S;\n}\n@endif\n\n# SH D[c], D[a], D[b] (RR)\n:sh Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x0\n{\n\tlocal shift_count:4 = sext(Rd1215[0,6]);\n\tshift_count = (shift_count << (32 - 6)) s>> (32 - 6);\n\tternary(Rd2831, shift_count s>= 0, Rd0811 << shift_count, Rd0811 >> -shift_count);\n}\n\n# SHD[c], D[a], const9 (RC)\n:sh Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x0 & op2020=1) & const1220S\n{\n\tlocal tmp = -const1220S;\n\tRd2831 = Rd0811 >> tmp[0,6];\n}\n\n# SHD[c], D[a], const9 (RC)\n:sh Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x0 & op2020=0 ) & const1220S\n{\n\tRd2831 = Rd0811 << const1220S[0,6];\n}\n\n# SH.AND.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal pos1 = (Rd0811 >> const1620Z) & 1;\n\tlocal pos2 = (Rd1215 >> const2327Z) & 1;\n\tlocal tmp = pos1 & pos2;\n\tRd2831 = (Rd2831 << 1) | zext(tmp[0,1]);\n}\n\n# SH.ANDN.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal pos1 = (Rd0811 >> const1620Z) & 1;\n\tlocal pos2 = (Rd1215 >> const2327Z) & 1;\n\tlocal tmp = pos1 & ~pos2;\n\tRd2831 = (Rd2831 << 1) | zext(tmp[0,1]);\n}\n\n# SH.EQ D[c], D[a], D[b] (RR)\n:sh.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x370\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 == Rd1215);\n}\n\n# SH.EQ D[c], D[a], const9 (RC)\n:sh.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x37 ) & const1220S\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 == const1220S);\n}\n\n# SH.GE D[c], D[a], D[b] (RR)\n:sh.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x3b0\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 s>= Rd1215);\n}\n\n# SH.GE D[c], D[a], const9 (RC)\n:sh.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3b ) & const1220S\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 s>= const1220S);\n}\n\n# SH.GE.U D[c], D[a], D[b] (RR)\n:sh.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x3c0\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 >= Rd1215);\n}\n\n# SH.GE.U D[c], D[a], const9 (RC)\n:sh.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3c ) & const1220Z\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 >= const1220Z);\n}\n\n# SH.H D[c], D[a], D[b] (RR)\n:sh.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x400\n{\n\tlocal res1:2;\n\tlocal res0:2;\n\tlocal shift_count:4 = sext(Rd1215[0,5]);\n\tshift_count = (shift_count << (16 - 5)) s>> (16 - 5);\n\tternary(res1, (shift_count s>= 0), Rd0811[16,16] << shift_count, Rd0811[16,16] >> -shift_count);\n\tternary(res0, (shift_count s>= 0), Rd0811[0,16] << shift_count, Rd0811[0,16] >> -shift_count);\n\tRd2831 = zext(res1 << 16) | zext(res0);\n}\n\n# SH.H D[c], D[a], const9 (RC)\n:sh.h Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x40 ) & const1220S\n{\n\tlocal res1:2;\n\tlocal res0:2;\n\tlocal shift_count = sext(const1220S[0,5]);\n\tshift_count = (shift_count << (16 - 5)) s>> (16 - 5);\n\tternary(res1, (shift_count s>= 0), Rd0811[16,16] << shift_count, Rd0811[16,16] >> -shift_count);\n\tternary(res0, (shift_count s>= 0), Rd0811[0,16] << shift_count, Rd0811[0,16] >> -shift_count);\n\tRd2831 = zext(res1 << 16) | zext(res0);\n}\n\n# SH.LT D[c], D[a], D[b] (RR)\n:sh.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x390\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 s< Rd1215);\n}\n\n# SH.LT D[c], D[a], const9 (RC)\n:sh.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x39 ) & const1220S\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 s< const1220S);\n}\n\n# SH.LT.U D[c], D[a], D[b] (RR)\n:sh.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x3a0\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 < Rd1215);\n}\n\n# SH.LT.U D[c], D[a], const9 (RC)\n:sh.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3a ) & const1220Z\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 < const1220Z);\n}\n\n# SH.NAND.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.nand.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0\n{\n\tlocal tmp1 = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp0 = ((Rd1215 >> const2327Z) & 1) == 1;\n\tlocal res = !(tmp1 && tmp0);\n\tRd2831 = (Rd2831 << 1) | zext(res);\n}\n\n# SH.NE D[c], D[a], D[b] (RR)\n:sh.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x380\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 != Rd1215);\n}\n\n# SH.NE D[c], D[a], const9 (RC)\n:sh.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x38 ) & const1220S\n{\n\tRd2831 = (Rd2831 << 1) | zext(Rd0811 != const1220S);\n}\n\n# SH.NOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal tmp1 = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp0 = ((Rd1215 >> const2327Z) & 1) == 1;\n\tlocal res = !(tmp1 || tmp0);\n\tRd2831 = (Rd2831 << 1) | zext(res);\n}\n\n# SH.OR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp1 = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp0 = ((Rd1215 >> const2327Z) & 1) == 1;\n\tlocal res = tmp1 || tmp0;\n\tRd2831 = (Rd2831 << 1) | zext(res);\n}\n\n# SH.ORN.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.orn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x1\n{\n\tlocal tmp1 = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp0 = ((Rd1215 >> const2327Z) & 1) == 1;\n\tlocal res = tmp1 || !tmp0;\n\tRd2831 = (Rd2831 << 1) | zext(res);\n}\n\n# SH.XNOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.xnor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal tmp1 = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp0 = ((Rd1215 >> const2327Z) & 1) == 1;\n\tlocal res = !(tmp1 ^ tmp0);\n\tRd2831 = (Rd2831 << 1) | zext(res);\n}\n\n# SH.XOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:sh.xor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal tmp1 = ((Rd0811 >> const1620Z) & 1) == 1;\n\tlocal tmp0 = ((Rd1215 >> const2327Z) & 1) == 1;\n\tlocal res = tmp1 ^ tmp0;\n\tRd2831 = (Rd2831 << 1) | zext(res);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SHA D[a], const4 (SRC)\n:sha Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x86\n{\n\tlocal shift_count:4 = sext(const1215S[0,4]);\n\tshift_count = (shift_count << (32 - 4)) s>> (32 - 4);\n\tlocal res:4 = Rd0811;\n\tlocal shift_dir:1 = shift_count s< 0;\n\tres = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1);\n\toverflowflags(res);\n\tRd0811 = res;\n}\n@endif\n\n# SHA D[c], D[a], D[b] (RR)\n:sha Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x10\n{\n\tlocal shift_count:4 = sext(Rd1215[0,6]);\n\tshift_count = (shift_count << (32 - 6)) s>> (32 - 6);\n\tlocal res:4 = Rd0811;\n\tlocal shift_dir:1 = shift_count s< 0;\n\tres = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1);\n\toverflowflags(res);\n\tRd2831 = res;\n}\n\n# SHA D[c], D[a], const9 (RC)\n:sha Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x1 ) & const1220S\n{\n\tlocal shift_count:4 = sext(const1220S[0,6]);\n\tshift_count = (shift_count << (32 - 6)) s>> (32 - 6);\n\tlocal res:4 = Rd0811;\n\tlocal shift_dir:1 = shift_count s< 0;\n\tres = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1);\n\toverflowflags(res);\n\tRd2831 = res;\n}\n\n# SHA.H D[c], D[a], D[b] (RR)\n:sha.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x410\n{\n\tlocal shift_count:4 = sext(Rd1215[0,5]);\n\tlocal res1:4 = sext(Rd0811[16,16]);\n\tlocal res0:4 = sext(Rd0811[0,16]);\n\tif (shift_count s> 0) goto ;\n\tif (shift_count == 0) goto ;\n\tshift_count = 0 - shift_count;\n\tlocal msk:4;\n\tternary(msk, Rd0811[31,1] != 0, (((1 << shift_count) - 1) << (16 - shift_count)), 0);\n\tres1 = msk | sext(Rd0811[16,16] s>> shift_count);\n\tres0 = msk | sext(Rd0811[0,16] s>> shift_count);\n\tgoto ;\n \n\tres1 = sext(Rd0811[16,16] << shift_count);\n\tres0 = sext(Rd0811[0,16] << shift_count);\n \n\tRd2831 = zext(res1[0,16] << 16) | zext(res0[0,16]);\n}\n\n# SHA.H D[c], D[a], const9 (RC)\n:sha.h Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x41 ) & const1220S\n{\n\tlocal shift_count:4 = sext(const1220S[0,5]);\n\tlocal res1:4 = sext(Rd0811[16,16]);\n\tlocal res0:4 = sext(Rd0811[0,16]);\n\tif (shift_count s> 0) goto ;\n\tif (shift_count == 0) goto ;\n\tshift_count = 0 - shift_count;\n\tlocal msk:4;\n\tternary(msk, Rd0811[31,1] != 0, (((1 << shift_count) - 1) << (16 - shift_count)), 0);\n\tres1 = msk | sext(Rd0811[16,16] s>> shift_count);\n\tres0 = msk | sext(Rd0811[0,16] s>> shift_count);\n\tgoto ;\n \n\tres1 = sext(Rd0811[16,16] << shift_count);\n\tres0 = sext(Rd0811[0,16] << shift_count);\n \n\tRd2831 = (zext(res1[0,16]) << 16) | zext(res0[0,16]);\n}\n\n# SHAS D[c], D[a], D[b] (RR)\n:shas Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x20\n{\n\tlocal shift_count:4 = sext(Rd1215[0,6]);\n\tshift_count = (shift_count << (32 - 6)) s>> (32 - 6);\n\tlocal res:4 = Rd0811;\n\tlocal shift_dir:1 = shift_count s< 0;\n\tres = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1);\n\toverflowflags(res);\n\tssov(Rd2831, res, 32);\n}\n\n# SHAS D[c], D[a], const9 (RC)\n:shas Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x2 ) & const1220S\n{\n\tlocal shift_count:4 = sext(const1220S[0,6]);\n\tshift_count = (shift_count << (32 - 6)) s>> (32 - 6);\n\tlocal res:4 = Rd0811;\n\tlocal shift_dir:1 = shift_count s< 0;\n\tres = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1);\n\toverflowflags(res);\n\tssov(Rd2831, res, 32);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.A A[10], const8, A[15] (SC)\n:st.a SC,a15 is PCPMode=0 & a15 & op0007=0xf8 & SC\n{\n\tbuild SC;\n\t*[ram]:4 SC = a15;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.A A[b], off4, A[15] (SRO)\n:st.a SRO,a15 is PCPMode=0 & a15 & op0007=0xec & SRO\n{\n\tbuild SRO;\n\t*[ram]:4 SRO = a15;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.A A[15], off4, A[a] (SSRO)\n:st.a SSRO,Ra0811 is PCPMode=0 & Ra0811 & op0007=0xe8 & SSRO\n{\n\tbuild SSRO;\n\t*[ram]:4 SSRO = Ra0811;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.A A[b], A[a] (SSR)(Post-increment Addressing Mode)\n# ST.A A[b], A[a] (SSR)\n:st.a SSR,Ra0811 is PCPMode=0 & Ra0811 & op0607=0x3 & SSR\n{\n\tbuild SSR;\n\t*[ram]:4 SSR = Ra0811;\n}\n@endif\n\n# ST.A A[b], off10, A[a] (BO)(Post-increment Addressing Mode)\n# ST.A P[b], A[a] (BO)(Bit-reverse Addressing Mode)\n# ST.A A[b], off10, A[a] (BO)(Pre-increment Addressing Mode)\n# ST.A A[b], off10, A[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.A P[b], A[a] (BO)(Index Addressing Mode)\n:st.a BO,Ra0811 is PCPMode=0 & ( Ra0811 & op0607=0x2 ; op2225=0x6 ) & BO\n{\n\tbuild BO;\n\t*[ram]:4 BO = Ra0811;\n}\n\n# ST.A P[b], off10, A[a] (BO)(Circular Addressing Mode)\n#:st.a BO,Ra0811 is PCPMode=0 & ( Ra0811 & op0007=0xa9 ; op2227=0x16 ) & BO\n:st.a [Rpe1215/Rpo1215^\"+c\"^]off10,Ra0811 is PCPMode=0 & Ra0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x16\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\t*[ram]:4 EA = Ra0811;\n}\n\n# ST.A off18, A[a] (ABS)(Absolute Addressing Mode)\n:st.a off18,Ra0811 is PCPMode=0 & ( Ra0811 & op0007=0xa5 ; op2627=0x2 ) & off18\n{\n\t*[ram]:4 off18 = Ra0811;\n}\n\n# ST.A A[b], off16, A[a] (BOL)(Base + Long Offset Addressing Mode)\n:st.a BOL,Ra0811 is PCPMode=0 & ( Ra0811 & op0007=0xb5 ) ... & BOL\n{\n\tbuild BOL;\n\t*[ram]:4 BOL = Ra0811;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.B A[b], D[a] (SSR)\n# ST.B A[b], D[a] (SSR)(Post-increment Addressing Mode)\n:st.b SSR,Rd0811 is PCPMode=0 & Rd0811 & op0607=0x0 & SSR\n{\n\tbuild SSR;\n\t*[ram]:1 SSR = Rd0811[0,8];\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.B A[15], off4, D[a] (SSRO)\n:st.b SSRO,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x28 & SSRO\n{\n\tbuild SSRO;\n\t*[ram]:1 SSRO = Rd0811[0,8];\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.B A[b], off4, D[15] (SRO)\n:st.b SRO,d15 is PCPMode=0 & d15 & op0007=0x2c & SRO\n{\n\tbuild SRO;\n\t*[ram]:1 SRO = d15[0,8];\n}\n@endif\n\n# ST.B off18, D[a] (ABS)(Absolute Addressing Mode)\n:st.b off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x25 ; op2627=0x0 ) & off18\n{\n\t*[ram]:1 off18 = Rd0811[0,8];\n}\n\n# ST.B A[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode)\n:st.b BOL,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xe9 ) ... & BOL\n{\n\tbuild BOL;\n\t*[ram]:1 BOL = Rd0811[0,8];\n}\n\n# ST.B A[b], off10, D[a] (BO)(Post-increment Addressing Mode)\n# ST.B P[b], D[a] (BO)(Bit-reverse Addressing Mode)\n# ST.B A[b], off10, D[a] (BO)(Pre-increment Addressing Mode)\n# ST.B A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.B P[b], D[a] (BO)(Index Addressing Mode)\n:st.b BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x0 ) & BO\n{\n\tbuild BO;\n\t*[ram]:1 BO = Rd0811[0,8];\n}\n\n# ST.B P[b], off10, D[a] (BO)(Circular Addressing Mode)\n#:st.b BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x10 ) & BO\n:st.b [Rpe1215/Rpo1215^\"+c\"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x10\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\t*[ram]:1 EA = Rd0811[0,8];\n}\n\n# ST.D A[b], off10, E[a] (BO)(Post-increment Addressing Mode)\n# ST.D P[b], E[a] (BO)(Bit-reverse Addressing Mode)\n# ST.D A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)\n# ST.D A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.D P[b], E[a] (BO)(Index Addressing Mode)\n:st.d BO,Re0811 is PCPMode=0 & ( Re0811 & op0607=0x2 ; op2225=0x5 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Re0811;\n}\n\n# ST.D off18, E[a] (ABS)(Absolute Addressing Mode)\n:st.d off18,Re0811 is PCPMode=0 & ( Re0811 & op0007=0xa5 ; op2627=0x1 ) & off18\n{\n\t*[ram]:8 off18 = Re0811;\n}\n\n# ST.D P[b], off10, E[a] (BO)(Circular Addressing Mode)\n#:st.d BO,Re0811 is PCPMode=0 & ( Re0811 & op0007=0xa9 ; op2227=0x15 ) & BO\n:st.d [Rpe1215/Rpo1215^\"+c\"^]off10,Re0811 is PCPMode=0 & Re0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x15\n{\n\tlocal EA0:4;\n\tlocal EA2:4;\n\tlocal EA4:4;\n\tlocal EA6:4;\n\tCircularAddressingMode4(Rpe1215, Rpo1215, EA0, EA2, EA4, EA6, off10, 2);\n\t*[ram]:2 EA6 = Re0811[48,16];\n\t*[ram]:2 EA4 = Re0811[32,16];\n\t*[ram]:2 EA2 = Re0811[16,16];\n\t*[ram]:2 EA0 = Re0811[0,16];\n}\n\n# ST.DA A[b], off10, P[a] (BO)(Post-increment Addressing Mode)\n# ST.DA P[b], P[a] (BO)(Bit-reverse Addressing Mode)\n# ST.DA A[b], off10, P[a] (BO)(Pre-increment Addressing Mode)\n# ST.DA A[b], off10, P[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.DA P[b], P[a] (BO)(Index Addressing Mode)\n:st.da BO,Rp0811 is PCPMode=0 & ( Rp0811 & op0607=0x2 ; op2225=0x7 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Rp0811;\n}\n\n# ST.DA P[b], off10, P[a] (BO)(Circular Addressing Mode)\n#:st.da BO,Rp0811 is PCPMode=0 & ( Rp0811 & op0007=0xa9 ; op2227=0x17 ) & BO\n:st.da [Rpe1215/Rpo1215^\"+c\"^]off10,Rp0811 is PCPMode=0 & Rp0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x17\n{\n\tlocal EA0:4;\n\tlocal EA4:4;\n\tCircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA4, off10, 4);\n\t*[ram]:4 EA0 = Rp0811[0,32];\n\t*[ram]:4 EA4 = Rp0811[32,32];\n}\n\n# ST.DA off18, P[a] (ABS)(Absolute Addressing Mode)\n:st.da off18,Rp0811 is PCPMode=0 & ( Rp0811 & op0007=0xa5 ; op2627=0x3 ) & off18\n{\n\t*[ram]:8 off18 = Rp0811;\n}\n\n@if defined(TRICORE_V2)\n:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x89 ; op2227=0x9 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Re0811;\n\t*[ram]:8 BO+8 = ReN0811;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0xa9 ; op1621=0x0 & op2227=0x09 & op2831=0x0 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Re0811;\n\t*[ram]:8 BO+8 = ReN0811;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x89 ; op2227=0x19 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Re0811;\n\t*[ram]:8 BO+8 = ReN0811;\n}\n@endif\n\n@if defined(TRICORE_V2)\n#:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0xa9 ; op2227=0x19 ) & BO\n:st.dd [Rpe1215/Rpo1215^\"+c\"^]off10,Re0811/ReN0811 is PCPMode=0 & Re0811 & ReN0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x19\n{\n\tlocal EA0:4;\n\tlocal EA8:4;\n\tCircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA8, off10, 8);\n\t*[ram]:8 EA0 = Re0811;\n\t*[ram]:8 EA8 = ReN0811;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x89 ; op2227=0x29 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Re0811;\n\t*[ram]:8 BO+8 = ReN0811;\n}\n@endif\n\n@if defined(TRICORE_V2)\n:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0xa9 ; op1621=0x0 & op2227=0x29 & op2831=0x0 ) & BO\n{\n\tbuild BO;\n\t*[ram]:8 BO = Re0811;\n\t*[ram]:8 BO+8 = ReN0811;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.H A[b], D[a] (SSR)(Post-increment Addressing Mode)\n# ST.H A[b], D[a] (SSR)\n:st.h SSR,Rd0811 is PCPMode=0 & Rd0811 & op0607=0x2 & SSR\n{\n\tbuild SSR;\n\t*[ram]:2 SSR = Rd0811[0,16];\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.H A[15], off4, D[a] (SSRO)\n:st.h SSRO,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xa8 & SSRO\n{\n\tbuild SSRO;\n\t*[ram]:2 SSRO = Rd0811[0,16];\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.H A[b], off4, D[15] (SRO)\n:st.h SRO,d15 is PCPMode=0 & d15 & op0007=0xac & SRO\n{\n\tbuild SRO;\n\t*[ram]:2 SRO = d15[0,16];\n}\n@endif\n\n# ST.H A[b], off10, D[a] (BO)(Post-increment Addressing Mode)\n# ST.H P[b], D[a] (BO)(Bit-reverse Addressing Mode)\n# ST.H A[b], off10, D[a] (BO)(Pre-increment Addressing Mode)\n# ST.H A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.H P[b], D[a] (BO)(Index Addressing Mode)\n:st.h BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x2 ) & BO\n{\n\tbuild BO;\n\t*[ram]:2 BO = Rd0811[0,16];\n}\n\n# ST.H A[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode)\n:st.h BOL,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xf9 ) ... & BOL\n{\n\tbuild BOL;\n\t*[ram]:2 BOL = Rd0811[0,16];\n}\n\n# ST.H P[b], off10, D[a] (BO)(Circular Addressing Mode)\n#:st.h BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x12 ) & BO\n:st.h [Rpe1215/Rpo1215^\"+c\"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x12\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\t*[ram]:2 EA = Rd0811[0,16];\n}\n\n# ST.H off18, D[a] (ABS)(Absolute Addressing Mode)\n:st.h off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x25 ; op2627=0x2 ) & off18\n{\n\t*[ram]:2 off18 = Rd0811[0,16];\n}\n\n# ST.Q off18, D[a] (ABS)(Absolute Addressing Mode)\n:st.q off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x65 ; op2627=0x0 ) & off18\n{\n\t*[ram]:2 off18 = Rd0811[16,16];\n}\n\n# ST.Q A[b], off10, D[a] (BO)(Post-increment Addressing Mode)\n# ST.Q P[b], D[a] (BO)(Bit-reverse Addressing Mode)\n# ST.Q A[b], off10, D[a] (BO)(Pre-increment Addressing Mode)\n# ST.Q A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.Q P[b], D[a] (BO)(Index Addressing Mode)\n:st.q BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x8 ) & BO\n{\n\tbuild BO;\n\t*[ram]:2 BO = Rd0811[16,16];\n}\n\n#:st.q BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x18 ) & BO\n:st.q [Rpe1215/Rpo1215^\"+c\"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x18\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\t*[ram]:2 EA = Rd0811[16,16];\n}\n\n# ST.T off18, bpos3, b (ABSB)\n:st.t off18,const0810Z,const1111Z is PCPMode=0 & ( const0810Z & const1111Z & op0007=0xd5 ; op2627=0x0 ) & off18\n{\n\tlocal tmp:1 = *[ram]:1 off18;\n\tternary(tmp, const1111Z,\n\t\ttmp | (1 << const0810Z),\n\t\ttmp & ~(1 << const0810Z));\n\t*[ram]:1 off18 = tmp;\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.W A[10], const8, D[15] (SC)\n:st.w SC,d15 is PCPMode=0 & d15 & op0007=0x78 & SC\n{\n\tbuild SC;\n\t*[ram]:4 SC = d15;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.W A[b], D[a] (SSR)\n# ST.W A[b], D[a] (SSR)(Post-increment Addressing Mode)\n:st.w SSR,Rd0811 is PCPMode=0 & Rd0811 & op0607=0x1 & SSR\n{\n\tbuild SSR;\n\t*[ram]:4 SSR = Rd0811;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.W A[15], off4, D[a] (SSRO)\n:st.w SSRO,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x68 & SSRO\n{\n\tbuild SSRO;\n\t*[ram]:4 SSRO = Rd0811;\n}\n@endif\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# ST.W A[b], off4, D[15] (SRO)\n:st.w SRO,d15 is PCPMode=0 & d15 & op0007=0x6c & SRO\n{\n\tbuild SRO;\n\t*[ram]:4 SRO = d15;\n}\n@endif\n\n# ST.W A[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode)\n:st.w BOL,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x59 ) ... & BOL\n{\n\tbuild BOL;\n\t*[ram]:4 BOL = Rd0811;\n}\n\n# ST.W off18, D[a] (ABS)(Absolute Addressing Mode)\n:st.w off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa5 ; op2627=0x0 ) & off18\n{\n\t*[ram]:4 off18 = Rd0811;\n}\n\n# ST.W A[b], off10, D[a] (BO)(Post-increment Addressing Mode)\n# ST.W P[b], D[a] (BO)(Bit-reverse Addressing Mode)\n# ST.W A[b], off10, D[a] (BO)(Pre-increment Addressing Mode)\n# ST.W A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)\n# ST.W P[b], D[a] (BO)(Index Addressing Mode)\n:st.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x4 ) & BO\n{\n\tbuild BO;\n\t*[ram]:4 BO = Rd0811;\n}\n\n# ST.W P[b], off10, D[a] (BO)(Circular Addressing Mode)\n#:st.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x14 ) & BO\n:st.w [Rpe1215/Rpo1215^\"+c\"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x14\n{\n\tlocal EA0:4;\n\tlocal EA2:4;\n\tCircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA2, off10, 2);\n\t*[ram]:2 EA2 = Rd0811[16,16];\n\t*[ram]:2 EA0 = Rd0811[0,16];\n}\n\n# STLCX off18 (ABS)(Absolute Addressing Mode)\n:stlcx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x0 ) & off18\n{\n\t#TODO context\n\tstore_lower_context(off18);\n}\n\n# STLCX A[b], off10 (BO)(Base + Short Index Addressing Mode)\n:stlcx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; op2227=0x26 ) & BO\n{\n\t#TODO context\n\tbuild BO;\n\tstore_lower_context(BO);\n}\n\n# STUCX off18 (ABS)(Absolute Addressing Mode)\n:stucx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x1 ) & off18\n{\n\t#TODO context\n\tstore_upper_context(off18);\n}\n\n# STUCX A[b], off10 (BO)(Base + Short Index Addressing Mode)\n:stucx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; op2227=0x27 ) & BO\n{\n\t#TODO context\n\tbuild BO;\n\tstore_upper_context(BO);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SUB D[a], D[15], D[b] (SRR)\n:sub Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x52\n{\n\tRd0811 = d15 - Rd1215;\n\toverflowflags(Rd0811);\n}\n@endif\n\n# SUB D[15], D[a], D[b] (SRR)\n:sub d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x5a\n{\n\td15 = Rd0811 - Rd1215;\n\toverflowflags(d15);\n}\n\n# SUB D[a], D[b] (SRR)\n:sub Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa2\n{\n\tRd0811 = Rd0811 - Rd1215;\n\toverflowflags(Rd0811);\n}\n\n# SUB D[c], D[a], D[b] (RR)\n:sub Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x80\n{\n\tRd2831 = Rd0811 - Rd1215;\n\toverflowflags(Rd2831);\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SUB.A A[10], const8 (SC)\n:sub.a a10,const0815Z is PCPMode=0 & a10 & const0815Z & op0007=0x20\n{\n\ta10 = a10 - const0815Z;\n}\n@endif\n\n# SUB.A A[c], A[a], A[b] (RR)\n:sub.a Ra2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Ra2831 & op1627=0x20\n{\n\tRa2831 = Ra0811 - Ra1215;\n}\n\n# SUB.B D[c], D[a], D[b] (RR)\n:sub.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x480\n{\n\tlocal result3:4 = zext(Rd0811[24,8] - Rd1215[24,8]);\n\tlocal result2:4 = zext(Rd0811[16,8] - Rd1215[16,8]);\n\tlocal result1:4 = zext(Rd0811[8,8] - Rd1215[8,8]);\n\tlocal result0:4 = zext(Rd0811[0,8] - Rd1215[0,8]);\n\toverflowflagsb(result3, result2, result1, result0);\n\tRd2831 = zext(result3[0,8] << 24) | zext(result2[0,8] << 16) | zext(result1[0,8] << 8) | zext(result0[0,8]);\n}\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# SUB.F D[c], D[d], D[a] (RRR)\n:sub.f Rd2831,Rd2427,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x6b & op1215=0x0 ; Rd2427 & Rd2831 & op1623=0x31\n{\n\t#TODO float\n\t#TODO flags\n\tRd2831 = Rd2427 f- Rd0811;\n}\n@endif\n\n# SUB.H D[c], D[a], D[b] (RR)\n:sub.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x680\n{\n\tlocal result1:4 = zext(Rd0811[16,16] - Rd1215[16,16]);\n\tlocal result0:4 = zext(Rd0811[0,16] - Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tRd2831 = (zext(result1[0,16]) << 16) | zext(result0[0,16]);\n}\n\n# SUBC D[c], D[a], D[b] (RR)\n:subc Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xd0\n{\n\tlocal tmp:5 = zext(Rd0811) - zext(Rd1215) + zext($(PSW_C)) - 1;\n\tRd2831 = tmp[0,32];\n\t$(PSW_C) = tmp[32,1];\n\toverflowflags(Rd2831);\n}\n\n# SUBS D[a], D[b] (SRR)\n:subs Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x62\n{\n\tlocal result:4 = Rd0811 - Rd1215;\n\toverflowflags(result);\n\tssov(Rd0811, result, 32);\n}\n\n# SUBS D[c], D[a], D[b] (RR)\n:subs Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xa0\n{\n\tlocal result:4 = Rd0811 - Rd1215;\n\toverflowflags(result);\n\tssov(Rd2831, result, 32);\n}\n\n# SUBS.H D[c], D[a], D[b] (RR)\n:subs.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6a0\n{\n\tlocal result1:4 = zext(Rd0811[16,16] - Rd1215[16,16]);\n\tlocal result0:4 = zext(Rd0811[0,16] - Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tssov(Rd2831[16,16], result1[0,16], 16);\n\tssov(Rd2831[0,16], result0[0,16], 16);\n}\n\n# SUBS.HU D[c], D[a], D[b] (RR)\n:subs.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6b0\n{\n\tlocal result1:4 = zext(Rd0811[16,16] - Rd1215[16,16]);\n\tlocal result0:4 = zext(Rd0811[0,16] - Rd1215[0,16]);\n\toverflowflagsh(result1, result0);\n\tsuov(Rd2831[16,16], result1[0,16], 16);\n\tsuov(Rd2831[0,16], result0[0,16], 16);\n}\n\n# SUBS.U D[c], D[a], D[b] (RR)\n:subs.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xb0\n{\n\tlocal result:4 = Rd0811 - Rd1215;\n\toverflowflags(result);\n\tsuov(Rd2831, result, 32);\n}\n\n# SUBX D[c], D[a], D[b] (RR)\n:subx Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xc0\n{\n\tRd2831 = Rd0811 - Rd1215;\n\tlocal tmp:5 = zext(Rd0811) + ~zext(Rd1215) + 1;\n\t$(PSW_C) = tmp[32,1];\n\toverflowflags(Rd2831);\n}\n\n# SVLCX (SYS)\n:svlcx is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x200\n{\n\t#TODO context\n\t# if (FCX == 0) trap(FCU);\n\t# tmp_FCX = FCX;\n\t# EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};\n\t# new_FCX = M(EA, word);\n\t# M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4], A[5], A[6], A[7], D[4], D[5], D[6], D[7]};\n\t# PCXI.PCPN = ICR.CCPN\n\t# PCXI.PIE = ICR.IE;\n\t# PCXI.UL = 0;\n\t# PCXI[19:0] = FCX[19:0];\n\t# FCX[19:0] = new_FCX[19:0];\n\t# if (tmp_FCX == LCX) trap(FCD);\n}\n\n# SWAP.W A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)\n# SWAP.W P[b], D[a] (BO)(Bit-reverse Addressing Mode)\n# SWAP.W A[b], off10, D[a] (BO)(Pre-increment Addressing Mode)\n# SWAP.W A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)\n# SWAP.W P[b], D[a] (BO)(Index Addressing Mode)\n:swap.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x1 ; op2225=0x0 ) & BO\n{\n\tbuild BO;\n\tlocal tmp:4 = *[ram]:4 BO;\n\t*[ram]:4 BO = Rd0811;\n\tRd0811 = tmp;\n}\n\n# SWAP.W off18, D[a] (ABS)(Absolute Addressing Mode)\n:swap.w off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xe5 ; op2627=0x0 ) & off18\n{\n\tlocal tmp:4 = *[ram]:4 off18;\n\t*[ram]:4 off18 = Rd0811;\n\tRd0811 = tmp;\n}\n\n# SWAP.W P[b], off10, D[a] (BO)(Circular Addressing Mode)\n#:swap.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x69 ; op2227=0x10 ) & BO\n:swap.w [Rpe1215/Rpo1215^\"+c\"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x10\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tlocal tmp:4 = *[ram]:4 EA;\n\t*[ram]:4 EA = Rd0811;\n\tRd0811 = tmp;\n}\n\n@if defined(TRICORE_V2)\n# SWAPMSK.W A[b], off10, E[a] (BO)(Post-increment Addressing Mode)\n# SWAPMSK.W P[b], E[a] (BO)(Bit-reverse Addressing Mode)\n# SWAPMSK.W A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)\n# SWAPMSK.W A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)\n# SWAPMSK.W P[b], E[a] (BO)(Index Addressing Mode)\n:swapmsk.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0607=0x1 ; op2225=0x2 ) & BO\n{\n\tbuild BO;\n\tlocal tmp:4 = *[ram]:4 BO;\n\t*[ram]:4 BO = (tmp & ~Reo0811) | (Ree0811 & Reo0811);\n}\n\n# SWAPMSK.W P[b], off10, E[a] (BO)(Circular Addressing Mode)\n#:swapmsk.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0x69 ; op2227=0x12 ) & BO\n:swapmsk.w [Rpe1215/Rpo1215^\"+c\"^]off10,Ree0811/Reo0811 is PCPMode=0 & Ree0811 & Reo0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x12\n{\n\tlocal EA:4;\n\tCircularAddressingMode(Rpe1215, Rpo1215, EA, off10);\n\tlocal tmp:4 = *[ram]:4 EA;\n\t*[ram]:4 EA = (tmp & ~Reo0811) | (Ree0811 & Reo0811);\n}\n@endif\n\n# SYSCALL const9 (RC)\n:syscall const1220Z is PCPMode=0 & ( op0007=0xad & op0811=0x0 ; op2131=0x4 ) & const1220Z\n{\n\t#TODO TIN SYS\n\ttrap(const1220Z[0,8]);\n}\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:tlbdemap Rd0811 is PCPMode=0 & Rd0811 & op0007=0x75 & op1215=0x0 ; op1631=0x0\n{\n\ttlbdemap(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:tlbflush.a is PCPMode=0 & op0007=0x75 & op0815=0x0 ; op1631=0x40\n{\n\ttlbflusha();\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:tlbflush.b is PCPMode=0 & op0007=0x75 & op0815=0x0 ; op1631=0x50\n{\n\ttlbflushb();\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:tlbmap Re0811 is PCPMode=0 & Re0811 & op0007=0x75 & op1215=0x0 ; op1631=0x400\n{\n\ttlbmap(Re0811);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:tlbprobe.a Rd0811 is PCPMode=0 & Rd0811 & op0007=0x75 & op1215=0x0 ; op1631=0x80\n{\n\ttlbprobea(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n:tlbprobe.i Rd0811 is PCPMode=0 & Rd0811 & op0007=0x75 & op1215=0x0 ; op1631=0x90\n{\n\ttlbprobei(Rd0811);\n}\n@endif\n\n# TRAPSV (SYS)\n:trapsv is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x540\n{\n\t#TODO TIN SOVF\n\tif ($(PSW_SV) == 0) goto inst_next;\n\ttrap();\n}\n\n# TRAPV (SYS)\n:trapv is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x500\n{\n\t#TODO TIN OVF\n\tif ($(PSW_V) == 0) goto inst_next;\n\ttrap();\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# UNPACK E[c], D[a] (RR)\n:unpack Re2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Re2831 & op1627=0x80\n{\n\t#TODO\n\t#TODO float En+1 = exp and En = mantissa\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# UPDFL D[a] (RR)\n:updfl Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; op1631=0xc1\n{\n\t$(PSW_FS) = ($(PSW_FS) & ~Rd0811[15,1]) | (Rd0811[7,1] & Rd0811[15,1]);\n\t$(PSW_FI) = ($(PSW_FI) & ~Rd0811[14,1]) | (Rd0811[6,1] & Rd0811[14,1]);\n\t$(PSW_FV) = ($(PSW_FV) & ~Rd0811[13,1]) | (Rd0811[5,1] & Rd0811[13,1]);\n\t$(PSW_FZ) = ($(PSW_FZ) & ~Rd0811[12,1]) | (Rd0811[4,1] & Rd0811[12,1]);\n\t$(PSW_FU) = ($(PSW_FU) & ~Rd0811[11,1]) | (Rd0811[3,1] & Rd0811[11,1]);\n\t$(PSW_FX) = ($(PSW_FX) & ~Rd0811[10,1]) | (Rd0811[2,1] & Rd0811[10,1]);\n\t$(PSW_RM) = ($(PSW_RM) & ~Rd0811[8,2]) | (Rd0811[0,2] & Rd0811[8,2]);\n}\n@endif\n\n@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# UTOF D[c], D[a] (RR)\n:utof Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x161\n{\n\t#TODO float\n\t#TODO flags\n\t#TODO unsigned\n\t# Rd2831 = int2float(Rd0811);\n}\n@endif\n\n@if defined(TRICORE_V2)\n# WAIT (SYS)\n:wait is PCPMode=0 & op0007=0xd & op0815=0 ; op1621=0 & op2227=0x16 & op2831=0\n{\n\twait();\n}\n@endif\n\n# XNOR D[c], D[a], D[b] (RR)\n:xnor Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xd0\n{\n\tRd2831 = ~(Rd0811 ^ Rd1215);\n}\n\n# XNOR D[c], D[a], const9 (RC)\n:xnor Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xd ) & const1220Z\n{\n\tRd2831 = ~(Rd0811 ^ const1220Z);\n}\n\n# XNOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:xnor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x2\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831 = zext(!(tmpa[0,1] ^ tmpb[0,1]));\n}\n\n@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)\n# XOR D[a], D[b] (SRR)\n:xor Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc6\n{\n\tRd0811 = Rd0811 ^ Rd1215;\n}\n@endif\n\n# XOR D[c], D[a], D[b] (RR)\n:xor Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xc0\n{\n\tRd2831 = Rd0811 ^ Rd1215;\n}\n\n# XOR D[c], D[a], const9 (RC)\n:xor Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xc ) & const1220Z\n{\n\tRd2831 = Rd0811 ^ const1220Z;\n}\n\n# XOR.EQ D[c], D[a], D[b] (RR)\n:xor.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2f0\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 == Rd1215);\n}\n\n# XOR.EQ D[c], D[a], const9 (RC)\n:xor.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2f ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 == const1220S);\n}\n\n# XOR.GE D[c], D[a], D[b] (RR)\n:xor.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x330\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s>= Rd1215);\n}\n\n# XOR.GE D[c], D[a], const9 (RC)\n:xor.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x33 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s>= const1220S);\n}\n\n# XOR.GE.U D[c], D[a], D[b] (RR)\n:xor.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x340\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 >= Rd1215);\n}\n\n# XOR.GE.U D[c], D[a], const9 (RC)\n:xor.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x34 ) & const1220Z\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 >= const1220Z);\n}\n\n# XOR.LT D[c], D[a], D[b] (RR)\n:xor.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x310\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s< Rd1215);\n}\n\n# XOR.LT D[c], D[a], const9 (RC)\n:xor.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x31 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s< const1220S);\n}\n\n# XOR.LT.U D[c], D[a], D[b] (RR)\n:xor.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x320\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 < Rd1215);\n}\n\n# XOR.LT.U D[c], D[a], const9 (RC)\n:xor.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x32 ) & const1220Z\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 < const1220Z);\n}\n\n# XOR.NE D[c], D[a], D[b] (RR)\n:xor.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x300\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 != Rd1215);\n}\n\n# XOR.NE D[c], D[a], const9 (RC)\n:xor.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x30 ) & const1220S\n{\n\tRd2831[0,1] = Rd2831[0,1] ^ (Rd0811 != const1220S);\n}\n\n# XOR.T D[c], D[a], pos1, D[b], pos2 (BIT)\n:xor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x3\n{\n\tlocal tmpa = (Rd0811 >> const1620Z) & 1;\n\tlocal tmpb = (Rd1215 >> const2327Z) & 1;\n\tRd2831 = zext(tmpa[0,1] ^ tmpb[0,1]);\n}\n\n@if defined(TRICORE_V2)\n:xpose.b Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Re2831 & op1627=0x830\n{\n\tRe2831 = zext(Rd0811[24,8] << 56)|zext(Rd1215[24,8] << 48)|zext(Rd0811[8,8] << 40)|zext(Rd1215[8,8] << 32)|zext(Rd0811[16,8] << 24)|zext(Rd1215[16,8] << 16)|zext(Rd0811[0,8] << 8)|zext(Rd1215[0,8]);\n}\n@endif\n\n@if defined(TRICORE_V2)\n:xpose.h Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Re2831 & op1627=0x820\n{\n\tRe2831 = zext(Rd0811[16,16] << 48)|zext(Rd1215[16,16] << 32)|zext(Rd0811[0,16] << 16)|zext(Rd1215[0,16]);\n}\n@endif\n\n# @if defined(TRICORE_V2)\n# :yield\n# {\n# }\n# @endif\n\n\n@include \"tricore.pcp.sinc\"\n" }, { "path": "pypcode/processors/tricore/data/languages/tricore.slaspec", "content": "@define Tricore \"\"\n\n@define TRICORE_GENERIC \"\"\n#@define TRICORE_RIDER_D \"\"\n#@define TRICORE_RIDER_B \"\"\n\n@define TRICORE_V2 \"\"\n\n#@define TRICORE_VERBOSE \"\"\n\ndefine endian=little;\n\n@include \"tricore.sinc\"\n" }, { "path": "pypcode/processors/tricore/data/manuals/tricore.idx", "content": "@tc_v131_instructionset_v138.pdf[TriCore Architecture Volume 2: Instruction Set, V1.3 & V1.3.1]\nABS, 66\nABS.B, 67\nABSDIF, 69\nABSDIF.B, 71\nABSDIF.H, 71\nABSDIFS, 73\nABSDIFS.H, 75\nABS.H, 67\nABSS, 76\nABSS.H, 77\nADD, 78\nADD.A, 81\nADD.B, 83\nADDC, 85\nADD.F, 511\nADD.H, 83\nADDI, 87\nADDIH, 88\nADDIH.A, 89\nADDS, 90\nADDSC.A, 96\nADDSC.AT, 96\nADDS.H, 92\nADDS.HU, 92\nADDS.U, 94\nADDX, 98\nAND, 100\nAND.ANDN.T, 102\nAND.AND.T, 102\nAND.EQ, 104\nAND.GE, 105\nAND.GE.U, 105\nAND.LT, 107\nAND.LT.U, 107\nANDN, 111\nAND.NE, 109\nAND.NOR.T, 102\nANDN.T, 112\nAND.OR.T, 102\nAND.T, 110\nBISR, 113\nBMERGE, 115\nBSPLIT, 116\nCACHEA.I, 117\nCACHEA.W, 120\nCACHEA.WI, 123\nCACHEI.W, 126\nCACHEI.WI, 128\nCADD, 130\nCADDN, 132\nCALL, 134\nCALLA, 137\nCALLI, 139\nCLO, 141\nCLO.H, 142\nCLS, 143\nCLS.H, 144\nCLZ, 145\nCLZ.H, 146\nCMOV, 147\nCMOVN, 148\nCMP.F, 513\nCSUB, 149\nCSUBN, 150\nDEBUG, 151\nDEXTR, 152\nDISABLE, 153\nDIV.F, 515\nDSYNC, 154\nDVADJ, 155\nDVINIT, 157\nDVINIT.B, 157\nDVINIT.BU, 157\nDVINIT.H, 157\nDVINIT.HU, 157\nDVINIT.U, 157\nDVSTEP, 162\nDVSTEP.U, 162\nENABLE, 165\nEQ, 166\nEQ.A, 168\nEQANY.B, 171\nEQANY.H, 171\nEQ.B, 169\nEQ.H, 169\nEQ.W, 169\nEQZ.A, 173\nEXTR, 174\nEXTR.U, 174\nFTOI, 517\nFTOIZ, 518\nFTOQ31, 519\nFTOQ31Z, 521\nFTOU, 523\nFTOUZ, 524\nGE, 176\nGE.A, 178\nGE.U, 176\nIMASK, 179\nINSERT, 182\nINSN.T, 181\nINS.T, 181\nISYNC, 185\nITOF, 525\nIXMAX, 186\nIXMAX.U, 186\nIXMIN, 188\nIXMIN.U, 188\nJ, 190\nJA, 191\nJEQ, 192\nJEQ.A, 194\nJGE, 195\nJGE.U, 195\nJGEZ, 197\nJGTZ, 198\nJI, 199\nJL, 200\nJLA, 201\nJLEZ, 202\nJLI, 203\nJLT, 204\nJLT.U, 204\nJLTZ, 206\nJNE, 207\nJNE.A, 209\nJNED, 210\nJNEI, 212\nJNZ, 214\nJNZ.A, 215\nJNZ.T, 216\nJZ, 217\nJZ.A, 218\nJZ.T, 219\nLD.A, 220\nLD.B, 224\nLD.BU, 224\nLD.D, 229\nLD.DA, 232\nLD.H, 235\nLD.HU, 238\nLDLCX, 246\nLDMST, 247\nLD.Q, 240\nLDUCX, 250\nLD.W, 242\nLEA, 251\nLOOP, 253\nLOOPU, 255\nLT, 256\nLT.A, 259\nLT.B, 260\nLT.BU, 260\nLT.H, 262\nLT.HU, 262\nLT.U, 256\nLT.W, 264\nLT.WU, 264\nMADD, 265\nMADD.F, 526\nMADD.H, 268\nMADDM.H, 282\nMADDMS.H, 282\nMADD.Q, 272\nMADDR.H, 286\nMADDR.Q, 291\nMADDRS.H, 286\nMADDRS.Q, 291\nMADDS, 265\nMADDS.H, 268\nMADDS.Q, 272\nMADDS.U, 279\nMADDSU.H, 293\nMADDSUM.H, 297\nMADDSUMS.H, 297\nMADDSUR.H, 301\nMADDSURS.H, 301\nMADDSUS.H, 293\nMADD.U, 279\nMAX, 306\nMAX.B, 308\nMAX.BU, 308\nMAX.H, 310\nMAX.HU, 310\nMAX.U, 306\nMFCR, 311\nMIN, 312\nMIN.B, 314\nMIN.BU, 314\nMIN.H, 316\nMIN.HU, 316\nMIN.U, 312\nMOV, 317\nMOV.A, 319\nMOV.AA, 321\nMOV.D, 322\nMOVH, 324\nMOVH.A, 325\nMOV.U, 323\nMSUB, 326\nMSUBAD.H, 343\nMSUBADM.H, 347\nMSUBADMS.H, 347\nMSUBADR.H, 351\nMSUBADRS.H, 351\nMSUBADS.H, 343\nMSUB.F, 528\nMSUB.H, 329\nMSUBM.H, 356\nMSUBMS.H, 356\nMSUB.Q, 333\nMSUBR.H, 360\nMSUBR.Q, 365\nMSUBRS.H, 360\nMSUBRS.Q, 365\nMSUBS, 326\nMSUBS.H, 329\nMSUBS.Q, 333\nMSUBS.U, 340\nMSUB.U, 340\nMTCR, 367\nMUL, 368\nMUL.F, 530\nMUL.H, 371\nMULM.H, 379\nMUL.Q, 374\nMULR.H, 382\nMULR.Q, 385\nMULS, 368\nMULS.U, 377\nMUL.U, 377\nNAND, 387\nNAND.T, 388\nNE, 389\nNE.A, 390\nNEZ.A, 391\nNOP, 392\nNOR, 393\nNOR.T, 394\nNOT, 395\nOR, 396\nOR.ANDN.T, 398\nOR.AND.T, 398\nOR.EQ, 400\nOR.GE, 401\nOR.GE.U, 401\nOR.LT, 403\nOR.LT.U, 403\nORN, 407\nOR.NE, 405\nOR.NOR.T, 398\nORN.T, 408\nOR.OR.T, 398\nOR.T, 406\nPACK, 409\nPARITY, 412\nQ31TOF, 532\nQSEED.F, 533\nRET, 413\nRFE, 415\nRFM, 417\nRSLCX, 419\nRSTV, 420\nRSUB, 421\nRSUBS, 423\nRSUBS.U, 423\nSAT.B, 425\nSAT.BU, 427\nSAT.H, 428\nSAT.HU, 430\nSEL, 431\nSELN, 432\nSH, 433\nSHA, 446\nSHA.H, 449\nSH.ANDN.T, 443\nSH.AND.T, 443\nSHAS, 451\nSH.EQ, 435\nSH.GE, 436\nSH.GE.U, 436\nSH.H, 438\nSH.LT, 440\nSH.LT.U, 440\nSH.NAND.T, 443\nSH.NE, 442\nSH.NOR.T, 443\nSH.ORN.T, 443\nSH.OR.T, 443\nSH.XNOR.T, 443\nSH.XOR.T, 443\nST.A, 453\nST.B, 457\nST.D, 460\nST.DA, 463\nST.H, 466\nSTLCX, 476\nST.Q, 469\nST.T, 471\nSTUCX, 477\nST.W, 472\nSUB, 478\nSUB.A, 480\nSUB.B, 481\nSUBC, 483\nSUB.F, 535\nSUB.H, 481\nSUBS, 484\nSUBS.H, 486\nSUBS.HU, 486\nSUBS.U, 484\nSUBX, 488\nSVLCX, 489\nSWAP.W, 491\nSYSCALL, 494\nTLBDEMAP, 541\nTLBFLUSH.A, 542\nTLBFLUSH.B, 542\nTLBMAP, 544\nTLBPROBE.A, 546\nTLBPROBE.I, 548\nTRAPSV, 495\nTRAPV, 496\nUNPACK, 497\nUPDFL, 537\nUTOF, 539\nXNOR, 499\nXNOR.T, 500\nXOR, 501\nXOR.EQ, 503\nXOR.GE, 504\nXOR.GE.U, 504\nXOR.LT, 506\nXOR.LT.U, 506\nXOR.NE, 508\nXOR.T, 509\n" }, { "path": "pypcode/processors/tricore/data/manuals/tricore2.idx", "content": "@Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf [TriCore TC1.6P & TC1.6E Instruction Set, User Manual (Volume 2), V1.0 2013-07]\nABS, 49\nABS.B, 50\nABS.H, 50\nABSDIF, 52\nABSDIF.B, 53\nABSDIF.H, 53\nABSDIFS, 55\nABSDIFS.H, 56\nABSS, 57\nABSS.H, 58\nADD, 59\nADD.A, 62\nADD.B, 63\nADD.F, 447\nADD.H, 63\nADDC, 65\nADDI, 66\nADDIH, 67\nADDIH.A, 68\nADDS, 69\nADDS.H, 71\nADDS.HU, 71\nADDS.U, 73\nADDSC.A, 74\nADDSC.AT, 74\nADDX, 76\nAND, 77\nAND.AND.T, 79\nAND.ANDN.T, 79\nAND.EQ, 81\nAND.GE, 82\nAND.GE.U, 82\nAND.LT, 84\nAND.LT.U, 84\nAND.NE, 86\nAND.NOR.T, 79\nAND.OR.T, 79\nAND.T, 87\nANDN, 88\nANDN.T, 89\nBISR, 90\nBMERGE, 92\nBSPLIT, 93\nCACHEA.I, 94\nCACHEA.W, 96\nCACHEA.WI, 98\nCACHEI.I, 102\nCACHEI.W, 100\nCACHEI.WI, 104\nCADD, 106\nCADDN, 108\nCALL, 110\nCALLA, 112\nCALLI, 113\nCLO, 115\nCLO.H, 116\nCLS, 117\nCLS.H, 118\nCLZ, 119\nCLZ.H, 120\nCMOV, 121\nCMOVN, 122\nCMP.F, 448\nCMPSWAP.W, 123\n# COP, \nCRC32, 125\nCSUB, 126\nCSUBN, 127\nDEBUG, 128\nDEXTR, 129\nDISABLE, 130\nDIV, 134\nDIV.F, 449\nDIV.U, 134\nDSYNC, 131\nDVADJ, 132\nDVINIT, 136\nDVINIT.B, 136\nDVINIT.BU, 136\nDVINIT.H, 136\nDVINIT.HU, 136\nDVINIT.U, 136\nDVSTEP, 139\nDVSTEP.U, 139\nENABLE, 141\nEQ, 142\nEQ.A, 144\nEQ.B, 145\nEQ.H, 145\nEQ.W, 145\nEQANY.B, 147\nEQANY.H, 147\nEQZ.A, 149\nEXTR, 150\nEXTR.U, 150\nFCALL, 152\nFCALLA, 153\nFCALLI, 154\nFRET, 155\nFTOI, 450\nFTOIZ, 451\nFTOQ31, 452\nFTOQ31Z, 453\nFTOU, 454\nFTOUZ, 455\nGE, 156\nGE.A, 158\nGE.U, 156\nIMASK, 159\nINS.T, 161\nINSERT, 162\nINSN.T, 161\nISYNC, 164\nITOF, 456\nIXMAX, 165\nIXMAX.U, 165\nIXMIN, 167\nIXMIN.U, 167\nJ, 169\nJA, 170\nJEQ, 171\nJEQ.A, 173\nJGE, 174\nJGE.U, 174\nJGEZ, 176\nJGTZ, 177\nJI, 178\nJL, 179\nJLA, 180\nJLEZ, 181\nJLI, 182\nJLT, 183\nJLT.U, 183\nJLTZ, 185\nJNE, 186\nJNE.A, 188\nJNED, 189\nJNEI, 190\nJNZ, 191\nJNZ.A, 192\nJNZ.T, 193\nJZ, 194\nJZ.A, 195\nJZ.T, 196\nLD.A, 197\nLD.B, 200\nLD.BU, 200\nLD.D, 204\nLD.DA, 206\n# LD.DD, \nLD.H, 208\nLD.HU, 208\nLD.Q, 212\nLD.W, 214\nLDLCX, 217\nLDMST, 218\nLDUCX, 220\nLEA, 221\nLOOP, 222\nLOOPU, 223\nLT, 224\nLT.A, 226\nLT.B, 227\nLT.BU, 227\nLT.H, 228\nLT.HU, 228\nLT.U, 224\nLT.W, 229\nLT.WU, 229\nMADD, 230\nMADD.F, 457\nMADD.H, 233\nMADD.Q, 237\nMADD.U, 243\nMADDM.H, 245\nMADDMS.H, 245\nMADDR.H, 248\nMADDR.Q, 252\nMADDRS.H, 248\nMADDRS.Q, 252\nMADDS, 230\nMADDS.H, 233\nMADDS.Q, 237\nMADDS.U, 243\nMADDSU.H, 254\nMADDSUM.H, 258\nMADDSUMS.H, 258\nMADDSUR.H, 261\nMADDSURS.H, 261\nMADDSUS.H, 254\nMAX, 265\nMAX.B, 267\nMAX.BU, 267\nMAX.H, 268\nMAX.HU, 268\nMAX.U, 265\nMFCR, 269\n# MFFR, \nMIN, 270\nMIN.B, 272\nMIN.BU, 272\nMIN.H, 273\nMIN.HU, 273\nMIN.U, 270\nMOV, 274\nMOV.A, 277\nMOV.AA, 278\nMOV.D, 279\nMOV.U, 280\nMOVH, 281\nMOVH.A, 282\nMSUB, 283\nMSUB.F, 459\nMSUB.H, 286\nMSUB.Q, 290\nMSUB.U, 296\nMSUBAD.H, 298\nMSUBADM.H, 302\nMSUBADMS.H, 302\nMSUBADR.H, 305\nMSUBADRS.H, 305\nMSUBADS.H, 298\nMSUBM.H, 309\nMSUBMS.H, 309\nMSUBR.H, 312\nMSUBR.Q, 316\nMSUBRS.H, 312\nMSUBRS.Q, 316\nMSUBS, 283\nMSUBS.H, 286\nMSUBS.Q, 290\nMSUBS.U, 296\nMTCR, 318\n# MTFR, \nMUL, 319\nMUL.F, 461\nMUL.H, 322\nMUL.Q, 324\nMUL.U, 327\nMULM.H, 329\nMULMS.H, 331\nMULR.H, 332\nMULR.Q, 334\nMULS, 319\nMULS.U, 327\nNAND, 335\nNAND.T, 336\nNE, 337\nNE.A, 338\nNEZ.A, 339\nNOP, 340\nNOR, 341\nNOR.T, 342\nNOT, 343\nOR, 344\nOR.AND.T, 346\nOR.ANDN.T, 346\nOR.EQ, 348\nOR.GE, 349\nOR.GE.U, 349\nOR.LT, 351\nOR.LT.U, 351\nOR.NE, 353\nOR.NOR.T, 346\nOR.OR.T, 346\nOR.T, 354\nORN, 355\nORN.T, 356\nPACK, 357\nPARITY, 359\nQ31TOF, 462\nQSEED.F, 463\nRESTORE, 360\nRET, 361\nRFE, 363\nRFM, 365\nRSLCX, 366\nRSTV, 367\nRSUB, 368\nRSUBS, 369\nRSUBS.U, 369\nSAT.B, 370\nSAT.BU, 371\nSAT.H, 372\nSAT.HU, 373\nSEL, 374\nSELN, 375\nSH, 376\nSH.AND.T, 385\nSH.ANDN.T, 385\nSH.EQ, 378\nSH.GE, 379\nSH.GE.U, 379\nSH.H, 381\nSH.LT, 382\nSH.LT.U, 382\nSH.NAND.T, 385\nSH.NE, 384\nSH.NOR.T, 385\nSH.OR.T, 385\nSH.ORN.T, 385\nSH.XNOR.T, 385\nSH.XOR.T, 385\nSHA, 387\nSHA.H, 389\nSHAS, 391\nST.A, 393\nST.B, 396\nST.D, 399\nST.DA, 401\n# ST.DD, \nST.H, 403\nST.Q, 406\nST.T, 408\nST.W, 409\nSTLCX, 412\nSTUCX, 413\nSUB, 414\nSUB.A, 416\nSUB.B, 417\nSUB.F, 464\nSUB.H, 417\nSUBC, 419\nSUBS, 420\nSUBS.H, 422\nSUBS.HU, 422\nSUBS.U, 420\nSUBX, 424\nSVLCX, 425\nSWAP.W, 426\nSWAPMSK.W, 428\nSYSCALL, 430\n# TLBDEMAP, \n# TLBFLUSH.A, \n# TLBFLUSH.B, \n# TLBMAP, \n# TLBPROBE.A, \n# TLBPROBE.I, \nTRAPSV, 431\nTRAPV, 432\nUNPACK, 433\nUPDFL, 465\nUTOF, 466\nWAIT, 435\nXNOR, 436\nXNOR.T, 437\nXOR, 438\nXOR.EQ, 439\nXOR.GE, 440\nXOR.GE.U, 440\nXOR.LT, 442\nXOR.LT.U, 442\nXOR.NE, 444\nXOR.T, 445\n# XPOSE.B, \n# XPOSE.H, \n# YIELD, \n" }, { "path": "pypcode/processors/tricore/data/patterns/patternconstraints.xml", "content": "\n \n tricore_patterns.xml\n \n\n" }, { "path": "pypcode/processors/tricore/data/patterns/tricore_patterns.xml", "content": "\n \n \n 00000000 10010000 >\n 10011101 ........ ........ ........ >\n 00011101 ........ ........ ........ >\n 11011100 00001011 >\n 00101101 00001011 00000000 00110000 >\n 00111100 ........ >\n \n \n 00000010 ........ >\n 00000101 ....1111 ........ ....01.. >\n 00001100 ........ >\n 00111011 ....0000 ........ 1111.... >\n 00111011 ....0000 ........ 0100.... >\n 00111011 ....0000 ........ 1000.... >\n 10000010 ....1111 >\n 10000010 ....0100 >\n 10000010 ....1000 >\n 01111101 ....0000 ........ 1111.... >\n 10010001 ....0000 ........ 1111.... >\n 01111101 ....0000 ........ 0100.... >\n 01111101 ....0000 ........ 1000.... >\n 11011010 ........ >\n 00011101 ........ ........ ........ >\n 10000101 ....1111 ........ ....00.. >\n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/unix32/cc.xml", "content": "\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/unix32/probe_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/unix32/try_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/unix64/cc.xml", "content": "\n \n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n\t\n \n \n \n \n \n\t\n\t \n\t\n\t\n\t \n\t\n\t\n\t \n\t\n \n \n\t\n\t\n\t\n \n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/unix64/probe_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/unix64/try_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/windows32/probe_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/windows32/try_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/windows64/probe_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/extensions/rust/windows64/try_fixup.xml", "content": "\n \n \n\t\n \n\n" }, { "path": "pypcode/processors/x86/data/languages/adx.sinc", "content": ":ADCX Reg32, rm32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... {\n\ttmp:5 = zext(Reg32) + zext(rm32) + zext(CF);\n\ttmpCF:1 = tmp(4); # just the carry byte \n\tCF = tmpCF != 0;\n\tReg32 = tmp:4;\n\tbuild check_Reg32_dest;\n}\n\n@ifdef IA64\n:ADCX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 {\n\ttmp:9 = zext(Reg64) + zext(rm64) + zext(CF);\n\ttmpCF:1 = tmp(8); # just the carry byte \n\tCF = tmpCF != 0;\n\tReg64 = tmp:8;\n}\n@endif\n\n:ADOX Reg32, rm32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... {\n\ttmp:5 = zext(Reg32) + zext(rm32) + zext(OF);\n\ttmpOF:1 = tmp(4); # just the carry byte \n\tOF = tmpOF != 0;\n\tReg32 = tmp:4;\n\tbuild check_Reg32_dest;\n}\n\n@ifdef IA64\n:ADOX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 {\n\ttmp:9 = zext(Reg64) + zext(rm64) + zext(OF);\n\ttmpOF:1 = tmp(8); # just the carry byte \n\tOF = tmpOF != 0;\n\tReg64 = tmp:8;\n}\n@endif\n" }, { "path": "pypcode/processors/x86/data/languages/avx.sinc", "content": "# INFO This file automatically generated by andre on Tue Apr 30 15:35:00 2024\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx_manual.sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/ia.sinc']\n\n# ADDPD 3-33 PAGE 603 LINE 33405\n:VADDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal m:16 = XmmReg2_m128;\n\tXmmReg1[0,64] = vexVVVV_XmmReg[0,64] f+ m[0,64];\n XmmReg1[64,64] = vexVVVV_XmmReg[64,64] f+ m[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# ADDPD 3-33 PAGE 603 LINE 33408\n:VADDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal m:32 = YmmReg2_m256;\n\tYmmReg1[0,64] = vexVVVV_YmmReg[0,64] f+ m[0,64];\n YmmReg1[64,64] = vexVVVV_YmmReg[64,64] f+ m[64,64];\n YmmReg1[128,64] = vexVVVV_YmmReg[128,64] f+ m[128,64];\n YmmReg1[192,64] = vexVVVV_YmmReg[192,64] f+ m[192,64];\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# ADDPS 3-36 PAGE 606 LINE 33558\n:VADDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = XmmReg2_m128;\n\tXmmReg1[0,32] = vexVVVV_XmmReg[0,32] f+ tmp[0,32];\n XmmReg1[32,32] = vexVVVV_XmmReg[32,32] f+ tmp[32,32];\n XmmReg1[64,32] = vexVVVV_XmmReg[64,32] f+ tmp[64,32];\n XmmReg1[96,32] = vexVVVV_XmmReg[96,32] f+ tmp[96,32];\n ZmmReg1 = zext(XmmReg1);\n}\n\n\n# ADDPS 3-36 PAGE 606 LINE 33560\n:VADDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = YmmReg2_m256;\n\tYmmReg1[0,32] = vexVVVV_YmmReg[0,32] f+ tmp[0,32];\n YmmReg1[32,32] = vexVVVV_YmmReg[32,32] f+ tmp[32,32];\n YmmReg1[64,32] = vexVVVV_YmmReg[64,32] f+ tmp[64,32];\n YmmReg1[96,32] = vexVVVV_YmmReg[96,32] f+ tmp[96,32];\n YmmReg1[128,32] = vexVVVV_YmmReg[128,32] f+ tmp[128,32];\n YmmReg1[160,32] = vexVVVV_YmmReg[160,32] f+ tmp[160,32];\n YmmReg1[192,32] = vexVVVV_YmmReg[192,32] f+ tmp[192,32];\n YmmReg1[224,32] = vexVVVV_YmmReg[224,32] f+ tmp[224,32];\n \n\tZmmReg1 = zext(YmmReg1);\n}\n\n# ADDSD 3-39 PAGE 609 LINE 33718\n:VADDSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:8 = vexVVVV_XmmReg[0,64] f+ XmmReg2_m64[0,64];\n\tZmmReg1 = zext(tmp);\n}\n\n# ADDSS 3-41 PAGE 611 LINE 33812\n:VADDSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:4 = vexVVVV_XmmReg[0,32] f+ XmmReg2_m32[0,32];\n\tZmmReg1 = zext(tmp);\n}\n\n# ADDSUBPD 3-43 PAGE 613 LINE 33906\ndefine pcodeop vaddsubpd_avx ;\n:VADDSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vaddsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ADDSUBPD 3-43 PAGE 613 LINE 33909\n:VADDSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vaddsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ADDSUBPS 3-45 PAGE 615 LINE 34013\ndefine pcodeop vaddsubps_avx ;\n:VADDSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vaddsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ADDSUBPS 3-45 PAGE 615 LINE 34016\n:VADDSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vaddsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDPD 3-64 PAGE 634 LINE 34821\ndefine pcodeop vandpd_avx ;\n:VANDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vandpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDPD 3-64 PAGE 634 LINE 34824\n:VANDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vandpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDPS 3-67 PAGE 637 LINE 34947\ndefine pcodeop vandps_avx ;\n:VANDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vandps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDPS 3-67 PAGE 637 LINE 34950\n:VANDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vandps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDNPD 3-70 PAGE 640 LINE 35081\ndefine pcodeop vandnpd_avx ;\n:VANDNPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vandnpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDNPD 3-70 PAGE 640 LINE 35084\n:VANDNPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vandnpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDNPS 3-73 PAGE 643 LINE 35207\ndefine pcodeop vandnps_avx ;\n:VANDNPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vandnps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ANDNPS 3-73 PAGE 643 LINE 35210\n:VANDNPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vandnps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDPD 3-78 PAGE 648 LINE 35433\ndefine pcodeop vblendpd_avx ;\n:VBLENDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8_3_0 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8_3_0\n{\n\tlocal tmp:16 = vblendpd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8_3_0:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDPD 3-78 PAGE 648 LINE 35436\n:VBLENDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8_3_0 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8_3_0\n{\n\tlocal tmp:32 = vblendpd_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8_3_0:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDPS 3-81 PAGE 651 LINE 35580\ndefine pcodeop vblendps_avx ;\n:VBLENDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vblendps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDPS 3-81 PAGE 651 LINE 35583\n:VBLENDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vblendps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDVPD 3-83 PAGE 653 LINE 35684\ndefine pcodeop vblendvpd_avx ;\n:VBLENDVPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4\n{\n\tlocal tmp:16 = vblendvpd_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDVPD 3-83 PAGE 653 LINE 35688\n:VBLENDVPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; Ymm_imm8_7_4\n{\n\tlocal tmp:32 = vblendvpd_avx( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDVPS 3-85 PAGE 655 LINE 35789\ndefine pcodeop vblendvps_avx ;\n:VBLENDVPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4\n{\n\tlocal tmp:16 = vblendvps_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 );\n\tZmmReg1 = zext(tmp);\n}\n\n# BLENDVPS 3-85 PAGE 655 LINE 35793\n:VBLENDVPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; Ymm_imm8_7_4\n{\n\tlocal tmp:32 = vblendvps_avx( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CMPPD 3-155 PAGE 725 LINE 39240\nVCMPPD_mon: \"VCMPEQPD\" is imm8=0x0 { }\nVCMPPD_op: \"\" is imm8=0x0 { export 0x0:1; }\nVCMPPD_mon: \"VCMPLTPD\" is imm8=0x1 { }\nVCMPPD_op: \"\" is imm8=0x1 { export 0x1:1; }\nVCMPPD_mon: \"VCMPLEPD\" is imm8=0x2 { }\nVCMPPD_op: \"\" is imm8=0x2 { export 0x2:1; }\nVCMPPD_mon: \"VCMPUNORDPD\" is imm8=0x3 { }\nVCMPPD_op: \"\" is imm8=0x3 { export 0x3:1; }\nVCMPPD_mon: \"VCMPNEQPD\" is imm8=0x4 { }\nVCMPPD_op: \"\" is imm8=0x4 { export 0x4:1; }\nVCMPPD_mon: \"VCMPNLTPD\" is imm8=0x5 { }\nVCMPPD_op: \"\" is imm8=0x5 { export 0x5:1; }\nVCMPPD_mon: \"VCMPNLEPD\" is imm8=0x6 { }\nVCMPPD_op: \"\" is imm8=0x6 { export 0x6:1; }\nVCMPPD_mon: \"VCMPORDPD\" is imm8=0x7 { }\nVCMPPD_op: \"\" is imm8=0x7 { export 0x7:1; }\nVCMPPD_mon: \"VCMPEQ_UQPD\" is imm8=0x8 { }\nVCMPPD_op: \"\" is imm8=0x8 { export 0x8:1; }\nVCMPPD_mon: \"VCMPNGEPD\" is imm8=0x9 { }\nVCMPPD_op: \"\" is imm8=0x9 { export 0x9:1; }\nVCMPPD_mon: \"VCMPNGTPD\" is imm8=0xa { }\nVCMPPD_op: \"\" is imm8=0xa { export 0xa:1; }\nVCMPPD_mon: \"VCMPFALSEPD\" is imm8=0xb { }\nVCMPPD_op: \"\" is imm8=0xb { export 0xb:1; }\nVCMPPD_mon: \"VCMPNEQ_OQPD\" is imm8=0xc { }\nVCMPPD_op: \"\" is imm8=0xc { export 0xc:1; }\nVCMPPD_mon: \"VCMPGEPD\" is imm8=0xd { }\nVCMPPD_op: \"\" is imm8=0xd { export 0xd:1; }\nVCMPPD_mon: \"VCMPGTPD\" is imm8=0xe { }\nVCMPPD_op: \"\" is imm8=0xe { export 0xe:1; }\nVCMPPD_mon: \"VCMPTRUEPD\" is imm8=0xf { }\nVCMPPD_op: \"\" is imm8=0xf { export 0xf:1; }\nVCMPPD_mon: \"VCMPEQ_OSPD\" is imm8=0x10 { }\nVCMPPD_op: \"\" is imm8=0x10 { export 0x10:1; }\nVCMPPD_mon: \"VCMPLT_OQPD\" is imm8=0x11 { }\nVCMPPD_op: \"\" is imm8=0x11 { export 0x11:1; }\nVCMPPD_mon: \"VCMPLE_OQPD\" is imm8=0x12 { }\nVCMPPD_op: \"\" is imm8=0x12 { export 0x12:1; }\nVCMPPD_mon: \"VCMPUNORD_SPD\" is imm8=0x13 { }\nVCMPPD_op: \"\" is imm8=0x13 { export 0x13:1; }\nVCMPPD_mon: \"VCMPNEQ_USPD\" is imm8=0x14 { }\nVCMPPD_op: \"\" is imm8=0x14 { export 0x14:1; }\nVCMPPD_mon: \"VCMPNLT_UQPD\" is imm8=0x15 { }\nVCMPPD_op: \"\" is imm8=0x15 { export 0x15:1; }\nVCMPPD_mon: \"VCMPNLE_UQPD\" is imm8=0x16 { }\nVCMPPD_op: \"\" is imm8=0x16 { export 0x16:1; }\nVCMPPD_mon: \"VCMPORD_SPD\" is imm8=0x17 { }\nVCMPPD_op: \"\" is imm8=0x17 { export 0x17:1; }\nVCMPPD_mon: \"VCMPEQ_USPD\" is imm8=0x18 { }\nVCMPPD_op: \"\" is imm8=0x18 { export 0x18:1; }\nVCMPPD_mon: \"VCMPNGE_UQPD\" is imm8=0x19 { }\nVCMPPD_op: \"\" is imm8=0x19 { export 0x19:1; }\nVCMPPD_mon: \"VCMPNGT_UQPD\" is imm8=0x1a { }\nVCMPPD_op: \"\" is imm8=0x1a { export 0x1a:1; }\nVCMPPD_mon: \"VCMPFALSE_OSPD\" is imm8=0x1b { }\nVCMPPD_op: \"\" is imm8=0x1b { export 0x1b:1; }\nVCMPPD_mon: \"VCMPNEQ_OSPD\" is imm8=0x1c { }\nVCMPPD_op: \"\" is imm8=0x1c { export 0x1c:1; }\nVCMPPD_mon: \"VCMPGE_OQPD\" is imm8=0x1d { }\nVCMPPD_op: \"\" is imm8=0x1d { export 0x1d:1; }\nVCMPPD_mon: \"VCMPGT_OQPD\" is imm8=0x1e { }\nVCMPPD_op: \"\" is imm8=0x1e { export 0x1e:1; }\nVCMPPD_mon: \"VCMPTRUE_USPD\" is imm8=0x1f { }\nVCMPPD_op: \"\" is imm8=0x1f { export 0x1f:1; }\nVCMPPD_mon: \"VCMPPD\" is imm8 { }\nVCMPPD_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\ndefine pcodeop vcmppd_avx ;\n:^VCMPPD_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m128^VCMPPD_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; VCMPPD_mon & VCMPPD_op\n{\n\tlocal tmp:16 = vcmppd_avx( vexVVVV_XmmReg, XmmReg2_m128, VCMPPD_op );\n\tZmmReg1 = zext(tmp);\n}\n\n# CMPPD 3-155 PAGE 725 LINE 39243\n:^VCMPPD_mon YmmReg1, vexVVVV_YmmReg, YmmReg2_m256^VCMPPD_op is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC2; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; VCMPPD_mon & VCMPPD_op\n{\n\tlocal tmp:32 = vcmppd_avx( vexVVVV_YmmReg, YmmReg2_m256, VCMPPD_op );\n\tZmmReg1 = zext(tmp);\n}\n\n# CMPPS 3-162 PAGE 732 LINE 39607\nVCMPPS_mon: \"VCMPEQPS\" is imm8=0x0 { }\nVCMPPS_op: \"\" is imm8=0x0 { export 0x0:1; }\nVCMPPS_mon: \"VCMPLTPS\" is imm8=0x1 { }\nVCMPPS_op: \"\" is imm8=0x1 { export 0x1:1; }\nVCMPPS_mon: \"VCMPLEPS\" is imm8=0x2 { }\nVCMPPS_op: \"\" is imm8=0x2 { export 0x2:1; }\nVCMPPS_mon: \"VCMPUNORDPS\" is imm8=0x3 { }\nVCMPPS_op: \"\" is imm8=0x3 { export 0x3:1; }\nVCMPPS_mon: \"VCMPNEQPS\" is imm8=0x4 { }\nVCMPPS_op: \"\" is imm8=0x4 { export 0x4:1; }\nVCMPPS_mon: \"VCMPNLTPS\" is imm8=0x5 { }\nVCMPPS_op: \"\" is imm8=0x5 { export 0x5:1; }\nVCMPPS_mon: \"VCMPNLEPS\" is imm8=0x6 { }\nVCMPPS_op: \"\" is imm8=0x6 { export 0x6:1; }\nVCMPPS_mon: \"VCMPORDPS\" is imm8=0x7 { }\nVCMPPS_op: \"\" is imm8=0x7 { export 0x7:1; }\nVCMPPS_mon: \"VCMPEQ_UQPS\" is imm8=0x8 { }\nVCMPPS_op: \"\" is imm8=0x8 { export 0x8:1; }\nVCMPPS_mon: \"VCMPNGEPS\" is imm8=0x9 { }\nVCMPPS_op: \"\" is imm8=0x9 { export 0x9:1; }\nVCMPPS_mon: \"VCMPNGTPS\" is imm8=0xa { }\nVCMPPS_op: \"\" is imm8=0xa { export 0xa:1; }\nVCMPPS_mon: \"VCMPFALSEPS\" is imm8=0xb { }\nVCMPPS_op: \"\" is imm8=0xb { export 0xb:1; }\nVCMPPS_mon: \"VCMPNEQ_OQPS\" is imm8=0xc { }\nVCMPPS_op: \"\" is imm8=0xc { export 0xc:1; }\nVCMPPS_mon: \"VCMPGEPS\" is imm8=0xd { }\nVCMPPS_op: \"\" is imm8=0xd { export 0xd:1; }\nVCMPPS_mon: \"VCMPGTPS\" is imm8=0xe { }\nVCMPPS_op: \"\" is imm8=0xe { export 0xe:1; }\nVCMPPS_mon: \"VCMPTRUEPS\" is imm8=0xf { }\nVCMPPS_op: \"\" is imm8=0xf { export 0xf:1; }\nVCMPPS_mon: \"VCMPEQ_OSPS\" is imm8=0x10 { }\nVCMPPS_op: \"\" is imm8=0x10 { export 0x10:1; }\nVCMPPS_mon: \"VCMPLT_OQPS\" is imm8=0x11 { }\nVCMPPS_op: \"\" is imm8=0x11 { export 0x11:1; }\nVCMPPS_mon: \"VCMPLE_OQPS\" is imm8=0x12 { }\nVCMPPS_op: \"\" is imm8=0x12 { export 0x12:1; }\nVCMPPS_mon: \"VCMPUNORD_SPS\" is imm8=0x13 { }\nVCMPPS_op: \"\" is imm8=0x13 { export 0x13:1; }\nVCMPPS_mon: \"VCMPNEQ_USPS\" is imm8=0x14 { }\nVCMPPS_op: \"\" is imm8=0x14 { export 0x14:1; }\nVCMPPS_mon: \"VCMPNLT_UQPS\" is imm8=0x15 { }\nVCMPPS_op: \"\" is imm8=0x15 { export 0x15:1; }\nVCMPPS_mon: \"VCMPNLE_UQPS\" is imm8=0x16 { }\nVCMPPS_op: \"\" is imm8=0x16 { export 0x16:1; }\nVCMPPS_mon: \"VCMPORD_SPS\" is imm8=0x17 { }\nVCMPPS_op: \"\" is imm8=0x17 { export 0x17:1; }\nVCMPPS_mon: \"VCMPEQ_USPS\" is imm8=0x18 { }\nVCMPPS_op: \"\" is imm8=0x18 { export 0x18:1; }\nVCMPPS_mon: \"VCMPNGE_UQPS\" is imm8=0x19 { }\nVCMPPS_op: \"\" is imm8=0x19 { export 0x19:1; }\nVCMPPS_mon: \"VCMPNGT_UQPS\" is imm8=0x1a { }\nVCMPPS_op: \"\" is imm8=0x1a { export 0x1a:1; }\nVCMPPS_mon: \"VCMPFALSE_OSPS\" is imm8=0x1b { }\nVCMPPS_op: \"\" is imm8=0x1b { export 0x1b:1; }\nVCMPPS_mon: \"VCMPNEQ_OSPS\" is imm8=0x1c { }\nVCMPPS_op: \"\" is imm8=0x1c { export 0x1c:1; }\nVCMPPS_mon: \"VCMPGE_OQPS\" is imm8=0x1d { }\nVCMPPS_op: \"\" is imm8=0x1d { export 0x1d:1; }\nVCMPPS_mon: \"VCMPGT_OQPS\" is imm8=0x1e { }\nVCMPPS_op: \"\" is imm8=0x1e { export 0x1e:1; }\nVCMPPS_mon: \"VCMPTRUE_USPS\" is imm8=0x1f { }\nVCMPPS_op: \"\" is imm8=0x1f { export 0x1f:1; }\nVCMPPS_mon: \"VCMPPS\" is imm8 { }\nVCMPPS_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\ndefine pcodeop vcmpps_avx ;\n:^VCMPPS_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m128^VCMPPS_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; VCMPPS_mon & VCMPPS_op\n{\n\tlocal tmp:16 = vcmpps_avx( vexVVVV_XmmReg, XmmReg2_m128, VCMPPS_op );\n\tZmmReg1 = zext(tmp);\n}\n\n# CMPPS 3-162 PAGE 732 LINE 39610\n:^VCMPPS_mon YmmReg1, vexVVVV_YmmReg, YmmReg2_m256^VCMPPS_op is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC2; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; VCMPPS_mon & VCMPPS_op\n{\n\tlocal tmp:32 = vcmpps_avx( vexVVVV_YmmReg, YmmReg2_m256, VCMPPS_op );\n\tZmmReg1 = zext(tmp);\n}\n\n# CMPSD 3-173 PAGE 743 LINE 40154\nVCMPSD_mon: \"VCMPEQSD\" is imm8=0x0 { }\nVCMPSD_op: \"\" is imm8=0x0 { export 0x0:1; }\nVCMPSD_mon: \"VCMPLTSD\" is imm8=0x1 { }\nVCMPSD_op: \"\" is imm8=0x1 { export 0x1:1; }\nVCMPSD_mon: \"VCMPLESD\" is imm8=0x2 { }\nVCMPSD_op: \"\" is imm8=0x2 { export 0x2:1; }\nVCMPSD_mon: \"VCMPUNORDSD\" is imm8=0x3 { }\nVCMPSD_op: \"\" is imm8=0x3 { export 0x3:1; }\nVCMPSD_mon: \"VCMPNEQSD\" is imm8=0x4 { }\nVCMPSD_op: \"\" is imm8=0x4 { export 0x4:1; }\nVCMPSD_mon: \"VCMPNLTSD\" is imm8=0x5 { }\nVCMPSD_op: \"\" is imm8=0x5 { export 0x5:1; }\nVCMPSD_mon: \"VCMPNLESD\" is imm8=0x6 { }\nVCMPSD_op: \"\" is imm8=0x6 { export 0x6:1; }\nVCMPSD_mon: \"VCMPORDSD\" is imm8=0x7 { }\nVCMPSD_op: \"\" is imm8=0x7 { export 0x7:1; }\nVCMPSD_mon: \"VCMPEQ_UQSD\" is imm8=0x8 { }\nVCMPSD_op: \"\" is imm8=0x8 { export 0x8:1; }\nVCMPSD_mon: \"VCMPNGESD\" is imm8=0x9 { }\nVCMPSD_op: \"\" is imm8=0x9 { export 0x9:1; }\nVCMPSD_mon: \"VCMPNGTSD\" is imm8=0xa { }\nVCMPSD_op: \"\" is imm8=0xa { export 0xa:1; }\nVCMPSD_mon: \"VCMPFALSESD\" is imm8=0xb { }\nVCMPSD_op: \"\" is imm8=0xb { export 0xb:1; }\nVCMPSD_mon: \"VCMPNEQ_OQSD\" is imm8=0xc { }\nVCMPSD_op: \"\" is imm8=0xc { export 0xc:1; }\nVCMPSD_mon: \"VCMPGESD\" is imm8=0xd { }\nVCMPSD_op: \"\" is imm8=0xd { export 0xd:1; }\nVCMPSD_mon: \"VCMPGTSD\" is imm8=0xe { }\nVCMPSD_op: \"\" is imm8=0xe { export 0xe:1; }\nVCMPSD_mon: \"VCMPTRUESD\" is imm8=0xf { }\nVCMPSD_op: \"\" is imm8=0xf { export 0xf:1; }\nVCMPSD_mon: \"VCMPEQ_OSSD\" is imm8=0x10 { }\nVCMPSD_op: \"\" is imm8=0x10 { export 0x10:1; }\nVCMPSD_mon: \"VCMPLT_OQSD\" is imm8=0x11 { }\nVCMPSD_op: \"\" is imm8=0x11 { export 0x11:1; }\nVCMPSD_mon: \"VCMPLE_OQSD\" is imm8=0x12 { }\nVCMPSD_op: \"\" is imm8=0x12 { export 0x12:1; }\nVCMPSD_mon: \"VCMPUNORD_SSD\" is imm8=0x13 { }\nVCMPSD_op: \"\" is imm8=0x13 { export 0x13:1; }\nVCMPSD_mon: \"VCMPNEQ_USSD\" is imm8=0x14 { }\nVCMPSD_op: \"\" is imm8=0x14 { export 0x14:1; }\nVCMPSD_mon: \"VCMPNLT_UQSD\" is imm8=0x15 { }\nVCMPSD_op: \"\" is imm8=0x15 { export 0x15:1; }\nVCMPSD_mon: \"VCMPNLE_UQSD\" is imm8=0x16 { }\nVCMPSD_op: \"\" is imm8=0x16 { export 0x16:1; }\nVCMPSD_mon: \"VCMPORD_SSD\" is imm8=0x17 { }\nVCMPSD_op: \"\" is imm8=0x17 { export 0x17:1; }\nVCMPSD_mon: \"VCMPEQ_USSD\" is imm8=0x18 { }\nVCMPSD_op: \"\" is imm8=0x18 { export 0x18:1; }\nVCMPSD_mon: \"VCMPNGE_UQSD\" is imm8=0x19 { }\nVCMPSD_op: \"\" is imm8=0x19 { export 0x19:1; }\nVCMPSD_mon: \"VCMPNGT_UQSD\" is imm8=0x1a { }\nVCMPSD_op: \"\" is imm8=0x1a { export 0x1a:1; }\nVCMPSD_mon: \"VCMPFALSE_OSSD\" is imm8=0x1b { }\nVCMPSD_op: \"\" is imm8=0x1b { export 0x1b:1; }\nVCMPSD_mon: \"VCMPNEQ_OSSD\" is imm8=0x1c { }\nVCMPSD_op: \"\" is imm8=0x1c { export 0x1c:1; }\nVCMPSD_mon: \"VCMPGE_OQSD\" is imm8=0x1d { }\nVCMPSD_op: \"\" is imm8=0x1d { export 0x1d:1; }\nVCMPSD_mon: \"VCMPGT_OQSD\" is imm8=0x1e { }\nVCMPSD_op: \"\" is imm8=0x1e { export 0x1e:1; }\nVCMPSD_mon: \"VCMPTRUE_USSD\" is imm8=0x1f { }\nVCMPSD_op: \"\" is imm8=0x1f { export 0x1f:1; }\nVCMPSD_mon: \"VCMPSD\" is imm8 { }\nVCMPSD_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\ndefine pcodeop vcmpsd_avx ;\n:^VCMPSD_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m64^VCMPSD_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op\n{\n\tlocal tmp:16 = vcmpsd_avx( vexVVVV_XmmReg, XmmReg2_m64, VCMPSD_op );\n\tZmmReg1 = zext(tmp);\n}\n\n# CMPSS 3-177 PAGE 747 LINE 40390\nVCMPSS_mon: \"VCMPEQSS\" is imm8=0x0 { }\nVCMPSS_op: \"\" is imm8=0x0 { export 0x0:1; }\nVCMPSS_mon: \"VCMPLTSS\" is imm8=0x1 { }\nVCMPSS_op: \"\" is imm8=0x1 { export 0x1:1; }\nVCMPSS_mon: \"VCMPLESS\" is imm8=0x2 { }\nVCMPSS_op: \"\" is imm8=0x2 { export 0x2:1; }\nVCMPSS_mon: \"VCMPUNORDSS\" is imm8=0x3 { }\nVCMPSS_op: \"\" is imm8=0x3 { export 0x3:1; }\nVCMPSS_mon: \"VCMPNEQSS\" is imm8=0x4 { }\nVCMPSS_op: \"\" is imm8=0x4 { export 0x4:1; }\nVCMPSS_mon: \"VCMPNLTSS\" is imm8=0x5 { }\nVCMPSS_op: \"\" is imm8=0x5 { export 0x5:1; }\nVCMPSS_mon: \"VCMPNLESS\" is imm8=0x6 { }\nVCMPSS_op: \"\" is imm8=0x6 { export 0x6:1; }\nVCMPSS_mon: \"VCMPORDSS\" is imm8=0x7 { }\nVCMPSS_op: \"\" is imm8=0x7 { export 0x7:1; }\nVCMPSS_mon: \"VCMPEQ_UQSS\" is imm8=0x8 { }\nVCMPSS_op: \"\" is imm8=0x8 { export 0x8:1; }\nVCMPSS_mon: \"VCMPNGESS\" is imm8=0x9 { }\nVCMPSS_op: \"\" is imm8=0x9 { export 0x9:1; }\nVCMPSS_mon: \"VCMPNGTSS\" is imm8=0xa { }\nVCMPSS_op: \"\" is imm8=0xa { export 0xa:1; }\nVCMPSS_mon: \"VCMPFALSESS\" is imm8=0xb { }\nVCMPSS_op: \"\" is imm8=0xb { export 0xb:1; }\nVCMPSS_mon: \"VCMPNEQ_OQSS\" is imm8=0xc { }\nVCMPSS_op: \"\" is imm8=0xc { export 0xc:1; }\nVCMPSS_mon: \"VCMPGESS\" is imm8=0xd { }\nVCMPSS_op: \"\" is imm8=0xd { export 0xd:1; }\nVCMPSS_mon: \"VCMPGTSS\" is imm8=0xe { }\nVCMPSS_op: \"\" is imm8=0xe { export 0xe:1; }\nVCMPSS_mon: \"VCMPTRUESS\" is imm8=0xf { }\nVCMPSS_op: \"\" is imm8=0xf { export 0xf:1; }\nVCMPSS_mon: \"VCMPEQ_OSSS\" is imm8=0x10 { }\nVCMPSS_op: \"\" is imm8=0x10 { export 0x10:1; }\nVCMPSS_mon: \"VCMPLT_OQSS\" is imm8=0x11 { }\nVCMPSS_op: \"\" is imm8=0x11 { export 0x11:1; }\nVCMPSS_mon: \"VCMPLE_OQSS\" is imm8=0x12 { }\nVCMPSS_op: \"\" is imm8=0x12 { export 0x12:1; }\nVCMPSS_mon: \"VCMPUNORD_SSS\" is imm8=0x13 { }\nVCMPSS_op: \"\" is imm8=0x13 { export 0x13:1; }\nVCMPSS_mon: \"VCMPNEQ_USSS\" is imm8=0x14 { }\nVCMPSS_op: \"\" is imm8=0x14 { export 0x14:1; }\nVCMPSS_mon: \"VCMPNLT_UQSS\" is imm8=0x15 { }\nVCMPSS_op: \"\" is imm8=0x15 { export 0x15:1; }\nVCMPSS_mon: \"VCMPNLE_UQSS\" is imm8=0x16 { }\nVCMPSS_op: \"\" is imm8=0x16 { export 0x16:1; }\nVCMPSS_mon: \"VCMPORD_SSS\" is imm8=0x17 { }\nVCMPSS_op: \"\" is imm8=0x17 { export 0x17:1; }\nVCMPSS_mon: \"VCMPEQ_USSS\" is imm8=0x18 { }\nVCMPSS_op: \"\" is imm8=0x18 { export 0x18:1; }\nVCMPSS_mon: \"VCMPNGE_UQSS\" is imm8=0x19 { }\nVCMPSS_op: \"\" is imm8=0x19 { export 0x19:1; }\nVCMPSS_mon: \"VCMPNGT_UQSS\" is imm8=0x1a { }\nVCMPSS_op: \"\" is imm8=0x1a { export 0x1a:1; }\nVCMPSS_mon: \"VCMPFALSE_OSSS\" is imm8=0x1b { }\nVCMPSS_op: \"\" is imm8=0x1b { export 0x1b:1; }\nVCMPSS_mon: \"VCMPNEQ_OSSS\" is imm8=0x1c { }\nVCMPSS_op: \"\" is imm8=0x1c { export 0x1c:1; }\nVCMPSS_mon: \"VCMPGE_OQSS\" is imm8=0x1d { }\nVCMPSS_op: \"\" is imm8=0x1d { export 0x1d:1; }\nVCMPSS_mon: \"VCMPGT_OQSS\" is imm8=0x1e { }\nVCMPSS_op: \"\" is imm8=0x1e { export 0x1e:1; }\nVCMPSS_mon: \"VCMPTRUE_USSS\" is imm8=0x1f { }\nVCMPSS_op: \"\" is imm8=0x1f { export 0x1f:1; }\nVCMPSS_mon: \"VCMPSS\" is imm8 { }\nVCMPSS_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\ndefine pcodeop vcmpss_avx ;\n:^VCMPSS_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m32^VCMPSS_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op\n{\n\tlocal tmp:16 = vcmpss_avx( vexVVVV_XmmReg, XmmReg2_m32, VCMPSS_op );\n\tZmmReg1 = zext(tmp);\n}\n\n# COMISD 3-186 PAGE 756 LINE 40860\n:VCOMISD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n fucompe(XmmReg1[0,64], XmmReg2_m64[0,64]);\n}\n\n# COMISS 3-188 PAGE 758 LINE 40938\n:VCOMISS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tfucompe(XmmReg1[0,32], XmmReg2_m32[0,32]);\n}\n\n# CVTDQ2PD 3-228 PAGE 798 LINE 43074\ndefine pcodeop vcvtdq2pd_avx ;\n:VCVTDQ2PD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vcvtdq2pd_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTDQ2PD 3-228 PAGE 798 LINE 43077\n:VCVTDQ2PD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vcvtdq2pd_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTDQ2PS 3-232 PAGE 802 LINE 43242\ndefine pcodeop vcvtdq2ps_avx ;\n:VCVTDQ2PS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vcvtdq2ps_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTDQ2PS 3-232 PAGE 802 LINE 43245\n:VCVTDQ2PS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vcvtdq2ps_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPD2DQ 3-235 PAGE 805 LINE 43408\ndefine pcodeop vcvtpd2dq_avx ;\n:VCVTPD2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vcvtpd2dq_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPD2DQ 3-235 PAGE 805 LINE 43411\n:VCVTPD2DQ XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vcvtpd2dq_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPD2PS 3-240 PAGE 810 LINE 43643\ndefine pcodeop vcvtpd2ps_avx ;\n:VCVTPD2PS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vcvtpd2ps_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPD2PS 3-240 PAGE 810 LINE 43646\n:VCVTPD2PS XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vcvtpd2ps_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPS2DQ 3-246 PAGE 816 LINE 43927\ndefine pcodeop vcvtps2dq_avx ;\n:VCVTPS2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vcvtps2dq_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPS2DQ 3-246 PAGE 816 LINE 43930\n:VCVTPS2DQ YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vcvtps2dq_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPS2PD 3-249 PAGE 819 LINE 44098\ndefine pcodeop vcvtps2pd_avx ;\n:VCVTPS2PD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vcvtps2pd_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTPS2PD 3-249 PAGE 819 LINE 44101\n:VCVTPS2PD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vcvtps2pd_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTSD2SI 3-253 PAGE 823 LINE 44315\n:VCVTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m64\n{\n\tReg32 = trunc(round(XmmReg2_m64[0,64]));\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# CVTSD2SI 3-253 PAGE 823 LINE 44317\n@ifdef IA64\n:VCVTSD2SI Reg64, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m64\n{\n\tReg64 = round(XmmReg2_m64[0,64]);\n}\n@endif\n\n# CVTSD2SS 3-255 PAGE 825 LINE 44414\n:VCVTSD2SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:4 = float2float(XmmReg2_m64[0,64]);\n\tXmmReg1[0,32] = tmp;\n\tXmmReg1[32,96] = vexVVVV_XmmReg[32,96];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTSI2SD 3-257 PAGE 827 LINE 44516\n:VCVTSI2SD XmmReg1, vexVVVV_XmmReg, rm32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32\n{\n\tlocal tmp:8 = int2float(rm32);\n\tXmmReg1[0,64] = tmp;\n\tXmmReg1[64,64] = vexVVVV_XmmReg[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTSI2SD 3-257 PAGE 827 LINE 44519\n@ifdef IA64\n:VCVTSI2SD XmmReg1, vexVVVV_XmmReg, rm64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64\n{\n\tlocal tmp:8 = int2float(rm64);\n\tXmmReg1[0,64] = tmp;\n\tXmmReg1[64,64] = vexVVVV_XmmReg[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n@endif\n\n# CVTSI2SS 3-259 PAGE 829 LINE 44632\n:VCVTSI2SS XmmReg1, vexVVVV_XmmReg, rm32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32\n{\n\tlocal tmp:4 = int2float( rm32 );\n\tXmmReg1[0,32] = tmp;\n\tXmmReg1[32,96] = vexVVVV_XmmReg[32,96];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTSI2SS 3-259 PAGE 829 LINE 44634\n@ifdef IA64\n:VCVTSI2SS XmmReg1, vexVVVV_XmmReg, rm64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64\n{\n\tlocal tmp:4 = int2float( rm64 );\n\tXmmReg1[0,32] = tmp;\n\tXmmReg1[32,96] = vexVVVV_XmmReg[32,96];\n\tZmmReg1 = zext(XmmReg1);\n}\n@endif\n\n# CVTSS2SD 3-261 PAGE 831 LINE 44744\n:VCVTSS2SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:8 = float2float( XmmReg2_m32[0,32] );\n\tXmmReg1[0,64] = tmp;\n\tXmmReg1[64,64] = vexVVVV_XmmReg[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTSS2SI 3-263 PAGE 833 LINE 44835\n:VCVTSS2SI Reg32, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m32\n{\n\tReg32 = trunc(round(XmmReg2_m32[0,32]));\n}\n\n# CVTSS2SI 3-263 PAGE 833 LINE 44837\n@ifdef IA64\n:VCVTSS2SI Reg64, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m32\n{\n\tReg64 = trunc(round(XmmReg2_m32[0,32]));\n}\n\n@endif\n\n# CVTTPD2DQ 3-265 PAGE 835 LINE 44930\n:VCVTTPD2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = XmmReg2_m128;\n\tXmmReg1[0,32] = trunc(tmp[0,64]);\n\tXmmReg1[32,32] = trunc(tmp[64,64]);\n\tXmmReg1[64,32] = 0;\n\tXmmReg1[96,32] = 0;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTTPD2DQ 3-265 PAGE 835 LINE 44933\n:VCVTTPD2DQ XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = YmmReg2_m256;\n\tXmmReg1[0,32] = trunc(tmp[0,64]);\n\tXmmReg1[32,32] = trunc(tmp[64,64]);\n\tXmmReg1[64,32] = trunc(tmp[128,64]);\n\tXmmReg1[96,32] = trunc(tmp[192,64]);\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTTPS2DQ 3-270 PAGE 840 LINE 45163\n:VCVTTPS2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = XmmReg2_m128;\n\tXmmReg1[0,32] = trunc(tmp[0,32]);\n\tXmmReg1[32,32] = trunc(tmp[32,32]);\n\tXmmReg1[64,32] = trunc(tmp[64,32]);\n\tXmmReg1[96,32] = trunc(tmp[96,32]);\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# CVTTPS2DQ 3-270 PAGE 840 LINE 45166\n:VCVTTPS2DQ YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = YmmReg2_m256;\n\tYmmReg1[0,32] = trunc(tmp[0,32]);\n\tYmmReg1[32,32] = trunc(tmp[32,32]);\n\tYmmReg1[64,32] = trunc(tmp[64,32]);\n\tYmmReg1[96,32] = trunc(tmp[96,32]);\n\tYmmReg1[128,32] = trunc(tmp[128,32]);\n\tYmmReg1[160,32] = trunc(tmp[160,32]);\n\tYmmReg1[192,32] = trunc(tmp[192,32]);\n\tYmmReg1[224,32] = trunc(tmp[224,32]);\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# CVTTSD2SI 3-274 PAGE 844 LINE 45379\n:VCVTTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m64\n{\n\tReg32 = trunc(XmmReg2_m64[0,64]);\n}\n\n# CVTTSD2SI 3-274 PAGE 844 LINE 45382\n@ifdef IA64\n:VCVTTSD2SI Reg64, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m64\n{\n\tReg64 = trunc(XmmReg2_m64[0,64]);\n}\n\n@endif\n\n# CVTTSS2SI 3-276 PAGE 846 LINE 45473\n:VCVTTSS2SI Reg32, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m32\n{\n\tReg32 = trunc(XmmReg2_m32[0,32]);\n}\n\n# CVTTSS2SI 3-276 PAGE 846 LINE 45476\n@ifdef IA64\n:VCVTTSS2SI Reg64, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m32\n{\n\tReg64 = trunc(XmmReg2_m32[0,32]);\n}\n@endif\n\n# DIVPD 3-288 PAGE 858 LINE 46023\ndefine pcodeop vdivpd_avx ;\n:VDIVPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vdivpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# DIVPD 3-288 PAGE 858 LINE 46026\n:VDIVPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vdivpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# DIVPS 3-291 PAGE 861 LINE 46164\ndefine pcodeop vdivps_avx ;\n:VDIVPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vdivps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# DIVPS 3-291 PAGE 861 LINE 46167\n:VDIVPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vdivps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# DIVSD 3-294 PAGE 864 LINE 46312\n:VDIVSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tXmmReg1[0,64] = vexVVVV_XmmReg[0,64] f/ XmmReg2_m64[0,64];\n\tXmmReg1[64,64] = vexVVVV_XmmReg[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# DIVSS 3-296 PAGE 866 LINE 46410\n:VDIVSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tXmmReg1[0,32] = vexVVVV_XmmReg[0,32] f/ XmmReg2_m32[0,32];\n\tXmmReg1[32,96] = vexVVVV_XmmReg[32,96];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# DPPD 3-298 PAGE 868 LINE 46509\ndefine pcodeop vdppd_avx ;\n:VDPPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x41; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vdppd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# DPPS 3-300 PAGE 870 LINE 46612\ndefine pcodeop vdpps_avx ;\n:VDPPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vdpps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# DPPS 3-300 PAGE 870 LINE 46616\n:VDPPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vdpps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# EXTRACTPS 3-307 PAGE 877 LINE 46978\ndefine pcodeop vextractps_avx ;\n:VEXTRACTPS rm32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x17; XmmReg1 ... & rm32; imm8\n{\n\trm32 = vextractps_avx( XmmReg1, imm8:1 );\n}\n\n# HADDPD 3-427 PAGE 997 LINE 52447\n:VHADDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal m:16 = XmmReg2_m128;\n XmmReg1[0,64] = vexVVVV_XmmReg[0,64] f+ vexVVVV_XmmReg[64,64];\n XmmReg1[64,64] = m[0,64] f+ m[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# HADDPD 3-427 PAGE 997 LINE 52450\n:VHADDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal m:32 = YmmReg2_m256;\n YmmReg1[0,64] = vexVVVV_YmmReg[0,64] f+ vexVVVV_YmmReg[64,64];\n YmmReg1[64,64] = m[0,64] f+ m[64,64];\n YmmReg1[128,64] = vexVVVV_YmmReg[128,64] f+ vexVVVV_YmmReg[192,64];\n YmmReg1[192,64] = m[128,64] f+ m[192,64];\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# HADDPS 3-430 PAGE 1000 LINE 52586\ndefine pcodeop vhaddps_avx ;\n:VHADDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vhaddps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# HADDPS 3-430 PAGE 1000 LINE 52589\n:VHADDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vhaddps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# HSUBPD 3-434 PAGE 1004 LINE 52795\ndefine pcodeop vhsubpd_avx ;\n:VHSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vhsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# HSUBPD 3-434 PAGE 1004 LINE 52798\n:VHSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vhsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# HSUBPS 3-437 PAGE 1007 LINE 52933\ndefine pcodeop vhsubps_avx ;\n:VHSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vhsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# HSUBPS 3-437 PAGE 1007 LINE 52936\n:VHSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vhsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# INSERTPS 3-454 PAGE 1024 LINE 53780\ndefine pcodeop vinsertps_avx ;\n:VINSERTPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8\n{\n\tlocal tmp:16 = vinsertps_avx( vexVVVV_XmmReg, XmmReg2_m32, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# LDDQU 3-518 PAGE 1088 LINE 57123\ndefine pcodeop vlddqu_avx ;\n:VLDDQU XmmReg1, m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xF0; (XmmReg1 & ZmmReg1) ... & m128\n{\n\tlocal tmp:16 = vlddqu_avx( m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# LDDQU 3-518 PAGE 1088 LINE 57126\n:VLDDQU YmmReg1, m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xF0; (YmmReg1 & ZmmReg1) ... & m256\n{\n\tlocal tmp:32 = vlddqu_avx( m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# LDMXCSR 3-520 PAGE 1090 LINE 57208\ndefine pcodeop vldmxcsr_avx ;\n:VLDMXCSR m32 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0xAE; reg_opcode=2 ... & m32\n{\n\tvldmxcsr_avx( m32 );\n\t# TODO missing destination or side effects\n}\n\n# MASKMOVDQU 4-8 PAGE 1128 LINE 59041\ndefine pcodeop vmaskmovdqu_avx ;\n:VMASKMOVDQU XmmReg1, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xF7; XmmReg1 & (mod=0x3 & XmmReg2)\n{\n\tvmaskmovdqu_avx( XmmReg1, XmmReg2 );\n\t# TODO missing destination or side effects\n}\n\n# MAXPD 4-12 PAGE 1132 LINE 59201\ndefine pcodeop vmaxpd_avx ;\n:VMAXPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vmaxpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MAXPD 4-12 PAGE 1132 LINE 59203\n:VMAXPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vmaxpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MAXPS 4-15 PAGE 1135 LINE 59350\ndefine pcodeop vmaxps_avx ;\n:VMAXPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vmaxps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MAXPS 4-15 PAGE 1135 LINE 59353\n:VMAXPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vmaxps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MAXSD 4-18 PAGE 1138 LINE 59503\ndefine pcodeop vmaxsd_avx ;\n:VMAXSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vmaxsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MAXSS 4-20 PAGE 1140 LINE 59606\ndefine pcodeop vmaxss_avx ;\n:VMAXSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vmaxss_avx( vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MINPD 4-23 PAGE 1143 LINE 59765\ndefine pcodeop vminpd_avx ;\n:VMINPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vminpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MINPD 4-23 PAGE 1143 LINE 59768\n:VMINPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vminpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MINPS 4-26 PAGE 1146 LINE 59909\ndefine pcodeop vminps_avx ;\n:VMINPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vminps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MINPS 4-26 PAGE 1146 LINE 59912\n:VMINPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vminps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MINSD 4-29 PAGE 1149 LINE 60061\ndefine pcodeop vminsd_avx ;\n:VMINSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vminsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MINSS 4-31 PAGE 1151 LINE 60164\ndefine pcodeop vminss_avx ;\n:VMINSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vminss_avx( vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61358\n:VMOVD XmmReg1, rm32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6E; (XmmReg1 & ZmmReg1) ... & rm32\n{\n\tZmmReg1 = zext( rm32 );\n}\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61360\n@ifdef IA64\n:VMOVQ XmmReg1, rm64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x6E; (XmmReg1 & ZmmReg1) ... & rm64\n{\n\tZmmReg1 = zext( rm64 );\n}\n@endif\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61362\n:VMOVD rm32, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; XmmReg1 ... & rm32\n{\n\trm32 = XmmReg1 [0,32];\n}\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61364\n@ifdef IA64\n:VMOVQ rm64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7E; XmmReg1 ... & rm64\n{\n\trm64 = XmmReg1 [0,64];\n}\n@endif\n\n# MOVDDUP 4-59 PAGE 1179 LINE 61521\n:VMOVDDUP XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:8 = XmmReg2_m64[0,64];\n\tXmmReg1[0,64] = tmp;\n XmmReg1[64,64] = tmp;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVDDUP 4-59 PAGE 1179 LINE 61523\n:VMOVDDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = YmmReg2_m256;\n\tlocal tmp1:8 = tmp[0,64];\n\tlocal tmp2:8 = tmp[128,64];\n\tYmmReg1[0,64] = tmp1;\n YmmReg1[64,64] = tmp1;\n YmmReg1[128,64] = tmp2;\n YmmReg1[192,64] = tmp2;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61930\n:VMOVDQU XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = XmmReg2_m128;\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61932\n:VMOVDQU XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; (XmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128\n{\n\tXmmReg2_m128 = XmmReg1;\n\tbuild XmmReg2_m128_extend;\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61934\n:VMOVDQU YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = YmmReg2_m256;\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61936\n:VMOVDQU m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & m256\n{\n\tm256 = YmmReg1;\n}\n\n:VMOVDQU YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 & (mod=3 & ZmmReg2 & YmmReg2)\n{\n\tZmmReg2 = zext( YmmReg1 );\n}\n\n# MOVHLPS 4-76 PAGE 1196 LINE 62410\ndefine pcodeop vmovhlps_avx ;\n:VMOVHLPS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)\n{\n\tlocal tmp:16 = vmovhlps_avx( vexVVVV_XmmReg, XmmReg2 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVHPD 4-78 PAGE 1198 LINE 62483\ndefine pcodeop vmovhpd_avx ;\n:VMOVHPD XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64\n{\n\tlocal tmp:16 = vmovhpd_avx( vexVVVV_XmmReg, m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVHPD 4-78 PAGE 1198 LINE 62489\n:VMOVHPD m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x17; XmmReg1 ... & m64\n{\n\tm64 = vmovhpd_avx( XmmReg1 );\n}\n\n# MOVHPS 4-80 PAGE 1200 LINE 62570\ndefine pcodeop vmovhps_avx ;\n:VMOVHPS XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64\n{\n\tlocal tmp:16 = vmovhps_avx( vexVVVV_XmmReg, m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVHPS 4-80 PAGE 1200 LINE 62576\n:VMOVHPS m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x17; XmmReg1 ... & m64\n{\n\tm64 = vmovhps_avx( XmmReg1 );\n}\n\n# MOVLHPS 4-82 PAGE 1202 LINE 62658\ndefine pcodeop vmovlhps_avx ;\n:VMOVLHPS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)\n{\n\tlocal tmp:16 = vmovlhps_avx( vexVVVV_XmmReg, XmmReg2 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVLPD 4-84 PAGE 1204 LINE 62731\ndefine pcodeop vmovlpd_avx ;\n:VMOVLPD XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64\n{\n\tlocal tmp:16 = vmovlpd_avx( vexVVVV_XmmReg, m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVLPD 4-84 PAGE 1204 LINE 62737\n:VMOVLPD m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x13; XmmReg1 ... & m64\n{\n\tm64 = vmovlpd_avx( XmmReg1 );\n}\n\n# MOVLPS 4-86 PAGE 1206 LINE 62816\ndefine pcodeop vmovlps_avx ;\n:VMOVLPS XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64\n{\n\tlocal tmp:16 = vmovlps_avx( vexVVVV_XmmReg, m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVLPS 4-86 PAGE 1206 LINE 62822\n:VMOVLPS m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x13; XmmReg1 ... & m64\n{\n\tm64 = vmovlps_avx( XmmReg1 );\n}\n\n# MOVMSKPD 4-88 PAGE 1208 LINE 62906\ndefine pcodeop vmovmskpd_avx ;\n:VMOVMSKPD Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2)\n{\n\tReg32 = vmovmskpd_avx( XmmReg2 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# MOVMSKPD 4-88 PAGE 1208 LINE 62910\n:VMOVMSKPD Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2)\n{\n\tReg32 = vmovmskpd_avx( YmmReg2 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# MOVMSKPS 4-90 PAGE 1210 LINE 62986\ndefine pcodeop vmovmskps_avx ;\n:VMOVMSKPS Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2)\n{\n\tReg32 = vmovmskps_avx( XmmReg2 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# MOVMSKPS 4-90 PAGE 1210 LINE 62990\n:VMOVMSKPS Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2)\n{\n\tReg32 = vmovmskps_avx( YmmReg2 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# MOVNTDQA 4-92 PAGE 1212 LINE 63084\ndefine pcodeop vmovntdqa_avx ;\n:VMOVNTDQA XmmReg1, m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x2A; (XmmReg1 & ZmmReg1) ... & m128\n{\n\tlocal tmp:16 = vmovntdqa_avx( m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVNTDQ 4-94 PAGE 1214 LINE 63187\ndefine pcodeop vmovntdq_avx ;\n:VMOVNTDQ m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE7; XmmReg1 ... & m128\n{\n\tm128 = vmovntdq_avx( XmmReg1 );\n}\n\n# MOVNTDQ 4-94 PAGE 1214 LINE 63189\n:VMOVNTDQ m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE7; YmmReg1 ... & m256\n{\n\tm256 = vmovntdq_avx( YmmReg1 );\n}\n\n# MOVNTPD 4-98 PAGE 1218 LINE 63357\ndefine pcodeop vmovntpd_avx ;\n:VMOVNTPD m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; XmmReg1 ... & m128\n{\n\tm128 = vmovntpd_avx( XmmReg1 );\n}\n\n# MOVNTPD 4-98 PAGE 1218 LINE 63359\n:VMOVNTPD m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; YmmReg1 ... & m256\n{\n\tm256 = vmovntpd_avx( YmmReg1 );\n}\n\n# MOVNTPS 4-100 PAGE 1220 LINE 63441\ndefine pcodeop vmovntps_avx ;\n:VMOVNTPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; XmmReg1 ... & m128\n{\n\tm128 = vmovntps_avx( XmmReg1 );\n}\n\n# MOVNTPS 4-100 PAGE 1220 LINE 63443\n:VMOVNTPS m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; YmmReg1 ... & m256\n{\n\tm256 = vmovntps_avx( YmmReg1 );\n}\n\n# MOVQ 4-103 PAGE 1223 LINE 63579\n:VMOVQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tZmmReg1 = zext(XmmReg2_m64[0,64]);\n}\n\n# MOVQ 4-103 PAGE 1223 LINE 63585\n:VMOVQ m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD6; XmmReg1 ... & m64\n{\n\tm64 = XmmReg1[0,64];\n}\n\n:VMOVQ XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD6; XmmReg1 & (mod=3 & XmmReg2 & ZmmReg2 )\n{\n\tZmmReg2 = zext( XmmReg1[0,64] );\n}\n\n# MOVSHDUP 4-114 PAGE 1234 LINE 64126\ndefine pcodeop vmovshdup_avx ;\n:VMOVSHDUP XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x16; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vmovshdup_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVSHDUP 4-114 PAGE 1234 LINE 64128\n:VMOVSHDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vmovshdup_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVSLDUP 4-117 PAGE 1237 LINE 64280\ndefine pcodeop vmovsldup_avx ;\n:VMOVSLDUP XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vmovsldup_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVSLDUP 4-117 PAGE 1237 LINE 64282\n:VMOVSLDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vmovsldup_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64433\n\n:VMOVSS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)\n{\n\tXmmReg1[0,32] = XmmReg2[0,32];\n\tXmmReg1[32,96] = vexVVVV_XmmReg[32,96];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64435\n:VMOVSS XmmReg1, m32 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & ZmmReg1) ... & m32\n{\n\tZmmReg1 = zext( m32 );\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64439\n:VMOVSS XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))\n{\n\tXmmReg2[0,32] = XmmReg1[0,32];\n\tXmmReg2[32,96] = vexVVVV_XmmReg[32,96];\n\tZmmReg2 = zext(XmmReg2);\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64441\n:VMOVSS m32, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m32\n{\n\tm32 = XmmReg1[0,32];\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64687\n:VMOVUPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n local tmp:16 = XmmReg2_m128;\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64689\n:VMOVUPD XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; (XmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128\n{\n\tXmmReg2_m128 = XmmReg1;\n\tbuild XmmReg2_m128_extend;\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64691\n:VMOVUPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = YmmReg2_m256;\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64693\n:VMOVUPD m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 ... & m256\n{\n\tm256 = YmmReg1;\n}\n\n:VMOVUPD YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 & ( mod=3 & YmmReg2 & ZmmReg2 )\n{\n\tlocal tmp:32 = YmmReg1;\n\tZmmReg2 = zext(tmp);\n}\n\n# MPSADBW 4-136 PAGE 1256 LINE 65135\ndefine pcodeop vmpsadbw_avx ;\n:VMPSADBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vmpsadbw_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MULPD 4-146 PAGE 1266 LINE 65682\n:VMULPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal m:16 = XmmReg2_m128;\n XmmReg1[0,64] = vexVVVV_XmmReg[0,64] f* m[0,64];\n XmmReg1[64,64] = vexVVVV_XmmReg[64,64] f* m[64,64];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MULPD 4-146 PAGE 1266 LINE 65684\n:VMULPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal m:32 = YmmReg2_m256;\n YmmReg1[0,64] = vexVVVV_YmmReg[0,64] f* m[0,64];\n YmmReg1[64,64] = vexVVVV_YmmReg[64,64] f* m[64,64];\n YmmReg1[128,64] = vexVVVV_YmmReg[128,64] f* m[128,64];\n YmmReg1[192,64] = vexVVVV_YmmReg[192,64] f* m[192,64];\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# MULPS 4-149 PAGE 1269 LINE 65813\n:VMULPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal m:16 = XmmReg2_m128;\n XmmReg1[0,32] = vexVVVV_XmmReg[0,32] f* m[0,32];\n XmmReg1[32,32] = vexVVVV_XmmReg[32,32] f* m[32,32];\n XmmReg1[64,32] = vexVVVV_XmmReg[64,32] f* m[64,32];\n XmmReg1[96,32] = vexVVVV_XmmReg[96,32] f* m[96,32];\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MULPS 4-149 PAGE 1269 LINE 65815\n:VMULPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal m:32 = YmmReg2_m256;\n YmmReg1[0,32] = vexVVVV_YmmReg[0,32] f* m[0,32];\n YmmReg1[32,32] = vexVVVV_YmmReg[32,32] f* m[32,32];\n YmmReg1[64,32] = vexVVVV_YmmReg[64,32] f* m[64,32];\n YmmReg1[96,32] = vexVVVV_YmmReg[96,32] f* m[96,32];\n YmmReg1[128,32] = vexVVVV_YmmReg[128,32] f* m[128,32];\n YmmReg1[160,32] = vexVVVV_YmmReg[160,32] f* m[160,32];\n YmmReg1[192,32] = vexVVVV_YmmReg[192,32] f* m[192,32];\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# MULSD 4-152 PAGE 1272 LINE 65956\n:VMULSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:8 = vexVVVV_XmmReg[0,64] f* XmmReg2_m64[0,64];\n\tZmmReg1 = zext(tmp);\n}\n\n# MULSS 4-154 PAGE 1274 LINE 66052\n:VMULSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:4 = vexVVVV_XmmReg[0,32] f* XmmReg2_m32[0,32];\n\tZmmReg1 = zext(tmp);\n}\n\n# ORPD 4-168 PAGE 1288 LINE 66720\ndefine pcodeop vorpd_avx ;\n:VORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ORPD 4-168 PAGE 1288 LINE 66722\n:VORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ORPS 4-171 PAGE 1291 LINE 66846\ndefine pcodeop vorps_avx ;\n:VORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vorps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ORPS 4-171 PAGE 1291 LINE 66848\n:VORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vorps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67302\ndefine pcodeop vpabsb_avx ;\n:VPABSB XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpabsb_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67305\ndefine pcodeop vpabsw_avx ;\n:VPABSW XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpabsw_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67308\ndefine pcodeop vpabsd_avx ;\n:VPABSD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpabsd_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67629\ndefine pcodeop vpacksswb_avx ;\n:VPACKSSWB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpacksswb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67633\ndefine pcodeop vpackssdw_avx ;\n:VPACKSSDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpackssdw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKUSDW 4-194 PAGE 1314 LINE 68086\ndefine pcodeop vpackusdw_avx ;\n:VPACKUSDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpackusdw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKUSWB 4-199 PAGE 1319 LINE 68366\ndefine pcodeop vpackuswb_avx ;\n:VPACKUSWB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpackuswb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68658\ndefine pcodeop vpaddb_avx ;\n:VPADDB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68660\ndefine pcodeop vpaddw_avx ;\n:VPADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68662\ndefine pcodeop vpaddd_avx ;\n:VPADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68664\ndefine pcodeop vpaddq_avx ;\n:VPADDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69040\ndefine pcodeop vpaddsb_avx ;\n:VPADDSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69042\ndefine pcodeop vpaddsw_avx ;\n:VPADDSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69257\ndefine pcodeop vpaddusb_avx ;\n:VPADDUSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddusb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69260\ndefine pcodeop vpaddusw_avx ;\n:VPADDUSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpaddusw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PALIGNR 4-219 PAGE 1339 LINE 69485\ndefine pcodeop vpalignr_avx ;\n:VPALIGNR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpalignr_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PAND 4-223 PAGE 1343 LINE 69678\ndefine pcodeop vpand_avx ;\n:VPAND XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpand_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69854\ndefine pcodeop vpandn_avx ;\n:VPANDN XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpandn_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70085\ndefine pcodeop vpavgb_avx ;\n:VPAVGB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpavgb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70088\ndefine pcodeop vpavgw_avx ;\n:VPAVGW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpavgw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PBLENDVB 4-234 PAGE 1354 LINE 70296\ndefine pcodeop vpblendvb_avx ;\n:VPBLENDVB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4\n{\n\tlocal tmp:16 = vpblendvb_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PBLENDW 4-238 PAGE 1358 LINE 70522\ndefine pcodeop vpblendw_avx ;\n:VPBLENDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpblendw_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70821\ndefine pcodeop vpcmpeqb_avx ;\n:VPCMPEQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x74; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpeqb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70824\ndefine pcodeop vpcmpeqw_avx ;\n:VPCMPEQW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpeqw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70827\ndefine pcodeop vpcmpeqd_avx ;\n:VPCMPEQD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpeqd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPESTRI 4-253 PAGE 1373 LINE 71311\ndefine pcodeop vpcmpestri_avx ;\n:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x61; XmmReg1 ... & XmmReg2_m128; imm8\n{\n\tvpcmpestri_avx( XmmReg1, XmmReg2_m128, imm8:1 );\n\t# TODO missing destination or side effects\n}\n\n# PCMPESTRM 4-255 PAGE 1375 LINE 71395\ndefine pcodeop vpcmpestrm_avx ;\n:VPCMPESTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x60; XmmReg1 ... & XmmReg2_m128; imm8\n{\n\tvpcmpestrm_avx( XmmReg1, XmmReg2_m128, imm8:1 );\n\t# TODO missing destination or side effects\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71499\ndefine pcodeop vpcmpgtb_avx ;\n:VPCMPGTB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpgtb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71502\ndefine pcodeop vpcmpgtw_avx ;\n:VPCMPGTW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpgtw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71505\ndefine pcodeop vpcmpgtd_avx ;\n:VPCMPGTD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpgtd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTQ 4-263 PAGE 1383 LINE 71833\ndefine pcodeop vpcmpgtq_avx ;\n:VPCMPGTQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x37; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpcmpgtq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPISTRI 4-266 PAGE 1386 LINE 71966\ndefine pcodeop vpcmpistri_avx ;\n:VPCMPISTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x63; XmmReg1 ... & XmmReg2_m128; imm8\n{\n\tvpcmpistri_avx( XmmReg1, XmmReg2_m128, imm8:1 );\n\t# TODO missing destination or side effects\n}\n\n# PCMPISTRM 4-268 PAGE 1388 LINE 72052\ndefine pcodeop vpcmpistrm_avx ;\n:VPCMPISTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x62; XmmReg1 ... & XmmReg2_m128; imm8\n{\n\tvpcmpistrm_avx( XmmReg1, XmmReg2_m128, imm8:1 );\n\t# TODO missing destination or side effects\n}\n\n# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72322\ndefine pcodeop vpextrb_avx ;\n:VPEXTRB Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8\n{\n\tlocal tmp8:1 = imm8;\n\tlocal tmp = XmmReg1 >> (tmp8[0,3]*8);\n\tRmr32 = zext(tmp[0,8]);\n\tbuild check_Rmr32_dest;\n}\n\n:VPEXTRB m8, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; (XmmReg1 ... & m8); imm8\n{\n\tlocal tmp8:1 = imm8;\n\tlocal tmp = XmmReg1 >> (tmp8[0,3]*8);\n\tm8 = tmp[0,8];\n}\n\n# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72326\ndefine pcodeop vpextrd_avx ;\n:VPEXTRD Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*32);\n\tRmr32 = tmp(0);\n\tbuild check_Rmr32_dest;\n}\n\n:VPEXTRD m32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & m32; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*32);\n\tm32 = tmp(0);\n}\n\n# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72330\ndefine pcodeop vpextrq_avx ;\n@ifdef IA64\n:VPEXTRQ rm64, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8\n{\n\trm64 = vpextrq_avx( XmmReg1, imm8:1 );\n}\n@endif\n\n# PEXTRW 4-277 PAGE 1397 LINE 72478\ndefine pcodeop vpextrw_avx ;\n:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8\n{\n\tReg32 = vpextrw_avx( XmmReg2, imm8:1 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# PEXTRW 4-277 PAGE 1397 LINE 72483\n:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8\n{\n\tReg32_m16 = vpextrw_avx( XmmReg1, imm8:1 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72627\ndefine pcodeop vphaddw_avx ;\n:VPHADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x01; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72630\ndefine pcodeop vphaddd_avx ;\n:VPHADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x02; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHADDSW 4-284 PAGE 1404 LINE 72821\ndefine pcodeop vphaddsw_avx ;\n:VPHADDSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphaddsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHMINPOSUW 4-286 PAGE 1406 LINE 72939\ndefine pcodeop vphminposuw_avx ;\n:VPHMINPOSUW XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x41; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphminposuw_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73032\ndefine pcodeop vphsubw_avx ;\n:VPHSUBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x05; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphsubw_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73035\ndefine pcodeop vphsubd_avx ;\n:VPHSUBD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x06; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphsubd_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHSUBSW 4-291 PAGE 1411 LINE 73197\ndefine pcodeop vphsubsw_avx ;\n:VPHSUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x07; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vphsubsw_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73321\ndefine pcodeop vpinsrb_avx ;\n:VPINSRB XmmReg1, vexVVVV_XmmReg, Reg32_m8, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x20; (XmmReg1 & ZmmReg1) ... & Reg32_m8; imm8\n{\n\tlocal tmp:16 = vpinsrb_avx( vexVVVV_XmmReg, Reg32_m8, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324\ndefine pcodeop vpinsrd_avx ;\n:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8\n{\n\tlocal tmp:16 = vpinsrd_avx( vexVVVV_XmmReg, rm32, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327\ndefine pcodeop vpinsrq_avx ;\n@ifdef IA64\n:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8\n{\n\tlocal tmp:16 = vpinsrq_avx( vexVVVV_XmmReg, rm64, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# PINSRW 4-296 PAGE 1416 LINE 73446\ndefine pcodeop vpinsrw_avx ;\n:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8\n{\n\tlocal tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMADDUBSW 4-298 PAGE 1418 LINE 73552\ndefine pcodeop vpmaddubsw_avx ;\n:VPMADDUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaddubsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMADDWD 4-301 PAGE 1421 LINE 73700\ndefine pcodeop vpmaddwd_avx ;\n:VPMADDWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaddwd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73882\ndefine pcodeop vpmaxsb_avx ;\n:VPMAXSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaxsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73885\ndefine pcodeop vpmaxsw_avx ;\n:VPMAXSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaxsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73888\ndefine pcodeop vpmaxsd_avx ;\n:VPMAXSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaxsd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74283\ndefine pcodeop vpmaxub_avx ;\n:VPMAXUB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaxub_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74286\ndefine pcodeop vpmaxuw_avx ;\n:VPMAXUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaxuw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74534\ndefine pcodeop vpmaxud_avx ;\n:VPMAXUD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmaxud_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74736\ndefine pcodeop vpminsb_avx ;\n:VPMINSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpminsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74739\ndefine pcodeop vpminsw_avx ;\n:VPMINSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpminsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74989\ndefine pcodeop vpminsd_avx ;\n:VPMINSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpminsd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75195\ndefine pcodeop vpminub_avx ;\n:VPMINUB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpminub_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75198\ndefine pcodeop vpminuw_avx ;\n:VPMINUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpminuw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75445\ndefine pcodeop vpminud_avx ;\n:VPMINUD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpminud_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75770\ndefine pcodeop vpmovsxbw_avx ;\n:VPMOVSXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vpmovsxbw_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75772\ndefine pcodeop vpmovsxbd_avx ;\n:VPMOVSXBD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vpmovsxbd_avx( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75774\ndefine pcodeop vpmovsxbq_avx ;\n:VPMOVSXBQ XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x22; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tlocal tmp:16 = vpmovsxbq_avx( XmmReg2_m16 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75776\ndefine pcodeop vpmovsxwd_avx ;\n:VPMOVSXWD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x23; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vpmovsxwd_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75778\ndefine pcodeop vpmovsxwq_avx ;\n:VPMOVSXWQ XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x24; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vpmovsxwq_avx( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75780\ndefine pcodeop vpmovsxdq_avx ;\n:VPMOVSXDQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vpmovsxdq_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76285\ndefine pcodeop vpmovzxbw_avx ;\n:VPMOVZXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x30; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vpmovzxbw_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76288\ndefine pcodeop vpmovzxbd_avx ;\n:VPMOVZXBD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x31; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vpmovzxbd_avx( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76291\ndefine pcodeop vpmovzxbq_avx ;\n:VPMOVZXBQ XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x32; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tlocal tmp:16 = vpmovzxbq_avx( XmmReg2_m16 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76294\ndefine pcodeop vpmovzxwd_avx ;\n:VPMOVZXWD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x33; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vpmovzxwd_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76297\ndefine pcodeop vpmovzxwq_avx ;\n:VPMOVZXWQ XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x34; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vpmovzxwq_avx( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76301\ndefine pcodeop vpmovzxdq_avx ;\n:VPMOVZXDQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x35; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vpmovzxdq_avx( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULDQ 4-359 PAGE 1479 LINE 76788\ndefine pcodeop vpmuldq_avx ;\n:VPMULDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmuldq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULHRSW 4-362 PAGE 1482 LINE 76928\ndefine pcodeop vpmulhrsw_avx ;\n:VPMULHRSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmulhrsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULHUW 4-366 PAGE 1486 LINE 77141\ndefine pcodeop vpmulhuw_avx ;\n:VPMULHUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmulhuw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULHW 4-370 PAGE 1490 LINE 77370\ndefine pcodeop vpmulhw_avx ;\n:VPMULHW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmulhw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77576\ndefine pcodeop vpmulld_avx ;\n:VPMULLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmulld_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULLW 4-378 PAGE 1498 LINE 77775\ndefine pcodeop vpmullw_avx ;\n:VPMULLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmullw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULUDQ 4-382 PAGE 1502 LINE 77969\ndefine pcodeop vpmuludq_avx ;\n:VPMULUDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpmuludq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# POR 4-399 PAGE 1519 LINE 78850\ndefine pcodeop vpor_avx ;\n:VPOR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpor_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSADBW 4-408 PAGE 1528 LINE 79240\ndefine pcodeop vpsadbw_avx ;\n:VPSADBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsadbw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFB 4-412 PAGE 1532 LINE 79460\ndefine pcodeop vpshufb_avx ;\n:VPSHUFB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpshufb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFD 4-416 PAGE 1536 LINE 79651\ndefine pcodeop vpshufd_avx ;\n:VPSHUFD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpshufd_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFHW 4-420 PAGE 1540 LINE 79857\ndefine pcodeop vpshufhw_avx ;\n:VPSHUFHW XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpshufhw_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFLW 4-423 PAGE 1543 LINE 80032\ndefine pcodeop vpshuflw_avx ;\n:VPSHUFLW XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpshuflw_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80269\ndefine pcodeop vpsignb_avx ;\n:VPSIGNB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsignb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80272\ndefine pcodeop vpsignw_avx ;\n:VPSIGNW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x09; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsignw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80275\ndefine pcodeop vpsignd_avx ;\n:VPSIGND XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsignd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLDQ 4-431 PAGE 1551 LINE 80485\ndefine pcodeop vpslldq_avx ;\n:VPSLLDQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=7 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpslldq_avx( XmmReg2, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80620\ndefine pcodeop vpsllw_avx ;\n:VPSLLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsllw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80623\n:VPSLLW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsllw_avx( XmmReg2, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80626\ndefine pcodeop vpslld_avx ;\n:VPSLLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpslld_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80629\n:VPSLLD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpslld_avx( XmmReg2, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80632\ndefine pcodeop vpsllq_avx ;\n:VPSLLQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsllq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80635\n:VPSLLQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsllq_avx( XmmReg2, imm8:1 );\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81305\ndefine pcodeop vpsraw_avx ;\n:VPSRAW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsraw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81308\n:VPSRAW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=4 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsraw_avx( XmmReg2, imm8:1 );\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81311\ndefine pcodeop vpsrad_avx ;\n:VPSRAD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsrad_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81314\n:VPSRAD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=4 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsrad_avx( XmmReg2, imm8:1 );\n}\n\n# PSRLDQ 4-455 PAGE 1575 LINE 81873\ndefine pcodeop vpsrldq_avx ;\n:VPSRLDQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=3 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsrldq_avx( XmmReg2, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82012\ndefine pcodeop vpsrlw_avx ;\n:VPSRLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsrlw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82015\n:VPSRLW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsrlw_avx( XmmReg2, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82018\ndefine pcodeop vpsrld_avx ;\n:VPSRLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsrld_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82021\n:VPSRLD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsrld_avx( XmmReg2, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82024\ndefine pcodeop vpsrlq_avx ;\n:VPSRLQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsrlq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82027\n:VPSRLQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8\n{\n\tvexVVVV_XmmReg = vpsrlq_avx( XmmReg2, imm8:1 );\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82689\ndefine pcodeop vpsubb_avx ;\n:VPSUBB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82691\ndefine pcodeop vpsubw_avx ;\n:VPSUBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82694\ndefine pcodeop vpsubd_avx ;\n:VPSUBD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBQ 4-476 PAGE 1596 LINE 83101\ndefine pcodeop vpsubq_avx ;\n:VPSUBQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83258\ndefine pcodeop vpsubsb_avx ;\n:VPSUBSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83261\ndefine pcodeop vpsubsw_avx ;\n:VPSUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83498\ndefine pcodeop vpsubusb_avx ;\n:VPSUBUSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubusb_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83501\ndefine pcodeop vpsubusw_avx ;\n:VPSUBUSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsubusw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PTEST 4-487 PAGE 1607 LINE 83728\ndefine pcodeop vptest_avx ;\n:VPTEST XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x17; XmmReg1 ... & XmmReg2_m128\n{\n\tlocal val1 = XmmReg2_m128;\n\tlocal val2 = XmmReg1;\n\tZF = (val1 & val2) == 0;\n\tCF = (val1 & ~val2) == 0;\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# PTEST 4-487 PAGE 1607 LINE 83730\n:VPTEST YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x17; YmmReg1 ... & YmmReg2_m256\n{\n\tlocal val1 = YmmReg2_m256;\n\tlocal val2 = YmmReg1;\n\tZF = (val1 & val2) == 0;\n\tCF = (val1 & ~val2) == 0;\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83929\ndefine pcodeop vpunpckhbw_avx ;\n:VPUNPCKHBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpckhbw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83932\ndefine pcodeop vpunpckhwd_avx ;\n:VPUNPCKHWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpckhwd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83935\ndefine pcodeop vpunpckhdq_avx ;\n:VPUNPCKHDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpckhdq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83938\ndefine pcodeop vpunpckhqdq_avx ;\n:VPUNPCKHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpckhqdq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84529\ndefine pcodeop vpunpcklbw_avx ;\n:VPUNPCKLBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpcklbw_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84532\ndefine pcodeop vpunpcklwd_avx ;\n:VPUNPCKLWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpcklwd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84535\ndefine pcodeop vpunpckldq_avx ;\n:VPUNPCKLDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpckldq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84538\ndefine pcodeop vpunpcklqdq_avx ;\n:VPUNPCKLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpunpcklqdq_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85495\n:VPXOR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vexVVVV_XmmReg ^ XmmReg2_m128;\n\tZmmReg1 = zext(tmp);\n}\n\n# RCPPS 4-526 PAGE 1646 LINE 85950\ndefine pcodeop vrcpps_avx ;\n:VRCPPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x53; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vrcpps_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# RCPPS 4-526 PAGE 1646 LINE 85953\n:VRCPPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x53; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vrcpps_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# RCPSS 4-528 PAGE 1648 LINE 86052\ndefine pcodeop vrcpss_avx ;\n:VRCPSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x53; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vrcpss_avx( vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ROUNDPD 4-564 PAGE 1684 LINE 87791\ndefine pcodeop vroundpd_avx ;\n:VROUNDPD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x09; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vroundpd_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ROUNDPD 4-564 PAGE 1684 LINE 87795\n:VROUNDPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x09; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vroundpd_avx( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ROUNDPS 4-567 PAGE 1687 LINE 87934\ndefine pcodeop vroundps_avx ;\n:VROUNDPS XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vroundps_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ROUNDPS 4-567 PAGE 1687 LINE 87938\n:VROUNDPS YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vroundps_avx( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ROUNDSD 4-570 PAGE 1690 LINE 88058\ndefine pcodeop vroundsd_avx ;\n:VROUNDSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8\n{\n\tlocal tmp:16 = vroundsd_avx( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# ROUNDSS 4-572 PAGE 1692 LINE 88145\ndefine pcodeop vroundss_avx ;\n:VROUNDSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8\n{\n\tlocal tmp:16 = vroundss_avx( vexVVVV_XmmReg, XmmReg2_m32, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# RSQRTPS 4-576 PAGE 1696 LINE 88301\ndefine pcodeop vrsqrtps_avx ;\n:VRSQRTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vrsqrtps_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# RSQRTPS 4-576 PAGE 1696 LINE 88304\n:VRSQRTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x52; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vrsqrtps_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# RSQRTSS 4-578 PAGE 1698 LINE 88399\ndefine pcodeop vrsqrtss_avx ;\n:VRSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vrsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SHUFPD 4-617 PAGE 1737 LINE 90223\ndefine pcodeop vshufpd_avx ;\n:VSHUFPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vshufpd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SHUFPD 4-617 PAGE 1737 LINE 90227\n:VSHUFPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vshufpd_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SHUFPS 4-622 PAGE 1742 LINE 90483\ndefine pcodeop vshufps_avx ;\n:VSHUFPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vshufps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SHUFPS 4-622 PAGE 1742 LINE 90486\n:VSHUFPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vshufps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SQRTPD 4-632 PAGE 1752 LINE 91001\ndefine pcodeop vsqrtpd_avx ;\n:VSQRTPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vsqrtpd_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SQRTPD 4-632 PAGE 1752 LINE 91004\n:VSQRTPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vsqrtpd_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SQRTPS 4-635 PAGE 1755 LINE 91133\ndefine pcodeop vsqrtps_avx ;\n:VSQRTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vsqrtps_avx( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SQRTPS 4-635 PAGE 1755 LINE 91136\n:VSQRTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vsqrtps_avx( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SQRTSD 4-638 PAGE 1758 LINE 91272\ndefine pcodeop vsqrtsd_avx ;\n:VSQRTSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vsqrtsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SQRTSS 4-640 PAGE 1760 LINE 91367\ndefine pcodeop vsqrtss_avx ;\n:VSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# STMXCSR 4-647 PAGE 1767 LINE 91697\ndefine pcodeop vstmxcsr_avx ;\n:VSTMXCSR m32 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0xAE; reg_opcode=3 ... & m32\n{\n\tm32 = vstmxcsr_avx( );\n}\n\n# SUBPD 4-656 PAGE 1776 LINE 92116\ndefine pcodeop vsubpd_avx ;\n:VSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SUBPD 4-656 PAGE 1776 LINE 92118\n:VSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SUBPS 4-659 PAGE 1779 LINE 92265\ndefine pcodeop vsubps_avx ;\n:VSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SUBPS 4-659 PAGE 1779 LINE 92267\n:VSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# SUBSD 4-662 PAGE 1782 LINE 92419\n:VSUBSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:8 = vexVVVV_XmmReg[0,64] f- XmmReg2_m64[0,64];\n\tZmmReg1 = zext(tmp);\n}\n\n# SUBSS 4-664 PAGE 1784 LINE 92512\n:VSUBSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:4 = vexVVVV_XmmReg[0,32] f- XmmReg2_m32[0,32];\n\tZmmReg1 = zext(tmp);\n}\n\n# UCOMISD 4-683 PAGE 1803 LINE 93421\n:VUCOMISD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2E; XmmReg1 ... & XmmReg2_m64\n{\n\tval1:8 = XmmReg1[0,64];\n\tval2:8 = XmmReg2_m64[0,64];\n\tfucompe(val1, val2);\n}\n\n# UCOMISS 4-685 PAGE 1805 LINE 93504\n:VUCOMISS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2E; XmmReg1 ... & XmmReg2_m32\n{\n\tval1:4 = XmmReg1[0,32];\n\tval2:4 = XmmReg2_m32[0,32];\n\tfucompe(val1, val2);\n}\n\n# UNPCKHPD 4-688 PAGE 1808 LINE 93623\ndefine pcodeop vunpckhpd_avx ;\n:VUNPCKHPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vunpckhpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKHPD 4-688 PAGE 1808 LINE 93626\n:VUNPCKHPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vunpckhpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKHPS 4-692 PAGE 1812 LINE 93807\ndefine pcodeop vunpckhps_avx ;\n:VUNPCKHPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vunpckhps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKHPS 4-692 PAGE 1812 LINE 93810\n:VUNPCKHPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vunpckhps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKLPD 4-696 PAGE 1816 LINE 94039\ndefine pcodeop vunpcklpd_avx ;\n:VUNPCKLPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vunpcklpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKLPD 4-696 PAGE 1816 LINE 94042\n:VUNPCKLPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vunpcklpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKLPS 4-700 PAGE 1820 LINE 94225\ndefine pcodeop vunpcklps_avx ;\n:VUNPCKLPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vunpcklps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# UNPCKLPS 4-700 PAGE 1820 LINE 94228\n:VUNPCKLPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vunpcklps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94909\n:VBROADCASTSS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal val:4 = XmmReg2_m32[0,32];\n\tXmmReg1[0,32] = val;\n\tXmmReg1[32,32] = val;\n\tXmmReg1[64,32] = val;\n\tXmmReg1[96,32] = val;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94911\n:VBROADCASTSS YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal val:4 = XmmReg2_m32[0,32];\n\tYmmReg1[0,32] = val;\n\tYmmReg1[32,32] = val;\n\tYmmReg1[64,32] = val;\n\tYmmReg1[96,32] = val;\n\tYmmReg1[128,32] = val;\n\tYmmReg1[160,32] = val;\n\tYmmReg1[192,32] = val;\n\tYmmReg1[224,32] = val;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94913\n:VBROADCASTSD YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal val:8 = XmmReg2_m64[0,64];\n\tYmmReg1[0,64] = val;\n\tYmmReg1[64,64] = val;\n\tYmmReg1[128,64] = val;\n\tYmmReg1[192,64] = val;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94915\n:VBROADCASTF128 YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal val:16 = XmmReg2_m128;\n\tYmmReg1[0,128] = val;\n\tYmmReg1[128,128] = val;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99102\n:VEXTRACTF128 XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x19; (YmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128; imm8\n{\n\tlocal ext:1 = (imm8:1 & 1) == 1;\n\t\n\tlocal val:16 = YmmReg1[0,128];\n\t\n\tif (ext == 0) goto ;\n\n val = YmmReg1[128,128];\n \n \n XmmReg2_m128 = val;\n\tbuild XmmReg2_m128_extend;\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109703\n:VINSERTF128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal ext:1 = (imm8:1 & 1) == 1;\n local src1_0 = vexVVVV_YmmReg[0, 128];\n local src1_1 = vexVVVV_YmmReg[128, 128];\n \n src2:16 = XmmReg2_m128;\n \n\tYmmReg1[0,128] = src2;\n\tYmmReg1[128,128] = src1_1;\n\t\n\tif (ext == 0) goto ;\n\n\tYmmReg1[0,128] = src1_0;\n\tYmmReg1[128,128] = src2;\n\n \t\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110151\ndefine pcodeop vmaskmovps_avx ;\n:VMASKMOVPS XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & m128\n{\n\tlocal tmp:16 = vmaskmovps_avx( vexVVVV_XmmReg, m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110154\n:VMASKMOVPS YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & m256\n{\n\tlocal tmp:32 = vmaskmovps_avx( vexVVVV_YmmReg, m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110157\ndefine pcodeop vmaskmovpd_avx ;\n:VMASKMOVPD XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & m128\n{\n\tlocal tmp:16 = vmaskmovpd_avx( vexVVVV_XmmReg, m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110160\n:VMASKMOVPD YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2D; (YmmReg1 & ZmmReg1) ... & m256\n{\n\tlocal tmp:32 = vmaskmovpd_avx( vexVVVV_YmmReg, m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110163\n:VMASKMOVPS m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2E; XmmReg1 ... & m128\n{\n\tm128 = vmaskmovps_avx( vexVVVV_XmmReg, XmmReg1 );\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110166\n:VMASKMOVPS m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2E; YmmReg1 ... & m256\n{\n\tm256 = vmaskmovps_avx( vexVVVV_YmmReg, YmmReg1 );\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110168\n:VMASKMOVPD m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2F; XmmReg1 ... & m128\n{\n\tm128 = vmaskmovpd_avx( vexVVVV_XmmReg, XmmReg1 );\n}\n\n# VMASKMOV 5-318 PAGE 2142 LINE 110171\n:VMASKMOVPD m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2F; YmmReg1 ... & m256\n{\n\tm256 = vmaskmovpd_avx( vexVVVV_YmmReg, YmmReg1 );\n}\n\n# VPERM2F128 5-358 PAGE 2182 LINE 112216\ndefine pcodeop vperm2f128_avx ;\n:VPERM2F128 YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x06; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vperm2f128_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112860\ndefine pcodeop vpermilpd_avx ;\n:VPERMILPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpermilpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112863\n:VPERMILPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpermilpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112875\n:VPERMILPD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x05; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpermilpd_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112877\n:VPERMILPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x05; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpermilpd_avx( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113158\ndefine pcodeop vpermilps_avx ;\n:VPERMILPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpermilps_avx( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113161\n:VPERMILPS XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpermilps_avx( XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113164\n:VPERMILPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpermilps_avx( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113167\n:VPERMILPS YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpermilps_avx( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122257\ndefine pcodeop vtestps_avx ;\n:VTESTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0E; XmmReg1 ... & XmmReg2_m128\n{\n\tlocal val1 = XmmReg2_m128;\n\tlocal val2 = XmmReg1;\n\tlocal ztest = val1 & val2;\n\tZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1]) == 0;\n\tlocal ctest = val1 & ~val2;\n\tCF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1]) == 0;\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122260\n:VTESTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0E; YmmReg1 ... & YmmReg2_m256\n{\n\tlocal val1 = YmmReg2_m256;\n\tlocal val2 = YmmReg1;\n\tlocal ztest = val1 & val2;\n\tZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1] | ztest[160,1] | ztest[191,1] | ztest[224,1] | ztest[255,1]) == 0;\n\tlocal ctest = val1 & ~val2;\n\tCF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1] | ctest[160,1] | ctest[191,1] | ctest[224,1] | ctest[255,1]) == 0;\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122263\ndefine pcodeop vtestpd_avx ;\n:VTESTPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0F; XmmReg1 ... & XmmReg2_m128\n{\n\tlocal val1 = XmmReg2_m128;\n\tlocal val2 = XmmReg1;\n\tlocal ztest = val1 & val2;\n\tZF = (ztest[63,1] | ztest[127,1]) == 0;\n\tlocal ctest = val1 & ~val2;\n\tCF = (ctest[63,1] | ctest[127,1]) == 0;\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122266\n:VTESTPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0F; YmmReg1 ... & YmmReg2_m256\n{\n\tlocal val1 = YmmReg2_m256;\n\tlocal val2 = YmmReg1;\n\tlocal ztest = val1 & val2;\n\tZF = (ztest[63,1] | ztest[127,1] | ztest[191,1] | ztest[255,1]) == 0;\n\tlocal ctest = val1 & ~val2;\n\tCF = (ctest[63,1] | ctest[127,1] | ctest[191,1] | ctest[255,1]) == 0;\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# XORPD 5-596 PAGE 2420 LINE 123828\n:VXORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\ttmp:16 = XmmReg2_m128;\n XmmReg1[0,64] = ( vexVVVV_XmmReg[0,64] ^ tmp[0,64] );\n XmmReg1[64,64] = ( vexVVVV_XmmReg[64,64] ^ tmp[64,64] );\n ZmmReg1 = zext(XmmReg1);\n}\n\n# XORPD 5-596 PAGE 2420 LINE 123831\n:VXORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\ttmp:32 = YmmReg2_m256;\n YmmReg1[0,64] = ( vexVVVV_YmmReg[0,64] ^ tmp[0,64] );\n YmmReg1[64,64] = ( vexVVVV_YmmReg[64,64] ^ tmp[64,64] );\n YmmReg1[128,64] = ( vexVVVV_YmmReg[128,64] ^ tmp[128,64] );\n YmmReg1[192,64] = ( vexVVVV_YmmReg[192,64] ^ tmp[192,64] );\n ZmmReg1 = zext(YmmReg1);\n}\n\n# XORPS 5-599 PAGE 2423 LINE 123953\n:VXORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\ttmp:16 = XmmReg2_m128;\n XmmReg1[0,32] = ( vexVVVV_XmmReg[0,32] ^ tmp[0,32] );\n XmmReg1[32,32] = ( vexVVVV_XmmReg[32,32] ^ tmp[32,32] );\n XmmReg1[64,32] = ( vexVVVV_XmmReg[64,32] ^ tmp[64,32] );\n XmmReg1[96,32] = ( vexVVVV_XmmReg[96,32] ^ tmp[96,32] );\n ZmmReg1 = zext(XmmReg1);\n}\n\n# XORPS 5-599 PAGE 2423 LINE 123956\n:VXORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\ttmp:32 = YmmReg2_m256;\n YmmReg1[0,32] = ( vexVVVV_YmmReg[0,32] ^ tmp[0,32] );\n YmmReg1[32,32] = ( vexVVVV_YmmReg[32,32] ^ tmp[32,32] );\n YmmReg1[64,32] = ( vexVVVV_YmmReg[64,32] ^ tmp[64,32] );\n YmmReg1[96,32] = ( vexVVVV_YmmReg[96,32] ^ tmp[96,32] );\n YmmReg1[128,32] = ( vexVVVV_YmmReg[128,32] ^ tmp[128,32] );\n YmmReg1[160,32] = ( vexVVVV_YmmReg[160,32] ^ tmp[160,32] );\n YmmReg1[192,32] = ( vexVVVV_YmmReg[192,32] ^ tmp[192,32] );\n YmmReg1[224,32] = ( vexVVVV_YmmReg[224,32] ^ tmp[224,32] ); \n ZmmReg1 = zext(YmmReg1);\n}\n\n# INFO This file automatically generated by andre on Tue Apr 30 16:08:43 2024\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['--cpuid-match', 'F16C', '--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx_manual.sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/ia.sinc']\n\n# VCVTPH2PS 5-34 PAGE 1858 LINE 95957\ndefine pcodeop vcvtph2ps_f16c ;\n:VCVTPH2PS XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vcvtph2ps_f16c( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VCVTPH2PS 5-34 PAGE 1858 LINE 95960\n:VCVTPH2PS YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vcvtph2ps_f16c( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96110\ndefine pcodeop vcvtps2ph_f16c ;\n:VCVTPS2PH XmmReg2_m64, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x1D; XmmReg1 ... & XmmReg2_m64; imm8\n{\n\tXmmReg2_m64 = vcvtps2ph_f16c( XmmReg1, imm8:1 );\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96113\n:VCVTPS2PH XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x1D; (YmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128; imm8\n{\n\tXmmReg2_m128 = vcvtps2ph_f16c( YmmReg1, imm8:1 );\n\tbuild XmmReg2_m128_extend;\n}\n\n\n" }, { "path": "pypcode/processors/x86/data/languages/avx2.sinc", "content": "# INFO This file automatically generated by andre on Tue Apr 30 16:10:11 2024\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['--cpuid-match', 'AVX2', '--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx2_manual.sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/ia.sinc']\n\n# MOVNTDQA 4-92 PAGE 1212 LINE 63086\ndefine pcodeop vmovntdqa_avx2 ;\n:VMOVNTDQA YmmReg1, m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x2A; (YmmReg1 & ZmmReg1) ... & m256\n{\n\tlocal tmp:32 = vmovntdqa_avx2( m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MPSADBW 4-136 PAGE 1256 LINE 65140\ndefine pcodeop vmpsadbw_avx2 ;\n:VMPSADBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vmpsadbw_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67311\ndefine pcodeop vpabsb_avx2 ;\n:VPABSB YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpabsb_avx2( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67314\ndefine pcodeop vpabsw_avx2 ;\n:VPABSW YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpabsw_avx2( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67317\ndefine pcodeop vpabsd_avx2 ;\n:VPABSD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpabsd_avx2( YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67637\ndefine pcodeop vpacksswb_avx2 ;\n:VPACKSSWB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpacksswb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67641\ndefine pcodeop vpackssdw_avx2 ;\n:VPACKSSDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpackssdw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKUSDW 4-194 PAGE 1314 LINE 68090\ndefine pcodeop vpackusdw_avx2 ;\n:VPACKUSDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpackusdw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PACKUSWB 4-199 PAGE 1319 LINE 68370\ndefine pcodeop vpackuswb_avx2 ;\n:VPACKUSWB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpackuswb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68666\ndefine pcodeop vpaddb_avx2 ;\n:VPADDB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68668\ndefine pcodeop vpaddw_avx2 ;\n:VPADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68670\ndefine pcodeop vpaddd_avx2 ;\n:VPADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68672\ndefine pcodeop vpaddq_avx2 ;\n:VPADDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69045\ndefine pcodeop vpaddsb_avx2 ;\n:VPADDSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69048\ndefine pcodeop vpaddsw_avx2 ;\n:VPADDSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69263\ndefine pcodeop vpaddusb_avx2 ;\n:VPADDUSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddusb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69266\ndefine pcodeop vpaddusw_avx2 ;\n:VPADDUSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpaddusw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PALIGNR 4-219 PAGE 1339 LINE 69489\ndefine pcodeop vpalignr_avx2 ;\n:VPALIGNR YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpalignr_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PAND 4-223 PAGE 1343 LINE 69680\ndefine pcodeop vpand_avx2 ;\n:VPAND YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpand_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69856\ndefine pcodeop vpandn_avx2 ;\n:VPANDN YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpandn_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70091\ndefine pcodeop vpavgb_avx2 ;\n:VPAVGB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpavgb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70094\ndefine pcodeop vpavgw_avx2 ;\n:VPAVGW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpavgw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PBLENDVB 4-234 PAGE 1354 LINE 70300\ndefine pcodeop vpblendvb_avx2 ;\n:VPBLENDVB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; Ymm_imm8_7_4\n{\n\tlocal tmp:32 = vpblendvb_avx2( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PBLENDW 4-238 PAGE 1358 LINE 70525\ndefine pcodeop vpblendw_avx2 ;\n:VPBLENDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpblendw_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70830\ndefine pcodeop vpcmpeqb_avx2 ;\n:VPCMPEQB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x74; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpeqb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70833\ndefine pcodeop vpcmpeqw_avx2 ;\n:VPCMPEQW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpeqw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70837\ndefine pcodeop vpcmpeqd_avx2 ;\n:VPCMPEQD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpeqd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71508\ndefine pcodeop vpcmpgtb_avx2 ;\n:VPCMPGTB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpgtb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71511\ndefine pcodeop vpcmpgtw_avx2 ;\n:VPCMPGTW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpgtw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71514\ndefine pcodeop vpcmpgtd_avx2 ;\n:VPCMPGTD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpgtd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCMPGTQ 4-263 PAGE 1383 LINE 71835\ndefine pcodeop vpcmpgtq_avx2 ;\n:VPCMPGTQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x37; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpcmpgtq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72633\ndefine pcodeop vphaddw_avx2 ;\n:VPHADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x01; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vphaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72636\ndefine pcodeop vphaddd_avx2 ;\n:VPHADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x02; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vphaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHADDSW 4-284 PAGE 1404 LINE 72824\ndefine pcodeop vphaddsw_avx2 ;\n:VPHADDSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vphaddsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73038\ndefine pcodeop vphsubw_avx2 ;\n:VPHSUBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x05; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vphsubw_avx2( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73041\ndefine pcodeop vphsubd_avx2 ;\n:VPHSUBD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x06; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vphsubd_avx2( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PHSUBSW 4-291 PAGE 1411 LINE 73200\ndefine pcodeop vphsubsw_avx2 ;\n:VPHSUBSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x07; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vphsubsw_avx2( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMADDUBSW 4-298 PAGE 1418 LINE 73555\ndefine pcodeop vpmaddubsw_avx2 ;\n:VPMADDUBSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaddubsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMADDWD 4-301 PAGE 1421 LINE 73704\ndefine pcodeop vpmaddwd_avx2 ;\n:VPMADDWD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaddwd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73891\ndefine pcodeop vpmaxsb_avx2 ;\n:VPMAXSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaxsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73894\ndefine pcodeop vpmaxsw_avx2 ;\n:VPMAXSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaxsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73897\ndefine pcodeop vpmaxsd_avx2 ;\n:VPMAXSD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaxsd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74289\ndefine pcodeop vpmaxub_avx2 ;\n:VPMAXUB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaxub_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74292\ndefine pcodeop vpmaxuw_avx2 ;\n:VPMAXUW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaxuw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74537\ndefine pcodeop vpmaxud_avx2 ;\n:VPMAXUD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmaxud_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74742\ndefine pcodeop vpminsb_avx2 ;\n:VPMINSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpminsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74745\ndefine pcodeop vpminsw_avx2 ;\n:VPMINSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpminsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74992\ndefine pcodeop vpminsd_avx2 ;\n:VPMINSD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpminsd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75201\ndefine pcodeop vpminub_avx2 ;\n:VPMINUB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpminub_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75204\ndefine pcodeop vpminuw_avx2 ;\n:VPMINUW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpminuw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75448\ndefine pcodeop vpminud_avx2 ;\n:VPMINUD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpminud_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75782\ndefine pcodeop vpmovsxbw_avx2 ;\n:VPMOVSXBW YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpmovsxbw_avx2( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75784\ndefine pcodeop vpmovsxbd_avx2 ;\n:VPMOVSXBD YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x21; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:32 = vpmovsxbd_avx2( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75786\ndefine pcodeop vpmovsxbq_avx2 ;\n:VPMOVSXBQ YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x22; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:32 = vpmovsxbq_avx2( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75788\ndefine pcodeop vpmovsxwd_avx2 ;\n:VPMOVSXWD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x23; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpmovsxwd_avx2( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75791\ndefine pcodeop vpmovsxwq_avx2 ;\n:VPMOVSXWQ YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x24; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:32 = vpmovsxwq_avx2( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75793\ndefine pcodeop vpmovsxdq_avx2 ;\n:VPMOVSXDQ YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x25; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpmovsxdq_avx2( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76304\ndefine pcodeop vpmovzxbw_avx2 ;\n:VPMOVZXBW YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x30; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpmovzxbw_avx2( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76306\ndefine pcodeop vpmovzxbd_avx2 ;\n:VPMOVZXBD YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x31; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:32 = vpmovzxbd_avx2( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76309\ndefine pcodeop vpmovzxbq_avx2 ;\n:VPMOVZXBQ YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x32; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:32 = vpmovzxbq_avx2( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76312\ndefine pcodeop vpmovzxwd_avx2 ;\n:VPMOVZXWD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x33; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpmovzxwd_avx2( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76314\ndefine pcodeop vpmovzxwq_avx2 ;\n:VPMOVZXWQ YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x34; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:32 = vpmovzxwq_avx2( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMOVZX 4-350 PAGE 1470 LINE 76317\ndefine pcodeop vpmovzxdq_avx2 ;\n:VPMOVZXDQ YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x35; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpmovzxdq_avx2( XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULDQ 4-359 PAGE 1479 LINE 76791\ndefine pcodeop vpmuldq_avx2 ;\n:VPMULDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmuldq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULHRSW 4-362 PAGE 1482 LINE 76931\ndefine pcodeop vpmulhrsw_avx2 ;\n:VPMULHRSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmulhrsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULHUW 4-366 PAGE 1486 LINE 77144\ndefine pcodeop vpmulhuw_avx2 ;\n:VPMULHUW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmulhuw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULHW 4-370 PAGE 1490 LINE 77373\ndefine pcodeop vpmulhw_avx2 ;\n:VPMULHW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmulhw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77579\ndefine pcodeop vpmulld_avx2 ;\n:VPMULLD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmulld_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULLW 4-378 PAGE 1498 LINE 77778\ndefine pcodeop vpmullw_avx2 ;\n:VPMULLW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmullw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMULUDQ 4-382 PAGE 1502 LINE 77973\ndefine pcodeop vpmuludq_avx2 ;\n:VPMULUDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpmuludq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# POR 4-399 PAGE 1519 LINE 78852\ndefine pcodeop vpor_avx2 ;\n:VPOR YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpor_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSADBW 4-408 PAGE 1528 LINE 79245\ndefine pcodeop vpsadbw_avx2 ;\n:VPSADBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsadbw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFB 4-412 PAGE 1532 LINE 79463\ndefine pcodeop vpshufb_avx2 ;\n:VPSHUFB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpshufb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFD 4-416 PAGE 1536 LINE 79653\ndefine pcodeop vpshufd_avx2 ;\n:VPSHUFD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpshufd_avx2( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFHW 4-420 PAGE 1540 LINE 79860\ndefine pcodeop vpshufhw_avx2 ;\n:VPSHUFHW YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpshufhw_avx2( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSHUFLW 4-423 PAGE 1543 LINE 80035\ndefine pcodeop vpshuflw_avx2 ;\n:VPSHUFLW YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpshuflw_avx2( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80278\ndefine pcodeop vpsignb_avx2 ;\n:VPSIGNB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsignb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80281\ndefine pcodeop vpsignw_avx2 ;\n:VPSIGNW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x09; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsignw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80284\ndefine pcodeop vpsignd_avx2 ;\n:VPSIGND YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsignd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLDQ 4-431 PAGE 1551 LINE 80488\ndefine pcodeop vpslldq_avx2 ;\n:VPSLLDQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=7 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpslldq_avx2( YmmReg2, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80638\ndefine pcodeop vpsllw_avx2 ;\n:VPSLLW YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsllw_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80641\n:VPSLLW vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x71; reg_opcode=6 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsllw_avx2( YmmReg2, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80656\ndefine pcodeop vpslld_avx2 ;\n:VPSLLD YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpslld_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80659\n:VPSLLD vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x72; reg_opcode=6 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpslld_avx2( YmmReg2, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80662\ndefine pcodeop vpsllq_avx2 ;\n:VPSLLQ YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsllq_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80664\n:VPSLLQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=6 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsllq_avx2( YmmReg2, imm8:1 );\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81317\ndefine pcodeop vpsraw_avx2 ;\n:VPSRAW YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsraw_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81320\n:VPSRAW vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x71; reg_opcode=4 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsraw_avx2( YmmReg2, imm8:1 );\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81323\ndefine pcodeop vpsrad_avx2 ;\n:VPSRAD YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsrad_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81326\n:VPSRAD vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x72; reg_opcode=4 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsrad_avx2( YmmReg2, imm8:1 );\n}\n\n# PSRLDQ 4-455 PAGE 1575 LINE 81876\ndefine pcodeop vpsrldq_avx2 ;\n:VPSRLDQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=3 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsrldq_avx2( YmmReg2, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82030\ndefine pcodeop vpsrlw_avx2 ;\n:VPSRLW YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsrlw_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82033\n:VPSRLW vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x71; reg_opcode=2 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsrlw_avx2( YmmReg2, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82048\ndefine pcodeop vpsrld_avx2 ;\n:VPSRLD YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsrld_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82051\n:VPSRLD vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x72; reg_opcode=2 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsrld_avx2( YmmReg2, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82054\ndefine pcodeop vpsrlq_avx2 ;\n:VPSRLQ YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:32 = vpsrlq_avx2( vexVVVV_YmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82056\n:VPSRLQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=2 & (mod=0x3 & YmmReg2); imm8\n{\n\tvexVVVV_YmmReg = vpsrlq_avx2( YmmReg2, imm8:1 );\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82696\ndefine pcodeop vpsubb_avx2 ;\n:VPSUBB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82698\ndefine pcodeop vpsubw_avx2 ;\n:VPSUBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82700\ndefine pcodeop vpsubd_avx2 ;\n:VPSUBD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBQ 4-476 PAGE 1596 LINE 83104\ndefine pcodeop vpsubq_avx2 ;\n:VPSUBQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83264\ndefine pcodeop vpsubsb_avx2 ;\n:VPSUBSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83267\ndefine pcodeop vpsubsw_avx2 ;\n:VPSUBSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83504\ndefine pcodeop vpsubusb_avx2 ;\n:VPSUBUSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubusb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83507\ndefine pcodeop vpsubusw_avx2 ;\n:VPSUBUSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsubusw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83940\ndefine pcodeop vpunpckhbw_avx2 ;\n:VPUNPCKHBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpckhbw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83942\ndefine pcodeop vpunpckhwd_avx2 ;\n:VPUNPCKHWD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpckhwd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83944\ndefine pcodeop vpunpckhdq_avx2 ;\n:VPUNPCKHDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpckhdq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83946\ndefine pcodeop vpunpckhqdq_avx2 ;\n:VPUNPCKHQDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpckhqdq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84541\ndefine pcodeop vpunpcklbw_avx2 ;\n:VPUNPCKLBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpcklbw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84544\ndefine pcodeop vpunpcklwd_avx2 ;\n:VPUNPCKLWD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpcklwd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84547\ndefine pcodeop vpunpckldq_avx2 ;\n:VPUNPCKLDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpckldq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84550\ndefine pcodeop vpunpcklqdq_avx2 ;\n:VPUNPCKLQDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpunpcklqdq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85497\n:VPXOR YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vexVVVV_YmmReg ^ YmmReg2_m256;\n\tZmmReg1 = zext(tmp);\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99432\n:VEXTRACTI128 XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x39; (YmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128; imm8\n{\n\tlocal ext:1 = (imm8:1 & 1) == 1;\n\t\n\tlocal val:16 = YmmReg1[0,128];\n\t\n\tif (ext == 0) goto ;\n\n val = YmmReg1[128,128];\n \n \n XmmReg2_m128 = val;\n\tbuild XmmReg2_m128_extend;\n}\n\n# VPBLENDD 5-321 PAGE 2145 LINE 110309\ndefine pcodeop vpblendd_avx2 ;\n:VPBLENDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x02; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n{\n\tlocal tmp:16 = vpblendd_avx2( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBLENDD 5-321 PAGE 2145 LINE 110312\n:VPBLENDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x02; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpblendd_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110776\n:VPBROADCASTB XmmReg1, XmmReg2_m8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m8\n{\n\tlocal val:1 = XmmReg2_m8[0,8];\n\tXmmReg1[0,8] = val;\n\tXmmReg1[8,8] = val;\n\tXmmReg1[16,8] = val;\n\tXmmReg1[24,8] = val;\n\tXmmReg1[32,8] = val;\n\tXmmReg1[40,8] = val;\n\tXmmReg1[48,8] = val;\n\tXmmReg1[56,8] = val;\n\tXmmReg1[64,8] = val;\n\tXmmReg1[72,8] = val;\n\tXmmReg1[80,8] = val;\n\tXmmReg1[88,8] = val;\n\tXmmReg1[96,8] = val;\n\tXmmReg1[104,8] = val;\n\tXmmReg1[112,8] = val;\n\tXmmReg1[120,8] = val;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110778\n:VPBROADCASTB YmmReg1, XmmReg2_m8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m8\n{\n\tlocal val:1 = XmmReg2_m8[0,8];\n\tYmmReg1[0,8] = val;\n\tYmmReg1[8,8] = val;\n\tYmmReg1[16,8] = val;\n\tYmmReg1[24,8] = val;\n\tYmmReg1[32,8] = val;\n\tYmmReg1[40,8] = val;\n\tYmmReg1[48,8] = val;\n\tYmmReg1[56,8] = val;\n\tYmmReg1[64,8] = val;\n\tYmmReg1[72,8] = val;\n\tYmmReg1[80,8] = val;\n\tYmmReg1[88,8] = val;\n\tYmmReg1[96,8] = val;\n\tYmmReg1[104,8] = val;\n\tYmmReg1[112,8] = val;\n\tYmmReg1[120,8] = val;\n\t\n\tYmmReg1[128,8] = val;\n\tYmmReg1[136,8] = val;\n\tYmmReg1[144,8] = val;\n\tYmmReg1[152,8] = val;\n\tYmmReg1[160,8] = val;\n\tYmmReg1[168,8] = val;\n\tYmmReg1[176,8] = val;\n\tYmmReg1[184,8] = val;\n\tYmmReg1[192,8] = val;\n\tYmmReg1[200,8] = val;\n\tYmmReg1[208,8] = val;\n\tYmmReg1[216,8] = val;\n\tYmmReg1[224,8] = val;\n\tYmmReg1[232,8] = val;\n\tYmmReg1[240,8] = val;\n\tYmmReg1[248,8] = val;\n\t\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110787\n:VPBROADCASTW XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tlocal val:2 = XmmReg2_m16[0,16];\n\tXmmReg1[0,16] = val;\n\tXmmReg1[16,16] = val;\n\tXmmReg1[32,16] = val;\n\tXmmReg1[48,16] = val;\n\tXmmReg1[64,16] = val;\n\tXmmReg1[80,16] = val;\n\tXmmReg1[96,16] = val;\n\tXmmReg1[112,16] = val;\n\t\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110789\n:VPBROADCASTW YmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tlocal val:2 = XmmReg2_m16[0,16];\n\tYmmReg1[0,16] = val;\n\tYmmReg1[16,16] = val;\n\tYmmReg1[32,16] = val;\n\tYmmReg1[48,16] = val;\n\tYmmReg1[64,16] = val;\n\tYmmReg1[80,16] = val;\n\tYmmReg1[96,16] = val;\n\tYmmReg1[112,16] = val;\n\t\n\tYmmReg1[128,16] = val;\n\tYmmReg1[144,16] = val;\n\tYmmReg1[160,16] = val;\n\tYmmReg1[176,16] = val;\n\tYmmReg1[192,16] = val;\n\tYmmReg1[208,16] = val;\n\tYmmReg1[224,16] = val;\n\tYmmReg1[240,16] = val;\n\t\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110800\n:VPBROADCASTD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal val:4 = XmmReg2_m32[0,32];\n\tXmmReg1[0,32] = val;\n\tXmmReg1[32,32] = val;\n\tXmmReg1[64,32] = val;\n\tXmmReg1[96,32] = val;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110802\n:VPBROADCASTD YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal val:4 = XmmReg2_m32[0,32];\n\tYmmReg1[0,32] = val;\n\tYmmReg1[32,32] = val;\n\tYmmReg1[64,32] = val;\n\tYmmReg1[96,32] = val;\n\tYmmReg1[128,32] = val;\n\tYmmReg1[160,32] = val;\n\tYmmReg1[192,32] = val;\n\tYmmReg1[224,32] = val;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110813\n:VPBROADCASTQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal val:8 = XmmReg2_m64[0,64];\n\tXmmReg1[0,64] = val;\n\tXmmReg1[64,64] = val;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110815\n:VPBROADCASTQ YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal val:8 = XmmReg2_m64[0,64];\n\tYmmReg1[0,64] = val;\n\tYmmReg1[64,64] = val;\n\tYmmReg1[128,64] = val;\n\tYmmReg1[192,64] = val;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110843\n:VBROADCASTI128 YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal val:16 = XmmReg2_m128;\n\tYmmReg1[0,128] = val;\n\tYmmReg1[128,128] = val;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VPERM2I128 5-360 PAGE 2184 LINE 112312\ndefine pcodeop vperm2i128_avx2 ;\n:VPERM2I128 YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vperm2i128_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112405\ndefine pcodeop vpermd_avx2 ;\n:VPERMD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpermd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMPD 5-381 PAGE 2205 LINE 113452\ndefine pcodeop vpermpd_avx2 ;\n:VPERMPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x01; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpermpd_avx2( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMPS 5-384 PAGE 2208 LINE 113633\ndefine pcodeop vpermps_avx2 ;\n:VPERMPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpermps_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPERMQ 5-387 PAGE 2211 LINE 113768\ndefine pcodeop vpermq_avx2 ;\n:VPERMQ YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x00; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n{\n\tlocal tmp:32 = vpermq_avx2( YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114262\ndefine pcodeop vpmaskmovd_avx2 ;\n:VPMASKMOVD XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x8C; (XmmReg1 & ZmmReg1) ... & m128\n{\n\tlocal tmp:16 = vpmaskmovd_avx2( vexVVVV_XmmReg, m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114264\n:VPMASKMOVD YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x8C; (YmmReg1 & ZmmReg1) ... & m256\n{\n\tlocal tmp:32 = vpmaskmovd_avx2( vexVVVV_YmmReg, m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114266\ndefine pcodeop vpmaskmovq_avx2 ;\n:VPMASKMOVQ XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x8C; (XmmReg1 & ZmmReg1) ... & m128\n{\n\tlocal tmp:16 = vpmaskmovq_avx2( vexVVVV_XmmReg, m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114268\n:VPMASKMOVQ YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x8C; (YmmReg1 & ZmmReg1) ... & m256\n{\n\tlocal tmp:32 = vpmaskmovq_avx2( vexVVVV_YmmReg, m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114270\n:VPMASKMOVD m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x8E; XmmReg1 ... & m128\n{\n\tm128 = vpmaskmovd_avx2( vexVVVV_XmmReg, XmmReg1 );\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114272\n:VPMASKMOVD m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x8E; YmmReg1 ... & m256\n{\n\tm256 = vpmaskmovd_avx2( vexVVVV_YmmReg, YmmReg1 );\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114274\n:VPMASKMOVQ m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x8E; XmmReg1 ... & m128\n{\n\tm128 = vpmaskmovq_avx2( vexVVVV_XmmReg, XmmReg1 );\n}\n\n# VPMASKMOV 5-397 PAGE 2221 LINE 114276\n:VPMASKMOVQ m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x8E; YmmReg1 ... & m256\n{\n\tm256 = vpmaskmovq_avx2( vexVVVV_YmmReg, YmmReg1 );\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116620\ndefine pcodeop vpsllvd_avx2 ;\n:VPSLLVD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsllvd_avx2( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116623\ndefine pcodeop vpsllvq_avx2 ;\n:VPSLLVQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsllvq_avx2( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116626\n:VPSLLVD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsllvd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116629\n:VPSLLVQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsllvq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116874\ndefine pcodeop vpsravd_avx2 ;\n:VPSRAVD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsravd_avx2( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116877\n:VPSRAVD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsravd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117139\ndefine pcodeop vpsrlvd_avx2 ;\n:VPSRLVD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsrlvd_avx2( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117142\ndefine pcodeop vpsrlvq_avx2 ;\n:VPSRLVQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vpsrlvq_avx2( vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117145\n:VPSRLVD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsrlvd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117148\n:VPSRLVQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:32 = vpsrlvq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/avx2_manual.sinc", "content": "# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785\ndefine pcodeop vinserti128 ;\n:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 {\n\tlocal tmp:16 = XmmReg2_m128;\n\tlocal cond0:16 = zext((imm8_0:1 & 0x1) == 0);\n\tlocal cond1:16 = zext((imm8_0:1 & 0x1) == 1);\n\t# ignoring all but the least significant bit\n\tYmmReg1[0,128] = (cond0 * tmp) + (cond1 * vexVVVV_YmmReg[0,128]);\n\tYmmReg1[128,128] = (cond0 * vexVVVV_YmmReg[128,128]) + (cond1 * tmp);\n\n}\n\n# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903\ndefine pcodeop vgatherdpd ;\n:VGATHERDPD XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & ZmmReg1) ... & q_vm32x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vgatherdpd(XmmReg1, q_vm32x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vgatherdpd(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n\n# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106908\n@ifdef IA64\ndefine pcodeop vgatherqpd ;\n:VGATHERQPD XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & ZmmReg1) ... & q_vm64x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vgatherqpd(XmmReg1, q_vm64x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vgatherqpd(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n@endif\n\n# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106913\n:VGATHERDPD YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x92; (YmmReg1 & ZmmReg1) ... & q_vm32x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tYmmReg1 = vgatherdpd(YmmReg1, q_vm32x, vexVVVV_YmmReg);\n\tYmmReg1 = vgatherdpd(YmmReg1, vexVVVV_YmmReg);\n\tZmmReg1 = zext(YmmReg1);\n\tvexVVVV_YmmReg = 0;\n}\n\n# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106918\n@ifdef IA64\n:VGATHERQPD YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x93; (YmmReg1 & ZmmReg1) ... & q_vm64y {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tYmmReg1 = vgatherqpd(YmmReg1, q_vm64y, vexVVVV_YmmReg);\n\tYmmReg1 = vgatherqpd(YmmReg1, vexVVVV_YmmReg);\n\tZmmReg1 = zext(YmmReg1);\n\tvexVVVV_YmmReg = 0;\n}\n@endif\n\n\n# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107130\ndefine pcodeop vgatherdps ;\n:VGATHERDPS XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & ZmmReg1) ... & d_vm32x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vgatherdps(XmmReg1, d_vm32x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vgatherdps(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n\n# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107135\n@ifdef IA64\ndefine pcodeop vgatherqps ;\n:VGATHERQPS XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & ZmmReg1) ... & d_vm64x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vgatherqps(XmmReg1, d_vm64x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vgatherqps(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n@endif\n\n# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107140\n:VGATHERDPS YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x92; (YmmReg1 & ZmmReg1) ... & d_vm32y {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tYmmReg1 = vgatherdps(YmmReg1, d_vm32y, vexVVVV_YmmReg);\n\tYmmReg1 = vgatherdps(YmmReg1, vexVVVV_YmmReg);\n\tZmmReg1 = zext(YmmReg1);\n\tvexVVVV_YmmReg = 0;\n}\n\n# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107145\n@ifdef IA64\n:VGATHERQPS XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & ZmmReg1) ... & d_vm64y {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vgatherqps(XmmReg1, d_vm64y, vexVVVV_XmmReg);\n\tXmmReg1 = vgatherqps(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(XmmReg1);\n\tvexVVVV_XmmReg = 0;\n}\n@endif\n\n# PCMPEQQ 4-250 PAGE 1370 LINE 71171\n:VPCMPEQQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x29; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal mask:8 = 0xffffffffffffffff;\n\tYmmReg1[0,64] = zext(vexVVVV_YmmReg[0,64] == YmmReg2_m256[0,64]) * mask;\n\tYmmReg1[64,64] = zext(vexVVVV_YmmReg[64,64] == YmmReg2_m256[64,64]) * mask;\n\tYmmReg1[128,64] = zext(vexVVVV_YmmReg[128,64] == YmmReg2_m256[128,64]) * mask;\n\tYmmReg1[192,64] = zext(vexVVVV_YmmReg[192,64] == YmmReg2_m256[192,64]) * mask;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107884\ndefine pcodeop vpgatherdd ;\n:VPGATHERDD XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & ZmmReg1) ... & d_vm32x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vpgatherdd(XmmReg1, d_vm32x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vpgatherdd(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n\n# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107888\n@ifdef IA64\ndefine pcodeop vpgatherqd ;\n:VPGATHERQD XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & ZmmReg1) ... & d_vm64x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vpgatherqd(XmmReg1, d_vm64x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n@endif\n\n# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107892\n:VPGATHERDD YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x90; (YmmReg1 & ZmmReg1) ... & d_vm32y {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tYmmReg1 = vpgatherdd(YmmReg1, d_vm32y, vexVVVV_YmmReg);\n\tYmmReg1 = vpgatherdd(YmmReg1, vexVVVV_YmmReg);\n\tZmmReg1 = zext(YmmReg1);\n\tvexVVVV_YmmReg = 0;\n}\n\n# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107896\n@ifdef IA64\n:VPGATHERQD XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & ZmmReg1) ... & d_vm64y {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vpgatherqd(XmmReg1, d_vm64y, vexVVVV_XmmReg);\n\tlocal tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n@endif\n\n\n# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108234\ndefine pcodeop vpgatherdq ;\n:VPGATHERDQ XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & ZmmReg1) ... & q_vm32x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vpgatherdq(XmmReg1, q_vm32x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vpgatherdq(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n\n# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108238\n@ifdef IA64\ndefine pcodeop vpgatherqq ;\n:VPGATHERQQ XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & ZmmReg1) ... & q_vm64x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tXmmReg1 = vpgatherqq(XmmReg1, q_vm64x, vexVVVV_XmmReg);\n\tlocal tmp:16 = vpgatherqq(XmmReg1, vexVVVV_XmmReg);\n\tZmmReg1 = zext(tmp);\n\tvexVVVV_XmmReg = 0;\n}\n@endif\n\n# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108242\n:VPGATHERDQ YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x90; (YmmReg1 & ZmmReg1) ... & q_vm32x {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tYmmReg1 = vpgatherdq(YmmReg1, q_vm32x, vexVVVV_YmmReg);\n\tYmmReg1 = vpgatherdq(YmmReg1, vexVVVV_YmmReg);\n\tZmmReg1 = zext(YmmReg1);\n\tvexVVVV_YmmReg = 0;\n}\n\n# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108246\n@ifdef IA64\n:VPGATHERQQ YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x91; (YmmReg1 & ZmmReg1) ... & q_vm64y {\n# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now\n#\tYmmReg1 = vpgatherqq(YmmReg1, q_vm64y, vexVVVV_YmmReg);\n\tYmmReg1 = vpgatherqq(YmmReg1, vexVVVV_YmmReg);\n\tZmmReg1 = zext(YmmReg1);\n\tvexVVVV_YmmReg = 0;\n}\n@endif\n\n\n# PMOVMSKB 4-338 PAGE 1458 LINE 75655\n:VPMOVMSKB Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & YmmReg2) & check_Reg32_dest\n{\n\tlocal byte_mask:4 = 0:4;\n\tbyte_mask[0,1] = YmmReg2[7,1];\n\tbyte_mask[1,1] = YmmReg2[15,1];\n\tbyte_mask[2,1] = YmmReg2[23,1];\n\tbyte_mask[3,1] = YmmReg2[31,1];\n\tbyte_mask[4,1] = YmmReg2[39,1];\n\tbyte_mask[5,1] = YmmReg2[47,1];\n\tbyte_mask[6,1] = YmmReg2[55,1];\n\tbyte_mask[7,1] = YmmReg2[63,1];\n\tbyte_mask[8,1] = YmmReg2[71,1];\n\tbyte_mask[9,1] = YmmReg2[79,1];\n\tbyte_mask[10,1] = YmmReg2[87,1];\n\tbyte_mask[11,1] = YmmReg2[95,1];\n\tbyte_mask[12,1] = YmmReg2[103,1];\n\tbyte_mask[13,1] = YmmReg2[111,1];\n\tbyte_mask[14,1] = YmmReg2[119,1];\n\tbyte_mask[15,1] = YmmReg2[127,1];\n\tbyte_mask[16,1] = YmmReg2[135,1];\n\tbyte_mask[17,1] = YmmReg2[143,1];\n\tbyte_mask[18,1] = YmmReg2[151,1];\n\tbyte_mask[19,1] = YmmReg2[159,1];\n\tbyte_mask[20,1] = YmmReg2[167,1];\n\tbyte_mask[21,1] = YmmReg2[175,1];\n\tbyte_mask[22,1] = YmmReg2[183,1];\n\tbyte_mask[23,1] = YmmReg2[191,1];\n\tbyte_mask[24,1] = YmmReg2[199,1];\n\tbyte_mask[25,1] = YmmReg2[207,1];\n\tbyte_mask[26,1] = YmmReg2[215,1];\n\tbyte_mask[27,1] = YmmReg2[223,1];\n\tbyte_mask[28,1] = YmmReg2[231,1];\n\tbyte_mask[29,1] = YmmReg2[239,1];\n\tbyte_mask[30,1] = YmmReg2[247,1];\n\tbyte_mask[31,1] = YmmReg2[255,1];\n\tReg32 = zext(byte_mask);\n\tbuild check_Reg32_dest;\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/avx512.sinc", "content": "# INFO This file automatically generated by andre on Wed May 8 15:10:16 2024\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['--cpuid-match', 'AVX512', '--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc']\n\n# ADDPD 3-33 PAGE 603 LINE 33411\ndefine pcodeop vaddpd_avx512vl ;\n:VADDPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vaddpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ADDPD 3-33 PAGE 603 LINE 33414\n:VADDPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vaddpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\t\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ADDPD 3-33 PAGE 603 LINE 33417\ndefine pcodeop vaddpd_avx512f ;\n:VADDPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vaddpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\t\n\tZmmReg1 = ZmmResult;\n}\n\n# ADDPS 3-36 PAGE 606 LINE 33562\ndefine pcodeop vaddps_avx512vl ;\n:VADDPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vaddps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ADDPS 3-36 PAGE 606 LINE 33565\n:VADDPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vaddps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst);\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\t\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ADDPS 3-36 PAGE 606 LINE 33568\ndefine pcodeop vaddps_avx512f ;\n:VADDPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vaddps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\t\n\tZmmReg1 = ZmmResult;\n}\n\n# ADDSD 3-39 PAGE 609 LINE 33721\ndefine pcodeop vaddsd_avx512f ;\n:VADDSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vaddsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ADDSS 3-41 PAGE 611 LINE 33815\ndefine pcodeop vaddss_avx512f ;\n:VADDSS XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vaddss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ANDPD 3-64 PAGE 634 LINE 34827\ndefine pcodeop vandpd_avx512vl ;\n:VANDPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vandpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ANDPD 3-64 PAGE 634 LINE 34830\n:VANDPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vandpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\t\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ANDPD 3-64 PAGE 634 LINE 34833\ndefine pcodeop vandpd_avx512dq ;\n:VANDPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vandpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\t\n\tZmmReg1 = ZmmResult;\n}\n\n# ANDPS 3-67 PAGE 637 LINE 34953\ndefine pcodeop vandps_avx512vl ;\n:VANDPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vandps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ANDPS 3-67 PAGE 637 LINE 34956\n:VANDPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp:32 = vandps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tbuild YmmOpMask32;\n\t\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ANDPS 3-67 PAGE 637 LINE 34959\ndefine pcodeop vandps_avx512dq ;\n:VANDPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vandps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# ANDNPD 3-70 PAGE 640 LINE 35087\ndefine pcodeop vandnpd_avx512vl ;\n:VANDNPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vandnpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ANDNPD 3-70 PAGE 640 LINE 35090\n:VANDNPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vandnpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ANDNPD 3-70 PAGE 640 LINE 35093\ndefine pcodeop vandnpd_avx512dq ;\n:VANDNPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vandnpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# ANDNPS 3-73 PAGE 643 LINE 35213\ndefine pcodeop vandnps_avx512vl ;\n:VANDNPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vandnps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ANDNPS 3-73 PAGE 643 LINE 35216\n:VANDNPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vandnps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ANDNPS 3-73 PAGE 643 LINE 35219\ndefine pcodeop vandnps_avx512dq ;\n:VANDNPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vandnps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# CMPPD 3-155 PAGE 725 LINE 39246\ndefine pcodeop vcmppd_avx512vl ;\n:^VCMPPD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m64bcst; VCMPPD_mon & VCMPPD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vcmppd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, VCMPPD_op );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# CMPPD 3-155 PAGE 725 LINE 39250\n:^VCMPPD_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m64bcst; VCMPPD_mon & VCMPPD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vcmppd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, VCMPPD_op );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# CMPPD 3-155 PAGE 725 LINE 39254\ndefine pcodeop vcmppd_avx512f ;\n:^VCMPPD_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m64bcst; VCMPPD_mon & VCMPPD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vcmppd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VCMPPD_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# CMPPS 3-162 PAGE 732 LINE 39613\ndefine pcodeop vcmpps_avx512vl ;\n:^VCMPPS_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m32bcst; VCMPPS_mon & VCMPPS_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vcmpps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, VCMPPS_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# CMPPS 3-162 PAGE 732 LINE 39617\n:^VCMPPS_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m32bcst; VCMPPS_mon & VCMPPS_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vcmpps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, VCMPPS_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# CMPPS 3-162 PAGE 732 LINE 39621\ndefine pcodeop vcmpps_avx512f ;\n:^VCMPPS_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m32bcst; VCMPPS_mon & VCMPPS_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vcmpps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VCMPPS_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# CMPSD 3-173 PAGE 743 LINE 40157\ndefine pcodeop vcmpsd_avx512f ;\n:^VCMPSD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m64^VCMPSD_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp = vcmpsd_avx512f( evexV5_XmmReg, XmmReg2_m64, VCMPSD_op );\n\tKReg_reg = zext(AVXOpMask[0,1]) & tmp;\n}\n\n# CMPSS 3-177 PAGE 747 LINE 40393\ndefine pcodeop vcmpss_avx512f ;\n:^VCMPSS_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m32^VCMPSS_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp = vcmpss_avx512f( evexV5_XmmReg, XmmReg2_m32, VCMPSS_op );\n\tKReg_reg = zext(AVXOpMask[0,1]) & tmp;\n}\n\n# COMISD 3-186 PAGE 756 LINE 40863\ndefine pcodeop vcomisd_avx512f ;\n:VCOMISD XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcomisd_avx512f( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# COMISS 3-188 PAGE 758 LINE 40941\ndefine pcodeop vcomiss_avx512f ;\n:VCOMISS XmmReg1, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcomiss_avx512f( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTDQ2PD 3-228 PAGE 798 LINE 43080\ndefine pcodeop vcvtdq2pd_avx512vl ;\n:VCVTDQ2PD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexBType=1; ] # (TupleType HV)\n{\n\tXmmResult = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTDQ2PD 3-228 PAGE 798 LINE 43083\n:VCVTDQ2PD YmmReg1^YmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTDQ2PD 3-228 PAGE 798 LINE 43086\ndefine pcodeop vcvtdq2pd_avx512f ;\n:VCVTDQ2PD ZmmReg1^ZmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexBType=1; ] # (TupleType HV)\n{\n\tZmmResult = vcvtdq2pd_avx512f( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# CVTDQ2PS 3-232 PAGE 802 LINE 43248\ndefine pcodeop vcvtdq2ps_avx512vl ;\n:VCVTDQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtdq2ps_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTDQ2PS 3-232 PAGE 802 LINE 43251\n:VCVTDQ2PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtdq2ps_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTDQ2PS 3-232 PAGE 802 LINE 43254\ndefine pcodeop vcvtdq2ps_avx512f ;\n:VCVTDQ2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtdq2ps_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# CVTPD2DQ 3-235 PAGE 805 LINE 43414\ndefine pcodeop vcvtpd2dq_avx512vl ;\n:VCVTPD2DQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2dq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTPD2DQ 3-235 PAGE 805 LINE 43417\n:VCVTPD2DQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtpd2dq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTPD2DQ 3-235 PAGE 805 LINE 43420\ndefine pcodeop vcvtpd2dq_avx512f ;\n:VCVTPD2DQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtpd2dq_avx512f( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTPD2PS 3-240 PAGE 810 LINE 43649\ndefine pcodeop vcvtpd2ps_avx512vl ;\n:VCVTPD2PS XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2ps_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTPD2PS 3-240 PAGE 810 LINE 43653\n:VCVTPD2PS XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2ps_avx512vl( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTPD2PS 3-240 PAGE 810 LINE 43657\ndefine pcodeop vcvtpd2ps_avx512f ;\n:VCVTPD2PS YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtpd2ps_avx512f( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTPS2DQ 3-246 PAGE 816 LINE 43933\ndefine pcodeop vcvtps2dq_avx512vl ;\n:VCVTPS2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtps2dq_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTPS2DQ 3-246 PAGE 816 LINE 43936\n:VCVTPS2DQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtps2dq_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTPS2DQ 3-246 PAGE 816 LINE 43939\ndefine pcodeop vcvtps2dq_avx512f ;\n:VCVTPS2DQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtps2dq_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# CVTPS2PD 3-249 PAGE 819 LINE 44104\ndefine pcodeop vcvtps2pd_avx512vl ;\n:VCVTPS2PD XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tXmmResult = vcvtps2pd_avx512vl( XmmReg2_m64_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTPS2PD 3-249 PAGE 819 LINE 44107\n:VCVTPS2PD YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvtps2pd_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTPS2PD 3-249 PAGE 819 LINE 44110\ndefine pcodeop vcvtps2pd_avx512f ;\n:VCVTPS2PD ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tZmmResult = vcvtps2pd_avx512f( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# CVTSD2SI 3-253 PAGE 823 LINE 44320\ndefine pcodeop vcvtsd2si_avx512f ;\n:VCVTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvtsd2si_avx512f( XmmReg2_m64 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# CVTSD2SI 3-253 PAGE 823 LINE 44322\n@ifdef IA64\n:VCVTSD2SI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvtsd2si_avx512f( XmmReg2_m64 );\n}\n@endif\n\n# CVTSD2SS 3-255 PAGE 825 LINE 44417\ndefine pcodeop vcvtsd2ss_avx512f ;\n:VCVTSD2SS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vcvtsd2ss_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tXmmResult[0,32] = (zext(XmmOpMask[0,1]) * XmmResult[0,32]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTSI2SD 3-257 PAGE 827 LINE 44522\ndefine pcodeop vcvtsi2sd_avx512f ;\n:VCVTSI2SD XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtsi2sd_avx512f( evexV5_XmmReg, rm32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTSI2SD 3-257 PAGE 827 LINE 44525\n@ifdef IA64\n:VCVTSI2SD XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtsi2sd_avx512f( evexV5_XmmReg, rm64 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# CVTSI2SS 3-259 PAGE 829 LINE 44636\ndefine pcodeop vcvtsi2ss_avx512f ;\n:VCVTSI2SS XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtsi2ss_avx512f( evexV5_XmmReg, rm32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# CVTSI2SS 3-259 PAGE 829 LINE 44638\n@ifdef IA64\n:VCVTSI2SS XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtsi2ss_avx512f( evexV5_XmmReg, rm64 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# CVTSS2SD 3-261 PAGE 831 LINE 44747\ndefine pcodeop vcvtss2sd_avx512f ;\n:VCVTSS2SD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vcvtss2sd_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tXmmResult[0,64] = (zext(XmmOpMask[0,1]) * XmmResult[0,64]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTSS2SI 3-263 PAGE 833 LINE 44839\ndefine pcodeop vcvtss2si_avx512f ;\n:VCVTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvtss2si_avx512f( XmmReg2_m32 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# CVTSS2SI 3-263 PAGE 833 LINE 44841\n@ifdef IA64\n:VCVTSS2SI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvtss2si_avx512f( XmmReg2_m32 );\n}\n@endif\n\n# CVTTPD2DQ 3-265 PAGE 835 LINE 44936\ndefine pcodeop vcvttpd2dq_avx512vl ;\n:VCVTTPD2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttpd2dq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTTPD2DQ 3-265 PAGE 835 LINE 44940\n:VCVTTPD2DQ XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttpd2dq_avx512vl( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTTPD2DQ 3-265 PAGE 835 LINE 44944\ndefine pcodeop vcvttpd2dq_avx512f ;\n:VCVTTPD2DQ YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvttpd2dq_avx512f( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTTPS2DQ 3-270 PAGE 840 LINE 45169\ndefine pcodeop vcvttps2dq_avx512vl ;\n:VCVTTPS2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttps2dq_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# CVTTPS2DQ 3-270 PAGE 840 LINE 45173\n:VCVTTPS2DQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvttps2dq_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# CVTTPS2DQ 3-270 PAGE 840 LINE 45177\ndefine pcodeop vcvttps2dq_avx512f ;\n:VCVTTPS2DQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvttps2dq_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# CVTTSD2SI 3-274 PAGE 844 LINE 45385\ndefine pcodeop vcvttsd2si_avx512f ;\n:VCVTTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvttsd2si_avx512f( XmmReg2_m64 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# CVTTSD2SI 3-274 PAGE 844 LINE 45388\n@ifdef IA64\n:VCVTTSD2SI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvttsd2si_avx512f( XmmReg2_m64 );\n}\n@endif\n\n# CVTTSS2SI 3-276 PAGE 846 LINE 45479\ndefine pcodeop vcvttss2si_avx512f ;\n:VCVTTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvttss2si_avx512f( XmmReg2_m32 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# CVTTSS2SI 3-276 PAGE 846 LINE 45482\n@ifdef IA64\n:VCVTTSS2SI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvttss2si_avx512f( XmmReg2_m32 );\n}\n@endif\n\n# DIVPD 3-288 PAGE 858 LINE 46029\ndefine pcodeop vdivpd_avx512vl ;\n:VDIVPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vdivpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# DIVPD 3-288 PAGE 858 LINE 46033\n:VDIVPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vdivpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# DIVPD 3-288 PAGE 858 LINE 46037\ndefine pcodeop vdivpd_avx512f ;\n:VDIVPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vdivpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# DIVPS 3-291 PAGE 861 LINE 46170\ndefine pcodeop vdivps_avx512vl ;\n:VDIVPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vdivps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# DIVPS 3-291 PAGE 861 LINE 46174\n:VDIVPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vdivps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# DIVPS 3-291 PAGE 861 LINE 46178\ndefine pcodeop vdivps_avx512f ;\n:VDIVPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vdivps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# DIVSD 3-294 PAGE 864 LINE 46315\ndefine pcodeop vdivsd_avx512f ;\n:VDIVSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vdivsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# DIVSS 3-296 PAGE 866 LINE 46413\ndefine pcodeop vdivss_avx512f ;\n:VDIVSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vdivss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# EXTRACTPS 3-307 PAGE 877 LINE 46983\ndefine pcodeop vextractps_avx512f ;\n:VEXTRACTPS rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x17; XmmReg1 ... & rm32; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\trm32 = vextractps_avx512f( XmmReg1, imm8:1 );\n}\n\n# INSERTPS 3-454 PAGE 1024 LINE 53785\ndefine pcodeop vinsertps_avx512f ;\n:VINSERTPS XmmReg1, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vinsertps_avx512f( evexV5_XmmReg, XmmReg2_m32, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n\n# MAXPD 4-12 PAGE 1132 LINE 59206\ndefine pcodeop vmaxpd_avx512vl ;\n:VMAXPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vmaxpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MAXPD 4-12 PAGE 1132 LINE 59210\n:VMAXPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vmaxpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MAXPD 4-12 PAGE 1132 LINE 59214\ndefine pcodeop vmaxpd_avx512f ;\n:VMAXPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vmaxpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MAXPS 4-15 PAGE 1135 LINE 59356\ndefine pcodeop vmaxps_avx512vl ;\n:VMAXPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vmaxps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MAXPS 4-15 PAGE 1135 LINE 59359\n:VMAXPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vmaxps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MAXPS 4-15 PAGE 1135 LINE 59362\ndefine pcodeop vmaxps_avx512f ;\n:VMAXPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vmaxps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MAXSD 4-18 PAGE 1138 LINE 59506\ndefine pcodeop vmaxsd_avx512f ;\n:VMAXSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vmaxsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MAXSS 4-20 PAGE 1140 LINE 59609\ndefine pcodeop vmaxss_avx512f ;\n:VMAXSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vmaxss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MINPD 4-23 PAGE 1143 LINE 59771\ndefine pcodeop vminpd_avx512vl ;\n:VMINPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vminpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MINPD 4-23 PAGE 1143 LINE 59774\n:VMINPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vminpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MINPD 4-23 PAGE 1143 LINE 59777\ndefine pcodeop vminpd_avx512f ;\n:VMINPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vminpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MINPS 4-26 PAGE 1146 LINE 59915\ndefine pcodeop vminps_avx512vl ;\n:VMINPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vminps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MINPS 4-26 PAGE 1146 LINE 59918\n:VMINPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vminps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MINPS 4-26 PAGE 1146 LINE 59921\ndefine pcodeop vminps_avx512f ;\n:VMINPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vminps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MINSD 4-29 PAGE 1149 LINE 60063\ndefine pcodeop vminsd_avx512f ;\n:VMINSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vminsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MINSS 4-31 PAGE 1151 LINE 60166\ndefine pcodeop vminss_avx512f ;\n:VMINSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vminss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60852\n:VMOVAPD XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = XmmReg2_m128 ;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60855\n:VMOVAPD YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = YmmReg2_m256;\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60858\ndefine pcodeop vmovapd_avx512f ;\n:VMOVAPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = ZmmReg2_m512;\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n:VMOVAPD XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1 ;\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VMOVAPD m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1 ;\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60864\n:VMOVAPD YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1 ;\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask64;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VMOVAPD m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x29; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1 ;\n\tYmmMask = m256;\n\tbuild YmmOpMask64;\n\tm256 = YmmResult;\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60867\n:VMOVAPD ZmmReg2^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x29; ZmmReg1 & mod=3 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmResult = ZmmReg1 ;\n\tZmmMask = ZmmReg2;\n\tbuild ZmmOpMask64;\n\tZmmReg2 = ZmmResult;\n}\n\n:VMOVAPD m512 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x29; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmResult = ZmmReg1 ;\n\tZmmMask = m512;\n\tbuild ZmmOpMask64;\n\tm512 = ZmmResult;\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61047\n:VMOVAPS XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = XmmReg2_m128;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61050\n:VMOVAPS YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = YmmReg2_m256;\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61053\ndefine pcodeop vmovaps_avx512f ;\n:VMOVAPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = ZmmReg2_m512 ;\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61056\n:VMOVAPS XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VMOVAPS m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; (XmmReg1) ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61059\n:VMOVAPS YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1;\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VMOVAPS m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; (YmmReg1 & YmmOpMask32) ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1;\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = YmmResult;\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61062\n:VMOVAPS ZmmReg2^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; ZmmReg1 & mod=3 & ZmmOpMask32 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmResult = ZmmReg1 ;\n\tZmmMask = ZmmReg2;\n\tbuild ZmmOpMask32;\n\tZmmReg2 = ZmmResult;\n}\n\n:VMOVAPS m512 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; (ZmmReg1 & ZmmOpMask32) ... & m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmResult = ZmmReg1 ;\n\tZmmMask = m512;\n\tbuild ZmmOpMask32;\n\tm512 = ZmmResult;\n}\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61366\n:VMOVD XmmReg1, rm32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6E; XmmReg1 ... & rm32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)\n{\n\tXmmReg1 = zext(rm32);\n}\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61368\n@ifdef IA64\n:VMOVQ XmmReg1, rm64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x6E; XmmReg1 ... & rm64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)\n{\n\tXmmReg1 = zext(rm64);\n}\n@endif\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61370\n:VMOVD rm32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; XmmReg1 ... & rm32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\trm32 = XmmReg1[0,32];\n}\n\n# MOVD/MOVQ 4-55 PAGE 1175 LINE 61372\n@ifdef IA64\n:VMOVQ rm64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7E; XmmReg1 ... & rm64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\trm64 = XmmReg1[0,64];\n}\n@endif\n\n# MOVDDUP 4-59 PAGE 1179 LINE 61526\ndefine pcodeop vmovddup_avx512vl ;\n:VMOVDDUP XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM)\n{\n\tXmmResult = vmovddup_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDDUP 4-59 PAGE 1179 LINE 61529\n:VMOVDDUP YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM)\n{\n\tYmmResult = vmovddup_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDDUP 4-59 PAGE 1179 LINE 61532\ndefine pcodeop vmovddup_avx512f ;\n:VMOVDDUP ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM)\n{\n\tZmmResult = vmovddup_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61675\ndefine pcodeop vmovdqa32_avx512vl ;\n:VMOVDQA32 XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = vmovdqa32_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61678\n:VMOVDQA32 YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = vmovdqa32_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61681\ndefine pcodeop vmovdqa32_avx512f ;\n:VMOVDQA32 ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = vmovdqa32_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61684\n:VMOVDQA32 XmmReg2_m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmReg2_m128 = vmovdqa32_avx512vl( XmmReg1 );\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61687\n:VMOVDQA32 YmmReg2_m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmReg2_m256 = vmovdqa32_avx512vl( YmmReg1 );\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61690\n:VMOVDQA32 ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmReg2_m512 = vmovdqa32_avx512f( ZmmReg1 );\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61693\ndefine pcodeop vmovdqa64_avx512vl ;\n:VMOVDQA64 XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = vmovdqa64_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61696\n:VMOVDQA64 YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = vmovdqa64_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61699\ndefine pcodeop vmovdqa64_avx512f ;\n:VMOVDQA64 ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = vmovdqa64_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61702\n:VMOVDQA64 XmmReg2_m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmReg2_m128 = vmovdqa64_avx512vl( XmmReg1 );\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61705\n:VMOVDQA64 YmmReg2_m256^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmReg2_m256 = vmovdqa64_avx512vl( YmmReg1 );\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61708\n:VMOVDQA64 ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmReg2_m512 = vmovdqa64_avx512f( ZmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61938\ndefine pcodeop vmovdqu8_avx512vl ;\n:VMOVDQU8 XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = vmovdqu8_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61941\n:VMOVDQU8 YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = vmovdqu8_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61944\ndefine pcodeop vmovdqu8_avx512bw ;\n:VMOVDQU8 ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = vmovdqu8_avx512bw( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61947\n:VMOVDQU8 XmmReg2_m128^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmReg2_m128 = vmovdqu8_avx512vl( XmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61950\n:VMOVDQU8 YmmReg2_m256^YmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmReg2_m256 = vmovdqu8_avx512vl( YmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61953\n:VMOVDQU8 ZmmReg2_m512^ZmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmReg2_m512 = vmovdqu8_avx512bw( ZmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61956\ndefine pcodeop vmovdqu16_avx512vl ;\n:VMOVDQU16 XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = vmovdqu16_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61959\n:VMOVDQU16 YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = vmovdqu16_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61962\ndefine pcodeop vmovdqu16_avx512bw ;\n:VMOVDQU16 ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = vmovdqu16_avx512bw( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61965\n:VMOVDQU16 XmmReg2_m128^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmReg2_m128 = vmovdqu16_avx512vl( XmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61968\n:VMOVDQU16 YmmReg2_m256^YmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmReg2_m256 = vmovdqu16_avx512vl( YmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61971\n:VMOVDQU16 ZmmReg2_m512^ZmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmReg2_m512 = vmovdqu16_avx512bw( ZmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61974\ndefine pcodeop vmovdqu32_avx512vl ;\n:VMOVDQU32 XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = vmovdqu32_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61987\n:VMOVDQU32 YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = vmovdqu32_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61990\ndefine pcodeop vmovdqu32_avx512f ;\n:VMOVDQU32 ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = vmovdqu32_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61993\n:VMOVDQU32 XmmReg2_m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmReg2_m128 = vmovdqu32_avx512vl( XmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61996\n:VMOVDQU32 YmmReg2_m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmReg2_m256 = vmovdqu32_avx512vl( YmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61999\n:VMOVDQU32 ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmReg2_m512 = vmovdqu32_avx512f( ZmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62002\ndefine pcodeop vmovdqu64_avx512vl ;\n:VMOVDQU64 XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = vmovdqu64_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62005\n:VMOVDQU64 YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = vmovdqu64_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62008\ndefine pcodeop vmovdqu64_avx512f ;\n:VMOVDQU64 ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = vmovdqu64_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62011\n:VMOVDQU64 XmmReg2_m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmReg2_m128 = vmovdqu64_avx512vl( XmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62014\n:VMOVDQU64 YmmReg2_m256^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmReg2_m256 = vmovdqu64_avx512vl( YmmReg1 );\n}\n\n# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62017\n:VMOVDQU64 ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmReg2_m512 = vmovdqu64_avx512f( ZmmReg1 );\n}\n\n# MOVHLPS 4-76 PAGE 1196 LINE 62412\n:VMOVHLPS XmmReg1, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)\n{\n\tlocal src1 = evexV5_XmmReg[64,64];\n\tlocal src2 = XmmReg2[64,64];\n\tXmmReg1[0,64] = src2;\n\tXmmReg1[64,64] = src2;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVHPD 4-78 PAGE 1198 LINE 62485\ndefine pcodeop vmovhpd_avx512f ;\n:VMOVHPD XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal src1 = evexV5_XmmReg[0,64];\n\tlocal src2 = m64[0,64];\n\tXmmReg1[0,64] = src2;\n\tXmmReg1[64,64] = src2;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVHPD 4-78 PAGE 1198 LINE 62491\n:VMOVHPD m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x17; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\tm64 = vmovhpd_avx512f( XmmReg1 );\n}\n\n# MOVHPS 4-80 PAGE 1200 LINE 62572\ndefine pcodeop vmovhps_avx512f ;\n:VMOVHPS XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2)\n{\n\tXmmResult = vmovhps_avx512f( evexV5_XmmReg, m64 );\n\tXmmMask = XmmReg1;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVHPS 4-80 PAGE 1200 LINE 62578\n:VMOVHPS m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x17; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2-MR)\n{\n\tm64 = vmovhps_avx512f( XmmReg1 );\n}\n\n# MOVLHPS 4-82 PAGE 1202 LINE 62660\n# WARNING: duplicate opcode EVEX.NDS.128.0F.W0 16 /r last seen on 4-80 PAGE 1200 LINE 62572 for \"VMOVLHPS xmm1, xmm2, xmm3\"\ndefine pcodeop vmovlhps_avx512f ;\n:VMOVLHPS XmmReg1, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)\n{\n\tlocal tmp:16 = vmovlhps_avx512f( evexV5_XmmReg, XmmReg2 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVLPD 4-84 PAGE 1204 LINE 62733\ndefine pcodeop vmovlpd_avx512f ;\n:VMOVLPD XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vmovlpd_avx512f( evexV5_XmmReg, m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVLPD 4-84 PAGE 1204 LINE 62739\n:VMOVLPD m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x13; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\tm64 = vmovlpd_avx512f( XmmReg1 );\n}\n\n# MOVLPS 4-86 PAGE 1206 LINE 62818\n# WARNING: duplicate opcode EVEX.NDS.128.0F.W0 12 /r last seen on 4-76 PAGE 1196 LINE 62412 for \"VMOVLPS xmm2, xmm1, m64\"\ndefine pcodeop vmovlps_avx512f ;\n:VMOVLPS XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2)\n{\n\tlocal tmp:16 = vmovlps_avx512f( evexV5_XmmReg, m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVLPS 4-86 PAGE 1206 LINE 62824\n:VMOVLPS m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x13; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2-MR)\n{\n\tm64 = vmovlps_avx512f( XmmReg1 );\n}\n\n# MOVNTDQA 4-92 PAGE 1212 LINE 63088\ndefine pcodeop vmovntdqa_avx512vl ;\n:VMOVNTDQA XmmReg1, m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x2A; (XmmReg1 & ZmmReg1) ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp:16 = vmovntdqa_avx512vl( m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVNTDQA 4-92 PAGE 1212 LINE 63090\n:VMOVNTDQA YmmReg1, m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x2A; (YmmReg1 & ZmmReg1) ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp:32 = vmovntdqa_avx512vl( m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVNTDQA 4-92 PAGE 1212 LINE 63092\ndefine pcodeop vmovntdqa_avx512f ;\n:VMOVNTDQA ZmmReg1, m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x2A; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmReg1 = vmovntdqa_avx512f( m512 );\n\n}\n\n# MOVNTDQ 4-94 PAGE 1214 LINE 63191\ndefine pcodeop vmovntdq_avx512vl ;\n:VMOVNTDQ m128, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xE7; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm128 = vmovntdq_avx512vl( XmmReg1 );\n}\n\n# MOVNTDQ 4-94 PAGE 1214 LINE 63193\n:VMOVNTDQ m256, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xE7; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm256 = vmovntdq_avx512vl( YmmReg1 );\n}\n\n# MOVNTDQ 4-94 PAGE 1214 LINE 63195\ndefine pcodeop vmovntdq_avx512f ;\n:VMOVNTDQ m512, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xE7; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm512 = vmovntdq_avx512f( ZmmReg1 );\n}\n\n# MOVNTPD 4-98 PAGE 1218 LINE 63361\ndefine pcodeop vmovntpd_avx512vl ;\n:VMOVNTPD m128, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2B; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm128 = vmovntpd_avx512vl( XmmReg1 );\n}\n\n# MOVNTPD 4-98 PAGE 1218 LINE 63363\n:VMOVNTPD m256, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2B; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm256 = vmovntpd_avx512vl( YmmReg1 );\n}\n\n# MOVNTPD 4-98 PAGE 1218 LINE 63365\ndefine pcodeop vmovntpd_avx512f ;\n:VMOVNTPD m512, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2B; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm512 = vmovntpd_avx512f( ZmmReg1 );\n}\n\n# MOVNTPS 4-100 PAGE 1220 LINE 63445\ndefine pcodeop vmovntps_avx512vl ;\n:VMOVNTPS m128, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2B; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm128 = vmovntps_avx512vl( XmmReg1 );\n}\n\n# MOVNTPS 4-100 PAGE 1220 LINE 63447\n:VMOVNTPS m256, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2B; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm256 = vmovntps_avx512vl( YmmReg1 );\n}\n\n# MOVNTPS 4-100 PAGE 1220 LINE 63449\ndefine pcodeop vmovntps_avx512f ;\n:VMOVNTPS m512, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2B; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tm512 = vmovntps_avx512f( ZmmReg1 );\n}\n\n# MOVQ 4-103 PAGE 1223 LINE 63581\n:VMOVQ XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)\n{\n\tZmmReg1 = zext(XmmReg2_m64[0,64]);\n}\n\n# MOVQ 4-103 PAGE 1223 LINE 63587\n:VMOVQ XmmReg2, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0xD6; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\tZmmReg2 = zext( XmmReg1[0,64] );\n}\n\n:VMOVQ m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0xD6; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\tm64 = XmmReg1[0,64];\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63978\ndefine pcodeop vmovsd_avx512f ;\n:VMOVSD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2)\n{\n\tXmmResult = XmmReg2;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tXmmResult[0,64] = (zext(XmmOpMask[0,1]) * XmmResult[0,64]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);\n\tXmmResult[64,64] = evexV5_XmmReg[64,64];\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63981\n:VMOVSD XmmReg1^XmmOpMask, m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)\n{\n\tlocal tmp:8 = m64;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\ttmp = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63983\n:VMOVSD XmmReg2^XmmOpMask, evexV5_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x11; XmmReg1 & ZmmReg1 & XmmOpMask & (mod=0x3 & XmmReg2)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tXmmResult[0,64] = (zext(XmmOpMask[0,1]) * XmmResult[0,64]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);\n\tXmmResult[64,64] = evexV5_XmmReg[64,64];\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63986\n:VMOVSD m64^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & XmmOpMask; byte=0x11; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\tXmmResult = vmovsd_avx512f( XmmReg1 );\n\tlocal tmp:8 = m64;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\ttmp = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);\n\tm64 = tmp;\n\t\n}\n\n# MOVSHDUP 4-114 PAGE 1234 LINE 64130\ndefine pcodeop vmovshdup_avx512vl ;\n:VMOVSHDUP XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vmovshdup_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVSHDUP 4-114 PAGE 1234 LINE 64133\n:VMOVSHDUP YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vmovshdup_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVSHDUP 4-114 PAGE 1234 LINE 64136\ndefine pcodeop vmovshdup_avx512f ;\n:VMOVSHDUP ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vmovshdup_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVSLDUP 4-117 PAGE 1237 LINE 64284\ndefine pcodeop vmovsldup_avx512vl ;\n:VMOVSLDUP XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vmovsldup_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVSLDUP 4-117 PAGE 1237 LINE 64287\n:VMOVSLDUP YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vmovsldup_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVSLDUP 4-117 PAGE 1237 LINE 64290\ndefine pcodeop vmovsldup_avx512f ;\n:VMOVSLDUP ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vmovsldup_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64443\n:VMOVSS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2)\n{\n\tlocal tmp:4 = XmmReg2[0,32];\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tXmmResult = evexV5_XmmReg;\n\tXmmResult[0,32] = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64446\n:VMOVSS XmmReg1^XmmOpMask, m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)\n{\n\tlocal tmp:4 = m32;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\ttmp = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);\n\tZmmReg1 = zext(tmp);\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64448\n:VMOVSS XmmReg2^XmmOpMask, evexV5_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))\n{\n\tlocal tmp:4 = XmmReg1[0,32];\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tXmmResult = evexV5_XmmReg;\n\tXmmResult[0,32] = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);\n\tZmmReg2 = zext(XmmResult);\n}\n\n# MOVSS 4-120 PAGE 1240 LINE 64451\n:VMOVSS m32^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask; byte=0x11; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)\n{\n\tlocal tmp:4 = XmmReg1[0,32];\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask;\n\tm32 = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64695\n:VMOVUPD XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = XmmReg2_m128 ;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64698\n:VMOVUPD XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VMOVUPD m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; (XmmReg1) ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64701\n:VMOVUPD YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = YmmReg2_m256;\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64704\n:VMOVUPD YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1;\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask64;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VMOVUPD m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x11; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1;\n\tYmmMask = m256;\n\tbuild YmmOpMask64;\n\tm256 = YmmResult;\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64707\n:VMOVUPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = ZmmReg2_m512;\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVUPD 4-126 PAGE 1246 LINE 64710\n:VMOVUPD ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x11; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmResult = ZmmReg1;\n\tZmmMask = ZmmReg2_m512;\n\tbuild ZmmOpMask64;\n\tZmmReg2_m512 = ZmmResult;\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64880\n:VMOVUPS XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tXmmResult = XmmReg2_m128;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64883\n:VMOVUPS YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tYmmResult = YmmReg2_m256;\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64886\n:VMOVUPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)\n{\n\tZmmResult = ZmmReg2_m512;\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64889\n:VMOVUPS XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VMOVUPS m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64892\n:VMOVUPS YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1;\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VMOVUPS m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x11; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tYmmResult = YmmReg1;\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = YmmResult;\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64895\n:VMOVUPS ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & ZmmOpMask32; byte=0x11; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)\n{\n\tZmmResult = ZmmReg1;\n\tZmmMask = ZmmReg2_m512;\n\tbuild ZmmOpMask32;\n\tZmmReg2_m512 = ZmmResult;\n}\n\n# MULPD 4-146 PAGE 1266 LINE 65686\ndefine pcodeop vmulpd_avx512vl ;\n:VMULPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vmulpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MULPD 4-146 PAGE 1266 LINE 65689\n:VMULPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vmulpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MULPD 4-146 PAGE 1266 LINE 65692\ndefine pcodeop vmulpd_avx512f ;\n:VMULPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vmulpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# MULPS 4-149 PAGE 1269 LINE 65817\ndefine pcodeop vmulps_avx512vl ;\n:VMULPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vmulps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MULPS 4-149 PAGE 1269 LINE 65820\n:VMULPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vmulps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# MULPS 4-149 PAGE 1269 LINE 65823\ndefine pcodeop vmulps_avx512f ;\n:VMULPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vmulps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# MULSD 4-152 PAGE 1272 LINE 65959\ndefine pcodeop vmulsd_avx512f ;\n:VMULSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vmulsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# MULSS 4-154 PAGE 1274 LINE 66055\ndefine pcodeop vmulss_avx512f ;\n:VMULSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vmulss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ORPD 4-168 PAGE 1288 LINE 66724\ndefine pcodeop vorpd_avx512vl ;\n:VORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vorpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ORPD 4-168 PAGE 1288 LINE 66727\n:VORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vorpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ORPD 4-168 PAGE 1288 LINE 66730\ndefine pcodeop vorpd_avx512dq ;\n:VORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# ORPS 4-171 PAGE 1291 LINE 66850\ndefine pcodeop vorps_avx512vl ;\n:VORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vorps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# ORPS 4-171 PAGE 1291 LINE 66853\n:VORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vorps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# ORPS 4-171 PAGE 1291 LINE 66856\ndefine pcodeop vorps_avx512dq ;\n:VORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67320\ndefine pcodeop vpabsb_avx512vl ;\n:VPABSB XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpabsb_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67323\n:VPABSB YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpabsb_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67326\ndefine pcodeop vpabsb_avx512bw ;\n:VPABSB ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpabsb_avx512bw( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67329\ndefine pcodeop vpabsw_avx512vl ;\n:VPABSW XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpabsw_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67344\n:VPABSW YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpabsw_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67347\ndefine pcodeop vpabsw_avx512bw ;\n:VPABSW ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpabsw_avx512bw( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67350\ndefine pcodeop vpabsd_avx512vl ;\n:VPABSD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpabsd_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67353\n:VPABSD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpabsd_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67357\ndefine pcodeop vpabsd_avx512f ;\n:VPABSD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpabsd_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67360\ndefine pcodeop vpabsq_avx512vl ;\n:VPABSQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpabsq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67363\n:VPABSQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpabsq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67366\ndefine pcodeop vpabsq_avx512f ;\n:VPABSQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpabsq_avx512f( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67645\ndefine pcodeop vpacksswb_avx512vl ;\n:VPACKSSWB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpacksswb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67649\n:VPACKSSWB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpacksswb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67653\ndefine pcodeop vpacksswb_avx512bw ;\n:VPACKSSWB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x63; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpacksswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67657\ndefine pcodeop vpackssdw_avx512vl ;\n:VPACKSSDW XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpackssdw_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67674\n:VPACKSSDW YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpackssdw_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67678\ndefine pcodeop vpackssdw_avx512bw ;\n:VPACKSSDW ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpackssdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PACKUSDW 4-194 PAGE 1314 LINE 68094\ndefine pcodeop vpackusdw_avx512vl ;\n:VPACKUSDW XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpackusdw_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PACKUSDW 4-194 PAGE 1314 LINE 68098\n:VPACKUSDW YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpackusdw_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PACKUSDW 4-194 PAGE 1314 LINE 68103\ndefine pcodeop vpackusdw_avx512bw ;\n:VPACKUSDW ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpackusdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PACKUSWB 4-199 PAGE 1319 LINE 68374\ndefine pcodeop vpackuswb_avx512vl ;\n:VPACKUSWB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpackuswb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PACKUSWB 4-199 PAGE 1319 LINE 68378\n:VPACKUSWB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpackuswb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PACKUSWB 4-199 PAGE 1319 LINE 68382\ndefine pcodeop vpackuswb_avx512bw ;\n:VPACKUSWB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x67; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpackuswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68674\ndefine pcodeop vpaddb_avx512vl ;\n:VPADDB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpaddb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68677\ndefine pcodeop vpaddw_avx512vl ;\n:VPADDW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpaddw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68680\ndefine pcodeop vpaddd_avx512vl ;\n:VPADDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpaddd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68683\ndefine pcodeop vpaddq_avx512vl ;\n:VPADDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpaddq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68686\n:VPADDB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpaddb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68689\n:VPADDW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpaddw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68692\n:VPADDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpaddd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68707\n:VPADDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpaddq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68710\ndefine pcodeop vpaddb_avx512bw ;\n:VPADDB ZmmReg1^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFC; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpaddb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68713\ndefine pcodeop vpaddw_avx512bw ;\n:VPADDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpaddw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68716\ndefine pcodeop vpaddd_avx512f ;\n:VPADDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpaddd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68719\ndefine pcodeop vpaddq_avx512f ;\n:VPADDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpaddq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69051\ndefine pcodeop vpaddsb_avx512vl ;\n:VPADDSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpaddsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69054\n:VPADDSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpaddsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69057\ndefine pcodeop vpaddsb_avx512bw ;\n:VPADDSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpaddsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69060\ndefine pcodeop vpaddsw_avx512vl ;\n:VPADDSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpaddsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69063\n:VPADDSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpaddsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69066\ndefine pcodeop vpaddsw_avx512bw ;\n:VPADDSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xED; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpaddsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69269\ndefine pcodeop vpaddusb_avx512vl ;\n:VPADDUSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpaddusb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69273\n:VPADDUSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpaddusb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69277\ndefine pcodeop vpaddusb_avx512bw ;\n:VPADDUSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpaddusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69281\ndefine pcodeop vpaddusw_avx512vl ;\n:VPADDUSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpaddusw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69285\n:VPADDUSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpaddusw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PADDUSB/PADDUSW 4-216 PAGE 1336 LINE 69302\ndefine pcodeop vpaddusw_avx512bw ;\n:VPADDUSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpaddusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PALIGNR 4-219 PAGE 1339 LINE 69495\ndefine pcodeop vpalignr_avx512vl ;\n:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PALIGNR 4-219 PAGE 1339 LINE 69499\n:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PALIGNR 4-219 PAGE 1339 LINE 69505\ndefine pcodeop vpalignr_avx512bw ;\n:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PAND 4-223 PAGE 1343 LINE 69684\ndefine pcodeop vpandd_avx512vl ;\n:VPANDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpandd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PAND 4-223 PAGE 1343 LINE 69687\n:VPANDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpandd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PAND 4-223 PAGE 1343 LINE 69690\ndefine pcodeop vpandd_avx512f ;\n:VPANDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpandd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PAND 4-223 PAGE 1343 LINE 69693\ndefine pcodeop vpandq_avx512vl ;\n:VPANDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpandq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PAND 4-223 PAGE 1343 LINE 69696\n:VPANDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpandq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PAND 4-223 PAGE 1343 LINE 69699\ndefine pcodeop vpandq_avx512f ;\n:VPANDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpandq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69859\ndefine pcodeop vpandnd_avx512vl ;\n:VPANDND XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpandnd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69862\n:VPANDND YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpandnd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69865\ndefine pcodeop vpandnd_avx512f ;\n:VPANDND ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpandnd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69868\ndefine pcodeop vpandnq_avx512vl ;\n:VPANDNQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpandnq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69871\n:VPANDNQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpandnq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PANDN 4-226 PAGE 1346 LINE 69874\ndefine pcodeop vpandnq_avx512f ;\n:VPANDNQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpandnq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70097\ndefine pcodeop vpavgb_avx512vl ;\n:VPAVGB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpavgb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70100\n:VPAVGB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpavgb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70103\ndefine pcodeop vpavgb_avx512bw ;\n:VPAVGB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE0; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpavgb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70106\ndefine pcodeop vpavgw_avx512vl ;\n:VPAVGW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpavgw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70109\n:VPAVGW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpavgw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70112\ndefine pcodeop vpavgw_avx512bw ;\n:VPAVGW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE3; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpavgw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70841\ndefine pcodeop vpcmpeqd_avx512vl ;\n:VPCMPEQD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x76; KReg_reg ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpeqd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n\t\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70846\n:VPCMPEQD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x76; KReg_reg ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpeqd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70851\ndefine pcodeop vpcmpeqd_avx512f ;\n:VPCMPEQD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x76; KReg_reg ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpeqd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70855\ndefine pcodeop vpcmpeqb_avx512vl ;\n:VPCMPEQB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x74; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpeqb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70873\n:VPCMPEQB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x74; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpeqb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70878\ndefine pcodeop vpcmpeqb_avx512bw ;\n:VPCMPEQB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x74; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpeqb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,64]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70883\ndefine pcodeop vpcmpeqw_avx512vl ;\n:VPCMPEQW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x75; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpeqw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70888\n:VPCMPEQW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x75; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpeqw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70893\ndefine pcodeop vpcmpeqw_avx512bw ;\n:VPCMPEQW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x75; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpeqw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# PCMPEQQ 4-250 PAGE 1370 LINE 71174\ndefine pcodeop vpcmpeqq_avx512vl ;\n:VPCMPEQQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x29; KReg_reg ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpeqq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# PCMPEQQ 4-250 PAGE 1370 LINE 71179\n:VPCMPEQQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x29; KReg_reg ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpeqq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# PCMPEQQ 4-250 PAGE 1370 LINE 71184\ndefine pcodeop vpcmpeqq_avx512f ;\n:VPCMPEQQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x29; KReg_reg ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpeqq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71517\ndefine pcodeop vpcmpgtd_avx512vl ;\n:VPCMPGTD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpgtd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71521\n:VPCMPGTD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpgtd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71525\ndefine pcodeop vpcmpgtd_avx512f ;\n:VPCMPGTD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpgtd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71529\ndefine pcodeop vpcmpgtb_avx512vl ;\n:VPCMPGTB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x64; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpgtb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71533\n:VPCMPGTB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x64; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpgtb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71545\ndefine pcodeop vpcmpgtb_avx512bw ;\n:VPCMPGTB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x64; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpgtb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,64]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71549\ndefine pcodeop vpcmpgtw_avx512vl ;\n:VPCMPGTW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x65; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpgtw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71553\n:VPCMPGTW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x65; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpgtw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71557\ndefine pcodeop vpcmpgtw_avx512bw ;\n:VPCMPGTW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x65; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpgtw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# PCMPGTQ 4-263 PAGE 1383 LINE 71837\ndefine pcodeop vpcmpgtq_avx512vl ;\n:VPCMPGTQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x37; KReg_reg ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpgtq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# PCMPGTQ 4-263 PAGE 1383 LINE 71841\n:VPCMPGTQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x37; KReg_reg ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpgtq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# PCMPGTQ 4-263 PAGE 1383 LINE 71849\ndefine pcodeop vpcmpgtq_avx512f ;\n:VPCMPGTQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x37; KReg_reg ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpgtq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72334\n@ifdef IA64\n:VPEXTRB Reg32, XmmReg1, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32 & Reg64; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*8);\n\tReg64 = zext(tmp[0,8]);\n}\n@endif\n\n:VPEXTRB Reg32, XmmReg1, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*8);\n\tReg32 = zext(tmp[0,8]);\n}\n\n:VPEXTRB m8, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 ... & m8; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*8);\n\tm8 = tmp[0,8];\n}\n\n# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72339\n:VPEXTRD rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & rm32; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*32);\n\trm32 = tmp[0,32];\n}\n\n# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72343\n@ifdef IA64\n:VPEXTRQ rm64, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*64);\n\trm64 = tmp[0,64];\n}\n@endif\n\n# PEXTRW 4-277 PAGE 1397 LINE 72488\n@ifdef IA64\n:VPEXTRW Reg32, XmmReg2, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & Reg64 & (mod=0x3 & XmmReg2); imm8\n{\n\tlocal tmp = XmmReg2 >> (imm8*16);\n\tReg64 = zext(tmp[0,16]);\n}\n@endif\n\n:VPEXTRW Reg32, XmmReg2, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8\n{\n\tlocal tmp = XmmReg2 >> (imm8*16);\n\tReg32 = zext(tmp[0,16]);\n}\n\n# PEXTRW 4-277 PAGE 1397 LINE 72494\n@ifdef IA64\n:VPEXTRW Reg32, XmmReg1, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32 & Reg64; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*16);\n\tReg64 = zext(tmp[0,16]);\n}\n@endif\n\n:VPEXTRW Reg32, XmmReg1, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*16);\n\tReg32 = zext(tmp[0,16]);\n}\n\n\n:VPEXTRW m16, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & m16; imm8\n{\n\tlocal tmp = XmmReg1 >> (imm8*16);\n\tm16 = tmp[0,16];\n}\n\n# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73330\ndefine pcodeop vpinsrb_avx512bw ;\n:VPINSRB XmmReg1, evexV5_XmmReg, Reg32_m8, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x20; (XmmReg1 & ZmmReg1) ... & Reg32_m8; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)\n{\n\tlocal tmp:16 = vpinsrb_avx512bw( evexV5_XmmReg, Reg32_m8, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73333\ndefine pcodeop vpinsrd_avx512dq ;\n:VPINSRD XmmReg1, evexV5_XmmReg, rm32, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)\n{\n\tlocal tmp:16 = vpinsrd_avx512dq( evexV5_XmmReg, rm32, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73336\ndefine pcodeop vpinsrq_avx512dq ;\n@ifdef IA64\n:VPINSRQ XmmReg1, evexV5_XmmReg, rm64, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)\n{\n\tlocal tmp:16 = vpinsrq_avx512dq( evexV5_XmmReg, rm64, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# PINSRW 4-296 PAGE 1416 LINE 73449\ndefine pcodeop vpinsrw_avx512bw ;\n:VPINSRW XmmReg1, evexV5_XmmReg, Reg32_m16, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)\n{\n\tlocal tmp:16 = vpinsrw_avx512bw( evexV5_XmmReg, Reg32_m16, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PMADDUBSW 4-298 PAGE 1418 LINE 73558\ndefine pcodeop vpmaddubsw_avx512vl ;\n:VPMADDUBSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmaddubsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMADDUBSW 4-298 PAGE 1418 LINE 73562\n:VPMADDUBSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmaddubsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMADDUBSW 4-298 PAGE 1418 LINE 73566\ndefine pcodeop vpmaddubsw_avx512bw ;\n:VPMADDUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x04; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmaddubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMADDWD 4-301 PAGE 1421 LINE 73708\ndefine pcodeop vpmaddwd_avx512vl ;\n:VPMADDWD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmaddwd_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMADDWD 4-301 PAGE 1421 LINE 73712\n:VPMADDWD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmaddwd_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMADDWD 4-301 PAGE 1421 LINE 73716\ndefine pcodeop vpmaddwd_avx512bw ;\n:VPMADDWD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF5; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmaddwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73900\ndefine pcodeop vpmaxsb_avx512vl ;\n:VPMAXSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmaxsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73903\n:VPMAXSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmaxsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73906\ndefine pcodeop vpmaxsb_avx512bw ;\n:VPMAXSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmaxsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73909\ndefine pcodeop vpmaxsw_avx512vl ;\n:VPMAXSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmaxsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73912\n:VPMAXSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmaxsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73915\ndefine pcodeop vpmaxsw_avx512bw ;\n:VPMAXSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEE; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmaxsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73918\ndefine pcodeop vpmaxsd_avx512vl ;\n:VPMAXSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmaxsd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73933\n:VPMAXSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmaxsd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73936\ndefine pcodeop vpmaxsd_avx512f ;\n:VPMAXSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmaxsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73939\ndefine pcodeop vpmaxsq_avx512vl ;\n:VPMAXSQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmaxsq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73942\n:VPMAXSQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmaxsq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73945\ndefine pcodeop vpmaxsq_avx512f ;\n:VPMAXSQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmaxsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74295\ndefine pcodeop vpmaxub_avx512vl ;\n:VPMAXUB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmaxub_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74298\n:VPMAXUB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmaxub_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74301\ndefine pcodeop vpmaxub_avx512bw ;\n:VPMAXUB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDE; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmaxub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74304\ndefine pcodeop vpmaxuw_avx512vl ;\n:VPMAXUW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmaxuw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74307\n:VPMAXUW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmaxuw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74310\ndefine pcodeop vpmaxuw_avx512bw ;\n:VPMAXUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3E; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmaxuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74540\ndefine pcodeop vpmaxud_avx512vl ;\n:VPMAXUD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmaxud_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74543\n:VPMAXUD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmaxud_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74546\ndefine pcodeop vpmaxud_avx512f ;\n:VPMAXUD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmaxud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74549\ndefine pcodeop vpmaxuq_avx512vl ;\n:VPMAXUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmaxuq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74552\n:VPMAXUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmaxuq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74555\ndefine pcodeop vpmaxuq_avx512f ;\n:VPMAXUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmaxuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74748\ndefine pcodeop vpminsb_avx512vl ;\n:VPMINSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpminsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74751\n:VPMINSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpminsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74754\ndefine pcodeop vpminsb_avx512bw ;\n:VPMINSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpminsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74757\ndefine pcodeop vpminsw_avx512vl ;\n:VPMINSW XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpminsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74760\n:VPMINSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpminsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74763\ndefine pcodeop vpminsw_avx512bw ;\n:VPMINSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEA; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpminsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74995\ndefine pcodeop vpminsd_avx512vl ;\n:VPMINSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpminsd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74998\n:VPMINSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpminsd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75001\ndefine pcodeop vpminsd_avx512f ;\n:VPMINSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpminsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75004\ndefine pcodeop vpminsq_avx512vl ;\n:VPMINSQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpminsq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75007\n:VPMINSQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpminsq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75010\ndefine pcodeop vpminsq_avx512f ;\n:VPMINSQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpminsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75207\ndefine pcodeop vpminub_avx512vl ;\n:VPMINUB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpminub_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75210\n:VPMINUB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpminub_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75213\ndefine pcodeop vpminub_avx512bw ;\n:VPMINUB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_ZmmReg; byte=0xDA; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpminub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75216\ndefine pcodeop vpminuw_avx512vl ;\n:VPMINUW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpminuw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75219\n:VPMINUW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpminuw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75222\ndefine pcodeop vpminuw_avx512bw ;\n:VPMINUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpminuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75451\ndefine pcodeop vpminud_avx512vl ;\n:VPMINUD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpminud_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75454\n:VPMINUD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpminud_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75457\ndefine pcodeop vpminud_avx512f ;\n:VPMINUD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpminud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75460\ndefine pcodeop vpminuq_avx512vl ;\n:VPMINUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpminuq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75463\n:VPMINUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpminuq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75466\ndefine pcodeop vpminuq_avx512f ;\n:VPMINUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpminuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75796\ndefine pcodeop vpmovsxbw_avx512vl ;\n:VPMOVSXBW XmmReg1^XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovsxbw_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75799\n:VPMOVSXBW YmmReg1^YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovsxbw_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75802\ndefine pcodeop vpmovsxbw_avx512bw ;\n:VPMOVSXBW ZmmReg1^ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovsxbw_avx512bw( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVSX 4-340 PAGE 1460 LINE 75805\ndefine pcodeop vpmovsxbd_avx512vl ;\n:VPMOVSXBD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovsxbd_avx512vl( XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75819\n:VPMOVSXBD YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovsxbd_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75822\ndefine pcodeop vpmovsxbd_avx512f ;\n:VPMOVSXBD ZmmReg1^ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovsxbd_avx512f( XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75825\ndefine pcodeop vpmovsxbq_avx512vl ;\n:VPMOVSXBQ XmmReg1^XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovsxbq_avx512vl( XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75828\n:VPMOVSXBQ YmmReg1^YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovsxbq_avx512vl( XmmReg2_m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75831\ndefine pcodeop vpmovsxbq_avx512f ;\n:VPMOVSXBQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovsxbq_avx512f( XmmReg2_m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75834\ndefine pcodeop vpmovsxwd_avx512vl ;\n:VPMOVSXWD XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovsxwd_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75837\n:VPMOVSXWD YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovsxwd_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75840\ndefine pcodeop vpmovsxwd_avx512f ;\n:VPMOVSXWD ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovsxwd_avx512f( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75843\ndefine pcodeop vpmovsxwq_avx512vl ;\n:VPMOVSXWQ XmmReg1^XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovsxwq_avx512vl( XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75846\n:VPMOVSXWQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovsxwq_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75849\ndefine pcodeop vpmovsxwq_avx512f ;\n:VPMOVSXWQ ZmmReg1^ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovsxwq_avx512f( XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75852\ndefine pcodeop vpmovsxdq_avx512vl ;\n:VPMOVSXDQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovsxdq_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75855\n:VPMOVSXDQ YmmReg1^YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovsxdq_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVSX 4-341 PAGE 1461 LINE 75858\ndefine pcodeop vpmovsxdq_avx512f ;\n:VPMOVSXDQ ZmmReg1^ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovsxdq_avx512f( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76329\ndefine pcodeop vpmovzxbw_avx512vl ;\n:VPMOVZXBW XmmReg1^XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovzxbw_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76332\n:VPMOVZXBW YmmReg1^YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovzxbw_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76335\ndefine pcodeop vpmovzxbw_avx512bw ;\n:VPMOVZXBW ZmmReg1^ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovzxbw_avx512bw( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76338\ndefine pcodeop vpmovzxbd_avx512vl ;\n:VPMOVZXBD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovzxbd_avx512vl( XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76341\n:VPMOVZXBD YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovzxbd_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76344\ndefine pcodeop vpmovzxbd_avx512f ;\n:VPMOVZXBD ZmmReg1^ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovzxbd_avx512f( XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76347\ndefine pcodeop vpmovzxbq_avx512vl ;\n:VPMOVZXBQ XmmReg1^XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovzxbq_avx512vl( XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76350\n:VPMOVZXBQ YmmReg1^YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovzxbq_avx512vl( XmmReg2_m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76353\ndefine pcodeop vpmovzxbq_avx512f ;\n:VPMOVZXBQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovzxbq_avx512f( XmmReg2_m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76356\ndefine pcodeop vpmovzxwd_avx512vl ;\n:VPMOVZXWD XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovzxwd_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76359\n:VPMOVZXWD YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovzxwd_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76362\ndefine pcodeop vpmovzxwd_avx512f ;\n:VPMOVZXWD ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovzxwd_avx512f( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76365\ndefine pcodeop vpmovzxwq_avx512vl ;\n:VPMOVZXWQ XmmReg1^XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovzxwq_avx512vl( XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76368\n:VPMOVZXWQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovzxwq_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVZX 4-351 PAGE 1471 LINE 76371\ndefine pcodeop vpmovzxwq_avx512f ;\n:VPMOVZXWQ ZmmReg1^ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovzxwq_avx512f( XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMOVZX 4-352 PAGE 1472 LINE 76386\ndefine pcodeop vpmovzxdq_avx512vl ;\n:VPMOVZXDQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tXmmResult = vpmovzxdq_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMOVZX 4-352 PAGE 1472 LINE 76389\n:VPMOVZXDQ YmmReg1^YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tYmmResult = vpmovzxdq_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMOVZX 4-352 PAGE 1472 LINE 76392\ndefine pcodeop vpmovzxdq_avx512f ;\n:VPMOVZXDQ ZmmReg1^ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)\n{\n\tZmmResult = vpmovzxdq_avx512f( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULDQ 4-359 PAGE 1479 LINE 76794\ndefine pcodeop vpmuldq_avx512vl ;\n:VPMULDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmuldq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULDQ 4-359 PAGE 1479 LINE 76798\n:VPMULDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmuldq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULDQ 4-359 PAGE 1479 LINE 76802\ndefine pcodeop vpmuldq_avx512f ;\n:VPMULDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmuldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULHRSW 4-362 PAGE 1482 LINE 76934\ndefine pcodeop vpmulhrsw_avx512vl ;\n:VPMULHRSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmulhrsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULHRSW 4-362 PAGE 1482 LINE 76937\n:VPMULHRSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmulhrsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULHRSW 4-362 PAGE 1482 LINE 76940\ndefine pcodeop vpmulhrsw_avx512bw ;\n:VPMULHRSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0B; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmulhrsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULHUW 4-366 PAGE 1486 LINE 77147\ndefine pcodeop vpmulhuw_avx512vl ;\n:VPMULHUW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmulhuw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULHUW 4-366 PAGE 1486 LINE 77151\n:VPMULHUW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmulhuw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULHUW 4-366 PAGE 1486 LINE 77155\ndefine pcodeop vpmulhuw_avx512bw ;\n:VPMULHUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE4; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmulhuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULHW 4-370 PAGE 1490 LINE 77376\ndefine pcodeop vpmulhw_avx512vl ;\n:VPMULHW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmulhw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULHW 4-370 PAGE 1490 LINE 77379\n:VPMULHW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmulhw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULHW 4-370 PAGE 1490 LINE 77382\ndefine pcodeop vpmulhw_avx512bw ;\n:VPMULHW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmulhw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77582\ndefine pcodeop vpmulld_avx512vl ;\n:VPMULLD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmulld_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77585\n:VPMULLD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmulld_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77588\ndefine pcodeop vpmulld_avx512f ;\n:VPMULLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmulld_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77591\ndefine pcodeop vpmullq_avx512vl ;\n:VPMULLQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmullq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77594\n:VPMULLQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmullq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77597\ndefine pcodeop vpmullq_avx512dq ;\n:VPMULLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmullq_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULLW 4-378 PAGE 1498 LINE 77781\ndefine pcodeop vpmullw_avx512vl ;\n:VPMULLW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpmullw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULLW 4-378 PAGE 1498 LINE 77784\n:VPMULLW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpmullw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULLW 4-378 PAGE 1498 LINE 77787\ndefine pcodeop vpmullw_avx512bw ;\n:VPMULLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpmullw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PMULUDQ 4-382 PAGE 1502 LINE 77977\ndefine pcodeop vpmuludq_avx512vl ;\n:VPMULUDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpmuludq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PMULUDQ 4-382 PAGE 1502 LINE 77981\n:VPMULUDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpmuludq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PMULUDQ 4-382 PAGE 1502 LINE 77985\ndefine pcodeop vpmuludq_avx512f ;\n:VPMULUDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpmuludq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# POR 4-399 PAGE 1519 LINE 78854\ndefine pcodeop vpord_avx512vl ;\n:VPORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpord_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# POR 4-399 PAGE 1519 LINE 78857\n:VPORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpord_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# POR 4-399 PAGE 1519 LINE 78860\ndefine pcodeop vpord_avx512f ;\n:VPORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# POR 4-399 PAGE 1519 LINE 78863\ndefine pcodeop vporq_avx512vl ;\n:VPORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vporq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# POR 4-399 PAGE 1519 LINE 78866\n:VPORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vporq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# POR 4-399 PAGE 1519 LINE 78869\ndefine pcodeop vporq_avx512f ;\n:VPORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vporq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSADBW 4-408 PAGE 1528 LINE 79250\ndefine pcodeop vpsadbw_avx512vl ;\n:VPSADBW XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp:16 = vpsadbw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PSADBW 4-408 PAGE 1528 LINE 79255\n:VPSADBW YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsadbw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSADBW 4-408 PAGE 1528 LINE 79260\ndefine pcodeop vpsadbw_avx512bw ;\n:VPSADBW ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF6; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsadbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSHUFB 4-412 PAGE 1532 LINE 79466\ndefine pcodeop vpshufb_avx512vl ;\n:VPSHUFB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpshufb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSHUFB 4-412 PAGE 1532 LINE 79468\n:VPSHUFB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpshufb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSHUFB 4-412 PAGE 1532 LINE 79470\ndefine pcodeop vpshufb_avx512bw ;\n:VPSHUFB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x00; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpshufb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSHUFD 4-416 PAGE 1536 LINE 79656\ndefine pcodeop vpshufd_avx512vl ;\n:VPSHUFD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpshufd_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSHUFD 4-416 PAGE 1536 LINE 79659\n:VPSHUFD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpshufd_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSHUFD 4-416 PAGE 1536 LINE 79662\ndefine pcodeop vpshufd_avx512f ;\n:VPSHUFD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpshufd_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSHUFHW 4-420 PAGE 1540 LINE 79863\ndefine pcodeop vpshufhw_avx512vl ;\n:VPSHUFHW XmmReg1^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpshufhw_avx512vl( XmmReg2_m128, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSHUFHW 4-420 PAGE 1540 LINE 79866\n:VPSHUFHW YmmReg1^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpshufhw_avx512vl( YmmReg2_m256, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSHUFHW 4-420 PAGE 1540 LINE 79869\ndefine pcodeop vpshufhw_avx512bw ;\n:VPSHUFHW ZmmReg1^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpshufhw_avx512bw( ZmmReg2_m512, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSHUFLW 4-423 PAGE 1543 LINE 80038\ndefine pcodeop vpshuflw_avx512vl ;\n:VPSHUFLW XmmReg1^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpshuflw_avx512vl( XmmReg2_m128, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSHUFLW 4-423 PAGE 1543 LINE 80041\n:VPSHUFLW YmmReg1^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpshuflw_avx512vl( YmmReg2_m256, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSHUFLW 4-423 PAGE 1543 LINE 80044\ndefine pcodeop vpshuflw_avx512bw ;\n:VPSHUFLW ZmmReg1^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpshuflw_avx512bw( ZmmReg2_m512, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSLLDQ 4-431 PAGE 1551 LINE 80491\ndefine pcodeop vpslldq_avx512vl ;\n:VPSLLDQ evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=7 ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tlocal tmp:64 = vpslldq_avx512vl( XmmReg2_m128, imm8:1 );\n\tevexV5_ZmmReg = zext(tmp);\n}\n\n# PSLLDQ 4-431 PAGE 1551 LINE 80493\n:VPSLLDQ evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=7 ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tlocal tmp:64 = vpslldq_avx512vl( YmmReg2_m256, imm8:1 );\n\tevexV5_ZmmReg = zext(tmp);\n}\n\n# PSLLDQ 4-431 PAGE 1551 LINE 80495\ndefine pcodeop vpslldq_avx512bw ;\n:VPSLLDQ evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x73; reg_opcode=7 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tevexV5_ZmmReg = vpslldq_avx512bw( ZmmReg2_m512, imm8:1 );\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80667\ndefine pcodeop vpsllw_avx512vl ;\n:VPSLLW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsllw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80670\n:VPSLLW YmmReg1^YmmOpMask16, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsllw_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80673\ndefine pcodeop vpsllw_avx512bw ;\n:VPSLLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsllw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80676\n:VPSLLW evexV5_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=6 ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tXmmResult = vpsllw_avx512vl( XmmReg2_m128, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask16;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80678\n:VPSLLW evexV5_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=6 ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tYmmResult = vpsllw_avx512vl( YmmReg2_m256, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask16;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80680\n:VPSLLW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=6 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tZmmResult = vpsllw_avx512bw( ZmmReg2_m512, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask16;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80682\ndefine pcodeop vpslld_avx512vl ;\n:VPSLLD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpslld_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80685\n:VPSLLD YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpslld_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80688\ndefine pcodeop vpslld_avx512f ;\n:VPSLLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xF2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpslld_avx512f( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80691\n:VPSLLD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=6 ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vpslld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask32;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80694\n:VPSLLD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=6 ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vpslld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask32;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80697\n:VPSLLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=6 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vpslld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask32;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80700\ndefine pcodeop vpsllq_avx512vl ;\n:VPSLLQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsllq_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80703\n:VPSLLQ YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsllq_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80706\ndefine pcodeop vpsllq_avx512f ;\n:VPSLLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsllq_avx512f( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80721\n:VPSLLQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=6 ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vpsllq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask64;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80724\n:VPSLLQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=6 ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vpsllq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask64;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80727\n:VPSLLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=6 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vpsllq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask64;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81329\ndefine pcodeop vpsraw_avx512vl ;\n:VPSRAW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsraw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81332\n:VPSRAW YmmReg1^YmmOpMask16, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsraw_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81335\ndefine pcodeop vpsraw_avx512bw ;\n:VPSRAW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsraw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81350\n:VPSRAW evexV5_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=4 ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tXmmResult = vpsraw_avx512vl( XmmReg2_m128, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask16;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81352\n:VPSRAW evexV5_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=4 ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tYmmResult = vpsraw_avx512vl( YmmReg2_m256, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask16;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81354\n:VPSRAW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=4 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)\n{\n\tZmmResult = vpsraw_avx512bw( ZmmReg2_m512, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask16;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81356\ndefine pcodeop vpsrad_avx512vl ;\n:VPSRAD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsrad_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81359\n:VPSRAD YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsrad_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81362\ndefine pcodeop vpsrad_avx512f ;\n:VPSRAD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsrad_avx512f( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81365\n:VPSRAD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vpsrad_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask32;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81368\n:VPSRAD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vpsrad_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask32;\n\tevexV5_ZmmReg = zext(YmmResult);\n\t\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81371\n:VPSRAD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vpsrad_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask32;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81374\ndefine pcodeop vpsraq_avx512vl ;\n:VPSRAQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsraq_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81377\n:VPSRAQ YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsraq_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81380\ndefine pcodeop vpsraq_avx512f ;\n:VPSRAQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsraq_avx512f( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81383\n:VPSRAQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vpsraq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask64;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81386\n:VPSRAQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vpsraq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask64;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81389\n:VPSRAQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vpsraq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask64;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSRLDQ 4-455 PAGE 1575 LINE 81879\ndefine pcodeop vpsrldq_avx512vl ;\n:VPSRLDQ evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=3 ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp:64 = vpsrldq_avx512vl( XmmReg2_m128, imm8:1 );\n\tevexV5_ZmmReg = zext(tmp);\n}\n\n# PSRLDQ 4-455 PAGE 1575 LINE 81881\n:VPSRLDQ evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=3 ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp:64 = vpsrldq_avx512vl( YmmReg2_m256, imm8:1 );\n\tevexV5_ZmmReg = zext(tmp);\n}\n\n# PSRLDQ 4-455 PAGE 1575 LINE 81883\ndefine pcodeop vpsrldq_avx512bw ;\n:VPSRLDQ evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x73; reg_opcode=3 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tevexV5_ZmmReg = vpsrldq_avx512bw( ZmmReg2_m512, imm8:1 );\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82059\ndefine pcodeop vpsrlw_avx512vl ;\n:VPSRLW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsrlw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82062\n:VPSRLW YmmReg1^YmmOpMask16, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsrlw_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82065\ndefine pcodeop vpsrlw_avx512bw ;\n:VPSRLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsrlw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82068\n:VPSRLW evexV5_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=2 ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsrlw_avx512vl( XmmReg2_m128, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask16;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82070\n:VPSRLW evexV5_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=2 ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsrlw_avx512vl( YmmReg2_m256, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask16;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82072\n:VPSRLW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=2 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsrlw_avx512bw( ZmmReg2_m512, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask16;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82074\ndefine pcodeop vpsrld_avx512vl ;\n:VPSRLD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsrld_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82077\n:VPSRLD YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsrld_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82080\ndefine pcodeop vpsrld_avx512f ;\n:VPSRLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xD2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsrld_avx512f( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82084\n:VPSRLD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=2 ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vpsrld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask32;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82088\n:VPSRLD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=2 ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vpsrld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask32;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82091\n:VPSRLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=2 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vpsrld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask32;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82094\ndefine pcodeop vpsrlq_avx512vl ;\n:VPSRLQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tXmmResult = vpsrlq_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82097\n:VPSRLQ YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tYmmResult = vpsrlq_avx512vl( evexV5_YmmReg, XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82100\ndefine pcodeop vpsrlq_avx512f ;\n:VPSRLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)\n{\n\tZmmResult = vpsrlq_avx512f( evexV5_ZmmReg, XmmReg2_m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82115\n:VPSRLQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=2 ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vpsrlq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask64;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82119\n:VPSRLQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=2 ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vpsrlq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask64;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82122\n:VPSRLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=2 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vpsrlq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask64;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82702\ndefine pcodeop vpsubb_avx512vl ;\n:VPSUBB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsubb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82705\n:VPSUBB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsubb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82708\ndefine pcodeop vpsubb_avx512bw ;\n:VPSUBB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsubb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82711\ndefine pcodeop vpsubw_avx512vl ;\n:VPSUBW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsubw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82714\n:VPSUBW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsubw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82717\ndefine pcodeop vpsubw_avx512bw ;\n:VPSUBW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsubw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82733\ndefine pcodeop vpsubd_avx512vl ;\n:VPSUBD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsubd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82736\n:VPSUBD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsubd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82743\ndefine pcodeop vpsubd_avx512f ;\n:VPSUBD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsubd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBQ 4-476 PAGE 1596 LINE 83111\ndefine pcodeop vpsubq_avx512vl ;\n:VPSUBQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsubq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBQ 4-476 PAGE 1596 LINE 83114\n:VPSUBQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsubq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBQ 4-476 PAGE 1596 LINE 83117\ndefine pcodeop vpsubq_avx512f ;\n:VPSUBQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xFB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsubq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83270\ndefine pcodeop vpsubsb_avx512vl ;\n:VPSUBSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsubsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83274\n:VPSUBSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsubsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83278\ndefine pcodeop vpsubsb_avx512bw ;\n:VPSUBSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsubsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83282\ndefine pcodeop vpsubsw_avx512vl ;\n:VPSUBSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsubsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83286\n:VPSUBSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsubsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBSB/PSUBSW 4-480 PAGE 1600 LINE 83302\ndefine pcodeop psubsw_avx512bw ;\n:PSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n{\n\tZmmReg1 = psubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83510\ndefine pcodeop vpsubusb_avx512vl ;\n:VPSUBUSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsubusb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83514\n:VPSUBUSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsubusb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83518\ndefine pcodeop vpsubusb_avx512bw ;\n:VPSUBUSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsubusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83522\ndefine pcodeop vpsubusw_avx512vl ;\n:VPSUBUSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsubusw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83526\n:VPSUBUSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsubusw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PSUBUSB/PSUBUSW 4-484 PAGE 1604 LINE 83543\ndefine pcodeop vpsubusw_avx512bw ;\n:VPSUBUSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsubusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83948\ndefine pcodeop vpunpckhbw_avx512vl ;\n:VPUNPCKHBW XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpunpckhbw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83952\ndefine pcodeop vpunpckhwd_avx512vl ;\n:VPUNPCKHWD XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpunpckhwd_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83955\ndefine pcodeop vpunpckhdq_avx512vl ;\n:VPUNPCKHDQ XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpunpckhdq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83958\ndefine pcodeop vpunpckhqdq_avx512vl ;\n:VPUNPCKHQDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpunpckhqdq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83974\n:VPUNPCKHBW YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpunpckhbw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83977\n:VPUNPCKHWD YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpunpckhwd_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83980\n:VPUNPCKHDQ YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpunpckhdq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83984\n:VPUNPCKHQDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpunpckhqdq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83988\ndefine pcodeop vpunpckhbw_avx512bw ;\n:VPUNPCKHBW ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x68; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpunpckhbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83991\ndefine pcodeop vpunpckhwd_avx512bw ;\n:VPUNPCKHWD ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x69; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpunpckhwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83994\ndefine pcodeop vpunpckhdq_avx512f ;\n:VPUNPCKHDQ ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpunpckhdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83997\ndefine pcodeop vpunpckhqdq_avx512f ;\n:VPUNPCKHQDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpunpckhqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84553\ndefine pcodeop vpunpcklbw_avx512vl ;\n:VPUNPCKLBW XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpunpcklbw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84556\ndefine pcodeop vpunpcklwd_avx512vl ;\n:VPUNPCKLWD XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpunpcklwd_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84559\ndefine pcodeop vpunpckldq_avx512vl ;\n:VPUNPCKLDQ XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpunpckldq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84562\ndefine pcodeop vpunpcklqdq_avx512vl ;\n:VPUNPCKLQDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpunpcklqdq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84578\n:VPUNPCKLBW YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpunpcklbw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84581\n:VPUNPCKLWD YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpunpcklwd_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84584\n:VPUNPCKLDQ YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpunpckldq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84587\n:VPUNPCKLQDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpunpcklqdq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84590\ndefine pcodeop vpunpcklbw_avx512bw ;\n:VPUNPCKLBW ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x60; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpunpcklbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84593\ndefine pcodeop vpunpcklwd_avx512bw ;\n:VPUNPCKLWD ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x61; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpunpcklwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84596\ndefine pcodeop vpunpckldq_avx512f ;\n:VPUNPCKLDQ ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x62; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpunpckldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84599\ndefine pcodeop vpunpcklqdq_avx512f ;\n:VPUNPCKLQDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpunpcklqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85503\ndefine pcodeop vpxord_avx512vl ;\n:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpxord_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85505\n:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpxord_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85507\ndefine pcodeop vpxord_avx512f ;\n:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpxord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85514\ndefine pcodeop vpxorq_avx512vl ;\n:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpxorq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85521\n:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpxorq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PXOR 4-518 PAGE 1638 LINE 85523\ndefine pcodeop vpxorq_avx512f ;\n:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpxorq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# SHUFPD 4-617 PAGE 1737 LINE 90231\ndefine pcodeop vshufpd_avx512vl ;\n:VSHUFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vshufpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SHUFPD 4-617 PAGE 1737 LINE 90235\n:VSHUFPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vshufpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# SHUFPD 4-617 PAGE 1737 LINE 90239\ndefine pcodeop vshufpd_avx512f ;\n:VSHUFPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vshufpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# SHUFPS 4-622 PAGE 1742 LINE 90489\ndefine pcodeop vshufps_avx512vl ;\n:VSHUFPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vshufps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SHUFPS 4-622 PAGE 1742 LINE 90493\n:VSHUFPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vshufps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# SHUFPS 4-622 PAGE 1742 LINE 90497\ndefine pcodeop vshufps_avx512f ;\n:VSHUFPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vshufps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# SQRTPD 4-632 PAGE 1752 LINE 91007\ndefine pcodeop vsqrtpd_avx512vl ;\n:VSQRTPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vsqrtpd_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SQRTPD 4-632 PAGE 1752 LINE 91010\n:VSQRTPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vsqrtpd_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# SQRTPD 4-632 PAGE 1752 LINE 91013\ndefine pcodeop vsqrtpd_avx512f ;\n:VSQRTPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vsqrtpd_avx512f( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# SQRTPS 4-635 PAGE 1755 LINE 91139\ndefine pcodeop vsqrtps_avx512vl ;\n:VSQRTPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vsqrtps_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SQRTPS 4-635 PAGE 1755 LINE 91142\n:VSQRTPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vsqrtps_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# SQRTPS 4-635 PAGE 1755 LINE 91145\ndefine pcodeop vsqrtps_avx512f ;\n:VSQRTPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vsqrtps_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# SQRTSD 4-638 PAGE 1758 LINE 91276\ndefine pcodeop vsqrtsd_avx512f ;\n:VSQRTSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vsqrtsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SQRTSS 4-640 PAGE 1760 LINE 91371\ndefine pcodeop vsqrtss_avx512f ;\n:VSQRTSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vsqrtss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SUBPD 4-656 PAGE 1776 LINE 92120\ndefine pcodeop vsubpd_avx512vl ;\n:VSUBPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vsubpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SUBPD 4-656 PAGE 1776 LINE 92123\n:VSUBPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vsubpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# SUBPD 4-656 PAGE 1776 LINE 92126\ndefine pcodeop vsubpd_avx512f ;\n:VSUBPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vsubpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# SUBPS 4-659 PAGE 1779 LINE 92269\ndefine pcodeop vsubps_avx512vl ;\n:VSUBPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vsubps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SUBPS 4-659 PAGE 1779 LINE 92272\n:VSUBPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vsubps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# SUBPS 4-659 PAGE 1779 LINE 92275\ndefine pcodeop vsubps_avx512f ;\n:VSUBPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vsubps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# SUBSD 4-662 PAGE 1782 LINE 92421\ndefine pcodeop vsubsd_avx512f ;\n:VSUBSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vsubsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# SUBSS 4-664 PAGE 1784 LINE 92514\ndefine pcodeop vsubss_avx512f ;\n:VSUBSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vsubss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# UCOMISD 4-683 PAGE 1803 LINE 93424\ndefine pcodeop vucomisd_avx512f ;\n:VUCOMISD XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vucomisd_avx512f( XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n\t# TODO set flags AF, CF, OF, PF, SF, ZF\n}\n\n# UCOMISS 4-685 PAGE 1805 LINE 93507\ndefine pcodeop vucomiss_avx512f ;\n:VUCOMISS XmmReg1, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vucomiss_avx512f( XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n\t# TODO set flags AF, CF, OF, PF, SF, ZF\n}\n\n# UNPCKHPD 4-688 PAGE 1808 LINE 93629\ndefine pcodeop vunpckhpd_avx512vl ;\n:VUNPCKHPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vunpckhpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# UNPCKHPD 4-688 PAGE 1808 LINE 93632\n:VUNPCKHPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vunpckhpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# UNPCKHPD 4-688 PAGE 1808 LINE 93635\ndefine pcodeop vunpckhpd_avx512f ;\n:VUNPCKHPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vunpckhpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# UNPCKHPS 4-692 PAGE 1812 LINE 93813\ndefine pcodeop vunpckhps_avx512vl ;\n:VUNPCKHPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vunpckhps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# UNPCKHPS 4-692 PAGE 1812 LINE 93817\n:VUNPCKHPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vunpckhps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# UNPCKHPS 4-692 PAGE 1812 LINE 93821\ndefine pcodeop vunpckhps_avx512f ;\n:VUNPCKHPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vunpckhps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# UNPCKLPD 4-696 PAGE 1816 LINE 94045\ndefine pcodeop vunpcklpd_avx512vl ;\n:VUNPCKLPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vunpcklpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# UNPCKLPD 4-696 PAGE 1816 LINE 94048\n:VUNPCKLPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vunpcklpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# UNPCKLPD 4-696 PAGE 1816 LINE 94051\ndefine pcodeop vunpcklpd_avx512f ;\n:VUNPCKLPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vunpcklpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# UNPCKLPS 4-700 PAGE 1820 LINE 94231\ndefine pcodeop vunpcklps_avx512vl ;\n:VUNPCKLPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vunpcklps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# UNPCKLPS 4-700 PAGE 1820 LINE 94234\n:VUNPCKLPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vunpcklps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# UNPCKLPS 4-700 PAGE 1820 LINE 94237\ndefine pcodeop vunpcklps_avx512f ;\n:VUNPCKLPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vunpcklps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94615\ndefine pcodeop valignd_avx512vl ;\n:VALIGND XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x03; ((XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst); imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = valignd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94619\ndefine pcodeop valignq_avx512vl ;\n:VALIGNQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x03; ((XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst); imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = valignq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94623\n:VALIGND YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x03; ((YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst); imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = valignd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94627\n:VALIGNQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x03; ((YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst); imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = valignq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94631\ndefine pcodeop valignd_avx512f ;\n:VALIGND ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x03; ((ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst); imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = valignd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94635\ndefine pcodeop valignq_avx512f ;\n:VALIGNQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x03; ((ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst); imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = valignq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94787\ndefine pcodeop vblendmpd_avx512vl ;\n:VBLENDMPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vblendmpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94790\n:VBLENDMPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vblendmpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94793\ndefine pcodeop vblendmpd_avx512f ;\n:VBLENDMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vblendmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94796\ndefine pcodeop vblendmps_avx512vl ;\n:VBLENDMPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vblendmps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94799\n:VBLENDMPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vblendmps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94802\ndefine pcodeop vblendmps_avx512f ;\n:VBLENDMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vblendmps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94917\ndefine pcodeop vbroadcastsd_avx512vl ;\n:VBROADCASTSD YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcastsd_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94920\ndefine pcodeop vbroadcastsd_avx512f ;\n:VBROADCASTSD ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastsd_avx512f( XmmReg2_m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94923\ndefine pcodeop vbroadcastf32x2_avx512vl ;\n:VBROADCASTF32X2 YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcastf32x2_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94926\ndefine pcodeop vbroadcastf32x2_avx512dq ;\n:VBROADCASTF32X2 ZmmReg1^ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastf32x2_avx512dq( XmmReg2_m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94929\ndefine pcodeop vbroadcastss_avx512vl ;\n:VBROADCASTSS XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tXmmResult = vbroadcastss_avx512vl( XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94932\n:VBROADCASTSS YmmReg1^YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcastss_avx512vl( XmmReg2_m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94935\ndefine pcodeop vbroadcastss_avx512f ;\n:VBROADCASTSS ZmmReg1^ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastss_avx512f( XmmReg2_m32 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94938\ndefine pcodeop vbroadcastf32x4_avx512vl ;\n:VBROADCASTF32X4 YmmReg1^YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcastf32x4_avx512vl( m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94941\ndefine pcodeop vbroadcastf32x4_avx512f ;\n:VBROADCASTF32X4 ZmmReg1^ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastf32x4_avx512f( m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94944\ndefine pcodeop vbroadcastf64x2_avx512vl ;\n:VBROADCASTF64X2 YmmReg1^YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcastf64x2_avx512vl( m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94947\ndefine pcodeop vbroadcastf64x2_avx512dq ;\n:VBROADCASTF64X2 ZmmReg1^ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastf64x2_avx512dq( m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94950\ndefine pcodeop vbroadcastf32x8_avx512dq ;\n:VBROADCASTF32X8 ZmmReg1^ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1B; (ZmmReg1 & ZmmOpMask32) ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastf32x8_avx512dq( m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VBROADCAST 5-12 PAGE 1836 LINE 94953\ndefine pcodeop vbroadcastf64x4_avx512f ;\n:VBROADCASTF64X4 ZmmReg1^ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1B; (ZmmReg1 & ZmmOpMask64) ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcastf64x4_avx512f( m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCASTM 5-19 PAGE 1843 LINE 95303\ndefine pcodeop vpbroadcastmb2q_avx512vl ;\n:VPBROADCASTMB2Q XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x2A; (XmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:16 = vpbroadcastmb2q_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBROADCASTM 5-19 PAGE 1843 LINE 95305\n:VPBROADCASTMB2Q YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x2A; (YmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:32 = vpbroadcastmb2q_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBROADCASTM 5-19 PAGE 1843 LINE 95307\ndefine pcodeop vpbroadcastmb2q_avx512cd ;\n:VPBROADCASTMB2Q ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x2A; ZmmReg1 & KReg_rm\n{\n\tZmmReg1 = vpbroadcastmb2q_avx512cd( KReg_rm );\n}\n\n# VPBROADCASTM 5-19 PAGE 1843 LINE 95309\ndefine pcodeop vpbroadcastmw2d_avx512vl ;\n:VPBROADCASTMW2D XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x3A; (XmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:16 = vpbroadcastmw2d_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBROADCASTM 5-19 PAGE 1843 LINE 95311\n:VPBROADCASTMW2D YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x3A; (YmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:32 = vpbroadcastmw2d_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBROADCASTM 5-19 PAGE 1843 LINE 95313\ndefine pcodeop vpbroadcastmw2d_avx512cd ;\n:VPBROADCASTMW2D ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x3A; ZmmReg1 & KReg_rm\n{\n\tZmmReg1 = vpbroadcastmw2d_avx512cd( KReg_rm );\n}\n\n# VCOMPRESSPD 5-21 PAGE 1845 LINE 95380\ndefine pcodeop vcompresspd_avx512vl ;\n:VCOMPRESSPD XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tXmmResult = vcompresspd_avx512vl( XmmReg1, XmmOpMask );\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VCOMPRESSPD m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmMask = m128;\n\tbuild XmmOpMask;\n\tXmmResult = vcompresspd_avx512vl( XmmReg1, XmmOpMask );\n\tm128 = XmmResult;\n}\n\n# VCOMPRESSPD 5-21 PAGE 1845 LINE 95383\n:VCOMPRESSPD YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask;\n\tYmmResult = vcompresspd_avx512vl( YmmReg1, YmmOpMask );\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VCOMPRESSPD m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmMask = m256;\n\tbuild YmmOpMask;\n\tYmmResult = vcompresspd_avx512vl( YmmReg1, YmmOpMask );\n\tm256 = YmmResult;\n}\n\n# VCOMPRESSPD 5-21 PAGE 1845 LINE 95386\ndefine pcodeop vcompresspd_avx512f ;\n:VCOMPRESSPD ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmMask = ZmmReg2;\n\tbuild ZmmOpMask;\n\tZmmResult = vcompresspd_avx512f( ZmmReg1, ZmmOpMask );\n\tZmmReg2 = ZmmResult;\n}\n\n:VCOMPRESSPD m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmMask = m512;\n\tbuild ZmmOpMask;\n\tZmmResult = vcompresspd_avx512f( ZmmReg1, ZmmOpMask );\n\tm512 = ZmmResult;\n}\n\n# VCOMPRESSPS 5-23 PAGE 1847 LINE 95481\ndefine pcodeop vcompressps_avx512vl ;\n:VCOMPRESSPS XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tXmmResult = vcompressps_avx512vl( XmmReg1, XmmOpMask );\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VCOMPRESSPS m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmMask = m128;\n\tbuild XmmOpMask;\n\tXmmResult = vcompressps_avx512vl( XmmReg1, XmmOpMask );\n\tm128 = XmmResult;\n}\n\n# VCOMPRESSPS 5-23 PAGE 1847 LINE 95484\n:VCOMPRESSPS YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask;\n\tYmmResult = vcompressps_avx512vl( YmmReg1, YmmOpMask );\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VCOMPRESSPS m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmMask = m256;\n\tbuild YmmOpMask;\n\tYmmResult = vcompressps_avx512vl( YmmReg1, YmmOpMask );\n\tm256 = YmmResult;\n}\n\n# VCOMPRESSPS 5-23 PAGE 1847 LINE 95487\ndefine pcodeop vcompressps_avx512f ;\n:VCOMPRESSPS ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmMask = ZmmReg2;\n\tbuild ZmmOpMask;\n\tZmmResult = vcompressps_avx512f( ZmmReg1, ZmmOpMask );\n\tZmmReg2 = ZmmResult;\n}\n\n:VCOMPRESSPS m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmMask = m512;\n\tbuild ZmmOpMask;\n\tZmmResult = vcompressps_avx512f( ZmmReg1, ZmmOpMask );\n\tm512 = ZmmResult;\n}\n\n# VCVTPD2QQ 5-25 PAGE 1849 LINE 95583\ndefine pcodeop vcvtpd2qq_avx512vl ;\n:VCVTPD2QQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2qq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPD2QQ 5-25 PAGE 1849 LINE 95586\n:VCVTPD2QQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtpd2qq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPD2QQ 5-25 PAGE 1849 LINE 95589\ndefine pcodeop vcvtpd2qq_avx512dq ;\n:VCVTPD2QQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtpd2qq_avx512dq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPD2UDQ 5-28 PAGE 1852 LINE 95706\ndefine pcodeop vcvtpd2udq_avx512vl ;\n:VCVTPD2UDQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2udq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPD2UDQ 5-28 PAGE 1852 LINE 95709\n:VCVTPD2UDQ XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2udq_avx512vl( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPD2UDQ 5-28 PAGE 1852 LINE 95712\ndefine pcodeop vcvtpd2udq_avx512f ;\n:VCVTPD2UDQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtpd2udq_avx512f( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPD2UQQ 5-31 PAGE 1855 LINE 95833\ndefine pcodeop vcvtpd2uqq_avx512vl ;\n:VCVTPD2UQQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtpd2uqq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPD2UQQ 5-31 PAGE 1855 LINE 95836\n:VCVTPD2UQQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtpd2uqq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPD2UQQ 5-31 PAGE 1855 LINE 95839\ndefine pcodeop vcvtpd2uqq_avx512dq ;\n:VCVTPD2UQQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtpd2uqq_avx512dq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2PS 5-34 PAGE 1858 LINE 95963\ndefine pcodeop vcvtph2ps_avx512vl ;\n:VCVTPH2PS XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vcvtph2ps_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2PS 5-34 PAGE 1858 LINE 95966\n:VCVTPH2PS YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vcvtph2ps_avx512vl( XmmReg2_m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2PS 5-34 PAGE 1858 LINE 95969\ndefine pcodeop vcvtph2ps_avx512f ;\n:VCVTPH2PS ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tZmmResult = vcvtph2ps_avx512f( YmmReg2_m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96116\n# INFO mnemonic VCVTPS2PH was found in ../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96119\n# INFO mnemonic VCVTPS2PH was found in ../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96122\n# INFO mnemonic VCVTPS2PH was found in ../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc\n\n# VCVTPS2UDQ 5-41 PAGE 1865 LINE 96305\ndefine pcodeop vcvtps2udq_avx512vl ;\n:VCVTPS2UDQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtps2udq_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPS2UDQ 5-41 PAGE 1865 LINE 96309\n:VCVTPS2UDQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtps2udq_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPS2UDQ 5-41 PAGE 1865 LINE 96313\ndefine pcodeop vcvtps2udq_avx512f ;\n:VCVTPS2UDQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtps2udq_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPS2QQ 5-44 PAGE 1868 LINE 96434\ndefine pcodeop vcvtps2qq_avx512vl ;\n:VCVTPS2QQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tXmmResult = vcvtps2qq_avx512vl( XmmReg2_m64_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPS2QQ 5-44 PAGE 1868 LINE 96437\n:VCVTPS2QQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvtps2qq_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPS2QQ 5-44 PAGE 1868 LINE 96440\ndefine pcodeop vcvtps2qq_avx512dq ;\n:VCVTPS2QQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tZmmResult = vcvtps2qq_avx512dq( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPS2UQQ 5-47 PAGE 1871 LINE 96560\ndefine pcodeop vcvtps2uqq_avx512vl ;\n:VCVTPS2UQQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tXmmResult = vcvtps2uqq_avx512vl( XmmReg2_m64_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPS2UQQ 5-47 PAGE 1871 LINE 96563\n:VCVTPS2UQQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvtps2uqq_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPS2UQQ 5-47 PAGE 1871 LINE 96566\ndefine pcodeop vcvtps2uqq_avx512dq ;\n:VCVTPS2UQQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tZmmResult = vcvtps2uqq_avx512dq( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTQQ2PD 5-50 PAGE 1874 LINE 96686\ndefine pcodeop vcvtqq2pd_avx512vl ;\n:VCVTQQ2PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtqq2pd_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTQQ2PD 5-50 PAGE 1874 LINE 96689\n:VCVTQQ2PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtqq2pd_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTQQ2PD 5-50 PAGE 1874 LINE 96692\ndefine pcodeop vcvtqq2pd_avx512dq ;\n:VCVTQQ2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtqq2pd_avx512dq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTQQ2PS 5-52 PAGE 1876 LINE 96797\ndefine pcodeop vcvtqq2ps_avx512vl ;\n:VCVTQQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtqq2ps_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTQQ2PS 5-52 PAGE 1876 LINE 96800\n:VCVTQQ2PS XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtqq2ps_avx512vl( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTQQ2PS 5-52 PAGE 1876 LINE 96803\ndefine pcodeop vcvtqq2ps_avx512dq ;\n:VCVTQQ2PS YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtqq2ps_avx512dq( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTSD2USI 5-54 PAGE 1878 LINE 96907\ndefine pcodeop vcvtsd2usi_avx512f ;\n:VCVTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x79; Reg32 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvtsd2usi_avx512f( XmmReg2_m64 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# VCVTSD2USI 5-54 PAGE 1878 LINE 96909\n@ifdef IA64\n:VCVTSD2USI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x79; Reg64 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvtsd2usi_avx512f( XmmReg2_m64 );\n}\n@endif\n\n# VCVTSS2USI 5-55 PAGE 1879 LINE 96967\ndefine pcodeop vcvtss2usi_avx512f ;\n:VCVTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x79; Reg32 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvtss2usi_avx512f( XmmReg2_m32 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# VCVTSS2USI 5-55 PAGE 1879 LINE 96969\n@ifdef IA64\n:VCVTSS2USI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x79; Reg64 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvtss2usi_avx512f( XmmReg2_m32 );\n}\n@endif\n\n# VCVTTPD2QQ 5-57 PAGE 1881 LINE 97040\ndefine pcodeop vcvttpd2qq_avx512vl ;\n:VCVTTPD2QQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttpd2qq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPD2QQ 5-57 PAGE 1881 LINE 97043\n:VCVTTPD2QQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvttpd2qq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPD2QQ 5-57 PAGE 1881 LINE 97046\ndefine pcodeop vcvttpd2qq_avx512dq ;\n:VCVTTPD2QQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvttpd2qq_avx512dq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97147\ndefine pcodeop vcvttpd2udq_avx512vl ;\n:VCVTTPD2UDQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttpd2udq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97152\n:VCVTTPD2UDQ XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttpd2udq_avx512vl( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97156\ndefine pcodeop vcvttpd2udq_avx512f ;\n:VCVTTPD2UDQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvttpd2udq_avx512f( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97272\ndefine pcodeop vcvttpd2uqq_avx512vl ;\n:VCVTTPD2UQQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttpd2uqq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97276\n:VCVTTPD2UQQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvttpd2uqq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97280\ndefine pcodeop vcvttpd2uqq_avx512dq ;\n:VCVTTPD2UQQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvttpd2uqq_avx512dq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97385\ndefine pcodeop vcvttps2udq_avx512vl ;\n:VCVTTPS2UDQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvttps2udq_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97389\n:VCVTTPS2UDQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvttps2udq_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97393\ndefine pcodeop vcvttps2udq_avx512f ;\n:VCVTTPS2UDQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvttps2udq_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPS2QQ 5-66 PAGE 1890 LINE 97497\ndefine pcodeop vcvttps2qq_avx512vl ;\n:VCVTTPS2QQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tXmmResult = vcvttps2qq_avx512vl( XmmReg2_m64_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPS2QQ 5-66 PAGE 1890 LINE 97500\n:VCVTTPS2QQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvttps2qq_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPS2QQ 5-66 PAGE 1890 LINE 97503\ndefine pcodeop vcvttps2qq_avx512dq ;\n:VCVTTPS2QQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tZmmResult = vcvttps2qq_avx512dq( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97608\ndefine pcodeop vcvttps2uqq_avx512vl ;\n:VCVTTPS2UQQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tXmmResult = vcvttps2uqq_avx512vl( XmmReg2_m64_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97611\n:VCVTTPS2UQQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvttps2uqq_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97615\ndefine pcodeop vcvttps2uqq_avx512dq ;\n:VCVTTPS2UQQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tZmmResult = vcvttps2uqq_avx512dq( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTSD2USI 5-70 PAGE 1894 LINE 97722\ndefine pcodeop vcvttsd2usi_avx512f ;\n:VCVTTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x78; Reg32 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvttsd2usi_avx512f( XmmReg2_m64 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# VCVTTSD2USI 5-70 PAGE 1894 LINE 97725\n@ifdef IA64\n:VCVTTSD2USI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x78; Reg64 ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvttsd2usi_avx512f( XmmReg2_m64 );\n}\n@endif\n\n# VCVTTSS2USI 5-71 PAGE 1895 LINE 97782\ndefine pcodeop vcvttss2usi_avx512f ;\n:VCVTTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x78; Reg32 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg32 = vcvttss2usi_avx512f( XmmReg2_m32 );\n\t# TODO Reg64 = zext(Reg32)\n}\n\n# VCVTTSS2USI 5-71 PAGE 1895 LINE 97785\n@ifdef IA64\n:VCVTTSS2USI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x78; Reg64 ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)\n{\n\tReg64 = vcvttss2usi_avx512f( XmmReg2_m32 );\n}\n@endif\n\n# VCVTUDQ2PD 5-73 PAGE 1897 LINE 97852\ndefine pcodeop vcvtudq2pd_avx512vl ;\n:VCVTUDQ2PD XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tXmmResult = vcvtudq2pd_avx512vl( XmmReg2_m64_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUDQ2PD 5-73 PAGE 1897 LINE 97855\n:VCVTUDQ2PD YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tYmmResult = vcvtudq2pd_avx512vl( XmmReg2_m128_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTUDQ2PD 5-73 PAGE 1897 LINE 97859\ndefine pcodeop vcvtudq2pd_avx512f ;\n:VCVTUDQ2PD ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)\n{\n\tZmmResult = vcvtudq2pd_avx512f( YmmReg2_m256_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTUDQ2PS 5-75 PAGE 1899 LINE 97962\ndefine pcodeop vcvtudq2ps_avx512vl ;\n:VCVTUDQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtudq2ps_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUDQ2PS 5-75 PAGE 1899 LINE 97965\n:VCVTUDQ2PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtudq2ps_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTUDQ2PS 5-75 PAGE 1899 LINE 97968\ndefine pcodeop vcvtudq2ps_avx512f ;\n:VCVTUDQ2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtudq2ps_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTUQQ2PD 5-77 PAGE 1901 LINE 98078\ndefine pcodeop vcvtuqq2pd_avx512vl ;\n:VCVTUQQ2PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtuqq2pd_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUQQ2PD 5-77 PAGE 1901 LINE 98081\n:VCVTUQQ2PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtuqq2pd_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTUQQ2PD 5-77 PAGE 1901 LINE 98084\ndefine pcodeop vcvtuqq2pd_avx512dq ;\n:VCVTUQQ2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vcvtuqq2pd_avx512dq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTUQQ2PS 5-79 PAGE 1903 LINE 98193\ndefine pcodeop vcvtuqq2ps_avx512vl ;\n:VCVTUQQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtuqq2ps_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUQQ2PS 5-79 PAGE 1903 LINE 98196\n:VCVTUQQ2PS XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vcvtuqq2ps_avx512vl( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUQQ2PS 5-79 PAGE 1903 LINE 98199\ndefine pcodeop vcvtuqq2ps_avx512dq ;\n:VCVTUQQ2PS YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vcvtuqq2ps_avx512dq( ZmmReg2_m512_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTUSI2SD 5-81 PAGE 1905 LINE 98308\ndefine pcodeop vcvtusi2sd_avx512f ;\n:VCVTUSI2SD XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtusi2sd_avx512f( evexV5_XmmReg, rm32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VCVTUSI2SD 5-81 PAGE 1905 LINE 98311\n@ifdef IA64\n:VCVTUSI2SD XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtusi2sd_avx512f( evexV5_XmmReg, rm64 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# VCVTUSI2SS 5-83 PAGE 1907 LINE 98381\ndefine pcodeop vcvtusi2ss_avx512f ;\n:VCVTUSI2SS XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtusi2ss_avx512f( evexV5_XmmReg, rm32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VCVTUSI2SS 5-83 PAGE 1907 LINE 98383\n@ifdef IA64\n:VCVTUSI2SS XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vcvtusi2ss_avx512f( evexV5_XmmReg, rm64 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# VDBPSADBW 5-85 PAGE 1909 LINE 98455\ndefine pcodeop vdbpsadbw_avx512vl ;\n:VDBPSADBW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vdbpsadbw_avx512vl( evexV5_XmmReg, XmmReg2_m128, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VDBPSADBW 5-85 PAGE 1909 LINE 98460\n:VDBPSADBW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vdbpsadbw_avx512vl( evexV5_YmmReg, YmmReg2_m256, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VDBPSADBW 5-85 PAGE 1909 LINE 98465\ndefine pcodeop vdbpsadbw_avx512bw ;\n:VDBPSADBW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x42; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vdbpsadbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VEXPANDPD 5-89 PAGE 1913 LINE 98660\ndefine pcodeop vexpandpd_avx512vl ;\n:VEXPANDPD XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tXmmResult = vexpandpd_avx512vl( XmmReg2_m128, XmmOpMask );\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VEXPANDPD 5-89 PAGE 1913 LINE 98663\n:VEXPANDPD YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask;\n\tYmmResult = vexpandpd_avx512vl( YmmReg2_m256, YmmOpMask );\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VEXPANDPD 5-89 PAGE 1913 LINE 98665\ndefine pcodeop vexpandpd_avx512f ;\n:VEXPANDPD ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask;\n\tZmmResult = vexpandpd_avx512f( ZmmReg2_m512, ZmmOpMask );\n\tZmmReg1 = ZmmResult;\n}\n\n# VEXPANDPS 5-91 PAGE 1915 LINE 98748\ndefine pcodeop vexpandps_avx512vl ;\n:VEXPANDPS XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tXmmResult = vexpandps_avx512vl( XmmReg2_m128, XmmOpMask );\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VEXPANDPS 5-91 PAGE 1915 LINE 98750\n:VEXPANDPS YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask;\n\tYmmResult = vexpandps_avx512vl( YmmReg2_m256 );\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VEXPANDPS 5-91 PAGE 1915 LINE 98752\ndefine pcodeop vexpandps_avx512f ;\n:VEXPANDPS ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask;\n\tZmmResult = vexpandps_avx512f( ZmmReg2_m512, ZmmOpMask );\n\tZmmReg1 = ZmmResult;\n}\n\n# VEXP2PD 5-95 PAGE 1919 LINE 98936\ndefine pcodeop vexp2pd_avx512er ;\n:VEXP2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vexp2pd_avx512er( ZmmReg1, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VEXP2PS 5-97 PAGE 1921 LINE 99019\ndefine pcodeop vexp2ps_avx512er ;\n:VEXP2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vexp2ps_avx512er( ZmmReg1, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99105\ndefine pcodeop vextractf32x4_avx512vl ;\n:VEXTRACTF32X4 XmmReg2^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf32x4_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTF32X4 m128^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf32x4_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99108\ndefine pcodeop vextractf32x4_avx512f ;\n:VEXTRACTF32x4 XmmReg2^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf32x4_avx512f( ZmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTF32x4 m128^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf32x4_avx512f( ZmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99111\ndefine pcodeop vextractf64x2_avx512vl ;\n:VEXTRACTF64X2 XmmReg2^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf64x2_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTF64X2 m128^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf64x2_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99114\ndefine pcodeop vextractf64x2_avx512dq ;\n:VEXTRACTF64X2 XmmReg2^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf64x2_avx512dq( ZmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTF64X2 m128^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextractf64x2_avx512dq( ZmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99117\ndefine pcodeop vextractf32x8_avx512dq ;\n:VEXTRACTF32X8 YmmReg2^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextractf32x8_avx512dq( ZmmReg1, imm8:1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VEXTRACTF32X8 m256^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 ... & m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextractf32x8_avx512dq( ZmmReg1, imm8:1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = YmmResult;\n}\n\n# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99120\ndefine pcodeop vextractf64x4_avx512f ;\n:VEXTRACTF64x4 YmmReg2^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextractf64x4_avx512f( ZmmReg1, imm8:1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask64;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VEXTRACTF64x4 m256^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 ... & m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextractf64x4_avx512f( ZmmReg1, imm8:1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask64;\n\tm256 = YmmResult;\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99435\ndefine pcodeop vextracti32x4_avx512vl ;\n:VEXTRACTI32X4 XmmReg2^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti32x4_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTI32X4 m128^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti32x4_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99438\ndefine pcodeop vextracti32x4_avx512f ;\n:VEXTRACTI32x4 XmmReg2^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti32x4_avx512f( ZmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTI32x4 m128^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti32x4_avx512f( ZmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99441\ndefine pcodeop vextracti64x2_avx512vl ;\n:VEXTRACTI64X2 XmmReg2^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti64x2_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTI64X2 m128^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti64x2_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99444\ndefine pcodeop vextracti64x2_avx512dq ;\n:VEXTRACTI64X2 XmmReg2^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti64x2_avx512dq( ZmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VEXTRACTI64X2 m128^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tXmmResult = vextracti64x2_avx512dq( ZmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99447\ndefine pcodeop vextracti32x8_avx512dq ;\n:VEXTRACTI32X8 YmmReg2^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextracti32x8_avx512dq( ZmmReg1, imm8:1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VEXTRACTI32X8 m256^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 ... & m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextracti32x8_avx512dq( ZmmReg1, imm8:1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = YmmResult;\n}\n\n# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99450\ndefine pcodeop vextracti64x4_avx512f ;\n:VEXTRACTI64x4 YmmReg2^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextracti64x4_avx512f( ZmmReg1, imm8:1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask64;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VEXTRACTI64x4 m256^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 ... & m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vextracti64x4_avx512f( ZmmReg1, imm8:1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask64;\n\tm256 = YmmResult;\n}\n# VFIXUPIMMPD 5-112 PAGE 1936 LINE 99754\ndefine pcodeop vfixupimmpd_avx512vl ;\n:VFIXUPIMMPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfixupimmpd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFIXUPIMMPD 5-112 PAGE 1936 LINE 99757\n:VFIXUPIMMPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfixupimmpd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFIXUPIMMPD 5-112 PAGE 1936 LINE 99760\ndefine pcodeop vfixupimmpd_avx512f ;\n:VFIXUPIMMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfixupimmpd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFIXUPIMMPS 5-116 PAGE 1940 LINE 99957\ndefine pcodeop vfixupimmps_avx512vl ;\n:VFIXUPIMMPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfixupimmps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFIXUPIMMPS 5-116 PAGE 1940 LINE 99960\n:VFIXUPIMMPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfixupimmps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFIXUPIMMPS 5-116 PAGE 1940 LINE 99963\ndefine pcodeop vfixupimmps_avx512f ;\n:VFIXUPIMMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfixupimmps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 100159\ndefine pcodeop vfixupimmsd_avx512f ;\n:VFIXUPIMMSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfixupimmsd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFIXUPIMMSS 5-123 PAGE 1947 LINE 100331\ndefine pcodeop vfixupimmss_avx512f ;\n:VFIXUPIMMSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfixupimmss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100523\ndefine pcodeop vfmadd132pd_avx512vl ;\n:VFMADD132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n{\n\tXmmResult = vfmadd132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100526\ndefine pcodeop vfmadd213pd_avx512vl ;\n:VFMADD213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmadd213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100529\ndefine pcodeop vfmadd231pd_avx512vl ;\n:VFMADD231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmadd231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100532\n:VFMADD132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmadd132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100535\n:VFMADD213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmadd213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100538\n:VFMADD231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmadd231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100541\ndefine pcodeop vfmadd132pd_avx512f ;\n:VFMADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100544\ndefine pcodeop vfmadd213pd_avx512f ;\n:VFMADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100547\ndefine pcodeop vfmadd231pd_avx512f ;\n:VFMADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100884\ndefine pcodeop vfmadd132ps_avx512vl ;\n:VFMADD132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmadd132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100887\ndefine pcodeop vfmadd213ps_avx512vl ;\n:VFMADD213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmadd213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100890\ndefine pcodeop vfmadd231ps_avx512vl ;\n:VFMADD231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmadd231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100893\n:VFMADD132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmadd132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100896\n:VFMADD213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmadd213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100899\n:VFMADD231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmadd231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100902\ndefine pcodeop vfmadd132ps_avx512f ;\n:VFMADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100905\ndefine pcodeop vfmadd213ps_avx512f ;\n:VFMADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100908\ndefine pcodeop vfmadd231ps_avx512f ;\n:VFMADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101235\ndefine pcodeop vfmadd132sd_avx512f ;\n:VFMADD132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmadd132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101238\ndefine pcodeop vfmadd213sd_avx512f ;\n:VFMADD213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmadd213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101241\ndefine pcodeop vfmadd231sd_avx512f ;\n:VFMADD231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmadd231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101403\ndefine pcodeop vfmadd132ss_avx512f ;\n:VFMADD132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmadd132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101406\ndefine pcodeop vfmadd213ss_avx512f ;\n:VFMADD213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmadd213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101409\ndefine pcodeop vfmadd231ss_avx512f ;\n:VFMADD231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmadd231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101585\ndefine pcodeop vfmaddsub213pd_avx512vl ;\n:VFMADDSUB213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmaddsub213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101589\ndefine pcodeop vfmaddsub231pd_avx512vl ;\n:VFMADDSUB231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmaddsub231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101593\ndefine pcodeop vfmaddsub132pd_avx512vl ;\n:VFMADDSUB132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmaddsub132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101597\n:VFMADDSUB213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmaddsub213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101601\n:VFMADDSUB231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmaddsub231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101605\n:VFMADDSUB132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmaddsub132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101621\ndefine pcodeop vfmaddsub213pd_avx512f ;\n:VFMADDSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmaddsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101625\ndefine pcodeop vfmaddsub231pd_avx512f ;\n:VFMADDSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmaddsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101629\ndefine pcodeop vfmaddsub132pd_avx512f ;\n:VFMADDSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmaddsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102024\ndefine pcodeop vfmaddsub213ps_avx512vl ;\n:VFMADDSUB213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmaddsub213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102028\ndefine pcodeop vfmaddsub231ps_avx512vl ;\n:VFMADDSUB231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmaddsub231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102031\ndefine pcodeop vfmaddsub132ps_avx512vl ;\n:VFMADDSUB132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmaddsub132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102034\n:VFMADDSUB213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmaddsub213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102038\n:VFMADDSUB231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmaddsub231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102041\n:VFMADDSUB132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmaddsub132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102044\ndefine pcodeop vfmaddsub213ps_avx512f ;\n:VFMADDSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmaddsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102048\ndefine pcodeop vfmaddsub231ps_avx512f ;\n:VFMADDSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmaddsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102051\ndefine pcodeop vfmaddsub132ps_avx512f ;\n:VFMADDSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmaddsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102454\ndefine pcodeop vfmsubadd132pd_avx512vl ;\n:VFMSUBADD132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsubadd132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102458\ndefine pcodeop vfmsubadd213pd_avx512vl ;\n:VFMSUBADD213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsubadd213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102462\ndefine pcodeop vfmsubadd231pd_avx512vl ;\n:VFMSUBADD231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsubadd231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102466\n:VFMSUBADD132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsubadd132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102470\n:VFMSUBADD213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsubadd213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102474\n:VFMSUBADD231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsubadd231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102490\ndefine pcodeop vfmsubadd132pd_avx512f ;\n:VFMSUBADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsubadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102494\ndefine pcodeop vfmsubadd213pd_avx512f ;\n:VFMSUBADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsubadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102498\ndefine pcodeop vfmsubadd231pd_avx512f ;\n:VFMSUBADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsubadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102894\ndefine pcodeop vfmsubadd132ps_avx512vl ;\n:VFMSUBADD132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsubadd132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102897\ndefine pcodeop vfmsubadd213ps_avx512vl ;\n:VFMSUBADD213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsubadd213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102901\ndefine pcodeop vfmsubadd231ps_avx512vl ;\n:VFMSUBADD231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsubadd231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102904\n:VFMSUBADD132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsubadd132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102907\n:VFMSUBADD213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsubadd213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102911\n:VFMSUBADD231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsubadd231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102914\ndefine pcodeop vfmsubadd132ps_avx512f ;\n:VFMSUBADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsubadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102917\ndefine pcodeop vfmsubadd213ps_avx512f ;\n:VFMSUBADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsubadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102921\ndefine pcodeop vfmsubadd231ps_avx512f ;\n:VFMSUBADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsubadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103332\ndefine pcodeop vfmsub132pd_avx512vl ;\n:VFMSUB132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsub132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103335\ndefine pcodeop vfmsub213pd_avx512vl ;\n:VFMSUB213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsub213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103338\ndefine pcodeop vfmsub231pd_avx512vl ;\n:VFMSUB231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsub231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103341\n:VFMSUB132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsub132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103344\n:VFMSUB213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsub213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103347\n:VFMSUB231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsub231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103350\ndefine pcodeop vfmsub132pd_avx512f ;\n:VFMSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103353\ndefine pcodeop vfmsub213pd_avx512f ;\n:VFMSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103356\ndefine pcodeop vfmsub231pd_avx512f ;\n:VFMSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103692\ndefine pcodeop vfmsub132ps_avx512vl ;\n:VFMSUB132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsub132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103695\ndefine pcodeop vfmsub213ps_avx512vl ;\n:VFMSUB213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsub213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103698\ndefine pcodeop vfmsub231ps_avx512vl ;\n:VFMSUB231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfmsub231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103701\n:VFMSUB132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsub132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103704\n:VFMSUB213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsub213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103707\n:VFMSUB231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfmsub231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103710\ndefine pcodeop vfmsub132ps_avx512f ;\n:VFMSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103713\ndefine pcodeop vfmsub213ps_avx512f ;\n:VFMSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103716\ndefine pcodeop vfmsub231ps_avx512f ;\n:VFMSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104042\ndefine pcodeop vfmsub132sd_avx512f ;\n:VFMSUB132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmsub132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104045\ndefine pcodeop vfmsub213sd_avx512f ;\n:VFMSUB213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmsub213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104048\ndefine pcodeop vfmsub231sd_avx512f ;\n:VFMSUB231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmsub231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104217\ndefine pcodeop vfmsub132ss_avx512f ;\n:VFMSUB132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmsub132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104220\ndefine pcodeop vfmsub213ss_avx512f ;\n:VFMSUB213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmsub213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104223\ndefine pcodeop vfmsub231ss_avx512f ;\n:VFMSUB231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfmsub231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104401\ndefine pcodeop vfnmadd132pd_avx512vl ;\n:VFNMADD132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmadd132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104405\ndefine pcodeop vfnmadd213pd_avx512vl ;\n:VFNMADD213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmadd213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104408\ndefine pcodeop vfnmadd231pd_avx512vl ;\n:VFNMADD231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmadd231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104412\n:VFNMADD132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmadd132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104416\n:VFNMADD213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmadd213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104419\n:VFNMADD231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmadd231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104423\ndefine pcodeop vfnmadd132pd_avx512f ;\n:VFNMADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104426\ndefine pcodeop vfnmadd213pd_avx512f ;\n:VFNMADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104429\ndefine pcodeop vfnmadd231pd_avx512f ;\n:VFNMADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104760\ndefine pcodeop vfnmadd132ps_avx512vl ;\n:VFNMADD132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmadd132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104763\ndefine pcodeop vfnmadd213ps_avx512vl ;\n:VFNMADD213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmadd213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104766\ndefine pcodeop vfnmadd231ps_avx512vl ;\n:VFNMADD231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmadd231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104769\n:VFNMADD132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmadd132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104772\n:VFNMADD213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmadd213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104775\n:VFNMADD231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmadd231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104778\n:VFNMADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmadd132ps_avx512vl( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104781\ndefine pcodeop vfnmadd213ps_avx512f ;\n:VFNMADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104784\ndefine pcodeop vfnmadd231ps_avx512f ;\n:VFNMADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105098\ndefine pcodeop vfnmadd132sd_avx512f ;\n:VFNMADD132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmadd132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105101\ndefine pcodeop vfnmadd213sd_avx512f ;\n:VFNMADD213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmadd213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105104\ndefine pcodeop vfnmadd231sd_avx512f ;\n:VFNMADD231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmadd231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105270\ndefine pcodeop vfnmadd132ss_avx512f ;\n:VFNMADD132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmadd132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105273\ndefine pcodeop vfnmadd213ss_avx512f ;\n:VFNMADD213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmadd213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105276\ndefine pcodeop vfnmadd231ss_avx512f ;\n:VFNMADD231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmadd231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105451\ndefine pcodeop vfnmsub132pd_avx512vl ;\n:VFNMSUB132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmsub132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105455\ndefine pcodeop vfnmsub213pd_avx512vl ;\n:VFNMSUB213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmsub213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105458\ndefine pcodeop vfnmsub231pd_avx512vl ;\n:VFNMSUB231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmsub231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105462\n:VFNMSUB132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmsub132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105466\n:VFNMSUB213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmsub213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105469\n:VFNMSUB231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmsub231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105473\ndefine pcodeop vfnmsub132pd_avx512f ;\n:VFNMSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105476\ndefine pcodeop vfnmsub213pd_avx512f ;\n:VFNMSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105479\ndefine pcodeop vfnmsub231pd_avx512f ;\n:VFNMSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105800\ndefine pcodeop vfnmsub132ps_avx512vl ;\n:VFNMSUB132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmsub132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105803\ndefine pcodeop vfnmsub213ps_avx512vl ;\n:VFNMSUB213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmsub213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105806\ndefine pcodeop vfnmsub231ps_avx512vl ;\n:VFNMSUB231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vfnmsub231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105809\n:VFNMSUB132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmsub132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105812\n:VFNMSUB213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmsub213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105815\n:VFNMSUB231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vfnmsub231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105818\ndefine pcodeop vfnmsub132ps_avx512f ;\n:VFNMSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105821\ndefine pcodeop vfnmsub213ps_avx512f ;\n:VFNMSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105824\ndefine pcodeop vfnmsub231ps_avx512f ;\n:VFNMSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vfnmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106135\ndefine pcodeop vfnmsub132sd_avx512f ;\n:VFNMSUB132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmsub132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106138\ndefine pcodeop vfnmsub213sd_avx512f ;\n:VFNMSUB213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmsub213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106141\ndefine pcodeop vfnmsub231sd_avx512f ;\n:VFNMSUB231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmsub231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106307\ndefine pcodeop vfnmsub132ss_avx512f ;\n:VFNMSUB132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmsub132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106310\ndefine pcodeop vfnmsub213ss_avx512f ;\n:VFNMSUB213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmsub213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106313\ndefine pcodeop vfnmsub231ss_avx512f ;\n:VFNMSUB231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vfnmsub231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFPCLASSPD 5-242 PAGE 2066 LINE 106466\n# There is an error in the manual where the immediate byte is not specified in the operand encoding, but it is present\ndefine pcodeop vfpclasspd_avx512vl ;\n:VFPCLASSPD KReg_reg AVXOpMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tKReg_reg = vfpclasspd_avx512vl( XmmReg2_m128_m64bcst, AVXOpMask, imm8:1 );\n}\n\n# VFPCLASSPD 5-242 PAGE 2066 LINE 106470\n:VFPCLASSPD KReg_reg AVXOpMask, YmmReg2_m256_m64bcst,imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tKReg_reg = vfpclasspd_avx512vl( YmmReg2_m256_m64bcst, AVXOpMask, imm8:1 );\n}\n\n# VFPCLASSPD 5-242 PAGE 2066 LINE 106474\ndefine pcodeop vfpclasspd_avx512dq ;\n:VFPCLASSPD KReg_reg AVXOpMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tKReg_reg = vfpclasspd_avx512dq( ZmmReg2_m512_m64bcst, AVXOpMask, imm8:1 );\n}\n\n# VFPCLASSPS 5-245 PAGE 2069 LINE 106608\n# There is an error in the manual where the immediate byte is not specified in the operand encoding, but it is present\ndefine pcodeop vfpclassps_avx512vl ;\n:VFPCLASSPS KReg_reg AVXOpMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tKReg_reg = vfpclassps_avx512vl( XmmReg2_m128_m32bcst, AVXOpMask, imm8:1 );\n}\n\n# VFPCLASSPS 5-245 PAGE 2069 LINE 106612\n:VFPCLASSPS KReg_reg AVXOpMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tKReg_reg = vfpclassps_avx512vl( YmmReg2_m256_m32bcst, AVXOpMask,imm8:1 );\n}\n\n# VFPCLASSPS 5-245 PAGE 2069 LINE 106616\ndefine pcodeop vfpclassps_avx512dq ;\n:VFPCLASSPS KReg_reg AVXOpMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tKReg_reg = vfpclassps_avx512dq( ZmmReg2_m512_m32bcst, AVXOpMask, imm8:1 );\n}\n\n# VFPCLASSSD 5-247 PAGE 2071 LINE 106722\ndefine pcodeop vfpclasssd_avx512dq ;\n:VFPCLASSSD KReg_reg AVXOpMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tKReg_reg = vfpclasssd_avx512dq( XmmReg2_m64, AVXOpMask );\n}\n\n# VFPCLASSSS 5-249 PAGE 2073 LINE 106810\ndefine pcodeop vfpclassss_avx512dq ;\n:VFPCLASSSS KReg_reg AVXOpMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tKReg_reg = vfpclassss_avx512dq( XmmReg2_m32, AVXOpMask );\n}\n\n# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107357\n# WARNING: did not recognize qualifier /vsib for \"VGATHERDPS xmm1 {k1}, vm32x\"\ndefine pcodeop vgatherdps_avx512vl ;\n:VGATHERDPS XmmReg1^XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgatherdps_avx512vl( m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107359\n# WARNING: did not recognize qualifier /vsib for \"VGATHERDPS ymm1 {k1}, vm32y\"\n:VGATHERDPS YmmReg1^YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vgatherdps_avx512vl( m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107361\n# WARNING: did not recognize qualifier /vsib for \"VGATHERDPS zmm1 {k1}, vm32z\"\ndefine pcodeop vgatherdps_avx512f ;\n:VGATHERDPS ZmmReg1^ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (ZmmReg1 & ZmmOpMask32) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vgatherdps_avx512f( m32 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107363\n# WARNING: did not recognize qualifier /vsib for \"VGATHERDPD xmm1 {k1}, vm32x\"\ndefine pcodeop vgatherdpd_avx512vl ;\n:VGATHERDPD XmmReg1^XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgatherdpd_avx512vl( m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107366\n# WARNING: did not recognize qualifier /vsib for \"VGATHERDPD ymm1 {k1}, vm32x\"\n:VGATHERDPD YmmReg1^YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vgatherdpd_avx512vl( m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107369\n# WARNING: did not recognize qualifier /vsib for \"VGATHERDPD zmm1 {k1}, vm32y\"\ndefine pcodeop vgatherdpd_avx512f ;\n:VGATHERDPD ZmmReg1^ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (ZmmReg1 & ZmmOpMask64) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vgatherdpd_avx512f( m32 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107497\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF0DPS vm32z {k1}\"\ndefine pcodeop vgatherpf0dps_avx512pf ;\n:VGATHERPF0DPS m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf0dps_avx512pf( m32, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107500\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF0QPS vm64z {k1}\"\ndefine pcodeop vgatherpf0qps_avx512pf ;\n:VGATHERPF0QPS m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf0qps_avx512pf( m64, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107503\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF0DPD vm32y {k1}\"\ndefine pcodeop vgatherpf0dpd_avx512pf ;\n:VGATHERPF0DPD m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf0dpd_avx512pf( m32, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107506\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF0QPD vm64z {k1}\"\ndefine pcodeop vgatherpf0qpd_avx512pf ;\n:VGATHERPF0QPD m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf0qpd_avx512pf( m64, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107620\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF1DPS vm32z {k1}\"\ndefine pcodeop vgatherpf1dps_avx512pf ;\n:VGATHERPF1DPS m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf1dps_avx512pf( m32 , XmmOpMask);\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107623\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF1QPS vm64z {k1}\"\ndefine pcodeop vgatherpf1qps_avx512pf ;\n:VGATHERPF1QPS m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf1qps_avx512pf( m64, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107626\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF1DPD vm32y {k1}\"\ndefine pcodeop vgatherpf1dpd_avx512pf ;\n:VGATHERPF1DPD m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf1dpd_avx512pf( m32, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107629\n# WARNING: did not recognize qualifier /vsib for \"VGATHERPF1QPD vm64z {k1}\"\ndefine pcodeop vgatherpf1qpd_avx512pf ;\n:VGATHERPF1QPD m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvgatherpf1qpd_avx512pf( m64, XmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107742\n# WARNING: did not recognize qualifier /vsib for \"VGATHERQPS xmm1 {k1}, vm64x\"\ndefine pcodeop vgatherqps_avx512vl ;\n:VGATHERQPS XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgatherqps_avx512vl( m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107745\n# WARNING: did not recognize qualifier /vsib for \"VGATHERQPS xmm1 {k1}, vm64y\"\n:VGATHERQPS XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgatherqps_avx512vl( m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107748\n# WARNING: did not recognize qualifier /vsib for \"VGATHERQPS ymm1 {k1}, vm64z\"\ndefine pcodeop vgatherqps_avx512f ;\n:VGATHERQPS YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vgatherqps_avx512f( m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107751\n# WARNING: did not recognize qualifier /vsib for \"VGATHERQPD xmm1 {k1}, vm64x\"\ndefine pcodeop vgatherqpd_avx512vl ;\n:VGATHERQPD XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgatherqpd_avx512vl( m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107753\n# WARNING: did not recognize qualifier /vsib for \"VGATHERQPD ymm1 {k1}, vm64y\"\n:VGATHERQPD YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vgatherqpd_avx512vl( m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107755\n# WARNING: did not recognize qualifier /vsib for \"VGATHERQPD zmm1 {k1}, vm64z\"\ndefine pcodeop vgatherqpd_avx512f ;\n:VGATHERQPD ZmmReg1^ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (ZmmReg1 & ZmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vgatherqpd_avx512f( m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108099\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERDD xmm1 {k1}, vm32x\"\ndefine pcodeop vpgatherdd_avx512vl ;\n:VPGATHERDD XmmReg1^XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpgatherdd_avx512vl( m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108101\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERDD ymm1 {k1}, vm32y\"\n:VPGATHERDD YmmReg1^YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpgatherdd_avx512vl( m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108103\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERDD zmm1 {k1}, vm32z\"\ndefine pcodeop vpgatherdd_avx512f ;\n:VPGATHERDD ZmmReg1^ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (ZmmReg1 & ZmmOpMask32) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpgatherdd_avx512f( m32 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108105\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERDQ xmm1 {k1}, vm32x\"\ndefine pcodeop vpgatherdq_avx512vl ;\n:VPGATHERDQ XmmReg1^XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpgatherdq_avx512vl( m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108107\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERDQ ymm1 {k1}, vm32x\"\n:VPGATHERDQ YmmReg1^YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpgatherdq_avx512vl( m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108109\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERDQ zmm1 {k1}, vm32y\"\ndefine pcodeop vpgatherdq_avx512f ;\n:VPGATHERDQ ZmmReg1^ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (ZmmReg1 & ZmmOpMask64) ... & m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpgatherdq_avx512f( m32 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108457\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERQD xmm1 {k1}, vm64x\"\ndefine pcodeop vpgatherqd_avx512vl ;\n:VPGATHERQD XmmReg1^XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpgatherqd_avx512vl( m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108459\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERQD xmm1 {k1}, vm64y\"\n:VPGATHERQD XmmReg1^XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpgatherqd_avx512vl( m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108461\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERQD ymm1 {k1}, vm64z\"\ndefine pcodeop vpgatherqd_avx512f ;\n:VPGATHERQD YmmReg1^YmmOpMask32, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpgatherqd_avx512f( m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108463\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERQQ xmm1 {k1}, vm64x\"\ndefine pcodeop vpgatherqq_avx512vl ;\n:VPGATHERQQ XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpgatherqq_avx512vl( m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108465\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERQQ ymm1 {k1}, vm64y\"\n:VPGATHERQQ YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpgatherqq_avx512vl( m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108467\n# WARNING: did not recognize qualifier /vsib for \"VPGATHERQQ zmm1 {k1}, vm64z\"\ndefine pcodeop vpgatherqq_avx512f ;\n:VPGATHERQQ ZmmReg1^ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (ZmmReg1 & ZmmOpMask64) ... & m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpgatherqq_avx512f( m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETEXPPD 5-288 PAGE 2112 LINE 108594\ndefine pcodeop vgetexppd_avx512vl ;\n:VGETEXPPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vgetexppd_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETEXPPD 5-288 PAGE 2112 LINE 108598\n:VGETEXPPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vgetexppd_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGETEXPPD 5-288 PAGE 2112 LINE 108602\ndefine pcodeop vgetexppd_avx512f ;\n:VGETEXPPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vgetexppd_avx512f( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETEXPPS 5-291 PAGE 2115 LINE 108760\ndefine pcodeop vgetexpps_avx512vl ;\n:VGETEXPPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vgetexpps_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETEXPPS 5-291 PAGE 2115 LINE 108764\n:VGETEXPPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vgetexpps_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGETEXPPS 5-291 PAGE 2115 LINE 108768\ndefine pcodeop vgetexpps_avx512f ;\n:VGETEXPPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vgetexpps_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETEXPSD 5-295 PAGE 2119 LINE 108959\ndefine pcodeop vgetexpsd_avx512f ;\n:VGETEXPSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgetexpsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETEXPSS 5-297 PAGE 2121 LINE 109037\ndefine pcodeop vgetexpss_avx512f ;\n:VGETEXPSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgetexpss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETMANTPD 5-299 PAGE 2123 LINE 109120\ndefine pcodeop vgetmantpd_avx512vl ;\n:VGETMANTPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vgetmantpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETMANTPD 5-299 PAGE 2123 LINE 109125\n:VGETMANTPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vgetmantpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGETMANTPD 5-299 PAGE 2123 LINE 109130\ndefine pcodeop vgetmantpd_avx512f ;\n:VGETMANTPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vgetmantpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETMANTPS 5-303 PAGE 2127 LINE 109339\ndefine pcodeop vgetmantps_avx512vl ;\n:VGETMANTPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tXmmResult = vgetmantps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETMANTPS 5-303 PAGE 2127 LINE 109344\n:VGETMANTPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tYmmResult = vgetmantps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGETMANTPS 5-303 PAGE 2127 LINE 109349\ndefine pcodeop vgetmantps_avx512f ;\n:VGETMANTPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)\n{\n\tZmmResult = vgetmantps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETMANTSD 5-306 PAGE 2130 LINE 109519\ndefine pcodeop vgetmantsd_avx512f ;\n:VGETMANTSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgetmantsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETMANTSS 5-308 PAGE 2132 LINE 109610\ndefine pcodeop vgetmantss_avx512f ;\n:VGETMANTSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vgetmantss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109706\ndefine pcodeop vinsertf32x4_avx512vl ;\n:VINSERTF32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vinsertf32x4_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109709\ndefine pcodeop vinsertf32x4_avx512f ;\n:VINSERTF32X4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinsertf32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109712\ndefine pcodeop vinsertf64x2_avx512vl ;\n:VINSERTF64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vinsertf64x2_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109715\ndefine pcodeop vinsertf64x2_avx512dq ;\n:VINSERTF64X2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinsertf64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109718\ndefine pcodeop vinsertf32x8_avx512dq ;\n:VINSERTF32X8 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinsertf32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109721\ndefine pcodeop vinsertf64x4_avx512f ;\n:VINSERTF64X4 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinsertf64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109930\ndefine pcodeop vinserti32x4_avx512vl ;\n:VINSERTI32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vinserti32x4_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109933\ndefine pcodeop vinserti32x4_avx512f ;\n:VINSERTI32X4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinserti32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109936\ndefine pcodeop vinserti64x2_avx512vl ;\n:VINSERTI64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tYmmResult = vinserti64x2_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109939\ndefine pcodeop vinserti64x2_avx512dq ;\n:VINSERTI64X2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinserti64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109942\ndefine pcodeop vinserti32x8_avx512dq ;\n:VINSERTI32X8 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinserti32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109945\ndefine pcodeop vinserti64x4_avx512f ;\n:VINSERTI64X4 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)\n{\n\tZmmResult = vinserti64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110393\ndefine pcodeop vpblendmb_avx512vl ;\n:VPBLENDMB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpblendmb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110396\n:VPBLENDMB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpblendmb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110399\ndefine pcodeop vpblendmb_avx512bw ;\n:VPBLENDMB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpblendmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110402\ndefine pcodeop vpblendmw_avx512vl ;\n:VPBLENDMW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpblendmw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110405\n:VPBLENDMW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpblendmw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110408\ndefine pcodeop vpblendmw_avx512bw ;\n:VPBLENDMW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpblendmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110495\ndefine pcodeop vpblendmd_avx512vl ;\n:VPBLENDMD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpblendmd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110498\n:VPBLENDMD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpblendmd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110501\ndefine pcodeop vpblendmd_avx512f ;\n:VPBLENDMD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpblendmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110504\ndefine pcodeop vpblendmq_avx512vl ;\n:VPBLENDMQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpblendmq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110507\n:VPBLENDMQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpblendmq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110510\ndefine pcodeop vpblendmq_avx512f ;\n:VPBLENDMQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpblendmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110617\n# WARNING: did not recognize operand \"reg\" (encoding ModRM:r/m (r)) for \"VPBROADCASTB xmm1 {k1}{z}, reg\"\n#TODO: fix\ndefine pcodeop vpbroadcastb_avx512vl ;\n:VPBROADCASTB XmmReg1^XmmOpMask8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask8)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tlocal tmp:16 = vpbroadcastb_avx512vl( );\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(tmp);\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110619\n# WARNING: did not recognize operand \"reg\" (encoding ModRM:r/m (r)) for \"VPBROADCASTB ymm1 {k1}{z}, reg\"\n:VPBROADCASTB YmmReg1^YmmOpMask8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask8)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpbroadcastb_avx512vl( );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110621\n# WARNING: did not recognize operand \"reg\" (encoding ModRM:r/m (r)) for \"VPBROADCASTB zmm1 {k1}{z}, reg\"\ndefine pcodeop vpbroadcastb_avx512bw ;\n:VPBROADCASTB ZmmReg1^ZmmOpMask8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; ZmmReg1 & ZmmOpMask8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpbroadcastb_avx512bw( );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110623\n# WARNING: did not recognize operand \"reg\" (encoding ModRM:r/m (r)) for \"VPBROADCASTW xmm1 {k1}{z}, reg\"\ndefine pcodeop vpbroadcastw_avx512vl ;\n:VPBROADCASTW XmmReg1^XmmOpMask16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask16)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpbroadcastw_avx512vl( );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110625\n# WARNING: did not recognize operand \"reg\" (encoding ModRM:r/m (r)) for \"VPBROADCASTW ymm1 {k1}{z}, reg\"\n:VPBROADCASTW YmmReg1^YmmOpMask16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask16)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpbroadcastw_avx512vl( );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110627\n# WARNING: did not recognize operand \"reg\" (encoding ModRM:r/m (r)) for \"VPBROADCASTW zmm1 {k1}{z}, reg\"\ndefine pcodeop vpbroadcastw_avx512bw ;\n:VPBROADCASTW ZmmReg1^ZmmOpMask16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; ZmmReg1 & ZmmOpMask16\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpbroadcastw_avx512bw( );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110629\n# WARNING: did not recognize operand \"r32\" (encoding ModRM:r/m (r)) for \"VPBROADCASTD xmm1 {k1}{z}, r32\"\ndefine pcodeop vpbroadcastd_avx512vl ;\n:VPBROADCASTD XmmReg1^XmmOpMask32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask32)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpbroadcastd_avx512vl( );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110631\n# WARNING: did not recognize operand \"r32\" (encoding ModRM:r/m (r)) for \"VPBROADCASTD ymm1 {k1}{z}, r32\"\n:VPBROADCASTD YmmReg1^YmmOpMask32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask32)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpbroadcastd_avx512vl( );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110633\n# WARNING: did not recognize operand \"r32\" (encoding ModRM:r/m (r)) for \"VPBROADCASTD zmm1 {k1}{z}, r32\"\ndefine pcodeop vpbroadcastd_avx512f ;\n:VPBROADCASTD ZmmReg1^ZmmOpMask32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; ZmmReg1 & ZmmOpMask32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpbroadcastd_avx512f( );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110635\n# WARNING: did not recognize operand \"r64\" (encoding ModRM:r/m (r)) for \"VPBROADCASTQ xmm1 {k1}{z}, r64\"\ndefine pcodeop vpbroadcastq_avx512vl ;\n@ifdef IA64\n:VPBROADCASTQ XmmReg1^XmmOpMask64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask64)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpbroadcastq_avx512vl( );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n@endif\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110637\n# WARNING: did not recognize operand \"r64\" (encoding ModRM:r/m (r)) for \"VPBROADCASTQ ymm1 {k1}{z}, r64\"\n@ifdef IA64\n:VPBROADCASTQ YmmReg1^YmmOpMask64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask64)\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpbroadcastq_avx512vl( );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n@endif\n\n# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110639\n# WARNING: did not recognize operand \"r64\" (encoding ModRM:r/m (r)) for \"VPBROADCASTQ zmm1 {k1}{z}, r64\"\ndefine pcodeop vpbroadcastq_avx512f ;\n@ifdef IA64\n:VPBROADCASTQ ZmmReg1^ZmmOpMask64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; ZmmReg1 & ZmmOpMask64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpbroadcastq_avx512f( );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n@endif\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110780\n:VPBROADCASTB XmmReg1^XmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tXmmResult = vpbroadcastb_avx512vl( XmmReg2_m8 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110782\n:VPBROADCASTB YmmReg1^YmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & XmmReg2_m8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vpbroadcastb_avx512vl( XmmReg2_m8 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110784\n:VPBROADCASTB ZmmReg1^ZmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask8) ... & XmmReg2_m8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vpbroadcastb_avx512bw( XmmReg2_m8 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110791\n:VPBROADCASTW XmmReg1^XmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m16\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tXmmResult = vpbroadcastw_avx512vl( XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110794\n:VPBROADCASTW YmmReg1^YmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m16\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vpbroadcastw_avx512vl( XmmReg2_m16 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110797\n:VPBROADCASTW ZmmReg1^ZmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m16\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vpbroadcastw_avx512bw( XmmReg2_m16 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110804\n:VPBROADCASTD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tXmmResult = vpbroadcastd_avx512vl( XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110807\n:VPBROADCASTD YmmReg1^YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vpbroadcastd_avx512vl( XmmReg2_m32 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110810\n:VPBROADCASTD ZmmReg1^ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vpbroadcastd_avx512f( XmmReg2_m32 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110817\n:VPBROADCASTQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tXmmResult = vpbroadcastq_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110819\n:VPBROADCASTQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vpbroadcastq_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110821\n:VPBROADCASTQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vpbroadcastq_avx512f( XmmReg2_m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-331 PAGE 2155 LINE 110823\ndefine pcodeop vbroadcasti32x2_avx512vl ;\n:VBROADCASTI32x2 XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tXmmResult = vbroadcasti32x2_avx512vl( XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110837\n:VBROADCASTI32x2 YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcasti32x2_avx512vl( XmmReg2_m64 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110840\ndefine pcodeop vbroadcasti32x2_avx512dq ;\n:VBROADCASTI32x2 ZmmReg1^ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcasti32x2_avx512dq( XmmReg2_m64 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110845\ndefine pcodeop vbroadcasti32x4_avx512vl ;\n:VBROADCASTI32X4 YmmReg1^YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcasti32x4_avx512vl( m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110848\ndefine pcodeop vbroadcasti32x4_avx512f ;\n:VBROADCASTI32X4 ZmmReg1^ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask32) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcasti32x4_avx512f( m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110851\ndefine pcodeop vbroadcasti64x2_avx512vl ;\n:VBROADCASTI64X2 YmmReg1^YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tYmmResult = vbroadcasti64x2_avx512vl( m128 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110854\ndefine pcodeop vbroadcasti64x2_avx512dq ;\n:VBROADCASTI64X2 ZmmReg1^ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcasti64x2_avx512dq( m128 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110857\ndefine pcodeop vbroadcasti32x8_avx512dq ;\n:VBROADCASTI32X8 ZmmReg1^ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcasti32x8_avx512dq( m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPBROADCAST 5-332 PAGE 2156 LINE 110860\ndefine pcodeop vbroadcasti64x4_avx512f ;\n:VBROADCASTI64X4 ZmmReg1^ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5B; (ZmmReg1 & ZmmOpMask64) ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)\n{\n\tZmmResult = vbroadcasti64x4_avx512f( m256 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111259\nVPCMPB_mon: \"VPCMPEQB\" is imm8=0x0 { }\nVPCMPB_mon: \"VPCMPLTB\" is imm8=0x1 { }\nVPCMPB_mon: \"VPCMPLEB\" is imm8=0x2 { }\nVPCMPB_mon: \"VPCMPEQB\" is imm8=0x4 { }\nVPCMPB_mon: \"VPCMPNLTB\" is imm8=0x5 { }\nVPCMPB_mon: \"VPCMPNLEB\" is imm8=0x6 { }\nVPCMPB_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPB_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPB_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPB_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPB_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPB_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPB_mon: \"VPCMPB\" is imm8 { }\nVPCMPB_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\ndefine pcodeop vpcmpb_avx512vl ;\n:^VPCMPB_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPB_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128; VPCMPB_mon & VPCMPB_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpb_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPB_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111263\n:^VPCMPB_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPB_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256; VPCMPB_mon & VPCMPB_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpb_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPB_op );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111267\ndefine pcodeop vpcmpb_avx512bw ;\n:^VPCMPB_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPB_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512; VPCMPB_mon & VPCMPB_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPB_op );\n\tKReg_reg = zext(AVXOpMask[0,64]) & tmp;\n}\n\n\n\n# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111271\nVPCMPUB_mon: \"VPCMPEQUB\" is imm8=0x0 { }\nVPCMPUB_mon: \"VPCMPLTUB\" is imm8=0x1 { }\nVPCMPUB_mon: \"VPCMPLEUB\" is imm8=0x2 { }\nVPCMPUB_mon: \"VPCMPEQUB\" is imm8=0x4 { }\nVPCMPUB_mon: \"VPCMPNLTUB\" is imm8=0x5 { }\nVPCMPUB_mon: \"VPCMPNLEUB\" is imm8=0x6 { }\nVPCMPUB_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPUB_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPUB_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPUB_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPUB_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPUB_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPUB_mon: \"VPCMPUB\" is imm8 { }\nVPCMPUB_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\ndefine pcodeop vpcmpub_avx512vl ;\n:^VPCMPUB_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPUB_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128; VPCMPUB_mon & VPCMPUB_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpub_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPUB_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111275\n:^VPCMPUB_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPUB_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256; VPCMPUB_mon & VPCMPUB_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpub_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPUB_op );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111279\ndefine pcodeop vpcmpub_avx512bw ;\n:^VPCMPUB_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPUB_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512; VPCMPUB_mon & VPCMPUB_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPUB_op );\n\tKReg_reg = zext(AVXOpMask[0,64]) & tmp;\n\t\n}\n\n\n# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111422\nVPCMPD_mon: \"VPCMPEQD\" is imm8=0x0 { }\nVPCMPD_mon: \"VPCMPLTD\" is imm8=0x1 { }\nVPCMPD_mon: \"VPCMPLED\" is imm8=0x2 { }\nVPCMPD_mon: \"VPCMPEQD\" is imm8=0x4 { }\nVPCMPD_mon: \"VPCMPNLTD\" is imm8=0x5 { }\nVPCMPD_mon: \"VPCMPNLED\" is imm8=0x6 { }\nVPCMPD_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPD_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPD_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPD_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPD_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPD_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPD_mon: \"VPCMPD\" is imm8 { }\nVPCMPD_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\ndefine pcodeop vpcmpd_avx512vl ;\n:^VPCMPD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst^VPCMPD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m32bcst; VPCMPD_mon & VPCMPD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, VPCMPD_op );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111426\n:^VPCMPD_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst^VPCMPD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m32bcst; VPCMPD_mon & VPCMPD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, VPCMPD_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111430\ndefine pcodeop vpcmpd_avx512f ;\n:^VPCMPD_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VPCMPD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m32bcst; VPCMPD_mon & VPCMPD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VPCMPD_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n\n# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111434\nVPCMPUD_mon: \"VPCMPEQUD\" is imm8=0x0 { }\nVPCMPUD_mon: \"VPCMPLTUD\" is imm8=0x1 { }\nVPCMPUD_mon: \"VPCMPLEUD\" is imm8=0x2 { }\nVPCMPUD_mon: \"VPCMPEQUD\" is imm8=0x4 { }\nVPCMPUD_mon: \"VPCMPNLTUD\" is imm8=0x5 { }\nVPCMPUD_mon: \"VPCMPNLEUD\" is imm8=0x6 { }\nVPCMPUD_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPUD_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPUD_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPUD_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPUD_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPUD_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPUD_mon: \"VPCMPUD\" is imm8 { }\nVPCMPUD_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\ndefine pcodeop vpcmpud_avx512vl ;\n:^VPCMPUD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst^VPCMPUD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m32bcst; VPCMPUD_mon & VPCMPUD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpud_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, VPCMPUD_op );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111438\n:^VPCMPUD_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst^VPCMPUD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m32bcst; VPCMPUD_mon & VPCMPUD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpud_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, VPCMPUD_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111442\ndefine pcodeop vpcmpud_avx512f ;\n:^VPCMPUD_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VPCMPUD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m32bcst; VPCMPUD_mon & VPCMPUD_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VPCMPUD_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n\nVPCMPQ_mon: \"VPCMPEQQ\" is imm8=0x0 { }\nVPCMPQ_mon: \"VPCMPLTQ\" is imm8=0x1 { }\nVPCMPQ_mon: \"VPCMPLEQ\" is imm8=0x2 { }\nVPCMPQ_mon: \"VPCMPEQQ\" is imm8=0x4 { }\nVPCMPQ_mon: \"VPCMPNLTQ\" is imm8=0x5 { }\nVPCMPQ_mon: \"VPCMPNLEQ\" is imm8=0x6 { }\nVPCMPQ_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPQ_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPQ_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPQ_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPQ_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPQ_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPQ_mon: \"VPCMPQ\" is imm8 { }\nVPCMPQ_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\n# VPCMPQ/VPCMPQ 5-345 PAGE 2169 LINE 111573\ndefine pcodeop vpcmpq_avx512vl ;\n:^VPCMPQ_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst^VPCMPQ_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m64bcst; VPCMPQ_mon & VPCMPQ_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, VPCMPQ_op );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# VPCMPQ/VPCMPQ 5-345 PAGE 2169 LINE 111577\n:^VPCMPQ_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst^VPCMPQ_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m64bcst; VPCMPQ_mon & VPCMPQ_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, VPCMPQ_op );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPCMPQ/VPCMPQ 5-345 PAGE 2169 LINE 111581\ndefine pcodeop vpcmpq_avx512f ;\n:^VPCMPQ_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VPCMPQ_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m64bcst; VPCMPQ_mon & VPCMPQ_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VPCMPQ_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n\nVPCMPUQ_mon: \"VPCMPEQUQ\" is imm8=0x0 { }\nVPCMPUQ_mon: \"VPCMPLTUQ\" is imm8=0x1 { }\nVPCMPUQ_mon: \"VPCMPLEUQ\" is imm8=0x2 { }\nVPCMPUQ_mon: \"VPCMPEQUQ\" is imm8=0x4 { }\nVPCMPUQ_mon: \"VPCMPNLTUQ\" is imm8=0x5 { }\nVPCMPUQ_mon: \"VPCMPNLEUQ\" is imm8=0x6 { }\nVPCMPUQ_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPUQ_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPUQ_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPUQ_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPUQ_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPUQ_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPUQ_mon: \"VPCMPUQ\" is imm8 { }\nVPCMPUQ_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\n# VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111585\ndefine pcodeop vpcmpuq_avx512vl ;\n:^VPCMPUQ_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst^VPCMPUQ_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m64bcst; VPCMPUQ_mon & VPCMPUQ_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpuq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, VPCMPUQ_op );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111589\n:^VPCMPUQ_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst^VPCMPUQ_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m64bcst; VPCMPUQ_mon & VPCMPUQ_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpuq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, VPCMPUQ_op );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111593\ndefine pcodeop vpcmpuq_avx512f ;\n:^VPCMPUQ_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VPCMPUQ_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m64bcst; VPCMPUQ_mon & VPCMPUQ_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vpcmpuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VPCMPUQ_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n\nVPCMPW_mon: \"VPCMPEQW\" is imm8=0x0 { }\nVPCMPW_mon: \"VPCMPLTW\" is imm8=0x1 { }\nVPCMPW_mon: \"VPCMPLEW\" is imm8=0x2 { }\nVPCMPW_mon: \"VPCMPEQW\" is imm8=0x4 { }\nVPCMPW_mon: \"VPCMPNLTW\" is imm8=0x5 { }\nVPCMPW_mon: \"VPCMPNLEW\" is imm8=0x6 { }\nVPCMPW_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPW_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPW_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPW_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPW_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPW_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPW_mon: \"VPCMPW\" is imm8 { }\nVPCMPW_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\n\n# VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111724\ndefine pcodeop vpcmpw_avx512vl ;\n:^VPCMPW_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPW_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128; VPCMPW_mon & VPCMPW_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpw_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPW_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111728\n:^VPCMPW_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPW_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256; VPCMPW_mon & VPCMPW_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpw_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPW_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111732\ndefine pcodeop vpcmpw_avx512bw ;\n:^VPCMPW_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPW_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512; VPCMPW_mon & VPCMPW_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPW_op );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n\nVPCMPUW_mon: \"VPCMPEQUW\" is imm8=0x0 { }\nVPCMPUW_mon: \"VPCMPLTUW\" is imm8=0x1 { }\nVPCMPUW_mon: \"VPCMPLEUW\" is imm8=0x2 { }\nVPCMPUW_mon: \"VPCMPEQUW\" is imm8=0x4 { }\nVPCMPUW_mon: \"VPCMPNLTUW\" is imm8=0x5 { }\nVPCMPUW_mon: \"VPCMPNLEUW\" is imm8=0x6 { }\nVPCMPUW_op: \"\" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }\nVPCMPUW_op: \"\" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }\nVPCMPUW_op: \"\" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }\nVPCMPUW_op: \"\" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }\nVPCMPUW_op: \"\" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }\nVPCMPUW_op: \"\" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }\n\nVPCMPUW_mon: \"VPCMPUW\" is imm8 { }\nVPCMPUW_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\n\n# VPCMPUW/VPCMPUUW 5-348 PAGE 2172 LINE 111724\ndefine pcodeop vpcmpuw_avx512vl ;\n:^VPCMPUW_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPUW_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128; VPCMPUW_mon & VPCMPUW_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpuw_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPUW_op );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPCMPUW/VPCMPUUW 5-348 PAGE 2172 LINE 111728\n:^VPCMPUW_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPUW_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256; VPCMPUW_mon & VPCMPUW_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpuw_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPUW_op );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPCMPUW/VPCMPUUW 5-348 PAGE 2172 LINE 111732\ndefine pcodeop vpcmpuw_avx512bw ;\n:^VPCMPUW_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPUW_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512; VPCMPUW_mon & VPCMPUW_op\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vpcmpuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPUW_op );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n\n\n# VPCOMPRESSD 5-351 PAGE 2175 LINE 111873\ndefine pcodeop vpcompressd_avx512vl ;\n:VPCOMPRESSD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpcompressd_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPCOMPRESSD m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpcompressd_avx512vl( XmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VPCOMPRESSD 5-351 PAGE 2175 LINE 111875\n:VPCOMPRESSD YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpcompressd_avx512vl( YmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPCOMPRESSD m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpcompressd_avx512vl( YmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = YmmResult;\n}\n\n# VPCOMPRESSD 5-351 PAGE 2175 LINE 111877\ndefine pcodeop vpcompressd_avx512f ;\n:VPCOMPRESSD ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpcompressd_avx512f( ZmmReg1 );\n\tZmmMask = ZmmReg2_m512;\n\tbuild ZmmOpMask32;\n\tZmmReg2_m512 = ZmmResult;\n}\n\n# VPCOMPRESSQ 5-353 PAGE 2177 LINE 111970\ndefine pcodeop vpcompressq_avx512vl ;\n:VPCOMPRESSQ XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmReg2 = vpcompressq_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPCOMPRESSQ m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpcompressq_avx512vl( XmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask64;\n\tm128 = XmmResult;\n}\n\n# VPCOMPRESSQ 5-353 PAGE 2177 LINE 111972\n:VPCOMPRESSQ YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpcompressq_avx512vl( YmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask64;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPCOMPRESSQ m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x8B; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpcompressq_avx512vl( YmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask64;\n\tm256 = YmmResult;\n}\n\n# VPCOMPRESSQ 5-353 PAGE 2177 LINE 111974\ndefine pcodeop vpcompressq_avx512f ;\n:VPCOMPRESSQ ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpcompressq_avx512f( ZmmReg1 );\n\tZmmMask = ZmmReg2_m512;\n\tbuild ZmmOpMask64;\n\tZmmReg2_m512 = ZmmResult;\n}\n\n# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112068\ndefine pcodeop vpconflictd_avx512vl ;\n:VPCONFLICTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpconflictd_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112072\n:VPCONFLICTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpconflictd_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112076\ndefine pcodeop vpconflictd_avx512cd ;\n:VPCONFLICTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpconflictd_avx512cd( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112080\ndefine pcodeop vpconflictq_avx512vl ;\n:VPCONFLICTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpconflictq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112084\n:VPCONFLICTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpconflictq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112088\ndefine pcodeop vpconflictq_avx512cd ;\n:VPCONFLICTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpconflictq_avx512cd( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112407\ndefine pcodeop vpermd_avx512vl ;\n:VPERMD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpermd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112410\ndefine pcodeop vpermd_avx512f ;\n:VPERMD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpermd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112413\ndefine pcodeop vpermw_avx512vl ;\n:VPERMW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpermw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112417\n:VPERMW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpermw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112421\ndefine pcodeop vpermw_avx512bw ;\n:VPERMW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x8D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpermw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112553\ndefine pcodeop vpermi2w_avx512vl ;\n:VPERMI2W XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpermi2w_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112556\n:VPERMI2W YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpermi2w_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112559\ndefine pcodeop vpermi2w_avx512bw ;\n:VPERMI2W ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x75; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpermi2w_avx512bw( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112562\ndefine pcodeop vpermi2d_avx512vl ;\n:VPERMI2D XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpermi2d_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112566\n:VPERMI2D YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpermi2d_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112570\ndefine pcodeop vpermi2d_avx512f ;\n:VPERMI2D ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpermi2d_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112574\ndefine pcodeop vpermi2q_avx512vl ;\n:VPERMI2Q XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpermi2q_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112578\n:VPERMI2Q YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpermi2q_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112582\ndefine pcodeop vpermi2q_avx512f ;\n:VPERMI2Q ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpermi2q_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112586\ndefine pcodeop vpermi2ps_avx512vl ;\n:VPERMI2PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpermi2ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112590\n:VPERMI2PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpermi2ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112594\ndefine pcodeop vpermi2ps_avx512f ;\n:VPERMI2PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpermi2ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112610\ndefine pcodeop vpermi2pd_avx512vl ;\n:VPERMI2PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpermi2pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112614\n:VPERMI2PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpermi2pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112618\ndefine pcodeop vpermi2pd_avx512f ;\n:VPERMI2PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpermi2pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112866\ndefine pcodeop vpermilpd_avx512vl ;\n:VPERMILPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tXmmResult = vpermilpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112869\n:VPERMILPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vpermilpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112872\ndefine pcodeop vpermilpd_avx512f ;\n:VPERMILPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x0D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vpermilpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112879\n:VPERMILPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)\n{\n\tXmmResult = vpermilpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112882\n:VPERMILPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)\n{\n\tYmmResult = vpermilpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMILPD 5-371 PAGE 2195 LINE 112885\n:VPERMILPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)\n{\n\tZmmResult = vpermilpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113170\ndefine pcodeop vpermilps_avx512vl ;\n:VPERMILPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tXmmResult = vpermilps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113173\n:VPERMILPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vpermilps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113176\ndefine pcodeop vpermilps_avx512f ;\n:VPERMILPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x0C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vpermilps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113179\n:VPERMILPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)\n{\n\tXmmResult = vpermilps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113182\n:VPERMILPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)\n{\n\tYmmResult = vpermilps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMILPS 5-376 PAGE 2200 LINE 113186\n:VPERMILPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)\n{\n\tZmmResult = vpermilps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMPD 5-381 PAGE 2205 LINE 113456\ndefine pcodeop vpermpd_avx512vl ;\n:VPERMPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)\n{\n\tYmmResult = vpermpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMPD 5-381 PAGE 2205 LINE 113459\ndefine pcodeop vpermpd_avx512f ;\n:VPERMPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)\n{\n\tZmmResult = vpermpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMPD 5-381 PAGE 2205 LINE 113462\n:VPERMPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vpermpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMPD 5-381 PAGE 2205 LINE 113465\n:VPERMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vpermpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMPS 5-384 PAGE 2208 LINE 113636\ndefine pcodeop vpermps_avx512vl ;\n:VPERMPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpermps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMPS 5-384 PAGE 2208 LINE 113639\ndefine pcodeop vpermps_avx512f ;\n:VPERMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpermps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMQ 5-387 PAGE 2211 LINE 113771\ndefine pcodeop vpermq_avx512vl ;\n:VPERMQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)\n{\n\tYmmResult = vpermq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMQ 5-387 PAGE 2211 LINE 113774\ndefine pcodeop vpermq_avx512f ;\n:VPERMQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)\n{\n\tZmmResult = vpermq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMQ 5-387 PAGE 2211 LINE 113777\n:VPERMQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vpermq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMQ 5-387 PAGE 2211 LINE 113780\n:VPERMQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vpermq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\ndefine pcodeop vpermt2pd_avx512f;\n:VPERMT2PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x7F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst {\n\tXmmResult = vpermt2pd_avx512f( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n:VPERMT2PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x7F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst {\n\tYmmResult = vpermt2pd_avx512f( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n:VPERMT2PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst {\n\tZmmResult = vpermt2pd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPEXPANDD 5-390 PAGE 2214 LINE 113945\ndefine pcodeop vpexpandd_avx512vl ;\n:VPEXPANDD XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpexpandd_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPEXPANDD 5-390 PAGE 2214 LINE 113948\n:VPEXPANDD YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpexpandd_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPEXPANDD 5-390 PAGE 2214 LINE 113951\ndefine pcodeop vpexpandd_avx512f ;\n:VPEXPANDD ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpexpandd_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPEXPANDQ 5-392 PAGE 2216 LINE 114033\ndefine pcodeop vpexpandq_avx512vl ;\n:VPEXPANDQ XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vpexpandq_avx512vl( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPEXPANDQ 5-392 PAGE 2216 LINE 114035\n:VPEXPANDQ YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tYmmResult = vpexpandq_avx512vl( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPEXPANDQ 5-392 PAGE 2216 LINE 114037\ndefine pcodeop vpexpandq_avx512f ;\n:VPEXPANDQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tZmmResult = vpexpandq_avx512f( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114118\ndefine pcodeop vplzcntd_avx512vl ;\n:VPLZCNTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vplzcntd_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114122\n:VPLZCNTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vplzcntd_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114126\ndefine pcodeop vplzcntd_avx512cd ;\n:VPLZCNTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vplzcntd_avx512cd( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114130\ndefine pcodeop vplzcntq_avx512vl ;\n:VPLZCNTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vplzcntq_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114134\n:VPLZCNTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vplzcntq_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114138\ndefine pcodeop vplzcntq_avx512cd ;\n:VPLZCNTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vplzcntq_avx512cd( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114413\ndefine pcodeop vpmovm2b_avx512vl ;\n:VPMOVM2B XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x28; (XmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:16 = vpmovm2b_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114415\n:VPMOVM2B YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x28; (YmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:32 = vpmovm2b_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114417\ndefine pcodeop vpmovm2b_avx512bw ;\n:VPMOVM2B ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x28; ZmmReg1 & KReg_rm\n{\n\tZmmReg1 = vpmovm2b_avx512bw( KReg_rm );\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114419\ndefine pcodeop vpmovm2w_avx512vl ;\n:VPMOVM2W XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x28; (XmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:16 = vpmovm2w_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114421\n:VPMOVM2W YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x28; (YmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:32 = vpmovm2w_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114423\ndefine pcodeop vpmovm2w_avx512bw ;\n:VPMOVM2W ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x28; ZmmReg1 & KReg_rm\n{\n\tZmmReg1 = vpmovm2w_avx512bw( KReg_rm );\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114425\ndefine pcodeop vpmovm2d_avx512vl ;\n:VPMOVM2D XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x38; (XmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:16 = vpmovm2d_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114427\n:VPMOVM2D YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x38; (YmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:32 = vpmovm2d_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114429\ndefine pcodeop vpmovm2d_avx512dq ;\n:VPMOVM2D ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x38; ZmmReg1 & KReg_rm\n{\n\tZmmReg1 = vpmovm2d_avx512dq( KReg_rm );\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114431\ndefine pcodeop vpmovm2q_avx512vl ;\n:VPMOVM2Q XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x38; (XmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:16 = vpmovm2q_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114433\n:VPMOVM2Q YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x38; (YmmReg1 & ZmmReg1) & KReg_rm\n{\n\tlocal tmp:32 = vpmovm2q_avx512vl( KReg_rm );\n\tZmmReg1 = zext(tmp);\n}\n\n# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114435\ndefine pcodeop vpmovm2q_avx512dq ;\n:VPMOVM2Q ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x38; ZmmReg1 & KReg_rm\n{\n\tZmmReg1 = vpmovm2q_avx512dq( KReg_rm );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114542\ndefine pcodeop vpmovb2m_avx512vl ;\n:VPMOVB2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x29; KReg_reg & (mod=0x3 & XmmReg2)\n{\n\tKReg_reg = vpmovb2m_avx512vl( XmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114544\n:VPMOVB2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x29; KReg_reg & (mod=0x3 & YmmReg2)\n{\n\tKReg_reg = vpmovb2m_avx512vl( YmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114546\ndefine pcodeop vpmovb2m_avx512bw ;\n:VPMOVB2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x29; KReg_reg & (mod=0x3 & ZmmReg2)\n{\n\tKReg_reg = vpmovb2m_avx512bw( ZmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114548\ndefine pcodeop vpmovw2m_avx512vl ;\n:VPMOVW2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x29; KReg_reg & (mod=0x3 & XmmReg2)\n{\n\tKReg_reg = vpmovw2m_avx512vl( XmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114550\n:VPMOVW2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x29; KReg_reg & (mod=0x3 & YmmReg2)\n{\n\tKReg_reg = vpmovw2m_avx512vl( YmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114552\ndefine pcodeop vpmovw2m_avx512bw ;\n:VPMOVW2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x29; KReg_reg & (mod=0x3 & ZmmReg2)\n{\n\tKReg_reg = vpmovw2m_avx512bw( ZmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114554\ndefine pcodeop vpmovd2m_avx512vl ;\n:VPMOVD2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x39; KReg_reg & (mod=0x3 & XmmReg2)\n{\n\tKReg_reg = vpmovd2m_avx512vl( XmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114556\n:VPMOVD2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x39; KReg_reg & (mod=0x3 & YmmReg2)\n{\n\tKReg_reg = vpmovd2m_avx512vl( YmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114558\ndefine pcodeop vpmovd2m_avx512dq ;\n:VPMOVD2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x39; KReg_reg & (mod=0x3 & ZmmReg2)\n{\n\tKReg_reg = vpmovd2m_avx512dq( ZmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114560\ndefine pcodeop vpmovq2m_avx512vl ;\n:VPMOVQ2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x39; KReg_reg & (mod=0x3 & XmmReg2)\n{\n\tKReg_reg = vpmovq2m_avx512vl( XmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114562\n:VPMOVQ2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x39; KReg_reg & (mod=0x3 & YmmReg2)\n{\n\tKReg_reg = vpmovq2m_avx512vl( YmmReg2 );\n}\n\n# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114564\ndefine pcodeop vpmovq2m_avx512dq ;\n:VPMOVQ2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x39; KReg_reg & (mod=0x3 & ZmmReg2)\n{\n\tKReg_reg = vpmovq2m_avx512dq( ZmmReg2 );\n}\n\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115959\ndefine pcodeop vprolvd_avx512vl ;\n:VPROLVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tXmmResult = vprolvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115962\ndefine pcodeop vprold_avx512vl ;\n:VPROLD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tXmmResult = vprold_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask32;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115965\ndefine pcodeop vprolvq_avx512vl ;\n:VPROLVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tXmmResult = vprolvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115968\ndefine pcodeop vprolq_avx512vl ;\n:VPROLQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tXmmResult = vprolq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask64;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115971\n:VPROLVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vprolvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115974\n:VPROLD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tYmmResult = vprold_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask32;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115977\n:VPROLVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vprolvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115980\n:VPROLQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tYmmResult = vprolq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask64;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115983\ndefine pcodeop vprolvd_avx512f ;\n:VPROLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vprolvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115987\ndefine pcodeop vprold_avx512f ;\n:VPROLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tZmmResult = vprold_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask32;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115990\ndefine pcodeop vprolvq_avx512f ;\n:VPROLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vprolvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115993\ndefine pcodeop vprolq_avx512f ;\n:VPROLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tZmmResult = vprolq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask64;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116190\ndefine pcodeop vprorvd_avx512vl ;\n:VPRORVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tXmmResult = vprorvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116194\ndefine pcodeop vprord_avx512vl ;\n:VPRORD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tXmmResult = vprord_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask32;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116197\ndefine pcodeop vprorvq_avx512vl ;\n:VPRORVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tXmmResult = vprorvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116200\ndefine pcodeop vprorq_avx512vl ;\n:VPRORQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tXmmResult = vprorq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = evexV5_XmmReg;\n\tbuild XmmOpMask64;\n\tevexV5_ZmmReg = zext(XmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116203\n:VPRORVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vprorvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116207\n:VPRORD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tYmmResult = vprord_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask32;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116210\n:VPRORVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tYmmResult = vprorvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116213\n:VPRORQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tYmmResult = vprorq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = evexV5_YmmReg;\n\tbuild YmmOpMask64;\n\tevexV5_ZmmReg = zext(YmmResult);\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116216\ndefine pcodeop vprorvd_avx512f ;\n:VPRORVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vprorvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116220\ndefine pcodeop vprord_avx512f ;\n:VPRORD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tZmmResult = vprord_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask32;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116223\ndefine pcodeop vprorvq_avx512f ;\n:VPRORVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)\n{\n\tZmmResult = vprorvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116226\ndefine pcodeop vprorq_avx512f ;\n:VPRORQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)\n{\n\tZmmResult = vprorq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = evexV5_ZmmReg;\n\tbuild ZmmOpMask64;\n\tevexV5_ZmmReg = ZmmResult;\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116424\ndefine pcodeop vpscatterdd_avx512vl ;\n:VPSCATTERDD x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterdd_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116426\n:VPSCATTERDD y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterdd_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116428\ndefine pcodeop vpscatterdd_avx512f ;\n:VPSCATTERDD z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterdd_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116430\ndefine pcodeop vpscatterdq_avx512vl ;\n:VPSCATTERDQ x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterdq_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116432\n:VPSCATTERDQ y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterdq_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116434\ndefine pcodeop vpscatterdq_avx512f ;\n:VPSCATTERDQ z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterdq_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n@ifdef IA64\n#technically these should be supported in 32-bit mode, but the assembly differences are notable, and we don't handle vm64 in 32-bit\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116436\n# WARNING: did not recognize qualifier /vsib for \"VPSCATTERQD vm64x {k1}, xmm1\"\ndefine pcodeop vpscatterqd_avx512vl ;\n:VPSCATTERQD q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterqd_avx512vl( q_vm64x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116438\n# WARNING: did not recognize qualifier /vsib for \"VPSCATTERQD vm64y {k1}, xmm1\"\n:VPSCATTERQD q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterqd_avx512vl( q_vm64x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116440\n# WARNING: did not recognize qualifier /vsib for \"VPSCATTERQD vm64z {k1}, ymm1\"\ndefine pcodeop vpscatterqd_avx512f ;\n:VPSCATTERQD q_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA1; YmmReg1 ... & q_vm64y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterqd_avx512f( q_vm64y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116442\n# WARNING: did not recognize qualifier /vsib for \"VPSCATTERQQ vm64x {k1}, xmm1\"\ndefine pcodeop vpscatterqq_avx512vl ;\n:VPSCATTERQQ x_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA1; XmmReg1 ... & x_vm64x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterqq_avx512vl( x_vm64x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116444\n# WARNING: did not recognize qualifier /vsib for \"VPSCATTERQQ vm64y {k1}, ymm1\"\n:VPSCATTERQQ y_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA1; YmmReg1 ... & y_vm64y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterqq_avx512vl( y_vm64y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116446\n# WARNING: did not recognize qualifier /vsib for \"VPSCATTERQQ vm64z {k1}, zmm1\"\ndefine pcodeop vpscatterqq_avx512f ;\n:VPSCATTERQQ z_vm64z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA1; ZmmReg1 ... & z_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvpscatterqq_avx512f( z_vm64z, ZmmOpMask, ZmmReg1 );\n\t# TODO missing destination or side effects\n}\n@endif\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116632\ndefine pcodeop vpsllvw_avx512vl ;\n:VPSLLVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsllvw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116635\n:VPSLLVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsllvw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116638\ndefine pcodeop vpsllvw_avx512bw ;\n:VPSLLVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x12; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsllvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116641\ndefine pcodeop vpsllvd_avx512vl ;\n:VPSLLVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsllvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116644\n:VPSLLVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsllvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116647\ndefine pcodeop vpsllvd_avx512f ;\n:VPSLLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsllvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116650\ndefine pcodeop vpsllvq_avx512vl ;\n:VPSLLVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsllvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116653\n:VPSLLVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsllvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116656\ndefine pcodeop vpsllvq_avx512f ;\n:VPSLLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsllvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116880\ndefine pcodeop vpsravw_avx512vl ;\n:VPSRAVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x11; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsravw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116883\n:VPSRAVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x11; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsravw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116886\ndefine pcodeop vpsravw_avx512bw ;\n:VPSRAVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x11; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsravw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116889\ndefine pcodeop vpsravd_avx512vl ;\n:VPSRAVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsravd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116893\n:VPSRAVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsravd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116897\ndefine pcodeop vpsravd_avx512f ;\n:VPSRAVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsravd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116901\ndefine pcodeop vpsravq_avx512vl ;\n:VPSRAVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsravq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116905\n:VPSRAVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsravq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116910\ndefine pcodeop vpsravq_avx512f ;\n:VPSRAVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsravq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117151\ndefine pcodeop vpsrlvw_avx512vl ;\n:VPSRLVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tXmmResult = vpsrlvw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117154\n:VPSRLVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tYmmResult = vpsrlvw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117157\ndefine pcodeop vpsrlvw_avx512bw ;\n:VPSRLVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x10; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tZmmResult = vpsrlvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117160\ndefine pcodeop vpsrlvd_avx512vl ;\n:VPSRLVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsrlvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117163\n:VPSRLVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsrlvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117166\ndefine pcodeop vpsrlvd_avx512f ;\n:VPSRLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsrlvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117169\ndefine pcodeop vpsrlvq_avx512vl ;\n:VPSRLVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpsrlvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117172\n:VPSRLVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpsrlvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117175\ndefine pcodeop vpsrlvq_avx512f ;\n:VPSRLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpsrlvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117395\ndefine pcodeop vpternlogd_avx512vl ;\n:VPTERNLOGD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpternlogd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117400\n:VPTERNLOGD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpternlogd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117405\ndefine pcodeop vpternlogd_avx512f ;\n:VPTERNLOGD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpternlogd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117410\ndefine pcodeop vpternlogq_avx512vl ;\n:VPTERNLOGQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vpternlogq_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117415\n:VPTERNLOGQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vpternlogq_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117420\ndefine pcodeop vpternlogq_avx512f ;\n:VPTERNLOGQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vpternlogq_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117559\ndefine pcodeop vptestmb_avx512vl ;\n:VPTESTMB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestmb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117562\n:VPTESTMB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestmb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117565\ndefine pcodeop vptestmb_avx512bw ;\n:VPTESTMB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,64]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117568\ndefine pcodeop vptestmw_avx512vl ;\n:VPTESTMW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestmw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117571\n:VPTESTMW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestmw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117574\ndefine pcodeop vptestmw_avx512bw ;\n:VPTESTMW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117577\ndefine pcodeop vptestmd_avx512vl ;\n:VPTESTMD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestmd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117581\n:VPTESTMD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestmd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117585\ndefine pcodeop vptestmd_avx512f ;\n:VPTESTMD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117589\ndefine pcodeop vptestmq_avx512vl ;\n:VPTESTMQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestmq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117593\n:VPTESTMQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestmq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117597\ndefine pcodeop vptestmq_avx512f ;\n:VPTESTMQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117717\ndefine pcodeop vptestnmb_avx512vl ;\n:VPTESTNMB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestnmb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117721\n:VPTESTNMB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestnmb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117725\ndefine pcodeop vptestnmb_avx512f ;\n:VPTESTNMB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestnmb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,64]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117729\ndefine pcodeop vptestnmw_avx512vl ;\n:VPTESTNMW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestnmw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117733\n:VPTESTNMW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestnmw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117737\ndefine pcodeop vptestnmw_avx512f ;\n:VPTESTNMW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)\n{\n\tlocal tmp = vptestnmw_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );\n\tKReg_reg = zext(AVXOpMask[0,32]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117741\ndefine pcodeop vptestnmd_avx512vl ;\n:VPTESTNMD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestnmd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117745\n:VPTESTNMD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestnmd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117749\ndefine pcodeop vptestnmd_avx512f ;\n:VPTESTNMD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestnmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tKReg_reg = zext(AVXOpMask[0,16]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117753\ndefine pcodeop vptestnmq_avx512vl ;\n:VPTESTNMQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestnmq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,2]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117757\n:VPTESTNMQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestnmq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,4]) & tmp;\n}\n\n# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117761\ndefine pcodeop vptestnmq_avx512f ;\n:VPTESTNMQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tlocal tmp = vptestnmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tKReg_reg = zext(AVXOpMask[0,8]) & tmp;\n}\n\n# VRANGEPD 5-470 PAGE 2294 LINE 117905\ndefine pcodeop vrangepd_avx512vl ;\n:VRANGEPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrangepd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRANGEPD 5-470 PAGE 2294 LINE 117910\n:VRANGEPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrangepd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRANGEPD 5-470 PAGE 2294 LINE 117915\ndefine pcodeop vrangepd_avx512dq ;\n:VRANGEPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrangepd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRANGEPS 5-475 PAGE 2299 LINE 118139\ndefine pcodeop vrangeps_avx512vl ;\n:VRANGEPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrangeps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRANGEPS 5-475 PAGE 2299 LINE 118144\n:VRANGEPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrangeps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRANGEPS 5-475 PAGE 2299 LINE 118149\ndefine pcodeop vrangeps_avx512dq ;\n:VRANGEPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrangeps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRANGESD 5-479 PAGE 2303 LINE 118318\ndefine pcodeop vrangesd_avx512dq ;\n:VRANGESD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrangesd_avx512dq( evexV5_XmmReg, XmmReg2_m64, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRANGESS 5-482 PAGE 2306 LINE 118473\ndefine pcodeop vrangess_avx512dq ;\n:VRANGESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrangess_avx512dq( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCP14PD 5-485 PAGE 2309 LINE 118626\ndefine pcodeop vrcp14pd_avx512vl ;\n:VRCP14PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrcp14pd_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCP14PD 5-485 PAGE 2309 LINE 118629\n:VRCP14PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrcp14pd_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRCP14PD 5-485 PAGE 2309 LINE 118632\ndefine pcodeop vrcp14pd_avx512f ;\n:VRCP14PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrcp14pd_avx512f( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRCP14SD 5-487 PAGE 2311 LINE 118726\ndefine pcodeop vrcp14sd_avx512f ;\n:VRCP14SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrcp14sd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCP14PS 5-489 PAGE 2313 LINE 118800\ndefine pcodeop vrcp14ps_avx512vl ;\n:VRCP14PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrcp14ps_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCP14PS 5-489 PAGE 2313 LINE 118803\n:VRCP14PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrcp14ps_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRCP14PS 5-489 PAGE 2313 LINE 118806\ndefine pcodeop vrcp14ps_avx512f ;\n:VRCP14PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrcp14ps_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRCP14SS 5-491 PAGE 2315 LINE 118904\ndefine pcodeop vrcp14ss_avx512f ;\n:VRCP14SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrcp14ss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCP28PD 5-493 PAGE 2317 LINE 118979\ndefine pcodeop vrcp28pd_avx512er ;\n:VRCP28PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrcp28pd_avx512er( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRCP28SD 5-495 PAGE 2319 LINE 119074\ndefine pcodeop vrcp28sd_avx512er ;\n:VRCP28SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrcp28sd_avx512er( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCP28PS 5-497 PAGE 2321 LINE 119167\ndefine pcodeop vrcp28ps_avx512er ;\n:VRCP28PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrcp28ps_avx512er( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRCP28SS 5-499 PAGE 2323 LINE 119263\ndefine pcodeop vrcp28ss_avx512er ;\n:VRCP28SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrcp28ss_avx512er( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VREDUCEPD 5-501 PAGE 2325 LINE 119356\ndefine pcodeop vreducepd_avx512vl ;\n:VREDUCEPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vreducepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VREDUCEPD 5-501 PAGE 2325 LINE 119360\n:VREDUCEPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vreducepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VREDUCEPD 5-501 PAGE 2325 LINE 119364\ndefine pcodeop vreducepd_avx512dq ;\n:VREDUCEPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vreducepd_avx512dq( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VREDUCESD 5-504 PAGE 2328 LINE 119510\ndefine pcodeop vreducesd_avx512dq ;\n:VREDUCESD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vreducesd_avx512dq( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VREDUCEPS 5-506 PAGE 2330 LINE 119605\ndefine pcodeop vreduceps_avx512vl ;\n:VREDUCEPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vreduceps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VREDUCEPS 5-506 PAGE 2330 LINE 119609\n:VREDUCEPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vreduceps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VREDUCEPS 5-506 PAGE 2330 LINE 119613\ndefine pcodeop vreduceps_avx512dq ;\n:VREDUCEPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vreduceps_avx512dq( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VREDUCESS 5-508 PAGE 2332 LINE 119719\ndefine pcodeop vreducess_avx512dq ;\n:VREDUCESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vreducess_avx512dq( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRNDSCALEPD 5-510 PAGE 2334 LINE 119814\ndefine pcodeop vrndscalepd_avx512vl ;\n:VRNDSCALEPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrndscalepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRNDSCALEPD 5-510 PAGE 2334 LINE 119818\n:VRNDSCALEPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrndscalepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRNDSCALEPD 5-510 PAGE 2334 LINE 119822\ndefine pcodeop vrndscalepd_avx512f ;\n:VRNDSCALEPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrndscalepd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRNDSCALESD 5-514 PAGE 2338 LINE 119998\ndefine pcodeop vrndscalesd_avx512f ;\n:VRNDSCALESD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrndscalesd_avx512f( evexV5_XmmReg, XmmReg2_m64, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRNDSCALEPS 5-516 PAGE 2340 LINE 120116\ndefine pcodeop vrndscaleps_avx512vl ;\n:VRNDSCALEPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrndscaleps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRNDSCALEPS 5-516 PAGE 2340 LINE 120120\n:VRNDSCALEPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrndscaleps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRNDSCALEPS 5-516 PAGE 2340 LINE 120124\ndefine pcodeop vrndscaleps_avx512f ;\n:VRNDSCALEPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrndscaleps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRNDSCALESS 5-519 PAGE 2343 LINE 120263\ndefine pcodeop vrndscaless_avx512f ;\n:VRNDSCALESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrndscaless_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRT14PD 5-521 PAGE 2345 LINE 120381\ndefine pcodeop vrsqrt14pd_avx512vl ;\n:VRSQRT14PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrsqrt14pd_avx512vl( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRT14PD 5-521 PAGE 2345 LINE 120385\n:VRSQRT14PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrsqrt14pd_avx512vl( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRSQRT14PD 5-521 PAGE 2345 LINE 120389\ndefine pcodeop vrsqrt14pd_avx512f ;\n:VRSQRT14PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrsqrt14pd_avx512f( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRSQRT14SD 5-523 PAGE 2347 LINE 120491\ndefine pcodeop vrsqrt14sd_avx512f ;\n:VRSQRT14SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrsqrt14sd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRT14PS 5-525 PAGE 2349 LINE 120578\ndefine pcodeop vrsqrt14ps_avx512vl ;\n:VRSQRT14PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vrsqrt14ps_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRT14PS 5-525 PAGE 2349 LINE 120582\n:VRSQRT14PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vrsqrt14ps_avx512vl( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRSQRT14PS 5-525 PAGE 2349 LINE 120586\ndefine pcodeop vrsqrt14ps_avx512f ;\n:VRSQRT14PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrsqrt14ps_avx512f( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRSQRT14SS 5-527 PAGE 2351 LINE 120690\ndefine pcodeop vrsqrt14ss_avx512f ;\n:VRSQRT14SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrsqrt14ss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRT28PD 5-529 PAGE 2353 LINE 120778\ndefine pcodeop vrsqrt28pd_avx512er ;\n:VRSQRT28PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrsqrt28pd_avx512er( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRSQRT28SD 5-531 PAGE 2355 LINE 120869\ndefine pcodeop vrsqrt28sd_avx512er ;\n:VRSQRT28SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrsqrt28sd_avx512er( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRT28PS 5-533 PAGE 2357 LINE 120959\ndefine pcodeop vrsqrt28ps_avx512er ;\n:VRSQRT28PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vrsqrt28ps_avx512er( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRSQRT28SS 5-535 PAGE 2359 LINE 121051\ndefine pcodeop vrsqrt28ss_avx512er ;\n:VRSQRT28SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vrsqrt28ss_avx512er( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCALEFPD 5-537 PAGE 2361 LINE 121140\ndefine pcodeop vscalefpd_avx512vl ;\n:VSCALEFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vscalefpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCALEFPD 5-537 PAGE 2361 LINE 121143\n:VSCALEFPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vscalefpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSCALEFPD 5-537 PAGE 2361 LINE 121146\ndefine pcodeop vscalefpd_avx512f ;\n:VSCALEFPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vscalefpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSCALEFSD 5-540 PAGE 2364 LINE 121269\ndefine pcodeop vscalefsd_avx512f ;\n:VSCALEFSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vscalefsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCALEFPS 5-542 PAGE 2366 LINE 121355\ndefine pcodeop vscalefps_avx512vl ;\n:VSCALEFPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vscalefps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCALEFPS 5-542 PAGE 2366 LINE 121358\n:VSCALEFPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vscalefps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSCALEFPS 5-542 PAGE 2366 LINE 121361\ndefine pcodeop vscalefps_avx512f ;\n:VSCALEFPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vscalefps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSCALEFSS 5-544 PAGE 2368 LINE 121470\ndefine pcodeop vscalefss_avx512f ;\n:VSCALEFSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tXmmResult = vscalefss_avx512f( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121559\ndefine pcodeop vscatterdps_avx512vl ;\n:VSCATTERDPS x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterdps_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121561\n:VSCATTERDPS y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterdps_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121563\ndefine pcodeop vscatterdps_avx512f ;\n:VSCATTERDPS z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterdps_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121565\ndefine pcodeop vscatterdpd_avx512vl ;\n:VSCATTERDPD x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterdpd_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121567\n:VSCATTERDPD y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterdpd_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121569\ndefine pcodeop vscatterdpd_avx512f ;\n:VSCATTERDPD z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterdpd_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n@ifdef IA64\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121571\ndefine pcodeop vscatterqps_avx512vl ;\n:VSCATTERQPS q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterqps_avx512vl( q_vm64x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121573\n:VSCATTERQPS q_vm64y^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterqps_avx512vl( q_vm64y, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121575\ndefine pcodeop vscatterqps_avx512f ;\n:VSCATTERQPS q_vm64z^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA3; YmmReg1 ... & q_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterqps_avx512f( q_vm64z, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121577\ndefine pcodeop vscatterqpd_avx512vl ;\n:VSCATTERQPD x_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA3; XmmReg1 ... & x_vm64x\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterqpd_avx512vl( x_vm64x, XmmOpMask, XmmReg1 );\n\t# TODO missing destination or side effects\n}\n\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121579\n:VSCATTERQPD y_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA3; YmmReg1 ... & y_vm64y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterqpd_avx512vl( y_vm64y, YmmOpMask, YmmReg1 );\n\t# TODO missing destination or side effects\n}\n@endif\n\n@ifdef IA64\n# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121581\ndefine pcodeop vscatterqpd_avx512f ;\n:VSCATTERQPD z_vm64z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA3; ZmmReg1 ... & z_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterqpd_avx512f( z_vm64z, ZmmOpMask, ZmmReg1 );\n\t# TODO missing destination or side effects\n}\n@endif\n\n# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121759\ndefine pcodeop vscatterpf0dps_avx512pf ;\n:VSCATTERPF0DPS z_vm32z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=5 ... & z_vm32z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf0dps_avx512pf( z_vm32z , ZmmOpMask);\n\t# TODO missing destination or side effects\n}\n\n@ifdef IA64\n# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121762\ndefine pcodeop vscatterpf0qps_avx512pf ;\n:VSCATTERPF0QPS z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf0qps_avx512pf( z_vm64z, ZmmOpMask );\n\t# TODO missing destination or side effects\n}\n@endif\n\n# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121765\ndefine pcodeop vscatterpf0dpd_avx512pf ;\n:VSCATTERPF0DPD y_vm32y^YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=5 ... & y_vm32y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf0dpd_avx512pf( y_vm32y, YmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n@ifdef IA64\n# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121768\ndefine pcodeop vscatterpf0qpd_avx512pf ;\n:VSCATTERPF0QPD z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf0qpd_avx512pf( z_vm64z, ZmmOpMask );\n\t# TODO missing destination or side effects\n}\n@endif\n\n# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121877\ndefine pcodeop vscatterpf1dps_avx512pf ;\n:VSCATTERPF1DPS z_vm32z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=6 ... & z_vm32z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf1dps_avx512pf( z_vm32z, ZmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n@ifdef IA64\n# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121880\ndefine pcodeop vscatterpf1qps_avx512pf ;\n:VSCATTERPF1QPS z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf1qps_avx512pf( z_vm64z, ZmmOpMask );\n\t# TODO missing destination or side effects\n}\n@endif\n\n# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121883\ndefine pcodeop vscatterpf1dpd_avx512pf ;\n:VSCATTERPF1DPD y_vm32y^YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=6 ... & y_vm32y\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf1dpd_avx512pf( y_vm32y, YmmOpMask );\n\t# TODO missing destination or side effects\n}\n\n@ifdef IA64\n# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121886\ndefine pcodeop vscatterpf1qpd_avx512pf ;\n:VSCATTERPF1QPD z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)\n{\n\tvscatterpf1qpd_avx512pf( z_vm64z, ZmmOpMask );\n\t# TODO missing destination or side effects\n}\n@endif\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121994\ndefine pcodeop vshuff32x4_avx512vl ;\n:VSHUFF32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vshuff32x4_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121998\ndefine pcodeop vshuff32x4_avx512f ;\n:VSHUFF32x4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vshuff32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122002\ndefine pcodeop vshuff64x2_avx512vl ;\n:VSHUFF64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vshuff64x2_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122006\ndefine pcodeop vshuff64x2_avx512f ;\n:VSHUFF64x2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vshuff64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122010\ndefine pcodeop vshufi32x4_avx512vl ;\n:VSHUFI32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vshufi32x4_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122013\ndefine pcodeop vshufi32x4_avx512f ;\n:VSHUFI32x4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vshufi32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122016\ndefine pcodeop vshufi64x2_avx512vl ;\n:VSHUFI64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vshufi64x2_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122019\ndefine pcodeop vshufi64x2_avx512f ;\n:VSHUFI64x2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vshufi64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# XORPD 5-596 PAGE 2420 LINE 123834\ndefine pcodeop vxorpd_avx512vl ;\n:VXORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vxorpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# XORPD 5-596 PAGE 2420 LINE 123837\n:VXORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vxorpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# XORPD 5-596 PAGE 2420 LINE 123840\ndefine pcodeop vxorpd_avx512dq ;\n:VXORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vxorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# XORPS 5-599 PAGE 2423 LINE 123959\ndefine pcodeop vxorps_avx512vl ;\n:VXORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tXmmResult = vxorps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# XORPS 5-599 PAGE 2423 LINE 123962\n:VXORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tYmmResult = vxorps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# XORPS 5-599 PAGE 2423 LINE 123965\ndefine pcodeop vxorps_avx512dq ;\n:VXORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)\n{\n\tZmmResult = vxorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# AVX512 BMI, FMA, and FP16 updates\n\n# AESDEC 3-51 PAGE 621 LINE 35875\ndefine pcodeop vaesdec_vaes ;\n:VAESDEC XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:16 = vaesdec_vaes( evexV5_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESDEC 3-51 PAGE 621 LINE 35879\n:VAESDEC YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:32 = vaesdec_vaes( evexV5_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESDEC 3-51 PAGE 621 LINE 35883\n:VAESDEC ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDE; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmReg1 = vaesdec_vaes( evexV5_ZmmReg, ZmmReg2_m512 );\n}\n\n# AESDECLAST 3-57 PAGE 627 LINE 36144\ndefine pcodeop vaesdeclast_vaes ;\n:VAESDECLAST XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:16 = vaesdeclast_vaes( evexV5_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESDECLAST 3-57 PAGE 627 LINE 36148\n:VAESDECLAST YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:32 = vaesdeclast_vaes( evexV5_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESDECLAST 3-57 PAGE 627 LINE 36152\n:VAESDECLAST ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDF; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmReg1 = vaesdeclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 );\n}\n\n# AESENC 3-63 PAGE 633 LINE 36420\ndefine pcodeop vaesenc_vaes ;\n:VAESENC XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:16 = vaesenc_vaes( evexV5_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESENC 3-63 PAGE 633 LINE 36423\n:VAESENC YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:32 = vaesenc_vaes( evexV5_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESENC 3-63 PAGE 633 LINE 36426\n:VAESENC ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDC; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmReg1 = vaesenc_vaes( evexV5_ZmmReg, ZmmReg2_m512 );\n}\n\n# AESENCLAST 3-69 PAGE 639 LINE 36687\ndefine pcodeop vaesenclast_vaes ;\n:VAESENCLAST XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:16 = vaesenclast_vaes( evexV5_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESENCLAST 3-69 PAGE 639 LINE 36691\n:VAESENCLAST YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:32 = vaesenclast_vaes( evexV5_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# AESENCLAST 3-69 PAGE 639 LINE 36695\n:VAESENCLAST ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDD; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmReg1 = vaesenclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 );\n}\n\n# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56498\ndefine pcodeop vgf2p8affineinvqb_avx512vl ;\n:VGF2P8AFFINEINVQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vgf2p8affineinvqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56501\n:VGF2P8AFFINEINVQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vgf2p8affineinvqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56504\ndefine pcodeop vgf2p8affineinvqb_avx512f ;\n:VGF2P8AFFINEINVQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vgf2p8affineinvqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56642\ndefine pcodeop vgf2p8affineqb_avx512vl ;\n:VGF2P8AFFINEQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vgf2p8affineqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56645\n:VGF2P8AFFINEQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vgf2p8affineqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56648\ndefine pcodeop vgf2p8affineqb_avx512f ;\n:VGF2P8AFFINEQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCE; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vgf2p8affineqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# GF2P8MULB 3-481 PAGE 1051 LINE 56754\ndefine pcodeop vgf2p8mulb_avx512vl ;\n:VGF2P8MULB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vgf2p8mulb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# GF2P8MULB 3-481 PAGE 1051 LINE 56757\n:VGF2P8MULB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vgf2p8mulb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# GF2P8MULB 3-481 PAGE 1051 LINE 56760\ndefine pcodeop vgf2p8mulb_avx512f ;\n:VGF2P8MULB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vgf2p8mulb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# PCLMULQDQ 4-242 PAGE 1362 LINE 76037\ndefine pcodeop vpclmulqdq_vpclmulqdq ;\n:VPCLMULQDQ XmmReg1, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:16 = vpclmulqdq_vpclmulqdq( evexV5_XmmReg, XmmReg2_m128, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCLMULQDQ 4-242 PAGE 1362 LINE 76042\n:VPCLMULQDQ YmmReg1, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x44; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:32 = vpclmulqdq_vpclmulqdq( evexV5_YmmReg, YmmReg2_m256, imm8:1 );\n\tZmmReg1 = zext(tmp);\n}\n\n# PCLMULQDQ 4-242 PAGE 1362 LINE 76047\n:VPCLMULQDQ ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x44; ZmmReg1 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmReg1 = vpclmulqdq_vpclmulqdq( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );\n}\n\n# VADDPH 5-5 PAGE 1829 LINE 101735\ndefine pcodeop vaddph_avx512fp16 ;\n:VADDPH XmmReg1 XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vaddph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VADDPH 5-5 PAGE 1829 LINE 101738\n:VADDPH YmmReg1 YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vaddph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VADDPH 5-5 PAGE 1829 LINE 101741\n:VADDPH ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x58; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vaddph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VADDSH 5-7 PAGE 1831 LINE 101824\ndefine pcodeop vaddsh_avx512fp16 ;\n:VADDSH XmmReg1 XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vaddsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\nVCMPPH_mon: \"VCMPEQPH\" is imm8=0x0 { }\nVCMPPH_op: \"\" is imm8=0x0 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPLTPH\" is imm8=0x1 { }\nVCMPPH_op: \"\" is imm8=0x1 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPLEPH\" is imm8=0x2 { }\nVCMPPH_op: \"\" is imm8=0x2 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPUNORDPH\" is imm8=0x3 { }\nVCMPPH_op: \"\" is imm8=0x3 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNEQPH\" is imm8=0x4 { }\nVCMPPH_op: \"\" is imm8=0x4 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNLTPH\" is imm8=0x5 { }\nVCMPPH_op: \"\" is imm8=0x5 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNLEPH\" is imm8=0x6 { }\nVCMPPH_op: \"\" is imm8=0x6 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPORDPH\" is imm8=0x7 { }\nVCMPPH_op: \"\" is imm8=0x7 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPEQ_UQPH\" is imm8=0x8 { }\nVCMPPH_op: \"\" is imm8=0x8 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNGEPH\" is imm8=0x9 { }\nVCMPPH_op: \"\" is imm8=0x9 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNGTPH\" is imm8=0xa { }\nVCMPPH_op: \"\" is imm8=0xa & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPFALSEPH\" is imm8=0xb { }\nVCMPPH_op: \"\" is imm8=0xb & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNEQ_OQPH\" is imm8=0xc { }\nVCMPPH_op: \"\" is imm8=0xc & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPGEPH\" is imm8=0xd { }\nVCMPPH_op: \"\" is imm8=0xd & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPGTPH\" is imm8=0xe { }\nVCMPPH_op: \"\" is imm8=0xe & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPTRUEPH\" is imm8=0xf { }\nVCMPPH_op: \"\" is imm8=0xf & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPEQ_OSPH\" is imm8=0x10 { }\nVCMPPH_op: \"\" is imm8=0x10 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPLT_OQPH\" is imm8=0x11 { }\nVCMPPH_op: \"\" is imm8=0x11 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPLE_OQPH\" is imm8=0x12 { }\nVCMPPH_op: \"\" is imm8=0x12 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPUNORD_SPH\" is imm8=0x13 { }\nVCMPPH_op: \"\" is imm8=0x13 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNEQ_USPH\" is imm8=0x14 { }\nVCMPPH_op: \"\" is imm8=0x14 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNLT_UQPH\" is imm8=0x15 { }\nVCMPPH_op: \"\" is imm8=0x15 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNLE_UQPH\" is imm8=0x16 { }\nVCMPPH_op: \"\" is imm8=0x16 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPORD_SPH\" is imm8=0x17 { }\nVCMPPH_op: \"\" is imm8=0x17 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPEQ_USPH\" is imm8=0x18 { }\nVCMPPH_op: \"\" is imm8=0x18 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNGE_UQPH\" is imm8=0x19 { }\nVCMPPH_op: \"\" is imm8=0x19 & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNGT_UQPH\" is imm8=0x1a { }\nVCMPPH_op: \"\" is imm8=0x1a & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPFALSE_OSPH\" is imm8=0x1b { }\nVCMPPH_op: \"\" is imm8=0x1b & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPNEQ_OSPH\" is imm8=0x1c { }\nVCMPPH_op: \"\" is imm8=0x1c & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPGE_OQPH\" is imm8=0x1d { }\nVCMPPH_op: \"\" is imm8=0x1d & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPGT_OQPH\" is imm8=0x1e { }\nVCMPPH_op: \"\" is imm8=0x1e & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPTRUE_USPH\" is imm8=0x1f { }\nVCMPPH_op: \"\" is imm8=0x1f & imm8_val { export *[const]:1 imm8_val; }\nVCMPPH_mon: \"VCMPPH\" is imm8 { }\nVCMPPH_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\ndefine pcodeop vcmpph_avx512fp16;\n:^VCMPPH_mon KReg_reg^XmmOpMask, evexV5_XmmReg, XmmReg2_m128_m16bcst^VCMPPH_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m16bcst; VCMPPH_mon & VCMPPH_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vcmpph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst, XmmOpMask, VCMPPH_op );\n}\n\n# VCMPPH 5-21 PAGE 1845 LINE 102586\n:^VCMPPH_mon KReg_reg^YmmOpMask, evexV5_YmmReg, YmmReg2_m256_m16bcst^VCMPPH_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask & evexV5_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m16bcst; VCMPPH_mon & VCMPPH_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\n\tKReg_reg = vcmpph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst, YmmOpMask, VCMPPH_op );\n}\n\n# VCMPPH 5-21 PAGE 1845 LINE 102590\n:^VCMPPH_mon KReg_reg^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512_m16bcst^VCMPPH_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m16bcst; VCMPPH_mon & VCMPPH_op\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vcmpph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst, ZmmOpMask, VCMPPH_op );\n}\n\nVCMPSH_mon: \"VCMPEQSH\" is imm8=0x0 { }\nVCMPSH_op: \"\" is imm8=0x0 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPLTSH\" is imm8=0x1 { }\nVCMPSH_op: \"\" is imm8=0x1 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPLESH\" is imm8=0x2 { }\nVCMPSH_op: \"\" is imm8=0x2 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPUNORDSH\" is imm8=0x3 { }\nVCMPSH_op: \"\" is imm8=0x3 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNEQSH\" is imm8=0x4 { }\nVCMPSH_op: \"\" is imm8=0x4 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNLTSH\" is imm8=0x5 { }\nVCMPSH_op: \"\" is imm8=0x5 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNLESH\" is imm8=0x6 { }\nVCMPSH_op: \"\" is imm8=0x6 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPORDSH\" is imm8=0x7 { }\nVCMPSH_op: \"\" is imm8=0x7 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPEQ_UQSH\" is imm8=0x8 { }\nVCMPSH_op: \"\" is imm8=0x8 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNGESH\" is imm8=0x9 { }\nVCMPSH_op: \"\" is imm8=0x9 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNGTSH\" is imm8=0xa { }\nVCMPSH_op: \"\" is imm8=0xa & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPFALSESH\" is imm8=0xb { }\nVCMPSH_op: \"\" is imm8=0xb & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNEQ_OQSH\" is imm8=0xc { }\nVCMPSH_op: \"\" is imm8=0xc & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPGESH\" is imm8=0xd { }\nVCMPSH_op: \"\" is imm8=0xd & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPGTSH\" is imm8=0xe { }\nVCMPSH_op: \"\" is imm8=0xe & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPTRUESH\" is imm8=0xf { }\nVCMPSH_op: \"\" is imm8=0xf & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPEQ_OSSH\" is imm8=0x10 { }\nVCMPSH_op: \"\" is imm8=0x10 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPLT_OQSH\" is imm8=0x11 { }\nVCMPSH_op: \"\" is imm8=0x11 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPLE_OQSH\" is imm8=0x12 { }\nVCMPSH_op: \"\" is imm8=0x12 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPUNORD_SSH\" is imm8=0x13 { }\nVCMPSH_op: \"\" is imm8=0x13 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNEQ_USSH\" is imm8=0x14 { }\nVCMPSH_op: \"\" is imm8=0x14 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNLT_UQSH\" is imm8=0x15 { }\nVCMPSH_op: \"\" is imm8=0x15 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNLE_UQSH\" is imm8=0x16 { }\nVCMPSH_op: \"\" is imm8=0x16 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPORD_SSH\" is imm8=0x17 { }\nVCMPSH_op: \"\" is imm8=0x17 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPEQ_USSH\" is imm8=0x18 { }\nVCMPSH_op: \"\" is imm8=0x18 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNGE_UQSH\" is imm8=0x19 { }\nVCMPSH_op: \"\" is imm8=0x19 & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNGT_UQSH\" is imm8=0x1a { }\nVCMPSH_op: \"\" is imm8=0x1a & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPFALSE_OSSH\" is imm8=0x1b { }\nVCMPSH_op: \"\" is imm8=0x1b & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPNEQ_OSSH\" is imm8=0x1c { }\nVCMPSH_op: \"\" is imm8=0x1c & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPGE_OQSH\" is imm8=0x1d { }\nVCMPSH_op: \"\" is imm8=0x1d & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPGT_OQSH\" is imm8=0x1e { }\nVCMPSH_op: \"\" is imm8=0x1e & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPTRUE_USSH\" is imm8=0x1f { }\nVCMPSH_op: \"\" is imm8=0x1f & imm8_val { export *[const]:1 imm8_val; }\nVCMPSH_mon: \"VCMPSH\" is imm8 { }\nVCMPSH_op: \", \"^imm8 is imm8 { export *[const]:1 imm8; }\n\n# VCMPSH 5-23 PAGE 1847 LINE 102692\ndefine pcodeop vcmpsh_avx512fp16 ;\n:^VCMPSH_mon KReg_reg^XmmOpMask, evexV5_XmmReg, XmmReg2_m16^VCMPSH_op is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m16; VCMPSH_mon & VCMPSH_op\n{\n\tKReg_reg = vcmpsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, XmmOpMask, VCMPSH_op );\n}\n\n# VCOMISH 5-25 PAGE 1849 LINE 102783\ndefine pcodeop vcomish_avx512fp16 ;\n:VCOMISH XmmReg1, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0); byte=0x2F; XmmReg1 ... & XmmReg2_m16\n{\n\tvcomish_avx512fp16( XmmReg1, XmmReg2_m16 );\n\t# TODO missing destination or side effects\n}\n\n# VCVTDQ2PH 5-31 PAGE 1855 LINE 103058\ndefine pcodeop vcvtdq2ph_avx512fp16 ;\n:VCVTDQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtdq2ph_avx512fp16( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTDQ2PH 5-31 PAGE 1855 LINE 103062\n:VCVTDQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtdq2ph_avx512fp16( YmmReg2_m256_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\t\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTDQ2PH 5-31 PAGE 1855 LINE 103066\n:VCVTDQ2PH YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x5B; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtdq2ph_avx512fp16( ZmmReg2_m512_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTNE2PS2BF16 5-33 PAGE 1857 LINE 103147\ndefine pcodeop vcvtne2ps2bf16_avx512vl ;\n:VCVTNE2PS2BF16 XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtne2ps2bf16_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTNE2PS2BF16 5-33 PAGE 1857 LINE 103150\n:VCVTNE2PS2BF16 YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x72; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtne2ps2bf16_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTNE2PS2BF16 5-33 PAGE 1857 LINE 103153\ndefine pcodeop vcvtne2ps2bf16_avx512f ;\n:VCVTNE2PS2BF16 ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x72; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvtne2ps2bf16_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTNEPS2BF16 5-35 PAGE 1859 LINE 103231\ndefine pcodeop vcvtneps2bf16_avx512vl ;\n:VCVTNEPS2BF16 XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtneps2bf16_avx512vl( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTNEPS2BF16 5-35 PAGE 1859 LINE 103234\n:VCVTNEPS2BF16 XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x72; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtneps2bf16_avx512vl( YmmReg2_m256_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTNEPS2BF16 5-35 PAGE 1859 LINE 103237\ndefine pcodeop vcvtneps2bf16_avx512f ;\n:VCVTNEPS2BF16 YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x72; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtneps2bf16_avx512f( ZmmReg2_m512_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPD2PH 5-37 PAGE 1861 LINE 103327\ndefine pcodeop vcvtpd2ph_avx512fp16 ;\n:VCVTPD2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtpd2ph_avx512fp16( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,32]);\n}\n\n# VCVTPD2PH 5-37 PAGE 1861 LINE 103331\n:VCVTPD2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtpd2ph_avx512fp16( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTPD2PH 5-37 PAGE 1861 LINE 103335\n:VCVTPD2PH XmmReg1^XmmOpMask16, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5A; (XmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtpd2ph_avx512fp16( ZmmReg2_m512_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2DQ 5-45 PAGE 1869 LINE 103774\ndefine pcodeop vcvtph2dq_avx512fp16 ;\n:VCVTPH2DQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tXmmResult = vcvtph2dq_avx512fp16( XmmReg2_m64_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2DQ 5-45 PAGE 1869 LINE 103778\n:VCVTPH2DQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x5B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tYmmResult = vcvtph2dq_avx512fp16( XmmReg2_m128_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2DQ 5-45 PAGE 1869 LINE 103782\n:VCVTPH2DQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x5B; ZmmReg1 ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tZmmResult = vcvtph2dq_avx512fp16( YmmReg2_m256_m16bcst );\n ZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2PD 5-47 PAGE 1871 LINE 103861\ndefine pcodeop vcvtph2pd_avx512fp16 ;\n:VCVTPH2PD XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst\n{\n\tXmmResult = vcvtph2pd_avx512fp16( XmmReg2_m32_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2PD 5-47 PAGE 1871 LINE 103864\n:VCVTPH2PD YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n{\n\tYmmResult = vcvtph2pd_avx512fp16( XmmReg2_m64_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2PD 5-47 PAGE 1871 LINE 103867\n:VCVTPH2PD ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x5A; ZmmReg1 ... & XmmReg2_m128_m16bcst\n{\n\tZmmResult = vcvtph2pd_avx512fp16( XmmReg2_m128_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2PS/VCVTPH2PSX 5-49 PAGE 1873 LINE 103953\ndefine pcodeop vcvtph2psx_avx512fp16 ;\n:VCVTPH2PSX XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32; byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tXmmResult = vcvtph2psx_avx512fp16( XmmReg2_m64_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2PS/VCVTPH2PSX 5-49 PAGE 1873 LINE 103957\n:VCVTPH2PSX YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32; byte=0x13; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tYmmResult = vcvtph2psx_avx512fp16( XmmReg2_m128_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2PS/VCVTPH2PSX 5-49 PAGE 1873 LINE 103961\n:VCVTPH2PSX ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32; byte=0x13; ZmmReg1 ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tZmmResult = vcvtph2psx_avx512fp16( YmmReg2_m256_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2QQ 5-53 PAGE 1877 LINE 104149\ndefine pcodeop vcvtph2qq_avx512fp16 ;\n:VCVTPH2QQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x7B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst\n{\n\tXmmResult = vcvtph2qq_avx512fp16( XmmReg2_m32_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2QQ 5-53 PAGE 1877 LINE 104152\n:VCVTPH2QQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x7B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n{\n\tYmmResult = vcvtph2qq_avx512fp16( XmmReg2_m64_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2QQ 5-53 PAGE 1877 LINE 104155\n:VCVTPH2QQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x7B; ZmmReg1 ... & XmmReg2_m128_m16bcst\n{\n\tZmmResult = vcvtph2qq_avx512fp16( XmmReg2_m128_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2UDQ 5-55 PAGE 1879 LINE 104237\ndefine pcodeop vcvtph2udq_avx512fp16 ;\n:VCVTPH2UDQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tXmmResult = vcvtph2udq_avx512fp16( XmmReg2_m64_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2UDQ 5-55 PAGE 1879 LINE 104241\n:VCVTPH2UDQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tYmmResult = vcvtph2udq_avx512fp16( XmmReg2_m128_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2UDQ 5-55 PAGE 1879 LINE 104245\n:VCVTPH2UDQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x79; ZmmReg1 ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tZmmResult = vcvtph2udq_avx512fp16( YmmReg2_m256_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2UQQ 5-57 PAGE 1881 LINE 104324\ndefine pcodeop vcvtph2uqq_avx512fp16 ;\n:VCVTPH2UQQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst\n{\n\tXmmResult = vcvtph2uqq_avx512fp16( XmmReg2_m32_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2UQQ 5-57 PAGE 1881 LINE 104327\n:VCVTPH2UQQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n{\n\tYmmResult = vcvtph2uqq_avx512fp16( XmmReg2_m64_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2UQQ 5-57 PAGE 1881 LINE 104331\n:VCVTPH2UQQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x79; ZmmReg1 ... & XmmReg2_m128_m16bcst\n{\n\tZmmResult = vcvtph2uqq_avx512fp16( XmmReg2_m128_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2UW 5-59 PAGE 1883 LINE 104412\ndefine pcodeop vcvtph2uw_avx512fp16 ;\n:VCVTPH2UW XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtph2uw_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2UW 5-59 PAGE 1883 LINE 104415\n:VCVTPH2UW YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtph2uw_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2UW 5-59 PAGE 1883 LINE 104418\n:VCVTPH2UW ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvtph2uw_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTPH2W 5-61 PAGE 1885 LINE 104499\ndefine pcodeop vcvtph2w_avx512fp16 ;\n:VCVTPH2W XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtph2w_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPH2W 5-61 PAGE 1885 LINE 104502\n:VCVTPH2W YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtph2w_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTPH2W 5-61 PAGE 1885 LINE 104505\n:VCVTPH2W ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvtph2w_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n\n# VCVTPS2PHX 5-67 PAGE 1891 LINE 104781\ndefine pcodeop vcvtps2phx_avx512fp16 ;\n:VCVTPS2PHX XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtps2phx_avx512fp16( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTPS2PHX 5-67 PAGE 1891 LINE 104785\n:VCVTPS2PHX XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x1D; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtps2phx_avx512fp16( YmmReg2_m256_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTPS2PHX 5-67 PAGE 1891 LINE 104789\n:VCVTPS2PHX YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x1D; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtps2phx_avx512fp16( ZmmReg2_m512_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTQQ2PH 5-78 PAGE 1902 LINE 105354\ndefine pcodeop vcvtqq2ph_avx512fp16 ;\n:VCVTQQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtqq2ph_avx512fp16( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,32]);\n}\n\n# VCVTQQ2PH 5-78 PAGE 1902 LINE 105358\n:VCVTQQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtqq2ph_avx512fp16( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTQQ2PH 5-78 PAGE 1902 LINE 105362\n:VCVTQQ2PH XmmReg1^XmmOpMask16, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtqq2ph_avx512fp16( ZmmReg2_m512_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTSD2SH 5-82 PAGE 1906 LINE 105553\ndefine pcodeop vcvtsd2sh_avx512fp16 ;\n:VCVTSD2SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tXmmResult = vcvtsd2sh_avx512fp16( evexV5_XmmReg, XmmReg2_m64 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTSH2SD 5-85 PAGE 1909 LINE 105683\ndefine pcodeop vcvtsh2sd_avx512fp16 ;\n:VCVTSH2SD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vcvtsh2sd_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,64], XmmOpMask[0,1], XmmResult[0,64], XmmMask[0,64]);\n\tXmmResult[64,64] = XmmReg1[16,64]; # DEST[127:64] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTSH2SI 5-86 PAGE 1910 LINE 105738\ndefine pcodeop vcvtsh2si_avx512fp16 ;\n:VCVTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m16\n{\n\tReg32 = vcvtsh2si_avx512fp16( XmmReg2_m16 );\n}\n\n# VCVTSH2SI 5-86 PAGE 1910 LINE 105740\n@ifdef IA64\n:VCVTSH2SI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m16\n{\n\tReg64 = vcvtsh2si_avx512fp16( XmmReg2_m16 );\n}\n@endif\n\n# VCVTSH2SS 5-87 PAGE 1911 LINE 105796\ndefine pcodeop vcvtsh2ss_avx512fp16 ;\n:VCVTSH2SS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vcvtsh2ss_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);\n\tXmmResult[32,96] = XmmReg1[32,96]; # DEST[127:32] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTSH2USI 5-88 PAGE 1912 LINE 105851\ndefine pcodeop vcvtsh2usi_avx512fp16 ;\n:VCVTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x79; Reg32 ... & XmmReg2_m16\n{\n\tReg32 = vcvtsh2usi_avx512fp16( XmmReg2_m16 );\n}\n\n# VCVTSH2USI 5-88 PAGE 1912 LINE 105853\n@ifdef IA64\n:VCVTSH2USI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x79; Reg64 ... & XmmReg2_m16\n{\n\tReg64 = vcvtsh2usi_avx512fp16( XmmReg2_m16 );\n}\n@endif\n\n# VCVTSI2SH 5-89 PAGE 1913 LINE 105910\ndefine pcodeop vcvtsi2sh_avx512fp16 ;\n:VCVTSI2SH XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32\n{\n\tlocal tmp:16 = vcvtsi2sh_avx512fp16( evexV5_XmmReg, rm32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VCVTSI2SH 5-89 PAGE 1913 LINE 105914\n@ifdef IA64\n:VCVTSI2SH XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64\n{\n\tlocal tmp:16 = vcvtsi2sh_avx512fp16( evexV5_XmmReg, rm64 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# VCVTSS2SH 5-91 PAGE 1915 LINE 105984\ndefine pcodeop vcvtss2sh_avx512fp16 ;\n:VCVTSS2SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tXmmResult = vcvtss2sh_avx512fp16( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2DQ 5-100 PAGE 1924 LINE 106453\ndefine pcodeop vcvttph2dq_avx512fp16 ;\n:VCVTTPH2DQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tXmmResult = vcvttph2dq_avx512fp16( XmmReg2_m64_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2DQ 5-100 PAGE 1924 LINE 106457\n:VCVTTPH2DQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x5B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tYmmResult = vcvttph2dq_avx512fp16( XmmReg2_m128_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPH2DQ 5-100 PAGE 1924 LINE 106461\n:VCVTTPH2DQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x5B; ZmmReg1 ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tZmmResult = vcvttph2dq_avx512fp16( YmmReg2_m256_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPH2QQ 5-102 PAGE 1926 LINE 106537\ndefine pcodeop vcvttph2qq_avx512fp16 ;\n:VCVTTPH2QQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst\n{\n\tXmmResult = vcvttph2qq_avx512fp16( XmmReg2_m32_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2QQ 5-102 PAGE 1926 LINE 106541\n:VCVTTPH2QQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x7A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n{\n\tYmmResult = vcvttph2qq_avx512fp16( XmmReg2_m64_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPH2QQ 5-102 PAGE 1926 LINE 106545\n:VCVTTPH2QQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x7A; ZmmReg1 ... & XmmReg2_m128_m16bcst\n{\n\tZmmResult = vcvttph2qq_avx512fp16( XmmReg2_m128_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPH2UDQ 5-104 PAGE 1928 LINE 106622\ndefine pcodeop vcvttph2udq_avx512fp16 ;\n:VCVTTPH2UDQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tXmmResult = vcvttph2udq_avx512fp16( XmmReg2_m64_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2UDQ 5-104 PAGE 1928 LINE 106626\n:VCVTTPH2UDQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tYmmResult = vcvttph2udq_avx512fp16( XmmReg2_m128_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPH2UDQ 5-104 PAGE 1928 LINE 106630\n:VCVTTPH2UDQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x78; ZmmReg1 ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)\n{\n\tZmmResult = vcvttph2udq_avx512fp16( YmmReg2_m256_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPH2UQQ 5-106 PAGE 1930 LINE 106706\ndefine pcodeop vcvttph2uqq_avx512fp16 ;\n:VCVTTPH2UQQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst\n{\n\tXmmResult = vcvttph2uqq_avx512fp16( XmmReg2_m32_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2UQQ 5-106 PAGE 1930 LINE 106710\n:VCVTTPH2UQQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst\n{\n\tYmmResult = vcvttph2uqq_avx512fp16( XmmReg2_m64_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPH2UQQ 5-106 PAGE 1930 LINE 106714\n:VCVTTPH2UQQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x78; ZmmReg1 ... & XmmReg2_m128_m16bcst\n{\n\tZmmResult = vcvttph2uqq_avx512fp16( XmmReg2_m128_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPH2UW 5-108 PAGE 1932 LINE 106790\ndefine pcodeop vcvttph2uw_avx512fp16 ;\n:VCVTTPH2UW XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvttph2uw_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2UW 5-108 PAGE 1932 LINE 106794\n:VCVTTPH2UW YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvttph2uw_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPH2UW 5-108 PAGE 1932 LINE 106798\n:VCVTTPH2UW ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7C; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvttph2uw_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTPH2W 5-110 PAGE 1934 LINE 106874\ndefine pcodeop vcvttph2w_avx512fp16 ;\n:VCVTTPH2W XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvttph2w_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTTPH2W 5-110 PAGE 1934 LINE 106878\n:VCVTTPH2W YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvttph2w_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTTPH2W 5-110 PAGE 1934 LINE 106882\n:VCVTTPH2W ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7C; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvttph2w_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTTSH2SI 5-119 PAGE 1943 LINE 107355\ndefine pcodeop vcvttsh2si_avx512fp16 ;\n:VCVTTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m16\n{\n\tReg32 = vcvttsh2si_avx512fp16( XmmReg2_m16 );\n}\n\n# VCVTTSH2SI 5-119 PAGE 1943 LINE 107358\n@ifdef IA64\n:VCVTTSH2SI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m16\n{\n\tReg64 = vcvttsh2si_avx512fp16( XmmReg2_m16 );\n}\n@endif\n\n# VCVTTSH2USI 5-120 PAGE 1944 LINE 107409\ndefine pcodeop vcvttsh2usi_avx512fp16 ;\n:VCVTTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x78; Reg32 ... & XmmReg2_m16\n{\n\tReg32 = vcvttsh2usi_avx512fp16( XmmReg2_m16 );\n}\n\n# VCVTTSH2USI 5-120 PAGE 1944 LINE 107412\n@ifdef IA64\n:VCVTTSH2USI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x78; Reg64 ... & XmmReg2_m16\n{\n\tReg64 = vcvttsh2usi_avx512fp16( XmmReg2_m16 );\n}\n@endif\n\n# VCVTUDQ2PH 5-124 PAGE 1948 LINE 107633\ndefine pcodeop vcvtudq2ph_avx512fp16 ;\n:VCVTUDQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtudq2ph_avx512fp16( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTUDQ2PH 5-124 PAGE 1948 LINE 107637\n:VCVTUDQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtudq2ph_avx512fp16( YmmReg2_m256_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUDQ2PH 5-124 PAGE 1948 LINE 107641\n:VCVTUDQ2PH YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7A; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtudq2ph_avx512fp16( ZmmReg2_m512_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTUQQ2PH 5-130 PAGE 1954 LINE 107951\ndefine pcodeop vcvtuqq2ph_avx512fp16 ;\n:VCVTUQQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtuqq2ph_avx512fp16( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,32]);\n}\n\n# VCVTUQQ2PH 5-130 PAGE 1954 LINE 107955\n:VCVTUQQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtuqq2ph_avx512fp16( YmmReg2_m256_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult[0,64]);\n}\n\n# VCVTUQQ2PH 5-130 PAGE 1954 LINE 107959\n:VCVTUQQ2PH XmmReg1^XmmOpMask16, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtuqq2ph_avx512fp16( ZmmReg2_m512_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUSI2SH 5-132 PAGE 1956 LINE 108039\ndefine pcodeop vcvtusi2sh_avx512fp16 ;\n:VCVTUSI2SH XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm32\n{\n\tlocal tmp:16 = vcvtusi2sh_avx512fp16( evexV5_XmmReg, rm32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VCVTUSI2SH 5-132 PAGE 1956 LINE 108043\n@ifdef IA64\n:VCVTUSI2SH XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm64\n{\n\tlocal tmp:16 = vcvtusi2sh_avx512fp16( evexV5_XmmReg, rm64 );\n\tZmmReg1 = zext(tmp);\n}\n@endif\n\n# VCVTUW2PH 5-140 PAGE 1964 LINE 108377\ndefine pcodeop vcvtuw2ph_avx512fp16 ;\n:VCVTUW2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtuw2ph_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTUW2PH 5-140 PAGE 1964 LINE 108380\n:VCVTUW2PH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtuw2ph_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTUW2PH 5-140 PAGE 1964 LINE 108383\n:VCVTUW2PH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvtuw2ph_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VCVTW2PH 5-142 PAGE 1966 LINE 108464\ndefine pcodeop vcvtw2ph_avx512fp16 ;\n:VCVTW2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vcvtw2ph_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VCVTW2PH 5-142 PAGE 1966 LINE 108467\n:VCVTW2PH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vcvtw2ph_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VCVTW2PH 5-142 PAGE 1966 LINE 108470\n:VCVTW2PH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vcvtw2ph_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VDIVPH 5-147 PAGE 1971 LINE 108747\ndefine pcodeop vdivph_avx512fp16 ;\n:VDIVPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vdivph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VDIVPH 5-147 PAGE 1971 LINE 108750\n:VDIVPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vdivph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VDIVPH 5-147 PAGE 1971 LINE 108753\n:VDIVPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5E; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vdivph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VDIVSH 5-149 PAGE 1973 LINE 108842\ndefine pcodeop vdivsh_avx512fp16 ;\n:VDIVSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vdivsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = evexV5_XmmReg[16,112]; #DEST[127:16] := SRC1[127:16]\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VDPBF16PS 5-150 PAGE 1974 LINE 108901\ndefine pcodeop vdpbf16ps_avx512vl ;\n:VDPBF16PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vdpbf16ps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VDPBF16PS 5-150 PAGE 1974 LINE 108905\n:VDPBF16PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x52; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vdpbf16ps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VDPBF16PS 5-150 PAGE 1974 LINE 108909\ndefine pcodeop vdpbf16ps_avx512f ;\n:VDPBF16PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x52; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vdpbf16ps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109930\ndefine pcodeop vfcmaddcph_avx512fp16 ;\n:VFCMADDCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfcmaddcph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109934\n:VFCMADDCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfcmaddcph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109938\n:VFCMADDCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfcmaddcph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109942\ndefine pcodeop vfmaddcph_avx512fp16 ;\n:VFMADDCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmaddcph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109946\n:VFMADDCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmaddcph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109950\n:VFMADDCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmaddcph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFCMADDCSH/VFMADDCSH 5-173 PAGE 1997 LINE 110095\ndefine pcodeop vfcmaddcsh_avx512fp16 ;\n:VFCMADDCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tXmmResult = vfcmaddcsh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);\n\tXmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMADDCSH/VFMADDCSH 5-173 PAGE 1997 LINE 110100\ndefine pcodeop vfmaddcsh_avx512fp16 ;\n:VFMADDCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tXmmResult = vfmaddcsh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);\n\tXmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110198\ndefine pcodeop vfcmulcph_avx512fp16 ;\n:VFCMULCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0xD6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfcmulcph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110202\n:VFCMULCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0xD6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfcmulcph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110206\n:VFCMULCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0xD6; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfcmulcph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110210\ndefine pcodeop vfmulcph_avx512fp16 ;\n:VFMULCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0xD6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmulcph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110213\n:VFMULCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0xD6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmulcph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110216\n:VFMULCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0xD6; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmulcph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFCMULCSH/VFMULCSH 5-178 PAGE 2002 LINE 110374\ndefine pcodeop vfcmulcsh_avx512fp16 ;\n:VFCMULCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xD7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tXmmResult = vfcmulcsh_avx512fp16( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);\n\tXmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFCMULCSH/VFMULCSH 5-178 PAGE 2002 LINE 110379\ndefine pcodeop vfmulcsh_avx512fp16 ;\n:VFMULCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xD7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tXmmResult = vfmulcsh_avx512fp16( evexV5_XmmReg, XmmReg2_m32 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);\n\tXmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111596\ndefine pcodeop vfmadd132ph_avx512fp16 ;\n:VFMADD132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmadd132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111599\n:VFMADD132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmadd132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111602\n:VFMADD132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x98; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmadd132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111605\ndefine pcodeop vfmadd213ph_avx512fp16 ;\n:VFMADD213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmadd213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111608\n:VFMADD213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmadd213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111611\n:VFMADD213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xA8; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmadd213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111614\ndefine pcodeop vfmadd231ph_avx512fp16 ;\n:VFMADD231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmadd231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111617\n:VFMADD231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmadd231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111620\n:VFMADD231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xB8; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmadd231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111623\ndefine pcodeop vfnmadd132ph_avx512fp16 ;\n:VFNMADD132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfnmadd132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111627\n:VFNMADD132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfnmadd132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111631\n:VFNMADD132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x9C; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfnmadd132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111635\ndefine pcodeop vfnmadd213ph_avx512fp16 ;\n:VFNMADD213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfnmadd213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111639\n:VFNMADD213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfnmadd213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111655\n:VFNMADD213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xAC; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfnmadd213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111659\ndefine pcodeop vfnmadd231ph_avx512fp16 ;\n:VFNMADD231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfnmadd231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111663\n:VFNMADD231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfnmadd231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111667\n:VFNMADD231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xBC; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfnmadd231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112545\ndefine pcodeop vfmadd132sh_avx512fp16 ;\n:VFMADD132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfmadd132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112548\ndefine pcodeop vfmadd213sh_avx512fp16 ;\n:VFMADD213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfmadd213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112551\ndefine pcodeop vfmadd231sh_avx512fp16 ;\n:VFMADD231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfmadd231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112554\ndefine pcodeop vfnmadd132sh_avx512fp16 ;\n:VFNMADD132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfnmadd132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112557\ndefine pcodeop vfnmadd213sh_avx512fp16 ;\n:VFNMADD213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfnmadd213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112560\ndefine pcodeop vfnmadd231sh_avx512fp16 ;\n:VFNMADD231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfnmadd231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113276\ndefine pcodeop vfmaddsub132ph_avx512fp16 ;\n:VFMADDSUB132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmaddsub132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113280\n:VFMADDSUB132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmaddsub132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113284\n:VFMADDSUB132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x96; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmaddsub132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113288\ndefine pcodeop vfmaddsub213ph_avx512fp16 ;\n:VFMADDSUB213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmaddsub213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113292\n:VFMADDSUB213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmaddsub213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113296\n:VFMADDSUB213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xA6; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmaddsub213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113300\ndefine pcodeop vfmaddsub231ph_avx512fp16 ;\n:VFMADDSUB231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmaddsub231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113304\n:VFMADDSUB231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmaddsub231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113308\n:VFMADDSUB231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xB6; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmaddsub231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114283\ndefine pcodeop vfmsub132ph_avx512fp16 ;\n:VFMSUB132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmsub132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114286\n:VFMSUB132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmsub132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114289\n:VFMSUB132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x9A; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmsub132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114292\ndefine pcodeop vfmsub213ph_avx512fp16 ;\n:VFMSUB213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmsub213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114295\n:VFMSUB213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmsub213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114298\n:VFMSUB213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xAA; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmsub213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114301\ndefine pcodeop vfmsub231ph_avx512fp16 ;\n:VFMSUB231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmsub231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114304\n:VFMSUB231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmsub231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114307\n:VFMSUB231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xBA; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmsub231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114310\ndefine pcodeop vfnmsub132ph_avx512fp16 ;\n:VFNMSUB132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfnmsub132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114314\n:VFNMSUB132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfnmsub132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114318\n:VFNMSUB132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x9E; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfnmsub132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114322\ndefine pcodeop vfnmsub213ph_avx512fp16 ;\n:VFNMSUB213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfnmsub213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114326\n:VFNMSUB213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfnmsub213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114342\n:VFNMSUB213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xAE; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfnmsub213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114346\ndefine pcodeop vfnmsub231ph_avx512fp16 ;\n:VFNMSUB231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfnmsub231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114350\n:VFNMSUB231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfnmsub231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114354\n:VFNMSUB231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xBE; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfnmsub231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115111\ndefine pcodeop vfmsub132sh_avx512fp16 ;\n:VFMSUB132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfmsub132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115114\ndefine pcodeop vfmsub213sh_avx512fp16 ;\n:VFMSUB213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfmsub213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115117\ndefine pcodeop vfmsub231sh_avx512fp16 ;\n:VFMSUB231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfmsub231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115120\ndefine pcodeop vfnmsub132sh_avx512fp16 ;\n:VFNMSUB132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfnmsub132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115124\ndefine pcodeop vfnmsub213sh_avx512fp16 ;\n:VFNMSUB213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfnmsub213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115128\ndefine pcodeop vfnmsub231sh_avx512fp16 ;\n:VFNMSUB231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vfnmsub231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115851\ndefine pcodeop vfmsubadd132ph_avx512fp16 ;\n:VFMSUBADD132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmsubadd132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115855\n:VFMSUBADD132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmsubadd132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115859\n:VFMSUBADD132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x97; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmsubadd132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115863\ndefine pcodeop vfmsubadd213ph_avx512fp16 ;\n:VFMSUBADD213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmsubadd213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115867\n:VFMSUBADD213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmsubadd213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115871\n:VFMSUBADD213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xA7; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmsubadd213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115875\ndefine pcodeop vfmsubadd231ph_avx512fp16 ;\n:VFMSUBADD231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vfmsubadd231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115879\n:VFMSUBADD231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vfmsubadd231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115883\n:VFMSUBADD231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xB7; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vfmsubadd231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\nClassNeg: \"Negative\" is imm8_6=1 & imm8_7=0 {}\nClassNeg: \"Negative,SNAN\" is imm8_6=1 & imm8_7=1 {}\nClassNeg: \"SNAN\" is imm8_6=0 & imm8_7=1 {}\n\nClassDenorm: \"Denormal\" is imm8_5=1 & imm8_6_7=0 {}\nClassDenorm: \"Denormal,\"^ClassNeg is imm8_5=1 & ClassNeg {}\nClassDenorm: ClassNeg is imm8_5=0 & ClassNeg {}\n\nClassNegI: \"NegINF\" is imm8_4=1 & imm8_5_7=0 {}\nClassNegI: \"NegINF,\"^ClassDenorm is imm8_4=1 & ClassDenorm {}\nClassNegI: ClassDenorm is imm8_4=0 & ClassDenorm {}\n\nClassPosI: \"PosINF\" is imm8_3=1 & imm8_4_7=0 {}\nClassPosI: \"PosINF,\"^ClassNegI is imm8_3=1 & ClassNegI {}\nClassPosI: ClassNegI is imm8_3=0 & ClassNegI {}\n\nClassNegZ: \"NegZero\" is imm8_2=1 & imm8_3_7=0 {}\nClassNegZ: \"NegZero,\"^ClassPosI is imm8_2=1 & ClassPosI {}\nClassNegZ: ClassPosI is imm8_2=0 & ClassPosI {}\n\nClassPosZ: \"PosZero\" is imm8_1=1 & imm8_2_7=0 {}\nClassPosZ: \"PosZero,\"^ClassNegZ is imm8_1=1 & ClassNegZ {}\nClassPosZ: ClassNegZ is imm8_1=0 & ClassNegZ {}\n\nClassQNaN: \"QNAN\" is imm8_0=1 & imm8_1_7=0 {}\nClassQNaN: \"QNAN,\"^ClassPosZ is imm8_0=1 & ClassPosZ {}\nClassQNaN: ClassPosZ is imm8_0=0 & ClassPosZ {}\nClassQNaN: \"\" is imm8=0 {}\n\nClassOp: \"{\"^ClassQNaN^\"}\" is ClassQNaN & imm8 { export *[const]:1 imm8;}\n# VFPCLASSPH 5-332 PAGE 2156 LINE 118786\ndefine pcodeop vfpclassph_avx512fp16 ;\n:VFPCLASSPH KReg_reg^XmmOpMask, XmmReg2_m128_m16bcst, ClassOp is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m16bcst; ClassOp\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tlocal tmp:8 = vfpclassph_avx512fp16( XmmReg2_m128_m16bcst, XmmOpMask, ClassOp );\n\tKReg_reg = tmp;\n}\n\n# VFPCLASSPH 5-332 PAGE 2156 LINE 118792\n:VFPCLASSPH KReg_reg^XmmOpMask, YmmReg2_m256_m16bcst, ClassOp is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m16bcst; ClassOp\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tlocal tmp:8 = vfpclassph_avx512fp16( YmmReg2_m256_m16bcst, XmmOpMask, ClassOp );\n\tKReg_reg = tmp;\n}\n\n# VFPCLASSPH 5-332 PAGE 2156 LINE 118798\n:VFPCLASSPH KReg_reg^XmmOpMask, ZmmReg2_m512_m16bcst, ClassOp is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m16bcst; ClassOp\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tlocal tmp:8 = vfpclassph_avx512fp16( ZmmReg2_m512_m16bcst, XmmOpMask, ClassOp );\n\tKReg_reg = tmp;\n}\n\n# VFPCLASSSH 5-339 PAGE 2163 LINE 119114\ndefine pcodeop vfpclasssh_avx512fp16 ;\n:VFPCLASSSH KReg_reg^XmmOpMask, XmmReg2_m16, ClassOp is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x67; KReg_reg ... & XmmReg2_m16; ClassOp\n{\n\tlocal tmp:8 = vfpclasssh_avx512fp16( XmmReg2_m16, XmmOpMask, ClassOp );\n\tKReg_reg = tmp;\n}\n\n# VGETEXPPH 5-359 PAGE 2183 LINE 120137\ndefine pcodeop vgetexpph_avx512fp16 ;\n:VGETEXPPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vgetexpph_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETEXPPH 5-359 PAGE 2183 LINE 120141\n:VGETEXPPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vgetexpph_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGETEXPPH 5-359 PAGE 2183 LINE 120145\n:VGETEXPPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16; byte=0x42; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vgetexpph_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETEXPSH 5-368 PAGE 2192 LINE 120571\ndefine pcodeop vgetexpsh_avx512fp16 ;\n:VGETEXPSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vgetexpsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETMANTPH 5-376 PAGE 2200 LINE 120939\ndefine pcodeop vgetmantph_avx512fp16 ;\n:VGETMANTPH XmmReg1^XmmOpMask16,XmmReg2_m128_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask16; byte=0x26; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vgetmantph_avx512fp16( XmmReg2_m128_m16bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VGETMANTPH 5-376 PAGE 2200 LINE 120943\n:VGETMANTPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask16; byte=0x26; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vgetmantph_avx512fp16( YmmReg2_m256_m16bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VGETMANTPH 5-376 PAGE 2200 LINE 120947\n:VGETMANTPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask16; byte=0x26; ZmmReg1 ... & ZmmReg2_m512_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vgetmantph_avx512fp16( ZmmReg2_m512_m16bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VGETMANTSH 5-385 PAGE 2209 LINE 121406\ndefine pcodeop vgetmantsh_avx512fp16 ;\n:VGETMANTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16, imm8 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16; imm8\n{\n\tXmmResult = vgetmantsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMAXPH 5-400 PAGE 2224 LINE 122191\ndefine pcodeop vmaxph_avx512fp16 ;\n:VMAXPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vmaxph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMAXPH 5-400 PAGE 2224 LINE 122194\n:VMAXPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vmaxph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VMAXPH 5-400 PAGE 2224 LINE 122197\n:VMAXPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5F; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vmaxph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VMAXSH 5-402 PAGE 2226 LINE 122291\ndefine pcodeop vmaxsh_avx512fp16 ;\n:VMAXSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vmaxsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMINPH 5-404 PAGE 2228 LINE 122372\ndefine pcodeop vminph_avx512fp16 ;\n:VMINPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vminph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMINPH 5-404 PAGE 2228 LINE 122375\n:VMINPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vminph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VMINPH 5-404 PAGE 2228 LINE 122378\n:VMINPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5D; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vminph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VMINSH 5-406 PAGE 2230 LINE 122472\ndefine pcodeop vminsh_avx512fp16 ;\n:VMINSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vminsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMOVSH 5-408 PAGE 2232 LINE 122557\ndefine pcodeop vmovsh_avx512fp16 ;\n:VMOVSH XmmReg1^XmmOpMask, m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & m16\n{\n\tlocal tmp = m16;\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], tmp, XmmMask[0,16]);\n\tXmmResult[16,112] = 0;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMOVSH 5-408 PAGE 2232 LINE 122559\n:VMOVSH m16^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask; byte=0x11; XmmReg1 ... & m16\n{\n\tlocal tmp:2 = XmmReg1(0);\n\tlocal mask = m16;\n\tbuild XmmOpMask;\n\tconditionalAssign(tmp, XmmOpMask[0,1], tmp, mask);\n\tm16 = tmp;\n}\n\n# VMOVSH 5-408 PAGE 2232 LINE 122561\n# WARNING: duplicate opcode EVEX.LLIG.F3.MAP5.W0 10 /r last seen on 5-408 PAGE 2232 LINE 122557 for \"VMOVSH xmm1{k1}{z}, xmm2, xmm3\"\n:VMOVSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)\n{\n\tlocal tmp = XmmReg2(0);\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], tmp, XmmMask[0,16]);\n\tXmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] := SRC1[127:16]\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMOVSH 5-408 PAGE 2232 LINE 122564\n# WARNING: duplicate opcode EVEX.LLIG.F3.MAP5.W0 11 /r last seen on 5-408 PAGE 2232 LINE 122559 for \"VMOVSH xmm1{k1}{z}, xmm2, xmm3\"\n:VMOVSH XmmReg2^XmmOpMask, evexV5_XmmReg, XmmReg1 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))\n{\n\tXmmResult = XmmReg1;\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] := SRC1[127:16]\n\tZmmReg2 = zext(XmmResult);\n}\n\n# VMOVW 5-410 PAGE 2234 LINE 122642\ndefine pcodeop vmovw_avx512fp16 ;\n:VMOVW XmmReg1, rm16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_WIG); byte=0x6E; (XmmReg1 & ZmmReg1) ... & rm16\n{\n\tlocal tmp:2 = rm16 ;\n\tZmmReg1 = zext(tmp);\n}\n\n# VMOVW 5-410 PAGE 2234 LINE 122644\n:VMOVW rm16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_WIG); byte=0x7E; XmmReg1 ... & rm16\n{\n\trm16 = XmmReg1(0);\n}\n\n# VMULPH 5-411 PAGE 2235 LINE 122691\ndefine pcodeop vmulph_avx512fp16 ;\n:VMULPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vmulph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VMULPH 5-411 PAGE 2235 LINE 122694\n:VMULPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vmulph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VMULPH 5-411 PAGE 2235 LINE 122697\n:VMULPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x59; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vmulph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VMULSH 5-413 PAGE 2237 LINE 122785\ndefine pcodeop vmulsh_avx512fp16 ;\n:VMULSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vmulsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] := SRC1[127:16]\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122845\ndefine pcodeop vp2intersectd_avx512vl ;\n:VP2INTERSECTD KReg_reg, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x68; KReg_reg ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vp2intersectd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );\n}\n\n# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122849\n:VP2INTERSECTD KReg_reg, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x68; KReg_reg ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vp2intersectd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );\n}\n\n# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122853\ndefine pcodeop vp2intersectd_avx512f ;\n:VP2INTERSECTD KReg_reg, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x68; KReg_reg ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vp2intersectd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n}\n\n# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122857\ndefine pcodeop vp2intersectq_avx512vl ;\n:VP2INTERSECTQ KReg_reg, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x68; KReg_reg ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vp2intersectq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n}\n\n# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122861\n:VP2INTERSECTQ KReg_reg, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x68; KReg_reg ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vp2intersectq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n}\n\n# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122865\ndefine pcodeop vp2intersectq_avx512f ;\n:VP2INTERSECTQ KReg_reg, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x68; KReg_reg ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tKReg_reg = vp2intersectq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124606\ndefine pcodeop vpcompressb_avx512_vbmi2 ;\n:VPCOMPRESSB m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x63; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tXmmResult = vpcompressb_avx512_vbmi2( XmmReg1, XmmOpMask );\n\tm128 = XmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124608\n# WARNING: duplicate opcode EVEX.128.66.0F38.W0 63 /r last seen on 5-449 PAGE 2273 LINE 124606 for \"VPCOMPRESSB xmm1{k1}{z}, xmm2\"\n:VPCOMPRESSB XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x63; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))\n{\n\tXmmResult = vpcompressb_avx512_vbmi2( XmmReg1, XmmOpMask );\n\tZmmReg2 = zext(XmmResult);\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124610\n:VPCOMPRESSB m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x63; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tYmmResult = vpcompressb_avx512_vbmi2( YmmReg1, YmmOpMask );\n\tm256 = YmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124612\n# WARNING: duplicate opcode EVEX.256.66.0F38.W0 63 /r last seen on 5-449 PAGE 2273 LINE 124610 for \"VPCOMPRESSB ymm1{k1}{z}, ymm2\"\n:VPCOMPRESSB YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x63; YmmReg1 & (mod=0x3 & (YmmReg2 & ZmmReg2))\n{\n\tYmmResult = vpcompressb_avx512_vbmi2( YmmReg1, YmmOpMask );\n\tZmmReg2 = zext(YmmResult);\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124614\n:VPCOMPRESSB m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x63; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tZmmResult = vpcompressb_avx512_vbmi2( ZmmReg1, ZmmOpMask );\n\tm512 = ZmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124616\n# WARNING: duplicate opcode EVEX.512.66.0F38.W0 63 /r last seen on 5-449 PAGE 2273 LINE 124614 for \"VPCOMPRESSB zmm1{k1}{z}, zmm2\"\n:VPCOMPRESSB ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x63; ZmmReg1 & (mod=0x3 & ZmmReg2)\n{\n\tZmmResult = vpcompressb_avx512_vbmi2( ZmmReg1, ZmmOpMask );\n\tZmmReg2 = ZmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124618\ndefine pcodeop vpcompressw_avx512_vbmi2 ;\n:VPCOMPRESSW m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x63; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tXmmResult = vpcompressw_avx512_vbmi2( XmmReg1, XmmOpMask );\n\tm128 = XmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124620\n# WARNING: duplicate opcode EVEX.128.66.0F38.W1 63 /r last seen on 5-449 PAGE 2273 LINE 124618 for \"VPCOMPRESSW xmm1{k1}{z}, xmm2\"\n:VPCOMPRESSW XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x63; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))\n{\n\tXmmResult = vpcompressw_avx512_vbmi2( XmmReg1, XmmOpMask );\n\tZmmReg2 = zext(XmmResult);\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124622\n:VPCOMPRESSW m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x63; YmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tYmmResult = vpcompressw_avx512_vbmi2( YmmReg1, YmmOpMask );\n\tm256 = YmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124624\n# WARNING: duplicate opcode EVEX.256.66.0F38.W1 63 /r last seen on 5-449 PAGE 2273 LINE 124622 for \"VPCOMPRESSW ymm1{k1}{z}, ymm2\"\n:VPCOMPRESSW YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x63; YmmReg1 & (mod=0x3 & (YmmReg2 & ZmmReg2))\n{\n\tYmmResult = vpcompressw_avx512_vbmi2( YmmReg1, YmmOpMask );\n\tZmmReg2 = zext(YmmResult);\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124626\n:VPCOMPRESSW m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x63; ZmmReg1 ... & m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tZmmResult = vpcompressw_avx512_vbmi2( ZmmReg1, ZmmOpMask );\n\tm512 = ZmmResult;\n}\n\n# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124628\n# WARNING: duplicate opcode EVEX.512.66.0F38.W1 63 /r last seen on 5-449 PAGE 2273 LINE 124626 for \"VPCOMPRESSW zmm1{k1}{z}, zmm2\"\n:VPCOMPRESSW ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x63; ZmmReg1 & (mod=0x3 & ZmmReg2)\n{\n\tZmmResult = vpcompressw_avx512_vbmi2( ZmmReg1, ZmmOpMask );\n\tZmmReg2 = ZmmResult;\n}\n\n# VPDPBUSD 5-459 PAGE 2283 LINE 125092\ndefine pcodeop vpdpbusd_avx512_vnni ;\n:VPDPBUSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpdpbusd_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPDPBUSD 5-459 PAGE 2283 LINE 125097\n:VPDPBUSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpdpbusd_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPDPBUSD 5-459 PAGE 2283 LINE 125102\n:VPDPBUSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x50; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpdpbusd_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPDPBUSDS 5-461 PAGE 2285 LINE 125211\ndefine pcodeop vpdpbusds_avx512_vnni ;\n:VPDPBUSDS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpdpbusds_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPDPBUSDS 5-461 PAGE 2285 LINE 125217\n:VPDPBUSDS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpdpbusds_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPDPBUSDS 5-461 PAGE 2285 LINE 125223\n:VPDPBUSDS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpdpbusds_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPDPWSSD 5-463 PAGE 2287 LINE 125329\ndefine pcodeop vpdpwssd_avx512_vnni ;\n:VPDPWSSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpdpwssd_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPDPWSSD 5-463 PAGE 2287 LINE 125334\n:VPDPWSSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x52; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpdpwssd_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPDPWSSD 5-463 PAGE 2287 LINE 125339\n:VPDPWSSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x52; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpdpwssd_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPDPWSSDS 5-465 PAGE 2289 LINE 125436\ndefine pcodeop vpdpwssds_avx512_vnni ;\n:VPDPWSSDS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x53; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpdpwssds_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPDPWSSDS 5-465 PAGE 2289 LINE 125442\n:VPDPWSSDS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x53; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpdpwssds_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPDPWSSDS 5-465 PAGE 2289 LINE 125448\n:VPDPWSSDS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x53; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpdpwssds_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMB 5-471 PAGE 2295 LINE 125727\ndefine pcodeop vpermb_avx512vl ;\n:VPERMB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpermb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMB 5-471 PAGE 2295 LINE 125730\n:VPERMB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpermb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMB 5-471 PAGE 2295 LINE 125733\ndefine pcodeop vpermb_avx512_vbmi ;\n:VPERMB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x8D; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpermb_avx512_vbmi( evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMI2B 5-476 PAGE 2300 LINE 125958\ndefine pcodeop vpermi2b_avx512vl ;\n:VPERMI2B XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpermi2b_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMI2B 5-476 PAGE 2300 LINE 125961\n:VPERMI2B YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpermi2b_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMI2B 5-476 PAGE 2300 LINE 125964\ndefine pcodeop vpermi2b_avx512_vbmi ;\n:VPERMI2B ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x75; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpermi2b_avx512_vbmi( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMT2B 5-503 PAGE 2327 LINE 127434\ndefine pcodeop vpermt2b_avx512vl ;\n:VPERMT2B XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpermt2b_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMT2B 5-503 PAGE 2327 LINE 127437\n:VPERMT2B YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpermt2b_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMT2B 5-503 PAGE 2327 LINE 127440\ndefine pcodeop vpermt2b_avx512_vbmi ;\n:VPERMT2B ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpermt2b_avx512_vbmi( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127524\ndefine pcodeop vpermt2w_avx512vl ;\n:VPERMT2W XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpermt2w_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127527\n:VPERMT2W YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpermt2w_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127530\ndefine pcodeop vpermt2w_avx512bw ;\n:VPERMT2W ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpermt2w_avx512bw( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127533\ndefine pcodeop vpermt2d_avx512vl ;\n:VPERMT2D XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpermt2d_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127536\n:VPERMT2D YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x7E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpermt2d_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127539\ndefine pcodeop vpermt2d_avx512f ;\n:VPERMT2D ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x7E; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpermt2d_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127542\ndefine pcodeop vpermt2q_avx512vl ;\n:VPERMT2Q XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpermt2q_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127545\n:VPERMT2Q YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x7E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpermt2q_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127548\ndefine pcodeop vpermt2q_avx512f ;\n:VPERMT2Q ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x7E; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpermt2q_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127551\ndefine pcodeop vpermt2ps_avx512vl ;\n:VPERMT2PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x7F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpermt2ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127554\n:VPERMT2PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x7F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpermt2ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127557\ndefine pcodeop vpermt2ps_avx512f ;\n:VPERMT2PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpermt2ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127806\ndefine pcodeop vpexpandb_avx512_vbmi2 ;\n:VPEXPANDB XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tXmmResult = vpexpandb_avx512_vbmi2( XmmReg2_m128, XmmOpMask );\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127810\n:VPEXPANDB YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tYmmResult = vpexpandb_avx512_vbmi2( YmmReg2_m256, YmmOpMask );\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127814\n:VPEXPANDB ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x62; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tZmmResult = vpexpandb_avx512_vbmi2( ZmmReg2_m512, ZmmOpMask );\n\tZmmReg1 = ZmmResult;\n}\n\n# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127818\ndefine pcodeop vpexpandw_avx512_vbmi2 ;\n:VPEXPANDW XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tXmmResult = vpexpandw_avx512_vbmi2( XmmReg2_m128, XmmOpMask );\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127822\n:VPEXPANDW YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tYmmResult = vpexpandw_avx512_vbmi2( YmmReg2_m256, YmmOpMask );\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127826\n:VPEXPANDW ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x62; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)\n{\n\tZmmResult = vpexpandw_avx512_vbmi2( ZmmReg2_m512, ZmmOpMask );\n\tZmmReg1 = ZmmResult;\n}\n\n# VPMADD52HUQ 5-534 PAGE 2358 LINE 128946\ndefine pcodeop vpmadd52huq_avx512_ifma ;\n:VPMADD52HUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0xB5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpmadd52huq_avx512_ifma( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPMADD52HUQ 5-534 PAGE 2358 LINE 128950\n:VPMADD52HUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0xB5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpmadd52huq_avx512_ifma( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPMADD52HUQ 5-534 PAGE 2358 LINE 128954\n:VPMADD52HUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0xB5; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpmadd52huq_avx512_ifma( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPMADD52LUQ 5-536 PAGE 2360 LINE 129044\ndefine pcodeop vpmadd52luq_avx512_ifma ;\n:VPMADD52LUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0xB4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpmadd52luq_avx512_ifma( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPMADD52LUQ 5-536 PAGE 2360 LINE 129048\n:VPMADD52LUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0xB4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpmadd52luq_avx512_ifma( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPMADD52LUQ 5-536 PAGE 2360 LINE 129052\n:VPMADD52LUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0xB4; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpmadd52luq_avx512_ifma( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPMULTISHIFTQB 5-571 PAGE 2395 LINE 130845\ndefine pcodeop vpmultishiftqb_avx512_vbmi ;\n:VPMULTISHIFTQB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0x83; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpmultishiftqb_avx512_vbmi( evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPMULTISHIFTQB 5-571 PAGE 2395 LINE 130849\n:VPMULTISHIFTQB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0x83; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpmultishiftqb_avx512_vbmi( evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPMULTISHIFTQB 5-571 PAGE 2395 LINE 130853\n:VPMULTISHIFTQB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x83; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpmultishiftqb_avx512_vbmi( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130938\ndefine pcodeop vpopcntb_avx512_bitalg ;\n:VPOPCNTB XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpopcntb_avx512_bitalg( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask8;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130941\n:VPOPCNTB YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpopcntb_avx512_bitalg( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask8;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130944\n:VPOPCNTB ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8; byte=0x54; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpopcntb_avx512_bitalg( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask8;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130947\ndefine pcodeop vpopcntw_avx512_bitalg ;\n:VPOPCNTW XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpopcntw_avx512_bitalg( XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130950\n:VPOPCNTW YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpopcntw_avx512_bitalg( YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130953\n:VPOPCNTW ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16; byte=0x54; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpopcntw_avx512_bitalg( ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130956\ndefine pcodeop vpopcntd_avx512_vpopcntdq ;\n:VPOPCNTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpopcntd_avx512_vpopcntdq( XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130959\n:VPOPCNTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpopcntd_avx512_vpopcntdq( YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130962\n:VPOPCNTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpopcntd_avx512_vpopcntdq( ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130965\ndefine pcodeop vpopcntq_avx512_vpopcntdq ;\n:VPOPCNTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpopcntq_avx512_vpopcntdq( XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130968\n:VPOPCNTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpopcntq_avx512_vpopcntdq( YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPOPCNT 5-573 PAGE 2397 LINE 130971\n:VPOPCNTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpopcntq_avx512_vpopcntdq( ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131746\ndefine pcodeop vpshldw_avx512_vbmi2 ;\n:VPSHLDW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpshldw_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131749\n:VPSHLDW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpshldw_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131752\n:VPSHLDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x70; ZmmReg1 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpshldw_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131755\ndefine pcodeop vpshldd_avx512_vbmi2 ;\n:VPSHLDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshldd_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131758\n:VPSHLDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshldd_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131761\n:VPSHLDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshldd_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131764\ndefine pcodeop vpshldq_avx512_vbmi2 ;\n:VPSHLDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshldq_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131767\n:VPSHLDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshldq_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHLD 5-588 PAGE 2412 LINE 131770\n:VPSHLDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshldq_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131888\ndefine pcodeop vpshldvw_avx512_vbmi2 ;\n:VPSHLDVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpshldvw_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131891\n:VPSHLDVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpshldvw_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131894\n:VPSHLDVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x70; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpshldvw_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131897\ndefine pcodeop vpshldvd_avx512_vbmi2 ;\n:VPSHLDVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshldvd_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131900\n:VPSHLDVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshldvd_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131903\n:VPSHLDVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshldvd_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131906\ndefine pcodeop vpshldvq_avx512_vbmi2 ;\n:VPSHLDVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshldvq_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131909\n:VPSHLDVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshldvq_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHLDV 5-591 PAGE 2415 LINE 131912\n:VPSHLDVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshldvq_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132044\ndefine pcodeop vpshrdw_avx512_vbmi2 ;\n:VPSHRDW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpshrdw_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132047\n:VPSHRDW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x72; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpshrdw_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132050\n:VPSHRDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x72; ZmmReg1 ... & ZmmReg2_m512; imm8\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpshrdw_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132053\ndefine pcodeop vpshrdd_avx512_vbmi2 ;\n:VPSHRDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshrdd_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132056\n:VPSHRDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshrdd_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132059\n:VPSHRDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshrdd_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132062\ndefine pcodeop vpshrdq_avx512_vbmi2 ;\n:VPSHRDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshrdq_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132065\n:VPSHRDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshrdq_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHRD 5-594 PAGE 2418 LINE 132068\n:VPSHRDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshrdq_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132183\ndefine pcodeop vpshrdvw_avx512_vbmi2 ;\n:VPSHRDVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tXmmResult = vpshrdvw_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132186\n:VPSHRDVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x72; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tYmmResult = vpshrdvw_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132189\n:VPSHRDVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x72; ZmmReg1 ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tZmmResult = vpshrdvw_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132192\ndefine pcodeop vpshrdvd_avx512_vbmi2 ;\n:VPSHRDVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshrdvd_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask32;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132195\n:VPSHRDVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshrdvd_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask32;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132198\n:VPSHRDVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m32bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshrdvd_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask32;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132201\ndefine pcodeop vpshrdvq_avx512_vbmi2 ;\n:VPSHRDVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vpshrdvq_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask64;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132204\n:VPSHRDVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vpshrdvq_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask64;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VPSHRDV 5-597 PAGE 2421 LINE 132207\n:VPSHRDVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m64bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vpshrdvq_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask64;\n\tZmmReg1 = ZmmResult;\n}\n\n# VPSHUFBITQMB 5-600 PAGE 2424 LINE 132322\ndefine pcodeop vpshufbitqmb_avx512_bitalg ;\n:VPSHUFBITQMB KReg_reg^XmmOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x8F; KReg_reg ... & XmmReg2_m128\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:2 = vpshufbitqmb_avx512_bitalg( evexV5_XmmReg, XmmReg2_m128, XmmOpMask );\n\tKReg_reg = zext(tmp);\n}\n\n# VPSHUFBITQMB 5-600 PAGE 2424 LINE 132325\n:VPSHUFBITQMB KReg_reg^YmmOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask & evexV5_YmmReg; byte=0x8F; KReg_reg ... & YmmReg2_m256\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:4 = vpshufbitqmb_avx512_bitalg( evexV5_YmmReg, YmmReg2_m256, YmmOpMask );\n\tKReg_reg = zext(tmp);\n}\n\n# VPSHUFBITQMB 5-600 PAGE 2424 LINE 132328\n:VPSHUFBITQMB KReg_reg^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask & evexV5_ZmmReg; byte=0x8F; KReg_reg ... & ZmmReg2_m512\n[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)\n{\n\tlocal tmp:8 = vpshufbitqmb_avx512_bitalg( evexV5_ZmmReg, ZmmReg2_m512, ZmmOpMask );\n\tKReg_reg = zext(tmp);\n}\n\n\n# VRCPPH 5-646 PAGE 2470 LINE 134707\ndefine pcodeop vrcpph_avx512fp16 ;\n:VRCPPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vrcpph_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRCPPH 5-646 PAGE 2470 LINE 134710\n:VRCPPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vrcpph_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRCPPH 5-646 PAGE 2470 LINE 134713\n:VRCPPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16; byte=0x4C; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vrcpph_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRCPSH 5-648 PAGE 2472 LINE 134789\ndefine pcodeop vrcpsh_avx512fp16 ;\n:VRCPSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vrcpsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n\n# VREDUCEPH 5-652 PAGE 2476 LINE 134998\ndefine pcodeop vreduceph_avx512fp16 ;\n:VREDUCEPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask16; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vreduceph_avx512fp16( XmmReg2_m128_m16bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VREDUCEPH 5-652 PAGE 2476 LINE 135003\n:VREDUCEPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask16; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vreduceph_avx512fp16( YmmReg2_m256_m16bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VREDUCEPH 5-652 PAGE 2476 LINE 135008\n:VREDUCEPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask16; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vreduceph_avx512fp16( ZmmReg2_m512_m16bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VREDUCESH 5-659 PAGE 2483 LINE 135336\ndefine pcodeop vreducesh_avx512fp16 ;\n:VREDUCESH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16, imm8 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16; imm8\n{\n\tXmmResult = vreducesh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRNDSCALEPH 5-666 PAGE 2490 LINE 135677\ndefine pcodeop vrndscaleph_avx512fp16 ;\n:VRNDSCALEPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask16; byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vrndscaleph_avx512fp16( XmmReg2_m128_m16bcst, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRNDSCALEPH 5-666 PAGE 2490 LINE 135681\n:VRNDSCALEPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask16; byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vrndscaleph_avx512fp16( YmmReg2_m256_m16bcst, imm8:1 );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRNDSCALEPH 5-666 PAGE 2490 LINE 135685\n:VRNDSCALEPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask16; byte=0x08; ZmmReg1 ... & ZmmReg2_m512_m16bcst; imm8\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vrndscaleph_avx512fp16( ZmmReg2_m512_m16bcst, imm8:1 );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRNDSCALESH 5-674 PAGE 2498 LINE 136097\ndefine pcodeop vrndscalesh_avx512fp16 ;\n:VRNDSCALESH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16, imm8 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16; imm8\n{\n\tXmmResult = vrndscalesh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, imm8:1 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRTPH 5-686 PAGE 2510 LINE 136692\ndefine pcodeop vrsqrtph_avx512fp16 ;\n:VRSQRTPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16; byte=0x4E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vrsqrtph_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VRSQRTPH 5-686 PAGE 2510 LINE 136696\n:VRSQRTPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16; byte=0x4E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vrsqrtph_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VRSQRTPH 5-686 PAGE 2510 LINE 136700\n:VRSQRTPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16; byte=0x4E; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vrsqrtph_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VRSQRTSH 5-688 PAGE 2512 LINE 136781\ndefine pcodeop vrsqrtsh_avx512fp16 ;\n:VRSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vrsqrtsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCALEFPH 5-692 PAGE 2516 LINE 136971\ndefine pcodeop vscalefph_avx512fp16 ;\n:VSCALEFPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vscalefph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSCALEFPH 5-692 PAGE 2516 LINE 136974\n:VSCALEFPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vscalefph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSCALEFPH 5-692 PAGE 2516 LINE 136977\n:VSCALEFPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x2C; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vscalefph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSCALEFSH 5-699 PAGE 2523 LINE 137301\ndefine pcodeop vscalefsh_avx512fp16 ;\n:VSCALEFSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vscalefsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSQRTPH 5-712 PAGE 2536 LINE 137925\ndefine pcodeop vsqrtph_avx512fp16 ;\n:VSQRTPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vsqrtph_avx512fp16( XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSQRTPH 5-712 PAGE 2536 LINE 137928\n:VSQRTPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vsqrtph_avx512fp16( YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSQRTPH 5-712 PAGE 2536 LINE 137931\n:VSQRTPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vsqrtph_avx512fp16( ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSQRTSH 5-714 PAGE 2538 LINE 138003\ndefine pcodeop vsqrtsh_avx512fp16 ;\n:VSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vsqrtsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSUBPH 5-715 PAGE 2539 LINE 138057\ndefine pcodeop vsubph_avx512fp16 ;\n:VSUBPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tXmmResult = vsubph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask16;\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VSUBPH 5-715 PAGE 2539 LINE 138060\n:VSUBPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tYmmResult = vsubph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );\n\tYmmMask = YmmReg1;\n\tbuild YmmOpMask16;\n\tZmmReg1 = zext(YmmResult);\n}\n\n# VSUBPH 5-715 PAGE 2539 LINE 138063\n:VSUBPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5C; ZmmReg1 ... & ZmmReg2_m512_m16bcst\n[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)\n{\n\tZmmResult = vsubph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );\n\tZmmMask = ZmmReg1;\n\tbuild ZmmOpMask16;\n\tZmmReg1 = ZmmResult;\n}\n\n# VSUBSH 5-717 PAGE 2541 LINE 138152\ndefine pcodeop vsubsh_avx512fp16 ;\n:VSUBSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tXmmResult = vsubsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );\n\tXmmMask = XmmReg1;\n\tbuild XmmOpMask;\n\tconditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tXmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged\n\tZmmReg1 = zext(XmmResult);\n}\n\n# VUCOMISH 5-721 PAGE 2545 LINE 138358\ndefine pcodeop vucomish_avx512fp16 ;\n:VUCOMISH XmmReg1, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16\n{\n\tlocal tmp:16 = vucomish_avx512fp16( XmmReg2_m16 );\n\tZmmReg1 = zext(tmp);\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/avx512_manual.sinc", "content": "\n# KADDW/KADDB/KADDQ/KADDD 3-496 PAGE 1066 LINE 55984\n:KADDW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x4A; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = vex1VVV_KReg[0,16] + KReg_rm[0,16];\n\tKReg_reg = zext(tmp);\n}\n\n# KADDW/KADDB/KADDQ/KADDD 3-496 PAGE 1066 LINE 55986\n:KADDB KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x4A; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = vex1VVV_KReg[0,8] + KReg_rm[0,8];\n\tKReg_reg = zext(tmp);\n}\n\n# KADDW/KADDB/KADDQ/KADDD 3-496 PAGE 1066 LINE 55988\n:KADDQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x4A; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = vex1VVV_KReg[0,64] + KReg_rm[0,64];\n\tKReg_reg = zext(tmp);\n}\n\n# KADDW/KADDB/KADDQ/KADDD 3-496 PAGE 1066 LINE 55990\n:KADDD KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x4A; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = vex1VVV_KReg[0,32] + KReg_rm[0,32];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDW/KANDB/KANDQ/KANDD 3-497 PAGE 1067 LINE 56039\n:KANDW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x41; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = vex1VVV_KReg[0,16] & KReg_rm[0,16];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDW/KANDB/KANDQ/KANDD 3-497 PAGE 1067 LINE 56041\n:KANDB KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x41; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = vex1VVV_KReg[0,8] & KReg_rm[0,8];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDW/KANDB/KANDQ/KANDD 3-497 PAGE 1067 LINE 56043\n:KANDQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x41; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = vex1VVV_KReg[0,64] & KReg_rm[0,64];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDW/KANDB/KANDQ/KANDD 3-497 PAGE 1067 LINE 56045\n:KANDD KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x41; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = vex1VVV_KReg[0,32] & KReg_rm[0,32];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDNW/KANDNB/KANDNQ/KANDND 3-498 PAGE 1068 LINE 56100\n:KANDNW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x42; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = ~vex1VVV_KReg[0,16] & KReg_rm[0,16];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDNW/KANDNB/KANDNQ/KANDND 3-498 PAGE 1068 LINE 56102\n:KANDNB KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x42; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = ~vex1VVV_KReg[0,8] & KReg_rm[0,8];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDNW/KANDNB/KANDNQ/KANDND 3-498 PAGE 1068 LINE 56104\n:KANDNQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x42; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = ~vex1VVV_KReg[0,64] & KReg_rm[0,64];\n\tKReg_reg = zext(tmp);\n}\n\n# KANDNW/KANDNB/KANDNQ/KANDND 3-498 PAGE 1068 LINE 56106\n:KANDND KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x42; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = ~vex1VVV_KReg[0,32] & KReg_rm[0,32];\n\tKReg_reg = zext(tmp);\n}\n\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56160\n:KMOVW KReg_reg, RegK_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x90; KReg_reg ... & RegK_m16\n{\n\tKReg_reg = zext(RegK_m16);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56162\n:KMOVB KReg_reg, RegK_m8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x90; KReg_reg ... & RegK_m8\n{\n\tKReg_reg = zext(RegK_m8);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56164\n:KMOVQ KReg_reg, RegK_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1); byte=0x90; KReg_reg ... & RegK_m64\n{\n\tKReg_reg = zext(RegK_m64);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56166\n:KMOVD KReg_reg, RegK_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x90; KReg_reg ... & RegK_m32\n{\n\tKReg_reg = zext(RegK_m32);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56168\n:KMOVW m16, KReg_reg is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x91; KReg_reg ... & m16\n{\n\tm16 = KReg_reg[0,16];\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56170\n:KMOVB m8, KReg_reg is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x91; KReg_reg ... & m8\n{\n\tm8 = KReg_reg[0,8];\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56172\n:KMOVQ m64, KReg_reg is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1); byte=0x91; KReg_reg ... & m64\n{\n\tm64 = KReg_reg[0,64];\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56174\n:KMOVD m32, KReg_reg is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x91; KReg_reg ... & m32\n{\n\tm32 = KReg_reg[0,32];\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56176\n:KMOVW KReg_reg, Rmr32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x92; mod=3 & Rmr32 &KReg_reg\n{\n\tKReg_reg = zext(Rmr32[0,16]);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56178\n:KMOVB KReg_reg, Rmr32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x92; mod=3 & Rmr32 & KReg_reg\n{\n\tKReg_reg = zext(Rmr32[0,8]);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56180\n@ifdef IA64\n:KMOVQ KReg_reg, Rmr64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x92; mod=3 & Rmr64 & KReg_reg\n{\n\tKReg_reg = zext(Rmr64);\n}\n@endif\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56182\n:KMOVD KReg_reg, Rmr32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x92; mod=3 & Rmr32 & KReg_reg\n{\n\tKReg_reg = zext(Rmr32);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56184\n:KMOVW Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm\n{\n\tReg32 = zext(KReg_rm[0,16]);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56186\n:KMOVB Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm\n{\n\tReg32 = zext(KReg_rm[0,8]);\n}\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56188\n@ifdef IA64\n:KMOVQ Reg64, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x93; Reg64 & KReg_rm\n{\n\tReg64 = KReg_rm[0,64];\n}\n@endif\n\n# KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56190\n:KMOVD Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm\n{\n\tReg32 = KReg_rm[0,32];\n}\n\n# KNOTW/KNOTB/KNOTQ/KNOTD 3-501 PAGE 1071 LINE 56266\n:KNOTW KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x44; KReg_reg & KReg_rm\n{\n\tKReg_reg = zext(~KReg_rm[0,16]);\n}\n\n# KNOTW/KNOTB/KNOTQ/KNOTD 3-501 PAGE 1071 LINE 56268\n:KNOTB KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x44; KReg_reg & KReg_rm\n{\n\tKReg_reg = zext(~KReg_rm[0,8]);\n}\n\n# KNOTW/KNOTB/KNOTQ/KNOTD 3-501 PAGE 1071 LINE 56270\n:KNOTQ KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1); byte=0x44; KReg_reg & KReg_rm\n{\n\tKReg_reg = zext(~KReg_rm[0,64]);\n}\n\n# KNOTW/KNOTB/KNOTQ/KNOTD 3-501 PAGE 1071 LINE 56272\n:KNOTD KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x44; KReg_reg & KReg_rm\n{\n\tKReg_reg = zext(~KReg_rm[0,32]);\n}\n\n# KORW/KORB/KORQ/KORD 3-502 PAGE 1072 LINE 56325\n:KORW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x45; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = vex1VVV_KReg[0,16] | KReg_rm[0,16];\n\tKReg_reg = zext(tmp);\n}\n\n# KORW/KORB/KORQ/KORD 3-502 PAGE 1072 LINE 56327\n:KORB KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x45; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = vex1VVV_KReg[0,8] | KReg_rm[0,8];\n\tKReg_reg = zext(tmp);\n}\n\n# KORW/KORB/KORQ/KORD 3-502 PAGE 1072 LINE 56329\n:KORQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x45; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = vex1VVV_KReg[0,64] | KReg_rm[0,64];\n\tKReg_reg = zext(tmp);\n}\n\n# KORW/KORB/KORQ/KORD 3-502 PAGE 1072 LINE 56331\n:KORD KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x45; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = vex1VVV_KReg[0,32] | KReg_rm[0,32];\n\tKReg_reg = zext(tmp);\n}\n\n# KORTESTW/KORTESTB/KORTESTQ/KORTESTD 3-503 PAGE 1073 LINE 56385\n:KORTESTW KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x98; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = KReg_reg[0,16] | KReg_rm[0,16];\n\tZF = (tmp == 0);\n\tCF = (tmp == 0xffff);\n}\n\n# KORTESTW/KORTESTB/KORTESTQ/KORTESTD 3-503 PAGE 1073 LINE 56387\n:KORTESTB KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x98; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = KReg_reg[0,8] | KReg_rm[0,8];\n\tZF = (tmp == 0);\n\tCF = (tmp == 0xff);\n}\n\n# KORTESTW/KORTESTB/KORTESTQ/KORTESTD 3-503 PAGE 1073 LINE 56389\n:KORTESTQ KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1); byte=0x98; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = KReg_reg[0,64] | KReg_rm[0,64];\n\tZF = (tmp == 0);\n\tCF = (tmp == 0xffffffffffffffff);\n}\n\n# KORTESTW/KORTESTB/KORTESTQ/KORTESTD 3-503 PAGE 1073 LINE 56391\n:KORTESTD KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x98; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = KReg_reg[0,32] | KReg_rm[0,32];\n\tZF = (tmp == 0);\n\tCF = (tmp == 0xffffffff);\n}\n\n# KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD 3-505 PAGE 1075 LINE 56481\n:KSHIFTLW KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x32; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:2 = KReg_rm[0,16] << imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD 3-505 PAGE 1075 LINE 56483\n:KSHIFTLB KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x32; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:1 = KReg_rm[0,8] << imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD 3-505 PAGE 1075 LINE 56485\n:KSHIFTLQ KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x33; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:8 = KReg_rm[0,64] << imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD 3-505 PAGE 1075 LINE 56487\n:KSHIFTLD KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x33; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:4 = KReg_reg[0,32] << imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD 3-507 PAGE 1077 LINE 56562\n:KSHIFTRW KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x30; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:2 = KReg_rm[0,16] >> imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD 3-507 PAGE 1077 LINE 56564\n:KSHIFTRB KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x30; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:1 = KReg_rm[0,8] >> imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD 3-507 PAGE 1077 LINE 56566\n:KSHIFTRQ KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x31; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:8 = KReg_rm[0,64] >> imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD 3-507 PAGE 1077 LINE 56568\n:KSHIFTRD KReg_reg, KReg_rm, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x31; KReg_reg & KReg_rm; imm8\n{\n\tlocal tmp:4 = KReg_rm[0,32] >> imm8:1;\n\tKReg_reg = zext(tmp);\n}\n\n# KTESTW/KTESTB/KTESTQ/KTESTD 3-509 PAGE 1079 LINE 56643\n:KTESTW KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x99; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = KReg_reg[0,16] & KReg_rm[0,16];\n\tZF = (tmp == 0);\n\ttmp = KReg_reg[0,16] & ~KReg_rm[0,16];\n\tCF = (tmp == 0);\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# KTESTW/KTESTB/KTESTQ/KTESTD 3-509 PAGE 1079 LINE 56645\n:KTESTB KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x99; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = KReg_reg[0,8] & KReg_rm[0,8];\n\tZF = (tmp == 0);\n\ttmp = KReg_reg[0,8] & ~KReg_rm[0,8];\n\tCF = (tmp == 0);\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# KTESTW/KTESTB/KTESTQ/KTESTD 3-509 PAGE 1079 LINE 56647\n:KTESTQ KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1); byte=0x99; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = KReg_reg[0,64] & KReg_rm[0,64];\n\tZF = (tmp == 0);\n\ttmp = KReg_reg[0,64] & ~KReg_rm[0,64];\n\tCF = (tmp == 0);\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# KTESTW/KTESTB/KTESTQ/KTESTD 3-509 PAGE 1079 LINE 56649\n:KTESTD KReg_reg, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x99; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = KReg_reg[0,32] & KReg_rm[0,32];\n\tZF = (tmp == 0);\n\ttmp = KReg_reg[0,32] & ~KReg_rm[0,32];\n\tCF = (tmp == 0);\n\tAF = 0;\n\tOF = 0;\n\tPF = 0;\n\tSF = 0;\n}\n\n# KUNPCKBW/KUNPCKWD/KUNPCKDQ 3-511 PAGE 1081 LINE 56747\n:KUNPCKBW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x4B; KReg_reg & KReg_rm\n{\n\tlocal src1:1 = vex1VVV_KReg[0,8];\n\tlocal src2:1 = KReg_rm[0,8];\n\tKReg_reg = 0;\n\tKReg_reg[0,8] = src2;\n\tKReg_reg[8,8] = src1;\n}\n\n# KUNPCKBW/KUNPCKWD/KUNPCKDQ 3-511 PAGE 1081 LINE 56749\n:KUNPCKWD KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x4B; KReg_reg & KReg_rm\n{\n\tlocal src1:2 = vex1VVV_KReg[0,16];\n\tlocal src2:2 = KReg_rm[0,16];\n\tKReg_reg = 0;\n\tKReg_reg[0,16] = src2;\n\tKReg_reg[16,16] = src1;\n}\n\n# KUNPCKBW/KUNPCKWD/KUNPCKDQ 3-511 PAGE 1081 LINE 56751\n:KUNPCKDQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x4B; KReg_reg & KReg_rm\n{\n\tlocal src1:4 = vex1VVV_KReg[0,32];\n\tlocal src2:4 = KReg_rm[0,32];\n\tKReg_reg = 0;\n\tKReg_reg[0,32] = src2;\n\tKReg_reg[32,32] = src1;\n}\n\n# KXNORW/KXNORB/KXNORQ/KXNORD 3-512 PAGE 1082 LINE 56806\n:KXNORW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x46; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = ~(vex1VVV_KReg[0,16] ^ KReg_rm[0,16]);\n\tKReg_reg = zext(tmp);\n}\n\n# KXNORW/KXNORB/KXNORQ/KXNORD 3-512 PAGE 1082 LINE 56808\n:KXNORB KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x46; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = ~(vex1VVV_KReg[0,8] ^ KReg_rm[0,8]);\n\tKReg_reg = zext(tmp);\n}\n\n# KXNORW/KXNORB/KXNORQ/KXNORD 3-512 PAGE 1082 LINE 56810\n:KXNORQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x46; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = ~(vex1VVV_KReg[0,64] ^ KReg_rm[0,64]);\n\tKReg_reg = zext(tmp);\n}\n\n# KXNORW/KXNORB/KXNORQ/KXNORD 3-512 PAGE 1082 LINE 56812\n:KXNORD KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x46; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = ~(vex1VVV_KReg[0,32] ^ KReg_rm[0,32]);\n\tKReg_reg = zext(tmp);\n}\n\n# KXORW/KXORB/KXORQ/KXORD 3-513 PAGE 1083 LINE 56866\n:KXORW KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x47; KReg_reg & KReg_rm\n{\n\tlocal tmp:2 = vex1VVV_KReg[0,16] ^ KReg_rm[0,16];\n\tKReg_reg = zext(tmp);\n}\n\n# KXORW/KXORB/KXORQ/KXORD 3-513 PAGE 1083 LINE 56868\n:KXORB KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vex1VVV_KReg; byte=0x47; KReg_reg & KReg_rm\n{\n\tlocal tmp:1 = vex1VVV_KReg[0,8] ^ KReg_rm[0,8];\n\tKReg_reg = zext(tmp);\n}\n\n# KXORW/KXORB/KXORQ/KXORD 3-513 PAGE 1083 LINE 56870\n:KXORQ KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x47; KReg_reg & KReg_rm\n{\n\tlocal tmp:8 = vex1VVV_KReg[0,64] ^ KReg_rm[0,64];\n\tKReg_reg = zext(tmp);\n}\n\n# KXORW/KXORB/KXORQ/KXORD 3-513 PAGE 1083 LINE 56872\n:KXORD KReg_reg, vex1VVV_KReg, KReg_rm is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vex1VVV_KReg; byte=0x47; KReg_reg & KReg_rm\n{\n\tlocal tmp:4 = vex1VVV_KReg[0,32] ^ KReg_rm[0,32];\n\tKReg_reg = zext(tmp);\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96116\ndefine pcodeop vcvtps2ph_avx512vl ;\n:VCVTPS2PH XmmReg2^XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8\n{\n\tXmmResult = vcvtps2ph_avx512vl( XmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tXmmResult[0,16] = (zext(XmmOpMask[0,1]) * XmmResult[0,16]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,16]);\n\tXmmResult[16,16] = (zext(XmmOpMask[1,1]) * XmmResult[16,16]) + (zext(!XmmOpMask[1,1]) * XmmMask[16,16]);\n\tXmmResult[32,16] = (zext(XmmOpMask[2,1]) * XmmResult[32,16]) + (zext(!XmmOpMask[2,1]) * XmmMask[32,16]);\n\tXmmResult[48,16] = (zext(XmmOpMask[3,1]) * XmmResult[48,16]) + (zext(!XmmOpMask[3,1]) * XmmMask[48,16]);\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VCVTPS2PH m64^XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; XmmReg1 ... & m64; imm8\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vcvtps2ph_avx512vl( XmmReg1, imm8:1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask;\n\tXmmResult[0,16] = (zext(XmmOpMask[0,1]) * XmmResult[0,16]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,16]);\n\tXmmResult[16,16] = (zext(XmmOpMask[1,1]) * XmmResult[16,16]) + (zext(!XmmOpMask[1,1]) * XmmMask[16,16]);\n\tXmmResult[32,16] = (zext(XmmOpMask[2,1]) * XmmResult[32,16]) + (zext(!XmmOpMask[2,1]) * XmmMask[32,16]);\n\tXmmResult[48,16] = (zext(XmmOpMask[3,1]) * XmmResult[48,16]) + (zext(!XmmOpMask[3,1]) * XmmMask[48,16]);\n\tm64 = XmmResult[0,64];\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96119\n:VCVTPS2PH XmmReg2^XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8\n{\n\tXmmResult = vcvtps2ph_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask;\n\tXmmResult[0,16] = (zext(XmmOpMask[0,1]) * XmmResult[0,16]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,16]);\n\tXmmResult[16,16] = (zext(XmmOpMask[1,1]) * XmmResult[16,16]) + (zext(!XmmOpMask[1,1]) * XmmMask[16,16]);\n\tXmmResult[32,16] = (zext(XmmOpMask[2,1]) * XmmResult[32,16]) + (zext(!XmmOpMask[2,1]) * XmmMask[32,16]);\n\tXmmResult[48,16] = (zext(XmmOpMask[3,1]) * XmmResult[48,16]) + (zext(!XmmOpMask[3,1]) * XmmMask[48,16]);\n\tXmmResult[64,16] = (zext(XmmOpMask[4,1]) * XmmResult[64,16]) + (zext(!XmmOpMask[4,1]) * XmmMask[64,16]);\n\tXmmResult[80,16] = (zext(XmmOpMask[5,1]) * XmmResult[80,16]) + (zext(!XmmOpMask[5,1]) * XmmMask[80,16]);\n\tXmmResult[96,16] = (zext(XmmOpMask[6,1]) * XmmResult[96,16]) + (zext(!XmmOpMask[6,1]) * XmmMask[96,16]);\n\tXmmResult[112,16] = (zext(XmmOpMask[7,1]) * XmmResult[112,16]) + (zext(!XmmOpMask[7,1]) * XmmMask[112,16]);\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96119\n:VCVTPS2PH m128^XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; YmmReg1 ... & m128; imm8\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vcvtps2ph_avx512vl( YmmReg1, imm8:1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask;\n\tXmmResult[0,16] = (zext(XmmOpMask[0,1]) * XmmResult[0,16]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,16]);\n\tXmmResult[16,16] = (zext(XmmOpMask[1,1]) * XmmResult[16,16]) + (zext(!XmmOpMask[1,1]) * XmmMask[16,16]);\n\tXmmResult[32,16] = (zext(XmmOpMask[2,1]) * XmmResult[32,16]) + (zext(!XmmOpMask[2,1]) * XmmMask[32,16]);\n\tXmmResult[48,16] = (zext(XmmOpMask[3,1]) * XmmResult[48,16]) + (zext(!XmmOpMask[3,1]) * XmmMask[48,16]);\n\tXmmResult[64,16] = (zext(XmmOpMask[4,1]) * XmmResult[64,16]) + (zext(!XmmOpMask[4,1]) * XmmMask[64,16]);\n\tXmmResult[80,16] = (zext(XmmOpMask[5,1]) * XmmResult[80,16]) + (zext(!XmmOpMask[5,1]) * XmmMask[80,16]);\n\tXmmResult[96,16] = (zext(XmmOpMask[6,1]) * XmmResult[96,16]) + (zext(!XmmOpMask[6,1]) * XmmMask[96,16]);\n\tXmmResult[112,16] = (zext(XmmOpMask[7,1]) * XmmResult[112,16]) + (zext(!XmmOpMask[7,1]) * XmmMask[112,16]);\n\tm128 = XmmResult;\n}\n\n# VCVTPS2PH 5-37 PAGE 1861 LINE 96122\ndefine pcodeop vcvtps2ph_avx512f ;\n:VCVTPS2PH YmmReg2^YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8\n{\n\tYmmResult = vcvtps2ph_avx512f( ZmmReg1, imm8:1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask;\n\tYmmResult[0,16] = (zext(YmmOpMask[0,1]) * YmmResult[0,16]) + (zext(!YmmOpMask[0,1]) * YmmMask[0,16]);\n\tYmmResult[16,16] = (zext(YmmOpMask[1,1]) * YmmResult[16,16]) + (zext(!YmmOpMask[1,1]) * YmmMask[16,16]);\n\tYmmResult[32,16] = (zext(YmmOpMask[2,1]) * YmmResult[32,16]) + (zext(!YmmOpMask[2,1]) * YmmMask[32,16]);\n\tYmmResult[48,16] = (zext(YmmOpMask[3,1]) * YmmResult[48,16]) + (zext(!YmmOpMask[3,1]) * YmmMask[48,16]);\n\tYmmResult[64,16] = (zext(YmmOpMask[4,1]) * YmmResult[64,16]) + (zext(!YmmOpMask[4,1]) * YmmMask[64,16]);\n\tYmmResult[80,16] = (zext(YmmOpMask[5,1]) * YmmResult[80,16]) + (zext(!YmmOpMask[5,1]) * YmmMask[80,16]);\n\tYmmResult[96,16] = (zext(YmmOpMask[6,1]) * YmmResult[96,16]) + (zext(!YmmOpMask[6,1]) * YmmMask[96,16]);\n\tYmmResult[112,16] = (zext(YmmOpMask[7,1]) * YmmResult[112,16]) + (zext(!YmmOpMask[7,1]) * YmmMask[112,16]);\n\tYmmResult[128,16] = (zext(YmmOpMask[8,1]) * YmmResult[128,16]) + (zext(!YmmOpMask[8,1]) * YmmMask[128,16]);\n\tYmmResult[144,16] = (zext(YmmOpMask[9,1]) * YmmResult[144,16]) + (zext(!YmmOpMask[9,1]) * YmmMask[144,16]);\n\tYmmResult[160,16] = (zext(YmmOpMask[10,1]) * YmmResult[160,16]) + (zext(!YmmOpMask[10,1]) * YmmMask[160,16]);\n\tYmmResult[176,16] = (zext(YmmOpMask[11,1]) * YmmResult[176,16]) + (zext(!YmmOpMask[11,1]) * YmmMask[176,16]);\n\tYmmResult[192,16] = (zext(YmmOpMask[12,1]) * YmmResult[192,16]) + (zext(!YmmOpMask[12,1]) * YmmMask[192,16]);\n\tYmmResult[208,16] = (zext(YmmOpMask[13,1]) * YmmResult[208,16]) + (zext(!YmmOpMask[13,1]) * YmmMask[208,16]);\n\tYmmResult[224,16] = (zext(YmmOpMask[14,1]) * YmmResult[224,16]) + (zext(!YmmOpMask[14,1]) * YmmMask[224,16]);\n\tYmmResult[240,16] = (zext(YmmOpMask[15,1]) * YmmResult[240,16]) + (zext(!YmmOpMask[15,1]) * YmmMask[240,16]);\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VCVTPS2PH m256^YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; ZmmReg1 ... & m256; imm8\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vcvtps2ph_avx512f( ZmmReg1, imm8:1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask;\n\tYmmResult[0,16] = (zext(YmmOpMask[0,1]) * YmmResult[0,16]) + (zext(!YmmOpMask[0,1]) * YmmMask[0,16]);\n\tYmmResult[16,16] = (zext(YmmOpMask[1,1]) * YmmResult[16,16]) + (zext(!YmmOpMask[1,1]) * YmmMask[16,16]);\n\tYmmResult[32,16] = (zext(YmmOpMask[2,1]) * YmmResult[32,16]) + (zext(!YmmOpMask[2,1]) * YmmMask[32,16]);\n\tYmmResult[48,16] = (zext(YmmOpMask[3,1]) * YmmResult[48,16]) + (zext(!YmmOpMask[3,1]) * YmmMask[48,16]);\n\tYmmResult[64,16] = (zext(YmmOpMask[4,1]) * YmmResult[64,16]) + (zext(!YmmOpMask[4,1]) * YmmMask[64,16]);\n\tYmmResult[80,16] = (zext(YmmOpMask[5,1]) * YmmResult[80,16]) + (zext(!YmmOpMask[5,1]) * YmmMask[80,16]);\n\tYmmResult[96,16] = (zext(YmmOpMask[6,1]) * YmmResult[96,16]) + (zext(!YmmOpMask[6,1]) * YmmMask[96,16]);\n\tYmmResult[112,16] = (zext(YmmOpMask[7,1]) * YmmResult[112,16]) + (zext(!YmmOpMask[7,1]) * YmmMask[112,16]);\n\tYmmResult[128,16] = (zext(YmmOpMask[8,1]) * YmmResult[128,16]) + (zext(!YmmOpMask[8,1]) * YmmMask[128,16]);\n\tYmmResult[144,16] = (zext(YmmOpMask[9,1]) * YmmResult[144,16]) + (zext(!YmmOpMask[9,1]) * YmmMask[144,16]);\n\tYmmResult[160,16] = (zext(YmmOpMask[10,1]) * YmmResult[160,16]) + (zext(!YmmOpMask[10,1]) * YmmMask[160,16]);\n\tYmmResult[176,16] = (zext(YmmOpMask[11,1]) * YmmResult[176,16]) + (zext(!YmmOpMask[11,1]) * YmmMask[176,16]);\n\tYmmResult[192,16] = (zext(YmmOpMask[12,1]) * YmmResult[192,16]) + (zext(!YmmOpMask[12,1]) * YmmMask[192,16]);\n\tYmmResult[208,16] = (zext(YmmOpMask[13,1]) * YmmResult[208,16]) + (zext(!YmmOpMask[13,1]) * YmmMask[208,16]);\n\tYmmResult[224,16] = (zext(YmmOpMask[14,1]) * YmmResult[224,16]) + (zext(!YmmOpMask[14,1]) * YmmMask[224,16]);\n\tYmmResult[240,16] = (zext(YmmOpMask[15,1]) * YmmResult[240,16]) + (zext(!YmmOpMask[15,1]) * YmmMask[240,16]);\n\tm256 = YmmResult;\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115319\ndefine pcodeop vpmovdb_avx512vl ;\n:VPMOVDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovdb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovdb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask8;\n\tm32 = XmmResult[0,32];\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115322\ndefine pcodeop vpmovsdb_avx512vl ;\n:VPMOVSDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsdb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVSDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovsdb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask8;\n\tm32 = XmmResult[0,32];\n}\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115326\ndefine pcodeop vpmovusdb_avx512vl ;\n:VPMOVUSDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusdb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVUSDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovusdb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask8;\n\tm32 = XmmResult[0,32];\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115330\n:VPMOVDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovdb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; YmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovdb_avx512vl( YmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115333\n:VPMOVSDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsdb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVSDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; YmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovsdb_avx512vl( YmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115337\n:VPMOVUSDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusdb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVUSDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; YmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovusdb_avx512vl( YmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115341\ndefine pcodeop vpmovdb_avx512f ;\n:VPMOVDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovdb_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; ZmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovdb_avx512f( ZmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask8;\n\tm128 = XmmResult;\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115344\ndefine pcodeop vpmovsdb_avx512f ;\n:VPMOVSDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsdb_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVSDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; ZmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovsdb_avx512f( ZmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask8;\n\tm128 = XmmResult;\n}\n\n# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115348\ndefine pcodeop vpmovusdb_avx512f ;\n:VPMOVUSDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusdb_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVUSDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; ZmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovusdb_avx512f( ZmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask8;\n\tm128 = XmmResult;\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115532\ndefine pcodeop vpmovdw_avx512vl ;\n:VPMOVDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovdw_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovdw_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask16;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115535\ndefine pcodeop vpmovsdw_avx512vl ;\n:VPMOVSDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsdw_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVSDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovsdw_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask16;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115539\ndefine pcodeop vpmovusdw_avx512vl ;\n:VPMOVUSDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusdw_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVUSDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovusdw_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask16;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115543\n:VPMOVDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovdw_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovdw_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask16;\n\tm128 = XmmResult;\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115546\n:VPMOVSDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsdw_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVSDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovsdw_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask16;\n\tm128 = XmmResult;\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115550\n:VPMOVUSDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusdw_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVUSDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovusdw_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask16;\n\tm128 = XmmResult;\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115554\ndefine pcodeop vpmovdw_avx512f ;\n:VPMOVDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovdw_avx512f( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask16;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovdw_avx512f( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask16;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115557\ndefine pcodeop vpmovsdw_avx512f ;\n:VPMOVSDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovsdw_avx512f( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask16;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVSDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovsdw_avx512f( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask16;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115561\ndefine pcodeop vpmovusdw_avx512f ;\n:VPMOVUSDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovusdw_avx512f( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask16;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVUSDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovusdw_avx512f( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask16;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114671\ndefine pcodeop vpmovqb_avx512vl ;\n:VPMOVQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,16]);\n}\n\n:VPMOVQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; XmmReg1 ... & m16\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovqb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m16);\n\tbuild XmmOpMask8;\n\tm16 = XmmResult[0,16];\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114674\ndefine pcodeop vpmovsqb_avx512vl ;\n:VPMOVSQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,16]);\n}\n\n:VPMOVSQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; XmmReg1 ... & m16\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovsqb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m16);\n\tbuild XmmOpMask8;\n\tm16 = zext(XmmResult[0,16]);\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114678\ndefine pcodeop vpmovusqb_avx512vl ;\n:VPMOVUSQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,16]);\n}\n\n:VPMOVUSQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; XmmReg1 ... & m16\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovusqb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m16);\n\tbuild XmmOpMask8;\n\tm16 = zext(XmmResult[0,16]);\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114682\n:VPMOVQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; YmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovqb_avx512vl( YmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask8;\n\tm32 = XmmResult[0,32];\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114685\n:VPMOVSQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVSQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; YmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovsqb_avx512vl( YmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask8;\n\tm32 = XmmResult[0,32];\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114689\n:VPMOVUSQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVUSQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; YmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovusqb_avx512vl( YmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask8;\n\tm32 = XmmResult[0,32];\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114693\ndefine pcodeop vpmovqb_avx512f ;\n:VPMOVQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqb_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; ZmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovqb_avx512f( ZmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114696\ndefine pcodeop vpmovsqb_avx512f ;\n:VPMOVSQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqb_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVSQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; ZmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovsqb_avx512f( ZmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114700\ndefine pcodeop vpmovusqb_avx512f ;\n:VPMOVUSQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqb_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVUSQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; ZmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)\n{\n\tXmmResult = vpmovusqb_avx512f( ZmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114887\ndefine pcodeop vpmovqw_avx512vl ;\n:VPMOVQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqw_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovqw_avx512vl( XmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask16;\n\tm32 = zext(XmmResult[0,32]);\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114890\ndefine pcodeop vpmovsqw_avx512vl ;\n:VPMOVSQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqw_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVSQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovsqw_avx512vl( XmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask16;\n\tm32 = zext(XmmResult[0,32]);\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114894\ndefine pcodeop vpmovusqw_avx512vl ;\n:VPMOVUSQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqw_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,32]);\n}\n\n:VPMOVUSQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; XmmReg1 ... & m32\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovusqw_avx512vl( XmmReg1 );\n\tXmmMask = zext(m32);\n\tbuild XmmOpMask16;\n\tm32 = zext(XmmResult[0,32]);\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114898\n:VPMOVQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqw_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; YmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovqw_avx512vl( YmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask16;\n\tm64 = zext(XmmResult[0,64]);\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114901\n:VPMOVSQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqw_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVSQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; YmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovsqw_avx512vl( YmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask16;\n\tm64 = zext(XmmResult[0,64]);\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114905\n:VPMOVUSQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqw_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVUSQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; YmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovusqw_avx512vl( YmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask16;\n\tm64 = zext(XmmResult[0,64]);\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114909\ndefine pcodeop vpmovqw_avx512f ;\n:VPMOVQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqw_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; ZmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovqw_avx512f( ZmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask16;\n\tm128 = XmmResult;\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114912\ndefine pcodeop vpmovsqw_avx512f ;\n:VPMOVSQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqw_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVSQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; ZmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovsqw_avx512f( ZmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask16;\n\tm128 = XmmResult;\n}\n\n# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114916\ndefine pcodeop vpmovusqw_avx512f ;\n:VPMOVUSQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqw_avx512f( ZmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask16;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVUSQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; ZmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)\n{\n\tXmmResult = vpmovusqw_avx512f( ZmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask16;\n\tm128 = XmmResult;\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115104\ndefine pcodeop vpmovqd_avx512vl ;\n:VPMOVQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqd_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVQD m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; XmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovqd_avx512vl( XmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115108\ndefine pcodeop vpmovsqd_avx512vl ;\n:VPMOVSQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqd_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVSQD m64^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovsqd_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask32;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115113\ndefine pcodeop vpmovusqd_avx512vl ;\n:VPMOVUSQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqd_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVUSQD m64^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tm64 = vpmovusqd_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask32;\n\tm64 = XmmResult[0,64];\n}\n\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115118\n:VPMOVQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovqd_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovqd_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115122\n:VPMOVSQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovsqd_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVSQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovsqd_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115127\n:VPMOVUSQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovusqd_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask32;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVUSQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovusqd_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask32;\n\tm128 = XmmResult;\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115131\ndefine pcodeop vpmovqd_avx512f ;\n:VPMOVQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovqd_avx512f( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovqd_avx512f( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115134\ndefine pcodeop vpmovsqd_avx512f ;\n:VPMOVSQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovsqd_avx512f( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVSQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovsqd_avx512f( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115138\ndefine pcodeop vpmovusqd_avx512f ;\n:VPMOVUSQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovusqd_avx512f( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask32;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVUSQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovusqd_avx512f( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask32;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115748\ndefine pcodeop vpmovwb_avx512vl ;\n:VPMOVWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovwb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovwb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115751\ndefine pcodeop vpmovswb_avx512vl ;\n:VPMOVSWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovswb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVSWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovswb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115754\ndefine pcodeop vpmovuswb_avx512vl ;\n:VPMOVUSWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovuswb_avx512vl( XmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult[0,64]);\n}\n\n:VPMOVUSWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; XmmReg1 ... & m64\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovuswb_avx512vl( XmmReg1 );\n\tXmmMask = zext(m64);\n\tbuild XmmOpMask8;\n\tm64 = XmmResult[0,64];\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115757\n:VPMOVWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovwb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult);\n\n}\n\n:VPMOVWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovwb_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask8;\n\tm128 = XmmResult;\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115760\n:VPMOVSWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovswb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVSWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovswb_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask8;\n\tm128 = XmmResult;\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115763\n:VPMOVUSWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2\n{\n\tXmmResult = vpmovuswb_avx512vl( YmmReg1 );\n\tXmmMask = XmmReg2;\n\tbuild XmmOpMask8;\n\tZmmReg2 = zext(XmmResult);\n}\n\n:VPMOVUSWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; YmmReg1 ... & m128\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tXmmResult = vpmovuswb_avx512vl( YmmReg1 );\n\tXmmMask = m128;\n\tbuild XmmOpMask8;\n\tm128 = XmmResult;\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115766\ndefine pcodeop vpmovwb_avx512bw ;\n:VPMOVWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovwb_avx512bw( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask8;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovwb_avx512bw( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask8;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115769\ndefine pcodeop vpmovswb_avx512bw ;\n:VPMOVSWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovswb_avx512bw( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask8;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVSWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovswb_avx512bw( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask8;\n\tm256 = zext(YmmResult);\n}\n\n# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115772\ndefine pcodeop vpmovuswb_avx512bw ;\n:VPMOVUSWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2\n{\n\tYmmResult = vpmovuswb_avx512bw( ZmmReg1 );\n\tYmmMask = YmmReg2;\n\tbuild YmmOpMask8;\n\tZmmReg2 = zext(YmmResult);\n}\n\n:VPMOVUSWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; ZmmReg1 ... & m256\n[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)\n{\n\tYmmResult = vpmovuswb_avx512bw( ZmmReg1 );\n\tYmmMask = m256;\n\tbuild YmmOpMask8;\n\tm256 = zext(YmmResult);\n}" }, { "path": "pypcode/processors/x86/data/languages/avx_manual.sinc", "content": "# MOVAPD 4-45 PAGE 1165 LINE 60844\n:VMOVAPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = XmmReg2_m128;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60846\n:VMOVAPD XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & XmmReg1 & (XmmReg2 & ZmmReg2)\n{\n\tXmmReg2 = XmmReg1;\n\tZmmReg2 = zext(XmmReg2);\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60846\n:VMOVAPD m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; XmmReg1 ... & m128\n{\n\tm128 = XmmReg1;\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60848\n:VMOVAPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tYmmReg1 = YmmReg2_m256;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# MOVAPD 4-45 PAGE 1165 LINE 60850\n:VMOVAPD YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & YmmReg1 & (YmmReg2 & ZmmReg2)\n{\n\tYmmReg2 = YmmReg1;\n\tZmmReg2 = zext(YmmReg2);\n}\n:VMOVAPD m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; YmmReg1 ... & m256\n{\n\tm256 = YmmReg1;\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61039\n:VMOVAPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = XmmReg2_m128;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61041\n:VMOVAPS XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & XmmReg1 & (XmmReg2 & ZmmReg2)\n{\n\tXmmReg2 = XmmReg1;\n\tZmmReg2 = zext(XmmReg2);\n}\n:VMOVAPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; XmmReg1 ... & m128\n{\n\tm128 = XmmReg1;\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61043\n:VMOVAPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tYmmReg1 = YmmReg2_m256;\n\tZmmReg1 = zext(YmmReg2_m256);\n}\n\n# MOVAPS 4-49 PAGE 1169 LINE 61045\n:VMOVAPS YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & YmmReg1 & (YmmReg2 & ZmmReg2)\n{\n\tYmmReg2 = YmmReg1;\n\tZmmReg2 = zext(YmmReg2);\n}\n:VMOVAPS m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; YmmReg1 ... & m256\n{\n\tm256 = YmmReg1;\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61667\n# Note: we do not model the exception generated if VMOVDQA is used with a memory operand which is not 16-bye aligned\n:VMOVDQA XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = XmmReg2_m128;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669\n:VMOVDQA XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; mod=3 & XmmReg1 & (XmmReg2 & ZmmReg2)\n{\n\tZmmReg2 = zext(XmmReg1);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669\n:VMOVDQA m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 ... & m128\n{\n\tm128 = XmmReg1;\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61671\n:VMOVDQA YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tYmmReg1 = YmmReg2_m256;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61673\n:VMOVDQA YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; mod=3 & YmmReg1 & (YmmReg2 & ZmmReg2)\n{\n\tYmmReg2 = YmmReg1;\n\tZmmReg2 = zext(YmmReg2);\n}\n:VMOVDQA m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & m256\n{\n\tm256 = YmmReg1;\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63970\n:VMOVSD XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; XmmReg1 & ZmmReg1 & (mod=0x3 & XmmReg2)\n{\n\tlocal tmpa:8 = XmmReg2[0,64];\n\tlocal tmpb:8 = vexVVVV_XmmReg[64,64];\n\tXmmReg1[0,64] = tmpa;\n\tXmmReg1[64,64] = tmpb;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63972\n:VMOVSD XmmReg1, m64 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1 & ZmmReg1) ... & m64\n{\n\tXmmReg1[0,64] = m64;\n\tXmmReg1[64,64] = 0;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63974\n:VMOVSD XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))\n{\n\tlocal tmpa:8 = XmmReg1[0,64];\n\tlocal tmpb:8 = vexVVVV_XmmReg[64,64];\n\tXmmReg2[0,64] = tmpa;\n\tXmmReg2[64,64] = tmpb;\n\tZmmReg2 = zext(XmmReg2);\n}\n\n# MOVSD 4-111 PAGE 1231 LINE 63976\n:VMOVSD m64, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m64\n{\n\tm64 = XmmReg1[0,64];\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64872\n:VMOVUPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = XmmReg2_m128;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64874\n# break this into two constructors to handle the zext for the register destination case\n:VMOVUPS XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 & (mod = 3 & XmmReg2 & ZmmReg2) \n{\n\tXmmReg2 = XmmReg1;\n\tZmmReg2 = zext(XmmReg2);\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64874\n:VMOVUPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m128\n{\n\tm128 = XmmReg1;\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64876\n:VMOVUPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tYmmReg1 = YmmReg2_m256;\n\tZmmReg1 = zext(YmmReg1);\n}\n\n# MOVUPS 4-130 PAGE 1250 LINE 64878\n# TODO in general, what do we do with the zext of only the register case; needs investigation\n:VMOVUPS YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; mod=3 & YmmReg1 & (YmmReg2 & ZmmReg2)\n{\n\tYmmReg2 = YmmReg1;\n\tZmmReg2 = zext(YmmReg2);\n}\n:VMOVUPS m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 ... & m256\n{\n\tm256 = YmmReg1;\n}\n\n# PCMPEQQ 4-250 PAGE 1370 LINE 71169\n:VPCMPEQQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x29; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1[0,64] = zext(vexVVVV_XmmReg[0,64] == XmmReg2_m128[0,64]) * 0xffffffffffffffff:8;\n\tXmmReg1[64,64] = zext(vexVVVV_XmmReg[64,64] == XmmReg2_m128[64,64]) * 0xffffffffffffffff:8;\n\tZmmReg1 = zext(XmmReg1);\n}\n\n\n# PMOVMSKB 4-338 PAGE 1458 LINE 75651\n:VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest\n{\n\tlocal byte_mask:2 = 0:2;\n\tbyte_mask[0,1] = XmmReg2[7,1];\n\tbyte_mask[1,1] = XmmReg2[15,1];\n\tbyte_mask[2,1] = XmmReg2[23,1];\n\tbyte_mask[3,1] = XmmReg2[31,1];\n\tbyte_mask[4,1] = XmmReg2[39,1];\n\tbyte_mask[5,1] = XmmReg2[47,1];\n\tbyte_mask[6,1] = XmmReg2[55,1];\n\tbyte_mask[7,1] = XmmReg2[63,1];\n\tbyte_mask[8,1] = XmmReg2[71,1];\n\tbyte_mask[9,1] = XmmReg2[79,1];\n\tbyte_mask[10,1] = XmmReg2[87,1];\n\tbyte_mask[11,1] = XmmReg2[95,1];\n\tbyte_mask[12,1] = XmmReg2[103,1];\n\tbyte_mask[13,1] = XmmReg2[111,1];\n\tbyte_mask[14,1] = XmmReg2[119,1];\n\tbyte_mask[15,1] = XmmReg2[127,1];\n\tReg32 = zext(byte_mask);\n\tbuild check_Reg32_dest;\n}\n\n# VZEROALL 5-563 PAGE 2387 LINE 122405\n:VZEROALL is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77\n{\n\tZMM0[0,64] = 0:8; ZMM0[64,64] = 0:8; ZMM0[128,64] = 0:8; ZMM0[192,64] = 0:8; ZMM0[256,64] = 0:8; ZMM0[320,64] = 0:8; ZMM0[384,64] = 0:8; ZMM0[448,64] = 0:8;\n\tZMM1[0,64] = 0:8; ZMM1[64,64] = 0:8; ZMM1[128,64] = 0:8; ZMM1[192,64] = 0:8; ZMM1[256,64] = 0:8; ZMM1[320,64] = 0:8; ZMM1[384,64] = 0:8; ZMM1[448,64] = 0:8;\n\tZMM2[0,64] = 0:8; ZMM2[64,64] = 0:8; ZMM2[128,64] = 0:8; ZMM2[192,64] = 0:8; ZMM2[256,64] = 0:8; ZMM2[320,64] = 0:8; ZMM2[384,64] = 0:8; ZMM2[448,64] = 0:8;\n\tZMM3[0,64] = 0:8; ZMM3[64,64] = 0:8; ZMM3[128,64] = 0:8; ZMM3[192,64] = 0:8; ZMM3[256,64] = 0:8; ZMM3[320,64] = 0:8; ZMM3[384,64] = 0:8; ZMM3[448,64] = 0:8;\n\tZMM4[0,64] = 0:8; ZMM4[64,64] = 0:8; ZMM4[128,64] = 0:8; ZMM4[192,64] = 0:8; ZMM4[256,64] = 0:8; ZMM4[320,64] = 0:8; ZMM4[384,64] = 0:8; ZMM4[448,64] = 0:8;\n\tZMM5[0,64] = 0:8; ZMM5[64,64] = 0:8; ZMM5[128,64] = 0:8; ZMM5[192,64] = 0:8; ZMM5[256,64] = 0:8; ZMM5[320,64] = 0:8; ZMM5[384,64] = 0:8; ZMM5[448,64] = 0:8;\n\tZMM6[0,64] = 0:8; ZMM6[64,64] = 0:8; ZMM6[128,64] = 0:8; ZMM6[192,64] = 0:8; ZMM6[256,64] = 0:8; ZMM6[320,64] = 0:8; ZMM6[384,64] = 0:8; ZMM6[448,64] = 0:8;\n\tZMM7[0,64] = 0:8; ZMM7[64,64] = 0:8; ZMM7[128,64] = 0:8; ZMM7[192,64] = 0:8; ZMM7[256,64] = 0:8; ZMM7[320,64] = 0:8; ZMM7[384,64] = 0:8; ZMM7[448,64] = 0:8;\n}\n\n@ifdef IA64\n:VZEROALL is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77\n{\n\tZMM0[0,64] = 0:8; ZMM0[64,64] = 0:8; ZMM0[128,64] = 0:8; ZMM0[192,64] = 0:8; ZMM0[256,64] = 0:8; ZMM0[320,64] = 0:8; ZMM0[384,64] = 0:8; ZMM0[448,64] = 0:8;\n\tZMM1[0,64] = 0:8; ZMM1[64,64] = 0:8; ZMM1[128,64] = 0:8; ZMM1[192,64] = 0:8; ZMM1[256,64] = 0:8; ZMM1[320,64] = 0:8; ZMM1[384,64] = 0:8; ZMM1[448,64] = 0:8;\n\tZMM2[0,64] = 0:8; ZMM2[64,64] = 0:8; ZMM2[128,64] = 0:8; ZMM2[192,64] = 0:8; ZMM2[256,64] = 0:8; ZMM2[320,64] = 0:8; ZMM2[384,64] = 0:8; ZMM2[448,64] = 0:8;\n\tZMM3[0,64] = 0:8; ZMM3[64,64] = 0:8; ZMM3[128,64] = 0:8; ZMM3[192,64] = 0:8; ZMM3[256,64] = 0:8; ZMM3[320,64] = 0:8; ZMM3[384,64] = 0:8; ZMM3[448,64] = 0:8;\n\tZMM4[0,64] = 0:8; ZMM4[64,64] = 0:8; ZMM4[128,64] = 0:8; ZMM4[192,64] = 0:8; ZMM4[256,64] = 0:8; ZMM4[320,64] = 0:8; ZMM4[384,64] = 0:8; ZMM4[448,64] = 0:8;\n\tZMM5[0,64] = 0:8; ZMM5[64,64] = 0:8; ZMM5[128,64] = 0:8; ZMM5[192,64] = 0:8; ZMM5[256,64] = 0:8; ZMM5[320,64] = 0:8; ZMM5[384,64] = 0:8; ZMM5[448,64] = 0:8;\n\tZMM6[0,64] = 0:8; ZMM6[64,64] = 0:8; ZMM6[128,64] = 0:8; ZMM6[192,64] = 0:8; ZMM6[256,64] = 0:8; ZMM6[320,64] = 0:8; ZMM6[384,64] = 0:8; ZMM6[448,64] = 0:8;\n\tZMM7[0,64] = 0:8; ZMM7[64,64] = 0:8; ZMM7[128,64] = 0:8; ZMM7[192,64] = 0:8; ZMM7[256,64] = 0:8; ZMM7[320,64] = 0:8; ZMM7[384,64] = 0:8; ZMM7[448,64] = 0:8;\n\tZMM8[0,64] = 0:8; ZMM8[64,64] = 0:8; ZMM8[128,64] = 0:8; ZMM8[192,64] = 0:8; ZMM8[256,64] = 0:8; ZMM8[320,64] = 0:8; ZMM8[384,64] = 0:8; ZMM8[448,64] = 0:8;\n\tZMM9[0,64] = 0:8; ZMM9[64,64] = 0:8; ZMM9[128,64] = 0:8; ZMM9[192,64] = 0:8; ZMM9[256,64] = 0:8; ZMM9[320,64] = 0:8; ZMM9[384,64] = 0:8; ZMM9[448,64] = 0:8;\n\tZMM10[0,64] = 0:8; ZMM10[64,64] = 0:8; ZMM10[128,64] = 0:8; ZMM10[192,64] = 0:8; ZMM10[256,64] = 0:8; ZMM10[320,64] = 0:8; ZMM10[384,64] = 0:8; ZMM10[448,64] = 0:8;\n\tZMM11[0,64] = 0:8; ZMM11[64,64] = 0:8; ZMM11[128,64] = 0:8; ZMM11[192,64] = 0:8; ZMM11[256,64] = 0:8; ZMM11[320,64] = 0:8; ZMM11[384,64] = 0:8; ZMM11[448,64] = 0:8;\n\tZMM12[0,64] = 0:8; ZMM12[64,64] = 0:8; ZMM12[128,64] = 0:8; ZMM12[192,64] = 0:8; ZMM12[256,64] = 0:8; ZMM12[320,64] = 0:8; ZMM12[384,64] = 0:8; ZMM12[448,64] = 0:8;\n\tZMM13[0,64] = 0:8; ZMM13[64,64] = 0:8; ZMM13[128,64] = 0:8; ZMM13[192,64] = 0:8; ZMM13[256,64] = 0:8; ZMM13[320,64] = 0:8; ZMM13[384,64] = 0:8; ZMM13[448,64] = 0:8;\n\tZMM14[0,64] = 0:8; ZMM14[64,64] = 0:8; ZMM14[128,64] = 0:8; ZMM14[192,64] = 0:8; ZMM14[256,64] = 0:8; ZMM14[320,64] = 0:8; ZMM14[384,64] = 0:8; ZMM14[448,64] = 0:8;\n\tZMM15[0,64] = 0:8; ZMM15[64,64] = 0:8; ZMM15[128,64] = 0:8; ZMM15[192,64] = 0:8; ZMM15[256,64] = 0:8; ZMM15[320,64] = 0:8; ZMM15[384,64] = 0:8; ZMM15[448,64] = 0:8;\n}\n@endif\n\n# VZEROUPPER 5-565 PAGE 2389 LINE 122480\n:VZEROUPPER is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77\n{\n\tZMM0[128,64] = 0:8; ZMM0[192,64] = 0:8; ZMM0[256,64] = 0:8; ZMM0[320,64] = 0:8; ZMM0[384,64] = 0:8; ZMM0[448,64] = 0:8;\n\tZMM1[128,64] = 0:8; ZMM1[192,64] = 0:8; ZMM1[256,64] = 0:8; ZMM1[320,64] = 0:8; ZMM1[384,64] = 0:8; ZMM1[448,64] = 0:8;\n\tZMM2[128,64] = 0:8; ZMM2[192,64] = 0:8; ZMM2[256,64] = 0:8; ZMM2[320,64] = 0:8; ZMM2[384,64] = 0:8; ZMM2[448,64] = 0:8;\n\tZMM3[128,64] = 0:8; ZMM3[192,64] = 0:8; ZMM3[256,64] = 0:8; ZMM3[320,64] = 0:8; ZMM3[384,64] = 0:8; ZMM3[448,64] = 0:8;\n\tZMM4[128,64] = 0:8; ZMM4[192,64] = 0:8; ZMM4[256,64] = 0:8; ZMM4[320,64] = 0:8; ZMM4[384,64] = 0:8; ZMM4[448,64] = 0:8;\n\tZMM5[128,64] = 0:8; ZMM5[192,64] = 0:8; ZMM5[256,64] = 0:8; ZMM5[320,64] = 0:8; ZMM5[384,64] = 0:8; ZMM5[448,64] = 0:8;\n\tZMM6[128,64] = 0:8; ZMM6[192,64] = 0:8; ZMM6[256,64] = 0:8; ZMM6[320,64] = 0:8; ZMM6[384,64] = 0:8; ZMM6[448,64] = 0:8;\n\tZMM7[128,64] = 0:8; ZMM7[192,64] = 0:8; ZMM7[256,64] = 0:8; ZMM7[320,64] = 0:8; ZMM7[384,64] = 0:8; ZMM7[448,64] = 0:8;\n}\n\n@ifdef IA64\n:VZEROUPPER is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77\n{\n\tZMM0[128,64] = 0:8; ZMM0[192,64] = 0:8; ZMM0[256,64] = 0:8; ZMM0[320,64] = 0:8; ZMM0[384,64] = 0:8; ZMM0[448,64] = 0:8;\n\tZMM1[128,64] = 0:8; ZMM1[192,64] = 0:8; ZMM1[256,64] = 0:8; ZMM1[320,64] = 0:8; ZMM1[384,64] = 0:8; ZMM1[448,64] = 0:8;\n\tZMM2[128,64] = 0:8; ZMM2[192,64] = 0:8; ZMM2[256,64] = 0:8; ZMM2[320,64] = 0:8; ZMM2[384,64] = 0:8; ZMM2[448,64] = 0:8;\n\tZMM3[128,64] = 0:8; ZMM3[192,64] = 0:8; ZMM3[256,64] = 0:8; ZMM3[320,64] = 0:8; ZMM3[384,64] = 0:8; ZMM3[448,64] = 0:8;\n\tZMM4[128,64] = 0:8; ZMM4[192,64] = 0:8; ZMM4[256,64] = 0:8; ZMM4[320,64] = 0:8; ZMM4[384,64] = 0:8; ZMM4[448,64] = 0:8;\n\tZMM5[128,64] = 0:8; ZMM5[192,64] = 0:8; ZMM5[256,64] = 0:8; ZMM5[320,64] = 0:8; ZMM5[384,64] = 0:8; ZMM5[448,64] = 0:8;\n\tZMM6[128,64] = 0:8; ZMM6[192,64] = 0:8; ZMM6[256,64] = 0:8; ZMM6[320,64] = 0:8; ZMM6[384,64] = 0:8; ZMM6[448,64] = 0:8;\n\tZMM7[128,64] = 0:8; ZMM7[192,64] = 0:8; ZMM7[256,64] = 0:8; ZMM7[320,64] = 0:8; ZMM7[384,64] = 0:8; ZMM7[448,64] = 0:8;\n\tZMM8[128,64] = 0:8; ZMM8[192,64] = 0:8; ZMM8[256,64] = 0:8; ZMM8[320,64] = 0:8; ZMM8[384,64] = 0:8; ZMM8[448,64] = 0:8;\n\tZMM9[128,64] = 0:8; ZMM9[192,64] = 0:8; ZMM9[256,64] = 0:8; ZMM9[320,64] = 0:8; ZMM9[384,64] = 0:8; ZMM9[448,64] = 0:8;\n\tZMM10[128,64] = 0:8; ZMM10[192,64] = 0:8; ZMM10[256,64] = 0:8; ZMM10[320,64] = 0:8; ZMM10[384,64] = 0:8; ZMM10[448,64] = 0:8;\n\tZMM11[128,64] = 0:8; ZMM11[192,64] = 0:8; ZMM11[256,64] = 0:8; ZMM11[320,64] = 0:8; ZMM11[384,64] = 0:8; ZMM11[448,64] = 0:8;\n\tZMM12[128,64] = 0:8; ZMM12[192,64] = 0:8; ZMM12[256,64] = 0:8; ZMM12[320,64] = 0:8; ZMM12[384,64] = 0:8; ZMM12[448,64] = 0:8;\n\tZMM13[128,64] = 0:8; ZMM13[192,64] = 0:8; ZMM13[256,64] = 0:8; ZMM13[320,64] = 0:8; ZMM13[384,64] = 0:8; ZMM13[448,64] = 0:8;\n\tZMM14[128,64] = 0:8; ZMM14[192,64] = 0:8; ZMM14[256,64] = 0:8; ZMM14[320,64] = 0:8; ZMM14[384,64] = 0:8; ZMM14[448,64] = 0:8;\n\tZMM15[128,64] = 0:8; ZMM15[192,64] = 0:8; ZMM15[256,64] = 0:8; ZMM15[320,64] = 0:8; ZMM15[384,64] = 0:8; ZMM15[448,64] = 0:8;\n\n}\n@endif\n\n" }, { "path": "pypcode/processors/x86/data/languages/bmi1.sinc", "content": "macro tzcntflags(input, output) {\n ZF = (output == 0);\n CF = (input == 0);\n # OF, SF, PF, AF are undefined\n}\n\n\n####\n#### BMI1 instructions\n####\n\n# TODO remove ANDN from ia.sinc ?????\n:ANDN Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf2; Reg32 ... & check_Reg32_dest ... &rm32\n{\n Reg32 = ~(vexVVVV_r32) & rm32;\n resultflags(Reg32);\n OF = 0;\n CF = 0;\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n# TODO remove ANDN from ia.sinc ?????\n:ANDN Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf2; Reg64 ... & rm64\n{\n Reg64 = ~(vexVVVV_r64) & rm64;\n resultflags(Reg64);\n OF = 0;\n CF = 0;\n}\n@endif\n\n\n:BEXTR Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32\n{\n sourceTmp:1 = vexVVVV_r32[0,8];\n lengthTmp:1 = vexVVVV_r32[8,8];\n\n Reg32 = (rm32 >> sourceTmp) & ((1 << lengthTmp) - 1);\n build check_Reg32_dest;\n\n ZF = (Reg32 == 0);\n OF = 0;\n CF = 0;\n # AF, SF, and PF are undefined\n}\n\n@ifdef IA64\n:BEXTR Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64\n{\n sourceTmp:1 = vexVVVV_r64[0,8];\n lengthTmp:1 = vexVVVV_r64[8,8];\n\n Reg64 = (rm64 >> sourceTmp) & ((1 << lengthTmp) - 1);\n\n ZF = (Reg64 == 0);\n OF = 0;\n CF = 0;\n # AF, SF, and PF are undefined\n}\n@endif\n\n\n:BLSI vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=3 ... & check_vexVVVV_r32_dest ... & rm32\n{\n vexVVVV_r32 = -rm32 & rm32;\n build check_vexVVVV_r32_dest;\n\n ZF = (vexVVVV_r32 == 0);\n SF = (vexVVVV_r32 s< 0);\n CF = (rm32 != 0);\n OF = 0;\n # AF and PF are undefined\n}\n\n@ifdef IA64\n:BLSI vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=3 ... & rm64\n{\n vexVVVV_r64 = -rm64 & rm64;\n\n ZF = (vexVVVV_r64 == 0);\n SF = (vexVVVV_r64 s< 0);\n CF = (rm64 != 0);\n OF = 0;\n # AF and PF are undefined\n}\n@endif\n\n\n:BLSMSK vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=2 ... & check_vexVVVV_r32_dest ... &rm32\n{\n CF = (rm32 == 0);\n vexVVVV_r32 = (rm32 - 1) ^ rm32;\n\n SF = (vexVVVV_r32 s< 0);\n build check_vexVVVV_r32_dest;\n ZF = 0;\n OF = 0;\n # AF and PF are undefined\n}\n\n@ifdef IA64\n:BLSMSK vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=2 ... & rm64\n{\n CF = (rm64 == 0);\n vexVVVV_r64 = (rm64 - 1) ^ rm64;\n\n SF = (vexVVVV_r64 s< 0);\n ZF = 0;\n OF = 0;\n # AF and PF are undefined\n}\n@endif\n\n\n:BLSR vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=1 ... & check_vexVVVV_r32_dest ... &rm32\n{\n CF = (rm32 == 0);\n vexVVVV_r32 = (rm32 - 1) & rm32;\n build check_vexVVVV_r32_dest;\n\n ZF = (vexVVVV_r32 == 0);\n SF = (vexVVVV_r32 s< 0);\n OF = 0;\n # AF and PF are undefined\n}\n\n@ifdef IA64\n:BLSR vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=1 ... & rm64\n{\n CF = (rm64 == 0);\n vexVVVV_r64 = (rm64 - 1) & rm64;\n\n ZF = (vexVVVV_r64 == 0);\n SF = (vexVVVV_r64 s< 0);\n OF = 0;\n # AF and PF are undefined\n}\n@endif\n\n# not as documented in manual; requires PRE_66 prefix to get 16-bit operation\n:TZCNT Reg16, rm16\tis vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBC; Reg16 ... & rm16 {\n\n countTmp:2 = 0;\n inputTmp:2 = rm16;\n\n \n if ((inputTmp & 1) != 0) goto ;\n\n countTmp = countTmp + 1;\n inputTmp = (inputTmp >> 1) | 0x8000;\n goto ;\n\n \n tzcntflags(rm16, countTmp);\n Reg16 = countTmp;\n \n}\n\n:TZCNT Reg32, rm32\tis vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBC; Reg32 ... & check_Reg32_dest ... & rm32 {\n\n countTmp:4 = 0;\n inputTmp:4 = rm32;\n\n \n if ((inputTmp & 1) != 0) goto ;\n\n countTmp = countTmp + 1;\n inputTmp = (inputTmp >> 1) | 0x80000000;\n goto ;\n\n \n tzcntflags(rm32, countTmp);\n Reg32 = countTmp;\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:TZCNT Reg64, rm64\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBC; Reg64 ... & rm64 {\n\n countTmp:8 = 0;\n inputTmp:8 = rm64;\n\n \n if ((inputTmp & 1) != 0) goto ;\n\n countTmp = countTmp + 1;\n inputTmp = (inputTmp >> 1) | 0x8000000000000000;\n goto ;\n\n \n tzcntflags(rm64, countTmp);\n Reg64 = countTmp;\n}\n@endif\n" }, { "path": "pypcode/processors/x86/data/languages/bmi2.sinc", "content": "####\n#### BMI2 instructions\n####\n\n\n:BZHI Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32\n{\n indexTmp:1 = vexVVVV_r32:1;\n\n # saturate index amount to 32; operand size or higher does not clear any bits\n shift:1 = (indexTmp <= 32) * (32 - indexTmp);\n\n # clear the upper bits\n Reg32 = (rm32 << shift) >> shift;\n build check_Reg32_dest;\n\n ZF = (Reg32 == 0);\n SF = (Reg32 s< 0);\n CF = indexTmp > 31;\n OF = 0;\n # AF and PF are undefined\n}\n\n@ifdef IA64\n:BZHI Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64\n{\n indexTmp:1 = vexVVVV_r64:1;\n\n # saturate index amount to 64; operand size or higher does not clear any bits\n shift:1 = (indexTmp <= 64) * (64 - indexTmp);\n\n # clear the upper bits\n Reg64 = (rm64 << shift) >> shift;\n\n ZF = (Reg64 == 0);\n SF = (Reg64 s< 0);\n CF = indexTmp > 63;\n OF = 0;\n # AF and PF are undefined\n}\n@endif\n\n\n:MULX Reg32, vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf6; Reg32 ... & check_Reg32_dest ... & check_vexVVVV_r32_dest ... & rm32\n{\n temp:8 = zext(EDX) * zext(rm32);\n\n vexVVVV_r32 = temp:4;\n build check_vexVVVV_r32_dest;\n Reg32 = temp(4);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:MULX Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf6; Reg64 ... & rm64\n{\n temp:16 = zext(RDX) * zext(rm64);\n\n vexVVVV_r64 = temp:8;\n Reg64 = temp(8);\n}\n@endif\n\n\n:PDEP Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32\n{\n sourceTmp:4 = vexVVVV_r32;\n\n indexTmp:4 = 1;\n resultTmp:4 = 0;\n\n \n maskBit:4 = rm32 & indexTmp;\n\n if (maskBit == 0) goto ;\n resultTmp = resultTmp | (maskBit * (sourceTmp & 1));\n sourceTmp = sourceTmp >> 1;\n\n \n indexTmp = indexTmp << 1;\n if (indexTmp != 0) goto ;\n\n Reg32 = resultTmp;\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:PDEP Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64\n{\n sourceTmp:8 = vexVVVV_r64;\n\n indexTmp:8 = 1;\n resultTmp:8 = 0;\n\n \n maskBit:8 = rm64 & indexTmp;\n\n if (maskBit == 0) goto ;\n resultTmp = resultTmp | (maskBit * (sourceTmp & 1));\n sourceTmp = sourceTmp >> 1;\n\n \n indexTmp = indexTmp << 1;\n if (indexTmp != 0) goto ;\n\n Reg64 = resultTmp;\n}\n@endif\n\n\n:PEXT Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32\n{\n indexTmp:4 = 0x80000000;\n resultTmp:4 = 0;\n\n \n maskBit:4 = rm32 & indexTmp;\n\n if (maskBit == 0) goto ;\n resultTmp = (resultTmp << 1) | zext((maskBit & vexVVVV_r32) != 0);\n\n \n indexTmp = indexTmp >> 1;\n if (indexTmp != 0) goto ;\n\n build check_Reg32_dest;\n Reg32 = resultTmp;\n}\n\n@ifdef IA64\n:PEXT Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64\n{\n indexTmp:8 = 0x8000000000000000;\n resultTmp:8 = 0;\n\n \n maskBit:8 = rm64 & indexTmp;\n\n if (maskBit == 0) goto ;\n resultTmp = (resultTmp << 1) | zext((maskBit & vexVVVV_r64) != 0);\n\n \n indexTmp = indexTmp >> 1;\n if (indexTmp != 0) goto ;\n\n Reg64 = resultTmp;\n}\n@endif\n\n\n:RORX Reg32, rm32, imm8 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F3A) & $(VEX_W0); byte=0xf0; Reg32 ... & check_Reg32_dest ... & rm32; imm8\n{\n shiftTmp:1 = (imm8:1 & 0x1F);\n\n Reg32 = (rm32 >> shiftTmp) | ( rm32 << (32 - shiftTmp));\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:RORX Reg64, rm64, imm8 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F3A) & $(VEX_W1); byte=0xf0; Reg64 ... & rm64; imm8\n{\n shiftTmp:1 = (imm8:1 & 0x3F);\n\n Reg64 = (rm64 >> shiftTmp) | ( rm64 << (64 - shiftTmp));\n}\n@endif\n\n\n:SARX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32\n{\n Reg32 = rm32 s>> (vexVVVV_r32 & 0x0000001F);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:SARX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64\n{\n Reg64 = rm64 s>> (vexVVVV_r64 & 0x000000000000003F);\n}\n@endif\n\n\n:SHLX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32\n{\n Reg32 = rm32 << (vexVVVV_r32 & 0x0000001F);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:SHLX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64\n{\n Reg64 = rm64 << (vexVVVV_r64 & 0x000000000000003F);\n}\n@endif\n\n\n:SHRX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32\n{\n Reg32 = rm32 >> (vexVVVV_r32 & 0x0000001F);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:SHRX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64\n{\n Reg64 = rm64 >> (vexVVVV_r64 & 0x000000000000003F);\n}\n@endif\n\n" }, { "path": "pypcode/processors/x86/data/languages/cet.sinc", "content": "#\n# Instructions based on Intel Control-flow Enforcement Technology Preview\n#\n# Note: Shadow Stack semantics is not currently implemented correctly in these instructions\n# nor in the instructions affected by CET\n#\n\n\ndefine pcodeop ShadowStackPush8B;\ndefine pcodeop ShadowStackPush4B;\n\ndefine pcodeop ShadowStackLoad8B;\ndefine pcodeop ShadowStackLoad4B;\n\n:INCSSPD r32 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=5 & r32 {\n SSP = SSP + zext(4 * r32:1);\n}\n@ifdef IA64\n:INCSSPQ r64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & $(REX_W) & byte=0x0f; byte=0xae; reg_opcode=5 & r64 {\n SSP = SSP + zext(8 * r64:1);\n}\n@endif\n\n:RDSSPD r32 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0x1e; mod=3 & reg_opcode=1 & r32 {\n r32 = SSP:4;\n}\n@ifdef IA64\n:RDSSPQ r64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & $(REX_W) & byte=0x0f; byte=0x1e; mod=3 & reg_opcode=1 & r64 {\n r64 = SSP;\n}\n@endif\n\n:SAVEPREVSSP is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; byte=0xea {\n tmp:8 = SSP;\n SSP = SSP & ~0x7;\n ShadowStackPush8B(tmp);\n}\n \n\n:RSTORSSP m64 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; ( mod != 0b11 & reg_opcode=5 ) ... & m64 {\n tmp_SSP:8 = m64;\n SSP = tmp_SSP & ~0x01;\n}\n\ndefine pcodeop writeToShadowStack;\ndefine pcodeop writeToUserShadowStack;\n\n\n:WRSSD rm32,Reg32 is vexMode=0 & byte=0x0f; byte=0x38; byte=0xf6; rm32 & Reg32 ... { \n writeToShadowStack(rm32, Reg32);\n}\n@ifdef IA64\n:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... { \n writeToShadowStack(rm64, Reg64);\n}\n@endif\n\n:WRUSSD rm32,Reg32 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0xf5; rm32 & Reg32 ... { \n writeToUserShadowStack(rm32, Reg32);\n}\n@ifdef IA64\n:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... { \n writeToUserShadowStack(rm64, Reg64);\n}\n@endif\n\ndefine pcodeop markShadowStackBusy;\ndefine pcodeop clearShadowStackBusy;\n\n:SETSSBSY is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; byte=0xe8 {\n SSP = markShadowStackBusy(IA32_PL0_SSP);\n}\n\n:CLRSSBSY m64 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0xae; reg_opcode=6 ... & m64 {\n clearShadowStackBusy(m64);\n SSP=0;\n}\n\n:ENDBR32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; byte=0xfb {}\n@ifdef IA64\n:ENDBR64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; byte=0xfa {}\n@endif\n\n\n" }, { "path": "pypcode/processors/x86/data/languages/clwb.sinc", "content": "define pcodeop clwb;\n:CLWB m8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=6 ... {\n\tclwb(m8);\n}\n\n@ifdef IA64\ndefine pcodeop clflushopt;\n:CLFLUSHOPT m8 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=7 ... {\n\tclflushopt(m8);\n}\n@endif\n\n# Note: PCOMMIT was deprecated prior to it ever being implemented in production processors.\n# I never found the encoding for it. Therefore, no constructor.\n" }, { "path": "pypcode/processors/x86/data/languages/fma.sinc", "content": "#\n# x86 FMA instructions\n#\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101211\ndefine pcodeop vfmadd132pd_fma ;\n:VFMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101214\ndefine pcodeop vfmadd213pd_fma ;\n:VFMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101217\ndefine pcodeop vfmadd231pd_fma ;\n:VFMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101220\n:VFMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101223\n:VFMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101226\n:VFMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101572\ndefine pcodeop vfmadd132ps_fma ;\n:VFMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101575\ndefine pcodeop vfmadd213ps_fma ;\n:VFMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101578\ndefine pcodeop vfmadd231ps_fma ;\n:VFMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101581\n:VFMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101584\n:VFMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101587\n# WARNING: did not recognize VEX field 0 for \"VFMADD231PS ymm1, ymm2, ymm3/m256\"\n:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101931\ndefine pcodeop vfmadd132sd_fma ;\n:VFMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101934\ndefine pcodeop vfmadd213sd_fma ;\n:VFMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101937\ndefine pcodeop vfmadd231sd_fma ;\n:VFMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102099\ndefine pcodeop vfmadd132ss_fma ;\n:VFMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102102\ndefine pcodeop vfmadd213ss_fma ;\n:VFMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102105\ndefine pcodeop vfmadd231ss_fma ;\n:VFMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102272\ndefine pcodeop vfmaddsub132pd_fma ;\n:VFMADDSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmaddsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102275\ndefine pcodeop vfmaddsub213pd_fma ;\n:VFMADDSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmaddsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102278\ndefine pcodeop vfmaddsub231pd_fma ;\n:VFMADDSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmaddsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102281\n:VFMADDSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmaddsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102284\n:VFMADDSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmaddsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102287\n:VFMADDSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmaddsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102711\ndefine pcodeop vfmaddsub132ps_fma ;\n:VFMADDSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmaddsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102714\ndefine pcodeop vfmaddsub213ps_fma ;\n:VFMADDSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmaddsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102717\ndefine pcodeop vfmaddsub231ps_fma ;\n:VFMADDSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmaddsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102720\n:VFMADDSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmaddsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102723\n:VFMADDSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmaddsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102726\n:VFMADDSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmaddsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103141\ndefine pcodeop vfmsubadd132pd_fma ;\n:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsubadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103144\ndefine pcodeop vfmsubadd213pd_fma ;\n:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsubadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103147\ndefine pcodeop vfmsubadd231pd_fma ;\n:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsubadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103150\n:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsubadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103153\n:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsubadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103156\n:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsubadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103581\ndefine pcodeop vfmsubadd132ps_fma ;\n:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsubadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103584\ndefine pcodeop vfmsubadd213ps_fma ;\n:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsubadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103587\ndefine pcodeop vfmsubadd231ps_fma ;\n:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsubadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103590\n:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsubadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103593\n:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsubadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103596\n:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsubadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104019\ndefine pcodeop vfmsub132pd_fma ;\n:VFMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104022\ndefine pcodeop vfmsub213pd_fma ;\n:VFMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104025\ndefine pcodeop vfmsub231pd_fma ;\n:VFMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104028\n:VFMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104031\n:VFMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104034\n:VFMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104379\ndefine pcodeop vfmsub132ps_fma ;\n:VFMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104382\ndefine pcodeop vfmsub213ps_fma ;\n:VFMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104385\ndefine pcodeop vfmsub231ps_fma ;\n:VFMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104388\n:VFMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104391\n:VFMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104394\n# WARNING: did not recognize VEX field 0 for \"VFMSUB231PS ymm1, ymm2, ymm3/m256\"\n:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104738\ndefine pcodeop vfmsub132sd_fma ;\n:VFMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104741\ndefine pcodeop vfmsub213sd_fma ;\n:VFMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104744\ndefine pcodeop vfmsub231sd_fma ;\n:VFMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104913\ndefine pcodeop vfmsub132ss_fma ;\n:VFMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104916\ndefine pcodeop vfmsub213ss_fma ;\n:VFMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104919\ndefine pcodeop vfmsub231ss_fma ;\n:VFMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105088\ndefine pcodeop vfnmadd132pd_fma ;\n:VFNMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105091\ndefine pcodeop vfnmadd213pd_fma ;\n:VFNMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105094\ndefine pcodeop vfnmadd231pd_fma ;\n:VFNMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105097\n:VFNMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105100\n:VFNMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105103\n:VFNMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105447\ndefine pcodeop vfnmadd132ps_fma ;\n:VFNMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105450\ndefine pcodeop vfnmadd213ps_fma ;\n:VFNMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105453\ndefine pcodeop vfnmadd231ps_fma ;\n:VFNMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105456\n:VFNMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105459\n:VFNMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105462\n# WARNING: did not recognize VEX field 0 for \"VFNMADD231PS ymm1, ymm2, ymm3/m256\"\n:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105794\ndefine pcodeop vfnmadd132sd_fma ;\n:VFNMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfnmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105797\ndefine pcodeop vfnmadd213sd_fma ;\n:VFNMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfnmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105800\ndefine pcodeop vfnmadd231sd_fma ;\n:VFNMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfnmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105966\ndefine pcodeop vfnmadd132ss_fma ;\n:VFNMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfnmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105969\ndefine pcodeop vfnmadd213ss_fma ;\n:VFNMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfnmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105972\ndefine pcodeop vfnmadd231ss_fma ;\n:VFNMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfnmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106138\ndefine pcodeop vfnmsub132pd_fma ;\n:VFNMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106141\ndefine pcodeop vfnmsub213pd_fma ;\n:VFNMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106144\ndefine pcodeop vfnmsub231pd_fma ;\n:VFNMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106147\n:VFNMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106150\n:VFNMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106153\n:VFNMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106487\ndefine pcodeop vfnmsub132ps_fma ;\n:VFNMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106490\ndefine pcodeop vfnmsub213ps_fma ;\n:VFNMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106493\ndefine pcodeop vfnmsub231ps_fma ;\n:VFNMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128\n{\n\tlocal tmp:16 = vfnmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106496\n:VFNMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106499\n:VFNMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106502\n# WARNING: did not recognize VEX field 0 for \"VFNMSUB231PS ymm1, ymm2, ymm3/m256\"\n:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256\n{\n\tlocal tmp:16 = vfnmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106832\ndefine pcodeop vfnmsub132sd_fma ;\n:VFNMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfnmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106835\ndefine pcodeop vfnmsub213sd_fma ;\n:VFNMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfnmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106838\ndefine pcodeop vfnmsub231sd_fma ;\n:VFNMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64\n{\n\tlocal tmp:16 = vfnmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107004\ndefine pcodeop vfnmsub132ss_fma ;\n:VFNMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfnmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107007\ndefine pcodeop vfnmsub213ss_fma ;\n:VFNMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfnmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107010\ndefine pcodeop vfnmsub231ss_fma ;\n:VFNMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32\n{\n\tlocal tmp:16 = vfnmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );\n\tZmmReg1 = zext(tmp);\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/ia.sinc", "content": "# SLA specification file for Intel x86\n\n@ifdef IA64\n@define SIZE \"8\"\n@define STACKPTR \"RSP\"\n@else\n@define SIZE \"4\"\n@define STACKPTR \"ESP\"\n@endif\n\ndefine endian=little;\n\ndefine space ram type=ram_space size=$(SIZE) default;\ndefine space register type=register_space size=4;\n\n# General purpose registers\n\n@ifdef IA64\ndefine register offset=0 size=8 [ RAX RCX RDX RBX RSP RBP RSI RDI ];\ndefine register offset=0 size=4 [ EAX _ ECX _ EDX _ EBX _ ESP _ EBP _ ESI _ EDI ];\ndefine register offset=0 size=2 [ AX _ _ _ CX _ _ _ DX _ _ _ BX _ _ _ SP _ _ _ BP _ _ _ SI _ _ _ DI ];\ndefine register offset=0 size=1 [ AL AH _ _ _ _ _ _ CL CH _ _ _ _ _ _ DL DH _ _ _ _ _ _ BL BH _ _ _ _ _ _ SPL _ _ _ _ _ _ _ BPL _ _ _ _ _ _ _ SIL _ _ _ _ _ _ _ DIL ];\n\ndefine register offset=0x80 size=8 [ R8 R9 R10 R11 R12 R13 R14 R15 ];\ndefine register offset=0x80 size=4 [ R8D _ R9D _ R10D _ R11D _ R12D _ R13D _ R14D _ R15D _ ];\ndefine register offset=0x80 size=2 [ R8W _ _ _ R9W _ _ _ R10W _ _ _ R11W _ _ _ R12W _ _ _ R13W _ _ _ R14W _ _ _ R15W _ _ _ ];\ndefine register offset=0x80 size=1 [ R8B _ _ _ _ _ _ _ R9B _ _ _ _ _ _ _ R10B _ _ _ _ _ _ _ R11B _ _ _ _ _ _ _ R12B _ _ _ _ _ _ _ R13B _ _ _ _ _ _ _ R14B _ _ _ _ _ _ _ R15B _ _ _ _ _ _ _ ];\n@else\ndefine register offset=0 size=4 [ EAX ECX EDX EBX ESP EBP ESI EDI ];\ndefine register offset=0 size=2 [ AX _ CX _ DX _ BX _ SP _ BP _ SI _ DI ];\ndefine register offset=0 size=1 [ AL AH _ _ CL CH _ _ DL DH _ _ BL BH ];\n@endif\n\n# Segment registers\ndefine register offset=0x100 size=2 [ ES CS SS DS FS GS ];\ndefine register offset=0x110 size=$(SIZE) [ FS_OFFSET GS_OFFSET ];\n\n# Flags\ndefine register offset=0x200 size=1 [ CF F1 PF F3 AF F5 ZF SF\n TF IF DF OF IOPL NT F15\n RF VM AC VIF VIP ID ];\n@ifdef IA64\ndefine register offset=0x280 size=8 [ rflags RIP ];\ndefine register offset=0x280 size=4 [ eflags _ EIP _ ];\ndefine register offset=0x280 size=2 [ flags _ _ _ IP _ _ _];\n@else\ndefine register offset=0x280 size=4 [ eflags EIP] ;\ndefine register offset=0x280 size=2 [ flags _ IP] ;\n@endif\n\n# Debug and control registers\n\n@ifdef IA64\ndefine register offset=0x300 size=8 [ DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7\n DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15\n CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7\n CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 ];\n@else\ndefine register offset=0x300 size=4 [ DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7\n CR0 _ CR2 CR3 CR4 ];\ndefine register offset=0x400 size=4 [ TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 ];\n@endif\n\n#Processor State Register - currently only XFEATURE_ENABLED_MASK=XCR0 is defined\n#\ndefine register offset=0x600 size=8 [ XCR0 ];\n\n# Memory Protection Extensions (MPX)\ndefine register offset=0x700 size=8 [ BNDCFGS BNDCFGU BNDSTATUS ];\n\ndefine register offset=0x740 size=16 [ BND0 BND1 BND2 BND3 _ _ _ _ ];\ndefine register offset=0x740 size=8 [ BND0_LB BND0_UB BND1_LB BND1_UB BND2_LB BND2_UB BND3_LB BND3_UB _ _ _ _ _ _ _ _ ];\n\n# Control Flow Extensions\ndefine register offset=0x7c0 size=8 [ SSP IA32_PL2_SSP IA32_PL1_SSP IA32_PL0_SSP ];\n\n# NOTE: ST registers moved with Ghidra 10.0.3 (v2.12) and previously occupied the offset range 0x1000-104f.\n# Automated address re-mapping was not provided and requires use of FixOldSTVariableStorageScript\n#\t\tto fixup uses within a program. The range 0x1000-104f should remain reserved and unused.\n# define register offset=0x1000 size=80 [ OLD_ST_REGION ]; \n\ndefine register offset=0x1090 size=1 [ C0 C1 C2 C3 ];\ndefine register offset=0x1094 size=4 [ MXCSR ];\ndefine register offset=0x10a0 size=2 [ FPUControlWord FPUStatusWord FPUTagWord\n FPULastInstructionOpcode ];\ndefine register offset=0x10a8 size=$(SIZE) [ FPUDataPointer FPUInstructionPointer ];\ndefine register offset=0x10c8 size=2 [ FPUPointerSelector FPUDataSelector]; #FCS FDS\n# FCS is not modeled, deprecated as 0.\n# FDS is not modeled, deprecated as 0.\n \n# Floating point registers - as they are in 32-bit protected mode\n# See overlapping MM registers below\ndefine register offset=0x1100 size=10 [ ST0 ];\ndefine register offset=0x1110 size=10 [ ST1 ];\ndefine register offset=0x1120 size=10 [ ST2 ];\ndefine register offset=0x1130 size=10 [ ST3 ];\ndefine register offset=0x1140 size=10 [ ST4 ];\ndefine register offset=0x1150 size=10 [ ST5 ];\ndefine register offset=0x1160 size=10 [ ST6 ];\ndefine register offset=0x1170 size=10 [ ST7 ];\n\n# NOTE: The upper 16-bits of the x87 ST registers go unused in MMX.\n# These upper 16-bits should be set to all ones by any MMX instruction, which correspond to the \n# floating-point representation of NaNs or infinities. \n# Although not currently modeled, the 2-byte ST0h..ST7h registers are provided for that purpose.\n \ndefine register offset=0x1100 size=8 [ MM0 _ MM1 _ MM2 _ MM3 _ MM4 _ MM5 _ MM6 _ MM7 _ ];\ndefine register offset=0x1100 size=4 [\n MM0_Da MM0_Db _ _\n MM1_Da MM1_Db _ _\n MM2_Da MM2_Db _ _\n MM3_Da MM3_Db _ _\n MM4_Da MM4_Db _ _\n MM5_Da MM5_Db _ _\n MM6_Da MM6_Db _ _\n MM7_Da MM7_Db _ _\n];\ndefine register offset=0x1100 size=2 [\n MM0_Wa MM0_Wb MM0_Wc MM0_Wd ST0h _ _ _\n MM1_Wa MM1_Wb MM1_Wc MM1_Wd ST1h _ _ _\n MM2_Wa MM2_Wb MM2_Wc MM2_Wd ST2h _ _ _\n MM3_Wa MM3_Wb MM3_Wc MM3_Wd ST3h _ _ _\n MM4_Wa MM4_Wb MM4_Wc MM4_Wd ST4h _ _ _\n MM5_Wa MM5_Wb MM5_Wc MM5_Wd ST5h _ _ _\n MM6_Wa MM6_Wb MM6_Wc MM6_Wd ST6h _ _ _\n MM7_Wa MM7_Wb MM7_Wc MM7_Wd ST7h _ _ _\n];\ndefine register offset=0x1100 size=1 [ \n MM0_Ba MM0_Bb MM0_Bc MM0_Bd MM0_Be MM0_Bf MM0_Bg MM0_Bh _ _ _ _ _ _ _ _ \n MM1_Ba MM1_Bb MM1_Bc MM1_Bd MM1_Be MM1_Bf MM1_Bg MM1_Bh _ _ _ _ _ _ _ _ \n MM2_Ba MM2_Bb MM2_Bc MM2_Bd MM2_Be MM2_Bf MM2_Bg MM2_Bh _ _ _ _ _ _ _ _ \n MM3_Ba MM3_Bb MM3_Bc MM3_Bd MM3_Be MM3_Bf MM3_Bg MM3_Bh _ _ _ _ _ _ _ _ \n MM4_Ba MM4_Bb MM4_Bc MM4_Bd MM4_Be MM4_Bf MM4_Bg MM4_Bh _ _ _ _ _ _ _ _ \n MM5_Ba MM5_Bb MM5_Bc MM5_Bd MM5_Be MM5_Bf MM5_Bg MM5_Bh _ _ _ _ _ _ _ _ \n MM6_Ba MM6_Bb MM6_Bc MM6_Bd MM6_Be MM6_Bf MM6_Bg MM6_Bh _ _ _ _ _ _ _ _ \n MM7_Ba MM7_Bb MM7_Bc MM7_Bd MM7_Be MM7_Bf MM7_Bg MM7_Bh _ _ _ _ _ _ _ _\n];\n\n\ndefine register offset=0x1180 size=16 [ xmmTmp1 xmmTmp2 ];\ndefine register offset=0x1180 size=8 [\n xmmTmp1_Qa xmmTmp1_Qb\n xmmTmp2_Qa xmmTmp2_Qb\n];\ndefine register offset=0x1180 size=4 [\n xmmTmp1_Da xmmTmp1_Db xmmTmp1_Dc xmmTmp1_Dd\n xmmTmp2_Da xmmTmp2_Db xmmTmp2_Dc xmmTmp2_Dd\n];\n\n#\n# YMM0 - YMM7 - available in 32 bit mode\n# YMM0 - YMM15 - available in 64 bit mode\n# \n\n# YMMx_H is the formal name for the high double quadword of the YMMx register, XMMx is the overlay in the XMM register set\ndefine register offset=0x1200 size=16 [\n\tXMM0 YMM0_H\t_\t_\n\tXMM1 YMM1_H\t_\t_\n\tXMM2 YMM2_H\t_\t_\n\tXMM3 YMM3_H\t_\t_\n\tXMM4 YMM4_H\t_\t_\n\tXMM5 YMM5_H\t_\t_\n\tXMM6 YMM6_H\t_\t_\n\tXMM7 YMM7_H\t_\t_\n\tXMM8 YMM8_H\t_\t_\n\tXMM9 YMM9_H\t_\t_\n\tXMM10 YMM10_H\t_\t_\n\tXMM11 YMM11_H\t_\t_\n\tXMM12 YMM12_H\t_\t_\n\tXMM13 YMM13_H\t_\t_\n\tXMM14 YMM14_H\t_\t_\n\tXMM15 YMM15_H\t_\t_\n\tXMM16 YMM16_H\t_\t_\n\tXMM17 YMM17_H\t_\t_\n\tXMM18 YMM18_H\t_\t_\n\tXMM19 YMM19_H\t_\t_\n\tXMM20 YMM20_H\t_\t_\n\tXMM21 YMM21_H\t_\t_\n\tXMM22 YMM22_H\t_\t_\n\tXMM23 YMM23_H\t_\t_\n\tXMM24 YMM24_H\t_\t_\n\tXMM25 YMM25_H\t_\t_\n\tXMM26 YMM26_H\t_\t_\n\tXMM27 YMM27_H\t_\t_\n\tXMM28 YMM28_H\t_\t_\n\tXMM29 YMM29_H\t_\t_\n\tXMM30 YMM30_H\t_\t_\n\tXMM31 YMM31_H\t_\t_\n\t\n];\n\ndefine register offset=0x1200 size=8 [\n\tXMM0_Qa XMM0_Qb _ _ _ _ _ _\n\tXMM1_Qa XMM1_Qb _ _ _ _ _ _\n\tXMM2_Qa XMM2_Qb _ _ _ _ _ _\n\tXMM3_Qa XMM3_Qb _ _ _ _ _ _\n\tXMM4_Qa XMM4_Qb _ _ _ _ _ _\n\tXMM5_Qa XMM5_Qb _ _ _ _ _ _\n\tXMM6_Qa XMM6_Qb _ _ _ _ _ _\n\tXMM7_Qa XMM7_Qb _ _ _ _ _ _\n\tXMM8_Qa XMM8_Qb _ _ _ _ _ _\n\tXMM9_Qa XMM9_Qb _ _ _ _ _ _\n\tXMM10_Qa XMM10_Qb _ _ _ _ _ _\n\tXMM11_Qa XMM11_Qb _ _ _ _ _ _\n\tXMM12_Qa XMM12_Qb _ _ _ _ _ _\n\tXMM13_Qa XMM13_Qb _ _ _ _ _ _\n\tXMM14_Qa XMM14_Qb _ _ _ _ _ _\n\tXMM15_Qa XMM15_Qb _ _ _ _ _ _\n\tXMM16_Qa XMM16_Qb _ _ _ _ _ _\n\tXMM17_Qa XMM17_Qb _ _ _ _ _ _\n\tXMM18_Qa XMM18_Qb _ _ _ _ _ _\n\tXMM19_Qa XMM19_Qb _ _ _ _ _ _\n\tXMM20_Qa XMM20_Qb _ _ _ _ _ _\n\tXMM21_Qa XMM21_Qb _ _ _ _ _ _\n\tXMM22_Qa XMM22_Qb _ _ _ _ _ _\n\tXMM23_Qa XMM23_Qb _ _ _ _ _ _\n\tXMM24_Qa XMM24_Qb _ _ _ _ _ _\n\tXMM25_Qa XMM25_Qb _ _ _ _ _ _\n\tXMM26_Qa XMM26_Qb _ _ _ _ _ _\n\tXMM27_Qa XMM27_Qb _ _ _ _ _ _\n\tXMM28_Qa XMM28_Qb _ _ _ _ _ _\n\tXMM29_Qa XMM29_Qb _ _ _ _ _ _\n\tXMM30_Qa XMM30_Qb _ _ _ _ _ _\n\tXMM31_Qa XMM31_Qb _ _ _ _ _ _\n];\ndefine register offset=0x1200 size=4 [\n\tXMM0_Da XMM0_Db XMM0_Dc XMM0_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM1_Da XMM1_Db XMM1_Dc XMM1_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM2_Da XMM2_Db XMM2_Dc XMM2_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM3_Da XMM3_Db XMM3_Dc XMM3_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM4_Da XMM4_Db XMM4_Dc XMM4_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM5_Da XMM5_Db XMM5_Dc XMM5_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM6_Da XMM6_Db XMM6_Dc XMM6_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM7_Da XMM7_Db XMM7_Dc XMM7_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM8_Da XMM8_Db XMM8_Dc XMM8_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM9_Da XMM9_Db XMM9_Dc XMM9_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM10_Da XMM10_Db XMM10_Dc XMM10_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM11_Da XMM11_Db XMM11_Dc XMM11_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM12_Da XMM12_Db XMM12_Dc XMM12_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM13_Da XMM13_Db XMM13_Dc XMM13_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM14_Da XMM14_Db XMM14_Dc XMM14_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM15_Da XMM15_Db XMM15_Dc XMM15_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM16_Da XMM16_Db XMM16_Dc XMM16_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM17_Da XMM17_Db XMM17_Dc XMM17_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM18_Da XMM18_Db XMM18_Dc XMM18_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM19_Da XMM19_Db XMM19_Dc XMM19_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM20_Da XMM20_Db XMM20_Dc XMM20_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM21_Da XMM21_Db XMM21_Dc XMM21_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM22_Da XMM22_Db XMM22_Dc XMM22_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM23_Da XMM23_Db XMM23_Dc XMM23_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM24_Da XMM24_Db XMM24_Dc XMM24_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM25_Da XMM25_Db XMM25_Dc XMM25_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM26_Da XMM26_Db XMM26_Dc XMM26_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM27_Da XMM27_Db XMM27_Dc XMM27_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM28_Da XMM28_Db XMM28_Dc XMM28_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM29_Da XMM29_Db XMM29_Dc XMM29_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM30_Da XMM30_Db XMM30_Dc XMM30_Dd _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM31_Da XMM31_Db XMM31_Dc XMM31_Dd _ _ _ _ _ _ _ _ _ _ _ _\n];\ndefine register offset=0x1200 size=2 [\n\tXMM0_Wa XMM0_Wb XMM0_Wc XMM0_Wd XMM0_We XMM0_Wf XMM0_Wg XMM0_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM1_Wa XMM1_Wb XMM1_Wc XMM1_Wd XMM1_We XMM1_Wf XMM1_Wg XMM1_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM2_Wa XMM2_Wb XMM2_Wc XMM2_Wd XMM2_We XMM2_Wf XMM2_Wg XMM2_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM3_Wa XMM3_Wb XMM3_Wc XMM3_Wd XMM3_We XMM3_Wf XMM3_Wg XMM3_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM4_Wa XMM4_Wb XMM4_Wc XMM4_Wd XMM4_We XMM4_Wf XMM4_Wg XMM4_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM5_Wa XMM5_Wb XMM5_Wc XMM5_Wd XMM5_We XMM5_Wf XMM5_Wg XMM5_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM6_Wa XMM6_Wb XMM6_Wc XMM6_Wd XMM6_We XMM6_Wf XMM6_Wg XMM6_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM7_Wa XMM7_Wb XMM7_Wc XMM7_Wd XMM7_We XMM7_Wf XMM7_Wg XMM7_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM8_Wa XMM8_Wb XMM8_Wc XMM8_Wd XMM8_We XMM8_Wf XMM8_Wg XMM8_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM9_Wa XMM9_Wb XMM9_Wc XMM9_Wd XMM9_We XMM9_Wf XMM9_Wg XMM9_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM10_Wa XMM10_Wb XMM10_Wc XMM10_Wd XMM10_We XMM10_Wf XMM10_Wg XMM10_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM11_Wa XMM11_Wb XMM11_Wc XMM11_Wd XMM11_We XMM11_Wf XMM11_Wg XMM11_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM12_Wa XMM12_Wb XMM12_Wc XMM12_Wd XMM12_We XMM12_Wf XMM12_Wg XMM12_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM13_Wa XMM13_Wb XMM13_Wc XMM13_Wd XMM13_We XMM13_Wf XMM13_Wg XMM13_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM14_Wa XMM14_Wb XMM14_Wc XMM14_Wd XMM14_We XMM14_Wf XMM14_Wg XMM14_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM15_Wa XMM15_Wb XMM15_Wc XMM15_Wd XMM15_We XMM15_Wf XMM15_Wg XMM15_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM16_Wa XMM16_Wb XMM16_Wc XMM16_Wd XMM16_We XMM16_Wf XMM16_Wg XMM16_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM17_Wa XMM17_Wb XMM17_Wc XMM17_Wd XMM17_We XMM17_Wf XMM17_Wg XMM17_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM18_Wa XMM18_Wb XMM18_Wc XMM18_Wd XMM18_We XMM18_Wf XMM18_Wg XMM18_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM19_Wa XMM19_Wb XMM19_Wc XMM19_Wd XMM19_We XMM19_Wf XMM19_Wg XMM19_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM20_Wa XMM20_Wb XMM20_Wc XMM20_Wd XMM20_We XMM20_Wf XMM20_Wg XMM20_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM21_Wa XMM21_Wb XMM21_Wc XMM21_Wd XMM21_We XMM21_Wf XMM21_Wg XMM21_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM22_Wa XMM22_Wb XMM22_Wc XMM22_Wd XMM22_We XMM22_Wf XMM22_Wg XMM22_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM23_Wa XMM23_Wb XMM23_Wc XMM23_Wd XMM23_We XMM23_Wf XMM23_Wg XMM23_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM24_Wa XMM24_Wb XMM24_Wc XMM24_Wd XMM24_We XMM24_Wf XMM24_Wg XMM24_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM25_Wa XMM25_Wb XMM25_Wc XMM25_Wd XMM25_We XMM25_Wf XMM25_Wg XMM25_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM26_Wa XMM26_Wb XMM26_Wc XMM26_Wd XMM26_We XMM26_Wf XMM26_Wg XMM26_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM27_Wa XMM27_Wb XMM27_Wc XMM27_Wd XMM27_We XMM27_Wf XMM27_Wg XMM27_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM28_Wa XMM28_Wb XMM28_Wc XMM28_Wd XMM28_We XMM28_Wf XMM28_Wg XMM28_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM29_Wa XMM29_Wb XMM29_Wc XMM29_Wd XMM29_We XMM29_Wf XMM29_Wg XMM29_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM30_Wa XMM30_Wb XMM30_Wc XMM30_Wd XMM30_We XMM30_Wf XMM30_Wg XMM30_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM31_Wa XMM31_Wb XMM31_Wc XMM31_Wd XMM31_We XMM31_Wf XMM31_Wg XMM31_Wh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n];\ndefine register offset=0x1200 size=1 [\n\tXMM0_Ba XMM0_Bb XMM0_Bc XMM0_Bd XMM0_Be XMM0_Bf XMM0_Bg XMM0_Bh XMM0_Bi XMM0_Bj XMM0_Bk XMM0_Bl XMM0_Bm XMM0_Bn XMM0_Bo XMM0_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM1_Ba XMM1_Bb XMM1_Bc XMM1_Bd XMM1_Be XMM1_Bf XMM1_Bg XMM1_Bh XMM1_Bi XMM1_Bj XMM1_Bk XMM1_Bl XMM1_Bm XMM1_Bn XMM1_Bo XMM1_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM2_Ba XMM2_Bb XMM2_Bc XMM2_Bd XMM2_Be XMM2_Bf XMM2_Bg XMM2_Bh XMM2_Bi XMM2_Bj XMM2_Bk XMM2_Bl XMM2_Bm XMM2_Bn XMM2_Bo XMM2_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM3_Ba XMM3_Bb XMM3_Bc XMM3_Bd XMM3_Be XMM3_Bf XMM3_Bg XMM3_Bh XMM3_Bi XMM3_Bj XMM3_Bk XMM3_Bl XMM3_Bm XMM3_Bn XMM3_Bo XMM3_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM4_Ba XMM4_Bb XMM4_Bc XMM4_Bd XMM4_Be XMM4_Bf XMM4_Bg XMM4_Bh XMM4_Bi XMM4_Bj XMM4_Bk XMM4_Bl XMM4_Bm XMM4_Bn XMM4_Bo XMM4_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM5_Ba XMM5_Bb XMM5_Bc XMM5_Bd XMM5_Be XMM5_Bf XMM5_Bg XMM5_Bh XMM5_Bi XMM5_Bj XMM5_Bk XMM5_Bl XMM5_Bm XMM5_Bn XMM5_Bo XMM5_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM6_Ba XMM6_Bb XMM6_Bc XMM6_Bd XMM6_Be XMM6_Bf XMM6_Bg XMM6_Bh XMM6_Bi XMM6_Bj XMM6_Bk XMM6_Bl XMM6_Bm XMM6_Bn XMM6_Bo XMM6_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM7_Ba XMM7_Bb XMM7_Bc XMM7_Bd XMM7_Be XMM7_Bf XMM7_Bg XMM7_Bh XMM7_Bi XMM7_Bj XMM7_Bk XMM7_Bl XMM7_Bm XMM7_Bn XMM7_Bo XMM7_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM8_Ba XMM8_Bb XMM8_Bc XMM8_Bd XMM8_Be XMM8_Bf XMM8_Bg XMM8_Bh XMM8_Bi XMM8_Bj XMM8_Bk XMM8_Bl XMM8_Bm XMM8_Bn XMM8_Bo XMM8_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM9_Ba XMM9_Bb XMM9_Bc XMM9_Bd XMM9_Be XMM9_Bf XMM9_Bg XMM9_Bh XMM9_Bi XMM9_Bj XMM9_Bk XMM9_Bl XMM9_Bm XMM9_Bn XMM9_Bo XMM9_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM10_Ba XMM10_Bb XMM10_Bc XMM10_Bd XMM10_Be XMM10_Bf XMM10_Bg XMM10_Bh XMM10_Bi XMM10_Bj XMM10_Bk XMM10_Bl XMM10_Bm XMM10_Bn XMM10_Bo XMM10_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM11_Ba XMM11_Bb XMM11_Bc XMM11_Bd XMM11_Be XMM11_Bf XMM11_Bg XMM11_Bh XMM11_Bi XMM11_Bj XMM11_Bk XMM11_Bl XMM11_Bm XMM11_Bn XMM11_Bo XMM11_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM12_Ba XMM12_Bb XMM12_Bc XMM12_Bd XMM12_Be XMM12_Bf XMM12_Bg XMM12_Bh XMM12_Bi XMM12_Bj XMM12_Bk XMM12_Bl XMM12_Bm XMM12_Bn XMM12_Bo XMM12_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM13_Ba XMM13_Bb XMM13_Bc XMM13_Bd XMM13_Be XMM13_Bf XMM13_Bg XMM13_Bh XMM13_Bi XMM13_Bj XMM13_Bk XMM13_Bl XMM13_Bm XMM13_Bn XMM13_Bo XMM13_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM14_Ba XMM14_Bb XMM14_Bc XMM14_Bd XMM14_Be XMM14_Bf XMM14_Bg XMM14_Bh XMM14_Bi XMM14_Bj XMM14_Bk XMM14_Bl XMM14_Bm XMM14_Bn XMM14_Bo XMM14_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM15_Ba XMM15_Bb XMM15_Bc XMM15_Bd XMM15_Be XMM15_Bf XMM15_Bg XMM15_Bh XMM15_Bi XMM15_Bj XMM15_Bk XMM15_Bl XMM15_Bm XMM15_Bn XMM15_Bo XMM15_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM16_Ba XMM16_Bb XMM16_Bc XMM16_Bd XMM16_Be XMM16_Bf XMM16_Bg XMM16_Bh XMM16_Bi XMM16_Bj XMM16_Bk XMM16_Bl XMM16_Bm XMM16_Bn XMM16_Bo XMM16_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM17_Ba XMM17_Bb XMM17_Bc XMM17_Bd XMM17_Be XMM17_Bf XMM17_Bg XMM17_Bh XMM17_Bi XMM17_Bj XMM17_Bk XMM17_Bl XMM17_Bm XMM17_Bn XMM17_Bo XMM17_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM18_Ba XMM18_Bb XMM18_Bc XMM18_Bd XMM18_Be XMM18_Bf XMM18_Bg XMM18_Bh XMM18_Bi XMM18_Bj XMM18_Bk XMM18_Bl XMM18_Bm XMM18_Bn XMM18_Bo XMM18_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM19_Ba XMM19_Bb XMM19_Bc XMM19_Bd XMM19_Be XMM19_Bf XMM19_Bg XMM19_Bh XMM19_Bi XMM19_Bj XMM19_Bk XMM19_Bl XMM19_Bm XMM19_Bn XMM19_Bo XMM19_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM20_Ba XMM20_Bb XMM20_Bc XMM20_Bd XMM20_Be XMM20_Bf XMM20_Bg XMM20_Bh XMM20_Bi XMM20_Bj XMM20_Bk XMM20_Bl XMM20_Bm XMM20_Bn XMM20_Bo XMM20_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM21_Ba XMM21_Bb XMM21_Bc XMM21_Bd XMM21_Be XMM21_Bf XMM21_Bg XMM21_Bh XMM21_Bi XMM21_Bj XMM21_Bk XMM21_Bl XMM21_Bm XMM21_Bn XMM21_Bo XMM21_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM22_Ba XMM22_Bb XMM22_Bc XMM22_Bd XMM22_Be XMM22_Bf XMM22_Bg XMM22_Bh XMM22_Bi XMM22_Bj XMM22_Bk XMM22_Bl XMM22_Bm XMM22_Bn XMM22_Bo XMM22_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM23_Ba XMM23_Bb XMM23_Bc XMM23_Bd XMM23_Be XMM23_Bf XMM23_Bg XMM23_Bh XMM23_Bi XMM23_Bj XMM23_Bk XMM23_Bl XMM23_Bm XMM23_Bn XMM23_Bo XMM23_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM24_Ba XMM24_Bb XMM24_Bc XMM24_Bd XMM24_Be XMM24_Bf XMM24_Bg XMM24_Bh XMM24_Bi XMM24_Bj XMM24_Bk XMM24_Bl XMM24_Bm XMM24_Bn XMM24_Bo XMM24_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM25_Ba XMM25_Bb XMM25_Bc XMM25_Bd XMM25_Be XMM25_Bf XMM25_Bg XMM25_Bh XMM25_Bi XMM25_Bj XMM25_Bk XMM25_Bl XMM25_Bm XMM25_Bn XMM25_Bo XMM25_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM26_Ba XMM26_Bb XMM26_Bc XMM26_Bd XMM26_Be XMM26_Bf XMM26_Bg XMM26_Bh XMM26_Bi XMM26_Bj XMM26_Bk XMM26_Bl XMM26_Bm XMM26_Bn XMM26_Bo XMM26_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM27_Ba XMM27_Bb XMM27_Bc XMM27_Bd XMM27_Be XMM27_Bf XMM27_Bg XMM27_Bh XMM27_Bi XMM27_Bj XMM27_Bk XMM27_Bl XMM27_Bm XMM27_Bn XMM27_Bo XMM27_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM28_Ba XMM28_Bb XMM28_Bc XMM28_Bd XMM28_Be XMM28_Bf XMM28_Bg XMM28_Bh XMM28_Bi XMM28_Bj XMM28_Bk XMM28_Bl XMM28_Bm XMM28_Bn XMM28_Bo XMM28_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM29_Ba XMM29_Bb XMM29_Bc XMM29_Bd XMM29_Be XMM29_Bf XMM29_Bg XMM29_Bh XMM29_Bi XMM29_Bj XMM29_Bk XMM29_Bl XMM29_Bm XMM29_Bn XMM29_Bo XMM29_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM30_Ba XMM30_Bb XMM30_Bc XMM30_Bd XMM30_Be XMM30_Bf XMM30_Bg XMM30_Bh XMM30_Bi XMM30_Bj XMM30_Bk XMM30_Bl XMM30_Bm XMM30_Bn XMM30_Bo XMM30_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n\tXMM31_Ba XMM31_Bb XMM31_Bc XMM31_Bd XMM31_Be XMM31_Bf XMM31_Bg XMM31_Bh XMM31_Bi XMM31_Bj XMM31_Bk XMM31_Bl XMM31_Bm XMM31_Bn XMM31_Bo XMM31_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\n];\n\ndefine register offset=0x1200 size=32 [\n\tYMM0\t_\tYMM1\t_\n\tYMM2\t_\tYMM3\t_\n\tYMM4\t_\tYMM5\t_\n\tYMM6\t_\tYMM7\t_\n\tYMM8\t_\tYMM9\t_\n\tYMM10\t_\tYMM11\t_\n\tYMM12\t_\tYMM13\t_\n\tYMM14\t_\tYMM15\t_\n\tYMM16\t_\tYMM17\t_\n\tYMM18\t_\tYMM19\t_\n\tYMM20\t_\tYMM21\t_\n\tYMM22\t_\tYMM23\t_\n\tYMM24\t_\tYMM25\t_\n\tYMM26\t_\tYMM27\t_\n\tYMM28\t_\tYMM29\t_\n\tYMM30\t_\tYMM31\t_\n];\n\ndefine register offset=0x1200 size=64 [\n\tZMM0\tZMM1\n\tZMM2\tZMM3\n\tZMM4\tZMM5\n\tZMM6\tZMM7\n\tZMM8\tZMM9\n\tZMM10\tZMM11\n\tZMM12\tZMM13\n\tZMM14\tZMM15\n\tZMM16\tZMM17\n\tZMM18\tZMM19\n\tZMM20\tZMM21\n\tZMM22\tZMM23\n\tZMM24\tZMM25\n\tZMM26\tZMM27\n\tZMM28\tZMM29\n\tZMM30\tZMM31\n];\n\n# Define context bits\ndefine register offset=0x2000 size=8 contextreg;\n\n# AVX-512 opmask registers\ndefine register offset=2100 size=8 [\n\tK0 K1 K2 K3 K4 K5 K6 K7\n];\n\n# dummy registers for managing broadcast data for AVX512\ndefine register offset=2200 size=4 [ BCST4 ];\ndefine register offset=2200 size=8 [ BCST8 ];\ndefine register offset=2200 size=16 [ BCST16 ];\ndefine register offset=2200 size=32 [ BCST32 ];\ndefine register offset=2200 size=64 [ BCST64 ];\n\ndefine register offset=2300 size=16 [ XmmResult _ _ _ XmmMask ];\ndefine register offset=2300 size=32 [ YmmResult _ YmmMask ];\ndefine register offset=2300 size=64 [ ZmmResult ZmmMask ];\n\n\n#\n#\n# This context layout is important: the 32 bit version sees addrsize as just the\n# low-order bit, whereas the 64 bit sees both bits. This ensures that the 32 and 64\n# are technically binary compatible, but since the 32 bit language can't see that\n# addrsize is 2 bits, they won't be pulled up into constructors where bit 0 is always\n# 0 (which it is), and then you don't get the decision conflicts that choose\n# context over table order\n#\n#\n\ndefine context contextreg\n@ifdef IA64\n # Stored context\n longMode=(0,0) # 0 for 32-bit emulation, 1 for 64-bit mode\n reserved=(1,3)\n addrsize=(4,5) # =0 16-bit addressing =1 32-bit addressing =2 64-bit addressing\n@else\n # Stored context\n reserved=(0,3)\n addrsize=(5,5) # =0 16-bit addressing =1 32-bit addressing\n@endif\n bit64=(4,4) # =0 16/32 bit =1 64-bit\n opsize=(6,7) # =0 16-bit operands =1 32-bit operands =2 64-bit operands\n segover=(8,10) # 0=default 1=cs 2=ss 3=ds 4=es 5=fs 6=gs\n highseg=(8,8) # high bit of segover will be set for ES, FS, GS\n protectedMode=(11,11) # 0 for real mode, 1 for protected mode\n # End stored context\n\n mandover=(12,14) # 0x66 0xf2 or 0xf3 overrides (for mandatory prefixes)\n repneprefx=(12,12) # 0xf2 REPNE prefi\n repprefx=(13,13) # 0xf3 REP prefix\n xacquireprefx=(12,12) # 0xf2 XACQUIRE prefix\n xreleaseprefx=(13,13) # 0xf3 XRELEASE prefix\n prefix_f2=(12,12) # This is not really a REPNE override, it means there is a real(read)/implied(vex) f2 byte\n prefix_f3=(13,13) # This is not really a REP override, it means there is an real(read)/implied(vex) f3 byte\n prefix_66=(14,14) # This is not really a OPSIZE override, it means there is an real(read)/implied(vex) 66 byte\n\n rexWRXBprefix=(15,18) # REX.WRXB bits\n rexWprefix=(15,15) # REX.W bit prefix (opsize=2 when REX.W is set)\n rexRprefix=(16,16) # REX.R bit prefix extend r\n rexXprefix=(17,17) # REX.X bit prefix extend SIB index field to 4 bits\n rexBprefix=(18,18) # REX.B bit prefix extend r/m, SIB base, Reg operand\n rexprefix=(19,19) # True if the Rex prefix is present - note, if present, vex_mode is not supported\n # rexWRXB bits can be re-used since they are incompatible.\n\n vexMode=(20,21) # 2 for evex instruction, 1 for vexMode, 0 for normal\n \n evexL = (22,23) # 0 for 128, 1 for 256, 2 for 512 (also used for rounding control)\n evexLp=(22,22) # EVEX.L'\n vexL=(23,23) # 0 for 128, 1 for 256\n\n evexV5_XmmReg=(24,28) # evex byte for matching ZmmReg\n evexV5_YmmReg=(24,28) # evex byte for matching ZmmReg\n evexV5_ZmmReg=(24,28) # evex byte for matching ZmmReg\n evexV5=(24,28) # EVEX.V' combined with EVEX.vvvv\n evexVp=(24,24) # EVEX.V' bit prefix extends EVEX.vvvv (stored inverted)\n vexVVVV=(25,28) # value of vex byte for matching\n vexVVVV_r32=(25,28) # value of vex byte for matching a normal 32 bit register\n vexVVVV_r64=(25,28) # value of vex byte for matching a normal 64 bit register\n vexVVVV_XmmReg=(25,28) # value of vex byte for matching XmmReg\n vexVVVV_YmmReg=(25,28) # value of vex byte for matching YmmReg\n vexVVVV_ZmmReg=(25,28) # value of vex byte for matching ZmmReg\n\n vexHighV=(25,25)\n evexVopmask=(26,28) # VEX.vvvv opmask\n\n suffix3D=(22,29) # 3DNow suffix byte (overlaps un-modified vex context region)\n \n instrPhase=(30,30) # 0: initial/prefix phase, 1: primary instruction phase\n\n lockprefx=(31,31) # 0xf0 LOCK prefix\n \n vexMMMMM=(32,36) # need to match for preceding bytes 1=0x0F, 2=0x0F 0x38, 3=0x0F 0x3A\n\n evexRp=(37,37) # EVEX.R' bit prefix extends r\n evexB = (38,38) # EVEX.b Broadcast\n evexZ = (39,39) # Opmask behavior 1 for zeroing-masking, 0 for merging-masking\n evexAAA=(40,42) # Opmask selector\n evexOpmask=(40,42) # Used for attaching Opmask registers\n evexD8Type=(43,43) # Used for compressed Disp8*N, can range from 1 to 64\n evexBType=(47,47) # Used for Disp8*N (see table 2-34 in 325462-sdm-vol-1-2abcd-3abcd-4.pdf)\n evexTType=(44,47) # Used for Disp8*N (see table 2-35 in 325462-sdm-vol-1-2abcd-3abcd-4.pdf)\n evexDisp8=(44,46)\n reservedHigh=(48,63) # reserved for future use\n\n;\n\n\n# These are only to be used with pre-REX (original 8086, 80386) and REX encoding. Do not use with VEX encoding.\n# These are to be used to designate that the opcode sequence begins with one of these \"mandatory\" prefix values.\n# This allows the other prefixes to come before the mandatory value.\n# For example: CRC32 r32, r16 -- 66 F2 OF 38 F1 C8\n\n@define PRE_NO\t\t\"mandover=0\"\n@define PRE_66\t\t\"prefix_66=1\"\n@define PRE_F3\t\t\"prefix_f3=1\"\n@define PRE_F2\t\t\"prefix_f2=1\"\n\n\n\n# Define special registers for debugger\n@ifdef IA64\ndefine register offset=0x2200 size=4 [ IDTR_Limit ];\ndefine register offset=0x2200 size=12 [ IDTR ];\ndefine register offset=0x2204 size=8 [ IDTR_Address ];\n\ndefine register offset=0x2220 size=4 [ GDTR_Limit ];\ndefine register offset=0x2220 size=12 [ GDTR ];\ndefine register offset=0x2224 size=8 [ GDTR_Address ];\n\ndefine register offset=0x2240 size=4 [ LDTR_Limit ];\ndefine register offset=0x2240 size=14 [ LDTR ];\ndefine register offset=0x2244 size=8 [ LDTR_Address ];\ndefine register offset=0x2248 size=2 [ LDTR_Attributes ];\n\ndefine register offset=0x2260 size=4 [ TR_Limit ];\ndefine register offset=0x2260 size=14 [ TR ];\ndefine register offset=0x2264 size=8 [ TR_Address ];\ndefine register offset=0x2268 size=2 [ TR_Attributes ];\n@else\ndefine register offset=0x2200 size=6 [ IDTR ];\ndefine register offset=0x2200 size=2 [ IDTR_Limit ];\ndefine register offset=0x2202 size=4 [ IDTR_Address ];\n\ndefine register offset=0x2210 size=6 [ GDTR ];\ndefine register offset=0x2210 size=2 [ GDTR_Limit ];\ndefine register offset=0x2212 size=4 [ GDTR_Address ];\n\ndefine register offset=0x2220 size=6 [ LDTR ];\ndefine register offset=0x2220 size=2 [ LDTR_Limit ];\ndefine register offset=0x2222 size=4 [ LDTR_Address ];\n\ndefine register offset=0x2230 size=6 [ TR ];\ndefine register offset=0x2230 size=2 [ TR_Limit ];\ndefine register offset=0x2232 size=4 [ TR_Address ];\n@endif\n\ndefine token opbyte (8)\n byte=(0,7)\n high4=(4,7)\n high5=(3,7)\n low5=(0,4)\n byte_4=(4,4)\n byte_0=(0,0)\n;\n\ndefine token modrm (8)\n mod = (6,7)\n reg_opcode = (3,5)\n reg_opcode_hb = (5,5)\n r_m = (0,2)\n row = (4,7)\n col = (0,2)\n page = (3,3)\n cond = (0,3)\n reg8 = (3,5)\n reg16 = (3,5)\n reg32 = (3,5)\n reg64 = (3,5)\n reg8_x0 = (3,5)\n reg8_x1 = (3,5)\n reg16_x = (3,5)\n reg32_x = (3,5)\n reg64_x = (3,5)\n Sreg = (3,5)\n creg = (3,5)\n creg_x = (3,5)\n debugreg = (3,5)\n debugreg_x = (3,5)\n testreg = (3,5)\n r8 = (0,2)\n r16 = (0,2)\n r32 = (0,2)\n r64 = (0,2)\n r8_x0 = (0,2)\n r8_x1 = (0,2)\n r16_x = (0,2)\n r32_x = (0,2)\n r64_x = (0,2)\n frow = (4,7)\n fpage = (3,3)\n freg = (0,2)\n rexw = (3,3)\n rexr = (2,2)\n rexx = (1,1)\n rexb = (0,0)\n mmxmod = (6,7)\n mmxreg = (3,5)\n mmxreg1 = (3,5)\n mmxreg2 = (0,2)\n xmmmod = (6,7)\n xmmreg = (3,5)\n ymmreg = (3,5)\n zmmreg = (3,5)\n \n xmmreg1 = (3,5)\n ymmreg1 = (3,5)\n zmmreg1 = (3,5)\n xmmreg2 = (0,2)\n ymmreg2 = (0,2)\n zmmreg2 = (0,2)\n\n xmmreg_x = (3,5)\n ymmreg_x = (3,5)\n zmmreg_x = (3,5)\n xmmreg1_x = (3,5)\n ymmreg1_x = (3,5)\n zmmreg1_x = (3,5)\n xmmreg1_r = (3,5)\n ymmreg1_r = (3,5)\n zmmreg1_r = (3,5)\n xmmreg1_rx = (3,5)\n ymmreg1_rx = (3,5)\n zmmreg1_rx = (3,5)\n xmmreg2_b = (0,2)\n ymmreg2_b = (0,2)\n zmmreg2_b = (0,2)\n xmmreg2_x = (0,2)\n ymmreg2_x = (0,2)\n zmmreg2_x = (0,2)\n xmmreg2_bx = (0,2)\n ymmreg2_bx = (0,2)\n zmmreg2_bx = (0,2)\n \n\n vex_pp = (0,1)\n vex_l = (2,2)\n vex_vvvv = (3,6)\n vex_r = (7,7)\n vex_x = (6,6)\n vex_b = (5,5)\n vex_w = (7,7)\n vex_mmmmm = (0,4)\n \n evex_rp = (4,4)\n evex_res = (3,3)\n evex_res2 = (2,2)\n evex_mmm = (0,2)\n \n evex_z = (7,7)\n evex_lp = (6,6)\n evex_l = (5,5)\n evex_b = (4,4)\n evex_vp = (3,3)\n evex_aaa = (0,2)\n opmaskreg = (3,5)\n opmaskrm = (0,2)\n \n bnd1 = (3,5)\n bnd1_lb = (3,5)\n bnd1_ub = (3,5)\n bnd2 = (0,2)\n bnd2_lb = (0,2)\n bnd2_ub = (0,2)\n;\n\ndefine token sib (8)\n ss\t\t\t= (6,7)\n index\t\t\t= (3,5)\n index_x\t\t= (3,5)\n index64\t\t= (3,5)\n index64_x\t\t= (3,5)\n xmm_vsib\t\t= (3,5)\n xmm_vsib_x\t= (3,5)\n ymm_vsib\t\t= (3,5)\n ymm_vsib_x\t= (3,5)\n zmm_vsib\t\t= (3,5)\n zmm_vsib_x\t= (3,5)\n base\t\t\t= (0,2)\n base_x\t\t= (0,2)\n base64\t\t= (0,2)\n base64_x\t\t= (0,2)\n;\n\ndefine token I8 (8)\n Xmm_imm8_7_4=(4,7)\n Ymm_imm8_7_4=(4,7)\n imm8_7=(7,7)\n imm8_6=(6,6)\n imm8_6_7=(6,7)\n imm8_5=(5,5)\n imm8_5_7=(5,7)\n imm8_4=(4,4)\n imm8_4_7=(4,7)\n imm8_3=(3,3)\n imm8_3_7=(3,7)\n imm8_2=(2,2)\n imm8_2_7=(2,7)\n imm8_1=(1,1)\n imm8_1_7=(1,7)\n imm8_0=(0,0)\n imm8_3_0=(0,3)\n imm8=(0,7)\n imm8_val=(0,7)\n simm8=(0,7) signed\n;\n \ndefine token I16 (16) imm16_15=(15,15) imm16=(0,15) simm16=(0,15) signed j16=(0,15);\ndefine token I32 (32) imm32=(0,31) simm32=(0,31) signed;\ndefine token I64 (64) imm64=(0,63) simm64=(0,63) signed;\ndefine token override (8) over=(0,7);\n\nattach variables [ r32 reg32 base index ] [ EAX ECX EDX EBX ESP EBP ESI EDI ];\nattach variables [ r16 reg16 ] [ AX CX DX BX SP BP SI DI ];\nattach variables [ r8 reg8 ] [ AL CL DL BL AH CH DH BH ];\nattach variables Sreg [ ES CS SS DS FS GS _ _ ];\nattach variables freg [ ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 ];\nattach variables [ debugreg ] [ DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 ];\n@ifdef IA64\nattach variables [ r64 reg64 base64 index64 ] [ RAX RCX RDX RBX RSP RBP RSI RDI ];\nattach variables [ r64_x reg64_x base64_x index64_x ] [ R8 R9 R10 R11 R12 R13 R14 R15 ];\nattach variables [ r32_x reg32_x base_x index_x ] [ R8D R9D R10D R11D R12D R13D R14D R15D ];\nattach variables [ r16_x reg16_x ] [ R8W R9W R10W R11W R12W R13W R14W R15W ];\nattach variables [ r8_x0 reg8_x0 ] [ AL CL DL BL SPL BPL SIL DIL ];\nattach variables [ r8_x1 reg8_x1 ] [ R8B R9B R10B R11B R12B R13B R14B R15B ];\nattach variables [ debugreg_x ] [ DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 ];\nattach variables creg [ CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 ];\nattach variables creg_x [ CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 ];\n@else\nattach variables [ testreg ] [ TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 ];\nattach variables creg [ CR0 _ CR2 CR3 CR4 _ _ _ ];\n@endif\n\nattach values ss [ 1 2 4 8];\n\nattach variables [ mmxreg mmxreg1 mmxreg2 ] [ MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 ];\n\nattach variables [ xmmreg xmmreg1 xmmreg2 xmm_vsib ] [ XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 ];\n\nattach variables [ xmmreg_x xmmreg1_x xmmreg2_b xmm_vsib_x ] [ XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 ];\n\nattach variables [ xmmreg1_r xmmreg2_x ] [ XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 ];\n\nattach variables [ xmmreg1_rx xmmreg2_bx ] [ XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 ];\n\nattach variables [ vexVVVV_XmmReg Xmm_imm8_7_4 ] [ XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 ];\n\nattach variables [ vexVVVV_YmmReg Ymm_imm8_7_4 ] [ YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 ];\n\nattach variables [ vexVVVV_ZmmReg ] [ ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 ];\n\nattach variables [ evexV5_XmmReg ] [ XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15\n\t XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 ];\n\nattach variables [ evexV5_YmmReg ] [ YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15\n\t YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 ];\n\nattach variables [ evexV5_ZmmReg ] [ ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15\n\t ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 ];\n\n@ifdef IA64\nattach variables [ vexVVVV_r32 ] [ EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D ];\nattach variables [ vexVVVV_r64 ] [ RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 ];\n@else\nattach variables [ vexVVVV_r32 ] [ EAX ECX EDX EBX ESP EBP ESI EDI _ _ _ _ _ _ _ _ ];\n@endif\n\nattach variables [ evexOpmask opmaskreg opmaskrm evexVopmask ] [ K0 K1 K2 K3 K4 K5 K6 K7 ];\n\nattach variables [ ymmreg ymmreg1 ymmreg2 ymm_vsib ]\t\t\t[ YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 ];\nattach variables [ ymmreg_x ymmreg1_x ymmreg2_b ymm_vsib_x ]\t[ YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 ];\nattach variables [ ymmreg1_r ymmreg2_x ]\t\t\t\t\t\t[ YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 ];\nattach variables [ ymmreg1_rx ymmreg2_bx ]\t\t\t\t\t\t[ YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 ];\n\nattach variables [ zmmreg zmmreg1 zmmreg2 zmm_vsib ]\t\t\t[ ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ];\nattach variables [ zmmreg_x zmmreg1_x zmmreg2_b zmm_vsib_x ]\t[ ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 ];\nattach variables [ zmmreg1_r zmmreg2_x ]\t\t\t\t\t\t[ ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ];\nattach variables [ zmmreg1_rx zmmreg2_bx ]\t\t\t\t\t\t[ ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 ];\n\nattach variables [ bnd1 bnd2 ] [ BND0 BND1 BND2 BND3 _ _ _ _ ];\nattach variables [ bnd1_lb bnd2_lb ] [ BND0_LB BND1_LB BND2_LB BND3_LB _ _ _ _ ];\nattach variables [ bnd1_ub bnd2_ub ] [ BND0_UB BND1_UB BND2_UB BND3_UB _ _ _ _ ];\n\ndefine pcodeop segment; # Define special pcodeop that calculates the RAM address\n # given the segment selector and offset as input\n\ndefine pcodeop in; # force in/out to show up in decompiler\ndefine pcodeop out;\ndefine pcodeop sysenter;\ndefine pcodeop sysexit;\ndefine pcodeop syscall;\ndefine pcodeop sysret;\ndefine pcodeop swapgs;\ndefine pcodeop invlpg;\ndefine pcodeop invlpga;\ndefine pcodeop invpcid;\ndefine pcodeop rdtscp;\ndefine pcodeop mwait;\ndefine pcodeop mwaitx;\ndefine pcodeop monitor;\ndefine pcodeop monitorx;\ndefine pcodeop swi; # for INT instruction\n\ndefine pcodeop LOCK; # for LOCK prefix\ndefine pcodeop UNLOCK; # for LOCK prefix\ndefine pcodeop XACQUIRE; # for XACQUIRE prefix\ndefine pcodeop XRELEASE; # for XRELEASE prefix\n\n# MFL: definitions for AMD hardware assisted virtualization instructions\ndefine pcodeop clgi; # clear global interrupt flag (GIF)\ndefine pcodeop stgi; # set global interrupt flag (GIF)\ndefine pcodeop vmload; # Load state from VMCD, opcode 0f 01 da\ndefine pcodeop vmmcall; # Call VMM, opcode 0f 01 d9\ndefine pcodeop vmrun; # Run virtual machine, opcode 0f 01 d8\ndefine pcodeop vmsave; # Save state to VMCB, opcode 0f 0a db\n\n# MFL: definitions for Intel IA hardware assisted virtualization instructions\ndefine pcodeop invept; # Invalidate Translations Derived from extended page tables (EPT); opcode 66 0f 38 80\ndefine pcodeop invvpid; # Invalidate Translations Based on virtual-processor identifier (VPID); opcode 66 0f 38 81\ndefine pcodeop vmcall; # Call to VM monitor by causing VM exit, opcode 0f 01 c1\ndefine pcodeop vmclear; # Clear virtual-machine control structure, opcode 66 0f c7 /6\ndefine pcodeop vmfunc; # call virtual-machine function refernced by EAX\ndefine pcodeop vmlaunch; # Launch virtual machine managed by current VMCCS; opcode 0f 01 c2\ndefine pcodeop vmresume; # Resume virtual machine managed by current VMCS; opcode 0f 01 c3\ndefine pcodeop vmptrld; # Load pointer to virtual-machine control structure; opcode 0f c6 /6\ndefine pcodeop vmptrst; # Store pointer to virtual-machine control structure; opcode 0f c7 /7\ndefine pcodeop vmread; # Read field from virtual-machine control structure; opcode 0f 78\ndefine pcodeop vmwrite; # Write field to virtual-machine control structure; opcode 0f 79\ndefine pcodeop vmxoff; # Leave VMX operation; opcode 0f 01 c4\ndefine pcodeop vmxon; # Enter VMX operation; opcode f3 0f C7 /6 \n\n@ifdef IA64\n@define LONGMODE_ON \"longMode=1\"\n@define LONGMODE_OFF \"longMode=0\"\n@else\n@define LONGMODE_OFF \"opsize=opsize\" # NOP\n@endif\n\n#when not in 64-bit mode, opcode 0x82 results in the same instruction as opcode 0x80\n#in 64-bit mode, opcode 0x82 results in #UD\n#see 22.15 \"Undefined Opcodes\" of the intel manual\n@ifdef IA64\n@define BYTE_80_82 \"(byte=0x80 | (longMode=0 & byte=0x82))\"\n@else\n@define BYTE_80_82 \"(byte=0x80 | byte=0x82)\"\n@endif\n\n@include \"macros.sinc\"\n\n@ifdef IA64\nReg8: reg8 is rexprefix=0 & reg8 { export reg8; }\nReg8: reg8_x0 is rexprefix=1 & rexRprefix=0 & reg8_x0 { export reg8_x0; }\nReg8: reg8_x1 is rexprefix=1 & rexRprefix=1 & reg8_x1 { export reg8_x1; }\nReg16: reg16 is rexRprefix=0 & reg16 { export reg16; }\nReg16: reg16_x is rexRprefix=1 & reg16_x { export reg16_x; }\nReg32: reg32 is rexRprefix=0 & reg32 { export reg32; }\nReg32: reg32_x is rexRprefix=1 & reg32_x { export reg32_x; }\nReg64: reg64 is rexRprefix=0 & reg64 { export reg64; }\nReg64: reg64_x is rexRprefix=1 & reg64_x { export reg64_x; }\nRmr8: r8 is rexprefix=0 & r8 { export r8; }\nRmr8: r8_x0 is rexprefix=1 & rexBprefix=0 & r8_x0 { export r8_x0; }\nRmr8: r8_x1 is rexprefix=1 & rexBprefix=1 & r8_x1 { export r8_x1; }\nCRmr8: r8 is rexBprefix=0 & r8\t { export r8; }\nCRmr8: r8 is addrsize=2 & rexBprefix=0 & r8 { export r8; }\nCRmr8: r8_x0 is addrsize=2 & rexprefix=1 & rexBprefix=0 & r8_x0 { export r8_x0; }\nCRmr8: r8_x1 is addrsize=2 & rexprefix=1 & rexBprefix=1 & r8_x1 { export r8_x1; }\nRmr16: r16 is rexBprefix=0 & r16 { export r16; }\nRmr16: r16_x is rexBprefix=1 & r16_x { export r16_x; }\nCRmr16: r16 is rexBprefix=0 & r16 { export r16; }\nCRmr16: r16_x is rexBprefix=1 & r16_x { export r16_x; }\nRmr32: r32 is rexBprefix=0 & r32 { export r32; }\nRmr32: r32_x is rexBprefix=1 & r32_x { export r32_x; }\nCRmr32: r32 is rexBprefix=0 & r32 & r64 { export r64; }\nCRmr32: r32_x is rexBprefix=1 & r32_x & r64_x { export r64_x; }\nRmr64: r64 is rexBprefix=0 & r64 { export r64; }\nRmr64: r64_x is rexBprefix=1 & r64_x { export r64_x; }\nBase: base is rexBprefix=0 & base { export base; }\nBase: base_x is rexBprefix=1 & base_x { export base_x; }\nIndex: index is rexXprefix=0 & index { export index; }\nIndex: index_x is rexXprefix=1 & index_x { export index_x; }\nBase64: base64 is rexBprefix=0 & base64 { export base64; }\nBase64: base64_x is rexBprefix=1 & base64_x { export base64_x; }\nIndex64: index64 is rexXprefix=0 & index64 { export index64; }\nIndex64: index64_x is rexXprefix=1 & index64_x { export index64_x; }\nXmmReg: xmmreg is rexRprefix=0 & xmmreg { export xmmreg; }\nXmmReg: xmmreg_x is rexRprefix=1 & xmmreg_x { export xmmreg_x; }\nXmmReg1: xmmreg1 is rexRprefix=0 & xmmreg1 { export xmmreg1; }\nXmmReg1: xmmreg1_x is rexRprefix=1 & xmmreg1_x { export xmmreg1_x; }\nXmmReg1: xmmreg1_r is rexRprefix=0 & evexRp=1 & xmmreg1_r { export xmmreg1_r; }\nXmmReg1: xmmreg1_rx is rexRprefix=1 & evexRp=1 & xmmreg1_rx { export xmmreg1_rx; }\nXmmReg2: xmmreg2 is rexBprefix=0 & xmmreg2 { export xmmreg2; }\nXmmReg2: xmmreg2_b is rexBprefix=1 & xmmreg2_b { export xmmreg2_b; }\nXmmReg2: xmmreg2_x is rexBprefix=0 & rexXprefix=1 & xmmreg2_x { export xmmreg2_x; }\nXmmReg2: xmmreg2_bx is rexBprefix=1 & rexXprefix=1 & xmmreg2_bx { export xmmreg2_bx; }\n\nYmmReg1: ymmreg1 is rexRprefix=0 & ymmreg1 { export ymmreg1; }\nYmmReg1: ymmreg1_x is rexRprefix=1 & ymmreg1_x { export ymmreg1_x; }\nYmmReg1: ymmreg1_r is rexRprefix=0 & evexRp=1 & ymmreg1_r { export ymmreg1_r; }\nYmmReg1: ymmreg1_rx is rexRprefix=1 & evexRp=1 & ymmreg1_rx { export ymmreg1_rx; }\nYmmReg2: ymmreg2 is rexBprefix=0 & ymmreg2 { export ymmreg2; }\nYmmReg2: ymmreg2_b is rexBprefix=1 & ymmreg2_b { export ymmreg2_b; }\nYmmReg2: ymmreg2_x is rexBprefix=0 & rexXprefix=1 & ymmreg2_x { export ymmreg2_x; }\nYmmReg2: ymmreg2_bx is rexBprefix=1 & rexXprefix=1 & ymmreg2_bx { export ymmreg2_bx; }\n\nZmmReg1: zmmreg1 is rexRprefix=0 & zmmreg1 { export zmmreg1; }\nZmmReg1: zmmreg1_x is rexRprefix=1 & zmmreg1_x { export zmmreg1_x; }\nZmmReg1: zmmreg1_r is rexRprefix=0 & evexRp=1 & zmmreg1_r { export zmmreg1_r; }\nZmmReg1: zmmreg1_rx is rexRprefix=1 & evexRp=1 & zmmreg1_rx { export zmmreg1_rx; }\nZmmReg2: zmmreg2 is rexBprefix=0 & zmmreg2 { export zmmreg2; }\nZmmReg2: zmmreg2_b is rexBprefix=1 & zmmreg2_b { export zmmreg2_b; }\nZmmReg2: zmmreg2_x is rexBprefix=0 & rexXprefix=1 & zmmreg2_x { export zmmreg2_x; }\nZmmReg2: zmmreg2_bx is rexBprefix=1 & rexXprefix=1 & zmmreg2_bx { export zmmreg2_bx; }\n\nXmm_vsib: xmm_vsib is rexXprefix=0 & xmm_vsib { export xmm_vsib; }\nXmm_vsib: xmm_vsib_x is rexXprefix=1 & xmm_vsib_x { export xmm_vsib_x; }\nYmm_vsib: ymm_vsib is rexXprefix=0 & ymm_vsib { export ymm_vsib; }\nYmm_vsib: ymm_vsib_x is rexXprefix=1 & ymm_vsib_x { export ymm_vsib_x; }\nZmm_vsib: zmm_vsib is rexXprefix=0 & zmm_vsib { export zmm_vsib; }\nZmm_vsib: zmm_vsib_x is rexXprefix=1 & zmm_vsib_x { export zmm_vsib_x; }\n@else\nReg8: reg8 is reg8 { export reg8; }\nReg16: reg16 is reg16 { export reg16; }\nReg32: reg32 is reg32 { export reg32; }\nRmr8: r8 is r8 { export r8; }\nCRmr8: r8 is r8 { export r8; }\nRmr16: r16 is r16 { export r16; }\nCRmr16: r16 is r16 { export r16; }\nRmr32: r32 is r32 { export r32; }\nCRmr32: r32 is r32 { export r32; }\nBase: base is base { export base; }\nIndex: index is index { export index; }\nXmmReg: xmmreg is xmmreg { export xmmreg; }\nXmmReg1: xmmreg1 is xmmreg1 { export xmmreg1; }\nXmmReg2: xmmreg2 is xmmreg2 { export xmmreg2; }\nYmmReg1: ymmreg1 is ymmreg1 { export ymmreg1; }\nYmmReg2: ymmreg2 is ymmreg2 { export ymmreg2; }\nZmmReg1: zmmreg1 is zmmreg1 { export zmmreg1; }\nZmmReg2: zmmreg2 is zmmreg2 { export zmmreg2; }\nXmm_vsib: xmm_vsib is xmm_vsib { export xmm_vsib; }\nYmm_vsib: ymm_vsib is ymm_vsib { export ymm_vsib; }\nZmm_vsib: zmm_vsib is zmm_vsib { export zmm_vsib; }\n@endif\n\n# signed immediate value subconstructors\n\nsimm8_16: simm8 is simm8 { export *[const]:2 simm8; }\nsimm8_32: simm8 is simm8 { export *[const]:4 simm8; }\n@ifdef IA64\nsimm8_64: simm8 is simm8 { export *[const]:8 simm8; }\n@endif\nsimm16_16: simm16 is simm16 { export *[const]:2 simm16; }\nsimm32_32: simm32 is simm32 { export *[const]:4 simm32; }\n@ifdef IA64\nsimm32_64: simm32 is simm32 { export *[const]:8 simm32; }\nimm32_64: imm32 is imm32 { export *[const]:8 imm32; }\n@endif\n\n# EVEX used a compressed Disp8*N format\n\n# Table 2-35:\n# TupleType | EVEX.B | InputSize | EVEX.W | Broadcast |N (VL=128) | N (VL=256) | N (VL=512) | evexBType\n# Full Mem | 0 | 32bit | 0 | none | 16 | 32 | 64 | 0\n# Full Mem | 1 | 32bit | 0 | {1tox} | 4 | 4 | 4 | 0\n# Full Mem | 0 | 64bit | 1 | none | 16 | 32 | 64 | 0\n# Full Mem | 1 | 64bit | 1 | {1tox} | 8 | 8 | 8 | 0\n# Half Mem | 0 | 32bit | 0 | none | 8 | 16 | 32 | 1\n# Half Mem | 1 | 32bit | 0 | {1tox} | 4 | 4 | 4 | 1\n\nevexDisp8N: offs is evexD8Type=0 & evexBType=0 & evexB=0 & evexL=0 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=0 & evexB=0 & evexL=1 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=0 & evexB=0 & evexL=2 [ offs = 6; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=0 & evexB=1 & rexWprefix=0 [ offs = 2; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=0 & evexB=1 & rexWprefix=1 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=1 & evexB=1 & rexWprefix=0 [ offs = 2; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=1 & evexB=0 & evexL=0 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=1 & evexB=0 & evexL=1 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=0 & evexBType=1 & evexB=0 & evexL=2 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\n\n# Table 2-35:\n# TupleType | InputSize | EVEX.W | N (VL=128) | N (VL=256) | N (VL=512) | evexTType\n# Full Mem | N/A | N/A | 16 | 32 | 64 | 0\n# Tuple 1 Scalar | 8bit | N/A | 1 | 1 | 1 | 1\n# Tuple 1 Scalar | 16bit | N/A | 2 | 2 | 2 | 2\n# Tuple 1 Scalar | 32bit | 0 | 4 | 4 | 4 | 3\n# Tuple 1 Scalar | 64bit | 1 | 8 | 8 | 8 | 3\n# Tuple 1 Fixed | 32bit | N/A | 4 | 4 | 4 | 4\n# Tuple 1 Fixed | 64bit | N/A | 8 | 8 | 8 | 5\n# Tuple 2 | 32bit | 0 | 8 | 8 | 8 | 6\n# Tuple 2 | 64bit | 1 | N/A | 16 | 16 | 6\n# Tuple 4 | 32bit | 0 | N/A | 16 | 16 | 7\n# Tuple 4 | 64bit | 1 | N/A | N/A | 32 | 7\n# Tuple 8 | 32bit | 0 | N/A | N/A | 32 | 8\n# Half Mem | N/A | N/A | 8 | 16 | 32 | 9\n# Quarter Mem | N/A | N/A | 4 | 8 | 16 | A\n# Eighth Mem | N/A | N/A | 2 | 4 | 8 | B\n# Mem128 | N/A | 1 | 16 | 16 | 16 | C\n# MOVDDUP | N/A | N/A | 8 | 32 | 64 | D\n\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x0 & evexL=0 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x0 & evexL=1 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x0 & evexL=2 [ offs = 6; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x9 & evexL=0 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x9 & evexL=1 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x9 & evexL=2 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xa & evexL=0 [ offs = 2; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xa & evexL=1 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xa & evexL=2 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xb & evexL=0 [ offs = 1; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xb & evexL=1 [ offs = 2; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xb & evexL=2 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\n\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x1 [ offs = 0; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x2 [ offs = 1; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x3 & rexWprefix=0 [ offs = 2; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x3 & rexWprefix=1 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x4 [ offs = 2; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x5 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x6 & rexWprefix=0 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x6 & rexWprefix=1 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x7 & rexWprefix=0 [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x7 & rexWprefix=1 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0x8 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\n\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xc [ offs = 4; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=0 [ offs = 3; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=1 [ offs = 5; evexDisp8=offs; ] { export *[const]:1 offs; }\nevexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=2 [ offs = 6; evexDisp8=offs; ] { export *[const]:1 offs; }\n\n\nsimm8_16: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:2 disp8N; }\nsimm8_32: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:4 disp8N; }\n@ifdef IA64\nsimm8_64: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:8 disp8N; }\n@endif\n\nusimm8_16: imm8 is imm8 & imm8_7=0 { export *[const]:2 imm8; }\nusimm8_16: val is imm8 & imm8_7=1 [ val = 0xff00 | imm8; ] { export *[const]:2 val; }\nusimm8_32: imm8 is imm8 & imm8_7=0 { export *[const]:4 imm8; }\nusimm8_32: val is imm8 & imm8_7=1 [ val = 0xffffff00 | imm8; ] { export *[const]:4 val; }\n@ifdef IA64\nusimm8_64: imm8 is imm8 & imm8_7=0 { export *[const]:8 imm8; }\nusimm8_64: val is imm8 & imm8_7=1 [ val = 0xffffffffffffff00 | imm8; ] { export *[const]:8 val; }\n@endif\n\n# unused\n#usimm16_32: imm16 is imm16 & imm16_15=0 { export *[const]:4 imm16; }\n#usimm16_32: val is imm16 & imm16_15=1 [ val = 0xffff0000 | imm16; ] { export *[const]:4 val; }\n\n# RIP/EIP relative address - NOTE: export of size 0 is intentional so it may be adjusted\npcRelSimm32: addr\tis simm32 [ addr=inst_next+simm32; ] { export addr; }\n\n# 16-bit addressing modes (the offset portion)\naddr16: [BX + SI]\t\tis mod=0 & r_m=0 & BX & SI\t\t{ local tmp=BX+SI; export tmp; }\naddr16: [BX + DI]\t\tis mod=0 & r_m=1 & BX & DI\t\t{ local tmp=BX+DI; export tmp; }\naddr16: [BP + SI]\t\tis mod=0 & r_m=2 & BP & SI\t\t{ local tmp=BP+SI; export tmp; }\naddr16: [BP + DI]\t\tis mod=0 & r_m=3 & BP & DI\t\t{ local tmp=BP+DI; export tmp; }\naddr16: [SI]\t\tis mod=0 & r_m=4 & SI\t\t\t{ export SI; }\naddr16: [DI]\t\tis mod=0 & r_m=5 & DI\t\t\t{ export DI; }\naddr16: [imm16]\t\tis mod=0 & r_m=6; imm16\t\t\t{ export *[const]:2 imm16; }\naddr16: [BX]\t\tis mod=0 & r_m=7 & BX\t\t\t{ export BX; }\naddr16: [BX + SI + simm8_16] is mod=1 & r_m=0 & BX & SI; simm8_16 { local tmp=BX+SI+simm8_16; export tmp; }\naddr16: [BX + DI + simm8_16] is mod=1 & r_m=1 & BX & DI; simm8_16 { local tmp=BX+DI+simm8_16; export tmp; }\naddr16: [BP + SI + simm8_16] is mod=1 & r_m=2 & BP & SI; simm8_16 { local tmp=BP+SI+simm8_16; export tmp; }\naddr16: [BP + DI + simm8_16] is mod=1 & r_m=3 & BP & DI; simm8_16 { local tmp=BP+DI+simm8_16; export tmp; }\naddr16: [SI + simm8_16] is mod=1 & r_m=4 & SI; simm8_16 { local tmp=SI+simm8_16; export tmp; }\naddr16: [DI + simm8_16] is mod=1 & r_m=5 & DI; simm8_16 { local tmp=DI+simm8_16; export tmp; }\naddr16: [BP + simm8_16] is mod=1 & r_m=6 & BP; simm8_16 { local tmp=BP+simm8_16; export tmp; }\naddr16: [BX + simm8_16] is mod=1 & r_m=7 & BX; simm8_16 { local tmp=BX+simm8_16; export tmp; }\naddr16: [BX + SI + imm16] is mod=2 & r_m=0 & BX & SI; imm16 { local tmp=BX+SI+imm16; export tmp; }\naddr16: [BX + DI + imm16] is mod=2 & r_m=1 & BX & DI; imm16 { local tmp=BX+DI+imm16; export tmp; }\naddr16: [BP + SI + imm16] is mod=2 & r_m=2 & BP & SI; imm16 { local tmp=BP+SI+imm16; export tmp; }\naddr16: [BP + DI + imm16] is mod=2 & r_m=3 & BP & DI; imm16 {local tmp=BP+DI+imm16; export tmp; }\naddr16: [SI + imm16] is mod=2 & r_m=4 & SI; imm16 { local tmp=SI+imm16; export tmp; }\naddr16: [DI + imm16] is mod=2 & r_m=5 & DI; imm16 { local tmp=DI+imm16; export tmp; }\naddr16: [BP + imm16] is mod=2 & r_m=6 & BP; imm16 { local tmp=BP+imm16; export tmp; }\naddr16: [BX + imm16] is mod=2 & r_m=7 & BX; imm16 { local tmp=BX+imm16; export tmp; }\n\n# 32-bit addressing modes (the offset portion)\naddr32: [Rmr32]\t\t\t\t\t\t\tis mod=0 & Rmr32 \t\t\t\t\t\t\t { export Rmr32; }\naddr32: [Rmr32 + simm8_32]\t\t\t\tis mod=1 & Rmr32; simm8_32 \t\t\t { local tmp=Rmr32+simm8_32; export tmp; }\naddr32: [Rmr32]\t\t\t\t\t\t\tis mod=1 & r_m!=4 & Rmr32; simm8=0\t\t\t { export Rmr32; }\naddr32: [Rmr32 + imm32]\t\t\t\t\tis mod=2 & Rmr32; imm32 { local tmp=Rmr32+imm32; export tmp; }\naddr32: [Rmr32]\t\t\t\t\t\t\tis mod=2 & r_m!=4 & Rmr32; imm32=0 { export Rmr32; }\naddr32: [imm32]\t\t\t\t\t\t\tis mod=0 & r_m=5; imm32 { export *[const]:4 imm32; }\naddr32: [Base + Index*ss]\t\t\t\tis mod=0 & r_m=4; Index & Base & ss { local tmp=Base+Index*ss; export tmp; }\naddr32: [Base]\t\t\t\t\t\t\tis mod=0 & r_m=4; index=4 & Base { export Base; }\naddr32: [Index*ss + imm32]\t\t\t\tis mod=0 & r_m=4; Index & base=5 & ss; imm32 { local tmp=imm32+Index*ss; export tmp; }\naddr32: [imm32]\t\t\t\t\t\t\tis mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:4 imm32; }\naddr32: [Base + Index*ss + simm8_32]\tis mod=1 & r_m=4; Index & Base & ss; simm8_32 { local tmp=simm8_32+Base+Index*ss; export tmp; }\naddr32: [Base + simm8_32]\t\t\t\tis mod=1 & r_m=4; index=4 & Base; simm8_32 { local tmp=simm8_32+Base; export tmp; }\naddr32: [Base + Index*ss]\t\t\t\tis mod=1 & r_m=4; Index & Base & ss; simm8=0 { local tmp=Base+Index*ss; export tmp; }\naddr32: [Base]\t\t\t\t\t\t\tis mod=1 & r_m=4; index=4 & Base; simm8=0 { export Base; }\naddr32: [Base + Index*ss + imm32]\t\tis mod=2 & r_m=4; Index & Base & ss; imm32 { local tmp=imm32+Base+Index*ss; export tmp; }\naddr32: [Base + imm32]\t\t\t\t\tis mod=2 & r_m=4; index=4 & Base; imm32 { local tmp=imm32+Base; export tmp; }\naddr32: [Base + Index*ss]\t\t\t\tis mod=2 & r_m=4; Index & Base & ss; imm32=0 { local tmp=Base+Index*ss; export tmp; }\naddr32: [Base]\t\t\t\t\t\t\tis mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; }\n@ifdef IA64\naddr32: [pcRelSimm32]\t\t\t\t\tis bit64=1 & mod=0 & r_m=4; index=4 & base=5; pcRelSimm32 { export *[const]:4 pcRelSimm32; }\n\nAddr32_64: [pcRelSimm32]\t\t\t\tis mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; }\nAddr32_64: [imm32]\t\t\t\t\t\tis mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:8 imm32; }\nAddr32_64: addr32\t\t\t\t\t\tis addr32\t\t\t\t\t\t\t\t\t { tmp:8 = sext(addr32); export tmp; }\n\n\n@endif\n\n# 64-bit addressing modes (the offset portion)\n\n@ifdef IA64\naddr64: [Rmr64]\t\t\t\t\t\t\tis mod=0 & Rmr64 { export Rmr64; }\naddr64: [Rmr64 + simm8_64]\t\t\t\tis mod=1 & Rmr64; simm8_64 { local tmp=Rmr64+simm8_64; export tmp; }\naddr64: [Rmr64 + simm32_64]\t\t\t\tis mod=2 & Rmr64; simm32_64 { local tmp=Rmr64+simm32_64; export tmp; }\naddr64: [Rmr64]\t\t\t\t\t\t\tis mod=1 & r_m!=4 & Rmr64; simm8=0 { export Rmr64; }\naddr64: [Rmr64]\t\t\t\t\t\t\tis mod=2 & r_m!=4 & Rmr64; simm32=0 { export Rmr64; }\naddr64: [pcRelSimm32]\t\t\t\t\tis mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; }\naddr64: [Base64 + Index64*ss]\t\t\tis mod=0 & r_m=4; Index64 & Base64 & ss { local tmp=Base64+Index64*ss; export tmp; }\naddr64: [Base64]\t\t\t\t\t\tis mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { export Base64; }\naddr64: [simm32_64 + Index64*ss]\t\tis mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64 { local tmp=simm32_64+Index64*ss; export tmp; }\naddr64: [Index64*ss]\t\t\t\t\tis mod=0 & r_m=4; Index64 & base64=5 & ss; imm32=0 { local tmp=Index64*ss; export tmp; }\naddr64: [simm32_64]\t\t\t\t\t\tis mod=0 & r_m=4; rexXprefix=0 & index64=4 & base64=5; simm32_64 { export *[const]:8 simm32_64; }\naddr64: [Base64 + simm8_64]\t\t\t\tis mod=1 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm8_64 { local tmp=simm8_64+Base64; export tmp; }\naddr64: [Base64 + Index64*ss + simm8_64] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8_64 { local tmp=simm8_64+Base64+Index64*ss; export tmp; }\naddr64: [Base64 + Index64*ss]\t\t\tis mod=1 & r_m=4; Index64 & Base64 & ss; simm8=0 { local tmp=Base64+Index64*ss; export tmp; }\naddr64: [Base64 + simm32_64]\t\t\tis mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm32_64 { local tmp=simm32_64+Base64; export tmp; }\naddr64: [Base64]\t\t\t\t\t\tis mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0 { export Base64; }\naddr64: [Base64 + Index64*ss + simm32_64] is mod=2 & r_m=4; Index64 & Base64 & ss; simm32_64 { local tmp=simm32_64+Base64+Index64*ss; export tmp; }\naddr64: [Base64 + Index64*ss]\t\t\tis mod=2 & r_m=4; Index64 & Base64 & ss; imm32=0 { local tmp=Base64+Index64*ss; export tmp; }\n@endif\n\ncurrentCS: CS is protectedMode=0 & CS { tmp:4 = (inst_next >> 4) & 0xf000; CS = tmp:2; export CS; }\ncurrentCS: CS is protectedMode=1 & CS { tmp:4 = (inst_next >> 16) & 0xffff; CS = tmp:2; export CS; }\n \nsegWide: is segover=0\t\t { export 0:$(SIZE); }\nsegWide: CS: is segover=1 & CS\t{ export 0:$(SIZE); }\nsegWide: SS: is segover=2 & SS\t{ export 0:$(SIZE); }\nsegWide: DS: is segover=3 & DS\t{ export 0:$(SIZE); }\nsegWide: ES: is segover=4 & ES\t{ export 0:$(SIZE); }\nsegWide: FS: is segover=5 & FS\t{ export FS_OFFSET; }\nsegWide: GS: is segover=6 & GS\t{ export GS_OFFSET; }\n\nseg16: \t is segover=0\t\t\t{ export DS; }\nseg16: currentCS: is segover=1 & currentCS\t{ export currentCS; }\nseg16: SS: is segover=2 & SS\t{ export SS; }\nseg16: DS: is segover=3 & DS\t{ export DS; }\nseg16: ES: is segover=4 & ES\t{ export ES; }\nseg16: FS: is segover=5 & FS\t{ export FS; }\nseg16: GS: is segover=6 & GS\t{ export GS; }\n\nMem16: addr16\tis (segover=0 & mod=0 & r_m=2) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16\tis (segover=0 & mod=0 & r_m=3) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16\tis (segover=0 & mod=1 & r_m=2) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16\tis (segover=0 & mod=1 & r_m=3) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16 \tis (segover=0 & mod=1 & r_m=6) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16 is (segover=0 & mod=2 & r_m=2) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16 is (segover=0 & mod=2 & r_m=3) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: addr16 \tis (segover=0 & mod=2 & r_m=6) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; }\nMem16: seg16^addr16\tis seg16; addr16\t\t\t\t\t\t\t \t { tmp:$(SIZE) = segment(seg16,addr16); export tmp; }\n\nMem: Mem16 is addrsize=0 & Mem16 { export Mem16; }\n\n@ifdef IA64\nMem: segWide^Addr32_64 is $(LONGMODE_ON) & addrsize=1 & segWide; Addr32_64 \t\t\t{ export Addr32_64; }\nMem: segWide^Addr32_64 is $(LONGMODE_ON) & addrsize=1 & segWide & highseg=1; Addr32_64\t{ tmp:8 = segWide + Addr32_64; export tmp; }\nMem: segWide^addr64 is $(LONGMODE_ON) & addrsize=2 & segWide; addr64 { export addr64; }\nMem: segWide^addr64 is $(LONGMODE_ON) & addrsize=2 & segWide & highseg=1; addr64 { tmp:$(SIZE) = segWide + addr64; export tmp; }\nMem: segWide^addr32 is $(LONGMODE_OFF) & addrsize=1 & segWide; addr32 \t\t{ tmp:$(SIZE) = zext(addr32); export tmp; }\n@else\nMem: segWide^addr32 is $(LONGMODE_OFF) & addrsize=1 & segWide; addr32 \t\t{ export addr32; }\n@endif\nMem: segWide^addr32 is $(LONGMODE_OFF) & addrsize=1 & segWide & highseg=1; addr32 \t{ tmp:$(SIZE) = segWide + zext(addr32); export tmp; }\n\nrel8: reloc is simm8 [ reloc=inst_next+simm8; ] { export *[ram]:$(SIZE) reloc; }\nrel16: reloc is simm16 [ reloc=((inst_next >> 16) << 16) | ((inst_next + simm16) & 0xFFFF); ] { export *[ram]:$(SIZE) reloc; }\nrel32: reloc is simm32 [ reloc=inst_next+simm32; ] { export *[ram]:$(SIZE) reloc; }\n\n\nm8: \"byte ptr\" Mem \tis Mem { export *:1 Mem; }\nm16: \"word ptr\" Mem \tis Mem { export *:2 Mem; }\nm32: \"dword ptr\" Mem \tis Mem { export *:4 Mem; }\nm64: \"qword ptr\" Mem \tis Mem { export *:8 Mem; }\nm80: \"tword ptr\" Mem is Mem { export *:10 Mem; }\nm128: \"xmmword ptr\" Mem\tis Mem { export *:16 Mem; }\nm256: \"ymmword ptr\" Mem\tis Mem { export *:32 Mem; }\nm512: \"zmmword ptr\" Mem is Mem { export *:64 Mem; }\n\nm32fp: \"float ptr\" Mem is Mem { export *:4 Mem; }\nm64fp: \"double ptr\" Mem is Mem { export *:8 Mem; }\nm80fp: \"extended double ptr\" Mem is Mem { export *:10 Mem; }\n\n##\n## VSIB\n##\n\nvaddr32x: [Base + Xmm_vsib*ss]\t\t\t\t\tis mod=0 & r_m=4; Xmm_vsib & Base & ss\t\t\t\t\t{ local tmp=zext(Base)+Xmm_vsib*ss; export tmp; }\nvaddr32x: [Xmm_vsib*ss + simm32_32]\t\t\t\tis mod=0 & r_m=4; Xmm_vsib & base=5 & ss;\tsimm32_32\t{ local tmp=zext(simm32_32)+Xmm_vsib*ss; export tmp; }\nvaddr32x: [Base + Xmm_vsib*ss + simm8_32]\t\tis mod=1 & r_m=4; Xmm_vsib & Base & ss;\t\tsimm8_32\t{ local tmp=zext(Base)+zext(simm8_32)+Xmm_vsib*ss; export tmp; }\nvaddr32x: [Base + Xmm_vsib*ss + simm32_32]\t\tis mod=2 & r_m=4; Xmm_vsib & Base & ss;\t\tsimm32_32\t{ local tmp=zext(Base)+zext(simm32_32)+Xmm_vsib*ss; export tmp; }\n\nvaddr32y: [Base + Ymm_vsib*ss]\t\t\t\t\tis mod=0 & r_m=4; Ymm_vsib & Base & ss\t\t\t\t\t{ local tmp=zext(Base)+Ymm_vsib*ss; export tmp; }\nvaddr32y: [Ymm_vsib*ss + simm32_32]\t\t\t\tis mod=0 & r_m=4; Ymm_vsib & base=5 & ss;\tsimm32_32\t{ local tmp=zext(simm32_32)+Ymm_vsib*ss; export tmp; }\nvaddr32y: [Base + Ymm_vsib*ss + simm8_32]\t\tis mod=1 & r_m=4; Ymm_vsib & Base & ss;\t\tsimm8_32\t{ local tmp=zext(Base)+zext(simm8_32)+Ymm_vsib*ss; export tmp; }\nvaddr32y: [Base + Ymm_vsib*ss + simm32_32]\t\tis mod=2 & r_m=4; Ymm_vsib & Base & ss;\t\tsimm32_32\t{ local tmp=zext(Base)+zext(simm32_32)+Ymm_vsib*ss; export tmp; }\n\nvaddr32z: [Base + Zmm_vsib*ss]\t\t\t\t\tis mod=0 & r_m=4; Zmm_vsib & Base & ss\t\t\t\t\t{ local tmp=zext(Base)+Zmm_vsib*ss; export tmp; }\nvaddr32z: [Zmm_vsib*ss + simm32_32]\t\t\t\tis mod=0 & r_m=4; Zmm_vsib & base=5 & ss;\tsimm32_32\t{ local tmp=zext(simm32_32)+Zmm_vsib*ss; export tmp; }\nvaddr32z: [Base + Zmm_vsib*ss + simm8_32]\t\tis mod=1 & r_m=4; Zmm_vsib & Base & ss;\t\tsimm8_32\t{ local tmp=zext(Base)+zext(simm8_32)+Zmm_vsib*ss; export tmp; }\nvaddr32z: [Base + Zmm_vsib*ss + simm32_32]\t\tis mod=2 & r_m=4; Zmm_vsib & Base & ss;\t\tsimm32_32\t{ local tmp=zext(Base)+zext(simm32_32)+Zmm_vsib*ss; export tmp; }\n\n@ifdef IA64\nvaddr64x: [Base64 + Xmm_vsib*ss]\t\t\t\tis mod=0 & r_m=4; Xmm_vsib & Base64 & ss\t\t\t\t{ local tmp=zext(Base64)+Xmm_vsib*ss; export tmp; }\nvaddr64x: [Xmm_vsib*ss + simm32_64]\t\t\t\tis mod=0 & r_m=4; Xmm_vsib & base64=5 & ss;\tsimm32_64\t{ local tmp=zext(simm32_64)+Xmm_vsib*ss; export tmp; }\nvaddr64x: [Base64 + Xmm_vsib*ss + simm8_64]\t\tis mod=1 & r_m=4; Xmm_vsib & Base64 & ss;\tsimm8_64\t{ local tmp=zext(Base64)+zext(simm8_64)+Xmm_vsib*ss; export tmp; }\nvaddr64x: [Base64 + Xmm_vsib*ss + simm32_64]\tis mod=2 & r_m=4; Xmm_vsib & Base64 & ss;\tsimm32_64\t{ local tmp=zext(Base64)+zext(simm32_64)+Xmm_vsib*ss; export tmp; }\n\nvaddr64y: [Base64 + Ymm_vsib*ss]\t\t\t\tis mod=0 & r_m=4; Ymm_vsib & Base64 & ss\t\t\t\t{ local tmp=zext(Base64)+Ymm_vsib*ss; export tmp; }\nvaddr64y: [Ymm_vsib*ss + simm32_64]\t\t\t\tis mod=0 & r_m=4; Ymm_vsib & base64=5 & ss;\tsimm32_64\t{ local tmp=zext(simm32_64)+Ymm_vsib*ss; export tmp; }\nvaddr64y: [Base64 + Ymm_vsib*ss + simm8_64]\t\tis mod=1 & r_m=4; Ymm_vsib & Base64 & ss;\tsimm8_64\t{ local tmp=zext(Base64)+zext(simm8_64)+Ymm_vsib*ss; export tmp; }\nvaddr64y: [Base64 + Ymm_vsib*ss + simm32_64]\tis mod=2 & r_m=4; Ymm_vsib & Base64 & ss;\tsimm32_64\t{ local tmp=zext(Base64)+zext(simm32_64)+Ymm_vsib*ss; export tmp; }\n\nvaddr64z: [Base64 + Zmm_vsib*ss]\t\t\t\tis mod=0 & r_m=4; Zmm_vsib & Base64 & ss\t\t\t\t{ local tmp=zext(Base64)+Zmm_vsib*ss; export tmp; }\nvaddr64z: [Zmm_vsib*ss + simm32_64]\t\t\t\tis mod=0 & r_m=4; Zmm_vsib & base64=5 & ss;\tsimm32_64\t{ local tmp=zext(simm32_64)+Zmm_vsib*ss; export tmp; }\nvaddr64z: [Base64 + Zmm_vsib*ss + simm8_64]\t\tis mod=1 & r_m=4; Zmm_vsib & Base64 & ss;\tsimm8_64\t{ local tmp=zext(Base64)+zext(simm8_64)+Zmm_vsib*ss; export tmp; }\nvaddr64z: [Base64 + Zmm_vsib*ss + simm32_64]\tis mod=2 & r_m=4; Zmm_vsib & Base64 & ss;\tsimm32_64\t{ local tmp=zext(Base64)+zext(simm32_64)+Zmm_vsib*ss; export tmp; }\n@endif\n\n\nvMem32x: segWide^vaddr32x\tis addrsize=1 & segWide; vaddr32x\t\t\t\t\t{ export vaddr32x; }\nvMem32x: segWide^vaddr32x\tis addrsize=1 & segWide & highseg=1; vaddr32x\t\t{ export vaddr32x; }\n\nvMem32y: segWide^vaddr32y\tis addrsize=1 & segWide; vaddr32y\t\t\t\t\t{ export vaddr32y; }\nvMem32y: segWide^vaddr32y\tis addrsize=1 & segWide & highseg=1; vaddr32y\t\t{ export vaddr32y; }\n\nvMem32z: segWide^vaddr32z\tis addrsize=1 & segWide; vaddr32z\t\t\t\t\t{ export vaddr32z; }\nvMem32z: segWide^vaddr32z\tis addrsize=1 & segWide & highseg=1; vaddr32z \t\t{ export vaddr32z; }\n\n@ifdef IA64\n# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base.\n# Behavior is coded to match Binutils; exceeds what the manual indicates is possible.\nvMem32x: segWide^vaddr64x\tis addrsize=2 & segWide; vaddr64x \t\t{ export vaddr64x; }\nvMem32x: segWide^vaddr64x\tis addrsize=2 & segWide & highseg=1; vaddr64x \t\t{ export vaddr64x; }\n\n# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base.\n# Behavior is coded to match Binutils; exceeds what the manual indicates is possible.\nvMem32y: segWide^vaddr64y\tis addrsize=2 & segWide; vaddr64y \t\t{ export vaddr64y; }\nvMem32y: segWide^vaddr64y\tis addrsize=2 & segWide & highseg=1; vaddr64y \t\t{ export vaddr64y; }\n\n# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base.\n# Behavior is coded to match Binutils; exceeds what the manual indicates is possible.\nvMem32z: segWide^vaddr64z\tis addrsize=2 & segWide; vaddr64z \t\t{ export vaddr64z; }\nvMem32z: segWide^vaddr64z\tis addrsize=2 & segWide & highseg=1; vaddr64z \t\t{ export vaddr64z;}\n\n# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base.\n# Behavior is coded to match Binutils; exceeds what the manual indicates is possible.\nvMem64x: segWide^vaddr32x\tis addrsize=1 & segWide; vaddr32x \t\t\t\t\t{ export vaddr32x; }\nvMem64x: segWide^vaddr32x\tis addrsize=1 & segWide & highseg=1; vaddr32x\t\t{ export vaddr32x; }\n\nvMem64x: segWide^vaddr64x\tis addrsize=2 & segWide; vaddr64x \t\t{ export vaddr64x; }\nvMem64x: segWide^vaddr64x\tis addrsize=2 & segWide & highseg=1; vaddr64x \t\t{ export vaddr64x; }\n\n# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base.\n# Behavior is coded to match Binutils; exceeds what the manual indicates is possible.\nvMem64y: segWide^vaddr32y\tis addrsize=1 & segWide; vaddr32y \t\t\t\t\t{ export vaddr32y; }\nvMem64y: segWide^vaddr32y\tis addrsize=1 & segWide & highseg=1; vaddr32y\t\t{ export vaddr32y; }\n\nvMem64y: segWide^vaddr64y\tis addrsize=2 & segWide; vaddr64y \t\t{ export vaddr64y; }\nvMem64y: segWide^vaddr64y\tis addrsize=2 & segWide & highseg=1; vaddr64y \t\t{ export vaddr64y; }\n\n# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base.\n# Behavior is coded to match Binutils; exceeds what the manual indicates is possible.\nvMem64z: segWide^vaddr32z\tis addrsize=1 & segWide; vaddr32z \t\t\t\t\t{ export vaddr32z; }\nvMem64z: segWide^vaddr32z\tis addrsize=1 & segWide & highseg=1; vaddr32z\t\t{ export vaddr32z; }\n\nvMem64z: segWide^vaddr64z\tis addrsize=2 & segWide; vaddr64z \t\t{ export vaddr64z; }\nvMem64z: segWide^vaddr64z\tis addrsize=2 & segWide & highseg=1; vaddr64z \t\t{ export vaddr64z; }\n@endif\n\n\nd_vm32x: \"dword ptr \"^vMem32x is vMem32x { }\nd_vm32y: \"dword ptr \"^vMem32y is vMem32y { }\n# not used d_vm32z: \"dword ptr \"^vMem32z is vMem32z { }\n\n@ifdef IA64\nd_vm64x: \"dword ptr \"^vMem64x is vMem64x { }\nd_vm64y: \"dword ptr \"^vMem64y is vMem64y { }\n# not used d_vm64z: \"dword ptr \"^vMem64z is vMem64z { }\n@endif\n\n\nq_vm32x: \"qword ptr \"^vMem32x is vMem32x { export vMem32x; }\n# not used q_vm32y: \"qword ptr \"^vMem32y is vMem32y { }\n# not used q_vm32z: \"qword ptr \"^vMem32z is vMem32z { }\n\n@ifdef IA64\nq_vm64x: \"qword ptr \"^vMem64x is vMem64x { export vMem64x; }\nq_vm64y: \"qword ptr \"^vMem64y is vMem64y { export vMem64y; }\nq_vm64z: \"qword ptr \"^vMem64z is vMem64z { export vMem64z; }\n@endif\n\nx_vm32x: \"xmmword ptr \"^vMem32x is vMem32x { export vMem32x; }\ny_vm32y: \"ymmword ptr \"^vMem32y is vMem32y { export vMem32y; }\nz_vm32z: \"zmmword ptr \"^vMem32z is vMem32z { export vMem32z; }\n\n@ifdef IA64\nx_vm64x: \"xmmword ptr \"^vMem64x is vMem64x { export vMem64x; }\ny_vm64y: \"ymmword ptr \"^vMem64y is vMem64y { export vMem64y; }\nz_vm64z: \"zmmword ptr \"^vMem64z is vMem64z { export vMem64z; }\n@endif\n\nReg32_m8: Rmr32 is mod=3 & Rmr32 { export Rmr32; }\nReg32_m8: m8 is m8 { local tmp:4 = zext(m8); export tmp; }\nReg32_m16: Rmr32 is mod=3 & Rmr32 { export Rmr32; }\nReg32_m16: m16 is m16 { local tmp:4 = zext(m16); export tmp; }\n\nmmxreg2_m64: mmxreg2 is mod=3 & mmxreg2 { export mmxreg2; }\nmmxreg2_m64: m64 is m64 { export m64; }\n\nXmmReg2_m8: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m8: m8 is m8 { local tmp:16 = zext(m8); export tmp; }\nXmmReg2_m16: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m16: m16 is m16 { local tmp:16 = zext(m16); export tmp; }\nXmmReg2_m32: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m32: m32 is m32 { local tmp:16 = zext(m32); export tmp; }\nXmmReg2_m64: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m64: m64 is m64 { local tmp:16 = zext(m64); export tmp; }\nXmmReg2_m128: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m128: m128 is m128 { export m128; }\n\nYmmReg2_m256: YmmReg2 is mod=3 & YmmReg2 { export YmmReg2; }\nYmmReg2_m256: m256 is m256 { export m256; }\n\nZmmReg2_m512: ZmmReg2 is mod=3 & ZmmReg2 { export ZmmReg2; }\nZmmReg2_m512: m512 is m512 { export m512; }\n\n# used to extend ZmmReg2 if not assigning to m128\nXmmReg2_m128_extend: XmmReg2 is mod=3 & XmmReg2 & ZmmReg2 { ZmmReg2 = zext(XmmReg2); }\nXmmReg2_m128_extend: XmmReg2 is mod & XmmReg2 { }\n\nm16bcst32: m16 is m16 { local tmp:2 = m16; BCST4[0,16] = tmp; BCST4[16,16] = tmp; export BCST4; }\n\nm16bcst64: m16 is m16 { local tmp:2 = m16; BCST8[0,16] = tmp; BCST8[16,16] = tmp; BCST8[32,16] = tmp; BCST8[48,16] = tmp; export BCST8; }\nm16bcst128: m16 is m16 {\n\tlocal tmp:2 = m16;\n\tBCST16[0,16] = tmp; BCST16[16,16] = tmp; BCST16[32,16] = tmp; BCST16[48,16] = tmp;\n\tBCST16[64,16] = tmp; BCST16[80,16] = tmp; BCST16[96,16] = tmp; BCST16[112,16] = tmp;\n\texport BCST16;\n}\nm16bcst256: m16 is m16 {\n\tlocal tmp:2 = m16;\n\tBCST32[0,16] = tmp; BCST32[16,16] = tmp; BCST32[32,16] = tmp; BCST32[48,16] = tmp;\n\tBCST32[64,16] = tmp; BCST32[80,16] = tmp; BCST32[96,16] = tmp; BCST32[112,16] = tmp;\n\tBCST32[128,16] = tmp; BCST32[144,16] = tmp; BCST32[160,16] = tmp; BCST32[176,16] = tmp;\n\tBCST32[192,16] = tmp; BCST32[208,16] = tmp; BCST32[224,16] = tmp; BCST32[240,16] = tmp;\n\texport BCST32;\n}\nm16bcst512: m16 is m16 {\n\tlocal tmp:2 = m16;\n\tBCST64[0,16] = tmp; BCST64[16,16] = tmp; BCST64[32,16] = tmp; BCST64[48,16] = tmp;\n\tBCST64[64,16] = tmp; BCST64[80,16] = tmp; BCST64[96,16] = tmp; BCST64[112,16] = tmp;\n\tBCST64[128,16] = tmp; BCST64[144,16] = tmp; BCST64[160,16] = tmp; BCST64[176,16] = tmp;\n\tBCST64[192,16] = tmp; BCST64[208,16] = tmp; BCST64[224,16] = tmp; BCST64[240,16] = tmp;\n\tBCST64[256,16] = tmp; BCST64[272,16] = tmp; BCST64[288,16] = tmp; BCST64[304,16] = tmp;\n\tBCST64[320,16] = tmp; BCST64[336,16] = tmp; BCST64[352,16] = tmp; BCST64[368,16] = tmp;\n\tBCST64[384,16] = tmp; BCST64[400,16] = tmp; BCST64[416,16] = tmp; BCST64[432,16] = tmp;\n\tBCST64[448,16] = tmp; BCST64[464,16] = tmp; BCST64[480,16] = tmp; BCST64[496,16] = tmp;\n\texport BCST64;\n}\n\nm32bcst64: m32 is m32 { local tmp:4 = m32; BCST8[0,32] = tmp; BCST8[32,32] = tmp; export BCST8; }\nm32bcst128: m32 is m32 { local tmp:4 = m32; BCST16[0,32] = tmp; BCST16[32,32] = tmp; BCST16[64,32] = tmp; BCST16[96,32] = tmp; export BCST16; }\nm32bcst256: m32 is m32 {\n\tlocal tmp:4 = m32;\n\tBCST32[0,32] = tmp; BCST32[32,32] = tmp; BCST32[64,32] = tmp; BCST32[96,32] = tmp;\n\tBCST32[128,32] = tmp; BCST32[160,32] = tmp; BCST32[192,32] = tmp; BCST32[224,32] = tmp;\n\texport BCST32;\n}\nm32bcst512: m32 is m32 {\n\tlocal tmp:4 = m32;\n\tBCST64[0,32] = tmp; BCST64[32,32] = tmp; BCST64[64,32] = tmp; BCST64[96,32] = tmp;\n\tBCST64[128,32] = tmp; BCST64[160,32] = tmp; BCST64[192,32] = tmp; BCST64[224,32] = tmp;\n\tBCST64[256,32] = tmp; BCST64[288,32] = tmp; BCST64[320,32] = tmp; BCST64[352,32] = tmp;\n\tBCST64[384,32] = tmp; BCST64[416,32] = tmp; BCST64[448,32] = tmp; BCST64[480,32] = tmp;\n\texport BCST64;\n}\n\nm64bcst128: m64 is m64 { local tmp:8 = m64; BCST16[0,64] = tmp; BCST16[64,64] = tmp; export BCST16; }\nm64bcst256: m64 is m64 { local tmp:8 = m64; BCST32[0,64] = tmp; BCST32[64,64] = tmp; BCST32[128,64] = tmp; BCST32[192,64] = tmp; export BCST32; }\nm64bcst512: m64 is m64 {\n\tlocal tmp:8 = m64;\n\tBCST64[0,64] = tmp; BCST64[64,64] = tmp; BCST64[128,64] = tmp; BCST64[192,64] = tmp;\n\tBCST64[256,64] = tmp; BCST64[320,64] = tmp; BCST64[384,64] = tmp; BCST64[448,64] = tmp;\n\texport BCST64;\n}\n\nXmmReg2_m32_m16bcst: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m32_m16bcst: m32 is m32 & evexDisp8N { local tmp:16 = zext(m32); export tmp; }\nXmmReg2_m32_m16bcst: m16bcst32 is evexB=1 & m16bcst32 & evexDisp8N { local tmp:16 = zext(m16bcst32); export tmp; }\n\nXmmReg2_m64_m16bcst: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m64_m16bcst: m64 is m64 & evexDisp8N { local tmp:16 = zext(m64); export tmp; }\nXmmReg2_m64_m16bcst: m16bcst64 is evexB=1 & m16bcst64 & evexDisp8N { local tmp:16 = zext(m16bcst64); export tmp; }\n\nXmmReg2_m64_m32bcst: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m64_m32bcst: m64 is m64 & evexDisp8N { local tmp:16 = zext(m64); export tmp; }\nXmmReg2_m64_m32bcst: m32bcst64 is evexB=1 & m32bcst64 & evexDisp8N { local tmp:16 = zext(m32bcst64); export tmp; }\n\nXmmReg2_m128_m16bcst: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m128_m16bcst: m128 is m128& evexDisp8N { export m128; }\nXmmReg2_m128_m16bcst: m16bcst128 is evexB=1 & m16bcst128 & evexDisp8N { export m16bcst128; }\n\nXmmReg2_m128_m32bcst: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m128_m32bcst: m128 is m128& evexDisp8N { export m128; }\nXmmReg2_m128_m32bcst: m32bcst128 is evexB=1 & m32bcst128 & evexDisp8N { export m32bcst128; }\n\nXmmReg2_m128_m64bcst: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; }\nXmmReg2_m128_m64bcst: m128 is m128 & evexDisp8N { export m128; }\nXmmReg2_m128_m64bcst: m64bcst128 is evexB=1 & m64bcst128 & evexDisp8N { export m64bcst128; }\n\nYmmReg2_m256_m16bcst: YmmReg2 is mod=3 & YmmReg2 { export YmmReg2; }\nYmmReg2_m256_m16bcst: m256 is m256 & evexDisp8N { export m256; }\nYmmReg2_m256_m16bcst: m16bcst256 is evexB=1 & m16bcst256 & evexDisp8N { export m16bcst256; }\n\nYmmReg2_m256_m32bcst: YmmReg2 is mod=3 & YmmReg2 { export YmmReg2; }\nYmmReg2_m256_m32bcst: m256 is m256 & evexDisp8N { export m256; }\nYmmReg2_m256_m32bcst: m32bcst256 is evexB=1 & m32bcst256 & evexDisp8N { export m32bcst256; }\n\nYmmReg2_m256_m64bcst: YmmReg2 is mod=3 & YmmReg2 { export YmmReg2; }\nYmmReg2_m256_m64bcst: m256 is m256 & evexDisp8N { export m256; }\nYmmReg2_m256_m64bcst: m64bcst256 is evexB=1 & m64bcst256 & evexDisp8N { export m64bcst256; }\n\nZmmReg2_m512_m16bcst: ZmmReg2 is mod=3 & ZmmReg2 { export ZmmReg2; }\nZmmReg2_m512_m16bcst: m512 is m512 & evexDisp8N { export m512; }\nZmmReg2_m512_m16bcst: m16bcst512 is evexB=1 & m16bcst512 & evexDisp8N { export m16bcst512; }\n\nZmmReg2_m512_m32bcst: ZmmReg2 is mod=3 & ZmmReg2 { export ZmmReg2; }\nZmmReg2_m512_m32bcst: m512 is m512 & evexDisp8N { export m512; }\nZmmReg2_m512_m32bcst: m32bcst512 is evexB=1 & m32bcst512 & evexDisp8N { export m32bcst512; }\n\nZmmReg2_m512_m64bcst: ZmmReg2 is mod=3 & ZmmReg2 { export ZmmReg2; }\nZmmReg2_m512_m64bcst: m512 is m512 & evexDisp8N { export m512; }\nZmmReg2_m512_m64bcst: m64bcst512 is evexB=1 & m64bcst512 & evexDisp8N { export m64bcst512; }\n\nmoffs8: seg16^[imm16] is addrsize=0 & seg16 & imm16 { tmp:$(SIZE) = segment(seg16,imm16:2); export *:1 tmp; }\nmoffs8: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:$(SIZE) = segWide + imm32; export *:1 tmp; }\nmoffs8: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:1 imm32; }\n@ifdef IA64\nmoffs8: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:1 tmp; }\nmoffs8: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:1 imm64; }\n@endif\nmoffs16: seg16^[imm16] is addrsize=0 & seg16 & imm16 { tmp:$(SIZE) = segment(seg16,imm16:2); export *:2 tmp; }\nmoffs16: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:$(SIZE) = segWide + imm32; export *:2 tmp; }\nmoffs16: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:2 imm32; }\n@ifdef IA64\nmoffs16: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:2 tmp; }\nmoffs16: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:2 imm64; }\n@endif\n\nmoffs32: seg16^[imm16] is addrsize=0 & seg16 & imm16 { tmp:$(SIZE) = segment(seg16,imm16:2); export *:4 tmp; }\nmoffs32: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:4 imm32; }\nmoffs32: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:$(SIZE) = segWide + imm32; export *:4 tmp; }\n@ifdef IA64\nmoffs32: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:4 imm64; }\nmoffs32: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:4 tmp; }\n@endif\n\n@ifdef IA64\nmoffs64: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:8 imm64; }\nmoffs64: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:8 tmp; }\nmoffs64: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:8 imm32; }\nmoffs64: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:8 = segWide + imm32; export *:8 tmp; }\n@endif\n# TODO: segment register offset in 64bit might not be right\n\n# String memory access\ndseSI1: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 1-2*zext(DF); export *:1 tmp; }\ndseSI1: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 1-2*zext(DF); export *:1 tmp; }\ndseSI2: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 2-4*zext(DF); export *:2 tmp; }\ndseSI2: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 2-4*zext(DF); export *:2 tmp; }\ndseSI4: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 4-8*zext(DF); export *:4 tmp; }\ndseSI4: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 4-8*zext(DF); export *:4 tmp; }\neseDI1: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 1-2*zext(DF); export *:1 tmp; }\neseDI1: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+1-2*zext(DF); export *:1 tmp; }\neseDI2: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 2-4*zext(DF); export *:2 tmp; }\neseDI2: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+2-4*zext(DF); export *:2 tmp; }\neseDI4: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 4-8*zext(DF); export *:4 tmp; }\neseDI4: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+4-8*zext(DF); export *:4 tmp; }\n\n@ifdef IA64\n# quadword string functions\ndseSI8: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 8-16*zext(DF); export *:8 tmp; }\ndseSI8: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 8-16*zext(DF); export *:8 tmp; }\neseDI8: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 8-16*zext(DF); export *:8 tmp; }\neseDI8: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+8-16*zext(DF); export *:8 tmp; }\n\ndseSI1: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 1-2*zext(DF); export *:1 tmp; }\ndseSI2: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 2-4*zext(DF); export *:2 tmp; }\ndseSI4: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 4-8*zext(DF); export *:4 tmp; }\ndseSI8: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 8-16*zext(DF); export *:8 tmp; }\neseDI1: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+1-2*zext(DF); export *:1 tmp; }\neseDI2: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+2-4*zext(DF); export *:2 tmp; }\neseDI4: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+4-8*zext(DF); export *:4 tmp; }\neseDI8: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+8-16*zext(DF); export *:8 tmp; }\n@endif\n\nrm8: Rmr8 is mod=3 & Rmr8 { export Rmr8; }\nrm8: \"byte ptr\" Mem is Mem { export *:1 Mem; }\n\nrm16: Rmr16 is mod=3 & Rmr16 { export Rmr16; }\nrm16: \"word ptr\" Mem is Mem { export *:2 Mem; }\n\nrm32: Rmr32 is mod=3 & Rmr32 { export Rmr32; }\nrm32: \"dword ptr\" Mem is Mem { export *:4 Mem; }\n\n@ifdef IA64\nrm64: Rmr64 is mod=3 & Rmr64 { export Rmr64; }\nrm64: \"qword ptr\" Mem is Mem { export *:8 Mem; }\n@endif\n\nn1: one\tis epsilon\t\t\t[ one = 1; ] { export *[const]:1 one; }\n\n@ifdef IA64\n# Handle zero extension in 64-bit mode for 32-bit destination registers\ncheck_Reg32_dest:\tis rexRprefix=0 & reg32 & reg64\t{ reg64 = zext(reg32); }\t\ncheck_Reg32_dest:\tis rexRprefix=1 & reg32_x & reg64_x\t{ reg64_x = zext(reg32_x); }\ncheck_Rmr32_dest:\tis rexBprefix=0 & r32 & r64\t\t{ r64 = zext(r32); }\ncheck_Rmr32_dest:\tis rexBprefix=1 & r32_x & r64_x \t{ r64_x = zext(r32_x); }\ncheck_rm32_dest:\tis mod=3 & check_Rmr32_dest\t\t{ build check_Rmr32_dest; }\ncheck_EAX_dest:\t\tis epsilon\t\t\t\t\t\t\t\t\t{ RAX = zext(EAX); }\ncheck_EDX_dest: is epsilon { RDX = zext(EDX); } \ncheck_vexVVVV_r32_dest: is bit64=1 & vexVVVV_r64 & vexVVVV_r32 { vexVVVV_r64 = zext(vexVVVV_r32);}\n@else \ncheck_Reg32_dest:\tis epsilon\t{ }\ncheck_Rmr32_dest:\tis epsilon\t{ }\ncheck_EAX_dest:\t\tis epsilon { }\ncheck_EDX_dest:\t\tis epsilon { }\ncheck_vexVVVV_r32_dest: is epsilon { }\n@endif\ncheck_rm32_dest:\tis epsilon\t{ }\n\n\nptr1616: reloc is protectedMode=0 & imm16; j16\t\t[ reloc = j16*0x10 + imm16; ] { CS = j16; export *[ram]:4 reloc; }\nptr1616: reloc is protectedMode=1 & imm16; j16\t\t[ reloc = j16*0x10000 + imm16; ] { CS = j16; export *[ram]:4 reloc; }\nptr1632: j16\":\"imm32 is imm32; j16\t{ CS = j16; export *:4 imm32; }\n\n# conditions\n\ncc: \"O\" is cond=0 { export OF; }\ncc: \"NO\" is cond=1 { local tmp = !OF; export tmp; }\ncc: \"C\" is cond=2 { export CF; }\ncc: \"NC\" is cond=3 { local tmp = !CF; export tmp; }\ncc: \"Z\" is cond=4 { export ZF; }\ncc: \"NZ\" is cond=5 { local tmp = !ZF; export tmp; }\ncc: \"BE\" is cond=6 { local tmp = CF || ZF; export tmp; }\ncc: \"A\" is cond=7 { local tmp = !(CF || ZF); export tmp; }\ncc: \"S\" is cond=8 { export SF; }\ncc: \"NS\" is cond=9 { local tmp = !SF; export tmp; }\ncc: \"P\" is cond=10 { export PF; }\ncc: \"NP\" is cond=11 { local tmp = !PF; export tmp; }\ncc: \"L\" is cond=12 { local tmp = OF != SF; export tmp; }\ncc: \"GE\" is cond=13 { local tmp = OF == SF; export tmp; }\ncc: \"LE\" is cond=14 { local tmp = ZF || (OF != SF); export tmp; }\ncc: \"G\" is cond=15 { local tmp = !ZF && (OF == SF); export tmp; }\n\n# repeat prefixes\nrep: \".REP\" is ((repprefx=1 & repneprefx=0)|(repprefx=0 & repneprefx=1)) & addrsize=0 { if (CX==0) goto inst_next; CX=CX-1; }\nrep: \".REP\" is ((repprefx=1 & repneprefx=0)|(repprefx=0 & repneprefx=1)) & addrsize=1 { if (ECX==0) goto inst_next; ECX=ECX-1; }\n@ifdef IA64\nrep: \".REP\" is ((repprefx=1 & repneprefx=0)|(repprefx=0 & repneprefx=1)) & addrsize=2 { if (RCX==0) goto inst_next; RCX=RCX-1; }\n@endif\nrep: is repprefx=0 & repneprefx=0\t\t\t{ }\n\nreptail:\tis ((repprefx=1 & repneprefx=0)|(repprefx=0 & repneprefx=1))\t\t\t{ goto inst_start; }\nreptail:\tis repprefx=0 & repneprefx=0\t\t\t{ }\n\nrepe: \".REPE\" is repprefx=1 & repneprefx=0 & addrsize=0 { if (CX==0) goto inst_next; CX=CX-1; }\nrepe: \".REPE\" is repprefx=1 & repneprefx=0 & addrsize=1 { if (ECX==0) goto inst_next; ECX=ECX-1; }\n@ifdef IA64\nrepe: \".REPE\" is repprefx=1 & repneprefx=0 & addrsize=2 { if (RCX==0) goto inst_next; RCX=RCX-1; }\n@endif\nrepe: \".REPNE\" is repneprefx=1 & repprefx=0 & addrsize=0 { if (CX==0) goto inst_next; CX=CX-1; }\nrepe: \".REPNE\" is repneprefx=1 & repprefx=0 & addrsize=1 { if (ECX==0) goto inst_next; ECX=ECX-1; }\n@ifdef IA64\nrepe: \".REPNE\" is repneprefx=1 & repprefx=0 & addrsize=2 { if (RCX==0) goto inst_next; RCX=RCX-1; }\n@endif\nrepe: is repprefx=0 & repneprefx=0 { }\n\nrepetail: is repprefx=1 & repneprefx=0 { if (ZF) goto inst_start; }\nrepetail: is repneprefx=1 & repprefx=0 { if (!ZF) goto inst_start; }\nrepetail: is repprefx=0 & repneprefx=0 { }\n\n# XACQUIRE/XRELEASE prefix\nxacq_xrel_prefx: \".XACQUIRE\"\tis xacquireprefx=1 & xreleaseprefx=0 { XACQUIRE(); }\nxacq_xrel_prefx: \".XRELEASE\"\tis xacquireprefx=0 & xreleaseprefx=1 { XRELEASE(); }\nxacq_xrel_prefx: \tis epsilon { }\n\n#the XRELEASE prefix can be used with several variants of MOV (without the LOCK prefix)\nxrelease: \".XRELEASE\"\tis xacquireprefx=0 & xreleaseprefx=1 { XRELEASE(); }\nxrelease: \tis epsilon { }\n\n#XCHG with a memory destination asserts a LOCK signal whether or not there is a LOCK prefix (f0) \n#\"alwaysLock\" constructor will place \"LOCK\" in the disassembly if the prefix occurs \nalwaysLock: \".LOCK\"\tis lockprefx=1 { LOCK(); }\nalwaysLock: \t is epsilon { LOCK(); }\n\n#check for LOCK prefix and the optional XACQUIRE/XRELEASE\nlockx: xacq_xrel_prefx^\".LOCK\"\tis lockprefx=1 & xacq_xrel_prefx { build xacq_xrel_prefx; LOCK(); }\nlockx: \t\t is epsilon { }\n\n#\"unlock\" constructor is used to pair every LOCK pcodeop with a matching UNLOCK pcodeop\nunlock:\t\tis lockprefx=1 { UNLOCK(); }\nunlock:\t\tis epsilon { }\n\nKReg_reg: opmaskreg is opmaskreg { export opmaskreg; }\nKReg_rm: opmaskrm is opmaskrm { export opmaskrm; }\n# not used vexVVVV_KReg: evexVopmask is evexVopmask { export evexVopmask; }\nvex1VVV_KReg: evexVopmask is evexVopmask & vexHighV=0 { export evexVopmask; }\n\nXmmMaskMode: is evexZ=0 { }\nXmmMaskMode: \"{z}\" is evexZ=1 { XmmMask=0; }\n\nYmmMaskMode: is evexZ=0 { }\nYmmMaskMode: \"{z}\" is evexZ=1 { YmmMask=0; }\n\nZmmMaskMode: is evexZ=0 { }\nZmmMaskMode: \"{z}\" is evexZ=1 { ZmmMask=0; }\n\nAVXOpMask: \"{\"^evexOpmask^\"}\" is evexOpmask { export evexOpmask; }\nAVXOpMask: is evexOpmask=0 { local tmp:8 = 0xffffffffffffffff; export *[const]:8 tmp; }\n# Z=0: merge masking\n# Z=1: zero masking\nXmmOpMask: AVXOpMask^XmmMaskMode is AVXOpMask & XmmMaskMode {\n\texport AVXOpMask;\n}\n\nXmmOpMask8: AVXOpMask^XmmMaskMode is AVXOpMask & XmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(XmmResult[0,8], mask[0,1], XmmResult[0,8], XmmMask[0,8]);\n\tconditionalAssign(XmmResult[8,8], mask[1,1],XmmResult[8,8], XmmMask[8,8]);\n\tconditionalAssign(XmmResult[16,8], mask[2,1], XmmResult[16,8], XmmMask[16,8]);\n\tconditionalAssign(XmmResult[24,8], mask[3,1], XmmResult[24,8], XmmMask[24,8]);\n\tconditionalAssign(XmmResult[32,8], mask[4,1], XmmResult[32,8], XmmMask[32,8]);\n\tconditionalAssign(XmmResult[40,8], mask[5,1], XmmResult[40,8], XmmMask[40,8]);\n\tconditionalAssign(XmmResult[48,8], mask[6,1], XmmResult[48,8], XmmMask[48,8]);\n\tconditionalAssign(XmmResult[56,8], mask[7,1], XmmResult[56,8], XmmMask[56,8]);\n\tconditionalAssign(XmmResult[64,8], mask[8,1], XmmResult[64,8], XmmMask[64,8]);\n\tconditionalAssign(XmmResult[72,8], mask[9,1], XmmResult[72,8], XmmMask[72,8]);\n\tconditionalAssign(XmmResult[80,8], mask[10,1], XmmResult[80,8], XmmMask[80,8]);\n\tconditionalAssign(XmmResult[88,8], mask[11,1], XmmResult[88,8], XmmMask[88,8]);\n\tconditionalAssign(XmmResult[96,8], mask[12,1], XmmResult[96,8], XmmMask[96,8]);\n\tconditionalAssign(XmmResult[104,8], mask[13,1], XmmResult[104,8], XmmMask[104,8]);\n\tconditionalAssign(XmmResult[112,8], mask[14,1], XmmResult[112,8], XmmMask[112,8]);\n\tconditionalAssign(XmmResult[120,8], mask[15,1], XmmResult[120,8], XmmMask[120,8]);\n}\n\nXmmOpMask8: is evexOpmask=0 {\n}\n\nXmmOpMask16: AVXOpMask^XmmMaskMode is AVXOpMask & XmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(XmmResult[0,16], mask[0,1], XmmResult[0,16], XmmMask[0,16]);\n\tconditionalAssign(XmmResult[16,16], mask[1,1], XmmResult[16,16], XmmMask[16,16]);\n\tconditionalAssign(XmmResult[32,16], mask[2,1], XmmResult[32,16], XmmMask[32,16]);\n\tconditionalAssign(XmmResult[48,16], mask[3,1], XmmResult[48,16], XmmMask[48,16]);\n\tconditionalAssign(XmmResult[64,16], mask[4,1], XmmResult[64,16], XmmMask[64,16]);\n\tconditionalAssign(XmmResult[80,16], mask[5,1], XmmResult[80,16], XmmMask[80,16]);\n\tconditionalAssign(XmmResult[96,16], mask[6,1], XmmResult[96,16], XmmMask[96,16]);\n\tconditionalAssign(XmmResult[112,16], mask[7,1], XmmResult[112,16], XmmMask[112,16]);\n}\n\nXmmOpMask16: is evexOpmask=0 {\n}\n\n\nXmmOpMask32: AVXOpMask^XmmMaskMode is AVXOpMask & XmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(XmmResult[0,32], mask[0,1], XmmResult[0,32], XmmMask[0,32]);\n\tconditionalAssign(XmmResult[32,32], mask[1,1], XmmResult[32,32], XmmMask[32,32]);\n\tconditionalAssign(XmmResult[64,32], mask[2,1], XmmResult[64,32], XmmMask[64,32]);\n\tconditionalAssign(XmmResult[96,32], mask[3,1], XmmResult[96,32], XmmMask[96,32]);\n}\n\nXmmOpMask32: is evexOpmask=0 {\n}\n\nXmmOpMask64: AVXOpMask^XmmMaskMode is AVXOpMask & XmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(XmmResult[0,64], mask[0,1], XmmResult[0,64], XmmMask[0,64]);\n\tconditionalAssign(XmmResult[64,64], mask[1,1], XmmResult[64,64], XmmMask[64,64]);\n}\n\nXmmOpMask64: is evexOpmask=0 {\n}\n\nYmmOpMask: AVXOpMask^YmmMaskMode is AVXOpMask & YmmMaskMode {\n\texport AVXOpMask;\n}\n\nYmmOpMask8: AVXOpMask^YmmMaskMode is AVXOpMask & YmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(YmmResult[0,8], mask[0,1], YmmResult[0,8], YmmMask[0,8]);\n\tconditionalAssign(YmmResult[8,8], mask[1,1], YmmResult[8,8], YmmMask[8,8]);\n\tconditionalAssign(YmmResult[16,8], mask[2,1], YmmResult[16,8], YmmMask[16,8]);\n\tconditionalAssign(YmmResult[24,8], mask[3,1], YmmResult[24,8], YmmMask[24,8]);\n\tconditionalAssign(YmmResult[32,8], mask[4,1], YmmResult[32,8], YmmMask[32,8]);\n\tconditionalAssign(YmmResult[40,8], mask[5,1], YmmResult[40,8], YmmMask[40,8]);\n\tconditionalAssign(YmmResult[48,8], mask[6,1], YmmResult[48,8], YmmMask[48,8]);\n\tconditionalAssign(YmmResult[56,8], mask[7,1], YmmResult[56,8], YmmMask[56,8]);\n\tconditionalAssign(YmmResult[64,8], mask[8,1], YmmResult[64,8], YmmMask[64,8]);\n\tconditionalAssign(YmmResult[72,8], mask[9,1], YmmResult[72,8], YmmMask[72,8]);\n\tconditionalAssign(YmmResult[80,8], mask[10,1], YmmResult[80,8], YmmMask[80,8]);\n\tconditionalAssign(YmmResult[88,8], mask[11,1], YmmResult[88,8], YmmMask[88,8]);\n\tconditionalAssign(YmmResult[96,8], mask[12,1], YmmResult[96,8], YmmMask[96,8]);\n\tconditionalAssign(YmmResult[104,8], mask[13,1], YmmResult[104,8], YmmMask[104,8]);\n\tconditionalAssign(YmmResult[112,8], mask[14,1], YmmResult[112,8], YmmMask[112,8]);\n\tconditionalAssign(YmmResult[120,8], mask[15,1], YmmResult[120,8], YmmMask[120,8]);\n\tconditionalAssign(YmmResult[128,8], mask[16,1], YmmResult[128,8], YmmMask[128,8]);\n\tconditionalAssign(YmmResult[136,8], mask[17,1], YmmResult[136,8], YmmMask[136,8]);\n\tconditionalAssign(YmmResult[144,8], mask[18,1], YmmResult[144,8], YmmMask[144,8]);\n\tconditionalAssign(YmmResult[152,8], mask[19,1], YmmResult[152,8], YmmMask[152,8]);\n\tconditionalAssign(YmmResult[160,8], mask[20,1], YmmResult[160,8], YmmMask[160,8]);\n\tconditionalAssign(YmmResult[168,8], mask[21,1], YmmResult[168,8], YmmMask[168,8]);\n\tconditionalAssign(YmmResult[176,8], mask[22,1], YmmResult[176,8], YmmMask[176,8]);\n\tconditionalAssign(YmmResult[184,8], mask[23,1], YmmResult[184,8], YmmMask[184,8]);\n\tconditionalAssign(YmmResult[192,8], mask[24,1], YmmResult[192,8], YmmMask[192,8]);\n\tconditionalAssign(YmmResult[200,8], mask[25,1], YmmResult[200,8], YmmMask[200,8]);\n\tconditionalAssign(YmmResult[208,8], mask[26,1], YmmResult[208,8], YmmMask[208,8]);\n\tconditionalAssign(YmmResult[216,8], mask[27,1], YmmResult[216,8], YmmMask[216,8]);\n\tconditionalAssign(YmmResult[224,8], mask[28,1], YmmResult[224,8], YmmMask[224,8]);\n\tconditionalAssign(YmmResult[232,8], mask[29,1], YmmResult[232,8], YmmMask[232,8]);\n}\n\nYmmOpMask8: is evexOpmask=0 {\n}\n\nYmmOpMask16: AVXOpMask^YmmMaskMode is AVXOpMask & YmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(YmmResult[0,16], mask[0,1], YmmResult[0,16], YmmMask[0,16]);\n\tconditionalAssign(YmmResult[16,16], mask[1,1], YmmResult[16,16], YmmMask[16,16]);\n\tconditionalAssign(YmmResult[32,16], mask[2,1], YmmResult[32,16], YmmMask[32,16]);\n\tconditionalAssign(YmmResult[48,16], mask[3,1], YmmResult[48,16], YmmMask[48,16]);\n\tconditionalAssign(YmmResult[64,16], mask[4,1], YmmResult[64,16], YmmMask[64,16]);\n\tconditionalAssign(YmmResult[80,16], mask[5,1], YmmResult[80,16], YmmMask[80,16]);\n\tconditionalAssign(YmmResult[96,16], mask[6,1], YmmResult[96,16], YmmMask[96,16]);\n\tconditionalAssign(YmmResult[112,16], mask[7,1], YmmResult[112,16], YmmMask[112,16]);\n\tconditionalAssign(YmmResult[128,16], mask[8,1], YmmResult[128,16], YmmMask[128,16]);\n\tconditionalAssign(YmmResult[144,16], mask[9,1], YmmResult[144,16], YmmMask[144,16]);\n\tconditionalAssign(YmmResult[160,16], mask[10,1], YmmResult[160,16], YmmMask[160,16]);\n\tconditionalAssign(YmmResult[176,16], mask[11,1], YmmResult[176,16], YmmMask[176,16]);\n\tconditionalAssign(YmmResult[192,16], mask[12,1], YmmResult[192,16], YmmMask[192,16]);\n\tconditionalAssign(YmmResult[208,16], mask[13,1], YmmResult[208,16], YmmMask[208,16]);\n\tconditionalAssign(YmmResult[224,16], mask[14,1], YmmResult[224,16], YmmMask[224,16]);\n\tconditionalAssign(YmmResult[240,16], mask[15,1], YmmResult[240,16], YmmMask[240,16]);\n}\n\nYmmOpMask16: is evexOpmask=0 {\n}\n\nYmmOpMask32: AVXOpMask^YmmMaskMode is AVXOpMask & YmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(YmmResult[0,32], mask[0,1], YmmResult[0,32], YmmMask[0,32]);\n\tconditionalAssign(YmmResult[32,32], mask[1,1], YmmResult[32,32], YmmMask[32,32]);\n\tconditionalAssign(YmmResult[64,32], mask[2,1], YmmResult[64,32], YmmMask[64,32]);\n\tconditionalAssign(YmmResult[96,32], mask[3,1], YmmResult[96,32], YmmMask[96,32]);\n\tconditionalAssign(YmmResult[128,32], mask[4,1], YmmResult[128,32], YmmMask[128,32]);\n\tconditionalAssign(YmmResult[160,32], mask[5,1], YmmResult[160,32], YmmMask[160,32]);\n\tconditionalAssign(YmmResult[192,32], mask[6,1], YmmResult[192,32], YmmMask[192,32]);\n\tconditionalAssign(YmmResult[224,32], mask[7,1], YmmResult[224,32], YmmMask[224,32]);\n}\n\nYmmOpMask32: is evexOpmask=0 {\n}\n\nYmmOpMask64: AVXOpMask^YmmMaskMode is AVXOpMask & YmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(YmmResult[0,64], mask[0,1], YmmResult[0,64], YmmMask[0,64]);\n\tconditionalAssign(YmmResult[64,64], mask[1,1], YmmResult[64,64], YmmMask[64,64]);\n\tconditionalAssign(YmmResult[128,64], mask[2,1], YmmResult[128,64], YmmMask[128,64]);\n\tconditionalAssign(YmmResult[192,64], mask[3,1], YmmResult[192,64], YmmMask[192,64]);\n}\n\nYmmOpMask64: is evexOpmask=0 {\n}\n\nZmmOpMask: AVXOpMask^ZmmMaskMode is AVXOpMask & ZmmMaskMode {\n\texport AVXOpMask;\n}\n\nZmmOpMask8: AVXOpMask^ZmmMaskMode is AVXOpMask & ZmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(ZmmResult[0,8], mask[0,1], ZmmResult[0,8], ZmmMask[0,8]);\n\tconditionalAssign(ZmmResult[8,8], mask[1,1], ZmmResult[8,8], ZmmMask[8,8]);\n\tconditionalAssign(ZmmResult[16,8], mask[2,1], ZmmResult[16,8], ZmmMask[16,8]);\n\tconditionalAssign(ZmmResult[24,8], mask[3,1], ZmmResult[24,8], ZmmMask[24,8]);\n\tconditionalAssign(ZmmResult[32,8], mask[4,1], ZmmResult[32,8], ZmmMask[32,8]);\n\tconditionalAssign(ZmmResult[40,8], mask[5,1], ZmmResult[40,8], ZmmMask[40,8]);\n\tconditionalAssign(ZmmResult[48,8], mask[6,1], ZmmResult[48,8], ZmmMask[48,8]);\n\tconditionalAssign(ZmmResult[56,8], mask[7,1], ZmmResult[56,8], ZmmMask[56,8]);\n\tconditionalAssign(ZmmResult[64,8], mask[8,1], ZmmResult[64,8], ZmmMask[64,8]);\n\tconditionalAssign(ZmmResult[72,8], mask[9,1], ZmmResult[72,8], ZmmMask[72,8]);\n\tconditionalAssign(ZmmResult[80,8], mask[10,1], ZmmResult[80,8], ZmmMask[80,8]);\n\tconditionalAssign(ZmmResult[88,8], mask[11,1], ZmmResult[88,8], ZmmMask[88,8]);\n\tconditionalAssign(ZmmResult[96,8], mask[12,1], ZmmResult[96,8], ZmmMask[96,8]);\n\tconditionalAssign(ZmmResult[104,8], mask[13,1], ZmmResult[104,8], ZmmMask[104,8]);\n\tconditionalAssign(ZmmResult[112,8], mask[14,1], ZmmResult[112,8], ZmmMask[112,8]);\n\tconditionalAssign(ZmmResult[120,8], mask[15,1], ZmmResult[120,8], ZmmMask[120,8]);\n\tconditionalAssign(ZmmResult[128,8], mask[16,1], ZmmResult[128,8], ZmmMask[128,8]);\n\tconditionalAssign(ZmmResult[136,8], mask[17,1], ZmmResult[136,8], ZmmMask[136,8]);\n\tconditionalAssign(ZmmResult[144,8], mask[18,1], ZmmResult[144,8], ZmmMask[144,8]);\n\tconditionalAssign(ZmmResult[152,8], mask[19,1], ZmmResult[152,8], ZmmMask[152,8]);\n\tconditionalAssign(ZmmResult[160,8], mask[20,1], ZmmResult[160,8], ZmmMask[160,8]);\n\tconditionalAssign(ZmmResult[168,8], mask[21,1], ZmmResult[168,8], ZmmMask[168,8]);\n\tconditionalAssign(ZmmResult[176,8], mask[22,1], ZmmResult[176,8], ZmmMask[176,8]);\n\tconditionalAssign(ZmmResult[184,8], mask[23,1], ZmmResult[184,8], ZmmMask[184,8]);\n\tconditionalAssign(ZmmResult[192,8], mask[24,1], ZmmResult[192,8], ZmmMask[192,8]);\n\tconditionalAssign(ZmmResult[200,8], mask[25,1], ZmmResult[200,8], ZmmMask[200,8]);\n\tconditionalAssign(ZmmResult[208,8], mask[26,1], ZmmResult[208,8], ZmmMask[208,8]);\n\tconditionalAssign(ZmmResult[216,8], mask[27,1], ZmmResult[216,8], ZmmMask[216,8]);\n\tconditionalAssign(ZmmResult[224,8], mask[28,1], ZmmResult[224,8], ZmmMask[224,8]);\n\tconditionalAssign(ZmmResult[232,8], mask[29,1], ZmmResult[232,8], ZmmMask[232,8]);\n\tconditionalAssign(ZmmResult[240,8], mask[30,1], ZmmResult[240,8], ZmmMask[240,8]);\n\tconditionalAssign(ZmmResult[248,8], mask[31,1], ZmmResult[248,8], ZmmMask[248,8]);\n\tconditionalAssign(ZmmResult[256,8], mask[32,1], ZmmResult[256,8], ZmmMask[256,8]);\n\tconditionalAssign(ZmmResult[264,8], mask[33,1], ZmmResult[264,8], ZmmMask[264,8]);\n\tconditionalAssign(ZmmResult[272,8], mask[34,1], ZmmResult[272,8], ZmmMask[272,8]);\n\tconditionalAssign(ZmmResult[280,8], mask[35,1], ZmmResult[280,8], ZmmMask[280,8]);\n\tconditionalAssign(ZmmResult[288,8], mask[36,1], ZmmResult[288,8], ZmmMask[288,8]);\n\tconditionalAssign(ZmmResult[296,8], mask[37,1], ZmmResult[296,8], ZmmMask[296,8]);\n\tconditionalAssign(ZmmResult[304,8], mask[38,1], ZmmResult[304,8], ZmmMask[304,8]);\n\tconditionalAssign(ZmmResult[312,8], mask[39,1], ZmmResult[312,8], ZmmMask[312,8]);\n\tconditionalAssign(ZmmResult[320,8], mask[40,1], ZmmResult[320,8], ZmmMask[320,8]);\n\tconditionalAssign(ZmmResult[328,8], mask[41,1], ZmmResult[328,8], ZmmMask[328,8]);\n\tconditionalAssign(ZmmResult[336,8], mask[42,1], ZmmResult[336,8], ZmmMask[336,8]);\n\tconditionalAssign(ZmmResult[344,8], mask[43,1], ZmmResult[344,8], ZmmMask[344,8]);\n\tconditionalAssign(ZmmResult[352,8], mask[44,1], ZmmResult[352,8], ZmmMask[352,8]);\n\tconditionalAssign(ZmmResult[360,8], mask[45,1], ZmmResult[360,8], ZmmMask[360,8]);\n\tconditionalAssign(ZmmResult[368,8], mask[46,1], ZmmResult[368,8], ZmmMask[368,8]);\n\tconditionalAssign(ZmmResult[376,8], mask[47,1], ZmmResult[376,8], ZmmMask[376,8]);\n\tconditionalAssign(ZmmResult[384,8], mask[48,1], ZmmResult[384,8], ZmmMask[384,8]);\n\tconditionalAssign(ZmmResult[392,8], mask[49,1], ZmmResult[392,8], ZmmMask[392,8]);\n\tconditionalAssign(ZmmResult[400,8], mask[50,1], ZmmResult[400,8], ZmmMask[400,8]);\n\tconditionalAssign(ZmmResult[408,8], mask[51,1], ZmmResult[408,8], ZmmMask[408,8]);\n\tconditionalAssign(ZmmResult[416,8], mask[52,1], ZmmResult[416,8], ZmmMask[416,8]);\n\tconditionalAssign(ZmmResult[424,8], mask[53,1], ZmmResult[424,8], ZmmMask[424,8]);\n\tconditionalAssign(ZmmResult[432,8], mask[54,1], ZmmResult[432,8], ZmmMask[432,8]);\n\tconditionalAssign(ZmmResult[440,8], mask[55,1], ZmmResult[440,8], ZmmMask[440,8]);\n\tconditionalAssign(ZmmResult[448,8], mask[56,1], ZmmResult[448,8], ZmmMask[448,8]);\n\tconditionalAssign(ZmmResult[456,8], mask[57,1], ZmmResult[456,8], ZmmMask[456,8]);\n\tconditionalAssign(ZmmResult[464,8], mask[58,1], ZmmResult[464,8], ZmmMask[464,8]);\n\tconditionalAssign(ZmmResult[472,8], mask[59,1], ZmmResult[472,8], ZmmMask[472,8]);\n\tconditionalAssign(ZmmResult[480,8], mask[60,1], ZmmResult[480,8], ZmmMask[480,8]);\n\tconditionalAssign(ZmmResult[488,8], mask[61,1], ZmmResult[488,8], ZmmMask[488,8]);\n\tconditionalAssign(ZmmResult[496,8], mask[62,1], ZmmResult[496,8], ZmmMask[496,8]);\n\tconditionalAssign(ZmmResult[504,8], mask[63,1], ZmmResult[504,8], ZmmMask[504,8]);\n}\n\nZmmOpMask8: is evexOpmask=0 {\n}\n\nZmmOpMask16: AVXOpMask^ZmmMaskMode is AVXOpMask & ZmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(ZmmResult[0,16], mask[0,1], ZmmResult[0,16], ZmmMask[0,16]);\n\tconditionalAssign(ZmmResult[16,16], mask[1,1], ZmmResult[16,16], ZmmMask[16,16]);\n\tconditionalAssign(ZmmResult[32,16], mask[2,1], ZmmResult[32,16], ZmmMask[32,16]);\n\tconditionalAssign(ZmmResult[48,16], mask[3,1], ZmmResult[48,16], ZmmMask[48,16]);\n\tconditionalAssign(ZmmResult[64,16], mask[4,1], ZmmResult[64,16], ZmmMask[64,16]);\n\tconditionalAssign(ZmmResult[80,16], mask[5,1], ZmmResult[80,16], ZmmMask[80,16]);\n\tconditionalAssign(ZmmResult[96,16], mask[6,1], ZmmResult[96,16], ZmmMask[96,16]);\n\tconditionalAssign(ZmmResult[112,16], mask[7,1], ZmmResult[112,16], ZmmMask[112,16]);\n\tconditionalAssign(ZmmResult[128,16], mask[8,1], ZmmResult[128,16], ZmmMask[128,16]);\n\tconditionalAssign(ZmmResult[144,16], mask[9,1], ZmmResult[144,16], ZmmMask[144,16]);\n\tconditionalAssign(ZmmResult[160,16], mask[10,1], ZmmResult[160,16], ZmmMask[160,16]);\n\tconditionalAssign(ZmmResult[176,16], mask[11,1], ZmmResult[176,16], ZmmMask[176,16]);\n\tconditionalAssign(ZmmResult[192,16], mask[12,1], ZmmResult[192,16], ZmmMask[192,16]);\n\tconditionalAssign(ZmmResult[208,16], mask[13,1], ZmmResult[208,16], ZmmMask[208,16]);\n\tconditionalAssign(ZmmResult[224,16], mask[14,1], ZmmResult[224,16], ZmmMask[224,16]);\n\tconditionalAssign(ZmmResult[240,16], mask[15,1], ZmmResult[240,16], ZmmMask[240,16]);\n\tconditionalAssign(ZmmResult[256,16], mask[16,1], ZmmResult[256,16], ZmmMask[256,16]);\n\tconditionalAssign(ZmmResult[272,16], mask[17,1], ZmmResult[272,16], ZmmMask[272,16]);\n\tconditionalAssign(ZmmResult[288,16], mask[18,1], ZmmResult[288,16], ZmmMask[288,16]);\n\tconditionalAssign(ZmmResult[304,16], mask[19,1], ZmmResult[304,16], ZmmMask[304,16]);\n\tconditionalAssign(ZmmResult[320,16], mask[20,1], ZmmResult[320,16], ZmmMask[320,16]);\n\tconditionalAssign(ZmmResult[336,16], mask[21,1], ZmmResult[336,16], ZmmMask[336,16]);\n\tconditionalAssign(ZmmResult[352,16], mask[22,1], ZmmResult[352,16], ZmmMask[352,16]);\n\tconditionalAssign(ZmmResult[368,16], mask[23,1], ZmmResult[368,16], ZmmMask[368,16]);\n\tconditionalAssign(ZmmResult[384,16], mask[24,1], ZmmResult[384,16], ZmmMask[384,16]);\n\tconditionalAssign(ZmmResult[400,16], mask[25,1], ZmmResult[400,16], ZmmMask[400,16]);\n\tconditionalAssign(ZmmResult[416,16], mask[26,1], ZmmResult[416,16], ZmmMask[416,16]);\n\tconditionalAssign(ZmmResult[432,16], mask[27,1], ZmmResult[432,16], ZmmMask[432,16]);\n\tconditionalAssign(ZmmResult[448,16], mask[28,1], ZmmResult[448,16], ZmmMask[448,16]);\n\tconditionalAssign(ZmmResult[464,16], mask[29,1], ZmmResult[464,16], ZmmMask[464,16]);\n\tconditionalAssign(ZmmResult[480,16], mask[30,1], ZmmResult[480,16], ZmmMask[480,16]);\n\tconditionalAssign(ZmmResult[496,16], mask[31,1], ZmmResult[496,16], ZmmMask[496,16]);\n}\n\nZmmOpMask16: is evexOpmask=0 {\n}\n\nZmmOpMask32: AVXOpMask^ZmmMaskMode is AVXOpMask & ZmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(ZmmResult[0,32], mask[0,1], ZmmResult[0,32], ZmmMask[0,32]);\n\tconditionalAssign(ZmmResult[32,32], mask[1,1], ZmmResult[32,32], ZmmMask[32,32]);\n\tconditionalAssign(ZmmResult[64,32], mask[2,1], ZmmResult[64,32], ZmmMask[64,32]);\n\tconditionalAssign(ZmmResult[96,32], mask[3,1], ZmmResult[96,32], ZmmMask[96,32]);\n\tconditionalAssign(ZmmResult[128,32], mask[4,1], ZmmResult[128,32], ZmmMask[128,32]);\n\tconditionalAssign(ZmmResult[160,32], mask[5,1], ZmmResult[160,32], ZmmMask[160,32]);\n\tconditionalAssign(ZmmResult[192,32], mask[6,1], ZmmResult[192,32], ZmmMask[192,32]);\n\tconditionalAssign(ZmmResult[224,32], mask[7,1], ZmmResult[224,32], ZmmMask[224,32]);\n\tconditionalAssign(ZmmResult[256,32], mask[8,1], ZmmResult[256,32], ZmmMask[256,32]);\n\tconditionalAssign(ZmmResult[288,32], mask[9,1], ZmmResult[288,32], ZmmMask[288,32]);\n\tconditionalAssign(ZmmResult[320,32], mask[10,1], ZmmResult[320,32], ZmmMask[320,32]);\n\tconditionalAssign(ZmmResult[352,32], mask[11,1], ZmmResult[352,32], ZmmMask[352,32]);\n\tconditionalAssign(ZmmResult[384,32], mask[12,1], ZmmResult[384,32], ZmmMask[384,32]);\n\tconditionalAssign(ZmmResult[416,32], mask[13,1], ZmmResult[416,32], ZmmMask[416,32]);\n\tconditionalAssign(ZmmResult[448,32], mask[14,1], ZmmResult[448,32], ZmmMask[448,32]);\n\tconditionalAssign(ZmmResult[480,32], mask[15,1], ZmmResult[480,32], ZmmMask[480,32]);\n}\n\nZmmOpMask32: is evexOpmask=0 {\n}\n\nZmmOpMask64: AVXOpMask^ZmmMaskMode is AVXOpMask & ZmmMaskMode {\n\tlocal mask = AVXOpMask;\n\tconditionalAssign(ZmmResult[0,64], mask[0,1], ZmmResult[0,64], ZmmMask[0,64]);\n\tconditionalAssign(ZmmResult[64,64], mask[1,1], ZmmResult[64,64], ZmmMask[64,64]);\n\tconditionalAssign(ZmmResult[128,64], mask[2,1], ZmmResult[128,64], ZmmMask[128,64]);\n\tconditionalAssign(ZmmResult[192,64], mask[3,1], ZmmResult[192,64], ZmmMask[192,64]);\n\tconditionalAssign(ZmmResult[256,64], mask[4,1], ZmmResult[256,64], ZmmMask[256,64]);\n\tconditionalAssign(ZmmResult[320,64], mask[5,1], ZmmResult[320,64], ZmmMask[320,64]);\n\tconditionalAssign(ZmmResult[384,64], mask[6,1], ZmmResult[384,64], ZmmMask[384,64]);\n\tconditionalAssign(ZmmResult[448,64], mask[7,1], ZmmResult[448,64], ZmmMask[448,64]);\n}\n\nZmmOpMask64: is evexOpmask=0 {\n}\n\n\nRegK_m8: KReg_rm is mod=3 & KReg_rm { tmp:1 = KReg_rm[0,8]; export tmp; }\nRegK_m8: m8 is m8 { tmp:1 = m8; export tmp; }\nRegK_m16: KReg_rm is mod=3 & KReg_rm { tmp:2 = KReg_rm[0,16]; export tmp;}\nRegK_m16: m16 is m16 { tmp:2 = m16; export tmp; }\nRegK_m32: KReg_rm is mod=3 & KReg_rm { tmp:4 = KReg_rm[0,32]; export tmp; }\nRegK_m32: m32 is m32 { tmp:4 = m32; export tmp; }\nRegK_m64: KReg_rm is mod=3 & KReg_rm { export KReg_rm; }\nRegK_m64: m64 is m64 { export m64; }\n\n# Some macros\n\nmacro ptr2(r,x) {\n r = zext(x);\n}\n\nmacro ptr4(r,x) {\n@ifdef IA64\n r = zext(x);\n@else\n r = x;\n@endif\n}\n\nmacro ptr8(r,x) {\n@ifdef IA64\n r = x;\n@else\n r = x:$(SIZE);\n@endif\n}\n\nmacro push22(x) {\n mysave:2 = x;\n SP = SP -2;\n tmp:$(SIZE) = segment(SS,SP);\n *:2 tmp = mysave;\n}\n\nmacro push24(x) {\n mysave:4 = x;\n SP = SP-4;\n tmp:$(SIZE) = segment(SS,SP);\n *:4 tmp = mysave;\n}\n\nmacro push28(x) {\n mysave:8 = x;\n SP = SP-8;\n tmp:$(SIZE) = segment(SS,SP);\n *:8 tmp = mysave;\n}\n\nmacro push42(x) {\n mysave:2 = x;\n $(STACKPTR) = $(STACKPTR) - 2;\n *:2 $(STACKPTR) = mysave;\n}\n\nmacro push44(x) {\n mysave:4 = x;\n $(STACKPTR) = $(STACKPTR) - 4;\n *:4 $(STACKPTR) = mysave;\n}\n\nmacro pushseg44(x) {\n mysave:2 = x;\n $(STACKPTR) = $(STACKPTR) - 4;\n *:2 $(STACKPTR) = mysave;\n}\n\nmacro push48(x) {\n mysave:8 = x;\n $(STACKPTR) = $(STACKPTR) - 8;\n *:8 $(STACKPTR) = mysave;\n}\n\n@ifdef IA64\nmacro push82(x) {\n mysave:2 = x;\n $(STACKPTR) = $(STACKPTR) - 2;\n *:2 $(STACKPTR) = mysave;\n}\n\nmacro push84(x) {\n mysave:4 = x;\n $(STACKPTR) = $(STACKPTR) - 4;\n *:4 $(STACKPTR) = mysave;\n}\n\nmacro push88(x) {\n mysave:8 = x;\n $(STACKPTR) = $(STACKPTR) - 8;\n *:8 $(STACKPTR) = mysave;\n}\n\nmacro pushseg88(x) {\n mysave:8 = zext(x);\n $(STACKPTR) = $(STACKPTR) - 8;\n *:8 $(STACKPTR) = mysave;\n}\n@endif\n\nmacro pop22(x) {\n tmp:$(SIZE) = segment(SS,SP);\n x = *:2 tmp;\n SP = SP+2;\n}\n\nmacro pop24(x) {\n tmp:$(SIZE) = segment(SS,SP);\n x = *:4 tmp;\n SP = SP+4;\n}\n\nmacro pop28(x) {\n tmp:$(SIZE) = segment(SS,SP);\n x = *:8 tmp;\n SP = SP+8;\n}\n\nmacro pop42(x) {\n x = *:2 $(STACKPTR);\n ESP = ESP + 2;\n}\n\nmacro pop44(x) {\n x = *:4 $(STACKPTR);\n ESP = ESP + 4;\n}\n\nmacro popseg44(x) {\n x = *:2 $(STACKPTR);\n ESP = ESP + 4;\n}\n\nmacro pop48(x) {\n x = *:8 $(STACKPTR);\n ESP = ESP + 8;\n}\n\n@ifdef IA64\nmacro pop82(x) {\n x = *:2 $(STACKPTR);\n RSP = RSP + 2;\n}\n\nmacro pop84(x) {\n x = *:4 $(STACKPTR);\n RSP = RSP + 4;\n}\n\nmacro pop88(x) {\n x = *:8 $(STACKPTR);\n RSP = RSP + 8;\n}\n\nmacro popseg88(x) {\n x = *:2 $(STACKPTR);\n RSP = RSP + 8;\n}\n@endif\n\nmacro unpackflags(tmp) {\n NT = (tmp & 0x4000) != 0;\n# IOPL = (tmp & 0x1000) != 0;\n OF = (tmp & 0x0800) != 0;\n DF = (tmp & 0x0400) != 0;\n IF = (tmp & 0x0200) != 0;\n TF = (tmp & 0x0100) != 0;\n SF = (tmp & 0x0080) != 0;\n ZF = (tmp & 0x0040) != 0;\n AF = (tmp & 0x0010) != 0;\n PF = (tmp & 0x0004) != 0;\n CF = (tmp & 0x0001) != 0;\n}\n\nmacro unpackeflags(tmp) {\n ID = (tmp & 0x00200000) != 0;\n AC = (tmp & 0x00040000) != 0;\n# RF = (tmp & 0x00010000) != 0;\n VIP = 0;\n VIF = 0;\n}\n\nmacro packflags(tmp) {\n tmp= (0x4000 * zext(NT&1))\n# | (0x1000 * zext(IOPL&1))\n | (0x0800 * zext(OF&1))\n | (0x0400 * zext(DF&1)) | (0x0200 * zext(IF&1)) | (0x0100 * zext(TF&1))\n | (0x0080 * zext(SF&1)) | (0x0040 * zext(ZF&1)) | (0x0010 * zext(AF&1))\n | (0x0004 * zext(PF&1)) | (0x0001 * zext(CF&1));\n}\n\nmacro packeflags(tmp) {\n tmp = tmp | (0x00200000 * zext(ID&1)) | (0x00100000 * zext(VIP&1))\n | (0x00080000 * zext(VIF&1)) | (0x00040000 * zext(AC&1));\n}\n\nmacro addflags(op1,op2) {\n CF = carry(op1,op2);\n OF = scarry(op1,op2);\n}\n\n#\n# full-adder carry and overflow calculations\n#\nmacro addCarryFlags ( op1, op2 ) {\n\tlocal CFcopy = zext(CF);\n\tCF = carry( op1, op2 );\n\tOF = scarry( op1, op2 );\n\tlocal result = op1 + op2;\n\tCF = CF || carry( result, CFcopy );\n\tOF = OF ^^ scarry( result, CFcopy );\n\top1 = result + CFcopy;\n\t# AF not implemented\n}\n\n\nmacro subCarryFlags ( op1, op2 ) {\n\tlocal CFcopy = zext(CF);\n\tCF = op1 < op2;\n\tOF = sborrow( op1, op2 );\n\tlocal result = op1 - op2;\n\tCF = CF || (result < CFcopy);\n\tOF = OF ^^ sborrow( result, CFcopy );\n\top1 = result - CFcopy;\n\t# AF not implemented\n}\n\nmacro resultflags(result) {\n SF = result s< 0;\n ZF = result == 0;\n PF = ((popcount(result & 0xff) & 1:1) == 0);\n # AF not implemented\n}\n\nmacro shiftresultflags(result,count) {\n\n local notzero = (count != 0);\n\n local newSF = (result s< 0);\n SF = (!notzero & SF) | (notzero & newSF);\n\n local newZF = (result == 0);\n ZF = (!notzero & ZF) | (notzero & newZF);\n \n local newPF = ((popcount(result & 0xff) & 1:1) == 0);\n PF = (!notzero & PF) | (notzero & newPF);\n # AF not implemented\n}\n\nmacro subflags(op1,op2) {\n CF = op1 < op2;\n OF = sborrow(op1,op2);\n}\n\nmacro negflags(op1) {\n CF = (op1 != 0);\n OF = sborrow(0,op1);\n}\n\nmacro logicalflags() {\n CF = 0;\n OF = 0;\n}\n\nmacro imultflags(low,total){\n CF = sext(low) != total;\n OF = CF;\n}\n\nmacro multflags(highhalf) {\n CF = highhalf != 0;\n OF = CF;\n}\n\nmacro rolflags(result,count) {\n\n local notzero = (count != 0);\n local newCF = ((result & 1) != 0);\n CF = (!notzero & CF) | (notzero & newCF);\n\n local one = (count == 1);\n local newOF = CF ^ (result s< 0);\n OF = (!one & OF) | (one & newOF);\n}\n\nmacro rorflags(result,count) {\n\n local notzero = (count != 0);\n local newCF = (result s< 0);\n CF = (!notzero & CF) | (notzero & newCF);\n\n local one = (count == 1);\n local newOF = (result s< 0) ^ ((result << 1) s< 0);\n OF = (!one & OF) | (one & newOF);\n}\n\nmacro shlflags(op1,result,count) { # works for shld also\n\n local notzero = (count != 0);\n local newCF = ( (op1 << (count - 1)) s< 0 );\n CF = (!notzero & CF) | (notzero & newCF);\n\n local one = (count == 1);\n local newOF = CF ^ (result s< 0);\n OF = (!one & OF) | (one & newOF);\n}\n\nmacro sarflags(op1,result,count) {\n\n local notzero = (count != 0);\n local newCF = ( ( (op1 s>> (count - 1)) & 1 ) != 0 );\n CF = (!notzero & CF) | (notzero & newCF);\n\n local one = (count == 1);\n OF = (!one & OF);\n}\n\nmacro shrflags(op1,result,count) {\n\n local notzero = (count != 0);\n local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 );\n CF = (!notzero & CF) | (notzero & newCF);\n\n local one = (count == 1);\n local newOF = (op1 s< 0);\n OF = (!one & OF) | (one & newOF);\n}\n\nmacro shrdflags(op1,result,count) {\n\n local notzero = (count != 0);\n local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 );\n CF = (!notzero & CF) | (notzero & newCF);\n\n local one = (count == 1);\n local newOF = ((op1 s< 0) ^ (result s< 0));\n OF = (!one & OF) | (one & newOF);\n}\n\nmacro fdec() {\n local tmp = ST7;\n\tST7 = ST6;\n\tST6 = ST5;\n\tST5 = ST4;\n\tST4 = ST3;\n\tST3 = ST2;\n\tST2 = ST1;\n\tST1 = ST0;\n\tST0 = tmp;\n}\n\nmacro finc() {\n local tmp = ST0;\n\tST0 = ST1;\n\tST1 = ST2;\n\tST2 = ST3;\n\tST3 = ST4;\n\tST4 = ST5;\n\tST5 = ST6;\n\tST6 = ST7;\n\tST7 = tmp;\n}\n\nmacro fpop() {\n\tST0 = ST1;\n\tST1 = ST2;\n\tST2 = ST3;\n\tST3 = ST4;\n\tST4 = ST5;\n\tST5 = ST6;\n\tST6 = ST7;\n}\n\n macro fpushv(val) {\n\tST7 = ST6;\n\tST6 = ST5;\n\tST5 = ST4;\n\tST4 = ST3;\n\tST3 = ST2;\n\tST2 = ST1;\n\tST1 = ST0;\n\tST0 = val;\n}\n\nmacro fpopv(val) {\n val = ST0;\n\tST0 = ST1;\n\tST1 = ST2;\n\tST2 = ST3;\n\tST3 = ST4;\n\tST4 = ST5;\n\tST5 = ST6;\n\tST6 = ST7;\n}\n\nmacro fcom(val) {\n C1 = 0;\n \n C2 = nan(ST0) || nan(val);\n C0 = C2 | ( ST0 f< val ); \n C3 = C2 | ( ST0 f== val );\n\n FPUStatusWord = (zext(C0)<<8) | (zext(C1)<<9) | (zext(C2)<<10) | (zext(C3)<<14);\n}\n\nmacro fcomi(val) {\n PF = nan(ST0) || nan(val);\n\tZF = PF | ( ST0 f== val );\n\tCF = PF | ( ST0 f< val ); \n \n OF = 0;\n AF = 0;\n SF = 0;\n\t\n FPUStatusWord = FPUStatusWord & 0xfdff; # Clear C1\n C1 = 0;\n}\n\n# floating point NaN comparison into EFLAGS\nmacro fucompe(val1, val2) {\n PF = nan(val1) || nan(val2 );\n ZF = PF | ( val1 f== val2 );\n CF = PF | ( val1 f< val2 ); \n \n OF = 0;\n AF = 0;\n SF = 0;\n}\n\n# The base level constructors\n# The prefixes\n:^instruction is instrPhase=0 & over=0x2e; instruction [ segover=1; ] {} # CS override\n:^instruction is instrPhase=0 & over=0x36; instruction [ segover=2; ] {} # SS override\n:^instruction is instrPhase=0 & over=0x3e; instruction [ segover=3; ] {} # DS override\n:^instruction is instrPhase=0 & over=0x26; instruction [ segover=4; ] {} # ES override\n:^instruction is instrPhase=0 & over=0x64; instruction [ segover=5; ] {} # FS override\n:^instruction is instrPhase=0 & over=0x65; instruction [ segover=6; ] {} # GS override\n:^instruction is instrPhase=0 & over=0x66; instruction [ opsize=opsize $xor 1; mandover = mandover $xor 1; ] {} # Operand size override\n:^instruction is instrPhase=0 & over=0x67; instruction [ addrsize=addrsize $xor 1; ] {} # Address size override\n:^instruction is instrPhase=0 & over=0xf2; instruction [ repneprefx=1; repprefx=0; ] {}\n:^instruction is instrPhase=0 & over=0xf3; instruction [ repneprefx=0; repprefx=1; ] {}\n:^instruction is instrPhase=0 & over=0xf0; instruction [ lockprefx=1; ] {}\n@ifdef IA64\n\n#\n# REX opcode extension prefixes\n#\n\n# REX prefix present\n# Specification is \"REX\"\n@define REX \"longMode=1 & rexprefix=1 & rexWprefix=0\"\n\n# Specification is \"REX.W\"\n@define REX_W \"longMode=1 & rexprefix=1 & rexWprefix=1\"\n\n\n\n# TODO I don't think the following line can really happen because the 66 67 prefix must come before REX prefix\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & over=0x66 & opsize=2; instruction [ opsize=0; mandover=mandover $xor 1; ] {} # Operand size override\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & over=0x67 & addrsize=2; instruction [ addrsize=1; ] {} # Address size override\n\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & row=0x4 & rexw=0 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=1; rexWprefix=0; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & row=0x4 & rexw=1 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=2; rexWprefix=1; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & opsize=0 & row=0x4 & rexw=0 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=0; rexWprefix=0; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & opsize=0 & row=0x4 & rexw=1 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=2; rexWprefix=1; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {}\n\n # if longmode is off (on 64-bit processor in 32-bit compatibility mode), there is no 64-bit addressing, make sure is off before parsing\n #\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & addrsize=2 & instruction [ addrsize=1; ] {}\n@endif\n\n#\n# VEX definitions: One from each group must be present in the decoding; following the specification from the manual.\n#\n\n# VEX encoding for type of VEX data flow.\n# Specification is \"VEX.\", \"VEX.NDS\", \"VEX.NDD\", or \"VEX.DDS\". If only \"VEX.\" is present, then \"VEX_NONE\" must be used. \n@define VEX_NONE\t\"vexMode=1\"\n@define VEX_NDS\t\t\"vexMode=1\"\n@define VEX_NDD\t\t\"vexMode=1\"\n@define VEX_DDS\t\t\"vexMode=1\"\n\n# Specification is \"LIG\", \"LZ\", \"128\", or \"256\".\n@define VEX_LIG\t\t\"vexL\"\n@define VEX_LZ\t\t\"vexL=0\"\n@define VEX_L128\t\"vexL=0\"\n@define VEX_L256\t\"vexL=1\"\n@define EVEX_L512\t\"evexLp=1 & vexL=0\"\n@define EVEX_LLIG\t\"evexLp & vexL\"\n\n# These are only to be used with VEX or EVEX decoding, where only one \"mandatory\" prefix is encoded in the VEX or EVEX.\n# If no prefix is specified, then VEX_PRE_NONE must be used.\n# No other \"physical\" prefixes are allowed.\n# Specification is \"(empty)\", \"66\", \"F3\", or \"F2\". If none of these are present (empty), then \"VEX_PRE_NONE\" must be used.\n@define VEX_PRE_NONE\t\"mandover=0\"\n@define VEX_PRE_66\t\t\"mandover=1\"\n@define VEX_PRE_F3\t\t\"mandover=2\"\n@define VEX_PRE_F2\t\t\"mandover=4\"\n\n# Specification is \"0F\", \"0F38\", or \"0F3A\".\n@define VEX_0F\t\t\"vexMMMMM=1\"\n@define VEX_0F38\t\"vexMMMMM=2\"\n@define VEX_0F3A\t\"vexMMMMM=3\"\n@define VEX_MAP4\t\"vexMMMMM=4\"\n@define VEX_MAP5\t\"vexMMMMM=5\"\n@define VEX_MAP6\t\"vexMMMMM=6\"\n\n# Specification is \"WIG\", \"W0\", or \"W1\".\n@define VEX_WIG\t\t\"rexWprefix\"\n@define VEX_W0\t\t\"rexWprefix=0\"\n@define VEX_W1\t\t\"rexWprefix=1\"\n\n@define EVEX_NONE\t\"vexMode=2\"\n@define EVEX_NDS\t\"vexMode=2\"\n@define EVEX_NDD\t\"vexMode=2\"\n@define EVEX_DDS\t\"vexMode=2\"\n\n@ifdef IA64\n\n# 64-bit 3-byte VEX\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_66=1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f3=1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f2=1; ] {}\n\n# 64-bit 2-byte VEX\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=0; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=1; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_66=1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=2; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f3=1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=3; instruction\n [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {}\n\n# 4-byte EVEX prefix\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=0; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;\n evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=1; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;\n evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_66=1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=2; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;\n evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_f3=1; ] {}\n:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=3; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;\n evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_f2=1; ] {}\n@endif\n\n# 32-bit 3-byte VEX\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction\n [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction\n [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_66=1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction\n [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f3=1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction\n [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f2=1; ] {}\n\n# 32-bit 2-byte VEX\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=0; instruction\n [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=1; instruction\n [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_66=1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=2; instruction\n [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f3=1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=3; instruction\n [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {}\n\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=0; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=1; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_66=1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=2; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f3=1; ] {}\n:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;\n vex_w & vex_vvvv & evex_res2=1 & vex_pp=3; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction\n [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f2=1; ] {}\n\n# Many of the multimedia instructions have a \"mandatory\" prefix, either 0x66, 0xf2 or 0xf3\n# where the prefix really becomes part of the encoding. We collect the three possible prefixes of this\n# sort in the mandover context variable so we can pattern all three at once\n\n# 3DNow pre-parse to isolate suffix byte into context (suffix3D)\n# - general format: 0x0f 0x0f [sib] [displacement] \n# - must determine number of bytes consumed by addressing modes\n# TODO: determine supported prefixes? (e.g., 0x26)\n\nSuffix3D: imm8 is imm8 [ suffix3D=imm8; ] { }\n\n:^instruction is instrPhase=0 & (byte=0x0f; byte=0x0f; XmmReg ... & m64; Suffix3D) ... & instruction ... [ instrPhase=1; ] { }\n:^instruction is instrPhase=0 & (byte=0x0f; byte=0x0f; mmxmod=3; Suffix3D) ... & instruction ... [ instrPhase=1; ] { }\n\n\n# Instructions in alphabetical order\n\n# See 'lockable.sinc' file for instructions that are lockable\nwith : lockprefx=0 {\n\n:AAA\t\t\tis vexMode=0 & bit64=0 & byte=0x37\t\t{ local car = ((AL & 0xf) > 9) | AF; AL = (AL+6*car)&0xf; AH=AH+car; CF=car; AF=car; }\n:AAD imm8\t\tis vexMode=0 & bit64=0 & byte=0xd5; imm8\t{ AL = AL + imm8*AH; AH=0; resultflags(AX); }\n:AAM imm8\t\tis vexMode=0 & bit64=0 & byte=0xd4; imm8\t{ AH = AL/imm8; AL = AL % imm8; resultflags(AX); }\n:AAS\t\t\tis vexMode=0 & bit64=0 & byte=0x3f\t\t{ local car = ((AL & 0xf) > 9) | AF; AL = (AL-6*car)&0xf; AH=AH-car; CF=car; AF=car; }\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:ADC AL,imm8\t\tis vexMode=0 & byte=0x14; AL & imm8\t\t\t\t\t\t{ addCarryFlags( AL, imm8:1 ); resultflags( AL ); }\n:ADC AX,imm16\t\tis vexMode=0 & opsize=0 & byte=0x15; AX & imm16\t\t\t{ addCarryFlags( AX, imm16:2 ); resultflags( AX ); }\n:ADC EAX,imm32\t\tis vexMode=0 & opsize=1 & byte=0x15; EAX & check_EAX_dest & imm32 { addCarryFlags( EAX, imm32:4 ); build check_EAX_dest; resultflags( EAX ); }\n@ifdef IA64\n:ADC RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x15; RAX & simm32 { addCarryFlags( RAX, simm32 ); resultflags( RAX ); }\n@endif\n:ADC Rmr8,imm8\t\tis vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=2; imm8 { addCarryFlags( Rmr8, imm8:1 ); resultflags( Rmr8 ); }\n:ADC Rmr16,imm16\tis vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=2; imm16 { addCarryFlags( Rmr16, imm16:2 ); resultflags( Rmr16 ); }\n:ADC Rmr32,imm32\tis vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=2; imm32 { addCarryFlags( Rmr32, imm32:4 ); build check_Rmr32_dest; resultflags( Rmr32 ); }\n@ifdef IA64\n:ADC Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=2; simm32 { addCarryFlags( Rmr64, simm32 ); resultflags( Rmr64 ); }\n@endif\n:ADC Rmr16,simm8_16\tis vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=2; simm8_16\t{ addCarryFlags( Rmr16, simm8_16 ); resultflags( Rmr16 ); }\n:ADC Rmr32,simm8_32\tis vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=2; simm8_32 { addCarryFlags( Rmr32, simm8_32 ); build check_Rmr32_dest; resultflags( Rmr32 ); }\n@ifdef IA64\n:ADC Rmr64,simm8_64\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=2; simm8_64 { addCarryFlags( Rmr64, simm8_64 ); resultflags( Rmr64 ); }\n@endif\n:ADC Rmr8,Reg8 is vexMode=0 & byte=0x10; mod=3 & Rmr8 & Reg8 { addCarryFlags( Rmr8, Reg8 ); resultflags( Rmr8 ); }\n:ADC Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x11; mod=3 & Rmr16 & Reg16 { addCarryFlags( Rmr16, Reg16 ); resultflags( Rmr16 ); }\n:ADC Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x11; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { addCarryFlags( Rmr32, Reg32 ); build check_Rmr32_dest; resultflags( Rmr32 ); }\n@ifdef IA64\n:ADC Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x11; mod=3 & Rmr64 & Reg64 { addCarryFlags( Rmr64, Reg64 ); resultflags( Rmr64 ); }\n@endif\n:ADC Reg8,rm8 is vexMode=0 & byte=0x12; rm8 & Reg8 ... { addCarryFlags( Reg8, rm8 ); resultflags( Reg8 ); }\n:ADC Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x13; rm16 & Reg16 ... { addCarryFlags( Reg16, rm16 ); resultflags( Reg16 ); }\n:ADC Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x13; rm32 & Reg32 ... & check_Reg32_dest ... { addCarryFlags( Reg32, rm32 ); build check_Reg32_dest; resultflags( Reg32 ); }\n@ifdef IA64\n:ADC Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x13; rm64 & Reg64 ... { addCarryFlags( Reg64, rm64 ); resultflags( Reg64 ); }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:ADD AL,imm8\t\tis vexMode=0 & byte=0x4; AL & imm8\t\t\t\t\t{ addflags( AL,imm8 ); AL = AL + imm8; resultflags( AL); }\n:ADD AX,imm16\t\tis vexMode=0 & opsize=0 & byte=0x5; AX & imm16\t\t\t{ addflags( AX,imm16); AX = AX + imm16; resultflags( AX); }\n:ADD EAX,imm32\t\tis vexMode=0 & opsize=1 & byte=0x5; EAX & check_EAX_dest & imm32\t\t\t{ addflags( EAX,imm32); EAX = EAX + imm32; build check_EAX_dest; resultflags( EAX); }\n@ifdef IA64\n:ADD RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x5; RAX & simm32 { addflags( RAX,simm32); RAX = RAX + simm32; resultflags( RAX); }\n@endif\n:ADD Rmr8,imm8\t\tis vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=0; imm8\t\t{ addflags( Rmr8,imm8 ); Rmr8 = Rmr8 + imm8; resultflags( Rmr8); }\n:ADD Rmr16,imm16\t\tis vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=0; imm16\t{ addflags( Rmr16,imm16); Rmr16 = Rmr16 + imm16; resultflags( Rmr16); }\n:ADD Rmr32,imm32\t\tis vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0; imm32\t{ addflags( Rmr32,imm32); Rmr32 = Rmr32 + imm32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:ADD Rmr64,simm32\t\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=0; simm32\t{ addflags( Rmr64,simm32); Rmr64 = Rmr64 + simm32; resultflags( Rmr64); }\n@endif\n:ADD Rmr16,simm8_16\t\tis vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=0; simm8_16\t{ addflags( Rmr16,simm8_16); Rmr16 = Rmr16 + simm8_16; resultflags( Rmr16); }\n:ADD Rmr32,simm8_32\t\tis vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0; simm8_32\t{ addflags( Rmr32,simm8_32); Rmr32 = Rmr32 + simm8_32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:ADD Rmr64,simm8_64\t\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=0; simm8_64\t{ addflags( Rmr64,simm8_64); Rmr64 = Rmr64 + simm8_64; resultflags( Rmr64); }\n@endif\n:ADD Rmr8,Reg8 is vexMode=0 & byte=0x00; mod=3 & Rmr8 & Reg8 { addflags( Rmr8,Reg8 ); Rmr8 = Rmr8 + Reg8; resultflags( Rmr8); }\n:ADD Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x1; mod=3 & Rmr16 & Reg16 { addflags( Rmr16,Reg16); Rmr16 = Rmr16 + Reg16; resultflags( Rmr16); }\n:ADD Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x1; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { addflags( Rmr32,Reg32); Rmr32 = Rmr32 + Reg32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:ADD Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x1; mod=3 & Rmr64 & Reg64 { addflags( Rmr64,Reg64); Rmr64 = Rmr64 + Reg64; resultflags( Rmr64); }\n@endif\n:ADD Reg8,rm8 is vexMode=0 & byte=0x2; rm8 & Reg8 ... { addflags( Reg8,rm8 ); Reg8 = Reg8 + rm8; resultflags( Reg8); }\n:ADD Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x3; rm16 & Reg16 ... { addflags(Reg16,rm16 ); Reg16 = Reg16 + rm16; resultflags(Reg16); }\n:ADD Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x3; rm32 & Reg32 ... & check_Reg32_dest ... { addflags(Reg32,rm32 ); Reg32 = Reg32 + rm32; build check_Reg32_dest; resultflags(Reg32); }\n@ifdef IA64\n:ADD Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x3; rm64 & Reg64 ... { addflags(Reg64,rm64 ); Reg64 = Reg64 + rm64; resultflags(Reg64); }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:AND AL,imm8 is vexMode=0 & byte=0x24; AL & imm8 { logicalflags(); AL = AL & imm8; resultflags( AL); }\n:AND AX,imm16 is vexMode=0 & opsize=0 & byte=0x25; AX & imm16 { logicalflags(); AX = AX & imm16; resultflags( AX); }\n:AND EAX,imm32 is vexMode=0 & opsize=1 & byte=0x25; EAX & check_EAX_dest & imm32 { logicalflags(); EAX = EAX & imm32; build check_EAX_dest; resultflags( EAX); }\n@ifdef IA64\n:AND RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x25; RAX & simm32 { logicalflags(); RAX = RAX & simm32; resultflags( RAX); }\n@endif\n:AND Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=4; imm8 { logicalflags(); Rmr8 = Rmr8 & imm8; resultflags( Rmr8); }\n:AND Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=4; imm16 { logicalflags(); Rmr16 = Rmr16 & imm16; resultflags( Rmr16); }\n:AND Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=4; imm32 { logicalflags(); Rmr32 = Rmr32 & imm32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:AND Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=4; simm32 { logicalflags(); Rmr64 = Rmr64 & simm32; resultflags( Rmr64); }\n@endif\n:AND Rmr16,usimm8_16\t\tis vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=4; usimm8_16\t{ logicalflags(); Rmr16 = Rmr16 & usimm8_16; resultflags( Rmr16); }\n:AND Rmr32,usimm8_32\t\tis vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=4; usimm8_32\t{ logicalflags(); Rmr32 = Rmr32 & usimm8_32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:AND Rmr64,usimm8_64\t\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=4; usimm8_64\t{ logicalflags(); Rmr64 = Rmr64 & usimm8_64; resultflags( Rmr64); }\n@endif\n:AND Rmr8,Reg8 is vexMode=0 & byte=0x20; mod=3 & Rmr8 & Reg8 { logicalflags(); Rmr8 = Rmr8 & Reg8; resultflags( Rmr8); }\n:AND Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x21; mod=3 & Rmr16 & Reg16 { logicalflags(); Rmr16 = Rmr16 & Reg16; resultflags( Rmr16); }\n:AND Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x21; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { logicalflags(); Rmr32 = Rmr32 & Reg32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:AND Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x21; mod=3 & Rmr64 & Reg64 { logicalflags(); Rmr64 = Rmr64 & Reg64; resultflags( Rmr64); }\n@endif\n:AND Reg8,rm8 is vexMode=0 & byte=0x22; rm8 & Reg8 ... { logicalflags(); Reg8 = Reg8 & rm8; resultflags( Reg8); }\n:AND Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x23; rm16 & Reg16 ... { logicalflags(); Reg16 = Reg16 & rm16; resultflags(Reg16); }\n:AND Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x23; rm32 & Reg32 ... & check_Reg32_dest ... { logicalflags(); Reg32 = Reg32 & rm32; build check_Reg32_dest; resultflags(Reg32); }\n@ifdef IA64\n:AND Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x23; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 & rm64; resultflags(Reg64); }\n@endif\n\n#ARPL is not encodable in 64-bit mode\n:ARPL rm16,Reg16 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & byte=0x63; rm16 & Reg16 ... { local rpldest=rm16&3; local rplsrc=Reg16&3; local rpldiff=rplsrc-rpldest;\n ZF = rpldiff s> 0; rm16 = rm16 + (zext(CF) * rpldiff); }\n\n:BOUND Reg16,m16 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & opsize=0 & byte=0x62; m16 & Reg16 ... { }\n:BOUND Reg32,m32 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & opsize=1 & byte=0x62; m32 & Reg32 ... { }\n\n#:BSF Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbc; rm16 & Reg16 ... { ZF = rm16 == 0;\n# choose = 0xffff * (zext((0xff & rm16) == 0));\n# mask = (0xf00 & choose) | (0xf | ~choose);\n# pos = 8 & choose;\n# choose = 0xffff * (zext((mask & rm16) == 0));\n# mask1 = (mask << 2) & (mask << 4);\n# mask2 = (mask >> 2) & mask;\n# mask = (mask1 & choose) | (mask2 | ~choose);\n# pos = pos + (4 & choose);\n# choose = 0xffff * (zext((mask & rm16) == 0));\n# mask1 = (mask << 1) & (mask << 2);\n# mask2 = (mask >> 1) & mask;\n# mask = (mask1 & choose) | (mask2 | ~choose);\n# pos = pos + (2 & choose);\n# choose = zext((mask & rm16) == 0);\n# Reg16 = pos + choose; }\n \n:BSF Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbc; rm16 & Reg16 ...\n{\n bitIndex:2 = 0;\n\n ZF = ( rm16 == 0 );\n \n if ( ZF == 1 ) goto ;\n \n\n if ( ((rm16 >> bitIndex) & 0x0001) != 0 ) goto ;\n bitIndex = bitIndex + 1;\n goto ;\n \n\n Reg16 = bitIndex;\n} \n\n#:BSF Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbc; rm32 & Reg32 ... & check_Reg32_dest ... { ZF = rm32 == 0; \n# choose = 0xffffffff * (zext((0xffff & rm32) == 0));\n# mask = (0xff0000 & choose) | (0xff | ~choose); \n# pos = 16 & choose; \n# choose = 0xffffffff * (zext((mask & rm32) == 0)); \n# mask1 = (mask << 4) & (mask << 8); \n# mask2 = (mask >> 4) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos + (8 & choose); \n# choose = 0xffffffff * (zext((mask & rm32) == 0)); \n# mask1 = (mask << 2) & (mask << 4); \n# mask2 = (mask >> 2) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos + (4 & choose); \n# choose = 0xffffffff * (zext((mask & rm32) == 0)); \n# mask1 = (mask << 1) & (mask << 2); \n# mask2 = (mask >> 1) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos + (2 & choose); \n# choose = zext((mask & rm32) == 0); \n# Reg32 = pos + choose; \n# build check_Reg32_dest; }\n\n:BSF Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbc; rm32 & Reg32 ... & check_Reg32_dest ... \n{\n bitIndex:4 = 0;\n\n ZF = ( rm32 == 0 );\n \n if ( ZF == 1 ) goto ;\n \n\n if ( ((rm32 >> bitIndex) & 0x00000001) != 0 ) goto ;\n bitIndex = bitIndex + 1;\n goto ;\n \n\n Reg32 = bitIndex;\n build check_Reg32_dest;\n} \n \n@ifdef IA64\n#:BSF Reg64,rm64 is vexMode=0 & opsize=2 & byte=0xf; byte=0xbc; rm64 & Reg64 ... { ZF = rm64 == 0;\n## TODO: NEED TO EXTEND THIS TO 64bit op \n# choose = 0xffffffff * (zext((0xffff & rm64) == 0));\n# mask = (0xff0000 & choose) | (0xff | ~choose); \n# pos = 16 & choose; \n# choose = 0xffffffff * (zext((mask & rm64) == 0)); \n# mask1 = (mask << 4) & (mask << 8); \n# mask2 = (mask >> 4) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos + (8 & choose); \n# choose = 0xffffffff * (zext((mask & rm64) == 0)); \n# mask1 = (mask << 2) & (mask << 4); \n# mask2 = (mask >> 2) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos + (4 & choose); \n# choose = 0xffffffff * (zext((mask & rm64) == 0)); \n# mask1 = (mask << 1) & (mask << 2); \n# mask2 = (mask >> 1) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos + (2 & choose); \n# choose = zext((mask & rm64) == 0); \n# Reg64 = pos + choose; } \n\n:BSF Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbc; rm64 & Reg64 ... \n{\n bitIndex:8 = 0;\n\n ZF = ( rm64 == 0 );\n \n if ( ZF == 1 ) goto ;\n \n\n if ( ((rm64 >> bitIndex) & 0x0000000000000001) != 0 ) goto ;\n bitIndex = bitIndex + 1;\n goto ;\n \n\n Reg64 = bitIndex;\n} \n@endif\n\n#:BSR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbd; rm16 & Reg16 ... { ZF = rm16 == 0; \n# choose = 0xffff * (zext((0xff00 & rm16) == 0));\n# mask = (0xf000 & ~choose) | (0xf0 | choose); \n# pos = 16 - (8 & choose); \n# choose = 0xffff * (zext((mask & rm16) == 0)); \n# mask1 = (mask >> 2) & (mask >> 4); \n# mask2 = (mask << 2) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (4 & choose); \n# choose = 0xffff * (zext((mask & rm16) == 0)); \n# mask1 = (mask >> 1) & (mask >> 2); \n# mask2 = (mask << 1) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (2 & choose); \n# choose = zext((mask & rm16) == 0); \n# Reg16 = pos - choose; } \n\n:BSR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbd; rm16 & Reg16 ... \n{\n bitIndex:2 = 15;\n\n ZF = ( rm16 == 0 );\n \n if ( ZF == 1 ) goto ;\n \n\n if ( (rm16 >> bitIndex) != 0 ) goto ;\n bitIndex = bitIndex - 1;\n goto ;\n \n\n Reg16 = bitIndex;\n} \n\n#:BSR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbd; rm32 & Reg32 ... & check_Reg32_dest ... { ZF = rm32 == 0; \n# choose = 0xffffffff * (zext((0xffff0000 & rm32) == 0)); \n# mask = (0xff000000 & ~choose) | (0xff00 | choose); \n# pos = 32 - (16 & choose); \n# choose = 0xffffffff * (zext((mask & rm32) == 0)); \n# mask1 = (mask >> 4) & (mask >> 8); \n# mask2 = (mask << 4) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (8 & choose); \n# choose = 0xffffffff * (zext((mask & rm32) == 0)); \n# mask1 = (mask >> 2) & (mask >> 4); \n# mask2 = (mask << 2) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (4 & choose); \n# choose = 0xffffffff * (zext((mask & rm32) == 0)); \n# mask1 = (mask >> 1) & (mask >> 2); \n# mask2 = (mask << 1) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (2 & choose); \n# choose = zext((mask & rm32) == 0); \n# Reg32 = pos - choose; \n# build check_Reg32_dest; }\n \n:BSR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbd; rm32 & Reg32 ... & check_Reg32_dest ...\n{\n bitIndex:4 = 31;\n\n ZF = ( rm32 == 0 );\n \n if ( ZF == 1 ) goto ;\n \n\n if ( (rm32 >> bitIndex) != 0 ) goto ;\n bitIndex = bitIndex - 1;\n goto ;\n \n\n Reg32 = bitIndex;\n build check_Reg32_dest;\n} \n\n\n@ifdef IA64\n#:BSR Reg64,rm64 is vexMode=0 & opsize=2 & byte=0xf; byte=0xbd; rm64 & Reg64 ... { ZF = rm64 == 0; \n## TODO: NEED TO EXTEND THIS TO 64bit op \n# choose = 0xffffffff * (zext((0xffff0000 & rm64) == 0)); \n# mask = (0xff000000 & ~choose) | (0xff00 | choose); \n# pos = 32 - (16 & choose); \n# choose = 0xffffffff * (zext((mask & rm64) == 0)); \n# mask1 = (mask >> 4) & (mask >> 8); \n# mask2 = (mask << 4) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (8 & choose); \n# choose = 0xffffffff * (zext((mask & rm64) == 0)); \n# mask1 = (mask >> 2) & (mask >> 4); \n# mask2 = (mask << 2) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (4 & choose); \n# choose = 0xffffffff * (zext((mask & rm64) == 0)); \n# mask1 = (mask >> 1) & (mask >> 2); \n# mask2 = (mask << 1) & mask; \n# mask = (mask1 & choose) | (mask2 | ~choose); \n# pos = pos - (2 & choose); \n# choose = zext((mask & rm64) == 0); \n# Reg64 = pos - choose; } \n\n:BSR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbd; rm64 & Reg64 ... \n{\n bitIndex:8 = 63;\n\n ZF = ( rm64 == 0 );\n \n if ( ZF == 1 ) goto ;\n \n\n if ( (rm64 >> bitIndex) != 0 ) goto ;\n bitIndex = bitIndex - 1;\n goto ;\n \n\n Reg64 = bitIndex;\n} \n\n@endif\n\n:BSWAP Rmr32 is vexMode=0 & byte=0xf; row=12 & page=1 & Rmr32 & check_Rmr32_dest\n { local tmp = (Rmr32 & 0xff000000) >> 24 ;\n tmp = tmp | ((Rmr32 & 0x00ff0000) >> 8 );\n tmp = tmp | ((Rmr32 & 0x0000ff00) << 8 );\n Rmr32 = tmp | ((Rmr32 & 0x000000ff) << 24); \n build check_Rmr32_dest; }\n@ifdef IA64\n:BSWAP Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; row=12 & page=1 & Rmr64\n { local tmp = (Rmr64 & 0xff00000000000000) >> 56 ;\n tmp = tmp | ((Rmr64 & 0x00ff000000000000) >> 40 );\n tmp = tmp | ((Rmr64 & 0x0000ff0000000000) >> 24 );\n tmp = tmp | ((Rmr64 & 0x000000ff00000000) >> 8 );\n tmp = tmp | ((Rmr64 & 0x00000000ff000000) << 8 );\n tmp = tmp | ((Rmr64 & 0x0000000000ff0000) << 24 );\n tmp = tmp | ((Rmr64 & 0x000000000000ff00) << 40 );\n Rmr64 = tmp | ((Rmr64 & 0x00000000000000ff) << 56); }\n@endif\n\n:BT Rmr16,Reg16\t\tis vexMode=0 & opsize=0 & byte=0xf; byte=0xa3; mod=3 & Rmr16 & Reg16\t\t{ CF = ((Rmr16 >> (Reg16 & 0xf)) & 1) != 0; }\n:BT Mem,Reg16\t\tis vexMode=0 & opsize=0 & byte=0xf; byte=0xa3; Mem & Reg16 ...\t\t{ local ptr = Mem + (sext(Reg16) s>> 3);\n\t\t\t\t\t\t\t\t\t\t\t CF = ((*:1 ptr >> (Reg16 & 0x7)) & 1) != 0; }\n:BT Rmr32,Reg32\t\tis vexMode=0 & opsize=1 & byte=0xf; byte=0xa3; mod=3 & Rmr32 & Reg32\t\t{ CF = ((Rmr32 >> (Reg32 & 0x1f)) & 1) != 0; }\n:BT Mem,Reg32\t\tis vexMode=0 & opsize=1 & byte=0xf; byte=0xa3; Mem & Reg32 ...\t\t{\n@ifdef IA64\n local ptr = Mem + (sext(Reg32) s>> 3);\n@else\n local ptr = Mem + (Reg32 s>> 3);\n@endif\n CF = ((*:1 ptr >> (Reg32 & 0x7)) & 1) != 0;\n}\n@ifdef IA64\n:BT Rmr64,Reg64\t\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xa3; mod=3 & Rmr64 & Reg64\t\t{ CF = ((Rmr64 >> (Reg64 & 0x3f)) & 1) != 0; }\n:BT Mem,Reg64\t\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xa3; Mem & Reg64 ...\t\t{ local ptr = Mem + (Reg64 s>> 3);\n\t\t\t\t\t\t\t\t\t\t\t CF = ((*:1 ptr >> (Reg64 & 0x7)) & 1) != 0; }\n@endif\n:BT rm16,imm8 is vexMode=0 & opsize=0 & byte=0xf; byte=0xba; (rm16 & reg_opcode=4 ...); imm8 { CF = ((rm16 >> (imm8 & 0x0f)) & 1) != 0; } \n:BT rm32,imm8 is vexMode=0 & opsize=1 & byte=0xf; byte=0xba; (rm32 & reg_opcode=4 ...); imm8 { CF = ((rm32 >> (imm8 & 0x1f)) & 1) != 0; }\n@ifdef IA64\n:BT rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xba; (rm64 & reg_opcode=4 ...); imm8 { CF = ((rm64 >> (imm8 & 0x3f)) & 1) != 0; }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:BTC Rmr16,Reg16\tis vexMode=0 & opsize=0 & byte=0xf; byte=0xbb; mod=3 & Rmr16 & Reg16\t\t{ local bit=Reg16&0xf; local val=(Rmr16>>bit)&1; Rmr16=Rmr16^(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32^(1<>bit)&1; Rmr64=Rmr64^(1<>bit)&1; Rmr16=Rmr16^(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32^(1<>bit)&1; Rmr64=Rmr64^(1<>bit)&1; Rmr16=Rmr16 & ~(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 & ~(1<>bit)&1; Rmr64=Rmr64 & ~(1<>bit)&1; Rmr16=Rmr16 & ~(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 & ~(1<>bit)&1; Rmr64=Rmr64 & ~(1<>bit)&1; Rmr16=Rmr16 | (1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 | (1<>bit)&1; Rmr64=Rmr64 | (1<>bit)&1; Rmr16=Rmr16 | (1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 | (1<>bit)&1; Rmr64=Rmr64 | (1<;\n AL = dest;\n goto inst_next;\n\n Rmr8 = Reg8;\n }\n:CMPXCHG Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xb1; mod=3 & Rmr16 & Reg16 \n{ \n local dest = Rmr16;\n subflags(AX,dest); \n local diff = AX-dest; \n resultflags(diff);\n if (ZF) goto ;\n AX = dest;\n goto inst_next;\n\n Rmr16 = Reg16;\n }\n:CMPXCHG Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xb1; mod=3 & Rmr32 & Reg32 & check_EAX_dest & check_Rmr32_dest\n{\n\t#this instruction writes to either EAX or Rmr32\n\t#in 64-bit mode, a 32-bit register that is written to \n\t#(and only the register that is written to) \n\t#must be zero-extended to 64 bits\n local dest = Rmr32;\n subflags(EAX,dest); \n local diff = EAX-dest; \n resultflags(diff);\n if (ZF) goto ;\n EAX = dest;\n build check_EAX_dest;\n goto inst_next;\n\n Rmr32 = Reg32;\n build check_Rmr32_dest;\n}\n@ifdef IA64\n:CMPXCHG Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xb1; mod=3 & Rmr64 & Reg64 \n{ \n local dest = Rmr64;\n subflags(RAX,dest); \n local diff = RAX-dest; \n resultflags(diff);\n if (ZF) goto ;\n RAX = dest;\n goto inst_next;\n\n Rmr64 = Reg64;\n} \n@endif\n\n# CMPXCHG8B See 'lockable.sinc' for memory destination, lockable variants\n\n# This \"bad_CMPXCHG8B\" instruction encoding was not meant to be part of the x86 language.\n# It was allowed by a toolchain (at Intel) and was encoded into at least one library.\n# GCC does not recognize it. It does not make any semantic sense.\ndefine pcodeop bad_CMPXCHG8B;\n:bad_CMPXCHG8B r32 is vexMode=0 & byte=0xf; byte=0xc7; ( mod = 0b11 & reg_opcode=0b001 ) & r32 {\n r32 = bad_CMPXCHG8B(r32);\n}\n\n# CMPXCHG16B See 'lockable.sinc' for memory destination, lockable variants\n\ndefine pcodeop cpuid;\ndefine pcodeop cpuid_basic_info;\ndefine pcodeop cpuid_Version_info;\ndefine pcodeop cpuid_cache_tlb_info;\ndefine pcodeop cpuid_serial_info;\ndefine pcodeop cpuid_Deterministic_Cache_Parameters_info;\ndefine pcodeop cpuid_MONITOR_MWAIT_Features_info;\ndefine pcodeop cpuid_Thermal_Power_Management_info;\ndefine pcodeop cpuid_Extended_Feature_Enumeration_info;\ndefine pcodeop cpuid_Direct_Cache_Access_info;\ndefine pcodeop cpuid_Architectural_Performance_Monitoring_info;\ndefine pcodeop cpuid_Extended_Topology_info;\ndefine pcodeop cpuid_Processor_Extended_States_info;\ndefine pcodeop cpuid_Quality_of_Service_info;\ndefine pcodeop cpuid_brand_part1_info;\ndefine pcodeop cpuid_brand_part2_info;\ndefine pcodeop cpuid_brand_part3_info;\n\n# CPUID is very difficult to implement correctly\n# The side-effects of the call will show up, but not the correct values\n\n:CPUID is vexMode=0 & byte=0xf; byte=0xa2 {\n tmpptr:$(SIZE) = 0;\n if (EAX == 0) goto ;\n if (EAX == 1) goto ;\n if (EAX == 2) goto ;\n if (EAX == 3) goto ;\n if (EAX == 0x4) goto ;\n if (EAX == 0x5) goto ;\n if (EAX == 0x6) goto ;\n if (EAX == 0x7) goto ;\n if (EAX == 0x9) goto ;\n if (EAX == 0xa) goto ;\n if (EAX == 0xb) goto ;\n if (EAX == 0xd) goto ;\n if (EAX == 0xf) goto ;\n if (EAX == 0x80000002) goto ;\n if (EAX == 0x80000003) goto ;\n if (EAX == 0x80000004) goto ;\n tmpptr = cpuid(EAX);\n goto ;\n \n tmpptr = cpuid_basic_info(EAX);\n goto ;\n \n tmpptr = cpuid_Version_info(EAX);\n goto ;\n \n tmpptr = cpuid_cache_tlb_info(EAX);\n goto ;\n \n tmpptr = cpuid_serial_info(EAX);\n goto ;\n \n tmpptr = cpuid_Deterministic_Cache_Parameters_info(EAX);\n goto ; \n \n tmpptr = cpuid_MONITOR_MWAIT_Features_info(EAX);\n goto ; \n \n tmpptr = cpuid_Thermal_Power_Management_info(EAX);\n goto ;\n \n tmpptr = cpuid_Extended_Feature_Enumeration_info(EAX);\n goto ;\n \n tmpptr = cpuid_Direct_Cache_Access_info(EAX);\n goto ;\n \n tmpptr = cpuid_Architectural_Performance_Monitoring_info(EAX);\n goto ;\n \n tmpptr = cpuid_Extended_Topology_info(EAX);\n goto ;\n \n tmpptr = cpuid_Processor_Extended_States_info(EAX);\n goto ;\n \n tmpptr = cpuid_Quality_of_Service_info(EAX);\n goto ;\n \n tmpptr = cpuid_brand_part1_info(EAX);\n goto ;\n \n tmpptr = cpuid_brand_part2_info(EAX);\n goto ;\n \n tmpptr = cpuid_brand_part3_info(EAX);\n goto ; \n \n@ifdef IA64\n\tRAX = zext(*:4 (tmpptr));\n\tRBX = zext(*:4 (tmpptr + 4));\n\tRDX = zext(*:4 (tmpptr + 8));\n\tRCX = zext(*:4 (tmpptr + 12));\n@else\n\tEAX = *tmpptr;\n\tEBX = *(tmpptr + 4);\n\tEDX = *(tmpptr + 8);\n\tECX = *(tmpptr + 12);\n@endif\n}\n\n\n:DAA is vexMode=0 & bit64=0 & byte=0x27 { local car = ((AL & 0xf) > 9) | AF;\n AL = AL + 6 * car;\n CF = CF | car * carry(AL,6);\n AF = car;\n car = ((AL & 0xf0) > 0x90) | CF;\n AL = AL + 0x60 * car;\n CF = car; }\n:DAS is vexMode=0 & bit64=0 & byte=0x2f { local car = ((AL & 0xf) > 9) | AF;\n AL = AL - 6 * car;\n CF = CF | car * (AL < 6);\n AF = car;\n car = (AL > 0x9f) | CF;\n AL = AL - 0x60 * car;\n CF = car; }\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:DEC Rmr8 is vexMode=0 & byte=0xfe; mod=3 & Rmr8 & reg_opcode=1 { OF = sborrow(Rmr8,1); Rmr8 = Rmr8 - 1; resultflags( Rmr8); }\n:DEC Rmr16 is vexMode=0 & opsize=0 & byte=0xff; mod=3 & Rmr16 & reg_opcode=1 { OF = sborrow(Rmr16,1); Rmr16 = Rmr16 - 1; resultflags(Rmr16); }\n:DEC Rmr32 is vexMode=0 & opsize=1 & byte=0xff; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=1 { OF = sborrow(Rmr32,1); Rmr32 = Rmr32 - 1; build check_rm32_dest; resultflags(Rmr32); }\n@ifdef IA64\n:DEC Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xff; mod=3 & Rmr64 & reg_opcode=1 { OF = sborrow(Rmr64,1); Rmr64 = Rmr64 - 1; resultflags(Rmr64); }\n@endif\n\n:DEC Rmr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & row=4 & page=1 & Rmr16 { OF = sborrow(Rmr16,1); Rmr16 = Rmr16 - 1; resultflags( Rmr16); }\n:DEC Rmr32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & row=4 & page=1 & Rmr32 & check_Rmr32_dest { OF = sborrow(Rmr32,1); Rmr32 = Rmr32 - 1; build check_Rmr32_dest; resultflags( Rmr32); }\n\n:DIV rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=6 ... { rm8ext:2 = zext(rm8);\n local quotient = AX / rm8ext; # DE exception if quotient doesn't fit in AL\n local rem = AX % rm8ext;\n AL = quotient:1;\n AH = rem:1; }\n:DIV rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=6 ... { rm16ext:4 = zext(rm16);\n tmp:4 = (zext(DX) << 16) | zext(AX); # DE exception if quotient doesn't fit in AX\n local quotient = tmp / rm16ext;\n AX = quotient:2;\n local rem = tmp % rm16ext;\n DX = rem:2; }\n:DIV rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EDX_dest ... & check_EAX_dest ... & reg_opcode=6 ... { rm32ext:8 = zext(rm32);\n tmp:8 = (zext(EDX) << 32) | zext(EAX); # DE exception if quotient doesn't fit in EAX\n local quotient = tmp / rm32ext;\n EAX = quotient:4;\n build check_EAX_dest;\n local rem = tmp % rm32ext;\n EDX = rem:4;\n build check_EDX_dest; }\n@ifdef IA64\n:DIV rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=6 ... { rm64ext:16 = zext(rm64);\n tmp:16 = (zext(RDX) << 64) | zext(RAX); # DE exception if quotient doesn't fit in RAX\n local quotient = tmp / rm64ext;\n RAX = quotient:8;\n local rem = tmp % rm64ext;\n RDX = rem:8; } \n@endif\n\nenterFrames: low5 is low5 { tmp:1 = low5; export tmp; }\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc8; imm16; enterFrames & low5=0x00 {\n push44(EBP);\n EBP = ESP;\n ESP = ESP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc8; imm16; enterFrames & low5=0x01 {\n push44(EBP);\n frameTemp:4 = ESP;\n\n push44(frameTemp);\n EBP = frameTemp;\n ESP = ESP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc8; imm16; enterFrames {\n push44(EBP);\n frameTemp:4 = ESP;\n@ifdef IA64\n ESPt:$(SIZE) = zext(ESP);\n EBPt:$(SIZE) = zext(EBP);\n@else\n ESPt:$(SIZE) = ESP;\n EBPt:$(SIZE) = EBP;\n@endif\n\n ii:1 = enterFrames - 1;\n\n EBPt = EBPt - 4;\n ESPt = ESPt - 4;\n *:4 ESPt = *:4 EBPt;\n ii = ii - 1;\n if (ii s> 0) goto ;\n\n tmp_offset:4 = 4 * zext(enterFrames - 1);\n ESP = ESP - tmp_offset;\n EBP = EBP - tmp_offset;\n\n push44(frameTemp);\n EBP = frameTemp;\n ESP = ESP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc8; imm16; enterFrames & low5=0x00 {\n push42(BP);\n BP = SP;\n SP = SP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc8; imm16; enterFrames & low5=0x01 {\n push42(BP);\n frameTemp:2 = SP;\n\n push42(frameTemp);\n BP = frameTemp;\n SP = SP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc8; imm16; enterFrames {\n push42(BP);\n frameTemp:2 = SP;\n@ifdef IA64\n ESPt:$(SIZE) = zext(ESP);\n EBPt:$(SIZE) = zext(EBP);\n@else\n ESPt:$(SIZE) = ESP;\n EBPt:$(SIZE) = EBP;\n@endif\n\n ii:1 = enterFrames - 1;\n\n EBPt = EBPt - 2;\n ESPt = ESPt - 2;\n *:2 ESPt = *:2 EBPt;\n ii = ii - 1;\n if (ii s> 0) goto ;\n\n tmp_offset:4 = 2 * zext(enterFrames - 1);\n ESP = ESP - tmp_offset;\n EBP = EBP - tmp_offset;\n\n push42(frameTemp);\n BP = frameTemp;\n SP = SP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xc8; imm16; enterFrames & low5=0x00 {\n push22(BP);\n BP = SP;\n SP = SP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xc8; imm16; enterFrames & low5=0x01 {\n push22(BP);\n frameTemp:2 = SP;\n\n push22(frameTemp);\n BP = frameTemp;\n SP = SP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & seg16 & addrsize=0 & opsize=1 & byte=0xc8; imm16; enterFrames {\n push24(zext(BP));\n frameTemp:2 = SP;\n\n SPt:2 = SP;\n BPt:2 = BP;\n ii:1 = enterFrames - 1;\n\n\n BPt = BPt - 4;\n tmp2:$(SIZE) = segment(seg16,BPt);\n SPt = SPt - 4;\n tmp:$(SIZE) = segment(SS,SPt);\n *:4 tmp = *:4 tmp2;\n ii = ii - 1;\n if (ii s> 0) goto ;\n\n tmp_offset:2 = 4 * zext(enterFrames - 1);\n SP = SP - tmp_offset;\n BP = BP - tmp_offset;\n\n push24(zext(frameTemp));\n BP = frameTemp;\n SP = SP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & seg16 & addrsize=0 & opsize=0 & byte=0xc8; imm16; enterFrames {\n push22(BP);\n frameTemp:2 = SP;\n\n SPt:2 = SP;\n BPt:2 = BP;\n ii:1 = enterFrames - 1;\n\n BPt = BPt - 2;\n tmp2:$(SIZE) = segment(seg16,BPt);\n SPt = SPt - 2;\n tmp:$(SIZE) = segment(SS,SPt);\n *:2 tmp = *:2 tmp2;\n ii = ii - 1;\n if (ii s> 0) goto ;\n\n tmp_offset:2 = 2 * zext(enterFrames - 1);\n SP = SP - tmp_offset;\n BP = BP - tmp_offset;\n\n push22(frameTemp);\n BP = frameTemp;\n SP = SP - imm16;\n}\n\n@ifdef IA64\n:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & byte=0xc8; imm16; enterFrames & low5=0x00 {\n push88(RBP);\n RBP = RSP;\n RSP = RSP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & byte=0xc8; imm16; enterFrames & low5=0x01 {\n push88(RBP);\n frameTemp:8 = RSP;\n\n push88(frameTemp);\n RBP = frameTemp;\n RSP = RSP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & byte=0xc8; imm16; enterFrames {\n push88(RBP);\n frameTemp:8 = RSP;\n\n RSPt:$(SIZE) = RSP;\n RBPt:$(SIZE) = RBP;\n ii:1 = enterFrames - 1;\n\n RBPt = RBPt - 8;\n RSPt = RSPt - 8;\n *:8 RSPt = *:8 RBPt;\n ii = ii - 1;\n if (ii s> 0) goto ;\n\n tmp_offset:8 = 8 * zext(enterFrames - 1);\n RSP = RSP - tmp_offset;\n RBP = RBP - tmp_offset;\n\n push88(frameTemp);\n RBP = frameTemp;\n RSP = RSP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xc8; imm16; enterFrames & low5=0x00 {\n push82(BP);\n RBP = RSP;\n RSP = RSP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xc8; imm16; enterFrames & low5=0x01 {\n push82(BP);\n frameTemp:2 = SP;\n\n push82(frameTemp);\n BP = frameTemp;\n RSP = RSP - imm16;\n}\n\n:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xc8; imm16; enterFrames {\n push82(BP);\n frameTemp:2 = SP;\n\n RSPt:$(SIZE) = RSP;\n RBPt:$(SIZE) = RBP;\n ii:1 = enterFrames - 1;\n\n RBPt = RBPt - 2;\n RSPt = RSPt - 2;\n *:2 RSPt = *:2 RBPt;\n ii = ii - 1;\n if (ii s> 0) goto ;\n\n tmp_offset:8 = 2 * zext(enterFrames - 1);\n RSP = RSP - tmp_offset;\n RBP = RBP - tmp_offset;\n\n push82(frameTemp);\n BP = frameTemp;\n RSP = RSP - imm16;\n}\n@endif\n\n\n\n# Informs the 80287 coprocessor of the switch to protected mode, treated as NOP for 80387 and later.\n# We used to have a pseudo-op, but as this is a legacy instruction which is now explicitly treated\n# as a NOP. We treat it as a NOP as well.\n:FSETPM \tis vexMode=0 & byte=0xdb; byte=0xe4\t{ } # 80287 set protected mode\n\n:HLT is vexMode=0 & byte=0xf4 { goto inst_start; }\n\n:IDIV rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=7 ... { rm8ext:2 = sext(rm8);\n local quotient = AX s/ rm8ext; # DE exception if quotient doesn't fit in AL\n local rem = AX s% rm8ext;\n AL = quotient:1;\n AH = rem:1; }\n:IDIV rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=7 ... { rm16ext:4 = sext(rm16);\n tmp:4 = (zext(DX) << 16) | zext(AX); # DE exception if quotient doesn't fit in AX\n local quotient = tmp s/ rm16ext;\n AX = quotient:2;\n local rem = tmp s% rm16ext;\n DX = rem:2; }\n:IDIV rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EAX_dest ... & check_EDX_dest ... & reg_opcode=7 ... { rm32ext:8 = sext(rm32);\n tmp:8 = (zext(EDX) << 32) | zext(EAX); # DE exception if quotient doesn't fit in EAX\n local quotient = tmp s/ rm32ext;\n EAX = quotient:4;\n build check_EAX_dest;\n local rem = tmp s% rm32ext;\n EDX = rem:4; \n build check_EDX_dest; }\n@ifdef IA64\n:IDIV rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=7 ... { rm64ext:16 = sext(rm64);\n tmp:16 = (zext(RDX) << 64) | zext(RAX); # DE exception if quotient doesn't fit in RAX\n local quotient = tmp s/ rm64ext;\n RAX = quotient:8;\n local rem = tmp s% rm64ext;\n RDX = rem:8; }\n@endif\n\n:IMUL rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=5 ... { AX = sext(AL) * sext(rm8); imultflags(AL,AX); } \n:IMUL rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=5 ... { tmp:4 = sext(AX) * sext(rm16);\n DX = tmp(2); AX = tmp(0); imultflags(AX,tmp); }\n:IMUL rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EAX_dest ... & check_EDX_dest ... & reg_opcode=5 ... { tmp:8 = sext(EAX) * sext(rm32);\n EDX = tmp(4); build check_EDX_dest; EAX = tmp(0); build check_EAX_dest; imultflags(EAX,tmp); }\n@ifdef IA64\n# We do a second multiply so emulator(s) that only have precision up to 64 bits will still get lower 64 bits correct\n:IMUL rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=5 ... { tmp:16 = sext(RAX) * sext(rm64);\n RAX = RAX * rm64; RDX = tmp(8); imultflags(RAX,tmp); }\n@endif\n:IMUL Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xaf; rm16 & Reg16 ... { tmp:4 = sext(Reg16) * sext(rm16);\n Reg16 = tmp(0); high:2 = tmp(2); imultflags(Reg16,tmp);}\n:IMUL Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xaf; rm32 & Reg32 ... & check_Reg32_dest ... { tmp:8 = sext(Reg32) * sext(rm32);\n Reg32 = tmp(0); high:4 = tmp(4); imultflags(Reg32,tmp); build check_Reg32_dest; }\n@ifdef IA64\n# We do a second multiply so emulator(s) that only have precision up to 64 bits will still get lower 64 bits correct\n:IMUL Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xaf; rm64 & Reg64 ... { tmp:16 = sext(Reg64) * sext(rm64);\n Reg64 = Reg64 * rm64; high:8 = tmp(8); imultflags(Reg64,tmp);}\n@endif\n:IMUL Reg16,rm16,simm8_16 is vexMode=0 & opsize=0 & byte=0x6b; (rm16 & Reg16 ...) ; simm8_16 { tmp:4 = sext(rm16) * sext(simm8_16);\n Reg16 = tmp(0); high:2 = tmp(2); imultflags(Reg16,tmp);}\n:IMUL Reg32,rm32,simm8_32 is vexMode=0 & opsize=1 & byte=0x6b; (rm32 & Reg32 ... & check_Reg32_dest ... ) ; simm8_32 { tmp:8 = sext(rm32) * sext(simm8_32);\n Reg32 = tmp(0); high:4 = tmp(4); imultflags(Reg32,tmp); build check_Reg32_dest; }\n@ifdef IA64\n# We do a second multiply so emulator(s) that only have precision up to 64 bits will still get lower 64 bits correct\n:IMUL Reg64,rm64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x6b; (rm64 & Reg64 ...) ; simm8_64 { tmp:16 = sext(rm64) * sext(simm8_64);\n Reg64 = rm64 * simm8_64; high:8 = tmp(8); imultflags(Reg64,tmp);}\n@endif\n:IMUL Reg16,rm16,simm16_16 is vexMode=0 & opsize=0 & byte=0x69; (rm16 & Reg16 ...) ; simm16_16 { tmp:4 = sext(rm16) * sext(simm16_16);\n Reg16 = tmp(0); high:2 = tmp(2); imultflags(Reg16,tmp);}\n:IMUL Reg32,rm32,simm32_32 is vexMode=0 & opsize=1 & byte=0x69; (rm32 & Reg32 ... & check_Reg32_dest ...) ; simm32_32 { tmp:8 = sext(rm32) * sext(simm32_32);\n Reg32 = tmp(0); high:4 = tmp(4); imultflags(Reg32,tmp); build check_Reg32_dest; }\n@ifdef IA64\n:IMUL Reg64,rm64,simm32_32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x69; (rm64 & Reg64 ...) ; simm32_32 { tmp:16 = sext(rm64) * sext(simm32_32);\n Reg64 = rm64 * sext(simm32_32); high:8 = tmp(8); imultflags(Reg64,tmp);}\n@endif\n\n# these appear in intelman2.pdf, but do they really exist?\n#:IMUL Reg16,simm8_16 is vexMode=0 & opsize=0 & byte=0x6b; Reg16; simm8_16\n#:IMUL Reg32,simm8_32 is vexMode=0 & opsize=1 & byte=0x6b; Reg32; simm8_32\n#:IMUL Reg16,simm16 is vexMode=0 & opsize=0 & byte=0x69; Reg16; simm16\n#:IMUL Reg32,simm32 is vexMode=0 & opsize=1 & byte=0x69; Reg32; simm32\n\n:IN AL, imm8 is vexMode=0 & AL & (byte=0xe4; imm8) { tmp:1 = imm8; AL = in(tmp); }\n:IN AX, imm8 is vexMode=0 & opsize=0 & AX & (byte=0xe5; imm8) { tmp:1 = imm8; AX = in(tmp); }\n:IN EAX, imm8 is vexMode=0 & opsize=1 & EAX & check_EAX_dest & (byte=0xe5; imm8) { tmp:1 = imm8; EAX = in(tmp); build check_EAX_dest; }\n@ifdef IA64\n:IN RAX, imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & RAX & (byte=0xe5; imm8) { tmp:1 = imm8; RAX = in(tmp); }\n@endif\n:IN AL, DX is vexMode=0 & AL & DX & (byte=0xec) { AL = in(DX); }\n:IN AX, DX is vexMode=0 & opsize=0 & AX & DX & (byte=0xed) { AX = in(DX); }\n:IN EAX, DX is vexMode=0 & opsize=1 & EAX & check_EAX_dest & DX & (byte=0xed) { EAX = in(DX); build check_EAX_dest; }\n@ifdef IA64\n:IN RAX, DX is $(LONGMODE_ON) & vexMode=0 & opsize=2 & RAX & DX & (byte=0xed) { RAX = in(DX); }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:INC Rmr8\tis vexMode=0 & byte=0xfe; mod=3 & Rmr8 & reg_opcode=0\t\t\t{ OF = scarry(Rmr8,1); Rmr8 = Rmr8 + 1; resultflags( Rmr8); }\n:INC Rmr16\tis vexMode=0 & opsize=0 & byte=0xff; mod=3 & Rmr16 & reg_opcode=0\t{ OF = scarry(Rmr16,1); Rmr16 = Rmr16 + 1; resultflags(Rmr16); }\n:INC Rmr32\tis vexMode=0 & opsize=1 & byte=0xff; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0\t{ OF = scarry(Rmr32,1); Rmr32 = Rmr32 + 1; build check_Rmr32_dest; resultflags(Rmr32); }\n@ifdef IA64\n:INC Rmr64\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xff; mod=3 & Rmr64 & reg_opcode=0\t{ OF = scarry(Rmr64,1); Rmr64 = Rmr64 + 1; resultflags(Rmr64); }\n@endif\n\n:INC Rmr16\tis $(LONGMODE_OFF) & vexMode=0 & opsize=0 & row = 4 & page = 0 & Rmr16 { OF = scarry(Rmr16,1); Rmr16 = Rmr16 + 1; resultflags( Rmr16); }\n:INC Rmr32\tis $(LONGMODE_OFF) & vexMode=0 & opsize=1 & row = 4 & page = 0 & Rmr32 { OF = scarry(Rmr32,1); Rmr32 = Rmr32 + 1; resultflags( Rmr32); }\n\n:INSB^rep^reptail eseDI1,DX is vexMode=0 & rep & reptail & byte=0x6c & eseDI1 & DX { build rep; build eseDI1; eseDI1 = in(DX); build reptail; }\n:INSW^rep^reptail eseDI2,DX is vexMode=0 & rep & reptail & opsize=0 & byte=0x6d & eseDI2 & DX { build rep; build eseDI2; eseDI2 = in(DX); build reptail; }\n:INSD^rep^reptail eseDI4,DX is vexMode=0 & rep & reptail & opsize=1 & byte=0x6d & eseDI4 & DX { build rep; build eseDI4; eseDI4 = in(DX); build reptail; }\n:INSD^rep^reptail eseDI4,DX is vexMode=0 & rep & reptail & opsize=2 & byte=0x6d & eseDI4 & DX { build rep; build eseDI4; eseDI4 = in(DX); build reptail; }\n\n:INT1 is vexMode=0 & byte=0xf1 { tmp:1 = 0x1; intloc:$(SIZE) = swi(tmp); call [intloc]; return [0:1]; }\n:INT3 is vexMode=0 & byte=0xcc { tmp:1 = 0x3; intloc:$(SIZE) = swi(tmp); call [intloc]; return [0:1]; }\n:INT imm8 is vexMode=0 & byte=0xcd; imm8 { tmp:1 = imm8; intloc:$(SIZE) = swi(tmp); call [intloc]; }\n:INTO is vexMode=0 & byte=0xce & bit64=0\n{\n tmp:1 = 0x4;\n intloc:$(SIZE) = swi(tmp);\n\n if (OF != 1) goto ;\n call [intloc];\n \n}\n\n:INVD is vexMode=0 & byte=0xf; byte=0x8 {}\n:INVLPG Mem is vexMode=0 & byte=0xf; byte=0x1; ( reg_opcode=7 ) ... & Mem { invlpg(Mem); }\n\n:INVLPGA is vexMode=0 & addrsize=0 & byte=0xf; byte=0x1; byte=0xDF { invlpga(AX,ECX); }\n:INVLPGA is vexMode=0 & addrsize=1 & byte=0xf; byte=0x1; byte=0xDF { invlpga(EAX,ECX); }\n@ifdef IA64\n:INVLPGA is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; byte=0x1; byte=0xDF { invlpga(RAX,ECX); }\n@endif\n\n:INVPCID r32, m128 is vexMode=0 & addrsize=1 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x82; r32 ... & m128 { invpcid(r32, m128); }\n@ifdef IA64\n:INVPCID r64, m128 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x82; r64 ... & m128 { invpcid(r64, m128); }\n@endif\n\n:IRET is vexMode=0 & addrsize=0 & opsize=0 & byte=0xcf { pop22(IP); EIP=zext(IP); pop22(CS); pop22(flags); return [EIP]; } \n:IRET is vexMode=0 & addrsize=1 & opsize=0 & byte=0xcf { pop42(IP); EIP=zext(IP); pop42(CS); pop42(flags); return [EIP]; } \n@ifdef IA64\n:IRET is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xcf { pop82(IP); RIP=zext(IP); pop82(CS); pop82(flags); return [RIP]; } \n@endif\n:IRETD is vexMode=0 & addrsize=0 & opsize=1 & byte=0xcf { pop24(EIP); tmp:4=0; pop24(tmp); CS=tmp(0); pop24(tmp); flags=tmp(0); return [EIP]; }\n:IRETD is vexMode=0 & addrsize=1 & opsize=1 & byte=0xcf { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); pop44(eflags); return [EIP]; }\n@ifdef IA64\n:IRETD is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xcf { pop84(RIP); tmp:8=0; pop84(tmp); CS=tmp(0); pop84(eflags); return [RIP]; }\n:IRETQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcf { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); pop88(rflags); return [RIP]; }\n@endif\n\n:J^cc rel8 is vexMode=0 & row=7 & cc; rel8 { if (cc) goto rel8; }\n:J^cc rel16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; row=8 & cc; rel16 { if (cc) goto rel16; }\n:J^cc rel32 is vexMode=0 & opsize=1 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; }\n:J^cc rel32 is vexMode=0 & opsize=2 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; }\n# The following is vexMode=0 & picked up by the line above. rel32 works for both 32 and 64 bit\n#@ifdef IA64\n#:J^cc rel32 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; }\n#@endif\n\n:JCXZ rel8 is vexMode=0 & addrsize=0 & byte=0xe3; rel8 { if (CX==0) goto rel8; }\n:JECXZ rel8 is vexMode=0 & addrsize=1 & byte=0xe3; rel8 { if (ECX==0) goto rel8; }\n@ifdef IA64\n:JRCXZ rel8 is $(LONGMODE_ON) & addrsize=2 & vexMode=0 & byte=0xe3; rel8 { if (RCX==0) goto rel8; }\n@endif\n\n:JMP rel8 is vexMode=0 & byte=0xeb; rel8 { goto rel8; }\n:JMP rel16 is vexMode=0 & opsize=0 & byte=0xe9; rel16 { goto rel16; }\n:JMP rel32 is vexMode=0 & opsize=1 & byte=0xe9; rel32 { goto rel32; }\n:JMP rel32 is vexMode=0 & opsize=2 & byte=0xe9; rel32 { goto rel32; }\n\n:JMP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xff & currentCS; rm16 & reg_opcode=4 ...\t{ target:4 = segment(currentCS,rm16); goto [target]; }\n:JMP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xff; rm16 & reg_opcode=4 ...\t{ goto [rm16]; }\n:JMP rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xff; rm32 & reg_opcode=4 ... { goto [rm32]; }\n@ifdef IA64\n:JMP rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xff & currentCS; rm16 & reg_opcode=4 ...\t{ goto [rm16]; }\n:JMP rm64 is $(LONGMODE_ON) & vexMode=0 & byte=0xff; rm64 & reg_opcode=4 ... { goto [rm64]; }\n@endif\n\n:JMPF ptr1616 is vexMode=0 & opsize=0 & byte=0xea; ptr1616 { goto ptr1616; }\n:JMPF ptr1632 is vexMode=0 & opsize=1 & byte=0xea; ptr1632 { goto ptr1632; }\n:JMPF Mem is vexMode=0 & opsize=0 & byte=0xff; Mem & reg_opcode=5 ... { target:$(SIZE) = zext(*:2 Mem); goto [target]; }\n:JMPF Mem is vexMode=0 & opsize=1 & byte=0xff; Mem & reg_opcode=5 ... {\n@ifdef IA64\n target:$(SIZE) = zext(*:4 Mem);\n@else\n target:$(SIZE) = *:4 Mem;\n@endif\n goto [target];\n}\n@ifdef IA64\n:JMPF Mem is vexMode=0 & opsize=2 & byte=0xff; Mem & reg_opcode=5 ... { target:$(SIZE) = *:8 Mem; goto [target]; }\n@endif\n\n# Initially disallowed in 64bit mode, but later reintroduced\n:LAHF is vexMode=0 & byte=0x9f { AH=(SF<<7)|(ZF<<6)|(AF<<4)|(PF<<2)|2|CF; }\n\n:LAR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x2; rm16 & Reg16 ... { Reg16 = rm16 & 0xff00; ZF=1; }\n:LAR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x2; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32 & 0xffff00; build check_Reg32_dest; ZF=1; }\n@ifdef IA64\n:LAR Reg64,rm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x2; rm32 & Reg64 ... { Reg64 = zext( rm32 & 0xffff00 ); ZF=1; }\n@endif\n\n:LDMXCSR m32\t\tis vexMode=0 & byte=0xf; byte=0xae; ( mod != 0b11 & reg_opcode=2 ) ... & m32 { MXCSR = m32; }\n\n# 16 & 32-bit only\n:LDS Reg16,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xC5; Mem & Reg16 ... { tmp:4 = *Mem; DS = tmp(2); Reg16 = tmp(0); }\n:LDS Reg32,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xC5 & bit64=0; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; DS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; }\n\n:LSS Reg16,Mem is vexMode=0 & opsize=0 & byte=0x0F; byte=0xB2; Mem & Reg16 ... { tmp:4 = *Mem; SS = tmp(2); Reg16 = tmp(0); }\n:LSS Reg32,Mem is vexMode=0 & opsize=1 & byte=0x0F; byte=0xB2; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; SS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; }\n@ifdef IA64\n:LSS Reg64,Mem is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xB2; Mem & Reg64 ... { tmp:10 = *Mem; SS = tmp(8); Reg64 = tmp(0); }\n@endif\n\n# 16 & 32-bit only\n:LES Reg16,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xC4; Mem & Reg16 ... { tmp:4 = *Mem; ES = tmp(2); Reg16 = tmp(0); }\n:LES Reg32,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xC4 & bit64=0; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; ES = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; }\n\n:LFS Reg16,Mem is vexMode=0 & opsize=0 & byte=0x0F; byte=0xB4; Mem & Reg16 ... { tmp:4 = *Mem; FS = tmp(2); Reg16 = tmp(0); }\n:LFS Reg32,Mem is vexMode=0 & opsize=1 & byte=0x0F; byte=0xB4; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; FS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; }\n@ifdef IA64\n:LFS Reg64,Mem is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xB4; Mem & Reg64 ... { tmp:10 = *Mem; FS = tmp(8); Reg64 = tmp(0); }\n@endif\n:LGS Reg16,Mem is vexMode=0 & opsize=0 & byte=0x0F; byte=0xB5; Mem & Reg16 ... { tmp:4 = *Mem; GS = tmp(2); Reg16 = tmp(0); }\n:LGS Reg32,Mem is vexMode=0 & opsize=1 & byte=0x0F; byte=0xB5; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; GS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; }\n@ifdef IA64\n:LGS Reg64,Mem is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xB5; Mem & Reg64 ... { tmp:10 = *Mem; GS = tmp(8); Reg64 = tmp(0); }\n@endif\n\n#in 64-bit mode address size of 16 is not encodable\n:LEA Reg16,addr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & addrsize=0 & byte=0x8D; addr16 & Reg16 ... { Reg16 = addr16; }\n:LEA Reg32,addr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & addrsize=0 & byte=0x8D; addr16 & Reg32 ... { Reg32 = zext(addr16); }\n\n:LEA Reg16,addr32 is vexMode=0 & opsize=0 & addrsize=1 & byte=0x8D; addr32 & Reg16 ... { Reg16 = addr32(0); }\n:LEA Reg32,addr32 is vexMode=0 & opsize=1 & addrsize=1 & byte=0x8D; addr32 & Reg32 ... & check_Reg32_dest ... {\n Reg32 = addr32;\n\tbuild check_Reg32_dest;\n}\n\n@ifdef IA64\n:LEA Reg16,addr64 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & addrsize=2 & byte=0x8D; addr64 & Reg16 ... { Reg16 = addr64(0); }\n:LEA Reg32,addr64 is $(LONGMODE_ON) & vexMode=0 & opsize=1 & addrsize=2 & byte=0x8D; addr64 & Reg32 ... & check_Reg32_dest ... { \n Reg32 = addr64(0);\n build check_Reg32_dest;\n}\n:LEA Reg64,addr32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & addrsize=1 & byte=0x8D; addr32 & Reg64 ... { Reg64 = zext(addr32); }\n:LEA Reg64,addr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & addrsize=2 & byte=0x8D; addr64 & Reg64 ... { Reg64 = addr64; }\n@endif\n\n:LEAVE is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xc9 { SP = BP; pop22(BP); }\n:LEAVE is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xc9 { ESP = EBP; pop24(EBP); }\n:LEAVE is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc9 { ESP = EBP; pop44(EBP); }\n:LEAVE is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc9 { ESP = EBP; pop42(BP); }\n@ifdef IA64\n:LEAVE is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xc9 { RSP = RBP; pop82(BP); }\n:LEAVE is $(LONGMODE_ON) & vexMode=0 & byte=0xc9 { RSP = RBP; pop88(RBP); }\n@endif\n\ndefine pcodeop GlobalDescriptorTableRegister;\n:LGDT m16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=2 ) ... & m16\n{\n\tGlobalDescriptorTableRegister(m16);\n}\n\n:LGDT m32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=2 ) ... & m32\n{\n\tGlobalDescriptorTableRegister(m32);\n}\n@ifdef IA64\n:LGDT m64 is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=2 ) ... & m64\n{\n\tGlobalDescriptorTableRegister(m64);\n}\n@endif\n\ndefine pcodeop InterruptDescriptorTableRegister;\n:LIDT m16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=3 ) ... & m16\n{\n\tInterruptDescriptorTableRegister(m16);\n}\n\n:LIDT m32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=3 ) ... & m32\n{\n\tInterruptDescriptorTableRegister(m32);\n}\n@ifdef IA64\n:LIDT m64 is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=3 ) ... & m64\n{\n\tInterruptDescriptorTableRegister(m64);\n}\n@endif\n\ndefine pcodeop LocalDescriptorTableRegister;\n:LLDT rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=2 ...\n{\n\tLocalDescriptorTableRegister(rm16);\n}\n\n@ifdef IA64\n:LMSW rm16 is vexMode=0 & byte=0xf; byte=0x01; rm16 & reg_opcode=6 ...\n{\n CR0 = (CR0 & 0xFFFFFFFFFFFFFFF0) | zext(rm16 & 0x000F);\n}\n@else\n:LMSW rm16 is vexMode=0 & byte=0xf; byte=0x01; rm16 & reg_opcode=6 ...\n{\n CR0 = (CR0 & 0xFFFFFFF0) | zext(rm16 & 0x000F);\n}\n@endif\n\n:LODSB^rep^reptail dseSI1 is vexMode=0 & rep & reptail & byte=0xAC & dseSI1 { build rep; build dseSI1; AL=dseSI1; build reptail; }\n:LODSW^rep^reptail dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xAD & dseSI2 { build rep; build dseSI2; AX=dseSI2; build reptail; }\n:LODSD^rep^reptail dseSI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xAD & dseSI4 { build rep; build dseSI4; EAX=dseSI4; build reptail; }\n@ifdef IA64\n:LODSQ^rep^reptail dseSI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xAD & dseSI8 { build rep; build dseSI8; RAX=dseSI8; build reptail; }\n@endif\n\n:LOOP rel8 is vexMode=0 & addrsize=0 & byte=0xE2; rel8 { CX = CX -1; if (CX!=0) goto rel8; }\n:LOOP rel8 is vexMode=0 & addrsize=1 & byte=0xE2; rel8 { ECX = ECX -1; if (ECX!=0) goto rel8; }\n@ifdef IA64\n:LOOP rel8 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xE2; rel8 { RCX = RCX -1; if (RCX!=0) goto rel8; }\n@endif\n\n:LOOPZ rel8 is vexMode=0 & addrsize=0 & byte=0xE1; rel8 { CX = CX -1; if (CX!=0 && ZF!=0) goto rel8; }\n:LOOPZ rel8 is vexMode=0 & addrsize=1 & byte=0xE1; rel8 { ECX = ECX -1; if (ECX!=0 && ZF!=0) goto rel8; }\n@ifdef IA64\n:LOOPZ rel8 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xE1; rel8 { RCX = RCX -1; if (RCX!=0 && ZF!=0) goto rel8; }\n@endif\n\n:LOOPNZ rel8 is vexMode=0 & addrsize=0 & byte=0xE0; rel8 { CX = CX -1; if (CX!=0 && ZF==0) goto rel8; }\n:LOOPNZ rel8 is vexMode=0 & addrsize=1 & byte=0xE0; rel8 { ECX = ECX -1; if (ECX!=0 && ZF==0) goto rel8; }\n@ifdef IA64\n:LOOPNZ rel8 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xE0; rel8 { RCX = RCX -1; if (RCX!=0 && ZF==0) goto rel8; }\n@endif\n\ndefine pcodeop SegmentLimit;\n:LSL Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x3; rm16 & Reg16 ...\n{\n tmp:3 = SegmentLimit(rm16);\n Reg16 = tmp:2;\n ZF = tmp[16,1];\n}\n\n:LSL Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x3; rm32 & Reg32 ...\n{\n tmp:3 = SegmentLimit(rm32);\n Reg32 = zext(tmp:2);\n ZF = tmp[16,1];\n}\n\n@ifdef IA64\n:LSL Reg64,rm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x3; rm32 & Reg64 ...\n{\n tmp:3 = SegmentLimit(rm32);\n Reg64 = zext(tmp:2);\n ZF = tmp[16,1];\n}\n@endif\n\ndefine pcodeop TaskRegister;\n:LTR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=3 ... { TaskRegister(rm16); }\n\n:MOV Rmr8,Reg8 is vexMode=0 & byte=0x88; mod=3 & Rmr8 & Reg8 { Rmr8=Reg8; }\n\n:MOV^xrelease m8,Reg8 is vexMode=0 & xrelease & byte=0x88; m8 & Reg8 ... \n{ \n build xrelease;\n build m8;\n m8=Reg8;\n }\n\n:MOV Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x89; mod=3 & Rmr16 & Reg16 { Rmr16=Reg16; }\n\n:MOV^xrelease m16,Reg16 is vexMode=0 & xrelease & opsize=0 & byte=0x89; m16 & Reg16 ... \n{ \n build xrelease;\n build m16; \n m16=Reg16;\n }\n\n:MOV Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x89; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { Rmr32=Reg32; build check_Rmr32_dest; }\n\n:MOV^xrelease m32,Reg32 is vexMode=0 & xrelease & opsize=1 & byte=0x89; m32 & Reg32 ... \n{ \n build xrelease; \n build m32; \n m32=Reg32;\n}\n\n@ifdef IA64\n:MOV Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x89; mod=3 & Rmr64 & Reg64 { Rmr64=Reg64; }\n\n:MOV^xrelease m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & xrelease & opsize=2 & byte=0x89; m64 & Reg64 ... \n{ \n build xrelease;\n build m64; \n m64=Reg64;\n }\n\n@endif\n:MOV Reg8,rm8 is vexMode=0 & byte=0x8a; rm8 & Reg8 ... { Reg8 = rm8; }\n:MOV Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x8b; rm16 & Reg16 ... { Reg16 = rm16; }\n:MOV Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x8b; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32; build check_Reg32_dest; }\n@ifdef IA64\n:MOV Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8b; rm64 & Reg64 ... { Reg64 = rm64; }\n@endif\n:MOV rm16,Sreg is vexMode=0 & byte=0x8c; rm16 & Sreg ... { rm16 = Sreg; }\n:MOV Sreg,rm16 is vexMode=0 & byte=0x8e; rm16 & Sreg ... { Sreg=rm16; }\n:MOV AL,moffs8 is vexMode=0 & byte=0xa0; AL & moffs8 { AL=moffs8; }\n:MOV AX,moffs16 is vexMode=0 & opsize=0 & byte=0xa1; AX & moffs16 { AX=moffs16; }\n:MOV EAX,moffs32 is vexMode=0 & opsize=1 & byte=0xa1; EAX & check_EAX_dest & moffs32 { EAX=moffs32; build check_EAX_dest; }\n@ifdef IA64\n:MOV RAX,moffs64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xa1; RAX & moffs64 { RAX=moffs64; }\n@endif\n:MOV moffs8,AL is vexMode=0 & byte=0xa2; AL & moffs8 { moffs8=AL; }\n:MOV moffs16,AX is vexMode=0 & opsize=0 & byte=0xa3; AX & moffs16 { moffs16=AX; }\n:MOV moffs32,EAX is vexMode=0 & opsize=1 & byte=0xa3; EAX & moffs32 { moffs32=EAX; }\n@ifdef IA64\n:MOV moffs64,RAX is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xa3; RAX & moffs64 { moffs64=RAX; }\n@endif\n:MOV CRmr8,imm8 is vexMode=0 & row=11 & page=0 & CRmr8; imm8 { CRmr8 = imm8; }\n:MOV CRmr16,imm16 is vexMode=0 & opsize=0 & row=11 & page=1 & CRmr16; imm16 { CRmr16 = imm16; }\n:MOV CRmr32,imm32 is vexMode=0 & opsize=1 & row=11 & page=1 & CRmr32; imm32 { CRmr32 = imm32; }\n@ifdef IA64\n:MOV Rmr64,imm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & row=11 & page=1 & Rmr64; imm64 { Rmr64 = imm64; }\n@endif\n:MOV Rmr8,imm8 is vexMode=0 & byte=0xc6; (mod=3 & Rmr8 & reg_opcode=0); imm8 { Rmr8 = imm8; }\n\n:MOV^xrelease m8,imm8 is vexMode=0 & xrelease & byte=0xc6; m8 & reg_opcode=0 ...; imm8 \n{ \n build xrelease; \n build m8; \n m8 = imm8;\n}\n:MOV Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0xc7; (mod=3 & Rmr16 & reg_opcode=0); imm16 { Rmr16 = imm16; }\n\n:MOV^xrelease m16,imm16 is vexMode=0 & xrelease & opsize=0 & byte=0xc7; m16 & reg_opcode=0 ...; imm16 \n{ \n build xrelease; \n build m16; \n m16 = imm16;\n}\n\n:MOV Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0xc7; (mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0); imm32 { Rmr32 = imm32; build check_Rmr32_dest; }\n\n:MOV^xrelease m32,imm32 is vexMode=0 & xrelease & opsize=1 & byte=0xc7; (m32 & reg_opcode=0 ...); imm32 \n{ \n build xrelease; \n build m32;\n m32 = imm32;\n}\n@ifdef IA64\n:MOV Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xc7; (mod=3 & Rmr64 & reg_opcode=0); simm32 { Rmr64 = simm32; }\n\n:MOV^xrelease m64,simm32 is $(LONGMODE_ON) & vexMode=0 & xrelease & opsize=2 & byte=0xc7; (m64 & reg_opcode=0 ...); simm32 \n{ \n build xrelease; \n build m64;\n m64 = simm32; \n}\n@endif\n\n:MOV creg, Rmr32 is vexMode=0 & byte=0xf; byte=0x22; Rmr32 & creg {\n@ifdef IA64\n creg=zext(Rmr32);\n@else\n creg=Rmr32;\n@endif\n}\n@ifdef IA64\n:MOV creg, Rmr64 is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0x22; Rmr64 & creg { creg=Rmr64; }\n:MOV creg_x, Rmr64 is $(LONGMODE_ON) & vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x22; Rmr64 & creg_x { creg_x=Rmr64; }\n@endif\n\n:MOV Rmr32, creg is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x20; Rmr32 & creg {\n@ifdef IA64\n Rmr32 = creg:4;\n@else\n Rmr32 = creg;\n@endif\n}\n@ifdef IA64\n:MOV Rmr64, creg is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0x20; Rmr64 & creg { Rmr64 = creg; }\n:MOV Rmr64, creg_x is $(LONGMODE_ON) & vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x20; Rmr64 & creg_x { Rmr64 = creg_x; }\n@endif\n\n:MOV Rmr32, debugreg is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x21; Rmr32 & debugreg {\n@ifdef IA64\n Rmr32 = debugreg:4;\n@else\n Rmr32 = debugreg;\n@endif\n}\n@ifdef IA64\n:MOV Rmr64, debugreg is $(LONGMODE_ON) & vexMode=0 & bit64=1 & byte=0xf; byte=0x21; Rmr64 & debugreg { Rmr64 = debugreg; }\n:MOV Rmr64, debugreg_x is $(LONGMODE_ON) & vexMode=0 & bit64=1 & rexRprefix=1 & byte=0xf; byte=0x21; Rmr64 & debugreg_x { Rmr64 = debugreg_x; }\n@endif\n\n:MOV debugreg, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x23; Rmr32 & debugreg {\n@ifdef IA64\n debugreg = zext(Rmr32);\n@else\n debugreg = Rmr32;\n@endif\n}\n@ifdef IA64\n:MOV debugreg, Rmr64 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & byte=0xf; byte=0x23; Rmr64 & debugreg & mod=3 { debugreg = Rmr64; }\n:MOV debugreg_x, Rmr64 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & rexRprefix=1 & byte=0xf; byte=0x23; Rmr64 & debugreg_x & mod=3 { debugreg_x = Rmr64; }\n@endif\n\n@ifndef IA64\n# These are obsolete instructions after the 486 generation.\n:MOV r32, testreg\tis vexMode=0 & byte=0xf; byte=0x24; r32 & testreg & mod=3 { r32 = testreg; }\n:MOV testreg, r32\tis vexMode=0 & byte=0xf; byte=0x26; r32 & testreg & mod=3 { testreg = r32; }\n@endif\n\ndefine pcodeop swap_bytes;\n:MOVBE Reg16, m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf0; Reg16 ... & m16 { Reg16 = swap_bytes( m16 ); }\n:MOVBE Reg32, m32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg32 ... & m32 { Reg32 = swap_bytes( m32 ); }\n:MOVBE m16, Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf1; Reg16 ... & m16 { m16 = swap_bytes( Reg16 ); }\n:MOVBE m32, Reg32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg32 ... & m32 { m32 = swap_bytes( Reg32 ); }\n@ifdef IA64\n:MOVBE Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg64 ... & m64 { Reg64 = swap_bytes( m64 ); }\n:MOVBE m64, Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg64 ... & m64 { m64 = swap_bytes( Reg64 ); }\n@endif\n\n\n:MOVNTI Mem,Reg32 is vexMode=0 & opsize = 1; byte=0xf; byte=0xc3; Mem & Reg32 ... { *Mem = Reg32; }\n@ifdef IA64\n:MOVNTI Mem,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize = 2; byte=0xf; byte=0xc3; Mem & Reg64 ... { *Mem = Reg64; }\n@endif\n\n:MOVSB^rep^reptail eseDI1,dseSI1 is vexMode=0 & rep & reptail & byte=0xa4 & eseDI1 & dseSI1 { build rep; build eseDI1; build dseSI1; eseDI1 = dseSI1; build reptail; }\n:MOVSW^rep^reptail eseDI2,dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xa5 & eseDI2 & dseSI2 { build rep; build eseDI2; build dseSI2; eseDI2 = dseSI2; build reptail; }\n:MOVSD^rep^reptail eseDI4,dseSI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xa5 & eseDI4 & dseSI4 { build rep; build eseDI4; build dseSI4; eseDI4 = dseSI4; build reptail; }\n@ifdef IA64\n:MOVSQ^rep^reptail eseDI8,dseSI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xa5 & eseDI8 & dseSI8 { build rep; build eseDI8; build dseSI8; eseDI8 = dseSI8; build reptail; }\n@endif\n\n:MOVSX Reg16,rm8 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbe; rm8 & Reg16 ... { Reg16 = sext(rm8); }\n:MOVSX Reg32,rm8 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbe; rm8 & Reg32 ... & check_Reg32_dest ... { Reg32 = sext(rm8); build check_Reg32_dest; }\n@ifdef IA64\n:MOVSX Reg64,rm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbe; rm8 & Reg64 ... { Reg64 = sext(rm8); }\n@endif\n:MOVSX Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbf; rm16 & Reg16 ... { Reg16 = rm16; }\n:MOVSX Reg32,rm16 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbf; rm16 & Reg32 ... & check_Reg32_dest ... { Reg32 = sext(rm16); build check_Reg32_dest; }\n@ifdef IA64\n:MOVSX Reg64,rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbf; rm16 & Reg64 ... { Reg64 = sext(rm16); }\n@endif\n\n:MOVSXD Reg32,rm32 is vexMode=0 & bit64=1 & opsize=1 & byte=0x63; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32; build check_Reg32_dest; }\n@ifdef IA64\n:MOVSXD Reg64,rm32 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & opsize=2 & byte=0x63; rm32 & Reg64 ... { Reg64 = sext(rm32); }\n@endif\n\n:MOVZX Reg16,rm8 is vexMode=0 & opsize=0 & byte=0xf; byte=0xb6; rm8 & Reg16 ... { Reg16 = zext(rm8); }\n:MOVZX Reg32,rm8 is vexMode=0 & opsize=1 & byte=0xf; byte=0xb6; rm8 & Reg32 ... & check_Reg32_dest ... { Reg32 = zext(rm8); build check_Reg32_dest; }\n@ifdef IA64\n:MOVZX Reg64,rm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xb6; rm8 & Reg64 ... { Reg64 = zext(rm8); }\n@endif\n:MOVZX Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xb7; rm16 & Reg16 ... { Reg16 = rm16; }\n:MOVZX Reg32,rm16 is vexMode=0 & opsize=1 & byte=0xf; byte=0xb7; rm16 & Reg32 ... & check_Reg32_dest ... { Reg32 = zext(rm16); build check_Reg32_dest; }\n@ifdef IA64\n:MOVZX Reg64,rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xb7; rm16 & Reg64 ... { Reg64 = zext(rm16); }\n@endif\n\n:MUL rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=4 ... { AX=zext(AL)*zext(rm8); multflags(AH); }\n:MUL rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=4 ... { tmp:4=zext(AX)*zext(rm16); DX=tmp(2); AX=tmp(0); multflags(DX); }\n:MUL rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EAX_dest ... & check_EDX_dest ... & reg_opcode=4 ... { tmp:8=zext(EAX)*zext(rm32); EDX=tmp(4); build check_EDX_dest; multflags(EDX); EAX=tmp(0); build check_EAX_dest; }\n@ifdef IA64\n:MUL rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=4 ... { tmp:16=zext(RAX)*zext(rm64); RDX=tmp(8); RAX=tmp(0); multflags(RDX); }\n@endif\n\n:MWAIT is vexMode=0 & byte=0x0f; byte=0x01; byte=0xC9 { mwait(); }\n:MWAITX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xFB { mwaitx(); }\n:MONITOR is vexMode=0 & byte=0x0f; byte=0x01; byte=0xC8 { monitor(); }\n:MONITORX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xFA { monitorx(); }\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:NEG Rmr8 is vexMode=0 & byte=0xf6; mod=3 & Rmr8 & reg_opcode=3 { negflags(Rmr8); Rmr8 = -Rmr8; resultflags(Rmr8 ); }\n:NEG Rmr16 is vexMode=0 & opsize=0 & byte=0xf7; mod=3 & Rmr16 & reg_opcode=3 { negflags(Rmr16); Rmr16 = -Rmr16; resultflags(Rmr16); }\n:NEG Rmr32 is vexMode=0 & opsize=1 & byte=0xf7; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=3 { negflags(Rmr32); Rmr32 = -Rmr32; resultflags(Rmr32); build check_Rmr32_dest;}\n@ifdef IA64\n:NEG Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=3 { negflags(Rmr64); Rmr64 = -Rmr64; resultflags(Rmr64); }\n@endif\n\n:NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8) { }\n:NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16 ... { }\n:NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32 ... { }\n:NOP^\"/reserved\" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ... { }\n:NOP^\"/reserved\" rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; byte=0x18; rm32 & reg_opcode_hb=1 ... { }\n:NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x1f; rm16 & reg_opcode=0 ... { }\n:NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; byte=0x1f; rm32 & reg_opcode=0 ... { }\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:NOT Rmr8 is vexMode=0 & byte=0xf6; mod=3 & Rmr8 & reg_opcode=2 { Rmr8 = ~Rmr8; }\n:NOT Rmr16 is vexMode=0 & opsize=0 & byte=0xf7; mod=3 & Rmr16 & reg_opcode=2 { Rmr16 = ~Rmr16; }\n:NOT Rmr32 is vexMode=0 & opsize=1 & byte=0xf7; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=2 { Rmr32 = ~Rmr32; build check_Rmr32_dest;}\n@ifdef IA64\n:NOT Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=2 { Rmr64 = ~Rmr64; }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:OR AL,imm8 is vexMode=0 & byte=0x0c; AL & imm8 { logicalflags(); AL = AL | imm8; resultflags( AL); }\n:OR AX,imm16 is vexMode=0 & opsize=0 & byte=0xd; AX & imm16 { logicalflags(); AX = AX | imm16; resultflags( AX); }\n:OR EAX,imm32 is vexMode=0 & opsize=1 & byte=0xd; EAX & check_EAX_dest & imm32 { logicalflags(); EAX = EAX | imm32; build check_EAX_dest; resultflags( EAX); }\n@ifdef IA64\n:OR RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xd; RAX & simm32 { logicalflags(); RAX = RAX | simm32; resultflags( RAX); }\n@endif\n:OR Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=1; imm8 { logicalflags(); Rmr8 = Rmr8 | imm8; resultflags( Rmr8); }\n:OR Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=1; imm16 { logicalflags(); Rmr16 = Rmr16 | imm16; resultflags( Rmr16); }\n:OR Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=1; imm32 { logicalflags(); Rmr32 = Rmr32 | imm32; build check_rm32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:OR Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=1; simm32 { logicalflags(); tmp:8 = Rmr64; Rmr64 = tmp | simm32; resultflags( Rmr64); }\n@endif\n:OR Rmr16,usimm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=1; usimm8_16 { logicalflags(); Rmr16 = Rmr16 | usimm8_16; resultflags( Rmr16); }\n:OR Rmr32,usimm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=1; usimm8_32 { logicalflags(); Rmr32 = Rmr32 | usimm8_32; build check_rm32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:OR Rmr64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=1; usimm8_64 { logicalflags(); Rmr64 = Rmr64 | usimm8_64; resultflags( Rmr64); }\n@endif\n:OR Rmr8,Reg8 is vexMode=0 & byte=0x8; mod=3 & Rmr8 & Reg8 { logicalflags(); Rmr8 = Rmr8 | Reg8; resultflags( Rmr8); }\n:OR Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x9; mod=3 & Rmr16 & Reg16 { logicalflags(); Rmr16 = Rmr16 | Reg16; resultflags( Rmr16); }\n:OR Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x9; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { logicalflags(); Rmr32 = Rmr32 | Reg32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:OR Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x9; mod=3 & Rmr64 & Reg64 { logicalflags(); Rmr64 = Rmr64 | Reg64; resultflags( Rmr64); }\n@endif\n:OR Reg8,rm8 is vexMode=0 & byte=0xa; rm8 & Reg8 ... { logicalflags(); Reg8 = Reg8 | rm8; resultflags( Reg8); }\n:OR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xb; rm16 & Reg16 ... { logicalflags(); Reg16 = Reg16 | rm16; resultflags(Reg16); }\n:OR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xb; rm32 & Reg32 ... & check_Reg32_dest ... { logicalflags(); Reg32 = Reg32 | rm32; build check_Reg32_dest; resultflags(Reg32); }\n@ifdef IA64\n:OR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xb; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 | rm64; resultflags(Reg64); }\n@endif\n\n:OUT imm8,AL is vexMode=0 & byte=0xe6; imm8 & AL { tmp:1 = imm8; out(tmp,AL); }\n:OUT imm8,AX is vexMode=0 & opsize=0 & byte=0xe7; imm8 & AX { tmp:1 = imm8; out(tmp,AX); }\n:OUT imm8,EAX is vexMode=0 & byte=0xe7; imm8 & EAX { tmp:1 = imm8; out(tmp,EAX); }\n:OUT DX,AL is vexMode=0 & byte=0xee & DX & AL { out(DX,AL); }\n:OUT DX,AX is vexMode=0 & opsize=0 & byte=0xef & DX & AX { out(DX,AX); }\n:OUT DX,EAX is vexMode=0 & byte=0xef & DX & EAX { out(DX,EAX); }\n\n:OUTSB^rep^reptail DX,dseSI1 is vexMode=0 & rep & reptail & byte=0x6e & DX & dseSI1 { build rep; build dseSI1; out(dseSI1,DX); build reptail;}\n:OUTSW^rep^reptail DX,dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0x6f & DX & dseSI2 { build rep; build dseSI2; out(dseSI2,DX); build reptail;}\n:OUTSD^rep^reptail DX,dseSI4 is vexMode=0 & rep & reptail & byte=0x6f & DX & dseSI4 { build rep; build dseSI4; out(dseSI4,DX); build reptail;}\n\n:PAUSE is vexMode=0 & opsize=0 & $(PRE_F3) & byte=0x90 { }\n:PAUSE is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x90 { }\n\n:POP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { local val:2 = 0; pop22(val); build rm16; rm16 = val; }\n:POP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { local val:2 = 0; pop42(val); build rm16; rm16 = val; }\n:POP rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x8f; rm32 & reg_opcode=0 ... { local val:4 = 0; pop24(val); build rm32; rm32 = val; }\n:POP rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x8f; rm32 & reg_opcode=0 ... { local val:4 = 0; pop44(val); build rm32; rm32 = val; }\n@ifdef IA64\n:POP rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { local val:2 = 0; pop82(val); build rm16; rm16 = val; }\n:POP rm64 is $(LONGMODE_ON) & vexMode=0 & byte=0x8f; rm64 & reg_opcode=0 ... { local val:8 = 0; pop88(val); build rm64; rm64 = val; }\n@endif\n\n:POP Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & row=5 & page=1 & Rmr16 { local val:2 = 0; pop22(val); Rmr16 = val; }\n:POP Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & row=5 & page=1 & Rmr16 { local val:2 = 0; pop42(val); Rmr16 = val; }\n:POP Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & row=5 & page=1 & Rmr32 { local val:4 = 0; pop24(val); Rmr32 = val; }\n:POP Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & row=5 & page=1 & Rmr32 { local val:4 = 0; pop44(val); Rmr32 = val; }\n@ifdef IA64\n:POP Rmr16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & row=5 & page=1 & Rmr16 { local val:2 = 0; pop82(val); Rmr16 = val; }\n:POP Rmr64 is $(LONGMODE_ON) & vexMode=0 & row=5 & page=1 & Rmr64 { local val:8 = 0; pop88(val); Rmr64 = val; }\n@endif\n\n:POP DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x1f & DS { pop22(DS); }\n:POP DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x1f & DS { popseg44(DS); }\n:POP ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x7 & ES { pop22(ES); }\n:POP ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x7 & ES { popseg44(ES); }\n:POP SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x17 & SS { pop22(SS); }\n:POP SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x17 & SS { popseg44(SS); }\n:POP FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xf; byte=0xa1 & FS { pop22(FS); }\n:POP FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xf; byte=0xa1 & FS { popseg44(FS); }\n@ifdef IA64\n:POP FS is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; byte=0xa1 & FS { popseg88(FS); }\n@endif\n:POP GS is vexMode=0 & addrsize=0 & byte=0xf; byte=0xa9 & GS { pop22(GS); }\n:POP GS is vexMode=0 & addrsize=1 & byte=0xf; byte=0xa9 & GS { popseg44(GS); }\n@ifdef IA64\n:POP GS is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; byte=0xa9 & GS { popseg88(GS); }\n@endif\n\n:POPA is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x61 { pop22(DI); pop22(SI); pop22(BP); tmp:2=0; pop22(tmp); pop22(BX); pop22(DX); pop22(CX); pop22(AX); }\n:POPA is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x61 { pop42(DI); pop42(SI); pop42(BP); tmp:2=0; pop42(tmp); pop42(BX); pop42(DX); pop42(CX); pop42(AX); }\n:POPAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x61 { pop24(EDI); pop24(ESI); pop24(EBP); tmp:4=0; pop24(tmp); pop24(EBX); pop24(EDX); pop24(ECX); pop24(EAX); }\n:POPAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x61 { pop44(EDI); pop44(ESI); pop44(EBP); tmp:4=0; pop44(tmp); pop44(EBX); pop44(EDX); pop44(ECX); pop44(EAX); }\n:POPF is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x9d { pop22(flags); unpackflags(flags); }\n:POPF is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x9d { pop42(flags); unpackflags(flags); }\n:POPFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x9d { pop24(eflags); unpackflags(eflags); unpackeflags(eflags); }\n:POPFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x9d { pop44(eflags); unpackflags(eflags); unpackeflags(eflags); }\n@ifdef IA64\n:POPF is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0x9d { pop82(flags); unpackflags(flags); }\n:POPFQ is $(LONGMODE_ON) & vexMode=0 & byte=0x9d { pop88(rflags); unpackflags(rflags); unpackeflags(rflags); }\n@endif\n\n:PREFETCH m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode=0 ... { }\n:PREFETCH m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode ... { } # rest aliased to /0\n:PREFETCHW m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode=1 ... { }\n:PREFETCHWT1 m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode=2 ... { }\n\n:PREFETCHT0 m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=1 ) ... & m8 { }\n:PREFETCHT1 m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=2 ) ... & m8 { }\n:PREFETCHT2 m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=3 ) ... & m8 { }\n:PREFETCHNTA m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=0 ) ... & m8 { }\n\ndefine pcodeop ptwrite;\n\n:PTWRITE rm32 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xae; rm32 & reg_opcode=4 ... { ptwrite(rm32); }\n@ifdef IA64\n:PTWRITE rm64 is vexMode=0 & $(PRE_F3) & opsize=2 & byte=0x0f; byte=0xae; rm64 & reg_opcode=4 ... { ptwrite(rm64); }\n@endif\n\n:PUSH rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xff; rm16 & reg_opcode=6 ... { push22(rm16); }\n:PUSH rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xff; rm16 & reg_opcode=6 ... { push42(rm16); }\n\n:PUSH rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xff; rm32 & reg_opcode=6 ... { push24(rm32); }\n:PUSH rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xff; rm32 & reg_opcode=6 ... { push44(rm32); }\n@ifdef IA64\n:PUSH rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xff; rm16 & reg_opcode=6 ... { push82(rm16); }\n:PUSH rm64 is $(LONGMODE_ON) & vexMode=0 & byte=0xff; rm64 & reg_opcode=6 ... { push88(rm64); }\n@endif\n\n:PUSH Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & row=5 & page=0 & Rmr16 { push22(Rmr16); }\n:PUSH Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & row=5 & page=0 & Rmr16 { push42(Rmr16); }\n:PUSH Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & row=5 & page=0 & Rmr32 { push24(Rmr32); }\n:PUSH Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & row=5 & page=0 & Rmr32 { push44(Rmr32); }\n@ifdef IA64\n:PUSH Rmr16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & row=5 & page=0 & Rmr16 { push82(Rmr16); }\n:PUSH Rmr64 is $(LONGMODE_ON) & vexMode=0 & row=5 & page=0 & Rmr64 { push88(Rmr64); }\n@endif\n\n:PUSH simm8_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x6a; simm8_16 { tmp:2=simm8_16; push22(tmp); }\n:PUSH simm8_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x6a; simm8_16 { tmp:2=simm8_16; push42(tmp); }\n:PUSH simm8_32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x6a; simm8_32 { tmp:4=simm8_32; push24(tmp); }\n:PUSH simm8_32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x6a; simm8_32 { tmp:4=simm8_32; push44(tmp); }\n@ifdef IA64\n:PUSH simm8_16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0x6a; simm8_16 { tmp:2=simm8_16; push82(tmp); }\n:PUSH simm8_64 is $(LONGMODE_ON) & vexMode=0 & byte=0x6a; simm8_64 { tmp:8=simm8_64; push88(tmp); }\n@endif\n\n:PUSH simm16_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x68; simm16_16 { tmp:2=simm16_16; push22(tmp); }\n:PUSH simm16_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x68; simm16_16 { tmp:2=simm16_16; push42(tmp); }\n:PUSH imm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x68; imm32 { tmp:4=imm32; push24(tmp); }\n:PUSH imm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x68; imm32 { tmp:4=imm32; push44(tmp); }\n@ifdef IA64\n:PUSH simm16_16 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0x68; simm16_16 { tmp:2=simm16_16; push82(tmp); }\n:PUSH simm32_64 is $(LONGMODE_ON) & vexMode=0 & byte=0x68; simm32_64 { tmp:8=simm32_64; push88(tmp); }\n@endif\n\n:PUSH CS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xe & CS { push22(CS); }\n:PUSH CS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xe & CS { pushseg44(CS); }\n:PUSH SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x16 & SS { push22(SS); }\n:PUSH SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x16 & SS { pushseg44(SS); }\n:PUSH DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x1e & DS { push22(DS); }\n:PUSH DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x1e & DS { pushseg44(DS); }\n:PUSH ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x6 & ES { push22(ES); }\n:PUSH ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x6 & ES { pushseg44(ES); }\n:PUSH FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xf; byte=0xa0 & FS { push22(FS); }\n:PUSH FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xf; byte=0xa0 & FS { pushseg44(FS); }\n@ifdef IA64\n:PUSH FS is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa0 & FS { push82(FS); }\n:PUSH FS is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0xa0 & FS { pushseg88(FS); }\n@endif\n:PUSH GS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xf; byte=0xa8 & GS { push22(GS); }\n:PUSH GS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xf; byte=0xa8 & GS { pushseg44(GS); }\n@ifdef IA64\n:PUSH GS is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa8 & GS { push82(GS); }\n:PUSH GS is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0xa8 & GS { pushseg88(GS); }\n@endif\n\n:PUSHA is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x60 { local tmp=SP; push22(AX); push22(CX); push22(DX); push22(BX); push22(tmp); push22(BP); push22(SI); push22(DI); }\n:PUSHA is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x60 { local tmp=SP; push42(AX); push42(CX); push42(DX); push42(BX); push42(tmp); push42(BP); push42(SI); push42(DI); }\n:PUSHAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x60 { local tmp=ESP; push24(EAX); push24(ECX); push24(EDX); push24(EBX); push24(tmp); push24(EBP); push24(ESI); push24(EDI); }\n:PUSHAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x60 { local tmp=ESP; push44(EAX); push44(ECX); push44(EDX); push44(EBX); push44(tmp); push44(EBP); push44(ESI); push44(EDI); }\n\n:PUSHF is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x9c { packflags(flags); push22(flags); }\n:PUSHF is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x9c { packflags(flags); push42(flags); }\n:PUSHFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x9c { packflags(eflags); packeflags(eflags); push24(eflags); }\n:PUSHFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x9c { packflags(eflags); packeflags(eflags); push44(eflags); }\n@ifdef IA64\n:PUSHF is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0x9c { packflags(flags); push82(flags); }\n:PUSHFQ is $(LONGMODE_ON) & vexMode=0 & byte=0x9c { packflags(rflags); packeflags(rflags); push88(rflags); }\n@endif\n\n:RCL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm8 s< 0; rm8 = (rm8 << 1) | tmpCF; OF = CF ^ (rm8 s< 0); }\n:RCL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=2 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt));rm8=tmp(0); CF=(tmp&0x100)!=0; }\n:RCL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; }\n:RCL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm16 s< 0; rm16 = (rm16 << 1) | zext(tmpCF); OF = CF ^ (rm16 s< 0);}\n:RCL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=2 ... {local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; }\n:RCL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; }\n:RCL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=2 ... { local tmpCF=CF; CF=rm32 s< 0; rm32=(rm32<<1)|zext(tmpCF); OF=CF^(rm32 s< 0); build check_rm32_dest; }\n:RCL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=2 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; }\n:RCL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=2 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; }\n@ifdef IA64\n:RCL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=2 ... { local tmpCF=CF; CF=rm64 s< 0; rm64=(rm64<<1)|zext(tmpCF); OF=CF^(rm64 s< 0);}\n\n:RCL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=2 ... \n{ \n local cnt:1=CL&0x3f;\n local rm64_copy:8 = rm64;\n local CF_copy:1 = CF;\n rotated:8 = rm64_copy << cnt;\n rotated = rotated | (rm64_copy >> (65 -cnt));\n local CF_bit:8 = zext(CF_copy) << cnt-1;\n rotated = rotated | CF_bit;\n conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(64-cnt)) & rm64_copy) != 0);\n rm64 = rotated; \n}\n\n:RCL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=2 ... ; imm8 \n{ \n local cnt:1=imm8&0x3f; \n local rm64_copy:8 = rm64;\n local CF_copy:1 = CF;\n rotated:8 = rm64_copy << cnt;\n rotated = rotated | (rm64_copy >> (65 -cnt));\n local CF_bit:8 = zext(CF_copy) << cnt-1;\n rotated = rotated | CF_bit;\n conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(64-cnt)) & rm64_copy) != 0);\n rm64 = rotated;\n}\n@endif\n\n:RCR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm8 s< 0; CF=(rm8&1)!=0; rm8=(rm8>>1)|(tmpCF<<7); OF=OF^(rm8 s< 0); }\n:RCR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=3 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; }\n:RCR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; }\n:RCR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm16 s< 0; CF=(rm16&1)!=0; rm16=(rm16>>1)|(zext(tmpCF)<<15); OF=OF^(rm16 s< 0); }\n:RCR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=3 ... { local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; }\n:RCR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; }\n:RCR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=3 ... { local tmpCF=CF; OF=rm32 s< 0; CF=(rm32&1)!=0; rm32=(rm32>>1)|(zext(tmpCF)<<31); OF=OF^(rm32 s< 0); build check_rm32_dest; }\n:RCR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=3 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; }\n:RCR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=3 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; }\n@ifdef IA64\n:RCR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm64 s< 0; CF=(rm64&1)!=0; rm64=(rm64>>1)|(zext(tmpCF)<<63); OF=OF^(rm64 s< 0); }\n\n:RCR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=3 ... \n{ \n local cnt:1=CL&0x3f; \n local rm64_copy:8 = rm64;\n local CF_copy:1 = CF;\n rotated:8 = rm64_copy >> cnt;\n rotated = rotated | (rm64_copy << (65 -cnt));\n local CF_bit:8 = zext(CF_copy) << 64-cnt;\n rotated = rotated | CF_bit;\n conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(cnt-1)) & rm64_copy) != 0);\n rm64 = rotated;\n }\n\n:RCR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=3 ... ; imm8 \n{ \n local cnt:1=imm8&0x3f; \n local rm64_copy:8 = rm64;\n local CF_copy:1 = CF;\n rotated:8 = rm64_copy >> cnt;\n rotated = rotated | (rm64_copy << (65 -cnt));\n local CF_bit:8 = zext(CF_copy) << 64-cnt;\n rotated = rotated | CF_bit;\n conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(cnt-1)) & rm64_copy) != 0);\n rm64 = rotated;\n }\n@endif\n\n@ifdef IA64\ndefine pcodeop readfsbase;\n:RDFSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=0 & r32 { r32 = readfsbase(); }\n:RDFSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=0 & r64 { r64 = readfsbase(); }\n\ndefine pcodeop readgsbase;\n:RDGSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=1 & r32 { r32 = readgsbase(); }\n:RDGSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=1 & r64 { r64 = readgsbase(); }\n@endif\n\ndefine pcodeop rdmsr;\n:RDMSR is vexMode=0 & byte=0xf; byte=0x32 & check_EAX_dest & check_EDX_dest {\n\ttmp:8 = rdmsr(ECX);\n\tEDX = tmp(4); build check_EDX_dest;\n\tEAX = tmp(0); build check_EAX_dest;\n}\n\ndefine pcodeop readPID;\n:RDPID r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xc7; reg_opcode=7 & r32 { r32 = readPID(); }\n@ifdef IA64\n:RDPID r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xc7; reg_opcode=7 & r64 { r64 = readPID(); }\n@endif\n\ndefine pcodeop rdpkru_u32;\n:RDPKRU is vexMode=0 & byte=0x0f; byte=0x01; byte=0xee { EAX = rdpkru_u32(); }\n\ndefine pcodeop rdpmc;\n:RDPMC is vexMode=0 & byte=0xf; byte=0x33 { tmp:8 = rdpmc(ECX); EDX = tmp(4); EAX = tmp:4; }\n\ndefine pcodeop rdtsc;\n:RDTSC is vexMode=0 & byte=0xf; byte=0x31 { tmp:8 = rdtsc(); EDX = tmp(4); EAX = tmp(0); }\n\n:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xc3 { pop22(IP); EIP=segment(CS,IP); return [EIP]; }\n:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc3 { pop42(IP); EIP=zext(IP); return [EIP]; }\n:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xc3 { pop24(EIP); return [EIP]; }\n:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc3 { pop44(EIP); return [EIP]; }\n@ifdef IA64\n:RET is $(LONGMODE_ON) & vexMode=0 & byte=0xc3 { pop88(RIP); return [RIP]; }\n@endif\n\n:RETF is vexMode=0 & addrsize=0 & opsize=0 & byte=0xcb { pop22(IP); pop22(CS); EIP = segment(CS,IP); return [EIP]; }\n:RETF is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xcb { pop42(IP); EIP=zext(IP); pop42(CS); return [EIP]; } \n@ifdef IA64\n:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xcb { pop82(IP); RIP=zext(IP); pop82(CS); return [RIP]; } \n:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xcb { pop82(IP); RIP=zext(IP); pop82(CS); return [RIP]; } \n@endif\n:RETF is vexMode=0 & addrsize=0 & opsize=1 & byte=0xcb { pop24(EIP); tmp:4=0; pop24(tmp); CS=tmp(0); return [EIP]; }\n:RETF is vexMode=0 & addrsize=1 & opsize=1 & byte=0xcb { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); return [EIP]; }\n@ifdef IA64\n:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xcb { pop48(EIP); RIP=zext(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); return [RIP]; }\n:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcb { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); return [RIP]; }\n@endif\n\n:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xc2; imm16 { pop22(IP); EIP=zext(IP); SP=SP+imm16; return [EIP]; } \n:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc2; imm16 { pop42(IP); EIP=zext(IP); ESP=ESP+imm16; return [EIP]; } \n:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xc2; imm16 { pop24(EIP); SP=SP+imm16; return [EIP]; }\n:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc2; imm16 { pop44(EIP); ESP=ESP+imm16; return [EIP]; }\n@ifdef IA64\n:RET imm16 is $(LONGMODE_ON) & vexMode=0 & byte=0xc2; imm16 { pop88(RIP); RSP=RSP+imm16; return [RIP]; }\n@endif\n\n:RETF imm16 is vexMode=0 & addrsize=0 & opsize=0 & byte=0xca; imm16 { pop22(IP); EIP=zext(IP); pop22(CS); SP=SP+imm16; return [EIP]; } \n:RETF imm16 is vexMode=0 & addrsize=1 & opsize=0 & byte=0xca; imm16 { pop42(IP); EIP=zext(IP); pop42(CS); ESP=ESP+imm16; return [EIP]; } \n@ifdef IA64\n:RETF imm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xca; imm16 { pop82(IP); RIP=zext(IP); pop82(CS); RSP=RSP+imm16; return [RIP]; } \n@endif\n\n:RETF imm16 is vexMode=0 & addrsize=0 & opsize=1 & byte=0xca; imm16 { pop24(EIP); tmp:4=0; pop24(tmp); CS=tmp(0); SP=SP+imm16; return [EIP]; }\n:RETF imm16 is vexMode=0 & addrsize=1 & opsize=1 & byte=0xca; imm16 { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); ESP=ESP+imm16; return [EIP]; }\n@ifdef IA64\n:RETF imm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xca; imm16 { pop84(EIP); tmp:4=0; pop84(tmp); RIP=zext(EIP); CS=tmp(0); RSP=RSP+imm16; return [RIP]; }\n:RETF imm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xca; imm16 { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); RSP=RSP+imm16; return [RIP]; }\n@endif\n\n:ROL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=0 ... { CF = rm8 s< 0; rm8 = (rm8 << 1) | CF; OF = CF ^ (rm8 s< 0); }\n:ROL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=0 ... { local cnt = CL & 0x7; local count_and_mask = CL & 0x1f;rm8 = (rm8 << cnt) | (rm8 >> (8 - cnt)); rolflags(rm8, count_and_mask);}\n:ROL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0x7; rm8 = (rm8 << cnt) | (rm8 >> (8 - cnt)); rolflags(rm8,imm8 & 0x1f:1);}\n:ROL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=0 ... { CF = rm16 s< 0; rm16 = (rm16 << 1) | zext(CF); OF = CF ^ (rm16 s< 0); }\n:ROL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=0 ... { local cnt = CL & 0xf; local count_and_mask = CL & 0x1f;rm16 = (rm16 << cnt) | (rm16 >> (16 - cnt)); rolflags(rm16,count_and_mask);}\n:ROL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0xf; rm16 = (rm16 << cnt) | (rm16 >> (16 - cnt)); rolflags(rm16,imm8 & 0x1f:1);}\n:ROL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=0 ... { CF = rm32 s< 0; rm32 = (rm32 << 1) | zext(CF); OF = CF ^ (rm32 s< 0); build check_rm32_dest; }\n:ROL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=0 ... { local cnt = CL & 0x1f; rm32 = (rm32 << cnt) | (rm32 >> (32 - cnt)); rolflags(rm32,cnt); build check_rm32_dest; }\n:ROL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0x1f; rm32 = (rm32 << cnt) | (rm32 >> (32 - cnt)); rolflags(rm32,cnt); build check_rm32_dest; }\n@ifdef IA64\n:ROL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=0 ... { CF = rm64 s< 0; rm64 = (rm64 << 1) | zext(CF); OF = CF ^ (rm64 s< 0); }\n:ROL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=0 ... { local cnt = CL & 0x3f; rm64 = (rm64 << cnt) | (rm64 >> (64 - cnt)); rolflags(rm64,cnt);}\n:ROL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0x3f; rm64 = (rm64 << cnt) | (rm64 >> (64 - cnt)); rolflags(rm64,cnt);}\n@endif\n \n:ROR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=1 ... { CF = rm8 & 1; rm8 = (rm8 >> 1) | (CF << 7); OF = ((rm8 & 0x40) != 0) ^ (rm8 s< 0); }\n:ROR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=1 ... { local cnt = CL & 0x7; local count_and_mask = CL & 0x1f;rm8 = (rm8 >> cnt) | (rm8 << (8 - cnt)); rorflags(rm8,count_and_mask);}\n:ROR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0x7; rm8 = (rm8 >> cnt) | (rm8 << (8 - cnt)); rorflags(rm8,imm8 & 0x1f:1);}\n:ROR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=1 ... { CF=(rm16 & 1)!=0; rm16=(rm16>>1)|(zext(CF)<<15); OF=((rm16 & 0x4000) != 0) ^ (rm16 s< 0); }\n:ROR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=1 ... { local cnt = CL & 0xf; local count_and_mask = CL & 0x1f; rm16 = (rm16 >> cnt) | (rm16 << (16 - cnt)); rorflags(rm16,count_and_mask);}\n:ROR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0xf; rm16 = (rm16 >> cnt) | (rm16 << (16 - cnt)); rorflags(rm16,imm8 & 0x1f:1);}\n:ROR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=1 ... { CF=(rm32&1)!=0; rm32=(rm32>>1)|(zext(CF)<<31); OF=((rm32&0x40000000)!=0) ^ (rm32 s< 0); build check_rm32_dest; }\n:ROR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=1 ... { local cnt = CL & 0x1f; rm32 = (rm32 >> cnt) | (rm32 << (32 - cnt)); rorflags(rm32,cnt); build check_rm32_dest; }\n:ROR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0x1f; rm32 = (rm32 >> cnt) | (rm32 << (32 - cnt)); rorflags(rm32,cnt); build check_rm32_dest; }\n@ifdef IA64\n:ROR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=1 ... { CF=(rm64&1)!=0; rm64=(rm64>>1)|(zext(CF)<<63); OF=((rm64&0x4000000000000000)!=0) ^ (rm64 s< 0); }\n:ROR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=1 ... { local cnt = CL & 0x3f; rm64 = (rm64 >> cnt) | (rm64 << (64 - cnt)); rorflags(rm64,cnt);}\n:ROR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0x3f; rm64 = (rm64 >> cnt) | (rm64 << (64 - cnt)); rorflags(rm64,cnt);}\n@endif\n\ndefine pcodeop smm_restore_state;\n:RSM is vexMode=0 & byte=0xf; byte=0xaa { tmp:4 = smm_restore_state(); return [tmp]; }\n\n# Initially disallowed in 64bit mode, but later reintroduced\n:SAHF is vexMode=0 & byte=0x9e { SF = (AH & 0x80) != 0;\n ZF = (AH & 0x40) != 0;\n AF = (AH & 0x10) != 0;\n PF = (AH & 0x04) != 0;\n CF = (AH & 0x01) != 0; }\n\n:SALC is vexMode=0 & bit64=0 & byte=0xd6 { AL = CF * 0xff; }\n\n:SAR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=7 ... { CF = rm8 & 1; OF = 0; rm8 = rm8 s>> 1; resultflags(rm8); }\n:SAR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=7 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 s>> count;\n sarflags(tmp, rm8,count); shiftresultflags(rm8,count); }\n:SAR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 s>> count;\n sarflags(tmp, rm8,count); shiftresultflags(rm8,count); }\n:SAR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=7 ... { CF = (rm16 & 1) != 0; OF = 0; rm16 = rm16 s>> 1; resultflags(rm16); }\n:SAR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=7 ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 s>> count;\n sarflags(tmp, rm16,count); shiftresultflags(rm16,count); }\n:SAR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 s>> count;\n sarflags(tmp, rm16,count); shiftresultflags(rm16,count); }\n:SAR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=7 ... { CF = (rm32 & 1) != 0; OF = 0; rm32 = rm32 s>> 1; build check_rm32_dest; resultflags(rm32); }\n:SAR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=7 ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 s>> count; build check_rm32_dest;\n sarflags(tmp, rm32,count); shiftresultflags(rm32,count); }\n:SAR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 s>> count; build check_rm32_dest;\n sarflags(tmp, rm32,count); shiftresultflags(rm32,count); }\n@ifdef IA64\n:SAR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=7 ... { CF = (rm64 & 1) != 0; OF = 0; rm64 = rm64 s>> 1; resultflags(rm64); }\n:SAR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=7 ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 s>> count;\n sarflags(tmp, rm64,count); shiftresultflags(rm64,count); }\n:SAR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 s>> count;\n sarflags(tmp, rm64,count); shiftresultflags(rm64,count); }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:SBB AL,imm8 is vexMode=0 & byte=0x1c; AL & imm8\t\t\t\t\t\t\t\t\t{ subCarryFlags( AL, imm8 ); resultflags(AL); }\n:SBB AX,imm16 is vexMode=0 & opsize=0 & byte=0x1d; AX & imm16\t\t\t\t\t\t{ subCarryFlags( AX, imm16 ); resultflags(AX); }\n:SBB EAX,imm32 is vexMode=0 & opsize=1 & byte=0x1d; EAX & check_EAX_dest & imm32\t{ subCarryFlags( EAX, imm32 ); build check_EAX_dest; resultflags(EAX); }\n@ifdef IA64\n:SBB RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x1d; RAX & simm32\t\t\t\t\t\t{ subCarryFlags( RAX, simm32 ); resultflags(RAX); }\n@endif\n:SBB Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=3; imm8\t\t\t\t\t\t\t\t{ subCarryFlags( Rmr8, imm8 ); resultflags(Rmr8); }\n:SBB Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=3; imm16\t\t\t\t\t\t\t{ subCarryFlags( Rmr16, imm16 ); resultflags(Rmr16); }\n:SBB Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=3; imm32\t{ subCarryFlags( Rmr32, imm32 ); build check_Rmr32_dest; resultflags(Rmr32); }\n@ifdef IA64\n:SBB Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=3; simm32\t\t\t\t\t\t\t{ subCarryFlags( Rmr64, simm32 ); resultflags(Rmr64); }\n@endif\n\n:SBB Rmr16,simm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=3; simm8_16\t\t\t\t\t\t{ subCarryFlags( Rmr16, simm8_16 ); resultflags(Rmr16); }\n:SBB Rmr32,simm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=3; simm8_32\t{ subCarryFlags( Rmr32, simm8_32 ); build check_Rmr32_dest; resultflags(Rmr32); }\n@ifdef IA64\n:SBB Rmr64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=3; simm8_64\t\t\t\t\t\t{ subCarryFlags( Rmr64, simm8_64 ); resultflags(Rmr64); }\n@endif\n\n:SBB Rmr8,Reg8 is vexMode=0 & byte=0x18; mod=3 & Rmr8 & Reg8\t\t\t\t\t\t\t\t\t\t\t{ subCarryFlags( Rmr8, Reg8 ); resultflags(Rmr8); }\n:SBB Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x19; mod=3 & Rmr16 & Reg16\t\t\t\t\t\t{ subCarryFlags( Rmr16, Reg16 ); resultflags(Rmr16); }\n:SBB Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x19; mod=3 & Rmr32 & check_Rmr32_dest & Reg32\t{ subCarryFlags( Rmr32, Reg32 ); build check_Rmr32_dest; resultflags(Rmr32); }\n@ifdef IA64\n:SBB Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x19; mod=3 & Rmr64 & Reg64\t\t\t\t\t\t{ subCarryFlags( Rmr64, Reg64 ); resultflags(Rmr64); }\n@endif\n\n:SBB Reg8,rm8 is vexMode=0 & byte=0x1a; rm8 & Reg8 ...\t\t\t\t\t\t\t\t\t\t\t{ subCarryFlags( Reg8, rm8 ); resultflags(Reg8); }\n:SBB Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x1b; rm16 & Reg16 ...\t\t\t\t\t\t{ subCarryFlags( Reg16, rm16 ); resultflags(Reg16); }\n:SBB Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x1b; rm32 & Reg32 ... & check_Reg32_dest ...\t{ subCarryFlags( Reg32, rm32 ); build check_Reg32_dest; resultflags(Reg32); }\n@ifdef IA64\n:SBB Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x1b; rm64 & Reg64 ...\t\t\t\t\t\t{ subCarryFlags( Reg64, rm64 ); resultflags(Reg64); }\n@endif\n\n:SCASB^repe^repetail eseDI1 is vexMode=0 & repe & repetail & byte=0xae & eseDI1 { build repe; build eseDI1; subflags(AL,eseDI1); local diff=AL-eseDI1; resultflags(diff); build repetail; }\n:SCASW^repe^repetail eseDI2 is vexMode=0 & repe & repetail & opsize=0 & byte=0xaf & eseDI2 { build repe; build eseDI2; subflags(AX,eseDI2); local diff=AX-eseDI2; resultflags(diff); build repetail; }\n:SCASD^repe^repetail eseDI4 is vexMode=0 & repe & repetail & opsize=1 & byte=0xaf & eseDI4 { build repe; build eseDI4; subflags(EAX,eseDI4); local diff=EAX-eseDI4; resultflags(diff); build repetail; }\n@ifdef IA64\n:SCASQ^repe^repetail eseDI8 is $(LONGMODE_ON) & vexMode=0 & repe & repetail & opsize=2 & byte=0xaf & eseDI8 { build repe; build eseDI8; subflags(RAX,eseDI8); local diff=RAX-eseDI8; resultflags(diff); build repetail; }\n@endif\n\n:SET^cc rm8 is vexMode=0 & byte=0xf; row=9 & cc; rm8 { rm8 = cc; }\n\n# manual is not consistent on operands\n:SGDT m16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=0 ) ... & m16\n{\n\tm16 = GlobalDescriptorTableRegister();\n}\n\n:SGDT m32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=0 ) ... & m32\n{\n\tm32 = GlobalDescriptorTableRegister();\n}\n\n@ifdef IA64\n:SGDT m64 is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=0 ) ... & m64\n{\n\tm64 = GlobalDescriptorTableRegister();\n}\n@endif\n\n\n:SHL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 &(reg_opcode=4|reg_opcode=6) ... { CF = rm8 s< 0; rm8 = rm8 << 1; OF = CF ^ (rm8 s< 0); resultflags(rm8); }\n:SHL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 << count;\n shlflags(tmp, rm8,count); shiftresultflags(rm8,count); }\n:SHL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 << count;\n shlflags(tmp, rm8,count); shiftresultflags(rm8,count); }\n:SHL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & (reg_opcode=4|reg_opcode=6) ... { CF = rm16 s< 0; rm16 = rm16 << 1; OF = CF ^ (rm16 s< 0); resultflags(rm16); }\n:SHL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 << count;\n shlflags(tmp, rm16,count); shiftresultflags(rm16,count); }\n:SHL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 << count;\n shlflags(tmp, rm16,count); shiftresultflags(rm16,count); }\n:SHL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & (reg_opcode=4|reg_opcode=6) ... { CF = rm32 s< 0; rm32 = rm32 << 1; OF = CF ^ (rm32 s< 0); build check_rm32_dest; resultflags(rm32); }\n:SHL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 << count; build check_rm32_dest;\n shlflags(tmp, rm32,count); shiftresultflags(rm32,count); }\n:SHL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 << count; build check_rm32_dest;\n shlflags(tmp, rm32,count); shiftresultflags(rm32,count); }\n@ifdef IA64\n:SHL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & (reg_opcode=4|reg_opcode=6) ... { CF = rm64 s< 0; rm64 = rm64 << 1; OF = CF ^ (rm64 s< 0); resultflags(rm64); }\n:SHL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 << count;\n shlflags(tmp, rm64,count); shiftresultflags(rm64,count); }\n:SHL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 << count;\n shlflags(tmp, rm64,count); shiftresultflags(rm64,count); }\n@endif\n\n:SHLD rm16,Reg16,imm8 is vexMode=0 & opsize=0; byte=0x0F; byte=0xA4; rm16 & Reg16 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16;\n rm16 = (rm16 << count) | (Reg16 >> (16 - count));\n shlflags(tmp,rm16,count); shiftresultflags(rm16,count);}\n:SHLD rm16,Reg16,CL is vexMode=0 & opsize=0; byte=0x0F; byte=0xA5; CL & rm16 & Reg16 ... { local count = CL & 0x1f; local tmp = rm16;\n rm16 = (rm16 << count) | (Reg16 >> (16 - count));\n shlflags(tmp,rm16,count); shiftresultflags(rm16,count); }\n:SHLD rm32,Reg32,imm8 is vexMode=0 & opsize=1; byte=0x0F; byte=0xA4; rm32 & check_rm32_dest ... & Reg32 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32;\n rm32 = (rm32 << count) | (Reg32 >> (32 - count)); build check_rm32_dest;\n shlflags(tmp,rm32,count); shiftresultflags(rm32,count); }\n:SHLD rm32,Reg32,CL is vexMode=0 & opsize=1; byte=0x0F; byte=0xA5; CL & rm32 & check_rm32_dest ... & Reg32 ... { local count = CL & 0x1f; local tmp = rm32;\n rm32 = (rm32 << count) | (Reg32 >> (32 - count)); build check_rm32_dest;\n shlflags(tmp,rm32,count); shiftresultflags(rm32,count); }\n@ifdef IA64\n:SHLD rm64,Reg64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xA4; rm64 & Reg64 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64;\n rm64 = (rm64 << count) | (Reg64 >> (64 - count));\n shlflags(tmp,rm64,count); shiftresultflags(rm64,count); }\n:SHLD rm64,Reg64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xA5; CL & rm64 & Reg64 ... { local count = CL & 0x3f; local tmp = rm64;\n rm64 = (rm64 << count) | (Reg64 >> (64 - count));\n shlflags(tmp,rm64,count); shiftresultflags(rm64,count); }\n@endif\n\n:SHRD rm16,Reg16,imm8 is vexMode=0 & opsize=0; byte=0x0F; byte=0xAC; rm16 & Reg16 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16;\n rm16 = (rm16 >> count) | (Reg16 << (16 - count));\n shrdflags(tmp,rm16,count); shiftresultflags(rm16,count); }\n:SHRD rm16,Reg16,CL is vexMode=0 & opsize=0; byte=0x0F; byte=0xAD; CL & rm16 & Reg16 ... { local count = CL & 0x1f; local tmp = rm16;\n rm16 = (rm16 >> count) | (Reg16 << (16 - count));\n shrdflags(tmp,rm16,count); shiftresultflags(rm16,count); }\n:SHRD rm32,Reg32,imm8 is vexMode=0 & opsize=1; byte=0x0F; byte=0xAC; rm32 & check_rm32_dest ... & Reg32 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32;\n rm32 = (rm32 >> count) | (Reg32 << (32 - count)); build check_rm32_dest;\n shrdflags(tmp,rm32,count); shiftresultflags(rm32,count); }\n:SHRD rm32,Reg32,CL is vexMode=0 & opsize=1; byte=0x0F; byte=0xAD; CL & rm32 & check_rm32_dest ... & Reg32 ... { local count = CL & 0x1f; local tmp = rm32;\n rm32 = (rm32 >> count) | (Reg32 << (32 - count)); build check_rm32_dest;\n shrdflags(tmp,rm32,count); shiftresultflags(rm32,count); }\n@ifdef IA64\n:SHRD rm64,Reg64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xAC; rm64 & Reg64 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64;\n rm64 = (rm64 >> count) | (Reg64 << (64 - count));\n shrdflags(tmp,rm64,count); shiftresultflags(rm64,count); }\n:SHRD rm64,Reg64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xAD; CL & rm64 & Reg64 ... { local count = CL & 0x3f; local tmp = rm64;\n rm64 = (rm64 >> count) | (Reg64 << (64 - count));\n shrdflags(tmp,rm64,count); shiftresultflags(rm64,count); }\n@endif\n\n:SHR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=5 ... { CF = rm8 & 1; OF = 0; rm8 = rm8 >> 1; resultflags(rm8); }\n:SHR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 >> count;\n shrflags(tmp, rm8,count); shiftresultflags(rm8,count); }\n:SHR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 >> count;\n shrflags(tmp, rm8,count); shiftresultflags(rm8,count); }\n:SHR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=5 ... { CF = (rm16 & 1) != 0; OF = 0; rm16 = rm16 >> 1; resultflags(rm16); }\n:SHR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 >> count;\n shrflags(tmp, rm16,count); shiftresultflags(rm16,count); }\n:SHR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 >> count;\n shrflags(tmp, rm16,count); shiftresultflags(rm16,count); }\n:SHR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=5 ... { CF = (rm32 & 1) != 0; OF = 0; rm32 = rm32 >> 1; build check_rm32_dest; resultflags(rm32); }\n:SHR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest;\n shrflags(tmp, rm32,count); shiftresultflags(rm32,count); }\n:SHR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest;\n shrflags(tmp, rm32,count); shiftresultflags(rm32,count); }\n@ifdef IA64\n:SHR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 ®_opcode=5 ... { CF = (rm64 & 1) != 0; OF = 0; rm64 = rm64 >> 1; resultflags(rm64); }\n:SHR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=5 ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 >> count;\n shrflags(tmp, rm64,count); shiftresultflags(rm64,count); }\n:SHR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 >> count;\n shrflags(tmp, rm64,count); shiftresultflags(rm64,count); }\n@endif\n\n:SIDT m16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=1 ) ... & m16\n{\n\tm16 = InterruptDescriptorTableRegister();\n}\n\n:SIDT m32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=1 ) ... & m32\n{\n\tm32 = InterruptDescriptorTableRegister();\n}\n@ifdef IA64\n:SIDT m64 is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=1 ) ... & m64\n{\n\tm64 = InterruptDescriptorTableRegister();\n}\n@endif\n\ndefine pcodeop skinit;\n:SKINIT EAX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xde & EAX { skinit(EAX); }\n\n:SLDT rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=0 ...\n{\n\trm16 = LocalDescriptorTableRegister();\n}\n:SLDT rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x0; rm32 & reg_opcode=0 ...\n{\n\trm32 = LocalDescriptorTableRegister();\n}\n@ifdef IA64\n:SLDT rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x0; rm64 & reg_opcode=0 ...\n{\n\trm64 = LocalDescriptorTableRegister();\n}\n@endif\n\n:SMSW rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x01; rm16 & reg_opcode=4 ... { rm16 = CR0:2; }\n:SMSW rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x01; rm32 & reg_opcode=4 ... { rm32 = zext(CR0:2); }\n@ifdef IA64\n:SMSW rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x01; rm64 & reg_opcode=4 ... { rm64 = CR0; }\n@endif\n\n:STAC is vexMode=0 & byte=0x0f; byte=0x01; byte=0xcb { AC = 1; }\n:STC is vexMode=0 & byte=0xf9 { CF = 1; }\n:STD is vexMode=0 & byte=0xfd { DF = 1; }\n# MFL: AMD instruction\n# TODO: define the action.\n# STGI: set global interrupt flag (GIF); while GIF is zero, all external interrupts are disabled.\n:STGI is vexMode=0 & byte=0x0f; byte=0x01; byte=0xdc { stgi(); }\n:STI is vexMode=0 & byte=0xfb { IF = 1; }\n\n:STMXCSR m32 is vexMode=0 & byte=0xf; byte=0xae; ( mod != 0b11 & reg_opcode=3 ) ... & m32 { m32 = MXCSR; }\n\n:STOSB^rep^reptail eseDI1 is vexMode=0 & rep & reptail & byte=0xaa & eseDI1 { build rep; build eseDI1; eseDI1=AL; build reptail; }\n:STOSW^rep^reptail eseDI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xab & eseDI2 { build rep; build eseDI2; eseDI2=AX; build reptail; }\n:STOSD^rep^reptail eseDI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xab & eseDI4 { build rep; build eseDI4; eseDI4=EAX; build reptail; }\n@ifdef IA64\n:STOSQ^rep^reptail eseDI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xab & eseDI8 { build rep; build eseDI8; eseDI8=RAX; build reptail; }\n@endif\n\n:STR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=1 ... { rm16 = TaskRegister(); }\n:STR Rmr32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x0; Rmr32 & mod=3 & reg_opcode=1 & check_Rmr32_dest {\n\tlocal tmp:2 = TaskRegister();\n\tRmr32 = zext(tmp);\n\tbuild check_Rmr32_dest;\n}\n@ifdef IA64\n:STR Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x0; Rmr64 & mod=3 & reg_opcode=1 {\n\tlocal tmp:2 = TaskRegister();\n\tRmr64 = zext(tmp);\n}\n@endif\n\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:SUB AL,imm8 is vexMode=0 & byte=0x2c; AL & imm8 { subflags( AL,imm8 ); AL = AL - imm8; resultflags( AL); }\n:SUB AX,imm16 is vexMode=0 & opsize=0 & byte=0x2d; AX & imm16 { subflags( AX,imm16); AX = AX - imm16; resultflags( AX); }\n:SUB EAX,imm32 is vexMode=0 & opsize=1 & byte=0x2d; EAX & check_EAX_dest & imm32 { subflags( EAX,imm32); EAX = EAX - imm32; build check_EAX_dest; resultflags( EAX); }\n@ifdef IA64\n:SUB RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x2d; RAX & simm32 { subflags( RAX,simm32); RAX = RAX - simm32; resultflags( RAX); }\n@endif\n:SUB Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=5; imm8 { subflags( Rmr8,imm8 ); Rmr8 = Rmr8 - imm8; resultflags( Rmr8); }\n:SUB Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=5; imm16 { subflags( Rmr16,imm16); Rmr16 = Rmr16 - imm16; resultflags( Rmr16); }\n:SUB Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=5; imm32 { subflags( Rmr32,imm32); Rmr32 = Rmr32 - imm32; build check_rm32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:SUB Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=5; simm32 { subflags( Rmr64,simm32); Rmr64 = Rmr64 - simm32; resultflags( Rmr64); }\n@endif\n:SUB Rmr16,simm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=5; simm8_16 { subflags( Rmr16,simm8_16); Rmr16 = Rmr16 - simm8_16; resultflags( Rmr16); }\n:SUB Rmr32,simm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=5; simm8_32 { subflags( Rmr32,simm8_32); Rmr32 = Rmr32 - simm8_32; build check_rm32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:SUB Rmr64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=5; simm8_64 { subflags( Rmr64,simm8_64); Rmr64 = Rmr64 - simm8_64; resultflags( Rmr64); }\n@endif\n:SUB Rmr8,Reg8 is vexMode=0 & byte=0x28; mod=3 & Rmr8 & Reg8 { subflags( Rmr8,Reg8 ); Rmr8 = Rmr8 - Reg8; resultflags( Rmr8); }\n:SUB Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x29; mod=3 & Rmr16 & Reg16 { subflags( Rmr16,Reg16); Rmr16 = Rmr16 - Reg16; resultflags( Rmr16); }\n:SUB Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x29; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { subflags( Rmr32,Reg32); Rmr32 = Rmr32 - Reg32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:SUB Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x29; mod=3 & Rmr64 & Reg64 { subflags( Rmr64,Reg64); Rmr64 = Rmr64 - Reg64; resultflags( Rmr64); }\n@endif\n:SUB Reg8,rm8 is vexMode=0 & byte=0x2a; rm8 & Reg8 ... { subflags( Reg8,rm8 ); Reg8 = Reg8 - rm8; resultflags( Reg8); }\n:SUB Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x2b; rm16 & Reg16 ... { subflags(Reg16,rm16 ); Reg16 = Reg16 - rm16; resultflags(Reg16); }\n:SUB Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x2b; rm32 & Reg32 ... & check_Reg32_dest ... { subflags(Reg32,rm32 ); Reg32 = Reg32 - rm32; build check_Reg32_dest; resultflags(Reg32); }\n@ifdef IA64\n:SUB Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x2b; rm64 & Reg64 ... { subflags(Reg64,rm64 ); Reg64 = Reg64 - rm64; resultflags(Reg64); }\n@endif\n\n:SYSENTER is vexMode=0 & byte=0x0f; byte=0x34 { sysenter(); }\n:SYSEXIT is vexMode=0 & byte=0x0f; byte=0x35 { sysexit();\n@ifdef IA64\n RIP=RCX; return [RIP];\n@endif\n }\n\n:SYSCALL is vexMode=0 & byte=0x0f; byte=0x05 { syscall(); }\n\n# returning to 32bit mode loads ECX\n# returning to 64bit mode loads RCX\n:SYSRET is vexMode=0 & byte=0x0f; byte=0x07 { sysret();\n@ifdef IA64\n RIP=RCX; return [RIP];\n@endif\n }\n\n:SWAPGS is vexMode=0 & bit64=1 & byte=0x0f; byte=0x01; byte=0xf8 { swapgs(); }\n\n:RDTSCP is vexMode=0 & bit64=1 & byte=0x0f; byte=0x01; byte=0xf9 { rdtscp(); }\n\n:TEST AL,imm8 is vexMode=0 & byte=0xA8; AL & imm8 { logicalflags(); local tmp = AL & imm8; resultflags(tmp); }\n:TEST AX,imm16 is vexMode=0 & opsize=0; byte=0xA9; AX & imm16 { logicalflags(); local tmp = AX & imm16; resultflags(tmp); }\n:TEST EAX,imm32 is vexMode=0 & opsize=1; byte=0xA9; EAX & imm32 { logicalflags(); local tmp = EAX & imm32; resultflags(tmp); }\n@ifdef IA64\n:TEST RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0xA9; RAX & simm32 { logicalflags(); local tmp = RAX & simm32; resultflags(tmp); }\n@endif\n:TEST rm8,imm8 is vexMode=0 & byte=0xF6; rm8 & (reg_opcode=0 | reg_opcode=1) ... ; imm8 { logicalflags(); local tmp = rm8 & imm8; resultflags(tmp); }\n:TEST rm16,imm16 is vexMode=0 & opsize=0; byte=0xF7; rm16 & (reg_opcode=0 | reg_opcode=1) ... ; imm16 { logicalflags(); local tmp = rm16 & imm16; resultflags(tmp); }\n:TEST rm32,imm32 is vexMode=0 & opsize=1; byte=0xF7; rm32 & (reg_opcode=0 | reg_opcode=1) ... ; imm32 { logicalflags(); local tmp = rm32 & imm32; resultflags(tmp); }\n@ifdef IA64\n:TEST rm64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0xF7; rm64 & (reg_opcode=0 | reg_opcode=1) ... ; simm32 { logicalflags(); local tmp = rm64 & simm32; resultflags(tmp); }\n@endif\n:TEST rm8,Reg8 is vexMode=0 & byte=0x84; rm8 & Reg8 ... { logicalflags(); local tmp = rm8 & Reg8; resultflags(tmp); }\n:TEST rm16,Reg16 is vexMode=0 & opsize=0; byte=0x85; rm16 & Reg16 ... { logicalflags(); local tmp = rm16 & Reg16; resultflags(tmp); }\n:TEST rm32,Reg32 is vexMode=0 & opsize=1; byte=0x85; rm32 & Reg32 ... { logicalflags(); local tmp = rm32 & Reg32; resultflags(tmp); }\n@ifdef IA64\n:TEST rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x85; rm64 & Reg64 ... { logicalflags(); local tmp = rm64 & Reg64; resultflags(tmp); }\n@endif\n\ndefine pcodeop invalidInstructionException;\n:UD0 Reg32, rm32 is vexMode=0 & byte=0x0f; byte=0xff; rm32 & Reg32 ... { local target:$(SIZE) = invalidInstructionException(); goto [target]; }\n:UD1 Reg32, rm32 is vexMode=0 & byte=0x0f; byte=0xb9; rm32 & Reg32 ... { local target:$(SIZE) = invalidInstructionException(); goto [target]; }\n:UD2 is vexMode=0 & byte=0xf; byte=0xb { local target:$(SIZE) = invalidInstructionException(); goto [target]; }\n\ndefine pcodeop verr;\ndefine pcodeop verw;\n:VERR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=4 ... { ZF = verr(); }\n:VERW rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=5 ... { ZF = verw(); }\n\n# MFL added VMX opcodes\n#\n# AMD hardware assisted virtualization opcodes\n:VMLOAD EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xda & EAX { vmload(EAX); }\n@ifdef IA64\n:VMLOAD RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xda & RAX { vmload(RAX); }\n@endif\n:VMMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd9 { vmmcall(); }\n# Limiting the effective address size to 32 and 64 bit. Surely we're not expecting a 16-bit VM address, are we?\n:VMRUN EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xd8 & EAX { vmrun(EAX); }\n@ifdef IA64\n:VMRUN RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xd8 & RAX { vmrun(RAX); }\n@endif\n# Limiting the effective address size to 32 and 64 bit. Surely we're not expecting a 16-bit VM address, are we?\n:VMSAVE EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xdb & EAX { vmsave(EAX); }\n@ifdef IA64\n:VMSAVE RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xdb & RAX { vmsave(RAX); }\n@endif\n#\n\n#\n# Intel hardware assisted virtualization opcodes\n@ifdef IA64\n:INVEPT Reg64, m128 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg64 ... & m128 { invept(Reg64, m128); }\n@endif\n:INVEPT Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg32 ... & m128 { invept(Reg32, m128); }\n@ifdef IA64\n:INVVPID Reg64, m128 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg64 ... & m128 { invvpid(Reg64, m128); }\n@endif\n:INVVPID Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg32 ... & m128 { invvpid(Reg32, m128); }\n:VMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc1 { vmcall(); }\n@ifdef IA64\n:VMCLEAR m64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmclear(m64); }\n@endif\n#TODO: invokes a VM function specified in EAX\n:VMFUNC EAX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd4 & EAX { vmfunc(EAX); }\n#TODO: this launches the VM managed by the current VMCS. How is the VMCS expressed for the emulator? For Ghidra analysis?\n:VMLAUNCH is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc2 { vmlaunch(); }\n#TODO: this resumes the VM managed by the current VMCS. How is the VMCS expressed for the emulator? For Ghidra analysis?\n:VMRESUME is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc3 { vmresume(); }\n#TODO: this loads the VMCS pointer from the m64 memory address and makes the VMCS pointer valid; how to express\n# this for analysis and emulation?\n:VMPTRLD m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmptrld(m64); }\n#TODO: stores the current VMCS pointer into the specified 64-bit memory address; how to express this for analysis and emulation?\n#TODO: note that the Intel manual does not specify m64 (which it does for VMPTRLD, yet it does state that \"the operand\n# of this instruction is always 64-bits and is always in memory\". Is it an error that the \"Instruction\" entry in the \n# box giving the definition does not specify m64?\n:VMPTRST m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=7 ) ... & m64 { vmptrst(m64); }\n:VMREAD rm32, Reg32 is $(PRE_NO) & vexMode=0 & opsize=1 & byte=0x0f; byte=0x78; rm32 & check_rm32_dest ... & Reg32 ... { rm32 = vmread(Reg32); build check_rm32_dest; }\n@ifdef IA64\n:VMREAD rm64, Reg64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x78; rm64 & Reg64 ... { rm64 = vmread(Reg64); }\n@endif\n:VMWRITE Reg32, rm32 is $(PRE_NO) & vexMode=0 & opsize=1 & byte=0x0f; byte=0x79; rm32 & Reg32 ... & check_Reg32_dest ... { vmwrite(rm32,Reg32); build check_Reg32_dest; }\n@ifdef IA64\n:VMWRITE Reg64, rm64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x79; rm64 & Reg64 ... { vmwrite(rm64,Reg64); }\n@endif\n:VMXOFF is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc4 { vmxoff(); }\n# NB: this opcode is incorrect in the 2005 edition of the Intel manual. Opcode below is taken from the 2008 version.\n:VMXON m64 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmxon(m64); }\n\n#END of changes for VMX opcodes\n\n:WAIT is vexMode=0 & byte=0x9b { }\n:WBINVD is vexMode=0 & byte=0xf; byte=0x9 { }\n\n@ifdef IA64\ndefine pcodeop writefsbase;\n:WRFSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=2 & r32 { tmp:8 = zext(r32); writefsbase(tmp); }\n:WRFSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=2 & r64 { writefsbase(r64); }\n\ndefine pcodeop writegsbase;\n:WRGSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=3 & r32 { tmp:8 = zext(r32); writegsbase(tmp); }\n:WRGSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=3 & r64 { writegsbase(r64); }\n@endif\n\ndefine pcodeop wrpkru;\n:WRPKRU is byte=0x0F; byte=0x01; byte=0xEF { wrpkru(EAX); }\n\ndefine pcodeop wrmsr;\n:WRMSR is vexMode=0 & byte=0xf; byte=0x30 { tmp:8 = (zext(EDX) << 32) | zext(EAX); wrmsr(ECX,tmp); }\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:XADD Rmr8,Reg8 \tis vexMode=0 & byte=0x0F; byte=0xC0; mod=3 & Rmr8 & Reg8 { addflags( Rmr8,Reg8 ); local tmp = Rmr8 + Reg8; Reg8 = Rmr8; Rmr8 = tmp; resultflags(tmp); }\n:XADD Rmr16,Reg16\tis vexMode=0 & opsize=0 & byte=0x0F; byte=0xC1; mod=3 & Rmr16 & Reg16 { addflags(Rmr16,Reg16); local tmp = Rmr16 + Reg16; Reg16 = Rmr16; Rmr16 = tmp; resultflags(tmp); }\n:XADD Rmr32,Reg32\tis vexMode=0 & opsize=1 & byte=0x0F; byte=0xC1; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 & check_Reg32_dest { addflags(Rmr32,Reg32); local tmp = Rmr32 + Reg32; Reg32 = Rmr32; Rmr32 = tmp; build check_Rmr32_dest; build check_Reg32_dest; resultflags(tmp); }\n@ifdef IA64\n:XADD Rmr64,Reg64\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xC1; mod=3 & Rmr64 & Reg64 { addflags(Rmr64,Reg64); local tmp = Rmr64 + Reg64; Reg64 = Rmr64; Rmr64 = tmp; resultflags(tmp); }\n@endif\n\ndefine pcodeop xabort;\n\n:XABORT imm8 is vexMode=0 & byte=0xc6; byte=0xf8; imm8 { tmp:1 = imm8; xabort(tmp); }\n\ndefine pcodeop xbegin;\ndefine pcodeop xend;\n\n:XBEGIN rel16 is vexMode=0 & opsize=0 & byte=0xc7; byte=0xf8; rel16 { xbegin(&:$(SIZE) rel16); }\n:XBEGIN rel32 is vexMode=0 & (opsize=1 | opsize=2) & byte=0xc7; byte=0xf8; rel32 { xbegin(&:$(SIZE) rel32); }\n\n:XEND is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd5 { xend(); }\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:XCHG AX,Rmr16 is vexMode=0 & opsize=0 & row = 9 & page = 0 & AX & Rmr16 { local tmp = AX; AX = Rmr16; Rmr16 = tmp; }\n:XCHG EAX,Rmr32 is vexMode=0 & opsize=1 & row = 9 & page = 0 & EAX & check_EAX_dest & Rmr32 & check_Rmr32_dest { local tmp = EAX; EAX = Rmr32; build check_EAX_dest; Rmr32 = tmp; build check_Rmr32_dest; }\n@ifdef IA64\n:XCHG RAX,Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & row = 9 & page = 0 & RAX & Rmr64 { local tmp = RAX; RAX = Rmr64; Rmr64 = tmp; }\n@endif\n\n:XCHG Rmr8,Reg8 is vexMode=0 & byte=0x86; mod=3 & Rmr8 & Reg8 { local tmp = Rmr8; Rmr8 = Reg8; Reg8 = tmp; }\n:XCHG Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x87; mod=3 & Rmr16 & Reg16 { local tmp = Rmr16; Rmr16 = Reg16; Reg16 = tmp; }\n:XCHG Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x87; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 & check_Reg32_dest\t{ local tmp = Rmr32; Rmr32 = Reg32; build check_Rmr32_dest; Reg32 = tmp; build check_Reg32_dest;}\n@ifdef IA64\n:XCHG Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x87; mod=3 & Rmr64 & Reg64 { local tmp = Rmr64; Rmr64 = Reg64; Reg64 = tmp; }\n@endif\n\n:XLAT seg16^BX is vexMode=0 & addrsize=0 & seg16 & byte=0xd7; BX { tmp:$(SIZE)= 0; ptr2(tmp,BX+zext(AL)); AL = *tmp; }\n:XLAT segWide^EBX is vexMode=0 & addrsize=1 & segWide & byte=0xd7; EBX { tmp:$(SIZE)= 0; ptr4(tmp,EBX+zext(AL)); AL = *tmp; }\n@ifdef IA64\n:XLAT segWide^RBX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & segWide & byte=0xd7; RBX { tmp:$(SIZE)= 0; ptr8(tmp,RBX+zext(AL)); AL = *tmp; }\n@endif\n\n# See 'lockable.sinc' for memory destination, lockable variants\n:XOR AL,imm8 is vexMode=0 & byte=0x34; AL & imm8 { logicalflags(); AL = AL ^ imm8; resultflags( AL); }\n:XOR AX,imm16 is vexMode=0 & opsize=0 & byte=0x35; AX & imm16 { logicalflags(); AX = AX ^ imm16; resultflags( AX); }\n:XOR EAX,imm32 is vexMode=0 & opsize=1 & byte=0x35; EAX & imm32 & check_EAX_dest\t{ logicalflags(); EAX = EAX ^ imm32; build check_EAX_dest; resultflags( EAX);}\n@ifdef IA64\n:XOR RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x35; RAX & simm32 { logicalflags(); RAX = RAX ^ simm32; resultflags( RAX); }\n@endif\n:XOR Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=6; imm8 { logicalflags(); Rmr8 = Rmr8 ^ imm8; resultflags( Rmr8); }\n:XOR Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=6; imm16 { logicalflags(); Rmr16 = Rmr16 ^ imm16; resultflags( Rmr16); }\n:XOR Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=6; imm32 { logicalflags(); Rmr32 = Rmr32 ^ imm32; build check_rm32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:XOR Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=6; simm32 { logicalflags(); Rmr64 = Rmr64 ^ simm32; resultflags( Rmr64); }\n@endif\n:XOR Rmr16,usimm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=6; usimm8_16 { logicalflags(); Rmr16 = Rmr16 ^ usimm8_16; resultflags( Rmr16); }\n:XOR Rmr32,usimm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=6; usimm8_32 { logicalflags(); Rmr32 = Rmr32 ^ usimm8_32; build check_rm32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:XOR Rmr64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=6; usimm8_64 { logicalflags(); Rmr64 = Rmr64 ^ usimm8_64; resultflags( Rmr64); }\n@endif\n:XOR Rmr8,Reg8 is vexMode=0 & byte=0x30; mod=3 & Rmr8 & Reg8 { logicalflags(); Rmr8 = Rmr8 ^ Reg8; resultflags( Rmr8); }\n:XOR Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x31; mod=3 & Rmr16 & Reg16 { logicalflags(); Rmr16 = Rmr16 ^ Reg16; resultflags( Rmr16); }\n:XOR Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x31; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { logicalflags(); Rmr32 = Rmr32 ^ Reg32; build check_Rmr32_dest; resultflags( Rmr32); }\n@ifdef IA64\n:XOR Rmr64,Reg64 is vexMode=0 & $(LONGMODE_ON) & opsize=2 & byte=0x31; mod=3 & Rmr64 & Reg64 { logicalflags(); Rmr64 = Rmr64 ^ Reg64; resultflags( Rmr64); }\n@endif\n:XOR Reg8,rm8 is vexMode=0 & byte=0x32; rm8 & Reg8 ... { logicalflags(); Reg8 = Reg8 ^ rm8; resultflags( Reg8); }\n:XOR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x33; rm16 & Reg16 ... { logicalflags(); Reg16 = Reg16 ^ rm16; resultflags(Reg16); }\n:XOR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x33; rm32 & Reg32 ... & check_Reg32_dest ... { logicalflags(); Reg32 = Reg32 ^ rm32; build check_Reg32_dest; resultflags(Reg32); }\n@ifdef IA64\n:XOR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x33; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 ^ rm64; resultflags(Reg64); }\n@endif\n\n:XGETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD0 { local tmp = XCR0 >> 32; EDX = tmp:4; EAX = XCR0:4; }\n:XSETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD1 { XCR0 = (zext(EDX) << 32) | zext(EAX); }\n\ndefine pcodeop xsave;\ndefine pcodeop xsave64;\ndefine pcodeop xsavec;\ndefine pcodeop xsavec64;\ndefine pcodeop xsaveopt;\ndefine pcodeop xsaveopt64;\ndefine pcodeop xsaves;\ndefine pcodeop xsaves64;\ndefine pcodeop xrstor;\ndefine pcodeop xrstor64;\ndefine pcodeop xrstors;\ndefine pcodeop xrstors64;\n\n:XRSTOR Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xrstor(Mem, tmp); }\n@ifdef IA64\n:XRSTOR64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xrstor64(Mem, tmp); }\n@endif\n\n:XRSTORS Mem is vexMode=0 & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=3 ) ... & Mem { tmp:4 = 512; xrstors(Mem, tmp); }\n@ifdef IA64\n:XRSTORS64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=3 ) ... & Mem { tmp:4 = 512; xrstors64(Mem, tmp); }\n@endif\n\n:XSAVE Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsave(Mem, tmp); }\n@ifdef IA64\n:XSAVE64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsave64(Mem, tmp); }\n@endif\n\n:XSAVEC Mem is vexMode=0 & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsavec(Mem, tmp); }\n@ifdef IA64\n:XSAVEC64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsavec64(Mem, tmp); }\n@endif\n\n:XSAVEOPT Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=6 ) ... & Mem { tmp:4 = 512; xsaveopt(Mem, tmp); }\n@ifdef IA64\n:XSAVEOPT64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=6 ) ... & Mem { tmp:4 = 512; xsaveopt64(Mem, tmp); }\n@endif\n\n:XSAVES Mem is vexMode=0 & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xsaves(Mem, tmp); }\n@ifdef IA64\n:XSAVES64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xsaves64(Mem, tmp); }\n@endif\n\ndefine pcodeop xtest;\n:XTEST is byte=0x0F; byte=0x01; byte=0xD6 { ZF = xtest(); }\n\n:LFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=5 & r_m=0 { }\n:MFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=6 & r_m=0 { }\n:SFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=7 & r_m=0 { }\n\n#\n# floating point instructions\n#\ndefine pcodeop f2xm1;\n:F2XM1 is vexMode=0 & byte=0xD9; byte=0xF0 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = f2xm1(ST0); \n} # compute 2^x-1\n\n:FABS is vexMode=0 & byte=0xD9; byte=0xE1 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = abs(ST0); \n}\n \n:FADD m32fp is vexMode=0 & byte=0xD8; reg_opcode=0 ... & m32fp \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f+ float2float(m32fp); \n}\n \n:FADD m64fp is vexMode=0 & byte=0xDC; reg_opcode=0 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f+ float2float(m64fp); \n} \n\n:FADD ST0, freg is vexMode=0 & byte=0xD8; frow=12 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f+ freg; \n}\n \n:FADD freg, ST0 is vexMode=0 & byte=0xDC; frow=12 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = freg f+ ST0; \n} \n\n:FADDP is vexMode=0 & byte=0xDE; byte=0xC1 \n{ \n FPUInstructionPointer = inst_start;\n ST1 = ST0 f+ ST1; \n fpop(); \n} \n\n:FADDP freg, ST0 is vexMode=0 & byte=0xDE; frow=12 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = ST0 f+ freg; \n fpop();\n} \n\n:FIADD m32 is vexMode=0 & byte=0xDA; reg_opcode=0 ... & m32 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f+ int2float(m32); \n} \n\n:FIADD m16 is vexMode=0 & byte=0xDE; reg_opcode=0 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f+ int2float(m16); \n} \n\ndefine pcodeop from_bcd;\n:FBLD m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & m80 \n{ \n FPUInstructionPointer = inst_start;\n fdec(); \n ST0 = from_bcd(m80); \n}\n\ndefine pcodeop to_bcd;\n:FBSTP m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & m80 \n{ \n FPUInstructionPointer = inst_start;\n m80 = to_bcd(ST0); \n fpop(); \n}\n\n:FCHS is vexMode=0 & byte=0xD9; byte=0xE0 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = f- ST0; \n}\n\n:FCLEX is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE2 \n{ \n FPUStatusWord[0,8] = 0; \n FPUStatusWord[15,1] = 0; \n}\n\n:FNCLEX is vexMode=0 & byte=0xDB; byte=0xE2 \n{ \n FPUStatusWord[0,8] = 0; \n FPUStatusWord[15,1] = 0; \n} \n\n:FCMOVB ST0, freg is vexMode=0 & byte=0xDA; frow=12 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( !CF ) goto inst_next; \n ST0 = freg; \n} \n\n:FCMOVE ST0, freg is vexMode=0 & byte=0xDA; frow=12 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( !ZF ) goto inst_next; \n ST0 = freg; \n} \n\n:FCMOVBE ST0, freg is vexMode=0 & byte=0xDA; frow=13 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( !CF & !ZF ) goto inst_next; \n ST0 = freg; \n} \n\n:FCMOVU ST0, freg is vexMode=0 & byte=0xDA; frow=13 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( !PF ) goto inst_next; \n ST0 = freg; \n} \n\n:FCMOVNB ST0, freg is vexMode=0 & byte=0xDB; frow=12 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( CF ) goto inst_next; \n ST0 = freg; \n} \n\n:FCMOVNE ST0, freg is vexMode=0 & byte=0xDB; frow=12 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( ZF ) goto inst_next; \n ST0 = freg; \n} \n\n:FCMOVNBE ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( CF & ZF ) goto inst_next; \n ST0 = freg; \n} \n:FCMOVNU ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n if ( PF ) goto inst_next; \n ST0 = freg; \n} \n \n:FCOM m32fp is vexMode=0 & byte=0xD8; reg_opcode=2 ... & m32fp \n{\n FPUInstructionPointer = inst_start; \n local tmp=float2float(m32fp); \n fcom(tmp); \n} \n\n:FCOM m64fp is vexMode=0 & byte=0xDC; reg_opcode=2 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n local tmp=float2float(m64fp); \n fcom(tmp); \n} \n\n:FCOM freg is vexMode=0 & byte=0xD8; frow=13 & fpage=0 & freg \n{ \n FPUInstructionPointer = inst_start;\n fcom(freg); \n} \n\n:FCOM is vexMode=0 & byte=0xD8; byte=0xD1 \n{ \n FPUInstructionPointer = inst_start;\n fcom(ST1);\n} \n\n:FCOMP m32fp is vexMode=0 & byte=0xD8; reg_opcode=3 ... & m32fp \n{ \n FPUInstructionPointer = inst_start;\n local tmp=float2float(m32fp); \n fcom(tmp); \n fpop(); \n} \n\n:FCOMP m64fp is vexMode=0 & byte=0xDC; reg_opcode=3 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n local tmp=float2float(m64fp); \n fcom(tmp); \n fpop(); \n} \n\n:FCOMP freg is vexMode=0 & byte=0xD8; frow=13 & fpage=1 & freg \n{\n FPUInstructionPointer = inst_start; \n fcom(freg); \n fpop(); \n} \n\n:FCOMP is vexMode=0 & byte=0xD8; byte=0xD9 \n{ \n FPUInstructionPointer = inst_start;\n fcom(ST1); \n fpop();\n} \n\n:FCOMPP is vexMode=0 & byte=0xDE; byte=0xD9 \n{ \n FPUInstructionPointer = inst_start;\n fcom(ST1); \n fpop(); \n fpop(); \n} \n \n:FCOMI ST0, freg is vexMode=0 & byte=0xDB; frow=15 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n fcomi(freg); \n} \n\n:FCOMIP ST0, freg is vexMode=0 & byte=0xDF; frow=15 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n fcomi(freg); \n fpop();\n} \n\n:FUCOMI ST0, freg is vexMode=0 & byte=0xDB; frow=14 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n fcomi(freg); \n} \n\n:FUCOMIP ST0, freg is vexMode=0 & byte=0xDF; frow=14 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n fcomi(freg);\n fpop();\n} \n \ndefine pcodeop fcos;\n:FCOS\t\t\t is vexMode=0 & byte=0xD9; byte=0xFF\t\t\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n ST0 = fcos(ST0); \n}\n \n:FDECSTP\t\t is vexMode=0 & byte=0xD9; byte=0xF6\t\t\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n fdec(); \n FPUStatusWord = FPUStatusWord & 0xfeff; \n C0 = 0; #Clear C0\n}\n\n# Legacy 8087 instructions. Still valid but treated as NOP instructions.\n:FDISI is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE1 {}\n:FNDISI is vexMode=0 & byte=0xDB; byte=0xE1 {}\n:FENI is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE0 {}\n:FNENI is vexMode=0 & byte=0xDB; byte=0xE0 {}\n\n:FDIV m32fp is vexMode=0 & byte=0xD8; reg_opcode=6 ... & m32fp \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f/ float2float(m32fp); \n} \n\n:FDIV m64fp is vexMode=0 & byte=0xDC; reg_opcode=6 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f/ float2float(m64fp); \n} \n\n:FDIV ST0,freg is vexMode=0 & byte=0xD8; frow=15 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f/ freg; \n} \n\n:FDIV freg,ST0 is vexMode=0 & byte=0xDC; frow=15 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = freg f/ ST0; \n} \n\n:FDIVP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = freg f/ ST0;\n fpop();\n} \n\n:FDIVP is vexMode=0 & byte=0xDE; byte=0xF9 \n{ \n FPUInstructionPointer = inst_start;\n ST1 = ST1 f/ ST0; \n fpop();\n} \n\n:FIDIV m32 is vexMode=0 & byte=0xDA; reg_opcode=6 ... & m32 \n{ \n FPUInstructionPointer = inst_start; \n ST0 = ST0 f/ int2float(m32); \n} \n\n:FIDIV m16 is vexMode=0 & byte=0xDE; reg_opcode=6 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f/ int2float(m16); \n} \n \n:FDIVR m32fp is vexMode=0 & byte=0xD8; reg_opcode=7 ... & m32fp \n{ \n FPUInstructionPointer = inst_start;\n ST0 = float2float(m32fp) f/ ST0; \n} \n\n:FDIVR m64fp is vexMode=0 & byte=0xDC; reg_opcode=7 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n ST0 = float2float(m64fp) f/ ST0; \n} \n\n:FDIVR ST0,freg is vexMode=0 & byte=0xD8; frow=15 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = freg f/ ST0; \n} \n\n:FDIVR freg,ST0 is vexMode=0 & byte=0xDC; frow=15 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = ST0 f/ freg; \n} \n\n:FDIVRP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=0 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = ST0 f/ freg; \n fpop();\n} \n\n:FDIVRP is vexMode=0 & byte=0xDE; byte=0xF1 \n{ \n FPUInstructionPointer = inst_start;\n ST1 = ST0 f/ ST1; \n fpop();\n} \n\n:FIDIVR m32 is vexMode=0 & byte=0xDA; reg_opcode=7 ... & m32 \n{\n FPUInstructionPointer = inst_start;\n ST0 = int2float(m32) f/ ST0; \n} \n\n:FIDIVR m16 is vexMode=0 & byte=0xDE; reg_opcode=7 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = int2float(m16) f/ ST0; \n} \n\ndefine pcodeop ffree;\n:FFREE freg is vexMode=0 & byte=0xDD; frow=12 & fpage=0 & freg \n{ \n FPUInstructionPointer = inst_start;\n FPUTagWord = ffree(freg); # Set freg to invalid value\n}\n\n:FFREEP freg is vexMode=0 & byte=0xDF; frow=12 & fpage=0 & freg \n{ \n FPUInstructionPointer = inst_start;\n FPUTagWord = ffree(freg); \n fpop(); # FFREE and pop\n}\n \n:FICOM m16 is vexMode=0 & byte=0xDE; reg_opcode=2 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n local tmp = int2float(m16); \n fcom(tmp); \n} \n\n:FICOM m32 is vexMode=0 & byte=0xDA; reg_opcode=2 ... & m32 \n{ \n FPUInstructionPointer = inst_start;\n local tmp = int2float(m32); \n fcom(tmp);\n} \n\n:FICOMP m16 is vexMode=0 & byte=0xDE; (mod != 0b11 & reg_opcode=3) ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n local tmp = int2float(m16); \n fcom(tmp); \n fpop(); \n} \n\n:FICOMP m32 is vexMode=0 & byte=0xDA; reg_opcode=3 ... & m32 \n{\n FPUInstructionPointer = inst_start;\n local tmp = int2float(m32); \n fcom(tmp); \n fpop(); \n} \n \n:FILD m16 is vexMode=0 & byte=0xDF; reg_opcode=0 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n fdec(); ST0 = int2float(m16); \n} \n\n:FILD m32 is vexMode=0 & byte=0xDB; reg_opcode=0 ... & m32\n{ \n FPUInstructionPointer = inst_start;\n fdec(); \n ST0 = int2float(m32); \n} \n\n:FILD m64 is vexMode=0 & byte=0xDF; reg_opcode=5 ... & m64\n{ \n FPUInstructionPointer = inst_start;\n fdec(); \n ST0 = int2float(m64); \n} \n \n:FINCSTP is vexMode=0 & byte=0xD9; byte=0xF7 \n{ \n FPUInstructionPointer = inst_start;\n finc(); \n} \n\n:FINIT is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE3 \n{\n FPUControlWord = 0x037f; \n FPUStatusWord = 0x0000; \n FPUTagWord = 0xffff; \n FPUDataPointer = 0x00000000; \n FPUInstructionPointer = 0x00000000; \n FPULastInstructionOpcode = 0x0000; \n C0 = 0; \n C1 = 0; \n C2 = 0; \n C3 = 0; \n} \n\n:FNINIT is vexMode=0 & byte=0xDB; byte=0xE3 \n{\n FPUControlWord = 0x037f; \n FPUStatusWord = 0x0000; \n FPUTagWord = 0xffff; \n FPUDataPointer = 0x00000000; \n FPUInstructionPointer = 0x00000000; \n FPULastInstructionOpcode = 0x0000; \n C0 = 0; \n C1 = 0; \n C2 = 0; \n C3 = 0; \n} \n\n:FIST m16 is vexMode=0 & byte=0xDF; (mod != 0b11 & reg_opcode=2) ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n tmp:10 = round(ST0);\n m16 = trunc(tmp); \n} \n\n:FIST m32 is vexMode=0 & byte=0xDB; (mod != 0b11 & reg_opcode=2) ... & m32 \n{ \n FPUInstructionPointer = inst_start;\n tmp:10 = round(ST0); \n m32 = trunc(tmp); \n} \n\n:FISTP m16 is vexMode=0 & byte=0xDF; reg_opcode=3 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n tmp:10 = round(ST0); \n fpop(); \n m16 = trunc(tmp); \n} \n\n:FISTP m32 is vexMode=0 & byte=0xDB; reg_opcode=3 ... & m32\n{ \n FPUInstructionPointer = inst_start;\n tmp:10 = round(ST0);\n fpop();\n m32 = trunc(tmp); \n} \n\n:FISTP m64 is vexMode=0 & byte=0xDF; reg_opcode=7 ... & m64 \n{\n FPUInstructionPointer = inst_start;\n tmp:10 = round(ST0); \n fpop(); \n m64 = trunc(tmp); \n} \n\n:FISTTP m16 is vexMode=0 & byte=0xDF; reg_opcode=1 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n m16 = trunc(ST0); \n fpop();\n} \n\n:FISTTP m32 is vexMode=0 & byte=0xDB; reg_opcode=1 ... & m32 \n{ \n FPUInstructionPointer = inst_start;\n m32 = trunc(ST0); \n fpop(); \n}\n \n:FISTTP m64 is vexMode=0 & byte=0xDD; reg_opcode=1 ... & m64\n{ \n FPUInstructionPointer = inst_start;\n m64 = trunc(ST0); \n fpop(); \n} \n \n:FLD m32fp is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=0) ... & m32fp \n{ \n FPUInstructionPointer = inst_start;\n fdec();\n ST0 = float2float(m32fp); \n} \n\n:FLD m64fp is vexMode=0 & byte=0xDD; reg_opcode=0 ... & m64fp\n{\n FPUInstructionPointer = inst_start;\n fdec(); \n ST0 = float2float(m64fp);\n} \n\n:FLD m80fp is vexMode=0 & byte=0xDB; reg_opcode=5 ... & m80fp\n{\n FPUInstructionPointer = inst_start;\n fpushv(m80fp); \n} \n\n# Be careful that you don't clobber freg during fpushv, need a tmp to hold the value\n:FLD freg is vexMode=0 & byte=0xD9; frow=12 & fpage=0 & freg { tmp:10 = freg; fpushv(tmp); } \n \n:FLD1 is vexMode=0 & byte=0xD9; byte=0xE8 \n{ \n FPUInstructionPointer = inst_start;\n one:4 = 1; \n tmp:10 = int2float(one); \n fpushv(tmp); \n} \n\n:FLDL2T\t\tis vexMode=0 & byte=0xD9; byte=0xE9\n{ \n FPUInstructionPointer = inst_start;\n src:8 = 0x400a934f0979a371; \n tmp:10 = float2float(src); \n fpushv(tmp); \n}\n\n:FLDL2E\t\tis vexMode=0 & byte=0xD9; byte=0xEA\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n src:8 = 0x3ff71547652b82fe;\n tmp:10 = float2float(src); \n fpushv(tmp); \n}\n\n:FLDPI\t\tis vexMode=0 & byte=0xD9; byte=0xEB\t\t\t\n{\n FPUInstructionPointer = inst_start;\n src:8 = 0x400921fb54442d18; \n tmp:10 = float2float(src); \n fpushv(tmp);\n}\n\n:FLDLG2\t\tis vexMode=0 & byte=0xD9; byte=0xEC\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n src:8 = 0x3fd34413509f79ff; \n tmp:10 = float2float(src); \n fpushv(tmp); \n}\n\n:FLDLN2\t\tis vexMode=0 & byte=0xD9; byte=0xED\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n src:8 = 0x3fe62e42fefa39ef;\n tmp:10 = float2float(src); \n fpushv(tmp); \n}\n\n:FLDZ\t\tis vexMode=0 & byte=0xD9; byte=0xEE\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n zero:4 = 0;\n tmp:10 = int2float(zero); \n fpushv(tmp); \n}\n\n:FLDCW m16 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=5) ... & m16 \n{ \n FPUControlWord = m16; \n}\n\ndefine pcodeop fldenv;\n:FLDENV Mem is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=4) ... & Mem\n{\n FPUControlWord = *:2 (Mem);\n FPUStatusWord = *:2 (Mem + 4);\n FPUTagWord = *:2 (Mem + 8);\n FPUDataPointer = *:4 (Mem + 20);\n FPUInstructionPointer = *:4 (Mem + 12);\n FPULastInstructionOpcode = *:2 (Mem + 18);\n}\n\n:FMUL m32fp is vexMode=0 & byte=0xD8; reg_opcode=1 ... & m32fp\n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f* float2float(m32fp); \n} \n\n:FMUL m64fp is vexMode=0 & byte=0xDC; reg_opcode=1 ... & m64fp \n{ \n ST0 = ST0 f* float2float(m64fp); \n FPUInstructionPointer = inst_start;\n} \n\n:FMUL freg is vexMode=0 & byte=0xD8; frow=12 & fpage=1 & freg \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f* freg; \n} \n\n:FMUL freg is vexMode=0 & byte=0xDC; frow=12 & fpage=1 & freg \n{ \n FPUInstructionPointer = inst_start;\n freg = freg f* ST0; \n} \n\n:FMULP freg is vexMode=0 & byte=0xDE; frow=12 & fpage=1 & freg \n{ \n FPUInstructionPointer = inst_start;\n freg = ST0 f* freg; \n fpop(); \n} \n\n:FMULP is vexMode=0 & byte=0xDE; byte=0xC9 \n{ \n FPUInstructionPointer = inst_start;\n ST1 = ST0 f* ST1; \n fpop(); \n} \n\n:FIMUL m32 is vexMode=0 & byte=0xDA; reg_opcode=1 ... & m32 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f* int2float(m32); \n} \n\n:FIMUL m16 is vexMode=0 & byte=0xDE; reg_opcode=1 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = ST0 f* int2float(m16); \n} \n\n:FNOP is vexMode=0 & byte=0xD9; byte=0xD0 \n{ \n FPUInstructionPointer = inst_start;\n}\n\ndefine pcodeop fpatan;\n:FPATAN\t\tis vexMode=0 & byte=0xD9; byte=0xF3\n{\n FPUInstructionPointer = inst_start;\n ST1 = fpatan(ST1, ST0); \n fpop(); \n}\n\n:FPREM is vexMode=0 & byte=0xD9; byte=0xF8 \n{ \n FPUInstructionPointer = inst_start;\n local tmp = ST0 f/ ST1; \n tmp = tmp f* ST1; \n ST0 = ST0 f- tmp; \n}\n\n:FPREM1 is vexMode=0 & byte=0xD9; byte=0xF5 \n{ \n FPUInstructionPointer = inst_start;\n local tmp = ST0 f/ ST1; \n tmp = tmp f* ST1; \n ST0 = ST0 f- tmp; \n}\n\ndefine pcodeop fptan;\n:FPTAN\t\tis vexMode=0 & byte=0xD9; byte=0xF2\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n ST0 = fptan(ST0); \n one:4 = 1;\n tmp:10 = int2float(one);\n fpushv(tmp); \n}\n\n:FRNDINT is vexMode=0 & byte=0xD9; byte=0xFC \n{ \n FPUInstructionPointer = inst_start;\n local tmp = round(ST0);\n ST0 = tmp; \n}\n\n:FRSTOR Mem is vexMode=0 & byte=0xDD; reg_opcode=4 ... & Mem\n{\n FPUControlWord = *:2 (Mem);\n FPUStatusWord = *:2 (Mem + 4);\n FPUTagWord = *:2 (Mem + 8);\n FPUDataPointer = *:4 (Mem + 20);\n FPUInstructionPointer = *:4 (Mem + 12);\n FPULastInstructionOpcode = *:2 (Mem + 18);\n\n ST0 = *:10 (Mem + 28);\n ST1 = *:10 (Mem + 38);\n ST2 = *:10 (Mem + 48);\n ST3 = *:10 (Mem + 58);\n ST4 = *:10 (Mem + 68);\n ST5 = *:10 (Mem + 78);\n ST6 = *:10 (Mem + 88);\n ST7 = *:10 (Mem + 98);\n}\n\n:FSAVE Mem is vexMode=0 & byte=0x9B; byte=0xDD; reg_opcode=6 ... & Mem\n{\n *:2 (Mem) = FPUControlWord;\n *:2 (Mem + 4) = FPUStatusWord;\n *:2 (Mem + 8) = FPUTagWord;\n *:4 (Mem + 20) = FPUDataPointer;\n *:4 (Mem + 12) = FPUInstructionPointer;\n *:2 (Mem + 18) = FPULastInstructionOpcode;\n\n *:10 (Mem + 28) = ST0;\n *:10 (Mem + 38) = ST1;\n *:10 (Mem + 48) = ST2;\n *:10 (Mem + 58) = ST3;\n *:10 (Mem + 68) = ST4;\n *:10 (Mem + 78) = ST5;\n *:10 (Mem + 88) = ST6;\n *:10 (Mem + 98) = ST7;\n\n FPUControlWord = 0x037f;\n FPUStatusWord = 0x0000;\n FPUTagWord = 0xffff;\n FPUDataPointer = 0x00000000;\n FPUInstructionPointer = 0x00000000;\n FPULastInstructionOpcode = 0x0000;\n}\n\n:FNSAVE Mem is vexMode=0 & byte=0xDD; reg_opcode=6 ... & Mem\n{\n *:2 (Mem) = FPUControlWord;\n *:2 (Mem + 4) = FPUStatusWord;\n *:2 (Mem + 8) = FPUTagWord;\n *:4 (Mem + 20) = FPUDataPointer;\n *:4 (Mem + 12) = FPUInstructionPointer;\n *:2 (Mem + 18) = FPULastInstructionOpcode;\n\n *:10 (Mem + 28) = ST0;\n *:10 (Mem + 38) = ST1;\n *:10 (Mem + 48) = ST2;\n *:10 (Mem + 58) = ST3;\n *:10 (Mem + 68) = ST4;\n *:10 (Mem + 78) = ST5;\n *:10 (Mem + 88) = ST6;\n *:10 (Mem + 98) = ST7;\n\n FPUControlWord = 0x037f;\n FPUStatusWord = 0x0000;\n FPUTagWord = 0xffff;\n FPUDataPointer = 0x00000000;\n FPUInstructionPointer = 0x00000000;\n FPULastInstructionOpcode = 0x0000;\n}\n\ndefine pcodeop fscale;\n:FSCALE\t\t is vexMode=0 & byte=0xD9; byte=0xFD\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n ST0 = fscale(ST0, ST1); \n}\n\ndefine pcodeop fsin;\n:FSIN\t\t is vexMode=0 & byte=0xD9; byte=0xFE\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n ST0 = fsin(ST0); \n}\n\n:FSINCOS\t is vexMode=0 & byte=0xD9; byte=0xFB\t\t\t\n{ \n FPUInstructionPointer = inst_start;\n tmp:10 = fcos(ST0); \n ST0 = fsin(ST0); \n fpushv(tmp);\n}\n\n:FSQRT is vexMode=0 & byte=0xD9; byte=0xFA \n{ \n FPUInstructionPointer = inst_start;\n ST0 = sqrt(ST0); \n}\n\n:FST m32fp is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=2) ... & m32fp \n{ \n FPUInstructionPointer = inst_start;\n m32fp = float2float(ST0); \n} \n\n:FST m64fp is vexMode=0 & byte=0xDD; reg_opcode=2 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n m64fp = float2float(ST0); \n} \n\n:FST freg is vexMode=0 & byte=0xDD; frow=13 & fpage=0 & freg \n{ \n FPUInstructionPointer = inst_start;\n freg = ST0; \n} \n\n:FSTP m32fp is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=3) ... & m32fp \n{\n FPUInstructionPointer = inst_start;\n m32fp = float2float(ST0); \n fpop();\n} \n\n:FSTP m64fp is vexMode=0 & byte=0xDD; reg_opcode=3 ... & m64fp \n{ \n FPUInstructionPointer = inst_start;\n m64fp = float2float(ST0); \n fpop();\n} \n\n:FSTP m80fp is vexMode=0 & byte=0xDB; reg_opcode=7 ... & m80fp\n{\n FPUInstructionPointer = inst_start;\n fpopv(m80fp); \n} \n\n:FSTP freg is vexMode=0 & byte=0xDD; frow=13 & fpage=1 & freg \n{\n FPUInstructionPointer = inst_start;\n fpopv(freg); \n} \n\n:FSTCW m16 is vexMode=0 & byte=0x9B; byte=0xD9; (mod != 0b11 & reg_opcode=7) ... & m16\n{\n m16 = FPUControlWord; \n}\n\n:FNSTCW m16 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=7) ... & m16\n{\n m16 = FPUControlWord; \n}\n\n:FSTENV Mem is vexMode=0 & byte=0x9B; byte=0xD9; (mod != 0b11 & reg_opcode=6) ... & Mem\n{\n *:2 (Mem) = FPUControlWord;\n *:2 (Mem + 4) = FPUStatusWord;\n *:2 (Mem + 8) = FPUTagWord;\n *:4 (Mem + 20) = FPUDataPointer;\n *:4 (Mem + 12) = FPUInstructionPointer;\n *:2 (Mem + 18) = FPULastInstructionOpcode;\n}\n\n:FNSTENV Mem is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=6) ... & Mem\n{\n *:2 (Mem) = FPUControlWord;\n *:2 (Mem + 4) = FPUStatusWord;\n *:2 (Mem + 8) = FPUTagWord;\n *:4 (Mem + 20) = FPUDataPointer;\n *:4 (Mem + 12) = FPUInstructionPointer;\n *:2 (Mem + 18) = FPULastInstructionOpcode;\n}\n\n:FSTSW m16 is vexMode=0 & byte=0x9B; byte=0xDD; reg_opcode=7 ... & m16 \n{ \n m16 = FPUStatusWord; \n}\n\n:FSTSW AX is vexMode=0 & byte=0x9B; byte=0xDF; byte=0xE0 & AX \n{ \n AX = FPUStatusWord; \n}\n\n:FNSTSW m16 is vexMode=0 & byte=0xDD; reg_opcode=7 ... & m16 \n{\n m16 = FPUStatusWord; \n}\n\n:FNSTSW AX is vexMode=0 & byte=0xDF; byte=0xE0 & AX \n{\n AX = FPUStatusWord; \n}\n\n:FSUB m32fp is vexMode=0 & byte=0xD8; reg_opcode=4 ... & m32fp \n{\n FPUInstructionPointer = inst_start;\n ST0 = ST0 f- float2float(m32fp); \n} \n\n:FSUB m64fp is vexMode=0 & byte=0xDC; reg_opcode=4 ... & m64fp \n{\n FPUInstructionPointer = inst_start;\n ST0 = ST0 f- float2float(m64fp); \n} \n\n:FSUB ST0,freg is vexMode=0 & byte=0xD8; frow=14 & fpage=0 & freg & ST0 \n{\n FPUInstructionPointer = inst_start;\n ST0 = ST0 f- freg; \n} \n\n:FSUB freg,ST0 is vexMode=0 & byte=0xDC; frow=14 & fpage=1 & freg & ST0 \n{ \n FPUInstructionPointer = inst_start;\n freg = freg f- ST0; \n} \n\n:FSUBP is vexMode=0 & byte=0xDE; byte=0xE9\n{\n FPUInstructionPointer = inst_start;\n ST1 = ST1 f- ST0; \n fpop(); \n} \n\n:FSUBP freg,ST0 is vexMode=0 & byte=0xDE; frow=14 & fpage=1 & freg & ST0\n{\n FPUInstructionPointer = inst_start;\n freg = freg f- ST0; \n fpop(); \n} \n\n:FISUB m32 is vexMode=0 & byte=0xDA; (mod != 0b11 & reg_opcode=4) ... & m32 \n{\n FPUInstructionPointer = inst_start;\n ST0 = ST0 f- int2float(m32); \n} \n\n:FISUB m16 is vexMode=0 & byte=0xDE; reg_opcode=4 ... & m16 \n{\n FPUInstructionPointer = inst_start;\n ST0 = ST0 f- int2float(m16); \n} \n \n:FSUBR m32fp is vexMode=0 & byte=0xD8; reg_opcode=5 ... & m32fp \n{\n FPUInstructionPointer = inst_start;\n ST0 = float2float(m32fp) f- ST0; \n} \n\n:FSUBR m64fp is vexMode=0 & byte=0xDC; reg_opcode=5 ... & m64fp \n{\n FPUInstructionPointer = inst_start;\n ST0 = float2float(m64fp) f- ST0; \n} \n\n:FSUBR ST0,freg is vexMode=0 & byte=0xD8; frow=14 & fpage=1 & freg & ST0 \n{\n FPUInstructionPointer = inst_start;\n ST0 = freg f- ST0; \n} \n\n:FSUBR freg,ST0 is vexMode=0 & byte=0xDC; frow=14 & fpage=0 & freg & ST0\n{ \n FPUInstructionPointer = inst_start;\n freg = ST0 f- freg; \n} \n\n:FSUBRP is vexMode=0 & byte=0xDE; byte=0xE1 \n{\n FPUInstructionPointer = inst_start;\n ST1 = ST0 f- ST1; fpop(); \n} \n\n:FSUBRP freg,ST0 is vexMode=0 & byte=0xDE; frow=14 & fpage=0 & freg & ST0 \n{\n FPUInstructionPointer = inst_start;\n freg = ST0 f- freg; fpop(); \n} \n\n:FISUBR m32 is vexMode=0 & byte=0xDA; reg_opcode=5 ... & m32 \n{\n FPUInstructionPointer = inst_start;\n ST0 = int2float(m32) f- ST0; \n} \n\n:FISUBR m16 is vexMode=0 & byte=0xDE; reg_opcode=5 ... & m16 \n{ \n FPUInstructionPointer = inst_start;\n ST0 = int2float(m16) f- ST0; \n} \n \n:FTST is vexMode=0 & byte=0xD9; byte=0xE4 \n{ \n FPUInstructionPointer = inst_start;\n zero:4 = 0;\n tmp:10 = int2float(zero);\n fcom(tmp); \n} \n \n:FUCOM freg is vexMode=0 & byte=0xDD; frow=14 & fpage=0 & freg \n{ \n FPUInstructionPointer = inst_start;\n fcom(freg); \n} \n\n:FUCOM is vexMode=0 & byte=0xDD; byte=0xE1 \n{ \n fcom(ST1); \n} \n\n:FUCOMP freg is vexMode=0 & byte=0xDD; frow=14 & fpage=1 & freg \n{\n FPUInstructionPointer = inst_start;\n fcom(freg); \n fpop();\n} \n\n:FUCOMP is vexMode=0 & byte=0xDD; byte=0xE9 \n{\n FPUInstructionPointer = inst_start;\n fcom(ST1); \n fpop(); \n} \n\n:FUCOMPP is vexMode=0 & byte=0xDA; byte=0xE9 \n{ \n FPUInstructionPointer = inst_start;\n fcom(ST1); \n fpop();\n fpop(); \n} \n \n:FXAM is vexMode=0 & byte=0xD9; byte=0xE5\n{\n FPUInstructionPointer = inst_start;\n # this is not an exact implementation, but gets the sign and zero tests right\n izero:4 = 0;\n fzero:10 = int2float(izero);\n \n # did not know how test for infinity or empty\n C0 = nan(ST0);\n \n # sign of ST0\n C1 = ( ST0 f< fzero );\n\n # assume normal if not zero \n C2 = ( ST0 f!= fzero );\n\n # equal to zero \n C3 = ( ST0 f== fzero );\n \n FPUStatusWord = (zext(C0)<<8) | (zext(C1)<<9) | (zext(C2)<<10) | (zext(C3)<<14);\n}\n \n:FXCH freg is vexMode=0 & byte=0xD9; frow=12 & fpage=1 & freg \n{ \n FPUInstructionPointer = inst_start;\n local tmp = ST0; \n ST0 = freg; \n freg = tmp; \n} \n\n:FXCH is vexMode=0 & byte=0xD9; byte=0xC9 \n{ \n FPUInstructionPointer = inst_start;\n local tmp = ST0;\n ST0 = ST1;\n ST1 = tmp; \n} \n\n# fxsave and fxrstor\ndefine pcodeop _fxsave;\ndefine pcodeop _fxrstor;\n@ifdef IA64\ndefine pcodeop _fxsave64;\ndefine pcodeop _fxrstor64;\n@endif\n\n# this saves the FPU state into 512 bytes of memory\n:FXSAVE Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem\n{\n _fxsave(Mem);\n}\n\n:FXRSTOR Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem\n{\n _fxrstor(Mem);\n}\n\n@ifdef IA64\n# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode\n:FXSAVE Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem\n{\n _fxsave(Mem);\n}\n\n:FXSAVE64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem\n{\n _fxsave64(Mem);\n}\n\n:FXRSTOR Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem\n{\n _fxrstor(Mem);\n}\n\n:FXRSTOR64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem\n{\n _fxrstor64(Mem);\n}\n@endif\n\ndefine pcodeop extract_significand;\ndefine pcodeop extract_exponent;\n:FXTRACT is vexMode=0 & byte=0xD9; byte=0xF4 \n{ \n FPUInstructionPointer = inst_start;\n significand:10 = extract_significand(ST0);\n exponent:10 = extract_exponent(ST0);\n ST0 = exponent;\n fpushv(significand);\n}\n\n:FYL2X is vexMode=0 & byte=0xD9; byte=0xF1 \n{ \n FPUInstructionPointer = inst_start;\n local log2st0 = ST0; \n ST1 = ST1 f* log2st0; \n fpop();\n}\n:FYL2XP1 is vexMode=0 & byte=0xD9; byte=0xF9 \n{ \n FPUInstructionPointer = inst_start;\n one:4 = 1;\n tmp:10 = int2float(one);\n log2st0:10 = ST0 f+ tmp;\n ST1 = ST1 f* log2st0; \n fpop(); \n}\n\n#\n# MMX instructions\n#\n\n:ADDPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x58; XmmReg ... & m128\n{\n XmmReg[0,64] = XmmReg[0,64] f+ m128[0,64];\n XmmReg[64,64] = XmmReg[64,64] f+ m128[64,64];\n}\n\n:ADDPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f+ XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] f+ XmmReg2[64,64];\n}\n\n:ADDPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x58; m128 & XmmReg ...\n{\n local m:16 = m128;\t# Guarantee value is in a fixed location\n XmmReg[0,32] = XmmReg[0,32] f+ m[0,32];\n XmmReg[32,32] = XmmReg[32,32] f+ m[32,32];\n XmmReg[64,32] = XmmReg[64,32] f+ m[64,32];\n XmmReg[96,32] = XmmReg[96,32] f+ m[96,32];\n}\n\n:ADDPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f+ XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] f+ XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] f+ XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] f+ XmmReg2[96,32];\n}\n\n:ADDSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x58; m64 & XmmReg ...\n{\n XmmReg[0,64] = XmmReg[0,64] f+ m64;\n}\n\n:ADDSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f+ XmmReg2[0,64];\n}\n\n:ADDSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x58; m32 & XmmReg ...\n{\n XmmReg[0,32] = XmmReg[0,32] f+ m32;\n}\n\n:ADDSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f+ XmmReg2[0,32];\n}\n\n:ADDSUBPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD0; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] f- m[0,64];\n XmmReg[64,64] = XmmReg[64,64] f+ m[64,64];\n}\n\n:ADDSUBPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD0; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] f+ XmmReg2[64,64];\n}\n\n:ADDSUBPS XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xD0; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] f- m[0,32];\n XmmReg[32,32] = XmmReg[32,32] f+ m[32,32];\n XmmReg[64,32] = XmmReg[64,32] f- m[64,32];\n XmmReg[96,32] = XmmReg[96,32] f+ m[96,32];\n}\n\n:ADDSUBPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xD0; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] f+ XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] f- XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] f+ XmmReg2[96,32];\n}\n\n# special FLOATING POINT bitwise AND\n:ANDPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x54; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] & m[0,64];\n XmmReg[64,64] = XmmReg[64,64] & m[64,64];\n}\n\n# special FLOATING POINT bitwise AND\n:ANDPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x54; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] & XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] & XmmReg2[64,64];\n}\n\n# special FLOATING POINT bitwise AND\n:ANDPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x54; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] & m[0,32];\n XmmReg[32,32] = XmmReg[32,32] & m[32,32];\n XmmReg[64,32] = XmmReg[64,32] & m[64,32];\n XmmReg[96,32] = XmmReg[96,32] & m[96,32];\n}\n\n# special FLOATING POINT bitwise AND\n:ANDPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x54; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] & XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] & XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] & XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] & XmmReg2[96,32];\n}\n\n# special FLOATING POINT bitwise AND NOT\n:ANDNPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x55; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = ~XmmReg[0,64] & m[0,64];\n XmmReg[64,64] = ~XmmReg[64,64] & m[64,64];\n}\n\n:ANDNPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x55; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = ~XmmReg1[0,64] & XmmReg2[0,64];\n XmmReg1[64,64] = ~XmmReg1[64,64] & XmmReg2[64,64];\n}\n\n# special FLOATING POINT bitwise AND NOT\n:ANDNPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x55; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = ~XmmReg[0,32] & m[0,32];\n XmmReg[32,32] = ~XmmReg[32,32] & m[32,32];\n XmmReg[64,32] = ~XmmReg[64,32] & m[64,32];\n XmmReg[96,32] = ~XmmReg[96,32] & m[96,32];\n}\n\n:ANDNPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x55; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = ~XmmReg1[0,32] & XmmReg2[0,32];\n XmmReg1[32,32] = ~XmmReg1[32,32] & XmmReg2[32,32];\n XmmReg1[64,32] = ~XmmReg1[64,32] & XmmReg2[64,32];\n XmmReg1[96,32] = ~XmmReg1[96,32] & XmmReg2[96,32];\n}\n\n# predicate mnemonics for \"CMP...PD\" opcode\nXmmCondPD: \"EQ\" is imm8=0 { \n\txmmTmp1_Qa = zext( xmmTmp1_Qa f== xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( xmmTmp1_Qb f== xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"LT\" is imm8=1 { \n\txmmTmp1_Qa = zext( xmmTmp1_Qa f< xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( xmmTmp1_Qb f< xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"LE\" is imm8=2 {\n xmmTmp1_Qa = zext( xmmTmp1_Qa f<= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( xmmTmp1_Qb f<= xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"UNORD\" is imm8=3 {\n xmmTmp1_Qa = zext( nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( nan(xmmTmp1_Qb) || nan(xmmTmp2_Qb) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"NEQ\" is imm8=4 {\n xmmTmp1_Qa = zext( xmmTmp1_Qa f!= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( xmmTmp1_Qb f!= xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"NLT\" is imm8=5 {\n xmmTmp1_Qa = zext( !(xmmTmp1_Qa f< xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( !(xmmTmp1_Qb f< xmmTmp2_Qb) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"NLE\" is imm8=6 {\n xmmTmp1_Qa = zext( !(xmmTmp1_Qa f<= xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( !(xmmTmp1_Qb f<= xmmTmp2_Qb) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondPD: \"ORD\" is imm8=7 {\n xmmTmp1_Qa = zext( !(nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa)) ) * 0xFFFFFFFFFFFFFFFF; \n xmmTmp1_Qb = zext( !(nan(xmmTmp1_Qb) || nan(xmmTmp2_Qb)) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\ndefine pcodeop cmppd;\nXmmCondPD:\t is imm8 {\n\txmmTmp1_Qa = cmppd(xmmTmp1_Qa, xmmTmp2_Qa, imm8:1);\n\txmmTmp1_Qb = cmppd(xmmTmp1_Qb, xmmTmp2_Qb, imm8:1);\n}\n\n# immediate operand for \"CMP...PD\" opcode\n# note: normally blank, \"imm8\" emits for all out of range cases\nCMPPD_OPERAND: is imm8<8 { }\nCMPPD_OPERAND: \", \"^imm8 is imm8 { }\n\n:CMP^XmmCondPD^\"PD\" XmmReg,m128^CMPPD_OPERAND is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC2; (m128 & XmmReg ...); XmmCondPD & CMPPD_OPERAND\n{\n local m:16 = m128;\n\txmmTmp1_Qa = XmmReg[0,64];\n\txmmTmp1_Qb = XmmReg[64,64];\n\n\txmmTmp2_Qa = m[0,64];\n\txmmTmp2_Qb = m[64,64];\n\n\tbuild XmmCondPD;\n\t\n\tXmmReg[0,64] = xmmTmp1_Qa;\n\tXmmReg[64,64] = xmmTmp1_Qb;\n}\n\n:CMP^XmmCondPD^\"PD\" XmmReg1,XmmReg2^CMPPD_OPERAND is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondPD & CMPPD_OPERAND \n{\n\txmmTmp1_Qa = XmmReg1[0,64];\n\txmmTmp1_Qb = XmmReg1[64,64];\n\t\n\txmmTmp2_Qa = XmmReg2[0,64];\n\txmmTmp2_Qb = XmmReg2[64,64];\n\t\n\tbuild XmmCondPD;\n\t\n\tXmmReg1[0,64] = xmmTmp1_Qa;\n\tXmmReg1[64,64] = xmmTmp1_Qb;\n}\n\n\n# predicate mnemonics for \"CMP...PS\" opcode\nXmmCondPS: \"EQ\" is imm8=0 { \n\txmmTmp1_Da = zext( xmmTmp1_Da f== xmmTmp2_Da ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( xmmTmp1_Db f== xmmTmp2_Db ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( xmmTmp1_Dc f== xmmTmp2_Dc ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( xmmTmp1_Dd f== xmmTmp2_Dd ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"LT\" is imm8=1 { \n\txmmTmp1_Da = zext( xmmTmp1_Da f< xmmTmp2_Da ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( xmmTmp1_Db f< xmmTmp2_Db ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( xmmTmp1_Dc f< xmmTmp2_Dc ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( xmmTmp1_Dd f< xmmTmp2_Dd ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"LE\" is imm8=2 {\n xmmTmp1_Da = zext( xmmTmp1_Da f<= xmmTmp2_Da ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( xmmTmp1_Db f<= xmmTmp2_Db ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( xmmTmp1_Dc f<= xmmTmp2_Dc ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( xmmTmp1_Dd f<= xmmTmp2_Dd ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"UNORD\" is imm8=3 {\n xmmTmp1_Da = zext( nan(xmmTmp1_Da) || nan(xmmTmp2_Da) ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( nan(xmmTmp1_Db) || nan(xmmTmp2_Db) ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( nan(xmmTmp1_Dc) || nan(xmmTmp2_Dc) ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( nan(xmmTmp1_Dd) || nan(xmmTmp2_Dd) ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"NEQ\" is imm8=4 {\n xmmTmp1_Da = zext( xmmTmp1_Da f!= xmmTmp2_Da ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( xmmTmp1_Db f!= xmmTmp2_Db ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( xmmTmp1_Dc f!= xmmTmp2_Dc ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( xmmTmp1_Dd f!= xmmTmp2_Dd ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"NLT\" is imm8=5 {\n xmmTmp1_Da = zext( !(xmmTmp1_Da f< xmmTmp2_Da) ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( !(xmmTmp1_Db f< xmmTmp2_Db) ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( !(xmmTmp1_Dc f< xmmTmp2_Dc) ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( !(xmmTmp1_Dd f< xmmTmp2_Dd) ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"NLE\" is imm8=6 {\n xmmTmp1_Da = zext( !(xmmTmp1_Da f<= xmmTmp2_Da) ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( !(xmmTmp1_Db f<= xmmTmp2_Db) ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( !(xmmTmp1_Dc f<= xmmTmp2_Dc) ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( !(xmmTmp1_Dd f<= xmmTmp2_Dd) ) * 0xFFFFFFFF;\n}\n\nXmmCondPS: \"ORD\" is imm8=7 {\n xmmTmp1_Da = zext( !(nan(xmmTmp1_Da) || nan(xmmTmp2_Da)) ) * 0xFFFFFFFF; \n xmmTmp1_Db = zext( !(nan(xmmTmp1_Db) || nan(xmmTmp2_Db)) ) * 0xFFFFFFFF; \n xmmTmp1_Dc = zext( !(nan(xmmTmp1_Dc) || nan(xmmTmp2_Dc)) ) * 0xFFFFFFFF; \n xmmTmp1_Dd = zext( !(nan(xmmTmp1_Dd) || nan(xmmTmp2_Dd)) ) * 0xFFFFFFFF;\n}\n\ndefine pcodeop cmpps;\nXmmCondPS:\t is imm8 {\n\txmmTmp1_Da = cmpps(xmmTmp1_Da, xmmTmp2_Da, imm8:1);\n\txmmTmp1_Db = cmpps(xmmTmp1_Db, xmmTmp2_Db, imm8:1);\n\txmmTmp1_Dc = cmpps(xmmTmp1_Dc, xmmTmp2_Dc, imm8:1);\n\txmmTmp1_Dd = cmpps(xmmTmp1_Dd, xmmTmp2_Dd, imm8:1);\n}\n\n# immediate operand for \"CMP...PS\" opcode\n# note: normally blank, \"imm8\" emits for all out of range cases\nCMPPS_OPERAND: is imm8<8 { }\nCMPPS_OPERAND: \", \"^imm8 is imm8 { }\n\n:CMP^XmmCondPS^\"PS\" XmmReg,m128^CMPPS_OPERAND is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC2; (m128 & XmmReg ...); XmmCondPS & CMPPS_OPERAND\n{\n local m:16 = m128;\n\txmmTmp1_Da = XmmReg[0,32];\n\txmmTmp1_Db = XmmReg[32,32];\n\txmmTmp1_Dc = XmmReg[64,32];\n\txmmTmp1_Dd = XmmReg[96,32];\n\n\txmmTmp2_Da = m[0,32];\n\txmmTmp2_Db = m[32,32];\n\txmmTmp2_Dc = m[64,32];\n\txmmTmp2_Dd = m[96,32];\n\n\tbuild XmmCondPS;\n\t\n\tXmmReg[0,32] = xmmTmp1_Da;\n\tXmmReg[32,32] = xmmTmp1_Db;\n\tXmmReg[64,32] = xmmTmp1_Dc;\n\tXmmReg[96,32] = xmmTmp1_Dd;\n}\n\n:CMP^XmmCondPS^\"PS\" XmmReg1,XmmReg2^CMPPS_OPERAND is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondPS & CMPPS_OPERAND \n{\n\txmmTmp1_Da = XmmReg1[0,32];\n\txmmTmp1_Db = XmmReg1[32,32];\n\txmmTmp1_Dc = XmmReg1[64,32];\n\txmmTmp1_Dd = XmmReg1[96,32];\n\t\n\txmmTmp2_Da = XmmReg2[0,32];\n\txmmTmp2_Db = XmmReg2[32,32];\n\txmmTmp2_Dc = XmmReg2[64,32];\n\txmmTmp2_Dd = XmmReg2[96,32];\n\t\n\tbuild XmmCondPS;\n\t\n\tXmmReg1[0,32] = xmmTmp1_Da;\n\tXmmReg1[32,32] = xmmTmp1_Db;\n\tXmmReg1[64,32] = xmmTmp1_Dc;\n\tXmmReg1[96,32] = xmmTmp1_Dd;\n}\n\n\n# predicate mnemonics for \"CMP...SD\" opcode\nXmmCondSD: \"EQ\" is imm8=0 { \n\txmmTmp1_Qa = zext( xmmTmp1_Qa f== xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"LT\" is imm8=1 { \n\txmmTmp1_Qa = zext( xmmTmp1_Qa f< xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"LE\" is imm8=2 {\n xmmTmp1_Qa = zext( xmmTmp1_Qa f<= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"UNORD\" is imm8=3 {\n xmmTmp1_Qa = zext( nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"NEQ\" is imm8=4 {\n xmmTmp1_Qa = zext( xmmTmp1_Qa f!= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"NLT\" is imm8=5 {\n xmmTmp1_Qa = zext( !(xmmTmp1_Qa f< xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"NLE\" is imm8=6 {\n xmmTmp1_Qa = zext( !(xmmTmp1_Qa f<= xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\nXmmCondSD: \"ORD\" is imm8=7 {\n xmmTmp1_Qa = zext( !(nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa)) ) * 0xFFFFFFFFFFFFFFFF; \n}\n\n\ndefine pcodeop cmpsd;\nXmmCondSD:\t is imm8 {\n\txmmTmp1_Qa = cmpsd(xmmTmp1_Qa, xmmTmp2_Qa, imm8:1);\n}\n\n# immediate operand for \"CMP...SD\" opcode\n# note: normally blank, \"imm8\" emits for all out of range cases\nCMPSD_OPERAND: is imm8<8 { }\nCMPSD_OPERAND: \", \"^imm8 is imm8 { }\n\n:CMP^XmmCondSD^\"SD\" XmmReg, m64^CMPSD_OPERAND is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xC2; (m64 & XmmReg ...); XmmCondSD & CMPSD_OPERAND\n{ \n\txmmTmp1_Qa = XmmReg[0,64];\n\txmmTmp2_Qa = m64;\n\tbuild XmmCondSD;\n\tXmmReg[0,64] = xmmTmp1_Qa;\n}\n\n:CMP^XmmCondSD^\"SD\" XmmReg1, XmmReg2^CMPSD_OPERAND is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondSD & CMPSD_OPERAND\n{ \n\txmmTmp1_Qa = XmmReg1[0,64];\n\txmmTmp2_Qa = XmmReg2[0,64];\n\tbuild XmmCondSD;\n\tXmmReg1[0,64] = xmmTmp1_Qa;\n}\n\n\n# predicate mnemonics for \"CMP...SS\" opcode\nXmmCondSS: \"EQ\" is imm8=0 { \n\txmmTmp1_Da = zext( xmmTmp1_Da f== xmmTmp2_Da ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"LT\" is imm8=1 { \n\txmmTmp1_Da = zext( xmmTmp1_Da f< xmmTmp2_Da ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"LE\" is imm8=2 {\n xmmTmp1_Da = zext( xmmTmp1_Da f<= xmmTmp2_Da ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"UNORD\" is imm8=3 {\n xmmTmp1_Da = zext( nan(xmmTmp1_Da) || nan(xmmTmp2_Da) ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"NEQ\" is imm8=4 {\n xmmTmp1_Da = zext( xmmTmp1_Da f!= xmmTmp2_Da ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"NLT\" is imm8=5 {\n xmmTmp1_Da = zext( !(xmmTmp1_Da f< xmmTmp2_Da) ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"NLE\" is imm8=6 {\n xmmTmp1_Da = zext( !(xmmTmp1_Da f<= xmmTmp2_Da) ) * 0xFFFFFFFF; \n}\n\nXmmCondSS: \"ORD\" is imm8=7 {\n xmmTmp1_Da = zext( !(nan(xmmTmp1_Da) || nan(xmmTmp2_Da)) ) * 0xFFFFFFFF; \n}\n\n\ndefine pcodeop cmpss;\nXmmCondSS:\t is imm8 {\n\txmmTmp1_Da = cmpss(xmmTmp1_Da, xmmTmp2_Da, imm8:1);\n}\n\n# immediate operand for \"CMP...SS\" opcode\n# note: normally blank, \"imm8\" emits for all out of range cases\nCMPSS_OPERAND: is imm8<8 { }\nCMPSS_OPERAND: \", \"^imm8 is imm8 { }\n\n:CMP^XmmCondSS^\"SS\" XmmReg, m32^CMPSS_OPERAND is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xC2; (m32 & XmmReg ...); XmmCondSS & CMPSS_OPERAND\n{ \n\txmmTmp1_Da = XmmReg[0,32];\n\txmmTmp2_Da = m32;\n\tbuild XmmCondSS;\n\tXmmReg[0,32] = xmmTmp1_Da;\n}\n\n:CMP^XmmCondSS^\"SS\" XmmReg1, XmmReg2^CMPSS_OPERAND is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondSS & CMPSS_OPERAND\n{ \n\txmmTmp1_Da = XmmReg1[0,32];\n\txmmTmp2_Da = XmmReg2[0,32];\n\tbuild XmmCondSS;\n\tXmmReg1[0,32] = xmmTmp1_Da;\n}\n\n\n:COMISD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2F; m64 & XmmReg ...\n{\n fucompe(XmmReg[0,64], m64);\n}\n \n:COMISD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2F; xmmmod=3 & XmmReg1 & XmmReg2\n{\n fucompe(XmmReg1[0,64], XmmReg2[0,64]);\n}\n\n:COMISS XmmReg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2F; m32 & XmmReg ...\n{\n fucompe(XmmReg[0,32], m32);\n}\n\n:COMISS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2F; xmmmod=3 & XmmReg1 & XmmReg2\n{\n fucompe(XmmReg1[0,32], XmmReg2[0,32]);\n}\n\n:CVTDQ2PD XmmReg, m64 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xE6; m64 & XmmReg ...\n{\n local m:8 = m64;\n XmmReg[0,64] = int2float( m[0,32] );\n XmmReg[64,64] = int2float( m[32,32] );\n}\n\n:CVTDQ2PD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xE6; xmmmod=3 & XmmReg1 & XmmReg2\n{\n local tmp:8 = XmmReg2[0,64];\n XmmReg1[0,64] = int2float( tmp[0,32] );\n XmmReg1[64,64] = int2float( tmp[32,32] );\n}\n\n:CVTDQ2PS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5B; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = int2float( m[0,32] );\n XmmReg[32,32] = int2float( m[32,32] );\n XmmReg[64,32] = int2float( m[64,32] );\n XmmReg[96,32] = int2float( m[96,32] );\n}\n\n:CVTDQ2PS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5B; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = int2float( XmmReg2[0,32] );\n XmmReg1[32,32] = int2float( XmmReg2[32,32] );\n XmmReg1[64,32] = int2float( XmmReg2[64,32] );\n XmmReg1[96,32] = int2float( XmmReg2[96,32] );\n}\n\n:CVTPD2DQ XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xE6; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = trunc( m[0,64] );\n XmmReg[32,32] = trunc( m[64,64] );\n XmmReg[64,32] = 0;\n XmmReg[96,32] = 0;\n}\n\n:CVTPD2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xE6; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = trunc( XmmReg2[0,64] );\n XmmReg1[32,32] = trunc( XmmReg2[64,64] );\n XmmReg1[64,32] = 0;\n XmmReg1[96,32] = 0;\n}\n\n:CVTPD2PI mmxreg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2D; mmxreg ... & m128\n{\n local m:16 = m128;\n mmxreg[0,32] = trunc( m[0,64] );\n mmxreg[32,32] = trunc( m[64,64] );\n}\n\n:CVTPD2PI mmxreg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2D; xmmmod=3 & mmxreg1 & XmmReg2\n{\n mmxreg1[0,32] = trunc( XmmReg2[0,64] );\n mmxreg1[32,32] = trunc( XmmReg2[64,64] );\n}\n\n:CVTPD2PS XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5A; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = float2float( m[0,64] );\n XmmReg[32,32] = float2float( m[64,64] );\n XmmReg[64,32] = 0;\n XmmReg[96,32] = 0;\n}\n\n:CVTPD2PS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = float2float( XmmReg2[0,64] );\n XmmReg1[32,32] = float2float( XmmReg2[64,64] );\n XmmReg1[64,32] = 0;\n XmmReg1[96,32] = 0;\n}\n\n:CVTPI2PD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2A; m64 & XmmReg ...\n{\n local m:8 = m64;\n XmmReg[0,64] = int2float(m[0,32]);\n XmmReg[64,64] = int2float(m[32,32]);\n}\n\n:CVTPI2PD XmmReg1, mmxreg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2A; xmmmod=3 & XmmReg1 & mmxreg2\n{\n XmmReg1[0,64] = int2float(mmxreg2[0,32]);\n XmmReg1[64,64] = int2float(mmxreg2[32,32]);\n}\n\n:CVTPI2PS XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2A; m64 & XmmReg ...\n{\n local m:8 = m64;\n XmmReg[0,32] = int2float(m[0,32]);\n XmmReg[32,32] = int2float(m[32,32]);\n}\n\n:CVTPI2PS XmmReg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2A; xmmmod=3 & XmmReg1 & mmxreg2\n{\n XmmReg1[0,32] = int2float(mmxreg2[0,32]);\n XmmReg1[32,32] = int2float(mmxreg2[32,32]);\n}\n\n:CVTPS2DQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5B; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = trunc( m[0,32] );\n XmmReg[32,32] = trunc( m[32,32] );\n XmmReg[64,32] = trunc( m[64,32] );\n XmmReg[96,32] = trunc( m[96,32] );\n}\n\n:CVTPS2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5B; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = trunc( XmmReg2[0,32] );\n XmmReg1[32,32] = trunc( XmmReg2[32,32] );\n XmmReg1[64,32] = trunc( XmmReg2[64,32] );\n XmmReg1[96,32] = trunc( XmmReg2[96,32] );\n}\n\n:CVTPS2PD XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5A; m64 & XmmReg ...\n{\n local m:8 = m64;\n XmmReg[0,64] = float2float( m[0,32] );\n XmmReg[64,64] = float2float( m[32,32] );\n}\n\n:CVTPS2PD XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2\n{\n local tmp:8 = XmmReg2[0,64];\n XmmReg1[0,64] = float2float( tmp[0,32] );\n XmmReg1[64,64] = float2float( tmp[32,32] );\n}\n\n:CVTPS2PI mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2D; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,32] = round(m[0,32]);\n mmxreg[32,32] = round(m[32,32]);\n FPUTagWord = 0x0000; \n}\n\n:CVTPS2PI mmxreg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2D; xmmmod=3 & mmxreg1 & XmmReg2\n{\n mmxreg1[0,32] = round(XmmReg2[0,32]);\n mmxreg1[32,32] = round(XmmReg2[32,32]);\n FPUTagWord = 0x0000; \n}\n\n:CVTSD2SI Reg32, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2D; (Reg32 & check_Reg32_dest) ... & m64\n{\n Reg32 = trunc(round(m64));\n build check_Reg32_dest;\n}\n\n:CVTSD2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg32 & check_Reg32_dest & XmmReg2\n{\n Reg32 = trunc(round(XmmReg2[0,64]));\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:CVTSD2SI Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2D; Reg64 ... & m64\n{\n Reg64 = trunc(round(m64));\n}\n\n:CVTSD2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg64 & XmmReg2\n{\n Reg64 = trunc(round(XmmReg2[0,64]));\n}\n@endif\n\n:CVTSD2SS XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5A; m64 & XmmReg ...\n{\n XmmReg[0,32] = float2float(m64);\n}\n\n:CVTSD2SS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = float2float(XmmReg2[0,64]);\n}\n\n:CVTSI2SD XmmReg, rm32 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2A; rm32 & XmmReg ...\n{\n XmmReg[0,64] = int2float(rm32);\n}\n\n@ifdef IA64\n:CVTSI2SD XmmReg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2A; rm64 & XmmReg ...\n{\n XmmReg[0,64] = int2float(rm64);\n}\n@endif\n\n:CVTSI2SS XmmReg, rm32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2A; rm32 & XmmReg ...\n{\n XmmReg[0,32] = int2float(rm32);\n}\n\n@ifdef IA64\n:CVTSI2SS XmmReg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2A; rm64 & XmmReg ...\n{\n XmmReg[0,32] = int2float(rm64);\n}\n@endif\n\n:CVTSS2SD XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5A; m32 & XmmReg ...\n{\n XmmReg[0,64] = float2float(m32);\n}\n\n:CVTSS2SD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = float2float(XmmReg2[0,32]);\n}\n\n:CVTSS2SI Reg32, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2D; (Reg32 & check_Reg32_dest) ... & m32\n{\n Reg32 = trunc(round(m32));\n build check_Reg32_dest;\n}\n\n:CVTSS2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg32 & check_Reg32_dest & XmmReg2\n{\n Reg32 = trunc(round(XmmReg2[0,32]));\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:CVTSS2SI Reg64, m32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2D; Reg64 ... & m32\n{\n Reg64 = trunc(round(m32));\n}\n\n:CVTSS2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg64 & XmmReg2\n{\n Reg64 = trunc(round(XmmReg2[0,32]));\n}\n@endif\n \n:CVTTPD2PI mmxreg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2C; mmxreg ... & m128\n{\n local m:16 = m128;\n mmxreg[0,32] = trunc(m[0,64]);\n mmxreg[32,32] = trunc(m[64,64]);\n FPUTagWord = 0x0000; \n}\n\n:CVTTPD2PI mmxreg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2C; xmmmod=3 & mmxreg1 & XmmReg2\n{\n mmxreg1[0,32] = trunc(XmmReg2[0,64]);\n mmxreg1[32,32] = trunc(XmmReg2[64,64]);\n FPUTagWord = 0x0000; \n}\n\n:CVTTPD2DQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE6; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = trunc(m[0,64]);\n XmmReg[32,32] = trunc(m[64,64]);\n XmmReg[64,32] = 0;\n XmmReg[96,32] = 0;\n}\n\n:CVTTPD2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE6; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = trunc(XmmReg2[0,64]);\n XmmReg1[32,32] = trunc(XmmReg2[64,64]);\n XmmReg1[64,32] = 0;\n XmmReg1[96,32] = 0;\n}\n\n:CVTTPS2DQ XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5B; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = trunc(m[0,32]);\n XmmReg[32,32] = trunc(m[32,32]);\n XmmReg[64,32] = trunc(m[64,32]);\n XmmReg[96,32] = trunc(m[96,32]);\n}\n\n:CVTTPS2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5B; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = trunc(XmmReg2[0,32]);\n XmmReg1[32,32] = trunc(XmmReg2[32,32]);\n XmmReg1[64,32] = trunc(XmmReg2[64,32]);\n XmmReg1[96,32] = trunc(XmmReg2[96,32]);\n}\n\n:CVTTPS2PI mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2C; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,32] = trunc(m[0,32]);\n mmxreg[32,32] = trunc(m[32,32]);\n FPUTagWord = 0x0000; \n}\n\n:CVTTPS2PI mmxreg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2C; xmmmod=3 & mmxreg1 & XmmReg2\n{\n mmxreg1[0,32] = trunc(XmmReg2[0,32]);\n mmxreg1[32,32] = trunc(XmmReg2[32,32]);\n FPUTagWord = 0x0000; \n}\n\n:CVTTSD2SI Reg32, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2C; (Reg32 & check_Reg32_dest) ... & m64\n{\n Reg32 = trunc(m64);\n build check_Reg32_dest;\n}\n\n:CVTTSD2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg32 & check_Reg32_dest & XmmReg2\n{\n Reg32 = trunc(XmmReg2[0,64]);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:CVTTSD2SI Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2C; Reg64 ... & m64\n{\n Reg64 = trunc(m64);\n}\n\n:CVTTSD2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg64 & XmmReg2\n{\n Reg64 = trunc(XmmReg2[0,64]);\n}\n@endif\n \n:CVTTSS2SI Reg32, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2C; (Reg32 & check_Reg32_dest) ... & m32\n{\n Reg32 = trunc(m32);\n build check_Reg32_dest;\n}\n\n:CVTTSS2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg32 & check_Reg32_dest & XmmReg2\n{\n Reg32 = trunc(XmmReg2[0,32]);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:CVTTSS2SI Reg64, m32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2C; Reg64 ... & m32\n{\n Reg64 = trunc(m32);\n}\n\n:CVTTSS2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg64 & XmmReg2\n{\n Reg64 = trunc(XmmReg2[0,32]);\n}\n@endif\n\ndefine pcodeop divpd;\n:DIVPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5E; XmmReg ... & m128 { XmmReg = divpd(XmmReg, m128); }\n:DIVPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = divpd(XmmReg1, XmmReg2); }\n\ndefine pcodeop divps;\n:DIVPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5E; XmmReg ... & m128 { XmmReg = divps(XmmReg, m128); }\n:DIVPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = divps(XmmReg1, XmmReg2); }\n \n:DIVSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5E; m64 & XmmReg ...\n{\n XmmReg[0,64] = XmmReg[0,64] f/ m64;\n}\n\n:DIVSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f/ XmmReg2[0,64];\n}\n\n:DIVSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5E; m32 & XmmReg ...\n{\n XmmReg[0,32] = XmmReg[0,32] f/ m32;\n}\n\n:DIVSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f/ XmmReg2[0,32];\n}\n\n:EMMS is vexMode=0 & byte=0x0F; byte=0x77 { FPUTagWord = 0xFFFF; }\n\n:HADDPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7C; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] f+ XmmReg[64,64];\n XmmReg[64,64] = m[0,64] f+ m[64,64];\n}\n\n:HADDPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7C; xmmmod=3 & XmmReg1 & XmmReg2\n{\n local tmp:16 = XmmReg2;\n XmmReg1[0,64] = XmmReg1[0,64] f+ XmmReg1[64,64];\n XmmReg1[64,64] = tmp[0,64] f+ tmp[64,64];\n}\n\n:HADDPS XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7C; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] f+ XmmReg[32,32];\n XmmReg[32,32] = XmmReg[64,32] f+ XmmReg[96,32];\n XmmReg[64,32] = m[0,32] f+ m[32,32];\n XmmReg[96,32] = m[64,32] f+ m[96,32];\n}\n\n:HADDPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7C; xmmmod=3 & XmmReg1 & XmmReg2\n{\n local tmp:16 = XmmReg2;\n XmmReg1[0,32] = XmmReg1[0,32] f+ XmmReg1[32,32];\n XmmReg1[32,32] = XmmReg1[64,32] f+ XmmReg1[96,32];\n XmmReg1[64,32] = tmp[0,32] f+ tmp[32,32];\n XmmReg1[96,32] = tmp[64,32] f+ tmp[96,32];\n}\n\n:HSUBPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7D; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] f- XmmReg[64,64];\n XmmReg[64,64] = m[0,64] f- m[64,64];\n}\n\n:HSUBPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7D; xmmmod=3 & XmmReg1 & XmmReg2\n{\n local tmp:16 = XmmReg2;\n XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg1[64,64];\n XmmReg1[64,64] = tmp[0,64] f- tmp[64,64];\n}\n\n:HSUBPS XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7D; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] f- XmmReg[32,32];\n XmmReg[32,32] = XmmReg[64,32] f- XmmReg[96,32];\n XmmReg[64,32] = m[0,32] f- m[32,32];\n XmmReg[96,32] = m[64,32] f- m[96,32];\n}\n\n:HSUBPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7D; xmmmod=3 & XmmReg1 & XmmReg2\n{\n local tmp:16 = XmmReg2;\n XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg1[32,32];\n XmmReg1[32,32] = XmmReg1[64,32] f- XmmReg1[96,32];\n XmmReg1[64,32] = tmp[0,32] f- tmp[32,32];\n XmmReg1[96,32] = tmp[64,32] f- tmp[96,32];\n}\n\n#--------------------\n#SSE3...\n#--------------------\n\ndefine pcodeop lddqu;\n:LDDQU XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xF0; XmmReg ... & m128 { XmmReg = lddqu(XmmReg, m128); }\n\ndefine pcodeop maskmovdqu;\n:MASKMOVDQU XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF7; XmmReg1 & XmmReg2\t\t{ XmmReg1 = maskmovdqu(XmmReg1, XmmReg2); }\n\ndefine pcodeop maxpd;\n:MAXPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5F; XmmReg ... & m128 { XmmReg = maxpd(XmmReg, m128); }\n:MAXPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = maxpd(XmmReg1, XmmReg2); }\n\ndefine pcodeop maxps;\n:MAXPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5F; XmmReg ... & m128 { XmmReg = maxps(XmmReg, m128); }\n:MAXPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = maxps(XmmReg1, XmmReg2); }\n\n:MAXSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5F; XmmReg ... & m64\n{\n local tmp:8 = m64;\n if (tmp f< XmmReg[0,64]) goto inst_next;\n XmmReg[0,64] = tmp;\n}\n\n:MAXSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2\n{\n if (XmmReg2[0,64] f< XmmReg1[0,64]) goto inst_next;\n XmmReg1[0,64] = XmmReg2[0,64];\n}\n\n:MAXSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5F; XmmReg ... & m32\n{\n local tmp:4 = m32;\n if (tmp f< XmmReg[0,32]) goto inst_next;\n XmmReg[0,32] = tmp;\n}\n\n:MAXSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2\n{\n if (XmmReg2[0,32] f< XmmReg1[0,32]) goto inst_next;\n XmmReg1[0,32] = XmmReg2[0,32];\n}\n\ndefine pcodeop minpd;\n:MINPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5D; XmmReg ... & m128 { XmmReg = minpd(XmmReg, m128); }\n:MINPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = minpd(XmmReg1, XmmReg2); }\n\ndefine pcodeop minps;\n:MINPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5D; XmmReg ... & m128 { XmmReg = minps(XmmReg, m128); }\n:MINPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = minps(XmmReg1, XmmReg2); }\n\n:MINSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5D; XmmReg ... & m64\n{\n local tmp:8 = m64;\n if (XmmReg[0,64] f< tmp) goto inst_next;\n XmmReg[0,64] = tmp;\n}\n\n:MINSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2\n{\n if (XmmReg1[0,64] f< XmmReg2[0,64]) goto inst_next;\n XmmReg1[0,64] = XmmReg2[0,64];\n}\n\n:MINSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5D; XmmReg ... & m32\n{\n local tmp:4 = m32;\n if (XmmReg[0,32] f< tmp) goto inst_next;\n XmmReg[0,32] = tmp;\n}\n\n:MINSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2\n{\n if (XmmReg1[0,32] f< XmmReg2[0,32]) goto inst_next;\n XmmReg1[0,32] = XmmReg2[0,32];\n}\n\n:MOVAPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x28; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = m[0,64];\n XmmReg[64,64] = m[64,64];\n}\n\n:MOVAPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x28; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg2[64,64];\n}\n\n:MOVAPD m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x29; m128 & XmmReg ...\n{\n m128 = XmmReg;\n}\n\n:MOVAPD XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x29; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg2[0,64] = XmmReg1[0,64];\n XmmReg2[64,64] = XmmReg1[64,64];\n}\n\n:MOVAPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x28; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = m[0,32];\n XmmReg[32,32] = m[32,32];\n XmmReg[64,32] = m[64,32];\n XmmReg[96,32] = m[96,32];\n}\n\n:MOVAPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x28; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg2[96,32];\n}\n\n:MOVAPS m128, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x29; m128 & XmmReg ...\n{\n m128 = XmmReg;\n}\n\n:MOVAPS XmmReg2, XmmReg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x29; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg2[0,32] = XmmReg1[0,32];\n XmmReg2[32,32] = XmmReg1[32,32];\n XmmReg2[64,32] = XmmReg1[64,32];\n XmmReg2[96,32] = XmmReg1[96,32];\n}\n\n:MOVD mmxreg, rm32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6E; rm32 & mmxreg ... { mmxreg = zext(rm32); }\n:MOVD rm32, mmxreg is vexMode=0 & rexWprefix=0 & mandover=0 & byte=0x0F; byte=0x7E; rm32 & check_rm32_dest ... & mmxreg ... { rm32 = mmxreg(0); build check_rm32_dest; }\n:MOVD XmmReg, rm32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6E; rm32 & XmmReg ... { XmmReg = zext(rm32); }\n:MOVD rm32, XmmReg is vexMode=0 & $(PRE_66) & rexWprefix=0 & byte=0x0F; byte=0x7E; rm32 & check_rm32_dest ... & XmmReg ... { rm32 = XmmReg(0); build check_rm32_dest; }\n@ifdef IA64\n:MOVQ mmxreg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0x0F; byte=0x6E; rm64 & mmxreg ... { mmxreg = rm64; }\n:MOVQ rm64, mmxreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0x0F; byte=0x7E; rm64 & mmxreg ... { rm64 = mmxreg; }\n:MOVQ XmmReg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x6E; rm64 & XmmReg ... { XmmReg = zext(rm64); }\n:MOVQ rm64, XmmReg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x7E; rm64 & XmmReg ... { rm64 = XmmReg(0); }\n@endif\n\n\n:MOVDIRI Mem,Reg32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x38; byte=0xF9; Mem & Reg32 ... { *Mem = Reg32; }\n@ifdef IA64\n:MOVDIRI Mem,Reg64 is vexMode=0 & $(PRE_NO) & $(REX_W) & byte=0x0F; byte=0x38; byte=0xF9; Mem & Reg64 ... { *Mem = Reg64; }\n@endif\n\ndefine pcodeop movdir64b;\n:MOVDIR64B Reg16, m512 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & addrsize=0 & byte=0x0F; byte=0x38; byte=0xF8; Reg16 ... & m512 {\n\tmovdir64b(Reg16, m512);\n}\n:MOVDIR64B Reg32, m512 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & addrsize=1 & byte=0x0F; byte=0x38; byte=0xF8; Reg32 ... & m512 {\n\tmovdir64b(Reg32, m512);\n}\n\n@ifdef IA64\n:MOVDIR64B Reg32, m512 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & addrsize=1 & byte=0x0F; byte=0x38; byte=0xF8; Reg32 ... & m512 {\n\tmovdir64b(Reg32, m512);\n}\n\n:MOVDIR64B Reg64, m512 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF8; Reg64 ... & m512 {\n\tmovdir64b(Reg64, m512);\n}\n@endif\n\n:MOVDDUP XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x12; m64 & XmmReg ...\n{\n XmmReg[0,64] = m64;\n XmmReg[64,64] = m64;\n}\n\n:MOVDDUP XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x12; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg2[0,64];\n}\n\n:MOVSHDUP XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x16; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = m[32,32];\n XmmReg[32,32] = m[32,32];\n XmmReg[64,32] = m[96,32];\n XmmReg[96,32] = m[96,32];\n}\n\n:MOVSHDUP XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x16; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg2[32,32];\n XmmReg1[32,32] = XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg2[96,32];\n XmmReg1[96,32] = XmmReg2[96,32];\n}\n\n:MOVSLDUP XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x12; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = m[0,32];\n XmmReg[32,32] = m[0,32];\n XmmReg[64,32] = m[64,32];\n XmmReg[96,32] = m[64,32];\n}\n\n:MOVSLDUP XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x12; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg2[0,32];\n XmmReg1[64,32] = XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg2[64,32];\n}\n\n:MOVDQA XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6F; XmmReg ... & m128 { XmmReg = m128; } \n:MOVDQA XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg2; }\n:MOVDQA m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7F; XmmReg ... & m128 { m128 = XmmReg; }\n:MOVDQA XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg2 = XmmReg1; }\n\n:MOVDQU XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x6F; XmmReg ... & m128 { XmmReg = m128; }\n:MOVDQU XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x6F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg2; }\n:MOVDQU m128, XmmReg is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7F; XmmReg ... & m128 { m128 = XmmReg; } \n:MOVDQU XmmReg2, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg2 = XmmReg1; }\n\n# TODO: this vexMode=0 & is potentially wrong\n\ndefine pcodeop movdq2q;\n:MOVDQ2Q mmxreg2, XmmReg1 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xD6; XmmReg1 & mmxreg2 { mmxreg2 = movdq2q(mmxreg2, XmmReg1); }\n\n:MOVHLPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x12; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,64] = XmmReg2[64,64]; }\n\n:MOVHPD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x16; XmmReg ... & m64 { XmmReg[64,64] = m64; }\n\n:MOVHPD m64, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x17; XmmReg ... & m64 { m64 = XmmReg[64,64]; }\n\n:MOVHPS XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x16; XmmReg ... & m64 { XmmReg[64,64] = m64; }\n\n:MOVHPS m64, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x17; XmmReg ... & m64 { m64 = XmmReg[64,64]; }\n\n:MOVLHPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x16; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[64,64] = XmmReg2[0,64]; }\n\n:MOVLPD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x12; XmmReg ... & m64 { XmmReg[0,64] = m64; }\n\n:MOVLPD m64, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x13; XmmReg ... & m64 { m64 = XmmReg[0,64]; }\n\n:MOVLPS XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x12; XmmReg ... & m64 { XmmReg[0,64] = m64; }\n\n:MOVLPS m64, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x13; XmmReg ... & m64 { m64 = XmmReg[0,64]; }\n\ndefine pcodeop movmskpd;\n:MOVMSKPD Reg32, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x50; XmmReg2 & Reg32 { Reg32 = movmskpd(Reg32, XmmReg2); }\n\ndefine pcodeop movmskps;\n:MOVMSKPS Reg32, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x50; XmmReg2 & Reg32 { Reg32 = movmskps(Reg32, XmmReg2); }\n\n:MOVNTQ m64, mmxreg is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE7; mmxreg ... & m64 { m64 = mmxreg; }\n\n:MOVNTDQ m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE7; XmmReg ... & m128 { m128 = XmmReg; }\n\n:MOVNTPD m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2B; XmmReg ... & m128 { m128 = XmmReg; }\n\n:MOVNTPS m128, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2B; XmmReg ... & m128 { m128 = XmmReg; }\n\n:MOVQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6F; mmxreg ... & m64 { mmxreg = m64; }\n:MOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg2; }\n:MOVQ m64, mmxreg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x7F; mmxreg ... & m64 { m64 = mmxreg; }\n:MOVQ mmxreg2, mmxreg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x7F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg2 = mmxreg1; }\n\n:MOVQ XmmReg, m64 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7E; XmmReg ... & m64\n{\n\tXmmReg = zext(m64);\n}\n\n:MOVQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7E; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n\tXmmReg1 = zext(XmmReg2[0,64]);\n}\n\n:MOVQ m64, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD6; m64 & XmmReg ...\n{\n m64 = XmmReg[0,64];\n}\n\n:MOVQ XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD6; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg2 = zext(XmmReg1[0,64]);\n}\n\n:MOVQ2DQ XmmReg, mmxreg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xD6; XmmReg & mmxreg2\n{\n XmmReg = zext(mmxreg2);\n# may need to model x87 FPU state changes too ?????\n}\n\n:MOVSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x10; m64 & XmmReg ...\n{\n XmmReg[0,64] = m64;\n XmmReg[64,64] = 0;\n}\n\n:MOVSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg2[0,64];\n}\n\n:MOVSD m64, XmmReg is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x11; m64 & XmmReg ...\n{\n m64 = XmmReg[0,64];\n}\n\n:MOVSD XmmReg2, XmmReg1 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg2[0,64] = XmmReg1[0,64];\n}\n\n:MOVSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x10; m32 & XmmReg ...\n{\n XmmReg[0,32] = m32;\n XmmReg[32,32] = 0;\n XmmReg[64,32] = 0;\n XmmReg[96,32] = 0;\n}\n\n:MOVSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg2[0,32];\n}\n\n:MOVSS m32, XmmReg is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x11; m32 & XmmReg ...\n{\n m32 = XmmReg[0,32];\n}\n\n:MOVSS XmmReg2, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg2[0,32] = XmmReg1[0,32];\n}\n\n:MOVUPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x10; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = m[0,64];\n XmmReg[64,64] = m[64,64];\n}\n\n:MOVUPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg2[64,64];\n}\n\n:MOVUPD m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x11; m128 & XmmReg ...\n{\n m128 = XmmReg;\n}\n\n:MOVUPD XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg2[0,64] = XmmReg1[0,64];\n XmmReg2[64,64] = XmmReg1[64,64];\n}\n\n# Not sure why someone had done it this way ?????\n#Xmm2m128: m128 is vexMode=0 & m128 { export m128; } \n#Xmm2m128: XmmReg2 is vexMode=0 & xmmmod=3 & XmmReg2 { export XmmReg2; }\n#\n#define pcodeop movups;\n##:MOVUPS XmmReg, m128 is vexMode=0 & byte=0x0F; byte=0x10; XmmReg ... & m128\t\t\t\t\t{ XmmReg = movups(XmmReg, m128); }\n##:MOVUPS XmmReg1, XmmReg2 is vexMode=0 & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = movups(XmmReg1, XmmReg2); }\n#\n#:MOVUPS XmmReg,Xmm2m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x10; XmmReg ... & Xmm2m128 { XmmReg = movups(XmmReg, Xmm2m128); }\n\n:MOVUPS XmmReg, m128 is vexMode=0 & byte=0x0F; byte=0x10; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = m[0,32];\n XmmReg[32,32] = m[32,32];\n XmmReg[64,32] = m[64,32];\n XmmReg[96,32] = m[96,32];\n}\n\n:MOVUPS XmmReg1, XmmReg2 is vexMode=0 & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg2[96,32];\n}\n\n:MOVUPS m128, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x11; m128 & XmmReg ...\n{\n m128 = XmmReg;\n}\n\n:MOVUPS XmmReg2, XmmReg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg2[0,32] = XmmReg1[0,32];\n XmmReg2[32,32] = XmmReg1[32,32];\n XmmReg2[64,32] = XmmReg1[64,32];\n XmmReg2[96,32] = XmmReg1[96,32];\n}\n\n:MULPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x59; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] f* m[0,64];\n XmmReg[64,64] = XmmReg[64,64] f* m[64,64];\n}\n\n:MULPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f* XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] f* XmmReg2[64,64];\n}\n\n:MULPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x59; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] f* m[0,32];\n XmmReg[32,32] = XmmReg[32,32] f* m[32,32];\n XmmReg[64,32] = XmmReg[64,32] f* m[64,32];\n XmmReg[96,32] = XmmReg[96,32] f* m[96,32];\n}\n\n:MULPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f* XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] f* XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] f* XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] f* XmmReg2[96,32];\n}\n\n:MULSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x59; m64 & XmmReg ...\n{\n XmmReg[0,64] = XmmReg[0,64] f* m64;\n}\n\n:MULSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f* XmmReg2[0,64];\n}\n\n:MULSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x59; m32 & XmmReg ...\n{\n XmmReg[0,32] = XmmReg[0,32] f* m32;\n}\n\n:MULSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f* XmmReg2[0,32];\n}\n\n:ORPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x56; XmmReg ... & m128 { XmmReg = XmmReg | m128; }\n:ORPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x56; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 | XmmReg2; }\n\n:ORPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x56; XmmReg ... & m128 { XmmReg = XmmReg | m128; }\n:ORPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x56; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 | XmmReg2; }\n\n# what about these ?????\ndefine pcodeop packsswb;\n:PACKSSWB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x63; mmxreg ... & m64 { mmxreg = packsswb(mmxreg, m64); }\n:PACKSSWB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x63; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = packsswb(mmxreg1, mmxreg2); }\n\ndefine pcodeop packssdw;\n:PACKSSDW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6B; mmxreg ... & m64 { mmxreg = packssdw(mmxreg, m64); }\n:PACKSSDW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6B; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = packssdw(mmxreg1, mmxreg2); }\n\n:PACKSSWB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x63; XmmReg ... & m128 { XmmReg = packsswb(XmmReg, m128); }\n:PACKSSWB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x63; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = packsswb(XmmReg1, XmmReg2); }\n:PACKSSDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6B; XmmReg ... & m128 { XmmReg = packssdw(XmmReg, m128); }\n:PACKSSDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6B; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = packssdw(XmmReg1, XmmReg2); }\n\n#sword < 0 : ubyte = 0\n#sword > 0xff: ubyte = 0xff\n#otherwise ubyte = sword\nmacro sswub(sword, ubyte) {\n ubyte = (sword s> 0xff:2) * 0xff:1;\n ubyte = ubyte + (sword s> 0:2) * (sword s<= 0xff:2) * sword:1;\n}\n\n:PACKUSWB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x67; mmxreg ... & m64\n{\n local dest_copy:8 = mmxreg;\n local src_copy:8 = m64;\n local ubyte:1 = 0;\n sswub(dest_copy[0,16],ubyte);\n mmxreg[0,8] = ubyte;\n sswub(dest_copy[16,16],ubyte);\n mmxreg[8,8] = ubyte;\n sswub(dest_copy[32,16],ubyte);\n mmxreg[16,8] = ubyte;\n sswub(dest_copy[48,16],ubyte);\n mmxreg[24,8] = ubyte;\n sswub(src_copy[0,16],ubyte);\n mmxreg[32,8] = ubyte;\n sswub(src_copy[16,16],ubyte);\n mmxreg[40,8] = ubyte;\n sswub(src_copy[32,16],ubyte);\n mmxreg[48,8] = ubyte;\n sswub(src_copy[48,16],ubyte);\n mmxreg[56,8] = ubyte;\n}\n\n:PACKUSWB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x67; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n local dest_copy:8 = mmxreg1;\n local src_copy:8 = mmxreg2;\n local ubyte:1 = 0;\n sswub(dest_copy[0,16],ubyte);\n mmxreg1[0,8] = ubyte;\n sswub(dest_copy[16,16],ubyte);\n mmxreg1[8,8] = ubyte;\n sswub(dest_copy[32,16],ubyte);\n mmxreg1[16,8] = ubyte;\n sswub(dest_copy[48,16],ubyte);\n mmxreg1[24,8] = ubyte;\n sswub(src_copy[0,16],ubyte);\n mmxreg1[32,8] = ubyte;\n sswub(src_copy[16,16],ubyte);\n mmxreg1[40,8] = ubyte;\n sswub(src_copy[32,16],ubyte);\n mmxreg1[48,8] = ubyte;\n sswub(src_copy[48,16],ubyte);\n mmxreg1[56,8] = ubyte;\n}\n\n:PACKUSWB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x67; XmmReg ... & m128\n{\n local dest_copy:16 = XmmReg;\n local src_copy:16 = m128;\n local ubyte:1 = 0;\n sswub(dest_copy[0,16],ubyte);\n XmmReg[0,8] = ubyte;\n sswub(dest_copy[16,16],ubyte);\n XmmReg[8,8] = ubyte;\n sswub(dest_copy[32,16],ubyte);\n XmmReg[16,8] = ubyte;\n sswub(dest_copy[48,16],ubyte);\n XmmReg[24,8] = ubyte;\n sswub(dest_copy[64,16],ubyte);\n XmmReg[32,8] = ubyte;\n sswub(dest_copy[80,16],ubyte);\n XmmReg[40,8] = ubyte;\n sswub(dest_copy[96,16],ubyte);\n XmmReg[48,8] = ubyte;\n sswub(dest_copy[112,16],ubyte);\n XmmReg[56,8] = ubyte;\n\n sswub(src_copy[0,16],ubyte);\n XmmReg[64,8] = ubyte;\n sswub(src_copy[16,16],ubyte);\n XmmReg[72,8] = ubyte;\n sswub(src_copy[32,16],ubyte);\n XmmReg[80,8] = ubyte;\n sswub(src_copy[48,16],ubyte);\n XmmReg[88,8] = ubyte;\n sswub(src_copy[64,16],ubyte);\n XmmReg[96,8] = ubyte;\n sswub(src_copy[80,16],ubyte);\n XmmReg[104,8] = ubyte;\n sswub(src_copy[96,16],ubyte);\n XmmReg[112,8] = ubyte;\n sswub(src_copy[112,16],ubyte);\n XmmReg[120,8] = ubyte;\n}\n\n:PACKUSWB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x67; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n local dest_copy:16 = XmmReg1;\n local src_copy:16 = XmmReg2;\n local ubyte:1 = 0;\n sswub(dest_copy[0,16],ubyte);\n XmmReg1[0,8] = ubyte;\n sswub(dest_copy[16,16],ubyte);\n XmmReg1[8,8] = ubyte;\n sswub(dest_copy[32,16],ubyte);\n XmmReg1[16,8] = ubyte;\n sswub(dest_copy[48,16],ubyte);\n XmmReg1[24,8] = ubyte;\n sswub(dest_copy[64,16],ubyte);\n XmmReg1[32,8] = ubyte;\n sswub(dest_copy[80,16],ubyte);\n XmmReg1[40,8] = ubyte;\n sswub(dest_copy[96,16],ubyte);\n XmmReg1[48,8] = ubyte;\n sswub(dest_copy[112,16],ubyte);\n XmmReg1[56,8] = ubyte;\n\n sswub(src_copy[0,16],ubyte);\n XmmReg1[64,8] = ubyte;\n sswub(src_copy[16,16],ubyte);\n XmmReg1[72,8] = ubyte;\n sswub(src_copy[32,16],ubyte);\n XmmReg1[80,8] = ubyte;\n sswub(src_copy[48,16],ubyte);\n XmmReg1[88,8] = ubyte;\n sswub(src_copy[64,16],ubyte);\n XmmReg1[96,8] = ubyte;\n sswub(src_copy[80,16],ubyte);\n XmmReg1[104,8] = ubyte;\n sswub(src_copy[96,16],ubyte);\n XmmReg1[112,8] = ubyte;\n sswub(src_copy[112,16],ubyte);\n XmmReg1[120,8] = ubyte;\n}\n\ndefine pcodeop pabsb;\n:PABSB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1c; mmxreg ... & m64\t\t\t\t\t{ mmxreg=pabsb(mmxreg,m64); }\n:PABSB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1c; mmxmod = 3 & mmxreg1 & mmxreg2\t{ mmxreg1=pabsb(mmxreg1,mmxreg2); }\n:PABSB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1c; XmmReg ... & m128 { XmmReg=pabsb(XmmReg,m128); }\n:PABSB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1c; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pabsb(XmmReg1,XmmReg2); }\n\ndefine pcodeop pabsw;\n:PABSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1d; mmxreg ... & m64\t\t\t\t\t{ mmxreg=pabsw(mmxreg,m64); }\n:PABSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1d; mmxmod = 3 & mmxreg1 & mmxreg2\t{ mmxreg1=pabsw(mmxreg1,mmxreg2); }\n:PABSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1d; XmmReg ... & m128 { XmmReg=pabsw(XmmReg,m128); }\n:PABSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1d; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pabsw(XmmReg1,XmmReg2); }\n\ndefine pcodeop pabsd;\n:PABSD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1e; mmxreg ... & m64\t\t\t\t\t{ mmxreg=pabsd(mmxreg,m64); }\n:PABSD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1e; mmxmod = 3 & mmxreg1 & mmxreg2\t{ mmxreg1=pabsd(mmxreg1,mmxreg2); }\n:PABSD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1e; XmmReg ... & m128 { XmmReg=pabsd(XmmReg,m128); }\n:PABSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1e; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pabsd(XmmReg1,XmmReg2); }\n\n:PADDB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFC; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,8] = mmxreg[0,8] + m[0,8];\n mmxreg[8,8] = mmxreg[8,8] + m[8,8];\n mmxreg[16,8] = mmxreg[16,8] + m[16,8];\n mmxreg[24,8] = mmxreg[24,8] + m[24,8];\n mmxreg[32,8] = mmxreg[32,8] + m[32,8];\n mmxreg[40,8] = mmxreg[40,8] + m[40,8];\n mmxreg[48,8] = mmxreg[48,8] + m[48,8];\n mmxreg[56,8] = mmxreg[56,8] + m[56,8];\n}\n\n:PADDB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFC; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,8] = mmxreg1[0,8] + mmxreg2[0,8];\n mmxreg1[8,8] = mmxreg1[8,8] + mmxreg2[8,8];\n mmxreg1[16,8] = mmxreg1[16,8] + mmxreg2[16,8];\n mmxreg1[24,8] = mmxreg1[24,8] + mmxreg2[24,8];\n mmxreg1[32,8] = mmxreg1[32,8] + mmxreg2[32,8];\n mmxreg1[40,8] = mmxreg1[40,8] + mmxreg2[40,8];\n mmxreg1[48,8] = mmxreg1[48,8] + mmxreg2[48,8];\n mmxreg1[56,8] = mmxreg1[56,8] + mmxreg2[56,8];\n}\n\n:PADDW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFD; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,16] = mmxreg[0,16] + m[0,16];\n mmxreg[16,16] = mmxreg[16,16] + m[16,16];\n mmxreg[32,16] = mmxreg[32,16] + m[32,16];\n mmxreg[48,16] = mmxreg[48,16] + m[48,16];\n}\n\n:PADDW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFD; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = mmxreg1[0,16] + mmxreg2[0,16];\n mmxreg1[16,16] = mmxreg1[16,16] + mmxreg2[16,16];\n mmxreg1[32,16] = mmxreg1[32,16] + mmxreg2[32,16];\n mmxreg1[48,16] = mmxreg1[48,16] + mmxreg2[48,16];\n}\n\n:PADDD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFE; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,32] = mmxreg[0,32] + m[0,32];\n mmxreg[32,32] = mmxreg[32,32] + m[32,32];\n}\n\n:PADDD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFE; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,32] = mmxreg1[0,32] + mmxreg2[0,32];\n mmxreg1[32,32] = mmxreg1[32,32] + mmxreg2[32,32];\n}\n\n:PADDB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFC; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,8] = XmmReg[0,8] + m[0,8];\n XmmReg[8,8] = XmmReg[8,8] + m[8,8];\n XmmReg[16,8] = XmmReg[16,8] + m[16,8];\n XmmReg[24,8] = XmmReg[24,8] + m[24,8];\n XmmReg[32,8] = XmmReg[32,8] + m[32,8];\n XmmReg[40,8] = XmmReg[40,8] + m[40,8];\n XmmReg[48,8] = XmmReg[48,8] + m[48,8];\n XmmReg[56,8] = XmmReg[56,8] + m[56,8];\n XmmReg[64,8] = XmmReg[64,8] + m[64,8];\n XmmReg[72,8] = XmmReg[72,8] + m[72,8];\n XmmReg[80,8] = XmmReg[80,8] + m[80,8];\n XmmReg[88,8] = XmmReg[88,8] + m[88,8];\n XmmReg[96,8] = XmmReg[96,8] + m[96,8];\n XmmReg[104,8] = XmmReg[104,8] + m[104,8];\n XmmReg[112,8] = XmmReg[112,8] + m[112,8];\n XmmReg[120,8] = XmmReg[120,8] + m[120,8];\n}\n\n## example of bitfield solution\n#:PADDB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFC; xmmmod = 3 & XmmReg1 & XmmReg2 \n#{\n# XmmReg1[ 0,8] = XmmReg1[ 0,8] + XmmReg2[ 0,8];\n# XmmReg1[ 8,8] = XmmReg1[ 8,8] + XmmReg2[ 8,8];\n# XmmReg1[ 16,8] = XmmReg1[ 16,8] + XmmReg2[ 16,8];\n# XmmReg1[ 24,8] = XmmReg1[ 24,8] + XmmReg2[ 24,8];\n# XmmReg1[ 32,8] = XmmReg1[ 32,8] + XmmReg2[ 32,8];\n# XmmReg1[ 40,8] = XmmReg1[ 40,8] + XmmReg2[ 40,8];\n# XmmReg1[ 48,8] = XmmReg1[ 48,8] + XmmReg2[ 48,8];\n# XmmReg1[ 56,8] = XmmReg1[ 56,8] + XmmReg2[ 56,8];\n## XmmReg1[ 64,8] = XmmReg1[ 64,8] + XmmReg2[ 64,8];\n## XmmReg1[ 72,8] = XmmReg1[ 72,8] + XmmReg2[ 72,8];\n## XmmReg1[ 80,8] = XmmReg1[ 80,8] + XmmReg2[ 80,8];\n## XmmReg1[ 88,8] = XmmReg1[ 88,8] + XmmReg2[ 88,8];\n## XmmReg1[ 96,8] = XmmReg1[ 96,8] + XmmReg2[ 96,8];\n## XmmReg1[104,8] = XmmReg1[104,8] + XmmReg2[104,8];\n## XmmReg1[112,8] = XmmReg1[112,8] + XmmReg2[112,8];\n## XmmReg1[120,8] = XmmReg1[120,8] + XmmReg2[120,8];\n#}\n\n# full set of XMM byte registers\n:PADDB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFC; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,8] = XmmReg1[0,8] + XmmReg2[0,8];\n XmmReg1[8,8] = XmmReg1[8,8] + XmmReg2[8,8];\n XmmReg1[16,8] = XmmReg1[16,8] + XmmReg2[16,8];\n XmmReg1[24,8] = XmmReg1[24,8] + XmmReg2[24,8];\n XmmReg1[32,8] = XmmReg1[32,8] + XmmReg2[32,8];\n XmmReg1[40,8] = XmmReg1[40,8] + XmmReg2[40,8];\n XmmReg1[48,8] = XmmReg1[48,8] + XmmReg2[48,8];\n XmmReg1[56,8] = XmmReg1[56,8] + XmmReg2[56,8];\n XmmReg1[64,8] = XmmReg1[64,8] + XmmReg2[64,8];\n XmmReg1[72,8] = XmmReg1[72,8] + XmmReg2[72,8];\n XmmReg1[80,8] = XmmReg1[80,8] + XmmReg2[80,8];\n XmmReg1[88,8] = XmmReg1[88,8] + XmmReg2[88,8];\n XmmReg1[96,8] = XmmReg1[96,8] + XmmReg2[96,8];\n XmmReg1[104,8] = XmmReg1[104,8] + XmmReg2[104,8];\n XmmReg1[112,8] = XmmReg1[112,8] + XmmReg2[112,8];\n XmmReg1[120,8] = XmmReg1[120,8] + XmmReg2[120,8];\n}\n\n:PADDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFD; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,16] = XmmReg[0,16] + m[0,16];\n XmmReg[16,16] = XmmReg[16,16] + m[16,16];\n XmmReg[32,16] = XmmReg[32,16] + m[32,16];\n XmmReg[48,16] = XmmReg[48,16] + m[48,16];\n XmmReg[64,16] = XmmReg[64,16] + m[64,16];\n XmmReg[80,16] = XmmReg[80,16] + m[80,16];\n XmmReg[96,16] = XmmReg[96,16] + m[96,16];\n XmmReg[112,16] = XmmReg[112,16] + m[112,16];\n}\n\n:PADDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFD; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,16] = XmmReg1[0,16] + XmmReg2[0,16];\n XmmReg1[16,16] = XmmReg1[16,16] + XmmReg2[16,16];\n XmmReg1[32,16] = XmmReg1[32,16] + XmmReg2[32,16];\n XmmReg1[48,16] = XmmReg1[48,16] + XmmReg2[48,16];\n XmmReg1[64,16] = XmmReg1[64,16] + XmmReg2[64,16];\n XmmReg1[80,16] = XmmReg1[80,16] + XmmReg2[80,16];\n XmmReg1[96,16] = XmmReg1[96,16] + XmmReg2[96,16];\n XmmReg1[112,16] = XmmReg1[112,16] + XmmReg2[112,16];\n}\n\n:PADDD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFE; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] + m[0,32];\n XmmReg[32,32] = XmmReg[32,32] + m[32,32];\n XmmReg[64,32] = XmmReg[64,32] + m[64,32];\n XmmReg[96,32] = XmmReg[96,32] + m[96,32];\n}\n\n:PADDD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFE; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] + XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] + XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] + XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] + XmmReg2[96,32];\n}\n\n:PADDQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD4; mmxreg ... & m64\n{\n mmxreg = mmxreg + m64;\n}\n\n:PADDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD4; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1 = mmxreg1 + mmxreg2;\n}\n\n:PADDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD4; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] + m[0,64];\n XmmReg[64,64] = XmmReg[64,64] + m[64,64];\n}\n\n:PADDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD4; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] + XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] + XmmReg2[64,64];\n}\n\ndefine pcodeop paddsb;\n:PADDSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEC; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddsb(mmxreg1, mmxreg2_m64); }\n\ndefine pcodeop paddsw;\n:PADDSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xED; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddsw(mmxreg1, mmxreg2_m64); }\n\n:PADDSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEC; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddsb(XmmReg1, XmmReg2_m128); }\n:PADDSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xED; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddsw(XmmReg1, XmmReg2_m128); }\n\ndefine pcodeop paddusb;\n:PADDUSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDC; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddusb(mmxreg1, mmxreg2_m64); }\n\ndefine pcodeop paddusw;\n:PADDUSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDD; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddusw(mmxreg1, mmxreg2_m64); }\n\n:PADDUSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDC; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddusb(XmmReg1, XmmReg2_m128); }\n:PADDUSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDD; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddusw(XmmReg1, XmmReg2_m128); }\n\n:PALIGNR mmxreg, m64, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x3A; byte=0x0F; m64 & mmxreg ...; imm8\n{\n temp:16 = ( ( zext(mmxreg) << 64 ) | zext( m64 ) ) >> ( imm8 * 8 );\n mmxreg = temp:8;\n}\n \n:PALIGNR mmxreg1, mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x3A; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2; imm8\n{\n temp:16 = ( ( zext(mmxreg1) << 64 ) | zext( mmxreg2 ) ) >> ( imm8 * 8 );\n mmxreg1 = temp:8;\n}\n \n:PALIGNR XmmReg1, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0F; m128 & XmmReg1 ...; imm8\n{\n temp:32 = ( ( zext(XmmReg1) << 128 ) | zext( m128 ) ) >> ( imm8 * 8 );\n XmmReg1 = temp:16;\n}\n\n:PALIGNR XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0F; xmmmod=3 & XmmReg1 & XmmReg2; imm8\n{\n temp:32 = ( ( zext(XmmReg1) << 128 ) | zext( XmmReg2 ) ) >> ( imm8 * 8 );\n XmmReg1 = temp:16;\n}\n\n:PAND mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDB; mmxreg ... & m64\t{ mmxreg = mmxreg & m64; }\n:PAND mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDB; mmxmod = 3 & mmxreg1 & mmxreg2\t{ mmxreg1 = mmxreg1 & mmxreg2; }\n:PAND XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDB; XmmReg ... & m128\t{ XmmReg = XmmReg & m128; }\n:PAND XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDB; xmmmod = 3 & XmmReg1 & XmmReg2\t{ XmmReg1 = XmmReg1 & XmmReg2; }\n\n:PANDN mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDF; mmxreg ... & m64\t\t\t\t{ mmxreg = ~mmxreg & m64; }\n:PANDN mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDF; mmxmod = 3 & mmxreg1 & mmxreg2\t{ mmxreg1 = ~mmxreg1 & mmxreg2; }\n:PANDN XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDF; XmmReg ... & m128\t\t\t { XmmReg = ~XmmReg & m128; }\n:PANDN XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDF; xmmmod = 3 & XmmReg1 & XmmReg2\t{ XmmReg1 = ~XmmReg1 & XmmReg2; }\n\ndefine pcodeop pavgb;\n:PAVGB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE0; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,8] = pavgb(mmxreg[0,8], m[0,8]);\n mmxreg[8,8] = pavgb(mmxreg[8,8], m[8,8]);\n mmxreg[16,8] = pavgb(mmxreg[16,8], m[16,8]);\n mmxreg[24,8] = pavgb(mmxreg[24,8], m[24,8]);\n mmxreg[32,8] = pavgb(mmxreg[32,8], m[32,8]);\n mmxreg[40,8] = pavgb(mmxreg[40,8], m[40,8]);\n mmxreg[48,8] = pavgb(mmxreg[48,8], m[48,8]);\n mmxreg[56,8] = pavgb(mmxreg[56,8], m[56,8]);\n}\n\n:PAVGB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE0; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,8] = pavgb(mmxreg1[0,8], mmxreg2[0,8]);\n mmxreg1[8,8] = pavgb(mmxreg1[8,8], mmxreg2[8,8]);\n mmxreg1[16,8] = pavgb(mmxreg1[16,8], mmxreg2[16,8]);\n mmxreg1[24,8] = pavgb(mmxreg1[24,8], mmxreg2[24,8]);\n mmxreg1[32,8] = pavgb(mmxreg1[32,8], mmxreg2[32,8]);\n mmxreg1[40,8] = pavgb(mmxreg1[40,8], mmxreg2[40,8]);\n mmxreg1[48,8] = pavgb(mmxreg1[48,8], mmxreg2[48,8]);\n mmxreg1[56,8] = pavgb(mmxreg1[56,8], mmxreg2[56,8]);\n}\n\ndefine pcodeop pavgw;\n:PAVGW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE3; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,16] = pavgw(mmxreg[0,16], m[0,16]);\n mmxreg[16,16] = pavgw(mmxreg[16,16], m[16,16]);\n mmxreg[32,16] = pavgw(mmxreg[32,16], m[32,16]);\n mmxreg[48,16] = pavgw(mmxreg[48,16], m[48,16]);\n}\n\n:PAVGW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE3; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = pavgw(mmxreg1[0,16], mmxreg2[0,16]);\n mmxreg1[16,16] = pavgw(mmxreg1[16,16], mmxreg2[16,16]);\n mmxreg1[32,16] = pavgw(mmxreg1[32,16], mmxreg2[32,16]);\n mmxreg1[48,16] = pavgw(mmxreg1[48,16], mmxreg2[48,16]);\n}\n\n:PAVGB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE0; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,8] = pavgb(XmmReg[0,8], m[0,8]);\n XmmReg[8,8] = pavgb(XmmReg[8,8], m[8,8]);\n XmmReg[16,8] = pavgb(XmmReg[16,8], m[16,8]);\n XmmReg[24,8] = pavgb(XmmReg[24,8], m[24,8]);\n XmmReg[32,8] = pavgb(XmmReg[32,8], m[32,8]);\n XmmReg[40,8] = pavgb(XmmReg[40,8], m[40,8]);\n XmmReg[48,8] = pavgb(XmmReg[48,8], m[48,8]);\n XmmReg[56,8] = pavgb(XmmReg[56,8], m[56,8]);\n XmmReg[64,8] = pavgb(XmmReg[64,8], m[64,8]);\n XmmReg[72,8] = pavgb(XmmReg[72,8], m[72,8]);\n XmmReg[80,8] = pavgb(XmmReg[80,8], m[80,8]);\n XmmReg[88,8] = pavgb(XmmReg[88,8], m[88,8]);\n XmmReg[96,8] = pavgb(XmmReg[96,8], m[96,8]);\n XmmReg[104,8] = pavgb(XmmReg[104,8], m[104,8]);\n XmmReg[112,8] = pavgb(XmmReg[112,8], m[112,8]);\n XmmReg[120,8] = pavgb(XmmReg[120,8], m[120,8]);\n}\n\n# full set of XMM byte registers\n:PAVGB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE0; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,8] = pavgb(XmmReg1[0,8], XmmReg2[0,8]);\n XmmReg1[8,8] = pavgb(XmmReg1[8,8], XmmReg2[8,8]);\n XmmReg1[16,8] = pavgb(XmmReg1[16,8], XmmReg2[16,8]);\n XmmReg1[24,8] = pavgb(XmmReg1[24,8], XmmReg2[24,8]);\n XmmReg1[32,8] = pavgb(XmmReg1[32,8], XmmReg2[32,8]);\n XmmReg1[40,8] = pavgb(XmmReg1[40,8], XmmReg2[40,8]);\n XmmReg1[48,8] = pavgb(XmmReg1[48,8], XmmReg2[48,8]);\n XmmReg1[56,8] = pavgb(XmmReg1[56,8], XmmReg2[56,8]);\n XmmReg1[64,8] = pavgb(XmmReg1[64,8], XmmReg2[64,8]);\n XmmReg1[72,8] = pavgb(XmmReg1[72,8], XmmReg2[72,8]);\n XmmReg1[80,8] = pavgb(XmmReg1[80,8], XmmReg2[80,8]);\n XmmReg1[88,8] = pavgb(XmmReg1[88,8], XmmReg2[88,8]);\n XmmReg1[96,8] = pavgb(XmmReg1[96,8], XmmReg2[96,8]);\n XmmReg1[104,8] = pavgb(XmmReg1[104,8], XmmReg2[104,8]);\n XmmReg1[112,8] = pavgb(XmmReg1[112,8], XmmReg2[112,8]);\n XmmReg1[120,8] = pavgb(XmmReg1[120,8], XmmReg2[120,8]);\n}\n\n:PAVGW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE3; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,16] = pavgw(XmmReg[0,16], m[0,16]);\n XmmReg[16,16] = pavgw(XmmReg[16,16], m[16,16]);\n XmmReg[32,16] = pavgw(XmmReg[32,16], m[32,16]);\n XmmReg[48,16] = pavgw(XmmReg[48,16], m[48,16]);\n XmmReg[64,16] = pavgw(XmmReg[64,16], m[64,16]);\n XmmReg[80,16] = pavgw(XmmReg[80,16], m[80,16]);\n XmmReg[96,16] = pavgw(XmmReg[96,16], m[96,16]);\n XmmReg[112,16] = pavgw(XmmReg[112,16], m[112,16]);\n}\n\n:PAVGW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE3; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,16] = pavgw(XmmReg1[0,16], XmmReg2[0,16]);\n XmmReg1[16,16] = pavgw(XmmReg1[16,16], XmmReg2[16,16]);\n XmmReg1[32,16] = pavgw(XmmReg1[32,16], XmmReg2[32,16]);\n XmmReg1[48,16] = pavgw(XmmReg1[48,16], XmmReg2[48,16]);\n XmmReg1[64,16] = pavgw(XmmReg1[64,16], XmmReg2[64,16]);\n XmmReg1[80,16] = pavgw(XmmReg1[80,16], XmmReg2[80,16]);\n XmmReg1[96,16] = pavgw(XmmReg1[96,16], XmmReg2[96,16]);\n XmmReg1[112,16] = pavgw(XmmReg1[112,16], XmmReg2[112,16]);\n}\n\n:PCMPEQB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x74; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,8] = (mmxreg[0,8] == m[0,8]) * 0xFF;\n mmxreg[8,8] = (mmxreg[8,8] == m[8,8]) * 0xFF;\n mmxreg[16,8] = (mmxreg[16,8] == m[16,8]) * 0xFF;\n mmxreg[24,8] = (mmxreg[24,8] == m[24,8]) * 0xFF;\n mmxreg[32,8] = (mmxreg[32,8] == m[32,8]) * 0xFF;\n mmxreg[40,8] = (mmxreg[40,8] == m[40,8]) * 0xFF;\n mmxreg[48,8] = (mmxreg[48,8] == m[48,8]) * 0xFF;\n mmxreg[56,8] = (mmxreg[56,8] == m[56,8]) * 0xFF;\n}\n\n:PCMPEQB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x74; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,8] = (mmxreg1[0,8] == mmxreg2[0,8]) * 0xFF;\n mmxreg1[8,8] = (mmxreg1[8,8] == mmxreg2[8,8]) * 0xFF;\n mmxreg1[16,8] = (mmxreg1[16,8] == mmxreg2[16,8]) * 0xFF;\n mmxreg1[24,8] = (mmxreg1[24,8] == mmxreg2[24,8]) * 0xFF;\n mmxreg1[32,8] = (mmxreg1[32,8] == mmxreg2[32,8]) * 0xFF;\n mmxreg1[40,8] = (mmxreg1[40,8] == mmxreg2[40,8]) * 0xFF;\n mmxreg1[48,8] = (mmxreg1[48,8] == mmxreg2[48,8]) * 0xFF;\n mmxreg1[56,8] = (mmxreg1[56,8] == mmxreg2[56,8]) * 0xFF;\n}\n\n:PCMPEQW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x75; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,16] = zext(mmxreg[0,16] == m[0,16]) * 0xFFFF;\n mmxreg[16,16] = zext(mmxreg[16,16] == m[16,16]) * 0xFFFF;\n mmxreg[32,16] = zext(mmxreg[32,16] == m[32,16]) * 0xFFFF;\n mmxreg[48,16] = zext(mmxreg[48,16] == m[48,16]) * 0xFFFF;\n}\n\n:PCMPEQW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x75; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = zext(mmxreg1[0,16] == mmxreg2[0,16]) * 0xFFFF;\n mmxreg1[16,16] = zext(mmxreg1[16,16] == mmxreg2[16,16]) * 0xFFFF;\n mmxreg1[32,16] = zext(mmxreg1[32,16] == mmxreg2[32,16]) * 0xFFFF;\n mmxreg1[48,16] = zext(mmxreg1[48,16] == mmxreg2[48,16]) * 0xFFFF;\n}\n\n:PCMPEQD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x76; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,32] = zext(mmxreg[0,32] == m[0,32]) * 0xFFFFFFFF;\n mmxreg[32,32] = zext(mmxreg[32,32] == m[32,32]) * 0xFFFFFFFF;\n}\n\n:PCMPEQD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x76; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,32] = zext(mmxreg1[0,32] == mmxreg2[0,32]) * 0xFFFFFFFF;\n mmxreg1[32,32] = zext(mmxreg1[32,32] == mmxreg2[32,32]) * 0xFFFFFFFF;\n}\n\n:PCMPEQB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x74; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,8] = (XmmReg[0,8] == m[0,8]) * 0xFF;\n XmmReg[8,8] = (XmmReg[8,8] == m[8,8]) * 0xFF;\n XmmReg[16,8] = (XmmReg[16,8] == m[16,8]) * 0xFF;\n XmmReg[24,8] = (XmmReg[24,8] == m[24,8]) * 0xFF;\n XmmReg[32,8] = (XmmReg[32,8] == m[32,8]) * 0xFF;\n XmmReg[40,8] = (XmmReg[40,8] == m[40,8]) * 0xFF;\n XmmReg[48,8] = (XmmReg[48,8] == m[48,8]) * 0xFF;\n XmmReg[56,8] = (XmmReg[56,8] == m[56,8]) * 0xFF;\n XmmReg[64,8] = (XmmReg[64,8] == m[64,8]) * 0xFF;\n XmmReg[72,8] = (XmmReg[72,8] == m[72,8]) * 0xFF;\n XmmReg[80,8] = (XmmReg[80,8] == m[80,8]) * 0xFF;\n XmmReg[88,8] = (XmmReg[88,8] == m[88,8]) * 0xFF;\n XmmReg[96,8] = (XmmReg[96,8] == m[96,8]) * 0xFF;\n XmmReg[104,8] = (XmmReg[104,8] == m[104,8]) * 0xFF;\n XmmReg[112,8] = (XmmReg[112,8] == m[112,8]) * 0xFF;\n XmmReg[120,8] = (XmmReg[120,8] == m[120,8]) * 0xFF;\n}\n\n# full set of XMM byte registers\n:PCMPEQB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x74; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,8] = (XmmReg1[0,8] == XmmReg2[0,8]) * 0xFF;\n XmmReg1[8,8] = (XmmReg1[8,8] == XmmReg2[8,8]) * 0xFF;\n XmmReg1[16,8] = (XmmReg1[16,8] == XmmReg2[16,8]) * 0xFF;\n XmmReg1[24,8] = (XmmReg1[24,8] == XmmReg2[24,8]) * 0xFF;\n XmmReg1[32,8] = (XmmReg1[32,8] == XmmReg2[32,8]) * 0xFF;\n XmmReg1[40,8] = (XmmReg1[40,8] == XmmReg2[40,8]) * 0xFF;\n XmmReg1[48,8] = (XmmReg1[48,8] == XmmReg2[48,8]) * 0xFF;\n XmmReg1[56,8] = (XmmReg1[56,8] == XmmReg2[56,8]) * 0xFF;\n XmmReg1[64,8] = (XmmReg1[64,8] == XmmReg2[64,8]) * 0xFF;\n XmmReg1[72,8] = (XmmReg1[72,8] == XmmReg2[72,8]) * 0xFF;\n XmmReg1[80,8] = (XmmReg1[80,8] == XmmReg2[80,8]) * 0xFF;\n XmmReg1[88,8] = (XmmReg1[88,8] == XmmReg2[88,8]) * 0xFF;\n XmmReg1[96,8] = (XmmReg1[96,8] == XmmReg2[96,8]) * 0xFF;\n XmmReg1[104,8] = (XmmReg1[104,8] == XmmReg2[104,8]) * 0xFF;\n XmmReg1[112,8] = (XmmReg1[112,8] == XmmReg2[112,8]) * 0xFF;\n XmmReg1[120,8] = (XmmReg1[120,8] == XmmReg2[120,8]) * 0xFF;\n}\n\n:PCMPEQW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x75; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,16] = zext(XmmReg[0,16] == m[0,16]) * 0xFFFF;\n XmmReg[16,16] = zext(XmmReg[16,16] == m[16,16]) * 0xFFFF;\n XmmReg[32,16] = zext(XmmReg[32,16] == m[32,16]) * 0xFFFF;\n XmmReg[48,16] = zext(XmmReg[48,16] == m[48,16]) * 0xFFFF;\n XmmReg[64,16] = zext(XmmReg[64,16] == m[64,16]) * 0xFFFF;\n XmmReg[80,16] = zext(XmmReg[80,16] == m[80,16]) * 0xFFFF;\n XmmReg[96,16] = zext(XmmReg[96,16] == m[96,16]) * 0xFFFF;\n XmmReg[112,16] = zext(XmmReg[112,16] == m[112,16]) * 0xFFFF;\n}\n\n:PCMPEQW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x75; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,16] = zext(XmmReg1[0,16] == XmmReg2[0,16]) * 0xFFFF;\n XmmReg1[16,16] = zext(XmmReg1[16,16] == XmmReg2[16,16]) * 0xFFFF;\n XmmReg1[32,16] = zext(XmmReg1[32,16] == XmmReg2[32,16]) * 0xFFFF;\n XmmReg1[48,16] = zext(XmmReg1[48,16] == XmmReg2[48,16]) * 0xFFFF;\n XmmReg1[64,16] = zext(XmmReg1[64,16] == XmmReg2[64,16]) * 0xFFFF;\n XmmReg1[80,16] = zext(XmmReg1[80,16] == XmmReg2[80,16]) * 0xFFFF;\n XmmReg1[96,16] = zext(XmmReg1[96,16] == XmmReg2[96,16]) * 0xFFFF;\n XmmReg1[112,16] = zext(XmmReg1[112,16] == XmmReg2[112,16]) * 0xFFFF;\n}\n\n:PCMPEQD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x76; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = zext(XmmReg[0,32] == m[0,32]) * 0xFFFFFFFF;\n XmmReg[32,32] = zext(XmmReg[32,32] == m[32,32]) * 0xFFFFFFFF;\n XmmReg[64,32] = zext(XmmReg[64,32] == m[64,32]) * 0xFFFFFFFF;\n XmmReg[96,32] = zext(XmmReg[96,32] == m[96,32]) * 0xFFFFFFFF;\n}\n\n:PCMPEQD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x76; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = zext(XmmReg1[0,32] == XmmReg2[0,32]) * 0xFFFFFFFF;\n XmmReg1[32,32] = zext(XmmReg1[32,32] == XmmReg2[32,32]) * 0xFFFFFFFF;\n XmmReg1[64,32] = zext(XmmReg1[64,32] == XmmReg2[64,32]) * 0xFFFFFFFF;\n XmmReg1[96,32] = zext(XmmReg1[96,32] == XmmReg2[96,32]) * 0xFFFFFFFF;\n}\n\n:PCMPGTB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x64; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,8] = (mmxreg[0,8] s> m[0,8]) * 0xFF;\n mmxreg[8,8] = (mmxreg[8,8] s> m[8,8]) * 0xFF;\n mmxreg[16,8] = (mmxreg[16,8] s> m[16,8]) * 0xFF;\n mmxreg[24,8] = (mmxreg[24,8] s> m[24,8]) * 0xFF;\n mmxreg[32,8] = (mmxreg[32,8] s> m[32,8]) * 0xFF;\n mmxreg[40,8] = (mmxreg[40,8] s> m[40,8]) * 0xFF;\n mmxreg[48,8] = (mmxreg[48,8] s> m[48,8]) * 0xFF;\n mmxreg[56,8] = (mmxreg[56,8] s> m[56,8]) * 0xFF;\n}\n\n:PCMPGTB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x64; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,8] = (mmxreg1[0,8] s> mmxreg2[0,8]) * 0xFF;\n mmxreg1[8,8] = (mmxreg1[8,8] s> mmxreg2[8,8]) * 0xFF;\n mmxreg1[16,8] = (mmxreg1[16,8] s> mmxreg2[16,8]) * 0xFF;\n mmxreg1[24,8] = (mmxreg1[24,8] s> mmxreg2[24,8]) * 0xFF;\n mmxreg1[32,8] = (mmxreg1[32,8] s> mmxreg2[32,8]) * 0xFF;\n mmxreg1[40,8] = (mmxreg1[40,8] s> mmxreg2[40,8]) * 0xFF;\n mmxreg1[48,8] = (mmxreg1[48,8] s> mmxreg2[48,8]) * 0xFF;\n mmxreg1[56,8] = (mmxreg1[56,8] s> mmxreg2[56,8]) * 0xFF;\n}\n\n:PCMPGTW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x65; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,16] = zext(mmxreg[0,16] s> m[0,16]) * 0xFFFF;\n mmxreg[16,16] = zext(mmxreg[16,16] s> m[16,16]) * 0xFFFF;\n mmxreg[32,16] = zext(mmxreg[32,16] s> m[32,16]) * 0xFFFF;\n mmxreg[48,16] = zext(mmxreg[48,16] s> m[48,16]) * 0xFFFF;\n}\n\n:PCMPGTW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x65; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = zext(mmxreg1[0,16] s> mmxreg2[0,16]) * 0xFFFF;\n mmxreg1[16,16] = zext(mmxreg1[16,16] s> mmxreg2[16,16]) * 0xFFFF;\n mmxreg1[32,16] = zext(mmxreg1[32,16] s> mmxreg2[32,16]) * 0xFFFF;\n mmxreg1[48,16] = zext(mmxreg1[48,16] s> mmxreg2[48,16]) * 0xFFFF;\n}\n\n:PCMPGTD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x66; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,32] = zext(mmxreg[0,32] s> m[0,32]) * 0xFFFFFFFF;\n mmxreg[32,32] = zext(mmxreg[32,32] s> m[32,32]) * 0xFFFFFFFF;\n}\n\n:PCMPGTD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x66; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,32] = zext(mmxreg1[0,32] s> mmxreg2[0,32]) * 0xFFFFFFFF;\n mmxreg1[32,32] = zext(mmxreg1[32,32] s> mmxreg2[32,32]) * 0xFFFFFFFF;\n}\n\n:PCMPGTB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x64; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,8] = (XmmReg[0,8] s> m[0,8]) * 0xFF;\n XmmReg[8,8] = (XmmReg[8,8] s> m[8,8]) * 0xFF;\n XmmReg[16,8] = (XmmReg[16,8] s> m[16,8]) * 0xFF;\n XmmReg[24,8] = (XmmReg[24,8] s> m[24,8]) * 0xFF;\n XmmReg[32,8] = (XmmReg[32,8] s> m[32,8]) * 0xFF;\n XmmReg[40,8] = (XmmReg[40,8] s> m[40,8]) * 0xFF;\n XmmReg[48,8] = (XmmReg[48,8] s> m[48,8]) * 0xFF;\n XmmReg[56,8] = (XmmReg[56,8] s> m[56,8]) * 0xFF;\n XmmReg[64,8] = (XmmReg[64,8] s> m[64,8]) * 0xFF;\n XmmReg[72,8] = (XmmReg[72,8] s> m[72,8]) * 0xFF;\n XmmReg[80,8] = (XmmReg[80,8] s> m[80,8]) * 0xFF;\n XmmReg[88,8] = (XmmReg[88,8] s> m[88,8]) * 0xFF;\n XmmReg[96,8] = (XmmReg[96,8] s> m[96,8]) * 0xFF;\n XmmReg[104,8] = (XmmReg[104,8] s> m[104,8]) * 0xFF;\n XmmReg[112,8] = (XmmReg[112,8] s> m[112,8]) * 0xFF;\n XmmReg[120,8] = (XmmReg[120,8] s> m[120,8]) * 0xFF;\n}\n\n# full set of XMM byte registers\n:PCMPGTB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x64; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,8] = (XmmReg1[0,8] s> XmmReg2[0,8]) * 0xFF;\n XmmReg1[8,8] = (XmmReg1[8,8] s> XmmReg2[8,8]) * 0xFF;\n XmmReg1[16,8] = (XmmReg1[16,8] s> XmmReg2[16,8]) * 0xFF;\n XmmReg1[24,8] = (XmmReg1[24,8] s> XmmReg2[24,8]) * 0xFF;\n XmmReg1[32,8] = (XmmReg1[32,8] s> XmmReg2[32,8]) * 0xFF;\n XmmReg1[40,8] = (XmmReg1[40,8] s> XmmReg2[40,8]) * 0xFF;\n XmmReg1[48,8] = (XmmReg1[48,8] s> XmmReg2[48,8]) * 0xFF;\n XmmReg1[56,8] = (XmmReg1[56,8] s> XmmReg2[56,8]) * 0xFF;\n XmmReg1[64,8] = (XmmReg1[64,8] s> XmmReg2[64,8]) * 0xFF;\n XmmReg1[72,8] = (XmmReg1[72,8] s> XmmReg2[72,8]) * 0xFF;\n XmmReg1[80,8] = (XmmReg1[80,8] s> XmmReg2[80,8]) * 0xFF;\n XmmReg1[88,8] = (XmmReg1[88,8] s> XmmReg2[88,8]) * 0xFF;\n XmmReg1[96,8] = (XmmReg1[96,8] s> XmmReg2[96,8]) * 0xFF;\n XmmReg1[104,8] = (XmmReg1[104,8] s> XmmReg2[104,8]) * 0xFF;\n XmmReg1[112,8] = (XmmReg1[112,8] s> XmmReg2[112,8]) * 0xFF;\n XmmReg1[120,8] = (XmmReg1[120,8] s> XmmReg2[120,8]) * 0xFF;\n}\n\n:PCMPGTW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x65; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,16] = zext(XmmReg[0,16] s> m[0,16]) * 0xFFFF;\n XmmReg[16,16] = zext(XmmReg[16,16] s> m[16,16]) * 0xFFFF;\n XmmReg[32,16] = zext(XmmReg[32,16] s> m[32,16]) * 0xFFFF;\n XmmReg[48,16] = zext(XmmReg[48,16] s> m[48,16]) * 0xFFFF;\n XmmReg[64,16] = zext(XmmReg[64,16] s> m[64,16]) * 0xFFFF;\n XmmReg[80,16] = zext(XmmReg[80,16] s> m[80,16]) * 0xFFFF;\n XmmReg[96,16] = zext(XmmReg[96,16] s> m[96,16]) * 0xFFFF;\n XmmReg[112,16] = zext(XmmReg[112,16] s> m[112,16]) * 0xFFFF;\n}\n\n:PCMPGTW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x65; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,16] = zext(XmmReg1[0,16] s> XmmReg2[0,16]) * 0xFFFF;\n XmmReg1[16,16] = zext(XmmReg1[16,16] s> XmmReg2[16,16]) * 0xFFFF;\n XmmReg1[32,16] = zext(XmmReg1[32,16] s> XmmReg2[32,16]) * 0xFFFF;\n XmmReg1[48,16] = zext(XmmReg1[48,16] s> XmmReg2[48,16]) * 0xFFFF;\n XmmReg1[64,16] = zext(XmmReg1[64,16] s> XmmReg2[64,16]) * 0xFFFF;\n XmmReg1[80,16] = zext(XmmReg1[80,16] s> XmmReg2[80,16]) * 0xFFFF;\n XmmReg1[96,16] = zext(XmmReg1[96,16] s> XmmReg2[96,16]) * 0xFFFF;\n XmmReg1[112,16] = zext(XmmReg1[112,16] s> XmmReg2[112,16]) * 0xFFFF;\n}\n\n:PCMPGTD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x66; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = zext(XmmReg[0,32] s> m[0,32]) * 0xFFFFFFFF;\n XmmReg[32,32] = zext(XmmReg[32,32] s> m[32,32]) * 0xFFFFFFFF;\n XmmReg[64,32] = zext(XmmReg[64,32] s> m[64,32]) * 0xFFFFFFFF;\n XmmReg[96,32] = zext(XmmReg[96,32] s> m[96,32]) * 0xFFFFFFFF;\n}\n\n:PCMPGTD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x66; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = zext(XmmReg1[0,32] s> XmmReg2[0,32]) * 0xFFFFFFFF;\n XmmReg1[32,32] = zext(XmmReg1[32,32] s> XmmReg2[32,32]) * 0xFFFFFFFF;\n XmmReg1[64,32] = zext(XmmReg1[64,32] s> XmmReg2[64,32]) * 0xFFFFFFFF;\n XmmReg1[96,32] = zext(XmmReg1[96,32] s> XmmReg2[96,32]) * 0xFFFFFFFF;\n}\n\n:PEXTRW Reg32, mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC5; Reg32 & mmxreg2; imm8\n{\n temp:8 = mmxreg2 >> ( (imm8 & 0x03) * 16 );\n Reg32 = zext(temp:2);\n}\n\n:PEXTRW Reg32, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC5; Reg32 & XmmReg2 & check_Reg32_dest; imm8\n{\n local shift:1 = (imm8 & 0x7) * 16:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg2[0,64] >> shift, XmmReg2[64,64] >> (shift-64));\n Reg32 = zext(temp:2);\n build check_Reg32_dest;\n}\n\n#break PEXTRW with reg/mem dest into two constructors to handle zext in register case\n:PEXTRW Rmr32, XmmReg1, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x15; (mod = 3 & Rmr32 & check_Rmr32_dest) & XmmReg1 ; imm8\n{\n local shift:1 = (imm8 & 0x7) * 16:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg1[0,64] >> shift,XmmReg1[64,64] >> (shift - 64));\n Rmr32 = zext(temp:2);\n build check_Rmr32_dest;\n}\n\n:PEXTRW m16, XmmReg1, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x15; XmmReg1 ... & m16; imm8\n{\n local shift:1 = (imm8 & 0x7) * 16:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg1[0,64] >> shift,XmmReg1[64,64] >> (shift - 64));\n m16 = temp:2; \n}\n\ndefine pcodeop phaddd;\n:PHADDD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x02; mmxreg ... & m64 { mmxreg=phaddd(mmxreg,m64); }\n:PHADDD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x02; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phaddd(mmxreg1,mmxreg2); }\n:PHADDD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x02; XmmReg ... & m128 { XmmReg=phaddd(XmmReg,m128); }\n:PHADDD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x02; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phaddd(XmmReg1,XmmReg2); }\n\ndefine pcodeop phaddw;\n:PHADDW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x01; mmxreg ... & m64 { mmxreg=phaddw(mmxreg,m64); }\n:PHADDW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x01; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phaddw(mmxreg1,mmxreg2); }\n:PHADDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x01; XmmReg ... & m128 { XmmReg=phaddw(XmmReg,m128); }\n:PHADDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x01; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phaddw(XmmReg1,XmmReg2); }\n\ndefine pcodeop phaddsw;\n:PHADDSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x03; mmxreg ... & m64 { mmxreg=phaddsw(mmxreg,m64); }\n:PHADDSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x03; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phaddsw(mmxreg1,mmxreg2); }\n:PHADDSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x03; XmmReg ... & m128 { XmmReg=phaddsw(XmmReg,m128); }\n:PHADDSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x03; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phaddsw(XmmReg1,XmmReg2); }\n\ndefine pcodeop phsubd;\n:PHSUBD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x06; mmxreg ... & m64 { mmxreg=phsubd(mmxreg,m64); }\n:PHSUBD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x06; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phsubd(mmxreg1,mmxreg2); }\n:PHSUBD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x06; XmmReg ... & m128 { XmmReg=phsubd(XmmReg,m128); }\n:PHSUBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x06; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phsubd(XmmReg1,XmmReg2); }\n\ndefine pcodeop phsubw;\n:PHSUBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x05; mmxreg ... & m64 { mmxreg=phsubw(mmxreg,m64); }\n:PHSUBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x05; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phsubw(mmxreg1,mmxreg2); }\n:PHSUBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x05; XmmReg ... & m128 { XmmReg=phsubw(XmmReg,m128); }\n:PHSUBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x05; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phsubw(XmmReg1,XmmReg2); }\n\ndefine pcodeop phsubsw;\n:PHSUBSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x07; mmxreg ... & m64 { mmxreg=phsubsw(mmxreg,m64); }\n:PHSUBSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x07; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phsubsw(mmxreg1,mmxreg2); }\n:PHSUBSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x07; XmmReg ... & m128 { XmmReg=phsubsw(XmmReg,m128); }\n:PHSUBSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x07; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phsubsw(XmmReg1,XmmReg2); }\n\n:PINSRW mmxreg, Rmr32, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; mmxmod=3 & Rmr32 & mmxreg; imm8 \n{ \n local destIndex:1 = (imm8 & 0x7) * 16:1;\n mmxreg = mmxreg & ~(0xffff:8 << destIndex);\n local newVal:8 = zext(Rmr32[0,16]);\n mmxreg = mmxreg | (newVal << destIndex);\n}\n\n:PINSRW mmxreg, m16, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; m16 & mmxreg ... ; imm8 \n{ \n local destIndex:1 = (imm8 & 0x7) * 16:1;\n mmxreg = mmxreg & ~(0xffff:8 << destIndex);\n local newVal:8 = zext(m16);\n mmxreg = mmxreg | (newVal << destIndex);\n}\n\n:PINSRW XmmReg, Rmr32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC4; xmmmod=3 & Rmr32 & XmmReg; imm8 \n{ \n local destIndex:1 = (imm8 & 0x7) * 16:1;\n local useLow:1 = destIndex < 64:1;\n local newLow:8 = zext(Rmr32:2) << destIndex;\n newLow = (XmmReg[0,64] & ~(0xffff:8 << destIndex)) | newLow;\n local newHigh:8 = zext(Rmr32:2) << (destIndex-64:1);\n newHigh = (XmmReg[64,64] & ~(0xffff:8 << (destIndex - 64:1))) | newHigh;\n conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]);\n conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]);\n}\n\n:PINSRW XmmReg, m16, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC4; m16 & XmmReg ...; imm8 \n{ \n local destIndex:1 = (imm8 & 0x7) * 16:1;\n local useLow:1 = destIndex < 64:1;\n local newLow:8 = zext(m16) << destIndex;\n newLow = (XmmReg[0,64] & ~(0xffff:8 << destIndex)) | newLow;\n local newHigh:8 = zext(m16) << (destIndex-64:1);\n newHigh = (XmmReg[64,64] & ~(0xffff:8 << (destIndex - 64:1))) | newHigh;\n conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]);\n conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]);\n}\n\ndefine pcodeop pmaddubsw;\n:PMADDUBSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x04; mmxreg ... & m64 { mmxreg=pmaddubsw(mmxreg,m64); }\n:PMADDUBSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x04; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pmaddubsw(mmxreg1,mmxreg2); }\n:PMADDUBSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x04; XmmReg ... & m128 { XmmReg=pmaddubsw(XmmReg,m128); }\n:PMADDUBSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x04; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pmaddubsw(XmmReg1,XmmReg2); }\n\ndefine pcodeop pmaddwd;\n:PMADDWD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF5; mmxreg ... & m64 { mmxreg = pmaddwd(mmxreg, m64); }\n:PMADDWD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF5; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = pmaddwd(mmxreg1, mmxreg2); }\n:PMADDWD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF5; XmmReg ... & m128 { XmmReg = pmaddwd(XmmReg, m128); }\n:PMADDWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF5; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = pmaddwd(XmmReg1, XmmReg2); }\n\n:PMAXSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEE; mmxreg1 ... & mmxreg2_m64 \n{ \n local srcCopy:8 = mmxreg2_m64;\n conditionalAssign(mmxreg1[0,16],srcCopy[0,16] s> mmxreg1[0,16],srcCopy[0,16],mmxreg1[0,16]); \n conditionalAssign(mmxreg1[16,16],srcCopy[16,16] s> mmxreg1[16,16],srcCopy[16,16],mmxreg1[16,16]); \n conditionalAssign(mmxreg1[32,16],srcCopy[32,16] s> mmxreg1[32,16],srcCopy[32,16],mmxreg1[32,16]); \n conditionalAssign(mmxreg1[48,16],srcCopy[48,16] s> mmxreg1[48,16],srcCopy[48,16],mmxreg1[48,16]); \n}\n\n:PMAXSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEE; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128; \n conditionalAssign(XmmReg1[0,16],srcCopy[0,16] s> XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]);\n conditionalAssign(XmmReg1[16,16],srcCopy[16,16] s> XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]);\n conditionalAssign(XmmReg1[32,16],srcCopy[32,16] s> XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]);\n conditionalAssign(XmmReg1[48,16],srcCopy[48,16] s> XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]);\n conditionalAssign(XmmReg1[64,16],srcCopy[64,16] s> XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]);\n conditionalAssign(XmmReg1[80,16],srcCopy[80,16] s> XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]);\n conditionalAssign(XmmReg1[96,16],srcCopy[96,16] s> XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]);\n conditionalAssign(XmmReg1[112,16],srcCopy[112,16] s> XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]);\n}\n\n:PMAXUB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDE; mmxreg1 ... & mmxreg2_m64 \n{ \n local srcCopy:8 = mmxreg2_m64;\n conditionalAssign(mmxreg1[0,8],srcCopy[0,8] > mmxreg1[0,8],srcCopy[0,8],mmxreg1[0,8]); \n conditionalAssign(mmxreg1[8,8],srcCopy[8,8] > mmxreg1[8,8],srcCopy[8,8],mmxreg1[8,8]); \n conditionalAssign(mmxreg1[16,8],srcCopy[16,8] > mmxreg1[16,8],srcCopy[16,8],mmxreg1[16,8]); \n conditionalAssign(mmxreg1[24,8],srcCopy[24,8] > mmxreg1[24,8],srcCopy[24,8],mmxreg1[24,8]); \n conditionalAssign(mmxreg1[32,8],srcCopy[32,8] > mmxreg1[32,8],srcCopy[32,8],mmxreg1[32,8]); \n conditionalAssign(mmxreg1[40,8],srcCopy[40,8] > mmxreg1[40,8],srcCopy[40,8],mmxreg1[40,8]); \n conditionalAssign(mmxreg1[48,8],srcCopy[48,8] > mmxreg1[48,8],srcCopy[48,8],mmxreg1[48,8]); \n conditionalAssign(mmxreg1[56,8],srcCopy[56,8] > mmxreg1[56,8],srcCopy[56,8],mmxreg1[56,8]); \n}\n\n:PMAXUB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDE; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,8],srcCopy[0,8] > XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]); \n conditionalAssign(XmmReg1[8,8],srcCopy[8,8] > XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]); \n conditionalAssign(XmmReg1[16,8],srcCopy[16,8] > XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]); \n conditionalAssign(XmmReg1[24,8],srcCopy[24,8] > XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]); \n conditionalAssign(XmmReg1[32,8],srcCopy[32,8] > XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]); \n conditionalAssign(XmmReg1[40,8],srcCopy[40,8] > XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]); \n conditionalAssign(XmmReg1[48,8],srcCopy[48,8] > XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]); \n conditionalAssign(XmmReg1[56,8],srcCopy[56,8] > XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]); \n conditionalAssign(XmmReg1[64,8],srcCopy[64,8] > XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]); \n conditionalAssign(XmmReg1[72,8],srcCopy[72,8] > XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]); \n conditionalAssign(XmmReg1[80,8],srcCopy[80,8] > XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]); \n conditionalAssign(XmmReg1[88,8],srcCopy[88,8] > XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]); \n conditionalAssign(XmmReg1[96,8],srcCopy[96,8] > XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]); \n conditionalAssign(XmmReg1[104,8],srcCopy[104,8] > XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]); \n conditionalAssign(XmmReg1[112,8],srcCopy[112,8] > XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]); \n conditionalAssign(XmmReg1[120,8],srcCopy[120,8] > XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]); \n}\n\n:PMINSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEA; mmxreg1 ... & mmxreg2_m64 \n{ \n local srcCopy:8 = mmxreg2_m64;\n conditionalAssign(mmxreg1[0,16],srcCopy[0,16] s< mmxreg1[0,16],srcCopy[0,16],mmxreg1[0,16]); \n conditionalAssign(mmxreg1[16,16],srcCopy[16,16] s< mmxreg1[16,16],srcCopy[16,16],mmxreg1[16,16]); \n conditionalAssign(mmxreg1[32,16],srcCopy[32,16] s< mmxreg1[32,16],srcCopy[32,16],mmxreg1[32,16]); \n conditionalAssign(mmxreg1[48,16],srcCopy[48,16] s< mmxreg1[48,16],srcCopy[48,16],mmxreg1[48,16]); \n}\n\n:PMINSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEA; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128; \n conditionalAssign(XmmReg1[0,16],srcCopy[0,16] s< XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]);\n conditionalAssign(XmmReg1[16,16],srcCopy[16,16] s< XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]);\n conditionalAssign(XmmReg1[32,16],srcCopy[32,16] s< XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]);\n conditionalAssign(XmmReg1[48,16],srcCopy[48,16] s< XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]);\n conditionalAssign(XmmReg1[64,16],srcCopy[64,16] s< XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]);\n conditionalAssign(XmmReg1[80,16],srcCopy[80,16] s< XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]);\n conditionalAssign(XmmReg1[96,16],srcCopy[96,16] s< XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]);\n conditionalAssign(XmmReg1[112,16],srcCopy[112,16] s< XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]);\n}\n\n:PMINUB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDA; mmxreg1 ... & mmxreg2_m64 \n{ \n local srcCopy:8 = mmxreg2_m64;\n conditionalAssign(mmxreg1[0,8],srcCopy[0,8] < mmxreg1[0,8],srcCopy[0,8],mmxreg1[0,8]); \n conditionalAssign(mmxreg1[8,8],srcCopy[8,8] < mmxreg1[8,8],srcCopy[8,8],mmxreg1[8,8]); \n conditionalAssign(mmxreg1[16,8],srcCopy[16,8] < mmxreg1[16,8],srcCopy[16,8],mmxreg1[16,8]); \n conditionalAssign(mmxreg1[24,8],srcCopy[24,8] < mmxreg1[24,8],srcCopy[24,8],mmxreg1[24,8]); \n conditionalAssign(mmxreg1[32,8],srcCopy[32,8] < mmxreg1[32,8],srcCopy[32,8],mmxreg1[32,8]); \n conditionalAssign(mmxreg1[40,8],srcCopy[40,8] < mmxreg1[40,8],srcCopy[40,8],mmxreg1[40,8]); \n conditionalAssign(mmxreg1[48,8],srcCopy[48,8] < mmxreg1[48,8],srcCopy[48,8],mmxreg1[48,8]); \n conditionalAssign(mmxreg1[56,8],srcCopy[56,8] < mmxreg1[56,8],srcCopy[56,8],mmxreg1[56,8]); \n}\n\n:PMINUB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDA; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,8],srcCopy[0,8] < XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]); \n conditionalAssign(XmmReg1[8,8],srcCopy[8,8] < XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]); \n conditionalAssign(XmmReg1[16,8],srcCopy[16,8] < XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]); \n conditionalAssign(XmmReg1[24,8],srcCopy[24,8] < XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]); \n conditionalAssign(XmmReg1[32,8],srcCopy[32,8] < XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]); \n conditionalAssign(XmmReg1[40,8],srcCopy[40,8] < XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]); \n conditionalAssign(XmmReg1[48,8],srcCopy[48,8] < XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]); \n conditionalAssign(XmmReg1[56,8],srcCopy[56,8] < XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]); \n conditionalAssign(XmmReg1[64,8],srcCopy[64,8] < XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]); \n conditionalAssign(XmmReg1[72,8],srcCopy[72,8] < XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]); \n conditionalAssign(XmmReg1[80,8],srcCopy[80,8] < XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]); \n conditionalAssign(XmmReg1[88,8],srcCopy[88,8] < XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]); \n conditionalAssign(XmmReg1[96,8],srcCopy[96,8] < XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]); \n conditionalAssign(XmmReg1[104,8],srcCopy[104,8] < XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]); \n conditionalAssign(XmmReg1[112,8],srcCopy[112,8] < XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]); \n conditionalAssign(XmmReg1[120,8],srcCopy[120,8] < XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]); \n}\n\n#in 64-bit mode the default operand size is 64 bits\n#note that gcc assembles pmovmskb eax, mm0 and pmovmskb rax, mm0 to 0f d7 c0\n:PMOVMSKB Reg32, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD7; mod = 3 & Reg32 & mmxreg2 & check_Reg32_dest\n{ \n\tlocal byte_mask:1 = 0:1;\n\tbyte_mask[0,1] = mmxreg2[7,1];\n\tbyte_mask[1,1] = mmxreg2[15,1];\n\tbyte_mask[2,1] = mmxreg2[23,1];\n\tbyte_mask[3,1] = mmxreg2[31,1];\n\tbyte_mask[4,1] = mmxreg2[39,1];\n\tbyte_mask[5,1] = mmxreg2[47,1];\n\tbyte_mask[6,1] = mmxreg2[55,1];\n\tbyte_mask[7,1] = mmxreg2[63,1];\n\tReg32 = zext(byte_mask);\n\tbuild check_Reg32_dest;\n}\n\n#in 64-bit mode the default operand size is 64 bits\n#note that gcc assembles pmovmskb eax, xmm0 and pmovmskb rax, xmm0 to 66 0f d7 c0\n:PMOVMSKB Reg32, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD7; mod = 3 & Reg32 & XmmReg2 & check_Reg32_dest\n{ \n\tlocal byte_mask:2 = 0:2;\n\tbyte_mask[0,1] = XmmReg2[7,1];\n\tbyte_mask[1,1] = XmmReg2[15,1];\n\tbyte_mask[2,1] = XmmReg2[23,1];\n\tbyte_mask[3,1] = XmmReg2[31,1];\n\tbyte_mask[4,1] = XmmReg2[39,1];\n\tbyte_mask[5,1] = XmmReg2[47,1];\n\tbyte_mask[6,1] = XmmReg2[55,1];\n\tbyte_mask[7,1] = XmmReg2[63,1];\n\tbyte_mask[8,1] = XmmReg2[71,1];\n\tbyte_mask[9,1] = XmmReg2[79,1];\n\tbyte_mask[10,1] = XmmReg2[87,1];\n\tbyte_mask[11,1] = XmmReg2[95,1];\n\tbyte_mask[12,1] = XmmReg2[103,1];\n\tbyte_mask[13,1] = XmmReg2[111,1];\n\tbyte_mask[14,1] = XmmReg2[119,1];\n\tbyte_mask[15,1] = XmmReg2[127,1];\n\tReg32 = zext(byte_mask);\n\tbuild check_Reg32_dest;\n}\n\t\ndefine pcodeop pmulhrsw;\n:PMULHRSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0B; mmxreg ... & m64 { mmxreg=pmulhrsw(mmxreg,m64); }\n:PMULHRSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0B; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pmulhrsw(mmxreg1,mmxreg2); }\n:PMULHRSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0B; XmmReg ... & m128 { XmmReg=pmulhrsw(XmmReg,m128); }\n:PMULHRSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0B; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pmulhrsw(XmmReg1,XmmReg2); }\n\ndefine pcodeop pmulhuw;\n:PMULHUW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE4; mmxreg ... & m64 { mmxreg = pmulhuw(mmxreg, m64); }\n:PMULHUW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE4; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = pmulhuw(mmxreg1, mmxreg2); }\n:PMULHUW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE4; XmmReg ... & m128 { XmmReg = pmulhuw(XmmReg, m128); }\n:PMULHUW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE4; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = pmulhuw(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmulhw;\n:PMULHW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE5; mmxreg ... & m64 { mmxreg = pmulhw(mmxreg, m64); }\n:PMULHW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE5; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = pmulhw(mmxreg1, mmxreg2); }\n:PMULHW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE5; XmmReg ... & m128 { XmmReg = pmulhw(XmmReg, m128); }\n:PMULHW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE5; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = pmulhw(XmmReg1, XmmReg2); }\n\n:PMULLW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD5; mmxreg ... & m64 {\n local m:8 = m64;\n mmxreg[0,16] = mmxreg[0,16] * m[0,16];\n mmxreg[16,16] = mmxreg[16,16] * m[16,16];\n mmxreg[32,16] = mmxreg[32,16] * m[32,16];\n mmxreg[48,16] = mmxreg[48,16] * m[48,16];\n}\n\n:PMULLW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD5; mmxmod = 3 & mmxreg1 & mmxreg2 {\n mmxreg1[0,16] = mmxreg1[0,16] * mmxreg2[0,16];\n mmxreg1[16,16] = mmxreg1[16,16] * mmxreg2[16,16];\n mmxreg1[32,16] = mmxreg1[32,16] * mmxreg2[32,16];\n mmxreg1[48,16] = mmxreg1[48,16] * mmxreg2[48,16];\n}\n\n:PMULLW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD5; XmmReg ... & m128 {\n local m:16 = m128;\n XmmReg[0,16] = XmmReg[0,16] * m[0,16];\n XmmReg[16,16] = XmmReg[16,16] * m[16,16];\n XmmReg[32,16] = XmmReg[32,16] * m[32,16];\n XmmReg[48,16] = XmmReg[48,16] * m[48,16];\n XmmReg[64,16] = XmmReg[64,16] * m[64,16];\n XmmReg[80,16] = XmmReg[80,16] * m[80,16];\n XmmReg[96,16] = XmmReg[96,16] * m[96,16];\n XmmReg[112,16] = XmmReg[112,16] * m[112,16];\n}\n\n:PMULLW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD5; xmmmod = 3 & XmmReg1 & XmmReg2 {\n XmmReg1[0,16] = XmmReg1[0,16] * XmmReg2[0,16];\n XmmReg1[16,16] = XmmReg1[16,16] * XmmReg2[16,16];\n XmmReg1[32,16] = XmmReg1[32,16] * XmmReg2[32,16];\n XmmReg1[48,16] = XmmReg1[48,16] * XmmReg2[48,16];\n XmmReg1[64,16] = XmmReg1[64,16] * XmmReg2[64,16];\n XmmReg1[80,16] = XmmReg1[80,16] * XmmReg2[80,16];\n XmmReg1[96,16] = XmmReg1[96,16] * XmmReg2[96,16];\n XmmReg1[112,16] = XmmReg1[112,16] * XmmReg2[112,16];\n }\n\n:PMULUDQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF4; mmxreg ... & m64\n{\n local a:8 = zext(mmxreg[0,32]);\n local b:8 = zext(m64[0,32]);\n mmxreg = a * b;\n}\n\n:PMULUDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF4; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n local a:8 = zext(mmxreg1[0,32]);\n local b:8 = zext(mmxreg2[0,32]);\n mmxreg1 = a * b;\n}\n\n:PMULUDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF4; XmmReg ... & m128\n{\n local a:8 = zext(XmmReg[0,32]);\n local b:8 = zext(m128[0,32]);\n XmmReg[0,64] = a * b;\n local c:8 = zext(XmmReg[64,32]);\n local d:8 = zext(m128[64,32]);\n XmmReg[64,64] = c * d;\n}\n\n:PMULUDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF4; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n local a:8 = zext(XmmReg1[0,32]);\n local b:8 = zext(XmmReg2[0,32]);\n XmmReg1[0,64] = a * b;\n local c:8 = zext(XmmReg1[64,32]);\n local d:8 = zext(XmmReg2[64,32]);\n XmmReg1[64,64] = c * d;\n}\n\n:POR mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEB; mmxreg ... & m64\t\t\t\t{ mmxreg = mmxreg | m64; }\n:POR mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEB; mmxmod = 3 & mmxreg1 & mmxreg2\t{ mmxreg1 = mmxreg1 | mmxreg2; }\n:POR XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEB; XmmReg ... & m128\t\t\t { XmmReg = XmmReg | m128; }\n:POR XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEB; xmmmod = 3 & XmmReg1 & XmmReg2\t{ XmmReg1 = XmmReg1 | XmmReg2; }\n\ndefine pcodeop psadbw;\n:PSADBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF6; mmxreg ... & m64 { mmxreg = psadbw(mmxreg, m64); }\n:PSADBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF6; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = psadbw(mmxreg1, mmxreg2); }\n:PSADBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF6; XmmReg ... & m128 { XmmReg = psadbw(XmmReg, m128); }\n:PSADBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF6; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = psadbw(XmmReg1, XmmReg2); }\n\n# these byte and word shuffles need to be done also ?????\ndefine pcodeop pshufb;\n:PSHUFB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x00; mmxreg1 ... & mmxreg2_m64 { mmxreg1=pshufb(mmxreg1,mmxreg2_m64); }\n:PSHUFB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x00; XmmReg1 ... & XmmReg2_m128 { XmmReg1=pshufb(XmmReg1,XmmReg2_m128); }\n\n# determine the total shift required by the bit fields in a shuffle opcode\nOrder0: order0 is imm8 [ order0 = ( imm8 & 0x3); ] { export *[const]:1 order0; }\nOrder1: order1 is imm8 [ order1 = ((imm8 >> 2) & 0x3); ] { export *[const]:1 order1; }\nOrder2: order2 is imm8 [ order2 = ((imm8 >> 4) & 0x3); ] { export *[const]:1 order2; }\nOrder3: order3 is imm8 [ order3 = ((imm8 >> 6) & 0x3); ] { export *[const]:1 order3; }\n\nmacro shuffle_4(dest,ord,c0,c1,c2,c3){\n dest = zext(ord == 0) * c0 + zext(ord == 1) * c1 + zext(ord == 2) * c2 + zext(ord == 3) * c3;\n}\n\n:PSHUFD XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x70; (XmmReg2_m128 & XmmReg1 ...); imm8 & Order0 & Order1 & Order2 & Order3\n{\n local c0 = XmmReg2_m128[0,32];\n local c1 = XmmReg2_m128[32,32];\n local c2 = XmmReg2_m128[64,32];\n local c3 = XmmReg2_m128[96,32];\n\n shuffle_4(XmmReg1[0,32],Order0,c0,c1,c2,c3);\n shuffle_4(XmmReg1[32,32],Order1,c0,c1,c2,c3);\n shuffle_4(XmmReg1[64,32],Order2,c0,c1,c2,c3);\n shuffle_4(XmmReg1[96,32],Order3,c0,c1,c2,c3);\n}\n\ndefine pcodeop pshufhw;\n:PSHUFHW XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x70; XmmReg2_m128 & XmmReg1 ...; imm8 { XmmReg1 = pshufhw(XmmReg1, XmmReg2_m128, imm8:8); }\n\ndefine pcodeop pshuflw;\n:PSHUFLW XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x70; XmmReg2_m128 & XmmReg1 ...; imm8 { XmmReg1 = pshuflw(XmmReg1, XmmReg2_m128, imm8:8); }\n\ndefine pcodeop pshufw;\n:PSHUFW mmxreg1, mmxreg2_m64, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x70; mmxreg2_m64 & mmxreg1 ...; imm8 { mmxreg1 = pshufw(mmxreg1, mmxreg2_m64, imm8:8); }\n\ndefine pcodeop psignb;\n:PSIGNB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x08; mmxreg ... & m64 { mmxreg=psignb(mmxreg,m64); }\n:PSIGNB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x08; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=psignb(mmxreg1,mmxreg2); }\n:PSIGNB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x08; XmmReg ... & m128 { XmmReg=psignb(XmmReg,m128); }\n:PSIGNB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x08; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=psignb(XmmReg1,XmmReg2); }\n\ndefine pcodeop psignw;\n:PSIGNW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x09; mmxreg ... & m64 { mmxreg=psignw(mmxreg,m64); }\n:PSIGNW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x09; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=psignw(mmxreg1,mmxreg2); }\n:PSIGNW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x09; XmmReg ... & m128 { XmmReg=psignw(XmmReg,m128); }\n:PSIGNW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x09; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=psignw(XmmReg1,XmmReg2); }\n\ndefine pcodeop psignd;\n:PSIGND mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0a; mmxreg ... & m64 { mmxreg=psignd(mmxreg,m64); }\n:PSIGND mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0a; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=psignd(mmxreg1,mmxreg2); }\n:PSIGND XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0a; XmmReg ... & m128 { XmmReg=psignd(XmmReg,m128); }\n:PSIGND XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0a; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=psignd(XmmReg1,XmmReg2); }\n\n#break into two 64-bit chunks so decompiler can follow constants\n:PSLLDQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; xmmmod = 3 & reg_opcode=7 & XmmReg2; imm8 \n{ \n\tif (imm8:1 > 15:1) goto ;\n local low64copy:8 = XmmReg2[0,64];\n XmmReg2[0,64] = XmmReg2[0,64] << (8:1 * imm8:1);\n if (imm8:1 > 8:1) goto ;\n XmmReg2[64,64] = (XmmReg2[64,64] << (8:1 * imm8:1)) | (low64copy >> (8:1 * (8 - imm8:1)));\n goto ;\n\n XmmReg2[64,64] = low64copy << (8:1 * (imm8 - 8));\n goto ;\n\n XmmReg2[0,64] = 0:8;\n XmmReg2[64,64] = 0:8;\n\n}\n\ndefine pcodeop psllw;\n:PSLLW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF1; mmxreg ... & m64 ... { mmxreg = psllw(mmxreg, m64); }\n:PSLLW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF1; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = psllw(mmxreg1, mmxreg2); }\n:PSLLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { mmxreg2 = psllw(mmxreg2, imm8:8); }\n\n:PSLLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxreg ... & m64 ... {\n local m:8 = m64;\n mmxreg[0,32] = mmxreg[0,32] << m[0,32];\n mmxreg[32,32] = mmxreg[32,32] << m[32,32];\n}\n\n:PSLLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxmod = 3 & mmxreg1 & mmxreg2 {\n mmxreg1[0,32] = mmxreg1[0,32] << mmxreg2[0,32];\n mmxreg1[32,32] = mmxreg1[32,32] << mmxreg2[32,32];\n}\n\n:PSLLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 {\n mmxreg2[0,32] = mmxreg2[0,32] << imm8;\n mmxreg2[32,32] = mmxreg2[32,32] << imm8;\n}\n\n:PSLLQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF3; mmxreg ... & m64 ... { mmxreg = mmxreg << m64; }\n:PSLLQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF3; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg1 << mmxreg2; }\n:PSLLQ mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { mmxreg2 = mmxreg2 << imm8:8; }\n\n:PSLLW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF1; XmmReg ... & m128 ... { XmmReg = psllw(XmmReg, m128); }\n:PSLLW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF1; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = psllw(XmmReg1, XmmReg2); }\n:PSLLW XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 { XmmReg2 = psllw(XmmReg2, imm8:8); }\n\n:PSLLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; XmmReg ... & m128 ... {\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] << m[0,32];\n XmmReg[32,32] = XmmReg[32,32] << m[32,32];\n XmmReg[64,32] = XmmReg[64,32] << m[64,32];\n XmmReg[96,32] = XmmReg[96,32] << m[96,32];\n}\n\n:PSLLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; xmmmod = 3 & XmmReg1 & XmmReg2 {\n XmmReg1[0,32] = XmmReg1[0,32] << XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] << XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] << XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] << XmmReg2[96,32];\n}\n\n:PSLLD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 {\n XmmReg2[0,32] = XmmReg2[0,32] << imm8;\n XmmReg2[32,32] = XmmReg2[32,32] << imm8;\n XmmReg2[64,32] = XmmReg2[64,32] << imm8;\n XmmReg2[96,32] = XmmReg2[96,32] << imm8;\n}\n \n:PSLLQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF3; XmmReg ... & m128 ... {\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] << m[0,64];\n XmmReg[64,64] = XmmReg[64,64] << m[64,64];\n}\n\n:PSLLQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF3; xmmmod = 3 & XmmReg1 & XmmReg2 {\n XmmReg1[0,64] = XmmReg1[0,64] << XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] << XmmReg2[64,64];\n}\n\n:PSLLQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 {\n XmmReg2[0,64] = XmmReg2[0,64] << imm8;\n XmmReg2[64,64] = XmmReg2[64,64] << imm8;\n}\n\ndefine pcodeop psraw;\n:PSRAW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE1; mmxreg ... & m64 ... { mmxreg = psraw(mmxreg, m64); }\n:PSRAW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE1; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = psraw(mmxreg1, mmxreg2); }\n:PSRAW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=4 & mmxreg2; imm8 { mmxreg2 = psraw(mmxreg2, imm8:8); }\n \n:PSRAD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE2; mmxreg ... & m64\n{\n# a count greater than 31 just clears all the bits\n mmxreg[0,32] = mmxreg[0,32] s>> m64;\n mmxreg[32,32] = mmxreg[32,32] s>> m64;\n}\n\n:PSRAD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE2; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n# a count greater than 31 just clears all the bits\n mmxreg1[0,32] = mmxreg1[0,32] s>> mmxreg2;\n mmxreg1[32,32] = mmxreg1[32,32] s>> mmxreg2;\n}\n\n:PSRAD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=4 & mmxreg2; imm8\n{\n# a count greater than 31 just clears all the bits\n mmxreg2[0,32] = mmxreg2[0,32] s>> imm8;\n mmxreg2[32,32] = mmxreg2[32,32] s>> imm8;\n}\n\n:PSRAW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE1; XmmReg ... & m128 ... { XmmReg = psraw(XmmReg, m128); }\n:PSRAW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE1; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = psraw(XmmReg1, XmmReg2); }\n:PSRAW XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=4 & XmmReg2; imm8 { XmmReg2 = psraw(XmmReg2, imm8:8); }\n \n:PSRAD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE2; m128 & XmmReg ...\n{\n# a count greater than 31 just clears all the bits\n XmmReg[0,32] = XmmReg[0,32] s>> m128;\n XmmReg[32,32] = XmmReg[32,32] s>> m128;\n XmmReg[64,32] = XmmReg[64,32] s>> m128;\n XmmReg[96,32] = XmmReg[96,32] s>> m128;\n}\n\n:PSRAD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE2; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n# a count greater than 31 just clears all the bits\n XmmReg1[0,32] = XmmReg1[0,32] s>> XmmReg2;\n XmmReg1[32,32] = XmmReg1[32,32] s>> XmmReg2;\n XmmReg1[64,32] = XmmReg1[64,32] s>> XmmReg2;\n XmmReg1[96,32] = XmmReg1[96,32] s>> XmmReg2;\n}\n\n:PSRAD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=4 & XmmReg2; imm8\n{\n# a count greater than 31 just clears all the bits\n XmmReg2[0,32] = XmmReg2[0,32] s>> imm8;\n XmmReg2[32,32] = XmmReg2[32,32] s>> imm8;\n XmmReg2[64,32] = XmmReg2[64,32] s>> imm8;\n XmmReg2[96,32] = XmmReg2[96,32] s>> imm8;\n}\n\n:PSRLDQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; xmmmod=3 & reg_opcode=3 & XmmReg2; imm8\n{\n# a count greater than 15 just clears all the bits\n XmmReg2 = XmmReg2 >> (imm8 * 8);\n}\n\n:PSRLW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD1; mmxreg ... & m64 ...\n{\n mmxreg[0,16] = mmxreg[0,16] >> m64;\n mmxreg[16,16] = mmxreg[16,16] >> m64;\n mmxreg[32,16] = mmxreg[32,16] >> m64;\n mmxreg[48,16] = mmxreg[48,16] >> m64;\n}\n\n:PSRLW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD1; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = mmxreg1[0,16] >> mmxreg2;\n mmxreg1[16,16] = mmxreg1[16,16] >> mmxreg2;\n mmxreg1[32,16] = mmxreg1[32,16] >> mmxreg2;\n mmxreg1[48,16] = mmxreg1[48,16] >> mmxreg2;\n}\n\n:PSRLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=2 & mmxreg2; imm8\n{\n mmxreg2[0,16] = mmxreg2[0,16] >> imm8;\n mmxreg2[16,16] = mmxreg2[16,16] >> imm8;\n mmxreg2[32,16] = mmxreg2[32,16] >> imm8;\n mmxreg2[48,16] = mmxreg2[48,16] >> imm8;\n}\n \n:PSRLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD2; mmxreg ... & m64 ...\n{\n mmxreg[0,32] = mmxreg[0,32] >> m64;\n mmxreg[32,32] = mmxreg[32,32] >> m64;\n}\n\n:PSRLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD2; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,32] = mmxreg1[0,32] >> mmxreg2;\n mmxreg1[32,32] = mmxreg1[32,32] >> mmxreg2;\n}\n\n:PSRLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=2 & mmxreg2; imm8\n{\n mmxreg2[0,32] = mmxreg2[0,32] >> imm8;\n mmxreg2[32,32] = mmxreg2[32,32] >> imm8;\n}\n\n:PSRLQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD3; mmxreg ... & m64 ...\n{\n mmxreg = mmxreg >> m64;\n }\n\n:PSRLQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD3; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1 = mmxreg1 >> mmxreg2;\n}\n\n:PSRLQ mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=2 & mmxreg2; imm8\n{\n mmxreg2 = mmxreg2 >> imm8;\n}\n \n:PSRLW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD1; XmmReg ... & m128 ...\n{\n XmmReg[0,16] = XmmReg[0,16] >> m128[0,64];\n XmmReg[16,16] = XmmReg[16,16] >> m128[0,64];\n XmmReg[32,16] = XmmReg[32,16] >> m128[0,64];\n XmmReg[48,16] = XmmReg[48,16] >> m128[0,64];\n XmmReg[64,16] = XmmReg[64,16] >> m128[0,64];\n XmmReg[80,16] = XmmReg[80,16] >> m128[0,64];\n XmmReg[96,16] = XmmReg[96,16] >> m128[0,64];\n XmmReg[112,16] = XmmReg[112,16] >> m128[0,64];\n}\n\n:PSRLW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD1; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n #save this off in case XmmReg1 and XmmReg2 are the same register\n local count:8 = XmmReg2[0,64];\n \n XmmReg1[0,16] = XmmReg1[0,16] >> count;\n XmmReg1[16,16] = XmmReg1[16,16] >> count;\n XmmReg1[32,16] = XmmReg1[32,16] >> count;\n XmmReg1[48,16] = XmmReg1[48,16] >> count;\n XmmReg1[64,16] = XmmReg1[64,16] >> count;\n XmmReg1[80,16] = XmmReg1[80,16] >> count;\n XmmReg1[96,16] = XmmReg1[96,16] >> count;\n XmmReg1[112,16] = XmmReg1[112,16] >> count;\n}\n\n:PSRLW XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=2 & XmmReg2; imm8\n{\n XmmReg2[0,16] = XmmReg2[0,16] >> imm8;\n XmmReg2[16,16] = XmmReg2[16,16] >> imm8;\n XmmReg2[32,16] = XmmReg2[32,16] >> imm8;\n XmmReg2[48,16] = XmmReg2[48,16] >> imm8;\n XmmReg2[64,16] = XmmReg2[64,16] >> imm8;\n XmmReg2[80,16] = XmmReg2[80,16] >> imm8;\n XmmReg2[96,16] = XmmReg2[96,16] >> imm8;\n XmmReg2[112,16] = XmmReg2[112,16] >> imm8;\n}\n\n:PSRLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD2; XmmReg ... & m128 ...\n{\n XmmReg[0,32] = XmmReg[0,32] >> m128[0,64];\n XmmReg[32,32] = XmmReg[32,32] >> m128[0,64];\n XmmReg[64,32] = XmmReg[64,32] >> m128[0,64];\n XmmReg[96,32] = XmmReg[96,32] >> m128[0,64];\n}\n\n:PSRLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD2; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n #save this off in case XmmReg1 and XmmReg2 are the same register\n local count = XmmReg2[0,64];\n \n XmmReg1[0,32] = XmmReg1[0,32] >> count;\n XmmReg1[32,32] = XmmReg1[32,32] >> count;\n XmmReg1[64,32] = XmmReg1[64,32] >> count;\n XmmReg1[96,32] = XmmReg1[96,32] >> count;\n}\n\n:PSRLD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=2 & XmmReg2; imm8\n{\n XmmReg2[0,32] = XmmReg2[0,32] >> imm8;\n XmmReg2[32,32] = XmmReg2[32,32] >> imm8;\n XmmReg2[64,32] = XmmReg2[64,32] >> imm8;\n XmmReg2[96,32] = XmmReg2[96,32] >> imm8;\n}\n \n:PSRLQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD3; XmmReg ... & m128 ...\n{\n XmmReg[0,64] = XmmReg[0,64] >> m128[0,64];\n XmmReg[64,64] = XmmReg[64,64] >> m128[0,64];\n}\n\n:PSRLQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD3; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n #save this off in case XmmReg1 and XmmReg2 are the same register\n local count = XmmReg2[0,64];\n \n XmmReg1[0,64] = XmmReg1[0,64] >> count;\n XmmReg1[64,64] = XmmReg1[64,64] >> count;\n}\n\n:PSRLQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=2 & XmmReg2; imm8\n{\n XmmReg2[0,64] = XmmReg2[0,64] >> imm8;\n XmmReg2[64,64] = XmmReg2[64,64] >> imm8;\n}\n\n:PSUBB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF8; mmxreg ... & m64 ...\n{\n local m:8 = m64;\n mmxreg[0,8] = mmxreg[0,8] - m[0,8];\n mmxreg[8,8] = mmxreg[8,8] - m[8,8];\n mmxreg[16,8] = mmxreg[16,8] - m[16,8];\n mmxreg[24,8] = mmxreg[24,8] - m[24,8];\n mmxreg[32,8] = mmxreg[32,8] - m[32,8];\n mmxreg[40,8] = mmxreg[40,8] - m[40,8];\n mmxreg[48,8] = mmxreg[48,8] - m[48,8];\n mmxreg[56,8] = mmxreg[56,8] - m[56,8];\n}\n\n:PSUBB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF8; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,8] = mmxreg1[0,8] - mmxreg2[0,8];\n mmxreg1[16,8] = mmxreg1[16,8] - mmxreg2[16,8];\n mmxreg1[24,8] = mmxreg1[24,8] - mmxreg2[24,8];\n mmxreg1[32,8] = mmxreg1[32,8] - mmxreg2[32,8];\n mmxreg1[40,8] = mmxreg1[40,8] - mmxreg2[40,8];\n mmxreg1[48,8] = mmxreg1[48,8] - mmxreg2[48,8];\n mmxreg1[56,8] = mmxreg1[56,8] - mmxreg2[56,8];\n}\n \n:PSUBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF9; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,16] = mmxreg[0,16] - m[0,16];\n mmxreg[16,16] = mmxreg[16,16] - m[16,16];\n mmxreg[32,16] = mmxreg[32,16] - m[32,16];\n mmxreg[48,16] = mmxreg[48,16] - m[48,16];\n}\n\n:PSUBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF9; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = mmxreg1[0,16] - mmxreg2[0,16];\n mmxreg1[16,16] = mmxreg1[16,16] - mmxreg2[16,16];\n mmxreg1[32,16] = mmxreg1[32,16] - mmxreg2[32,16];\n mmxreg1[48,16] = mmxreg1[48,16] - mmxreg2[48,16];\n}\n \n:PSUBD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFA; mmxreg ... & m64 ...\n{\n\tlocal m:8 = m64;\n\tmmxreg[0,32] = mmxreg[0,32] - m[0,32];\n\tmmxreg[32,32] = mmxreg[32,32] - m[32,32];\n}\n\n:PSUBD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFA; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n\tmmxreg1[0,32] = mmxreg1[0,32] - mmxreg2[0,32];\n\tmmxreg1[32,32] = mmxreg1[32,32] - mmxreg2[32,32];\n}\n\n:PSUBQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFB; mmxreg ... & m64 ...\t\t\t{ mmxreg = mmxreg - m64; }\n:PSUBQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFB; mmxmod = 3 & mmxreg1 & mmxreg2\t\t{ mmxreg1 = mmxreg1 - mmxreg2; }\n:PSUBQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFB; XmmReg ... & m128 ...\n{\n\tlocal m:16 = m128;\n\tXmmReg[0,64] = XmmReg[0,64] - m[0,64];\n\tXmmReg[64,64] = XmmReg[64,64] - m[64,64];\n}\n\n:PSUBQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFB; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n\tXmmReg1[0,64] = XmmReg1[0,64] - XmmReg2[0,64];\n\tXmmReg1[64,64] = XmmReg1[64,64] - XmmReg2[64,64];\n}\n\n:PSUBB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF8; XmmReg ... & m128 ...\n{\n local m:16 = m128;\n XmmReg[0,8] = XmmReg[0,8] - m[0,8];\n XmmReg[8,8] = XmmReg[8,8] - m[8,8];\n XmmReg[16,8] = XmmReg[16,8] - m[16,8];\n XmmReg[24,8] = XmmReg[24,8] - m[24,8];\n XmmReg[32,8] = XmmReg[32,8] - m[32,8];\n XmmReg[40,8] = XmmReg[40,8] - m[40,8];\n XmmReg[48,8] = XmmReg[48,8] - m[48,8];\n XmmReg[56,8] = XmmReg[56,8] - m[56,8];\n XmmReg[64,8] = XmmReg[64,8] - m[64,8];\n XmmReg[72,8] = XmmReg[72,8] - m[72,8];\n XmmReg[80,8] = XmmReg[80,8] - m[80,8];\n XmmReg[88,8] = XmmReg[88,8] - m[88,8];\n XmmReg[96,8] = XmmReg[96,8] - m[96,8];\n XmmReg[104,8] = XmmReg[104,8] - m[104,8];\n XmmReg[112,8] = XmmReg[112,8] - m[112,8];\n XmmReg[120,8] = XmmReg[120,8] - m[120,8];\n}\n\n:PSUBB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF8; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,8] = XmmReg1[0,8] - XmmReg2[0,8];\n XmmReg1[8,8] = XmmReg1[8,8] - XmmReg2[8,8];\n XmmReg1[16,8] = XmmReg1[16,8] - XmmReg2[16,8];\n XmmReg1[24,8] = XmmReg1[24,8] - XmmReg2[24,8];\n XmmReg1[32,8] = XmmReg1[32,8] - XmmReg2[32,8];\n XmmReg1[40,8] = XmmReg1[40,8] - XmmReg2[40,8];\n XmmReg1[48,8] = XmmReg1[48,8] - XmmReg2[48,8];\n XmmReg1[56,8] = XmmReg1[56,8] - XmmReg2[56,8];\n XmmReg1[64,8] = XmmReg1[64,8] - XmmReg2[64,8];\n XmmReg1[72,8] = XmmReg1[72,8] - XmmReg2[72,8];\n XmmReg1[80,8] = XmmReg1[80,8] - XmmReg2[80,8];\n XmmReg1[88,8] = XmmReg1[88,8] - XmmReg2[88,8];\n XmmReg1[96,8] = XmmReg1[96,8] - XmmReg2[96,8];\n XmmReg1[104,8] = XmmReg1[104,8] - XmmReg2[104,8];\n XmmReg1[112,8] = XmmReg1[112,8] - XmmReg2[112,8];\n XmmReg1[120,8] = XmmReg1[120,8] - XmmReg2[120,8];\n}\n \n:PSUBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF9; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,16] = XmmReg[0,16] - m[0,16];\n XmmReg[16,16] = XmmReg[16,16] - m[16,16];\n XmmReg[32,16] = XmmReg[32,16] - m[32,16];\n XmmReg[48,16] = XmmReg[48,16] - m[48,16];\n XmmReg[64,16] = XmmReg[64,16] - m[64,16];\n XmmReg[80,16] = XmmReg[80,16] - m[80,16];\n XmmReg[96,16] = XmmReg[96,16] - m[96,16];\n XmmReg[112,16] = XmmReg[112,16] - m[112,16];\n}\n\n:PSUBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF9; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,16] = XmmReg1[0,16] - XmmReg2[0,16];\n XmmReg1[16,16] = XmmReg1[16,16] - XmmReg2[16,16];\n XmmReg1[32,16] = XmmReg1[32,16] - XmmReg2[32,16];\n XmmReg1[48,16] = XmmReg1[48,16] - XmmReg2[48,16];\n XmmReg1[64,16] = XmmReg1[64,16] - XmmReg2[64,16];\n XmmReg1[80,16] = XmmReg1[80,16] - XmmReg2[80,16];\n XmmReg1[96,16] = XmmReg1[96,16] - XmmReg2[96,16];\n XmmReg1[112,16] = XmmReg1[112,16] - XmmReg2[112,16];\n}\n \n:PSUBD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFA; XmmReg ... & m128 ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] - m[0,32];\n XmmReg[32,32] = XmmReg[32,32] - m[32,32];\n XmmReg[64,32] = XmmReg[64,32] - m[64,32];\n XmmReg[96,32] = XmmReg[96,32] - m[96,32];\n}\n\n:PSUBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFA; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] - XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] - XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] - XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] - XmmReg2[96,32];\n}\n\ndefine pcodeop psubsb;\n:PSUBSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE8; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubsb(mmxreg1, mmxreg2_m64); }\n\ndefine pcodeop psubsw;\n:PSUBSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE9; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubsw(mmxreg1, mmxreg2_m64); }\n\n:PSUBSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE8; XmmReg1 ... & XmmReg2_m128 ... { XmmReg1 = psubsb(XmmReg1, XmmReg2_m128); }\n\n:PSUBSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE9; XmmReg1 ... & XmmReg2_m128 ... { XmmReg1 = psubsw(XmmReg1, XmmReg2_m128); }\n\ndefine pcodeop psubusb;\n:PSUBUSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD8; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubusb(mmxreg1, mmxreg2_m64); }\n\ndefine pcodeop psubusw;\n:PSUBUSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD9; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubusw(mmxreg1, mmxreg2_m64); }\n\n:PSUBUSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD8; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = psubusb(XmmReg1, XmmReg2_m128); }\n\n:PSUBUSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD9; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = psubusw(XmmReg1, XmmReg2_m128); }\n\n:PUNPCKHBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x68; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,8] = mmxreg[32,8];\n mmxreg[8,8] = m[32,8];\n mmxreg[16,8] = mmxreg[40,8];\n mmxreg[24,8] = m[40,8];\n mmxreg[32,8] = mmxreg[48,8];\n mmxreg[40,8] = m[48,8];\n mmxreg[48,8] = mmxreg[56,8];\n mmxreg[56,8] = m[56,8];\n}\n\n:PUNPCKHBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x68; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,8] = mmxreg1[32,8];\n mmxreg1[8,8] = mmxreg2[32,8];\n mmxreg1[16,8] = mmxreg1[40,8];\n mmxreg1[24,8] = mmxreg2[40,8];\n mmxreg1[32,8] = mmxreg1[48,8];\n mmxreg1[40,8] = mmxreg2[48,8];\n mmxreg1[48,8] = mmxreg1[56,8];\n mmxreg1[56,8] = mmxreg2[56,8];\n}\n \n:PUNPCKHWD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x69; mmxreg ... & m64\n{\n local m:8 = m64;\n mmxreg[0,16] = mmxreg[32,16];\n mmxreg[16,16] = m[32,16];\n mmxreg[32,16] = mmxreg[48,16];\n mmxreg[48,16] = m[48,16];\n}\n\n:PUNPCKHWD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x69; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,16] = mmxreg1[32,16];\n mmxreg1[16,16] = mmxreg2[32,16];\n mmxreg1[32,16] = mmxreg1[48,16];\n mmxreg1[48,16] = mmxreg2[48,16];\n}\n \n:PUNPCKHDQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6A; mmxreg ... & m64\n{\n mmxreg[0,32] = mmxreg[32,32];\n mmxreg[32,32] = m64[32,32];\n}\n\n:PUNPCKHDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6A; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[0,32] = mmxreg1[32,32];\n mmxreg1[32,32] = mmxreg2[32,32];\n}\n\n:PUNPCKHBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x68; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,8] = XmmReg[64,8];\n XmmReg[8,8] = m[64,8];\n XmmReg[16,8] = XmmReg[72,8];\n XmmReg[24,8] = m[72,8];\n XmmReg[32,8] = XmmReg[80,8];\n XmmReg[40,8] = m[80,8];\n XmmReg[48,8] = XmmReg[88,8];\n XmmReg[56,8] = m[88,8];\n XmmReg[64,8] = XmmReg[96,8];\n XmmReg[72,8] = m[96,8];\n XmmReg[80,8] = XmmReg[104,8];\n XmmReg[88,8] = m[104,8];\n XmmReg[96,8] = XmmReg[112,8];\n XmmReg[104,8] = m[112,8];\n XmmReg[112,8] = XmmReg[120,8];\n XmmReg[120,8] = m[120,8];\n}\n\n# full set of XMM byte registers\n:PUNPCKHBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x68; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,8] = XmmReg1[64,8];\n XmmReg1[8,8] = XmmReg2[64,8];\n XmmReg1[16,8] = XmmReg1[72,8];\n XmmReg1[24,8] = XmmReg2[72,8];\n XmmReg1[32,8] = XmmReg1[80,8];\n XmmReg1[40,8] = XmmReg2[80,8];\n XmmReg1[48,8] = XmmReg1[88,8];\n XmmReg1[56,8] = XmmReg2[88,8];\n XmmReg1[64,8] = XmmReg1[96,8];\n XmmReg1[72,8] = XmmReg2[96,8];\n XmmReg1[80,8] = XmmReg1[104,8];\n XmmReg1[88,8] = XmmReg2[104,8];\n XmmReg1[96,8] = XmmReg1[112,8];\n XmmReg1[104,8] = XmmReg2[112,8];\n XmmReg1[112,8] = XmmReg1[120,8];\n XmmReg1[120,8] = XmmReg2[120,8];\n}\n \n:PUNPCKHWD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x69; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,16] = XmmReg[64,16];\n XmmReg[16,16] = m[64,16];\n XmmReg[32,16] = XmmReg[80,16];\n XmmReg[48,16] = m[80,16];\n XmmReg[64,16] = XmmReg[96,16];\n XmmReg[80,16] = m[96,16];\n XmmReg[96,16] = XmmReg[112,16];\n XmmReg[112,16] = m[112,16];\n}\n\n:PUNPCKHWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x69; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,16] = XmmReg1[64,16];\n XmmReg1[16,16] = XmmReg2[64,16];\n XmmReg1[32,16] = XmmReg1[80,16];\n XmmReg1[48,16] = XmmReg2[80,16];\n XmmReg1[64,16] = XmmReg1[96,16];\n XmmReg1[80,16] = XmmReg2[96,16];\n XmmReg1[96,16] = XmmReg1[112,16];\n XmmReg1[112,16] = XmmReg2[112,16];\n}\n \n:PUNPCKHDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6A; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[64,32];\n XmmReg[32,32] = m[64,32];\n XmmReg[64,32] = XmmReg[96,32];\n XmmReg[96,32] = m[96,32];\n}\n\n:PUNPCKHDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6A; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[64,32];\n XmmReg1[32,32] = XmmReg2[64,32];\n XmmReg1[64,32] = XmmReg1[96,32];\n XmmReg1[96,32] = XmmReg2[96,32];\n}\n\n:PUNPCKHQDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6D; m128 & XmmReg ...\n{\n XmmReg[0,64] = XmmReg[64,64];\n XmmReg[64,64] = m128[64,64];\n}\n\n:PUNPCKHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6D; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[64,64];\n XmmReg1[64,64] = XmmReg2[64,64];\n}\n\n:PUNPCKLBW mmxreg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x60; mmxreg ... & m32\n{\n local m:4 = m32;\n mmxreg[56,8] = m[24,8];\n mmxreg[48,8] = mmxreg[24,8];\n mmxreg[40,8] = m[16,8];\n mmxreg[32,8] = mmxreg[16,8];\n mmxreg[24,8] = m[8,8];\n mmxreg[16,8] = mmxreg[8,8];\n mmxreg[8,8] = m[0,8];\n# mmxreg[0,8] = mmxreg[0,8]; superfluous\n}\n \n:PUNPCKLBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x60; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[56,8] = mmxreg2[24,8];\n mmxreg1[48,8] = mmxreg1[24,8];\n mmxreg1[40,8] = mmxreg2[16,8];\n mmxreg1[32,8] = mmxreg1[16,8];\n mmxreg1[24,8] = mmxreg2[8,8];\n mmxreg1[16,8] = mmxreg1[8,8];\n mmxreg1[8,8] = mmxreg2[0,8];\n# mmxreg1[0,8] = mmxreg1[0,8]; superfluous\n}\n \n:PUNPCKLWD mmxreg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x61; mmxreg ... & m32\n{\n local m:4 = m32;\n mmxreg[48,16] = m[16,16];\n mmxreg[32,16] = mmxreg[16,16];\n mmxreg[16,16] = m[0,16];\n# mmxreg[0,16] = mmxreg[0,16]; superfluous\n}\n\n:PUNPCKLWD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x61; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[48,16] = mmxreg2[16,16];\n mmxreg1[32,16] = mmxreg1[16,16];\n mmxreg1[16,16] = mmxreg2[0,16];\n# mmxreg1[0,16] = mmxreg1[0,16]; superfluous\n}\n\n:PUNPCKLDQ mmxreg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x62; mmxreg ... & m32\n{\n mmxreg[32,32] = m32;\n# mmxreg[0,32] = mmxreg[0,32]; superfluous\n}\n\n:PUNPCKLDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x62; mmxmod = 3 & mmxreg1 & mmxreg2\n{\n mmxreg1[32,32] = mmxreg2[0,32];\n# mmxreg1[0,32] = mmxreg1[0,32]; superfluous\n}\n\n:PUNPCKLBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x60; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[120,8] = m[56,8];\n XmmReg[112,8] = XmmReg[56,8];\n XmmReg[104,8] = m[48,8];\n XmmReg[96,8] = XmmReg[48,8];\n XmmReg[88,8] = m[40,8];\n XmmReg[80,8] = XmmReg[40,8];\n XmmReg[72,8] = m[32,8];\n XmmReg[64,8] = XmmReg[32,8];\n XmmReg[56,8] = m[24,8];\n XmmReg[48,8] = XmmReg[24,8];\n XmmReg[40,8] = m[16,8];\n XmmReg[32,8] = XmmReg[16,8];\n XmmReg[24,8] = m[8,8];\n XmmReg[16,8] = XmmReg[8,8];\n XmmReg[8,8] = m[0,8];\n# XmmReg[0,8] = XmmReg[0,8]; superfluous\n}\n\n:PUNPCKLBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x60; xmmmod = 3 &\nXmmReg1 & XmmReg2\n{\n XmmReg1[120,8] = XmmReg2[56,8];\n XmmReg1[112,8] = XmmReg1[56,8];\n XmmReg1[104,8] = XmmReg2[48,8];\n XmmReg1[96,8] = XmmReg1[48,8];\n XmmReg1[88,8] = XmmReg2[40,8];\n XmmReg1[80,8] = XmmReg1[40,8];\n XmmReg1[72,8] = XmmReg2[32,8];\n XmmReg1[64,8] = XmmReg1[32,8];\n XmmReg1[56,8] = XmmReg2[24,8];\n XmmReg1[48,8] = XmmReg1[24,8];\n XmmReg1[40,8] = XmmReg2[16,8];\n XmmReg1[32,8] = XmmReg1[16,8];\n XmmReg1[24,8] = XmmReg2[8,8];\n XmmReg1[16,8] = XmmReg1[8,8];\n XmmReg1[8,8] = XmmReg2[0,8];\n# XmmReg1[0,8] = XmmReg1[0,8]; superfluous\n}\n\n:PUNPCKLWD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x61; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[112,16] = m[48,16];\n XmmReg[96,16] = XmmReg[48,16];\n XmmReg[80,16] = m[32,16];\n XmmReg[64,16] = XmmReg[32,16];\n XmmReg[48,16] = m[16,16];\n XmmReg[32,16] = XmmReg[16,16];\n XmmReg[16,16] = m[0,16];\n# XmmReg[0,16] = XmmReg[0,16]; superfluous\n}\n\n:PUNPCKLWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x61; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[112,16] = XmmReg2[48,16];\n XmmReg1[96,16] = XmmReg1[48,16];\n XmmReg1[80,16] = XmmReg2[32,16];\n XmmReg1[64,16] = XmmReg1[32,16];\n XmmReg1[48,16] = XmmReg2[16,16];\n XmmReg1[32,16] = XmmReg1[16,16];\n XmmReg1[16,16] = XmmReg2[0,16];\n# XmmReg1[0,16] = XmmReg1[0,16]; superfluous\n}\n\n:PUNPCKLDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x62; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[96,32] = m[32,32];\n XmmReg[64,32] = XmmReg[32,32];\n XmmReg[32,32] = m[0,32];\n# XmmReg[0,32] = XmmReg[0,32]; superfluous\n}\n\n:PUNPCKLDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x62; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[96,32] = XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[32,32];\n XmmReg1[32,32] = XmmReg2[0,32];\n# XmmReg1[0,32] = XmmReg1[0,32]; superfluous\n}\n\ndefine pcodeop punpcklqdq;\n:PUNPCKLQDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6C; m128 & XmmReg ...\n{\n XmmReg[64,64] = m128[0,64];\n# XmmReg[0,64] = XmmReg[0,64]; superfluous\n}\n\n:PUNPCKLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6C; xmmmod = 3 & XmmReg1 & XmmReg2\n{\n XmmReg1[64,64] = XmmReg2[0,64];\n# XmmReg1[0,64] = XmmReg1[0,64]; superfluous\n}\n\n:PXOR mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEF; mmxreg ... & m64 { mmxreg = mmxreg ^ m64; }\n:PXOR mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEF; mmxmod = 3 & mmxreg1 & mmxreg2\t\t{ mmxreg1 = mmxreg1 ^ mmxreg2; }\n:PXOR XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEF; XmmReg ... & m128 { XmmReg = XmmReg ^ m128; }\n:PXOR XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEF; xmmmod = 3 & XmmReg1 & XmmReg2\t{ XmmReg1 = XmmReg1 ^ XmmReg2; }\n\ndefine pcodeop rcpps;\n:RCPPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x53; XmmReg ... & m128 { XmmReg = rcpps(XmmReg, m128); }\n:RCPPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x53; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rcpps(XmmReg1, XmmReg2); }\n\ndefine pcodeop rcpss;\n:RCPSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x53; XmmReg ... & m32 { XmmReg = rcpss(XmmReg, m32); }\n:RCPSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x53; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rcpss(XmmReg1, XmmReg2); }\n\ndefine pcodeop rsqrtps;\n:RSQRTPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x52; XmmReg ... & m128 { XmmReg = rsqrtps(XmmReg, m128); }\n:RSQRTPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x52; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rsqrtps(XmmReg1, XmmReg2); }\n\ndefine pcodeop rsqrtss;\n:RSQRTSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x52; XmmReg ... & m32 { XmmReg = rsqrtss(XmmReg, m32); }\n:RSQRTSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x52; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rsqrtss(XmmReg1, XmmReg2); }\n\n:SHUFPD XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC6; XmmReg1 ... & XmmReg2_m128; imm8 \n{ \n local srcLow:8 = XmmReg2_m128[0,64];\n local srcHigh:8 = XmmReg2_m128[64,64];\n local destLow:8 = XmmReg1[0,64];\n local destHigh:8 = XmmReg1[64,64];\n local control:1 = (imm8 & 0x1)== 0:1;\n conditionalAssign(XmmReg1[0,64],control,destLow,destHigh);\n control = (imm8 & 0x2) == 0:1;\n conditionalAssign(XmmReg1[64,64],control,srcLow,srcHigh); \n}\n\n:SHUFPS XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC6; (XmmReg2_m128 & XmmReg1 ...); imm8 & Order0 & Order1 & Order2 & Order3\n{\n local xmmreg2_m128_c0 = XmmReg2_m128[0,32];\n local xmmreg2_m128_c1 = XmmReg2_m128[32,32];\n local xmmreg2_m128_c2 = XmmReg2_m128[64,32];\n local xmmreg2_m128_c3 = XmmReg2_m128[96,32];\n\n local xmm_c0 = XmmReg1[0,32];\n local xmm_c1 = XmmReg1[32,32];\n local xmm_c2 = XmmReg1[64,32];\n local xmm_c3 = XmmReg1[96,32];\n\n shuffle_4(XmmReg1[0,32],Order0,xmm_c0,xmm_c1,xmm_c2,xmm_c3);\n shuffle_4(XmmReg1[32,32],Order1,xmm_c0,xmm_c1,xmm_c2,xmm_c3);\n shuffle_4(XmmReg1[64,32],Order2,xmmreg2_m128_c0,xmmreg2_m128_c1,xmmreg2_m128_c2,xmmreg2_m128_c3);\n shuffle_4(XmmReg1[96,32],Order3,xmmreg2_m128_c0,xmmreg2_m128_c1,xmmreg2_m128_c2,xmmreg2_m128_c3);\n}\n\ndefine pcodeop sqrtpd;\n:SQRTPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x51; XmmReg ... & m128 { XmmReg = sqrtpd(XmmReg, m128); }\n:SQRTPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = sqrtpd(XmmReg1, XmmReg2); }\n\ndefine pcodeop sqrtps;\n:SQRTPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x51; XmmReg ... & m128 { XmmReg = sqrtps(XmmReg, m128); }\n:SQRTPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = sqrtps(XmmReg1, XmmReg2); }\n\n:SQRTSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x51; XmmReg ... & m64 { XmmReg[0,64] = sqrt(m64); }\n:SQRTSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,64] = sqrt(XmmReg2[0,64]); }\n\n:SQRTSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x51; XmmReg ... & m32 { XmmReg[0,32] = sqrt(m32); }\n:SQRTSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,32] = sqrt(XmmReg2[0,32]); }\n\n:SUBPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5C;XmmReg ... & m128\n{\n local m:16 = m128;\n XmmReg[0,64] = XmmReg[0,64] f- m[0,64];\n XmmReg[64,64] = XmmReg[64,64] f- m[64,64];\n}\n\n:SUBPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg2[0,64];\n XmmReg1[64,64] = XmmReg1[64,64] f- XmmReg2[64,64];\n}\n\n:SUBPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5C; XmmReg ... & m128\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[0,32] f- m[0,32];\n XmmReg[32,32] = XmmReg[32,32] f- m[32,32];\n XmmReg[64,32] = XmmReg[64,32] f- m[64,32];\n XmmReg[96,32] = XmmReg[96,32] f- m[96,32];\n}\n\n:SUBPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg2[0,32];\n XmmReg1[32,32] = XmmReg1[32,32] f- XmmReg2[32,32];\n XmmReg1[64,32] = XmmReg1[64,32] f- XmmReg2[64,32];\n XmmReg1[96,32] = XmmReg1[96,32] f- XmmReg2[96,32];\n}\n\n:SUBSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5C; XmmReg ... & m64 { XmmReg[0,64] = XmmReg[0,64] f- m64; }\n:SUBSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg2[0,64]; }\n\n:SUBSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5C; XmmReg ...& m32 { XmmReg[0,32] = XmmReg[0,32] f- m32; }\n:SUBSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg2[0,32]; }\n\n#Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS\n# RESULT <- UnorderedCompare(SRC1[63-0] <> SRC2[63-0]) {\n# * Set EFLAGS *CASE (RESULT) OF\n# UNORDERED: ZF,PF,CF <- 111;\n# GREATER_THAN: ZF,PF,CF <- 000;\n# LESS_THAN: ZF,PF,CF <- 001;\n# EQUAL: ZF,PF,CF <- 100;\n# ESAC;\n# OF,AF,SF <- 0;}\n\n:UCOMISD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2E; m64 & XmmReg ...\n{\n\tfucompe(XmmReg[0,64], m64);\n}\n\n:UCOMISD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2E; xmmmod=3 & XmmReg1 & XmmReg2\n{\n\tfucompe(XmmReg1[0,64], XmmReg2[0,64]);\n}\n\n#Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS\n# RESULT <- UnorderedCompare(SRC1[31-0] <> SRC2[31-0]) {\n# * Set EFLAGS *CASE (RESULT) OF\n# UNORDERED: ZF,PF,CF <- 111;\n# GREATER_THAN: ZF,PF,CF <- 000;\n# LESS_THAN: ZF,PF,CF <- 001;\n# EQUAL: ZF,PF,CF <- 100;\n# ESAC;\n# OF,AF,SF <- 0;}\n\n:UCOMISS XmmReg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2E; m32 & XmmReg ...\n{\n fucompe(XmmReg[0,32], m32);\n}\n\n:UCOMISS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2E; xmmmod=3 & XmmReg1 & XmmReg2\n{\n fucompe(XmmReg1[0,32], XmmReg2[0,32]);\n}\n\n:UNPCKHPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x15; m128 & XmmReg ...\n{\n XmmReg[0,64] = XmmReg[64,64];\n XmmReg[64,64] = m128[64,64];\n}\n\n:UNPCKHPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x15; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = XmmReg1[64,64];\n XmmReg1[64,64] = XmmReg2[64,64];\n}\n\n:UNPCKHPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x15; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = XmmReg[64,32];\n XmmReg[64,32] = XmmReg[96,32];\n XmmReg[32,32] = m[64,32];\n XmmReg[96,32] = m[96,32];\n}\n\n:UNPCKHPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x15; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = XmmReg1[64,32];\n XmmReg1[32,32] = XmmReg2[64,32];\n XmmReg1[64,32] = XmmReg1[96,32]; # XmmReg1 and XmmReg2 could be the same register, preserve XmmReg1[64,32] till later\n XmmReg1[96,32] = XmmReg2[96,32];\n}\n\n:UNPCKLPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x14; m128 & XmmReg ...\n{\n# XmmReg[0,64] = XmmReg[0,64]; superfluous\n XmmReg[64,64] = m128[0,64];\n}\n\n:UNPCKLPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x14; xmmmod=3 & XmmReg1 & XmmReg2\n{\n# XmmReg1[0,64] = XmmReg1[0,64]; superfluous\n XmmReg1[64,64] = XmmReg2[0,64];\n}\n\n:UNPCKLPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x14; m128 & XmmReg ...\n{\n local m:16 = m128;\n# XmmReg[0,32] = XmmReg[0,32]; superfluous\n XmmReg[64,32] = XmmReg[32,32];\n XmmReg[32,32] = m[0,32];\n XmmReg[96,32] = m[32,32];\n}\n\n:UNPCKLPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x14; xmmmod=3 & XmmReg1 & XmmReg2\n{\n# XmmReg1[0,32] = XmmReg1[0,32]; superfluous\n XmmReg1[64,32] = XmmReg1[32,32];\n XmmReg1[96,32] = XmmReg2[32,32];\n XmmReg1[32,32] = XmmReg2[0,32]; # XmmReg1 and XmmReg2 could be the same register, preserve Db till last\n}\n\n:XORPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x57; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,64] = ( XmmReg[0,64] ^ m[0,64] );\n XmmReg[64,64] = ( XmmReg[64,64] ^ m[64,64] );\n}\n\n:XORPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x57; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,64] = ( XmmReg1[0,64] ^ XmmReg2[0,64] );\n XmmReg1[64,64] = ( XmmReg1[64,64] ^ XmmReg2[64,64] );\n}\n\n:XORPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x57; m128 & XmmReg ...\n{\n local m:16 = m128;\n XmmReg[0,32] = ( XmmReg[0,32] ^ m[0,32] );\n XmmReg[32,32] = ( XmmReg[32,32] ^ m[32,32] );\n XmmReg[64,32] = ( XmmReg[64,32] ^ m[64,32] );\n XmmReg[96,32] = ( XmmReg[96,32] ^ m[96,32] );\n}\n\n:XORPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x57; xmmmod=3 & XmmReg1 & XmmReg2\n{\n XmmReg1[0,32] = ( XmmReg1[0,32] ^ XmmReg2[0,32] );\n XmmReg1[32,32] = ( XmmReg1[32,32] ^ XmmReg2[32,32] );\n XmmReg1[64,32] = ( XmmReg1[64,32] ^ XmmReg2[64,32] );\n XmmReg1[96,32] = ( XmmReg1[96,32] ^ XmmReg2[96,32] );\n}\n\n####\n#### VIA Padlock instructions\n####\n\ndefine pcodeop xstore_available;\ndefine pcodeop xstore;\ndefine pcodeop xcrypt_ecb;\ndefine pcodeop xcrypt_cbc;\ndefine pcodeop xcrypt_ctr;\ndefine pcodeop xcrypt_cfb;\ndefine pcodeop xcrypt_ofb;\ndefine pcodeop montmul;\ndefine pcodeop xsha1;\ndefine pcodeop xsha256;\n\n:XSTORE is vexMode=0 & mandover=0 & byte=0x0F; byte=0xA7; byte=0xC0 { \n\tEAX = xstore_available(EDX,EDI); \n}\n\n:XSTORE.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xC0 { \n\tEAX = xstore(ECX,EDX,EDI);\n\tECX = 0;\n}\n\n:XCRYPTECB.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xC8 { \n\txcrypt_ecb(ECX,EDX,EBX,ESI,EDI); \n}\n\n:XCRYPTCBC.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xD0 { \n\txcrypt_cbc(ECX,EAX,EDX,EBX,ESI,EDI); \n}\n\n:XCRYPTCTR.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xD8 { \n\txcrypt_ctr(ECX,EAX,EDX,EBX,ESI,EDI); \n}\n\n:XCRYPTCFB.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xE0 { \n\txcrypt_cfb(ECX,EAX,EDX,EBX,ESI,EDI); \n}\n\n:XCRYPTOFB.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xE8 { \n\txcrypt_ofb(ECX,EAX,EDX,EBX,ESI,EDI); \n}\n\n:MONTMUL.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA6; byte=0xC0 { \n\tmontmul(EAX,ECX,ESI); \n\tECX=0; \n\tEDX=0; \n}\n\n:XSHA1.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA6; byte=0xC8 {\n\txsha1(ECX,ESI,EDI); \n\tEAX = ECX;\n}\n\n:XSHA256.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA6; byte=0xD0 { \n\txsha256(ECX,ESI,EDI); \n\tEAX = ECX; \n}\n\n####\n#### SSE4.1 instructions\n####\n\ndefine pcodeop mpsadbw;\n:MPSADBW XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x42; XmmReg ... & m128; imm8 { XmmReg = mpsadbw(XmmReg, m128, imm8:8); }\n:MPSADBW XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x42; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = mpsadbw(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop phminposuw;\n:PHMINPOSUW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x41; XmmReg ... & m128 { XmmReg = phminposuw(m128); }\n:PHMINPOSUW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x41; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = phminposuw(XmmReg2); }\n\ndefine pcodeop pmuldq;\n:PMULDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x28; XmmReg ... & m128 { XmmReg = pmuldq(XmmReg, m128); }\n:PMULDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x28; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmuldq(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmulld;\n:PMULLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x40; XmmReg ... & m128 { XmmReg = pmulld(XmmReg, m128); }\n:PMULLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x40; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmulld(XmmReg1, XmmReg2); }\n\ndefine pcodeop dpps;\n:DPPS XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x40; XmmReg ... & m128; imm8 { XmmReg = dpps(XmmReg, m128, imm8:8); }\n:DPPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x40; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = dpps(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop dppd;\n:DPPD XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x41; XmmReg ... & m128; imm8 { XmmReg = dppd(XmmReg, m128, imm8:8); }\n:DPPD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x41; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = dppd(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop blendps;\n:BLENDPS XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0C; XmmReg ... & m128; imm8 { XmmReg = blendps(XmmReg, m128, imm8:8); }\n:BLENDPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0C; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = blendps(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop blendpd;\n:BLENDPD XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0D; XmmReg ... & m128; imm8 { XmmReg = blendpd(XmmReg, m128, imm8:8); }\n:BLENDPD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0D; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = blendpd(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop blendvps;\n:BLENDVPS XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x14; XmmReg ... & m128 { XmmReg = blendvps(XmmReg, m128, XMM0); }\n:BLENDVPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x14; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = blendvps(XmmReg1, XmmReg2, XMM0); }\n\ndefine pcodeop blendvpd;\n:BLENDVPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x15; XmmReg ... & m128 { XmmReg = blendvpd(XmmReg, m128, XMM0); }\n:BLENDVPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x15; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = blendvpd(XmmReg1, XmmReg2, XMM0); }\n\ndefine pcodeop pblendvb;\n:PBLENDVB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x10; XmmReg ... & m128 { XmmReg = pblendvb(XmmReg, m128, XMM0); }\n:PBLENDVB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x10; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pblendvb(XmmReg1, XmmReg2, XMM0); }\n\ndefine pcodeop pblendw;\n:PBLENDW XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0E; XmmReg ... & m128; imm8 { XmmReg = pblendw(XmmReg, m128, imm8:8); }\n:PBLENDW XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0E; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = pblendw(XmmReg1, XmmReg2, imm8:8); }\n\n:PMINSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x38; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,8],srcCopy[0,8] s< XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]);\n conditionalAssign(XmmReg1[8,8],srcCopy[8,8] s< XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]);\n conditionalAssign(XmmReg1[16,8],srcCopy[16,8] s< XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]);\n conditionalAssign(XmmReg1[24,8],srcCopy[24,8] s< XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]);\n conditionalAssign(XmmReg1[32,8],srcCopy[32,8] s< XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]);\n conditionalAssign(XmmReg1[40,8],srcCopy[40,8] s< XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]);\n conditionalAssign(XmmReg1[48,8],srcCopy[48,8] s< XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]);\n conditionalAssign(XmmReg1[56,8],srcCopy[56,8] s< XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]);\n conditionalAssign(XmmReg1[64,8],srcCopy[64,8] s< XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]);\n conditionalAssign(XmmReg1[72,8],srcCopy[72,8] s< XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]);\n conditionalAssign(XmmReg1[80,8],srcCopy[80,8] s< XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]);\n conditionalAssign(XmmReg1[88,8],srcCopy[88,8] s< XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]);\n conditionalAssign(XmmReg1[96,8],srcCopy[96,8] s< XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]);\n conditionalAssign(XmmReg1[104,8],srcCopy[104,8] s< XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]);\n conditionalAssign(XmmReg1[112,8],srcCopy[112,8] s< XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]);\n conditionalAssign(XmmReg1[120,8],srcCopy[120,8] s< XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]);\n}\n\n:PMINUW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3A; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128; \n conditionalAssign(XmmReg1[0,16],srcCopy[0,16] < XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]);\n conditionalAssign(XmmReg1[16,16],srcCopy[16,16] < XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]);\n conditionalAssign(XmmReg1[32,16],srcCopy[32,16] < XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]);\n conditionalAssign(XmmReg1[48,16],srcCopy[48,16] < XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]);\n conditionalAssign(XmmReg1[64,16],srcCopy[64,16] < XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]);\n conditionalAssign(XmmReg1[80,16],srcCopy[80,16] < XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]);\n conditionalAssign(XmmReg1[96,16],srcCopy[96,16] < XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]);\n conditionalAssign(XmmReg1[112,16],srcCopy[112,16] < XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]);\n}\n\n:PMINUD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3B; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,32],srcCopy[0,32] < XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]);\n conditionalAssign(XmmReg1[32,32],srcCopy[32,32] < XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]);\n conditionalAssign(XmmReg1[64,32],srcCopy[64,32] < XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]);\n conditionalAssign(XmmReg1[96,32],srcCopy[96,32] < XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]);\n}\n\n:PMINSD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x39; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,32],srcCopy[0,32] s< XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]);\n conditionalAssign(XmmReg1[32,32],srcCopy[32,32] s< XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]);\n conditionalAssign(XmmReg1[64,32],srcCopy[64,32] s< XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]);\n conditionalAssign(XmmReg1[96,32],srcCopy[96,32] s< XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]);\n}\n\n:PMAXSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3C; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,8],srcCopy[0,8] s> XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]);\n conditionalAssign(XmmReg1[8,8],srcCopy[8,8] s> XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]);\n conditionalAssign(XmmReg1[16,8],srcCopy[16,8] s> XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]);\n conditionalAssign(XmmReg1[24,8],srcCopy[24,8] s> XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]);\n conditionalAssign(XmmReg1[32,8],srcCopy[32,8] s> XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]);\n conditionalAssign(XmmReg1[40,8],srcCopy[40,8] s> XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]);\n conditionalAssign(XmmReg1[48,8],srcCopy[48,8] s> XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]);\n conditionalAssign(XmmReg1[56,8],srcCopy[56,8] s> XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]);\n conditionalAssign(XmmReg1[64,8],srcCopy[64,8] s> XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]);\n conditionalAssign(XmmReg1[72,8],srcCopy[72,8] s> XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]);\n conditionalAssign(XmmReg1[80,8],srcCopy[80,8] s> XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]);\n conditionalAssign(XmmReg1[88,8],srcCopy[88,8] s> XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]);\n conditionalAssign(XmmReg1[96,8],srcCopy[96,8] s> XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]);\n conditionalAssign(XmmReg1[104,8],srcCopy[104,8] s> XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]);\n conditionalAssign(XmmReg1[112,8],srcCopy[112,8] s> XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]);\n conditionalAssign(XmmReg1[120,8],srcCopy[120,8] s> XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]);\n}\n\n\n:PMAXUW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3E; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128; \n conditionalAssign(XmmReg1[0,16],srcCopy[0,16] > XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]);\n conditionalAssign(XmmReg1[16,16],srcCopy[16,16] > XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]);\n conditionalAssign(XmmReg1[32,16],srcCopy[32,16] > XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]);\n conditionalAssign(XmmReg1[48,16],srcCopy[48,16] > XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]);\n conditionalAssign(XmmReg1[64,16],srcCopy[64,16] > XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]);\n conditionalAssign(XmmReg1[80,16],srcCopy[80,16] > XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]);\n conditionalAssign(XmmReg1[96,16],srcCopy[96,16] > XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]);\n conditionalAssign(XmmReg1[112,16],srcCopy[112,16] > XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]);\n}\n\n:PMAXUD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3F; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,32],srcCopy[0,32] > XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]);\n conditionalAssign(XmmReg1[32,32],srcCopy[32,32] > XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]);\n conditionalAssign(XmmReg1[64,32],srcCopy[64,32] > XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]);\n conditionalAssign(XmmReg1[96,32],srcCopy[96,32] > XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]);\n}\n\n:PMAXSD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3D; XmmReg1 ... & XmmReg2_m128 \n{ \n local srcCopy:16 = XmmReg2_m128;\n conditionalAssign(XmmReg1[0,32],srcCopy[0,32] s> XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]);\n conditionalAssign(XmmReg1[32,32],srcCopy[32,32] s> XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]);\n conditionalAssign(XmmReg1[64,32],srcCopy[64,32] s> XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]);\n conditionalAssign(XmmReg1[96,32],srcCopy[96,32] s> XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]);\n}\n\ndefine pcodeop roundps;\n:ROUNDPS XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x08; XmmReg ... & m128; imm8 { XmmReg = roundps(XmmReg, m128, imm8:8); }\n:ROUNDPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x08; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundps(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop roundss;\n:ROUNDSS XmmReg, m32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0A; XmmReg ... & m32; imm8 { XmmReg = roundss(XmmReg, m32, imm8:8); }\n:ROUNDSS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0A; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundss(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop roundpd;\n:ROUNDPD XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x09; XmmReg ... & m128; imm8 { XmmReg = roundpd(XmmReg, m128, imm8:8); }\n:ROUNDPD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x09; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundpd(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop roundsd;\n:ROUNDSD XmmReg, m64, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0B; XmmReg ... & m64; imm8 { XmmReg = roundsd(XmmReg, m64, imm8:8); }\n:ROUNDSD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0B; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundsd(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop insertps;\n:INSERTPS XmmReg, m32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x21; XmmReg ... & m32; imm8 { XmmReg = insertps(XmmReg, m32, imm8:8); }\n:INSERTPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x21; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = insertps(XmmReg1, XmmReg2, imm8:8); }\n\n:PINSRB XmmReg, rm32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x20; XmmReg ... & rm32; imm8 \n{ \n local destIndex:1 = (imm8 & 0xf) * 8:1;\n local useLow:1 = destIndex < 64:1;\n local newLow:8 = zext(rm32:1) << destIndex;\n newLow = (XmmReg[0,64] & ~(0xff:8 << destIndex)) | newLow;\n local newHigh:8 = zext(rm32:1) << (destIndex-64:1);\n newHigh = (XmmReg[64,64] & ~(0xff:8 << (destIndex - 64:1))) | newHigh;\n conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]);\n conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]);\n}\n\n:PINSRD XmmReg, rm32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x22; XmmReg ... & rm32; imm8 \n{ \n local destIndex:1 = (imm8 & 0x3) * 32:1;\n local useLow:1 = destIndex < 64:1;\n local newLow:8 = zext(rm32) << destIndex;\n newLow = (XmmReg[0,64] & ~(0xffffffff:8 << destIndex)) | newLow;\n local newHigh:8 = zext(rm32) << (destIndex-64:1);\n newHigh = (XmmReg[64,64] & ~(0xffffffff:8 << (destIndex - 64:1))) | newHigh;\n conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]);\n conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]);\n}\n\n@ifdef IA64\n:PINSRQ XmmReg, rm64, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & $(REX_W) & byte=0x0F; byte=0x3A; byte=0x22; XmmReg ... & rm64; imm8 \n{ \n local useHigh:1 = imm8 & 0x1;\n conditionalAssign(XmmReg[0,64],!useHigh,rm64,XmmReg[0,64]);\n conditionalAssign(XmmReg[64,64],useHigh,rm64,XmmReg[64,64]);\n}\n@endif\n\ndefine pcodeop extractps;\n@ifdef IA64\n:EXTRACTPS rm64, XmmReg, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x17; XmmReg ... & rm64; imm8 { rm64 = extractps(XmmReg, imm8:8); }\n@endif\n:EXTRACTPS rm32, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x17; XmmReg ... & rm32 & check_rm32_dest ...; imm8 { rm32 = extractps(XmmReg, imm8:8); build check_rm32_dest; }\n\n:PEXTRB Rmr32, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x14; mod=3 & XmmReg & Rmr32 & check_Rmr32_dest; imm8 \n{ \n local shift:1 = (imm8 & 0xf) * 8:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64));\n Rmr32 = zext(temp:1);\n build check_Rmr32_dest;\n}\n\n:PEXTRB Mem, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x14; XmmReg ... & Mem; imm8 \n{ \n local shift:1 = (imm8 & 0xf) * 8:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64));\n *Mem = temp:1;\n}\n\n:PEXTRD Rmr32, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x16; mod=3 & XmmReg & Rmr32 & check_Rmr32_dest; imm8 \n{ \n local shift:1 = (imm8 & 0x3) * 32:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64));\n Rmr32 = zext(temp:4);\n build check_Rmr32_dest; \n}\n\n:PEXTRD Mem, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x16; XmmReg ... & Mem; imm8 \n{ \n local shift:1 = (imm8 & 0x3) * 32:1;\n local low:1 = shift < 64:1;\n local temp:8;\n conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64));\n *Mem = temp:4;\n}\n\n@ifdef IA64\n:PEXTRQ Rmr64, XmmReg, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & $(REX_W) & byte=0x0F; byte=0x3A; byte=0x16; mod=3 & XmmReg & Rmr64; imm8 \n{ \n local high:1 = imm8 & 0x1;\n conditionalAssign(Rmr64,high,XmmReg[64,64],XmmReg[0,64]);\n}\n\n:PEXTRQ Mem, XmmReg, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & $(REX_W) & byte=0x0F; byte=0x3A; byte=0x16; XmmReg ... & Mem; imm8 \n{ \n local high:1 = imm8 & 0x1;\n local temp:8;\n conditionalAssign(temp,high,XmmReg[64,64],XmmReg[0,64]);\n *Mem = temp;\n}\n@endif\n\ndefine pcodeop pmovsxbw;\n:PMOVSXBW XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x20; XmmReg ... & m64 { XmmReg = pmovsxbw(XmmReg, m64); }\n:PMOVSXBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x20; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxbw(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovsxbd;\n:PMOVSXBD XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x21; XmmReg ... & m32 { XmmReg = pmovsxbd(XmmReg, m32); }\n:PMOVSXBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x21; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxbd(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovsxbq;\n:PMOVSXBQ XmmReg, m16 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x22; XmmReg ... & m16 { XmmReg = pmovsxbq(XmmReg, m16); }\n:PMOVSXBQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x22; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxbq(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovsxwd;\n:PMOVSXWD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x23; XmmReg ... & m64 { XmmReg = pmovsxwd(XmmReg, m64); }\n:PMOVSXWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x23; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxwd(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovsxwq;\n:PMOVSXWQ XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x24; XmmReg ... & m32 { XmmReg = pmovsxwq(XmmReg, m32); }\n:PMOVSXWQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x24; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxwq(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovsxdq;\n:PMOVSXDQ XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x25; XmmReg ... & m64 { XmmReg = pmovsxdq(XmmReg, m64); }\n:PMOVSXDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x25; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxdq(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovzxbw;\n:PMOVZXBW XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x30; XmmReg ... & m64 { XmmReg = pmovzxbw(XmmReg, m64); }\n:PMOVZXBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x30; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxbw(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovzxbd;\n:PMOVZXBD XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x31; XmmReg ... & m32 { XmmReg = pmovzxbd(XmmReg, m32); }\n:PMOVZXBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x31; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxbd(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovzxbq;\n:PMOVZXBQ XmmReg, m16 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x32; XmmReg ... & m16 { XmmReg = pmovzxbq(XmmReg, m16); }\n:PMOVZXBQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x32; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxbq(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovzxwd;\n:PMOVZXWD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x33; XmmReg ... & m64 { XmmReg = pmovzxwd(XmmReg, m64); }\n:PMOVZXWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x33; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxwd(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovzxwq;\n:PMOVZXWQ XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x34; XmmReg ... & m32 { XmmReg = pmovzxwq(XmmReg, m32); }\n:PMOVZXWQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x34; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxwq(XmmReg1, XmmReg2); }\n\ndefine pcodeop pmovzxdq;\n:PMOVZXDQ XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x35; XmmReg ... & m64 { XmmReg = pmovzxdq(XmmReg, m64); }\n:PMOVZXDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x35; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxdq(XmmReg1, XmmReg2); }\n\n:PTEST XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x17; XmmReg ... & m128 {\n local temp_m128:16 = m128;\n local tmp = temp_m128 & XmmReg;\n ZF = tmp == 0;\n local tmp2 = temp_m128 & ~XmmReg;\n CF = tmp2 == 0;\n AF = 0;\n OF = 0;\n PF = 0;\n SF = 0;\n}\n\n:PTEST XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x17; xmmmod=3 & XmmReg1 & XmmReg2 {\n local tmp = XmmReg2 & XmmReg1;\n ZF = tmp == 0;\n local tmp2 = XmmReg2 & ~XmmReg1;\n CF = tmp2 == 0;\n AF = 0;\n OF = 0;\n PF = 0;\n SF = 0;\n}\n\n:PCMPEQQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x29; XmmReg ... & m128 \n{ \n\tlocal temp_m128:16 = m128;\n\tXmmReg[0,64] = zext(XmmReg[0,64] == temp_m128[0,64]) * 0xffffffffffffffff:8;\n\tXmmReg[64,64] = zext(XmmReg[64,64] == temp_m128[64,64]) * 0xffffffffffffffff:8;\n}\n:PCMPEQQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x29; xmmmod=3 & XmmReg1 & XmmReg2 \n{ \n\tXmmReg1[0,64] = zext(XmmReg1[0,64] == XmmReg2[0,64]) * 0xffffffffffffffff:8;\n\tXmmReg1[64,64] = zext(XmmReg1[64,64] == XmmReg2[64,64]) * 0xffffffffffffffff:8;\n}\n\ndefine pcodeop packusdw;\n:PACKUSDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x2B; XmmReg ... & m128 { XmmReg = packusdw(XmmReg, m128); }\n:PACKUSDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x2B; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = packusdw(XmmReg1, XmmReg2); }\n\ndefine pcodeop movntdqa;\n:MOVNTDQA XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x2A; XmmReg ... & m128 { XmmReg = movntdqa(XmmReg, m128); }\n\n####\n#### SSE4.2 instructions\n####\n\ndefine pcodeop crc32;\n:CRC32 Reg32, rm8 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF0; Reg32 ... & check_Reg32_dest ... & rm8 { Reg32 = crc32(Reg32, rm8); build check_Reg32_dest; }\n:CRC32 Reg32, rm16 is vexMode=0 & opsize=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF1; Reg32 ... & check_Reg32_dest ... & rm16 { Reg32 = crc32(Reg32, rm16); build check_Reg32_dest; }\n:CRC32 Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF1; Reg32 ... & check_Reg32_dest ... & rm32 { Reg32 = crc32(Reg32, rm32); build check_Reg32_dest; }\n@ifdef IA64\n:CRC32 Reg32, rm8 is vexMode=0 & opsize=1 & $(PRE_F2) & $(REX) & byte=0x0F; byte=0x38; byte=0xF0; Reg32 ... & check_Reg32_dest ... & rm8 { Reg32 = crc32(Reg32, rm8); build check_Reg32_dest; }\n:CRC32 Reg64, rm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & $(REX_W) & byte=0x0F; byte=0x38; byte=0xF0; Reg64 ... & rm8 { Reg64 = crc32(Reg64, rm8); }\n:CRC32 Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & $(REX_W) & byte=0x0F; byte=0x38; byte=0xF1; Reg64 ... & rm64 { Reg64 = crc32(Reg64, rm64); }\n@endif\n\ndefine pcodeop pcmpestri;\n:PCMPESTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61; XmmReg ... & m128; imm8 { ECX = pcmpestri(XmmReg, m128, imm8:8); }\n:PCMPESTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpestri(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop pcmpestrm;\n:PCMPESTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; XmmReg ... & m128; imm8 { XMM0 = pcmpestrm(XmmReg, m128, imm8:8); }\n:PCMPESTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpestrm(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop pcmpistri;\n:PCMPISTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63; XmmReg ... & m128; imm8 { ECX = pcmpistri(XmmReg, m128, imm8:8); }\n:PCMPISTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpistri(XmmReg1, XmmReg2, imm8:8); }\n\ndefine pcodeop pcmpistrm;\n:PCMPISTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x62; XmmReg ... & m128; imm8 { XMM0 = pcmpistrm(XmmReg, m128, imm8:8); }\n:PCMPISTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x62; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpistrm(XmmReg1, XmmReg2, imm8:8); }\n\n:PCMPGTQ XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x37; XmmReg1 ... & XmmReg2_m128 \n{ \n XmmReg1[0,64] = 0xffffffffffffffff:8 * (zext(XmmReg1[0,64] s> XmmReg2_m128[0,64]));\n XmmReg1[64,64] = 0xffffffffffffffff:8 * (zext(XmmReg1[64,64] s> XmmReg2_m128[64,64]));\n}\n\nmacro popcountflags(src){\n\tOF = 0:1;\n\tSF = 0:1;\n\tAF = 0:1;\n\tCF = 0:1;\n\tPF = 0:1;\n\tZF = (src == 0);\n}\n:POPCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_F3) & byte=0x0F; byte=0xB8; Reg16 ... & rm16 { popcountflags(rm16); Reg16 = popcount(rm16); }\n:POPCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xB8; Reg32 ... & check_Reg32_dest ... & rm32 { popcountflags(rm32); Reg32 = popcount(rm32); build check_Reg32_dest; }\n@ifdef IA64\n:POPCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xB8; Reg64 ... & rm64 { popcountflags(rm64); Reg64 = popcount(rm64); }\n@endif\n\n####\n#### AESNI instructions\n####\n\ndefine pcodeop aesdec;\n:AESDEC XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xde; XmmReg1 ... & XmmReg2_m128 {\n\tXmmReg1 = aesdec(XmmReg1, XmmReg2_m128);\n}\n:VAESDEC XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xde; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 {\n\tXmmReg1 = aesdec(vexVVVV_XmmReg, XmmReg2_m128);\n\tYmmReg1 = zext(XmmReg1);\n}\n\ndefine pcodeop aesdeclast;\n:AESDECLAST XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdf; XmmReg1 ... & XmmReg2_m128 {\n\tXmmReg1 = aesdeclast(XmmReg1, XmmReg2_m128);\n}\n:VAESDECLAST XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xdf; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 {\n\tXmmReg1 = aesdeclast(vexVVVV_XmmReg, XmmReg2_m128);\n\tYmmReg1 = zext(XmmReg1);\n}\n\ndefine pcodeop aesenc;\n:AESENC XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdc; XmmReg1 ... & XmmReg2_m128 {\n\tXmmReg1 = aesenc(XmmReg1, XmmReg2_m128);\n}\n:VAESENC XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xdc; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 {\n\tXmmReg1 = aesenc(vexVVVV_XmmReg, XmmReg2_m128);\n\tYmmReg1 = zext(XmmReg1);\n}\n\ndefine pcodeop aesenclast;\n:AESENCLAST XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdd; XmmReg1 ... & XmmReg2_m128 {\n\tXmmReg1 = aesenclast(XmmReg1, XmmReg2_m128);\n}\n:VAESENCLAST XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xdd; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 {\n\tXmmReg1 = aesenclast(vexVVVV_XmmReg, XmmReg2_m128);\n\tYmmReg1 = zext(XmmReg1);\n}\n\ndefine pcodeop aesimc;\n:AESIMC XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdb; XmmReg1 ... & XmmReg2_m128 {\n\tXmmReg1 = aesimc(XmmReg2_m128);\n}\n:VAESIMC XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0xdb; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 {\n\tXmmReg1 = aesimc(XmmReg2_m128);\n\tYmmReg1 = zext(XmmReg1);\n}\n\ndefine pcodeop aeskeygenassist;\n:AESKEYGENASSIST XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0xdf; XmmReg1 ... & XmmReg2_m128; imm8 {\n\tXmmReg1 = aeskeygenassist(XmmReg2_m128, imm8:1);\n}\n:VAESKEYGENASSIST XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0xdf; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 {\n\tXmmReg1 = aeskeygenassist(XmmReg2_m128, imm8:1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n\n\n####\n#### Deprecated 3DNow! instructions\n####\n\ndefine pcodeop PackedIntToFloatingDwordConv;\n:PI2FD mmxreg, m64 is vexMode=0 & suffix3D=0x0D & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedIntToFloatingDwordConv(mmxreg, m64); }\n:PI2FD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x0D & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedIntToFloatingDwordConv(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingToIntDwordConv;\n:PF2ID mmxreg, m64 is vexMode=0 & suffix3D=0x1D & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingToIntDwordConv(mmxreg, m64); }\n:PF2ID mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x1D & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingToIntDwordConv(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingCompareGE;\n:PFCMPGE mmxreg, m64 is vexMode=0 & suffix3D=0x90 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingCompareGE(mmxreg, m64); }\n:PFCMPGE mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x90 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingCompareGE(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingCompareGT;\n:PFCMPGT mmxreg, m64 is vexMode=0 & suffix3D=0xA0 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingCompareGT(mmxreg, m64); }\n:PFCMPGT mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA0 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingCompareGT(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingCompareEQ;\n:PFCMPEQ mmxreg, m64 is vexMode=0 & suffix3D=0xB0 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingCompareEQ(mmxreg, m64); }\n:PFCMPEQ mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB0 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingCompareEQ(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingAccumulate;\n:PFACC mmxreg, m64 is vexMode=0 & suffix3D=0xAE & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingAccumulate(mmxreg, m64); }\n:PFACC mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xAE & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingAccumulate(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingADD;\n:PFADD mmxreg, m64 is vexMode=0 & suffix3D=0x9E & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingADD(mmxreg, m64); }\n:PFADD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x9E & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingADD(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingSUB;\n:PFSUB mmxreg, m64 is vexMode=0 & suffix3D=0x9A & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingSUB(mmxreg, m64); }\n:PFSUB mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x9A & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingSUB(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingSUBR;\n:PFSUBR mmxreg, m64 is vexMode=0 & suffix3D=0xAA & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingSUBR(mmxreg, m64); }\n:PFSUBR mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xAA & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingSUBR(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingMIN;\n:PFMIN mmxreg, m64 is vexMode=0 & suffix3D=0x94 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingMIN(mmxreg, m64); }\n:PFMIN mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x94 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingMIN(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingMAX;\n:PFMAX mmxreg, m64 is vexMode=0 & suffix3D=0xA4 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingMAX(mmxreg, m64); }\n:PFMAX mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA4 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingMAX(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingMUL;\n:PFMUL mmxreg, m64 is vexMode=0 & suffix3D=0xB4 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingMUL(mmxreg, m64); }\n:PFMUL mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB4 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingMUL(mmxreg1, mmxreg2); }\n\ndefine pcodeop FloatingReciprocalAprox;\n:PFRCP mmxreg, m64 is vexMode=0 & suffix3D=0x96 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = FloatingReciprocalAprox(mmxreg, m64); }\n:PFRCP mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x96 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = FloatingReciprocalAprox(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingReciprocalSQRAprox;\n:PFRSQRT mmxreg, m64 is vexMode=0 & suffix3D=0x97 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalSQRAprox(mmxreg, m64); }\n:PFRSQRT mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x97 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalSQRAprox(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingReciprocalIter1;\n:PFRCPIT1 mmxreg, m64 is vexMode=0 & suffix3D=0xA6 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalIter1(mmxreg, m64); }\n:PFRCPIT1 mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA6 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalIter1(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingReciprocalSQRIter1;\n:PFRSQIT1 mmxreg, m64 is vexMode=0 & suffix3D=0xA7 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalSQRIter1(mmxreg, m64); }\n:PFRSQIT1 mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA7 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalSQRIter1(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingReciprocalIter2;\n:PFRCPIT2 mmxreg, m64 is vexMode=0 & suffix3D=0xB6 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalIter2(mmxreg, m64); }\n:PFRCPIT2 mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB6 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalIter2(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedAverageUnsignedBytes;\n:PAVGUSB mmxreg, m64 is vexMode=0 & suffix3D=0xBF & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedAverageUnsignedBytes(mmxreg, m64); }\n:PAVGUSB mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xBF & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedAverageUnsignedBytes(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedAverageHighRoundedWord;\n:PMULHRW mmxreg, m64 is vexMode=0 & suffix3D=0xB7 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedAverageHighRoundedWord(mmxreg, m64); }\n:PMULHRW mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB7 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedAverageHighRoundedWord(mmxreg1, mmxreg2); }\n\ndefine pcodeop FastExitMediaState;\n:FEMMS is vexMode=0 & byte=0x0F; byte=0x0E { FastExitMediaState(); }\n\n#define pcodeop PrefetchDataIntoCache;\n#:PREFETCH m8 is vexMode=0 & byte=0x0F; byte=0x18; m8 { PrefetchDataIntoCache(m8); }\n\n#define pcodeop PrefetchDataIntoCacheWrite;\n#:PREFETCHW m8 is vexMode=0 & byte=0x0F; byte=0x0D; reg_opcode=1 ... & m8 { PrefetchDataIntoCacheWrite(m8); }\n\n# 3DNow! extensions\n\ndefine pcodeop PackedFloatingToIntWord;\n:PF2IW mmxreg, m64 is vexMode=0 & suffix3D=0x1C & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingToIntWord(mmxreg, m64); }\n:PF2IW mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x1C & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingToIntWord(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedIntToFloatingWord;\n:PI2FW mmxreg, m64 is vexMode=0 & suffix3D=0x0C & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedIntToFloatingWord(mmxreg, m64); }\n:PI2FW mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x0C & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedIntToFloatingWord(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingNegAccumulate;\n:PFNACC mmxreg, m64 is vexMode=0 & suffix3D=0x8A & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingNegAccumulate(mmxreg, m64); }\n:PFNACC mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x8A & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingNegAccumulate(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedFloatingPosNegAccumulate;\n:PFPNACC mmxreg, m64 is vexMode=0 & suffix3D=0x8E & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingPosNegAccumulate(mmxreg, m64); }\n:PFPNACC mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x8E & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingPosNegAccumulate(mmxreg1, mmxreg2); }\n\ndefine pcodeop PackedSwapDWords;\n:PSWAPD mmxreg, m64 is vexMode=0 & suffix3D=0xBB & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedSwapDWords(mmxreg, m64); }\n:PSWAPD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xBB & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedSwapDWords(mmxreg1, mmxreg2); }\n\ndefine pcodeop MaskedMoveQWord;\n:MASKMOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF7; mmxmod = 3 & mmxreg1 & mmxreg2\t\t{ mmxreg1 = MaskedMoveQWord(mmxreg1, mmxreg2); }\n\n\n####\n#### SSE4a instructions\n####\n\nbitLen: val is imm8 [ val=imm8 & 0x3f; ] { export *[const]:1 val; }\nlsbOffset: val is imm8 [ val=imm8 & 0x3f; ] { export *[const]:1 val; }\n:EXTRQ XmmReg2, bitLen, lsbOffset is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x78; reg_opcode=0 & XmmReg2; bitLen; lsbOffset {\n\tlocal mask:16 = ((1 << bitLen) - 1) << lsbOffset;\n\tlocal val:16 = (XmmReg2 & mask) >> lsbOffset;\n\tXmmReg2 = val;\n}\n\n:EXTRQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x79; XmmReg1 & XmmReg2 {\n\tlocal len = XmmReg2[0,6];\n\tlocal offs = XmmReg2[6,6];\n\tlocal mask = ((1 << len) - 1) << offs;\n\tlocal val = (XmmReg1 & mask) >> offs;\n\tXmmReg1 = val;\n}\n\n:INSERTQ XmmReg1, XmmReg2, bitLen, lsbOffset is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x78; XmmReg1 & XmmReg2; bitLen; lsbOffset {\n\tlocal mask:16 = ((1 << bitLen) - 1) << lsbOffset;\n\tlocal val:16 = (zext(XmmReg2[0,64]) & ((1 << bitLen) - 1));\n\tXmmReg1 = (XmmReg1 & ~zext(mask)) | (zext(val) << lsbOffset);\n}\n\n:INSERTQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x79; XmmReg1 & XmmReg2 {\n\tlocal len = XmmReg2[64,6];\n\tlocal offs = XmmReg2[72,6];\n\tlocal mask:16 = ((1 << len) - 1) << offs;\n\tlocal val:16 = (zext(XmmReg2[0,64]) & ((1 << len) - 1));\n\tXmmReg1 = (XmmReg1 & ~zext(mask)) | (zext(val) << offs);\n}\n\n:MOVNTSD m64, XmmReg1 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2B; XmmReg1 ... & m64 {\n\tm64 = XmmReg1[0,64];\n}\n\n:MOVNTSS m32, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2B; XmmReg1 ... & m32 {\n\tm32 = XmmReg1[0,32];\n}\n} # end with : lockprefx=0\n" }, { "path": "pypcode/processors/x86/data/languages/lockable.sinc", "content": "# The LOCK prefix is only valid for certain instructions, otherwise, from the\n# Intel instruction manual:\n# An undefined opcode exception will also be generated if the LOCK prefix\n# is used with any instruction not in the above list.\n# The instructions in this file have their non-lockable counterparts in ia.sinc\n\n:ADC^lockx m8,imm8\t\tis vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=2 ... ; imm8 \n{ \n build lockx; \n build m8;\n addCarryFlags(m8, imm8:1); \n resultflags(m8);\n build unlock;\n}\n\n:ADC^lockx m16,imm16\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=2 ...; imm16 \n{ \n build lockx;\n build m16;\n addCarryFlags(m16, imm16:2);\n resultflags(m16);\n build unlock; \n}\n\n:ADC^lockx m32,imm32\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=2 ...; imm32 \n{ \n build lockx;\n build m32;\n addCarryFlags(m32, imm32:4);\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:ADC^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=2 ...; simm32 \n{ \n build lockx;\n build m64;\n addCarryFlags(m64,simm32);\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:ADC^lockx m16,simm8_16\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=2 ...; simm8_16\t\n{\n build lockx; \n build m16;\n addCarryFlags(m16,simm8_16);\n resultflags(m16);\n build unlock; \n}\n\n:ADC^lockx m32,simm8_32\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=2 ...; simm8_32 \n{\n build lockx;\n build m32;\n addCarryFlags(m32,simm8_32);\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:ADC^lockx m64,simm8_64\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=2 ...; simm8_64 \n{\n build lockx;\n build m64;\n addCarryFlags(m64,simm8_64);\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:ADC^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x10; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n addCarryFlags(m8, Reg8);\n resultflags(m8);\n build unlock;\n}\n\n:ADC^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x11; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n addCarryFlags(m16, Reg16);\n resultflags(m16);\n build unlock;\n}\n\n:ADC^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x11; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n addCarryFlags(m32, Reg32);\n resultflags(m32);\n build unlock;\n}\n\n@ifdef IA64\n:ADC^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x11; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n addCarryFlags(m64, Reg64);\n resultflags(m64);\n build unlock;\n}\n@endif\n\n:ADD^lockx m8,imm8\t\tis vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=0 ...; imm8\t\t\n{\n build lockx;\n build m8;\n addflags(m8,imm8);\n m8 = m8 + imm8;\n resultflags(m8);\n build unlock;\n}\n\n:ADD^lockx m16,imm16\t\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=0 ...; imm16\t\n{\n build lockx;\n build m16;\n addflags(m16,imm16);\n m16 = m16 + imm16;\n resultflags(m16);\n build unlock;\n}\n\n:ADD^lockx m32,imm32\t\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=0 ...; imm32\t\n{\n build lockx;\n build m32;\n addflags(m32,imm32);\n m32 = m32 + imm32;\n resultflags(m32);\n build unlock;\n}\n\n@ifdef IA64\n:ADD^lockx m64,simm32\t\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=0 ...; simm32\t\n{\n build lockx;\n build m64;\n addflags(m64,simm32);\n m64 = m64 + simm32;\n resultflags(m64);\n build unlock;\n}\n@endif\n\n:ADD^lockx m16,simm8_16\t\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=0 ...; simm8_16\t\n{\n build lockx;\n build m16;\n addflags(m16,simm8_16);\n m16 = m16 + simm8_16;\n resultflags(m16);\n build unlock;\n}\n\n:ADD^lockx m32,simm8_32\t\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=0 ...; simm8_32\t\n{\n build lockx;\n build m32;\n addflags(m32,simm8_32);\n m32 = m32 + simm8_32;\n resultflags(m32);\n build unlock;\n}\n\n@ifdef IA64\n:ADD^lockx m64,simm8_64\t\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=0 ...; simm8_64\t\n{\n build lockx;\n build m64;\n addflags(m64,simm8_64);\n m64 = m64 + simm8_64;\n resultflags(m64);\n build unlock;\n}\n@endif\n\n:ADD^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x00; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n addflags(m8,Reg8);\n m8 = m8 + Reg8;\n resultflags(m8);\n build unlock;\n}\n\n:ADD^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x1; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n addflags(m16,Reg16);\n m16 = m16 + Reg16;\n resultflags(m16);\n build unlock;\n}\n\n:ADD^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x1; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n addflags(m32,Reg32);\n m32 = m32 + Reg32;\n resultflags(m32);\n build unlock;\n}\n\n@ifdef IA64\n:ADD^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x1; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n addflags(m64,Reg64);\n m64 = m64 + Reg64;\n resultflags(m64);\n build unlock;\n}\n@endif\n\n:AND^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=4 ...; imm8 \n{\n build lockx;\n build m8;\n logicalflags();\n m8 = m8 & imm8;\n resultflags(m8);\n build unlock;\n}\n\n:AND^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=4 ...; imm16 \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 & imm16;\n resultflags(m16);\n build unlock;\n}\n\n:AND^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=4 ...; imm32 \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 & imm32;\n resultflags(m32);\n build unlock;\n}\n\n@ifdef IA64\n:AND^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=4 ...; simm32 \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 & simm32;\n resultflags(m64);\n build unlock;\n}\n@endif\n\n:AND^lockx m16,usimm8_16\t\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=4 ...; usimm8_16\t\n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 & usimm8_16;\n resultflags(m16);\n build unlock;\n}\n\n:AND^lockx m32,usimm8_32\t\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=4 ...; usimm8_32\t\n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 & usimm8_32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:AND^lockx m64,usimm8_64\t\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=4 ...; usimm8_64\t\n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 & usimm8_64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:AND^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x20; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n logicalflags();\n m8 = m8 & Reg8;\n resultflags(m8);\n build unlock; \n}\n\n:AND^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x21; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 & Reg16;\n resultflags(m16);\n build unlock; \n}\n\n:AND^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x21; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 & Reg32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:AND^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x21; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 & Reg64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:BTC^lockx Mem,Reg16\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0xf; byte=0xbb; Mem & Reg16 ...\t\t\n{\n build lockx;\n build Mem;\n local ptr = Mem + (sext(Reg16) s>> 3);\n local bit=Reg16&7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr= *:1 ptr ^(1<> 3);\n@else\n local ptr = Mem + (Reg32 s>> 3);\n@endif\n local bit=Reg32&7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr ^ (1<> 3);\n local bit=Reg64&7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr ^ (1<>bit)&1;\n m16=m16^(1<>bit)&1;\n CF=(val!=0);\n m32=m32^(1<>bit)&1;\n m64=m64^(1<> 3);\n local bit=Reg16&7;\n local val=(*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr & ~(1<> 3);\n@else\n local ptr = Mem + (Reg32 s>> 3);\n@endif\n local bit = Reg32 & 7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr & ~(1<> 3);\n local bit = Reg64 & 7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr & ~(1<>bit)&1;\n m16=m16 & ~(1<>bit)&1;\n CF=(val!=0);\n m32=m32 & ~(1<>bit)&1;\n m64=m64 & ~(1<> 3);\n local bit = Reg16&7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr | (1<>3);\n@else\n local ptr = Mem + (Reg32 s>>3);\n@endif\n local bit = Reg32 & 7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr | (1<>3);\n local bit = Reg64 & 7;\n local val = (*:1 ptr >> bit) & 1;\n *:1 ptr = *:1 ptr | (1<>bit)&1;\n m16=m16 | (1<>bit)&1;\n CF=(val!=0);\n m32=m32 | (1<>bit)&1;\n m64=m64 | (1<;\n AL = dest;\n goto ;\n\n m8 = Reg8;\n\n build unlock;\n}\n\n:CMPXCHG^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xf; byte=0xb1; m16 & Reg16 ... \n{\n build lockx;\n local dest = m16;\n subflags(AX,dest); \n local diff = AX-dest; \n resultflags(diff);\n if (ZF) goto ;\n AX = dest;\n goto ;\n\n m16 = Reg16;\n\n build unlock; \n}\n\n:CMPXCHG^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xf; byte=0xb1; m32 & Reg32 ... & check_EAX_dest ...\n{\n build lockx;\n #this instruction writes to either EAX or Rmr32\n\t#in 64-bit mode, a 32-bit register that is written to \n\t#(and only the register that is written to) \n\t#must be zero-extended to 64 bits\n local dest = m32;\n subflags(EAX,dest); \n local diff = EAX-dest; \n resultflags(diff);\n if (ZF) goto ;\n EAX = dest;\n build check_EAX_dest;\n goto ;\n\n m32 = Reg32;\n\n build unlock;\n}\n\n@ifdef IA64\n:CMPXCHG^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf; byte=0xb1; m64 & Reg64 ... \n{\n build lockx;\n local dest = m64;\n subflags(RAX,dest); \n local diff = RAX-dest; \n resultflags(diff);\n if (ZF) goto ;\n RAX = dest;\n goto ;\n\n m64 = Reg64;\n\n build unlock;\n}\n@endif\n\n:CMPXCHG8B^lockx m64 is vexMode=0 & lockx & unlock & byte=0xf; byte=0xc7; ( mod != 0b11 & reg_opcode=1 ) ... & m64 \n{\n build lockx;\n local dest = m64;\n ZF = ((zext(EDX) << 32) | zext(EAX)) == dest;\n if (ZF == 1) goto ;\n EDX = dest(4);\n EAX = dest:4;\n goto ;\n\n m64 = (zext(ECX) << 32) | zext(EBX);\n \n build unlock;\n}\n\n@ifdef IA64\n:CMPXCHG16B^lockx m128\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf; byte=0xc7; ( mod != 0b11 & reg_opcode=1 ) ... & ( m128 ) {\n build lockx;\n local dest = m128;\n ZF = ((zext(RDX) << 64) | zext(RAX)) == dest;\n if (ZF == 1) goto ;\n RDX = dest(8);\n RAX = dest:8;\n goto ;\n\n m128 = ((zext(RCX) << 64) | zext(RBX));\n\n build unlock;\n}\n@endif\n\n:DEC^lockx m8 is vexMode=0 & lockx & unlock & byte=0xfe; m8 & reg_opcode=1 ... \n{\n build lockx;\n build m8;\n OF = sborrow(m8,1);\n m8 = m8 - 1;\n resultflags(m8);\n build unlock; \n}\n\n:DEC^lockx m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xff; m16 & reg_opcode=1 ... \n{\n build lockx;\n build m16;\n OF = sborrow(m16,1);\n m16 = m16 - 1;\n resultflags(m16);\n build unlock; \n}\n\n:DEC^lockx m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xff; m32 & reg_opcode=1 ... \n{\n build lockx;\n build m32;\n OF = sborrow(m32,1);\n m32 = m32 - 1;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:DEC^lockx m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xff; m64 & reg_opcode=1 ... \n{\n build lockx;\n build m64;\n OF = sborrow(m64,1);\n m64 = m64 - 1;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:INC^lockx m8\tis vexMode=0 & lockx & unlock & byte=0xfe; m8 ...\t\t\t\t\n{\n build lockx;\n build m8;\n OF = scarry(m8,1);\n m8 = m8 + 1;\n resultflags( m8);\n build unlock; \n}\n\n:INC^lockx m16\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0xff; m16 ...\t\n{\n build lockx;\n build m16;\n OF = scarry(m16,1);\n m16 = m16 + 1;\n resultflags(m16);\n build unlock; \n}\n\n:INC^lockx m32\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0xff; m32 ...\t\n{\n build lockx;\n build m32;\n OF = scarry(m32,1);\n m32 = m32 + 1;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:INC^lockx m64\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xff; m64 ... \n{\n build lockx;\n build m64;\n OF = scarry(m64,1);\n m64 = m64 + 1;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:NEG^lockx m8 is vexMode=0 & lockx & unlock & byte=0xf6; m8 & reg_opcode=3 ... \n{\n build lockx;\n build m8;\n negflags(m8);\n m8 = -m8;\n resultflags(m8);\n build unlock; \n}\n\n:NEG^lockx m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xf7; m16 & reg_opcode=3 ... \n{\n build lockx;\n build m16;\n negflags(m16);\n m16 = -m16;\n resultflags(m16);\n build unlock; \n}\n\n:NEG^lockx m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xf7; m32 & reg_opcode=3 ... \n{\n build lockx;\n build m32;\n negflags(m32);\n m32 = -m32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:NEG^lockx m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf7; m64 & reg_opcode=3 ... \n{\n build lockx;\n build m64;\n negflags(m64);\n m64 = -m64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:NOT^lockx m8 is vexMode=0 & lockx & unlock & byte=0xf6; m8 & reg_opcode=2 ... \n{\n build lockx;\n build m8;\n m8 = ~m8;\n build unlock; \n}\n\n:NOT^lockx m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xf7; m16 & reg_opcode=2 ... \n{\n build lockx;\n build m16;\n m16 = ~m16;\n build unlock; \n}\n\n:NOT^lockx m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xf7; m32 & reg_opcode=2 ... \n{\n build lockx;\n build m32;\n m32 = ~m32;\n build unlock; \n}\n\n@ifdef IA64\n:NOT^lockx m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf7; m64 & reg_opcode=2 ... \n{\n build lockx;\n build m64;\n m64 = ~m64;\n build unlock; \n}\n@endif\n\n:OR^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=1 ...; imm8 \n{\n build lockx;\n build m8;\n logicalflags();\n m8 = m8 | imm8;\n resultflags(m8);\n build unlock; \n}\n\n:OR^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=1 ...; imm16 \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 | imm16;\n resultflags(m16);\n build unlock; \n}\n\n:OR^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=1 ...; imm32 \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 | imm32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:OR^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=1 ...; simm32 \n{\n build lockx;\n build m64;\n logicalflags();\n tmp:8 = m64;\n m64 = tmp | simm32;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:OR^lockx m16,usimm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=1 ...; usimm8_16 \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 | usimm8_16;\n resultflags(m16);\n build unlock; \n}\n\n:OR^lockx m32,usimm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=1 ...; usimm8_32 \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 | usimm8_32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:OR^lockx m64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=1 ...; usimm8_64 \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 | usimm8_64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:OR^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x8; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n logicalflags();\n m8 = m8 | Reg8;\n resultflags(m8);\n build unlock; \n}\n\n:OR^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x9; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 | Reg16;\n resultflags(m16);\n build unlock; \n}\n\n:OR^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x9; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 | Reg32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:OR^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x9; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 | Reg64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:SBB^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=3 ...; imm8\t\t\t\t\t\t\t\t\n{\n build lockx;\n build m8;\n subCarryFlags(m8, imm8);\n resultflags(m8);\n build unlock; \n}\n\n:SBB^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=3 ...; imm16\t\t\t\t\t\t\t\n{\n build lockx;\n build m16;\n subCarryFlags(m16, imm16);\n resultflags(m16);\n build unlock; \n}\n\n:SBB^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=3 ...; imm32\t\n{\n build lockx;\n build m32;\n subCarryFlags(m32, imm32);\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:SBB^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=3 ...; simm32\t\t\t\t\t\t\t\n{\n build lockx;\n build m64;\n subCarryFlags(m64, simm32);\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:SBB^lockx m16,simm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=3 ...; simm8_16\t\t\t\t\t\t\n{\n build lockx;\n build m16;\n subCarryFlags(m16, simm8_16);\n resultflags(m16);\n build unlock; \n}\n\n:SBB^lockx m32,simm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=3 ...; simm8_32\t\n{\n build lockx;\n build m32;\n subCarryFlags(m32, simm8_32);\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:SBB^lockx m64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=3 ...; simm8_64\t\t\t\t\t\t\n{\n build lockx;\n build m64;\n subCarryFlags(m64, simm8_64);\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:SBB^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x18; m8 & Reg8 ...\t\t\t\t\t\t\t\t\t\t\t\n{\n build lockx;\n build m8;\n subCarryFlags(m8, Reg8);\n resultflags(m8);\n build unlock; \n}\n\n:SBB^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x19; m16 & Reg16 ...\t\t\t\t\t\t\n{\n build lockx;\n build m16;\n subCarryFlags(m16, Reg16);\n resultflags(m16);\n build unlock; \n}\n\n:SBB^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x19; m32 & Reg32 ...\t\n{\n build lockx;\n build m32;\n subCarryFlags(m32, Reg32);\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:SBB^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x19; m64 & Reg64 ...\t\t\t\t\t\t\n{\n build lockx;\n build m64;\n subCarryFlags(m64, Reg64);\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:SUB^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=5 ...; imm8 \n{\n build lockx;\n build m8;\n subflags(m8,imm8);\n m8 = m8 - imm8;\n resultflags(m8);\n build unlock; \n}\n\n:SUB^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=5 ...; imm16 \n{\n build lockx;\n build m16;\n subflags(m16,imm16);\n m16 = m16 - imm16;\n resultflags(m16);\n build unlock; \n}\n\n:SUB^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=5 ...; imm32 \n{\n build lockx;\n build m32;\n subflags(m32,imm32);\n m32 = m32 - imm32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:SUB^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=5 ...; simm32 \n{\n build lockx;\n build m64;\n subflags(m64,simm32);\n m64 = m64 - simm32;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:SUB^lockx m16,simm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=5 ...; simm8_16 \n{\n build lockx;\n build m16;\n subflags(m16,simm8_16);\n m16 = m16 - simm8_16;\n resultflags(m16);\n build unlock; \n}\n\n:SUB^lockx m32,simm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=5 ...; simm8_32 \n{\n build lockx;\n build m32;\n subflags(m32,simm8_32);\n m32 = m32 - simm8_32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:SUB^lockx m64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=5 ...; simm8_64 \n{\n build lockx;\n build m64;\n subflags(m64,simm8_64);\n m64 = m64 - simm8_64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:SUB^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x28; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n subflags(m8,Reg8);\n m8 = m8 - Reg8;\n resultflags(m8);\n build unlock; \n}\n\n:SUB^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x29; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n subflags(m16,Reg16);\n m16 = m16 - Reg16;\n resultflags(m16);\n build unlock; \n}\n\n:SUB^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x29; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n subflags(m32,Reg32);\n m32 = m32 - Reg32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:SUB^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x29; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n subflags(m64,Reg64);\n m64 = m64 - Reg64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:XADD^lockx m8,Reg8 \tis vexMode=0 & lockx & unlock & byte=0x0F; byte=0xC0; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n addflags( m8,Reg8);\n local tmp = m8 + Reg8;\n Reg8 = m8;\n m8 = tmp;\n resultflags(tmp);\n build unlock; \n}\n\n:XADD^lockx m16,Reg16\tis vexMode=0 & lockx & unlock & opsize=0 & byte=0x0F; byte=0xC1; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n addflags(m16,Reg16);\n local tmp = m16 + Reg16;\n Reg16 = m16;\n m16 = tmp;\n resultflags(tmp);\n build unlock; \n}\n\n:XADD^lockx m32,Reg32\tis vexMode=0 & lockx & unlock & opsize=1 & byte=0x0F; byte=0xC1; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n addflags(m32,Reg32);\n local tmp = m32 + Reg32;\n Reg32 = m32;\n m32 = tmp;\n resultflags(tmp);\n build unlock; \n}\n\n@ifdef IA64\n:XADD^lockx m64,Reg64\tis $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x0F; byte=0xC1; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n addflags(m64,Reg64);\n local tmp = m64 + Reg64;\n Reg64 = m64;\n m64 = tmp;\n resultflags(tmp);\n build unlock; \n}\n@endif\n\n# XCHG with memory operands always asserts a lock signal regardless of prefix presence\n:XCHG^xacq_xrel_prefx^alwaysLock m8,Reg8 is vexMode=0 & xacq_xrel_prefx & alwaysLock & byte=0x86; m8 & Reg8 ... \n{ \n build xacq_xrel_prefx;\n build alwaysLock; \n build m8;\n local tmp = m8; \n m8 = Reg8;\n Reg8 = tmp; \n UNLOCK();\n}\n\n:XCHG^xacq_xrel_prefx^alwaysLock m16,Reg16 is vexMode=0 & xacq_xrel_prefx & alwaysLock & opsize=0 & byte=0x87; m16 & Reg16 ... \n{ \n build xacq_xrel_prefx;\n build alwaysLock;\n build m16;\n local tmp = m16; \n m16 = Reg16; \n Reg16 = tmp; \n UNLOCK();\n}\n\n:XCHG^xacq_xrel_prefx^alwaysLock m32,Reg32 is vexMode=0 & xacq_xrel_prefx & alwaysLock & opsize=1 & byte=0x87; m32 & Reg32 ... \n{ \n build xacq_xrel_prefx;\n build alwaysLock;\n build m32;\n local tmp = m32; \n m32 = Reg32; \n Reg32 = tmp; \n UNLOCK(); \n}\n\n@ifdef IA64\n:XCHG^xacq_xrel_prefx^alwaysLock m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & xacq_xrel_prefx & alwaysLock & opsize=2 & byte=0x87; m64 & Reg64 ... \n{ \n build xacq_xrel_prefx; \n build alwaysLock;\n build m64;\n local tmp = m64; \n m64 = Reg64; \n Reg64 = tmp; \n UNLOCK(); \n}\n@endif\n\n:XOR^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=6 ...; imm8 \n{\n build lockx;\n build m8;\n logicalflags();\n m8 = m8 ^ imm8;\n resultflags(m8);\n build unlock; \n}\n\n:XOR^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=6 ...; imm16 \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 ^ imm16;\n resultflags(m16);\n build unlock; \n}\n\n:XOR^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=6 ...; imm32 \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 ^ imm32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:XOR^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=6 ...; simm32 \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 ^ simm32;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:XOR^lockx m16,usimm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=6 ...; usimm8_16 \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 ^ usimm8_16;\n resultflags(m16);\n build unlock; \n}\n\n:XOR^lockx m32,usimm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=6 ...; usimm8_32 \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 ^ usimm8_32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:XOR^lockx m64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=6 ...; usimm8_64 \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 ^ usimm8_64;\n resultflags(m64);\n build unlock; \n}\n@endif\n\n:XOR^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x30; m8 & Reg8 ... \n{\n build lockx;\n build m8;\n logicalflags();\n m8 = m8 ^ Reg8;\n resultflags(m8);\n build unlock; \n}\n\n:XOR^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x31; m16 & Reg16 ... \n{\n build lockx;\n build m16;\n logicalflags();\n m16 = m16 ^ Reg16;\n resultflags(m16);\n build unlock; \n}\n\n:XOR^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x31; m32 & Reg32 ... \n{\n build lockx;\n build m32;\n logicalflags();\n m32 = m32 ^ Reg32;\n resultflags(m32);\n build unlock; \n}\n\n@ifdef IA64\n:XOR^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x31; m64 & Reg64 ... \n{\n build lockx;\n build m64;\n logicalflags();\n m64 = m64 ^ Reg64;\n resultflags(m64);\n build unlock; \n}\n@endif\n" }, { "path": "pypcode/processors/x86/data/languages/lzcnt.sinc", "content": "macro lzcntflags(input, output) {\n ZF = (output == 0);\n CF = (input == 0);\n # OF, SF, PF, AF are undefined\n}\n\n####\n#### LZCNT instructions\n####\n\n\n:LZCNT Reg16, rm16\tis vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg16 ... & rm16 {\n\n Reg16 = lzcount(rm16);\n lzcntflags(rm16, Reg16);\n}\n\n:LZCNT Reg32, rm32\tis vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg32 ... & check_Reg32_dest ... & rm32 {\n\n Reg32 = lzcount(rm32);\n lzcntflags(rm32, Reg32);\n build check_Reg32_dest;\n}\n\n@ifdef IA64\n:LZCNT Reg64, rm64\tis $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBD; Reg64 ... & rm64 {\n\n Reg64 = lzcount(rm64);\n lzcntflags(rm64, Reg64);\n}\n@endif\n\n" }, { "path": "pypcode/processors/x86/data/languages/macros.sinc", "content": "macro conditionalAssign(dest, cond, trueVal, falseVal) {\n dest = zext(cond) * trueVal | zext(!cond) * falseVal;\t\n}" }, { "path": "pypcode/processors/x86/data/languages/mpx.sinc", "content": "define pcodeop br_exception;\n\n\n# BNDMK needs the base address register only\n# - if no base register, needs 0\n\n@ifdef IA64\nbndmk_addr64: [Rmr64]\t\t\t\t\t\t\tis mod=0 & Rmr64\t\t\t\t\t\t\t\t\t\t\t\t\t{ export Rmr64; }\nbndmk_addr64: [Rmr64 + simm8_64]\t\t\t\tis mod=1 & Rmr64; simm8_64\t\t\t\t\t\t\t\t\t\t\t{ export Rmr64; }\nbndmk_addr64: [simm32_64 + Rmr64]\t\t\t\tis mod=2 & Rmr64; simm32_64\t\t\t\t\t\t\t\t\t\t\t{ export Rmr64; }\nbndmk_addr64: [Rmr64]\t\t\t\t\t\t\tis mod=1 & r_m!=4 & Rmr64; simm8=0\t\t\t\t\t\t\t\t\t{ export Rmr64; }\nbndmk_addr64: [Rmr64]\t\t\t\t\t\t\tis mod=2 & r_m!=4 & Rmr64; simm32=0\t\t\t\t\t\t\t\t\t{ export Rmr64; }\n#invalid bndmk_addr64: [riprel]\t\t\t\t \tis mod=0 & r_m=5; simm32 [ riprel=inst_next+simm32; ]\t\t\t\t{ export *[const]:8 riprel; }\nbndmk_addr64: [Base64 + Index64*ss]\t\t\t\tis mod=0 & r_m=4; Index64 & Base64 & ss\t\t\t\t\t\t\t\t{ export Base64; }\nbndmk_addr64: [Base64]\t\t\t\t\t\t\tis mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64\t\t\t\t\t{ export Base64; }\nbndmk_addr64: [simm32_64 + Index64*ss]\t\t\tis mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64\t\t\t\t{ tmp:8 = 0; export tmp; }\nbndmk_addr64: [Index64*ss]\t\t\t\t\t\tis mod=0 & r_m=4; Index64 & base64=5 & ss; imm32=0\t\t\t\t\t{ tmp:8 = 0; export tmp; }\nbndmk_addr64: [simm32_64]\t\t\t\t\t\tis mod=0 & r_m=4; rexXprefix=0 & index64=4 & base64=5; simm32_64\t{ tmp:8 = 0; export tmp; }\nbndmk_addr64: [Base64 + Index64*ss + simm8_64]\tis mod=1 & r_m=4; Index64 & Base64 & ss; simm8_64\t\t\t\t\t{ export Base64; }\nbndmk_addr64: [Base64 + Index64*ss]\t\t\t\tis mod=1 & r_m=4; Index64 & Base64 & ss; simm8=0\t\t\t\t\t{ export Base64; }\nbndmk_addr64: [Base64 + simm8_64]\t\t\t\tis mod=1 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm8_64\t\t{ export Base64; }\nbndmk_addr64: [simm32_64 + Base64 + Index64*ss]\tis mod=2 & r_m=4; Index64 & Base64 & ss; simm32_64\t\t\t\t\t{ export Base64; }\nbndmk_addr64: [simm32_64 + Base64]\t\t\t\tis mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm32_64\t\t{ export Base64; }\nbndmk_addr64: [Base64 + Index64*ss]\t\t\t\tis mod=2 & r_m=4; Index64 & Base64 & ss; imm32=0\t\t\t\t\t{ export Base64; }\nbndmk_addr64: [Base64]\t\t\t\t\t\t\tis mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0\t\t{ export Base64; }\n@endif\n\nbndmk_addr32: [Rmr32]\t\t\t\t\t\t\tis mod=0 & Rmr32\t\t\t\t\t\t\t\t{ export Rmr32; }\nbndmk_addr32: [Rmr32 + simm8_32]\t\t\t\tis mod=1 & Rmr32; simm8_32\t\t\t\t\t\t{ export Rmr32; }\nbndmk_addr32: [Rmr32]\t\t\t\t\t\t\tis mod=1 & r_m!=4 & Rmr32; simm8=0\t\t\t\t{ export Rmr32; }\nbndmk_addr32: [imm32 + Rmr32]\t\t\t\t\tis mod=2 & Rmr32; imm32\t\t\t\t\t\t\t{ export Rmr32; }\nbndmk_addr32: [Rmr32]\t\t\t\t\t\t\tis mod=2 & r_m!=4 & Rmr32; imm32=0\t\t\t\t{ export Rmr32; }\nbndmk_addr32: [imm32]\t\t\t\t\t\t\tis mod=0 & r_m=5; imm32\t\t\t\t\t\t\t{ tmp:4 = 0; export tmp; }\nbndmk_addr32: [Base + Index*ss]\t\t\t\t\tis mod=0 & r_m=4; Index & Base & ss\t\t\t\t{ export Base; }\nbndmk_addr32: [Base]\t\t\t\t\t\t\tis mod=0 & r_m=4; index=4 & Base\t\t\t\t{ export Base; }\nbndmk_addr32: [imm32 + Index*ss]\t\t\t\tis mod=0 & r_m=4; Index & base=5 & ss; imm32\t{ tmp:4 = 0; export tmp; }\nbndmk_addr32: [imm32]\t\t\t\t\t\t\tis mod=0 & r_m=4; index=4 & base=5; imm32\t\t{ tmp:4 = 0; export tmp; }\nbndmk_addr32: [Base + Index*ss + simm8_32]\t\tis mod=1 & r_m=4; Index & Base & ss; simm8_32\t{ export Base; }\nbndmk_addr32: [Base + simm8_32]\t\t\t\t\tis mod=1 & r_m=4; index=4 & Base; simm8_32\t\t{ export Base; }\nbndmk_addr32: [Base + Index*ss]\t\t\t\t\tis mod=1 & r_m=4; Index & Base & ss; simm8=0\t{ export Base; }\nbndmk_addr32: [Base]\t\t\t\t\t\t\tis mod=1 & r_m=4; index=4 & Base; simm8=0\t\t{ export Base; }\nbndmk_addr32: [imm32 + Base + Index*ss]\t\t\tis mod=2 & r_m=4; Index & Base & ss; imm32\t\t{ export Base; }\nbndmk_addr32: [imm32 + Base]\t\t\t\t\tis mod=2 & r_m=4; index=4 & Base; imm32\t\t\t{ export Base; }\nbndmk_addr32: [Base + Index*ss]\t\t\t\t\tis mod=2 & r_m=4; Index & Base & ss; imm32=0\t{ export Base; }\nbndmk_addr32: [Base]\t\t\t\t\t\t\tis mod=2 & r_m=4; index=4 & Base; imm32=0\t\t{ export Base; }\n\n\n\n@ifdef IA64\n\n:BNDCL bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_lb & Rmr64 {\n# if (reg < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(Rmr64 < bnd1_lb) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCL bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_lb) ... & Mem {\n# if (LEA(mem) < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(Mem < bnd1_lb) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCU bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_ub & Rmr64 {\n# if (reg > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(Rmr64 > ~bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCU bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_ub) ... & Mem {\n# if (LEA(mem) > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(Mem > ~bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCN bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd1_ub & Rmr64 {\n# if (reg > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(Rmr64 > bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCN bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; (bnd1 & bnd1_ub) ... & Mem {\n# if (LEA(mem) > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(Mem > bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n#TODO: This probably cannot be fully modeled \n:BNDLDX bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0x1A; bnd1 ... & Mem {\n#\tBNDSTATUS = bndldx_status( Mem, BNDCFGS, BNDCFGU );\n#\tbnd1 = bndldx( Mem, BNDCFGS, BNDCFGU );\n\t\n# core implementation\n bnd1 = *:16 Mem;\n}\n\n:BNDMK bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & ( bndmk_addr64 & Mem ) {\n# BND.LB and BND.UB set from m64\n\tbnd1_lb = bndmk_addr64;\n\tbnd1_ub = Mem;\n}\n\n:BNDMOV bnd1, m128 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; bnd1 ... & m128 {\n\tbnd1 = m128;\n}\n\n:BNDMOV bnd1, bnd2 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd2 {\n\tbnd1 = bnd2;\n}\n\n:BNDMOV m128, bnd1 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; bnd1 ... & m128 {\n\tm128 = bnd1;\n}\n\n:BNDMOV bnd2, bnd1 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd2 {\n\tbnd2 = bnd1;\n}\n\n#TODO: This probably cannot be fully modeled \n:BNDSTX Mem, bnd1 is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0x1B; bnd1 ... & Mem {\n#\tBNDSTATUS = bndstx_status( bnd1, BNDCFGS, BNDCFGU );\n#\tMem = bndstx( bnd1, BNDCFGS, BNDCFGU );\n\n# core implementation\n *:16 Mem = bnd1;\n}\n\n@endif\n\n:BNDCL bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_lb & Rmr32 {\n# if (reg < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(zext(Rmr32) < bnd1_lb) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCL bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_lb) ... & Mem {\n# if (LEA(mem) < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(zext(Mem) < bnd1_lb) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCU bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_ub & Rmr32 {\n# if (reg > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(zext(Rmr32) > ~bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCU bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_ub) ... & Mem {\n# if (LEA(mem) > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(zext(Mem) > ~bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCN bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd1_ub & Rmr32 {\n# if (reg > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(zext(Rmr32) > bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n:BNDCN bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; (bnd1 & bnd1_ub) ... & Mem {\n# if (LEA(mem) > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION\n if !(zext(Mem) > bnd1_ub) goto ;\n BNDSTATUS = 0x01;\n br_exception();\n \n}\n\n#TODO: This probably cannot be fully modeled \n:BNDLDX bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0x1A; ( bnd1 & bnd1_lb & bnd1_ub ) ... & Mem {\n#\tBNDSTATUS = bndldx_status( Mem, BNDCFGS, BNDCFGU );\n#\tbnd1 = bndldx( Mem, BNDCFGS, BNDCFGU );\n\t\n# core implementation\n tmp:8 = *:8 Mem;\n bnd1_lb = zext(tmp:4);\n tmp2:4 = tmp(4);\n bnd1_ub = zext(tmp2);\n}\n\n:BNDMK bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & ( bndmk_addr32 & Mem ) {\n# BND.LB and BND.UB set from m32\n\tbnd1_lb = zext(bndmk_addr32);\n\tbnd1_ub = zext(Mem);\n}\n\n:BNDMOV bnd1, m64 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; ( bnd1 & bnd1_lb & bnd1_ub ) ... & m64 {\n\ttmp:8 = m64;\n\tbnd1_lb = zext(tmp:4);\n tmp2:4 = tmp(4);\n bnd1_ub = zext(tmp2);\n}\n\n:BNDMOV bnd1, bnd2 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd2 {\n\tbnd1 = bnd2;\n}\n\n:BNDMOV m64, bnd1 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & m64 {\n\tm64 = (zext(bnd1_ub:4) << 32) | zext(bnd1_lb:4);\n}\n\n:BNDMOV bnd2, bnd1 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd2 {\n\tbnd2 = bnd1;\n}\n\n#TODO: This probably cannot be fully modeled \n:BNDSTX Mem, bnd1 is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & Mem {\n#\tBNDSTATUS = bndstx_status( bnd1, BNDCFGS, BNDCFGU );\n#\tMem = bndstx( bnd1, BNDCFGS, BNDCFGU );\n\n# core implementation\n *:8 Mem = (zext(bnd1_ub:4) << 32) | zext(bnd1_lb:4);\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86RealV1.lang", "content": "\n\n \n x86:LE:16:Real Mode\n x86\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86RealV1.trans", "content": "\n\n x86:LE:16:Real Mode\n x86:LE:16:Real Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86RealV2.lang", "content": "\n\n \n x86:LE:16:Real Mode\n x86\n Real Mode\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86RealV2.trans", "content": "\n\n x86:LE:16:Real Mode\n x86:LE:16:Real Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86RealV3.lang", "content": "\n\n \n x86:LE:16:Real Mode\n x86\n Real Mode\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86RealV3.trans", "content": "\n\n x86:LE:16:Real Mode\n x86:LE:16:Real Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86V1.lang", "content": "\n\n \n x86:LE:32:default\n x86\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86V1.trans", "content": "\n\n x86:LE:32:default\n x86:LE:32:default\n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86V2.lang", "content": "\n\n \n x86:LE:32:default\n x86\n default\n 32\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86V2.trans", "content": "\n\n x86:LE:32:default\n x86:LE:32:default\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86V3.lang", "content": "\n\n \n x86:LE:32:default\n x86\n default\n 32\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86V3.trans", "content": "\n\n x86:LE:32:default\n x86:LE:32:default\n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_compat32_v2.lang", "content": "\n\n \n x86:LE:64:compat32\n x86\n compat32\n 64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_compat32_v2.trans", "content": "\n\n x86:LE:64:compat32\n x86:LE:64:compat32\n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_compat32_v3.lang", "content": "\n\n \n x86:LE:64:compat32\n x86\n compat32\n 64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_compat32_v3.trans", "content": "\n\n x86:LE:64:compat32\n x86:LE:64:compat32\n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_v1.lang", "content": "\n\n \n x64:LE:64:default\n x64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_v1.trans", "content": "\n\n x64:LE:64:default\n x86:LE:64:default\n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_v2.lang", "content": "\n\n \n x86:LE:64:default\n x86\n default\n 64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_v2.trans", "content": "\n\n x86:LE:64:default\n x86:LE:64:default\n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_v3.lang", "content": "\n\n \n x86:LE:64:default\n x86\n default\n 64\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_64bit_v3.trans", "content": "\n\n x86:LE:64:default\n x86:LE:64:default\n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_ProtV2.lang", "content": "\n\n \n x86:LE:16:Protected Mode\n x86\n Protected Mode\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_ProtV2.trans", "content": "\n\n x86:LE:16:Protected Mode\n x86:LE:16:Protected Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_ProtV3.lang", "content": "\n\n \n x86:LE:16:Protected Mode\n x86\n Protected Mode\n 16\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86_ProtV3.trans", "content": "\n\n x86:LE:16:Protected Mode\n x86:LE:16:Protected Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86smmV1.lang", "content": "\n\n \n x86:LE:32:System Management Mode\n x86\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86smmV1.trans", "content": "\n\n x86:LE:32:System Management Mode\n x86:LE:32:System Management Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86smmV2.lang", "content": "\n\n \n x86:LE:32:System Management Mode\n x86\n System Management Mode\n 32\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86smmV2.trans", "content": "\n\n x86:LE:32:System Management Mode\n x86:LE:32:System Management Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86smmV3.lang", "content": "\n\n \n x86:LE:32:System Management Mode\n x86\n System Management Mode\n 32\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/old/x86smmV3.trans", "content": "\n\n x86:LE:32:System Management Mode\n x86:LE:32:System Management Mode\n \n\n\n" }, { "path": "pypcode/processors/x86/data/languages/pclmulqdq.sinc", "content": "# Due to limitations on variable length matching that preclude opcode matching afterwards, all memory addressing forms of PCLMULQDQ are decoded to PCLMULQDQ, not the macro names.\n# Display is non-standard, but semantics, and de-compilation should be correct.\n\nmacro pclmul(src1, src2, dest) {\n local i:4 = 0:4;\n local temp:16 = 0;\n\n \n if (i > 63:4) goto ;\n if ((src1 & (1 << i)) == 0) goto ; \n temp = temp ^ (src2 << i);\n \n i = i+1;\n goto ;\n \n dest = temp;\n}\n\n:PCLMULLQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x00\n{\n local src1:16 = zext(XmmReg1[0,64]);\n local src2:16 = zext(XmmReg2[0,64]);\n pclmul(src1,src2,XmmReg1);\n}\n\n:PCLMULHQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x01\n{\n local src1:16 = zext(XmmReg1[64,64]);\n local src2:16 = zext(XmmReg2[0,64]);\n pclmul(src1,src2,XmmReg1);\n}\n\n:PCLMULLQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x10\n{\n local src1:16 = zext(XmmReg1[0,64]);\n local src2:16 = zext(XmmReg2[64,64]);\n pclmul(src1,src2,XmmReg1);\n}\n\n:PCLMULHQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x11\n{\n local src1:16 = zext(XmmReg1[64,64]);\n local src2:16 = zext(XmmReg2[64,64]);\n pclmul(src1,src2,XmmReg1);\n}\n\n:PCLMULQDQ XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; imm8 & imm8_4 & imm8_0\n{\n\tif (imm8_0:1) goto ;\n\t\tsrc1:16 = zext(XmmReg1[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc1 = zext(XmmReg1[64,64]);\n\t\n\t\n\t\t\n\tif (imm8_4:1) goto ;\n\t\tsrc2:16 = zext(XmmReg2[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc2 = zext(XmmReg2[64,64]);\n\t\t\n\t\n\t\n pclmul(src1,src2,XmmReg1); \n}\n\n:PCLMULQDQ XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; XmmReg ... & m128; imm8 & imm8_4 & imm8_0\n{\n\tif (imm8_0:1) goto ;\n\t\tsrc1:16 = zext(XmmReg[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc1 = zext(XmmReg[64,64]);\n\t\n\t\n local m:16 = m128;\t\t\n\tif (imm8_4:1) goto ;\n\t\tsrc2:16 = zext(m[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc2 = zext(m[64,64]);\n\t\t\n\t\n\t\n pclmul(src1,src2,XmmReg);\n}\n\n:VPCLMULLQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x00\n{\n local src1:16 = zext(vexVVVV_XmmReg[0,64]);\n local src2:16 = zext(XmmReg2[0,64]);\n pclmul(src1,src2,XmmReg1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n:VPCLMULHQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x01\n{\n local src1:16 = zext(vexVVVV_XmmReg[64,64]);\n local src2:16 = zext(XmmReg2[0,64]);\n pclmul(src1,src2,XmmReg1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n:VPCLMULLQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x10\n{\n local src1:16 = zext(vexVVVV_XmmReg[0,64]);\n local src2:16 = zext(XmmReg2[64,64]);\n pclmul(src1,src2,XmmReg1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n:VPCLMULHQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x11\n{\n local src1:16 = zext(vexVVVV_XmmReg[64,64]);\n local src2:16 = zext(XmmReg2[64,64]);\n pclmul(src1,src2,XmmReg1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; imm8 & imm8_4 & imm8_0\n{\n\tif (imm8_0:1) goto ;\n\t\tsrc1:16 = zext(vexVVVV_XmmReg[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc1 = zext(vexVVVV_XmmReg[64,64]);\n\t\n\t\n\t\t\n\tif (imm8_4:1) goto ;\n\t\tsrc2:16 = zext(XmmReg2[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc2 = zext(XmmReg2[64,64]);\n\t\t\n\t\n\t\n pclmul(src1,src2,XmmReg1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; (XmmReg1 & YmmReg1) ... & m128; imm8 & imm8_4 & imm8_0\n{\n\tif (imm8_0:1) goto ;\n\t\tsrc1:16 = zext(vexVVVV_XmmReg[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc1 = zext(vexVVVV_XmmReg[64,64]);\n\t\n\t\n\n local m:16 = m128;\n\tif (imm8_4:1) goto ;\n\t\tsrc2:16 = zext(m[0,64]);\n\t\tgoto ;\n\t\t\n\t\n\t\tsrc2 = zext(m[64,64]);\n\t\t\n\t\n\t\n pclmul(src1,src2,XmmReg1);\n\tYmmReg1 = zext(XmmReg1);\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/rdrand.sinc", "content": "define pcodeop rdrand;\ndefine pcodeop rdrandIsValid;\n\nmacro rdflags(){\n\tOF = 0; SF = 0; ZF = 0; AF = 0; PF = 0;\n}\n\n:RDRAND Rmr16 is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; mod=3 & Rmr16 & reg_opcode=6 \n{ \n\tRmr16 = rdrand(); \n\tCF=rdrandIsValid();\n\trdflags();\n\t\n}\n:RDRAND Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=6 \n{ \n\tRmr32 = rdrand(); \n\tCF=rdrandIsValid();\n\trdflags();\n}\n@ifdef IA64\n:RDRAND Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=6 \n{ \n\tRmr64 = rdrand(); \n\tCF=rdrandIsValid();\n\trdflags();\n}\n@endif\n\ndefine pcodeop rdseed;\ndefine pcodeop rdseedIsValid;\n:RDSEED Rmr16 is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; mod=3 & Rmr16 & reg_opcode=7 \n{ \n\tRmr16 = rdseed(); \n\tCF=rdseedIsValid();\n\trdflags();\n}\n:RDSEED Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=7 \n{ \n\tRmr32 = rdseed(); \n\tCF=rdseedIsValid();\n\trdflags();\n}\n@ifdef IA64\n:RDSEED Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=7 \n{ \n\tRmr64 = rdseed(); \n\tCF=rdseedIsValid();\n\trdflags();\n}\n@endif\n" }, { "path": "pypcode/processors/x86/data/languages/sgx.sinc", "content": "define pcodeop encls_ecreate;\ndefine pcodeop encls_eadd;\ndefine pcodeop encls_einit;\ndefine pcodeop encls_einit_ZF;\ndefine pcodeop encls_eremove;\ndefine pcodeop encls_eremove_ZF;\ndefine pcodeop encls_edbgrd;\ndefine pcodeop encls_edbgrd_RBX;\ndefine pcodeop encls_edbgwr;\ndefine pcodeop encls_eextend;\ndefine pcodeop encls_eldb;\ndefine pcodeop encls_eldb_ZF;\ndefine pcodeop encls_eldu;\ndefine pcodeop encls_eldu_ZF;\ndefine pcodeop encls_eblock;\ndefine pcodeop encls_eblock_ZF;\ndefine pcodeop encls_epa;\ndefine pcodeop encls_ewb;\ndefine pcodeop encls_ewb_ZF;\ndefine pcodeop encls_ewb_CF;\ndefine pcodeop encls_etrack;\ndefine pcodeop encls_etrack_ZF;\ndefine pcodeop encls_eaug;\ndefine pcodeop encls_emodpr;\ndefine pcodeop encls_emodpr_ZF;\ndefine pcodeop encls_emodt;\ndefine pcodeop encls_emodt_ZF;\ndefine pcodeop encls_unknown;\n\n:ENCLS is vexMode=0 & byte=0x0f; byte=0x01; byte=0xcf {\n\n\tif ( EAX != 0x0 ) goto ;\n\t\tencls_ecreate( RBX, RCX );\n\t\tgoto ;\n\t\t\n\t\n\tif ( EAX != 0x1 ) goto ;\n\t\tencls_eadd( RBX, RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x2 ) goto ;\n\t\tRAX = encls_einit( RBX, RCX, RDX );\n\t\tZF = encls_einit_ZF( RBX, RCX, RDX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x3 ) goto ;\n\t\tRAX = encls_eremove( RCX );\n\t\tZF = encls_eremove_ZF( RBX, RCX, RDX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x4 ) goto ;\n\t\tRAX = encls_edbgrd( RCX );\n\t\tRBX = encls_edbgrd_RBX( RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x5 ) goto ;\n\t\tRAX = encls_edbgwr( RBX, RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x6 ) goto ;\n\t\tencls_eextend( RBX, RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x7 ) goto ;\n\t\tRAX = encls_eldb( RBX, RCX, RDX );\n\t\tZF = encls_eldb_ZF( RBX, RCX, RDX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x8 ) goto ;\n\t\tRAX = encls_eldu( RBX, RCX, RDX );\n\t\tZF = encls_eldu_ZF( RBX, RCX, RDX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x9 ) goto ;\n\t\tRAX = encls_eblock( RCX );\n\t\tZF = encls_eblock_ZF( RCX );\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0xA ) goto ;\n\t\tencls_epa( RBX, RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0xB ) goto ;\n\t\tRAX = encls_ewb( RBX, RCX, RDX );\n\t\tZF = encls_ewb_ZF( RBX, RCX, RDX );\n\t\tCF = encls_ewb_CF( RBX, RCX, RDX );\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0xC ) goto ;\n\t\tRAX = encls_etrack( RCX );\n\t\tZF = encls_etrack_ZF( RBX, RCX, RDX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0xD ) goto ;\n\t\tencls_eaug( RBX, RCX, RDX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0xE ) goto ;\n\t\tRAX = encls_emodpr( RBX, RCX );\n\t\tZF = encls_emodpr_ZF( RCX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0xF ) goto ;\n\t\tRAX = encls_emodt( RBX, RCX );\n\t\tZF = encls_emodt_ZF( RCX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\t\tencls_unknown();\n\n\t\t\t\n}\n\n\ndefine pcodeop enclu_ereport;\ndefine pcodeop enclu_egetkey;\ndefine pcodeop enclu_egetkey_ZF;\ndefine pcodeop enclu_eenter_EAX;\ndefine pcodeop enclu_eenter_RCX;\ndefine pcodeop enclu_eenter_TF;\ndefine pcodeop enclu_eresume;\ndefine pcodeop enclu_eexit;\ndefine pcodeop enclu_eexit_TF;\ndefine pcodeop enclu_eaccept;\ndefine pcodeop enclu_eaccept_ZF;\ndefine pcodeop enclu_emodpe;\ndefine pcodeop enclu_eacceptcopy;\ndefine pcodeop enclu_eacceptcopy_ZF;\ndefine pcodeop enclu_unknown;\n\n:ENCLU is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd7 {\n\n\tif ( EAX != 0x0 ) goto ;\n\t\tenclu_ereport( RBX, RCX, RDX );\n\t\tgoto ;\n\t\t\n\t\n\tif ( EAX != 0x1 ) goto ;\n\t\tRAX = enclu_egetkey( RBX, RCX );\n\t\tZF = enclu_egetkey_ZF( RBX, RCX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x2 ) goto ;\n\t\ttempBX:8 = RBX;\n\t\ttempCX:8 = RCX;\n\t\t\n\t\tEAX = enclu_eenter_EAX( tempBX, tempCX );\n\t\tRCX = enclu_eenter_RCX( tempBX, tempCX );\n\t\tTF = enclu_eenter_TF( tempBX, tempCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x3 ) goto ;\n\t\tTF = enclu_eresume( RBX, RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x4 ) goto ;\n\t\tRCX = enclu_eexit( RBX );\n\t\tTF = enclu_eexit_TF( RBX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x5 ) goto ;\n\t\tRAX = enclu_eaccept( RBX, RCX );\n\t\tZF = enclu_eaccept_ZF( RBX, RCX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x6 ) goto ;\n\t\tenclu_emodpe( RBX, RCX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x7 ) goto ;\n\t\tRAX = enclu_eacceptcopy( RBX, RCX, RDX );\n\t\tZF = enclu_eacceptcopy_ZF( RBX, RCX, RDX );\n\t\tCF = 0;\n\t\tPF = 0;\n\t\tAF = 0;\n\t\tOF = 0;\n\t\tSF = 0;\n\t\tgoto ;\n\n\t\n\t\tenclu_unknown();\n\n\t\t\t\n}\n" }, { "path": "pypcode/processors/x86/data/languages/sha.sinc", "content": "# INFO This file automatically generated by andre on Fri Mar 16 15:13:25 2018\n# INFO Direct edits to this file may be lost in future updates\n# INFO Command line arguments: ['--sinc', '--cpuid-match', 'SHA']\n\n# SHA1RNDS4 4-602 PAGE 1722 LINE 89511\ndefine pcodeop sha1rnds4_sha ;\n:SHA1RNDS4 XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & byte=0x0F; byte=0x3A; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8\n{\n\tXmmReg1 = sha1rnds4_sha( XmmReg1, XmmReg2_m128, imm8:1 );\n}\n\n# SHA1NEXTE 4-604 PAGE 1724 LINE 89602\ndefine pcodeop sha1nexte_sha ;\n:SHA1NEXTE XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = sha1nexte_sha( XmmReg1, XmmReg2_m128 );\n}\n\n# SHA1MSG1 4-605 PAGE 1725 LINE 89654\ndefine pcodeop sha1msg1_sha ;\n:SHA1MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = sha1msg1_sha( XmmReg1, XmmReg2_m128 );\n}\n\n# SHA1MSG2 4-606 PAGE 1726 LINE 89708\ndefine pcodeop sha1msg2_sha ;\n:SHA1MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = sha1msg2_sha( XmmReg1, XmmReg2_m128 );\n}\n\n# SHA256RNDS2 4-607 PAGE 1727 LINE 89765\ndefine pcodeop sha256rnds2_sha ;\n:SHA256RNDS2 XmmReg1, XmmReg2_m128, XMM0 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 & XMM0\n{\n\tXmmReg1 = sha256rnds2_sha( XmmReg1, XmmReg2_m128, XMM0 );\n}\n\n# SHA256MSG1 4-609 PAGE 1729 LINE 89847\ndefine pcodeop sha256msg1_sha ;\n:SHA256MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = sha256msg1_sha( XmmReg1, XmmReg2_m128 );\n}\n\n# SHA256MSG2 4-610 PAGE 1730 LINE 89900\ndefine pcodeop sha256msg2_sha ;\n:SHA256MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCD; (XmmReg1 & YmmReg1) ... & XmmReg2_m128\n{\n\tXmmReg1 = sha256msg2_sha( XmmReg1, XmmReg2_m128 );\n}\n\n" }, { "path": "pypcode/processors/x86/data/languages/smx.sinc", "content": "define pcodeop getsec_capabilities;\ndefine pcodeop getsec_enteraccs;\ndefine pcodeop getsec_exitac;\ndefine pcodeop getsec_senter;\ndefine pcodeop getsec_sexit;\ndefine pcodeop getsec_parameters_EAX;\ndefine pcodeop getsec_parameters_EBX;\ndefine pcodeop getsec_parameters_ECX;\ndefine pcodeop getsec_smctrl;\ndefine pcodeop getsec_wakeup;\ndefine pcodeop getsec_unknown;\n\n\n:GETSEC is vexMode=0 & byte=0x0f; byte=0x37 {\n\n\tif ( EAX != 0x0 ) goto ;\n\t EAX = 0;\n\t if ( EBX != 0x0 ) goto ;\n\t\tEAX = getsec_capabilities( EBX );\n\t\tgoto ;\n\t\t\n\t\n\tif ( EAX != 0x2 ) goto ;\n\t\tgetsec_enteraccs( EBX, ECX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x3 ) goto ;\n@ifdef IA64\n\t getsec_exitac( RBX, EDX );\n@else\n\t getsec_exitac( EBX, EDX );\n@endif\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x4 ) goto ;\n\t getsec_senter( EBX, ECX, EDX);\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x5 ) goto ;\n\t getsec_sexit();\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x6 ) goto ;\n\t EAX = getsec_parameters_EAX( EBX );\n\t ECX = getsec_parameters_ECX( EBX );\n\t EBX = getsec_parameters_EBX( EBX );\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x7 ) goto ;\n\t getsec_smctrl(EBX);\n\t\tgoto ;\n\n\t\n\tif ( EAX != 0x8 ) goto ;\n\t getsec_wakeup();\n\t\tgoto ;\n\n\t\n\t\tgetsec_unknown();\n\n\t\t\t\n}\n" }, { "path": "pypcode/processors/x86/data/languages/x86-16-real.pspec", "content": "\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-16.cspec", "content": "\n\n\n\n \n\t \n\t\n\t\n\t\n\t \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-16.gdis", "content": "\n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-16.pspec", "content": "\n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-32-golang.cspec", "content": "\n\n\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\n\t \n\t\n\t\n\t \n\t\n\n\t\n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\n\t\n\t \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\n\t\n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-32-golang.register.info", "content": "\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64-compat32.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64-gcc.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\n \n \n \t\n \n \n \n \n \n \n \n \n \t\n \t\n \n\t\n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n\t \n \n \n \n \n\t \n\t \n\t \n\t \n\t\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n \n \n\t \n\t \n\t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64-golang.cspec", "content": "\n\n\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\n\t\n\n\t\n\t\t\n\t\n\n\t\n\t\n\n\t\n\n\t\n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t \n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t \n\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t \n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t \n\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t \n\t\t\t\t \n\t\t\t\n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t \n\t\t\t \n\t\t\n\t\n \n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t \n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t \n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t \n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n \n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\t\n\t\t\t\n\t\t\n\t\n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64-golang.register.info", "content": "\n\t\n\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64-swift.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64-win.cspec", "content": "\n\n\n\n\n\n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \t \n \t \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64.dwarf", "content": "\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t\n\t\t \n\t\t \n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t\n\t\n\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86-64.slaspec", "content": "@define IA64 \"IA64\"\n@include \"x86.slaspec\"\nwith : lockprefx=0 {\n@include \"sgx.sinc\"\n@include \"fma.sinc\"\n}\n" }, { "path": "pypcode/processors/x86/data/languages/x86.dwarf", "content": "\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t \n\t\t\n\t\t \n\t\t \n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n\t\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\n\n" }, { "path": "pypcode/processors/x86/data/languages/x86.ldefs", "content": "\n\n\n \n Intel/AMD 32-bit x86\n \n \n \n \n \n \n \n \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n \n \n \n \n \n \n Intel/AMD 32-bit x86 System Management Mode\n \n \n \n \n Intel/AMD 16-bit x86 Real Mode\n \n\t\n\t\n\t\n\t\n\t\n\t\n \n \n \n \n Intel/AMD 16-bit x86 Protected Mode\n \n\t\n \n \n \n \n Intel/AMD 64-bit x86\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n Intel/AMD 64-bit x86 in 32-bit compatibility mode (long mode off)\n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86.opinion", "content": "\n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86.pspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86.slaspec", "content": "@include \"ia.sinc\"\n@include \"lockable.sinc\"\nwith : lockprefx=0 {\n@include \"avx.sinc\"\n@include \"avx_manual.sinc\"\n@include \"avx2.sinc\"\n@include \"avx2_manual.sinc\"\n@include \"avx512.sinc\"\n@include \"avx512_manual.sinc\"\n@include \"adx.sinc\"\n@include \"clwb.sinc\"\n@include \"pclmulqdq.sinc\"\n@include \"mpx.sinc\"\n@include \"lzcnt.sinc\"\n@include \"bmi1.sinc\"\n@include \"bmi2.sinc\"\n@include \"sha.sinc\"\n@include \"smx.sinc\"\n@include \"cet.sinc\"\n@include \"rdrand.sinc\"\n}\n" }, { "path": "pypcode/processors/x86/data/languages/x86borland.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86delphi.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86gcc.cspec", "content": "\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\t\n\t\n\t \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/languages/x86win.cspec", "content": "\n\n\n \n\t \n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\n\t\n \t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\t\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n \n\n\n \n \n \n \n \n \n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n\n \n\n \n \n \n \n \n \n \n\n\n\n \n \n \n \n \n\n\n\n \n \n \n \n \n \n \n \n\n\n\n \n \n \n \n\n\n\n \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/manuals/x86.idx", "content": "@325383-sdm-vol-2abcd.pdf [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z, Oct 2019 (325383-071US)]\nAAA, 120\nAAD, 122\nBLENDPS, 123\nAAM, 124\nAAS, 126\nADC, 128\nADCX, 131\nADD, 133\nADDPD, 135\nVADDPD, 135\nADDPS, 138\nVADDPS, 138\nADDSD, 141\nVADDSD, 141\nADDSS, 143\nVADDSS, 143\nADDSUBPD, 145\nVADDSUBPD, 145\nADDSUBPS, 147\nVADDSUBPS, 147\nADOX, 150\nAESDEC, 152\nVAESDEC, 152\nAESDECLAST, 154\nVAESDECLAST, 154\nAESENC, 156\nVAESENC, 156\nAESENCLAST, 158\nVAESENCLAST, 158\nAESIMC, 160\nVAESIMC, 160\nAESKEYGENASSIST, 161\nVAESKEYGENASSIST, 161\nAND, 163\nANDN, 165\nANDPD, 166\nVANDPD, 166\nANDPS, 169\nVANDPS, 169\nANDNPD, 172\nVANDNPD, 172\nANDNPS, 175\nVANDNPS, 175\nARPL, 178\nBLENDPD, 180\nVBLENDPD, 180\nBEXTR, 182\nBLENDPS, 183\nVBLENDPS, 183\nBLENDVPD, 185\nVBLENDVPD, 185\nBLENDVPS, 187\nVBLENDVPS, 187\nBLSI, 190\nBLSMSK, 191\nBLSR, 192\nBNDCL, 193\nBNDCU, 195\nBNDCN, 195\nBNDLDX, 197\nBNDMK, 200\nBNDMOV, 202\nBNDSTX, 205\nBOUND, 208\nBSF, 210\nBSR, 212\nBSWAP, 214\nBT, 215\nBTC, 217\nBTR, 219\nBTS, 221\nBZHI, 223\nCALL, 224\nCBW, 241\nCWDE, 241\nCDQE, 241\nCLAC, 242\nCLC, 243\nCLD, 244\nCLDEMOTE, 245\nCLFLUSH, 247\nCLFLUSHOPT, 249\nCLI, 251\nCLRSBSY, 253\nCLTS, 255\nCLWB, 256\nCMC, 258\nCMOV, 259\nCMOVA, 259\nCMOVAE, 259\nCMOVB, 259\nCMOVBE, 259\nCMOVC, 259\nCMOVE, 259\nCMOVG, 259\nCMOVGE, 259\nCMOVL, 259\nCMOVLE, 259\nCMOVNA, 259\nCMOVNAE, 259\nCMOVNB, 259\nCMOVNBE, 259\nCMOVNC, 259\nCMOVNE, 259\nCMOVNG, 259\nCMOVNGE, 259\nCMOVNL, 259\nCMOVNLE, 259\nCMOVNO, 259\nCMOVNP, 259\nCMOVNS, 259\nCMOVNZ, 259\nCMOVO, 259\nCMOVP, 259\nCMOVPE, 259\nCMOVPO, 259\nCMOVS, 259\nCMOVZ, 259\nCMP, 263\nCMPPD, 265\nVCMPPD, 265\nCMPEQPD, 267\nCMPLTPD, 267\nCMPLEPD, 267\nCMPUNORDPD, 267\nCMPNEQPD, 267\nCMPNLTPD, 267\nCMPNLEPD, 267\nCMPORDPD, 267\nVCMPEQPD, 268\nVCMPLTPD, 268\nVCMPLEPD, 268\nVCMPUNORDPD, 268\nVCMPNEPD, 268\nVCMPNLTPD, 268\nVCMPNLEPD, 268\nVCMPORDPD, 268\nVCMPEQ_UQPD, 268\nVCMPNGEPD, 268\nVCMPNGTPD, 268\nVCMPFALSEPD, 268\nVCMPNEQ_OQPD, 268\nVCMPGEPD, 268\nVCMPGTPD, 268\nVCMPTRUEPD, 268\nVCMPEQ_OSPD, 268\nVCMPLT_OQPD, 268\nVCMPLE_OQPD, 268\nVCMPUNORD_SPD, 268\nVCMPNEQ_USPD, 268\nVCMPNLT_UQPD, 268\nVCMPNLE_UQPD, 268\nVCMPORD_SPD, 268\nVCMPEQ_USPD, 268\nVCMPNGE_UQPD, 268\nVCMPNGT_UQPD, 268\nVCMPFALSE_OSPD, 268\nVCMPNEQ_OSPD, 268\nVCMPGE_OQPD, 268\nVCMPGT_OQPD, 268\nVCMPTRUE_USPD, 268\nCMPPS, 272\nVCMPPS, 272\nCMPEQPS, 273\nCMPLTPS, 273\nCMPLEPS, 273\nCMPUNORDPS, 273\nCMPNEQPS, 273\nCMPNLTPS, 273\nCMPNLEPS, 273\nCMPORDPS, 273\nVCMPEQPS, 274\nVCMPLTPS, 274\nVCMPLEPS, 274\nVCMPUNORDPS, 274\nVCMPNEQPS, 274\nVCMPNLTPS, 274\nVCMPNLEPS, 274\nVCMPORDPS, 274\nVCMPEQ_UQPS, 274\nVCMPNGEPS, 274\nVCMPNGTPS, 274\nVCMPFALSEPS, 274\nVCMPNEQ_OQPS, 274\nVCMPGEPS, 274\nVCMPGTPS, 274\nVCMPTRUEPS, 274\nVCMPEQ_OSPS, 274\nVCMPLT_OQPS, 274\nVCMPLE_OQPS, 274\nVCMPUNORD_SPS, 274\nVCMPNEQ_USPS, 274\nVCMPNLT_UQPS, 274\nVCMPNLE_UQPS, 274\nVCMPORD_SPS, 274\nVCMPEQ_USPS, 274\nVCMPNGE_UQPS, 274\nVCMPNGT_UQPS, 274\nVCMPFALSE_OSPS, 274\nVCMPNEQ_OSPS, 274\nVCMPGE_OQPS, 274\nVCMPGT_OQPS, 274\nVCMPTRUE_USPS, 274\nCMPS, 279\nCMPSB, 279\nCMPSW, 279\nCMPSQ, 279\nCMPSD, 283\nVCMPSD, 283\nCMPEQSD, 284\nCMPLTSD, 284\nCMPLESD, 284\nCMPUNORDSD, 284\nCMPNEQSD, 284\nCMPNLTSD, 284\nCMPNLESD, 284\nCMPORDSD, 284\nVCMPEQSD, 284\nVCMPLTSD, 284\nVCMPLESD, 284\nVCMPUNORDSD, 284\nVCMPNEQSD, 284\nVCMPNLTSD, 284\nVCMPNLESD, 284\nVCMPORDSD, 284\nVCMPEQ_UQSD, 284\nVCMPNGESD, 284\nVCMPNGTSD, 284\nVCMPFALSESD, 284\nVCMPNEQ_OQSD, 284\nVCMPGESD, 284\nVCMPGTSD, 285\nVCMPTRUESD, 285\nVCMPEQ_OSSD, 285\nVCMPLT_OQSD, 285\nVCMPLE_OQSD, 285\nVCMPUNORD_SSD, 285\nVCMPNEQ_USSD, 285\nVCMPNLT_UQSD, 285\nVCMPNLE_UQSD, 285\nVCMPORD_SSD, 285\nVCMPEQ_USSD, 285\nVCMPNGE_UQSD, 285\nVCMPNGT_UQSD, 285\nVCMPFALSE_OSSD, 285\nVCMPNEQ_OSSD, 285\nVCMPGE_OQSD, 285\nVCMPGT_OQSD, 285\nVCMPTRUE_USSD, 285\nCMPSS, 287\nVCMPSS, 287\nCMPEQSS, 288\nCMPLTSS, 288\nCMPLESS, 288\nCMPUNORDSS, 288\nCMPNEQSS, 288\nCMPNLTSS, 288\nCMPNLESS, 288\nCMPORDSS, 288\nVCMPEQSS, 288\nVCMPLTSS, 288\nVCMPLESS, 288\nVCMPUNORDSS, 288\nVCMPNEQSS, 288\nVCMPNLTSS, 288\nVCMPNLESS, 288\nVCMPORDSS, 288\nVCMPEQ_UQSS, 288\nVCMPNGESS, 288\nVCMPNGTSS, 288\nVCMPFALSESS, 288\nVCMPNEQ_OQSS, 288\nVCMPGESS, 288\nVCMPGTSS, 289\nVCMPTRUESS, 289\nVCMPEQ_OSSS, 289\nVCMPLT_OQSS, 289\nVCMPLE_OQSS, 289\nVCMPUNORD_SSS, 289\nVCMPNEQ_USSS, 289\nVCMPNLT_UQSS, 289\nVCMPNLE_UQSS, 289\nVCMPORD_SSS, 289\nVCMPEQ_USSS, 289\nVCMPNGE_UQSS, 289\nVCMPNGT_UQSS, 289\nVCMPFALSE_OSSS, 289\nVCMPNEQ_OSSS, 289\nVCMPGE_OQSS, 289\nVCMPGT_OQSS, 289\nVCMPTRUE_USSS, 289\nCMPXCHG, 291\nCMPXCHG8B, 293\nCMPXCHG16B, 293\nCOMISD, 296\nVCOMISD, 296\nCOMISS, 298\nVCOMISS, 298\nCPUID, 300\nCRC32, 339\nCVTDQ2PD, 342\nVCVTDQ2PD, 342\nCVTDQ2PS, 346\nVCVTDQ2PS, 346\nCVTPD2DQ, 349\nVCVTPD2DQ, 349\nCVTPD2PI, 353\nCVTPD2PS, 354\nVCVTPD2PS, 354\nCVTPI2PD, 358\nCVTPI2PS, 359\nCVTPS2DQ, 360\nVCVTPS2DQ, 360\nCVTPS2PD, 363\nVCVTPS2PD, 363\nCVTPS2PI, 366\nCVTSD2SI, 367\nVCVTSD2SI, 367\nCVTSD2SS, 369\nVCVTSD2SS, 369\nCVTSI2SD, 371\nVCVTSI2SD, 371\nCVTSI2SS, 373\nVCVTSI2SS, 373\nCVTSS2SD, 375\nVCVTSS2SD, 375\nCVTSS2SI, 377\nVCVTSS2SI, 377\nCVTTPD2DQ, 379\nVCVTTPD2DQ, 379\nCVTTPD2PI, 383\nCVTTPS2DQ, 384\nVCVTTPS2DQ, 384\nCVTTPS2PI, 387\nCVTTSD2SI, 388\nVCVTTSD2SI, 388\nCVTTSS2SI, 390\nVCVTTSS2SI, 390\nCWD, 392\nCDQ, 392\nCQO, 392\nDAA, 393\nDAS, 395\nDEC, 397\nDIV, 399\nDIVPD, 402\nVDIVPD, 402\nDIVPS, 405\nVDIVPS, 405\nDIVSD, 408\nVDIVSD, 408\nDIVSS, 410\nVDIVSS, 410\nDPPD, 412\nVDPPD, 412\nDPPS, 414\nVDPPS, 414\nEMMS, 417\nENTER, 420\nEXTRACTPS, 423\nVEXTRACTPS, 423\nF2XM1, 425\nFABS, 427\nFADD, 428\nFADDP, 428\nFIADD, 428\nFBLD, 431\nFBSTP, 433\nFCHS, 435\nFCLEX, 437\nFNCLEX, 437\nFCMOV, 439\nFCMOVB, 439\nFCMOVE, 439\nFCMOVBE, 439\nFCMOVU, 439\nFCMOVNB, 439\nFCMOVNE, 439\nFCMOVNBE, 439\nFCMOVNU, 439\nFCOM, 441\nFCOMP, 441\nFCOMPP, 441\nFCOMI, 444\nFCOMIP, 444\nFUCOMI, 444\nFUCOMIP, 444\nFCOS, 447\nFDECSTP, 449\nFDIV, 450\nFDIVP, 450\nFIDIV, 450\nFDIVR, 453\nFDIVRP, 453\nFIDIVR, 453\nFFREE, 456\nFICOM, 456\nFICOMP, 457\nFILD, 459\nFINCSTP, 461\nFINIT, 462\nFNINIT, 462\nFIST, 464\nFISTP, 464\nFISTTP, 467\nFLD, 469\nFLD1, 471\nFLDL2T, 471\nFLDL2E, 471\nFLDPI, 471\nFLDLG2, 471\nFLDLN2, 471\nFLDZ, 471\nFLDCW, 473\nFLDENV, 475\nFMUL, 477\nFMULP, 477\nFIMUL, 477\nFNOP, 480\nFPATAN, 481\nFPREM, 483\nFPREM1, 485\nFPTAN, 487\nFRNDINT, 489\nFRSTOR, 490\nFSAVE, 492\nFNSAVE, 492\nFSCALE, 495\nFSIN, 497\nFSINCOS, 499\nFSQRT, 501\nFST, 503\nFSTP, 503\nFSTCW, 505\nFNSTCW, 505\nFSTENV, 507\nFNSTENV, 507\nFSTSW, 509\nFNSTSW, 509\nFSUB, 511\nFSUBP, 511\nFISUB, 511\nFSUBR, 514\nFSUBRP, 514\nFISUBR, 514\nFTST, 517\nFUCOM, 519\nFUCOMP, 519\nFUCOMPP, 519\nFXAM, 522\nFXCH, 524\nFXRSTOR, 526\nFXRSTOR64, 526\nFXSAVE, 529\nFXSAVE64, 529\nFXTRACT, 537\nFYL2X, 539\nFYL2XP1, 541\nGF2P8AFFINEINVQB, 543\nGF2P8AFFINEQB, 546\nGF2P8MULB, 548\nHADDPD, 550\nVHADDPD, 550\nHADDPS, 553\nVHADDPS, 553\nHLT, 556\nHSUBPD, 557\nVHSUBPD, 557\nHSUBPS, 560\nVHSUBPS, 560\nIDIV, 563\nIMUL, 566\nIN, 570\nINC, 572\nINCSSPD, 574\nINCSSPQ, 574\nINS, 576\nINSB, 576\nINSW, 576\nINSD, 576\nINSERTPS, 579\nVINSERTPS, 579\nINT, 582\nINTO, 582\nINT3, 582\nINVD, 597\nINVLPG, 599\nINVPCID, 601\nIRET, 604\nIRETD, 604\nIRETQ, 604\nJ, 613\nJA, 613\nJAE, 613\nJB, 613\nJBE, 613\nJC, 613\nJCXZ, 613\nJECXZ, 613\nJRCXZ, 613\nJE, 613\nJG, 613\nJGE, 613\nJL, 613\nJLE, 613\nJNA, 613\nJNAE, 613\nJNB, 613\nJNBE, 613\nJNC, 613\nJNE, 613\nJNG, 613\nJNGE, 613\nJNL, 613\nJNLE, 613\nJNO, 613\nJNP, 613\nJNS, 613\nJNZ, 613\nJO, 613\nJP, 613\nJPE, 613\nJPO, 613\nJS, 613\nJZ, 613\nJMP, 618\nKADDW, 627\nKADDB, 627\nKADDQ, 627\nKADDD, 627\nKANDW, 628\nKANDB, 628\nKANDQ, 628\nKANDD, 628\nKANDNW, 629\nKANDNB, 629\nKANDNQ, 629\nKANDND, 629\nKMOVW, 630\nKMOVB, 630\nKMOVQ, 630\nKMOVD, 630\nKNOTW, 632\nKNOTB, 632\nKNOTQ, 632\nKNOTD, 632\nKORW, 633\nKORB, 633\nKORQ, 633\nKORD, 633\nKORTESTW, 634\nKORTESTB, 634\nKORTESTQ, 634\nKORTESTD, 634\nKSHIFTLW, 636\nKSHIFTLB, 636\nKSHIFTLQ, 636\nKSHIFTLD, 636\nKSHIFTRW, 638\nKSHIFTRB, 638\nKSHIFTRQ, 638\nKSHIFTRD, 638\nKTESTW, 640\nKTESTB, 640\nKTESTQ, 640\nKTESTD, 640\nKUNPCKBW, 642\nKUNPCKWD, 642\nKUNPCKDQ, 642\nKXNORW, 643\nKXNORB, 643\nKXNORQ, 643\nKXNORD, 643\nKXORW, 644\nKXORB, 644\nKXORQ, 644\nKXORD, 644\nLAHF, 645\nLAR, 646\nLDDQU, 649\nVLDDQU, 649\nLDMXCSR, 651\nVLDMXCSR, 651\nLDS, 652\nLES, 652\nLFS, 652\nLGS, 652\nLSS, 652\nLEA, 656\nLEAVE, 658\nLFENCE, 660\nLGDT, 661\nLIDT, 661\nLLDT, 664\nLMSW, 666\nLOCK, 668\nLODS, 670\nLODSB, 670\nLODSW, 670\nLODSD, 670\nLODSQ, 670\nLOOP, 673\nLOOPE, 673\nLOOPNE, 673\nLSL, 675\nLTR, 678\nLZCNT, 680\nMASKMOVDQU, 690\nVMASKMOVDQU, 690\nMASKMOVQ, 692\nMAXPD, 694\nVMAXPD, 694\nMAXPS, 697\nVMAXPS, 697\nMAXSD, 700\nVMAXSD, 700\nMAXSS, 702\nVMAXSS, 702\nMFENCE, 704\nMINPD, 705\nVMINPD, 705\nMINPS, 708\nVMINPS, 708\nMINSD, 711\nVMINSD, 711\nMINSS, 713\nVMINSS, 713\nMONITOR, 715\nMOV, 717\nMOVAPD, 727\nVMOVPAD, 727\nMOVAPS, 731\nVMOVAPS, 731\nMOVBE, 735\nMOVD, 737\nVMOVD, 737\nMOVQ, 737\nVMOVQ, 737\nMOVDDUP, 741\nVMOVDDUP, 741\nMOVDIRI, 744\nMOVDIR64B, 746\nMOVDQA, 748\nVMOVDQA, 748\nVMOVDQA32, 748\nVMOVDQA64, 748\nMOVDQU, 753\nVMOVDQU, 753\nVMOVDQU8, 753\nVMOVDQU16, 753\nVMOVDQU32, 753\nVMOVDQU64, 753\nMOVDQ2Q, 761\nMOVHLPS, 762\nVMOVHLPS, 762\nMOVHPD, 764\nVMOVHPD, 764\nMOVHPS, 766\nVMOVHPS, 766\nMOVLHPS, 768\nVMOVLHPS, 768\nMOVLPD, 770\nVMOVLPD, 770\nMOVLPS, 772\nVMOVLPS, 772\nMOVMSKPD, 774\nVMOVMSKPD, 774\nMOVMSKPS, 776\nVMOVMSKPS, 776\nMOVNTDQA, 778\nVMOVNTDQA, 778\nMOVNTDQ, 780\nVMOVNTDQ, 780\nMOVNTI, 782\nMOVNTPD, 784\nVMOVNTPD, 784\nMOVNTPS, 786\nVMOVNTPS, 786\nMOVNTQ, 788\nMOVQ, 789\nVMOVQ, 789\nMOVQ2DQ, 792\nMOVS, 793\nMOVSB, 793\nMOVSW, 793\nMOVSQ, 793\nMOVSD, 797\nVMOVSD, 797\nMOVSHDUP, 800\nVMOVSHDUP, 800\nMOVSLDUP, 803\nVMOVSLDUP, 803\nMOVSS, 806\nVMOVSS, 806\nMOVSX, 810\nMOVSXD, 810\nMOVUPD, 812\nVMOVUPD, 812\nMOVUPS, 816\nVMOVUPS, 816\nMOVZX, 820\nMPSADBW, 822\nVMPSADBW, 822\nMUL, 830\nMULPD, 832\nVMULPD, 832\nMULPS, 835\nVMULPS, 835\nMULSD, 838\nVMULSD, 838\nMULSS, 840\nVMULSS, 840\nMULX, 842\nMWAIT, 844\nNEG, 847\nNOP, 849\nNOT, 850\nOR, 852\nORPD, 854\nVORPD, 854\nORPS, 857\nVORPS, 857\nOUT, 860\nOUTS, 862\nOUTSB, 862\nOUTSW, 862\nOUTSD, 862\nPABSB, 866\nVPABSB, 866\nPABSW, 866\nVPABSW, 866\nPABSD, 866\nVPABSD, 866\nPABSQ, 866\nVPABSQ, 866\nPACKSSWB, 872\nVPACKSSWB, 872\nPACKSSDW, 872\nVPACKSSDW, 872\nPACKUSDW, 880\nVPACKUSDW, 880\nPACKUSWB, 885\nVPACKUSWB, 885\nPADDB, 890\nVPADDB, 890\nPADDW, 890\nVPADDW, 890\nPADDD, 890\nVPADDD, 890\nPADDQ, 890\nVPADDQ, 890\nPADDSB, 897\nVPADDSB, 897\nPADDSW, 897\nVPADDSW, 897\nPADDUSB, 901\nVPADDUSB, 901\nPADDUSW, 901\nVPADDUSW, 901\nPALIGNR, 905\nVPALIGNR, 905\nPAND, 909\nVPAND, 909\nVPANDD, 909\nVPANDQ, 909\nPANDN, 912\nVPANDN, 912\nVPANDND, 912\nVPANDNQ, 912\nPAUSE, 915\nPAVGB, 916\nVPAVGB, 916\nPAVGW, 916\nVPAVGW, 916\nPBLENDVB, 920\nVPBLENDVB, 920\nPBLENDW, 924\nVPBLENDW, 924\nPCLMULQDQ, 927\nVPCLMULQDQ, 927\nPCMPEQB, 930\nVPCMPEQB, 930\nPCMPEQW, 930\nVPCMPEQW, 930\nPCMPEQD, 930\nVPCMPEQD, 930\nPCMPEQQ, 936\nVPCMPEQQ, 936\nPCMPESTRI, 939\nVPCMPESTRI, 939\nPCMPESTRM, 941\nVPCMPESTRM, 941\nPCMPGTB, 943\nVPCMPGTB, 943\nPCMPGTW, 943\nVPCMPGTW, 943\nPCMPGTD, 943\nVPCMPGTD, 943\nPCMPGTQ, 949\nVPCMPGTQ, 949\nPCMPISTRI, 952\nVPCMPISTRI, 952\nPCMPISTRM, 954\nVPCMPISTRM, 954\nPDEP, 956\nPEXT, 958\nPEXTRB, 960\nVPEXTRB, 960\nPEXTRD, 960\nVPEXTRD, 960\nPEXTRQ, 960\nVPEXTRQ, 960\nPEXTRW, 963\nVPEXTRW, 963\nPHADDW, 966\nVPHADDW, 966\nPHADDD, 966\nVPHADDD, 966\nPHADDSW, 970\nVPHADDSW, 970\nPHMINPOSUW, 972\nVPHMINPOSUW, 972\nPHSUBW, 974\nVPHSUBW, 974\nPHSUBD, 974\nPHSUBSW, 977\nVPHSUBSW, 977\nPINSRB, 979\nVPINSRB, 979\nPINSRD, 979\nVPINSRD, 979\nPINSRQ, 979\nVPINSRQ, 979\nPINSRW, 982\nVPINSRW, 982\nPMADDUBSW, 984\nVPMADDUBSW, 984\nPMADDWD, 987\nVPMADDWD, 987\nPMAXSB, 990\nVPMAXSB, 990\nPMAXSW, 990\nVPMAXSW, 990\nPMAXSD, 990\nVPMAXSD, 990\nPMAXSQ, 990\nVPMAXSQ, 990\nPMAXUB, 997\nVPMAXUB, 997\nPMAXUW, 997\nVPMAXUW, 997\nPMAXUD, 1002\nVPMAXUD, 1002\nPMAXUQ, 1002\nVPMAXUQ, 1002\nPMINSB, 1006\nVPMINSB, 1006\nPMINSW, 1006\nVPMINSW, 1006\nPMINSD, 1011\nVPMINSD, 1011\nPMINSQ, 1011\nVPMINSQ, 1011\nPMINUB, 1015\nVPMINUB, 1015\nPMINUW, 1015\nVPMINUW, 1015\nPMINUD, 1020\nVPMINUD, 1020\nPMINUQ, 1020\nVPMINUQ, 1020\nPMOVMSKB, 1024\nVPMOVMSKB, 1024\nPMOVSX, 1026\nPMOVSXBW, 1026\nVPMOVSXBW, 1026\nPMOVSXBD, 1026\nVPMOVSXBD, 1026\nPMOVSXBQ, 1026\nVPMOVSXBQ, 1026\nPMOVSXWD, 1026\nVPMOVSXWD, 1026\nPMOVSXWQ, 1026\nVPMOVSXWQ, 1026\nPMOVSXDQ, 1026\nVPMOVSXDQ, 1026\nPMOVZX, 1035\nPMOVZXBW, 1035\nVPMOVZXBW, 1035\nPMOVZXBD, 1035\nVPMOVZXBD, 1035\nPMOVZXBQ, 1035\nVPMOVZXBQ, 1035\nPMOVZXWD, 1035\nVPMOVZXWD, 1035\nPMOVZXWQ, 1035\nVPMOVZXWQ, 1035\nPMOVZXDQ, 1035\nVPMOVZXDQ, 1035\nPMULDQ, 1044\nVPMULDQ, 1044\nPMULHRSW, 1047\nVPMULHRSW, 1047\nPMULHUW, 1051\nVPMULHUW, 1051\nPMULHW, 1055\nVPMULHW, 1055\nPMULLD, 1059\nVPMULLD, 1059\nPMULLQ, 1059\nVPMULLQ, 1059\nPMULLW, 1063\nVPMULLW, 1063\nPMULUDQ, 1067\nVPMULUDQ, 1067\nPOP, 1070\nPOPA, 1075\nPOPAD, 1075\nPOPCNT, 1077\nPOPF, 1079\nPOPFD, 1079\nPOPFQ, 1079\nPOR, 1083\nPREFETCHT0, 1086\nPREFETCHT1, 1086\nPREFETCHT2, 1086\nPREFETCHNTA, 1086\nPREFETCHW, 1088\nPREFETCHWT1, 2090\nPSADBW, 1090\nVPSADBW, 1090\nPSHUFB, 1094\nVPSHUFB, 1094\nPSHUFD, 1098\nVPSHUFD, 1098\nPSHUFHW, 1102\nVPSHUFHW, 1102\nPSHUFLW, 1105\nVPSHUFLW, 1105\nPSHUFW, 1108\nPSIGNB, 1109\nVPSIGNB, 1109\nPSIGNW, 1109\nVPSIGNW, 1109\nPSIGND, 1109\nVPSIGND, 1109\nPSLLDQ, 1113\nVPSLLDQ, 1113\nPSLLW, 1115\nVPSLLW, 1115\nPSLLD, 1115\nVPSLLD, 1115\nPSLLQ, 1115\nVPSLLQ, 1115\nPSRAW, 1127\nVPSRAW, 1127\nPSRAD, 1127\nVPSRAD, 1127\nVPSRAQ, 1127\nPSRLDQ, 1137\nVPSRLDQ, 1137\nPSRLW, 1139\nVPSRLW, 1139\nPSRLD, 1139\nVPSRLD, 1139\nPSRLQ, 1139\nVPSRLQ, 1139\nPSUBB, 1151\nVPSUBB, 1151\nPSUBW, 1151\nVPSUBW, 1151\nPSUBD, 1151\nVPSUBD, 1151\nPSUBQ, 1158\nVPSUBQ, 1158\nPSUBSB, 1161\nVPSUBSB, 1161\nPSUBSW, 1161\nVPSUBSW, 1161\nPSUBUSB, 1165\nVPSUBUSB, 1165\nPSUBUSW, 1165\nVPSUBUSW, 1165\nPTEST, 1169\nVPTEST, 1169\nPTWRITE, 1171\nPUNPCKHBW, 1173\nVPUNPCKHBW, 1173\nPUNPCKHWD, 1173\nVPUNPCKHWD, 1173\nPUNPCKHDQ, 1173\nVPUNPCKHDQ, 1173\nPUNPCKHQDQ, 1173\nVPUNPCKHQDQ, 1173\nPUNPCKLBW, 1183\nVPUNPCKLBW, 1183\nPUNPCKLWD, 1183\nVPUNPCKLWD, 1183\nPUNPCKLDQ, 1183\nVPUNPCKLDQ, 1183\nPUNPCKLQDQ, 1183\nVPUNPCKLQDQ, 1183\nPUSH, 1193\nPUSHA, 1196\nPUSHAD, 1196\nPUSHF, 1198\nPUSHFD, 1198\nPUSHFQ, 1198\nPXOR, 1200\nVPXOR, 1200\nVPXORD, 1200\nVPXORQ, 1200\nRCL, 1203\nRCR, 1203\nROL, 1203\nROR, 1203\nRCPPS, 1208\nVRCPPS, 1208\nRCPSS, 1210\nVRCPSS, 1210\nRDFSBASE, 1212\nRDGSBASE, 1212\nRDMSR, 1214\nRDPID, 1216\nRDPKRU, 1217\nRDPMC, 1219\nRDRAND, 1221\nRDSEED, 1223\nRDSSPD, 1225\nRDSSPQ, 1225\nRDTSC, 1227\nRDTSCP, 1229\nREP, 1231\nREPE, 1231\nREPZ, 1231\nREPNE, 1231\nREPNZ, 1231\nRET, 1235\nRORX, 1248\nROUNDPD, 1249\nVROUNDPD, 1249\nROUNDPS, 1252\nVROUNDPS, 1252\nROUNDSD, 1255\nVROUNDSD, 1255\nROUNDSS, 1257\nVROUNDSS, 1257\nRSM, 1259\nRSQRTPS, 1261\nVRSQRTPS, 1261\nRSQRTSS, 1263\nVRSQRTSS, 1263\nRSTORSSP, 1265\nSAHF, 1268\nSAL, 1270\nSAR, 1270\nSHL, 1270\nSHR, 1270\nSARX, 1275\nSHLX, 1275\nSHRX, 1275\nSBB, 1279\nSCAS, 1282\nSCASB, 1282\nSCASW, 1282\nSCASD, 1282\nSCASQ, 1282\nSET, 1286\nSETA, 1286\nSETAE, 1286\nSETB, 1286\nSETBE, 1286\nSETC, 1286\nSETE, 1286\nSETG, 1286\nSETGE, 1286\nSETL, 1286\nSETLE, 1286\nSETNA, 1286\nSETNAE, 1286\nSETNB, 1286\nSETNBE, 1286\nSETNC, 1286\nSETNE, 1286\nSETNG, 1286\nSETNGE, 1286\nSETNL, 1286\nSETNLE, 1286\nSETNO, 1286\nSETNP, 1286\nSETNS, 1286\nSETNZ, 1286\nSETO, 1286\nSETP, 1286\nSETPE, 1286\nSETPO, 1286\nSETS, 1286\nSETZ, 1286\nSETSSBSY, 1289\nSFENCE, 1291\nSGDT, 1292\nSHA1RNDS4, 1294\nSHA1NEXTE, 1296\nSHA1MSG1, 1297\nSHA1MSG2, 1298\nSHA256RNDS2, 1299\nSHA256MSG1, 1301\nSHA256MSG2, 1302\nSHLD, 1303\nSHRD, 1306\nSHUFPD, 1309\nVSHUFPD, 1309\nSHUFPS, 1314\nVSHUFPS, 1314\nSIDT, 1318\nSLDT, 1320\nSMSW, 1322\nSQRTPD, 1324\nVSQRTPD, 1324\nSQRTPS, 1327\nVSQRTPS, 1327\nSQRTSD, 1330\nVSQRTSD, 1330\nSQRTSS, 1332\nVSQRTSS, 1332\nSTAC, 1334\nSTC, 1335\nSTD, 1336\nSTI, 1337\nSTMXCSR, 1339\nSTOS, 1340\nSTOSB, 1340\nSTOSW, 1340\nSTOSD, 1340\nSTOSQ, 1340\nSTR, 1344\nSUB, 1346\nSUBPD, 1348\nVSUBPD, 1348\nSUBPS, 1351\nVSUBPS, 1351\nSUBSD, 1354\nVSUBSD, 1354\nSUBSS, 1356\nVSUBSS, 1356\nSWAPGS, 1358\nSYSCALL, 1360\nSYSENTER, 1363\nSYSEXIT, 1366\nSYSRET, 1369\nTEST, 1372\nTPAUSE, 1374\nTZCNT, 1376\nUCOMISD, 1378\nVUCOMISD, 1378\nUCOMISS, 1380\nVUCOMISS, 1380\nUD0, 1382\nUD1, 1382\nUD2, 1382\nUMONITOR, 1383\nUMWAIT, 1385\nUNPCKHPD, 1387\nVUNPCKHPD, 1387\nUNPCKHPS, 1391\nVUNPCKHPS, 1391\nUNPCKLPD, 1395\nVUNPCKLPD, 1395\nUNPCKLPS, 1399\nVUNPCKLPS, 1399\nVALIGND, 1407\nVALIGNQ, 1407\nVBLENDMPD, 1411\nVBLENDMPS, 1411\nVBROADCAST, 1414\nVBROADCASTSS, 1414\nVBROADCASTSD, 1414\nVBROADCASTF128, 1414\nVBROADCASTF32X2, 1414\nVBROADCASTF32X4, 1414\nVBROADCASTF64X2, 1414\nVBROADCASTF32X8, 1414\nVBROADCASTF64X4, 1414\nVCOMPRESSPD, 1422\nVCOMPRESSPS, 1424\nVCVTPD2QQ, 1426\nVCVTPD2UDQ, 1429\nVCVTPD2UQQ, 1432\nVCVTPH2PS, 1435\nVCVTPS2PH, 1438\nVCVTPS2UDQ, 1442\nVCVTPS2QQ, 1445\nVCVTPS2UQQ, 1448\nVCVTQQ2PD, 1451\nVCVTQQ2PS, 1453\nVCVTSD2USI, 1455\nVCVTSS2USI, 1456\nVCVTTPD2QQ, 1458\nVCVTTPD2UDQ, 1460\nVCVTTPD2UQQ, 1463\nVCVTTPS2UDQ, 1465\nVCVTTPS2QQ, 1467\nVCVTTPS2UQQ, 1469\nVCVTTSD2USI, 1471\nVCVTTSS2USI, 1472\nVCVTUDQ2PD, 1474\nVCVTUDQ2PS, 1476\nVCVTUQQ2PD, 1478\nVCVTUQQ2PS, 1480\nVCVTUSI2SD, 1482\nVCVTUSI2SS, 1484\nVDBPSADBW, 1486\nVEXPANDPD, 1490\nVEXPANDPS, 1492\nVERR, 1494\nVERW, 1494\nVEXP2PD, 2096\nVEXP2PS, 2098\nVEXTRACTF128, 1496\nVEXTRACTF32X4, 1496\nVEXTRACTF64X2, 1496\nVEXTRACTF32X8, 1496\nVEXTRACTF64X4, 1496\nVEXTRACTI128, 1502\nVEXTRACTI32X4, 1502\nVEXTRACTI64X2, 1502\nVEXTRACTI32X8, 1502\nVEXTRACTI64X4, 1502\nVFIXUPIMMPD, 1508\nVFIXUPIMMPS, 1512\nVFIXUPIMMSD, 1516\nVFIXUPIMMSS, 1519\nVFMADD132PD, 1522\nVFMADD213PD, 1522\nVFMADD231PD, 1522\nVFMADD132PS, 1529\nVFMADD213PS, 1529\nVFMADD231PS, 1529\nVFMADD132SD, 1536\nVFMADD213SD, 1536\nVFMADD231SD, 1536\nVFMADD132SS, 1539\nVFMADD213SS, 1539\nVFMADD231SS, 1539\nVFMADDSUB132PD, 1542\nVFMADDSUB213PD, 1542\nVFMADDSUB231PD, 1542\nVFMADDSUB132PS, 1552\nVFMADDSUB213PS, 1552\nVFMADDSUB231PS, 1552\nVFMSUBADD132PD, 1561\nVFMSUBADD213PD, 1561\nVFMSUBADD231PD, 1561\nVFMSUBADD132PS, 1571\nVFMSUBADD213PS, 1571\nVFMSUBADD231PS, 1571\nVFMSUB132PD, 1581\nVFMSUB213PD, 1581\nVFMSUB231PD, 1581\nVFMSUB132PS, 1588\nVFMSUB213PS, 1588\nVFMSUB231PS, 1588\nVFMSUB132SD, 1595\nVFMSUB213SD, 1595\nVFMSUB231SD, 1595\nVFMSUB132SS, 1598\nVFMSUB213SS, 1598\nVFMSUB231SS, 1598\nVFNMADD132PD, 1601\nVFNMADD213PD, 1601\nVFNMADD231PD, 1601\nVFNMADD132PS, 1608\nVFNMADD213PS, 1608\nVFNMADD231PS, 1608\nVFNMADD132SD, 1614\nVFNMADD213SD, 1614\nVFNMADD231SD, 1614\nVFNMADD132SS, 1617\nVFNMADD213SS, 1617\nVFNMADD231SS, 1617\nVFNMSUB132PD, 1620\nVFNMSUB213PD, 1620\nVFNMSUB231PD, 1620\nVFNMSUB132PS, 1626\nVFNMSUB213PS, 1626\nVFNMSUB231PS, 1626\nVFNMSUB132SD, 1632\nVFNMSUB213SD, 1632\nVFNMSUB231SD, 1632\nVFNMSUB132SS, 1635\nVFNMSUB213SS, 1635\nVFNMSUB231SS, 1635\nVFPCLASSPD, 1638\nVFPCLASSPS, 1641\nVFPCLASSSD, 1643\nVFPCLASSSS, 1645\nVGATHERDPD, 1647\nVGATHERQPD, 1647\nVGATHERDPS, 1652\nVGATHERQPS, 1652\nVGATHERPFODPS, 2100\nVGATHERPFOQPS, 2100\nVGATHERPFODPD, 2100\nVGATHERPFOQPD, 2100\nVGATHERPF1DPS, 2102\nVGATHERPF1QPS, 2102\nVGATHERPF1DPD, 2102\nVGATHERPF1QPD, 2102\nVGETEXPPD, 1663\nVGETEXPPS, 1666\nVGETEXPSD, 1670\nVGETEXPSS, 1672\nVGETMANTPD, 1674\nVGETMANTPS, 1678\nVGETMANTSD, 1681\nVGETMANTSS, 1683\nVINSERTF128, 1685\nVINSERTF32X4, 1685\nVINSERTF64X2, 1685\nVINSERTF32X8, 1685\nVINSERTF64X4, 1685\nVINSERTI128, 1689\nVINSERTI32X4, 1689\nVINSERTI64X2, 1689\nVINSERTI32X8, 1689\nVINSERTI64X4, 1689\nVMASKMOV, 1693\nVMASKMOVPS, 1693\nVMASKMOVPD, 1693\nVBLENDD, 1696\nVPBLENDMB, 1698\nVPBLENDMW, 1698\nVPBLENDMD, 1700\nVPBLENDMQ, 1700\nVPBROADCASTB, 1703\nVPBROADCASTW, 1703\nVPBROADCASTD, 1703\nVPBROADCASTQ, 1703\nVPBROADCASTI32X2, 1706\nVPBROADCASTI128, 1706\nVPBROADCASTI32X4, 1706\nVPBROADCASTI64X2, 1706\nVPBROADCASTI32X8, 1706\nVPBROADCASTI64X4, 1706\nVPBROADCASTM, 1715\nVPBROADCASTMB2Q, 1715\nVPBROADCASTMW2D, 1715\nVPCMPB, 1717\nVPCMPUB, 1717\nVPCMPD, 1720\nVPCMPUD, 1720\nVPCMPQ, 1723\nVPCMPUQ, 1723\nVPCMPW, 1726\nVPCMPUW, 1726\nVCOMPRESSB, 1729\nVCOMPRESSW, 1729\nVCOMPRESSD, 1732\nVCOMPRESSQ, 1734\nVPCONFLICTD, 1736\nVPCONFLICTQ, 1736\nVPDPBUSD, 1739\nVPDPBUSDS, 1741\nVPDWSSD, 1743\nVPDPWSSDS, 1745\nVPERM2F128, 1747\nVPERM2I128, 1749\nVPERMB, 1751\nVPERMD, 1753\nVPERMW, 1753\nVPERMI2B, 1756\nVPERMI2W, 1758\nVPERMI2D, 1758\nVPERMI2Q, 1758\nVPERMI2PS, 1758\nVPERMI2PD, 1758\nVPERMILPD, 1764\nVPERMILPS, 1769\nVPERMPD, 1774\nVPERMPS, 1777\nVPERMQ, 1780\nVPERMT2B, 1783\nVPERMT2W, 1785\nVPERMT2D, 1785\nVPERMT2Q, 1785\nVPERMT2PS, 1785\nVPERMT2PD, 1785\nVPEXPANDB, 1790\nVPEXPANDW, 1790\nVEXPANDD, 1793\nVEXPANDQ, 1795\nVPGATHERDD, 1797\nVPGATHERQD, 1797\nVPGATHERDQ, 1804\nVPGATHERQQ, 1804\nVPLZCNTD, 1811\nVPLZCNTQ, 1811\nVPMADD52HUQ, 1814\nVPMADD52LUQ, 1816\nVPMASKMOVD, 1818\nVPMASKMOVQ, 1818\nVPMOVM2B, 1832\nVPMOVM2W, 1832\nVPMOVM2D, 1832\nVPMOVM2Q, 1832\nVPMOVB2M, 1821\nVPMOVW2M, 1821\nVPMOVD2M, 1821\nVPMOVQ2M, 1821\nVPMOVQB, 1835\nVPMOVSQB, 1835\nVPMOVUSQB, 1835\nVPMOVQW, 1843\nVPMOVSQW, 1843\nVPMOVUSQW, 1843\nVPMOVQD, 1839\nVPMOVSQD, 1839\nVPMOVUSQD, 1839\nVPMOVDB, 1824\nVPMOVSDB, 1824\nVPMOVUSDB, 1824\nVPMOVDW, 1828\nVPMOVSDW, 1828\nVPMOVUSDW, 1828\nVPMOVWB, 1847\nVPMOVSWB, 1847\nVPMOVUSWB, 1847\nVPMULTISHIFTQB, 1851\nVPOPCNTB, 1853\nVPOPCNTW, 1853\nVPOPCNTD, 1853\nVPOPCNTQ, 1853\nPROLD, 1856\nVPROLD, 1856\nPROLVD, 1856\nVPROLVD, 1856\nPROLVQ, 1856\nVPROLVQ, 1856\nPRORD, 1861\nVPRORD, 1861\nPRORVD, 1861\nVPRORVD, 1861\nPRORQ, 1861\nVPRORQ, 1861\nPRORVQ, 1861\nVPRORVQ, 1861\nVPSCATTERDD, 1866\nVPSCATTERDQ, 1866\nVPSCATTERQD, 1866\nVPSCATTERQQ, 1866\nVPSHLD, 1870\nVPSHLDW, 1870\nVPSHLDD, 1870\nVPSHLDQ, 1870\nVPSHLDV, 1873\nVPSHLDVW, 1873\nVPSHLDVD, 1873\nVPSHLDVQ, 1873\nVPSHRD, 1876\nVPSHRDW, 1876\nVPSHRDD, 1876\nVPSHRDQ, 1876\nVPSHRDV, 1879\nVPSHRDVW, 1879\nVPSHRDVD, 1879\nVPSHRDVQ, 1879\nVPSHUFBITQMB, 1882\nVPSLLVW, 1883\nVPSLLVD, 1883\nVPSLLVQ, 1883\nVPSRAVW, 1888\nVPSRAVD, 1888\nVPSRAVQ, 1888\nVPSRLVW, 1893\nVPSRLVD, 1893\nVPSRLVQ, 1893\nVPTERNLOGD, 1898\nVPTERNLOGQ, 1898\nVPTESTMB, 1901\nVPTESTMW, 1901\nVPTESTMD, 1901\nVPTESTMQ, 1901\nVPTESTNMB, 1904\nVPTESTNMW, 1904\nVPTESTNMD, 1904\nVPTESTNMQ, 1904\nVRANGEPD, 1908\nVRANGEPS, 1913\nVRANGESD, 1917\nVRANGESS, 1920\nVRCP14PD, 1923\nVRCP14SD, 1925\nVRCP14PS, 1927\nVRCP14SS, 1929\nVRCP28PD, 2108\nVRCP28SD, 2110\nVRCP28PS, 2112\nVRCP28SS, 2114\nVREDUCEPD, 1931\nVREDUCESD, 1934\nVREDUCEPS, 1936\nVREDUCESS, 1938\nVRNDSCALEPD, 1940\nVRNDSCALESD, 1944\nVRNDSCALEPS, 1946\nVRNDSCALESS, 1949\nVRSQRT14PD, 1951\nVRSQRT14SD, 1953\nVRSQRT14PS, 1955\nVRSQRT14SS, 1957\nVRSQRT28PD, 2116\nVRSQRT28SD, 2118\nVRSQRT28PS, 2120\nVRSQRT28SS, 2122\nVSCALEFPD, 1959\nVSCALEFSD, 1962\nVSCALEFPS, 1964\nVSCALEFSS, 1967\nVSCATTERDPS, 1969\nVSCATTERDPD, 1969\nVSCATTERQPS, 1969\nVSCATTERQPD, 1969\nVSCATTERPFODPS, 2124\nVSCATTERPFOQPS, 2124\nVSCATTERPFODPD, 2124\nVSCATTERPFOQPD, 2124\nVSCATTERPF1DPS, 2126\nVSCATTERPF1QPS, 2126\nVSCATTERPF1DPD, 2126\nVSCATTERPF1QPD, 2126\nVSHUFF32X4, 1973\nVSHUFF64X2, 1973\nVSHUFI32X4, 1973\nVSHUFI64X2, 1973\nVTESTPD, 1978\nVTESTPS, 1978\nVZEROALL, 1981\nVZEROUPPER, 1982\nWAIT, 1983\nFWAIT, 1983\nWBINVD, 1984\nWRFSBASE, 1986\nWRGSBASE, 1986\nWRMSR, 1988\nWRPKRU, 1990\nWRSSD, 1991\nWRSSQ, 1991\nWRUSSD, 1993\nWRUSSQ, 1993\nXACQUIRE, 1995\nXRELEASE, 1995\nXABORT, 1999\nXADD, 2001\nXBEGIN, 2003\nXCHG, 2006\nXEND, 2008\nXGETBV, 2010\nXLAT, 2012\nXLATB, 2012\nXOR, 2014\nXORPD, 2016\nVXORPD, 2016\nXORPS, 2019\nVXORPS, 2019\nXRSTOR, 2022\nXRSTOR64, 2022\nXSTORS, 2027\nXSTORS64, 2027\nXSAVE, 2031\nXSAVE64, 2031\nXSAVEC, 2034\nXSAVEC64, 2034\nXSAVEOPT, 2037\nXSAVEOPT64, 2037\nXSAVES, 2040\nXSAVES64, 2040\nXSETBV, 2043\nXTEST, 2045\n\n@24594.pdf [AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Rev 3.32 March 2021 (24594)]\nBLCFILL, 135\nBLCI, 137\nBLCIC, 139\nBLCMSK, 141\nBLCS, 143\nBLSFILL, 145\nBLSIC, 149\nCLZERO, 190\nLLWPCB, 255\nLOOPNZ, 260\nLOOPZ, 260\nLWPINS, 262\nLWPVAL, 264\nMONITORX, 271\nMWAITX, 297\nPREFETCH, 323\nSLWPCB, 380\nT1MSKC, 388\nTZMSK, 394\nUD0, 396\nUD1, 396\nUD2, 396\nCLGI, 414\nINVLPGA, 428\nSKINIT, 496\nSTGI, 504\nVMLOAD, 524\nVMMCALL, 526\nVMRUN, 527\nVMSAVE, 532\n\n@26568.pdf [AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, Rev 3.24 May 2020 (26568)]\nEXTRQ, 181\nINSERTQ, 196\nMOVNTSD, 260\nMOVNTSS, 262\nVPHSUBD, 388\nVPOR, 474\nVSTMXCSR, 615\nVBROADCASTI128, 639\nVFMADDPD, 656\nVFMADDPS, 659\nVFMADDSD, 662\nVFMADDSS, 665\nVFMADDSUBPD, 668\nVFMADDSUBPS, 671\nVFMADDPD, 674\nVFMADDPS, 677\nVFMSUBPD, 680\nVFMSUBPS, 683\nVFMSUBSD, 686\nVFMSUBSS, 689\nVFNMADDPD, 692\nVFNMADDPS, 695\nVFNMADDSD, 698\nVFNMADDSS, 701\nVFNMSUBPD, 704\nVFNMSUBPS, 707\nVFNMSUBSD, 710\nVFNMSUBSS, 713\nVFRCZPD, 716\nVFRCZPS, 718\nVFRCZSD, 720\nVFRCZSS, 722\nVPCMOV, 750\nVPCOMB, 752\nVPCOMD, 754\nVPCOMQ, 756\nVPCOMUB, 758\nVPCOMUD, 760\nVPCOMUQ, 762\nVPCOMUW, 764\nVPCOMW, 766\nVPERMIL2PD, 774\nVPERMIL2PS, 778\nVPHADDBD, 803\nVPHADDBQ, 805\nVPHADDBW, 807\nVPHADDDQ, 809\nVPHADDUBD, 811\nVPHADDUBQ, 813\nVPHADDUBW, 815\nVPHADDUDQ, 817\nVPHADDUWD, 819\nVPHADDUWQ, 821\nVPHADDWD, 823\nVPHADDWQ, 825\nVPHSUBBW, 827\nVPHSUBDQ, 829\nVPHSUBWD, 831\nVPMACSDD, 833\nVPMACSDQH, 835\nVPMACSDQL, 837\nVPMACSSDD, 839\nVPMACSSDQH, 841\nVPMACSSDQL, 843\nVPMACSSWD, 845\nVPMACSSWW, 847\nVPMACSWD, 849\nVPMACSWW, 851\nVPMADCSSWD, 853\nVPMADCSWD, 855\nVPPERM, 861\nVPROTB, 863\nVPROTD, 865\nVPROTQ, 867\nVPROTW, 869\nVPSHAB, 871\nVPSHAD, 873\nVPSHAQ, 875\nVPSHAW, 877\nVPSHLB, 879\nVPSHLD, 881\nVPSHLQ, 883\nVPSHLW, 885\n\n@26569_APM_V5.pdf [AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, Rev 3.15 May 2018 (26569)]\nFEMMS, 48\nPAVGUSB, 100\nPF2ID, 118\nPF2IW, 120\nPFACC, 122\nPFADD, 124\nPFCMPEQ, 126\nPFCMPGE, 128\nPFCMPGT, 131\nPFMAX, 133\nPFMIN, 135\nPFMUL, 137\nPFNACC, 139\nPFPNACC, 142\nPFRCP, 145\nPFRCPIT1, 148\nPFRCPIT2, 151\nPFRSQIT1, 154\nPFRSQRT, 157\nPFSUB, 160\nPFSUBR, 162\nPI2FD, 164\nPI2FW, 166\nPMULHRW, 182\nPSWAPD, 231\n\n@AMD64_128-bit_SSE5_Instructions.pdf [AMD64 Technology 128-Bit SSE5 Instruction Set, Rev 3.01 August 2007 (43479)]\nCOMPD, 32\nCOMPS, 35\nCOMSD, 38\nCOMSS, 42\nCVTPH2PS, 45\nCVTPS2PH, 47\nFMADDPD, 50\nFMADDPS, 53\nFMADDSD, 56\nFMADDSS, 59\nFMSUBPD, 62\nFMSUBPS, 65\nFMSUBSD, 68\nFMSUBSS, 71\nFNMADDPD, 74\nFNMADDPS, 77\nFNMADDSD, 80\nFNMADDSS, 83\nFNMSUBPD, 86\nFNMSUBPS, 89\nFNMSUBSD, 92\nFNMSUBSS, 95\nFRCZPD, 98\nFRCZPS, 100\nFRCZSD, 102\nFRCZSS, 104\nPCMOV, 106\nPCOMB, 109\nPCOMD, 112\nPCOMQ, 115\nPCOMUB, 118\nPCOMUD, 121\nPCOMUQ, 124\nPCOMUW, 127\nPCOMW, 130\nPERMPD, 133\nPERMPS, 137\nPHADDBD, 141\nPHADDBQ, 143\nPHADDBW, 145\nPHADDDQ, 147\nPHADDUBD, 149\nPHADDUBQ, 151\nPHADDUBW, 153\nPHADDUDQ, 155\nPHADDUWD, 157\nPHADDUWQ, 159\nPHADDWD, 161\nPHADDWQ, 163\nPHSUBBW, 165\nPHSUBBQ, 167\nPHSUBWD, 169\nPMACSDD, 171\nPMACSDQH, 174\nPMACSDQL, 177\nPMACSSDD, 180\nPMACSSDQH, 183\nPMACSSDQL, 186\nPMACSSWD, 189\nPMACSSWW, 192\nPMACSWD, 195\nPMACSWW, 198\nPMADCSSWD, 201\nPMADCSWD, 204\nPPERM, 207\nPROTB, 211\nPROTD, 214\nPROTQ, 217\nPROTW, 220\nPSHAB, 223\nPSHAD, 225\nPSHAQ, 227\nPSHAW, 229\nPSHLB, 231\nPSHLD, 233\nPSHLQ, 236\nPSHLW, 238\n\n@326019-074.pdf [Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3C: System Programming Guide, Part 3, 326019-074US April 2021]\nINVEPT, 157\nINVVPID, 160\nVMCALL, 163\nVMCLEAR, 165\nVMFUNC, 167\nVMLAUNCH, 168\nVMRESUME, 168\nVMPTRLD, 171\nVMPTRST, 173\nVMREAD, 175\nVMWRITE, 178\nVMXOFF, 180\nVMXON, 182\n" }, { "path": "pypcode/processors/x86/data/patterns/patternconstraints.xml", "content": "\n \n \t\n \t x86win_patterns.xml\n \t\n \t\n \t x86win_patterns.xml\n \t\n \t\n \t x86delphi_patterns.xml\n \t\n \n x86gcc_patterns.xml\n \n \n \n \n \n x86-64win_patterns.xml\n \n \n x86-64gcc_patterns.xml\n \n \n \n \n \t\n \t\tx86-16_default_patterns.xml\n \t\n \n \n \n \t\n \t\tx86-16_default_patterns.xml\n \t\n \n\n" }, { "path": "pypcode/processors/x86/data/patterns/prepatternconstraints.xml", "content": "\n\n \n \t\n \t x86win_prepatterns.xml\n \t\n \t\n \t x86win_prepatterns.xml\n \t\n \t\n \t x86gcc_prepatterns.xml\n \t\n \n \n \n \t\n \t x86gcc_prepatterns.xml\n \t\n \n \n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86-16_default_patterns.xml", "content": "\n \n \n 0xc9c3 \t\n 0xc9cb \t\n 0x4dcb \t \n 0.011... 1100.011\t\t\n 1100.010 .0.....0 0x00\t\n 1100.010 .0.....0 0x00 0x90\t\n 0xc390\t\t\t\t\t\n 0xcb90\n 0xc3\n \n \n 0x558bec \t\t\t\t\n 0x5589e5 \t\t\t\t\n 0xc8 000....0 0x0000 \t\n 0x8cd89045 \t\t\t\t\n 0x8cd055\t\t\t\t\t\n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86-64gcc_patterns.xml", "content": "\n \n \n 0x90 0x90 \n 0xc3 0x90 \n 0x6690 \n 0xc9 0xc3 \n 0xe9........ \n 0xe9........90 \n 0xeb.. \n 0xeb..90 \n 0x5d 0xc3 \n 0x5b 0xc3 \n 0x41 010111.. 0xc3 \n 0x31c0 0xc3 \n 0x4883c4 ....1000 0xc3 \n 0x666690 \n 0x0f1f00 \n 0x0f1f4000 \n 0x0f1f440000 \n 0x660f1f440000 \n 0x0f1f8000000000 \n 0x0f1f840000000000 \n 0x660f1f840000000000 \n \n \n \n 0x48 0x89 0x5c 0x24 11...000 0x48 0x89 0x6c 0x24 11...000 \n 0x48 0x89 0x5c 0x24 11...000 0x4c 0x89 0x64 0x24 111..000 \n 0x48 0x89 0x6c 0x24 11...000 0x4c 0x89 0x64 0x24 111..000 \n 0x5589e5 \n 0x554889e5 \n 0x534889fb \n 0x554889fd \n 0x534889fb \n 0x53 0x48 0x83 0xec 0....000 \n 0x53 0x48 0x81 0xec .....000 00...... 0x00 \n \n 0x55 0x48 0x89 0xe5 0x48 100000.1 0xec .....000 \n 0x554889e553 \n 0x554889fd53 \n 0x554889e548897df8 \n 0x53 0x48 0x89 0xfb 0xe8 ........ ........ 0xff 0xff \n 0x4154 0x55 0100100. 0x89 11...... \n 0x4154 0x55 0x53 0100100. 0x89 11...... \n \n 0x415741564155 \n 0x41564155 \n 0x41554154 \n 0x41 010101.. 0100100. 0x89 11...... 0x55 \n \n \n \n 0xf3 0x0f 0x1e 0xfa 0x48 0x89 0x5c 0x24 11...000 0x48 0x89 0x6c 0x24 11...000 \n 0xf3 0x0f 0x1e 0xfa 0x48 0x89 0x5c 0x24 11...000 0x4c 0x89 0x64 0x24 111..000 \n 0xf3 0x0f 0x1e 0xfa 0x48 0x89 0x6c 0x24 11...000 0x4c 0x89 0x64 0x24 111..000 \n 0xf3 0x0f 0x1e 0xfa 0x5589e5 \n 0xf3 0x0f 0x1e 0xfa 0x554889e5 \n 0xf3 0x0f 0x1e 0xfa 0x534889fb \n 0xf3 0x0f 0x1e 0xfa 0x554889fd \n 0xf3 0x0f 0x1e 0xfa 0x534889fb \n 0xf3 0x0f 0x1e 0xfa 0x53 0x48 0x83 0xec 0....000 \n 0xf3 0x0f 0x1e 0xfa 0x53 0x48 0x81 0xec .....000 00...... 0x00 \n \n 0xf3 0x0f 0x1e 0xfa 0x55 0x48 0x89 0xe5 0x48 100000.1 0xec .....000 \n 0xf3 0x0f 0x1e 0xfa 0x554889e553 \n 0xf3 0x0f 0x1e 0xfa 0x554889fd53 \n 0xf3 0x0f 0x1e 0xfa 0x554889e548897df8 \n 0xf3 0x0f 0x1e 0xfa 0x53 0x48 0x89 0xfb 0xe8 ........ ........ 0xff 0xff \n 0xf3 0x0f 0x1e 0xfa 0x4154 0x55 0100100. 0x89 11...... \n 0xf3 0x0f 0x1e 0xfa 0x4154 0x55 0x53 0100100. 0x89 11...... \n \n 0xf3 0x0f 0x1e 0xfa 0x415741564155 \n 0xf3 0x0f 0x1e 0xfa 0x41564155 \n 0xf3 0x0f 0x1e 0xfa 0x41554154 \n 0xf3 0x0f 0x1e 0xfa 0x41 010101.. 0100100. 0x89 11...... 0x55 \n 0xf3 0x0f 0x1e 0xfa 0x41 010101.. 0x41 010101.. 0100100. 0x89 11...... \n \n \n \n \n \n \n \n 0x90 0x90 \n 0xc3 0x90 \n 0x6690 \n 0xc9 0xc3 \n 0xe9........ \n 0xe9........90 \n 0xeb.. \n 0xeb..90 \n 0x5d 0xc3 \n 0x5b 0xc3 \n 0x41 010111.. 0xc3 \n 0x31c0 0xc3 \n 0x4883c4 ....1000 0xc3 \n 0x666690 \n 0x0f1f00 \n 0x0f1f4000 \n 0x0f1f440000 \n 0x660f1f440000 \n 0x0f1f8000000000 \n 0x0f1f840000000000 \n 0x660f1f840000000000 \n \n \n 0xf3 0x0f 0x1e 0xfa \n \n \n \n \n \n\n 0x5589e5 \n \n\n\n\n 0x55 0x53 0100100. 0x89 11...... \n \n\n\n\n 0x4154 0x55 0100100. 0x89 11...... \n \n\n\n\n 0x4154 0x55 0x53 0100100. 0x89 11...... \n \n\n\n\n 0x53 0x48 0x83 0xec 0....000 \n \n\n\n\n 0x48 0x83 0xec .....000 \n \n\n\n\n 0x48 0x81 0xec .....000 00...... 0x00 \n \n\n\n\n 0x55 0x53 0x48 0x83 100000.1 0xec .....000 \n \n\n \n\n 0x554889e5 \n \n\n\n\n 0x55 0x48 0x89 0xe5 0x48 100000.1 0xec .....000 \n \n\n\n\n 0x554889e553 \n \n\n\n\n 0x4157 0x4156 0x4155 \n \n\n\n\n 0x4157 0x4156 \n \n\n\n\n 0x4156 0x4155 \n \n\n\n\n 0x41554154 \n \n\n\n\n 0x41 010101.. 0100100. 0x89 11...... 0x55 \n \n\n\n\n 0x41 010101.. 0x41 010101.. 0100100. 0x89 11...... \n \n\n\n\n 0x41 010101.. 0x41 010101.. 0100100. 0x89 11...... \n \n\n \n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86-64win_patterns.xml", "content": "\n \n 0x909090 * 0x4883ec \n \n \n \n 0x909090 * 0x4889 01...100..100100 \n \n \n \n 0x90 * 0x4889 01...100..100100 0x..4889 \n \n \n \n 0x90 * 0x4889 01...100..100100 ......00 01010...01010... \n \n \n \n 0xc3 * 0x4889 01...100..100100 ......00 01010...01010... \n \n \n \n 0xc3 * 0x55488d2c24 \n \n \n \n 0x90 * 0x55488d2c24 \n \n \n \n 0x90 * 01010... 0x55488d2c24 \n \n \n \n 0xc3 * 01010... 0x55488d2c24 \n \n \n \n 0x909090 * 0x488bc4 \n \n \n \n 0x90 * 0xfff54883ec \n \n \n \n 0x90 * 0x554883ec \n \n \n \n 0xc3 * 0x554883ec \n \n \n\n\n \n 0xcccccc * 0x4883ec \n \n \n \n 0xcccccc * 0x4889 01...100..100100 \n \n \n \n 0xcccccc * 0x488bc4 \n \n \n \n 0xcc * 0xfff54883ec \n \n \n \n 0xcc * 0x40 01010... 0x4883ec \n \n \n \n 0xcc * 0x554883ec \n \n \n \n 0xcccccc * 0x4055488b 11101... \n \n \n \n 0xcc * 0x4c8b 11...100 0x4883ec \n \n \n \n 0xcccc * 0x4c8b 11...100 01001.01 0x89 \n \n \n \n \n 01001... 0x3b 0x0d ........ ........ ........ ........\n 0x75 0x10\n 01001... 0xc1 0xc1 0x10\n 0x66 0xf7 0xc1 0xff 0xff\n 0x75 0x01\n 0xc3\n 01001... 0xc1 0xc9 0x10\n 0xe9 \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86delphi_patterns.xml", "content": "\n \n \n 0x9090 \n 0xc390 \n 0x5bc3 \n 0xc2 0000..00 0x00 \n 0xc2 0000..00 0x0090 \n 0xe8 ........ ........ ........ ........ 0xc3 \n 0xeb.. \n 0xe9........ \n \n \n \n 0x558bec \n 0x538bd8 \n \n 0x535657 \n 0x53568bd8 \n 0x53568bf0 \n 0x535684d2 \n 0x53 0x56 0x83 0xc4 1...1.00 \n \n \n \n\n \n \n 0x558bec\n \n \n \n \n 0x538bd8\n \n \n\n \n 0x535657\n \n \n \n \n 0x53568bd8\n \n \n\n \n 0x53568bf0\n \n \n \n \n 0x535684d2\n \n \n \n \n 0x53 0x56 0x83 0xc4 1...1.00\n \n \n\n\n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86gcc_patterns.xml", "content": "\n \n 0x5589e583ec \n \n \n \n \n 0x5589e581ec....0000 \n \n \n \n \n 0x5589e5..83ec \n \n \n \n \n 0x5589e5....83ec \n \n \n \n \n 0x5589e5 01010... 01010... \n \n \n \n \n 0x5589e58b 01...101 \n \n \n \n\n \n 0x83 0xec 0.....00 100010.1 01...100 ..100100 0.....00 \n \n \n\n \n 0x81 0xec ......00 0000.... 0x00 0x00 100010.1 01...100 ..100100 0.....00 \n \n \n \n \n 0x5. 0x83 0xec 0.....00 100010.1 01...100 ..100100 0.....00 \n \n \n \n \n 0x5. 0x81 0xec ......00 0000.... 0x00 0x00 \n \n \n \n \n 0x5. 0x5. 100000.1 0xec ......00 \n \n \n \n \n 0x5. 0x5. 0x5. 100000.1 0xec ......00 \n \n \n\n \n 0x5. 0x5. 0x5. 0x5. 100000.1 0xec ......00 \n \n \n \n \n 0x8b 0x04 0x24 0xc3 \n \n \n \n \n 0x8b 0x1c 0x24 0xc3 \n \n \n \n \n 0x8b 0x0c 0x24 0xc3 \n \n \n \n \n 0x8b 0x14 0x24 0xc3 \n \n \n \n \n 0x8b 0x34 0x24 0xc3 \n \n \n\n \n \n 0x90 \n 0xc3 \n 0xe9........ \n 0xeb.. \n 0x89f6 \n 0x8d7600 \n 0x8d742600 \n 0x8db600000000 \n 0x8dbf00000000 \n 0x8dbc2700000000 \n 0x8db42600000000 \n \n \n 0x5589e5 \n 0x8d 0x4c ..100100 0x04 0x83 0xe4 0xf. \n 0x57 0x8d 0x7c ..100100 0x08 0x83 0xe4 0xf. \n \n \n 0xf3 0x0f 0x1e 0xfb 0x5589e5 \n 0xf3 0x0f 0x1e 0xfb 0x8d 0x4c ..100100 0x04 0x83 0xe4 0xf. \n 0xf3 0x0f 0x1e 0xfb 0x57 0x8d 0x7c ..100100 0x08 0x83 0xe4 0xf. \n \n \n \n \n \n\n \n \n 0x90 \n 0xc3 \n 0xe9........ \n 0xeb.. \n 0x89f6 \n 0x8d7600 \n 0x8d742600 \n 0x8db600000000 \n 0x8dbf00000000 \n 0x8dbc2700000000 \n 0x8db42600000000 \n \n \n 0xf3 0x0f 0x1e 0xfb \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86gcc_prepatterns.xml", "content": "\n \n \n \n 0xff25........ \n 0x68......00 \n 0xe9......ff \n \n \n \n \n \n \n 0xf3 0x0f 0x1e 0xfa \n 0xf2 0xff 0x25 \n \n \n \n\n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86win_patterns.xml", "content": "\n \n \n 0xcc \n 0xcccc \n 0x90 \n 0xc3 \n 0xc9c3 \n 0xc2 ......00 0x00 \n \n \n 0x558bec \n 0x83ec 0.....00 \n 0x6aff68........64a100000000 \n 0x568bf1 \n 0xb8........e8........ 100000.1 0xec \n 0xb8........e8 \n 0x8bff558bec \n\n 0x538b 110110.. \n 0x535657 \n 0x535556 \n 0x535651 \n\n 0x53568bf2 \n 0x53568bd8 \n 0x53568bf1 \n 0x53568bda \n 0x53568bf0 \n 0x56578bf9 \n 0x56578bf1 \n\n \n \n \n\n \n \n 0xe9........ \n 0xeb.. \n \n \n 0x558bec \n 0x568bf1 \n 0xb8........e8........ 100000.1 0xec \n 0xb8........e8 \n 0x8bff558bec \n \n \n \n \n \n 0x558bec \n \n \n \n \n 0x8bff558bec \n \n \n \n \n \n 0xcccc \n 0xcccccc \n 0xcccccccc \n 0xcccccc \n \n \n 0x6a.. 0x68........ 0xe8 \n \n \n \n \n \n \n 0xcc \n 0xcccc \n 0x90 \n 0xc3 \n 0xc9c3 \n 0xc2 ......00 0x00 \n 0xe9........ \n 0xeb.. \n \n \n 01010... 0x8b 01...100 ..100100 000...00 \n \n \n \n \n \n 0x518d4c24042bc81bc0f7d023c88bc42500f0ffff3bc8720a8bc159948b00890424c32d001000008500ebe9 \n \n \n \n \n 0x518d4c24082bc883e10f03c11bc90bc159e9........ \n \n \n \n \n 0x518d4c24082bc883e10703c11bc90bc159e9........ \n \n \n\n \n \n \n 0x8b4df4 \n 0x64890d 0x00000000 \n 0x59 \n 0x5f \n 0x5f \n 0x5e \n 0x5b \n 0x8be5 \n 0x5d \n 0x51 \n 0xc3 \n \n \n \n\n \n \n 0x8b4df0 \n 0x64890d 0x00000000 \n 0x59 \n 0x5f \n 0x5f \n 0x5e \n 0x5b \n 0x8be5 \n 0x5d \n 0x51 \n 0xc3 \n \n \n \n \n \n 0xcc \n \n \n \n \n 0x3b 0x0d 0x.. 0x.. 0x.. 0x..\n 0x75 0x01 \n 0xc3 \n 0xe9 \n \n \n \n \n\n" }, { "path": "pypcode/processors/x86/data/patterns/x86win_prepatterns.xml", "content": "\n \n \n \n 0x8bff\n 0x55\n 0x8bec\n 0x83ec20\n 0x8b4508\n 0x56\n 0x57\n 0x6a08\n 0x59\n 0xbe........\n 0x8d7de0\n 0xf3a5\n 0x8945f8\n 0x8b450c\n 0x5f\n 0x8945fc\n 0x5e\n 0x85c0\n 0x740c\n 0xf60008\n 0x7407\n 0xc745f4........\n 0x8d45f4\n 0x50\n 0xff75f0\n 0xff75e4\n 0xff75e0\n 0xff15........\n 0xc9\n 0xc20800 \n \n \n\n\n" }, { "path": "pypcode/py.typed", "content": "" }, { "path": "pypcode/pypcode_native.cpp", "content": "#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"sleigh/error.hh\"\n#include \"sleigh/loadimage.hh\"\n#include \"sleigh/opcodes.hh\"\n#include \"sleigh/sleigh.hh\"\n#include \"sleigh/space.hh\"\n#include \"sleigh/translate.hh\"\n#include \"sleigh/xml.hh\"\n\nnamespace nb = nanobind;\nusing namespace nb::literals;\nusing namespace ghidra;\n\nconst char *\n#include \"__version__.py\"\n ;\n\n// #define DEBUG 1\n\n#ifndef DEBUG\n#define DEBUG 0\n#endif\n\n#if DEBUG\n#define LOG(fmt, ...) fprintf(stderr, \"pypcode_native: \" fmt \"\\n\", ##__VA_ARGS__);\n#else\n#define LOG(fmt, ...) \\\n do { \\\n } while (0)\n#endif\n\n#define MIN(x, y) ((x) < (y) ? (x) : (y))\n\nstruct PcodeOp {\n OpCode m_opcode;\n std::optional m_output;\n std::vector m_inputs;\n};\n\nclass ContextPypcode : public ContextInternal {\n bool m_finalized;\n std::unordered_set m_variables;\n\npublic:\n ContextPypcode() : ContextInternal()\n {\n m_finalized = false;\n }\n\n void finalize()\n {\n m_finalized = true;\n }\n\n virtual void registerVariable(const string &nm, int4 sbit, int4 ebit)\n {\n if (!m_finalized) {\n ContextInternal::registerVariable(nm, sbit, ebit);\n m_variables.insert(nm);\n }\n }\n\n void resetAllVariables()\n {\n for (const string &nm : m_variables) {\n auto val = ContextDatabase::getDefaultValue(nm);\n setVariableRegion(nm, Address(Address::m_minimal), Address(), val);\n }\n }\n};\n\nclass SimpleLoadImage : public LoadImage {\n uintb m_baseaddr;\n int4 m_length;\n const unsigned char *m_data;\n\npublic:\n SimpleLoadImage() : LoadImage(\"nofile\")\n {\n m_baseaddr = 0;\n m_data = NULL;\n m_length = 0;\n }\n\n void setData(uintb ad, const unsigned char *ptr, int4 sz)\n {\n m_baseaddr = ad;\n m_data = ptr;\n m_length = sz;\n }\n\n void loadFill(uint1 *ptr, int4 size, const Address &addr)\n {\n LOG(\"Filling %d bytes at %lx\", size, addr.getOffset());\n uintb start = addr.getOffset();\n uintb max = m_baseaddr + m_length - 1;\n\n //\n // When decoding an instruction, SLEIGH will attempt to pull in several\n // bytes at a time, starting at each instruction boundary.\n //\n // If the start address is outside of the defined range, bail out.\n // Otherwise, if we have some data to provide but cannot satisfy the\n // entire request, fill the remainder of the buffer with zero.\n //\n if (start > max || start < m_baseaddr) {\n throw std::out_of_range(\"Attempting to lift outside buffer range\");\n }\n\n for (int4 i = 0; i < size; i++) {\n uintb curoff = start + i;\n if ((curoff < m_baseaddr) || (curoff > max)) {\n ptr[i] = 0;\n continue;\n }\n uintb diff = curoff - m_baseaddr;\n ptr[i] = m_data[(int4)diff];\n }\n }\n\n virtual string getArchType(void) const\n {\n return \"myload\";\n }\n virtual void adjustVma(long adjust)\n {\n }\n};\n\nclass PcodeEmitCacher : public PcodeEmit {\npublic:\n std::vector m_ops;\n bool m_bb_terminating_op_emitted;\n\n PcodeEmitCacher() : m_bb_terminating_op_emitted(false)\n {\n m_ops.reserve(512);\n }\n\n // Encode P-code ops into csleigh structures and append them to the translation buffer\n void dump(const Address &addr, OpCode opc, VarnodeData *outvar, VarnodeData *invars, int4 num_invars)\n {\n LOG(\"Emitting pcode op %d with %d-in,%d-out varnodes from %lx\",\n opc,\n num_invars,\n outvar ? 1 : 0,\n addr.getOffset());\n m_bb_terminating_op_emitted |= opc == CPUI_BRANCH || opc == CPUI_CBRANCH || opc == CPUI_BRANCHIND ||\n opc == CPUI_RETURN || opc == CPUI_CALL || opc == CPUI_CALLIND;\n\n m_ops.emplace_back();\n PcodeOp &op = m_ops.back();\n\n op.m_opcode = opc;\n if (outvar) {\n op.m_output.emplace(*outvar);\n }\n op.m_inputs.reserve(num_invars);\n for (int i = 0; i < num_invars; i++) {\n op.m_inputs.emplace_back(invars[i]);\n }\n }\n};\n\nstruct DisassemblyInstruction {\n Address m_addr;\n uint64_t m_length;\n std::string m_mnem;\n std::string m_body;\n};\n\nclass AssemblyEmitCacher : public AssemblyEmit {\npublic:\n DisassemblyInstruction &m_disas;\n\n AssemblyEmitCacher(DisassemblyInstruction &disas) : m_disas(disas)\n {\n }\n\n void dump(const Address &addr, const std::string &mnem, const std::string &body)\n {\n m_disas.m_addr = addr;\n m_disas.m_mnem = mnem;\n m_disas.m_body = body;\n };\n};\n\nclass Disassembly {\npublic:\n std::vector m_instructions;\n\n Disassembly()\n {\n LOG(\"Disassembly %p created\", this);\n }\n\n Disassembly(Disassembly &&o) noexcept : m_instructions(std::move(o.m_instructions))\n {\n LOG(\"Disassembly moved from %p to %p\", &o, this);\n }\n\n ~Disassembly()\n {\n LOG(\"Disassembly %p released\", this);\n }\n};\n\nclass Translation {\npublic:\n std::vector m_ops;\n\n Translation()\n {\n LOG(\"Translation %p created\", this);\n }\n\n Translation(Translation &&o) noexcept : m_ops(std::move(o.m_ops))\n {\n LOG(\"Translation moved from %p to %p\", &o, this);\n }\n\n ~Translation()\n {\n LOG(\"Translation %p released\", this);\n }\n};\n\nenum TranslateFlags {\n BB_TERMINATING = 1,\n};\n\nclass Context {\npublic:\n SimpleLoadImage m_loader;\n ContextPypcode m_context_db;\n DocumentStorage m_document_storage;\n Document *m_document;\n Element *m_tags;\n std::unique_ptr m_sleigh;\n\n Context(const std::string &path)\n {\n LOG(\"Context %p created\", this);\n\n // FIXME: Globals...\n AttributeId::initialize();\n ElementId::initialize();\n\n LOG(\"%p Loading slafile...\", this);\n istringstream sleighfilename(path);\n m_document = m_document_storage.parseDocument(sleighfilename);\n m_tags = m_document->getRoot();\n m_document_storage.registerTag(m_tags);\n\n LOG(\"Setting up translator\");\n m_sleigh.reset(new Sleigh(&m_loader, &m_context_db));\n m_sleigh->initialize(m_document_storage);\n m_context_db.finalize();\n }\n\n ~Context()\n {\n LOG(\"Context %p released\", this);\n }\n\n void reset(void)\n {\n m_sleigh.reset(new Sleigh(&m_loader, &m_context_db));\n m_sleigh->initialize(m_document_storage);\n m_context_db.finalize();\n }\n\n std::unique_ptr\n disassemble(const char *bytes, unsigned int num_bytes, uint64_t address, unsigned int max_instructions)\n {\n LOG(\"%p Disassembling bytes=%p, num_bytes=%d, address=%lx\", this, bytes, num_bytes, address);\n std::unique_ptr disassembly(new Disassembly());\n int num_instructions = 0;\n uint32_t offset = 0;\n\n m_sleigh->fastReset();\n m_loader.setData(address, (const unsigned char *)bytes, num_bytes);\n disassembly->m_instructions.reserve(10);\n\n while ((offset < num_bytes) && (!max_instructions || (num_instructions < max_instructions))) {\n Address addr(m_sleigh->getDefaultCodeSpace(), address + offset);\n\n disassembly->m_instructions.emplace_back();\n DisassemblyInstruction &ins = disassembly->m_instructions.back();\n\n AssemblyEmitCacher asm_cache(ins);\n\n // Disassemble the next instruction. If an error occurs after successful disassembly of at least one\n // instruction, suppress the error and return the successful disassembly. If the caller attempts\n // disassembly again at the position where the error occurred, then propagate the error.\n try {\n ins.m_length = m_sleigh->printAssembly(asm_cache, addr);\n } catch (BadDataError &err) {\n if (offset) {\n disassembly->m_instructions.resize(num_instructions);\n break;\n }\n throw err;\n }\n\n num_instructions += 1;\n offset += ins.m_length;\n }\n\n return disassembly;\n }\n\n std::unique_ptr translate(const char *bytes,\n unsigned int num_bytes,\n uint64_t base_address,\n unsigned int max_instructions,\n uint32_t flags)\n {\n LOG(\"%p Translating bytes=%p, num_bytes=%d, base_address=0x%lx, max_instructions=%d flags=0x%x\",\n this,\n bytes,\n num_bytes,\n base_address,\n max_instructions,\n flags);\n std::unique_ptr translation(new Translation);\n PcodeEmitCacher pcode_cache;\n uint32_t offset = 0;\n\n m_sleigh->fastReset();\n m_loader.setData(base_address, (const unsigned char *)bytes, num_bytes);\n\n int num_instructions = 0;\n while ((offset < num_bytes) && (!max_instructions || (num_instructions < max_instructions))) {\n Address addr(m_sleigh->getDefaultCodeSpace(), base_address + offset);\n LOG(\"Lifting at 0x%lx+0x%x=0x%lx\", base_address, offset, base_address + offset);\n\n int imark_idx = pcode_cache.m_ops.size();\n pcode_cache.m_ops.emplace_back();\n\n // Translate the next instruction. If an error occurs after successful translation of at least one\n // instruction, suppress the error and return the successful translation. If the caller attempts\n // translation again at the position where the error occurred, then propagate the error.\n uint32_t num_bytes_decoded = 0;\n try {\n num_bytes_decoded = m_sleigh->oneInstruction(pcode_cache, addr);\n } catch (BadDataError &err) {\n if (offset) {\n pcode_cache.m_ops.resize(imark_idx);\n break;\n }\n throw err;\n } catch (UnimplError &err) {\n if (offset) {\n pcode_cache.m_ops.resize(imark_idx);\n break;\n }\n throw err;\n }\n\n PcodeOp &imark_op = pcode_cache.m_ops[imark_idx];\n imark_op.m_opcode = OpCode::CPUI_IMARK;\n\n // Add varnode to imark op for every decoded instruction in this translation\n for (int sum = 0; sum < num_bytes_decoded;) {\n imark_op.m_inputs.emplace_back();\n VarnodeData &imark_vn = imark_op.m_inputs.back();\n imark_vn.space = addr.getSpace();\n imark_vn.offset = addr.getOffset() + sum;\n imark_vn.size = m_sleigh->instructionLength(addr);\n\n sum += imark_vn.size;\n num_instructions++;\n }\n\n if ((flags & TranslateFlags::BB_TERMINATING) && pcode_cache.m_bb_terminating_op_emitted) {\n LOG(\"Reached end of block\");\n break;\n }\n\n offset += num_bytes_decoded;\n }\n\n translation->m_ops = std::move(pcode_cache.m_ops);\n return translation;\n }\n};\n\nNB_MODULE(pypcode_native, m)\n{\n m.attr(\"__version__\") = __version__;\n\n m.doc() = \"pypcode native extension providing machine code disassembly and translation to P-Code.\";\n\n nb::exception(m, \"LowlevelError\"); // \"The lowest level error\"\n nb::exception(m, \"BadDataError\"); // \"Exception for bad instruction data\"\n nb::exception(m, \"UnimplError\"); // \"Exception for encountering unimplemented P-Code\"\n nb::exception(m, \"DecoderError\"); // \"An exception thrown by the XML parser\"\n\n nb::class_(m, \"AddrSpace\", \"A region where processor data is stored.\")\n .def_prop_ro(\n \"name\", [](AddrSpace &as) { return as.getName(); }, \"name(self) -> str\\nThe name of this address space.\");\n\n nb::class_
(m, \"Address\", \"Low level machine byte address.\")\n .def_prop_ro(\n \"space\",\n [](Address &a) { return a.getSpace(); },\n nb::rv_policy::reference_internal,\n \"space(self) -> AddrSpace\\nThe address space.\")\n .def_prop_ro(\n \"offset\", [](Address &a) { return a.getOffset(); }, \"offset(self) -> int\\nThe offset within the space.\");\n\n nb::class_(m, \"Varnode\", \"Data defining a specific memory location.\")\n .def(nb::init<>())\n .def_ro(\"space\",\n &VarnodeData::space,\n nb::rv_policy::reference_internal,\n \"space(self) -> AddrSpace\\nThe address space.\")\n .def_ro(\"offset\", &VarnodeData::offset, \"offset(self) -> int\\nThe offset within the space.\")\n .def_ro(\"size\", &VarnodeData::size, \"size(self) -> int\\nThe number of bytes in the location.\")\n .def(\n \"getRegisterName\",\n [](VarnodeData &a) { return a.space->getTrans()->getRegisterName(a.space, a.offset, a.size); },\n \"Return the register name if this Varnode references a register, otherwise return the empty string.\")\n .def(\n \"getUserDefinedOpName\",\n [](VarnodeData &a) {\n vector userops;\n a.space->getTrans()->getUserOpNames(userops);\n if (a.offset >= userops.size()) {\n throw std::out_of_range(\"index out of range\");\n }\n return userops[a.offset];\n },\n \"Get the name of a user defined operation.\")\n .def(\n \"getSpaceFromConst\",\n [](VarnodeData &a) { return a.getSpaceFromConst(); },\n nb::rv_policy::reference_internal,\n \"Recover encoded address space from constant value.\");\n\n nb::enum_(m, \"OpCode\", \"OpCode defining a specific p-code operation.\")\n .value(\"IMARK\", OpCode::CPUI_IMARK, \"Instruction marker\")\n .value(\"COPY\", OpCode::CPUI_COPY, \"Copy one operand to another\")\n .value(\"LOAD\", OpCode::CPUI_LOAD, \"Load from a pointer into a specified address space\")\n .value(\"STORE\", OpCode::CPUI_STORE, \"Store at a pointer into a specified address space\")\n .value(\"BRANCH\", OpCode::CPUI_BRANCH, \"Always branch\")\n .value(\"CBRANCH\", OpCode::CPUI_CBRANCH, \"Conditional branch\")\n .value(\"BRANCHIND\", OpCode::CPUI_BRANCHIND, \"Indirect branch (jumptable)\")\n .value(\"CALL\", OpCode::CPUI_CALL, \"Call to an absolute address\")\n .value(\"CALLIND\", OpCode::CPUI_CALLIND, \"Call through an indirect address\")\n .value(\"CALLOTHER\", OpCode::CPUI_CALLOTHER, \"User-defined operation\")\n .value(\"RETURN\", OpCode::CPUI_RETURN, \"Return from subroutine\")\n .value(\"INT_EQUAL\", OpCode::CPUI_INT_EQUAL, \"Integer comparison, equality (==)\")\n .value(\"INT_NOTEQUAL\", OpCode::CPUI_INT_NOTEQUAL, \"Integer comparison, in-equality (!=)\")\n .value(\"INT_SLESS\", OpCode::CPUI_INT_SLESS, \"Integer comparison, signed less-than (<)\")\n .value(\"INT_SLESSEQUAL\", OpCode::CPUI_INT_SLESSEQUAL, \"Integer comparison, signed less-than-or-equal (<=)\")\n .value(\"INT_LESS\", OpCode::CPUI_INT_LESS, \"Integer comparison, unsigned less-than (<)\")\n .value(\"INT_LESSEQUAL\", OpCode::CPUI_INT_LESSEQUAL, \"Integer comparison, unsigned less-than-or-equal (<=)\")\n .value(\"INT_ZEXT\", OpCode::CPUI_INT_ZEXT, \"Zero extension\")\n .value(\"INT_SEXT\", OpCode::CPUI_INT_SEXT, \"Sign extension\")\n .value(\"INT_ADD\", OpCode::CPUI_INT_ADD, \"Addition, signed or unsigned (+)\")\n .value(\"INT_SUB\", OpCode::CPUI_INT_SUB, \"Subtraction, signed or unsigned (-)\")\n .value(\"INT_CARRY\", OpCode::CPUI_INT_CARRY, \"Test for unsigned carry\")\n .value(\"INT_SCARRY\", OpCode::CPUI_INT_SCARRY, \"Test for signed carry\")\n .value(\"INT_SBORROW\", OpCode::CPUI_INT_SBORROW, \"Test for signed borrow\")\n .value(\"INT_2COMP\", OpCode::CPUI_INT_2COMP, \"Twos complement\")\n .value(\"INT_NEGATE\", OpCode::CPUI_INT_NEGATE, \"Logical/bitwise negation (~)\")\n .value(\"INT_XOR\", OpCode::CPUI_INT_XOR, \"Logical/bitwise exclusive-or (^)\")\n .value(\"INT_AND\", OpCode::CPUI_INT_AND, \"Logical/bitwise and (&)\")\n .value(\"INT_OR\", OpCode::CPUI_INT_OR, \"Logical/bitwise or (|)\")\n .value(\"INT_LEFT\", OpCode::CPUI_INT_LEFT, \"Left shift (<<)\")\n .value(\"INT_RIGHT\", OpCode::CPUI_INT_RIGHT, \"Right shift, logical (>>)\")\n .value(\"INT_SRIGHT\", OpCode::CPUI_INT_SRIGHT, \"Right shift, arithmetic (>>)\")\n .value(\"INT_MULT\", OpCode::CPUI_INT_MULT, \"Integer multiplication, signed and unsigned (*)\")\n .value(\"INT_DIV\", OpCode::CPUI_INT_DIV, \"Integer division, unsigned (/)\")\n .value(\"INT_SDIV\", OpCode::CPUI_INT_SDIV, \"Integer division, signed (/)\")\n .value(\"INT_REM\", OpCode::CPUI_INT_REM, \"Remainder/modulo, unsigned (%)\")\n .value(\"INT_SREM\", OpCode::CPUI_INT_SREM, \"Remainder/modulo, signed (%)\")\n .value(\"BOOL_NEGATE\", OpCode::CPUI_BOOL_NEGATE, \"Boolean negate (!)\")\n .value(\"BOOL_XOR\", OpCode::CPUI_BOOL_XOR, \"Boolean exclusive-or (^^)\")\n .value(\"BOOL_AND\", OpCode::CPUI_BOOL_AND, \"Boolean and (&&)\")\n .value(\"BOOL_OR\", OpCode::CPUI_BOOL_OR, \"Boolean or (||)\")\n .value(\"FLOAT_EQUAL\", OpCode::CPUI_FLOAT_EQUAL, \"Floating-point comparison, equality (==)\")\n .value(\"FLOAT_NOTEQUAL\", OpCode::CPUI_FLOAT_NOTEQUAL, \"Floating-point comparison, in-equality (!=)\")\n .value(\"FLOAT_LESS\", OpCode::CPUI_FLOAT_LESS, \"Floating-point comparison, less-than (<)\")\n .value(\"FLOAT_LESSEQUAL\", OpCode::CPUI_FLOAT_LESSEQUAL, \"Floating-point comparison, less-than-or-equal (<=)\")\n .value(\"FLOAT_NAN\", OpCode::CPUI_FLOAT_NAN, \"Not-a-number test (NaN)\")\n .value(\"FLOAT_ADD\", OpCode::CPUI_FLOAT_ADD, \"Floating-point addition (+)\")\n .value(\"FLOAT_DIV\", OpCode::CPUI_FLOAT_DIV, \"Floating-point division (/)\")\n .value(\"FLOAT_MULT\", OpCode::CPUI_FLOAT_MULT, \"Floating-point multiplication (*)\")\n .value(\"FLOAT_SUB\", OpCode::CPUI_FLOAT_SUB, \"Floating-point subtraction (-)\")\n .value(\"FLOAT_NEG\", OpCode::CPUI_FLOAT_NEG, \"Floating-point negation (-)\")\n .value(\"FLOAT_ABS\", OpCode::CPUI_FLOAT_ABS, \"Floating-point absolute value (abs)\")\n .value(\"FLOAT_SQRT\", OpCode::CPUI_FLOAT_SQRT, \"Floating-point square root (sqrt)\")\n .value(\"FLOAT_INT2FLOAT\", OpCode::CPUI_FLOAT_INT2FLOAT, \"Convert an integer to a floating-point\")\n .value(\"FLOAT_FLOAT2FLOAT\", OpCode::CPUI_FLOAT_FLOAT2FLOAT, \"Convert between different floating-point sizes\")\n .value(\"FLOAT_TRUNC\", OpCode::CPUI_FLOAT_TRUNC, \"Round towards zero\")\n .value(\"FLOAT_CEIL\", OpCode::CPUI_FLOAT_CEIL, \"Round towards +infinity\")\n .value(\"FLOAT_FLOOR\", OpCode::CPUI_FLOAT_FLOOR, \"Round towards -infinity\")\n .value(\"FLOAT_ROUND\", OpCode::CPUI_FLOAT_ROUND, \"Round towards nearest\")\n .value(\"MULTIEQUAL\", OpCode::CPUI_MULTIEQUAL, \"Phi-node operator\")\n .value(\"INDIRECT\", OpCode::CPUI_INDIRECT, \"Copy with an indirect effect\")\n .value(\"PIECE\", OpCode::CPUI_PIECE, \"Concatenate\")\n .value(\"SUBPIECE\", OpCode::CPUI_SUBPIECE, \"Truncate\")\n .value(\"CAST\", OpCode::CPUI_CAST, \"Cast from one data-type to another\")\n .value(\"PTRADD\", OpCode::CPUI_PTRADD, \"Index into an array ([])\")\n .value(\"PTRSUB\", OpCode::CPUI_PTRSUB, \"Drill down to a sub-field (->)\")\n .value(\"SEGMENTOP\", OpCode::CPUI_SEGMENTOP, \"Look-up a segmented address\")\n .value(\"CPOOLREF\", OpCode::CPUI_CPOOLREF, \"Recover a value from the constant pool\")\n .value(\"NEW\", OpCode::CPUI_NEW, \"Allocate a new object (new)\")\n .value(\"INSERT\", OpCode::CPUI_INSERT, \"Insert a bit-range\")\n .value(\"EXTRACT\", OpCode::CPUI_EXTRACT, \"Extract a bit-range\")\n .value(\"POPCOUNT\", OpCode::CPUI_POPCOUNT, \"Count the 1-bits\")\n .value(\"LZCOUNT\", OpCode::CPUI_LZCOUNT, \"Count the leading 0-bits\");\n\n nb::class_(m, \"PcodeOp\", \"Low-level representation of a single P-Code operation.\")\n .def_ro(\"opcode\", &PcodeOp::m_opcode, \"opcode(self) -> OpCode\\nOpcode for this operation.\")\n .def_ro(\"output\", &PcodeOp::m_output, \"output(self) -> Optional[Varnode]\\nOutput varnode for this operation.\")\n .def_ro(\"inputs\", &PcodeOp::m_inputs, \"inputs(self) -> List[Varnode]\\nInput varnodes for this operation.\");\n\n nb::class_(m, \"Translation\", \"P-Code translation.\")\n .def_ro(\"ops\", &Translation::m_ops, \"ops(self) -> List[PcodeOp]\\nThe translated sequence of P-Code ops.\");\n\n nb::class_(m, \"Instruction\", \"Disassembled machine code instruction.\")\n .def_ro(\"addr\", &DisassemblyInstruction::m_addr, \"addr(self) -> Address\\nAddress of this instruction.\")\n .def_ro(\n \"length\", &DisassemblyInstruction::m_length, \"length(self) -> int\\nLength, in bytes, of this instruction.\")\n .def_ro(\"mnem\", &DisassemblyInstruction::m_mnem, \"mnem(self) -> str\\nMnemonic string of this instruction.\")\n .def_ro(\"body\", &DisassemblyInstruction::m_body, \"body(self) -> str\\nOperand string of this instruction.\");\n\n nb::class_(m, \"Disassembly\", \"Machine Code Disassembly.\")\n .def_ro(\"instructions\",\n &Disassembly::m_instructions,\n \"instructions(self) -> List[Instruction]\\nThe disassembled instructions.\");\n\n m.attr(\"TRANSLATE_FLAGS_BB_TERMINATING\") = static_cast(TranslateFlags::BB_TERMINATING);\n\n nb::class_(m, \"Context\", \"Context for machine code translation and disassembly.\")\n .def(nb::init())\n .def(\n \"disassemble\",\n [](Context &t,\n nb::bytes buf,\n uint64_t base_address,\n uint64_t offset,\n uint64_t max_bytes,\n uint64_t max_instructions) {\n if (offset >= buf.size()) {\n throw std::out_of_range(\"offset out of range\");\n }\n uint64_t available_bytes = buf.size() - offset;\n max_bytes = max_bytes ? MIN(max_bytes, available_bytes) : available_bytes;\n return t.disassemble(buf.c_str() + offset, max_bytes, base_address, max_instructions);\n },\n \"buf\"_a,\n \"base_address\"_a = 0,\n \"offset\"_a = 0,\n \"max_bytes\"_a = 0,\n \"max_instructions\"_a = 0,\n nb::keep_alive<0, 1>(),\n R\"(Disassemble and format machine code as assembly code.\n\n .. ipython::\n\n In [0]: import pypcode\n ...: ctx = pypcode.Context(\"x86:LE:64:default\")\n ...: dx = ctx.disassemble(b\"\\x48\\x35\\x78\\x56\\x34\\x12\\xc3\")\n ...: for ins in dx.instructions:\n ...: print(f\"{ins.addr.offset:#x}/{ins.length}: {ins.mnem} {ins.body}\")\n 0x0/6: XOR RAX,0x12345678\n 0x6/1: RET\n\n Instructions are decoded from ``buf`` and formatted in :class:`.Instruction` s:\n * the end of the buffer is reached,\n * ``max_bytes`` or ``max_instructions`` is reached, or\n * an exception occurs.\n\n If an exception occurs following successful disassembly of at least one instruction, the exception is\n discarded and the successful disassembly is returned. If the exception occurs at disassembly of the first\n instruction, it will be raised. See below for possible exceptions.\n\n Args:\n buf (bytes): Machine code to disassemble.\n base_address (int): Base address of the code at offset being decoded, 0 by default.\n offset (int): Offset into ``bytes`` to begin disassembly, 0 by default.\n max_bytes (int): Maximum number of bytes to disassemble, or 0 for no limit (default).\n max_instructions (int): Maximum number of instructions to disassemble, or 0 for no limit (default).\n\n Returns:\n Disassembly: The disassembled machine code. Instructions are accessible through :attr:`.Disassembly.instructions`.\n\n Raises:\n BadDataError: The instruction at ``base_address`` could be decoded.\n )\")\n .def(\n \"getAllRegisters\",\n [](Context &t) {\n map regmap;\n t.m_sleigh->getAllRegisters(regmap);\n return regmap;\n },\n \"Get a mapping of all register locations to their corresponding names.\")\n .def(\n \"getRegisterName\",\n [](Context &t, AddrSpace *space, uint64_t offset, uint32_t size) {\n return t.m_sleigh->getRegisterName(space, offset, size);\n },\n \"space\"_a,\n \"offset\"_a,\n \"size\"_a,\n R\"(Get the name of a register.\n\n Args:\n space (AddrSpace): The address space.\n offset (int): Offset within the address space.\n size (int): Size of the register, in bytes.\n\n Returns:\n str: The register name, or the empty string if the register could not be identified.\n )\")\n .def(\"reset\", &Context::reset, \"Reset the context.\")\n .def(\n \"setVariableDefault\",\n [](Context &t, const std::string &name, uint32_t value) { t.m_context_db.setVariableDefault(name, value); },\n \"name\"_a,\n \"value\"_a,\n \"Provide a default value for a context variable.\")\n .def(\n \"translate\",\n [](Context &t,\n nb::bytes buf,\n uint64_t base_address,\n uint64_t offset,\n uint64_t max_bytes,\n uint64_t max_instructions,\n uint64_t flags) {\n if (offset >= buf.size()) {\n throw std::out_of_range(\"offset out of range\");\n }\n uint64_t available_bytes = buf.size() - offset;\n max_bytes = max_bytes ? MIN(max_bytes, available_bytes) : available_bytes;\n return t.translate(buf.c_str() + offset, max_bytes, base_address, max_instructions, flags);\n },\n \"buf\"_a,\n \"base_address\"_a = 0,\n \"offset\"_a = 0,\n \"max_bytes\"_a = 0,\n \"max_instructions\"_a = 0,\n \"flags\"_a = 0,\n nb::keep_alive<0, 1>(),\n R\"(Translate machine code to P-Code.\n\n .. ipython::\n\n In [0]: import pypcode\n ...: ctx = pypcode.Context(\"x86:LE:64:default\")\n ...: tx = ctx.translate(b\"\\x48\\x35\\x78\\x56\\x34\\x12\\xc3\") # xor rax, 0x12345678; ret\n ...: print(tx)\n IMARK ram[0:6]\n CF = 0x0\n OF = 0x0\n RAX = RAX ^ 0x12345678\n SF = RAX s< 0x0\n ZF = RAX == 0x0\n unique[28080:8] = RAX & 0xff\n unique[28100:1] = popcount(unique[28080:8])\n unique[28180:1] = unique[28100:1] & 0x1\n PF = unique[28180:1] == 0x0\n IMARK ram[6:1]\n RIP = *[ram]RSP\n RSP = RSP + 0x8\n return RIP\n\n Instructions are decoded from ``buf`` and translated to a sequence of :class:`.PcodeOp` s until:\n * the end of the buffer is reached,\n * ``max_bytes`` or ``max_instructions`` is reached,\n * if the ``BB_TERMINATING`` flag is set, an instruction which performs a branch is encountered, or\n * an exception occurs.\n\n A :class:`.PcodeOp` with opcode :attr:`OpCode.IMARK` is used to identify machine instructions corresponding\n to a translation. :attr:`OpCode.IMARK` ops precede the corresponding P-Code translation, and will have one\n or more input :class:`.Varnode` s identifying the address and length in bytes of the source machine\n instruction(s). The number of input :class:`.Varnode` s depends on the number of instructions that were\n decoded for the translation of the particular instruction.\n\n On architectures with branch delay slots, the effects of the delay slot instructions will be included in the\n translation of the branch instruction. For this reason, it is possible that more instructions than\n specified in ``max_instructions`` may be translated. The :attr:`OpCode.IMARK` op identifying the branch\n instruction will contain an input :class:`.Varnode` corresponding to the branch instruction, with\n additional input :class:`.Varnode` identifying corresponding delay slot instructions.\n\n If an exception occurs following successful translation of at least one instruction, the exception is\n discarded and the successful translation is returned. If the exception occurs during translation of the\n first instruction, the exception will be raised. See below for possible exceptions.\n\n Args:\n buf (bytes): Machine code to translate.\n base_address (int): Base address of the code at offset being decoded.\n offset (int): Offset into ``bytes`` to begin translation.\n max_bytes (int): Maximum number of bytes to translate.\n max_instructions (int): Maximum number of instructions to translate.\n flags (int): Flags controlling translation. See :class:`.TranslateFlags`.\n\n Returns:\n Translation: The P-Code translation of the input machine code. P-Code ops are accessible through :attr:`.Translation.ops`.\n\n Raises:\n BadDataError: The instruction at ``base_address`` could not be decoded.\n UnimplError: The P-Code for instruction at ``base_address`` is not yet implemented.\n )\");\n}\n" }, { "path": "pypcode/pypcode_native.pyi", "content": "from typing import Any, ClassVar, List, Optional\n\n__version__: str\n\nTRANSLATE_FLAGS_BB_TERMINATING: int\n\nclass BadDataError(Exception): ...\nclass DecoderError(Exception): ...\nclass LowlevelError(Exception): ...\nclass UnimplError(Exception): ...\n\nclass AddrSpace:\n def __init__(self, *args, **kwargs) -> None: ...\n @property\n def name(self) -> str: ...\n\nclass Address:\n def __init__(self, *args, **kwargs) -> None: ...\n @property\n def offset(self) -> int: ...\n @property\n def space(self) -> AddrSpace: ...\n\nclass Instruction:\n def __init__(self, *args, **kwargs) -> None: ...\n @property\n def addr(self) -> Address: ...\n @property\n def body(self) -> str: ...\n @property\n def length(self) -> int: ...\n @property\n def mnem(self) -> str: ...\n\nclass Disassembly:\n def __init__(self, *args, **kwargs) -> None: ...\n @property\n def instructions(self) -> List[Instruction]: ...\n\nclass OpCode:\n BOOL_AND: ClassVar[OpCode] = ...\n BOOL_NEGATE: ClassVar[OpCode] = ...\n BOOL_OR: ClassVar[OpCode] = ...\n BOOL_XOR: ClassVar[OpCode] = ...\n BRANCH: ClassVar[OpCode] = ...\n BRANCHIND: ClassVar[OpCode] = ...\n CALL: ClassVar[OpCode] = ...\n CALLIND: ClassVar[OpCode] = ...\n CALLOTHER: ClassVar[OpCode] = ...\n CAST: ClassVar[OpCode] = ...\n CBRANCH: ClassVar[OpCode] = ...\n COPY: ClassVar[OpCode] = ...\n CPOOLREF: ClassVar[OpCode] = ...\n EXTRACT: ClassVar[OpCode] = ...\n FLOAT_ABS: ClassVar[OpCode] = ...\n FLOAT_ADD: ClassVar[OpCode] = ...\n FLOAT_CEIL: ClassVar[OpCode] = ...\n FLOAT_DIV: ClassVar[OpCode] = ...\n FLOAT_EQUAL: ClassVar[OpCode] = ...\n FLOAT_FLOAT2FLOAT: ClassVar[OpCode] = ...\n FLOAT_FLOOR: ClassVar[OpCode] = ...\n FLOAT_INT2FLOAT: ClassVar[OpCode] = ...\n FLOAT_LESS: ClassVar[OpCode] = ...\n FLOAT_LESSEQUAL: ClassVar[OpCode] = ...\n FLOAT_MULT: ClassVar[OpCode] = ...\n FLOAT_NAN: ClassVar[OpCode] = ...\n FLOAT_NEG: ClassVar[OpCode] = ...\n FLOAT_NOTEQUAL: ClassVar[OpCode] = ...\n FLOAT_ROUND: ClassVar[OpCode] = ...\n FLOAT_SQRT: ClassVar[OpCode] = ...\n FLOAT_SUB: ClassVar[OpCode] = ...\n FLOAT_TRUNC: ClassVar[OpCode] = ...\n IMARK: ClassVar[OpCode] = ...\n INDIRECT: ClassVar[OpCode] = ...\n INSERT: ClassVar[OpCode] = ...\n INT_2COMP: ClassVar[OpCode] = ...\n INT_ADD: ClassVar[OpCode] = ...\n INT_AND: ClassVar[OpCode] = ...\n INT_CARRY: ClassVar[OpCode] = ...\n INT_DIV: ClassVar[OpCode] = ...\n INT_EQUAL: ClassVar[OpCode] = ...\n INT_LEFT: ClassVar[OpCode] = ...\n INT_LESS: ClassVar[OpCode] = ...\n INT_LESSEQUAL: ClassVar[OpCode] = ...\n INT_MULT: ClassVar[OpCode] = ...\n INT_NEGATE: ClassVar[OpCode] = ...\n INT_NOTEQUAL: ClassVar[OpCode] = ...\n INT_OR: ClassVar[OpCode] = ...\n INT_REM: ClassVar[OpCode] = ...\n INT_RIGHT: ClassVar[OpCode] = ...\n INT_SBORROW: ClassVar[OpCode] = ...\n INT_SCARRY: ClassVar[OpCode] = ...\n INT_SDIV: ClassVar[OpCode] = ...\n INT_SEXT: ClassVar[OpCode] = ...\n INT_SLESS: ClassVar[OpCode] = ...\n INT_SLESSEQUAL: ClassVar[OpCode] = ...\n INT_SREM: ClassVar[OpCode] = ...\n INT_SRIGHT: ClassVar[OpCode] = ...\n INT_SUB: ClassVar[OpCode] = ...\n INT_XOR: ClassVar[OpCode] = ...\n INT_ZEXT: ClassVar[OpCode] = ...\n LOAD: ClassVar[OpCode] = ...\n MULTIEQUAL: ClassVar[OpCode] = ...\n NEW: ClassVar[OpCode] = ...\n PIECE: ClassVar[OpCode] = ...\n POPCOUNT: ClassVar[OpCode] = ...\n LZCOUNT: ClassVar[OpCode] = ...\n PTRADD: ClassVar[OpCode] = ...\n PTRSUB: ClassVar[OpCode] = ...\n RETURN: ClassVar[OpCode] = ...\n SEGMENTOP: ClassVar[OpCode] = ...\n STORE: ClassVar[OpCode] = ...\n SUBPIECE: ClassVar[OpCode] = ...\n __entries: ClassVar[dict] = ...\n __name__: Any\n @property\n def name(self) -> str: ...\n @property\n def value(self) -> int: ...\n def __init__(self, *args, **kwargs) -> None: ...\n def __eq__(self, other) -> Any: ...\n def __ge__(self, other) -> Any: ...\n def __gt__(self, other) -> Any: ...\n def __hash__(self) -> Any: ...\n def __index__(self) -> Any: ...\n def __int__(self) -> Any: ...\n def __le__(self, other) -> Any: ...\n def __lt__(self, other) -> Any: ...\n def __ne__(self, other) -> Any: ...\n\nclass Varnode:\n def __init__(self) -> None: ...\n def getRegisterName(self) -> str: ...\n def getUserDefinedOpName(self) -> str: ...\n def getSpaceFromConst(self) -> AddrSpace: ...\n @property\n def offset(self) -> int: ...\n @property\n def size(self) -> int: ...\n @property\n def space(self) -> AddrSpace: ...\n\nclass PcodeOp:\n def __init__(self, *args, **kwargs) -> None: ...\n @property\n def inputs(self) -> List[Varnode]: ...\n @property\n def opcode(self) -> OpCode: ...\n @property\n def output(self) -> Optional[Varnode]: ...\n\nclass Translation:\n def __init__(self, *args, **kwargs) -> None: ...\n @property\n def ops(self) -> List[PcodeOp]: ...\n\nclass Context:\n def __init__(self, *args, **kwargs) -> None: ...\n def disassemble(\n self,\n bytes: bytes,\n base_address: int = ...,\n offset: int = ...,\n max_bytes: int = ...,\n max_instructions: int = ...,\n ) -> Disassembly: ...\n def getAllRegisters(self) -> dict[Varnode, str]: ...\n def getRegisterName(self, space: AddrSpace, offset: int, size: int) -> str: ...\n def reset(self) -> None: ...\n def setVariableDefault(self, name: str, value: int) -> None: ...\n def translate(\n self,\n bytes: bytes,\n base_address: int = ...,\n offset: int = ...,\n max_bytes: int = ...,\n max_instructions: int = ...,\n flags: int = ...,\n ) -> Translation: ...\n" }, { "path": "pypcode/sleigh/Makefile", "content": "# The C compiler\nBFDHOME=/usr\n\nMAKE_STATIC=\nARCH_TYPE=\nADDITIONAL_FLAGS=\nSLEIGHVERSION=sleigh-2.1.0\n\nEXTENSION_POINT=../../../../../../../ghidra.ext-u/Ghidra/Features/DecompilerExtensions/src/decompile/cpp\nGHIDRA_BIN=../../../../../../../ghidra.bin\n\nOS = $(shell uname -s)\nCPU = $(shell uname -m)\n\n# TODO: need to revise to support arm64/aarch64 arch - improve on both OS and arch detection \n\nifeq ($(OS),Linux)\n# Allow ARCH to be specified externally so we can build for 32-bit from a 64-bit Linux\nifndef ARCH\n ARCH=$(CPU)\nendif\nifeq ($(ARCH),x86_64)\n ARCH_TYPE=-m64\n OSDIR=linux_x86_64\nelse\n ARCH_TYPE=-m32\n OSDIR=linux_x86_32\nendif\nendif\n\nifeq ($(OS),Darwin)\n MAKE_STATIC=\n ARCH_TYPE=-arch x86_64\n ADDITIONAL_FLAGS=-mmacosx-version-min=10.6 -w\n OSDIR=mac_x86_64\nendif\n\nCXX=g++ -std=c++11\n\n# Debug flags\nDBG_CXXFLAGS=-g -Wall -Wno-sign-compare $(CFLAGS)\n#DBG_CXXFLAGS=-g -pg -Wall -Wno-sign-compare\n#DBG_CXXFLAGS=-g -fprofile-arcs -ftest-coverage -Wall -Wno-sign-compare\n\n# Optimization flags\nOPT_CXXFLAGS=-O2 -Wall -Wno-sign-compare $(CFLAGS)\n\nYACC=bison\n\n# libraries\n#INCLUDES=-I$(BFDHOME)/include\nINCLUDES=\nBFDLIB=-lbfd\n\nLNK=-lz\n\n# Source files\nALL_SOURCE= $(wildcard *.cc)\nALL_NAMES=$(subst .cc,,$(ALL_SOURCE))\nUNITTEST_SOURCE= $(wildcard ../unittests/*.cc)\nUNITTEST_NAMES=$(subst .cc,,$(UNITTEST_SOURCE))\nUNITTEST_STRIP=$(subst ../unittests/,,$(UNITTEST_NAMES))\n\nCOREEXT_SOURCE= $(wildcard coreext_*.cc)\nCOREEXT_NAMES=$(subst .cc,,$(COREEXT_SOURCE))\n\nGHIDRAEXT_SOURCE= $(wildcard ghidraext_*.cc)\nGHIDRAEXT_NAMES=$(subst .cc,,$(GHIDRAEXT_SOURCE))\n\nEXTERNAL_COREEXT_SOURCE= $(wildcard $(EXTENSION_POINT)/coreext_*.cc)\nEXTERNAL_GHIDRAEXT_SOURCE= $(wildcard $(EXTENSION_POINT)/ghidraext_*.cc)\nEXTERNAL_CONSOLEEXT_SOURCE= $(wildcard $(EXTENSION_POINT)/consoleext_*.cc)\nEXTERNAL_COREEXT_NAMES=$(subst .cc,,$(notdir $(EXTERNAL_COREEXT_SOURCE)))\nEXTERNAL_GHIDRAEXT_NAMES=$(subst .cc,,$(notdir $(EXTERNAL_GHIDRAEXT_SOURCE)))\nEXTERNAL_CONSOLEEXT_NAMES=$(subst .cc,,$(notdir $(EXTERNAL_CONSOLEEXT_SOURCE)))\n\n# The following macros partition all the source files, there should be no overlaps\n# Some core source files used in all projects\nCORE=\txml marshal space float address pcoderaw translate opcodes globalcontext\n# Additional core files for any projects that decompile\nDECCORE=capability architecture options graph cover block cast typeop database cpool \\\n\tcomment stringmanage modelrules fspec action loadimage grammar varnode op type \\\n\tvariable varmap jumptable emulate emulateutil flow userop expression multiprecision \\\n\tfuncdata funcdata_block funcdata_op funcdata_varnode unionresolve pcodeinject \\\n\theritage prefersplit rangeutil ruleaction subflow blockaction merge double \\\n\ttransform constseq coreaction condexe override dynamic crc32 prettyprint \\\n\tprintlanguage printc printjava memstate opbehavior paramid signature $(COREEXT_NAMES)\n# Files used for any project that use the sleigh decoder\nSLEIGH=\tsleigh pcodeparse pcodecompile sleighbase slghsymbol \\\n\tslghpatexpress slghpattern semantics context slaformat compression filemanage\n# Additional files for the GHIDRA specific build\nGHIDRA=\tghidra_arch inject_ghidra ghidra_translate loadimage_ghidra \\\n\ttypegrp_ghidra database_ghidra ghidra_context cpool_ghidra \\\n\tghidra_process comment_ghidra string_ghidra signature_ghidra $(GHIDRAEXT_NAMES)\n# Additional files specific to the sleigh compiler\nSLACOMP=slgh_compile slghparse slghscan\n# Additional special files that should not be considered part of the library\nSPECIAL=consolemain sleighexample test\n# Any additional modules for the command line decompiler\nEXTRA= $(filter-out $(CORE) $(DECCORE) $(SLEIGH) $(GHIDRA) $(SLACOMP) $(SPECIAL),$(ALL_NAMES))\n\nEXECS=decomp_dbg decomp_opt decomp_test_dbg ghidra_dbg ghidra_opt sleigh_dbg sleigh_opt libdecomp_dbg.a libdecomp.a\n\n# Possible conditional compilation flags\n# __TERMINAL__ # Turn on terminal support for console mode\n# CPUI_STATISTICS # Turn on collection of cover and cast statistics\n# CPUI_RULECOMPILE # Allow user defined dynamic rules\n\n# Debug compilation flags\n# OPACTION_DEBUG # Turns on all the action tracing facilities\n# MERGEMULTI_DEBUG # Check for MULTIEQUAL and INDIRECT intersections\n# BLOCKCONSISTENT_DEBUG # Check that block graph structure is consistent\n# DFSVERIFY_DEBUG # make sure that the block ordering algorithm produces\n# a true depth first traversal of the dominator tree\n# CPUI_DEBUG # This is the one controlling switch for all the other debug switches\n\nCOMMANDLINE_NAMES=$(CORE) $(DECCORE) $(EXTRA) $(SLEIGH) consolemain\nCOMMANDLINE_DEBUG=-DCPUI_DEBUG -D__TERMINAL__\nCOMMANDLINE_OPT=-D__TERMINAL__\n\nTEST_NAMES=$(CORE) $(DECCORE) $(SLEIGH) $(EXTRA) test \nTEST_DEBUG=-D__TERMINAL__\n\nGHIDRA_NAMES=$(CORE) $(DECCORE) $(GHIDRA)\nGHIDRA_NAMES_DBG=$(GHIDRA_NAMES) callgraph ifacedecomp testfunction ifaceterm interface\nGHIDRA_DEBUG=-DCPUI_DEBUG\nGHIDRA_OPT=\n\nSLEIGH_NAMES=$(CORE) $(SLEIGH) $(SLACOMP)\nSLEIGH_DEBUG=-DYYDEBUG\nSLEIGH_OPT=\n\n# The SLEIGH library is built with console mode objects and it\n# uses the COMMANDLINE_* options\nLIBSLA_NAMES=$(CORE) $(SLEIGH) loadimage sleigh memstate emulate opbehavior\n\n# The Decompiler library is built with console mode objects and it uses the COMMANDLINE_* options\nLIBDECOMP_NAMES=$(CORE) $(DECCORE) $(EXTRA) $(SLEIGH)\n\n# object file macros\nCOMMANDLINE_DBG_OBJS=$(COMMANDLINE_NAMES:%=com_dbg/%.o)\nCOMMANDLINE_OPT_OBJS=$(COMMANDLINE_NAMES:%=com_opt/%.o)\nTEST_DEBUG_OBJS=$(TEST_NAMES:%=test_dbg/%.o) $(UNITTEST_STRIP:%=test_dbg/%.o)\nGHIDRA_DBG_OBJS=$(GHIDRA_NAMES_DBG:%=ghi_dbg/%.o)\nGHIDRA_OPT_OBJS=$(GHIDRA_NAMES:%=ghi_opt/%.o)\nSLEIGH_DBG_OBJS=$(SLEIGH_NAMES:%=sla_dbg/%.o)\nSLEIGH_OPT_OBJS=$(SLEIGH_NAMES:%=sla_opt/%.o)\nLIBSLA_DBG_OBJS=$(LIBSLA_NAMES:%=com_dbg/%.o)\nLIBSLA_OPT_OBJS=$(LIBSLA_NAMES:%=com_opt/%.o)\nLIBSLA_SOURCE=$(LIBSLA_NAMES:%=%.cc) $(LIBSLA_NAMES:%=%.hh) \\\n\t$(SLACOMP:%=%.cc) slgh_compile.hh slghparse.hh types.h \\\n\tpartmap.hh error.hh slghparse.y pcodeparse.y xml.y slghscan.l loadimage_bfd.hh loadimage_bfd.cc\nLIBDECOMP_DBG_OBJS=$(LIBDECOMP_NAMES:%=com_dbg/%.o)\nLIBDECOMP_OPT_OBJS=$(LIBDECOMP_NAMES:%=com_opt/%.o)\n\n# conditionals to determine which dependency files to build\nDEPNAMES=com_dbg/depend com_opt/depend\nifeq ($(MAKECMDGOALS),install_ghidraopt)\n\tDEPNAMES=ghi_opt/depend\nendif\nifeq ($(MAKECMDGOALS),install_ghidradbg)\n\tDEPNAMES=ghi_dbg/depend\nendif\nifeq ($(MAKECMDGOALS),ghidra_opt)\n\tDEPNAMES=ghi_opt/depend\nendif\nifeq ($(MAKECMDGOALS),ghidra_opt_mac)\n\tDEPNAMES=ghi_opt/depend\nendif\nifeq ($(MAKECMDGOALS),ghidra_dbg)\n\tDEPNAMES=ghi_dbg/depend\nendif\nifeq ($(MAKECMDGOALS),sleigh_opt)\n\tDEPNAMES=sla_opt/depend\nendif\nifeq ($(MAKECMDGOALS),sleigh_opt_mac)\n\tDEPNAMES=sla_opt/depend\nendif\nifeq ($(MAKECMDGOALS),sleigh_dbg)\n\tDEPNAMES=sla_dbg/depend\nendif\nifeq ($(MAKECMDGOALS),libsla.a)\n\tDEPNAMES=com_opt/depend.lib_sla\nendif\nifeq ($(MAKECMDGOALS),libsla_dbg.a)\n\tDEPNAMES=com_dbg/depend.lib_sla\nendif\nifeq ($(MAKECMDGOALS),decomp_dbg)\n\tDEPNAMES=com_dbg/depend\nendif\nifeq ($(MAKECMDGOALS),decomp_opt)\n\tDEPNAMES=com_opt/depend\nendif\nifneq (,$(filter $(MAKECMDGOALS),decomp_test_dbg test))\n\tDEPNAMES=test_dbg/depend\nendif\nifeq ($(MAKECMDGOALS),reallyclean)\n\tDEPNAMES=\nendif\nifeq ($(MAKECMDGOALS),clean)\n\tDEPNAMES=\nendif\nifeq ($(MAKECMDGOALS),doc)\n\tDEPNAMES=\nendif\nifeq ($(MAKECMDGOALS),tags)\n\tDEPNAMES=\nendif\nifeq ($(MAKECMDGOALS),link_extensions)\n\tDEPNAMES=\nendif\nifeq ($(MAKECMDGOALS),link_extensions_hard)\n\tDEPNAMES=\nendif\n\ncom_dbg/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(COMMANDLINE_DEBUG) $< -o $@\ncom_opt/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(OPT_CXXFLAGS) $(ADDITIONAL_FLAGS) $(COMMANDLINE_OPT) $< -o $@\ntest_dbg/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(TEST_DEBUG) $< -o $@\ntest_dbg/%.o:\t../unittests/%.cc\n\t$(CXX) -I. $(ARCH_TYPE) -c $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(TEST_DEBUG) $< -o $@\nghi_dbg/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(GHIDRA_DEBUG) $< -o $@\nghi_opt/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(OPT_CXXFLAGS) $(ADDITIONAL_FLAGS) $(GHIDRA_OPT) $< -o $@\nsla_dbg/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(SLEIGH_DEBUG) $< -o $@\nsla_opt/%.o:\t%.cc\n\t$(CXX) $(ARCH_TYPE) -c $(OPT_CXXFLAGS) $(ADDITIONAL_FLAGS) $(SLEIGH_OPT) $< -o $@\n\ngrammar.cc:\tgrammar.y\n\t$(YACC) -l -o $@ $<\nxml.cc:\txml.y\n\t$(YACC) -l -o $@ $<\npcodeparse.cc:\tpcodeparse.y\n\t$(YACC) -l -o $@ $<\nslghparse.cc:\tslghparse.y\n\t$(YACC) -l -d -o $@ $<\nslghscan.cc:\tslghscan.l\n\t$(LEX) -L -o$@ $<\nruleparse.cc:\truleparse.y\n\t$(YACC) -p ruleparse -d -o $@ $<\n\nslghparse.hh:\tslghparse.y slghparse.cc\nslghscan.cc:\tslghparse.hh slgh_compile.hh\nruleparse.hh:\truleparse.y ruleparse.cc\n\ndecomp_dbg:\t$(COMMANDLINE_DBG_OBJS)\n\t$(CXX) $(DBG_CXXFLAGS) $(ARCH_TYPE) -o decomp_dbg $(COMMANDLINE_DBG_OBJS) $(BFDLIB) $(LNK)\n\ndecomp_opt:\t$(COMMANDLINE_OPT_OBJS)\n\t$(CXX) $(OPT_CXXFLAGS) $(ARCH_TYPE) -o decomp_opt $(COMMANDLINE_OPT_OBJS) $(BFDLIB) $(LNK)\n\n#decomp_test_dbg:\tDBG_CXXFLAGS += -D_GLIBCXX_ASSERTIONS -fsanitize=address,undefined\ndecomp_test_dbg:\t$(TEST_DEBUG_OBJS)\n\t$(CXX) $(DBG_CXXFLAGS) $(ARCH_TYPE) -o decomp_test_dbg $(TEST_DEBUG_OBJS) $(BFDLIB) $(LNK)\n\ntest: decomp_test_dbg\n\t./decomp_test_dbg\n\nghidra_dbg:\t$(GHIDRA_DBG_OBJS)\n\t$(CXX) $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(MAKE_STATIC) $(ARCH_TYPE) -o ghidra_dbg $(GHIDRA_DBG_OBJS)\n\nghidra_opt:\t$(GHIDRA_OPT_OBJS)\n\t$(CXX) $(OPT_CXXFLAGS) $(ADDITIONAL_FLAGS) $(MAKE_STATIC) $(ARCH_TYPE) -o ghidra_opt $(GHIDRA_OPT_OBJS)\n\nsleigh_dbg:\t$(SLEIGH_DBG_OBJS)\n\t$(CXX) $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(MAKE_STATIC) $(ARCH_TYPE) -o sleigh_dbg $(SLEIGH_DBG_OBJS) $(LNK)\n\nsleigh_opt:\t$(SLEIGH_OPT_OBJS)\n\t$(CXX) $(OPT_CXXFLAGS) $(ADDITIONAL_FLAGS) $(MAKE_STATIC) $(ARCH_TYPE) -o sleigh_opt $(SLEIGH_OPT_OBJS) $(LNK)\n\ninstall_ghidradbg:\tghidra_dbg\n\tcp ghidra_dbg $(GHIDRA_BIN)/Ghidra/Features/Decompiler/os/$(OSDIR)/decompile\n\ninstall_ghidraopt:\tghidra_opt\n\tcp ghidra_opt $(GHIDRA_BIN)/Ghidra/Features/Decompiler/os/$(OSDIR)/decompile\n\nlibsla_dbg.a:\t$(LIBSLA_DBG_OBJS)\n\trm -rf libsla_dbg.a\n\tar qc libsla_dbg.a $(LIBSLA_DBG_OBJS)\n\tranlib libsla_dbg.a\n\nlibsla.a:\t$(LIBSLA_OPT_OBJS)\n\trm -rf libsla.a\n\tar qc libsla.a $(LIBSLA_OPT_OBJS)\n\tranlib libsla.a\n\nlibdecomp_dbg.a:\t$(LIBDECOMP_DBG_OBJS)\n\trm -rf libdecomp_dbg.a\n\tar qc libdecomp_dbg.a $(LIBDECOMP_DBG_OBJS)\n\tranlib libdecomp_dbg.a\n\nlibdecomp.a:\t$(LIBDECOMP_OPT_OBJS)\n\trm -rf libdecomp.a\n\tar qc libdecomp.a $(LIBDECOMP_OPT_OBJS)\n\tranlib libdecomp.a\n\nsleighexamp_dir: slghscan.cc\n\trm -rf $(SLEIGHVERSION)\n\tmkdir $(SLEIGHVERSION)\n\tmkdir $(SLEIGHVERSION)/src $(SLEIGHVERSION)/specfiles\n\tcp ../../../../../Processors/x86/data/languages/x86.sla \\\n\t ../../../../../Processors/x86/data/languages/x86.slaspec \\\n\t ../../../../../Processors/x86/data/languages/ia.sinc \\\n\t\t $(SLEIGHVERSION)/specfiles\n\tcp $(LIBSLA_SOURCE) Makefile Doxyfile $(SLEIGHVERSION)/src\n\tcp sleighexample.cc $(SLEIGHVERSION)\n\tgrep ^-- sleighexample.cc | sed -e s/--// > $(SLEIGHVERSION)/Makefile\n\tgrep ^-a- sleighexample.cc | sed -e s/-a-// > $(SLEIGHVERSION)/README\n\tsed -e s/page\\ sleigh\\ /mainpage\\ / < $(SLEIGHVERSION)/src/sleigh.hh > $(SLEIGHVERSION)/spam\n\tmv $(SLEIGHVERSION)/spam $(SLEIGHVERSION)/src/sleigh.hh\n\tcd $(SLEIGHVERSION)/src; doxygen Doxyfile\n\nlink_extensions:\n\trm -rf coreext_*.cc coreext_*.hh ghidraext_*.cc ghidraext_*.hh consoleext_*.cc consoleext_*.hh\n\tfor i in $(EXTERNAL_COREEXT_NAMES) $(EXTERNAL_GHIDRAEXT_NAMES) $(EXTERNAL_CONSOLEEXT_NAMES); do \\\n\t\tln -s $(EXTENSION_POINT)/$$i.cc $$i.cc; \\\n\t\tln -s $(EXTENSION_POINT)/$$i.hh $$i.hh; \\\n\tdone\n\nlink_extensions_hard:\n\trm -rf coreext_*.cc coreext_*.hh ghidraext_*.cc ghidraext_*.hh consoleext_*.cc consoleext_*.hh\n\tfor i in $(EXTERNAL_COREEXT_NAMES) $(EXTERNAL_GHIDRAEXT_NAMES) $(EXTERNAL_CONSOLEEXT_NAMES); do \\\n\t\tln $(EXTENSION_POINT)/$$i.cc $$i.cc; \\\n\t\tln $(EXTENSION_POINT)/$$i.hh $$i.hh; \\\n\tdone\n\ntags:\n\tetags *.c *.h *.cc *.hh\n\n# Rules to build the different dependency files\ncom_dbg/depend:\t$(COMMANDLINE_NAMES:%=%.cc)\n\tmkdir -p com_dbg \n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(COMMANDLINE_DEBUG) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,com_dbg/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\ncom_opt/depend:\t$(COMMANDLINE_NAMES:%=%.cc)\n\tmkdir -p com_opt\n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(COMMANDLINE_OPT) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,com_opt/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\ntest_dbg/depend:\t$(TEST_NAMES:%=%.cc) $(UNITTEST_NAMES:%=%.cc)\n\tmkdir -p test_dbg\n\t@set -e; rm -f $@; \\\n\t$(CXX) -I. -MM $(TEST_DEBUG) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,test_dbg/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\nghi_dbg/depend:\t$(GHIDRA_NAMES_DBG:%=%.cc)\n\tmkdir -p ghi_dbg\n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(GHIDRA_DEBUG) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,ghi_dbg/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\nghi_opt/depend:\t$(GHIDRA_NAMES:%=%.cc)\n\tmkdir -p ghi_opt \n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(GHIDRA_OPT) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,ghi_opt/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\nsla_dbg/depend:\t$(SLEIGH_NAMES:%=%.cc)\n\tmkdir -p sla_dbg\n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(SLEIGH_DEBUG) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,sla_dbg/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\nsla_opt/depend:\t$(SLEIGH_NAMES:%=%.cc)\n\tmkdir -p sla_opt\n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(SLEIGH_OPT) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,sla_opt/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\ncom_opt/depend.lib_sla:\t$(LIBSLA_NAMES:%=%.cc)\n\tmkdir -p com_opt\n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(COMMANDLINE_OPT) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,com_opt/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\ncom_dbg/depend.lib_sla:\t$(LIBSLA_NAMES:%=%.cc)\n\tmkdir -p com_dbg\n\t@set -e; rm -f $@; \\\n\t$(CXX) -MM $(COMMANDLINE_DEBUG) $^ > $@.$$$$; \\\n\tsed 's,\\(.*\\)\\.o[ :]*,com_dbg/\\1.o $@ : ,g' < $@.$$$$ > $@; \\\n\trm -f $@.$$$$\n\ninclude $(DEPNAMES)\n\ndoc:\n\tdoxygen Doxyfile\n\nclean:\n\trm -f com_dbg/*.o com_opt/*.o test_dbg/*.o ghi_dbg/*.o ghi_opt/*.o sla_dbg/*.o sla_opt/*.o\n\trm -f *.gcov com_dbg/*.gcno com_dbg/*.gcda\n\nresetgcov:\n\trm -f *.gcov com_dbg/*.gcda\n\nreallyclean:\tclean\t\n\trm -rf coreext_*.cc coreext_*.hh ghidraext_*.cc ghidraext_*.hh consoleext_*.cc consoleext_*.hh\n\trm -rf com_dbg com_opt test_dbg ghi_dbg ghi_opt sla_dbg sla_opt\n\trm -f $(EXECS) TAGS *~\n\nsleigh_src:\n\tmkdir -p sleigh_src\n\tcp $(LIBSLA_SOURCE) Makefile sleigh_src\n" }, { "path": "pypcode/sleigh/address.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"address.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nAttributeId ATTRIB_FIRST = AttributeId(\"first\",27);\nAttributeId ATTRIB_LAST = AttributeId(\"last\",28);\nAttributeId ATTRIB_UNIQ = AttributeId(\"uniq\",29);\n\nElementId ELEM_ADDR = ElementId(\"addr\",11);\nElementId ELEM_RANGE = ElementId(\"range\",12);\nElementId ELEM_RANGELIST = ElementId(\"rangelist\",13);\nElementId ELEM_REGISTER = ElementId(\"register\",14);\nElementId ELEM_SEQNUM = ElementId(\"seqnum\",15);\nElementId ELEM_VARNODE = ElementId(\"varnode\",16);\n\nostream &operator<<(ostream &s,const SeqNum &sq)\n\n{\n sq.pc.printRaw(s);\n s << ':' << sq.uniq;\n return s;\n}\n\n/// This allows an Address to be written to a stream using\n/// the standard '<<' operator. This is a wrapper for the\n/// printRaw method and is intended for debugging and console\n/// mode uses.\n/// \\param s is the stream being written to\n/// \\param addr is the Address to write\n/// \\return the output stream\nostream &operator<<(ostream &s,const Address &addr)\n\n{\n addr.printRaw(s);\n return s;\n}\n\nSeqNum::SeqNum(Address::mach_extreme ex) : pc(ex)\n\n{\n uniq = (ex == Address::m_minimal) ? 0 : ~((uintm)0);\n}\n\nvoid SeqNum::encode(Encoder &encoder) const\n\n{\n encoder.openElement(ELEM_SEQNUM);\n pc.getSpace()->encodeAttributes(encoder,pc.getOffset());\n encoder.writeUnsignedInteger(ATTRIB_UNIQ, uniq);\n encoder.closeElement(ELEM_SEQNUM);\n}\n\nSeqNum SeqNum::decode(Decoder &decoder)\n\n{\n uintm uniq = ~((uintm)0);\n uint4 elemId = decoder.openElement(ELEM_SEQNUM);\n Address pc = Address::decode(decoder); // Recover address\n for(;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == ATTRIB_UNIQ) {\n uniq = decoder.readUnsignedInteger();\n break;\n }\n }\n decoder.closeElement(elemId);\n return SeqNum(pc,uniq);\n}\n\n/// Some data structures sort on an Address, and it is convenient\n/// to be able to create an Address that is either bigger than\n/// or smaller than all other Addresses.\n/// \\param ex is either \\e m_minimal or \\e m_maximal\nAddress::Address(mach_extreme ex)\n\n{\n if (ex == m_minimal) {\n base = (AddrSpace *)0;\n offset = 0;\n }\n else {\n base = (AddrSpace *) ~((uintp)0);\n offset = ~((uintb)0);\n }\n}\n\n/// Return \\b true if the range starting at \\b this extending the given number of bytes\n/// is contained by the second given range.\n/// \\param sz is the given number of bytes in \\b this range\n/// \\param op2 is the start of the second given range\n/// \\param sz2 is the number of bytes in the second given range\n/// \\return \\b true if the second given range contains \\b this range\nbool Address::containedBy(int4 sz,const Address &op2,int4 sz2) const\n\n{\n if (base != op2.base) return false;\n if (op2.offset > offset) return false;\n uintb off1 = offset + (sz-1);\n uintb off2 = op2.offset + (sz2-1);\n return (off2 >= off1);\n}\n\n/// Return -1 if (\\e op2,\\e sz2) is not properly contained in (\\e this,\\e sz).\n/// If it is contained, return the endian aware offset of (\\e op2,\\e sz2) \n/// I.e. if the least significant byte of the \\e op2 range falls on the least significant\n/// byte of the \\e this range, return 0. If it intersects the second least significant, return 1, etc.\n/// The -forceleft- toggle causes the check to be made against the left (lowest address) side\n/// of the container, regardless of the endianness. I.e. it forces a little endian interpretation.\n/// \\param sz is the size of \\e this range\n/// \\param op2 is the address of the second range\n/// \\param sz2 is the size of the second range\n/// \\param forceleft is \\b true if containments is forced to be on the left even for big endian\n/// \\return the endian aware offset, or -1\nint4 Address::justifiedContain(int4 sz,const Address &op2,int4 sz2,bool forceleft) const\n\n{ if (base != op2.base) return -1;\n if (op2.offset < offset) return -1;\n uintb off1 = offset + (sz-1);\n uintb off2 = op2.offset + (sz2-1);\n if (off2 > off1) return -1;\n if (base->isBigEndian()&&(!forceleft)) {\n return (int4)(off1 - off2);\n }\n return (int4)(op2.offset - offset);\n}\n\n/// If \\e this + \\e skip falls in the range\n/// \\e op to \\e op + \\e size, then a non-negative integer is\n/// returned indicating where in the interval it falls. I.e.\n/// if \\e this + \\e skip == \\e op, then 0 is returned. Otherwise\n/// -1 is returned.\n/// \\param skip is an adjust to \\e this address\n/// \\param op is the start of the range to check\n/// \\param size is the size of the range\n/// \\return an integer indicating how overlap occurs\nint4 Address::overlap(int4 skip,const Address &op,int4 size) const\n\n{\n uintb dist;\n\n if (base != op.base) return -1; // Must be in same address space to overlap\n if (base->getType()==IPTR_CONSTANT) return -1; // Must not be constants\n\n dist = base->wrapOffset(offset+skip-op.offset);\n\n if (dist >= size) return -1; // but must fall before op+size\n return (int4) dist;\n}\n\n/// Does the location \\e this, \\e sz form a contiguous region to \\e loaddr, \\e losz,\n/// where \\e this forms the most significant piece of the logical whole\n/// \\param sz is the size of \\e this hi region\n/// \\param loaddr is the starting address of the low region\n/// \\param losz is the size of the low region\n/// \\return \\b true if the pieces form a contiguous whole\nbool Address::isContiguous(int4 sz,const Address &loaddr,int4 losz) const\n\n{\n if (base != loaddr.base) return false;\n if (base->isBigEndian()) {\n uintb nextoff = base->wrapOffset(offset+sz);\n if (nextoff == loaddr.offset) return true;\n }\n else {\n uintb nextoff = base->wrapOffset(loaddr.offset+losz);\n if (nextoff == offset) return true;\n }\n return false;\n}\n\n/// If \\b this is (originally) a \\e join address, reevaluate it in terms of its new\n/// \\e offset and \\e size, changing the space and offset if necessary.\n/// \\param size is the new size in bytes of the underlying object\nvoid Address::renormalize(int4 size) {\n if (base->getType() == IPTR_JOIN)\n base->getManager()->renormalizeJoinAddress(*this,size);\n}\n\n/// This is usually used to decode an address from an \\b \\\n/// element, but any element can be used if it has the appropriate attributes\n/// - \\e space indicates the address space of the tag\n/// - \\e offset indicates the offset within the space\n///\n/// or a \\e name attribute can be used to recover an address\n/// based on a register name.\n/// \\param decoder is the stream decoder\n/// \\return the resulting Address\nAddress Address::decode(Decoder &decoder)\n\n{\n VarnodeData var;\n\n var.decode(decoder);\n return Address(var.space,var.offset);\n}\n\n/// This is usually used to decode an address from an \\b \\\n/// element, but any element can be used if it has the appropriate attributes\n/// - \\e space indicates the address space of the tag\n/// - \\e offset indicates the offset within the space\n/// - \\e size indicates the size of an address range\n///\n/// or a \\e name attribute can be used to recover an address\n/// and size based on a register name. If a size is recovered\n/// it is stored in \\e size reference.\n/// \\param decoder is the stream decoder\n/// \\param size is the reference to any recovered size\n/// \\return the resulting Address\nAddress Address::decode(Decoder &decoder,int4 &size)\n\n{\n VarnodeData var;\n\n var.decode(decoder);\n size = var.size;\n return Address(var.space,var.offset);\n}\n\nRange::Range(const RangeProperties &properties,const AddrSpaceManager *manage)\n\n{\n if (properties.isRegister) {\n const Translate *trans = manage->getDefaultCodeSpace()->getTrans();\n const VarnodeData &point(trans->getRegister(properties.spaceName));\n spc = point.space;\n first = point.offset;\n last = (first-1) + point.size;\n return;\n }\n spc = manage->getSpaceByName(properties.spaceName);\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"Undefined space: \"+properties.spaceName);\n\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"No address space indicated in range tag\");\n first = properties.first;\n last = properties.last;\n if (!properties.seenLast) {\n last = spc->getHighest();\n }\n if (first > spc->getHighest() || last > spc->getHighest() || last < first)\n throw LowlevelError(\"Illegal range tag\");\n}\n\n/// Get the last address +1, updating the space, or returning\n/// the extremal address if necessary\n/// \\param manage is used to fetch the next address space\nAddress Range::getLastAddrOpen(const AddrSpaceManager *manage) const\n\n{\n AddrSpace *curspc = spc;\n uintb curlast = last;\n if (curlast == curspc->getHighest()) {\n curspc = manage->getNextSpaceInOrder(curspc);\n curlast = 0;\n }\n else\n curlast += 1;\n if (curspc == (AddrSpace *)0)\n return Address(Address::m_maximal);\n return Address(curspc,curlast);\n}\n\n/// Output a description of this Range like: ram: 7f-9c\n/// \\param s is the output stream\nvoid Range::printBounds(ostream &s) const\n\n{\n s << spc->getName() << \": \";\n s << hex << first << '-' << last;\n}\n\n/// Encode \\b this to a stream as a \\ element.\n/// \\param encoder is the stream encoder\nvoid Range::encode(Encoder &encoder) const\n\n{\n encoder.openElement(ELEM_RANGE);\n encoder.writeSpace(ATTRIB_SPACE, spc);\n encoder.writeUnsignedInteger(ATTRIB_FIRST, first);\n encoder.writeUnsignedInteger(ATTRIB_LAST, last);\n encoder.closeElement(ELEM_RANGE);\n}\n\n/// Reconstruct this object from a \\ or \\ element\n/// \\param decoder is the stream decoder\nvoid Range::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement();\n if (elemId != ELEM_RANGE && elemId != ELEM_REGISTER)\n throw DecoderError(\"Expecting or element\");\n decodeFromAttributes(decoder);\n decoder.closeElement(elemId);\n}\n\n/// Reconstruct from attributes that may not be part of a \\ element.\n/// \\param decoder is the stream decoder\nvoid Range::decodeFromAttributes(Decoder &decoder)\n\n{\n spc = (AddrSpace *)0;\n bool seenLast = false;\n first = 0;\n last = 0;\n for(;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == ATTRIB_SPACE) {\n spc = decoder.readSpace();\n }\n else if (attribId == ATTRIB_FIRST) {\n first = decoder.readUnsignedInteger();\n }\n else if (attribId == ATTRIB_LAST) {\n last = decoder.readUnsignedInteger();\n seenLast = true;\n }\n else if (attribId == ATTRIB_NAME) {\n const Translate *trans = decoder.getAddrSpaceManager()->getDefaultCodeSpace()->getTrans();\n const VarnodeData &point(trans->getRegister(decoder.readString()));\n spc = point.space;\n first = point.offset;\n last = (first-1) + point.size;\n return;\t\t// There should be no (space,first,last) attributes\n }\n }\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"No address space indicated in range tag\");\n if (!seenLast) {\n last = spc->getHighest();\n }\n if (first > spc->getHighest() || last > spc->getHighest() || last < first)\n throw LowlevelError(\"Illegal range tag\");\n}\n\nvoid RangeProperties::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement();\n if (elemId != ELEM_RANGE && elemId != ELEM_REGISTER)\n throw DecoderError(\"Expecting or element\");\n for(;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == ATTRIB_SPACE)\n spaceName = decoder.readString();\n else if (attribId == ATTRIB_FIRST)\n first = decoder.readUnsignedInteger();\n else if (attribId == ATTRIB_LAST) {\n last = decoder.readUnsignedInteger();\n seenLast = true;\n }\n else if (attribId == ATTRIB_NAME) {\n spaceName = decoder.readString();\n isRegister = true;\n }\n }\n decoder.closeElement(elemId);\n}\n\n/// Insert a new Range merging as appropriate to maintain the disjoint cover\n/// \\param spc is the address space containing the new range\n/// \\param first is the offset of the first byte in the new range\n/// \\param last is the offset of the last byte in the new range\nvoid RangeList::insertRange(AddrSpace *spc,uintb first,uintb last)\n\n{\n set::iterator iter1,iter2;\n\n // we must have iter1.first > first\n iter1 = tree.upper_bound(Range(spc,first,first));\n\n // Set iter1 to first range with range.last >=first\n // It is either current iter1 or the one before\n if (iter1 != tree.begin()) {\n --iter1;\n if (((*iter1).spc!=spc)||((*iter1).last < first))\n ++iter1;\n }\n\n // Set iter2 to first range with range.first > last\n iter2 = tree.upper_bound(Range(spc,last,last));\n \n while(iter1!=iter2) {\n if ((*iter1).first < first)\n first = (*iter1).first;\n if ((*iter1).last > last)\n last = (*iter1).last;\n tree.erase(iter1++);\n }\n tree.insert(Range(spc,first,last));\n}\n\n/// Remove/narrow/split existing Range objects to eliminate the indicated addresses\n/// while still maintaining a disjoint cover.\n/// \\param spc is the address space of the address range to remove\n/// \\param first is the offset of the first byte of the range\n/// \\param last is the offset of the last byte of the range\nvoid RangeList::removeRange(AddrSpace *spc,uintb first,uintb last)\n\n{\t\t\t\t// remove a range\n set::iterator iter1,iter2;\n\n if (tree.empty()) return;\t// Nothing to do\n\n // we must have iter1.first > first\n iter1 = tree.upper_bound(Range(spc,first,first));\n\n // Set iter1 to first range with range.last >=first\n // It is either current iter1 or the one before\n if (iter1 != tree.begin()) {\n --iter1;\n if (((*iter1).spc!=spc)||((*iter1).last < first))\n ++iter1;\n }\n\n // Set iter2 to first range with range.first > last\n iter2 = tree.upper_bound(Range(spc,last,last));\n \n while(iter1!=iter2) {\n uintb a,b;\n\n a = (*iter1).first;\n b = (*iter1).last;\n tree.erase(iter1++);\n if (a last)\n tree.insert(Range(spc,last+1,b));\n }\n}\n\nvoid RangeList::merge(const RangeList &op2)\n\n{ // Merge -op2- into this rangelist\n set::const_iterator iter1,iter2;\n iter1 = op2.tree.begin();\n iter2 = op2.tree.end();\n while(iter1 != iter2) {\n const Range &range( *iter1 );\n ++iter1;\n insertRange(range.spc, range.first, range.last);\n }\n}\n\n/// Make sure indicated range of addresses is \\e contained in \\b this RangeList\n/// \\param addr is the first Address in the target range\n/// \\param size is the number of bytes in the target range\n/// \\return \\b true is the range is fully contained by this RangeList\nbool RangeList::inRange(const Address &addr,int4 size) const\n\n{\n set::const_iterator iter;\n\n if (addr.isInvalid()) return true; // We don't really care\n if (tree.empty()) return false;\n\n // iter = first range with its first > addr\n iter = tree.upper_bound(Range(addr.getSpace(),addr.getOffset(),addr.getOffset()));\n if (iter == tree.begin()) return false;\n // Set iter to last range with range.first <= addr\n --iter;\n // if (iter == tree.end()) // iter can't be end if non-empty\n // return false;\n if ((*iter).spc != addr.getSpace()) return false;\n if ((*iter).last >= addr.getOffset()+size-1)\n return true;\n return false;\n}\n\n/// If \\b this RangeList contains the specific address (spaceid,offset), return it\n/// \\return the containing Range or NULL\nconst Range *RangeList::getRange(AddrSpace *spaceid,uintb offset) const\n\n{\n if (tree.empty()) return (const Range *)0;\n\n // iter = first range with its first > offset\n set::const_iterator iter = tree.upper_bound(Range(spaceid,offset,offset));\n if (iter == tree.begin()) return (const Range *)0;\n // Set iter to last range with range.first <= offset\n --iter;\n if ((*iter).spc != spaceid) return (const Range *)0;\n if ((*iter).last >= offset)\n return &(*iter);\n return (const Range *)0;\n}\n\n/// Return the size of the biggest contiguous sequence of addresses in\n/// \\b this RangeList which contain the given address\n/// \\param addr is the given address\n/// \\param maxsize is the large range to consider before giving up\n/// \\return the size (in bytes) of the biggest range\nuintb RangeList::longestFit(const Address &addr,uintb maxsize) const\n\n{\n set::const_iterator iter;\n\n if (addr.isInvalid()) return 0;\n if (tree.empty()) return 0;\n\n // iter = first range with its first > addr\n uintb offset = addr.getOffset();\n iter = tree.upper_bound(Range(addr.getSpace(),offset,offset));\n if (iter == tree.begin()) return 0;\n // Set iter to last range with range.first <= addr\n --iter;\n uintb sizeres = 0;\n if ((*iter).last < offset) return sizeres;\n do {\n if ((*iter).spc != addr.getSpace()) break;\n if ((*iter).first > offset) break;\n sizeres += ((*iter).last + 1 - offset); // Size extends to end of range\n offset = (*iter).last + 1;\t// Try to chain on the next range\n if (sizeres >= maxsize) break; // Don't bother if past maxsize\n ++iter;\t\t\t// Next range in the chain\n } while(iter != tree.end());\n return sizeres;\n}\n\n/// \\return the first contiguous range of addresses or NULL if empty\nconst Range *RangeList::getFirstRange(void) const\n\n{\n if (tree.empty()) return (const Range *)0;\n return &(*tree.begin());\n}\n\n/// \\return the last contiguous range of addresses or NULL if empty\nconst Range *RangeList::getLastRange(void) const\n\n{\n if (tree.empty()) return (const Range *)0;\n set::const_iterator iter = tree.end();\n --iter;\n return &(*iter);\n}\n\n/// Treating offsets with their high-bits set as coming \\e before\n/// offset where the high-bit is clear, return the last/latest contiguous\n/// Range within the given address space\n/// \\param spaceid is the given address space\n/// \\return indicated Range or NULL if empty\nconst Range *RangeList::getLastSignedRange(AddrSpace *spaceid) const\n\n{\n uintb midway = spaceid->getHighest() / 2;\t\t// Maximal signed value\n Range range(spaceid,midway,midway);\n set::const_iterator iter = tree.upper_bound(range);\t// First element greater than -range- (should be MOST negative)\n\n if (iter!=tree.begin()) {\n --iter;\n if ((*iter).getSpace() == spaceid)\n return &(*iter);\n }\n\n // If there were no \"positive\" ranges, search for biggest negative range\n range = Range(spaceid,spaceid->getHighest(),spaceid->getHighest());\n iter = tree.upper_bound(range);\n if (iter != tree.begin()) {\n --iter;\n if ((*iter).getSpace() == spaceid)\n return &(*iter);\n }\n return (const Range *)0;\n}\n\n/// Print a one line description of each disjoint Range making up \\b this RangeList\n/// \\param s is the output stream\nvoid RangeList::printBounds(ostream &s) const\n\n{\n if (tree.empty())\n s << \"all\" << endl;\n else {\n set::const_iterator iter;\n for(iter=tree.begin();iter!=tree.end();++iter) {\n (*iter).printBounds(s);\n s << endl;\n }\n }\n}\n\n/// Encode \\b this as a \\ element\n/// \\param encoder is the stream encoder\nvoid RangeList::encode(Encoder &encoder) const\n\n{\n set::const_iterator iter;\n\n encoder.openElement(ELEM_RANGELIST);\n for(iter=tree.begin();iter!=tree.end();++iter) {\n (*iter).encode(encoder);\n }\n encoder.closeElement(ELEM_RANGELIST);\n}\n\n/// Recover each individual disjoint Range for \\b this RangeList.\n/// \\param decoder is the stream decoder\nvoid RangeList::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_RANGELIST);\n while(decoder.peekElement() != 0) {\n Range range;\n range.decode(decoder);\n tree.insert(range);\n }\n decoder.closeElement(elemId);\n}\n\n#ifdef UINTB4\nuintb uintbmasks[9] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };\n#else\nuintb uintbmasks[9] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff, 0xffffffffffLL,\n\t\t\t0xffffffffffffLL, 0xffffffffffffffLL, 0xffffffffffffffffLL };\n#endif\n\n/// Treat the given \\b val as a constant of \\b size bytes\n/// \\param val is the given value\n/// \\param size is the size in bytes\n/// \\return \\b true if the constant (as sized) has its sign bit set\nbool signbit_negative(uintb val,int4 size)\n\n{\t\t\t\t// Return true if signbit is set (negative)\n uintb mask = 0x80;\n mask <<= 8*(size-1);\n return ((val&mask) != 0);\n}\n\n/// Treat the given \\b in as a constant of \\b size bytes.\n/// Negate this constant keeping the upper bytes zero.\n/// \\param in is the given value\n/// \\param size is the size in bytes\n/// \\return the negation of the sized constant\nuintb uintb_negate(uintb in,int4 size)\n\n{\t\t\t\t// Invert bits\n return ((~in)&calc_mask(size));\n}\n\n/// Take the first \\b sizein bytes of the given \\b in and sign-extend\n/// this to \\b sizeout bytes, keeping any more significant bytes zero\n/// \\param in is the given value\n/// \\param sizein is the size to treat that value as an input\n/// \\param sizeout is the size to sign-extend the value to\n/// \\return the sign-extended value\nuintb sign_extend(uintb in,int4 sizein,int4 sizeout)\n\n{\n sizein = (sizein < sizeof(uintb)) ? sizein : sizeof(uintb);\n sizeout = (sizeout < sizeof(uintb)) ? sizeout : sizeof(uintb);\n intb sval = in;\n sval <<= (sizeof(intb) - sizein) * 8;\n uintb res = (uintb)(sval >> (sizeout - sizein) * 8);\n res >>= (sizeof(uintb) - sizeout)*8;\n return res;\n}\n\n/// Swap the least significant \\b size bytes in \\b val\n/// \\param val is a reference to the value to swap\n/// \\param size is the number of bytes to swap\nvoid byte_swap(intb &val,int4 size)\n\n{\n intb res = 0;\n while(size>0) {\n res <<= 8;\n res |= (val&0xff);\n val >>= 8;\n size -= 1;\n }\n val = res;\n}\n\n/// Swap the least significant \\b size bytes in \\b val\n/// \\param val is the value to swap\n/// \\param size is the number of bytes to swap\n/// \\return the swapped value\nuintb byte_swap(uintb val,int4 size)\n\n{\n uintb res=0;\n while(size>0) {\n res <<= 8;\n res |= (val&0xff);\n val >>= 8;\n size -= 1;\n }\n return res;\n}\n\n/// The least significant bit is index 0.\n/// \\param val is the given value\n/// \\return the index of the least significant set bit, or -1 if none are set\nint4 leastsigbit_set(uintb val)\n\n{\n if (val==0) return -1;\n int4 res = 0;\n int4 sz = 4*sizeof(uintb);\n uintb mask = ~((uintb)0);\n do {\n mask >>= sz;\n if ((mask&val)==0) {\n res += sz;\n val >>= sz;\n }\n sz >>= 1;\n } while(sz!=0);\n return res;\n}\n\n/// The least significant bit is index 0.\n/// \\param val is the given value\n/// \\return the index of the most significant set bit, or -1 if none are set\nint4 mostsigbit_set(uintb val)\n\n{\n if (val==0) return -1;\n int4 res = 8*sizeof(uintb)-1;\n int4 sz = 4*sizeof(uintb);\n uintb mask = ~((uintb)0);\n do {\n mask <<= sz;\n if ((mask&val)==0) {\n res -= sz;\n val <<= sz;\n }\n sz >>= 1;\n } while(sz != 0);\n return res;\n}\n\n/// Count the number (population) bits set.\n/// \\param val is the given value\n/// \\return the number of one bits\nint4 popcount(uintb val)\n\n{\n val = (val & 0x5555555555555555L) + ((val >> 1) & 0x5555555555555555L);\n val = (val & 0x3333333333333333L) + ((val >> 2) & 0x3333333333333333L);\n val = (val & 0x0f0f0f0f0f0f0f0fL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fL);\n val = (val & 0x00ff00ff00ff00ffL) + ((val >> 8) & 0x00ff00ff00ff00ffL);\n val = (val & 0x0000ffff0000ffffL) + ((val >> 16) & 0x0000ffff0000ffffL);\n int4 res = (int4)(val & 0xff);\n res += (int4)((val >> 32) & 0xff);\n return res;\n}\n\n/// Count the number of more significant zero bits before the most significant\n/// one bit in the representation of the given value;\n/// \\param val is the given value\n/// \\return the number of zero bits\nint4 count_leading_zeros(uintb val)\n\n{\n if (val == 0)\n return 8*sizeof(uintb);\n uintb mask = ~((uintb)0);\n int4 maskSize = 4*sizeof(uintb);\n mask &= (mask << maskSize);\n int4 bit = 0;\n\n do {\n if ((mask & val)==0) {\n bit += maskSize;\n maskSize >>= 1;\n mask |= (mask >> maskSize);\n }\n else {\n maskSize >>= 1;\n mask &= (mask << maskSize);\n }\n } while(maskSize != 0);\n return bit;\n}\n\n/// Return smallest number of form 2^n-1, bigger or equal to the given value\n/// \\param val is the given value\n/// \\return the mask\nuintb coveringmask(uintb val)\n\n{\n uintb res = val;\n int4 sz = 1;\n while(sz < 8*sizeof(uintb)) {\n res = res | (res>>sz);\n sz <<= 1;\n }\n return res;\n}\n\n/// Treat \\b val as a constant of size \\b sz.\n/// Scanning across the bits of \\b val return the number of transitions (from 0->1 or 1->0)\n/// If there are 2 or less transitions, this is an indication of a bit flag or a mask\n/// \\param val is the given value\n/// \\param sz is the size to treat the value as\n/// \\return the number of transitions\nint4 bit_transitions(uintb val,int4 sz)\n\n{\n int4 res = 0;\n int4 last = val & 1;\n int4 cur;\n for(int4 i=1;i<8*sz;++i) {\n val >>= 1;\n cur = val & 1;\n if (cur != last) {\n res += 1;\n last = cur;\n }\n if (val==0) break;\n }\n return res;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/address.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file address.hh\n/// \\brief Classes for specifying addresses and other low-level constants\n///\n/// All addresses are absolute and there are no registers in CPUI. However,\n/// all addresses are prefixed with an \"immutable\" pointer, which can\n/// specify a separate RAM space, a register space, an i/o space etc. Thus\n/// a translation from a real machine language will typically simulate registers\n/// by placing them in their own space, separate from RAM. Indirection\n/// (i.e. pointers) must be simulated through the LOAD and STORE ops.\n\n#ifndef __ADDRESS_HH__\n#define __ADDRESS_HH__\n\n#include \"space.hh\"\n\nnamespace ghidra {\n\nclass AddrSpaceManager;\n\nextern AttributeId ATTRIB_FIRST;\t///< Marshaling attribute \"first\"\nextern AttributeId ATTRIB_LAST;\t\t///< Marshaling attribute \"last\"\nextern AttributeId ATTRIB_UNIQ;\t\t///< Marshaling attribute \"uniq\"\n\nextern ElementId ELEM_ADDR;\t\t///< Marshaling element \\\nextern ElementId ELEM_RANGE;\t\t///< Marshaling element \\\nextern ElementId ELEM_RANGELIST;\t///< Marshaling element \\\nextern ElementId ELEM_REGISTER;\t\t///< Marshaling element \\\nextern ElementId ELEM_SEQNUM;\t\t///< Marshaling element \\\nextern ElementId ELEM_VARNODE;\t\t///< Marshaling element \\\n\n/// \\brief A low-level machine address for labelling bytes and data.\n///\n/// All data that can be manipulated within the processor reverse\n/// engineering model can be labelled with an Address. It is\n/// simply an address space (AddrSpace) and an offset within that\n/// space. Note that processor registers are typically modelled\n/// by creating a dedicated address space for them, as distinct\n/// from RAM say, and then specifying certain addresses within the\n/// register space that correspond to particular registers. However,\n/// an arbitrary address could refer to anything,\n/// RAM, ROM, cpu register, data segment, coprocessor, stack,\n/// nvram, etc.\n/// An Address represents an offset \\e only, not an offset and length\nclass Address {\nprotected:\n AddrSpace *base;\t\t///< Pointer to our address space\n uintb offset;\t\t\t///< Offset (in bytes)\npublic:\n /// An enum for specifying extremal addresses\n enum mach_extreme {\n m_minimal,\t\t\t///< Smallest possible address\n m_maximal\t\t\t///< Biggest possible address\n };\n Address(mach_extreme ex);\t///< Initialize an extremal address\n Address(void);\t\t///< Create an invalid address\n Address(AddrSpace *id,uintb off); ///< Construct an address with a space/offset pair\n Address(const Address &op2);\t///< A copy constructor\n\n bool isInvalid(void) const; ///< Is the address invalid?\n int4 getAddrSize(void) const; ///< Get the number of bytes in the address\n bool isBigEndian(void) const;\t///< Is data at this address big endian encoded\n void printRaw(ostream &s) const; ///< Write a raw version of the address to a stream\n int4 read(const string &s); ///< Read in the address from a string\n AddrSpace *getSpace(void) const; ///< Get the address space\n uintb getOffset(void) const; ///< Get the address offset\n char getShortcut(void) const;\t///< Get the shortcut character for the address space\n Address &operator=(const Address &op2); ///< Copy an address\n bool operator==(const Address &op2) const; ///< Compare two addresses for equality\n bool operator!=(const Address &op2) const; ///< Compare two addresses for inequality\n bool operator<(const Address &op2) const; ///< Compare two addresses via their natural ordering\n bool operator<=(const Address &op2) const; ///< Compare two addresses via their natural ordering\n Address operator+(int8 off) const; ///< Increment address by a number of bytes\n Address operator-(int8 off) const; ///< Decrement address by a number of bytes\n friend ostream &operator<<(ostream &s,const Address &addr); ///< Write out an address to stream\n bool containedBy(int4 sz,const Address &op2,int4 sz2) const;\t///< Determine if \\e op2 range contains \\b this range\n int4 justifiedContain(int4 sz,const Address &op2,int4 sz2,bool forceleft) const; ///< Determine if \\e op2 is the least significant part of \\e this.\n int4 overlap(int4 skip,const Address &op,int4 size) const; ///< Determine how \\b this address falls in a given address range\n int4 overlapJoin(int4 skip,const Address &op,int4 size) const;\t///< Determine how \\b this falls in a possible \\e join space address range\n bool isContiguous(int4 sz,const Address &loaddr,int4 losz) const; ///< Does \\e this form a contiguous range with \\e loaddr\n bool isConstant(void) const; ///< Is this a \\e constant \\e value\n void renormalize(int4 size);\t///< Make sure there is a backing JoinRecord if \\b this is in the \\e join space\n bool isJoin(void) const;\t///< Is this a \\e join \\e value\n void encode(Encoder &encoder) const; ///< Encode \\b this to a stream\n void encode(Encoder &encoder,int4 size) const; ///< Encode \\b this and a size to a stream\n\n /// Decode an address from a stream\n static Address decode(Decoder &decoder);\n\n /// Decode an address and size from a stream\n static Address decode(Decoder &decoder,int4 &size);\n};\n\n/// \\brief A class for uniquely labelling and comparing PcodeOps\n///\n/// Different PcodeOps generated by a single machine instruction\n/// can only be labelled with a single Address. But PcodeOps\n/// must be distinguishable and compared for execution order.\n/// A SeqNum extends the address for a PcodeOp to include:\n/// - A fixed \\e time field, which is set at the time the PcodeOp\n/// is created. The \\e time field guarantees a unique SeqNum\n/// for the life of the PcodeOp. \n/// - An \\e order field, which is guaranteed to be comparable\n/// for the execution order of the PcodeOp within its basic\n/// block. The \\e order field also provides uniqueness but\n/// may change over time if the syntax tree is manipulated.\nclass SeqNum {\n Address pc;\t\t ///< Program counter at start of instruction\n uintm uniq;\t\t ///< Number to guarantee uniqueness\n uintm order;\t\t ///< Number for order comparisons within a block\npublic:\n SeqNum(void) {}\t ///< Create an invalid sequence number\n SeqNum(Address::mach_extreme ex); ///< Create an extremal sequence number\n\n /// Create a sequence number with a specific \\e time field\n SeqNum(const Address &a,uintm b) : pc(a) { uniq = b; }\n\n /// Copy a sequence number\n SeqNum(const SeqNum &op2) : pc(op2.pc) { uniq = op2.uniq; }\n\n /// Get the address portion of a sequence number\n const Address &getAddr(void) const { return pc; }\n\n /// Get the \\e time field of a sequence number\n uintm getTime(void) const { return uniq; }\n \n /// Get the \\e order field of a sequence number\n uintm getOrder(void) const { return order; }\n\n /// Set the \\e order field of a sequence number\n void setOrder(uintm ord) { order = ord; }\n\n /// Compare two sequence numbers for equality\n bool operator==(const SeqNum &op2) const { return (uniq == op2.uniq); }\n\n /// Compare two sequence numbers for inequality\n bool operator!=(const SeqNum &op2) const { return (uniq != op2.uniq); }\n\n /// Compare two sequence numbers with their natural order\n bool operator<(const SeqNum &op2) const {\n if (pc == op2.pc)\n return (uniq < op2.uniq);\n return (pc < op2.pc);\n }\n\n /// Encode a SeqNum to a stream\n void encode(Encoder &encoder) const;\n\n /// Decode a SeqNum from a stream\n static SeqNum decode(Decoder &decoder);\n\n /// Write out a SeqNum in human readable form to a stream\n friend ostream &operator<<(ostream &s,const SeqNum &sq);\n};\n\nclass RangeProperties;\n\n/// \\brief A contiguous range of bytes in some address space\nclass Range {\n friend class RangeList;\n AddrSpace *spc;\t\t///< Space containing range\n uintb first;\t\t\t///< Offset of first byte in \\b this Range\n uintb last;\t\t\t///< Offset of last byte in \\b this Range\npublic:\n /// \\brief Construct a Range from offsets\n ///\n /// Offsets must expressed in \\e bytes as opposed to addressable \\e words\n /// \\param s is the address space containing the range\n /// \\param f is the offset of the first byte in the range\n /// \\param l is the offset of the last byte in the range\n Range(AddrSpace *s,uintb f,uintb l) {\n spc = s; first = f; last = l; }\n Range(void) {}\t\t\t\t\t///< Constructor for use with decode\n Range(const RangeProperties &properties,const AddrSpaceManager *manage);\t///< Construct range out of basic properties\n AddrSpace *getSpace(void) const { return spc; }\t///< Get the address space containing \\b this Range\n uintb getFirst(void) const { return first; }\t\t///< Get the offset of the first byte in \\b this Range\n uintb getLast(void) const { return last; }\t\t///< Get the offset of the last byte in \\b this Range\n Address getFirstAddr(void) const { return Address(spc,first); }\t///< Get the address of the first byte\n Address getLastAddr(void) const { return Address(spc,last); }\t\t///< Get the address of the last byte\n Address getLastAddrOpen(const AddrSpaceManager *manage) const;\t///< Get address of first byte after \\b this\n bool contains(const Address &addr) const;\t\t///< Determine if the address is in \\b this Range\n\n /// \\brief Sorting operator for Ranges\n ///\n /// Compare based on address space, then the starting offset\n /// \\param op2 is the Range to compare with \\b this\n /// \\return \\b true if \\b this comes before op2\n bool operator<(const Range &op2) const {\n if (spc->getIndex() != op2.spc->getIndex())\n return (spc->getIndex() < op2.spc->getIndex());\n return (first < op2.first); }\n void printBounds(ostream &s) const;\t\t\t///< Print \\b this Range to a stream\n void encode(Encoder &encoder) const;\t\t\t///< Encode \\b this Range to a stream\n void decode(Decoder &decoder);\t\t\t///< Restore \\b this from a stream\n void decodeFromAttributes(Decoder &decoder);\t\t///< Read \\b from attributes on another tag\n};\n\n/// \\brief A partially parsed description of a Range\n///\n/// Class that allows \\ tags to be parsed, when the address space doesn't yet exist\nclass RangeProperties {\n friend class Range;\n string spaceName;\t\t///< Name of the address space containing the range\n uintb first;\t\t\t///< Offset of first byte in the Range\n uintb last;\t\t\t///< Offset of last byte in the Range\n bool isRegister;\t\t///< Range is specified a register name\n bool seenLast;\t\t///< End of the range is actively specified\npublic:\n RangeProperties(void) { first = 0; last = 0; isRegister = false; seenLast = false; }\n void decode(Decoder &decoder);\t///< Decode \\b this from a stream\n};\n\n/// \\brief A disjoint set of Ranges, possibly across multiple address spaces\n///\n/// This is a container for addresses. It maintains a disjoint list of Ranges\n/// that cover all the addresses in the container. Ranges can be inserted\n/// and removed, but overlapping/adjacent ranges will get merged.\nclass RangeList {\n set tree;\t\t\t///< The sorted list of Range objects\npublic:\n RangeList(const RangeList &op2) { tree = op2.tree; }\t\t///< Copy constructor\n RangeList(void) {}\t\t\t\t\t\t///< Construct an empty container\n void clear(void) { tree.clear(); }\t\t\t\t///< Clear \\b this container to empty\n bool empty(void) const { return tree.empty(); }\t\t///< Return \\b true if \\b this is empty\n set::const_iterator begin(void) const { return tree.begin(); }\t///< Get iterator to beginning Range\n set::const_iterator end(void) const { return tree.end(); }\t///< Get iterator to ending Range\n int4 numRanges(void) const { return tree.size(); }\t\t///< Return the number of Range objects in container\n const Range *getFirstRange(void) const;\t\t\t///< Get the first Range\n const Range *getLastRange(void) const;\t\t\t///< Get the last Range\n const Range *getLastSignedRange(AddrSpace *spaceid) const;\t///< Get the last Range viewing offsets as signed\n const Range *getRange(AddrSpace *spaceid,uintb offset) const;\t///< Get Range containing the given byte\n void insertRange(AddrSpace *spc,uintb first,uintb last);\t///< Insert a range of addresses\n void removeRange(AddrSpace *spc,uintb first,uintb last);\t///< Remove a range of addresses\n void merge(const RangeList &op2);\t\t\t\t///< Merge another RangeList into \\b this\n bool inRange(const Address &addr,int4 size) const;\t\t///< Check containment an address range\n uintb longestFit(const Address &addr,uintb maxsize) const;\t///< Find size of biggest Range containing given address\n void printBounds(ostream &s) const;\t\t\t\t///< Print a description of \\b this RangeList to stream\n void encode(Encoder &encoder) const;\t\t\t\t///< Encode \\b this RangeList to a stream\n void decode(Decoder &decoder);\t\t\t\t///< Decode \\b this RangeList from a \\ element\n};\n\n/// Precalculated masks indexed by size\nextern uintb uintbmasks[];\n\n// Inline functions\n\n/// An invalid address is possible in some circumstances.\n/// This deliberately constructs an invalid address\ninline Address::Address(void) {\n base = (AddrSpace *)0;\n}\n\n/// This is the basic Address constructor\n/// \\param id is the space containing the address\n/// \\param off is the offset of the address\ninline Address::Address(AddrSpace *id,uintb off) {\n base=id; offset=off;\n}\n\n/// This is a standard copy constructor, copying the\n/// address space and the offset\n/// \\param op2 is the Address to copy\ninline Address::Address(const Address &op2) {\n base = op2.base;\n offset = op2.offset;\n}\n\n/// Determine if this is an invalid address. This only\n/// detects \\e deliberate invalid addresses.\n/// \\return \\b true if the address is invalid\ninline bool Address::isInvalid(void) const {\n return (base == (AddrSpace *)0);\n}\n\n/// Get the number of bytes needed to encode the \\e offset\n/// for this address.\n/// \\return the number of bytes in the encoding\ninline int4 Address::getAddrSize(void) const {\n return base->getAddrSize();\n}\n\n/// Determine if data stored at this address is big endian encoded.\n/// \\return \\b true if the address is big endian\ninline bool Address::isBigEndian(void) const {\n return base->isBigEndian();\n}\n\n/// Write a short-hand or debug version of this address to a\n/// stream.\n/// \\param s is the stream being written\ninline void Address::printRaw(ostream &s) const {\n if (base == (AddrSpace *)0) {\n s << \"invalid_addr\";\n return;\n }\n base->printRaw(s,offset);\n}\n\n/// Convert a string into an address. The string format can be\n/// tailored for the particular address space.\n/// \\param s is the string to parse\n/// \\return any size associated with the parsed string\ninline int4 Address::read(const string &s) {\n int4 sz; offset=base->read(s,sz); return sz;\n}\n\n/// Get the address space associated with this address.\n/// \\return the AddressSpace pointer, or \\b NULL if invalid\ninline AddrSpace *Address::getSpace(void) const {\n return base;\n}\n\n/// Get the offset of the address as an integer.\n/// \\return the offset integer\ninline uintb Address::getOffset(void) const {\n return offset;\n}\n\n/// Each address has a shortcut character associated with it\n/// for use with the read and printRaw methods.\n/// \\return the shortcut char\ninline char Address::getShortcut(void) const {\n return base->getShortcut();\n}\n\n/// This is a standard assignment operator, copying the\n/// address space pointer and the offset\n/// \\param op2 is the Address being assigned\n/// \\return a reference to altered address\ninline Address &Address::operator=(const Address &op2)\n\n{\n base = op2.base;\n offset = op2.offset;\n return *this;\n}\n\n/// Check if two addresses are equal. I.e. if their address\n/// space and offset are the same.\n/// \\param op2 is the address to compare to \\e this\n/// \\return \\b true if the addresses are the same\ninline bool Address::operator==(const Address &op2) const { \n return ((base==op2.base)&&(offset==op2.offset));\n}\n\n/// Check if two addresses are not equal. I.e. if either their\n/// address space or offset are different.\n/// \\param op2 is the address to compare to \\e this\n/// \\return \\b true if the addresses are different\ninline bool Address::operator!=(const Address &op2) const {\n return !(*this==op2);\n}\n\n/// Do an ordering comparison of two addresses. Addresses are\n/// sorted first on space, then on offset. So two addresses in\n/// the same space compare naturally based on their offset, but\n/// addresses in different spaces also compare. Different spaces\n/// are ordered by their index.\n/// \\param op2 is the address to compare to\n/// \\return \\b true if \\e this comes before \\e op2\ninline bool Address::operator<(const Address &op2) const {\n if (base != op2.base) {\n if (base == (AddrSpace *)0) {\n return true;\n }\n else if (base == (AddrSpace *) ~((uintp)0)) {\n return false;\n }\n else if (op2.base == (AddrSpace *)0) {\n return false;\n }\n else if (op2.base == (AddrSpace *) ~((uintp)0)) {\n return true;\n }\n return (base->getIndex() < op2.base->getIndex());\n }\n if (offset != op2.offset) return (offset < op2.offset);\n return false;\n}\n\n/// Do an ordering comparison of two addresses.\n/// \\param op2 is the address to compare to\n/// \\return \\b true if \\e this comes before or is equal to \\e op2\ninline bool Address::operator<=(const Address &op2) const {\n if (base != op2.base) {\n if (base == (AddrSpace *)0) {\n return true;\n }\n else if (base == (AddrSpace *) ~((uintp)0)) {\n return false;\n }\n else if (op2.base == (AddrSpace *)0) {\n return false;\n }\n else if (op2.base == (AddrSpace *) ~((uintp)0)) {\n return true;\n }\n return (base->getIndex() < op2.base->getIndex());\n }\n if (offset != op2.offset) return (offset < op2.offset);\n return true;\n}\n\n/// Add an integer value to the offset portion of the address.\n/// The addition takes into account the \\e size of the address\n/// space, and the Address will wrap around if necessary.\n/// \\param off is the number to add to the offset\n/// \\return the new incremented address\ninline Address Address::operator+(int8 off) const {\n return Address(base,base->wrapOffset(offset+off));\n}\n\n/// Subtract an integer value from the offset portion of the\n/// address. The subtraction takes into account the \\e size of\n/// the address space, and the Address will wrap around if\n/// necessary.\n/// \\param off is the number to subtract from the offset\n/// \\return the new decremented address\ninline Address Address::operator-(int8 off) const {\n return Address(base,base->wrapOffset(offset-off));\n}\n\n/// This method is equivalent to Address::overlap, but a range in the \\e join space can be\n/// considered overlapped with its constituent pieces.\n/// If \\e this + \\e skip falls in the range, \\e op to \\e op + \\e size, then a non-negative integer is\n/// returned indicating where in the interval it falls. Otherwise -1 is returned.\n/// \\param skip is an adjust to \\e this address\n/// \\param op is the start of the range to check\n/// \\param size is the size of the range\n/// \\return an integer indicating how overlap occurs\ninline int4 Address::overlapJoin(int4 skip,const Address &op,int4 size) const\n\n{\n return op.getSpace()->overlapJoin(op.getOffset(), size, base, offset, skip);\n}\n\n/// Determine if this address is from the \\e constant \\e space.\n/// All constant values are represented as an offset into\n/// the \\e constant \\e space.\n/// \\return \\b true if this address represents a constant\ninline bool Address::isConstant(void) const {\n return (base->getType() == IPTR_CONSTANT);\n}\n\n/// Determine if this address represents a set of joined memory locations.\n/// \\return \\b true if this address represents a join\ninline bool Address::isJoin(void) const {\n return (base->getType() == IPTR_JOIN);\n}\n\n/// Save an \\ element corresponding to this address to a\n/// stream. The exact format is determined by the address space,\n/// but this generally has a \\e space and an \\e offset attribute.\n/// \\param encoder is the stream encoder\ninline void Address::encode(Encoder &encoder) const {\n encoder.openElement(ELEM_ADDR);\n if (base!=(AddrSpace *)0)\n base->encodeAttributes(encoder,offset);\n encoder.closeElement(ELEM_ADDR);\n}\n\n/// Encode an \\ element corresponding to this address to a\n/// stream. The tag will also include an extra \\e size attribute\n/// so that it can describe an entire memory range.\n/// \\param encoder is the stream encoder\n/// \\param size is the number of bytes in the range\ninline void Address::encode(Encoder &encoder,int4 size) const {\n encoder.openElement(ELEM_ADDR);\n if (base!=(AddrSpace *)0)\n base->encodeAttributes(encoder,offset,size);\n encoder.closeElement(ELEM_ADDR);\n}\n\n/// \\param addr is the Address to test for containment\n/// \\return \\b true if addr is in \\b this Range\ninline bool Range::contains(const Address &addr) const {\n if (spc != addr.getSpace()) return false;\n if (first > addr.getOffset()) return false;\n if (last < addr.getOffset()) return false;\n return true;\n}\n\n/// \\param size is the desired size in bytes\n/// \\return a value appropriate for masking off the first \\e size bytes\ninline uintb calc_mask(int4 size) { return uintbmasks[((uint4)size) < 8 ? size : 8]; }\n\n/// Perform a CPUI_INT_RIGHT on the given val\n/// \\param val is the value to shift\n/// \\param sa is the number of bits to shift\n/// \\return the shifted value\ninline uintb pcode_right(uintb val,int4 sa) {\n if (sa >= 8*sizeof(uintb)) return 0;\n return val >> sa;\n}\n\n/// Perform a CPUI_INT_LEFT on the given val\n/// \\param val is the value to shift\n/// \\param sa is the number of bits to shift\n/// \\return the shifted value\ninline uintb pcode_left(uintb val,int4 sa) {\n if (sa >= 8*sizeof(uintb)) return 0;\n return val << sa;\n}\n\n/// \\brief Calculate smallest mask that covers the given value\n///\n/// Calculcate a mask that covers either the least significant byte, uint2, uint4, or uint8,\n/// whatever is smallest.\n/// \\param val is the given value\n/// \\return the minimal mask\ninline uintb minimalmask(uintb val)\n\n{\n if (val > 0xffffffff)\n return ~((uintb)0);\n if (val > 0xffff)\n return 0xffffffff;\n if (val > 0xff)\n return 0xffff;\n return 0xff;\n}\n\n/// \\brief Sign extend above given bit\n///\n/// Sign extend \\b val starting at \\b bit\n/// \\param val is the value to be sign-extended\n/// \\param bit is the index of the bit to extend from (0=least significant bit)\n/// \\return the sign extended value\ninline intb sign_extend(intb val,int4 bit)\n\n{\n int4 sa = 8*sizeof(intb) - (bit+1);\n val = (val << sa) >> sa;\n return val;\n}\n\n/// \\brief Clear all bits above given bit\n///\n/// Zero extend \\b val starting at \\b bit\n/// \\param val is the value to be zero extended\n/// \\param bit is the index of the bit to extend from (0=least significant bit)\n/// \\return the extended value\ninline intb zero_extend(intb val,int4 bit)\n\n{\n int4 sa = sizeof(intb)*8 - (bit+1);\n return (intb)(((uintb)val << sa) >> sa);\n}\n\nextern bool signbit_negative(uintb val,int4 size);\t///< Return true if the sign-bit is set\nextern uintb calc_mask(int4 size);\t\t\t///< Calculate a mask for a given byte size\nextern uintb uintb_negate(uintb in,int4 size);\t\t///< Negate the \\e sized value\nextern uintb sign_extend(uintb in,int4 sizein,int4 sizeout);\t///< Sign-extend a value between two byte sizes\n\nextern void byte_swap(intb &val,int4 size);\t\t///< Swap bytes in the given value\n\nextern uintb byte_swap(uintb val,int4 size);\t\t///< Return the given value with bytes swapped\nextern int4 leastsigbit_set(uintb val);\t\t\t///< Return index of least significant bit set in given value\nextern int4 mostsigbit_set(uintb val);\t\t\t///< Return index of most significant bit set in given value\nextern int4 popcount(uintb val);\t\t\t///< Return the number of one bits in the given value\nextern int4 count_leading_zeros(uintb val);\t\t///< Return the number of leading zero bits in the given value\n\nextern uintb coveringmask(uintb val);\t\t\t///< Return a mask that \\e covers the given value\nextern int4 bit_transitions(uintb val,int4 sz);\t\t///< Calculate the number of bit transitions in the sized value\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/compression.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"compression.hh\"\n\nnamespace ghidra {\n\n/// The compression \\b level ranges from 1-9 from faster/least compression to slower/most compression.\n/// Use a \\b level of 0 for no compression and -1 for the \\e default compression level.\n/// \\param level is the compression level\nCompress::Compress(int4 level)\n\n{\n compStream.zalloc = Z_NULL;\n compStream.zfree = Z_NULL;\n compStream.opaque = Z_NULL;\n int4 ret = deflateInit(&compStream, level);\n if (ret != Z_OK)\n throw LowlevelError(\"Could not initialize deflate stream state\");\n}\n\nCompress::~Compress(void)\n\n{\n deflateEnd(&compStream);\n}\n\n/// Return the number of bytes of output space still available. Output may be limited by the amount\n/// of space in the output buffer or the amount of data available in the current input buffer.\n/// \\param buffer is where compressed bytes are stored\n/// \\param sz is the size, in bytes, of the buffer\n/// \\param finish is set to \\b true if this is the final buffer to add to the stream\n/// \\return the number of output bytes still available\nint4 Compress::deflate(uint1 *buffer,int4 sz,bool finish)\n\n{\n int flush = finish ? Z_FINISH : Z_NO_FLUSH;\n compStream.avail_out = sz;\n compStream.next_out = buffer;\n\n int ret = ::deflate(&compStream, flush);\n if (ret == Z_STREAM_ERROR)\n throw LowlevelError(\"Error compressing stream\");\n return compStream.avail_out;\n}\n\nDecompress::Decompress(void)\n\n{\n streamFinished = false;\n compStream.zalloc = Z_NULL;\n compStream.zfree = Z_NULL;\n compStream.opaque = Z_NULL;\n compStream.avail_in = 0;\n compStream.next_in = Z_NULL;\n int ret = inflateInit(&compStream);\n if (ret != Z_OK)\n throw LowlevelError(\"Could not initialize inflate stream state\");\n}\n\n/// Return the number of bytes of output space still available. Output may be limited by the amount\n/// of space in the output buffer or the amount of data available in the current input buffer.\n/// \\param buffer is where uncompressed bytes are stored\n/// \\param sz is the size, in bytes, of the buffer\n/// \\return the number of output bytes still available\nint4 Decompress::inflate(uint1 *buffer,int4 sz)\n\n{\n compStream.avail_out = sz;\n compStream.next_out = buffer;\n\n int ret = ::inflate(&compStream, Z_NO_FLUSH);\n switch (ret) {\n case Z_NEED_DICT:\n case Z_DATA_ERROR:\n case Z_MEM_ERROR:\n case Z_STREAM_ERROR:\n throw LowlevelError(\"Error decompressing stream\");\n case Z_STREAM_END:\n streamFinished = true;\n break;\n default:\n break;\n }\n\n return compStream.avail_out;\n}\n\nDecompress::~Decompress(void)\n\n{\n inflateEnd(&compStream);\n}\n\nconst int4 CompressBuffer::IN_BUFFER_SIZE = 4096;\nconst int4 CompressBuffer::OUT_BUFFER_SIZE = 4096;\n\n/// \\param s is the backing output stream\n/// \\param level is the level of compression\nCompressBuffer::CompressBuffer(ostream &s,int4 level)\n : outStream(s), compressor(level)\n{\n inBuffer = new uint1[IN_BUFFER_SIZE];\n outBuffer = new uint1[OUT_BUFFER_SIZE];\n setp((char *)inBuffer,(char *)inBuffer + IN_BUFFER_SIZE-1);\n}\n\nCompressBuffer::~CompressBuffer(void)\n\n{\n delete [] inBuffer;\n delete [] outBuffer;\n}\n\n/// The compressor is called repeatedly and its output is written to the backing stream\n/// until the compressor can no longer fill the \\e output buffer.\n/// \\param lastBuffer is \\b true if this is the final set of bytes to add to the compressed stream\nvoid CompressBuffer::flushInput(bool lastBuffer)\n\n{\n int len = pptr() - pbase();\n compressor.input((uint1 *)pbase(),len);\n int4 outAvail;\n do {\n outAvail = OUT_BUFFER_SIZE;\n outAvail = compressor.deflate(outBuffer,outAvail,lastBuffer);\n outStream.write((char *)outBuffer,OUT_BUFFER_SIZE-outAvail);\n } while(outAvail == 0);\n pbump(-len);\n}\n\n/// \\param c is the final character filling the buffer\n/// \\return the written character\nint CompressBuffer::overflow(int c)\n\n{\n if (c != EOF) {\n *pptr() = c;\n pbump(1);\n }\n flushInput(false);\n return c;\n}\n\n/// \\return 0 for success\nint CompressBuffer::sync(void)\n\n{\n flushInput(true);\n return 0;\n}\n\n}\n" }, { "path": "pypcode/sleigh/compression.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file compression.hh\n/// \\brief The Compress and Decompress classes wrapping the deflate and inflate algorithms\n#ifndef __COMPRESSION__\n#define __COMPRESSION__\n\n#include \"error.hh\"\n#ifdef LOCAL_ZLIB\n#include \"../zlib/zlib.h\"\n#else\n#include \n#endif\n\nnamespace ghidra {\n\n/// \\brief Wrapper for the deflate algorithm\n///\n/// Initialize/free algorithm resources. Provide successive arrays of bytes to compress via\n/// the input() method. Compute successive arrays of compressed bytes via the deflate() method.\nclass Compress {\n z_stream compStream;\t\t///< The zlib deflate algorithm state\npublic:\n Compress(int4 level);\t\t///< Initialize the deflate algorithm state\n ~Compress(void);\t\t///< Free algorithm state resources\n\n /// \\brief Provide the next sequence of bytes to be compressed\n ///\n /// \\param buffer is a pointer to the bytes to compress\n /// \\param sz is the number of bytes\n void input(uint1 *buffer,int4 sz) {\n compStream.avail_in = sz;\n compStream.next_in = buffer;\n }\n int4 deflate(uint1 *buffer,int4 sz,bool finish);\t///< Deflate as much as possible into given buffer\n};\n\n/// \\brief Wrapper for the inflate algorithm\n///\n/// Initialize/free algorithm resources. Provide successive arrays of compressed bytes via\n/// the input() method. Compute successive arrays of uncompressed bytes via the inflate() method.\nclass Decompress {\n z_stream compStream;\t\t///< The zlib inflate algorithm state\n bool streamFinished;\t\t///< Set to \\b true if the end of the compressed stream has been reached\npublic:\n Decompress(void);\t\t///< Initialize the inflate algorithm state\n ~Decompress(void);\t\t///< Free algorithm state resources\n\n /// \\brief Provide the next sequence of compressed bytes\n ///\n /// \\param buffer is a pointer to the compressed bytes\n /// \\param sz is the number of bytes\n void input(uint1 *buffer,int4 sz) {\n compStream.next_in = buffer;\n compStream.avail_in = sz;\n }\n\n bool isFinished(void) const { return streamFinished; }\t///< Return \\b if end of compressed stream is reached\n int4 inflate(uint1 *buffer,int4 sz);\t///< Inflate as much as possible into given buffer\n};\n\n/// \\brief Stream buffer that performs compression\n///\n/// Provides an ostream filter that compresses the stream using the \\e deflate algorithm.\n/// The stream buffer is provided a backing stream that is the ultimate destination of the compressed bytes.\n/// A front-end stream is initialized with \\b this stream buffer.\n/// After writing the full sequence of bytes to compressed to the front-end stream, make sure to\n/// call the stream's flush() method to emit the final compressed bytes to the backing stream.\nclass CompressBuffer : public std::streambuf {\n static const int4 IN_BUFFER_SIZE;\t///< Number of bytes in the \\e input buffer\n static const int4 OUT_BUFFER_SIZE;\t///< Number of bytes in the \\e output buffer\n ostream &outStream;\t\t\t///< The backing stream receiving compressed bytes\n uint1 *inBuffer;\t\t\t///< The \\e input buffer\n uint1 *outBuffer;\t\t\t///< The \\e output buffer\n Compress compressor;\t\t\t///< Compressor state\nprotected:\n void flushInput(bool lastBuffer);\t///< Compress the current set of bytes in the \\e input buffer\n virtual int overflow(int c);\t\t///< Pass the filled input buffer to the compressor\n virtual int sync(void);\t\t///< Pass remaining bytes in the input buffer to the compressor\npublic:\n CompressBuffer(ostream &s,int4 level);\t///< Constructor\n ~CompressBuffer(void);\t\t\t///< Destructor\n};\n\n}\n\n#endif\n" }, { "path": "pypcode/sleigh/context.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"context.hh\"\n#include \"slghsymbol.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nParserContext::ParserContext(ContextCache *ccache,Translate *trans)\n\n{\n parsestate = uninitialized;\n contcache = ccache;\n translate = trans;\n if (ccache != (ContextCache *)0) {\n contextsize = ccache->getDatabase()->getContextSize();\n context = new uintm[ contextsize ];\n }\n else {\n contextsize = 0;\n context = (uintm *)0;\n }\n}\n\nvoid ParserContext::initialize(int4 maxstate,int4 maxparam,AddrSpace *spc)\n\n{\n const_space = spc;\n state.resize(maxstate);\n state[0].parent = (ConstructState *)0;\n for(int4 i=0;iinstructionLength(naddr);\n n2addr = naddr + length;\n }\n return n2addr;\n}\n\nuintm ParserContext::getInstructionBytes(int4 bytestart,int4 size,uint4 off) const\n\n{\t\t\t\t// Get bytes from the instruction stream into a intm\n\t\t\t\t// (assuming big endian format)\n off += bytestart;\n if (off >=16)\n throw BadDataError(\"Instruction is using more than 16 bytes\"); \n const uint1 *ptr = buf + off;\n uintm res = 0;\n for(int4 i=0;i= 16)\n throw BadDataError(\"Instruction is using more than 16 bytes\");\n const uint1 *ptr = buf + off;\n startbit = startbit % 8;\n int4 bytesize = (startbit+size-1)/8 + 1;\n uintm res = 0;\n for(int4 i=0;i>= 8*sizeof(uintm)-size;\t// Shift to bottom of intm\n return res;\n}\n\nuintm ParserContext::getContextBytes(int4 bytestart,int4 size) const\n\n{\t\t\t\t// Get bytes from context into a uintm\n int4 intstart = bytestart / sizeof(uintm);\n uintm res = context[ intstart ];\n int4 byteOffset = bytestart % sizeof(uintm);\n int4 unusedBytes = sizeof(uintm) - size;\n res <<= byteOffset*8;\n res >>= unusedBytes*8;\n int4 remaining = size - sizeof(uintm) + byteOffset;\n if ((remaining > 0)&&(++intstart < contextsize)) { // If we extend beyond boundary of a single uintm\n uintm res2 = context[ intstart ];\n unusedBytes = sizeof(uintm) - remaining;\n res2 >>= unusedBytes * 8;\n res |= res2;\n }\n return res;\n}\n\nuintm ParserContext::getContextBits(int4 startbit,int4 size) const\n\n{\n int4 intstart = startbit / (8*sizeof(uintm));\n uintm res = context[ intstart ]; // Get intm containing highest bit\n int4 bitOffset = startbit % (8*sizeof(uintm));\n int4 unusedBits = 8*sizeof(uintm) - size;\n res <<= bitOffset;\t// Shift startbit to highest position\n res >>= unusedBits;\n int4 remaining = size - 8*sizeof(uintm) + bitOffset;\n if ((remaining > 0) && (++intstart < contextsize)) {\n uintm res2 = context[ intstart ];\n unusedBits = 8*sizeof(uintm) - remaining;\n res2 >>= unusedBits;\n res |= res2;\n }\n return res;\n}\n\nvoid ParserContext::addCommit(TripleSymbol *sym,int4 num,uintm mask,bool flow,ConstructState *point)\n\n{\n contextcommit.emplace_back();\n ContextSet &set(contextcommit.back());\n\n set.sym = sym;\n set.point = point;\t\t// This is the current state\n set.num = num;\n set.mask = mask;\n set.value = context[num] & mask;\n set.flow = flow;\n}\n\nvoid ParserContext::applyCommits(void)\n\n{\n if (contextcommit.empty()) return;\n ParserWalker walker(this);\n walker.baseState();\n\n vector::iterator iter;\n\n for(iter=contextcommit.begin();iter!=contextcommit.end();++iter) {\n TripleSymbol *sym = (*iter).sym;\n Address commitaddr;\n if (sym->getType() == SleighSymbol::operand_symbol) {\n // The value for an OperandSymbol is probabably already\n // calculated, we just need to find the right\n // tree node of the state\n int4 i = ((OperandSymbol *)sym)->getIndex();\n FixedHandle &h((*iter).point->resolve[i]->hand);\n commitaddr = Address(h.space,h.offset_offset);\n }\n else {\n FixedHandle hand;\n sym->getFixedHandle(hand,walker);\n commitaddr = Address(hand.space,hand.offset_offset);\n }\n if (commitaddr.isConstant()) {\n // If the symbol handed to globalset was a computed value, the getFixedHandle calculation\n // will return a value in the constant space. If this is a case, we explicitly convert the\n // offset into the current address space\n uintb newoff = AddrSpace::addressToByte(commitaddr.getOffset(),addr.getSpace()->getWordSize());\n commitaddr = Address(addr.getSpace(),newoff);\n }\n\n\t\t\t\t// Commit context change\n if ((*iter).flow)\t\t// The context flows\n contcache->setContext(commitaddr,(*iter).num,(*iter).mask,(*iter).value);\n else { // Set the context so that is doesn't flow\n Address nextaddr = commitaddr + 1;\n if (nextaddr.getOffset() < commitaddr.getOffset())\n\tcontcache->setContext(commitaddr,(*iter).num,(*iter).mask,(*iter).value);\n else\n\tcontcache->setContext(commitaddr,nextaddr,(*iter).num,(*iter).mask,(*iter).value);\n }\n }\n}\n\nvoid ParserWalker::setOutOfBandState(Constructor *ct,int4 index,ConstructState *tempstate,const ParserWalker &otherwalker)\n\n{ // Initialize walker for future calls into getInstructionBytes assuming -ct- is the current position in the walk\n const ConstructState *pt = otherwalker.point;\n int4 curdepth = otherwalker.depth;\n while(pt->ct != ct) {\n if (curdepth <= 0) return;\n curdepth -= 1;\n pt = pt->parent;\n }\n OperandSymbol *sym = ct->getOperand(index);\n int4 i = sym->getOffsetBase();\n // if i<0, i.e. the offset of the operand is constructor relative\n // its possible that the branch corresponding to the operand\n // has not been constructed yet. Context expressions are\n // evaluated BEFORE the constructors branches are created.\n // So we have to construct the offset explicitly.\n if (i<0)\n tempstate->offset = pt->offset + sym->getRelativeOffset();\n else\n tempstate->offset = pt->resolve[index]->offset;\n\n tempstate->ct = ct;\n tempstate->length = pt->length;\n point = tempstate;\n depth = 0;\n breadcrumb[0] = 0;\n}\n\nvoid ParserWalkerChange::calcCurrentLength(int4 length,int4 numopers)\n\n{\t\t\t\t// Calculate the length of the current constructor\n\t\t\t\t// state assuming all its operands are constructed\n length += point->offset;\t// Convert relative length to absolute length\n for(int4 i=0;iresolve[i];\n int4 sublength = subpoint->length + subpoint->offset;\n\t\t\t\t// Since subpoint->offset is an absolute offset\n\t\t\t\t// (relative to beginning of instruction) sublength\n if (sublength > length)\t// is absolute and must be compared to absolute length\n length = sublength;\n }\n point->length = length - point->offset; // Convert back to relative length\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/context.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __CONTEXT_HH__\n#define __CONTEXT_HH__\n\n#include \"globalcontext.hh\"\n#include \"opcodes.hh\"\n\nnamespace ghidra {\n\nclass Token {\t\t\t// A multiple-byte sized chunk of pattern in a bitstream\n string name;\n int4 size;\t\t\t// Number of bytes in token;\n int4 index;\t\t\t// Index of this token, for resolving offsets\n bool bigendian;\npublic:\n Token(const string &nm,int4 sz,bool be,int4 ind) : name(nm) { size = sz; bigendian=be; index = ind; }\n int4 getSize(void) const { return size; }\n bool isBigEndian(void) const { return bigendian; }\n int4 getIndex(void) const { return index; }\n const string &getName(void) const { return name; }\n};\n\nstruct FixedHandle {\t\t// A handle that is fully resolved\n AddrSpace *space;\n uint4 size;\n AddrSpace *offset_space;\t// Either null or where dynamic offset is stored\n uintb offset_offset;\t\t// Either static offset or ptr offset\n uint4 offset_size;\t\t// Size of pointer\n AddrSpace *temp_space;\t// Consistent temporary location for value\n uintb temp_offset;\n};\n\nclass Constructor;\nstruct ConstructState {\n Constructor *ct;\n FixedHandle hand;\n vector resolve;\n ConstructState *parent;\n int4 length;\t\t\t// Length of this instantiation of the constructor\n uint4 offset;\t\t\t// Absolute offset (from start of instruction)\n};\n\nclass TripleSymbol;\nstruct ContextSet {\t\t// Instructions for setting a global context value\n TripleSymbol *sym;\t\t// Resolves to address where setting takes effect\n ConstructState *point;\t// Point at which context set was made\n int4 num;\t\t\t// Number of context word affected\n uintm mask;\t\t\t// Bits within word affected\n uintm value;\t\t\t// New setting for bits\n bool flow;\t\t\t// Does the new context flow from its set point\n};\n\nclass ParserWalker;\t\t// Forward declaration\nclass ParserWalkerChange;\nclass Translate;\n\nclass ParserContext {\n friend class ParserWalker;\n friend class ParserWalkerChange;\npublic:\n enum {\t\t\t// Possible states of the ParserContext\n uninitialized = 0,\t\t// Instruction has not been parsed at all\n disassembly = 1,\t\t// Instruction is parsed in preparation for disassembly\n pcode = 2\t\t\t// Instruction is parsed in preparation for generating p-code\n };\nprivate:\n Translate *translate;\t\t// Instruction parser\n int4 parsestate;\n AddrSpace *const_space;\n uint1 buf[16];\t\t// Buffer of bytes in the instruction stream\n uintm *context;\t\t// Pointer to local context\n int4 contextsize;\t\t// Number of entries in context array\n ContextCache *contcache; // Interface for getting/setting context\n vector contextcommit;\n Address addr;\t\t// Address of start of instruction\n Address naddr;\t\t// Address of next instruction\n mutable Address n2addr;\t// Address of instruction after the next\n Address calladdr;\t\t// For injections, this is the address of the call being overridden\n vector state; // Current resolved instruction\n ConstructState *base_state;\n int4 alloc;\t\t\t// Number of ConstructState's allocated\n int4 delayslot;\t\t// delayslot depth\npublic:\n ParserContext(ContextCache *ccache,Translate *trans);\n ~ParserContext(void) { if (context != (uintm *)0) delete [] context; }\n uint1 *getBuffer(void) { return buf; }\n void initialize(int4 maxstate,int4 maxparam,AddrSpace *spc);\n int4 getParserState(void) const { return parsestate; }\n void setParserState(int4 st) { parsestate = st; }\n void deallocateState(ParserWalkerChange &walker);\n void allocateOperand(int4 i,ParserWalkerChange &walker);\n void setAddr(const Address &ad) { addr = ad; n2addr = Address(); }\n void setNaddr(const Address &ad) { naddr = ad; }\n void setCalladdr(const Address &ad) { calladdr = ad; }\n void addCommit(TripleSymbol *sym,int4 num,uintm mask,bool flow,ConstructState *point);\n void clearCommits(void) { contextcommit.clear(); }\n void applyCommits(void);\n const Address &getAddr(void) const { return addr; }\n const Address &getNaddr(void) const { return naddr; }\n const Address &getN2addr(void) const;\n const Address &getDestAddr(void) const { return calladdr; }\n const Address &getRefAddr(void) const { return calladdr; }\n AddrSpace *getCurSpace(void) const { return addr.getSpace(); }\n AddrSpace *getConstSpace(void) const { return const_space; }\n uintm getInstructionBytes(int4 byteoff,int4 numbytes,uint4 off) const;\n uintm getContextBytes(int4 byteoff,int4 numbytes) const;\n uintm getInstructionBits(int4 startbit,int4 size,uint4 off) const;\n uintm getContextBits(int4 startbit,int4 size) const;\n void setContextWord(int4 i,uintm val,uintm mask) { context[i] = (context[i]&(~mask))|(mask&val); }\n void loadContext(void) { contcache->getContext(addr,context); }\n int4 getLength(void) const { return base_state->length; }\n void setDelaySlot(int4 val) { delayslot = val; }\n int4 getDelaySlot(void) const { return delayslot; }\n};\n \nclass ParserWalker {\t\t// A class for walking the ParserContext\n const ParserContext *const_context;\n const ParserContext *cross_context;\nprotected:\n ConstructState *point;\t// The current node being visited\n int4 depth;\t\t\t// Depth of the current node\n int4 breadcrumb[32];\t// Path of operands from root\npublic:\n ParserWalker(const ParserContext *c) { const_context = c; cross_context = (const ParserContext *)0; }\n ParserWalker(const ParserContext *c,const ParserContext *cross) { const_context = c; cross_context = cross; }\n const ParserContext *getParserContext(void) const { return const_context; }\n void baseState(void) { point = const_context->base_state; depth=0; breadcrumb[0] = 0; }\n void setOutOfBandState(Constructor *ct,int4 index,ConstructState *tempstate,const ParserWalker &otherwalker);\n bool isState(void) const { return (point != (ConstructState *)0); }\n void pushOperand(int4 i) { breadcrumb[depth++] = i+1; point = point->resolve[i]; breadcrumb[depth] = 0; }\n void popOperand(void) { point = point->parent; depth-= 1; }\n uint4 getOffset(int4 i) const { if (i<0) return point->offset; \n ConstructState *op=point->resolve[i]; return op->offset + op->length; }\n Constructor *getConstructor(void) const { return point->ct; }\n int4 getOperand(void) const { return breadcrumb[depth]; }\n FixedHandle &getParentHandle(void) { return point->hand; }\n const FixedHandle &getFixedHandle(int4 i) const { return point->resolve[i]->hand; }\n AddrSpace *getCurSpace(void) const { return const_context->getCurSpace(); }\n AddrSpace *getConstSpace(void) const { return const_context->getConstSpace(); }\n const Address &getAddr(void) const { if (cross_context != (const ParserContext *)0) { return cross_context->getAddr(); } return const_context->getAddr(); }\n const Address &getNaddr(void) const { if (cross_context != (const ParserContext *)0) { return cross_context->getNaddr();} return const_context->getNaddr(); }\n const Address &getN2addr(void) const { if (cross_context != (const ParserContext *)0) { return cross_context->getN2addr();} return const_context->getN2addr(); }\n const Address &getRefAddr(void) const { if (cross_context != (const ParserContext *)0) { return cross_context->getRefAddr();} return const_context->getRefAddr(); }\n const Address &getDestAddr(void) const { if (cross_context != (const ParserContext *)0) { return cross_context->getDestAddr();} return const_context->getDestAddr(); }\n int4 getLength(void) const { return const_context->getLength(); }\n uintm getInstructionBytes(int4 byteoff,int4 numbytes) const {\n return const_context->getInstructionBytes(byteoff,numbytes,point->offset); }\n uintm getContextBytes(int4 byteoff,int4 numbytes) const {\n return const_context->getContextBytes(byteoff,numbytes); }\n uintm getInstructionBits(int4 startbit,int4 size) const {\n return const_context->getInstructionBits(startbit,size,point->offset); }\n uintm getContextBits(int4 startbit,int4 size) const {\n return const_context->getContextBits(startbit,size); }\n};\n\nclass ParserWalkerChange : public ParserWalker { // Extension to walker that allows for on the fly modifications to tree\n friend class ParserContext;\n ParserContext *context;\npublic:\n ParserWalkerChange(ParserContext *c) : ParserWalker(c) { context = c; }\n ParserContext *getParserContext(void) { return context; }\n ConstructState *getPoint(void) { return point; }\n void setOffset(uint4 off) { point->offset = off; }\n void setConstructor(Constructor *c) { point->ct = c; }\n void setCurrentLength(int4 len) { point->length = len; }\n void calcCurrentLength(int4 length,int4 numopers);\n};\n\nstruct SleighError : public LowlevelError {\n SleighError(const string &s) : LowlevelError(s) {}\n};\n\ninline void ParserContext::deallocateState(ParserWalkerChange &walker) {\n alloc = 1;\n walker.context=this;\n walker.baseState();\n}\n\ninline void ParserContext::allocateOperand(int4 i,ParserWalkerChange &walker) {\n ConstructState *opstate = &state[alloc++];\n opstate->parent = walker.point;\n opstate->ct = (Constructor *)0;\n walker.point->resolve[i] = opstate;\n walker.breadcrumb[walker.depth++] += 1;\n walker.point = opstate;\n walker.breadcrumb[walker.depth] = 0;\n}\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/emulate.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"emulate.hh\"\n\nnamespace ghidra {\n\n/// Any time the emulator is about to execute a user-defined pcode op with the given name,\n/// the indicated breakpoint is invoked first. The break table does \\e not assume responsibility\n/// for freeing the breakpoint object.\n/// \\param name is the name of the user-defined pcode op\n/// \\param func is the breakpoint object to associate with the pcode op\nvoid BreakTableCallBack::registerPcodeCallback(const string &name,BreakCallBack *func)\n\n{\n func->setEmulate(emulate);\n vector userops;\n trans->getUserOpNames(userops);\n for(int4 i=0;isetEmulate(emulate);\n addresscallback[addr] = func;\n}\n\n/// This routine invokes the setEmulate method on each breakpoint currently in the table\n/// \\param emu is the emulator to be associated with the breakpoints\nvoid BreakTableCallBack::setEmulate(Emulate *emu)\n\n{ // Make sure all callbbacks are aware of new emulator\n emulate = emu;\n map::iterator iter1;\n\n for(iter1=addresscallback.begin();iter1!=addresscallback.end();++iter1)\n (*iter1).second->setEmulate(emu);\n\n map::iterator iter2;\n\n\n for(iter2=pcodecallback.begin();iter2!=pcodecallback.end();++iter2)\n (*iter2).second->setEmulate(emu);\n}\n\n/// This routine examines the pcode-op based container for any breakpoints associated with the\n/// given op. If one is found, its pcodeCallback method is invoked.\n/// \\param curop is pcode op being checked for breakpoints\n/// \\return \\b true if the breakpoint exists and returns \\b true, otherwise return \\b false\nbool BreakTableCallBack::doPcodeOpBreak(PcodeOpRaw *curop)\n\n{\n uintb val = curop->getInput(0)->offset;\n map::const_iterator iter;\n\n iter = pcodecallback.find(val);\n if (iter == pcodecallback.end()) return false;\n return (*iter).second->pcodeCallback(curop);\n}\n\n/// This routine examines the address based container for any breakpoints associated with the\n/// given address. If one is found, its addressCallback method is invoked.\n/// \\param addr is the address being checked for breakpoints\n/// \\return \\b true if the breakpoint exists and returns \\b true, otherwise return \\b false\nbool BreakTableCallBack::doAddressBreak(const Address &addr)\n\n{\n map::const_iterator iter;\n \n iter = addresscallback.find(addr);\n if (iter == addresscallback.end()) return false;\n return (*iter).second->addressCallback(addr);\n}\n\n/// Provide the emitter with the containers that will hold the cached p-code ops and varnodes.\n/// \\param ocache is the container for cached PcodeOpRaw\n/// \\param vcache is the container for cached VarnodeData\n/// \\param in is the map of OpBehavior\n/// \\param uniqReserve is the starting offset for temporaries in the \\e unique space\nPcodeEmitCache::PcodeEmitCache(vector &ocache,vector &vcache,\n\t\t\t const vector &in,uintb uniqReserve)\n : opcache(ocache), varcache(vcache), inst(in)\n{\n uniq = uniqReserve;\n}\n\n/// Create an internal copy of the VarnodeData and cache it.\n/// \\param var is the incoming VarnodeData being dumped\n/// \\return the cloned VarnodeData\nVarnodeData *PcodeEmitCache::createVarnode(const VarnodeData *var)\n\n{\n VarnodeData *res = new VarnodeData();\n *res = *var;\n varcache.push_back(res);\n return res;\n}\n\nvoid PcodeEmitCache::dump(const Address &addr,OpCode opc,VarnodeData *outvar,VarnodeData *vars,int4 isize)\n\n{\n PcodeOpRaw *op = new PcodeOpRaw();\n op->setSeqNum(addr,uniq);\n opcache.push_back(op);\n op->setBehavior( inst[opc] );\n uniq += 1;\n if (outvar != (VarnodeData *)0) {\n VarnodeData *outvn = createVarnode(outvar);\n op->setOutput(outvn);\n }\n for(int4 i=0;iaddInput(invn);\n }\n}\n\n/// This method executes a single pcode operation, the current one (returned by getCurrentOp()).\n/// The MemoryState of the emulator is queried and changed as needed to accomplish this.\nvoid Emulate::executeCurrentOp(void)\n\n{\n if (currentBehave == (OpBehavior *)0) {\t// Presumably a NO-OP\n fallthruOp();\n return;\n }\n if (currentBehave->isSpecial()) {\n switch(currentBehave->getOpcode()) {\n case CPUI_LOAD:\n executeLoad();\n fallthruOp();\n break;\n case CPUI_STORE:\n executeStore();\n fallthruOp();\n break;\n case CPUI_BRANCH:\n executeBranch();\n break;\n case CPUI_CBRANCH:\n if (executeCbranch())\n\texecuteBranch();\n else\n\tfallthruOp();\n break;\n case CPUI_BRANCHIND:\n executeBranchind();\n break;\n case CPUI_CALL:\n executeCall();\n break;\n case CPUI_CALLIND:\n executeCallind();\n break;\n case CPUI_CALLOTHER:\n executeCallother();\n break;\n case CPUI_RETURN:\n executeBranchind();\n break;\n case CPUI_MULTIEQUAL:\n executeMultiequal();\n fallthruOp();\n break;\n case CPUI_INDIRECT:\n executeIndirect();\n fallthruOp();\n break;\n case CPUI_SEGMENTOP:\n executeSegmentOp();\n fallthruOp();\n break;\n case CPUI_CPOOLREF:\n executeCpoolRef();\n fallthruOp();\n break;\n case CPUI_NEW:\n executeNew();\n fallthruOp();\n break;\n default:\n throw LowlevelError(\"Bad special op\");\n }\n }\n else if (currentBehave->isUnary()) {\t// Unary operation\n executeUnary();\n fallthruOp();\n }\n else {\t\t\t// Binary operation\n executeBinary();\n fallthruOp();\t\t// All binary ops are fallthrus\n }\n}\n\nvoid EmulateMemory::executeUnary(void)\n\n{\n uintb in1 = memstate->getValue(currentOp->getInput(0));\n uintb out = currentBehave->evaluateUnary(currentOp->getOutput()->size,\n\t\t\t\t\t currentOp->getInput(0)->size,in1);\n memstate->setValue(currentOp->getOutput(),out);\n}\n\nvoid EmulateMemory::executeBinary(void)\n\n{\n uintb in1 = memstate->getValue(currentOp->getInput(0));\n uintb in2 = memstate->getValue(currentOp->getInput(1));\n uintb out = currentBehave->evaluateBinary(currentOp->getOutput()->size,\n\t\t\t\t\t currentOp->getInput(0)->size,in1,in2);\n memstate->setValue(currentOp->getOutput(),out);\n}\n\nvoid EmulateMemory::executeLoad(void)\n\n{\n uintb off = memstate->getValue(currentOp->getInput(1));\n AddrSpace *spc = currentOp->getInput(0)->getSpaceFromConst();\n\n off = AddrSpace::addressToByte(off,spc->getWordSize());\n uintb res = memstate->getValue(spc,off,currentOp->getOutput()->size);\n memstate->setValue(currentOp->getOutput(),res);\n}\n\nvoid EmulateMemory::executeStore(void)\n\n{\n uintb val = memstate->getValue(currentOp->getInput(2)); // Value being stored\n uintb off = memstate->getValue(currentOp->getInput(1)); // Offset to store at\n AddrSpace *spc = currentOp->getInput(0)->getSpaceFromConst(); // Space to store in\n\n off = AddrSpace::addressToByte(off,spc->getWordSize());\n memstate->setValue(spc,off,currentOp->getInput(2)->size,val);\n}\n\nvoid EmulateMemory::executeBranch(void)\n\n{\n setExecuteAddress(currentOp->getInput(0)->getAddr());\n}\n\nbool EmulateMemory::executeCbranch(void)\n\n{\n uintb cond = memstate->getValue(currentOp->getInput(1));\n return (cond != 0);\n}\n\nvoid EmulateMemory::executeBranchind(void)\n\n{\n uintb off = memstate->getValue(currentOp->getInput(0));\n setExecuteAddress(Address(currentOp->getAddr().getSpace(),off));\n}\n\nvoid EmulateMemory::executeCall(void)\n\n{\n setExecuteAddress(currentOp->getInput(0)->getAddr());\n}\n\nvoid EmulateMemory::executeCallind(void)\n\n{\n uintb off = memstate->getValue(currentOp->getInput(0));\n setExecuteAddress(Address(currentOp->getAddr().getSpace(),off));\n}\n\nvoid EmulateMemory::executeCallother(void)\n\n{\n throw LowlevelError(\"CALLOTHER emulation not currently supported\");\n}\n\nvoid EmulateMemory::executeMultiequal(void)\n\n{\n throw LowlevelError(\"MULTIEQUAL appearing in unheritaged code?\");\n}\n\nvoid EmulateMemory::executeIndirect(void)\n\n{\n throw LowlevelError(\"INDIRECT appearing in unheritaged code?\");\n}\n\nvoid EmulateMemory::executeSegmentOp(void)\n\n{\n throw LowlevelError(\"SEGMENTOP emulation not currently supported\");\n}\n\nvoid EmulateMemory::executeCpoolRef(void)\n\n{\n throw LowlevelError(\"Cannot currently emulate cpool operator\");\n}\n\nvoid EmulateMemory::executeNew(void)\n\n{\n throw LowlevelError(\"Cannot currently emulate new operator\");\n}\n\n/// \\param t is the SLEIGH translator\n/// \\param s is the MemoryState the emulator should manipulate\n/// \\param b is the table of breakpoints the emulator should invoke\nEmulatePcodeCache::EmulatePcodeCache(Translate *t,MemoryState *s,BreakTable *b)\n : EmulateMemory(s)\n{\n trans = t;\n OpBehavior::registerInstructions(inst,t);\n breaktable = b;\n breaktable->setEmulate(this);\n}\n\n/// Free all the VarnodeData and PcodeOpRaw objects and clear the cache\nvoid EmulatePcodeCache::clearCache(void)\n\n{\n for(int4 i=0;ioneInstruction(emit,addr);\n current_op = 0;\n instruction_start = true;\n}\n\n/// Set-up currentOp and currentBehave\nvoid EmulatePcodeCache::establishOp(void)\n\n{\n if (current_op < opcache.size()) {\n currentOp = opcache[current_op];\n currentBehave = currentOp->getBehavior();\n return;\n }\n currentOp = (PcodeOpRaw *)0;\n currentBehave = (OpBehavior *)0;\n}\n\n/// Update the iterator into the current pcode cache, and if necessary, generate\n/// the pcode for the fallthru instruction and reset the iterator.\nvoid EmulatePcodeCache::fallthruOp(void)\n\n{\n instruction_start = false;\n current_op += 1;\n if (current_op >= opcache.size()) {\n current_address = current_address + instruction_length;\n createInstruction(current_address);\n }\n establishOp();\n}\n\n/// Since the full instruction is cached, we can do relative branches properly\nvoid EmulatePcodeCache::executeBranch(void)\n\n{\n const Address &destaddr( currentOp->getInput(0)->getAddr() );\n if (destaddr.isConstant()) {\n uintm id = destaddr.getOffset();\n id = id + (uintm)current_op;\n current_op = id;\n if (current_op == opcache.size())\n fallthruOp();\n else if ((current_op < 0)||(current_op >= opcache.size()))\n throw LowlevelError(\"Bad intra-instruction branch\");\n else\n establishOp();\n }\n else\n setExecuteAddress(destaddr);\n}\n\n/// Look for a breakpoint for the given user-defined op and invoke it.\n/// If it doesn't exist, or doesn't replace the action, throw an exception\nvoid EmulatePcodeCache::executeCallother(void)\n\n{\n if (!breaktable->doPcodeOpBreak(currentOp))\n throw LowlevelError(\"Userop not hooked\");\n fallthruOp();\n}\n\n/// Set the current execution address and cache the pcode translation of the machine instruction\n/// at that address\n/// \\param addr is the address where execution should continue\nvoid EmulatePcodeCache::setExecuteAddress(const Address &addr)\n\n{\n current_address = addr;\t// Copy -addr- BEFORE calling createInstruction\n // as it calls clear and may delete -addr-\n createInstruction(current_address);\n establishOp();\n}\n\n/// This routine executes an entire machine instruction at once, as a conventional debugger step\n/// function would do. If execution is at the start of an instruction, the breakpoints are checked\n/// and invoked as needed for the current address. If this routine is invoked while execution is\n/// in the middle of a machine instruction, execution is continued until the current instruction\n/// completes.\nvoid EmulatePcodeCache::executeInstruction(void)\n\n{\n if (instruction_start) {\n if (breaktable->doAddressBreak(current_address))\n return;\n }\n do {\n executeCurrentOp();\n } while(!instruction_start);\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/emulate.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file emulate.hh\n/// \\brief Classes for emulating p-code\n\n#ifndef __EMULATE_HH__\n#define __EMULATE_HH__\n\n#include \"memstate.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nclass Emulate;\t\t\t// Forward declaration\n\n/// \\brief A collection of breakpoints for the emulator\n///\n/// A BreakTable keeps track of an arbitrary number of breakpoints for an emulator.\n/// Breakpoints are either associated with a particular user-defined pcode op,\n/// or with a specific machine address (as in a standard debugger). Through the BreakTable\n/// object, an emulator can invoke breakpoints through the two methods\n/// - doPcodeOpBreak()\n/// - doAddressBreak()\n///\n/// depending on the type of breakpoint they currently want to invoke\nclass BreakTable {\npublic:\n virtual ~BreakTable(void) {};\n\n /// \\brief Associate a particular emulator with breakpoints in this table\n ///\n /// Breakpoints may need access to the context in which they are invoked. This\n /// routine provides the context for all breakpoints in the table.\n /// \\param emu is the Emulate context\n virtual void setEmulate(Emulate *emu)=0;\n\n /// \\brief Invoke any breakpoints associated with this particular pcodeop\n ///\n /// Within the table, the first breakpoint which is designed to work with this particular\n /// kind of pcode operation is invoked. If there was a breakpoint and it was designed\n /// to \\e replace the action of the pcode op, then \\b true is returned.\n /// \\param curop is the instance of a pcode op to test for breakpoints\n /// \\return \\b true if the action of the pcode op is performed by the breakpoint\n virtual bool doPcodeOpBreak(PcodeOpRaw *curop)=0;\n\n /// \\brief Invoke any breakpoints associated with this machine address\n ///\n /// Within the table, the first breakpoint which is designed to work with at this address\n /// is invoked. If there was a breakpoint, and if it was designed to \\e replace\n /// the action of the machine instruction, then \\b true is returned.\n /// \\param addr is address to test for breakpoints\n /// \\return \\b true if the machine instruction has been replaced by a breakpoint\n virtual bool doAddressBreak(const Address &addr)=0;\n};\n\n/// \\brief A breakpoint object\n///\n/// This is a base class for breakpoint objects in an emulator. The breakpoints are implemented\n/// as callback method, which is overridden for the particular behavior needed by the emulator.\n/// Each derived class must override either\n/// - pcodeCallback()\n/// - addressCallback()\n///\n/// depending on whether the breakpoint is tailored for a particular pcode op or for\n/// a machine address.\nclass BreakCallBack {\nprotected:\n Emulate *emulate;\t\t///< The emulator currently associated with this breakpoint\npublic:\n BreakCallBack(void);\t\t///< Generic breakpoint constructor\n virtual ~BreakCallBack(void) {}\n virtual bool pcodeCallback(PcodeOpRaw *op); ///< Call back method for pcode based breakpoints\n virtual bool addressCallback(const Address &addr); ///< Call back method for address based breakpoints\n void setEmulate(Emulate *emu); ///< Associate a particular emulator with this breakpoint\n};\n\n/// The base breakpoint needs no initialization parameters, the setEmulate() method must be\n/// called before the breakpoint can be invoked\ninline BreakCallBack::BreakCallBack(void)\n\n{\n emulate = (Emulate *)0;\n}\n\n/// This routine is invoked during emulation, if this breakpoint has somehow been associated with\n/// this kind of pcode op. The callback can perform any operation on the emulator context it wants.\n/// It then returns \\b true if these actions are intended to replace the action of the pcode op itself.\n/// Or it returns \\b false if the pcode op should still have its normal effect on the emulator context.\n/// \\param op is the particular pcode operation where the break occurs.\n/// \\return \\b true if the normal pcode op action should not occur\ninline bool BreakCallBack::pcodeCallback(PcodeOpRaw *op)\n\n{\n return true;\n}\n\n/// This routine is invoked during emulation, if this breakpoint has somehow been associated with\n/// this address. The callback can perform any operation on the emulator context it wants. It then\n/// returns \\b true if these actions are intended to replace the action of the \\b entire machine\n/// instruction at this address. Or it returns \\b false if the machine instruction should still be\n/// executed normally.\n/// \\param addr is the address where the break has occurred\n/// \\return \\b true if the machine instruction should not be executed\ninline bool BreakCallBack::addressCallback(const Address &addr)\n\n{\n return true;\n}\n\n/// Breakpoints can be associated with one emulator at a time.\n/// \\param emu is the emulator to associate this breakpoint with\ninline void BreakCallBack::setEmulate(Emulate *emu)\n\n{\n emulate = emu;\n}\n\n/// \\brief A basic instantiation of a breakpoint table\n///\n/// This object allows breakpoints to registered in the table via either\n/// - registerPcodeCallback() or\n/// = registerAddressCallback()\n///\n/// Breakpoints are stored in map containers, and the core BreakTable methods\n/// are implemented to search in these containers\nclass BreakTableCallBack : public BreakTable {\n Emulate *emulate;\t\t///< The emulator associated with this table\n Translate *trans;\t\t///< The translator \n map addresscallback;\t///< a container of pcode based breakpoints\n map pcodecallback; ///< a container of addressed based breakpoints\npublic:\n BreakTableCallBack(Translate *t); ///< Basic breaktable constructor\n void registerPcodeCallback(const string &nm,BreakCallBack *func); ///< Register a pcode based breakpoint\n void registerAddressCallback(const Address &addr,BreakCallBack *func); ///< Register an address based breakpoint\n virtual void setEmulate(Emulate *emu); ///< Associate an emulator with all breakpoints in the table\n virtual bool doPcodeOpBreak(PcodeOpRaw *curop); ///< Invoke any breakpoints for the given pcode op\n virtual bool doAddressBreak(const Address &addr); ///< Invoke any breakpoints for the given address\n};\n\n/// The break table needs a translator object so user-defined pcode ops can be registered against\n/// by name.\n/// \\param t is the translator object\ninline BreakTableCallBack::BreakTableCallBack(Translate *t)\n\n{\n emulate = (Emulate *)0;\n trans = t;\n}\n\n/// \\brief A pcode-based emulator interface.\n///\n/// The interface expects that the underlying emulation engine operates on individual pcode\n/// operations as its atomic operation. The interface allows execution stepping through\n/// individual pcode operations. The interface allows\n/// querying of the \\e current pcode op, the current machine address, and the rest of the\n/// machine state.\nclass Emulate {\nprotected:\n bool emu_halted;\t\t///< Set to \\b true if the emulator is halted\n OpBehavior *currentBehave;\t///< Behavior of the next op to execute\n virtual void executeUnary(void)=0; ///< Execute a unary arithmetic/logical operation\n virtual void executeBinary(void)=0; ///< Execute a binary arithmetic/logical operation\n virtual void executeLoad(void)=0; ///< Standard behavior for a p-code LOAD\n virtual void executeStore(void)=0; ///< Standard behavior for a p-code STORE\n\n /// \\brief Standard behavior for a BRANCH\n ///\n /// This routine performs a standard p-code BRANCH operation on the memory state.\n /// This same routine is used for CBRANCH operations if the condition\n /// has evaluated to \\b true.\n virtual void executeBranch(void)=0;\n\n /// \\brief Check if the conditional of a CBRANCH is \\b true\n ///\n /// This routine only checks if the condition for a p-code CBRANCH is true.\n /// It does \\e not perform the actual branch.\n /// \\return the boolean state indicated by the condition\n virtual bool executeCbranch(void)=0;\n virtual void executeBranchind(void)=0; ///< Standard behavior for a BRANCHIND\n virtual void executeCall(void)=0; ///< Standard behavior for a p-code CALL\n virtual void executeCallind(void)=0; ///< Standard behavior for a CALLIND\n virtual void executeCallother(void)=0; ///< Standard behavior for a user-defined p-code op\n virtual void executeMultiequal(void)=0; ///< Standard behavior for a MULTIEQUAL (phi-node)\n virtual void executeIndirect(void)=0;\t///< Standard behavior for an INDIRECT op\n virtual void executeSegmentOp(void)=0; ///< Behavior for a SEGMENTOP\n virtual void executeCpoolRef(void)=0; ///< Standard behavior for a CPOOLREF (constant pool reference) op\n virtual void executeNew(void)=0; ///< Standard behavior for (low-level) NEW op\n virtual void fallthruOp(void)=0; ///< Standard p-code fall-thru semantics\npublic:\n Emulate(void) { emu_halted = true; currentBehave = (OpBehavior *)0; }\t///< generic emulator constructor\n virtual ~Emulate(void) {}\n void setHalt(bool val);\t///< Set the \\e halt state of the emulator\n bool getHalt(void) const;\t///< Get the \\e halt state of the emulator\n virtual void setExecuteAddress(const Address &addr)=0; ///< Set the address of the next instruction to emulate\n virtual Address getExecuteAddress(void) const=0; ///< Get the address of the current instruction being executed\n void executeCurrentOp(void); ///< Do a single pcode op step\n};\n\n/// Applications and breakpoints can use this method and its companion getHalt() to\n/// terminate and restart the main emulator loop as needed. The emulator itself makes no use\n/// of this routine or the associated state variable \\b emu_halted.\n/// \\param val is what the halt state of the emulator should be set to\ninline void Emulate::setHalt(bool val)\n\n{\n emu_halted = val;\n}\n\n/// Applications and breakpoints can use this method and its companion setHalt() to\n/// terminate and restart the main emulator loop as needed. The emulator itself makes no use\n/// of this routine or the associated state variable \\b emu_halted.\n/// \\return \\b true if the emulator is in a \"halted\" state.\ninline bool Emulate::getHalt(void) const\n\n{\n return emu_halted;\n}\n\n/// \\brief An abstract Emulate class using a MemoryState object as the backing machine state\n///\n/// Most p-code operations are implemented using the MemoryState to fetch and store\n/// values. Control-flow is implemented partially in that setExecuteAddress() is called\n/// to indicate which instruction is being executed. The derived class must provide\n/// - fallthruOp()\n/// - setExecuteAddress()\n/// - getExecuteAddress()\n///\n/// The following p-code operations are stubbed out and will throw an exception:\n/// CALLOTHER, MULTIEQUAL, INDIRECT, CPOOLREF, SEGMENTOP, and NEW.\n/// Of course the derived class can override these.\n\nclass EmulateMemory : public Emulate {\nprotected:\n MemoryState *memstate;\t///< The memory state of the emulator\n PcodeOpRaw *currentOp;\t///< Current op to execute\n virtual void executeUnary(void);\n virtual void executeBinary(void);\n virtual void executeLoad(void);\n virtual void executeStore(void);\n virtual void executeBranch(void);\n virtual bool executeCbranch(void);\n virtual void executeBranchind(void);\n virtual void executeCall(void);\n virtual void executeCallind(void);\n virtual void executeCallother(void);\n virtual void executeMultiequal(void);\n virtual void executeIndirect(void);\n virtual void executeSegmentOp(void);\n virtual void executeCpoolRef(void);\n virtual void executeNew(void);\npublic:\n /// Construct given a memory state\n EmulateMemory(MemoryState *mem) { memstate = mem; currentOp = (PcodeOpRaw *)0; }\n MemoryState *getMemoryState(void) const; ///< Get the emulator's memory state\n};\n\n/// \\return the memory state object which this emulator uses\ninline MemoryState *EmulateMemory::getMemoryState(void) const\n\n{\n return memstate;\n}\n\n/// \\brief P-code emitter that dumps its raw Varnodes and PcodeOps to an in memory cache\n///\n/// This is used for emulation when full Varnode and PcodeOp objects aren't needed\nclass PcodeEmitCache : public PcodeEmit {\n vector &opcache;\t///< The cache of current p-code ops\n vector &varcache;\t///< The cache of current varnodes\n const vector &inst;\t///< Array of behaviors for translating OpCode\n uintm uniq;\t\t\t\t///< Starting offset for defining temporaries in \\e unique space\n VarnodeData *createVarnode(const VarnodeData *var);\t///< Clone and cache a raw VarnodeData\npublic:\n PcodeEmitCache(vector &ocache,vector &vcache,\n\t\t const vector &in,uintb uniqReserve);\t///< Constructor\n virtual void dump(const Address &addr,OpCode opc,VarnodeData *outvar,VarnodeData *vars,int4 isize);\n};\n\n/// \\brief A SLEIGH based implementation of the Emulate interface\n///\n/// This implementation uses a Translate object to translate machine instructions into\n/// pcode and caches pcode ops for later use by the emulator. The pcode is cached as soon\n/// as the execution address is set, either explicitly, or via branches and fallthrus. There\n/// are additional methods for inspecting the pcode ops in the current instruction as a sequence.\nclass EmulatePcodeCache : public EmulateMemory {\n Translate *trans;\t\t///< The SLEIGH translator\n vector opcache;\t///< The cache of current p-code ops\n vector varcache;\t///< The cache of current varnodes\n vector inst;\t///< Map from OpCode to OpBehavior\n BreakTable *breaktable;\t///< The table of breakpoints\n Address current_address;\t///< Address of current instruction being executed\n bool instruction_start;\t///< \\b true if next pcode op is start of instruction\n int4 current_op;\t\t///< Index of current pcode op within machine instruction\n int4 instruction_length;\t///< Length of current instruction in bytes\n void clearCache(void);\t///< Clear the p-code cache\n void createInstruction(const Address &addr); ///< Cache pcode for instruction at given address\n void establishOp(void);\nprotected:\n virtual void fallthruOp(void); ///< Execute fallthru semantics for the pcode cache\n virtual void executeBranch(void); ///< Execute branch (including relative branches)\n virtual void executeCallother(void); ///< Execute breakpoint for this user-defined op\npublic:\n EmulatePcodeCache(Translate *t,MemoryState *s,BreakTable *b);\t///< Pcode cache emulator constructor\n ~EmulatePcodeCache(void);\n bool isInstructionStart(void) const; ///< Return \\b true if we are at an instruction start\n int4 numCurrentOps(void) const; ///< Return number of pcode ops in translation of current instruction\n int4 getCurrentOpIndex(void) const; ///< Get the index of current pcode op within current instruction\n PcodeOpRaw *getOpByIndex(int4 i) const; ///< Get pcode op in current instruction translation by index\n virtual void setExecuteAddress(const Address &addr); ///< Set current execution address\n virtual Address getExecuteAddress(void) const; ///< Get current execution address\n void executeInstruction(void); ///< Execute (the rest of) a single machine instruction\n};\n\n/// Since the emulator can single step through individual pcode operations, the machine state\n/// may be halted in the \\e middle of a single machine instruction, unlike conventional debuggers.\n/// This routine can be used to determine if execution is actually at the beginning of a machine\n/// instruction.\n/// \\return \\b true if the next pcode operation is at the start of the instruction translation\ninline bool EmulatePcodeCache::isInstructionStart(void) const\n\n{\n return instruction_start;\n}\n\n/// A typical machine instruction translates into a sequence of pcode ops.\n/// \\return the number of ops in the sequence\ninline int4 EmulatePcodeCache::numCurrentOps(void) const\n\n{\n return opcache.size();\n}\n\n/// This routine can be used to determine where, within the sequence of ops in the translation\n/// of the entire machine instruction, the currently executing op is.\n/// \\return the index of the current (next) pcode op.\ninline int4 EmulatePcodeCache::getCurrentOpIndex(void) const\n\n{\n return current_op;\n}\n\n/// This routine can be used to examine ops other than the currently executing op in the\n/// machine instruction's translation sequence.\n/// \\param i is the desired op index\n/// \\return the pcode op at the indicated index\ninline PcodeOpRaw *EmulatePcodeCache::getOpByIndex(int4 i) const\n\n{\n return opcache[i];\n}\n\n/// \\return the currently executing machine address\ninline Address EmulatePcodeCache::getExecuteAddress(void) const\n\n{\n return current_address;\n}\n\n/** \\page sleighAPIemulate The SLEIGH Emulator\n \n \\section emu_overview Overview\n \n \\b SLEIGH provides a framework for emulating the processors which have a specification written\n for them. The key classes in this framework are:\n\n \\b Key \\b Classes\n - \\ref MemoryState\n - \\ref MemoryBank\n - \\ref BreakTable\n - \\ref BreakCallBack\n - \\ref Emulate\n - \\ref EmulatePcodeCache\n\n The MemoryState object holds the representation of registers and memory during emulation. It\n understands the address spaces defined in the \\b SLEIGH specification and how data is encoded\n in these spaces. It also knows any register names defined by the specification, so these\n can be used to set or query the state of these registers naturally.\n\n The emulation framework can be tailored to a particular environment by creating \\b breakpoint\n objects, which derive off the BreakCallBack interface. These can be used to create callbacks\n during emulation that have full access to the memory state and the emulator, so any action\n can be accomplished. The breakpoint callbacks can be designed to either augment or replace\n the instruction at a particular address, or the callback can be used to implement the action\n of a user-defined pcode op. The BreakCallBack objects are managed by the BreakTable object,\n which takes care of invoking the callback at the appropriate time.\n\n The Emulate object serves as a basic execution engine. Its main method is\n Emulate::executeCurrentOp() which executes a single pcode operation on the memory state.\n Methods exist for querying and setting the current execution address and examining the pcode\n op being executed.\n\n The main implementation of the Emulate interface is the EmulatePcodeCache object. It uses\n SLEIGH to translate machine instructions as they are executed. The currently executing instruction\n is translated into a cached sequence of pcode operations. Additional methods allow this entire\n sequence to be inspected, and there is another stepping function which allows the emulator\n to be stepped through an entire machine instruction at a time. The single pcode stepping methods\n are of course still available and the two methods can be used together without conflict.\n\n \\section emu_membuild Building a Memory State\n\n Assuming the SLEIGH Translate object and the LoadImage object have already been built\n (see \\ref sleighAPIbasic), the only required step left before instantiating an emulator\n is to create a MemoryState object. The MemoryState object can be instantiated simply by\n passing the constructor the Translate object, but before it will work properly, you need\n to register individual MemoryBank objects with it, for each address space that might\n get used by the emulator.\n\n A MemoryBank is a representation of data stored in a single address space\n There are some choices for the type of MemoryBank associated with an address space.\n A MemoryImage is a read-only memory bank that gets its data from a LoadImage. In order\n to make this writeable, or to create a writeable memory bank which starts with its bytes\n initialized to zero, you can use a MemoryHashOverlay or a MemoryPageOverlay.\n\n A MemoryHashOverlay overlays some other memory bank, such as a MemoryImage. If you read\n from a location that hasn't been written to directly before, you get the data in the underlying\n memory bank. But if you write to this overlay, the value is stored in a hash table, and\n subsequent reads will return this value. Internally, the hashtable stores values in a \\e preferred\n wordsize only on aligned addresses, but this is irrelevant to the interface. Unaligned requests\n are split up and handled transparently.\n\n A MemoryPageOverlay overlays another memory bank as well. But it implements writes to the bank\n by caching memory \\e pages. Any write creates an aligned page to hold the new data. The class\n takes care of loading and filling in pages as needed.\n\n Here is an example of instantiating a MemoryState and registering memory banks for a\n \\e ram space which is initialized with the load image. The \\e ram space is implemented\n with the MemoryPageOverlay, and the \\e register space and the \\e temporary space are implemented\n using the MemoryHashOverlay.\n\n \\code\n void setupMemoryState(Translate &trans,LoadImage &loader) {\n // Set up memory state object\n MemoryImage loadmemory(trans.getDefaultCodeSpace(),8,4096,&loader);\n MemoryPageOverlay ramstate(trans.getDefaultCodeSpace(),8,4096,&loadmemory);\n MemoryHashOverlay registerstate(trans.getSpaceByName(\"register\"),8,4096,4096,(MemoryBank *)0);\n MemoryHashOverlay tmpstate(trans.getUniqueSpace(),8,4096,4096,(MemoryBank *)0);\n\n MemoryState memstate(&trans);\t// Instantiate the memory state object\n memstate.setMemoryBank(&ramstate);\n memstate.setMemoryBank(®isterstate);\n memstate.setMemoryBank(&tmpstate);\n }\n \\endcode\n\n All the memory bank constructors need a preferred wordsize, which is most relevant to the hashtable\n implementation, and a page size, which is most relevant to the page implementation. The hash\n overlays need an additional initializer specifying how big the hashtable should be. The\n null pointers passed in, in place of a real memory bank, indicate that the memory bank is initialized\n with all zeroes. Once the memory banks are instantiated, they are registered with the memory state\n via the MemoryState::setMemoryBank() method.\n\n \\section emu_breakpoints Breakpoints\n\n In order to provide behavior within the emulator beyond just what the core instruction emulation\n provides, the framework supports \\b breakpoint classes. A breakpoint is created by deriving a\n class from the BreakCallBack class and overriding either BreakCallBack::addressCallback() or\n BreakCallBack::pcodeCallback(). Here is an example of a breakpoint that implements a\n standard C library \\e puts call an the x86 architecture. When the breakpoint is invoked,\n a call to \\e puts has just been made, so the stack pointer is pointing to the return address\n and the next 4 bytes on the stack are a pointer to the string being passed in.\n\n \\code\n class PutsCallBack : public BreakCallBack {\n public:\n virtual bool addressCallback(const Address &addr);\n };\n\n bool PutsCallBack::addressCallback(const Address &addr)\n\n {\n MemoryState *mem = emulate->getMemoryState();\n uint1 buffer[256];\n uint4 esp = mem->getValue(\"ESP\");\n AddrSpace *ram = mem->getTranslate()->getSpaceByName(\"ram\");\n\n uint4 param1 = mem->getValue(ram,esp+4,4);\n mem->getChunk(buffer,ram,param1,255);\n\n cout << (char *)&buffer << endl;\n\n uint4 returnaddr = mem->getValue(ram,esp,4);\n mem->setValue(\"ESP\",esp+8);\n emulate->setExecuteAddress(Address(ram,returnaddr));\n \n return true;\t\t\t// This replaces the indicated instruction\n }\n \n \\endcode\n\n Notice that the callback retrieves the value of the stack pointer by name. Using this\n value, the string pointer is retrieved, then the data for the actual string is retrieved.\n After dumping the string to standard out, the return address is recovered and the \\e return\n instruction is emulated by explicitly setting the next execution address to be the return value.\n\n \\section emu_finalsetup Running the Emulator\n Here is an example of instantiating an EmulatePcodeCache object. A breakpoint is also instantiated\n and registered with the BreakTable. \n\n \\code\n ...\n Sleigh trans(&loader,&context); // Instantiate the translator\n ...\n MemoryState memstate(&trans); // Instantiate the memory state\n ...\n BreakTableCallBack breaktable(&trans); // Instantiate a breakpoint table\n EmulatePcodeCache emulator(&trans,&memstate,&breaktable); // Instantiate the emulator\n\n // Set up the initial stack pointer\n memstate.setValue(\"ESP\",0xbffffffc);\n emulator.setExecuteAddress(Address(trans.getDefaultCodeSpace(),0x1D00114)); // Initial execution address\n \n PutsCallBack putscallback;\n breaktable.registerAddressCallback(Address(trans.getDefaultCodeSpace(),0x1D00130),&putscallback);\n\n AssemblyRaw assememit;\n for(;;) {\n Address addr = emulator.getExecuteAddress();\n trans.printAssembly(assememit,addr);\n emulator.executeInstruction();\n }\n\n \\endcode\n\n Notice how the initial stack pointer and initial execute address is set up. The breakpoint\n is registered with the BreakTable, giving it a specific address. The executeInstruction method\n is called inside the loop, to actually run the emulator. Notice that a disassembly of each\n instruction is printed after each step of the emulator.\n\n Other information can be examined from within this execution loop or in other tailored breakpoints.\n In particular, the Emulate::getCurrentOp() method can be used to retrieve the an instance\n of the currently executing pcode operation. From this starting point, you can examine the\n low-level objects:\n - PcodeOpRaw and\n - VarnodeData\n */\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/error.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file error.hh\n/// \\brief Base class for error handling facilities\n///\n/// This is also doubles as a place to list the common include files\n\n#ifndef __ERROR_HH__\n#define __ERROR_HH__\n\n#include \"types.h\"\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nnamespace ghidra {\n\nusing std::string;\nusing std::map;\nusing std::set;\nusing std::list;\nusing std::vector;\nusing std::pair;\nusing std::make_pair;\nusing std::ostream;\nusing std::istream;\nusing std::ifstream;\nusing std::ofstream;\nusing std::istringstream;\nusing std::ostringstream;\nusing std::ios;\nusing std::dec;\nusing std::hex;\nusing std::oct;\nusing std::setfill;\nusing std::fixed;\nusing std::setprecision;\nusing std::setw;\nusing std::endl;\nusing std::ws;\nusing std::min;\nusing std::max;\nusing std::to_string;\nusing std::piecewise_construct;\nusing std::forward_as_tuple;\n\n\n/// \\brief The lowest level error generated by the decompiler\n///\n/// This is the base error for all exceptions thrown by the\n/// decompiler. This underived form is thrown for very low\n/// level errors that immediately abort decompilation (usually\n/// for just a single function).\nstruct LowlevelError {\n string explain;\t\t///< Explanatory string\n /// Initialize the error with an explanatory string\n LowlevelError(const string &s) { explain = s; }\n\n const char *what() { return explain.c_str(); }\n};\n\n/// \\brief A generic recoverable error\n///\n/// This error is the most basic form of recoverable error,\n/// meaning there is some problem that the user did not take\n/// into account.\nstruct RecovError : public LowlevelError {\n /// Initialize the error with an explanatory string\n RecovError(const string &s) : LowlevelError(s) {}\n};\n\n/// \\brief An error generated while parsing a command or language\n///\n/// This error is generated when parsing character data of some\n/// form, as in a user command from the console or when parsing\n/// C syntax.\nstruct ParseError : public LowlevelError { // Parsing error\n /// Initialize the error with an explanatory string\n ParseError(const string &s) : LowlevelError(s) {}\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/filemanage.cc", "content": "/* ###\n * IP: GHIDRA\n * NOTE: Calls to Windows APIs\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"filemanage.hh\"\n\n#ifdef _WINDOWS\n#include \n\n#else\n// POSIX functions for searching directories\nextern \"C\" {\n#include \n#include \n#include \n#include \n}\n#endif\n\nnamespace ghidra {\n\n// Path name separator\n#ifdef _WINDOWS\nchar FileManage::separator = '\\\\';\nchar FileManage::separatorClass[] = \"/\\\\\";\n#else\nchar FileManage::separator = '/';\nchar FileManage::separatorClass[] = \"/\";\n#endif\n\nvoid FileManage::addDir2Path(const string &path)\n\n{\n if (path.size()>0) {\n pathlist.push_back(path);\n if (!isSeparator(path[path.size()-1]))\n pathlist.back() += separator;\n }\n}\n\nvoid FileManage::findFile(string &res,const string &name) const\n\n{\t\t\t\t// Search through paths to find file with given name\n vector::const_iterator iter;\n\n if (isSeparator(name[0])) {\n res = name;\n ifstream s(res.c_str());\n if (s) {\n s.close();\n return;\n }\n }\n else {\n for(iter=pathlist.begin();iter!=pathlist.end();++iter) {\n res = *iter + name;\n ifstream s(res.c_str());\n if (s) {\n\ts.close();\n\treturn;\n }\n }\n }\n res.clear();\t\t\t// Can't find it, return empty string\n}\n\n#ifdef _WINDOWS\nvoid FileManage::addCurrentDir(void)\n\n{\n char dirname[256];\n \n if (0!=GetCurrentDirectoryA(256,dirname)) {\n string filename(dirname);\n addDir2Path(filename);\n }\n}\n\n#else\nvoid FileManage::addCurrentDir(void)\n\n{\t\t\t\t// Add current working directory to path\n char dirname[256];\n char *buf;\n\n buf = getcwd(dirname,256);\n if ((char *)0 == buf) return;\n string filename(buf);\n addDir2Path(filename);\n}\n#endif\n\n#ifdef _WINDOWS\nbool FileManage::isDirectory(const string &path)\n\n{\n DWORD attribs = GetFileAttributes(path.c_str());\n if (attribs == INVALID_FILE_ATTRIBUTES) return false;\n return ((attribs & FILE_ATTRIBUTE_DIRECTORY)!=0);\n}\n\n#else\nbool FileManage::isDirectory(const string &path)\n\n{\n struct stat buf;\n if (stat(path.c_str(),&buf) < 0) {\n return false;\n }\n return S_ISDIR(buf.st_mode);\n}\n\n#endif\n\n#ifdef _WINDOWS\nbool FileManage::isSeparator(char c)\n\n{\n return (c == '/' || c == '\\\\');\n}\n\n#else\nbool FileManage::isSeparator(char c)\n\n{\n return c == separator;\n}\n\n#endif\n\n#ifdef _WINDOWS\nvoid FileManage::matchListDir(vector &res,const string &match,bool isSuffix,const string &dirname,bool allowdot)\n\n{\n WIN32_FIND_DATAA FindFileData;\n HANDLE hFind;\n string dirfinal;\n\n dirfinal = dirname;\n if (!isSeparator(dirfinal[dirfinal.size()-1]))\n dirfinal += separator;\n string regex = dirfinal + '*';\n\n hFind = FindFirstFileA(regex.c_str(),&FindFileData);\n if (hFind == INVALID_HANDLE_VALUE) return;\n do {\n string fullname(FindFileData.cFileName);\n if (match.size() <= fullname.size()) {\n if (allowdot||(fullname[0] != '.')) {\n\tif (isSuffix) {\n\t if (0==fullname.compare(fullname.size()-match.size(),match.size(),match))\n\t res.push_back(dirfinal + fullname);\n\t}\n\telse {\n\t if (0==fullname.compare(0,match.size(),match))\n\t res.push_back(dirfinal + fullname);\n\t}\n }\n }\n } while(0!=FindNextFileA(hFind,&FindFileData));\n FindClose(hFind);\n}\n\n#else\nvoid FileManage::matchListDir(vector &res,const string &match,bool isSuffix,const string &dirname,bool allowdot)\n\n{\t\t\t\t// Look through files in a directory for those matching -match-\n DIR *dir;\n struct dirent *entry;\n string dirfinal = dirname;\n if (!isSeparator(dirfinal[dirfinal.size()-1]))\n dirfinal += separator;\n\n dir = opendir(dirfinal.c_str());\n if (dir == (DIR *)0) return;\n entry = readdir(dir);\n while(entry != (struct dirent *)0) {\n string fullname(entry->d_name);\n if (match.size() <= fullname.size()) {\n if (allowdot||(fullname[0] != '.')) {\n\tif (isSuffix) {\n\t if (0==fullname.compare( fullname.size()-match.size(),match.size(),match))\n\t res.push_back( dirfinal + fullname );\n\t}\n\telse {\n\t if (0==fullname.compare(0,match.size(),match))\n\t res.push_back(dirfinal + fullname);\n\t}\n }\n }\n entry = readdir(dir);\n }\n closedir(dir);\n}\n#endif\n\nvoid FileManage::matchList(vector &res,const string &match,bool isSuffix) const\n\n{\n vector::const_iterator iter;\n\n for(iter=pathlist.begin();iter!=pathlist.end();++iter)\n matchListDir(res,match,isSuffix,*iter,false);\n}\n\n#ifdef _WINDOWS\n\nvoid FileManage::directoryList(vector &res,const string &dirname,bool allowdot)\n\n{\n WIN32_FIND_DATAA FindFileData;\n HANDLE hFind;\n string dirfinal = dirname;\n if (!isSeparator(dirfinal[dirfinal.size()-1]))\n dirfinal += separator;\n string regex = dirfinal + \"*\";\n const char *s = regex.c_str();\n \n\n hFind = FindFirstFileA(s,&FindFileData);\n if (hFind == INVALID_HANDLE_VALUE) return;\n do {\n if ( (FindFileData.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == FILE_ATTRIBUTE_DIRECTORY ) {\n string fullname(FindFileData.cFileName);\n if (allowdot || (fullname[0] != '.'))\n\tres.push_back(dirfinal + fullname);\n }\n } while(0!=FindNextFileA(hFind,&FindFileData));\n FindClose(hFind);\n}\n\n#else\nvoid FileManage::directoryList(vector &res,const string &dirname,bool allowdot)\n\n{ // List full pathnames of all directories under the directory -dir-\n DIR *dir;\n struct dirent *entry;\n string dirfinal;\n\n dirfinal = dirname;\n if (!isSeparator(dirfinal[dirfinal.size()-1]))\n dirfinal += separator;\n\n dir = opendir(dirfinal.c_str());\n if (dir == (DIR *)0) return;\n entry = readdir(dir);\n while(entry != (struct dirent *)0) {\n bool isDirectory = false;\n if (entry->d_type == DT_DIR)\n isDirectory = true;\n else if (entry->d_type == DT_UNKNOWN || entry->d_type == DT_LNK) {\n string path = dirfinal + entry->d_name;\n struct stat stbuf;\n stat(path.c_str(), &stbuf);\n isDirectory = S_ISDIR(stbuf.st_mode);\n }\n if (isDirectory) {\n string fullname(entry->d_name);\n if ((fullname!=\".\")&&(fullname!=\"..\")) {\n\tif (allowdot || (fullname[0] != '.'))\n\t res.push_back( dirfinal + fullname );\n }\n }\n entry = readdir(dir);\n }\n closedir(dir);\n}\n\n#endif\n\nvoid FileManage::scanDirectoryRecursive(vector &res,const string &matchname,const string &rootpath,int maxdepth)\n\n{\n if (maxdepth == 0) return;\n vector subdir;\n directoryList(subdir,rootpath);\n vector::const_iterator iter;\n for(iter = subdir.begin();iter!=subdir.end();++iter) {\n const string &curpath( *iter );\n string::size_type pos = curpath.find_last_of(separatorClass);\n if (pos == string::npos)\n pos = 0;\n else\n pos = pos + 1;\n if (curpath.compare(pos,string::npos,matchname)==0)\n res.push_back(curpath);\n else\n scanDirectoryRecursive(res,matchname,curpath,maxdepth-1); // Recurse\n }\n}\n\nvoid FileManage::splitPath(const string &full,string &path,string &base)\n\n{ // Split path string -full- into its -base-name and -path- (relative or absolute)\n // If there is no path, i.e. only a basename in full, then -path- will return as an empty string\n // otherwise -path- will be non-empty and end in a separator character\n string::size_type end = full.size()-1;\n if (isSeparator(full[full.size()-1])) // Take into account terminating separator\n end = full.size()-2;\n string::size_type pos = full.find_last_of(separatorClass,end);\n if (pos == string::npos) {\t// Didn't find any separator\n base = full;\n path.clear();\n }\n else {\n string::size_type sz = (end - pos);\n base = full.substr(pos+1,sz);\n path = full.substr(0,pos+1);\n }\n}\n\nstring FileManage::buildPath(const vector &pathels,int level)\n\n{ // Build an absolute path using elements from -pathels-, in reverse order\n // Build up to and including pathels[level]\n ostringstream s;\n\n for(int i=pathels.size()-1;i>=level;--i) {\n s << separator;\n s << pathels[i];\n }\n return s.str();\n}\n\nbool FileManage::testDevelopmentPath(const vector &pathels,int level,string &root)\n\n{ // Given pathels[level] is \"Ghidra\", determine if this is a Ghidra development layout\n if (level + 2 >= pathels.size()) return false;\n string parent = pathels[level + 1];\n if (parent.size() < 11) return false;\n string piecestr = parent.substr(0,7);\n if (piecestr != \"ghidra.\") return false;\n piecestr = parent.substr(parent.size() - 4);\n if (piecestr != \".git\") return false;\n root = buildPath(pathels,level+2);\n vector testpaths1;\n vector testpaths2;\n scanDirectoryRecursive(testpaths1,\"ghidra.git\",root,1);\n if (testpaths1.size() != 1) return false;\n scanDirectoryRecursive(testpaths2,\"Ghidra\",testpaths1[0],1);\n return (testpaths2.size() == 1);\n}\n\nbool FileManage::testInstallPath(const vector &pathels,int level,string &root)\n\n{\n if (level + 1 >= pathels.size()) return false;\n root = buildPath(pathels,level+1);\n vector testpaths1;\n vector testpaths2;\n scanDirectoryRecursive(testpaths1,\"server\",root,1);\n if (testpaths1.size() != 1) return false;\n scanDirectoryRecursive(testpaths2,\"server.conf\",testpaths1[0],1);\n return (testpaths2.size() == 1);\n}\n\nstring FileManage::discoverGhidraRoot(const char *argv0)\n\n{ // Find the root of the ghidra distribution based on current working directory and passed in path\n vector pathels;\n string cur(argv0);\n string base;\n int skiplevel = 0;\n bool isAbs = isAbsolutePath(cur);\n\n for(;;) {\n int sizebefore = cur.size();\n splitPath(cur,cur,base);\n if (cur.size() == sizebefore) break;\n if (base == \".\")\n skiplevel += 1;\n else if (base == \"..\")\n skiplevel += 2;\n if (skiplevel > 0)\n skiplevel -= 1;\n else\n pathels.push_back(base);\n }\n if (!isAbs) {\n FileManage curdir;\n curdir.addCurrentDir();\n cur = curdir.pathlist[0];\n for(;;) {\n int sizebefore = cur.size();\n splitPath(cur,cur,base);\n if (cur.size() == sizebefore) break;\n pathels.push_back(base);\n }\n }\n\n for(int i=0;i\n#include \n#include \n#include \n#include \n\nnamespace ghidra {\n\nusing std::vector;\nusing std::string;\nusing std::ifstream;\nusing std::ostringstream;\n\nclass FileManage {\n vector pathlist;\t// List of paths to search for files\n static char separator;\n static char separatorClass[];\t// Characters that can be accepted as a separator\n static string buildPath(const vector &pathels,int level);\n static bool testDevelopmentPath(const vector &pathels,int level,string &root);\n static bool testInstallPath(const vector &pathels,int level,string &root);\npublic:\n void addDir2Path(const string &path);\n void addCurrentDir(void);\n void findFile(string &res,const string &name) const; // Resolve full pathname\n void matchList(vector &res,const string &match,bool isSuffix) const; // List of files with suffix\n static bool isSeparator(char c);\n static bool isDirectory(const string &path);\n static void matchListDir(vector &res,const string &match,bool isSuffix,const string &dir,bool allowdot);\n static void directoryList(vector &res,const string &dirname,bool allowdot=false);\n static void scanDirectoryRecursive(vector &res,const string &matchname,const string &rootpath,int maxdepth);\n static void splitPath(const string &full,string &path,string &base);\n static bool isAbsolutePath(const string &full) { if (full.empty()) return false; return (full[0] == separator); }\n static string discoverGhidraRoot(const char *argv0);\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/float.cc", "content": "/* ###\n * IP: GHIDRA\n * NOTE: uses some windows and sparc specific floating point definitions\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"float.hh\"\n#include \"address.hh\"\n\n#include \n#include \n\nnamespace ghidra {\n\nusing std::ldexp;\nusing std::frexp;\nusing std::signbit;\nusing std::sqrt;\nusing std::floor;\nusing std::ceil;\nusing std::round;\nusing std::fabs;\n\n/// Set format for a given encoding size according to IEEE 754 standards\n/// \\param sz is the size of the encoding in bytes\nFloatFormat::FloatFormat(int4 sz)\n\n{\n size = sz;\n\n if (size == 4) {\n signbit_pos = 31;\n exp_pos = 23;\n exp_size = 8;\n frac_pos = 0;\n frac_size = 23;\n bias = 127;\n jbitimplied = true;\n }\n else if (size == 8) {\n signbit_pos = 63;\n exp_pos = 52;\n exp_size = 11;\n frac_pos = 0;\n frac_size = 52;\n bias = 1023;\n jbitimplied = true;\n }\n maxexponent = (1<>= 1;\t\t // Throw away 1 bit of precision we will\n\t\t\t\t// lose anyway, to make sure highbit is 0\n int4 precis = 8*sizeof(uintb) - 1; // fullword - 1 we threw away\n double res = (double)signif;\n int4 expchange = exp - precis + 1; // change in exponent is precis\n\t\t\t\t// -1 integer bit\n res = ldexp(res,expchange);\n if (sign)\n res = res * -1.0;\n return res;\n}\n\n/// \\brief Extract the sign, fractional, and exponent from a given floating-point value\n///\n/// \\param x is the given value\n/// \\param sgn passes back the sign\n/// \\param signif passes back the fractional part\n/// \\param exp passes back the exponent\n/// \\return the floating-point class of the value\nFloatFormat::floatclass FloatFormat::extractExpSig(double x,bool *sgn,uintb *signif,int4 *exp)\n\n{\n int4 e;\n\n *sgn = signbit(x);\n if (x == 0.0) return zero;\n if (std::isinf(x)) return infinity;\n if (std::isnan(x)) return nan;\n if (*sgn)\n x = -x;\n double norm = frexp(x,&e); // norm is between 1/2 and 1\n norm = ldexp(norm,8*sizeof(uintb)-1); // norm between 2^62 and 2^63\n\n *signif = (uintb)norm; // Convert to normalized integer\n *signif <<= 1;\n\n e -= 1; // Consider normalization between 1 and 2\n *exp = e;\n return normalized;\n}\n\n/// \\param x is an encoded floating-point value\n/// \\return the fraction part of the value aligned to the top of the word\nuintb FloatFormat::extractFractionalCode(uintb x) const\n\n{\n x >>= frac_pos;\t\t// Eliminate bits below\n x <<= 8*sizeof(uintb) - frac_size; // Align with top of word\n return x;\n}\n\n/// \\param x is an encoded floating-point value\n/// \\return the sign bit\nbool FloatFormat::extractSign(uintb x) const\n\n{\n x >>= signbit_pos;\n return ((x&1)!=0);\n}\n\n/// \\param x is an encoded floating-point value\n/// \\return the (signed) exponent\nint4 FloatFormat::extractExponentCode(uintb x) const\n\n{\n x >>= exp_pos;\n uintb mask = 1;\n mask = (mask<>= 8*sizeof(uintb) - frac_size;\n code <<= frac_pos;\t\t// Move bits into position;\n x |= code;\n return x;\n}\n\n/// \\param x is an encoded value (with sign set to zero)\n/// \\param sign is the sign bit to set\n/// \\return the encoded value with the sign bit set\nuintb FloatFormat::setSign(uintb x,bool sign) const\n\n{\n if (!sign) return x;\t\t// Assume bit is already zero\n uintb mask = 1;\n mask <<= signbit_pos;\n x |= mask;\t\t\t// Stick in the bit\n return x;\n}\n\n/// \\param x is an encoded value (with exponent set to zero)\n/// \\param code is the exponent to set\n/// \\return the encoded value with the new exponent\nuintb FloatFormat::setExponentCode(uintb x,uintb code) const\n\n{\n code <<= exp_pos;\t\t// Move bits into position\n x |= code;\n return x;\n}\n\n/// \\param sgn is set to \\b true for negative zero, \\b false for positive\n/// \\return the encoded zero\nuintb FloatFormat::getZeroEncoding(bool sgn) const\n\n{\n uintb res = 0;\n // Use IEEE 754 standard for zero encoding\n res = setFractionalCode(res,0);\n res = setExponentCode(res,0);\n return setSign(res,sgn);\n}\n\n/// \\param sgn is set to \\b true for negative infinity, \\b false for positive\n/// \\return the encoded infinity\nuintb FloatFormat::getInfinityEncoding(bool sgn) const\n\n{\n uintb res = 0;\n // Use IEEE 754 standard for infinity encoding\n res = setFractionalCode(res,0);\n res = setExponentCode(res,(uintb)maxexponent);\n return setSign(res,sgn);\n}\n\n/// \\param sgn is set to \\b true for negative NaN, \\b false for positive\n/// \\return the encoded NaN\nuintb FloatFormat::getNaNEncoding(bool sgn) const\n\n{\n uintb res = 0;\n // Use IEEE 754 standard for NaN encoding\n uintb mask = 1;\n mask <<= 8*sizeof(uintb)-1;\t// Create \"quiet\" NaN\n res = setFractionalCode(res,mask);\n res = setExponentCode(res,(uintb)maxexponent);\n return setSign(res,sgn);\n}\n\nvoid FloatFormat::calcPrecision(void)\n\n{\n decimalMinPrecision = (int4)floor(frac_size * 0.30103);\n // Precision needed to guarantee IEEE 754 binary -> decimal -> binary round trip conversion\n decimalMaxPrecision = (int4)ceil((frac_size + 1) * 0.30103) + 1;\n}\n\n/// \\param encoding is the encoding value\n/// \\param type points to the floating-point class, which is passed back\n/// \\return the equivalent double value\ndouble FloatFormat::getHostFloat(uintb encoding,floatclass *type) const\n\n{\n bool sgn = extractSign(encoding);\n uintb frac = extractFractionalCode(encoding);\n int4 exp = extractExponentCode(encoding);\n bool normal = true;\n\n if (exp == 0) {\n if ( frac == 0 ) {\t\t// Floating point zero\n *type = zero;\n return sgn ? -0.0 : +0.0;\n }\n *type = denormalized;\n // Number is denormalized\n normal = false;\n }\n else if (exp == maxexponent) {\n if ( frac == 0 ) {\t\t// Floating point infinity\n *type = infinity;\n double infinity = std::numeric_limits::infinity();\n return sgn ? -infinity : +infinity;\n }\n *type = nan;\n // encoding is \"Not a Number\" NaN\n double nan = std::numeric_limits::quiet_NaN();\n return sgn ? -nan : +nan; // Sign is usually ignored\n }\n else\n *type = normalized;\n\n // Get \"true\" exponent and fractional\n exp -= bias;\n if (normal && jbitimplied) {\n frac >>= 1;\t\t\t// Make room for 1 jbit\n uintb highbit = 1;\n highbit <<= 8*sizeof(uintb)-1;\n frac |= highbit;\t\t// Stick bit in at top\n }\n return createFloat(sgn,frac,exp);\n}\n\n/// \\brief Round a floating point value to the nearest even\n///\n/// \\param signif the significant bits of a floating point value\n/// \\param lowbitpos the position in signif of the floating point\n/// \\return true if we rounded up\n\nbool FloatFormat::roundToNearestEven(uintb &signif, int4 lowbitpos)\n\n{\n uintb lowbitmask = (lowbitpos < 8 * sizeof(uintb)) ? ((uintb)1 << lowbitpos) : 0;\n uintb midbitmask = (uintb)1 << (lowbitpos - 1);\n uintb epsmask = midbitmask - 1;\n bool odd = (signif & lowbitmask) != 0;\n if ((signif & midbitmask) != 0 && ((signif & epsmask) != 0 || odd)) {\n signif += midbitmask;\n return true;\n }\n return false;\n}\n\n\n/// \\param host is the double value to convert\n/// \\return the equivalent encoded value\nuintb FloatFormat::getEncoding(double host) const\n\n{\n floatclass type;\n bool sgn;\n uintb signif;\n int4 exp;\n\n type = extractExpSig(host, &sgn, &signif, &exp);\n if (type == zero)\n return getZeroEncoding(sgn);\n else if (type == infinity)\n return getInfinityEncoding(sgn);\n else if (type == nan)\n return getNaNEncoding(sgn);\n\n // convert exponent and fractional to their encodings\n exp += bias;\n\n if (exp < -frac_size)\t// Exponent is too small to represent\n return getZeroEncoding(sgn); // TODO handle round to non-zero\n\n if (exp < 1) {\t// Must be denormalized\n if (roundToNearestEven(signif, 8 * sizeof(uintb) - frac_size - exp)) {\n // TODO handle round to normal case\n if ((signif >> (8 * sizeof(uintb) - 1)) == 0) {\n\tsignif = (uintb)1 << (8 * sizeof(uintb) - 1);\n\texp += 1;\n }\n }\n uintb res = getZeroEncoding(sgn);\n return setFractionalCode(res, signif >> (-exp));\n }\n\n if (roundToNearestEven(signif, 8 * sizeof(uintb) - frac_size - 1)) {\n // if high bit is clear, then the add overflowed. Increase exp and set\n // signif to 1.\n if ((signif >> (8 * sizeof(uintb) - 1)) == 0) {\n signif = (uintb)1 << (8 * sizeof(uintb) - 1);\n exp += 1;\n }\n }\n\n if (exp >= maxexponent)\t// Exponent is too big to represent\n return getInfinityEncoding(sgn);\n\n if (jbitimplied && (exp != 0))\n signif <<= 1;\t\t// Cut off top bit (which should be 1)\n\n uintb res = 0;\n res = setFractionalCode(res, signif);\n res = setExponentCode(res, (uintb)exp);\n return setSign(res, sgn);\n}\n\n\n/// \\param encoding is the value in the \\e other FloatFormat\n/// \\param formin is the \\e other FloatFormat\n/// \\return the equivalent value in \\b this FloatFormat\nuintb FloatFormat::convertEncoding(uintb encoding,\n\t\t\t\t const FloatFormat *formin) const\n\n{\n bool sgn = formin->extractSign(encoding);\n uintb signif = formin->extractFractionalCode(encoding);\n int4 exp = formin->extractExponentCode(encoding);\n\n if (exp == formin->maxexponent) { // NaN or INFINITY encoding\n exp = maxexponent;\n if (signif != 0)\n return getNaNEncoding(sgn);\n else\n return getInfinityEncoding(sgn);\n }\n\n if (exp == 0) { // incoming is subnormal\n if (signif == 0)\n return getZeroEncoding(sgn);\n\n // normalize\n int4 lz = count_leading_zeros(signif);\n signif <<= lz;\n exp = -formin->bias - lz;\n }\n else { // incoming is normal\n exp -= formin->bias;\n if (jbitimplied)\n signif = ((uintb)1 << (8 * sizeof(uintb) - 1)) | (signif >> 1);\n }\n\n exp += bias;\n\n if (exp < -frac_size)\t// Exponent is too small to represent\n return getZeroEncoding(sgn); // TODO handle round to non-zero\n\n if (exp < 1) {\t// Must be denormalized\n if (roundToNearestEven(signif, 8 * sizeof(uintb) - frac_size - exp)) {\n // TODO handle carry to normal case\n if ((signif >> (8 * sizeof(uintb) - 1)) == 0) {\n\tsignif = (uintb)1 << (8 * sizeof(uintb) - 1);\n\texp += 1;\n }\n }\n uintb res = getZeroEncoding(sgn);\n return setFractionalCode(res, signif >> (-exp));\n }\n\n if (roundToNearestEven(signif, 8 * sizeof(uintb) - frac_size - 1)) {\n // if high bit is clear, then the add overflowed. Increase exp and set\n // signif to 1.\n if ((signif >> (8 * sizeof(uintb) - 1)) == 0) {\n signif = (uintb)1 << (8 * sizeof(uintb) - 1);\n exp += 1;\n }\n }\n\n if (exp >= maxexponent)\t// Exponent is too big to represent\n return getInfinityEncoding(sgn);\n\n if (jbitimplied && (exp != 0))\n signif <<= 1;\t\t// Cut off top bit (which should be 1)\n\n uintb res = 0;\n res = setFractionalCode(res, signif);\n res = setExponentCode(res, (uintb)exp);\n return setSign(res, sgn);\n}\n\n/// The string should be printed with the minimum number of digits to uniquely specify the underlying\n/// binary value. This currently only works for the 32-bit and 64-bit IEEE 754 formats.\n/// If the \\b forcesci parameter is \\b true, the string will always be printed using scientific notation.\n/// \\param host is the given value already converted to the host's \\b double format.\n/// \\param forcesci is \\b true if the value should be printed in scientific notation.\n/// \\return the decimal representation as a string\nstring FloatFormat::printDecimal(double host,bool forcesci) const\n\n{\n string res;\n for(int4 prec=decimalMinPrecision;;++prec) {\n ostringstream s;\n if (forcesci) {\n s.setf( ios::scientific ); // Set to scientific notation\n s.precision(prec-1);\t// scientific doesn't include first digit in precision count\n }\n else {\n s.unsetf( ios::floatfield );\t// Use \"default\" notation to allow fewer digits to be printed if possible\n s.precision(prec);\n }\n s << host;\n if (prec == decimalMaxPrecision) {\n return s.str();\n }\n res = s.str();\n double roundtrip = 0.0;\n istringstream t(res);\n if (size <= 4) {\n float tmp = 0.0;\n t >> tmp;\n roundtrip = tmp;\n }\n else {\n t >> roundtrip;\n }\n if (roundtrip == host)\n break;\n }\n return res;\n}\n\n// Currently we emulate floating point operations on the target\n// By converting the encoding to the host's encoding and then\n// performing the operation using the host's floating point unit\n// then the host's encoding is converted back to the targets encoding\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return \\b true if (a == b)\nuintb FloatFormat::opEqual(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n uintb res = (val1 == val2) ? 1 : 0;\n return res;\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return \\b true if (a != b)\nuintb FloatFormat::opNotEqual(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n uintb res = (val1 != val2) ? 1 : 0;\n return res;\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return \\b true if (a < b)\nuintb FloatFormat::opLess(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n uintb res = (val1 < val2) ? 1 : 0;\n return res;\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return \\b true if (a <= b)\nuintb FloatFormat::opLessEqual(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n uintb res = (val1 <= val2) ? 1 : 0;\n return res;\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return \\b true if a is Not-a-Number\nuintb FloatFormat::opNan(uintb a) const\n\n{\n floatclass type;\n getHostFloat(a,&type);\n uintb res = (type == FloatFormat::nan) ? 1 : 0;\n return res;\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return a + b\nuintb FloatFormat::opAdd(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n return getEncoding(val1 + val2);\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return a / b\nuintb FloatFormat::opDiv(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n return getEncoding(val1 / val2);\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return a * b\nuintb FloatFormat::opMult(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n return getEncoding(val1 * val2);\n}\n\n/// \\param a is the first floating-point value\n/// \\param b is the second floating-point value\n/// \\return a - b\nuintb FloatFormat::opSub(uintb a,uintb b) const\n\n{\n floatclass type;\n double val1 = getHostFloat(a,&type);\n double val2 = getHostFloat(b,&type);\n return getEncoding(val1 - val2);\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return -a\nuintb FloatFormat::opNeg(uintb a) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n return getEncoding(-val);\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return abs(a)\nuintb FloatFormat::opAbs(uintb a) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n return getEncoding(fabs(val));\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return sqrt(a)\nuintb FloatFormat::opSqrt(uintb a) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n return getEncoding(sqrt(val));\n}\n\n/// \\param a is a signed integer value\n/// \\param sizein is the number of bytes in the integer encoding\n/// \\return a converted to an encoded floating-point value\nuintb FloatFormat::opInt2Float(uintb a,int4 sizein) const\n\n{\n intb ival = sign_extend(a,8*sizein-1);\n double val = (double) ival;\t// Convert integer to float\n return getEncoding(val);\n}\n\n/// \\param a is an encoded floating-point value\n/// \\param outformat is the desired output FloatFormat\n/// \\return a converted to the output FloatFormat\nuintb FloatFormat::opFloat2Float(uintb a,const FloatFormat &outformat) const\n\n{\n return outformat.convertEncoding(a, this);\n}\n\n/// \\param a is an encoded floating-point value\n/// \\param sizeout is the desired encoding size of the output\n/// \\return an integer encoding of a\nuintb FloatFormat::opTrunc(uintb a,int4 sizeout) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n intb ival = (intb) val;\t// Convert to integer\n uintb res = (uintb) ival;\t// Convert to unsigned\n res &= calc_mask(sizeout);\t// Truncate to proper size\n return res;\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return ceil(a)\nuintb FloatFormat::opCeil(uintb a) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n return getEncoding(ceil(val));\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return floor(a)\nuintb FloatFormat::opFloor(uintb a) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n return getEncoding(floor(val));\n}\n\n/// \\param a is an encoded floating-point value\n/// \\return round(a)\nuintb FloatFormat::opRound(uintb a) const\n\n{\n floatclass type;\n double val = getHostFloat(a,&type);\n // return getEncoding(floor(val+.5)); // round half up\n return getEncoding(round(val)); // round half away from zero\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/float.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file float.hh\n/// \\brief Support for decoding different floating-point formats\n\n#ifndef __FLOAT_HH__\n#define __FLOAT_HH__\n\n#include \"error.hh\"\n\nnamespace ghidra {\n\n/// \\brief Encoding information for a single floating-point format\n///\n/// This class supports manipulation of a single floating-point encoding.\n/// An encoding can be converted to and from the host format and\n/// convenience methods allow p-code floating-point operations to be\n/// performed on natively encoded operands. This follows the IEEE754 standards.\nclass FloatFormat {\npublic:\n /// \\brief The various classes of floating-point encodings\n enum floatclass {\n normalized = 0,\t\t///< A normal floating-point number\n infinity = 1,\t\t///< An encoding representing an infinite value\n zero = 2,\t\t\t///< An encoding of the value zero\n nan = 3,\t\t\t///< An invalid encoding, Not-a-Number\n denormalized = 4\t\t///< A denormalized encoding (for very small values)\n };\nprivate:\n int4 size;\t\t\t///< Size of float in bytes (this format)\n int4 signbit_pos;\t\t///< Bit position of sign bit\n int4 frac_pos;\t\t///< (lowest) bit position of fractional part\n int4 frac_size;\t\t///< Number of bits in fractional part\n int4 exp_pos;\t\t\t///< (lowest) bit position of exponent\n int4 exp_size;\t\t///< Number of bits in exponent\n int4 bias;\t\t\t///< What to add to real exponent to get encoding\n int4 maxexponent;\t\t///< Maximum possible exponent\n int4 decimalMinPrecision;\t///< Minimum decimal digits of precision guaranteed by the format\n int4 decimalMaxPrecision;\t///< Maximum decimal digits of precision needed to uniquely represent value\n bool jbitimplied;\t\t///< Set to \\b true if integer bit of 1 is assumed\n static double createFloat(bool sign,uintb signif,int4 exp);\t ///< Create a double given sign, fractional, and exponent\n static floatclass extractExpSig(double x,bool *sgn,uintb *signif,int4 *exp);\n static bool roundToNearestEven(uintb &signif, int4 lowbitpos);\n uintb setFractionalCode(uintb x,uintb code) const;\t\t///< Set the fractional part of an encoded value\n uintb setSign(uintb x,bool sign) const;\t\t\t///< Set the sign bit of an encoded value\n uintb setExponentCode(uintb x,uintb code) const;\t\t///< Set the exponent of an encoded value\n uintb getZeroEncoding(bool sgn) const;\t\t\t///< Get an encoded zero value\n uintb getInfinityEncoding(bool sgn) const;\t\t\t///< Get an encoded infinite value\n uintb getNaNEncoding(bool sgn) const;\t\t\t\t///< Get an encoded NaN value\n void calcPrecision(void);\t\t\t\t\t///< Calculate the decimal precision of this format\npublic:\n FloatFormat(int4 sz);\t///< Construct default IEEE 754 standard settings\n int4 getSize(void) const { return size; }\t\t\t///< Get the size of the encoding in bytes\n double getHostFloat(uintb encoding,floatclass *type) const;\t///< Convert an encoding into host's double\n uintb getEncoding(double host) const;\t\t\t\t///< Convert host's double into \\b this encoding\n uintb convertEncoding(uintb encoding,const FloatFormat *formin) const;\t///< Convert between two different formats\n\n uintb extractFractionalCode(uintb x) const;\t\t\t///< Extract the fractional part of the encoding\n bool extractSign(uintb x) const;\t\t\t\t///< Extract the sign bit from the encoding\n int4 extractExponentCode(uintb x) const;\t\t\t///< Extract the exponent from the encoding\n\n string printDecimal(double host,bool forcesci) const;\t\t///< Print given value as a decimal string\n\n // Operations on floating point values\n\n uintb opEqual(uintb a,uintb b) const;\t\t\t///< Equality comparison (==)\n uintb opNotEqual(uintb a,uintb b) const;\t\t///< Inequality comparison (!=)\n uintb opLess(uintb a,uintb b) const;\t\t\t///< Less-than comparison (<)\n uintb opLessEqual(uintb a,uintb b) const;\t\t///< Less-than-or-equal comparison (<=)\n uintb opNan(uintb a) const;\t\t\t\t///< Test if Not-a-Number (NaN)\n uintb opAdd(uintb a,uintb b) const;\t\t\t///< Addition (+)\n uintb opDiv(uintb a,uintb b) const;\t\t\t///< Division (/)\n uintb opMult(uintb a,uintb b) const;\t\t\t///< Multiplication (*)\n uintb opSub(uintb a,uintb b) const;\t\t\t///< Subtraction (-)\n uintb opNeg(uintb a) const;\t\t\t\t///< Unary negate\n uintb opAbs(uintb a) const;\t\t\t\t///< Absolute value (abs)\n uintb opSqrt(uintb a) const;\t\t\t\t///< Square root (sqrt)\n uintb opTrunc(uintb a,int4 sizeout) const;\t\t///< Convert floating-point to integer\n uintb opCeil(uintb a) const;\t\t\t\t///< Ceiling (ceil)\n uintb opFloor(uintb a) const;\t\t\t\t///< Floor (floor)\n uintb opRound(uintb a) const;\t\t\t\t///< Round\n uintb opInt2Float(uintb a,int4 sizein) const;\t\t///< Convert integer to floating-point\n uintb opFloat2Float(uintb a,const FloatFormat &outformat) const;\t///< Convert between floating-point precisions\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/globalcontext.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"globalcontext.hh\"\n\nnamespace ghidra {\n\nElementId ELEM_CONTEXT_DATA = ElementId(\"context_data\",120);\nElementId ELEM_CONTEXT_POINTS = ElementId(\"context_points\",121);\nElementId ELEM_CONTEXT_POINTSET = ElementId(\"context_pointset\",122);\nElementId ELEM_CONTEXT_SET = ElementId(\"context_set\",123);\nElementId ELEM_SET = ElementId(\"set\",124);\nElementId ELEM_TRACKED_POINTSET = ElementId(\"tracked_pointset\",125);\nElementId ELEM_TRACKED_SET = ElementId(\"tracked_set\",126);\n\n/// Bits within the whole context blob are labeled starting with 0 as the most significant bit\n/// in the first word in the sequence. The new context value must be contained within a single\n/// word.\n/// \\param sbit is the starting (most significant) bit of the new value\n/// \\param ebit is the ending (least significant) bit of the new value\nContextBitRange::ContextBitRange(int4 sbit,int4 ebit)\n\n{\n word = sbit/(8*sizeof(uintm));\n startbit = sbit - word*8*sizeof(uintm);\n endbit = ebit - word*8*sizeof(uintm);\n shift = 8*sizeof(uintm)-endbit-1;\n mask = (~((uintm)0))>>(startbit+shift);\n}\n\n/// The register storage and value are encoded as a \\ element.\n/// \\param encoder is the stream encoder\nvoid TrackedContext::encode(Encoder &encoder) const\n\n{\n encoder.openElement(ELEM_SET);\n loc.space->encodeAttributes(encoder,loc.offset,loc.size);\n encoder.writeUnsignedInteger(ATTRIB_VAL, val);\n encoder.closeElement(ELEM_SET);\n}\n\n/// Parse a \\ element to fill in the storage and value details.\n/// \\param decoder is the stream decoder\nvoid TrackedContext::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_SET);\n loc.decodeFromAttributes(decoder);\n\n val = decoder.readUnsignedInteger(ATTRIB_VAL);\n decoder.closeElement(elemId);\n}\n\n/// \\brief Encode all tracked register values for a specific address to a stream\n///\n/// Encode all the tracked register values associated with a specific target address\n/// as a \\ tag.\n/// \\param encoder is the stream encoder\n/// \\param addr is the specific address we have tracked values for\n/// \\param vec is the list of tracked values\nvoid ContextDatabase::encodeTracked(Encoder &encoder,const Address &addr,const TrackedSet &vec)\n\n{\n if (vec.empty()) return;\n encoder.openElement(ELEM_TRACKED_POINTSET);\n addr.getSpace()->encodeAttributes(encoder,addr.getOffset() );\n for(int4 i=0;i element, decoding each child in turn to populate a list of\n/// TrackedContext objects.\n/// \\param decoder is the given stream decoder\n/// \\param vec is the container that will hold the new TrackedContext objects\nvoid ContextDatabase::decodeTracked(Decoder &decoder,TrackedSet &vec)\n\n{\n vec.clear();\t\t\t// Clear out any old stuff\n while(decoder.peekElement() != 0) {\n vec.emplace_back();\n vec.back().decode(decoder);\n }\n}\n\n/// The default value is returned for addresses that have not been overlaid with other values.\n/// \\param nm is the name of the context variable\n/// \\param val is the default value to establish\nvoid ContextDatabase::setVariableDefault(const string &nm,uintm val)\n\n{\n ContextBitRange &var( getVariable(nm) );\n var.setValue(getDefaultValue(),val);\n}\n\n/// This will return the default value used for addresses that have not been overlaid with other values.\n/// \\param nm is the name of the context variable\n/// \\return the variable's default value\nuintm ContextDatabase::getDefaultValue(const string &nm) const\n\n{\n const ContextBitRange &var( getVariable(nm) );\n return var.getValue(getDefaultValue());\n}\n\n/// The variable will be changed to the new value, starting at the given address up to the next\n/// point of change.\n/// \\param nm is the name of the context variable\n/// \\param addr is the given address\n/// \\param value is the new value to set\nvoid ContextDatabase::setVariable(const string &nm,const Address &addr,\n\t\t\t uintm value)\n{\n const ContextBitRange &bitrange( getVariable(nm) );\n int4 num = bitrange.getWord();\n uintm mask = bitrange.getMask()< contvec;\n getRegionToChangePoint(contvec,addr,num,mask);\n for(uint4 i=0;i contvec;\n getRegionToChangePoint(contvec,addr,num,mask);\n for(uint4 i=0;i vec;\n getRegionForSet(vec,addr1,addr2,num,mask);\n for(uint4 i=0;i vec;\n getRegionForSet(vec,begad,endad,bitrange.getWord(),bitrange.getMask() << bitrange.getShift());\n for(int4 i=0;i mem.offset) continue;\n tendoff = tcont.loc.offset + tcont.loc.size - 1;\n if (tendoff < endoff) continue;\n uintb res = tcont.val;\n // If we have proper containment, trim value based on endianness\n if (tcont.loc.space->isBigEndian()) {\n if (endoff != tendoff)\n\tres >>= (8* (tendoff - mem.offset));\n }\n else {\n if (mem.offset != tcont.loc.offset)\n\tres >>= (8* (mem.offset-tcont.loc.offset));\n }\n res &= calc_mask( mem.size ); // Final trim based on size\n return res;\n }\n return (uintb)0;\n}\n\n/// The \"array of words\" and mask array are resized to the given value. Old values are preserved,\n/// chopping off the last values, or appending zeroes, as needed.\n/// \\param sz is the new number of words to resize array to\nvoid ContextInternal::FreeArray::reset(int4 sz)\n\n{\n uintm *newarray = (uintm *)0;\n uintm *newmask = (uintm *)0;\n if (sz != 0) {\n newarray = new uintm[sz];\n newmask = new uintm[sz];\n int4 min;\n if (sz > size) {\n min = size;\n for(int4 i=min;i elements within a parent \\ element.\n/// \\param encoder is the stream encoder\n/// \\param addr is the address of the split point where the blob is valid\n/// \\param vec is the array of words holding the blob values\nvoid ContextInternal::encodeContext(Encoder &encoder,const Address &addr,const uintm *vec) const\n{\n encoder.openElement(ELEM_CONTEXT_POINTSET);\n addr.getSpace()->encodeAttributes(encoder,addr.getOffset() );\n map::const_iterator iter;\n for(iter=variables.begin();iter!=variables.end();++iter) {\n uintm val = (*iter).second.getValue(vec);\n encoder.openElement(ELEM_SET);\n encoder.writeString(ATTRIB_NAME, (*iter).first);\n encoder.writeUnsignedInteger(ATTRIB_VAL, val);\n encoder.closeElement(ELEM_SET);\n }\n encoder.closeElement(ELEM_CONTEXT_POINTSET);\n}\n\n/// \\brief Restore a context blob for given address range from a stream decoder\n///\n/// Parse either a \\ or \\ element. In either case,\n/// children are parsed to get context variable values. Then a context blob is\n/// reconstructed from the values. The new blob is added to the interval map based\n/// on the address range. If the start address is invalid, the default value of\n/// the context variables are painted. The second address can be invalid, if\n/// only a split point is known.\n/// \\param decoder is the stream decoder\n/// \\param addr1 is the starting address of the given range\n/// \\param addr2 is the ending address of the given range\nvoid ContextInternal::decodeContext(Decoder &decoder,const Address &addr1,const Address &addr2)\n\n{\n for(;;) {\n uint4 subId = decoder.openElement();\n if (subId != ELEM_SET) break;\n uintm val = decoder.readUnsignedInteger(ATTRIB_VAL);\n ContextBitRange &var(getVariable(decoder.readString(ATTRIB_NAME)));\n vector vec;\n if (addr1.isInvalid()) {\t\t// Invalid addr1, indicates we should set default value\n uintm *defaultBuffer = getDefaultValue();\n for(int4 i=0;i size) {\n size = sz;\n database.defaultValue().reset(size);\n }\n variables[nm] = bitrange;\n}\n\nContextBitRange &ContextInternal::getVariable(const string &nm)\n\n{\n map::iterator iter;\n\n iter = variables.find(nm);\n if (iter == variables.end())\n throw LowlevelError(\"Non-existent context variable: \"+nm);\n return (*iter).second;\n}\n\nconst ContextBitRange &ContextInternal::getVariable(const string &nm) const\n\n{\n map::const_iterator iter;\n\n iter = variables.find(nm);\n if (iter == variables.end())\n throw LowlevelError(\"Non-existent context variable: \"+nm);\n return (*iter).second;\n}\n\nconst uintm *ContextInternal::getContext(const Address &addr,\n\t\t\t\t\t uintb &first,uintb &last) const\n{\n int4 valid;\n Address before,after;\n const uintm *res = database.bounds(addr,before,after,valid).array;\n if (((valid&1)!=0)||(before.getSpace() != addr.getSpace()))\n first = 0;\n else\n first = before.getOffset();\n if (((valid&2)!=0)||(after.getSpace() != addr.getSpace()))\n last = addr.getSpace()->getHighest();\n else\n last = after.getOffset()-1;\n return res;\n}\n\nvoid ContextInternal::getRegionForSet(vector &res,const Address &addr1,const Address &addr2,\n\t\t\t\t int4 num,uintm mask)\n{\n database.split(addr1);\n partmap::iterator aiter,biter;\n\n aiter = database.begin(addr1);\n if (!addr2.isInvalid()) {\n database.split(addr2);\n biter = database.begin(addr2);\n }\n else\n biter = database.end();\n while(aiter != biter) {\n uintm *context = (*aiter).second.array;\n uintm *maskPtr = (*aiter).second.mask;\n res.push_back(context);\n maskPtr[num] |= mask;\t\t// Mark that this value is being definitely set\n ++aiter;\n }\n}\n\nvoid ContextInternal::getRegionToChangePoint(vector &res,const Address &addr,int4 num,uintm mask)\n\n{\n database.split(addr);\n partmap::iterator aiter,biter;\n uintm *maskArray,*vecArray;\n\n aiter = database.begin(addr);\n biter = database.end();\n if (aiter == biter) return;\n vecArray = (*aiter).second.array;\n res.push_back(vecArray);\n maskArray = (*aiter).second.mask;\n maskArray[num] |= mask;\n ++aiter;\n while(aiter != biter) {\n vecArray = (*aiter).second.array;\n maskArray = (*aiter).second.mask;\n if ((maskArray[num] & mask) != 0) break; // Reached point where this value was definitively set before\n res.push_back(vecArray);\n ++aiter;\n }\n}\n\nTrackedSet &ContextInternal::createSet(const Address &addr1,const Address &addr2)\n\n{\n TrackedSet &res(trackbase.clearRange(addr1,addr2));\n res.clear();\n return res;\n}\n\nvoid ContextInternal::encode(Encoder &encoder) const\n\n{\n if (database.empty() && trackbase.empty()) return;\n\n encoder.openElement(ELEM_CONTEXT_POINTS);\n\n partmap::const_iterator fiter,fenditer;\n fiter = database.begin();\n fenditer = database.end();\n for(;fiter!=fenditer;++fiter)\t// Save context at each changepoint\n encodeContext(encoder,(*fiter).first,(*fiter).second.array);\n \n partmap::const_iterator titer,tenditer;\n titer = trackbase.begin();\n tenditer = trackbase.end();\n for(;titer!=tenditer;++titer) \n encodeTracked(encoder,(*titer).first,(*titer).second);\n\n encoder.closeElement(ELEM_CONTEXT_POINTS);\n}\n\nvoid ContextInternal::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_CONTEXT_POINTS);\n for(;;) {\n uint4 subId = decoder.openElement();\n if (subId == 0) break;\n if (subId == ELEM_CONTEXT_POINTSET) {\n uint4 attribId = decoder.getNextAttributeId();\n decoder.rewindAttributes();\n if (attribId==0) {\n\tdecodeContext(decoder,Address(),Address());\t// Restore the default value\n }\n else {\n\tVarnodeData vData;\n\tvData.decodeFromAttributes(decoder);\n\tdecodeContext(decoder,vData.getAddr(),Address());\n }\n }\n else if (subId == ELEM_TRACKED_POINTSET) {\n VarnodeData vData;\n vData.decodeFromAttributes(decoder);\n decodeTracked(decoder,trackbase.split(vData.getAddr()) );\n }\n else\n throw LowlevelError(\"Bad tag\");\n decoder.closeElement(subId);\n }\n decoder.closeElement(elemId);\n}\n\nvoid ContextInternal::decodeFromSpec(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_CONTEXT_DATA);\n for(;;) {\n uint4 subId = decoder.openElement();\n if (subId == 0) break;\n Range range;\n range.decodeFromAttributes(decoder);\t// There MUST be a range\n Address addr1 = range.getFirstAddr();\n Address addr2 = range.getLastAddrOpen(decoder.getAddrSpaceManager());\n if (subId == ELEM_CONTEXT_SET) {\n decodeContext(decoder,addr1,addr2);\n }\n else if (subId == ELEM_TRACKED_SET) {\n decodeTracked(decoder,createSet(addr1,addr2));\n }\n else\n throw LowlevelError(\"Bad tag\");\n decoder.closeElement(subId);\n }\n decoder.closeElement(elemId);\n}\n\n/// \\param db is the context database that will be encapsulated\nContextCache::ContextCache(ContextDatabase *db)\n\n{\n database = db;\n curspace = (AddrSpace *)0;\t// Mark cache as invalid\n allowset = true;\n}\n\n/// Check if the address is in the current valid range. If it is, return the cached\n/// blob. Otherwise, make a call to the database and cache a new block and valid range.\n/// \\param addr is the given address\n/// \\param buf is where the blob should be stored\nvoid ContextCache::getContext(const Address &addr,uintm *buf) const\n\n{\n if ((addr.getSpace()!=curspace)||(first>addr.getOffset())||(lastgetContext(addr,first,last);\n }\n for(int4 i=0;igetContextSize();++i) \n buf[i] = context[i];\n}\n\n/// \\brief Change the value of a context variable at the given address with no bound\n///\n/// The context value is set starting at the given address and \\e paints memory up\n/// to the next explicit change point.\n/// \\param addr is the given starting address\n/// \\param num is the word index of the context variable\n/// \\param mask is the mask delimiting the context variable\n/// \\param value is the (already shifted) value to set\nvoid ContextCache::setContext(const Address &addr,int4 num,uintm mask,uintm value)\n\n{\n if (!allowset) return;\n database->setContextChangePoint(addr,num,mask,value);\n if ((addr.getSpace()==curspace)&&(first<=addr.getOffset())&&(last>=addr.getOffset()))\n curspace = (AddrSpace *)0;\t// Invalidate cache\n}\n\n/// \\brief Change the value of a context variable across an explicit address range\n///\n/// The context value is \\e painted across the range. The context variable is marked as\n/// explicitly changing at the starting address of the range.\n/// \\param addr1 is the starting address of the given range\n/// \\param addr2 is the ending address of the given range\n/// \\param num is the word index of the context variable\n/// \\param mask is the mask delimiting the context variable\n/// \\param value is the (already shifted) value to set\nvoid ContextCache::setContext(const Address &addr1,const Address &addr2,int4 num,uintm mask,uintm value)\n\n{\n if (!allowset) return;\n database->setContextRegion(addr1,addr2,num,mask,value);\n if ((addr1.getSpace()==curspace)&&(first<=addr1.getOffset())&&(last>=addr1.getOffset()))\n curspace = (AddrSpace *)0;\t// Invalidate cache\n if ((first<=addr2.getOffset())&&(last>=addr2.getOffset()))\n curspace = (AddrSpace *)0;\t// Invalidate cache\n if ((first>=addr1.getOffset())&&(first<=addr2.getOffset()))\n curspace = (AddrSpace *)0;\t// Invalidate cache\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/globalcontext.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __GLOBALCONTEXT_HH__\n#define __GLOBALCONTEXT_HH__\n\n/// \\file globalcontext.hh\n/// \\brief Utilities for getting address-based context to the disassembler and decompiler\n\n#include \"pcoderaw.hh\"\n#include \"partmap.hh\"\n\nnamespace ghidra {\n\nextern ElementId ELEM_CONTEXT_DATA;\t///< Marshaling element \\\nextern ElementId ELEM_CONTEXT_POINTS;\t///< Marshaling element \\\nextern ElementId ELEM_CONTEXT_POINTSET;\t///< Marshaling element \\\nextern ElementId ELEM_CONTEXT_SET;\t///< Marshaling element \\\nextern ElementId ELEM_SET;\t\t///< Marshaling element \\\nextern ElementId ELEM_TRACKED_POINTSET;\t///< Marshaling element \\\nextern ElementId ELEM_TRACKED_SET;\t///< Marshaling element \\\n\n/// \\brief Description of a context variable within the disassembly context \\e blob\n///\n/// Disassembly context is stored as individual (integer) values packed into a sequence of words. This class\n/// represents the info for encoding or decoding a single value within this sequence. A value is\n/// a contiguous range of bits within one context word. Size can range from 1 bit up to the size of a word.\nclass ContextBitRange {\n int4 word;\t\t///< Index of word containing this context value\n int4 startbit;\t///< Starting bit of the value within its word (0=most significant bit 1=least significant)\n int4 endbit;\t\t///< Ending bit of the value within its word\n int4 shift;\t\t///< Right-shift amount to apply when unpacking this value from its word\n uintm mask;\t\t///< Mask to apply (after shifting) when unpacking this value from its word\npublic:\n ContextBitRange(void) { }\t///< Construct an undefined bit range\n ContextBitRange(int4 sbit,int4 ebit);\t\t///< Construct a context value given an absolute bit range\n int4 getShift(void) const { return shift; }\t///< Return the shift-amount for \\b this value\n uintm getMask(void) const { return mask; }\t///< Return the mask for \\b this value\n int4 getWord(void) const { return word; }\t///< Return the word index for \\b this value\n\n /// \\brief Set \\b this value within a given context blob\n ///\n /// \\param vec is the given context blob to alter (as an array of uintm words)\n /// \\param val is the integer value to set\n void setValue(uintm *vec,uintm val) const {\n uintm newval = vec[word];\n newval &= ~(mask<>shift)&mask);\n }\n};\n\n/// \\brief A tracked register (Varnode) and the value it contains\n///\n/// This is the object returned when querying for tracked registers,\n/// via ContextDatabase::getTrackedSet(). It holds the storage details of the register and\n/// the actual value it holds at the point of the query.\nstruct TrackedContext {\n VarnodeData loc;\t///< Storage details of the register being tracked\n uintb val;\t\t///< The value of the register\n void decode(Decoder &decoder);\t\t\t///< Decode \\b this from a stream\n void encode(Encoder &encoder) const;\t\t\t///< Encode \\b this to a stream\n};\ntypedef vector TrackedSet;\t\t///< A set of tracked registers and their values (at one code point)\n\n/// \\brief An interface to a database of disassembly/decompiler \\b context information\n///\n/// \\b Context \\b information is a set of named variables that hold concrete values at specific\n/// addresses in the target executable being analyzed. A variable can hold different values at\n/// different addresses, but a specific value at a specific address never changes. Analysis recovers\n/// these values over time, populating this database, and querying this database lets analysis\n/// provides concrete values for memory locations in context.\n///\n/// Context variables come in two flavors:\n/// - \\b Low-level \\b context \\b variables:\n/// These can affect instruction decoding. These can be as small as a single bit and need to\n/// be defined in the Sleigh specification (so that Sleigh knows how they effect disassembly).\n/// These variables are not mapped to normal memory locations with an address space and offset\n/// (although they often have a corresponding embedding into a normal memory location).\n/// The model to keep in mind is a control register with specialized bit-fields within it.\n/// - \\b High-level \\b tracked \\b variables:\n/// These are normal memory locations that are to be treated as constants across some range of\n/// code. These are normally registers that are being tracked by the compiler outside the\n/// domain of normal local and global variables. They have a specific value established by\n/// the compiler coming into a function but are not supposed to be interpreted as a high-level\n/// variable. Typical examples are the direction flag (for \\e string instructions) and segment\n/// registers. All tracked variables are interpreted as a constant value at the start of a\n/// function, although the memory location can be recycled for other calculations later in the\n/// function.\n///\n/// Low-level context variables can be queried and set by name -- getVariable(), setVariable(),\n/// setVariableRegion() -- but the disassembler accesses all the variables at an address as a group\n/// via getContext(), setContextChangePoint(), setContextRegion(). In this setting, all the values\n/// are packed together in an array of words, a context \\e blob (See ContextBitRange).\n///\n/// Tracked variables are also queried as a group via getTrackedSet() and createSet(). These return\n/// a list of TrackedContext objects.\nclass ContextDatabase {\nprotected:\n static void encodeTracked(Encoder &encoder,const Address &addr,const TrackedSet &vec);\n static void decodeTracked(Decoder &decoder,TrackedSet &vec);\n\n /// \\brief Retrieve the context variable description object by name\n ///\n /// If the variable doesn't exist an exception is thrown.\n /// \\param nm is the name of the context value\n /// \\return the ContextBitRange object matching the name\n virtual ContextBitRange &getVariable(const string &nm)=0;\n\n /// \\brief Retrieve the context variable description object by name\n ///\n /// If the variable doesn't exist an exception is thrown.\n /// \\param nm is the name of the context value\n /// \\return the ContextBitRange object matching the name\n virtual const ContextBitRange &getVariable(const string &nm) const=0;\n\n /// \\brief Grab the context blob(s) for the given address range, marking bits that will be set\n ///\n /// This is an internal routine for obtaining the actual memory regions holding context values\n /// for the address range. This also informs the system which bits are getting set. A split is forced\n /// at the first address, and at least one memory region is passed back. The second address can be\n /// invalid in which case the memory region passed back is valid from the first address to whatever\n /// the next split point is.\n /// \\param res will hold pointers to memory regions for the given range\n /// \\param addr1 is the starting address of the range\n /// \\param addr2 is (1 past) the last address of the range or is invalid\n /// \\param num is the word index for the context value that will be set\n /// \\param mask is a mask of the value being set (within its word)\n virtual void getRegionForSet(vector &res,const Address &addr1,\n\t\t\t const Address &addr2,int4 num,uintm mask)=0;\n\n /// \\brief Grab the context blob(s) starting at the given address up to the first point of change\n ///\n /// This is an internal routine for obtaining the actual memory regions holding context values\n /// starting at the given address. A specific context value is specified, and all memory regions\n /// are returned up to the first address where that particular context value changes.\n /// \\param res will hold pointers to memory regions being passed back\n /// \\param addr is the starting address of the regions to fetch\n /// \\param num is the word index for the specific context value being set\n /// \\param mask is a mask of the context value being set (within its word)\n virtual void getRegionToChangePoint(vector &res,const Address &addr,int4 num,uintm mask)=0;\n\n /// \\brief Retrieve the memory region holding all default context values\n ///\n /// This fetches the active memory holding the default context values on top of which all other context\n /// values are overlaid.\n /// \\return the memory region holding all the default context values\n virtual uintm *getDefaultValue(void)=0;\n\n /// \\brief Retrieve the memory region holding all default context values\n ///\n /// This fetches the active memory holding the default context values on top of which all other context\n /// values are overlaid.\n /// \\return the memory region holding all the default context values\n virtual const uintm *getDefaultValue(void) const=0;\npublic:\n virtual ~ContextDatabase() {}\t\t\t///< Destructor\n\n /// \\brief Retrieve the number of words (uintm) in a context \\e blob\n ///\n /// \\return the number of words\n virtual int4 getContextSize(void) const=0;\n\n /// \\brief Register a new named context variable (as a bit range) with the database\n ///\n /// A new variable is registered by providing a name and the range of bits the value will occupy\n /// within the context blob. The full blob size is automatically increased if necessary. The variable\n /// must be contained within a single word, and all variables must be registered before any values can\n /// be set.\n /// \\param nm is the name of the new variable\n /// \\param sbit is the position of the variable's most significant bit within the blob\n /// \\param ebit is the position of the variable's least significant bit within the blob\n virtual void registerVariable(const string &nm,int4 sbit,int4 ebit)=0;\n\n /// \\brief Get the context blob of values associated with a given address\n ///\n /// \\param addr is the given address\n /// \\return the memory region holding the context values for the address\n virtual const uintm *getContext(const Address &addr) const=0;\n\n /// \\brief Get the context blob of values associated with a given address and its bounding offsets\n ///\n /// In addition to the memory region, the range of addresses for which the region is valid\n /// is passed back as offsets into the address space.\n /// \\param addr is the given address\n /// \\param first will hold the starting offset of the valid range\n /// \\param last will hold the ending offset of the valid range\n /// \\return the memory region holding the context values for the address\n virtual const uintm *getContext(const Address &addr,uintb &first,uintb &last) const=0;\n\n /// \\brief Get the set of default values for all tracked registers\n ///\n /// \\return the list of TrackedContext objects\n virtual TrackedSet &getTrackedDefault(void)=0;\n\n /// \\brief Get the set of tracked register values associated with the given address\n ///\n /// \\param addr is the given address\n /// \\return the list of TrackedContext objects\n virtual const TrackedSet &getTrackedSet(const Address &addr) const=0;\n\n /// \\brief Create a tracked register set that is valid over the given range\n ///\n /// This really should be an internal routine. The created set is empty, old values are blown\n /// away. If old/default values are to be preserved, they must be copied back in.\n /// \\param addr1 is the starting address of the given range\n /// \\param addr2 is (1 past) the ending address of the given range\n /// \\return the empty set of tracked register values\n virtual TrackedSet &createSet(const Address &addr1,const Address &addr2)=0;\n\n /// \\brief Encode the entire database to a stream\n ///\n /// \\param encoder is the stream encoder\n virtual void encode(Encoder &encoder) const=0;\n\n /// \\brief Restore the state of \\b this database object from the given stream decoder\n ///\n /// \\param decoder is the given stream decoder\n virtual void decode(Decoder &decoder)=0;\n\n /// \\brief Add initial context state from elements in the compiler/processor specifications\n ///\n /// Parse a \\ element from the given stream decoder from either the compiler\n /// or processor specification file for the architecture, initializing this database.\n /// \\param decoder is the given stream decoder\n virtual void decodeFromSpec(Decoder &decoder)=0;\n\n void setVariableDefault(const string &nm,uintm val);\t///< Provide a default value for a context variable\n uintm getDefaultValue(const string &nm) const;\t///< Retrieve the default value for a context variable\n void setVariable(const string &nm,const Address &addr,uintm value);\t///< Set a context value at the given address\n uintm getVariable(const string &nm,const Address &addr) const;\t///< Retrieve a context value at the given address\n void setContextChangePoint(const Address &addr,int4 num,uintm mask,uintm value);\n void setContextRegion(const Address &addr1,const Address &addr2,int4 num,uintm mask,uintm value);\n void setVariableRegion(const string &nm,const Address &begad,\n\t\t\t const Address &endad,uintm value);\n uintb getTrackedValue(const VarnodeData &mem,const Address &point) const;\n};\n\n/// \\brief An in-memory implementation of the ContextDatabase interface\n///\n/// Context blobs are held in a partition map on addresses. Any address within the map\n/// indicates a \\e split point, where the value of a context variable was explicitly changed.\n/// Sets of tracked registers are held in a separate partition map.\nclass ContextInternal : public ContextDatabase {\n\n /// \\brief A context blob, holding context values across some range of code addresses\n ///\n /// This is an internal object that allocates the actual \"array of words\" for a context blob.\n /// An associated mask array holds 1-bits for context variables that were explicitly set for the\n /// specific split point.\n struct FreeArray {\n uintm *array;\t\t///< The \"array of words\" holding context variable values\n uintm *mask;\t\t///< The mask array indicating which variables are explicitly set\n int4 size;\t\t\t///< The number of words in the array\n FreeArray(void) { size=0; array = (uintm *)0; mask = (uintm *)0; }\t///< Construct an empty context blob\n ~FreeArray(void) { if (size!=0) { delete [] array; delete [] mask; } }\t///< Destructor\n void reset(int4 sz);\t///< Resize the context blob, preserving old values\n FreeArray &operator=(const FreeArray &op2);\t///< Assignment operator\n };\n\n int4 size;\t\t\t///< Number of words in a context blob (for this architecture)\n map variables;\t\t///< Map from context variable name to description object\n partmap database;\t\t\t///< Partition map of context blobs (FreeArray)\n partmap trackbase;\t\t///< Partition map of tracked register sets\n void encodeContext(Encoder &encoder,const Address &addr,const uintm *vec) const;\n void decodeContext(Decoder &decoder,const Address &addr1,const Address &addr2);\n virtual ContextBitRange &getVariable(const string &nm);\n virtual const ContextBitRange &getVariable(const string &nm) const;\n virtual void getRegionForSet(vector &res,const Address &addr1,\n\t\t\t const Address &addr2,int4 num,uintm mask);\n virtual void getRegionToChangePoint(vector &res,const Address &addr,int4 num,uintm mask);\n virtual uintm *getDefaultValue(void) { return database.defaultValue().array; }\n virtual const uintm *getDefaultValue(void) const { return database.defaultValue().array; }\npublic:\n ContextInternal(void) { size = 0; }\n virtual ~ContextInternal(void) {}\n virtual int4 getContextSize(void) const { return size; }\n virtual void registerVariable(const string &nm,int4 sbit,int4 ebit);\n\n virtual const uintm *getContext(const Address &addr) const { return database.getValue(addr).array; }\n virtual const uintm *getContext(const Address &addr,uintb &first,uintb &last) const;\n\n virtual TrackedSet &getTrackedDefault(void) { return trackbase.defaultValue(); }\n virtual const TrackedSet &getTrackedSet(const Address &addr) const { return trackbase.getValue(addr); }\n virtual TrackedSet &createSet(const Address &addr1,const Address &addr2);\n\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder);\n virtual void decodeFromSpec(Decoder &decoder);\n};\n\n/// \\brief A helper class for caching the active context blob to minimize database lookups\n///\n/// This merely caches the last retrieved context blob (\"array of words\") and the range of\n/// addresses over which the blob is valid. It encapsulates the ContextDatabase itself and\n/// exposes a minimal interface (getContext() and setContext()).\nclass ContextCache {\n ContextDatabase *database;\t\t///< The encapsulated context database\n bool allowset;\t\t\t///< If set to \\b false, and setContext() call is dropped\n mutable AddrSpace *curspace;\t\t///< Address space of the current valid range\n mutable uintb first;\t\t\t///< Starting offset of the current valid range\n mutable uintb last;\t\t\t///< Ending offset of the current valid range\n mutable const uintm *context;\t\t///< The current cached context blob\npublic:\n ContextCache(ContextDatabase *db);\t///< Construct given a context database\n ContextDatabase *getDatabase(void) const { return database; }\t\t///< Retrieve the encapsulated database object\n void allowSet(bool val) { allowset = val; }\t\t///< Toggle whether setContext() calls are ignored\n void getContext(const Address &addr,uintm *buf) const;\t///< Retrieve the context blob for the given address\n void setContext(const Address &addr,int4 num,uintm mask,uintm value);\n void setContext(const Address &addr1,const Address &addr2,int4 num,uintm mask,uintm value);\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/loadimage.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"loadimage.hh\"\n\nnamespace ghidra {\n\n/// This is a convenience method wrapped around the core\n/// loadFill() routine. It automatically allocates an array\n/// of the desired size, and then fills it with load image data.\n/// If the array cannot be allocated, an exception is thrown.\n/// The caller assumes the responsibility of freeing the\n/// array after it has been used.\n/// \\param size is the number of bytes to read from the image\n/// \\param addr is the address of the first byte being read\n/// \\return a pointer to the desired bytes\nuint1 *LoadImage::load(int4 size,const Address &addr)\n\n{\n uint1 *buf = new uint1[ size ];\n if (buf == (uint1 *)0)\n throw LowlevelError(\"Out of memory\");\n loadFill(buf,size,addr);\n return buf;\n}\n\nRawLoadImage::RawLoadImage(const string &f) : LoadImage(f)\n\n{\n vma = 0;\n thefile = (ifstream *)0;\n spaceid = (AddrSpace *)0;\n filesize = 0;\n}\n\nRawLoadImage::~RawLoadImage(void)\n\n{\n if (thefile != (ifstream *)0) {\n thefile->close();\n delete thefile;\n }\n}\n\n/// The file is opened and its size immediately recovered.\nvoid RawLoadImage::open(void)\n\n{\n if (thefile != (ifstream *)0) throw LowlevelError(\"loadimage is already open\");\n thefile = new ifstream(filename.c_str());\n if (!(*thefile)) {\n string errmsg = \"Unable to open raw image file: \"+filename;\n throw LowlevelError(errmsg);\n }\n thefile->seekg(0,ios::end);\n filesize = thefile->tellg();\n}\n\nstring RawLoadImage::getArchType(void) const\n\n{\n return \"unknown\";\n}\n\nvoid RawLoadImage::adjustVma(long adjust)\n\n{\n adjust = AddrSpace::addressToByte(adjust,spaceid->getWordSize());\n vma += adjust;\n}\n\nvoid RawLoadImage::loadFill(uint1 *ptr,int4 size,const Address &addr)\n\n{\n uintb curaddr = addr.getOffset();\n uintb offset = 0;\n uintb readsize;\n\n curaddr -= vma;\t\t// Get relative offset of first byte\n while(size>0) {\n if (curaddr >= filesize) {\n if (offset == 0)\t\t// Initial address not within file\n\tbreak;\n memset(ptr+offset,0,size); // Fill out the rest of the buffer with 0\n return;\n }\n readsize = size;\n if (curaddr + readsize > filesize) // Adjust to biggest possible read\n readsize = filesize - curaddr;\n thefile->seekg(curaddr);\n thefile->read((char *)(ptr+offset),readsize);\n offset += readsize;\n size -= readsize;\n curaddr += readsize;\n }\n if (size > 0) {\n ostringstream errmsg;\n errmsg << \"Unable to load \" << dec << size << \" bytes at \" << addr.getShortcut();\n addr.printRaw(errmsg);\n throw DataUnavailError(errmsg.str());\n }\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/loadimage.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file loadimage.hh\n/// \\brief Classes and API for accessing a binary load image\n\n#ifndef __LOADIMAGE_HH__\n#define __LOADIMAGE_HH__\n\n#include \"address.hh\"\n\nnamespace ghidra {\n\n// XXX: On Windows, LoadImage is defined as a macro which conflicts with name\n// of the class declared in this file. For now, just undefine the macro.\n#ifdef _WINDOWS\n#ifdef LoadImage\n#undef LoadImage\n#endif\n#endif\n\n/// \\brief Exception indicating data was not available\n///\n/// This exception is thrown when a request for load image\n/// data cannot be met, usually because the requested address\n/// range is not in the image.\nstruct DataUnavailError : public LowlevelError {\n DataUnavailError(const string &s) : LowlevelError(s) {} ///< Instantiate with an explanatory string\n};\n\n/// \\brief A record indicating a function symbol\n///\n/// This is a lightweight object holding the Address and name of a function\nstruct LoadImageFunc {\n Address address;\t///< Start of function\n string name;\t\t///< Name of function\n};\n\n/// \\brief A record describing a section bytes in the executable\n///\n/// A lightweight object specifying the location and size of the section and basic properties\nstruct LoadImageSection {\n /// Boolean properties a section might have\n enum {\n unalloc = 1,\t\t///< Not allocated in memory (debug info)\n noload = 2,\t\t\t///< uninitialized section\n code = 4,\t\t\t///< code only\n data = 8,\t\t\t///< data only\n readonly = 16\t\t///< read only section\n };\n Address address;\t\t///< Starting address of section\n uintb size;\t\t\t///< Number of bytes in section\n uint4 flags;\t\t\t///< Properties of the section\n};\n\n/// \\brief An interface into a particular binary executable image\n///\n/// This class provides the abstraction needed by the decompiler\n/// for the numerous load file formats used to encode binary\n/// executables. The data encoding the machine instructions\n/// for the executable can be accessed via the addresses where\n/// that data would be loaded into RAM.\n/// Properties other than the main data and instructions of the\n/// binary are not supposed to repeatedly queried through this\n/// interface. This information is intended to be read from\n/// this class exactly once, during initialization, and used to\n/// populate the main decompiler database. This class currently\n/// has only rudimentary support for accessing such properties.\nclass LoadImage {\nprotected:\n string filename;\t\t///< Name of the loadimage\npublic:\n LoadImage(const string &f);\t///< LoadImage constructor\n virtual ~LoadImage(void);\t///< LoadImage destructor\n const string &getFileName(void) const; ///< Get the name of the LoadImage\n virtual void loadFill(uint1 *ptr,int4 size,const Address &addr)=0; ///< Get data from the LoadImage\n virtual void openSymbols(void) const; ///< Prepare to read symbols\n virtual void closeSymbols(void) const; ///< Stop reading symbols\n virtual bool getNextSymbol(LoadImageFunc &record) const; ///< Get the next symbol record\n virtual void openSectionInfo(void) const; ///< Prepare to read section info\n virtual void closeSectionInfo(void) const; ///< Stop reading section info\n virtual bool getNextSection(LoadImageSection &sec) const; ///< Get info on the next section\n virtual void getReadonly(RangeList &list) const; ///< Return list of \\e readonly address ranges\n virtual string getArchType(void) const=0; ///< Get a string indicating the architecture type\n virtual void adjustVma(long adjust)=0; ///< Adjust load addresses with a global offset\n uint1 *load(int4 size,const Address &addr);\t///< Load a chunk of image\n};\n\n/// \\brief A simple raw binary loadimage\n///\n/// This is probably the simplest loadimage. Bytes from the image are read directly from a file stream.\n/// The address associated with each byte is determined by a single value, the vma, which is the address\n/// of the first byte in the file. No symbols or sections are supported\nclass RawLoadImage : public LoadImage {\n uintb vma;\t\t\t///< Address of first byte in the file\n ifstream *thefile;\t\t///< Main file stream for image\n uintb filesize;\t\t///< Total number of bytes in the loadimage/file\n AddrSpace *spaceid;\t\t///< Address space that the file bytes are mapped to\npublic:\n RawLoadImage(const string &f); ///< RawLoadImage constructor\n void attachToSpace(AddrSpace *id) { spaceid = id; }\t///< Attach the raw image to a particular space\n void open(void);\t\t\t\t\t///< Open the raw file for reading\n virtual ~RawLoadImage(void);\t\t\t\t///< RawLoadImage destructor\n virtual void loadFill(uint1 *ptr,int4 size,const Address &addr);\n virtual string getArchType(void) const;\n virtual void adjustVma(long adjust);\n};\n\n/// For the base class there is no relevant initialization except\n/// the name of the image.\n/// \\param f is the name of the image\ninline LoadImage::LoadImage(const string &f) {\n filename = f;\n}\n\n/// The destructor for the load image object.\ninline LoadImage::~LoadImage(void) {\n}\n\n/// The loadimage is usually associated with a file. This routine\n/// retrieves the name as a string.\n/// \\return the name of the image\ninline const string &LoadImage::getFileName(void) const {\n return filename;\n}\n\n/// This routine should read in and parse any symbol information\n/// that the load image contains about executable. Once this\n/// method is called, individual symbol records are read out\n/// using the getNextSymbol() method.\ninline void LoadImage::openSymbols(void) const {\n}\n\n/// Once all the symbol information has been read out from the\n/// load image via the openSymbols() and getNextSymbol() calls,\n/// the application should call this method to free up resources\n/// used in parsing the symbol information.\ninline void LoadImage::closeSymbols(void) const {\n}\n\n/// This method is used to read out an individual symbol record,\n/// LoadImageFunc, from the load image. Right now, the only\n/// information that can be read out are function starts and the\n/// associated function name. This method can be called repeatedly\n/// to iterate through all the symbols, until it returns \\b false.\n/// This indicates the end of the symbols.\n/// \\param record is a reference to the symbol record to be filled in\n/// \\return \\b true if there are more records to read\ninline bool LoadImage::getNextSymbol(LoadImageFunc &record) const {\n return false;\n}\n\n/// This method initializes iteration over all the sections of\n/// bytes that are mapped by the load image. Once this is called,\n/// information on individual sections should be read out with\n/// the getNextSection() method.\ninline void LoadImage::openSectionInfo(void) const {\n}\n\n/// Once all the section information is read from the load image\n/// using the getNextSection() method, this method should be\n/// called to free up any resources used in parsing the section info.\ninline void LoadImage::closeSectionInfo(void) const {\n}\n\n/// This method is used to read out a record that describes a\n/// single section of bytes mapped by the load image. This\n/// method can be called repeatedly until it returns \\b false,\n/// to get info on additional sections.\n/// \\param record is a reference to the info record to be filled in\n/// \\return \\b true if there are more records to read\ninline bool LoadImage::getNextSection(LoadImageSection &record) const {\n return false;\n}\n\n/// This method should read out information about \\e all\n/// address ranges within the load image that are known to be\n/// \\b readonly. This method is intended to be called only\n/// once, so all information should be written to the passed\n/// RangeList object.\n/// \\param list is where readonly info will get put\ninline void LoadImage::getReadonly(RangeList &list) const {\n}\n\n/// \\fn void LoadImage::adjustVma(long adjust)\n/// Most load image formats automatically encode information\n/// about the true loading address(es) for the data in the image.\n/// But if this is missing or incorrect, this routine can be\n/// used to make a global adjustment to the load address. Only\n/// one adjustment is made across \\e all addresses in the image.\n/// The offset passed to this method is added to the stored\n/// or default value for any address queried in the image.\n/// This is most often used in a \\e raw binary file format. In\n/// this case, the entire executable file is intended to be\n/// read straight into RAM, as one contiguous chunk, in order to\n/// be executed. In the absence of any other info, the first\n/// byte of the image file is loaded at offset 0. This method\n/// then would adjust the load address of the first byte.\n/// \\param adjust is the offset amount to be added to default values\n\n/// \\fn string LoadImage::getArchType(void) const\n/// The load image class is intended to be a generic front-end\n/// to the large variety of load formats in use. This method\n/// should return a string that identifies the particular\n/// architecture this particular image is intended to run on.\n/// It is currently the responsibility of any derived LoadImage\n/// class to establish a format for this string, but it should\n/// generally contain some indication of the operating system\n/// and the processor.\n/// \\return the identifier string\n\n/// \\fn void LoadImage::loadFill(uint1 *ptr,int4 size,const Address &addr)\n/// This is the \\e core routine of a LoadImage. Given a particular\n/// address range, this routine retrieves the exact byte values\n/// that are stored at that address when the executable is loaded\n/// into RAM. The caller must supply a pre-allocated array\n/// of bytes where the returned bytes should be stored. If the\n/// requested address range does not exist in the image, or\n/// otherwise can't be retrieved, this method throws an\n/// DataUnavailError exception.\n/// \\param ptr points to where the resulting bytes will be stored\n/// \\param size is the number of bytes to retrieve from the image\n/// \\param addr is the starting address of the bytes to retrieve\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/loadimage_bfd.cc", "content": "/* ###\n * IP: GHIDRA\n * NOTE: Excluded from Build. Used for development only in support of console mode - Links to GNU BFD library which is GPL 3\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"loadimage_bfd.hh\"\n\nnamespace ghidra {\n\nint4 LoadImageBfd::bfdinit = 0;\t// Global initialization variable\n\nLoadImageBfd::LoadImageBfd(const string &f,const string &t) : LoadImage(f)\n\n{\n target = t;\n\n if (bfdinit == 0) {\n bfdinit = 1;\n bfd_init();\n }\n thebfd = (bfd *)0;\n spaceid = (AddrSpace *)0;\n symbol_table = (asymbol **)0;\n\n bufsize = 512;\t\t// Default buffer size\n bufoffset = ~((uintb)0);\n buffer = new uint1[ bufsize ];\n}\n\nLoadImageBfd::~LoadImageBfd(void)\n\n{\n if (symbol_table != (asymbol **)0)\n delete [] symbol_table;\n if (thebfd != (bfd *) 0)\n close();\n delete [] buffer;\n}\n\nstring LoadImageBfd::getArchType(void) const\n\n{\n string type;\n string targ;\n type = bfd_printable_name(thebfd);\n type += ':';\n targ = thebfd->xvec->name;\n type += targ;\n return type;\n}\n\nvoid LoadImageBfd::adjustVma(long adjust)\n\n{\n asection *s;\n adjust = AddrSpace::addressToByte(adjust,spaceid->getWordSize());\n for(s=thebfd->sections;s!=(asection *)NULL;s = s->next) {\n s->vma += adjust;\n s->lma += adjust;\n }\n}\n\nvoid LoadImageBfd::open(void)\n\n{\n if (thebfd != (bfd *)0) throw LowlevelError(\"BFD library did not initialize\");\n thebfd = bfd_openr(filename.c_str(),target.c_str());\n if (thebfd == (bfd *)0) {\n string errmsg=\"Unable to open image file: \";\n errmsg += filename;\n throw LowlevelError(errmsg);\n }\n if (!bfd_check_format( thebfd, bfd_object)) {\n string errmsg=\"File: \";\n errmsg += filename;\n errmsg += \" : not in recognized object file format\";\n throw LowlevelError(errmsg);\n }\n}\n\nvoid LoadImageBfd::close(void)\n\n{\n bfd_close(thebfd);\n thebfd = (bfd *)0;\n}\n\nasection *LoadImageBfd::findSection(uintb offset,uintb &secsize) const\n\n{ // Return section containing offset, or closest greater section\n asection *p;\n uintb start,stop;\n\n for(p = thebfd->sections; p != (asection *)NULL; p = p->next) {\n start = p->vma;\n secsize = (p->size!=0) ? p->size : p->rawsize;\n stop = start + secsize;\n if ((offset>=start)&&(offsetsections; p != (asection *)NULL; p = p->next) {\n if (p->vma > offset) {\n if (champ == (asection *)0)\n\tchamp = p;\n else if (p->vma < champ->vma)\n\tchamp = p;\n }\n }\n return champ;\n}\n\nvoid LoadImageBfd::loadFill(uint1 *ptr,int4 size,const Address &addr)\n\n{\n asection *p;\n uintb secsize;\n uintb curaddr,offset;\n bfd_size_type readsize;\n int4 cursize;\n\n if (addr.getSpace() != spaceid)\n throw DataUnavailError(\"Trying to get loadimage bytes from space: \"+addr.getSpace()->getName());\n curaddr = addr.getOffset();\n if ((curaddr>=bufoffset)&&(curaddr+size0) {\n p = findSection(curaddr,secsize);\n if (p == (asection *)0) {\n if (offset==0)\t\t// Initial address not mapped\n\tbreak;\n memset(buffer+offset,0,cursize); // Fill out the rest of the buffer with 0\n memcpy(ptr,buffer,size);\n return;\n }\n if (p->vma > curaddr) {\t// No section matches\n if (offset==0)\t\t// Initial address not mapped\n\tbreak;\n readsize = p->vma - curaddr;\n if (readsize > cursize)\n\treadsize = cursize;\n memset(buffer+offset,0,readsize); // Fill in with zeroes to next section\n }\n else {\n readsize = cursize;\n if (curaddr+readsize>p->vma+secsize)\t// Adjust to biggest possible read\n\treadsize = (bfd_size_type)(p->vma+secsize-curaddr);\n bfd_get_section_contents(thebfd,p,buffer+offset,(file_ptr)(curaddr-p->vma),readsize);\n }\n offset += readsize;\n cursize -= readsize;\n curaddr += readsize;\n }\n if (cursize > 0) {\n ostringstream errmsg;\n errmsg << \"Unable to load \" << dec << cursize << \" bytes at \" << addr.getShortcut();\n addr.printRaw(errmsg);\n throw DataUnavailError(errmsg.str());\n }\n memcpy(ptr,buffer,size);\t// Copy requested bytes from the buffer\n}\n\nvoid LoadImageBfd::advanceToNextSymbol(void) const\n\n{\n while(cursymbol < number_of_symbols) {\n const asymbol *a = symbol_table[cursymbol];\n if ((a->flags & BSF_FUNCTION)!=0) {\n if (a->name != (const char *)0)\n\treturn;\n }\n cursymbol += 1;\n }\n}\n\nvoid LoadImageBfd::openSymbols(void) const\n\n{\n long storage_needed;\n cursymbol = 0;\n if (symbol_table != (asymbol **)0) {\n advanceToNextSymbol();\n return;\n }\n\n if (!(bfd_get_file_flags(thebfd) & HAS_SYMS)) { // There are no symbols\n number_of_symbols = 0;\n return;\n }\n\n storage_needed = bfd_get_symtab_upper_bound(thebfd);\n if (storage_needed <= 0) {\n number_of_symbols = 0;\n return;\n }\n\n symbol_table = (asymbol **) new uint1[storage_needed]; // Storage needed in bytes\n number_of_symbols = bfd_canonicalize_symtab(thebfd,symbol_table);\n if (number_of_symbols <= 0) {\n delete [] symbol_table;\n symbol_table = (asymbol **)0;\n number_of_symbols = 0;\n return;\n }\n advanceToNextSymbol();\n // sort(symbol_table,symbol_table+number_of_symbols,compare_symbols);\n}\n\nbool LoadImageBfd::getNextSymbol(LoadImageFunc &record) const\n\n{ // Get record for next symbol if it exists, otherwise return false\n if (cursymbol >= number_of_symbols) return false;\n\n const asymbol *a = symbol_table[cursymbol];\n cursymbol += 1;\n advanceToNextSymbol();\n record.name = a->name;\n uintb val = bfd_asymbol_value(a);\n record.address = Address(spaceid,val);\n return true;\n}\n\nvoid LoadImageBfd::openSectionInfo(void) const\n\n{\n secinfoptr = thebfd->sections;\n}\n\nvoid LoadImageBfd::closeSectionInfo(void) const\n\n{\n secinfoptr = (asection *)0;\n}\n\nbool LoadImageBfd::getNextSection(LoadImageSection &record) const\n\n{\n if (secinfoptr == (asection *)0)\n return false;\n \n record.address = Address(spaceid,secinfoptr->vma);\n record.size = (secinfoptr->size!=0) ? secinfoptr->size : secinfoptr->rawsize;\n record.flags = 0;\n if ((secinfoptr->flags & SEC_ALLOC)==0)\n record.flags |= LoadImageSection::unalloc;\n if ((secinfoptr->flags & SEC_LOAD)==0)\n record.flags |= LoadImageSection::noload;\n if ((secinfoptr->flags & SEC_READONLY)!=0)\n record.flags |= LoadImageSection::readonly;\n if ((secinfoptr->flags & SEC_CODE)!=0)\n record.flags |= LoadImageSection::code;\n if ((secinfoptr->flags & SEC_DATA)!=0)\n record.flags |= LoadImageSection::data;\n secinfoptr = secinfoptr->next;\n return (secinfoptr != (asection *)0);\n}\n\nvoid LoadImageBfd::closeSymbols(void) const\n\n{\n if (symbol_table != (asymbol **)0)\n delete [] symbol_table;\n symbol_table = (asymbol **)0;\n number_of_symbols = 0;\n cursymbol = 0;\n}\n\nvoid LoadImageBfd::getReadonly(RangeList &list) const\n\n{ // List all ranges that are read only\n uintb start,stop,secsize;\n asection *p;\n\n for(p = thebfd->sections; p != (asection *)NULL; p = p->next) {\n if ((p->flags & SEC_READONLY)!=0) {\n start = p->vma;\n secsize = (p->size!=0) ? p->size : p->rawsize;\n if (secsize == 0) continue;\n stop = start + secsize - 1;\n list.insertRange(spaceid,start,stop);\n }\n }\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/loadimage_bfd.hh", "content": "/* ###\n * IP: GHIDRA\n * NOTE: Interface to GNU BFD library which is GPL 3\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// Use the GNU bfd library to manipulate a load image\n\n#ifndef __LOADIMAGE_BFD_HH__\n#define __LOADIMAGE_BFD_HH__\n\n#include \"loadimage.hh\"\n\n// bfd.h requires PACKAGE/PACKAGE_VERSION to be defined\n// https://sourceware.org/bugzilla/show_bug.cgi?id=14243\n\n#ifndef PACKAGE\n #define PACKAGE\n #define __LOADIMAGE_BFD__DEFINED_PACKAGE\n#endif\n\n#ifndef PACKAGE_VERSION\n #define PACKAGE_VERSION\n #define __LOADIMAGE_BFD__DEFINED_PACKAGE_VERSION\n#endif\n\n#include \n\n#ifdef __LOADIMAGE_BFD__DEFINED_PACKAGE\n #undef PACKAGE\n #undef __LOADIMAGE_BFD__DEFINED_PACKAGE\n#endif\n\n#ifdef __LOADIMAGE_BFD__DEFINED_PACKAGE_VERSION\n #undef PACKAGE_VERSION\n #undef __LOADIMAGE_BFD__DEFINED_PACKAGE_VERSION\n#endif\n\nnamespace ghidra {\n\nstruct ImportRecord {\n string dllname;\n string funcname;\n int ordinal;\n Address address;\n Address thunkaddress;\n};\n\nclass LoadImageBfd : public LoadImage {\n static int4 bfdinit;\t\t// Is the library (globally) initialized\n string target;\t\t// File format (supported by BFD)\n bfd *thebfd;\n AddrSpace *spaceid;\t\t// We need to map space id to segments but since\n\t\t\t\t// we are currently ignoring segments anyway...\n uintb bufoffset;\t\t// Starting offset of byte buffer\n uint4 bufsize;\t\t// Number of bytes in the buffer\n uint1 *buffer;\t\t// The actual buffer\n mutable asymbol **symbol_table;\n mutable long number_of_symbols;\n mutable long cursymbol;\n mutable asection *secinfoptr;\n asection *findSection(uintb offset,uintb &ssize) const; // Find section containing given offset\n void advanceToNextSymbol(void) const;\npublic:\n LoadImageBfd(const string &f,const string &t);\n void attachToSpace(AddrSpace *id) { spaceid = id; }\n void open(void);\t\t// Open any descriptors\n void close(void);\t\t// Close any descriptor\n void getImportTable(vector &irec) { throw LowlevelError(\"Not implemented\"); }\n virtual ~LoadImageBfd(void);\n virtual void loadFill(uint1 *ptr,int4 size,const Address &addr); // Load a chunk of image\n virtual void openSymbols(void) const;\n virtual void closeSymbols(void) const;\n virtual bool getNextSymbol(LoadImageFunc &record) const;\n virtual void openSectionInfo(void) const;\n virtual void closeSectionInfo(void) const;\n virtual bool getNextSection(LoadImageSection &sec) const;\n virtual void getReadonly(RangeList &list) const;\n virtual string getArchType(void) const;\n virtual void adjustVma(long adjust);\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/marshal.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"marshal.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nusing namespace PackedFormat;\n\nunordered_map AttributeId::lookupAttributeId;\n\nconst int4 PackedDecode::BUFFER_SIZE = 1024;\n\nconst char XmlEncode::spaces[] = \"\\n \";\nconst int4 XmlEncode::MAX_SPACES = 24+1;\n\n/// Access static vector of AttributeId objects that are registered during static initialization\n/// The list itself is created once on the first call to this method.\n/// \\return a reference to the vector\nvector &AttributeId::getList(void)\n\n{\n static vector thelist;\n return thelist;\n}\n\n/// This constructor should only be invoked for static objects. It registers the attribute for inclusion\n/// in the global hashtable.\n/// \\param nm is the name of the attribute\n/// \\param i is an id to associate with the attribute\n/// \\param scope is an id for the scope of this attribute\nAttributeId::AttributeId(const string &nm,uint4 i,int4 scope)\n : name(nm)\n{\n id = i;\n if (scope == 0)\n getList().push_back(this);\n}\n\n/// Fill the hashtable mapping attribute names to their id, from registered attribute objects\nvoid AttributeId::initialize(void)\n\n{\n vector &thelist(getList());\n for(int4 i=0;iname) != lookupAttributeId.end())\n throw DecoderError(attrib->name + \" attribute registered more than once\");\n#endif\n lookupAttributeId[attrib->name] = attrib->id;\n }\n thelist.clear();\n thelist.shrink_to_fit();\n}\n\nunordered_map ElementId::lookupElementId;\n\n/// Access static vector of ElementId objects that are registered during static initialization\n/// The list itself is created once on the first call to this method.\n/// \\return a reference to the vector\nvector &ElementId::getList(void)\n\n{\n static vector thelist;\n return thelist;\n}\n\n/// This constructor should only be invoked for static objects. It registers the element for inclusion\n/// in the global hashtable.\n/// \\param nm is the name of the element\n/// \\param i is an id to associate with the element\n/// \\param scope is an id for the scope of this element\nElementId::ElementId(const string &nm,uint4 i,int4 scope)\n : name(nm)\n{\n id = i;\n if (scope == 0)\n getList().push_back(this);\n}\n\n/// Fill the hashtable mapping element names to their id, from registered element objects\nvoid ElementId::initialize(void)\n\n{\n vector &thelist(getList());\n for(int4 i=0;iname) != lookupElementId.end())\n throw DecoderError(elem->name + \" element registered more than once\");\n#endif\n lookupElementId[elem->name] = elem->id;\n }\n thelist.clear();\n thelist.shrink_to_fit();\n}\n\nXmlDecode::~XmlDecode(void)\n\n{\n if (document != (Document *)0)\n delete document;\n}\n\nvoid XmlDecode::ingestStream(istream &s)\n\n{\n document = xml_tree(s);\n rootElement = document->getRoot();\n}\n\nuint4 XmlDecode::peekElement(void)\n\n{\n const Element *el;\n if (elStack.empty()) {\n if (rootElement == (const Element *)0)\n return 0;\n el = rootElement;\n }\n else {\n el = elStack.back();\n List::const_iterator iter = iterStack.back();\n if (iter == el->getChildren().end())\n return 0;\n el = *iter;\n }\n return ElementId::find(el->getName(),scope);\n}\n\nuint4 XmlDecode::openElement(void)\n\n{\n const Element *el;\n if (elStack.empty()) {\n if (rootElement == (const Element *)0)\n return 0;\t\t\t\t// Document already traversed\n el = rootElement;\n rootElement = (const Element *)0;\t\t// Only open once\n }\n else {\n el = elStack.back();\n List::const_iterator iter = iterStack.back();\n if (iter == el->getChildren().end())\n return 0;\t\t\t\t// Element already fully traversed\n el = *iter;\n iterStack.back() = ++iter;\n }\n elStack.push_back(el);\n iterStack.push_back(el->getChildren().begin());\n attributeIndex = -1;\n return ElementId::find(el->getName(),scope);\n}\n\nuint4 XmlDecode::openElement(const ElementId &elemId)\n\n{\n const Element *el;\n if (elStack.empty()) {\n if (rootElement == (const Element *)0)\n throw DecoderError(\"Expecting <\" + elemId.getName() + \"> but reached end of document\");\n el = rootElement;\n rootElement = (const Element *)0;\t\t// Only open document once\n }\n else {\n el = elStack.back();\n List::const_iterator iter = iterStack.back();\n if (iter != el->getChildren().end()) {\n el = *iter;\n iterStack.back() = ++iter;\n }\n else\n throw DecoderError(\"Expecting <\" + elemId.getName() + \"> but no remaining children in current element\");\n }\n if (el->getName() != elemId.getName())\n throw DecoderError(\"Expecting <\" + elemId.getName() + \"> but got <\" + el->getName() + \">\");\n elStack.push_back(el);\n iterStack.push_back(el->getChildren().begin());\n attributeIndex = -1;\n return elemId.getId();\n}\n\nvoid XmlDecode::closeElement(uint4 id)\n\n{\n#ifdef CPUI_DEBUG\n const Element *el = elStack.back();\n if (iterStack.back() != el->getChildren().end())\n throw DecoderError(\"Closing element <\" + el->getName() + \"> with additional children\");\n if (ElementId::find(el->getName(), scope) != id)\n throw DecoderError(\"Trying to close <\" + el->getName() + \"> with mismatching id\");\n#endif\n elStack.pop_back();\n iterStack.pop_back();\n attributeIndex = 1000;\t// Cannot read any additional attributes\n}\n\nvoid XmlDecode::closeElementSkipping(uint4 id)\n\n{\n#ifdef CPUI_DEBUG\n const Element *el = elStack.back();\n if (ElementId::find(el->getName(), scope) != id)\n throw DecoderError(\"Trying to close <\" + el->getName() + \"> with mismatching id\");\n#endif\n elStack.pop_back();\n iterStack.pop_back();\n attributeIndex = 1000; // We could check that id matches current element\n}\n\nvoid XmlDecode::rewindAttributes(void)\n\n{\n attributeIndex = -1;\n}\n\nuint4 XmlDecode::getNextAttributeId(void)\n\n{\n const Element *el = elStack.back();\n int4 nextIndex = attributeIndex + 1;\n if (nextIndex < el->getNumAttributes()) {\n attributeIndex = nextIndex;\n return AttributeId::find(el->getAttributeName(attributeIndex),scope);\n }\n return 0;\n}\n\nuint4 XmlDecode::getIndexedAttributeId(const AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n if (attributeIndex < 0 || attributeIndex >= el->getNumAttributes())\n return ATTRIB_UNKNOWN.getId();\n // For XML, the index is encoded directly in the attribute name\n const string &attribName(el->getAttributeName(attributeIndex));\n // Does the name start with desired attribute base name?\n if (0 != attribName.compare(0,attribId.getName().size(),attribId.getName()))\n return ATTRIB_UNKNOWN.getId();\n uint4 val = 0;\n istringstream s(attribName.substr(attribId.getName().size()));\t// Strip off the base name\n s >> dec >> val;\t\t// Decode the remaining decimal integer (starting at 1)\n if (val == 0)\n throw LowlevelError(\"Bad indexed attribute: \" + attribId.getName());\n return attribId.getId() + (val-1);\n}\n\n/// \\brief Find the attribute index, within the given element, for the given name\n///\n/// Run through the attributes of the element until we find the one matching the name,\n/// or throw an exception otherwise.\n/// \\param el is the given element to search\n/// \\param attribName is the attribute name to search for\n/// \\return the matching attribute index\nint4 XmlDecode::findMatchingAttribute(const Element *el,const string &attribName)\n\n{\n for(int4 i=0;igetNumAttributes();++i) {\n if (el->getAttributeName(i) == attribName)\n return i;\n }\n throw DecoderError(\"Attribute missing: \" + attribName);\n}\n\nbool XmlDecode::readBool(void)\n\n{\n const Element *el = elStack.back();\n return xml_readbool(el->getAttributeValue(attributeIndex));\n}\n\nbool XmlDecode::readBool(const AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n if (attribId == ATTRIB_CONTENT)\n return xml_readbool(el->getContent());\n int4 index = findMatchingAttribute(el, attribId.getName());\n return xml_readbool(el->getAttributeValue(index));\n}\n\nintb XmlDecode::readSignedInteger(void)\n\n{\n const Element *el = elStack.back();\n intb res = 0;\n istringstream s2(el->getAttributeValue(attributeIndex));\n s2.unsetf(ios::dec | ios::hex | ios::oct);\n s2 >> res;\n return res;\n}\n\nintb XmlDecode::readSignedInteger(const AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n intb res = 0;\n if (attribId == ATTRIB_CONTENT) {\n istringstream s(el->getContent());\n s.unsetf(ios::dec | ios::hex | ios::oct);\n s >> res;\n }\n else {\n int4 index = findMatchingAttribute(el, attribId.getName());\n istringstream s(el->getAttributeValue(index));\n s.unsetf(ios::dec | ios::hex | ios::oct);\n s >> res;\n }\n return res;\n}\n\nintb XmlDecode::readSignedIntegerExpectString(const string &expect,intb expectval)\n\n{\n const Element *el = elStack.back();\n const string &value( el->getAttributeValue(attributeIndex) );\n if (value == expect)\n return expectval;\n istringstream s2(value);\n s2.unsetf(ios::dec | ios::hex | ios::oct);\n intb res = 0;\n s2 >> res;\n return res;\n}\n\nintb XmlDecode::readSignedIntegerExpectString(const AttributeId &attribId,const string &expect,intb expectval)\n\n{\n string value = readString(attribId);\n if (value == expect)\n return expectval;\n istringstream s2(value);\n s2.unsetf(ios::dec | ios::hex | ios::oct);\n intb res = 0;\n s2 >> res;\n return res;\n}\n\nuintb XmlDecode::readUnsignedInteger(void)\n\n{\n const Element *el = elStack.back();\n uintb res = 0;\n istringstream s2(el->getAttributeValue(attributeIndex));\n s2.unsetf(ios::dec | ios::hex | ios::oct);\n s2 >> res;\n return res;\n}\n\nuintb XmlDecode::readUnsignedInteger(const AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n uintb res = 0;\n if (attribId == ATTRIB_CONTENT) {\n istringstream s(el->getContent());\n s.unsetf(ios::dec | ios::hex | ios::oct);\n s >> res;\n }\n else {\n int4 index = findMatchingAttribute(el, attribId.getName());\n istringstream s(el->getAttributeValue(index));\n s.unsetf(ios::dec | ios::hex | ios::oct);\n s >> res;\n }\n return res;\n}\n\nstring XmlDecode::readString(void)\n\n{\n const Element *el = elStack.back();\n return el->getAttributeValue(attributeIndex);\n}\n\nstring XmlDecode::readString(const AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n if (attribId == ATTRIB_CONTENT)\n return el->getContent();\n int4 index = findMatchingAttribute(el, attribId.getName());\n return el->getAttributeValue(index);\n}\n\nAddrSpace *XmlDecode::readSpace(void)\n\n{\n const Element *el = elStack.back();\n string nm = el->getAttributeValue(attributeIndex);\n AddrSpace *res = spcManager->getSpaceByName(nm);\n if (res == (AddrSpace *)0)\n throw DecoderError(\"Unknown address space name: \"+nm);\n return res;\n}\n\nAddrSpace *XmlDecode::readSpace(const AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n string nm;\n if (attribId == ATTRIB_CONTENT) {\n nm = el->getContent();\n }\n else {\n int4 index = findMatchingAttribute(el, attribId.getName());\n nm = el->getAttributeValue(index);\n }\n AddrSpace *res = spcManager->getSpaceByName(nm);\n if (res == (AddrSpace *)0)\n throw DecoderError(\"Unknown address space name: \"+nm);\n return res;\n}\n\nOpCode XmlDecode::readOpcode(void)\n\n{\n const Element *el = elStack.back();\n string nm = el->getAttributeValue(attributeIndex);\n OpCode opc = get_opcode(nm);\n if (opc == (OpCode)0)\n throw DecoderError(\"Bad encoded OpCode\");\n return opc;\n}\n\nOpCode XmlDecode::readOpcode(AttributeId &attribId)\n\n{\n const Element *el = elStack.back();\n string nm;\n if (attribId == ATTRIB_CONTENT) {\n nm = el->getContent();\n }\n else {\n int4 index = findMatchingAttribute(el, attribId.getName());\n nm = el->getAttributeValue(index);\n }\n OpCode opc = get_opcode(nm);\n if (opc == (OpCode)0)\n throw DecoderError(\"Bad encoded OpCode\");\n return opc;\n}\n\nvoid XmlEncode::newLine(void)\n\n{\n if (!doFormatting)\n return;\n\n int numSpaces = depth * 2 + 1;\n if (numSpaces > MAX_SPACES) {\n numSpaces = MAX_SPACES;\n }\n outStream.write(spaces,numSpaces);\n}\n\nvoid XmlEncode::openElement(const ElementId &elemId)\n\n{\n if (tagStatus == tag_start)\n outStream << '>';\n else\n tagStatus = tag_start;\n newLine();\n outStream << '<' << elemId.getName();\n depth += 1;\n}\n\nvoid XmlEncode::closeElement(const ElementId &elemId)\n\n{\n depth -= 1;\n if (tagStatus == tag_start) {\n outStream << \"/>\";\n tagStatus = tag_stop;\n return;\n }\n if (tagStatus != tag_content)\n newLine();\n else\n tagStatus = tag_stop;\n\n outStream << \"';\n}\n\nvoid XmlEncode::writeBool(const AttributeId &attribId,bool val)\n\n{\n if (attribId == ATTRIB_CONTENT) {\t// Special id indicating, text value\n if (tagStatus == tag_start) {\n outStream << '>';\n }\n if (val)\n outStream << \"true\";\n else\n outStream << \"false\";\n tagStatus = tag_content;\n return;\n }\n a_v_b(outStream, attribId.getName(), val);\n}\n\nvoid XmlEncode::writeSignedInteger(const AttributeId &attribId,intb val)\n\n{\n if (attribId == ATTRIB_CONTENT) {\t// Special id indicating, text value\n if (tagStatus == tag_start) {\n outStream << '>';\n }\n outStream << dec << val;\n tagStatus = tag_content;\n return;\n }\n a_v_i(outStream, attribId.getName(), val);\n}\n\nvoid XmlEncode::writeUnsignedInteger(const AttributeId &attribId,uintb val)\n\n{\n if (attribId == ATTRIB_CONTENT) {\t// Special id indicating, text value\n if (tagStatus == tag_start) {\n outStream << '>';\n }\n outStream << hex << \"0x\" << val;\n tagStatus = tag_content;\n return;\n }\n a_v_u(outStream, attribId.getName(), val);\n}\n\nvoid XmlEncode::writeString(const AttributeId &attribId,const string &val)\n\n{\n if (attribId == ATTRIB_CONTENT) {\t// Special id indicating, text value\n if (tagStatus == tag_start) {\n outStream << '>';\n }\n xml_escape(outStream, val.c_str());\n tagStatus = tag_content;\n return;\n }\n a_v(outStream,attribId.getName(),val);\n}\n\nvoid XmlEncode::writeStringIndexed(const AttributeId &attribId,uint4 index,const string &val)\n\n{\n outStream << ' ' << attribId.getName() << dec << index + 1;\n outStream << \"=\\\"\";\n xml_escape(outStream,val.c_str());\n outStream << \"\\\"\";\n\n}\n\nvoid XmlEncode::writeSpace(const AttributeId &attribId,const AddrSpace *spc)\n\n{\n if (attribId == ATTRIB_CONTENT) {\t// Special id indicating, text value\n if (tagStatus == tag_start) {\n outStream << '>';\n }\n xml_escape(outStream, spc->getName().c_str());\n tagStatus = tag_content;\n return;\n }\n a_v(outStream,attribId.getName(),spc->getName());\n}\n\nvoid XmlEncode::writeOpcode(const AttributeId &attribId,OpCode opc)\n\n{\n const char *name = get_opname(opc);\n if (attribId == ATTRIB_CONTENT) {\t// Special id indicating, text value\n if (tagStatus == tag_start) {\n outStream << '>';\n }\n outStream << name;\n tagStatus = tag_content;\n return;\n }\n outStream << ' ' << attribId.getName() << \"=\\\"\";\n outStream << name;\n outStream << \"\\\"\";\n}\n\n/// The integer is encoded, 7-bits per byte, starting with the most significant 7-bits.\n/// The integer is decode from the \\e current position, and the position is advanced.\n/// \\param len is the number of bytes to extract\nuint8 PackedDecode::readInteger(int4 len)\n\n{\n uint8 res = 0;\n while(len > 0) {\n res <<= RAWDATA_BITSPERBYTE;\n res |= (getNextByte(curPos) & RAWDATA_MASK);\n len -= 1;\n }\n return res;\n}\n\n/// The \\e current position is reset to the start of the current open element. Attributes are scanned\n/// and skipped until the attribute matching the given id is found. The \\e current position is set to the\n/// start of the matching attribute, in preparation for one of the read*() methods.\n/// If the id is not found an exception is thrown.\n/// \\param attribId is the attribute id to scan for.\nvoid PackedDecode::findMatchingAttribute(const AttributeId &attribId)\n\n{\n curPos = startPos;\n for(;;) {\n uint1 header1 = getByte(curPos);\n if ((header1 & HEADER_MASK) != ATTRIBUTE) break;\n uint4 id = header1 & ELEMENTID_MASK;\n if ((header1 & HEADEREXTEND_MASK) != 0) {\n id <<= RAWDATA_BITSPERBYTE;\n id |= (getBytePlus1(curPos) & RAWDATA_MASK);\n }\n if (attribId.getId() == id)\n return;\t\t// Found it\n skipAttribute();\n }\n throw DecoderError(\"Attribute \" + attribId.getName() + \" is not present\");\n}\n\n/// The attribute at the \\e current position is scanned enough to determine its length, and the position\n/// is advanced to the following byte.\nvoid PackedDecode::skipAttribute(void)\n\n{\n uint1 header1 = getNextByte(curPos);\t// Attribute header\n if ((header1 & HEADEREXTEND_MASK) != 0)\n getNextByte(curPos);\t\t// Extra byte for extended id\n uint1 typeByte = getNextByte(curPos);\t// Type (and length) byte\n uint1 attribType = typeByte >> TYPECODE_SHIFT;\n if (attribType == TYPECODE_BOOLEAN || attribType == TYPECODE_SPECIALSPACE)\n return;\t\t\t\t// has no additional data\n uint4 length = readLengthCode(typeByte);\t// Length of data in bytes\n if (attribType == TYPECODE_STRING) {\n length = readInteger(length);\t// Read length field to get final length of string\n }\n advancePosition(curPos, length);\t// Skip -length- data\n}\n\n/// This assumes the header and \\b type \\b byte have been read. Decode type and length info and finish\n/// skipping over the attribute so that the next call to getNextAttributeId() is on cut.\n/// \\param typeByte is the previously scanned type byte\nvoid PackedDecode::skipAttributeRemaining(uint1 typeByte)\n\n{\n uint1 attribType = typeByte >> TYPECODE_SHIFT;\n if (attribType == TYPECODE_BOOLEAN || attribType == TYPECODE_SPECIALSPACE)\n return;\t\t\t\t// has no additional data\n uint4 length = readLengthCode(typeByte);\t// Length of data in bytes\n if (attribType == TYPECODE_STRING) {\n length = readInteger(length);\t// Read length field to get final length of string\n }\n advancePosition(curPos, length);\t// Skip -length- data\n}\n\n/// Set decoder to beginning of the stream. Add padding to end of the stream.\n/// \\param bufPos is the number of bytes used by the last input buffer\nvoid PackedDecode::endIngest(int4 bufPos)\n\n{\n endPos.seqIter = inStream.begin();\t\t// Set position to beginning of stream\n if (endPos.seqIter != inStream.end()) {\n endPos.current = (*endPos.seqIter).start;\n endPos.end = (*endPos.seqIter).end;\n // Make sure there is at least one character after ingested buffer\n if (bufPos == BUFFER_SIZE) {\n // Last buffer was entirely filled\n uint1 *endbuf = new uint1[1];\t\t// Add one more buffer\n inStream.emplace_back(endbuf,endbuf + 1);\n bufPos = 0;\n }\n uint1 *buf = inStream.back().start;\n buf[bufPos] = ELEMENT_END;\n }\n}\n\nPackedDecode::~PackedDecode(void)\n\n{\n list::const_iterator iter;\n for(iter=inStream.begin();iter!=inStream.end();++iter) {\n delete [] (*iter).start;\n }\n}\n\nvoid PackedDecode::ingestStream(istream &s)\n\n{\n int4 gcount = 0;\n while(s.peek() > 0) {\n uint1 *buf = allocateNextInputBuffer(1);\n s.get((char *)buf,BUFFER_SIZE+1,'\\0');\n gcount = s.gcount();\n }\n endIngest(gcount);\n}\n\nuint4 PackedDecode::peekElement(void)\n\n{\n uint1 header1 = getByte(endPos);\n if ((header1 & HEADER_MASK) != ELEMENT_START)\n return 0;\n uint4 id = header1 & ELEMENTID_MASK;\n if ((header1 & HEADEREXTEND_MASK) != 0) {\n id <<= RAWDATA_BITSPERBYTE;\n id |= (getBytePlus1(endPos) & RAWDATA_MASK);\n }\n return id;\n}\n\nuint4 PackedDecode::openElement(void)\n\n{\n uint1 header1 = getByte(endPos);\n if ((header1 & HEADER_MASK) != ELEMENT_START)\n return 0;\n getNextByte(endPos);\n uint4 id = header1 & ELEMENTID_MASK;\n if ((header1 & HEADEREXTEND_MASK) != 0) {\n id <<= RAWDATA_BITSPERBYTE;\n id |= (getNextByte(endPos) & RAWDATA_MASK);\n }\n startPos = endPos;\n curPos = endPos;\n header1 = getByte(curPos);\n while((header1 & HEADER_MASK) == ATTRIBUTE) {\n skipAttribute();\n header1 = getByte(curPos);\n }\n endPos = curPos;\n curPos = startPos;\n attributeRead = true;\t\t// \"Last attribute was read\" is vacuously true\n return id;\n}\n\nuint4 PackedDecode::openElement(const ElementId &elemId)\n\n{\n uint4 id = openElement();\n if (id != elemId.getId()) {\n if (id == 0)\n throw DecoderError(\"Expecting <\" + elemId.getName() + \"> but did not scan an element\");\n throw DecoderError(\"Expecting <\" + elemId.getName() + \"> but id did not match\");\n }\n return id;\n}\n\nvoid PackedDecode::closeElement(uint4 id)\n\n{\n uint1 header1 = getNextByte(endPos);\n if ((header1 & HEADER_MASK) != ELEMENT_END)\n throw DecoderError(\"Expecting element close\");\n uint4 closeId = header1 & ELEMENTID_MASK;\n if ((header1 & HEADEREXTEND_MASK) != 0) {\n closeId <<= RAWDATA_BITSPERBYTE;\n closeId |= (getNextByte(endPos) & RAWDATA_MASK);\n }\n if (id != closeId)\n throw DecoderError(\"Did not see expected closing element\");\n}\n\nvoid PackedDecode::closeElementSkipping(uint4 id)\n\n{\n vector idstack;\n idstack.push_back(id);\n do {\n uint1 header1 = getByte(endPos) & HEADER_MASK;\n if (header1 == ELEMENT_END) {\n closeElement(idstack.back());\n idstack.pop_back();\n }\n else if (header1 == ELEMENT_START) {\n idstack.push_back(openElement());\n }\n else\n throw DecoderError(\"Corrupt stream\");\n } while(!idstack.empty());\n}\n\nvoid PackedDecode::rewindAttributes(void)\n\n{\n curPos = startPos;\n attributeRead = true;\n}\n\nuint4 PackedDecode::getNextAttributeId(void)\n\n{\n if (!attributeRead)\n skipAttribute();\n uint1 header1 = getByte(curPos);\n if ((header1 & HEADER_MASK) != ATTRIBUTE)\n return 0;\n uint4 id = header1 & ELEMENTID_MASK;\n if ((header1 & HEADEREXTEND_MASK) != 0) {\n id <<= RAWDATA_BITSPERBYTE;\n id |= (getBytePlus1(curPos) & RAWDATA_MASK);\n }\n attributeRead = false;\n return id;\n}\n\nuint4 PackedDecode::getIndexedAttributeId(const AttributeId &attribId)\n\n{\n return ATTRIB_UNKNOWN.getId();\t// PackedDecode never needs to reinterpret an attribute\n}\n\nbool PackedDecode::readBool(void)\n\n{\n uint1 header1 = getNextByte(curPos);\n if ((header1 & HEADEREXTEND_MASK)!=0)\n getNextByte(curPos);\n uint1 typeByte = getNextByte(curPos);\n attributeRead = true;\n if ((typeByte >> TYPECODE_SHIFT) != TYPECODE_BOOLEAN)\n throw DecoderError(\"Expecting boolean attribute\");\n return ((typeByte & LENGTHCODE_MASK) != 0);\n}\n\nbool PackedDecode::readBool(const AttributeId &attribId)\n\n{\n findMatchingAttribute(attribId);\n bool res = readBool();\n curPos = startPos;\n return res;\n}\n\nintb PackedDecode::readSignedInteger(void)\n\n{\n uint1 header1 = getNextByte(curPos);\n if ((header1 & HEADEREXTEND_MASK)!=0)\n getNextByte(curPos);\n uint1 typeByte = getNextByte(curPos);\n uint4 typeCode = typeByte >> TYPECODE_SHIFT;\n intb res;\n if (typeCode == TYPECODE_SIGNEDINT_POSITIVE) {\n res = readInteger(readLengthCode(typeByte));\n }\n else if (typeCode == TYPECODE_SIGNEDINT_NEGATIVE) {\n res = readInteger(readLengthCode(typeByte));\n res = -res;\n }\n else {\n skipAttributeRemaining(typeByte);\n attributeRead = true;\n throw DecoderError(\"Expecting signed integer attribute\");\n }\n attributeRead = true;\n return res;\n}\n\nintb PackedDecode::readSignedInteger(const AttributeId &attribId)\n\n{\n findMatchingAttribute(attribId);\n intb res = readSignedInteger();\n curPos = startPos;\n return res;\n}\n\nintb PackedDecode::readSignedIntegerExpectString(const string &expect,intb expectval)\n\n{\n intb res;\n Position tmpPos = curPos;\n uint1 header1 = getNextByte(tmpPos);\n if ((header1 & HEADEREXTEND_MASK)!=0)\n getNextByte(tmpPos);\n uint1 typeByte = getNextByte(tmpPos);\n uint4 typeCode = typeByte >> TYPECODE_SHIFT;\n if (typeCode == TYPECODE_STRING) {\n string val = readString();\n if (val != expect) {\n ostringstream s;\n s << \"Expecting string \\\"\" << expect << \"\\\" but read \\\"\" << val << \"\\\"\";\n throw DecoderError(s.str());\n }\n res = expectval;\n }\n else {\n res = readSignedInteger();\n }\n return res;\n}\n\nintb PackedDecode::readSignedIntegerExpectString(const AttributeId &attribId,const string &expect,intb expectval)\n\n{\n findMatchingAttribute(attribId);\n intb res = readSignedIntegerExpectString(expect,expectval);\n curPos = startPos;\n return res;\n}\n\nuintb PackedDecode::readUnsignedInteger(void)\n\n{\n uint1 header1 = getNextByte(curPos);\n if ((header1 & HEADEREXTEND_MASK)!=0)\n getNextByte(curPos);\n uint1 typeByte = getNextByte(curPos);\n uint4 typeCode = typeByte >> TYPECODE_SHIFT;\n uintb res;\n if (typeCode == TYPECODE_UNSIGNEDINT) {\n res = readInteger(readLengthCode(typeByte));\n }\n else {\n skipAttributeRemaining(typeByte);\n attributeRead = true;\n throw DecoderError(\"Expecting unsigned integer attribute\");\n }\n attributeRead = true;\n return res;\n}\n\nuintb PackedDecode::readUnsignedInteger(const AttributeId &attribId)\n\n{\n findMatchingAttribute(attribId);\n uintb res = readUnsignedInteger();\n curPos = startPos;\n return res;\n}\n\nstring PackedDecode::readString(void)\n\n{\n uint1 header1 = getNextByte(curPos);\n if ((header1 & HEADEREXTEND_MASK)!=0)\n getNextByte(curPos);\n uint1 typeByte = getNextByte(curPos);\n uint4 typeCode = typeByte >> TYPECODE_SHIFT;\n if (typeCode != TYPECODE_STRING) {\n skipAttributeRemaining(typeByte);\n attributeRead = true;\n throw DecoderError(\"Expecting string attribute\");\n }\n int4 length = readLengthCode(typeByte);\n length = readInteger(length);\n\n attributeRead = true;\n int4 curLen = curPos.end - curPos.current;\n if (curLen >= length) {\n string res((const char *)curPos.current,length);\n advancePosition(curPos, length);\n return res;\n }\n string res((const char *)curPos.current,curLen);\n length -= curLen;\n advancePosition(curPos, curLen);\n while(length > 0) {\n curLen = curPos.end - curPos.current;\n if (curLen > length)\n curLen = length;\n res.append((const char *)curPos.current,curLen);\n length -= curLen;\n advancePosition(curPos, curLen);\n }\n return res;\n}\n\nstring PackedDecode::readString(const AttributeId &attribId)\n\n{\n findMatchingAttribute(attribId);\n string res = readString();\n curPos = startPos;\n return res;\n}\n\nAddrSpace *PackedDecode::readSpace(void)\n\n{\n uint1 header1 = getNextByte(curPos);\n if ((header1 & HEADEREXTEND_MASK)!=0)\n getNextByte(curPos);\n uint1 typeByte = getNextByte(curPos);\n uint4 typeCode = typeByte >> TYPECODE_SHIFT;\n int4 res;\n AddrSpace *spc;\n if (typeCode == TYPECODE_ADDRESSSPACE) {\n res = readInteger(readLengthCode(typeByte));\n spc = spcManager->getSpace(res);\n if (spc == (AddrSpace *)0)\n throw DecoderError(\"Unknown address space index\");\n }\n else if (typeCode == TYPECODE_SPECIALSPACE) {\n uint4 specialCode = readLengthCode(typeByte);\n if (specialCode == SPECIALSPACE_STACK)\n spc = spcManager->getStackSpace();\n else if (specialCode == SPECIALSPACE_JOIN) {\n spc = spcManager->getJoinSpace();\n }\n else {\n throw DecoderError(\"Cannot marshal special address space\");\n }\n }\n else {\n skipAttributeRemaining(typeByte);\n attributeRead = true;\n throw DecoderError(\"Expecting space attribute\");\n }\n attributeRead = true;\n return spc;\n}\n\nAddrSpace *PackedDecode::readSpace(const AttributeId &attribId)\n\n{\n findMatchingAttribute(attribId);\n AddrSpace *res = readSpace();\n curPos = startPos;\n return res;\n}\n\nOpCode PackedDecode::readOpcode(void)\n\n{\n int4 val = (int4)readSignedInteger();\n if (val < 0 || val >= CPUI_MAX)\n throw DecoderError(\"Bad encoded OpCode\");\n return (OpCode)val;\n}\n\nOpCode PackedDecode::readOpcode(AttributeId &attribId)\n\n{\n findMatchingAttribute(attribId);\n OpCode opc = readOpcode();\n curPos = startPos;\n return opc;\n}\n\n/// The value is either an unsigned integer, an address space index, or (the absolute value of) a signed integer.\n/// A type header is passed in with the particular type code for the value already filled in.\n/// This method then fills in the length code, outputs the full type header and the encoded bytes of the integer.\n/// \\param typeByte is the type header\n/// \\param val is the integer value\nvoid PackedEncode::writeInteger(uint1 typeByte,uint8 val)\n\n{\n uint1 lenCode;\n int4 sa;\n if (val == 0) {\n lenCode = 0;\n sa = -1;\n }\n else if (val < 0x800000000) {\n if (val < 0x200000) {\n if (val < 0x80) {\n\tlenCode = 1;\t\t// 7-bits\n\tsa = 0;\n }\n else if (val < 0x4000) {\n\tlenCode = 2;\t\t// 14-bits\n\tsa = RAWDATA_BITSPERBYTE;\n }\n else {\n\tlenCode = 3;\t\t// 21-bits\n\tsa = 2*RAWDATA_BITSPERBYTE;\n }\n }\n else if (val < 0x10000000) {\n lenCode = 4;\t\t// 28-bits\n sa = 3*RAWDATA_BITSPERBYTE;\n }\n else {\n lenCode = 5;\t\t// 35-bits\n sa = 4*RAWDATA_BITSPERBYTE;\n }\n }\n else if (val < 0x2000000000000) {\n if (val < 0x40000000000) {\n lenCode = 6;\n sa = 5*RAWDATA_BITSPERBYTE;\n }\n else {\n lenCode = 7;\n sa = 6*RAWDATA_BITSPERBYTE;\n }\n }\n else {\n if (val < 0x100000000000000) {\n lenCode = 8;\n sa = 7*RAWDATA_BITSPERBYTE;\n }\n else if (val < 0x8000000000000000) {\n lenCode = 9;\n sa = 8*RAWDATA_BITSPERBYTE;\n }\n else {\n lenCode = 10;\n sa = 9*RAWDATA_BITSPERBYTE;\n }\n }\n typeByte |= lenCode;\n outStream.put(typeByte);\n for(;sa >= 0;sa -= RAWDATA_BITSPERBYTE) {\n uint1 piece = (val >> sa) & RAWDATA_MASK;\n piece |= RAWDATA_MARKER;\n outStream.put(piece);\n }\n}\n\nvoid PackedEncode::openElement(const ElementId &elemId)\n\n{\n writeHeader(ELEMENT_START, elemId.getId());\n}\n\nvoid PackedEncode::closeElement(const ElementId &elemId)\n\n{\n writeHeader(ELEMENT_END, elemId.getId());\n}\n\nvoid PackedEncode::writeBool(const AttributeId &attribId,bool val)\n\n{\n writeHeader(ATTRIBUTE, attribId.getId());\n uint1 typeByte = val ? ((TYPECODE_BOOLEAN << TYPECODE_SHIFT) | 1) : (TYPECODE_BOOLEAN << TYPECODE_SHIFT);\n outStream.put(typeByte);\n}\n\nvoid PackedEncode::writeSignedInteger(const AttributeId &attribId,intb val)\n\n{\n writeHeader(ATTRIBUTE, attribId.getId());\n uint1 typeByte;\n uint8 num;\n if (val < 0) {\n typeByte = (TYPECODE_SIGNEDINT_NEGATIVE << TYPECODE_SHIFT);\n num = -val;\n }\n else {\n typeByte = (TYPECODE_SIGNEDINT_POSITIVE << TYPECODE_SHIFT);\n num = val;\n }\n writeInteger(typeByte, num);\n}\n\nvoid PackedEncode::writeUnsignedInteger(const AttributeId &attribId,uintb val)\n\n{\n writeHeader(ATTRIBUTE, attribId.getId());\n writeInteger((TYPECODE_UNSIGNEDINT << TYPECODE_SHIFT),val);\n}\n\nvoid PackedEncode::writeString(const AttributeId &attribId,const string &val)\n\n{\n uint8 length = val.length();\n writeHeader(ATTRIBUTE, attribId.getId());\n writeInteger((TYPECODE_STRING << TYPECODE_SHIFT), length);\n outStream.write(val.c_str(), length);\n}\n\nvoid PackedEncode::writeStringIndexed(const AttributeId &attribId,uint4 index,const string &val)\n\n{\n uint8 length = val.length();\n writeHeader(ATTRIBUTE, attribId.getId() + index);\n writeInteger((TYPECODE_STRING << TYPECODE_SHIFT), length);\n outStream.write(val.c_str(), length);\n}\n\nvoid PackedEncode::writeSpace(const AttributeId &attribId,const AddrSpace *spc)\n\n{\n writeHeader(ATTRIBUTE, attribId.getId());\n switch(spc->getType()) {\n case IPTR_FSPEC:\n outStream.put((TYPECODE_SPECIALSPACE << TYPECODE_SHIFT) | SPECIALSPACE_FSPEC);\n break;\n case IPTR_IOP:\n outStream.put((TYPECODE_SPECIALSPACE << TYPECODE_SHIFT) | SPECIALSPACE_IOP);\n break;\n case IPTR_JOIN:\n outStream.put((TYPECODE_SPECIALSPACE << TYPECODE_SHIFT) | SPECIALSPACE_JOIN);\n break;\n case IPTR_SPACEBASE:\n if (spc->isFormalStackSpace())\n outStream.put((TYPECODE_SPECIALSPACE << TYPECODE_SHIFT) | SPECIALSPACE_STACK);\n else\n outStream.put((TYPECODE_SPECIALSPACE << TYPECODE_SHIFT) | SPECIALSPACE_SPACEBASE);\t// A secondary register offset space\n break;\n default:\n uint8 spcId = spc->getIndex();\n writeInteger((TYPECODE_ADDRESSSPACE << TYPECODE_SHIFT), spcId);\n break;\n }\n}\n\nvoid PackedEncode::writeOpcode(const AttributeId &attribId,OpCode opc)\n\n{\n writeHeader(ATTRIBUTE, attribId.getId());\n writeInteger((TYPECODE_SIGNEDINT_POSITIVE << TYPECODE_SHIFT), opc);\n}\n\n// Common attributes. Attributes with multiple uses\nAttributeId ATTRIB_CONTENT = AttributeId(\"XMLcontent\",1);\nAttributeId ATTRIB_ALIGN = AttributeId(\"align\",2);\nAttributeId ATTRIB_BIGENDIAN = AttributeId(\"bigendian\",3);\nAttributeId ATTRIB_CONSTRUCTOR = AttributeId(\"constructor\",4);\nAttributeId ATTRIB_DESTRUCTOR = AttributeId(\"destructor\",5);\nAttributeId ATTRIB_EXTRAPOP = AttributeId(\"extrapop\",6);\nAttributeId ATTRIB_FORMAT = AttributeId(\"format\",7);\nAttributeId ATTRIB_HIDDENRETPARM = AttributeId(\"hiddenretparm\",8);\nAttributeId ATTRIB_ID = AttributeId(\"id\",9);\nAttributeId ATTRIB_INDEX = AttributeId(\"index\",10);\nAttributeId ATTRIB_INDIRECTSTORAGE = AttributeId(\"indirectstorage\",11);\nAttributeId ATTRIB_METATYPE = AttributeId(\"metatype\",12);\nAttributeId ATTRIB_MODEL = AttributeId(\"model\",13);\nAttributeId ATTRIB_NAME = AttributeId(\"name\",14);\nAttributeId ATTRIB_NAMELOCK = AttributeId(\"namelock\",15);\nAttributeId ATTRIB_OFFSET = AttributeId(\"offset\",16);\nAttributeId ATTRIB_READONLY = AttributeId(\"readonly\",17);\nAttributeId ATTRIB_REF = AttributeId(\"ref\",18);\nAttributeId ATTRIB_SIZE = AttributeId(\"size\",19);\nAttributeId ATTRIB_SPACE = AttributeId(\"space\",20);\nAttributeId ATTRIB_THISPTR = AttributeId(\"thisptr\",21);\nAttributeId ATTRIB_TYPE = AttributeId(\"type\",22);\nAttributeId ATTRIB_TYPELOCK = AttributeId(\"typelock\",23);\nAttributeId ATTRIB_VAL = AttributeId(\"val\",24);\nAttributeId ATTRIB_VALUE = AttributeId(\"value\",25);\nAttributeId ATTRIB_WORDSIZE = AttributeId(\"wordsize\",26);\nAttributeId ATTRIB_STORAGE = AttributeId(\"storage\",149);\nAttributeId ATTRIB_STACKSPILL = AttributeId(\"stackspill\",150);\n\nAttributeId ATTRIB_UNKNOWN = AttributeId(\"XMLunknown\",159); // Number serves as next open index\n\n\nElementId ELEM_DATA = ElementId(\"data\",1);\nElementId ELEM_INPUT = ElementId(\"input\",2);\nElementId ELEM_OFF = ElementId(\"off\",3);\nElementId ELEM_OUTPUT = ElementId(\"output\",4);\nElementId ELEM_RETURNADDRESS = ElementId(\"returnaddress\",5);\nElementId ELEM_SYMBOL = ElementId(\"symbol\",6);\nElementId ELEM_TARGET = ElementId(\"target\",7);\nElementId ELEM_VAL = ElementId(\"val\",8);\nElementId ELEM_VALUE = ElementId(\"value\",9);\nElementId ELEM_VOID = ElementId(\"void\",10);\n\nElementId ELEM_UNKNOWN = ElementId(\"XMLunknown\",289); // Number serves as next open index\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/marshal.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __MARSHAL_HH__\n#define __MARSHAL_HH__\n\n#include \"xml.hh\"\n#include \"opcodes.hh\"\n#include \n#include \n\nnamespace ghidra {\n\nusing std::list;\nusing std::unordered_map;\n\n/// \\brief An annotation for a data element to being transferred to/from a stream\n///\n/// This class parallels the XML concept of an \\b attribute on an element. An AttributeId describes\n/// a particular piece of data associated with an ElementId. The defining characteristic of the AttributeId is\n/// its name. Internally this name is associated with an integer id. The name (and id) uniquely determine\n/// the data being labeled, within the context of a specific ElementId. Within this context, an AttributeId labels either\n/// - An unsigned integer\n/// - A signed integer\n/// - A boolean value\n/// - A string\n///\n/// The same AttributeId can be used to label a different type of data when associated with a different ElementId.\nclass AttributeId {\n static unordered_map lookupAttributeId;\t\t///< A map of AttributeId names to their associated id\n static vector &getList(void);\t\t\t///< Retrieve the list of static AttributeId\n string name;\t\t\t///< The name of the attribute\n uint4 id;\t\t\t///< The (internal) id of the attribute\npublic:\n AttributeId(const string &nm,uint4 i,int4 scope=0);\t///< Construct given a name and id\n const string &getName(void) const { return name; }\t\t\t\t///< Get the attribute's name\n uint4 getId(void) const { return id; }\t\t\t\t\t///< Get the attribute's id\n bool operator==(const AttributeId &op2) const { return (id == op2.id); }\t///< Test equality with another AttributeId\n static uint4 find(const string &nm,int4 scope);\t///< Find the id associated with a specific attribute name\n static void initialize(void);\t\t\t\t///< Populate a hashtable with all AttributeId objects\n friend bool operator==(uint4 id,const AttributeId &op2) { return (id == op2.id); }\t///< Test equality of a raw integer id with an AttributeId\n friend bool operator==(const AttributeId &op1,uint4 id) { return (op1.id == id); }\t///< Test equality of an AttributeId with a raw integer id\n};\n\n/// \\brief An annotation for a specific collection of hierarchical data\n///\n/// This class parallels the XML concept of an \\b element. An ElementId describes a collection of data, where each\n/// piece is annotated by a specific AttributeId. In addition, each ElementId can contain zero or more \\e child\n/// ElementId objects, forming a hierarchy of annotated data. Each ElementId has a name, which is unique at least\n/// within the context of its parent ElementId. Internally this name is associated with an integer id. A special\n/// AttributeId ATTRIB_CONTENT is used to label the XML element's text content, which is traditionally not labeled\n/// as an attribute.\nclass ElementId {\n static unordered_map lookupElementId;\t///< A map of ElementId names to their associated id\n static vector &getList(void);\t\t///< Retrieve the list of static ElementId\n string name;\t\t\t///< The name of the element\n uint4 id;\t\t\t///< The (internal) id of the attribute\npublic:\n ElementId(const string &nm,uint4 i,int4 scope=0);\t\t///< Construct given a name and id\n const string &getName(void) const { return name; }\t\t\t\t///< Get the element's name\n uint4 getId(void) const { return id; }\t\t\t\t\t///< Get the element's id\n bool operator==(const ElementId &op2) const { return (id == op2.id); }\t///< Test equality with another ElementId\n static uint4 find(const string &nm,int4 scope);\t///< Find the id associated with a specific element name\n static void initialize(void);\t\t\t\t///< Populate a hashtable with all ElementId objects\n friend bool operator==(uint4 id,const ElementId &op2) { return (id == op2.id); }\t///< Test equality of a raw integer id with an ElementId\n friend bool operator==(const ElementId &op1,uint4 id) { return (op1.id == id); }\t///< Test equality of an ElementId with a raw integer id\n friend bool operator!=(uint4 id,const ElementId &op2) { return (id != op2.id); }\t///< Test inequality of a raw integer id with an ElementId\n friend bool operator!=(const ElementId &op1,uint4 id) { return (op1.id != id); }\t///< Test inequality of an ElementId with a raw integer id\n};\n\nclass AddrSpace;\nclass AddrSpaceManager;\n\n/// \\brief A class for reading structured data from a stream\n///\n/// All data is loosely structured as with an XML document. A document contains a nested set\n/// of \\b elements, with labels corresponding to the ElementId class. A single element can hold\n/// zero or more attributes and zero or more child elements. An attribute holds a primitive\n/// data element (bool, integer, string) and is labeled by an AttributeId. The document is traversed\n/// using a sequence of openElement() and closeElement() calls, intermixed with read*() calls to extract\n/// the data. The elements are traversed in a depth first order. Attributes within an element can\n/// be traversed in order using repeated calls to the getNextAttributeId() method, followed by a calls to\n/// one of the read*(void) methods to extract the data. Alternately a read*(AttributeId) call can be used\n/// to extract data for an attribute known to be in the element. There is a special content attribute\n/// whose data can be extracted using a read*(AttributeId) call that is passed the special ATTRIB_CONTENT id.\n/// This attribute will not be traversed by getNextAttribute().\nclass Decoder {\nprotected:\n const AddrSpaceManager *spcManager;\t\t///< Manager for decoding address space attributes\npublic:\n Decoder(const AddrSpaceManager *spc) { spcManager = spc; }\t///< Base constructor\n\n const AddrSpaceManager *getAddrSpaceManager(void) const { return spcManager; }\t///< Get the manager used for address space decoding\n virtual ~Decoder(void) {}\t///< Destructor\n\n /// \\brief Prepare to decode a given stream\n ///\n /// Called once before any decoding. Currently this is assumed to make an internal copy of the stream data,\n /// i.e. the input stream is cleared before any decoding takes place.\n /// \\param s is the given input stream to be decode\n /// \\return \\b true if the stream was fully ingested\n virtual void ingestStream(istream &s)=0;\n\n /// \\brief Peek at the next child element of the current parent, without traversing in (opening) it.\n ///\n /// The element id is returned, which can be compared to ElementId labels.\n /// If there are no remaining child elements to traverse, 0 is returned.\n /// \\return the element id or 0\n virtual uint4 peekElement(void)=0;\n\n /// \\brief Open (traverse into) the next child element of the current parent.\n ///\n /// The child becomes the current parent. The list of attributes is initialized for use with getNextAttributeId.\n /// \\return the id of the child element\n virtual uint4 openElement(void)=0;\n\n /// \\brief Open (traverse into) the next child element, which must be of a specific type\n ///\n /// The child becomes the current parent, and its attributes are initialized for use with getNextAttributeId.\n /// The child must match the given element id or an exception is thrown.\n /// \\param elemId is the given element id to match\n /// \\return the id of the child element\n virtual uint4 openElement(const ElementId &elemId)=0;\n\n /// \\brief Close the current element\n ///\n /// The data for the current element is considered fully processed. If the element has additional children,\n /// an exception is thrown. The stream must indicate the end of the element in some way.\n /// \\param id is the id of the element to close (which must be the current element)\n virtual void closeElement(uint4 id)=0;\n\n /// \\brief Close the current element, skipping any child elements that have not yet been parsed\n ///\n /// This closes the given element, which must be current. If there are child elements that have not been\n /// parsed, this is not considered an error, and they are skipped over in the parse.\n /// \\param id is the id of the element to close (which must be the current element)\n virtual void closeElementSkipping(uint4 id)=0;\n\n /// \\brief Get the next attribute id for the current element\n ///\n /// Attributes are automatically set up for traversal using this method, when the element is opened.\n /// If all attributes have been traversed (or there are no attributes), 0 is returned.\n /// \\return the id of the next attribute or 0\n virtual uint4 getNextAttributeId(void)=0;\n\n /// \\brief Get the id for the (current) attribute, assuming it is indexed\n ///\n /// Assuming the previous call to getNextAttributeId() returned the id of ATTRIB_UNKNOWN,\n /// reinterpret the attribute as being an indexed form of the given attribute. If the attribute\n /// matches, return this indexed id, otherwise return ATTRIB_UNKNOWN.\n /// \\param attribId is the attribute being indexed\n /// \\return the indexed id or ATTRIB_UNKNOWN\n virtual uint4 getIndexedAttributeId(const AttributeId &attribId)=0;\n\n /// \\brief Reset attribute traversal for the current element\n ///\n /// Attributes for a single element can be traversed more than once using the getNextAttributeId method.\n virtual void rewindAttributes(void)=0;\n\n /// \\brief Parse the current attribute as a boolean value\n ///\n /// The last attribute, as returned by getNextAttributeId, is treated as a boolean, and its value is returned.\n /// \\return the boolean value associated with the current attribute.\n virtual bool readBool(void)=0;\n\n /// \\brief Find and parse a specific attribute in the current element as a boolean value\n ///\n /// The set of attributes for the current element is searched for a match to the given attribute id.\n /// This attribute is then parsed as a boolean and its value returned.\n /// If there is no attribute matching the id, an exception is thrown.\n /// Parsing via getNextAttributeId is reset.\n /// \\param attribId is the specific attribute id to match\n /// \\return the boolean value\n virtual bool readBool(const AttributeId &attribId)=0;\n\n /// \\brief Parse the current attribute as a signed integer value\n ///\n /// The last attribute, as returned by getNextAttributeId, is treated as a signed integer, and its value is returned.\n /// \\return the signed integer value associated with the current attribute.\n virtual intb readSignedInteger(void)=0;\n\n /// \\brief Find and parse a specific attribute in the current element as a signed integer\n ///\n /// The set of attributes for the current element is searched for a match to the given attribute id.\n /// This attribute is then parsed as a signed integer and its value returned.\n /// If there is no attribute matching the id, an exception is thrown.\n /// Parsing via getNextAttributeId is reset.\n /// \\param attribId is the specific attribute id to match\n /// \\return the signed integer value\n virtual intb readSignedInteger(const AttributeId &attribId)=0;\n\n /// \\brief Parse the current attribute as either a signed integer value or a string.\n ///\n /// If the attribute is an integer, its value is returned. If the attribute is a string, it must match an\n /// expected string passed to the method, and a predetermined integer value associated with the string is returned.\n /// If the attribute neither matches the expected string nor is an integer, the return value is undefined.\n /// \\param expect is the string value to expect if the attribute is encoded as a string\n /// \\param expectval is the integer value to return if the attribute matches the expected string\n /// \\return the encoded integer or the integer value associated with the expected string\n virtual intb readSignedIntegerExpectString(const string &expect,intb expectval)=0;\n\n /// \\brief Find and parse a specific attribute in the current element as either a signed integer or a string.\n ///\n /// If the attribute is an integer, its value is parsed and returned.\n /// If the attribute is encoded as a string, it must match an expected string passed to this method.\n /// In this case, a predetermined integer value is passed back, indicating a matching string was parsed.\n /// If the attribute neither matches the expected string nor is an integer, the return value is undefined.\n /// If there is no attribute matching the id, an exception is thrown.\n /// \\param attribId is the specific attribute id to match\n /// \\param expect is the string to expect, if the attribute is not encoded as an integer\n /// \\param expectval is the integer value to return if the attribute matches the expected string\n /// \\return the encoded integer or the integer value associated with the expected string\n virtual intb readSignedIntegerExpectString(const AttributeId &attribId,const string &expect,intb expectval)=0;\n\n /// \\brief Parse the current attribute as an unsigned integer value\n ///\n /// The last attribute, as returned by getNextAttributeId, is treated as an unsigned integer, and its value is returned.\n /// \\return the unsigned integer value associated with the current attribute.\n virtual uintb readUnsignedInteger(void)=0;\n\n /// \\brief Find and parse a specific attribute in the current element as an unsigned integer\n ///\n /// The set of attributes for the current element is searched for a match to the given attribute id.\n /// This attribute is then parsed as an unsigned integer and its value returned.\n /// If there is no attribute matching the id, an exception is thrown.\n /// Parsing via getNextAttributeId is reset.\n /// \\param attribId is the specific attribute id to match\n /// \\return the unsigned integer value\n virtual uintb readUnsignedInteger(const AttributeId &attribId)=0;\n\n /// \\brief Parse the current attribute as a string\n ///\n /// The last attribute, as returned by getNextAttributeId, is returned as a string.\n /// \\return the string associated with the current attribute.\n virtual string readString(void)=0;\n\n /// \\brief Find the specific attribute in the current element and return it as a string\n ///\n /// The set of attributes for the current element is searched for a match to the given attribute id.\n /// This attribute is then returned as a string. If there is no attribute matching the id, and exception is thrown.\n /// Parse via getNextAttributeId is reset.\n /// \\param attribId is the specific attribute id to match\n /// \\return the string associated with the attribute\n virtual string readString(const AttributeId &attribId)=0;\n\n /// \\brief Parse the current attribute as an address space\n ///\n /// The last attribute, as returned by getNextAttributeId, is returned as an address space.\n /// \\return the address space associated with the current attribute.\n virtual AddrSpace *readSpace(void)=0;\n\n /// \\brief Find the specific attribute in the current element and return it as an address space\n ///\n /// Search attributes from the current element for a match to the given attribute id.\n /// Return this attribute as an address space. If there is no attribute matching the id, an exception is thrown.\n /// Parse via getNextAttributeId is reset.\n /// \\param attribId is the specific attribute id to match\n /// \\return the address space associated with the attribute\n virtual AddrSpace *readSpace(const AttributeId &attribId)=0;\n\n /// \\brief Parse the current attribute as a p-code OpCode\n ///\n /// The last attribute, as returned by getNextAttributeId, is returned as an OpCode.\n /// \\return the OpCode associated with the current attribute\n virtual OpCode readOpcode(void)=0;\n\n /// \\brief Find the specific attribute in the current element and return it as an OpCode\n ///\n /// Search attributes from the current element for a match to the given attribute id.\n /// Return this attribute as an OpCode. If there is no matching attribute id, an exception is thrown.\n /// Parse via getNextAttributeId is reset.\n /// \\param attribId is the specific attribute id to match\n /// \\return the OpCode associated with the attribute\n virtual OpCode readOpcode(AttributeId &attribId)=0;\n\n /// \\brief Skip parsing of the next element\n ///\n /// The element skipped is the one that would be opened by the next call to openElement.\n void skipElement(void) {\n uint4 elemId = openElement();\n closeElementSkipping(elemId);\n }\n};\n\n/// \\brief A class for writing structured data to a stream\n///\n/// The resulting encoded data is structured similarly to an XML document. The document contains a nested set\n/// of \\b elements, with labels corresponding to the ElementId class. A single element can hold\n/// zero or more attributes and zero or more child elements. An \\b attribute holds a primitive\n/// data element (bool, integer, string) and is labeled by an AttributeId. The document is written\n/// using a sequence of openElement() and closeElement() calls, intermixed with write*() calls to encode\n/// the data primitives. All primitives written using a write*() call are associated with current open element,\n/// and all write*() calls for one element must come before opening any child element.\n/// The traditional XML element text content can be written using the special ATTRIB_CONTENT AttributeId, which\n/// must be the last write*() call associated with the specific element.\nclass Encoder {\npublic:\n virtual ~Encoder(void) {}\t\t///< Destructor\n\n /// \\brief Begin a new element in the encoding\n ///\n /// The element will have the given ElementId annotation and becomes the \\e current element.\n /// \\param elemId is the given ElementId annotation\n virtual void openElement(const ElementId &elemId)=0;\n\n /// \\brief End the current element in the encoding\n ///\n /// The current element must match the given annotation or an exception is thrown.\n /// \\param elemId is the given (expected) annotation for the current element\n virtual void closeElement(const ElementId &elemId)=0;\n\n /// \\brief Write an annotated boolean value into the encoding\n ///\n /// The boolean data is associated with the given AttributeId annotation and the current open element.\n /// \\param attribId is the given AttributeId annotation\n /// \\param val is boolean value to encode\n virtual void writeBool(const AttributeId &attribId,bool val)=0;\n\n /// \\brief Write an annotated signed integer value into the encoding\n ///\n /// The integer is associated with the given AttributeId annotation and the current open element.\n /// \\param attribId is the given AttributeId annotation\n /// \\param val is the signed integer value to encode\n virtual void writeSignedInteger(const AttributeId &attribId,intb val)=0;\n\n /// \\brief Write an annotated unsigned integer value into the encoding\n ///\n /// The integer is associated with the given AttributeId annotation and the current open element.\n /// \\param attribId is the given AttributeId annotation\n /// \\param val is the unsigned integer value to encode\n virtual void writeUnsignedInteger(const AttributeId &attribId,uintb val)=0;\n\n /// \\brief Write an annotated string into the encoding\n ///\n /// The string is associated with the given AttributeId annotation and the current open element.\n /// \\param attribId is the given AttributeId annotation\n /// \\param val is the string to encode\n virtual void writeString(const AttributeId &attribId,const string &val)=0;\n\n /// \\brief Write an annotated string, using an indexed attribute, into the encoding\n ///\n /// Multiple attributes with a shared name can be written to the same element by calling this method\n /// multiple times with a different \\b index value. The encoding will use attribute ids up to the base id\n /// plus the maximum index passed in. Implementors must be careful to not use other attributes with ids\n /// bigger than the base id within the element taking the indexed attribute.\n /// \\param attribId is the shared AttributeId\n /// \\param index is the unique index to associated with the string\n /// \\param val is the string to encode\n virtual void writeStringIndexed(const AttributeId &attribId,uint4 index,const string &val)=0;\n\n /// \\brief Write an address space reference into the encoding\n ///\n /// The address space is associated with the given AttributeId annotation and the current open element.\n /// \\param attribId is the given AttributeId annotation\n /// \\param spc is the address space to encode\n virtual void writeSpace(const AttributeId &attribId,const AddrSpace *spc)=0;\n\n /// \\brief Write a p-code operation opcode into the encoding, associating it with the given annotation\n ///\n /// \\param attribId is the given annotation\n /// \\param opc is the opcode\n virtual void writeOpcode(const AttributeId &attribId,OpCode opc)=0;\n\n};\n\n/// \\brief An XML based decoder\n///\n/// The underlying transfer encoding is an XML document. The decoder can either be initialized with an\n/// existing Element as the root of the data to transfer, or the ingestStream() method can be invoked\n/// to read the XML document from an input stream, in which case the decoder manages the Document object.\nclass XmlDecode : public Decoder {\n Document *document;\t\t\t\t///< An ingested XML document, owned by \\b this decoder\n const Element *rootElement;\t\t\t///< The root XML element to be decoded\n vector elStack;\t\t///< Stack of currently \\e open elements\n vector iterStack;\t///< Index of next child for each \\e open element\n int4 attributeIndex;\t\t\t\t///< Position of \\e current attribute to parse (in \\e current element)\n int4 scope;\t\t\t\t\t///< Scope of element/attribute tags to look up\n int4 findMatchingAttribute(const Element *el,const string &attribName);\npublic:\n XmlDecode(const AddrSpaceManager *spc,const Element *root,int4 sc=0) : Decoder(spc) {\n document = (Document *)0; rootElement = root; attributeIndex = -1; scope = sc; }\t///< Constructor with preparsed root\n XmlDecode(const AddrSpaceManager *spc,int4 sc=0) : Decoder(spc) {\n document = (Document *)0; rootElement = (const Element *)0; attributeIndex = -1; scope=sc; }\t///< Constructor for use with ingestStream\n const Element *getCurrentXmlElement(void) const { return elStack.back(); }\t///< Get pointer to underlying XML element object\n virtual ~XmlDecode(void);\n virtual void ingestStream(istream &s);\n virtual uint4 peekElement(void);\n virtual uint4 openElement(void);\n virtual uint4 openElement(const ElementId &elemId);\n virtual void closeElement(uint4 id);\n virtual void closeElementSkipping(uint4 id);\n virtual void rewindAttributes(void);\n virtual uint4 getNextAttributeId(void);\n virtual uint4 getIndexedAttributeId(const AttributeId &attribId);\n virtual bool readBool(void);\n virtual bool readBool(const AttributeId &attribId);\n virtual intb readSignedInteger(void);\n virtual intb readSignedInteger(const AttributeId &attribId);\n virtual intb readSignedIntegerExpectString(const string &expect,intb expectval);\n virtual intb readSignedIntegerExpectString(const AttributeId &attribId,const string &expect,intb expectval);\n virtual uintb readUnsignedInteger(void);\n virtual uintb readUnsignedInteger(const AttributeId &attribId);\n virtual string readString(void);\n virtual string readString(const AttributeId &attribId);\n virtual AddrSpace *readSpace(void);\n virtual AddrSpace *readSpace(const AttributeId &attribId);\n virtual OpCode readOpcode(void);\n virtual OpCode readOpcode(AttributeId &attribId);\n};\n\n/// \\brief An XML based encoder\n///\n/// The underlying transfer encoding is an XML document. The encoder is initialized with a stream which will\n/// receive the XML document as calls are made on the encoder.\nclass XmlEncode : public Encoder {\n friend class XmlDecode;\n enum {\n tag_start = 0,\t\t\t///< Tag has been opened, attributes can be written\n tag_content = 1,\t\t\t///< Opening tag and content have been written\n tag_stop = 2\t\t\t///< No tag is currently being written\n };\n static const char spaces[];\t\t///< Array of ' ' characters for emitting indents\n static const int4 MAX_SPACES;\t\t///< Maximum number of leading spaces when indenting XML\n ostream &outStream;\t\t\t///< The stream receiving the encoded data\n int4 tagStatus;\t\t\t///< Stage of writing an element tag\n int4 depth;\t\t\t\t///< Depth of open elements\n bool doFormatting;\t\t\t///< \\b true if encoder should indent and emit newlines\n void newLine(void);\t\t\t///< Emit a newline and proper indenting for the next tag\npublic:\n XmlEncode(ostream &s,bool doFormat=true) : outStream(s) { depth=0; tagStatus=tag_stop; doFormatting=doFormat; } ///< Construct from a stream\n virtual void openElement(const ElementId &elemId);\n virtual void closeElement(const ElementId &elemId);\n virtual void writeBool(const AttributeId &attribId,bool val);\n virtual void writeSignedInteger(const AttributeId &attribId,intb val);\n virtual void writeUnsignedInteger(const AttributeId &attribId,uintb val);\n virtual void writeString(const AttributeId &attribId,const string &val);\n virtual void writeStringIndexed(const AttributeId &attribId,uint4 index,const string &val);\n virtual void writeSpace(const AttributeId &attribId,const AddrSpace *spc);\n virtual void writeOpcode(const AttributeId &attribId,OpCode opc);\n};\n\n/// \\brief Protocol format for PackedEncode and PackedDecode classes\n///\n/// All bytes in the encoding are expected to be non-zero. Element encoding looks like\n/// - 01xiiiii is an element start\n/// - 10xiiiii is an element end\n/// - 11xiiiii is an attribute start\n///\n/// Where iiiii is the (first) 5 bits of the element/attribute id.\n/// If x=0, the id is complete. If x=1, the next byte contains 7 more bits of the id: 1iiiiiii\n///\n/// After an attribute start, there follows a \\e type byte: ttttllll, where the first 4 bits indicate the\n/// type of attribute and final 4 bits are a \\b length \\b code. The types are:\n/// - 1 = boolean (lengthcode=0 for false, lengthcode=1 for true)\n/// - 2 = positive signed integer\n/// - 3 = negative signed integer (stored in negated form)\n/// - 4 = unsigned integer\n/// - 5 = basic address space (encoded as the integer index of the space)\n/// - 6 = special address space (lengthcode 0=>stack 1=>join 2=>fspec 3=>iop)\n/// - 7 = string\n///\n/// All attribute types except \\e boolean and \\e special, have an encoded integer after the \\e type byte.\n/// The \\b length \\b code, indicates the number bytes used to encode the integer, 7-bits of info per byte, 1iiiiiii.\n/// A \\b length \\b code of zero is used to encode an integer value of 0, with no following bytes.\n///\n/// For strings, the integer encoded after the \\e type byte, is the actual length of the string. The\n/// string data itself is stored immediately after the length integer using UTF8 format.\nnamespace PackedFormat {\n static const uint1 HEADER_MASK = 0xc0;\t\t///< Bits encoding the record type\n static const uint1 ELEMENT_START = 0x40;\t\t///< Header for an element start record\n static const uint1 ELEMENT_END = 0x80;\t\t///< Header for an element end record\n static const uint1 ATTRIBUTE = 0xc0;\t\t\t///< Header for an attribute record\n static const uint1 HEADEREXTEND_MASK = 0x20;\t\t///< Bit indicating the id extends into the next byte\n static const uint1 ELEMENTID_MASK = 0x1f;\t\t///< Bits encoding (part of) the id in the record header\n static const uint1 RAWDATA_MASK = 0x7f;\t\t///< Bits of raw data in follow-on bytes\n static const int4 RAWDATA_BITSPERBYTE = 7;\t\t///< Number of bits used in a follow-on byte\n static const uint1 RAWDATA_MARKER = 0x80;\t\t///< The unused bit in follow-on bytes. (Always set to 1)\n static const int4 TYPECODE_SHIFT = 4;\t\t\t///< Bit position of the type code in the type byte\n static const uint1 LENGTHCODE_MASK = 0xf;\t\t///< Bits in the type byte forming the length code\n static const uint1 TYPECODE_BOOLEAN = 1;\t\t///< Type code for the \\e boolean type\n static const uint1 TYPECODE_SIGNEDINT_POSITIVE = 2;\t///< Type code for the \\e signed \\e positive \\e integer type\n static const uint1 TYPECODE_SIGNEDINT_NEGATIVE = 3;\t///< Type code for the \\e signed \\e negative \\e integer type\n static const uint1 TYPECODE_UNSIGNEDINT = 4;\t\t///< Type code for the \\e unsigned \\e integer type\n static const uint1 TYPECODE_ADDRESSSPACE = 5;\t\t///< Type code for the \\e address \\e space type\n static const uint1 TYPECODE_SPECIALSPACE = 6;\t\t///< Type code for the \\e special \\e address \\e space type\n static const uint1 TYPECODE_STRING = 7;\t\t///< Type code for the \\e string type\n static const uint4 SPECIALSPACE_STACK = 0;\t\t///< Special code for the \\e stack space\n static const uint4 SPECIALSPACE_JOIN = 1;\t\t///< Special code for the \\e join space\n static const uint4 SPECIALSPACE_FSPEC = 2;\t\t///< Special code for the \\e fspec space\n static const uint4 SPECIALSPACE_IOP = 3;\t\t///< Special code for the \\e iop space\n static const uint4 SPECIALSPACE_SPACEBASE = 4;\t///< Special code for a \\e spacebase space\n}\n\n/// \\brief A byte-based decoder designed to marshal info to the decompiler efficiently\n///\n/// The decoder expects an encoding as described in PackedFormat. When ingested, the stream bytes are\n/// held in a sequence of arrays (ByteChunk). During decoding, \\b this object maintains a Position in the\n/// stream at the start and end of the current open element, and a Position of the next attribute to read to\n/// facilitate getNextAttributeId() and associated read*() methods.\nclass PackedDecode : public Decoder {\npublic:\n static const int4 BUFFER_SIZE;\t///< The size, in bytes, of a single cached chunk of the input stream\nprivate:\n /// \\brief A bounded array of bytes\n class ByteChunk {\n friend class PackedDecode;\n uint1 *start;\t\t\t///< Start of the byte array\n uint1 *end;\t\t\t\t///< End of the byte array\n public:\n ByteChunk(uint1 *s,uint1 *e) { start = s; end = e; }\t///< Constructor\n };\n /// \\brief An iterator into input stream\n class Position {\n friend class PackedDecode;\n list::const_iterator seqIter;\t///< Current byte sequence\n uint1 *current;\t\t\t\t///< Current position in sequence\n uint1 *end;\t\t\t\t\t///< End of current sequence\n };\n list inStream;\t\t///< Incoming raw data as a sequence of byte arrays\n Position startPos;\t\t\t///< Position at the start of the current open element\n Position curPos;\t\t\t///< Position of the next attribute as returned by getNextAttributeId\n Position endPos;\t\t\t///< Ending position after all attributes in current open element\n bool attributeRead;\t\t\t///< Has the last attribute returned by getNextAttributeId been read\n uint1 getByte(Position &pos) { return *pos.current; }\t///< Get the byte at the current position, do not advance\n uint1 getBytePlus1(Position &pos);\t///< Get the byte following the current byte, do not advance position\n uint1 getNextByte(Position &pos);\t///< Get the byte at the current position and advance to the next byte\n void advancePosition(Position &pos,int4 skip);\t///< Advance the position by the given number of bytes\n uint8 readInteger(int4 len);\t\t///< Read an integer from the \\e current position given its length in bytes\n uint4 readLengthCode(uint1 typeByte) { return ((uint4)typeByte & PackedFormat::LENGTHCODE_MASK); }\t///< Extract length code from type byte\n void findMatchingAttribute(const AttributeId &attribId);\t///< Find attribute matching the given id in open element\n void skipAttribute(void);\t\t///< Skip over the attribute at the current position\n void skipAttributeRemaining(uint1 typeByte);\t///< Skip over remaining attribute data, after a mismatch\nprotected:\n uint1 *allocateNextInputBuffer(int4 pad);\t///< Allocate the next chunk of space in the input stream\n void endIngest(int4 bufPos);\t\t///< Finish set up for reading input stream\npublic:\n PackedDecode(const AddrSpaceManager *spcManager) : Decoder(spcManager) {}\t///< Constructor\n virtual ~PackedDecode(void);\n virtual void ingestStream(istream &s);\n virtual uint4 peekElement(void);\n virtual uint4 openElement(void);\n virtual uint4 openElement(const ElementId &elemId);\n virtual void closeElement(uint4 id);\n virtual void closeElementSkipping(uint4 id);\n virtual void rewindAttributes(void);\n virtual uint4 getNextAttributeId(void);\n virtual uint4 getIndexedAttributeId(const AttributeId &attribId);\n virtual bool readBool(void);\n virtual bool readBool(const AttributeId &attribId);\n virtual intb readSignedInteger(void);\n virtual intb readSignedInteger(const AttributeId &attribId);\n virtual intb readSignedIntegerExpectString(const string &expect,intb expectval);\n virtual intb readSignedIntegerExpectString(const AttributeId &attribId,const string &expect,intb expectval);\n virtual uintb readUnsignedInteger(void);\n virtual uintb readUnsignedInteger(const AttributeId &attribId);\n virtual string readString(void);\n virtual string readString(const AttributeId &attribId);\n virtual AddrSpace *readSpace(void);\n virtual AddrSpace *readSpace(const AttributeId &attribId);\n virtual OpCode readOpcode(void);\n virtual OpCode readOpcode(AttributeId &attribId);\n};\n\n/// \\brief A byte-based encoder designed to marshal from the decompiler efficiently\n///\n/// See PackedDecode for details of the encoding format.\nclass PackedEncode : public Encoder {\n ostream &outStream;\t\t\t///< The stream receiving the encoded data\n void writeHeader(uint1 header,uint4 id);\t///< Write a header, element or attribute, to stream\n void writeInteger(uint1 typeByte,uint8 val);\t///< Write an integer value to the stream\npublic:\n PackedEncode(ostream &s) : outStream(s) {} ///< Construct from a stream\n virtual void openElement(const ElementId &elemId);\n virtual void closeElement(const ElementId &elemId);\n virtual void writeBool(const AttributeId &attribId,bool val);\n virtual void writeSignedInteger(const AttributeId &attribId,intb val);\n virtual void writeUnsignedInteger(const AttributeId &attribId,uintb val);\n virtual void writeString(const AttributeId &attribId,const string &val);\n virtual void writeStringIndexed(const AttributeId &attribId,uint4 index,const string &val);\n virtual void writeSpace(const AttributeId &attribId,const AddrSpace *spc);\n virtual void writeOpcode(const AttributeId &attribId,OpCode opc);\n};\n\n/// An exception is thrown if the position currently points to the last byte in the stream\n/// \\param pos is the position in the stream to look ahead from\n/// \\return the next byte\ninline uint1 PackedDecode::getBytePlus1(Position &pos)\n\n{\n uint1 *ptr = pos.current + 1;\n if (ptr == pos.end) {\n list::const_iterator iter = pos.seqIter;\n ++iter;\n if (iter == inStream.end())\n throw DecoderError(\"Unexpected end of stream\");\n ptr = (*iter).start;\n }\n return *ptr;\n}\n\n/// An exception is thrown if there are no additional bytes in the stream\n/// \\param pos is the position of the byte\n/// \\return the byte at the current position\ninline uint1 PackedDecode::getNextByte(Position &pos)\n\n{\n uint1 res = *pos.current;\n pos.current += 1;\n if (pos.current != pos.end)\n return res;\n ++pos.seqIter;\n if (pos.seqIter == inStream.end())\n throw DecoderError(\"Unexpected end of stream\");\n pos.current = (*pos.seqIter).start;\n pos.end = (*pos.seqIter).end;\n return res;\n}\n\n/// An exception is thrown of position is advanced past the end of the stream\n/// \\param pos is the position being advanced\n/// \\param skip is the number of bytes to advance\ninline void PackedDecode::advancePosition(Position &pos,int4 skip)\n\n{\n while(pos.end - pos.current <= skip) {\n skip -= (pos.end - pos.current);\n ++pos.seqIter;\n if (pos.seqIter == inStream.end())\n throw DecoderError(\"Unexpected end of stream\");\n pos.current = (*pos.seqIter).start;\n pos.end = (*pos.seqIter).end;\n }\n pos.current += skip;\n}\n\n/// Allocate an array of BUFFER_SIZE bytes and add it to the in-memory stream\n/// \\param pad is the number of bytes of padding to add to the allocation size, above BUFFER_SIZE\n/// \\return the newly allocated buffer\ninline uint1 *PackedDecode::allocateNextInputBuffer(int4 pad)\n\n{\n uint1 *buf = new uint1[BUFFER_SIZE + pad];\n inStream.emplace_back(buf,buf+BUFFER_SIZE);\n return buf;\n}\n\n/// \\param header is the type of header\n/// \\param id is the id associated with the element or attribute\ninline void PackedEncode::writeHeader(uint1 header,uint4 id)\n\n{\n if (id > 0x1f) {\n header |= PackedFormat::HEADEREXTEND_MASK;\n header |= (id >> PackedFormat::RAWDATA_BITSPERBYTE);\n uint1 extendByte = (id & PackedFormat::RAWDATA_MASK) | PackedFormat::RAWDATA_MARKER;\n outStream.put(header);\n outStream.put(extendByte);\n }\n else {\n header |= id;\n outStream.put(header);\n }\n}\n\nextern ElementId ELEM_UNKNOWN;\t\t///< Special element to represent an element with an unrecognized name\nextern AttributeId ATTRIB_UNKNOWN;\t///< Special attribute to represent an attribute with an unrecognized name\nextern AttributeId ATTRIB_CONTENT;\t///< Special attribute for XML text content of an element\n\n/// The name is looked up in the scoped list of attributes. If the attribute is not in the list, a special\n/// placeholder attribute, ATTRIB_UNKNOWN, is returned as a placeholder for attributes with unrecognized names.\n/// \\param nm is the name of the attribute\n/// \\param scope is the id of the scope in which to lookup of the name\n/// \\return the associated id\ninline uint4 AttributeId::find(const string &nm,int4 scope)\n\n{\n if (scope == 0) {\t\t// Current only support reverse look up for scope 0\n unordered_map::const_iterator iter = lookupAttributeId.find(nm);\n if (iter != lookupAttributeId.end())\n return (*iter).second;\n }\n return ATTRIB_UNKNOWN.id;\n}\n\n/// The name is looked up in the scoped list of elements. If the element is not in the list, a special\n/// placeholder element, ELEM_UNKNOWN, is returned as a placeholder for elements with unrecognized names.\n/// \\param nm is the name of the element\n/// \\param scope is the id of the scope in which to search\n/// \\return the associated id\ninline uint4 ElementId::find(const string &nm,int4 scope)\n\n{\n if (scope == 0) {\n unordered_map::const_iterator iter = lookupElementId.find(nm);\n if (iter != lookupElementId.end())\n return (*iter).second;\n }\n return ELEM_UNKNOWN.id;\n}\n\nextern AttributeId ATTRIB_ALIGN;\t///< Marshaling attribute \"align\"\nextern AttributeId ATTRIB_BIGENDIAN;\t///< Marshaling attribute \"bigendian\"\nextern AttributeId ATTRIB_CONSTRUCTOR;\t///< Marshaling attribute \"constructor\"\nextern AttributeId ATTRIB_DESTRUCTOR;\t///< Marshaling attribute \"destructor\"\nextern AttributeId ATTRIB_EXTRAPOP;\t///< Marshaling attribute \"extrapop\"\nextern AttributeId ATTRIB_FORMAT;\t///< Marshaling attribute \"format\"\nextern AttributeId ATTRIB_HIDDENRETPARM;\t///< Marshaling attribute \"hiddenretparm\"\nextern AttributeId ATTRIB_ID;\t\t///< Marshaling attribute \"id\"\nextern AttributeId ATTRIB_INDEX;\t///< Marshaling attribute \"index\"\nextern AttributeId ATTRIB_INDIRECTSTORAGE;\t///< Marshaling attribute \"indirectstorage\"\nextern AttributeId ATTRIB_METATYPE;\t///< Marshaling attribute \"metatype\"\nextern AttributeId ATTRIB_MODEL;\t///< Marshaling attribute \"model\"\nextern AttributeId ATTRIB_NAME;\t\t///< Marshaling attribute \"name\"\nextern AttributeId ATTRIB_NAMELOCK;\t///< Marshaling attribute \"namelock\"\nextern AttributeId ATTRIB_OFFSET;\t///< Marshaling attribute \"offset\"\nextern AttributeId ATTRIB_READONLY;\t///< Marshaling attribute \"readonly\"\nextern AttributeId ATTRIB_REF;\t\t///< Marshaling attribute \"ref\"\nextern AttributeId ATTRIB_SIZE;\t\t///< Marshaling attribute \"size\"\nextern AttributeId ATTRIB_SPACE;\t///< Marshaling attribute \"space\"\nextern AttributeId ATTRIB_THISPTR;\t///< Marshaling attribute \"thisptr\"\nextern AttributeId ATTRIB_TYPE;\t\t///< Marshaling attribute \"type\"\nextern AttributeId ATTRIB_TYPELOCK;\t///< Marshaling attribute \"typelock\"\nextern AttributeId ATTRIB_VAL;\t\t///< Marshaling attribute \"val\"\nextern AttributeId ATTRIB_VALUE;\t///< Marshaling attribute \"value\"\nextern AttributeId ATTRIB_WORDSIZE;\t///< Marshaling attribute \"wordsize\"\nextern AttributeId ATTRIB_STORAGE;\t///< Marshaling attribute \"storage\"\nextern AttributeId ATTRIB_STACKSPILL;\t///< Marshaling attribute \"stackspill\"\n\nextern ElementId ELEM_DATA;\t\t///< Marshaling element \\\nextern ElementId ELEM_INPUT;\t\t///< Marshaling element \\\nextern ElementId ELEM_OFF;\t\t///< Marshaling element \\\nextern ElementId ELEM_OUTPUT;\t\t///< Marshaling element \\\nextern ElementId ELEM_RETURNADDRESS;\t///< Marshaling element \\\nextern ElementId ELEM_SYMBOL;\t\t///< Marshaling element \\\nextern ElementId ELEM_TARGET;\t\t///< Marshaling element \\\nextern ElementId ELEM_VAL;\t\t///< Marshaling element \\\nextern ElementId ELEM_VALUE;\t\t///< Marshaling element \\\nextern ElementId ELEM_VOID;\t\t///< Marshaling element \\\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/memstate.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"memstate.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\n/// This is a static convenience routine for decoding a value from a sequence of bytes depending\n/// on the desired endianness\n/// \\param ptr is the pointer to the bytes to decode\n/// \\param size is the number of bytes\n/// \\param bigendian is \\b true if the bytes are encoded in big endian form\n/// \\return the decoded value\nuintb MemoryBank::constructValue(const uint1 *ptr,int4 size,bool bigendian)\n\n{ \n uintb res = 0;\n\n if (bigendian) {\n for(int4 i=0;i=0;--i) {\n res <<= 8;\n res += (uintb) ptr[i];\n }\n }\n return res;\n}\n\n/// This is a static convenience routine for encoding bytes from a given value, depending on\n/// the desired endianness\n/// \\param ptr is a pointer to the location to write the encoded bytes\n/// \\param val is the value to be encoded\n/// \\param size is the number of bytes to encode\n/// \\param bigendian is \\b true if a big endian encoding is desired\nvoid MemoryBank::deconstructValue(uint1 *ptr,uintb val,int4 size,bool bigendian)\n\n{\n if (bigendian) {\n for(int4 i=size-1;i>=0;--i) {\n ptr[i] = (uint1) (val & 0xff);\n val >>= 8;\n }\n }\n else {\n for(int4 i=0;i>= 8;\n }\n }\n}\n\n/// A MemoryBank must be associated with a specific address space, have a preferred or natural\n/// \\e wordsize and a natural \\e pagesize. Both the \\e wordsize and \\e pagesize must be a power of 2.\n/// \\param spc is the associated address space\n/// \\param ws is the number of bytes in the preferred wordsize\n/// \\param ps is the number of bytes in a page\nMemoryBank::MemoryBank(AddrSpace *spc,int4 ws,int4 ps)\n\n{\n space = spc;\n wordsize = ws;\n pagesize = ps;\n}\n\n/// This routine only retrieves data from a single \\e page in the memory bank. Bytes need not\n/// be retrieved from the exact start of a page, but all bytes must come from \\e one page.\n/// A page is a fixed number of bytes, and the address of a page is always aligned based\n/// on that number of bytes. This routine may be overridden for a page based implementation\n/// of the MemoryBank. The default implementation retrieves the page as aligned words\n/// using the find method.\n/// \\param addr is the \\e aligned offset of the desired page\n/// \\param res is a pointer to where fetched data should be written\n/// \\param skip is the offset \\e into \\e the \\e page to get the bytes from\n/// \\param size is the number of bytes to retrieve\nvoid MemoryBank::getPage(uintb addr,uint1 *res,int4 skip,int4 size) const\n\n{ // Default implementation just iterates using find\n // but could be optimized\n uintb ptraddr = addr + skip;\n uintb endaddr = ptraddr + size;\n uintb startalign = ptraddr & ~((uintb)(wordsize-1));\n uintb endalign = endaddr & ~((uintb)(wordsize-1));\n if ((endaddr & ((uintb)(wordsize-1))) != 0)\n endalign += wordsize;\n\n uintb curval;\n bool bswap = ((HOST_ENDIAN==1) != space->isBigEndian());\n uint1 *ptr;\n do {\n curval = find(startalign);\n if (bswap)\n curval = byte_swap(curval,wordsize);\n ptr = (uint1 *)&curval;\n int4 sz = wordsize;\n if (startalign < addr) {\n ptr += (addr-startalign);\n sz = wordsize - (addr-startalign);\n }\n if (startalign + wordsize > endaddr)\n sz -= (startalign + wordsize -endaddr);\n memcpy(res,ptr,sz);\n res += sz;\n startalign += wordsize;\n } while(startalign != endalign);\n}\n\n/// This routine writes data only to a single \\e page of the memory bank. Bytes need not be\n/// written to the exact start of the page, but all bytes must be written to only one page\n/// when using this routine. A page is a\n/// fixed number of bytes, and the address of a page is always aligned based on this size.\n/// This routine may be overridden for a page based implementation of the MemoryBank. The\n/// default implementation writes the page as a sequence of aligned words, using the\n/// insert method.\n/// \\param addr is the \\e aligned offset of the desired page\n/// \\param val is a pointer to the bytes to be written into the page\n/// \\param skip is the offset \\e into \\e the \\e page where bytes will be written\n/// \\param size is the number of bytes to be written\nvoid MemoryBank::setPage(uintb addr,const uint1 *val,int4 skip,int4 size)\n \n{ // Default implementation just iterates using insert\n // but could be optimized\n uintb ptraddr = addr + skip;\n uintb endaddr = ptraddr + size;\n uintb startalign = ptraddr & ~((uintb)(wordsize-1));\n uintb endalign = endaddr & ~((uintb)(wordsize-1));\n if ((endaddr & ((uintb)(wordsize-1))) != 0)\n endalign += wordsize;\n\n uintb curval;\n bool bswap = ((HOST_ENDIAN==1) != space->isBigEndian());\n uint1 *ptr;\n do {\n ptr = (uint1 *)&curval;\n int4 sz = wordsize;\n if (startalign < addr) {\n ptr += (addr-startalign);\n sz = wordsize - (addr-startalign);\n }\n if (startalign + wordsize > endaddr)\n sz -= (startalign + wordsize - endaddr);\n if (sz != wordsize) {\n curval = find(startalign); // Part of word is copied from underlying\n memcpy(ptr,val,sz);\t // Rest is taken from -val-\n }\n else\n curval = *((const uintb *)val); // -val- supplies entire word\n if (bswap)\n curval = byte_swap(curval,wordsize);\n insert(startalign,curval);\n val += sz;\n startalign += wordsize;\n } while(startalign != endalign);\n}\n\n/// This routine is used to set a single value in the memory bank at an arbitrary address\n/// It takes into account the endianness of the associated address space when encoding the\n/// value as bytes in the bank. The value is broken up into aligned pieces of \\e wordsize and\n/// the actual \\b write is performed with the insert routine. If only parts of aligned words\n/// are written to, then the remaining parts are filled in with the original value, via the\n/// find routine.\n/// \\param offset is the start of the byte range to write\n/// \\param size is the number of bytes in the range to write\n/// \\param val is the value to be written\nvoid MemoryBank::setValue(uintb offset,int4 size,uintb val)\n\n{\n uintb alignmask = (uintb)(wordsize-1);\n uintb ind = offset & (~alignmask);\n int4 skip = offset & alignmask;\n int4 size1 = wordsize-skip;\n int4 size2;\n int4 gap;\n uintb val1,val2;\n\n if (size > size1) {\t\t// We have spill over\n size2 = size - size1;\n val1 = find(ind);\n val2 = find(ind+wordsize);\n gap = wordsize - size2;\n }\n else {\n if (size == wordsize) {\n insert(ind,val);\n return;\n }\n val1 = find(ind);\n val2 = 0;\n gap = size1-size;\n size1 = size;\n size2 = 0;\n }\n\n skip = skip * 8;\t\t// Convert from byte skip to bit skip\n gap = gap * 8;\t\t// Convert from byte to bits\n if (space->isBigEndian()) {\n if (size2 == 0) {\n val1 &= ~(calc_mask(size1)<> 8*size2;\n insert(ind,val1);\n val2 &= (~((uintb)0)) >> 8*size2;\n val2 |= val << gap;\n insert(ind+wordsize,val2);\n }\n }\n else {\n if (size2 == 0) {\n val1 &= ~(calc_mask(size1)<> 8*size1;\n val1 |= val << skip;\n insert(ind,val1);\n val2 &= (~((uintb)0)) << 8*size2;\n val2 |= val >> 8*size1;\n insert(ind+wordsize,val2);\n }\n }\n}\n\n/// This routine gets the value from a range of bytes at an arbitrary address.\n/// It takes into account the endianness of the underlying space when decoding the value.\n/// The value is constructed by making one or more aligned word queries, using the find method.\n/// The desired value may span multiple words and is reconstructed properly.\n/// \\param offset is the start of the byte range encoding the value\n/// \\param size is the number of bytes in the range\n/// \\return the decoded value\nuintb MemoryBank::getValue(uintb offset,int4 size) const\n\n{\n uintb res;\n \n uintb alignmask = (uintb) (wordsize-1);\n uintb ind = offset & (~alignmask);\n int4 skip = offset & alignmask;\n int4 size1 = wordsize-skip;\n int4 size2;\n int4 gap;\n uintb val1,val2;\n if (size > size1) {\t\t// We have spill over\n size2 = size - size1;\n val1 = find(ind);\n val2 = find(ind+wordsize);\n gap = wordsize - size2;\n }\n else {\n val1 = find(ind);\n val2 = 0;\n if (size == wordsize)\n return val1;\n gap = size1-size;\n size1 = size;\n size2 = 0;\n }\n\n if (space->isBigEndian()) {\n if (size2 == 0)\n res = val1>>(8*gap);\n else\n res = (val1<<(8*size2)) | (val2 >> (8*gap));\n }\n else {\n if (size2 == 0)\n res = val1 >> (skip*8);\n else\n res = (val1>>(skip*8)) | (val2<<(size1*8) );\n }\n res &= (uintb)calc_mask(size);\n return res;\n}\n\n/// This the most general method for writing a sequence of bytes into the memory bank.\n/// There is no restriction on the offset to write to or the number of bytes to be written,\n/// except that the range must be contained in the address space.\n/// \\param offset is the start of the byte range to be written\n/// \\param size is the number of bytes to write\n/// \\param val is a pointer to the sequence of bytes to be written into the bank\nvoid MemoryBank::setChunk(uintb offset,int4 size,const uint1 *val)\n\n{\n int4 cursize;\n int4 count;\n uintb pagemask = (uintb) (pagesize - 1);\n uintb offalign;\n int4 skip;\n\n count = 0;\n while(count < size) {\n cursize = pagesize;\n offalign = offset & ~pagemask;\n skip = 0;\n if (offalign != offset) {\n skip = offset - offalign;\n cursize -= skip;\n }\n if (size - count < cursize)\n cursize = size - count;\n setPage(offalign,val,skip,cursize);\n count += cursize;\n offset += cursize;\n val += cursize;\n }\n}\n\n/// This is the most general method for reading a sequence of bytes from the memory bank.\n/// There is no restriction on the offset or the number of bytes to read, except that the\n/// range must be contained in the address space.\n/// \\param offset is the start of the byte range to read\n/// \\param size is the number of bytes to read\n/// \\param res is a pointer to where the retrieved bytes should be stored\nvoid MemoryBank::getChunk(uintb offset,int4 size,uint1 *res) const\n\n{\n int4 cursize,count;\n uintb pagemask = (uintb) (pagesize-1);\n uintb offalign;\n int4 skip;\n\n count = 0;\n while(count < size) {\n cursize = pagesize;\n offalign = offset & ~pagemask;\n skip = 0;\n if (offalign != offset) {\n skip = offset-offalign;\n cursize -= skip;\n }\n if (size - count < cursize)\n cursize = size - count;\n getPage(offalign,res,skip,cursize);\n count += cursize;\n offset += cursize;\n res += cursize;\n }\n}\n\n/// Find an aligned word from the bank. First an attempt is made to fetch the data from the\n/// LoadImage. If this fails, the value is returned as 0.\n/// \\param addr is the address of the word to fetch\n/// \\return the fetched value\nuintb MemoryImage::find(uintb addr) const\n\n{ // Assume that -addr- is word aligned\n uintb res = 0;\t\t// Make sure all bytes start as 0, as load may not fill all bytes\n AddrSpace *spc = getSpace();\n try {\n uint1 *ptr = (uint1 *)&res;\n ptr += (HOST_ENDIAN==1) ? (sizeof(uintb) - getWordSize()) : 0;\n loader->loadFill(ptr,getWordSize(),Address(spc,addr));\n } catch(DataUnavailError &err) {\n // Pages not mapped in the load image, are assumed to be zero\n res = 0;\n }\n if ((HOST_ENDIAN==1) != spc->isBigEndian())\n res = byte_swap(res,getWordSize());\n return res;\n}\n\n/// Retrieve an aligned page from the bank. First an attempt is made to retrieve the\n/// page from the LoadImage, which may do its own zero filling. If the attempt fails, the\n/// page is entirely filled in with zeros.\nvoid MemoryImage::getPage(uintb addr,uint1 *res,int4 skip,int4 size) const\n\n{ // Assume that -addr- is page aligned\n AddrSpace *spc = getSpace();\n\n try {\n loader->loadFill(res,size,Address(spc,addr+skip));\n }\n catch(DataUnavailError &err) {\n // Pages not mapped in the load image, are assumed to be zero\n for(int4 i=0;i::iterator iter;\n\n uint1 *pageptr;\n\n iter = page.find(pageaddr);\n if (iter != page.end())\n pageptr = (*iter).second;\n else {\n pageptr = new uint1[getPageSize()];\n page[pageaddr] = pageptr;\n if (underlie == (MemoryBank *)0) {\n for(int4 i=0;igetPage(pageaddr,pageptr,0,getPageSize());\n }\n \n uintb pageoffset = addr & ((uintb)(getPageSize()-1));\n deconstructValue(pageptr + pageoffset,val,getWordSize(),getSpace()->isBigEndian());\n}\n\n/// This derived method first looks for the aligned word in the mapped pages. If the\n/// address is not mapped, the search is forwarded to the \\e underlying memory bank.\n/// If there is no underlying bank, zero is returned.\n/// \\param addr is the aligned offset of the word\n/// \\return the retrieved value\nuintb MemoryPageOverlay::find(uintb addr) const\n\n{\n uintb pageaddr = addr & ~((uintb)(getPageSize()-1));\n map::const_iterator iter;\n\n iter = page.find(pageaddr);\n if (iter == page.end()) {\n if (underlie == (MemoryBank *)0)\n return (uintb)0;\n return underlie->find(addr);\n }\n\n const uint1 *pageptr = (*iter).second;\n\n uintb pageoffset = addr & ((uintb)(getPageSize()-1));\n return constructValue(pageptr+pageoffset,getWordSize(),getSpace()->isBigEndian());\n}\n\n/// The desired page is looked for in the page cache. If it doesn't exist, the\n/// request is forwarded to \\e underlying bank. If there is no underlying bank, the\n/// result buffer is filled with zeros.\n/// \\param addr is the aligned offset of the page\n/// \\param res is the pointer to where retrieved bytes should be stored\n/// \\param skip is the offset \\e into \\e the \\e page from where bytes should be retrieved\n/// \\param size is the number of bytes to retrieve\nvoid MemoryPageOverlay::getPage(uintb addr,uint1 *res,int4 skip,int4 size) const\n\n{\n map::const_iterator iter;\n\n iter = page.find(addr);\n if (iter == page.end()) {\n if (underlie == (MemoryBank *)0) {\n for(int4 i=0;igetPage(addr,res,skip,size);\n return;\n }\n const uint1 *pageptr = (*iter).second;\n memcpy(res,pageptr+skip,size);\n}\n\n/// First, a cached version of the desired page is searched for via its address. If it doesn't\n/// exist, it is created, and its initial value is filled via the \\e underlying bank. The bytes\n/// to be written are then copied into the cached page.\n/// \\param addr is the aligned offset of the page to write\n/// \\param val is a pointer to bytes to be written into the page\n/// \\param skip is the offset \\e into \\e the \\e page where bytes should be written\n/// \\param size is the number of bytes to write\nvoid MemoryPageOverlay::setPage(uintb addr,const uint1 *val,int4 skip,int4 size)\n\n{\n map::iterator iter;\n uint1 *pageptr;\n\n iter = page.find(addr);\n if (iter == page.end()) {\n pageptr = new uint1[getPageSize()];\n page[addr] = pageptr;\n if (size != getPageSize()) {\n if (underlie == (MemoryBank *)0) {\n\tfor(int4 i=0;igetPage(addr,pageptr,0,getPageSize());\n }\n }\n else\n pageptr = (*iter).second;\n\n memcpy(pageptr+skip,val,size);\n}\n\n/// A page overlay memory bank needs all the parameters for a generic memory bank\n/// and it needs to know the underlying memory bank being overlayed.\n/// \\param spc is the address space associated with the memory bank\n/// \\param ws is the number of bytes in the preferred wordsize (must be power of 2)\n/// \\param ps is the number of bytes in a page (must be power of 2)\n/// \\param ul is the underlying MemoryBank\nMemoryPageOverlay::MemoryPageOverlay(AddrSpace *spc,int4 ws,int4 ps,MemoryBank *ul)\n : MemoryBank(spc,ws,ps)\n{\n underlie = ul;\n}\n\nMemoryPageOverlay::~MemoryPageOverlay(void)\n\n{\n map::iterator iter;\n\n for(iter=page.begin();iter!=page.end();++iter)\n delete [] (*iter).second;\n}\n\n/// Write the value into the hashtable, using \\b addr as a key.\n/// \\param addr is the aligned address of the word being written\n/// \\param val is the value of the word to write\nvoid MemoryHashOverlay::insert(uintb addr,uintb val)\n\n{\n int4 size = address.size();\n uintb offset = (addr>>alignshift) % size;\n for(int4 i=0;i>alignshift) % size;\n for(int4 i=0;ifind(addr);\n}\n\n/// A MemoryBank implemented as a hash table needs everything associated with a generic\n/// memory bank, but the constructor also needs to know the size of the hashtable and\n/// the underlying memorybank to forward reads and writes to.\n/// \\param spc is the address space associated with the memory bank\n/// \\param ws is the number of bytes in the preferred wordsize (must be power of 2)\n/// \\param ps is the number of bytes in a page (must be a power of 2)\n/// \\param hashsize is the maximum number of entries in the hashtable\n/// \\param ul is the underlying memory bank being overlayed\nMemoryHashOverlay::MemoryHashOverlay(AddrSpace *spc,int4 ws,int4 ps,int4 hashsize,MemoryBank *ul)\n : MemoryBank(spc,ws,ps), address(hashsize,0xBADBEEF), value(hashsize,0)\n{\n underlie = ul;\n collideskip = 1023;\n\n uint4 tmp = ws - 1;\n alignshift = 0;\n while(tmp != 0) {\n alignshift += 1;\n tmp >>= 1;\n }\n}\n\n/// MemoryBanks associated with specific address spaces must be registers with this MemoryState\n/// via this method. Each address space that will be used during emulation must be registered\n/// separately. The MemoryState object does \\e not assume responsibility for freeing the MemoryBank\n/// \\param bank is a pointer to the MemoryBank to be registered\nvoid MemoryState::setMemoryBank(MemoryBank *bank)\n\n{\n AddrSpace *spc = bank->getSpace();\n int4 index = spc->getIndex();\n\n while(index >= memspace.size())\n memspace.push_back((MemoryBank *)0);\n\n memspace[index] = bank;\n}\n\n/// Any MemoryBank that has been registered with this MemoryState can be retrieved via this\n/// method if the MemoryBank's associated address space is known.\n/// \\param spc is the address space of the desired MemoryBank\n/// \\return a pointer to the MemoryBank or \\b null if no bank is associated with \\e spc.\nMemoryBank *MemoryState::getMemoryBank(AddrSpace *spc) const\n\n{\n int4 index = spc->getIndex();\n if (index >= memspace.size())\n return (MemoryBank *)0;\n return memspace[index];\n}\n\n/// This is the main interface for writing values to the MemoryState.\n/// If there is no registered MemoryBank for the desired address space, or\n/// if there is some other error, an exception is thrown.\n/// \\param spc is the address space to write to\n/// \\param off is the offset where the value should be written\n/// \\param size is the number of bytes to be written\n/// \\param cval is the value to be written\nvoid MemoryState::setValue(AddrSpace *spc,uintb off,int4 size,uintb cval)\n\n{\n MemoryBank *mspace = getMemoryBank(spc);\n if (mspace == (MemoryBank *)0)\n throw LowlevelError(\"Setting value for unmapped memory space: \"+spc->getName());\n mspace->setValue(off,size,cval);\n}\n\n/// This is the main interface for reading values from the MemoryState.\n/// If there is no registered MemoryBank for the desired address space, or\n/// if there is some other error, an exception is thrown.\n/// \\param spc is the address space being queried\n/// \\param off is the offset of the value being queried\n/// \\param size is the number of bytes to query\n/// \\return the queried value\nuintb MemoryState::getValue(AddrSpace *spc,uintb off,int4 size) const\n\n{\n if (spc->getType() == IPTR_CONSTANT) return off;\n MemoryBank *mspace = getMemoryBank(spc);\n if (mspace == (MemoryBank *)0)\n throw LowlevelError(\"Getting value from unmapped memory space: \"+spc->getName());\n return mspace->getValue(off,size);\n}\n\n/// This is a convenience method for setting registers by name.\n/// Any register name known to the Translate object can be used as a write location.\n/// The associated address space, offset, and size is looked up and automatically\n/// passed to the main setValue routine.\n/// \\param nm is the name of the register\n/// \\param cval is the value to write to the register\nvoid MemoryState::setValue(const string &nm,uintb cval)\n\n{ // Set a \"register\" value\n const VarnodeData &vdata( trans->getRegister(nm) );\n setValue(vdata.space,vdata.offset,vdata.size,cval);\n}\n\n/// This is a convenience method for reading registers by name.\n/// Any register name known to the Translate object can be used as a read location.\n/// The associated address space, offset, and size is looked up and automatically\n/// passed to the main getValue routine.\n/// \\param nm is the name of the register\n/// \\return the value associated with that register\nuintb MemoryState::getValue(const string &nm) const\n\n{ // Get a \"register\" value\n const VarnodeData &vdata( trans->getRegister(nm) );\n return getValue(vdata.space,vdata.offset,vdata.size);\n}\n\n/// This is the main interface for reading a range of bytes from the MemorySate.\n/// The MemoryBank associated with the address space of the query is looked up\n/// and the request is forwarded to the getChunk method on the MemoryBank. If there\n/// is no registered MemoryBank or some other error, an exception is thrown\n/// \\param res is a pointer to the result buffer for storing retrieved bytes\n/// \\param spc is the desired address space\n/// \\param off is the starting offset of the byte range being queried\n/// \\param size is the number of bytes being queried\nvoid MemoryState::getChunk(uint1 *res,AddrSpace *spc,uintb off,int4 size) const\n\n{\n MemoryBank *mspace = getMemoryBank(spc);\n if (mspace == (MemoryBank *)0)\n throw LowlevelError(\"Getting chunk from unmapped memory space: \"+spc->getName());\n mspace->getChunk(off,size,res);\n}\n\n/// This is the main interface for setting values for a range of bytes in the MemoryState.\n/// The MemoryBank associated with the desired address space is looked up and the\n/// write is forwarded to the setChunk method on the MemoryBank. If there is no\n/// registered MemoryBank or some other error, an exception is throw.\n/// \\param val is a pointer to the byte values to be written into the MemoryState\n/// \\param spc is the address space being written\n/// \\param off is the starting offset of the range being written\n/// \\param size is the number of bytes to write\nvoid MemoryState::setChunk(const uint1 *val,AddrSpace *spc,uintb off,int4 size)\n\n{\n MemoryBank *mspace = getMemoryBank(spc);\n if (mspace == (MemoryBank *)0)\n throw LowlevelError(\"Setting chunk of unmapped memory space: \"+spc->getName());\n mspace->setChunk(off,size,val);\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/memstate.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file memstate.hh\n/// \\brief Classes for keeping track of memory state during emulation\n\n#ifndef __MEMSTATE_HH__\n#define __MEMSTATE_HH__\n\n#include \"pcoderaw.hh\"\n#include \"loadimage.hh\"\n\nnamespace ghidra {\n\n/// \\brief Memory storage/state for a single AddressSpace\n///\n/// Class for setting and getting memory values within a space\n/// The basic API is to get/set arrays of byte values via offset within the space.\n/// Helper functions getValue and setValue easily retrieve/store integers\n/// of various sizes from memory, using the endianness encoding specified by the space.\n/// Accesses through the public interface, are automatically broken down into\n/// \\b word accesses, through the private insert/find methods, and \\b page\n/// accesses through getPage/setPage. So these are the virtual methods that need\n/// to be overridden in the derived classes.\n\nclass MemoryBank {\n friend class MemoryPageOverlay;\n friend class MemoryHashOverlay;\n int4 wordsize;\t\t///< Number of bytes in an aligned word access\n int4 pagesize;\t\t///< Number of bytes in an aligned page access\n AddrSpace *space;\t\t///< The address space associated with this memory\nprotected:\n virtual void insert(uintb addr,uintb val)=0; ///< Insert a word in memory bank at an aligned location\n virtual uintb find(uintb addr) const=0; ///< Retrieve a word from memory bank at an aligned location\n virtual void getPage(uintb addr,uint1 *res,int4 skip,int4 size) const; ///< Retrieve data from a memory \\e page \n virtual void setPage(uintb addr,const uint1 *val,int4 skip,int4 size); ///< Write data into a memory page\npublic:\n MemoryBank(AddrSpace *spc,int4 ws,int4 ps); ///< Generic constructor for a memory bank\n virtual ~MemoryBank(void) {}\n int4 getWordSize(void) const;\t///< Get the number of bytes in a word for this memory bank\n int4 getPageSize(void) const;\t///< Get the number of bytes in a page for this memory bank\n AddrSpace *getSpace(void) const; ///< Get the address space associated with this memory bank\n \n void setValue(uintb offset,int4 size,uintb val); ///< Set the value of a (small) range of bytes\n uintb getValue(uintb offset,int4 size) const; ///< Retrieve the value encoded in a (small) range of bytes\n void setChunk(uintb offset,int4 size,const uint1 *val); ///< Set values of an arbitrary sequence of bytes\n void getChunk(uintb offset,int4 size,uint1 *res) const; ///< Retrieve an arbitrary sequence of bytes\n static uintb constructValue(const uint1 *ptr,int4 size,bool bigendian); ///< Decode bytes to value\n static void deconstructValue(uint1 *ptr,uintb val,int4 size,bool bigendian); ///< Encode value to bytes\n};\n\n/// A MemoryBank is instantiated with a \\e natural word size. Requests for arbitrary byte ranges\n/// may be broken down into units of this size.\n/// \\return the number of bytes in a \\e word.\ninline int4 MemoryBank::getWordSize(void) const\n\n{\n return wordsize;\n}\n\n/// A MemoryBank is instantiated with a \\e natural page size. Requests for large chunks of data\n/// may be broken down into units of this size.\n/// \\return the number of bytes in a \\e page.\ninline int4 MemoryBank::getPageSize(void) const\n\n{\n return pagesize;\n}\n\n/// A MemoryBank is a contiguous sequence of bytes associated with a particular address space.\n/// \\return the AddressSpace associated with this bank.\ninline AddrSpace *MemoryBank::getSpace(void) const\n\n{\n return space;\n}\n\n/// \\brief A kind of MemoryBank which retrieves its data from an underlying LoadImage\n///\n/// Any bytes requested on the bank which lie in the LoadImage are retrieved from\n/// the LoadImage. Other addresses in the space are filled in with zero.\n/// This bank cannot be written to.\nclass MemoryImage : public MemoryBank {\n LoadImage *loader;\t\t///< The underlying LoadImage\nprotected:\n virtual void insert(uintb addr,uintb val) {\n throw LowlevelError(\"Writing to read-only MemoryBank\"); } ///< Exception is thrown for write attempts\n virtual uintb find(uintb addr) const;\t///< Overridden find method\n virtual void getPage(uintb addr,uint1 *res,int4 skip,int4 size) const; ///< Overridded getPage method\npublic:\n MemoryImage(AddrSpace *spc,int4 ws,int4 ps,LoadImage *ld); ///< Constructor for a loadimage memorybank\n};\n\n/// \\brief Memory bank that overlays some other memory bank, using a \"copy on write\" behavior.\n///\n/// Pages are copied from the underlying object only when there is\n/// a write. The underlying access routines are overridden to make optimal use\n/// of this page implementation. The underlying memory bank can be a \\b null pointer\n/// in which case, this memory bank behaves as if it were initially filled with zeros.\nclass MemoryPageOverlay : public MemoryBank {\n MemoryBank *underlie;\t\t///< Underlying memory object\n map page;\t///< Overlayed pages\nprotected:\n virtual void insert(uintb addr,uintb val); ///< Overridden aligned word insert\n virtual uintb find(uintb addr) const;\t///< Overridden aligned word find\n virtual void getPage(uintb addr,uint1 *res,int4 skip,int4 size) const; ///< Overridden getPage\n virtual void setPage(uintb addr,const uint1 *val,int4 skip,int4 size); ///< Overridden setPage\npublic:\n MemoryPageOverlay(AddrSpace *spc,int4 ws,int4 ps,MemoryBank *ul); ///< Constructor for page overlay\n virtual ~MemoryPageOverlay(void);\n};\n\n/// \\brief A memory bank that implements reads and writes using a hash table.\n///\n/// The initial state of the\n/// bank is taken from an \\e underlying memory bank or is all zero, if this bank is initialized with\n/// a \\b null pointer. This implementation will not be very efficient for accessing entire pages.\nclass MemoryHashOverlay : public MemoryBank {\n MemoryBank *underlie;\t\t///< Underlying memory bank\n int4 alignshift;\t\t///< How many LSBs are thrown away from address when doing hash table lookup\n uintb collideskip;\t\t///< How many slots to skip after a hashtable collision\n vector address;\t///< The hashtable addresses\n vector value;\t\t///< The hashtable values\nprotected:\n virtual void insert(uintb addr,uintb val); ///< Overridden aligned word insert\n virtual uintb find(uintb addr) const;\t///< Overridden aligned word find\npublic:\n MemoryHashOverlay(AddrSpace *spc,int4 ws,int4 ps,int4 hashsize,MemoryBank *ul); ///< Constructor for hash overlay\n};\n\nclass Translate;\t\t// Forward declaration\n\n/// \\brief All storage/state for a pcode machine\n///\n/// Every piece of information in a pcode machine is representable as a triple\n/// (AddrSpace,offset,size). This class allows getting and setting\n/// of all state information of this form.\nclass MemoryState {\nprotected:\n Translate *trans;\t\t///< Architecture information about memory spaces\n vector memspace; ///< Memory banks associated with each address space\npublic:\n MemoryState(Translate *t);\t///< A constructor for MemoryState\n ~MemoryState(void) {}\n Translate *getTranslate(void) const; ///< Get the Translate object\n void setMemoryBank(MemoryBank *bank);\t///< Map a memory bank into the state\n MemoryBank *getMemoryBank(AddrSpace *spc) const; ///< Get a memory bank associated with a particular space\n void setValue(AddrSpace *spc,uintb off,int4 size,uintb cval); ///< Set a value on the memory state\n uintb getValue(AddrSpace *spc,uintb off,int4 size) const; ///< Retrieve a memory value from the memory state\n void setValue(const string &nm,uintb cval); ///< Set a value on a named register in the memory state\n uintb getValue(const string &nm) const; ///< Retrieve a value from a named register in the memory state\n void setValue(const VarnodeData *vn,uintb cval); ///< Set value on a given \\b varnode\n uintb getValue(const VarnodeData *vn) const; ///< Get a value from a \\b varnode\n void getChunk(uint1 *res,AddrSpace *spc,uintb off,int4 size) const; ///< Get a chunk of data from memory state\n void setChunk(const uint1 *val,AddrSpace *spc,uintb off,int4 size); ///< Set a chunk of data from memory state\n};\n\n/// The MemoryState needs a Translate object in order to be able to convert register names\n/// into varnodes\n/// \\param t is the translator\ninline MemoryState::MemoryState(Translate *t)\n\n{\n trans = t;\n}\n\n/// Retrieve the actual pcode translator being used by this machine state\n/// \\return a pointer to the Translate object\ninline Translate *MemoryState::getTranslate(void) const\n\n{\n return trans;\n}\n\n/// A convenience method for setting a value directly on a varnode rather than\n/// breaking out the components\n/// \\param vn is a pointer to the varnode to be written\n/// \\param cval is the value to write into the varnode\ninline void MemoryState::setValue(const VarnodeData *vn,uintb cval)\n\n{\n setValue(vn->space,vn->offset,vn->size,cval);\n}\n\n/// A convenience method for reading a value directly from a varnode rather\n/// than querying for the offset and space\n/// \\param vn is a pointer to the varnode to be read\n/// \\return the value read from the varnode\ninline uintb MemoryState::getValue(const VarnodeData *vn) const\n\n{\n return getValue(vn->space,vn->offset,vn->size);\n}\n\n} // End namespace ghidra\n #endif\n" }, { "path": "pypcode/sleigh/opbehavior.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"opbehavior.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\n/// This routine generates a vector of OpBehavior objects indexed by opcode\n/// \\param inst is the vector of behaviors to be filled\n/// \\param trans is the translator object needed by the floating point behaviors\nvoid OpBehavior::registerInstructions(vector &inst,const Translate *trans)\n\n{\n inst.insert(inst.end(),CPUI_MAX,(OpBehavior *)0);\n\n inst[CPUI_COPY] = new OpBehaviorCopy();\n inst[CPUI_LOAD] = new OpBehavior(CPUI_LOAD,false,true);\n inst[CPUI_STORE] = new OpBehavior(CPUI_STORE,false,true);\n inst[CPUI_BRANCH] = new OpBehavior(CPUI_BRANCH,false,true);\n inst[CPUI_CBRANCH] = new OpBehavior(CPUI_CBRANCH,false,true);\n inst[CPUI_BRANCHIND] = new OpBehavior(CPUI_BRANCHIND,false,true);\n inst[CPUI_CALL] = new OpBehavior(CPUI_CALL,false,true);\n inst[CPUI_CALLIND] = new OpBehavior(CPUI_CALLIND,false,true);\n inst[CPUI_CALLOTHER] = new OpBehavior(CPUI_CALLOTHER,false,true);\n inst[CPUI_RETURN] = new OpBehavior(CPUI_RETURN,false,true);\n\n inst[CPUI_MULTIEQUAL] = new OpBehavior(CPUI_MULTIEQUAL,false,true);\n inst[CPUI_INDIRECT] = new OpBehavior(CPUI_INDIRECT,false,true);\n\n inst[CPUI_PIECE] = new OpBehaviorPiece();\n inst[CPUI_SUBPIECE] = new OpBehaviorSubpiece();\n inst[CPUI_INT_EQUAL] = new OpBehaviorEqual();\n inst[CPUI_INT_NOTEQUAL] = new OpBehaviorNotEqual();\n inst[CPUI_INT_SLESS] = new OpBehaviorIntSless();\n inst[CPUI_INT_SLESSEQUAL] = new OpBehaviorIntSlessEqual();\n inst[CPUI_INT_LESS] = new OpBehaviorIntLess();\n inst[CPUI_INT_LESSEQUAL] = new OpBehaviorIntLessEqual();\n inst[CPUI_INT_ZEXT] = new OpBehaviorIntZext();\n inst[CPUI_INT_SEXT] = new OpBehaviorIntSext();\n inst[CPUI_INT_ADD] = new OpBehaviorIntAdd();\n inst[CPUI_INT_SUB] = new OpBehaviorIntSub();\n inst[CPUI_INT_CARRY] = new OpBehaviorIntCarry();\n inst[CPUI_INT_SCARRY] = new OpBehaviorIntScarry();\n inst[CPUI_INT_SBORROW] = new OpBehaviorIntSborrow();\n inst[CPUI_INT_2COMP] = new OpBehaviorInt2Comp();\n inst[CPUI_INT_NEGATE] = new OpBehaviorIntNegate();\n inst[CPUI_INT_XOR] = new OpBehaviorIntXor();\n inst[CPUI_INT_AND] = new OpBehaviorIntAnd();\n inst[CPUI_INT_OR] = new OpBehaviorIntOr();\n inst[CPUI_INT_LEFT] = new OpBehaviorIntLeft();\n inst[CPUI_INT_RIGHT] = new OpBehaviorIntRight();\n inst[CPUI_INT_SRIGHT] = new OpBehaviorIntSright();\n inst[CPUI_INT_MULT] = new OpBehaviorIntMult();\n inst[CPUI_INT_DIV] = new OpBehaviorIntDiv();\n inst[CPUI_INT_SDIV] = new OpBehaviorIntSdiv();\n inst[CPUI_INT_REM] = new OpBehaviorIntRem();\n inst[CPUI_INT_SREM] = new OpBehaviorIntSrem();\n\n inst[CPUI_BOOL_NEGATE] = new OpBehaviorBoolNegate();\n inst[CPUI_BOOL_XOR] = new OpBehaviorBoolXor();\n inst[CPUI_BOOL_AND] = new OpBehaviorBoolAnd();\n inst[CPUI_BOOL_OR] = new OpBehaviorBoolOr();\n\n inst[CPUI_CAST] = new OpBehavior(CPUI_CAST,false,true);\n inst[CPUI_PTRADD] = new OpBehavior(CPUI_PTRADD,false);\n inst[CPUI_PTRSUB] = new OpBehavior(CPUI_PTRSUB,false);\n\n inst[CPUI_FLOAT_EQUAL] = new OpBehaviorFloatEqual(trans);\n inst[CPUI_FLOAT_NOTEQUAL] = new OpBehaviorFloatNotEqual(trans);\n inst[CPUI_FLOAT_LESS] = new OpBehaviorFloatLess(trans);\n inst[CPUI_FLOAT_LESSEQUAL] = new OpBehaviorFloatLessEqual(trans);\n inst[CPUI_FLOAT_NAN] = new OpBehaviorFloatNan(trans);\n\n inst[CPUI_FLOAT_ADD] = new OpBehaviorFloatAdd(trans);\n inst[CPUI_FLOAT_DIV] = new OpBehaviorFloatDiv(trans);\n inst[CPUI_FLOAT_MULT] = new OpBehaviorFloatMult(trans);\n inst[CPUI_FLOAT_SUB] = new OpBehaviorFloatSub(trans);\n inst[CPUI_FLOAT_NEG] = new OpBehaviorFloatNeg(trans);\n inst[CPUI_FLOAT_ABS] = new OpBehaviorFloatAbs(trans);\n inst[CPUI_FLOAT_SQRT] = new OpBehaviorFloatSqrt(trans);\n\n inst[CPUI_FLOAT_INT2FLOAT] = new OpBehaviorFloatInt2Float(trans);\n inst[CPUI_FLOAT_FLOAT2FLOAT] = new OpBehaviorFloatFloat2Float(trans);\n inst[CPUI_FLOAT_TRUNC] = new OpBehaviorFloatTrunc(trans);\n inst[CPUI_FLOAT_CEIL] = new OpBehaviorFloatCeil(trans);\n inst[CPUI_FLOAT_FLOOR] = new OpBehaviorFloatFloor(trans);\n inst[CPUI_FLOAT_ROUND] = new OpBehaviorFloatRound(trans);\n inst[CPUI_SEGMENTOP] = new OpBehavior(CPUI_SEGMENTOP,false,true);\n inst[CPUI_CPOOLREF] = new OpBehavior(CPUI_CPOOLREF,false,true);\n inst[CPUI_NEW] = new OpBehavior(CPUI_NEW,false,true);\n inst[CPUI_INSERT] = new OpBehavior(CPUI_INSERT,false);\n inst[CPUI_EXTRACT] = new OpBehavior(CPUI_EXTRACT,false);\n inst[CPUI_POPCOUNT] = new OpBehaviorPopcount();\n inst[CPUI_LZCOUNT] = new OpBehaviorLzcount();\n}\n\n/// \\param sizeout is the size of the output in bytes\n/// \\param sizein is the size of the input in bytes\n/// \\param in1 is the input value\n/// \\return the output value\nuintb OpBehavior::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n string name(get_opname(opcode));\n throw LowlevelError(\"Unary emulation unimplemented for \"+name);\n}\n\n/// \\param sizeout is the size of the output in bytes\n/// \\param sizein is the size of the inputs in bytes\n/// \\param in1 is the first input value\n/// \\param in2 is the second input value\n/// \\return the output value\nuintb OpBehavior::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n string name(get_opname(opcode));\n throw LowlevelError(\"Binary emulation unimplemented for \"+name);\n}\n\n/// \\param sizeout is the size of the output in bytes\n/// \\param sizein is the size of the inputs in bytes\n/// \\param in1 is the first input value\n/// \\param in2 is the second input value\n/// \\param in3 is the third input value\n/// \\return the output value\nuintb OpBehavior::evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const\n\n{\n string name(get_opname(opcode));\n throw LowlevelError(\"Ternary emulation unimplemented for \"+name);\n}\n\n/// If the output value is known, recover the input value.\n/// \\param sizeout is the size of the output in bytes\n/// \\param out is the output value\n/// \\param sizein is the size of the input in bytes\n/// \\return the input value\nuintb OpBehavior::recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const\n\n{\n throw LowlevelError(\"Cannot recover input parameter without loss of information\");\n}\n\n/// If the output value and one of the input values is known, recover the value\n/// of the other input.\n/// \\param slot is the input slot to recover\n/// \\param sizeout is the size of the output in bytes\n/// \\param out is the output value\n/// \\param sizein is the size of the inputs in bytes\n/// \\param in is the known input value\n/// \\return the input value corresponding to the \\b slot\nuintb OpBehavior::recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const\n\n{\n throw LowlevelError(\"Cannot recover input parameter without loss of information\");\n}\n\nuintb OpBehaviorCopy::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n return in1;\n}\n\nuintb OpBehaviorCopy::recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const\n\n{\n return out;\n}\n\nuintb OpBehaviorEqual::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 == in2) ? 1 : 0;\n return res;\n}\n\nuintb OpBehaviorNotEqual::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 != in2) ? 1 : 0;\n return res;\n}\n\nuintb OpBehaviorIntSless::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res,mask,bit1,bit2;\n\n if (sizein<=0)\n res = 0;\n else {\n mask = 0x80;\n mask <<= 8*(sizein-1);\n bit1 = in1 & mask;\t\t// Get the sign bits\n bit2 = in2 & mask;\n if (bit1 != bit2)\n res = (bit1 != 0) ? 1 : 0;\n else\n res = (in1 < in2) ? 1 : 0;\n }\n return res;\n}\n\nuintb OpBehaviorIntSlessEqual::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res,mask,bit1,bit2;\n\n if (sizein<=0)\n res = 0;\n else {\n mask = 0x80;\n mask <<= 8*(sizein-1);\n bit1 = in1 & mask;\t\t// Get the sign bits\n bit2 = in2 & mask;\n if (bit1 != bit2)\n res = (bit1 != 0) ? 1 : 0;\n else\n res = (in1 <= in2) ? 1 : 0;\n }\n return res;\n}\n\nuintb OpBehaviorIntLess::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 < in2) ? 1 : 0;\n return res;\n}\n\nuintb OpBehaviorIntLessEqual::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 <= in2) ? 1 : 0;\n return res;\n}\n\nuintb OpBehaviorIntZext::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n return in1;\n}\n\nuintb OpBehaviorIntZext::recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const\n\n{\n uintb mask = calc_mask(sizein);\n if ((mask&out)!=out)\n throw EvaluationError(\"Output is not in range of zext operation\");\n return out;\n}\n\nuintb OpBehaviorIntSext::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n uintb res = sign_extend(in1,sizein,sizeout);\n return res;\n}\n\nuintb OpBehaviorIntSext::recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const\n\n{\n uintb masklong = calc_mask(sizeout);\n uintb maskshort = calc_mask(sizein);\n\n if ((out & (maskshort ^ (maskshort>>1))) == 0) { // Positive input\n if ((out & maskshort) != out)\n throw EvaluationError(\"Output is not in range of sext operation\");\n }\n else {\t\t\t// Negative input\n if ((out & (masklong^maskshort)) != (masklong^maskshort))\n throw EvaluationError(\"Output is not in range of sext operation\");\n }\n return (out&maskshort);\n}\n\nuintb OpBehaviorIntAdd::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 + in2) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorIntAdd::recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const\n\n{\n uintb res = (out-in) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorIntSub::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 - in2) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorIntSub::recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const\n\n{\n uintb res;\n if (slot==0)\n res = in + out;\n else\n res = in - out;\n res &= calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorIntCarry::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 > ((in1 + in2)&calc_mask(sizein))) ? 1 : 0;\n return res;\n}\n\nuintb OpBehaviorIntScarry::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = in1 + in2;\n\n uint4 a = (in1>>(sizein*8-1))&1; // Grab sign bit\n uint4 b = (in2>>(sizein*8-1))&1; // Grab sign bit\n uint4 r = (res>>(sizein*8-1))&1; // Grab sign bit\n \n r ^= a;\n a ^= b;\n a ^= 1;\n r &= a;\n return (uintb)r;\n}\n\nuintb OpBehaviorIntSborrow::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = in1 - in2;\n\n uint4 a = (in1>>(sizein*8-1))&1; // Grab sign bit\n uint4 b = (in2>>(sizein*8-1))&1; // Grab sign bit\n uint4 r = (res>>(sizein*8-1))&1; // Grab sign bit\n\n a ^= r;\n r ^= b;\n r ^= 1;\n a &= r;\n return (uintb)a;\n}\n\nuintb OpBehaviorInt2Comp::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n uintb res = uintb_negate(in1-1,sizein);\n return res;\n}\n\nuintb OpBehaviorInt2Comp::recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const\n\n{\n uintb res = uintb_negate(out-1,sizein);\n return res;\n}\n\nuintb OpBehaviorIntNegate::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n uintb res = uintb_negate(in1,sizein);\n return res;\n}\n\nuintb OpBehaviorIntNegate::recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const\n\n{\n uintb res = uintb_negate(out,sizein);\n return res;\n}\n\nuintb OpBehaviorIntXor::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = in1 ^ in2;\n return res;\n}\n\nuintb OpBehaviorIntAnd::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = in1 & in2;\n return res;\n}\n\nuintb OpBehaviorIntOr::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = in1 | in2;\n return res;\n}\n\nuintb OpBehaviorIntLeft::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n if (in2 >= sizeout*8){\n \treturn 0;\n }\n\tuintb res = (in1 << in2) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorIntLeft::recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const\n\n{\n if ((slot!=0) || (in >= sizeout*8))\n return OpBehavior::recoverInputBinary(slot,sizeout,out,sizein,in);\n int4 sa = in;\n if (((out<<(8*sizeout-sa))&calc_mask(sizeout))!=0)\n throw EvaluationError(\"Output is not in range of left shift operation\");\n return out >> sa;\n}\n\nuintb OpBehaviorIntRight::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n if (in2 >= sizeout*8){\n\t return 0;\n }\n uintb res = (in1&calc_mask(sizeout)) >> in2;\n return res;\n}\n\nuintb OpBehaviorIntRight::recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const\n\n{\n if ((slot!=0) || (in >= sizeout*8))\n return OpBehavior::recoverInputBinary(slot,sizeout,out,sizein,in);\n \n int4 sa = in;\n if ((out>>(8*sizein-sa))!=0)\n throw EvaluationError(\"Output is not in range of right shift operation\");\n return out << sa;\n}\n\nuintb OpBehaviorIntSright::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n if (in2 >= 8*sizeout){\n\t return signbit_negative(in1,sizein) ? calc_mask(sizeout) : 0;\n }\n\n uintb res;\n if (signbit_negative(in1,sizein)) {\n res = in1 >> in2;\n uintb mask = calc_mask(sizein);\n mask = (mask >> in2) ^ mask;\n res |= mask;\n }\n else {\n res = in1 >> in2;\n }\n return res;\n}\n\nuintb OpBehaviorIntSright::recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const\n\n{\n if ((slot!=0) || (in >= sizeout*8))\n return OpBehavior::recoverInputBinary(slot,sizeout,out,sizein,in);\n \n int4 sa = in;\n uintb testval = out>>(sizein*8-sa-1);\n int4 count=0;\n for(int4 i=0;i<=sa;++i) {\n if ((testval&1)!=0) count += 1;\n testval >>= 1;\n }\n if (count != sa+1)\n throw EvaluationError(\"Output is not in range of right shift operation\");\n return out<getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opEqual(in1,in2);\n}\n\nuintb OpBehaviorFloatNotEqual::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opNotEqual(in1,in2);\n}\n\nuintb OpBehaviorFloatLess::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opLess(in1,in2);\n}\n\nuintb OpBehaviorFloatLessEqual::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opLessEqual(in1,in2);\n}\n\nuintb OpBehaviorFloatNan::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opNan(in1);\n}\n\nuintb OpBehaviorFloatAdd::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opAdd(in1,in2);\n}\n\nuintb OpBehaviorFloatDiv::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opDiv(in1,in2);\n}\n\nuintb OpBehaviorFloatMult::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opMult(in1,in2);\n}\n\nuintb OpBehaviorFloatSub::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateBinary(sizeout,sizein,in1,in2);\n\n return format->opSub(in1,in2);\n}\n\nuintb OpBehaviorFloatNeg::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opNeg(in1);\n}\n\nuintb OpBehaviorFloatAbs::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opAbs(in1);\n}\n\nuintb OpBehaviorFloatSqrt::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opSqrt(in1);\n}\n\nuintb OpBehaviorFloatInt2Float::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizeout);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opInt2Float(in1,sizein);\n}\n\nuintb OpBehaviorFloatFloat2Float::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *formatout = translate->getFloatFormat(sizeout);\n if (formatout == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n const FloatFormat *formatin = translate->getFloatFormat(sizein);\n if (formatin == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return formatin->opFloat2Float(in1,*formatout);\n}\n\nuintb OpBehaviorFloatTrunc::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opTrunc(in1,sizeout);\n}\n\nuintb OpBehaviorFloatCeil::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opCeil(in1);\n}\n\nuintb OpBehaviorFloatFloor::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opFloor(in1);\n}\n\nuintb OpBehaviorFloatRound::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n const FloatFormat *format = translate->getFloatFormat(sizein);\n if (format == (const FloatFormat *)0)\n return OpBehavior::evaluateUnary(sizeout,sizein,in1);\n\n return format->opRound(in1);\n}\n\nuintb OpBehaviorPiece::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = ( in1<<((sizeout-sizein)*8)) | in2;\n return res;\n}\n\nuintb OpBehaviorSubpiece::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n if (in2 >= sizeof(uintb))\n return 0;\n uintb res = (in1>>(in2*8)) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorPtradd::evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const\n\n{\n uintb res = (in1 + in2 * in3) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorPtrsub::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const\n\n{\n uintb res = (in1 + in2) & calc_mask(sizeout);\n return res;\n}\n\nuintb OpBehaviorPopcount::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n return (uintb)popcount(in1);\n}\n\nuintb OpBehaviorLzcount::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const\n\n{\n return (uintb)(count_leading_zeros(in1) - 8*(sizeof(uintb) - sizein));\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/opbehavior.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file opbehavior.hh\n/// \\brief Classes for describing the behavior of individual p-code operations\n#ifndef __OPBEHAVIOR_HH__\n#define __OPBEHAVIOR_HH__\n\n#include \"error.hh\"\n#include \"opcodes.hh\"\n\nnamespace ghidra {\n\nclass Translate;\t\t// Forward declaration\n\n/// This exception is thrown when emulation evaluation of an operator fails for some reason.\n/// This can be thrown for either forward or reverse emulation\nstruct EvaluationError : public LowlevelError {\n EvaluationError(const string &s) : LowlevelError(s) {} ///< Initialize the error with an explanatory string\n};\n\n/// \\brief Class encapsulating the action/behavior of specific pcode opcodes\n///\n/// At the lowest level, a pcode op is one of a small set of opcodes that\n/// operate on varnodes (address space, offset, size). Classes derived from\n/// this base class encapsulate this basic behavior for each possible opcode.\n/// These classes describe the most basic behaviors and include:\n/// * uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb int2)\n/// * uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1)\n/// * uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in)\n/// * uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein)\nclass OpBehavior {\n OpCode opcode;\t\t///< the internal enumeration for pcode types\n bool isunary;\t\t\t///< true= use unary interfaces, false = use binary\n bool isspecial;\t\t///< Is op not a normal unary or binary op\npublic:\n OpBehavior(OpCode opc,bool isun); ///< A behavior constructor\n\n OpBehavior(OpCode opc,bool isun,bool isspec);\t///< A special behavior constructor\n\n virtual ~OpBehavior(void) {}\n\n /// \\brief Get the opcode for this pcode operation\n OpCode getOpcode(void) const;\n\n /// \\brief Check if this is a special operator\n bool isSpecial(void) const;\n\n /// \\brief Check if operator is unary\n bool isUnary(void) const;\n\n /// \\brief Emulate the unary op-code on an input value\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n \n /// \\brief Emulate the binary op-code on input values\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n\n /// \\brief Emulate the ternary op-code on input values\n virtual uintb evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const;\n\n /// \\brief Reverse the binary op-code operation, recovering an input value\n virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const;\n \n /// \\brief Reverse the unary op-code operation, recovering the input value\n virtual uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const;\n\n static void registerInstructions(vector &inst,const Translate *trans); ///< Build all pcode behaviors\n};\n\n/// This kind of OpBehavior is associated with a particular opcode and is either unary or binary\n/// \\param opc is the opcode of the behavior\n/// \\param isun is \\b true if the behavior is unary, \\b false if binary\ninline OpBehavior::OpBehavior(OpCode opc,bool isun)\n\n{\n opcode = opc;\n isunary = isun;\n isspecial = false;\n}\n\n/// This kind of OpBehavior can be set to \\b special, if it neither unary or binary.\n/// \\param opc is the opcode of the behavior\n/// \\param isun is \\b true if the behavior is unary\n/// \\param isspec is \\b true if the behavior is neither unary or binary\ninline OpBehavior::OpBehavior(OpCode opc,bool isun,bool isspec)\n\n{\n opcode = opc;\n isunary = isun;\n isspecial = isspec;\n}\n\n/// There is an internal enumeration value for each type of pcode operation.\n/// This routine returns that value.\n/// \\return the opcode value\ninline OpCode OpBehavior::getOpcode(void) const {\n return opcode;\n}\n\n/// If this function returns false, the operation is a normal unary or binary operation\n/// which can be evaluated calling evaluateBinary() or evaluateUnary().\n/// Otherwise, the operation requires special handling to emulate properly\ninline bool OpBehavior::isSpecial(void) const {\n return isspecial;\n}\n\n/// The operated can either be evaluated as unary or binary\n/// \\return \\b true if the operator is unary\ninline bool OpBehavior::isUnary(void) const {\n return isunary;\n}\n\n// A class for each opcode\n\n/// CPUI_COPY behavior\nclass OpBehaviorCopy : public OpBehavior {\npublic:\n OpBehaviorCopy(void) : OpBehavior(CPUI_COPY,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n virtual uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const;\n};\n\n/// CPUI_INT_EQUAL behavior\nclass OpBehaviorEqual : public OpBehavior {\npublic:\n OpBehaviorEqual(void) : OpBehavior(CPUI_INT_EQUAL,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_NOTEQUAL behavior\nclass OpBehaviorNotEqual : public OpBehavior {\npublic:\n OpBehaviorNotEqual(void) : OpBehavior(CPUI_INT_NOTEQUAL,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_SLESS behavior\nclass OpBehaviorIntSless : public OpBehavior {\npublic:\n OpBehaviorIntSless(void) : OpBehavior(CPUI_INT_SLESS,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_SLESSEQUAL behavior\nclass OpBehaviorIntSlessEqual : public OpBehavior {\npublic:\n OpBehaviorIntSlessEqual(void) : OpBehavior(CPUI_INT_SLESSEQUAL,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_LESS behavior\nclass OpBehaviorIntLess : public OpBehavior {\npublic:\n OpBehaviorIntLess(void) : OpBehavior(CPUI_INT_LESS,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_LESSEQUAL behavior\nclass OpBehaviorIntLessEqual : public OpBehavior {\npublic:\n OpBehaviorIntLessEqual(void): OpBehavior(CPUI_INT_LESSEQUAL,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_ZEXT behavior\nclass OpBehaviorIntZext : public OpBehavior {\npublic:\n OpBehaviorIntZext(void): OpBehavior(CPUI_INT_ZEXT,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n virtual uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const;\n};\n\n/// CPUI_INT_SEXT behavior\nclass OpBehaviorIntSext : public OpBehavior {\npublic:\n OpBehaviorIntSext(void): OpBehavior(CPUI_INT_SEXT,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n virtual uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const;\n};\n\n/// CPUI_INT_ADD behavior\nclass OpBehaviorIntAdd : public OpBehavior {\npublic:\n OpBehaviorIntAdd(void): OpBehavior(CPUI_INT_ADD,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const;\n};\n\n/// CPUI_INT_SUB behavior\nclass OpBehaviorIntSub : public OpBehavior {\npublic:\n OpBehaviorIntSub(void): OpBehavior(CPUI_INT_SUB,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const;\n};\n\n/// CPUI_INT_CARRY behavior\nclass OpBehaviorIntCarry : public OpBehavior {\npublic:\n OpBehaviorIntCarry(void): OpBehavior(CPUI_INT_CARRY,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_SCARRY behavior\nclass OpBehaviorIntScarry : public OpBehavior {\npublic:\n OpBehaviorIntScarry(void): OpBehavior(CPUI_INT_SCARRY,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_SBORROW behavior\nclass OpBehaviorIntSborrow : public OpBehavior {\npublic:\n OpBehaviorIntSborrow(void): OpBehavior(CPUI_INT_SBORROW,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_2COMP behavior\nclass OpBehaviorInt2Comp : public OpBehavior {\npublic:\n OpBehaviorInt2Comp(void): OpBehavior(CPUI_INT_2COMP,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n virtual uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const;\n};\n\n/// CPUI_INT_NEGATE behavior\nclass OpBehaviorIntNegate : public OpBehavior {\npublic:\n OpBehaviorIntNegate(void): OpBehavior(CPUI_INT_NEGATE,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n virtual uintb recoverInputUnary(int4 sizeout,uintb out,int4 sizein) const;\n};\n\n/// CPUI_INT_XOR behavior\nclass OpBehaviorIntXor : public OpBehavior {\npublic:\n OpBehaviorIntXor(void): OpBehavior(CPUI_INT_XOR,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_AND behavior\nclass OpBehaviorIntAnd : public OpBehavior {\npublic:\n OpBehaviorIntAnd(void): OpBehavior(CPUI_INT_AND,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_OR behavior\nclass OpBehaviorIntOr : public OpBehavior {\npublic:\n OpBehaviorIntOr(void): OpBehavior(CPUI_INT_OR,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_LEFT behavior\nclass OpBehaviorIntLeft : public OpBehavior {\npublic:\n OpBehaviorIntLeft(void): OpBehavior(CPUI_INT_LEFT,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const;\n};\n\n/// CPUI_INT_RIGHT behavior\nclass OpBehaviorIntRight : public OpBehavior {\npublic:\n OpBehaviorIntRight(void): OpBehavior(CPUI_INT_RIGHT,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const;\n};\n\n/// CPUI_INT_SRIGHT behavior\nclass OpBehaviorIntSright : public OpBehavior {\npublic:\n OpBehaviorIntSright(void): OpBehavior(CPUI_INT_SRIGHT,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const;\n};\n\n/// CPUI_INT_MULT behavior\nclass OpBehaviorIntMult : public OpBehavior {\npublic:\n OpBehaviorIntMult(void): OpBehavior(CPUI_INT_MULT,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_DIV behavior\nclass OpBehaviorIntDiv : public OpBehavior {\npublic:\n OpBehaviorIntDiv(void): OpBehavior(CPUI_INT_DIV,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_SDIV behavior\nclass OpBehaviorIntSdiv : public OpBehavior {\npublic:\n OpBehaviorIntSdiv(void): OpBehavior(CPUI_INT_SDIV,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_REM behavior\nclass OpBehaviorIntRem : public OpBehavior {\npublic:\n OpBehaviorIntRem(void): OpBehavior(CPUI_INT_REM,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_INT_SREM behavior\nclass OpBehaviorIntSrem : public OpBehavior {\npublic:\n OpBehaviorIntSrem(void): OpBehavior(CPUI_INT_SREM,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_BOOL_NEGATE behavior\nclass OpBehaviorBoolNegate : public OpBehavior {\npublic:\n OpBehaviorBoolNegate(void): OpBehavior(CPUI_BOOL_NEGATE,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_BOOL_XOR behavior\nclass OpBehaviorBoolXor : public OpBehavior {\npublic:\n OpBehaviorBoolXor(void): OpBehavior(CPUI_BOOL_XOR,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_BOOL_AND behavior\nclass OpBehaviorBoolAnd : public OpBehavior {\npublic:\n OpBehaviorBoolAnd(void): OpBehavior(CPUI_BOOL_AND,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_BOOL_OR behavior\nclass OpBehaviorBoolOr : public OpBehavior {\npublic:\n OpBehaviorBoolOr(void): OpBehavior(CPUI_BOOL_OR,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_EQUAL behavior\nclass OpBehaviorFloatEqual : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatEqual(const Translate *trans): OpBehavior(CPUI_FLOAT_EQUAL,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_NOTEQUAL behavior\nclass OpBehaviorFloatNotEqual : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatNotEqual(const Translate *trans): OpBehavior(CPUI_FLOAT_NOTEQUAL,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_LESS behavior\nclass OpBehaviorFloatLess : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatLess(const Translate *trans) : OpBehavior(CPUI_FLOAT_LESS,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_LESSEQUAL behavior\nclass OpBehaviorFloatLessEqual : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatLessEqual(const Translate *trans) : OpBehavior(CPUI_FLOAT_LESSEQUAL,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_NAN behavior\nclass OpBehaviorFloatNan : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatNan(const Translate *trans) : OpBehavior(CPUI_FLOAT_NAN,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_ADD behavior\nclass OpBehaviorFloatAdd : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatAdd(const Translate *trans) : OpBehavior(CPUI_FLOAT_ADD,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_DIV behavior\nclass OpBehaviorFloatDiv : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatDiv(const Translate *trans) : OpBehavior(CPUI_FLOAT_DIV,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_MULT behavior\nclass OpBehaviorFloatMult : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatMult(const Translate *trans) : OpBehavior(CPUI_FLOAT_MULT,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_SUB behavior\nclass OpBehaviorFloatSub : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatSub(const Translate *trans) : OpBehavior(CPUI_FLOAT_SUB,false) { translate = trans; }\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_FLOAT_NEG behavior\nclass OpBehaviorFloatNeg : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatNeg(const Translate *trans) : OpBehavior(CPUI_FLOAT_NEG,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_ABS behavior\nclass OpBehaviorFloatAbs : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatAbs(const Translate *trans) : OpBehavior(CPUI_FLOAT_ABS,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_SQRT behavior\nclass OpBehaviorFloatSqrt : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatSqrt(const Translate *trans) : OpBehavior(CPUI_FLOAT_SQRT,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_INT2FLOAT behavior\nclass OpBehaviorFloatInt2Float : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatInt2Float(const Translate *trans) : OpBehavior(CPUI_FLOAT_INT2FLOAT,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_FLOAT2FLOAT behavior\nclass OpBehaviorFloatFloat2Float : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatFloat2Float(const Translate *trans) : OpBehavior(CPUI_FLOAT_FLOAT2FLOAT,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_TRUNC behavior\nclass OpBehaviorFloatTrunc : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatTrunc(const Translate *trans) : OpBehavior(CPUI_FLOAT_TRUNC,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_CEIL behavior\nclass OpBehaviorFloatCeil : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatCeil(const Translate *trans) : OpBehavior(CPUI_FLOAT_CEIL,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_FLOOR behavior\nclass OpBehaviorFloatFloor : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatFloor(const Translate *trans) : OpBehavior(CPUI_FLOAT_FLOOR,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_FLOAT_ROUND behavior\nclass OpBehaviorFloatRound : public OpBehavior {\n const Translate *translate;\t///< Translate object for recovering float format\npublic:\n OpBehaviorFloatRound(const Translate *trans) : OpBehavior(CPUI_FLOAT_ROUND,true) { translate = trans; }\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_PIECE behavior\nclass OpBehaviorPiece : public OpBehavior {\npublic:\n OpBehaviorPiece(void) : OpBehavior(CPUI_PIECE,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_SUBPIECE behavior\nclass OpBehaviorSubpiece : public OpBehavior {\npublic:\n OpBehaviorSubpiece(void) : OpBehavior(CPUI_SUBPIECE,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_PTRADD behavior\nclass OpBehaviorPtradd : public OpBehavior {\npublic:\n OpBehaviorPtradd(void) : OpBehavior(CPUI_PTRADD,false) {}\t///< Constructor\n virtual uintb evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const;\n};\n\n/// CPUI_PTRSUB behavior\nclass OpBehaviorPtrsub : public OpBehavior {\npublic:\n OpBehaviorPtrsub(void) : OpBehavior(CPUI_PTRSUB,false) {}\t///< Constructor\n virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const;\n};\n\n/// CPUI_POPCOUNT behavior\nclass OpBehaviorPopcount : public OpBehavior {\npublic:\n OpBehaviorPopcount(void) : OpBehavior(CPUI_POPCOUNT,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n/// CPUI_LZCOUNT behavior\nclass OpBehaviorLzcount : public OpBehavior {\npublic:\n OpBehaviorLzcount(void) : OpBehavior(CPUI_LZCOUNT,true) {}\t///< Constructor\n virtual uintb evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const;\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/opcodes.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"opcodes.hh\"\n#include \"types.h\"\n\nnamespace ghidra {\n\n/// \\brief Names of operations associated with their opcode number\n///\n/// Some of the names have been replaced with special placeholder\n/// ops for the sleigh compiler and interpreter these are as follows:\n/// - MULTIEQUAL = BUILD\n/// - INDIRECT = DELAY_SLOT\n/// - PTRADD = LABEL\n/// - PTRSUB = CROSSBUILD\nstatic const char *opcode_name[] = {\n \"BLANK\", \"COPY\", \"LOAD\", \"STORE\",\n \"BRANCH\", \"CBRANCH\", \"BRANCHIND\", \"CALL\",\n \"CALLIND\", \"CALLOTHER\", \"RETURN\", \"INT_EQUAL\",\n \"INT_NOTEQUAL\", \"INT_SLESS\", \"INT_SLESSEQUAL\", \"INT_LESS\",\n \"INT_LESSEQUAL\", \"INT_ZEXT\", \"INT_SEXT\", \"INT_ADD\",\n \"INT_SUB\", \"INT_CARRY\", \"INT_SCARRY\", \"INT_SBORROW\",\n \"INT_2COMP\", \"INT_NEGATE\", \"INT_XOR\", \"INT_AND\",\n \"INT_OR\", \"INT_LEFT\", \"INT_RIGHT\", \"INT_SRIGHT\",\n \"INT_MULT\", \"INT_DIV\", \"INT_SDIV\", \"INT_REM\",\n \"INT_SREM\", \"BOOL_NEGATE\", \"BOOL_XOR\", \"BOOL_AND\",\n \"BOOL_OR\", \"FLOAT_EQUAL\", \"FLOAT_NOTEQUAL\", \"FLOAT_LESS\",\n \"FLOAT_LESSEQUAL\", \"UNUSED1\", \"FLOAT_NAN\", \"FLOAT_ADD\",\n \"FLOAT_DIV\", \"FLOAT_MULT\", \"FLOAT_SUB\", \"FLOAT_NEG\",\n \"FLOAT_ABS\", \"FLOAT_SQRT\", \"INT2FLOAT\", \"FLOAT2FLOAT\",\n \"TRUNC\", \"CEIL\", \"FLOOR\", \"ROUND\",\n \"BUILD\", \"DELAY_SLOT\", \"PIECE\", \"SUBPIECE\", \"CAST\",\n \"LABEL\", \"CROSSBUILD\", \"SEGMENTOP\", \"CPOOLREF\", \"NEW\",\n \"INSERT\", \"EXTRACT\", \"POPCOUNT\", \"LZCOUNT\"\n};\n\nstatic const int4 opcode_indices[] = {\n 0, 39, 37, 40, 38, 4, 6, 60, 7, 8, 9, 64, 5, 57, 1, 68, 66,\n 61, 71, 55, 52, 47, 48, 41, 43, 44, 49, 46, 51, 42, 53, 50, 58, 70,\n 54, 24, 19, 27, 21, 33, 11, 29, 15, 16, 32, 25, 12, 28, 35, 30,\n 23, 22, 34, 18, 13, 14, 36, 31, 20, 26, 17, 65, 2, 73, 69, 62, 72, 10, 59,\n 67, 3, 63, 56, 45\n};\n\n/// \\param opc is an OpCode value\n/// \\return the name of the operation as a string\nconst char *get_opname(OpCode opc)\n\n{\n return opcode_name[opc];\n}\n\n/// \\param nm is the name of an operation\n/// \\return the corresponding OpCode value\nOpCode get_opcode(const string &nm)\n\n{\n int4 min = 1;\t\t\t// Don't include BLANK\n int4 max = CPUI_MAX-1;\n int4 cur,ind;\n\n while(min <= max) {\t\t// Binary search\n cur = (min + max)/2;\n ind = opcode_indices[cur];\t// Get opcode in cur's sort slot\n if (opcode_name[ind] < nm)\n min = cur + 1;\t\t// Everything equal or below cur is less\n else if (opcode_name[ind] > nm)\n max = cur - 1;\t\t// Everything equal or above cur is greater\n else\n return (OpCode)ind;\t// Found the match\n }\n return (OpCode)0;\t// Name isn't an op\n}\n\n/// Every comparison operation has a complementary form that produces\n/// the opposite output on the same inputs. Set \\b reorder to true if\n/// the complimentary operation involves reordering the input parameters.\n/// \\param opc is the OpCode to complement\n/// \\param reorder is set to \\b true if the inputs need to be reordered\n/// \\return the complementary OpCode or CPUI_MAX if not given a comparison operation\nOpCode get_booleanflip(OpCode opc,bool &reorder)\n\n{\n switch(opc) {\n case CPUI_INT_EQUAL:\n reorder = false;\n return CPUI_INT_NOTEQUAL;\n case CPUI_INT_NOTEQUAL:\n reorder = false;\n return CPUI_INT_EQUAL;\n case CPUI_INT_SLESS:\n reorder = true;\n return CPUI_INT_SLESSEQUAL;\n case CPUI_INT_SLESSEQUAL:\n reorder = true;\n return CPUI_INT_SLESS;\n case CPUI_INT_LESS:\n reorder = true;\n return CPUI_INT_LESSEQUAL;\n case CPUI_INT_LESSEQUAL:\n reorder = true;\n return CPUI_INT_LESS;\n case CPUI_BOOL_NEGATE:\n reorder = false;\n return CPUI_COPY;\n case CPUI_FLOAT_EQUAL:\n reorder = false;\n return CPUI_FLOAT_NOTEQUAL;\n case CPUI_FLOAT_NOTEQUAL:\n reorder = false;\n return CPUI_FLOAT_EQUAL;\n case CPUI_FLOAT_LESS:\n reorder = true;\n return CPUI_FLOAT_LESSEQUAL;\n case CPUI_FLOAT_LESSEQUAL:\n reorder = true;\n return CPUI_FLOAT_LESS;\n default:\n break;\n }\n return CPUI_MAX;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/opcodes.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file opcodes.hh\n/// \\brief All the individual p-code operations\n\n#ifndef __OPCODES_HH__\n#define __OPCODES_HH__\n\n#include \n\nnamespace ghidra {\n\nusing std::string;\n\n/// \\brief The op-code defining a specific p-code operation (PcodeOp)\n///\n/// These break up into categories:\n/// - Branching operations\n/// - Load and Store\n/// - Comparison operations\n/// - Arithmetic operations\n/// - Logical operations\n/// - Extension and truncation operations\nenum OpCode {\n CPUI_IMARK = 0,\n\n\n CPUI_COPY = 1,\t\t///< Copy one operand to another\n CPUI_LOAD = 2,\t\t///< Load from a pointer into a specified address space\n CPUI_STORE = 3,\t\t///< Store at a pointer into a specified address space\n\n CPUI_BRANCH = 4,\t\t///< Always branch\n CPUI_CBRANCH = 5,\t\t///< Conditional branch\n CPUI_BRANCHIND = 6,\t\t///< Indirect branch (jumptable)\n\n CPUI_CALL = 7,\t\t///< Call to an absolute address\n CPUI_CALLIND = 8,\t\t///< Call through an indirect address\n CPUI_CALLOTHER = 9,\t\t///< User-defined operation\n CPUI_RETURN = 10,\t\t///< Return from subroutine\n\n\t\t\t\t// Integer/bit operations\n\n CPUI_INT_EQUAL = 11,\t\t///< Integer comparison, equality (==)\n CPUI_INT_NOTEQUAL = 12,\t///< Integer comparison, in-equality (!=)\n CPUI_INT_SLESS = 13,\t\t///< Integer comparison, signed less-than (<)\n CPUI_INT_SLESSEQUAL = 14,\t///< Integer comparison, signed less-than-or-equal (<=)\n CPUI_INT_LESS = 15,\t\t///< Integer comparison, unsigned less-than (<)\n\t\t\t\t// This also indicates a borrow on unsigned substraction\n CPUI_INT_LESSEQUAL = 16,\t///< Integer comparison, unsigned less-than-or-equal (<=)\n CPUI_INT_ZEXT = 17,\t\t///< Zero extension\n CPUI_INT_SEXT = 18,\t\t///< Sign extension\n CPUI_INT_ADD = 19,\t\t///< Addition, signed or unsigned (+)\n CPUI_INT_SUB = 20,\t\t///< Subtraction, signed or unsigned (-)\n CPUI_INT_CARRY = 21,\t\t///< Test for unsigned carry\n CPUI_INT_SCARRY = 22,\t\t///< Test for signed carry\n CPUI_INT_SBORROW = 23,\t///< Test for signed borrow\n CPUI_INT_2COMP = 24,\t\t///< Twos complement\n CPUI_INT_NEGATE = 25,\t\t///< Logical/bitwise negation (~)\n CPUI_INT_XOR = 26,\t\t///< Logical/bitwise exclusive-or (^)\n CPUI_INT_AND = 27,\t\t///< Logical/bitwise and (&)\n CPUI_INT_OR = 28,\t\t///< Logical/bitwise or (|)\n CPUI_INT_LEFT = 29,\t\t///< Left shift (<<)\n CPUI_INT_RIGHT = 30,\t\t///< Right shift, logical (>>)\n CPUI_INT_SRIGHT = 31,\t\t///< Right shift, arithmetic (>>)\n CPUI_INT_MULT = 32,\t\t///< Integer multiplication, signed and unsigned (*)\n CPUI_INT_DIV = 33,\t\t///< Integer division, unsigned (/)\n CPUI_INT_SDIV = 34,\t\t///< Integer division, signed (/)\n CPUI_INT_REM = 35,\t\t///< Remainder/modulo, unsigned (%)\n CPUI_INT_SREM = 36,\t\t///< Remainder/modulo, signed (%)\n\n CPUI_BOOL_NEGATE = 37,\t///< Boolean negate (!)\n CPUI_BOOL_XOR = 38,\t\t///< Boolean exclusive-or (^^)\n CPUI_BOOL_AND = 39,\t\t///< Boolean and (&&)\n CPUI_BOOL_OR = 40,\t\t///< Boolean or (||)\n\n\t\t\t\t// Floating point operations\n\n CPUI_FLOAT_EQUAL = 41, ///< Floating-point comparison, equality (==)\n CPUI_FLOAT_NOTEQUAL = 42,\t///< Floating-point comparison, in-equality (!=)\n CPUI_FLOAT_LESS = 43,\t\t///< Floating-point comparison, less-than (<)\n CPUI_FLOAT_LESSEQUAL = 44,\t///< Floating-point comparison, less-than-or-equal (<=)\n // Slot 45 is currently unused\n CPUI_FLOAT_NAN = 46,\t ///< Not-a-number test (NaN)\n \n CPUI_FLOAT_ADD = 47, ///< Floating-point addition (+)\n CPUI_FLOAT_DIV = 48, ///< Floating-point division (/)\n CPUI_FLOAT_MULT = 49, ///< Floating-point multiplication (*)\n CPUI_FLOAT_SUB = 50, ///< Floating-point subtraction (-)\n CPUI_FLOAT_NEG = 51, ///< Floating-point negation (-)\n CPUI_FLOAT_ABS = 52, ///< Floating-point absolute value (abs)\n CPUI_FLOAT_SQRT = 53, ///< Floating-point square root (sqrt)\n\n CPUI_FLOAT_INT2FLOAT = 54, ///< Convert an integer to a floating-point\n CPUI_FLOAT_FLOAT2FLOAT = 55, ///< Convert between different floating-point sizes\n CPUI_FLOAT_TRUNC = 56, ///< Round towards zero\n CPUI_FLOAT_CEIL = 57, ///< Round towards +infinity\n CPUI_FLOAT_FLOOR = 58, ///< Round towards -infinity\n CPUI_FLOAT_ROUND = 59,\t///< Round towards nearest\n\n\t\t\t\t// Internal opcodes for simplification. Not\n\t\t\t\t// typically generated in a direct translation.\n\n\t\t\t\t// Data-flow operations\n CPUI_MULTIEQUAL = 60,\t\t///< Phi-node operator\n CPUI_INDIRECT = 61,\t\t///< Copy with an indirect effect\n CPUI_PIECE = 62,\t\t///< Concatenate\n CPUI_SUBPIECE = 63,\t\t///< Truncate\n\n CPUI_CAST = 64,\t\t///< Cast from one data-type to another\n CPUI_PTRADD = 65,\t\t///< Index into an array ([])\n CPUI_PTRSUB = 66,\t\t///< Drill down to a sub-field (->)\n CPUI_SEGMENTOP = 67,\t\t///< Look-up a \\e segmented address\n CPUI_CPOOLREF = 68,\t\t///< Recover a value from the \\e constant \\e pool\n CPUI_NEW = 69,\t\t///< Allocate a new object (new)\n CPUI_INSERT = 70,\t\t///< Insert a bit-range\n CPUI_EXTRACT = 71,\t\t///< Extract a bit-range\n CPUI_POPCOUNT = 72,\t\t///< Count the 1-bits\n CPUI_LZCOUNT = 73,\t\t///< Count the leading 0-bits\n\n CPUI_MAX = 74\t\t\t///< Value indicating the end of the op-code values\n};\n\nextern const char *get_opname(OpCode opc);\t\t///< Convert an OpCode to the name as a string\nextern OpCode get_opcode(const string &nm);\t\t///< Convert a name string to the matching OpCode\n\nextern OpCode get_booleanflip(OpCode opc,bool &reorder);\t///< Get the complementary OpCode\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/partmap.hh", "content": "/* ###\n * IP: GHIDRA\n * NOTE: very generic partition container\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file partmap.hh\n/// \\brief The partmap<> template mapping a linear space to value objects\n#ifndef __PARTMAP_HH__\n#define __PARTMAP_HH__\n\n#include \n\nnamespace ghidra {\n\n/// \\brief A map from a linear space to value objects\n///\n/// The partmap is a template class taking:\n/// - _linetype which represents an element in the linear space\n/// - _valuetype which are the objects that linear space maps to\n///\n/// Let R be the linear space with an ordering, and let { a_i } be a finite set\n/// of points in R.\n/// The a_i partition R into a finite number of disjoint sets\n/// { x : x < a_0 }, { x : x>=a_0 && x < a_1 }, ...\n/// { x : x>=a_i && x < a_i+1 }, ...\n/// { x : x>=a_n }\n///\n/// A partmap maps elements of this partition to _valuetype objects\n/// A _valuetype is then associated with any element x in R by\n/// looking up the value associated with the partition element\n/// containing x.\n///\n/// The map is defined by starting with a \\e default value object that applies\n/// to the whole linear space. Then \\e split points are introduced, one at a time,\n/// in the linear space. At each split point, the associated value object is split\n/// into two objects. At any point the value object describing some part of the linear space\n/// can be changed.\ntemplate\nclass partmap {\npublic:\n typedef std::map<_linetype,_valuetype> maptype;\t\t///< Defining the map from split points to value objects\n typedef typename maptype::iterator iterator;\t\t\t///< A partmap iterator is an iterator into the map\n typedef typename maptype::const_iterator const_iterator;\t///< A constant iterator\nprivate:\n maptype database;\t\t\t\t\t\t///< Map from linear split points to the value objects\n _valuetype defaultvalue;\t\t\t\t\t///< The value object \\e before the first split point\npublic:\n _valuetype &getValue(const _linetype &pnt);\t\t\t///< Get the value object at a point\n const _valuetype &getValue(const _linetype &pnt) const;\t///< Get the value object at a point\n const _valuetype &bounds(const _linetype &pnt,_linetype &before,_linetype &after,int &valid) const;\n _valuetype &split(const _linetype &pnt);\t\t\t///< Introduce a new split point\n const _valuetype &defaultValue(void) const { return defaultvalue; }\t///< Get the default value object\n _valuetype &defaultValue(void) { return defaultvalue; }\t\t///< Get the default value object\n _valuetype & clearRange(const _linetype &pnt1,const _linetype &pnt2);\t///< Clear a range of split points\n const_iterator begin(void) const { return database.begin(); }\t\t///< Beginning of split points\n const_iterator end(void) const { return database.end(); }\t\t///< End of split points\n iterator begin(void) { return database.begin(); }\t\t\t///< Beginning of split points\n iterator end(void) { return database.end(); }\t\t\t\t///< End of split points\n const_iterator begin(const _linetype &pnt) const { return database.lower_bound(pnt); }\t///< Get first split point after given point\n iterator begin(const _linetype &pnt) { return database.lower_bound(pnt); }\t///< Get first split point after given point\n void clear(void) { database.clear(); }\t\t\t\t///< Clear all split points\n bool empty(void) const { return database.empty(); }\t\t\t///< Return \\b true if there are no split points\n};\n\n/// Look up the first split point coming before the given point\n/// and return the value object it maps to. If there is no earlier split point\n/// return the default value.\n/// \\param pnt is the given point in the linear space\n/// \\return the corresponding value object\ntemplate\n _valuetype &partmap<_linetype,_valuetype>::\n getValue(const _linetype &pnt)\n \n {\n iterator iter;\n\n iter = database.upper_bound(pnt);\n if (iter == database.begin())\n return defaultvalue;\n --iter;\n return (*iter).second;\n }\n\n/// Look up the first split point coming before the given point\n/// and return the value object it maps to. If there is no earlier split point\n/// return the default value.\n/// \\param pnt is the given point in the linear space\n/// \\return the corresponding value object\ntemplate\n const _valuetype &partmap<_linetype,_valuetype>::\n getValue(const _linetype &pnt) const\n \n {\n const_iterator iter;\n \n iter = database.upper_bound(pnt);\n if (iter == database.begin())\n return defaultvalue;\n --iter;\n return (*iter).second;\n }\n\n/// Add (if not already present) a point to the linear partition.\n/// \\param pnt is the (new) point\n/// \\return the (possibly) new value object for the range starting at the point\ntemplate\n _valuetype &partmap<_linetype,_valuetype>::\n split(const _linetype &pnt)\n\n {\n iterator iter;\n \n iter = database.upper_bound(pnt);\n if (iter != database.begin()) {\n --iter;\n if ((*iter).first == pnt)\t// point matches exactly\n\treturn (*iter).second;\t// Return old ref\n _valuetype &newref( database[pnt] ); // Create new ref at point\n newref = (*iter).second;\t// Copy of original partition value\n return newref;\n }\n _valuetype &newref( database[pnt] ); // Create new ref at point\n newref = defaultvalue;\t// Copy of defaultvalue\n return newref;\n }\n\n/// Split points are introduced at the two boundary points of the given range,\n/// and all split points in between are removed. The value object that was initially\n/// present at the left-most boundary point becomes the value (as a copy) for the whole range.\n/// \\param pnt1 is the left-most boundary point of the range\n/// \\param pnt2 is the right-most boundary point\n/// \\return the value object assigned to the range\ntemplate\n _valuetype &partmap<_linetype,_valuetype>::\n clearRange(const _linetype &pnt1,const _linetype &pnt2)\n {\n split(pnt1);\n split(pnt2);\n iterator beg = begin(pnt1);\n iterator end = begin(pnt2);\n \n _valuetype &ref( (*beg).second );\n ++beg;\n database.erase(beg,end);\n return ref;\n } \n\n/// \\brief Get the value object for a given point and return the range over which the value object applies\n///\n/// Pass back a \\b before and \\b after point defining the maximal range over which the value applies.\n/// An additional validity code is passed back describing which of the bounding points apply:\n/// - 0 if both bounds apply\n/// - 1 if there is no lower bound\n/// - 2 if there is no upper bound,\n/// - 3 if there is neither a lower or upper bound\n/// \\param pnt is the given point around which to compute the range\n/// \\param before is a reference to the passed back lower bound\n/// \\param after is a reference to the passed back upper bound\n/// \\param valid is a reference to the passed back validity code\n/// \\return the corresponding value object\ntemplate\n const _valuetype &partmap<_linetype,_valuetype>::\n bounds(const _linetype &pnt,_linetype &before,_linetype &after,int &valid) const\n {\n if (database.empty()) {\n valid = 3;\n return defaultvalue;\n }\n const_iterator iter,enditer;\n \n enditer = database.upper_bound(pnt);\n if (enditer != database.begin()) {\n iter = enditer;\n --iter;\n before = (*iter).first;\n if (enditer == database.end())\n\tvalid = 2;\t\t// No upperbound\n else {\n\tafter = (*enditer).first;\n\tvalid = 0;\t\t// Fully bounded\n }\n return (*iter).second;\n }\n valid = 1;\t\t\t// No lowerbound\n after = (*enditer).first;\n return defaultvalue;\n }\n\n} // End namespace ghidra\n#endif\n\n#if 0\n\n#include \nusing std::cout;\n\nint main(int argc,char **argv)\n\n{\n partmap data;\n\n data.defaultValue() = 0;\n data.split(5) = 5;\n data.split(2) = 2;\n data.split(3) = 4;\n data.split(3) = 3;\n\n cout << data.getValue(6) << endl;\n cout << data.getValue(8) << endl;\n cout << data.getValue(4) << endl;\n cout << data.getValue(1) << endl;\n \n partmap::const_iterator iter;\n\n iter = data.begin(3);\n while(iter!=data.end()) {\n cout << (*iter).second << endl;\n ++iter;\n }\n}\n#endif\n\n" }, { "path": "pypcode/sleigh/pcodecompile.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"pcodecompile.hh\"\n\nnamespace ghidra {\n\nstring Location::format(void) const\n\n{\n ostringstream s;\n s << filename << \":\" << dec << lineno;\n return s.str();\n}\n\n ExprTree::ExprTree(VarnodeTpl *vn)\n\n{\n outvn = vn;\n ops = new vector;\n}\n\nExprTree::ExprTree(OpTpl *op)\n\n{\n ops = new vector;\n ops->push_back(op);\n if (op->getOut() != (VarnodeTpl *)0)\n outvn = new VarnodeTpl(*op->getOut());\n else\n outvn = (VarnodeTpl *)0;\n}\n\nExprTree::~ExprTree(void)\n\n{\n if (outvn != (VarnodeTpl *)0)\n delete outvn;\n if (ops != (vector *)0) {\n for(int4 i=0;isize();++i)\n delete (*ops)[i];\n delete ops;\n }\n}\n\nvector *ExprTree::appendParams(OpTpl *op,vector *param)\n\n{\t\t\t\t// Create op expression with entire list of expression\n\t\t\t\t// inputs\n vector *res = new vector;\n \n for(int4 i=0;isize();++i) {\n res->insert(res->end(),(*param)[i]->ops->begin(),(*param)[i]->ops->end());\n (*param)[i]->ops->clear();\n op->addInput((*param)[i]->outvn);\n (*param)[i]->outvn = (VarnodeTpl *)0;\n delete (*param)[i];\n }\n res->push_back(op);\n delete param;\n return res;\n}\n\nvector *ExprTree::toVector(ExprTree *expr)\n\n{\t\t\t\t// Grab the op vector and delete the output expression\n vector *res = expr->ops;\n expr->ops = (vector *)0;\n delete expr;\n return res;\n}\n\nvoid ExprTree::setOutput(VarnodeTpl *newout)\n\n{\t\t\t\t// Force the output of the expression to be new out\n\t\t\t\t// If the original output is named, this requires\n\t\t\t\t// an extra COPY op\n OpTpl *op;\n if (outvn == (VarnodeTpl *)0)\n throw SleighError(\"Expression has no output\");\n if (outvn->isUnnamed()) {\n delete outvn;\n op = ops->back();\n op->clearOutput();\n op->setOutput(newout);\n }\n else {\n op = new OpTpl(CPUI_COPY);\n op->addInput(outvn);\n op->setOutput(newout);\n ops->push_back(op);\n }\n outvn = new VarnodeTpl(*newout);\n}\n\nvoid PcodeCompile::force_size(VarnodeTpl *vt,const ConstTpl &size,const vector &ops)\n\n{\n if ((vt->getSize().getType()!=ConstTpl::real)||(vt->getSize().getReal() != 0))\n return;\t\t\t// Size already exists\n\n vt->setSize(size);\n if (!vt->isLocalTemp()) return;\n\t\t\t\t// If the variable is a local temporary\n\t\t\t\t// The size may need to be propagated to the various\n\t\t\t\t// uses of the variable\n OpTpl *op;\n VarnodeTpl *vn;\n\n for(int4 i=0;igetOut();\n if ((vn!=(VarnodeTpl *)0)&&(vn->isLocalTemp())) {\n if (vn->getOffset() == vt->getOffset()) {\n\tif ((size.getType() == ConstTpl::real)&&(vn->getSize().getType() == ConstTpl::real)&&\n\t (vn->getSize().getReal() != 0) && (vn->getSize().getReal() != size.getReal()))\n\t throw SleighError(\"Localtemp size mismatch\");\n\tvn->setSize(size);\n }\n }\n for(int4 j=0;jnumInput();++j) {\n vn = op->getIn(j);\n if (vn->isLocalTemp()&&(vn->getOffset()==vt->getOffset())) {\n\tif ((size.getType() == ConstTpl::real)&&(vn->getSize().getType() == ConstTpl::real)&&\n\t (vn->getSize().getReal() != 0) && (vn->getSize().getReal() != size.getReal()))\n\t throw SleighError(\"Localtemp size mismatch\");\n\tvn->setSize(size);\n }\n }\n }\n}\n\nvoid PcodeCompile::matchSize(int4 j,OpTpl *op,bool inputonly,const vector &ops)\n\n{\t\t\t\t// Find something to fill in zero size varnode\n\t\t\t\t// j is the slot we are trying to fill (-1=output)\n\t\t\t\t// Don't check output for non-zero if inputonly is true\n VarnodeTpl *match = (VarnodeTpl *)0;\n VarnodeTpl *vt;\n int4 i,inputsize;\n\n vt = (j==-1) ? op->getOut() : op->getIn(j);\n if (!inputonly) {\n if (op->getOut() != (VarnodeTpl *)0)\n if (!op->getOut()->isZeroSize())\n\tmatch = op->getOut();\n }\n inputsize = op->numInput();\n for(i=0;igetIn(i)->isZeroSize()) continue;\n match = op->getIn(i);\n }\n if (match != (VarnodeTpl *)0)\n force_size(vt,match->getSize(),ops);\n}\n\nvoid PcodeCompile::fillinZero(OpTpl *op,const vector &ops)\n\n{\t\t\t\t// Try to get rid of zero size varnodes in op\n // Right now this is written assuming operands for the constructor are\n // are built before any other pcode in the constructor is generated\n\n int4 inputsize,i;\n\n switch(op->getOpcode()) {\n case CPUI_COPY:\t\t\t// Instructions where all inputs and output are same size\n case CPUI_INT_ADD:\n case CPUI_INT_SUB:\n case CPUI_INT_2COMP:\n case CPUI_INT_NEGATE:\n case CPUI_INT_XOR:\n case CPUI_INT_AND:\n case CPUI_INT_OR:\n case CPUI_INT_MULT:\n case CPUI_INT_DIV:\n case CPUI_INT_SDIV:\n case CPUI_INT_REM:\n case CPUI_INT_SREM:\n case CPUI_FLOAT_ADD:\n case CPUI_FLOAT_DIV:\n case CPUI_FLOAT_MULT:\n case CPUI_FLOAT_SUB:\n case CPUI_FLOAT_NEG:\n case CPUI_FLOAT_ABS:\n case CPUI_FLOAT_SQRT:\n case CPUI_FLOAT_CEIL:\n case CPUI_FLOAT_FLOOR:\n case CPUI_FLOAT_ROUND:\n if ((op->getOut()!=(VarnodeTpl *)0)&&(op->getOut()->isZeroSize()))\n matchSize(-1,op,false,ops);\n inputsize = op->numInput();\n for(i=0;igetIn(i)->isZeroSize())\n\tmatchSize(i,op,false,ops);\n break;\n case CPUI_INT_EQUAL:\t\t// Instructions with bool output\n case CPUI_INT_NOTEQUAL:\n case CPUI_INT_SLESS:\n case CPUI_INT_SLESSEQUAL:\n case CPUI_INT_LESS:\n case CPUI_INT_LESSEQUAL:\n case CPUI_INT_CARRY:\n case CPUI_INT_SCARRY:\n case CPUI_INT_SBORROW:\n case CPUI_FLOAT_EQUAL:\n case CPUI_FLOAT_NOTEQUAL:\n case CPUI_FLOAT_LESS:\n case CPUI_FLOAT_LESSEQUAL:\n case CPUI_FLOAT_NAN:\n case CPUI_BOOL_NEGATE:\n case CPUI_BOOL_XOR:\n case CPUI_BOOL_AND:\n case CPUI_BOOL_OR:\n if (op->getOut()->isZeroSize())\n force_size(op->getOut(),ConstTpl(ConstTpl::real,1),ops);\n inputsize = op->numInput();\n for(i=0;igetIn(i)->isZeroSize())\n\tmatchSize(i,op,true,ops);\n break;\n // The shift amount does not necessarily have to be the same size\n // But if no size is specified, assume it is the same size\n case CPUI_INT_LEFT:\n case CPUI_INT_RIGHT:\n case CPUI_INT_SRIGHT:\n if (op->getOut()->isZeroSize()) {\n if (!op->getIn(0)->isZeroSize())\n\tforce_size(op->getOut(),op->getIn(0)->getSize(),ops);\n }\n else if (op->getIn(0)->isZeroSize())\n force_size(op->getIn(0),op->getOut()->getSize(),ops);\n // fallthru to subpiece constant check\n case CPUI_SUBPIECE:\n if (op->getIn(1)->isZeroSize())\n force_size(op->getIn(1),ConstTpl(ConstTpl::real,4),ops);\n break;\n case CPUI_CPOOLREF:\n if (op->getOut()->isZeroSize() && (!op->getIn(0)->isZeroSize()))\n force_size(op->getOut(),op->getIn(0)->getSize(),ops);\n if (op->getIn(0)->isZeroSize() && (!op->getOut()->isZeroSize()))\n force_size(op->getIn(0),op->getOut()->getSize(),ops);\n for(i=1;inumInput();++i) {\n if (op->getIn(i)->isZeroSize())\n\tforce_size(op->getIn(i),ConstTpl(ConstTpl::real,sizeof(uintb)),ops);\n }\n break;\n default:\n break;\n }\n}\n\nbool PcodeCompile::propagateSize(ConstructTpl *ct)\n\n{\t\t\t\t// Fill in size for varnodes with size 0\n\t\t\t\t// Return first OpTpl with a size 0 varnode\n\t\t\t\t// that cannot be filled in or NULL otherwise\n vector zerovec,zerovec2;\n vector::const_iterator iter;\n int4 lastsize;\n\n for(iter=ct->getOpvec().begin();iter!=ct->getOpvec().end();++iter)\n if ((*iter)->isZeroSize()) {\n fillinZero(*iter,ct->getOpvec());\n if ((*iter)->isZeroSize())\n\tzerovec.push_back(*iter);\n }\n lastsize = zerovec.size() + 1;\n while( zerovec.size() < lastsize ) {\n lastsize = zerovec.size();\n zerovec2.clear();\n for(iter=zerovec.begin();iter!=zerovec.end();++iter) {\n fillinZero(*iter,ct->getOpvec());\n if ((*iter)->isZeroSize())\n\tzerovec2.push_back( *iter );\n }\n zerovec = zerovec2;\n }\n if ( lastsize != 0 ) return false;\n return true;\n}\n\nVarnodeTpl *PcodeCompile::buildTemporary(void)\n\n{\t\t\t\t// Build temporary variable (with zerosize)\n VarnodeTpl *res = new VarnodeTpl(ConstTpl(uniqspace),\n\t\t\t\t ConstTpl(ConstTpl::real,allocateTemp()),\n\t\t\t\t ConstTpl(ConstTpl::real,0));\n res->setUnnamed(true);\n return res;\n}\n\nLabelSymbol *PcodeCompile::defineLabel(string *name)\n\n{ // Create a label symbol\n LabelSymbol *labsym = new LabelSymbol(*name,local_labelcount++);\n delete name;\n addSymbol(labsym);\t\t// Add symbol to local scope\n return labsym;\n}\n\nvector *PcodeCompile::placeLabel(LabelSymbol *labsym)\n\n{ // Create placeholder OpTpl for a label\n if (labsym->isPlaced()) {\n reportError(getLocation(labsym), \"Label '\" + labsym->getName() + \"' is placed more than once\");\n }\n labsym->setPlaced();\n vector *res = new vector;\n OpTpl *op = new OpTpl(LABELBUILD);\n VarnodeTpl *idvn = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t\t ConstTpl(ConstTpl::real,labsym->getIndex()),\n\t\t\t\t ConstTpl(ConstTpl::real,4));\n op->addInput(idvn);\n res->push_back(op);\n return res;\n}\n\nvector *PcodeCompile::newOutput(bool usesLocalKey,ExprTree *rhs,string *varname,uint4 size)\n\n{\n VarnodeSymbol *sym;\n VarnodeTpl *tmpvn = buildTemporary();\n if (size != 0)\n tmpvn->setSize(ConstTpl(ConstTpl::real,size)); // Size was explicitly specified\n else if ((rhs->getSize().getType()==ConstTpl::real)&&(rhs->getSize().getReal()!=0))\n tmpvn->setSize(rhs->getSize());\t// Inherit size from unnamed expression result\n\t\t\t\t// Only inherit if the size is real, otherwise we\n\t\t\t\t// cannot build the VarnodeSymbol with a placeholder constant\n rhs->setOutput(tmpvn);\n sym = new VarnodeSymbol(*varname,tmpvn->getSpace().getSpace(),tmpvn->getOffset().getReal(),tmpvn->getSize().getReal()); // Create new symbol regardless\n addSymbol(sym);\n if ((!usesLocalKey) && enforceLocalKey)\n reportError(getLocation(sym), \"Must use 'local' keyword to define symbol '\"+*varname + \"'\");\n delete varname;\n return ExprTree::toVector(rhs);\n}\n\nvoid PcodeCompile::newLocalDefinition(string *varname,uint4 size)\n\n{ // Create a new temporary symbol (without generating any pcode)\n VarnodeSymbol *sym;\n sym = new VarnodeSymbol(*varname,uniqspace,allocateTemp(),size);\n addSymbol(sym);\n delete varname;\n}\n\nExprTree *PcodeCompile::createOp(OpCode opc,ExprTree *vn)\n\n{\t\t\t\t// Create new expression with output -outvn-\n\t\t\t\t// built by performing -opc- on input vn.\n\t\t\t\t// Free input expression\n VarnodeTpl *outvn = buildTemporary();\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn->outvn);\n op->setOutput(outvn);\n vn->ops->push_back(op);\n vn->outvn = new VarnodeTpl(*outvn);\n return vn;\n}\n\nExprTree *PcodeCompile::createOp(OpCode opc,ExprTree *vn1,\n\t\t\t\t ExprTree *vn2)\n\n{\t\t\t\t// Create new expression with output -outvn-\n\t\t\t\t// built by performing -opc- on inputs vn1 and vn2.\n\t\t\t\t// Free input expressions\n VarnodeTpl *outvn = buildTemporary();\n vn1->ops->insert(vn1->ops->end(),vn2->ops->begin(),vn2->ops->end());\n vn2->ops->clear();\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn1->outvn);\n op->addInput(vn2->outvn);\n vn2->outvn = (VarnodeTpl *)0;\n op->setOutput(outvn);\n vn1->ops->push_back(op);\n vn1->outvn = new VarnodeTpl(*outvn);\n delete vn2;\n return vn1;\n}\n\nExprTree *PcodeCompile::createOpOut(VarnodeTpl *outvn,OpCode opc,\n\t\t\t\t ExprTree *vn1,ExprTree *vn2)\n{ // Create an op with explicit output and two inputs\n vn1->ops->insert(vn1->ops->end(),vn2->ops->begin(),vn2->ops->end());\n vn2->ops->clear();\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn1->outvn);\n op->addInput(vn2->outvn);\n vn2->outvn = (VarnodeTpl *)0;\n op->setOutput(outvn);\n vn1->ops->push_back(op);\n vn1->outvn = new VarnodeTpl(*outvn);\n delete vn2;\n return vn1;\n}\n\nExprTree *PcodeCompile::createOpOutUnary(VarnodeTpl *outvn,OpCode opc,ExprTree *vn)\n\n{ // Create an op with explicit output and 1 input\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn->outvn);\n op->setOutput(outvn);\n vn->ops->push_back(op);\n vn->outvn = new VarnodeTpl(*outvn);\n return vn;\n}\n\nvector *PcodeCompile::createOpNoOut(OpCode opc,ExprTree *vn)\n\n{\t\t\t\t// Create new expression by creating op with given -opc-\n\t\t\t\t// and single input vn. Free the input expression\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn->outvn);\n vn->outvn = (VarnodeTpl *)0;\t// There is no longer an output to this expression\n vector *res = vn->ops;\n vn->ops = (vector *)0;\n delete vn;\n res->push_back(op);\n return res;\n}\n\nvector *PcodeCompile::createOpNoOut(OpCode opc,ExprTree *vn1,ExprTree *vn2)\n\n{\t\t\t\t// Create new expression by creating op with given -opc-\n\t\t\t\t// and inputs vn1 and vn2. Free the input expressions\n vector *res = vn1->ops;\n vn1->ops = (vector *)0;\n res->insert(res->end(),vn2->ops->begin(),vn2->ops->end());\n vn2->ops->clear();\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn1->outvn);\n vn1->outvn = (VarnodeTpl *)0;\n op->addInput(vn2->outvn);\n vn2->outvn = (VarnodeTpl *)0;\n res->push_back(op);\n delete vn1;\n delete vn2;\n return res;\n}\n\nvector *PcodeCompile::createOpConst(OpCode opc,uintb val)\n\n{\n VarnodeTpl *vn = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t\t ConstTpl(ConstTpl::real,val),\n\t\t\t\t ConstTpl(ConstTpl::real,4));\n vector *res = new vector;\n OpTpl *op = new OpTpl(opc);\n op->addInput(vn);\n res->push_back(op);\n return res;\n}\n\nExprTree *PcodeCompile::createLoad(StarQuality *qual,ExprTree *ptr)\n\n{\t\t\t\t// Create new load expression, free ptr expression\n VarnodeTpl *outvn = buildTemporary();\n OpTpl *op = new OpTpl(CPUI_LOAD);\n // The first varnode input to the load is a constant reference to the AddrSpace being loaded\n // from. Internally, we really store the pointer to the AddrSpace as the reference, but this\n // isn't platform independent. So officially, we assume that the constant reference will be the\n // AddrSpace index. We can safely assume this always has size 4.\n VarnodeTpl *spcvn = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t\t qual->id,\n\t\t\t\t ConstTpl(ConstTpl::real,8));\n op->addInput(spcvn);\n op->addInput(ptr->outvn);\n op->setOutput(outvn);\n ptr->ops->push_back(op);\n if (qual->size > 0)\n force_size(outvn,ConstTpl(ConstTpl::real,qual->size),*ptr->ops);\n ptr->outvn = new VarnodeTpl(*outvn);\n delete qual;\n return ptr;\n}\n\nvector *PcodeCompile::createStore(StarQuality *qual,\n\t\t\t\t\t ExprTree *ptr,ExprTree *val)\n{\n vector *res = ptr->ops;\n ptr->ops = (vector *)0;\n res->insert(res->end(),val->ops->begin(),val->ops->end());\n val->ops->clear();\n OpTpl *op = new OpTpl(CPUI_STORE);\n // The first varnode input to the store is a constant reference to the AddrSpace being loaded\n // from. Internally, we really store the pointer to the AddrSpace as the reference, but this\n // isn't platform independent. So officially, we assume that the constant reference will be the\n // AddrSpace index. We can safely assume this always has size 4.\n VarnodeTpl *spcvn = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t\t qual->id,\n\t\t\t\t ConstTpl(ConstTpl::real,8));\n op->addInput(spcvn);\n op->addInput(ptr->outvn);\n op->addInput(val->outvn);\n res->push_back(op);\n force_size(val->outvn,ConstTpl(ConstTpl::real,qual->size),*res);\n ptr->outvn = (VarnodeTpl *)0;\n val->outvn = (VarnodeTpl *)0;\n delete ptr;\n delete val;\n delete qual;\n return res;\n}\n\nExprTree *PcodeCompile::createUserOp(UserOpSymbol *sym,vector *param)\n\n{ // Create userdefined pcode op, given symbol and parameters\n VarnodeTpl *outvn = buildTemporary();\n ExprTree *res = new ExprTree();\n res->ops = createUserOpNoOut(sym,param);\n res->ops->back()->setOutput(outvn);\n res->outvn = new VarnodeTpl(*outvn);\n return res;\n}\n\nvector *PcodeCompile::createUserOpNoOut(UserOpSymbol *sym,vector *param)\n\n{\n OpTpl *op = new OpTpl(CPUI_CALLOTHER);\n VarnodeTpl *vn = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t\t ConstTpl(ConstTpl::real,sym->getIndex()),\n\t\t\t\t ConstTpl(ConstTpl::real,4));\n op->addInput(vn);\n return ExprTree::appendParams(op,param);\n}\n\nExprTree *PcodeCompile::createVariadic(OpCode opc,vector *param)\n\n{\n VarnodeTpl *outvn = buildTemporary();\n ExprTree *res = new ExprTree();\n OpTpl *op = new OpTpl(opc);\n res->ops = ExprTree::appendParams(op,param);\n res->ops->back()->setOutput(outvn);\n res->outvn = new VarnodeTpl(*outvn);\n return res;\n}\n\nvoid PcodeCompile::appendOp(OpCode opc,ExprTree *res,uintb constval,int4 constsz)\n\n{ // Take output of res expression, combine with constant,\n // using opc operation, return the resulting expression\n OpTpl *op = new OpTpl(opc);\n VarnodeTpl *constvn = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t\t\t ConstTpl(ConstTpl::real,constval),\n\t\t\t\t\t ConstTpl(ConstTpl::real,constsz));\n VarnodeTpl *outvn = buildTemporary();\n op->addInput(res->outvn);\n op->addInput(constvn);\n op->setOutput(outvn);\n res->ops->push_back(op);\n res->outvn = new VarnodeTpl(*outvn);\n}\n\nVarnodeTpl *PcodeCompile::buildTruncatedVarnode(VarnodeTpl *basevn,uint4 bitoffset,uint4 numbits)\n\n{ // Build a truncated form -basevn- that matches the bitrange [ -bitoffset-, -numbits- ] if possible\n // using just ConstTpl mechanics, otherwise return null\n uint4 byteoffset = bitoffset / 8; // Convert to byte units\n uint4 numbytes = numbits / 8;\n uintb fullsz = 0;\n if (basevn->getSize().getType() == ConstTpl::real) {\n // If we know the size of base, make sure the bit range is in bounds\n fullsz = basevn->getSize().getReal();\n if (fullsz == 0) return (VarnodeTpl *)0;\n if (byteoffset + numbytes > fullsz)\n throw SleighError(\"Requested bit range out of bounds\");\n }\n\n if ((bitoffset % 8) != 0) return (VarnodeTpl *)0;\n if ((numbits % 8) != 0) return (VarnodeTpl *)0;\n\n ConstTpl::const_type offset_type = basevn->getOffset().getType();\n if ((offset_type != ConstTpl::real)&&(offset_type != ConstTpl::handle))\n return (VarnodeTpl *)0;\n\n ConstTpl specialoff;\n if (offset_type == ConstTpl::handle) {\n // We put in the correct adjustment to offset assuming things are little endian\n // We defer the correct big endian calculation until after the consistency check\n // because we need to know the subtable export sizes\n specialoff = ConstTpl(ConstTpl::handle,basevn->getOffset().getHandleIndex(),\n\t\t\t ConstTpl::v_offset_plus,byteoffset);\n }\n else { \n if (basevn->getSize().getType() != ConstTpl::real)\n throw SleighError(\"Could not construct requested bit range\");\n uintb plus;\n if (defaultspace->isBigEndian())\n plus = fullsz - (byteoffset + numbytes);\n else\n plus = byteoffset;\n specialoff = ConstTpl(ConstTpl::real,basevn->getOffset().getReal() + plus);\n }\n VarnodeTpl *res = new VarnodeTpl(basevn->getSpace(),specialoff,ConstTpl(ConstTpl::real,numbytes));\n return res;\n}\n\nvector *PcodeCompile::assignBitRange(VarnodeTpl *vn,uint4 bitoffset,uint4 numbits,ExprTree *rhs)\n\n{ // Create an expression assigning the rhs to a bitrange within sym\n string errmsg;\n if (numbits == 0)\n errmsg = \"Size of bitrange is zero\";\n uint4 smallsize = (numbits+7)/8; // Size of input (output of rhs)\n bool shiftneeded = (bitoffset != 0);\n bool zextneeded = true;\n uintb mask = (uintb)2;\n mask = ~(((mask<<(numbits-1))-1) << bitoffset);\n\n if (vn->getSize().getType()==ConstTpl::real) {\n // If we know the size of the bitranged varnode, we can\n // do some immediate checks, and possibly simplify things\n uint4 symsize = vn->getSize().getReal();\n if (symsize > 0)\n zextneeded = (symsize > smallsize);\n symsize *= 8;\t\t// Convert to number of bits\n if ((bitoffset>=symsize)||(bitoffset+numbits>symsize))\n errmsg = \"Assigned bitrange is bad\";\n else if ((bitoffset==0)&&(numbits==symsize))\n errmsg = \"Assigning to bitrange is superfluous\";\n }\n\n if (errmsg.size()>0) {\t// Was there an error condition\n reportError((const Location *)0, errmsg);\t// Report the error\n delete vn;\t\t\t// Clean up\n vector *resops = rhs->ops; // Passthru old expression\n rhs->ops = (vector *)0;\n delete rhs;\n return resops;\n }\n\n // We know what the size of the input has to be\n force_size(rhs->outvn,ConstTpl(ConstTpl::real,smallsize),*rhs->ops);\n\n ExprTree *res;\n VarnodeTpl *finalout = buildTruncatedVarnode(vn,bitoffset,numbits);\n if (finalout != (VarnodeTpl *)0) {\n delete vn;\t// Don't keep the original Varnode object\n res = createOpOutUnary(finalout,CPUI_COPY,rhs);\n }\n else {\n if (bitoffset + numbits > 64)\n errmsg = \"Assigned bitrange extends past first 64 bits\";\n res = new ExprTree(vn);\n appendOp(CPUI_INT_AND,res,mask,0);\n if (zextneeded)\n createOp(CPUI_INT_ZEXT,rhs);\n if (shiftneeded)\n appendOp(CPUI_INT_LEFT,rhs,bitoffset,4);\n \n finalout = new VarnodeTpl(*vn);\n res = createOpOut(finalout,CPUI_INT_OR,res,rhs);\n }\n if (errmsg.size() > 0)\n reportError((const Location *)0, errmsg);\n vector *resops = res->ops;\n res->ops = (vector *)0;\n delete res;\n return resops;\n}\n\nExprTree *PcodeCompile::createBitRange(SpecificSymbol *sym,uint4 bitoffset,uint4 numbits)\n\n{ // Create an expression computing the indicated bitrange of sym\n // The result is truncated to the smallest byte size that can\n // contain the indicated number of bits. The result has the\n // desired bits shifted all the way to the right\n string errmsg;\n if (numbits == 0)\n errmsg = \"Size of bitrange is zero\";\n VarnodeTpl *vn = sym->getVarnode();\n uint4 finalsize = (numbits+7)/8; // Round up to neareast byte size\n uint4 truncshift = 0;\n bool maskneeded = ((numbits%8)!=0);\n bool truncneeded = true;\n\n // Special case where we can set the size, without invoking\n // a truncation operator\n if ((errmsg.size()==0)&&(bitoffset==0)&&(!maskneeded)) {\n if ((vn->getSpace().getType()==ConstTpl::handle)&&vn->isZeroSize()) {\n vn->setSize(ConstTpl(ConstTpl::real,finalsize));\n ExprTree *res = new ExprTree(vn);\n // VarnodeTpl *cruft = buildTemporary();\n // delete cruft;\n return res;\n }\n }\n\n if (errmsg.size()==0) {\n VarnodeTpl *truncvn = buildTruncatedVarnode(vn,bitoffset,numbits);\n if (truncvn != (VarnodeTpl *)0) { // If we are able to construct a simple truncated varnode\n ExprTree *res = new ExprTree(truncvn); // Return just the varnode as an expression\n delete vn;\n return res;\n }\n }\n\n if (vn->getSize().getType()==ConstTpl::real) {\n // If we know the size of the input varnode, we can\n // do some immediate checks, and possibly simplify things\n uint4 insize = vn->getSize().getReal();\n if (insize > 0) {\n truncneeded = (finalsize < insize);\n insize *= 8;\t\t// Convert to number of bits\n if ((bitoffset >= insize)||(bitoffset+numbits > insize))\n\terrmsg = \"Bitrange is bad\";\n if (maskneeded && ((bitoffset+numbits)==insize))\n\tmaskneeded = false;\n }\n }\n\n uintb mask = (uintb)2;\n mask = ((mask<<(numbits-1))-1);\n \n if (truncneeded && ((bitoffset % 8)==0)) {\n truncshift = bitoffset/8;\n bitoffset = 0;\n }\n\n if ((bitoffset==0)&&(!truncneeded)&&(!maskneeded))\n errmsg = \"Superfluous bitrange\";\n\n if (maskneeded && (finalsize > 8))\n errmsg = \"Illegal masked bitrange producing varnode larger than 64 bits: \" + sym->getName();\n\n ExprTree *res = new ExprTree(vn);\n\n if (errmsg.size()>0) {\t// Check for error condition\n reportError(getLocation(sym), errmsg);\n return res;\n }\n\n if (bitoffset !=0)\n appendOp(CPUI_INT_RIGHT,res,bitoffset,4);\n if (truncneeded)\n appendOp(CPUI_SUBPIECE,res,truncshift,4);\n if (maskneeded)\n appendOp(CPUI_INT_AND,res,mask,finalsize);\n force_size(res->outvn,ConstTpl(ConstTpl::real,finalsize),*res->ops);\n return res;\n}\n\nVarnodeTpl *PcodeCompile::addressOf(VarnodeTpl *var,uint4 size)\n\n{\t\t\t\t// Produce constant varnode that is the offset\n\t\t\t\t// portion of varnode -var-\n if (size==0) {\t\t// If no size specified\n if (var->getSpace().getType() == ConstTpl::spaceid) {\n AddrSpace *spc = var->getSpace().getSpace();\t// Look to the particular space\n size = spc->getAddrSize(); // to see if it has a standard address size\n }\n }\n VarnodeTpl *res;\n if ((var->getOffset().getType() == ConstTpl::real)&&(var->getSpace().getType() == ConstTpl::spaceid)) {\n AddrSpace *spc = var->getSpace().getSpace();\n uintb off = AddrSpace::byteToAddress(var->getOffset().getReal(),spc->getWordSize());\n res = new VarnodeTpl(ConstTpl(constantspace),\n\t\t\t ConstTpl(ConstTpl::real,off),\n\t\t\t ConstTpl(ConstTpl::real,size));\n }\n else\n res = new VarnodeTpl(ConstTpl(constantspace),var->getOffset(),ConstTpl(ConstTpl::real,size));\n delete var;\n return res;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/pcodecompile.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __PCODECOMPILE_HH__\n#define __PCODECOMPILE_HH__\n\n#include \"slghsymbol.hh\"\n\nnamespace ghidra {\n\nclass Location {\n string filename;\n int4 lineno;\npublic:\n Location(void) {}\n Location(const string &fname, const int4 line) { filename = fname; lineno = line; }\n string getFilename(void) const { return filename; }\n int4 getLineno(void) const { return lineno; }\n string format(void) const;\n};\n\nstruct StarQuality {\n ConstTpl id;\n uint4 size;\n};\n\nclass ExprTree {\t\t// A flattened expression tree\n friend class PcodeCompile;\n vector *ops;\t// flattened ops making up the expression\n VarnodeTpl *outvn;\t\t// Output varnode of the expression\n\t\t\t\t// If the last op has an output, -outvn- is\n\t\t\t\t// a COPY of that varnode\npublic:\n ExprTree(void) { ops = (vector *)0; outvn = (VarnodeTpl *)0; }\n ExprTree(VarnodeTpl *vn);\n ExprTree(OpTpl *op);\n ~ExprTree(void);\n void setOutput(VarnodeTpl *newout);\n VarnodeTpl *getOut(void) { return outvn; }\n const ConstTpl &getSize(void) const { return outvn->getSize(); }\n static vector *appendParams(OpTpl *op,vector *param);\n static vector *toVector(ExprTree *expr);\n};\n\nclass PcodeCompile {\n AddrSpace *defaultspace;\n AddrSpace *constantspace;\n AddrSpace *uniqspace;\n uint4 local_labelcount;\t// Number of labels in current constructor\n bool enforceLocalKey;\t\t// Force slaspec to use 'local' keyword when defining temporary varnodes\n virtual uint4 allocateTemp(void)=0;\n virtual void addSymbol(SleighSymbol *sym)=0;\npublic:\n PcodeCompile(void) { defaultspace=(AddrSpace *)0; constantspace=(AddrSpace *)0;\n \t \t \t \t \t uniqspace=(AddrSpace *)0; local_labelcount=0; enforceLocalKey=false; }\n virtual ~PcodeCompile(void) {}\n virtual const Location *getLocation(SleighSymbol *sym) const=0;\n virtual void reportError(const Location *loc, const string &msg)=0;\n virtual void reportWarning(const Location *loc, const string &msg)=0;\n void resetLabelCount(void) { local_labelcount=0; }\n void setDefaultSpace(AddrSpace *spc) { defaultspace = spc; }\n void setConstantSpace(AddrSpace *spc) { constantspace = spc; }\n void setUniqueSpace(AddrSpace *spc) { uniqspace = spc; }\n void setEnforceLocalKey(bool val) { enforceLocalKey = val; }\n AddrSpace *getDefaultSpace(void) const { return defaultspace; }\n AddrSpace *getConstantSpace(void) const { return constantspace; }\n VarnodeTpl *buildTemporary(void);\n LabelSymbol *defineLabel(string *name);\n vector *placeLabel(LabelSymbol *sym);\n vector *newOutput(bool usesLocalKey,ExprTree *rhs,string *varname,uint4 size=0);\n void newLocalDefinition(string *varname,uint4 size=0);\n ExprTree *createOp(OpCode opc,ExprTree *vn);\n ExprTree *createOp(OpCode opc,ExprTree *vn1,ExprTree *vn2);\n ExprTree *createOpOut(VarnodeTpl *outvn,OpCode opc,ExprTree *vn1,ExprTree *vn2);\n ExprTree *createOpOutUnary(VarnodeTpl *outvn,OpCode opc,ExprTree *vn);\n vector *createOpNoOut(OpCode opc,ExprTree *vn);\n vector *createOpNoOut(OpCode opc,ExprTree *vn1,ExprTree *vn2);\n vector *createOpConst(OpCode opc,uintb val);\n ExprTree *createLoad(StarQuality *qual,ExprTree *ptr);\n vector *createStore(StarQuality *qual,ExprTree *ptr,ExprTree *val);\n ExprTree *createUserOp(UserOpSymbol *sym,vector *param);\n vector *createUserOpNoOut(UserOpSymbol *sym,vector *param);\n ExprTree *createVariadic(OpCode opc,vector *param);\n void appendOp(OpCode opc,ExprTree *res,uintb constval,int4 constsz);\n VarnodeTpl *buildTruncatedVarnode(VarnodeTpl *basevn,uint4 bitoffset,uint4 numbits);\n vector *assignBitRange(VarnodeTpl *vn,uint4 bitoffset,uint4 numbits,ExprTree *rhs);\n ExprTree *createBitRange(SpecificSymbol *sym,uint4 bitoffset,uint4 numbits);\n VarnodeTpl *addressOf(VarnodeTpl *var,uint4 size);\n static void force_size(VarnodeTpl *vt,const ConstTpl &size,const vector &ops);\n static void matchSize(int4 j,OpTpl *op,bool inputonly,const vector &ops);\n static void fillinZero(OpTpl *op,const vector &ops);\n static bool propagateSize(ConstructTpl *ct);\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/pcodeparse.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/* A Bison parser, made by GNU Bison 3.5.1. */\n\n/* Bison implementation for Yacc-like parsers in C\n\n Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation,\n Inc.\n\n This program is free software: you can redistribute it and/or modify\n it under the terms of the GNU General Public License as published by\n the Free Software Foundation, either version 3 of the License, or\n (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program. If not, see . */\n\n/* As a special exception, you may create a larger work that contains\n part or all of the Bison parser skeleton and distribute that work\n under terms of your choice, so long as that work isn't itself a\n parser generator using the skeleton or a modified version thereof\n as a parser skeleton. Alternatively, if you modify or redistribute\n the parser skeleton itself, you may (at your option) remove this\n special exception, which will cause the skeleton and the resulting\n Bison output files to be licensed under the GNU General Public\n License without this special exception.\n\n This special exception was added by the Free Software Foundation in\n version 2.2 of Bison. */\n\n/* C LALR(1) parser skeleton written by Richard Stallman, by\n simplifying the original so-called \"semantic\" parser. */\n\n/* All symbols defined below should begin with yy or YY, to avoid\n infringing on user name space. This should be done even for local\n variables, as they might otherwise be expanded by user macros.\n There are some unavoidable exceptions within include files to\n define necessary library symbols; they are noted \"INFRINGES ON\n USER NAME SPACE\" below. */\n\n/* Undocumented macros, especially those whose name start with YY_,\n are private implementation details. Do not rely on them. */\n\n/* Identify Bison output. */\n#define YYBISON 1\n\n/* Bison version. */\n#define YYBISON_VERSION \"3.5.1\"\n\n/* Skeleton name. */\n#define YYSKELETON_NAME \"yacc.c\"\n\n/* Pure parsers. */\n#define YYPURE 0\n\n/* Push parsers. */\n#define YYPUSH 0\n\n/* Pull parsers. */\n#define YYPULL 1\n\n/* Substitute the type names. */\n#define YYSTYPE PCODESTYPE\n/* Substitute the variable and function names. */\n#define yyparse pcodeparse\n#define yylex pcodelex\n#define yyerror pcodeerror\n#define yydebug pcodedebug\n#define yynerrs pcodenerrs\n#define yylval pcodelval\n#define yychar pcodechar\n\n/* First part of user prologue. */\n\n#include \"pcodeparse.hh\"\n\n//#define YYERROR_VERBOSE\nnamespace ghidra {\n\nextern int pcodelex(void);\nstatic PcodeSnippet *pcode;\nextern int pcodeerror(const char *str );\n\n\n# ifndef YY_CAST\n# ifdef __cplusplus\n# define YY_CAST(Type, Val) static_cast (Val)\n# define YY_REINTERPRET_CAST(Type, Val) reinterpret_cast (Val)\n# else\n# define YY_CAST(Type, Val) ((Type) (Val))\n# define YY_REINTERPRET_CAST(Type, Val) ((Type) (Val))\n# endif\n# endif\n# ifndef YY_NULLPTR\n# if defined __cplusplus\n# if 201103L <= __cplusplus\n# define YY_NULLPTR nullptr\n# else\n# define YY_NULLPTR 0\n# endif\n# else\n# define YY_NULLPTR ((void*)0)\n# endif\n# endif\n\n/* Enabling verbose error messages. */\n#ifdef YYERROR_VERBOSE\n# undef YYERROR_VERBOSE\n# define YYERROR_VERBOSE 1\n#else\n# define YYERROR_VERBOSE 0\n#endif\n\n\n/* Debug traces. */\n#ifndef PCODEDEBUG\n# if defined YYDEBUG\n#if YYDEBUG\n# define PCODEDEBUG 1\n# else\n# define PCODEDEBUG 0\n# endif\n# else /* ! defined YYDEBUG */\n# define PCODEDEBUG 0\n# endif /* ! defined YYDEBUG */\n#endif /* ! defined PCODEDEBUG */\n#if PCODEDEBUG\nextern int pcodedebug;\n#endif\n\n/* Token type. */\n#ifndef PCODETOKENTYPE\n# define PCODETOKENTYPE\n enum pcodetokentype\n {\n OP_BOOL_OR = 258,\n OP_BOOL_AND = 259,\n OP_BOOL_XOR = 260,\n OP_EQUAL = 261,\n OP_NOTEQUAL = 262,\n OP_FEQUAL = 263,\n OP_FNOTEQUAL = 264,\n OP_GREATEQUAL = 265,\n OP_LESSEQUAL = 266,\n OP_SLESS = 267,\n OP_SGREATEQUAL = 268,\n OP_SLESSEQUAL = 269,\n OP_SGREAT = 270,\n OP_FLESS = 271,\n OP_FGREAT = 272,\n OP_FLESSEQUAL = 273,\n OP_FGREATEQUAL = 274,\n OP_LEFT = 275,\n OP_RIGHT = 276,\n OP_SRIGHT = 277,\n OP_FADD = 278,\n OP_FSUB = 279,\n OP_SDIV = 280,\n OP_SREM = 281,\n OP_FMULT = 282,\n OP_FDIV = 283,\n OP_ZEXT = 284,\n OP_CARRY = 285,\n OP_BORROW = 286,\n OP_SEXT = 287,\n OP_SCARRY = 288,\n OP_SBORROW = 289,\n OP_NAN = 290,\n OP_ABS = 291,\n OP_SQRT = 292,\n OP_CEIL = 293,\n OP_FLOOR = 294,\n OP_ROUND = 295,\n OP_INT2FLOAT = 296,\n OP_FLOAT2FLOAT = 297,\n OP_TRUNC = 298,\n OP_NEW = 299,\n BADINTEGER = 300,\n GOTO_KEY = 301,\n CALL_KEY = 302,\n RETURN_KEY = 303,\n IF_KEY = 304,\n ENDOFSTREAM = 305,\n LOCAL_KEY = 306,\n INTEGER = 307,\n STRING = 308,\n SPACESYM = 309,\n USEROPSYM = 310,\n VARSYM = 311,\n OPERANDSYM = 312,\n JUMPSYM = 313,\n LABELSYM = 314\n };\n#endif\n\n/* Value type. */\n#if ! defined PCODESTYPE && ! defined PCODESTYPE_IS_DECLARED\nunion PCODESTYPE\n{\n\n uintb *i;\n string *str;\n vector *param;\n StarQuality *starqual;\n VarnodeTpl *varnode;\n ExprTree *tree;\n vector *stmt;\n ConstructTpl *sem;\n\n SpaceSymbol *spacesym;\n UserOpSymbol *useropsym;\n LabelSymbol *labelsym;\n OperandSymbol *operandsym;\n VarnodeSymbol *varsym;\n SpecificSymbol *specsym;\n\n\n};\ntypedef union PCODESTYPE PCODESTYPE;\n# define PCODESTYPE_IS_TRIVIAL 1\n# define PCODESTYPE_IS_DECLARED 1\n#endif\n\n\nextern PCODESTYPE pcodelval;\n\nint pcodeparse (void);\n\n\n\n\n\n#ifdef short\n# undef short\n#endif\n\n/* On compilers that do not define __PTRDIFF_MAX__ etc., make sure\n and (if available) are included\n so that the code can choose integer types of a good width. */\n\n#ifndef __PTRDIFF_MAX__\n# include /* INFRINGES ON USER NAME SPACE */\n# if defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__\n# include /* INFRINGES ON USER NAME SPACE */\n# define YY_STDINT_H\n# endif\n#endif\n\n/* Narrow types that promote to a signed type and that can represent a\n signed or unsigned integer of at least N bits. In tables they can\n save space and decrease cache pressure. Promoting to a signed type\n helps avoid bugs in integer arithmetic. */\n\n#ifdef __INT_LEAST8_MAX__\ntypedef __INT_LEAST8_TYPE__ yytype_int8;\n#elif defined YY_STDINT_H\ntypedef int_least8_t yytype_int8;\n#else\ntypedef signed char yytype_int8;\n#endif\n\n#ifdef __INT_LEAST16_MAX__\ntypedef __INT_LEAST16_TYPE__ yytype_int16;\n#elif defined YY_STDINT_H\ntypedef int_least16_t yytype_int16;\n#else\ntypedef short yytype_int16;\n#endif\n\n#if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__\ntypedef __UINT_LEAST8_TYPE__ yytype_uint8;\n#elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \\\n && UINT_LEAST8_MAX <= INT_MAX)\ntypedef uint_least8_t yytype_uint8;\n#elif !defined __UINT_LEAST8_MAX__ && UCHAR_MAX <= INT_MAX\ntypedef unsigned char yytype_uint8;\n#else\ntypedef short yytype_uint8;\n#endif\n\n#if defined __UINT_LEAST16_MAX__ && __UINT_LEAST16_MAX__ <= __INT_MAX__\ntypedef __UINT_LEAST16_TYPE__ yytype_uint16;\n#elif (!defined __UINT_LEAST16_MAX__ && defined YY_STDINT_H \\\n && UINT_LEAST16_MAX <= INT_MAX)\ntypedef uint_least16_t yytype_uint16;\n#elif !defined __UINT_LEAST16_MAX__ && USHRT_MAX <= INT_MAX\ntypedef unsigned short yytype_uint16;\n#else\ntypedef int yytype_uint16;\n#endif\n\n#ifndef YYPTRDIFF_T\n# if defined __PTRDIFF_TYPE__ && defined __PTRDIFF_MAX__\n# define YYPTRDIFF_T __PTRDIFF_TYPE__\n# define YYPTRDIFF_MAXIMUM __PTRDIFF_MAX__\n# elif defined PTRDIFF_MAX\n# ifndef ptrdiff_t\n# include /* INFRINGES ON USER NAME SPACE */\n# endif\n# define YYPTRDIFF_T ptrdiff_t\n# define YYPTRDIFF_MAXIMUM PTRDIFF_MAX\n# else\n# define YYPTRDIFF_T long\n# define YYPTRDIFF_MAXIMUM LONG_MAX\n# endif\n#endif\n\n#ifndef YYSIZE_T\n# ifdef __SIZE_TYPE__\n# define YYSIZE_T __SIZE_TYPE__\n# elif defined size_t\n# define YYSIZE_T size_t\n# elif defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__\n# include /* INFRINGES ON USER NAME SPACE */\n# define YYSIZE_T size_t\n# else\n# define YYSIZE_T unsigned\n# endif\n#endif\n\n#define YYSIZE_MAXIMUM \\\n YY_CAST (YYPTRDIFF_T, \\\n (YYPTRDIFF_MAXIMUM < YY_CAST (YYSIZE_T, -1) \\\n ? YYPTRDIFF_MAXIMUM \\\n : YY_CAST (YYSIZE_T, -1)))\n\n#define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X))\n\n/* Stored state numbers (used for stacks). */\ntypedef yytype_int16 yy_state_t;\n\n/* State numbers in computations. */\ntypedef int yy_state_fast_t;\n\n#ifndef YY_\n# if defined YYENABLE_NLS && YYENABLE_NLS\n# if ENABLE_NLS\n# include /* INFRINGES ON USER NAME SPACE */\n# define YY_(Msgid) dgettext (\"bison-runtime\", Msgid)\n# endif\n# endif\n# ifndef YY_\n# define YY_(Msgid) Msgid\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE_PURE\n# if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__)\n# define YY_ATTRIBUTE_PURE __attribute__ ((__pure__))\n# else\n# define YY_ATTRIBUTE_PURE\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE_UNUSED\n# if defined __GNUC__ && 2 < __GNUC__ + (7 <= __GNUC_MINOR__)\n# define YY_ATTRIBUTE_UNUSED __attribute__ ((__unused__))\n# else\n# define YY_ATTRIBUTE_UNUSED\n# endif\n#endif\n\n/* Suppress unused-variable warnings by \"using\" E. */\n#if ! defined lint || defined __GNUC__\n# define YYUSE(E) ((void) (E))\n#else\n# define YYUSE(E) /* empty */\n#endif\n\n#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__\n/* Suppress an incorrect diagnostic about yylval being uninitialized. */\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \\\n _Pragma (\"GCC diagnostic push\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wuninitialized\\\"\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wmaybe-uninitialized\\\"\")\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END \\\n _Pragma (\"GCC diagnostic pop\")\n#else\n# define YY_INITIAL_VALUE(Value) Value\n#endif\n#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END\n#endif\n#ifndef YY_INITIAL_VALUE\n# define YY_INITIAL_VALUE(Value) /* Nothing. */\n#endif\n\n#if defined __cplusplus && defined __GNUC__ && ! defined __ICC && 6 <= __GNUC__\n# define YY_IGNORE_USELESS_CAST_BEGIN \\\n _Pragma (\"GCC diagnostic push\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wuseless-cast\\\"\")\n# define YY_IGNORE_USELESS_CAST_END \\\n _Pragma (\"GCC diagnostic pop\")\n#endif\n#ifndef YY_IGNORE_USELESS_CAST_BEGIN\n# define YY_IGNORE_USELESS_CAST_BEGIN\n# define YY_IGNORE_USELESS_CAST_END\n#endif\n\n\n#define YY_ASSERT(E) ((void) (0 && (E)))\n\n#if ! defined yyoverflow || YYERROR_VERBOSE\n\n/* The parser invokes alloca or malloc; define the necessary symbols. */\n\n# ifdef YYSTACK_USE_ALLOCA\n# if YYSTACK_USE_ALLOCA\n# ifdef __GNUC__\n# define YYSTACK_ALLOC __builtin_alloca\n# elif defined __BUILTIN_VA_ARG_INCR\n# include /* INFRINGES ON USER NAME SPACE */\n# elif defined _AIX\n# define YYSTACK_ALLOC __alloca\n# elif defined _MSC_VER\n# include /* INFRINGES ON USER NAME SPACE */\n# define alloca _alloca\n# else\n# define YYSTACK_ALLOC alloca\n# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS\n# include /* INFRINGES ON USER NAME SPACE */\n /* Use EXIT_SUCCESS as a witness for stdlib.h. */\n# ifndef EXIT_SUCCESS\n# define EXIT_SUCCESS 0\n# endif\n# endif\n# endif\n# endif\n# endif\n\n# ifdef YYSTACK_ALLOC\n /* Pacify GCC's 'empty if-body' warning. */\n# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)\n# ifndef YYSTACK_ALLOC_MAXIMUM\n /* The OS might guarantee only one guard page at the bottom of the stack,\n and a page size can be as small as 4096 bytes. So we cannot safely\n invoke alloca (N) if N exceeds 4096. Use a slightly smaller number\n to allow for a few compiler-allocated temporary stack slots. */\n# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */\n# endif\n# else\n# define YYSTACK_ALLOC YYMALLOC\n# define YYSTACK_FREE YYFREE\n# ifndef YYSTACK_ALLOC_MAXIMUM\n# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM\n# endif\n# if (defined __cplusplus && ! defined EXIT_SUCCESS \\\n && ! ((defined YYMALLOC || defined malloc) \\\n && (defined YYFREE || defined free)))\n# include /* INFRINGES ON USER NAME SPACE */\n# ifndef EXIT_SUCCESS\n# define EXIT_SUCCESS 0\n# endif\n# endif\n# ifndef YYMALLOC\n# define YYMALLOC malloc\n# if ! defined malloc && ! defined EXIT_SUCCESS\nvoid *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */\n# endif\n# endif\n# ifndef YYFREE\n# define YYFREE free\n# if ! defined free && ! defined EXIT_SUCCESS\nvoid free (void *); /* INFRINGES ON USER NAME SPACE */\n# endif\n# endif\n# endif\n#endif /* ! defined yyoverflow || YYERROR_VERBOSE */\n\n\n#if (! defined yyoverflow \\\n && (! defined __cplusplus \\\n || (defined PCODESTYPE_IS_TRIVIAL && PCODESTYPE_IS_TRIVIAL)))\n\n/* A type that is properly aligned for any stack member. */\nunion yyalloc\n{\n yy_state_t yyss_alloc;\n YYSTYPE yyvs_alloc;\n};\n\n/* The size of the maximum gap between one aligned stack and the next. */\n# define YYSTACK_GAP_MAXIMUM (YYSIZEOF (union yyalloc) - 1)\n\n/* The size of an array large to enough to hold all stacks, each with\n N elements. */\n# define YYSTACK_BYTES(N) \\\n ((N) * (YYSIZEOF (yy_state_t) + YYSIZEOF (YYSTYPE)) \\\n + YYSTACK_GAP_MAXIMUM)\n\n# define YYCOPY_NEEDED 1\n\n/* Relocate STACK from its old location to the new one. The\n local variables YYSIZE and YYSTACKSIZE give the old and new number of\n elements in the stack, and YYPTR gives the new location of the\n stack. Advance YYPTR to a properly aligned location for the next\n stack. */\n# define YYSTACK_RELOCATE(Stack_alloc, Stack) \\\n do \\\n { \\\n YYPTRDIFF_T yynewbytes; \\\n YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \\\n Stack = &yyptr->Stack_alloc; \\\n yynewbytes = yystacksize * YYSIZEOF (*Stack) + YYSTACK_GAP_MAXIMUM; \\\n yyptr += yynewbytes / YYSIZEOF (*yyptr); \\\n } \\\n while (0)\n\n#endif\n\n#if defined YYCOPY_NEEDED && YYCOPY_NEEDED\n/* Copy COUNT objects from SRC to DST. The source and destination do\n not overlap. */\n# ifndef YYCOPY\n# if defined __GNUC__ && 1 < __GNUC__\n# define YYCOPY(Dst, Src, Count) \\\n __builtin_memcpy (Dst, Src, YY_CAST (YYSIZE_T, (Count)) * sizeof (*(Src)))\n# else\n# define YYCOPY(Dst, Src, Count) \\\n do \\\n { \\\n YYPTRDIFF_T yyi; \\\n for (yyi = 0; yyi < (Count); yyi++) \\\n (Dst)[yyi] = (Src)[yyi]; \\\n } \\\n while (0)\n# endif\n# endif\n#endif /* !YYCOPY_NEEDED */\n\n/* YYFINAL -- State number of the termination state. */\n#define YYFINAL 3\n/* YYLAST -- Last index in YYTABLE. */\n#define YYLAST 2214\n\n/* YYNTOKENS -- Number of terminals. */\n#define YYNTOKENS 80\n/* YYNNTS -- Number of nonterminals. */\n#define YYNNTS 13\n/* YYNRULES -- Number of rules. */\n#define YYNRULES 116\n/* YYNSTATES -- Number of states. */\n#define YYNSTATES 294\n\n#define YYUNDEFTOK 2\n#define YYMAXUTOK 314\n\n\n/* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM\n as returned by yylex, with out-of-bounds checking. */\n#define YYTRANSLATE(YYX) \\\n (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)\n\n/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM\n as returned by yylex. */\nstatic const yytype_int8 yytranslate[] =\n{\n 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 40, 2, 2, 2, 35, 9, 2,\n 75, 76, 33, 29, 78, 30, 2, 34, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 73, 7,\n 14, 74, 15, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 77, 2, 79, 8, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 6, 2, 41, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,\n 5, 10, 11, 12, 13, 16, 17, 18, 19, 20,\n 21, 22, 23, 24, 25, 26, 27, 28, 31, 32,\n 36, 37, 38, 39, 42, 43, 44, 45, 46, 47,\n 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\n 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,\n 68, 69, 70, 71, 72\n};\n\n#if PCODEDEBUG\n /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */\nstatic const yytype_uint8 yyrline[] =\n{\n 0, 99, 99, 101, 102, 103, 104, 106, 107, 108,\n 109, 110, 111, 112, 113, 114, 115, 116, 117, 118,\n 119, 120, 121, 122, 123, 124, 126, 127, 128, 129,\n 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,\n 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,\n 170, 171, 172, 173, 174, 175, 176, 177, 178, 179,\n 180, 181, 182, 183, 184, 185, 186, 187, 188, 190,\n 191, 192, 193, 195, 196, 197, 198, 199, 200, 202,\n 203, 204, 206, 207, 208, 209, 210, 212, 213, 215,\n 216, 218, 219, 220, 222, 223, 224\n};\n#endif\n\n#if PCODEDEBUG || YYERROR_VERBOSE || 0\n/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.\n First, the terminals, then, starting at YYNTOKENS, nonterminals. */\nstatic const char *const yytname[] =\n{\n \"$end\", \"error\", \"$undefined\", \"OP_BOOL_OR\", \"OP_BOOL_AND\",\n \"OP_BOOL_XOR\", \"'|'\", \"';'\", \"'^'\", \"'&'\", \"OP_EQUAL\", \"OP_NOTEQUAL\",\n \"OP_FEQUAL\", \"OP_FNOTEQUAL\", \"'<'\", \"'>'\", \"OP_GREATEQUAL\",\n \"OP_LESSEQUAL\", \"OP_SLESS\", \"OP_SGREATEQUAL\", \"OP_SLESSEQUAL\",\n \"OP_SGREAT\", \"OP_FLESS\", \"OP_FGREAT\", \"OP_FLESSEQUAL\", \"OP_FGREATEQUAL\",\n \"OP_LEFT\", \"OP_RIGHT\", \"OP_SRIGHT\", \"'+'\", \"'-'\", \"OP_FADD\", \"OP_FSUB\",\n \"'*'\", \"'/'\", \"'%'\", \"OP_SDIV\", \"OP_SREM\", \"OP_FMULT\", \"OP_FDIV\", \"'!'\",\n \"'~'\", \"OP_ZEXT\", \"OP_CARRY\", \"OP_BORROW\", \"OP_SEXT\", \"OP_SCARRY\",\n \"OP_SBORROW\", \"OP_NAN\", \"OP_ABS\", \"OP_SQRT\", \"OP_CEIL\", \"OP_FLOOR\",\n \"OP_ROUND\", \"OP_INT2FLOAT\", \"OP_FLOAT2FLOAT\", \"OP_TRUNC\", \"OP_NEW\",\n \"BADINTEGER\", \"GOTO_KEY\", \"CALL_KEY\", \"RETURN_KEY\", \"IF_KEY\",\n \"ENDOFSTREAM\", \"LOCAL_KEY\", \"INTEGER\", \"STRING\", \"SPACESYM\", \"USEROPSYM\",\n \"VARSYM\", \"OPERANDSYM\", \"JUMPSYM\", \"LABELSYM\", \"':'\", \"'='\", \"'('\",\n \"')'\", \"'['\", \"','\", \"']'\", \"$accept\", \"rtl\", \"rtlmid\", \"statement\",\n \"expr\", \"sizedstar\", \"jumpdest\", \"varnode\", \"integervarnode\",\n \"lhsvarnode\", \"label\", \"specificsymbol\", \"paramlist\", YY_NULLPTR\n};\n#endif\n\n# ifdef YYPRINT\n/* YYTOKNUM[NUM] -- (External) token number corresponding to the\n (internal) symbol number NUM (which must be that of a token). */\nstatic const yytype_int16 yytoknum[] =\n{\n 0, 256, 257, 258, 259, 260, 124, 59, 94, 38,\n 261, 262, 263, 264, 60, 62, 265, 266, 267, 268,\n 269, 270, 271, 272, 273, 274, 275, 276, 277, 43,\n 45, 278, 279, 42, 47, 37, 280, 281, 282, 283,\n 33, 126, 284, 285, 286, 287, 288, 289, 290, 291,\n 292, 293, 294, 295, 296, 297, 298, 299, 300, 301,\n 302, 303, 304, 305, 306, 307, 308, 309, 310, 311,\n 312, 313, 314, 58, 61, 40, 41, 91, 44, 93\n};\n# endif\n\n#define YYPACT_NINF (-65)\n\n#define yypact_value_is_default(Yyn) \\\n ((Yyn) == YYPACT_NINF)\n\n#define YYTABLE_NINF (-109)\n\n#define yytable_value_is_error(Yyn) \\\n ((Yyn) == YYTABLE_NINF)\n\n /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing\n STATE-NUM. */\nstatic const yytype_int16 yypact[] =\n{\n -65, 32, 1720, -65, 308, -45, -23, -65, -6, 416,\n -1, 1670, -65, 74, -64, -48, -13, -65, -65, -65,\n -65, 1670, -51, -65, -44, -65, -16, -65, 7, -65,\n -65, 58, 66, 19, 18, -65, 24, -65, -65, 1670,\n 95, -65, 1670, 140, -65, 1670, 1670, 1670, 1670, 1670,\n 73, 115, 149, 152, 153, 154, 155, 156, 157, 158,\n 159, 160, 161, 162, 164, 167, 1670, 1789, 1670, -65,\n -7, 4, 169, 179, 180, 1670, 1670, 1635, 181, 182,\n 1670, 184, 529, -65, -65, -65, 171, 186, 146, -65,\n 183, -65, 273, -65, -65, -65, -65, 1670, 1670, 1670,\n 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670,\n 1670, 1670, 1670, 531, 1670, 1670, 1670, 1670, 1670, 1670,\n 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670,\n 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670,\n 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670, 1670,\n 9, -65, 189, -2, 190, -65, 191, 1670, -65, -65,\n 174, 1846, 2105, -25, 1670, 177, 185, 1883, 187, -65,\n 193, 178, 252, 253, 256, 600, 386, 669, 423, 494,\n 738, 807, 876, 945, 1014, 1083, 1152, 1221, 1290, 310,\n 63, -65, 2141, 2175, 2175, 632, 700, 768, 833, 833,\n 833, 833, 902, 902, 902, 902, 902, 902, 902, 902,\n 902, 902, 902, 902, 10, 10, 10, -19, -19, -19,\n -19, -65, -65, -65, -65, -65, -65, -65, 257, -65,\n 192, 194, 5, 1920, 1670, -65, 260, 1670, 1957, -65,\n -65, -65, 204, 205, -65, -65, -65, -65, -65, 1670,\n -65, 1670, 1670, -65, -65, -65, -65, -65, -65, -65,\n -65, -65, -65, 1670, -65, -65, -65, 206, -65, 1670,\n -65, 1994, -65, 2105, -65, 195, -65, 1359, 1428, 1497,\n 1566, 196, 2031, -65, 199, -65, -65, -65, -65, -65,\n -65, 1670, 2068, -65\n};\n\n /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.\n Performed when YYTABLE does not specify something else to do. Zero\n means the default is an error. */\nstatic const yytype_int8 yydefact[] =\n{\n 3, 0, 0, 1, 0, 0, 92, 103, 0, 0,\n 0, 0, 2, 0, 102, 101, 0, 111, 112, 113,\n 4, 0, 0, 100, 0, 25, 99, 101, 0, 105,\n 99, 0, 0, 0, 0, 95, 94, 98, 93, 0,\n 0, 97, 0, 0, 23, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 26,\n 99, 0, 0, 0, 0, 0, 114, 0, 0, 0,\n 0, 0, 0, 110, 109, 91, 0, 0, 0, 18,\n 0, 21, 0, 41, 68, 54, 42, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 114, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 27, 0, 0, 0, 5, 0, 0, 12, 104,\n 0, 0, 115, 0, 0, 0, 0, 0, 0, 106,\n 90, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 28, 57, 56, 55, 45, 43, 44, 31, 32,\n 58, 59, 33, 36, 34, 35, 37, 38, 39, 40,\n 60, 61, 62, 63, 46, 47, 48, 29, 30, 64,\n 65, 49, 50, 52, 51, 53, 66, 67, 0, 86,\n 0, 0, 0, 0, 0, 9, 0, 0, 0, 16,\n 17, 7, 0, 0, 96, 20, 22, 24, 72, 0,\n 71, 0, 0, 78, 69, 70, 80, 81, 82, 77,\n 76, 79, 83, 0, 88, 19, 85, 0, 6, 0,\n 8, 0, 14, 116, 13, 0, 89, 0, 0, 0,\n 0, 0, 0, 11, 0, 73, 74, 75, 84, 87,\n 10, 0, 0, 15\n};\n\n /* YYPGOTO[NTERM-NUM]. */\nstatic const yytype_int16 yypgoto[] =\n{\n -65, -65, -65, -65, -11, 348, -8, 1, 198, -65,\n 351, 0, 242\n};\n\n /* YYDEFGOTO[NTERM-NUM]. */\nstatic const yytype_int16 yydefgoto[] =\n{\n -1, 1, 2, 20, 162, 68, 40, 69, 23, 24,\n 41, 70, 163\n};\n\n /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If\n positive, shift that token. If negative, reduce the rule whose\n number is the opposite. If YYTABLE_NINF, syntax error. */\nstatic const yytype_int16 yytable[] =\n{\n 67, 43, 26, 22, 30, 29, 44, 4, 5, 73,\n 77, 155, 268, 72, 143, 144, 145, 146, 147, 148,\n 149, 31, 78, 5, 79, 74, 75, 32, 88, -108,\n 80, 90, 3, 81, 92, 93, 94, 95, 96, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 33, 236, 35, 237, 34, 113, 7, 151, -107, 36,\n 37, -107, 76, 14, 161, 38, 152, 35, 153, 167,\n 154, 39, 82, 83, 36, 37, 45, 156, 157, 269,\n 38, 84, 30, 169, 85, 86, 175, 176, 177, 178,\n 179, 180, 181, 182, 183, 184, 185, 186, 187, 188,\n 189, 87, 89, 192, 193, 194, 195, 196, 197, 198,\n 199, 200, 201, 202, 203, 204, 205, 206, 207, 208,\n 209, 210, 211, 212, 213, 214, 215, 216, 217, 218,\n 219, 220, 221, 222, 223, 224, 225, 226, 227, 264,\n 71, 237, 228, 17, 18, 19, 233, 91, 97, 114,\n 115, 116, 117, 238, 118, 119, 120, 121, 122, 123,\n 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\n 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,\n 144, 145, 146, 147, 148, 149, 114, 115, 116, 117,\n 98, 118, 119, 120, 121, 122, 123, 124, 125, 126,\n 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,\n 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,\n 147, 148, 149, 271, 99, 172, 273, 100, 101, 102,\n 103, 104, 105, 106, 107, 108, 109, 110, 277, 111,\n 278, 279, 112, 158, 159, 160, 165, 166, 234, 168,\n 170, 239, 280, 171, 229, 231, 232, 244, 282, 245,\n 246, 240, 173, 247, 265, 242, 243, 272, 266, 275,\n 276, 281, 267, 291, 284, 289, 114, 115, 116, 117,\n 292, 118, 119, 120, 121, 122, 123, 124, 125, 126,\n 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,\n 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,\n 147, 148, 149, 114, 115, 116, 117, 4, 118, 119,\n 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\n 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 21, 230, 174, 25, 190, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 7, 0, 0, 0,\n 0, 0, 0, 14, 27, 0, 0, 17, 18, 19,\n 0, 28, 0, 0, 0, 0, 262, 0, 263, 114,\n 115, 116, 117, 0, 118, 119, 120, 121, 122, 123,\n 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\n 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,\n 144, 145, 146, 147, 148, 149, 114, 115, 116, 117,\n 5, 118, 119, 120, 121, 122, 123, 124, 125, 126,\n 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,\n 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,\n 147, 148, 149, 0, 249, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 35, 0, 0, 0, 0, 0,\n 0, 36, 37, 0, 0, 0, 0, 38, 0, 0,\n 0, 0, 0, 42, 0, 0, 0, 114, 115, 116,\n 117, 251, 118, 119, 120, 121, 122, 123, 124, 125,\n 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,\n 136, 137, 138, 139, 140, 141, 142, 143, 144, 145,\n 146, 147, 148, 149, 114, 115, 116, 117, 4, 118,\n 119, 120, 121, 122, 123, 124, 125, 126, 127, 128,\n 129, 130, 131, 132, 133, 134, 135, 136, 137, 138,\n 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,\n 149, 0, 252, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 7, 0, 0,\n 0, 0, 0, 0, 14, 27, 0, 0, 17, 18,\n 19, 0, 0, 114, 115, 116, 117, 191, 118, 119,\n 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\n 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,\n 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,\n 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,\n 148, 149, 114, 115, 116, 117, 248, 118, 119, 120,\n 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,\n 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,\n 141, 142, 143, 144, 145, 146, 147, 148, 149, 119,\n 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\n 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 0, 114, 115, 116, 117, 250, 118, 119, 120, 121,\n 122, 123, 124, 125, 126, 127, 128, 129, 130, 131,\n 132, 133, 134, 135, 136, 137, 138, 139, 140, 141,\n 142, 143, 144, 145, 146, 147, 148, 149, 120, 121,\n 122, 123, 124, 125, 126, 127, 128, 129, 130, 131,\n 132, 133, 134, 135, 136, 137, 138, 139, 140, 141,\n 142, 143, 144, 145, 146, 147, 148, 149, 0, 0,\n 114, 115, 116, 117, 253, 118, 119, 120, 121, 122,\n 123, 124, 125, 126, 127, 128, 129, 130, 131, 132,\n 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,\n 143, 144, 145, 146, 147, 148, 149, 124, 125, 126,\n 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,\n 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,\n 147, 148, 149, 0, 0, 0, 0, 0, 0, 114,\n 115, 116, 117, 254, 118, 119, 120, 121, 122, 123,\n 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\n 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,\n 144, 145, 146, 147, 148, 149, -109, -109, -109, -109,\n -109, -109, -109, -109, -109, -109, -109, -109, 136, 137,\n 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,\n 148, 149, 0, 0, 0, 0, 0, 0, 114, 115,\n 116, 117, 255, 118, 119, 120, 121, 122, 123, 124,\n 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,\n 135, 136, 137, 138, 139, 140, 141, 142, 143, 144,\n 145, 146, 147, 148, 149, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 114, 115, 116,\n 117, 256, 118, 119, 120, 121, 122, 123, 124, 125,\n 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,\n 136, 137, 138, 139, 140, 141, 142, 143, 144, 145,\n 146, 147, 148, 149, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 114, 115, 116, 117,\n 257, 118, 119, 120, 121, 122, 123, 124, 125, 126,\n 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,\n 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,\n 147, 148, 149, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 114, 115, 116, 117, 258,\n 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,\n 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,\n 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,\n 148, 149, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 114, 115, 116, 117, 259, 118,\n 119, 120, 121, 122, 123, 124, 125, 126, 127, 128,\n 129, 130, 131, 132, 133, 134, 135, 136, 137, 138,\n 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,\n 149, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 114, 115, 116, 117, 260, 118, 119,\n 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\n 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 114, 115, 116, 117, 261, 118, 119, 120,\n 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,\n 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,\n 141, 142, 143, 144, 145, 146, 147, 148, 149, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 114, 115, 116, 117, 285, 118, 119, 120, 121,\n 122, 123, 124, 125, 126, 127, 128, 129, 130, 131,\n 132, 133, 134, 135, 136, 137, 138, 139, 140, 141,\n 142, 143, 144, 145, 146, 147, 148, 149, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 114, 115, 116, 117, 286, 118, 119, 120, 121, 122,\n 123, 124, 125, 126, 127, 128, 129, 130, 131, 132,\n 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,\n 143, 144, 145, 146, 147, 148, 149, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 114,\n 115, 116, 117, 287, 118, 119, 120, 121, 122, 123,\n 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\n 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,\n 144, 145, 146, 147, 148, 149, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 114, 115,\n 116, 117, 288, 118, 119, 120, 121, 122, 123, 124,\n 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,\n 135, 136, 137, 138, 139, 140, 141, 142, 143, 144,\n 145, 146, 147, 148, 149, 0, 0, 0, 0, 4,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 46, 0, 47, 6, 0, 0, 0, 0, 0, 164,\n 48, 49, 50, 51, 0, 52, 53, 54, 55, 56,\n 57, 58, 59, 60, 61, 62, 63, 64, 7, 4,\n 0, 0, 0, 0, 5, 14, 27, 0, 65, 17,\n 18, 19, 0, 0, 0, 66, 0, 0, 0, 0,\n 0, 0, 0, 6, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 7, 8,\n 9, 10, 11, 12, 13, 14, 15, 0, 16, 17,\n 18, 19, 114, 115, 116, 117, 0, 118, 119, 120,\n 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,\n 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,\n 141, 142, 143, 144, 145, 146, 147, 148, 149, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 150, 114,\n 115, 116, 117, 235, 118, 119, 120, 121, 122, 123,\n 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\n 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,\n 144, 145, 146, 147, 148, 149, 114, 115, 116, 117,\n 241, 118, 119, 120, 121, 122, 123, 124, 125, 126,\n 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,\n 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,\n 147, 148, 149, 114, 115, 116, 117, 270, 118, 119,\n 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\n 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\n 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\n 114, 115, 116, 117, 274, 118, 119, 120, 121, 122,\n 123, 124, 125, 126, 127, 128, 129, 130, 131, 132,\n 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,\n 143, 144, 145, 146, 147, 148, 149, 114, 115, 116,\n 117, 283, 118, 119, 120, 121, 122, 123, 124, 125,\n 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,\n 136, 137, 138, 139, 140, 141, 142, 143, 144, 145,\n 146, 147, 148, 149, 114, 115, 116, 117, 290, 118,\n 119, 120, 121, 122, 123, 124, 125, 126, 127, 128,\n 129, 130, 131, 132, 133, 134, 135, 136, 137, 138,\n 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,\n 149, 114, 115, 116, 117, 293, 118, 119, 120, 121,\n 122, 123, 124, 125, 126, 127, 128, 129, 130, 131,\n 132, 133, 134, 135, 136, 137, 138, 139, 140, 141,\n 142, 143, 144, 145, 146, 147, 148, 149, 114, 115,\n 116, 117, 0, 118, 119, 120, 121, 122, 123, 124,\n 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,\n 135, 136, 137, 138, 139, 140, 141, 142, 143, 144,\n 145, 146, 147, 148, 149, 115, 116, 117, 0, 118,\n 119, 120, 121, 122, 123, 124, 125, 126, 127, 128,\n 129, 130, 131, 132, 133, 134, 135, 136, 137, 138,\n 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,\n 149, 117, 0, 118, 119, 120, 121, 122, 123, 124,\n 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,\n 135, 136, 137, 138, 139, 140, 141, 142, 143, 144,\n 145, 146, 147, 148, 149\n};\n\nstatic const yytype_int16 yycheck[] =\n{\n 11, 9, 2, 2, 4, 4, 7, 9, 14, 73,\n 21, 7, 7, 13, 33, 34, 35, 36, 37, 38,\n 39, 66, 73, 14, 75, 73, 74, 72, 39, 77,\n 74, 42, 0, 77, 45, 46, 47, 48, 49, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 73, 76, 58, 78, 77, 66, 58, 68, 74, 65,\n 66, 77, 75, 65, 75, 71, 73, 58, 75, 80,\n 77, 77, 65, 15, 65, 66, 77, 73, 74, 74,\n 71, 15, 82, 82, 65, 67, 97, 98, 99, 100,\n 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,\n 111, 77, 7, 114, 115, 116, 117, 118, 119, 120,\n 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,\n 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,\n 141, 142, 143, 144, 145, 146, 147, 148, 149, 76,\n 66, 78, 150, 69, 70, 71, 157, 7, 75, 3,\n 4, 5, 6, 164, 8, 9, 10, 11, 12, 13,\n 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,\n 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\n 34, 35, 36, 37, 38, 39, 3, 4, 5, 6,\n 75, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, 234, 75, 79, 237, 75, 75, 75,\n 75, 75, 75, 75, 75, 75, 75, 75, 249, 75,\n 251, 252, 75, 74, 65, 65, 65, 65, 74, 65,\n 79, 74, 263, 67, 65, 65, 65, 79, 269, 7,\n 7, 76, 79, 7, 7, 78, 73, 7, 76, 65,\n 65, 65, 78, 74, 79, 79, 3, 4, 5, 6,\n 291, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, 3, 4, 5, 6, 9, 8, 9,\n 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 2, 153, 79, 2, 112, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, 58, -1, -1, -1,\n -1, -1, -1, 65, 66, -1, -1, 69, 70, 71,\n -1, 73, -1, -1, -1, -1, 76, -1, 78, 3,\n 4, 5, 6, -1, 8, 9, 10, 11, 12, 13,\n 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,\n 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\n 34, 35, 36, 37, 38, 39, 3, 4, 5, 6,\n 14, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, -1, 78, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, 58, -1, -1, -1, -1, -1,\n -1, 65, 66, -1, -1, -1, -1, 71, -1, -1,\n -1, -1, -1, 77, -1, -1, -1, 3, 4, 5,\n 6, 78, 8, 9, 10, 11, 12, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 3, 4, 5, 6, 9, 8,\n 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,\n 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\n 39, -1, 78, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, 58, -1, -1,\n -1, -1, -1, -1, 65, 66, -1, -1, 69, 70,\n 71, -1, -1, 3, 4, 5, 6, 76, 8, 9,\n 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\n 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\n 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,\n 38, 39, 3, 4, 5, 6, 76, 8, 9, 10,\n 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,\n 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,\n 31, 32, 33, 34, 35, 36, 37, 38, 39, 9,\n 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n -1, 3, 4, 5, 6, 76, 8, 9, 10, 11,\n 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 10, 11,\n 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, -1, -1,\n 3, 4, 5, 6, 76, 8, 9, 10, 11, 12,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,\n 33, 34, 35, 36, 37, 38, 39, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, -1, -1, -1, -1, -1, -1, 3,\n 4, 5, 6, 76, 8, 9, 10, 11, 12, 13,\n 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,\n 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\n 34, 35, 36, 37, 38, 39, 14, 15, 16, 17,\n 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\n 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,\n 38, 39, -1, -1, -1, -1, -1, -1, 3, 4,\n 5, 6, 76, 8, 9, 10, 11, 12, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, 3, 4, 5,\n 6, 76, 8, 9, 10, 11, 12, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, 3, 4, 5, 6,\n 76, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, 3, 4, 5, 6, 76,\n 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\n 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\n 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,\n 38, 39, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, 3, 4, 5, 6, 76, 8,\n 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,\n 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\n 39, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, 3, 4, 5, 6, 76, 8, 9,\n 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, 3, 4, 5, 6, 76, 8, 9, 10,\n 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,\n 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,\n 31, 32, 33, 34, 35, 36, 37, 38, 39, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, 3, 4, 5, 6, 76, 8, 9, 10, 11,\n 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n 3, 4, 5, 6, 76, 8, 9, 10, 11, 12,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,\n 33, 34, 35, 36, 37, 38, 39, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, 3,\n 4, 5, 6, 76, 8, 9, 10, 11, 12, 13,\n 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,\n 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\n 34, 35, 36, 37, 38, 39, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, 3, 4,\n 5, 6, 76, 8, 9, 10, 11, 12, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, -1, -1, -1, -1, 9,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n 30, -1, 32, 33, -1, -1, -1, -1, -1, 74,\n 40, 41, 42, 43, -1, 45, 46, 47, 48, 49,\n 50, 51, 52, 53, 54, 55, 56, 57, 58, 9,\n -1, -1, -1, -1, 14, 65, 66, -1, 68, 69,\n 70, 71, -1, -1, -1, 75, -1, -1, -1, -1,\n -1, -1, -1, 33, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, 58, 59,\n 60, 61, 62, 63, 64, 65, 66, -1, 68, 69,\n 70, 71, 3, 4, 5, 6, -1, 8, 9, 10,\n 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,\n 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,\n 31, 32, 33, 34, 35, 36, 37, 38, 39, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, 59, 3,\n 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,\n 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,\n 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\n 34, 35, 36, 37, 38, 39, 3, 4, 5, 6,\n 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, 3, 4, 5, 6, 7, 8, 9,\n 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,\n 33, 34, 35, 36, 37, 38, 39, 3, 4, 5,\n 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 3, 4, 5, 6, 7, 8,\n 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,\n 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\n 39, 3, 4, 5, 6, 7, 8, 9, 10, 11,\n 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 3, 4,\n 5, 6, -1, 8, 9, 10, 11, 12, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, 4, 5, 6, -1, 8,\n 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,\n 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\n 39, 6, -1, 8, 9, 10, 11, 12, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39\n};\n\n /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing\n symbol of state STATE-NUM. */\nstatic const yytype_int8 yystos[] =\n{\n 0, 81, 82, 0, 9, 14, 33, 58, 59, 60,\n 61, 62, 63, 64, 65, 66, 68, 69, 70, 71,\n 83, 85, 87, 88, 89, 90, 91, 66, 73, 87,\n 91, 66, 72, 73, 77, 58, 65, 66, 71, 77,\n 86, 90, 77, 86, 7, 77, 30, 32, 40, 41,\n 42, 43, 45, 46, 47, 48, 49, 50, 51, 52,\n 53, 54, 55, 56, 57, 68, 75, 84, 85, 87,\n 91, 66, 91, 73, 73, 74, 75, 84, 73, 75,\n 74, 77, 65, 15, 15, 65, 67, 77, 84, 7,\n 84, 7, 84, 84, 84, 84, 84, 75, 75, 75,\n 75, 75, 75, 75, 75, 75, 75, 75, 75, 75,\n 75, 75, 75, 84, 3, 4, 5, 6, 8, 9,\n 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 59, 84, 73, 75, 77, 7, 73, 74, 74, 65,\n 65, 84, 84, 92, 74, 65, 65, 84, 65, 87,\n 79, 67, 79, 79, 79, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 92, 76, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 86, 65,\n 88, 65, 65, 84, 74, 7, 76, 78, 84, 74,\n 76, 7, 78, 73, 79, 7, 7, 7, 76, 78,\n 76, 78, 78, 76, 76, 76, 76, 76, 76, 76,\n 76, 76, 76, 78, 76, 7, 76, 78, 7, 74,\n 7, 84, 7, 84, 7, 65, 65, 84, 84, 84,\n 84, 65, 84, 7, 79, 76, 76, 76, 76, 79,\n 7, 74, 84, 7\n};\n\n /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */\nstatic const yytype_int8 yyr1[] =\n{\n 0, 80, 81, 82, 82, 82, 82, 83, 83, 83,\n 83, 83, 83, 83, 83, 83, 83, 83, 83, 83,\n 83, 83, 83, 83, 83, 83, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,\n 84, 84, 84, 84, 84, 84, 84, 84, 84, 85,\n 85, 85, 85, 86, 86, 86, 86, 86, 86, 87,\n 87, 87, 88, 88, 88, 88, 88, 89, 89, 90,\n 90, 91, 91, 91, 92, 92, 92\n};\n\n /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */\nstatic const yytype_int8 yyr2[] =\n{\n 0, 2, 2, 0, 2, 4, 6, 4, 5, 4,\n 7, 6, 3, 5, 5, 9, 4, 4, 3, 5,\n 5, 3, 5, 2, 5, 1, 1, 2, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 2, 2, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 2, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 2, 4,\n 4, 4, 4, 6, 6, 6, 4, 4, 4, 4,\n 4, 4, 4, 4, 6, 4, 3, 6, 4, 6,\n 4, 3, 1, 1, 1, 1, 4, 1, 1, 1,\n 1, 1, 1, 1, 3, 2, 4, 1, 1, 3,\n 3, 1, 1, 1, 0, 1, 3\n};\n\n\n#define yyerrok (yyerrstatus = 0)\n#define yyclearin (yychar = YYEMPTY)\n#define YYEMPTY (-2)\n#define YYEOF 0\n\n#define YYACCEPT goto yyacceptlab\n#define YYABORT goto yyabortlab\n#define YYERROR goto yyerrorlab\n\n\n#define YYRECOVERING() (!!yyerrstatus)\n\n#define YYBACKUP(Token, Value) \\\n do \\\n if (yychar == YYEMPTY) \\\n { \\\n yychar = (Token); \\\n yylval = (Value); \\\n YYPOPSTACK (yylen); \\\n yystate = *yyssp; \\\n goto yybackup; \\\n } \\\n else \\\n { \\\n yyerror (YY_(\"syntax error: cannot back up\")); \\\n YYERROR; \\\n } \\\n while (0)\n\n/* Error token number */\n#define YYTERROR 1\n#define YYERRCODE 256\n\n\n\n/* Enable debugging if requested. */\n#if PCODEDEBUG\n\n# ifndef YYFPRINTF\n# include /* INFRINGES ON USER NAME SPACE */\n# define YYFPRINTF fprintf\n# endif\n\n# define YYDPRINTF(Args) \\\ndo { \\\n if (yydebug) \\\n YYFPRINTF Args; \\\n} while (0)\n\n/* This macro is provided for backward compatibility. */\n#ifndef YY_LOCATION_PRINT\n# define YY_LOCATION_PRINT(File, Loc) ((void) 0)\n#endif\n\n\n# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \\\ndo { \\\n if (yydebug) \\\n { \\\n YYFPRINTF (stderr, \"%s \", Title); \\\n yy_symbol_print (stderr, \\\n Type, Value); \\\n YYFPRINTF (stderr, \"\\n\"); \\\n } \\\n} while (0)\n\n\n/*-----------------------------------.\n| Print this symbol's value on YYO. |\n`-----------------------------------*/\n\nstatic void\nyy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep)\n{\n FILE *yyoutput = yyo;\n YYUSE (yyoutput);\n if (!yyvaluep)\n return;\n# ifdef YYPRINT\n if (yytype < YYNTOKENS)\n YYPRINT (yyo, yytoknum[yytype], *yyvaluep);\n# endif\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n YYUSE (yytype);\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n/*---------------------------.\n| Print this symbol on YYO. |\n`---------------------------*/\n\nstatic void\nyy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep)\n{\n YYFPRINTF (yyo, \"%s %s (\",\n yytype < YYNTOKENS ? \"token\" : \"nterm\", yytname[yytype]);\n\n yy_symbol_value_print (yyo, yytype, yyvaluep);\n YYFPRINTF (yyo, \")\");\n}\n\n/*------------------------------------------------------------------.\n| yy_stack_print -- Print the state stack from its BOTTOM up to its |\n| TOP (included). |\n`------------------------------------------------------------------*/\n\nstatic void\nyy_stack_print (yy_state_t *yybottom, yy_state_t *yytop)\n{\n YYFPRINTF (stderr, \"Stack now\");\n for (; yybottom <= yytop; yybottom++)\n {\n int yybot = *yybottom;\n YYFPRINTF (stderr, \" %d\", yybot);\n }\n YYFPRINTF (stderr, \"\\n\");\n}\n\n# define YY_STACK_PRINT(Bottom, Top) \\\ndo { \\\n if (yydebug) \\\n yy_stack_print ((Bottom), (Top)); \\\n} while (0)\n\n\n/*------------------------------------------------.\n| Report that the YYRULE is going to be reduced. |\n`------------------------------------------------*/\n\nstatic void\nyy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule)\n{\n int yylno = yyrline[yyrule];\n int yynrhs = yyr2[yyrule];\n int yyi;\n YYFPRINTF (stderr, \"Reducing stack by rule %d (line %d):\\n\",\n yyrule - 1, yylno);\n /* The symbols being reduced. */\n for (yyi = 0; yyi < yynrhs; yyi++)\n {\n YYFPRINTF (stderr, \" $%d = \", yyi + 1);\n yy_symbol_print (stderr,\n yystos[+yyssp[yyi + 1 - yynrhs]],\n &yyvsp[(yyi + 1) - (yynrhs)]\n );\n YYFPRINTF (stderr, \"\\n\");\n }\n}\n\n# define YY_REDUCE_PRINT(Rule) \\\ndo { \\\n if (yydebug) \\\n yy_reduce_print (yyssp, yyvsp, Rule); \\\n} while (0)\n\n/* Nonzero means print parse trace. It is left uninitialized so that\n multiple parsers can coexist. */\nint yydebug;\n#else /* !PCODEDEBUG */\n# define YYDPRINTF(Args)\n# define YY_SYMBOL_PRINT(Title, Type, Value, Location)\n# define YY_STACK_PRINT(Bottom, Top)\n# define YY_REDUCE_PRINT(Rule)\n#endif /* !PCODEDEBUG */\n\n\n/* YYINITDEPTH -- initial size of the parser's stacks. */\n#ifndef YYINITDEPTH\n# define YYINITDEPTH 200\n#endif\n\n/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only\n if the built-in stack extension method is used).\n\n Do not make this value too large; the results are undefined if\n YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)\n evaluated with infinite-precision integer arithmetic. */\n\n#ifndef YYMAXDEPTH\n# define YYMAXDEPTH 10000\n#endif\n\n\n#if YYERROR_VERBOSE\n\n# ifndef yystrlen\n# if defined __GLIBC__ && defined _STRING_H\n# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S)))\n# else\n/* Return the length of YYSTR. */\nstatic YYPTRDIFF_T\nyystrlen (const char *yystr)\n{\n YYPTRDIFF_T yylen;\n for (yylen = 0; yystr[yylen]; yylen++)\n continue;\n return yylen;\n}\n# endif\n# endif\n\n# ifndef yystpcpy\n# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE\n# define yystpcpy stpcpy\n# else\n/* Copy YYSRC to YYDEST, returning the address of the terminating '\\0' in\n YYDEST. */\nstatic char *\nyystpcpy (char *yydest, const char *yysrc)\n{\n char *yyd = yydest;\n const char *yys = yysrc;\n\n while ((*yyd++ = *yys++) != '\\0')\n continue;\n\n return yyd - 1;\n}\n# endif\n# endif\n\n# ifndef yytnamerr\n/* Copy to YYRES the contents of YYSTR after stripping away unnecessary\n quotes and backslashes, so that it's suitable for yyerror. The\n heuristic is that double-quoting is unnecessary unless the string\n contains an apostrophe, a comma, or backslash (other than\n backslash-backslash). YYSTR is taken from yytname. If YYRES is\n null, do not copy; instead, return the length of what the result\n would have been. */\nstatic YYPTRDIFF_T\nyytnamerr (char *yyres, const char *yystr)\n{\n if (*yystr == '\"')\n {\n YYPTRDIFF_T yyn = 0;\n char const *yyp = yystr;\n\n for (;;)\n switch (*++yyp)\n {\n case '\\'':\n case ',':\n goto do_not_strip_quotes;\n\n case '\\\\':\n if (*++yyp != '\\\\')\n goto do_not_strip_quotes;\n else\n goto append;\n\n append:\n default:\n if (yyres)\n yyres[yyn] = *yyp;\n yyn++;\n break;\n\n case '\"':\n if (yyres)\n yyres[yyn] = '\\0';\n return yyn;\n }\n do_not_strip_quotes: ;\n }\n\n if (yyres)\n return yystpcpy (yyres, yystr) - yyres;\n else\n return yystrlen (yystr);\n}\n# endif\n\n/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message\n about the unexpected token YYTOKEN for the state stack whose top is\n YYSSP.\n\n Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is\n not large enough to hold the message. In that case, also set\n *YYMSG_ALLOC to the required number of bytes. Return 2 if the\n required number of bytes is too large to store. */\nstatic int\nyysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg,\n yy_state_t *yyssp, int yytoken)\n{\n enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };\n /* Internationalized format string. */\n const char *yyformat = YY_NULLPTR;\n /* Arguments of yyformat: reported tokens (one for the \"unexpected\",\n one per \"expected\"). */\n char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];\n /* Actual size of YYARG. */\n int yycount = 0;\n /* Cumulated lengths of YYARG. */\n YYPTRDIFF_T yysize = 0;\n\n /* There are many possibilities here to consider:\n - If this state is a consistent state with a default action, then\n the only way this function was invoked is if the default action\n is an error action. In that case, don't check for expected\n tokens because there are none.\n - The only way there can be no lookahead present (in yychar) is if\n this state is a consistent state with a default action. Thus,\n detecting the absence of a lookahead is sufficient to determine\n that there is no unexpected or expected token to report. In that\n case, just report a simple \"syntax error\".\n - Don't assume there isn't a lookahead just because this state is a\n consistent state with a default action. There might have been a\n previous inconsistent state, consistent state with a non-default\n action, or user semantic action that manipulated yychar.\n - Of course, the expected token list depends on states to have\n correct lookahead information, and it depends on the parser not\n to perform extra reductions after fetching a lookahead from the\n scanner and before detecting a syntax error. Thus, state merging\n (from LALR or IELR) and default reductions corrupt the expected\n token list. However, the list is correct for canonical LR with\n one exception: it will still contain any token that will not be\n accepted due to an error action in a later state.\n */\n if (yytoken != YYEMPTY)\n {\n int yyn = yypact[+*yyssp];\n YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);\n yysize = yysize0;\n yyarg[yycount++] = yytname[yytoken];\n if (!yypact_value_is_default (yyn))\n {\n /* Start YYX at -YYN if negative to avoid negative indexes in\n YYCHECK. In other words, skip the first -YYN actions for\n this state because they are default actions. */\n int yyxbegin = yyn < 0 ? -yyn : 0;\n /* Stay within bounds of both yycheck and yytname. */\n int yychecklim = YYLAST - yyn + 1;\n int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;\n int yyx;\n\n for (yyx = yyxbegin; yyx < yyxend; ++yyx)\n if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR\n && !yytable_value_is_error (yytable[yyx + yyn]))\n {\n if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)\n {\n yycount = 1;\n yysize = yysize0;\n break;\n }\n yyarg[yycount++] = yytname[yyx];\n {\n YYPTRDIFF_T yysize1\n = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);\n if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)\n yysize = yysize1;\n else\n return 2;\n }\n }\n }\n }\n\n switch (yycount)\n {\n# define YYCASE_(N, S) \\\n case N: \\\n yyformat = S; \\\n break\n default: /* Avoid compiler warnings. */\n YYCASE_(0, YY_(\"syntax error\"));\n YYCASE_(1, YY_(\"syntax error, unexpected %s\"));\n YYCASE_(2, YY_(\"syntax error, unexpected %s, expecting %s\"));\n YYCASE_(3, YY_(\"syntax error, unexpected %s, expecting %s or %s\"));\n YYCASE_(4, YY_(\"syntax error, unexpected %s, expecting %s or %s or %s\"));\n YYCASE_(5, YY_(\"syntax error, unexpected %s, expecting %s or %s or %s or %s\"));\n# undef YYCASE_\n }\n\n {\n /* Don't count the \"%s\"s in the final size, but reserve room for\n the terminator. */\n YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1;\n if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)\n yysize = yysize1;\n else\n return 2;\n }\n\n if (*yymsg_alloc < yysize)\n {\n *yymsg_alloc = 2 * yysize;\n if (! (yysize <= *yymsg_alloc\n && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))\n *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;\n return 1;\n }\n\n /* Avoid sprintf, as that infringes on the user's name space.\n Don't have undefined behavior even if the translation\n produced a string with the wrong number of \"%s\"s. */\n {\n char *yyp = *yymsg;\n int yyi = 0;\n while ((*yyp = *yyformat) != '\\0')\n if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)\n {\n yyp += yytnamerr (yyp, yyarg[yyi++]);\n yyformat += 2;\n }\n else\n {\n ++yyp;\n ++yyformat;\n }\n }\n return 0;\n}\n#endif /* YYERROR_VERBOSE */\n\n/*-----------------------------------------------.\n| Release the memory associated to this symbol. |\n`-----------------------------------------------*/\n\nstatic void\nyydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)\n{\n YYUSE (yyvaluep);\n if (!yymsg)\n yymsg = \"Deleting\";\n YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);\n\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n switch (yytype)\n {\n case 65: /* INTEGER */\n { delete ((*yyvaluep).i); }\n break;\n\n case 66: /* STRING */\n { delete ((*yyvaluep).str); }\n break;\n\n case 82: /* rtlmid */\n { delete ((*yyvaluep).sem); }\n break;\n\n case 83: /* statement */\n { if (((*yyvaluep).stmt) != (vector *)0) { for(int4 i=0;i<((*yyvaluep).stmt)->size();++i) delete (*((*yyvaluep).stmt))[i]; delete ((*yyvaluep).stmt);} }\n break;\n\n case 84: /* expr */\n { delete ((*yyvaluep).tree); }\n break;\n\n case 85: /* sizedstar */\n { delete ((*yyvaluep).starqual); }\n break;\n\n case 86: /* jumpdest */\n { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); }\n break;\n\n case 87: /* varnode */\n { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); }\n break;\n\n case 88: /* integervarnode */\n { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); }\n break;\n\n case 89: /* lhsvarnode */\n { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); }\n break;\n\n case 92: /* paramlist */\n { for(int4 i=0;i<((*yyvaluep).param)->size();++i) delete (*((*yyvaluep).param))[i]; delete ((*yyvaluep).param); }\n break;\n\n default:\n break;\n }\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n\n\n/* The lookahead symbol. */\nint yychar;\n\n/* The semantic value of the lookahead symbol. */\nYYSTYPE yylval;\n/* Number of syntax errors so far. */\nint yynerrs;\n\n\n/*----------.\n| yyparse. |\n`----------*/\n\nint\nyyparse (void)\n{\n yy_state_fast_t yystate;\n /* Number of tokens to shift before error messages enabled. */\n int yyerrstatus;\n\n /* The stacks and their tools:\n 'yyss': related to states.\n 'yyvs': related to semantic values.\n\n Refer to the stacks through separate pointers, to allow yyoverflow\n to reallocate them elsewhere. */\n\n /* The state stack. */\n yy_state_t yyssa[YYINITDEPTH];\n yy_state_t *yyss;\n yy_state_t *yyssp;\n\n /* The semantic value stack. */\n YYSTYPE yyvsa[YYINITDEPTH];\n YYSTYPE *yyvs;\n YYSTYPE *yyvsp;\n\n YYPTRDIFF_T yystacksize;\n\n int yyn;\n int yyresult;\n /* Lookahead token as an internal (translated) token number. */\n int yytoken = 0;\n /* The variables used to return semantic value and location from the\n action routines. */\n YYSTYPE yyval;\n\n#if YYERROR_VERBOSE\n /* Buffer for error messages, and its allocated size. */\n char yymsgbuf[128];\n char *yymsg = yymsgbuf;\n YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf;\n#endif\n\n#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))\n\n /* The number of symbols on the RHS of the reduced rule.\n Keep to zero when no symbol should be popped. */\n int yylen = 0;\n\n yyssp = yyss = yyssa;\n yyvsp = yyvs = yyvsa;\n yystacksize = YYINITDEPTH;\n\n YYDPRINTF ((stderr, \"Starting parse\\n\"));\n\n yystate = 0;\n yyerrstatus = 0;\n yynerrs = 0;\n yychar = YYEMPTY; /* Cause a token to be read. */\n goto yysetstate;\n\n\n/*------------------------------------------------------------.\n| yynewstate -- push a new state, which is found in yystate. |\n`------------------------------------------------------------*/\nyynewstate:\n /* In all cases, when you get here, the value and location stacks\n have just been pushed. So pushing a state here evens the stacks. */\n yyssp++;\n\n\n/*--------------------------------------------------------------------.\n| yysetstate -- set current state (the top of the stack) to yystate. |\n`--------------------------------------------------------------------*/\nyysetstate:\n YYDPRINTF ((stderr, \"Entering state %d\\n\", yystate));\n YY_ASSERT (0 <= yystate && yystate < YYNSTATES);\n YY_IGNORE_USELESS_CAST_BEGIN\n *yyssp = YY_CAST (yy_state_t, yystate);\n YY_IGNORE_USELESS_CAST_END\n\n if (yyss + yystacksize - 1 <= yyssp)\n#if !defined yyoverflow && !defined YYSTACK_RELOCATE\n goto yyexhaustedlab;\n#else\n {\n /* Get the current used size of the three stacks, in elements. */\n YYPTRDIFF_T yysize = yyssp - yyss + 1;\n\n# if defined yyoverflow\n {\n /* Give user a chance to reallocate the stack. Use copies of\n these so that the &'s don't force the real ones into\n memory. */\n yy_state_t *yyss1 = yyss;\n YYSTYPE *yyvs1 = yyvs;\n\n /* Each stack pointer address is followed by the size of the\n data in use in that stack, in bytes. This used to be a\n conditional around just the two extra args, but that might\n be undefined if yyoverflow is a macro. */\n yyoverflow (YY_(\"memory exhausted\"),\n &yyss1, yysize * YYSIZEOF (*yyssp),\n &yyvs1, yysize * YYSIZEOF (*yyvsp),\n &yystacksize);\n yyss = yyss1;\n yyvs = yyvs1;\n }\n# else /* defined YYSTACK_RELOCATE */\n /* Extend the stack our own way. */\n if (YYMAXDEPTH <= yystacksize)\n goto yyexhaustedlab;\n yystacksize *= 2;\n if (YYMAXDEPTH < yystacksize)\n yystacksize = YYMAXDEPTH;\n\n {\n yy_state_t *yyss1 = yyss;\n union yyalloc *yyptr =\n YY_CAST (union yyalloc *,\n YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize))));\n if (! yyptr)\n goto yyexhaustedlab;\n YYSTACK_RELOCATE (yyss_alloc, yyss);\n YYSTACK_RELOCATE (yyvs_alloc, yyvs);\n# undef YYSTACK_RELOCATE\n if (yyss1 != yyssa)\n YYSTACK_FREE (yyss1);\n }\n# endif\n\n yyssp = yyss + yysize - 1;\n yyvsp = yyvs + yysize - 1;\n\n YY_IGNORE_USELESS_CAST_BEGIN\n YYDPRINTF ((stderr, \"Stack size increased to %ld\\n\",\n YY_CAST (long, yystacksize)));\n YY_IGNORE_USELESS_CAST_END\n\n if (yyss + yystacksize - 1 <= yyssp)\n YYABORT;\n }\n#endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */\n\n if (yystate == YYFINAL)\n YYACCEPT;\n\n goto yybackup;\n\n\n/*-----------.\n| yybackup. |\n`-----------*/\nyybackup:\n /* Do appropriate processing given the current state. Read a\n lookahead token if we need one and don't already have one. */\n\n /* First try to decide what to do without reference to lookahead token. */\n yyn = yypact[yystate];\n if (yypact_value_is_default (yyn))\n goto yydefault;\n\n /* Not known => get a lookahead token if don't already have one. */\n\n /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */\n if (yychar == YYEMPTY)\n {\n YYDPRINTF ((stderr, \"Reading a token: \"));\n yychar = yylex ();\n }\n\n if (yychar <= YYEOF)\n {\n yychar = yytoken = YYEOF;\n YYDPRINTF ((stderr, \"Now at end of input.\\n\"));\n }\n else\n {\n yytoken = YYTRANSLATE (yychar);\n YY_SYMBOL_PRINT (\"Next token is\", yytoken, &yylval, &yylloc);\n }\n\n /* If the proper action on seeing token YYTOKEN is to reduce or to\n detect an error, take that action. */\n yyn += yytoken;\n if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)\n goto yydefault;\n yyn = yytable[yyn];\n if (yyn <= 0)\n {\n if (yytable_value_is_error (yyn))\n goto yyerrlab;\n yyn = -yyn;\n goto yyreduce;\n }\n\n /* Count tokens shifted since error; after three, turn off error\n status. */\n if (yyerrstatus)\n yyerrstatus--;\n\n /* Shift the lookahead token. */\n YY_SYMBOL_PRINT (\"Shifting\", yytoken, &yylval, &yylloc);\n yystate = yyn;\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n *++yyvsp = yylval;\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n /* Discard the shifted token. */\n yychar = YYEMPTY;\n goto yynewstate;\n\n\n/*-----------------------------------------------------------.\n| yydefault -- do the default action for the current state. |\n`-----------------------------------------------------------*/\nyydefault:\n yyn = yydefact[yystate];\n if (yyn == 0)\n goto yyerrlab;\n goto yyreduce;\n\n\n/*-----------------------------.\n| yyreduce -- do a reduction. |\n`-----------------------------*/\nyyreduce:\n /* yyn is the number of a rule to reduce with. */\n yylen = yyr2[yyn];\n\n /* If YYLEN is nonzero, implement the default value of the action:\n '$$ = $1'.\n\n Otherwise, the following line sets YYVAL to garbage.\n This behavior is undocumented and Bison\n users should not rely upon it. Assigning to YYVAL\n unconditionally makes the parser a bit smaller, and it avoids a\n GCC warning that YYVAL may be used uninitialized. */\n yyval = yyvsp[1-yylen];\n\n\n YY_REDUCE_PRINT (yyn);\n switch (yyn)\n {\n case 2:\n { pcode->setResult((yyvsp[-1].sem)); }\n break;\n\n case 3:\n { (yyval.sem) = new ConstructTpl(); }\n break;\n\n case 4:\n { (yyval.sem) = (yyvsp[-1].sem); if (!(yyval.sem)->addOpList(*(yyvsp[0].stmt))) { delete (yyvsp[0].stmt); yyerror(\"Multiple delayslot declarations\"); YYERROR; } delete (yyvsp[0].stmt); }\n break;\n\n case 5:\n { (yyval.sem) = (yyvsp[-3].sem); pcode->newLocalDefinition((yyvsp[-1].str)); }\n break;\n\n case 6:\n { (yyval.sem) = (yyvsp[-5].sem); pcode->newLocalDefinition((yyvsp[-3].str),*(yyvsp[-1].i)); delete (yyvsp[-1].i); }\n break;\n\n case 7:\n { (yyvsp[-1].tree)->setOutput((yyvsp[-3].varnode)); (yyval.stmt) = ExprTree::toVector((yyvsp[-1].tree)); }\n break;\n\n case 8:\n { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-3].str)); }\n break;\n\n case 9:\n { (yyval.stmt) = pcode->newOutput(false,(yyvsp[-1].tree),(yyvsp[-3].str)); }\n break;\n\n case 10:\n { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); }\n break;\n\n case 11:\n { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); }\n break;\n\n case 12:\n { (yyval.stmt) = (vector *)0; string errmsg = \"Redefinition of symbol: \"+(yyvsp[-1].specsym)->getName(); yyerror(errmsg.c_str()); YYERROR; }\n break;\n\n case 13:\n { (yyval.stmt) = pcode->createStore((yyvsp[-4].starqual),(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 14:\n { (yyval.stmt) = pcode->createUserOpNoOut((yyvsp[-4].useropsym),(yyvsp[-2].param)); }\n break;\n\n case 15:\n { (yyval.stmt) = pcode->assignBitRange((yyvsp[-8].varnode),(uint4)*(yyvsp[-6].i),(uint4)*(yyvsp[-4].i),(yyvsp[-1].tree)); delete (yyvsp[-6].i), delete (yyvsp[-4].i); }\n break;\n\n case 16:\n { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); yyerror(\"Illegal truncation on left-hand side of assignment\"); YYERROR; }\n break;\n\n case 17:\n { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); yyerror(\"Illegal subpiece on left-hand side of assignment\"); YYERROR; }\n break;\n\n case 18:\n { (yyval.stmt) = pcode->createOpNoOut(CPUI_BRANCH,new ExprTree((yyvsp[-1].varnode))); }\n break;\n\n case 19:\n { (yyval.stmt) = pcode->createOpNoOut(CPUI_CBRANCH,new ExprTree((yyvsp[-1].varnode)),(yyvsp[-3].tree)); }\n break;\n\n case 20:\n { (yyval.stmt) = pcode->createOpNoOut(CPUI_BRANCHIND,(yyvsp[-2].tree)); }\n break;\n\n case 21:\n { (yyval.stmt) = pcode->createOpNoOut(CPUI_CALL,new ExprTree((yyvsp[-1].varnode))); }\n break;\n\n case 22:\n { (yyval.stmt) = pcode->createOpNoOut(CPUI_CALLIND,(yyvsp[-2].tree)); }\n break;\n\n case 23:\n { (yyval.stmt) = (vector *)0; yyerror(\"Must specify an indirect parameter for return\"); YYERROR; }\n break;\n\n case 24:\n { (yyval.stmt) = pcode->createOpNoOut(CPUI_RETURN,(yyvsp[-2].tree)); }\n break;\n\n case 25:\n { (yyval.stmt) = pcode->placeLabel( (yyvsp[0].labelsym) ); }\n break;\n\n case 26:\n { (yyval.tree) = new ExprTree((yyvsp[0].varnode)); }\n break;\n\n case 27:\n { (yyval.tree) = pcode->createLoad((yyvsp[-1].starqual),(yyvsp[0].tree)); }\n break;\n\n case 28:\n { (yyval.tree) = (yyvsp[-1].tree); }\n break;\n\n case 29:\n { (yyval.tree) = pcode->createOp(CPUI_INT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 30:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 31:\n { (yyval.tree) = pcode->createOp(CPUI_INT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 32:\n { (yyval.tree) = pcode->createOp(CPUI_INT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 33:\n { (yyval.tree) = pcode->createOp(CPUI_INT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 34:\n { (yyval.tree) = pcode->createOp(CPUI_INT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 35:\n { (yyval.tree) = pcode->createOp(CPUI_INT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 36:\n { (yyval.tree) = pcode->createOp(CPUI_INT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 37:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SLESS,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 38:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SLESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 39:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SLESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 40:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SLESS,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 41:\n { (yyval.tree) = pcode->createOp(CPUI_INT_2COMP,(yyvsp[0].tree)); }\n break;\n\n case 42:\n { (yyval.tree) = pcode->createOp(CPUI_INT_NEGATE,(yyvsp[0].tree)); }\n break;\n\n case 43:\n { (yyval.tree) = pcode->createOp(CPUI_INT_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 44:\n { (yyval.tree) = pcode->createOp(CPUI_INT_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 45:\n { (yyval.tree) = pcode->createOp(CPUI_INT_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 46:\n { (yyval.tree) = pcode->createOp(CPUI_INT_LEFT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 47:\n { (yyval.tree) = pcode->createOp(CPUI_INT_RIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 48:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SRIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 49:\n { (yyval.tree) = pcode->createOp(CPUI_INT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 50:\n { (yyval.tree) = pcode->createOp(CPUI_INT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 51:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SDIV,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 52:\n { (yyval.tree) = pcode->createOp(CPUI_INT_REM,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 53:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SREM,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 54:\n { (yyval.tree) = pcode->createOp(CPUI_BOOL_NEGATE,(yyvsp[0].tree)); }\n break;\n\n case 55:\n { (yyval.tree) = pcode->createOp(CPUI_BOOL_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 56:\n { (yyval.tree) = pcode->createOp(CPUI_BOOL_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 57:\n { (yyval.tree) = pcode->createOp(CPUI_BOOL_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 58:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 59:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 60:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 61:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 62:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 63:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 64:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 65:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 66:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 67:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 68:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NEG,(yyvsp[0].tree)); }\n break;\n\n case 69:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ABS,(yyvsp[-1].tree)); }\n break;\n\n case 70:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_SQRT,(yyvsp[-1].tree)); }\n break;\n\n case 71:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SEXT,(yyvsp[-1].tree)); }\n break;\n\n case 72:\n { (yyval.tree) = pcode->createOp(CPUI_INT_ZEXT,(yyvsp[-1].tree)); }\n break;\n\n case 73:\n { (yyval.tree) = pcode->createOp(CPUI_INT_CARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 74:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SCARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 75:\n { (yyval.tree) = pcode->createOp(CPUI_INT_SBORROW,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 76:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_FLOAT2FLOAT,(yyvsp[-1].tree)); }\n break;\n\n case 77:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_INT2FLOAT,(yyvsp[-1].tree)); }\n break;\n\n case 78:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NAN,(yyvsp[-1].tree)); }\n break;\n\n case 79:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_TRUNC,(yyvsp[-1].tree)); }\n break;\n\n case 80:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_CEIL,(yyvsp[-1].tree)); }\n break;\n\n case 81:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_FLOOR,(yyvsp[-1].tree)); }\n break;\n\n case 82:\n { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ROUND,(yyvsp[-1].tree)); }\n break;\n\n case 83:\n { (yyval.tree) = pcode->createOp(CPUI_NEW,(yyvsp[-1].tree)); }\n break;\n\n case 84:\n { (yyval.tree) = pcode->createOp(CPUI_NEW,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 85:\n { (yyval.tree) = pcode->createOp(CPUI_SUBPIECE,new ExprTree((yyvsp[-3].specsym)->getVarnode()),new ExprTree((yyvsp[-1].varnode))); }\n break;\n\n case 86:\n { (yyval.tree) = pcode->createBitRange((yyvsp[-2].specsym),0,(uint4)(*(yyvsp[0].i) * 8)); delete (yyvsp[0].i); }\n break;\n\n case 87:\n { (yyval.tree) = pcode->createBitRange((yyvsp[-5].specsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i), delete (yyvsp[-1].i); }\n break;\n\n case 88:\n { (yyval.tree) = pcode->createUserOp((yyvsp[-3].useropsym),(yyvsp[-1].param)); }\n break;\n\n case 89:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl((yyvsp[-3].spacesym)->getSpace()); }\n break;\n\n case 90:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl((yyvsp[-1].spacesym)->getSpace()); }\n break;\n\n case 91:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl(pcode->getDefaultSpace()); }\n break;\n\n case 92:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl(pcode->getDefaultSpace()); }\n break;\n\n case 93:\n { VarnodeTpl *sym = (yyvsp[0].specsym)->getVarnode(); (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; }\n break;\n\n case 94:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::j_curspace_size)); delete (yyvsp[0].i); }\n break;\n\n case 95:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); yyerror(\"Parsed integer is too big (overflow)\"); }\n break;\n\n case 96:\n { AddrSpace *spc = (yyvsp[-1].spacesym)->getSpace(); (yyval.varnode) = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*(yyvsp[-3].i)),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete (yyvsp[-3].i); }\n break;\n\n case 97:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::j_relative,(yyvsp[0].labelsym)->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); (yyvsp[0].labelsym)->incrementRefCount(); }\n break;\n\n case 98:\n { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = \"Unknown jump destination: \"+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; }\n break;\n\n case 99:\n { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); }\n break;\n\n case 100:\n { (yyval.varnode) = (yyvsp[0].varnode); }\n break;\n\n case 101:\n { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = \"Unknown varnode parameter: \"+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; }\n break;\n\n case 102:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::real,0)); delete (yyvsp[0].i); }\n break;\n\n case 103:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); yyerror(\"Parsed integer is too big (overflow)\"); }\n break;\n\n case 104:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); }\n break;\n\n case 105:\n { (yyval.varnode) = pcode->addressOf((yyvsp[0].varnode),0); }\n break;\n\n case 106:\n { (yyval.varnode) = pcode->addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); }\n break;\n\n case 107:\n { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); }\n break;\n\n case 108:\n { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = \"Unknown assignment varnode: \"+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; }\n break;\n\n case 109:\n { (yyval.labelsym) = (yyvsp[-1].labelsym); }\n break;\n\n case 110:\n { (yyval.labelsym) = pcode->defineLabel( (yyvsp[-1].str) ); }\n break;\n\n case 111:\n { (yyval.specsym) = (yyvsp[0].varsym); }\n break;\n\n case 112:\n { (yyval.specsym) = (yyvsp[0].operandsym); }\n break;\n\n case 113:\n { (yyval.specsym) = (yyvsp[0].specsym); }\n break;\n\n case 114:\n { (yyval.param) = new vector; }\n break;\n\n case 115:\n { (yyval.param) = new vector; (yyval.param)->push_back((yyvsp[0].tree)); }\n break;\n\n case 116:\n { (yyval.param) = (yyvsp[-2].param); (yyval.param)->push_back((yyvsp[0].tree)); }\n break;\n\n\n\n default: break;\n }\n /* User semantic actions sometimes alter yychar, and that requires\n that yytoken be updated with the new translation. We take the\n approach of translating immediately before every use of yytoken.\n One alternative is translating here after every semantic action,\n but that translation would be missed if the semantic action invokes\n YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or\n if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an\n incorrect destructor might then be invoked immediately. In the\n case of YYERROR or YYBACKUP, subsequent parser actions might lead\n to an incorrect destructor call or verbose syntax error message\n before the lookahead is translated. */\n YY_SYMBOL_PRINT (\"-> $$ =\", yyr1[yyn], &yyval, &yyloc);\n\n YYPOPSTACK (yylen);\n yylen = 0;\n YY_STACK_PRINT (yyss, yyssp);\n\n *++yyvsp = yyval;\n\n /* Now 'shift' the result of the reduction. Determine what state\n that goes to, based on the state we popped back to and the rule\n number reduced by. */\n {\n const int yylhs = yyr1[yyn] - YYNTOKENS;\n const int yyi = yypgoto[yylhs] + *yyssp;\n yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp\n ? yytable[yyi]\n : yydefgoto[yylhs]);\n }\n\n goto yynewstate;\n\n\n/*--------------------------------------.\n| yyerrlab -- here on detecting error. |\n`--------------------------------------*/\nyyerrlab:\n /* Make sure we have latest lookahead translation. See comments at\n user semantic actions for why this is necessary. */\n yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);\n\n /* If not already recovering from an error, report this error. */\n if (!yyerrstatus)\n {\n ++yynerrs;\n#if ! YYERROR_VERBOSE\n yyerror (YY_(\"syntax error\"));\n#else\n# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \\\n yyssp, yytoken)\n {\n char const *yymsgp = YY_(\"syntax error\");\n int yysyntax_error_status;\n yysyntax_error_status = YYSYNTAX_ERROR;\n if (yysyntax_error_status == 0)\n yymsgp = yymsg;\n else if (yysyntax_error_status == 1)\n {\n if (yymsg != yymsgbuf)\n YYSTACK_FREE (yymsg);\n yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc)));\n if (!yymsg)\n {\n yymsg = yymsgbuf;\n yymsg_alloc = sizeof yymsgbuf;\n yysyntax_error_status = 2;\n }\n else\n {\n yysyntax_error_status = YYSYNTAX_ERROR;\n yymsgp = yymsg;\n }\n }\n yyerror (yymsgp);\n if (yysyntax_error_status == 2)\n goto yyexhaustedlab;\n }\n# undef YYSYNTAX_ERROR\n#endif\n }\n\n\n\n if (yyerrstatus == 3)\n {\n /* If just tried and failed to reuse lookahead token after an\n error, discard it. */\n\n if (yychar <= YYEOF)\n {\n /* Return failure if at end of input. */\n if (yychar == YYEOF)\n YYABORT;\n }\n else\n {\n yydestruct (\"Error: discarding\",\n yytoken, &yylval);\n yychar = YYEMPTY;\n }\n }\n\n /* Else will try to reuse lookahead token after shifting the error\n token. */\n goto yyerrlab1;\n\n\n/*---------------------------------------------------.\n| yyerrorlab -- error raised explicitly by YYERROR. |\n`---------------------------------------------------*/\nyyerrorlab:\n /* Pacify compilers when the user code never invokes YYERROR and the\n label yyerrorlab therefore never appears in user code. */\n if (0)\n YYERROR;\n\n /* Do not reclaim the symbols of the rule whose action triggered\n this YYERROR. */\n YYPOPSTACK (yylen);\n yylen = 0;\n YY_STACK_PRINT (yyss, yyssp);\n yystate = *yyssp;\n goto yyerrlab1;\n\n\n/*-------------------------------------------------------------.\n| yyerrlab1 -- common code for both syntax error and YYERROR. |\n`-------------------------------------------------------------*/\nyyerrlab1:\n yyerrstatus = 3; /* Each real token shifted decrements this. */\n\n for (;;)\n {\n yyn = yypact[yystate];\n if (!yypact_value_is_default (yyn))\n {\n yyn += YYTERROR;\n if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)\n {\n yyn = yytable[yyn];\n if (0 < yyn)\n break;\n }\n }\n\n /* Pop the current state because it cannot handle the error token. */\n if (yyssp == yyss)\n YYABORT;\n\n\n yydestruct (\"Error: popping\",\n yystos[yystate], yyvsp);\n YYPOPSTACK (1);\n yystate = *yyssp;\n YY_STACK_PRINT (yyss, yyssp);\n }\n\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n *++yyvsp = yylval;\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n\n /* Shift the error token. */\n YY_SYMBOL_PRINT (\"Shifting\", yystos[yyn], yyvsp, yylsp);\n\n yystate = yyn;\n goto yynewstate;\n\n\n/*-------------------------------------.\n| yyacceptlab -- YYACCEPT comes here. |\n`-------------------------------------*/\nyyacceptlab:\n yyresult = 0;\n goto yyreturn;\n\n\n/*-----------------------------------.\n| yyabortlab -- YYABORT comes here. |\n`-----------------------------------*/\nyyabortlab:\n yyresult = 1;\n goto yyreturn;\n\n\n#if !defined yyoverflow || YYERROR_VERBOSE\n/*-------------------------------------------------.\n| yyexhaustedlab -- memory exhaustion comes here. |\n`-------------------------------------------------*/\nyyexhaustedlab:\n yyerror (YY_(\"memory exhausted\"));\n yyresult = 2;\n /* Fall through. */\n#endif\n\n\n/*-----------------------------------------------------.\n| yyreturn -- parsing is finished, return the result. |\n`-----------------------------------------------------*/\nyyreturn:\n if (yychar != YYEMPTY)\n {\n /* Make sure we have latest lookahead translation. See comments at\n user semantic actions for why this is necessary. */\n yytoken = YYTRANSLATE (yychar);\n yydestruct (\"Cleanup: discarding lookahead\",\n yytoken, &yylval);\n }\n /* Do not reclaim the symbols of the rule whose action triggered\n this YYABORT or YYACCEPT. */\n YYPOPSTACK (yylen);\n YY_STACK_PRINT (yyss, yyssp);\n while (yyssp != yyss)\n {\n yydestruct (\"Cleanup: popping\",\n yystos[+*yyssp], yyvsp);\n YYPOPSTACK (1);\n }\n#ifndef yyoverflow\n if (yyss != yyssa)\n YYSTACK_FREE (yyss);\n#endif\n#if YYERROR_VERBOSE\n if (yymsg != yymsgbuf)\n YYSTACK_FREE (yymsg);\n#endif\n return yyresult;\n}\n\n\n#define IDENTREC_SIZE 46\nconst IdentRec PcodeLexer::idents[]= { // Sorted list of identifiers\n { \"!=\", OP_NOTEQUAL },\n { \"&&\", OP_BOOL_AND },\n { \"<<\", OP_LEFT },\n { \"<=\", OP_LESSEQUAL },\n { \"==\", OP_EQUAL },\n { \">=\", OP_GREATEQUAL },\n { \">>\", OP_RIGHT },\n { \"^^\", OP_BOOL_XOR },\n { \"||\", OP_BOOL_OR },\n { \"abs\", OP_ABS },\n { \"borrow\", OP_BORROW },\n { \"call\", CALL_KEY },\n { \"carry\", OP_CARRY },\n { \"ceil\", OP_CEIL },\n { \"f!=\", OP_FNOTEQUAL },\n { \"f*\", OP_FMULT },\n { \"f+\", OP_FADD },\n { \"f-\", OP_FSUB },\n { \"f/\", OP_FDIV },\n { \"f<\", OP_FLESS },\n { \"f<=\", OP_FLESSEQUAL },\n { \"f==\", OP_FEQUAL },\n { \"f>\", OP_FGREAT },\n { \"f>=\", OP_FGREATEQUAL },\n { \"float2float\", OP_FLOAT2FLOAT },\n { \"floor\", OP_FLOOR },\n { \"goto\", GOTO_KEY },\n { \"if\", IF_KEY },\n { \"int2float\", OP_INT2FLOAT },\n { \"local\", LOCAL_KEY },\n { \"nan\", OP_NAN },\n { \"return\", RETURN_KEY },\n { \"round\", OP_ROUND },\n { \"s%\", OP_SREM },\n { \"s/\", OP_SDIV },\n { \"s<\", OP_SLESS },\n { \"s<=\", OP_SLESSEQUAL },\n { \"s>\", OP_SGREAT },\n { \"s>=\", OP_SGREATEQUAL },\n { \"s>>\",OP_SRIGHT },\n { \"sborrow\", OP_SBORROW },\n { \"scarry\", OP_SCARRY },\n { \"sext\", OP_SEXT },\n { \"sqrt\", OP_SQRT },\n { \"trunc\", OP_TRUNC },\n { \"zext\", OP_ZEXT }\n};\n\nint4 PcodeLexer::findIdentifier(const string &str) const\n\n{\n int4 low = 0;\n int4 high = IDENTREC_SIZE-1;\n int4 comp;\n do {\n int4 targ = (low+high)/2;\n comp = str.compare(idents[targ].nm);\n if (comp < 0) \t\t// str comes before targ\n high = targ-1;\n else if (comp > 0)\t\t// str comes after targ\n low = targ + 1;\n else\n return targ;\n } while(low <= high);\n return -1;\n}\n\nint4 PcodeLexer::moveState(void)\n\n{\n switch(curstate) {\n case start:\n switch(curchar) {\n case '#':\n curstate = comment;\n return start;\n case '|':\n if (lookahead1 == '|') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '&':\n if (lookahead1 == '&') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '^':\n if (lookahead1 == '^') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '>':\n if ((lookahead1 == '>')||(lookahead1=='=')) {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '<':\n if ((lookahead1 == '<')||(lookahead1=='=')) {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '=':\n if (lookahead1 == '=') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '!':\n if (lookahead1 == '=') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '(':\n case ')':\n case ',':\n case ':':\n case '[':\n case ']':\n case ';':\n case '+':\n case '-':\n case '*':\n case '/':\n case '%':\n case '~':\n return punctuation;\n case 's':\n case 'f':\n if (curchar == 's') {\n\tif ((lookahead1 == '/')||(lookahead1=='%')) {\n\t starttoken();\n\t curstate = special2;\n\t return start;\n\t}\n\telse if (lookahead1 == '<') {\n\t starttoken();\n\t if (lookahead2 == '=')\n\t curstate = special3;\n\t else\n\t curstate = special2;\n\t return start;\n\t}\n\telse if (lookahead1 == '>') {\n\t starttoken();\n\t if ((lookahead2=='>')||(lookahead2=='='))\n\t curstate = special3;\n\t else\n\t curstate = special2;\n\t return start;\n\t}\n }\n else {\t\t\t// curchar == 'f'\n\tif ((lookahead1=='+')||(lookahead1=='-')||(lookahead1=='*')||(lookahead1=='/')) {\n\t starttoken();\n\t curstate = special2;\n\t return start;\n\t}\n\telse if (((lookahead1=='=')||(lookahead1=='!'))&&(lookahead2=='=')) {\n\t starttoken();\n\t curstate = special3;\n\t return start;\n\t}\n\telse if ((lookahead1=='<')||(lookahead1=='>')) {\n\t starttoken();\n\t if (lookahead2 == '=')\n\t curstate = special3;\n\t else\n\t curstate = special2;\n\t return start;\n\t}\n }\n // fall through here, treat 's' and 'f' as ordinary characters\n case 'a':\n case 'b':\n case 'c':\n case 'd':\n case 'e':\n case 'g':\n case 'h':\n case 'i':\n case 'j':\n case 'k':\n case 'l':\n case 'm':\n case 'n':\n case 'o':\n case 'p':\n case 'q':\n case 'r':\n case 't':\n case 'u':\n case 'v':\n case 'w':\n case 'x':\n case 'y':\n case 'z':\n case 'A':\n case 'B':\n case 'C':\n case 'D':\n case 'E':\n case 'F':\n case 'G':\n case 'H':\n case 'I':\n case 'J':\n case 'K':\n case 'L':\n case 'M':\n case 'N':\n case 'O':\n case 'P':\n case 'Q':\n case 'R':\n case 'S':\n case 'T':\n case 'U':\n case 'V':\n case 'W':\n case 'X':\n case 'Y':\n case 'Z':\n case '_':\n case '.':\n starttoken();\n if (isIdent(lookahead1)) {\n\tcurstate = identifier;\n\treturn start;\n }\n curstate = start;\n return identifier;\n case '0':\n starttoken();\n if (lookahead1 == 'x') {\n\tcurstate = hexstring;\n\treturn start;\n }\n if (isDec(lookahead1)) {\n\tcurstate = decstring;\n\treturn start;\n }\n curstate = start;\n return decstring;\n case '1':\n case '2':\n case '3':\n case '4':\n case '5':\n case '6':\n case '7':\n case '8':\n case '9':\n starttoken();\n if (isDec(lookahead1)) {\n\tcurstate = decstring;\n\treturn start;\n }\n curstate = start;\n return decstring;\n case '\\n':\n case ' ':\n case '\\t':\n case '\\v':\n case '\\r':\n return start;\t\t// Ignore whitespace\n case '\\0':\n curstate = endstream;\n return endstream;\n default:\n curstate = illegal;\n return illegal;\n }\n break;\n case special2:\n advancetoken();\n curstate = start;\n return identifier;\n case special3:\n advancetoken();\n curstate = special32;\n return start;\n case special32:\n advancetoken();\n curstate = start;\n return identifier;\n case comment:\n if (curchar == '\\n')\n curstate = start;\n else if (curchar == '\\0') {\n curstate = endstream;\n return endstream;\n }\n return start;\n case identifier:\n advancetoken();\n if (isIdent(lookahead1))\n return start;\n curstate = start;\n return identifier;\n case hexstring:\n advancetoken();\n if (isHex(lookahead1))\n return start;\n curstate = start;\n return hexstring;\n case decstring:\n advancetoken();\n if (isDec(lookahead1))\n return start;\n curstate = start;\n return decstring;\n default:\n curstate = endstream;\n }\n return endstream;\n}\n\nint4 PcodeLexer::getNextToken(void)\n\n{ // Will return either: identifier, punctuation, hexstring, decstring, endstream, or illegal\n // If identifier, hexstring, or decstring, curtoken will be filled with the characters\n int4 tok;\n do {\n curchar = lookahead1;\n lookahead1 = lookahead2;\n if (endofstream)\n lookahead2 = '\\0';\n else {\n s->get(lookahead2);\n if (!(*s)) {\n\tendofstream = true;\n\tlookahead2 = '\\0';\n }\n }\n tok = moveState();\n } while(tok == start);\n if (tok == identifier) {\n curtoken[tokpos] = '\\0';\t// Append null terminator\n curidentifier = curtoken;\n int4 num = findIdentifier(curidentifier);\n if (num < 0)\t\t\t// Not a keyword\n return STRING;\n return idents[num].id;\n }\n else if ((tok == hexstring)||(tok == decstring)) {\n curtoken[tokpos] = '\\0';\n istringstream s1(curtoken);\n s1.unsetf(ios::dec | ios::hex | ios::oct);\n s1 >> curnum;\n if (!s1)\n return BADINTEGER;\n return INTEGER;\n }\n else if (tok == endstream) {\n if (!endofstreamsent) {\n endofstreamsent = true;\n return ENDOFSTREAM;\t// Send 'official' end of stream token\n }\n return 0;\t\t\t// 0 means end of file to parser\n }\n else if (tok == illegal)\n return 0;\n return (int4)curchar;\n}\n\nvoid PcodeLexer::initialize(istream *t)\n\n{ // Set up for new lex\n s = t;\n curstate = start;\n tokpos = 0;\n endofstream = false;\n endofstreamsent = false;\n lookahead1 = 0;\n lookahead2 = 0;\n s->get(lookahead1);\t\t// Buffer the first two characters\n if (!(*s)) {\n endofstream = true;\n lookahead1 = 0;\n return;\n }\n s->get(lookahead2);\n if (!(*s)) {\n endofstream = true;\n lookahead2 = 0;\n return;\n }\n}\n\nuint4 PcodeSnippet::allocateTemp(void)\n\n{ // Allocate a variable in the unique space and return the offset\n uint4 res = tempbase;\n tempbase += 16;\n return res;\n}\n\nvoid PcodeSnippet::addSymbol(SleighSymbol *sym)\n\n{\n pair res;\n\n res = tree.insert( sym );\n if (!res.second) {\n reportError((const Location *)0,\"Duplicate symbol name: \"+sym->getName());\n delete sym;\t\t// Symbol is unattached to anything else\n }\n}\n\nvoid PcodeSnippet::clear(void)\n\n{ // Clear everything, prepare for a new parse against the same language\n SymbolTree::iterator iter,tmpiter;\n iter = tree.begin();\n while(iter != tree.end()) {\n SleighSymbol *sym = *iter;\n tmpiter = iter;\n ++iter;\t\t\t// Increment now, as node may be deleted\n if (sym->getType() != SleighSymbol::space_symbol) {\n delete sym;\t\t// Free any old local symbols\n tree.erase(tmpiter);\n }\n }\n if (result != (ConstructTpl *)0) {\n delete result;\n result = (ConstructTpl *)0;\n }\n // tempbase = 0;\n errorcount = 0;\n firsterror.clear();\n resetLabelCount();\n}\n\nPcodeSnippet::PcodeSnippet(const SleighBase *slgh)\n : PcodeCompile()\n{\n sleigh = slgh;\n tempbase = 0;\n errorcount = 0;\n result = (ConstructTpl *)0;\n setDefaultSpace(slgh->getDefaultCodeSpace());\n setConstantSpace(slgh->getConstantSpace());\n setUniqueSpace(slgh->getUniqueSpace());\n int4 num = slgh->numSpaces();\n for(int4 i=0;igetSpace(i);\n spacetype type = spc->getType();\n if ((type==IPTR_CONSTANT)||(type==IPTR_PROCESSOR)||(type==IPTR_SPACEBASE)||(type==IPTR_INTERNAL))\n tree.insert(new SpaceSymbol(spc));\n }\n addSymbol(new FlowDestSymbol(\"inst_dest\",slgh->getConstantSpace()));\n addSymbol(new FlowRefSymbol(\"inst_ref\",slgh->getConstantSpace()));\n}\n\nPcodeSnippet::~PcodeSnippet(void)\n\n{\n SymbolTree::iterator iter;\n for(iter=tree.begin();iter!=tree.end();++iter)\n delete *iter;\t\t// Free ALL temporary symbols\n if (result != (ConstructTpl *)0) {\n delete result;\n result = (ConstructTpl *)0;\n }\n}\n\nvoid PcodeSnippet::reportError(const Location *loc, const string &msg)\n\n{\n if (errorcount == 0)\n firsterror = msg;\n errorcount += 1;\n}\n\nint4 PcodeSnippet::lex(void)\n\n{\n int4 tok = lexer.getNextToken();\n if (tok == STRING) {\n SleighSymbol *sym;\n SleighSymbol tmpsym(lexer.getIdentifier());\n SymbolTree::const_iterator iter = tree.find(&tmpsym);\n if (iter != tree.end())\n sym = *iter;\t\t// Found a local symbol\n else\n sym = sleigh->findSymbol(lexer.getIdentifier());\n if (sym != (SleighSymbol *)0) {\n switch(sym->getType()) {\n case SleighSymbol::space_symbol:\n\tyylval.spacesym = (SpaceSymbol *)sym;\n\treturn SPACESYM;\n case SleighSymbol::userop_symbol:\n\tyylval.useropsym = (UserOpSymbol *)sym;\n\treturn USEROPSYM;\n case SleighSymbol::varnode_symbol:\n\tyylval.varsym = (VarnodeSymbol *)sym;\n\treturn VARSYM;\n case SleighSymbol::operand_symbol:\n\tyylval.operandsym = (OperandSymbol *)sym;\n\treturn OPERANDSYM;\n case SleighSymbol::start_symbol:\n case SleighSymbol::end_symbol:\n case SleighSymbol::next2_symbol:\n case SleighSymbol::flowdest_symbol:\n case SleighSymbol::flowref_symbol:\n\tyylval.specsym = (SpecificSymbol *)sym;\n\treturn JUMPSYM;\n case SleighSymbol::label_symbol:\n\tyylval.labelsym = (LabelSymbol *)sym;\n\treturn LABELSYM;\n case SleighSymbol::dummy_symbol:\n\tbreak;\n default:\n\t// The translator may have other symbols in it that we don't want visible in the snippet compiler\n\tbreak;\n }\n }\n yylval.str = new string(lexer.getIdentifier());\n return STRING;\n }\n if (tok == INTEGER) {\n yylval.i = new uintb(lexer.getNumber());\n return INTEGER;\n }\n return tok;\n}\n\n bool PcodeSnippet::parseStream(istream &s)\n\n{\n lexer.initialize(&s);\n pcode = this;\t\t\t// Setup global object for yyparse\n int4 res = yyparse();\n if (res != 0) {\n reportError((const Location *)0,\"Syntax error\");\n return false;\n }\n if (!PcodeCompile::propagateSize(result)) {\n reportError((const Location *)0,\"Could not resolve at least 1 variable size\");\n return false;\n }\n return true;\n}\n\nvoid PcodeSnippet::addOperand(const string &name,int4 index)\n\n{ // Add an operand symbol for this snippet\n OperandSymbol *sym = new OperandSymbol(name,index,(Constructor *)0);\n addSymbol(sym);\n}\n\nint pcodelex(void) {\n return pcode->lex();\n}\n\nint pcodeerror(const char *s)\n\n{\n pcode->reportError((const Location *)0,s);\n return 0;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/pcodeparse.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __PCODEPARSE_HH__\n#define __PCODEPARSE_HH__\n\n#include \"pcodecompile.hh\"\n#include \"sleighbase.hh\"\n\nnamespace ghidra {\n\n// Classes for compiling a standalone snippet of pcode, given an existing sleigh language\n\nstruct IdentRec {\n const char *nm;\n int4 id;\n};\n\nclass PcodeLexer {\npublic:\n enum {\t\t\t// Lexer states\n start,\n special2,\t\t\t// Middle of special 2 character operator\n special3, // First character of special 3 character operator\n special32,\t\t\t// Second character of special 3 character operator\n comment,\t\t\t// Middle of an endofline comment\n punctuation,\t\t// Punctuation character\n identifier,\t\t\t// Middle of an identifier\n hexstring,\t\t\t// Middle of a hexidecimal number\n decstring,\t\t\t// Middle of a decimal number\n endstream,\t\t\t// Reached end of stream\n illegal\t\t\t// Scanned an illegal character\n };\nprivate:\n static const IdentRec idents[];\n int4 curstate;\n char curchar,lookahead1,lookahead2;\n char curtoken[256];\n int4 tokpos;\n bool endofstream;\n bool endofstreamsent;\n istream *s;\n string curidentifier;\n uintb curnum;\n void starttoken(void) { curtoken[0] = curchar; tokpos = 1; }\n void advancetoken(void) { curtoken[tokpos++] = curchar; }\n bool isIdent(char c) const { return (isalnum(c)||(c=='_')||(c=='.')); }\n bool isHex(char c) const { return isxdigit(c); }\n bool isDec(char c) const { return isdigit(c); }\n int4 findIdentifier(const string &str) const;\n int4 moveState(void);\npublic:\n PcodeLexer(void) { s = (istream *)0; }\n void initialize(istream *t);\n int4 getNextToken(void);\n const string &getIdentifier(void) const { return curidentifier; }\n uintb getNumber(void) const { return curnum; }\n};\n\nclass PcodeSnippet : public PcodeCompile {\n PcodeLexer lexer;\n const SleighBase *sleigh;\t// Language from which we get symbols\n SymbolTree tree;\t\t// Symbols in the local scope of the snippet (temporaries)\n uint4 tempbase;\n int4 errorcount;\n string firsterror;\n ConstructTpl *result;\n virtual uint4 allocateTemp(void);\n virtual void addSymbol(SleighSymbol *sym);\npublic: \n PcodeSnippet(const SleighBase *slgh);\n void setResult(ConstructTpl *res) { result = res; }\n ConstructTpl *releaseResult(void) { ConstructTpl *res = result; result = (ConstructTpl *)0; return res; }\n virtual ~PcodeSnippet(void);\n virtual const Location *getLocation(SleighSymbol *sym) const { return (const Location *)0; }\n virtual void reportError(const Location *loc, const string &msg);\n virtual void reportWarning(const Location *loc, const string &msg) {}\n bool hasErrors(void) const { return (errorcount != 0); }\n const string getErrorMessage(void) const { return firsterror; }\n void setUniqueBase(uint4 val) { tempbase = val; }\n uint4 getUniqueBase(void) const { return tempbase; }\n void clear(void);\n int lex(void);\n bool parseStream(istream& s);\n void addOperand(const string &name,int4 index);\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/pcodeparse.y", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n%define api.prefix {pcode}\n%{\n#include \"pcodeparse.hh\"\n\n//#define YYERROR_VERBOSE\nnamespace ghidra {\n\nextern int pcodelex(void);\nstatic PcodeSnippet *pcode;\nextern int pcodeerror(const char *str );\n%}\n\n%union {\n uintb *i;\n string *str;\n vector *param;\n StarQuality *starqual;\n VarnodeTpl *varnode;\n ExprTree *tree;\n vector *stmt;\n ConstructTpl *sem;\n\n SpaceSymbol *spacesym;\n UserOpSymbol *useropsym;\n LabelSymbol *labelsym;\n OperandSymbol *operandsym;\n VarnodeSymbol *varsym;\n SpecificSymbol *specsym;\n}\n\n%expect 3\n// Conflicts\n// 1 integervarnode ':' conflict (does ':' apply to INTEGER or varnode)\n// resolved by shifting which applies ':' to INTEGER (best solution)\n// 2 statement -> STRING . conflicts (STRING might be mislabelled varnode, or temporary declaration)\n// resolved by shifting which means assume this is a temporary declaration\n\n%left OP_BOOL_OR\n%left OP_BOOL_AND OP_BOOL_XOR\n%left '|'\n%left ';'\n%left '^'\n%left '&'\n%left OP_EQUAL OP_NOTEQUAL OP_FEQUAL OP_FNOTEQUAL\n%nonassoc '<' '>' OP_GREATEQUAL OP_LESSEQUAL OP_SLESS OP_SGREATEQUAL OP_SLESSEQUAL OP_SGREAT OP_FLESS OP_FGREAT OP_FLESSEQUAL OP_FGREATEQUAL\n%left OP_LEFT OP_RIGHT OP_SRIGHT\n%left '+' '-' OP_FADD OP_FSUB\n%left '*' '/' '%' OP_SDIV OP_SREM OP_FMULT OP_FDIV\n%right '!' '~'\n%token OP_ZEXT OP_CARRY OP_BORROW OP_SEXT OP_SCARRY OP_SBORROW OP_NAN OP_ABS\n%token OP_SQRT OP_CEIL OP_FLOOR OP_ROUND OP_INT2FLOAT OP_FLOAT2FLOAT\n%token OP_TRUNC OP_NEW\n\n%token BADINTEGER GOTO_KEY CALL_KEY RETURN_KEY IF_KEY ENDOFSTREAM LOCAL_KEY\n\n%token INTEGER\n%token STRING\n%token SPACESYM\n%token USEROPSYM\n%token VARSYM\n%token OPERANDSYM\n%token JUMPSYM\n%token LABELSYM\n\n%type paramlist\n%type rtlmid\n%type statement\n%type expr\n%type varnode integervarnode lhsvarnode jumpdest\n%type label\n%type sizedstar\n%type specificsymbol\n\n%destructor { delete $$; } INTEGER\n%destructor { delete $$; } STRING\n%destructor { for(int4 i=0;i<$$->size();++i) delete (*$$)[i]; delete $$; } paramlist\n%destructor { delete $$; } rtlmid\n%destructor { if ($$ != (vector *)0) { for(int4 i=0;i<$$->size();++i) delete (*$$)[i]; delete $$;} } statement\n%destructor { delete $$; } expr\n%destructor { if ($$ != (VarnodeTpl *)0) delete $$; } varnode integervarnode lhsvarnode jumpdest\n%destructor { delete $$; } sizedstar\n\n%%\nrtl: rtlmid ENDOFSTREAM { pcode->setResult($1); }\n ;\nrtlmid: /* EMPTY */\t\t\t{ $$ = new ConstructTpl(); }\n | rtlmid statement\t\t\t{ $$ = $1; if (!$$->addOpList(*$2)) { delete $2; yyerror(\"Multiple delayslot declarations\"); YYERROR; } delete $2; }\n | rtlmid LOCAL_KEY STRING ';' { $$ = $1; pcode->newLocalDefinition($3); }\n | rtlmid LOCAL_KEY STRING ':' INTEGER ';' { $$ = $1; pcode->newLocalDefinition($3,*$5); delete $5; }\n ;\nstatement: lhsvarnode '=' expr ';'\t{ $3->setOutput($1); $$ = ExprTree::toVector($3); }\n | LOCAL_KEY STRING '=' expr ';'\t{ $$ = pcode->newOutput(true,$4,$2); }\n | STRING '=' expr ';'\t\t\t{ $$ = pcode->newOutput(false,$3,$1); }\n | LOCAL_KEY STRING ':' INTEGER '=' expr ';'\t{ $$ = pcode->newOutput(true,$6,$2,*$4); delete $4; }\n | STRING ':' INTEGER '=' expr ';'\t{ $$ = pcode->newOutput(true,$5,$1,*$3); delete $3; }\n | LOCAL_KEY specificsymbol '=' { $$ = (vector *)0; string errmsg = \"Redefinition of symbol: \"+$2->getName(); yyerror(errmsg.c_str()); YYERROR; }\n | sizedstar expr '=' expr ';'\t\t{ $$ = pcode->createStore($1,$2,$4); }\n | USEROPSYM '(' paramlist ')' ';'\t{ $$ = pcode->createUserOpNoOut($1,$3); }\n | lhsvarnode '[' INTEGER ',' INTEGER ']' '=' expr ';' { $$ = pcode->assignBitRange($1,(uint4)*$3,(uint4)*$5,$8); delete $3, delete $5; }\n | varnode ':' INTEGER '='\t\t{ $$ = (vector *)0; delete $1; delete $3; yyerror(\"Illegal truncation on left-hand side of assignment\"); YYERROR; }\n | varnode '(' INTEGER ')'\t\t{ $$ = (vector *)0; delete $1; delete $3; yyerror(\"Illegal subpiece on left-hand side of assignment\"); YYERROR; }\n | GOTO_KEY jumpdest ';'\t\t{ $$ = pcode->createOpNoOut(CPUI_BRANCH,new ExprTree($2)); }\n | IF_KEY expr GOTO_KEY jumpdest ';'\t{ $$ = pcode->createOpNoOut(CPUI_CBRANCH,new ExprTree($4),$2); }\n | GOTO_KEY '[' expr ']' ';'\t\t{ $$ = pcode->createOpNoOut(CPUI_BRANCHIND,$3); }\n | CALL_KEY jumpdest ';'\t\t{ $$ = pcode->createOpNoOut(CPUI_CALL,new ExprTree($2)); }\n | CALL_KEY '[' expr ']' ';'\t\t{ $$ = pcode->createOpNoOut(CPUI_CALLIND,$3); }\n | RETURN_KEY ';'\t\t\t{ $$ = (vector *)0; yyerror(\"Must specify an indirect parameter for return\"); YYERROR; }\n | RETURN_KEY '[' expr ']' ';'\t\t{ $$ = pcode->createOpNoOut(CPUI_RETURN,$3); }\n | label { $$ = pcode->placeLabel( $1 ); }\n ;\nexpr: varnode { $$ = new ExprTree($1); }\n | sizedstar expr %prec '!'\t{ $$ = pcode->createLoad($1,$2); }\n | '(' expr ')'\t\t{ $$ = $2; }\n | expr '+' expr\t\t{ $$ = pcode->createOp(CPUI_INT_ADD,$1,$3); }\n | expr '-' expr\t\t{ $$ = pcode->createOp(CPUI_INT_SUB,$1,$3); }\n | expr OP_EQUAL expr\t\t{ $$ = pcode->createOp(CPUI_INT_EQUAL,$1,$3); }\n | expr OP_NOTEQUAL expr\t{ $$ = pcode->createOp(CPUI_INT_NOTEQUAL,$1,$3); }\n | expr '<' expr\t\t{ $$ = pcode->createOp(CPUI_INT_LESS,$1,$3); }\n | expr OP_GREATEQUAL expr\t{ $$ = pcode->createOp(CPUI_INT_LESSEQUAL,$3,$1); }\n | expr OP_LESSEQUAL expr\t{ $$ = pcode->createOp(CPUI_INT_LESSEQUAL,$1,$3); }\n | expr '>' expr\t\t{ $$ = pcode->createOp(CPUI_INT_LESS,$3,$1); }\n | expr OP_SLESS expr\t\t{ $$ = pcode->createOp(CPUI_INT_SLESS,$1,$3); }\n | expr OP_SGREATEQUAL expr\t{ $$ = pcode->createOp(CPUI_INT_SLESSEQUAL,$3,$1); }\n | expr OP_SLESSEQUAL expr\t{ $$ = pcode->createOp(CPUI_INT_SLESSEQUAL,$1,$3); }\n | expr OP_SGREAT expr\t\t{ $$ = pcode->createOp(CPUI_INT_SLESS,$3,$1); }\n | '-' expr\t%prec '!' \t{ $$ = pcode->createOp(CPUI_INT_2COMP,$2); }\n | '~' expr\t\t\t{ $$ = pcode->createOp(CPUI_INT_NEGATE,$2); }\n | expr '^' expr\t\t{ $$ = pcode->createOp(CPUI_INT_XOR,$1,$3); }\n | expr '&' expr\t\t{ $$ = pcode->createOp(CPUI_INT_AND,$1,$3); }\n | expr '|' expr\t\t{ $$ = pcode->createOp(CPUI_INT_OR,$1,$3); }\n | expr OP_LEFT expr\t\t{ $$ = pcode->createOp(CPUI_INT_LEFT,$1,$3); }\n | expr OP_RIGHT expr\t\t{ $$ = pcode->createOp(CPUI_INT_RIGHT,$1,$3); }\n | expr OP_SRIGHT expr\t\t{ $$ = pcode->createOp(CPUI_INT_SRIGHT,$1,$3); }\n | expr '*' expr\t\t{ $$ = pcode->createOp(CPUI_INT_MULT,$1,$3); }\n | expr '/' expr\t\t{ $$ = pcode->createOp(CPUI_INT_DIV,$1,$3); }\n | expr OP_SDIV expr\t\t{ $$ = pcode->createOp(CPUI_INT_SDIV,$1,$3); }\n | expr '%' expr\t\t{ $$ = pcode->createOp(CPUI_INT_REM,$1,$3); }\n | expr OP_SREM expr\t\t{ $$ = pcode->createOp(CPUI_INT_SREM,$1,$3); }\n | '!' expr\t\t\t{ $$ = pcode->createOp(CPUI_BOOL_NEGATE,$2); }\n | expr OP_BOOL_XOR expr\t{ $$ = pcode->createOp(CPUI_BOOL_XOR,$1,$3); }\n | expr OP_BOOL_AND expr\t{ $$ = pcode->createOp(CPUI_BOOL_AND,$1,$3); }\n | expr OP_BOOL_OR expr\t{ $$ = pcode->createOp(CPUI_BOOL_OR,$1,$3); }\n | expr OP_FEQUAL expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_EQUAL,$1,$3); }\n | expr OP_FNOTEQUAL expr\t{ $$ = pcode->createOp(CPUI_FLOAT_NOTEQUAL,$1,$3); }\n | expr OP_FLESS expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_LESS,$1,$3); }\n | expr OP_FGREAT expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_LESS,$3,$1); }\n | expr OP_FLESSEQUAL expr\t{ $$ = pcode->createOp(CPUI_FLOAT_LESSEQUAL,$1,$3); }\n | expr OP_FGREATEQUAL expr\t{ $$ = pcode->createOp(CPUI_FLOAT_LESSEQUAL,$3,$1); }\n | expr OP_FADD expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_ADD,$1,$3); }\n | expr OP_FSUB expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_SUB,$1,$3); }\n | expr OP_FMULT expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_MULT,$1,$3); }\n | expr OP_FDIV expr\t\t{ $$ = pcode->createOp(CPUI_FLOAT_DIV,$1,$3); }\n | OP_FSUB expr %prec '!' { $$ = pcode->createOp(CPUI_FLOAT_NEG,$2); }\n | OP_ABS '(' expr ')'\t\t{ $$ = pcode->createOp(CPUI_FLOAT_ABS,$3); }\n | OP_SQRT '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_SQRT,$3); }\n | OP_SEXT '(' expr ')'\t{ $$ = pcode->createOp(CPUI_INT_SEXT,$3); }\n | OP_ZEXT '(' expr ')'\t{ $$ = pcode->createOp(CPUI_INT_ZEXT,$3); }\n | OP_CARRY '(' expr ',' expr ')' { $$ = pcode->createOp(CPUI_INT_CARRY,$3,$5); }\n | OP_SCARRY '(' expr ',' expr ')' { $$ = pcode->createOp(CPUI_INT_SCARRY,$3,$5); }\n | OP_SBORROW '(' expr ',' expr ')' { $$ = pcode->createOp(CPUI_INT_SBORROW,$3,$5); }\n | OP_FLOAT2FLOAT '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_FLOAT2FLOAT,$3); }\n | OP_INT2FLOAT '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_INT2FLOAT,$3); }\n | OP_NAN '(' expr ')'\t\t{ $$ = pcode->createOp(CPUI_FLOAT_NAN,$3); }\n | OP_TRUNC '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_TRUNC,$3); }\n | OP_CEIL '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_CEIL,$3); }\n | OP_FLOOR '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_FLOOR,$3); }\n | OP_ROUND '(' expr ')'\t{ $$ = pcode->createOp(CPUI_FLOAT_ROUND,$3); };\n | OP_NEW '(' expr ')' { $$ = pcode->createOp(CPUI_NEW,$3); };\n | OP_NEW '(' expr ',' expr ')' { $$ = pcode->createOp(CPUI_NEW,$3,$5); }\n | specificsymbol '(' integervarnode ')' { $$ = pcode->createOp(CPUI_SUBPIECE,new ExprTree($1->getVarnode()),new ExprTree($3)); }\n | specificsymbol ':' INTEGER\t{ $$ = pcode->createBitRange($1,0,(uint4)(*$3 * 8)); delete $3; }\n | specificsymbol '[' INTEGER ',' INTEGER ']' { $$ = pcode->createBitRange($1,(uint4)*$3,(uint4)*$5); delete $3, delete $5; }\n | USEROPSYM '(' paramlist ')' { $$ = pcode->createUserOp($1,$3); }\n ; \nsizedstar: '*' '[' SPACESYM ']' ':' INTEGER { $$ = new StarQuality; $$->size = *$6; delete $6; $$->id=ConstTpl($3->getSpace()); }\n | '*' '[' SPACESYM ']'\t{ $$ = new StarQuality; $$->size = 0; $$->id=ConstTpl($3->getSpace()); }\n | '*' ':' INTEGER\t\t{ $$ = new StarQuality; $$->size = *$3; delete $3; $$->id=ConstTpl(pcode->getDefaultSpace()); }\n | '*'\t\t\t\t{ $$ = new StarQuality; $$->size = 0; $$->id=ConstTpl(pcode->getDefaultSpace()); }\n ;\njumpdest: JUMPSYM\t\t{ VarnodeTpl *sym = $1->getVarnode(); $$ = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; }\n | INTEGER\t\t\t{ $$ = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::j_curspace_size)); delete $1; }\n | BADINTEGER { $$ = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); yyerror(\"Parsed integer is too big (overflow)\"); }\n | INTEGER '[' SPACESYM ']'\t{ AddrSpace *spc = $3->getSpace(); $$ = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete $1; }\n | label { $$ = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::j_relative,$1->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); $1->incrementRefCount(); }\n | STRING\t\t\t{ $$ = (VarnodeTpl *)0; string errmsg = \"Unknown jump destination: \"+*$1; delete $1; yyerror(errmsg.c_str()); YYERROR; }\n ;\nvarnode: specificsymbol\t\t{ $$ = $1->getVarnode(); }\n | integervarnode\t\t{ $$ = $1; }\n | STRING\t\t\t{ $$ = (VarnodeTpl *)0; string errmsg = \"Unknown varnode parameter: \"+*$1; delete $1; yyerror(errmsg.c_str()); YYERROR; }\n ;\nintegervarnode: INTEGER\t\t{ $$ = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,0)); delete $1; }\n | BADINTEGER { $$ = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); yyerror(\"Parsed integer is too big (overflow)\"); }\n | INTEGER ':' INTEGER\t\t{ $$ = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,*$3)); delete $1; delete $3; }\n | '&' varnode { $$ = pcode->addressOf($2,0); }\n | '&' ':' INTEGER varnode { $$ = pcode->addressOf($4,*$3); delete $3; }\n ;\nlhsvarnode: specificsymbol\t{ $$ = $1->getVarnode(); }\n | STRING\t\t\t{ $$ = (VarnodeTpl *)0; string errmsg = \"Unknown assignment varnode: \"+*$1; delete $1; yyerror(errmsg.c_str()); YYERROR; }\n ;\nlabel: '<' LABELSYM '>' { $$ = $2; }\n | '<' STRING '>' { $$ = pcode->defineLabel( $2 ); }\n ;\nspecificsymbol: VARSYM\t\t{ $$ = $1; }\n | OPERANDSYM\t\t\t{ $$ = $1; }\n | JUMPSYM\t\t\t{ $$ = $1; }\n ;\nparamlist: /* EMPTY */\t\t{ $$ = new vector; }\n | expr\t\t\t{ $$ = new vector; $$->push_back($1); }\n | paramlist ',' expr\t\t{ $$ = $1; $$->push_back($3); }\n ;\n%%\n\n#define IDENTREC_SIZE 46\nconst IdentRec PcodeLexer::idents[]= { // Sorted list of identifiers\n { \"!=\", OP_NOTEQUAL },\n { \"&&\", OP_BOOL_AND },\n { \"<<\", OP_LEFT },\n { \"<=\", OP_LESSEQUAL },\n { \"==\", OP_EQUAL },\n { \">=\", OP_GREATEQUAL },\n { \">>\", OP_RIGHT },\n { \"^^\", OP_BOOL_XOR },\n { \"||\", OP_BOOL_OR },\n { \"abs\", OP_ABS },\n { \"borrow\", OP_BORROW },\n { \"call\", CALL_KEY },\n { \"carry\", OP_CARRY },\n { \"ceil\", OP_CEIL },\n { \"f!=\", OP_FNOTEQUAL },\n { \"f*\", OP_FMULT },\n { \"f+\", OP_FADD },\n { \"f-\", OP_FSUB },\n { \"f/\", OP_FDIV },\n { \"f<\", OP_FLESS },\n { \"f<=\", OP_FLESSEQUAL },\n { \"f==\", OP_FEQUAL },\n { \"f>\", OP_FGREAT },\n { \"f>=\", OP_FGREATEQUAL },\n { \"float2float\", OP_FLOAT2FLOAT },\n { \"floor\", OP_FLOOR },\n { \"goto\", GOTO_KEY },\n { \"if\", IF_KEY },\n { \"int2float\", OP_INT2FLOAT },\n { \"local\", LOCAL_KEY },\n { \"nan\", OP_NAN },\n { \"return\", RETURN_KEY },\n { \"round\", OP_ROUND },\n { \"s%\", OP_SREM },\n { \"s/\", OP_SDIV },\n { \"s<\", OP_SLESS },\n { \"s<=\", OP_SLESSEQUAL },\n { \"s>\", OP_SGREAT },\n { \"s>=\", OP_SGREATEQUAL },\n { \"s>>\",OP_SRIGHT },\n { \"sborrow\", OP_SBORROW },\n { \"scarry\", OP_SCARRY },\n { \"sext\", OP_SEXT },\n { \"sqrt\", OP_SQRT },\n { \"trunc\", OP_TRUNC },\n { \"zext\", OP_ZEXT }\n};\n\nint4 PcodeLexer::findIdentifier(const string &str) const\n\n{\n int4 low = 0;\n int4 high = IDENTREC_SIZE-1;\n int4 comp;\n do {\n int4 targ = (low+high)/2;\n comp = str.compare(idents[targ].nm);\n if (comp < 0) \t\t// str comes before targ\n high = targ-1;\n else if (comp > 0)\t\t// str comes after targ\n low = targ + 1;\n else\n return targ;\n } while(low <= high);\n return -1;\n}\n\nint4 PcodeLexer::moveState(void)\n\n{\n switch(curstate) {\n case start:\n switch(curchar) {\n case '#':\n curstate = comment;\n return start;\n case '|':\n if (lookahead1 == '|') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '&':\n if (lookahead1 == '&') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '^':\n if (lookahead1 == '^') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '>':\n if ((lookahead1 == '>')||(lookahead1=='=')) {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '<':\n if ((lookahead1 == '<')||(lookahead1=='=')) {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '=':\n if (lookahead1 == '=') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '!':\n if (lookahead1 == '=') {\n\tstarttoken();\n\tcurstate = special2;\n\treturn start;\n }\n return punctuation;\n case '(':\n case ')':\n case ',':\n case ':':\n case '[':\n case ']':\n case ';':\n case '+':\n case '-':\n case '*':\n case '/':\n case '%':\n case '~':\n return punctuation;\n case 's':\n case 'f':\n if (curchar == 's') {\n\tif ((lookahead1 == '/')||(lookahead1=='%')) {\n\t starttoken();\n\t curstate = special2;\n\t return start;\n\t}\n\telse if (lookahead1 == '<') {\n\t starttoken();\n\t if (lookahead2 == '=')\n\t curstate = special3;\n\t else\n\t curstate = special2;\n\t return start;\n\t}\n\telse if (lookahead1 == '>') {\n\t starttoken();\n\t if ((lookahead2=='>')||(lookahead2=='='))\n\t curstate = special3;\n\t else\n\t curstate = special2;\n\t return start;\n\t}\n }\n else {\t\t\t// curchar == 'f'\n\tif ((lookahead1=='+')||(lookahead1=='-')||(lookahead1=='*')||(lookahead1=='/')) {\n\t starttoken();\n\t curstate = special2;\n\t return start;\n\t}\n\telse if (((lookahead1=='=')||(lookahead1=='!'))&&(lookahead2=='=')) {\n\t starttoken();\n\t curstate = special3;\n\t return start;\n\t}\n\telse if ((lookahead1=='<')||(lookahead1=='>')) {\n\t starttoken();\n\t if (lookahead2 == '=')\n\t curstate = special3;\n\t else\n\t curstate = special2;\n\t return start;\n\t}\n }\n // fall through here, treat 's' and 'f' as ordinary characters\n case 'a':\n case 'b':\n case 'c':\n case 'd':\n case 'e':\n case 'g':\n case 'h':\n case 'i':\n case 'j':\n case 'k':\n case 'l':\n case 'm':\n case 'n':\n case 'o':\n case 'p':\n case 'q':\n case 'r':\n case 't':\n case 'u':\n case 'v':\n case 'w':\n case 'x':\n case 'y':\n case 'z':\n case 'A':\n case 'B':\n case 'C':\n case 'D':\n case 'E':\n case 'F':\n case 'G':\n case 'H':\n case 'I':\n case 'J':\n case 'K':\n case 'L':\n case 'M':\n case 'N':\n case 'O':\n case 'P':\n case 'Q':\n case 'R':\n case 'S':\n case 'T':\n case 'U':\n case 'V':\n case 'W':\n case 'X':\n case 'Y':\n case 'Z':\n case '_':\n case '.':\n starttoken();\n if (isIdent(lookahead1)) {\n\tcurstate = identifier;\n\treturn start;\n }\n curstate = start;\n return identifier;\n case '0':\n starttoken();\n if (lookahead1 == 'x') {\n\tcurstate = hexstring;\n\treturn start;\n }\n if (isDec(lookahead1)) {\n\tcurstate = decstring;\n\treturn start;\n }\n curstate = start;\n return decstring;\n case '1':\n case '2':\n case '3':\n case '4':\n case '5':\n case '6':\n case '7':\n case '8':\n case '9':\n starttoken();\n if (isDec(lookahead1)) {\n\tcurstate = decstring;\n\treturn start;\n }\n curstate = start;\n return decstring;\n case '\\n':\n case ' ':\n case '\\t':\n case '\\v':\n case '\\r':\n return start;\t\t// Ignore whitespace\n case '\\0':\n curstate = endstream;\n return endstream;\n default:\n curstate = illegal;\n return illegal;\n }\n break;\n case special2:\n advancetoken();\n curstate = start;\n return identifier;\n case special3:\n advancetoken();\n curstate = special32;\n return start;\n case special32:\n advancetoken();\n curstate = start;\n return identifier;\n case comment:\n if (curchar == '\\n')\n curstate = start;\n else if (curchar == '\\0') {\n curstate = endstream;\n return endstream;\n }\n return start;\n case identifier:\n advancetoken();\n if (isIdent(lookahead1))\n return start;\n curstate = start;\n return identifier;\n case hexstring:\n advancetoken();\n if (isHex(lookahead1))\n return start;\n curstate = start;\n return hexstring;\n case decstring:\n advancetoken();\n if (isDec(lookahead1))\n return start;\n curstate = start;\n return decstring;\n default:\n curstate = endstream;\n }\n return endstream;\n}\n\nint4 PcodeLexer::getNextToken(void)\n\n{ // Will return either: identifier, punctuation, hexstring, decstring, endstream, or illegal\n // If identifier, hexstring, or decstring, curtoken will be filled with the characters\n int4 tok;\n do {\n curchar = lookahead1;\n lookahead1 = lookahead2;\n if (endofstream)\n lookahead2 = '\\0';\n else {\n s->get(lookahead2);\n if (!(*s)) {\n\tendofstream = true;\n\tlookahead2 = '\\0';\n }\n }\n tok = moveState();\n } while(tok == start);\n if (tok == identifier) {\n curtoken[tokpos] = '\\0';\t// Append null terminator\n curidentifier = curtoken;\n int4 num = findIdentifier(curidentifier);\n if (num < 0)\t\t\t// Not a keyword\n return STRING;\n return idents[num].id;\n }\n else if ((tok == hexstring)||(tok == decstring)) {\n curtoken[tokpos] = '\\0';\n istringstream s1(curtoken);\n s1.unsetf(ios::dec | ios::hex | ios::oct);\n s1 >> curnum;\n if (!s1)\n return BADINTEGER;\n return INTEGER;\n }\n else if (tok == endstream) {\n if (!endofstreamsent) {\n endofstreamsent = true;\n return ENDOFSTREAM;\t// Send 'official' end of stream token\n }\n return 0;\t\t\t// 0 means end of file to parser\n }\n else if (tok == illegal)\n return 0;\n return (int4)curchar;\n}\n\nvoid PcodeLexer::initialize(istream *t)\n\n{ // Set up for new lex\n s = t;\n curstate = start;\n tokpos = 0;\n endofstream = false;\n endofstreamsent = false;\n lookahead1 = 0;\n lookahead2 = 0;\n s->get(lookahead1);\t\t// Buffer the first two characters\n if (!(*s)) {\n endofstream = true;\n lookahead1 = 0;\n return;\n }\n s->get(lookahead2);\n if (!(*s)) {\n endofstream = true;\n lookahead2 = 0;\n return;\n }\n}\n\nuint4 PcodeSnippet::allocateTemp(void)\n\n{ // Allocate a variable in the unique space and return the offset\n uint4 res = tempbase;\n tempbase += 16;\n return res;\n}\n\nvoid PcodeSnippet::addSymbol(SleighSymbol *sym)\n\n{\n pair res;\n\n res = tree.insert( sym );\n if (!res.second) {\n reportError((const Location *)0,\"Duplicate symbol name: \"+sym->getName());\n delete sym;\t\t// Symbol is unattached to anything else\n }\n}\n\nvoid PcodeSnippet::clear(void)\n\n{ // Clear everything, prepare for a new parse against the same language\n SymbolTree::iterator iter,tmpiter;\n iter = tree.begin();\n while(iter != tree.end()) {\n SleighSymbol *sym = *iter;\n tmpiter = iter;\n ++iter;\t\t\t// Increment now, as node may be deleted\n if (sym->getType() != SleighSymbol::space_symbol) {\n delete sym;\t\t// Free any old local symbols\n tree.erase(tmpiter);\n }\n }\n if (result != (ConstructTpl *)0) {\n delete result;\n result = (ConstructTpl *)0;\n }\n // tempbase = 0;\n errorcount = 0;\n firsterror.clear();\n resetLabelCount();\n}\n\nPcodeSnippet::PcodeSnippet(const SleighBase *slgh)\n : PcodeCompile()\n{\n sleigh = slgh;\n tempbase = 0;\n errorcount = 0;\n result = (ConstructTpl *)0;\n setDefaultSpace(slgh->getDefaultCodeSpace());\n setConstantSpace(slgh->getConstantSpace());\n setUniqueSpace(slgh->getUniqueSpace());\n int4 num = slgh->numSpaces();\n for(int4 i=0;igetSpace(i);\n spacetype type = spc->getType();\n if ((type==IPTR_CONSTANT)||(type==IPTR_PROCESSOR)||(type==IPTR_SPACEBASE)||(type==IPTR_INTERNAL))\n tree.insert(new SpaceSymbol(spc));\n }\n addSymbol(new FlowDestSymbol(\"inst_dest\",slgh->getConstantSpace()));\n addSymbol(new FlowRefSymbol(\"inst_ref\",slgh->getConstantSpace()));\n}\n\nPcodeSnippet::~PcodeSnippet(void)\n\n{\n SymbolTree::iterator iter;\n for(iter=tree.begin();iter!=tree.end();++iter)\n delete *iter;\t\t// Free ALL temporary symbols\n if (result != (ConstructTpl *)0) {\n delete result;\n result = (ConstructTpl *)0;\n }\n}\n\nvoid PcodeSnippet::reportError(const Location *loc, const string &msg)\n\n{\n if (errorcount == 0)\n firsterror = msg;\n errorcount += 1;\n}\n\nint4 PcodeSnippet::lex(void)\n\n{\n int4 tok = lexer.getNextToken();\n if (tok == STRING) {\n SleighSymbol *sym;\n SleighSymbol tmpsym(lexer.getIdentifier());\n SymbolTree::const_iterator iter = tree.find(&tmpsym);\n if (iter != tree.end())\n sym = *iter;\t\t// Found a local symbol\n else\n sym = sleigh->findSymbol(lexer.getIdentifier());\n if (sym != (SleighSymbol *)0) {\n switch(sym->getType()) {\n case SleighSymbol::space_symbol:\n\tyylval.spacesym = (SpaceSymbol *)sym;\n\treturn SPACESYM;\n case SleighSymbol::userop_symbol:\n\tyylval.useropsym = (UserOpSymbol *)sym;\n\treturn USEROPSYM;\n case SleighSymbol::varnode_symbol:\n\tyylval.varsym = (VarnodeSymbol *)sym;\n\treturn VARSYM;\n case SleighSymbol::operand_symbol:\n\tyylval.operandsym = (OperandSymbol *)sym;\n\treturn OPERANDSYM;\n case SleighSymbol::start_symbol:\n case SleighSymbol::end_symbol:\n case SleighSymbol::next2_symbol:\n case SleighSymbol::flowdest_symbol:\n case SleighSymbol::flowref_symbol:\n\tyylval.specsym = (SpecificSymbol *)sym;\n\treturn JUMPSYM;\n case SleighSymbol::label_symbol:\n\tyylval.labelsym = (LabelSymbol *)sym;\n\treturn LABELSYM;\n case SleighSymbol::dummy_symbol:\n\tbreak;\n default:\n\t// The translator may have other symbols in it that we don't want visible in the snippet compiler\n\tbreak;\n }\n }\n yylval.str = new string(lexer.getIdentifier());\n return STRING;\n }\n if (tok == INTEGER) {\n yylval.i = new uintb(lexer.getNumber());\n return INTEGER;\n }\n return tok;\n}\n\n bool PcodeSnippet::parseStream(istream &s)\n\n{\n lexer.initialize(&s);\n pcode = this;\t\t\t// Setup global object for yyparse\n int4 res = yyparse();\n if (res != 0) {\n reportError((const Location *)0,\"Syntax error\");\n return false;\n }\n if (!PcodeCompile::propagateSize(result)) {\n reportError((const Location *)0,\"Could not resolve at least 1 variable size\");\n return false;\n }\n return true;\n}\n\nvoid PcodeSnippet::addOperand(const string &name,int4 index)\n\n{ // Add an operand symbol for this snippet\n OperandSymbol *sym = new OperandSymbol(name,index,(Constructor *)0);\n addSymbol(sym);\n}\n\nint pcodelex(void) {\n return pcode->lex();\n}\n\nint pcodeerror(const char *s)\n\n{\n pcode->reportError((const Location *)0,s);\n return 0;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/pcoderaw.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"pcoderaw.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\n/// Build this VarnodeData from an \\, \\, or \\ element.\n/// \\param decoder is the stream decoder\nvoid VarnodeData::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement();\n decodeFromAttributes(decoder);\n decoder.closeElement(elemId);\n}\n\n/// Collect attributes for the VarnodeData possibly from amidst other attributes\n/// \\param decoder is the stream decoder\nvoid VarnodeData::decodeFromAttributes(Decoder &decoder)\n\n{\n space = (AddrSpace *)0;\n size = 0;\n for(;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0)\n break;\t\t// Its possible to have no attributes in an tag\n if (attribId == ATTRIB_SPACE) {\n space = decoder.readSpace();\n decoder.rewindAttributes();\n offset = space->decodeAttributes(decoder,size);\n break;\n }\n else if (attribId == ATTRIB_NAME) {\n const Translate *trans = decoder.getAddrSpaceManager()->getDefaultCodeSpace()->getTrans();\n const VarnodeData &point(trans->getRegister(decoder.readString()));\n *this = point;\n break;\n }\n }\n}\n\n/// Return \\b true, if \\b this, as an address range, contains the other address range\n/// \\param op2 is the other VarnodeData to test for containment\n/// \\return \\b true if \\b this contains the other\nbool VarnodeData::contains(const VarnodeData &op2) const\n\n{\n if (space != op2.space) return false;\n if (op2.offset < offset) return false;\n if ((offset + (size-1)) < (op2.offset + (op2.size-1))) return false;\n return true;\n}\n\n/// If \\b this and \\b lo form a contiguous range of bytes, where \\b this makes up the most significant\n/// bytes and \\b lo makes up the least significant bytes, return \\b true.\n/// \\param lo is the given VarnodeData to compare with\n/// \\return \\b true if the two byte ranges are contiguous and in order\nbool VarnodeData::isContiguous(const VarnodeData &lo) const\n\n{\n if (space != lo.space) return false;\n if (space->isBigEndian()) {\n uintb nextoff = space->wrapOffset(offset+size);\n if (nextoff == lo.offset) return true;\n }\n else {\n uintb nextoff = space->wrapOffset(lo.offset+lo.size);\n if (nextoff == offset) return true;\n }\n return false;\n}\n\n/// This assumes the \\ element is already open.\n/// Decode info suitable for call to PcodeEmit::dump. The output pointer is changed to null if there\n/// is no output for this op, otherwise the existing pointer is used to store the output.\n/// \\param decoder is the stream decoder\n/// \\param isize is the (preparsed) number of input parameters for the p-code op\n/// \\param invar is an array of storage for the input Varnodes\n/// \\param outvar is a (handle) to the storage for the output Varnode\n/// \\return the p-code op OpCode\nOpCode PcodeOpRaw::decode(Decoder &decoder,int4 isize,VarnodeData *invar,VarnodeData **outvar)\n\n{\n OpCode opcode = (OpCode)decoder.readSignedInteger(ATTRIB_CODE);\n uint4 subId = decoder.peekElement();\n if (subId == ELEM_VOID) {\n decoder.openElement();\n decoder.closeElement(subId);\n *outvar = (VarnodeData *)0;\n }\n else {\n (*outvar)->decode(decoder);\n }\n for(int4 i=0;igetConstantSpace();\n invar[i].offset = (uintb)(uintp)decoder.readSpace(ATTRIB_NAME);\n invar[i].size = sizeof(void *);\n decoder.closeElement(subId);\n }\n else\n invar[i].decode(decoder);\n }\n return opcode;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/pcoderaw.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file pcoderaw.hh\n/// \\brief Raw descriptions of varnodes and p-code ops\n#ifndef __PCODERAW_HH__\n#define __PCODERAW_HH__\n\n#include \"address.hh\"\n#include \"opbehavior.hh\"\n\nnamespace ghidra {\n\n/// \\brief Data defining a specific memory location\n///\n/// Within the decompiler's model of a processor, any register,\n/// memory location, or other variable can always be represented\n/// as an address space, an offset within the space, and the\n/// size of the sequence of bytes. This is more commonly referred\n/// to as a Varnode, but this is a bare-bones container\n/// for the data that doesn't have the cached attributes and\n/// the dataflow links of the Varnode within its syntax tree.\nstruct VarnodeData {\n AddrSpace *space;\t\t///< The address space\n uintb offset;\t\t\t///< The offset within the space\n uint4 size; ///< The number of bytes in the location\n bool operator<(const VarnodeData &op2) const; ///< An ordering for VarnodeData\n bool operator==(const VarnodeData &op2) const; ///< Compare for equality\n bool operator!=(const VarnodeData &op2) const; ///< Compare for inequality\n\n /// Get the location of the varnode as an address\n Address getAddr(void) const;\n\n /// Treat \\b this as a constant and recover encoded address space\n AddrSpace *getSpaceFromConst(void) const;\n\n /// Recover this object from a stream\n void decode(Decoder &decoder);\n\n /// Recover \\b this object from attributes of the current open element\n void decodeFromAttributes(Decoder &decoder);\n\n /// Does \\b this container another given VarnodeData\n bool contains(const VarnodeData &op2) const;\n\n /// Is \\b this contiguous (as the most significant piece) with the given VarnodeData\n bool isContiguous(const VarnodeData &lo) const;\n};\n\n/// VarnodeData can be sorted in terms of the space its in\n/// (the space's \\e index), the offset within the space,\n/// and finally by the size.\n/// \\param op2 is the object being compared to\n/// \\return true if \\e this is less than \\e op2\ninline bool VarnodeData::operator<(const VarnodeData &op2) const {\n if (space != op2.space) return (space->getIndex() < op2.space->getIndex());\n if (offset != op2.offset) return (offset < op2.offset);\n return (size > op2.size);\t// BIG sizes come first\n}\n\n/// Compare VarnodeData for equality. The space, offset, and size\n/// must all be exactly equal\n/// \\param op2 is the object being compared to\n/// \\return true if \\e this is equal to \\e op2\ninline bool VarnodeData::operator==(const VarnodeData &op2) const {\n if (space != op2.space) return false;\n if (offset != op2.offset) return false;\n return (size == op2.size);\n}\n\n/// Compare VarnodeData for inequality. If either the space,\n/// offset, or size is not equal, return \\b true.\n/// \\param op2 is the object being compared to\n/// \\return true if \\e this is not equal to \\e op2\ninline bool VarnodeData::operator!=(const VarnodeData &op2) const {\n if (space != op2.space) return true;\n if (offset != op2.offset) return true;\n return (size != op2.size);\n}\n\n/// This is a convenience function to construct a full Address from the\n/// VarnodeData's address space and offset\n/// \\return the address of the varnode\ninline Address VarnodeData::getAddr(void) const {\n return Address(space,offset);\n}\n\n/// \\return the encoded AddrSpace\ninline AddrSpace *VarnodeData::getSpaceFromConst(void) const {\n return (AddrSpace *)(uintp)offset;\n}\n\n/// \\brief A low-level representation of a single pcode operation\n///\n/// This is just the minimum amount of data to represent a pcode operation\n/// An opcode, sequence number, optional output varnode\n/// and input varnodes\nclass PcodeOpRaw {\n OpBehavior *behave;\t\t///< The opcode for this operation\n SeqNum seq;\t ///< Identifying address and index of this operation\n VarnodeData *out;\t\t///< Output varnode triple\n vector in;\t///< Raw varnode inputs to this op\npublic:\n void setBehavior(OpBehavior *be); ///< Set the opcode for this op\n OpBehavior *getBehavior(void) const; ///< Retrieve the behavior for this op\n OpCode getOpcode(void) const;\t///< Get the opcode for this op\n void setSeqNum(const Address &a,uintm b); ///< Set the sequence number\n const SeqNum &getSeqNum(void) const; ///< Retrieve the sequence number\n const Address &getAddr(void) const; ///< Get address of this operation\n void setOutput(VarnodeData *o); ///< Set the output varnode for this op\n VarnodeData *getOutput(void) const; ///< Retrieve the output varnode for this op\n void addInput(VarnodeData *i); ///< Add an additional input varnode to this op\n void clearInputs(void);\t///< Remove all input varnodes to this op\n int4 numInput(void) const;\t///< Get the number of input varnodes to this op\n VarnodeData *getInput(int4 i) const; ///< Get the i-th input varnode for this op\n\n /// \\brief Decode the raw OpCode and input/output Varnode data for a PcodeOp\n static OpCode decode(Decoder &decoder,int4 isize,VarnodeData *invar,VarnodeData **outvar);\n};\n\n/// The core behavior for this operation is controlled by an OpBehavior object\n/// which knows how output is determined given inputs. This routine sets that object\n/// \\param be is the behavior object\ninline void PcodeOpRaw::setBehavior(OpBehavior *be)\n\n{\n behave = be;\n}\n\n/// Get the underlying behavior object for this pcode operation. From this\n/// object you can determine how the object evaluates inputs to get the output\n/// \\return the behavior object\ninline OpBehavior *PcodeOpRaw::getBehavior(void) const\n\n{\n return behave;\n}\n\n/// The possible types of pcode operations are enumerated by OpCode\n/// This routine retrieves the enumeration value for this particular op\n/// \\return the opcode value\ninline OpCode PcodeOpRaw::getOpcode(void) const\n\n{\n return behave->getOpcode();\n}\n\n/// Every pcode operation has a \\b sequence \\b number\n/// which associates the operation with the address of the machine instruction\n/// being translated and an order number which provides an index for this\n/// particular operation within the entire translation of the machine instruction\n/// \\param a is the instruction address\n/// \\param b is the order number\ninline void PcodeOpRaw::setSeqNum(const Address &a,uintm b)\n\n{\n seq = SeqNum(a,b);\n}\n\n/// Every pcode operation has a \\b sequence \\b number which associates\n/// the operation with the address of the machine instruction being translated\n/// and an index number for this operation within the translation.\n/// \\return a reference to the sequence number\ninline const SeqNum &PcodeOpRaw::getSeqNum(void) const\n\n{\n return seq;\n}\n\n/// This is a convenience function to get the address of the machine instruction\n/// (of which this pcode op is a translation)\n/// \\return the machine instruction address\ninline const Address &PcodeOpRaw::getAddr(void) const\n\n{\n return seq.getAddr();\n}\n\n/// Most pcode operations output to a varnode. This routine sets what that varnode is.\n/// \\param o is the varnode to set as output\ninline void PcodeOpRaw::setOutput(VarnodeData *o)\n\n{\n out = o;\n}\n\n/// Most pcode operations have an output varnode. This routine retrieves that varnode.\n/// \\return the output varnode or \\b null if there is no output\ninline VarnodeData *PcodeOpRaw::getOutput(void) const\n\n{\n return out;\n}\n\n/// A PcodeOpRaw is initially created with no input varnodes. Inputs are added with this method.\n/// Varnodes are added in order, so the first addInput call creates input 0, for example.\n/// \\param i is the varnode to be added as input\ninline void PcodeOpRaw::addInput(VarnodeData *i)\n\n{\n in.push_back(i);\n}\n\n/// If the inputs to a pcode operation need to be changed, this routine clears the existing\n/// inputs so new ones can be added.\ninline void PcodeOpRaw::clearInputs(void)\n\n{\n in.clear();\n}\n\n/// \\return the number of inputs\ninline int4 PcodeOpRaw::numInput(void) const\n\n{\n return in.size();\n}\n\n/// Input varnodes are indexed starting at 0. This retrieves the input varnode by index.\n/// The index \\e must be in range, or unpredicatable behavior will result. Use the numInput method\n/// to get the number of inputs.\n/// \\param i is the index of the desired input\n/// \\return the desired input varnode\ninline VarnodeData *PcodeOpRaw::getInput(int4 i) const\n\n{\n return in[i];\n}\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/semantics.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"semantics.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nConstTpl::ConstTpl(const_type tp)\n\n{\t\t\t\t// Constructor for relative jump constants and uniques\n type = tp;\n}\n\nConstTpl::ConstTpl(const_type tp,uintb val)\n\n{\t\t\t\t// Constructor for real constants\n type = tp;\n value_real = val;\n value.handle_index = 0;\n select = v_space;\n}\n\nConstTpl::ConstTpl(const_type tp,int4 ht,v_field vf)\n\n{\t\t\t\t// Constructor for handle constant\n type = handle;\n value.handle_index = ht;\n select = vf;\n value_real = 0;\n}\n\nConstTpl::ConstTpl(const_type tp,int4 ht,v_field vf,uintb plus)\n\n{\n type = handle;\n value.handle_index = ht;\n select = vf;\n value_real = plus;\n}\n\nConstTpl::ConstTpl(AddrSpace *sid)\n\n{\n type = spaceid;\n value.spaceid = sid;\n}\n\nbool ConstTpl::isConstSpace(void) const\n\n{\n if (type==spaceid)\n return (value.spaceid->getType()==IPTR_CONSTANT);\n return false;\n}\n\nbool ConstTpl::isUniqueSpace(void) const\n\n{\n if (type==spaceid)\n return (value.spaceid->getType()==IPTR_INTERNAL);\n return false;\n}\n\nbool ConstTpl::operator==(const ConstTpl &op2) const\n\n{\n if (type != op2.type) return false;\n switch(type) {\n case real:\n return (value_real == op2.value_real);\n case handle:\n if (value.handle_index != op2.value.handle_index) return false;\n if (select != op2.select) return false;\n break;\n case spaceid:\n return (value.spaceid == op2.value.spaceid);\n default:\t\t\t// Nothing additional to compare\n break;\n }\n return true;\n}\n\nbool ConstTpl::operator<(const ConstTpl &op2) const\n\n{\n if (type != op2.type) return (type < op2.type);\n switch(type) {\n case real:\n return (value_real < op2.value_real);\n case handle:\n if (value.handle_index != op2.value.handle_index)\n return (value.handle_index < op2.value.handle_index);\n if (select != op2.select) return (select < op2.select);\n break;\n case spaceid:\n return (value.spaceid < op2.value.spaceid);\n default:\t\t\t// Nothing additional to compare\n break;\n }\n return false;\n}\n\nuintb ConstTpl::fix(const ParserWalker &walker) const\n\n{ // Get the value of the ConstTpl in context\n // NOTE: if the property is dynamic this returns the property\n // of the temporary storage\n switch(type) {\n case j_start:\n return walker.getAddr().getOffset(); // Fill in starting address placeholder with real address\n case j_next:\n return walker.getNaddr().getOffset(); // Fill in next address placeholder with real address\n case j_next2:\n return walker.getN2addr().getOffset(); // Fill in next2 address placeholder with real address\n case j_flowref:\n return walker.getRefAddr().getOffset();\n case j_flowref_size:\n return walker.getRefAddr().getAddrSize();\n case j_flowdest:\n return walker.getDestAddr().getOffset();\n case j_flowdest_size:\n return walker.getDestAddr().getAddrSize();\n case j_curspace_size:\n return walker.getCurSpace()->getAddrSize();\n case j_curspace:\n return (uintb)(uintp)walker.getCurSpace();\n case handle:\n {\n const FixedHandle &hand(walker.getFixedHandle(value.handle_index));\n switch(select) {\n case v_space:\n\tif (hand.offset_space == (AddrSpace *)0)\n\t return (uintb)(uintp)hand.space;\n\treturn (uintb)(uintp)hand.temp_space;\n case v_offset:\n\tif (hand.offset_space==(AddrSpace *)0)\n\t return hand.offset_offset;\n\treturn hand.temp_offset;\n case v_size:\n\treturn hand.size;\n case v_offset_plus:\n\tif (hand.space != walker.getConstSpace()) { // If we are not a constant\n\t if (hand.offset_space==(AddrSpace *)0)\n\t return hand.offset_offset + (value_real&0xffff); // Adjust offset by truncation amount\n\t return hand.temp_offset + (value_real&0xffff);\n\t}\n\telse {\t\t\t// If we are a constant, we want to return a shifted value\n\t uintb val;\n\t if (hand.offset_space==(AddrSpace *)0)\n\t val = hand.offset_offset;\n\t else\n\t val = hand.temp_offset;\n\t val >>= 8 * (value_real>>16);\n\t return val;\n\t}\n }\n break;\n }\n case j_relative:\n case real:\n return value_real;\n case spaceid:\n return (uintb)(uintp)value.spaceid;\n }\n return 0;\t\t\t// Should never reach here\n}\n\nAddrSpace *ConstTpl::fixSpace(const ParserWalker &walker) const\n\n{\t\t\t\t// Get the value of the ConstTpl in context\n\t\t\t\t// when we know it is a space\n switch(type) {\n case j_curspace:\n return walker.getCurSpace();\n case handle:\n {\n const FixedHandle &hand(walker.getFixedHandle(value.handle_index));\n switch(select) {\n case v_space:\n\tif (hand.offset_space == (AddrSpace *)0)\n\t return hand.space;\n\treturn hand.temp_space;\n default:\n\tbreak;\n }\n break;\n }\n case spaceid:\n return value.spaceid;\n case j_flowref:\n return walker.getRefAddr().getSpace();\n default:\n break;\n }\n throw LowlevelError(\"ConstTpl is not a spaceid as expected\");\n}\n\nvoid ConstTpl::fillinSpace(FixedHandle &hand,const ParserWalker &walker) const\n\n{ // Fill in the space portion of a FixedHandle, base on this ConstTpl\n switch(type) {\n case j_curspace:\n hand.space = walker.getCurSpace();\n return;\n case handle:\n {\n const FixedHandle &otherhand(walker.getFixedHandle(value.handle_index));\n switch(select) {\n case v_space:\n\thand.space = otherhand.space;\n\treturn;\n default:\n\tbreak;\n }\n break;\n }\n case spaceid:\n hand.space = value.spaceid;\n return;\n default:\n break;\n }\n throw LowlevelError(\"ConstTpl is not a spaceid as expected\");\n}\n\nvoid ConstTpl::fillinOffset(FixedHandle &hand,const ParserWalker &walker) const\n\n{ // Fillin the offset portion of a FixedHandle, based on this ConstTpl\n // If the offset value is dynamic, indicate this in the handle\n // we don't just fill in the temporary variable offset\n // we assume hand.space is already filled in\n if (type == handle) {\n const FixedHandle &otherhand(walker.getFixedHandle(value.handle_index));\n hand.offset_space = otherhand.offset_space;\n hand.offset_offset = otherhand.offset_offset;\n hand.offset_size = otherhand.offset_size;\n hand.temp_space = otherhand.temp_space;\n hand.temp_offset = otherhand.temp_offset;\n }\n else {\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = hand.space->wrapOffset(fix(walker));\n }\n}\n\nvoid ConstTpl::transfer(const vector ¶ms)\n\n{\t\t\t\t// Replace old handles with new handles\n if (type != handle) return;\n HandleTpl *newhandle = params[value.handle_index];\n\n switch(select) {\n case v_space:\n *this = newhandle->getSpace();\n break;\n case v_offset:\n *this = newhandle->getPtrOffset();\n break;\n case v_offset_plus:\n {\n uintb tmp = value_real;\n *this = newhandle->getPtrOffset();\n if (type == real) {\n\tvalue_real += (tmp&0xffff);\n }\n else if ((type == handle)&&(select == v_offset)) {\n\tselect = v_offset_plus;\n\tvalue_real = tmp;\n }\n else\n\tthrow LowlevelError(\"Cannot truncate macro input in this way\");\n break;\n }\n case v_size:\n *this = newhandle->getSize();\n break;\n }\n}\n\nvoid ConstTpl::changeHandleIndex(const vector &handmap)\n\n{\n if (type == handle)\n value.handle_index = handmap[value.handle_index];\n}\n\nvoid ConstTpl::encode(Encoder &encoder) const\n\n{\n switch(type) {\n case real:\n encoder.openElement(sla::ELEM_CONST_REAL);\n encoder.writeUnsignedInteger(sla::ATTRIB_VAL, value_real);\n encoder.closeElement(sla::ELEM_CONST_REAL);\n break;\n case handle:\n encoder.openElement(sla::ELEM_CONST_HANDLE);\n encoder.writeSignedInteger(sla::ATTRIB_VAL, value.handle_index);\n encoder.writeSignedInteger(sla::ATTRIB_S, select);\n if (select == v_offset_plus)\n encoder.writeUnsignedInteger(sla::ATTRIB_PLUS, value_real);\n encoder.closeElement(sla::ELEM_CONST_HANDLE);\n break;\n case j_start:\n encoder.openElement(sla::ELEM_CONST_START);\n encoder.closeElement(sla::ELEM_CONST_START);\n break;\n case j_next:\n encoder.openElement(sla::ELEM_CONST_NEXT);\n encoder.closeElement(sla::ELEM_CONST_NEXT);\n break;\n case j_next2:\n encoder.openElement(sla::ELEM_CONST_NEXT2);\n encoder.closeElement(sla::ELEM_CONST_NEXT2);\n break;\n case j_curspace:\n encoder.openElement(sla::ELEM_CONST_CURSPACE);\n encoder.closeElement(sla::ELEM_CONST_CURSPACE);\n break;\n case j_curspace_size:\n encoder.openElement(sla::ELEM_CONST_CURSPACE_SIZE);\n encoder.closeElement(sla::ELEM_CONST_CURSPACE_SIZE);\n break;\n case spaceid:\n encoder.openElement(sla::ELEM_CONST_SPACEID);\n encoder.writeSpace(sla::ATTRIB_SPACE, value.spaceid);\n encoder.closeElement(sla::ELEM_CONST_SPACEID);\n break;\n case j_relative:\n encoder.openElement(sla::ELEM_CONST_RELATIVE);\n encoder.writeUnsignedInteger(sla::ATTRIB_VAL, value_real);\n encoder.closeElement(sla::ELEM_CONST_RELATIVE);\n break;\n case j_flowref:\n encoder.openElement(sla::ELEM_CONST_FLOWREF);\n encoder.closeElement(sla::ELEM_CONST_FLOWREF);\n break;\n case j_flowref_size:\n encoder.openElement(sla::ELEM_CONST_FLOWREF_SIZE);\n encoder.closeElement(sla::ELEM_CONST_FLOWREF_SIZE);\n break;\n case j_flowdest:\n encoder.openElement(sla::ELEM_CONST_FLOWDEST);\n encoder.closeElement(sla::ELEM_CONST_FLOWDEST);\n break;\n case j_flowdest_size:\n encoder.openElement(sla::ELEM_CONST_FLOWDEST_SIZE);\n encoder.closeElement(sla::ELEM_CONST_FLOWDEST_SIZE);\n break;\n }\n}\n\nvoid ConstTpl::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement();\n if (el == sla::ELEM_CONST_REAL) {\n type = real;\n value_real = decoder.readUnsignedInteger(sla::ATTRIB_VAL);\n }\n else if (el == sla::ELEM_CONST_HANDLE) {\n type = handle;\n value.handle_index = decoder.readSignedInteger(sla::ATTRIB_VAL);\n uint4 selectInt = decoder.readSignedInteger(sla::ATTRIB_S);\n if (selectInt > v_offset_plus)\n throw DecoderError(\"Bad handle selector encoding\");\n select = (v_field)selectInt;\n if (select == v_offset_plus) {\n value_real = decoder.readUnsignedInteger(sla::ATTRIB_PLUS);\n }\n }\n else if (el == sla::ELEM_CONST_START) {\n type = j_start;\n }\n else if (el == sla::ELEM_CONST_NEXT) {\n type = j_next;\n }\n else if (el == sla::ELEM_CONST_NEXT2) {\n type = j_next2;\n }\n else if (el == sla::ELEM_CONST_CURSPACE) {\n type = j_curspace;\n }\n else if (el == sla::ELEM_CONST_CURSPACE_SIZE) {\n type = j_curspace_size;\n }\n else if (el == sla::ELEM_CONST_SPACEID) {\n type = spaceid;\n value.spaceid = decoder.readSpace(sla::ATTRIB_SPACE);\n }\n else if (el == sla::ELEM_CONST_RELATIVE) {\n type = j_relative;\n value_real = decoder.readUnsignedInteger(sla::ATTRIB_VAL);\n }\n else if (el == sla::ELEM_CONST_FLOWREF) {\n type = j_flowref;\n }\n else if (el == sla::ELEM_CONST_FLOWREF_SIZE) {\n type = j_flowref_size;\n }\n else if (el == sla::ELEM_CONST_FLOWDEST) {\n type = j_flowdest;\n }\n else if (el == sla::ELEM_CONST_FLOWDEST_SIZE) {\n type = j_flowdest_size;\n }\n else\n throw LowlevelError(\"Bad constant type\");\n decoder.closeElement(el);\n}\n\nVarnodeTpl::VarnodeTpl(int4 hand,bool zerosize) :\n space(ConstTpl::handle,hand,ConstTpl::v_space), offset(ConstTpl::handle,hand,ConstTpl::v_offset), size(ConstTpl::handle,hand,ConstTpl::v_size)\n{\t\t\t\t// Varnode built from a handle\n\t\t\t\t// if zerosize is true, set the size constant to zero\n if (zerosize)\n size = ConstTpl(ConstTpl::real,0);\n unnamed_flag = false;\n}\n\nVarnodeTpl::VarnodeTpl(const ConstTpl &sp,const ConstTpl &off,const ConstTpl &sz) :\n space(sp), offset(off), size(sz)\n\n{\n unnamed_flag = false;\n}\n\nVarnodeTpl::VarnodeTpl(const VarnodeTpl &vn)\n : space(vn.space), offset(vn.offset), size(vn.size)\n{\t\t\t\t// A clone of the VarnodeTpl\n unnamed_flag = vn.unnamed_flag;\n}\n\nbool VarnodeTpl::isLocalTemp(void) const\n\n{\n if (space.getType() != ConstTpl::spaceid) return false;\n if (space.getSpace()->getType()!=IPTR_INTERNAL) return false;\n return true;\n}\n\nbool VarnodeTpl::isDynamic(const ParserWalker &walker) const\n\n{\n if (offset.getType()!=ConstTpl::handle) return false;\n\t\t\t\t// Technically we should probably check all three\n\t\t\t\t// ConstTpls for dynamic handles, but in all cases\n\t\t\t\t// if there is any dynamic piece then the offset is\n const FixedHandle &hand(walker.getFixedHandle(offset.getHandleIndex()));\n return (hand.offset_space != (AddrSpace *)0);\n}\n\nint4 VarnodeTpl::transfer(const vector ¶ms)\n\n{\n bool doesOffsetPlus = false;\n int4 handleIndex;\n int4 plus;\n if ((offset.getType() == ConstTpl::handle)&&(offset.getSelect()==ConstTpl::v_offset_plus)) {\n handleIndex = offset.getHandleIndex();\n plus = (int4)offset.getReal();\n doesOffsetPlus = true;\n }\n space.transfer(params);\n offset.transfer(params);\n size.transfer(params);\n if (doesOffsetPlus) {\n if (isLocalTemp())\n return plus;\t\t// A positive number indicates truncation of a local temp\n if (params[handleIndex]->getSize().isZero())\n return plus;\t\t// or a zerosize object\n }\n return -1;\n}\n\nvoid VarnodeTpl::changeHandleIndex(const vector &handmap)\n\n{\n space.changeHandleIndex(handmap);\n offset.changeHandleIndex(handmap);\n size.changeHandleIndex(handmap);\n}\n\nbool VarnodeTpl::adjustTruncation(int4 sz,bool isbigendian)\n\n{ // We know this->offset is an offset_plus, check that the truncation is in bounds (given -sz-)\n // adjust plus for endianness if necessary\n // return true if truncation is in bounds\n if (size.getType() != ConstTpl::real)\n return false;\n int4 numbytes = (int4) size.getReal();\n int4 byteoffset = (int4) offset.getReal();\n if (numbytes + byteoffset > sz) return false;\n\n // Encode the original truncation amount with the plus value\n uintb val = byteoffset;\n val <<= 16;\n if (isbigendian) {\n val |= (uintb)(sz - (numbytes+byteoffset));\n }\n else {\n val |= (uintb) byteoffset;\n }\n \n\n offset = ConstTpl(ConstTpl::handle,offset.getHandleIndex(),ConstTpl::v_offset_plus,val);\n return true;\n}\n\nvoid VarnodeTpl::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VARNODE_TPL);\n space.encode(encoder);\n offset.encode(encoder);\n size.encode(encoder);\n encoder.closeElement(sla::ELEM_VARNODE_TPL);\n}\n\nvoid VarnodeTpl::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_VARNODE_TPL);\n space.decode(decoder);\n offset.decode(decoder);\n size.decode(decoder);\n decoder.closeElement(el);\n}\n\nbool VarnodeTpl::operator==(const VarnodeTpl &op2) const\n\n{\n return space==op2.space && offset==op2.offset && size==op2.size;\n}\n\nbool VarnodeTpl::operator!=(const VarnodeTpl &op2) const\n\n{\n return !(*this == op2);\n}\n\nbool VarnodeTpl::operator<(const VarnodeTpl &op2) const\n\n{\n if (!(space==op2.space)) return (spacegetSpace();\n size = vn->getSize();\n ptrspace = ConstTpl(ConstTpl::real,0);\n ptroffset = vn->getOffset();\n}\n\nHandleTpl::HandleTpl(const ConstTpl &spc,const ConstTpl &sz,const VarnodeTpl *vn,\n\t\t AddrSpace *t_space,uintb t_offset) :\n space(spc), size(sz), ptrspace(vn->getSpace()), ptroffset(vn->getOffset()), ptrsize(vn->getSize()),\n temp_space(t_space), temp_offset(ConstTpl::real,t_offset)\n{\t\t\t\t// Build handle to thing being pointed at by -vn-\n}\n\nvoid HandleTpl::fix(FixedHandle &hand,const ParserWalker &walker) const\n\n{\n if (ptrspace.getType() == ConstTpl::real) {\n // The export is unstarred, but this doesn't mean the varnode\n // being exported isn't dynamic\n space.fillinSpace(hand,walker);\n hand.size = size.fix(walker);\n ptroffset.fillinOffset(hand,walker);\n }\n else {\n hand.space = space.fixSpace(walker);\n hand.size = size.fix(walker);\n hand.offset_offset = ptroffset.fix(walker);\n hand.offset_space = ptrspace.fixSpace(walker);\n if (hand.offset_space->getType()==IPTR_CONSTANT) {\n\t\t\t\t// Handle could have been dynamic but wasn't\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = AddrSpace::addressToByte(hand.offset_offset,hand.space->getWordSize());\n hand.offset_offset = hand.space->wrapOffset(hand.offset_offset);\n }\n else {\n hand.offset_size = ptrsize.fix(walker);\n hand.temp_space = temp_space.fixSpace(walker);\n hand.temp_offset = temp_offset.fix(walker);\n }\n }\n}\n\nvoid HandleTpl::changeHandleIndex(const vector &handmap)\n\n{\n space.changeHandleIndex(handmap);\n size.changeHandleIndex(handmap);\n ptrspace.changeHandleIndex(handmap);\n ptroffset.changeHandleIndex(handmap);\n ptrsize.changeHandleIndex(handmap);\n temp_space.changeHandleIndex(handmap);\n temp_offset.changeHandleIndex(handmap);\n}\n\nvoid HandleTpl::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_HANDLE_TPL);\n space.encode(encoder);\n size.encode(encoder);\n ptrspace.encode(encoder);\n ptroffset.encode(encoder);\n ptrsize.encode(encoder);\n temp_space.encode(encoder);\n temp_offset.encode(encoder);\n encoder.closeElement(sla::ELEM_HANDLE_TPL);\n}\n\nvoid HandleTpl::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_HANDLE_TPL);\n space.decode(decoder);\n size.decode(decoder);\n ptrspace.decode(decoder);\n ptroffset.decode(decoder);\n ptrsize.decode(decoder);\n temp_space.decode(decoder);\n temp_offset.decode(decoder);\n decoder.closeElement(el);\n}\n\nOpTpl::~OpTpl(void)\n\n{\t\t\t\t// An OpTpl owns its varnode_tpls\n if (output != (VarnodeTpl *)0)\n delete output;\n vector::iterator iter;\n for(iter=input.begin();iter!=input.end();++iter)\n delete *iter;\n}\n\nbool OpTpl::isZeroSize(void) const\n\n{\t\t\t\t// Return if any input or output has zero size\n vector::const_iterator iter;\n\n if (output != (VarnodeTpl *)0)\n if (output->isZeroSize()) return true;\n for(iter=input.begin();iter!=input.end();++iter)\n if ((*iter)->isZeroSize()) return true;\n return false;\n}\n\nvoid OpTpl::removeInput(int4 index)\n\n{ // Remove the indicated input\n delete input[index];\n for(int4 i=index;i &handmap)\n\n{\n if (output != (VarnodeTpl *)0)\n output->changeHandleIndex(handmap);\n vector::const_iterator iter;\n\n for(iter=input.begin();iter!=input.end();++iter)\n (*iter)->changeHandleIndex(handmap);\n}\n\nvoid OpTpl::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_OP_TPL);\n encoder.writeOpcode(sla::ATTRIB_CODE, opc);\n if (output == (VarnodeTpl *)0) {\n encoder.openElement(sla::ELEM_NULL);\n encoder.closeElement(sla::ELEM_NULL);\n }\n else\n output->encode(encoder);\n for(int4 i=0;iencode(encoder);\n encoder.closeElement(sla::ELEM_OP_TPL);\n}\n\nvoid OpTpl::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_OP_TPL);\n opc = decoder.readOpcode(sla::ATTRIB_CODE);\n uint4 subel = decoder.peekElement();\n if (subel == sla::ELEM_NULL) {\n decoder.openElement();\n decoder.closeElement(subel);\n output = (VarnodeTpl *)0;\n }\n else {\n output = new VarnodeTpl();\n output->decode(decoder);\n }\n while(decoder.peekElement() != 0) {\n VarnodeTpl *vn = new VarnodeTpl();\n vn->decode(decoder);\n input.push_back(vn);\n }\n decoder.closeElement(el);\n}\n\nConstructTpl::~ConstructTpl(void)\n\n{\t\t\t\t// Constructor owns its ops and handles\n vector::iterator oiter;\n for(oiter=vec.begin();oiter!=vec.end();++oiter)\n delete *oiter;\n if (result != (HandleTpl *)0)\n delete result;\n}\n\nbool ConstructTpl::addOp(OpTpl *ot)\n\n{\n if (ot->getOpcode() == DELAY_SLOT) {\n if (delayslot != 0)\n return false;\t\t// Cannot have multiple delay slots\n delayslot = ot->getIn(0)->getOffset().getReal();\n }\n else if (ot->getOpcode() == LABELBUILD)\n numlabels += 1;\t\t// Count labels\n vec.push_back(ot);\n return true;\n}\n\nbool ConstructTpl::addOpList(const vector &oplist)\n\n{\n for(int4 i=0;i &check,AddrSpace *const_space)\n\n{ // Make sure there is a build statement for all subtable params\n // Return 0 upon success, 1 if there is a duplicate BUILD, 2 if there is a build for a non-subtable\n vector::iterator iter;\n OpTpl *op;\n VarnodeTpl *indvn;\n\n for(iter=vec.begin();iter!=vec.end();++iter) {\n op = *iter;\n if (op->getOpcode() == BUILD) {\n int4 index = op->getIn(0)->getOffset().getReal();\n if (check[index] != 0)\n\treturn check[index];\t// Duplicate BUILD statement or non-subtable\n check[index] = 1;\t\t// Mark to avoid future duplicate build\n }\n }\n for(int4 i=0;iaddInput(indvn);\n vec.insert(vec.begin(),op);\n }\n }\n return 0;\n}\n\nbool ConstructTpl::buildOnly(void) const\n\n{\n vector::const_iterator iter;\n OpTpl *op;\n for(iter=vec.begin();iter!=vec.end();++iter) {\n op = *iter;\n if (op->getOpcode() != BUILD)\n return false;\n }\n return true;\n}\n\nvoid ConstructTpl::changeHandleIndex(const vector &handmap)\n\n{\n vector::const_iterator iter;\n OpTpl *op;\n\n for(iter=vec.begin();iter!=vec.end();++iter) {\n op = *iter;\n if (op->getOpcode() == BUILD) {\n int4 index = op->getIn(0)->getOffset().getReal();\n index = handmap[index];\n op->getIn(0)->setOffset(index);\n }\n else\n op->changeHandleIndex(handmap);\n }\n if (result != (HandleTpl *)0)\n result->changeHandleIndex(handmap);\n}\n\nvoid ConstructTpl::setInput(VarnodeTpl *vn,int4 index,int4 slot)\n\n{ // set the VarnodeTpl input for a particular op\n // for use with optimization routines\n OpTpl *op = vec[index];\n VarnodeTpl *oldvn = op->getIn(slot);\n op->setInput(vn,slot);\n if (oldvn != (VarnodeTpl *)0)\n delete oldvn;\n}\n\nvoid ConstructTpl::setOutput(VarnodeTpl *vn,int4 index)\n\n{ // set the VarnodeTpl output for a particular op\n // for use with optimization routines\n OpTpl *op = vec[index];\n VarnodeTpl *oldvn = op->getOut();\n op->setOutput(vn);\n if (oldvn != (VarnodeTpl *)0)\n delete oldvn;\n}\n\nvoid ConstructTpl::deleteOps(const vector &indices)\n\n{ // delete a particular set of ops\n for(uint4 i=0;i poscur)\n vec.pop_back();\n}\n\nvoid ConstructTpl::encode(Encoder &encoder,int4 sectionid) const\n\n{\n encoder.openElement(sla::ELEM_CONSTRUCT_TPL);\n if (sectionid >=0 )\n encoder.writeSignedInteger(sla::ATTRIB_SECTION, sectionid);\n if (delayslot != 0)\n encoder.writeSignedInteger(sla::ATTRIB_DELAY, delayslot);\n if (numlabels != 0)\n encoder.writeSignedInteger(sla::ATTRIB_LABELS, numlabels);\n if (result != (HandleTpl *)0)\n result->encode(encoder);\n else {\n encoder.openElement(sla::ELEM_NULL);\n encoder.closeElement(sla::ELEM_NULL);\n }\n for(int4 i=0;iencode(encoder);\n encoder.closeElement(sla::ELEM_CONSTRUCT_TPL);\n}\n\nint4 ConstructTpl::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_CONSTRUCT_TPL);\n int4 sectionid = -1;\n uint4 attrib = decoder.getNextAttributeId();\n while(attrib != 0) {\n if (attrib == sla::ATTRIB_DELAY) {\n delayslot = decoder.readSignedInteger();\n }\n else if (attrib == sla::ATTRIB_LABELS) {\n numlabels = decoder.readSignedInteger();\n }\n else if (attrib == sla::ATTRIB_SECTION) {\n sectionid = decoder.readSignedInteger();\n }\n attrib = decoder.getNextAttributeId();\n }\n uint4 subel = decoder.peekElement();\n if (subel == sla::ELEM_NULL) {\n decoder.openElement();\n decoder.closeElement(subel);\n result = (HandleTpl *)0;\n }\n else {\n result = new HandleTpl();\n result->decode(decoder);\n }\n while(decoder.peekElement() != 0) {\n OpTpl *op = new OpTpl();\n op->decode(decoder);\n vec.push_back(op);\n }\n decoder.closeElement(el);\n return sectionid;\n}\n\nvoid PcodeBuilder::build(ConstructTpl *construct,int4 secnum)\n\n{\n if (construct == (ConstructTpl *)0)\n throw UnimplError(\"\",0);\t// Pcode is not implemented for this constructor\n\n uint4 oldbase = labelbase;\t// Recursively store old labelbase\n labelbase = labelcount;\t// Set the newbase\n labelcount += construct->numLabels();\t// Add labels from this template\n\n vector::const_iterator iter;\n OpTpl *op;\n const vector &ops(construct->getOpvec());\n\n for(iter=ops.begin();iter!=ops.end();++iter) {\n op = *iter;\n switch(op->getOpcode()) {\n case BUILD:\n appendBuild( op, secnum );\n break;\n case DELAY_SLOT:\n delaySlot( op );\n break;\n case LABELBUILD:\n setLabel( op );\n break;\n case CROSSBUILD:\n appendCrossBuild(op,secnum);\n break;\n default:\n dump( op );\n break;\n }\n }\n labelbase = oldbase;\t\t// Restore old labelbase\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/semantics.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __SEMANTICS_HH__\n#define __SEMANTICS_HH__\n\n#include \"context.hh\"\n#include \"slaformat.hh\"\n\nnamespace ghidra {\n\n// We remap these opcodes for internal use during pcode generation\n\n#define BUILD CPUI_MULTIEQUAL\n#define DELAY_SLOT CPUI_INDIRECT\n#define CROSSBUILD CPUI_PTRSUB\n#define MACROBUILD CPUI_CAST\n#define LABELBUILD CPUI_PTRADD\n\nclass Translate;\t\t// Forward declaration\nclass HandleTpl;\t\t// Forward declaration\nclass ConstTpl {\npublic:\n enum const_type { real=0, handle=1, j_start=2, j_next=3, j_next2=4, j_curspace=5, \n\t\t j_curspace_size=6, spaceid=7, j_relative=8,\n\t\t j_flowref=9, j_flowref_size=10, j_flowdest=11, j_flowdest_size=12 };\n enum v_field { v_space=0, v_offset=1, v_size=2, v_offset_plus=3 };\nprivate:\n const_type type;\n union {\n // uintb real;\t\t\t// an actual constant\n AddrSpace *spaceid;\t// Id (pointer) for registered space\n int4 handle_index;\t\t// Place holder for run-time determined value\n } value;\n uintb value_real;\n v_field select;\t\t// Which part of handle to use as constant\npublic:\n ConstTpl(void) { type = real; value_real = 0; }\n ConstTpl(const ConstTpl &op2) {\n type=op2.type; value=op2.value; value_real=op2.value_real; select=op2.select; }\n ConstTpl(const_type tp,uintb val);\n ConstTpl(const_type tp);\n ConstTpl(AddrSpace *sid);\n ConstTpl(const_type tp,int4 ht,v_field vf);\n ConstTpl(const_type tp,int4 ht,v_field vf,uintb plus);\n bool isConstSpace(void) const;\n bool isUniqueSpace(void) const;\n bool operator==(const ConstTpl &op2) const;\n bool operator<(const ConstTpl &op2) const;\n uintb getReal(void) const { return value_real; }\n AddrSpace *getSpace(void) const { return value.spaceid; }\n int4 getHandleIndex(void) const { return value.handle_index; }\n const_type getType(void) const { return type; }\n v_field getSelect(void) const { return select; }\n uintb fix(const ParserWalker &walker) const;\n AddrSpace *fixSpace(const ParserWalker &walker) const;\n void transfer(const vector ¶ms);\n bool isZero(void) const { return ((type==real)&&(value_real==0)); }\n void changeHandleIndex(const vector &handmap);\n void fillinSpace(FixedHandle &hand,const ParserWalker &walker) const;\n void fillinOffset(FixedHandle &hand,const ParserWalker &walker) const;\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder);\n};\n\nclass VarnodeTpl {\n friend class OpTpl;\n friend class HandleTpl;\n ConstTpl space,offset,size;\n bool unnamed_flag;\npublic:\n VarnodeTpl(int4 hand,bool zerosize);\n VarnodeTpl(void) : space(), offset(), size() { unnamed_flag=false; }\n VarnodeTpl(const ConstTpl &sp,const ConstTpl &off,const ConstTpl &sz);\n VarnodeTpl(const VarnodeTpl &vn);\n const ConstTpl &getSpace(void) const { return space; }\n const ConstTpl &getOffset(void) const { return offset; }\n const ConstTpl &getSize(void) const { return size; }\n bool isDynamic(const ParserWalker &walker) const;\n int4 transfer(const vector ¶ms);\n bool isZeroSize(void) const { return size.isZero(); }\n bool operator==(const VarnodeTpl &op2) const;\n bool operator!=(const VarnodeTpl &op2) const;\n bool operator<(const VarnodeTpl &op2) const;\n void setOffset(uintb constVal) { offset = ConstTpl(ConstTpl::real,constVal); }\n void setRelative(uintb constVal) { offset = ConstTpl(ConstTpl::j_relative,constVal); }\n void setSize(const ConstTpl &sz ) { size = sz; }\n bool isUnnamed(void) const { return unnamed_flag; }\n void setUnnamed(bool val) { unnamed_flag = val; }\n bool isLocalTemp(void) const;\n bool isRelative(void) const { return (offset.getType() == ConstTpl::j_relative); }\n void changeHandleIndex(const vector &handmap);\n bool adjustTruncation(int4 sz,bool isbigendian);\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder);\n};\n\nclass HandleTpl {\n ConstTpl space;\n ConstTpl size;\n ConstTpl ptrspace;\n ConstTpl ptroffset;\n ConstTpl ptrsize;\n ConstTpl temp_space;\n ConstTpl temp_offset;\npublic:\n HandleTpl(void) {}\n HandleTpl(const VarnodeTpl *vn);\n HandleTpl(const ConstTpl &spc,const ConstTpl &sz,const VarnodeTpl *vn,\n\t AddrSpace *t_space,uintb t_offset);\n const ConstTpl &getSpace(void) const { return space; }\n const ConstTpl &getPtrSpace(void) const { return ptrspace; }\n const ConstTpl &getPtrOffset(void) const { return ptroffset; }\n const ConstTpl &getPtrSize(void) const { return ptrsize; }\n const ConstTpl &getSize(void) const { return size; }\n const ConstTpl &getTempSpace(void) const { return temp_space; }\n const ConstTpl &getTempOffset(void) const { return temp_offset; }\n void setSize(const ConstTpl &sz) { size = sz; }\n void setPtrSize(const ConstTpl &sz) { ptrsize=sz; }\n void setPtrOffset(uintb val) { ptroffset = ConstTpl(ConstTpl::real,val); }\n void setTempOffset(uintb val) { temp_offset = ConstTpl(ConstTpl::real,val); }\n void fix(FixedHandle &hand,const ParserWalker &walker) const;\n void changeHandleIndex(const vector &handmap);\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder);\n};\n\nclass OpTpl {\n VarnodeTpl *output;\n OpCode opc;\n vector input;\npublic:\n OpTpl(void) {}\n OpTpl(OpCode oc) { opc = oc; output = (VarnodeTpl *)0; }\n ~OpTpl(void);\n VarnodeTpl *getOut(void) const { return output; }\n int4 numInput(void) const { return input.size(); }\n VarnodeTpl *getIn(int4 i) const { return input[i]; }\n OpCode getOpcode(void) const { return opc; }\n bool isZeroSize(void) const;\n void setOpcode(OpCode o) { opc = o; }\n void setOutput(VarnodeTpl *vt) { output = vt; }\n void clearOutput(void) { delete output; output = (VarnodeTpl *)0; }\n void addInput(VarnodeTpl *vt) { input.push_back(vt); }\n void setInput(VarnodeTpl *vt,int4 slot) { input[slot] = vt; }\n void removeInput(int4 index);\n void changeHandleIndex(const vector &handmap);\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder);\n};\n\nclass ConstructTpl {\n friend class SleighCompile;\nprotected:\n uint4 delayslot;\n uint4 numlabels;\t\t// Number of label templates\n vector vec;\n HandleTpl *result;\n void setOpvec(vector &opvec) { vec = opvec; }\n void setNumLabels(uint4 val) { numlabels = val; }\npublic:\n ConstructTpl(void) { delayslot=0; numlabels=0; result = (HandleTpl *)0; }\n ~ConstructTpl(void);\n uint4 delaySlot(void) const { return delayslot; }\n uint4 numLabels(void) const { return numlabels; }\n const vector &getOpvec(void) const { return vec; }\n HandleTpl *getResult(void) const { return result; }\n bool addOp(OpTpl *ot);\n bool addOpList(const vector &oplist);\n void setResult(HandleTpl *t) { result = t; }\n int4 fillinBuild(vector &check,AddrSpace *const_space);\n bool buildOnly(void) const;\n void changeHandleIndex(const vector &handmap);\n void setInput(VarnodeTpl *vn,int4 index,int4 slot);\n void setOutput(VarnodeTpl *vn,int4 index);\n void deleteOps(const vector &indices);\n void encode(Encoder &encoder,int4 sectionid) const;\n int4 decode(Decoder &decoder);\n};\n\nclass PcodeEmit; // Forward declaration for emitter\n\nclass PcodeBuilder { // SLEIGH specific pcode generator\n uint4 labelbase;\n uint4 labelcount;\nprotected:\n ParserWalker *walker;\n virtual void dump( OpTpl *op )=0;\npublic:\n PcodeBuilder(uint4 lbcnt) { labelbase=labelcount=lbcnt; }\n virtual ~PcodeBuilder(void) {}\n\n uint4 getLabelBase(void) const { return labelbase; }\n ParserWalker *getCurrentWalker() const { return walker; }\n void build(ConstructTpl *construct,int4 secnum);\n virtual void appendBuild(OpTpl *bld,int4 secnum)=0;\n virtual void delaySlot(OpTpl *op)=0;\n virtual void setLabel(OpTpl *op)=0;\n virtual void appendCrossBuild(OpTpl *bld,int4 secnum)=0;\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/slaformat.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"slaformat.hh\"\n\nnamespace ghidra {\nnamespace sla {\nconst int4 FORMAT_SCOPE = 1;\nconst int4 FORMAT_VERSION = 4;\n\n// ATTRIB_CONTEXT = 1 is reserved\nAttributeId ATTRIB_VAL = AttributeId(\"val\", 2, FORMAT_SCOPE);\nAttributeId ATTRIB_ID = AttributeId(\"id\", 3, FORMAT_SCOPE);\nAttributeId ATTRIB_SPACE = AttributeId(\"space\", 4, FORMAT_SCOPE);\nAttributeId ATTRIB_S = AttributeId(\"s\", 5, FORMAT_SCOPE);\nAttributeId ATTRIB_OFF = AttributeId(\"off\", 6, FORMAT_SCOPE);\nAttributeId ATTRIB_CODE = AttributeId(\"code\", 7, FORMAT_SCOPE);\nAttributeId ATTRIB_MASK = AttributeId(\"mask\", 8, FORMAT_SCOPE);\nAttributeId ATTRIB_INDEX = AttributeId(\"index\", 9, FORMAT_SCOPE);\nAttributeId ATTRIB_NONZERO = AttributeId(\"nonzero\", 10, FORMAT_SCOPE);\nAttributeId ATTRIB_PIECE = AttributeId(\"piece\", 11, FORMAT_SCOPE);\nAttributeId ATTRIB_NAME = AttributeId(\"name\", 12, FORMAT_SCOPE);\nAttributeId ATTRIB_SCOPE = AttributeId(\"scope\", 13, FORMAT_SCOPE);\nAttributeId ATTRIB_STARTBIT = AttributeId(\"startbit\", 14, FORMAT_SCOPE);\nAttributeId ATTRIB_SIZE = AttributeId(\"size\", 15, FORMAT_SCOPE);\nAttributeId ATTRIB_TABLE = AttributeId(\"table\", 16, FORMAT_SCOPE);\nAttributeId ATTRIB_CT = AttributeId(\"ct\", 17, FORMAT_SCOPE);\nAttributeId ATTRIB_MINLEN = AttributeId(\"minlen\", 18, FORMAT_SCOPE);\nAttributeId ATTRIB_BASE = AttributeId(\"base\", 19, FORMAT_SCOPE);\nAttributeId ATTRIB_NUMBER = AttributeId(\"number\", 20, FORMAT_SCOPE);\nAttributeId ATTRIB_CONTEXT = AttributeId(\"context\", 21, FORMAT_SCOPE);\nAttributeId ATTRIB_PARENT = AttributeId(\"parent\", 22, FORMAT_SCOPE);\nAttributeId ATTRIB_SUBSYM = AttributeId(\"subsym\", 23, FORMAT_SCOPE);\nAttributeId ATTRIB_LINE = AttributeId(\"line\", 24, FORMAT_SCOPE);\nAttributeId ATTRIB_SOURCE = AttributeId(\"source\", 25, FORMAT_SCOPE);\nAttributeId ATTRIB_LENGTH = AttributeId(\"length\", 26, FORMAT_SCOPE);\nAttributeId ATTRIB_FIRST = AttributeId(\"first\", 27, FORMAT_SCOPE);\nAttributeId ATTRIB_PLUS = AttributeId(\"plus\", 28, FORMAT_SCOPE);\nAttributeId ATTRIB_SHIFT = AttributeId(\"shift\", 29, FORMAT_SCOPE);\nAttributeId ATTRIB_ENDBIT = AttributeId(\"endbit\", 30, FORMAT_SCOPE);\nAttributeId ATTRIB_SIGNBIT = AttributeId(\"signbit\", 31, FORMAT_SCOPE);\nAttributeId ATTRIB_ENDBYTE = AttributeId(\"endbyte\", 32, FORMAT_SCOPE);\nAttributeId ATTRIB_STARTBYTE = AttributeId(\"startbyte\", 33, FORMAT_SCOPE);\n\nAttributeId ATTRIB_VERSION = AttributeId(\"version\", 34, FORMAT_SCOPE);\nAttributeId ATTRIB_BIGENDIAN = AttributeId(\"bigendian\", 35, FORMAT_SCOPE);\nAttributeId ATTRIB_ALIGN = AttributeId(\"align\", 36, FORMAT_SCOPE);\nAttributeId ATTRIB_UNIQBASE = AttributeId(\"uniqbase\", 37, FORMAT_SCOPE);\nAttributeId ATTRIB_MAXDELAY = AttributeId(\"maxdelay\", 38, FORMAT_SCOPE);\nAttributeId ATTRIB_UNIQMASK = AttributeId(\"uniqmask\", 39, FORMAT_SCOPE);\nAttributeId ATTRIB_NUMSECTIONS = AttributeId(\"numsections\", 40, FORMAT_SCOPE);\nAttributeId ATTRIB_DEFAULTSPACE = AttributeId(\"defaultspace\", 41, FORMAT_SCOPE);\nAttributeId ATTRIB_DELAY = AttributeId(\"delay\", 42, FORMAT_SCOPE);\nAttributeId ATTRIB_WORDSIZE = AttributeId(\"wordsize\", 43, FORMAT_SCOPE);\nAttributeId ATTRIB_PHYSICAL = AttributeId(\"physical\", 44, FORMAT_SCOPE);\nAttributeId ATTRIB_SCOPESIZE = AttributeId(\"scopesize\", 45, FORMAT_SCOPE);\nAttributeId ATTRIB_SYMBOLSIZE = AttributeId(\"symbolsize\", 46, FORMAT_SCOPE);\nAttributeId ATTRIB_VARNODE = AttributeId(\"varnode\", 47, FORMAT_SCOPE);\nAttributeId ATTRIB_LOW = AttributeId(\"low\", 48, FORMAT_SCOPE);\nAttributeId ATTRIB_HIGH = AttributeId(\"high\", 49, FORMAT_SCOPE);\nAttributeId ATTRIB_FLOW = AttributeId(\"flow\", 50, FORMAT_SCOPE);\nAttributeId ATTRIB_CONTAIN = AttributeId(\"contain\", 51, FORMAT_SCOPE);\nAttributeId ATTRIB_I = AttributeId(\"i\", 52, FORMAT_SCOPE);\nAttributeId ATTRIB_NUMCT = AttributeId(\"numct\", 53, FORMAT_SCOPE);\nAttributeId ATTRIB_SECTION = AttributeId(\"section\", 54, FORMAT_SCOPE);\nAttributeId ATTRIB_LABELS = AttributeId(\"labels\", 55, FORMAT_SCOPE);\n\nElementId ELEM_CONST_REAL = ElementId(\"const_real\", 1, FORMAT_SCOPE);\nElementId ELEM_VARNODE_TPL = ElementId(\"varnode_tpl\", 2, FORMAT_SCOPE);\nElementId ELEM_CONST_SPACEID = ElementId(\"const_spaceid\", 3, FORMAT_SCOPE);\nElementId ELEM_CONST_HANDLE = ElementId(\"const_handle\", 4, FORMAT_SCOPE);\nElementId ELEM_OP_TPL = ElementId(\"op_tpl\", 5, FORMAT_SCOPE);\nElementId ELEM_MASK_WORD = ElementId(\"mask_word\", 6, FORMAT_SCOPE);\nElementId ELEM_PAT_BLOCK = ElementId(\"pat_block\", 7, FORMAT_SCOPE);\nElementId ELEM_PRINT = ElementId(\"print\", 8, FORMAT_SCOPE);\nElementId ELEM_PAIR = ElementId(\"pair\", 9, FORMAT_SCOPE);\nElementId ELEM_CONTEXT_PAT = ElementId(\"context_pat\", 10, FORMAT_SCOPE);\nElementId ELEM_NULL = ElementId(\"null\", 11, FORMAT_SCOPE);\nElementId ELEM_OPERAND_EXP = ElementId(\"operand_exp\", 12, FORMAT_SCOPE);\nElementId ELEM_OPERAND_SYM = ElementId(\"operand_sym\", 13, FORMAT_SCOPE);\nElementId ELEM_OPERAND_SYM_HEAD = ElementId(\"operand_sym_head\", 14, FORMAT_SCOPE);\nElementId ELEM_OPER = ElementId(\"oper\", 15, FORMAT_SCOPE);\nElementId ELEM_DECISION = ElementId(\"decision\", 16, FORMAT_SCOPE);\nElementId ELEM_OPPRINT = ElementId(\"opprint\", 17, FORMAT_SCOPE);\nElementId ELEM_INSTRUCT_PAT = ElementId(\"instruct_pat\", 18, FORMAT_SCOPE);\nElementId ELEM_COMBINE_PAT = ElementId(\"combine_pat\", 19, FORMAT_SCOPE);\nElementId ELEM_CONSTRUCTOR = ElementId(\"constructor\", 20, FORMAT_SCOPE);\nElementId ELEM_CONSTRUCT_TPL = ElementId(\"construct_tpl\", 21, FORMAT_SCOPE);\nElementId ELEM_SCOPE = ElementId(\"scope\", 22, FORMAT_SCOPE);\nElementId ELEM_VARNODE_SYM = ElementId(\"varnode_sym\", 23, FORMAT_SCOPE);\nElementId ELEM_VARNODE_SYM_HEAD = ElementId(\"varnode_sym_head\", 24, FORMAT_SCOPE);\nElementId ELEM_USEROP = ElementId(\"userop\", 25, FORMAT_SCOPE);\nElementId ELEM_USEROP_HEAD = ElementId(\"userop_head\", 26, FORMAT_SCOPE);\nElementId ELEM_TOKENFIELD = ElementId(\"tokenfield\", 27, FORMAT_SCOPE);\nElementId ELEM_VAR = ElementId(\"var\", 28, FORMAT_SCOPE);\nElementId ELEM_CONTEXTFIELD = ElementId(\"contextfield\", 29, FORMAT_SCOPE);\nElementId ELEM_HANDLE_TPL = ElementId(\"handle_tpl\", 30, FORMAT_SCOPE);\nElementId ELEM_CONST_RELATIVE = ElementId(\"const_relative\", 31, FORMAT_SCOPE);\nElementId ELEM_CONTEXT_OP = ElementId(\"context_op\", 32, FORMAT_SCOPE);\n\nElementId ELEM_SLEIGH = ElementId(\"sleigh\", 33, FORMAT_SCOPE);\nElementId ELEM_SPACES = ElementId(\"spaces\", 34, FORMAT_SCOPE);\nElementId ELEM_SOURCEFILES = ElementId(\"sourcefiles\", 35, FORMAT_SCOPE);\nElementId ELEM_SOURCEFILE = ElementId(\"sourcefile\", 36, FORMAT_SCOPE);\nElementId ELEM_SPACE = ElementId(\"space\", 37, FORMAT_SCOPE);\nElementId ELEM_SYMBOL_TABLE = ElementId(\"symbol_table\", 38, FORMAT_SCOPE);\nElementId ELEM_VALUE_SYM = ElementId(\"value_sym\", 39, FORMAT_SCOPE);\nElementId ELEM_VALUE_SYM_HEAD = ElementId(\"value_sym_head\", 40, FORMAT_SCOPE);\nElementId ELEM_CONTEXT_SYM = ElementId(\"context_sym\", 41, FORMAT_SCOPE);\nElementId ELEM_CONTEXT_SYM_HEAD = ElementId(\"context_sym_head\", 42, FORMAT_SCOPE);\nElementId ELEM_END_SYM = ElementId(\"end_sym\", 43, FORMAT_SCOPE);\nElementId ELEM_END_SYM_HEAD = ElementId(\"end_sym_head\", 44, FORMAT_SCOPE);\nElementId ELEM_SPACE_OTHER = ElementId(\"space_other\", 45, FORMAT_SCOPE);\nElementId ELEM_SPACE_UNIQUE = ElementId(\"space_unique\", 46, FORMAT_SCOPE);\nElementId ELEM_AND_EXP = ElementId(\"and_exp\", 47, FORMAT_SCOPE);\nElementId ELEM_DIV_EXP = ElementId(\"div_exp\", 48, FORMAT_SCOPE);\nElementId ELEM_LSHIFT_EXP = ElementId(\"lshift_exp\", 49, FORMAT_SCOPE);\nElementId ELEM_MINUS_EXP = ElementId(\"minus_exp\", 50, FORMAT_SCOPE);\nElementId ELEM_MULT_EXP = ElementId(\"mult_exp\", 51, FORMAT_SCOPE);\nElementId ELEM_NOT_EXP = ElementId(\"not_exp\", 52, FORMAT_SCOPE);\nElementId ELEM_OR_EXP = ElementId(\"or_exp\", 53, FORMAT_SCOPE);\nElementId ELEM_PLUS_EXP = ElementId(\"plus_exp\", 54, FORMAT_SCOPE);\nElementId ELEM_RSHIFT_EXP = ElementId(\"rshift_exp\", 55, FORMAT_SCOPE);\nElementId ELEM_SUB_EXP = ElementId(\"sub_exp\", 56, FORMAT_SCOPE);\nElementId ELEM_XOR_EXP = ElementId(\"xor_exp\", 57, FORMAT_SCOPE);\nElementId ELEM_INTB = ElementId(\"intb\", 58, FORMAT_SCOPE);\nElementId ELEM_END_EXP = ElementId(\"end_exp\", 59, FORMAT_SCOPE);\nElementId ELEM_NEXT2_EXP = ElementId(\"next2_exp\", 60, FORMAT_SCOPE);\nElementId ELEM_START_EXP = ElementId(\"start_exp\", 61, FORMAT_SCOPE);\nElementId ELEM_EPSILON_SYM = ElementId(\"epsilon_sym\", 62, FORMAT_SCOPE);\nElementId ELEM_EPSILON_SYM_HEAD = ElementId(\"epsilon_sym_head\", 63, FORMAT_SCOPE);\nElementId ELEM_NAME_SYM = ElementId(\"name_sym\", 64, FORMAT_SCOPE);\nElementId ELEM_NAME_SYM_HEAD = ElementId(\"name_sym_head\", 65, FORMAT_SCOPE);\nElementId ELEM_NAMETAB = ElementId(\"nametab\", 66, FORMAT_SCOPE);\nElementId ELEM_NEXT2_SYM = ElementId(\"next2_sym\", 67, FORMAT_SCOPE);\nElementId ELEM_NEXT2_SYM_HEAD = ElementId(\"next2_sym_head\", 68, FORMAT_SCOPE);\nElementId ELEM_START_SYM = ElementId(\"start_sym\", 69, FORMAT_SCOPE);\nElementId ELEM_START_SYM_HEAD = ElementId(\"start_sym_head\", 70, FORMAT_SCOPE);\nElementId ELEM_SUBTABLE_SYM = ElementId(\"subtable_sym\", 71, FORMAT_SCOPE);\nElementId ELEM_SUBTABLE_SYM_HEAD = ElementId(\"subtable_sym_head\", 72, FORMAT_SCOPE);\nElementId ELEM_VALUEMAP_SYM = ElementId(\"valuemap_sym\", 73, FORMAT_SCOPE);\nElementId ELEM_VALUEMAP_SYM_HEAD = ElementId(\"valuemap_sym_head\", 74, FORMAT_SCOPE);\nElementId ELEM_VALUETAB = ElementId(\"valuetab\", 75, FORMAT_SCOPE);\nElementId ELEM_VARLIST_SYM = ElementId(\"varlist_sym\", 76, FORMAT_SCOPE);\nElementId ELEM_VARLIST_SYM_HEAD = ElementId(\"varlist_sym_head\", 77, FORMAT_SCOPE);\nElementId ELEM_OR_PAT = ElementId(\"or_pat\", 78, FORMAT_SCOPE);\nElementId ELEM_COMMIT = ElementId(\"commit\", 79, FORMAT_SCOPE);\nElementId ELEM_CONST_START = ElementId(\"const_start\", 80, FORMAT_SCOPE);\nElementId ELEM_CONST_NEXT = ElementId(\"const_next\", 81, FORMAT_SCOPE);\nElementId ELEM_CONST_NEXT2 = ElementId(\"const_next2\", 82, FORMAT_SCOPE);\nElementId ELEM_CONST_CURSPACE = ElementId(\"const_curspace\", 83, FORMAT_SCOPE);\nElementId ELEM_CONST_CURSPACE_SIZE = ElementId(\"const_curspace_size\", 84, FORMAT_SCOPE);\nElementId ELEM_CONST_FLOWREF = ElementId(\"const_flowref\", 85, FORMAT_SCOPE);\nElementId ELEM_CONST_FLOWREF_SIZE = ElementId(\"const_flowref_size\", 86, FORMAT_SCOPE);\nElementId ELEM_CONST_FLOWDEST = ElementId(\"const_flowdest\", 87, FORMAT_SCOPE);\nElementId ELEM_CONST_FLOWDEST_SIZE = ElementId(\"const_flowdest_size\", 88, FORMAT_SCOPE);\n\n/// The bytes of the header are read from the stream and verified against the required form and current version.\n/// If the form matches, \\b true is returned. No additional bytes are read.\n/// \\param s is the given stream\n/// \\return \\b true if a valid header is present\nbool isSlaFormat(istream &s)\n\n{\n uint1 header[4];\n s.read((char *)header,4);\n if (!s)\n return false;\n if (header[0] != 's' || header[1] != 'l' || header[2] != 'a')\n return false;\n if (header[3] != FORMAT_VERSION)\n return false;\n return true;\n}\n\n/// A valid header, including the format version number, is written to the stream.\n/// \\param s is the given stream\nvoid writeSlaHeader(ostream &s)\n\n{\n char header[4];\n header[0] = 's';\n header[1] = 'l';\n header[2] = 'a';\n header[3] = FORMAT_VERSION;\n s.write(header,4);\n}\n\n/// \\param s is the backing stream that will receive the final bytes of the .sla file\n/// \\param level is the compression level\nFormatEncode::FormatEncode(ostream &s,int4 level)\n : PackedEncode(compStream), compBuffer(s,level), compStream(&compBuffer)\n{\n writeSlaHeader(s);\n}\n\nvoid FormatEncode::flush(void)\n\n{\n compStream.flush();\n}\n\nconst int4 FormatDecode::IN_BUFFER_SIZE = 4096;\n\n/// \\param spcManager is the (uninitialized) manager that will hold decoded address spaces\nFormatDecode::FormatDecode(const AddrSpaceManager *spcManager)\n : PackedDecode(spcManager)\n{\n inBuffer = new uint1[IN_BUFFER_SIZE];\n}\n\nFormatDecode::~FormatDecode(void)\n\n{\n delete [] inBuffer;\n}\n\nvoid FormatDecode::ingestStream(istream &s)\n\n{\n if (!isSlaFormat(s))\n throw LowlevelError(\"Missing SLA format header\");\n Decompress decompressor;\n uint1 *outBuf;\n int4 outAvail = 0;\n\n while(!decompressor.isFinished()) {\n s.read((char *)inBuffer,IN_BUFFER_SIZE);\n int4 gcount = s.gcount();\n if (gcount == 0)\n\tbreak;\n decompressor.input(inBuffer,gcount);\n do {\n if (outAvail == 0) {\n\toutBuf = allocateNextInputBuffer(0);\n\toutAvail = BUFFER_SIZE;\n }\n outAvail = decompressor.inflate(outBuf + (BUFFER_SIZE - outAvail), outAvail);\n } while(outAvail == 0);\n\n }\n endIngest(BUFFER_SIZE - outAvail);\n}\n\n}\t// End sla namespace\n}\t// End ghidra namespace\n" }, { "path": "pypcode/sleigh/slaformat.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file slaformat.hh\n/// \\brief Encoding values for the SLA file format\n#ifndef __SLAFORMAT__\n#define __SLAFORMAT__\n\n#include \"compression.hh\"\n#include \"marshal.hh\"\n\nnamespace ghidra {\nnamespace sla {\n\nextern const int4 FORMAT_SCOPE;\t\t///< Grouping elements/attributes for SLA file format\nextern const int4 FORMAT_VERSION;\t///< Current version of the .sla file\n\nextern AttributeId ATTRIB_VAL;\t\t///< SLA format attribute \"val\"\nextern AttributeId ATTRIB_ID;\t\t///< SLA format attribute \"id\"\nextern AttributeId ATTRIB_SPACE;\t///< SLA format attribute \"space\"\nextern AttributeId ATTRIB_S;\t\t///< SLA format attribute \"s\"\nextern AttributeId ATTRIB_OFF;\t\t///< SLA format attribute \"off\"\nextern AttributeId ATTRIB_CODE;\t\t///< SLA format attribute \"code\"\nextern AttributeId ATTRIB_MASK;\t\t///< SLA format attribute \"mask\"\nextern AttributeId ATTRIB_INDEX;\t///< SLA format attribute \"index\"\nextern AttributeId ATTRIB_NONZERO;\t///< SLA format attribute \"nonzero\"\nextern AttributeId ATTRIB_PIECE;\t///< SLA format attribute \"piece\"\nextern AttributeId ATTRIB_NAME;\t\t///< SLA format attribute \"name\"\nextern AttributeId ATTRIB_SCOPE;\t///< SLA format attribute \"scope\"\nextern AttributeId ATTRIB_STARTBIT;\t///< SLA format attribute \"startbit\"\nextern AttributeId ATTRIB_SIZE;\t\t///< SLA format attribute \"size\"\nextern AttributeId ATTRIB_TABLE;\t///< SLA format attribute \"table\"\nextern AttributeId ATTRIB_CT;\t\t///< SLA format attribute \"ct\"\nextern AttributeId ATTRIB_MINLEN;\t///< SLA format attribute \"minlen\"\nextern AttributeId ATTRIB_BASE;\t\t///< SLA format attribute \"base\"\nextern AttributeId ATTRIB_NUMBER;\t///< SLA format attribute \"number\"\nextern AttributeId ATTRIB_CONTEXT;\t///< SLA format attribute \"context\"\nextern AttributeId ATTRIB_PARENT;\t///< SLA format attribute \"parent\"\nextern AttributeId ATTRIB_SUBSYM;\t///< SLA format attribute \"subsym\"\nextern AttributeId ATTRIB_LINE;\t\t///< SLA format attribute \"line\"\nextern AttributeId ATTRIB_SOURCE;\t///< SLA format attribute \"source\"\nextern AttributeId ATTRIB_LENGTH;\t///< SLA format attribute \"length\"\nextern AttributeId ATTRIB_FIRST;\t///< SLA format attribute \"first\"\nextern AttributeId ATTRIB_PLUS;\t\t///< SLA format attribute \"plus\"\nextern AttributeId ATTRIB_SHIFT;\t///< SLA format attribute \"shift\"\nextern AttributeId ATTRIB_ENDBIT;\t///< SLA format attribute \"endbit\"\nextern AttributeId ATTRIB_SIGNBIT;\t///< SLA format attribute \"signbit\"\nextern AttributeId ATTRIB_ENDBYTE;\t///< SLA format attribute \"endbyte\"\nextern AttributeId ATTRIB_STARTBYTE;\t///< SLA format attribute \"startbyte\"\n\nextern AttributeId ATTRIB_VERSION;\t///< SLA format attribute \"version\"\nextern AttributeId ATTRIB_BIGENDIAN;\t///< SLA format attribute \"bigendian\"\nextern AttributeId ATTRIB_ALIGN;\t///< SLA format attribute \"align\"\nextern AttributeId ATTRIB_UNIQBASE;\t///< SLA format attribute \"uniqbase\"\nextern AttributeId ATTRIB_MAXDELAY;\t///< SLA format attribute \"maxdelay\"\nextern AttributeId ATTRIB_UNIQMASK;\t///< SLA format attribute \"uniqmask\"\nextern AttributeId ATTRIB_NUMSECTIONS;\t///< SLA format attribute \"numsections\"\nextern AttributeId ATTRIB_DEFAULTSPACE;\t///< SLA format attribute \"defaultspace\"\nextern AttributeId ATTRIB_DELAY;\t///< SLA format attribute \"delay\"\nextern AttributeId ATTRIB_WORDSIZE;\t///< SLA format attribute \"wordsize\"\nextern AttributeId ATTRIB_PHYSICAL;\t///< SLA format attribute \"physical\"\nextern AttributeId ATTRIB_SCOPESIZE;\t///< SLA format attribute \"scopesize\"\nextern AttributeId ATTRIB_SYMBOLSIZE;\t///< SLA format attribute \"symbolsize\"\nextern AttributeId ATTRIB_VARNODE;\t///< SLA format attribute \"varnode\"\nextern AttributeId ATTRIB_LOW;\t\t///< SLA format attribute \"low\"\nextern AttributeId ATTRIB_HIGH;\t\t///< SLA format attribute \"high\"\nextern AttributeId ATTRIB_FLOW;\t\t///< SLA format attribute \"flow\"\nextern AttributeId ATTRIB_CONTAIN;\t///< SLA format attribute \"contain\"\nextern AttributeId ATTRIB_I;\t\t///< SLA format attribute \"i\"\nextern AttributeId ATTRIB_NUMCT;\t///< SLA format attribute \"numct\"\nextern AttributeId ATTRIB_SECTION;\t///< SLA format attribute \"section\"\nextern AttributeId ATTRIB_LABELS;\t///< SLA format attribute \"labels\"\n\nextern ElementId ELEM_CONST_REAL;\t///< SLA format element \"const_real\"\nextern ElementId ELEM_VARNODE_TPL;\t///< SLA format element \"varnode_tpl\"\nextern ElementId ELEM_CONST_SPACEID;\t///< SLA format element \"const_spaceid\"\nextern ElementId ELEM_CONST_HANDLE;\t///< SLA format element \"const_handle\"\nextern ElementId ELEM_OP_TPL;\t\t///< SLA format element \"op_tpl\"\nextern ElementId ELEM_MASK_WORD;\t///< SLA format element \"mask_word\"\nextern ElementId ELEM_PAT_BLOCK;\t///< SLA format element \"pat_block\"\nextern ElementId ELEM_PRINT;\t\t///< SLA format element \"print\"\nextern ElementId ELEM_PAIR;\t\t///< SLA format element \"pair\"\nextern ElementId ELEM_CONTEXT_PAT;\t///< SLA format element \"context_pat\"\nextern ElementId ELEM_NULL;\t\t///< SLA format element \"null\"\nextern ElementId ELEM_OPERAND_EXP;\t///< SLA format element \"operand_exp\"\nextern ElementId ELEM_OPERAND_SYM;\t///< SLA format element \"operand_sym\"\nextern ElementId ELEM_OPERAND_SYM_HEAD;\t///< SLA format element \"operand_sym_head\"\nextern ElementId ELEM_OPER;\t\t///< SLA format element \"oper\"\nextern ElementId ELEM_DECISION;\t\t///< SLA format element \"decision\"\nextern ElementId ELEM_OPPRINT;\t\t///< SLA format element \"opprint\"\nextern ElementId ELEM_INSTRUCT_PAT;\t///< SLA format element \"instruct_pat\"\nextern ElementId ELEM_COMBINE_PAT;\t///< SLA format element \"combine_pat\"\nextern ElementId ELEM_CONSTRUCTOR;\t///< SLA format element \"constructor\"\nextern ElementId ELEM_CONSTRUCT_TPL;\t///< SLA format element \"construct_tpl\"\nextern ElementId ELEM_SCOPE;\t\t///< SLA format element \"scope\"\nextern ElementId ELEM_VARNODE_SYM;\t///< SLA format element \"varnode_sym\"\nextern ElementId ELEM_VARNODE_SYM_HEAD;\t///< SLA format element \"varnode_sym_head\"\nextern ElementId ELEM_USEROP;\t\t///< SLA format element \"userop\"\nextern ElementId ELEM_USEROP_HEAD;\t///< SLA format element \"userop_head\"\nextern ElementId ELEM_TOKENFIELD;\t///< SLA format element \"tokenfield\"\nextern ElementId ELEM_VAR;\t\t///< SLA format element \"var\"\nextern ElementId ELEM_CONTEXTFIELD;\t///< SLA format element \"contextfield\"\nextern ElementId ELEM_HANDLE_TPL;\t///< SLA format element \"handle_tpl\"\nextern ElementId ELEM_CONST_RELATIVE;\t///< SLA format element \"const_relative\"\nextern ElementId ELEM_CONTEXT_OP;\t///< SLA format element \"context_op\"\n\nextern ElementId ELEM_SLEIGH;\t\t///< SLA format element \"sleigh\"\nextern ElementId ELEM_SPACES;\t\t///< SLA format element \"spaces\"\nextern ElementId ELEM_SOURCEFILES;\t///< SLA format element \"sourcefiles\"\nextern ElementId ELEM_SOURCEFILE;\t///< SLA format element \"sourcefile\"\nextern ElementId ELEM_SPACE;\t\t///< SLA format element \"space\"\nextern ElementId ELEM_SYMBOL_TABLE;\t///< SLA format element \"symbol_table\"\nextern ElementId ELEM_VALUE_SYM;\t///< SLA format element \"value_sym\"\nextern ElementId ELEM_VALUE_SYM_HEAD;\t///< SLA format element \"value_sym_head\"\nextern ElementId ELEM_CONTEXT_SYM;\t///< SLA format element \"context_sym\"\nextern ElementId ELEM_CONTEXT_SYM_HEAD;\t///< SLA format element \"context_sym_head\"\nextern ElementId ELEM_END_SYM;\t\t///< SLA format element \"end_sym\"\nextern ElementId ELEM_END_SYM_HEAD;\t///< SLA format element \"end_sym_head\"\nextern ElementId ELEM_SPACE_OTHER;\t///< SLA format element \"space_other\"\nextern ElementId ELEM_SPACE_UNIQUE;\t///< SLA format element \"space_unique\"\nextern ElementId ELEM_AND_EXP;\t\t///< SLA format element \"and_exp\"\nextern ElementId ELEM_DIV_EXP;\t\t///< SLA format element \"div_exp\"\nextern ElementId ELEM_LSHIFT_EXP;\t///< SLA format element \"lshift_exp\"\nextern ElementId ELEM_MINUS_EXP;\t///< SLA format element \"minus_exp\"\nextern ElementId ELEM_MULT_EXP;\t\t///< SLA format element \"mult_exp\"\nextern ElementId ELEM_NOT_EXP;\t\t///< SLA format element \"not_exp\"\nextern ElementId ELEM_OR_EXP;\t\t///< SLA format element \"or_exp\"\nextern ElementId ELEM_PLUS_EXP;\t\t///< SLA format element \"plus_exp\"\nextern ElementId ELEM_RSHIFT_EXP;\t///< SLA format element \"rshift_exp\"\nextern ElementId ELEM_SUB_EXP;\t\t///< SLA format element \"sub_exp\"\nextern ElementId ELEM_XOR_EXP;\t\t///< SLA format element \"xor_exp\"\nextern ElementId ELEM_INTB;\t\t///< SLA format element \"intb\"\nextern ElementId ELEM_END_EXP;\t\t///< SLA format element \"end_exp\"\nextern ElementId ELEM_NEXT2_EXP;\t///< SLA format element \"next2_exp\"\nextern ElementId ELEM_START_EXP;\t///< SLA format element \"start_exp\"\nextern ElementId ELEM_EPSILON_SYM;\t///< SLA format element \"epsilon_sym\"\nextern ElementId ELEM_EPSILON_SYM_HEAD;\t///< SLA format element \"epsilon_sym_head\"\nextern ElementId ELEM_NAME_SYM;\t\t///< SLA format element \"name_sym\"\nextern ElementId ELEM_NAME_SYM_HEAD;\t///< SLA format element \"name_sym_head\"\nextern ElementId ELEM_NAMETAB;\t\t///< SLA format element \"nametab\"\nextern ElementId ELEM_NEXT2_SYM;\t///< SLA format element \"next2_sym\"\nextern ElementId ELEM_NEXT2_SYM_HEAD;\t///< SLA format element \"next2_sym_head\"\nextern ElementId ELEM_START_SYM;\t///< SLA format element \"start_sym\"\nextern ElementId ELEM_START_SYM_HEAD;\t///< SLA format element \"start_sym_head\"\nextern ElementId ELEM_SUBTABLE_SYM;\t///< SLA format element \"subtable_sym\"\nextern ElementId ELEM_SUBTABLE_SYM_HEAD;\t///< SLA format element \"subtable_sym_head\"\nextern ElementId ELEM_VALUEMAP_SYM;\t///< SLA format element \"valuemap_sym\"\nextern ElementId ELEM_VALUEMAP_SYM_HEAD;\t///< SLA format element \"valuemap_sym_head\"\nextern ElementId ELEM_VALUETAB;\t\t///< SLA format element \"valuetab\"\nextern ElementId ELEM_VARLIST_SYM;\t///< SLA format element \"varlist_sym\"\nextern ElementId ELEM_VARLIST_SYM_HEAD;\t///< SLA format element \"varlist_sym_head\"\nextern ElementId ELEM_OR_PAT;\t\t///< SLA format element \"or_pat\"\nextern ElementId ELEM_COMMIT;\t\t///< SLA format element \"commit\"\nextern ElementId ELEM_CONST_START;\t///< SLA format element \"const_start\"\nextern ElementId ELEM_CONST_NEXT;\t///< SLA format element \"const_next\"\nextern ElementId ELEM_CONST_NEXT2;\t///< SLA format element \"const_next2\"\nextern ElementId ELEM_CONST_CURSPACE;\t///< SLA format element \"curspace\"\nextern ElementId ELEM_CONST_CURSPACE_SIZE;\t///< SLA format element \"curspace_size\"\nextern ElementId ELEM_CONST_FLOWREF;\t///< SLA format element \"const_flowref\"\nextern ElementId ELEM_CONST_FLOWREF_SIZE;\t///< SLA format element \"const_flowref_size\"\nextern ElementId ELEM_CONST_FLOWDEST;\t///< SLA format element \"const_flowdest\"\nextern ElementId ELEM_CONST_FLOWDEST_SIZE;\t///< SLA format element \"const_flowdest_size\"\n\nextern bool isSlaFormat(istream &s);\t///< Verify a .sla file header at the current point of the given stream\nextern void writeSlaHeader(ostream &s);\t///< Write a .sla file header to the given stream\n\n/// \\brief The encoder for the .sla file format\n///\n/// This provides the format header, does compression, and encodes the raw data elements/attributes.\nclass FormatEncode : public PackedEncode {\n CompressBuffer compBuffer;\t\t///< The compression stream filter\n ostream compStream;\t\t\t///< The front-end stream receiving uncompressed bytes\npublic:\n FormatEncode(ostream &s,int4 level);\t///< Initialize an encoder at a specific compression level\n void flush(void);\t\t\t///< Flush any buffered bytes in the encoder to the backing stream\n};\n\n/// \\brief The decoder for the .sla file format\n///\n/// This verifies the .sla file header, does decompression, and decodes the raw data elements/attributes.\nclass FormatDecode : public PackedDecode {\n static const int4 IN_BUFFER_SIZE;\t///< The size of the \\e input buffer\n uint1 *inBuffer;\t\t\t///< The \\e input buffer\npublic:\n FormatDecode(const AddrSpaceManager *spcManager);\t///< Initialize the decoder\n virtual ~FormatDecode(void);\t\t\t\t///< Destructor\n virtual void ingestStream(istream &s);\n};\n\n}\t// End namespace sla\n}\t// End namespace ghidra\n\n#endif\n" }, { "path": "pypcode/sleigh/sleigh.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"sleigh.hh\"\n#include \"loadimage.hh\"\n\nnamespace ghidra {\n\nPcodeCacher::PcodeCacher(void)\n\n{\n // We aim to allocate this array only once\n uint4 maxsize = 600;\n poolstart = new VarnodeData[ maxsize ];\n endpool = poolstart + maxsize;\n curpool = poolstart;\n}\n\nPcodeCacher::~PcodeCacher(void)\n\n{\n delete [] poolstart;\n}\n\n/// Expand the VarnodeData pool so that \\e size more elements fit, and return\n/// a pointer to first available element.\n/// \\param size is the number of elements to expand the pool by\n/// \\return the first available VarnodeData\nVarnodeData *PcodeCacher::expandPool(uint4 size)\n\n{\n uint4 curmax = endpool - poolstart;\n uint4 cursize = curpool - poolstart;\n if (cursize + size <= curmax)\n return curpool;\t\t// No expansion necessary\n uint4 increase = (cursize + size) - curmax;\n if (increase < 100)\t\t// Increase by at least 100\n increase = 100;\n\n uint4 newsize = curmax + increase;\n\n VarnodeData *newpool = new VarnodeData[newsize];\n for(uint4 i=0;i::iterator iter;\n for(iter=label_refs.begin();iter!=label_refs.end();++iter) {\n VarnodeData *ref = (*iter).dataptr;\n (*iter).dataptr = newpool + (ref - poolstart);\n }\n \n delete [] poolstart;\t\t// Free up old pool\n poolstart = newpool;\n curpool = newpool + (cursize + size);\n endpool = newpool + newsize;\n return newpool + cursize;\n}\n\n/// Store off a reference to the Varnode and the absolute index of the next\n/// instruction. The Varnode must be an operand of the current instruction.\n/// \\param ptr is the Varnode reference\nvoid PcodeCacher::addLabelRef(VarnodeData *ptr)\n\n{\n label_refs.emplace_back();\n label_refs.back().dataptr = ptr;\n label_refs.back().calling_index = issued.size();\n}\n\n/// The label has an id that is referred to by Varnodes holding\n/// intra-instruction branch targets, prior to converting\n/// them to a \\e relative \\e branch offset. The label is associated with\n/// the absolute index of the next PcodeData object to be issued,\n/// facilitating this conversion.\n/// \\param id is the given id of the label\nvoid PcodeCacher::addLabel(uint4 id)\n\n{\n while(labels.size() <= id)\n labels.push_back(0xbadbeef);\n labels[ id ] = issued.size();\n}\n\nvoid PcodeCacher::clear(void)\n\n{\n curpool = poolstart;\n issued.clear();\n label_refs.clear();\n labels.clear();\n}\n\n/// Assuming all the PcodeData has been generated for an\n/// instruction, go resolve any relative offsets and back\n/// patch their value(s) into the PcodeData\nvoid PcodeCacher::resolveRelatives(void)\n\n{\n list::const_iterator iter;\n for(iter=label_refs.begin();iter!=label_refs.end();++iter) {\n VarnodeData *ptr = (*iter).dataptr;\n uint4 id = ptr->offset;\n if ((id >= labels.size())||(labels[id] == 0xbadbeef))\n throw LowlevelError(\"Reference to non-existant sleigh label\");\n // Calculate the relative index given the two absolute indices\n uintb res = labels[id] - (*iter).calling_index;\n res &= calc_mask( ptr->size );\n ptr->offset = res;\n }\n}\n\n/// Each p-code operation is presented to the emitter via its dump() method.\n/// \\param addr is the Address associated with the p-code operation\n/// \\param emt is the emitter\nvoid PcodeCacher::emit(const Address &addr,PcodeEmit *emt) const\n\n{\n vector::const_iterator iter;\n\n for(iter=issued.begin();iter!=issued.end();++iter)\n emt->dump(addr,(*iter).opc,(*iter).outvar,(*iter).invar,(*iter).isize);\n}\n\n/// \\brief Generate a concrete VarnodeData object from the given template (VarnodeTpl)\n///\n/// \\param vntpl is the template to reference\n/// \\param vn is the object to fill in with concrete values\nvoid SleighBuilder::generateLocation(const VarnodeTpl *vntpl,VarnodeData &vn)\n\n{\n vn.space = vntpl->getSpace().fixSpace(*walker);\n vn.size = vntpl->getSize().fix(*walker);\n if (vn.space == const_space)\n vn.offset = vntpl->getOffset().fix(*walker) & calc_mask(vn.size);\n else if (vn.space == uniq_space) {\n vn.offset = vntpl->getOffset().fix(*walker);\n vn.offset |= uniqueoffset;\n }\n else\n vn.offset = vn.space->wrapOffset(vntpl->getOffset().fix(*walker));\n}\n\n/// \\brief Generate a pointer VarnodeData from a dynamic template (VarnodeTpl)\n///\n/// The symbol represents a value referenced through a dynamic pointer.\n/// This method generates the varnode representing the pointer itself and also\n/// returns the address space in anticipation of generating the LOAD or STORE\n/// that actually manipulates the value.\n/// \\param vntpl is the dynamic template to reference\n/// \\param vn is the object to fill with concrete values\n/// \\return the address space being pointed to\nAddrSpace *SleighBuilder::generatePointer(const VarnodeTpl *vntpl,VarnodeData &vn)\n\n{\n const FixedHandle &hand(walker->getFixedHandle(vntpl->getOffset().getHandleIndex()));\n vn.space = hand.offset_space;\n vn.size = hand.offset_size;\n if (vn.space == const_space)\n vn.offset = hand.offset_offset & calc_mask(vn.size);\n else if (vn.space == uniq_space)\n vn.offset = hand.offset_offset | uniqueoffset;\n else\n vn.offset = vn.space->wrapOffset(hand.offset_offset);\n return hand.space;\n}\n\n/// \\brief Add in an additional offset to the address of a dynamic Varnode\n///\n/// The Varnode is ultimately read/written via LOAD/STORE operation AND has undergone a truncation\n/// operation, so an additional offset needs to get added to the pointer referencing the Varnode.\n/// \\param op is the LOAD/STORE operation being generated\n/// \\param vntpl is the dynamic Varnode\nvoid SleighBuilder::generatePointerAdd(PcodeData *op,const VarnodeTpl *vntpl)\n\n{\n uintb offsetPlus = vntpl->getOffset().getReal() & 0xffff;\n if (offsetPlus == 0) {\n return;\n }\n PcodeData *nextop = cache->allocateInstruction();\n nextop->opc = op->opc;\n nextop->invar = op->invar;\n nextop->isize = op->isize;\n nextop->outvar = op->outvar;\n op->isize = 2;\n op->opc = CPUI_INT_ADD;\n VarnodeData *newparams = op->invar = cache->allocateVarnodes(2);\n newparams[0] = nextop->invar[1];\n newparams[1].space = const_space;\t// Add in V_OFFSET_PLUS\n newparams[1].offset = offsetPlus;\n newparams[1].size = newparams[0].size;\n op->outvar = nextop->invar + 1;\t// Output of ADD is input to original op\n op->outvar->space = uniq_space;\t\t// Result of INT_ADD in special runtime temp\n op->outvar->offset = uniq_space->getTrans()->getUniqueStart(Translate::RUNTIME_BITRANGE_EA);\n}\n\nvoid SleighBuilder::dump(OpTpl *op)\n\n{\t\t\t\t// Dump on op through low-level dump interface\n\t\t\t\t// filling in dynamic loads and stores if necessary\n PcodeData *thisop;\n VarnodeData *invars;\n VarnodeData *loadvars;\n VarnodeData *storevars;\n VarnodeTpl *vn,*outvn;\n int4 isize = op->numInput();\n\t\t\t\t// First build all the inputs\n invars = cache->allocateVarnodes(isize);\n for(int4 i=0;igetIn(i);\n if (vn->isDynamic(*walker)) {\n generateLocation(vn,invars[i]); // Input of -op- is really temporary storage\n PcodeData *load_op = cache->allocateInstruction();\n load_op->opc = CPUI_LOAD;\n load_op->outvar = invars + i;\n load_op->isize = 2;\n loadvars = load_op->invar = cache->allocateVarnodes(2);\n AddrSpace *spc = generatePointer(vn,loadvars[1]);\n loadvars[0].space = const_space;\n loadvars[0].offset = (uintb)(uintp)spc;\n loadvars[0].size = sizeof(spc);\n if (vn->getOffset().getSelect() == ConstTpl::v_offset_plus)\n\tgeneratePointerAdd(load_op, vn);\n }\n else\n generateLocation(vn,invars[i]);\n }\n if ((isize>0)&&(op->getIn(0)->isRelative())) {\n invars->offset += getLabelBase();\n cache->addLabelRef(invars);\n }\n thisop = cache->allocateInstruction();\n thisop->opc = op->getOpcode();\n thisop->invar = invars;\n thisop->isize = isize;\n outvn = op->getOut();\n if (outvn != (VarnodeTpl *)0) {\n if (outvn->isDynamic(*walker)) {\n storevars = cache->allocateVarnodes(3);\n generateLocation(outvn,storevars[2]); // Output of -op- is really temporary storage\n thisop->outvar = storevars+2;\n PcodeData *store_op = cache->allocateInstruction();\n store_op->opc = CPUI_STORE;\n store_op->isize = 3;\n // store_op->outvar = (VarnodeData *)0;\n store_op->invar = storevars;\n AddrSpace *spc = generatePointer(outvn,storevars[1]); // pointer\n storevars[0].space = const_space;\n storevars[0].offset = (uintb)(uintp)spc; // space in which to store\n storevars[0].size = sizeof(spc);\n if (outvn->getOffset().getSelect() == ConstTpl::v_offset_plus)\n\tgeneratePointerAdd(store_op,outvn);\n }\n else {\n thisop->outvar = cache->allocateVarnodes(1);\n generateLocation(outvn,*thisop->outvar);\n }\n }\n}\n\n/// \\brief Build a named p-code section of a constructor that contains only implied BUILD directives\n///\n/// If a named section of a constructor is empty, we still need to walk\n/// through any subtables that might contain p-code in their named sections.\n/// This method treats each subtable operand as an implied \\e build directive,\n/// in the otherwise empty section.\n/// \\param ct is the matching currently Constructor being built\n/// \\param secnum is the particular \\e named section number to build\nvoid SleighBuilder::buildEmpty(Constructor *ct,int4 secnum)\n\n{\n int4 numops = ct->getNumOperands();\n \n for(int4 i=0;igetOperand(i)->getDefiningSymbol();\n if (sym == (SubtableSymbol *)0) continue;\n if (sym->getType() != SleighSymbol::subtable_symbol) continue;\n\n walker->pushOperand(i);\n ConstructTpl *construct = walker->getConstructor()->getNamedTempl(secnum);\n if (construct == (ConstructTpl *)0)\n buildEmpty(walker->getConstructor(),secnum);\n else\n build(construct,secnum);\n walker->popOperand();\n }\n}\n\n/// Bits used to make temporary registers unique across multiple instructions\n/// are generated based on the given address.\n/// \\param addr is the given Address\nvoid SleighBuilder::setUniqueOffset(const Address &addr)\n\n{\n uniqueoffset = (addr.getOffset() & uniquemask)<<8;\n}\n\n/// \\brief Constructor\n///\n/// \\param w is the parsed instruction\n/// \\param dcache is a cache of nearby instruction parses\n/// \\param pc will hold the PcodeData and VarnodeData objects produced by \\b this builder\n/// \\param cspc is the constant address space\n/// \\param uspc is the unique address space\n/// \\param umask is the mask to use to find unique bits within an Address\nSleighBuilder::SleighBuilder(ParserWalker *w,DisassemblyCache *dcache,PcodeCacher *pc,AddrSpace *cspc,\n\t\t\t AddrSpace *uspc,uint4 umask)\n : PcodeBuilder(0)\n{\n walker = w;\n discache = dcache;\n cache = pc;\n const_space = cspc;\n uniq_space = uspc;\n uniquemask = umask;\n uniqueoffset = (walker->getAddr().getOffset() & uniquemask)<<8;\n}\n\nvoid SleighBuilder::appendBuild(OpTpl *bld,int4 secnum)\n\n{\n // Append p-code for a particular build statement\n int4 index = bld->getIn(0)->getOffset().getReal(); // Recover operand index from build statement\n\t\t\t\t// Check if operand is a subtable\n SubtableSymbol *sym = (SubtableSymbol *)walker->getConstructor()->getOperand(index)->getDefiningSymbol();\n if ((sym==(SubtableSymbol *)0)||(sym->getType() != SleighSymbol::subtable_symbol)) return;\n \n walker->pushOperand(index);\n Constructor *ct = walker->getConstructor();\n if (secnum >=0) {\n ConstructTpl *construct = ct->getNamedTempl(secnum);\n if (construct == (ConstructTpl *)0)\n buildEmpty(ct,secnum);\n else\n build(construct,secnum);\n }\n else {\n ConstructTpl *construct = ct->getTempl();\n build(construct,-1);\n }\n walker->popOperand();\n}\n\nvoid SleighBuilder::delaySlot(OpTpl *op)\n\n{\n // Append pcode for an entire instruction (delay slot)\n // in the middle of the current instruction\n ParserWalker *tmp = walker;\n uintb olduniqueoffset = uniqueoffset;\n\n Address baseaddr = tmp->getAddr();\n int4 fallOffset = tmp->getLength();\n int4 delaySlotByteCnt = tmp->getParserContext()->getDelaySlot();\n int4 bytecount = 0;\n do {\n Address newaddr = baseaddr + fallOffset;\n setUniqueOffset(newaddr);\n const ParserContext *pos = discache->getParserContext(newaddr);\n if (pos->getParserState() != ParserContext::pcode)\n throw LowlevelError(\"Could not obtain cached delay slot instruction\");\n int4 len = pos->getLength();\n\n ParserWalker newwalker( pos );\n walker = &newwalker;\n walker->baseState();\n build(walker->getConstructor()->getTempl(),-1); // Build the whole delay slot\n fallOffset += len;\n bytecount += len;\n } while(bytecount < delaySlotByteCnt);\n walker = tmp;\t\t\t// Restore original context\n uniqueoffset = olduniqueoffset;\n}\n\nvoid SleighBuilder::setLabel(OpTpl *op)\n\n{\n cache->addLabel( op->getIn(0)->getOffset().getReal()+getLabelBase() );\n}\n\nvoid SleighBuilder::appendCrossBuild(OpTpl *bld,int4 secnum)\n\n{\n // Weave in the p-code section from an instruction at another address\n // bld-param(0) contains the address of the instruction\n // bld-param(1) contains the section number\n if (secnum>=0)\n throw LowlevelError(\"CROSSBUILD directive within a named section\");\n secnum = bld->getIn(1)->getOffset().getReal();\n VarnodeTpl *vn = bld->getIn(0);\n AddrSpace *spc = vn->getSpace().fixSpace(*walker);\n uintb addr = spc->wrapOffset( vn->getOffset().fix(*walker) );\n\n ParserWalker *tmp = walker;\n uintb olduniqueoffset = uniqueoffset;\n\n Address newaddr(spc,addr);\n setUniqueOffset(newaddr);\n const ParserContext *pos = discache->getParserContext( newaddr );\n if (pos->getParserState() != ParserContext::pcode)\n throw LowlevelError(\"Could not obtain cached crossbuild instruction\");\n \n ParserWalker newwalker( pos, tmp->getParserContext() );\n walker = &newwalker;\n\n walker->baseState();\n Constructor *ct = walker->getConstructor();\n ConstructTpl *construct = ct->getNamedTempl(secnum);\n if (construct == (ConstructTpl *)0)\n buildEmpty(ct,secnum);\n else\n build(construct,secnum);\n walker = tmp;\n uniqueoffset = olduniqueoffset;\n}\n\n/// \\param min is the minimum number of allocations before a reuse is expected\n/// \\param hashsize is the number of elements in the hash-table\nvoid DisassemblyCache::initialize(int4 min,int4 hashsize)\n\n{\n minimumreuse = min;\n mask = hashsize-1;\n uintb masktest = coveringmask((uintb)mask);\n if (masktest != (uintb)mask)\t// -hashsize- must be a power of 2\n throw LowlevelError(\"Bad windowsize for disassembly cache\");\n list = new ParserContext *[minimumreuse];\n nextfree = 0;\n hashtable = new ParserContext *[hashsize];\n for(int4 i=0;iinitialize(75,20,constspace);\n list[i] = pos;\n }\n ParserContext *pos = list[0];\n for(int4 i=0;isetParserState(ParserContext::uninitialized);\n}\n\n/// Return a (possibly cached) ParserContext that is associated with \\e addr\n/// If n different calls to this interface are made with n different Addresses, if\n/// - n <= minimumreuse AND\n/// - all the addresses are within the windowsize (=mask+1)\n///\n/// then the cacher guarantees that you get all different ParserContext objects\n/// \\param addr is the Address to disassemble at\n/// \\return the ParserContext associated with the address\nParserContext *DisassemblyCache::getParserContext(const Address &addr)\n\n{\n int4 hashindex = ((int4) addr.getOffset()) & mask;\n ParserContext *res = hashtable[ hashindex ];\n if (res->getAddr() == addr)\n return res;\n res = list[ nextfree ];\n nextfree += 1;\t\t// Advance the circular index\n if (nextfree >= minimumreuse)\n nextfree = 0;\n res->setAddr(addr);\n res->setParserState(ParserContext::uninitialized);\t// Need to start over with parsing\n hashtable[ hashindex ] = res;\t// Stick it into the hashtable\n return res;\n}\n\n/// \\param ld is the LoadImage to draw program bytes from\n/// \\param c_db is the context database\nSleigh::Sleigh(LoadImage *ld,ContextDatabase *c_db)\n : SleighBase()\n\n{\n loader = ld;\n context_db = c_db;\n cache = new ContextCache(c_db);\n discache = (DisassemblyCache *)0;\n}\n\nvoid Sleigh::clearForDelete(void)\n\n{\n delete cache;\n if (discache != (DisassemblyCache *)0)\n delete discache;\n}\n\nSleigh::~Sleigh(void)\n\n{\n clearForDelete();\n}\n\n/// Completely clear everything except the base and reconstruct\n/// with a new LoadImage and ContextDatabase\n/// \\param ld is the new LoadImage\n/// \\param c_db is the new ContextDatabase\nvoid Sleigh::reset(LoadImage *ld,ContextDatabase *c_db)\n\n{\n clearForDelete();\n pcode_cache.clear();\n loader = ld;\n context_db = c_db;\n cache = new ContextCache(c_db);\n discache = (DisassemblyCache *)0;\n}\n\nvoid Sleigh::fastReset()\n\n{\n if (discache) {\n discache->fastReset();\n }\n}\n\n/// The .sla file from the document store is loaded and cache objects are prepared\n/// \\param store is the document store containing the main \\ tag.\nvoid Sleigh::initialize(DocumentStorage &store)\n\n{\n if (!isInitialized()) {\t// Initialize the base if not already\n const Element *el = store.getTag(\"sleigh\");\n if (el == (const Element *)0)\n throw LowlevelError(\"Could not find sleigh tag\");\n sla::FormatDecode decoder(this);\n ifstream s(el->getContent(), std::ios_base::binary);\n if (!s)\n throw LowlevelError(\"Could not open .sla file: \" + el->getContent());\n decoder.ingestStream(s);\n s.close();\n decode(decoder);\n }\n else\n reregisterContext();\n uint4 parser_cachesize = 2;\n uint4 parser_windowsize = 32;\n if ((maxdelayslotbytes > 1)||(unique_allocatemask != 0)) {\n parser_cachesize = 8;\n parser_windowsize = 256;\n }\n discache = new DisassemblyCache(this,cache,getConstantSpace(),parser_cachesize,parser_windowsize);\n}\n\n/// \\brief Obtain a parse tree for the instruction at the given address\n///\n/// The tree may be cached from a previous access. If the address\n/// has not been parsed, disassembly is performed, and a new parse tree\n/// is prepared. Depending on the desired \\e state, the parse tree\n/// can be prepared either for disassembly or for p-code generation.\n/// \\param addr is the given address of the instruction\n/// \\param state is the desired parse state.\n/// \\return the parse tree object (ParseContext)\nParserContext *Sleigh::obtainContext(const Address &addr,int4 state) const\n\n{\n ParserContext *pos = discache->getParserContext(addr);\n int4 curstate = pos->getParserState();\n if (curstate >= state)\n return pos;\n if (curstate == ParserContext::uninitialized) {\n resolve(*pos);\n if (state == ParserContext::disassembly)\n return pos;\n }\n // If we reach here, state must be ParserContext::pcode\n resolveHandles(*pos);\n return pos;\n}\n\n/// Resolve \\e all the constructors involved in the instruction at the indicated address\n/// \\param pos is the parse object that will hold the resulting tree\nvoid Sleigh::resolve(ParserContext &pos) const\n\n{\n loader->loadFill(pos.getBuffer(),16,pos.getAddr());\n ParserWalkerChange walker(&pos);\n pos.deallocateState(walker);\t// Clear the previous resolve and initialize the walker\n Constructor *ct,*subct;\n uint4 off;\n int4 oper,numoper;\n\n pos.setDelaySlot(0);\n walker.setOffset(0);\t\t// Initial offset\n pos.clearCommits();\t\t// Clear any old context commits\n pos.loadContext();\t\t// Get context for current address\n ct = root->resolve(walker);\t// Base constructor\n walker.setConstructor(ct);\n ct->applyContext(walker);\n while(walker.isState()) {\n ct = walker.getConstructor();\n oper = walker.getOperand();\n numoper = ct->getNumOperands();\n while(oper < numoper) {\n OperandSymbol *sym = ct->getOperand(oper);\n off = walker.getOffset(sym->getOffsetBase()) + sym->getRelativeOffset();\n pos.allocateOperand(oper,walker); // Descend into new operand and reserve space\n walker.setOffset(off);\n TripleSymbol *tsym = sym->getDefiningSymbol();\n if (tsym != (TripleSymbol *)0) {\n\tsubct = tsym->resolve(walker);\n\tif (subct != (Constructor *)0) {\n\t walker.setConstructor(subct);\n\t subct->applyContext(walker);\n\t break;\n\t}\n }\n walker.setCurrentLength(sym->getMinimumLength());\n walker.popOperand();\n oper += 1;\n }\n if (oper >= numoper) { // Finished processing constructor\n walker.calcCurrentLength(ct->getMinimumLength(),numoper);\n walker.popOperand();\n\t\t\t\t// Check for use of delayslot\n ConstructTpl *templ = ct->getTempl();\n if ((templ != (ConstructTpl *)0)&&(templ->delaySlot() > 0))\n\tpos.setDelaySlot(templ->delaySlot());\n }\n }\n pos.setNaddr(pos.getAddr()+pos.getLength());\t// Update Naddr to pointer after instruction\n pos.setParserState(ParserContext::disassembly);\n}\n\n/// Resolve handle templates for the given parse tree, assuming Constructors\n/// are already resolved.\n/// \\param pos is the given parse tree\nvoid Sleigh::resolveHandles(ParserContext &pos) const\n\n{\n TripleSymbol *triple;\n Constructor *ct;\n int4 oper,numoper;\n\n ParserWalker walker(&pos);\n walker.baseState();\n while(walker.isState()) {\n ct = walker.getConstructor();\n oper = walker.getOperand();\n numoper = ct->getNumOperands();\n while(oper < numoper) {\n OperandSymbol *sym = ct->getOperand(oper);\n walker.pushOperand(oper);\t// Descend into node\n triple = sym->getDefiningSymbol();\n if (triple != (TripleSymbol *)0) {\n\tif (triple->getType() == SleighSymbol::subtable_symbol)\n\t break;\n\telse\t\t\t// Some other kind of symbol as an operand\n\t triple->getFixedHandle(walker.getParentHandle(),walker);\n }\n else {\t\t\t// Must be an expression\n\tPatternExpression *patexp = sym->getDefiningExpression();\n\tintb res = patexp->getValue(walker);\n\tFixedHandle &hand(walker.getParentHandle());\n\thand.space = pos.getConstSpace(); // Result of expression is a constant\n\thand.offset_space = (AddrSpace *)0;\n\thand.offset_offset = (uintb)res;\n\thand.size = 0;\t\t// This size should not get used\n }\n walker.popOperand();\n oper += 1;\n }\n if (oper >= numoper) {\t// Finished processing constructor\n ConstructTpl *templ = ct->getTempl();\n if (templ != (ConstructTpl *)0) {\n\tHandleTpl *res = templ->getResult();\n\tif (res != (HandleTpl *)0)\t// Pop up handle to containing operand\n\t res->fix(walker.getParentHandle(),walker);\n\t// If we need an indicator that the constructor exports nothing try\n // else\n\t// walker.getParentHandle().setInvalid();\n }\n walker.popOperand();\n }\n }\n pos.setParserState(ParserContext::pcode);\n}\n\nint4 Sleigh::instructionLength(const Address &baseaddr) const\n\n{\n ParserContext *pos = obtainContext(baseaddr,ParserContext::disassembly);\n return pos->getLength();\n}\n\nint4 Sleigh::printAssembly(AssemblyEmit &emit,const Address &baseaddr) const\n\n{\n int4 sz;\n\n ParserContext *pos = obtainContext(baseaddr,ParserContext::disassembly);\n ParserWalker walker(pos);\n walker.baseState();\n \n Constructor *ct = walker.getConstructor();\n ostringstream mons;\n ct->printMnemonic(mons,walker);\n ostringstream body;\n ct->printBody(body,walker);\n emit.dump(baseaddr,mons.str(),body.str());\n sz = pos->getLength();\n return sz;\n}\n\nint4 Sleigh::oneInstruction(PcodeEmit &emit,const Address &baseaddr) const\n\n{\n int4 fallOffset;\n if (alignment != 1) {\n if ((baseaddr.getOffset() % alignment)!=0) {\n ostringstream s;\n s << \"Instruction address not aligned: \" << baseaddr;\n throw UnimplError(s.str(),0);\n }\n }\n \n ParserContext *pos = obtainContext(baseaddr,ParserContext::pcode);\n pos->applyCommits();\n fallOffset = pos->getLength();\n \n if (pos->getDelaySlot()>0) {\n int4 bytecount = 0;\n do {\n // Do not pass pos->getNaddr() to obtainContext, as pos may have been previously cached and had naddr adjusted\n ParserContext *delaypos = obtainContext(pos->getAddr() + fallOffset,ParserContext::pcode);\n delaypos->applyCommits();\n int4 len = delaypos->getLength();\n fallOffset += len;\n bytecount += len;\n } while(bytecount < pos->getDelaySlot());\n pos->setNaddr(pos->getAddr()+fallOffset);\n }\n ParserWalker walker(pos);\n walker.baseState();\n pcode_cache.clear();\n SleighBuilder builder(&walker,discache,&pcode_cache,getConstantSpace(),getUniqueSpace(),unique_allocatemask);\n try {\n builder.build(walker.getConstructor()->getTempl(),-1);\n pcode_cache.resolveRelatives();\n pcode_cache.emit(baseaddr,&emit);\n } catch(UnimplError &err) {\n ostringstream s;\n s << \"Instruction not implemented in pcode:\\n \";\n ParserWalker *cur = builder.getCurrentWalker();\n cur->baseState();\n Constructor *ct = cur->getConstructor();\n cur->getAddr().printRaw(s);\n s << \": \";\n ct->printMnemonic(s,*cur);\n s << \" \";\n ct->printBody(s,*cur);\n err.explain = s.str();\n err.instruction_length = fallOffset;\n throw err;\n }\n return fallOffset;\n}\n\nvoid Sleigh::registerContext(const string &name,int4 sbit,int4 ebit)\n\n{\n context_db->registerVariable(name,sbit,ebit);\n}\n\nvoid Sleigh::setContextDefault(const string &name,uintm val)\n\n{\n context_db->setVariableDefault(name,val);\n}\n\nvoid Sleigh::allowContextSet(bool val) const\n\n{\n cache->allowSet(val);\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/sleigh.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file sleigh.hh\n/// \\brief Classes and utilities for the main SLEIGH engine\n\n#ifndef __SLEIGH_HH__\n#define __SLEIGH_HH__\n\n#include \"sleighbase.hh\"\n\nnamespace ghidra {\n\nclass LoadImage;\n\n/// \\brief Class for describing a relative p-code branch destination\n///\n/// An intra-instruction p-code branch takes a \\e relative operand.\n/// The actual value produced during p-code generation is calculated at\n/// the last second using \\b this. It stores the index of the BRANCH\n/// instruction and a reference to its destination operand. This initially\n/// holds a reference to a destination \\e label symbol, but is later updated\n/// with the final relative value.\nstruct RelativeRecord {\n VarnodeData *dataptr;\t\t///< Varnode indicating relative offset\n uintb calling_index;\t\t///< Index of instruction containing relative offset\n};\n\n/// \\brief Data for building one p-code instruction\n///\n/// Raw data used by the emitter to produce a single PcodeOp\nstruct PcodeData {\n OpCode opc;\t\t\t///< The op code\n VarnodeData *outvar;\t \t///< Output Varnode data (or null)\n VarnodeData *invar;\t\t///< Array of input Varnode data\n int4 isize;\t\t\t///< Number of input Varnodes\n};\n\n/// \\brief Class for caching a chunk of p-code, prior to emitting\n///\n/// The engine accumulates PcodeData and VarnodeData objects for\n/// a single instruction. Once the full instruction is constructed,\n/// the objects are passed to the emitter (PcodeEmit) via the emit() method.\n/// The class acts as a pool of memory for PcodeData and VarnodeData objects\n/// that can be reused repeatedly to emit multiple instructions.\nclass PcodeCacher {\n VarnodeData *poolstart;\t\t///< Start of the pool of VarnodeData objects\n VarnodeData *curpool;\t\t\t///< First unused VarnodeData\n VarnodeData *endpool;\t\t\t///< End of the pool of VarnodeData objects\n vector issued;\t\t///< P-code ops issued for the current instruction\n list label_refs;\t///< References to labels\n vector labels;\t\t\t///< Locations of labels\n VarnodeData *expandPool(uint4 size);\t///< Expand the memory pool\npublic:\n PcodeCacher(void);\t\t///< Constructor\n ~PcodeCacher(void);\t\t///< Destructor\n\n /// \\brief Allocate data objects for a new set of Varnodes\n ///\n /// \\param size is the number of objects to allocate\n /// \\return a pointer to the array of available VarnodeData objects\n VarnodeData *allocateVarnodes(uint4 size) {\n VarnodeData *newptr = curpool + size;\n if (newptr <= endpool) {\n VarnodeData *res = curpool;\n curpool = newptr;\n return res;\n }\n return expandPool(size);\n }\n\n /// \\brief Allocate a data object for a new p-code operation\n ///\n /// \\return the new PcodeData object\n PcodeData *allocateInstruction(void) {\n issued.emplace_back();\n PcodeData *res = &issued.back();\n res->outvar = (VarnodeData *)0;\n res->invar = (VarnodeData *)0;\n return res;\n }\n void addLabelRef(VarnodeData *ptr);\t///< Denote a Varnode holding a \\e relative \\e branch offset\n void addLabel(uint4 id);\t\t///< Attach a label to the \\e next p-code instruction\n void clear(void);\t\t\t///< Reset the cache so that all objects are unallocated\n void resolveRelatives(void);\t\t///< Rewrite branch target Varnodes as \\e relative offsets\n void emit(const Address &addr,PcodeEmit *emt) const;\t///< Pass the cached p-code data to the emitter\n};\n\n/// \\brief A container for disassembly context used by the SLEIGH engine\n///\n/// This acts as a factor for the ParserContext objects which are used to disassemble\n/// a single instruction. These all share a ContextCache which is a front end for\n/// accessing the ContextDatabase and resolving context variables from the SLEIGH spec.\n/// ParserContext objects are stored in a hash-table keyed by the address of the instruction.\nclass DisassemblyCache {\n Translate *translate;\t\t///< The Translate object that owns this cache\n ContextCache *contextcache;\t///< Cached values from the ContextDatabase\n AddrSpace *constspace;\t///< The constant address space\n int4 minimumreuse;\t\t///< Can call getParserContext this many times, before a ParserContext is reused\n uint4 mask;\t\t\t///< Size of the hashtable in form 2^n-1\n ParserContext **list;\t\t///< (circular) array of currently cached ParserContext objects\n int4 nextfree;\t\t///< Current end/beginning of circular list\n ParserContext **hashtable;\t///< Hashtable for looking up ParserContext via Address\n void initialize(int4 min,int4 hashsize);\t///< Initialize the hash-table of ParserContexts\n void free(void);\t\t///< Free the hash-table of ParserContexts\npublic:\n DisassemblyCache(Translate *trans,ContextCache *ccache,AddrSpace *cspace,int4 cachesize,int4 windowsize);\t///< Constructor\n ~DisassemblyCache(void) { free(); }\t///< Destructor\n ParserContext *getParserContext(const Address &addr);\t\t///< Get the parser for a particular Address\n void fastReset(); ///< Reset parser states to uninitialized\n};\n\n/// \\brief Build p-code from a pre-parsed instruction\n///\n/// Through the build() method, \\b this walks the parse tree and prepares data\n/// for final emission as p-code. (The final emitting is done separately through the\n/// PcodeCacher.emit() method). Generally, only p-code for one instruction is prepared.\n/// But, through the \\b delay-slot mechanism, build() may recursively visit\n/// additional instructions.\nclass SleighBuilder : public PcodeBuilder {\n virtual void dump( OpTpl *op );\n AddrSpace *const_space;\t\t///< The constant address space\n AddrSpace *uniq_space;\t\t///< The unique address space\n uintb uniquemask;\t\t\t///< Mask of address bits to use to uniquify temporary registers\n uintb uniqueoffset;\t\t\t///< Uniquifier bits for \\b this instruction\n DisassemblyCache *discache;\t\t///< Cache of disassembled instructions\n PcodeCacher *cache;\t\t\t///< Cache accumulating p-code data for the instruction\n void buildEmpty(Constructor *ct,int4 secnum);\n void generateLocation(const VarnodeTpl *vntpl,VarnodeData &vn);\n AddrSpace *generatePointer(const VarnodeTpl *vntpl,VarnodeData &vn);\n void generatePointerAdd(PcodeData *op,const VarnodeTpl *vntpl);\n void setUniqueOffset(const Address &addr);\t///< Set uniquifying bits for the current instruction\npublic:\n SleighBuilder(ParserWalker *w,DisassemblyCache *dcache,PcodeCacher *pc,AddrSpace *cspc,AddrSpace *uspc,uint4 umask);\n virtual void appendBuild(OpTpl *bld,int4 secnum);\n virtual void delaySlot(OpTpl *op);\n virtual void setLabel(OpTpl *op);\n virtual void appendCrossBuild(OpTpl *bld,int4 secnum);\n};\n\n/// \\brief A full SLEIGH engine\n///\n/// Its provided with a LoadImage of the bytes to be disassembled and\n/// a ContextDatabase.\n///\n/// Assembly is produced via the printAssembly() method, provided with an\n/// AssemblyEmit object and an Address.\n///\n/// P-code is produced via the oneInstruction() method, provided with a PcodeEmit\n/// object and an Address.\nclass Sleigh : public SleighBase {\n LoadImage *loader;\t\t\t///< The mapped bytes in the program\n ContextDatabase *context_db;\t\t///< Database of context values steering disassembly\n ContextCache *cache;\t\t\t///< Cache of recently used context values\n mutable DisassemblyCache *discache;\t///< Cache of recently parsed instructions\n mutable PcodeCacher pcode_cache;\t///< Cache of p-code data just prior to emitting\n void clearForDelete(void);\t\t///< Delete the context and disassembly caches\nprotected:\n ParserContext *obtainContext(const Address &addr,int4 state) const;\n void resolve(ParserContext &pos) const;\t///< Generate a parse tree suitable for disassembly\n void resolveHandles(ParserContext &pos) const;\t///< Prepare the parse tree for p-code generation\npublic:\n Sleigh(LoadImage *ld,ContextDatabase *c_db);\t\t///< Constructor\n virtual ~Sleigh(void);\t\t\t\t///< Destructor\n void reset(LoadImage *ld,ContextDatabase *c_db);\t///< Reset the engine for a new program\n void fastReset();\t\t\t\t\t///< Quickly reset the engine\n virtual void initialize(DocumentStorage &store);\n virtual void registerContext(const string &name,int4 sbit,int4 ebit);\n virtual void setContextDefault(const string &nm,uintm val);\n virtual void allowContextSet(bool val) const;\n virtual int4 instructionLength(const Address &baseaddr) const;\n virtual int4 oneInstruction(PcodeEmit &emit,const Address &baseaddr) const;\n virtual int4 printAssembly(AssemblyEmit &emit,const Address &baseaddr) const;\n};\n\n/** \\page sleigh SLEIGH\n\n \\section sleightoc Table of Contents\n\n - \\ref sleighoverview\n - \\ref sleighbuild\n - \\ref sleighuse\n - \\subpage sleighAPIbasic\n - \\subpage sleighAPIemulate\n\n \\b Key \\b Classes\n - \\ref Translate\n - \\ref AssemblyEmit\n - \\ref PcodeEmit\n - \\ref LoadImage\n - \\ref ContextDatabase\n\n \\section sleighoverview Overview\n\n Welcome to \\b SLEIGH, a machine language translation and\n dissassembly engine. SLEIGH is both a processor\n specification language and the associated library and\n tools for using such a specification to generate assembly\n and to generate \\b pcode, a reverse engineering Register\n Transfer Language (RTL), from binary machine instructions.\n \n SLEIGH was originally based on \\b SLED, a\n \\e Specification \\e Language \\e for \\e Encoding \\e and\n \\e Decoding, designed by Norman Ramsey and Mary F. Fernandez,\n which performed disassembly (and assembly). SLEIGH\n extends SLED by providing semantic descriptions (via the\n RTL) of machine instructions and other practical enhancements\n for doing real world reverse engineering. \n\n SLEIGH is part of Project \\b GHIDRA. It provides the core\n of the GHIDRA disassembler and the data-flow and\n decompilation analysis. However, SLEIGH can serve as a\n standalone library for use in other applications for\n providing a generic disassembly and RTL translation interface.\n\n \\section sleighbuild Building SLEIGH\n\n There are a couple of \\e make targets for building the SLEIGH\n library from source. These are:\n\n \\code\n make libsla.a # Build the main library\n\n make libsla_dbg.a # Build the library with debug symbols\n \\endcode\n\n The source code file \\e sleighexample.cc has a complete example\n of initializing the Translate engine and using it to generate\n assembly and pcode. The source has a hard-coded file name,\n \\e x86testcode, as the example binary executable it attempts\n to decode, but this can easily be changed. It also needs\n a SLEIGH specification file (\\e .sla) to be present.\n\n Building the example application can be done with something\n similar to the following makefile fragment.\n\n \\code\n # The C compiler\n CXX=g++\n\n # Debug flags\n DBG_CXXFLAGS=-g -Wall -Wno-sign-compare\n\n OPT_CXXFLAGS=-O2 -Wall -Wno-sign-compare\n\n # libraries\n INCLUDES=-I./src\n\n LNK=src/libsla_dbg.a\n\n sleighexample.o: sleighexample.cc\n $(CXX) -c $(DBG_CXXFLAGS) -o sleighexample sleighexample.o $(LNK)\n \n clean:\n rm -rf *.o sleighexample\n \\endcode\n\n \\section sleighuse Using SLEIGH\n\n SLEIGH is a generic reverse engineering tool in the sense\n that the API is designed to be completely processor\n independent. In order to process binary executables for a\n specific processor, The library reads in a \\e\n specification \\e file, which describes how instructions\n are encoded and how they are interpreted by the processor.\n An application which needs to do disassembly or generate\n \\b pcode can design to the SLEIGH API once, and then the\n application will automatically support any processor for\n which there is a specification.\n \n For working with a single processor, the SLEIGH library\n needs to load a single \\e compiled form of the processor\n specification, which is traditionally given a \".sla\" suffix.\n Most common processors already have a \".sla\" file available.\n So to use SLEIGH with these processors, the library merely\n needs to be made aware of the desired file. This documentation\n covers the use of the SLEIGH API, assuming that this\n specification file is available.\n\n The \".sla\" files themselves are created by running\n the \\e compiler on a file written in the formal SLEIGH\n language. These files traditionally have the suffix \".slaspec\"\n For those who want to design such a specification for a new\n processor, please refer to the document, \"SLEIGH: A Language\n for Rapid Processor Specification.\"\n\n */\n\n /**\n \\page sleighAPIbasic The Basic SLEIGH Interface\n\n To use SLEIGH as a library within an application, there\n are basically five classes that you need to be aware of.\n\n - \\ref sleightranslate\n - \\ref sleighassememit\n - \\ref sleighpcodeemit\n - \\ref sleighloadimage\n - \\ref sleighcontext\n \n \\section sleightranslate Translate (or Sleigh)\n\n The core SLEIGH class is Sleigh, which is derived from the\n interface, Translate. In order to instantiate it in your code,\n you need a LoadImage object, and a ContextDatabase object.\n The load image is responsible for retrieving instruction\n bytes, based on address, from a binary executable. The context\n database provides the library extra mode information that may\n be necessary to do the disassembly or translation. This can\n be used, for instance, to specify that an x86 binary is running\n in 32-bit mode, or to specify that an ARM processor is running\n in THUMB mode. Once these objects are built, the Sleigh\n object can be immediately instantiated.\n\n \\code\n LoadImageBfd *loader;\n ContextDatabase *context;\n Translate *trans;\n\n // Set up the loadimage\n // Providing an executable name and architecture\n string loadimagename = \"x86testcode\";\n string bfdtarget= \"default\";\n\n loader = new LoadImageBfd(loadimagename,bfdtarget);\n loader->open(); // Load the executable from file\n\n context = new ContextInternal(); // Create a processor context\n\n trans = new Sleigh(loader,context); // Instantiate the translator\n \\endcode\n\n Once the Sleigh object is in hand, the only required\n initialization step left is to inform it of the \".sla\" file.\n The file is in XML format and needs to be read in using\n SLEIGH's built-in XML parser. The following code accomplishes\n this.\n\n \\code\n string sleighfilename = \"specfiles/x86.sla\";\n DocumentStorage docstorage;\n Element *sleighroot = docstorage.openDocument(sleighfilename)->getRoot();\n docstorage.registerTag(sleighroot);\n trans->initialize(docstorage); // Initialize the translator\n \\endcode\n\n \\section sleighassememit AssemblyEmit\n\n In order to do disassembly, you need to derive a class from\n AssemblyEmit, and implement the method \\e dump. The library\n will call this method exactly once, for each instruction\n disassembled.\n\n This routine simply needs to decide how (and where) to print\n the corresponding portion of the disassembly. For instance,\n\n \\code\n class AssemblyRaw : public AssemblyEmit {\n public:\n virtual void dump(const Address &addr,const string &mnem,const string &body) {\n addr.printRaw(cout);\n cout << \": \" << mnem << ' ' << body << endl;\n }\n };\n \\endcode\n\n This is a minimal implementation that simply dumps the\n disassembly straight to standard out. Once this object is\n instantiated, the Sleigh object can use it to write out\n assembly via the Translate::printAssembly() method.\n\n \\code\n AssemblyEmit *assememit = new AssemblyRaw();\n\n Address addr(trans->getDefaultCodeSpace(),0x80484c0);\n int4 length; // Length of instruction in bytes\n\n length = trans->printAssembly(*assememit,addr);\n addr = addr + length; // Advance to next instruction\n length = trans->printAssembly(*assememit,addr);\n addr = addr + length;\n length = trans->printAssembly(*assememit,addr);\n \\endcode\n\n \\section sleighpcodeemit PcodeEmit\n\n In order to generate a \\b pcode translation of a machine\n instruction, you need to derive a class from PcodeEmit and\n implement the virtual method \\e dump. This method will be\n invoked once for each \\b pcode operation in the translation\n of a machine instruction. There will likely be multiple calls\n per instruction. Each call passes in a single \\b pcode\n operation, complete with its possible varnode output, and\n all of its varnode inputs. Here is an example of a PcodeEmit\n object that simply prints out the \\b pcode.\n\n \\code\n class PcodeRawOut : public PcodeEmit {\n public:\n virtual void dump(const Address &addr,OpCode opc,VarnodeData *outvar,VarnodeData *vars,int4 isize);\n };\n\n static void print_vardata(ostream &s,VarnodeData &data)\n\n {\n s << '(' << data.space->getName() << ',';\n data.space->printOffset(s,data.offset);\n s << ',' << dec << data.size << ')';\n }\n\n void PcodeRawOut::dump(const Address &addr,OpCode opc,VarnodeData *outvar,VarnodeData *vars,int4 isize)\n\n {\n if (outvar != (VarnodeData *)0) { // The output is optional\n print_vardata(cout,*outvar);\n cout << \" = \";\n }\n cout << get_opname(opc);\n // Possibly check for a code reference or a space reference\n for(int4 i=0;igetDefaultCodeSpace(),0x80484c0);\n int4 length; // Length of instruction in bytes\n\n length = trans->oneInstruction(*pcodeemit,addr);\n addr = addr + length; // Advance to next instruction\n length = trans->oneInstruction(*pcodeemit,addr);\n addr = addr + length;\n length = trans->oneInstruction(*pcodeemit,addr);\n \\endcode\n\n For an application to properly \\e follow \\e flow, while translating\n machine instructions into pcode, the emitted pcode must be\n inspected for the various branch operations.\n\n \\section sleighloadimage LoadImage\n\n A LoadImage holds all the binary data from an executable file\n in the format similar to how it would exist when being executed\n by a real processor. The interface to this from SLEIGH is\n actually very simple, although it can hide a complicated\n structure. One method does most of the work, LoadImage::loadFill().\n It takes a byte pointer, a size, and an Address. The method\n is expected to fill in the \\e ptr array with \\e size bytes\n taken from the load image, corresponding to the address \\e addr.\n There are two more virtual methods that are required for a\n complete implementation of LoadImage, \\e getArchType and\n \\e adjustVma, but these do not need to be implemented fully.\n\n \\code\n class MyLoadImage : public LoadImage {\n public:\n MyLoadImage(const string &nm) : Loadimage(nm) {}\n virtual void loadFill(uint1 *ptr,int4 size,const Address &addr);\n virtual string getArchType(void) const { return \"mytype\"; }\n virtual void adjustVma(long adjust) {}\n };\n \\endcode\n\n \\section sleighcontext ContextDatabase\n\n The ContextDatabase needs to keep track of any possible\n context variable and its value, over different address ranges.\n In most cases, you probably don't need to override the class\n yourself, but can use the built-in class, ContextInternal.\n This provides the basic functionality required and will work\n for different architectures. What you may need to do is\n set values for certain variables, depending on the processor\n and the environment it is running in. For instance, for\n the x86 platform, you need to set the \\e addrsize and \\e opsize\n bits, to indicate the processor would be running in 32-bit\n mode. The context variables specific to a particular processor\n are established by the SLEIGH spec. So the variables can\n only be set \\e after the spec has been loaded.\n\n \\code\n ...\n context = new ContextInternal();\n trans = new Sleigh(loader,context);\n DocumentStorage docstorage;\n Element *root = docstorage.openDocument(\"specfiles/x86.sla\")->getRoot();\n docstorage.registerTag(root);\n trans->initialize(docstorage);\n\n context->setVariableDefault(\"addrsize\",1); // Address size is 32-bits\n context->setVariableDefault(\"opsize\",1); // Operand size is 32-bits\n \\endcode\n\n \n */\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/sleighbase.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"sleighbase.hh\"\n\nnamespace ghidra {\n\nconst uint4 SleighBase::MAX_UNIQUE_SIZE = 256;\n\nint4 SourceFileIndexer::index(const string filename){\n\tauto it = fileToIndex.find(filename);\n\tif (fileToIndex.end() != it){\n\t\treturn it->second;\n\t}\n\tfileToIndex[filename] = leastUnusedIndex;\n\tindexToFile[leastUnusedIndex] = filename;\n\treturn leastUnusedIndex++;\n}\n\nint4 SourceFileIndexer::getIndex(string filename){\n\treturn fileToIndex[filename];\n}\n\nstring SourceFileIndexer::getFilename(int4 index){\n\treturn indexToFile[index];\n}\n\nvoid SourceFileIndexer::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_SOURCEFILES);\n while(decoder.peekElement() == sla::ELEM_SOURCEFILE) {\n int4 subel = decoder.openElement();\n string filename = decoder.readString(sla::ATTRIB_NAME);\n int4 index = decoder.readSignedInteger(sla::ATTRIB_INDEX);\n decoder.closeElement(subel);\n fileToIndex[filename] = index;\n indexToFile[index] = filename;\n }\n decoder.closeElement(el);\n}\n\nvoid SourceFileIndexer::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_SOURCEFILES);\n for (int4 i = 0; i < leastUnusedIndex; ++i){\n encoder.openElement(sla::ELEM_SOURCEFILE);\n encoder.writeString(sla::ATTRIB_NAME, indexToFile.at(i));\n encoder.writeSignedInteger(sla::ATTRIB_INDEX, i);\n encoder.closeElement(sla::ELEM_SOURCEFILE);\n }\n encoder.closeElement(sla::ELEM_SOURCEFILES);\n}\n\nSleighBase::SleighBase(void)\n\n{\n root = (SubtableSymbol *)0;\n maxdelayslotbytes = 0;\n unique_allocatemask = 0;\n numSections = 0;\n}\n\n/// Assuming the symbol table is populated, iterate through the table collecting\n/// registers (for the map), user-op names, and context fields.\nvoid SleighBase::buildXrefs(vector &errorPairs)\n\n{\n SymbolScope *glb = symtab.getGlobalScope();\n SymbolTree::const_iterator iter;\n SleighSymbol *sym;\n ostringstream s;\n\n for(iter=glb->begin();iter!=glb->end();++iter) {\n sym = *iter;\n if (sym->getType() == SleighSymbol::varnode_symbol) {\n pair ins(((VarnodeSymbol *)sym)->getFixedVarnode(),sym->getName());\n pair::iterator,bool> res = varnode_xref.insert(ins);\n if (!res.second) {\n\terrorPairs.push_back(sym->getName());\n\terrorPairs.push_back((*(res.first)).second);\n }\n }\n else if (sym->getType() == SleighSymbol::userop_symbol) {\n int4 index = ((UserOpSymbol *)sym)->getIndex();\n while(userop.size() <= index)\n\tuserop.push_back(\"\");\n userop[index] = sym->getName();\n }\n else if (sym->getType() == SleighSymbol::context_symbol) {\n ContextSymbol *csym = (ContextSymbol *)sym;\n ContextField *field = (ContextField *)csym->getPatternValue();\n int4 startbit = field->getStartBit();\n int4 endbit = field->getEndBit();\n registerContext(csym->getName(),startbit,endbit);\n }\n }\n}\n\n/// If \\b this SleighBase is being reused with a new program, the context\n/// variables need to be registered with the new program's database\nvoid SleighBase::reregisterContext(void)\n\n{\n SymbolScope *glb = symtab.getGlobalScope();\n SymbolTree::const_iterator iter;\n SleighSymbol *sym;\n for(iter=glb->begin();iter!=glb->end();++iter) {\n sym = *iter;\n if (sym->getType() == SleighSymbol::context_symbol) {\n ContextSymbol *csym = (ContextSymbol *)sym;\n ContextField *field = (ContextField *)csym->getPatternValue();\n int4 startbit = field->getStartBit();\n int4 endbit = field->getEndBit();\n registerContext(csym->getName(),startbit,endbit);\n }\n }\n}\n\nconst VarnodeData &SleighBase::getRegister(const string &nm) const\n\n{\n VarnodeSymbol *sym = (VarnodeSymbol *)findSymbol(nm);\n if (sym == (VarnodeSymbol *)0)\n throw SleighError(\"Unknown register name: \"+nm);\n if (sym->getType() != SleighSymbol::varnode_symbol)\n throw SleighError(\"Symbol is not a register: \"+nm);\n return sym->getFixedVarnode();\n}\n\nstring SleighBase::getRegisterName(AddrSpace *base,uintb off,int4 size) const\n\n{\n VarnodeData sym;\n sym.space = base;\n sym.offset = off;\n sym.size = size;\n map::const_iterator iter = varnode_xref.upper_bound(sym); // First point greater than offset\n if (iter == varnode_xref.begin()) return \"\";\n iter--;\n const VarnodeData &point((*iter).first);\n if (point.space != base) return \"\";\n uintb offbase = point.offset;\n if (point.offset+point.size >= off+size)\n return (*iter).second;\n \n while(iter != varnode_xref.begin()) {\n --iter;\n const VarnodeData &point((*iter).first);\n if ((point.space != base)||(point.offset != offbase)) return \"\";\n if (point.offset+point.size >= off+size)\n return (*iter).second;\n }\n return \"\";\n}\n\nstring SleighBase::getExactRegisterName(AddrSpace *base,uintb off,int4 size) const\n\n{\n VarnodeData sym;\n sym.space = base;\n sym.offset = off;\n sym.size = size;\n map::const_iterator iter = varnode_xref.find(sym);\n if (iter == varnode_xref.end()) return \"\";\n return (*iter).second;\n}\n\nvoid SleighBase::getAllRegisters(map ®list) const\n\n{\n reglist = varnode_xref;\n}\n\nvoid SleighBase::getUserOpNames(vector &res) const\n\n{\n res = userop;\t\t// Return list of all language defined user ops (with index)\n}\n\n/// Write a tag fully describing the details of the space.\n/// \\param encoder is the stream being written\n/// \\param spc is the given address space\nvoid SleighBase::encodeSlaSpace(Encoder &encoder,AddrSpace *spc) const\n\n{\n if (spc->getType() == IPTR_INTERNAL)\n encoder.openElement(sla::ELEM_SPACE_UNIQUE);\n else if (spc->isOtherSpace())\n encoder.openElement(sla::ELEM_SPACE_OTHER);\n else\n encoder.openElement(sla::ELEM_SPACE);\n encoder.writeString(sla::ATTRIB_NAME,spc->getName());\n encoder.writeSignedInteger(sla::ATTRIB_INDEX, spc->getIndex());\n encoder.writeBool(sla::ATTRIB_BIGENDIAN, isBigEndian());\n encoder.writeSignedInteger(sla::ATTRIB_DELAY, spc->getDelay());\n// if (spc->getDelay() != spc->getDeadcodeDelay())\n// encoder.writeSignedInteger(sla::ATTRIB_DEADCODEDELAY, spc->getDeadcodeDelay());\n encoder.writeSignedInteger(sla::ATTRIB_SIZE, spc->getAddrSize());\n if (spc->getWordSize() > 1)\n encoder.writeSignedInteger(sla::ATTRIB_WORDSIZE, spc->getWordSize());\n encoder.writeBool(sla::ATTRIB_PHYSICAL, spc->hasPhysical());\n if (spc->getType() == IPTR_INTERNAL)\n encoder.closeElement(sla::ELEM_SPACE_UNIQUE);\n else if (spc->isOtherSpace())\n encoder.closeElement(sla::ELEM_SPACE_OTHER);\n else\n encoder.closeElement(sla::ELEM_SPACE);\n}\n\n/// This does the bulk of the work of creating a .sla file\n/// \\param encoder is the stream encoder\nvoid SleighBase::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_SLEIGH);\n encoder.writeSignedInteger(sla::ATTRIB_VERSION, sla::FORMAT_VERSION);\n encoder.writeBool(sla::ATTRIB_BIGENDIAN, isBigEndian());\n encoder.writeSignedInteger(sla::ATTRIB_ALIGN, alignment);\n encoder.writeUnsignedInteger(sla::ATTRIB_UNIQBASE, getUniqueBase());\n if (maxdelayslotbytes > 0)\n encoder.writeUnsignedInteger(sla::ATTRIB_MAXDELAY, maxdelayslotbytes);\n if (unique_allocatemask != 0)\n encoder.writeUnsignedInteger(sla::ATTRIB_UNIQMASK, unique_allocatemask);\n if (numSections != 0)\n encoder.writeUnsignedInteger(sla::ATTRIB_NUMSECTIONS, numSections);\n indexer.encode(encoder);\n encoder.openElement(sla::ELEM_SPACES);\n encoder.writeString(sla::ATTRIB_DEFAULTSPACE, getDefaultCodeSpace()->getName());\n for(int4 i=0;igetType()==IPTR_CONSTANT) || \n\t(spc->getType()==IPTR_FSPEC)||\n\t(spc->getType()==IPTR_IOP)||\n\t(spc->getType()==IPTR_JOIN))\n continue;\n encodeSlaSpace(encoder,spc);\n }\n encoder.closeElement(sla::ELEM_SPACES);\n symtab.encode(encoder);\n encoder.closeElement(sla::ELEM_SLEIGH);\n}\n\n/// This is identical to the functionality of decodeSpace, but the AddrSpace information is stored\n/// in the .sla file format.\n/// \\param decoder is the stream decoder\n/// \\param trans is the translator object to be associated with the new space\n/// \\return a pointer to the initialized AddrSpace\nAddrSpace *SleighBase::decodeSlaSpace(Decoder &decoder,const Translate *trans)\n\n{\n uint4 elemId = decoder.openElement();\n AddrSpace *res;\n int4 index = 0;\n int4 addressSize = 0;\n int4 delay = -1;\n int4 deadcodedelay = -1;\n string name;\n int4 wordsize = 1;\n bool bigEnd = false;\n uint4 flags = 0;\n for (;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == sla::ATTRIB_NAME) {\n name = decoder.readString();\n }\n if (attribId == sla::ATTRIB_INDEX)\n index = decoder.readSignedInteger();\n else if (attribId == sla::ATTRIB_SIZE)\n addressSize = decoder.readSignedInteger();\n else if (attribId == sla::ATTRIB_WORDSIZE)\n wordsize = decoder.readSignedInteger();\n else if (attribId == sla::ATTRIB_BIGENDIAN) {\n bigEnd = decoder.readBool();\n }\n else if (attribId == sla::ATTRIB_DELAY)\n delay = decoder.readSignedInteger();\n else if (attribId == sla::ATTRIB_PHYSICAL) {\n if (decoder.readBool())\n\tflags |= AddrSpace::hasphysical;\n }\n }\n decoder.closeElement(elemId);\n if (deadcodedelay == -1)\n deadcodedelay = delay;\t// If deadcodedelay attribute not present, set it to delay\n if (index == 0)\n throw LowlevelError(\"Expecting index attribute\");\n if (elemId == sla::ELEM_SPACE_UNIQUE)\n res = new UniqueSpace(this,trans,index,flags);\n else if (elemId == sla::ELEM_SPACE_OTHER)\n res = new OtherSpace(this,trans,index);\n else {\n if (addressSize == 0 || delay == -1 || name.size() == 0)\n throw LowlevelError(\"Expecting size/delay/name attributes\");\n res = new AddrSpace(this,trans,IPTR_PROCESSOR,name,bigEnd,addressSize,wordsize,index,flags,delay,deadcodedelay);\n }\n\n return res;\n}\n\n/// This is identical in functionality to decodeSpaces but the AddrSpace information\n/// is stored in the .sla file format.\n/// \\param decoder is the stream decoder\n/// \\param trans is the processor translator to be associated with the spaces\nvoid SleighBase::decodeSlaSpaces(Decoder &decoder,const Translate *trans)\n\n{\n // The first space should always be the constant space\n insertSpace(new ConstantSpace(this,trans));\n\n uint4 elemId = decoder.openElement(sla::ELEM_SPACES);\n string defname = decoder.readString(sla::ATTRIB_DEFAULTSPACE);\n while(decoder.peekElement() != 0) {\n AddrSpace *spc = decodeSlaSpace(decoder,trans);\n insertSpace(spc);\n }\n decoder.closeElement(elemId);\n AddrSpace *spc = getSpaceByName(defname);\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"Bad 'defaultspace' attribute: \"+defname);\n setDefaultCodeSpace(spc->getIndex());\n}\n\n/// This parses the main \\ tag (from a .sla file), which includes the description\n/// of address spaces and the symbol table, with its associated decoding tables\n/// \\param decoder is the stream to decode\nvoid SleighBase::decode(Decoder &decoder)\n\n{\n maxdelayslotbytes = 0;\n unique_allocatemask = 0;\n numSections = 0;\n int4 version = 0;\n uint4 el = decoder.openElement(sla::ELEM_SLEIGH);\n uint4 attrib = decoder.getNextAttributeId();\n while(attrib != 0) {\n if (attrib == sla::ATTRIB_BIGENDIAN)\n setBigEndian(decoder.readBool());\n else if (attrib == sla::ATTRIB_ALIGN)\n alignment = decoder.readSignedInteger();\n else if (attrib == sla::ATTRIB_UNIQBASE)\n setUniqueBase(decoder.readUnsignedInteger());\n else if (attrib == sla::ATTRIB_MAXDELAY)\n maxdelayslotbytes = decoder.readUnsignedInteger();\n else if (attrib == sla::ATTRIB_UNIQMASK)\n unique_allocatemask = decoder.readUnsignedInteger();\n else if (attrib == sla::ATTRIB_NUMSECTIONS)\n numSections = decoder.readUnsignedInteger();\n else if (attrib == sla::ATTRIB_VERSION)\n version = decoder.readSignedInteger();\n attrib = decoder.getNextAttributeId();\n }\n if (version != sla::FORMAT_VERSION)\n throw LowlevelError(\".sla file has wrong format\");\n indexer.decode(decoder);\n decodeSlaSpaces(decoder,this);\n symtab.decode(decoder,this);\n decoder.closeElement(el);\n root = (SubtableSymbol *)symtab.getGlobalScope()->findSymbol(\"instruction\");\n vector errorPairs;\n buildXrefs(errorPairs);\n if (!errorPairs.empty())\n throw SleighError(\"Duplicate register pairs\");\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/sleighbase.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file sleighbase.hh\n/// \\brief Base class for applications that process SLEIGH format specifications\n#ifndef __SLEIGHBASE_HH__\n#define __SLEIGHBASE_HH__\n\n#include \"translate.hh\"\n#include \"slaformat.hh\"\n#include \"slghsymbol.hh\"\n\nnamespace ghidra {\n\n/// \\brief class for recording source file information for SLEIGH constructors.\n\n///\n/// A SLEIGH specification may contain many source files. This class is\n/// used to associate each constructor in a SLEIGH language to the source\n/// file where it is defined. This information is useful when debugging\n/// SLEIGH specifications. Sourcefiles are assigned a numeric index and\n/// the mapping from indices to filenames is written to the generated .sla\n/// file. For each constructor, the data written to the .sla file includes\n/// the source file index.\nclass SourceFileIndexer {\npublic:\n SourceFileIndexer() {leastUnusedIndex = 0;}\n ~SourceFileIndexer(void) { }\n ///Returns the index of the file. If the file is not in the index it is added.\n int4 index(const string filename);\n int4 getIndex(const string);\t///< get the index of a file. Error if the file is not in the index.\n string getFilename(int4);\t///< get the filename corresponding to an index\n void decode(Decoder &decoder);\t///< decode a stored index mapping from a stream\n void encode(Encoder &encoder) const;\t///< Encode the index mapping to stream\n\nprivate:\n int4 leastUnusedIndex; ///< one-up count for assigning indices to files\n map indexToFile; ///< map from indices to files\n map fileToIndex; ///< map from files to indices\n};\n\n/// \\brief Common core of classes that read or write SLEIGH specification files natively.\n\n///\n/// This class represents what's in common across the SLEIGH infrastructure between:\n/// - Reading the various SLEIGH specification files\n/// - Building and writing out SLEIGH specification files\nclass SleighBase : public Translate {\n vector userop;\t\t///< Names of user-define p-code ops for \\b this Translate object\n map varnode_xref;\t///< A map from Varnodes in the \\e register space to register names\nprotected:\n SubtableSymbol *root;\t\t///< The root SLEIGH decoding symbol\n SymbolTable symtab;\t\t///< The SLEIGH symbol table\n uint4 maxdelayslotbytes;\t///< Maximum number of bytes in a delay-slot directive\n uint4 unique_allocatemask;\t///< Bits that are guaranteed to be zero in the unique allocation scheme\n uint4 numSections;\t\t///< Number of \\e named sections\n SourceFileIndexer indexer; ///< source file index used when generating SLEIGH constructor debug info\n void buildXrefs(vector &errorPairs);\t///< Build register map. Collect user-ops and context-fields.\n void reregisterContext(void);\t///< Reregister context fields for a new executable\n AddrSpace *decodeSlaSpace(Decoder &decoder,const Translate *trans); ///< Add a space parsed from a .sla file\n void decodeSlaSpaces(Decoder &decoder,const Translate *trans); ///< Restore address spaces from a .sla file\n void decode(Decoder &decoder);\t/// Decode a SELIGH specification from a stream\npublic:\n static const uint4 MAX_UNIQUE_SIZE; ///< Maximum size of a varnode in the unique space (should match value in SleighBase.java)\n SleighBase(void);\t\t///< Construct an uninitialized translator\n bool isInitialized(void) const { return (root != (SubtableSymbol *)0); }\t///< Return \\b true if \\b this is initialized\n virtual ~SleighBase(void) {}\t///< Destructor\n virtual const VarnodeData &getRegister(const string &nm) const;\n virtual string getRegisterName(AddrSpace *base,uintb off,int4 size) const;\n virtual string getExactRegisterName(AddrSpace *base,uintb off,int4 size) const;\n virtual void getAllRegisters(map ®list) const;\n virtual void getUserOpNames(vector &res) const;\n\n SleighSymbol *findSymbol(const string &nm) const { return symtab.findSymbol(nm); }\t///< Find a specific SLEIGH symbol by name in the current scope\n SleighSymbol *findSymbol(uintm id) const { return symtab.findSymbol(id); }\t///< Find a specific SLEIGH symbol by id\n SleighSymbol *findGlobalSymbol(const string &nm) const { return symtab.findGlobalSymbol(nm); }\t///< Find a specific global SLEIGH symbol by name\n void encodeSlaSpace(Encoder &encoder,AddrSpace *spc) const;\t///< Write the details of given space in .sla format\n void encode(Encoder &encoder) const;\t///< Write out the SLEIGH specification as a \\ tag.\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/slgh_compile.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"slgh_compile.hh\"\n#include \"filemanage.hh\"\n#include \n\nextern FILE *sleighin;\t\t// Global pointer to file for lexer\nextern int sleighlex_destroy(void);\n\nnamespace ghidra {\n\nSleighCompile *slgh;\t\t// Global pointer to sleigh object for use with parser\n#ifdef YYDEBUG\nextern int sleighdebug;\t\t// Global debugging state for parser\n#endif\nextern int sleighparse(void);\n\n/// This must be constructed with the \\e main section of p-code, which can contain no p-code\n/// \\param rtl is the \\e main section of p-code\n/// \\param scope is the symbol scope associated with the section\nSectionVector::SectionVector(ConstructTpl *rtl,SymbolScope *scope)\n\n{\n nextindex = -1;\n main.section = rtl;\n main.scope = scope;\n}\n\n/// Associate the new section with \\b nextindex, established prior to parsing\n/// \\param rtl is the \\e named section of p-code\n/// \\param scope is the associated symbol scope\nvoid SectionVector::append(ConstructTpl *rtl,SymbolScope *scope)\n\n{\n while(named.size() <= nextindex)\n named.emplace_back();\n named[ nextindex ] = RtlPair(rtl,scope);\n}\n\n/// Construct with the default qualities for an address space, which\n/// can then be overridden with further parsing.\n/// \\param nm is the name of the address space\nSpaceQuality::SpaceQuality(const string &nm)\n\n{\n name = nm;\n type = ramtype;\n size = 0;\n wordsize = 1;\n isdefault = false;\n}\n\n/// Establish default qualities for the field, which can then be overridden\n/// by further parsing. A name and bit range must always be explicitly given.\n/// \\param nm is the parsed name for the field\n/// \\param l is the parsed lower bound of the bit range\n/// \\param h is the parse upper bound of the bit range\nFieldQuality::FieldQuality(string *nm,uintb *l,uintb *h)\n\n{\n name = *nm;\n low = *l;\n high = *h;\n signext = false;\n flow = true;\n hex = true;\n delete nm;\n delete l;\n delete h;\n}\n\n/// Establish each component of the \\b with block header\n/// \\param s is the subtable (or null)\n/// \\param pq is the pattern to prepend (or null)\n/// \\param cvec is the set of context changes (or null)\nvoid WithBlock::set(SubtableSymbol *s, PatternEquation *pq, vector *cvec)\n\n{\n ss = s;\n pateq = pq;\n if (pateq != (PatternEquation *)0)\n pateq->layClaim();\n if (cvec != (vector *)0) {\n for(int4 i=0;isize();++i)\n contvec.push_back((*cvec)[i]);\t// Lay claim to -cvec-s pointers, we don't clone\n delete cvec;\n }\n}\n\nWithBlock::~WithBlock(void)\n\n{\n if (pateq != (PatternEquation *)0)\n PatternEquation::release(pateq);\n for(int4 i=0;i &stack, PatternEquation *pateq)\n\n{\n list::const_iterator iter;\n for(iter=stack.begin();iter!=stack.end();++iter) {\n PatternEquation *witheq = (*iter).pateq;\n if (witheq != (PatternEquation *)0)\n pateq = new EquationAnd(witheq, pateq);\n }\n return pateq;\n}\n\n/// \\brief Build a complete array of context changes from any surrounding \\b with blocks\n///\n/// Given a list of ContextChanges parsed locally from a Constructor and the stack of\n/// surrounding \\b with blocks, make a new list of ContextChanges, prepending everything from\n/// the stack to the local vector. Return the new list and delete the old.\n/// \\param stack is the current \\b with block stack\n/// \\param contvec is the local list of ContextChanges (or null)\n/// \\return the new list of ContextChanges\nvector *WithBlock::collectAndPrependContext(const list &stack, vector *contvec)\n\n{\n vector *res = (vector *)0;\n list::const_iterator iter;\n for(iter=stack.begin();iter!=stack.end();++iter) {\n const vector &changelist( (*iter).contvec );\n if (changelist.size() == 0) continue;\n if (res == (vector *)0)\n res = new vector();\n for(int4 i=0;ipush_back(changelist[i]->clone());\n }\n }\n if (contvec != (vector *)0) {\n if (contvec->size() != 0) {\n if (res == (vector *)0)\n\tres = new vector();\n for(int4 i=0;isize();++i)\n\tres->push_back((*contvec)[i]);\t\t// lay claim to contvecs pointer\n }\n delete contvec;\n }\n return res;\n}\n\n/// \\brief Get the active subtable from the stack of currently active \\b with blocks\n///\n/// Find the subtable associated with the innermost \\b with block and return it.\n/// \\param stack is the stack of currently active \\b with blocks\n/// \\return the innermost subtable (or null)\nSubtableSymbol *WithBlock::getCurrentSubtable(const list &stack)\n\n{\n list::const_iterator iter;\n for(iter=stack.begin();iter!=stack.end();++iter) {\n if ((*iter).ss != (SubtableSymbol *)0)\n return (*iter).ss;\n }\n return (SubtableSymbol *)0;\n}\n\nvoid ConsistencyChecker::OptimizeRecord::copyFromExcludingSize(ConsistencyChecker::OptimizeRecord &that)\n\n{\n this->writeop = that.writeop;\n this->readop = that.readop;\n this->inslot = that.inslot;\n this->writecount = that.writecount;\n this->readcount = that.readcount;\n this->writesection = that.writesection;\n this->readsection = that.readsection;\n this->opttype = that.opttype;\n}\n\nvoid ConsistencyChecker::OptimizeRecord::update(int4 opIdx, int4 slotIdx, int4 secNum)\n\n{\n if (slotIdx >= 0) {\n updateRead(opIdx, slotIdx, secNum);\n }\n else {\n updateWrite(opIdx, secNum);\n }\n}\n\nvoid ConsistencyChecker::OptimizeRecord::updateRead(int4 i, int4 inslot, int4 secNum)\n\n{\n this->readop = i;\n this->readcount++;\n this->inslot = inslot;\n this->readsection = secNum;\n}\n\nvoid ConsistencyChecker::OptimizeRecord::updateWrite(int4 i, int4 secNum)\n\n{\n this->writeop = i;\n this->writecount++;\n this->writesection = secNum;\n}\n\nvoid ConsistencyChecker::OptimizeRecord::updateExport()\n\n{\n this->writeop = 0;\n this->readop = 0;\n this->writecount = 2;\n this->readcount = 2;\n this->readsection = -2;\n this->writesection = -2;\n}\n\nvoid ConsistencyChecker::OptimizeRecord::updateCombine(ConsistencyChecker::OptimizeRecord &that)\n\n{\n if (that.writecount != 0) {\n this->writeop = that.writeop;\n this->writesection = that.writesection;\n }\n if (that.readcount != 0) {\n this->readop = that.readop;\n this->inslot = that.inslot;\n this->readsection = that.readsection;\n }\n this->writecount += that.writecount;\n this->readcount += that.readcount;\n // opttype is not relevant here\n}\n\n/// \\brief Construct the consistency checker and optimizer\n///\n/// \\param sleigh is the parsed SLEIGH spec\n/// \\param rt is the root subtable of the SLEIGH spec\n/// \\param un is \\b true to request \"Unnecessary extension\" warnings\n/// \\param warndead is \\b true to request warnings for written but not read temporaries\nConsistencyChecker::ConsistencyChecker(SleighCompile *sleigh,SubtableSymbol *rt,bool un,bool warndead)\n\n{\n compiler = sleigh;\n root_symbol = rt;\n unnecessarypcode = 0;\n readnowrite = 0;\n writenoread = 0;\n printextwarning = un;\n printdeadwarning = warndead;\n}\n\n/// \\brief Recover a specific value for the size associated with a Varnode template\n///\n/// This method is passed a ConstTpl that is assumed to be the \\e size attribute of\n/// a VarnodeTpl (as returned by getSize()). This method recovers the specific\n/// integer value for this constant template or throws an exception.\n/// The integer value can either be immediately available from parsing, derived\n/// from a Constructor operand symbol whose size is known, or taken from\n/// the calculated export size of a subtable symbol.\n/// \\param sizeconst is the Varnode size template\n/// \\param ct is the Constructor containing the Varnode\n/// \\return the integer value\nint4 ConsistencyChecker::recoverSize(const ConstTpl &sizeconst,Constructor *ct)\n\n{\n int4 size,handindex;\n OperandSymbol *opsym;\n SubtableSymbol *tabsym;\n map::const_iterator iter;\n\n switch(sizeconst.getType()) {\n case ConstTpl::real:\n size = (int4) sizeconst.getReal();\n break;\n case ConstTpl::handle:\n handindex = sizeconst.getHandleIndex();\n opsym = ct->getOperand(handindex);\n size = opsym->getSize();\n if (size == -1) {\n tabsym = dynamic_cast(opsym->getDefiningSymbol());\n if (tabsym == (SubtableSymbol *)0)\n\tthrow SleighError(\"Could not recover varnode template size\");\n iter = sizemap.find(tabsym);\n if (iter == sizemap.end())\n\tthrow SleighError(\"Subtable out of order\");\n size = (*iter).second;\n }\n break;\n default:\n throw SleighError(\"Bad constant type as varnode template size\");\n }\n return size;\n}\n\n/// \\brief Convert an unnecessary CPUI_INT_ZEXT and CPUI_INT_SEXT into a COPY\n///\n/// SLEIGH allows \\b zext and \\b sext notation even if the input and output\n/// Varnodes are ultimately the same size. In this case, a warning may be\n/// issued and the operator is converted to a CPUI_COPY.\n/// \\param op is the given CPUI_INT_ZEXT or CPUI_INT_SEXT operator to check\n/// \\param ct is the Constructor containing the operator\nvoid ConsistencyChecker::dealWithUnnecessaryExt(OpTpl *op,Constructor *ct)\n\n{\n if (printextwarning) {\n ostringstream msg;\n msg << \"Unnecessary \";\n printOpName(msg,op);\n compiler->reportWarning(compiler->getLocation(ct), msg.str());\n }\n op->setOpcode(CPUI_COPY);\t// Equivalent to copy\n unnecessarypcode += 1;\n}\n\n/// \\brief Convert an unnecessary CPUI_SUBPIECE into a COPY\n///\n/// SLEIGH allows truncation notation even if the input and output Varnodes are\n/// ultimately the same size. In this case, a warning may be issued and the operator\n/// is converted to a CPUI_COPY.\n/// \\param op is the given CPUI_SUBPIECE operator\n/// \\param ct is the containing Constructor\nvoid ConsistencyChecker::dealWithUnnecessaryTrunc(OpTpl *op,Constructor *ct)\n\n{\n if (printextwarning) {\n ostringstream msg;\n msg << \"Unnecessary \";\n printOpName(msg,op);\n compiler->reportWarning(compiler->getLocation(ct), msg.str());\n }\n op->setOpcode(CPUI_COPY);\t// Equivalent to copy\n op->removeInput(1);\n unnecessarypcode += 1;\n}\n\n/// \\brief Check for misuse of the given operator and print a warning\n///\n/// This method currently checks for:\n/// - Unsigned less-than comparison with zero\n///\n/// \\param op is the given operator\n/// \\param ct is the Constructor owning the operator\n/// \\return \\b false if the operator is fatally misused\nbool ConsistencyChecker::checkOpMisuse(OpTpl *op,Constructor *ct)\n\n{\n switch(op->getOpcode()) {\n case CPUI_INT_LESS:\n {\n VarnodeTpl *vn = op->getIn(1);\n if (vn->getSpace().isConstSpace() && vn->getOffset().isZero()) {\n\tcompiler->reportWarning(compiler->getLocation(ct), \"Unsigned comparison with zero is always false\");\n }\n }\n break;\n default:\n break;\n }\n return true;\n}\n\n/// \\brief Make sure the given operator meets size restrictions\n///\n/// Many SLEIGH operators require that inputs and/or outputs are the\n/// same size, or they have other specific size requirement.\n/// Print an error and return \\b false for any violations.\n/// \\param op is the given p-code operator\n/// \\param ct is the Constructor owning the operator\n/// \\return \\b true if there are no size restriction violations\nbool ConsistencyChecker::sizeRestriction(OpTpl *op,Constructor *ct)\n\n{ // Make sure op template meets size restrictions\n // Return false and any info about mismatched sizes\n int4 vnout,vn0,vn1;\n AddrSpace *spc;\n\n switch(op->getOpcode()) {\n case CPUI_COPY:\t\t\t// Instructions where all inputs and output are same size\n case CPUI_INT_2COMP:\n case CPUI_INT_NEGATE:\n case CPUI_FLOAT_NEG:\n case CPUI_FLOAT_ABS:\n case CPUI_FLOAT_SQRT:\n case CPUI_FLOAT_CEIL:\n case CPUI_FLOAT_FLOOR:\n case CPUI_FLOAT_ROUND:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n if (vnout == vn0) return true;\n if ((vnout==0)||(vn0==0)) return true;\n printOpError(op,ct,-1,0,\"Input and output sizes must match\");\n return false;\n case CPUI_INT_ADD:\n case CPUI_INT_SUB:\n case CPUI_INT_XOR:\n case CPUI_INT_AND:\n case CPUI_INT_OR:\n case CPUI_INT_MULT:\n case CPUI_INT_DIV:\n case CPUI_INT_SDIV:\n case CPUI_INT_REM:\n case CPUI_INT_SREM:\n case CPUI_FLOAT_ADD:\n case CPUI_FLOAT_DIV:\n case CPUI_FLOAT_MULT:\n case CPUI_FLOAT_SUB:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n vn1 = recoverSize(op->getIn(1)->getSize(),ct);\n if (vn1 == -1) {\n printOpError(op,ct,1,1,\"Using subtable with exports in expression\");\n return false;\n }\n if ((vnout!=0)&&(vn0!=0)&&(vnout!=vn0)) {\n printOpError(op,ct,-1,0,\"The output and all input sizes must match\");\n return false;\n }\n if ((vnout!=0)&&(vn1!=0)&&(vnout!=vn1)) {\n printOpError(op,ct,-1,1,\"The output and all input sizes must match\");\n return false;\n }\n if ((vn0!=0)&&(vn1!=0)&&(vn0!=vn1)) {\n printOpError(op,ct,0,1,\"The output and all input sizes must match\");\n return false;\n }\n return true;\n case CPUI_FLOAT_NAN:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n if (vnout != 1) {\n printOpError(op,ct,-1,-1,\"Output must be a boolean (size 1)\");\n return false;\n }\n break;\n case CPUI_INT_EQUAL:\t\t// Instructions with bool output, all inputs equal size\n case CPUI_INT_NOTEQUAL:\n case CPUI_INT_SLESS:\n case CPUI_INT_SLESSEQUAL:\n case CPUI_INT_LESS:\n case CPUI_INT_LESSEQUAL:\n case CPUI_INT_CARRY:\n case CPUI_INT_SCARRY:\n case CPUI_INT_SBORROW:\n case CPUI_FLOAT_EQUAL:\n case CPUI_FLOAT_NOTEQUAL:\n case CPUI_FLOAT_LESS:\n case CPUI_FLOAT_LESSEQUAL:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n if (vnout != 1) {\n printOpError(op,ct,-1,-1,\"Output must be a boolean (size 1)\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n vn1 = recoverSize(op->getIn(1)->getSize(),ct);\n if (vn1 == -1) {\n printOpError(op,ct,1,1,\"Using subtable with exports in expression\");\n return false;\n }\n if ((vn0==0)||(vn1==0)) return true;\n if (vn0 != vn1) {\n printOpError(op,ct,0,1,\"Inputs must be the same size\");\n return false;\n }\n return true;\n case CPUI_BOOL_XOR:\n case CPUI_BOOL_AND:\n case CPUI_BOOL_OR:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n if (vnout != 1) {\n printOpError(op,ct,-1,-1,\"Output must be a boolean (size 1)\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n if (vn0 != 1) {\n printOpError(op,ct,0,0,\"Input must be a boolean (size 1)\");\n return false;\n }\n return true;\n case CPUI_BOOL_NEGATE:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n if (vnout != 1) {\n printOpError(op,ct,-1,-1,\"Output must be a boolean (size 1)\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n if (vn0 != 1) {\n printOpError(op,ct,0,0,\"Input must be a boolean (size 1)\");\n return false;\n }\n return true;\n // The shift amount does not necessarily have to be the same size\n // But the output and first parameter must be same size\n case CPUI_INT_LEFT:\n case CPUI_INT_RIGHT:\n case CPUI_INT_SRIGHT:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n if ((vnout==0)||(vn0==0)) return true;\n if (vnout != vn0) {\n printOpError(op,ct,-1,0,\"Output and first input must be the same size\");\n return false;\n }\n return true;\n case CPUI_INT_ZEXT:\n case CPUI_INT_SEXT:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n if ((vnout==0)||(vn0==0)) return true;\n if (vnout == vn0) {\n dealWithUnnecessaryExt(op,ct);\n return true;\n }\n else if (vnout < vn0) {\n printOpError(op,ct,-1,0,\"Output size must be strictly bigger than input size\");\n return false;\n }\n return true;\n case CPUI_CBRANCH:\n vn1 = recoverSize(op->getIn(1)->getSize(),ct);\n if (vn1 == -1) {\n printOpError(op,ct,1,1,\"Using subtable with exports in expression\");\n return false;\n }\n if (vn1 != 1) {\n printOpError(op,ct,1,1,\"Input must be a boolean (size 1)\");\n return false;\n }\n return true;\n case CPUI_LOAD:\n case CPUI_STORE:\n if (op->getIn(0)->getOffset().getType() != ConstTpl::spaceid)\n return true;\n spc = op->getIn(0)->getOffset().getSpace();\n vn1 = recoverSize(op->getIn(1)->getSize(),ct);\n if (vn1 == -1) {\n printOpError(op,ct,1,1,\"Using subtable with exports in expression\");\n return false;\n }\n if ((vn1!=0)&&(vn1 != spc->getAddrSize())) {\n printOpError(op,ct,1,1,\"Pointer size must match size of space\");\n return false;\n }\n return true;\n case CPUI_SUBPIECE:\n vnout = recoverSize(op->getOut()->getSize(),ct);\n if (vnout == -1) {\n printOpError(op,ct,-1,-1,\"Using subtable with exports in expression\");\n return false;\n }\n vn0 = recoverSize(op->getIn(0)->getSize(),ct);\n if (vn0 == -1) {\n printOpError(op,ct,0,0,\"Using subtable with exports in expression\");\n return false;\n }\n vn1 = op->getIn(1)->getOffset().getReal();\n if ((vnout==0)||(vn0==0)) return true;\n if ((vnout==vn0)&&(vn1==0)) { // No actual truncation is occuring\n dealWithUnnecessaryTrunc(op,ct);\n return true;\n }\n else if (vnout>=vn0) {\n printOpError(op,ct,-1,0,\"Output must be strictly smaller than input\");\n return false;\n }\n if (vnout>vn0-vn1) {\n printOpError(op,ct,-1,0,\"Too much truncation\");\n return false;\n }\n return true;\n default:\n break;\n }\n return true;\n}\n\n/// \\brief Print the name of a p-code operator (for warning and error messages)\n///\n/// Print the full name of the operator with its syntax token in parentheses.\n/// \\param s is the output stream to write to\n/// \\param op is the operator to print\nvoid ConsistencyChecker::printOpName(ostream &s,OpTpl *op)\n\n{\n switch(op->getOpcode()) {\n case CPUI_COPY:\n s << \"Copy(=)\";\n break;\n case CPUI_LOAD:\n s << \"Load(*)\";\n break;\n case CPUI_STORE:\n s << \"Store(*)\";\n break;\n case CPUI_BRANCH:\n s << \"Branch(goto)\";\n break;\n case CPUI_CBRANCH:\n s << \"Conditional branch(if)\";\n break;\n case CPUI_BRANCHIND:\n s << \"Indirect branch(goto[])\";\n break;\n case CPUI_CALL:\n s << \"Call\";\n break;\n case CPUI_CALLIND:\n s << \"Indirect Call\";\n break;\n case CPUI_CALLOTHER:\n s << \"User defined\";\n break;\n case CPUI_RETURN:\n s << \"Return\";\n break;\n case CPUI_INT_EQUAL:\n s << \"Equality(==)\";\n break;\n case CPUI_INT_NOTEQUAL:\n s << \"Notequal(!=)\";\n break;\n case CPUI_INT_SLESS:\n s << \"Signed less than(s<)\";\n break;\n case CPUI_INT_SLESSEQUAL:\n s << \"Signed less than or equal(s<=)\";\n break;\n case CPUI_INT_LESS:\n s << \"Less than(<)\";\n break;\n case CPUI_INT_LESSEQUAL:\n s << \"Less than or equal(<=)\";\n break;\n case CPUI_INT_ZEXT:\n s << \"Zero extension(zext)\";\n break;\n case CPUI_INT_SEXT:\n s << \"Signed extension(sext)\";\n break;\n case CPUI_INT_ADD:\n s << \"Addition(+)\";\n break;\n case CPUI_INT_SUB:\n s << \"Subtraction(-)\";\n break;\n case CPUI_INT_CARRY:\n s << \"Carry\";\n break;\n case CPUI_INT_SCARRY:\n s << \"Signed carry\";\n break;\n case CPUI_INT_SBORROW:\n s << \"Signed borrow\";\n break;\n case CPUI_INT_2COMP:\n s << \"Twos complement(-)\";\n break;\n case CPUI_INT_NEGATE:\n s << \"Negate(~)\";\n break;\n case CPUI_INT_XOR:\n s << \"Exclusive or(^)\";\n break;\n case CPUI_INT_AND:\n s << \"And(&)\";\n break;\n case CPUI_INT_OR:\n s << \"Or(|)\";\n break;\n case CPUI_INT_LEFT:\n s << \"Left shift(<<)\";\n break;\n case CPUI_INT_RIGHT:\n s << \"Right shift(>>)\";\n break;\n case CPUI_INT_SRIGHT:\n s << \"Signed right shift(s>>)\";\n break;\n case CPUI_INT_MULT:\n s << \"Multiplication(*)\";\n break;\n case CPUI_INT_DIV:\n s << \"Division(/)\";\n break;\n case CPUI_INT_SDIV:\n s << \"Signed division(s/)\";\n break;\n case CPUI_INT_REM:\n s << \"Remainder(%)\";\n break;\n case CPUI_INT_SREM:\n s << \"Signed remainder(s%)\";\n break;\n case CPUI_BOOL_NEGATE:\n s << \"Boolean negate(!)\";\n break;\n case CPUI_BOOL_XOR:\n s << \"Boolean xor(^^)\";\n break;\n case CPUI_BOOL_AND:\n s << \"Boolean and(&&)\";\n break;\n case CPUI_BOOL_OR:\n s << \"Boolean or(||)\";\n break;\n case CPUI_FLOAT_EQUAL:\n s << \"Float equal(f==)\";\n break;\n case CPUI_FLOAT_NOTEQUAL:\n s << \"Float notequal(f!=)\";\n break;\n case CPUI_FLOAT_LESS:\n s << \"Float less than(f<)\";\n break;\n case CPUI_FLOAT_LESSEQUAL:\n s << \"Float less than or equal(f<=)\";\n break;\n case CPUI_FLOAT_NAN:\n s << \"Not a number(nan)\";\n break;\n case CPUI_FLOAT_ADD:\n s << \"Float addition(f+)\";\n break;\n case CPUI_FLOAT_DIV:\n s << \"Float division(f/)\";\n break;\n case CPUI_FLOAT_MULT:\n s << \"Float multiplication(f*)\";\n break;\n case CPUI_FLOAT_SUB:\n s << \"Float subtractions(f-)\";\n break;\n case CPUI_FLOAT_NEG:\n s << \"Float minus(f-)\";\n break;\n case CPUI_FLOAT_ABS:\n s << \"Absolute value(abs)\";\n break;\n case CPUI_FLOAT_SQRT:\n s << \"Square root\";\n break;\n case CPUI_FLOAT_INT2FLOAT:\n s << \"Integer to float conversion(int2float)\";\n break;\n case CPUI_FLOAT_FLOAT2FLOAT:\n s << \"Float to float conversion(float2float)\";\n break;\n case CPUI_FLOAT_TRUNC:\n s << \"Float truncation(trunc)\";\n break;\n case CPUI_FLOAT_CEIL:\n s << \"Ceiling(ceil)\";\n break;\n case CPUI_FLOAT_FLOOR:\n s << \"Floor\";\n break;\n case CPUI_FLOAT_ROUND:\n s << \"Round\";\n break;\n case CPUI_MULTIEQUAL:\n s << \"Build\";\n break;\n case CPUI_INDIRECT:\n s << \"Delay\";\n break;\n case CPUI_SUBPIECE:\n s << \"Truncation(:)\";\n break;\n case CPUI_SEGMENTOP:\n s << \"Segment table(segment)\";\n break;\n case CPUI_CPOOLREF:\n s << \"Constant Pool(cpool)\";\n break;\n case CPUI_NEW:\n s << \"New object(newobject)\";\n break;\n case CPUI_POPCOUNT:\n s << \"Count bits(popcount)\";\n break;\n case CPUI_LZCOUNT:\n s << \"Count leading zero bits(lzcount)\";\n break;\n default:\n break;\n }\n}\n\n/// \\brief Get the OperandSymbol associated with an input/output Varnode of the given p-code operator\n///\n/// Find the Constructor operand associated with a specified Varnode, if it exists.\n/// The Varnode is specified by the p-code operator using it and the input \\e slot index, with -1\n/// indicating the operator's output Varnode. Not all Varnode's are associated with a\n/// Constructor operand, in which case \\e null is returned.\n/// \\param slot is the input \\e slot index, or -1 for an output Varnode\n/// \\param op is the p-code operator using the Varnode\n/// \\param ct is the Constructor containing the p-code and operands\n/// \\return the associated operand or null\nOperandSymbol *ConsistencyChecker::getOperandSymbol(int4 slot,OpTpl *op,Constructor *ct)\n\n{\n VarnodeTpl *vn;\n OperandSymbol *opsym;\n int4 handindex;\n\n if (slot == -1)\n vn = op->getOut();\n else\n vn = op->getIn(slot);\n \n switch(vn->getSize().getType()) {\n case ConstTpl::handle:\n handindex = vn->getSize().getHandleIndex();\n opsym = ct->getOperand(handindex);\n break;\n default:\n opsym = (OperandSymbol *)0;\n break;\n }\n return opsym;\n}\n\n/// \\brief Print an error message describing a size restriction violation\n///\n/// The given p-code operator is assumed to violate the Varnode size rules for its opcode.\n/// If the violation is for two Varnodes that should be the same size, each Varnode is indicated\n/// as an input \\e slot index, where -1 indicates the operator's output Varnode.\n/// If the violation is for a single Varnode, its \\e slot index is passed in twice.\n/// \\param op is the given p-code operator\n/// \\param ct is the containing Constructor\n/// \\param err1 is the slot of the first violating Varnode\n/// \\param err2 is the slot of the second violating Varnode (or equal to \\b err1)\n/// \\param msg is additional description that is appended to the error message\nvoid ConsistencyChecker::printOpError(OpTpl *op,Constructor *ct,int4 err1,int4 err2,const string &msg)\n\n{\n SubtableSymbol *sym = ct->getParent();\n OperandSymbol *op1,*op2;\n\n op1 = getOperandSymbol(err1,op,ct);\n if (err2 != err1)\n op2 = getOperandSymbol(err2,op,ct);\n else\n op2 = (OperandSymbol *)0;\n\n ostringstream msgBuilder;\n\n msgBuilder << \"Size restriction error in table '\" << sym->getName() << \"'\" << endl;\n if ((op1 != (OperandSymbol *)0)&&(op2 != (OperandSymbol *)0))\n msgBuilder << \" Problem with operands '\" << op1->getName() << \"' and '\" << op2->getName() << \"'\";\n else if (op1 != (OperandSymbol *)0)\n msgBuilder << \" Problem with operand 1 '\" << op1->getName() << \"'\";\n else if (op2 != (OperandSymbol *)0)\n msgBuilder << \" Problem with operand 2 '\" << op2->getName() << \"'\";\n else\n msgBuilder << \" Problem\";\n msgBuilder << \" in \";\n printOpName(msgBuilder,op);\n msgBuilder << \" operator\" << endl << \" \" << msg;\n\n compiler->reportError(compiler->getLocation(ct), msgBuilder.str());\n}\n\n/// \\brief Check all p-code operators within a given Constructor section for misuse and size consistency\n///\n/// Each operator within the section is checked in turn, and warning and error messages are emitted\n/// if necessary. The method returns \\b false if there is a fatal error associated with any\n/// operator.\n/// \\param ct is the Constructor to check\n/// \\param cttpl is the specific p-code section to check\n/// \\return \\b true if there are no fatal errors in the section\nbool ConsistencyChecker::checkConstructorSection(Constructor *ct,ConstructTpl *cttpl)\n\n{\n if (cttpl == (ConstructTpl *)0)\n return true;\t\t// Nothing to check\n vector::const_iterator iter;\n const vector &ops(cttpl->getOpvec());\n bool testresult = true;\n\n for(iter=ops.begin();iter!=ops.end();++iter) {\n if (!sizeRestriction(*iter,ct))\n testresult = false;\n if (!checkOpMisuse(*iter,ct))\n testresult = false;\n }\n return testresult;\n}\n\n/// \\brief Check the given p-code operator for too large temporary registers\n///\n/// Return \\b true if the output or one of the inputs to the operator\n/// is in the \\e unique space and larger than SleighBase::MAX_UNIQUE_SIZE\n/// \\param op is the given operator\n/// \\return \\b true if the operator has a too large temporary parameter\nbool ConsistencyChecker::hasLargeTemporary(OpTpl *op)\n\n{\n VarnodeTpl *out = op->getOut();\n if ((out != (VarnodeTpl*)0x0) && isTemporaryAndTooBig(out)) {\n return true;\n }\n for(int4 i = 0;i < op->numInput();++i) {\n VarnodeTpl *in = op->getIn(i);\n if (isTemporaryAndTooBig(in)) {\n return true;\n }\n }\n return false;\n}\n\n/// \\brief Check if the given Varnode is a too large temporary register\n///\n/// Return \\b true precisely when the Varnode is in the \\e unique space and\n/// has size larger than SleighBase::MAX_UNIQUE_SIZE\n/// \\param vn is the given Varnode\n/// \\return \\b true if the Varnode is a too large temporary register\nbool ConsistencyChecker::isTemporaryAndTooBig(VarnodeTpl *vn)\n\n{\n return vn->getSpace().isUniqueSpace() && (vn->getSize().getReal() > SleighBase::MAX_UNIQUE_SIZE);\n}\n\n/// \\brief Resolve the offset of the given \\b truncated Varnode\n///\n/// SLEIGH allows a Varnode to be derived from another larger Varnode using\n/// truncation or bit range notation. The final offset of the truncated Varnode may not\n/// be calculable immediately during parsing, especially if the address space is big endian\n/// and the size of the containing Varnode is not immediately known.\n/// This method recovers the final offset of the truncated Varnode now that all sizes are\n/// known and otherwise checks that the truncation expression is valid.\n/// \\param ct is the Constructor containing the Varnode\n/// \\param slot is the \\e slot index of the truncated Varnode (for error messages)\n/// \\param op is the operator using the truncated Varnode (for error messages)\n/// \\param vn is the given truncated Varnode\n/// \\param isbigendian is \\b true if the Varnode is in a big endian address space\n/// \\return \\b true if the truncation expression was valid\nbool ConsistencyChecker::checkVarnodeTruncation(Constructor *ct,int4 slot,\n\t\t\t\t\t\tOpTpl *op,VarnodeTpl *vn,bool isbigendian)\n{\n const ConstTpl &off( vn->getOffset() );\n if (off.getType() != ConstTpl::handle) return true;\n if (off.getSelect() != ConstTpl::v_offset_plus) return true;\n ConstTpl::const_type sztype = vn->getSize().getType();\n if ((sztype != ConstTpl::real)&&(sztype != ConstTpl::handle)) {\n printOpError(op,ct,slot,slot,\"Bad truncation expression\");\n return false;\n }\n int4 sz = recoverSize(off,ct); // Recover the size of the original operand\n if (sz <= 0) {\n printOpError(op,ct,slot,slot,\"Could not recover size\");\n return false;\n }\n bool res = vn->adjustTruncation(sz,isbigendian);\n if (!res) {\n printOpError(op,ct,slot,slot,\"Truncation operator out of bounds\");\n return false;\n }\n return true;\n}\n\n/// \\brief Check and adjust truncated Varnodes in the given Constructor p-code section\n///\n/// Run through all Varnodes looking for offset templates marked as ConstTpl::v_offset_plus,\n/// which indicates they were constructed using truncation notation. These truncation expressions\n/// are checked for validity and adjusted depending on the endianness of the address space.\n/// \\param ct is the Constructor\n/// \\param cttpl is the given p-code section\n/// \\param isbigendian is set to \\b true if the SLEIGH specification is big endian\n/// \\return \\b true if all truncation expressions were valid\nbool ConsistencyChecker::checkSectionTruncations(Constructor *ct,ConstructTpl *cttpl,bool isbigendian)\n\n{\n vector::const_iterator iter;\n const vector &ops(cttpl->getOpvec());\n bool testresult = true;\n \n for(iter=ops.begin();iter!=ops.end();++iter) {\n OpTpl *op = *iter;\n VarnodeTpl *outvn = op->getOut();\n if (outvn != (VarnodeTpl *)0) {\n if (!checkVarnodeTruncation(ct,-1,op,outvn,isbigendian))\n\ttestresult = false;\n }\n for(int4 i=0;inumInput();++i) {\n if (!checkVarnodeTruncation(ct,i,op,op->getIn(i),isbigendian))\n\ttestresult = false;\n }\n }\n return testresult;\n}\n\n/// \\brief Check all Constructors within the given subtable for operator misuse and size consistency\n///\n/// Each Constructor and section is checked in turn. Additionally, the size of Constructor\n/// exports is checked for consistency across the subtable. Constructors within one subtable must\n/// all export the same size Varnode if the export at all.\n/// \\param sym is the given subtable to check\n/// \\return \\b true if there are no fatal misuse or consistency violations\nbool ConsistencyChecker::checkSubtable(SubtableSymbol *sym)\n\n{\n int4 tablesize = -1;\n int4 numconstruct = sym->getNumConstructors();\n Constructor *ct;\n bool testresult = true;\n bool seenemptyexport = false;\n bool seennonemptyexport = false;\n\n for(int4 i=0;igetConstructor(i);\n if (!checkConstructorSection(ct,ct->getTempl()))\n testresult = false;\n int4 numsection = ct->getNumSections();\n for(int4 j=0;jgetNamedTempl(j)))\n\ttestresult = false;\n }\n\n if (ct->getTempl() == (ConstructTpl *)0) continue;\t// Unimplemented\n HandleTpl *exportres = ct->getTempl()->getResult();\n if (exportres != (HandleTpl *)0) {\n if (seenemptyexport && (!seennonemptyexport)) {\n\tostringstream msg;\n\tmsg << \"Table '\" << sym->getName() << \"' exports inconsistently; \";\n\tmsg << \"Constructor starting at line \" << dec << ct->getLineno() << \" is first inconsistency\";\n\tcompiler->reportError(compiler->getLocation(ct), msg.str());\n\ttestresult = false;\n }\n seennonemptyexport = true;\n int4 exsize = recoverSize(exportres->getSize(),ct);\n if (tablesize == -1)\n\ttablesize = exsize;\n if (exsize != tablesize) {\n\tostringstream msg;\n\tmsg << \"Table '\" << sym->getName() << \"' has inconsistent export size; \";\n\tmsg << \"Constructor starting at line \" << dec << ct->getLineno() << \" is first conflict\";\n\tcompiler->reportError(compiler->getLocation(ct), msg.str());\n\ttestresult = false;\n }\n }\n else {\n if (seennonemptyexport && (!seenemptyexport)) {\n\tostringstream msg;\n\tmsg << \"Table '\" << sym->getName() << \"' exports inconsistently; \";\n\tmsg << \"Constructor starting at line \" << dec << ct->getLineno() << \" is first inconsistency\";\n\tcompiler->reportError(compiler->getLocation(ct), msg.str());\n\ttestresult = false;\n }\n seenemptyexport = true;\n }\n }\n if (seennonemptyexport) {\n if (tablesize == 0) {\n compiler->reportWarning(compiler->getLocation(sym), \"Table '\" + sym->getName() + \"' exports size 0\");\n }\n sizemap[sym] = tablesize;\t// Remember recovered size\n }\n else\n sizemap[sym] = -1;\n \n return testresult;\n}\n\n/// \\brief Establish ordering on subtables so that more dependent tables come first\n///\n/// Do a depth first traversal of SubtableSymbols starting at the root table going\n/// through Constructors and then through their operands, establishing a post-order on the\n/// subtables. This allows the size restriction checks to recursively calculate sizes of dependent\n/// subtables first and propagate their values into more global Varnodes (as Constructor operands)\n/// \\param root is the root subtable\nvoid ConsistencyChecker::setPostOrder(SubtableSymbol *root)\n\n{\n postorder.clear();\n sizemap.clear();\n\n vector path;\n vector state;\n vector ctstate;\n\n sizemap[root] = -1;\t\t// Mark root as traversed\n path.push_back(root);\n state.push_back(0);\n ctstate.push_back(0);\n\n while(!path.empty()) {\n SubtableSymbol *cur = path.back();\n int4 ctind = state.back();\n if (ctind >= cur->getNumConstructors()) {\n path.pop_back(); \t\t// Table is fully traversed\n state.pop_back();\n ctstate.pop_back();\n postorder.push_back(cur);\t// Post the traversed table\n }\n else {\n Constructor *ct = cur->getConstructor(ctind);\n int4 oper = ctstate.back();\n if (oper >= ct->getNumOperands()) {\n\tstate.back() = ctind + 1; // Constructor fully traversed\n\tctstate.back() = 0;\n }\n else {\n\tctstate.back() = oper + 1;\n\tOperandSymbol *opsym = ct->getOperand(oper);\n\tSubtableSymbol *subsym = dynamic_cast(opsym->getDefiningSymbol());\n\tif (subsym != (SubtableSymbol *)0) {\n\t map::const_iterator iter;\n\t iter = sizemap.find(subsym);\n\t if (iter == sizemap.end()) { // Not traversed yet\n\t sizemap[subsym] = -1; // Mark table as traversed\n\t path.push_back(subsym); // Recurse\n\t state.push_back(0);\n\t ctstate.push_back(0);\n\t }\n\t}\n }\n }\n }\n}\n\nmap::iterator ConsistencyChecker::UniqueState::lesserIter(uintb offset)\n\n{\n if (recs.begin() == recs.end()) {\n return recs.end();\n }\n map::iterator iter;\n iter = recs.lower_bound(offset);\n if (iter == recs.begin()) {\n return recs.end();\n }\n return std::prev(iter);\n}\n\nConsistencyChecker::OptimizeRecord ConsistencyChecker::UniqueState::coalesce(vector &records)\n\n{\n uintb minOff = -1;\n uintb maxOff = -1;\n vector::iterator iter;\n\n for (iter = records.begin(); iter != records.end(); ++iter) {\n if (minOff == -1 || (*iter)->offset < minOff) {\n minOff = (*iter)->offset;\n }\n if (maxOff == -1 || (*iter)->offset + (*iter)->size > maxOff) {\n maxOff = (*iter)->offset + (*iter)->size;\n }\n }\n\n OptimizeRecord result(minOff, maxOff - minOff);\n\n for (iter = records.begin(); iter != records.end(); ++iter) {\n result.updateCombine(**iter);\n }\n\n return result;\n}\n\nvoid ConsistencyChecker::UniqueState::set(uintb offset, int4 size, OptimizeRecord &rec)\n\n{\n vector records;\n getDefinitions(records, offset, size);\n records.push_back(&rec);\n OptimizeRecord coalesced = coalesce(records);\n recs.erase(recs.lower_bound(coalesced.offset), recs.lower_bound(coalesced.offset+coalesced.size));\n recs.insert(pair(coalesced.offset, coalesced));\n}\n\nvoid ConsistencyChecker::UniqueState::getDefinitions(vector &result, uintb offset, int4 size)\n\n{\n if (size == 0) {\n size = 1;\n }\n map::iterator iter;\n iter = lesserIter(offset);\n uintb cursor = offset;\n if (iter != recs.end() && endOf(iter) > offset) {\n OptimizeRecord &preRec = iter->second;\n cursor = endOf(iter);\n result.push_back(&preRec);\n }\n uintb end = offset + size;\n iter = recs.lower_bound(offset);\n while (iter != recs.end() && iter->first < end) {\n if (iter->first > cursor) {\n // The iterator becomes invalid with this insertion, so take the new one.\n iter = recs.insert(pair(cursor,OptimizeRecord(cursor, iter->first - cursor))).first;\n result.push_back(&iter->second);\n iter++; // Put the (now valid) iterator back to where it was.\n }\n // No need to truncate, as we're just counting a read\n result.push_back(&iter->second);\n cursor = endOf(iter);\n iter++;\n }\n if (end > cursor) {\n iter = recs.insert(pair(cursor,OptimizeRecord(cursor, end - cursor))).first;\n result.push_back(&iter->second);\n }\n}\n\n/// \\brief Test whether two given Varnodes intersect\n///\n/// This test must be conservative. If it can't explicitly prove that the\n/// Varnodes don't intersect, it returns \\b true (a possible intersection).\n/// \\param vn1 is the first Varnode to check\n/// \\param vn2 is the second Varnode to check\n/// \\return \\b true if there is a possible intersection of the Varnodes' storage\nbool ConsistencyChecker::possibleIntersection(const VarnodeTpl *vn1,const VarnodeTpl *vn2)\n\n{ // Conservatively test whether vn1 and vn2 can intersect\n if (vn1->getSpace().isConstSpace()) return false;\n if (vn2->getSpace().isConstSpace()) return false;\n\n bool u1 = vn1->getSpace().isUniqueSpace();\n bool u2 = vn2->getSpace().isUniqueSpace();\n\n if (u1 != u2) return false;\n\n if (vn1->getSpace().getType() != ConstTpl::spaceid) return true;\n if (vn2->getSpace().getType() != ConstTpl::spaceid) return true;\n AddrSpace *spc = vn1->getSpace().getSpace();\n if (spc != vn2->getSpace().getSpace()) return false;\n\n\n if (vn2->getOffset().getType() != ConstTpl::real) return true;\n if (vn2->getSize().getType() != ConstTpl::real) return true;\n\n if (vn1->getOffset().getType() != ConstTpl::real) return true;\n if (vn1->getSize().getType() != ConstTpl::real) return true;\n\n uintb offset = vn1->getOffset().getReal();\n uintb size = vn1->getSize().getReal();\n\n uintb off = vn2->getOffset().getReal();\n if (off+vn2->getSize().getReal()-1 < offset) return false;\n if (off > (offset+size-1)) return false;\n return true;\n}\n\n/// \\brief Check if a p-code operator reads from or writes to a given Varnode\n///\n/// A write check is always performed. A read check is performed only if requested.\n/// Return \\b true if there is a possible write (or read) of the Varnode.\n/// The checks need to be extremely conservative. If it can't be determined what\n/// exactly is being read or written, \\b true (possible interference) is returned.\n/// \\param vn is the given Varnode\n/// \\param op is p-code operator to test for interference\n/// \\param checkread is \\b true if read interference should be checked\n/// \\return \\b true if there is write (or read) interference\nbool ConsistencyChecker::readWriteInterference(const VarnodeTpl *vn,const OpTpl *op,bool checkread) const\n\n{\n switch(op->getOpcode()) {\n case BUILD:\n case CROSSBUILD:\n case DELAY_SLOT:\n case MACROBUILD:\n case CPUI_LOAD:\n case CPUI_STORE:\n case CPUI_BRANCH:\n case CPUI_CBRANCH:\n case CPUI_BRANCHIND:\n case CPUI_CALL:\n case CPUI_CALLIND:\n case CPUI_CALLOTHER:\n case CPUI_RETURN:\n case LABELBUILD:\t\t// Another value might jump in here\n return true;\n default:\n break;\n }\n\n if (checkread) {\n int4 numinputs = op->numInput();\n for(int4 i=0;igetIn(i)))\n\treturn true;\n }\n\n // We always check for writes to -vn-\n const VarnodeTpl *vn2 = op->getOut();\n if (vn2 != (const VarnodeTpl *)0) {\n\tif (possibleIntersection(vn,vn2))\n return true;\n }\n return false;\n}\n\n/// \\brief Accumulate read/write info if the given Varnode is temporary\n///\n/// If the Varnode is in the \\e unique space, an OptimizationRecord for it is looked\n/// up based on its offset. Information about how a p-code operator uses the Varnode\n/// is accumulated in the record.\n/// \\param state is collection of OptimizationRecords associated with temporary Varnodes\n/// \\param vn is the given Varnode to check (which may or may not be temporary)\n/// \\param i is the index of the operator using the Varnode (within its p-code section)\n/// \\param inslot is the \\e slot index of the Varnode within its operator\n/// \\param secnum is the section number containing the operator\nvoid ConsistencyChecker::examineVn(UniqueState &state,\n\t\t\t\t const VarnodeTpl *vn,uint4 i,int4 inslot,int4 secnum)\n{\n if (vn == (const VarnodeTpl *)0) return;\n if (!vn->getSpace().isUniqueSpace()) return;\n if (vn->getOffset().getType() != ConstTpl::real) return;\n\n uintb offset = vn->getOffset().getReal();\n int4 size = vn->getSize().getReal();\n if (inslot >= 0) {\n vector defs;\n state.getDefinitions(defs,offset,size);\n for (vector::iterator iter=defs.begin();iter!=defs.end();++iter) {\n (*iter)->updateRead(i,inslot,secnum);\n }\n }\n else {\n OptimizeRecord rec(offset,size);\n rec.updateWrite(i,secnum);\n state.set(offset,size,rec);\n }\n}\n\n/// \\brief Gather statistics about read and writes to temporary Varnodes within a given p-code section\n///\n/// For each temporary Varnode, count how many times it is read from or written to\n/// in the given section of p-code operators.\n/// \\param ct is the given Constructor\n/// \\param state is the (initially empty) collection of count records\n/// \\param secnum is the given p-code section number\nvoid ConsistencyChecker::optimizeGather1(Constructor *ct,UniqueState &state,int4 secnum) const\n\n{\n ConstructTpl *tpl;\n if (secnum < 0)\n tpl = ct->getTempl();\n else\n tpl = ct->getNamedTempl(secnum);\n if (tpl == (ConstructTpl *)0)\n return;\n const vector &ops( tpl->getOpvec() );\n for(uint4 i=0;inumInput();++j) {\n const VarnodeTpl *vnin = op->getIn(j);\n examineVn(state,vnin,i,j,secnum);\n }\n const VarnodeTpl *vn = op->getOut();\n examineVn(state,vn,i,-1,secnum);\n }\n}\n\n/// \\brief Mark Varnodes in the export of the given p-code section as read and written\n///\n/// As part of accumulating read/write info for temporary Varnodes, examine the export Varnode\n/// for the section, and if it involves a temporary, mark it as both read and written, guaranteeing\n/// that the Varnode is not optimized away.\n/// \\param ct is the given Constructor\n/// \\param state is the collection of count records\n/// \\param secnum is the given p-code section number\nvoid ConsistencyChecker::optimizeGather2(Constructor *ct,UniqueState &state,int4 secnum) const\n\n{\n ConstructTpl *tpl;\n if (secnum < 0)\n tpl = ct->getTempl();\n else\n tpl = ct->getNamedTempl(secnum);\n if (tpl == (ConstructTpl *)0)\n return;\n HandleTpl *hand = tpl->getResult();\n if (hand == (HandleTpl *)0) return;\n if (hand->getPtrSpace().isUniqueSpace()) {\n if (hand->getPtrOffset().getType() == ConstTpl::real) {\n uintb offset = hand->getPtrOffset().getReal();\n int4 size = hand->getPtrSize().getReal();\n vector defs;\n state.getDefinitions(defs,offset,size);\n for (vector::iterator iter=defs.begin();iter!=defs.end();++iter) {\n\t(*iter)->updateExport();\n\t// NOTE: Could this just be updateRead?\n\t// Technically, an exported handle could be written by the parent....\n }\n }\n }\n if (hand->getSpace().isUniqueSpace()) {\n if ((hand->getPtrSpace().getType() == ConstTpl::real)&&\n\t(hand->getPtrOffset().getType() == ConstTpl::real)) {\n uintb offset = hand->getPtrOffset().getReal();\n int4 size = hand->getPtrSize().getReal();\n vector defs;\n state.getDefinitions(defs,offset,size);\n for (vector::iterator iter=defs.begin();iter!=defs.end();++iter) {\n\t(*iter)->updateExport();\n\t// NOTE: Could this just be updateRead?\n\t// Technically, an exported handle could be written by the parent....\n }\n }\n }\n}\n\n/// \\brief Search for an OptimizeRecord indicating a temporary Varnode that can be optimized away\n///\n/// OptimizeRecords for all temporary Varnodes must already be calculated.\n/// Find a record indicating a temporary Varnode that is written once and read once through a COPY.\n/// Test propagation of the other Varnode associated with the COPY, making sure:\n/// if propagation is backward, the Varnode must not cross another read or write, and\n/// if propagation is forward, the Varnode must not cross another write.\n/// If all the requirements pass, return the record indicating that the COPY can be removed.\n/// \\param ct is the Constructor owning the p-code\n/// \\param state is the collection of OptimizeRecords to search\n/// \\return a passing OptimizeRecord or null\nconst ConsistencyChecker::OptimizeRecord *ConsistencyChecker::findValidRule(Constructor *ct,\n\t\t\t\t\t\t\t\t\t const UniqueState &state) const\n{\n map::const_iterator iter;\n iter = state.begin();\n while(iter!=state.end()) {\n const OptimizeRecord &currec( (*iter).second );\n ++iter;\n if ((currec.writecount==1)&&(currec.readcount==1)&&(currec.readsection==currec.writesection)) {\n // Temporary must be read and written exactly once\n ConstructTpl *tpl;\n if (currec.readsection < 0)\n\ttpl = ct->getTempl();\n else\n\ttpl = ct->getNamedTempl(currec.readsection);\n const vector &ops( tpl->getOpvec() );\n const OpTpl *writeop = ops[ currec.writeop ];\n const OpTpl *readop = ops[ currec.readop ];\n if (currec.writeop >= currec.readop) // Read must come after write\n\tthrow SleighError(\"Read of temporary before write\");\n\n VarnodeTpl *writevn = writeop->getOut();\n VarnodeTpl *readvn = readop->getIn(currec.inslot);\n // Because the record can change size and position, we have to check if the varnode\n // \"connecting\" the write and read ops is actually the same varnode. If not, then we can't\n // optimize it out.\n // There may be an opportunity here to re-write the size/offset when either the write or read\n // op is a COPY, but I'll leave that for later discussion.\n // Actually, maybe not. If the truncate would be of a handle, we can't.\n if (*writevn != *readvn) {\n\tcontinue;\n }\n\n if (readop->getOpcode() == CPUI_COPY) {\n\tbool saverecord = true;\n\tcurrec.opttype = 0;\t// Read op is a COPY\n\tconst VarnodeTpl *vn = readop->getOut();\n\tfor(int4 i=currec.writeop+1;igetOpcode() == CPUI_COPY) {\n\tbool saverecord = true;\n\tcurrec.opttype = 1;\t// Write op is a COPY\n\tconst VarnodeTpl *vn = writeop->getIn(0);\n\tfor(int4 i=currec.writeop+1;i deleteops;\n ConstructTpl *ctempl;\n if (rec.readsection < 0)\n ctempl = ct->getTempl();\n else\n ctempl = ct->getNamedTempl(rec.readsection);\n \n if (rec.opttype == 0) { // If read op is COPY\n int4 readop = rec.readop;\n OpTpl *op = ctempl->getOpvec()[ readop ];\n VarnodeTpl *vnout = new VarnodeTpl(*op->getOut()); // Make COPY output\n ctempl->setOutput(vnout,rec.writeop); // become write output\n deleteops.push_back(readop); // and then delete the read (COPY)\n }\n else if (rec.opttype == 1) { // If write op is COPY\n int4 writeop = rec.writeop;\n OpTpl *op = ctempl->getOpvec()[ writeop ];\n VarnodeTpl *vnin = new VarnodeTpl(*op->getIn(0));\t// Make COPY input\n ctempl->setInput(vnin,rec.readop,rec.inslot); // become read input\n deleteops.push_back(writeop); // and then delete the write (COPY)\n }\n ctempl->deleteOps(deleteops);\n}\n\n/// \\brief Issue error/warning messages for unused temporary Varnodes\n///\n/// An error message is issued if a temporary is read but not written.\n/// A warning may be issued if a temporary is written but not read.\n/// \\param ct is the Constructor\n/// \\param state is the collection of records associated with each temporary Varnode\nvoid ConsistencyChecker::checkUnusedTemps(Constructor *ct,const UniqueState &state)\n\n{\n map::const_iterator iter;\n iter = state.begin();\n while(iter != state.end()) {\n const OptimizeRecord &currec( (*iter).second );\n if (currec.readcount == 0) {\n if (printdeadwarning)\n\tcompiler->reportWarning(compiler->getLocation(ct), \"Temporary is written but not read\");\n writenoread += 1;\n }\n else if (currec.writecount == 0) {\n compiler->reportError(compiler->getLocation(ct), \"Temporary is read but not written\");\n readnowrite += 1;\n }\n ++iter;\n }\n}\n\n/// \\brief In the given Constructor p-code section, check for temporary Varnodes that are too large\n///\n/// Run through all Varnodes in the constructor, if a Varnode is in the \\e unique\n/// space and its size exceeds the threshold SleighBase::MAX_UNIQUE_SIZE, issue\n/// a warning. Note that this method returns after the first large Varnode is found.\n/// \\param ct is the given Constructor\n/// \\param ctpl is the specific p-code section\nvoid ConsistencyChecker::checkLargeTemporaries(Constructor *ct,ConstructTpl *ctpl)\n\n{\n vector ops = ctpl->getOpvec();\n for(vector::iterator iter = ops.begin();iter != ops.end();++iter) {\n if (hasLargeTemporary(*iter)) {\n compiler->reportError(\n\t compiler->getLocation(ct),\n\t \"Constructor uses temporary varnode larger than \" + to_string(SleighBase::MAX_UNIQUE_SIZE) + \" bytes.\");\n return;\n }\n }\n}\n\n/// \\brief Do p-code optimization on each section of the given Constructor\n///\n/// For p-code section, statistics on temporary Varnode usage is collected,\n/// and unnecessary COPY operators are removed.\n/// \\param ct is the given Constructor\nvoid ConsistencyChecker::optimize(Constructor *ct)\n\n{\n const OptimizeRecord *currec;\n UniqueState state;\n int4 numsections = ct->getNumSections();\n do {\n state.clear();\n for(int4 i=-1;iisBigEndian();\n for(int4 i=0;igetNumConstructors();\n Constructor *ct;\n for(int4 j=0;jgetConstructor(j);\n\n int4 numsections = ct->getNumSections();\n for(int4 k=-1;kgetTempl();\n\telse\n\t tpl = ct->getNamedTempl(k);\n\tif (tpl == (ConstructTpl *)0)\n\t continue;\n\tif (!checkSectionTruncations(ct,tpl,isbigendian))\n\t testresult = false;\n }\n }\n }\n return testresult;\n}\n\n/// This counts Constructors that contain temporary Varnodes that are too large.\n/// If requested, an individual warning is printed for each Constructor.\nvoid ConsistencyChecker::testLargeTemporary(void)\n\n{\n for(int4 i=0;igetNumConstructors();\n Constructor *ct;\n for(int4 j=0;jgetConstructor(j);\n\n int4 numsections = ct->getNumSections();\n for(int4 k=-1;kgetTempl();\n\telse\n\t tpl = ct->getNamedTempl(k);\n\tif (tpl == (ConstructTpl *)0)\n\t continue;\n\tcheckLargeTemporaries(ct, tpl);\n }\n }\n }\n}\n\nvoid ConsistencyChecker::optimizeAll(void)\n\n{\n for(int4 i=0;igetNumConstructors();\n Constructor *ct;\n for(int4 i=0;igetConstructor(i);\n optimize(ct);\n }\n }\n}\n\nostream& operator<<(ostream &os, const ConsistencyChecker::OptimizeRecord &rec) {\n os << \"{writeop=\" << rec.writeop << \" readop=\" << rec.readop << \" inslot=\" << rec.inslot <<\n \" writecount=\" << rec.writecount << \" readcount=\" << rec.readcount <<\n\t\" opttype=\" << rec.opttype << \"}\";\n return os;\n}\n\n/// Sort based on the containing Varnode, then on the bit boundary\n/// \\param op2 is a field to compare with \\b this\n/// \\return \\b true if \\b this should be sorted before the other field\nbool FieldContext::operator<(const FieldContext &op2) const\n\n{\n if (sym->getName() != op2.sym->getName())\n return (sym->getName() < op2.sym->getName());\n return (qual->low < op2.qual->low);\n}\n\nvoid MacroBuilder::free(void)\n\n{\n vector::iterator iter;\n\n for(iter=params.begin();iter!=params.end();++iter)\n delete *iter;\n\n params.clear();\n}\n\n/// The error is passed up to the main parse object and a note is made\n/// locally that an error occurred so parsing can be terminated immediately.\n/// \\param loc is the parse location where the error occurred\n/// \\param val is the error message\nvoid MacroBuilder::reportError(const Location* loc, const string &val)\n\n{\n slgh->reportError(loc, val);\n haserror = true;\n}\n\n/// Given the op corresponding to the invocation, set up the specific parameters.\n/// \\param macroop is the given MACRO directive op\nvoid MacroBuilder::setMacroOp(OpTpl *macroop)\n\n{\n VarnodeTpl *vn;\n HandleTpl *hand;\n free();\n for(int4 i=1;inumInput();++i) {\n vn = macroop->getIn(i);\n hand = new HandleTpl(vn);\n params.push_back(hand);\n }\n}\n\n/// \\brief Given a cloned OpTpl, substitute parameters and add to the output list\n///\n/// VarnodesTpls used by the op are examined to see if they are derived from\n/// parameters of the macro. If so, details of the parameters actively passed\n/// as part of the specific macro invocation are substituted into the VarnodeTpl.\n/// Truncation operations on a macro parameter may cause additional CPUI_SUBPIECE\n/// operators to be inserted as part of the expansion and certain forms are not\n/// permitted.\n/// \\param op is the cloned op to emit\n/// \\param params is the set of parameters specific to the macro invocation\n/// \\return \\b true if there are no illegal truncations\nbool MacroBuilder::transferOp(OpTpl *op,vector ¶ms)\n\n{ // Fix handle details of a macro generated OpTpl relative to its specific invocation\n // and transfer it into the output stream\n VarnodeTpl *outvn = op->getOut();\n int4 handleIndex = 0;\n int4 plus;\n bool hasrealsize = false;\n uintb realsize = 0;\n\n if (outvn != (VarnodeTpl *)0) {\n plus = outvn->transfer(params);\n if (plus >= 0) {\n reportError((const Location *)0, \"Cannot currently assign to bitrange of macro parameter that is a temporary\");\n return false;\n }\n }\n for(int4 i=0;inumInput();++i) {\n VarnodeTpl *vn = op->getIn(i);\n if (vn->getOffset().getType() == ConstTpl::handle) {\n handleIndex = vn->getOffset().getHandleIndex();\n hasrealsize = (vn->getSize().getType() == ConstTpl::real);\n realsize = vn->getSize().getReal();\n }\n plus = vn->transfer(params);\n if (plus >= 0) {\n if (!hasrealsize) {\n\treportError((const Location *)0, \"Problem with bit range operator in macro\");\n\treturn false;\n }\n uintb newtemp = slgh->getUniqueAddr(); // Generate a new temporary location\n\n // Generate a SUBPIECE op that implements the offset_plus\n OpTpl *subpieceop = new OpTpl(CPUI_SUBPIECE);\n VarnodeTpl *newvn = new VarnodeTpl(ConstTpl(slgh->getUniqueSpace()),ConstTpl(ConstTpl::real,newtemp),\n\t\t\t\t\t ConstTpl(ConstTpl::real,realsize));\n subpieceop->setOutput(newvn);\n HandleTpl *hand = params[handleIndex];\n VarnodeTpl *origvn = new VarnodeTpl( hand->getSpace(), hand->getPtrOffset(), hand->getSize() );\n subpieceop->addInput(origvn);\n VarnodeTpl *plusvn = new VarnodeTpl( ConstTpl(slgh->getConstantSpace()), ConstTpl(ConstTpl::real,plus),\n\t\t\t\t\t ConstTpl(ConstTpl::real, 4) );\n subpieceop->addInput(plusvn);\n outvec.push_back(subpieceop);\n\n delete vn;\t\t// Replace original varnode\n op->setInput(new VarnodeTpl( *newvn ), i); // with output of subpiece\n }\n }\n outvec.push_back(op);\n return true;\n}\n\nvoid MacroBuilder::dump(OpTpl *op)\n\n{\n OpTpl *clone;\n VarnodeTpl *v_clone,*vn;\n \n clone = new OpTpl(op->getOpcode());\n vn = op->getOut();\n if (vn != (VarnodeTpl *)0) {\n v_clone = new VarnodeTpl(*vn);\n clone->setOutput(v_clone);\n }\n for(int4 i=0;inumInput();++i) {\n vn = op->getIn(i);\n v_clone = new VarnodeTpl(*vn);\n if (v_clone->isRelative()) {\n // Adjust relative index, depending on the labelbase\n uintb val = v_clone->getOffset().getReal() + getLabelBase();\n v_clone->setRelative(val);\n }\n clone->addInput(v_clone);\n }\n if (!transferOp(clone,params))\n delete clone;\n}\n\nvoid MacroBuilder::setLabel(OpTpl *op)\n\n{ // A label within a macro is local to the macro, but when\n // we expand the macro, we have to adjust the index of\n // the label, which is local to the macro, so that it fits\n // in with other labels local to the parent\n OpTpl *clone;\n VarnodeTpl *v_clone;\n\n clone = new OpTpl(op->getOpcode());\n v_clone = new VarnodeTpl( *op->getIn(0) ); // Clone the label index\n // Make adjustment to macro local value so that it is parent local\n uintb val = v_clone->getOffset().getReal() + getLabelBase();\n v_clone->setOffset(val);\n clone->addInput(v_clone);\n outvec.push_back(clone);\n}\n\nuint4 SleighPcode::allocateTemp(void)\n\n{\n return compiler->getUniqueAddr();\n}\n\nconst Location *SleighPcode::getLocation(SleighSymbol *sym) const\n\n{\n return compiler->getLocation(sym);\n}\n\nvoid SleighPcode::reportError(const Location *loc, const string &msg)\n\n{\n return compiler->reportError(loc, msg);\n}\n\nvoid SleighPcode::reportWarning(const Location *loc, const string &msg)\n\n{\n return compiler->reportWarning(loc, msg);\n}\n\nvoid SleighPcode::addSymbol(SleighSymbol *sym)\n\n{\n return compiler->addSymbol(sym);\n}\n\nSleighCompile::SleighCompile(void)\n : SleighBase()\n{\n pcode.setCompiler(this);\n contextlock = false;\t\t// Context layout is not locked\n userop_count = 0;\n errors = 0;\n warnunnecessarypcode = false;\n warndeadtemps = false;\n lenientconflicterrors = true;\n warnalllocalcollisions = false;\n warnallnops = false;\n failinsensitivedups = true;\n debugoutput = false;\n root = (SubtableSymbol *)0;\n curmacro = (MacroSymbol *)0;\n curct = (Constructor *)0;\n}\n\n/// Create the address spaces: \\b const, \\b unique, and \\b other.\n/// Define the special symbols: \\b inst_start, \\b inst_next, \\b inst_next2, \\b epsilon.\n/// Define the root subtable symbol: \\b instruction\nvoid SleighCompile::predefinedSymbols(void)\n\n{\n symtab.addScope();\t\t// Create global scope\n\n\t\t\t\t// Some predefined symbols\n root = new SubtableSymbol(\"instruction\"); // Base constructors\n symtab.addSymbol(root);\n insertSpace(new ConstantSpace(this,this));\n SpaceSymbol *spacesym = new SpaceSymbol(getConstantSpace()); // Constant space\n symtab.addSymbol(spacesym);\n OtherSpace *otherSpace = new OtherSpace(this,this,OtherSpace::INDEX);\n insertSpace(otherSpace);\n spacesym = new SpaceSymbol(otherSpace);\n symtab.addSymbol(spacesym);\n insertSpace(new UniqueSpace(this,this,numSpaces(),0));\n spacesym = new SpaceSymbol(getUniqueSpace()); // Temporary register space\n symtab.addSymbol(spacesym);\n StartSymbol *startsym = new StartSymbol(\"inst_start\",getConstantSpace());\n symtab.addSymbol(startsym);\n EndSymbol *endsym = new EndSymbol(\"inst_next\",getConstantSpace());\n symtab.addSymbol(endsym);\n Next2Symbol *next2sym = new Next2Symbol(\"inst_next2\",getConstantSpace());\n symtab.addSymbol(next2sym);\n EpsilonSymbol *epsilon = new EpsilonSymbol(\"epsilon\",getConstantSpace());\n symtab.addSymbol(epsilon);\n pcode.setConstantSpace(getConstantSpace());\n pcode.setUniqueSpace(getUniqueSpace());\n}\n\n/// \\brief Calculate the complete context layout for all definitions sharing the same backing storage Varnode\n///\n/// Internally context is stored in an array of (32-bit) words. The bit-range for each field definition is\n/// adjusted to pack the fields within this array, but overlapping bit-ranges between definitions are preserved.\n/// Due to the internal storage word size, the covering range across a set of overlapping definitions cannot\n/// exceed the word size (of 32-bits).\n/// Within the sorted list of all context definitions, the subset sharing the same backing storage is\n/// provided to this method as a starting index and a size (of the subset), along with the total number\n/// of context bits already allocated.\n/// \\param start is the provided starting index of the definition subset\n/// \\param sz is the provided number of definitions in the subset\n/// \\param numbits is the number of previously allocated context bits\n/// \\return the total number of allocated bits (after the new allocations)\nint4 SleighCompile::calcContextVarLayout(int4 start,int4 sz,int4 numbits)\n\n{\n VarnodeSymbol *sym = contexttable[start].sym;\n FieldQuality *qual;\n int4 i,j;\n int4 maxbits;\n \n if ((sym->getSize()) % 4 != 0)\n reportError(getCurrentLocation(), \"Invalid size of context register '\"+sym->getName()+\"': must be a multiple of 4 bytes\");\n maxbits = sym->getSize() * 8 -1;\n i = 0;\n while(ilow;\n int4 max = qual->high;\n if ((max - min) > (8*sizeof(uintm)))\n reportError(getCurrentLocation(), \"Size of bitfield '\" + qual->name + \"' larger than 32 bits\");\n if (max > maxbits)\n reportError(getCurrentLocation(), \"Scope of bitfield '\" + qual->name + \"' extends beyond the size of context register\");\n j = i+1;\n // Find union of fields overlapping with first field\n while(jlow <= max) {\t// We have overlap of context variables\n\tif (qual->high > max)\n\t max = qual->high;\n\t// reportWarning(\"Local context variables overlap in \"+sym->getName(),false);\n }\n else\n\tbreak;\n j = j+1;\n }\n\n int4 alloc = max-min+1;\n int4 startword = numbits / (8*sizeof(uintm));\n int4 endword = (numbits+alloc-1) / (8*sizeof(uintm));\n if (startword != endword)\n numbits = endword * (8*sizeof(uintm)); // Bump up to next word\n\n uint4 low = numbits;\n numbits += alloc;\n\n for(;ilow - min + low;\n uint4 h = numbits-1-(max-qual->high);\n ContextField *field = new ContextField(qual->signext,l,h);\n addSymbol(new ContextSymbol(qual->name,field,sym,qual->low,qual->high,qual->flow));\n }\n \n }\n sym->markAsContext();\n return numbits;\n}\n\n/// A separate decision tree is calculated for each subtable, and information about\n/// conflicting patterns is accumulated. Identical pattern pairs are reported\n/// as errors, and indistinguishable pattern pairs are reported as errors depending\n/// on the \\b lenientconflicterrors setting.\nvoid SleighCompile::buildDecisionTrees(void)\n\n{\n DecisionProperties props;\n root->buildDecisionTree(props);\n\n for(int4 i=0;ibuildDecisionTree(props);\n\n const vector > &ierrors( props.getIdentErrors() );\n if (ierrors.size() != 0) {\n string identMsg = \"Constructor has identical pattern to constructor at \";\n for(int4 i=0;iformat());\n reportError(locB, identMsg + locA->format());\n }\n }\n\n const vector > &cerrors( props.getConflictErrors() );\n if (!lenientconflicterrors && cerrors.size() != 0) {\n string conflictMsg = \"Constructor pattern cannot be distinguished from constructor at \";\n for(int4 i=0;iformat());\n reportError(locB, conflictMsg + locA->format());\n }\n }\n}\n\n/// For each Constructor, generate the final pattern (TokenPattern) used to match it from\n/// the parsed constraints (PatternEquation). Accumulated error messages are reported.\nvoid SleighCompile::buildPatterns(void)\n\n{\n if (root == 0) {\n reportError((const Location *)0, \"No patterns to match.\");\n return;\n }\n ostringstream msg;\n root->buildPattern(msg);\t// This should recursively hit everything\n if (root->isError()) {\n reportError(getLocation(root), msg.str());\n errors += 1;\n }\n for(int4 i=0;iisError()) {\n reportError(getLocation(tables[i]), \"Problem in table '\"+tables[i]->getName() + \"':\" + msg.str());\n errors += 1;\n }\n if (tables[i]->getPattern() == (TokenPattern *)0) {\n reportWarning(getLocation(tables[i]), \"Unreferenced table '\"+tables[i]->getName() + \"'\");\n }\n }\n}\n\n/// Optimization is performed across all p-code sections. Size restriction and other consistency\n/// checks are performed. Errors and warnings are reported as appropriate.\nvoid SleighCompile::checkConsistency(void)\n\n{\n ConsistencyChecker checker(this, root,warnunnecessarypcode,warndeadtemps);\n\n if (!checker.testSizeRestrictions()) {\n errors += 1;\n return;\n }\n if (!checker.testTruncations()) {\n errors += 1;\n return;\n }\n if ((!warnunnecessarypcode)&&(checker.getNumUnnecessaryPcode() > 0)) {\n ostringstream msg;\n msg << dec << checker.getNumUnnecessaryPcode();\n msg << \" unnecessary extensions/truncations were converted to copies\";\n reportWarning(msg.str());\n reportWarning(\"Use -u switch to list each individually\");\n }\n checker.optimizeAll();\n if (checker.getNumReadNoWrite() > 0) {\n errors += 1;\n return;\n }\n if ((!warndeadtemps)&&(checker.getNumWriteNoRead() > 0)) {\n ostringstream msg;\n msg << dec << checker.getNumWriteNoRead();\n msg << \" operations wrote to temporaries that were not read\";\n reportWarning(msg.str());\n reportWarning(\"Use -t switch to list each individually\");\n }\n checker.testLargeTemporary();\n}\n\n/// \\brief Search for offset matches between a previous set and the given current set\n///\n/// This method is given a collection of offsets, each mapped to a particular set index.\n/// A new set of offsets and set index is given. The new set is added to the collection.\n/// If any offset in the new set matches an offset in one of the old sets, the old matching\n/// set index is returned. Otherwise -1 is returned.\n/// \\param local2Operand is the collection of previous offsets\n/// \\param locals is the new given set of offsets\n/// \\param operand is the new given set index\n/// \\return the set index of an old matching offset or -1\nint4 SleighCompile::findCollision(map &local2Operand,const vector &locals,int operand)\n\n{\n for(int4 i=0;i::iterator,bool> res;\n res = local2Operand.insert(pair(locals[i],operand));\n if (!res.second) {\n int4 oldIndex = (*res.first).second;\n if (oldIndex != operand)\n\treturn oldIndex;\n }\n }\n return -1;\n}\n\n/// Because local variables can be exported and subtable symbols can be reused as operands across\n/// multiple Constructors, its possible for different operands in the same Constructor to be assigned\n/// the same exported local variable. As this is a potential spec design problem, this method searches\n/// for these collisions and potentially reports a warning.\n/// For each operand of the given Constructor, the potential local variable exports are collected and\n/// compared with the other operands. Any potential collision may generate a warning and causes\n/// \\b false to be returned.\n/// \\param ct is the given Constructor\n/// \\return \\b true if there are no potential collisions between operands\nbool SleighCompile::checkLocalExports(Constructor *ct)\n\n{\n if (ct->getTempl() == (ConstructTpl *)0)\n return true;\t\t// No template, collisions impossible\n if (ct->getTempl()->buildOnly())\n return true;\t\t// Operand exports aren't manipulated, so no collision is possible\n if (ct->getNumOperands() < 2)\n return true;\t\t// Collision can only happen with multiple operands\n bool noCollisions = true;\n map collect;\n for(int4 i=0;igetNumOperands();++i) {\n vector newCollect;\n ct->getOperand(i)->collectLocalValues(newCollect);\n if (newCollect.empty()) continue;\n int4 collideOperand = findCollision(collect, newCollect, i);\n if (collideOperand >= 0) {\n noCollisions = false;\n if (warnalllocalcollisions) {\n\treportWarning(getLocation(ct), \"Possible operand collision between symbols '\"\n\t\t + ct->getOperand(collideOperand)->getName()\n\t\t + \"' and '\"\n\t\t + ct->getOperand(i)->getName() + \"'\");\n }\n break;\t// Don't continue\n }\n }\n return noCollisions;\n}\n\n/// Check each Constructor for collisions in turn. If there are any collisions\n/// report a warning indicating the number of Construtors with collisions. Optionally\n/// generate a warning for each colliding Constructor.\nvoid SleighCompile::checkLocalCollisions(void)\n\n{\n int4 collisionCount = 0;\n SubtableSymbol *sym = root; // Start with the instruction table\n int4 i = -1;\n for(;;) {\n int4 numconst = sym->getNumConstructors();\n for(int4 j=0;jgetConstructor(j)))\n\tcollisionCount += 1;\n }\n i+=1;\n if (i>=tables.size()) break;\n sym = tables[i];\n }\n if (collisionCount > 0) {\n ostringstream msg;\n msg << dec << collisionCount << \" constructors with local collisions between operands\";\n reportWarning(msg.str());\n if (!warnalllocalcollisions)\n reportWarning(\"Use -c switch to list each individually\");\n }\n}\n\n/// The number of \\e empty Constructors, with no p-code and no export, is always reported.\n/// Optionally, empty Constructors are reported individually.\nvoid SleighCompile::checkNops(void)\n\n{\n if (noplist.size() > 0) {\n if (warnallnops) {\n for(int4 i=0;i` directive, in an address space of\n/// type \\e IPTR_PROCESSOR (either RAM or REGISTER)\nvoid SleighCompile::checkCaseSensitivity(void)\n\n{\n if (!failinsensitivedups) return;\t\t// Case insensitive duplicates don't cause error\n map registerMap;\n SymbolScope *scope = symtab.getGlobalScope();\n SymbolTree::const_iterator iter;\n for(iter=scope->begin();iter!=scope->end();++iter) {\n SleighSymbol *sym = *iter;\n if (sym->getType() != SleighSymbol::varnode_symbol) continue;\n VarnodeSymbol *vsym = (VarnodeSymbol *)sym;\n AddrSpace *space = vsym->getFixedVarnode().space;\n if (space->getType() != IPTR_PROCESSOR) continue;\n string nm = sym->getName();\n transform(nm.begin(), nm.end(), nm.begin(), ::toupper);\n pair::iterator,bool> check;\n check = registerMap.insert( pair(nm,sym) );\n if (!check.second) {\t// Name already existed\n SleighSymbol *oldsym = (*check.first).second;\n ostringstream s;\n s << \"Name collision: \" << sym->getName() << \" --- \";\n s << \"Duplicate symbol \" << oldsym->getName();\n const Location *oldLocation = getLocation(oldsym);\n if (oldLocation != (Location *) 0x0) {\n s << \" defined at \" << oldLocation->format();\n }\n const Location *location = getLocation(sym);\n reportError(location,s.str());\n }\n }\n}\n\n/// Each label symbol define which operator is being labeled and must also be\n/// used as a jump destination by at least 1 operator. A description of each\n/// symbol violating this is accumulated in a string returned by this method.\n/// \\param scope is the scope across which to look for label symbols\n/// \\return the accumulated error messages\nstring SleighCompile::checkSymbols(SymbolScope *scope)\n\n{\n ostringstream msg;\n SymbolTree::const_iterator iter;\n for(iter=scope->begin();iter!=scope->end();++iter) {\n LabelSymbol *sym = (LabelSymbol *)*iter;\n if (sym->getType() != SleighSymbol::label_symbol) continue;\n if (sym->getRefCount() == 0)\n msg << \" Label <\" << sym->getName() << \"> was placed but not used\" << endl;\n else if (!sym->isPlaced())\n msg << \" Label <\" << sym->getName() << \"> was referenced but never placed\" << endl;\n }\n return msg.str();\n}\n\n/// The symbol definition is assumed to have just been parsed. It is added to the\n/// table within the current scope as determined by the parse state and is cross\n/// referenced with the current parse location.\n/// Duplicate symbol exceptions are caught and reported as a parse error.\n/// \\param sym is the new symbol\nvoid SleighCompile::addSymbol(SleighSymbol *sym)\n\n{\n try {\n symtab.addSymbol(sym);\n symbolLocationMap[sym] = *getCurrentLocation();\n }\n catch(SleighError &err) {\n reportError(err.explain);\n }\n}\n\n/// \\param ctor is the given Constructor\n/// \\return the filename and line number\nconst Location *SleighCompile::getLocation(Constructor *ctor) const\n\n{\n return &ctorLocationMap.at(ctor);\n}\n\n/// \\param sym is the given symbol\n/// \\return the filename and line number or null if location not found\nconst Location *SleighCompile::getLocation(SleighSymbol *sym) const\n\n{\n try {\n return &symbolLocationMap.at(sym);\n } catch (const out_of_range &e) {\n return nullptr;\n }\n}\n\n/// The current filename and line number are placed into a Location object\n/// which is then returned.\n/// \\return the current Location\nconst Location *SleighCompile::getCurrentLocation(void) const\n\n{\n // Update the location cache field\n currentLocCache = Location(filename.back(), lineno.back());\n return ¤tLocCache;\n}\n\n/// \\brief Format an error or warning message given an optional source location\n///\n/// \\param loc is the given source location (or null)\n/// \\param msg is the message\n/// \\return the formatted message\nstring SleighCompile::formatStatusMessage(const Location* loc, const string &msg)\n\n{\n ostringstream s;\n if (loc != (Location*)0) {\n s << loc->format();\n s << \": \";\n }\n s << msg;\n return s.str();\n}\n\n/// The error message is formatted indicating the location of the error in source.\n/// The message is displayed for the user and a count is incremented.\n/// Otherwise, parsing can continue, but the compiler will not produce an output file.\n/// \\param loc is the location of the error\n/// \\param msg is the error message\nvoid SleighCompile::reportError(const Location* loc, const string &msg)\n\n{\n reportError(formatStatusMessage(loc, msg));\n}\n\n/// The message is formatted and displayed for the user and a count is incremented.\n/// If there are too many fatal errors, the entire compilation process is terminated.\n/// Otherwise, parsing can continue, but the compiler will not produce an output file.\n/// \\param msg is the error message\nvoid SleighCompile::reportError(const string &msg)\n\n{\n cerr << filename.back() << \":\" << lineno.back() << \" - ERROR \" << msg << endl;\n errors += 1;\n if (errors > 1000000) {\n cerr << \"Too many errors: Aborting\" << endl;\n exit(2);\n }\n}\n\n/// The message indicates a potential problem with the SLEIGH specification but does not\n/// prevent compilation from producing output.\n/// \\param loc is the location of the problem in source\n/// \\param msg is the warning message\nvoid SleighCompile::reportWarning(const Location* loc, const string &msg)\n\n{\n reportWarning(formatStatusMessage(loc, msg));\n}\n\n/// The message indicates a potential problem with the SLEIGH specification but does not\n/// prevent compilation from producing output.\n/// \\param msg is the warning message\nvoid SleighCompile::reportWarning(const string &msg)\n\n{\n cerr << \"WARN \" << msg << endl;\n}\n\n/// The \\e unique space acts as a pool of temporary registers that are drawn as needed.\n/// As Varnode sizes are frequently inferred and not immediately available during the parse,\n/// this method does not make an assumption about the size of the requested temporary Varnode.\n/// It reserves a fixed amount of space and returns its starting offset.\n/// \\return the starting offset of the new temporary register\nuint4 SleighCompile::getUniqueAddr(void)\n\n{\n uint4 base = getUniqueBase();\n setUniqueBase(base + SleighBase::MAX_UNIQUE_SIZE);\n return base;\n}\n\n/// This method is called after parsing is complete. It builds the final Constructor patterns,\n/// builds decision trees, does p-code optimization, and builds cross referencing structures.\n/// A number of checks are also performed, which may generate errors or warnings, including\n/// size restriction checks, pattern conflict checks, NOP constructor checks, and\n/// local collision checks. Once this method is run, \\b this SleighCompile is ready for the\n/// encode method.\nvoid SleighCompile::process(void)\n\n{\n checkNops();\n checkCaseSensitivity();\n if (getDefaultCodeSpace() == (AddrSpace *)0)\n reportError(\"No default space specified\");\n if (errors>0) return;\n checkConsistency();\n if (errors>0) return;\n checkLocalCollisions();\n if (errors>0) return;\n buildPatterns();\n if (errors>0) return;\n buildDecisionTrees();\n if (errors>0) return;\n vector errorPairs;\n buildXrefs(errorPairs);\t\t// Make sure we can build crossrefs properly\n if (!errorPairs.empty()) {\n for(int4 i=0;i::const_iterator iter = preproc_defines.find(nm);\n if (iter == preproc_defines.end()) return false;\n res = (*iter).second;\n return true;\n}\n\n/// The string value is associated with the variable name.\n/// \\param nm is the name of the given preprocessor variable\n/// \\param value is the string value to associate\nvoid SleighCompile::setPreprocValue(const string &nm,const string &value)\n\n{\n preproc_defines[nm] = value;\n}\n\n/// Any existing string value associated with the variable is removed.\n/// \\param nm is the name of the given preprocessor variable\n/// \\return \\b true if the variable had a value (was defined) initially\nbool SleighCompile::undefinePreprocValue(const string &nm)\n\n{\n map::iterator iter = preproc_defines.find(nm);\n if (iter==preproc_defines.end()) return false;\n preproc_defines.erase(iter);\n return true;\n}\n\n// Functions needed by the parser\n\n/// \\brief Define a new SLEIGH token\n///\n/// In addition to the name and size, an endianness code is provided, with the possible values:\n/// - -1 indicates a \\e little endian interpretation is forced on the token\n/// - 0 indicates the global endianness setting is used for the token\n/// - 1 indicates a \\e big endian interpretation is forced on the token\n///\n/// \\param name is the name of the token\n/// \\param sz is the number of bits in the token\n/// \\param endian is the endianness code\n/// \\return the new token symbol\nTokenSymbol *SleighCompile::defineToken(string *name,uintb *sz,int4 endian)\n\n{\n uint4 size = *sz;\n delete sz;\n if ((size&7)!=0) {\n reportError(getCurrentLocation(), \"'\" + *name + \"': token size must be multiple of 8\");\n size = (size/8)+1;\n }\n else\n size = size/8;\n bool isBig;\n if (endian ==0)\n isBig = isBigEndian();\n else\n isBig = (endian > 0);\n Token *newtoken = new Token(*name,size,isBig,tokentable.size());\n tokentable.push_back(newtoken);\n delete name;\n TokenSymbol *res = new TokenSymbol(newtoken);\n addSymbol(res);\n return res;\n}\n\n/// \\brief Add a new field definition to the given token\n///\n/// \\param sym is the given token\n/// \\param qual is the set of parsed qualities to associate with the new field\nvoid SleighCompile::addTokenField(TokenSymbol *sym,FieldQuality *qual)\n\n{\n if (qual->high < qual->low) {\n ostringstream s;\n s << \"Field '\" << qual->name << \"' starts at \" << qual->low << \" and ends at \" << qual->high;\n reportError(getCurrentLocation(), s.str());\n }\n if (sym->getToken()->getSize() * 8 <= qual->high) {\n ostringstream s;\n s << \"Field '\" << qual->name << \"' high must be less than token size\";\n reportError(getCurrentLocation(), s.str());\n }\n TokenField *field = new TokenField(sym->getToken(),qual->signext,qual->low,qual->high);\n addSymbol(new ValueSymbol(qual->name,field));\n delete qual;\n}\n\n/// \\brief Add a new context field definition to the given backing Varnode\n///\n/// \\param sym is the given Varnode providing backing storage for the context field\n/// \\param qual is the set of parsed qualities to associate with the new field\nbool SleighCompile::addContextField(VarnodeSymbol *sym,FieldQuality *qual)\n\n{\n if (qual->high < qual->low) {\n ostringstream s;\n s << \"Context field '\" << qual->name << \"' starts at \" << qual->low << \" and ends at \" << qual->high;\n reportError(getCurrentLocation(), s.str());\n }\n if (sym->getSize() * 8 <= qual->high) {\n ostringstream s;\n s << \"Context field '\" << qual->name << \"' high must be less than context size\";\n reportError(getCurrentLocation(), s.str());\n }\n if (contextlock)\n return false;\t\t// Context layout has already been satisfied\n\n contexttable.push_back(FieldContext(sym,qual));\n return true;\n}\n\n/// \\brief Define a new addresds space\n///\n/// \\param qual is the set of parsed qualities to associate with the new space\nvoid SleighCompile::newSpace(SpaceQuality *qual)\n\n{\n if (qual->size == 0) {\n reportError(getCurrentLocation(), \"Space definition '\" + qual->name + \"' missing size attribute\");\n delete qual;\n return;\n }\n\n int4 delay = (qual->type == SpaceQuality::registertype) ? 0 : 1;\n AddrSpace *spc = new AddrSpace(this,this,IPTR_PROCESSOR,qual->name,isBigEndian(),\n\t\t\t\t qual->size,qual->wordsize,numSpaces(),AddrSpace::hasphysical,delay,delay);\n insertSpace(spc);\n if (qual->isdefault) {\n if (getDefaultCodeSpace() != (AddrSpace *)0)\n reportError(getCurrentLocation(), \"Multiple default spaces -- '\" + getDefaultCodeSpace()->getName() + \"', '\" + qual->name + \"'\");\n else {\n setDefaultCodeSpace(spc->getIndex());\t// Make the flagged space the default\n pcode.setDefaultSpace(spc);\n }\n }\n delete qual;\n addSymbol( new SpaceSymbol(spc) );\n}\n\n/// \\brief Start a new named p-code section and define the associated section symbol\n///\n/// \\param nm is the name of the section\n/// \\return the new section symbol\nSectionSymbol *SleighCompile::newSectionSymbol(const string &nm)\n\n{\n SectionSymbol *sym = new SectionSymbol(nm,sections.size());\n try {\n symtab.addGlobalSymbol(sym);\n } catch(SleighError &err) {\n reportError(getCurrentLocation(), err.explain);\n }\n sections.push_back(sym);\n numSections = sections.size();\n return sym;\n}\n\n/// \\brief Set the global endianness of the SLEIGH specification\n///\n/// This \\b must be called at the very beginning of the parse.\n/// This method additionally establishes predefined symbols for the specification.\n/// \\param end is the endianness value (0=little 1=big)\nvoid SleighCompile::setEndian(int4 end)\n\n{\n setBigEndian( (end == 1) );\n predefinedSymbols();\t\t// Set up symbols now that we know endianness\n}\n\n/// \\brief Definition a set of Varnodes\n///\n/// Storage for each Varnode is allocated in sequence from the given address space,\n/// starting from the specified offset.\n/// \\param spacesym is the given address space\n/// \\param off is the starting offset\n/// \\param size is the size (in bytes) to allocate for each Varnode\n/// \\param names is the list of Varnode names to define\nvoid SleighCompile::defineVarnodes(SpaceSymbol *spacesym,uintb *off,uintb *size,vector *names)\n\n{\n AddrSpace *spc = spacesym->getSpace();\n uintb myoff = *off;\n for(int4 i=0;isize();++i) {\n if ((*names)[i] != \"_\")\n addSymbol( new VarnodeSymbol((*names)[i],spc,myoff,*size) );\n myoff += *size;\n }\n delete names;\n delete off;\n delete size;\n}\n\n/// \\brief Define a new Varnode symbol as a subrange of bits within another symbol\n///\n/// If the ends of the range fall on byte boundaries, we\n/// simply define a normal VarnodeSymbol, otherwise we create\n/// a special symbol which is a place holder for the bitrange operator\n/// \\param name is the name of the new Varnode\n/// \\param sym is the parent Varnode\n/// \\param bitoffset is the (least significant) starting bit of the new Varnode within the parent\n/// \\param numb is the number of bits in the new Varnode\nvoid SleighCompile::defineBitrange(string *name,VarnodeSymbol *sym,uint4 bitoffset,uint4 numb)\n\n{\n string namecopy = *name;\n delete name;\n uint4 size = 8*sym->getSize(); // Number of bits\n if (numb == 0) {\n reportError(getCurrentLocation(), \"'\" + namecopy + \"': size of bitrange is zero\");\n return;\n }\n if ((bitoffset >= size)||((bitoffset+numb)>size)) {\n reportError(getCurrentLocation(), \"'\" + namecopy + \"': bad bitrange\");\n return;\n }\n if ((bitoffset%8 == 0)&&(numb%8 == 0)) {\n // This can be reduced to an ordinary varnode definition\n AddrSpace *newspace = sym->getFixedVarnode().space;\n uintb newoffset = sym->getFixedVarnode().offset;\n int4 newsize = numb/8;\n if (isBigEndian())\n newoffset += (size-bitoffset-numb)/8;\n else\n newoffset += bitoffset/8;\n addSymbol( new VarnodeSymbol(namecopy,newspace,newoffset,newsize) );\n }\n else\t\t\t\t// Otherwise define the special symbol\n addSymbol( new BitrangeSymbol(namecopy,sym,bitoffset,numb) );\n}\n\n/// \\brief Define a list of new user-defined operators\n///\n/// A new symbol is created for each name.\n/// \\param names is the list of names\nvoid SleighCompile::addUserOp(vector *names)\n\n{\n for(int4 i=0;isize();++i) {\n UserOpSymbol *sym = new UserOpSymbol((*names)[i]);\n sym->setIndex(userop_count++);\n addSymbol( sym );\n }\n delete names;\n}\n\n/// Find duplicates in the list and null out any entry but the first.\n/// Return an example of a symbol with duplicates or null if there are\n/// no duplicates.\n/// \\param symlist is the given list of symbols (which may contain nulls)\n/// \\return an example symbol with a duplicate are null\nSleighSymbol *SleighCompile::dedupSymbolList(vector *symlist)\n\n{\n SleighSymbol *res = (SleighSymbol *)0;\n for(int4 i=0;isize();++i) {\n SleighSymbol *sym = (*symlist)[i];\n if (sym == (SleighSymbol *)0) continue;\n for(int4 j=i+1;jsize();++j) {\n if ((*symlist)[j] == sym) { // Found a duplicate\n\tres = sym;\t\t// Return example duplicate for error reporting\n\t(*symlist)[j] = (SleighSymbol *)0; // Null out the duplicate\n }\n }\n }\n return res;\n}\n\n/// \\brief Attach a list integer values, to each value symbol in the given list\n///\n/// Each symbol's original bit representation is no longer used as the absolute integer\n/// value associated with the symbol. Instead it is used to map into this integer list.\n/// \\param symlist is the given list of value symbols\n/// \\param numlist is the list of integer values to attach\nvoid SleighCompile::attachValues(vector *symlist,vector *numlist)\n\n{\n SleighSymbol *dupsym = dedupSymbolList(symlist);\n if (dupsym != (SleighSymbol *)0)\n reportWarning(getCurrentLocation(), \"'attach values' list contains duplicate entries: \"+dupsym->getName());\n for(int4 i=0;isize();++i) {\n ValueSymbol *sym = (ValueSymbol *)(*symlist)[i];\n if (sym == (ValueSymbol *)0) continue;\n PatternValue *patval = sym->getPatternValue();\n if (patval->maxValue() + 1 != numlist->size()) {\n ostringstream msg;\n msg << \"Attach value '\" + sym->getName();\n msg << \"' (range 0..\" << patval->maxValue() << \") is wrong size for list (of \" << numlist->size() << \" entries)\";\n reportError(getCurrentLocation(), msg.str());\n }\n symtab.replaceSymbol(sym, new ValueMapSymbol(sym->getName(),patval,*numlist));\n }\n delete numlist;\n delete symlist;\n}\n\n/// \\brief Attach a list of display names to the given list of value symbols\n///\n/// Each symbol's original bit representation is no longer used as the display name\n/// for the symbol. Instead it is used to map into this list of display names.\n/// \\param symlist is the given list of value symbols\n/// \\param names is the list of display names to attach\nvoid SleighCompile::attachNames(vector *symlist,vector *names)\n\n{\n SleighSymbol *dupsym = dedupSymbolList(symlist);\n if (dupsym != (SleighSymbol *)0)\n reportWarning(getCurrentLocation(), \"'attach names' list contains duplicate entries: \"+dupsym->getName());\n for(int4 i=0;isize();++i) {\n ValueSymbol *sym = (ValueSymbol *)(*symlist)[i];\n if (sym == (ValueSymbol *)0) continue;\n PatternValue *patval = sym->getPatternValue();\n if (patval->maxValue() + 1 != names->size()) {\n ostringstream msg;\n msg << \"Attach name '\" + sym->getName();\n msg << \"' (range 0..\" << patval->maxValue() << \") is wrong size for list (of \" << names->size() << \" entries)\";\n reportError(getCurrentLocation(), msg.str());\n }\n symtab.replaceSymbol(sym,new NameSymbol(sym->getName(),patval,*names));\n }\n delete names;\n delete symlist;\n}\n\n/// \\brief Attach a list of Varnodes to the given list of value symbols\n///\n/// Each symbol's original bit representation is no longer used as the display name and\n/// semantic value of the symbol. Instead it is used to map into this list of Varnodes.\n/// \\param symlist is the given list of value symbols\n/// \\param varlist is the list of Varnodes to attach\nvoid SleighCompile::attachVarnodes(vector *symlist,vector *varlist)\n\n{\n SleighSymbol *dupsym = dedupSymbolList(symlist);\n if (dupsym != (SleighSymbol *)0)\n reportWarning(getCurrentLocation(), \"'attach variables' list contains duplicate entries: \"+dupsym->getName());\n for(int4 i=0;isize();++i) {\n ValueSymbol *sym = (ValueSymbol *)(*symlist)[i];\n if (sym == (ValueSymbol *)0) continue;\n PatternValue *patval = sym->getPatternValue();\n if (patval->maxValue() + 1 != varlist->size()) {\n ostringstream msg;\n msg << \"Attach varnode '\" + sym->getName();\n msg << \"' (range 0..\" << patval->maxValue() << \") is wrong size for list (of \" << varlist->size() << \" entries)\";\n reportError(getCurrentLocation(), msg.str());\n }\n int4 sz = 0; \n for(int4 j=0;jsize();++j) {\n VarnodeSymbol *vsym = (VarnodeSymbol *)(*varlist)[j];\n if (vsym != (VarnodeSymbol *)0) {\n\tif (sz == 0)\n\t sz = vsym->getFixedVarnode().size;\n\telse if (sz != vsym->getFixedVarnode().size) {\n\t ostringstream msg;\n\t msg << \"Attach statement contains varnodes of different sizes -- \" << dec << sz << \" != \" << dec << vsym->getFixedVarnode().size;\n\t reportError(getCurrentLocation(), msg.str());\n\t break;\n\t}\n }\n }\n symtab.replaceSymbol(sym,new VarnodeListSymbol(sym->getName(),patval,*varlist));\n }\n delete varlist;\n delete symlist;\n}\n\n/// \\brief Define a new SLEIGH subtable\n///\n/// A symbol and table entry are created.\n/// \\param nm is the name of the new subtable\nSubtableSymbol *SleighCompile::newTable(string *nm)\n\n{\n SubtableSymbol *sym = new SubtableSymbol(*nm);\n addSymbol(sym);\n tables.push_back(sym);\n delete nm;\n return sym;\n}\n\n/// \\brief Define a new operand for the given Constructor\n///\n/// A symbol local to the Constructor is defined, which initially is unmapped.\n/// Operands are defined in order.\n/// \\param ct is the given Constructor\n/// \\param nm is the name of the new operand\nvoid SleighCompile::newOperand(Constructor *ct,string *nm)\n\n{\n int4 index = ct->getNumOperands();\n OperandSymbol *sym = new OperandSymbol(*nm,index,ct);\n addSymbol(sym);\n ct->addOperand(sym);\n delete nm;\n}\n\n/// \\brief Create a new constraint equation based on the given operand\n///\n/// The constraint forces the operand to \\e match the specified expression\n/// \\param sym is the given operand\n/// \\param patexp is the specified expression\n/// \\return the new constraint equation\nPatternEquation *SleighCompile::constrainOperand(OperandSymbol *sym,PatternExpression *patexp)\n\n{\n PatternEquation *res;\n FamilySymbol *famsym = dynamic_cast(sym->getDefiningSymbol());\n if (famsym != (FamilySymbol *)0) { // Operand already defined as family symbol\n\t\t\t\t// This equation must be a constraint\n res = new EqualEquation(famsym->getPatternValue(),patexp);\n }\n else {\t\t\t// Operand is currently undefined, so we can't constrain\n PatternExpression::release(patexp);\n res = (PatternEquation *)0;\n }\n return res;\n}\n\n/// \\brief Map the local operand symbol to a PatternExpression\n///\n/// The operand symbol's display string and semantic value are calculated at\n/// disassembly time based on the specified expression.\n/// \\param sym is the local operand\n/// \\param patexp is the expression to map to the operand\nvoid SleighCompile::defineOperand(OperandSymbol *sym,PatternExpression *patexp)\n\n{\n try {\n sym->defineOperand(patexp);\n sym->setOffsetIrrelevant();\t// If not a self-definition, the operand has no\n\t\t\t\t// pattern directly associated with it, so\n\t\t\t\t// the operand's offset is irrelevant\n }\n catch(SleighError &err) {\n reportError(getCurrentLocation(), err.explain);\n PatternExpression::release(patexp);\n }\n}\n\n/// \\brief Define a new \\e invisible operand based on an existing symbol\n///\n/// A new symbol is defined that is considered an operand of the current Constructor,\n/// but its display does not contribute to the display of the Constructor.\n/// The new symbol may still contribute matching patterns and p-code\n/// \\param sym is the existing symbol that the new operand maps to\n/// \\return an (unconstrained) operand pattern\nPatternEquation *SleighCompile::defineInvisibleOperand(TripleSymbol *sym)\n\n{\n int4 index = curct->getNumOperands();\n OperandSymbol *opsym = new OperandSymbol(sym->getName(),index,curct);\n addSymbol(opsym);\n curct->addInvisibleOperand(opsym);\n PatternEquation *res = new OperandEquation(opsym->getIndex());\n SleighSymbol::symbol_type tp = sym->getType();\n try {\n if ((tp==SleighSymbol::value_symbol)||(tp==SleighSymbol::context_symbol)) {\n opsym->defineOperand(sym->getPatternExpression());\n }\n else {\n opsym->defineOperand(sym);\n }\n }\n catch(SleighError &err) {\n reportError(getCurrentLocation(), err.explain);\n }\n return res;\n}\n\n/// \\brief Map given operand to a global symbol of same name\n///\n/// The operand symbol still acts as a local symbol but gets its display,\n/// pattern, and semantics from the global symbol.\n/// \\param sym is the given operand\nvoid SleighCompile::selfDefine(OperandSymbol *sym)\n\n{\n TripleSymbol *glob = dynamic_cast(symtab.findSymbol(sym->getName(),1));\n if (glob == (TripleSymbol *)0) {\n reportError(getCurrentLocation(), \"No matching global symbol '\" + sym->getName() + \"'\");\n return;\n }\n SleighSymbol::symbol_type tp = glob->getType();\n try {\n if ((tp==SleighSymbol::value_symbol)||(tp==SleighSymbol::context_symbol)) {\n sym->defineOperand(glob->getPatternExpression());\n }\n else\n sym->defineOperand(glob);\n }\n catch(SleighError &err) {\n reportError(getCurrentLocation(), err.explain);\n }\n}\n\n/// \\brief Set \\e export of a Constructor to the given Varnode\n///\n/// SLEIGH symbols matching the Constructor use this Varnode as their semantic storage/value.\n/// \\param ct is the Constructor p-code section\n/// \\param vn is the given Varnode\n/// \\return the p-code section\nConstructTpl *SleighCompile::setResultVarnode(ConstructTpl *ct,VarnodeTpl *vn)\n\n{\n HandleTpl *res = new HandleTpl(vn);\n delete vn;\n ct->setResult(res);\n return ct;\n}\n\n/// \\brief Set a Constructor export to be the location pointed to by the given Varnode\n///\n/// SLEIGH symbols matching the Constructor use this dynamic location as their semantic storage/value.\n/// \\param ct is the Constructor p-code section\n/// \\param star describes the pointer details\n/// \\param vn is the given Varnode pointer\n/// \\return the p-code section\nConstructTpl *SleighCompile::setResultStarVarnode(ConstructTpl *ct,StarQuality *star,VarnodeTpl *vn)\n\n{\n HandleTpl *res = new HandleTpl(star->id,ConstTpl(ConstTpl::real,star->size),vn,\n\t\t\t\t getUniqueSpace(),getUniqueAddr());\n delete star;\n delete vn;\n ct->setResult(res);\n return ct;\n}\n\n/// \\brief Create a change operation that makes a temporary change to a context variable\n///\n/// The new change operation is added to the current list.\n/// When executed, the change operation will assign a new value to the given context variable\n/// using the specified expression. The change only applies within the parsing of a single instruction.\n/// Because we are in the middle of parsing, the \\b inst_next and \\b inst_next2 values have not \n/// been computed yet. So we check to make sure the value expression doesn't use this symbol.\n/// \\param vec is the current list of change operations\n/// \\param sym is the given context variable affected by the operation\n/// \\param pe is the specified expression\n/// \\return \\b true if the expression does not use the \\b inst_next or \\b inst_next2 symbol\nbool SleighCompile::contextMod(vector *vec,ContextSymbol *sym,PatternExpression *pe)\n\n{\n vector vallist;\n pe->listValues(vallist);\n for(uint4 i=0;i(vallist[i]) != (const EndInstructionValue *)0)\n return false;\n if (dynamic_cast(vallist[i]) != (const Next2InstructionValue *)0)\n return false;\n }\n // Otherwise we generate a \"temporary\" change to context instruction (ContextOp)\n ContextField *field = (ContextField *)sym->getPatternValue();\n ContextOp *op = new ContextOp(field->getStartBit(),field->getEndBit(),pe);\n vec->push_back(op);\n return true;\n}\n\n/// \\brief Create a change operation that makes a context variable change permanent\n///\n/// The new change operation is added to the current list.\n/// When executed, the operation makes the final value of the given context variable permanent,\n/// starting at the specified address symbol. This value is set for contexts starting at the\n/// specified symbol address and may flow to following addresses depending on the variable settings.\n/// \\param vec is the current list of change operations\n/// \\param sym is the specified address symbol\n/// \\param cvar is the given context variable\nvoid SleighCompile::contextSet(vector *vec,TripleSymbol *sym,\n\t\t\t\tContextSymbol *cvar)\n\n{\n ContextField *field = (ContextField *)cvar->getPatternValue();\n ContextCommit *op = new ContextCommit(sym,field->getStartBit(),field->getEndBit(),cvar->getFlow());\n vec->push_back(op);\n}\n\n/// \\brief Create a macro symbol (with parameter names)\n///\n/// An uninitialized symbol is defined and a macro table entry assigned.\n/// The body of the macro must be provided later with the buildMacro method.\n/// \\param name is the name of the macro\n/// \\param params is the list of parameter names for the macro\n/// \\return the new macro symbol\nMacroSymbol *SleighCompile::createMacro(string *name,vector *params)\n\n{\n curct = (Constructor *)0;\t// Not currently defining a Constructor\n curmacro = new MacroSymbol(*name,macrotable.size());\n delete name;\n addSymbol(curmacro);\n symtab.addScope();\t\t// New scope for the body of the macro definition\n pcode.resetLabelCount();\t// Macros have their own labels\n for(int4 i=0;isize();++i) {\n OperandSymbol *oper = new OperandSymbol((*params)[i],i,(Constructor *)0);\n addSymbol(oper);\n curmacro->addOperand(oper);\n }\n delete params;\n return curmacro;\n}\n\n/// \\brief Pass through operand properties of an invoked macro to the parent operands\n///\n/// Match up any qualities of the macro's OperandSymbols with any OperandSymbol passed\n/// into the macro.\n/// \\param sym is the macro being invoked\n/// \\param param is the list of expressions passed to the macro\nvoid SleighCompile::compareMacroParams(MacroSymbol *sym,const vector ¶m)\n\n{\n for(uint4 i=0;igetOut();\n if (outvn == (VarnodeTpl *)0) continue;\n // Check if an OperandSymbol was passed into this macro\n if (outvn->getOffset().getType() != ConstTpl::handle) continue;\n int4 hand = outvn->getOffset().getHandleIndex();\n\n // The matching operands\n OperandSymbol *macroop = sym->getOperand(i);\n OperandSymbol *parentop;\n if (curct == (Constructor *)0)\n parentop = curmacro->getOperand(hand);\n else\n parentop = curct->getOperand(hand);\n\n // This is the only property we check right now\n if (macroop->isCodeAddress())\n parentop->setCodeAddress();\n }\n}\n\n/// \\brief Create a p-code sequence that invokes a macro\n///\n/// The given parameter expressions are expanded first into the p-code sequence,\n/// followed by a final macro build directive.\n/// \\param sym is the macro being invoked\n/// \\param param is the sequence of parameter expressions passed to the macro\n/// \\return the p-code sequence\nvector *SleighCompile::createMacroUse(MacroSymbol *sym,vector *param)\n\n{\n if (sym->getNumOperands() != param->size()) {\n bool tooManyParams = param->size() > sym->getNumOperands();\n string errmsg = \"Invocation of macro '\" + sym->getName() + \"' passes too \" + (tooManyParams ? \"many\" : \"few\") + \" parameters\";\n reportError(getCurrentLocation(), errmsg);\n return new vector;\n }\n compareMacroParams(sym,*param);\n OpTpl *op = new OpTpl(MACROBUILD);\n VarnodeTpl *idvn = new VarnodeTpl(ConstTpl(getConstantSpace()),\n\t\t\t\t ConstTpl(ConstTpl::real,sym->getIndex()),\n\t\t\t\t ConstTpl(ConstTpl::real,4));\n op->addInput(idvn);\n return ExprTree::appendParams(op,param);\n}\n\n/// \\brief Create a SectionVector containing just the \\e main p-code section with no named sections\n///\n/// \\param main is the main p-code section\n/// \\return the new SectionVector\nSectionVector *SleighCompile::standaloneSection(ConstructTpl *main)\n\n{\n SectionVector *res = new SectionVector(main,symtab.getCurrentScope());\n return res;\n}\n\n/// \\brief Start a new named p-code section after the given \\e main p-code section\n///\n/// The \\b main p-code section must already be constructed, and the new named section\n/// symbol defined. A SectionVector is initialized with the \\e main section, and a\n/// symbol scope is created for the new p-code section.\n/// \\param main is the existing \\e main p-code section\n/// \\param sym is the existing symbol for the new named p-code section\n/// \\return the new SectionVector\nSectionVector *SleighCompile::firstNamedSection(ConstructTpl *main,SectionSymbol *sym)\n\n{\n sym->incrementDefineCount();\n SymbolScope *curscope = symtab.getCurrentScope(); // This should be a Constructor scope\n SymbolScope *parscope = curscope->getParent();\n if (parscope != symtab.getGlobalScope())\n throw LowlevelError(\"firstNamedSection called when not in Constructor scope\"); // Unrecoverable error\n symtab.addScope();\t\t// Add new scope under the Constructor scope\n SectionVector *res = new SectionVector(main,curscope);\n res->setNextIndex(sym->getTemplateId());\n return res;\n}\n\n/// \\brief Complete a named p-code section and prepare for a new named section\n///\n/// The actual p-code templates are assigned to a previously registered p-code section symbol\n/// and is added to the existing Section Vector. The old symbol scope is popped and another\n/// scope is created for the new named section.\n/// \\param vec is the existing SectionVector\n/// \\param section contains the p-code templates to assign to the previous section\n/// \\param sym is the symbol describing the new named section being parsed\n/// \\return the updated SectionVector\nSectionVector *SleighCompile::nextNamedSection(SectionVector *vec,ConstructTpl *section,SectionSymbol *sym)\n\n{\n sym->incrementDefineCount();\n SymbolScope *curscope = symtab.getCurrentScope();\n symtab.popScope();\t\t// Pop the scope of the last named section\n SymbolScope *parscope = symtab.getCurrentScope()->getParent();\n if (parscope != symtab.getGlobalScope())\n throw LowlevelError(\"nextNamedSection called when not in section scope\"); // Unrecoverable\n symtab.addScope();\t\t// Add new scope under the Constructor scope (not the last section scope)\n vec->append(section,curscope); // Associate finished section\n vec->setNextIndex(sym->getTemplateId()); // Set index for the NEXT section (not been fully parsed yet)\n return vec;\n}\n\n/// \\brief Fill-in final named section to match the previous SectionSymbol\n///\n/// The provided p-code templates are assigned to the previously registered p-code section symbol,\n/// and the completed section is added to the SectionVector.\n/// \\param vec is the existing SectionVector\n/// \\param section contains the p-code templates to assign to the last section\n/// \\return the updated SectionVector\nSectionVector *SleighCompile::finalNamedSection(SectionVector *vec,ConstructTpl *section)\n\n{\n vec->append(section,symtab.getCurrentScope());\n symtab.popScope();\t\t// Pop the section scope\n return vec;\n}\n\n/// \\brief Create the \\b crossbuild directive as a p-code template\n///\n/// \\param addr is the address symbol indicating the instruction to \\b crossbuild\n/// \\param sym is the symbol indicating the p-code to be build\n/// \\return the p-code template\nvector *SleighCompile::createCrossBuild(VarnodeTpl *addr,SectionSymbol *sym)\n\n{\n unique_allocatemask = 1;\n vector *res = new vector();\n VarnodeTpl *sectionid = new VarnodeTpl(ConstTpl(getConstantSpace()),\n ConstTpl(ConstTpl::real,sym->getTemplateId()),\n ConstTpl(ConstTpl::real,4));\n // This is simply a single pcodeop (template), where the opcode indicates the crossbuild directive\n OpTpl *op = new OpTpl( CROSSBUILD );\n op->addInput(addr);\t\t// The first input is the VarnodeTpl representing the address\n op->addInput(sectionid);\t// The second input is the indexed representing the named pcode section to build\n res->push_back(op);\n sym->incrementRefCount();\t// Keep track of the references to the section symbol\n return res;\n}\n\n/// \\brief Prepare for a new section of p-code templates\n///\n/// Create the ConstructTpl to hold the templates and reset counters.\n/// \\return the new ConstructTpl\nConstructTpl *SleighCompile::enterSection(void)\n\n{\n ConstructTpl *tpl = new ConstructTpl();\n pcode.resetLabelCount();\t// Macros have their own labels\n return tpl;\n}\n\n/// \\brief Create a new Constructor under the given subtable\n///\n/// Create the object and initialize parsing for the new definition\n/// \\param sym is the given subtable or null for the root table\n/// \\return the new Constructor\nConstructor *SleighCompile::createConstructor(SubtableSymbol *sym)\n\n{\n if (sym == (SubtableSymbol *)0)\n sym = WithBlock::getCurrentSubtable(withstack);\n if (sym == (SubtableSymbol *)0)\n sym = root;\n curmacro = (MacroSymbol *)0;\t// Not currently defining a macro\n curct = new Constructor(sym);\n curct->setLineno(lineno.back());\n ctorLocationMap[curct] = *getCurrentLocation();\n sym->addConstructor(curct);\n symtab.addScope();\t\t// Make a new symbol scope for our constructor\n pcode.resetLabelCount();\n int4 index = indexer.index(ctorLocationMap[curct].getFilename());\n curct->setSrcIndex(index);\n return curct;\n}\n\n/// \\brief Reset state after a parsing error in the previous Constructor\nvoid SleighCompile::resetConstructors(void)\n\n{\n symtab.setCurrentScope(symtab.getGlobalScope()); // Purge any dangling local scopes\n}\n\n/// Run through the section looking for MACRO directives. The directive includes an\n/// id for a specific macro in the table. Using the MacroBuilder class each directive\n/// is replaced with new sequence of OpTpls that tailors the macro with parameters\n/// in its invocation. Any errors encountered during expansion are reported.\n/// Other OpTpls in the section are unchanged.\n/// \\param ctpl is the given section of p-code to expand\n/// \\return \\b true if there were no errors expanding a macro\nbool SleighCompile::expandMacros(ConstructTpl *ctpl)\n\n{\n vector newvec;\n vector::const_iterator iter;\n OpTpl *op;\n \n for(iter=ctpl->getOpvec().begin();iter!=ctpl->getOpvec().end();++iter) {\n op = *iter;\n if (op->getOpcode() == MACROBUILD) {\n MacroBuilder builder(this,newvec,ctpl->numLabels());\n int4 index = op->getIn(0)->getOffset().getReal();\n if (index >= macrotable.size())\n\treturn false;\n builder.setMacroOp(op);\n ConstructTpl *macro_tpl = macrotable[index];\n builder.build(macro_tpl,-1);\n ctpl->setNumLabels( ctpl->numLabels() + macro_tpl->numLabels() );\n delete op;\t\t// Throw away the place holder op\n if (builder.hasError())\n\treturn false;\n }\n else\n newvec.push_back(op);\n }\n ctpl->setOpvec(newvec);\n return true;\n}\n\n/// For each p-code section of the given Constructor:\n/// - Expand macros\n/// - Check that labels are both defined and referenced\n/// - Generate BUILD directives for subtable operands\n/// - Propagate Varnode sizes throughout the section\n///\n/// Each action may generate errors or warnings.\n/// \\param big is the given Constructor\n/// \\param vec is the list of p-code sections\n/// \\return \\b true if there were no fatal errors\nbool SleighCompile::finalizeSections(Constructor *big,SectionVector *vec)\n\n{\n vector errors;\n\n RtlPair cur = vec->getMainPair();\n int4 i=-1;\n string sectionstring = \" Main section: \";\n int4 max = vec->getMaxId();\n for(;;) {\n string errstring;\n\n errstring = checkSymbols(cur.scope); // Check labels in the section's scope\n if (errstring.size()!=0) {\n errors.push_back(sectionstring + errstring);\n }\n else {\n if (!expandMacros(cur.section))\n\terrors.push_back(sectionstring + \"Could not expand macros\");\n vector check;\n big->markSubtableOperands(check);\n int4 res = cur.section->fillinBuild(check,getConstantSpace());\n if (res == 1)\n\terrors.push_back(sectionstring + \"Duplicate BUILD statements\");\n if (res == 2)\n\terrors.push_back(sectionstring + \"Unnecessary BUILD statements\");\n \n if (!PcodeCompile::propagateSize(cur.section))\n\terrors.push_back(sectionstring + \"Could not resolve at least 1 variable size\");\n }\n if (i < 0) {\t\t// These potential errors only apply to main section\n if (cur.section->getResult() != (HandleTpl *)0) {\t// If there is an export statement\n\tif (big->getParent()==root)\n\t errors.push_back(\" Cannot have export statement in root constructor\");\n\telse if (!forceExportSize(cur.section))\n\t errors.push_back(\" Size of export is unknown\");\n }\n }\n if (cur.section->delaySlot() != 0) { // Delay slot is present in this constructor\n if (root != big->getParent()) { // it is not in a root constructor\n\tostringstream msg;\n\tmsg << \"Delay slot used in non-root constructor \";\n\tbig->printInfo(msg);\n\tmsg << endl;\n\treportWarning(getLocation(big), msg.str());\n }\n if (cur.section->delaySlot() > maxdelayslotbytes)\t// Keep track of maximum delayslot parameter\n\tmaxdelayslotbytes = cur.section->delaySlot();\n }\n do {\n i += 1;\n if (i >= max) break;\n cur = vec->getNamedPair(i);\n } while(cur.section == (ConstructTpl *)0);\n \n if (i >= max) break;\n SectionSymbol *sym = sections[i];\n sectionstring = \" \" + sym->getName() + \" section: \";\n }\n if (!errors.empty()) {\n ostringstream s;\n s << \"in \";\n big->printInfo(s);\n reportError(getLocation(big), s.str());\n for(int4 j=0;j &ops(ct->getOpvec());\n VarnodeTpl *vn;\n OpTpl *op;\n\n for(int4 i=0;igetOut();\n if ((vn!=(VarnodeTpl *)0)&&(vn->isLocalTemp())) {\n if (vn->getOffset() == offset)\n\treturn vn;\n }\n for(int4 j=0;jnumInput();++j) {\n vn = op->getIn(j);\n if (vn->isLocalTemp()&&(vn->getOffset()==offset))\n\treturn vn;\n }\n }\n return (VarnodeTpl *)0;\n}\n\n/// \\brief Propagate local variable sizes into an \\b export statement\n///\n/// Look for zero size temporary Varnodes in \\b export statements, search for\n/// the matching local Varnode symbol and force its size on the \\b export.\n/// \\param ct is the Constructor whose \\b export is to be modified\n/// \\return \\b false if a local zero size can't be updated\nbool SleighCompile::forceExportSize(ConstructTpl *ct)\n\n{\n HandleTpl *result = ct->getResult();\n if (result == (HandleTpl *)0) return true;\n\n VarnodeTpl *vt;\n\n if (result->getPtrSpace().isUniqueSpace()&&result->getPtrSize().isZero()) {\n vt = findSize(result->getPtrOffset(),ct);\n if (vt == (VarnodeTpl *)0) return false;\n result->setPtrSize(vt->getSize());\n }\n else if (result->getSpace().isUniqueSpace()&&result->getSize().isZero()) {\n vt = findSize(result->getPtrOffset(),ct);\n if (vt == (VarnodeTpl *)0) return false;\n result->setSize(vt->getSize());\n }\n return true;\n}\n\n/// \\brief Insert a region of zero bits into an address offset\n///\n/// \\param addr is the address offset\n/// \\return the modified offset\nuintb SleighCompile::insertCrossBuildRegion(uintb addr)\n\n{\n uintb upperbits = (addr >> UNIQUE_CROSSBUILD_POSITION) << (UNIQUE_CROSSBUILD_POSITION + UNIQUE_CROSSBUILD_NUMBITS);\n uintb lowerbits = (addr << (8*sizeof(uintb) - UNIQUE_CROSSBUILD_POSITION)) >> (8*sizeof(uintb) - UNIQUE_CROSSBUILD_POSITION);\n return upperbits | lowerbits;\n}\n\n/// \\brief If the given Varnode is in the \\e unique space, insert a region of zero bits\n///\n/// \\param vn is the given Varnode\nvoid SleighCompile::shiftUniqueVn(VarnodeTpl *vn)\n\n{\n if (vn->getSpace().isUniqueSpace() && (vn->getOffset().getType() == ConstTpl::real)) {\n uintb val = insertCrossBuildRegion(vn->getOffset().getReal());\n vn->setOffset(val);\n }\n}\n\n/// \\brief Insert a region of zero bits for any Varnode used by the given op in the \\e unique space\n///\n/// \\param op is the given op\nvoid SleighCompile::shiftUniqueOp(OpTpl *op)\n\n{\n VarnodeTpl *outvn = op->getOut();\n if (outvn != (VarnodeTpl *)0)\n shiftUniqueVn(outvn);\n for(int4 i=0;inumInput();++i)\n shiftUniqueVn(op->getIn(i));\n}\n\n/// \\brief Insert a region of zero bits for both \\e dynamic or \\e static Varnode aspects in the \\e unique space\n///\n/// \\param hand is a handle template whose aspects should be modified\nvoid SleighCompile::shiftUniqueHandle(HandleTpl *hand)\n\n{\n if (hand->getSpace().isUniqueSpace() && (hand->getPtrSpace().getType() == ConstTpl::real)\n && (hand->getPtrOffset().getType() == ConstTpl::real)) {\n uintb val = insertCrossBuildRegion(hand->getPtrOffset().getReal());\n hand->setPtrOffset(val);\n }\n else if (hand->getPtrSpace().isUniqueSpace() && (hand->getPtrOffset().getType() == ConstTpl::real)) {\n uintb val = insertCrossBuildRegion(hand->getPtrOffset().getReal());\n hand->setPtrOffset(val);\n }\n \n if (hand->getTempSpace().isUniqueSpace() && (hand->getTempOffset().getType() == ConstTpl::real)) {\n uintb val = insertCrossBuildRegion(hand->getTempOffset().getReal());\n hand->setTempOffset(val);\n }\n}\n\n/// \\brief Insert a region of zero bits for any Varnode in the \\e unique space for all p-code in the given section\n///\n/// \\param tpl is the given p-code section\nvoid SleighCompile::shiftUniqueConstruct(ConstructTpl *tpl)\n\n{\n HandleTpl *result = tpl->getResult();\n if (result != (HandleTpl *)0)\n shiftUniqueHandle(result);\n const vector &vec( tpl->getOpvec() );\n for(int4 i=0;igetNumConstructors();\n for(int4 j=0;jgetConstructor(j);\n ConstructTpl *tpl = ct->getTempl();\n if (tpl != (ConstructTpl *)0)\n\tshiftUniqueConstruct(tpl);\n for(int4 k=0;kgetNamedTempl(k);\n\tif (namedtpl != (ConstructTpl *)0)\n\t shiftUniqueConstruct(namedtpl);\n }\n }\n i+=1;\n if (i>=tables.size()) break;\n sym = tables[i];\n }\n uint4 ubase = getUniqueBase(); // We have to adjust the unique base\n ubase += 1 << UNIQUE_CROSSBUILD_POSITION;\n ubase <<= UNIQUE_CROSSBUILD_NUMBITS;\n setUniqueBase(ubase);\n}\n\n/// \\brief Add a new \\b with block to the current stack\n///\n/// All subsequent Constructors adopt properties declared in the \\b with header.\n/// \\param ss the subtable to assign to each Constructor, or null\n/// \\param pateq is an pattern equation constraining each Constructor, or null\n/// \\param contvec is a context change applied to each Constructor, or null\nvoid SleighCompile::pushWith(SubtableSymbol *ss,PatternEquation *pateq,vector *contvec)\n\n{\n withstack.emplace_back();\n withstack.back().set(ss,pateq,contvec);\n}\n\n/// \\brief Pop the current \\b with block from the stack\nvoid SleighCompile::popWith(void)\n\n{\n withstack.pop_back();\n}\n\n/// \\brief Finish building a given Constructor after all its pieces have been parsed\n///\n/// The constraint pattern and context changes are modified by the current \\b with block.\n/// The result along with any p-code sections are registered with the Constructor object.\n/// \\param big is the given Constructor\n/// \\param pateq is the parsed pattern equation\n/// \\param contvec is the list of context changes or null\n/// \\param vec is the collection of p-code sections, or null\nvoid SleighCompile::buildConstructor(Constructor *big,PatternEquation *pateq,vector *contvec,SectionVector *vec)\n\n{\n bool noerrors = true;\n if (vec != (SectionVector *)0) { // If the sections were implemented\n noerrors = finalizeSections(big,vec);\n if (noerrors) {\t\t// Attach the sections to the Constructor\n big->setMainSection(vec->getMainSection());\n int4 max = vec->getMaxId();\n for(int4 i=0;igetNamedSection(i);\n\tif (section != (ConstructTpl *)0)\n\t big->setNamedSection(section,i);\n }\n }\n delete vec;\n }\n if (noerrors) {\n pateq = WithBlock::collectAndPrependPattern(withstack, pateq);\n contvec = WithBlock::collectAndPrependContext(withstack, contvec);\n big->addEquation(pateq);\n big->removeTrailingSpace();\n if (contvec != (vector *)0) {\n big->addContext(*contvec);\n delete contvec;\n }\n }\n symtab.popScope();\t\t// In all cases pop scope\n}\n\n/// \\brief Finish defining a macro given a set of p-code templates for its body\n///\n/// Try to propagate sizes through the templates, expand any (sub)macros and make\n/// sure any label symbols are defined and used.\n/// \\param sym is the macro being defined\n/// \\param rtl is the set of p-code templates\nvoid SleighCompile::buildMacro(MacroSymbol *sym,ConstructTpl *rtl)\n\n{\n string errstring = checkSymbols(symtab.getCurrentScope());\n if (errstring.size() != 0) {\n reportError(getCurrentLocation(), \"In definition of macro '\"+sym->getName() + \"': \" + errstring);\n return;\n }\n if (!expandMacros(rtl)) {\n reportError(getCurrentLocation(), \"Could not expand submacro in definition of macro '\" + sym->getName() + \"'\");\n return;\n }\n PcodeCompile::propagateSize(rtl); // Propagate size information (as much as possible)\n sym->setConstruct(rtl);\n symtab.popScope();\t\t// Pop local variables used to define macro\n macrotable.push_back(rtl);\n}\n\n/// \\brief Record a NOP constructor at the current location\n///\n/// The location is recorded and may be reported on after parsing.\nvoid SleighCompile::recordNop(void)\n\n{\n string msg = formatStatusMessage(getCurrentLocation(), \"NOP detected\");\n\n noplist.push_back(msg);\n}\n\n/// \\brief Run the full compilation process, given a path to the specification file\n///\n/// The specification file is opened and a parse is started. Errors and warnings\n/// are printed to standard out, and if no fatal errors are encountered, the compiled\n/// form of the specification is written out.\n/// \\param filein is the given path to the specification file to compile\n/// \\param fileout is the path to output file\n/// \\return an error code, where 0 indicates that a compiled file was successfully produced\nint4 SleighCompile::run_compilation(const string &filein,const string &fileout)\n\n{\n parseFromNewFile(filein);\n slgh = this;\t\t// Set global pointer up for parser\n sleighin = fopen(filein.c_str(),\"r\");\t// Open the file for the lexer\n if (sleighin == (FILE *)0) {\n cerr << \"Unable to open specfile: \" << filein << endl;\n return 2;\n }\n\n try {\n int4 parseres = sleighparse();\t// Try to parse\n fclose(sleighin);\n if (parseres==0)\n process();\t// Do all the post-processing\n if ((parseres==0)&&(numErrors()==0)) { // If no errors\n ofstream s(fileout,ios::binary);\n if (!s) {\n\tostringstream errs;\n\terrs << \"Unable to open output file: \" << fileout;\n\tthrow SleighError(errs.str());\n }\n if (debugoutput) {\n\t// If the debug output format was requested, use the XML encoder\n\tXmlEncode encoder(s);\n\tencode(encoder);\n }\n else {\n\t// Use the standard .sla format encoder\n\tsla::FormatEncode encoder(s,-1);\n\tencode(encoder);\n\tencoder.flush();\n }\n s.close();\n }\n else {\n cerr << \"No output produced\" <getRoot();\n for(;;) {\n const List &list(el->getChildren());\n List::const_iterator iter;\n for(iter=list.begin();iter!=list.end();++iter) {\n el = *iter;\n if (el->getName() == \"processorfile\") {\n\tspecfileout = el->getContent();\n\tint4 num = el->getNumAttributes();\n\tfor(int4 i=0;igetAttributeName(i)==\"slaspec\")\n\t specfilein = el->getAttributeValue(i);\n\t else {\n\t compiler.setPreprocValue(el->getAttributeName(i),el->getAttributeValue(i));\n\t }\n\t}\n }\n else if (el->getName() == \"language_spec\")\n\tbreak;\n else if (el->getName() == \"language_description\")\n\tbreak;\n }\n if (iter==list.end()) break;\n }\n delete doc;\n\n if (specfilein.size() == 0) {\n cerr << \"Input slaspec file was not specified in \" << filein << endl;\n exit(1);\n }\n if (specfileout.size() == 0) {\n cerr << \"Output sla file was not specified in \" << filein << endl;\n exit(1);\n }\n return compiler.run_compilation(specfilein,specfileout);\n}\n\nstatic void findSlaSpecs(vector &res, const string &dir, const string &suffix)\n\n{\n FileManage::matchListDir(res, suffix, true, dir, false);\n \n vector dirs;\n FileManage::directoryList(dirs, dir);\n vector::const_iterator iter;\n for(iter = dirs.begin();iter!=dirs.end();++iter) {\n const string &nextdir( *iter );\n findSlaSpecs(res, nextdir,suffix);\n }\n}\n\n/// \\brief Set all compiler options at the same time\n///\n/// \\param defines is map of \\e variable to \\e value that is passed to the preprocessor\n/// \\param unnecessaryPcodeWarning is \\b true for individual warnings about unnecessary p-code ops\n/// \\param lenientConflict is \\b false to report indistinguishable patterns as errors\n/// \\param allCollisionWarning is \\b true for individual warnings about constructors with colliding operands\n/// \\param allNopWarning is \\b true for individual warnings about NOP constructors\n/// \\param deadTempWarning is \\b true for individual warnings about dead temporary varnodes\n/// \\param enforceLocalKeyWord is \\b true to force all local variable definitions to use the \\b local keyword\n/// \\param caseSensitiveRegisterNames is \\b true if register names are allowed to be case sensitive\n/// \\param debugOutput is \\b true if the output file is written using the debug (XML) form of the .sla format\nvoid SleighCompile::setAllOptions(const map &defines, bool unnecessaryPcodeWarning,\n\t\t\t\t bool lenientConflict, bool allCollisionWarning,\n\t\t\t\t bool allNopWarning,bool deadTempWarning,bool enforceLocalKeyWord,\n\t\t\t\t bool caseSensitiveRegisterNames,bool debugOutput)\n{\n map::const_iterator iter = defines.begin();\n for (iter = defines.begin(); iter != defines.end(); iter++) {\n setPreprocValue((*iter).first, (*iter).second);\n }\n setUnnecessaryPcodeWarning(unnecessaryPcodeWarning);\n setLenientConflict(lenientConflict);\n setLocalCollisionWarning( allCollisionWarning );\n setAllNopWarning( allNopWarning );\n setDeadTempWarning(deadTempWarning);\n setEnforceLocalKeyWord(enforceLocalKeyWord);\n setInsensitiveDuplicateError(!caseSensitiveRegisterNames);\n setDebugOutput(debugOutput);\n}\n\nstatic void segvHandler(int sig) {\n exit(1);\t\t\t// Just die - prevents OS from popping-up a dialog\n}\n\n} // End namespace ghidra\n\nint main(int argc,char **argv)\n\n{\n using namespace ghidra;\n\n int4 retval = 0;\n\n signal(SIGSEGV, &segvHandler); // Exit on SEGV errors\n\n#ifdef YYDEBUG\n sleighdebug = 0;\n#endif\n\n if (argc < 2) {\n cerr << \"USAGE: sleigh [-x] [-dNAME=VALUE] inputfile [outputfile]\" << endl;\n cerr << \" -a scan for all slaspec files recursively where inputfile is a directory\" << endl;\n cerr << \" -x turns on parser debugging\" << endl;\n cerr << \" -y write .sla using XML debug format\" << endl;\n cerr << \" -u print warnings for unnecessary pcode instructions\" << endl;\n cerr << \" -l report pattern conflicts\" << endl;\n cerr << \" -n print warnings for all NOP constructors\" << endl;\n cerr << \" -t print warnings for dead temporaries\" << endl;\n cerr << \" -e enforce use of 'local' keyword for temporaries\" << endl;\n cerr << \" -c print warnings for all constructors with colliding operands\" << endl;\n cerr << \" -s treat register names as case sensitive\" << endl;\n cerr << \" -DNAME=VALUE defines a preprocessor macro NAME with value VALUE\" << endl;\n exit(2);\n }\n\n const string SLAEXT(\".sla\");\t// Default sla extension\n const string SLASPECEXT(\".slaspec\");\n map defines;\n bool unnecessaryPcodeWarning = false;\n bool lenientConflict = true;\n bool allCollisionWarning = false;\n bool allNopWarning = false;\n bool deadTempWarning = false;\n bool enforceLocalKeyWord = false;\n bool caseSensitiveRegisterNames = false;\n bool debugOutput = false;\n \n bool compileAll = false;\n \n int4 i;\n for(i=1;i slaspecs;\n string dirStr = \".\";\n if (i != argc)\n dirStr = argv[i];\n findSlaSpecs(slaspecs, dirStr,SLASPECEXT);\n cout << \"Compiling \" << dec << slaspecs.size() << \" slaspec files in \" << dirStr << endl;\n for(int4 j=0;j \"sleigh file.slaspec file.sla\"\n\tstring fileoutSTR = fileinPreExt;\n\tfileoutSTR.append(SLAEXT);\n\tretval = compiler.run_compilation(fileinExamine,fileoutSTR);\n }else{\n\tretval = run_xml(fileinExamine,compiler);\n }\n \n }\n }\n return retval;\n}\n" }, { "path": "pypcode/sleigh/slgh_compile.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file slgh_compile.hh\n/// \\brief High-level control of the sleigh compilation process\n#ifndef __SLGH_COMPILE_HH__\n#define __SLGH_COMPILE_HH__\n\n#include \"sleighbase.hh\"\n#include \"pcodecompile.hh\"\n#include \"filemanage.hh\"\n#include \n#include \n#include \n\nnamespace ghidra {\n\nusing std::cout;\nusing std::cerr;\nusing std::out_of_range;\nusing std::string;\n\n/// \\brief A helper class to associate a \\e named Constructor section with its symbol scope\n///\n/// A Constructor can contain multiple named sections of p-code. There is a \\e main\n/// section associated with the constructor, but other sections are possible and can\n/// be accessed through the \\b crossbuild directive, which allows their operations to be\n/// incorporated into nearby instructions. During parsing of a SLEIGH file, \\b this class\n/// associates a named section with its dedicated symbol scope.\nstruct RtlPair {\n ConstructTpl *section;\t///< A named p-code section\n SymbolScope *scope;\t\t///< Symbol scope associated with the section\n RtlPair(void) { section = (ConstructTpl *)0; scope = (SymbolScope *)0; }\t///< Construct on empty pair\n RtlPair(ConstructTpl *sec,SymbolScope *sc) { section = sec; scope = sc; }\t///< Constructor\n};\n\n/// \\brief A collection of \\e named p-code sections for a single Constructor\n///\n/// A Constructor always has a \\b main section of p-code (which may be empty).\n/// Alternately a Constructor may define additional \\e named sections of p-code.\n/// Operations in these sections are emitted using the \\b crossbuild directive and\n/// can be incorporated into following instructions.\n///\n/// Internally different sections (RtlPair) are identified by index. A\n/// SectionSymbol holds the section's name and its corresponding index.\nclass SectionVector {\n int4 nextindex;\t\t///< Index of the section currently being parsed.\n RtlPair main;\t\t\t///< The main section\n vector named;\t///< Named sections accessed by index\npublic:\n SectionVector(ConstructTpl *rtl,SymbolScope *scope);\t\t\t\t\t///< Constructor\n ConstructTpl *getMainSection(void) const { return main.section; }\t\t\t///< Get the \\e main section\n ConstructTpl *getNamedSection(int4 index) const { return named[index].section; }\t///< Get a \\e named section by index\n RtlPair getMainPair(void) const { return main; }\t\t\t\t\t///< Get the \\e main section/namespace pair\n RtlPair getNamedPair(int4 i) const { return named[i]; }\t\t///< Get a \\e named section/namespace pair by index\n void setNextIndex(int4 i) { nextindex = i; }\t\t\t\t///< Set the index of the currently parsing \\e named section\n int4 getMaxId(void) const { return named.size(); }\t\t\t///< Get the maximum (exclusive) named section index\n void append(ConstructTpl *rtl,SymbolScope *scope);\t\t\t///< Add a new \\e named section\n};\n\n/// \\brief Qualities associated (via parsing) with an address space\n///\n/// An object of this class accumulates properties of an address space as they\n/// are parsed in the \\b define statement prior to formally allocating the AddrSpace object.\nstruct SpaceQuality {\n /// \\brief The type of space being defined\n enum {\n ramtype,\t\t///< An address space representing normal, indexed, memory\n registertype\t///< An address space containing registers\n };\n string name;\t\t///< Name of the address space\n uint4 type;\t\t///< Type of address space, \\e ramtype or \\e registertype\n uint4 size;\t\t///< Number of bytes required to index all bytes of the space\n uint4 wordsize; ///< Number of bytes in an addressable unit of the space\n bool isdefault;\t///< \\b true if the new address space will be the default\n SpaceQuality(const string &nm);\t///< Constructor\n};\n\n/// \\brief Qualities associated (via parsing) with a token or context \\b field\n///\n/// An object of this class accumulates properties of a field as they\n/// are parsed in of a \\b define \\b token block prior to formally allocating the\n/// TokenField or FieldContext object.\nstruct FieldQuality {\n string name;\t\t///< Name of the field\n uint4 low;\t\t///< The least significant bit of the field within the token\n uint4 high;\t\t///< The most significant bit of the field within the token\n bool signext;\t\t///< \\b true if the field's value is signed\n bool flow;\t\t///< \\b true if the context \\b flows for this field.\n bool hex;\t\t///< \\b true if the field value is displayed in hex\n FieldQuality(string *nm,uintb *l,uintb *h);\t///< Constructor\n};\n\n/// \\brief Subtable, pattern, and context information applied across a \\b with block\n///\n/// The header of a \\b with block is applied to all constructors in the block. It\n/// attaches each constructor to a specific subtable. A pattern expression and/or a\n/// a series of context changes is attached to each constructor as well.\nclass WithBlock {\n SubtableSymbol *ss;\t\t\t///< Subtable containing each Constructor (or null for root table)\n PatternEquation *pateq;\t\t///< Pattern to prepend to each Constructor (or null)\n vector contvec;\t///< Context change to associate with each constructor (or null)\npublic:\n WithBlock(void) { pateq = (PatternEquation *)0; }\t///< Constructor\n void set(SubtableSymbol *s, PatternEquation *pq, vector *cvec);\t///< Set components of the header\n ~WithBlock(void);\t///< Destructor\n static PatternEquation *collectAndPrependPattern(const list &stack, PatternEquation *pateq);\n static vector *collectAndPrependContext(const list &stack, vector *contvec);\n static SubtableSymbol *getCurrentSubtable(const list &stack);\n};\n\nclass SleighCompile;\n\n/// \\brief Derive Varnode sizes and optimize p-code in SLEIGH Constructors\n///\n/// This class examines p-code parsed from a SLEIGH file and performs three main tasks:\n/// - Enforcing size rules in Constructor p-code,\n/// - Optimizing p-code within a Constructor, and\n/// - Searching for other p-code validity violations\n///\n/// Many p-code operators require that their input and/or output operands are all the same size\n/// or have other specific size restrictions on their operands. This class enforces those requirements.\n///\n/// This class performs limited optimization of p-code within a Constructor by performing COPY\n/// propagation through \\e temporary registers.\n///\n/// This class searches for unnecessary truncations and extensions, temporary varnodes that are either dead,\n/// read before written, or that exceed the standard allocation size.\nclass ConsistencyChecker {\npublic:\n /// \\brief Description of how a temporary register is being used within a Constructor\n ///\n /// This counts reads and writes of the register. If the register is read only once, the\n /// particular p-code op and input slot reading it is recorded. If the register is written\n /// only once, the particular p-code op writing it is recorded.\n struct OptimizeRecord {\n uintb offset; ///< Offset of the varnode address\n int4 size; ///< Size in bytes of the varnode or piece (immutable)\n int4 writeop; ///< Index of the (last) p-code op writing to register (or -1)\n int4 readop; ///< Index of the (last) p-code op reading the register (or -1)\n int4 inslot; ///< Input slot of p-code op reading the register (or -1)\n int4 writecount; ///< Number of times the register is written\n int4 readcount;\t\t ///< Number of times the register is read\n int4 writesection; ///< Section containing (last) p-code op writing to the register (or -2)\n int4 readsection; ///< Section containing (last) p-code op reading the register (or -2)\n mutable int4 opttype; ///< 0 = register read by a COPY, 1 = register written by a COPY (-1 otherwise)\n\n /// \\brief Construct a record, initializing counts\n OptimizeRecord(uintb offset, int4 size) {\n this->offset = offset;\n this->size = size;\n writeop = -1; readop = -1; inslot=-1; writecount=0; readcount=0; writesection=-2; readsection=-2; opttype=-1;\n }\n void copyFromExcludingSize(OptimizeRecord &that);\n void update(int4 opIdx, int4 slotIdx, int4 secNum);\n void updateRead(int4 i, int4 inslot, int4 secNum);\n void updateWrite(int4 i, int4 secNum);\n void updateExport();\n void updateCombine(OptimizeRecord &that);\n };\nprivate:\n class UniqueState {\n map recs;\n static uintb endOf(map::iterator &iter) { return iter->first + iter->second.size; }\n OptimizeRecord coalesce(vector &records);\n map::iterator lesserIter(uintb offset);\n public:\n void clear(void) { recs.clear(); }\n void set(uintb offset, int4 size, OptimizeRecord &rec);\n void getDefinitions(vector &result, uintb offset, int4 size);\n map::const_iterator begin(void) const { return recs.begin(); }\n map::const_iterator end(void) const { return recs.end(); }\n };\n\n SleighCompile *compiler;\t///< Parsed form of the SLEIGH file being examined\n int4 unnecessarypcode;\t///< Count of unnecessary extension/truncation operations\n int4 readnowrite;\t\t///< Count of temporary registers that are read but not written\n int4 writenoread;\t\t///< Count of temporary registers that are written but not read\n bool printextwarning;\t\t///< Set to \\b true if warning emitted for each unnecessary truncation/extension\n bool printdeadwarning;\t///< Set to \\b true if warning emitted for each written but not read temporary\n SubtableSymbol *root_symbol;\t///< The root symbol table for the parsed SLEIGH file\n vector postorder;\t///< Subtables sorted into \\e post order (dependent tables listed earlier)\n map sizemap;\t///< Sizes associated with table \\e exports\n OperandSymbol *getOperandSymbol(int4 slot,OpTpl *op,Constructor *ct);\n void printOpName(ostream &s,OpTpl *op);\n void printOpError(OpTpl *op,Constructor *ct,int4 err1,int4 err2,const string &message);\n int4 recoverSize(const ConstTpl &sizeconst,Constructor *ct);\n bool checkOpMisuse(OpTpl *op,Constructor *ct);\n bool sizeRestriction(OpTpl *op,Constructor *ct);\n bool checkConstructorSection(Constructor *ct,ConstructTpl *cttpl);\n bool hasLargeTemporary(OpTpl *op);\n bool isTemporaryAndTooBig(VarnodeTpl *vn);\n bool checkVarnodeTruncation(Constructor *ct,int4 slot,OpTpl *op,VarnodeTpl *vn,bool isbigendian);\n bool checkSectionTruncations(Constructor *ct,ConstructTpl *cttpl,bool isbigendian);\n bool checkSubtable(SubtableSymbol *sym);\n void dealWithUnnecessaryExt(OpTpl *op,Constructor *ct);\n void dealWithUnnecessaryTrunc(OpTpl *op,Constructor *ct);\n void setPostOrder(SubtableSymbol *root);\n\n // Optimization routines\n static void examineVn(UniqueState &state,const VarnodeTpl *vn,uint4 i,int4 inslot,int4 secnum);\n static bool possibleIntersection(const VarnodeTpl *vn1,const VarnodeTpl *vn2);\n bool readWriteInterference(const VarnodeTpl *vn,const OpTpl *op,bool checkread) const;\n void optimizeGather1(Constructor *ct,UniqueState &state,int4 secnum) const;\n void optimizeGather2(Constructor *ct,UniqueState &state,int4 secnum) const;\n const OptimizeRecord *findValidRule(Constructor *ct,const UniqueState &state) const;\n void applyOptimization(Constructor *ct,const OptimizeRecord &rec);\n void checkUnusedTemps(Constructor *ct,const UniqueState &state);\n void checkLargeTemporaries(Constructor *ct,ConstructTpl *ctpl);\n void optimize(Constructor *ct);\npublic:\n ConsistencyChecker(SleighCompile *sleigh, SubtableSymbol *rt,bool unnecessary,bool warndead);\n bool testSizeRestrictions(void);\t\t///< Test size consistency of all p-code\n bool testTruncations(void);\t\t\t///< Test truncation validity of all p-code\n void testLargeTemporary(void);\t\t///< Test for temporary Varnodes that are too large\n void optimizeAll(void);\t\t\t///< Do COPY propagation optimization on all p-code\n int4 getNumUnnecessaryPcode(void) const { return unnecessarypcode; }\t///< Return the number of unnecessary extensions and truncations\n int4 getNumReadNoWrite(void) const { return readnowrite; }\t///< Return the number of temporaries read but not written\n int4 getNumWriteNoRead(void) const { return writenoread; }\t///< Return the number of temporaries written but not read\n};\n\n/// \\brief Helper function holding properties of a \\e context field prior to calculating the context layout\n///\n/// This holds the concrete Varnode reprensenting the context field's physical storage and the\n/// properties of the field itself, prior to the final ContextField being allocated.\nstruct FieldContext {\n VarnodeSymbol *sym;\t\t///< The concrete Varnode representing physical storage for the field\n FieldQuality *qual;\t\t///< Qualities of the field, as parsed\n bool operator<(const FieldContext &op2) const;\t///< Sort context fields based on their least significant bit boundary\n FieldContext(VarnodeSymbol *s,FieldQuality *q) { sym=s; qual=q; }\t///< Constructor\n};\n\n/// \\brief A class for expanding macro directives within a p-code section\n///\n/// It is handed a (partial) list of p-code op templates (OpTpl). The\n/// macro directive is established with the setMacroOp() method. Then calling\n/// build() expands the macro into the list of OpTpls, providing parameter\n/// substitution. The class is derived from PcodeBuilder, where the dump() method,\n/// instead of emitting raw p-code, clones the macro templates into the list\n/// of OpTpls.\nclass MacroBuilder : public PcodeBuilder {\n SleighCompile *slgh;\t\t///< The SLEIGH parsing object\n bool haserror;\t\t///< Set to \\b true by the build() method if there was an error\n vector &outvec;\t///< The partial list of op templates to expand the macro into\n vector params;\t///< List of parameters to substitute into the macro\n bool transferOp(OpTpl *op,vector ¶ms);\n virtual void dump( OpTpl *op );\n void free(void);\t\t\t\t\t\t///< Free resources used by the builder\n void reportError(const Location* loc, const string &val);\t///< Report error encountered expanding the macro\npublic:\n MacroBuilder(SleighCompile *sl,vector &ovec,uint4 lbcnt) : PcodeBuilder(lbcnt),outvec(ovec) {\n slgh = sl; haserror = false; }\t\t\t\t\t///< Constructor\n void setMacroOp(OpTpl *macroop);\t\t\t\t\t///< Establish the MACRO directive to expand\n bool hasError(void) const { return haserror; }\t\t\t///< Return \\b true if there were errors during expansion\n virtual ~MacroBuilder(void) { free(); }\n virtual void appendBuild(OpTpl *bld,int4 secnum) { dump(bld); }\n virtual void delaySlot(OpTpl *op) { dump(op); }\n virtual void setLabel(OpTpl *op);\n virtual void appendCrossBuild(OpTpl *bld,int4 secnum) { dump(bld); }\n};\n\n/// \\brief Parsing for the semantic section of Constructors\n///\n/// This is just the base p-code compiler for building OpTpl and VarnodeTpl.\n/// Symbols, locations, and error/warning messages are tied into to the main\n/// parser.\nclass SleighPcode : public PcodeCompile {\n SleighCompile *compiler;\t\t\t///< The main SLEIGH parser\n virtual uint4 allocateTemp(void);\n virtual const Location *getLocation(SleighSymbol *sym) const;\n virtual void reportError(const Location* loc, const string &msg);\n virtual void reportWarning(const Location* loc, const string &msg);\n virtual void addSymbol(SleighSymbol *sym);\npublic:\n SleighPcode(void) : PcodeCompile() { compiler = (SleighCompile *)0; }\t///< Constructor\n void setCompiler(SleighCompile *comp) { compiler = comp; }\t\t///< Hook in the main parser\n};\n\n/// \\brief SLEIGH specification compiling\n///\n/// Class for parsing SLEIGH specifications (.slaspec files) and producing the\n/// \\e compiled form (.sla file), which can then be loaded by a SLEIGH disassembly\n/// and p-code generation engine. This full parser contains the p-code parser SleighPcode\n/// within it. The main entry point is run_compilation(), which takes the input and output\n/// file paths as parameters. Various options and preprocessor macros can be set using the\n/// various set*() methods prior to calling run_compilation.\nclass SleighCompile : public SleighBase {\n friend class SleighPcode;\n static const int4 UNIQUE_CROSSBUILD_POSITION = 8;\n static const int4 UNIQUE_CROSSBUILD_NUMBITS = 8;\npublic:\n SleighPcode pcode;\t\t\t///< The p-code parsing (sub)engine\nprivate:\n map preproc_defines;\t///< Defines for the preprocessor\n vector contexttable;\t///< Context field definitions (prior to defining ContextField and ContextSymbol)\n vector macrotable;\t///< SLEIGH macro definitions\n vector tokentable;\t\t///< SLEIGH token definitions\n vector tables;\t///< SLEIGH subtables\n vector sections;\t///< Symbols defining Constructor sections\n list withstack;\t\t///< Current stack of \\b with blocks\n Constructor *curct;\t\t\t///< Current Constructor being defined\n MacroSymbol *curmacro;\t\t///< Current macro being defined\n bool contextlock;\t\t\t///< If the context layout has been established yet\n vector relpath;\t\t///< Relative path (to cwd) for each filename\n vector filename;\t\t///< Stack of current files being parsed\n vector lineno;\t\t\t///< Current line number for each file in stack\n map ctorLocationMap;\t\t///< Map each Constructor to its defining parse location\n map symbolLocationMap;\t///< Map each symbol to its defining parse location\n int4 userop_count;\t\t\t///< Number of userops defined\n bool warnunnecessarypcode;\t\t///< \\b true if we warn of unnecessary ZEXT or SEXT\n bool warndeadtemps;\t\t\t///< \\b true if we warn of temporaries that are written but not read\n bool lenientconflicterrors;\t\t///< \\b true if we ignore most pattern conflict errors\n bool warnalllocalcollisions;\t\t///< \\b true if local export collisions generate individual warnings\n bool warnallnops;\t\t\t///< \\b true if pcode NOPs generate individual warnings\n bool failinsensitivedups;\t\t///< \\b true if case insensitive register duplicates cause error\n bool debugoutput;\t\t\t///< \\b true if output .sla is written in XML debug format\n vector noplist;\t\t///< List of individual NOP warnings\n mutable Location currentLocCache;\t///< Location for (last) request of current location\n int4 errors;\t\t\t\t///< Number of fatal errors encountered\n\n const Location* getCurrentLocation(void) const;\t///< Get the current file and line number being parsed\n void predefinedSymbols(void);\t\t\t\t///< Get SLEIGHs predefined address spaces and symbols\n int4 calcContextVarLayout(int4 start,int4 sz,int4 numbits);\n void buildDecisionTrees(void);\t\t\t///< Build decision trees for all subtables\n void buildPatterns(void);\t\t///< Generate final match patterns based on parse constraint equations\n void checkConsistency(void);\t\t///< Perform final consistency checks on the SLEIGH definitions\n static int4 findCollision(map &local2Operand,const vector &locals,int operand);\n bool checkLocalExports(Constructor *ct);\t///< Check for operands that \\e might export the same local variable\n void checkLocalCollisions(void);\t///< Check all Constructors for local export collisions between operands\n void checkNops(void);\t\t\t///< Report on all Constructors with empty semantic sections\n void checkCaseSensitivity(void);\t///< Check that register names can be treated as case insensitive\n string checkSymbols(SymbolScope *scope);\t///< Make sure label symbols are both defined and used\n void addSymbol(SleighSymbol *sym);\t///< Add a new symbol to the current scope\n SleighSymbol *dedupSymbolList(vector *symlist);\t///< Deduplicate the given list of symbols\n bool expandMacros(ConstructTpl *ctpl);\t///< Expand any formal SLEIGH macros in the given section of p-code\n\n bool finalizeSections(Constructor *big,SectionVector *vec);\t///< Do final checks, expansions, and linking for p-code sections\n static VarnodeTpl *findSize(const ConstTpl &offset,const ConstructTpl *ct);\n static bool forceExportSize(ConstructTpl *ct);\n static uintb insertCrossBuildRegion(uintb addr);\n static void shiftUniqueVn(VarnodeTpl *vn);\n static void shiftUniqueOp(OpTpl *op);\n static void shiftUniqueHandle(HandleTpl *hand);\n static void shiftUniqueConstruct(ConstructTpl *tpl);\n static string formatStatusMessage(const Location* loc, const string &msg);\n void checkUniqueAllocation(void);\t///< Modify temporary Varnode offsets to support \\b crossbuilds\n void process(void);\t\t\t///< Do all post processing on the parsed data structures\npublic:\n SleighCompile(void);\t\t\t\t\t\t///< Constructor\n const Location *getLocation(Constructor* ctor) const;\t\t///< Get the source location of the given Constructor's definition\n const Location *getLocation(SleighSymbol *sym) const;\t\t///< Get the source location of the given symbol's definition\n void reportError(const string &msg);\t\t\t\t///< Issue a fatal error message\n void reportError(const Location *loc, const string &msg);\t///< Issue a fatal error message with a source location\n void reportWarning(const string &msg);\t\t\t///< Issue a warning message\n void reportWarning(const Location *loc, const string &msg);\t///< Issue a warning message with a source location\n int4 numErrors(void) const { return errors; }\t\t\t///< Return the current number of fatal errors\n\n uint4 getUniqueAddr(void);\t\t\t\t\t///< Get the next available temporary register offset\n\n /// \\brief Set whether unnecessary truncation and extension operators generate warnings individually\n ///\n /// \\param val is \\b true if warnings are generated individually. The default is \\b false.\n void setUnnecessaryPcodeWarning(bool val) { warnunnecessarypcode = val; }\n\n /// \\brief Set whether dead temporary registers generate warnings individually\n ///\n /// \\param val is \\b true if warnings are generated individually. The default is \\b false.\n void setDeadTempWarning(bool val) { warndeadtemps = val; }\n\n /// \\brief Set whether named temporary registers must be defined using the \\b local keyword.\n ///\n /// \\param val is \\b true if the \\b local keyword must always be used. The default is \\b false.\n void setEnforceLocalKeyWord(bool val) { pcode.setEnforceLocalKey(val); }\n\n /// \\brief Set whether indistinguishable Constructor patterns generate fatal errors\n ///\n /// \\param val is \\b true if no error is generated. The default is \\b true.\n void setLenientConflict(bool val) { lenientconflicterrors = val; }\n\n /// \\brief Set whether collisions in exported locals generate warnings individually\n ///\n /// \\param val is \\b true if warnings are generated individually. The default is \\b false.\n void setLocalCollisionWarning(bool val) { warnalllocalcollisions = val; }\n\n /// \\brief Set whether NOP Constructors generate warnings individually\n ///\n /// \\param val is \\b true if warnings are generated individually. The default is \\b false.\n void setAllNopWarning(bool val) { warnallnops = val; }\n\n /// \\brief Set whether case insensitive duplicates of register names cause an error\n ///\n /// \\param val is \\b true is duplicates cause an error.\n void setInsensitiveDuplicateError(bool val) { failinsensitivedups = val; }\n\n /// \\brief Set whether the output .sla file should be written in XML debug format\n ///\n /// \\param val is \\b true if the XML debug format should be used\n void setDebugOutput(bool val) { debugoutput = val; }\n\n // Lexer functions\n void calcContextLayout(void);\t\t\t\t///< Calculate the internal context field layout\n string grabCurrentFilePath(void) const;\t\t///< Get the path to the current source file\n void parseFromNewFile(const string &fname);\t\t///< Push a new source file to the current parse stack\n void parsePreprocMacro(void);\t\t\t\t///< Mark start of parsing for an expanded preprocessor macro\n void parseFileFinished(void);\t\t\t\t///< Mark end of parsing for the current file or macro\n void nextLine(void) { lineno.back() += 1; }\t\t///< Indicate parsing proceeded to the next line of the current file\n bool getPreprocValue(const string &nm,string &res) const;\t///< Retrieve a given preprocessor variable\n void setPreprocValue(const string &nm,const string &value);\t///< Set a given preprocessor variable\n bool undefinePreprocValue(const string &nm);\t\t///< Remove the value associated with the given preprocessor variable\n\n // Parser functions\n TokenSymbol *defineToken(string *name,uintb *sz,int4 endian);\n void addTokenField(TokenSymbol *sym,FieldQuality *qual);\n bool addContextField(VarnodeSymbol *sym,FieldQuality *qual);\n void newSpace(SpaceQuality *qual);\n SectionSymbol *newSectionSymbol(const string &nm);\n void setEndian(int4 end);\n\n /// \\brief Set instruction alignment for the SLEIGH specification\n ///\n /// \\param val is the alignment value in bytes. 1 is the default indicating no alignment\n void setAlignment(int4 val) { alignment = val; }\n\n void defineVarnodes(SpaceSymbol *spacesym,uintb *off,uintb *size,vector *names);\n void defineBitrange(string *name,VarnodeSymbol *sym,uint4 bitoffset,uint4 numb);\n void addUserOp(vector *names);\n void attachValues(vector *symlist,vector *numlist);\n void attachNames(vector *symlist,vector *names);\n void attachVarnodes(vector *symlist,vector *varlist);\n SubtableSymbol *newTable(string *nm);\n void newOperand(Constructor *ct,string *nm);\n PatternEquation *constrainOperand(OperandSymbol *sym,PatternExpression *patexp);\n void defineOperand(OperandSymbol *sym,PatternExpression *patexp);\n PatternEquation *defineInvisibleOperand(TripleSymbol *sym);\n void selfDefine(OperandSymbol *sym);\n ConstructTpl *setResultVarnode(ConstructTpl *ct,VarnodeTpl *vn);\n ConstructTpl *setResultStarVarnode(ConstructTpl *ct,StarQuality *star,VarnodeTpl *vn);\n bool contextMod(vector *vec,ContextSymbol *sym,PatternExpression *pe);\n void contextSet(vector *vec,TripleSymbol *sym,ContextSymbol *cvar);\n MacroSymbol *createMacro(string *name,vector *param);\n void compareMacroParams(MacroSymbol *sym,const vector ¶m);\n vector *createMacroUse(MacroSymbol *sym,vector *param);\n SectionVector *standaloneSection(ConstructTpl *main);\n SectionVector *firstNamedSection(ConstructTpl *main,SectionSymbol *sym);\n SectionVector *nextNamedSection(SectionVector *vec,ConstructTpl *section,SectionSymbol *sym);\n SectionVector *finalNamedSection(SectionVector *vec,ConstructTpl *section);\n vector *createCrossBuild(VarnodeTpl *addr,SectionSymbol *sym);\n ConstructTpl *enterSection(void);\n Constructor *createConstructor(SubtableSymbol *sym);\n bool isInRoot(Constructor *ct) const { return (root == ct->getParent()); }\t///< Is the Constructor in the root table?\n void resetConstructors(void);\n void pushWith(SubtableSymbol *ss,PatternEquation *pateq,vector *contvec);\n void popWith(void);\n void buildConstructor(Constructor *big,PatternEquation *pateq,vector *contvec,SectionVector *vec);\n void buildMacro(MacroSymbol *sym,ConstructTpl *rtl);\n void recordNop(void);\n\n // Virtual functions (not used by the compiler)\n virtual void initialize(DocumentStorage &store) {}\n virtual int4 instructionLength(const Address &baseaddr) const { return 0; }\n virtual int4 oneInstruction(PcodeEmit &emit,const Address &baseaddr) const { return 0; }\n virtual int4 printAssembly(AssemblyEmit &emit,const Address &baseaddr) const { return 0; }\n\n void setAllOptions(const map &defines, bool unnecessaryPcodeWarning,\n\t\t bool lenientConflict, bool allCollisionWarning,\n\t\t bool allNopWarning,bool deadTempWarning,bool enforceLocalKeyWord,\n\t\t bool caseSensitiveRegisterNames,bool debugOutput);\n int4 run_compilation(const string &filein,const string &fileout);\n};\n\nostream& operator<<(ostream &os, const ConsistencyChecker::OptimizeRecord &rec);\n\nextern SleighCompile *slgh;\t\t///< A global reference to the SLEIGH compiler accessible to the parse functions\nextern int yydebug;\t\t\t///< Debug state for the SLEIGH parse functions\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/slghparse.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/* A Bison parser, made by GNU Bison 3.5.1. */\n\n/* Bison implementation for Yacc-like parsers in C\n\n Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation,\n Inc.\n\n This program is free software: you can redistribute it and/or modify\n it under the terms of the GNU General Public License as published by\n the Free Software Foundation, either version 3 of the License, or\n (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program. If not, see . */\n\n/* As a special exception, you may create a larger work that contains\n part or all of the Bison parser skeleton and distribute that work\n under terms of your choice, so long as that work isn't itself a\n parser generator using the skeleton or a modified version thereof\n as a parser skeleton. Alternatively, if you modify or redistribute\n the parser skeleton itself, you may (at your option) remove this\n special exception, which will cause the skeleton and the resulting\n Bison output files to be licensed under the GNU General Public\n License without this special exception.\n\n This special exception was added by the Free Software Foundation in\n version 2.2 of Bison. */\n\n/* C LALR(1) parser skeleton written by Richard Stallman, by\n simplifying the original so-called \"semantic\" parser. */\n\n/* All symbols defined below should begin with yy or YY, to avoid\n infringing on user name space. This should be done even for local\n variables, as they might otherwise be expanded by user macros.\n There are some unavoidable exceptions within include files to\n define necessary library symbols; they are noted \"INFRINGES ON\n USER NAME SPACE\" below. */\n\n/* Undocumented macros, especially those whose name start with YY_,\n are private implementation details. Do not rely on them. */\n\n/* Identify Bison output. */\n#define YYBISON 1\n\n/* Bison version. */\n#define YYBISON_VERSION \"3.5.1\"\n\n/* Skeleton name. */\n#define YYSKELETON_NAME \"yacc.c\"\n\n/* Pure parsers. */\n#define YYPURE 0\n\n/* Push parsers. */\n#define YYPUSH 0\n\n/* Pull parsers. */\n#define YYPULL 1\n\n/* Substitute the type names. */\n#define YYSTYPE SLEIGHSTYPE\n/* Substitute the variable and function names. */\n#define yyparse sleighparse\n#define yylex sleighlex\n#define yyerror sleigherror\n#define yydebug sleighdebug\n#define yynerrs sleighnerrs\n#define yylval sleighlval\n#define yychar sleighchar\n\n/* First part of user prologue. */\n\n#include \"slgh_compile.hh\"\n\nextern FILE *sleighin;\nextern int sleighlex(void);\n\nnamespace ghidra {\n\nextern SleighCompile *slgh;\nextern int4 actionon;\nextern int sleighdebug;\nextern int sleigherror(const char *str );\n\n\n# ifndef YY_CAST\n# ifdef __cplusplus\n# define YY_CAST(Type, Val) static_cast (Val)\n# define YY_REINTERPRET_CAST(Type, Val) reinterpret_cast (Val)\n# else\n# define YY_CAST(Type, Val) ((Type) (Val))\n# define YY_REINTERPRET_CAST(Type, Val) ((Type) (Val))\n# endif\n# endif\n# ifndef YY_NULLPTR\n# if defined __cplusplus\n# if 201103L <= __cplusplus\n# define YY_NULLPTR nullptr\n# else\n# define YY_NULLPTR 0\n# endif\n# else\n# define YY_NULLPTR ((void*)0)\n# endif\n# endif\n\n/* Enabling verbose error messages. */\n#ifdef YYERROR_VERBOSE\n# undef YYERROR_VERBOSE\n# define YYERROR_VERBOSE 1\n#else\n# define YYERROR_VERBOSE 0\n#endif\n\n/* Use api.header.include to #include this header\n instead of duplicating it here. */\n#ifndef YY_SLEIGH_SLGHPARSE_HH_INCLUDED\n# define YY_SLEIGH_SLGHPARSE_HH_INCLUDED\n/* Debug traces. */\n#ifndef SLEIGHDEBUG\n# if defined YYDEBUG\n#if YYDEBUG\n# define SLEIGHDEBUG 1\n# else\n# define SLEIGHDEBUG 0\n# endif\n# else /* ! defined YYDEBUG */\n# define SLEIGHDEBUG 0\n# endif /* ! defined YYDEBUG */\n#endif /* ! defined SLEIGHDEBUG */\n#if SLEIGHDEBUG\nextern int sleighdebug;\n#endif\n\n/* Token type. */\n#ifndef SLEIGHTOKENTYPE\n# define SLEIGHTOKENTYPE\n enum sleightokentype\n {\n OP_BOOL_OR = 258,\n OP_BOOL_AND = 259,\n OP_BOOL_XOR = 260,\n OP_OR = 261,\n OP_XOR = 262,\n OP_AND = 263,\n OP_EQUAL = 264,\n OP_NOTEQUAL = 265,\n OP_FEQUAL = 266,\n OP_FNOTEQUAL = 267,\n OP_GREATEQUAL = 268,\n OP_LESSEQUAL = 269,\n OP_SLESS = 270,\n OP_SGREATEQUAL = 271,\n OP_SLESSEQUAL = 272,\n OP_SGREAT = 273,\n OP_FLESS = 274,\n OP_FGREAT = 275,\n OP_FLESSEQUAL = 276,\n OP_FGREATEQUAL = 277,\n OP_LEFT = 278,\n OP_RIGHT = 279,\n OP_SRIGHT = 280,\n OP_FADD = 281,\n OP_FSUB = 282,\n OP_SDIV = 283,\n OP_SREM = 284,\n OP_FMULT = 285,\n OP_FDIV = 286,\n OP_ZEXT = 287,\n OP_CARRY = 288,\n OP_BORROW = 289,\n OP_SEXT = 290,\n OP_SCARRY = 291,\n OP_SBORROW = 292,\n OP_NAN = 293,\n OP_ABS = 294,\n OP_SQRT = 295,\n OP_CEIL = 296,\n OP_FLOOR = 297,\n OP_ROUND = 298,\n OP_INT2FLOAT = 299,\n OP_FLOAT2FLOAT = 300,\n OP_TRUNC = 301,\n OP_CPOOLREF = 302,\n OP_NEW = 303,\n OP_POPCOUNT = 304,\n OP_LZCOUNT = 305,\n BADINTEGER = 306,\n GOTO_KEY = 307,\n CALL_KEY = 308,\n RETURN_KEY = 309,\n IF_KEY = 310,\n DEFINE_KEY = 311,\n ATTACH_KEY = 312,\n MACRO_KEY = 313,\n SPACE_KEY = 314,\n TYPE_KEY = 315,\n RAM_KEY = 316,\n DEFAULT_KEY = 317,\n REGISTER_KEY = 318,\n ENDIAN_KEY = 319,\n WITH_KEY = 320,\n ALIGN_KEY = 321,\n OP_UNIMPL = 322,\n TOKEN_KEY = 323,\n SIGNED_KEY = 324,\n NOFLOW_KEY = 325,\n HEX_KEY = 326,\n DEC_KEY = 327,\n BIG_KEY = 328,\n LITTLE_KEY = 329,\n SIZE_KEY = 330,\n WORDSIZE_KEY = 331,\n OFFSET_KEY = 332,\n NAMES_KEY = 333,\n VALUES_KEY = 334,\n VARIABLES_KEY = 335,\n PCODEOP_KEY = 336,\n IS_KEY = 337,\n LOCAL_KEY = 338,\n DELAYSLOT_KEY = 339,\n CROSSBUILD_KEY = 340,\n EXPORT_KEY = 341,\n BUILD_KEY = 342,\n CONTEXT_KEY = 343,\n ELLIPSIS_KEY = 344,\n GLOBALSET_KEY = 345,\n BITRANGE_KEY = 346,\n CHAR = 347,\n INTEGER = 348,\n INTB = 349,\n STRING = 350,\n SYMBOLSTRING = 351,\n SPACESYM = 352,\n SECTIONSYM = 353,\n TOKENSYM = 354,\n USEROPSYM = 355,\n VALUESYM = 356,\n VALUEMAPSYM = 357,\n CONTEXTSYM = 358,\n NAMESYM = 359,\n VARSYM = 360,\n BITSYM = 361,\n SPECSYM = 362,\n VARLISTSYM = 363,\n OPERANDSYM = 364,\n JUMPSYM = 365,\n MACROSYM = 366,\n LABELSYM = 367,\n SUBTABLESYM = 368\n };\n#endif\n\n/* Value type. */\n#if ! defined SLEIGHSTYPE && ! defined SLEIGHSTYPE_IS_DECLARED\nunion SLEIGHSTYPE\n{\n\n char ch;\n uintb *i;\n intb *big;\n string *str;\n vector *strlist;\n vector *biglist;\n vector *param;\n SpaceQuality *spacequal;\n FieldQuality *fieldqual;\n StarQuality *starqual;\n VarnodeTpl *varnode;\n ExprTree *tree;\n vector *stmt;\n ConstructTpl *sem;\n SectionVector *sectionstart;\n Constructor *construct;\n PatternEquation *pateq;\n PatternExpression *patexp;\n\n vector *symlist;\n vector *contop;\n SleighSymbol *anysym;\n SpaceSymbol *spacesym;\n SectionSymbol *sectionsym;\n TokenSymbol *tokensym;\n UserOpSymbol *useropsym;\n MacroSymbol *macrosym;\n LabelSymbol *labelsym;\n SubtableSymbol *subtablesym;\n OperandSymbol *operandsym;\n VarnodeListSymbol *varlistsym;\n VarnodeSymbol *varsym;\n BitrangeSymbol *bitsym;\n NameSymbol *namesym;\n ValueSymbol *valuesym;\n ValueMapSymbol *valuemapsym;\n ContextSymbol *contextsym;\n FamilySymbol *famsym;\n SpecificSymbol *specsym;\n\n\n};\ntypedef union SLEIGHSTYPE SLEIGHSTYPE;\n# define SLEIGHSTYPE_IS_TRIVIAL 1\n# define SLEIGHSTYPE_IS_DECLARED 1\n#endif\n\n\nextern SLEIGHSTYPE sleighlval;\n\nint sleighparse (void);\n\n#endif /* !YY_SLEIGH_SLGHPARSE_HH_INCLUDED */\n\n\n\n#ifdef short\n# undef short\n#endif\n\n/* On compilers that do not define __PTRDIFF_MAX__ etc., make sure\n and (if available) are included\n so that the code can choose integer types of a good width. */\n\n#ifndef __PTRDIFF_MAX__\n# include /* INFRINGES ON USER NAME SPACE */\n# if defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__\n# include /* INFRINGES ON USER NAME SPACE */\n# define YY_STDINT_H\n# endif\n#endif\n\n/* Narrow types that promote to a signed type and that can represent a\n signed or unsigned integer of at least N bits. In tables they can\n save space and decrease cache pressure. Promoting to a signed type\n helps avoid bugs in integer arithmetic. */\n\n#ifdef __INT_LEAST8_MAX__\ntypedef __INT_LEAST8_TYPE__ yytype_int8;\n#elif defined YY_STDINT_H\ntypedef int_least8_t yytype_int8;\n#else\ntypedef signed char yytype_int8;\n#endif\n\n#ifdef __INT_LEAST16_MAX__\ntypedef __INT_LEAST16_TYPE__ yytype_int16;\n#elif defined YY_STDINT_H\ntypedef int_least16_t yytype_int16;\n#else\ntypedef short yytype_int16;\n#endif\n\n#if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__\ntypedef __UINT_LEAST8_TYPE__ yytype_uint8;\n#elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \\\n && UINT_LEAST8_MAX <= INT_MAX)\ntypedef uint_least8_t yytype_uint8;\n#elif !defined __UINT_LEAST8_MAX__ && UCHAR_MAX <= INT_MAX\ntypedef unsigned char yytype_uint8;\n#else\ntypedef short yytype_uint8;\n#endif\n\n#if defined __UINT_LEAST16_MAX__ && __UINT_LEAST16_MAX__ <= __INT_MAX__\ntypedef __UINT_LEAST16_TYPE__ yytype_uint16;\n#elif (!defined __UINT_LEAST16_MAX__ && defined YY_STDINT_H \\\n && UINT_LEAST16_MAX <= INT_MAX)\ntypedef uint_least16_t yytype_uint16;\n#elif !defined __UINT_LEAST16_MAX__ && USHRT_MAX <= INT_MAX\ntypedef unsigned short yytype_uint16;\n#else\ntypedef int yytype_uint16;\n#endif\n\n#ifndef YYPTRDIFF_T\n# if defined __PTRDIFF_TYPE__ && defined __PTRDIFF_MAX__\n# define YYPTRDIFF_T __PTRDIFF_TYPE__\n# define YYPTRDIFF_MAXIMUM __PTRDIFF_MAX__\n# elif defined PTRDIFF_MAX\n# ifndef ptrdiff_t\n# include /* INFRINGES ON USER NAME SPACE */\n# endif\n# define YYPTRDIFF_T ptrdiff_t\n# define YYPTRDIFF_MAXIMUM PTRDIFF_MAX\n# else\n# define YYPTRDIFF_T long\n# define YYPTRDIFF_MAXIMUM LONG_MAX\n# endif\n#endif\n\n#ifndef YYSIZE_T\n# ifdef __SIZE_TYPE__\n# define YYSIZE_T __SIZE_TYPE__\n# elif defined size_t\n# define YYSIZE_T size_t\n# elif defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__\n# include /* INFRINGES ON USER NAME SPACE */\n# define YYSIZE_T size_t\n# else\n# define YYSIZE_T unsigned\n# endif\n#endif\n\n#define YYSIZE_MAXIMUM \\\n YY_CAST (YYPTRDIFF_T, \\\n (YYPTRDIFF_MAXIMUM < YY_CAST (YYSIZE_T, -1) \\\n ? YYPTRDIFF_MAXIMUM \\\n : YY_CAST (YYSIZE_T, -1)))\n\n#define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X))\n\n/* Stored state numbers (used for stacks). */\ntypedef yytype_int16 yy_state_t;\n\n/* State numbers in computations. */\ntypedef int yy_state_fast_t;\n\n#ifndef YY_\n# if defined YYENABLE_NLS && YYENABLE_NLS\n# if ENABLE_NLS\n# include /* INFRINGES ON USER NAME SPACE */\n# define YY_(Msgid) dgettext (\"bison-runtime\", Msgid)\n# endif\n# endif\n# ifndef YY_\n# define YY_(Msgid) Msgid\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE_PURE\n# if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__)\n# define YY_ATTRIBUTE_PURE __attribute__ ((__pure__))\n# else\n# define YY_ATTRIBUTE_PURE\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE_UNUSED\n# if defined __GNUC__ && 2 < __GNUC__ + (7 <= __GNUC_MINOR__)\n# define YY_ATTRIBUTE_UNUSED __attribute__ ((__unused__))\n# else\n# define YY_ATTRIBUTE_UNUSED\n# endif\n#endif\n\n/* Suppress unused-variable warnings by \"using\" E. */\n#if ! defined lint || defined __GNUC__\n# define YYUSE(E) ((void) (E))\n#else\n# define YYUSE(E) /* empty */\n#endif\n\n#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__\n/* Suppress an incorrect diagnostic about yylval being uninitialized. */\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \\\n _Pragma (\"GCC diagnostic push\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wuninitialized\\\"\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wmaybe-uninitialized\\\"\")\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END \\\n _Pragma (\"GCC diagnostic pop\")\n#else\n# define YY_INITIAL_VALUE(Value) Value\n#endif\n#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END\n#endif\n#ifndef YY_INITIAL_VALUE\n# define YY_INITIAL_VALUE(Value) /* Nothing. */\n#endif\n\n#if defined __cplusplus && defined __GNUC__ && ! defined __ICC && 6 <= __GNUC__\n# define YY_IGNORE_USELESS_CAST_BEGIN \\\n _Pragma (\"GCC diagnostic push\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wuseless-cast\\\"\")\n# define YY_IGNORE_USELESS_CAST_END \\\n _Pragma (\"GCC diagnostic pop\")\n#endif\n#ifndef YY_IGNORE_USELESS_CAST_BEGIN\n# define YY_IGNORE_USELESS_CAST_BEGIN\n# define YY_IGNORE_USELESS_CAST_END\n#endif\n\n\n#define YY_ASSERT(E) ((void) (0 && (E)))\n\n#if ! defined yyoverflow || YYERROR_VERBOSE\n\n/* The parser invokes alloca or malloc; define the necessary symbols. */\n\n# ifdef YYSTACK_USE_ALLOCA\n# if YYSTACK_USE_ALLOCA\n# ifdef __GNUC__\n# define YYSTACK_ALLOC __builtin_alloca\n# elif defined __BUILTIN_VA_ARG_INCR\n# include /* INFRINGES ON USER NAME SPACE */\n# elif defined _AIX\n# define YYSTACK_ALLOC __alloca\n# elif defined _MSC_VER\n# include /* INFRINGES ON USER NAME SPACE */\n# define alloca _alloca\n# else\n# define YYSTACK_ALLOC alloca\n# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS\n# include /* INFRINGES ON USER NAME SPACE */\n /* Use EXIT_SUCCESS as a witness for stdlib.h. */\n# ifndef EXIT_SUCCESS\n# define EXIT_SUCCESS 0\n# endif\n# endif\n# endif\n# endif\n# endif\n\n# ifdef YYSTACK_ALLOC\n /* Pacify GCC's 'empty if-body' warning. */\n# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)\n# ifndef YYSTACK_ALLOC_MAXIMUM\n /* The OS might guarantee only one guard page at the bottom of the stack,\n and a page size can be as small as 4096 bytes. So we cannot safely\n invoke alloca (N) if N exceeds 4096. Use a slightly smaller number\n to allow for a few compiler-allocated temporary stack slots. */\n# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */\n# endif\n# else\n# define YYSTACK_ALLOC YYMALLOC\n# define YYSTACK_FREE YYFREE\n# ifndef YYSTACK_ALLOC_MAXIMUM\n# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM\n# endif\n# if (defined __cplusplus && ! defined EXIT_SUCCESS \\\n && ! ((defined YYMALLOC || defined malloc) \\\n && (defined YYFREE || defined free)))\n# include /* INFRINGES ON USER NAME SPACE */\n# ifndef EXIT_SUCCESS\n# define EXIT_SUCCESS 0\n# endif\n# endif\n# ifndef YYMALLOC\n# define YYMALLOC malloc\n# if ! defined malloc && ! defined EXIT_SUCCESS\nvoid *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */\n# endif\n# endif\n# ifndef YYFREE\n# define YYFREE free\n# if ! defined free && ! defined EXIT_SUCCESS\nvoid free (void *); /* INFRINGES ON USER NAME SPACE */\n# endif\n# endif\n# endif\n#endif /* ! defined yyoverflow || YYERROR_VERBOSE */\n\n\n#if (! defined yyoverflow \\\n && (! defined __cplusplus \\\n || (defined SLEIGHSTYPE_IS_TRIVIAL && SLEIGHSTYPE_IS_TRIVIAL)))\n\n/* A type that is properly aligned for any stack member. */\nunion yyalloc\n{\n yy_state_t yyss_alloc;\n YYSTYPE yyvs_alloc;\n};\n\n/* The size of the maximum gap between one aligned stack and the next. */\n# define YYSTACK_GAP_MAXIMUM (YYSIZEOF (union yyalloc) - 1)\n\n/* The size of an array large to enough to hold all stacks, each with\n N elements. */\n# define YYSTACK_BYTES(N) \\\n ((N) * (YYSIZEOF (yy_state_t) + YYSIZEOF (YYSTYPE)) \\\n + YYSTACK_GAP_MAXIMUM)\n\n# define YYCOPY_NEEDED 1\n\n/* Relocate STACK from its old location to the new one. The\n local variables YYSIZE and YYSTACKSIZE give the old and new number of\n elements in the stack, and YYPTR gives the new location of the\n stack. Advance YYPTR to a properly aligned location for the next\n stack. */\n# define YYSTACK_RELOCATE(Stack_alloc, Stack) \\\n do \\\n { \\\n YYPTRDIFF_T yynewbytes; \\\n YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \\\n Stack = &yyptr->Stack_alloc; \\\n yynewbytes = yystacksize * YYSIZEOF (*Stack) + YYSTACK_GAP_MAXIMUM; \\\n yyptr += yynewbytes / YYSIZEOF (*yyptr); \\\n } \\\n while (0)\n\n#endif\n\n#if defined YYCOPY_NEEDED && YYCOPY_NEEDED\n/* Copy COUNT objects from SRC to DST. The source and destination do\n not overlap. */\n# ifndef YYCOPY\n# if defined __GNUC__ && 1 < __GNUC__\n# define YYCOPY(Dst, Src, Count) \\\n __builtin_memcpy (Dst, Src, YY_CAST (YYSIZE_T, (Count)) * sizeof (*(Src)))\n# else\n# define YYCOPY(Dst, Src, Count) \\\n do \\\n { \\\n YYPTRDIFF_T yyi; \\\n for (yyi = 0; yyi < (Count); yyi++) \\\n (Dst)[yyi] = (Src)[yyi]; \\\n } \\\n while (0)\n# endif\n# endif\n#endif /* !YYCOPY_NEEDED */\n\n/* YYFINAL -- State number of the termination state. */\n#define YYFINAL 5\n/* YYLAST -- Last index in YYTABLE. */\n#define YYLAST 2629\n\n/* YYNTOKENS -- Number of terminals. */\n#define YYNTOKENS 137\n/* YYNNTS -- Number of nonterminals. */\n#define YYNNTS 71\n/* YYNRULES -- Number of rules. */\n#define YYNRULES 336\n/* YYNSTATES -- Number of states. */\n#define YYNSTATES 714\n\n#define YYUNDEFTOK 2\n#define YYMAXUTOK 368\n\n\n/* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM\n as returned by yylex, with out-of-bounds checking. */\n#define YYTRANSLATE(YYX) \\\n (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)\n\n/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM\n as returned by yylex. */\nstatic const yytype_uint8 yytranslate[] =\n{\n 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 136, 43, 2, 2, 2, 38, 11, 2,\n 129, 130, 36, 32, 131, 33, 2, 37, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 135, 8,\n 17, 128, 18, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 132, 2, 133, 9, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 134, 6, 127, 44, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,\n 5, 7, 10, 12, 13, 14, 15, 16, 19, 20,\n 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,\n 31, 34, 35, 39, 40, 41, 42, 45, 46, 47,\n 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\n 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,\n 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,\n 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\n 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\n 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,\n 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,\n 118, 119, 120, 121, 122, 123, 124, 125, 126\n};\n\n#if SLEIGHDEBUG\n /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */\nstatic const yytype_int16 yyrline[] =\n{\n 0, 155, 155, 156, 157, 158, 160, 161, 162, 163,\n 164, 165, 166, 167, 168, 169, 171, 172, 173, 174,\n 176, 177, 179, 181, 183, 184, 185, 186, 187, 189,\n 191, 192, 195, 196, 197, 198, 199, 201, 202, 203,\n 204, 205, 206, 208, 210, 211, 212, 213, 214, 215,\n 216, 218, 220, 222, 224, 225, 227, 230, 232, 234,\n 236, 238, 241, 243, 244, 245, 247, 249, 250, 251,\n 254, 255, 258, 260, 261, 262, 264, 265, 267, 268,\n 269, 270, 271, 272, 273, 274, 275, 277, 278, 279,\n 280, 282, 284, 287, 288, 289, 290, 291, 292, 293,\n 294, 295, 296, 297, 298, 299, 301, 302, 303, 304,\n 306, 307, 309, 310, 312, 313, 315, 316, 317, 318,\n 319, 320, 321, 324, 325, 326, 327, 329, 330, 332,\n 333, 334, 335, 336, 337, 339, 340, 342, 344, 345,\n 347, 348, 349, 350, 351, 353, 354, 355, 356, 358,\n 359, 360, 361, 362, 363, 364, 365, 366, 367, 368,\n 369, 370, 371, 372, 373, 374, 375, 376, 377, 378,\n 379, 380, 381, 382, 384, 385, 386, 387, 388, 389,\n 390, 391, 392, 393, 394, 395, 396, 397, 398, 399,\n 400, 401, 402, 403, 404, 405, 406, 407, 408, 409,\n 410, 411, 412, 413, 414, 415, 416, 417, 418, 419,\n 420, 421, 422, 423, 424, 425, 426, 427, 428, 429,\n 430, 431, 432, 433, 434, 435, 436, 437, 438, 439,\n 440, 441, 442, 443, 444, 445, 446, 447, 448, 449,\n 450, 452, 453, 454, 455, 457, 458, 459, 460, 461,\n 462, 463, 465, 466, 467, 468, 470, 471, 472, 473,\n 474, 476, 477, 478, 480, 481, 483, 484, 485, 486,\n 487, 488, 490, 491, 492, 493, 494, 496, 497, 498,\n 499, 501, 502, 504, 505, 506, 508, 509, 510, 512,\n 513, 514, 517, 518, 520, 521, 522, 524, 526, 527,\n 528, 529, 531, 532, 533, 535, 536, 537, 538, 539,\n 541, 542, 544, 545, 547, 548, 551, 552, 553, 555,\n 556, 557, 559, 560, 561, 562, 563, 564, 565, 566,\n 567, 568, 569, 570, 571, 572, 573\n};\n#endif\n\n#if SLEIGHDEBUG || YYERROR_VERBOSE || 0\n/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.\n First, the terminals, then, starting at YYNTOKENS, nonterminals. */\nstatic const char *const yytname[] =\n{\n \"$end\", \"error\", \"$undefined\", \"OP_BOOL_OR\", \"OP_BOOL_AND\",\n \"OP_BOOL_XOR\", \"'|'\", \"OP_OR\", \"';'\", \"'^'\", \"OP_XOR\", \"'&'\", \"OP_AND\",\n \"OP_EQUAL\", \"OP_NOTEQUAL\", \"OP_FEQUAL\", \"OP_FNOTEQUAL\", \"'<'\", \"'>'\",\n \"OP_GREATEQUAL\", \"OP_LESSEQUAL\", \"OP_SLESS\", \"OP_SGREATEQUAL\",\n \"OP_SLESSEQUAL\", \"OP_SGREAT\", \"OP_FLESS\", \"OP_FGREAT\", \"OP_FLESSEQUAL\",\n \"OP_FGREATEQUAL\", \"OP_LEFT\", \"OP_RIGHT\", \"OP_SRIGHT\", \"'+'\", \"'-'\",\n \"OP_FADD\", \"OP_FSUB\", \"'*'\", \"'/'\", \"'%'\", \"OP_SDIV\", \"OP_SREM\",\n \"OP_FMULT\", \"OP_FDIV\", \"'!'\", \"'~'\", \"OP_ZEXT\", \"OP_CARRY\", \"OP_BORROW\",\n \"OP_SEXT\", \"OP_SCARRY\", \"OP_SBORROW\", \"OP_NAN\", \"OP_ABS\", \"OP_SQRT\",\n \"OP_CEIL\", \"OP_FLOOR\", \"OP_ROUND\", \"OP_INT2FLOAT\", \"OP_FLOAT2FLOAT\",\n \"OP_TRUNC\", \"OP_CPOOLREF\", \"OP_NEW\", \"OP_POPCOUNT\", \"OP_LZCOUNT\",\n \"BADINTEGER\", \"GOTO_KEY\", \"CALL_KEY\", \"RETURN_KEY\", \"IF_KEY\",\n \"DEFINE_KEY\", \"ATTACH_KEY\", \"MACRO_KEY\", \"SPACE_KEY\", \"TYPE_KEY\",\n \"RAM_KEY\", \"DEFAULT_KEY\", \"REGISTER_KEY\", \"ENDIAN_KEY\", \"WITH_KEY\",\n \"ALIGN_KEY\", \"OP_UNIMPL\", \"TOKEN_KEY\", \"SIGNED_KEY\", \"NOFLOW_KEY\",\n \"HEX_KEY\", \"DEC_KEY\", \"BIG_KEY\", \"LITTLE_KEY\", \"SIZE_KEY\",\n \"WORDSIZE_KEY\", \"OFFSET_KEY\", \"NAMES_KEY\", \"VALUES_KEY\", \"VARIABLES_KEY\",\n \"PCODEOP_KEY\", \"IS_KEY\", \"LOCAL_KEY\", \"DELAYSLOT_KEY\", \"CROSSBUILD_KEY\",\n \"EXPORT_KEY\", \"BUILD_KEY\", \"CONTEXT_KEY\", \"ELLIPSIS_KEY\",\n \"GLOBALSET_KEY\", \"BITRANGE_KEY\", \"CHAR\", \"INTEGER\", \"INTB\", \"STRING\",\n \"SYMBOLSTRING\", \"SPACESYM\", \"SECTIONSYM\", \"TOKENSYM\", \"USEROPSYM\",\n \"VALUESYM\", \"VALUEMAPSYM\", \"CONTEXTSYM\", \"NAMESYM\", \"VARSYM\", \"BITSYM\",\n \"SPECSYM\", \"VARLISTSYM\", \"OPERANDSYM\", \"JUMPSYM\", \"MACROSYM\", \"LABELSYM\",\n \"SUBTABLESYM\", \"'}'\", \"'='\", \"'('\", \"')'\", \"','\", \"'['\", \"']'\", \"'{'\",\n \"':'\", \"' '\", \"$accept\", \"spec\", \"definition\", \"constructorlike\",\n \"endiandef\", \"aligndef\", \"tokendef\", \"tokenprop\", \"contextdef\",\n \"contextprop\", \"fielddef\", \"contextfielddef\", \"spacedef\", \"spaceprop\",\n \"varnodedef\", \"bitrangedef\", \"bitrangelist\", \"bitrangesingle\",\n \"pcodeopdef\", \"valueattach\", \"nameattach\", \"varattach\", \"macrodef\",\n \"withblockstart\", \"withblockmid\", \"withblock\", \"id_or_nil\",\n \"bitpat_or_nil\", \"macrostart\", \"rtlbody\", \"constructor\",\n \"constructprint\", \"subtablestart\", \"pexpression\", \"pequation\", \"elleq\",\n \"ellrt\", \"atomic\", \"constraint\", \"contextblock\", \"contextlist\",\n \"section_def\", \"rtlfirstsection\", \"rtlcontinue\", \"rtl\", \"rtlmid\",\n \"statement\", \"expr\", \"sizedstar\", \"jumpdest\", \"varnode\",\n \"integervarnode\", \"lhsvarnode\", \"label\", \"exportvarnode\", \"familysymbol\",\n \"specificsymbol\", \"charstring\", \"intblist\", \"intbpart\", \"stringlist\",\n \"stringpart\", \"anystringlist\", \"anystringpart\", \"valuelist\", \"valuepart\",\n \"varlist\", \"varpart\", \"paramlist\", \"oplist\", \"anysymbol\", YY_NULLPTR\n};\n#endif\n\n# ifdef YYPRINT\n/* YYTOKNUM[NUM] -- (External) token number corresponding to the\n (internal) symbol number NUM (which must be that of a token). */\nstatic const yytype_int16 yytoknum[] =\n{\n 0, 256, 257, 258, 259, 260, 124, 261, 59, 94,\n 262, 38, 263, 264, 265, 266, 267, 60, 62, 268,\n 269, 270, 271, 272, 273, 274, 275, 276, 277, 278,\n 279, 280, 43, 45, 281, 282, 42, 47, 37, 283,\n 284, 285, 286, 33, 126, 287, 288, 289, 290, 291,\n 292, 293, 294, 295, 296, 297, 298, 299, 300, 301,\n 302, 303, 304, 305, 306, 307, 308, 309, 310, 311,\n 312, 313, 314, 315, 316, 317, 318, 319, 320, 321,\n 322, 323, 324, 325, 326, 327, 328, 329, 330, 331,\n 332, 333, 334, 335, 336, 337, 338, 339, 340, 341,\n 342, 343, 344, 345, 346, 347, 348, 349, 350, 351,\n 352, 353, 354, 355, 356, 357, 358, 359, 360, 361,\n 362, 363, 364, 365, 366, 367, 368, 125, 61, 40,\n 41, 44, 91, 93, 123, 58, 32\n};\n# endif\n\n#define YYPACT_NINF (-293)\n\n#define yypact_value_is_default(Yyn) \\\n ((Yyn) == YYPACT_NINF)\n\n#define YYTABLE_NINF (-271)\n\n#define yytable_value_is_error(Yyn) \\\n ((Yyn) == YYTABLE_NINF)\n\n /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing\n STATE-NUM. */\nstatic const yytype_int16 yypact[] =\n{\n 35, 12, 37, -293, -15, -293, 20, 1667, 303, 61,\n -72, -13, 41, -293, -293, -293, -293, -293, 430, -293,\n 1591, -293, 89, -293, -293, -293, -293, -293, -293, -293,\n -293, 40, -293, 47, -293, 24, 180, 84, -293, -293,\n 2467, 99, 2486, -27, 160, 191, 211, -41, -41, -41,\n 206, -293, -293, 234, -293, -293, -293, 244, -293, -293,\n -293, -293, -293, -293, -293, -293, -293, -293, -293, -293,\n -293, -293, -293, 346, 247, -293, 249, 320, 251, -293,\n 253, -293, 255, 261, -33, -293, -293, -293, -293, -293,\n 78, -293, -293, -293, -293, 286, -293, 78, -293, -293,\n -293, 286, 390, 392, -293, -293, 305, 290, -293, -293,\n 313, 415, -293, 301, 6, -293, 307, -293, -293, 36,\n 323, -16, -92, 344, 78, 327, -293, -293, -293, 328,\n 330, -293, -293, -293, -293, 331, 83, 355, 356, 337,\n 1721, 1522, -293, -293, -293, -293, -293, -293, 339, -293,\n 78, 5, -293, -293, 368, -293, 45, -293, 5, -293,\n -293, 457, 362, -293, 2419, -293, 354, -293, -293, -54,\n -293, -293, 186, 2503, 466, 370, -293, -24, 470, -293,\n -87, 474, -293, 60, 352, 365, 381, 388, 393, 397,\n -293, -293, -293, -293, -293, 262, -22, -103, -293, 369,\n 389, 10, 1571, 406, 367, 314, 382, 384, 372, 33,\n 387, -293, 385, -293, -293, -293, 391, 94, -293, 1571,\n -8, -293, 149, -293, 151, -293, 1543, 16, 78, 78,\n 78, -293, -60, -293, 1543, 1543, 1543, 1543, 1543, 1543,\n -60, -293, 400, -293, -293, -293, 386, -293, 431, -293,\n -293, -293, -293, -293, 2443, -293, -293, -293, 416, -293,\n -293, -21, -293, -293, -293, -39, -293, -293, 419, 399,\n 403, 404, 405, 424, -293, -293, 417, -293, -293, 519,\n 532, 447, 452, -293, 427, -293, -293, -293, 1571, 552,\n -293, 1571, 553, -293, 1571, 1571, 1571, 1571, 1571, 433,\n 442, 443, 445, 482, 483, 485, 487, 522, 523, 525,\n 527, 558, 563, 566, 603, 606, 639, 640, -293, 1571,\n 1845, 1571, -293, 139, -4, 448, 587, 602, 363, 642,\n 771, -293, 164, 802, -293, 807, 712, 1571, 714, 1571,\n 1571, 1571, 1528, 749, 752, 1571, 754, 1543, 1543, -293,\n 1543, 2405, -293, -293, -293, 85, 884, -293, -50, -293,\n -293, -293, 2405, 2405, 2405, 2405, 2405, 2405, -293, 819,\n 794, 812, -293, -293, -293, -293, 829, -293, -293, -293,\n -293, -293, -293, -293, -293, 830, 869, 870, 874, 314,\n -293, -293, 882, -293, 906, 325, -293, 564, -293, 604,\n -293, -293, -293, -293, 1571, 1571, 1571, 1571, 1571, 1571,\n 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571,\n 1571, 1571, 1571, 808, 1571, 1571, 1571, 1571, 1571, 1571,\n 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571,\n 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571,\n 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571, 1571,\n 409, -293, 14, 914, 949, -293, 1571, 950, -293, 930,\n 212, 989, -293, 990, 1092, -293, 1127, -293, -293, -293,\n -293, 1898, 1012, 2218, 66, 1938, 136, 1571, 1006, 1047,\n 1978, 1045, -293, -293, 380, 1543, 1543, 1543, 1543, 1543,\n 1543, 1543, 1543, 1543, 1051, -293, 1087, 1132, -293, -293,\n -293, -10, 1167, 1085, 1114, -293, 1125, 1126, 1166, 1170,\n -293, 1200, 1203, 1332, 1367, 1372, 848, 685, 888, 725,\n 767, 928, 968, 1008, 1048, 1088, 1128, 1168, 1208, 1248,\n 162, 644, 1288, 1328, 182, -293, 2257, 2294, 2294, 2328,\n 2360, 2430, 1773, 1773, 1773, 1773, 2484, 2484, 2484, 2484,\n 2484, 2484, 2484, 2484, 2484, 2484, 2484, 2484, 1856, 1856,\n 1856, 2382, 2382, 2382, 2382, -293, -293, -293, -293, -293,\n -293, -293, 1407, 1246, 1285, -293, 2018, 0, 1412, 1447,\n 1452, 314, -293, -293, -293, 1571, 1487, 1571, -293, 1492,\n 2058, -293, -293, -293, 1350, -293, 2463, 285, 1556, 169,\n 169, 296, 296, -293, -293, 1613, 1543, 1543, 1656, 216,\n -293, -293, 321, 1390, -27, -293, -293, -293, -293, 1429,\n -293, -293, -293, -293, -293, 1571, -293, 1571, 1571, -293,\n -293, -293, -293, -293, -293, -293, -293, -293, -293, -293,\n 1571, -293, -293, -293, -293, -293, 1430, -293, -293, 1571,\n -293, -293, -293, -293, 2098, -293, 2218, -293, -293, 1438,\n 1409, 1443, 1565, 2396, -293, -293, 1549, 1550, -293, -293,\n 1450, 1573, -293, 1368, 1408, 1448, 1488, 1451, 2138, -293,\n 1462, 1475, 1480, -293, -293, -293, -293, -293, -293, -293,\n -293, -293, -293, -293, -293, 1571, 1470, 1473, 2178, 1597,\n 1600, -293, -293, -293\n};\n\n /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.\n Performed when YYTABLE does not specify something else to do. Zero\n means the default is an error. */\nstatic const yytype_int16 yydefact[] =\n{\n 0, 0, 0, 2, 0, 1, 0, 0, 0, 0,\n 67, 0, 0, 89, 4, 5, 3, 6, 0, 7,\n 0, 8, 0, 9, 10, 11, 12, 13, 14, 17,\n 63, 0, 18, 0, 16, 0, 0, 0, 15, 19,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 69, 68, 0, 88, 87, 23, 0, 322, 323,\n 324, 325, 328, 329, 330, 331, 332, 336, 333, 334,\n 335, 326, 327, 27, 0, 29, 0, 31, 0, 43,\n 0, 50, 0, 0, 0, 66, 64, 65, 145, 82,\n 0, 281, 83, 86, 85, 84, 81, 0, 78, 80,\n 90, 79, 0, 0, 44, 45, 0, 0, 28, 293,\n 0, 0, 30, 0, 0, 54, 0, 303, 304, 0,\n 0, 0, 0, 319, 70, 0, 34, 35, 36, 0,\n 0, 39, 40, 41, 42, 0, 0, 0, 0, 0,\n 140, 0, 272, 273, 274, 275, 124, 276, 123, 126,\n 0, 127, 106, 111, 113, 114, 125, 282, 127, 20,\n 21, 0, 0, 294, 0, 57, 0, 53, 55, 0,\n 305, 306, 0, 0, 0, 0, 284, 0, 0, 311,\n 0, 0, 320, 0, 127, 71, 0, 0, 0, 0,\n 46, 47, 48, 49, 61, 0, 0, 244, 257, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 256, 254,\n 0, 277, 0, 278, 279, 280, 0, 255, 146, 0,\n 0, 253, 0, 173, 252, 110, 0, 0, 0, 0,\n 0, 129, 0, 112, 0, 0, 0, 0, 0, 0,\n 0, 22, 0, 295, 292, 296, 0, 52, 0, 309,\n 307, 308, 302, 298, 0, 299, 59, 285, 0, 286,\n 288, 0, 58, 313, 312, 0, 60, 72, 0, 0,\n 0, 0, 0, 0, 254, 255, 0, 259, 252, 0,\n 0, 0, 0, 247, 246, 251, 248, 245, 0, 0,\n 250, 0, 0, 170, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 238, 0,\n 0, 0, 174, 252, 0, 0, 0, 0, 0, 0,\n 143, 271, 0, 0, 266, 0, 0, 0, 0, 316,\n 0, 316, 0, 0, 0, 0, 0, 0, 0, 91,\n 0, 122, 92, 93, 115, 108, 109, 107, 0, 75,\n 145, 76, 117, 118, 120, 121, 119, 116, 77, 24,\n 0, 0, 300, 297, 301, 287, 0, 289, 291, 283,\n 315, 314, 310, 321, 62, 0, 0, 0, 0, 0,\n 265, 264, 0, 243, 0, 0, 165, 0, 168, 0,\n 189, 216, 202, 190, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 316, 0,\n 0, 0, 316, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 175, 0, 0, 0, 147, 0, 0, 154, 0,\n 0, 0, 267, 0, 144, 263, 0, 261, 141, 161,\n 258, 0, 0, 317, 0, 0, 0, 0, 0, 0,\n 0, 0, 104, 105, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 134, 0, 0, 128, 138,\n 145, 0, 0, 0, 0, 290, 0, 0, 0, 0,\n 260, 242, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 176, 205, 204, 203, 193,\n 191, 192, 179, 180, 206, 207, 181, 184, 182, 183,\n 185, 186, 187, 188, 208, 209, 210, 211, 194, 195,\n 196, 177, 178, 212, 213, 197, 198, 200, 199, 201,\n 214, 215, 0, 0, 0, 236, 0, 0, 0, 0,\n 0, 0, 269, 142, 151, 0, 0, 0, 158, 0,\n 0, 160, 159, 149, 0, 94, 101, 102, 100, 98,\n 99, 95, 96, 97, 103, 0, 0, 0, 0, 0,\n 73, 137, 0, 0, 0, 32, 33, 37, 38, 0,\n 249, 167, 169, 171, 220, 0, 219, 0, 0, 226,\n 217, 218, 228, 229, 230, 225, 224, 227, 240, 231,\n 0, 233, 234, 239, 166, 235, 0, 150, 148, 0,\n 164, 163, 162, 268, 0, 156, 318, 172, 155, 0,\n 0, 0, 0, 0, 74, 139, 0, 0, 26, 25,\n 0, 0, 241, 0, 0, 0, 0, 0, 0, 153,\n 0, 0, 0, 130, 133, 135, 136, 56, 51, 221,\n 222, 223, 232, 237, 152, 0, 0, 0, 0, 0,\n 0, 157, 131, 132\n};\n\n /* YYPGOTO[NTERM-NUM]. */\nstatic const yytype_int16 yypgoto[] =\n{\n -293, -293, 1578, 1579, -293, -293, -293, -293, -293, -293,\n -293, -293, -293, -293, -293, -293, -293, 1497, -293, -293,\n -293, -293, -293, -293, -293, -293, -293, -293, -293, 1373,\n -293, -293, -293, -192, -94, -293, 1471, -293, -293, -108,\n -293, 1022, -293, -293, 1281, 1135, -293, -196, -139, -195,\n -125, 1184, 1315, -138, -293, -90, -52, 1616, -293, -293,\n 1025, -293, -293, -293, 366, -293, -293, -293, -292, -293,\n 15\n};\n\n /* YYDEFGOTO[NTERM-NUM]. */\nstatic const yytype_int16 yydefgoto[] =\n{\n -1, 2, 14, 15, 3, 16, 17, 18, 19, 20,\n 73, 77, 21, 22, 23, 24, 114, 115, 25, 26,\n 27, 28, 29, 30, 31, 32, 53, 184, 33, 361,\n 34, 35, 36, 351, 151, 152, 153, 154, 155, 232,\n 358, 621, 509, 510, 139, 140, 218, 483, 321, 289,\n 322, 221, 222, 290, 333, 352, 323, 95, 178, 261,\n 111, 164, 174, 254, 120, 172, 181, 265, 484, 183,\n 74\n};\n\n /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If\n positive, shift that token. If negative, reduce the rule whose\n number is the opposite. If YYTABLE_NINF, syntax error. */\nstatic const yytype_int16 yytable[] =\n{\n 156, 219, 223, 158, 465, 292, 320, 156, 658, 258,\n 247, 228, 376, 229, 167, 220, 230, 175, 293, 619,\n 359, 263, 228, 342, 229, 195, 179, 230, 38, 281,\n 185, 264, 282, 89, 156, 78, 51, 5, 6, 40,\n 180, 6, 362, 363, 364, 365, 366, 367, 42, 486,\n 240, 156, 248, 504, 52, 105, 227, 108, 505, 234,\n 156, 43, 235, 236, 237, 238, 506, 332, 44, 380,\n 277, 45, 507, 117, 360, 118, 269, 46, 198, 381,\n 327, 109, 259, 508, 260, 377, 279, 378, 224, 4,\n 176, 119, 395, 229, 382, 397, 230, 79, 399, 400,\n 401, 402, 403, 280, 1, 110, 7, 8, 9, 84,\n 8, 9, 379, 37, 113, 10, 177, 620, 10, 90,\n 208, 343, 54, 423, 466, 461, 540, 344, 659, 91,\n 544, 467, 92, 93, 355, 356, 357, 231, 156, 156,\n 156, 481, 294, 278, 485, 11, 354, 39, 11, 490,\n 170, 325, 171, 278, 334, 492, 493, 190, 494, 191,\n 94, 337, 80, 12, 81, -262, 12, 85, 338, 50,\n 102, 103, 13, 239, 353, 13, 55, 82, 83, 245,\n 141, 88, 353, 353, 353, 353, 353, 353, 255, 96,\n 267, 268, 142, 143, 144, 145, 596, 597, 146, 147,\n 148, 500, 501, 472, 149, 502, 503, 150, 526, 527,\n 528, 529, 530, 531, 532, 533, 534, 535, 536, 537,\n 538, 539, -263, 541, 542, 543, -263, 106, 546, 547,\n 548, 549, 550, 551, 552, 553, 554, 555, 556, 557,\n 558, 559, 560, 561, 562, 563, 564, 565, 566, 567,\n 568, 569, 570, 571, 572, 573, 574, 575, 576, 577,\n 578, 579, 580, 581, 520, 582, 599, 597, 462, 374,\n 586, 463, 474, 195, 464, 97, 278, 345, 112, -261,\n 477, 346, 211, -261, 213, 91, 214, 215, 98, 99,\n 475, 600, 648, 597, 249, 353, 353, 497, 353, 113,\n 250, 116, 251, 606, 607, 608, 609, 610, 611, 612,\n 613, 614, 653, 597, 498, 499, 100, 500, 501, 252,\n 589, 502, 503, 590, 676, 195, 198, 677, 424, 425,\n 426, 427, 502, 503, 428, 123, 429, 278, 430, 431,\n 432, 433, 434, 435, 436, 437, 438, 439, 440, 441,\n 442, 443, 444, 445, 446, 447, 448, 449, 450, 451,\n 452, 453, 454, 455, 456, 457, 458, 459, 208, 124,\n 274, 228, 125, 229, 195, 129, 230, 130, 198, 135,\n 211, 136, 213, 137, 214, 215, 196, 495, 275, 138,\n 496, 157, 497, 328, 47, 48, 49, 276, 159, 664,\n 160, 666, 131, 132, 133, 134, 196, 678, 679, 498,\n 499, 161, 500, 501, 121, 122, 502, 503, 197, 162,\n 208, 163, 274, 165, 672, 673, 196, 198, 126, 166,\n 127, 128, 211, 283, 213, 169, 214, 215, 56, 683,\n 275, 684, 685, 353, 353, 353, 353, 353, 353, 353,\n 353, 353, 182, 283, 686, 173, 186, 187, 523, 188,\n 189, 192, 193, 688, 194, 241, 663, 226, 242, 208,\n 233, 274, 246, 283, 256, 284, 257, 285, 262, 219,\n 223, 211, 266, 213, 231, 214, 215, 270, 329, 275,\n 330, 286, 287, 220, 271, 284, 326, 285, 471, 272,\n 211, 288, 213, 273, 214, 215, 335, 336, 331, 708,\n 605, 286, 287, 340, 324, 284, 339, 285, 370, 371,\n 341, 291, 375, 389, 211, 670, 213, 383, 214, 215,\n 369, 286, 287, 384, 385, 386, 387, 390, 57, 278,\n 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,\n 391, 68, 69, 70, 71, 388, 72, 392, 393, 394,\n 396, 398, 404, 671, 353, 353, 224, 424, 425, 426,\n 427, 405, 406, 428, 407, 429, 468, 430, 431, 432,\n 433, 434, 435, 436, 437, 438, 439, 440, 441, 442,\n 443, 444, 445, 446, 447, 448, 449, 450, 451, 452,\n 453, 454, 455, 456, 457, 458, 459, 424, 425, 426,\n 427, 408, 409, 428, 410, 429, 411, 430, 431, 432,\n 433, 434, 435, 436, 437, 438, 439, 440, 441, 442,\n 443, 444, 445, 446, 447, 448, 449, 450, 451, 452,\n 453, 454, 455, 456, 457, 458, 459, 424, 425, 426,\n 427, 412, 413, 428, 414, 429, 415, 430, 431, 432,\n 433, 434, 435, 436, 437, 438, 439, 440, 441, 442,\n 443, 444, 445, 446, 447, 448, 449, 450, 451, 452,\n 453, 454, 455, 456, 457, 458, 459, 416, 424, 425,\n 426, 427, 417, 469, 428, 418, 429, 524, 430, 431,\n 432, 433, 434, 435, 436, 437, 438, 439, 440, 441,\n 442, 443, 444, 445, 446, 447, 448, 449, 450, 451,\n 452, 453, 454, 455, 456, 457, 458, 459, 424, 425,\n 426, 427, 419, 470, 428, 420, 429, 525, 430, 431,\n 432, 433, 434, 435, 436, 437, 438, 439, 440, 441,\n 442, 443, 444, 445, 446, 447, 448, 449, 450, 451,\n 452, 453, 454, 455, 456, 457, 458, 459, 421, 422,\n 424, 425, 426, 427, 649, 650, 428, 473, 429, -270,\n 430, 431, 432, 433, 434, 435, 436, 437, 438, 439,\n 440, 441, 442, 443, 444, 445, 446, 447, 448, 449,\n 450, 451, 452, 453, 454, 455, 456, 457, 458, 459,\n 478, 424, 425, 426, 427, 479, 635, 428, 480, 429,\n 482, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 488, 637, 428, 489, 429,\n 491, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 230, 512, 428, 638, 429,\n 513, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 515, 516, 428, 545, 429,\n 514, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 517, 518, 428, 634, 429,\n 519, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 521, 522, 428, 636, 429,\n 584, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 585, 587, 428, 639, 429,\n 588, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 591, 592, 428, 640, 429,\n -262, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 593, 601, 428, 641, 429,\n 595, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 602, 604, 428, 642, 429,\n 615, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 616, 623, 428, 643, 429,\n 624, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 625, 626, 428, 644, 429,\n 617, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 622, 627, 428, 645, 429,\n 628, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 629, 630, 428, 646, 429,\n 631, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 632, 655, 428, 647, 429,\n 633, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 654, 656, 428, 651, 429,\n 660, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 661, 669, 428, 652, 429,\n 662, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 665, 680, 428, 699, 429,\n 667, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 682, 687, 428, 700, 429,\n 691, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 690, 495, 693, 692, 496, 347, 497, 701, 695,\n 696, 698, 195, 697, 703, 498, 499, 348, 500, 501,\n 705, 706, 502, 503, 498, 499, 707, 500, 501, 75,\n 709, 502, 503, 710, 295, 712, 296, 197, 713, 86,\n 87, 168, 225, 368, 297, 298, 299, 300, 702, 301,\n 302, 303, 304, 305, 306, 307, 308, 309, 310, 311,\n 312, 313, 314, 315, 316, 198, 142, 143, 144, 145,\n 675, 511, 146, 147, 148, 618, 583, 476, 149, 681,\n 349, 150, 101, 0, 0, 0, 487, 142, 143, 144,\n 145, 211, 0, 213, 147, 214, 215, 195, 0, 0,\n 0, 0, 350, 196, 0, 0, 0, 208, 0, 274,\n 0, 0, 0, 0, 317, 619, 0, 0, 0, 211,\n 318, 213, 197, 214, 215, 0, 0, 275, 0, 76,\n 319, 58, 59, 60, 61, 62, 63, 64, 65, 66,\n 67, 0, 68, 69, 70, 71, 0, 72, 0, 0,\n 198, 199, 200, 201, 202, 0, 0, 142, 143, 144,\n 145, 211, 195, 213, 147, 214, 215, 0, 196, 40,\n 0, 0, 0, 0, 0, 0, 41, 0, 42, 0,\n 0, 0, 203, 204, 205, 0, 207, 197, 0, 0,\n 0, 43, 208, 0, 209, 0, 0, 0, 44, 210,\n 0, 45, 0, 0, 211, 212, 213, 46, 214, 215,\n 216, 0, 217, 674, 0, 198, 199, 200, 201, 202,\n 434, 435, 436, 437, 438, 439, 440, 441, 442, 443,\n 444, 445, 446, 447, 448, 449, 450, 451, 452, 453,\n 454, 455, 456, 457, 458, 459, 0, 203, 204, 205,\n 206, 207, 0, 0, 0, 0, 0, 208, 0, 209,\n 0, 0, 0, 0, 210, 0, 0, 0, 0, 211,\n 212, 213, 0, 214, 215, 216, 0, 217, 424, 425,\n 426, 427, 0, 0, 428, 0, 429, 0, 430, 431,\n 432, 433, 434, 435, 436, 437, 438, 439, 440, 441,\n 442, 443, 444, 445, 446, 447, 448, 449, 450, 451,\n 452, 453, 454, 455, 456, 457, 458, 459, 449, 450,\n 451, 452, 453, 454, 455, 456, 457, 458, 459, 0,\n 0, 424, 425, 426, 427, 0, 594, 428, 0, 429,\n 460, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 598, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 603, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 657, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 668, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 689, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 704, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 711, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 424, 425, 426, 427, 0, 0, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 425, 426, 427, 0, 0, 428, 0, 429, 0,\n 430, 431, 432, 433, 434, 435, 436, 437, 438, 439,\n 440, 441, 442, 443, 444, 445, 446, 447, 448, 449,\n 450, 451, 452, 453, 454, 455, 456, 457, 458, 459,\n 427, 0, 0, 428, 0, 429, 0, 430, 431, 432,\n 433, 434, 435, 436, 437, 438, 439, 440, 441, 442,\n 443, 444, 445, 446, 447, 448, 449, 450, 451, 452,\n 453, 454, 455, 456, 457, 458, 459, 428, 0, 429,\n 0, 430, 431, 432, 433, 434, 435, 436, 437, 438,\n 439, 440, 441, 442, 443, 444, 445, 446, 447, 448,\n 449, 450, 451, 452, 453, 454, 455, 456, 457, 458,\n 459, 429, 0, 430, 431, 432, 433, 434, 435, 436,\n 437, 438, 439, 440, 441, 442, 443, 444, 445, 446,\n 447, 448, 449, 450, 451, 452, 453, 454, 455, 456,\n 457, 458, 459, 495, 694, 0, 496, 0, 497, 0,\n 0, 0, 495, 0, 0, 496, 0, 497, 453, 454,\n 455, 456, 457, 458, 459, 498, 499, 0, 500, 501,\n 0, 0, 502, 503, 498, 499, 0, 500, 501, 0,\n 0, 502, 503, 430, 431, 432, 433, 434, 435, 436,\n 437, 438, 439, 440, 441, 442, 443, 444, 445, 446,\n 447, 448, 449, 450, 451, 452, 453, 454, 455, 456,\n 457, 458, 459, 496, 0, 497, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 498, 499, 0, 500, 501, 0, 0, 502,\n 503, -271, -271, -271, -271, -271, -271, -271, -271, -271,\n -271, -271, -271, 446, 447, 448, 449, 450, 451, 452,\n 453, 454, 455, 456, 457, 458, 459, 243, 0, 58,\n 59, 60, 61, 62, 63, 64, 65, 66, 67, 0,\n 68, 69, 70, 71, 0, 72, 0, 0, 0, 0,\n 0, 372, 244, 58, 59, 60, 61, 62, 63, 64,\n 65, 66, 67, 0, 68, 69, 70, 71, 0, 72,\n 0, 0, 0, 0, 0, 104, 373, 58, 59, 60,\n 61, 62, 63, 64, 65, 66, 67, 0, 68, 69,\n 70, 71, 0, 72, 107, 0, 58, 59, 60, 61,\n 62, 63, 64, 65, 66, 67, 0, 68, 69, 70,\n 71, 253, 72, 58, 59, 60, 61, 62, 63, 64,\n 65, 66, 67, 0, 68, 69, 70, 71, 0, 72\n};\n\nstatic const yytype_int16 yycheck[] =\n{\n 90, 140, 140, 97, 8, 200, 202, 97, 8, 33,\n 64, 6, 33, 8, 8, 140, 11, 33, 8, 29,\n 80, 108, 6, 219, 8, 11, 118, 11, 8, 132,\n 124, 118, 135, 9, 124, 20, 108, 0, 1, 72,\n 132, 1, 234, 235, 236, 237, 238, 239, 81, 341,\n 158, 141, 106, 103, 126, 40, 150, 42, 108, 14,\n 150, 94, 17, 18, 19, 20, 116, 206, 101, 108,\n 195, 104, 122, 114, 134, 116, 184, 110, 64, 118,\n 205, 108, 106, 133, 108, 106, 108, 108, 140, 77,\n 106, 132, 288, 8, 133, 291, 11, 8, 294, 295,\n 296, 297, 298, 125, 69, 132, 69, 70, 71, 69,\n 70, 71, 133, 128, 108, 78, 132, 127, 78, 95,\n 106, 129, 135, 319, 128, 321, 418, 135, 128, 105,\n 422, 135, 108, 109, 228, 229, 230, 132, 228, 229,\n 230, 337, 132, 195, 340, 108, 130, 127, 108, 345,\n 114, 203, 116, 205, 206, 347, 348, 74, 350, 76,\n 136, 128, 73, 126, 75, 132, 126, 127, 135, 108,\n 86, 87, 135, 128, 226, 135, 135, 88, 89, 164,\n 102, 134, 234, 235, 236, 237, 238, 239, 173, 9,\n 130, 131, 114, 115, 116, 117, 130, 131, 120, 121,\n 122, 32, 33, 328, 126, 36, 37, 129, 404, 405,\n 406, 407, 408, 409, 410, 411, 412, 413, 414, 415,\n 416, 417, 128, 419, 420, 421, 132, 128, 424, 425,\n 426, 427, 428, 429, 430, 431, 432, 433, 434, 435,\n 436, 437, 438, 439, 440, 441, 442, 443, 444, 445,\n 446, 447, 448, 449, 450, 451, 452, 453, 454, 455,\n 456, 457, 458, 459, 389, 460, 130, 131, 129, 254,\n 466, 132, 108, 11, 135, 95, 328, 128, 118, 128,\n 332, 132, 118, 132, 120, 105, 122, 123, 108, 109,\n 126, 487, 130, 131, 108, 347, 348, 12, 350, 108,\n 114, 90, 116, 495, 496, 497, 498, 499, 500, 501,\n 502, 503, 130, 131, 29, 30, 136, 32, 33, 133,\n 108, 36, 37, 111, 108, 11, 64, 111, 3, 4,\n 5, 6, 36, 37, 9, 129, 11, 389, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, 40, 41, 42, 106, 135,\n 108, 6, 128, 8, 11, 128, 11, 128, 64, 128,\n 118, 128, 120, 128, 122, 123, 17, 7, 126, 128,\n 10, 105, 12, 11, 91, 92, 93, 135, 8, 595,\n 8, 597, 82, 83, 84, 85, 17, 86, 87, 29,\n 30, 106, 32, 33, 48, 49, 36, 37, 36, 129,\n 106, 108, 108, 8, 616, 617, 17, 64, 82, 128,\n 84, 85, 118, 64, 120, 128, 122, 123, 8, 635,\n 126, 637, 638, 495, 496, 497, 498, 499, 500, 501,\n 502, 503, 108, 64, 650, 132, 129, 129, 133, 129,\n 129, 106, 106, 659, 127, 8, 591, 128, 106, 106,\n 102, 108, 118, 64, 8, 106, 106, 108, 8, 618,\n 618, 118, 8, 120, 132, 122, 123, 106, 106, 126,\n 108, 122, 123, 618, 106, 106, 129, 108, 135, 106,\n 118, 132, 120, 106, 122, 123, 122, 135, 126, 705,\n 130, 122, 123, 128, 108, 106, 129, 108, 132, 88,\n 129, 132, 106, 106, 118, 615, 120, 108, 122, 123,\n 130, 122, 123, 134, 131, 131, 131, 18, 108, 591,\n 110, 111, 112, 113, 114, 115, 116, 117, 118, 119,\n 18, 121, 122, 123, 124, 131, 126, 110, 106, 132,\n 8, 8, 129, 615, 616, 617, 618, 3, 4, 5,\n 6, 129, 129, 9, 129, 11, 128, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 40, 41, 42, 3, 4, 5,\n 6, 129, 129, 9, 129, 11, 129, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 40, 41, 42, 3, 4, 5,\n 6, 129, 129, 9, 129, 11, 129, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 40, 41, 42, 129, 3, 4,\n 5, 6, 129, 106, 9, 129, 11, 133, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, 40, 41, 42, 3, 4,\n 5, 6, 129, 131, 9, 129, 11, 133, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, 40, 41, 42, 129, 129,\n 3, 4, 5, 6, 130, 131, 9, 135, 11, 8,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,\n 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,\n 8, 3, 4, 5, 6, 8, 131, 9, 106, 11,\n 106, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 106, 131, 9, 106, 11,\n 106, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 11, 77, 9, 131, 11,\n 106, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 106, 106, 9, 130, 11,\n 128, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 106, 106, 9, 130, 11,\n 106, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 133, 110, 9, 130, 11,\n 106, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 106, 106, 9, 130, 11,\n 130, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 106, 106, 9, 130, 11,\n 8, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 8, 130, 9, 130, 11,\n 128, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 128, 131, 9, 130, 11,\n 129, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 128, 131, 9, 130, 11,\n 106, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 130, 130, 9, 130, 11,\n 128, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 128, 130, 9, 130, 11,\n 130, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 135, 133, 9, 130, 11,\n 8, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 8, 130, 9, 130, 11,\n 8, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 8, 131, 9, 130, 11,\n 8, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 8, 106, 9, 130, 11,\n 8, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 8, 106, 9, 130, 11,\n 8, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, 106, 106, 9, 130, 11,\n 131, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 133, 7, 8, 131, 10, 33, 12, 130, 30,\n 30, 8, 11, 133, 133, 29, 30, 44, 32, 33,\n 128, 116, 36, 37, 29, 30, 116, 32, 33, 8,\n 130, 36, 37, 130, 33, 8, 35, 36, 8, 31,\n 31, 114, 141, 240, 43, 44, 45, 46, 130, 48,\n 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,\n 59, 60, 61, 62, 63, 64, 114, 115, 116, 117,\n 618, 360, 120, 121, 122, 510, 462, 332, 126, 624,\n 107, 129, 36, -1, -1, -1, 128, 114, 115, 116,\n 117, 118, -1, 120, 121, 122, 123, 11, -1, -1,\n -1, -1, 129, 17, -1, -1, -1, 106, -1, 108,\n -1, -1, -1, -1, 113, 29, -1, -1, -1, 118,\n 119, 120, 36, 122, 123, -1, -1, 126, -1, 108,\n 129, 110, 111, 112, 113, 114, 115, 116, 117, 118,\n 119, -1, 121, 122, 123, 124, -1, 126, -1, -1,\n 64, 65, 66, 67, 68, -1, -1, 114, 115, 116,\n 117, 118, 11, 120, 121, 122, 123, -1, 17, 72,\n -1, -1, -1, -1, -1, -1, 79, -1, 81, -1,\n -1, -1, 96, 97, 98, -1, 100, 36, -1, -1,\n -1, 94, 106, -1, 108, -1, -1, -1, 101, 113,\n -1, 104, -1, -1, 118, 119, 120, 110, 122, 123,\n 124, -1, 126, 127, -1, 64, 65, 66, 67, 68,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\n 37, 38, 39, 40, 41, 42, -1, 96, 97, 98,\n 99, 100, -1, -1, -1, -1, -1, 106, -1, 108,\n -1, -1, -1, -1, 113, -1, -1, -1, -1, 118,\n 119, 120, -1, 122, 123, 124, -1, 126, 3, 4,\n 5, 6, -1, -1, 9, -1, 11, -1, 13, 14,\n 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\n 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,\n 35, 36, 37, 38, 39, 40, 41, 42, 32, 33,\n 34, 35, 36, 37, 38, 39, 40, 41, 42, -1,\n -1, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n 65, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, 8, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 3, 4, 5, 6, -1, -1, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 4, 5, 6, -1, -1, 9, -1, 11, -1,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,\n 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,\n 6, -1, -1, 9, -1, 11, -1, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 40, 41, 42, 9, -1, 11,\n -1, 13, 14, 15, 16, 17, 18, 19, 20, 21,\n 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,\n 42, 11, -1, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 40, 41, 42, 7, 8, -1, 10, -1, 12, -1,\n -1, -1, 7, -1, -1, 10, -1, 12, 36, 37,\n 38, 39, 40, 41, 42, 29, 30, -1, 32, 33,\n -1, -1, 36, 37, 29, 30, -1, 32, 33, -1,\n -1, 36, 37, 13, 14, 15, 16, 17, 18, 19,\n 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,\n 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\n 40, 41, 42, 10, -1, 12, -1, -1, -1, -1,\n -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,\n -1, -1, 29, 30, -1, 32, 33, -1, -1, 36,\n 37, 17, 18, 19, 20, 21, 22, 23, 24, 25,\n 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,\n 36, 37, 38, 39, 40, 41, 42, 108, -1, 110,\n 111, 112, 113, 114, 115, 116, 117, 118, 119, -1,\n 121, 122, 123, 124, -1, 126, -1, -1, -1, -1,\n -1, 108, 133, 110, 111, 112, 113, 114, 115, 116,\n 117, 118, 119, -1, 121, 122, 123, 124, -1, 126,\n -1, -1, -1, -1, -1, 108, 133, 110, 111, 112,\n 113, 114, 115, 116, 117, 118, 119, -1, 121, 122,\n 123, 124, -1, 126, 108, -1, 110, 111, 112, 113,\n 114, 115, 116, 117, 118, 119, -1, 121, 122, 123,\n 124, 108, 126, 110, 111, 112, 113, 114, 115, 116,\n 117, 118, 119, -1, 121, 122, 123, 124, -1, 126\n};\n\n /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing\n symbol of state STATE-NUM. */\nstatic const yytype_uint8 yystos[] =\n{\n 0, 69, 138, 141, 77, 0, 1, 69, 70, 71,\n 78, 108, 126, 135, 139, 140, 142, 143, 144, 145,\n 146, 149, 150, 151, 152, 155, 156, 157, 158, 159,\n 160, 161, 162, 165, 167, 168, 169, 128, 8, 127,\n 72, 79, 81, 94, 101, 104, 110, 91, 92, 93,\n 108, 108, 126, 163, 135, 135, 8, 108, 110, 111,\n 112, 113, 114, 115, 116, 117, 118, 119, 121, 122,\n 123, 124, 126, 147, 207, 8, 108, 148, 207, 8,\n 73, 75, 88, 89, 69, 127, 139, 140, 134, 9,\n 95, 105, 108, 109, 136, 194, 9, 95, 108, 109,\n 136, 194, 86, 87, 108, 207, 128, 108, 207, 108,\n 132, 197, 118, 108, 153, 154, 90, 114, 116, 132,\n 201, 201, 201, 129, 135, 128, 82, 84, 85, 128,\n 128, 82, 83, 84, 85, 128, 128, 128, 128, 181,\n 182, 102, 114, 115, 116, 117, 120, 121, 122, 126,\n 129, 171, 172, 173, 174, 175, 192, 105, 171, 8,\n 8, 106, 129, 108, 198, 8, 128, 8, 154, 128,\n 114, 116, 202, 132, 199, 33, 106, 132, 195, 118,\n 132, 203, 108, 206, 164, 171, 129, 129, 129, 129,\n 74, 76, 106, 106, 127, 11, 17, 36, 64, 65,\n 66, 67, 68, 96, 97, 98, 99, 100, 106, 108,\n 113, 118, 119, 120, 122, 123, 124, 126, 183, 185,\n 187, 188, 189, 190, 193, 173, 128, 171, 6, 8,\n 11, 132, 176, 102, 14, 17, 18, 19, 20, 128,\n 176, 8, 106, 108, 133, 207, 118, 64, 106, 108,\n 114, 116, 133, 108, 200, 207, 8, 106, 33, 106,\n 108, 196, 8, 108, 118, 204, 8, 130, 131, 176,\n 106, 106, 106, 106, 108, 126, 135, 187, 193, 108,\n 125, 132, 135, 64, 106, 108, 122, 123, 132, 186,\n 190, 132, 186, 8, 132, 33, 35, 43, 44, 45,\n 46, 48, 49, 50, 51, 52, 53, 54, 55, 56,\n 57, 58, 59, 60, 61, 62, 63, 113, 119, 129,\n 184, 185, 187, 193, 108, 193, 129, 187, 11, 106,\n 108, 126, 185, 191, 193, 122, 135, 128, 135, 129,\n 128, 129, 184, 129, 135, 128, 132, 33, 44, 107,\n 129, 170, 192, 193, 130, 171, 171, 171, 177, 80,\n 134, 166, 170, 170, 170, 170, 170, 170, 166, 130,\n 132, 88, 108, 133, 207, 106, 33, 106, 108, 133,\n 108, 118, 133, 108, 134, 131, 131, 131, 131, 106,\n 18, 18, 110, 106, 132, 184, 8, 184, 8, 184,\n 184, 184, 184, 184, 129, 129, 129, 129, 129, 129,\n 129, 129, 129, 129, 129, 129, 129, 129, 129, 129,\n 129, 129, 129, 184, 3, 4, 5, 6, 9, 11,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,\n 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,\n 65, 184, 129, 132, 135, 8, 128, 135, 128, 106,\n 131, 135, 187, 135, 108, 126, 189, 193, 8, 8,\n 106, 184, 106, 184, 205, 184, 205, 128, 106, 106,\n 184, 106, 170, 170, 170, 7, 10, 12, 29, 30,\n 32, 33, 36, 37, 103, 108, 116, 122, 133, 179,\n 180, 181, 77, 106, 128, 106, 106, 106, 106, 106,\n 187, 133, 110, 133, 133, 133, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 205, 184, 184, 184, 205, 130, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 186, 188, 106, 106, 184, 106, 130, 108,\n 111, 106, 106, 8, 8, 128, 130, 131, 8, 130,\n 184, 130, 128, 8, 131, 130, 170, 170, 170, 170,\n 170, 170, 170, 170, 170, 129, 128, 128, 182, 29,\n 127, 178, 128, 131, 106, 130, 130, 130, 130, 135,\n 133, 8, 8, 8, 130, 131, 130, 131, 131, 130,\n 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,\n 131, 130, 130, 130, 8, 130, 131, 8, 8, 128,\n 8, 8, 8, 187, 184, 8, 184, 8, 8, 106,\n 192, 193, 170, 170, 127, 178, 108, 111, 86, 87,\n 106, 197, 106, 184, 184, 184, 184, 106, 184, 8,\n 133, 131, 131, 8, 8, 30, 30, 133, 8, 130,\n 130, 130, 130, 133, 8, 128, 116, 116, 184, 130,\n 130, 8, 8, 8\n};\n\n /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */\nstatic const yytype_uint8 yyr1[] =\n{\n 0, 137, 138, 138, 138, 138, 139, 139, 139, 139,\n 139, 139, 139, 139, 139, 139, 140, 140, 140, 140,\n 141, 141, 142, 143, 144, 144, 144, 144, 144, 145,\n 146, 146, 147, 147, 147, 147, 147, 148, 148, 148,\n 148, 148, 148, 149, 150, 150, 150, 150, 150, 150,\n 150, 151, 151, 152, 153, 153, 154, 155, 156, 157,\n 158, 159, 160, 161, 161, 161, 162, 163, 163, 163,\n 164, 164, 165, 166, 166, 166, 167, 167, 168, 168,\n 168, 168, 168, 168, 168, 168, 168, 169, 169, 169,\n 169, 170, 170, 170, 170, 170, 170, 170, 170, 170,\n 170, 170, 170, 170, 170, 170, 171, 171, 171, 171,\n 172, 172, 173, 173, 174, 174, 175, 175, 175, 175,\n 175, 175, 175, 175, 175, 175, 175, 176, 176, 177,\n 177, 177, 177, 177, 177, 178, 178, 179, 180, 180,\n 181, 181, 181, 181, 181, 182, 182, 182, 182, 183,\n 183, 183, 183, 183, 183, 183, 183, 183, 183, 183,\n 183, 183, 183, 183, 183, 183, 183, 183, 183, 183,\n 183, 183, 183, 183, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 184, 184, 184, 184, 184, 184, 184, 184, 184,\n 184, 185, 185, 185, 185, 186, 186, 186, 186, 186,\n 186, 186, 187, 187, 187, 187, 188, 188, 188, 188,\n 188, 189, 189, 189, 190, 190, 191, 191, 191, 191,\n 191, 191, 192, 192, 192, 192, 192, 193, 193, 193,\n 193, 194, 194, 195, 195, 195, 196, 196, 196, 196,\n 196, 196, 197, 197, 198, 198, 198, 199, 200, 200,\n 200, 200, 201, 201, 201, 202, 202, 202, 202, 202,\n 203, 203, 204, 204, 204, 204, 205, 205, 205, 206,\n 206, 206, 207, 207, 207, 207, 207, 207, 207, 207,\n 207, 207, 207, 207, 207, 207, 207\n};\n\n /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */\nstatic const yytype_int8 yyr2[] =\n{\n 0, 2, 1, 2, 2, 2, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,\n 5, 5, 5, 2, 6, 9, 9, 2, 3, 2,\n 3, 2, 7, 7, 2, 2, 2, 7, 7, 2,\n 2, 2, 2, 2, 3, 3, 4, 4, 4, 4,\n 2, 10, 5, 4, 1, 2, 8, 4, 5, 5,\n 5, 4, 6, 1, 2, 2, 2, 0, 1, 1,\n 0, 1, 5, 3, 4, 1, 5, 5, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 1,\n 2, 1, 1, 1, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 2, 2, 1, 3, 3, 3,\n 2, 1, 2, 1, 1, 3, 3, 3, 3, 3,\n 3, 3, 3, 1, 1, 1, 1, 0, 3, 0,\n 5, 8, 8, 5, 2, 3, 3, 2, 1, 3,\n 1, 4, 5, 3, 4, 0, 2, 4, 6, 4,\n 5, 4, 7, 6, 3, 5, 5, 9, 4, 4,\n 4, 3, 5, 5, 5, 3, 5, 5, 3, 5,\n 2, 5, 5, 1, 1, 2, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 2,\n 2, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 2, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 2, 4, 4, 4,\n 4, 6, 6, 6, 4, 4, 4, 4, 4, 4,\n 4, 4, 6, 4, 4, 4, 3, 6, 1, 4,\n 4, 6, 4, 3, 1, 1, 1, 1, 1, 4,\n 1, 1, 1, 1, 1, 1, 1, 1, 3, 2,\n 4, 1, 1, 1, 3, 3, 1, 2, 4, 3,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 2, 3, 1, 2, 1, 2, 1, 2,\n 3, 2, 3, 1, 1, 2, 2, 3, 1, 1,\n 2, 2, 3, 1, 1, 1, 1, 2, 2, 2,\n 3, 1, 1, 1, 2, 2, 0, 1, 3, 0,\n 1, 3, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1\n};\n\n\n#define yyerrok (yyerrstatus = 0)\n#define yyclearin (yychar = YYEMPTY)\n#define YYEMPTY (-2)\n#define YYEOF 0\n\n#define YYACCEPT goto yyacceptlab\n#define YYABORT goto yyabortlab\n#define YYERROR goto yyerrorlab\n\n\n#define YYRECOVERING() (!!yyerrstatus)\n\n#define YYBACKUP(Token, Value) \\\n do \\\n if (yychar == YYEMPTY) \\\n { \\\n yychar = (Token); \\\n yylval = (Value); \\\n YYPOPSTACK (yylen); \\\n yystate = *yyssp; \\\n goto yybackup; \\\n } \\\n else \\\n { \\\n yyerror (YY_(\"syntax error: cannot back up\")); \\\n YYERROR; \\\n } \\\n while (0)\n\n/* Error token number */\n#define YYTERROR 1\n#define YYERRCODE 256\n\n\n\n/* Enable debugging if requested. */\n#if SLEIGHDEBUG\n\n# ifndef YYFPRINTF\n# include /* INFRINGES ON USER NAME SPACE */\n# define YYFPRINTF fprintf\n# endif\n\n# define YYDPRINTF(Args) \\\ndo { \\\n if (yydebug) \\\n YYFPRINTF Args; \\\n} while (0)\n\n/* This macro is provided for backward compatibility. */\n#ifndef YY_LOCATION_PRINT\n# define YY_LOCATION_PRINT(File, Loc) ((void) 0)\n#endif\n\n\n# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \\\ndo { \\\n if (yydebug) \\\n { \\\n YYFPRINTF (stderr, \"%s \", Title); \\\n yy_symbol_print (stderr, \\\n Type, Value); \\\n YYFPRINTF (stderr, \"\\n\"); \\\n } \\\n} while (0)\n\n\n/*-----------------------------------.\n| Print this symbol's value on YYO. |\n`-----------------------------------*/\n\nstatic void\nyy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep)\n{\n FILE *yyoutput = yyo;\n YYUSE (yyoutput);\n if (!yyvaluep)\n return;\n# ifdef YYPRINT\n if (yytype < YYNTOKENS)\n YYPRINT (yyo, yytoknum[yytype], *yyvaluep);\n# endif\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n YYUSE (yytype);\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n/*---------------------------.\n| Print this symbol on YYO. |\n`---------------------------*/\n\nstatic void\nyy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep)\n{\n YYFPRINTF (yyo, \"%s %s (\",\n yytype < YYNTOKENS ? \"token\" : \"nterm\", yytname[yytype]);\n\n yy_symbol_value_print (yyo, yytype, yyvaluep);\n YYFPRINTF (yyo, \")\");\n}\n\n/*------------------------------------------------------------------.\n| yy_stack_print -- Print the state stack from its BOTTOM up to its |\n| TOP (included). |\n`------------------------------------------------------------------*/\n\nstatic void\nyy_stack_print (yy_state_t *yybottom, yy_state_t *yytop)\n{\n YYFPRINTF (stderr, \"Stack now\");\n for (; yybottom <= yytop; yybottom++)\n {\n int yybot = *yybottom;\n YYFPRINTF (stderr, \" %d\", yybot);\n }\n YYFPRINTF (stderr, \"\\n\");\n}\n\n# define YY_STACK_PRINT(Bottom, Top) \\\ndo { \\\n if (yydebug) \\\n yy_stack_print ((Bottom), (Top)); \\\n} while (0)\n\n\n/*------------------------------------------------.\n| Report that the YYRULE is going to be reduced. |\n`------------------------------------------------*/\n\nstatic void\nyy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule)\n{\n int yylno = yyrline[yyrule];\n int yynrhs = yyr2[yyrule];\n int yyi;\n YYFPRINTF (stderr, \"Reducing stack by rule %d (line %d):\\n\",\n yyrule - 1, yylno);\n /* The symbols being reduced. */\n for (yyi = 0; yyi < yynrhs; yyi++)\n {\n YYFPRINTF (stderr, \" $%d = \", yyi + 1);\n yy_symbol_print (stderr,\n yystos[+yyssp[yyi + 1 - yynrhs]],\n &yyvsp[(yyi + 1) - (yynrhs)]\n );\n YYFPRINTF (stderr, \"\\n\");\n }\n}\n\n# define YY_REDUCE_PRINT(Rule) \\\ndo { \\\n if (yydebug) \\\n yy_reduce_print (yyssp, yyvsp, Rule); \\\n} while (0)\n\n/* Nonzero means print parse trace. It is left uninitialized so that\n multiple parsers can coexist. */\nint yydebug;\n#else /* !SLEIGHDEBUG */\n# define YYDPRINTF(Args)\n# define YY_SYMBOL_PRINT(Title, Type, Value, Location)\n# define YY_STACK_PRINT(Bottom, Top)\n# define YY_REDUCE_PRINT(Rule)\n#endif /* !SLEIGHDEBUG */\n\n\n/* YYINITDEPTH -- initial size of the parser's stacks. */\n#ifndef YYINITDEPTH\n# define YYINITDEPTH 200\n#endif\n\n/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only\n if the built-in stack extension method is used).\n\n Do not make this value too large; the results are undefined if\n YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)\n evaluated with infinite-precision integer arithmetic. */\n\n#ifndef YYMAXDEPTH\n# define YYMAXDEPTH 10000\n#endif\n\n\n#if YYERROR_VERBOSE\n\n# ifndef yystrlen\n# if defined __GLIBC__ && defined _STRING_H\n# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S)))\n# else\n/* Return the length of YYSTR. */\nstatic YYPTRDIFF_T\nyystrlen (const char *yystr)\n{\n YYPTRDIFF_T yylen;\n for (yylen = 0; yystr[yylen]; yylen++)\n continue;\n return yylen;\n}\n# endif\n# endif\n\n# ifndef yystpcpy\n# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE\n# define yystpcpy stpcpy\n# else\n/* Copy YYSRC to YYDEST, returning the address of the terminating '\\0' in\n YYDEST. */\nstatic char *\nyystpcpy (char *yydest, const char *yysrc)\n{\n char *yyd = yydest;\n const char *yys = yysrc;\n\n while ((*yyd++ = *yys++) != '\\0')\n continue;\n\n return yyd - 1;\n}\n# endif\n# endif\n\n# ifndef yytnamerr\n/* Copy to YYRES the contents of YYSTR after stripping away unnecessary\n quotes and backslashes, so that it's suitable for yyerror. The\n heuristic is that double-quoting is unnecessary unless the string\n contains an apostrophe, a comma, or backslash (other than\n backslash-backslash). YYSTR is taken from yytname. If YYRES is\n null, do not copy; instead, return the length of what the result\n would have been. */\nstatic YYPTRDIFF_T\nyytnamerr (char *yyres, const char *yystr)\n{\n if (*yystr == '\"')\n {\n YYPTRDIFF_T yyn = 0;\n char const *yyp = yystr;\n\n for (;;)\n switch (*++yyp)\n {\n case '\\'':\n case ',':\n goto do_not_strip_quotes;\n\n case '\\\\':\n if (*++yyp != '\\\\')\n goto do_not_strip_quotes;\n else\n goto append;\n\n append:\n default:\n if (yyres)\n yyres[yyn] = *yyp;\n yyn++;\n break;\n\n case '\"':\n if (yyres)\n yyres[yyn] = '\\0';\n return yyn;\n }\n do_not_strip_quotes: ;\n }\n\n if (yyres)\n return yystpcpy (yyres, yystr) - yyres;\n else\n return yystrlen (yystr);\n}\n# endif\n\n/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message\n about the unexpected token YYTOKEN for the state stack whose top is\n YYSSP.\n\n Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is\n not large enough to hold the message. In that case, also set\n *YYMSG_ALLOC to the required number of bytes. Return 2 if the\n required number of bytes is too large to store. */\nstatic int\nyysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg,\n yy_state_t *yyssp, int yytoken)\n{\n enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };\n /* Internationalized format string. */\n const char *yyformat = YY_NULLPTR;\n /* Arguments of yyformat: reported tokens (one for the \"unexpected\",\n one per \"expected\"). */\n char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];\n /* Actual size of YYARG. */\n int yycount = 0;\n /* Cumulated lengths of YYARG. */\n YYPTRDIFF_T yysize = 0;\n\n /* There are many possibilities here to consider:\n - If this state is a consistent state with a default action, then\n the only way this function was invoked is if the default action\n is an error action. In that case, don't check for expected\n tokens because there are none.\n - The only way there can be no lookahead present (in yychar) is if\n this state is a consistent state with a default action. Thus,\n detecting the absence of a lookahead is sufficient to determine\n that there is no unexpected or expected token to report. In that\n case, just report a simple \"syntax error\".\n - Don't assume there isn't a lookahead just because this state is a\n consistent state with a default action. There might have been a\n previous inconsistent state, consistent state with a non-default\n action, or user semantic action that manipulated yychar.\n - Of course, the expected token list depends on states to have\n correct lookahead information, and it depends on the parser not\n to perform extra reductions after fetching a lookahead from the\n scanner and before detecting a syntax error. Thus, state merging\n (from LALR or IELR) and default reductions corrupt the expected\n token list. However, the list is correct for canonical LR with\n one exception: it will still contain any token that will not be\n accepted due to an error action in a later state.\n */\n if (yytoken != YYEMPTY)\n {\n int yyn = yypact[+*yyssp];\n YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);\n yysize = yysize0;\n yyarg[yycount++] = yytname[yytoken];\n if (!yypact_value_is_default (yyn))\n {\n /* Start YYX at -YYN if negative to avoid negative indexes in\n YYCHECK. In other words, skip the first -YYN actions for\n this state because they are default actions. */\n int yyxbegin = yyn < 0 ? -yyn : 0;\n /* Stay within bounds of both yycheck and yytname. */\n int yychecklim = YYLAST - yyn + 1;\n int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;\n int yyx;\n\n for (yyx = yyxbegin; yyx < yyxend; ++yyx)\n if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR\n && !yytable_value_is_error (yytable[yyx + yyn]))\n {\n if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)\n {\n yycount = 1;\n yysize = yysize0;\n break;\n }\n yyarg[yycount++] = yytname[yyx];\n {\n YYPTRDIFF_T yysize1\n = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);\n if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)\n yysize = yysize1;\n else\n return 2;\n }\n }\n }\n }\n\n switch (yycount)\n {\n# define YYCASE_(N, S) \\\n case N: \\\n yyformat = S; \\\n break\n default: /* Avoid compiler warnings. */\n YYCASE_(0, YY_(\"syntax error\"));\n YYCASE_(1, YY_(\"syntax error, unexpected %s\"));\n YYCASE_(2, YY_(\"syntax error, unexpected %s, expecting %s\"));\n YYCASE_(3, YY_(\"syntax error, unexpected %s, expecting %s or %s\"));\n YYCASE_(4, YY_(\"syntax error, unexpected %s, expecting %s or %s or %s\"));\n YYCASE_(5, YY_(\"syntax error, unexpected %s, expecting %s or %s or %s or %s\"));\n# undef YYCASE_\n }\n\n {\n /* Don't count the \"%s\"s in the final size, but reserve room for\n the terminator. */\n YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1;\n if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)\n yysize = yysize1;\n else\n return 2;\n }\n\n if (*yymsg_alloc < yysize)\n {\n *yymsg_alloc = 2 * yysize;\n if (! (yysize <= *yymsg_alloc\n && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))\n *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;\n return 1;\n }\n\n /* Avoid sprintf, as that infringes on the user's name space.\n Don't have undefined behavior even if the translation\n produced a string with the wrong number of \"%s\"s. */\n {\n char *yyp = *yymsg;\n int yyi = 0;\n while ((*yyp = *yyformat) != '\\0')\n if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)\n {\n yyp += yytnamerr (yyp, yyarg[yyi++]);\n yyformat += 2;\n }\n else\n {\n ++yyp;\n ++yyformat;\n }\n }\n return 0;\n}\n#endif /* YYERROR_VERBOSE */\n\n/*-----------------------------------------------.\n| Release the memory associated to this symbol. |\n`-----------------------------------------------*/\n\nstatic void\nyydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)\n{\n YYUSE (yyvaluep);\n if (!yymsg)\n yymsg = \"Deleting\";\n YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);\n\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n YYUSE (yytype);\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n\n\n/* The lookahead symbol. */\nint yychar;\n\n/* The semantic value of the lookahead symbol. */\nYYSTYPE yylval;\n/* Number of syntax errors so far. */\nint yynerrs;\n\n\n/*----------.\n| yyparse. |\n`----------*/\n\nint\nyyparse (void)\n{\n yy_state_fast_t yystate;\n /* Number of tokens to shift before error messages enabled. */\n int yyerrstatus;\n\n /* The stacks and their tools:\n 'yyss': related to states.\n 'yyvs': related to semantic values.\n\n Refer to the stacks through separate pointers, to allow yyoverflow\n to reallocate them elsewhere. */\n\n /* The state stack. */\n yy_state_t yyssa[YYINITDEPTH];\n yy_state_t *yyss;\n yy_state_t *yyssp;\n\n /* The semantic value stack. */\n YYSTYPE yyvsa[YYINITDEPTH];\n YYSTYPE *yyvs;\n YYSTYPE *yyvsp;\n\n YYPTRDIFF_T yystacksize;\n\n int yyn;\n int yyresult;\n /* Lookahead token as an internal (translated) token number. */\n int yytoken = 0;\n /* The variables used to return semantic value and location from the\n action routines. */\n YYSTYPE yyval;\n\n#if YYERROR_VERBOSE\n /* Buffer for error messages, and its allocated size. */\n char yymsgbuf[128];\n char *yymsg = yymsgbuf;\n YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf;\n#endif\n\n#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))\n\n /* The number of symbols on the RHS of the reduced rule.\n Keep to zero when no symbol should be popped. */\n int yylen = 0;\n\n yyssp = yyss = yyssa;\n yyvsp = yyvs = yyvsa;\n yystacksize = YYINITDEPTH;\n\n YYDPRINTF ((stderr, \"Starting parse\\n\"));\n\n yystate = 0;\n yyerrstatus = 0;\n yynerrs = 0;\n yychar = YYEMPTY; /* Cause a token to be read. */\n goto yysetstate;\n\n\n/*------------------------------------------------------------.\n| yynewstate -- push a new state, which is found in yystate. |\n`------------------------------------------------------------*/\nyynewstate:\n /* In all cases, when you get here, the value and location stacks\n have just been pushed. So pushing a state here evens the stacks. */\n yyssp++;\n\n\n/*--------------------------------------------------------------------.\n| yysetstate -- set current state (the top of the stack) to yystate. |\n`--------------------------------------------------------------------*/\nyysetstate:\n YYDPRINTF ((stderr, \"Entering state %d\\n\", yystate));\n YY_ASSERT (0 <= yystate && yystate < YYNSTATES);\n YY_IGNORE_USELESS_CAST_BEGIN\n *yyssp = YY_CAST (yy_state_t, yystate);\n YY_IGNORE_USELESS_CAST_END\n\n if (yyss + yystacksize - 1 <= yyssp)\n#if !defined yyoverflow && !defined YYSTACK_RELOCATE\n goto yyexhaustedlab;\n#else\n {\n /* Get the current used size of the three stacks, in elements. */\n YYPTRDIFF_T yysize = yyssp - yyss + 1;\n\n# if defined yyoverflow\n {\n /* Give user a chance to reallocate the stack. Use copies of\n these so that the &'s don't force the real ones into\n memory. */\n yy_state_t *yyss1 = yyss;\n YYSTYPE *yyvs1 = yyvs;\n\n /* Each stack pointer address is followed by the size of the\n data in use in that stack, in bytes. This used to be a\n conditional around just the two extra args, but that might\n be undefined if yyoverflow is a macro. */\n yyoverflow (YY_(\"memory exhausted\"),\n &yyss1, yysize * YYSIZEOF (*yyssp),\n &yyvs1, yysize * YYSIZEOF (*yyvsp),\n &yystacksize);\n yyss = yyss1;\n yyvs = yyvs1;\n }\n# else /* defined YYSTACK_RELOCATE */\n /* Extend the stack our own way. */\n if (YYMAXDEPTH <= yystacksize)\n goto yyexhaustedlab;\n yystacksize *= 2;\n if (YYMAXDEPTH < yystacksize)\n yystacksize = YYMAXDEPTH;\n\n {\n yy_state_t *yyss1 = yyss;\n union yyalloc *yyptr =\n YY_CAST (union yyalloc *,\n YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize))));\n if (! yyptr)\n goto yyexhaustedlab;\n YYSTACK_RELOCATE (yyss_alloc, yyss);\n YYSTACK_RELOCATE (yyvs_alloc, yyvs);\n# undef YYSTACK_RELOCATE\n if (yyss1 != yyssa)\n YYSTACK_FREE (yyss1);\n }\n# endif\n\n yyssp = yyss + yysize - 1;\n yyvsp = yyvs + yysize - 1;\n\n YY_IGNORE_USELESS_CAST_BEGIN\n YYDPRINTF ((stderr, \"Stack size increased to %ld\\n\",\n YY_CAST (long, yystacksize)));\n YY_IGNORE_USELESS_CAST_END\n\n if (yyss + yystacksize - 1 <= yyssp)\n YYABORT;\n }\n#endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */\n\n if (yystate == YYFINAL)\n YYACCEPT;\n\n goto yybackup;\n\n\n/*-----------.\n| yybackup. |\n`-----------*/\nyybackup:\n /* Do appropriate processing given the current state. Read a\n lookahead token if we need one and don't already have one. */\n\n /* First try to decide what to do without reference to lookahead token. */\n yyn = yypact[yystate];\n if (yypact_value_is_default (yyn))\n goto yydefault;\n\n /* Not known => get a lookahead token if don't already have one. */\n\n /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */\n if (yychar == YYEMPTY)\n {\n YYDPRINTF ((stderr, \"Reading a token: \"));\n yychar = yylex ();\n }\n\n if (yychar <= YYEOF)\n {\n yychar = yytoken = YYEOF;\n YYDPRINTF ((stderr, \"Now at end of input.\\n\"));\n }\n else\n {\n yytoken = YYTRANSLATE (yychar);\n YY_SYMBOL_PRINT (\"Next token is\", yytoken, &yylval, &yylloc);\n }\n\n /* If the proper action on seeing token YYTOKEN is to reduce or to\n detect an error, take that action. */\n yyn += yytoken;\n if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)\n goto yydefault;\n yyn = yytable[yyn];\n if (yyn <= 0)\n {\n if (yytable_value_is_error (yyn))\n goto yyerrlab;\n yyn = -yyn;\n goto yyreduce;\n }\n\n /* Count tokens shifted since error; after three, turn off error\n status. */\n if (yyerrstatus)\n yyerrstatus--;\n\n /* Shift the lookahead token. */\n YY_SYMBOL_PRINT (\"Shifting\", yytoken, &yylval, &yylloc);\n yystate = yyn;\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n *++yyvsp = yylval;\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n /* Discard the shifted token. */\n yychar = YYEMPTY;\n goto yynewstate;\n\n\n/*-----------------------------------------------------------.\n| yydefault -- do the default action for the current state. |\n`-----------------------------------------------------------*/\nyydefault:\n yyn = yydefact[yystate];\n if (yyn == 0)\n goto yyerrlab;\n goto yyreduce;\n\n\n/*-----------------------------.\n| yyreduce -- do a reduction. |\n`-----------------------------*/\nyyreduce:\n /* yyn is the number of a rule to reduce with. */\n yylen = yyr2[yyn];\n\n /* If YYLEN is nonzero, implement the default value of the action:\n '$$ = $1'.\n\n Otherwise, the following line sets YYVAL to garbage.\n This behavior is undocumented and Bison\n users should not rely upon it. Assigning to YYVAL\n unconditionally makes the parser a bit smaller, and it avoids a\n GCC warning that YYVAL may be used uninitialized. */\n yyval = yyvsp[1-yylen];\n\n\n YY_REDUCE_PRINT (yyn);\n switch (yyn)\n {\n case 19:\n { slgh->resetConstructors(); }\n break;\n\n case 20:\n { slgh->setEndian(1); }\n break;\n\n case 21:\n { slgh->setEndian(0); }\n break;\n\n case 22:\n { slgh->setAlignment(*(yyvsp[-1].i)); delete (yyvsp[-1].i); }\n break;\n\n case 23:\n {}\n break;\n\n case 24:\n { (yyval.tokensym) = slgh->defineToken((yyvsp[-3].str),(yyvsp[-1].i),0); }\n break;\n\n case 25:\n { (yyval.tokensym) = slgh->defineToken((yyvsp[-6].str),(yyvsp[-4].i),-1); }\n break;\n\n case 26:\n { (yyval.tokensym) = slgh->defineToken((yyvsp[-6].str),(yyvsp[-4].i),1); }\n break;\n\n case 27:\n { (yyval.tokensym) = (yyvsp[-1].tokensym); slgh->addTokenField((yyvsp[-1].tokensym),(yyvsp[0].fieldqual)); }\n break;\n\n case 28:\n { string errmsg=(yyvsp[0].anysym)->getName()+\": redefined as a token\"; slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 29:\n {}\n break;\n\n case 30:\n { (yyval.varsym) = (yyvsp[0].varsym); }\n break;\n\n case 31:\n { (yyval.varsym) = (yyvsp[-1].varsym); if (!slgh->addContextField( (yyvsp[-1].varsym), (yyvsp[0].fieldqual) ))\n { slgh->reportError(\"All context definitions must come before constructors\"); YYERROR; } }\n break;\n\n case 32:\n { (yyval.fieldqual) = new FieldQuality((yyvsp[-6].str),(yyvsp[-3].i),(yyvsp[-1].i)); }\n break;\n\n case 33:\n { delete (yyvsp[-3].i); delete (yyvsp[-1].i); string errmsg = (yyvsp[-6].anysym)->getName()+\": redefined as field\"; slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 34:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->signext = true; }\n break;\n\n case 35:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = true; }\n break;\n\n case 36:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = false; }\n break;\n\n case 37:\n { (yyval.fieldqual) = new FieldQuality((yyvsp[-6].str),(yyvsp[-3].i),(yyvsp[-1].i)); }\n break;\n\n case 38:\n { delete (yyvsp[-3].i); delete (yyvsp[-1].i); string errmsg = (yyvsp[-6].anysym)->getName()+\": redefined as field\"; slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 39:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->signext = true; }\n break;\n\n case 40:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->flow = false; }\n break;\n\n case 41:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = true; }\n break;\n\n case 42:\n { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = false; }\n break;\n\n case 43:\n { slgh->newSpace((yyvsp[-1].spacequal)); }\n break;\n\n case 44:\n { (yyval.spacequal) = new SpaceQuality(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 45:\n { string errmsg = (yyvsp[0].anysym)->getName()+\": redefined as space\"; slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 46:\n { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->type = SpaceQuality::ramtype; }\n break;\n\n case 47:\n { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->type = SpaceQuality::registertype; }\n break;\n\n case 48:\n { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->size = *(yyvsp[0].i); delete (yyvsp[0].i); }\n break;\n\n case 49:\n { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->wordsize = *(yyvsp[0].i); delete (yyvsp[0].i); }\n break;\n\n case 50:\n { (yyval.spacequal) = (yyvsp[-1].spacequal); (yyval.spacequal)->isdefault = true; }\n break;\n\n case 51:\n {\n slgh->defineVarnodes((yyvsp[-8].spacesym),(yyvsp[-5].i),(yyvsp[-2].i),(yyvsp[-1].strlist)); }\n break;\n\n case 52:\n { slgh->reportError(\"Parsed integer is too big (overflow)\"); YYERROR; }\n break;\n\n case 56:\n {\n slgh->defineBitrange((yyvsp[-7].str),(yyvsp[-5].varsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i); delete (yyvsp[-1].i); }\n break;\n\n case 57:\n { slgh->addUserOp((yyvsp[-1].strlist)); }\n break;\n\n case 58:\n { slgh->attachValues((yyvsp[-2].symlist),(yyvsp[-1].biglist)); }\n break;\n\n case 59:\n { slgh->attachNames((yyvsp[-2].symlist),(yyvsp[-1].strlist)); }\n break;\n\n case 60:\n { slgh->attachVarnodes((yyvsp[-2].symlist),(yyvsp[-1].symlist)); }\n break;\n\n case 61:\n { slgh->buildMacro((yyvsp[-3].macrosym),(yyvsp[-1].sem)); }\n break;\n\n case 62:\n { slgh->pushWith((yyvsp[-4].subtablesym),(yyvsp[-2].pateq),(yyvsp[-1].contop)); }\n break;\n\n case 66:\n { slgh->popWith(); }\n break;\n\n case 67:\n { (yyval.subtablesym) = (SubtableSymbol *)0; }\n break;\n\n case 68:\n { (yyval.subtablesym) = (yyvsp[0].subtablesym); }\n break;\n\n case 69:\n { (yyval.subtablesym) = slgh->newTable((yyvsp[0].str)); }\n break;\n\n case 70:\n { (yyval.pateq) = (PatternEquation *)0; }\n break;\n\n case 71:\n { (yyval.pateq) = (yyvsp[0].pateq); }\n break;\n\n case 72:\n { (yyval.macrosym) = slgh->createMacro((yyvsp[-3].str),(yyvsp[-1].strlist)); }\n break;\n\n case 73:\n { (yyval.sectionstart) = slgh->standaloneSection((yyvsp[-1].sem)); }\n break;\n\n case 74:\n { (yyval.sectionstart) = slgh->finalNamedSection((yyvsp[-2].sectionstart),(yyvsp[-1].sem)); }\n break;\n\n case 75:\n { (yyval.sectionstart) = (SectionVector *)0; }\n break;\n\n case 76:\n { slgh->buildConstructor((yyvsp[-4].construct),(yyvsp[-2].pateq),(yyvsp[-1].contop),(yyvsp[0].sectionstart)); }\n break;\n\n case 77:\n { slgh->buildConstructor((yyvsp[-4].construct),(yyvsp[-2].pateq),(yyvsp[-1].contop),(yyvsp[0].sectionstart)); }\n break;\n\n case 78:\n { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 79:\n { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 80:\n { (yyval.construct) = (yyvsp[-1].construct); if (slgh->isInRoot((yyvsp[-1].construct))) { (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); } else slgh->newOperand((yyvsp[-1].construct),(yyvsp[0].str)); }\n break;\n\n case 81:\n { (yyval.construct) = (yyvsp[-1].construct); if (!slgh->isInRoot((yyvsp[-1].construct))) { slgh->reportError(\"Unexpected '^' at start of print pieces\"); YYERROR; } }\n break;\n\n case 82:\n { (yyval.construct) = (yyvsp[-1].construct); }\n break;\n\n case 83:\n { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 84:\n { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 85:\n { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(string(\" \")); }\n break;\n\n case 86:\n { (yyval.construct) = (yyvsp[-1].construct); slgh->newOperand((yyvsp[-1].construct),(yyvsp[0].str)); }\n break;\n\n case 87:\n { (yyval.construct) = slgh->createConstructor((yyvsp[-1].subtablesym)); }\n break;\n\n case 88:\n { SubtableSymbol *sym=slgh->newTable((yyvsp[-1].str)); (yyval.construct) = slgh->createConstructor(sym); }\n break;\n\n case 89:\n { (yyval.construct) = slgh->createConstructor((SubtableSymbol *)0); }\n break;\n\n case 90:\n { (yyval.construct) = (yyvsp[-1].construct); }\n break;\n\n case 91:\n { (yyval.patexp) = new ConstantValue(*(yyvsp[0].big)); delete (yyvsp[0].big); }\n break;\n\n case 92:\n { if ((actionon==1)&&((yyvsp[0].famsym)->getType() != SleighSymbol::context_symbol))\n { string errmsg=\"Global symbol \"+(yyvsp[0].famsym)->getName(); errmsg += \" is not allowed in action expression\"; slgh->reportError(errmsg); } (yyval.patexp) = (yyvsp[0].famsym)->getPatternValue(); }\n break;\n\n case 93:\n { (yyval.patexp) = (yyvsp[0].specsym)->getPatternExpression(); }\n break;\n\n case 94:\n { (yyval.patexp) = (yyvsp[-1].patexp); }\n break;\n\n case 95:\n { (yyval.patexp) = new PlusExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 96:\n { (yyval.patexp) = new SubExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 97:\n { (yyval.patexp) = new MultExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 98:\n { (yyval.patexp) = new LeftShiftExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 99:\n { (yyval.patexp) = new RightShiftExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 100:\n { (yyval.patexp) = new AndExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 101:\n { (yyval.patexp) = new OrExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 102:\n { (yyval.patexp) = new XorExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 103:\n { (yyval.patexp) = new DivExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); }\n break;\n\n case 104:\n { (yyval.patexp) = new MinusExpression((yyvsp[0].patexp)); }\n break;\n\n case 105:\n { (yyval.patexp) = new NotExpression((yyvsp[0].patexp)); }\n break;\n\n case 107:\n { (yyval.pateq) = new EquationAnd((yyvsp[-2].pateq),(yyvsp[0].pateq)); }\n break;\n\n case 108:\n { (yyval.pateq) = new EquationOr((yyvsp[-2].pateq),(yyvsp[0].pateq)); }\n break;\n\n case 109:\n { (yyval.pateq) = new EquationCat((yyvsp[-2].pateq),(yyvsp[0].pateq)); }\n break;\n\n case 110:\n { (yyval.pateq) = new EquationLeftEllipsis((yyvsp[0].pateq)); }\n break;\n\n case 112:\n { (yyval.pateq) = new EquationRightEllipsis((yyvsp[-1].pateq)); }\n break;\n\n case 115:\n { (yyval.pateq) = (yyvsp[-1].pateq); }\n break;\n\n case 116:\n { (yyval.pateq) = new EqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); }\n break;\n\n case 117:\n { (yyval.pateq) = new NotEqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); }\n break;\n\n case 118:\n { (yyval.pateq) = new LessEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); }\n break;\n\n case 119:\n { (yyval.pateq) = new LessEqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); }\n break;\n\n case 120:\n { (yyval.pateq) = new GreaterEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); }\n break;\n\n case 121:\n { (yyval.pateq) = new GreaterEqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); }\n break;\n\n case 122:\n { (yyval.pateq) = slgh->constrainOperand((yyvsp[-2].operandsym),(yyvsp[0].patexp)); \n if ((yyval.pateq) == (PatternEquation *)0) \n { string errmsg=\"Constraining currently undefined operand \"+(yyvsp[-2].operandsym)->getName(); slgh->reportError(errmsg); } }\n break;\n\n case 123:\n { (yyval.pateq) = new OperandEquation((yyvsp[0].operandsym)->getIndex()); slgh->selfDefine((yyvsp[0].operandsym)); }\n break;\n\n case 124:\n { (yyval.pateq) = new UnconstrainedEquation((yyvsp[0].specsym)->getPatternExpression()); }\n break;\n\n case 125:\n { (yyval.pateq) = slgh->defineInvisibleOperand((yyvsp[0].famsym)); }\n break;\n\n case 126:\n { (yyval.pateq) = slgh->defineInvisibleOperand((yyvsp[0].subtablesym)); }\n break;\n\n case 127:\n { (yyval.contop) = (vector *)0; }\n break;\n\n case 128:\n { (yyval.contop) = (yyvsp[-1].contop); }\n break;\n\n case 129:\n { (yyval.contop) = new vector; }\n break;\n\n case 130:\n { (yyval.contop) = (yyvsp[-4].contop); if (!slgh->contextMod((yyvsp[-4].contop),(yyvsp[-3].contextsym),(yyvsp[-1].patexp))) { string errmsg=\"Cannot use 'inst_next' or 'inst_next2' to set context variable: \"+(yyvsp[-3].contextsym)->getName(); slgh->reportError(errmsg); YYERROR; } }\n break;\n\n case 131:\n { (yyval.contop) = (yyvsp[-7].contop); slgh->contextSet((yyvsp[-7].contop),(yyvsp[-4].famsym),(yyvsp[-2].contextsym)); }\n break;\n\n case 132:\n { (yyval.contop) = (yyvsp[-7].contop); slgh->contextSet((yyvsp[-7].contop),(yyvsp[-4].specsym),(yyvsp[-2].contextsym)); }\n break;\n\n case 133:\n { (yyval.contop) = (yyvsp[-4].contop); slgh->defineOperand((yyvsp[-3].operandsym),(yyvsp[-1].patexp)); }\n break;\n\n case 134:\n { string errmsg=\"Expecting context symbol, not \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 135:\n { (yyval.sectionsym) = slgh->newSectionSymbol( *(yyvsp[-1].str) ); delete (yyvsp[-1].str); }\n break;\n\n case 136:\n { (yyval.sectionsym) = (yyvsp[-1].sectionsym); }\n break;\n\n case 137:\n { (yyval.sectionstart) = slgh->firstNamedSection((yyvsp[-1].sem),(yyvsp[0].sectionsym)); }\n break;\n\n case 138:\n { (yyval.sectionstart) = (yyvsp[0].sectionstart); }\n break;\n\n case 139:\n { (yyval.sectionstart) = slgh->nextNamedSection((yyvsp[-2].sectionstart),(yyvsp[-1].sem),(yyvsp[0].sectionsym)); }\n break;\n\n case 140:\n { (yyval.sem) = (yyvsp[0].sem); if ((yyval.sem)->getOpvec().empty() && ((yyval.sem)->getResult() == (HandleTpl *)0)) slgh->recordNop(); }\n break;\n\n case 141:\n { (yyval.sem) = slgh->setResultVarnode((yyvsp[-3].sem),(yyvsp[-1].varnode)); }\n break;\n\n case 142:\n { (yyval.sem) = slgh->setResultStarVarnode((yyvsp[-4].sem),(yyvsp[-2].starqual),(yyvsp[-1].varnode)); }\n break;\n\n case 143:\n { string errmsg=\"Unknown export varnode: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 144:\n { string errmsg=\"Unknown pointer varnode: \"+*(yyvsp[0].str); delete (yyvsp[-1].starqual); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 145:\n { (yyval.sem) = slgh->enterSection(); }\n break;\n\n case 146:\n { (yyval.sem) = (yyvsp[-1].sem); if (!(yyval.sem)->addOpList(*(yyvsp[0].stmt))) { delete (yyvsp[0].stmt); slgh->reportError(\"Multiple delayslot declarations\"); YYERROR; } delete (yyvsp[0].stmt); }\n break;\n\n case 147:\n { (yyval.sem) = (yyvsp[-3].sem); slgh->pcode.newLocalDefinition((yyvsp[-1].str)); }\n break;\n\n case 148:\n { (yyval.sem) = (yyvsp[-5].sem); slgh->pcode.newLocalDefinition((yyvsp[-3].str),*(yyvsp[-1].i)); delete (yyvsp[-1].i); }\n break;\n\n case 149:\n { (yyvsp[-1].tree)->setOutput((yyvsp[-3].varnode)); (yyval.stmt) = ExprTree::toVector((yyvsp[-1].tree)); }\n break;\n\n case 150:\n { (yyval.stmt) = slgh->pcode.newOutput(true,(yyvsp[-1].tree),(yyvsp[-3].str)); }\n break;\n\n case 151:\n { (yyval.stmt) = slgh->pcode.newOutput(false,(yyvsp[-1].tree),(yyvsp[-3].str)); }\n break;\n\n case 152:\n { (yyval.stmt) = slgh->pcode.newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); }\n break;\n\n case 153:\n { (yyval.stmt) = slgh->pcode.newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); }\n break;\n\n case 154:\n { (yyval.stmt) = (vector *)0; string errmsg = \"Redefinition of symbol: \"+(yyvsp[-1].specsym)->getName(); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 155:\n { (yyval.stmt) = slgh->pcode.createStore((yyvsp[-4].starqual),(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 156:\n { (yyval.stmt) = slgh->pcode.createUserOpNoOut((yyvsp[-4].useropsym),(yyvsp[-2].param)); }\n break;\n\n case 157:\n { (yyval.stmt) = slgh->pcode.assignBitRange((yyvsp[-8].varnode),(uint4)*(yyvsp[-6].i),(uint4)*(yyvsp[-4].i),(yyvsp[-1].tree)); delete (yyvsp[-6].i), delete (yyvsp[-4].i); }\n break;\n\n case 158:\n { (yyval.stmt)=slgh->pcode.assignBitRange((yyvsp[-3].bitsym)->getParentSymbol()->getVarnode(),(yyvsp[-3].bitsym)->getBitOffset(),(yyvsp[-3].bitsym)->numBits(),(yyvsp[-1].tree)); }\n break;\n\n case 159:\n { delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); slgh->reportError(\"Illegal truncation on left-hand side of assignment\"); YYERROR; }\n break;\n\n case 160:\n { delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); slgh->reportError(\"Illegal subpiece on left-hand side of assignment\"); YYERROR; }\n break;\n\n case 161:\n { (yyval.stmt) = slgh->pcode.createOpConst(BUILD,(yyvsp[-1].operandsym)->getIndex()); }\n break;\n\n case 162:\n { (yyval.stmt) = slgh->createCrossBuild((yyvsp[-3].varnode),(yyvsp[-1].sectionsym)); }\n break;\n\n case 163:\n { (yyval.stmt) = slgh->createCrossBuild((yyvsp[-3].varnode),slgh->newSectionSymbol(*(yyvsp[-1].str))); delete (yyvsp[-1].str); }\n break;\n\n case 164:\n { (yyval.stmt) = slgh->pcode.createOpConst(DELAY_SLOT,*(yyvsp[-2].i)); delete (yyvsp[-2].i); }\n break;\n\n case 165:\n { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_BRANCH,new ExprTree((yyvsp[-1].varnode))); }\n break;\n\n case 166:\n { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_CBRANCH,new ExprTree((yyvsp[-1].varnode)),(yyvsp[-3].tree)); }\n break;\n\n case 167:\n { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_BRANCHIND,(yyvsp[-2].tree)); }\n break;\n\n case 168:\n { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_CALL,new ExprTree((yyvsp[-1].varnode))); }\n break;\n\n case 169:\n { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_CALLIND,(yyvsp[-2].tree)); }\n break;\n\n case 170:\n { slgh->reportError(\"Must specify an indirect parameter for return\"); YYERROR; }\n break;\n\n case 171:\n { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_RETURN,(yyvsp[-2].tree)); }\n break;\n\n case 172:\n { (yyval.stmt) = slgh->createMacroUse((yyvsp[-4].macrosym),(yyvsp[-2].param)); }\n break;\n\n case 173:\n { (yyval.stmt) = slgh->pcode.placeLabel( (yyvsp[0].labelsym) ); }\n break;\n\n case 174:\n { (yyval.tree) = new ExprTree((yyvsp[0].varnode)); }\n break;\n\n case 175:\n { (yyval.tree) = slgh->pcode.createLoad((yyvsp[-1].starqual),(yyvsp[0].tree)); }\n break;\n\n case 176:\n { (yyval.tree) = (yyvsp[-1].tree); }\n break;\n\n case 177:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 178:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 179:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 180:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 181:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 182:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 183:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 184:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 185:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESS,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 186:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 187:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 188:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESS,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 189:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_2COMP,(yyvsp[0].tree)); }\n break;\n\n case 190:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_NEGATE,(yyvsp[0].tree)); }\n break;\n\n case 191:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 192:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 193:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 194:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LEFT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 195:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_RIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 196:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SRIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 197:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 198:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 199:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SDIV,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 200:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_REM,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 201:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SREM,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 202:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_NEGATE,(yyvsp[0].tree)); }\n break;\n\n case 203:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 204:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 205:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 206:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 207:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 208:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 209:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 210:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 211:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); }\n break;\n\n case 212:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 213:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 214:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 215:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); }\n break;\n\n case 216:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_NEG,(yyvsp[0].tree)); }\n break;\n\n case 217:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_ABS,(yyvsp[-1].tree)); }\n break;\n\n case 218:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_SQRT,(yyvsp[-1].tree)); }\n break;\n\n case 219:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SEXT,(yyvsp[-1].tree)); }\n break;\n\n case 220:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_ZEXT,(yyvsp[-1].tree)); }\n break;\n\n case 221:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_CARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 222:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SCARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 223:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SBORROW,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 224:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_FLOAT2FLOAT,(yyvsp[-1].tree)); }\n break;\n\n case 225:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_INT2FLOAT,(yyvsp[-1].tree)); }\n break;\n\n case 226:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_NAN,(yyvsp[-1].tree)); }\n break;\n\n case 227:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_TRUNC,(yyvsp[-1].tree)); }\n break;\n\n case 228:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_CEIL,(yyvsp[-1].tree)); }\n break;\n\n case 229:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_FLOOR,(yyvsp[-1].tree)); }\n break;\n\n case 230:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_ROUND,(yyvsp[-1].tree)); }\n break;\n\n case 231:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_NEW,(yyvsp[-1].tree)); }\n break;\n\n case 232:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_NEW,(yyvsp[-3].tree),(yyvsp[-1].tree)); }\n break;\n\n case 233:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_POPCOUNT,(yyvsp[-1].tree)); }\n break;\n\n case 234:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_LZCOUNT,(yyvsp[-1].tree)); }\n break;\n\n case 235:\n { (yyval.tree) = slgh->pcode.createOp(CPUI_SUBPIECE,new ExprTree((yyvsp[-3].specsym)->getVarnode()),new ExprTree((yyvsp[-1].varnode))); }\n break;\n\n case 236:\n { (yyval.tree) = slgh->pcode.createBitRange((yyvsp[-2].specsym),0,(uint4)(*(yyvsp[0].i) * 8)); delete (yyvsp[0].i); }\n break;\n\n case 237:\n { (yyval.tree) = slgh->pcode.createBitRange((yyvsp[-5].specsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i), delete (yyvsp[-1].i); }\n break;\n\n case 238:\n { (yyval.tree)=slgh->pcode.createBitRange((yyvsp[0].bitsym)->getParentSymbol(),(yyvsp[0].bitsym)->getBitOffset(),(yyvsp[0].bitsym)->numBits()); }\n break;\n\n case 239:\n { (yyval.tree) = slgh->pcode.createUserOp((yyvsp[-3].useropsym),(yyvsp[-1].param)); }\n break;\n\n case 240:\n { if ((*(yyvsp[-1].param)).size() < 2) { string errmsg = \"Must at least two inputs to cpool\"; slgh->reportError(errmsg); YYERROR; } (yyval.tree) = slgh->pcode.createVariadic(CPUI_CPOOLREF,(yyvsp[-1].param)); }\n break;\n\n case 241:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl((yyvsp[-3].spacesym)->getSpace()); }\n break;\n\n case 242:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl((yyvsp[-1].spacesym)->getSpace()); }\n break;\n\n case 243:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl(slgh->getDefaultCodeSpace()); }\n break;\n\n case 244:\n { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl(slgh->getDefaultCodeSpace()); }\n break;\n\n case 245:\n { VarnodeTpl *sym = (yyvsp[0].specsym)->getVarnode(); (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; }\n break;\n\n case 246:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::j_curspace_size)); delete (yyvsp[0].i); }\n break;\n\n case 247:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); slgh->reportError(\"Parsed integer is too big (overflow)\"); }\n break;\n\n case 248:\n { (yyval.varnode) = (yyvsp[0].operandsym)->getVarnode(); (yyvsp[0].operandsym)->setCodeAddress(); }\n break;\n\n case 249:\n { AddrSpace *spc = (yyvsp[-1].spacesym)->getSpace(); (yyval.varnode) = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*(yyvsp[-3].i)),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete (yyvsp[-3].i); }\n break;\n\n case 250:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::j_relative,(yyvsp[0].labelsym)->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); (yyvsp[0].labelsym)->incrementRefCount(); }\n break;\n\n case 251:\n { string errmsg = \"Unknown jump destination: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 252:\n { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); }\n break;\n\n case 253:\n { (yyval.varnode) = (yyvsp[0].varnode); }\n break;\n\n case 254:\n { string errmsg = \"Unknown varnode parameter: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 255:\n { string errmsg = \"Subtable not attached to operand: \"+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 256:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::real,0)); delete (yyvsp[0].i); }\n break;\n\n case 257:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); slgh->reportError(\"Parsed integer is too big (overflow)\"); }\n break;\n\n case 258:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); }\n break;\n\n case 259:\n { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),0); }\n break;\n\n case 260:\n { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); }\n break;\n\n case 261:\n { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); }\n break;\n\n case 262:\n { string errmsg = \"Unknown assignment varnode: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 263:\n { string errmsg = \"Subtable not attached to operand: \"+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 264:\n { (yyval.labelsym) = (yyvsp[-1].labelsym); }\n break;\n\n case 265:\n { (yyval.labelsym) = slgh->pcode.defineLabel( (yyvsp[-1].str) ); }\n break;\n\n case 266:\n { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); }\n break;\n\n case 267:\n { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),0); }\n break;\n\n case 268:\n { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); }\n break;\n\n case 269:\n { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); }\n break;\n\n case 270:\n { string errmsg=\"Unknown export varnode: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 271:\n { string errmsg = \"Subtable not attached to operand: \"+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 272:\n { (yyval.famsym) = (yyvsp[0].valuesym); }\n break;\n\n case 273:\n { (yyval.famsym) = (yyvsp[0].valuemapsym); }\n break;\n\n case 274:\n { (yyval.famsym) = (yyvsp[0].contextsym); }\n break;\n\n case 275:\n { (yyval.famsym) = (yyvsp[0].namesym); }\n break;\n\n case 276:\n { (yyval.famsym) = (yyvsp[0].varlistsym); }\n break;\n\n case 277:\n { (yyval.specsym) = (yyvsp[0].varsym); }\n break;\n\n case 278:\n { (yyval.specsym) = (yyvsp[0].specsym); }\n break;\n\n case 279:\n { (yyval.specsym) = (yyvsp[0].operandsym); }\n break;\n\n case 280:\n { (yyval.specsym) = (yyvsp[0].specsym); }\n break;\n\n case 281:\n { (yyval.str) = new string; (*(yyval.str)) += (yyvsp[0].ch); }\n break;\n\n case 282:\n { (yyval.str) = (yyvsp[-1].str); (*(yyval.str)) += (yyvsp[0].ch); }\n break;\n\n case 283:\n { (yyval.biglist) = (yyvsp[-1].biglist); }\n break;\n\n case 284:\n { (yyval.biglist) = new vector; (yyval.biglist)->push_back(intb(*(yyvsp[0].i))); delete (yyvsp[0].i); }\n break;\n\n case 285:\n { (yyval.biglist) = new vector; (yyval.biglist)->push_back(-intb(*(yyvsp[0].i))); delete (yyvsp[0].i); }\n break;\n\n case 286:\n { (yyval.biglist) = new vector; (yyval.biglist)->push_back(intb(*(yyvsp[0].i))); delete (yyvsp[0].i); }\n break;\n\n case 287:\n { (yyval.biglist) = new vector; (yyval.biglist)->push_back(-intb(*(yyvsp[0].i))); delete (yyvsp[0].i); }\n break;\n\n case 288:\n { if (*(yyvsp[0].str)!=\"_\") { string errmsg = \"Expecting integer but saw: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n (yyval.biglist) = new vector; (yyval.biglist)->push_back((intb)0xBADBEEF); delete (yyvsp[0].str); }\n break;\n\n case 289:\n { (yyval.biglist) = (yyvsp[-1].biglist); (yyval.biglist)->push_back(intb(*(yyvsp[0].i))); delete (yyvsp[0].i); }\n break;\n\n case 290:\n { (yyval.biglist) = (yyvsp[-2].biglist); (yyval.biglist)->push_back(-intb(*(yyvsp[0].i))); delete (yyvsp[0].i); }\n break;\n\n case 291:\n { if (*(yyvsp[0].str)!=\"_\") { string errmsg = \"Expecting integer but saw: \"+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n (yyval.biglist) = (yyvsp[-1].biglist); (yyval.biglist)->push_back((intb)0xBADBEEF); delete (yyvsp[0].str); }\n break;\n\n case 292:\n { (yyval.strlist) = (yyvsp[-1].strlist); }\n break;\n\n case 293:\n { (yyval.strlist) = new vector; (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 294:\n { (yyval.strlist) = new vector; (yyval.strlist)->push_back( *(yyvsp[0].str) ); delete (yyvsp[0].str); }\n break;\n\n case 295:\n { (yyval.strlist) = (yyvsp[-1].strlist); (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 296:\n { string errmsg = (yyvsp[0].anysym)->getName()+\": redefined\"; slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 297:\n { (yyval.strlist) = (yyvsp[-1].strlist); }\n break;\n\n case 298:\n { (yyval.strlist) = new vector; (yyval.strlist)->push_back( *(yyvsp[0].str) ); delete (yyvsp[0].str); }\n break;\n\n case 299:\n { (yyval.strlist) = new vector; (yyval.strlist)->push_back( (yyvsp[0].anysym)->getName() ); }\n break;\n\n case 300:\n { (yyval.strlist) = (yyvsp[-1].strlist); (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 301:\n { (yyval.strlist) = (yyvsp[-1].strlist); (yyval.strlist)->push_back((yyvsp[0].anysym)->getName()); }\n break;\n\n case 302:\n { (yyval.symlist) = (yyvsp[-1].symlist); }\n break;\n\n case 303:\n { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].valuesym)); }\n break;\n\n case 304:\n { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].contextsym)); }\n break;\n\n case 305:\n { (yyval.symlist) = new vector; (yyval.symlist)->push_back( (yyvsp[0].valuesym) ); }\n break;\n\n case 306:\n { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].contextsym)); }\n break;\n\n case 307:\n { (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((yyvsp[0].valuesym)); }\n break;\n\n case 308:\n { (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((yyvsp[0].contextsym)); }\n break;\n\n case 309:\n { string errmsg = *(yyvsp[0].str)+\": is not a value pattern\"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n break;\n\n case 310:\n { (yyval.symlist) = (yyvsp[-1].symlist); }\n break;\n\n case 311:\n { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].varsym)); }\n break;\n\n case 312:\n { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].varsym)); }\n break;\n\n case 313:\n { if (*(yyvsp[0].str)!=\"_\") { string errmsg = *(yyvsp[0].str)+\": is not a varnode symbol\"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n\t\t\t\t (yyval.symlist) = new vector; (yyval.symlist)->push_back((SleighSymbol *)0); delete (yyvsp[0].str); }\n break;\n\n case 314:\n { (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((yyvsp[0].varsym)); }\n break;\n\n case 315:\n { if (*(yyvsp[0].str)!=\"_\") { string errmsg = *(yyvsp[0].str)+\": is not a varnode symbol\"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; }\n (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((SleighSymbol *)0); delete (yyvsp[0].str); }\n break;\n\n case 316:\n { (yyval.param) = new vector; }\n break;\n\n case 317:\n { (yyval.param) = new vector; (yyval.param)->push_back((yyvsp[0].tree)); }\n break;\n\n case 318:\n { (yyval.param) = (yyvsp[-2].param); (yyval.param)->push_back((yyvsp[0].tree)); }\n break;\n\n case 319:\n { (yyval.strlist) = new vector; }\n break;\n\n case 320:\n { (yyval.strlist) = new vector; (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 321:\n { (yyval.strlist) = (yyvsp[-2].strlist); (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n break;\n\n case 322:\n { (yyval.anysym) = (yyvsp[0].spacesym); }\n break;\n\n case 323:\n { (yyval.anysym) = (yyvsp[0].sectionsym); }\n break;\n\n case 324:\n { (yyval.anysym) = (yyvsp[0].tokensym); }\n break;\n\n case 325:\n { (yyval.anysym) = (yyvsp[0].useropsym); }\n break;\n\n case 326:\n { (yyval.anysym) = (yyvsp[0].macrosym); }\n break;\n\n case 327:\n { (yyval.anysym) = (yyvsp[0].subtablesym); }\n break;\n\n case 328:\n { (yyval.anysym) = (yyvsp[0].valuesym); }\n break;\n\n case 329:\n { (yyval.anysym) = (yyvsp[0].valuemapsym); }\n break;\n\n case 330:\n { (yyval.anysym) = (yyvsp[0].contextsym); }\n break;\n\n case 331:\n { (yyval.anysym) = (yyvsp[0].namesym); }\n break;\n\n case 332:\n { (yyval.anysym) = (yyvsp[0].varsym); }\n break;\n\n case 333:\n { (yyval.anysym) = (yyvsp[0].varlistsym); }\n break;\n\n case 334:\n { (yyval.anysym) = (yyvsp[0].operandsym); }\n break;\n\n case 335:\n { (yyval.anysym) = (yyvsp[0].specsym); }\n break;\n\n case 336:\n { (yyval.anysym) = (yyvsp[0].bitsym); }\n break;\n\n\n\n default: break;\n }\n /* User semantic actions sometimes alter yychar, and that requires\n that yytoken be updated with the new translation. We take the\n approach of translating immediately before every use of yytoken.\n One alternative is translating here after every semantic action,\n but that translation would be missed if the semantic action invokes\n YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or\n if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an\n incorrect destructor might then be invoked immediately. In the\n case of YYERROR or YYBACKUP, subsequent parser actions might lead\n to an incorrect destructor call or verbose syntax error message\n before the lookahead is translated. */\n YY_SYMBOL_PRINT (\"-> $$ =\", yyr1[yyn], &yyval, &yyloc);\n\n YYPOPSTACK (yylen);\n yylen = 0;\n YY_STACK_PRINT (yyss, yyssp);\n\n *++yyvsp = yyval;\n\n /* Now 'shift' the result of the reduction. Determine what state\n that goes to, based on the state we popped back to and the rule\n number reduced by. */\n {\n const int yylhs = yyr1[yyn] - YYNTOKENS;\n const int yyi = yypgoto[yylhs] + *yyssp;\n yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp\n ? yytable[yyi]\n : yydefgoto[yylhs]);\n }\n\n goto yynewstate;\n\n\n/*--------------------------------------.\n| yyerrlab -- here on detecting error. |\n`--------------------------------------*/\nyyerrlab:\n /* Make sure we have latest lookahead translation. See comments at\n user semantic actions for why this is necessary. */\n yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);\n\n /* If not already recovering from an error, report this error. */\n if (!yyerrstatus)\n {\n ++yynerrs;\n#if ! YYERROR_VERBOSE\n yyerror (YY_(\"syntax error\"));\n#else\n# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \\\n yyssp, yytoken)\n {\n char const *yymsgp = YY_(\"syntax error\");\n int yysyntax_error_status;\n yysyntax_error_status = YYSYNTAX_ERROR;\n if (yysyntax_error_status == 0)\n yymsgp = yymsg;\n else if (yysyntax_error_status == 1)\n {\n if (yymsg != yymsgbuf)\n YYSTACK_FREE (yymsg);\n yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc)));\n if (!yymsg)\n {\n yymsg = yymsgbuf;\n yymsg_alloc = sizeof yymsgbuf;\n yysyntax_error_status = 2;\n }\n else\n {\n yysyntax_error_status = YYSYNTAX_ERROR;\n yymsgp = yymsg;\n }\n }\n yyerror (yymsgp);\n if (yysyntax_error_status == 2)\n goto yyexhaustedlab;\n }\n# undef YYSYNTAX_ERROR\n#endif\n }\n\n\n\n if (yyerrstatus == 3)\n {\n /* If just tried and failed to reuse lookahead token after an\n error, discard it. */\n\n if (yychar <= YYEOF)\n {\n /* Return failure if at end of input. */\n if (yychar == YYEOF)\n YYABORT;\n }\n else\n {\n yydestruct (\"Error: discarding\",\n yytoken, &yylval);\n yychar = YYEMPTY;\n }\n }\n\n /* Else will try to reuse lookahead token after shifting the error\n token. */\n goto yyerrlab1;\n\n\n/*---------------------------------------------------.\n| yyerrorlab -- error raised explicitly by YYERROR. |\n`---------------------------------------------------*/\nyyerrorlab:\n /* Pacify compilers when the user code never invokes YYERROR and the\n label yyerrorlab therefore never appears in user code. */\n if (0)\n YYERROR;\n\n /* Do not reclaim the symbols of the rule whose action triggered\n this YYERROR. */\n YYPOPSTACK (yylen);\n yylen = 0;\n YY_STACK_PRINT (yyss, yyssp);\n yystate = *yyssp;\n goto yyerrlab1;\n\n\n/*-------------------------------------------------------------.\n| yyerrlab1 -- common code for both syntax error and YYERROR. |\n`-------------------------------------------------------------*/\nyyerrlab1:\n yyerrstatus = 3; /* Each real token shifted decrements this. */\n\n for (;;)\n {\n yyn = yypact[yystate];\n if (!yypact_value_is_default (yyn))\n {\n yyn += YYTERROR;\n if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)\n {\n yyn = yytable[yyn];\n if (0 < yyn)\n break;\n }\n }\n\n /* Pop the current state because it cannot handle the error token. */\n if (yyssp == yyss)\n YYABORT;\n\n\n yydestruct (\"Error: popping\",\n yystos[yystate], yyvsp);\n YYPOPSTACK (1);\n yystate = *yyssp;\n YY_STACK_PRINT (yyss, yyssp);\n }\n\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n *++yyvsp = yylval;\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n\n /* Shift the error token. */\n YY_SYMBOL_PRINT (\"Shifting\", yystos[yyn], yyvsp, yylsp);\n\n yystate = yyn;\n goto yynewstate;\n\n\n/*-------------------------------------.\n| yyacceptlab -- YYACCEPT comes here. |\n`-------------------------------------*/\nyyacceptlab:\n yyresult = 0;\n goto yyreturn;\n\n\n/*-----------------------------------.\n| yyabortlab -- YYABORT comes here. |\n`-----------------------------------*/\nyyabortlab:\n yyresult = 1;\n goto yyreturn;\n\n\n#if !defined yyoverflow || YYERROR_VERBOSE\n/*-------------------------------------------------.\n| yyexhaustedlab -- memory exhaustion comes here. |\n`-------------------------------------------------*/\nyyexhaustedlab:\n yyerror (YY_(\"memory exhausted\"));\n yyresult = 2;\n /* Fall through. */\n#endif\n\n\n/*-----------------------------------------------------.\n| yyreturn -- parsing is finished, return the result. |\n`-----------------------------------------------------*/\nyyreturn:\n if (yychar != YYEMPTY)\n {\n /* Make sure we have latest lookahead translation. See comments at\n user semantic actions for why this is necessary. */\n yytoken = YYTRANSLATE (yychar);\n yydestruct (\"Cleanup: discarding lookahead\",\n yytoken, &yylval);\n }\n /* Do not reclaim the symbols of the rule whose action triggered\n this YYABORT or YYACCEPT. */\n YYPOPSTACK (yylen);\n YY_STACK_PRINT (yyss, yyssp);\n while (yyssp != yyss)\n {\n yydestruct (\"Cleanup: popping\",\n yystos[+*yyssp], yyvsp);\n YYPOPSTACK (1);\n }\n#ifndef yyoverflow\n if (yyss != yyssa)\n YYSTACK_FREE (yyss);\n#endif\n#if YYERROR_VERBOSE\n if (yymsg != yymsgbuf)\n YYSTACK_FREE (yymsg);\n#endif\n return yyresult;\n}\n\n\nint sleigherror(const char *s)\n\n{\n slgh->reportError(s);\n return 0;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/slghparse.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/* A Bison parser, made by GNU Bison 3.5.1. */\n\n/* Bison interface for Yacc-like parsers in C\n\n Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation,\n Inc.\n\n This program is free software: you can redistribute it and/or modify\n it under the terms of the GNU General Public License as published by\n the Free Software Foundation, either version 3 of the License, or\n (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program. If not, see . */\n\n/* As a special exception, you may create a larger work that contains\n part or all of the Bison parser skeleton and distribute that work\n under terms of your choice, so long as that work isn't itself a\n parser generator using the skeleton or a modified version thereof\n as a parser skeleton. Alternatively, if you modify or redistribute\n the parser skeleton itself, you may (at your option) remove this\n special exception, which will cause the skeleton and the resulting\n Bison output files to be licensed under the GNU General Public\n License without this special exception.\n\n This special exception was added by the Free Software Foundation in\n version 2.2 of Bison. */\n\n/* Undocumented macros, especially those whose name start with YY_,\n are private implementation details. Do not rely on them. */\n\n#ifndef YY_SLEIGH_SLGHPARSE_HH_INCLUDED\n# define YY_SLEIGH_SLGHPARSE_HH_INCLUDED\n/* Debug traces. */\n#ifndef SLEIGHDEBUG\n# if defined YYDEBUG\n#if YYDEBUG\n# define SLEIGHDEBUG 1\n# else\n# define SLEIGHDEBUG 0\n# endif\n# else /* ! defined YYDEBUG */\n# define SLEIGHDEBUG 0\n# endif /* ! defined YYDEBUG */\n#endif /* ! defined SLEIGHDEBUG */\n#if SLEIGHDEBUG\nextern int sleighdebug;\n#endif\n\n/* Token type. */\n#ifndef SLEIGHTOKENTYPE\n# define SLEIGHTOKENTYPE\n enum sleightokentype\n {\n OP_BOOL_OR = 258,\n OP_BOOL_AND = 259,\n OP_BOOL_XOR = 260,\n OP_OR = 261,\n OP_XOR = 262,\n OP_AND = 263,\n OP_EQUAL = 264,\n OP_NOTEQUAL = 265,\n OP_FEQUAL = 266,\n OP_FNOTEQUAL = 267,\n OP_GREATEQUAL = 268,\n OP_LESSEQUAL = 269,\n OP_SLESS = 270,\n OP_SGREATEQUAL = 271,\n OP_SLESSEQUAL = 272,\n OP_SGREAT = 273,\n OP_FLESS = 274,\n OP_FGREAT = 275,\n OP_FLESSEQUAL = 276,\n OP_FGREATEQUAL = 277,\n OP_LEFT = 278,\n OP_RIGHT = 279,\n OP_SRIGHT = 280,\n OP_FADD = 281,\n OP_FSUB = 282,\n OP_SDIV = 283,\n OP_SREM = 284,\n OP_FMULT = 285,\n OP_FDIV = 286,\n OP_ZEXT = 287,\n OP_CARRY = 288,\n OP_BORROW = 289,\n OP_SEXT = 290,\n OP_SCARRY = 291,\n OP_SBORROW = 292,\n OP_NAN = 293,\n OP_ABS = 294,\n OP_SQRT = 295,\n OP_CEIL = 296,\n OP_FLOOR = 297,\n OP_ROUND = 298,\n OP_INT2FLOAT = 299,\n OP_FLOAT2FLOAT = 300,\n OP_TRUNC = 301,\n OP_CPOOLREF = 302,\n OP_NEW = 303,\n OP_POPCOUNT = 304,\n OP_LZCOUNT = 305,\n BADINTEGER = 306,\n GOTO_KEY = 307,\n CALL_KEY = 308,\n RETURN_KEY = 309,\n IF_KEY = 310,\n DEFINE_KEY = 311,\n ATTACH_KEY = 312,\n MACRO_KEY = 313,\n SPACE_KEY = 314,\n TYPE_KEY = 315,\n RAM_KEY = 316,\n DEFAULT_KEY = 317,\n REGISTER_KEY = 318,\n ENDIAN_KEY = 319,\n WITH_KEY = 320,\n ALIGN_KEY = 321,\n OP_UNIMPL = 322,\n TOKEN_KEY = 323,\n SIGNED_KEY = 324,\n NOFLOW_KEY = 325,\n HEX_KEY = 326,\n DEC_KEY = 327,\n BIG_KEY = 328,\n LITTLE_KEY = 329,\n SIZE_KEY = 330,\n WORDSIZE_KEY = 331,\n OFFSET_KEY = 332,\n NAMES_KEY = 333,\n VALUES_KEY = 334,\n VARIABLES_KEY = 335,\n PCODEOP_KEY = 336,\n IS_KEY = 337,\n LOCAL_KEY = 338,\n DELAYSLOT_KEY = 339,\n CROSSBUILD_KEY = 340,\n EXPORT_KEY = 341,\n BUILD_KEY = 342,\n CONTEXT_KEY = 343,\n ELLIPSIS_KEY = 344,\n GLOBALSET_KEY = 345,\n BITRANGE_KEY = 346,\n CHAR = 347,\n INTEGER = 348,\n INTB = 349,\n STRING = 350,\n SYMBOLSTRING = 351,\n SPACESYM = 352,\n SECTIONSYM = 353,\n TOKENSYM = 354,\n USEROPSYM = 355,\n VALUESYM = 356,\n VALUEMAPSYM = 357,\n CONTEXTSYM = 358,\n NAMESYM = 359,\n VARSYM = 360,\n BITSYM = 361,\n SPECSYM = 362,\n VARLISTSYM = 363,\n OPERANDSYM = 364,\n JUMPSYM = 365,\n MACROSYM = 366,\n LABELSYM = 367,\n SUBTABLESYM = 368\n };\n#endif\n\n/* Value type. */\n#if ! defined SLEIGHSTYPE && ! defined SLEIGHSTYPE_IS_DECLARED\nunion SLEIGHSTYPE\n{\n\n char ch;\n uintb *i;\n intb *big;\n string *str;\n vector *strlist;\n vector *biglist;\n vector *param;\n SpaceQuality *spacequal;\n FieldQuality *fieldqual;\n StarQuality *starqual;\n VarnodeTpl *varnode;\n ExprTree *tree;\n vector *stmt;\n ConstructTpl *sem;\n SectionVector *sectionstart;\n Constructor *construct;\n PatternEquation *pateq;\n PatternExpression *patexp;\n\n vector *symlist;\n vector *contop;\n SleighSymbol *anysym;\n SpaceSymbol *spacesym;\n SectionSymbol *sectionsym;\n TokenSymbol *tokensym;\n UserOpSymbol *useropsym;\n MacroSymbol *macrosym;\n LabelSymbol *labelsym;\n SubtableSymbol *subtablesym;\n OperandSymbol *operandsym;\n VarnodeListSymbol *varlistsym;\n VarnodeSymbol *varsym;\n BitrangeSymbol *bitsym;\n NameSymbol *namesym;\n ValueSymbol *valuesym;\n ValueMapSymbol *valuemapsym;\n ContextSymbol *contextsym;\n FamilySymbol *famsym;\n SpecificSymbol *specsym;\n\n\n};\ntypedef union SLEIGHSTYPE SLEIGHSTYPE;\n# define SLEIGHSTYPE_IS_TRIVIAL 1\n# define SLEIGHSTYPE_IS_DECLARED 1\n#endif\n\n\nextern SLEIGHSTYPE sleighlval;\n\nint sleighparse (void);\n\n#endif /* !YY_SLEIGH_SLGHPARSE_HH_INCLUDED */\n" }, { "path": "pypcode/sleigh/slghparse.y", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n%define api.prefix {sleigh}\n%{\n#include \"slgh_compile.hh\"\n\nextern FILE *sleighin;\nextern int sleighlex(void);\n\nnamespace ghidra {\n\nextern SleighCompile *slgh;\nextern int4 actionon;\nextern int sleighdebug;\nextern int sleigherror(const char *str );\n%}\n\n%union {\n char ch;\n uintb *i;\n intb *big;\n string *str;\n vector *strlist;\n vector *biglist;\n vector *param;\n SpaceQuality *spacequal;\n FieldQuality *fieldqual;\n StarQuality *starqual;\n VarnodeTpl *varnode;\n ExprTree *tree;\n vector *stmt;\n ConstructTpl *sem;\n SectionVector *sectionstart;\n Constructor *construct;\n PatternEquation *pateq;\n PatternExpression *patexp;\n\n vector *symlist;\n vector *contop;\n SleighSymbol *anysym;\n SpaceSymbol *spacesym;\n SectionSymbol *sectionsym;\n TokenSymbol *tokensym;\n UserOpSymbol *useropsym;\n MacroSymbol *macrosym;\n LabelSymbol *labelsym;\n SubtableSymbol *subtablesym;\n OperandSymbol *operandsym;\n VarnodeListSymbol *varlistsym;\n VarnodeSymbol *varsym;\n BitrangeSymbol *bitsym;\n NameSymbol *namesym;\n ValueSymbol *valuesym;\n ValueMapSymbol *valuemapsym;\n ContextSymbol *contextsym;\n FamilySymbol *famsym;\n SpecificSymbol *specsym;\n}\n\n%expect 5\n// Conflicts\n// 2 charstring conflicts (do we lump CHARs together before appending to constructprint)\n// resolved by shifting which lumps before appending (best solution)\n// 1 integervarnode ':' conflict (does ':' apply to INTEGER or varnode)\n// resolved by shifting which applies ':' to INTEGER (best solution)\n// 2 statement -> STRING . conflicts (STRING might be mislabelled varnode, or temporary declaration)\n// resolved by shifting which means assume this is a temporary declaration\n\n%left OP_BOOL_OR\n%left OP_BOOL_AND OP_BOOL_XOR\n%left '|' OP_OR\n%left ';'\n%left '^' OP_XOR\n%left '&' OP_AND\n%left OP_EQUAL OP_NOTEQUAL OP_FEQUAL OP_FNOTEQUAL\n%nonassoc '<' '>' OP_GREATEQUAL OP_LESSEQUAL OP_SLESS OP_SGREATEQUAL OP_SLESSEQUAL OP_SGREAT OP_FLESS OP_FGREAT OP_FLESSEQUAL OP_FGREATEQUAL\n%left OP_LEFT OP_RIGHT OP_SRIGHT\n%left '+' '-' OP_FADD OP_FSUB\n%left '*' '/' '%' OP_SDIV OP_SREM OP_FMULT OP_FDIV\n%right '!' '~'\n%token OP_ZEXT OP_CARRY OP_BORROW OP_SEXT OP_SCARRY OP_SBORROW OP_NAN OP_ABS\n%token OP_SQRT OP_CEIL OP_FLOOR OP_ROUND OP_INT2FLOAT OP_FLOAT2FLOAT\n%token OP_TRUNC OP_CPOOLREF OP_NEW OP_POPCOUNT OP_LZCOUNT\n\n%token BADINTEGER GOTO_KEY CALL_KEY RETURN_KEY IF_KEY\n%token DEFINE_KEY ATTACH_KEY MACRO_KEY SPACE_KEY TYPE_KEY RAM_KEY DEFAULT_KEY\n%token REGISTER_KEY ENDIAN_KEY WITH_KEY ALIGN_KEY OP_UNIMPL\n%token TOKEN_KEY SIGNED_KEY NOFLOW_KEY HEX_KEY DEC_KEY BIG_KEY LITTLE_KEY\n%token SIZE_KEY WORDSIZE_KEY OFFSET_KEY NAMES_KEY VALUES_KEY VARIABLES_KEY PCODEOP_KEY IS_KEY LOCAL_KEY\n%token DELAYSLOT_KEY CROSSBUILD_KEY EXPORT_KEY BUILD_KEY CONTEXT_KEY ELLIPSIS_KEY GLOBALSET_KEY BITRANGE_KEY\n\n%token CHAR\n%token INTEGER\n%token INTB\n%token STRING SYMBOLSTRING\n%token SPACESYM\n%token SECTIONSYM\n%token TOKENSYM\n%token USEROPSYM\n%token VALUESYM\n%token VALUEMAPSYM\n%token CONTEXTSYM\n%token NAMESYM\n%token VARSYM\n%token BITSYM\n%token SPECSYM\n%token VARLISTSYM\n%token OPERANDSYM\n%token JUMPSYM\n%token MACROSYM\n%token LABELSYM\n%token SUBTABLESYM\n\n%type macrostart\n%type paramlist\n%type rtl rtlmid\n%type rtlbody rtlfirstsection rtlcontinue\n%type statement\n%type expr\n%type varnode integervarnode exportvarnode lhsvarnode jumpdest\n%type label\n%type pequation bitpat_or_nil elleq ellrt atomic constraint\n%type pexpression\n%type charstring\n%type constructprint subtablestart\n%type section_def\n%type contextprop\n%type tokenprop\n%type spaceprop\n%type fielddef contextfielddef\n%type sizedstar\n%type stringlist stringpart anystringlist anystringpart oplist\n%type intblist intbpart\n%type valuelist valuepart varlist varpart\n%type contextlist contextblock\n%type anysymbol\n%type familysymbol\n%type specificsymbol\n%type id_or_nil\n\n%%\nspec: endiandef\n | spec aligndef\n | spec definition\n | spec constructorlike\n ;\ndefinition: tokendef\n | contextdef\n | spacedef\n | varnodedef\n | bitrangedef\n | pcodeopdef\n | valueattach\n | nameattach\n | varattach\n | error ';'\n ;\nconstructorlike: constructor\n | macrodef\n | withblock\n | error '}' { slgh->resetConstructors(); }\n ;\nendiandef: DEFINE_KEY ENDIAN_KEY '=' BIG_KEY ';' { slgh->setEndian(1); }\n | DEFINE_KEY ENDIAN_KEY '=' LITTLE_KEY ';' { slgh->setEndian(0); }\n ;\naligndef: DEFINE_KEY ALIGN_KEY '=' INTEGER ';' { slgh->setAlignment(*$4); delete $4; }\n ;\ntokendef: tokenprop ';' {}\n ;\ntokenprop: DEFINE_KEY TOKEN_KEY STRING '(' INTEGER ')' { $$ = slgh->defineToken($3,$5,0); }\n | DEFINE_KEY TOKEN_KEY STRING '(' INTEGER ')' ENDIAN_KEY '=' LITTLE_KEY { $$ = slgh->defineToken($3,$5,-1); }\n | DEFINE_KEY TOKEN_KEY STRING '(' INTEGER ')' ENDIAN_KEY '=' BIG_KEY { $$ = slgh->defineToken($3,$5,1); }\n | tokenprop fielddef\t\t { $$ = $1; slgh->addTokenField($1,$2); }\n | DEFINE_KEY TOKEN_KEY anysymbol { string errmsg=$3->getName()+\": redefined as a token\"; slgh->reportError(errmsg); YYERROR; }\n ;\ncontextdef: contextprop ';' {}\n ;\ncontextprop: DEFINE_KEY CONTEXT_KEY VARSYM { $$ = $3; }\n | contextprop contextfielddef\t\t { $$ = $1; if (!slgh->addContextField( $1, $2 ))\n { slgh->reportError(\"All context definitions must come before constructors\"); YYERROR; } }\n ;\nfielddef: STRING '=' '(' INTEGER ',' INTEGER ')' { $$ = new FieldQuality($1,$4,$6); }\n | anysymbol '=' '(' INTEGER ',' INTEGER ')' { delete $4; delete $6; string errmsg = $1->getName()+\": redefined as field\"; slgh->reportError(errmsg); YYERROR; }\n | fielddef SIGNED_KEY\t\t\t{ $$ = $1; $$->signext = true; }\n | fielddef HEX_KEY\t\t\t{ $$ = $1; $$->hex = true; }\n | fielddef DEC_KEY\t\t\t{ $$ = $1; $$->hex = false; }\n ;\ncontextfielddef: STRING '=' '(' INTEGER ',' INTEGER ')' { $$ = new FieldQuality($1,$4,$6); }\n | anysymbol '=' '(' INTEGER ',' INTEGER ')' { delete $4; delete $6; string errmsg = $1->getName()+\": redefined as field\"; slgh->reportError(errmsg); YYERROR; }\n | contextfielddef SIGNED_KEY\t\t\t{ $$ = $1; $$->signext = true; }\n | contextfielddef NOFLOW_KEY\t\t\t{ $$ = $1; $$->flow = false; }\n | contextfielddef HEX_KEY\t\t\t{ $$ = $1; $$->hex = true; }\n | contextfielddef DEC_KEY\t\t\t{ $$ = $1; $$->hex = false; }\n ;\nspacedef: spaceprop ';'\t\t\t{ slgh->newSpace($1); }\n ;\nspaceprop: DEFINE_KEY SPACE_KEY STRING\t{ $$ = new SpaceQuality(*$3); delete $3; }\n | DEFINE_KEY SPACE_KEY anysymbol\t{ string errmsg = $3->getName()+\": redefined as space\"; slgh->reportError(errmsg); YYERROR; }\n | spaceprop TYPE_KEY '=' RAM_KEY\t{ $$ = $1; $$->type = SpaceQuality::ramtype; }\n | spaceprop TYPE_KEY '=' REGISTER_KEY { $$ = $1; $$->type = SpaceQuality::registertype; }\n | spaceprop SIZE_KEY '=' INTEGER\t{ $$ = $1; $$->size = *$4; delete $4; }\n | spaceprop WORDSIZE_KEY '=' INTEGER\t{ $$ = $1; $$->wordsize = *$4; delete $4; }\n | spaceprop DEFAULT_KEY { $$ = $1; $$->isdefault = true; }\n ;\nvarnodedef: DEFINE_KEY SPACESYM OFFSET_KEY '=' INTEGER SIZE_KEY '=' INTEGER stringlist ';' {\n slgh->defineVarnodes($2,$5,$8,$9); }\n | DEFINE_KEY SPACESYM OFFSET_KEY '=' BADINTEGER { slgh->reportError(\"Parsed integer is too big (overflow)\"); YYERROR; }\n ;\nbitrangedef: DEFINE_KEY BITRANGE_KEY bitrangelist ';'\n ;\nbitrangelist: bitrangesingle\n | bitrangelist bitrangesingle\n ;\nbitrangesingle: STRING '=' VARSYM '[' INTEGER ',' INTEGER ']' {\n slgh->defineBitrange($1,$3,(uint4)*$5,(uint4)*$7); delete $5; delete $7; }\n ;\npcodeopdef: DEFINE_KEY PCODEOP_KEY stringlist ';' { slgh->addUserOp($3); }\n ;\nvalueattach: ATTACH_KEY VALUES_KEY valuelist intblist ';' { slgh->attachValues($3,$4); }\n ;\nnameattach: ATTACH_KEY NAMES_KEY valuelist anystringlist ';' { slgh->attachNames($3,$4); }\n ;\nvarattach: ATTACH_KEY VARIABLES_KEY valuelist varlist ';' { slgh->attachVarnodes($3,$4); }\n ;\nmacrodef: macrostart '{' rtl '}'\t{ slgh->buildMacro($1,$3); }\n ;\n\nwithblockstart: WITH_KEY id_or_nil ':' bitpat_or_nil contextblock '{' { slgh->pushWith($2,$4,$5); }\n ;\nwithblockmid: withblockstart\n | withblockmid definition\n | withblockmid constructorlike\n ;\nwithblock: withblockmid '}' { slgh->popWith(); }\n \nid_or_nil: /* empty */ { $$ = (SubtableSymbol *)0; }\n | SUBTABLESYM { $$ = $1; }\n | STRING { $$ = slgh->newTable($1); }\n ;\n\nbitpat_or_nil: /* empty */ { $$ = (PatternEquation *)0; }\n | pequation { $$ = $1; }\n ;\n\nmacrostart: MACRO_KEY STRING '(' oplist ')' { $$ = slgh->createMacro($2,$4); }\n ;\nrtlbody: '{' rtl '}' { $$ = slgh->standaloneSection($2); }\n | '{' rtlcontinue rtlmid '}' { $$ = slgh->finalNamedSection($2,$3); }\n | OP_UNIMPL { $$ = (SectionVector *)0; }\n ;\nconstructor: constructprint IS_KEY pequation contextblock rtlbody { slgh->buildConstructor($1,$3,$4,$5); }\n | subtablestart IS_KEY pequation contextblock rtlbody { slgh->buildConstructor($1,$3,$4,$5); }\n ;\nconstructprint: subtablestart STRING\t{ $$ = $1; $$->addSyntax(*$2); delete $2; }\n | subtablestart charstring\t\t{ $$ = $1; $$->addSyntax(*$2); delete $2; }\n | subtablestart SYMBOLSTRING\t\t{ $$ = $1; if (slgh->isInRoot($1)) { $$->addSyntax(*$2); delete $2; } else slgh->newOperand($1,$2); }\n | subtablestart '^'\t\t\t\t{ $$ = $1; if (!slgh->isInRoot($1)) { slgh->reportError(\"Unexpected '^' at start of print pieces\"); YYERROR; } }\n | constructprint '^'\t\t\t\t{ $$ = $1; }\n | constructprint STRING\t\t\t{ $$ = $1; $$->addSyntax(*$2); delete $2; }\n | constructprint charstring\t\t{ $$ = $1; $$->addSyntax(*$2); delete $2; }\n | constructprint ' '\t\t\t\t{ $$ = $1; $$->addSyntax(string(\" \")); }\n | constructprint SYMBOLSTRING\t\t{ $$ = $1; slgh->newOperand($1,$2); }\n ;\nsubtablestart: SUBTABLESYM ':'\t{ $$ = slgh->createConstructor($1); }\n | STRING ':'\t\t\t\t\t{ SubtableSymbol *sym=slgh->newTable($1); $$ = slgh->createConstructor(sym); }\n | ':'\t\t\t\t\t\t\t{ $$ = slgh->createConstructor((SubtableSymbol *)0); }\n | subtablestart ' '\t\t\t{ $$ = $1; }\n ;\npexpression: INTB\t\t\t{ $$ = new ConstantValue(*$1); delete $1; }\n// familysymbol is not acceptable in an action expression because it isn't attached to an offset\n | familysymbol\t\t\t{ if ((actionon==1)&&($1->getType() != SleighSymbol::context_symbol))\n { string errmsg=\"Global symbol \"+$1->getName(); errmsg += \" is not allowed in action expression\"; slgh->reportError(errmsg); } $$ = $1->getPatternValue(); }\n// | CONTEXTSYM { $$ = $1->getPatternValue(); }\n | specificsymbol\t\t\t{ $$ = $1->getPatternExpression(); }\n | '(' pexpression ')'\t\t\t{ $$ = $2; }\n | pexpression '+' pexpression\t\t{ $$ = new PlusExpression($1,$3); }\n | pexpression '-' pexpression\t\t{ $$ = new SubExpression($1,$3); }\n | pexpression '*' pexpression\t\t{ $$ = new MultExpression($1,$3); }\n | pexpression OP_LEFT pexpression\t{ $$ = new LeftShiftExpression($1,$3); }\n | pexpression OP_RIGHT pexpression\t{ $$ = new RightShiftExpression($1,$3); }\n | pexpression OP_AND pexpression\t{ $$ = new AndExpression($1,$3); }\n | pexpression OP_OR pexpression\t{ $$ = new OrExpression($1,$3); }\n | pexpression OP_XOR pexpression\t{ $$ = new XorExpression($1,$3); }\n | pexpression '/' pexpression\t\t{ $$ = new DivExpression($1,$3); }\n | '-' pexpression %prec '!'\t\t{ $$ = new MinusExpression($2); }\n | '~' pexpression\t\t\t{ $$ = new NotExpression($2); }\n ;\npequation: elleq\n | pequation '&' pequation\t\t{ $$ = new EquationAnd($1,$3); }\n | pequation '|' pequation\t\t{ $$ = new EquationOr($1,$3); }\n | pequation ';' pequation\t\t{ $$ = new EquationCat($1,$3); }\n ;\nelleq: ELLIPSIS_KEY ellrt\t\t{ $$ = new EquationLeftEllipsis($2); }\n | ellrt\n ;\nellrt: atomic ELLIPSIS_KEY\t\t{ $$ = new EquationRightEllipsis($1); }\n | atomic\n ;\natomic: constraint\n | '(' pequation ')'\t\t\t{ $$ = $2; }\n ;\nconstraint: familysymbol '=' pexpression { $$ = new EqualEquation($1->getPatternValue(),$3); }\n | familysymbol OP_NOTEQUAL pexpression { $$ = new NotEqualEquation($1->getPatternValue(),$3); }\n | familysymbol '<' pexpression\t{ $$ = new LessEquation($1->getPatternValue(),$3); }\n | familysymbol OP_LESSEQUAL pexpression { $$ = new LessEqualEquation($1->getPatternValue(),$3); }\n | familysymbol '>' pexpression\t{ $$ = new GreaterEquation($1->getPatternValue(),$3); }\n | familysymbol OP_GREATEQUAL pexpression { $$ = new GreaterEqualEquation($1->getPatternValue(),$3); }\n | OPERANDSYM '=' pexpression\t\t{ $$ = slgh->constrainOperand($1,$3); \n if ($$ == (PatternEquation *)0) \n { string errmsg=\"Constraining currently undefined operand \"+$1->getName(); slgh->reportError(errmsg); } }\n | OPERANDSYM\t\t\t\t{ $$ = new OperandEquation($1->getIndex()); slgh->selfDefine($1); }\n | SPECSYM { $$ = new UnconstrainedEquation($1->getPatternExpression()); }\n | familysymbol { $$ = slgh->defineInvisibleOperand($1); }\n | SUBTABLESYM { $$ = slgh->defineInvisibleOperand($1); }\n ;\ncontextblock:\t\t\t\t{ $$ = (vector *)0; }\n | '[' contextlist ']'\t\t\t{ $$ = $2; }\n ;\ncontextlist: \t\t\t\t{ $$ = new vector; }\n | contextlist CONTEXTSYM '=' pexpression ';' { $$ = $1; if (!slgh->contextMod($1,$2,$4)) { string errmsg=\"Cannot use 'inst_next' or 'inst_next2' to set context variable: \"+$2->getName(); slgh->reportError(errmsg); YYERROR; } }\n | contextlist GLOBALSET_KEY '(' familysymbol ',' CONTEXTSYM ')' ';' { $$ = $1; slgh->contextSet($1,$4,$6); }\n | contextlist GLOBALSET_KEY '(' specificsymbol ',' CONTEXTSYM ')' ';' { $$ = $1; slgh->contextSet($1,$4,$6); }\n | contextlist OPERANDSYM '=' pexpression ';' { $$ = $1; slgh->defineOperand($2,$4); }\n | contextlist STRING { string errmsg=\"Expecting context symbol, not \"+*$2; delete $2; slgh->reportError(errmsg); YYERROR; }\n ;\nsection_def: OP_LEFT STRING OP_RIGHT { $$ = slgh->newSectionSymbol( *$2 ); delete $2; }\n | OP_LEFT SECTIONSYM OP_RIGHT { $$ = $2; }\n ;\nrtlfirstsection: rtl section_def { $$ = slgh->firstNamedSection($1,$2); }\n ;\nrtlcontinue: rtlfirstsection { $$ = $1; }\n | rtlcontinue rtlmid section_def { $$ = slgh->nextNamedSection($1,$2,$3); }\n ;\nrtl: rtlmid { $$ = $1; if ($$->getOpvec().empty() && ($$->getResult() == (HandleTpl *)0)) slgh->recordNop(); }\n | rtlmid EXPORT_KEY exportvarnode ';' { $$ = slgh->setResultVarnode($1,$3); }\n | rtlmid EXPORT_KEY sizedstar lhsvarnode ';' { $$ = slgh->setResultStarVarnode($1,$3,$4); }\n | rtlmid EXPORT_KEY STRING\t\t{ string errmsg=\"Unknown export varnode: \"+*$3; delete $3; slgh->reportError(errmsg); YYERROR; }\n | rtlmid EXPORT_KEY sizedstar STRING\t{ string errmsg=\"Unknown pointer varnode: \"+*$4; delete $3; delete $4; slgh->reportError(errmsg); YYERROR; }\n ;\nrtlmid: /* EMPTY */\t\t\t{ $$ = slgh->enterSection(); }\n | rtlmid statement\t\t\t{ $$ = $1; if (!$$->addOpList(*$2)) { delete $2; slgh->reportError(\"Multiple delayslot declarations\"); YYERROR; } delete $2; }\n | rtlmid LOCAL_KEY STRING ';' { $$ = $1; slgh->pcode.newLocalDefinition($3); }\n | rtlmid LOCAL_KEY STRING ':' INTEGER ';' { $$ = $1; slgh->pcode.newLocalDefinition($3,*$5); delete $5; }\n ;\nstatement: lhsvarnode '=' expr ';'\t{ $3->setOutput($1); $$ = ExprTree::toVector($3); }\n | LOCAL_KEY STRING '=' expr ';'\t{ $$ = slgh->pcode.newOutput(true,$4,$2); }\n | STRING '=' expr ';'\t\t\t{ $$ = slgh->pcode.newOutput(false,$3,$1); }\n | LOCAL_KEY STRING ':' INTEGER '=' expr ';'\t{ $$ = slgh->pcode.newOutput(true,$6,$2,*$4); delete $4; }\n | STRING ':' INTEGER '=' expr ';'\t{ $$ = slgh->pcode.newOutput(true,$5,$1,*$3); delete $3; }\n | LOCAL_KEY specificsymbol '=' { $$ = (vector *)0; string errmsg = \"Redefinition of symbol: \"+$2->getName(); slgh->reportError(errmsg); YYERROR; }\n | sizedstar expr '=' expr ';'\t\t{ $$ = slgh->pcode.createStore($1,$2,$4); }\n | USEROPSYM '(' paramlist ')' ';'\t{ $$ = slgh->pcode.createUserOpNoOut($1,$3); }\n | lhsvarnode '[' INTEGER ',' INTEGER ']' '=' expr ';' { $$ = slgh->pcode.assignBitRange($1,(uint4)*$3,(uint4)*$5,$8); delete $3, delete $5; }\n | BITSYM '=' expr ';' { $$=slgh->pcode.assignBitRange($1->getParentSymbol()->getVarnode(),$1->getBitOffset(),$1->numBits(),$3); }\n | varnode ':' INTEGER '='\t\t{ delete $1; delete $3; slgh->reportError(\"Illegal truncation on left-hand side of assignment\"); YYERROR; }\n | varnode '(' INTEGER ')'\t\t{ delete $1; delete $3; slgh->reportError(\"Illegal subpiece on left-hand side of assignment\"); YYERROR; }\n | BUILD_KEY OPERANDSYM ';'\t\t{ $$ = slgh->pcode.createOpConst(BUILD,$2->getIndex()); }\n | CROSSBUILD_KEY varnode ',' SECTIONSYM ';' { $$ = slgh->createCrossBuild($2,$4); }\n | CROSSBUILD_KEY varnode ',' STRING ';' { $$ = slgh->createCrossBuild($2,slgh->newSectionSymbol(*$4)); delete $4; }\n | DELAYSLOT_KEY '(' INTEGER ')' ';'\t{ $$ = slgh->pcode.createOpConst(DELAY_SLOT,*$3); delete $3; }\n | GOTO_KEY jumpdest ';'\t\t{ $$ = slgh->pcode.createOpNoOut(CPUI_BRANCH,new ExprTree($2)); }\n | IF_KEY expr GOTO_KEY jumpdest ';'\t{ $$ = slgh->pcode.createOpNoOut(CPUI_CBRANCH,new ExprTree($4),$2); }\n | GOTO_KEY '[' expr ']' ';'\t\t{ $$ = slgh->pcode.createOpNoOut(CPUI_BRANCHIND,$3); }\n | CALL_KEY jumpdest ';'\t\t{ $$ = slgh->pcode.createOpNoOut(CPUI_CALL,new ExprTree($2)); }\n | CALL_KEY '[' expr ']' ';'\t\t{ $$ = slgh->pcode.createOpNoOut(CPUI_CALLIND,$3); }\n | RETURN_KEY ';'\t\t\t{ slgh->reportError(\"Must specify an indirect parameter for return\"); YYERROR; }\n | RETURN_KEY '[' expr ']' ';'\t\t{ $$ = slgh->pcode.createOpNoOut(CPUI_RETURN,$3); }\n | MACROSYM '(' paramlist ')' ';' { $$ = slgh->createMacroUse($1,$3); }\n | label { $$ = slgh->pcode.placeLabel( $1 ); }\n ;\nexpr: varnode { $$ = new ExprTree($1); }\n | sizedstar expr %prec '!'\t{ $$ = slgh->pcode.createLoad($1,$2); }\n | '(' expr ')'\t\t{ $$ = $2; }\n | expr '+' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_ADD,$1,$3); }\n | expr '-' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_SUB,$1,$3); }\n | expr OP_EQUAL expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_EQUAL,$1,$3); }\n | expr OP_NOTEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_INT_NOTEQUAL,$1,$3); }\n | expr '<' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_LESS,$1,$3); }\n | expr OP_GREATEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_INT_LESSEQUAL,$3,$1); }\n | expr OP_LESSEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_INT_LESSEQUAL,$1,$3); }\n | expr '>' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_LESS,$3,$1); }\n | expr OP_SLESS expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_SLESS,$1,$3); }\n | expr OP_SGREATEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_INT_SLESSEQUAL,$3,$1); }\n | expr OP_SLESSEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_INT_SLESSEQUAL,$1,$3); }\n | expr OP_SGREAT expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_SLESS,$3,$1); }\n | '-' expr\t%prec '!' \t{ $$ = slgh->pcode.createOp(CPUI_INT_2COMP,$2); }\n | '~' expr\t\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_NEGATE,$2); }\n | expr '^' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_XOR,$1,$3); }\n | expr '&' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_AND,$1,$3); }\n | expr '|' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_OR,$1,$3); }\n | expr OP_LEFT expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_LEFT,$1,$3); }\n | expr OP_RIGHT expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_RIGHT,$1,$3); }\n | expr OP_SRIGHT expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_SRIGHT,$1,$3); }\n | expr '*' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_MULT,$1,$3); }\n | expr '/' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_DIV,$1,$3); }\n | expr OP_SDIV expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_SDIV,$1,$3); }\n | expr '%' expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_REM,$1,$3); }\n | expr OP_SREM expr\t\t{ $$ = slgh->pcode.createOp(CPUI_INT_SREM,$1,$3); }\n | '!' expr\t\t\t{ $$ = slgh->pcode.createOp(CPUI_BOOL_NEGATE,$2); }\n | expr OP_BOOL_XOR expr\t{ $$ = slgh->pcode.createOp(CPUI_BOOL_XOR,$1,$3); }\n | expr OP_BOOL_AND expr\t{ $$ = slgh->pcode.createOp(CPUI_BOOL_AND,$1,$3); }\n | expr OP_BOOL_OR expr\t{ $$ = slgh->pcode.createOp(CPUI_BOOL_OR,$1,$3); }\n | expr OP_FEQUAL expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_EQUAL,$1,$3); }\n | expr OP_FNOTEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_NOTEQUAL,$1,$3); }\n | expr OP_FLESS expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_LESS,$1,$3); }\n | expr OP_FGREAT expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_LESS,$3,$1); }\n | expr OP_FLESSEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_LESSEQUAL,$1,$3); }\n | expr OP_FGREATEQUAL expr\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_LESSEQUAL,$3,$1); }\n | expr OP_FADD expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_ADD,$1,$3); }\n | expr OP_FSUB expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_SUB,$1,$3); }\n | expr OP_FMULT expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_MULT,$1,$3); }\n | expr OP_FDIV expr\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_DIV,$1,$3); }\n | OP_FSUB expr %prec '!' { $$ = slgh->pcode.createOp(CPUI_FLOAT_NEG,$2); }\n | OP_ABS '(' expr ')'\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_ABS,$3); }\n | OP_SQRT '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_SQRT,$3); }\n | OP_SEXT '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_INT_SEXT,$3); }\n | OP_ZEXT '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_INT_ZEXT,$3); }\n | OP_CARRY '(' expr ',' expr ')' { $$ = slgh->pcode.createOp(CPUI_INT_CARRY,$3,$5); }\n | OP_SCARRY '(' expr ',' expr ')' { $$ = slgh->pcode.createOp(CPUI_INT_SCARRY,$3,$5); }\n | OP_SBORROW '(' expr ',' expr ')' { $$ = slgh->pcode.createOp(CPUI_INT_SBORROW,$3,$5); }\n | OP_FLOAT2FLOAT '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_FLOAT2FLOAT,$3); }\n | OP_INT2FLOAT '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_INT2FLOAT,$3); }\n | OP_NAN '(' expr ')'\t\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_NAN,$3); }\n | OP_TRUNC '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_TRUNC,$3); }\n | OP_CEIL '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_CEIL,$3); }\n | OP_FLOOR '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_FLOOR,$3); }\n | OP_ROUND '(' expr ')'\t{ $$ = slgh->pcode.createOp(CPUI_FLOAT_ROUND,$3); }\n | OP_NEW '(' expr ')' { $$ = slgh->pcode.createOp(CPUI_NEW,$3); }\n | OP_NEW '(' expr ',' expr ')' { $$ = slgh->pcode.createOp(CPUI_NEW,$3,$5); }\n | OP_POPCOUNT '(' expr ')' { $$ = slgh->pcode.createOp(CPUI_POPCOUNT,$3); }\n | OP_LZCOUNT '(' expr ')' { $$ = slgh->pcode.createOp(CPUI_LZCOUNT,$3); }\n | specificsymbol '(' integervarnode ')' { $$ = slgh->pcode.createOp(CPUI_SUBPIECE,new ExprTree($1->getVarnode()),new ExprTree($3)); }\n | specificsymbol ':' INTEGER\t{ $$ = slgh->pcode.createBitRange($1,0,(uint4)(*$3 * 8)); delete $3; }\n | specificsymbol '[' INTEGER ',' INTEGER ']' { $$ = slgh->pcode.createBitRange($1,(uint4)*$3,(uint4)*$5); delete $3, delete $5; }\n | BITSYM { $$=slgh->pcode.createBitRange($1->getParentSymbol(),$1->getBitOffset(),$1->numBits()); }\n | USEROPSYM '(' paramlist ')' { $$ = slgh->pcode.createUserOp($1,$3); }\n | OP_CPOOLREF '(' paramlist ')' { if ((*$3).size() < 2) { string errmsg = \"Must at least two inputs to cpool\"; slgh->reportError(errmsg); YYERROR; } $$ = slgh->pcode.createVariadic(CPUI_CPOOLREF,$3); }\n ; \nsizedstar: '*' '[' SPACESYM ']' ':' INTEGER { $$ = new StarQuality; $$->size = *$6; delete $6; $$->id=ConstTpl($3->getSpace()); }\n | '*' '[' SPACESYM ']'\t{ $$ = new StarQuality; $$->size = 0; $$->id=ConstTpl($3->getSpace()); }\n | '*' ':' INTEGER\t\t{ $$ = new StarQuality; $$->size = *$3; delete $3; $$->id=ConstTpl(slgh->getDefaultCodeSpace()); }\n | '*'\t\t\t\t{ $$ = new StarQuality; $$->size = 0; $$->id=ConstTpl(slgh->getDefaultCodeSpace()); }\n ;\njumpdest: JUMPSYM\t\t{ VarnodeTpl *sym = $1->getVarnode(); $$ = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; }\n | INTEGER\t\t\t{ $$ = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::j_curspace_size)); delete $1; }\n | BADINTEGER { $$ = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); slgh->reportError(\"Parsed integer is too big (overflow)\"); }\n | OPERANDSYM\t\t\t{ $$ = $1->getVarnode(); $1->setCodeAddress(); }\n | INTEGER '[' SPACESYM ']'\t{ AddrSpace *spc = $3->getSpace(); $$ = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete $1; }\n | label { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::j_relative,$1->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); $1->incrementRefCount(); }\n | STRING\t\t\t{ string errmsg = \"Unknown jump destination: \"+*$1; delete $1; slgh->reportError(errmsg); YYERROR; }\n ;\nvarnode: specificsymbol\t\t{ $$ = $1->getVarnode(); }\n | integervarnode\t\t{ $$ = $1; }\n | STRING\t\t\t{ string errmsg = \"Unknown varnode parameter: \"+*$1; delete $1; slgh->reportError(errmsg); YYERROR; }\n | SUBTABLESYM { string errmsg = \"Subtable not attached to operand: \"+$1->getName(); slgh->reportError(errmsg); YYERROR; }\n ;\nintegervarnode: INTEGER\t\t{ $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,0)); delete $1; }\n | BADINTEGER { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); slgh->reportError(\"Parsed integer is too big (overflow)\"); }\n | INTEGER ':' INTEGER\t\t{ $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,*$3)); delete $1; delete $3; }\n | '&' varnode { $$ = slgh->pcode.addressOf($2,0); }\n | '&' ':' INTEGER varnode { $$ = slgh->pcode.addressOf($4,*$3); delete $3; }\n ;\nlhsvarnode: specificsymbol\t{ $$ = $1->getVarnode(); }\n | STRING\t\t\t{ string errmsg = \"Unknown assignment varnode: \"+*$1; delete $1; slgh->reportError(errmsg); YYERROR; }\n | SUBTABLESYM { string errmsg = \"Subtable not attached to operand: \"+$1->getName(); slgh->reportError(errmsg); YYERROR; }\n ;\nlabel: '<' LABELSYM '>' { $$ = $2; }\n | '<' STRING '>' { $$ = slgh->pcode.defineLabel( $2 ); }\n ;\nexportvarnode: specificsymbol\t{ $$ = $1->getVarnode(); }\n | '&' varnode { $$ = slgh->pcode.addressOf($2,0); }\n | '&' ':' INTEGER varnode { $$ = slgh->pcode.addressOf($4,*$3); delete $3; }\n | INTEGER ':' INTEGER\t\t{ $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,*$3)); delete $1; delete $3; }\n | STRING\t\t\t{ string errmsg=\"Unknown export varnode: \"+*$1; delete $1; slgh->reportError(errmsg); YYERROR; }\n | SUBTABLESYM { string errmsg = \"Subtable not attached to operand: \"+$1->getName(); slgh->reportError(errmsg); YYERROR; }\n ;\nfamilysymbol: VALUESYM\t\t{ $$ = $1; }\n | VALUEMAPSYM { $$ = $1; }\n | CONTEXTSYM { $$ = $1; }\n | NAMESYM\t\t\t{ $$ = $1; }\n | VARLISTSYM\t\t\t{ $$ = $1; }\n ;\nspecificsymbol: VARSYM\t\t{ $$ = $1; }\n | SPECSYM { $$ = $1; }\n | OPERANDSYM\t\t\t{ $$ = $1; }\n | JUMPSYM\t\t\t{ $$ = $1; }\n ;\ncharstring: CHAR\t\t{ $$ = new string; (*$$) += $1; }\n | charstring CHAR\t\t{ $$ = $1; (*$$) += $2; }\n ;\nintblist: '[' intbpart ']'\t{ $$ = $2; }\n | INTEGER { $$ = new vector; $$->push_back(intb(*$1)); delete $1; }\n | '-' INTEGER { $$ = new vector; $$->push_back(-intb(*$2)); delete $2; }\n ;\nintbpart: INTEGER\t\t{ $$ = new vector; $$->push_back(intb(*$1)); delete $1; }\n | '-' INTEGER { $$ = new vector; $$->push_back(-intb(*$2)); delete $2; }\n | STRING { if (*$1!=\"_\") { string errmsg = \"Expecting integer but saw: \"+*$1; delete $1; slgh->reportError(errmsg); YYERROR; }\n $$ = new vector; $$->push_back((intb)0xBADBEEF); delete $1; }\n | intbpart INTEGER { $$ = $1; $$->push_back(intb(*$2)); delete $2; }\n | intbpart '-' INTEGER { $$ = $1; $$->push_back(-intb(*$3)); delete $3; }\n | intbpart STRING { if (*$2!=\"_\") { string errmsg = \"Expecting integer but saw: \"+*$2; delete $2; slgh->reportError(errmsg); YYERROR; }\n $$ = $1; $$->push_back((intb)0xBADBEEF); delete $2; }\n ;\nstringlist: '[' stringpart ']'\t{ $$ = $2; }\n | STRING\t\t\t{ $$ = new vector; $$->push_back(*$1); delete $1; }\n ;\nstringpart: STRING\t\t{ $$ = new vector; $$->push_back( *$1 ); delete $1; }\n | stringpart STRING\t\t{ $$ = $1; $$->push_back(*$2); delete $2; }\n | stringpart anysymbol\t{ string errmsg = $2->getName()+\": redefined\"; slgh->reportError(errmsg); YYERROR; }\n ;\nanystringlist: '[' anystringpart ']' { $$ = $2; }\n ;\nanystringpart: STRING { $$ = new vector; $$->push_back( *$1 ); delete $1; }\n | anysymbol { $$ = new vector; $$->push_back( $1->getName() ); }\n | anystringpart STRING { $$ = $1; $$->push_back(*$2); delete $2; }\n | anystringpart anysymbol { $$ = $1; $$->push_back($2->getName()); }\n ;\nvaluelist: '[' valuepart ']'\t{ $$ = $2; }\n | VALUESYM\t\t\t{ $$ = new vector; $$->push_back($1); }\n | CONTEXTSYM { $$ = new vector; $$->push_back($1); }\n ;\nvaluepart: VALUESYM\t\t{ $$ = new vector; $$->push_back( $1 ); }\n | CONTEXTSYM { $$ = new vector; $$->push_back($1); }\n | valuepart VALUESYM\t\t{ $$ = $1; $$->push_back($2); }\n | valuepart CONTEXTSYM { $$ = $1; $$->push_back($2); }\n | valuepart STRING\t\t{ string errmsg = *$2+\": is not a value pattern\"; delete $2; slgh->reportError(errmsg); YYERROR; }\n ;\nvarlist: '[' varpart ']'\t{ $$ = $2; }\n | VARSYM\t\t\t{ $$ = new vector; $$->push_back($1); }\n ;\nvarpart: VARSYM\t\t\t{ $$ = new vector; $$->push_back($1); }\n | STRING { if (*$1!=\"_\") { string errmsg = *$1+\": is not a varnode symbol\"; delete $1; slgh->reportError(errmsg); YYERROR; }\n\t\t\t\t $$ = new vector; $$->push_back((SleighSymbol *)0); delete $1; }\n | varpart VARSYM\t\t{ $$ = $1; $$->push_back($2); }\n | varpart STRING\t\t{ if (*$2!=\"_\") { string errmsg = *$2+\": is not a varnode symbol\"; delete $2; slgh->reportError(errmsg); YYERROR; }\n $$ = $1; $$->push_back((SleighSymbol *)0); delete $2; }\n ;\nparamlist: /* EMPTY */\t\t{ $$ = new vector; }\n | expr\t\t\t{ $$ = new vector; $$->push_back($1); }\n | paramlist ',' expr\t\t{ $$ = $1; $$->push_back($3); }\n ;\noplist: /* EMPTY */\t\t{ $$ = new vector; }\n | STRING\t\t\t{ $$ = new vector; $$->push_back(*$1); delete $1; }\n | oplist ',' STRING\t\t{ $$ = $1; $$->push_back(*$3); delete $3; }\n ;\nanysymbol: SPACESYM\t\t{ $$ = $1; }\n | SECTIONSYM { $$ = $1; }\n | TOKENSYM\t\t\t{ $$ = $1; }\n | USEROPSYM\t\t\t{ $$ = $1; }\n | MACROSYM\t\t\t{ $$ = $1; }\n | SUBTABLESYM\t\t\t{ $$ = $1; }\n | VALUESYM\t\t\t{ $$ = $1; }\n | VALUEMAPSYM { $$ = $1; }\n | CONTEXTSYM { $$ = $1; }\n | NAMESYM\t\t\t{ $$ = $1; }\n | VARSYM\t\t\t{ $$ = $1; }\n | VARLISTSYM\t\t\t{ $$ = $1; }\n | OPERANDSYM\t\t\t{ $$ = $1; }\n | JUMPSYM\t\t\t{ $$ = $1; }\n | BITSYM { $$ = $1; }\n ;\n%%\n\nint sleigherror(const char *s)\n\n{\n slgh->reportError(s);\n return 0;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/slghpatexpress.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"slghpatexpress.hh\"\n#include \"sleighbase.hh\"\n\nnamespace ghidra {\n\nint4 TokenPattern::resolveTokens(const TokenPattern &tok1,const TokenPattern &tok2)\n\n{\t\t\t\t// Use the token lists to decide how the two patterns\n\t\t\t\t// should be aligned relative to each other\n\t\t\t\t// return how much -tok2- needs to be shifted\n\t\t\t\t// and set the resulting tokenlist and ellipses\n bool reversedirection = false;\n leftellipsis = false;\n rightellipsis = false;\n int4 ressa = 0;\n int4 minsize = tok1.toklist.size() < tok2.toklist.size() ? tok1.toklist.size() : tok2.toklist.size();\n if (minsize == 0) {\n\t\t\t\t// Check if pattern doesn't care about tokens\n if ((tok1.toklist.size()==0)&&(tok1.leftellipsis==false)&&(tok1.rightellipsis==false)) {\n toklist = tok2.toklist;\n leftellipsis = tok2.leftellipsis;\n rightellipsis = tok2.rightellipsis;\n return 0;\n }\n else if ((tok2.toklist.size()==0)&&(tok2.leftellipsis==false)&&(tok2.rightellipsis==false)) {\n toklist = tok1.toklist;\n leftellipsis = tok1.leftellipsis;\n rightellipsis = tok1.rightellipsis;\n return 0;\n }\n\t\t\t\t// If one of the ellipses is true then the pattern\n\t\t\t\t// still cares about tokens even though none are\n\t\t\t\t// specified\n }\n \n if (tok1.leftellipsis) {\n reversedirection = true;\n if (tok2.rightellipsis)\n throw SleighError(\"Right/left ellipsis\");\n else if (tok2.leftellipsis)\n leftellipsis = true;\n else if (tok1.toklist.size() != minsize) {\n ostringstream msg;\n msg << \"Mismatched pattern sizes -- \" << dec << tok1.toklist.size()\n\t << \" != \"\n\t << dec << minsize;\n throw SleighError(msg.str());\n }\n else if (tok1.toklist.size()==tok2.toklist.size())\n throw SleighError(\"Pattern size cannot vary (missing '...'?)\");\n }\n else if (tok1.rightellipsis) {\n if (tok2.leftellipsis)\n throw SleighError(\"Left/right ellipsis\");\n else if (tok2.rightellipsis)\n rightellipsis = true;\n else if (tok1.toklist.size() != minsize) {\n ostringstream msg;\n msg << \"Mismatched pattern sizes -- \" << dec << tok1.toklist.size()\n\t << \" != \"\n\t << dec << minsize;\n throw SleighError(msg.str());\n }\n else if (tok1.toklist.size()==tok2.toklist.size())\n throw SleighError(\"Pattern size cannot vary (missing '...'?)\");\n }\n else {\n if (tok2.leftellipsis) {\n reversedirection = true;\n if (tok2.toklist.size() != minsize) {\n\tostringstream msg;\n\tmsg << \"Mismatched pattern sizes -- \" << dec << tok2.toklist.size()\n\t << \" != \"\n\t << dec << minsize;\n\tthrow SleighError(msg.str());\n }\n else if (tok1.toklist.size()==tok2.toklist.size())\n\tthrow SleighError(\"Pattern size cannot vary (missing '...'?)\");\n }\n else if (tok2.rightellipsis) {\n if (tok2.toklist.size() != minsize) {\n\tostringstream msg;\n\tmsg << \"Mismatched pattern sizes -- \" << dec << tok2.toklist.size()\n\t << \" != \"\n\t << dec << minsize;\n\tthrow SleighError(msg.str());\n }\n else if (tok1.toklist.size()==tok2.toklist.size())\n\tthrow SleighError(\"Pattern size cannot vary (missing '...'?)\");\n }\n else {\n if (tok2.toklist.size() != tok1.toklist.size()) {\n\tostringstream msg;\n\tmsg << \"Mismatched pattern sizes -- \" << dec << tok2.toklist.size()\n\t << \" != \"\n\t << dec << tok1.toklist.size();\n\tthrow SleighError(msg.str());\n }\n }\n }\n if (reversedirection) {\n for(int4 i=0;igetSize();\n else\n for(int4 i=minsize;igetSize();\n if (tok1.toklist.size() < tok2.toklist.size())\n ressa = -ressa;\n }\n else {\n for(int4 i=0;i= 8) {\n offset += 1;\n startbit -= 8;\n endbit -= 8;\n }\n mask = (~((uintm)0)) << (sizeof(uintm)*8-size);\n byteval = (byteval << (sizeof(uintm)*8-size))& mask;\n mask >>= startbit;\n byteval >>= startbit;\n return new PatternBlock(offset,mask,byteval);\n}\n\nPatternBlock *TokenPattern::buildBigBlock(int4 size,int4 bitstart,int4 bitend,intb value)\n\n{\t\t\t\t// Build pattern block given a bigendian contiguous\n\t\t\t\t// range of bits and a value for those bits\n int4 tmpstart,startbit,endbit;\n PatternBlock *tmpblock,*block;\n\n startbit = 8*size - 1 - bitend;\n endbit = 8*size - 1 - bitstart;\n \n block = (PatternBlock *)0;\n while(endbit >= startbit) {\n tmpstart = endbit - (endbit & 7);\n if (tmpstart < startbit)\n tmpstart = startbit;\n tmpblock = buildSingle(tmpstart,endbit,(uintm)value);\n if (block == (PatternBlock *)0)\n block = tmpblock;\n else {\n PatternBlock *newblock = block->intersect(tmpblock);\n delete block;\n delete tmpblock;\n block = newblock;\n }\n value >>= (endbit-tmpstart+1);\n endbit = tmpstart - 1;\n }\n return block;\n}\n\nPatternBlock *TokenPattern::buildLittleBlock(int4 size,int4 bitstart,int4 bitend,intb value)\n\n{\t\t\t\t// Build pattern block given a littleendian contiguous\n\t\t\t\t// range of bits and a value for those bits\n PatternBlock *tmpblock,*block;\n int4 startbit,endbit;\n\n block = (PatternBlock *)0;\n\n // we need to convert a bit range specified on a little endian token where the\n // bit indices label the least sig bit as 0 into a bit range on big endian bytes\n // where the indices label the most sig bit as 0. The reversal due to\n // little->big endian cancels part of the reversal due to least->most sig bit\n // labelling, but not on the lower 3 bits. So the transform becomes\n // leave the upper bits the same, but transform the lower 3-bit value x into 7-x.\n\n startbit = (bitstart/8) * 8;\t// Get the high-order portion of little/LSB labelling\n endbit = (bitend/8) * 8;\n bitend = bitend % 8;\t\t// Get the low-order portion of little/LSB labelling\n bitstart = bitstart % 8;\n\n if (startbit == endbit) {\n startbit += 7 - bitend;\n endbit += 7 - bitstart;\n block = buildSingle(startbit,endbit,(uintm)value);\n }\n else {\n block = buildSingle(startbit,startbit+(7-bitstart),(uintm)value);\n value >>= (8-bitstart);\t// Cut off bits we just encoded\n startbit += 8;\n while(startbit != endbit) {\n tmpblock = buildSingle(startbit,startbit+7,(uintm)value);\n if (block == (PatternBlock *)0)\n\tblock = tmpblock;\n else {\n\tPatternBlock *newblock = block->intersect(tmpblock);\n\tdelete block;\n\tdelete tmpblock;\n\tblock = newblock;\n }\n value >>= 8;\n startbit += 8;\n }\n tmpblock = buildSingle(endbit+(7-bitend),endbit+7,(uintm)value);\n if (block == (PatternBlock *)0)\n block = tmpblock;\n else {\n PatternBlock *newblock = block->intersect(tmpblock);\n delete block;\n delete tmpblock;\n block = newblock;\n }\n }\n return block;\n}\n\nTokenPattern::TokenPattern(void)\n\n{\n leftellipsis = false;\n rightellipsis = false;\n pattern = new InstructionPattern(true);\n}\n\nTokenPattern::TokenPattern(bool tf)\n\n{\t\t\t\t// TRUE or FALSE pattern\n leftellipsis = false;\n rightellipsis = false;\n pattern = new InstructionPattern(tf);\n}\n \nTokenPattern::TokenPattern(Token *tok)\n\n{\n leftellipsis = false;\n rightellipsis = false;\n pattern = new InstructionPattern(true);\n toklist.push_back(tok);\n}\n\nTokenPattern::TokenPattern(Token *tok,intb value,int4 bitstart,int4 bitend)\n\n{\t\t\t\t// A basic instruction pattern\n\n toklist.push_back(tok);\n leftellipsis = false;\n rightellipsis = false;\n PatternBlock *block;\n\n if (tok->isBigEndian())\n block = buildBigBlock(tok->getSize(),bitstart,bitend,value);\n else\n block = buildLittleBlock(tok->getSize(),bitstart,bitend,value);\n pattern = new InstructionPattern(block);\n}\n\nTokenPattern::TokenPattern(intb value,int4 startbit,int4 endbit)\n\n{\t\t\t\t// A basic context pattern\n leftellipsis = false;\n rightellipsis = false;\n PatternBlock *block;\n int4 size = (endbit/8) + 1;\n\n block = buildBigBlock(size,size*8-1-endbit,size*8-1-startbit,value);\n pattern = new ContextPattern(block);\n}\n\nTokenPattern::TokenPattern(const TokenPattern &tokpat)\n\n{\n pattern = tokpat.pattern->simplifyClone();\n toklist = tokpat.toklist;\n leftellipsis = tokpat.leftellipsis;\n rightellipsis = tokpat.rightellipsis;\n}\n\nconst TokenPattern &TokenPattern::operator=(const TokenPattern &tokpat)\n\n{\n delete pattern;\n\n pattern = tokpat.pattern->simplifyClone();\n toklist = tokpat.toklist;\n leftellipsis = tokpat.leftellipsis;\n rightellipsis = tokpat.rightellipsis;\n return *this;\n}\n\nTokenPattern TokenPattern::doAnd(const TokenPattern &tokpat) const\n\n{\t\t\t\t// Return -this- AND tokpat\n TokenPattern res((Pattern *)0);\n int4 sa = res.resolveTokens(*this,tokpat);\n\n res.pattern = pattern->doAnd(tokpat.pattern,sa);\n return res;\n}\n\nTokenPattern TokenPattern::doOr(const TokenPattern &tokpat) const\n\n{\t\t\t\t// Return -this- OR tokpat\n TokenPattern res((Pattern *)0);\n int4 sa = res.resolveTokens(*this,tokpat);\n\n res.pattern = pattern->doOr(tokpat.pattern,sa);\n return res;\n}\n\nTokenPattern TokenPattern::doCat(const TokenPattern &tokpat) const\n\n{\t\t\t\t// Return Concatenation of -this- and -tokpat-\n TokenPattern res((Pattern *)0);\n int4 sa;\n\n res.leftellipsis = leftellipsis;\n res.rightellipsis = rightellipsis;\n res.toklist = toklist;\n if (rightellipsis||tokpat.leftellipsis) { // Check for interior ellipsis\n if (rightellipsis) {\n if (!tokpat.alwaysInstructionTrue())\n\tthrow SleighError(\"Interior ellipsis in pattern\");\n }\n if (tokpat.leftellipsis) {\n if (!alwaysInstructionTrue())\n\tthrow SleighError(\"Interior ellipsis in pattern\");\n res.leftellipsis = true;\n }\n sa = -1;\n }\n else {\n sa = 0;\n vector::const_iterator iter;\n\n for(iter=toklist.begin();iter!=toklist.end();++iter)\n sa += (*iter)->getSize();\n for(iter=tokpat.toklist.begin();iter!=tokpat.toklist.end();++iter)\n res.toklist.push_back(*iter);\n res.rightellipsis = tokpat.rightellipsis;\n }\n if (res.rightellipsis && res.leftellipsis)\n throw SleighError(\"Double ellipsis in pattern\");\n if (sa < 0)\n res.pattern = pattern->doAnd(tokpat.pattern,0);\n else\n res.pattern = pattern->doAnd(tokpat.pattern,sa);\n return res;\n}\n\nTokenPattern TokenPattern::commonSubPattern(const TokenPattern &tokpat) const\n\n{\t\t\t\t// Construct pattern that matches anything\n\t\t\t\t// that matches either -this- or -tokpat-\n TokenPattern patres((Pattern *)0); // Empty shell\n int4 i;\n bool reversedirection = false;\n\n if (leftellipsis||tokpat.leftellipsis) {\n if (rightellipsis||tokpat.rightellipsis)\n throw SleighError(\"Right/left ellipsis in commonSubPattern\");\n reversedirection = true;\n }\n\n\t\t\t\t// Find common subset of tokens and ellipses\n patres.leftellipsis = leftellipsis || tokpat.leftellipsis;\n patres.rightellipsis = rightellipsis || tokpat.rightellipsis;\n int4 minnum = toklist.size();\n int4 maxnum = tokpat.toklist.size();\n if (maxnum < minnum) {\n int4 tmp = minnum;\n minnum = maxnum;\n maxnum = tmp;\n }\n if (reversedirection) {\n for(i=0;icommonSubPattern(tokpat.pattern,0);\n return patres;\n}\n\nint4 TokenPattern::getMinimumLength(void) const\n\n{\t\t\t\t// Add up length of concatenated tokens\n int4 length = 0;\n for(int4 i=0;igetSize();\n return length;\n}\n\nvoid PatternExpression::release(PatternExpression *p)\n\n{\n p->refcount -= 1;\n if (p->refcount <= 0)\n delete p;\n}\n\nPatternExpression *PatternExpression::decodeExpression(Decoder &decoder,Translate *trans)\n\n{\n PatternExpression *res;\n uint4 el = decoder.peekElement();\n\n if (el == sla::ELEM_TOKENFIELD)\n res = new TokenField();\n else if (el == sla::ELEM_CONTEXTFIELD)\n res = new ContextField();\n else if (el == sla::ELEM_INTB)\n res = new ConstantValue();\n else if (el == sla::ELEM_OPERAND_EXP)\n res = new OperandValue();\n else if (el == sla::ELEM_START_EXP)\n res = new StartInstructionValue();\n else if (el == sla::ELEM_END_EXP)\n res = new EndInstructionValue();\n else if (el == sla::ELEM_PLUS_EXP)\n res = new PlusExpression();\n else if (el == sla::ELEM_SUB_EXP)\n res = new SubExpression();\n else if (el == sla::ELEM_MULT_EXP)\n res = new MultExpression();\n else if (el == sla::ELEM_LSHIFT_EXP)\n res = new LeftShiftExpression();\n else if (el == sla::ELEM_RSHIFT_EXP)\n res = new RightShiftExpression();\n else if (el == sla::ELEM_AND_EXP)\n res = new AndExpression();\n else if (el == sla::ELEM_OR_EXP)\n res = new OrExpression();\n else if (el == sla::ELEM_XOR_EXP)\n res = new XorExpression();\n else if (el == sla::ELEM_DIV_EXP)\n res = new DivExpression();\n else if (el == sla::ELEM_MINUS_EXP)\n res = new MinusExpression();\n else if (el == sla::ELEM_NOT_EXP)\n res = new NotExpression();\n else\n return (PatternExpression *)0;\n\n res->decode(decoder,trans);\n return res;\n}\n\nstatic intb getInstructionBytes(ParserWalker &walker,int4 bytestart,int4 byteend,bool bigendian)\n\n{\t\t\t\t// Build a intb from the instruction bytes\n intb res = 0;\n uintm tmp;\n int4 size,tmpsize;\n\n size = byteend-bytestart+1;\n tmpsize = size;\n while(tmpsize >= sizeof(uintm)) {\n tmp = walker.getInstructionBytes(bytestart,sizeof(uintm));\n res <<= 8*sizeof(uintm);\n res |= tmp;\n bytestart += sizeof(uintm);\n tmpsize -= sizeof(uintm);\n }\n if (tmpsize > 0) {\n tmp = walker.getInstructionBytes(bytestart,tmpsize);\n res <<= 8*tmpsize;\n res |= tmp;\n }\n if (!bigendian)\n byte_swap(res,size);\n return res;\n}\n\nstatic intb getContextBytes(ParserWalker &walker,int4 bytestart,int4 byteend)\n\n{\t\t\t\t// Build a intb from the context bytes\n intb res = 0;\n uintm tmp;\n int4 size;\n\n size = byteend-bytestart+1;\n while(size >= sizeof(uintm)) {\n tmp = walker.getContextBytes(bytestart,sizeof(uintm));\n res <<= 8*sizeof(uintm);\n res |= tmp;\n bytestart += sizeof(uintm);\n size = byteend-bytestart+1;\n }\n if (size > 0) {\n tmp = walker.getContextBytes(bytestart,size);\n res <<= 8*size;\n res |= tmp;\n }\n return res;\n}\n\nTokenField::TokenField(Token *tk,bool s,int4 bstart,int4 bend)\n\n{\n tok = tk;\n bigendian = tok->isBigEndian();\n signbit = s;\n bitstart = bstart;\n bitend = bend;\n if (tk->isBigEndian()) {\n byteend = (tk->getSize()*8 - bitstart - 1)/8;\n bytestart = (tk->getSize()*8 - bitend - 1)/8;\n }\n else {\n bytestart = bitstart/8;\n byteend = bitend/8;\n }\n shift = bitstart % 8;\n}\n\nintb TokenField::getValue(ParserWalker &walker) const\n\n{\t\t\t\t// Construct value given specific instruction stream\n intb res = getInstructionBytes(walker,bytestart,byteend,bigendian);\n \n res >>= shift;\n if (signbit)\n res = sign_extend(res,bitend-bitstart);\n else\n res = zero_extend(res,bitend-bitstart);\n return res;\n}\n\nTokenPattern TokenField::genPattern(intb val) const\n\n{\t\t\t\t// Generate corresponding pattern if the\n\t\t\t\t// value is forced to be val\n return TokenPattern(tok,val,bitstart,bitend);\n}\n\nvoid TokenField::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_TOKENFIELD);\n encoder.writeBool(sla::ATTRIB_BIGENDIAN, bigendian);\n encoder.writeBool(sla::ATTRIB_SIGNBIT, signbit);\n encoder.writeSignedInteger(sla::ATTRIB_STARTBIT, bitstart);\n encoder.writeSignedInteger(sla::ATTRIB_ENDBIT, bitend);\n encoder.writeSignedInteger(sla::ATTRIB_STARTBYTE, bytestart);\n encoder.writeSignedInteger(sla::ATTRIB_ENDBYTE, byteend);\n encoder.writeSignedInteger(sla::ATTRIB_SHIFT, shift);\n encoder.closeElement(sla::ELEM_TOKENFIELD);\n}\n\nvoid TokenField::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_TOKENFIELD);\n tok = (Token *)0;\n bigendian = decoder.readBool(sla::ATTRIB_BIGENDIAN);\n signbit = decoder.readBool(sla::ATTRIB_SIGNBIT);\n bitstart = decoder.readSignedInteger(sla::ATTRIB_STARTBIT);\n bitend = decoder.readSignedInteger(sla::ATTRIB_ENDBIT);\n bytestart = decoder.readSignedInteger(sla::ATTRIB_STARTBYTE);\n byteend = decoder.readSignedInteger(sla::ATTRIB_ENDBYTE);\n shift = decoder.readSignedInteger(sla::ATTRIB_SHIFT);\n decoder.closeElement(el);\n}\n\nContextField::ContextField(bool s,int4 sbit,int4 ebit)\n\n{\n signbit = s;\n startbit = sbit;\n endbit = ebit;\n startbyte = startbit/8;\n endbyte = endbit/8;\n shift = 7 - (endbit%8);\n}\n\nintb ContextField::getValue(ParserWalker &walker) const\n\n{\n intb res = getContextBytes(walker,startbyte,endbyte);\n res >>= shift;\n if (signbit)\n res = sign_extend(res,endbit-startbit);\n else\n res = zero_extend(res,endbit-startbit);\n return res;\n}\n\nTokenPattern ContextField::genPattern(intb val) const\n\n{\n return TokenPattern(val,startbit,endbit);\n}\n\nvoid ContextField::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_CONTEXTFIELD);\n encoder.writeBool(sla::ATTRIB_SIGNBIT, signbit);\n encoder.writeSignedInteger(sla::ATTRIB_STARTBIT, startbit);\n encoder.writeSignedInteger(sla::ATTRIB_ENDBIT, endbit);\n encoder.writeSignedInteger(sla::ATTRIB_STARTBYTE, startbyte);\n encoder.writeSignedInteger(sla::ATTRIB_ENDBYTE, endbyte);\n encoder.writeSignedInteger(sla::ATTRIB_SHIFT, shift);\n encoder.closeElement(sla::ELEM_CONTEXTFIELD);\n}\n\nvoid ContextField::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_CONTEXTFIELD);\n signbit = decoder.readBool(sla::ATTRIB_SIGNBIT);\n startbit = decoder.readSignedInteger(sla::ATTRIB_STARTBIT);\n endbit = decoder.readSignedInteger(sla::ATTRIB_ENDBIT);\n startbyte = decoder.readSignedInteger(sla::ATTRIB_STARTBYTE);\n endbyte = decoder.readSignedInteger(sla::ATTRIB_ENDBYTE);\n shift = decoder.readSignedInteger(sla::ATTRIB_SHIFT);\n decoder.closeElement(el);\n}\n\nvoid ConstantValue::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_INTB);\n encoder.writeSignedInteger(sla::ATTRIB_VAL, val);\n encoder.closeElement(sla::ELEM_INTB);\n}\n\nvoid ConstantValue::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_INTB);\n val = decoder.readSignedInteger(sla::ATTRIB_VAL);\n decoder.closeElement(el);\n}\n\nvoid StartInstructionValue::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_START_EXP);\n encoder.closeElement(sla::ELEM_START_EXP);\n}\n\nvoid StartInstructionValue::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_START_EXP);\n decoder.closeElement(el);\n}\n\nvoid EndInstructionValue::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_END_EXP);\n encoder.closeElement(sla::ELEM_END_EXP);\n}\n\nvoid EndInstructionValue::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_END_EXP);\n decoder.closeElement(el);\n}\n\nvoid Next2InstructionValue::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_NEXT2_EXP);\n encoder.closeElement(sla::ELEM_NEXT2_EXP);\n}\n\nvoid Next2InstructionValue::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_NEXT2_EXP);\n decoder.closeElement(el);\n}\n\nTokenPattern OperandValue::genPattern(intb val) const\n\n{\n // In general an operand cannot be interpreted as any sort\n // of static constraint in an equation, and if it is being\n // defined by the equation, it should be on the left hand side.\n // If the operand has a defining expression already, use\n // of the operand in the equation makes sense, its defining\n // expression would become a subexpression in the full\n // expression. However, since this can be accomplished\n // by explicitly copying the subexpression into the full\n // expression, we don't support operands as placeholders.\n throw SleighError(\"Operand used in pattern expression\");\n}\n\nintb OperandValue::minValue(void) const\n\n{\n throw SleighError(\"Operand used in pattern expression\");\n}\n\nintb OperandValue::maxValue(void) const\n\n{\n throw SleighError(\"Operand used in pattern expression\");\n}\n\nintb OperandValue::getValue(ParserWalker &walker) const\n\n{\t\t\t\t// Get the value of an operand when it is used in\n\t\t\t\t// an expression. \n OperandSymbol *sym = ct->getOperand(index);\n PatternExpression *patexp = sym->getDefiningExpression();\n if (patexp == (PatternExpression *)0) {\n TripleSymbol *defsym = sym->getDefiningSymbol();\n if (defsym != (TripleSymbol *)0)\n patexp = defsym->getPatternExpression();\n if (patexp == (PatternExpression *)0)\n return 0;\n }\n ConstructState tempstate;\n ParserWalker newwalker(walker.getParserContext());\n newwalker.setOutOfBandState(ct,index,&tempstate,walker);\n intb res = patexp->getValue(newwalker);\n return res;\n}\n\nintb OperandValue::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n OperandSymbol *sym = ct->getOperand(index);\n return sym->getDefiningExpression()->getSubValue(replace,listpos);\n}\n\nbool OperandValue::isConstructorRelative(void) const\n\n{\n OperandSymbol *sym = ct->getOperand(index);\n return (sym->getOffsetBase()==-1);\n}\n\nconst string &OperandValue::getName(void) const\n\n{\n OperandSymbol *sym = ct->getOperand(index);\n return sym->getName();\n}\n\nvoid OperandValue::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_OPERAND_EXP);\n encoder.writeSignedInteger(sla::ATTRIB_INDEX, index);\n encoder.writeUnsignedInteger(sla::ATTRIB_TABLE, ct->getParent()->getId());\n encoder.writeUnsignedInteger(sla::ATTRIB_CT, ct->getId());\t// Save id of our constructor\n encoder.closeElement(sla::ELEM_OPERAND_EXP);\n}\n\nvoid OperandValue::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_OPERAND_EXP);\n index = decoder.readSignedInteger(sla::ATTRIB_INDEX);\n uintm tabid = decoder.readUnsignedInteger(sla::ATTRIB_TABLE);\n uintm ctid = decoder.readUnsignedInteger(sla::ATTRIB_CT);\n SleighBase *sleigh = (SleighBase *)trans;\n SubtableSymbol *tab = dynamic_cast(sleigh->findSymbol(tabid));\n ct = tab->getConstructor(ctid);\n decoder.closeElement(el);\n}\n\nBinaryExpression::BinaryExpression(PatternExpression *l,PatternExpression *r)\n\n{\n (left=l)->layClaim();\n (right=r)->layClaim();\n}\n\nBinaryExpression::~BinaryExpression(void)\n\n{\t\t\t\t// Delete only non-pattern values\n if (left != (PatternExpression *)0)\n PatternExpression::release(left);\n if (right != (PatternExpression *)0)\n PatternExpression::release(right);\n}\n\nvoid BinaryExpression::encode(Encoder &encoder) const\n\n{\t\t\t\t// Outer tag is generated by derived classes\n left->encode(encoder);\n right->encode(encoder);\n}\n\nvoid BinaryExpression::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement();\n left = PatternExpression::decodeExpression(decoder,trans);\n right = PatternExpression::decodeExpression(decoder,trans);\n left->layClaim();\n right->layClaim();\n decoder.closeElement(el);\n}\n\nUnaryExpression::UnaryExpression(PatternExpression *u)\n\n{\n (unary=u)->layClaim();\n}\n\nUnaryExpression::~UnaryExpression(void)\n\n{\t\t\t\t// Delete only non-pattern values\n if (unary != (PatternExpression *)0)\n PatternExpression::release(unary);\n}\n\nvoid UnaryExpression::encode(Encoder &encoder) const\n\n{\t\t\t\t// Outer tag is generated by derived classes\n unary->encode(encoder);\n}\n\nvoid UnaryExpression::decode(Decoder &decoder,Translate *trans)\n\n{\n uint4 el = decoder.openElement();\n unary = PatternExpression::decodeExpression(decoder,trans);\n unary->layClaim();\n decoder.closeElement(el);\n}\n\nintb PlusExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval + rightval;\n}\n\nintb PlusExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval + rightval;\n}\n\nvoid PlusExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_PLUS_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_PLUS_EXP);\n}\n\nintb SubExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval - rightval;\n}\n\nintb SubExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval - rightval;\n}\n\nvoid SubExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_SUB_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_SUB_EXP);\n}\n\nintb MultExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval * rightval;\n}\n\nintb MultExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval * rightval;\n}\n\nvoid MultExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_MULT_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_MULT_EXP);\n}\n\nintb LeftShiftExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval << rightval;\n}\n\nintb LeftShiftExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval << rightval;\n}\n\nvoid LeftShiftExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_LSHIFT_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_LSHIFT_EXP);\n}\n\nintb RightShiftExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval >> rightval;\n}\n\nintb RightShiftExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval >> rightval;\n}\n\nvoid RightShiftExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_RSHIFT_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_RSHIFT_EXP);\n}\n\nintb AndExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval & rightval;\n}\n\nintb AndExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval & rightval;\n}\n\nvoid AndExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_AND_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_AND_EXP);\n}\n\nintb OrExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval | rightval;\n}\n\nintb OrExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval | rightval;\n}\n\nvoid OrExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_OR_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_OR_EXP);\n}\n\nintb XorExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval ^ rightval;\n}\n\nintb XorExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval ^ rightval;\n}\n\nvoid XorExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_XOR_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_XOR_EXP);\n}\n\nintb DivExpression::getValue(ParserWalker &walker) const\n\n{\n intb leftval = getLeft()->getValue(walker);\n intb rightval = getRight()->getValue(walker);\n return leftval / rightval;\n}\n\nintb DivExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb leftval = getLeft()->getSubValue(replace,listpos); // Must be left first\n intb rightval = getRight()->getSubValue(replace,listpos);\n return leftval / rightval;\n}\n\nvoid DivExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_DIV_EXP);\n BinaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_DIV_EXP);\n}\n\nintb MinusExpression::getValue(ParserWalker &walker) const\n\n{\n intb val = getUnary()->getValue(walker);\n return -val;\n}\n\nintb MinusExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb val = getUnary()->getSubValue(replace,listpos);\n return -val;\n}\n\nvoid MinusExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_MINUS_EXP);\n UnaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_MINUS_EXP);\n}\n\nintb NotExpression::getValue(ParserWalker &walker) const\n\n{\n intb val = getUnary()->getValue(walker);\n return ~val;\n}\n\nintb NotExpression::getSubValue(const vector &replace,int4 &listpos) const\n\n{\n intb val = getUnary()->getSubValue(replace,listpos);\n return ~val;\n}\n\nvoid NotExpression::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_NOT_EXP);\n UnaryExpression::encode(encoder);\n encoder.closeElement(sla::ELEM_NOT_EXP);\n}\n\nstatic bool advance_combo(vector &val,const vector &min,vector &max)\n\n{\n int4 i;\n\n i = 0;\n while(i &semval,\n\t\t\t\t vector &val)\n\n{\n TokenPattern respattern = lhs->genPattern(lhsval);\n\n for(int4 i=0;igenPattern(val[i]));\n return respattern;\n}\n\nvoid PatternEquation::release(PatternEquation *pateq)\n\n{\n pateq->refcount -= 1;\n if (pateq->refcount <= 0)\n delete pateq;\n}\n\nvoid OperandEquation::genPattern(const vector &ops) const\n\n{\n resultpattern = ops[index];\n}\n\nbool OperandEquation::resolveOperandLeft(OperandResolve &state) const\n\n{\n OperandSymbol *sym = state.operands[ index ];\n if (sym->isOffsetIrrelevant()) {\n sym->offsetbase = -1;\n sym->reloffset = 0;\n return true;\n }\n if (state.base == -2)\t\t// We have no base\n return false;\n sym->offsetbase = state.base;\n sym->reloffset = state.offset;\n state.cur_rightmost = index;\n state.size = 0;\t\t// Distance from right edge\n return true;\n}\n\nvoid OperandEquation::operandOrder(Constructor *ct,vector &order) const\n\n{\n OperandSymbol *sym = ct->getOperand(index);\n if (!sym->isMarked()) {\n order.push_back(sym);\n sym->setMark();\n }\n}\n\nUnconstrainedEquation::UnconstrainedEquation(PatternExpression *p)\n\n{\n (patex=p)->layClaim();\n}\n\nUnconstrainedEquation::~UnconstrainedEquation(void)\n\n{\n PatternExpression::release(patex);\n}\n\nvoid UnconstrainedEquation::genPattern(const vector &ops) const\n\n{\n resultpattern = patex->genMinPattern(ops);\n}\n\nbool UnconstrainedEquation::resolveOperandLeft(OperandResolve &state) const\n\n{\n state.cur_rightmost = -1;\n if (resultpattern.getLeftEllipsis()||resultpattern.getRightEllipsis()) // don't know length\n state.size = -1;\n else\n state.size = resultpattern.getMinimumLength();\n return true;\n}\n\nValExpressEquation::ValExpressEquation(PatternValue *l,PatternExpression *r)\n\n{\n (lhs=l)->layClaim();\n (rhs=r)->layClaim();\n}\n\nValExpressEquation::~ValExpressEquation(void)\n\n{\n PatternExpression::release(lhs);\n PatternExpression::release(rhs);\n}\n\nbool ValExpressEquation::resolveOperandLeft(OperandResolve &state) const\n\n{\n state.cur_rightmost = -1;\n if (resultpattern.getLeftEllipsis()||resultpattern.getRightEllipsis()) // don't know length\n state.size = -1;\n else\n state.size = resultpattern.getMinimumLength();\n return true;\n}\n\nvoid EqualEquation::genPattern(const vector &ops) const\n\n{\n intb lhsmin = lhs->minValue();\n intb lhsmax = lhs->maxValue();\n vector semval;\n vector min;\n vector max;\n vector cur;\n int4 count=0;\n\n rhs->listValues(semval);\n rhs->getMinMax(min,max);\n cur = min;\n\n do {\n intb val = rhs->getSubValue(cur);\n if ((val>=lhsmin)&&(val<=lhsmax)) {\n if (count==0)\n\tresultpattern = buildPattern(lhs,val,semval,cur);\n else\n\tresultpattern = resultpattern.doOr(buildPattern(lhs,val,semval,cur));\n count += 1;\n }\n } while(advance_combo(cur,min,max));\n if (count == 0)\n throw SleighError(\"Equal constraint is impossible to match\");\n}\n\nvoid NotEqualEquation::genPattern(const vector &ops) const\n\n{\n intb lhsmin = lhs->minValue();\n intb lhsmax = lhs->maxValue();\n vector semval;\n vector min;\n vector max;\n vector cur;\n int4 count=0;\n\n rhs->listValues(semval);\n rhs->getMinMax(min,max);\n cur = min;\n\n do {\n intb lhsval;\n intb val = rhs->getSubValue(cur);\n for(lhsval=lhsmin;lhsval<=lhsmax;++lhsval) {\n if (lhsval == val) continue;\n if (count==0)\n\tresultpattern = buildPattern(lhs,lhsval,semval,cur);\n else\n\tresultpattern = resultpattern.doOr(buildPattern(lhs,lhsval,semval,cur));\n count += 1;\n }\n } while(advance_combo(cur,min,max));\n if (count == 0)\n throw SleighError(\"Notequal constraint is impossible to match\");\n}\n\nvoid LessEquation::genPattern(const vector &ops) const\n\n{\n intb lhsmin = lhs->minValue();\n intb lhsmax = lhs->maxValue();\n vector semval;\n vector min;\n vector max;\n vector cur;\n int4 count=0;\n\n rhs->listValues(semval);\n rhs->getMinMax(min,max);\n cur = min;\n\n do {\n intb lhsval;\n intb val = rhs->getSubValue(cur);\n for(lhsval=lhsmin;lhsval<=lhsmax;++lhsval) {\n if (lhsval >= val) continue;\n if (count==0)\n\tresultpattern = buildPattern(lhs,lhsval,semval,cur);\n else\n\tresultpattern = resultpattern.doOr(buildPattern(lhs,lhsval,semval,cur));\n count += 1;\n }\n } while(advance_combo(cur,min,max));\n if (count == 0)\n throw SleighError(\"Less than constraint is impossible to match\");\n}\n\nvoid LessEqualEquation::genPattern(const vector &ops) const\n\n{\n intb lhsmin = lhs->minValue();\n intb lhsmax = lhs->maxValue();\n vector semval;\n vector min;\n vector max;\n vector cur;\n int4 count=0;\n\n rhs->listValues(semval);\n rhs->getMinMax(min,max);\n cur = min;\n\n do {\n intb lhsval;\n intb val = rhs->getSubValue(cur);\n for(lhsval=lhsmin;lhsval<=lhsmax;++lhsval) {\n if (lhsval > val) continue;\n if (count==0)\n\tresultpattern = buildPattern(lhs,lhsval,semval,cur);\n else\n\tresultpattern = resultpattern.doOr(buildPattern(lhs,lhsval,semval,cur));\n count += 1;\n }\n } while(advance_combo(cur,min,max));\n if (count == 0)\n throw SleighError(\"Less than or equal constraint is impossible to match\");\n}\n\nvoid GreaterEquation::genPattern(const vector &ops) const\n\n{\n intb lhsmin = lhs->minValue();\n intb lhsmax = lhs->maxValue();\n vector semval;\n vector min;\n vector max;\n vector cur;\n int4 count=0;\n\n rhs->listValues(semval);\n rhs->getMinMax(min,max);\n cur = min;\n\n do {\n intb lhsval;\n intb val = rhs->getSubValue(cur);\n for(lhsval=lhsmin;lhsval<=lhsmax;++lhsval) {\n if (lhsval <= val) continue;\n if (count==0)\n\tresultpattern = buildPattern(lhs,lhsval,semval,cur);\n else\n\tresultpattern = resultpattern.doOr(buildPattern(lhs,lhsval,semval,cur));\n count += 1;\n }\n } while(advance_combo(cur,min,max));\n if (count == 0)\n throw SleighError(\"Greater than constraint is impossible to match\");\n}\n\nvoid GreaterEqualEquation::genPattern(const vector &ops) const\n\n{\n intb lhsmin = lhs->minValue();\n intb lhsmax = lhs->maxValue();\n vector semval;\n vector min;\n vector max;\n vector cur;\n int4 count=0;\n\n rhs->listValues(semval);\n rhs->getMinMax(min,max);\n cur = min;\n\n do {\n intb lhsval;\n intb val = rhs->getSubValue(cur);\n for(lhsval=lhsmin;lhsval<=lhsmax;++lhsval) {\n if (lhsval < val) continue;\n if (count==0)\n\tresultpattern = buildPattern(lhs,lhsval,semval,cur);\n else\n\tresultpattern = resultpattern.doOr(buildPattern(lhs,lhsval,semval,cur));\n count += 1;\n }\n } while(advance_combo(cur,min,max));\n if (count == 0)\n throw SleighError(\"Greater than or equal constraint is impossible to match\");\n}\n\nEquationAnd::EquationAnd(PatternEquation *l,PatternEquation *r)\n\n{\n (left=l)->layClaim();\n (right=r)->layClaim();\n}\n\nEquationAnd::~EquationAnd(void)\n\n{\n PatternEquation::release(left);\n PatternEquation::release(right);\n}\n\nvoid EquationAnd::genPattern(const vector &ops) const\n\n{\n left->genPattern(ops);\n right->genPattern(ops);\n resultpattern = left->getTokenPattern().doAnd(right->getTokenPattern());\n}\n\nbool EquationAnd::resolveOperandLeft(OperandResolve &state) const\n\n{\n int4 cur_rightmost = -1;\t// Initially we don't know our rightmost\n int4 cur_size = -1;\t\t// or size traversed since rightmost\n bool res = right->resolveOperandLeft(state);\n if (!res) return false;\n if ((state.cur_rightmost != -1)&&(state.size != -1)) {\n cur_rightmost = state.cur_rightmost;\n cur_size = state.size;\n }\n res = left->resolveOperandLeft(state);\n if (!res) return false;\n if ((state.cur_rightmost == -1)||(state.size == -1)) {\n state.cur_rightmost = cur_rightmost;\n state.size = cur_size;\n }\n return true;\n}\n\nvoid EquationAnd::operandOrder(Constructor *ct,vector &order) const\n\n{\n left->operandOrder(ct,order);\t// List operands left\n right->operandOrder(ct,order); // to right\n}\n\nEquationOr::EquationOr(PatternEquation *l,PatternEquation *r)\n\n{\n (left=l)->layClaim();\n (right=r)->layClaim();\n}\n\nEquationOr::~EquationOr(void)\n\n{\n PatternEquation::release(left);\n PatternEquation::release(right);\n}\n\nvoid EquationOr::genPattern(const vector &ops) const\n\n{\n left->genPattern(ops);\n right->genPattern(ops);\n resultpattern = left->getTokenPattern().doOr(right->getTokenPattern());\n}\n\nbool EquationOr::resolveOperandLeft(OperandResolve &state) const\n\n{\n int4 cur_rightmost = -1;\t// Initially we don't know our rightmost\n int4 cur_size = -1;\t\t// or size traversed since rightmost\n bool res = right->resolveOperandLeft(state);\n if (!res) return false;\n if ((state.cur_rightmost != -1)&&(state.size != -1)) {\n cur_rightmost = state.cur_rightmost;\n cur_size = state.size;\n }\n res = left->resolveOperandLeft(state);\n if (!res) return false;\n if ((state.cur_rightmost == -1)||(state.size == -1)) {\n state.cur_rightmost = cur_rightmost;\n state.size = cur_size;\n }\n return true;\n}\n\nvoid EquationOr::operandOrder(Constructor *ct,vector &order) const\n\n{\n left->operandOrder(ct,order);\t// List operands left\n right->operandOrder(ct,order); // to right\n}\n\nEquationCat::EquationCat(PatternEquation *l,PatternEquation *r)\n\n{\n (left=l)->layClaim();\n (right=r)->layClaim();\n}\n\nEquationCat::~EquationCat(void)\n\n{\n PatternEquation::release(left);\n PatternEquation::release(right);\n}\n\nvoid EquationCat::genPattern(const vector &ops) const\n\n{\n left->genPattern(ops);\n right->genPattern(ops);\n resultpattern = left->getTokenPattern().doCat(right->getTokenPattern());\n}\n\nbool EquationCat::resolveOperandLeft(OperandResolve &state) const\n\n{\n bool res = left->resolveOperandLeft(state);\n if (!res) return false;\n int4 cur_base = state.base;\n int4 cur_offset = state.offset;\n if ((!left->getTokenPattern().getLeftEllipsis())&&(!left->getTokenPattern().getRightEllipsis())) {\n // Keep the same base\n state.offset += left->getTokenPattern().getMinimumLength(); // But add to its size\n }\n else if (state.cur_rightmost != -1) {\n state.base = state.cur_rightmost;\n state.offset = state.size;\n }\n else if (state.size != -1) {\n state.offset += state.size;\n }\n else {\n state.base = -2;\t\t// We have no anchor\n }\n int4 cur_rightmost = state.cur_rightmost;\n int4 cur_size = state.size;\n res = right->resolveOperandLeft(state);\n if (!res) return false;\n state.base = cur_base;\t// Restore base and offset\n state.offset = cur_offset;\n if (state.cur_rightmost == -1) {\n if ((state.size != -1)&&(cur_rightmost != -1)&&(cur_size != -1)) {\n state.cur_rightmost = cur_rightmost;\n state.size += cur_size;\n }\n }\n return true;\n}\n\nvoid EquationCat::operandOrder(Constructor *ct,vector &order) const\n\n{\n left->operandOrder(ct,order);\t// List operands left\n right->operandOrder(ct,order); // to right\n}\n\nvoid EquationLeftEllipsis::genPattern(const vector &ops) const\n\n{\n eq->genPattern(ops);\n resultpattern = eq->getTokenPattern();\n resultpattern.setLeftEllipsis(true);\n}\n\nbool EquationLeftEllipsis::resolveOperandLeft(OperandResolve &state) const\n\n{\n int4 cur_base = state.base;\n state.base = -2;\n bool res = eq->resolveOperandLeft(state);\n if (!res) return false;\n state.base = cur_base;\n \n return true;\n}\n\nvoid EquationLeftEllipsis::operandOrder(Constructor *ct,vector &order) const\n\n{\n eq->operandOrder(ct,order);\t// List operands\n}\n\nvoid EquationRightEllipsis::genPattern(const vector &ops) const\n\n{\n eq->genPattern(ops);\n resultpattern = eq->getTokenPattern();\n resultpattern.setRightEllipsis(true);\n}\n\nbool EquationRightEllipsis::resolveOperandLeft(OperandResolve &state) const\n\n{\n bool res = eq->resolveOperandLeft(state);\n if (!res) return false;\n state.size = -1;\t\t// Cannot predict size\n return true;\n}\n\nvoid EquationRightEllipsis::operandOrder(Constructor *ct,vector &order) const\n\n{\n eq->operandOrder(ct,order);\t// List operands\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/slghpatexpress.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __SLGHPATEXPRESS_HH__\n#define __SLGHPATEXPRESS_HH__\n\n#include \"slghpattern.hh\"\n\nnamespace ghidra {\n\nclass TokenPattern {\n Pattern *pattern;\n vector toklist;\n bool leftellipsis;\n bool rightellipsis;\n static PatternBlock *buildSingle(int4 startbit,int4 endbit,uintm byteval);\n static PatternBlock *buildBigBlock(int4 size,int4 bitstart,int4 bitend,intb value);\n static PatternBlock *buildLittleBlock(int4 size,int4 bitstart,int4 bitend,intb value);\n int4 resolveTokens(const TokenPattern &tokpat1,const TokenPattern &tokpat2);\n TokenPattern(Pattern *pat) { pattern = pat; leftellipsis=false; rightellipsis=false; }\npublic:\n TokenPattern(void);\t\t// TRUE pattern unassociated with a token\n TokenPattern(bool tf);\t// TRUE or FALSE pattern unassociated with a token\n TokenPattern(Token *tok);\t// TRUE pattern associated with token -tok-\n TokenPattern(Token *tok,intb value,int4 bitstart,int4 bitend);\n TokenPattern(intb value,int4 startbit,int4 endbit);\n TokenPattern(const TokenPattern &tokpat);\n ~TokenPattern(void) { delete pattern; }\n const TokenPattern &operator=(const TokenPattern &tokpat);\n void setLeftEllipsis(bool val) { leftellipsis = val; }\n void setRightEllipsis(bool val) { rightellipsis = val; }\n bool getLeftEllipsis(void) const { return leftellipsis; }\n bool getRightEllipsis(void) const { return rightellipsis; }\n TokenPattern doAnd(const TokenPattern &tokpat) const;\n TokenPattern doOr(const TokenPattern &tokpat) const;\n TokenPattern doCat(const TokenPattern &tokpat) const;\n TokenPattern commonSubPattern(const TokenPattern &tokpat) const;\n Pattern *getPattern(void) const { return pattern; }\n int4 getMinimumLength(void) const;\n bool alwaysTrue(void) const { return pattern->alwaysTrue(); }\n bool alwaysFalse(void) const { return pattern->alwaysFalse(); }\n bool alwaysInstructionTrue(void) const { return pattern->alwaysInstructionTrue(); }\n};\n\nclass PatternValue;\nclass PatternExpression {\n int4 refcount;\t\t\t// Number of objects referencing this\n\t\t\t\t// for deletion\nprotected:\n virtual ~PatternExpression(void) {} // Only delete through release\npublic:\n PatternExpression(void) { refcount = 0; }\n virtual intb getValue(ParserWalker &walker) const=0;\n virtual TokenPattern genMinPattern(const vector &ops) const=0;\n virtual void listValues(vector &list) const=0;\n virtual void getMinMax(vector &minlist,vector &maxlist) const=0;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const=0;\n virtual void encode(Encoder &encoder) const=0;\n virtual void decode(Decoder &decoder,Translate *trans)=0;\n intb getSubValue(const vector &replace) {\n int4 listpos = 0;\n return getSubValue(replace,listpos); }\n void layClaim(void) { refcount += 1; }\n static void release(PatternExpression *p);\n static PatternExpression *decodeExpression(Decoder &decoder,Translate *trans);\n};\n\nclass PatternValue : public PatternExpression {\npublic:\n virtual TokenPattern genPattern(intb val) const=0;\n virtual void listValues(vector &list) const { list.push_back(this); }\n virtual void getMinMax(vector &minlist,vector &maxlist) const { \n minlist.push_back(minValue()); maxlist.push_back(maxValue()); }\n virtual intb getSubValue(const vector &replace,int4 &listpos) const { return replace[listpos++]; }\n virtual intb minValue(void) const=0;\n virtual intb maxValue(void) const=0;\n};\n\nclass TokenField : public PatternValue {\n Token *tok;\n bool bigendian;\n bool signbit;\n int4 bitstart,bitend;\t\t// Bits within the token, 0 bit is LEAST significant\n int4 bytestart,byteend;\t// Bytes to read to get value\n int4 shift;\t\t\t// Amount to shift to align value (bitstart % 8)\npublic:\n TokenField(void) {}\t\t// For use with decode\n TokenField(Token *tk,bool s,int4 bstart,int4 bend);\n virtual intb getValue(ParserWalker &walker) const;\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(tok); }\n virtual TokenPattern genPattern(intb val) const;\n virtual intb minValue(void) const { return 0; }\n virtual intb maxValue(void) const { intb res=0; return zero_extend(~res,bitend-bitstart); }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass ContextField : public PatternValue {\n int4 startbit,endbit;\n int4 startbyte,endbyte;\n int4 shift;\n bool signbit;\npublic:\n ContextField(void) {}\t\t// For use with decode\n ContextField(bool s,int4 sbit,int4 ebit);\n int4 getStartBit(void) const { return startbit; }\n int4 getEndBit(void) const { return endbit; }\n bool getSignBit(void) const { return signbit; }\n virtual intb getValue(ParserWalker &walker) const;\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual TokenPattern genPattern(intb val) const;\n virtual intb minValue(void) const { return 0; }\n virtual intb maxValue(void) const { intb res=0; return zero_extend(~res,(endbit-startbit)); }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass ConstantValue : public PatternValue {\n intb val;\npublic:\n ConstantValue(void) {}\t// For use with decode\n ConstantValue(intb v) { val = v; }\n virtual intb getValue(ParserWalker &walker) const { return val; }\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual TokenPattern genPattern(intb v) const { return TokenPattern(val==v); }\n virtual intb minValue(void) const { return val; }\n virtual intb maxValue(void) const { return val; }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass StartInstructionValue : public PatternValue {\npublic:\n StartInstructionValue(void) {}\n virtual intb getValue(ParserWalker &walker) const {\n return (intb)AddrSpace::byteToAddress(walker.getAddr().getOffset(),walker.getAddr().getSpace()->getWordSize()); }\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual TokenPattern genPattern(intb val) const { return TokenPattern(); }\n virtual intb minValue(void) const { return (intb)0; }\n virtual intb maxValue(void) const { return (intb)0; }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n \nclass EndInstructionValue : public PatternValue {\npublic:\n EndInstructionValue(void) {}\n virtual intb getValue(ParserWalker &walker) const {\n return (intb)AddrSpace::byteToAddress(walker.getNaddr().getOffset(),walker.getNaddr().getSpace()->getWordSize()); }\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual TokenPattern genPattern(intb val) const { return TokenPattern(); }\n virtual intb minValue(void) const { return (intb)0; }\n virtual intb maxValue(void) const { return (intb)0; }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass Next2InstructionValue : public PatternValue {\npublic:\n Next2InstructionValue(void) {}\n virtual intb getValue(ParserWalker &walker) const {\n return (intb)AddrSpace::byteToAddress(walker.getN2addr().getOffset(),walker.getN2addr().getSpace()->getWordSize()); }\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual TokenPattern genPattern(intb val) const { return TokenPattern(); }\n virtual intb minValue(void) const { return (intb)0; }\n virtual intb maxValue(void) const { return (intb)0; }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass Constructor;\t\t// Forward declaration\nclass OperandSymbol;\nclass OperandValue : public PatternValue {\n int4 index;\t\t\t// This is the defining field of expression\n Constructor *ct;\t\t// cached pointer to constructor\npublic:\n OperandValue(void) { } // For use with decode\n OperandValue(int4 ind,Constructor *c) { index = ind; ct = c; }\n void changeIndex(int4 newind) { index = newind; }\n bool isConstructorRelative(void) const;\n const string &getName(void) const;\n virtual TokenPattern genPattern(intb val) const;\n virtual TokenPattern genMinPattern(const vector &ops) const { return ops[index]; }\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual intb minValue(void) const;\n virtual intb maxValue(void) const;\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass BinaryExpression : public PatternExpression {\n PatternExpression *left,*right;\nprotected:\n virtual ~BinaryExpression(void);\npublic:\n BinaryExpression(void) { left = (PatternExpression *)0; right = (PatternExpression *)0; } // For use with decode\n BinaryExpression(PatternExpression *l,PatternExpression *r);\n PatternExpression *getLeft(void) const { return left; }\n PatternExpression *getRight(void) const { return right; }\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual void listValues(vector &list) const {\n left->listValues(list); right->listValues(list); }\n virtual void getMinMax(vector &minlist,vector &maxlist) const {\n left->getMinMax(minlist,maxlist); right->getMinMax(minlist,maxlist); }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n};\n\nclass UnaryExpression : public PatternExpression {\n PatternExpression *unary;\nprotected:\n virtual ~UnaryExpression(void);\npublic:\n UnaryExpression(void) { unary = (PatternExpression *)0; } // For use with decode\n UnaryExpression(PatternExpression *u);\n PatternExpression *getUnary(void) const { return unary; }\n virtual TokenPattern genMinPattern(const vector &ops) const { return TokenPattern(); }\n virtual void listValues(vector &list) const {\n unary->listValues(list); }\n virtual void getMinMax(vector &minlist,vector &maxlist) const {\n unary->getMinMax(minlist,maxlist);\n }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,Translate *trans);\n}; \n\nclass PlusExpression : public BinaryExpression {\npublic:\n PlusExpression(void) {}\t// For use by decode\n PlusExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n \nclass SubExpression : public BinaryExpression {\npublic:\n SubExpression(void) {}\t// For use with decode\n SubExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n \nclass MultExpression : public BinaryExpression {\npublic:\n MultExpression(void) {}\t// For use with decode\n MultExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n \nclass LeftShiftExpression : public BinaryExpression {\npublic:\n LeftShiftExpression(void) {}\n LeftShiftExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n\nclass RightShiftExpression : public BinaryExpression {\npublic:\n RightShiftExpression(void) {}\n RightShiftExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n\nclass AndExpression : public BinaryExpression {\npublic:\n AndExpression(void) {}\n AndExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n \nclass OrExpression : public BinaryExpression {\npublic:\n OrExpression(void) {}\n OrExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n \nclass XorExpression : public BinaryExpression {\npublic:\n XorExpression(void) {}\n XorExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n\nclass DivExpression : public BinaryExpression {\npublic:\n DivExpression(void) {}\n DivExpression(PatternExpression *l,PatternExpression *r) : BinaryExpression(l,r) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n};\n\nclass MinusExpression : public UnaryExpression {\npublic:\n MinusExpression(void) {}\n MinusExpression(PatternExpression *u) : UnaryExpression(u) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n}; \n\nclass NotExpression : public UnaryExpression {\npublic:\n NotExpression(void) {}\n NotExpression(PatternExpression *u) : UnaryExpression(u) {}\n virtual intb getValue(ParserWalker &walker) const;\n virtual intb getSubValue(const vector &replace,int4 &listpos) const;\n virtual void encode(Encoder &encoder) const;\n}; \n\nstruct OperandResolve {\n vector &operands;\n OperandResolve(vector &ops) : operands(ops) {\n base=-1; offset=0; cur_rightmost = -1; size = 0; }\n int4 base;\t\t// Current base operand (as we traverse the pattern equation from left to right)\n int4 offset;\t\t// Bytes we have traversed from the LEFT edge of the current base\n int4 cur_rightmost;\t// (resulting) rightmost operand in our pattern\n int4 size;\t\t// (resulting) bytes traversed from the LEFT edge of the rightmost\n};\n\n// operandOrder returns a vector of the self-defining OperandSymbols as the appear\n// in left to right order in the pattern\nclass PatternEquation {\n int4 refcount;\t\t\t// Number of objects referencing this\nprotected:\n mutable TokenPattern resultpattern; // Resulting pattern generated by this equation\n virtual ~PatternEquation(void) {} // Only delete through release\npublic:\n PatternEquation(void) { refcount = 0; }\n const TokenPattern &getTokenPattern(void) const { return resultpattern; }\n virtual void genPattern(const vector &ops) const=0;\n virtual bool resolveOperandLeft(OperandResolve &state) const=0;\n virtual void operandOrder(Constructor *ct,vector &order) const {}\n void layClaim(void) { refcount += 1; }\n static void release(PatternEquation *pateq);\n};\n\nclass OperandEquation : public PatternEquation { // Equation that defines operand\n int4 index;\npublic:\n OperandEquation(int4 ind) { index = ind; }\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n virtual void operandOrder(Constructor *ct,vector &order) const;\n};\n\nclass UnconstrainedEquation : public PatternEquation { // Unconstrained equation, just get tokens\n PatternExpression *patex;\nprotected:\n virtual ~UnconstrainedEquation(void);\npublic:\n UnconstrainedEquation(PatternExpression *p);\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n};\n\nclass ValExpressEquation : public PatternEquation {\nprotected:\n PatternValue *lhs;\n PatternExpression *rhs;\n virtual ~ValExpressEquation(void);\npublic:\n ValExpressEquation(PatternValue *l,PatternExpression *r);\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n};\n\nclass EqualEquation : public ValExpressEquation {\npublic:\n EqualEquation(PatternValue *l,PatternExpression *r) : ValExpressEquation(l,r) {}\n virtual void genPattern(const vector &ops) const;\n};\n\nclass NotEqualEquation : public ValExpressEquation {\npublic:\n NotEqualEquation(PatternValue *l,PatternExpression *r) : ValExpressEquation(l,r) {}\n virtual void genPattern(const vector &ops) const;\n};\n\nclass LessEquation : public ValExpressEquation {\npublic:\n LessEquation(PatternValue *l,PatternExpression *r) : ValExpressEquation(l,r) {}\n virtual void genPattern(const vector &ops) const;\n};\n\nclass LessEqualEquation : public ValExpressEquation {\npublic:\n LessEqualEquation(PatternValue *l,PatternExpression *r) : ValExpressEquation(l,r) {}\n virtual void genPattern(const vector &ops) const;\n};\n\nclass GreaterEquation : public ValExpressEquation {\npublic:\n GreaterEquation(PatternValue *l,PatternExpression *r) : ValExpressEquation(l,r) {}\n virtual void genPattern(const vector &ops) const;\n};\n\nclass GreaterEqualEquation : public ValExpressEquation {\npublic:\n GreaterEqualEquation(PatternValue *l,PatternExpression *r) : ValExpressEquation(l,r) {}\n virtual void genPattern(const vector &ops) const;\n};\n\nclass EquationAnd : public PatternEquation { // Pattern Equations ANDed together\n PatternEquation *left;\n PatternEquation *right;\nprotected:\n virtual ~EquationAnd(void);\npublic:\n EquationAnd(PatternEquation *l,PatternEquation *r);\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n virtual void operandOrder(Constructor *ct,vector &order) const;\n};\n\nclass EquationOr : public PatternEquation { // Pattern Equations ORed together\n PatternEquation *left;\n PatternEquation *right;\nprotected:\n virtual ~EquationOr(void);\npublic:\n EquationOr(PatternEquation *l,PatternEquation *r);\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n virtual void operandOrder(Constructor *ct,vector &order) const;\n};\n\nclass EquationCat : public PatternEquation { // Pattern Equations concatenated\n PatternEquation *left;\n PatternEquation *right;\nprotected:\n virtual ~EquationCat(void);\npublic:\n EquationCat(PatternEquation *l,PatternEquation *r);\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n virtual void operandOrder(Constructor *ct,vector &order) const;\n};\n\nclass EquationLeftEllipsis : public PatternEquation { // Equation preceded by ellipses\n PatternEquation *eq;\nprotected:\n virtual ~EquationLeftEllipsis(void) { PatternEquation::release(eq); }\npublic:\n EquationLeftEllipsis(PatternEquation *e) { (eq=e)->layClaim(); }\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n virtual void operandOrder(Constructor *ct,vector &order) const;\n};\n\nclass EquationRightEllipsis : public PatternEquation { // Equation preceded by ellipses\n PatternEquation *eq;\nprotected:\n virtual ~EquationRightEllipsis(void) { PatternEquation::release(eq); }\npublic:\n EquationRightEllipsis(PatternEquation *e) { (eq=e)->layClaim(); }\n virtual void genPattern(const vector &ops) const;\n virtual bool resolveOperandLeft(OperandResolve &state) const;\n virtual void operandOrder(Constructor *ct,vector &order) const;\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/slghpattern.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"slghpattern.hh\"\n#include \"slaformat.hh\"\n\nnamespace ghidra {\n\nuintm DisjointPattern::getMask(int4 startbit,int4 size,bool context) const\n\n{\n PatternBlock *block = getBlock(context);\n if (block != (PatternBlock *)0)\n return block->getMask(startbit,size);\n return 0;\n}\n\nuintm DisjointPattern::getValue(int4 startbit,int4 size,bool context) const\n\n{\n PatternBlock *block = getBlock(context);\n if (block != (PatternBlock *)0)\n return block->getValue(startbit,size);\n return 0;\n}\n\nint4 DisjointPattern::getLength(bool context) const\n\n{\n PatternBlock *block = getBlock(context);\n if (block != (PatternBlock *)0)\n return block->getLength();\n return 0;\n}\n\nbool DisjointPattern::specializes(const DisjointPattern *op2) const\n\n{\t\t\t\t// Return true, if everywhere this's mask is non-zero\n\t\t\t\t// op2's mask is non-zero and op2's value match this's\n PatternBlock *a,*b;\n\n a = getBlock(false);\n b = op2->getBlock(false);\n if ((b != (PatternBlock *)0)&&(!b->alwaysTrue())) {\t// a must match existing block\n if (a == (PatternBlock *)0) return false;\n if (!a->specializes(b)) return false;\n }\n a = getBlock(true);\n b = op2->getBlock(true);\n if ((b != (PatternBlock *)0)&&(!b->alwaysTrue())) {\t// a must match existing block\n if (a == (PatternBlock *)0) return false;\n if (!a->specializes(b)) return false;\n }\n return true;\n}\n\nbool DisjointPattern::identical(const DisjointPattern *op2) const\n\n{\t\t\t\t// Return true if patterns match exactly\n PatternBlock *a,*b;\n \n a = getBlock(false);\n b = op2->getBlock(false);\n if (b != (PatternBlock *)0) {\t// a must match existing block\n if (a == (PatternBlock *)0) {\n if (!b->alwaysTrue())\n\treturn false;\n }\n else if (!a->identical(b))\n return false;\n }\n else {\n if ((a != (PatternBlock *)0)&&(!a->alwaysTrue()))\n return false;\n }\n a = getBlock(true);\n b = op2->getBlock(true);\n if (b != (PatternBlock *)0) {\t// a must match existing block\n if (a == (PatternBlock *)0) {\n if (!b->alwaysTrue())\n\treturn false;\n }\n else if (!a->identical(b))\n return false;\n }\n else {\n if ((a != (PatternBlock *)0)&&(!a->alwaysTrue()))\n return false;\n }\n return true;\n}\n\nstatic bool resolveIntersectBlock(PatternBlock *bl1,PatternBlock *bl2,PatternBlock *thisblock)\n\n{\n PatternBlock *inter;\n bool allocated = false;\n bool res = true;\n\n if (bl1 == (PatternBlock *)0)\n inter = bl2;\n else if (bl2 == (PatternBlock *)0)\n inter = bl1;\n else {\n allocated = true;\n inter = bl1->intersect(bl2);\n }\n if (inter == (PatternBlock *)0) {\n if (thisblock != (PatternBlock *)0)\n res = false;\n }\n else if (thisblock == (PatternBlock *)0)\n res = false;\n else\n res = thisblock->identical(inter);\n if (allocated)\n delete inter;\n return res;\n}\n\nbool DisjointPattern::resolvesIntersect(const DisjointPattern *op1,const DisjointPattern *op2) const\n\n{ // Is this pattern equal to the intersection of -op1- and -op2-\n if (!resolveIntersectBlock(op1->getBlock(false),op2->getBlock(false),getBlock(false)))\n return false;\n return resolveIntersectBlock(op1->getBlock(true),op2->getBlock(true),getBlock(true));\n}\n\nDisjointPattern *DisjointPattern::decodeDisjoint(Decoder &decoder)\n\n{\t\t\t\t// DisjointPattern factory\n DisjointPattern *res;\n uint4 el = decoder.peekElement();\n if (el == sla::ELEM_INSTRUCT_PAT)\n res = new InstructionPattern();\n else if (el == sla::ELEM_CONTEXT_PAT)\n res = new ContextPattern();\n else\n res = new CombinePattern();\n res->decode(decoder);\n return res;\n}\n\nvoid PatternBlock::normalize(void)\n\n{\n if (nonzerosize<=0) {\t\t// Check if alwaystrue or alwaysfalse\n offset = 0;\t\t\t// in which case we don't need mask and value\n maskvec.clear();\n valvec.clear();\n return;\n }\n vector::iterator iter1,iter2;\n \n iter1 = maskvec.begin();\t// Cut zeros from beginning of mask\n iter2 = valvec.begin();\n while((iter1 != maskvec.end())&&((*iter1)==0)) {\n iter1++;\n iter2++;\n offset += sizeof(uintm);\n }\n maskvec.erase(maskvec.begin(),iter1);\n valvec.erase(valvec.begin(),iter2);\n\n if (!maskvec.empty()) {\n int4 suboff = 0;\t\t// Cut off unaligned zeros from beginning of mask\n uintm tmp = maskvec[0];\n while(tmp != 0) {\n suboff += 1;\n tmp >>= 8;\n }\n suboff = sizeof(uintm)-suboff;\n if (suboff != 0) {\n offset += suboff;\t\t// Slide up maskvec by suboff bytes\n for(int4 i=0;i> ((sizeof(uintm)-suboff)*8));\n\tmaskvec[i] = tmp;\n }\n maskvec.back() <<= suboff*8;\n for(int4 i=0;i> ((sizeof(uintm)-suboff)*8));\n\tvalvec[i] = tmp;\n }\n valvec.back() <<= suboff*8;\n }\n \n iter1 = maskvec.end();\t// Cut zeros from end of mask\n iter2 = valvec.end();\n while(iter1 != maskvec.begin()) {\n --iter1;\n --iter2;\n if ((*iter1) != 0) break; // Find last non-zero\n }\n if (iter1 != maskvec.end()) {\n iter1++;\t\t\t// Find first zero, in last zero chain\n iter2++;\n }\n maskvec.erase(iter1,maskvec.end());\n valvec.erase(iter2,valvec.end());\n }\n\n if (maskvec.empty()) {\n offset = 0;\n nonzerosize = 0;\t\t// Always true\n return;\n }\n nonzerosize = maskvec.size() * sizeof(uintm);\n uintm tmp = maskvec.back();\t// tmp must be nonzero\n while( (tmp&0xff) == 0) {\n nonzerosize -= 1;\n tmp >>= 8;\n }\n}\n\nPatternBlock::PatternBlock(int4 off,uintm msk,uintm val)\n\n{\t\t\t\t// Define mask and value pattern, confined to one uintm\n offset = off;\n maskvec.push_back(msk);\n valvec.push_back(val);\n nonzerosize = sizeof(uintm);\t// Assume all non-zero bytes before normalization\n normalize();\n}\n\nPatternBlock::PatternBlock(bool tf)\n\n{\n offset = 0;\n if (tf)\n nonzerosize = 0;\n else\n nonzerosize = -1;\n}\n\nPatternBlock::PatternBlock(const PatternBlock *a,const PatternBlock *b)\n\n{\t\t\t\t// Construct PatternBlock by ANDing two others together\n PatternBlock *res = a->intersect(b);\n offset = res->offset;\n nonzerosize = res->nonzerosize;\n maskvec = res->maskvec;\n valvec = res->valvec;\n delete res;\n}\n\nPatternBlock::PatternBlock(vector &list)\n\n{\t\t\t\t// AND several blocks together to construct new block\n PatternBlock *res,*next;\n\n if (list.empty()) {\t\t// If not ANDing anything\n offset = 0;\t\t\t// make constructed block always true\n nonzerosize = 0;\n return;\n }\n res = list[0];\n for(int4 i=1;iintersect(list[i]);\n delete res;\n res = next;\n }\n offset = res->offset;\n nonzerosize = res->nonzerosize;\n maskvec = res->maskvec;\n valvec = res->valvec;\n delete res;\n}\n\nPatternBlock *PatternBlock::clone(void) const\n\n{\n PatternBlock *res = new PatternBlock(true);\n\n res->offset = offset;\n res->nonzerosize = nonzerosize;\n res->maskvec = maskvec;\n res->valvec = valvec;\n return res;\n}\n\nPatternBlock *PatternBlock::commonSubPattern(const PatternBlock *b) const\n\n{\t\t\t\t// The resulting pattern has a 1-bit in the mask\n\t\t\t\t// only if the two pieces have a 1-bit and the\n\t\t\t\t// values agree\n PatternBlock *res = new PatternBlock(true);\n int4 maxlength = (getLength() > b->getLength()) ? getLength() : b->getLength();\n\n res->offset = 0;\n int4 offset = 0;\n uintm mask1,val1,mask2,val2;\n uintm resmask,resval;\n while(offset < maxlength) {\n mask1 = getMask(offset*8,sizeof(uintm)*8);\n val1 = getValue(offset*8,sizeof(uintm)*8);\n mask2 = b->getMask(offset*8,sizeof(uintm)*8);\n val2 = b->getValue(offset*8,sizeof(uintm)*8);\n resmask = mask1 & mask2 & ~(val1^val2);\n resval = val1 & val2 & resmask;\n res->maskvec.push_back(resmask);\n res->valvec.push_back(resval);\n offset += sizeof(uintm);\n }\n res->nonzerosize = maxlength;\n res->normalize();\n return res;\n}\n\nPatternBlock *PatternBlock::intersect(const PatternBlock *b) const\n\n{ // Construct the intersecting pattern\n if (alwaysFalse() || b->alwaysFalse())\n return new PatternBlock(false);\n PatternBlock *res = new PatternBlock(true);\n int4 maxlength = (getLength() > b->getLength()) ? getLength() : b->getLength();\n\n res->offset = 0;\n int4 offset = 0;\n uintm mask1,val1,mask2,val2,commonmask;\n uintm resmask,resval;\n while(offset < maxlength) {\n mask1 = getMask(offset*8,sizeof(uintm)*8);\n val1 = getValue(offset*8,sizeof(uintm)*8);\n mask2 = b->getMask(offset*8,sizeof(uintm)*8);\n val2 = b->getValue(offset*8,sizeof(uintm)*8);\n commonmask = mask1 & mask2;\t// Bits in mask shared by both patterns\n if ((commonmask & val1) != (commonmask & val2)) {\n res->nonzerosize = -1;\t// Impossible pattern\n res->normalize();\n return res;\n }\n resmask = mask1 | mask2;\n resval = (mask1 & val1) | (mask2 & val2);\n res->maskvec.push_back(resmask);\n res->valvec.push_back(resval);\n offset += sizeof(uintm);\n }\n res->nonzerosize = maxlength;\n res->normalize();\n return res;\n}\n\nbool PatternBlock::specializes(const PatternBlock *op2) const\n\n{\t\t\t\t// does every masked bit in -this- match the corresponding\n\t\t\t\t// masked bit in -op2-\n int4 length = 8*op2->getLength();\n int4 tmplength;\n uintm mask1,mask2,value1,value2;\n int4 sbit = 0;\n while(sbit < length) {\n tmplength = length-sbit;\n if (tmplength > 8*sizeof(uintm))\n tmplength = 8*sizeof(uintm);\n mask1 = getMask(sbit,tmplength);\n value1 = getValue(sbit,tmplength);\n mask2 = op2->getMask(sbit,tmplength);\n value2 = op2->getValue(sbit,tmplength);\n if ((mask1 & mask2) != mask2) return false;\n if ((value1 & mask2) != (value2 & mask2)) return false;\n sbit += tmplength;\n }\n return true;\n}\n\nbool PatternBlock::identical(const PatternBlock *op2) const\n\n{\t\t\t\t// Do the mask and value match exactly\n int4 tmplength;\n int4 length = 8*op2->getLength();\n tmplength = 8*getLength();\n if (tmplength > length)\n length = tmplength;\t\t// Maximum of two lengths\n uintm mask1,mask2,value1,value2;\n int4 sbit = 0;\n while(sbit < length) {\n tmplength = length-sbit;\n if (tmplength > 8*sizeof(uintm))\n tmplength = 8*sizeof(uintm);\n mask1 = getMask(sbit,tmplength);\n value1 = getValue(sbit,tmplength);\n mask2 = op2->getMask(sbit,tmplength);\n value2 = op2->getValue(sbit,tmplength);\n if (mask1 != mask2) return false;\n if ((mask1&value1) != (mask2&value2)) return false;\n sbit += tmplength;\n }\n return true;\n}\n\nuintm PatternBlock::getMask(int4 startbit,int4 size) const\n\n{\n startbit -= 8*offset;\n // Note the division and remainder here is unsigned. Then it is recast to signed. \n // If startbit is negative, then wordnum1 is either negative or very big,\n // if (unsigned size is same as sizeof int)\n // In either case, shift should come out between 0 and 8*sizeof(uintm)-1\n int4 wordnum1 = startbit/(8*sizeof(uintm));\n int4 shift = startbit % (8*sizeof(uintm));\n int4 wordnum2 = (startbit+size-1)/(8*sizeof(uintm));\n uintm res;\n\n if ((wordnum1<0)||(wordnum1>=maskvec.size()))\n res = 0;\n else\n res = maskvec[wordnum1];\n\n res <<= shift;\n if (wordnum1 != wordnum2) {\n uintm tmp;\n if ((wordnum2<0)||(wordnum2>=maskvec.size()))\n tmp = 0;\n else\n tmp = maskvec[wordnum2];\n res |= (tmp>>(8*sizeof(uintm)-shift));\n }\n res >>= (8*sizeof(uintm) - size);\n \n return res;\n}\n\nuintm PatternBlock::getValue(int4 startbit,int4 size) const\n\n{\n startbit -= 8*offset;\n int4 wordnum1 = startbit/(8*sizeof(uintm));\n int4 shift = startbit % (8*sizeof(uintm));\n int4 wordnum2 = (startbit+size-1)/(8*sizeof(uintm));\n uintm res;\n\n if ((wordnum1<0)||(wordnum1>=valvec.size()))\n res = 0;\n else\n res = valvec[wordnum1];\n res <<= shift;\n if (wordnum1 != wordnum2) {\n uintm tmp;\n if ((wordnum2<0)||(wordnum2>=valvec.size()))\n tmp = 0;\n else\n tmp = valvec[wordnum2];\n res |= (tmp>>(8*sizeof(uintm)-shift));\n }\n res >>= (8*sizeof(uintm) - size);\n \n return res;\n}\n\nbool PatternBlock::isInstructionMatch(ParserWalker &walker) const\n\n{\n if (nonzerosize<=0) return (nonzerosize==0);\n int4 off = offset;\n for(int4 i=0;inumDisjoint()>0)\n return b->doAnd(this,-sa);\n\n const CombinePattern *b2 = dynamic_cast(b);\n if (b2 != (const CombinePattern *)0)\n return b->doAnd(this,-sa);\n\n const ContextPattern *b3 = dynamic_cast(b);\n if (b3 != (const ContextPattern *)0) {\n InstructionPattern *newpat = (InstructionPattern *)simplifyClone();\n if (sa < 0)\n newpat->shiftInstruction(-sa);\n return new CombinePattern((ContextPattern *)b3->simplifyClone(),newpat);\n }\n const InstructionPattern *b4 = (const InstructionPattern *)b;\n\n PatternBlock *respattern;\n if (sa < 0) {\n PatternBlock *a = maskvalue->clone();\n a->shift(-sa);\n respattern = a->intersect(b4->maskvalue);\n delete a;\n }\n else {\n PatternBlock *c = b4->maskvalue->clone();\n c->shift(sa);\n respattern = maskvalue->intersect(c);\n delete c;\n }\n return new InstructionPattern(respattern);\n}\n\nPattern *InstructionPattern::commonSubPattern(const Pattern *b,int4 sa) const\n\n{\n if (b->numDisjoint()>0)\n return b->commonSubPattern(this,-sa);\n\n const CombinePattern *b2 = dynamic_cast(b);\n if (b2 != (const CombinePattern *)0)\n return b->commonSubPattern(this,-sa);\n\n const ContextPattern *b3 = dynamic_cast(b);\n if (b3 != (const ContextPattern *)0) {\n InstructionPattern *res = new InstructionPattern(true);\n return res;\n }\n const InstructionPattern *b4 = (const InstructionPattern *)b;\n \n PatternBlock *respattern;\n if (sa < 0) {\n PatternBlock *a = maskvalue->clone();\n a->shift(-sa);\n respattern = a->commonSubPattern(b4->maskvalue);\n delete a;\n }\n else {\n PatternBlock *c = b4->maskvalue->clone();\n c->shift(sa);\n respattern = maskvalue->commonSubPattern(c);\n delete c;\n }\n return new InstructionPattern(respattern);\n}\n\nPattern *InstructionPattern::doOr(const Pattern *b,int4 sa) const\n\n{\n if (b->numDisjoint()>0)\n return b->doOr(this,-sa);\n\n const CombinePattern *b2 = dynamic_cast(b);\n if (b2 != (const CombinePattern *)0)\n return b->doOr(this,-sa);\n\n DisjointPattern *res1,*res2;\n res1 = (DisjointPattern *)simplifyClone();\n res2 = (DisjointPattern *)b->simplifyClone();\n if (sa < 0)\n res1->shiftInstruction(-sa);\n else\n res2->shiftInstruction(sa);\n return new OrPattern(res1,res2);\n}\n\nvoid InstructionPattern::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_INSTRUCT_PAT);\n maskvalue->encode(encoder);\n encoder.closeElement(sla::ELEM_INSTRUCT_PAT);\n}\n\nvoid InstructionPattern::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_INSTRUCT_PAT);\n maskvalue = new PatternBlock(true);\n maskvalue->decode(decoder);\n decoder.closeElement(el);\n}\n\nPattern *ContextPattern::doOr(const Pattern *b,int4 sa) const\n\n{\n const ContextPattern *b2 = dynamic_cast(b);\n if (b2 == (const ContextPattern *)0)\n return b->doOr(this,-sa);\n\n return new OrPattern((DisjointPattern *)simplifyClone(),(DisjointPattern *)b2->simplifyClone());\n}\n\nPattern *ContextPattern::doAnd(const Pattern *b,int4 sa) const\n\n{\n const ContextPattern *b2 = dynamic_cast(b);\n if (b2 == (const ContextPattern *)0)\n return b->doAnd(this,-sa);\n\n PatternBlock *resblock = maskvalue->intersect(b2->maskvalue);\n return new ContextPattern(resblock);\n}\n\nPattern *ContextPattern::commonSubPattern(const Pattern *b,int4 sa) const\n\n{\n const ContextPattern *b2 = dynamic_cast(b);\n if (b2 == (const ContextPattern *)0)\n return b->commonSubPattern(this,-sa);\n\n PatternBlock *resblock = maskvalue->commonSubPattern(b2->maskvalue);\n return new ContextPattern(resblock);\n}\n\nvoid ContextPattern::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_CONTEXT_PAT);\n maskvalue->encode(encoder);\n encoder.closeElement(sla::ELEM_CONTEXT_PAT);\n}\n\nvoid ContextPattern::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_CONTEXT_PAT);\n maskvalue = new PatternBlock(true);\n maskvalue->decode(decoder);\n decoder.closeElement(el);\n}\n\nCombinePattern::~CombinePattern(void)\n\n{\n if (context != (ContextPattern *)0)\n delete context;\n if (instr != (InstructionPattern *)0)\n delete instr;\n}\n\nbool CombinePattern::isMatch(ParserWalker &walker) const\n\n{\n if (!instr->isMatch(walker)) return false;\n if (!context->isMatch(walker)) return false;\n return true;\n}\n\nbool CombinePattern::alwaysTrue(void) const\n\n{\n return (context->alwaysTrue() && instr->alwaysTrue());\n}\n\nbool CombinePattern::alwaysFalse(void) const\n\n{\n return (context->alwaysFalse() || instr->alwaysFalse());\n}\n\nPattern *CombinePattern::doAnd(const Pattern *b,int4 sa) const\n\n{\n CombinePattern *tmp;\n \n if (b->numDisjoint() != 0)\n return b->doAnd(this,-sa);\n\n const CombinePattern *b2 = dynamic_cast(b);\n if (b2 != (CombinePattern *)0) {\n ContextPattern *c = (ContextPattern *)context->doAnd(b2->context,0);\n InstructionPattern *i = (InstructionPattern *)instr->doAnd(b2->instr,sa);\n tmp = new CombinePattern(c,i);\n }\n else {\n const InstructionPattern *b3 = dynamic_cast(b);\n if (b3 != (const InstructionPattern *)0) {\n InstructionPattern *i = (InstructionPattern *)instr->doAnd(b3,sa);\n tmp = new CombinePattern((ContextPattern *)context->simplifyClone(),i);\n }\n else {\t\t\t// Must be a ContextPattern\n ContextPattern *c = (ContextPattern *)context->doAnd(b,0);\n InstructionPattern *newpat = (InstructionPattern *) instr->simplifyClone();\n if (sa < 0)\n\tnewpat->shiftInstruction(-sa);\n tmp = new CombinePattern(c,newpat);\n }\n }\n return tmp;\n}\n\nPattern *CombinePattern::commonSubPattern(const Pattern *b,int4 sa) const\n\n{\n Pattern *tmp;\n\n if (b->numDisjoint() != 0)\n return b->commonSubPattern(this,-sa);\n\n const CombinePattern *b2 = dynamic_cast(b);\n if (b2 != (CombinePattern *)0) {\n ContextPattern *c = (ContextPattern *)context->commonSubPattern(b2->context,0);\n InstructionPattern *i = (InstructionPattern *)instr->commonSubPattern(b2->instr,sa);\n tmp = new CombinePattern(c,i);\n }\n else {\n const InstructionPattern *b3 = dynamic_cast(b);\n if (b3 != (const InstructionPattern *)0)\n tmp = instr->commonSubPattern(b3,sa);\n else\t\t\t// Must be a ContextPattern\n tmp = context->commonSubPattern(b,0);\n }\n return tmp;\n}\n\nPattern *CombinePattern::doOr(const Pattern *b,int4 sa) const\n\n{\n if (b->numDisjoint() != 0)\n return b->doOr(this,-sa);\n\n DisjointPattern *res1 = (DisjointPattern *)simplifyClone();\n DisjointPattern *res2 = (DisjointPattern *)b->simplifyClone();\n if (sa < 0)\n res1->shiftInstruction(-sa);\n else\n res2->shiftInstruction(sa);\n OrPattern *tmp = new OrPattern(res1,res2);\n return tmp;\n}\n\nPattern *CombinePattern::simplifyClone(void) const\n\n{\t\t\t\t// We should only have to think at \"our\" level\n if (context->alwaysTrue())\n return instr->simplifyClone();\n if (instr->alwaysTrue())\n return context->simplifyClone();\n if (context->alwaysFalse()||instr->alwaysFalse())\n return new InstructionPattern(false);\n return new CombinePattern((ContextPattern *)context->simplifyClone(),\n\t\t\t (InstructionPattern *)instr->simplifyClone());\n}\n\nvoid CombinePattern::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_COMBINE_PAT);\n context->encode(encoder);\n instr->encode(encoder);\n encoder.closeElement(sla::ELEM_COMBINE_PAT);\n}\n\nvoid CombinePattern::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_COMBINE_PAT);\n context = new ContextPattern();\n context->decode(decoder);\n instr = new InstructionPattern();\n instr->decode(decoder);\n decoder.closeElement(el);\n}\n\nOrPattern::OrPattern(DisjointPattern *a,DisjointPattern *b)\n\n{\n orlist.push_back(a);\n orlist.push_back(b);\n}\n\nOrPattern::OrPattern(const vector &list)\n\n{\n vector::const_iterator iter;\n\n for(iter=list.begin();iter!=list.end();++iter)\n orlist.push_back(*iter);\n}\n\nOrPattern::~OrPattern(void)\n\n{\n vector::iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n delete *iter;\n}\n\nvoid OrPattern::shiftInstruction(int4 sa)\n\n{\n vector::iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n (*iter)->shiftInstruction(sa);\n}\n\nbool OrPattern::isMatch(ParserWalker &walker) const\n\n{\n for(int4 i=0;iisMatch(walker))\n return true;\n return false;\n}\n\nbool OrPattern::alwaysTrue(void) const\n\n{\t\t\t\t// This isn't quite right because different branches\n\t\t\t\t// may cover the entire gamut\n vector::const_iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n if ((*iter)->alwaysTrue()) return true;\n return false;\n}\n\nbool OrPattern::alwaysFalse(void) const\n\n{\n vector::const_iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n if (!(*iter)->alwaysFalse()) return false;\n return true;\n}\n\nbool OrPattern::alwaysInstructionTrue(void) const\n\n{\n vector::const_iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n if (!(*iter)->alwaysInstructionTrue()) return false;\n return true;\n}\n\nPattern *OrPattern::doAnd(const Pattern *b,int4 sa) const\n\n{\n const OrPattern *b2 = dynamic_cast(b);\n vector newlist;\n vector::const_iterator iter,iter2;\n DisjointPattern *tmp;\n OrPattern *tmpor;\n\n if (b2 == (const OrPattern *)0) {\n for(iter=orlist.begin();iter!=orlist.end();++iter) {\n tmp = (DisjointPattern *)(*iter)->doAnd(b,sa);\n newlist.push_back(tmp);\n }\n }\n else {\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n for(iter2=b2->orlist.begin();iter2!=b2->orlist.end();++iter2) {\n\ttmp = (DisjointPattern *)(*iter)->doAnd(*iter2,sa);\n\tnewlist.push_back(tmp);\n }\n }\n tmpor = new OrPattern(newlist);\n return tmpor;\n}\n\nPattern *OrPattern::commonSubPattern(const Pattern *b,int4 sa) const\n\n{\n vector::const_iterator iter;\n Pattern *res,*next;\n\n iter = orlist.begin();\n res = (*iter)->commonSubPattern(b,sa);\n iter++;\n\n if (sa > 0)\n sa = 0;\n while(iter!=orlist.end()) {\n next = (*iter)->commonSubPattern(res,sa);\n delete res;\n res = next;\n ++iter;\n }\n return res;\n}\n\nPattern *OrPattern::doOr(const Pattern *b,int4 sa) const\n\n{\n const OrPattern *b2 = dynamic_cast(b);\n vector newlist;\n vector::const_iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n newlist.push_back((DisjointPattern *)(*iter)->simplifyClone());\n if (sa < 0)\n for(iter=orlist.begin();iter!=orlist.end();++iter)\n (*iter)->shiftInstruction(-sa);\n\n if (b2 == (const OrPattern *)0)\n newlist.push_back((DisjointPattern *)b->simplifyClone());\n else {\n for(iter=b2->orlist.begin();iter!=b2->orlist.end();++iter)\n newlist.push_back((DisjointPattern *)(*iter)->simplifyClone());\n }\n if (sa > 0)\n for(int4 i=0;ishiftInstruction(sa);\n\n OrPattern *tmpor = new OrPattern(newlist);\n return tmpor;\n}\n\nPattern *OrPattern::simplifyClone(void) const\n\n{\t\t\t\t// Look for alwaysTrue eliminate alwaysFalse\n vector::const_iterator iter;\n\n for(iter=orlist.begin();iter!=orlist.end();++iter) // Look for alwaysTrue\n if ((*iter)->alwaysTrue())\n return new InstructionPattern(true);\n\n vector newlist;\n for(iter=orlist.begin();iter!=orlist.end();++iter) // Look for alwaysFalse\n if (!(*iter)->alwaysFalse())\n newlist.push_back((DisjointPattern *)(*iter)->simplifyClone());\n \n if (newlist.empty())\n return new InstructionPattern(false);\n else if (newlist.size() == 1)\n return newlist[0];\n return new OrPattern(newlist);\n}\n\nvoid OrPattern::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_OR_PAT);\n for(int4 i=0;iencode(encoder);\n encoder.closeElement(sla::ELEM_OR_PAT);\n}\n\nvoid OrPattern::decode(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_OR_PAT);\n while(decoder.peekElement() != 0) {\n DisjointPattern *pat = DisjointPattern::decodeDisjoint(decoder);\n orlist.push_back(pat);\n }\n decoder.closeElement(el);\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/slghpattern.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __SLGHPATTERN_HH__\n#define __SLGHPATTERN_HH__\n\n#include \"context.hh\"\n\nnamespace ghidra {\n\n// A mask/value pair viewed as two bitstreams\nclass PatternBlock {\n int4 offset;\t\t\t// Offset to non-zero byte of mask\n int4 nonzerosize;\t\t// Last byte(+1) containing nonzero mask\n vector maskvec;\t// Mask\n vector valvec;\t\t// Value\n void normalize(void);\npublic:\n PatternBlock(int4 off,uintm msk,uintm val);\n PatternBlock(bool tf);\n PatternBlock(const PatternBlock *a,const PatternBlock *b);\n PatternBlock(vector &list);\n PatternBlock *commonSubPattern(const PatternBlock *b) const;\n PatternBlock *intersect(const PatternBlock *b) const;\n bool specializes(const PatternBlock *op2) const;\n bool identical(const PatternBlock *op2) const;\n PatternBlock *clone(void) const;\n void shift(int4 sa) { offset += sa; normalize(); }\n int4 getLength(void) const { return offset+nonzerosize; }\n uintm getMask(int4 startbit,int4 size) const;\n uintm getValue(int4 startbit,int4 size) const;\n bool alwaysTrue(void) const { return (nonzerosize==0); }\n bool alwaysFalse(void) const { return (nonzerosize==-1); }\n bool isInstructionMatch(ParserWalker &walker) const;\n bool isContextMatch(ParserWalker &walker) const;\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder);\n};\n\nclass DisjointPattern;\nclass Pattern {\npublic:\n virtual ~Pattern(void) {}\n virtual Pattern *simplifyClone(void) const=0;\n virtual void shiftInstruction(int4 sa)=0;\n virtual Pattern *doOr(const Pattern *b,int4 sa) const=0;\n virtual Pattern *doAnd(const Pattern *b,int4 sa) const=0;\n virtual Pattern *commonSubPattern(const Pattern *b,int4 sa) const=0;\n virtual bool isMatch(ParserWalker &walker) const=0; // Does this pattern match context\n virtual int4 numDisjoint(void) const=0;\n virtual DisjointPattern *getDisjoint(int4 i) const=0;\n virtual bool alwaysTrue(void) const=0;\n virtual bool alwaysFalse(void) const=0;\n virtual bool alwaysInstructionTrue(void) const=0;\n virtual void encode(Encoder &encoder) const=0;\n virtual void decode(Decoder &decoder)=0;\n};\n\nclass DisjointPattern : public Pattern { // A pattern with no ORs in it\n virtual PatternBlock *getBlock(bool context) const=0;\npublic:\n virtual int4 numDisjoint(void) const { return 0; }\n virtual DisjointPattern *getDisjoint(int4 i) const { return (DisjointPattern *)0; }\n uintm getMask(int4 startbit,int4 size,bool context) const;\n uintm getValue(int4 startbit,int4 size,bool context) const;\n int4 getLength(bool context) const;\n bool specializes(const DisjointPattern *op2) const;\n bool identical(const DisjointPattern *op2) const;\n bool resolvesIntersect(const DisjointPattern *op1,const DisjointPattern *op2) const;\n static DisjointPattern *decodeDisjoint(Decoder &decoder);\n};\n\nclass InstructionPattern : public DisjointPattern { // Matches the instruction bitstream\n PatternBlock *maskvalue;\n virtual PatternBlock *getBlock(bool context) const { return context ? (PatternBlock *)0 : maskvalue; }\npublic:\n InstructionPattern(void) { maskvalue = (PatternBlock *)0; } // For use with decode\n InstructionPattern(PatternBlock *mv) { maskvalue = mv; }\n InstructionPattern(bool tf) { maskvalue = new PatternBlock(tf); }\n PatternBlock *getBlock(void) { return maskvalue; }\n virtual ~InstructionPattern(void) { if (maskvalue != (PatternBlock *)0) delete maskvalue; }\n virtual Pattern *simplifyClone(void) const { return new InstructionPattern(maskvalue->clone()); }\n virtual void shiftInstruction(int4 sa) { maskvalue->shift(sa); }\n virtual Pattern *doOr(const Pattern *b,int4 sa) const;\n virtual Pattern *doAnd(const Pattern *b,int4 sa) const;\n virtual Pattern *commonSubPattern(const Pattern *b,int4 sa) const;\n virtual bool isMatch(ParserWalker &walker) const { return maskvalue->isInstructionMatch(walker); }\n virtual bool alwaysTrue(void) const { return maskvalue->alwaysTrue(); }\n virtual bool alwaysFalse(void) const { return maskvalue->alwaysFalse(); }\n virtual bool alwaysInstructionTrue(void) const { return maskvalue->alwaysTrue(); }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder);\n};\n\nclass ContextPattern : public DisjointPattern { // Matches the context bitstream\n PatternBlock *maskvalue;\n virtual PatternBlock *getBlock(bool context) const { return context ? maskvalue : (PatternBlock *)0; }\npublic:\n ContextPattern(void) { maskvalue = (PatternBlock *)0; } // For use with decode\n ContextPattern(PatternBlock *mv) { maskvalue = mv; }\n PatternBlock *getBlock(void) { return maskvalue; }\n virtual ~ContextPattern(void) { if (maskvalue != (PatternBlock *)0) delete maskvalue; }\n virtual Pattern *simplifyClone(void) const { return new ContextPattern(maskvalue->clone()); }\n virtual void shiftInstruction(int4 sa) { } // do nothing\n virtual Pattern *doOr(const Pattern *b,int4 sa) const;\n virtual Pattern *doAnd(const Pattern *b,int4 sa) const;\n virtual Pattern *commonSubPattern(const Pattern *b,int4 sa) const;\n virtual bool isMatch(ParserWalker &walker) const { return maskvalue->isContextMatch(walker); }\n virtual bool alwaysTrue(void) const { return maskvalue->alwaysTrue(); }\n virtual bool alwaysFalse(void) const { return maskvalue->alwaysFalse(); }\n virtual bool alwaysInstructionTrue(void) const { return true; }\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder);\n};\n\n// A pattern with a context piece and an instruction piece\nclass CombinePattern : public DisjointPattern {\n ContextPattern *context;\t// Context piece\n InstructionPattern *instr;\t// Instruction piece\n virtual PatternBlock *getBlock(bool cont) const { return cont ? context->getBlock() : instr->getBlock(); }\npublic:\n CombinePattern(void) { context = (ContextPattern *)0; instr = (InstructionPattern *)0; }\n CombinePattern(ContextPattern *con,InstructionPattern *in) {\n context = con; instr = in; }\n virtual ~CombinePattern(void);\n virtual Pattern *simplifyClone(void) const;\n virtual void shiftInstruction(int4 sa) { instr->shiftInstruction(sa); }\n virtual bool isMatch(ParserWalker &walker) const;\n virtual bool alwaysTrue(void) const;\n virtual bool alwaysFalse(void) const;\n virtual bool alwaysInstructionTrue(void) const { return instr->alwaysInstructionTrue(); }\n virtual Pattern *doOr(const Pattern *b,int4 sa) const;\n virtual Pattern *doAnd(const Pattern *b,int4 sa) const;\n virtual Pattern *commonSubPattern(const Pattern *b,int4 sa) const;\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder);\n};\n\nclass OrPattern : public Pattern {\n vector orlist;\npublic:\n OrPattern(void) {}\t\t// For use with decode\n OrPattern(DisjointPattern *a,DisjointPattern *b);\n OrPattern(const vector &list);\n virtual ~OrPattern(void);\n virtual Pattern *simplifyClone(void) const;\n virtual void shiftInstruction(int4 sa);\n virtual bool isMatch(ParserWalker &walker) const;\n virtual int4 numDisjoint(void) const { return orlist.size(); }\n virtual DisjointPattern *getDisjoint(int4 i) const { return orlist[i]; }\n virtual bool alwaysTrue(void) const;\n virtual bool alwaysFalse(void) const;\n virtual bool alwaysInstructionTrue(void) const;\n virtual Pattern *doOr(const Pattern *b,int4 sa) const;\n virtual Pattern *doAnd(const Pattern *b,int4 sa) const;\n virtual Pattern *commonSubPattern(const Pattern *b,int4 sa) const;\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder);\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/slghscan.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#define YY_INT_ALIGNED short int\n\n/* A lexical scanner generated by flex */\n\n#define yy_create_buffer sleigh_create_buffer\n#define yy_delete_buffer sleigh_delete_buffer\n#define yy_scan_buffer sleigh_scan_buffer\n#define yy_scan_string sleigh_scan_string\n#define yy_scan_bytes sleigh_scan_bytes\n#define yy_init_buffer sleigh_init_buffer\n#define yy_flush_buffer sleigh_flush_buffer\n#define yy_load_buffer_state sleigh_load_buffer_state\n#define yy_switch_to_buffer sleigh_switch_to_buffer\n#define yypush_buffer_state sleighpush_buffer_state\n#define yypop_buffer_state sleighpop_buffer_state\n#define yyensure_buffer_stack sleighensure_buffer_stack\n#define yy_flex_debug sleigh_flex_debug\n#define yyin sleighin\n#define yyleng sleighleng\n#define yylex sleighlex\n#define yylineno sleighlineno\n#define yyout sleighout\n#define yyrestart sleighrestart\n#define yytext sleightext\n#define yywrap sleighwrap\n#define yyalloc sleighalloc\n#define yyrealloc sleighrealloc\n#define yyfree sleighfree\n\n#define FLEX_SCANNER\n#define YY_FLEX_MAJOR_VERSION 2\n#define YY_FLEX_MINOR_VERSION 6\n#define YY_FLEX_SUBMINOR_VERSION 4\n#if YY_FLEX_SUBMINOR_VERSION > 0\n#define FLEX_BETA\n#endif\n\n#ifdef yy_create_buffer\n#define sleigh_create_buffer_ALREADY_DEFINED\n#else\n#define yy_create_buffer sleigh_create_buffer\n#endif\n\n#ifdef yy_delete_buffer\n#define sleigh_delete_buffer_ALREADY_DEFINED\n#else\n#define yy_delete_buffer sleigh_delete_buffer\n#endif\n\n#ifdef yy_scan_buffer\n#define sleigh_scan_buffer_ALREADY_DEFINED\n#else\n#define yy_scan_buffer sleigh_scan_buffer\n#endif\n\n#ifdef yy_scan_string\n#define sleigh_scan_string_ALREADY_DEFINED\n#else\n#define yy_scan_string sleigh_scan_string\n#endif\n\n#ifdef yy_scan_bytes\n#define sleigh_scan_bytes_ALREADY_DEFINED\n#else\n#define yy_scan_bytes sleigh_scan_bytes\n#endif\n\n#ifdef yy_init_buffer\n#define sleigh_init_buffer_ALREADY_DEFINED\n#else\n#define yy_init_buffer sleigh_init_buffer\n#endif\n\n#ifdef yy_flush_buffer\n#define sleigh_flush_buffer_ALREADY_DEFINED\n#else\n#define yy_flush_buffer sleigh_flush_buffer\n#endif\n\n#ifdef yy_load_buffer_state\n#define sleigh_load_buffer_state_ALREADY_DEFINED\n#else\n#define yy_load_buffer_state sleigh_load_buffer_state\n#endif\n\n#ifdef yy_switch_to_buffer\n#define sleigh_switch_to_buffer_ALREADY_DEFINED\n#else\n#define yy_switch_to_buffer sleigh_switch_to_buffer\n#endif\n\n#ifdef yypush_buffer_state\n#define sleighpush_buffer_state_ALREADY_DEFINED\n#else\n#define yypush_buffer_state sleighpush_buffer_state\n#endif\n\n#ifdef yypop_buffer_state\n#define sleighpop_buffer_state_ALREADY_DEFINED\n#else\n#define yypop_buffer_state sleighpop_buffer_state\n#endif\n\n#ifdef yyensure_buffer_stack\n#define sleighensure_buffer_stack_ALREADY_DEFINED\n#else\n#define yyensure_buffer_stack sleighensure_buffer_stack\n#endif\n\n#ifdef yylex\n#define sleighlex_ALREADY_DEFINED\n#else\n#define yylex sleighlex\n#endif\n\n#ifdef yyrestart\n#define sleighrestart_ALREADY_DEFINED\n#else\n#define yyrestart sleighrestart\n#endif\n\n#ifdef yylex_init\n#define sleighlex_init_ALREADY_DEFINED\n#else\n#define yylex_init sleighlex_init\n#endif\n\n#ifdef yylex_init_extra\n#define sleighlex_init_extra_ALREADY_DEFINED\n#else\n#define yylex_init_extra sleighlex_init_extra\n#endif\n\n#ifdef yylex_destroy\n#define sleighlex_destroy_ALREADY_DEFINED\n#else\n#define yylex_destroy sleighlex_destroy\n#endif\n\n#ifdef yyget_debug\n#define sleighget_debug_ALREADY_DEFINED\n#else\n#define yyget_debug sleighget_debug\n#endif\n\n#ifdef yyset_debug\n#define sleighset_debug_ALREADY_DEFINED\n#else\n#define yyset_debug sleighset_debug\n#endif\n\n#ifdef yyget_extra\n#define sleighget_extra_ALREADY_DEFINED\n#else\n#define yyget_extra sleighget_extra\n#endif\n\n#ifdef yyset_extra\n#define sleighset_extra_ALREADY_DEFINED\n#else\n#define yyset_extra sleighset_extra\n#endif\n\n#ifdef yyget_in\n#define sleighget_in_ALREADY_DEFINED\n#else\n#define yyget_in sleighget_in\n#endif\n\n#ifdef yyset_in\n#define sleighset_in_ALREADY_DEFINED\n#else\n#define yyset_in sleighset_in\n#endif\n\n#ifdef yyget_out\n#define sleighget_out_ALREADY_DEFINED\n#else\n#define yyget_out sleighget_out\n#endif\n\n#ifdef yyset_out\n#define sleighset_out_ALREADY_DEFINED\n#else\n#define yyset_out sleighset_out\n#endif\n\n#ifdef yyget_leng\n#define sleighget_leng_ALREADY_DEFINED\n#else\n#define yyget_leng sleighget_leng\n#endif\n\n#ifdef yyget_text\n#define sleighget_text_ALREADY_DEFINED\n#else\n#define yyget_text sleighget_text\n#endif\n\n#ifdef yyget_lineno\n#define sleighget_lineno_ALREADY_DEFINED\n#else\n#define yyget_lineno sleighget_lineno\n#endif\n\n#ifdef yyset_lineno\n#define sleighset_lineno_ALREADY_DEFINED\n#else\n#define yyset_lineno sleighset_lineno\n#endif\n\n#ifdef yywrap\n#define sleighwrap_ALREADY_DEFINED\n#else\n#define yywrap sleighwrap\n#endif\n\n#ifdef yyalloc\n#define sleighalloc_ALREADY_DEFINED\n#else\n#define yyalloc sleighalloc\n#endif\n\n#ifdef yyrealloc\n#define sleighrealloc_ALREADY_DEFINED\n#else\n#define yyrealloc sleighrealloc\n#endif\n\n#ifdef yyfree\n#define sleighfree_ALREADY_DEFINED\n#else\n#define yyfree sleighfree\n#endif\n\n#ifdef yytext\n#define sleightext_ALREADY_DEFINED\n#else\n#define yytext sleightext\n#endif\n\n#ifdef yyleng\n#define sleighleng_ALREADY_DEFINED\n#else\n#define yyleng sleighleng\n#endif\n\n#ifdef yyin\n#define sleighin_ALREADY_DEFINED\n#else\n#define yyin sleighin\n#endif\n\n#ifdef yyout\n#define sleighout_ALREADY_DEFINED\n#else\n#define yyout sleighout\n#endif\n\n#ifdef yy_flex_debug\n#define sleigh_flex_debug_ALREADY_DEFINED\n#else\n#define yy_flex_debug sleigh_flex_debug\n#endif\n\n#ifdef yylineno\n#define sleighlineno_ALREADY_DEFINED\n#else\n#define yylineno sleighlineno\n#endif\n\n/* First, we deal with platform-specific or compiler-specific issues. */\n\n/* begin standard C headers. */\n#include \n#include \n#include \n#include \n\n/* end standard C headers. */\n\n/* flex integer type definitions */\n\n#ifndef FLEXINT_H\n#define FLEXINT_H\n\n/* C99 systems have . Non-C99 systems may or may not. */\n\n#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L\n\n/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,\n * if you want the limit (max/min) macros for int types. \n */\n#ifndef __STDC_LIMIT_MACROS\n#define __STDC_LIMIT_MACROS 1\n#endif\n\n#include \ntypedef int8_t flex_int8_t;\ntypedef uint8_t flex_uint8_t;\ntypedef int16_t flex_int16_t;\ntypedef uint16_t flex_uint16_t;\ntypedef int32_t flex_int32_t;\ntypedef uint32_t flex_uint32_t;\n#else\ntypedef signed char flex_int8_t;\ntypedef short int flex_int16_t;\ntypedef int flex_int32_t;\ntypedef unsigned char flex_uint8_t; \ntypedef unsigned short int flex_uint16_t;\ntypedef unsigned int flex_uint32_t;\n\n/* Limits of integral types. */\n#ifndef INT8_MIN\n#define INT8_MIN (-128)\n#endif\n#ifndef INT16_MIN\n#define INT16_MIN (-32767-1)\n#endif\n#ifndef INT32_MIN\n#define INT32_MIN (-2147483647-1)\n#endif\n#ifndef INT8_MAX\n#define INT8_MAX (127)\n#endif\n#ifndef INT16_MAX\n#define INT16_MAX (32767)\n#endif\n#ifndef INT32_MAX\n#define INT32_MAX (2147483647)\n#endif\n#ifndef UINT8_MAX\n#define UINT8_MAX (255U)\n#endif\n#ifndef UINT16_MAX\n#define UINT16_MAX (65535U)\n#endif\n#ifndef UINT32_MAX\n#define UINT32_MAX (4294967295U)\n#endif\n\n#ifndef SIZE_MAX\n#define SIZE_MAX (~(size_t)0)\n#endif\n\n#endif /* ! C99 */\n\n#endif /* ! FLEXINT_H */\n\n/* begin standard C++ headers. */\n\n/* TODO: this is always defined, so inline it */\n#define yyconst const\n\n#if defined(__GNUC__) && __GNUC__ >= 3\n#define yynoreturn __attribute__((__noreturn__))\n#else\n#define yynoreturn\n#endif\n\n/* Returned upon end-of-file. */\n#define YY_NULL 0\n\n/* Promotes a possibly negative, possibly signed char to an\n * integer in range [0..255] for use as an array index.\n */\n#define YY_SC_TO_UI(c) ((YY_CHAR) (c))\n\n/* Enter a start condition. This macro really ought to take a parameter,\n * but we do it the disgusting crufty way forced on us by the ()-less\n * definition of BEGIN.\n */\n#define BEGIN (yy_start) = 1 + 2 *\n/* Translate the current start state into a value that can be later handed\n * to BEGIN to return to the state. The YYSTATE alias is for lex\n * compatibility.\n */\n#define YY_START (((yy_start) - 1) / 2)\n#define YYSTATE YY_START\n/* Action number for EOF rule of a given start state. */\n#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)\n/* Special action meaning \"start processing a new file\". */\n#define YY_NEW_FILE yyrestart( yyin )\n#define YY_END_OF_BUFFER_CHAR 0\n\n/* Size of default input buffer. */\n#ifndef YY_BUF_SIZE\n#ifdef __ia64__\n/* On IA-64, the buffer size is 16k, not 8k.\n * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case.\n * Ditto for the __ia64__ case accordingly.\n */\n#define YY_BUF_SIZE 32768\n#else\n#define YY_BUF_SIZE 16384\n#endif /* __ia64__ */\n#endif\n\n/* The state buf must be large enough to hold one state per character in the main buffer.\n */\n#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))\n\n#ifndef YY_TYPEDEF_YY_BUFFER_STATE\n#define YY_TYPEDEF_YY_BUFFER_STATE\ntypedef struct yy_buffer_state *YY_BUFFER_STATE;\n#endif\n\n#ifndef YY_TYPEDEF_YY_SIZE_T\n#define YY_TYPEDEF_YY_SIZE_T\ntypedef size_t yy_size_t;\n#endif\n\nextern int yyleng;\n\nextern FILE *yyin, *yyout;\n\n#define EOB_ACT_CONTINUE_SCAN 0\n#define EOB_ACT_END_OF_FILE 1\n#define EOB_ACT_LAST_MATCH 2\n \n #define YY_LESS_LINENO(n)\n #define YY_LINENO_REWIND_TO(ptr)\n \n/* Return all but the first \"n\" matched characters back to the input stream. */\n#define yyless(n) \\\n\tdo \\\n\t\t{ \\\n\t\t/* Undo effects of setting up yytext. */ \\\n int yyless_macro_arg = (n); \\\n YY_LESS_LINENO(yyless_macro_arg);\\\n\t\t*yy_cp = (yy_hold_char); \\\n\t\tYY_RESTORE_YY_MORE_OFFSET \\\n\t\t(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \\\n\t\tYY_DO_BEFORE_ACTION; /* set up yytext again */ \\\n\t\t} \\\n\twhile ( 0 )\n#define unput(c) yyunput( c, (yytext_ptr) )\n\n#ifndef YY_STRUCT_YY_BUFFER_STATE\n#define YY_STRUCT_YY_BUFFER_STATE\nstruct yy_buffer_state\n\t{\n\tFILE *yy_input_file;\n\n\tchar *yy_ch_buf;\t\t/* input buffer */\n\tchar *yy_buf_pos;\t\t/* current position in input buffer */\n\n\t/* Size of input buffer in bytes, not including room for EOB\n\t * characters.\n\t */\n\tint yy_buf_size;\n\n\t/* Number of characters read into yy_ch_buf, not including EOB\n\t * characters.\n\t */\n\tint yy_n_chars;\n\n\t/* Whether we \"own\" the buffer - i.e., we know we created it,\n\t * and can realloc() it to grow it, and should free() it to\n\t * delete it.\n\t */\n\tint yy_is_our_buffer;\n\n\t/* Whether this is an \"interactive\" input source; if so, and\n\t * if we're using stdio for input, then we want to use getc()\n\t * instead of fread(), to make sure we stop fetching input after\n\t * each newline.\n\t */\n\tint yy_is_interactive;\n\n\t/* Whether we're considered to be at the beginning of a line.\n\t * If so, '^' rules will be active on the next match, otherwise\n\t * not.\n\t */\n\tint yy_at_bol;\n\n int yy_bs_lineno; /**< The line count. */\n int yy_bs_column; /**< The column count. */\n\n\t/* Whether to try to fill the input buffer when we reach the\n\t * end of it.\n\t */\n\tint yy_fill_buffer;\n\n\tint yy_buffer_status;\n\n#define YY_BUFFER_NEW 0\n#define YY_BUFFER_NORMAL 1\n\t/* When an EOF's been seen but there's still some text to process\n\t * then we mark the buffer as YY_EOF_PENDING, to indicate that we\n\t * shouldn't try reading from the input source any more. We might\n\t * still have a bunch of tokens to match, though, because of\n\t * possible backing-up.\n\t *\n\t * When we actually see the EOF, we change the status to \"new\"\n\t * (via yyrestart()), so that the user can continue scanning by\n\t * just pointing yyin at a new input file.\n\t */\n#define YY_BUFFER_EOF_PENDING 2\n\n\t};\n#endif /* !YY_STRUCT_YY_BUFFER_STATE */\n\n/* Stack of input buffers. */\nstatic size_t yy_buffer_stack_top = 0; /**< index of top of stack. */\nstatic size_t yy_buffer_stack_max = 0; /**< capacity of stack. */\nstatic YY_BUFFER_STATE * yy_buffer_stack = NULL; /**< Stack as an array. */\n\n/* We provide macros for accessing buffer states in case in the\n * future we want to put the buffer states in a more general\n * \"scanner state\".\n *\n * Returns the top of the stack, or NULL.\n */\n#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \\\n ? (yy_buffer_stack)[(yy_buffer_stack_top)] \\\n : NULL)\n/* Same as previous macro, but useful when we know that the buffer stack is not\n * NULL or when we need an lvalue. For internal use only.\n */\n#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]\n\n/* yy_hold_char holds the character lost when yytext is formed. */\nstatic char yy_hold_char;\nstatic int yy_n_chars;\t\t/* number of characters read into yy_ch_buf */\nint yyleng;\n\n/* Points to current character in buffer. */\nstatic char *yy_c_buf_p = NULL;\nstatic int yy_init = 0;\t\t/* whether we need to initialize */\nstatic int yy_start = 0;\t/* start state number */\n\n/* Flag which is used to allow yywrap()'s to do buffer switches\n * instead of setting up a fresh yyin. A bit of a hack ...\n */\nstatic int yy_did_buffer_switch_on_eof;\n\nvoid yyrestart ( FILE *input_file );\nvoid yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer );\nYY_BUFFER_STATE yy_create_buffer ( FILE *file, int size );\nvoid yy_delete_buffer ( YY_BUFFER_STATE b );\nvoid yy_flush_buffer ( YY_BUFFER_STATE b );\nvoid yypush_buffer_state ( YY_BUFFER_STATE new_buffer );\nvoid yypop_buffer_state ( void );\n\nstatic void yyensure_buffer_stack ( void );\nstatic void yy_load_buffer_state ( void );\nstatic void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file );\n#define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER )\n\nYY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size );\nYY_BUFFER_STATE yy_scan_string ( const char *yy_str );\nYY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len );\n\nvoid *yyalloc ( yy_size_t );\nvoid *yyrealloc ( void *, yy_size_t );\nvoid yyfree ( void * );\n\n#define yy_new_buffer yy_create_buffer\n#define yy_set_interactive(is_interactive) \\\n\t{ \\\n\tif ( ! YY_CURRENT_BUFFER ){ \\\n yyensure_buffer_stack (); \\\n\t\tYY_CURRENT_BUFFER_LVALUE = \\\n yy_create_buffer( yyin, YY_BUF_SIZE ); \\\n\t} \\\n\tYY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \\\n\t}\n#define yy_set_bol(at_bol) \\\n\t{ \\\n\tif ( ! YY_CURRENT_BUFFER ){\\\n yyensure_buffer_stack (); \\\n\t\tYY_CURRENT_BUFFER_LVALUE = \\\n yy_create_buffer( yyin, YY_BUF_SIZE ); \\\n\t} \\\n\tYY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \\\n\t}\n#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)\n\ntypedef flex_uint8_t YY_CHAR;\n\nFILE *yyin = NULL, *yyout = NULL;\n\ntypedef int yy_state_type;\n\nextern int yylineno;\nint yylineno = 1;\n\nextern char *yytext;\n#ifdef yytext_ptr\n#undef yytext_ptr\n#endif\n#define yytext_ptr yytext\n\nstatic yy_state_type yy_get_previous_state ( void );\nstatic yy_state_type yy_try_NUL_trans ( yy_state_type current_state );\nstatic int yy_get_next_buffer ( void );\nstatic void yynoreturn yy_fatal_error ( const char* msg );\n\n/* Done after the current pattern has been matched and before the\n * corresponding action - sets up yytext.\n */\n#define YY_DO_BEFORE_ACTION \\\n\t(yytext_ptr) = yy_bp; \\\n\tyyleng = (int) (yy_cp - yy_bp); \\\n\t(yy_hold_char) = *yy_cp; \\\n\t*yy_cp = '\\0'; \\\n\t(yy_c_buf_p) = yy_cp;\n#define YY_NUM_RULES 165\n#define YY_END_OF_BUFFER 166\n/* This struct is not used in this scanner,\n but its presence is necessary. */\nstruct yy_trans_info\n\t{\n\tflex_int32_t yy_verify;\n\tflex_int32_t yy_nxt;\n\t};\nstatic const flex_int16_t yy_accept[533] =\n { 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 166, 14, 7, 8, 6, 14,\n 3, 13, 4, 13, 13, 13, 13, 5, 1, 58,\n 56, 57, 58, 50, 58, 25, 51, 52, 52, 26,\n 51, 51, 51, 51, 51, 51, 51, 51, 51, 51,\n 51, 51, 51, 51, 51, 23, 22, 20, 21, 22,\n 17, 19, 18, 15, 68, 66, 67, 61, 68, 61,\n 64, 62, 64, 59, 96, 94, 95, 96, 89, 96,\n 85, 88, 90, 91, 91, 88, 88, 90, 83, 84,\n 87, 90, 90, 71, 86, 69, 162, 160, 161, 154,\n\n 155, 162, 154, 154, 156, 157, 157, 154, 154, 154,\n 154, 156, 156, 156, 156, 156, 156, 156, 156, 156,\n 156, 156, 156, 156, 156, 156, 154, 99, 97, 165,\n 165, 164, 163, 7, 6, 0, 13, 13, 13, 13,\n 13, 1, 1, 56, 0, 55, 50, 0, 51, 0,\n 0, 52, 51, 51, 51, 51, 51, 51, 51, 51,\n 51, 51, 51, 51, 51, 51, 51, 51, 51, 51,\n 51, 23, 23, 20, 0, 19, 15, 15, 66, 0,\n 65, 0, 64, 63, 59, 59, 94, 76, 89, 0,\n 0, 0, 0, 90, 90, 0, 0, 91, 75, 77,\n\n 78, 74, 90, 90, 69, 69, 160, 106, 155, 0,\n 101, 156, 0, 0, 157, 104, 107, 105, 108, 103,\n 102, 156, 156, 156, 156, 156, 156, 156, 156, 156,\n 0, 118, 116, 117, 119, 122, 0, 123, 156, 156,\n 145, 156, 156, 156, 156, 156, 156, 156, 156, 110,\n 109, 112, 113, 156, 156, 156, 156, 156, 156, 100,\n 97, 97, 0, 164, 163, 163, 0, 13, 13, 13,\n 13, 0, 54, 53, 51, 41, 51, 51, 38, 51,\n 51, 37, 51, 51, 51, 51, 51, 51, 51, 51,\n 51, 51, 51, 51, 51, 51, 51, 0, 0, 0,\n\n 0, 80, 0, 82, 93, 92, 90, 90, 0, 159,\n 158, 133, 156, 156, 156, 156, 156, 156, 156, 156,\n 156, 121, 124, 120, 125, 156, 156, 156, 156, 156,\n 132, 156, 156, 156, 156, 114, 115, 111, 156, 156,\n 156, 156, 156, 156, 2, 0, 13, 13, 13, 12,\n 24, 0, 51, 51, 51, 51, 51, 51, 51, 51,\n 51, 51, 51, 51, 51, 43, 51, 51, 28, 51,\n 51, 51, 16, 0, 60, 0, 70, 0, 79, 81,\n 90, 90, 98, 0, 156, 156, 147, 156, 135, 156,\n 156, 156, 156, 156, 156, 146, 156, 156, 156, 156,\n\n 156, 156, 156, 156, 156, 129, 134, 156, 126, 13,\n 13, 9, 51, 51, 51, 51, 51, 51, 46, 51,\n 51, 51, 51, 51, 51, 27, 32, 51, 51, 51,\n 90, 90, 156, 152, 127, 141, 156, 156, 156, 156,\n 136, 156, 153, 156, 156, 156, 156, 137, 156, 156,\n 140, 11, 10, 51, 51, 51, 51, 39, 42, 36,\n 45, 51, 51, 51, 35, 47, 51, 51, 90, 72,\n 128, 156, 156, 151, 156, 156, 156, 156, 156, 148,\n 156, 130, 51, 51, 33, 30, 49, 51, 51, 51,\n 51, 90, 156, 156, 156, 156, 144, 156, 156, 131,\n\n 51, 34, 51, 51, 51, 44, 90, 156, 156, 156,\n 156, 156, 143, 40, 29, 51, 48, 73, 156, 149,\n 156, 138, 142, 51, 150, 156, 51, 139, 51, 51,\n 31, 0\n } ;\n\nstatic const YY_CHAR yy_ec[256] =\n { 0,\n 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,\n 2, 1, 2, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 4, 5, 6, 7, 8, 9, 10, 11, 12,\n 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\n 23, 23, 23, 23, 23, 23, 23, 24, 25, 26,\n 27, 28, 29, 30, 31, 31, 31, 31, 31, 31,\n 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,\n 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,\n 33, 11, 34, 35, 36, 11, 37, 38, 39, 40,\n\n 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\n 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,\n 61, 62, 63, 64, 65, 66, 1, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11\n } ;\n\nstatic const YY_CHAR yy_meta[67] =\n { 0,\n 1, 1, 2, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 4, 3, 3, 3, 3, 5, 3, 6,\n 6, 6, 6, 3, 3, 3, 3, 3, 3, 3,\n 6, 5, 3, 3, 3, 5, 6, 6, 6, 6,\n 6, 6, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 3, 3, 3, 3\n } ;\n\nstatic const flex_int16_t yy_base[570] =\n { 0,\n 0, 937, 66, 936, 132, 935, 198, 934, 264, 933,\n 330, 932, 0, 394, 961, 968, 396, 968, 0, 948,\n 968, 0, 968, 903, 917, 920, 911, 968, 952, 968,\n 397, 968, 948, 0, 941, 968, 0, 365, 384, 968,\n 904, 906, 899, 908, 898, 906, 901, 365, 903, 905,\n 371, 365, 358, 906, 891, 938, 968, 409, 968, 928,\n 968, 0, 968, 936, 968, 416, 968, 968, 932, 925,\n 0, 968, 881, 932, 968, 419, 968, 907, 0, 402,\n 968, 968, 915, 377, 406, 404, 405, 0, 968, 968,\n 968, 884, 881, 968, 968, 927, 968, 432, 968, 902,\n\n 0, 916, 968, 917, 0, 384, 420, 419, 899, 420,\n 890, 886, 398, 413, 882, 862, 454, 870, 410, 410,\n 429, 869, 423, 466, 865, 877, 853, 968, 913, 968,\n 912, 968, 911, 454, 0, 0, 0, 857, 870, 872,\n 854, 906, 968, 474, 902, 901, 0, 0, 0, 463,\n 0, 466, 861, 395, 855, 451, 864, 843, 846, 852,\n 858, 857, 847, 848, 853, 434, 858, 847, 841, 409,\n 838, 888, 968, 493, 0, 0, 887, 968, 496, 883,\n 882, 0, 0, 0, 884, 968, 497, 968, 0, 0,\n 836, 831, 833, 865, 0, 488, 0, 490, 968, 968,\n\n 968, 968, 831, 836, 877, 968, 512, 968, 0, 0,\n 968, 0, 497, 0, 500, 968, 968, 968, 968, 968,\n 968, 824, 824, 832, 476, 831, 824, 823, 825, 820,\n 844, 968, 968, 968, 968, 843, 842, 841, 816, 810,\n 0, 809, 825, 824, 812, 802, 808, 803, 801, 968,\n 968, 830, 498, 805, 818, 794, 799, 795, 791, 968,\n 847, 968, 846, 968, 845, 968, 834, 809, 800, 790,\n 799, 829, 507, 0, 798, 0, 786, 783, 0, 801,\n 792, 0, 780, 794, 786, 778, 792, 795, 785, 779,\n 787, 788, 785, 784, 767, 778, 782, 808, 807, 806,\n\n 778, 968, 763, 0, 511, 0, 778, 766, 801, 513,\n 0, 0, 759, 764, 763, 756, 761, 757, 752, 769,\n 754, 968, 968, 968, 968, 478, 753, 781, 765, 750,\n 0, 749, 760, 741, 747, 968, 968, 968, 742, 741,\n 738, 737, 742, 735, 968, 777, 750, 738, 736, 0,\n 968, 773, 735, 747, 742, 725, 744, 732, 724, 727,\n 736, 735, 720, 719, 732, 0, 731, 721, 0, 729,\n 732, 713, 968, 754, 968, 753, 968, 752, 968, 968,\n 727, 711, 968, 749, 710, 720, 0, 698, 0, 710,\n 702, 695, 701, 698, 699, 0, 710, 703, 693, 711,\n\n 697, 693, 706, 691, 690, 0, 0, 704, 0, 698,\n 700, 0, 691, 689, 678, 689, 686, 694, 0, 675,\n 677, 681, 679, 674, 689, 0, 0, 673, 689, 681,\n 677, 676, 664, 0, 0, 0, 684, 666, 664, 697,\n 0, 670, 0, 667, 670, 658, 664, 0, 662, 651,\n 0, 0, 0, 670, 667, 653, 652, 0, 0, 0,\n 0, 655, 669, 664, 0, 0, 656, 641, 647, 0,\n 0, 644, 652, 0, 657, 647, 641, 655, 645, 0,\n 635, 0, 643, 651, 0, 0, 0, 652, 636, 648,\n 647, 646, 641, 634, 636, 646, 0, 643, 625, 0,\n\n 624, 0, 638, 642, 622, 0, 620, 627, 618, 622,\n 616, 615, 0, 0, 0, 615, 0, 0, 629, 0,\n 577, 0, 0, 548, 0, 510, 511, 0, 467, 462,\n 0, 968, 534, 540, 546, 548, 554, 558, 564, 566,\n 572, 574, 580, 584, 586, 592, 598, 600, 606, 612,\n 614, 620, 626, 632, 634, 636, 485, 638, 640, 642,\n 473, 644, 429, 647, 650, 653, 656, 659, 662\n } ;\n\nstatic const flex_int16_t yy_def[570] =\n { 0,\n 532, 1, 532, 3, 532, 5, 532, 7, 532, 9,\n 532, 11, 533, 534, 532, 532, 532, 532, 535, 532,\n 532, 536, 532, 536, 536, 536, 536, 532, 537, 532,\n 532, 532, 538, 539, 532, 532, 540, 532, 532, 532,\n 540, 540, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 541, 532, 532, 532, 532,\n 532, 542, 532, 543, 532, 532, 532, 532, 544, 532,\n 545, 532, 545, 546, 532, 532, 532, 532, 547, 532,\n 532, 532, 548, 532, 532, 532, 532, 548, 532, 532,\n 532, 548, 548, 532, 532, 549, 532, 532, 532, 532,\n\n 550, 532, 532, 532, 551, 532, 532, 532, 532, 532,\n 532, 551, 551, 551, 551, 551, 551, 551, 551, 551,\n 551, 551, 551, 551, 551, 551, 532, 532, 552, 532,\n 553, 532, 554, 532, 535, 555, 536, 536, 536, 536,\n 536, 537, 532, 532, 538, 532, 539, 556, 540, 532,\n 557, 532, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 541, 532, 532, 558, 542, 543, 532, 532, 544,\n 532, 559, 545, 545, 546, 532, 532, 532, 547, 560,\n 532, 532, 532, 548, 548, 532, 561, 532, 532, 532,\n\n 532, 532, 548, 548, 549, 532, 532, 532, 550, 562,\n 532, 551, 532, 563, 532, 532, 532, 532, 532, 532,\n 532, 551, 551, 551, 551, 551, 551, 551, 551, 551,\n 532, 532, 532, 532, 532, 532, 532, 532, 551, 551,\n 551, 551, 551, 551, 551, 551, 551, 551, 551, 532,\n 532, 532, 532, 551, 551, 551, 551, 551, 551, 532,\n 552, 532, 553, 532, 554, 532, 564, 536, 536, 536,\n 536, 565, 532, 557, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 540, 540, 566, 567, 568,\n\n 532, 532, 532, 548, 532, 561, 548, 548, 569, 532,\n 563, 551, 551, 551, 551, 551, 551, 551, 551, 551,\n 551, 532, 532, 532, 532, 551, 551, 551, 551, 551,\n 551, 551, 551, 551, 551, 532, 532, 532, 551, 551,\n 551, 551, 551, 551, 532, 564, 536, 536, 536, 536,\n 532, 565, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 532, 566, 532, 567, 532, 568, 532, 532,\n 548, 548, 532, 569, 551, 551, 551, 551, 551, 551,\n 551, 551, 551, 551, 551, 551, 551, 551, 551, 551,\n\n 551, 551, 551, 551, 551, 551, 551, 551, 551, 536,\n 536, 536, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 540, 540, 540, 540, 540,\n 548, 548, 551, 551, 551, 551, 551, 551, 551, 551,\n 551, 551, 551, 551, 551, 551, 551, 551, 551, 551,\n 551, 536, 536, 540, 540, 540, 540, 540, 540, 540,\n 540, 540, 540, 540, 540, 540, 540, 540, 548, 548,\n 551, 551, 551, 551, 551, 551, 551, 551, 551, 551,\n 551, 551, 540, 540, 540, 540, 540, 540, 540, 540,\n 540, 548, 551, 551, 551, 551, 551, 551, 551, 551,\n\n 540, 540, 540, 540, 540, 540, 548, 551, 551, 551,\n 551, 551, 551, 540, 540, 540, 540, 548, 551, 551,\n 551, 551, 551, 540, 551, 551, 540, 551, 540, 540,\n 540, 0, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532\n } ;\n\nstatic const flex_int16_t yy_nxt[1035] =\n { 0,\n 16, 17, 18, 17, 16, 16, 19, 20, 16, 16,\n 16, 21, 21, 16, 16, 21, 21, 22, 16, 16,\n 16, 16, 16, 23, 16, 16, 16, 16, 16, 16,\n 22, 22, 16, 16, 16, 22, 24, 22, 22, 25,\n 22, 22, 22, 22, 22, 22, 22, 22, 26, 22,\n 22, 22, 22, 22, 22, 22, 22, 22, 27, 22,\n 22, 22, 28, 16, 16, 16, 30, 31, 32, 31,\n 30, 33, 34, 35, 30, 30, 30, 36, 36, 30,\n 30, 36, 30, 37, 30, 38, 39, 39, 39, 36,\n 40, 30, 36, 30, 30, 30, 37, 37, 36, 36,\n\n 30, 37, 41, 42, 43, 44, 45, 37, 37, 46,\n 37, 37, 37, 47, 37, 48, 49, 50, 37, 51,\n 52, 53, 37, 54, 55, 37, 37, 37, 30, 30,\n 30, 30, 57, 58, 59, 58, 57, 57, 57, 60,\n 57, 57, 57, 61, 61, 57, 57, 61, 57, 62,\n 57, 57, 57, 57, 57, 57, 57, 57, 57, 57,\n 57, 57, 62, 62, 57, 57, 57, 62, 62, 62,\n 62, 62, 62, 62, 62, 62, 62, 62, 62, 62,\n 62, 62, 62, 62, 62, 62, 62, 62, 62, 62,\n 62, 62, 62, 62, 63, 57, 57, 57, 65, 66,\n\n 67, 66, 68, 69, 68, 70, 68, 68, 65, 68,\n 68, 68, 68, 68, 68, 71, 68, 68, 68, 68,\n 68, 68, 68, 68, 68, 68, 68, 68, 71, 71,\n 68, 68, 72, 71, 71, 71, 71, 71, 71, 71,\n 71, 71, 73, 71, 71, 71, 71, 71, 71, 71,\n 71, 71, 71, 71, 71, 71, 71, 71, 71, 71,\n 68, 68, 68, 68, 75, 76, 77, 76, 78, 75,\n 79, 80, 75, 81, 75, 82, 82, 82, 82, 82,\n 82, 83, 82, 84, 85, 85, 85, 82, 82, 86,\n 82, 87, 75, 75, 88, 88, 89, 90, 91, 88,\n\n 88, 88, 88, 88, 88, 88, 92, 88, 88, 88,\n 88, 88, 88, 88, 88, 88, 88, 88, 88, 88,\n 93, 88, 88, 88, 88, 88, 94, 95, 75, 82,\n 97, 98, 99, 98, 100, 97, 101, 102, 103, 104,\n 97, 103, 103, 103, 103, 103, 103, 105, 103, 106,\n 107, 107, 107, 103, 103, 108, 109, 110, 97, 97,\n 105, 105, 103, 103, 111, 105, 112, 113, 114, 115,\n 116, 117, 118, 105, 119, 105, 105, 120, 105, 121,\n 105, 122, 105, 123, 124, 125, 105, 105, 105, 105,\n 105, 126, 97, 127, 128, 103, 132, 134, 144, 134,\n\n 144, 160, 150, 152, 152, 152, 152, 164, 168, 166,\n 174, 165, 174, 190, 196, 161, 167, 179, 169, 179,\n 187, 213, 187, 133, 151, 198, 198, 198, 198, 199,\n 200, 201, 202, 207, 311, 207, 197, 276, 191, 215,\n 215, 215, 215, 214, 216, 217, 219, 220, 223, 225,\n 277, 241, 192, 226, 224, 134, 295, 134, 231, 242,\n 243, 193, 296, 248, 227, 245, 228, 232, 233, 246,\n 234, 244, 235, 249, 250, 144, 290, 144, 306, 236,\n 237, 238, 273, 273, 251, 152, 152, 152, 152, 279,\n 274, 252, 280, 253, 174, 291, 174, 179, 187, 179,\n\n 187, 239, 531, 254, 255, 530, 256, 305, 305, 198,\n 198, 198, 198, 207, 394, 207, 310, 310, 257, 215,\n 215, 215, 215, 315, 337, 338, 273, 273, 395, 316,\n 305, 305, 310, 310, 130, 130, 130, 130, 130, 130,\n 131, 131, 131, 131, 131, 131, 135, 529, 135, 135,\n 135, 135, 137, 137, 142, 142, 142, 142, 142, 142,\n 145, 145, 145, 145, 147, 528, 147, 147, 147, 147,\n 149, 149, 172, 172, 172, 172, 172, 172, 176, 176,\n 177, 177, 177, 177, 177, 177, 180, 180, 180, 180,\n 183, 183, 185, 185, 185, 185, 185, 185, 189, 527,\n\n 189, 189, 189, 189, 195, 195, 205, 205, 205, 205,\n 205, 205, 209, 526, 209, 209, 209, 209, 212, 212,\n 261, 261, 261, 261, 261, 261, 263, 263, 263, 263,\n 263, 263, 265, 265, 265, 265, 265, 265, 267, 267,\n 272, 272, 298, 298, 299, 299, 300, 300, 309, 309,\n 346, 346, 346, 352, 352, 352, 374, 374, 374, 376,\n 376, 376, 378, 378, 378, 384, 384, 384, 525, 524,\n 523, 522, 521, 520, 519, 518, 517, 516, 515, 514,\n 513, 512, 511, 510, 509, 508, 507, 506, 505, 504,\n 503, 502, 501, 500, 499, 498, 497, 496, 495, 494,\n\n 493, 492, 491, 490, 489, 488, 487, 486, 485, 484,\n 483, 482, 481, 480, 479, 478, 477, 476, 475, 474,\n 473, 472, 471, 470, 469, 468, 467, 466, 465, 464,\n 463, 462, 461, 460, 459, 458, 457, 456, 455, 454,\n 453, 452, 451, 450, 449, 448, 447, 446, 445, 444,\n 443, 442, 441, 440, 439, 438, 437, 436, 435, 434,\n 433, 383, 432, 431, 377, 375, 373, 430, 429, 428,\n 427, 426, 425, 424, 423, 422, 421, 420, 419, 418,\n 417, 416, 415, 414, 413, 351, 412, 411, 410, 345,\n 409, 408, 407, 406, 405, 404, 403, 402, 401, 400,\n\n 399, 398, 397, 396, 393, 392, 391, 390, 389, 388,\n 387, 386, 385, 383, 382, 381, 380, 379, 377, 375,\n 373, 372, 371, 370, 369, 368, 367, 366, 365, 364,\n 363, 362, 361, 360, 359, 358, 357, 356, 355, 354,\n 353, 351, 350, 349, 348, 347, 345, 266, 264, 262,\n 344, 343, 342, 341, 340, 339, 336, 335, 334, 333,\n 332, 331, 330, 329, 328, 327, 326, 325, 324, 323,\n 322, 321, 320, 319, 318, 317, 314, 313, 312, 206,\n 308, 307, 304, 303, 302, 301, 186, 180, 181, 178,\n 173, 297, 294, 293, 292, 289, 288, 287, 286, 285,\n\n 284, 283, 282, 281, 278, 275, 145, 146, 143, 271,\n 270, 269, 268, 266, 264, 262, 260, 259, 258, 247,\n 240, 230, 229, 222, 221, 218, 211, 210, 208, 206,\n 204, 203, 194, 188, 186, 184, 182, 181, 178, 175,\n 173, 171, 170, 163, 162, 159, 158, 157, 156, 155,\n 154, 153, 148, 146, 143, 141, 140, 139, 138, 136,\n 532, 129, 96, 74, 64, 56, 29, 15, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532\n } ;\n\nstatic const flex_int16_t yy_chk[1035] =\n { 0,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n 1, 1, 1, 1, 1, 1, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\n 3, 3, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n 5, 5, 5, 5, 5, 5, 5, 5, 7, 7,\n\n 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n 7, 7, 7, 7, 9, 9, 9, 9, 9, 9,\n 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,\n 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,\n 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,\n\n 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,\n 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,\n 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n 11, 11, 11, 11, 11, 11, 14, 17, 31, 17,\n\n 31, 48, 38, 39, 39, 39, 39, 51, 53, 52,\n 58, 51, 58, 80, 84, 48, 52, 66, 53, 66,\n 76, 106, 76, 14, 38, 85, 85, 85, 85, 86,\n 86, 87, 87, 98, 563, 98, 84, 154, 80, 107,\n 107, 107, 107, 106, 108, 108, 110, 110, 113, 114,\n 154, 119, 80, 114, 113, 134, 170, 134, 117, 119,\n 120, 80, 170, 123, 114, 121, 114, 117, 117, 121,\n 117, 120, 117, 123, 124, 144, 166, 144, 561, 117,\n 117, 117, 150, 150, 124, 152, 152, 152, 152, 156,\n 557, 124, 156, 124, 174, 166, 174, 179, 187, 179,\n\n 187, 117, 530, 124, 124, 529, 124, 196, 196, 198,\n 198, 198, 198, 207, 326, 207, 213, 213, 124, 215,\n 215, 215, 215, 225, 253, 253, 273, 273, 326, 225,\n 305, 305, 310, 310, 533, 533, 533, 533, 533, 533,\n 534, 534, 534, 534, 534, 534, 535, 527, 535, 535,\n 535, 535, 536, 536, 537, 537, 537, 537, 537, 537,\n 538, 538, 538, 538, 539, 526, 539, 539, 539, 539,\n 540, 540, 541, 541, 541, 541, 541, 541, 542, 542,\n 543, 543, 543, 543, 543, 543, 544, 544, 544, 544,\n 545, 545, 546, 546, 546, 546, 546, 546, 547, 524,\n\n 547, 547, 547, 547, 548, 548, 549, 549, 549, 549,\n 549, 549, 550, 521, 550, 550, 550, 550, 551, 551,\n 552, 552, 552, 552, 552, 552, 553, 553, 553, 553,\n 553, 553, 554, 554, 554, 554, 554, 554, 555, 555,\n 556, 556, 558, 558, 559, 559, 560, 560, 562, 562,\n 564, 564, 564, 565, 565, 565, 566, 566, 566, 567,\n 567, 567, 568, 568, 568, 569, 569, 569, 519, 516,\n 512, 511, 510, 509, 508, 507, 505, 504, 503, 501,\n 499, 498, 496, 495, 494, 493, 492, 491, 490, 489,\n 488, 484, 483, 481, 479, 478, 477, 476, 475, 473,\n\n 472, 469, 468, 467, 464, 463, 462, 457, 456, 455,\n 454, 450, 449, 447, 446, 445, 444, 442, 440, 439,\n 438, 437, 433, 432, 431, 430, 429, 428, 425, 424,\n 423, 422, 421, 420, 418, 417, 416, 415, 414, 413,\n 411, 410, 408, 405, 404, 403, 402, 401, 400, 399,\n 398, 397, 395, 394, 393, 392, 391, 390, 388, 386,\n 385, 384, 382, 381, 378, 376, 374, 372, 371, 370,\n 368, 367, 365, 364, 363, 362, 361, 360, 359, 358,\n 357, 356, 355, 354, 353, 352, 349, 348, 347, 346,\n 344, 343, 342, 341, 340, 339, 335, 334, 333, 332,\n\n 330, 329, 328, 327, 321, 320, 319, 318, 317, 316,\n 315, 314, 313, 309, 308, 307, 303, 301, 300, 299,\n 298, 297, 296, 295, 294, 293, 292, 291, 290, 289,\n 288, 287, 286, 285, 284, 283, 281, 280, 278, 277,\n 275, 272, 271, 270, 269, 268, 267, 265, 263, 261,\n 259, 258, 257, 256, 255, 254, 252, 249, 248, 247,\n 246, 245, 244, 243, 242, 240, 239, 238, 237, 236,\n 231, 230, 229, 228, 227, 226, 224, 223, 222, 205,\n 204, 203, 194, 193, 192, 191, 185, 181, 180, 177,\n 172, 171, 169, 168, 167, 165, 164, 163, 162, 161,\n\n 160, 159, 158, 157, 155, 153, 146, 145, 142, 141,\n 140, 139, 138, 133, 131, 129, 127, 126, 125, 122,\n 118, 116, 115, 112, 111, 109, 104, 102, 100, 96,\n 93, 92, 83, 78, 74, 73, 70, 69, 64, 60,\n 56, 55, 54, 50, 49, 47, 46, 45, 44, 43,\n 42, 41, 35, 33, 29, 27, 26, 25, 24, 20,\n 15, 12, 10, 8, 6, 4, 2, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532, 532, 532, 532, 532, 532, 532,\n 532, 532, 532, 532\n } ;\n\nstatic yy_state_type yy_last_accepting_state;\nstatic char *yy_last_accepting_cpos;\n\nextern int yy_flex_debug;\nint yy_flex_debug = 0;\n\n/* The intent behind this definition is that it'll catch\n * any uses of REJECT which flex missed.\n */\n#define REJECT reject_used_but_not_detected\n#define yymore() yymore_used_but_not_detected\n#define YY_MORE_ADJ 0\n#define YY_RESTORE_YY_MORE_OFFSET\nchar *yytext;\n/* ###\n * IP: GHIDRA\n * NOTE: flex skeletons are NOT bound by flex's BSD license\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#define sleighwrap() 1\n#define YY_SKIP_YYWRAP\n\n/* If we are building don't include unistd.h */\n/* flex provides us with this macro for turning it off */\n#ifdef _WIN32\n#define YY_NO_UNISTD_H\nstatic int isatty (int fildes) { return 0; }\n#endif\n\n#include \"slgh_compile.hh\"\n\nnamespace ghidra {\n\n#include \"slghparse.hh\"\n\nstruct FileStreamState {\n YY_BUFFER_STATE lastbuffer;\t// Last lex buffer corresponding to the stream\n FILE *file; // The NEW file stream\n};\n\nextern SleighCompile *slgh;\nint4 last_preproc; // lex state before last preprocessing erasure\nint4 actionon; // whether '&' '|' and '^' are treated as actionon in pattern section\nint4 withsection = 0; // whether we are between the 'with' keyword and its open brace '{'\nvector filebuffers;\nvector ifstack;\nint4 negative_if = -1;\n\nvoid preproc_error(const string &err)\n\n{\n slgh->reportError((const Location *)0, err);\n cerr << \"Terminating due to error in preprocessing\" << endl;\n exit(1);\n}\n\nvoid check_to_endofline(istream &s)\n\n{ // Make sure there is nothing to the end of the line\n s >> ws;\n if (!s.eof())\n if (s.peek() != '#')\n preproc_error(\"Extra characters in preprocessor directive\"); \n}\n\nstring read_identifier(istream &s)\n\n{ // Read a proper identifier from the stream\n s >> ws; // Skip any whitespace\n string res;\n while(!s.eof()) {\n char tok = s.peek();\n if (isalnum(tok) || (tok == '_')) {\n s >> tok;\n res += tok;\n }\n else\n break;\n }\n return res;\n}\n\nvoid preprocess_string(istream &s,string &res)\n\n{ // Grab string surrounded by double quotes from stream or call preprocess_error\n int4 val;\n \n s >> ws; // Skip any whitespace\n val = s.get();\n if (val != '\\\"')\n preproc_error(\"Expecting double quoted string\");\n val = s.get();\n while((val != '\\\"')&&(val>=0)) {\n res += (char)val;\n val = s.get();\n }\n if (val != '\\\"')\n preproc_error(\"Missing terminating double quote\");\n}\n\nextern int4 preprocess_if(istream &s); // Forward declaration for recursion\n\nint4 read_defined_operator(istream &s)\n\n{ // We have seen a -defined- keyword in an if or elif\n // Read macro name used as input, return 1 if it is defined\n char tok = ' ';\n string macroname;\n \n s >> ws >> tok;\n if (tok != '(')\n preproc_error(\"Badly formed \\\"defined\\\" operator\");\n macroname = read_identifier(s);\n int4 res = slgh->getPreprocValue(macroname,macroname) ? 1 : 0;\n s >> ws >> tok;\n if (tok != ')')\n preproc_error(\"Badly formed \\\"defined\\\" operator\");\n return res;\n}\n\nint4 read_boolean_clause(istream &s)\n\n{\t\t\t\t// We have seen an if or elif\n\t\t\t\t// return 1 if condition is true or else 0\n s >> ws;\n if (s.peek()=='(') {\t\t// Parenthetical expression spawns recursion\n int4 val = s.get();\n int4 res = preprocess_if(s);\n s >> ws;\n val = s.get();\n if (val != ')')\n preproc_error(\"Unbalanced parentheses\");\n return res;\n }\n\t\t\t\t// Otherwise we must have a normal comparison operator\n string lhs,rhs,comp;\n\n if (s.peek()=='\\\"')\t\t// Read left-hand side string\n preprocess_string(s,lhs);\n else {\n lhs = read_identifier(s);\n if (lhs == \"defined\")\n return read_defined_operator(s);\n if (!slgh->getPreprocValue(lhs,lhs))\n preproc_error(\"Could not find preprocessor macro \"+lhs);\n }\n\n char tok;\n s >> tok; // Read comparison symbol\n comp += tok;\n s >> tok;\n comp += tok;\n \n s >> ws;\n if (s.peek()=='\\\"') // Read right-hand side string\n preprocess_string(s,rhs);\n else {\n rhs = read_identifier(s);\n if (!slgh->getPreprocValue(rhs,rhs))\n preproc_error(\"Could not find preprocessor macro \"+rhs);\n }\n\n if (comp == \"==\")\n return (lhs == rhs) ? 1 : 0;\n else if (comp==\"!=\")\n return (lhs != rhs) ? 1 : 0;\n else\n preproc_error(\"Syntax error in condition\");\n return 0;\n}\n\nint4 preprocess_if(istream &s)\n\n{\n int4 res = read_boolean_clause(s);\n s >> ws;\n while((!s.eof())&&(s.peek()!=')')) {\n string boolop;\n char tok;\n s >> tok;\n boolop += tok;\n s >> tok;\n boolop += tok;\n int4 res2 = read_boolean_clause(s);\n if (boolop == \"&&\")\n res = res & res2;\n else if (boolop == \"||\")\n res = res | res2;\n else if (boolop == \"^^\")\n res = res ^ res2;\n else\n preproc_error(\"Syntax error in expression\");\n s >> ws;\n }\n return res;\n}\n\nvoid expand_preprocmacros(string &str)\n\n{\n string::size_type pos;\n string::size_type lastpos = 0;\n pos = str.find(\"$(\",lastpos);\n if (pos == string::npos)\n return;\n string res;\n for(;;) {\n if (pos == string::npos) {\n res += str.substr(lastpos);\n str = res;\n return;\n }\n else {\n res += str.substr(lastpos,(pos-lastpos));\n string::size_type endpos = str.find(')',pos+2);\n if (endpos == string::npos) {\n\tpreproc_error(\"Unterminated macro in string\");\n\tbreak;\n }\n string macro = str.substr(pos+2, endpos - (pos+2));\n string value;\n if (!slgh->getPreprocValue(macro,value)) {\n\tpreproc_error(\"Unknown preprocessing macro \"+macro);\n\tbreak;\n }\n res += value;\n lastpos = endpos + 1;\n }\n pos = str.find(\"$(\",lastpos);\n }\n}\n\nint4 preprocess(int4 cur_state,int4 blank_state)\n\n{\n string str(sleightext);\n string::size_type pos = str.find('#');\n if (pos != string::npos)\n str.erase(pos);\n istringstream s(str);\n string type;\n\n if (cur_state != blank_state)\n last_preproc = cur_state;\n\n s.get(); // Skip the preprocessor marker\n s >> type;\n if (type == \"include\") {\n if (negative_if == -1) { // Not in the middle of a false if clause\n filebuffers.push_back(FileStreamState()); // Save state of current file\n filebuffers.back().lastbuffer = YY_CURRENT_BUFFER;\n filebuffers.back().file = (FILE *)0;\n s >> ws;\n string fname;\n preprocess_string(s,fname);\n expand_preprocmacros(fname);\n slgh->parseFromNewFile(fname);\n fname = slgh->grabCurrentFilePath();\n sleighin = fopen(fname.c_str(),\"r\");\n if (sleighin == (FILE *)0)\n preproc_error(\"Could not open included file \"+fname);\n filebuffers.back().file = sleighin;\n sleigh_switch_to_buffer( sleigh_create_buffer(sleighin, YY_BUF_SIZE) );\n check_to_endofline(s);\n }\n }\n else if (type == \"define\") {\n if (negative_if == -1) {\n string varname;\n string value;\n varname = read_identifier(s); // Get name of variable being defined\n s >> ws;\n if (s.peek() == '\\\"')\n preprocess_string(s,value);\n else\n value = read_identifier(s);\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor definition\");\n slgh->setPreprocValue(varname,value);\n check_to_endofline(s);\n }\n }\n else if (type == \"undef\") {\n if (negative_if == -1) {\n string varname;\n varname = read_identifier(s);\t\t// Name of variable to undefine\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor undef\");\n slgh->undefinePreprocValue(varname);\n check_to_endofline(s);\n }\n }\n else if (type==\"ifdef\") {\n string varname;\n varname = read_identifier(s);\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor ifdef\");\n string value;\n int4 truth = (slgh->getPreprocValue(varname,value)) ? 1 : 0;\n ifstack.push_back(truth);\n check_to_endofline(s);\n }\n else if (type==\"ifndef\") {\n string varname;\n varname = read_identifier(s);\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor ifndef\");\n string value;\n int4 truth = (slgh->getPreprocValue(varname,value)) ? 0 : 1;\t// flipped from ifdef\n ifstack.push_back(truth);\n check_to_endofline(s);\n }\n else if (type==\"if\") {\n int4 truth = preprocess_if(s);\n if (!s.eof())\n preproc_error(\"Unbalanced parentheses\");\n ifstack.push_back(truth);\n }\n else if (type==\"elif\") {\n if (ifstack.empty())\n preproc_error(\"elif without preceding if\");\n if ((ifstack.back()&2)!=0)\t\t// We have already seen an else clause\n preproc_error(\"elif follows else\");\n if ((ifstack.back()&4)!=0) // We have already seen a true elif clause\n ifstack.back() = 4; // don't include any other elif clause\n else if ((ifstack.back()&1)!=0) // Last clause was a true if\n ifstack.back() = 4; // don't include this elif\n else {\n int4 truth = preprocess_if(s);\n if (!s.eof())\n preproc_error(\"Unbalanced parentheses\");\n if (truth==0)\n ifstack.back() = 0;\n else\n ifstack.back() = 5;\n }\n }\n else if (type==\"endif\") {\n if (ifstack.empty())\n preproc_error(\"preprocessing endif without matching if\");\n ifstack.pop_back();\n check_to_endofline(s);\n }\n else if (type==\"else\") {\n if (ifstack.empty())\n preproc_error(\"preprocessing else without matching if\");\n if ((ifstack.back()&2)!=0)\n preproc_error(\"second else for one if\");\n if ((ifstack.back()&4)!=0) // Seen a true elif clause before\n ifstack.back() = 6;\n else if (ifstack.back()==0)\n ifstack.back() = 3;\n else\n ifstack.back() = 2;\n check_to_endofline(s);\n }\n else\n preproc_error(\"Unknown preprocessing directive: \"+type);\n\n if (negative_if >= 0) { // We were in a false state\n if (negative_if+1 < ifstack.size())\n return blank_state; // false state is still deep in stack\n else // false state is popped off or is current and changed\n negative_if = -1;\n }\n if (ifstack.empty()) return last_preproc;\n if ((ifstack.back()&1)==0) {\n negative_if = ifstack.size()-1;\n return blank_state;\n }\n return last_preproc;\n}\n\nvoid preproc_macroexpand(void)\n\n{\n filebuffers.push_back(FileStreamState());\n filebuffers.back().lastbuffer = YY_CURRENT_BUFFER;\n filebuffers.back().file = (FILE *)0;\n string macro(sleightext);\n macro.erase(0,2);\n macro.erase(macro.size()-1,1);\n string value;\n if (!slgh->getPreprocValue(macro,value))\n preproc_error(\"Unknown preprocessing macro \"+macro);\n sleigh_switch_to_buffer( sleigh_scan_string( value.c_str() ) );\n slgh->parsePreprocMacro();\n}\n\nint4 find_symbol(void) {\n string * newstring = new string(sleightext);\n SleighSymbol *sym = slgh->findSymbol(*newstring);\n if (sym == (SleighSymbol *)0) {\n sleighlval.str = newstring;\n return STRING;\n }\n delete newstring;\n switch(sym->getType()) {\n case SleighSymbol::section_symbol:\n sleighlval.sectionsym = (SectionSymbol *)sym;\n return SECTIONSYM;\n case SleighSymbol::space_symbol:\n sleighlval.spacesym = (SpaceSymbol *)sym;\n return SPACESYM;\n case SleighSymbol::token_symbol:\n sleighlval.tokensym = (TokenSymbol *)sym;\n return TOKENSYM;\n case SleighSymbol::userop_symbol:\n sleighlval.useropsym = (UserOpSymbol *)sym;\n return USEROPSYM;\n case SleighSymbol::value_symbol:\n sleighlval.valuesym = (ValueSymbol *)sym;\n return VALUESYM;\n case SleighSymbol::valuemap_symbol:\n sleighlval.valuemapsym = (ValueMapSymbol *)sym;\n return VALUEMAPSYM;\n case SleighSymbol::name_symbol:\n sleighlval.namesym = (NameSymbol *)sym;\n return NAMESYM;\n case SleighSymbol::varnode_symbol:\n sleighlval.varsym = (VarnodeSymbol *)sym;\n return VARSYM;\n case SleighSymbol::bitrange_symbol:\n sleighlval.bitsym = (BitrangeSymbol *)sym;\n return BITSYM;\n case SleighSymbol::varnodelist_symbol:\n sleighlval.varlistsym = (VarnodeListSymbol *)sym;\n return VARLISTSYM;\n case SleighSymbol::operand_symbol:\n sleighlval.operandsym = (OperandSymbol *)sym;\n return OPERANDSYM;\n case SleighSymbol::start_symbol:\n case SleighSymbol::end_symbol:\n case SleighSymbol::next2_symbol:\n case SleighSymbol::flowdest_symbol:\n case SleighSymbol::flowref_symbol:\n sleighlval.specsym = (SpecificSymbol *)sym;\n return JUMPSYM;\n case SleighSymbol::subtable_symbol:\n sleighlval.subtablesym = (SubtableSymbol *)sym;\n return SUBTABLESYM;\n case SleighSymbol::macro_symbol:\n sleighlval.macrosym = (MacroSymbol *)sym;\n return MACROSYM;\n case SleighSymbol::label_symbol:\n sleighlval.labelsym = (LabelSymbol *)sym;\n return LABELSYM;\n case SleighSymbol::epsilon_symbol:\n sleighlval.specsym = (SpecificSymbol *)sym;\n return SPECSYM;\n case SleighSymbol::context_symbol:\n sleighlval.contextsym = (ContextSymbol *)sym;\n return CONTEXTSYM;\n case SleighSymbol::dummy_symbol:\n break;\n }\n return -1; // Should never reach here\n}\n\nint4 scan_number(char *numtext,SLEIGHSTYPE *lval,bool signednum)\n\n{\n uintb val;\n if (numtext[0] == '0' && numtext[1] == 'b') {\n val = 0;\n numtext += 2;\n while ((*numtext) != 0) {\n val <<= 1;\n if (*numtext == '1') {\n val |= 1;\n }\n ++numtext;\n }\n } else {\n istringstream s(numtext);\n s.unsetf(ios::dec | ios::hex | ios::oct);\n s >> val;\n if (!s)\n return BADINTEGER;\n }\n if (signednum) {\n lval->big = new intb(val);\n return INTB;\n }\n lval->i = new uintb(val);\n return INTEGER;\n}\n\n} // End namespace ghidra\n\nusing namespace ghidra;\n\n#define INITIAL 0\n#define defblock 1\n#define macroblock 2\n#define print 3\n#define pattern 4\n#define sem 5\n#define preproc 6\n\n#ifndef YY_NO_UNISTD_H\n/* Special case for \"unistd.h\", since it is non-ANSI. We include it way\n * down here because we want the user's section 1 to have been scanned first.\n * The user has a chance to override it with an option.\n */\n#include \n#endif\n\n#ifndef YY_EXTRA_TYPE\n#define YY_EXTRA_TYPE void *\n#endif\n\nstatic int yy_init_globals ( void );\n\n/* Accessor methods to globals.\n These are made visible to non-reentrant scanners for convenience. */\n\nint yylex_destroy ( void );\n\nint yyget_debug ( void );\n\nvoid yyset_debug ( int debug_flag );\n\nYY_EXTRA_TYPE yyget_extra ( void );\n\nvoid yyset_extra ( YY_EXTRA_TYPE user_defined );\n\nFILE *yyget_in ( void );\n\nvoid yyset_in ( FILE * _in_str );\n\nFILE *yyget_out ( void );\n\nvoid yyset_out ( FILE * _out_str );\n\n\t\t\tint yyget_leng ( void );\n\nchar *yyget_text ( void );\n\nint yyget_lineno ( void );\n\nvoid yyset_lineno ( int _line_number );\n\n/* Macros after this point can all be overridden by user definitions in\n * section 1.\n */\n\n#ifndef YY_SKIP_YYWRAP\n#ifdef __cplusplus\nextern \"C\" int yywrap ( void );\n#else\nextern int yywrap ( void );\n#endif\n#endif\n\n#ifndef YY_NO_UNPUT\n \n static void yyunput ( int c, char *buf_ptr );\n \n#endif\n\n#ifndef yytext_ptr\nstatic void yy_flex_strncpy ( char *, const char *, int );\n#endif\n\n#ifdef YY_NEED_STRLEN\nstatic int yy_flex_strlen ( const char * );\n#endif\n\n#ifndef YY_NO_INPUT\n#ifdef __cplusplus\nstatic int yyinput ( void );\n#else\nstatic int input ( void );\n#endif\n\n#endif\n\n/* Amount of stuff to slurp up with each read. */\n#ifndef YY_READ_BUF_SIZE\n#ifdef __ia64__\n/* On IA-64, the buffer size is 16k, not 8k */\n#define YY_READ_BUF_SIZE 16384\n#else\n#define YY_READ_BUF_SIZE 8192\n#endif /* __ia64__ */\n#endif\n\n/* Copy whatever the last rule matched to the standard output. */\n#ifndef ECHO\n/* This used to be an fputs(), but since the string might contain NUL's,\n * we now use fwrite().\n */\n#define ECHO do { if (fwrite( yytext, (size_t) yyleng, 1, yyout )) {} } while (0)\n#endif\n\n/* Gets input and stuffs it into \"buf\". number of characters read, or YY_NULL,\n * is returned in \"result\".\n */\n#ifndef YY_INPUT\n#define YY_INPUT(buf,result,max_size) \\\n\tif ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \\\n\t\t{ \\\n\t\tint c = '*'; \\\n\t\tint n; \\\n\t\tfor ( n = 0; n < max_size && \\\n\t\t\t (c = getc( yyin )) != EOF && c != '\\n'; ++n ) \\\n\t\t\tbuf[n] = (char) c; \\\n\t\tif ( c == '\\n' ) \\\n\t\t\tbuf[n++] = (char) c; \\\n\t\tif ( c == EOF && ferror( yyin ) ) \\\n\t\t\tYY_FATAL_ERROR( \"input in flex scanner failed\" ); \\\n\t\tresult = n; \\\n\t\t} \\\n\telse \\\n\t\t{ \\\n\t\terrno=0; \\\n\t\twhile ( (result = (int) fread(buf, 1, (yy_size_t) max_size, yyin)) == 0 && ferror(yyin)) \\\n\t\t\t{ \\\n\t\t\tif( errno != EINTR) \\\n\t\t\t\t{ \\\n\t\t\t\tYY_FATAL_ERROR( \"input in flex scanner failed\" ); \\\n\t\t\t\tbreak; \\\n\t\t\t\t} \\\n\t\t\terrno=0; \\\n\t\t\tclearerr(yyin); \\\n\t\t\t} \\\n\t\t}\\\n\\\n\n#endif\n\n/* No semi-colon after return; correct usage is to write \"yyterminate();\" -\n * we don't want an extra ';' after the \"return\" because that will cause\n * some compilers to complain about unreachable statements.\n */\n#ifndef yyterminate\n#define yyterminate() return YY_NULL\n#endif\n\n/* Number of entries by which start-condition stack grows. */\n#ifndef YY_START_STACK_INCR\n#define YY_START_STACK_INCR 25\n#endif\n\n/* Report a fatal error. */\n#ifndef YY_FATAL_ERROR\n#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )\n#endif\n\n/* end tables serialization structures and prototypes */\n\n/* Default declaration of generated scanner - a define so the user can\n * easily add parameters.\n */\n#ifndef YY_DECL\n#define YY_DECL_IS_OURS 1\n\nextern int yylex (void);\n\n#define YY_DECL int yylex (void)\n#endif /* !YY_DECL */\n\n/* Code executed at the beginning of each rule, after yytext and yyleng\n * have been set up.\n */\n#ifndef YY_USER_ACTION\n#define YY_USER_ACTION\n#endif\n\n/* Code executed at the end of each rule. */\n#ifndef YY_BREAK\n#define YY_BREAK /*LINTED*/break;\n#endif\n\n#define YY_RULE_SETUP \\\n\tif ( yyleng > 0 ) \\\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_at_bol = \\\n\t\t\t\t(yytext[yyleng - 1] == '\\n'); \\\n\tYY_USER_ACTION\n\n/** The main scanner function which does all the work.\n */\nYY_DECL\n{\n\tyy_state_type yy_current_state;\n\tchar *yy_cp, *yy_bp;\n\tint yy_act;\n \n\tif ( !(yy_init) )\n\t\t{\n\t\t(yy_init) = 1;\n\n#ifdef YY_USER_INIT\n\t\tYY_USER_INIT;\n#endif\n\n\t\tif ( ! (yy_start) )\n\t\t\t(yy_start) = 1;\t/* first start state */\n\n\t\tif ( ! yyin )\n\t\t\tyyin = stdin;\n\n\t\tif ( ! yyout )\n\t\t\tyyout = stdout;\n\n\t\tif ( ! YY_CURRENT_BUFFER ) {\n\t\t\tyyensure_buffer_stack ();\n\t\t\tYY_CURRENT_BUFFER_LVALUE =\n\t\t\t\tyy_create_buffer( yyin, YY_BUF_SIZE );\n\t\t}\n\n\t\tyy_load_buffer_state( );\n\t\t}\n\n\t{\n\n\twhile ( /*CONSTCOND*/1 )\t\t/* loops until end-of-file is reached */\n\t\t{\n\t\tyy_cp = (yy_c_buf_p);\n\n\t\t/* Support of yytext. */\n\t\t*yy_cp = (yy_hold_char);\n\n\t\t/* yy_bp points to the position in yy_ch_buf of the start of\n\t\t * the current run.\n\t\t */\n\t\tyy_bp = yy_cp;\n\n\t\tyy_current_state = (yy_start);\n\t\tyy_current_state += YY_AT_BOL();\nyy_match:\n\t\tdo\n\t\t\t{\n\t\t\tYY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ;\n\t\t\tif ( yy_accept[yy_current_state] )\n\t\t\t\t{\n\t\t\t\t(yy_last_accepting_state) = yy_current_state;\n\t\t\t\t(yy_last_accepting_cpos) = yy_cp;\n\t\t\t\t}\n\t\t\twhile ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )\n\t\t\t\t{\n\t\t\t\tyy_current_state = (int) yy_def[yy_current_state];\n\t\t\t\tif ( yy_current_state >= 533 )\n\t\t\t\t\tyy_c = yy_meta[yy_c];\n\t\t\t\t}\n\t\t\tyy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c];\n\t\t\t++yy_cp;\n\t\t\t}\n\t\twhile ( yy_base[yy_current_state] != 968 );\n\nyy_find_action:\n\t\tyy_act = yy_accept[yy_current_state];\n\t\tif ( yy_act == 0 )\n\t\t\t{ /* have to back up */\n\t\t\tyy_cp = (yy_last_accepting_cpos);\n\t\t\tyy_current_state = (yy_last_accepting_state);\n\t\t\tyy_act = yy_accept[yy_current_state];\n\t\t\t}\n\n\t\tYY_DO_BEFORE_ACTION;\n\ndo_action:\t/* This label is used only to access EOF actions. */\n\n\t\tswitch ( yy_act )\n\t{ /* beginning of action switch */\n\t\t\tcase 0: /* must back up */\n\t\t\t/* undo the effects of YY_DO_BEFORE_ACTION */\n\t\t\t*yy_cp = (yy_hold_char);\n\t\t\tyy_cp = (yy_last_accepting_cpos);\n\t\t\tyy_current_state = (yy_last_accepting_state);\n\t\t\tgoto yy_find_action;\n\ncase 1:\n/* rule 1 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(INITIAL,preproc) ); }\n\tYY_BREAK\ncase 2:\nYY_RULE_SETUP\n{ preproc_macroexpand(); }\n\tYY_BREAK\ncase 3:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 4:\nYY_RULE_SETUP\n{ BEGIN(print); slgh->calcContextLayout(); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 5:\nYY_RULE_SETUP\n{ BEGIN(sem); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 6:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 7:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 8:\n/* rule 8 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); }\n\tYY_BREAK\ncase 9:\nYY_RULE_SETUP\n{ BEGIN(macroblock); return MACRO_KEY; }\n\tYY_BREAK\ncase 10:\nYY_RULE_SETUP\n{ BEGIN(defblock); return DEFINE_KEY; }\n\tYY_BREAK\ncase 11:\nYY_RULE_SETUP\n{ BEGIN(defblock); slgh->calcContextLayout(); return ATTACH_KEY; }\n\tYY_BREAK\ncase 12:\nYY_RULE_SETUP\n{ BEGIN(pattern); withsection = 1; slgh->calcContextLayout(); return WITH_KEY; }\n\tYY_BREAK\ncase 13:\nYY_RULE_SETUP\n{ return find_symbol(); }\n\tYY_BREAK\ncase 14:\nYY_RULE_SETUP\n{ return sleightext[0]; }\n\tYY_BREAK\ncase 15:\n/* rule 15 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(macroblock,preproc) ); }\n\tYY_BREAK\ncase 16:\nYY_RULE_SETUP\n{ preproc_macroexpand(); }\n\tYY_BREAK\ncase 17:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 18:\nYY_RULE_SETUP\n{ BEGIN(sem); return sleightext[0]; }\n\tYY_BREAK\ncase 19:\nYY_RULE_SETUP\n{ sleighlval.str = new string(sleightext); return STRING; }\n\tYY_BREAK\ncase 20:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 21:\n/* rule 21 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); }\n\tYY_BREAK\ncase 22:\nYY_RULE_SETUP\n{ return sleightext[0]; }\n\tYY_BREAK\ncase 23:\n/* rule 23 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(defblock,preproc) ); }\n\tYY_BREAK\ncase 24:\nYY_RULE_SETUP\n{ preproc_macroexpand(); }\n\tYY_BREAK\ncase 25:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 26:\nYY_RULE_SETUP\n{ BEGIN(INITIAL); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 27:\nYY_RULE_SETUP\n{ return SPACE_KEY; }\n\tYY_BREAK\ncase 28:\nYY_RULE_SETUP\n{ return TYPE_KEY; }\n\tYY_BREAK\ncase 29:\nYY_RULE_SETUP\n{ return RAM_KEY; }\n\tYY_BREAK\ncase 30:\nYY_RULE_SETUP\n{ return DEFAULT_KEY; }\n\tYY_BREAK\ncase 31:\nYY_RULE_SETUP\n{ return REGISTER_KEY; }\n\tYY_BREAK\ncase 32:\nYY_RULE_SETUP\n{ return TOKEN_KEY; }\n\tYY_BREAK\ncase 33:\nYY_RULE_SETUP\n{ return CONTEXT_KEY; }\n\tYY_BREAK\ncase 34:\nYY_RULE_SETUP\n{ return BITRANGE_KEY; }\n\tYY_BREAK\ncase 35:\nYY_RULE_SETUP\n{ return SIGNED_KEY; }\n\tYY_BREAK\ncase 36:\nYY_RULE_SETUP\n{ return NOFLOW_KEY; }\n\tYY_BREAK\ncase 37:\nYY_RULE_SETUP\n{ return HEX_KEY; }\n\tYY_BREAK\ncase 38:\nYY_RULE_SETUP\n{ return DEC_KEY; }\n\tYY_BREAK\ncase 39:\nYY_RULE_SETUP\n{ return ENDIAN_KEY; }\n\tYY_BREAK\ncase 40:\nYY_RULE_SETUP\n{ return ALIGN_KEY; }\n\tYY_BREAK\ncase 41:\nYY_RULE_SETUP\n{ return BIG_KEY; }\n\tYY_BREAK\ncase 42:\nYY_RULE_SETUP\n{ return LITTLE_KEY; }\n\tYY_BREAK\ncase 43:\nYY_RULE_SETUP\n{ return SIZE_KEY; }\n\tYY_BREAK\ncase 44:\nYY_RULE_SETUP\n{ return WORDSIZE_KEY; }\n\tYY_BREAK\ncase 45:\nYY_RULE_SETUP\n{ return OFFSET_KEY; }\n\tYY_BREAK\ncase 46:\nYY_RULE_SETUP\n{ return NAMES_KEY; }\n\tYY_BREAK\ncase 47:\nYY_RULE_SETUP\n{ return VALUES_KEY; }\n\tYY_BREAK\ncase 48:\nYY_RULE_SETUP\n{ return VARIABLES_KEY; }\n\tYY_BREAK\ncase 49:\nYY_RULE_SETUP\n{ return PCODEOP_KEY; }\n\tYY_BREAK\ncase 50:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 51:\nYY_RULE_SETUP\n{ return find_symbol(); }\n\tYY_BREAK\ncase 52:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,false); }\n\tYY_BREAK\ncase 53:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,false); }\n\tYY_BREAK\ncase 54:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,false); }\n\tYY_BREAK\ncase 55:\nYY_RULE_SETUP\n{ sleighlval.str = new string(sleightext+1,strlen(sleightext)-2); return STRING; }\n\tYY_BREAK\ncase 56:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 57:\n/* rule 57 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); }\n\tYY_BREAK\ncase 58:\nYY_RULE_SETUP\n{ return sleightext[0]; }\n\tYY_BREAK\ncase 59:\n/* rule 59 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(print,preproc) ); }\n\tYY_BREAK\ncase 60:\nYY_RULE_SETUP\n{ preproc_macroexpand(); }\n\tYY_BREAK\ncase 61:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return CHAR; }\n\tYY_BREAK\ncase 62:\nYY_RULE_SETUP\n{ sleighlval.ch = '^'; return '^'; }\n\tYY_BREAK\ncase 63:\nYY_RULE_SETUP\n{ BEGIN(pattern); actionon=0; return IS_KEY; }\n\tYY_BREAK\ncase 64:\nYY_RULE_SETUP\n{ sleighlval.str = new string(sleightext); return SYMBOLSTRING; }\n\tYY_BREAK\ncase 65:\nYY_RULE_SETUP\n{ sleighlval.str = new string(sleightext+1,strlen(sleightext)-2); return STRING; }\n\tYY_BREAK\ncase 66:\nYY_RULE_SETUP\n{ sleighlval.ch = ' '; return ' '; }\n\tYY_BREAK\ncase 67:\n/* rule 67 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); return ' '; }\n\tYY_BREAK\ncase 68:\nYY_RULE_SETUP\n{ return sleightext[0]; }\n\tYY_BREAK\ncase 69:\n/* rule 69 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(pattern,preproc) ); }\n\tYY_BREAK\ncase 70:\nYY_RULE_SETUP\n{ preproc_macroexpand(); }\n\tYY_BREAK\ncase 71:\nYY_RULE_SETUP\n{ BEGIN((withsection==1) ? INITIAL:sem); withsection=0; sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 72:\nYY_RULE_SETUP\n{ BEGIN(INITIAL); return OP_UNIMPL; }\n\tYY_BREAK\ncase 73:\nYY_RULE_SETUP\n{ return GLOBALSET_KEY; }\n\tYY_BREAK\ncase 74:\nYY_RULE_SETUP\n{ return OP_RIGHT; }\n\tYY_BREAK\ncase 75:\nYY_RULE_SETUP\n{ return OP_LEFT; }\n\tYY_BREAK\ncase 76:\nYY_RULE_SETUP\n{ return OP_NOTEQUAL; }\n\tYY_BREAK\ncase 77:\nYY_RULE_SETUP\n{ return OP_LESSEQUAL; }\n\tYY_BREAK\ncase 78:\nYY_RULE_SETUP\n{ return OP_GREATEQUAL; }\n\tYY_BREAK\ncase 79:\nYY_RULE_SETUP\n{ return OP_AND; }\n\tYY_BREAK\ncase 80:\nYY_RULE_SETUP\n{ return OP_OR; }\n\tYY_BREAK\ncase 81:\nYY_RULE_SETUP\n{ return OP_XOR; }\n\tYY_BREAK\ncase 82:\nYY_RULE_SETUP\n{ return ELLIPSIS_KEY; }\n\tYY_BREAK\ncase 83:\nYY_RULE_SETUP\n{ actionon = 1; sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 84:\nYY_RULE_SETUP\n{ actionon = 0; sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 85:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return (actionon==0) ? sleightext[0] : OP_AND; }\n\tYY_BREAK\ncase 86:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return (actionon==0) ? sleightext[0] : OP_OR; }\n\tYY_BREAK\ncase 87:\nYY_RULE_SETUP\n{ return OP_XOR; }\n\tYY_BREAK\ncase 88:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 89:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 90:\nYY_RULE_SETUP\n{ return find_symbol(); }\n\tYY_BREAK\ncase 91:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,true); }\n\tYY_BREAK\ncase 92:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,true); }\n\tYY_BREAK\ncase 93:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,true); }\n\tYY_BREAK\ncase 94:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 95:\n/* rule 95 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); }\n\tYY_BREAK\ncase 96:\nYY_RULE_SETUP\n{ return sleightext[0]; }\n\tYY_BREAK\ncase 97:\n/* rule 97 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(sem,preproc) ); }\n\tYY_BREAK\ncase 98:\nYY_RULE_SETUP\n{ preproc_macroexpand(); }\n\tYY_BREAK\ncase 99:\nYY_RULE_SETUP\n{ BEGIN(INITIAL); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 100:\nYY_RULE_SETUP\n{ return OP_BOOL_OR; }\n\tYY_BREAK\ncase 101:\nYY_RULE_SETUP\n{ return OP_BOOL_AND; }\n\tYY_BREAK\ncase 102:\nYY_RULE_SETUP\n{ return OP_BOOL_XOR; }\n\tYY_BREAK\ncase 103:\nYY_RULE_SETUP\n{ return OP_RIGHT; }\n\tYY_BREAK\ncase 104:\nYY_RULE_SETUP\n{ return OP_LEFT; }\n\tYY_BREAK\ncase 105:\nYY_RULE_SETUP\n{ return OP_EQUAL; }\n\tYY_BREAK\ncase 106:\nYY_RULE_SETUP\n{ return OP_NOTEQUAL; }\n\tYY_BREAK\ncase 107:\nYY_RULE_SETUP\n{ return OP_LESSEQUAL; }\n\tYY_BREAK\ncase 108:\nYY_RULE_SETUP\n{ return OP_GREATEQUAL; }\n\tYY_BREAK\ncase 109:\nYY_RULE_SETUP\n{ return OP_SDIV; }\n\tYY_BREAK\ncase 110:\nYY_RULE_SETUP\n{ return OP_SREM; }\n\tYY_BREAK\ncase 111:\nYY_RULE_SETUP\n{ return OP_SRIGHT; }\n\tYY_BREAK\ncase 112:\nYY_RULE_SETUP\n{ return OP_SLESS; }\n\tYY_BREAK\ncase 113:\nYY_RULE_SETUP\n{ return OP_SGREAT; }\n\tYY_BREAK\ncase 114:\nYY_RULE_SETUP\n{ return OP_SLESSEQUAL; }\n\tYY_BREAK\ncase 115:\nYY_RULE_SETUP\n{ return OP_SGREATEQUAL; }\n\tYY_BREAK\ncase 116:\nYY_RULE_SETUP\n{ return OP_FADD; }\n\tYY_BREAK\ncase 117:\nYY_RULE_SETUP\n{ return OP_FSUB; }\n\tYY_BREAK\ncase 118:\nYY_RULE_SETUP\n{ return OP_FMULT; }\n\tYY_BREAK\ncase 119:\nYY_RULE_SETUP\n{ return OP_FDIV; }\n\tYY_BREAK\ncase 120:\nYY_RULE_SETUP\n{ return OP_FEQUAL; }\n\tYY_BREAK\ncase 121:\nYY_RULE_SETUP\n{ return OP_FNOTEQUAL; }\n\tYY_BREAK\ncase 122:\nYY_RULE_SETUP\n{ return OP_FLESS; }\n\tYY_BREAK\ncase 123:\nYY_RULE_SETUP\n{ return OP_FGREAT; }\n\tYY_BREAK\ncase 124:\nYY_RULE_SETUP\n{ return OP_FLESSEQUAL; }\n\tYY_BREAK\ncase 125:\nYY_RULE_SETUP\n{ return OP_FGREATEQUAL; }\n\tYY_BREAK\ncase 126:\nYY_RULE_SETUP\n{ return OP_ZEXT; }\n\tYY_BREAK\ncase 127:\nYY_RULE_SETUP\n{ return OP_CARRY; }\n\tYY_BREAK\ncase 128:\nYY_RULE_SETUP\n{ return OP_BORROW; }\n\tYY_BREAK\ncase 129:\nYY_RULE_SETUP\n{ return OP_SEXT; }\n\tYY_BREAK\ncase 130:\nYY_RULE_SETUP\n{ return OP_SCARRY; }\n\tYY_BREAK\ncase 131:\nYY_RULE_SETUP\n{ return OP_SBORROW; }\n\tYY_BREAK\ncase 132:\nYY_RULE_SETUP\n{ return OP_NAN; }\n\tYY_BREAK\ncase 133:\nYY_RULE_SETUP\n{ return OP_ABS; }\n\tYY_BREAK\ncase 134:\nYY_RULE_SETUP\n{ return OP_SQRT; }\n\tYY_BREAK\ncase 135:\nYY_RULE_SETUP\n{ return OP_CEIL; }\n\tYY_BREAK\ncase 136:\nYY_RULE_SETUP\n{ return OP_FLOOR; }\n\tYY_BREAK\ncase 137:\nYY_RULE_SETUP\n{ return OP_ROUND; }\n\tYY_BREAK\ncase 138:\nYY_RULE_SETUP\n{ return OP_INT2FLOAT; }\n\tYY_BREAK\ncase 139:\nYY_RULE_SETUP\n{ return OP_FLOAT2FLOAT; }\n\tYY_BREAK\ncase 140:\nYY_RULE_SETUP\n{ return OP_TRUNC; }\n\tYY_BREAK\ncase 141:\nYY_RULE_SETUP\n{ return OP_CPOOLREF; }\n\tYY_BREAK\ncase 142:\nYY_RULE_SETUP\n{ return OP_NEW; }\n\tYY_BREAK\ncase 143:\nYY_RULE_SETUP\n{ return OP_POPCOUNT; }\n\tYY_BREAK\ncase 144:\nYY_RULE_SETUP\n{ return OP_LZCOUNT; }\n\tYY_BREAK\ncase 145:\nYY_RULE_SETUP\n{ return IF_KEY; }\n\tYY_BREAK\ncase 146:\nYY_RULE_SETUP\n{ return GOTO_KEY; }\n\tYY_BREAK\ncase 147:\nYY_RULE_SETUP\n{ return CALL_KEY; }\n\tYY_BREAK\ncase 148:\nYY_RULE_SETUP\n{ return RETURN_KEY; }\n\tYY_BREAK\ncase 149:\nYY_RULE_SETUP\n{ return DELAYSLOT_KEY; }\n\tYY_BREAK\ncase 150:\nYY_RULE_SETUP\n{ return CROSSBUILD_KEY; }\n\tYY_BREAK\ncase 151:\nYY_RULE_SETUP\n{ return EXPORT_KEY; }\n\tYY_BREAK\ncase 152:\nYY_RULE_SETUP\n{ return BUILD_KEY; }\n\tYY_BREAK\ncase 153:\nYY_RULE_SETUP\n{ return LOCAL_KEY; }\n\tYY_BREAK\ncase 154:\nYY_RULE_SETUP\n{ sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\tYY_BREAK\ncase 155:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 156:\nYY_RULE_SETUP\n{ return find_symbol(); }\n\tYY_BREAK\ncase 157:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,false); }\n\tYY_BREAK\ncase 158:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,false); }\n\tYY_BREAK\ncase 159:\nYY_RULE_SETUP\n{ return scan_number(sleightext,&sleighlval,false); }\n\tYY_BREAK\ncase 160:\nYY_RULE_SETUP\n\n\tYY_BREAK\ncase 161:\n/* rule 161 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); }\n\tYY_BREAK\ncase 162:\nYY_RULE_SETUP\n{ return sleightext[0]; }\n\tYY_BREAK\ncase 163:\n/* rule 163 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); BEGIN( preprocess(preproc,preproc) ); }\n\tYY_BREAK\ncase 164:\n/* rule 164 can match eol */\nYY_RULE_SETUP\n{ slgh->nextLine(); }\n\tYY_BREAK\ncase YY_STATE_EOF(INITIAL):\ncase YY_STATE_EOF(defblock):\ncase YY_STATE_EOF(macroblock):\ncase YY_STATE_EOF(print):\ncase YY_STATE_EOF(pattern):\ncase YY_STATE_EOF(sem):\ncase YY_STATE_EOF(preproc):\n{ sleigh_delete_buffer( YY_CURRENT_BUFFER );\n if (filebuffers.empty())\n yyterminate(); \n sleigh_switch_to_buffer( filebuffers.back().lastbuffer );\n\t FILE *curfile = filebuffers.back().file;\n\t if (curfile != (FILE *)0)\n\t fclose(curfile);\n filebuffers.pop_back();\n slgh->parseFileFinished();\n }\n\tYY_BREAK\ncase 165:\nYY_RULE_SETUP\nECHO;\n\tYY_BREAK\n\n\tcase YY_END_OF_BUFFER:\n\t\t{\n\t\t/* Amount of text matched not including the EOB char. */\n\t\tint yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;\n\n\t\t/* Undo the effects of YY_DO_BEFORE_ACTION. */\n\t\t*yy_cp = (yy_hold_char);\n\t\tYY_RESTORE_YY_MORE_OFFSET\n\n\t\tif ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )\n\t\t\t{\n\t\t\t/* We're scanning a new file or input source. It's\n\t\t\t * possible that this happened because the user\n\t\t\t * just pointed yyin at a new source and called\n\t\t\t * yylex(). If so, then we have to assure\n\t\t\t * consistency between YY_CURRENT_BUFFER and our\n\t\t\t * globals. Here is the right place to do so, because\n\t\t\t * this is the first action (other than possibly a\n\t\t\t * back-up) that will match for the new input source.\n\t\t\t */\n\t\t\t(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;\n\t\t\t}\n\n\t\t/* Note that here we test for yy_c_buf_p \"<=\" to the position\n\t\t * of the first EOB in the buffer, since yy_c_buf_p will\n\t\t * already have been incremented past the NUL character\n\t\t * (since all states make transitions on EOB to the\n\t\t * end-of-buffer state). Contrast this with the test\n\t\t * in input().\n\t\t */\n\t\tif ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )\n\t\t\t{ /* This was really a NUL. */\n\t\t\tyy_state_type yy_next_state;\n\n\t\t\t(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;\n\n\t\t\tyy_current_state = yy_get_previous_state( );\n\n\t\t\t/* Okay, we're now positioned to make the NUL\n\t\t\t * transition. We couldn't have\n\t\t\t * yy_get_previous_state() go ahead and do it\n\t\t\t * for us because it doesn't know how to deal\n\t\t\t * with the possibility of jamming (and we don't\n\t\t\t * want to build jamming into it because then it\n\t\t\t * will run more slowly).\n\t\t\t */\n\n\t\t\tyy_next_state = yy_try_NUL_trans( yy_current_state );\n\n\t\t\tyy_bp = (yytext_ptr) + YY_MORE_ADJ;\n\n\t\t\tif ( yy_next_state )\n\t\t\t\t{\n\t\t\t\t/* Consume the NUL. */\n\t\t\t\tyy_cp = ++(yy_c_buf_p);\n\t\t\t\tyy_current_state = yy_next_state;\n\t\t\t\tgoto yy_match;\n\t\t\t\t}\n\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tyy_cp = (yy_c_buf_p);\n\t\t\t\tgoto yy_find_action;\n\t\t\t\t}\n\t\t\t}\n\n\t\telse switch ( yy_get_next_buffer( ) )\n\t\t\t{\n\t\t\tcase EOB_ACT_END_OF_FILE:\n\t\t\t\t{\n\t\t\t\t(yy_did_buffer_switch_on_eof) = 0;\n\n\t\t\t\tif ( yywrap( ) )\n\t\t\t\t\t{\n\t\t\t\t\t/* Note: because we've taken care in\n\t\t\t\t\t * yy_get_next_buffer() to have set up\n\t\t\t\t\t * yytext, we can now set up\n\t\t\t\t\t * yy_c_buf_p so that if some total\n\t\t\t\t\t * hoser (like flex itself) wants to\n\t\t\t\t\t * call the scanner after we return the\n\t\t\t\t\t * YY_NULL, it'll still work - another\n\t\t\t\t\t * YY_NULL will get returned.\n\t\t\t\t\t */\n\t\t\t\t\t(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;\n\n\t\t\t\t\tyy_act = YY_STATE_EOF(YY_START);\n\t\t\t\t\tgoto do_action;\n\t\t\t\t\t}\n\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tif ( ! (yy_did_buffer_switch_on_eof) )\n\t\t\t\t\t\tYY_NEW_FILE;\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\tcase EOB_ACT_CONTINUE_SCAN:\n\t\t\t\t(yy_c_buf_p) =\n\t\t\t\t\t(yytext_ptr) + yy_amount_of_matched_text;\n\n\t\t\t\tyy_current_state = yy_get_previous_state( );\n\n\t\t\t\tyy_cp = (yy_c_buf_p);\n\t\t\t\tyy_bp = (yytext_ptr) + YY_MORE_ADJ;\n\t\t\t\tgoto yy_match;\n\n\t\t\tcase EOB_ACT_LAST_MATCH:\n\t\t\t\t(yy_c_buf_p) =\n\t\t\t\t&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];\n\n\t\t\t\tyy_current_state = yy_get_previous_state( );\n\n\t\t\t\tyy_cp = (yy_c_buf_p);\n\t\t\t\tyy_bp = (yytext_ptr) + YY_MORE_ADJ;\n\t\t\t\tgoto yy_find_action;\n\t\t\t}\n\t\tbreak;\n\t\t}\n\n\tdefault:\n\t\tYY_FATAL_ERROR(\n\t\t\t\"fatal flex scanner internal error--no action found\" );\n\t} /* end of action switch */\n\t\t} /* end of scanning one token */\n\t} /* end of user's declarations */\n} /* end of yylex */\n\n/* yy_get_next_buffer - try to read in a new buffer\n *\n * Returns a code representing an action:\n *\tEOB_ACT_LAST_MATCH -\n *\tEOB_ACT_CONTINUE_SCAN - continue scanning from current position\n *\tEOB_ACT_END_OF_FILE - end of file\n */\nstatic int yy_get_next_buffer (void)\n{\n \tchar *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;\n\tchar *source = (yytext_ptr);\n\tint number_to_move, i;\n\tint ret_val;\n\n\tif ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )\n\t\tYY_FATAL_ERROR(\n\t\t\"fatal flex scanner internal error--end of buffer missed\" );\n\n\tif ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )\n\t\t{ /* Don't try to fill the buffer, so this is an EOF. */\n\t\tif ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )\n\t\t\t{\n\t\t\t/* We matched a single character, the EOB, so\n\t\t\t * treat this as a final EOF.\n\t\t\t */\n\t\t\treturn EOB_ACT_END_OF_FILE;\n\t\t\t}\n\n\t\telse\n\t\t\t{\n\t\t\t/* We matched some text prior to the EOB, first\n\t\t\t * process it.\n\t\t\t */\n\t\t\treturn EOB_ACT_LAST_MATCH;\n\t\t\t}\n\t\t}\n\n\t/* Try to read more data. */\n\n\t/* First move last chars to start of buffer. */\n\tnumber_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1);\n\n\tfor ( i = 0; i < number_to_move; ++i )\n\t\t*(dest++) = *(source++);\n\n\tif ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )\n\t\t/* don't do the read, it's not guaranteed to return an EOF,\n\t\t * just force an EOF\n\t\t */\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;\n\n\telse\n\t\t{\n\t\t\tint num_to_read =\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;\n\n\t\twhile ( num_to_read <= 0 )\n\t\t\t{ /* Not enough room in the buffer - grow it. */\n\n\t\t\t/* just a shorter name for the current buffer */\n\t\t\tYY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE;\n\n\t\t\tint yy_c_buf_p_offset =\n\t\t\t\t(int) ((yy_c_buf_p) - b->yy_ch_buf);\n\n\t\t\tif ( b->yy_is_our_buffer )\n\t\t\t\t{\n\t\t\t\tint new_size = b->yy_buf_size * 2;\n\n\t\t\t\tif ( new_size <= 0 )\n\t\t\t\t\tb->yy_buf_size += b->yy_buf_size / 8;\n\t\t\t\telse\n\t\t\t\t\tb->yy_buf_size *= 2;\n\n\t\t\t\tb->yy_ch_buf = (char *)\n\t\t\t\t\t/* Include room in for 2 EOB chars. */\n\t\t\t\t\tyyrealloc( (void *) b->yy_ch_buf,\n\t\t\t\t\t\t\t (yy_size_t) (b->yy_buf_size + 2) );\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t/* Can't grow it, we don't own it. */\n\t\t\t\tb->yy_ch_buf = NULL;\n\n\t\t\tif ( ! b->yy_ch_buf )\n\t\t\t\tYY_FATAL_ERROR(\n\t\t\t\t\"fatal error - scanner input buffer overflow\" );\n\n\t\t\t(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];\n\n\t\t\tnum_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -\n\t\t\t\t\t\tnumber_to_move - 1;\n\n\t\t\t}\n\n\t\tif ( num_to_read > YY_READ_BUF_SIZE )\n\t\t\tnum_to_read = YY_READ_BUF_SIZE;\n\n\t\t/* Read in more data. */\n\t\tYY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),\n\t\t\t(yy_n_chars), num_to_read );\n\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);\n\t\t}\n\n\tif ( (yy_n_chars) == 0 )\n\t\t{\n\t\tif ( number_to_move == YY_MORE_ADJ )\n\t\t\t{\n\t\t\tret_val = EOB_ACT_END_OF_FILE;\n\t\t\tyyrestart( yyin );\n\t\t\t}\n\n\t\telse\n\t\t\t{\n\t\t\tret_val = EOB_ACT_LAST_MATCH;\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buffer_status =\n\t\t\t\tYY_BUFFER_EOF_PENDING;\n\t\t\t}\n\t\t}\n\n\telse\n\t\tret_val = EOB_ACT_CONTINUE_SCAN;\n\n\tif (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {\n\t\t/* Extend the array by 50%, plus the number we really need. */\n\t\tint new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc(\n\t\t\t(void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size );\n\t\tif ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )\n\t\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_get_next_buffer()\" );\n\t\t/* \"- 2\" to take care of EOB's */\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2);\n\t}\n\n\t(yy_n_chars) += number_to_move;\n\tYY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;\n\tYY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;\n\n\t(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];\n\n\treturn ret_val;\n}\n\n/* yy_get_previous_state - get the state just before the EOB char was reached */\n\n static yy_state_type yy_get_previous_state (void)\n{\n\tyy_state_type yy_current_state;\n\tchar *yy_cp;\n \n\tyy_current_state = (yy_start);\n\tyy_current_state += YY_AT_BOL();\n\n\tfor ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )\n\t\t{\n\t\tYY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);\n\t\tif ( yy_accept[yy_current_state] )\n\t\t\t{\n\t\t\t(yy_last_accepting_state) = yy_current_state;\n\t\t\t(yy_last_accepting_cpos) = yy_cp;\n\t\t\t}\n\t\twhile ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )\n\t\t\t{\n\t\t\tyy_current_state = (int) yy_def[yy_current_state];\n\t\t\tif ( yy_current_state >= 533 )\n\t\t\t\tyy_c = yy_meta[yy_c];\n\t\t\t}\n\t\tyy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c];\n\t\t}\n\n\treturn yy_current_state;\n}\n\n/* yy_try_NUL_trans - try to make a transition on the NUL character\n *\n * synopsis\n *\tnext_state = yy_try_NUL_trans( current_state );\n */\n static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )\n{\n\tint yy_is_jam;\n \tchar *yy_cp = (yy_c_buf_p);\n\n\tYY_CHAR yy_c = 1;\n\tif ( yy_accept[yy_current_state] )\n\t\t{\n\t\t(yy_last_accepting_state) = yy_current_state;\n\t\t(yy_last_accepting_cpos) = yy_cp;\n\t\t}\n\twhile ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )\n\t\t{\n\t\tyy_current_state = (int) yy_def[yy_current_state];\n\t\tif ( yy_current_state >= 533 )\n\t\t\tyy_c = yy_meta[yy_c];\n\t\t}\n\tyy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c];\n\tyy_is_jam = (yy_current_state == 532);\n\n\t\treturn yy_is_jam ? 0 : yy_current_state;\n}\n\n#ifndef YY_NO_UNPUT\n\n static void yyunput (int c, char * yy_bp )\n{\n\tchar *yy_cp;\n \n yy_cp = (yy_c_buf_p);\n\n\t/* undo effects of setting up yytext */\n\t*yy_cp = (yy_hold_char);\n\n\tif ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )\n\t\t{ /* need to shift things up to make room */\n\t\t/* +2 for EOB chars. */\n\t\tint number_to_move = (yy_n_chars) + 2;\n\t\tchar *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[\n\t\t\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];\n\t\tchar *source =\n\t\t\t\t&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];\n\n\t\twhile ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )\n\t\t\t*--dest = *--source;\n\n\t\tyy_cp += (int) (dest - source);\n\t\tyy_bp += (int) (dest - source);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars =\n\t\t\t(yy_n_chars) = (int) YY_CURRENT_BUFFER_LVALUE->yy_buf_size;\n\n\t\tif ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )\n\t\t\tYY_FATAL_ERROR( \"flex scanner push-back overflow\" );\n\t\t}\n\n\t*--yy_cp = (char) c;\n\n\t(yytext_ptr) = yy_bp;\n\t(yy_hold_char) = *yy_cp;\n\t(yy_c_buf_p) = yy_cp;\n}\n\n#endif\n\n#ifndef YY_NO_INPUT\n#ifdef __cplusplus\n static int yyinput (void)\n#else\n static int input (void)\n#endif\n\n{\n\tint c;\n \n\t*(yy_c_buf_p) = (yy_hold_char);\n\n\tif ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )\n\t\t{\n\t\t/* yy_c_buf_p now points to the character we want to return.\n\t\t * If this occurs *before* the EOB characters, then it's a\n\t\t * valid NUL; if not, then we've hit the end of the buffer.\n\t\t */\n\t\tif ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )\n\t\t\t/* This was really a NUL. */\n\t\t\t*(yy_c_buf_p) = '\\0';\n\n\t\telse\n\t\t\t{ /* need more input */\n\t\t\tint offset = (int) ((yy_c_buf_p) - (yytext_ptr));\n\t\t\t++(yy_c_buf_p);\n\n\t\t\tswitch ( yy_get_next_buffer( ) )\n\t\t\t\t{\n\t\t\t\tcase EOB_ACT_LAST_MATCH:\n\t\t\t\t\t/* This happens because yy_g_n_b()\n\t\t\t\t\t * sees that we've accumulated a\n\t\t\t\t\t * token and flags that we need to\n\t\t\t\t\t * try matching the token before\n\t\t\t\t\t * proceeding. But for input(),\n\t\t\t\t\t * there's no matching to consider.\n\t\t\t\t\t * So convert the EOB_ACT_LAST_MATCH\n\t\t\t\t\t * to EOB_ACT_END_OF_FILE.\n\t\t\t\t\t */\n\n\t\t\t\t\t/* Reset buffer status. */\n\t\t\t\t\tyyrestart( yyin );\n\n\t\t\t\t\t/*FALLTHROUGH*/\n\n\t\t\t\tcase EOB_ACT_END_OF_FILE:\n\t\t\t\t\t{\n\t\t\t\t\tif ( yywrap( ) )\n\t\t\t\t\t\treturn 0;\n\n\t\t\t\t\tif ( ! (yy_did_buffer_switch_on_eof) )\n\t\t\t\t\t\tYY_NEW_FILE;\n#ifdef __cplusplus\n\t\t\t\t\treturn yyinput();\n#else\n\t\t\t\t\treturn input();\n#endif\n\t\t\t\t\t}\n\n\t\t\t\tcase EOB_ACT_CONTINUE_SCAN:\n\t\t\t\t\t(yy_c_buf_p) = (yytext_ptr) + offset;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\tc = *(unsigned char *) (yy_c_buf_p);\t/* cast for 8-bit char's */\n\t*(yy_c_buf_p) = '\\0';\t/* preserve yytext */\n\t(yy_hold_char) = *++(yy_c_buf_p);\n\n\tYY_CURRENT_BUFFER_LVALUE->yy_at_bol = (c == '\\n');\n\n\treturn c;\n}\n#endif\t/* ifndef YY_NO_INPUT */\n\n/** Immediately switch to a different input stream.\n * @param input_file A readable stream.\n * \n * @note This function does not reset the start condition to @c INITIAL .\n */\n void yyrestart (FILE * input_file )\n{\n \n\tif ( ! YY_CURRENT_BUFFER ){\n yyensure_buffer_stack ();\n\t\tYY_CURRENT_BUFFER_LVALUE =\n yy_create_buffer( yyin, YY_BUF_SIZE );\n\t}\n\n\tyy_init_buffer( YY_CURRENT_BUFFER, input_file );\n\tyy_load_buffer_state( );\n}\n\n/** Switch to a different input buffer.\n * @param new_buffer The new input buffer.\n * \n */\n void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer )\n{\n \n\t/* TODO. We should be able to replace this entire function body\n\t * with\n\t *\t\tyypop_buffer_state();\n\t *\t\tyypush_buffer_state(new_buffer);\n */\n\tyyensure_buffer_stack ();\n\tif ( YY_CURRENT_BUFFER == new_buffer )\n\t\treturn;\n\n\tif ( YY_CURRENT_BUFFER )\n\t\t{\n\t\t/* Flush out information for old buffer. */\n\t\t*(yy_c_buf_p) = (yy_hold_char);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);\n\t\t}\n\n\tYY_CURRENT_BUFFER_LVALUE = new_buffer;\n\tyy_load_buffer_state( );\n\n\t/* We don't actually know whether we did this switch during\n\t * EOF (yywrap()) processing, but the only time this flag\n\t * is looked at is after yywrap() is called, so it's safe\n\t * to go ahead and always set it.\n\t */\n\t(yy_did_buffer_switch_on_eof) = 1;\n}\n\nstatic void yy_load_buffer_state (void)\n{\n \t(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;\n\t(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;\n\tyyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;\n\t(yy_hold_char) = *(yy_c_buf_p);\n}\n\n/** Allocate and initialize an input buffer state.\n * @param file A readable stream.\n * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.\n * \n * @return the allocated buffer state.\n */\n YY_BUFFER_STATE yy_create_buffer (FILE * file, int size )\n{\n\tYY_BUFFER_STATE b;\n \n\tb = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) );\n\tif ( ! b )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_create_buffer()\" );\n\n\tb->yy_buf_size = size;\n\n\t/* yy_ch_buf has to be 2 characters longer than the size given because\n\t * we need to put in 2 end-of-buffer characters.\n\t */\n\tb->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) );\n\tif ( ! b->yy_ch_buf )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_create_buffer()\" );\n\n\tb->yy_is_our_buffer = 1;\n\n\tyy_init_buffer( b, file );\n\n\treturn b;\n}\n\n/** Destroy the buffer.\n * @param b a buffer created with yy_create_buffer()\n * \n */\n void yy_delete_buffer (YY_BUFFER_STATE b )\n{\n \n\tif ( ! b )\n\t\treturn;\n\n\tif ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */\n\t\tYY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;\n\n\tif ( b->yy_is_our_buffer )\n\t\tyyfree( (void *) b->yy_ch_buf );\n\n\tyyfree( (void *) b );\n}\n\n/* Initializes or reinitializes a buffer.\n * This function is sometimes called more than once on the same buffer,\n * such as during a yyrestart() or at EOF.\n */\n static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file )\n\n{\n\tint oerrno = errno;\n \n\tyy_flush_buffer( b );\n\n\tb->yy_input_file = file;\n\tb->yy_fill_buffer = 1;\n\n /* If b is the current buffer, then yy_init_buffer was _probably_\n * called from yyrestart() or through yy_get_next_buffer.\n * In that case, we don't want to reset the lineno or column.\n */\n if (b != YY_CURRENT_BUFFER){\n b->yy_bs_lineno = 1;\n b->yy_bs_column = 0;\n }\n\n b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;\n \n\terrno = oerrno;\n}\n\n/** Discard all buffered characters. On the next scan, YY_INPUT will be called.\n * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.\n * \n */\n void yy_flush_buffer (YY_BUFFER_STATE b )\n{\n \tif ( ! b )\n\t\treturn;\n\n\tb->yy_n_chars = 0;\n\n\t/* We always need two end-of-buffer characters. The first causes\n\t * a transition to the end-of-buffer state. The second causes\n\t * a jam in that state.\n\t */\n\tb->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;\n\tb->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;\n\n\tb->yy_buf_pos = &b->yy_ch_buf[0];\n\n\tb->yy_at_bol = 1;\n\tb->yy_buffer_status = YY_BUFFER_NEW;\n\n\tif ( b == YY_CURRENT_BUFFER )\n\t\tyy_load_buffer_state( );\n}\n\n/** Pushes the new state onto the stack. The new state becomes\n * the current state. This function will allocate the stack\n * if necessary.\n * @param new_buffer The new state.\n * \n */\nvoid yypush_buffer_state (YY_BUFFER_STATE new_buffer )\n{\n \tif (new_buffer == NULL)\n\t\treturn;\n\n\tyyensure_buffer_stack();\n\n\t/* This block is copied from yy_switch_to_buffer. */\n\tif ( YY_CURRENT_BUFFER )\n\t\t{\n\t\t/* Flush out information for old buffer. */\n\t\t*(yy_c_buf_p) = (yy_hold_char);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);\n\t\t}\n\n\t/* Only push if top exists. Otherwise, replace top. */\n\tif (YY_CURRENT_BUFFER)\n\t\t(yy_buffer_stack_top)++;\n\tYY_CURRENT_BUFFER_LVALUE = new_buffer;\n\n\t/* copied from yy_switch_to_buffer. */\n\tyy_load_buffer_state( );\n\t(yy_did_buffer_switch_on_eof) = 1;\n}\n\n/** Removes and deletes the top of the stack, if present.\n * The next element becomes the new top.\n * \n */\nvoid yypop_buffer_state (void)\n{\n \tif (!YY_CURRENT_BUFFER)\n\t\treturn;\n\n\tyy_delete_buffer(YY_CURRENT_BUFFER );\n\tYY_CURRENT_BUFFER_LVALUE = NULL;\n\tif ((yy_buffer_stack_top) > 0)\n\t\t--(yy_buffer_stack_top);\n\n\tif (YY_CURRENT_BUFFER) {\n\t\tyy_load_buffer_state( );\n\t\t(yy_did_buffer_switch_on_eof) = 1;\n\t}\n}\n\n/* Allocates the stack if it does not exist.\n * Guarantees space for at least one push.\n */\nstatic void yyensure_buffer_stack (void)\n{\n\tyy_size_t num_to_alloc;\n \n\tif (!(yy_buffer_stack)) {\n\n\t\t/* First allocation is just for 2 elements, since we don't know if this\n\t\t * scanner will even need a stack. We use 2 instead of 1 to avoid an\n\t\t * immediate realloc on the next call.\n */\n num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */\n\t\t(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc\n\t\t\t\t\t\t\t\t(num_to_alloc * sizeof(struct yy_buffer_state*)\n\t\t\t\t\t\t\t\t);\n\t\tif ( ! (yy_buffer_stack) )\n\t\t\tYY_FATAL_ERROR( \"out of dynamic memory in yyensure_buffer_stack()\" );\n\n\t\tmemset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));\n\n\t\t(yy_buffer_stack_max) = num_to_alloc;\n\t\t(yy_buffer_stack_top) = 0;\n\t\treturn;\n\t}\n\n\tif ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){\n\n\t\t/* Increase the buffer to prepare for a possible push. */\n\t\tyy_size_t grow_size = 8 /* arbitrary grow size */;\n\n\t\tnum_to_alloc = (yy_buffer_stack_max) + grow_size;\n\t\t(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc\n\t\t\t\t\t\t\t\t((yy_buffer_stack),\n\t\t\t\t\t\t\t\tnum_to_alloc * sizeof(struct yy_buffer_state*)\n\t\t\t\t\t\t\t\t);\n\t\tif ( ! (yy_buffer_stack) )\n\t\t\tYY_FATAL_ERROR( \"out of dynamic memory in yyensure_buffer_stack()\" );\n\n\t\t/* zero only the new slots.*/\n\t\tmemset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));\n\t\t(yy_buffer_stack_max) = num_to_alloc;\n\t}\n}\n\n/** Setup the input buffer state to scan directly from a user-specified character buffer.\n * @param base the character buffer\n * @param size the size in bytes of the character buffer\n * \n * @return the newly allocated buffer state object.\n */\nYY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size )\n{\n\tYY_BUFFER_STATE b;\n \n\tif ( size < 2 ||\n\t base[size-2] != YY_END_OF_BUFFER_CHAR ||\n\t base[size-1] != YY_END_OF_BUFFER_CHAR )\n\t\t/* They forgot to leave room for the EOB's. */\n\t\treturn NULL;\n\n\tb = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) );\n\tif ( ! b )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_scan_buffer()\" );\n\n\tb->yy_buf_size = (int) (size - 2);\t/* \"- 2\" to take care of EOB's */\n\tb->yy_buf_pos = b->yy_ch_buf = base;\n\tb->yy_is_our_buffer = 0;\n\tb->yy_input_file = NULL;\n\tb->yy_n_chars = b->yy_buf_size;\n\tb->yy_is_interactive = 0;\n\tb->yy_at_bol = 1;\n\tb->yy_fill_buffer = 0;\n\tb->yy_buffer_status = YY_BUFFER_NEW;\n\n\tyy_switch_to_buffer( b );\n\n\treturn b;\n}\n\n/** Setup the input buffer state to scan a string. The next call to yylex() will\n * scan from a @e copy of @a str.\n * @param yystr a NUL-terminated string to scan\n * \n * @return the newly allocated buffer state object.\n * @note If you want to scan bytes that may contain NUL values, then use\n * yy_scan_bytes() instead.\n */\nYY_BUFFER_STATE yy_scan_string (const char * yystr )\n{\n \n\treturn yy_scan_bytes( yystr, (int) strlen(yystr) );\n}\n\n/** Setup the input buffer state to scan the given bytes. The next call to yylex() will\n * scan from a @e copy of @a bytes.\n * @param yybytes the byte buffer to scan\n * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes.\n * \n * @return the newly allocated buffer state object.\n */\nYY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len )\n{\n\tYY_BUFFER_STATE b;\n\tchar *buf;\n\tyy_size_t n;\n\tint i;\n \n\t/* Get memory for full buffer, including space for trailing EOB's. */\n\tn = (yy_size_t) (_yybytes_len + 2);\n\tbuf = (char *) yyalloc( n );\n\tif ( ! buf )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_scan_bytes()\" );\n\n\tfor ( i = 0; i < _yybytes_len; ++i )\n\t\tbuf[i] = yybytes[i];\n\n\tbuf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;\n\n\tb = yy_scan_buffer( buf, n );\n\tif ( ! b )\n\t\tYY_FATAL_ERROR( \"bad buffer in yy_scan_bytes()\" );\n\n\t/* It's okay to grow etc. this buffer, and we should throw it\n\t * away when we're done.\n\t */\n\tb->yy_is_our_buffer = 1;\n\n\treturn b;\n}\n\n#ifndef YY_EXIT_FAILURE\n#define YY_EXIT_FAILURE 2\n#endif\n\nstatic void yynoreturn yy_fatal_error (const char* msg )\n{\n\t\t\tfprintf( stderr, \"%s\\n\", msg );\n\texit( YY_EXIT_FAILURE );\n}\n\n/* Redefine yyless() so it works in section 3 code. */\n\n#undef yyless\n#define yyless(n) \\\n\tdo \\\n\t\t{ \\\n\t\t/* Undo effects of setting up yytext. */ \\\n int yyless_macro_arg = (n); \\\n YY_LESS_LINENO(yyless_macro_arg);\\\n\t\tyytext[yyleng] = (yy_hold_char); \\\n\t\t(yy_c_buf_p) = yytext + yyless_macro_arg; \\\n\t\t(yy_hold_char) = *(yy_c_buf_p); \\\n\t\t*(yy_c_buf_p) = '\\0'; \\\n\t\tyyleng = yyless_macro_arg; \\\n\t\t} \\\n\twhile ( 0 )\n\n/* Accessor methods (get/set functions) to struct members. */\n\n/** Get the current line number.\n * \n */\nint yyget_lineno (void)\n{\n \n return yylineno;\n}\n\n/** Get the input stream.\n * \n */\nFILE *yyget_in (void)\n{\n return yyin;\n}\n\n/** Get the output stream.\n * \n */\nFILE *yyget_out (void)\n{\n return yyout;\n}\n\n/** Get the length of the current token.\n * \n */\nint yyget_leng (void)\n{\n return yyleng;\n}\n\n/** Get the current token.\n * \n */\n\nchar *yyget_text (void)\n{\n return yytext;\n}\n\n/** Set the current line number.\n * @param _line_number line number\n * \n */\nvoid yyset_lineno (int _line_number )\n{\n \n yylineno = _line_number;\n}\n\n/** Set the input stream. This does not discard the current\n * input buffer.\n * @param _in_str A readable stream.\n * \n * @see yy_switch_to_buffer\n */\nvoid yyset_in (FILE * _in_str )\n{\n yyin = _in_str ;\n}\n\nvoid yyset_out (FILE * _out_str )\n{\n yyout = _out_str ;\n}\n\nint yyget_debug (void)\n{\n return yy_flex_debug;\n}\n\nvoid yyset_debug (int _bdebug )\n{\n yy_flex_debug = _bdebug ;\n}\n\nstatic int yy_init_globals (void)\n{\n /* Initialization is the same as for the non-reentrant scanner.\n * This function is called from yylex_destroy(), so don't allocate here.\n */\n\n (yy_buffer_stack) = NULL;\n (yy_buffer_stack_top) = 0;\n (yy_buffer_stack_max) = 0;\n (yy_c_buf_p) = NULL;\n (yy_init) = 0;\n (yy_start) = 0;\n\n/* Defined in main.c */\n#ifdef YY_STDINIT\n yyin = stdin;\n yyout = stdout;\n#else\n yyin = NULL;\n yyout = NULL;\n#endif\n\n /* For future reference: Set errno on error, since we are called by\n * yylex_init()\n */\n return 0;\n}\n\n/* yylex_destroy is for both reentrant and non-reentrant scanners. */\nint yylex_destroy (void)\n{\n \n /* Pop the buffer stack, destroying each element. */\n\twhile(YY_CURRENT_BUFFER){\n\t\tyy_delete_buffer( YY_CURRENT_BUFFER );\n\t\tYY_CURRENT_BUFFER_LVALUE = NULL;\n\t\tyypop_buffer_state();\n\t}\n\n\t/* Destroy the stack itself. */\n\tyyfree((yy_buffer_stack) );\n\t(yy_buffer_stack) = NULL;\n\n /* Reset the globals. This is important in a non-reentrant scanner so the next time\n * yylex() is called, initialization will occur. */\n yy_init_globals( );\n\n return 0;\n}\n\n/*\n * Internal utility routines.\n */\n\n#ifndef yytext_ptr\nstatic void yy_flex_strncpy (char* s1, const char * s2, int n )\n{\n\t\t\n\tint i;\n\tfor ( i = 0; i < n; ++i )\n\t\ts1[i] = s2[i];\n}\n#endif\n\n#ifdef YY_NEED_STRLEN\nstatic int yy_flex_strlen (const char * s )\n{\n\tint n;\n\tfor ( n = 0; s[n]; ++n )\n\t\t;\n\n\treturn n;\n}\n#endif\n\nvoid *yyalloc (yy_size_t size )\n{\n\t\t\treturn malloc(size);\n}\n\nvoid *yyrealloc (void * ptr, yy_size_t size )\n{\n\t\t\n\t/* The cast to (char *) in the following accommodates both\n\t * implementations that use char* generic pointers, and those\n\t * that use void* generic pointers. It works with the latter\n\t * because both ANSI C and C++ allow castless assignment from\n\t * any pointer type to void*, and deal with argument conversions\n\t * as though doing an assignment.\n\t */\n\treturn realloc(ptr, size);\n}\n\nvoid yyfree (void * ptr )\n{\n\t\t\tfree( (char *) ptr );\t/* see yyrealloc() for (char *) cast */\n}\n\n#define YYTABLES_NAME \"yytables\"\n\n" }, { "path": "pypcode/sleigh/slghscan.l", "content": "/* ###\n * IP: GHIDRA\n * NOTE: flex skeletons are NOT bound by flex's BSD license\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n%option prefix=\"sleigh\"\n%{\n#define sleighwrap() 1\n#define YY_SKIP_YYWRAP\n\n/* If we are building don't include unistd.h */\n/* flex provides us with this macro for turning it off */\n#ifdef _WIN32\n#define YY_NO_UNISTD_H\nstatic int isatty (int fildes) { return 0; }\n#endif\n\n#include \"slgh_compile.hh\"\n\nnamespace ghidra {\n\n#include \"slghparse.hh\"\n\nstruct FileStreamState {\n YY_BUFFER_STATE lastbuffer;\t// Last lex buffer corresponding to the stream\n FILE *file; // The NEW file stream\n};\n\nextern SleighCompile *slgh;\nint4 last_preproc; // lex state before last preprocessing erasure\nint4 actionon; // whether '&' '|' and '^' are treated as actionon in pattern section\nint4 withsection = 0; // whether we are between the 'with' keyword and its open brace '{'\nvector filebuffers;\nvector ifstack;\nint4 negative_if = -1;\n\nvoid preproc_error(const string &err)\n\n{\n slgh->reportError((const Location *)0, err);\n cerr << \"Terminating due to error in preprocessing\" << endl;\n exit(1);\n}\n\nvoid check_to_endofline(istream &s)\n\n{ // Make sure there is nothing to the end of the line\n s >> ws;\n if (!s.eof())\n if (s.peek() != '#')\n preproc_error(\"Extra characters in preprocessor directive\"); \n}\n\nstring read_identifier(istream &s)\n\n{ // Read a proper identifier from the stream\n s >> ws; // Skip any whitespace\n string res;\n while(!s.eof()) {\n char tok = s.peek();\n if (isalnum(tok) || (tok == '_')) {\n s >> tok;\n res += tok;\n }\n else\n break;\n }\n return res;\n}\n\nvoid preprocess_string(istream &s,string &res)\n\n{ // Grab string surrounded by double quotes from stream or call preprocess_error\n int4 val;\n \n s >> ws; // Skip any whitespace\n val = s.get();\n if (val != '\\\"')\n preproc_error(\"Expecting double quoted string\");\n val = s.get();\n while((val != '\\\"')&&(val>=0)) {\n res += (char)val;\n val = s.get();\n }\n if (val != '\\\"')\n preproc_error(\"Missing terminating double quote\");\n}\n\nextern int4 preprocess_if(istream &s); // Forward declaration for recursion\n\nint4 read_defined_operator(istream &s)\n\n{ // We have seen a -defined- keyword in an if or elif\n // Read macro name used as input, return 1 if it is defined\n char tok = ' ';\n string macroname;\n \n s >> ws >> tok;\n if (tok != '(')\n preproc_error(\"Badly formed \\\"defined\\\" operator\");\n macroname = read_identifier(s);\n int4 res = slgh->getPreprocValue(macroname,macroname) ? 1 : 0;\n s >> ws >> tok;\n if (tok != ')')\n preproc_error(\"Badly formed \\\"defined\\\" operator\");\n return res;\n}\n\nint4 read_boolean_clause(istream &s)\n\n{\t\t\t\t// We have seen an if or elif\n\t\t\t\t// return 1 if condition is true or else 0\n s >> ws;\n if (s.peek()=='(') {\t\t// Parenthetical expression spawns recursion\n int4 val = s.get();\n int4 res = preprocess_if(s);\n s >> ws;\n val = s.get();\n if (val != ')')\n preproc_error(\"Unbalanced parentheses\");\n return res;\n }\n\t\t\t\t// Otherwise we must have a normal comparison operator\n string lhs,rhs,comp;\n\n if (s.peek()=='\\\"')\t\t// Read left-hand side string\n preprocess_string(s,lhs);\n else {\n lhs = read_identifier(s);\n if (lhs == \"defined\")\n return read_defined_operator(s);\n if (!slgh->getPreprocValue(lhs,lhs))\n preproc_error(\"Could not find preprocessor macro \"+lhs);\n }\n\n char tok;\n s >> tok; // Read comparison symbol\n comp += tok;\n s >> tok;\n comp += tok;\n \n s >> ws;\n if (s.peek()=='\\\"') // Read right-hand side string\n preprocess_string(s,rhs);\n else {\n rhs = read_identifier(s);\n if (!slgh->getPreprocValue(rhs,rhs))\n preproc_error(\"Could not find preprocessor macro \"+rhs);\n }\n\n if (comp == \"==\")\n return (lhs == rhs) ? 1 : 0;\n else if (comp==\"!=\")\n return (lhs != rhs) ? 1 : 0;\n else\n preproc_error(\"Syntax error in condition\");\n return 0;\n}\n\nint4 preprocess_if(istream &s)\n\n{\n int4 res = read_boolean_clause(s);\n s >> ws;\n while((!s.eof())&&(s.peek()!=')')) {\n string boolop;\n char tok;\n s >> tok;\n boolop += tok;\n s >> tok;\n boolop += tok;\n int4 res2 = read_boolean_clause(s);\n if (boolop == \"&&\")\n res = res & res2;\n else if (boolop == \"||\")\n res = res | res2;\n else if (boolop == \"^^\")\n res = res ^ res2;\n else\n preproc_error(\"Syntax error in expression\");\n s >> ws;\n }\n return res;\n}\n\nvoid expand_preprocmacros(string &str)\n\n{\n string::size_type pos;\n string::size_type lastpos = 0;\n pos = str.find(\"$(\",lastpos);\n if (pos == string::npos)\n return;\n string res;\n for(;;) {\n if (pos == string::npos) {\n res += str.substr(lastpos);\n str = res;\n return;\n }\n else {\n res += str.substr(lastpos,(pos-lastpos));\n string::size_type endpos = str.find(')',pos+2);\n if (endpos == string::npos) {\n\tpreproc_error(\"Unterminated macro in string\");\n\tbreak;\n }\n string macro = str.substr(pos+2, endpos - (pos+2));\n string value;\n if (!slgh->getPreprocValue(macro,value)) {\n\tpreproc_error(\"Unknown preprocessing macro \"+macro);\n\tbreak;\n }\n res += value;\n lastpos = endpos + 1;\n }\n pos = str.find(\"$(\",lastpos);\n }\n}\n\nint4 preprocess(int4 cur_state,int4 blank_state)\n\n{\n string str(sleightext);\n string::size_type pos = str.find('#');\n if (pos != string::npos)\n str.erase(pos);\n istringstream s(str);\n string type;\n\n if (cur_state != blank_state)\n last_preproc = cur_state;\n\n s.get(); // Skip the preprocessor marker\n s >> type;\n if (type == \"include\") {\n if (negative_if == -1) { // Not in the middle of a false if clause\n filebuffers.push_back(FileStreamState()); // Save state of current file\n filebuffers.back().lastbuffer = YY_CURRENT_BUFFER;\n filebuffers.back().file = (FILE *)0;\n s >> ws;\n string fname;\n preprocess_string(s,fname);\n expand_preprocmacros(fname);\n slgh->parseFromNewFile(fname);\n fname = slgh->grabCurrentFilePath();\n sleighin = fopen(fname.c_str(),\"r\");\n if (sleighin == (FILE *)0)\n preproc_error(\"Could not open included file \"+fname);\n filebuffers.back().file = sleighin;\n sleigh_switch_to_buffer( sleigh_create_buffer(sleighin, YY_BUF_SIZE) );\n check_to_endofline(s);\n }\n }\n else if (type == \"define\") {\n if (negative_if == -1) {\n string varname;\n string value;\n varname = read_identifier(s); // Get name of variable being defined\n s >> ws;\n if (s.peek() == '\\\"')\n preprocess_string(s,value);\n else\n value = read_identifier(s);\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor definition\");\n slgh->setPreprocValue(varname,value);\n check_to_endofline(s);\n }\n }\n else if (type == \"undef\") {\n if (negative_if == -1) {\n string varname;\n varname = read_identifier(s);\t\t// Name of variable to undefine\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor undef\");\n slgh->undefinePreprocValue(varname);\n check_to_endofline(s);\n }\n }\n else if (type==\"ifdef\") {\n string varname;\n varname = read_identifier(s);\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor ifdef\");\n string value;\n int4 truth = (slgh->getPreprocValue(varname,value)) ? 1 : 0;\n ifstack.push_back(truth);\n check_to_endofline(s);\n }\n else if (type==\"ifndef\") {\n string varname;\n varname = read_identifier(s);\n if (varname.size()==0)\n preproc_error(\"Error in preprocessor ifndef\");\n string value;\n int4 truth = (slgh->getPreprocValue(varname,value)) ? 0 : 1;\t// flipped from ifdef\n ifstack.push_back(truth);\n check_to_endofline(s);\n }\n else if (type==\"if\") {\n int4 truth = preprocess_if(s);\n if (!s.eof())\n preproc_error(\"Unbalanced parentheses\");\n ifstack.push_back(truth);\n }\n else if (type==\"elif\") {\n if (ifstack.empty())\n preproc_error(\"elif without preceding if\");\n if ((ifstack.back()&2)!=0)\t\t// We have already seen an else clause\n preproc_error(\"elif follows else\");\n if ((ifstack.back()&4)!=0) // We have already seen a true elif clause\n ifstack.back() = 4; // don't include any other elif clause\n else if ((ifstack.back()&1)!=0) // Last clause was a true if\n ifstack.back() = 4; // don't include this elif\n else {\n int4 truth = preprocess_if(s);\n if (!s.eof())\n preproc_error(\"Unbalanced parentheses\");\n if (truth==0)\n ifstack.back() = 0;\n else\n ifstack.back() = 5;\n }\n }\n else if (type==\"endif\") {\n if (ifstack.empty())\n preproc_error(\"preprocessing endif without matching if\");\n ifstack.pop_back();\n check_to_endofline(s);\n }\n else if (type==\"else\") {\n if (ifstack.empty())\n preproc_error(\"preprocessing else without matching if\");\n if ((ifstack.back()&2)!=0)\n preproc_error(\"second else for one if\");\n if ((ifstack.back()&4)!=0) // Seen a true elif clause before\n ifstack.back() = 6;\n else if (ifstack.back()==0)\n ifstack.back() = 3;\n else\n ifstack.back() = 2;\n check_to_endofline(s);\n }\n else\n preproc_error(\"Unknown preprocessing directive: \"+type);\n\n if (negative_if >= 0) { // We were in a false state\n if (negative_if+1 < ifstack.size())\n return blank_state; // false state is still deep in stack\n else // false state is popped off or is current and changed\n negative_if = -1;\n }\n if (ifstack.empty()) return last_preproc;\n if ((ifstack.back()&1)==0) {\n negative_if = ifstack.size()-1;\n return blank_state;\n }\n return last_preproc;\n}\n\nvoid preproc_macroexpand(void)\n\n{\n filebuffers.push_back(FileStreamState());\n filebuffers.back().lastbuffer = YY_CURRENT_BUFFER;\n filebuffers.back().file = (FILE *)0;\n string macro(sleightext);\n macro.erase(0,2);\n macro.erase(macro.size()-1,1);\n string value;\n if (!slgh->getPreprocValue(macro,value))\n preproc_error(\"Unknown preprocessing macro \"+macro);\n sleigh_switch_to_buffer( sleigh_scan_string( value.c_str() ) );\n slgh->parsePreprocMacro();\n}\n\nint4 find_symbol(void) {\n string * newstring = new string(sleightext);\n SleighSymbol *sym = slgh->findSymbol(*newstring);\n if (sym == (SleighSymbol *)0) {\n sleighlval.str = newstring;\n return STRING;\n }\n delete newstring;\n switch(sym->getType()) {\n case SleighSymbol::section_symbol:\n sleighlval.sectionsym = (SectionSymbol *)sym;\n return SECTIONSYM;\n case SleighSymbol::space_symbol:\n sleighlval.spacesym = (SpaceSymbol *)sym;\n return SPACESYM;\n case SleighSymbol::token_symbol:\n sleighlval.tokensym = (TokenSymbol *)sym;\n return TOKENSYM;\n case SleighSymbol::userop_symbol:\n sleighlval.useropsym = (UserOpSymbol *)sym;\n return USEROPSYM;\n case SleighSymbol::value_symbol:\n sleighlval.valuesym = (ValueSymbol *)sym;\n return VALUESYM;\n case SleighSymbol::valuemap_symbol:\n sleighlval.valuemapsym = (ValueMapSymbol *)sym;\n return VALUEMAPSYM;\n case SleighSymbol::name_symbol:\n sleighlval.namesym = (NameSymbol *)sym;\n return NAMESYM;\n case SleighSymbol::varnode_symbol:\n sleighlval.varsym = (VarnodeSymbol *)sym;\n return VARSYM;\n case SleighSymbol::bitrange_symbol:\n sleighlval.bitsym = (BitrangeSymbol *)sym;\n return BITSYM;\n case SleighSymbol::varnodelist_symbol:\n sleighlval.varlistsym = (VarnodeListSymbol *)sym;\n return VARLISTSYM;\n case SleighSymbol::operand_symbol:\n sleighlval.operandsym = (OperandSymbol *)sym;\n return OPERANDSYM;\n case SleighSymbol::start_symbol:\n case SleighSymbol::end_symbol:\n case SleighSymbol::next2_symbol:\n case SleighSymbol::flowdest_symbol:\n case SleighSymbol::flowref_symbol:\n sleighlval.specsym = (SpecificSymbol *)sym;\n return JUMPSYM;\n case SleighSymbol::subtable_symbol:\n sleighlval.subtablesym = (SubtableSymbol *)sym;\n return SUBTABLESYM;\n case SleighSymbol::macro_symbol:\n sleighlval.macrosym = (MacroSymbol *)sym;\n return MACROSYM;\n case SleighSymbol::label_symbol:\n sleighlval.labelsym = (LabelSymbol *)sym;\n return LABELSYM;\n case SleighSymbol::epsilon_symbol:\n sleighlval.specsym = (SpecificSymbol *)sym;\n return SPECSYM;\n case SleighSymbol::context_symbol:\n sleighlval.contextsym = (ContextSymbol *)sym;\n return CONTEXTSYM;\n case SleighSymbol::dummy_symbol:\n break;\n }\n return -1; // Should never reach here\n}\n\nint4 scan_number(char *numtext,SLEIGHSTYPE *lval,bool signednum)\n\n{\n uintb val;\n if (numtext[0] == '0' && numtext[1] == 'b') {\n val = 0;\n numtext += 2;\n while ((*numtext) != 0) {\n val <<= 1;\n if (*numtext == '1') {\n val |= 1;\n }\n ++numtext;\n }\n } else {\n istringstream s(numtext);\n s.unsetf(ios::dec | ios::hex | ios::oct);\n s >> val;\n if (!s)\n return BADINTEGER;\n }\n if (signednum) {\n lval->big = new intb(val);\n return INTB;\n }\n lval->i = new uintb(val);\n return INTEGER;\n}\n\n} // End namespace ghidra\n\nusing namespace ghidra;\n\n%}\n\n%x defblock\n%x macroblock\n%x print\n%x pattern\n%x sem\n%x preproc\n%%\n\n^@[^\\n]*\\n? { slgh->nextLine(); BEGIN( preprocess(INITIAL,preproc) ); }\n\\$\\([a-zA-Z0-9_.][a-zA-Z0-9_.]*\\) { preproc_macroexpand(); }\n[(),\\-] { sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\: { BEGIN(print); slgh->calcContextLayout(); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\{ { BEGIN(sem); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n#.*\n[\\r\\ \\t\\v]+\n\\n { slgh->nextLine(); }\nmacro { BEGIN(macroblock); return MACRO_KEY; }\ndefine { BEGIN(defblock); return DEFINE_KEY; }\nattach { BEGIN(defblock); slgh->calcContextLayout(); return ATTACH_KEY; }\nwith { BEGIN(pattern); withsection = 1; slgh->calcContextLayout(); return WITH_KEY; }\n[a-zA-Z_.][a-zA-Z0-9_.]* { return find_symbol(); }\n. { return sleightext[0]; }\n\n^@[^\\n]*\\n? { slgh->nextLine(); BEGIN( preprocess(macroblock,preproc) ); }\n\\$\\([a-zA-Z0-9_.][a-zA-Z0-9_.]*\\) { preproc_macroexpand(); }\n[(),] { sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\{ { BEGIN(sem); return sleightext[0]; }\n[a-zA-Z_.][a-zA-Z0-9_.]* { sleighlval.str = new string(sleightext); return STRING; }\n[\\r\\ \\t\\v]+\n\\n { slgh->nextLine(); }\n. { return sleightext[0]; }\n\n^@[^\\n]*\\n? { slgh->nextLine(); BEGIN( preprocess(defblock,preproc) ); }\n\\$\\([a-zA-Z0-9_.][a-zA-Z0-9_.]*\\) { preproc_macroexpand(); }\n[(),=:\\[\\]] { sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\; { BEGIN(INITIAL); sleighlval.ch = sleightext[0]; return sleightext[0]; }\nspace { return SPACE_KEY; }\ntype { return TYPE_KEY; }\nram_space { return RAM_KEY; }\ndefault { return DEFAULT_KEY; }\nregister_space { return REGISTER_KEY; }\ntoken { return TOKEN_KEY; }\ncontext { return CONTEXT_KEY; }\nbitrange { return BITRANGE_KEY; }\nsigned { return SIGNED_KEY; }\nnoflow { return NOFLOW_KEY; }\nhex { return HEX_KEY; }\ndec { return DEC_KEY; }\nendian { return ENDIAN_KEY; }\nalignment { return ALIGN_KEY; }\nbig { return BIG_KEY; }\nlittle { return LITTLE_KEY; }\nsize { return SIZE_KEY; }\nwordsize { return WORDSIZE_KEY; }\noffset { return OFFSET_KEY; }\nnames { return NAMES_KEY; }\nvalues { return VALUES_KEY; }\nvariables { return VARIABLES_KEY; }\npcodeop { return PCODEOP_KEY; }\n#.*\n[a-zA-Z_.][a-zA-Z0-9_.]* { return find_symbol(); }\n[0-9]|[1-9][0-9]+\t{ return scan_number(sleightext,&sleighlval,false); }\n0x[0-9a-fA-F]+\t{ return scan_number(sleightext,&sleighlval,false); }\n0b[01]+\t\t{ return scan_number(sleightext,&sleighlval,false); }\n\\\"([^\\\"[:cntrl:]]|\\\"\\\")*\\\"\t{ sleighlval.str = new string(sleightext+1,strlen(sleightext)-2); return STRING; }\n[\\r\\ \\t\\v]+\n\\n { slgh->nextLine(); }\n. { return sleightext[0]; }\n\n\n^@[^\\n]*\\n? { slgh->nextLine(); BEGIN( preprocess(print,preproc) ); }\n\\$\\([a-zA-Z0-9_.][a-zA-Z0-9_.]*\\) { preproc_macroexpand(); }\n[~!@#$%&*()\\-=+\\[\\]{}|;:<>?,/0-9] { sleighlval.ch = sleightext[0]; return CHAR; }\n\\^ { sleighlval.ch = '^'; return '^'; }\nis { BEGIN(pattern); actionon=0; return IS_KEY; }\n[a-zA-Z_.][a-zA-Z0-9_.]* { sleighlval.str = new string(sleightext); return SYMBOLSTRING; }\n\\\"([^\\\"[:cntrl:]]|\\\"\\\")*\\\" { sleighlval.str = new string(sleightext+1,strlen(sleightext)-2); return STRING; }\n[\\r\\ \\t\\v]+ { sleighlval.ch = ' '; return ' '; }\n\\n { slgh->nextLine(); return ' '; }\n. { return sleightext[0]; }\n\n^@[^\\n]*\\n? { slgh->nextLine(); BEGIN( preprocess(pattern,preproc) ); }\n\\$\\([a-zA-Z0-9_.][a-zA-Z0-9_.]*\\) { preproc_macroexpand(); }\n\\{ { BEGIN((withsection==1) ? INITIAL:sem); withsection=0; sleighlval.ch = sleightext[0]; return sleightext[0]; }\nunimpl { BEGIN(INITIAL); return OP_UNIMPL; }\nglobalset { return GLOBALSET_KEY; }\n\\>\\> { return OP_RIGHT; }\n\\<\\< { return OP_LEFT; }\n\\!\\= { return OP_NOTEQUAL; }\n\\<\\= { return OP_LESSEQUAL; }\n\\>\\= { return OP_GREATEQUAL; }\n\\$and { return OP_AND; }\n\\$or { return OP_OR; }\n\\$xor { return OP_XOR; }\n\\.\\.\\. { return ELLIPSIS_KEY; }\n\\[ { actionon = 1; sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\] { actionon = 0; sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\& { sleighlval.ch = sleightext[0]; return (actionon==0) ? sleightext[0] : OP_AND; }\n\\| { sleighlval.ch = sleightext[0]; return (actionon==0) ? sleightext[0] : OP_OR; }\n\\^ { return OP_XOR; }\n[=(),:;+\\-*/~<>] { sleighlval.ch = sleightext[0]; return sleightext[0]; }\n#.*\n[a-zA-Z_.][a-zA-Z0-9_.]* { return find_symbol(); }\n[0-9]|[1-9][0-9]+ { return scan_number(sleightext,&sleighlval,true); }\n0x[0-9a-fA-F]+ { return scan_number(sleightext,&sleighlval,true); }\n0b[01]+ { return scan_number(sleightext,&sleighlval,true); }\n[\\r\\ \\t\\v]+\n\\n { slgh->nextLine(); }\n. { return sleightext[0]; }\n\n^@[^\\n]*\\n? { slgh->nextLine(); BEGIN( preprocess(sem,preproc) ); }\n\\$\\([a-zA-Z0-9_.][a-zA-Z0-9_.]*\\) { preproc_macroexpand(); }\n\\} { BEGIN(INITIAL); sleighlval.ch = sleightext[0]; return sleightext[0]; }\n\\|\\| { return OP_BOOL_OR; }\n\\&\\& { return OP_BOOL_AND; }\n\\^\\^ { return OP_BOOL_XOR; }\n\\>\\> { return OP_RIGHT; }\n\\<\\< { return OP_LEFT; }\n\\=\\= { return OP_EQUAL; }\n\\!\\= { return OP_NOTEQUAL; }\n\\<\\= { return OP_LESSEQUAL; }\n\\>\\= { return OP_GREATEQUAL; }\ns\\/ { return OP_SDIV; }\ns\\% { return OP_SREM; }\ns\\>\\> { return OP_SRIGHT; }\ns\\< { return OP_SLESS; }\ns\\> { return OP_SGREAT; }\ns\\<\\= { return OP_SLESSEQUAL; }\ns\\>\\= { return OP_SGREATEQUAL; }\nf\\+ { return OP_FADD; }\nf\\- { return OP_FSUB; }\nf\\* { return OP_FMULT; }\nf\\/ { return OP_FDIV; }\nf\\=\\= { return OP_FEQUAL; }\nf\\!\\= { return OP_FNOTEQUAL; }\nf\\< { return OP_FLESS; }\nf\\> { return OP_FGREAT; }\nf\\<\\= { return OP_FLESSEQUAL; }\nf\\>\\= { return OP_FGREATEQUAL; }\nzext { return OP_ZEXT; }\ncarry { return OP_CARRY; }\nborrow { return OP_BORROW; }\nsext { return OP_SEXT; }\nscarry { return OP_SCARRY; }\nsborrow { return OP_SBORROW; }\nnan { return OP_NAN; }\nabs { return OP_ABS; }\nsqrt { return OP_SQRT; }\nceil { return OP_CEIL; }\nfloor { return OP_FLOOR; }\nround { return OP_ROUND; }\nint2float { return OP_INT2FLOAT; }\nfloat2float { return OP_FLOAT2FLOAT; }\ntrunc { return OP_TRUNC; }\ncpool { return OP_CPOOLREF; }\nnewobject { return OP_NEW; }\npopcount { return OP_POPCOUNT; }\nlzcount { return OP_LZCOUNT; }\nif { return IF_KEY; }\ngoto { return GOTO_KEY; }\ncall { return CALL_KEY; }\nreturn { return RETURN_KEY; }\ndelayslot { return DELAYSLOT_KEY; }\ncrossbuild { return CROSSBUILD_KEY; }\nexport { return EXPORT_KEY; }\nbuild { return BUILD_KEY; }\nlocal { return LOCAL_KEY; }\n[=(),:\\[\\];!&|^+\\-*/%~<>] { sleighlval.ch = sleightext[0]; return sleightext[0]; }\n#.*\n[a-zA-Z_.][a-zA-Z0-9_.]* { return find_symbol(); }\n[0-9]|[1-9][0-9]+ { return scan_number(sleightext,&sleighlval,false); }\n0x[0-9a-fA-F]+ { return scan_number(sleightext,&sleighlval,false); }\n0b[01]+ { return scan_number(sleightext,&sleighlval,false); }\n[\\r\\ \\t\\v]+\n\\n { slgh->nextLine(); }\n. { return sleightext[0]; }\n\n^@.*\\n? { slgh->nextLine(); BEGIN( preprocess(preproc,preproc) ); }\n^.*\\n { slgh->nextLine(); }\n\n<> { sleigh_delete_buffer( YY_CURRENT_BUFFER );\n if (filebuffers.empty())\n yyterminate(); \n sleigh_switch_to_buffer( filebuffers.back().lastbuffer );\n\t FILE *curfile = filebuffers.back().file;\n\t if (curfile != (FILE *)0)\n\t fclose(curfile);\n filebuffers.pop_back();\n slgh->parseFileFinished();\n }\n" }, { "path": "pypcode/sleigh/slghsymbol.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"slghsymbol.hh\"\n#include \"sleighbase.hh\"\n#include \n\nnamespace ghidra {\n\nusing std::log;\n\nSleighSymbol *SymbolScope::addSymbol(SleighSymbol *a)\n\n{\n pair res;\n \n res = tree.insert( a );\n if (!res.second)\n return *res.first;\t\t// Symbol already exists in this table\n return a;\n}\n\nSleighSymbol *SymbolScope::findSymbol(const string &nm) const\n\n{\n SleighSymbol dummy(nm);\n SymbolTree::const_iterator iter;\n\n iter = tree.find( &dummy );\n if (iter != tree.end())\n return *iter;\n return (SleighSymbol *)0;\n}\n\nSymbolTable::~SymbolTable(void)\n\n{\n vector::iterator iter;\n for(iter=table.begin();iter!=table.end();++iter)\n delete *iter;\n vector::iterator siter;\n for(siter=symbollist.begin();siter!=symbollist.end();++siter)\n delete *siter;\n}\n\nvoid SymbolTable::addScope(void)\n\n{\n curscope = new SymbolScope(curscope,table.size());\n table.push_back(curscope);\n}\n\nvoid SymbolTable::popScope(void)\n\n{\n if (curscope != (SymbolScope *)0)\n curscope = curscope->getParent();\n}\n\nSymbolScope *SymbolTable::skipScope(int4 i) const\n\n{\n SymbolScope *res = curscope;\n while(i>0) {\n if (res->parent == (SymbolScope *)0) return res;\n res = res->parent;\n --i;\n }\n return res;\n}\n\nvoid SymbolTable::addGlobalSymbol(SleighSymbol *a)\n\n{\n a->id = symbollist.size();\n symbollist.push_back(a);\n SymbolScope *scope = getGlobalScope();\n a->scopeid = scope->getId();\n SleighSymbol *res = scope->addSymbol(a);\n if (res != a)\n throw SleighError(\"Duplicate symbol name '\" + a->getName() + \"'\");\n}\n\nvoid SymbolTable::addSymbol(SleighSymbol *a)\n\n{\n a->id = symbollist.size();\n symbollist.push_back(a);\n a->scopeid = curscope->getId();\n SleighSymbol *res = curscope->addSymbol(a);\n if (res != a)\n throw SleighError(\"Duplicate symbol name: \"+a->getName());\n}\n\nSleighSymbol *SymbolTable::findSymbolInternal(SymbolScope *scope,const string &nm) const\n\n{\n SleighSymbol *res;\n \n while(scope != (SymbolScope *)0) {\n res = scope->findSymbol(nm);\n if (res != (SleighSymbol *)0)\n return res;\n scope = scope->getParent();\t// Try higher scope\n }\n return (SleighSymbol *)0;\n}\n\nvoid SymbolTable::replaceSymbol(SleighSymbol *a,SleighSymbol *b)\n\n{\t\t\t\t// Replace symbol a with symbol b\n\t\t\t\t// assuming a and b have the same name\n SleighSymbol *sym;\n int4 i = table.size()-1;\n \n while(i>=0) {\t\t\t// Find the particular symbol\n sym = table[i]->findSymbol( a->getName() );\n if (sym == a) {\n table[i]->removeSymbol(a);\n b->id = a->id;\n b->scopeid = a->scopeid;\n symbollist[b->id] = b;\n table[i]->addSymbol(b);\n delete a;\n return;\n }\n --i;\n }\n}\n\nvoid SymbolTable::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_SYMBOL_TABLE);\n encoder.writeSignedInteger(sla::ATTRIB_SCOPESIZE, table.size());\n encoder.writeSignedInteger(sla::ATTRIB_SYMBOLSIZE, symbollist.size());\n for(int4 i=0;igetId());\n if (table[i]->getParent() == (SymbolScope *)0)\n encoder.writeUnsignedInteger(sla::ATTRIB_PARENT, 0);\n else\n encoder.writeUnsignedInteger(sla::ATTRIB_PARENT, table[i]->getParent()->getId());\n encoder.closeElement(sla::ELEM_SCOPE);\n }\n\n\t\t\t\t// First save the headers\n for(int4 i=0;iencodeHeader(encoder);\n\n\t\t\t\t// Now save the content of each symbol\n for(int4 i=0;iencode(encoder);\n encoder.closeElement(sla::ELEM_SYMBOL_TABLE);\n}\n\nvoid SymbolTable::decode(Decoder &decoder,SleighBase *trans)\n\n{\n int4 el = decoder.openElement(sla::ELEM_SYMBOL_TABLE);\n table.resize(decoder.readSignedInteger(sla::ATTRIB_SCOPESIZE), (SymbolScope *)0);\n symbollist.resize(decoder.readSignedInteger(sla::ATTRIB_SYMBOLSIZE), (SleighSymbol *)0);\n for(int4 i=0;idecode(decoder,trans);\n // Tag closed by decode method\n // decoder.closeElement(subel);\n }\n decoder.closeElement(el);\n}\n\nvoid SymbolTable::decodeSymbolHeader(Decoder &decoder)\n\n{\t\t\t\t// Put the shell of a symbol in the symbol table\n\t\t\t\t// in order to allow recursion\n SleighSymbol *sym;\n uint4 el = decoder.peekElement();\n if (el == sla::ELEM_USEROP_HEAD)\n sym = new UserOpSymbol();\n else if (el == sla::ELEM_EPSILON_SYM_HEAD)\n sym = new EpsilonSymbol();\n else if (el == sla::ELEM_VALUE_SYM_HEAD)\n sym = new ValueSymbol();\n else if (el == sla::ELEM_VALUEMAP_SYM_HEAD)\n sym = new ValueMapSymbol();\n else if (el == sla::ELEM_NAME_SYM_HEAD)\n sym = new NameSymbol();\n else if (el == sla::ELEM_VARNODE_SYM_HEAD)\n sym = new VarnodeSymbol();\n else if (el == sla::ELEM_CONTEXT_SYM_HEAD)\n sym = new ContextSymbol();\n else if (el == sla::ELEM_VARLIST_SYM_HEAD)\n sym = new VarnodeListSymbol();\n else if (el == sla::ELEM_OPERAND_SYM_HEAD)\n sym = new OperandSymbol();\n else if (el == sla::ELEM_START_SYM_HEAD)\n sym = new StartSymbol();\n else if (el == sla::ELEM_END_SYM_HEAD)\n sym = new EndSymbol();\n else if (el == sla::ELEM_NEXT2_SYM_HEAD)\n sym = new Next2Symbol();\n else if (el == sla::ELEM_SUBTABLE_SYM_HEAD)\n sym = new SubtableSymbol();\n else\n throw SleighError(\"Bad symbol xml\");\n sym->decodeHeader(decoder);\t// Restore basic elements of symbol\n symbollist[sym->id] = sym;\t// Put the basic symbol in the table\n table[sym->scopeid]->addSymbol(sym); // to allow recursion\n}\n\nvoid SymbolTable::purge(void)\n\n{\t\t\t\t// Get rid of unsavable symbols and scopes\n SleighSymbol *sym;\n for(int4 i=0;iscopeid != 0) { // Not in global scope\n if (sym->getType() == SleighSymbol::operand_symbol) continue;\n }\n else {\n switch(sym->getType()) {\n case SleighSymbol::space_symbol:\n case SleighSymbol::token_symbol:\n case SleighSymbol::epsilon_symbol:\n case SleighSymbol::section_symbol:\n case SleighSymbol::bitrange_symbol:\n\tbreak;\n case SleighSymbol::macro_symbol:\n\t{\t\t\t// Delete macro's local symbols\n\t MacroSymbol *macro = (MacroSymbol *)sym;\n\t for(int4 i=0;igetNumOperands();++i) {\n\t SleighSymbol *opersym = macro->getOperand(i);\n\t table[opersym->scopeid]->removeSymbol(opersym);\n\t symbollist[opersym->id] = (SleighSymbol *)0;\n\t delete opersym;\n\t }\n\t break;\n\t}\n case SleighSymbol::subtable_symbol:\n\t{\t\t\t// Delete unused subtables\n\t SubtableSymbol *subsym = (SubtableSymbol *)sym;\n\t if (subsym->getPattern() != (TokenPattern *)0) continue;\n\t for(int4 i=0;igetNumConstructors();++i) { // Go thru each constructor\n\t Constructor *con = subsym->getConstructor(i);\n\t for(int4 j=0;jgetNumOperands();++j) { // Go thru each operand\n\t OperandSymbol *oper = con->getOperand(j);\n\t table[oper->scopeid]->removeSymbol(oper);\n\t symbollist[oper->id] = (SleighSymbol *)0;\n\t delete oper;\n\t }\n\t }\n\t break;\t\t// Remove the subtable symbol itself\n\t}\n default:\n\tcontinue;\n }\n }\n table[sym->scopeid]->removeSymbol(sym); // Remove the symbol\n symbollist[i] = (SleighSymbol *)0;\n delete sym;\n }\n for(int4 i=1;itree.empty()) {\n delete table[i];\n table[i] = (SymbolScope *)0;\n }\n }\n renumber();\n}\n\nvoid SymbolTable::renumber(void)\n\n{\t\t\t\t// Renumber all the scopes and symbols\n\t\t\t\t// so that there are no gaps\n vector newtable;\n vector newsymbol;\n\t\t\t\t// First renumber the scopes\n SymbolScope *scope;\n for(int4 i=0;iid = newtable.size();\n newtable.push_back(scope);\n }\n }\n\t\t\t\t// Now renumber the symbols\n SleighSymbol *sym;\n for(int4 i=0;iscopeid = table[sym->scopeid]->id;\n sym->id = newsymbol.size();\n newsymbol.push_back(sym);\n }\n }\n table = newtable;\n symbollist = newsymbol;\n}\n\nvoid SleighSymbol::encodeHeader(Encoder &encoder) const\n\n{\t\t\t\t// Save the basic attributes of a symbol\n encoder.writeString(sla::ATTRIB_NAME, name);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, id);\n encoder.writeUnsignedInteger(sla::ATTRIB_SCOPE, scopeid);\n}\n\nvoid SleighSymbol::decodeHeader(Decoder &decoder)\n\n{\n uint4 el = decoder.openElement();\n name = decoder.readString(sla::ATTRIB_NAME);\n id = decoder.readUnsignedInteger(sla::ATTRIB_ID);\n scopeid = decoder.readUnsignedInteger(sla::ATTRIB_SCOPE);\n decoder.closeElement(el);\n}\n\nvoid SleighSymbol::encode(Encoder &encoder) const\n\n{\n throw LowlevelError(\"Symbol \"+name+\" cannot be encoded to stream directly\");\n}\n\nvoid SleighSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n throw LowlevelError(\"Symbol \"+name+\" cannot be decoded from stream directly\");\n}\n\nvoid UserOpSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_USEROP);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.writeSignedInteger(sla::ATTRIB_INDEX, index);\n encoder.closeElement(sla::ELEM_USEROP);\n}\n\nvoid UserOpSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_USEROP_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_USEROP_HEAD);\n}\n\nvoid UserOpSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n index = decoder.readSignedInteger(sla::ATTRIB_INDEX);\n decoder.closeElement(sla::ELEM_USEROP.getId());\n}\n\nPatternlessSymbol::PatternlessSymbol(void)\n\n{\t// The void constructor must explicitly build the ConstantValue. It is not decode (or encoded)\n patexp = new ConstantValue((intb)0);\n patexp->layClaim();\n}\n\nPatternlessSymbol::PatternlessSymbol(const string &nm)\n : SpecificSymbol(nm)\n{\n patexp = new ConstantValue((intb)0);\n patexp->layClaim();\n}\n\nPatternlessSymbol::~PatternlessSymbol(void)\n\n{\n PatternExpression::release(patexp);\n}\n\nvoid EpsilonSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n hand.space = const_space;\n hand.offset_space = (AddrSpace *)0; // Not a dynamic value\n hand.offset_offset = 0;\n hand.size = 0;\t\t// Cannot provide size\n}\n\nvoid EpsilonSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n s << '0';\n}\n\nVarnodeTpl *EpsilonSymbol::getVarnode(void) const\n\n{\n VarnodeTpl *res = new VarnodeTpl(ConstTpl(const_space),\n\t\t\t\t ConstTpl(ConstTpl::real,0),\n\t\t\t\t ConstTpl(ConstTpl::real,0));\n return res;\n}\n\nvoid EpsilonSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_EPSILON_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.closeElement(sla::ELEM_EPSILON_SYM);\n}\n\nvoid EpsilonSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_EPSILON_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_EPSILON_SYM_HEAD);\n}\n\nvoid EpsilonSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n const_space = trans->getConstantSpace();\n decoder.closeElement(sla::ELEM_EPSILON_SYM.getId());\n}\n\nValueSymbol::ValueSymbol(const string &nm,PatternValue *pv)\n : FamilySymbol(nm)\n{\n (patval=pv)->layClaim();\n}\n\nValueSymbol::~ValueSymbol(void)\n\n{\n if (patval != (PatternValue *)0)\n PatternExpression::release(patval);\n}\n\nvoid ValueSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n hand.space = walker.getConstSpace();\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = (uintb) patval->getValue(walker);\n hand.size = 0;\t\t// Cannot provide size\n}\n\nvoid ValueSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n intb val = patval->getValue(walker);\n if (val >= 0)\n s << \"0x\" << hex << val;\n else\n s << \"-0x\" << hex << -val;\n}\n\nvoid ValueSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VALUE_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n patval->encode(encoder);\n encoder.closeElement(sla::ELEM_VALUE_SYM);\n}\n\nvoid ValueSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VALUE_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_VALUE_SYM_HEAD);\n}\n\nvoid ValueSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans);\n patval->layClaim();\n decoder.closeElement(sla::ELEM_VALUE_SYM.getId());\n}\n\nvoid ValueMapSymbol::checkTableFill(void)\n\n{ // Check if all possible entries in the table have been filled\n intb min = patval->minValue();\n intb max = patval->maxValue();\n tableisfilled = (min>=0)&&(maxgetValue(walker);\n if ((ind >= valuetable.size())||(ind<0)||(valuetable[ind] == 0xBADBEEF)) {\n ostringstream s;\n s << walker.getAddr().getShortcut();\n walker.getAddr().printRaw(s);\n s << \": No corresponding entry in valuetable\";\n throw BadDataError(s.str());\n }\n }\n return (Constructor *)0;\n}\n\nvoid ValueMapSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n uint4 ind = (uint4) patval->getValue(walker);\n // The resolve routine has checked that -ind- must be a valid index\n hand.space = walker.getConstSpace();\n hand.offset_space = (AddrSpace *)0; // Not a dynamic value\n hand.offset_offset = (uintb)valuetable[ind];\n hand.size = 0;\t\t// Cannot provide size\n}\n\nvoid ValueMapSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n uint4 ind = (uint4)patval->getValue(walker);\n // ind is already checked to be in range by the resolve routine\n intb val = valuetable[ind];\n if (val >= 0)\n s << \"0x\" << hex << val;\n else\n s << \"-0x\" << hex << -val;\n}\n\nvoid ValueMapSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VALUEMAP_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n patval->encode(encoder);\n for(uint4 i=0;ilayClaim();\n while(decoder.peekElement() != 0) {\n uint4 subel = decoder.openElement();\n intb val = decoder.readSignedInteger(sla::ATTRIB_VAL);\n valuetable.push_back(val);\n decoder.closeElement(subel);\n }\n decoder.closeElement(sla::ELEM_VALUEMAP_SYM.getId());\n checkTableFill();\n}\n\nvoid NameSymbol::checkTableFill(void)\n\n{ // Check if all possible entries in the table have been filled\n intb min = patval->minValue();\n intb max = patval->maxValue();\n tableisfilled = (min>=0)&&(maxgetValue(walker);\n if ((ind >= nametable.size())||(ind<0)||((nametable[ind].size()==1)&&(nametable[ind][0]=='\\t'))) {\n ostringstream s;\n s << walker.getAddr().getShortcut();\n walker.getAddr().printRaw(s);\n s << \": No corresponding entry in nametable\";\n throw BadDataError(s.str());\n }\n }\n return (Constructor *)0;\n}\n\nvoid NameSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n uint4 ind = (uint4)patval->getValue(walker);\n // ind is already checked to be in range by the resolve routine\n s << nametable[ind];\n}\n\nvoid NameSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_NAME_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n patval->encode(encoder);\n for(int4 i=0;ilayClaim();\n while(decoder.peekElement() != 0) {\n uint4 subel = decoder.openElement();\n if (decoder.getNextAttributeId() == sla::ATTRIB_NAME)\n nametable.push_back(decoder.readString());\n else\n nametable.push_back(\"\\t\");\t\t// TAB indicates an illegal index\n decoder.closeElement(subel);\n }\n decoder.closeElement(sla::ELEM_NAME_SYM.getId());\n checkTableFill();\n}\n\nVarnodeSymbol::VarnodeSymbol(const string &nm,AddrSpace *base,uintb offset,int4 size)\n : PatternlessSymbol(nm)\n{\n fix.space = base;\n fix.offset = offset;\n fix.size = size;\n context_bits = false;\n}\n\nVarnodeTpl *VarnodeSymbol::getVarnode(void) const\n\n{\n return new VarnodeTpl(ConstTpl(fix.space),ConstTpl(ConstTpl::real,fix.offset),ConstTpl(ConstTpl::real,fix.size));\n}\n\nvoid VarnodeSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n hand.space = fix.space;\n hand.offset_space = (AddrSpace *)0; // Not a dynamic symbol\n hand.offset_offset = fix.offset;\n hand.size = fix.size;\n}\n\nvoid VarnodeSymbol::collectLocalValues(vector &results) const\n\n{\n if (fix.space->getType() == IPTR_INTERNAL)\n results.push_back(fix.offset);\n}\n\nvoid VarnodeSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VARNODE_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.writeSpace(sla::ATTRIB_SPACE,fix.space);\n encoder.writeUnsignedInteger(sla::ATTRIB_OFF, fix.offset);\n encoder.writeSignedInteger(sla::ATTRIB_SIZE, fix.size);\n encoder.closeElement(sla::ELEM_VARNODE_SYM);\n}\n\nvoid VarnodeSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VARNODE_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_VARNODE_SYM_HEAD);\n}\n\nvoid VarnodeSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n fix.space = decoder.readSpace(sla::ATTRIB_SPACE);\n fix.offset = decoder.readUnsignedInteger(sla::ATTRIB_OFF);\n fix.size = decoder.readSignedInteger(sla::ATTRIB_SIZE);\n\t\t\t\t// PatternlessSymbol does not need restoring\n decoder.closeElement(sla::ELEM_VARNODE_SYM.getId());\n}\n\nContextSymbol::ContextSymbol(const string &nm,ContextField *pate,VarnodeSymbol *v,\n\t\t\t uint4 l,uint4 h,bool fl)\n : ValueSymbol(nm,pate)\n{\n vn = v;\n low = l;\n high = h;\n flow = fl;\n}\n\nvoid ContextSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_CONTEXT_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.writeUnsignedInteger(sla::ATTRIB_VARNODE, vn->getId());\n encoder.writeSignedInteger(sla::ATTRIB_LOW, low);\n encoder.writeSignedInteger(sla::ATTRIB_HIGH, high);\n encoder.writeBool(sla::ATTRIB_FLOW, flow);\n patval->encode(encoder);\n encoder.closeElement(sla::ELEM_CONTEXT_SYM);\n}\n\nvoid ContextSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_CONTEXT_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_CONTEXT_SYM_HEAD);\n}\n\nvoid ContextSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n // SleighSymbol::decodeHeader(decoder);\t// Already filled in by the header tag\n flow = false;\n bool highMissing = true;\n bool lowMissing = true;\n uint4 attrib = decoder.getNextAttributeId();\n while(attrib != 0) {\n if (attrib == sla::ATTRIB_VARNODE) {\n uintm id = decoder.readUnsignedInteger();\n vn = (VarnodeSymbol *)trans->findSymbol(id);\n }\n else if (attrib == sla::ATTRIB_LOW) {\n low = decoder.readSignedInteger();\n lowMissing = false;\n }\n else if (attrib == sla::ATTRIB_HIGH) {\n high = decoder.readSignedInteger();\n highMissing = false;\n }\n else if (attrib == sla::ATTRIB_FLOW) {\n flow = decoder.readBool();\n }\n attrib = decoder.getNextAttributeId();\n }\n if (lowMissing || highMissing) {\n throw DecoderError(\"Missing high/low attributes\");\n }\n patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans);\n patval->layClaim();\n decoder.closeElement(sla::ELEM_CONTEXT_SYM.getId());\n}\n\nVarnodeListSymbol::VarnodeListSymbol(const string &nm,PatternValue *pv,const vector &vt)\n : ValueSymbol(nm,pv)\n{\n for(int4 i=0;iminValue();\n intb max = patval->maxValue();\n tableisfilled = (min>=0)&&(maxgetValue(walker);\n if ((ind<0)||(ind>=varnode_table.size())||(varnode_table[ind]==(VarnodeSymbol *)0)) {\n ostringstream s;\n s << walker.getAddr().getShortcut();\n walker.getAddr().printRaw(s);\n s << \": No corresponding entry in varnode list\";\n throw BadDataError(s.str());\n }\n }\n return (Constructor *)0;\n}\n\nvoid VarnodeListSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n uint4 ind = (uint4) patval->getValue(walker);\n // The resolve routine has checked that -ind- must be a valid index\n const VarnodeData &fix( varnode_table[ind]->getFixedVarnode() );\n hand.space = fix.space;\n hand.offset_space = (AddrSpace *)0; // Not a dynamic value\n hand.offset_offset = fix.offset;\n hand.size = fix.size;\n}\n\nint4 VarnodeListSymbol::getSize(void) const\n\n{\n for(int4 i=0;igetSize();\n }\n throw SleighError(\"No register attached to: \"+getName());\n}\n\nvoid VarnodeListSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n uint4 ind = (uint4)patval->getValue(walker);\n if (ind >= varnode_table.size())\n throw SleighError(\"Value out of range for varnode table\");\n s << varnode_table[ind]->getName();\n}\n\nvoid VarnodeListSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VARLIST_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n patval->encode(encoder);\n for(int4 i=0;igetId());\n encoder.closeElement(sla::ELEM_VAR);\n }\n }\n encoder.closeElement(sla::ELEM_VARLIST_SYM);\n}\n\nvoid VarnodeListSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_VARLIST_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_VARLIST_SYM_HEAD);\n}\n\nvoid VarnodeListSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans);\n patval->layClaim();\n while(decoder.peekElement() != 0) {\n uint4 subel = decoder.openElement();\n if (subel == sla::ELEM_VAR) {\n uintm id = decoder.readUnsignedInteger(sla::ATTRIB_ID);\n varnode_table.push_back( (VarnodeSymbol *)trans->findSymbol(id) );\n }\n else\n varnode_table.push_back( (VarnodeSymbol *)0 );\n decoder.closeElement(subel);\n }\n decoder.closeElement(sla::ELEM_VARLIST_SYM.getId());\n checkTableFill();\n}\n\nOperandSymbol::OperandSymbol(const string &nm,int4 index,Constructor *ct)\n : SpecificSymbol(nm)\n{\n flags = 0;\n hand = index;\n localexp = new OperandValue(index,ct);\n localexp->layClaim();\n defexp = (PatternExpression *)0;\n triple = (TripleSymbol *)0;\n}\n\nvoid OperandSymbol::defineOperand(PatternExpression *pe)\n\n{\n if ((defexp != (PatternExpression *)0)||(triple!=(TripleSymbol *)0))\n throw SleighError(\"Redefining operand\");\n defexp = pe;\n defexp->layClaim();\n}\n\nvoid OperandSymbol::defineOperand(TripleSymbol *tri)\n\n{\n if ((defexp != (PatternExpression *)0)||(triple!=(TripleSymbol *)0))\n throw SleighError(\"Redefining operand\");\n triple = tri;\n}\n\nOperandSymbol::~OperandSymbol(void)\n\n{\n PatternExpression::release(localexp);\n if (defexp != (PatternExpression *)0)\n PatternExpression::release(defexp);\n}\n\nVarnodeTpl *OperandSymbol::getVarnode(void) const\n\n{\n VarnodeTpl *res;\n if (defexp != (PatternExpression *)0)\n res = new VarnodeTpl(hand,true); // Definite constant handle\n else {\n SpecificSymbol *specsym = dynamic_cast(triple);\n if (specsym != (SpecificSymbol *)0)\n res = specsym->getVarnode();\n else if ((triple != (TripleSymbol *)0)&&\n\t ((triple->getType() == valuemap_symbol)||(triple->getType() == name_symbol)))\n res = new VarnodeTpl(hand,true); // Zero-size symbols\n else\n res = new VarnodeTpl(hand,false); // Possible dynamic handle\n }\n return res;\n}\n\nvoid OperandSymbol::getFixedHandle(FixedHandle &hnd,ParserWalker &walker) const\n\n{\n hnd = walker.getFixedHandle(hand);\n}\n\nint4 OperandSymbol::getSize(void) const\n\n{\n if (triple != (TripleSymbol *)0)\n return triple->getSize();\n return 0;\n}\n\nvoid OperandSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n walker.pushOperand(getIndex());\n if (triple != (TripleSymbol *)0) {\n if (triple->getType() == SleighSymbol::subtable_symbol)\n walker.getConstructor()->print(s,walker);\n else\n triple->print(s,walker);\n }\n else {\n intb val = defexp->getValue(walker);\n if (val >= 0)\n s << \"0x\" << hex << val;\n else\n s << \"-0x\" << hex << -val;\n }\n walker.popOperand();\n}\n\nvoid OperandSymbol::collectLocalValues(vector &results) const\n\n{\n if (triple != (TripleSymbol *)0)\n triple->collectLocalValues(results);\n}\n\nvoid OperandSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_OPERAND_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n if (triple != (TripleSymbol *)0)\n encoder.writeUnsignedInteger(sla::ATTRIB_SUBSYM, triple->getId());\n encoder.writeSignedInteger(sla::ATTRIB_OFF, reloffset);\n encoder.writeSignedInteger(sla::ATTRIB_BASE, offsetbase);\n encoder.writeSignedInteger(sla::ATTRIB_MINLEN, minimumlength);\n if (isCodeAddress())\n encoder.writeBool(sla::ATTRIB_CODE, true);\n encoder.writeSignedInteger(sla::ATTRIB_INDEX, hand);\n localexp->encode(encoder);\n if (defexp != (PatternExpression *)0)\n defexp->encode(encoder);\n encoder.closeElement(sla::ELEM_OPERAND_SYM);\n}\n\nvoid OperandSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_OPERAND_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_OPERAND_SYM_HEAD);\n}\n\nvoid OperandSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n defexp = (PatternExpression *)0;\n triple = (TripleSymbol *)0;\n flags = 0;\n uint4 attrib = decoder.getNextAttributeId();\n while(attrib != 0) {\n attrib = decoder.getNextAttributeId();\n if (attrib == sla::ATTRIB_INDEX)\n hand = decoder.readSignedInteger();\n else if (attrib == sla::ATTRIB_OFF)\n reloffset = decoder.readSignedInteger();\n else if (attrib == sla::ATTRIB_BASE)\n offsetbase = decoder.readSignedInteger();\n else if (attrib == sla::ATTRIB_MINLEN)\n minimumlength = decoder.readSignedInteger();\n else if (attrib == sla::ATTRIB_SUBSYM) {\n uintm id = decoder.readUnsignedInteger();\n triple = (TripleSymbol *)trans->findSymbol(id);\n }\n else if (attrib == sla::ATTRIB_CODE) {\n if (decoder.readBool())\n\tflags |= code_address;\n }\n }\n localexp = (OperandValue *)PatternExpression::decodeExpression(decoder,trans);\n localexp->layClaim();\n if (decoder.peekElement() != 0) {\n defexp = PatternExpression::decodeExpression(decoder,trans);\n defexp->layClaim();\n }\n decoder.closeElement(sla::ELEM_OPERAND_SYM.getId());\n}\n\nStartSymbol::StartSymbol(const string &nm,AddrSpace *cspc) : SpecificSymbol(nm)\n\n{\n const_space = cspc;\n patexp = new StartInstructionValue();\n patexp->layClaim();\n}\n\nStartSymbol::~StartSymbol(void)\n\n{\n if (patexp != (PatternExpression *)0)\n PatternExpression::release(patexp);\n}\n\nVarnodeTpl *StartSymbol::getVarnode(void) const\n\n{ // Returns current instruction offset as a constant\n ConstTpl spc(const_space);\n ConstTpl off(ConstTpl::j_start);\n ConstTpl sz_zero;\n return new VarnodeTpl(spc,off,sz_zero);\n}\n\nvoid StartSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n hand.space = walker.getCurSpace();\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = walker.getAddr().getOffset(); // Get starting address of instruction\n hand.size = hand.space->getAddrSize();\n}\n\nvoid StartSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n intb val = (intb) walker.getAddr().getOffset();\n s << \"0x\" << hex << val;\n}\n\nvoid StartSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_START_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.closeElement(sla::ELEM_START_SYM);\n}\n\nvoid StartSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_START_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_START_SYM_HEAD);\n}\n\nvoid StartSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n const_space = trans->getConstantSpace();\n patexp = new StartInstructionValue();\n patexp->layClaim();\n decoder.closeElement(sla::ELEM_START_SYM.getId());\n}\n\nEndSymbol::EndSymbol(const string &nm,AddrSpace *cspc) : SpecificSymbol(nm)\n\n{\n const_space = cspc;\n patexp = new EndInstructionValue();\n patexp->layClaim();\n}\n\nEndSymbol::~EndSymbol(void)\n\n{\n if (patexp != (PatternExpression *)0)\n PatternExpression::release(patexp);\n}\n\nVarnodeTpl *EndSymbol::getVarnode(void) const\n\n{ // Return next instruction offset as a constant\n ConstTpl spc(const_space);\n ConstTpl off(ConstTpl::j_next);\n ConstTpl sz_zero;\n return new VarnodeTpl(spc,off,sz_zero);\n}\n\nvoid EndSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n hand.space = walker.getCurSpace();\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = walker.getNaddr().getOffset(); // Get starting address of next instruction\n hand.size = hand.space->getAddrSize();\n}\n\nvoid EndSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n intb val = (intb) walker.getNaddr().getOffset();\n s << \"0x\" << hex << val;\n}\n\nvoid EndSymbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_END_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.closeElement(sla::ELEM_END_SYM);\n}\n\nvoid EndSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_END_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_END_SYM_HEAD);\n}\n\nvoid EndSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n const_space = trans->getConstantSpace();\n patexp = new EndInstructionValue();\n patexp->layClaim();\n decoder.closeElement(sla::ELEM_END_SYM.getId());\n}\n\nNext2Symbol::Next2Symbol(const string &nm,AddrSpace *cspc) : SpecificSymbol(nm)\n\n{\n const_space = cspc;\n patexp = new Next2InstructionValue();\n patexp->layClaim();\n}\n\nNext2Symbol::~Next2Symbol(void)\n\n{\n if (patexp != (PatternExpression *)0)\n PatternExpression::release(patexp);\n}\n\nVarnodeTpl *Next2Symbol::getVarnode(void) const\n\n{ // Return instruction offset after next instruction offset as a constant\n ConstTpl spc(const_space);\n ConstTpl off(ConstTpl::j_next2);\n ConstTpl sz_zero;\n return new VarnodeTpl(spc,off,sz_zero);\n}\n\nvoid Next2Symbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n hand.space = walker.getCurSpace();\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = walker.getN2addr().getOffset(); // Get instruction address after next instruction\n hand.size = hand.space->getAddrSize();\n}\n\nvoid Next2Symbol::print(ostream &s,ParserWalker &walker) const\n\n{\n intb val = (intb) walker.getN2addr().getOffset();\n s << \"0x\" << hex << val;\n}\n\nvoid Next2Symbol::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_NEXT2_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.closeElement(sla::ELEM_NEXT2_SYM);\n}\n\nvoid Next2Symbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_NEXT2_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_NEXT2_SYM_HEAD);\n}\n\nvoid Next2Symbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n const_space = trans->getConstantSpace();\n patexp = new Next2InstructionValue();\n patexp->layClaim();\n decoder.closeElement(sla::ELEM_NEXT2_SYM.getId());\n}\n\nFlowDestSymbol::FlowDestSymbol(const string &nm,AddrSpace *cspc) : SpecificSymbol(nm)\n\n{\n const_space = cspc;\n}\n\nVarnodeTpl *FlowDestSymbol::getVarnode(void) const\n\n{\n ConstTpl spc(const_space);\n ConstTpl off(ConstTpl::j_flowdest);\n ConstTpl sz_zero;\n return new VarnodeTpl(spc,off,sz_zero);\n}\n\nvoid FlowDestSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n Address refAddr = walker.getDestAddr();\n hand.space = const_space;\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = refAddr.getOffset();\n hand.size = refAddr.getAddrSize();\n}\n\nvoid FlowDestSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n intb val = (intb) walker.getDestAddr().getOffset();\n s << \"0x\" << hex << val;\n}\n\nFlowRefSymbol::FlowRefSymbol(const string &nm,AddrSpace *cspc) : SpecificSymbol(nm)\n\n{\n const_space = cspc;\n}\n\nVarnodeTpl *FlowRefSymbol::getVarnode(void) const\n\n{\n ConstTpl spc(const_space);\n ConstTpl off(ConstTpl::j_flowref);\n ConstTpl sz_zero;\n return new VarnodeTpl(spc,off,sz_zero);\n}\n\nvoid FlowRefSymbol::getFixedHandle(FixedHandle &hand,ParserWalker &walker) const\n\n{\n Address refAddr = walker.getRefAddr();\n hand.space = const_space;\n hand.offset_space = (AddrSpace *)0;\n hand.offset_offset = refAddr.getOffset();\n hand.size = refAddr.getAddrSize();\n}\n\nvoid FlowRefSymbol::print(ostream &s,ParserWalker &walker) const\n\n{\n intb val = (intb) walker.getRefAddr().getOffset();\n s << \"0x\" << hex << val;\n}\n\nConstructor::Constructor(void)\n\n{\n pattern = (TokenPattern *)0;\n parent = (SubtableSymbol *)0;\n pateq = (PatternEquation *)0;\n templ = (ConstructTpl *)0;\n firstwhitespace = -1;\n flowthruindex = -1;\n inerror = false;\n}\n\nConstructor::Constructor(SubtableSymbol *p)\n\n{\n pattern = (TokenPattern *)0;\n parent = p;\n pateq = (PatternEquation *)0;\n templ = (ConstructTpl *)0;\n firstwhitespace = -1;\n inerror = false;\n}\n\nConstructor::~Constructor(void)\n\n{\n if (pattern != (TokenPattern *)0)\n delete pattern;\n if (pateq != (PatternEquation *)0)\n PatternEquation::release(pateq);\n if (templ != (ConstructTpl *)0)\n delete templ;\n for(int4 i=0;i::iterator iter;\n for(iter=context.begin();iter!=context.end();++iter)\n delete *iter;\n}\n\nvoid Constructor::addInvisibleOperand(OperandSymbol *sym)\n\n{\n operands.push_back(sym);\n}\n\nvoid Constructor::addOperand(OperandSymbol *sym)\n\n{\n string operstring = \"\\n \";\t// Indicater character for operand\n operstring[1] = ('A'+operands.size()); // Encode index of operand\n operands.push_back(sym);\n printpiece.push_back(operstring); // Placeholder for operand's string\n}\n\nvoid Constructor::addSyntax(const string &syn)\n\n{\n string syntrim;\n\n if (syn.size() == 0) return;\n bool hasNonSpace = false;\n for(int4 i=0;ilayClaim();\n}\n\nvoid Constructor::setNamedSection(ConstructTpl *tpl,int4 id)\n\n{\t\t\t\t// Add a named section to the constructor\n while(namedtempl.size() <= id)\n namedtempl.push_back((ConstructTpl *)0);\n namedtempl[id] = tpl;\n}\n\nConstructTpl *Constructor::getNamedTempl(int4 secnum) const\n\n{\n if (secnum < namedtempl.size())\n return namedtempl[secnum];\n return (ConstructTpl *)0;\n}\n\nvoid Constructor::print(ostream &s,ParserWalker &walker) const\n\n{\n vector::const_iterator piter;\n\n for(piter=printpiece.begin();piter!=printpiece.end();++piter) {\n if ((*piter)[0] == '\\n') {\n int4 index = (*piter)[1]-'A';\n operands[index]->print(s,walker);\n }\n else\n s << *piter;\n }\n}\n\nvoid Constructor::printMnemonic(ostream &s,ParserWalker &walker) const\n\n{\n if (flowthruindex != -1) {\n SubtableSymbol *sym = dynamic_cast(operands[flowthruindex]->getDefiningSymbol());\n if (sym != (SubtableSymbol *)0) {\n walker.pushOperand(flowthruindex);\n walker.getConstructor()->printMnemonic(s,walker);\n walker.popOperand();\n return;\n }\n }\n int4 endind = (firstwhitespace==-1) ? printpiece.size() : firstwhitespace;\n for(int4 i=0;iprint(s,walker);\n }\n else\n s << printpiece[i];\n }\n}\n\nvoid Constructor::printBody(ostream &s,ParserWalker &walker) const\n\n{\n if (flowthruindex != -1) {\n SubtableSymbol *sym = dynamic_cast(operands[flowthruindex]->getDefiningSymbol());\n if (sym != (SubtableSymbol *)0) {\n walker.pushOperand(flowthruindex);\n walker.getConstructor()->printBody(s,walker);\n walker.popOperand();\n return;\n }\n }\n if (firstwhitespace == -1) return; // Nothing to print after firstwhitespace\n for(int4 i=firstwhitespace+1;iprint(s,walker);\n }\n else\n s << printpiece[i];\n }\n}\n\nvoid Constructor::removeTrailingSpace(void)\n\n{\n // Allow for user to force extra space at end of printing\n if ((!printpiece.empty())&&(printpiece.back()==\" \"))\n printpiece.pop_back();\n // while((!printpiece.empty())&&(printpiece.back()==\" \"))\n // printpiece.pop_back();\n}\n\nvoid Constructor::markSubtableOperands(vector &check) const\n\n{ // Adjust -check- so it has one entry for every operand, a 0 if it is a subtable, a 2 if it is not\n check.resize(operands.size());\n for(int4 i=0;igetDefiningSymbol();\n if ((sym != (TripleSymbol *)0)&&(sym->getType() == SleighSymbol::subtable_symbol))\n check[i] = 0;\n else\n check[i] = 2;\n }\n}\n\nvoid Constructor::collectLocalExports(vector &results) const\n\n{\n if (templ == (ConstructTpl *)0) return;\n HandleTpl *handle = templ->getResult();\n if (handle == (HandleTpl *)0) return;\n if (handle->getSpace().isConstSpace()) return;\t// Even if the value is dynamic, the pointed to value won't get used\n if (handle->getPtrSpace().getType() != ConstTpl::real) {\n if (handle->getTempSpace().isUniqueSpace())\n results.push_back(handle->getTempOffset().getReal());\n return;\n }\n if (handle->getSpace().isUniqueSpace()) {\n results.push_back(handle->getPtrOffset().getReal());\n return;\n }\n if (handle->getSpace().getType() == ConstTpl::handle) {\n int4 handleIndex = handle->getSpace().getHandleIndex();\n OperandSymbol *opSym = getOperand(handleIndex);\n opSym->collectLocalValues(results);\n }\n}\n\nbool Constructor::isRecursive(void) const\n\n{ // Does this constructor cause recursion with its table\n for(int4 i=0;igetDefiningSymbol();\n if (sym == parent) return true;\n }\n return false;\n}\n\nvoid Constructor::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_CONSTRUCTOR);\n encoder.writeUnsignedInteger(sla::ATTRIB_PARENT, parent->getId());\n encoder.writeSignedInteger(sla::ATTRIB_FIRST, firstwhitespace);\n encoder.writeSignedInteger(sla::ATTRIB_LENGTH, minimumlength);\n encoder.writeSignedInteger(sla::ATTRIB_SOURCE, src_index);\n encoder.writeSignedInteger(sla::ATTRIB_LINE, lineno);\n for(int4 i=0;igetId());\n encoder.closeElement(sla::ELEM_OPER);\n }\n for(int4 i=0;iencode(encoder);\n if (templ != (ConstructTpl *)0)\n templ->encode(encoder,-1);\n for(int4 i=0;iencode(encoder,i);\n }\n encoder.closeElement(sla::ELEM_CONSTRUCTOR);\n}\n\nvoid Constructor::decode(Decoder &decoder,SleighBase *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_CONSTRUCTOR);\n uintm id = decoder.readUnsignedInteger(sla::ATTRIB_PARENT);\n parent = (SubtableSymbol *)trans->findSymbol(id);\n firstwhitespace = decoder.readSignedInteger(sla::ATTRIB_FIRST);\n minimumlength = decoder.readSignedInteger(sla::ATTRIB_LENGTH);\n src_index = decoder.readSignedInteger(sla::ATTRIB_SOURCE);\n lineno = decoder.readSignedInteger(sla::ATTRIB_LINE);\n uint4 subel = decoder.peekElement();\n while(subel != 0) {\n if (subel == sla::ELEM_OPER) {\n decoder.openElement();\n uintm id = decoder.readUnsignedInteger(sla::ATTRIB_ID);\n OperandSymbol *sym = (OperandSymbol *)trans->findSymbol(id);\n operands.push_back(sym);\n decoder.closeElement(subel);\n }\n else if (subel == sla::ELEM_PRINT) {\n decoder.openElement();\n printpiece.push_back( decoder.readString(sla::ATTRIB_PIECE));\n decoder.closeElement(subel);\n }\n else if (subel == sla::ELEM_OPPRINT) {\n decoder.openElement();\n int4 index = decoder.readSignedInteger(sla::ATTRIB_ID);\n string operstring = \"\\n \";\n operstring[1] = ('A' + index);\n printpiece.push_back(operstring);\n decoder.closeElement(subel);\n }\n else if (subel == sla::ELEM_CONTEXT_OP) {\n ContextOp *c_op = new ContextOp();\n c_op->decode(decoder,trans);\n context.push_back(c_op);\n }\n else if (subel == sla::ELEM_COMMIT) {\n ContextCommit *c_op = new ContextCommit();\n c_op->decode(decoder,trans);\n context.push_back(c_op);\n }\n else {\n ConstructTpl *cur = new ConstructTpl();\n int4 sectionid = cur->decode(decoder);\n if (sectionid < 0) {\n\tif (templ != (ConstructTpl *)0)\n\t throw LowlevelError(\"Duplicate main section\");\n\ttempl = cur;\n }\n else {\n\twhile(namedtempl.size() <= sectionid)\n\t namedtempl.push_back((ConstructTpl *)0);\n\tif (namedtempl[sectionid] != (ConstructTpl *)0)\n\t throw LowlevelError(\"Duplicate named section\");\n\tnamedtempl[sectionid] = cur;\n }\n }\n subel = decoder.peekElement();\n }\n pattern = (TokenPattern *)0;\n if ((printpiece.size()==1)&&(printpiece[0][0]=='\\n'))\n flowthruindex = printpiece[0][1] - 'A';\n else\n flowthruindex = -1;\n decoder.closeElement(el);\n}\n\nvoid Constructor::orderOperands(void)\n\n{\n OperandSymbol *sym;\n vector patternorder;\n vector newops; // New order of the operands\n int4 lastsize;\n\n pateq->operandOrder(this,patternorder);\n for(int4 i=0;iisMarked()) {\n patternorder.push_back(sym);\n sym->setMark();\t\t// Make sure all operands are marked\n }\n }\n do {\n lastsize = newops.size();\n for(int4 i=0;iisMarked()) continue; // \"unmarked\" means it is already in newops\n if (sym->isOffsetIrrelevant()) continue; // expression Operands come last\n if ((sym->offsetbase == -1)||(!operands[sym->offsetbase]->isMarked())) {\n\tnewops.push_back(sym);\n\tsym->clearMark();\n }\n }\n } while(newops.size() != lastsize);\n for(int4 i=0;iisOffsetIrrelevant()) {\n newops.push_back(sym);\n sym->clearMark();\n }\n }\n\n if (newops.size() != operands.size())\n throw SleighError(\"Circular offset dependency between operands\");\n\n\n for(int4 i=0;ihand = i;\n newops[i]->localexp->changeIndex(i);\n }\n vector handmap;\t\t// Create index translation map\n for(int4 i=0;ihand);\n\n\t\t\t\t// Fix up offsetbase\n for(int4 i=0;ioffsetbase == -1) continue;\n sym->offsetbase = handmap[sym->offsetbase];\n }\n\n if (templ != (ConstructTpl *)0) // Fix up templates\n templ->changeHandleIndex(handmap);\n for(int4 i=0;ichangeHandleIndex(handmap);\n }\n\n\t\t\t\t// Fix up printpiece operand refs\n for(int4 i=0;i oppattern;\n bool recursion = false;\n\t\t\t\t// Generate pattern for each operand, store in oppattern\n for(int4 i=0;igetDefiningSymbol();\n PatternExpression *defexp = sym->getDefiningExpression();\n if (triple != (TripleSymbol *)0) {\n SubtableSymbol *subsym = dynamic_cast(triple);\n if (subsym != (SubtableSymbol *)0) {\n\tif (subsym->isBeingBuilt()) { // Detected recursion\n\t if (recursion) {\n\t throw SleighError(\"Illegal recursion\");\n\t }\n\t\t\t\t// We should also check that recursion is rightmost extreme\n\t recursion = true;\n\t oppattern.emplace_back();\n\t}\n\telse\n\t oppattern.push_back(*subsym->buildPattern(s));\n }\n else\n\toppattern.push_back(triple->getPatternExpression()->genMinPattern(oppattern));\n }\n else if (defexp != (PatternExpression *)0)\n oppattern.push_back(defexp->genMinPattern(oppattern));\n else {\n throw SleighError(sym->getName()+\": operand is undefined\");\n }\n TokenPattern &sympat( oppattern.back() );\n sym->minimumlength = sympat.getMinimumLength();\n if (sympat.getLeftEllipsis() || sympat.getRightEllipsis())\n sym->setVariableLength();\n }\n\n if (pateq == (PatternEquation *)0)\n throw SleighError(\"Missing equation\");\n\n\t\t\t\t// Build the entire pattern\n pateq->genPattern(oppattern);\n *pattern = pateq->getTokenPattern();\n if (pattern->alwaysFalse())\n throw SleighError(\"Impossible pattern\");\n if (recursion)\n pattern->setRightEllipsis(true);\n minimumlength = pattern->getMinimumLength(); // Get length of the pattern in bytes\n\n\t\t\t\t// Resolve offsets of the operands\n OperandResolve resolve(operands);\n if (!pateq->resolveOperandLeft(resolve))\n throw SleighError(\"Unable to resolve operand offsets\");\n\n for(int4 i=0;iisOffsetIrrelevant()) {\n sym->offsetbase = -1;\n sym->reloffset = 0;\n continue;\n }\n base = sym->offsetbase;\n offset = sym->reloffset;\n while(base >= 0) {\n sym = operands[base];\n if (sym->isVariableLength()) break; // Cannot resolve to absolute\n base = sym->offsetbase;\n offset += sym->getMinimumLength();\n offset += sym->reloffset;\n if (base < 0) {\n\toperands[i]->offsetbase = base;\n\toperands[i]->reloffset = offset;\n }\n }\n }\n\n // Make sure context expressions are valid\n for(int4 i=0;ivalidate();\n\n orderOperands();\t\t// Order the operands based on offset dependency\n return pattern;\n}\n\nvoid Constructor::printInfo(ostream &s) const\n\n{\t\t\t\t// Print identifying information about constructor\n\t\t\t\t// for use in error messages\n s << \"table \\\"\" << parent->getName();\n s << \"\\\" constructor starting at line \" << dec << lineno;\n}\n\nSubtableSymbol::SubtableSymbol(const string &nm) : TripleSymbol(nm)\n\n{\n beingbuilt = false;\n pattern = (TokenPattern *)0;\n decisiontree = (DecisionNode *)0;\n errors = 0;\n}\n\nSubtableSymbol::~SubtableSymbol(void)\n\n{\n if (pattern != (TokenPattern *)0)\n delete pattern;\n if (decisiontree != (DecisionNode *)0)\n delete decisiontree;\n vector::iterator iter;\n for(iter=construct.begin();iter!=construct.end();++iter)\n delete *iter;\n}\n\nvoid SubtableSymbol::collectLocalValues(vector &results) const\n\n{\n for(int4 i=0;icollectLocalExports(results);\n}\n\nvoid SubtableSymbol::encode(Encoder &encoder) const\n\n{\n if (decisiontree == (DecisionNode *)0) return; // Not fully formed\n encoder.openElement(sla::ELEM_SUBTABLE_SYM);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, getId());\n encoder.writeSignedInteger(sla::ATTRIB_NUMCT, construct.size());\n for(int4 i=0;iencode(encoder);\n decisiontree->encode(encoder);\n encoder.closeElement(sla::ELEM_SUBTABLE_SYM);\n}\n\nvoid SubtableSymbol::encodeHeader(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_SUBTABLE_SYM_HEAD);\n SleighSymbol::encodeHeader(encoder);\n encoder.closeElement(sla::ELEM_SUBTABLE_SYM_HEAD);\n}\n\nvoid SubtableSymbol::decode(Decoder &decoder,SleighBase *trans)\n\n{\n int4 numct = decoder.readSignedInteger(sla::ATTRIB_NUMCT);\n construct.reserve(numct);\n uint4 subel = decoder.peekElement();\n while(subel != 0) {\n if (subel == sla::ELEM_CONSTRUCTOR) {\n Constructor *ct = new Constructor();\n addConstructor(ct);\n ct->decode(decoder,trans);\n }\n else if (subel == sla::ELEM_DECISION) {\n decisiontree = new DecisionNode();\n decisiontree->decode(decoder,(DecisionNode *)0,this);\n }\n subel = decoder.peekElement();\n }\n pattern = (TokenPattern *)0;\n beingbuilt = false;\n errors = 0;\n decoder.closeElement(sla::ELEM_SUBTABLE_SYM.getId());\n}\n\nvoid SubtableSymbol::buildDecisionTree(DecisionProperties &props)\n\n{\t\t\t\t// Associate pattern disjoints to constructors\n if (pattern == (TokenPattern *)0) return; // Pattern not fully formed\n Pattern *pat;\n decisiontree = new DecisionNode((DecisionNode *)0);\n for(int4 i=0;igetPattern()->getPattern();\n if (pat->numDisjoint() == 0)\n decisiontree->addConstructorPair((const DisjointPattern *)pat,construct[i]);\n else\n for(int4 j=0;jnumDisjoint();++j)\n\tdecisiontree->addConstructorPair(pat->getDisjoint(j),construct[i]);\n }\n decisiontree->split(props);\t// Create the decision strategy\n}\n\nTokenPattern *SubtableSymbol::buildPattern(ostream &s)\n\n{\n if (pattern != (TokenPattern *)0) return pattern; // Already built\n\n errors = false;\n beingbuilt = true;\n pattern = new TokenPattern();\n if (construct.empty()) {\n s << \"Error: There are no constructors in table: \"+getName() << endl;\n errors = true;\n return pattern;\n }\n try {\n construct.front()->buildPattern(s);\n } catch(SleighError &err) {\n s << \"Error: \" << err.explain << \": for \";\n construct.front()->printInfo(s);\n s << endl;\n errors = true;\n }\n *pattern = *construct.front()->getPattern();\n for(int4 i=1;ibuildPattern(s);\n } catch(SleighError &err) {\n s << \"Error: \" << err.explain << \": for \";\n construct[i]->printInfo(s);\n s << endl;\n errors = true;\n }\n *pattern = construct[i]->getPattern()->commonSubPattern(*pattern);\n }\n beingbuilt = false;\n return pattern;\n}\n\nvoid DecisionProperties::identicalPattern(Constructor *a,Constructor *b)\n\n{ // Note that -a- and -b- have identical patterns\n if ((!a->isError())&&(!b->isError())) {\n a->setError(true);\n b->setError(true);\n\n identerrors.push_back(make_pair(a, b));\n }\n}\n\nvoid DecisionProperties::conflictingPattern(Constructor *a,Constructor *b)\n\n{ // Note that -a- and -b- have (potentially) conflicting patterns\n if ((!a->isError())&&(!b->isError())) {\n a->setError(true);\n b->setError(true);\n\n conflicterrors.push_back(make_pair(a, b));\n }\n}\n\nDecisionNode::DecisionNode(DecisionNode *p)\n\n{\n parent = p;\n num = 0;\n startbit = 0;\n bitsize = 0;\n contextdecision = false;\n}\n\nDecisionNode::~DecisionNode(void)\n\n{\t\t\t\t// We own sub nodes\n vector::iterator iter;\n for(iter=children.begin();iter!=children.end();++iter)\n delete *iter;\n vector >::iterator piter;\n for(piter=list.begin();piter!=list.end();++piter)\n delete (*piter).first;\t// Delete the patterns\n}\n\nvoid DecisionNode::addConstructorPair(const DisjointPattern *pat,Constructor *ct)\n\n{\n DisjointPattern *clone = (DisjointPattern *)pat->simplifyClone(); // We need to own pattern\n list.push_back(pair(clone,ct));\n num += 1;\n}\n\nint4 DecisionNode::getMaximumLength(bool context)\n\n{\t\t\t\t// Get maximum length of instruction pattern in bytes\n int4 max = 0;\n int4 val,i;\n\n for(i=0;igetLength(context);\n if (val > max)\n max = val;\n }\n return max;\n}\n\nint4 DecisionNode::getNumFixed(int4 low,int4 size,bool context)\n\n{\t\t\t\t// Get number of patterns that specify this field\n int4 count = 0;\n uintm mask;\n\t\t\t\t// Bits which must be specified in the mask\n uintm m = (size==8*sizeof(uintm)) ? 0 : (((uintm)1)<getMask(low,size,context);\n if ((mask&m)==m)\n count += 1;\n }\n return count;\n}\n\ndouble DecisionNode::getScore(int4 low,int4 size,bool context)\n\n{\n int4 numBins = 1 << size;\t\t// size is between 1 and 8\n int4 i;\n uintm val,mask;\n uintm m = ((uintm)1)< count(numBins,0);\n\n for(i=0;igetMask(low,size,context);\n if ((mask&m)!=m) continue;\t// Skip if field not fully specified\n val = list[i].first->getValue(low,size,context);\n total += 1;\n count[val] += 1;\n }\n if (total <= 0) return -1.0;\n double sc = 0.0;\n for(i=0;i= list.size()) return -1.0;\n double p = ((double)count[i])/total;\n sc -= p * log(p);\n }\n return ( sc / log(2.0) );\n}\n\nvoid DecisionNode::chooseOptimalField(void)\n\n{\n double score = 0.0;\n \n int4 sbit,size;\t\t// The current field\n bool context;\n double sc;\n\n int4 maxlength,numfixed,maxfixed;\n\n maxfixed = 1;\n context = true;\n do {\n maxlength = 8*getMaximumLength(context);\n for(sbit=0;sbit maxfixed)&&(sc > 0.0)) {\n\tscore = sc;\n\tmaxfixed = numfixed;\n\tstartbit = sbit;\n\tbitsize = 1;\n\tcontextdecision = context;\n\tcontinue;\n }\n\t\t\t\t// We have maximum patterns\n if (sc > score) {\n\tscore = sc;\n\tstartbit = sbit;\n\tbitsize = 1;\n\tcontextdecision = context;\n }\n }\n context = !context;\n } while(!context);\n\n context = true;\n do {\n maxlength = 8*getMaximumLength(context);\n for(size=2;size <= 8;++size) {\n for(sbit=0;sbit score) {\n\t score = sc;\n\t startbit = sbit;\n\t bitsize = size;\n\t contextdecision = context;\n\t}\n }\n }\n context = !context;\n } while(!context);\n if (score <= 0.0)\t\t// If we failed to get a positive score\n bitsize = 0;\t\t// treat the node as terminal\n}\n\nvoid DecisionNode::consistentValues(vector &bins,DisjointPattern *pat)\n\n{\t\t\t\t// Produce all possible values of -pat- by\n\t\t\t\t// iterating through all possible values of the\n\t\t\t\t// \"don't care\" bits within the value of -pat-\n\t\t\t\t// that intersects with this node (startbit,bitsize,context)\n uintm m = (bitsize==8*sizeof(uintm)) ? 0 : (((uintm)1)<getMask(startbit,bitsize,contextdecision);\n uintm commonValue = commonMask & pat->getValue(startbit,bitsize,contextdecision);\n uintm dontCareMask = m^commonMask;\n\n for(uintm i=0;i<=dontCareMask;++i) { // Iterate over values that contain all don't care bits\n if ((i&dontCareMask)!=i) continue; // If all 1 bits in the value are don't cares\n bins.push_back( commonValue | i ); // add 1 bits into full value and store\n }\n}\n\nvoid DecisionNode::split(DecisionProperties &props)\n\n{\n if (list.size() <= 1) {\n bitsize = 0;\t\t// Only one pattern, terminal node by default\n return;\n }\n\n chooseOptimalField();\n if (bitsize == 0) {\n orderPatterns(props);\n return;\n }\n if ((parent != (DecisionNode *)0) && (list.size() >= parent->num))\n throw LowlevelError(\"Child has as many Patterns as parent\");\n\n int4 numChildren = 1 << bitsize;\n\n for(int4 i=0;i vals;\t\t// Bins this pattern belongs in\n\t\t\t\t// If the pattern does not care about some\n\t\t\t\t// bits in the field we are splitting on, that\n\t\t\t\t// pattern will get put into multiple bins\n consistentValues(vals,list[i].first);\n for(int4 j=0;jaddConstructorPair(list[i].first,list[i].second);\n delete list[i].first;\t// We no longer need original pattern\n }\n list.clear();\n\n for(int4 i=0;isplit(props);\n}\n\nvoid DecisionNode::orderPatterns(DecisionProperties &props)\n\n{\n // This is a tricky routine. When this routine is called, the patterns remaining in the\n // the decision node can no longer be distinguished by examining additional bits. The basic\n // idea here is that the patterns should be ordered so that the most specialized should come\n // first in the list. Pattern 1 is a specialization of pattern 2, if the set of instructions\n // matching 1 is contained in the set matching 2. So in the simplest case, the pattern order\n // should represent a strict nesting. Unfortunately, there are many potential situations where\n // patterns don't necessarily nest.\n // 1) An \"or\" of two patterns. This can be an explicit '|' operator in the Constructor, in\n // which case this can be detected because the two patterns point to the same constructor\n // But the \"or\" can be implied across two constructors that do the same thing. This should\n // probably be flagged as an error except in the following case.\n // 2) Two patterns aren't properly nested, but they are \"resolved\" by a third pattern which\n // covers the intersection of the first two patterns. Sometimes its easier to specify\n // three cases that need to be distinguished in this way.\n // 3) Recursive constructors that use a \"guard\" context bit. The guard bit is used to prevent\n // the recursive constructor from matching repeatedly, but it's too much work to put a\n // constraint an the bit for every other pattern.\n // 4) Other situations where the ability to distinguish between constructors is hidden in\n // the subconstructors.\n // This routine can determine if an intersection results from case 1) or case 2)\n int4 i,j,k;\n vector > newlist;\n vector > conflictlist;\n\n // Check for identical patterns\n for(i=0;iidentical(jpat))\n\tprops.identicalPattern(list[i].second,list[j].second);\n }\n }\n\n newlist = list;\n for(i=0;ispecializes(jpat))\n\tbreak;\n if (!jpat->specializes(ipat)) { // We have a potential conflict\n\tConstructor *iconst = newlist[i].second;\n\tConstructor *jconst = list[j].second;\n\tif (iconst == jconst) { // This is an OR in the pattern for ONE constructor\n\t // So there is no conflict\n\t}\n\telse {\t\t\t// A true conflict that needs to be resolved\n\t conflictlist.push_back(pair(ipat,iconst));\n\t conflictlist.push_back(pair(jpat,jconst));\n\t}\n }\n }\n for(k=i-1;k>=j;--k)\n list[k+1] = list[k];\n list[j] = newlist[i];\n }\n \n // Check if intersection patterns are present, which resolve conflicts\n for(i=0;iresolvesIntersect(pat1,pat2)) {\n\tresolved = true;\n\tbreak;\n }\n }\n if (!resolved)\n props.conflictingPattern(const1,const2);\n }\n}\n\nConstructor *DecisionNode::resolve(ParserWalker &walker) const\n\n{\n if (bitsize == 0) {\t\t// The node is terminal\n vector >::const_iterator iter;\n for(iter=list.begin();iter!=list.end();++iter)\n if ((*iter).first->isMatch(walker))\n\treturn (*iter).second;\n ostringstream s;\n s << walker.getAddr().getShortcut();\n walker.getAddr().printRaw(s);\n s << \": Unable to resolve constructor\";\n throw BadDataError(s.str());\n }\n uintm val;\n if (contextdecision)\n val = walker.getContextBits(startbit,bitsize);\n else\n val = walker.getInstructionBits(startbit,bitsize);\n return children[val]->resolve(walker);\n}\n\nvoid DecisionNode::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_DECISION);\n encoder.writeSignedInteger(sla::ATTRIB_NUMBER, num);\n encoder.writeBool(sla::ATTRIB_CONTEXT, contextdecision);\n encoder.writeSignedInteger(sla::ATTRIB_STARTBIT, startbit);\n encoder.writeSignedInteger(sla::ATTRIB_SIZE, bitsize);\n for(int4 i=0;igetId());\n list[i].first->encode(encoder);\n encoder.closeElement(sla::ELEM_PAIR);\n }\n for(int4 i=0;iencode(encoder);\n encoder.closeElement(sla::ELEM_DECISION);\n}\n\nvoid DecisionNode::decode(Decoder &decoder,DecisionNode *par,SubtableSymbol *sub)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_DECISION);\n parent = par;\n num = decoder.readSignedInteger(sla::ATTRIB_NUMBER);\n contextdecision = decoder.readBool(sla::ATTRIB_CONTEXT);\n startbit = decoder.readSignedInteger(sla::ATTRIB_STARTBIT);\n bitsize = decoder.readSignedInteger(sla::ATTRIB_SIZE);\n uint4 subel = decoder.peekElement();\n while(subel != 0) {\n if (subel == sla::ELEM_PAIR) {\n decoder.openElement();\n uintm id = decoder.readSignedInteger(sla::ATTRIB_ID);\n Constructor *ct = sub->getConstructor(id);\n DisjointPattern *pat = DisjointPattern::decodeDisjoint(decoder);\n list.push_back(pair(pat,ct));\n decoder.closeElement(subel);\n }\n else if (subel == sla::ELEM_DECISION) {\n DecisionNode *subnode = new DecisionNode();\n subnode->decode(decoder,this,sub);\n children.push_back(subnode);\n }\n subel = decoder.peekElement();\n }\n decoder.closeElement(el);\n}\n\nstatic void calc_maskword(int4 sbit,int4 ebit,int4 &num,int4 &shift,uintm &mask)\n\n{\n num = sbit/(8*sizeof(uintm));\n if ( num != ebit/(8*sizeof(uintm)))\n throw SleighError(\"Context field not contained within one machine int\");\n sbit -= num*8*sizeof(uintm);\n ebit -= num*8*sizeof(uintm);\n\n shift = 8*sizeof(uintm)-ebit-1;\n mask = (~((uintm)0))>>(sbit+shift);\n mask <<= shift;\n}\n\nContextOp::ContextOp(int4 startbit,int4 endbit,PatternExpression *pe)\n\n{\n calc_maskword(startbit,endbit,num,shift,mask);\n patexp = pe;\n patexp->layClaim();\n}\n\nvoid ContextOp::apply(ParserWalkerChange &walker) const\n\n{\n uintm val = patexp->getValue(walker); // Get our value based on context\n val <<= shift;\n walker.getParserContext()->setContextWord(num,val,mask);\n}\n\nvoid ContextOp::validate(void) const\n\n{ // Throw an exception if the PatternExpression is not valid\n vector values;\n\n patexp->listValues(values);\t// Get all the expression tokens\n for(int4 i=0;i(values[i]);\n if (val == (const OperandValue *)0) continue;\n // Certain operands cannot be used in context expressions\n // because these are evaluated BEFORE the operand offset\n // has been recovered. If the offset is not relative to\n // the base constructor, then we throw an error\n if (!val->isConstructorRelative())\n throw SleighError(val->getName()+\": cannot be used in context expression\");\n }\n}\n\nvoid ContextOp::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_CONTEXT_OP);\n encoder.writeSignedInteger(sla::ATTRIB_I, num);\n encoder.writeSignedInteger(sla::ATTRIB_SHIFT, shift);\n encoder.writeUnsignedInteger(sla::ATTRIB_MASK, mask);\n patexp->encode(encoder);\n encoder.closeElement(sla::ELEM_CONTEXT_OP);\n}\n\nvoid ContextOp::decode(Decoder &decoder,SleighBase *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_CONTEXT_OP);\n num = decoder.readSignedInteger(sla::ATTRIB_I);\n shift = decoder.readSignedInteger(sla::ATTRIB_SHIFT);\n mask = decoder.readUnsignedInteger(sla::ATTRIB_MASK);\n patexp = PatternExpression::decodeExpression(decoder,trans);\n patexp->layClaim();\n decoder.closeElement(el);\n}\n\nContextChange *ContextOp::clone(void) const\n\n{\n ContextOp *res = new ContextOp();\n (res->patexp = patexp)->layClaim();\n res->mask = mask;\n res->num = num;\n res->shift = shift;\n return res;\n}\n\nContextCommit::ContextCommit(TripleSymbol *s,int4 sbit,int4 ebit,bool fl)\n\n{\n sym = s;\n flow = fl;\n\n int4 shift;\n calc_maskword(sbit,ebit,num,shift,mask);\n}\n\nvoid ContextCommit::apply(ParserWalkerChange &walker) const\n\n{\n walker.getParserContext()->addCommit(sym,num,mask,flow,walker.getPoint());\n}\n\nvoid ContextCommit::encode(Encoder &encoder) const\n\n{\n encoder.openElement(sla::ELEM_COMMIT);\n encoder.writeUnsignedInteger(sla::ATTRIB_ID, sym->getId());\n encoder.writeSignedInteger(sla::ATTRIB_NUMBER, num);\n encoder.writeUnsignedInteger(sla::ATTRIB_MASK, mask);\n encoder.writeBool(sla::ATTRIB_FLOW, flow);\n encoder.closeElement(sla::ELEM_COMMIT);\n}\n\nvoid ContextCommit::decode(Decoder &decoder,SleighBase *trans)\n\n{\n uint4 el = decoder.openElement(sla::ELEM_COMMIT);\n uintm id = decoder.readUnsignedInteger(sla::ATTRIB_ID);\n sym = (TripleSymbol *)trans->findSymbol(id);\n num = decoder.readSignedInteger(sla::ATTRIB_NUMBER);\n mask = decoder.readUnsignedInteger(sla::ATTRIB_MASK);\n flow = decoder.readBool(sla::ATTRIB_FLOW);\n decoder.closeElement(el);\n}\n\nContextChange *ContextCommit::clone(void) const\n\n{\n ContextCommit *res = new ContextCommit();\n res->sym = sym;\n res->flow = flow;\n res->mask = mask;\n res->num = num;\n return res;\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/slghsymbol.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __SLGHSYMBOL_HH__\n#define __SLGHSYMBOL_HH__\n\n#include \"semantics.hh\"\n#include \"slghpatexpress.hh\"\n\nnamespace ghidra {\n\nclass SleighBase;\t\t// Forward declaration\nclass SleighSymbol {\n friend class SymbolTable;\npublic:\n enum symbol_type { space_symbol, token_symbol, userop_symbol, value_symbol, valuemap_symbol,\n\t\t name_symbol, varnode_symbol, varnodelist_symbol, operand_symbol,\n\t\t start_symbol, end_symbol, next2_symbol, subtable_symbol, macro_symbol, section_symbol,\n bitrange_symbol, context_symbol, epsilon_symbol, label_symbol, flowdest_symbol, flowref_symbol,\n\t\t dummy_symbol };\nprivate:\n string name;\n uintm id;\t\t\t// Unique id across all symbols\n uintm scopeid;\t\t// Unique id of scope this symbol is in\npublic:\n SleighSymbol(void) {}\t\t// For use with decode\n SleighSymbol(const string &nm) { name = nm; id = 0; }\n virtual ~SleighSymbol(void) {}\n const string &getName(void) const { return name; }\n uintm getId(void) const { return id; }\n virtual symbol_type getType(void) const { return dummy_symbol; }\n virtual void encodeHeader(Encoder &encoder) const;\n void decodeHeader(Decoder &decoder);\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nstruct SymbolCompare {\n bool operator()(const SleighSymbol *a,const SleighSymbol *b) const {\n return (a->getName() < b->getName()); }\n};\n\ntypedef set SymbolTree;\nclass SymbolScope {\n friend class SymbolTable;\n SymbolScope *parent;\n SymbolTree tree;\n uintm id;\npublic:\n SymbolScope(SymbolScope *p,uintm i) { parent = p; id = i; }\n SymbolScope *getParent(void) const { return parent; }\n SleighSymbol *addSymbol(SleighSymbol *a);\n SleighSymbol *findSymbol(const string &nm) const;\n SymbolTree::const_iterator begin(void) const { return tree.begin(); }\n SymbolTree::const_iterator end(void) const { return tree.end(); }\n uintm getId(void) const { return id; }\n void removeSymbol(SleighSymbol *a) { tree.erase(a); }\n};\n\nclass SymbolTable {\n vector symbollist;\n vector table;\n SymbolScope *curscope;\n SymbolScope *skipScope(int4 i) const;\n SleighSymbol *findSymbolInternal(SymbolScope *scope,const string &nm) const;\n void renumber(void);\npublic:\n SymbolTable(void) { curscope = (SymbolScope *)0; }\n ~SymbolTable(void);\n SymbolScope *getCurrentScope(void) { return curscope; }\n SymbolScope *getGlobalScope(void) { return table[0]; }\n \n void setCurrentScope(SymbolScope *scope) { curscope = scope; }\n void addScope(void);\t\t// Add new scope off of current scope, make it current\n void popScope(void);\t\t// Make parent of current scope current\n void addGlobalSymbol(SleighSymbol *a);\n void addSymbol(SleighSymbol *a);\n SleighSymbol *findSymbol(const string &nm) const { return findSymbolInternal(curscope,nm); }\n SleighSymbol *findSymbol(const string &nm,int4 skip) const { return findSymbolInternal(skipScope(skip),nm); }\n SleighSymbol *findGlobalSymbol(const string &nm) const { return findSymbolInternal(table[0],nm); }\n SleighSymbol *findSymbol(uintm id) const { return symbollist[id]; }\n void replaceSymbol(SleighSymbol *a,SleighSymbol *b);\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder,SleighBase *trans);\n void decodeSymbolHeader(Decoder &decoder);\n void purge(void);\n};\n\nclass SpaceSymbol : public SleighSymbol {\n AddrSpace *space;\npublic:\n SpaceSymbol(AddrSpace *spc) : SleighSymbol(spc->getName()) { space = spc; }\n AddrSpace *getSpace(void) const { return space; }\n virtual symbol_type getType(void) const { return space_symbol; }\n};\n\nclass TokenSymbol : public SleighSymbol {\n Token *tok;\npublic:\n TokenSymbol(Token *t) : SleighSymbol(t->getName()) { tok = t; }\n ~TokenSymbol(void) { delete tok; }\n Token *getToken(void) const { return tok; }\n virtual symbol_type getType(void) const { return token_symbol; }\n};\n\nclass SectionSymbol : public SleighSymbol { // Named p-code sections\n int4 templateid;\t\t// Index into the ConstructTpl array\n int4 define_count;\t\t// Number of definitions of this named section\n int4 ref_count;\t\t// Number of references to this named section\npublic:\n SectionSymbol(const string &nm,int4 id) : SleighSymbol(nm) { templateid=id; define_count=0; ref_count=0; }\n int4 getTemplateId(void) const { return templateid; }\n void incrementDefineCount(void) { define_count += 1; }\n void incrementRefCount(void) { ref_count += 1; }\n int4 getDefineCount(void) const { return define_count; }\n int4 getRefCount(void) const { return ref_count; }\n virtual symbol_type getType(void) const { return section_symbol; }\n};\n\nclass UserOpSymbol : public SleighSymbol { // A user-defined pcode-op\n uint4 index;\npublic:\n UserOpSymbol(void) {}\t\t// For use with decode\n UserOpSymbol(const string &nm) : SleighSymbol(nm) { index = 0; }\n void setIndex(uint4 ind) { index = ind; }\n uint4 getIndex(void) const { return index; }\n virtual symbol_type getType(void) const { return userop_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass Constructor;\t\t// Forward declaration\n// This is the central sleigh object\nclass TripleSymbol : public SleighSymbol {\npublic:\n TripleSymbol(void) {}\n TripleSymbol(const string &nm) : SleighSymbol(nm) {}\n virtual Constructor *resolve(ParserWalker &walker) { return (Constructor *)0; }\n virtual PatternExpression *getPatternExpression(void) const=0;\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const=0;\n virtual int4 getSize(void) const { return 0; }\t// Size out of context\n virtual void print(ostream &s,ParserWalker &walker) const=0;\n virtual void collectLocalValues(vector &results) const {}\n};\n \nclass FamilySymbol : public TripleSymbol {\npublic:\n FamilySymbol(void) {}\n FamilySymbol(const string &nm) : TripleSymbol(nm) {}\n virtual PatternValue *getPatternValue(void) const=0;\n};\n\nclass SpecificSymbol : public TripleSymbol {\npublic:\n SpecificSymbol(void) {}\n SpecificSymbol(const string &nm) : TripleSymbol(nm) {}\n virtual VarnodeTpl *getVarnode(void) const=0;\n};\n\nclass PatternlessSymbol : public SpecificSymbol { // Behaves like constant 0 pattern\n ConstantValue *patexp;\npublic:\n PatternlessSymbol(void);\t// For use with decode\n PatternlessSymbol(const string &nm);\n virtual ~PatternlessSymbol(void);\n virtual PatternExpression *getPatternExpression(void) const { return patexp; }\n};\n\nclass EpsilonSymbol : public PatternlessSymbol { // Another name for zero pattern/value\n AddrSpace *const_space;\npublic:\n EpsilonSymbol(void) {}\t// For use with decode\n EpsilonSymbol(const string &nm,AddrSpace *spc) : PatternlessSymbol(nm) { const_space=spc; }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return epsilon_symbol; }\n virtual VarnodeTpl *getVarnode(void) const;\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass ValueSymbol : public FamilySymbol {\nprotected:\n PatternValue *patval;\npublic:\n ValueSymbol(void) { patval = (PatternValue *)0; } // For use with decode\n ValueSymbol(const string &nm,PatternValue *pv);\n virtual ~ValueSymbol(void);\n virtual PatternValue *getPatternValue(void) const { return patval; }\n virtual PatternExpression *getPatternExpression(void) const { return patval; }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return value_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass ValueMapSymbol : public ValueSymbol {\n vector valuetable;\n bool tableisfilled;\n void checkTableFill(void);\npublic:\n ValueMapSymbol(void) {}\t// For use with decode\n ValueMapSymbol(const string &nm,PatternValue *pv,const vector &vt) : ValueSymbol(nm,pv) { valuetable=vt; checkTableFill(); }\n virtual Constructor *resolve(ParserWalker &walker);\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return valuemap_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass NameSymbol : public ValueSymbol {\n vector nametable;\n bool tableisfilled;\n void checkTableFill(void);\npublic:\n NameSymbol(void) {}\t\t// For use with decode\n NameSymbol(const string &nm,PatternValue *pv,const vector &nt) : ValueSymbol(nm,pv) { nametable=nt; checkTableFill(); }\n virtual Constructor *resolve(ParserWalker &walker);\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return name_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass VarnodeSymbol : public PatternlessSymbol { // A global varnode\n VarnodeData fix;\n bool context_bits;\npublic:\n VarnodeSymbol(void) {}\t// For use with decode\n VarnodeSymbol(const string &nm,AddrSpace *base,uintb offset,int4 size);\n void markAsContext(void) { context_bits = true; }\n const VarnodeData &getFixedVarnode(void) const { return fix; }\n virtual VarnodeTpl *getVarnode(void) const;\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual int4 getSize(void) const { return fix.size; }\n virtual void print(ostream &s,ParserWalker &walker) const {\n s << getName(); }\n virtual void collectLocalValues(vector &results) const;\n virtual symbol_type getType(void) const { return varnode_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass BitrangeSymbol : public SleighSymbol { // A smaller bitrange within a varnode\n VarnodeSymbol *varsym;\t// Varnode containing the bitrange\n uint4 bitoffset;\t\t// least significant bit of range\n uint4 numbits;\t\t// number of bits in the range\npublic:\n BitrangeSymbol(void) {}\t// For use with decode\n BitrangeSymbol(const string &nm,VarnodeSymbol *sym,uint4 bitoff,uint4 num)\n : SleighSymbol(nm) { varsym=sym; bitoffset=bitoff; numbits=num; }\n VarnodeSymbol *getParentSymbol(void) const { return varsym; }\n uint4 getBitOffset(void) const { return bitoffset; }\n uint4 numBits(void) const { return numbits; }\n virtual symbol_type getType(void) const { return bitrange_symbol; }\n};\n\nclass ContextSymbol : public ValueSymbol {\n VarnodeSymbol *vn;\n uint4 low,high;\t\t// into a varnode\n bool flow;\npublic:\n ContextSymbol(void) {}\t// For use with decode\n ContextSymbol(const string &nm,ContextField *pate,VarnodeSymbol *v,uint4 l,uint4 h,bool flow);\n VarnodeSymbol *getVarnode(void) const { return vn; }\n uint4 getLow(void) const { return low; }\n uint4 getHigh(void) const { return high; }\n bool getFlow(void) const { return flow; }\n virtual symbol_type getType(void) const { return context_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass VarnodeListSymbol : public ValueSymbol {\n vector varnode_table;\n bool tableisfilled;\n void checkTableFill(void);\npublic:\n VarnodeListSymbol(void) {}\t// For use with decode\n VarnodeListSymbol(const string &nm,PatternValue *pv,const vector &vt); \n virtual Constructor *resolve(ParserWalker &walker);\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual int4 getSize(void) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return varnodelist_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n \nclass OperandSymbol : public SpecificSymbol {\n friend class Constructor;\n friend class OperandEquation;\npublic:\n enum { code_address=1, offset_irrel=2, variable_len=4, marked=8 };\nprivate:\n uint4 reloffset;\t\t// Relative offset\n int4 offsetbase;\t\t// Base operand to which offset is relative (-1=constructor start)\n int4 minimumlength;\t\t// Minimum size of operand (within instruction tokens)\n int4 hand;\t\t\t// Handle index\n OperandValue *localexp;\n TripleSymbol *triple;\t\t// Defining symbol\n PatternExpression *defexp;\t// OR defining expression\n uint4 flags;\n void setVariableLength(void) { flags |= variable_len; }\n bool isVariableLength(void) const { return ((flags&variable_len)!=0); }\npublic:\n OperandSymbol(void) {}\t// For use with decode\n OperandSymbol(const string &nm,int4 index,Constructor *ct);\n uint4 getRelativeOffset(void) const { return reloffset; }\n int4 getOffsetBase(void) const { return offsetbase; }\n int4 getMinimumLength(void) const { return minimumlength; }\n PatternExpression *getDefiningExpression(void) const { return defexp; }\n TripleSymbol *getDefiningSymbol(void) const { return triple; }\n int4 getIndex(void) const { return hand; }\n void defineOperand(PatternExpression *pe);\n void defineOperand(TripleSymbol *tri);\n void setCodeAddress(void) { flags |= code_address; }\n bool isCodeAddress(void) const { return ((flags&code_address)!=0); }\n void setOffsetIrrelevant(void) { flags |= offset_irrel; }\n bool isOffsetIrrelevant(void) const { return ((flags&offset_irrel)!=0); }\n void setMark(void) { flags |= marked; }\n void clearMark(void) { flags &= ~((uint4)marked); }\n bool isMarked(void) const { return ((flags&marked)!=0); }\n virtual ~OperandSymbol(void);\n virtual VarnodeTpl *getVarnode(void) const;\n virtual PatternExpression *getPatternExpression(void) const { return localexp; }\n virtual void getFixedHandle(FixedHandle &hnd,ParserWalker &walker) const;\n virtual int4 getSize(void) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual void collectLocalValues(vector &results) const;\n virtual symbol_type getType(void) const { return operand_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass StartSymbol : public SpecificSymbol {\n AddrSpace *const_space;\n PatternExpression *patexp;\npublic:\n StartSymbol(void) { patexp = (PatternExpression *)0; } // For use with decode\n StartSymbol(const string &nm,AddrSpace *cspc);\n virtual ~StartSymbol(void);\n virtual VarnodeTpl *getVarnode(void) const;\n virtual PatternExpression *getPatternExpression(void) const { return patexp; }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return start_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass EndSymbol : public SpecificSymbol {\n AddrSpace *const_space;\n PatternExpression *patexp;\npublic:\n EndSymbol(void) { patexp = (PatternExpression *)0; } // For use with decode\n EndSymbol(const string &nm,AddrSpace *cspc);\n virtual ~EndSymbol(void);\n virtual VarnodeTpl *getVarnode(void) const;\n virtual PatternExpression *getPatternExpression(void) const { return patexp; }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return end_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass Next2Symbol : public SpecificSymbol {\n AddrSpace *const_space;\n PatternExpression *patexp;\npublic:\n Next2Symbol(void) { patexp = (PatternExpression *)0; } // For use with decode\n Next2Symbol(const string &nm,AddrSpace *cspc);\n virtual ~Next2Symbol(void);\n virtual VarnodeTpl *getVarnode(void) const;\n virtual PatternExpression *getPatternExpression(void) const { return patexp; }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return next2_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass FlowDestSymbol : public SpecificSymbol {\n AddrSpace *const_space;\npublic:\n FlowDestSymbol(void) {}\t// For use with decode\n FlowDestSymbol(const string &nm,AddrSpace *cspc);\n virtual VarnodeTpl *getVarnode(void) const;\n virtual PatternExpression *getPatternExpression(void) const { throw SleighError(\"Cannot use symbol in pattern\"); }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return flowdest_symbol; }\n};\n\nclass FlowRefSymbol : public SpecificSymbol {\n AddrSpace *const_space;\npublic:\n FlowRefSymbol(void) {}\t// For use with decode\n FlowRefSymbol(const string &nm,AddrSpace *cspc);\n virtual VarnodeTpl *getVarnode(void) const;\n virtual PatternExpression *getPatternExpression(void) const { throw SleighError(\"Cannot use symbol in pattern\"); }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const;\n virtual void print(ostream &s,ParserWalker &walker) const;\n virtual symbol_type getType(void) const { return flowref_symbol; }\n};\n\nclass ContextChange {\t\t// Change to context command\npublic:\n virtual ~ContextChange(void) {}\n virtual void validate(void) const=0;\n virtual void encode(Encoder &encoder) const=0;\n virtual void decode(Decoder &decoder,SleighBase *trans)=0;\n virtual void apply(ParserWalkerChange &walker) const=0;\n virtual ContextChange *clone(void) const=0;\n};\n\nclass ContextOp : public ContextChange {\n PatternExpression *patexp;\t// Expression determining value\n int4 num;\t\t\t// index of word containing context variable to set\n uintm mask;\t\t\t// Mask off size of variable\n int4 shift;\t\t\t// Number of bits to shift value into place\npublic:\n ContextOp(int4 startbit,int4 endbit,PatternExpression *pe);\n ContextOp(void) {}\t\t// For use with decode\n virtual ~ContextOp(void) { PatternExpression::release(patexp); }\n virtual void validate(void) const;\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n virtual void apply(ParserWalkerChange &walker) const;\n virtual ContextChange *clone(void) const;\n};\n\nclass ContextCommit : public ContextChange {\n TripleSymbol *sym;\n int4 num;\t\t\t// Index of word containing context commit\n uintm mask;\t\t\t// mask of bits in word being committed\n bool flow;\t\t\t// Whether the context \"flows\" from the point of change\npublic:\n ContextCommit(void) {}\t// For use with decode\n ContextCommit(TripleSymbol *s,int4 sbit,int4 ebit,bool fl);\n virtual void validate(void) const {}\n virtual void encode(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n virtual void apply(ParserWalkerChange &walker) const;\n virtual ContextChange *clone(void) const;\n};\n\nclass SubtableSymbol;\nclass Constructor {\t\t// This is NOT a symbol\n TokenPattern *pattern;\n SubtableSymbol *parent;\n PatternEquation *pateq;\n vector operands;\n vector printpiece;\n vector context; // Context commands\n ConstructTpl *templ;\t\t// The main p-code section\n vector namedtempl; // Other named p-code sections\n int4 minimumlength;\t\t// Minimum length taken up by this constructor in bytes\n uintm id;\t\t\t// Unique id of constructor within subtable\n int4 firstwhitespace;\t\t// Index of first whitespace piece in -printpiece-\n int4 flowthruindex;\t\t// if >=0 then print only a single operand no markup\n int4 lineno;\n int4 src_index; //source file index\n mutable bool inerror; // An error is associated with this Constructor\n void orderOperands(void);\npublic:\n Constructor(void);\t\t// For use with decode\n Constructor(SubtableSymbol *p);\n ~Constructor(void);\n TokenPattern *buildPattern(ostream &s);\n TokenPattern *getPattern(void) const { return pattern; }\n void setMinimumLength(int4 l) { minimumlength = l; }\n int4 getMinimumLength(void) const { return minimumlength; }\n void setId(uintm i) { id = i; }\n uintm getId(void) const { return id; }\n void setLineno(int4 ln) { lineno = ln; }\n int4 getLineno(void) const { return lineno; }\n void setSrcIndex(int4 index) {src_index = index;}\n int4 getSrcIndex(void) {return src_index;}\n void addContext(const vector &vec) { context = vec; }\n void addOperand(OperandSymbol *sym);\n void addInvisibleOperand(OperandSymbol *sym);\n void addSyntax(const string &syn);\n void addEquation(PatternEquation *pe);\n void setMainSection(ConstructTpl *tpl) { templ = tpl; }\n void setNamedSection(ConstructTpl *tpl,int4 id);\n SubtableSymbol *getParent(void) const { return parent; }\n int4 getNumOperands(void) const { return operands.size(); }\n OperandSymbol *getOperand(int4 i) const { return operands[i]; }\n PatternEquation *getPatternEquation(void) const { return pateq; }\n ConstructTpl *getTempl(void) const { return templ; }\n ConstructTpl *getNamedTempl(int4 secnum) const;\n int4 getNumSections(void) const { return namedtempl.size(); }\n void printInfo(ostream &s) const;\n void print(ostream &s,ParserWalker &pos) const;\n void printMnemonic(ostream &s,ParserWalker &walker) const;\n void printBody(ostream &s,ParserWalker &walker) const;\n void removeTrailingSpace(void);\n void applyContext(ParserWalkerChange &walker) const {\n vector::const_iterator iter;\n for(iter=context.begin();iter!=context.end();++iter)\n (*iter)->apply(walker);\n }\n void markSubtableOperands(vector &check) const;\n void collectLocalExports(vector &results) const;\n void setError(bool val) const { inerror = val; }\n bool isError(void) const { return inerror; }\n bool isRecursive(void) const;\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass DecisionProperties {\n vector > identerrors;\n vector > conflicterrors;\npublic:\n void identicalPattern(Constructor *a,Constructor *b);\n void conflictingPattern(Constructor *a,Constructor *b);\n const vector > &getIdentErrors(void) const { return identerrors; }\n const vector > &getConflictErrors(void) const { return conflicterrors; }\n};\n\nclass DecisionNode {\n vector > list;\n vector children;\n int4 num;\t\t\t// Total number of patterns we distinguish\n bool contextdecision;\t\t// True if this is decision based on context\n int4 startbit,bitsize; // Bits in the stream on which to base the decision\n DecisionNode *parent;\n void chooseOptimalField(void);\n double getScore(int4 low,int4 size,bool context);\n int4 getNumFixed(int4 low,int4 size,bool context);\n int4 getMaximumLength(bool context);\n void consistentValues(vector &bins,DisjointPattern *pat);\npublic:\n DecisionNode(void) {}\t\t// For use with decode\n DecisionNode(DecisionNode *p);\n ~DecisionNode(void);\n Constructor *resolve(ParserWalker &walker) const;\n void addConstructorPair(const DisjointPattern *pat,Constructor *ct);\n void split(DecisionProperties &props);\n void orderPatterns(DecisionProperties &props);\n void encode(Encoder &encoder) const;\n void decode(Decoder &decoder,DecisionNode *par,SubtableSymbol *sub);\n};\n\nclass SubtableSymbol : public TripleSymbol {\n TokenPattern *pattern;\n bool beingbuilt,errors;\n vector construct; // All the Constructors in this table\n DecisionNode *decisiontree;\npublic:\n SubtableSymbol(void) { pattern = (TokenPattern *)0; decisiontree = (DecisionNode *)0; } // For use with decode\n SubtableSymbol(const string &nm);\n virtual ~SubtableSymbol(void);\n bool isBeingBuilt(void) const { return beingbuilt; }\n bool isError(void) const { return errors; }\n void addConstructor(Constructor *ct) { ct->setId(construct.size()); construct.push_back(ct); }\n void buildDecisionTree(DecisionProperties &props);\n TokenPattern *buildPattern(ostream &s);\n TokenPattern *getPattern(void) const { return pattern; }\n int4 getNumConstructors(void) const { return construct.size(); }\n Constructor *getConstructor(uintm id) const { return construct[id]; }\n virtual Constructor *resolve(ParserWalker &walker) { return decisiontree->resolve(walker); }\n virtual PatternExpression *getPatternExpression(void) const { throw SleighError(\"Cannot use subtable in expression\"); }\n virtual void getFixedHandle(FixedHandle &hand,ParserWalker &walker) const {\n throw SleighError(\"Cannot use subtable in expression\"); }\n virtual int4 getSize(void) const { return -1; }\n virtual void print(ostream &s,ParserWalker &walker) const {\n throw SleighError(\"Cannot use subtable in expression\"); }\n virtual void collectLocalValues(vector &results) const;\n virtual symbol_type getType(void) const { return subtable_symbol; }\n virtual void encode(Encoder &encoder) const;\n virtual void encodeHeader(Encoder &encoder) const;\n virtual void decode(Decoder &decoder,SleighBase *trans);\n};\n\nclass MacroSymbol : public SleighSymbol { // A user-defined pcode-macro\n int4 index;\n ConstructTpl *construct;\n vector operands;\npublic:\n MacroSymbol(const string &nm,int4 i) : SleighSymbol(nm) { index = i; construct = (ConstructTpl *)0; }\n int4 getIndex(void) const { return index; }\n void setConstruct(ConstructTpl *ct) { construct = ct; }\n ConstructTpl *getConstruct(void) const { return construct; }\n void addOperand(OperandSymbol *sym) { operands.push_back(sym); }\n int4 getNumOperands(void) const { return operands.size(); }\n OperandSymbol *getOperand(int4 i) const { return operands[i]; }\n virtual ~MacroSymbol(void) { if (construct != (ConstructTpl *)0) delete construct; }\n virtual symbol_type getType(void) const { return macro_symbol; }\n};\n\nclass LabelSymbol : public SleighSymbol { // A branch label\n uint4 index;\t\t\t// Local 1 up index of label\n bool isplaced;\t\t// Has the label been placed (not just referenced)\n uint4 refcount;\t\t// Number of references to this label\npublic:\n LabelSymbol(const string &nm,uint4 i) : SleighSymbol(nm) { index = i; refcount = 0; isplaced=false; }\n uint4 getIndex(void) const { return index; }\n void incrementRefCount(void) { refcount += 1; }\n uint4 getRefCount(void) const { return refcount; }\n void setPlaced(void) { isplaced = true; }\n bool isPlaced(void) const { return isplaced; }\n virtual symbol_type getType(void) const { return label_symbol; }\n};\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/space.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"space.hh\"\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nAttributeId ATTRIB_BASE = AttributeId(\"base\",89);\nAttributeId ATTRIB_DEADCODEDELAY = AttributeId(\"deadcodedelay\",90);\nAttributeId ATTRIB_DELAY = AttributeId(\"delay\", 91);\nAttributeId ATTRIB_LOGICALSIZE = AttributeId(\"logicalsize\",92);\nAttributeId ATTRIB_PHYSICAL = AttributeId(\"physical\",93);\n\n// ATTRIB_PIECE is a special attribute for supporting the legacy attributes \"piece1\", \"piece2\", ..., \"piece9\",\n// It is effectively a sequence of indexed attributes for use with Encoder::writeStringIndexed.\n// The index starts at the ids reserved for \"piece1\" thru \"piece9\" but can extend farther.\nAttributeId ATTRIB_PIECE = AttributeId(\"piece\",94);\t// Open slots 94-102\n\n/// Calculate \\e highest based on \\e addressSize, and \\e wordsize.\n/// This also calculates the default pointerLowerBound\nvoid AddrSpace::calcScaleMask(void)\n\n{\n highest = calc_mask(addressSize); // Maximum address\n highest = highest * wordsize + (wordsize-1); // Maximum byte address\n pointerLowerBound = 0;\n pointerUpperBound = highest;\n uintb bufferSize = (addressSize < 3) ? 0x100 : 0x1000;\n pointerLowerBound += bufferSize;\n pointerUpperBound -= bufferSize;\n}\n\n/// Initialize an address space with its basic attributes\n/// \\param m is the space manager associated with the new space\n/// \\param t is the processor translator associated with the new space\n/// \\param tp is the type of the new space (PROCESSOR, CONSTANT, INTERNAL,...)\n/// \\param nm is the name of the new space\n/// \\param bigEnd is \\b true for big endian encoding\n/// \\param size is the (offset encoding) size of the new space\n/// \\param ws is the number of bytes in an addressable unit\n/// \\param ind is the integer identifier for the new space\n/// \\param fl can be 0 or AddrSpace::hasphysical\n/// \\param dl is the number of rounds to delay heritage for the new space\n/// \\param dead is the number of rounds to delay before dead code removal\nAddrSpace::AddrSpace(AddrSpaceManager *m,const Translate *t,spacetype tp,const string &nm,bool bigEnd,\n\t\t uint4 size,uint4 ws, int4 ind,uint4 fl,int4 dl,int4 dead)\n{\n refcount = 0;\t\t\t// No references to this space yet\n manage = m;\n trans = t;\n type = tp;\n name = nm;\n addressSize = size;\n wordsize = ws;\n index = ind;\n delay = dl;\n deadcodedelay = dead;\n minimumPointerSize = 0;\t// (initially) assume pointers must match the space size exactly\n shortcut = ' ';\t\t// Placeholder meaning shortcut is unassigned\n\n // These are the flags we allow to be set from constructor\n flags = (fl & hasphysical);\n if (bigEnd)\n flags |= big_endian;\n flags |= (heritaged | does_deadcode);\t\t// Always on unless explicitly turned off in derived constructor\n \n calcScaleMask();\n}\n\n/// This is a partial constructor, for initializing a space\n/// via XML\n/// \\param m the associated address space manager\n/// \\param t is the processor translator\n/// \\param tp the basic type of the space\nAddrSpace::AddrSpace(AddrSpaceManager *m,const Translate *t,spacetype tp)\n\n{\n refcount = 0;\n manage = m;\n trans = t;\n type = tp;\n flags = (heritaged | does_deadcode);\t\t// Always on unless explicitly turned off in derived constructor\n wordsize = 1;\n minimumPointerSize = 0;\n shortcut = ' ';\n // We let big_endian get set by attribute\n}\n\n/// The logical form of the space is truncated from its actual size\n/// Pointers may refer to this original size put the most significant bytes are ignored\n/// \\param newsize is the size (in bytes) of the truncated (logical) space\nvoid AddrSpace::truncateSpace(uint4 newsize)\n\n{\n setFlags(truncated);\n addressSize = newsize;\n minimumPointerSize = newsize;\n calcScaleMask();\n}\n\n/// \\brief Determine if a given point is contained in an address range in \\b this address space\n///\n/// The point is specified as an address space and offset pair plus an additional number of bytes to \"skip\".\n/// A non-negative value is returned if the point falls in the address range.\n/// If the point falls on the first byte of the range, 0 is returned. For the second byte, 1 is returned, etc.\n/// Otherwise -1 is returned.\n/// \\param offset is the starting offset of the address range within \\b this space\n/// \\param size is the size of the address range in bytes\n/// \\param pointSpace is the address space of the given point\n/// \\param pointOff is the offset of the given point\n/// \\param pointSkip is the additional bytes to skip\n/// \\return a non-negative value indicating where the point falls in the range, or -1\nint4 AddrSpace::overlapJoin(uintb offset,int4 size,AddrSpace *pointSpace,uintb pointOff,int4 pointSkip) const\n\n{\n if (this != pointSpace)\n return -1;\n\n uintb dist = wrapOffset(pointOff+pointSkip-offset);\n\n if (dist >= size) return -1; // but must fall before op+size\n return (int4) dist;\n}\n\n/// Write the main attributes for an address within \\b this space.\n/// The caller provides only the \\e offset, and this routine fills\n/// in other details pertaining to this particular space.\n/// \\param encoder is the stream encoder\n/// \\param offset is the offset of the address\nvoid AddrSpace::encodeAttributes(Encoder &encoder,uintb offset) const\n\n{\n encoder.writeSpace(ATTRIB_SPACE,this);\n encoder.writeUnsignedInteger(ATTRIB_OFFSET, offset);\n}\n\n/// Write the main attributes of an address with \\b this space\n/// and a size. The caller provides the \\e offset and \\e size,\n/// and other details about this particular space are filled in.\n/// \\param encoder is the stream encoder\n/// \\param offset is the offset of the address\n/// \\param size is the size of the memory location\nvoid AddrSpace::encodeAttributes(Encoder &encoder,uintb offset,int4 size) const\n\n{\n encoder.writeSpace(ATTRIB_SPACE, this);\n encoder.writeUnsignedInteger(ATTRIB_OFFSET, offset);\n encoder.writeSignedInteger(ATTRIB_SIZE, size);\n}\n\n/// For an open element describing an address in \\b this space, this routine\n/// recovers the offset and possibly the size described by the element\n/// \\param decoder is the stream decoder\n/// \\param size is a reference where the recovered size should be stored\n/// \\return the recovered offset\nuintb AddrSpace::decodeAttributes(Decoder &decoder,uint4 &size) const\n\n{\n uintb offset;\n bool foundoffset = false;\n for(;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == ATTRIB_OFFSET) {\n foundoffset = true;\n offset = decoder.readUnsignedInteger();\n }\n else if (attribId == ATTRIB_SIZE) {\n size = decoder.readSignedInteger();\n }\n }\n if (!foundoffset)\n throw LowlevelError(\"Address is missing offset\");\n\n return offset;\n}\n\n/// Print the \\e offset as hexidecimal digits.\n/// \\param s is the stream to write to\n/// \\param offset is the offset to be printed\nvoid AddrSpace::printOffset(ostream &s,uintb offset) const\n\n{\n s << \"0x\" << hex << offset;\n}\n\n/// This is a printing method for the debugging routines. It\n/// prints taking into account the \\e wordsize, adding a\n/// \"+n\" if the offset is not on-cut with wordsize. It also\n/// returns the expected/typical size of values from this space.\n/// \\param s is the stream being written\n/// \\param offset is the offset to be printed\nvoid AddrSpace::printRaw(ostream &s,uintb offset) const\n\n{\n int4 sz = getAddrSize();\n if (sz > 4) {\n if ((offset>>32) == 0)\n sz = 4;\t\t\t// Don't print a bunch of zeroes at front of address\n else if ((offset>>48) == 0)\n sz = 6;\n }\n s << \"0x\" << setfill('0') << setw(2*sz) << hex << byteToAddress(offset,wordsize);\n if (wordsize>1) {\n int4 cut = offset % wordsize;\n if (cut != 0)\n s << '+' << dec << cut;\n }\n}\n\nstatic int4 get_offset_size(const char *ptr,uintb &offset)\n\n{\t\t\t\t// Get optional size and offset fields from string\n int4 size;\n uint4 val;\n char *ptr2;\n\n val = 0;\t\t\t// Defaults\n size = -1;\n if (*ptr == ':') {\n size = strtoul(ptr+1,&ptr2,0);\n if (*ptr2 == '+')\n val = strtoul(ptr2+1,&ptr2,0);\n }\n if (*ptr == '+')\n val = strtoul(ptr+1,&ptr2,0);\n\n offset += val;\t\t// Adjust offset\n return size;\n}\n\n/// For the console mode, an address space can tailor how it\n/// converts user strings into offsets within the space. The\n/// base routine can read and convert register names as well\n/// as absolute hex addresses. A size can be indicated by\n/// appending a ':' and integer, .i.e. 0x1000:2. Offsets within\n/// a register can be indicated by appending a '+' and integer,\n/// i.e. eax+2\n/// \\param s is the string to be parsed\n/// \\param size is a reference to the size being returned\n/// \\return the parsed offset\nuintb AddrSpace::read(const string &s,int4 &size) const\n\n{\n const char *enddata;\n char *tmpdata;\n int4 expsize;\n string::size_type append;\n string frontpart;\n uintb offset;\n \n append = s.find_first_of(\":+\");\n try {\n if (append == string::npos) {\n const VarnodeData &point(trans->getRegister(s));\n offset = point.offset;\n size = point.size;\n }\n else {\n frontpart = s.substr(0,append);\n const VarnodeData &point(trans->getRegister(frontpart));\n offset = point.offset;\n size = point.size;\n }\n }\n catch(LowlevelError &err) {\t// Name doesn't exist\n offset = strtoul(s.c_str(),&tmpdata,0);\n offset = addressToByte(offset,wordsize);\n enddata = (const char *) tmpdata;\n if (enddata - s.c_str() == s.size()) { // If no size or offset override\n size = manage->getDefaultSize();\t// Return \"natural\" size\n return offset;\n }\n size = manage->getDefaultSize();\n }\n if (append != string::npos) {\n enddata = s.c_str()+append;\n expsize = get_offset_size( enddata, offset );\n if (expsize!=-1) {\n size = expsize;\n return offset;\n }\n }\n return offset;\n}\n\n/// Walk attributes of the current element and recover all the properties defining\n/// this space. The processor translator, \\e trans, and the\n/// \\e type must already be filled in.\n/// \\param decoder is the stream decoder\nvoid AddrSpace::decodeBasicAttributes(Decoder &decoder)\n\n{\n deadcodedelay = -1;\n for (;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == ATTRIB_NAME) {\n name = decoder.readString();\n }\n if (attribId == ATTRIB_INDEX)\n index = decoder.readSignedInteger();\n else if (attribId == ATTRIB_SIZE)\n addressSize = decoder.readSignedInteger();\n else if (attribId == ATTRIB_WORDSIZE)\n wordsize = decoder.readUnsignedInteger();\n else if (attribId == ATTRIB_BIGENDIAN) {\n if (decoder.readBool())\n\tflags |= big_endian;\n }\n else if (attribId == ATTRIB_DELAY)\n delay = decoder.readSignedInteger();\n else if (attribId == ATTRIB_DEADCODEDELAY)\n deadcodedelay = decoder.readSignedInteger();\n else if (attribId == ATTRIB_PHYSICAL) {\n if (decoder.readBool())\n\tflags |= hasphysical;\n }\n \n }\n if (deadcodedelay == -1)\n deadcodedelay = delay;\t// If deadcodedelay attribute not present, set it to delay\n calcScaleMask();\n}\n\nvoid AddrSpace::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement();\t\t// Multiple tags: , , \n decodeBasicAttributes(decoder);\n decoder.closeElement(elemId);\n}\n\nconst string ConstantSpace::NAME = \"const\";\n\nconst int4 ConstantSpace::INDEX = 0;\n\n/// This constructs the unique constant space\n/// By convention, the name is always \"const\" and the index\n/// is always 0.\n/// \\param m is the associated address space manager\n/// \\param t is the associated processor translator\nConstantSpace::ConstantSpace(AddrSpaceManager *m,const Translate *t)\n : AddrSpace(m,t,IPTR_CONSTANT,NAME,false,sizeof(uintb),1,INDEX,0,0,0)\n{\n clearFlags(heritaged|does_deadcode|big_endian);\n if (HOST_ENDIAN==1)\t\t// Endianness always matches host\n setFlags(big_endian);\n}\n\nint4 ConstantSpace::overlapJoin(uintb offset,int4 size,AddrSpace *pointSpace,uintb pointOff,int4 pointSkip) const\n\n{\n return -1;\n}\n\n/// Constants are always printed as hexidecimal values in\n/// the debugger and console dumps\nvoid ConstantSpace::printRaw(ostream &s,uintb offset) const\n\n{\n s << \"0x\" << hex << offset;\n}\n\n/// As the ConstantSpace is never saved, it should never get\n/// decoded either.\nvoid ConstantSpace::decode(Decoder &decoder)\n\n{\n throw LowlevelError(\"Should never decode the constant space\");\n}\n\nconst string OtherSpace::NAME = \"OTHER\";\n\nconst int4 OtherSpace::INDEX = 1;\n\n/// Construct the \\b other space, which is automatically constructed\n/// by the compiler, and is only constructed once. The name should\n/// always by \\b OTHER.\n/// \\param m is the associated address space manager\n/// \\param t is the associated processor translator\n/// \\param ind is the integer identifier\nOtherSpace::OtherSpace(AddrSpaceManager *m,const Translate *t,int4 ind)\n : AddrSpace(m,t,IPTR_PROCESSOR,NAME,false,sizeof(uintb),1,INDEX,0,0,0)\n{\n clearFlags(heritaged|does_deadcode);\n setFlags(is_otherspace);\n}\n\nOtherSpace::OtherSpace(AddrSpaceManager *m,const Translate *t)\n : AddrSpace(m,t,IPTR_PROCESSOR)\n{\n clearFlags(heritaged|does_deadcode);\n setFlags(is_otherspace);\n}\n\nvoid OtherSpace::printRaw(ostream &s,uintb offset) const\n\n{\n s << \"0x\" << hex << offset;\n}\n\nconst string UniqueSpace::NAME = \"unique\";\n\nconst uint4 UniqueSpace::SIZE = 4;\n\n/// This is the constructor for the \\b unique space, which is\n/// automatically constructed by the analysis engine, and\n/// constructed only once. The name should always be \\b unique.\n/// \\param m is the associated address space manager\n/// \\param t is the associated processor translator\n/// \\param ind is the integer identifier\n/// \\param fl are attribute flags (currently unused)\nUniqueSpace::UniqueSpace(AddrSpaceManager *m,const Translate *t,int4 ind,uint4 fl)\n : AddrSpace(m,t,IPTR_INTERNAL,NAME,t->isBigEndian(),SIZE,1,ind,fl,0,0)\n{\n setFlags(hasphysical);\n}\n\nUniqueSpace::UniqueSpace(AddrSpaceManager *m,const Translate *t)\n : AddrSpace(m,t,IPTR_INTERNAL)\n{\n setFlags(hasphysical);\n}\n\nconst string JoinSpace::NAME = \"join\";\n\n/// This is the constructor for the \\b join space, which is automatically constructed by the\n/// analysis engine, and constructed only once. The name should always be \\b join.\n/// \\param m is the associated address space manager\n/// \\param t is the associated processor translator\n/// \\param ind is the integer identifier\nJoinSpace::JoinSpace(AddrSpaceManager *m,const Translate *t,int4 ind)\n : AddrSpace(m,t,IPTR_JOIN,NAME,t->isBigEndian(),sizeof(uintm),1,ind,0,0,0)\n{\n // This is a virtual space\n // setFlags(hasphysical);\n clearFlags(heritaged); // This space is never heritaged, but does dead-code analysis\n}\n\nint4 JoinSpace::overlapJoin(uintb offset,int4 size,AddrSpace *pointSpace,uintb pointOffset,int4 pointSkip) const\n\n{\n if (this == pointSpace) {\n // If the point is in the join space, translate the point into the piece address space\n JoinRecord *pieceRecord = getManager()->findJoin(pointOffset);\n int4 pos;\n Address addr = pieceRecord->getEquivalentAddress(pointOffset + pointSkip, pos);\n pointSpace = addr.getSpace();\n pointOffset = addr.getOffset();\n }\n else {\n if (pointSpace->getType() == IPTR_CONSTANT)\n return -1;\n pointOffset = pointSpace->wrapOffset(pointOffset + pointSkip);\n }\n JoinRecord *joinRecord = getManager()->findJoin(offset);\n // Set up so we traverse pieces in data order\n int4 startPiece,endPiece,dir;\n if (isBigEndian()) {\n startPiece = 0;\n endPiece = joinRecord->numPieces();\n dir = 1;\n }\n else {\n startPiece = joinRecord->numPieces() - 1;\n endPiece = -1;\n dir = -1;\n }\n int4 bytesAccum = 0;\n for(int4 i=startPiece;i!=endPiece;i += dir) {\n const VarnodeData &vData(joinRecord->getPiece(i));\n if (vData.space == pointSpace && pointOffset >= vData.offset && pointOffset <= vData.offset + (vData.size-1)) {\n int4 res = (int4)(pointOffset - vData.offset) + bytesAccum;\n if (res >= size)\n\treturn -1;\n return res;\n }\n bytesAccum += vData.size;\n }\n return -1;\n}\n\n/// Encode a \\e join address to the stream. This method in the interface only\n/// outputs attributes for a single element, so we are forced to encode what should probably\n/// be recursive elements into an attribute.\n/// \\param encoder is the stream encoder\n/// \\param offset is the offset within the address space to encode\nvoid JoinSpace::encodeAttributes(Encoder &encoder,uintb offset) const\n\n{\n JoinRecord *rec = getManager()->findJoin(offset); // Record must already exist\n encoder.writeSpace(ATTRIB_SPACE, this);\n int4 num = rec->numPieces();\n if (num > MAX_PIECES)\n throw LowlevelError(\"Exceeded maximum pieces in one join address\");\n for(int4 i=0;igetPiece(i) );\n ostringstream t;\n t << vdata.space->getName() << \":0x\";\n t << hex << vdata.offset << ':' << dec << vdata.size;\n encoder.writeStringIndexed(ATTRIB_PIECE, i, t.str());\n }\n if (num == 1)\n encoder.writeUnsignedInteger(ATTRIB_LOGICALSIZE, rec->getUnified().size);\n}\n\n/// Encode a \\e join address to the stream. This method in the interface only\n/// outputs attributes for a single element, so we are forced to encode what should probably\n/// be recursive elements into an attribute.\n/// \\param encoder is the stream encoder\n/// \\param offset is the offset within the address space to encode\n/// \\param size is the size of the memory location being encoded\nvoid JoinSpace::encodeAttributes(Encoder &encoder,uintb offset,int4 size) const\n\n{\n encodeAttributes(encoder,offset);\t// Ignore size\n}\n\n/// Parse the current element as a join address. Pieces of the join are encoded as a sequence\n/// of ATTRIB_PIECE attributes. \"piece1\" corresponds to the most significant piece. The\n/// Translate::findAddJoin method is used to construct a logical address within the join space.\n/// \\param decoder is the stream decoder\n/// \\param size is a reference to be filled in as the size encoded by the tag\n/// \\return the offset of the final address encoded by the tag\nuintb JoinSpace::decodeAttributes(Decoder &decoder,uint4 &size) const\n\n{\n vector pieces;\n uint4 logicalsize = 0;\n for(;;) {\n uint4 attribId = decoder.getNextAttributeId();\n if (attribId == 0) break;\n if (attribId == ATTRIB_LOGICALSIZE) {\n logicalsize = decoder.readUnsignedInteger();\n continue;\n }\n else if (attribId == ATTRIB_UNKNOWN)\n attribId = decoder.getIndexedAttributeId(ATTRIB_PIECE);\n if (attribId < ATTRIB_PIECE.getId())\n continue;\n int4 pos = (int4)(attribId - ATTRIB_PIECE.getId());\n if (pos > MAX_PIECES)\n continue;\n while(pieces.size() <= pos)\n pieces.emplace_back();\n VarnodeData &vdat( pieces[pos] );\n\n string attrVal = decoder.readString();\n string::size_type offpos = attrVal.find(':');\n if (offpos == string::npos) {\n const Translate *tr = getTrans();\n const VarnodeData &point(tr->getRegister(attrVal));\n vdat = point;\n }\n else {\n string::size_type szpos = attrVal.find(':',offpos+1);\n if (szpos==string::npos)\n\tthrow LowlevelError(\"join address piece attribute is malformed\");\n string spcname = attrVal.substr(0,offpos);\n vdat.space = getManager()->getSpaceByName(spcname);\n istringstream s1(attrVal.substr(offpos+1,szpos));\n s1.unsetf(ios::dec | ios::hex | ios::oct);\n s1 >> vdat.offset;\n istringstream s2(attrVal.substr(szpos+1));\n s2.unsetf(ios::dec | ios::hex | ios::oct);\n s2 >> vdat.size;\n }\n }\n JoinRecord *rec = getManager()->findAddJoin(pieces,logicalsize);\n size = rec->getUnified().size;\n return rec->getUnified().offset;\n}\n\nvoid JoinSpace::printRaw(ostream &s,uintb offset) const\n\n{\n JoinRecord *rec = getManager()->findJoin(offset);\n int4 szsum = 0;\n int4 num = rec->numPieces();\n s << '{';\n for(int4 i=0;igetPiece(i) );\n szsum += vdat.size;\n if (i!=0)\n s << ',';\n vdat.space->printRaw(s,vdat.offset);\n }\n if (num == 1) {\n szsum = rec->getUnified().size;\n s << ':' << szsum;\n }\n s << '}';\n}\n\nuintb JoinSpace::read(const string &s,int4 &size) const\n\n{\n vector pieces;\n int4 szsum = 0;\n int4 i=0;\n while(i < s.size()) {\n pieces.emplace_back();\t// Prepare to read next VarnodeData\n string token;\n while((igetRegister(token);\n }\n catch(LowlevelError &err) {\t// Name doesn't exist\n char tryShortcut = token[0];\n AddrSpace *spc = getManager()->getSpaceByShortcut(tryShortcut);\n if (spc == (AddrSpace *)0)\n\tthrow LowlevelError(\"Could not parse join string\");\n\n int4 subsize;\n pieces.back().space = spc;\n pieces.back().offset = spc->read(token.substr(1),subsize);\n pieces.back().size = subsize;\n }\n szsum += pieces.back().size;\n }\n JoinRecord *rec = getManager()->findAddJoin(pieces,0);\n size = szsum;\n return rec->getUnified().offset;\n}\n\nvoid JoinSpace::decode(Decoder &decoder)\n\n{\n throw LowlevelError(\"Should never decode join space\");\n}\n\n/// \\param m is the address space manager\n/// \\param t is the processor translator\nOverlaySpace::OverlaySpace(AddrSpaceManager *m,const Translate *t)\n : AddrSpace(m,t,IPTR_PROCESSOR)\n{\n baseSpace = (AddrSpace *)0;\n setFlags(overlay);\n}\n\nvoid OverlaySpace::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_SPACE_OVERLAY);\n name = decoder.readString(ATTRIB_NAME);\n index = decoder.readSignedInteger(ATTRIB_INDEX);\n \n baseSpace = decoder.readSpace(ATTRIB_BASE);\n decoder.closeElement(elemId);\n addressSize = baseSpace->getAddrSize();\n wordsize = baseSpace->getWordSize();\n delay = baseSpace->getDelay();\n deadcodedelay = baseSpace->getDeadcodeDelay();\n calcScaleMask();\n\n if (baseSpace->isBigEndian())\n setFlags(big_endian);\n if (baseSpace->hasPhysical())\n setFlags(hasphysical);\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/space.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file space.hh\n/// \\brief Classes for describing address spaces\n\n#ifndef __SPACE_HH__\n#define __SPACE_HH__\n\n#include \"error.hh\"\n#include \"marshal.hh\"\n\nnamespace ghidra {\n\n/// \\brief Fundemental address space types\n///\n/// Every address space must be one of the following core types\nenum spacetype {\n IPTR_CONSTANT = 0,\t ///< Special space to represent constants\n IPTR_PROCESSOR = 1,\t ///< Normal spaces modelled by processor\n IPTR_SPACEBASE = 2,\t ///< addresses = offsets off of base register\n IPTR_INTERNAL = 3,\t ///< Internally managed temporary space\n IPTR_FSPEC = 4,\t ///< Special internal FuncCallSpecs reference\n IPTR_IOP = 5, ///< Special internal PcodeOp reference\n IPTR_JOIN = 6\t\t ///< Special virtual space to represent split variables\n};\n\nclass AddrSpace;\nclass AddrSpaceManager;\nstruct VarnodeData;\nclass Translate;\n\nextern AttributeId ATTRIB_BASE;\t\t///< Marshaling attribute \"base\"\nextern AttributeId ATTRIB_DEADCODEDELAY;\t///< Marshaling attribute \"deadcodedelay\"\nextern AttributeId ATTRIB_DELAY;\t///< Marshaling attribute \"delay\"\nextern AttributeId ATTRIB_LOGICALSIZE;\t///< Marshaling attribute \"logicalsize\"\nextern AttributeId ATTRIB_PHYSICAL;\t///< Marshaling attribute \"physical\"\nextern AttributeId ATTRIB_PIECE;\t///< Marshaling attribute \"piece\"\n\n/// \\brief A region where processor data is stored\n///\n/// An AddrSpace (Address Space) is an arbitrary sequence of\n/// bytes where a processor can store data. As is usual with\n/// most processors' concept of RAM, an integer offset\n/// paired with an AddrSpace forms the address (See Address)\n/// of a byte. The \\e size of an AddrSpace indicates the number\n/// of bytes that can be separately addressed and is usually\n/// described by the number of bytes needed to encode the biggest\n/// offset. I.e. a \\e 4-byte address space means that there are\n/// offsets ranging from 0x00000000 to 0xffffffff within the space\n/// for a total of 2^32 addressable bytes within the space.\n/// There can be multiple address spaces, and it is typical to have spaces\n/// - \\b ram Modeling the main processor address bus\n/// - \\b register Modeling a processors registers\n///\n/// The processor specification can set up any address spaces it\n/// needs in an arbitrary manner, but \\e all data manipulated by\n/// the processor, which the specification hopes to model, must\n/// be contained in some address space, including RAM, ROM,\n/// general registers, special registers, i/o ports, etc.\n///\n/// The analysis engine also uses additional address spaces to\n/// model special concepts. These include\n/// - \\b const There is a \\e constant address space for\n/// modeling constant values in p-code expressions\n/// (See ConstantSpace)\n/// - \\b unique There is always a \\e unique address space used\n/// as a pool for temporary registers. (See UniqueSpace)\n///\nclass AddrSpace {\n friend class AddrSpaceManager; // Space container\npublic:\n enum {\n big_endian = 1,\t\t///< Space is big endian if set, little endian otherwise\n heritaged = 2,\t\t///< This space is heritaged\n does_deadcode = 4,\t\t///< Dead-code analysis is done on this space\n programspecific = 8, ///< Space is specific to a particular loadimage\n reverse_justification = 16, ///< Justification within aligned word is opposite of endianness\n formal_stackspace = 0x20,\t///< Space attached to the formal \\b stack \\b pointer\n overlay = 0x40,\t\t///< This space is an overlay of another space\n overlaybase = 0x80,\t\t///< This is the base space for overlay space(s)\n truncated = 0x100,\t\t///< Space is truncated from its original size, expect pointers larger than this size\n hasphysical = 0x200,\t///< Has physical memory associated with it\n is_otherspace = 0x400,\t///< Quick check for the OtherSpace derived class\n has_nearpointers = 0x800\t///< Does there exist near pointers into this space\n };\nprivate:\n spacetype type;\t\t///< Type of space (PROCESSOR, CONSTANT, INTERNAL, ...)\n AddrSpaceManager *manage; ///< Manager for processor using this space\n const Translate *trans;\t///< Processor translator (for register names etc) for this space\n int4 refcount;\t\t///< Number of managers using this space\n uint4 flags;\t\t\t///< Attributes of the space\n uintb highest;\t ///< Highest (byte) offset into this space\n uintb pointerLowerBound;\t///< Offset below which we don't search for pointers\n uintb pointerUpperBound;\t///< Offset above which we don't search for pointers\n char shortcut;\t\t///< Shortcut character for printing\nprotected:\n string name;\t\t\t///< Name of this space\n uint4 addressSize;\t\t///< Size of an address into this space in bytes\n uint4 wordsize;\t\t///< Size of unit being addressed (1=byte)\n int4 minimumPointerSize;\t///< Smallest size of a pointer into \\b this space (in bytes)\n int4 index;\t\t\t///< An integer identifier for the space\n int4 delay;\t\t\t///< Delay in heritaging this space\n int4 deadcodedelay;\t\t///< Delay before deadcode removal is allowed on this space\n void calcScaleMask(void);\t///< Calculate scale and mask\n void setFlags(uint4 fl);\t///< Set a cached attribute\n void clearFlags(uint4 fl);\t///< Clear a cached attribute\n void decodeBasicAttributes(Decoder &decoder);\t///< Read attributes for \\b this space from an open XML element\n void truncateSpace(uint4 newsize);\npublic:\n AddrSpace(AddrSpaceManager *m,const Translate *t,spacetype tp,const string &nm,bool bigEnd,\n\t uint4 size,uint4 ws,int4 ind,uint4 fl,int4 dl,int4 dead);\n AddrSpace(AddrSpaceManager *m,const Translate *t,spacetype tp); ///< For use with decode\n virtual ~AddrSpace(void) {}\t///< The address space destructor\n const string &getName(void) const; ///< Get the name\n AddrSpaceManager *getManager(void) const; ///< Get the space manager\n const Translate *getTrans(void) const; ///< Get the processor translator\n spacetype getType(void) const; ///< Get the type of space\n int4 getDelay(void) const; ///< Get number of heritage passes being delayed\n int4 getDeadcodeDelay(void) const; ///< Get number of passes before deadcode removal is allowed\n int4 getIndex(void) const;\t///< Get the integer identifier\n uint4 getWordSize(void) const; ///< Get the addressable unit size\n uint4 getAddrSize(void) const; ///< Get the size of the space\n uintb getHighest(void) const; ///< Get the highest byte-scaled address\n uintb getPointerLowerBound(void) const;\t///< Get lower bound for assuming an offset is a pointer\n uintb getPointerUpperBound(void) const;\t///< Get upper bound for assuming an offset is a pointer\n int4 getMinimumPtrSize(void) const;\t///< Get the minimum pointer size for \\b this space\n uintb wrapOffset(uintb off) const; ///< Wrap -off- to the offset that fits into this space\n char getShortcut(void) const; ///< Get the shortcut character\n bool isHeritaged(void) const;\t///< Return \\b true if dataflow has been traced\n bool doesDeadcode(void) const; ///< Return \\b true if dead code analysis should be done on this space\n bool hasPhysical(void) const; ///< Return \\b true if data is physically stored in this\n bool isBigEndian(void) const; ///< Return \\b true if values in this space are big endian\n bool isReverseJustified(void) const; ///< Return \\b true if alignment justification does not match endianness\n bool isFormalStackSpace(void) const;\t///< Return \\b true if \\b this is attached to the formal \\b stack \\b pointer\n bool isOverlay(void) const; ///< Return \\b true if this is an overlay space\n bool isOverlayBase(void) const; ///< Return \\b true if other spaces overlay this space\n bool isOtherSpace(void) const;\t///< Return \\b true if \\b this is the \\e other address space\n bool isTruncated(void) const; ///< Return \\b true if this space is truncated from its original size\n bool hasNearPointers(void) const;\t///< Return \\b true if \\e near (truncated) pointers into \\b this space are possible\n void printOffset(ostream &s,uintb offset) const; ///< Write an address offset to a stream\n\n virtual int4 numSpacebase(void) const;\t///< Number of base registers associated with this space\n virtual const VarnodeData &getSpacebase(int4 i) const;\t///< Get a base register that creates this virtual space\n virtual const VarnodeData &getSpacebaseFull(int4 i) const;\t///< Return original spacebase register before truncation\n virtual bool stackGrowsNegative(void) const;\t\t///< Return \\b true if a stack in this space grows negative\n virtual AddrSpace *getContain(void) const; ///< Return this space's containing space (if any)\n virtual int4 overlapJoin(uintb offset,int4 size,AddrSpace *pointSpace,uintb pointOff,int4 pointSkip) const;\n virtual void encodeAttributes(Encoder &encoder,uintb offset) const; ///< Encode address attributes to a stream\n virtual void encodeAttributes(Encoder &encoder,uintb offset,int4 size) const; ///< Encode an address and size attributes to a stream\n virtual uintb decodeAttributes(Decoder &decoder,uint4 &size) const; ///< Recover an offset and size\n virtual void printRaw(ostream &s,uintb offset) const; ///< Write an address in this space to a stream\n virtual uintb read(const string &s,int4 &size) const; ///< Read in an address (and possible size) from a string\n virtual void decode(Decoder &decoder); ///< Recover the details of this space from a stream\n\n static uintb addressToByte(uintb val,uint4 ws); ///< Scale from addressable units to byte units\n static uintb byteToAddress(uintb val,uint4 ws); ///< Scale from byte units to addressable units\n static int8 addressToByteInt(int8 val,uint4 ws); ///< Scale int4 from addressable units to byte units\n static int8 byteToAddressInt(int8 val,uint4 ws); ///< Scale int4 from byte units to addressable units\n static bool compareByIndex(const AddrSpace *a,const AddrSpace *b);\t///< Compare two spaces by their index\n};\n\n/// \\brief Special AddrSpace for representing constants during analysis.\n///\n/// The underlying RTL (See PcodeOp) represents all data in terms of\n/// an Address, which is made up of an AddrSpace and offset pair.\n/// In order to represent constants in the semantics of the RTL,\n/// there is a special \\e constant address space. An \\e offset\n/// within the address space encodes the actual constant represented\n/// by the pair. I.e. the pair (\\b const,4) represents the constant\n/// \\b 4 within the RTL. The \\e size of the ConstantSpace has\n/// no meaning, as we always want to be able to represent an arbitrarily\n/// large constant. In practice, the size of a constant is limited\n/// by the offset field of an Address.\nclass ConstantSpace : public AddrSpace {\npublic:\n ConstantSpace(AddrSpaceManager *m,const Translate *t); ///< Only constructor\n virtual int4 overlapJoin(uintb offset,int4 size,AddrSpace *pointSpace,uintb pointOff,int4 pointSkip) const;\n virtual void printRaw(ostream &s,uintb offset) const;\n virtual void decode(Decoder &decoder);\n static const string NAME;\t\t///< Reserved name for the address space\n static const int4 INDEX;\t\t///< Reserved index for constant space\n};\n\n/// \\brief Special AddrSpace for special/user-defined address spaces\nclass OtherSpace : public AddrSpace {\npublic:\n OtherSpace(AddrSpaceManager *m, const Translate *t, int4 ind);\t///< Constructor\n OtherSpace(AddrSpaceManager *m, const Translate *t);\t///< For use with decode\n virtual void printRaw(ostream &s, uintb offset) const;\n static const string NAME;\t\t///< Reserved name for the address space\n static const int4 INDEX;\t\t///< Reserved index for the other space\n};\n\n/// \\brief The pool of temporary storage registers\n///\n/// It is convenient both for modelling processor instructions\n/// in an RTL and for later transforming of the RTL to have a pool\n/// of temporary registers that can hold data but that aren't a\n/// formal part of the state of the processor. The UniqueSpace\n/// provides a specific location for this pool. The analysis\n/// engine always creates exactly one of these spaces named\n/// \\b unique. \nclass UniqueSpace : public AddrSpace {\npublic:\n UniqueSpace(AddrSpaceManager *m,const Translate *t,int4 ind,uint4 fl);\t///< Constructor\n UniqueSpace(AddrSpaceManager *m,const Translate *t);\t///< For use with decode\n static const string NAME;\t\t///< Reserved name for the unique space\n static const uint4 SIZE;\t\t///< Fixed size (in bytes) for unique space offsets\n};\n\n/// \\brief The pool of logically joined variables\n///\n/// Some logical variables are split across non-contiguous regions of memory. This space\n/// creates a virtual place for these logical variables to exist. Any memory location within this\n/// space is backed by 2 or more memory locations in other spaces that physically hold the pieces\n/// of the logical value. The database controlling symbols is responsible for keeping track of\n/// mapping the logical address in this space to its physical pieces. Offsets into this space do not\n/// have an absolute meaning, the database may vary what offset is assigned to what set of pieces.\nclass JoinSpace : public AddrSpace {\n static const int4 MAX_PIECES = 64;\t///< Maximum number of pieces that can be marshaled in one \\e join address\npublic:\n JoinSpace(AddrSpaceManager *m,const Translate *t,int4 ind);\n virtual int4 overlapJoin(uintb offset,int4 size,AddrSpace *pointSpace,uintb pointOff,int4 pointSkip) const;\n virtual void encodeAttributes(Encoder &encoder,uintb offset) const;\n virtual void encodeAttributes(Encoder &encoder,uintb offset,int4 size) const;\n virtual uintb decodeAttributes(Decoder &decoder,uint4 &size) const;\n virtual void printRaw(ostream &s,uintb offset) const;\n virtual uintb read(const string &s,int4 &size) const;\n virtual void decode(Decoder &decoder);\n static const string NAME;\t\t///< Reserved name for the join space\n};\n\n/// \\brief An overlay space.\n///\n/// A different code and data layout that occupies the same memory as another address space.\n/// Some compilers use this concept to increase the logical size of a program without increasing\n/// its physical memory requirements. An overlay space allows the same physical location to contain\n/// different code and be labeled with different symbols, depending on context.\n/// From the point of view of reverse engineering, the different code and symbols are viewed\n/// as a logically distinct space.\nclass OverlaySpace : public AddrSpace {\n AddrSpace *baseSpace;\t\t///< Space being overlayed\npublic:\n OverlaySpace(AddrSpaceManager *m,const Translate *t);\t///< Constructor\n virtual AddrSpace *getContain(void) const { return baseSpace; }\n virtual void decode(Decoder &decoder);\n};\n\n/// An internal method for derived classes to set space attributes\n/// \\param fl is the set of attributes to be set\ninline void AddrSpace::setFlags(uint4 fl) {\n flags |= fl;\n}\n\n/// An internal method for derived classes to clear space attibutes\n/// \\param fl is the set of attributes to clear\ninline void AddrSpace::clearFlags(uint4 fl) {\n flags &= ~fl;\n}\n\n/// Every address space has a (unique) name, which is referred\n/// to especially in configuration files via XML.\n/// \\return the name of this space\ninline const string &AddrSpace::getName(void) const {\n return name;\n}\n\n/// Every address space is associated with a manager of (all possible) spaces.\n/// This method recovers the address space manager object.\n/// \\return a pointer to the address space manager\ninline AddrSpaceManager *AddrSpace::getManager(void) const {\n return manage;\n}\n\n/// Every address space is associated with a processor which may have additional objects\n/// like registers etc. associated with it. This method returns a pointer to that processor\n/// translator\n/// \\return a pointer to the Translate object\ninline const Translate *AddrSpace::getTrans(void) const {\n return trans;\n}\n\n///\n/// Return the defining type for this address space.\n/// - IPTR_CONSTANT for the constant space\n/// - IPTR_PROCESSOR for a normal space\n/// - IPTR_INTERNAL for the temporary register space\n/// - IPTR_FSPEC for special FuncCallSpecs references\n/// - IPTR_IOP for special PcodeOp references\n/// \\return the basic type of this space\ninline spacetype AddrSpace::getType(void) const {\n return type;\n}\n\n/// If the heritage algorithms need to trace dataflow\n/// within this space, the algorithms can delay tracing this\n/// space in order to let indirect references into the space\n/// resolve themselves. This method indicates the number of\n/// rounds of dataflow analysis that should be skipped for this\n/// space to let this resolution happen\n/// \\return the number of rounds to skip heritage\ninline int4 AddrSpace::getDelay(void) const {\n return delay;\n}\n\n/// The point at which deadcode removal is performed on varnodes within\n/// a space can be set to skip some number of heritage passes, in case\n/// not all the varnodes are created within a single pass. This method\n/// gives the number of rounds that should be skipped before deadcode\n/// elimination begins\n/// \\return the number of rounds to skip deadcode removal\ninline int4 AddrSpace::getDeadcodeDelay(void) const {\n return deadcodedelay;\n}\n\n/// Each address space has an associated index that can be used\n/// as an integer encoding of the space.\n/// \\return the unique index\ninline int4 AddrSpace::getIndex(void) const {\n return index;\n}\n\n/// This method indicates the number of bytes contained in an\n/// \\e addressable \\e unit of this space. This is almost always\n/// 1, but can be any other small integer.\n/// \\return the number of bytes in a unit\ninline uint4 AddrSpace::getWordSize(void) const {\n return wordsize;\n}\n\n/// Return the number of bytes needed to represent an offset\n/// into this space. A space with 2^32 bytes has an address\n/// size of 4, for instance.\n/// \\return the size of an address\ninline uint4 AddrSpace::getAddrSize(void) const {\n return addressSize;\n}\n\n/// Get the highest (byte) offset possible for this space\n/// \\return the offset\ninline uintb AddrSpace::getHighest(void) const {\n return highest;\n}\n\n/// Constant offsets are tested against \\b this lower bound as a quick filter before\n/// attempting to lookup symbols.\n/// \\return the minimum offset that will be inferred as a pointer\ninline uintb AddrSpace::getPointerLowerBound(void) const {\n return pointerLowerBound;\n}\n\n/// Constant offsets are tested against \\b this upper bound as a quick filter before\n/// attempting to lookup symbols.\n/// \\return the maximum offset that will be inferred as a pointer\ninline uintb AddrSpace::getPointerUpperBound(void) const {\n return pointerUpperBound;\n}\n\n/// A value of 0 means the size must match exactly. If the space is truncated, or\n/// if there exists near pointers, this value may be non-zero.\ninline int4 AddrSpace::getMinimumPtrSize(void) const {\n return minimumPointerSize;\n}\n\n/// Calculate \\e off modulo the size of this address space in\n/// order to construct the offset \"equivalent\" to \\e off that\n/// fits properly into this space\n/// \\param off is the offset requested\n/// \\return the wrapped offset\ninline uintb AddrSpace::wrapOffset(uintb off) const {\n if (off <= highest)\t\t// Comparison is unsigned\n return off;\n intb mod = (intb)(highest+1);\n intb res = (intb)off % mod;\t// remainder is signed\n if (res<0)\t\t\t// Remainder may be negative\n res += mod;\t\t\t// Adding mod guarantees res is in (0,mod)\n return (uintb)res;\n}\n\n/// Return a unique short cut character that is associated\n/// with this space. The shortcut character can be used by\n/// the read method to quickly specify the space of an address.\n/// \\return the shortcut character\ninline char AddrSpace::getShortcut(void) const {\n return shortcut;\n}\n\n/// During analysis, memory locations in most spaces need to\n/// have their data-flow traced. This method returns \\b true\n/// for these spaces. For some of the special spaces, like\n/// the \\e constant space, tracing data flow makes no sense,\n/// and this routine will return \\b false.\n/// \\return \\b true if this space's data-flow is analyzed\ninline bool AddrSpace::isHeritaged(void) const {\n return ((flags & heritaged)!=0);\n}\n\n/// Most memory locations should have dead-code analysis performed,\n/// and this routine will return \\b true.\n/// For certain special spaces like the \\e constant space, dead-code\n/// analysis doesn't make sense, and this routine returns \\b false.\ninline bool AddrSpace::doesDeadcode(void) const {\n return ((flags & does_deadcode)!=0);\n}\n\n/// This routine returns \\b true, if, like most spaces, the space\n/// has actual read/writeable bytes associated with it.\n/// Some spaces, like the \\e constant space, do not.\n/// \\return \\b true if the space has physical data in it.\ninline bool AddrSpace::hasPhysical(void) const {\n return ((flags & hasphysical) !=0);\n}\n\n/// If integer values stored in this space are encoded in this\n/// space using the big endian format, then return \\b true.\n/// \\return \\b true if the space is big endian\ninline bool AddrSpace::isBigEndian(void) const {\n return ((flags&big_endian)!=0);\n}\n\n/// Certain architectures or compilers specify an alignment for accessing words within the space\n/// The space required for a variable must be rounded up to the alignment. For variables smaller\n/// than the alignment, there is the issue of how the variable is \"justified\" within the aligned\n/// word. Usually the justification depends on the endianness of the space, for certain weird\n/// cases the justification may be the opposite of the endianness.\ninline bool AddrSpace::isReverseJustified(void) const {\n return ((flags&reverse_justification)!=0);\n}\n\n/// Currently an architecture can declare only one formal stack pointer.\ninline bool AddrSpace::isFormalStackSpace(void) const {\n return ((flags&formal_stackspace)!=0);\n}\n\ninline bool AddrSpace::isOverlay(void) const {\n return ((flags&overlay)!=0);\n}\n\ninline bool AddrSpace::isOverlayBase(void) const {\n return ((flags&overlaybase)!=0);\n}\n\ninline bool AddrSpace::isOtherSpace(void) const {\n return ((flags&is_otherspace)!=0);\n}\n\n/// If this method returns \\b true, the logical form of this space is truncated from its actual size\n/// Pointers may refer to this original size put the most significant bytes are ignored\ninline bool AddrSpace::isTruncated(void) const {\n return ((flags&truncated)!=0);\n}\n\ninline bool AddrSpace::hasNearPointers(void) const {\n return ((flags&has_nearpointers)!=0);\n}\n\n/// Some spaces are \"virtual\", like the stack spaces, where addresses are really relative to a\n/// base pointer stored in a register, like the stackpointer. This routine will return non-zero\n/// if \\b this space is virtual and there is 1 (or more) associated pointer registers\n/// \\return the number of base registers associated with this space\ninline int4 AddrSpace::numSpacebase(void) const {\n return 0;\n}\n\n/// For virtual spaces, like the stack space, this routine returns the location information for\n/// a base register of the space. This routine will throw an exception if the register does not exist\n/// \\param i is the index of the base register starting at\n/// \\return the VarnodeData that describes the register\ninline const VarnodeData &AddrSpace::getSpacebase(int4 i) const {\n throw LowlevelError(name+\" space is not virtual and has no associated base register\");\n}\n\n/// If a stack pointer is truncated to fit the stack space, we may need to know the\n/// extent of the original register\n/// \\param i is the index of the base register\n/// \\return the original register before truncation\ninline const VarnodeData &AddrSpace::getSpacebaseFull(int4 i) const {\n throw LowlevelError(name+\" has no truncated registers\");\n}\n\n/// For stack (or other spacebase) spaces, this routine returns \\b true if the space can viewed as a stack\n/// and a \\b push operation causes the spacebase pointer to be decreased (grow negative)\n/// \\return \\b true if stacks grow in negative direction.\ninline bool AddrSpace::stackGrowsNegative(void) const {\n return true;\n}\n\n/// If this space is virtual, then\n/// this routine returns the containing address space, otherwise\n/// it returns NULL.\n/// \\return a pointer to the containing space or NULL\ninline AddrSpace *AddrSpace::getContain(void) const {\n return (AddrSpace *)0;\n}\n\n/// Given an offset into an address space based on the addressable unit size (wordsize),\n/// convert it into a byte relative offset\n/// \\param val is the offset to convert\n/// \\param ws is the number of bytes in the addressable word\n/// \\return the scaled offset\ninline uintb AddrSpace::addressToByte(uintb val,uint4 ws) {\n return val*ws;\n}\n\n/// Given an offset in an address space based on bytes, convert it\n/// into an offset relative to the addressable unit of the space (wordsize)\n/// \\param val is the offset to convert\n/// \\param ws is the number of bytes in the addressable word\n/// \\return the scaled offset\ninline uintb AddrSpace::byteToAddress(uintb val,uint4 ws) {\n return val/ws;\n}\n\n/// Given an int8 offset into an address space based on the addressable unit size (wordsize),\n/// convert it into a byte relative offset\n/// \\param val is the offset to convert\n/// \\param ws is the number of bytes in the addressable word\n/// \\return the scaled offset\ninline int8 AddrSpace::addressToByteInt(int8 val,uint4 ws) {\n return val*ws;\n}\n\n/// Given an int8 offset in an address space based on bytes, convert it\n/// into an offset relative to the addressable unit of the space (wordsize)\n/// \\param val is the offset to convert\n/// \\param ws is the number of bytes in the addressable word\n/// \\return the scaled offset\ninline int8 AddrSpace::byteToAddressInt(int8 val,uint4 ws) {\n return val/ws;\n}\n\n/// For sorting a sequence of address spaces.\n/// \\param a is the first space\n/// \\param b is the second space\n/// \\return \\b true if the first space should come before the second\ninline bool AddrSpace::compareByIndex(const AddrSpace *a,const AddrSpace *b) {\n return (a->index < b->index);\n}\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/translate.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"translate.hh\"\n\nnamespace ghidra {\n\nAttributeId ATTRIB_CODE = AttributeId(\"code\",43);\nAttributeId ATTRIB_CONTAIN = AttributeId(\"contain\",44);\nAttributeId ATTRIB_DEFAULTSPACE = AttributeId(\"defaultspace\",45);\nAttributeId ATTRIB_UNIQBASE = AttributeId(\"uniqbase\",46);\n\nElementId ELEM_OP = ElementId(\"op\",27);\nElementId ELEM_SLEIGH = ElementId(\"sleigh\",28);\nElementId ELEM_SPACE = ElementId(\"space\",29);\nElementId ELEM_SPACEID = ElementId(\"spaceid\",30);\nElementId ELEM_SPACES = ElementId(\"spaces\",31);\nElementId ELEM_SPACE_BASE = ElementId(\"space_base\",32);\nElementId ELEM_SPACE_OTHER = ElementId(\"space_other\",33);\nElementId ELEM_SPACE_OVERLAY = ElementId(\"space_overlay\",34);\nElementId ELEM_SPACE_UNIQUE = ElementId(\"space_unique\",35);\nElementId ELEM_TRUNCATE_SPACE = ElementId(\"truncate_space\",36);\n\n/// Parse a \\ element to configure \\b this object\n/// \\param decoder is the stream decoder\nvoid TruncationTag::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_TRUNCATE_SPACE);\n spaceName = decoder.readString(ATTRIB_SPACE);\n size = decoder.readUnsignedInteger(ATTRIB_SIZE);\n decoder.closeElement(elemId);\n}\n\n/// Construct a virtual space. This is usually used for the stack\n/// space, which is indicated by the \\b isFormal parameters, but multiple such spaces are allowed.\n/// \\param m is the manager for this \\b program \\b specific address space\n/// \\param t is associated processor translator\n/// \\param nm is the name of the space\n/// \\param ind is the integer identifier\n/// \\param sz is the size of the space\n/// \\param base is the containing space\n/// \\param dl is the heritage delay\n/// \\param isFormal is the formal stack space indicator\nSpacebaseSpace::SpacebaseSpace(AddrSpaceManager *m,const Translate *t,const string &nm,int4 ind,int4 sz,\n\t\t\t AddrSpace *base,int4 dl,bool isFormal)\n : AddrSpace(m,t,IPTR_SPACEBASE,nm,t->isBigEndian(),sz,base->getWordSize(),ind,0,dl,dl)\n{\n contain = base;\n hasbaseregister = false;\t// No base register assigned yet\n isNegativeStack = true;\t// default stack growth\n if (isFormal)\n setFlags(formal_stackspace);\n}\n\n/// This is a partial constructor, which must be followed up\n/// with decode in order to fillin the rest of the spaces\n/// attributes\n/// \\param m is the associated address space manager\n/// \\param t is the associated processor translator\nSpacebaseSpace::SpacebaseSpace(AddrSpaceManager *m,const Translate *t)\n : AddrSpace(m,t,IPTR_SPACEBASE)\n{\n hasbaseregister = false;\n isNegativeStack = true;\n setFlags(programspecific);\n}\n\n/// This routine sets the base register associated with this \\b virtual space\n/// It will throw an exception if something tries to set two (different) base registers\n/// \\param data is the location data for the base register\n/// \\param truncSize is the size of the space covered by the register\n/// \\param stackGrowth is \\b true if the stack which this register manages grows in a negative direction\nvoid SpacebaseSpace::setBaseRegister(const VarnodeData &data,int4 truncSize,bool stackGrowth)\n\n{\n if (hasbaseregister) {\n if ((baseloc != data)||(isNegativeStack != stackGrowth))\n throw LowlevelError(\"Attempt to assign more than one base register to space: \"+getName());\n }\n hasbaseregister = true;\n isNegativeStack = stackGrowth;\n baseOrig = data;\n baseloc = data;\n if (truncSize != baseloc.size) {\n if (baseloc.space->isBigEndian())\n baseloc.offset += (baseloc.size - truncSize);\n baseloc.size = truncSize;\n }\n}\n\nint4 SpacebaseSpace::numSpacebase(void) const\n\n{\n return hasbaseregister ? 1 : 0;\n}\n\nconst VarnodeData &SpacebaseSpace::getSpacebase(int4 i) const\n\n{\n if ((!hasbaseregister)||(i!=0))\n throw LowlevelError(\"No base register specified for space: \"+getName());\n return baseloc;\n}\n\nconst VarnodeData &SpacebaseSpace::getSpacebaseFull(int4 i) const\n\n{\n if ((!hasbaseregister)||(i!=0))\n throw LowlevelError(\"No base register specified for space: \"+getName());\n return baseOrig;\n}\n\nvoid SpacebaseSpace::decode(Decoder &decoder)\n\n{\n uint4 elemId = decoder.openElement(ELEM_SPACE_BASE);\n decodeBasicAttributes(decoder);\n contain = decoder.readSpace(ATTRIB_CONTAIN);\n decoder.closeElement(elemId);\n}\n\n/// The \\e join space range maps to the underlying pieces in a natural endian aware way.\n/// Given an offset in the range, figure out what address it is mapping to.\n/// The particular piece is passed back as an index, and the Address is returned.\n/// \\param offset is the offset within \\b this range to map\n/// \\param pos will hold the passed back piece index\n/// \\return the Address mapped to\nAddress JoinRecord::getEquivalentAddress(uintb offset,int4 &pos) const\n\n{\n if (offset < unified.offset)\n return Address();\t\t// offset comes before this range\n int4 smallOff = (int4)(offset - unified.offset);\n if (pieces[0].space->isBigEndian()) {\n for(pos=0;pos= 0; --pos) {\n int4 pieceSize = pieces[pos].size;\n if (smallOff < pieceSize)\n\tbreak;\n smallOff -= pieceSize;\n }\n if (pos < 0)\n return Address();\t\t// offset comes after this range\n }\n return Address(pieces[pos].space,pieces[pos].offset + smallOff);\n}\n\n/// Allow sorting on JoinRecords so that a collection of pieces can be quickly mapped to\n/// its logical whole, specified with a join address\nbool JoinRecord::operator<(const JoinRecord &op2) const\n\n{\n // Some joins may have same piece but different unified size (floating point)\n if (unified.size != op2.unified.size) // Compare size first\n return (unified.size < op2.unified.size);\n // Lexigraphic sort on pieces\n int4 i=0;\n for(;;) {\n if (pieces.size()==i) {\n return (op2.pieces.size()>i); // If more pieces in op2, it is bigger (return true), if same number this==op2, return false\n }\n if (op2.pieces.size()==i) return false; // More pieces in -this-, so it is bigger, return false\n if (pieces[i] != op2.pieces[i])\n return (pieces[i] < op2.pieces[i]);\n i += 1;\n }\n}\n\n/// Assuming the given list of VarnodeData go from most significant to least significant,\n/// merge any contiguous elements in the list. Varnodes that are not in the \\e stack address space\n/// are only merged if the resulting byte range has a formal register name.\n/// \\param seq is the given list of VarnodeData\n/// \\param trans is the language to use for register names\nvoid JoinRecord::mergeSequence(vector &seq,const Translate *trans)\n\n{\n int4 i=1;\n while(i= seq.size()) return;\n vector res;\n i = 1;\n res.push_back(seq.front());\n bool lastIsInformal = false;\n while(iisBigEndian() ? hi.offset : lo.offset;\n hi.size += lo.size;\n if (hi.space->getType() != IPTR_SPACEBASE) {\n\tlastIsInformal = trans->getExactRegisterName(hi.space, hi.offset, hi.size).size() == 0;\n }\n }\n else {\n if (lastIsInformal)\n\tbreak;\n res.push_back(lo);\n }\n i += 1;\n }\n if (lastIsInformal)\t// If the merge contains an informal register\n return;\t\t// throw it out and keep the original sequence\n seq = res;\n}\n\n/// Initialize manager containing no address spaces. All the cached space slots are set to null\nAddrSpaceManager::AddrSpaceManager(void)\n\n{\n defaultcodespace = (AddrSpace *)0;\n defaultdataspace = (AddrSpace *)0;\n constantspace = (AddrSpace *)0;\n iopspace = (AddrSpace *)0;\n fspecspace = (AddrSpace *)0;\n joinspace = (AddrSpace *)0;\n stackspace = (AddrSpace *)0;\n uniqspace = (AddrSpace *)0;\n joinallocate = 0;\n}\n\n/// The initialization of address spaces is the same across all\n/// variants of the Translate object. This routine initializes\n/// a single address space from a decoder element. It knows\n/// which class derived from AddrSpace to instantiate based on\n/// the ElementId.\n/// \\param decoder is the stream decoder\n/// \\param trans is the translator object to be associated with the new space\n/// \\return a pointer to the initialized AddrSpace\nAddrSpace *AddrSpaceManager::decodeSpace(Decoder &decoder,const Translate *trans)\n\n{\n uint4 elemId = decoder.peekElement();\n AddrSpace *res;\n if (elemId == ELEM_SPACE_BASE)\n res = new SpacebaseSpace(this,trans);\n else if (elemId == ELEM_SPACE_UNIQUE)\n res = new UniqueSpace(this,trans);\n else if (elemId == ELEM_SPACE_OTHER)\n res = new OtherSpace(this,trans);\n else if (elemId == ELEM_SPACE_OVERLAY)\n res = new OverlaySpace(this,trans);\n else\n res = new AddrSpace(this,trans,IPTR_PROCESSOR);\n\n res->decode(decoder);\n return res;\n}\n\n/// This routine initializes (almost) all the address spaces used\n/// for a particular processor by using a \\b \\ element,\n/// which contains child elements for the specific address spaces.\n/// This also instantiates the builtin \\e constant space. It\n/// should probably also instantiate the \\b iop, \\b fspec, and \\b join\n/// spaces, but this is currently done by the Architecture class.\n/// \\param decoder is the stream decoder\n/// \\param trans is the processor translator to be associated with the spaces\nvoid AddrSpaceManager::decodeSpaces(Decoder &decoder,const Translate *trans)\n\n{\n // The first space should always be the constant space\n insertSpace(new ConstantSpace(this,trans));\n\n uint4 elemId = decoder.openElement(ELEM_SPACES);\n string defname = decoder.readString(ATTRIB_DEFAULTSPACE);\n while(decoder.peekElement() != 0) {\n AddrSpace *spc = decodeSpace(decoder,trans);\n insertSpace(spc);\n }\n decoder.closeElement(elemId);\n AddrSpace *spc = getSpaceByName(defname);\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"Bad 'defaultspace' attribute: \"+defname);\n setDefaultCodeSpace(spc->getIndex());\n}\n\n/// Once all the address spaces have been initialized, this routine\n/// should be called once to establish the official \\e default\n/// space for the processor, via its index. Should only be\n/// called during initialization.\n/// \\param index is the index of the desired default space\nvoid AddrSpaceManager::setDefaultCodeSpace(int4 index)\n\n{\n if (defaultcodespace != (AddrSpace *)0)\n throw LowlevelError(\"Default space set multiple times\");\n if (baselist.size()<=index || baselist[index] == (AddrSpace *)0)\n throw LowlevelError(\"Bad index for default space\");\n defaultcodespace = baselist[index];\n defaultdataspace = defaultcodespace;\t\t// By default the default data space is the same\n}\n\n/// If the architecture has different code and data spaces, this routine can be called\n/// to set the \\e data space after the \\e code space has been set.\n/// \\param index is the index of the desired default space\nvoid AddrSpaceManager::setDefaultDataSpace(int4 index)\n\n{\n if (defaultcodespace == (AddrSpace *)0)\n throw LowlevelError(\"Default data space must be set after the code space\");\n if (baselist.size()<=index || baselist[index] == (AddrSpace *)0)\n throw LowlevelError(\"Bad index for default data space\");\n defaultdataspace = baselist[index];\n}\n\n/// For spaces with alignment restrictions, the address of a small variable must be justified\n/// within a larger aligned memory word, usually either to the left boundary for little endian encoding\n/// or to the right boundary for big endian encoding. Some compilers justify small variables to\n/// the opposite side of the one indicated by the endianness. Setting this property on a space\n/// causes the decompiler to use this justification\nvoid AddrSpaceManager::setReverseJustified(AddrSpace *spc)\n\n{\n spc->setFlags(AddrSpace::reverse_justification);\n}\n\n/// This adds a previously instantiated address space (AddrSpace)\n/// to the model for this processor. It checks a set of\n/// indexing and naming conventions for the space and throws\n/// an exception if the conventions are violated. Should\n/// only be called during initialization.\n/// \\todo This really shouldn't be public. Need to move the\n/// allocation of \\b iop, \\b fspec, and \\b join out of Architecture\n/// \\param spc the address space to insert\nvoid AddrSpaceManager::insertSpace(AddrSpace *spc)\n\n{\n bool nameTypeMismatch = false;\n bool duplicateName = false;\n bool duplicateId = false;\n switch(spc->getType()) {\n case IPTR_CONSTANT:\n if (spc->getName() != ConstantSpace::NAME)\n nameTypeMismatch = true;\n if (spc->index != ConstantSpace::INDEX)\n throw LowlevelError(\"const space must be assigned index 0\");\n constantspace = spc;\n break;\n case IPTR_INTERNAL:\n if (spc->getName() != UniqueSpace::NAME)\n nameTypeMismatch = true;\n if (uniqspace != (AddrSpace *)0)\n duplicateName = true;\n uniqspace = spc;\n break;\n case IPTR_FSPEC:\n if (spc->getName() != \"fspec\")\n nameTypeMismatch = true;\n if (fspecspace != (AddrSpace *)0)\n duplicateName = true;\n fspecspace = spc;\n break;\n case IPTR_JOIN:\n if (spc->getName() != JoinSpace::NAME)\n nameTypeMismatch = true;\n if (joinspace != (AddrSpace *)0)\n duplicateName = true;\n joinspace = spc;\n break;\n case IPTR_IOP:\n if (spc->getName() != \"iop\")\n nameTypeMismatch = true;\n if (iopspace != (AddrSpace *)0)\n duplicateName = true;\n iopspace = spc;\n break;\n case IPTR_SPACEBASE:\n if (spc->getName() == \"stack\") {\n if (stackspace != (AddrSpace *)0)\n\tduplicateName = true;\n stackspace = spc;\n }\n // fallthru\n case IPTR_PROCESSOR:\n if (spc->isOverlay()) {\t// If this is a new overlay space\n spc->getContain()->setFlags(AddrSpace::overlaybase); // Mark the base as being overlayed\n }\n else if (spc->isOtherSpace()) {\n if (spc->index != OtherSpace::INDEX)\n throw LowlevelError(\"OTHER space must be assigned index 1\");\n }\n break;\n }\n\n if (baselist.size() <= spc->index)\n baselist.resize(spc->index+1, (AddrSpace *)0);\n\n duplicateId = baselist[spc->index] != (AddrSpace *)0;\n\n if (!nameTypeMismatch && !duplicateName && !duplicateId) {\n duplicateName = !name2Space.insert(pair(spc->getName(),spc)).second;\n }\n\n if (nameTypeMismatch || duplicateName || duplicateId) {\n string errMsg = \"Space \" + spc->getName();\n if (nameTypeMismatch)\n errMsg = errMsg + \" was initialized with wrong type\";\n if (duplicateName)\n errMsg = errMsg + \" was initialized more than once\";\n if (duplicateId)\n errMsg = errMsg + \" was assigned as id duplicating: \"+baselist[spc->index]->getName();\n if (spc->refcount == 0)\n delete spc;\n spc = (AddrSpace *)0;\n throw LowlevelError(errMsg);\n }\n baselist[spc->index] = spc;\n spc->refcount += 1;\n assignShortcut(spc);\n}\n\n/// Different managers may need to share the same spaces. I.e. if different programs being\n/// analyzed share the same processor. This routine pulls in a reference of every space in -op2-\n/// in order to manage it from within -this-\n/// \\param op2 is a pointer to space manager being copied\nvoid AddrSpaceManager::copySpaces(const AddrSpaceManager *op2)\n\n{ // Insert every space in -op2- into -this- manager\n for(int4 i=0;ibaselist.size();++i) {\n AddrSpace *spc = op2->baselist[i];\n if (spc != (AddrSpace *)0)\n insertSpace(spc);\n }\n setDefaultCodeSpace(op2->getDefaultCodeSpace()->getIndex());\n setDefaultDataSpace(op2->getDefaultDataSpace()->getIndex());\n}\n\n/// Perform the \\e privileged act of associating a base register with an existing \\e virtual space\n/// \\param basespace is the virtual space\n/// \\param ptrdata is the location data for the base register\n/// \\param truncSize is the size of the space covered by the base register\n/// \\param stackGrowth is true if the stack grows \"normally\" towards address 0\nvoid AddrSpaceManager::addSpacebasePointer(SpacebaseSpace *basespace,const VarnodeData &ptrdata,int4 truncSize,bool stackGrowth)\n\n{\n basespace->setBaseRegister(ptrdata,truncSize,stackGrowth);\n}\n\n/// Provide a new specialized resolver for a specific AddrSpace. The manager takes ownership of resolver.\n/// \\param spc is the space to which the resolver is associated\n/// \\param rsolv is the new resolver object\nvoid AddrSpaceManager::insertResolver(AddrSpace *spc,AddressResolver *rsolv)\n\n{\n int4 ind = spc->getIndex();\n while(resolvelist.size() <= ind)\n resolvelist.push_back((AddressResolver *)0);\n if (resolvelist[ind] != (AddressResolver *)0)\n delete resolvelist[ind];\n resolvelist[ind] = rsolv;\n}\n\n/// This method establishes for a single address space, what range of constants are checked\n/// as possible symbol starts, when it is not known apriori that a constant is a pointer.\n/// \\param range is the range of values for a single address space\nvoid AddrSpaceManager::setInferPtrBounds(const Range &range)\n\n{\n range.getSpace()->pointerLowerBound = range.getFirst();\n range.getSpace()->pointerUpperBound = range.getLast();\n}\n\n/// Base destructor class, cleans up AddrSpace pointers which\n/// must be explicited created via \\e new\nAddrSpaceManager::~AddrSpaceManager(void)\n\n{\n for(vector::iterator iter=baselist.begin();iter!=baselist.end();++iter) {\n AddrSpace *spc = *iter;\n if (spc == (AddrSpace *)0) continue;\n if (spc->refcount > 1)\n spc->refcount -= 1;\n else\n delete spc;\n }\n for(int4 i=0;ishortcut != ' ') {\t// If the shortcut is already assigned\n shortcut2Space.insert(pair(spc->shortcut,spc));\n return;\n }\n char shortcut;\n switch(spc->getType()) {\n case IPTR_CONSTANT:\n shortcut = '#';\n break;\n case IPTR_PROCESSOR:\n if (spc->getName() == \"register\")\n shortcut = '%';\n else\n shortcut = spc->getName()[0];\n break;\n case IPTR_SPACEBASE:\n shortcut = 's';\n break;\n case IPTR_INTERNAL:\n shortcut = 'u';\n break;\n case IPTR_FSPEC:\n shortcut = 'f';\n break;\n case IPTR_JOIN:\n shortcut = 'j';\n break;\n case IPTR_IOP:\n shortcut = 'i';\n break;\n default:\n shortcut = 'x';\n break;\n }\n\n if (shortcut >= 'A' && shortcut <= 'Z')\n shortcut += 0x20;\n\n int4 collisionCount = 0;\n while(!shortcut2Space.insert(pair(shortcut,spc)).second) {\n collisionCount += 1;\n if (collisionCount >26) {\n // Could not find a unique shortcut, but we just re-use 'z' as we\n // can always use the long form to specify the address if there are really so many\n // spaces that need to be distinguishable (in the console mode)\n spc->shortcut = 'z';\n return;\n }\n shortcut += 1;\n if (shortcut < 'a' || shortcut > 'z')\n shortcut = 'a';\n }\n spc->shortcut = (char)shortcut;\n}\n\n/// \\param spc is the AddrSpace to mark\n/// \\param size is the (minimum) size of a near pointer in bytes\nvoid AddrSpaceManager::markNearPointers(AddrSpace *spc,int4 size)\n\n{\n spc->setFlags(AddrSpace::has_nearpointers);\n if (spc->minimumPointerSize == 0 && spc->addressSize != size)\n spc->minimumPointerSize = size;\n}\n\n/// All address spaces have a unique name associated with them.\n/// This routine retrieves the AddrSpace object based on the\n/// desired name.\n/// \\param nm is the name of the address space\n/// \\return a pointer to the AddrSpace object\nAddrSpace *AddrSpaceManager::getSpaceByName(const string &nm) const\n\n{\n map::const_iterator iter = name2Space.find(nm);\n if (iter == name2Space.end())\n return (AddrSpace *)0;\n return (*iter).second;\n}\n\n/// All address spaces have a unique shortcut (ASCII) character\n/// assigned to them. This routine retrieves an AddrSpace object\n/// given a specific shortcut.\n/// \\param sc is the shortcut character\n/// \\return a pointer to an AddrSpace\nAddrSpace *AddrSpaceManager::getSpaceByShortcut(char sc) const\n\n{\n map::const_iterator iter;\n iter = shortcut2Space.find(sc);\n if (iter == shortcut2Space.end())\n return (AddrSpace *)0;\n return (*iter).second;\n}\n\n/// \\brief Resolve a native constant into an Address\n///\n/// If there is a special resolver for the AddrSpace, this is invoked, otherwise\n/// basic wordsize conversion and wrapping is performed. If the address encoding is\n/// partial (as in a \\e near pointer) and the full encoding can be recovered, it is passed back.\n/// The \\e sz parameter indicates the number of bytes in constant and is used to determine if\n/// the constant is a partial or full pointer encoding. A value of -1 indicates the value is\n/// known to be a full encoding.\n/// \\param spc is the space to generate the address from\n/// \\param val is the constant encoding of the address\n/// \\param sz is the size of the constant encoding (or -1)\n/// \\param point is the context address (for recovering full encoding info if necessary)\n/// \\param fullEncoding is used to pass back the recovered full encoding of the pointer\n/// \\return the formal Address associated with the encoding\nAddress AddrSpaceManager::resolveConstant(AddrSpace *spc,uintb val,int4 sz,const Address &point,uintb &fullEncoding) const\n\n{\n int4 ind = spc->getIndex();\n if (ind < resolvelist.size()) {\n AddressResolver *resolve = resolvelist[ind];\n if (resolve != (AddressResolver *)0)\n return resolve->resolve(val,sz,point,fullEncoding);\n }\n fullEncoding = val;\n val = AddrSpace::addressToByte(val,spc->getWordSize());\n val = spc->wrapOffset(val);\n return Address(spc,val);\n}\n\n/// Get the next space in the absolute order of addresses.\n/// This ordering is determined by the AddrSpace index.\n/// \\param spc is the pointer to the space being queried\n/// \\return the pointer to the next space in absolute order\nAddrSpace *AddrSpaceManager::getNextSpaceInOrder(AddrSpace *spc) const\n{\n if (spc == (AddrSpace *)0) {\n return baselist[0];\n }\n if (spc == (AddrSpace *) ~((uintp)0)) {\n return (AddrSpace *)0;\n }\n int4 index = spc->getIndex() + 1;\n while (index < baselist.size()) {\n AddrSpace *res = baselist[index];\n if (res != (AddrSpace *)0)\n return res;\n index += 1;\n }\n return (AddrSpace *) ~((uintp)0);\n}\n\n/// Given a list of memory locations, the \\e pieces, either find a pre-existing JoinRecord or\n/// create a JoinRecord that represents the logical joining of the pieces. The pieces must\n/// be in order from most significant to least significant.\n/// \\param pieces if the list memory locations to be joined\n/// \\param logicalsize of a \\e single \\e piece join, or zero\n/// \\return a pointer to the JoinRecord\nJoinRecord *AddrSpaceManager::findAddJoin(const vector &pieces,uint4 logicalsize)\n\n{ // Find a pre-existing split record, or create a new one corresponding to the input -pieces-\n // If -logicalsize- is 0, calculate logical size as sum of pieces\n if (pieces.size() == 0)\n throw LowlevelError(\"Cannot create a join without pieces\");\n if ((pieces.size()==1)&&(logicalsize==0))\n throw LowlevelError(\"Cannot create a single piece join without a logical size\");\n\n uint4 totalsize;\n if (logicalsize != 0) {\n if (pieces.size() != 1)\n throw LowlevelError(\"Cannot specify logical size for multiple piece join\");\n totalsize = logicalsize;\n }\n else {\n totalsize = 0;\n for(int4 i=0;i::const_iterator iter;\n iter = splitset.find(&testnode);\n if (iter != splitset.end())\t\t// If already in the set\n return *iter;\n\n JoinRecord *newjoin = new JoinRecord();\n newjoin->pieces = pieces;\n \n uint4 roundsize = (totalsize + 15) & ~((uint4)0xf);\t// Next biggest multiple of 16\n\n newjoin->unified.space = joinspace;\n newjoin->unified.offset = joinallocate;\n joinallocate += roundsize;\n newjoin->unified.size = totalsize;\n splitset.insert(newjoin);\n splitlist.push_back(newjoin);\n return splitlist.back();\n}\n\n/// Given a specific \\e offset into the \\e join address space, recover the JoinRecord that\n/// contains the offset, as a range in the \\e join address space. If there is no existing\n/// record, null is returned.\n/// \\param offset is an offset into the join space\n/// \\return the JoinRecord containing that offset or null\nJoinRecord *AddrSpaceManager::findJoinInternal(uintb offset) const\n\n{\n int4 min=0;\n int4 max=splitlist.size()-1;\n while(min<=max) {\t\t// Binary search\n int4 mid = (min+max)/2;\n JoinRecord *rec = splitlist[mid];\n uintb val = rec->unified.offset;\n if (val + rec->unified.size <= offset)\n min = mid + 1;\n else if (val > offset)\n max = mid - 1;\n else\n return rec;\n }\n return (JoinRecord *)0;\n}\n\n/// Given a specific \\e offset into the \\e join address space, recover the JoinRecord that\n/// lists the pieces corresponding to that offset. The offset must originally have come from\n/// a JoinRecord returned by \\b findAddJoin, otherwise this method throws an exception.\n/// \\param offset is an offset into the join space\n/// \\return the JoinRecord for that offset\nJoinRecord *AddrSpaceManager::findJoin(uintb offset) const\n\n{\n int4 min=0;\n int4 max=splitlist.size()-1;\n while(min<=max) {\t\t// Binary search\n int4 mid = (min+max)/2;\n JoinRecord *rec = splitlist[mid];\n uintb val = rec->unified.offset;\n if (val == offset) return rec;\n if (val < offset)\n min = mid + 1;\n else\n max = mid - 1;\n }\n throw LowlevelError(\"Unlinked join address\");\n}\n\n/// Set the number of passes for a specific AddrSpace before deadcode removal is allowed\n/// for that space.\n/// \\param spc is the AddrSpace to change\n/// \\param delaydelta is the number of rounds to the delay should be set to\nvoid AddrSpaceManager::setDeadcodeDelay(AddrSpace *spc,int4 delaydelta)\n\n{\n spc->deadcodedelay = delaydelta;\n}\n\n/// Mark the named space as truncated from its original size\n/// \\param tag is a description of the space and how it should be truncated\nvoid AddrSpaceManager::truncateSpace(const TruncationTag &tag)\n\n{\n AddrSpace *spc = getSpaceByName(tag.getName());\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"Unknown space in command: \"+tag.getName());\n spc->truncateSpace(tag.getSize());\n}\n\n/// This handles the situation where we need to find a logical address to hold the lower\n/// precision floating-point value that is stored in a bigger register\n/// If the logicalsize (precision) requested matches the -realsize- of the register\n/// just return the real address. Otherwise construct a join address to hold the logical value\n/// \\param realaddr is the address of the real floating-point register\n/// \\param realsize is the size of the real floating-point register\n/// \\param logicalsize is the size (lower precision) size of the logical value\nAddress AddrSpaceManager::constructFloatExtensionAddress(const Address &realaddr,int4 realsize,\n\t\t\t\t\t\t\t int4 logicalsize)\n{\n if (logicalsize == realsize)\n return realaddr;\n vector pieces;\n pieces.emplace_back();\n pieces.back().space = realaddr.getSpace();\n pieces.back().offset = realaddr.getOffset();\n pieces.back().size = realsize;\n\n JoinRecord *join = findAddJoin(pieces,logicalsize);\n return join->getUnified().getAddr();\n}\n\n/// This handles the common case, of trying to find a join address given a high location and a low\n/// location. This may not return an address in the \\e join address space. It checks for the case\n/// where the two pieces are contiguous locations in a mappable space, in which case it just returns\n/// the containing address\n/// \\param translate is the Translate object used to find registers\n/// \\param hiaddr is the address of the most significant piece to be joined\n/// \\param hisz is the size of the most significant piece\n/// \\param loaddr is the address of the least significant piece\n/// \\param losz is the size of the least significant piece\n/// \\return an address representing the start of the joined range\nAddress AddrSpaceManager::constructJoinAddress(const Translate *translate,\n\t\t\t\t\t const Address &hiaddr,int4 hisz,\n\t\t\t\t\t const Address &loaddr,int4 losz)\n{\n spacetype hitp = hiaddr.getSpace()->getType();\n spacetype lotp = loaddr.getSpace()->getType();\n bool usejoinspace = true;\n if (((hitp != IPTR_SPACEBASE)&&(hitp != IPTR_PROCESSOR))||\n ((lotp != IPTR_SPACEBASE)&&(lotp != IPTR_PROCESSOR)))\n throw LowlevelError(\"Trying to join in appropriate locations\");\n if ((hitp == IPTR_SPACEBASE)||(lotp == IPTR_SPACEBASE)||\n (hiaddr.getSpace() == getDefaultCodeSpace())||\n (loaddr.getSpace() == getDefaultCodeSpace()))\n usejoinspace = false;\n if (hiaddr.isContiguous(hisz,loaddr,losz)) { // If we are contiguous\n if (!usejoinspace) { // and in a mappable space, just return the earliest address\n if (hiaddr.isBigEndian())\n\treturn hiaddr;\n return loaddr;\n }\n else {\t\t\t// If we are in a non-mappable (register) space, check to see if a parent register exists\n if (hiaddr.isBigEndian()) {\n\tif (translate->getRegisterName(hiaddr.getSpace(),hiaddr.getOffset(),(hisz+losz)).size() != 0)\n\t return hiaddr;\n }\n else {\n\tif (translate->getRegisterName(loaddr.getSpace(),loaddr.getOffset(),(hisz+losz)).size() != 0)\n\t return loaddr;\n }\n }\n }\n // Otherwise construct a formal JoinRecord\n vector pieces;\n pieces.emplace_back();\n pieces.emplace_back();\n pieces[0].space = hiaddr.getSpace();\n pieces[0].offset = hiaddr.getOffset();\n pieces[0].size = hisz;\n pieces[1].space = loaddr.getSpace();\n pieces[1].offset = loaddr.getOffset();\n pieces[1].size = losz;\n JoinRecord *join = findAddJoin(pieces,0);\n return join->getUnified().getAddr();\n}\n\n/// If an Address in the \\e join AddressSpace is shifted from its original offset, it may no\n/// longer have a valid JoinRecord. The shift or size change may even make the address of\n/// one of the pieces a more natural representation. Given a new Address and size, this method\n/// decides if there is a matching JoinRecord. If not it either constructs a new JoinRecord or\n/// computes the address within the containing piece. The given Address is changed if necessary\n/// either to the offset corresponding to the new JoinRecord or to a normal \\e non-join Address.\n/// \\param addr is the given Address\n/// \\param size is the size of the range in bytes\nvoid AddrSpaceManager::renormalizeJoinAddress(Address &addr,int4 size)\n\n{\n JoinRecord *joinRecord = findJoinInternal(addr.getOffset());\n if (joinRecord == (JoinRecord *)0)\n throw LowlevelError(\"Join address not covered by a JoinRecord\");\n if (addr.getOffset() == joinRecord->unified.offset && size == joinRecord->unified.size)\n return;\t\t// JoinRecord matches perfectly, no change necessary\n int4 pos1;\n Address addr1 = joinRecord->getEquivalentAddress(addr.getOffset(), pos1);\n int4 pos2;\n Address addr2 = joinRecord->getEquivalentAddress(addr.getOffset() + (size-1), pos2);\n if (addr2.isInvalid())\n throw LowlevelError(\"Join address range not covered\");\n if (pos1 == pos2) {\n addr = addr1;\n return;\n }\n vector newPieces;\n int4 sizeTrunc1 = (int4)(addr1.getOffset() - joinRecord->pieces[pos1].offset);\n int4 sizeTrunc2 = joinRecord->pieces[pos2].size - (int4)(addr2.getOffset() - joinRecord->pieces[pos2].offset) - 1;\n\n if (pos2 < pos1) {\t\t// Little endian\n newPieces.push_back(joinRecord->pieces[pos2]);\n pos2 += 1;\n while(pos2 <= pos1) {\n newPieces.push_back(joinRecord->pieces[pos2]);\n pos2 += 1;\n }\n newPieces.back().offset = addr1.getOffset();\n newPieces.back().size -= sizeTrunc1;\n newPieces.front().size -= sizeTrunc2;\n }\n else {\n newPieces.push_back(joinRecord->pieces[pos1]);\n pos1 += 1;\n while(pos1 <= pos2) {\n newPieces.push_back(joinRecord->pieces[pos1]);\n pos1 += 1;\n }\n newPieces.front().offset = addr1.getOffset();\n newPieces.front().size -= sizeTrunc1;\n newPieces.back().size -= sizeTrunc2;\n }\n JoinRecord *newJoinRecord = findAddJoin(newPieces, 0);\n addr = Address(newJoinRecord->unified.space,newJoinRecord->unified.offset);\n}\n\n/// The string \\e must contain a hexadecimal offset. The offset may be optionally prepended with \"0x\".\n/// The string may optionally start with the name of the address space to associate with the offset, followed\n/// by ':' to separate it from the offset. If the name is not present, the default data space is assumed.\n/// \\param val is the string to parse\n/// \\return the parsed address\nAddress AddrSpaceManager::parseAddressSimple(const string &val)\n\n{\n string::size_type col = val.find(':');\n AddrSpace *spc;\n if (col==string::npos) {\n spc = getDefaultDataSpace();\n col = 0;\n }\n else {\n string spcName = val.substr(0,col);\n spc = getSpaceByName(spcName);\n if (spc == (AddrSpace *)0)\n throw LowlevelError(\"Unknown address space: \" + spcName);\n col += 1;\n }\n if (col + 2 <= val.size()) {\n if (val[col] == '0' && val[col+1] == 'x')\n col += 2;\n }\n istringstream s(val.substr(col));\n uintb off;\n s >> hex >> off;\n return Address(spc,AddrSpace::addressToByte(off, spc->getWordSize()));\n}\n\n/// This constructs only a shell for the Translate object. It\n/// won't be usable until it is initialized for a specific processor\n/// The main entry point for this is the Translate::initialize method,\n/// which must be overridden by a derived class\nTranslate::Translate(void)\n\n{\n target_isbigendian = false;\n unique_base=0;\n alignment = 1;\n}\n\n/// If no floating-point format objects were registered by the \\b initialize method, this\n/// method will fill in some suitable default formats. These defaults are based on\n/// the 4-byte and 8-byte encoding specified by the IEEE 754 standard.\nvoid Translate::setDefaultFloatFormats(void)\n\n{\n if (floatformats.empty()) {\t// Default IEEE 754 float formats\n floatformats.push_back(FloatFormat(4));\n floatformats.push_back(FloatFormat(8));\n }\n}\n\n/// The pcode model for floating point encoding assumes that a\n/// consistent encoding is used for all values of a given size.\n/// This routine fetches the FloatFormat object given the size,\n/// in bytes, of the desired encoding.\n/// \\param size is the size of the floating-point value in bytes\n/// \\return a pointer to the floating-point format\nconst FloatFormat *Translate::getFloatFormat(int4 size) const\n\n{\n vector::const_iterator iter;\n\n for(iter=floatformats.begin();iter!=floatformats.end();++iter) {\n if ((*iter).getSize() == size)\n return &(*iter);\n }\n return (const FloatFormat *)0;\n}\n\n/// A convenience method for passing around p-code operations via stream.\n/// A single p-code operation is parsed from an \\ element and\n/// returned to the application via the PcodeEmit::dump method.\n/// \\param addr is the address (of the instruction) to associate with the p-code op\n/// \\param decoder is the stream decoder\nvoid PcodeEmit::decodeOp(const Address &addr,Decoder &decoder)\n\n{\n int4 opcode;\n int4 isize;\n VarnodeData outvar;\n VarnodeData invar[16];\n VarnodeData *outptr;\n\n uint4 elemId = decoder.openElement(ELEM_OP);\n isize = decoder.readSignedInteger(ATTRIB_SIZE);\n outptr = &outvar;\n if (isize <= 16)\n opcode = PcodeOpRaw::decode(decoder, isize, invar, &outptr);\n else {\n vector varStorage(isize,VarnodeData());\n opcode = PcodeOpRaw::decode(decoder, isize, varStorage.data(), &outptr);\n }\n decoder.closeElement(elemId);\n dump(addr,(OpCode)opcode,outptr,invar,isize);\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/translate.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file translate.hh\n/// \\brief Classes for disassembly and pcode generation\n///\n/// Classes for keeping track of spaces and registers (for a single architecture).\n\n#ifndef __TRANSLATE_HH__\n#define __TRANSLATE_HH__\n\n#include \"pcoderaw.hh\"\n#include \"float.hh\"\n\nnamespace ghidra {\n\nextern AttributeId ATTRIB_CODE;\t\t///< Marshaling attribute \"code\"\nextern AttributeId ATTRIB_CONTAIN;\t///< Marshaling attribute \"contain\"\nextern AttributeId ATTRIB_DEFAULTSPACE;\t///< Marshaling attribute \"defaultspace\"\nextern AttributeId ATTRIB_UNIQBASE;\t///< Marshaling attribute \"uniqbase\"\n\nextern ElementId ELEM_OP;\t\t///< Marshaling element \\\nextern ElementId ELEM_SLEIGH;\t\t///< Marshaling element \\\nextern ElementId ELEM_SPACE;\t\t///< Marshaling element \\\nextern ElementId ELEM_SPACEID;\t\t///< Marshaling element \\\nextern ElementId ELEM_SPACES;\t\t///< Marshaling element \\\nextern ElementId ELEM_SPACE_BASE;\t///< Marshaling element \\\nextern ElementId ELEM_SPACE_OTHER;\t///< Marshaling element \\\nextern ElementId ELEM_SPACE_OVERLAY;\t///< Marshaling element \\\nextern ElementId ELEM_SPACE_UNIQUE;\t///< Marshaling element \\\nextern ElementId ELEM_TRUNCATE_SPACE;\t///< Marshaling element \\\n\n// Some errors specific to the translation unit\n\n/// \\brief Exception for encountering unimplemented pcode\n///\n/// This error is thrown when a particular machine instruction\n/// cannot be translated into pcode. This particular error\n/// means that the particular instruction being decoded was valid,\n/// but the system doesn't know how to represent it in pcode.\nstruct UnimplError : public LowlevelError {\n int4 instruction_length;\t///< Number of bytes in the unimplemented instruction\n /// \\brief Constructor\n ///\n /// \\param s is a more verbose description of the error\n /// \\param l is the length (in bytes) of the unimplemented instruction\n UnimplError(const string &s,int4 l) : LowlevelError(s) { instruction_length = l; }\n};\n\n/// \\brief Exception for bad instruction data\n///\n/// This error is thrown when the system cannot decode data\n/// for a particular instruction. This usually means that the\n/// data is not really a machine instruction, but may indicate\n/// that the system is unaware of the particular instruction.\nstruct BadDataError : public LowlevelError {\n /// \\brief Constructor\n ///\n /// \\param s is a more verbose description of the error\n BadDataError(const string &s) : LowlevelError(s) {}\n};\n\nclass Translate;\n\n/// \\brief Object for describing how a space should be truncated\n///\n/// This can turn up in various XML configuration files and essentially acts\n/// as a command to override the size of an address space as defined by the architecture\nclass TruncationTag {\n string spaceName;\t///< Name of space to be truncated\n uint4 size;\t\t///< Size truncated addresses into the space\npublic:\n void decode(Decoder &decoder);\t\t\t\t///< Restore \\b this from a stream\n const string &getName(void) const { return spaceName; }\t///< Get name of address space being truncated\n uint4 getSize(void) const { return size; }\t\t\t///< Size (of pointers) for new truncated space\n};\n\n/// \\brief Abstract class for emitting pcode to an application\n///\n/// Translation engines pass back the generated pcode for an\n/// instruction to the application using this class.\nclass PcodeEmit {\npublic:\n virtual ~PcodeEmit(void) {}\t///< Virtual destructor\n\n /// \\brief The main pcode emit method.\n ///\n /// A single pcode instruction is returned to the application\n /// via this method. Particular applications override it\n /// to tailor how the operations are used.\n /// \\param addr is the Address of the machine instruction\n /// \\param opc is the opcode of the particular pcode instruction\n /// \\param outvar if not \\e null is a pointer to data about the\n /// output varnode\n /// \\param vars is a pointer to an array of VarnodeData for each\n /// input varnode\n /// \\param isize is the number of input varnodes\n virtual void dump(const Address &addr,OpCode opc,VarnodeData *outvar,VarnodeData *vars,int4 isize)=0;\n\n /// Emit pcode directly from an \\ element\n void decodeOp(const Address &addr,Decoder &decoder);\n};\n\n/// \\brief Abstract class for emitting disassembly to an application\n///\n/// Translation engines pass back the disassembly character data\n/// for decoded machine instructions to an application using this class.\nclass AssemblyEmit {\npublic:\n virtual ~AssemblyEmit(void) {} ///< Virtual destructor\n\n /// \\brief The main disassembly emitting method.\n ///\n /// The disassembly strings for a single machine instruction\n /// are passed back to an application through this method.\n /// Particular applications can tailor the use of the disassembly\n /// by overriding this method.\n /// \\param addr is the Address of the machine instruction\n /// \\param mnem is the decoded instruction mnemonic\n /// \\param body is the decode body (or operands) of the instruction\n virtual void dump(const Address &addr,const string &mnem,const string &body)=0;\n};\n\n/// \\brief Abstract class for converting native constants to addresses\n///\n/// This class is used if there is a special calculation to get from a constant embedded\n/// in the code being analyzed to the actual Address being referred to. This is used especially\n/// in the case of a segmented architecture, where \"near\" pointers must be extended to a full address\n/// with implied segment information.\nclass AddressResolver {\npublic:\n virtual ~AddressResolver(void) {} ///> Virtual destructor\n\n /// \\brief The main resolver method.\n ///\n /// Given a native constant in a specific context, resolve what address is being referred to.\n /// The constant can be a partially encoded pointer, in which case the full pointer encoding\n /// is recovered as well as the address. Whether or not a pointer is partially encoded or not\n /// is determined by the \\e sz parameter, indicating the number of bytes in the pointer. A value\n /// of -1 here indicates that the pointer is known to be a full encoding.\n /// \\param val is constant to be resolved to an address\n /// \\param sz is the size of \\e val in context (or -1).\n /// \\param point is the address at which this constant is being used\n /// \\param fullEncoding is used to hold the full pointer encoding if \\b val is a partial encoding\n /// \\return the resolved Address\n virtual Address resolve(uintb val,int4 sz,const Address &point,uintb &fullEncoding)=0;\n};\n\n/// \\brief A virtual space \\e stack space\n///\n/// In a lot of analysis situations it is convenient to extend\n/// the notion of an address space to mean bytes that are indexed\n/// relative to some base register. The canonical example of this\n/// is the \\b stack space, which models the concept of local\n/// variables stored on the stack. An address of (\\b stack, 8)\n/// might model the address of a function parameter on the stack\n/// for instance, and (\\b stack, 0xfffffff4) might be the address\n/// of a local variable. A space like this is inherently \\e virtual\n/// and contained within whatever space is being indexed into.\nclass SpacebaseSpace : public AddrSpace {\n friend class AddrSpaceManager;\n AddrSpace *contain;\t\t///< Containing space\n bool hasbaseregister;\t\t///< true if a base register has been attached\n bool isNegativeStack;\t\t///< true if stack grows in negative direction\n VarnodeData baseloc;\t\t///< location data of the base register\n VarnodeData baseOrig;\t\t///< Original base register before any truncation\n void setBaseRegister(const VarnodeData &data,int4 origSize,bool stackGrowth); ///< Set the base register at time space is created\npublic:\n SpacebaseSpace(AddrSpaceManager *m,const Translate *t,const string &nm,int4 ind,int4 sz,AddrSpace *base,int4 dl,bool isFormal);\n SpacebaseSpace(AddrSpaceManager *m,const Translate *t); ///< For use with decode\n virtual int4 numSpacebase(void) const;\n virtual const VarnodeData &getSpacebase(int4 i) const;\n virtual const VarnodeData &getSpacebaseFull(int4 i) const;\n virtual bool stackGrowsNegative(void) const { return isNegativeStack; }\n virtual AddrSpace *getContain(void) const { return contain; } ///< Return containing space\n virtual void decode(Decoder &decoder);\n};\n\n/// \\brief A record describing how logical values are split\n/// \n/// The decompiler can describe a logical value that is stored split across multiple\n/// physical memory locations. This record describes such a split. The pieces must be listed\n/// from \\e most \\e significant to \\e least \\e significant.\nclass JoinRecord {\n friend class AddrSpaceManager;\n vector pieces;\t///< All the physical pieces of the symbol, most significant to least\n VarnodeData unified; ///< Special entry representing entire symbol in one chunk\npublic:\n int4 numPieces(void) const { return pieces.size(); }\t///< Get number of pieces in this record\n bool isFloatExtension(void) const { return (pieces.size() == 1); }\t///< Does this record extend a float varnode\n const VarnodeData &getPiece(int4 i) const { return pieces[i]; }\t///< Get the i-th piece\n const VarnodeData &getUnified(void) const { return unified; }\t\t///< Get the Varnode whole\n Address getEquivalentAddress(uintb offset,int4 &pos) const;\t///< Given offset in \\e join space, get equivalent address of piece\n bool operator<(const JoinRecord &op2) const; ///< Compare records lexigraphically by pieces\n static void mergeSequence(vector &seq,const Translate *trans);\t///< Merge any contiguous ranges in a sequence\n};\n\n/// \\brief Comparator for JoinRecord objects\nstruct JoinRecordCompare {\n bool operator()(const JoinRecord *a,const JoinRecord *b) const {\n return *a < *b; }\t\t///< Compare to JoinRecords using their built-in comparison\n};\n\n/// \\brief A manager for different address spaces\n///\n/// Allow creation, lookup by name, lookup by shortcut, lookup by name, and iteration\n/// over address spaces\nclass AddrSpaceManager {\n vector baselist; ///< Every space we know about for this architecture\n vector resolvelist; ///< Special constant resolvers\n map name2Space;\t///< Map from name -> space\n map shortcut2Space;\t///< Map from shortcut -> space\n AddrSpace *constantspace;\t///< Quick reference to constant space\n AddrSpace *defaultcodespace;\t///< Default space where code lives, generally main RAM\n AddrSpace *defaultdataspace;\t///< Default space where data lives\n AddrSpace *iopspace;\t\t///< Space for internal pcode op pointers\n AddrSpace *fspecspace;\t///< Space for internal callspec pointers\n AddrSpace *joinspace;\t\t///< Space for unifying split variables\n AddrSpace *stackspace;\t///< Stack space associated with processor\n AddrSpace *uniqspace;\t\t///< Temporary space associated with processor\n uintb joinallocate;\t\t///< Next offset to be allocated in join space\n set splitset;\t///< Different splits that have been defined in join space\n vector splitlist; ///< JoinRecords indexed by join address\nprotected:\n AddrSpace *decodeSpace(Decoder &decoder,const Translate *trans); ///< Add a space to the model based an on XML tag\n void decodeSpaces(Decoder &decoder,const Translate *trans); ///< Restore address spaces in the model from a stream\n void setDefaultCodeSpace(int4 index); ///< Set the default address space (for code)\n void setDefaultDataSpace(int4 index);\t///< Set the default address space for data\n void setReverseJustified(AddrSpace *spc); ///< Set reverse justified property on this space\n void assignShortcut(AddrSpace *spc);\t///< Select a shortcut character for a new space\n void markNearPointers(AddrSpace *spc,int4 size);\t///< Mark that given space can be accessed with near pointers\n void insertSpace(AddrSpace *spc); ///< Add a new address space to the model\n void copySpaces(const AddrSpaceManager *op2);\t///< Copy spaces from another manager\n void addSpacebasePointer(SpacebaseSpace *basespace,const VarnodeData &ptrdata,int4 truncSize,bool stackGrowth); ///< Set the base register of a spacebase space\n void insertResolver(AddrSpace *spc,AddressResolver *rsolv); ///< Override the base resolver for a space\n void setInferPtrBounds(const Range &range);\t\t///< Set the range of addresses that can be inferred as pointers\n JoinRecord *findJoinInternal(uintb offset) const; ///< Find JoinRecord for \\e offset in the join space\npublic:\n AddrSpaceManager(void);\t///< Construct an empty address space manager\n virtual ~AddrSpaceManager(void); ///< Destroy the manager\n int4 getDefaultSize(void) const; ///< Get size of addresses for the default space\n AddrSpace *getSpaceByName(const string &nm) const; ///< Get address space by name\n AddrSpace *getSpaceByShortcut(char sc) const;\t///< Get address space from its shortcut\n AddrSpace *getIopSpace(void) const; ///< Get the internal pcode op space\n AddrSpace *getFspecSpace(void) const; ///< Get the internal callspec space\n AddrSpace *getJoinSpace(void) const; ///< Get the joining space\n AddrSpace *getStackSpace(void) const; ///< Get the stack space for this processor\n AddrSpace *getUniqueSpace(void) const; ///< Get the temporary register space for this processor\n AddrSpace *getDefaultCodeSpace(void) const; ///< Get the default address space of this processor\n AddrSpace *getDefaultDataSpace(void) const; ///< Get the default address space where data is stored\n AddrSpace *getConstantSpace(void) const; ///< Get the constant space\n Address getConstant(uintb val) const; ///< Get a constant encoded as an Address\n Address createConstFromSpace(AddrSpace *spc) const; ///< Create a constant address encoding an address space\n Address resolveConstant(AddrSpace *spc,uintb val,int4 sz,const Address &point,uintb &fullEncoding) const;\n int4 numSpaces(void) const; ///< Get the number of address spaces for this processor\n AddrSpace *getSpace(int4 i) const; ///< Get an address space via its index\n AddrSpace *getNextSpaceInOrder(AddrSpace *spc) const; ///< Get the next \\e contiguous address space\n JoinRecord *findAddJoin(const vector &pieces,uint4 logicalsize); ///< Get (or create) JoinRecord for \\e pieces\n JoinRecord *findJoin(uintb offset) const; ///< Find JoinRecord for \\e offset in the join space\n void setDeadcodeDelay(AddrSpace *spc,int4 delaydelta); ///< Set the deadcodedelay for a specific space\n void truncateSpace(const TruncationTag &tag);\t///< Mark a space as truncated from its original size\n\n /// \\brief Build a logically lower precision storage location for a bigger floating point register\n Address constructFloatExtensionAddress(const Address &realaddr,int4 realsize,int4 logicalsize);\n\n /// \\brief Build a logical whole from register pairs\n Address constructJoinAddress(const Translate *translate,const Address &hiaddr,int4 hisz,const Address &loaddr,int4 losz);\n\n /// \\brief Make sure a possibly offset \\e join address has a proper JoinRecord\n void renormalizeJoinAddress(Address &addr,int4 size);\n\n /// \\brief Parse a string with just an \\e address \\e space name and a hex offset\n Address parseAddressSimple(const string &val);\n};\n\n/// \\brief The interface to a translation engine for a processor.\n///\n/// This interface performs translations of instruction data\n/// for a particular processor. It has two main functions\n/// - Disassemble single machine instructions\n/// - %Translate single machine instructions into \\e pcode.\n///\n/// It is also the repository for information about the exact\n/// configuration of the reverse engineering model associated\n/// with the processor. In particular, it knows about all the\n/// address spaces, registers, and spacebases for the processor.\nclass Translate : public AddrSpaceManager {\npublic:\n /// Tagged addresses in the \\e unique address space\n enum UniqueLayout {\n RUNTIME_BOOLEAN_INVERT=0,\t\t///< Location of the runtime temporary for boolean inversion\n RUNTIME_RETURN_LOCATION=0x80,\t///< Location of the runtime temporary storing the return value\n RUNTIME_BITRANGE_EA=0x100,\t\t///< Location of the runtime temporary for storing an effective address\n INJECT=0x200,\t\t\t///< Range of temporaries for use in compiling p-code snippets\n ANALYSIS=0x10000000\t\t\t///< Range of temporaries for use during decompiler analysis\n };\nprivate:\n bool target_isbigendian;\t///< \\b true if the general endianness of the process is big endian\n uint4 unique_base;\t\t///< Starting offset into unique space\nprotected:\n int4 alignment; ///< Byte modulo on which instructions are aligned\n vector floatformats; ///< Floating point formats utilized by the processor\n\n void setBigEndian(bool val);\t///< Set general endianness to \\b big if val is \\b true\n void setUniqueBase(uint4 val); ///< Set the base offset for new temporary registers\npublic:\n Translate(void); \t\t///< Constructor for the translator\n void setDefaultFloatFormats(void); ///< If no explicit float formats, set up default formats\n bool isBigEndian(void) const; ///< Is the processor big endian?\n const FloatFormat *getFloatFormat(int4 size) const; ///< Get format for a particular floating point encoding\n int4 getAlignment(void) const; ///< Get the instruction alignment for the processor\n uint4 getUniqueBase(void) const; ///< Get the base offset for new temporary registers\n uint4 getUniqueStart(UniqueLayout layout) const;\t///< Get a tagged address within the \\e unique space\n\n /// \\brief Initialize the translator given XML configuration documents\n ///\n /// A translator gets initialized once, possibly using XML documents\n /// to configure it.\n /// \\param store is a set of configuration documents\n virtual void initialize(DocumentStorage &store)=0;\n\n /// \\brief Add a new context variable to the model for this processor\n ///\n /// Add the name of a context register used by the processor and\n /// how that register is packed into the context state. This\n /// information is used by a ContextDatabase to associate names\n /// with context information and to pack context into a single\n /// state variable for the translation engine.\n /// \\param name is the name of the new context variable\n /// \\param sbit is the first bit of the variable in the packed state\n /// \\param ebit is the last bit of the variable in the packed state\n virtual void registerContext(const string &name,int4 sbit,int4 ebit) {}\n\n /// \\brief Set the default value for a particular context variable\n ///\n /// Set the value to be returned for a context variable when\n /// there are no explicit address ranges specifying a value\n /// for the variable.\n /// \\param name is the name of the context variable\n /// \\param val is the value to be considered default\n virtual void setContextDefault(const string &name,uintm val) {}\n\n /// \\brief Toggle whether disassembly is allowed to affect context\n ///\n /// By default the disassembly/pcode translation engine can change\n /// the global context, thereby affecting later disassembly. Context\n /// may be getting determined by something other than control flow in,\n /// the disassembly, in which case this function can turn off changes\n /// made by the disassembly\n /// \\param val is \\b true to allow context changes, \\b false prevents changes\n virtual void allowContextSet(bool val) const {}\n\n /// \\brief Get a register as VarnodeData given its name\n ///\n /// Retrieve the location and size of a register given its name\n /// \\param nm is the name of the register\n /// \\return the VarnodeData for the register\n virtual const VarnodeData &getRegister(const string &nm) const=0;\n\n /// \\brief Get the name of the smallest containing register given a location and size\n ///\n /// Generic references to locations in a \\e register space are translated into the\n /// register \\e name. If a containing register isn't found, an empty string is returned.\n /// \\param base is the address space containing the location\n /// \\param off is the offset of the location\n /// \\param size is the size of the location\n /// \\return the name of the register, or an empty string\n virtual string getRegisterName(AddrSpace *base,uintb off,int4 size) const=0;\n\n /// \\brief Get the name of a register with an exact location and size\n ///\n /// If a register exists with the given location and size, return the name of the register.\n /// Otherwise return the empty string.\n /// \\param base is the address space containing the location\n /// \\param off is the offset of the location\n /// \\param size is the size of the location\n /// \\return the name of the register, or an empty string\n virtual string getExactRegisterName(AddrSpace *base,uintb off,int4 size) const=0;\n\n /// \\brief Get a list of all register names and the corresponding location\n ///\n /// Most processors have a list of named registers and possibly other memory locations\n /// that are specific to it. This function populates a map from the location information\n /// to the name, for every named location known by the translator\n /// \\param reglist is the map which will be populated by the call\n virtual void getAllRegisters(map ®list) const=0;\n\n /// \\brief Get a list of all \\e user-defined pcode ops\n ///\n /// The pcode model allows processors to define new pcode\n /// instructions that are specific to that processor. These\n /// \\e user-defined instructions are all identified by a name\n /// and an index. This method returns a list of these ops\n /// in index order.\n /// \\param res is the resulting vector of user op names\n virtual void getUserOpNames(vector &res) const=0;\n\n /// \\brief Get the length of a machine instruction\n ///\n /// This method decodes an instruction at a specific address\n /// just enough to find the number of bytes it uses within the\n /// instruction stream.\n /// \\param baseaddr is the Address of the instruction\n /// \\return the number of bytes in the instruction\n virtual int4 instructionLength(const Address &baseaddr) const=0;\n\n /// \\brief Transform a single machine instruction into pcode\n ///\n /// This is the main interface to the pcode translation engine.\n /// The \\e dump method in the \\e emit object is invoked exactly\n /// once for each pcode operation in the translation for the\n /// machine instruction at the given address.\n /// This routine can throw either\n /// - UnimplError or\n /// - BadDataError\n ///\n /// \\param emit is the tailored pcode emitting object\n /// \\param baseaddr is the Address of the machine instruction\n /// \\return the number of bytes in the machine instruction\n virtual int4 oneInstruction(PcodeEmit &emit,const Address &baseaddr) const=0;\n\n /// \\brief Disassemble a single machine instruction\n ///\n /// This is the main interface to the disassembler for the\n /// processor. It disassembles a single instruction and\n /// returns the result to the application via the \\e dump\n /// method in the \\e emit object.\n /// \\param emit is the disassembly emitting object\n /// \\param baseaddr is the address of the machine instruction to disassemble\n virtual int4 printAssembly(AssemblyEmit &emit,const Address &baseaddr) const=0;\n};\n\n/// Return the size of addresses for the processor's official\n/// default space. This space is usually the main RAM databus.\n/// \\return the size of an address in bytes\ninline int4 AddrSpaceManager::getDefaultSize(void) const {\n return defaultcodespace->getAddrSize();\n}\n\n/// There is a special address space reserved for encoding pointers\n/// to pcode operations as addresses. This allows a direct pointer\n/// to be \\e hidden within an operation, when manipulating pcode\n/// internally. (See IopSpace)\n/// \\return a pointer to the address space\ninline AddrSpace *AddrSpaceManager::getIopSpace(void) const {\n return iopspace;\n}\n\n/// There is a special address space reserved for encoding pointers\n/// to the FuncCallSpecs object as addresses. This allows direct\n/// pointers to be \\e hidden within an operation, when manipulating\n/// pcode internally. (See FspecSpace)\n/// \\return a pointer to the address space\ninline AddrSpace *AddrSpaceManager::getFspecSpace(void) const {\n return fspecspace;\n}\n\n/// There is a special address space reserved for providing a \n/// logical contiguous memory location for variables that are\n/// really split between two physical locations. This allows the\n/// the decompiler to work with the logical value. (See JoinSpace)\n/// \\return a pointer to the address space\ninline AddrSpace *AddrSpaceManager::getJoinSpace(void) const {\n return joinspace;\n}\n\n/// Most processors have registers and instructions that are\n/// reserved for implementing a stack. In the pcode translation,\n/// these are translated into locations and operations on a\n/// dedicated \\b stack address space. (See SpacebaseSpace)\n/// \\return a pointer to the \\b stack space\ninline AddrSpace *AddrSpaceManager::getStackSpace(void) const {\n return stackspace;\n}\n\n/// Both the pcode translation process and the simplification\n/// process need access to a pool of temporary registers that\n/// can be used for moving data around without affecting the\n/// address spaces used to formally model the processor's RAM\n/// and registers. These temporary locations are all allocated\n/// from a dedicated address space, referred to as the \\b unique\n/// space. (See UniqueSpace)\n/// \\return a pointer to the \\b unique space\ninline AddrSpace *AddrSpaceManager::getUniqueSpace(void) const {\n return uniqspace;\n}\n\n/// Most processors have a main address bus, on which the bulk\n/// of the processor's RAM is mapped. This matches SLEIGH's notion\n/// of the \\e default space. For Harvard architectures, this is the\n/// space where code exists (as opposed to data).\n/// \\return a pointer to the \\e default code space\ninline AddrSpace *AddrSpaceManager::getDefaultCodeSpace(void) const {\n return defaultcodespace;\n}\n\n/// Return the default address space for holding data. For most processors, this\n/// is just the main RAM space and is the same as the default \\e code space.\n/// For Harvard architectures, this is the space where data is stored\n/// (as opposed to code).\n/// \\return a pointer to the \\e default data space\ninline AddrSpace *AddrSpaceManager::getDefaultDataSpace(void) const {\n return defaultdataspace;\n}\n\n/// Pcode represents constant values within an operation as\n/// offsets within a special \\e constant address space. \n/// (See ConstantSpace)\n/// \\return a pointer to the \\b constant space\ninline AddrSpace *AddrSpaceManager::getConstantSpace(void) const {\n return constantspace;\n}\n\n/// This routine encodes a specific value as a \\e constant\n/// address. I.e. the address space of the resulting Address\n/// will be the \\b constant space, and the offset will be the\n/// value.\n/// \\param val is the constant value to encode\n/// \\return the \\e constant address\ninline Address AddrSpaceManager::getConstant(uintb val) const {\n return Address(constantspace,val);\n}\n\n/// This routine is used to encode a pointer to an address space\n/// as a \\e constant Address, for use in \\b LOAD and \\b STORE\n/// operations. This is used internally and is slightly more\n/// efficient than storing the formal index of the space\n/// param spc is the space pointer to be encoded\n/// \\return the encoded Address\ninline Address AddrSpaceManager::createConstFromSpace(AddrSpace *spc) const {\n return Address(constantspace,(uintb)(uintp)spc);\n}\n\n/// This returns the total number of address spaces used by the\n/// processor, including all special spaces, like the \\b constant\n/// space and the \\b iop space. \n/// \\return the number of spaces\ninline int4 AddrSpaceManager::numSpaces(void) const {\n return baselist.size();\n}\n\n/// This retrieves a specific address space via its formal index.\n/// All spaces have an index, and in conjunction with the numSpaces\n/// method, this method can be used to iterate over all spaces.\n/// \\param i is the index of the address space\n/// \\return a pointer to the desired space\ninline AddrSpace *AddrSpaceManager::getSpace(int4 i) const {\n return baselist[i];\n}\n\n/// Although endianness is usually specified on the space, most languages set an endianness\n/// across the entire processor. This routine sets the endianness to \\b big if the -val-\n/// is passed in as \\b true. Otherwise, the endianness is set to \\b small.\n/// \\param val is \\b true if the endianness should be set to \\b big\ninline void Translate::setBigEndian(bool val) {\n target_isbigendian = val; \n}\n\n/// The \\e unique address space, for allocating temporary registers,\n/// is used for both registers needed by the pcode translation\n/// engine and, later, by the simplification engine. This routine\n/// sets the boundary of the portion of the space allocated\n/// for the pcode engine, and sets the base offset where registers\n/// created by the simplification process can start being allocated.\n/// \\param val is the boundary offset\ninline void Translate::setUniqueBase(uint4 val) {\n if (val>unique_base) unique_base = val;\n}\n\n/// Processors can usually be described as using a big endian\n/// encoding or a little endian encoding. This routine returns\n/// \\b true if the processor globally uses big endian encoding.\n/// \\return \\b true if big endian\ninline bool Translate::isBigEndian(void) const {\n return target_isbigendian;\n}\n\n/// If machine instructions need to have a specific alignment\n/// for this processor, this routine returns it. I.e. a return\n/// value of 4, means that the address of all instructions\n/// must be a multiple of 4. If there is no\n/// specific alignment requirement, this routine returns 1.\n/// \\return the instruction alignment\ninline int4 Translate::getAlignment(void) const {\n return alignment;\n}\n\n/// Return the first offset within the \\e unique space after the range statically reserved by Translate.\n/// This is generally the starting offset where dynamic temporary registers can start to be allocated.\n/// \\return the first allocatable offset\ninline uint4 Translate::getUniqueBase(void) const {\n return unique_base;\n}\n\n/// Regions of the \\e unique space are reserved for specific uses. We select the start of a specific\n/// region based on the given tag.\n/// \\param layout is the given tag\n/// \\return the absolute offset into the \\e unique space\ninline uint4 Translate::getUniqueStart(UniqueLayout layout) const {\n return (layout != ANALYSIS) ? layout + unique_base : layout;\n}\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/types.h", "content": "/* ###\n * IP: GHIDRA\n * NOTE: Decompiler specific flags, refers to sparc,linux,windows,i386,apple,alpha,powerpc\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/* typedefs for getting specific word sizes */\n\n#ifndef __TYPES_H__\n#define __TYPES_H__\n\n#include \n\nnamespace ghidra {\n\n// Use of uintm and intm is deprecated. They must currently be set to be 32-bit.\ntypedef uint32_t uintm;\ntypedef int32_t intm;\n\ntypedef uint64_t uint8;\ntypedef int64_t int8;\ntypedef uint32_t uint4;\ntypedef int32_t int4;\ntypedef uint16_t uint2;\ntypedef int16_t int2;\ntypedef uint8_t uint1;\ntypedef int8_t int1;\n\n/* uintp is intended to be an unsigned integer that is the same size as a pointer */\ntypedef uintptr_t uintp;\n\n#if defined (__x86_64__) || defined (__i386__)\n#define HOST_ENDIAN 0\n\n#else // other platforms (not compatible with g++ 4.8.5)\nclass Endian {\npublic:\n static constexpr const union { int4 whole; int1 part[4]; } host = { 1 };\n};\n#define HOST_ENDIAN Endian::host.part[3]\n#endif\n\n#if defined(_WINDOWS)\n#pragma warning (disable:4312)\n#pragma warning (disable:4311)\n#pragma warning (disable:4267)\n#pragma warning (disable:4018)\n#pragma warning (disable:4244)\n\n/*\n The windows standard template library list implementation seems to have a philosophical difference with\n the standard regarding the validity of iterators pointing to objects that are moved between containers\n (via the splice method) These defines turn off the validity checks\n (These have been moved to the VC project spec)\n */\n//#define _SECURE_SCL 0\n//#define _HAS_ITERATOR_DEBUGGING 0\n#endif\n\n/*\n Big integers: These are intended to be arbitrary precison integers. However\n for efficiency, these are currently implemented as fixed precision.\n So for coding purposes, these should be interpreted as fixed\n precision integers that store as big a number as you would ever need.\n*/\n\ntypedef int8 intb;\t\t/* This is a signed big integer */\ntypedef uint8 uintb;\t\t/* This is an unsigned big integer */\n\n/*\n\nOther compilation flags\n\nCPUI_DEBUG -- This is the ONE debug switch that should be passed in\n from the compiler, all others are controlled below\n*/\n\n#ifdef CPUI_DEBUG\n# define OPACTION_DEBUG\n# define PRETTY_DEBUG\n# define TYPEPROP_DEBUG\n//# define __REMOTE_SOCKET__\n//# define DFSVERIFY_DEBUG\n//# define BLOCKCONSISTENT_DEBUG\n//# define MERGEMULTI_DEBUG\n//# define VARBANK_DEBUG\n#endif\n\n} // End namespace ghidra\n\n#endif\n" }, { "path": "pypcode/sleigh/xml.cc", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/* A Bison parser, made by GNU Bison 3.0.4. */\n\n/* Bison implementation for Yacc-like parsers in C\n\n Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.\n\n This program is free software: you can redistribute it and/or modify\n it under the terms of the GNU General Public License as published by\n the Free Software Foundation, either version 3 of the License, or\n (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program. If not, see . */\n\n/* As a special exception, you may create a larger work that contains\n part or all of the Bison parser skeleton and distribute that work\n under terms of your choice, so long as that work isn't itself a\n parser generator using the skeleton or a modified version thereof\n as a parser skeleton. Alternatively, if you modify or redistribute\n the parser skeleton itself, you may (at your option) remove this\n special exception, which will cause the skeleton and the resulting\n Bison output files to be licensed under the GNU General Public\n License without this special exception.\n\n This special exception was added by the Free Software Foundation in\n version 2.2 of Bison. */\n\n/* C LALR(1) parser skeleton written by Richard Stallman, by\n simplifying the original so-called \"semantic\" parser. */\n\n/* All symbols defined below should begin with yy or YY, to avoid\n infringing on user name space. This should be done even for local\n variables, as they might otherwise be expanded by user macros.\n There are some unavoidable exceptions within include files to\n define necessary library symbols; they are noted \"INFRINGES ON\n USER NAME SPACE\" below. */\n\n/* Identify Bison output. */\n#define YYBISON 1\n\n/* Bison version. */\n#define YYBISON_VERSION \"3.0.4\"\n\n/* Skeleton name. */\n#define YYSKELETON_NAME \"yacc.c\"\n\n/* Pure parsers. */\n#define YYPURE 0\n\n/* Push parsers. */\n#define YYPUSH 0\n\n/* Pull parsers. */\n#define YYPULL 1\n\n/* Substitute the type names. */\n#define YYSTYPE XMLSTYPE\n/* Substitute the variable and function names. */\n#define yyparse xmlparse\n#define yylex xmllex\n#define yyerror xmlerror\n#define yydebug xmldebug\n#define yynerrs xmlnerrs\n\n#define yylval xmllval\n#define yychar xmlchar\n\n/* Copy the first part of user declarations. */\n\n\n#include \"xml.hh\"\n// CharData mode look for '<' '&' or \"]]>\"\n// Name mode look for non-name char\n// CData mode looking for \"]]>\"\n// Entity mode looking for ending ';'\n// AttValue mode looking for endquote or '&'\n// Comment mode looking for \"--\"\n\n#include \n#include \n#include \n#include \n\nnamespace ghidra {\n\nstring Attributes::bogus_uri(\"http://unused.uri\");\n\n/// \\brief The XML character scanner\n///\n/// Tokenize a byte stream suitably for the main XML parser. The scanner expects an ASCII or UTF-8\n/// encoding. Characters is XML tag and attribute names are restricted to ASCII \"letters\", but\n/// extended UTF-8 characters can be used in any other character data: attribute values, content, comments. \nclass XmlScan {\npublic:\n /// \\brief Modes of the scanner\n enum mode { CharDataMode, CDataMode, AttValueSingleMode,\n\t AttValueDoubleMode, CommentMode, CharRefMode,\n\t NameMode, SNameMode, SingleMode };\n /// \\brief Additional tokens returned by the scanner, in addition to byte values 00-ff\n enum token { CharDataToken = 258,\n\t CDataToken = 259,\n\t AttValueToken = 260,\n\t CommentToken =261,\n\t CharRefToken = 262,\n\t NameToken = 263,\n\t SNameToken = 264,\n\t ElementBraceToken = 265,\n\t CommandBraceToken = 266 };\nprivate:\n mode curmode;\t\t\t///< The current scanning mode\n istream &s;\t\t\t///< The stream being scanned\n string *lvalue;\t\t///< Current string being built\n int4 lookahead[4];\t///< Lookahead into the byte stream\n int4 pos;\t\t\t\t///< Current position in the lookahead buffer\n bool endofstream;\t\t///< Has end of stream been reached\n void clearlvalue(void);\t///< Clear the current token string\n\n /// \\brief Get the next byte in the stream\n ///\n /// Maintain a lookahead of 4 bytes at all times so that we can check for special\n /// XML character sequences without consuming.\n /// \\return the next byte value as an integer\n int4 getxmlchar(void) {\n char c;\t \n int4 ret=lookahead[pos];\n if (!endofstream) {\n s.get(c); \n if (s.eof()||(c=='\\0')) {\n\tendofstream = true;\n\tlookahead[pos] = '\\n';\n }\n else\n\tlookahead[pos] = c;\n }\n else\n lookahead[pos] = -1;\n pos = (pos+1)&3;\n return ret;\n }\n int4 next(int4 i) { return lookahead[(pos+i)&3]; }\t///< Peek at the next (i-th) byte without consuming\n bool isLetter(int4 val) { return (((val>=0x41)&&(val<=0x5a))||((val>=0x61)&&(val<=0x7a))); }\t///< Is the given byte a \\e letter\n bool isInitialNameChar(int4 val);\t\t///< Is the given byte/character the valid start of an XML name\n bool isNameChar(int4 val);\t\t\t///< Is the given byte/character valid for an XML name\t\n bool isChar(int4 val);\t\t\t\t///< Is the given byte/character valid as an XML character\n int4 scanSingle(void);\t\t\t\t///< Scan for the next token in Single Character mode\n int4 scanCharData(void);\t\t\t\t///< Scan for the next token is Character Data mode\n int4 scanCData(void);\t\t\t\t\t///< Scan for the next token in CDATA mode\n int4 scanAttValue(int4 quote);\t\t///< Scan for the next token in Attribute Value mode\n int4 scanCharRef(void);\t\t\t\t///< Scan for the next token in Character Reference mode\n int4 scanComment(void);\t\t\t\t///< Scan for the next token in Comment mode\n int4 scanName(void);\t\t\t\t\t///< Scan a Name or return single non-name character\n int4 scanSName(void);\t\t\t\t\t///< Scan Name, allow white space before\npublic:\n XmlScan(istream &t);\t\t\t\t\t///< Construct scanner given a stream\n ~XmlScan(void);\t\t\t\t\t\t///< Destructor\n void setmode(mode m) { curmode = m; }\t///< Set the scanning mode\n int4 nexttoken(void);\t\t\t\t\t///< Get the next token\n string *lval(void) { string *ret = lvalue; lvalue = (string *)0; return ret; }\t///< Return the last \\e lvalue string\n};\n\n/// \\brief A parsed name/value pair\nstruct NameValue {\n string *name;\t\t///< The name\n string *value;\t///< The value\n};\n\nextern int xmllex(void);\t\t\t\t///< Interface to the scanner\nextern int xmlerror(const char *str);\t\t\t///< Interface for registering an error in parsing\nextern void print_content(const string &str);\t///< Send character data to the ContentHandler\nextern int4 convertEntityRef(const string &ref);\t///< Convert an XML entity to its equivalent character\nextern int4 convertCharRef(const string &ref);\t///< Convert an XML character reference to its equivalent character\nstatic XmlScan *global_scan;\t\t\t\t\t///< Global reference to the scanner\nstatic ContentHandler *handler;\t\t\t\t\t///< Global reference to the content handler\nstatic std::mutex global_scan_mutex;\nstatic std::mutex handler_mutex;\n\n\n\n# ifndef YY_NULLPTR\n# if defined __cplusplus && 201103L <= __cplusplus\n# define YY_NULLPTR nullptr\n# else\n# define YY_NULLPTR 0\n# endif\n# endif\n\n/* Enabling verbose error messages. */\n#ifdef YYERROR_VERBOSE\n# undef YYERROR_VERBOSE\n# define YYERROR_VERBOSE 1\n#else\n# define YYERROR_VERBOSE 0\n#endif\n\n\n/* Debug traces. */\n#ifndef XMLDEBUG\n# if defined YYDEBUG\n#if YYDEBUG\n# define XMLDEBUG 1\n# else\n# define XMLDEBUG 0\n# endif\n# else /* ! defined YYDEBUG */\n# define XMLDEBUG 0\n# endif /* ! defined YYDEBUG */\n#endif /* ! defined XMLDEBUG */\n#if XMLDEBUG\nextern int xmldebug;\n#endif\n\n/* Token type. */\n#ifndef XMLTOKENTYPE\n# define XMLTOKENTYPE\n enum xmltokentype\n {\n CHARDATA = 258,\n CDATA = 259,\n ATTVALUE = 260,\n COMMENT = 261,\n CHARREF = 262,\n NAME = 263,\n SNAME = 264,\n ELEMBRACE = 265,\n COMMBRACE = 266\n };\n#endif\n\n/* Value type. */\n#if ! defined XMLSTYPE && ! defined XMLSTYPE_IS_DECLARED\n\nunion XMLSTYPE\n{\n\n\n int4 i;\n string *str;\n Attributes *attr;\n NameValue *pair;\n\n\n};\n\ntypedef union XMLSTYPE XMLSTYPE;\n# define XMLSTYPE_IS_TRIVIAL 1\n# define XMLSTYPE_IS_DECLARED 1\n#endif\n\n\nextern XMLSTYPE xmllval;\n\nint xmlparse (void);\n\n\n\n/* Copy the second part of user declarations. */\n\n\n\n#ifdef short\n# undef short\n#endif\n\n#ifdef YYTYPE_UINT8\ntypedef YYTYPE_UINT8 yytype_uint8;\n#else\ntypedef unsigned char yytype_uint8;\n#endif\n\n#ifdef YYTYPE_INT8\ntypedef YYTYPE_INT8 yytype_int8;\n#else\ntypedef signed char yytype_int8;\n#endif\n\n#ifdef YYTYPE_UINT16\ntypedef YYTYPE_UINT16 yytype_uint16;\n#else\ntypedef unsigned short int yytype_uint16;\n#endif\n\n#ifdef YYTYPE_INT16\ntypedef YYTYPE_INT16 yytype_int16;\n#else\ntypedef short int yytype_int16;\n#endif\n\n#ifndef YYSIZE_T\n# ifdef __SIZE_TYPE__\n# define YYSIZE_T __SIZE_TYPE__\n# elif defined size_t\n# define YYSIZE_T size_t\n# elif ! defined YYSIZE_T\n# include /* INFRINGES ON USER NAME SPACE */\n# define YYSIZE_T size_t\n# else\n# define YYSIZE_T unsigned int\n# endif\n#endif\n\n#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)\n\n#ifndef YY_\n# if defined YYENABLE_NLS && YYENABLE_NLS\n# if ENABLE_NLS\n# include /* INFRINGES ON USER NAME SPACE */\n# define YY_(Msgid) dgettext (\"bison-runtime\", Msgid)\n# endif\n# endif\n# ifndef YY_\n# define YY_(Msgid) Msgid\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE\n# if (defined __GNUC__ \\\n && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \\\n || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C\n# define YY_ATTRIBUTE(Spec) __attribute__(Spec)\n# else\n# define YY_ATTRIBUTE(Spec) /* empty */\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE_PURE\n# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__))\n#endif\n\n#ifndef YY_ATTRIBUTE_UNUSED\n# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__))\n#endif\n\n#if !defined _Noreturn \\\n && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112)\n# if defined _MSC_VER && 1200 <= _MSC_VER\n# define _Noreturn __declspec (noreturn)\n# else\n# define _Noreturn YY_ATTRIBUTE ((__noreturn__))\n# endif\n#endif\n\n/* Suppress unused-variable warnings by \"using\" E. */\n#if ! defined lint || defined __GNUC__\n# define YYUSE(E) ((void) (E))\n#else\n# define YYUSE(E) /* empty */\n#endif\n\n#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__\n/* Suppress an incorrect diagnostic about yylval being uninitialized. */\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \\\n _Pragma (\"GCC diagnostic push\") \\\n _Pragma (\"GCC diagnostic ignored \\\"-Wuninitialized\\\"\")\\\n _Pragma (\"GCC diagnostic ignored \\\"-Wmaybe-uninitialized\\\"\")\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END \\\n _Pragma (\"GCC diagnostic pop\")\n#else\n# define YY_INITIAL_VALUE(Value) Value\n#endif\n#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END\n#endif\n#ifndef YY_INITIAL_VALUE\n# define YY_INITIAL_VALUE(Value) /* Nothing. */\n#endif\n\n\n#if ! defined yyoverflow || YYERROR_VERBOSE\n\n/* The parser invokes alloca or malloc; define the necessary symbols. */\n\n# ifdef YYSTACK_USE_ALLOCA\n# if YYSTACK_USE_ALLOCA\n# ifdef __GNUC__\n# define YYSTACK_ALLOC __builtin_alloca\n# elif defined __BUILTIN_VA_ARG_INCR\n# include /* INFRINGES ON USER NAME SPACE */\n# elif defined _AIX\n# define YYSTACK_ALLOC __alloca\n# elif defined _MSC_VER\n# include /* INFRINGES ON USER NAME SPACE */\n# define alloca _alloca\n# else\n# define YYSTACK_ALLOC alloca\n# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS\n# include /* INFRINGES ON USER NAME SPACE */\n /* Use EXIT_SUCCESS as a witness for stdlib.h. */\n# ifndef EXIT_SUCCESS\n# define EXIT_SUCCESS 0\n# endif\n# endif\n# endif\n# endif\n# endif\n\n# ifdef YYSTACK_ALLOC\n /* Pacify GCC's 'empty if-body' warning. */\n# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)\n# ifndef YYSTACK_ALLOC_MAXIMUM\n /* The OS might guarantee only one guard page at the bottom of the stack,\n and a page size can be as small as 4096 bytes. So we cannot safely\n invoke alloca (N) if N exceeds 4096. Use a slightly smaller number\n to allow for a few compiler-allocated temporary stack slots. */\n# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */\n# endif\n# else\n# define YYSTACK_ALLOC YYMALLOC\n# define YYSTACK_FREE YYFREE\n# ifndef YYSTACK_ALLOC_MAXIMUM\n# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM\n# endif\n# if (defined __cplusplus && ! defined EXIT_SUCCESS \\\n && ! ((defined YYMALLOC || defined malloc) \\\n && (defined YYFREE || defined free)))\n# include /* INFRINGES ON USER NAME SPACE */\n# ifndef EXIT_SUCCESS\n# define EXIT_SUCCESS 0\n# endif\n# endif\n# ifndef YYMALLOC\n# define YYMALLOC malloc\n# if ! defined malloc && ! defined EXIT_SUCCESS\nvoid *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */\n# endif\n# endif\n# ifndef YYFREE\n# define YYFREE free\n# if ! defined free && ! defined EXIT_SUCCESS\nvoid free (void *); /* INFRINGES ON USER NAME SPACE */\n# endif\n# endif\n# endif\n#endif /* ! defined yyoverflow || YYERROR_VERBOSE */\n\n\n#if (! defined yyoverflow \\\n && (! defined __cplusplus \\\n || (defined XMLSTYPE_IS_TRIVIAL && XMLSTYPE_IS_TRIVIAL)))\n\n/* A type that is properly aligned for any stack member. */\nunion yyalloc\n{\n yytype_int16 yyss_alloc;\n YYSTYPE yyvs_alloc;\n};\n\n/* The size of the maximum gap between one aligned stack and the next. */\n# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)\n\n/* The size of an array large to enough to hold all stacks, each with\n N elements. */\n# define YYSTACK_BYTES(N) \\\n ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \\\n + YYSTACK_GAP_MAXIMUM)\n\n# define YYCOPY_NEEDED 1\n\n/* Relocate STACK from its old location to the new one. The\n local variables YYSIZE and YYSTACKSIZE give the old and new number of\n elements in the stack, and YYPTR gives the new location of the\n stack. Advance YYPTR to a properly aligned location for the next\n stack. */\n# define YYSTACK_RELOCATE(Stack_alloc, Stack) \\\n do \\\n { \\\n YYSIZE_T yynewbytes; \\\n YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \\\n Stack = &yyptr->Stack_alloc; \\\n yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \\\n yyptr += yynewbytes / sizeof (*yyptr); \\\n } \\\n while (0)\n\n#endif\n\n#if defined YYCOPY_NEEDED && YYCOPY_NEEDED\n/* Copy COUNT objects from SRC to DST. The source and destination do\n not overlap. */\n# ifndef YYCOPY\n# if defined __GNUC__ && 1 < __GNUC__\n# define YYCOPY(Dst, Src, Count) \\\n __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))\n# else\n# define YYCOPY(Dst, Src, Count) \\\n do \\\n { \\\n YYSIZE_T yyi; \\\n for (yyi = 0; yyi < (Count); yyi++) \\\n (Dst)[yyi] = (Src)[yyi]; \\\n } \\\n while (0)\n# endif\n# endif\n#endif /* !YYCOPY_NEEDED */\n\n/* YYFINAL -- State number of the termination state. */\n#define YYFINAL 25\n/* YYLAST -- Last index in YYTABLE. */\n#define YYLAST 205\n\n/* YYNTOKENS -- Number of terminals. */\n#define YYNTOKENS 50\n/* YYNNTS -- Number of nonterminals. */\n#define YYNNTS 37\n/* YYNRULES -- Number of rules. */\n#define YYNRULES 70\n/* YYNSTATES -- Number of states. */\n#define YYNSTATES 151\n\n/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned\n by yylex, with out-of-bounds checking. */\n#define YYUNDEFTOK 2\n#define YYMAXUTOK 266\n\n#define YYTRANSLATE(YYX) \\\n ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)\n\n/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM\n as returned by yylex, without out-of-bounds checking. */\nstatic const yytype_uint8 yytranslate[] =\n{\n 0, 2, 2, 2, 2, 2, 2, 2, 2, 15,\n 13, 2, 2, 14, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 12, 18, 17, 48, 2, 2, 47, 16,\n 2, 2, 2, 2, 2, 19, 2, 46, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 49,\n 2, 32, 20, 21, 2, 25, 2, 23, 24, 31,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 28,\n 30, 2, 2, 2, 26, 2, 2, 2, 2, 29,\n 2, 22, 2, 27, 2, 2, 2, 2, 2, 40,\n 41, 34, 2, 42, 2, 37, 2, 2, 45, 44,\n 39, 38, 2, 2, 35, 36, 2, 2, 33, 2,\n 43, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\n 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,\n 5, 6, 7, 8, 9, 10, 11\n};\n\n#if XMLDEBUG\n /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */\nstatic const yytype_uint8 yyrline[] =\n{\n 0, 141, 141, 142, 143, 144, 145, 146, 147, 148,\n 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,\n 160, 161, 162, 163, 164, 166, 167, 168, 169, 170,\n 171, 172, 174, 175, 176, 177, 178, 179, 180, 182,\n 183, 184, 185, 186, 187, 188, 190, 191, 193, 194,\n 195, 196, 198, 199, 200, 201, 202, 203, 205, 206,\n 207, 208, 209, 210, 211, 213, 214, 216, 217, 218,\n 219\n};\n#endif\n\n#if XMLDEBUG || YYERROR_VERBOSE || 0\n/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.\n First, the terminals, then, starting at YYNTOKENS, nonterminals. */\nstatic const char *const yytname[] =\n{\n \"$end\", \"error\", \"$undefined\", \"CHARDATA\", \"CDATA\", \"ATTVALUE\",\n \"COMMENT\", \"CHARREF\", \"NAME\", \"SNAME\", \"ELEMBRACE\", \"COMMBRACE\", \"' '\",\n \"'\\\\n'\", \"'\\\\r'\", \"'\\\\t'\", \"'\\\\''\", \"'\\\"'\", \"'!'\", \"'-'\", \"'>'\", \"'?'\",\n \"'['\", \"'C'\", \"'D'\", \"'A'\", \"'T'\", \"']'\", \"'O'\", \"'Y'\", \"'P'\", \"'E'\",\n \"'='\", \"'v'\", \"'e'\", \"'r'\", \"'s'\", \"'i'\", \"'o'\", \"'n'\", \"'c'\", \"'d'\",\n \"'g'\", \"'x'\", \"'m'\", \"'l'\", \"'/'\", \"'&'\", \"'#'\", \"';'\", \"$accept\",\n \"document\", \"whitespace\", \"S\", \"attsinglemid\", \"attdoublemid\",\n \"AttValue\", \"elemstart\", \"commentstart\", \"Comment\", \"PI\", \"CDSect\",\n \"CDStart\", \"CDEnd\", \"doctypepro\", \"prologpre\", \"prolog\", \"doctypedecl\",\n \"Eq\", \"Misc\", \"VersionInfo\", \"EncodingDecl\", \"xmldeclstart\", \"XMLDecl\",\n \"element\", \"STag\", \"EmptyElemTag\", \"stagstart\", \"SAttribute\",\n \"etagbrace\", \"ETag\", \"content\", \"Reference\", \"refstart\", \"charrefstart\",\n \"CharRef\", \"EntityRef\", YY_NULLPTR\n};\n#endif\n\n# ifdef YYPRINT\n/* YYTOKNUM[NUM] -- (External) token number corresponding to the\n (internal) symbol number NUM (which must be that of a token). */\nstatic const yytype_uint16 yytoknum[] =\n{\n 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,\n 265, 266, 32, 10, 13, 9, 39, 34, 33, 45,\n 62, 63, 91, 67, 68, 65, 84, 93, 79, 89,\n 80, 69, 61, 118, 101, 114, 115, 105, 111, 110,\n 99, 100, 103, 120, 109, 108, 47, 38, 35, 59\n};\n# endif\n\n#define YYPACT_NINF -136\n\n#define yypact_value_is_default(Yystate) \\\n (!!((Yystate) == (-136)))\n\n#define YYTABLE_NINF -1\n\n#define yytable_value_is_error(Yytable_value) \\\n 0\n\n /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing\n STATE-NUM. */\nstatic const yytype_int16 yypact[] =\n{\n 132, -136, 42, -136, -136, -136, -136, 22, -136, 125,\n 9, 20, -136, -136, 143, 28, -136, 79, -136, 148,\n -136, -136, 16, 18, 6, -136, -136, -136, 32, 65,\n 148, -136, -136, 148, 38, 40, 93, 91, -136, -1,\n 63, -136, 39, 27, -136, 45, 26, 52, -12, -136,\n -136, -136, -136, 69, 57, 77, 104, -136, -3, -136,\n -136, -136, -136, 94, -136, 95, -136, -136, -4, 103,\n -136, -136, -136, 67, 136, -136, -136, 106, -136, 68,\n 109, 87, -136, 90, -136, 144, 2, -136, 138, 108,\n 117, -136, 118, -136, -136, -136, 125, -2, 3, -136,\n -136, 125, -136, 145, 131, -136, 147, 146, -136, -136,\n 121, -136, -136, -136, -136, -136, -136, -136, -136, 54,\n -136, 149, 130, 150, 152, -136, 142, 151, 140, 153,\n -136, 154, 155, 156, 157, 158, 159, 137, 161, 160,\n -136, 63, 162, 163, 136, -136, 164, -136, 63, 136,\n -136\n};\n\n /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.\n Performed when YYTABLE does not specify something else to do. Zero\n means the default is an error. */\nstatic const yytype_uint8 yydefact[] =\n{\n 0, 18, 0, 4, 5, 6, 7, 0, 8, 38,\n 0, 0, 36, 37, 31, 0, 28, 0, 27, 0,\n 58, 46, 0, 0, 21, 1, 9, 52, 0, 0,\n 30, 25, 29, 0, 0, 0, 0, 0, 2, 0,\n 0, 48, 0, 0, 53, 0, 0, 0, 0, 21,\n 26, 3, 42, 0, 0, 0, 0, 59, 0, 67,\n 64, 63, 62, 0, 60, 0, 47, 61, 0, 0,\n 66, 65, 33, 0, 0, 50, 49, 0, 19, 0,\n 0, 0, 43, 0, 44, 0, 0, 55, 0, 0,\n 0, 68, 0, 34, 10, 13, 35, 0, 0, 54,\n 51, 0, 20, 0, 0, 45, 0, 0, 22, 56,\n 0, 70, 69, 11, 16, 12, 14, 17, 15, 0,\n 41, 0, 0, 0, 0, 57, 0, 0, 0, 0,\n 24, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 32, 0, 0, 0, 0, 23, 0, 40, 0, 0,\n 39\n};\n\n /* YYPGOTO[NTERM-NUM]. */\nstatic const yytype_int16 yypgoto[] =\n{\n -136, -136, -8, -17, -136, -136, -133, -136, -136, 165,\n 166, -136, -136, -136, -136, -136, -136, -136, -135, 71,\n -136, -136, -136, -136, 17, -136, -136, -136, -136, -136,\n -136, -136, -64, -136, -136, -136, -136\n};\n\n /* YYDEFGOTO[NTERM-NUM]. */\nstatic const yytype_int8 yydefgoto[] =\n{\n -1, 7, 8, 9, 97, 98, 99, 10, 11, 12,\n 13, 62, 63, 108, 30, 14, 15, 31, 74, 16,\n 120, 36, 17, 18, 19, 20, 21, 22, 44, 65,\n 66, 39, 67, 68, 69, 70, 71\n};\n\n /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If\n positive, shift that token. If negative, reduce the rule whose\n number is the opposite. If YYTABLE_NINF, syntax error. */\nstatic const yytype_uint8 yytable[] =\n{\n 35, 26, 57, 113, 90, 43, 144, 45, 116, 1,\n 58, 147, 81, 149, 114, 86, 150, 27, 49, 56,\n 117, 45, 25, 73, 106, 40, 28, 26, 3, 4,\n 5, 6, 33, 115, 118, 26, 41, 45, 1, 3,\n 4, 5, 6, 87, 91, 59, 59, 76, 26, 46,\n 59, 47, 3, 4, 5, 6, 64, 96, 52, 75,\n 23, 53, 42, 24, 78, 26, 3, 4, 5, 6,\n 79, 80, 110, 77, 54, 3, 4, 5, 6, 3,\n 4, 5, 6, 48, 119, 32, 49, 126, 26, 82,\n 38, 3, 4, 5, 6, 72, 83, 84, 88, 93,\n 34, 50, 26, 89, 51, 3, 4, 5, 6, 23,\n 92, 26, 49, 101, 55, 103, 3, 4, 5, 6,\n 3, 4, 5, 6, 73, 85, 100, 96, 109, 102,\n 104, 73, 96, 3, 4, 5, 6, 3, 4, 5,\n 6, 125, 1, 2, 3, 4, 5, 6, 3, 4,\n 5, 6, 94, 95, 29, 3, 4, 5, 6, 37,\n 3, 4, 5, 6, 105, 107, 111, 112, 121, 122,\n 123, 128, 130, 124, 129, 127, 131, 133, 134, 141,\n 132, 0, 0, 138, 145, 136, 142, 0, 0, 135,\n 140, 0, 0, 0, 139, 137, 0, 143, 0, 0,\n 0, 146, 0, 148, 60, 61\n};\n\nstatic const yytype_int16 yycheck[] =\n{\n 17, 9, 3, 5, 8, 22, 141, 19, 5, 10,\n 11, 144, 24, 148, 16, 18, 149, 8, 21, 36,\n 17, 19, 0, 40, 22, 9, 6, 35, 12, 13,\n 14, 15, 15, 97, 98, 43, 20, 19, 10, 12,\n 13, 14, 15, 46, 48, 47, 47, 20, 56, 43,\n 47, 19, 12, 13, 14, 15, 39, 74, 20, 20,\n 18, 21, 46, 21, 19, 73, 12, 13, 14, 15,\n 44, 19, 89, 46, 34, 12, 13, 14, 15, 12,\n 13, 14, 15, 18, 101, 14, 21, 33, 96, 20,\n 19, 12, 13, 14, 15, 32, 39, 20, 4, 32,\n 21, 30, 110, 8, 33, 12, 13, 14, 15, 18,\n 7, 119, 21, 45, 21, 28, 12, 13, 14, 15,\n 12, 13, 14, 15, 141, 21, 20, 144, 20, 20,\n 40, 148, 149, 12, 13, 14, 15, 12, 13, 14,\n 15, 20, 10, 11, 12, 13, 14, 15, 12, 13,\n 14, 15, 16, 17, 11, 12, 13, 14, 15, 11,\n 12, 13, 14, 15, 20, 27, 49, 49, 23, 38,\n 23, 41, 20, 27, 24, 26, 34, 37, 25, 42,\n 29, -1, -1, 26, 22, 30, 25, -1, -1, 35,\n 31, -1, -1, -1, 36, 39, -1, 37, -1, -1,\n -1, 38, -1, 39, 39, 39\n};\n\n /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing\n symbol of state STATE-NUM. */\nstatic const yytype_uint8 yystos[] =\n{\n 0, 10, 11, 12, 13, 14, 15, 51, 52, 53,\n 57, 58, 59, 60, 65, 66, 69, 72, 73, 74,\n 75, 76, 77, 18, 21, 0, 52, 8, 6, 11,\n 64, 67, 69, 74, 21, 53, 71, 11, 69, 81,\n 9, 20, 46, 53, 78, 19, 43, 19, 18, 21,\n 69, 69, 20, 21, 34, 21, 53, 3, 11, 47,\n 59, 60, 61, 62, 74, 79, 80, 82, 83, 84,\n 85, 86, 32, 53, 68, 20, 20, 46, 19, 44,\n 19, 24, 20, 39, 20, 21, 18, 46, 4, 8,\n 8, 48, 7, 32, 16, 17, 53, 54, 55, 56,\n 20, 45, 20, 28, 40, 20, 22, 27, 63, 20,\n 53, 49, 49, 5, 16, 82, 5, 17, 82, 53,\n 70, 23, 38, 23, 27, 20, 33, 26, 41, 24,\n 20, 34, 29, 37, 25, 35, 30, 39, 26, 36,\n 31, 42, 25, 37, 68, 22, 38, 56, 39, 68,\n 56\n};\n\n /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */\nstatic const yytype_uint8 yyr1[] =\n{\n 0, 50, 51, 51, 52, 52, 52, 52, 53, 53,\n 54, 54, 54, 55, 55, 55, 56, 56, 57, 58,\n 59, 60, 61, 62, 63, 64, 64, 65, 65, 65,\n 66, 66, 67, 68, 68, 68, 69, 69, 69, 70,\n 71, 72, 73, 73, 73, 73, 74, 74, 75, 75,\n 76, 76, 77, 77, 78, 79, 80, 80, 81, 81,\n 81, 81, 81, 81, 81, 82, 82, 83, 84, 85,\n 86\n};\n\n /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */\nstatic const yytype_uint8 yyr2[] =\n{\n 0, 2, 2, 3, 1, 1, 1, 1, 1, 2,\n 1, 2, 2, 1, 2, 2, 2, 2, 1, 4,\n 5, 2, 3, 9, 3, 1, 2, 1, 1, 2,\n 2, 1, 9, 1, 2, 2, 1, 1, 1, 10,\n 11, 6, 3, 4, 4, 5, 1, 3, 2, 3,\n 3, 4, 2, 2, 3, 2, 3, 4, 0, 2,\n 2, 2, 2, 2, 2, 1, 1, 1, 2, 3,\n 3\n};\n\n\n#define yyerrok (yyerrstatus = 0)\n#define yyclearin (yychar = YYEMPTY)\n#define YYEMPTY (-2)\n#define YYEOF 0\n\n#define YYACCEPT goto yyacceptlab\n#define YYABORT goto yyabortlab\n#define YYERROR goto yyerrorlab\n\n\n#define YYRECOVERING() (!!yyerrstatus)\n\n#define YYBACKUP(Token, Value) \\\ndo \\\n if (yychar == YYEMPTY) \\\n { \\\n yychar = (Token); \\\n yylval = (Value); \\\n YYPOPSTACK (yylen); \\\n yystate = *yyssp; \\\n goto yybackup; \\\n } \\\n else \\\n { \\\n yyerror (YY_(\"syntax error: cannot back up\")); \\\n YYERROR; \\\n } \\\nwhile (0)\n\n/* Error token number */\n#define YYTERROR 1\n#define YYERRCODE 256\n\n\n\n/* Enable debugging if requested. */\n#if XMLDEBUG\n\n# ifndef YYFPRINTF\n# include /* INFRINGES ON USER NAME SPACE */\n# define YYFPRINTF fprintf\n# endif\n\n# define YYDPRINTF(Args) \\\ndo { \\\n if (yydebug) \\\n YYFPRINTF Args; \\\n} while (0)\n\n/* This macro is provided for backward compatibility. */\n#ifndef YY_LOCATION_PRINT\n# define YY_LOCATION_PRINT(File, Loc) ((void) 0)\n#endif\n\n\n# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \\\ndo { \\\n if (yydebug) \\\n { \\\n YYFPRINTF (stderr, \"%s \", Title); \\\n yy_symbol_print (stderr, \\\n Type, Value); \\\n YYFPRINTF (stderr, \"\\n\"); \\\n } \\\n} while (0)\n\n\n/*----------------------------------------.\n| Print this symbol's value on YYOUTPUT. |\n`----------------------------------------*/\n\nstatic void\nyy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)\n{\n FILE *yyo = yyoutput;\n YYUSE (yyo);\n if (!yyvaluep)\n return;\n# ifdef YYPRINT\n if (yytype < YYNTOKENS)\n YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);\n# endif\n YYUSE (yytype);\n}\n\n\n/*--------------------------------.\n| Print this symbol on YYOUTPUT. |\n`--------------------------------*/\n\nstatic void\nyy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)\n{\n YYFPRINTF (yyoutput, \"%s %s (\",\n yytype < YYNTOKENS ? \"token\" : \"nterm\", yytname[yytype]);\n\n yy_symbol_value_print (yyoutput, yytype, yyvaluep);\n YYFPRINTF (yyoutput, \")\");\n}\n\n/*------------------------------------------------------------------.\n| yy_stack_print -- Print the state stack from its BOTTOM up to its |\n| TOP (included). |\n`------------------------------------------------------------------*/\n\nstatic void\nyy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)\n{\n YYFPRINTF (stderr, \"Stack now\");\n for (; yybottom <= yytop; yybottom++)\n {\n int yybot = *yybottom;\n YYFPRINTF (stderr, \" %d\", yybot);\n }\n YYFPRINTF (stderr, \"\\n\");\n}\n\n# define YY_STACK_PRINT(Bottom, Top) \\\ndo { \\\n if (yydebug) \\\n yy_stack_print ((Bottom), (Top)); \\\n} while (0)\n\n\n/*------------------------------------------------.\n| Report that the YYRULE is going to be reduced. |\n`------------------------------------------------*/\n\nstatic void\nyy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)\n{\n unsigned long int yylno = yyrline[yyrule];\n int yynrhs = yyr2[yyrule];\n int yyi;\n YYFPRINTF (stderr, \"Reducing stack by rule %d (line %lu):\\n\",\n yyrule - 1, yylno);\n /* The symbols being reduced. */\n for (yyi = 0; yyi < yynrhs; yyi++)\n {\n YYFPRINTF (stderr, \" $%d = \", yyi + 1);\n yy_symbol_print (stderr,\n yystos[yyssp[yyi + 1 - yynrhs]],\n &(yyvsp[(yyi + 1) - (yynrhs)])\n );\n YYFPRINTF (stderr, \"\\n\");\n }\n}\n\n# define YY_REDUCE_PRINT(Rule) \\\ndo { \\\n if (yydebug) \\\n yy_reduce_print (yyssp, yyvsp, Rule); \\\n} while (0)\n\n/* Nonzero means print parse trace. It is left uninitialized so that\n multiple parsers can coexist. */\nint yydebug;\n#else /* !XMLDEBUG */\n# define YYDPRINTF(Args)\n# define YY_SYMBOL_PRINT(Title, Type, Value, Location)\n# define YY_STACK_PRINT(Bottom, Top)\n# define YY_REDUCE_PRINT(Rule)\n#endif /* !XMLDEBUG */\n\n\n/* YYINITDEPTH -- initial size of the parser's stacks. */\n#ifndef YYINITDEPTH\n# define YYINITDEPTH 200\n#endif\n\n/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only\n if the built-in stack extension method is used).\n\n Do not make this value too large; the results are undefined if\n YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)\n evaluated with infinite-precision integer arithmetic. */\n\n#ifndef YYMAXDEPTH\n# define YYMAXDEPTH 10000\n#endif\n\n\n#if YYERROR_VERBOSE\n\n# ifndef yystrlen\n# if defined __GLIBC__ && defined _STRING_H\n# define yystrlen strlen\n# else\n/* Return the length of YYSTR. */\nstatic YYSIZE_T\nyystrlen (const char *yystr)\n{\n YYSIZE_T yylen;\n for (yylen = 0; yystr[yylen]; yylen++)\n continue;\n return yylen;\n}\n# endif\n# endif\n\n# ifndef yystpcpy\n# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE\n# define yystpcpy stpcpy\n# else\n/* Copy YYSRC to YYDEST, returning the address of the terminating '\\0' in\n YYDEST. */\nstatic char *\nyystpcpy (char *yydest, const char *yysrc)\n{\n char *yyd = yydest;\n const char *yys = yysrc;\n\n while ((*yyd++ = *yys++) != '\\0')\n continue;\n\n return yyd - 1;\n}\n# endif\n# endif\n\n# ifndef yytnamerr\n/* Copy to YYRES the contents of YYSTR after stripping away unnecessary\n quotes and backslashes, so that it's suitable for yyerror. The\n heuristic is that double-quoting is unnecessary unless the string\n contains an apostrophe, a comma, or backslash (other than\n backslash-backslash). YYSTR is taken from yytname. If YYRES is\n null, do not copy; instead, return the length of what the result\n would have been. */\nstatic YYSIZE_T\nyytnamerr (char *yyres, const char *yystr)\n{\n if (*yystr == '\"')\n {\n YYSIZE_T yyn = 0;\n char const *yyp = yystr;\n\n for (;;)\n switch (*++yyp)\n {\n case '\\'':\n case ',':\n goto do_not_strip_quotes;\n\n case '\\\\':\n if (*++yyp != '\\\\')\n goto do_not_strip_quotes;\n /* Fall through. */\n default:\n if (yyres)\n yyres[yyn] = *yyp;\n yyn++;\n break;\n\n case '\"':\n if (yyres)\n yyres[yyn] = '\\0';\n return yyn;\n }\n do_not_strip_quotes: ;\n }\n\n if (! yyres)\n return yystrlen (yystr);\n\n return yystpcpy (yyres, yystr) - yyres;\n}\n# endif\n\n/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message\n about the unexpected token YYTOKEN for the state stack whose top is\n YYSSP.\n\n Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is\n not large enough to hold the message. In that case, also set\n *YYMSG_ALLOC to the required number of bytes. Return 2 if the\n required number of bytes is too large to store. */\nstatic int\nyysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,\n yytype_int16 *yyssp, int yytoken)\n{\n YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);\n YYSIZE_T yysize = yysize0;\n enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };\n /* Internationalized format string. */\n const char *yyformat = YY_NULLPTR;\n /* Arguments of yyformat. */\n char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];\n /* Number of reported tokens (one for the \"unexpected\", one per\n \"expected\"). */\n int yycount = 0;\n\n /* There are many possibilities here to consider:\n - If this state is a consistent state with a default action, then\n the only way this function was invoked is if the default action\n is an error action. In that case, don't check for expected\n tokens because there are none.\n - The only way there can be no lookahead present (in yychar) is if\n this state is a consistent state with a default action. Thus,\n detecting the absence of a lookahead is sufficient to determine\n that there is no unexpected or expected token to report. In that\n case, just report a simple \"syntax error\".\n - Don't assume there isn't a lookahead just because this state is a\n consistent state with a default action. There might have been a\n previous inconsistent state, consistent state with a non-default\n action, or user semantic action that manipulated yychar.\n - Of course, the expected token list depends on states to have\n correct lookahead information, and it depends on the parser not\n to perform extra reductions after fetching a lookahead from the\n scanner and before detecting a syntax error. Thus, state merging\n (from LALR or IELR) and default reductions corrupt the expected\n token list. However, the list is correct for canonical LR with\n one exception: it will still contain any token that will not be\n accepted due to an error action in a later state.\n */\n if (yytoken != YYEMPTY)\n {\n int yyn = yypact[*yyssp];\n yyarg[yycount++] = yytname[yytoken];\n if (!yypact_value_is_default (yyn))\n {\n /* Start YYX at -YYN if negative to avoid negative indexes in\n YYCHECK. In other words, skip the first -YYN actions for\n this state because they are default actions. */\n int yyxbegin = yyn < 0 ? -yyn : 0;\n /* Stay within bounds of both yycheck and yytname. */\n int yychecklim = YYLAST - yyn + 1;\n int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;\n int yyx;\n\n for (yyx = yyxbegin; yyx < yyxend; ++yyx)\n if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR\n && !yytable_value_is_error (yytable[yyx + yyn]))\n {\n if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)\n {\n yycount = 1;\n yysize = yysize0;\n break;\n }\n yyarg[yycount++] = yytname[yyx];\n {\n YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);\n if (! (yysize <= yysize1\n && yysize1 <= YYSTACK_ALLOC_MAXIMUM))\n return 2;\n yysize = yysize1;\n }\n }\n }\n }\n\n switch (yycount)\n {\n# define YYCASE_(N, S) \\\n case N: \\\n yyformat = S; \\\n break\n YYCASE_(0, YY_(\"syntax error\"));\n YYCASE_(1, YY_(\"syntax error, unexpected %s\"));\n YYCASE_(2, YY_(\"syntax error, unexpected %s, expecting %s\"));\n YYCASE_(3, YY_(\"syntax error, unexpected %s, expecting %s or %s\"));\n YYCASE_(4, YY_(\"syntax error, unexpected %s, expecting %s or %s or %s\"));\n YYCASE_(5, YY_(\"syntax error, unexpected %s, expecting %s or %s or %s or %s\"));\n# undef YYCASE_\n }\n\n {\n YYSIZE_T yysize1 = yysize + yystrlen (yyformat);\n if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))\n return 2;\n yysize = yysize1;\n }\n\n if (*yymsg_alloc < yysize)\n {\n *yymsg_alloc = 2 * yysize;\n if (! (yysize <= *yymsg_alloc\n && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))\n *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;\n return 1;\n }\n\n /* Avoid sprintf, as that infringes on the user's name space.\n Don't have undefined behavior even if the translation\n produced a string with the wrong number of \"%s\"s. */\n {\n char *yyp = *yymsg;\n int yyi = 0;\n while ((*yyp = *yyformat) != '\\0')\n if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)\n {\n yyp += yytnamerr (yyp, yyarg[yyi++]);\n yyformat += 2;\n }\n else\n {\n yyp++;\n yyformat++;\n }\n }\n return 0;\n}\n#endif /* YYERROR_VERBOSE */\n\n/*-----------------------------------------------.\n| Release the memory associated to this symbol. |\n`-----------------------------------------------*/\n\nstatic void\nyydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)\n{\n YYUSE (yyvaluep);\n if (!yymsg)\n yymsg = \"Deleting\";\n YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);\n\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n switch (yytype)\n {\n case 3: /* CHARDATA */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 4: /* CDATA */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 5: /* ATTVALUE */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 6: /* COMMENT */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 7: /* CHARREF */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 8: /* NAME */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 9: /* SNAME */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 10: /* ELEMBRACE */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 11: /* COMMBRACE */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 54: /* attsinglemid */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 55: /* attdoublemid */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 56: /* AttValue */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 61: /* CDSect */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 75: /* STag */\n\n { delete ((*yyvaluep).attr); }\n\n break;\n\n case 76: /* EmptyElemTag */\n\n { delete ((*yyvaluep).attr); }\n\n break;\n\n case 77: /* stagstart */\n\n { delete ((*yyvaluep).attr); }\n\n break;\n\n case 78: /* SAttribute */\n\n { delete ((*yyvaluep).pair); }\n\n break;\n\n case 80: /* ETag */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 82: /* Reference */\n\n { }\n\n break;\n\n case 85: /* CharRef */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n case 86: /* EntityRef */\n\n { delete ((*yyvaluep).str); }\n\n break;\n\n\n default:\n break;\n }\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n\n\n/* The lookahead symbol. */\nint yychar;\n\n/* The semantic value of the lookahead symbol. */\nYYSTYPE yylval;\n/* Number of syntax errors so far. */\nint yynerrs;\n\n\n/*----------.\n| yyparse. |\n`----------*/\n\nint\nyyparse (void)\n{\n int yystate;\n /* Number of tokens to shift before error messages enabled. */\n int yyerrstatus;\n\n /* The stacks and their tools:\n 'yyss': related to states.\n 'yyvs': related to semantic values.\n\n Refer to the stacks through separate pointers, to allow yyoverflow\n to reallocate them elsewhere. */\n\n /* The state stack. */\n yytype_int16 yyssa[YYINITDEPTH];\n yytype_int16 *yyss;\n yytype_int16 *yyssp;\n\n /* The semantic value stack. */\n YYSTYPE yyvsa[YYINITDEPTH];\n YYSTYPE *yyvs;\n YYSTYPE *yyvsp;\n\n YYSIZE_T yystacksize;\n\n int yyn;\n int yyresult;\n /* Lookahead token as an internal (translated) token number. */\n int yytoken = 0;\n /* The variables used to return semantic value and location from the\n action routines. */\n YYSTYPE yyval;\n\n#if YYERROR_VERBOSE\n /* Buffer for error messages, and its allocated size. */\n char yymsgbuf[128];\n char *yymsg = yymsgbuf;\n YYSIZE_T yymsg_alloc = sizeof yymsgbuf;\n#endif\n\n#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))\n\n /* The number of symbols on the RHS of the reduced rule.\n Keep to zero when no symbol should be popped. */\n int yylen = 0;\n\n yyssp = yyss = yyssa;\n yyvsp = yyvs = yyvsa;\n yystacksize = YYINITDEPTH;\n\n YYDPRINTF ((stderr, \"Starting parse\\n\"));\n\n yystate = 0;\n yyerrstatus = 0;\n yynerrs = 0;\n yychar = YYEMPTY; /* Cause a token to be read. */\n goto yysetstate;\n\n/*------------------------------------------------------------.\n| yynewstate -- Push a new state, which is found in yystate. |\n`------------------------------------------------------------*/\n yynewstate:\n /* In all cases, when you get here, the value and location stacks\n have just been pushed. So pushing a state here evens the stacks. */\n yyssp++;\n\n yysetstate:\n *yyssp = yystate;\n\n if (yyss + yystacksize - 1 <= yyssp)\n {\n /* Get the current used size of the three stacks, in elements. */\n YYSIZE_T yysize = yyssp - yyss + 1;\n\n#ifdef yyoverflow\n {\n /* Give user a chance to reallocate the stack. Use copies of\n these so that the &'s don't force the real ones into\n memory. */\n YYSTYPE *yyvs1 = yyvs;\n yytype_int16 *yyss1 = yyss;\n\n /* Each stack pointer address is followed by the size of the\n data in use in that stack, in bytes. This used to be a\n conditional around just the two extra args, but that might\n be undefined if yyoverflow is a macro. */\n yyoverflow (YY_(\"memory exhausted\"),\n &yyss1, yysize * sizeof (*yyssp),\n &yyvs1, yysize * sizeof (*yyvsp),\n &yystacksize);\n\n yyss = yyss1;\n yyvs = yyvs1;\n }\n#else /* no yyoverflow */\n# ifndef YYSTACK_RELOCATE\n goto yyexhaustedlab;\n# else\n /* Extend the stack our own way. */\n if (YYMAXDEPTH <= yystacksize)\n goto yyexhaustedlab;\n yystacksize *= 2;\n if (YYMAXDEPTH < yystacksize)\n yystacksize = YYMAXDEPTH;\n\n {\n yytype_int16 *yyss1 = yyss;\n union yyalloc *yyptr =\n (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));\n if (! yyptr)\n goto yyexhaustedlab;\n YYSTACK_RELOCATE (yyss_alloc, yyss);\n YYSTACK_RELOCATE (yyvs_alloc, yyvs);\n# undef YYSTACK_RELOCATE\n if (yyss1 != yyssa)\n YYSTACK_FREE (yyss1);\n }\n# endif\n#endif /* no yyoverflow */\n\n yyssp = yyss + yysize - 1;\n yyvsp = yyvs + yysize - 1;\n\n YYDPRINTF ((stderr, \"Stack size increased to %lu\\n\",\n (unsigned long int) yystacksize));\n\n if (yyss + yystacksize - 1 <= yyssp)\n YYABORT;\n }\n\n YYDPRINTF ((stderr, \"Entering state %d\\n\", yystate));\n\n if (yystate == YYFINAL)\n YYACCEPT;\n\n goto yybackup;\n\n/*-----------.\n| yybackup. |\n`-----------*/\nyybackup:\n\n /* Do appropriate processing given the current state. Read a\n lookahead token if we need one and don't already have one. */\n\n /* First try to decide what to do without reference to lookahead token. */\n yyn = yypact[yystate];\n if (yypact_value_is_default (yyn))\n goto yydefault;\n\n /* Not known => get a lookahead token if don't already have one. */\n\n /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */\n if (yychar == YYEMPTY)\n {\n YYDPRINTF ((stderr, \"Reading a token: \"));\n yychar = yylex ();\n }\n\n if (yychar <= YYEOF)\n {\n yychar = yytoken = YYEOF;\n YYDPRINTF ((stderr, \"Now at end of input.\\n\"));\n }\n else\n {\n yytoken = YYTRANSLATE (yychar);\n YY_SYMBOL_PRINT (\"Next token is\", yytoken, &yylval, &yylloc);\n }\n\n /* If the proper action on seeing token YYTOKEN is to reduce or to\n detect an error, take that action. */\n yyn += yytoken;\n if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)\n goto yydefault;\n yyn = yytable[yyn];\n if (yyn <= 0)\n {\n if (yytable_value_is_error (yyn))\n goto yyerrlab;\n yyn = -yyn;\n goto yyreduce;\n }\n\n /* Count tokens shifted since error; after three, turn off error\n status. */\n if (yyerrstatus)\n yyerrstatus--;\n\n /* Shift the lookahead token. */\n YY_SYMBOL_PRINT (\"Shifting\", yytoken, &yylval, &yylloc);\n\n /* Discard the shifted token. */\n yychar = YYEMPTY;\n\n yystate = yyn;\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n *++yyvsp = yylval;\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n goto yynewstate;\n\n\n/*-----------------------------------------------------------.\n| yydefault -- do the default action for the current state. |\n`-----------------------------------------------------------*/\nyydefault:\n yyn = yydefact[yystate];\n if (yyn == 0)\n goto yyerrlab;\n goto yyreduce;\n\n\n/*-----------------------------.\n| yyreduce -- Do a reduction. |\n`-----------------------------*/\nyyreduce:\n /* yyn is the number of a rule to reduce with. */\n yylen = yyr2[yyn];\n\n /* If YYLEN is nonzero, implement the default value of the action:\n '$$ = $1'.\n\n Otherwise, the following line sets YYVAL to garbage.\n This behavior is undocumented and Bison\n users should not rely upon it. Assigning to YYVAL\n unconditionally makes the parser a bit smaller, and it avoids a\n GCC warning that YYVAL may be used uninitialized. */\n yyval = yyvsp[1-yylen];\n\n\n YY_REDUCE_PRINT (yyn);\n switch (yyn)\n {\n case 10:\n\n { (yyval.str) = new string; global_scan->setmode(XmlScan::AttValueSingleMode); }\n\n break;\n\n case 11:\n\n { (yyval.str) = (yyvsp[-1].str); *(yyval.str) += *(yyvsp[0].str); delete (yyvsp[0].str); global_scan->setmode(XmlScan::AttValueSingleMode); }\n\n break;\n\n case 12:\n\n { (yyval.str) = (yyvsp[-1].str); *(yyval.str) += (yyvsp[0].i); global_scan->setmode(XmlScan::AttValueSingleMode); }\n\n break;\n\n case 13:\n\n { (yyval.str) = new string; global_scan->setmode(XmlScan::AttValueDoubleMode); }\n\n break;\n\n case 14:\n\n { (yyval.str) = (yyvsp[-1].str); *(yyval.str) += *(yyvsp[0].str); delete (yyvsp[0].str); global_scan->setmode(XmlScan::AttValueDoubleMode); }\n\n break;\n\n case 15:\n\n { (yyval.str) = (yyvsp[-1].str); *(yyval.str) += (yyvsp[0].i); global_scan->setmode(XmlScan::AttValueDoubleMode); }\n\n break;\n\n case 16:\n\n { (yyval.str) = (yyvsp[-1].str); }\n\n break;\n\n case 17:\n\n { (yyval.str) = (yyvsp[-1].str); }\n\n break;\n\n case 18:\n\n { global_scan->setmode(XmlScan::NameMode); delete (yyvsp[0].str); }\n\n break;\n\n case 19:\n\n { global_scan->setmode(XmlScan::CommentMode); delete (yyvsp[-3].str); }\n\n break;\n\n case 20:\n\n { delete (yyvsp[-3].str); }\n\n break;\n\n case 21:\n\n { delete (yyvsp[-1].str); yyerror(\"Processing instructions are not supported\"); YYERROR; }\n\n break;\n\n case 22:\n\n { (yyval.str) = (yyvsp[-1].str); }\n\n break;\n\n case 23:\n\n { global_scan->setmode(XmlScan::CDataMode); delete (yyvsp[-8].str); }\n\n break;\n\n case 32:\n\n { delete (yyvsp[-8].str); yyerror(\"DTD's not supported\"); YYERROR; }\n\n break;\n\n case 39:\n\n { handler->setVersion(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n\n break;\n\n case 40:\n\n { handler->setEncoding(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n\n break;\n\n case 46:\n\n { handler->endElement((yyvsp[0].attr)->getelemURI(),(yyvsp[0].attr)->getelemName(),(yyvsp[0].attr)->getelemName()); delete (yyvsp[0].attr); }\n\n break;\n\n case 47:\n\n { handler->endElement((yyvsp[-2].attr)->getelemURI(),(yyvsp[-2].attr)->getelemName(),(yyvsp[-2].attr)->getelemName()); delete (yyvsp[-2].attr); delete (yyvsp[0].str); }\n\n break;\n\n case 48:\n\n { handler->startElement((yyvsp[-1].attr)->getelemURI(),(yyvsp[-1].attr)->getelemName(),(yyvsp[-1].attr)->getelemName(),*(yyvsp[-1].attr)); (yyval.attr) = (yyvsp[-1].attr); }\n\n break;\n\n case 49:\n\n { handler->startElement((yyvsp[-2].attr)->getelemURI(),(yyvsp[-2].attr)->getelemName(),(yyvsp[-2].attr)->getelemName(),*(yyvsp[-2].attr)); (yyval.attr) = (yyvsp[-2].attr); }\n\n break;\n\n case 50:\n\n { handler->startElement((yyvsp[-2].attr)->getelemURI(),(yyvsp[-2].attr)->getelemName(),(yyvsp[-2].attr)->getelemName(),*(yyvsp[-2].attr)); (yyval.attr) = (yyvsp[-2].attr); }\n\n break;\n\n case 51:\n\n { handler->startElement((yyvsp[-3].attr)->getelemURI(),(yyvsp[-3].attr)->getelemName(),(yyvsp[-3].attr)->getelemName(),*(yyvsp[-3].attr)); (yyval.attr) = (yyvsp[-3].attr); }\n\n break;\n\n case 52:\n\n { (yyval.attr) = new Attributes((yyvsp[0].str)); global_scan->setmode(XmlScan::SNameMode); }\n\n break;\n\n case 53:\n\n { (yyval.attr) = (yyvsp[-1].attr); (yyval.attr)->add_attribute( (yyvsp[0].pair)->name, (yyvsp[0].pair)->value); delete (yyvsp[0].pair); global_scan->setmode(XmlScan::SNameMode); }\n\n break;\n\n case 54:\n\n { (yyval.pair) = new NameValue; (yyval.pair)->name = (yyvsp[-2].str); (yyval.pair)->value = (yyvsp[0].str); }\n\n break;\n\n case 55:\n\n { global_scan->setmode(XmlScan::NameMode); delete (yyvsp[-1].str); }\n\n break;\n\n case 56:\n\n { (yyval.str) = (yyvsp[-1].str); }\n\n break;\n\n case 57:\n\n { (yyval.str) = (yyvsp[-2].str); }\n\n break;\n\n case 58:\n\n { global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 59:\n\n { print_content( *(yyvsp[0].str) ); delete (yyvsp[0].str); global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 60:\n\n { global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 61:\n\n { string *tmp=new string(); *tmp += (yyvsp[0].i); print_content(*tmp); delete tmp; global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 62:\n\n { print_content( *(yyvsp[0].str) ); delete (yyvsp[0].str); global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 63:\n\n { global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 64:\n\n { global_scan->setmode(XmlScan::CharDataMode); }\n\n break;\n\n case 65:\n\n { (yyval.i) = convertEntityRef(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n\n break;\n\n case 66:\n\n { (yyval.i) = convertCharRef(*(yyvsp[0].str)); delete (yyvsp[0].str); }\n\n break;\n\n case 67:\n\n { global_scan->setmode(XmlScan::NameMode); }\n\n break;\n\n case 68:\n\n { global_scan->setmode(XmlScan::CharRefMode); }\n\n break;\n\n case 69:\n\n { (yyval.str) = (yyvsp[-1].str); }\n\n break;\n\n case 70:\n\n { (yyval.str) = (yyvsp[-1].str); }\n\n break;\n\n\n\n default: break;\n }\n /* User semantic actions sometimes alter yychar, and that requires\n that yytoken be updated with the new translation. We take the\n approach of translating immediately before every use of yytoken.\n One alternative is translating here after every semantic action,\n but that translation would be missed if the semantic action invokes\n YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or\n if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an\n incorrect destructor might then be invoked immediately. In the\n case of YYERROR or YYBACKUP, subsequent parser actions might lead\n to an incorrect destructor call or verbose syntax error message\n before the lookahead is translated. */\n YY_SYMBOL_PRINT (\"-> $$ =\", yyr1[yyn], &yyval, &yyloc);\n\n YYPOPSTACK (yylen);\n yylen = 0;\n YY_STACK_PRINT (yyss, yyssp);\n\n *++yyvsp = yyval;\n\n /* Now 'shift' the result of the reduction. Determine what state\n that goes to, based on the state we popped back to and the rule\n number reduced by. */\n\n yyn = yyr1[yyn];\n\n yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;\n if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)\n yystate = yytable[yystate];\n else\n yystate = yydefgoto[yyn - YYNTOKENS];\n\n goto yynewstate;\n\n\n/*--------------------------------------.\n| yyerrlab -- here on detecting error. |\n`--------------------------------------*/\nyyerrlab:\n /* Make sure we have latest lookahead translation. See comments at\n user semantic actions for why this is necessary. */\n yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);\n\n /* If not already recovering from an error, report this error. */\n if (!yyerrstatus)\n {\n ++yynerrs;\n#if ! YYERROR_VERBOSE\n yyerror (YY_(\"syntax error\"));\n#else\n# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \\\n yyssp, yytoken)\n {\n char const *yymsgp = YY_(\"syntax error\");\n int yysyntax_error_status;\n yysyntax_error_status = YYSYNTAX_ERROR;\n if (yysyntax_error_status == 0)\n yymsgp = yymsg;\n else if (yysyntax_error_status == 1)\n {\n if (yymsg != yymsgbuf)\n YYSTACK_FREE (yymsg);\n yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);\n if (!yymsg)\n {\n yymsg = yymsgbuf;\n yymsg_alloc = sizeof yymsgbuf;\n yysyntax_error_status = 2;\n }\n else\n {\n yysyntax_error_status = YYSYNTAX_ERROR;\n yymsgp = yymsg;\n }\n }\n yyerror (yymsgp);\n if (yysyntax_error_status == 2)\n goto yyexhaustedlab;\n }\n# undef YYSYNTAX_ERROR\n#endif\n }\n\n\n\n if (yyerrstatus == 3)\n {\n /* If just tried and failed to reuse lookahead token after an\n error, discard it. */\n\n if (yychar <= YYEOF)\n {\n /* Return failure if at end of input. */\n if (yychar == YYEOF)\n YYABORT;\n }\n else\n {\n yydestruct (\"Error: discarding\",\n yytoken, &yylval);\n yychar = YYEMPTY;\n }\n }\n\n /* Else will try to reuse lookahead token after shifting the error\n token. */\n goto yyerrlab1;\n\n\n/*---------------------------------------------------.\n| yyerrorlab -- error raised explicitly by YYERROR. |\n`---------------------------------------------------*/\nyyerrorlab:\n\n /* Pacify compilers like GCC when the user code never invokes\n YYERROR and the label yyerrorlab therefore never appears in user\n code. */\n if (/*CONSTCOND*/ 0)\n goto yyerrorlab;\n\n /* Do not reclaim the symbols of the rule whose action triggered\n this YYERROR. */\n YYPOPSTACK (yylen);\n yylen = 0;\n YY_STACK_PRINT (yyss, yyssp);\n yystate = *yyssp;\n goto yyerrlab1;\n\n\n/*-------------------------------------------------------------.\n| yyerrlab1 -- common code for both syntax error and YYERROR. |\n`-------------------------------------------------------------*/\nyyerrlab1:\n yyerrstatus = 3; /* Each real token shifted decrements this. */\n\n for (;;)\n {\n yyn = yypact[yystate];\n if (!yypact_value_is_default (yyn))\n {\n yyn += YYTERROR;\n if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)\n {\n yyn = yytable[yyn];\n if (0 < yyn)\n break;\n }\n }\n\n /* Pop the current state because it cannot handle the error token. */\n if (yyssp == yyss)\n YYABORT;\n\n\n yydestruct (\"Error: popping\",\n yystos[yystate], yyvsp);\n YYPOPSTACK (1);\n yystate = *yyssp;\n YY_STACK_PRINT (yyss, yyssp);\n }\n\n YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n *++yyvsp = yylval;\n YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n\n /* Shift the error token. */\n YY_SYMBOL_PRINT (\"Shifting\", yystos[yyn], yyvsp, yylsp);\n\n yystate = yyn;\n goto yynewstate;\n\n\n/*-------------------------------------.\n| yyacceptlab -- YYACCEPT comes here. |\n`-------------------------------------*/\nyyacceptlab:\n yyresult = 0;\n goto yyreturn;\n\n/*-----------------------------------.\n| yyabortlab -- YYABORT comes here. |\n`-----------------------------------*/\nyyabortlab:\n yyresult = 1;\n goto yyreturn;\n\n#if !defined yyoverflow || YYERROR_VERBOSE\n/*-------------------------------------------------.\n| yyexhaustedlab -- memory exhaustion comes here. |\n`-------------------------------------------------*/\nyyexhaustedlab:\n yyerror (YY_(\"memory exhausted\"));\n yyresult = 2;\n /* Fall through. */\n#endif\n\nyyreturn:\n if (yychar != YYEMPTY)\n {\n /* Make sure we have latest lookahead translation. See comments at\n user semantic actions for why this is necessary. */\n yytoken = YYTRANSLATE (yychar);\n yydestruct (\"Cleanup: discarding lookahead\",\n yytoken, &yylval);\n }\n /* Do not reclaim the symbols of the rule whose action triggered\n this YYABORT or YYACCEPT. */\n YYPOPSTACK (yylen);\n YY_STACK_PRINT (yyss, yyssp);\n while (yyssp != yyss)\n {\n yydestruct (\"Cleanup: popping\",\n yystos[*yyssp], yyvsp);\n YYPOPSTACK (1);\n }\n#ifndef yyoverflow\n if (yyss != yyssa)\n YYSTACK_FREE (yyss);\n#endif\n#if YYERROR_VERBOSE\n if (yymsg != yymsgbuf)\n YYSTACK_FREE (yymsg);\n#endif\n return yyresult;\n}\n\n\n\nXmlScan::XmlScan(istream &t) : s(t)\n\n{\n curmode = SingleMode;\n lvalue = (string *)0;\n pos = 0;\n endofstream = false;\n getxmlchar(); getxmlchar(); getxmlchar(); getxmlchar(); // Fill lookahead buffer\n}\n\nXmlScan::~XmlScan(void)\n\n{\n clearlvalue();\n}\n\nvoid XmlScan::clearlvalue(void)\n\n{\n if (lvalue != (string *)0)\n delete lvalue;\n}\n\nint4 XmlScan::scanSingle(void)\n\n{\n int4 res = getxmlchar();\n if (res == '<') {\n if (isInitialNameChar(next(0))) return ElementBraceToken;\n return CommandBraceToken;\n }\n return res;\n}\n\nint4 XmlScan::scanCharData(void)\n\n{\n clearlvalue();\n lvalue = new string();\n \n while(next(0) != -1) {\t\t// look for '<' '&' or ']]>'\n if (next(0) == '<') break;\n if (next(0) == '&') break;\n if (next(0) == ']')\n if (next(1)== ']')\n\tif (next(2)=='>')\n\t break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size()==0)\n return scanSingle();\n return CharDataToken;\n}\n\nint4 XmlScan::scanCData(void)\n\n{\n clearlvalue();\n lvalue = new string();\n\n while(next(0) != -1) {\t// Look for \"]]>\" and non-Char\n if (next(0)==']')\n if (next(1)==']')\n\tif (next(2)=='>')\n\t break;\n if (!isChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n return CDataToken;\t\t// CData can be empty\n}\n\nint4 XmlScan::scanCharRef(void)\n\n{\n int4 v;\n clearlvalue();\n lvalue = new string();\n if (next(0) == 'x') {\n *lvalue += getxmlchar();\n while(next(0) != -1) {\n v = next(0);\n if (v < '0') break;\n if ((v>'9')&&(v<'A')) break;\n if ((v>'F')&&(v<'a')) break;\n if (v>'f') break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size()==1)\n return 'x';\t\t// Must be at least 1 hex digit\n }\n else {\n while(next(0) != -1) {\n v = next(0);\n if (v<'0') break;\n if (v>'9') break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size()==0)\n return scanSingle();\n }\n return CharRefToken;\n}\n\nint4 XmlScan::scanAttValue(int4 quote)\n\n{\n clearlvalue();\n lvalue = new string();\n while(next(0) != -1) {\n if (next(0) == quote) break;\n if (next(0) == '<') break;\n if (next(0) == '&') break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size() == 0)\n return scanSingle();\n return AttValueToken;\n}\n\nint4 XmlScan::scanComment(void)\n\n{\n clearlvalue();\n lvalue = new string();\n\n while(next(0) != -1) {\n if (next(0)=='-')\n if (next(1)=='-')\n\tbreak;\n if (!isChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n return CommentToken;\n}\n\nint4 XmlScan::scanName(void)\n\n{\n clearlvalue();\n lvalue = new string();\n\n if (!isInitialNameChar(next(0)))\n return scanSingle();\n *lvalue += getxmlchar();\n while(next(0) != -1) {\n if (!isNameChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n return NameToken;\n}\n\nint4 XmlScan::scanSName(void)\n\n{\n int4 whitecount = 0;\n while((next(0)==' ')||(next(0)=='\\n')||(next(0)=='\\r')||(next(0)=='\\t')) {\n whitecount += 1;\n getxmlchar();\n }\n clearlvalue();\n lvalue = new string();\n if (!isInitialNameChar(next(0))) {\t// First non-whitespace is not Name char\n if (whitecount > 0)\n return ' ';\n return scanSingle();\n }\n *lvalue += getxmlchar();\n while(next(0) != -1) {\n if (!isNameChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n if (whitecount>0)\n return SNameToken;\n return NameToken;\n}\n\nbool XmlScan::isInitialNameChar(int4 val)\n\n{\n if (isLetter(val)) return true;\n if ((val=='_')||(val==':')) return true;\n return false;\n}\n\nbool XmlScan::isNameChar(int4 val)\n\n{\n if (isLetter(val)) return true;\n if ((val>='0')&&(val<='9')) return true;\n if ((val=='.')||(val=='-')||(val=='_')||(val==':')) return true;\n return false;\n}\n\nbool XmlScan::isChar(int4 val)\n\n{\n if (val>=0x20) return true;\n if ((val == 0xd)||(val==0xa)||(val==0x9)) return true;\n return false;\n}\n\nint4 XmlScan::nexttoken(void)\n\n{\n mode mymode = curmode;\n curmode = SingleMode;\n switch(mymode) {\n case CharDataMode:\n return scanCharData();\n case CDataMode:\n return scanCData();\n case AttValueSingleMode:\n return scanAttValue('\\'');\n case AttValueDoubleMode:\n return scanAttValue('\"');\n case CommentMode:\n return scanComment();\n case CharRefMode:\n return scanCharRef();\n case NameMode:\n return scanName();\n case SNameMode:\n return scanSName();\n case SingleMode:\n return scanSingle();\n }\n return -1;\n}\n\nvoid print_content(const string &str)\n\n{\n uint4 i;\n for(i=0;iignorableWhitespace(str.c_str(),0,str.size());\n else\n handler->characters(str.c_str(),0,str.size()); \n}\n\nint4 convertEntityRef(const string &ref)\n\n{\n if (ref == \"lt\") return '<';\n if (ref == \"amp\") return '&';\n if (ref == \"gt\") return '>';\n if (ref == \"quot\") return '\"';\n if (ref == \"apos\") return '\\'';\n return -1;\n}\n\nint4 convertCharRef(const string &ref)\n\n{\n uint4 i;\n int4 mult,val,cur;\n\n if (ref[0]=='x') {\n i = 1;\n mult = 16;\n }\n else {\n i = 0;\n mult = 10;\n }\n val = 0;\n for(;inexttoken();\n if (res>255)\n yylval.str = global_scan->lval();\n return res;\n}\n\nint xmlerror(const char *str)\n\n{\n handler->setError(str);\n return 0;\n}\n\nint4 xml_parse(istream &i,ContentHandler *hand,int4 dbg)\n\n{\n#if YYDEBUG\n yydebug = dbg;\n#endif\n std::lock_guard global_scan_lock(global_scan_mutex);\n std::lock_guard handler_lock(handler_mutex);\n global_scan = new XmlScan(i);\n handler = hand;\n handler->startDocument();\n int4 res = yyparse();\n if (res == 0)\n handler->endDocument();\n delete global_scan;\n return res;\n}\n\nvoid TreeHandler::startElement(const string &namespaceURI,const string &localName,\n\t\t\t const string &qualifiedName,const Attributes &atts)\n{\n Element *newel = new Element(cur);\n cur->addChild(newel);\n cur = newel;\n newel->setName(localName);\n for(int4 i=0;iaddAttribute(atts.getLocalName(i),atts.getValue(i));\n}\n\nvoid TreeHandler::endElement(const string &namespaceURI,const string &localName,\n\t\t\t const string &qualifiedName)\n{\n cur = cur->getParent();\n}\n\nvoid TreeHandler::characters(const char *text,int4 start,int4 length)\n\n{\n cur->addContent(text,start,length);\n}\n\nElement::~Element(void)\n\n{\n List::iterator iter;\n \n for(iter=children.begin();iter!=children.end();++iter)\n delete *iter;\n}\n\nconst string &Element::getAttributeValue(const string &nm) const\n\n{\n for(uint4 i=0;igetName()] = el;\n}\n\nconst Element *DocumentStorage::getTag(const string &nm) const\n\n{\n map::const_iterator iter;\n\n iter = tagmap.find(nm);\n if (iter != tagmap.end())\n return (*iter).second;\n return (const Element *)0;\n}\n\nDocument *xml_tree(istream &i)\n\n{\n Document *doc = new Document();\n TreeHandler handle(doc);\n if (0!=xml_parse(i,&handle)) {\n delete doc;\n throw DecoderError(handle.getError());\n }\n return doc;\n}\n\nvoid xml_escape(ostream &s,const char *str)\n\n{\n while(*str!='\\0') {\n if (*str < '?') {\n if (*str=='<') s << \"<\";\n else if (*str=='>') s << \">\";\n else if (*str=='&') s << \"&\";\n else if (*str=='\"') s << \""\";\n else if (*str=='\\'') s << \"'\";\n else s << *str;\n }\n else\n s << *str;\n str++;\n }\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/sleigh/xml.hh", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/// \\file xml.hh\n/// \\brief Lightweight (and incomplete) XML parser for marshaling data to and from the decompiler\n#ifndef __XML_HH__\n#define __XML_HH__\n\n#include \"types.h\"\n#include \n#include \n#include \n#include \n#include \n\nnamespace ghidra {\n\nusing std::string;\nusing std::vector;\nusing std::map;\nusing std::istream;\nusing std::ostream;\nusing std::ifstream;\nusing std::dec;\nusing std::hex;\n\n/// \\brief The \\e attributes for a single XML element\n///\n/// A container for name/value pairs (of strings) for the formal attributes, as collected during parsing.\n/// This object is used to initialize the Element object but is not part of the final, in memory, DOM model.\n/// This also holds other properties of the element that are unused in this implementation,\n/// including the \\e namespace URI.\nclass Attributes {\n static string bogus_uri;\t\t///< A placeholder for the namespace URI that should be attached to the element\n// static string prefix;\n string *elementname;\t\t\t///< The name of the XML element\n vector name;\t\t///< List of names for each formal XML attribute\n vector value;\t\t///< List of values for each formal XML attribute\npublic:\n Attributes(string *el) { elementname = el; }\t///< Construct from element name string\n ~Attributes(void) { \n for(uint4 i=0;i List;\t\t///< A list of XML elements\n\n/// \\brief An XML element. A node in the DOM tree.\n///\n/// This is the main node for the in-memory representation of the XML (DOM) tree.\nclass Element {\n string name;\t\t\t///< The (local) name of the element\n string content;\t\t///< Character content of the element\n vector attr;\t\t///< A list of attribute names for \\b this element\n vector value;\t\t///< a (corresponding) list of attribute values for \\b this element\nprotected:\n Element *parent;\t\t///< The parent Element (or null)\n List children;\t\t///< A list of child Element objects\npublic:\n Element(Element *par) { parent = par; }\t///< Constructor given a parent Element\n ~Element(void);\t\t\t\t///< Destructor\n void setName(const string &nm) { name = nm; }\t///< Set the local name of the element\n\n /// \\brief Append new character content to \\b this element\n ///\n /// \\param str is an array of character data\n /// \\param start is the index of the first character to append\n /// \\param length is the number of characters to append\n void addContent(const char *str,int4 start,int4 length) { \n // for(int4 i=0;i doclist;\t\t///< The list of documents held by this container\n map tagmap;\t///< The map from name to registered XML elements\npublic:\n ~DocumentStorage(void);\t\t///< Destructor\n\n /// \\brief Parse an XML document from the given stream\n ///\n /// Parsing starts immediately on the stream, attempting to make an in-memory DOM tree.\n /// An XmlException is thrown for any parsing error.\n /// \\param s is the given stream to parse\n /// \\return the in-memory DOM tree\n Document *parseDocument(istream &s);\n\n /// \\brief Open and parse an XML file\n ///\n /// The given filename is opened on the local filesystem and an attempt is made to parse\n /// its contents into an in-memory DOM tree. An XmlException is thrown for any parsing error.\n /// \\param filename is the name of the XML document file\n /// \\return the in-memory DOM tree\n Document *openDocument(const string &filename);\n\n /// \\brief Register the given XML Element object under its tag name\n ///\n /// Only one Element can be stored on \\b this object per tag name.\n /// \\param el is the given XML element\n void registerTag(const Element *el);\n\n /// \\brief Retrieve a registered XML Element by name\n ///\n /// \\param nm is the XML tag name\n /// \\return the matching registered Element or null\n const Element *getTag(const string &nm) const;\n};\n\n/// \\brief An exception thrown by the XML parser\n///\n/// This object holds the error message as passed to the SAX interface callback\n/// and is thrown as a formal exception.\nstruct DecoderError {\n string explain;\t\t///< Explanatory string\n DecoderError(const string &s) { explain = s; }\t///< Constructor\n const char *what() { return explain.c_str(); }\n};\n\n/// \\brief Start-up the XML parser given a stream and a handler\n///\n/// This runs the low-level XML parser.\n/// \\param i is the given stream to get character data from\n/// \\param hand is the ContentHandler that stores or processes the XML content events\n/// \\param dbg is non-zero if the parser should output debug information during its parse\n/// \\return 0 if there is no error during parsing or a (non-zero) error condition\nextern int4 xml_parse(istream &i,ContentHandler *hand,int4 dbg=0);\n\n/// \\brief Parse the given XML stream into an in-memory document\n///\n/// The stream is parsed using the standard ContentHandler for producing an in-memory\n/// DOM representation of the XML document.\n/// \\param i is the given stream\n/// \\return the in-memory XML document\nextern Document *xml_tree(istream &i);\n\n/// \\brief Send the given character array to a stream, escaping characters with special XML meaning\n///\n/// This makes the following character substitutions:\n/// - '<' => \"<\"\n/// - '>' => \">\"\n/// - '&' => \"&\"\n/// - '\"' => \""\"\n/// - '\\'' => \"'\"\n///\n/// \\param s is the stream to write to\n/// \\param str is the given character array to escape\nextern void xml_escape(ostream &s,const char *str);\n\n// Some helper functions for writing XML documents directly to a stream\n\n/// \\brief Output an XML attribute name/value pair to stream\n///\n/// \\param s is the output stream\n/// \\param attr is the name of the attribute\n/// \\param val is the attribute value\ninline void a_v(ostream &s,const string &attr,const string &val)\n\n{\n s << ' ' << attr << \"=\\\"\";\n xml_escape(s,val.c_str());\n s << \"\\\"\";\n}\n\n/// \\brief Output the given signed integer as an XML attribute value\n///\n/// \\param s is the output stream\n/// \\param attr is the name of the attribute\n/// \\param val is the given integer value\ninline void a_v_i(ostream &s,const string &attr,intb val)\n\n{\n s << ' ' << attr << \"=\\\"\" << dec << val << \"\\\"\";\n}\n\n/// \\brief Output the given unsigned integer as an XML attribute value\n///\n/// \\param s is the output stream\n/// \\param attr is the name of the attribute\n/// \\param val is the given unsigned integer value\ninline void a_v_u(ostream &s,const string &attr,uintb val)\n\n{\n s << ' ' << attr << \"=\\\"0x\" << hex << val << \"\\\"\";\n}\n\n/// \\brief Output the given boolean value as an XML attribute\n///\n/// \\param s is the output stream\n/// \\param attr is the name of the attribute\n/// \\param val is the given boolean value\ninline void a_v_b(ostream &s,const string &attr,bool val)\n\n{\n s << ' ' << attr << \"=\\\"\";\n if (val)\n s << \"true\";\n else\n s << \"false\";\n s << \"\\\"\";\n}\n\n/// \\brief Read an XML attribute value as a boolean\n///\n/// This method is intended to recognize the strings, \"true\", \"yes\", and \"1\"\n/// as a \\b true value. Anything else is returned as \\b false.\n/// \\param attr is the given XML attribute value (as a string)\n/// \\return either \\b true or \\b false\ninline bool xml_readbool(const string &attr)\n\n{\n if (attr.size()==0) return false;\n char firstc = attr[0];\n if (firstc=='t') return true;\n if (firstc=='1') return true;\n if (firstc=='y') return true; // For backward compatibility\n return false;\n}\n\n} // End namespace ghidra\n#endif\n" }, { "path": "pypcode/sleigh/xml.y", "content": "/* ###\n * IP: GHIDRA\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n * http://www.apache.org/licenses/LICENSE-2.0\n * \n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n%define api.prefix {xml}\n%{\n#include \"xml.hh\"\n// CharData mode look for '<' '&' or \"]]>\"\n// Name mode look for non-name char\n// CData mode looking for \"]]>\"\n// Entity mode looking for ending ';'\n// AttValue mode looking for endquote or '&'\n// Comment mode looking for \"--\"\n\n#include \n#include \n#include \n#include \n\nnamespace ghidra {\n\nstring Attributes::bogus_uri(\"http://unused.uri\");\n\n/// \\brief The XML character scanner\n///\n/// Tokenize a byte stream suitably for the main XML parser. The scanner expects an ASCII or UTF-8\n/// encoding. Characters is XML tag and attribute names are restricted to ASCII \"letters\", but\n/// extended UTF-8 characters can be used in any other character data: attribute values, content, comments. \nclass XmlScan {\npublic:\n /// \\brief Modes of the scanner\n enum mode { CharDataMode, CDataMode, AttValueSingleMode,\n\t AttValueDoubleMode, CommentMode, CharRefMode,\n\t NameMode, SNameMode, SingleMode };\n /// \\brief Additional tokens returned by the scanner, in addition to byte values 00-ff\n enum token { CharDataToken = 258,\n\t CDataToken = 259,\n\t AttValueToken = 260,\n\t CommentToken =261,\n\t CharRefToken = 262,\n\t NameToken = 263,\n\t SNameToken = 264,\n\t ElementBraceToken = 265,\n\t CommandBraceToken = 266 };\nprivate:\n mode curmode;\t\t\t///< The current scanning mode\n istream &s;\t\t\t///< The stream being scanned\n string *lvalue;\t\t///< Current string being built\n int4 lookahead[4];\t///< Lookahead into the byte stream\n int4 pos;\t\t\t\t///< Current position in the lookahead buffer\n bool endofstream;\t\t///< Has end of stream been reached\n void clearlvalue(void);\t///< Clear the current token string\n\n /// \\brief Get the next byte in the stream\n ///\n /// Maintain a lookahead of 4 bytes at all times so that we can check for special\n /// XML character sequences without consuming.\n /// \\return the next byte value as an integer\n int4 getxmlchar(void) {\n char c;\t \n int4 ret=lookahead[pos];\n if (!endofstream) {\n s.get(c); \n if (s.eof()||(c=='\\0')) {\n\tendofstream = true;\n\tlookahead[pos] = '\\n';\n }\n else\n\tlookahead[pos] = c;\n }\n else\n lookahead[pos] = -1;\n pos = (pos+1)&3;\n return ret;\n }\n int4 next(int4 i) { return lookahead[(pos+i)&3]; }\t///< Peek at the next (i-th) byte without consuming\n bool isLetter(int4 val) { return (((val>=0x41)&&(val<=0x5a))||((val>=0x61)&&(val<=0x7a))); }\t///< Is the given byte a \\e letter\n bool isInitialNameChar(int4 val);\t\t///< Is the given byte/character the valid start of an XML name\n bool isNameChar(int4 val);\t\t\t///< Is the given byte/character valid for an XML name\t\n bool isChar(int4 val);\t\t\t\t///< Is the given byte/character valid as an XML character\n int4 scanSingle(void);\t\t\t\t///< Scan for the next token in Single Character mode\n int4 scanCharData(void);\t\t\t\t///< Scan for the next token is Character Data mode\n int4 scanCData(void);\t\t\t\t\t///< Scan for the next token in CDATA mode\n int4 scanAttValue(int4 quote);\t\t///< Scan for the next token in Attribute Value mode\n int4 scanCharRef(void);\t\t\t\t///< Scan for the next token in Character Reference mode\n int4 scanComment(void);\t\t\t\t///< Scan for the next token in Comment mode\n int4 scanName(void);\t\t\t\t\t///< Scan a Name or return single non-name character\n int4 scanSName(void);\t\t\t\t\t///< Scan Name, allow white space before\npublic:\n XmlScan(istream &t);\t\t\t\t\t///< Construct scanner given a stream\n ~XmlScan(void);\t\t\t\t\t\t///< Destructor\n void setmode(mode m) { curmode = m; }\t///< Set the scanning mode\n int4 nexttoken(void);\t\t\t\t\t///< Get the next token\n string *lval(void) { string *ret = lvalue; lvalue = (string *)0; return ret; }\t///< Return the last \\e lvalue string\n};\n\n/// \\brief A parsed name/value pair\nstruct NameValue {\n string *name;\t\t///< The name\n string *value;\t///< The value\n};\n\nextern int xmllex(void);\t\t\t\t///< Interface to the scanner\nextern int xmlerror(const char *str);\t\t\t///< Interface for registering an error in parsing\nextern void print_content(const string &str);\t///< Send character data to the ContentHandler\nextern int4 convertEntityRef(const string &ref);\t///< Convert an XML entity to its equivalent character\nextern int4 convertCharRef(const string &ref);\t///< Convert an XML character reference to its equivalent character\nstatic XmlScan *global_scan;\t\t\t\t\t///< Global reference to the scanner\nstatic ContentHandler *handler;\t\t\t\t\t///< Global reference to the content handler\nstatic std::mutex global_scan_mutex;\nstatic std::mutex handler_mutex;\n\n%}\n\n%union {\n int4 i;\n string *str;\n Attributes *attr;\n NameValue *pair;\n}\n\n%expect 8\n\n%token CHARDATA CDATA ATTVALUE COMMENT CHARREF NAME SNAME ELEMBRACE COMMBRACE\n%type AttValue attsinglemid attdoublemid ETag CDSect CharRef EntityRef\n%type Reference\n%type EmptyElemTag STag stagstart\n%type SAttribute\n\n%destructor { } \n%destructor { delete $$; } <*>\n%%\n\ndocument: element Misc;\n\t | prolog element Misc;\nwhitespace: ' '\n\t | '\\n'\n\t | '\\r'\n\t | '\\t';\nS: whitespace\n | S whitespace ;\n\nattsinglemid: '\\'' { $$ = new string; global_scan->setmode(XmlScan::AttValueSingleMode); }\n\t | attsinglemid ATTVALUE { $$ = $1; *$$ += *$2; delete $2; global_scan->setmode(XmlScan::AttValueSingleMode); }\n\t | attsinglemid Reference { $$ = $1; *$$ += $2; global_scan->setmode(XmlScan::AttValueSingleMode); };\nattdoublemid: '\"' { $$ = new string; global_scan->setmode(XmlScan::AttValueDoubleMode); }\n\t | attdoublemid ATTVALUE { $$ = $1; *$$ += *$2; delete $2; global_scan->setmode(XmlScan::AttValueDoubleMode); }\n\t | attdoublemid Reference { $$ = $1; *$$ += $2; global_scan->setmode(XmlScan::AttValueDoubleMode); };\nAttValue: attsinglemid '\\'' { $$ = $1; }\n\t | attdoublemid '\"' { $$ = $1; };\nelemstart: ELEMBRACE { global_scan->setmode(XmlScan::NameMode); delete $1; };\ncommentstart: COMMBRACE '!' '-' '-' { global_scan->setmode(XmlScan::CommentMode); delete $1; } ;\nComment: commentstart COMMENT '-' '-' '>' { delete $2; } ;\nPI: COMMBRACE '?' { delete $1; yyerror(\"Processing instructions are not supported\"); YYERROR; };\nCDSect: CDStart CDATA CDEnd { $$ = $2; } ;\nCDStart: COMMBRACE '!' '[' 'C' 'D' 'A' 'T' 'A' '[' { global_scan->setmode(XmlScan::CDataMode); delete $1; } ;\nCDEnd: ']' ']' '>' ;\n\ndoctypepro: doctypedecl\n\t | doctypepro Misc;\nprologpre: XMLDecl\n\t | Misc\n\t | prologpre Misc;\nprolog: prologpre doctypepro\n\t| prologpre ;\n\ndoctypedecl: COMMBRACE '!' 'D' 'O' 'C' 'T' 'Y' 'P' 'E' { delete $1; yyerror(\"DTD's not supported\"); YYERROR; };\nEq: '='\n | S '='\n | Eq S ;\nMisc: Comment\n | PI\n | S ;\n \nVersionInfo: S 'v' 'e' 'r' 's' 'i' 'o' 'n' Eq AttValue { handler->setVersion(*$10); delete $10; };\nEncodingDecl: S 'e' 'n' 'c' 'o' 'd' 'i' 'n' 'g' Eq AttValue { handler->setEncoding(*$11); delete $11; };\nxmldeclstart: COMMBRACE '?' 'x' 'm' 'l' VersionInfo\nXMLDecl: xmldeclstart '?' '>'\n | xmldeclstart S '?' '>'\n | xmldeclstart EncodingDecl '?' '>'\n | xmldeclstart EncodingDecl S '?' '>' ;\n\nelement: EmptyElemTag { handler->endElement($1->getelemURI(),$1->getelemName(),$1->getelemName()); delete $1; }\n\t | STag content ETag { handler->endElement($1->getelemURI(),$1->getelemName(),$1->getelemName()); delete $1; delete $3; } ;\n\nSTag: stagstart '>' { handler->startElement($1->getelemURI(),$1->getelemName(),$1->getelemName(),*$1); $$ = $1; }\n | stagstart S '>' { handler->startElement($1->getelemURI(),$1->getelemName(),$1->getelemName(),*$1); $$ = $1; };\nEmptyElemTag: stagstart '/' '>' { handler->startElement($1->getelemURI(),$1->getelemName(),$1->getelemName(),*$1); $$ = $1; }\n\t | stagstart S '/' '>' { handler->startElement($1->getelemURI(),$1->getelemName(),$1->getelemName(),*$1); $$ = $1; };\n\nstagstart: elemstart NAME { $$ = new Attributes($2); global_scan->setmode(XmlScan::SNameMode); }\n\t | stagstart SAttribute { $$ = $1; $$->add_attribute( $2->name, $2->value); delete $2; global_scan->setmode(XmlScan::SNameMode); };\nSAttribute: SNAME Eq AttValue { $$ = new NameValue; $$->name = $1; $$->value = $3; };\netagbrace: COMMBRACE '/' { global_scan->setmode(XmlScan::NameMode); delete $1; };\nETag: etagbrace NAME '>' { $$ = $2; }\n | etagbrace NAME S '>' { $$ = $2; };\n\ncontent: { global_scan->setmode(XmlScan::CharDataMode); }\n\t | content CHARDATA { print_content( *$2 ); delete $2; global_scan->setmode(XmlScan::CharDataMode); }\n\t | content element { global_scan->setmode(XmlScan::CharDataMode); }\n\t | content Reference { string *tmp=new string(); *tmp += $2; print_content(*tmp); delete tmp; global_scan->setmode(XmlScan::CharDataMode); }\n\t | content CDSect { print_content( *$2 ); delete $2; global_scan->setmode(XmlScan::CharDataMode); }\n\t | content PI { global_scan->setmode(XmlScan::CharDataMode); }\n\t | content Comment { global_scan->setmode(XmlScan::CharDataMode); };\n\nReference: EntityRef { $$ = convertEntityRef(*$1); delete $1; }\n\t | CharRef { $$ = convertCharRef(*$1); delete $1; };\n\nrefstart: '&' { global_scan->setmode(XmlScan::NameMode); } ;\ncharrefstart: refstart '#' { global_scan->setmode(XmlScan::CharRefMode); };\nCharRef: charrefstart CHARREF ';' { $$ = $2; };\nEntityRef: refstart NAME ';' { $$ = $2; };\n%%\n\nXmlScan::XmlScan(istream &t) : s(t)\n\n{\n curmode = SingleMode;\n lvalue = (string *)0;\n pos = 0;\n endofstream = false;\n getxmlchar(); getxmlchar(); getxmlchar(); getxmlchar(); // Fill lookahead buffer\n}\n\nXmlScan::~XmlScan(void)\n\n{\n clearlvalue();\n}\n\nvoid XmlScan::clearlvalue(void)\n\n{\n if (lvalue != (string *)0)\n delete lvalue;\n}\n\nint4 XmlScan::scanSingle(void)\n\n{\n int4 res = getxmlchar();\n if (res == '<') {\n if (isInitialNameChar(next(0))) return ElementBraceToken;\n return CommandBraceToken;\n }\n return res;\n}\n\nint4 XmlScan::scanCharData(void)\n\n{\n clearlvalue();\n lvalue = new string();\n \n while(next(0) != -1) {\t\t// look for '<' '&' or ']]>'\n if (next(0) == '<') break;\n if (next(0) == '&') break;\n if (next(0) == ']')\n if (next(1)== ']')\n\tif (next(2)=='>')\n\t break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size()==0)\n return scanSingle();\n return CharDataToken;\n}\n\nint4 XmlScan::scanCData(void)\n\n{\n clearlvalue();\n lvalue = new string();\n\n while(next(0) != -1) {\t// Look for \"]]>\" and non-Char\n if (next(0)==']')\n if (next(1)==']')\n\tif (next(2)=='>')\n\t break;\n if (!isChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n return CDataToken;\t\t// CData can be empty\n}\n\nint4 XmlScan::scanCharRef(void)\n\n{\n int4 v;\n clearlvalue();\n lvalue = new string();\n if (next(0) == 'x') {\n *lvalue += getxmlchar();\n while(next(0) != -1) {\n v = next(0);\n if (v < '0') break;\n if ((v>'9')&&(v<'A')) break;\n if ((v>'F')&&(v<'a')) break;\n if (v>'f') break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size()==1)\n return 'x';\t\t// Must be at least 1 hex digit\n }\n else {\n while(next(0) != -1) {\n v = next(0);\n if (v<'0') break;\n if (v>'9') break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size()==0)\n return scanSingle();\n }\n return CharRefToken;\n}\n\nint4 XmlScan::scanAttValue(int4 quote)\n\n{\n clearlvalue();\n lvalue = new string();\n while(next(0) != -1) {\n if (next(0) == quote) break;\n if (next(0) == '<') break;\n if (next(0) == '&') break;\n *lvalue += getxmlchar();\n }\n if (lvalue->size() == 0)\n return scanSingle();\n return AttValueToken;\n}\n\nint4 XmlScan::scanComment(void)\n\n{\n clearlvalue();\n lvalue = new string();\n\n while(next(0) != -1) {\n if (next(0)=='-')\n if (next(1)=='-')\n\tbreak;\n if (!isChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n return CommentToken;\n}\n\nint4 XmlScan::scanName(void)\n\n{\n clearlvalue();\n lvalue = new string();\n\n if (!isInitialNameChar(next(0)))\n return scanSingle();\n *lvalue += getxmlchar();\n while(next(0) != -1) {\n if (!isNameChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n return NameToken;\n}\n\nint4 XmlScan::scanSName(void)\n\n{\n int4 whitecount = 0;\n while((next(0)==' ')||(next(0)=='\\n')||(next(0)=='\\r')||(next(0)=='\\t')) {\n whitecount += 1;\n getxmlchar();\n }\n clearlvalue();\n lvalue = new string();\n if (!isInitialNameChar(next(0))) {\t// First non-whitespace is not Name char\n if (whitecount > 0)\n return ' ';\n return scanSingle();\n }\n *lvalue += getxmlchar();\n while(next(0) != -1) {\n if (!isNameChar(next(0))) break;\n *lvalue += getxmlchar();\n }\n if (whitecount>0)\n return SNameToken;\n return NameToken;\n}\n\nbool XmlScan::isInitialNameChar(int4 val)\n\n{\n if (isLetter(val)) return true;\n if ((val=='_')||(val==':')) return true;\n return false;\n}\n\nbool XmlScan::isNameChar(int4 val)\n\n{\n if (isLetter(val)) return true;\n if ((val>='0')&&(val<='9')) return true;\n if ((val=='.')||(val=='-')||(val=='_')||(val==':')) return true;\n return false;\n}\n\nbool XmlScan::isChar(int4 val)\n\n{\n if (val>=0x20) return true;\n if ((val == 0xd)||(val==0xa)||(val==0x9)) return true;\n return false;\n}\n\nint4 XmlScan::nexttoken(void)\n\n{\n mode mymode = curmode;\n curmode = SingleMode;\n switch(mymode) {\n case CharDataMode:\n return scanCharData();\n case CDataMode:\n return scanCData();\n case AttValueSingleMode:\n return scanAttValue('\\'');\n case AttValueDoubleMode:\n return scanAttValue('\"');\n case CommentMode:\n return scanComment();\n case CharRefMode:\n return scanCharRef();\n case NameMode:\n return scanName();\n case SNameMode:\n return scanSName();\n case SingleMode:\n return scanSingle();\n }\n return -1;\n}\n\nvoid print_content(const string &str)\n\n{\n uint4 i;\n for(i=0;iignorableWhitespace(str.c_str(),0,str.size());\n else\n handler->characters(str.c_str(),0,str.size()); \n}\n\nint4 convertEntityRef(const string &ref)\n\n{\n if (ref == \"lt\") return '<';\n if (ref == \"amp\") return '&';\n if (ref == \"gt\") return '>';\n if (ref == \"quot\") return '\"';\n if (ref == \"apos\") return '\\'';\n return -1;\n}\n\nint4 convertCharRef(const string &ref)\n\n{\n uint4 i;\n int4 mult,val,cur;\n\n if (ref[0]=='x') {\n i = 1;\n mult = 16;\n }\n else {\n i = 0;\n mult = 10;\n }\n val = 0;\n for(;inexttoken();\n if (res>255)\n yylval.str = global_scan->lval();\n return res;\n}\n\nint xmlerror(const char *str)\n\n{\n handler->setError(str);\n return 0;\n}\n\nint4 xml_parse(istream &i,ContentHandler *hand,int4 dbg)\n\n{\n#if YYDEBUG\n yydebug = dbg;\n#endif\n std::lock_guard global_scan_lock(global_scan_mutex);\n std::lock_guard handler_lock(handler_mutex);\n global_scan = new XmlScan(i);\n handler = hand;\n handler->startDocument();\n int4 res = yyparse();\n if (res == 0)\n handler->endDocument();\n delete global_scan;\n return res;\n}\n\nvoid TreeHandler::startElement(const string &namespaceURI,const string &localName,\n\t\t\t const string &qualifiedName,const Attributes &atts)\n{\n Element *newel = new Element(cur);\n cur->addChild(newel);\n cur = newel;\n newel->setName(localName);\n for(int4 i=0;iaddAttribute(atts.getLocalName(i),atts.getValue(i));\n}\n\nvoid TreeHandler::endElement(const string &namespaceURI,const string &localName,\n\t\t\t const string &qualifiedName)\n{\n cur = cur->getParent();\n}\n\nvoid TreeHandler::characters(const char *text,int4 start,int4 length)\n\n{\n cur->addContent(text,start,length);\n}\n\nElement::~Element(void)\n\n{\n List::iterator iter;\n \n for(iter=children.begin();iter!=children.end();++iter)\n delete *iter;\n}\n\nconst string &Element::getAttributeValue(const string &nm) const\n\n{\n for(uint4 i=0;igetName()] = el;\n}\n\nconst Element *DocumentStorage::getTag(const string &nm) const\n\n{\n map::const_iterator iter;\n\n iter = tagmap.find(nm);\n if (iter != tagmap.end())\n return (*iter).second;\n return (const Element *)0;\n}\n\nDocument *xml_tree(istream &i)\n\n{\n Document *doc = new Document();\n TreeHandler handle(doc);\n if (0!=xml_parse(i,&handle)) {\n delete doc;\n throw DecoderError(handle.getError());\n }\n return doc;\n}\n\nvoid xml_escape(ostream &s,const char *str)\n\n{\n while(*str!='\\0') {\n if (*str < '?') {\n if (*str=='<') s << \"<\";\n else if (*str=='>') s << \">\";\n else if (*str=='&') s << \"&\";\n else if (*str=='\"') s << \""\";\n else if (*str=='\\'') s << \"'\";\n else s << *str;\n }\n else\n s << *str;\n str++;\n }\n}\n\n} // End namespace ghidra\n" }, { "path": "pypcode/zlib/README.txt", "content": "The source files in this directory are copied from the zlib compression library, version 1.3.1\navailable from https://www.zlib.net/ .\n\nThe source files here are only a subset of the complete zlib library. The files have not been\nchanged except for the addition of a comment at the top of each file, noting its association\nwith the zlib license and the version number.\n\nWithin Ghidra, the zlib license is available (in both the source repository and distributions)\nin licenses/zlib_License.txt. Additionally the license appears at the top of zlib.h in this\ndirectory.\n" }, { "path": "pypcode/zlib/adler32.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* adler32.c -- compute the Adler-32 checksum of a data stream\n * Copyright (C) 1995-2011, 2016 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* @(#) $Id$ */\n\n#include \"zutil.h\"\n\n#define BASE 65521U /* largest prime smaller than 65536 */\n#define NMAX 5552\n/* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */\n\n#define DO1(buf,i) {adler += (buf)[i]; sum2 += adler;}\n#define DO2(buf,i) DO1(buf,i); DO1(buf,i+1);\n#define DO4(buf,i) DO2(buf,i); DO2(buf,i+2);\n#define DO8(buf,i) DO4(buf,i); DO4(buf,i+4);\n#define DO16(buf) DO8(buf,0); DO8(buf,8);\n\n/* use NO_DIVIDE if your processor does not do division in hardware --\n try it both ways to see which is faster */\n#ifdef NO_DIVIDE\n/* note that this assumes BASE is 65521, where 65536 % 65521 == 15\n (thank you to John Reiser for pointing this out) */\n# define CHOP(a) \\\n do { \\\n unsigned long tmp = a >> 16; \\\n a &= 0xffffUL; \\\n a += (tmp << 4) - tmp; \\\n } while (0)\n# define MOD28(a) \\\n do { \\\n CHOP(a); \\\n if (a >= BASE) a -= BASE; \\\n } while (0)\n# define MOD(a) \\\n do { \\\n CHOP(a); \\\n MOD28(a); \\\n } while (0)\n# define MOD63(a) \\\n do { /* this assumes a is not negative */ \\\n z_off64_t tmp = a >> 32; \\\n a &= 0xffffffffL; \\\n a += (tmp << 8) - (tmp << 5) + tmp; \\\n tmp = a >> 16; \\\n a &= 0xffffL; \\\n a += (tmp << 4) - tmp; \\\n tmp = a >> 16; \\\n a &= 0xffffL; \\\n a += (tmp << 4) - tmp; \\\n if (a >= BASE) a -= BASE; \\\n } while (0)\n#else\n# define MOD(a) a %= BASE\n# define MOD28(a) a %= BASE\n# define MOD63(a) a %= BASE\n#endif\n\n/* ========================================================================= */\nuLong ZEXPORT adler32_z(uLong adler, const Bytef *buf, z_size_t len) {\n unsigned long sum2;\n unsigned n;\n\n /* split Adler-32 into component sums */\n sum2 = (adler >> 16) & 0xffff;\n adler &= 0xffff;\n\n /* in case user likes doing a byte at a time, keep it fast */\n if (len == 1) {\n adler += buf[0];\n if (adler >= BASE)\n adler -= BASE;\n sum2 += adler;\n if (sum2 >= BASE)\n sum2 -= BASE;\n return adler | (sum2 << 16);\n }\n\n /* initial Adler-32 value (deferred check for len == 1 speed) */\n if (buf == Z_NULL)\n return 1L;\n\n /* in case short lengths are provided, keep it somewhat fast */\n if (len < 16) {\n while (len--) {\n adler += *buf++;\n sum2 += adler;\n }\n if (adler >= BASE)\n adler -= BASE;\n MOD28(sum2); /* only added so many BASE's */\n return adler | (sum2 << 16);\n }\n\n /* do length NMAX blocks -- requires just one modulo operation */\n while (len >= NMAX) {\n len -= NMAX;\n n = NMAX / 16; /* NMAX is divisible by 16 */\n do {\n DO16(buf); /* 16 sums unrolled */\n buf += 16;\n } while (--n);\n MOD(adler);\n MOD(sum2);\n }\n\n /* do remaining bytes (less than NMAX, still just one modulo) */\n if (len) { /* avoid modulos if none remaining */\n while (len >= 16) {\n len -= 16;\n DO16(buf);\n buf += 16;\n }\n while (len--) {\n adler += *buf++;\n sum2 += adler;\n }\n MOD(adler);\n MOD(sum2);\n }\n\n /* return recombined sums */\n return adler | (sum2 << 16);\n}\n\n/* ========================================================================= */\nuLong ZEXPORT adler32(uLong adler, const Bytef *buf, uInt len) {\n return adler32_z(adler, buf, len);\n}\n\n/* ========================================================================= */\nlocal uLong adler32_combine_(uLong adler1, uLong adler2, z_off64_t len2) {\n unsigned long sum1;\n unsigned long sum2;\n unsigned rem;\n\n /* for negative len, return invalid adler32 as a clue for debugging */\n if (len2 < 0)\n return 0xffffffffUL;\n\n /* the derivation of this formula is left as an exercise for the reader */\n MOD63(len2); /* assumes len2 >= 0 */\n rem = (unsigned)len2;\n sum1 = adler1 & 0xffff;\n sum2 = rem * sum1;\n MOD(sum2);\n sum1 += (adler2 & 0xffff) + BASE - 1;\n sum2 += ((adler1 >> 16) & 0xffff) + ((adler2 >> 16) & 0xffff) + BASE - rem;\n if (sum1 >= BASE) sum1 -= BASE;\n if (sum1 >= BASE) sum1 -= BASE;\n if (sum2 >= ((unsigned long)BASE << 1)) sum2 -= ((unsigned long)BASE << 1);\n if (sum2 >= BASE) sum2 -= BASE;\n return sum1 | (sum2 << 16);\n}\n\n/* ========================================================================= */\nuLong ZEXPORT adler32_combine(uLong adler1, uLong adler2, z_off_t len2) {\n return adler32_combine_(adler1, adler2, len2);\n}\n\nuLong ZEXPORT adler32_combine64(uLong adler1, uLong adler2, z_off64_t len2) {\n return adler32_combine_(adler1, adler2, len2);\n}\n" }, { "path": "pypcode/zlib/deflate.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* deflate.c -- compress data using the deflation algorithm\n * Copyright (C) 1995-2024 Jean-loup Gailly and Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/*\n * ALGORITHM\n *\n * The \"deflation\" process depends on being able to identify portions\n * of the input text which are identical to earlier input (within a\n * sliding window trailing behind the input currently being processed).\n *\n * The most straightforward technique turns out to be the fastest for\n * most input files: try all possible matches and select the longest.\n * The key feature of this algorithm is that insertions into the string\n * dictionary are very simple and thus fast, and deletions are avoided\n * completely. Insertions are performed at each input character, whereas\n * string matches are performed only when the previous match ends. So it\n * is preferable to spend more time in matches to allow very fast string\n * insertions and avoid deletions. The matching algorithm for small\n * strings is inspired from that of Rabin & Karp. A brute force approach\n * is used to find longer strings when a small match has been found.\n * A similar algorithm is used in comic (by Jan-Mark Wams) and freeze\n * (by Leonid Broukhis).\n * A previous version of this file used a more sophisticated algorithm\n * (by Fiala and Greene) which is guaranteed to run in linear amortized\n * time, but has a larger average cost, uses more memory and is patented.\n * However the F&G algorithm may be faster for some highly redundant\n * files if the parameter max_chain_length (described below) is too large.\n *\n * ACKNOWLEDGEMENTS\n *\n * The idea of lazy evaluation of matches is due to Jan-Mark Wams, and\n * I found it in 'freeze' written by Leonid Broukhis.\n * Thanks to many people for bug reports and testing.\n *\n * REFERENCES\n *\n * Deutsch, L.P.,\"DEFLATE Compressed Data Format Specification\".\n * Available in http://tools.ietf.org/html/rfc1951\n *\n * A description of the Rabin and Karp algorithm is given in the book\n * \"Algorithms\" by R. Sedgewick, Addison-Wesley, p252.\n *\n * Fiala,E.R., and Greene,D.H.\n * Data Compression with Finite Windows, Comm.ACM, 32,4 (1989) 490-595\n *\n */\n\n/* @(#) $Id$ */\n\n#include \"deflate.h\"\n\nconst char deflate_copyright[] =\n \" deflate 1.3.1 Copyright 1995-2024 Jean-loup Gailly and Mark Adler \";\n/*\n If you use the zlib library in a product, an acknowledgment is welcome\n in the documentation of your product. If for some reason you cannot\n include such an acknowledgment, I would appreciate that you keep this\n copyright string in the executable of your product.\n */\n\ntypedef enum {\n need_more, /* block not completed, need more input or more output */\n block_done, /* block flush performed */\n finish_started, /* finish started, need only more output at next deflate */\n finish_done /* finish done, accept no more input or output */\n} block_state;\n\ntypedef block_state (*compress_func)(deflate_state *s, int flush);\n/* Compression function. Returns the block state after the call. */\n\nlocal block_state deflate_stored(deflate_state *s, int flush);\nlocal block_state deflate_fast(deflate_state *s, int flush);\n#ifndef FASTEST\nlocal block_state deflate_slow(deflate_state *s, int flush);\n#endif\nlocal block_state deflate_rle(deflate_state *s, int flush);\nlocal block_state deflate_huff(deflate_state *s, int flush);\n\n/* ===========================================================================\n * Local data\n */\n\n#define NIL 0\n/* Tail of hash chains */\n\n#ifndef TOO_FAR\n# define TOO_FAR 4096\n#endif\n/* Matches of length 3 are discarded if their distance exceeds TOO_FAR */\n\n/* Values for max_lazy_match, good_match and max_chain_length, depending on\n * the desired pack level (0..9). The values given below have been tuned to\n * exclude worst case performance for pathological files. Better values may be\n * found for specific files.\n */\ntypedef struct config_s {\n ush good_length; /* reduce lazy search above this match length */\n ush max_lazy; /* do not perform lazy search above this match length */\n ush nice_length; /* quit search above this match length */\n ush max_chain;\n compress_func func;\n} config;\n\n#ifdef FASTEST\nlocal const config configuration_table[2] = {\n/* good lazy nice chain */\n/* 0 */ {0, 0, 0, 0, deflate_stored}, /* store only */\n/* 1 */ {4, 4, 8, 4, deflate_fast}}; /* max speed, no lazy matches */\n#else\nlocal const config configuration_table[10] = {\n/* good lazy nice chain */\n/* 0 */ {0, 0, 0, 0, deflate_stored}, /* store only */\n/* 1 */ {4, 4, 8, 4, deflate_fast}, /* max speed, no lazy matches */\n/* 2 */ {4, 5, 16, 8, deflate_fast},\n/* 3 */ {4, 6, 32, 32, deflate_fast},\n\n/* 4 */ {4, 4, 16, 16, deflate_slow}, /* lazy matches */\n/* 5 */ {8, 16, 32, 32, deflate_slow},\n/* 6 */ {8, 16, 128, 128, deflate_slow},\n/* 7 */ {8, 32, 128, 256, deflate_slow},\n/* 8 */ {32, 128, 258, 1024, deflate_slow},\n/* 9 */ {32, 258, 258, 4096, deflate_slow}}; /* max compression */\n#endif\n\n/* Note: the deflate() code requires max_lazy >= MIN_MATCH and max_chain >= 4\n * For deflate_fast() (levels <= 3) good is ignored and lazy has a different\n * meaning.\n */\n\n/* rank Z_BLOCK between Z_NO_FLUSH and Z_PARTIAL_FLUSH */\n#define RANK(f) (((f) * 2) - ((f) > 4 ? 9 : 0))\n\n/* ===========================================================================\n * Update a hash value with the given input byte\n * IN assertion: all calls to UPDATE_HASH are made with consecutive input\n * characters, so that a running hash key can be computed from the previous\n * key instead of complete recalculation each time.\n */\n#define UPDATE_HASH(s,h,c) (h = (((h) << s->hash_shift) ^ (c)) & s->hash_mask)\n\n\n/* ===========================================================================\n * Insert string str in the dictionary and set match_head to the previous head\n * of the hash chain (the most recent string with same hash key). Return\n * the previous length of the hash chain.\n * If this file is compiled with -DFASTEST, the compression level is forced\n * to 1, and no hash chains are maintained.\n * IN assertion: all calls to INSERT_STRING are made with consecutive input\n * characters and the first MIN_MATCH bytes of str are valid (except for\n * the last MIN_MATCH-1 bytes of the input file).\n */\n#ifdef FASTEST\n#define INSERT_STRING(s, str, match_head) \\\n (UPDATE_HASH(s, s->ins_h, s->window[(str) + (MIN_MATCH-1)]), \\\n match_head = s->head[s->ins_h], \\\n s->head[s->ins_h] = (Pos)(str))\n#else\n#define INSERT_STRING(s, str, match_head) \\\n (UPDATE_HASH(s, s->ins_h, s->window[(str) + (MIN_MATCH-1)]), \\\n match_head = s->prev[(str) & s->w_mask] = s->head[s->ins_h], \\\n s->head[s->ins_h] = (Pos)(str))\n#endif\n\n/* ===========================================================================\n * Initialize the hash table (avoiding 64K overflow for 16 bit systems).\n * prev[] will be initialized on the fly.\n */\n#define CLEAR_HASH(s) \\\n do { \\\n s->head[s->hash_size - 1] = NIL; \\\n zmemzero((Bytef *)s->head, \\\n (unsigned)(s->hash_size - 1)*sizeof(*s->head)); \\\n } while (0)\n\n/* ===========================================================================\n * Slide the hash table when sliding the window down (could be avoided with 32\n * bit values at the expense of memory usage). We slide even when level == 0 to\n * keep the hash table consistent if we switch back to level > 0 later.\n */\n#if defined(__has_feature)\n# if __has_feature(memory_sanitizer)\n __attribute__((no_sanitize(\"memory\")))\n# endif\n#endif\nlocal void slide_hash(deflate_state *s) {\n unsigned n, m;\n Posf *p;\n uInt wsize = s->w_size;\n\n n = s->hash_size;\n p = &s->head[n];\n do {\n m = *--p;\n *p = (Pos)(m >= wsize ? m - wsize : NIL);\n } while (--n);\n n = wsize;\n#ifndef FASTEST\n p = &s->prev[n];\n do {\n m = *--p;\n *p = (Pos)(m >= wsize ? m - wsize : NIL);\n /* If n is not on any hash chain, prev[n] is garbage but\n * its value will never be used.\n */\n } while (--n);\n#endif\n}\n\n/* ===========================================================================\n * Read a new buffer from the current input stream, update the adler32\n * and total number of bytes read. All deflate() input goes through\n * this function so some applications may wish to modify it to avoid\n * allocating a large strm->next_in buffer and copying from it.\n * (See also flush_pending()).\n */\nlocal unsigned read_buf(z_streamp strm, Bytef *buf, unsigned size) {\n unsigned len = strm->avail_in;\n\n if (len > size) len = size;\n if (len == 0) return 0;\n\n strm->avail_in -= len;\n\n zmemcpy(buf, strm->next_in, len);\n if (strm->state->wrap == 1) {\n strm->adler = adler32(strm->adler, buf, len);\n }\n#ifdef GZIP\n else if (strm->state->wrap == 2) {\n strm->adler = crc32(strm->adler, buf, len);\n }\n#endif\n strm->next_in += len;\n strm->total_in += len;\n\n return len;\n}\n\n/* ===========================================================================\n * Fill the window when the lookahead becomes insufficient.\n * Updates strstart and lookahead.\n *\n * IN assertion: lookahead < MIN_LOOKAHEAD\n * OUT assertions: strstart <= window_size-MIN_LOOKAHEAD\n * At least one byte has been read, or avail_in == 0; reads are\n * performed for at least two bytes (required for the zip translate_eol\n * option -- not supported here).\n */\nlocal void fill_window(deflate_state *s) {\n unsigned n;\n unsigned more; /* Amount of free space at the end of the window. */\n uInt wsize = s->w_size;\n\n Assert(s->lookahead < MIN_LOOKAHEAD, \"already enough lookahead\");\n\n do {\n more = (unsigned)(s->window_size -(ulg)s->lookahead -(ulg)s->strstart);\n\n /* Deal with !@#$% 64K limit: */\n if (sizeof(int) <= 2) {\n if (more == 0 && s->strstart == 0 && s->lookahead == 0) {\n more = wsize;\n\n } else if (more == (unsigned)(-1)) {\n /* Very unlikely, but possible on 16 bit machine if\n * strstart == 0 && lookahead == 1 (input done a byte at time)\n */\n more--;\n }\n }\n\n /* If the window is almost full and there is insufficient lookahead,\n * move the upper half to the lower one to make room in the upper half.\n */\n if (s->strstart >= wsize + MAX_DIST(s)) {\n\n zmemcpy(s->window, s->window + wsize, (unsigned)wsize - more);\n s->match_start -= wsize;\n s->strstart -= wsize; /* we now have strstart >= MAX_DIST */\n s->block_start -= (long) wsize;\n if (s->insert > s->strstart)\n s->insert = s->strstart;\n slide_hash(s);\n more += wsize;\n }\n if (s->strm->avail_in == 0) break;\n\n /* If there was no sliding:\n * strstart <= WSIZE+MAX_DIST-1 && lookahead <= MIN_LOOKAHEAD - 1 &&\n * more == window_size - lookahead - strstart\n * => more >= window_size - (MIN_LOOKAHEAD-1 + WSIZE + MAX_DIST-1)\n * => more >= window_size - 2*WSIZE + 2\n * In the BIG_MEM or MMAP case (not yet supported),\n * window_size == input_size + MIN_LOOKAHEAD &&\n * strstart + s->lookahead <= input_size => more >= MIN_LOOKAHEAD.\n * Otherwise, window_size == 2*WSIZE so more >= 2.\n * If there was sliding, more >= WSIZE. So in all cases, more >= 2.\n */\n Assert(more >= 2, \"more < 2\");\n\n n = read_buf(s->strm, s->window + s->strstart + s->lookahead, more);\n s->lookahead += n;\n\n /* Initialize the hash value now that we have some input: */\n if (s->lookahead + s->insert >= MIN_MATCH) {\n uInt str = s->strstart - s->insert;\n s->ins_h = s->window[str];\n UPDATE_HASH(s, s->ins_h, s->window[str + 1]);\n#if MIN_MATCH != 3\n Call UPDATE_HASH() MIN_MATCH-3 more times\n#endif\n while (s->insert) {\n UPDATE_HASH(s, s->ins_h, s->window[str + MIN_MATCH-1]);\n#ifndef FASTEST\n s->prev[str & s->w_mask] = s->head[s->ins_h];\n#endif\n s->head[s->ins_h] = (Pos)str;\n str++;\n s->insert--;\n if (s->lookahead + s->insert < MIN_MATCH)\n break;\n }\n }\n /* If the whole input has less than MIN_MATCH bytes, ins_h is garbage,\n * but this is not important since only literal bytes will be emitted.\n */\n\n } while (s->lookahead < MIN_LOOKAHEAD && s->strm->avail_in != 0);\n\n /* If the WIN_INIT bytes after the end of the current data have never been\n * written, then zero those bytes in order to avoid memory check reports of\n * the use of uninitialized (or uninitialised as Julian writes) bytes by\n * the longest match routines. Update the high water mark for the next\n * time through here. WIN_INIT is set to MAX_MATCH since the longest match\n * routines allow scanning to strstart + MAX_MATCH, ignoring lookahead.\n */\n if (s->high_water < s->window_size) {\n ulg curr = s->strstart + (ulg)(s->lookahead);\n ulg init;\n\n if (s->high_water < curr) {\n /* Previous high water mark below current data -- zero WIN_INIT\n * bytes or up to end of window, whichever is less.\n */\n init = s->window_size - curr;\n if (init > WIN_INIT)\n init = WIN_INIT;\n zmemzero(s->window + curr, (unsigned)init);\n s->high_water = curr + init;\n }\n else if (s->high_water < (ulg)curr + WIN_INIT) {\n /* High water mark at or above current data, but below current data\n * plus WIN_INIT -- zero out to current data plus WIN_INIT, or up\n * to end of window, whichever is less.\n */\n init = (ulg)curr + WIN_INIT - s->high_water;\n if (init > s->window_size - s->high_water)\n init = s->window_size - s->high_water;\n zmemzero(s->window + s->high_water, (unsigned)init);\n s->high_water += init;\n }\n }\n\n Assert((ulg)s->strstart <= s->window_size - MIN_LOOKAHEAD,\n \"not enough room for search\");\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateInit_(z_streamp strm, int level, const char *version,\n int stream_size) {\n return deflateInit2_(strm, level, Z_DEFLATED, MAX_WBITS, DEF_MEM_LEVEL,\n Z_DEFAULT_STRATEGY, version, stream_size);\n /* To do: ignore strm->next_in if we use it as window */\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateInit2_(z_streamp strm, int level, int method,\n int windowBits, int memLevel, int strategy,\n const char *version, int stream_size) {\n deflate_state *s;\n int wrap = 1;\n static const char my_version[] = ZLIB_VERSION;\n\n if (version == Z_NULL || version[0] != my_version[0] ||\n stream_size != sizeof(z_stream)) {\n return Z_VERSION_ERROR;\n }\n if (strm == Z_NULL) return Z_STREAM_ERROR;\n\n strm->msg = Z_NULL;\n if (strm->zalloc == (alloc_func)0) {\n#ifdef Z_SOLO\n return Z_STREAM_ERROR;\n#else\n strm->zalloc = zcalloc;\n strm->opaque = (voidpf)0;\n#endif\n }\n if (strm->zfree == (free_func)0)\n#ifdef Z_SOLO\n return Z_STREAM_ERROR;\n#else\n strm->zfree = zcfree;\n#endif\n\n#ifdef FASTEST\n if (level != 0) level = 1;\n#else\n if (level == Z_DEFAULT_COMPRESSION) level = 6;\n#endif\n\n if (windowBits < 0) { /* suppress zlib wrapper */\n wrap = 0;\n if (windowBits < -15)\n return Z_STREAM_ERROR;\n windowBits = -windowBits;\n }\n#ifdef GZIP\n else if (windowBits > 15) {\n wrap = 2; /* write gzip wrapper instead */\n windowBits -= 16;\n }\n#endif\n if (memLevel < 1 || memLevel > MAX_MEM_LEVEL || method != Z_DEFLATED ||\n windowBits < 8 || windowBits > 15 || level < 0 || level > 9 ||\n strategy < 0 || strategy > Z_FIXED || (windowBits == 8 && wrap != 1)) {\n return Z_STREAM_ERROR;\n }\n if (windowBits == 8) windowBits = 9; /* until 256-byte window bug fixed */\n s = (deflate_state *) ZALLOC(strm, 1, sizeof(deflate_state));\n if (s == Z_NULL) return Z_MEM_ERROR;\n strm->state = (struct internal_state FAR *)s;\n s->strm = strm;\n s->status = INIT_STATE; /* to pass state test in deflateReset() */\n\n s->wrap = wrap;\n s->gzhead = Z_NULL;\n s->w_bits = (uInt)windowBits;\n s->w_size = 1 << s->w_bits;\n s->w_mask = s->w_size - 1;\n\n s->hash_bits = (uInt)memLevel + 7;\n s->hash_size = 1 << s->hash_bits;\n s->hash_mask = s->hash_size - 1;\n s->hash_shift = ((s->hash_bits + MIN_MATCH-1) / MIN_MATCH);\n\n s->window = (Bytef *) ZALLOC(strm, s->w_size, 2*sizeof(Byte));\n s->prev = (Posf *) ZALLOC(strm, s->w_size, sizeof(Pos));\n s->head = (Posf *) ZALLOC(strm, s->hash_size, sizeof(Pos));\n\n s->high_water = 0; /* nothing written to s->window yet */\n\n s->lit_bufsize = 1 << (memLevel + 6); /* 16K elements by default */\n\n /* We overlay pending_buf and sym_buf. This works since the average size\n * for length/distance pairs over any compressed block is assured to be 31\n * bits or less.\n *\n * Analysis: The longest fixed codes are a length code of 8 bits plus 5\n * extra bits, for lengths 131 to 257. The longest fixed distance codes are\n * 5 bits plus 13 extra bits, for distances 16385 to 32768. The longest\n * possible fixed-codes length/distance pair is then 31 bits total.\n *\n * sym_buf starts one-fourth of the way into pending_buf. So there are\n * three bytes in sym_buf for every four bytes in pending_buf. Each symbol\n * in sym_buf is three bytes -- two for the distance and one for the\n * literal/length. As each symbol is consumed, the pointer to the next\n * sym_buf value to read moves forward three bytes. From that symbol, up to\n * 31 bits are written to pending_buf. The closest the written pending_buf\n * bits gets to the next sym_buf symbol to read is just before the last\n * code is written. At that time, 31*(n - 2) bits have been written, just\n * after 24*(n - 2) bits have been consumed from sym_buf. sym_buf starts at\n * 8*n bits into pending_buf. (Note that the symbol buffer fills when n - 1\n * symbols are written.) The closest the writing gets to what is unread is\n * then n + 14 bits. Here n is lit_bufsize, which is 16384 by default, and\n * can range from 128 to 32768.\n *\n * Therefore, at a minimum, there are 142 bits of space between what is\n * written and what is read in the overlain buffers, so the symbols cannot\n * be overwritten by the compressed data. That space is actually 139 bits,\n * due to the three-bit fixed-code block header.\n *\n * That covers the case where either Z_FIXED is specified, forcing fixed\n * codes, or when the use of fixed codes is chosen, because that choice\n * results in a smaller compressed block than dynamic codes. That latter\n * condition then assures that the above analysis also covers all dynamic\n * blocks. A dynamic-code block will only be chosen to be emitted if it has\n * fewer bits than a fixed-code block would for the same set of symbols.\n * Therefore its average symbol length is assured to be less than 31. So\n * the compressed data for a dynamic block also cannot overwrite the\n * symbols from which it is being constructed.\n */\n\n s->pending_buf = (uchf *) ZALLOC(strm, s->lit_bufsize, LIT_BUFS);\n s->pending_buf_size = (ulg)s->lit_bufsize * 4;\n\n if (s->window == Z_NULL || s->prev == Z_NULL || s->head == Z_NULL ||\n s->pending_buf == Z_NULL) {\n s->status = FINISH_STATE;\n strm->msg = ERR_MSG(Z_MEM_ERROR);\n deflateEnd (strm);\n return Z_MEM_ERROR;\n }\n#ifdef LIT_MEM\n s->d_buf = (ushf *)(s->pending_buf + (s->lit_bufsize << 1));\n s->l_buf = s->pending_buf + (s->lit_bufsize << 2);\n s->sym_end = s->lit_bufsize - 1;\n#else\n s->sym_buf = s->pending_buf + s->lit_bufsize;\n s->sym_end = (s->lit_bufsize - 1) * 3;\n#endif\n /* We avoid equality with lit_bufsize*3 because of wraparound at 64K\n * on 16 bit machines and because stored blocks are restricted to\n * 64K-1 bytes.\n */\n\n s->level = level;\n s->strategy = strategy;\n s->method = (Byte)method;\n\n return deflateReset(strm);\n}\n\n/* =========================================================================\n * Check for a valid deflate stream state. Return 0 if ok, 1 if not.\n */\nlocal int deflateStateCheck(z_streamp strm) {\n deflate_state *s;\n if (strm == Z_NULL ||\n strm->zalloc == (alloc_func)0 || strm->zfree == (free_func)0)\n return 1;\n s = strm->state;\n if (s == Z_NULL || s->strm != strm || (s->status != INIT_STATE &&\n#ifdef GZIP\n s->status != GZIP_STATE &&\n#endif\n s->status != EXTRA_STATE &&\n s->status != NAME_STATE &&\n s->status != COMMENT_STATE &&\n s->status != HCRC_STATE &&\n s->status != BUSY_STATE &&\n s->status != FINISH_STATE))\n return 1;\n return 0;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateSetDictionary(z_streamp strm, const Bytef *dictionary,\n uInt dictLength) {\n deflate_state *s;\n uInt str, n;\n int wrap;\n unsigned avail;\n z_const unsigned char *next;\n\n if (deflateStateCheck(strm) || dictionary == Z_NULL)\n return Z_STREAM_ERROR;\n s = strm->state;\n wrap = s->wrap;\n if (wrap == 2 || (wrap == 1 && s->status != INIT_STATE) || s->lookahead)\n return Z_STREAM_ERROR;\n\n /* when using zlib wrappers, compute Adler-32 for provided dictionary */\n if (wrap == 1)\n strm->adler = adler32(strm->adler, dictionary, dictLength);\n s->wrap = 0; /* avoid computing Adler-32 in read_buf */\n\n /* if dictionary would fill window, just replace the history */\n if (dictLength >= s->w_size) {\n if (wrap == 0) { /* already empty otherwise */\n CLEAR_HASH(s);\n s->strstart = 0;\n s->block_start = 0L;\n s->insert = 0;\n }\n dictionary += dictLength - s->w_size; /* use the tail */\n dictLength = s->w_size;\n }\n\n /* insert dictionary into window and hash */\n avail = strm->avail_in;\n next = strm->next_in;\n strm->avail_in = dictLength;\n strm->next_in = (z_const Bytef *)dictionary;\n fill_window(s);\n while (s->lookahead >= MIN_MATCH) {\n str = s->strstart;\n n = s->lookahead - (MIN_MATCH-1);\n do {\n UPDATE_HASH(s, s->ins_h, s->window[str + MIN_MATCH-1]);\n#ifndef FASTEST\n s->prev[str & s->w_mask] = s->head[s->ins_h];\n#endif\n s->head[s->ins_h] = (Pos)str;\n str++;\n } while (--n);\n s->strstart = str;\n s->lookahead = MIN_MATCH-1;\n fill_window(s);\n }\n s->strstart += s->lookahead;\n s->block_start = (long)s->strstart;\n s->insert = s->lookahead;\n s->lookahead = 0;\n s->match_length = s->prev_length = MIN_MATCH-1;\n s->match_available = 0;\n strm->next_in = next;\n strm->avail_in = avail;\n s->wrap = wrap;\n return Z_OK;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateGetDictionary(z_streamp strm, Bytef *dictionary,\n uInt *dictLength) {\n deflate_state *s;\n uInt len;\n\n if (deflateStateCheck(strm))\n return Z_STREAM_ERROR;\n s = strm->state;\n len = s->strstart + s->lookahead;\n if (len > s->w_size)\n len = s->w_size;\n if (dictionary != Z_NULL && len)\n zmemcpy(dictionary, s->window + s->strstart + s->lookahead - len, len);\n if (dictLength != Z_NULL)\n *dictLength = len;\n return Z_OK;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateResetKeep(z_streamp strm) {\n deflate_state *s;\n\n if (deflateStateCheck(strm)) {\n return Z_STREAM_ERROR;\n }\n\n strm->total_in = strm->total_out = 0;\n strm->msg = Z_NULL; /* use zfree if we ever allocate msg dynamically */\n strm->data_type = Z_UNKNOWN;\n\n s = (deflate_state *)strm->state;\n s->pending = 0;\n s->pending_out = s->pending_buf;\n\n if (s->wrap < 0) {\n s->wrap = -s->wrap; /* was made negative by deflate(..., Z_FINISH); */\n }\n s->status =\n#ifdef GZIP\n s->wrap == 2 ? GZIP_STATE :\n#endif\n INIT_STATE;\n strm->adler =\n#ifdef GZIP\n s->wrap == 2 ? crc32(0L, Z_NULL, 0) :\n#endif\n adler32(0L, Z_NULL, 0);\n s->last_flush = -2;\n\n _tr_init(s);\n\n return Z_OK;\n}\n\n/* ===========================================================================\n * Initialize the \"longest match\" routines for a new zlib stream\n */\nlocal void lm_init(deflate_state *s) {\n s->window_size = (ulg)2L*s->w_size;\n\n CLEAR_HASH(s);\n\n /* Set the default configuration parameters:\n */\n s->max_lazy_match = configuration_table[s->level].max_lazy;\n s->good_match = configuration_table[s->level].good_length;\n s->nice_match = configuration_table[s->level].nice_length;\n s->max_chain_length = configuration_table[s->level].max_chain;\n\n s->strstart = 0;\n s->block_start = 0L;\n s->lookahead = 0;\n s->insert = 0;\n s->match_length = s->prev_length = MIN_MATCH-1;\n s->match_available = 0;\n s->ins_h = 0;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateReset(z_streamp strm) {\n int ret;\n\n ret = deflateResetKeep(strm);\n if (ret == Z_OK)\n lm_init(strm->state);\n return ret;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateSetHeader(z_streamp strm, gz_headerp head) {\n if (deflateStateCheck(strm) || strm->state->wrap != 2)\n return Z_STREAM_ERROR;\n strm->state->gzhead = head;\n return Z_OK;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflatePending(z_streamp strm, unsigned *pending, int *bits) {\n if (deflateStateCheck(strm)) return Z_STREAM_ERROR;\n if (pending != Z_NULL)\n *pending = strm->state->pending;\n if (bits != Z_NULL)\n *bits = strm->state->bi_valid;\n return Z_OK;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflatePrime(z_streamp strm, int bits, int value) {\n deflate_state *s;\n int put;\n\n if (deflateStateCheck(strm)) return Z_STREAM_ERROR;\n s = strm->state;\n#ifdef LIT_MEM\n if (bits < 0 || bits > 16 ||\n (uchf *)s->d_buf < s->pending_out + ((Buf_size + 7) >> 3))\n return Z_BUF_ERROR;\n#else\n if (bits < 0 || bits > 16 ||\n s->sym_buf < s->pending_out + ((Buf_size + 7) >> 3))\n return Z_BUF_ERROR;\n#endif\n do {\n put = Buf_size - s->bi_valid;\n if (put > bits)\n put = bits;\n s->bi_buf |= (ush)((value & ((1 << put) - 1)) << s->bi_valid);\n s->bi_valid += put;\n _tr_flush_bits(s);\n value >>= put;\n bits -= put;\n } while (bits);\n return Z_OK;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateParams(z_streamp strm, int level, int strategy) {\n deflate_state *s;\n compress_func func;\n\n if (deflateStateCheck(strm)) return Z_STREAM_ERROR;\n s = strm->state;\n\n#ifdef FASTEST\n if (level != 0) level = 1;\n#else\n if (level == Z_DEFAULT_COMPRESSION) level = 6;\n#endif\n if (level < 0 || level > 9 || strategy < 0 || strategy > Z_FIXED) {\n return Z_STREAM_ERROR;\n }\n func = configuration_table[s->level].func;\n\n if ((strategy != s->strategy || func != configuration_table[level].func) &&\n s->last_flush != -2) {\n /* Flush the last buffer: */\n int err = deflate(strm, Z_BLOCK);\n if (err == Z_STREAM_ERROR)\n return err;\n if (strm->avail_in || (s->strstart - s->block_start) + s->lookahead)\n return Z_BUF_ERROR;\n }\n if (s->level != level) {\n if (s->level == 0 && s->matches != 0) {\n if (s->matches == 1)\n slide_hash(s);\n else\n CLEAR_HASH(s);\n s->matches = 0;\n }\n s->level = level;\n s->max_lazy_match = configuration_table[level].max_lazy;\n s->good_match = configuration_table[level].good_length;\n s->nice_match = configuration_table[level].nice_length;\n s->max_chain_length = configuration_table[level].max_chain;\n }\n s->strategy = strategy;\n return Z_OK;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateTune(z_streamp strm, int good_length, int max_lazy,\n int nice_length, int max_chain) {\n deflate_state *s;\n\n if (deflateStateCheck(strm)) return Z_STREAM_ERROR;\n s = strm->state;\n s->good_match = (uInt)good_length;\n s->max_lazy_match = (uInt)max_lazy;\n s->nice_match = nice_length;\n s->max_chain_length = (uInt)max_chain;\n return Z_OK;\n}\n\n/* =========================================================================\n * For the default windowBits of 15 and memLevel of 8, this function returns a\n * close to exact, as well as small, upper bound on the compressed size. This\n * is an expansion of ~0.03%, plus a small constant.\n *\n * For any setting other than those defaults for windowBits and memLevel, one\n * of two worst case bounds is returned. This is at most an expansion of ~4% or\n * ~13%, plus a small constant.\n *\n * Both the 0.03% and 4% derive from the overhead of stored blocks. The first\n * one is for stored blocks of 16383 bytes (memLevel == 8), whereas the second\n * is for stored blocks of 127 bytes (the worst case memLevel == 1). The\n * expansion results from five bytes of header for each stored block.\n *\n * The larger expansion of 13% results from a window size less than or equal to\n * the symbols buffer size (windowBits <= memLevel + 7). In that case some of\n * the data being compressed may have slid out of the sliding window, impeding\n * a stored block from being emitted. Then the only choice is a fixed or\n * dynamic block, where a fixed block limits the maximum expansion to 9 bits\n * per 8-bit byte, plus 10 bits for every block. The smallest block size for\n * which this can occur is 255 (memLevel == 2).\n *\n * Shifts are used to approximate divisions, for speed.\n */\nuLong ZEXPORT deflateBound(z_streamp strm, uLong sourceLen) {\n deflate_state *s;\n uLong fixedlen, storelen, wraplen;\n\n /* upper bound for fixed blocks with 9-bit literals and length 255\n (memLevel == 2, which is the lowest that may not use stored blocks) --\n ~13% overhead plus a small constant */\n fixedlen = sourceLen + (sourceLen >> 3) + (sourceLen >> 8) +\n (sourceLen >> 9) + 4;\n\n /* upper bound for stored blocks with length 127 (memLevel == 1) --\n ~4% overhead plus a small constant */\n storelen = sourceLen + (sourceLen >> 5) + (sourceLen >> 7) +\n (sourceLen >> 11) + 7;\n\n /* if can't get parameters, return larger bound plus a zlib wrapper */\n if (deflateStateCheck(strm))\n return (fixedlen > storelen ? fixedlen : storelen) + 6;\n\n /* compute wrapper length */\n s = strm->state;\n switch (s->wrap) {\n case 0: /* raw deflate */\n wraplen = 0;\n break;\n case 1: /* zlib wrapper */\n wraplen = 6 + (s->strstart ? 4 : 0);\n break;\n#ifdef GZIP\n case 2: /* gzip wrapper */\n wraplen = 18;\n if (s->gzhead != Z_NULL) { /* user-supplied gzip header */\n Bytef *str;\n if (s->gzhead->extra != Z_NULL)\n wraplen += 2 + s->gzhead->extra_len;\n str = s->gzhead->name;\n if (str != Z_NULL)\n do {\n wraplen++;\n } while (*str++);\n str = s->gzhead->comment;\n if (str != Z_NULL)\n do {\n wraplen++;\n } while (*str++);\n if (s->gzhead->hcrc)\n wraplen += 2;\n }\n break;\n#endif\n default: /* for compiler happiness */\n wraplen = 6;\n }\n\n /* if not default parameters, return one of the conservative bounds */\n if (s->w_bits != 15 || s->hash_bits != 8 + 7)\n return (s->w_bits <= s->hash_bits && s->level ? fixedlen : storelen) +\n wraplen;\n\n /* default settings: return tight bound for that case -- ~0.03% overhead\n plus a small constant */\n return sourceLen + (sourceLen >> 12) + (sourceLen >> 14) +\n (sourceLen >> 25) + 13 - 6 + wraplen;\n}\n\n/* =========================================================================\n * Put a short in the pending buffer. The 16-bit value is put in MSB order.\n * IN assertion: the stream state is correct and there is enough room in\n * pending_buf.\n */\nlocal void putShortMSB(deflate_state *s, uInt b) {\n put_byte(s, (Byte)(b >> 8));\n put_byte(s, (Byte)(b & 0xff));\n}\n\n/* =========================================================================\n * Flush as much pending output as possible. All deflate() output, except for\n * some deflate_stored() output, goes through this function so some\n * applications may wish to modify it to avoid allocating a large\n * strm->next_out buffer and copying into it. (See also read_buf()).\n */\nlocal void flush_pending(z_streamp strm) {\n unsigned len;\n deflate_state *s = strm->state;\n\n _tr_flush_bits(s);\n len = s->pending;\n if (len > strm->avail_out) len = strm->avail_out;\n if (len == 0) return;\n\n zmemcpy(strm->next_out, s->pending_out, len);\n strm->next_out += len;\n s->pending_out += len;\n strm->total_out += len;\n strm->avail_out -= len;\n s->pending -= len;\n if (s->pending == 0) {\n s->pending_out = s->pending_buf;\n }\n}\n\n/* ===========================================================================\n * Update the header CRC with the bytes s->pending_buf[beg..s->pending - 1].\n */\n#define HCRC_UPDATE(beg) \\\n do { \\\n if (s->gzhead->hcrc && s->pending > (beg)) \\\n strm->adler = crc32(strm->adler, s->pending_buf + (beg), \\\n s->pending - (beg)); \\\n } while (0)\n\n/* ========================================================================= */\nint ZEXPORT deflate(z_streamp strm, int flush) {\n int old_flush; /* value of flush param for previous deflate call */\n deflate_state *s;\n\n if (deflateStateCheck(strm) || flush > Z_BLOCK || flush < 0) {\n return Z_STREAM_ERROR;\n }\n s = strm->state;\n\n if (strm->next_out == Z_NULL ||\n (strm->avail_in != 0 && strm->next_in == Z_NULL) ||\n (s->status == FINISH_STATE && flush != Z_FINISH)) {\n ERR_RETURN(strm, Z_STREAM_ERROR);\n }\n if (strm->avail_out == 0) ERR_RETURN(strm, Z_BUF_ERROR);\n\n old_flush = s->last_flush;\n s->last_flush = flush;\n\n /* Flush as much pending output as possible */\n if (s->pending != 0) {\n flush_pending(strm);\n if (strm->avail_out == 0) {\n /* Since avail_out is 0, deflate will be called again with\n * more output space, but possibly with both pending and\n * avail_in equal to zero. There won't be anything to do,\n * but this is not an error situation so make sure we\n * return OK instead of BUF_ERROR at next call of deflate:\n */\n s->last_flush = -1;\n return Z_OK;\n }\n\n /* Make sure there is something to do and avoid duplicate consecutive\n * flushes. For repeated and useless calls with Z_FINISH, we keep\n * returning Z_STREAM_END instead of Z_BUF_ERROR.\n */\n } else if (strm->avail_in == 0 && RANK(flush) <= RANK(old_flush) &&\n flush != Z_FINISH) {\n ERR_RETURN(strm, Z_BUF_ERROR);\n }\n\n /* User must not provide more input after the first FINISH: */\n if (s->status == FINISH_STATE && strm->avail_in != 0) {\n ERR_RETURN(strm, Z_BUF_ERROR);\n }\n\n /* Write the header */\n if (s->status == INIT_STATE && s->wrap == 0)\n s->status = BUSY_STATE;\n if (s->status == INIT_STATE) {\n /* zlib header */\n uInt header = (Z_DEFLATED + ((s->w_bits - 8) << 4)) << 8;\n uInt level_flags;\n\n if (s->strategy >= Z_HUFFMAN_ONLY || s->level < 2)\n level_flags = 0;\n else if (s->level < 6)\n level_flags = 1;\n else if (s->level == 6)\n level_flags = 2;\n else\n level_flags = 3;\n header |= (level_flags << 6);\n if (s->strstart != 0) header |= PRESET_DICT;\n header += 31 - (header % 31);\n\n putShortMSB(s, header);\n\n /* Save the adler32 of the preset dictionary: */\n if (s->strstart != 0) {\n putShortMSB(s, (uInt)(strm->adler >> 16));\n putShortMSB(s, (uInt)(strm->adler & 0xffff));\n }\n strm->adler = adler32(0L, Z_NULL, 0);\n s->status = BUSY_STATE;\n\n /* Compression must start with an empty pending buffer */\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n }\n#ifdef GZIP\n if (s->status == GZIP_STATE) {\n /* gzip header */\n strm->adler = crc32(0L, Z_NULL, 0);\n put_byte(s, 31);\n put_byte(s, 139);\n put_byte(s, 8);\n if (s->gzhead == Z_NULL) {\n put_byte(s, 0);\n put_byte(s, 0);\n put_byte(s, 0);\n put_byte(s, 0);\n put_byte(s, 0);\n put_byte(s, s->level == 9 ? 2 :\n (s->strategy >= Z_HUFFMAN_ONLY || s->level < 2 ?\n 4 : 0));\n put_byte(s, OS_CODE);\n s->status = BUSY_STATE;\n\n /* Compression must start with an empty pending buffer */\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n }\n else {\n put_byte(s, (s->gzhead->text ? 1 : 0) +\n (s->gzhead->hcrc ? 2 : 0) +\n (s->gzhead->extra == Z_NULL ? 0 : 4) +\n (s->gzhead->name == Z_NULL ? 0 : 8) +\n (s->gzhead->comment == Z_NULL ? 0 : 16)\n );\n put_byte(s, (Byte)(s->gzhead->time & 0xff));\n put_byte(s, (Byte)((s->gzhead->time >> 8) & 0xff));\n put_byte(s, (Byte)((s->gzhead->time >> 16) & 0xff));\n put_byte(s, (Byte)((s->gzhead->time >> 24) & 0xff));\n put_byte(s, s->level == 9 ? 2 :\n (s->strategy >= Z_HUFFMAN_ONLY || s->level < 2 ?\n 4 : 0));\n put_byte(s, s->gzhead->os & 0xff);\n if (s->gzhead->extra != Z_NULL) {\n put_byte(s, s->gzhead->extra_len & 0xff);\n put_byte(s, (s->gzhead->extra_len >> 8) & 0xff);\n }\n if (s->gzhead->hcrc)\n strm->adler = crc32(strm->adler, s->pending_buf,\n s->pending);\n s->gzindex = 0;\n s->status = EXTRA_STATE;\n }\n }\n if (s->status == EXTRA_STATE) {\n if (s->gzhead->extra != Z_NULL) {\n ulg beg = s->pending; /* start of bytes to update crc */\n uInt left = (s->gzhead->extra_len & 0xffff) - s->gzindex;\n while (s->pending + left > s->pending_buf_size) {\n uInt copy = s->pending_buf_size - s->pending;\n zmemcpy(s->pending_buf + s->pending,\n s->gzhead->extra + s->gzindex, copy);\n s->pending = s->pending_buf_size;\n HCRC_UPDATE(beg);\n s->gzindex += copy;\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n beg = 0;\n left -= copy;\n }\n zmemcpy(s->pending_buf + s->pending,\n s->gzhead->extra + s->gzindex, left);\n s->pending += left;\n HCRC_UPDATE(beg);\n s->gzindex = 0;\n }\n s->status = NAME_STATE;\n }\n if (s->status == NAME_STATE) {\n if (s->gzhead->name != Z_NULL) {\n ulg beg = s->pending; /* start of bytes to update crc */\n int val;\n do {\n if (s->pending == s->pending_buf_size) {\n HCRC_UPDATE(beg);\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n beg = 0;\n }\n val = s->gzhead->name[s->gzindex++];\n put_byte(s, val);\n } while (val != 0);\n HCRC_UPDATE(beg);\n s->gzindex = 0;\n }\n s->status = COMMENT_STATE;\n }\n if (s->status == COMMENT_STATE) {\n if (s->gzhead->comment != Z_NULL) {\n ulg beg = s->pending; /* start of bytes to update crc */\n int val;\n do {\n if (s->pending == s->pending_buf_size) {\n HCRC_UPDATE(beg);\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n beg = 0;\n }\n val = s->gzhead->comment[s->gzindex++];\n put_byte(s, val);\n } while (val != 0);\n HCRC_UPDATE(beg);\n }\n s->status = HCRC_STATE;\n }\n if (s->status == HCRC_STATE) {\n if (s->gzhead->hcrc) {\n if (s->pending + 2 > s->pending_buf_size) {\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n }\n put_byte(s, (Byte)(strm->adler & 0xff));\n put_byte(s, (Byte)((strm->adler >> 8) & 0xff));\n strm->adler = crc32(0L, Z_NULL, 0);\n }\n s->status = BUSY_STATE;\n\n /* Compression must start with an empty pending buffer */\n flush_pending(strm);\n if (s->pending != 0) {\n s->last_flush = -1;\n return Z_OK;\n }\n }\n#endif\n\n /* Start a new block or continue the current one.\n */\n if (strm->avail_in != 0 || s->lookahead != 0 ||\n (flush != Z_NO_FLUSH && s->status != FINISH_STATE)) {\n block_state bstate;\n\n bstate = s->level == 0 ? deflate_stored(s, flush) :\n s->strategy == Z_HUFFMAN_ONLY ? deflate_huff(s, flush) :\n s->strategy == Z_RLE ? deflate_rle(s, flush) :\n (*(configuration_table[s->level].func))(s, flush);\n\n if (bstate == finish_started || bstate == finish_done) {\n s->status = FINISH_STATE;\n }\n if (bstate == need_more || bstate == finish_started) {\n if (strm->avail_out == 0) {\n s->last_flush = -1; /* avoid BUF_ERROR next call, see above */\n }\n return Z_OK;\n /* If flush != Z_NO_FLUSH && avail_out == 0, the next call\n * of deflate should use the same flush parameter to make sure\n * that the flush is complete. So we don't have to output an\n * empty block here, this will be done at next call. This also\n * ensures that for a very small output buffer, we emit at most\n * one empty block.\n */\n }\n if (bstate == block_done) {\n if (flush == Z_PARTIAL_FLUSH) {\n _tr_align(s);\n } else if (flush != Z_BLOCK) { /* FULL_FLUSH or SYNC_FLUSH */\n _tr_stored_block(s, (char*)0, 0L, 0);\n /* For a full flush, this empty block will be recognized\n * as a special marker by inflate_sync().\n */\n if (flush == Z_FULL_FLUSH) {\n CLEAR_HASH(s); /* forget history */\n if (s->lookahead == 0) {\n s->strstart = 0;\n s->block_start = 0L;\n s->insert = 0;\n }\n }\n }\n flush_pending(strm);\n if (strm->avail_out == 0) {\n s->last_flush = -1; /* avoid BUF_ERROR at next call, see above */\n return Z_OK;\n }\n }\n }\n\n if (flush != Z_FINISH) return Z_OK;\n if (s->wrap <= 0) return Z_STREAM_END;\n\n /* Write the trailer */\n#ifdef GZIP\n if (s->wrap == 2) {\n put_byte(s, (Byte)(strm->adler & 0xff));\n put_byte(s, (Byte)((strm->adler >> 8) & 0xff));\n put_byte(s, (Byte)((strm->adler >> 16) & 0xff));\n put_byte(s, (Byte)((strm->adler >> 24) & 0xff));\n put_byte(s, (Byte)(strm->total_in & 0xff));\n put_byte(s, (Byte)((strm->total_in >> 8) & 0xff));\n put_byte(s, (Byte)((strm->total_in >> 16) & 0xff));\n put_byte(s, (Byte)((strm->total_in >> 24) & 0xff));\n }\n else\n#endif\n {\n putShortMSB(s, (uInt)(strm->adler >> 16));\n putShortMSB(s, (uInt)(strm->adler & 0xffff));\n }\n flush_pending(strm);\n /* If avail_out is zero, the application will call deflate again\n * to flush the rest.\n */\n if (s->wrap > 0) s->wrap = -s->wrap; /* write the trailer only once! */\n return s->pending != 0 ? Z_OK : Z_STREAM_END;\n}\n\n/* ========================================================================= */\nint ZEXPORT deflateEnd(z_streamp strm) {\n int status;\n\n if (deflateStateCheck(strm)) return Z_STREAM_ERROR;\n\n status = strm->state->status;\n\n /* Deallocate in reverse order of allocations: */\n TRY_FREE(strm, strm->state->pending_buf);\n TRY_FREE(strm, strm->state->head);\n TRY_FREE(strm, strm->state->prev);\n TRY_FREE(strm, strm->state->window);\n\n ZFREE(strm, strm->state);\n strm->state = Z_NULL;\n\n return status == BUSY_STATE ? Z_DATA_ERROR : Z_OK;\n}\n\n/* =========================================================================\n * Copy the source state to the destination state.\n * To simplify the source, this is not supported for 16-bit MSDOS (which\n * doesn't have enough memory anyway to duplicate compression states).\n */\nint ZEXPORT deflateCopy(z_streamp dest, z_streamp source) {\n#ifdef MAXSEG_64K\n (void)dest;\n (void)source;\n return Z_STREAM_ERROR;\n#else\n deflate_state *ds;\n deflate_state *ss;\n\n\n if (deflateStateCheck(source) || dest == Z_NULL) {\n return Z_STREAM_ERROR;\n }\n\n ss = source->state;\n\n zmemcpy((voidpf)dest, (voidpf)source, sizeof(z_stream));\n\n ds = (deflate_state *) ZALLOC(dest, 1, sizeof(deflate_state));\n if (ds == Z_NULL) return Z_MEM_ERROR;\n dest->state = (struct internal_state FAR *) ds;\n zmemcpy((voidpf)ds, (voidpf)ss, sizeof(deflate_state));\n ds->strm = dest;\n\n ds->window = (Bytef *) ZALLOC(dest, ds->w_size, 2*sizeof(Byte));\n ds->prev = (Posf *) ZALLOC(dest, ds->w_size, sizeof(Pos));\n ds->head = (Posf *) ZALLOC(dest, ds->hash_size, sizeof(Pos));\n ds->pending_buf = (uchf *) ZALLOC(dest, ds->lit_bufsize, LIT_BUFS);\n\n if (ds->window == Z_NULL || ds->prev == Z_NULL || ds->head == Z_NULL ||\n ds->pending_buf == Z_NULL) {\n deflateEnd (dest);\n return Z_MEM_ERROR;\n }\n /* following zmemcpy do not work for 16-bit MSDOS */\n zmemcpy(ds->window, ss->window, ds->w_size * 2 * sizeof(Byte));\n zmemcpy((voidpf)ds->prev, (voidpf)ss->prev, ds->w_size * sizeof(Pos));\n zmemcpy((voidpf)ds->head, (voidpf)ss->head, ds->hash_size * sizeof(Pos));\n zmemcpy(ds->pending_buf, ss->pending_buf, ds->lit_bufsize * LIT_BUFS);\n\n ds->pending_out = ds->pending_buf + (ss->pending_out - ss->pending_buf);\n#ifdef LIT_MEM\n ds->d_buf = (ushf *)(ds->pending_buf + (ds->lit_bufsize << 1));\n ds->l_buf = ds->pending_buf + (ds->lit_bufsize << 2);\n#else\n ds->sym_buf = ds->pending_buf + ds->lit_bufsize;\n#endif\n\n ds->l_desc.dyn_tree = ds->dyn_ltree;\n ds->d_desc.dyn_tree = ds->dyn_dtree;\n ds->bl_desc.dyn_tree = ds->bl_tree;\n\n return Z_OK;\n#endif /* MAXSEG_64K */\n}\n\n#ifndef FASTEST\n/* ===========================================================================\n * Set match_start to the longest match starting at the given string and\n * return its length. Matches shorter or equal to prev_length are discarded,\n * in which case the result is equal to prev_length and match_start is\n * garbage.\n * IN assertions: cur_match is the head of the hash chain for the current\n * string (strstart) and its distance is <= MAX_DIST, and prev_length >= 1\n * OUT assertion: the match length is not greater than s->lookahead.\n */\nlocal uInt longest_match(deflate_state *s, IPos cur_match) {\n unsigned chain_length = s->max_chain_length;/* max hash chain length */\n register Bytef *scan = s->window + s->strstart; /* current string */\n register Bytef *match; /* matched string */\n register int len; /* length of current match */\n int best_len = (int)s->prev_length; /* best match length so far */\n int nice_match = s->nice_match; /* stop if match long enough */\n IPos limit = s->strstart > (IPos)MAX_DIST(s) ?\n s->strstart - (IPos)MAX_DIST(s) : NIL;\n /* Stop when cur_match becomes <= limit. To simplify the code,\n * we prevent matches with the string of window index 0.\n */\n Posf *prev = s->prev;\n uInt wmask = s->w_mask;\n\n#ifdef UNALIGNED_OK\n /* Compare two bytes at a time. Note: this is not always beneficial.\n * Try with and without -DUNALIGNED_OK to check.\n */\n register Bytef *strend = s->window + s->strstart + MAX_MATCH - 1;\n register ush scan_start = *(ushf*)scan;\n register ush scan_end = *(ushf*)(scan + best_len - 1);\n#else\n register Bytef *strend = s->window + s->strstart + MAX_MATCH;\n register Byte scan_end1 = scan[best_len - 1];\n register Byte scan_end = scan[best_len];\n#endif\n\n /* The code is optimized for HASH_BITS >= 8 and MAX_MATCH-2 multiple of 16.\n * It is easy to get rid of this optimization if necessary.\n */\n Assert(s->hash_bits >= 8 && MAX_MATCH == 258, \"Code too clever\");\n\n /* Do not waste too much time if we already have a good match: */\n if (s->prev_length >= s->good_match) {\n chain_length >>= 2;\n }\n /* Do not look for matches beyond the end of the input. This is necessary\n * to make deflate deterministic.\n */\n if ((uInt)nice_match > s->lookahead) nice_match = (int)s->lookahead;\n\n Assert((ulg)s->strstart <= s->window_size - MIN_LOOKAHEAD,\n \"need lookahead\");\n\n do {\n Assert(cur_match < s->strstart, \"no future\");\n match = s->window + cur_match;\n\n /* Skip to next match if the match length cannot increase\n * or if the match length is less than 2. Note that the checks below\n * for insufficient lookahead only occur occasionally for performance\n * reasons. Therefore uninitialized memory will be accessed, and\n * conditional jumps will be made that depend on those values.\n * However the length of the match is limited to the lookahead, so\n * the output of deflate is not affected by the uninitialized values.\n */\n#if (defined(UNALIGNED_OK) && MAX_MATCH == 258)\n /* This code assumes sizeof(unsigned short) == 2. Do not use\n * UNALIGNED_OK if your compiler uses a different size.\n */\n if (*(ushf*)(match + best_len - 1) != scan_end ||\n *(ushf*)match != scan_start) continue;\n\n /* It is not necessary to compare scan[2] and match[2] since they are\n * always equal when the other bytes match, given that the hash keys\n * are equal and that HASH_BITS >= 8. Compare 2 bytes at a time at\n * strstart + 3, + 5, up to strstart + 257. We check for insufficient\n * lookahead only every 4th comparison; the 128th check will be made\n * at strstart + 257. If MAX_MATCH-2 is not a multiple of 8, it is\n * necessary to put more guard bytes at the end of the window, or\n * to check more often for insufficient lookahead.\n */\n Assert(scan[2] == match[2], \"scan[2]?\");\n scan++, match++;\n do {\n } while (*(ushf*)(scan += 2) == *(ushf*)(match += 2) &&\n *(ushf*)(scan += 2) == *(ushf*)(match += 2) &&\n *(ushf*)(scan += 2) == *(ushf*)(match += 2) &&\n *(ushf*)(scan += 2) == *(ushf*)(match += 2) &&\n scan < strend);\n /* The funny \"do {}\" generates better code on most compilers */\n\n /* Here, scan <= window + strstart + 257 */\n Assert(scan <= s->window + (unsigned)(s->window_size - 1),\n \"wild scan\");\n if (*scan == *match) scan++;\n\n len = (MAX_MATCH - 1) - (int)(strend - scan);\n scan = strend - (MAX_MATCH-1);\n\n#else /* UNALIGNED_OK */\n\n if (match[best_len] != scan_end ||\n match[best_len - 1] != scan_end1 ||\n *match != *scan ||\n *++match != scan[1]) continue;\n\n /* The check at best_len - 1 can be removed because it will be made\n * again later. (This heuristic is not always a win.)\n * It is not necessary to compare scan[2] and match[2] since they\n * are always equal when the other bytes match, given that\n * the hash keys are equal and that HASH_BITS >= 8.\n */\n scan += 2, match++;\n Assert(*scan == *match, \"match[2]?\");\n\n /* We check for insufficient lookahead only every 8th comparison;\n * the 256th check will be made at strstart + 258.\n */\n do {\n } while (*++scan == *++match && *++scan == *++match &&\n *++scan == *++match && *++scan == *++match &&\n *++scan == *++match && *++scan == *++match &&\n *++scan == *++match && *++scan == *++match &&\n scan < strend);\n\n Assert(scan <= s->window + (unsigned)(s->window_size - 1),\n \"wild scan\");\n\n len = MAX_MATCH - (int)(strend - scan);\n scan = strend - MAX_MATCH;\n\n#endif /* UNALIGNED_OK */\n\n if (len > best_len) {\n s->match_start = cur_match;\n best_len = len;\n if (len >= nice_match) break;\n#ifdef UNALIGNED_OK\n scan_end = *(ushf*)(scan + best_len - 1);\n#else\n scan_end1 = scan[best_len - 1];\n scan_end = scan[best_len];\n#endif\n }\n } while ((cur_match = prev[cur_match & wmask]) > limit\n && --chain_length != 0);\n\n if ((uInt)best_len <= s->lookahead) return (uInt)best_len;\n return s->lookahead;\n}\n\n#else /* FASTEST */\n\n/* ---------------------------------------------------------------------------\n * Optimized version for FASTEST only\n */\nlocal uInt longest_match(deflate_state *s, IPos cur_match) {\n register Bytef *scan = s->window + s->strstart; /* current string */\n register Bytef *match; /* matched string */\n register int len; /* length of current match */\n register Bytef *strend = s->window + s->strstart + MAX_MATCH;\n\n /* The code is optimized for HASH_BITS >= 8 and MAX_MATCH-2 multiple of 16.\n * It is easy to get rid of this optimization if necessary.\n */\n Assert(s->hash_bits >= 8 && MAX_MATCH == 258, \"Code too clever\");\n\n Assert((ulg)s->strstart <= s->window_size - MIN_LOOKAHEAD,\n \"need lookahead\");\n\n Assert(cur_match < s->strstart, \"no future\");\n\n match = s->window + cur_match;\n\n /* Return failure if the match length is less than 2:\n */\n if (match[0] != scan[0] || match[1] != scan[1]) return MIN_MATCH-1;\n\n /* The check at best_len - 1 can be removed because it will be made\n * again later. (This heuristic is not always a win.)\n * It is not necessary to compare scan[2] and match[2] since they\n * are always equal when the other bytes match, given that\n * the hash keys are equal and that HASH_BITS >= 8.\n */\n scan += 2, match += 2;\n Assert(*scan == *match, \"match[2]?\");\n\n /* We check for insufficient lookahead only every 8th comparison;\n * the 256th check will be made at strstart + 258.\n */\n do {\n } while (*++scan == *++match && *++scan == *++match &&\n *++scan == *++match && *++scan == *++match &&\n *++scan == *++match && *++scan == *++match &&\n *++scan == *++match && *++scan == *++match &&\n scan < strend);\n\n Assert(scan <= s->window + (unsigned)(s->window_size - 1), \"wild scan\");\n\n len = MAX_MATCH - (int)(strend - scan);\n\n if (len < MIN_MATCH) return MIN_MATCH - 1;\n\n s->match_start = cur_match;\n return (uInt)len <= s->lookahead ? (uInt)len : s->lookahead;\n}\n\n#endif /* FASTEST */\n\n#ifdef ZLIB_DEBUG\n\n#define EQUAL 0\n/* result of memcmp for equal strings */\n\n/* ===========================================================================\n * Check that the match at match_start is indeed a match.\n */\nlocal void check_match(deflate_state *s, IPos start, IPos match, int length) {\n /* check that the match is indeed a match */\n Bytef *back = s->window + (int)match, *here = s->window + start;\n IPos len = length;\n if (match == (IPos)-1) {\n /* match starts one byte before the current window -- just compare the\n subsequent length-1 bytes */\n back++;\n here++;\n len--;\n }\n if (zmemcmp(back, here, len) != EQUAL) {\n fprintf(stderr, \" start %u, match %d, length %d\\n\",\n start, (int)match, length);\n do {\n fprintf(stderr, \"(%02x %02x)\", *back++, *here++);\n } while (--len != 0);\n z_error(\"invalid match\");\n }\n if (z_verbose > 1) {\n fprintf(stderr,\"\\\\[%d,%d]\", start - match, length);\n do { putc(s->window[start++], stderr); } while (--length != 0);\n }\n}\n#else\n# define check_match(s, start, match, length)\n#endif /* ZLIB_DEBUG */\n\n/* ===========================================================================\n * Flush the current block, with given end-of-file flag.\n * IN assertion: strstart is set to the end of the current match.\n */\n#define FLUSH_BLOCK_ONLY(s, last) { \\\n _tr_flush_block(s, (s->block_start >= 0L ? \\\n (charf *)&s->window[(unsigned)s->block_start] : \\\n (charf *)Z_NULL), \\\n (ulg)((long)s->strstart - s->block_start), \\\n (last)); \\\n s->block_start = s->strstart; \\\n flush_pending(s->strm); \\\n Tracev((stderr,\"[FLUSH]\")); \\\n}\n\n/* Same but force premature exit if necessary. */\n#define FLUSH_BLOCK(s, last) { \\\n FLUSH_BLOCK_ONLY(s, last); \\\n if (s->strm->avail_out == 0) return (last) ? finish_started : need_more; \\\n}\n\n/* Maximum stored block length in deflate format (not including header). */\n#define MAX_STORED 65535\n\n/* Minimum of a and b. */\n#define MIN(a, b) ((a) > (b) ? (b) : (a))\n\n/* ===========================================================================\n * Copy without compression as much as possible from the input stream, return\n * the current block state.\n *\n * In case deflateParams() is used to later switch to a non-zero compression\n * level, s->matches (otherwise unused when storing) keeps track of the number\n * of hash table slides to perform. If s->matches is 1, then one hash table\n * slide will be done when switching. If s->matches is 2, the maximum value\n * allowed here, then the hash table will be cleared, since two or more slides\n * is the same as a clear.\n *\n * deflate_stored() is written to minimize the number of times an input byte is\n * copied. It is most efficient with large input and output buffers, which\n * maximizes the opportunities to have a single copy from next_in to next_out.\n */\nlocal block_state deflate_stored(deflate_state *s, int flush) {\n /* Smallest worthy block size when not flushing or finishing. By default\n * this is 32K. This can be as small as 507 bytes for memLevel == 1. For\n * large input and output buffers, the stored block size will be larger.\n */\n unsigned min_block = MIN(s->pending_buf_size - 5, s->w_size);\n\n /* Copy as many min_block or larger stored blocks directly to next_out as\n * possible. If flushing, copy the remaining available input to next_out as\n * stored blocks, if there is enough space.\n */\n unsigned len, left, have, last = 0;\n unsigned used = s->strm->avail_in;\n do {\n /* Set len to the maximum size block that we can copy directly with the\n * available input data and output space. Set left to how much of that\n * would be copied from what's left in the window.\n */\n len = MAX_STORED; /* maximum deflate stored block length */\n have = (s->bi_valid + 42) >> 3; /* number of header bytes */\n if (s->strm->avail_out < have) /* need room for header */\n break;\n /* maximum stored block length that will fit in avail_out: */\n have = s->strm->avail_out - have;\n left = s->strstart - s->block_start; /* bytes left in window */\n if (len > (ulg)left + s->strm->avail_in)\n len = left + s->strm->avail_in; /* limit len to the input */\n if (len > have)\n len = have; /* limit len to the output */\n\n /* If the stored block would be less than min_block in length, or if\n * unable to copy all of the available input when flushing, then try\n * copying to the window and the pending buffer instead. Also don't\n * write an empty block when flushing -- deflate() does that.\n */\n if (len < min_block && ((len == 0 && flush != Z_FINISH) ||\n flush == Z_NO_FLUSH ||\n len != left + s->strm->avail_in))\n break;\n\n /* Make a dummy stored block in pending to get the header bytes,\n * including any pending bits. This also updates the debugging counts.\n */\n last = flush == Z_FINISH && len == left + s->strm->avail_in ? 1 : 0;\n _tr_stored_block(s, (char *)0, 0L, last);\n\n /* Replace the lengths in the dummy stored block with len. */\n s->pending_buf[s->pending - 4] = len;\n s->pending_buf[s->pending - 3] = len >> 8;\n s->pending_buf[s->pending - 2] = ~len;\n s->pending_buf[s->pending - 1] = ~len >> 8;\n\n /* Write the stored block header bytes. */\n flush_pending(s->strm);\n\n#ifdef ZLIB_DEBUG\n /* Update debugging counts for the data about to be copied. */\n s->compressed_len += len << 3;\n s->bits_sent += len << 3;\n#endif\n\n /* Copy uncompressed bytes from the window to next_out. */\n if (left) {\n if (left > len)\n left = len;\n zmemcpy(s->strm->next_out, s->window + s->block_start, left);\n s->strm->next_out += left;\n s->strm->avail_out -= left;\n s->strm->total_out += left;\n s->block_start += left;\n len -= left;\n }\n\n /* Copy uncompressed bytes directly from next_in to next_out, updating\n * the check value.\n */\n if (len) {\n read_buf(s->strm, s->strm->next_out, len);\n s->strm->next_out += len;\n s->strm->avail_out -= len;\n s->strm->total_out += len;\n }\n } while (last == 0);\n\n /* Update the sliding window with the last s->w_size bytes of the copied\n * data, or append all of the copied data to the existing window if less\n * than s->w_size bytes were copied. Also update the number of bytes to\n * insert in the hash tables, in the event that deflateParams() switches to\n * a non-zero compression level.\n */\n used -= s->strm->avail_in; /* number of input bytes directly copied */\n if (used) {\n /* If any input was used, then no unused input remains in the window,\n * therefore s->block_start == s->strstart.\n */\n if (used >= s->w_size) { /* supplant the previous history */\n s->matches = 2; /* clear hash */\n zmemcpy(s->window, s->strm->next_in - s->w_size, s->w_size);\n s->strstart = s->w_size;\n s->insert = s->strstart;\n }\n else {\n if (s->window_size - s->strstart <= used) {\n /* Slide the window down. */\n s->strstart -= s->w_size;\n zmemcpy(s->window, s->window + s->w_size, s->strstart);\n if (s->matches < 2)\n s->matches++; /* add a pending slide_hash() */\n if (s->insert > s->strstart)\n s->insert = s->strstart;\n }\n zmemcpy(s->window + s->strstart, s->strm->next_in - used, used);\n s->strstart += used;\n s->insert += MIN(used, s->w_size - s->insert);\n }\n s->block_start = s->strstart;\n }\n if (s->high_water < s->strstart)\n s->high_water = s->strstart;\n\n /* If the last block was written to next_out, then done. */\n if (last)\n return finish_done;\n\n /* If flushing and all input has been consumed, then done. */\n if (flush != Z_NO_FLUSH && flush != Z_FINISH &&\n s->strm->avail_in == 0 && (long)s->strstart == s->block_start)\n return block_done;\n\n /* Fill the window with any remaining input. */\n have = s->window_size - s->strstart;\n if (s->strm->avail_in > have && s->block_start >= (long)s->w_size) {\n /* Slide the window down. */\n s->block_start -= s->w_size;\n s->strstart -= s->w_size;\n zmemcpy(s->window, s->window + s->w_size, s->strstart);\n if (s->matches < 2)\n s->matches++; /* add a pending slide_hash() */\n have += s->w_size; /* more space now */\n if (s->insert > s->strstart)\n s->insert = s->strstart;\n }\n if (have > s->strm->avail_in)\n have = s->strm->avail_in;\n if (have) {\n read_buf(s->strm, s->window + s->strstart, have);\n s->strstart += have;\n s->insert += MIN(have, s->w_size - s->insert);\n }\n if (s->high_water < s->strstart)\n s->high_water = s->strstart;\n\n /* There was not enough avail_out to write a complete worthy or flushed\n * stored block to next_out. Write a stored block to pending instead, if we\n * have enough input for a worthy block, or if flushing and there is enough\n * room for the remaining input as a stored block in the pending buffer.\n */\n have = (s->bi_valid + 42) >> 3; /* number of header bytes */\n /* maximum stored block length that will fit in pending: */\n have = MIN(s->pending_buf_size - have, MAX_STORED);\n min_block = MIN(have, s->w_size);\n left = s->strstart - s->block_start;\n if (left >= min_block ||\n ((left || flush == Z_FINISH) && flush != Z_NO_FLUSH &&\n s->strm->avail_in == 0 && left <= have)) {\n len = MIN(left, have);\n last = flush == Z_FINISH && s->strm->avail_in == 0 &&\n len == left ? 1 : 0;\n _tr_stored_block(s, (charf *)s->window + s->block_start, len, last);\n s->block_start += len;\n flush_pending(s->strm);\n }\n\n /* We've done all we can with the available input and output. */\n return last ? finish_started : need_more;\n}\n\n/* ===========================================================================\n * Compress as much as possible from the input stream, return the current\n * block state.\n * This function does not perform lazy evaluation of matches and inserts\n * new strings in the dictionary only for unmatched strings or for short\n * matches. It is used only for the fast compression options.\n */\nlocal block_state deflate_fast(deflate_state *s, int flush) {\n IPos hash_head; /* head of the hash chain */\n int bflush; /* set if current block must be flushed */\n\n for (;;) {\n /* Make sure that we always have enough lookahead, except\n * at the end of the input file. We need MAX_MATCH bytes\n * for the next match, plus MIN_MATCH bytes to insert the\n * string following the next match.\n */\n if (s->lookahead < MIN_LOOKAHEAD) {\n fill_window(s);\n if (s->lookahead < MIN_LOOKAHEAD && flush == Z_NO_FLUSH) {\n return need_more;\n }\n if (s->lookahead == 0) break; /* flush the current block */\n }\n\n /* Insert the string window[strstart .. strstart + 2] in the\n * dictionary, and set hash_head to the head of the hash chain:\n */\n hash_head = NIL;\n if (s->lookahead >= MIN_MATCH) {\n INSERT_STRING(s, s->strstart, hash_head);\n }\n\n /* Find the longest match, discarding those <= prev_length.\n * At this point we have always match_length < MIN_MATCH\n */\n if (hash_head != NIL && s->strstart - hash_head <= MAX_DIST(s)) {\n /* To simplify the code, we prevent matches with the string\n * of window index 0 (in particular we have to avoid a match\n * of the string with itself at the start of the input file).\n */\n s->match_length = longest_match (s, hash_head);\n /* longest_match() sets match_start */\n }\n if (s->match_length >= MIN_MATCH) {\n check_match(s, s->strstart, s->match_start, s->match_length);\n\n _tr_tally_dist(s, s->strstart - s->match_start,\n s->match_length - MIN_MATCH, bflush);\n\n s->lookahead -= s->match_length;\n\n /* Insert new strings in the hash table only if the match length\n * is not too large. This saves time but degrades compression.\n */\n#ifndef FASTEST\n if (s->match_length <= s->max_insert_length &&\n s->lookahead >= MIN_MATCH) {\n s->match_length--; /* string at strstart already in table */\n do {\n s->strstart++;\n INSERT_STRING(s, s->strstart, hash_head);\n /* strstart never exceeds WSIZE-MAX_MATCH, so there are\n * always MIN_MATCH bytes ahead.\n */\n } while (--s->match_length != 0);\n s->strstart++;\n } else\n#endif\n {\n s->strstart += s->match_length;\n s->match_length = 0;\n s->ins_h = s->window[s->strstart];\n UPDATE_HASH(s, s->ins_h, s->window[s->strstart + 1]);\n#if MIN_MATCH != 3\n Call UPDATE_HASH() MIN_MATCH-3 more times\n#endif\n /* If lookahead < MIN_MATCH, ins_h is garbage, but it does not\n * matter since it will be recomputed at next deflate call.\n */\n }\n } else {\n /* No match, output a literal byte */\n Tracevv((stderr,\"%c\", s->window[s->strstart]));\n _tr_tally_lit(s, s->window[s->strstart], bflush);\n s->lookahead--;\n s->strstart++;\n }\n if (bflush) FLUSH_BLOCK(s, 0);\n }\n s->insert = s->strstart < MIN_MATCH-1 ? s->strstart : MIN_MATCH-1;\n if (flush == Z_FINISH) {\n FLUSH_BLOCK(s, 1);\n return finish_done;\n }\n if (s->sym_next)\n FLUSH_BLOCK(s, 0);\n return block_done;\n}\n\n#ifndef FASTEST\n/* ===========================================================================\n * Same as above, but achieves better compression. We use a lazy\n * evaluation for matches: a match is finally adopted only if there is\n * no better match at the next window position.\n */\nlocal block_state deflate_slow(deflate_state *s, int flush) {\n IPos hash_head; /* head of hash chain */\n int bflush; /* set if current block must be flushed */\n\n /* Process the input block. */\n for (;;) {\n /* Make sure that we always have enough lookahead, except\n * at the end of the input file. We need MAX_MATCH bytes\n * for the next match, plus MIN_MATCH bytes to insert the\n * string following the next match.\n */\n if (s->lookahead < MIN_LOOKAHEAD) {\n fill_window(s);\n if (s->lookahead < MIN_LOOKAHEAD && flush == Z_NO_FLUSH) {\n return need_more;\n }\n if (s->lookahead == 0) break; /* flush the current block */\n }\n\n /* Insert the string window[strstart .. strstart + 2] in the\n * dictionary, and set hash_head to the head of the hash chain:\n */\n hash_head = NIL;\n if (s->lookahead >= MIN_MATCH) {\n INSERT_STRING(s, s->strstart, hash_head);\n }\n\n /* Find the longest match, discarding those <= prev_length.\n */\n s->prev_length = s->match_length, s->prev_match = s->match_start;\n s->match_length = MIN_MATCH-1;\n\n if (hash_head != NIL && s->prev_length < s->max_lazy_match &&\n s->strstart - hash_head <= MAX_DIST(s)) {\n /* To simplify the code, we prevent matches with the string\n * of window index 0 (in particular we have to avoid a match\n * of the string with itself at the start of the input file).\n */\n s->match_length = longest_match (s, hash_head);\n /* longest_match() sets match_start */\n\n if (s->match_length <= 5 && (s->strategy == Z_FILTERED\n#if TOO_FAR <= 32767\n || (s->match_length == MIN_MATCH &&\n s->strstart - s->match_start > TOO_FAR)\n#endif\n )) {\n\n /* If prev_match is also MIN_MATCH, match_start is garbage\n * but we will ignore the current match anyway.\n */\n s->match_length = MIN_MATCH-1;\n }\n }\n /* If there was a match at the previous step and the current\n * match is not better, output the previous match:\n */\n if (s->prev_length >= MIN_MATCH && s->match_length <= s->prev_length) {\n uInt max_insert = s->strstart + s->lookahead - MIN_MATCH;\n /* Do not insert strings in hash table beyond this. */\n\n check_match(s, s->strstart - 1, s->prev_match, s->prev_length);\n\n _tr_tally_dist(s, s->strstart - 1 - s->prev_match,\n s->prev_length - MIN_MATCH, bflush);\n\n /* Insert in hash table all strings up to the end of the match.\n * strstart - 1 and strstart are already inserted. If there is not\n * enough lookahead, the last two strings are not inserted in\n * the hash table.\n */\n s->lookahead -= s->prev_length - 1;\n s->prev_length -= 2;\n do {\n if (++s->strstart <= max_insert) {\n INSERT_STRING(s, s->strstart, hash_head);\n }\n } while (--s->prev_length != 0);\n s->match_available = 0;\n s->match_length = MIN_MATCH-1;\n s->strstart++;\n\n if (bflush) FLUSH_BLOCK(s, 0);\n\n } else if (s->match_available) {\n /* If there was no match at the previous position, output a\n * single literal. If there was a match but the current match\n * is longer, truncate the previous match to a single literal.\n */\n Tracevv((stderr,\"%c\", s->window[s->strstart - 1]));\n _tr_tally_lit(s, s->window[s->strstart - 1], bflush);\n if (bflush) {\n FLUSH_BLOCK_ONLY(s, 0);\n }\n s->strstart++;\n s->lookahead--;\n if (s->strm->avail_out == 0) return need_more;\n } else {\n /* There is no previous match to compare with, wait for\n * the next step to decide.\n */\n s->match_available = 1;\n s->strstart++;\n s->lookahead--;\n }\n }\n Assert (flush != Z_NO_FLUSH, \"no flush?\");\n if (s->match_available) {\n Tracevv((stderr,\"%c\", s->window[s->strstart - 1]));\n _tr_tally_lit(s, s->window[s->strstart - 1], bflush);\n s->match_available = 0;\n }\n s->insert = s->strstart < MIN_MATCH-1 ? s->strstart : MIN_MATCH-1;\n if (flush == Z_FINISH) {\n FLUSH_BLOCK(s, 1);\n return finish_done;\n }\n if (s->sym_next)\n FLUSH_BLOCK(s, 0);\n return block_done;\n}\n#endif /* FASTEST */\n\n/* ===========================================================================\n * For Z_RLE, simply look for runs of bytes, generate matches only of distance\n * one. Do not maintain a hash table. (It will be regenerated if this run of\n * deflate switches away from Z_RLE.)\n */\nlocal block_state deflate_rle(deflate_state *s, int flush) {\n int bflush; /* set if current block must be flushed */\n uInt prev; /* byte at distance one to match */\n Bytef *scan, *strend; /* scan goes up to strend for length of run */\n\n for (;;) {\n /* Make sure that we always have enough lookahead, except\n * at the end of the input file. We need MAX_MATCH bytes\n * for the longest run, plus one for the unrolled loop.\n */\n if (s->lookahead <= MAX_MATCH) {\n fill_window(s);\n if (s->lookahead <= MAX_MATCH && flush == Z_NO_FLUSH) {\n return need_more;\n }\n if (s->lookahead == 0) break; /* flush the current block */\n }\n\n /* See how many times the previous byte repeats */\n s->match_length = 0;\n if (s->lookahead >= MIN_MATCH && s->strstart > 0) {\n scan = s->window + s->strstart - 1;\n prev = *scan;\n if (prev == *++scan && prev == *++scan && prev == *++scan) {\n strend = s->window + s->strstart + MAX_MATCH;\n do {\n } while (prev == *++scan && prev == *++scan &&\n prev == *++scan && prev == *++scan &&\n prev == *++scan && prev == *++scan &&\n prev == *++scan && prev == *++scan &&\n scan < strend);\n s->match_length = MAX_MATCH - (uInt)(strend - scan);\n if (s->match_length > s->lookahead)\n s->match_length = s->lookahead;\n }\n Assert(scan <= s->window + (uInt)(s->window_size - 1),\n \"wild scan\");\n }\n\n /* Emit match if have run of MIN_MATCH or longer, else emit literal */\n if (s->match_length >= MIN_MATCH) {\n check_match(s, s->strstart, s->strstart - 1, s->match_length);\n\n _tr_tally_dist(s, 1, s->match_length - MIN_MATCH, bflush);\n\n s->lookahead -= s->match_length;\n s->strstart += s->match_length;\n s->match_length = 0;\n } else {\n /* No match, output a literal byte */\n Tracevv((stderr,\"%c\", s->window[s->strstart]));\n _tr_tally_lit(s, s->window[s->strstart], bflush);\n s->lookahead--;\n s->strstart++;\n }\n if (bflush) FLUSH_BLOCK(s, 0);\n }\n s->insert = 0;\n if (flush == Z_FINISH) {\n FLUSH_BLOCK(s, 1);\n return finish_done;\n }\n if (s->sym_next)\n FLUSH_BLOCK(s, 0);\n return block_done;\n}\n\n/* ===========================================================================\n * For Z_HUFFMAN_ONLY, do not look for matches. Do not maintain a hash table.\n * (It will be regenerated if this run of deflate switches away from Huffman.)\n */\nlocal block_state deflate_huff(deflate_state *s, int flush) {\n int bflush; /* set if current block must be flushed */\n\n for (;;) {\n /* Make sure that we have a literal to write. */\n if (s->lookahead == 0) {\n fill_window(s);\n if (s->lookahead == 0) {\n if (flush == Z_NO_FLUSH)\n return need_more;\n break; /* flush the current block */\n }\n }\n\n /* Output a literal byte */\n s->match_length = 0;\n Tracevv((stderr,\"%c\", s->window[s->strstart]));\n _tr_tally_lit(s, s->window[s->strstart], bflush);\n s->lookahead--;\n s->strstart++;\n if (bflush) FLUSH_BLOCK(s, 0);\n }\n s->insert = 0;\n if (flush == Z_FINISH) {\n FLUSH_BLOCK(s, 1);\n return finish_done;\n }\n if (s->sym_next)\n FLUSH_BLOCK(s, 0);\n return block_done;\n}\n" }, { "path": "pypcode/zlib/deflate.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* deflate.h -- internal compression state\n * Copyright (C) 1995-2024 Jean-loup Gailly\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* WARNING: this file should *not* be used by applications. It is\n part of the implementation of the compression library and is\n subject to change. Applications should only use zlib.h.\n */\n\n/* @(#) $Id$ */\n\n#ifndef DEFLATE_H\n#define DEFLATE_H\n\n#include \"zutil.h\"\n\n/* define NO_GZIP when compiling if you want to disable gzip header and\n trailer creation by deflate(). NO_GZIP would be used to avoid linking in\n the crc code when it is not needed. For shared libraries, gzip encoding\n should be left enabled. */\n#ifndef NO_GZIP\n# define GZIP\n#endif\n\n/* define LIT_MEM to slightly increase the speed of deflate (order 1% to 2%) at\n the cost of a larger memory footprint */\n/* #define LIT_MEM */\n\n/* ===========================================================================\n * Internal compression state.\n */\n\n#define LENGTH_CODES 29\n/* number of length codes, not counting the special END_BLOCK code */\n\n#define LITERALS 256\n/* number of literal bytes 0..255 */\n\n#define L_CODES (LITERALS+1+LENGTH_CODES)\n/* number of Literal or Length codes, including the END_BLOCK code */\n\n#define D_CODES 30\n/* number of distance codes */\n\n#define BL_CODES 19\n/* number of codes used to transfer the bit lengths */\n\n#define HEAP_SIZE (2*L_CODES+1)\n/* maximum heap size */\n\n#define MAX_BITS 15\n/* All codes must not exceed MAX_BITS bits */\n\n#define Buf_size 16\n/* size of bit buffer in bi_buf */\n\n#define INIT_STATE 42 /* zlib header -> BUSY_STATE */\n#ifdef GZIP\n# define GZIP_STATE 57 /* gzip header -> BUSY_STATE | EXTRA_STATE */\n#endif\n#define EXTRA_STATE 69 /* gzip extra block -> NAME_STATE */\n#define NAME_STATE 73 /* gzip file name -> COMMENT_STATE */\n#define COMMENT_STATE 91 /* gzip comment -> HCRC_STATE */\n#define HCRC_STATE 103 /* gzip header CRC -> BUSY_STATE */\n#define BUSY_STATE 113 /* deflate -> FINISH_STATE */\n#define FINISH_STATE 666 /* stream complete */\n/* Stream status */\n\n\n/* Data structure describing a single value and its code string. */\ntypedef struct ct_data_s {\n union {\n ush freq; /* frequency count */\n ush code; /* bit string */\n } fc;\n union {\n ush dad; /* father node in Huffman tree */\n ush len; /* length of bit string */\n } dl;\n} FAR ct_data;\n\n#define Freq fc.freq\n#define Code fc.code\n#define Dad dl.dad\n#define Len dl.len\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\ntypedef struct tree_desc_s {\n ct_data *dyn_tree; /* the dynamic tree */\n int max_code; /* largest code with non zero frequency */\n const static_tree_desc *stat_desc; /* the corresponding static tree */\n} FAR tree_desc;\n\ntypedef ush Pos;\ntypedef Pos FAR Posf;\ntypedef unsigned IPos;\n\n/* A Pos is an index in the character window. We use short instead of int to\n * save space in the various tables. IPos is used only for parameter passing.\n */\n\ntypedef struct internal_state {\n z_streamp strm; /* pointer back to this zlib stream */\n int status; /* as the name implies */\n Bytef *pending_buf; /* output still pending */\n ulg pending_buf_size; /* size of pending_buf */\n Bytef *pending_out; /* next pending byte to output to the stream */\n ulg pending; /* nb of bytes in the pending buffer */\n int wrap; /* bit 0 true for zlib, bit 1 true for gzip */\n gz_headerp gzhead; /* gzip header information to write */\n ulg gzindex; /* where in extra, name, or comment */\n Byte method; /* can only be DEFLATED */\n int last_flush; /* value of flush param for previous deflate call */\n\n /* used by deflate.c: */\n\n uInt w_size; /* LZ77 window size (32K by default) */\n uInt w_bits; /* log2(w_size) (8..16) */\n uInt w_mask; /* w_size - 1 */\n\n Bytef *window;\n /* Sliding window. Input bytes are read into the second half of the window,\n * and move to the first half later to keep a dictionary of at least wSize\n * bytes. With this organization, matches are limited to a distance of\n * wSize-MAX_MATCH bytes, but this ensures that IO is always\n * performed with a length multiple of the block size. Also, it limits\n * the window size to 64K, which is quite useful on MSDOS.\n * To do: use the user input buffer as sliding window.\n */\n\n ulg window_size;\n /* Actual size of window: 2*wSize, except when the user input buffer\n * is directly used as sliding window.\n */\n\n Posf *prev;\n /* Link to older string with same hash index. To limit the size of this\n * array to 64K, this link is maintained only for the last 32K strings.\n * An index in this array is thus a window index modulo 32K.\n */\n\n Posf *head; /* Heads of the hash chains or NIL. */\n\n uInt ins_h; /* hash index of string to be inserted */\n uInt hash_size; /* number of elements in hash table */\n uInt hash_bits; /* log2(hash_size) */\n uInt hash_mask; /* hash_size-1 */\n\n uInt hash_shift;\n /* Number of bits by which ins_h must be shifted at each input\n * step. It must be such that after MIN_MATCH steps, the oldest\n * byte no longer takes part in the hash key, that is:\n * hash_shift * MIN_MATCH >= hash_bits\n */\n\n long block_start;\n /* Window position at the beginning of the current output block. Gets\n * negative when the window is moved backwards.\n */\n\n uInt match_length; /* length of best match */\n IPos prev_match; /* previous match */\n int match_available; /* set if previous match exists */\n uInt strstart; /* start of string to insert */\n uInt match_start; /* start of matching string */\n uInt lookahead; /* number of valid bytes ahead in window */\n\n uInt prev_length;\n /* Length of the best match at previous step. Matches not greater than this\n * are discarded. This is used in the lazy match evaluation.\n */\n\n uInt max_chain_length;\n /* To speed up deflation, hash chains are never searched beyond this\n * length. A higher limit improves compression ratio but degrades the\n * speed.\n */\n\n uInt max_lazy_match;\n /* Attempt to find a better match only when the current match is strictly\n * smaller than this value. This mechanism is used only for compression\n * levels >= 4.\n */\n# define max_insert_length max_lazy_match\n /* Insert new strings in the hash table only if the match length is not\n * greater than this length. This saves time but degrades compression.\n * max_insert_length is used only for compression levels <= 3.\n */\n\n int level; /* compression level (1..9) */\n int strategy; /* favor or force Huffman coding*/\n\n uInt good_match;\n /* Use a faster search when the previous match is longer than this */\n\n int nice_match; /* Stop searching when current match exceeds this */\n\n /* used by trees.c: */\n /* Didn't use ct_data typedef below to suppress compiler warning */\n struct ct_data_s dyn_ltree[HEAP_SIZE]; /* literal and length tree */\n struct ct_data_s dyn_dtree[2*D_CODES+1]; /* distance tree */\n struct ct_data_s bl_tree[2*BL_CODES+1]; /* Huffman tree for bit lengths */\n\n struct tree_desc_s l_desc; /* desc. for literal tree */\n struct tree_desc_s d_desc; /* desc. for distance tree */\n struct tree_desc_s bl_desc; /* desc. for bit length tree */\n\n ush bl_count[MAX_BITS+1];\n /* number of codes at each bit length for an optimal tree */\n\n int heap[2*L_CODES+1]; /* heap used to build the Huffman trees */\n int heap_len; /* number of elements in the heap */\n int heap_max; /* element of largest frequency */\n /* The sons of heap[n] are heap[2*n] and heap[2*n+1]. heap[0] is not used.\n * The same heap array is used to build all trees.\n */\n\n uch depth[2*L_CODES+1];\n /* Depth of each subtree used as tie breaker for trees of equal frequency\n */\n\n#ifdef LIT_MEM\n# define LIT_BUFS 5\n ushf *d_buf; /* buffer for distances */\n uchf *l_buf; /* buffer for literals/lengths */\n#else\n# define LIT_BUFS 4\n uchf *sym_buf; /* buffer for distances and literals/lengths */\n#endif\n\n uInt lit_bufsize;\n /* Size of match buffer for literals/lengths. There are 4 reasons for\n * limiting lit_bufsize to 64K:\n * - frequencies can be kept in 16 bit counters\n * - if compression is not successful for the first block, all input\n * data is still in the window so we can still emit a stored block even\n * when input comes from standard input. (This can also be done for\n * all blocks if lit_bufsize is not greater than 32K.)\n * - if compression is not successful for a file smaller than 64K, we can\n * even emit a stored file instead of a stored block (saving 5 bytes).\n * This is applicable only for zip (not gzip or zlib).\n * - creating new Huffman trees less frequently may not provide fast\n * adaptation to changes in the input data statistics. (Take for\n * example a binary file with poorly compressible code followed by\n * a highly compressible string table.) Smaller buffer sizes give\n * fast adaptation but have of course the overhead of transmitting\n * trees more frequently.\n * - I can't count above 4\n */\n\n uInt sym_next; /* running index in symbol buffer */\n uInt sym_end; /* symbol table full when sym_next reaches this */\n\n ulg opt_len; /* bit length of current block with optimal trees */\n ulg static_len; /* bit length of current block with static trees */\n uInt matches; /* number of string matches in current block */\n uInt insert; /* bytes at end of window left to insert */\n\n#ifdef ZLIB_DEBUG\n ulg compressed_len; /* total bit length of compressed file mod 2^32 */\n ulg bits_sent; /* bit length of compressed data sent mod 2^32 */\n#endif\n\n ush bi_buf;\n /* Output buffer. bits are inserted starting at the bottom (least\n * significant bits).\n */\n int bi_valid;\n /* Number of valid bits in bi_buf. All bits above the last valid bit\n * are always zero.\n */\n\n ulg high_water;\n /* High water mark offset in window for initialized bytes -- bytes above\n * this are set to zero in order to avoid memory check warnings when\n * longest match routines access bytes past the input. This is then\n * updated to the new high water mark.\n */\n\n} FAR deflate_state;\n\n/* Output a byte on the stream.\n * IN assertion: there is enough room in pending_buf.\n */\n#define put_byte(s, c) {s->pending_buf[s->pending++] = (Bytef)(c);}\n\n\n#define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1)\n/* Minimum amount of lookahead, except at the end of the input file.\n * See deflate.c for comments about the MIN_MATCH+1.\n */\n\n#define MAX_DIST(s) ((s)->w_size-MIN_LOOKAHEAD)\n/* In order to simplify the code, particularly on 16 bit machines, match\n * distances are limited to MAX_DIST instead of WSIZE.\n */\n\n#define WIN_INIT MAX_MATCH\n/* Number of bytes after end of data in window to initialize in order to avoid\n memory checker errors from longest match routines */\n\n /* in trees.c */\nvoid ZLIB_INTERNAL _tr_init(deflate_state *s);\nint ZLIB_INTERNAL _tr_tally(deflate_state *s, unsigned dist, unsigned lc);\nvoid ZLIB_INTERNAL _tr_flush_block(deflate_state *s, charf *buf,\n ulg stored_len, int last);\nvoid ZLIB_INTERNAL _tr_flush_bits(deflate_state *s);\nvoid ZLIB_INTERNAL _tr_align(deflate_state *s);\nvoid ZLIB_INTERNAL _tr_stored_block(deflate_state *s, charf *buf,\n ulg stored_len, int last);\n\n#define d_code(dist) \\\n ((dist) < 256 ? _dist_code[dist] : _dist_code[256+((dist)>>7)])\n/* Mapping from a distance to a distance code. dist is the distance - 1 and\n * must not have side effects. _dist_code[256] and _dist_code[257] are never\n * used.\n */\n\n#ifndef ZLIB_DEBUG\n/* Inline versions of _tr_tally for speed: */\n\n#if defined(GEN_TREES_H) || !defined(STDC)\n extern uch ZLIB_INTERNAL _length_code[];\n extern uch ZLIB_INTERNAL _dist_code[];\n#else\n extern const uch ZLIB_INTERNAL _length_code[];\n extern const uch ZLIB_INTERNAL _dist_code[];\n#endif\n\n#ifdef LIT_MEM\n# define _tr_tally_lit(s, c, flush) \\\n { uch cc = (c); \\\n s->d_buf[s->sym_next] = 0; \\\n s->l_buf[s->sym_next++] = cc; \\\n s->dyn_ltree[cc].Freq++; \\\n flush = (s->sym_next == s->sym_end); \\\n }\n# define _tr_tally_dist(s, distance, length, flush) \\\n { uch len = (uch)(length); \\\n ush dist = (ush)(distance); \\\n s->d_buf[s->sym_next] = dist; \\\n s->l_buf[s->sym_next++] = len; \\\n dist--; \\\n s->dyn_ltree[_length_code[len]+LITERALS+1].Freq++; \\\n s->dyn_dtree[d_code(dist)].Freq++; \\\n flush = (s->sym_next == s->sym_end); \\\n }\n#else\n# define _tr_tally_lit(s, c, flush) \\\n { uch cc = (c); \\\n s->sym_buf[s->sym_next++] = 0; \\\n s->sym_buf[s->sym_next++] = 0; \\\n s->sym_buf[s->sym_next++] = cc; \\\n s->dyn_ltree[cc].Freq++; \\\n flush = (s->sym_next == s->sym_end); \\\n }\n# define _tr_tally_dist(s, distance, length, flush) \\\n { uch len = (uch)(length); \\\n ush dist = (ush)(distance); \\\n s->sym_buf[s->sym_next++] = (uch)dist; \\\n s->sym_buf[s->sym_next++] = (uch)(dist >> 8); \\\n s->sym_buf[s->sym_next++] = len; \\\n dist--; \\\n s->dyn_ltree[_length_code[len]+LITERALS+1].Freq++; \\\n s->dyn_dtree[d_code(dist)].Freq++; \\\n flush = (s->sym_next == s->sym_end); \\\n }\n#endif\n#else\n# define _tr_tally_lit(s, c, flush) flush = _tr_tally(s, 0, c)\n# define _tr_tally_dist(s, distance, length, flush) \\\n flush = _tr_tally(s, distance, length)\n#endif\n\n#endif /* DEFLATE_H */\n" }, { "path": "pypcode/zlib/gzguts.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* gzguts.h -- zlib internal header definitions for gz* operations\n * Copyright (C) 2004-2024 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n#ifdef _LARGEFILE64_SOURCE\n# ifndef _LARGEFILE_SOURCE\n# define _LARGEFILE_SOURCE 1\n# endif\n# undef _FILE_OFFSET_BITS\n# undef _TIME_BITS\n#endif\n\n#ifdef HAVE_HIDDEN\n# define ZLIB_INTERNAL __attribute__((visibility (\"hidden\")))\n#else\n# define ZLIB_INTERNAL\n#endif\n\n#include \n#include \"zlib.h\"\n#ifdef STDC\n# include \n# include \n# include \n#endif\n\n#ifndef _POSIX_SOURCE\n# define _POSIX_SOURCE\n#endif\n#include \n\n#ifdef _WIN32\n# include \n#endif\n\n#if defined(__TURBOC__) || defined(_MSC_VER) || defined(_WIN32)\n# include \n#endif\n\n#if defined(_WIN32)\n# define WIDECHAR\n#endif\n\n#ifdef WINAPI_FAMILY\n# define open _open\n# define read _read\n# define write _write\n# define close _close\n#endif\n\n#ifdef NO_DEFLATE /* for compatibility with old definition */\n# define NO_GZCOMPRESS\n#endif\n\n#if defined(STDC99) || (defined(__TURBOC__) && __TURBOC__ >= 0x550)\n# ifndef HAVE_VSNPRINTF\n# define HAVE_VSNPRINTF\n# endif\n#endif\n\n#if defined(__CYGWIN__)\n# ifndef HAVE_VSNPRINTF\n# define HAVE_VSNPRINTF\n# endif\n#endif\n\n#if defined(MSDOS) && defined(__BORLANDC__) && (BORLANDC > 0x410)\n# ifndef HAVE_VSNPRINTF\n# define HAVE_VSNPRINTF\n# endif\n#endif\n\n#ifndef HAVE_VSNPRINTF\n# ifdef MSDOS\n/* vsnprintf may exist on some MS-DOS compilers (DJGPP?),\n but for now we just assume it doesn't. */\n# define NO_vsnprintf\n# endif\n# ifdef __TURBOC__\n# define NO_vsnprintf\n# endif\n# ifdef WIN32\n/* In Win32, vsnprintf is available as the \"non-ANSI\" _vsnprintf. */\n# if !defined(vsnprintf) && !defined(NO_vsnprintf)\n# if !defined(_MSC_VER) || ( defined(_MSC_VER) && _MSC_VER < 1500 )\n# define vsnprintf _vsnprintf\n# endif\n# endif\n# endif\n# ifdef __SASC\n# define NO_vsnprintf\n# endif\n# ifdef VMS\n# define NO_vsnprintf\n# endif\n# ifdef __OS400__\n# define NO_vsnprintf\n# endif\n# ifdef __MVS__\n# define NO_vsnprintf\n# endif\n#endif\n\n/* unlike snprintf (which is required in C99), _snprintf does not guarantee\n null termination of the result -- however this is only used in gzlib.c where\n the result is assured to fit in the space provided */\n#if defined(_MSC_VER) && _MSC_VER < 1900\n# define snprintf _snprintf\n#endif\n\n#ifndef local\n# define local static\n#endif\n/* since \"static\" is used to mean two completely different things in C, we\n define \"local\" for the non-static meaning of \"static\", for readability\n (compile with -Dlocal if your debugger can't find static symbols) */\n\n/* gz* functions always use library allocation functions */\n#ifndef STDC\n extern voidp malloc(uInt size);\n extern void free(voidpf ptr);\n#endif\n\n/* get errno and strerror definition */\n#if defined UNDER_CE\n# include \n# define zstrerror() gz_strwinerror((DWORD)GetLastError())\n#else\n# ifndef NO_STRERROR\n# include \n# define zstrerror() strerror(errno)\n# else\n# define zstrerror() \"stdio error (consult errno)\"\n# endif\n#endif\n\n/* provide prototypes for these when building zlib without LFS */\n#if !defined(_LARGEFILE64_SOURCE) || _LFS64_LARGEFILE-0 == 0\n ZEXTERN gzFile ZEXPORT gzopen64(const char *, const char *);\n ZEXTERN z_off64_t ZEXPORT gzseek64(gzFile, z_off64_t, int);\n ZEXTERN z_off64_t ZEXPORT gztell64(gzFile);\n ZEXTERN z_off64_t ZEXPORT gzoffset64(gzFile);\n#endif\n\n/* default memLevel */\n#if MAX_MEM_LEVEL >= 8\n# define DEF_MEM_LEVEL 8\n#else\n# define DEF_MEM_LEVEL MAX_MEM_LEVEL\n#endif\n\n/* default i/o buffer size -- double this for output when reading (this and\n twice this must be able to fit in an unsigned type) */\n#define GZBUFSIZE 8192\n\n/* gzip modes, also provide a little integrity check on the passed structure */\n#define GZ_NONE 0\n#define GZ_READ 7247\n#define GZ_WRITE 31153\n#define GZ_APPEND 1 /* mode set to GZ_WRITE after the file is opened */\n\n/* values for gz_state how */\n#define LOOK 0 /* look for a gzip header */\n#define COPY 1 /* copy input directly */\n#define GZIP 2 /* decompress a gzip stream */\n\n/* internal gzip file state data structure */\ntypedef struct {\n /* exposed contents for gzgetc() macro */\n struct gzFile_s x; /* \"x\" for exposed */\n /* x.have: number of bytes available at x.next */\n /* x.next: next output data to deliver or write */\n /* x.pos: current position in uncompressed data */\n /* used for both reading and writing */\n int mode; /* see gzip modes above */\n int fd; /* file descriptor */\n char *path; /* path or fd for error messages */\n unsigned size; /* buffer size, zero if not allocated yet */\n unsigned want; /* requested buffer size, default is GZBUFSIZE */\n unsigned char *in; /* input buffer (double-sized when writing) */\n unsigned char *out; /* output buffer (double-sized when reading) */\n int direct; /* 0 if processing gzip, 1 if transparent */\n /* just for reading */\n int how; /* 0: get header, 1: copy, 2: decompress */\n z_off64_t start; /* where the gzip data started, for rewinding */\n int eof; /* true if end of input file reached */\n int past; /* true if read requested past end */\n /* just for writing */\n int level; /* compression level */\n int strategy; /* compression strategy */\n int reset; /* true if a reset is pending after a Z_FINISH */\n /* seek request */\n z_off64_t skip; /* amount to skip (already rewound if backwards) */\n int seek; /* true if seek request pending */\n /* error information */\n int err; /* error code */\n char *msg; /* error message */\n /* zlib inflate or deflate stream */\n z_stream strm; /* stream structure in-place (not a pointer) */\n} gz_state;\ntypedef gz_state FAR *gz_statep;\n\n/* shared functions */\nvoid ZLIB_INTERNAL gz_error(gz_statep, int, const char *);\n#if defined UNDER_CE\nchar ZLIB_INTERNAL *gz_strwinerror(DWORD error);\n#endif\n\n/* GT_OFF(x), where x is an unsigned value, is true if x > maximum z_off64_t\n value -- needed when comparing unsigned to z_off64_t, which is signed\n (possible z_off64_t types off_t, off64_t, and long are all signed) */\nunsigned ZLIB_INTERNAL gz_intmax(void);\n#define GT_OFF(x) (sizeof(int) == sizeof(z_off64_t) && (x) > gz_intmax())\n" }, { "path": "pypcode/zlib/inffast.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* inffast.c -- fast decoding\n * Copyright (C) 1995-2017 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n#include \"zutil.h\"\n#include \"inftrees.h\"\n#include \"inflate.h\"\n#include \"inffast.h\"\n\n#ifdef ASMINF\n# pragma message(\"Assembler code may have bugs -- use at your own risk\")\n#else\n\n/*\n Decode literal, length, and distance codes and write out the resulting\n literal and match bytes until either not enough input or output is\n available, an end-of-block is encountered, or a data error is encountered.\n When large enough input and output buffers are supplied to inflate(), for\n example, a 16K input buffer and a 64K output buffer, more than 95% of the\n inflate execution time is spent in this routine.\n\n Entry assumptions:\n\n state->mode == LEN\n strm->avail_in >= 6\n strm->avail_out >= 258\n start >= strm->avail_out\n state->bits < 8\n\n On return, state->mode is one of:\n\n LEN -- ran out of enough output space or enough available input\n TYPE -- reached end of block code, inflate() to interpret next block\n BAD -- error in block data\n\n Notes:\n\n - The maximum input bits used by a length/distance pair is 15 bits for the\n length code, 5 bits for the length extra, 15 bits for the distance code,\n and 13 bits for the distance extra. This totals 48 bits, or six bytes.\n Therefore if strm->avail_in >= 6, then there is enough input to avoid\n checking for available input while decoding.\n\n - The maximum bytes that a single length/distance pair can output is 258\n bytes, which is the maximum length that can be coded. inflate_fast()\n requires strm->avail_out >= 258 for each loop to avoid checking for\n output space.\n */\nvoid ZLIB_INTERNAL inflate_fast(z_streamp strm, unsigned start) {\n struct inflate_state FAR *state;\n z_const unsigned char FAR *in; /* local strm->next_in */\n z_const unsigned char FAR *last; /* have enough input while in < last */\n unsigned char FAR *out; /* local strm->next_out */\n unsigned char FAR *beg; /* inflate()'s initial strm->next_out */\n unsigned char FAR *end; /* while out < end, enough space available */\n#ifdef INFLATE_STRICT\n unsigned dmax; /* maximum distance from zlib header */\n#endif\n unsigned wsize; /* window size or zero if not using window */\n unsigned whave; /* valid bytes in the window */\n unsigned wnext; /* window write index */\n unsigned char FAR *window; /* allocated sliding window, if wsize != 0 */\n unsigned long hold; /* local strm->hold */\n unsigned bits; /* local strm->bits */\n code const FAR *lcode; /* local strm->lencode */\n code const FAR *dcode; /* local strm->distcode */\n unsigned lmask; /* mask for first level of length codes */\n unsigned dmask; /* mask for first level of distance codes */\n code const *here; /* retrieved table entry */\n unsigned op; /* code bits, operation, extra bits, or */\n /* window position, window bytes to copy */\n unsigned len; /* match length, unused bytes */\n unsigned dist; /* match distance */\n unsigned char FAR *from; /* where to copy match from */\n\n /* copy state to local variables */\n state = (struct inflate_state FAR *)strm->state;\n in = strm->next_in;\n last = in + (strm->avail_in - 5);\n out = strm->next_out;\n beg = out - (start - strm->avail_out);\n end = out + (strm->avail_out - 257);\n#ifdef INFLATE_STRICT\n dmax = state->dmax;\n#endif\n wsize = state->wsize;\n whave = state->whave;\n wnext = state->wnext;\n window = state->window;\n hold = state->hold;\n bits = state->bits;\n lcode = state->lencode;\n dcode = state->distcode;\n lmask = (1U << state->lenbits) - 1;\n dmask = (1U << state->distbits) - 1;\n\n /* decode literals and length/distances until end-of-block or not enough\n input data or output space */\n do {\n if (bits < 15) {\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n }\n here = lcode + (hold & lmask);\n dolen:\n op = (unsigned)(here->bits);\n hold >>= op;\n bits -= op;\n op = (unsigned)(here->op);\n if (op == 0) { /* literal */\n Tracevv((stderr, here->val >= 0x20 && here->val < 0x7f ?\n \"inflate: literal '%c'\\n\" :\n \"inflate: literal 0x%02x\\n\", here->val));\n *out++ = (unsigned char)(here->val);\n }\n else if (op & 16) { /* length base */\n len = (unsigned)(here->val);\n op &= 15; /* number of extra bits */\n if (op) {\n if (bits < op) {\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n }\n len += (unsigned)hold & ((1U << op) - 1);\n hold >>= op;\n bits -= op;\n }\n Tracevv((stderr, \"inflate: length %u\\n\", len));\n if (bits < 15) {\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n }\n here = dcode + (hold & dmask);\n dodist:\n op = (unsigned)(here->bits);\n hold >>= op;\n bits -= op;\n op = (unsigned)(here->op);\n if (op & 16) { /* distance base */\n dist = (unsigned)(here->val);\n op &= 15; /* number of extra bits */\n if (bits < op) {\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n if (bits < op) {\n hold += (unsigned long)(*in++) << bits;\n bits += 8;\n }\n }\n dist += (unsigned)hold & ((1U << op) - 1);\n#ifdef INFLATE_STRICT\n if (dist > dmax) {\n strm->msg = (char *)\"invalid distance too far back\";\n state->mode = BAD;\n break;\n }\n#endif\n hold >>= op;\n bits -= op;\n Tracevv((stderr, \"inflate: distance %u\\n\", dist));\n op = (unsigned)(out - beg); /* max distance in output */\n if (dist > op) { /* see if copy from window */\n op = dist - op; /* distance back in window */\n if (op > whave) {\n if (state->sane) {\n strm->msg =\n (char *)\"invalid distance too far back\";\n state->mode = BAD;\n break;\n }\n#ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR\n if (len <= op - whave) {\n do {\n *out++ = 0;\n } while (--len);\n continue;\n }\n len -= op - whave;\n do {\n *out++ = 0;\n } while (--op > whave);\n if (op == 0) {\n from = out - dist;\n do {\n *out++ = *from++;\n } while (--len);\n continue;\n }\n#endif\n }\n from = window;\n if (wnext == 0) { /* very common case */\n from += wsize - op;\n if (op < len) { /* some from window */\n len -= op;\n do {\n *out++ = *from++;\n } while (--op);\n from = out - dist; /* rest from output */\n }\n }\n else if (wnext < op) { /* wrap around window */\n from += wsize + wnext - op;\n op -= wnext;\n if (op < len) { /* some from end of window */\n len -= op;\n do {\n *out++ = *from++;\n } while (--op);\n from = window;\n if (wnext < len) { /* some from start of window */\n op = wnext;\n len -= op;\n do {\n *out++ = *from++;\n } while (--op);\n from = out - dist; /* rest from output */\n }\n }\n }\n else { /* contiguous in window */\n from += wnext - op;\n if (op < len) { /* some from window */\n len -= op;\n do {\n *out++ = *from++;\n } while (--op);\n from = out - dist; /* rest from output */\n }\n }\n while (len > 2) {\n *out++ = *from++;\n *out++ = *from++;\n *out++ = *from++;\n len -= 3;\n }\n if (len) {\n *out++ = *from++;\n if (len > 1)\n *out++ = *from++;\n }\n }\n else {\n from = out - dist; /* copy direct from output */\n do { /* minimum length is three */\n *out++ = *from++;\n *out++ = *from++;\n *out++ = *from++;\n len -= 3;\n } while (len > 2);\n if (len) {\n *out++ = *from++;\n if (len > 1)\n *out++ = *from++;\n }\n }\n }\n else if ((op & 64) == 0) { /* 2nd level distance code */\n here = dcode + here->val + (hold & ((1U << op) - 1));\n goto dodist;\n }\n else {\n strm->msg = (char *)\"invalid distance code\";\n state->mode = BAD;\n break;\n }\n }\n else if ((op & 64) == 0) { /* 2nd level length code */\n here = lcode + here->val + (hold & ((1U << op) - 1));\n goto dolen;\n }\n else if (op & 32) { /* end-of-block */\n Tracevv((stderr, \"inflate: end of block\\n\"));\n state->mode = TYPE;\n break;\n }\n else {\n strm->msg = (char *)\"invalid literal/length code\";\n state->mode = BAD;\n break;\n }\n } while (in < last && out < end);\n\n /* return unused bytes (on entry, bits < 8, so in won't go too far back) */\n len = bits >> 3;\n in -= len;\n bits -= len << 3;\n hold &= (1U << bits) - 1;\n\n /* update state and return */\n strm->next_in = in;\n strm->next_out = out;\n strm->avail_in = (unsigned)(in < last ? 5 + (last - in) : 5 - (in - last));\n strm->avail_out = (unsigned)(out < end ?\n 257 + (end - out) : 257 - (out - end));\n state->hold = hold;\n state->bits = bits;\n return;\n}\n\n/*\n inflate_fast() speedups that turned out slower (on a PowerPC G3 750CXe):\n - Using bit fields for code structure\n - Different op definition to avoid & for extra bits (do & for table bits)\n - Three separate decoding do-loops for direct, window, and wnext == 0\n - Special case for distance > 1 copies to do overlapped load and store copy\n - Explicit branch predictions (based on measured branch probabilities)\n - Deferring match copy and interspersed it with decoding subsequent codes\n - Swapping literal/length else\n - Swapping window/direct else\n - Larger unrolled copy loops (three is about right)\n - Moving len -= 3 statement into middle of loop\n */\n\n#endif /* !ASMINF */\n" }, { "path": "pypcode/zlib/inffast.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* inffast.h -- header to use inffast.c\n * Copyright (C) 1995-2003, 2010 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* WARNING: this file should *not* be used by applications. It is\n part of the implementation of the compression library and is\n subject to change. Applications should only use zlib.h.\n */\n\nvoid ZLIB_INTERNAL inflate_fast(z_streamp strm, unsigned start);\n" }, { "path": "pypcode/zlib/inffixed.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n /* inffixed.h -- table for decoding fixed codes\n * Generated automatically by makefixed().\n */\n\n /* WARNING: this file should *not* be used by applications.\n It is part of the implementation of this library and is\n subject to change. Applications should only use zlib.h.\n */\n\n static const code lenfix[512] = {\n {96,7,0},{0,8,80},{0,8,16},{20,8,115},{18,7,31},{0,8,112},{0,8,48},\n {0,9,192},{16,7,10},{0,8,96},{0,8,32},{0,9,160},{0,8,0},{0,8,128},\n {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},\n {0,8,120},{0,8,56},{0,9,208},{17,7,17},{0,8,104},{0,8,40},{0,9,176},\n {0,8,8},{0,8,136},{0,8,72},{0,9,240},{16,7,4},{0,8,84},{0,8,20},\n {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},\n {0,8,36},{0,9,168},{0,8,4},{0,8,132},{0,8,68},{0,9,232},{16,7,8},\n {0,8,92},{0,8,28},{0,9,152},{20,7,83},{0,8,124},{0,8,60},{0,9,216},\n {18,7,23},{0,8,108},{0,8,44},{0,9,184},{0,8,12},{0,8,140},{0,8,76},\n {0,9,248},{16,7,3},{0,8,82},{0,8,18},{21,8,163},{19,7,35},{0,8,114},\n {0,8,50},{0,9,196},{17,7,11},{0,8,98},{0,8,34},{0,9,164},{0,8,2},\n {0,8,130},{0,8,66},{0,9,228},{16,7,7},{0,8,90},{0,8,26},{0,9,148},\n {20,7,67},{0,8,122},{0,8,58},{0,9,212},{18,7,19},{0,8,106},{0,8,42},\n {0,9,180},{0,8,10},{0,8,138},{0,8,74},{0,9,244},{16,7,5},{0,8,86},\n {0,8,22},{64,8,0},{19,7,51},{0,8,118},{0,8,54},{0,9,204},{17,7,15},\n {0,8,102},{0,8,38},{0,9,172},{0,8,6},{0,8,134},{0,8,70},{0,9,236},\n {16,7,9},{0,8,94},{0,8,30},{0,9,156},{20,7,99},{0,8,126},{0,8,62},\n {0,9,220},{18,7,27},{0,8,110},{0,8,46},{0,9,188},{0,8,14},{0,8,142},\n {0,8,78},{0,9,252},{96,7,0},{0,8,81},{0,8,17},{21,8,131},{18,7,31},\n {0,8,113},{0,8,49},{0,9,194},{16,7,10},{0,8,97},{0,8,33},{0,9,162},\n {0,8,1},{0,8,129},{0,8,65},{0,9,226},{16,7,6},{0,8,89},{0,8,25},\n {0,9,146},{19,7,59},{0,8,121},{0,8,57},{0,9,210},{17,7,17},{0,8,105},\n {0,8,41},{0,9,178},{0,8,9},{0,8,137},{0,8,73},{0,9,242},{16,7,4},\n {0,8,85},{0,8,21},{16,8,258},{19,7,43},{0,8,117},{0,8,53},{0,9,202},\n {17,7,13},{0,8,101},{0,8,37},{0,9,170},{0,8,5},{0,8,133},{0,8,69},\n {0,9,234},{16,7,8},{0,8,93},{0,8,29},{0,9,154},{20,7,83},{0,8,125},\n {0,8,61},{0,9,218},{18,7,23},{0,8,109},{0,8,45},{0,9,186},{0,8,13},\n {0,8,141},{0,8,77},{0,9,250},{16,7,3},{0,8,83},{0,8,19},{21,8,195},\n {19,7,35},{0,8,115},{0,8,51},{0,9,198},{17,7,11},{0,8,99},{0,8,35},\n {0,9,166},{0,8,3},{0,8,131},{0,8,67},{0,9,230},{16,7,7},{0,8,91},\n {0,8,27},{0,9,150},{20,7,67},{0,8,123},{0,8,59},{0,9,214},{18,7,19},\n {0,8,107},{0,8,43},{0,9,182},{0,8,11},{0,8,139},{0,8,75},{0,9,246},\n {16,7,5},{0,8,87},{0,8,23},{64,8,0},{19,7,51},{0,8,119},{0,8,55},\n {0,9,206},{17,7,15},{0,8,103},{0,8,39},{0,9,174},{0,8,7},{0,8,135},\n {0,8,71},{0,9,238},{16,7,9},{0,8,95},{0,8,31},{0,9,158},{20,7,99},\n {0,8,127},{0,8,63},{0,9,222},{18,7,27},{0,8,111},{0,8,47},{0,9,190},\n {0,8,15},{0,8,143},{0,8,79},{0,9,254},{96,7,0},{0,8,80},{0,8,16},\n {20,8,115},{18,7,31},{0,8,112},{0,8,48},{0,9,193},{16,7,10},{0,8,96},\n {0,8,32},{0,9,161},{0,8,0},{0,8,128},{0,8,64},{0,9,225},{16,7,6},\n {0,8,88},{0,8,24},{0,9,145},{19,7,59},{0,8,120},{0,8,56},{0,9,209},\n {17,7,17},{0,8,104},{0,8,40},{0,9,177},{0,8,8},{0,8,136},{0,8,72},\n {0,9,241},{16,7,4},{0,8,84},{0,8,20},{21,8,227},{19,7,43},{0,8,116},\n {0,8,52},{0,9,201},{17,7,13},{0,8,100},{0,8,36},{0,9,169},{0,8,4},\n {0,8,132},{0,8,68},{0,9,233},{16,7,8},{0,8,92},{0,8,28},{0,9,153},\n {20,7,83},{0,8,124},{0,8,60},{0,9,217},{18,7,23},{0,8,108},{0,8,44},\n {0,9,185},{0,8,12},{0,8,140},{0,8,76},{0,9,249},{16,7,3},{0,8,82},\n {0,8,18},{21,8,163},{19,7,35},{0,8,114},{0,8,50},{0,9,197},{17,7,11},\n {0,8,98},{0,8,34},{0,9,165},{0,8,2},{0,8,130},{0,8,66},{0,9,229},\n {16,7,7},{0,8,90},{0,8,26},{0,9,149},{20,7,67},{0,8,122},{0,8,58},\n {0,9,213},{18,7,19},{0,8,106},{0,8,42},{0,9,181},{0,8,10},{0,8,138},\n {0,8,74},{0,9,245},{16,7,5},{0,8,86},{0,8,22},{64,8,0},{19,7,51},\n {0,8,118},{0,8,54},{0,9,205},{17,7,15},{0,8,102},{0,8,38},{0,9,173},\n {0,8,6},{0,8,134},{0,8,70},{0,9,237},{16,7,9},{0,8,94},{0,8,30},\n {0,9,157},{20,7,99},{0,8,126},{0,8,62},{0,9,221},{18,7,27},{0,8,110},\n {0,8,46},{0,9,189},{0,8,14},{0,8,142},{0,8,78},{0,9,253},{96,7,0},\n {0,8,81},{0,8,17},{21,8,131},{18,7,31},{0,8,113},{0,8,49},{0,9,195},\n {16,7,10},{0,8,97},{0,8,33},{0,9,163},{0,8,1},{0,8,129},{0,8,65},\n {0,9,227},{16,7,6},{0,8,89},{0,8,25},{0,9,147},{19,7,59},{0,8,121},\n {0,8,57},{0,9,211},{17,7,17},{0,8,105},{0,8,41},{0,9,179},{0,8,9},\n {0,8,137},{0,8,73},{0,9,243},{16,7,4},{0,8,85},{0,8,21},{16,8,258},\n {19,7,43},{0,8,117},{0,8,53},{0,9,203},{17,7,13},{0,8,101},{0,8,37},\n {0,9,171},{0,8,5},{0,8,133},{0,8,69},{0,9,235},{16,7,8},{0,8,93},\n {0,8,29},{0,9,155},{20,7,83},{0,8,125},{0,8,61},{0,9,219},{18,7,23},\n {0,8,109},{0,8,45},{0,9,187},{0,8,13},{0,8,141},{0,8,77},{0,9,251},\n {16,7,3},{0,8,83},{0,8,19},{21,8,195},{19,7,35},{0,8,115},{0,8,51},\n {0,9,199},{17,7,11},{0,8,99},{0,8,35},{0,9,167},{0,8,3},{0,8,131},\n {0,8,67},{0,9,231},{16,7,7},{0,8,91},{0,8,27},{0,9,151},{20,7,67},\n {0,8,123},{0,8,59},{0,9,215},{18,7,19},{0,8,107},{0,8,43},{0,9,183},\n {0,8,11},{0,8,139},{0,8,75},{0,9,247},{16,7,5},{0,8,87},{0,8,23},\n {64,8,0},{19,7,51},{0,8,119},{0,8,55},{0,9,207},{17,7,15},{0,8,103},\n {0,8,39},{0,9,175},{0,8,7},{0,8,135},{0,8,71},{0,9,239},{16,7,9},\n {0,8,95},{0,8,31},{0,9,159},{20,7,99},{0,8,127},{0,8,63},{0,9,223},\n {18,7,27},{0,8,111},{0,8,47},{0,9,191},{0,8,15},{0,8,143},{0,8,79},\n {0,9,255}\n };\n\n static const code distfix[32] = {\n {16,5,1},{23,5,257},{19,5,17},{27,5,4097},{17,5,5},{25,5,1025},\n {21,5,65},{29,5,16385},{16,5,3},{24,5,513},{20,5,33},{28,5,8193},\n {18,5,9},{26,5,2049},{22,5,129},{64,5,0},{16,5,2},{23,5,385},\n {19,5,25},{27,5,6145},{17,5,7},{25,5,1537},{21,5,97},{29,5,24577},\n {16,5,4},{24,5,769},{20,5,49},{28,5,12289},{18,5,13},{26,5,3073},\n {22,5,193},{64,5,0}\n };\n" }, { "path": "pypcode/zlib/inflate.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* inflate.c -- zlib decompression\n * Copyright (C) 1995-2022 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/*\n * Change history:\n *\n * 1.2.beta0 24 Nov 2002\n * - First version -- complete rewrite of inflate to simplify code, avoid\n * creation of window when not needed, minimize use of window when it is\n * needed, make inffast.c even faster, implement gzip decoding, and to\n * improve code readability and style over the previous zlib inflate code\n *\n * 1.2.beta1 25 Nov 2002\n * - Use pointers for available input and output checking in inffast.c\n * - Remove input and output counters in inffast.c\n * - Change inffast.c entry and loop from avail_in >= 7 to >= 6\n * - Remove unnecessary second byte pull from length extra in inffast.c\n * - Unroll direct copy to three copies per loop in inffast.c\n *\n * 1.2.beta2 4 Dec 2002\n * - Change external routine names to reduce potential conflicts\n * - Correct filename to inffixed.h for fixed tables in inflate.c\n * - Make hbuf[] unsigned char to match parameter type in inflate.c\n * - Change strm->next_out[-state->offset] to *(strm->next_out - state->offset)\n * to avoid negation problem on Alphas (64 bit) in inflate.c\n *\n * 1.2.beta3 22 Dec 2002\n * - Add comments on state->bits assertion in inffast.c\n * - Add comments on op field in inftrees.h\n * - Fix bug in reuse of allocated window after inflateReset()\n * - Remove bit fields--back to byte structure for speed\n * - Remove distance extra == 0 check in inflate_fast()--only helps for lengths\n * - Change post-increments to pre-increments in inflate_fast(), PPC biased?\n * - Add compile time option, POSTINC, to use post-increments instead (Intel?)\n * - Make MATCH copy in inflate() much faster for when inflate_fast() not used\n * - Use local copies of stream next and avail values, as well as local bit\n * buffer and bit count in inflate()--for speed when inflate_fast() not used\n *\n * 1.2.beta4 1 Jan 2003\n * - Split ptr - 257 statements in inflate_table() to avoid compiler warnings\n * - Move a comment on output buffer sizes from inffast.c to inflate.c\n * - Add comments in inffast.c to introduce the inflate_fast() routine\n * - Rearrange window copies in inflate_fast() for speed and simplification\n * - Unroll last copy for window match in inflate_fast()\n * - Use local copies of window variables in inflate_fast() for speed\n * - Pull out common wnext == 0 case for speed in inflate_fast()\n * - Make op and len in inflate_fast() unsigned for consistency\n * - Add FAR to lcode and dcode declarations in inflate_fast()\n * - Simplified bad distance check in inflate_fast()\n * - Added inflateBackInit(), inflateBack(), and inflateBackEnd() in new\n * source file infback.c to provide a call-back interface to inflate for\n * programs like gzip and unzip -- uses window as output buffer to avoid\n * window copying\n *\n * 1.2.beta5 1 Jan 2003\n * - Improved inflateBack() interface to allow the caller to provide initial\n * input in strm.\n * - Fixed stored blocks bug in inflateBack()\n *\n * 1.2.beta6 4 Jan 2003\n * - Added comments in inffast.c on effectiveness of POSTINC\n * - Typecasting all around to reduce compiler warnings\n * - Changed loops from while (1) or do {} while (1) to for (;;), again to\n * make compilers happy\n * - Changed type of window in inflateBackInit() to unsigned char *\n *\n * 1.2.beta7 27 Jan 2003\n * - Changed many types to unsigned or unsigned short to avoid warnings\n * - Added inflateCopy() function\n *\n * 1.2.0 9 Mar 2003\n * - Changed inflateBack() interface to provide separate opaque descriptors\n * for the in() and out() functions\n * - Changed inflateBack() argument and in_func typedef to swap the length\n * and buffer address return values for the input function\n * - Check next_in and next_out for Z_NULL on entry to inflate()\n *\n * The history for versions after 1.2.0 are in ChangeLog in zlib distribution.\n */\n\n#include \"zutil.h\"\n#include \"inftrees.h\"\n#include \"inflate.h\"\n#include \"inffast.h\"\n\n#ifdef MAKEFIXED\n# ifndef BUILDFIXED\n# define BUILDFIXED\n# endif\n#endif\n\nlocal int inflateStateCheck(z_streamp strm) {\n struct inflate_state FAR *state;\n if (strm == Z_NULL ||\n strm->zalloc == (alloc_func)0 || strm->zfree == (free_func)0)\n return 1;\n state = (struct inflate_state FAR *)strm->state;\n if (state == Z_NULL || state->strm != strm ||\n state->mode < HEAD || state->mode > SYNC)\n return 1;\n return 0;\n}\n\nint ZEXPORT inflateResetKeep(z_streamp strm) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n strm->total_in = strm->total_out = state->total = 0;\n strm->msg = Z_NULL;\n if (state->wrap) /* to support ill-conceived Java test suite */\n strm->adler = state->wrap & 1;\n state->mode = HEAD;\n state->last = 0;\n state->havedict = 0;\n state->flags = -1;\n state->dmax = 32768U;\n state->head = Z_NULL;\n state->hold = 0;\n state->bits = 0;\n state->lencode = state->distcode = state->next = state->codes;\n state->sane = 1;\n state->back = -1;\n Tracev((stderr, \"inflate: reset\\n\"));\n return Z_OK;\n}\n\nint ZEXPORT inflateReset(z_streamp strm) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n state->wsize = 0;\n state->whave = 0;\n state->wnext = 0;\n return inflateResetKeep(strm);\n}\n\nint ZEXPORT inflateReset2(z_streamp strm, int windowBits) {\n int wrap;\n struct inflate_state FAR *state;\n\n /* get the state */\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n\n /* extract wrap request from windowBits parameter */\n if (windowBits < 0) {\n if (windowBits < -15)\n return Z_STREAM_ERROR;\n wrap = 0;\n windowBits = -windowBits;\n }\n else {\n wrap = (windowBits >> 4) + 5;\n#ifdef GUNZIP\n if (windowBits < 48)\n windowBits &= 15;\n#endif\n }\n\n /* set number of window bits, free window if different */\n if (windowBits && (windowBits < 8 || windowBits > 15))\n return Z_STREAM_ERROR;\n if (state->window != Z_NULL && state->wbits != (unsigned)windowBits) {\n ZFREE(strm, state->window);\n state->window = Z_NULL;\n }\n\n /* update state and reset the rest of it */\n state->wrap = wrap;\n state->wbits = (unsigned)windowBits;\n return inflateReset(strm);\n}\n\nint ZEXPORT inflateInit2_(z_streamp strm, int windowBits,\n const char *version, int stream_size) {\n int ret;\n struct inflate_state FAR *state;\n\n if (version == Z_NULL || version[0] != ZLIB_VERSION[0] ||\n stream_size != (int)(sizeof(z_stream)))\n return Z_VERSION_ERROR;\n if (strm == Z_NULL) return Z_STREAM_ERROR;\n strm->msg = Z_NULL; /* in case we return an error */\n if (strm->zalloc == (alloc_func)0) {\n#ifdef Z_SOLO\n return Z_STREAM_ERROR;\n#else\n strm->zalloc = zcalloc;\n strm->opaque = (voidpf)0;\n#endif\n }\n if (strm->zfree == (free_func)0)\n#ifdef Z_SOLO\n return Z_STREAM_ERROR;\n#else\n strm->zfree = zcfree;\n#endif\n state = (struct inflate_state FAR *)\n ZALLOC(strm, 1, sizeof(struct inflate_state));\n if (state == Z_NULL) return Z_MEM_ERROR;\n Tracev((stderr, \"inflate: allocated\\n\"));\n strm->state = (struct internal_state FAR *)state;\n state->strm = strm;\n state->window = Z_NULL;\n state->mode = HEAD; /* to pass state test in inflateReset2() */\n ret = inflateReset2(strm, windowBits);\n if (ret != Z_OK) {\n ZFREE(strm, state);\n strm->state = Z_NULL;\n }\n return ret;\n}\n\nint ZEXPORT inflateInit_(z_streamp strm, const char *version,\n int stream_size) {\n return inflateInit2_(strm, DEF_WBITS, version, stream_size);\n}\n\nint ZEXPORT inflatePrime(z_streamp strm, int bits, int value) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n if (bits == 0)\n return Z_OK;\n state = (struct inflate_state FAR *)strm->state;\n if (bits < 0) {\n state->hold = 0;\n state->bits = 0;\n return Z_OK;\n }\n if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR;\n value &= (1L << bits) - 1;\n state->hold += (unsigned)value << state->bits;\n state->bits += (uInt)bits;\n return Z_OK;\n}\n\n/*\n Return state with length and distance decoding tables and index sizes set to\n fixed code decoding. Normally this returns fixed tables from inffixed.h.\n If BUILDFIXED is defined, then instead this routine builds the tables the\n first time it's called, and returns those tables the first time and\n thereafter. This reduces the size of the code by about 2K bytes, in\n exchange for a little execution time. However, BUILDFIXED should not be\n used for threaded applications, since the rewriting of the tables and virgin\n may not be thread-safe.\n */\nlocal void fixedtables(struct inflate_state FAR *state) {\n#ifdef BUILDFIXED\n static int virgin = 1;\n static code *lenfix, *distfix;\n static code fixed[544];\n\n /* build fixed huffman tables if first call (may not be thread safe) */\n if (virgin) {\n unsigned sym, bits;\n static code *next;\n\n /* literal/length table */\n sym = 0;\n while (sym < 144) state->lens[sym++] = 8;\n while (sym < 256) state->lens[sym++] = 9;\n while (sym < 280) state->lens[sym++] = 7;\n while (sym < 288) state->lens[sym++] = 8;\n next = fixed;\n lenfix = next;\n bits = 9;\n inflate_table(LENS, state->lens, 288, &(next), &(bits), state->work);\n\n /* distance table */\n sym = 0;\n while (sym < 32) state->lens[sym++] = 5;\n distfix = next;\n bits = 5;\n inflate_table(DISTS, state->lens, 32, &(next), &(bits), state->work);\n\n /* do this just once */\n virgin = 0;\n }\n#else /* !BUILDFIXED */\n# include \"inffixed.h\"\n#endif /* BUILDFIXED */\n state->lencode = lenfix;\n state->lenbits = 9;\n state->distcode = distfix;\n state->distbits = 5;\n}\n\n#ifdef MAKEFIXED\n#include \n\n/*\n Write out the inffixed.h that is #include'd above. Defining MAKEFIXED also\n defines BUILDFIXED, so the tables are built on the fly. makefixed() writes\n those tables to stdout, which would be piped to inffixed.h. A small program\n can simply call makefixed to do this:\n\n void makefixed(void);\n\n int main(void)\n {\n makefixed();\n return 0;\n }\n\n Then that can be linked with zlib built with MAKEFIXED defined and run:\n\n a.out > inffixed.h\n */\nvoid makefixed(void)\n{\n unsigned low, size;\n struct inflate_state state;\n\n fixedtables(&state);\n puts(\" /* inffixed.h -- table for decoding fixed codes\");\n puts(\" * Generated automatically by makefixed().\");\n puts(\" */\");\n puts(\"\");\n puts(\" /* WARNING: this file should *not* be used by applications.\");\n puts(\" It is part of the implementation of this library and is\");\n puts(\" subject to change. Applications should only use zlib.h.\");\n puts(\" */\");\n puts(\"\");\n size = 1U << 9;\n printf(\" static const code lenfix[%u] = {\", size);\n low = 0;\n for (;;) {\n if ((low % 7) == 0) printf(\"\\n \");\n printf(\"{%u,%u,%d}\", (low & 127) == 99 ? 64 : state.lencode[low].op,\n state.lencode[low].bits, state.lencode[low].val);\n if (++low == size) break;\n putchar(',');\n }\n puts(\"\\n };\");\n size = 1U << 5;\n printf(\"\\n static const code distfix[%u] = {\", size);\n low = 0;\n for (;;) {\n if ((low % 6) == 0) printf(\"\\n \");\n printf(\"{%u,%u,%d}\", state.distcode[low].op, state.distcode[low].bits,\n state.distcode[low].val);\n if (++low == size) break;\n putchar(',');\n }\n puts(\"\\n };\");\n}\n#endif /* MAKEFIXED */\n\n/*\n Update the window with the last wsize (normally 32K) bytes written before\n returning. If window does not exist yet, create it. This is only called\n when a window is already in use, or when output has been written during this\n inflate call, but the end of the deflate stream has not been reached yet.\n It is also called to create a window for dictionary data when a dictionary\n is loaded.\n\n Providing output buffers larger than 32K to inflate() should provide a speed\n advantage, since only the last 32K of output is copied to the sliding window\n upon return from inflate(), and since all distances after the first 32K of\n output will fall in the output data, making match copies simpler and faster.\n The advantage may be dependent on the size of the processor's data caches.\n */\nlocal int updatewindow(z_streamp strm, const Bytef *end, unsigned copy) {\n struct inflate_state FAR *state;\n unsigned dist;\n\n state = (struct inflate_state FAR *)strm->state;\n\n /* if it hasn't been done already, allocate space for the window */\n if (state->window == Z_NULL) {\n state->window = (unsigned char FAR *)\n ZALLOC(strm, 1U << state->wbits,\n sizeof(unsigned char));\n if (state->window == Z_NULL) return 1;\n }\n\n /* if window not in use yet, initialize */\n if (state->wsize == 0) {\n state->wsize = 1U << state->wbits;\n state->wnext = 0;\n state->whave = 0;\n }\n\n /* copy state->wsize or less output bytes into the circular window */\n if (copy >= state->wsize) {\n zmemcpy(state->window, end - state->wsize, state->wsize);\n state->wnext = 0;\n state->whave = state->wsize;\n }\n else {\n dist = state->wsize - state->wnext;\n if (dist > copy) dist = copy;\n zmemcpy(state->window + state->wnext, end - copy, dist);\n copy -= dist;\n if (copy) {\n zmemcpy(state->window, end - copy, copy);\n state->wnext = copy;\n state->whave = state->wsize;\n }\n else {\n state->wnext += dist;\n if (state->wnext == state->wsize) state->wnext = 0;\n if (state->whave < state->wsize) state->whave += dist;\n }\n }\n return 0;\n}\n\n/* Macros for inflate(): */\n\n/* check function to use adler32() for zlib or crc32() for gzip */\n#ifdef GUNZIP\n# define UPDATE_CHECK(check, buf, len) \\\n (state->flags ? crc32(check, buf, len) : adler32(check, buf, len))\n#else\n# define UPDATE_CHECK(check, buf, len) adler32(check, buf, len)\n#endif\n\n/* check macros for header crc */\n#ifdef GUNZIP\n# define CRC2(check, word) \\\n do { \\\n hbuf[0] = (unsigned char)(word); \\\n hbuf[1] = (unsigned char)((word) >> 8); \\\n check = crc32(check, hbuf, 2); \\\n } while (0)\n\n# define CRC4(check, word) \\\n do { \\\n hbuf[0] = (unsigned char)(word); \\\n hbuf[1] = (unsigned char)((word) >> 8); \\\n hbuf[2] = (unsigned char)((word) >> 16); \\\n hbuf[3] = (unsigned char)((word) >> 24); \\\n check = crc32(check, hbuf, 4); \\\n } while (0)\n#endif\n\n/* Load registers with state in inflate() for speed */\n#define LOAD() \\\n do { \\\n put = strm->next_out; \\\n left = strm->avail_out; \\\n next = strm->next_in; \\\n have = strm->avail_in; \\\n hold = state->hold; \\\n bits = state->bits; \\\n } while (0)\n\n/* Restore state from registers in inflate() */\n#define RESTORE() \\\n do { \\\n strm->next_out = put; \\\n strm->avail_out = left; \\\n strm->next_in = next; \\\n strm->avail_in = have; \\\n state->hold = hold; \\\n state->bits = bits; \\\n } while (0)\n\n/* Clear the input bit accumulator */\n#define INITBITS() \\\n do { \\\n hold = 0; \\\n bits = 0; \\\n } while (0)\n\n/* Get a byte of input into the bit accumulator, or return from inflate()\n if there is no input available. */\n#define PULLBYTE() \\\n do { \\\n if (have == 0) goto inf_leave; \\\n have--; \\\n hold += (unsigned long)(*next++) << bits; \\\n bits += 8; \\\n } while (0)\n\n/* Assure that there are at least n bits in the bit accumulator. If there is\n not enough available input to do that, then return from inflate(). */\n#define NEEDBITS(n) \\\n do { \\\n while (bits < (unsigned)(n)) \\\n PULLBYTE(); \\\n } while (0)\n\n/* Return the low n bits of the bit accumulator (n < 16) */\n#define BITS(n) \\\n ((unsigned)hold & ((1U << (n)) - 1))\n\n/* Remove n bits from the bit accumulator */\n#define DROPBITS(n) \\\n do { \\\n hold >>= (n); \\\n bits -= (unsigned)(n); \\\n } while (0)\n\n/* Remove zero to seven bits as needed to go to a byte boundary */\n#define BYTEBITS() \\\n do { \\\n hold >>= bits & 7; \\\n bits -= bits & 7; \\\n } while (0)\n\n/*\n inflate() uses a state machine to process as much input data and generate as\n much output data as possible before returning. The state machine is\n structured roughly as follows:\n\n for (;;) switch (state) {\n ...\n case STATEn:\n if (not enough input data or output space to make progress)\n return;\n ... make progress ...\n state = STATEm;\n break;\n ...\n }\n\n so when inflate() is called again, the same case is attempted again, and\n if the appropriate resources are provided, the machine proceeds to the\n next state. The NEEDBITS() macro is usually the way the state evaluates\n whether it can proceed or should return. NEEDBITS() does the return if\n the requested bits are not available. The typical use of the BITS macros\n is:\n\n NEEDBITS(n);\n ... do something with BITS(n) ...\n DROPBITS(n);\n\n where NEEDBITS(n) either returns from inflate() if there isn't enough\n input left to load n bits into the accumulator, or it continues. BITS(n)\n gives the low n bits in the accumulator. When done, DROPBITS(n) drops\n the low n bits off the accumulator. INITBITS() clears the accumulator\n and sets the number of available bits to zero. BYTEBITS() discards just\n enough bits to put the accumulator on a byte boundary. After BYTEBITS()\n and a NEEDBITS(8), then BITS(8) would return the next byte in the stream.\n\n NEEDBITS(n) uses PULLBYTE() to get an available byte of input, or to return\n if there is no input available. The decoding of variable length codes uses\n PULLBYTE() directly in order to pull just enough bytes to decode the next\n code, and no more.\n\n Some states loop until they get enough input, making sure that enough\n state information is maintained to continue the loop where it left off\n if NEEDBITS() returns in the loop. For example, want, need, and keep\n would all have to actually be part of the saved state in case NEEDBITS()\n returns:\n\n case STATEw:\n while (want < need) {\n NEEDBITS(n);\n keep[want++] = BITS(n);\n DROPBITS(n);\n }\n state = STATEx;\n case STATEx:\n\n As shown above, if the next state is also the next case, then the break\n is omitted.\n\n A state may also return if there is not enough output space available to\n complete that state. Those states are copying stored data, writing a\n literal byte, and copying a matching string.\n\n When returning, a \"goto inf_leave\" is used to update the total counters,\n update the check value, and determine whether any progress has been made\n during that inflate() call in order to return the proper return code.\n Progress is defined as a change in either strm->avail_in or strm->avail_out.\n When there is a window, goto inf_leave will update the window with the last\n output written. If a goto inf_leave occurs in the middle of decompression\n and there is no window currently, goto inf_leave will create one and copy\n output to the window for the next call of inflate().\n\n In this implementation, the flush parameter of inflate() only affects the\n return code (per zlib.h). inflate() always writes as much as possible to\n strm->next_out, given the space available and the provided input--the effect\n documented in zlib.h of Z_SYNC_FLUSH. Furthermore, inflate() always defers\n the allocation of and copying into a sliding window until necessary, which\n provides the effect documented in zlib.h for Z_FINISH when the entire input\n stream available. So the only thing the flush parameter actually does is:\n when flush is set to Z_FINISH, inflate() cannot return Z_OK. Instead it\n will return Z_BUF_ERROR if it has not reached the end of the stream.\n */\n\nint ZEXPORT inflate(z_streamp strm, int flush) {\n struct inflate_state FAR *state;\n z_const unsigned char FAR *next; /* next input */\n unsigned char FAR *put; /* next output */\n unsigned have, left; /* available input and output */\n unsigned long hold; /* bit buffer */\n unsigned bits; /* bits in bit buffer */\n unsigned in, out; /* save starting available input and output */\n unsigned copy; /* number of stored or match bytes to copy */\n unsigned char FAR *from; /* where to copy match bytes from */\n code here; /* current decoding table entry */\n code last; /* parent table entry */\n unsigned len; /* length to copy for repeats, bits to drop */\n int ret; /* return code */\n#ifdef GUNZIP\n unsigned char hbuf[4]; /* buffer for gzip header crc calculation */\n#endif\n static const unsigned short order[19] = /* permutation of code lengths */\n {16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15};\n\n if (inflateStateCheck(strm) || strm->next_out == Z_NULL ||\n (strm->next_in == Z_NULL && strm->avail_in != 0))\n return Z_STREAM_ERROR;\n\n state = (struct inflate_state FAR *)strm->state;\n if (state->mode == TYPE) state->mode = TYPEDO; /* skip check */\n LOAD();\n in = have;\n out = left;\n ret = Z_OK;\n for (;;)\n switch (state->mode) {\n case HEAD:\n if (state->wrap == 0) {\n state->mode = TYPEDO;\n break;\n }\n NEEDBITS(16);\n#ifdef GUNZIP\n if ((state->wrap & 2) && hold == 0x8b1f) { /* gzip header */\n if (state->wbits == 0)\n state->wbits = 15;\n state->check = crc32(0L, Z_NULL, 0);\n CRC2(state->check, hold);\n INITBITS();\n state->mode = FLAGS;\n break;\n }\n if (state->head != Z_NULL)\n state->head->done = -1;\n if (!(state->wrap & 1) || /* check if zlib header allowed */\n#else\n if (\n#endif\n ((BITS(8) << 8) + (hold >> 8)) % 31) {\n strm->msg = (char *)\"incorrect header check\";\n state->mode = BAD;\n break;\n }\n if (BITS(4) != Z_DEFLATED) {\n strm->msg = (char *)\"unknown compression method\";\n state->mode = BAD;\n break;\n }\n DROPBITS(4);\n len = BITS(4) + 8;\n if (state->wbits == 0)\n state->wbits = len;\n if (len > 15 || len > state->wbits) {\n strm->msg = (char *)\"invalid window size\";\n state->mode = BAD;\n break;\n }\n state->dmax = 1U << len;\n state->flags = 0; /* indicate zlib header */\n Tracev((stderr, \"inflate: zlib header ok\\n\"));\n strm->adler = state->check = adler32(0L, Z_NULL, 0);\n state->mode = hold & 0x200 ? DICTID : TYPE;\n INITBITS();\n break;\n#ifdef GUNZIP\n case FLAGS:\n NEEDBITS(16);\n state->flags = (int)(hold);\n if ((state->flags & 0xff) != Z_DEFLATED) {\n strm->msg = (char *)\"unknown compression method\";\n state->mode = BAD;\n break;\n }\n if (state->flags & 0xe000) {\n strm->msg = (char *)\"unknown header flags set\";\n state->mode = BAD;\n break;\n }\n if (state->head != Z_NULL)\n state->head->text = (int)((hold >> 8) & 1);\n if ((state->flags & 0x0200) && (state->wrap & 4))\n CRC2(state->check, hold);\n INITBITS();\n state->mode = TIME;\n /* fallthrough */\n case TIME:\n NEEDBITS(32);\n if (state->head != Z_NULL)\n state->head->time = hold;\n if ((state->flags & 0x0200) && (state->wrap & 4))\n CRC4(state->check, hold);\n INITBITS();\n state->mode = OS;\n /* fallthrough */\n case OS:\n NEEDBITS(16);\n if (state->head != Z_NULL) {\n state->head->xflags = (int)(hold & 0xff);\n state->head->os = (int)(hold >> 8);\n }\n if ((state->flags & 0x0200) && (state->wrap & 4))\n CRC2(state->check, hold);\n INITBITS();\n state->mode = EXLEN;\n /* fallthrough */\n case EXLEN:\n if (state->flags & 0x0400) {\n NEEDBITS(16);\n state->length = (unsigned)(hold);\n if (state->head != Z_NULL)\n state->head->extra_len = (unsigned)hold;\n if ((state->flags & 0x0200) && (state->wrap & 4))\n CRC2(state->check, hold);\n INITBITS();\n }\n else if (state->head != Z_NULL)\n state->head->extra = Z_NULL;\n state->mode = EXTRA;\n /* fallthrough */\n case EXTRA:\n if (state->flags & 0x0400) {\n copy = state->length;\n if (copy > have) copy = have;\n if (copy) {\n if (state->head != Z_NULL &&\n state->head->extra != Z_NULL &&\n (len = state->head->extra_len - state->length) <\n state->head->extra_max) {\n zmemcpy(state->head->extra + len, next,\n len + copy > state->head->extra_max ?\n state->head->extra_max - len : copy);\n }\n if ((state->flags & 0x0200) && (state->wrap & 4))\n state->check = crc32(state->check, next, copy);\n have -= copy;\n next += copy;\n state->length -= copy;\n }\n if (state->length) goto inf_leave;\n }\n state->length = 0;\n state->mode = NAME;\n /* fallthrough */\n case NAME:\n if (state->flags & 0x0800) {\n if (have == 0) goto inf_leave;\n copy = 0;\n do {\n len = (unsigned)(next[copy++]);\n if (state->head != Z_NULL &&\n state->head->name != Z_NULL &&\n state->length < state->head->name_max)\n state->head->name[state->length++] = (Bytef)len;\n } while (len && copy < have);\n if ((state->flags & 0x0200) && (state->wrap & 4))\n state->check = crc32(state->check, next, copy);\n have -= copy;\n next += copy;\n if (len) goto inf_leave;\n }\n else if (state->head != Z_NULL)\n state->head->name = Z_NULL;\n state->length = 0;\n state->mode = COMMENT;\n /* fallthrough */\n case COMMENT:\n if (state->flags & 0x1000) {\n if (have == 0) goto inf_leave;\n copy = 0;\n do {\n len = (unsigned)(next[copy++]);\n if (state->head != Z_NULL &&\n state->head->comment != Z_NULL &&\n state->length < state->head->comm_max)\n state->head->comment[state->length++] = (Bytef)len;\n } while (len && copy < have);\n if ((state->flags & 0x0200) && (state->wrap & 4))\n state->check = crc32(state->check, next, copy);\n have -= copy;\n next += copy;\n if (len) goto inf_leave;\n }\n else if (state->head != Z_NULL)\n state->head->comment = Z_NULL;\n state->mode = HCRC;\n /* fallthrough */\n case HCRC:\n if (state->flags & 0x0200) {\n NEEDBITS(16);\n if ((state->wrap & 4) && hold != (state->check & 0xffff)) {\n strm->msg = (char *)\"header crc mismatch\";\n state->mode = BAD;\n break;\n }\n INITBITS();\n }\n if (state->head != Z_NULL) {\n state->head->hcrc = (int)((state->flags >> 9) & 1);\n state->head->done = 1;\n }\n strm->adler = state->check = crc32(0L, Z_NULL, 0);\n state->mode = TYPE;\n break;\n#endif\n case DICTID:\n NEEDBITS(32);\n strm->adler = state->check = ZSWAP32(hold);\n INITBITS();\n state->mode = DICT;\n /* fallthrough */\n case DICT:\n if (state->havedict == 0) {\n RESTORE();\n return Z_NEED_DICT;\n }\n strm->adler = state->check = adler32(0L, Z_NULL, 0);\n state->mode = TYPE;\n /* fallthrough */\n case TYPE:\n if (flush == Z_BLOCK || flush == Z_TREES) goto inf_leave;\n /* fallthrough */\n case TYPEDO:\n if (state->last) {\n BYTEBITS();\n state->mode = CHECK;\n break;\n }\n NEEDBITS(3);\n state->last = BITS(1);\n DROPBITS(1);\n switch (BITS(2)) {\n case 0: /* stored block */\n Tracev((stderr, \"inflate: stored block%s\\n\",\n state->last ? \" (last)\" : \"\"));\n state->mode = STORED;\n break;\n case 1: /* fixed block */\n fixedtables(state);\n Tracev((stderr, \"inflate: fixed codes block%s\\n\",\n state->last ? \" (last)\" : \"\"));\n state->mode = LEN_; /* decode codes */\n if (flush == Z_TREES) {\n DROPBITS(2);\n goto inf_leave;\n }\n break;\n case 2: /* dynamic block */\n Tracev((stderr, \"inflate: dynamic codes block%s\\n\",\n state->last ? \" (last)\" : \"\"));\n state->mode = TABLE;\n break;\n case 3:\n strm->msg = (char *)\"invalid block type\";\n state->mode = BAD;\n }\n DROPBITS(2);\n break;\n case STORED:\n BYTEBITS(); /* go to byte boundary */\n NEEDBITS(32);\n if ((hold & 0xffff) != ((hold >> 16) ^ 0xffff)) {\n strm->msg = (char *)\"invalid stored block lengths\";\n state->mode = BAD;\n break;\n }\n state->length = (unsigned)hold & 0xffff;\n Tracev((stderr, \"inflate: stored length %u\\n\",\n state->length));\n INITBITS();\n state->mode = COPY_;\n if (flush == Z_TREES) goto inf_leave;\n /* fallthrough */\n case COPY_:\n state->mode = COPY;\n /* fallthrough */\n case COPY:\n copy = state->length;\n if (copy) {\n if (copy > have) copy = have;\n if (copy > left) copy = left;\n if (copy == 0) goto inf_leave;\n zmemcpy(put, next, copy);\n have -= copy;\n next += copy;\n left -= copy;\n put += copy;\n state->length -= copy;\n break;\n }\n Tracev((stderr, \"inflate: stored end\\n\"));\n state->mode = TYPE;\n break;\n case TABLE:\n NEEDBITS(14);\n state->nlen = BITS(5) + 257;\n DROPBITS(5);\n state->ndist = BITS(5) + 1;\n DROPBITS(5);\n state->ncode = BITS(4) + 4;\n DROPBITS(4);\n#ifndef PKZIP_BUG_WORKAROUND\n if (state->nlen > 286 || state->ndist > 30) {\n strm->msg = (char *)\"too many length or distance symbols\";\n state->mode = BAD;\n break;\n }\n#endif\n Tracev((stderr, \"inflate: table sizes ok\\n\"));\n state->have = 0;\n state->mode = LENLENS;\n /* fallthrough */\n case LENLENS:\n while (state->have < state->ncode) {\n NEEDBITS(3);\n state->lens[order[state->have++]] = (unsigned short)BITS(3);\n DROPBITS(3);\n }\n while (state->have < 19)\n state->lens[order[state->have++]] = 0;\n state->next = state->codes;\n state->lencode = (const code FAR *)(state->next);\n state->lenbits = 7;\n ret = inflate_table(CODES, state->lens, 19, &(state->next),\n &(state->lenbits), state->work);\n if (ret) {\n strm->msg = (char *)\"invalid code lengths set\";\n state->mode = BAD;\n break;\n }\n Tracev((stderr, \"inflate: code lengths ok\\n\"));\n state->have = 0;\n state->mode = CODELENS;\n /* fallthrough */\n case CODELENS:\n while (state->have < state->nlen + state->ndist) {\n for (;;) {\n here = state->lencode[BITS(state->lenbits)];\n if ((unsigned)(here.bits) <= bits) break;\n PULLBYTE();\n }\n if (here.val < 16) {\n DROPBITS(here.bits);\n state->lens[state->have++] = here.val;\n }\n else {\n if (here.val == 16) {\n NEEDBITS(here.bits + 2);\n DROPBITS(here.bits);\n if (state->have == 0) {\n strm->msg = (char *)\"invalid bit length repeat\";\n state->mode = BAD;\n break;\n }\n len = state->lens[state->have - 1];\n copy = 3 + BITS(2);\n DROPBITS(2);\n }\n else if (here.val == 17) {\n NEEDBITS(here.bits + 3);\n DROPBITS(here.bits);\n len = 0;\n copy = 3 + BITS(3);\n DROPBITS(3);\n }\n else {\n NEEDBITS(here.bits + 7);\n DROPBITS(here.bits);\n len = 0;\n copy = 11 + BITS(7);\n DROPBITS(7);\n }\n if (state->have + copy > state->nlen + state->ndist) {\n strm->msg = (char *)\"invalid bit length repeat\";\n state->mode = BAD;\n break;\n }\n while (copy--)\n state->lens[state->have++] = (unsigned short)len;\n }\n }\n\n /* handle error breaks in while */\n if (state->mode == BAD) break;\n\n /* check for end-of-block code (better have one) */\n if (state->lens[256] == 0) {\n strm->msg = (char *)\"invalid code -- missing end-of-block\";\n state->mode = BAD;\n break;\n }\n\n /* build code tables -- note: do not change the lenbits or distbits\n values here (9 and 6) without reading the comments in inftrees.h\n concerning the ENOUGH constants, which depend on those values */\n state->next = state->codes;\n state->lencode = (const code FAR *)(state->next);\n state->lenbits = 9;\n ret = inflate_table(LENS, state->lens, state->nlen, &(state->next),\n &(state->lenbits), state->work);\n if (ret) {\n strm->msg = (char *)\"invalid literal/lengths set\";\n state->mode = BAD;\n break;\n }\n state->distcode = (const code FAR *)(state->next);\n state->distbits = 6;\n ret = inflate_table(DISTS, state->lens + state->nlen, state->ndist,\n &(state->next), &(state->distbits), state->work);\n if (ret) {\n strm->msg = (char *)\"invalid distances set\";\n state->mode = BAD;\n break;\n }\n Tracev((stderr, \"inflate: codes ok\\n\"));\n state->mode = LEN_;\n if (flush == Z_TREES) goto inf_leave;\n /* fallthrough */\n case LEN_:\n state->mode = LEN;\n /* fallthrough */\n case LEN:\n if (have >= 6 && left >= 258) {\n RESTORE();\n inflate_fast(strm, out);\n LOAD();\n if (state->mode == TYPE)\n state->back = -1;\n break;\n }\n state->back = 0;\n for (;;) {\n here = state->lencode[BITS(state->lenbits)];\n if ((unsigned)(here.bits) <= bits) break;\n PULLBYTE();\n }\n if (here.op && (here.op & 0xf0) == 0) {\n last = here;\n for (;;) {\n here = state->lencode[last.val +\n (BITS(last.bits + last.op) >> last.bits)];\n if ((unsigned)(last.bits + here.bits) <= bits) break;\n PULLBYTE();\n }\n DROPBITS(last.bits);\n state->back += last.bits;\n }\n DROPBITS(here.bits);\n state->back += here.bits;\n state->length = (unsigned)here.val;\n if ((int)(here.op) == 0) {\n Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?\n \"inflate: literal '%c'\\n\" :\n \"inflate: literal 0x%02x\\n\", here.val));\n state->mode = LIT;\n break;\n }\n if (here.op & 32) {\n Tracevv((stderr, \"inflate: end of block\\n\"));\n state->back = -1;\n state->mode = TYPE;\n break;\n }\n if (here.op & 64) {\n strm->msg = (char *)\"invalid literal/length code\";\n state->mode = BAD;\n break;\n }\n state->extra = (unsigned)(here.op) & 15;\n state->mode = LENEXT;\n /* fallthrough */\n case LENEXT:\n if (state->extra) {\n NEEDBITS(state->extra);\n state->length += BITS(state->extra);\n DROPBITS(state->extra);\n state->back += state->extra;\n }\n Tracevv((stderr, \"inflate: length %u\\n\", state->length));\n state->was = state->length;\n state->mode = DIST;\n /* fallthrough */\n case DIST:\n for (;;) {\n here = state->distcode[BITS(state->distbits)];\n if ((unsigned)(here.bits) <= bits) break;\n PULLBYTE();\n }\n if ((here.op & 0xf0) == 0) {\n last = here;\n for (;;) {\n here = state->distcode[last.val +\n (BITS(last.bits + last.op) >> last.bits)];\n if ((unsigned)(last.bits + here.bits) <= bits) break;\n PULLBYTE();\n }\n DROPBITS(last.bits);\n state->back += last.bits;\n }\n DROPBITS(here.bits);\n state->back += here.bits;\n if (here.op & 64) {\n strm->msg = (char *)\"invalid distance code\";\n state->mode = BAD;\n break;\n }\n state->offset = (unsigned)here.val;\n state->extra = (unsigned)(here.op) & 15;\n state->mode = DISTEXT;\n /* fallthrough */\n case DISTEXT:\n if (state->extra) {\n NEEDBITS(state->extra);\n state->offset += BITS(state->extra);\n DROPBITS(state->extra);\n state->back += state->extra;\n }\n#ifdef INFLATE_STRICT\n if (state->offset > state->dmax) {\n strm->msg = (char *)\"invalid distance too far back\";\n state->mode = BAD;\n break;\n }\n#endif\n Tracevv((stderr, \"inflate: distance %u\\n\", state->offset));\n state->mode = MATCH;\n /* fallthrough */\n case MATCH:\n if (left == 0) goto inf_leave;\n copy = out - left;\n if (state->offset > copy) { /* copy from window */\n copy = state->offset - copy;\n if (copy > state->whave) {\n if (state->sane) {\n strm->msg = (char *)\"invalid distance too far back\";\n state->mode = BAD;\n break;\n }\n#ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR\n Trace((stderr, \"inflate.c too far\\n\"));\n copy -= state->whave;\n if (copy > state->length) copy = state->length;\n if (copy > left) copy = left;\n left -= copy;\n state->length -= copy;\n do {\n *put++ = 0;\n } while (--copy);\n if (state->length == 0) state->mode = LEN;\n break;\n#endif\n }\n if (copy > state->wnext) {\n copy -= state->wnext;\n from = state->window + (state->wsize - copy);\n }\n else\n from = state->window + (state->wnext - copy);\n if (copy > state->length) copy = state->length;\n }\n else { /* copy from output */\n from = put - state->offset;\n copy = state->length;\n }\n if (copy > left) copy = left;\n left -= copy;\n state->length -= copy;\n do {\n *put++ = *from++;\n } while (--copy);\n if (state->length == 0) state->mode = LEN;\n break;\n case LIT:\n if (left == 0) goto inf_leave;\n *put++ = (unsigned char)(state->length);\n left--;\n state->mode = LEN;\n break;\n case CHECK:\n if (state->wrap) {\n NEEDBITS(32);\n out -= left;\n strm->total_out += out;\n state->total += out;\n if ((state->wrap & 4) && out)\n strm->adler = state->check =\n UPDATE_CHECK(state->check, put - out, out);\n out = left;\n if ((state->wrap & 4) && (\n#ifdef GUNZIP\n state->flags ? hold :\n#endif\n ZSWAP32(hold)) != state->check) {\n strm->msg = (char *)\"incorrect data check\";\n state->mode = BAD;\n break;\n }\n INITBITS();\n Tracev((stderr, \"inflate: check matches trailer\\n\"));\n }\n#ifdef GUNZIP\n state->mode = LENGTH;\n /* fallthrough */\n case LENGTH:\n if (state->wrap && state->flags) {\n NEEDBITS(32);\n if ((state->wrap & 4) && hold != (state->total & 0xffffffff)) {\n strm->msg = (char *)\"incorrect length check\";\n state->mode = BAD;\n break;\n }\n INITBITS();\n Tracev((stderr, \"inflate: length matches trailer\\n\"));\n }\n#endif\n state->mode = DONE;\n /* fallthrough */\n case DONE:\n ret = Z_STREAM_END;\n goto inf_leave;\n case BAD:\n ret = Z_DATA_ERROR;\n goto inf_leave;\n case MEM:\n return Z_MEM_ERROR;\n case SYNC:\n /* fallthrough */\n default:\n return Z_STREAM_ERROR;\n }\n\n /*\n Return from inflate(), updating the total counts and the check value.\n If there was no progress during the inflate() call, return a buffer\n error. Call updatewindow() to create and/or update the window state.\n Note: a memory error from inflate() is non-recoverable.\n */\n inf_leave:\n RESTORE();\n if (state->wsize || (out != strm->avail_out && state->mode < BAD &&\n (state->mode < CHECK || flush != Z_FINISH)))\n if (updatewindow(strm, strm->next_out, out - strm->avail_out)) {\n state->mode = MEM;\n return Z_MEM_ERROR;\n }\n in -= strm->avail_in;\n out -= strm->avail_out;\n strm->total_in += in;\n strm->total_out += out;\n state->total += out;\n if ((state->wrap & 4) && out)\n strm->adler = state->check =\n UPDATE_CHECK(state->check, strm->next_out - out, out);\n strm->data_type = (int)state->bits + (state->last ? 64 : 0) +\n (state->mode == TYPE ? 128 : 0) +\n (state->mode == LEN_ || state->mode == COPY_ ? 256 : 0);\n if (((in == 0 && out == 0) || flush == Z_FINISH) && ret == Z_OK)\n ret = Z_BUF_ERROR;\n return ret;\n}\n\nint ZEXPORT inflateEnd(z_streamp strm) {\n struct inflate_state FAR *state;\n if (inflateStateCheck(strm))\n return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n if (state->window != Z_NULL) ZFREE(strm, state->window);\n ZFREE(strm, strm->state);\n strm->state = Z_NULL;\n Tracev((stderr, \"inflate: end\\n\"));\n return Z_OK;\n}\n\nint ZEXPORT inflateGetDictionary(z_streamp strm, Bytef *dictionary,\n uInt *dictLength) {\n struct inflate_state FAR *state;\n\n /* check state */\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n\n /* copy dictionary */\n if (state->whave && dictionary != Z_NULL) {\n zmemcpy(dictionary, state->window + state->wnext,\n state->whave - state->wnext);\n zmemcpy(dictionary + state->whave - state->wnext,\n state->window, state->wnext);\n }\n if (dictLength != Z_NULL)\n *dictLength = state->whave;\n return Z_OK;\n}\n\nint ZEXPORT inflateSetDictionary(z_streamp strm, const Bytef *dictionary,\n uInt dictLength) {\n struct inflate_state FAR *state;\n unsigned long dictid;\n int ret;\n\n /* check state */\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n if (state->wrap != 0 && state->mode != DICT)\n return Z_STREAM_ERROR;\n\n /* check for correct dictionary identifier */\n if (state->mode == DICT) {\n dictid = adler32(0L, Z_NULL, 0);\n dictid = adler32(dictid, dictionary, dictLength);\n if (dictid != state->check)\n return Z_DATA_ERROR;\n }\n\n /* copy dictionary to window using updatewindow(), which will amend the\n existing dictionary if appropriate */\n ret = updatewindow(strm, dictionary + dictLength, dictLength);\n if (ret) {\n state->mode = MEM;\n return Z_MEM_ERROR;\n }\n state->havedict = 1;\n Tracev((stderr, \"inflate: dictionary set\\n\"));\n return Z_OK;\n}\n\nint ZEXPORT inflateGetHeader(z_streamp strm, gz_headerp head) {\n struct inflate_state FAR *state;\n\n /* check state */\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n if ((state->wrap & 2) == 0) return Z_STREAM_ERROR;\n\n /* save header structure */\n state->head = head;\n head->done = 0;\n return Z_OK;\n}\n\n/*\n Search buf[0..len-1] for the pattern: 0, 0, 0xff, 0xff. Return when found\n or when out of input. When called, *have is the number of pattern bytes\n found in order so far, in 0..3. On return *have is updated to the new\n state. If on return *have equals four, then the pattern was found and the\n return value is how many bytes were read including the last byte of the\n pattern. If *have is less than four, then the pattern has not been found\n yet and the return value is len. In the latter case, syncsearch() can be\n called again with more data and the *have state. *have is initialized to\n zero for the first call.\n */\nlocal unsigned syncsearch(unsigned FAR *have, const unsigned char FAR *buf,\n unsigned len) {\n unsigned got;\n unsigned next;\n\n got = *have;\n next = 0;\n while (next < len && got < 4) {\n if ((int)(buf[next]) == (got < 2 ? 0 : 0xff))\n got++;\n else if (buf[next])\n got = 0;\n else\n got = 4 - got;\n next++;\n }\n *have = got;\n return next;\n}\n\nint ZEXPORT inflateSync(z_streamp strm) {\n unsigned len; /* number of bytes to look at or looked at */\n int flags; /* temporary to save header status */\n unsigned long in, out; /* temporary to save total_in and total_out */\n unsigned char buf[4]; /* to restore bit buffer to byte string */\n struct inflate_state FAR *state;\n\n /* check parameters */\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n if (strm->avail_in == 0 && state->bits < 8) return Z_BUF_ERROR;\n\n /* if first time, start search in bit buffer */\n if (state->mode != SYNC) {\n state->mode = SYNC;\n state->hold >>= state->bits & 7;\n state->bits -= state->bits & 7;\n len = 0;\n while (state->bits >= 8) {\n buf[len++] = (unsigned char)(state->hold);\n state->hold >>= 8;\n state->bits -= 8;\n }\n state->have = 0;\n syncsearch(&(state->have), buf, len);\n }\n\n /* search available input */\n len = syncsearch(&(state->have), strm->next_in, strm->avail_in);\n strm->avail_in -= len;\n strm->next_in += len;\n strm->total_in += len;\n\n /* return no joy or set up to restart inflate() on a new block */\n if (state->have != 4) return Z_DATA_ERROR;\n if (state->flags == -1)\n state->wrap = 0; /* if no header yet, treat as raw */\n else\n state->wrap &= ~4; /* no point in computing a check value now */\n flags = state->flags;\n in = strm->total_in; out = strm->total_out;\n inflateReset(strm);\n strm->total_in = in; strm->total_out = out;\n state->flags = flags;\n state->mode = TYPE;\n return Z_OK;\n}\n\n/*\n Returns true if inflate is currently at the end of a block generated by\n Z_SYNC_FLUSH or Z_FULL_FLUSH. This function is used by one PPP\n implementation to provide an additional safety check. PPP uses\n Z_SYNC_FLUSH but removes the length bytes of the resulting empty stored\n block. When decompressing, PPP checks that at the end of input packet,\n inflate is waiting for these length bytes.\n */\nint ZEXPORT inflateSyncPoint(z_streamp strm) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n return state->mode == STORED && state->bits == 0;\n}\n\nint ZEXPORT inflateCopy(z_streamp dest, z_streamp source) {\n struct inflate_state FAR *state;\n struct inflate_state FAR *copy;\n unsigned char FAR *window;\n unsigned wsize;\n\n /* check input */\n if (inflateStateCheck(source) || dest == Z_NULL)\n return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)source->state;\n\n /* allocate space */\n copy = (struct inflate_state FAR *)\n ZALLOC(source, 1, sizeof(struct inflate_state));\n if (copy == Z_NULL) return Z_MEM_ERROR;\n window = Z_NULL;\n if (state->window != Z_NULL) {\n window = (unsigned char FAR *)\n ZALLOC(source, 1U << state->wbits, sizeof(unsigned char));\n if (window == Z_NULL) {\n ZFREE(source, copy);\n return Z_MEM_ERROR;\n }\n }\n\n /* copy state */\n zmemcpy((voidpf)dest, (voidpf)source, sizeof(z_stream));\n zmemcpy((voidpf)copy, (voidpf)state, sizeof(struct inflate_state));\n copy->strm = dest;\n if (state->lencode >= state->codes &&\n state->lencode <= state->codes + ENOUGH - 1) {\n copy->lencode = copy->codes + (state->lencode - state->codes);\n copy->distcode = copy->codes + (state->distcode - state->codes);\n }\n copy->next = copy->codes + (state->next - state->codes);\n if (window != Z_NULL) {\n wsize = 1U << state->wbits;\n zmemcpy(window, state->window, wsize);\n }\n copy->window = window;\n dest->state = (struct internal_state FAR *)copy;\n return Z_OK;\n}\n\nint ZEXPORT inflateUndermine(z_streamp strm, int subvert) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n#ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR\n state->sane = !subvert;\n return Z_OK;\n#else\n (void)subvert;\n state->sane = 1;\n return Z_DATA_ERROR;\n#endif\n}\n\nint ZEXPORT inflateValidate(z_streamp strm, int check) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n state = (struct inflate_state FAR *)strm->state;\n if (check && state->wrap)\n state->wrap |= 4;\n else\n state->wrap &= ~4;\n return Z_OK;\n}\n\nlong ZEXPORT inflateMark(z_streamp strm) {\n struct inflate_state FAR *state;\n\n if (inflateStateCheck(strm))\n return -(1L << 16);\n state = (struct inflate_state FAR *)strm->state;\n return (long)(((unsigned long)((long)state->back)) << 16) +\n (state->mode == COPY ? state->length :\n (state->mode == MATCH ? state->was - state->length : 0));\n}\n\nunsigned long ZEXPORT inflateCodesUsed(z_streamp strm) {\n struct inflate_state FAR *state;\n if (inflateStateCheck(strm)) return (unsigned long)-1;\n state = (struct inflate_state FAR *)strm->state;\n return (unsigned long)(state->next - state->codes);\n}\n" }, { "path": "pypcode/zlib/inflate.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* inflate.h -- internal inflate state definition\n * Copyright (C) 1995-2019 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* WARNING: this file should *not* be used by applications. It is\n part of the implementation of the compression library and is\n subject to change. Applications should only use zlib.h.\n */\n\n/* define NO_GZIP when compiling if you want to disable gzip header and\n trailer decoding by inflate(). NO_GZIP would be used to avoid linking in\n the crc code when it is not needed. For shared libraries, gzip decoding\n should be left enabled. */\n#ifndef NO_GZIP\n# define GUNZIP\n#endif\n\n/* Possible inflate modes between inflate() calls */\ntypedef enum {\n HEAD = 16180, /* i: waiting for magic header */\n FLAGS, /* i: waiting for method and flags (gzip) */\n TIME, /* i: waiting for modification time (gzip) */\n OS, /* i: waiting for extra flags and operating system (gzip) */\n EXLEN, /* i: waiting for extra length (gzip) */\n EXTRA, /* i: waiting for extra bytes (gzip) */\n NAME, /* i: waiting for end of file name (gzip) */\n COMMENT, /* i: waiting for end of comment (gzip) */\n HCRC, /* i: waiting for header crc (gzip) */\n DICTID, /* i: waiting for dictionary check value */\n DICT, /* waiting for inflateSetDictionary() call */\n TYPE, /* i: waiting for type bits, including last-flag bit */\n TYPEDO, /* i: same, but skip check to exit inflate on new block */\n STORED, /* i: waiting for stored size (length and complement) */\n COPY_, /* i/o: same as COPY below, but only first time in */\n COPY, /* i/o: waiting for input or output to copy stored block */\n TABLE, /* i: waiting for dynamic block table lengths */\n LENLENS, /* i: waiting for code length code lengths */\n CODELENS, /* i: waiting for length/lit and distance code lengths */\n LEN_, /* i: same as LEN below, but only first time in */\n LEN, /* i: waiting for length/lit/eob code */\n LENEXT, /* i: waiting for length extra bits */\n DIST, /* i: waiting for distance code */\n DISTEXT, /* i: waiting for distance extra bits */\n MATCH, /* o: waiting for output space to copy string */\n LIT, /* o: waiting for output space to write literal */\n CHECK, /* i: waiting for 32-bit check value */\n LENGTH, /* i: waiting for 32-bit length (gzip) */\n DONE, /* finished check, done -- remain here until reset */\n BAD, /* got a data error -- remain here until reset */\n MEM, /* got an inflate() memory error -- remain here until reset */\n SYNC /* looking for synchronization bytes to restart inflate() */\n} inflate_mode;\n\n/*\n State transitions between above modes -\n\n (most modes can go to BAD or MEM on error -- not shown for clarity)\n\n Process header:\n HEAD -> (gzip) or (zlib) or (raw)\n (gzip) -> FLAGS -> TIME -> OS -> EXLEN -> EXTRA -> NAME -> COMMENT ->\n HCRC -> TYPE\n (zlib) -> DICTID or TYPE\n DICTID -> DICT -> TYPE\n (raw) -> TYPEDO\n Read deflate blocks:\n TYPE -> TYPEDO -> STORED or TABLE or LEN_ or CHECK\n STORED -> COPY_ -> COPY -> TYPE\n TABLE -> LENLENS -> CODELENS -> LEN_\n LEN_ -> LEN\n Read deflate codes in fixed or dynamic block:\n LEN -> LENEXT or LIT or TYPE\n LENEXT -> DIST -> DISTEXT -> MATCH -> LEN\n LIT -> LEN\n Process trailer:\n CHECK -> LENGTH -> DONE\n */\n\n/* State maintained between inflate() calls -- approximately 7K bytes, not\n including the allocated sliding window, which is up to 32K bytes. */\nstruct inflate_state {\n z_streamp strm; /* pointer back to this zlib stream */\n inflate_mode mode; /* current inflate mode */\n int last; /* true if processing last block */\n int wrap; /* bit 0 true for zlib, bit 1 true for gzip,\n bit 2 true to validate check value */\n int havedict; /* true if dictionary provided */\n int flags; /* gzip header method and flags, 0 if zlib, or\n -1 if raw or no header yet */\n unsigned dmax; /* zlib header max distance (INFLATE_STRICT) */\n unsigned long check; /* protected copy of check value */\n unsigned long total; /* protected copy of output count */\n gz_headerp head; /* where to save gzip header information */\n /* sliding window */\n unsigned wbits; /* log base 2 of requested window size */\n unsigned wsize; /* window size or zero if not using window */\n unsigned whave; /* valid bytes in the window */\n unsigned wnext; /* window write index */\n unsigned char FAR *window; /* allocated sliding window, if needed */\n /* bit accumulator */\n unsigned long hold; /* input bit accumulator */\n unsigned bits; /* number of bits in \"in\" */\n /* for string and stored block copying */\n unsigned length; /* literal or length of data to copy */\n unsigned offset; /* distance back to copy string from */\n /* for table and code decoding */\n unsigned extra; /* extra bits needed */\n /* fixed and dynamic code tables */\n code const FAR *lencode; /* starting table for length/literal codes */\n code const FAR *distcode; /* starting table for distance codes */\n unsigned lenbits; /* index bits for lencode */\n unsigned distbits; /* index bits for distcode */\n /* dynamic table building */\n unsigned ncode; /* number of code length code lengths */\n unsigned nlen; /* number of length code lengths */\n unsigned ndist; /* number of distance code lengths */\n unsigned have; /* number of code lengths in lens[] */\n code FAR *next; /* next available space in codes[] */\n unsigned short lens[320]; /* temporary storage for code lengths */\n unsigned short work[288]; /* work area for code table building */\n code codes[ENOUGH]; /* space for code tables */\n int sane; /* if false, allow invalid distance too far */\n int back; /* bits back of last unprocessed length/lit */\n unsigned was; /* initial length of match */\n};\n" }, { "path": "pypcode/zlib/inftrees.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* inftrees.c -- generate Huffman trees for efficient decoding\n * Copyright (C) 1995-2024 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n#include \"zutil.h\"\n#include \"inftrees.h\"\n\n#define MAXBITS 15\n\nconst char inflate_copyright[] =\n \" inflate 1.3.1 Copyright 1995-2024 Mark Adler \";\n/*\n If you use the zlib library in a product, an acknowledgment is welcome\n in the documentation of your product. If for some reason you cannot\n include such an acknowledgment, I would appreciate that you keep this\n copyright string in the executable of your product.\n */\n\n/*\n Build a set of tables to decode the provided canonical Huffman code.\n The code lengths are lens[0..codes-1]. The result starts at *table,\n whose indices are 0..2^bits-1. work is a writable array of at least\n lens shorts, which is used as a work area. type is the type of code\n to be generated, CODES, LENS, or DISTS. On return, zero is success,\n -1 is an invalid code, and +1 means that ENOUGH isn't enough. table\n on return points to the next available entry's address. bits is the\n requested root table index bits, and on return it is the actual root\n table index bits. It will differ if the request is greater than the\n longest code or if it is less than the shortest code.\n */\nint ZLIB_INTERNAL inflate_table(codetype type, unsigned short FAR *lens,\n unsigned codes, code FAR * FAR *table,\n unsigned FAR *bits, unsigned short FAR *work) {\n unsigned len; /* a code's length in bits */\n unsigned sym; /* index of code symbols */\n unsigned min, max; /* minimum and maximum code lengths */\n unsigned root; /* number of index bits for root table */\n unsigned curr; /* number of index bits for current table */\n unsigned drop; /* code bits to drop for sub-table */\n int left; /* number of prefix codes available */\n unsigned used; /* code entries in table used */\n unsigned huff; /* Huffman code */\n unsigned incr; /* for incrementing code, index */\n unsigned fill; /* index for replicating entries */\n unsigned low; /* low bits for current root entry */\n unsigned mask; /* mask for low root bits */\n code here; /* table entry for duplication */\n code FAR *next; /* next available space in table */\n const unsigned short FAR *base; /* base value table to use */\n const unsigned short FAR *extra; /* extra bits table to use */\n unsigned match; /* use base and extra for symbol >= match */\n unsigned short count[MAXBITS+1]; /* number of codes of each length */\n unsigned short offs[MAXBITS+1]; /* offsets in table for each length */\n static const unsigned short lbase[31] = { /* Length codes 257..285 base */\n 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31,\n 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0};\n static const unsigned short lext[31] = { /* Length codes 257..285 extra */\n 16, 16, 16, 16, 16, 16, 16, 16, 17, 17, 17, 17, 18, 18, 18, 18,\n 19, 19, 19, 19, 20, 20, 20, 20, 21, 21, 21, 21, 16, 203, 77};\n static const unsigned short dbase[32] = { /* Distance codes 0..29 base */\n 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193,\n 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145,\n 8193, 12289, 16385, 24577, 0, 0};\n static const unsigned short dext[32] = { /* Distance codes 0..29 extra */\n 16, 16, 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22,\n 23, 23, 24, 24, 25, 25, 26, 26, 27, 27,\n 28, 28, 29, 29, 64, 64};\n\n /*\n Process a set of code lengths to create a canonical Huffman code. The\n code lengths are lens[0..codes-1]. Each length corresponds to the\n symbols 0..codes-1. The Huffman code is generated by first sorting the\n symbols by length from short to long, and retaining the symbol order\n for codes with equal lengths. Then the code starts with all zero bits\n for the first code of the shortest length, and the codes are integer\n increments for the same length, and zeros are appended as the length\n increases. For the deflate format, these bits are stored backwards\n from their more natural integer increment ordering, and so when the\n decoding tables are built in the large loop below, the integer codes\n are incremented backwards.\n\n This routine assumes, but does not check, that all of the entries in\n lens[] are in the range 0..MAXBITS. The caller must assure this.\n 1..MAXBITS is interpreted as that code length. zero means that that\n symbol does not occur in this code.\n\n The codes are sorted by computing a count of codes for each length,\n creating from that a table of starting indices for each length in the\n sorted table, and then entering the symbols in order in the sorted\n table. The sorted table is work[], with that space being provided by\n the caller.\n\n The length counts are used for other purposes as well, i.e. finding\n the minimum and maximum length codes, determining if there are any\n codes at all, checking for a valid set of lengths, and looking ahead\n at length counts to determine sub-table sizes when building the\n decoding tables.\n */\n\n /* accumulate lengths for codes (assumes lens[] all in 0..MAXBITS) */\n for (len = 0; len <= MAXBITS; len++)\n count[len] = 0;\n for (sym = 0; sym < codes; sym++)\n count[lens[sym]]++;\n\n /* bound code lengths, force root to be within code lengths */\n root = *bits;\n for (max = MAXBITS; max >= 1; max--)\n if (count[max] != 0) break;\n if (root > max) root = max;\n if (max == 0) { /* no symbols to code at all */\n here.op = (unsigned char)64; /* invalid code marker */\n here.bits = (unsigned char)1;\n here.val = (unsigned short)0;\n *(*table)++ = here; /* make a table to force an error */\n *(*table)++ = here;\n *bits = 1;\n return 0; /* no symbols, but wait for decoding to report error */\n }\n for (min = 1; min < max; min++)\n if (count[min] != 0) break;\n if (root < min) root = min;\n\n /* check for an over-subscribed or incomplete set of lengths */\n left = 1;\n for (len = 1; len <= MAXBITS; len++) {\n left <<= 1;\n left -= count[len];\n if (left < 0) return -1; /* over-subscribed */\n }\n if (left > 0 && (type == CODES || max != 1))\n return -1; /* incomplete set */\n\n /* generate offsets into symbol table for each length for sorting */\n offs[1] = 0;\n for (len = 1; len < MAXBITS; len++)\n offs[len + 1] = offs[len] + count[len];\n\n /* sort symbols by length, by symbol order within each length */\n for (sym = 0; sym < codes; sym++)\n if (lens[sym] != 0) work[offs[lens[sym]]++] = (unsigned short)sym;\n\n /*\n Create and fill in decoding tables. In this loop, the table being\n filled is at next and has curr index bits. The code being used is huff\n with length len. That code is converted to an index by dropping drop\n bits off of the bottom. For codes where len is less than drop + curr,\n those top drop + curr - len bits are incremented through all values to\n fill the table with replicated entries.\n\n root is the number of index bits for the root table. When len exceeds\n root, sub-tables are created pointed to by the root entry with an index\n of the low root bits of huff. This is saved in low to check for when a\n new sub-table should be started. drop is zero when the root table is\n being filled, and drop is root when sub-tables are being filled.\n\n When a new sub-table is needed, it is necessary to look ahead in the\n code lengths to determine what size sub-table is needed. The length\n counts are used for this, and so count[] is decremented as codes are\n entered in the tables.\n\n used keeps track of how many table entries have been allocated from the\n provided *table space. It is checked for LENS and DIST tables against\n the constants ENOUGH_LENS and ENOUGH_DISTS to guard against changes in\n the initial root table size constants. See the comments in inftrees.h\n for more information.\n\n sym increments through all symbols, and the loop terminates when\n all codes of length max, i.e. all codes, have been processed. This\n routine permits incomplete codes, so another loop after this one fills\n in the rest of the decoding tables with invalid code markers.\n */\n\n /* set up for code type */\n switch (type) {\n case CODES:\n base = extra = work; /* dummy value--not used */\n match = 20;\n break;\n case LENS:\n base = lbase;\n extra = lext;\n match = 257;\n break;\n default: /* DISTS */\n base = dbase;\n extra = dext;\n match = 0;\n }\n\n /* initialize state for loop */\n huff = 0; /* starting code */\n sym = 0; /* starting code symbol */\n len = min; /* starting code length */\n next = *table; /* current table to fill in */\n curr = root; /* current table index bits */\n drop = 0; /* current bits to drop from code for index */\n low = (unsigned)(-1); /* trigger new sub-table when len > root */\n used = 1U << root; /* use root table entries */\n mask = used - 1; /* mask for comparing low */\n\n /* check available table space */\n if ((type == LENS && used > ENOUGH_LENS) ||\n (type == DISTS && used > ENOUGH_DISTS))\n return 1;\n\n /* process all codes and make table entries */\n for (;;) {\n /* create table entry */\n here.bits = (unsigned char)(len - drop);\n if (work[sym] + 1U < match) {\n here.op = (unsigned char)0;\n here.val = work[sym];\n }\n else if (work[sym] >= match) {\n here.op = (unsigned char)(extra[work[sym] - match]);\n here.val = base[work[sym] - match];\n }\n else {\n here.op = (unsigned char)(32 + 64); /* end of block */\n here.val = 0;\n }\n\n /* replicate for those indices with low len bits equal to huff */\n incr = 1U << (len - drop);\n fill = 1U << curr;\n min = fill; /* save offset to next table */\n do {\n fill -= incr;\n next[(huff >> drop) + fill] = here;\n } while (fill != 0);\n\n /* backwards increment the len-bit code huff */\n incr = 1U << (len - 1);\n while (huff & incr)\n incr >>= 1;\n if (incr != 0) {\n huff &= incr - 1;\n huff += incr;\n }\n else\n huff = 0;\n\n /* go to next symbol, update count, len */\n sym++;\n if (--(count[len]) == 0) {\n if (len == max) break;\n len = lens[work[sym]];\n }\n\n /* create new sub-table if needed */\n if (len > root && (huff & mask) != low) {\n /* if first time, transition to sub-tables */\n if (drop == 0)\n drop = root;\n\n /* increment past last table */\n next += min; /* here min is 1 << curr */\n\n /* determine length of next table */\n curr = len - drop;\n left = (int)(1 << curr);\n while (curr + drop < max) {\n left -= count[curr + drop];\n if (left <= 0) break;\n curr++;\n left <<= 1;\n }\n\n /* check for enough space */\n used += 1U << curr;\n if ((type == LENS && used > ENOUGH_LENS) ||\n (type == DISTS && used > ENOUGH_DISTS))\n return 1;\n\n /* point entry in root table to sub-table */\n low = huff & mask;\n (*table)[low].op = (unsigned char)curr;\n (*table)[low].bits = (unsigned char)root;\n (*table)[low].val = (unsigned short)(next - *table);\n }\n }\n\n /* fill in remaining table entry if code is incomplete (guaranteed to have\n at most one remaining entry, since if the code is incomplete, the\n maximum code length that was allowed to get this far is one bit) */\n if (huff != 0) {\n here.op = (unsigned char)64; /* invalid code marker */\n here.bits = (unsigned char)(len - drop);\n here.val = (unsigned short)0;\n next[huff] = here;\n }\n\n /* set return parameters */\n *table += used;\n *bits = root;\n return 0;\n}\n" }, { "path": "pypcode/zlib/inftrees.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* inftrees.h -- header to use inftrees.c\n * Copyright (C) 1995-2005, 2010 Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* WARNING: this file should *not* be used by applications. It is\n part of the implementation of the compression library and is\n subject to change. Applications should only use zlib.h.\n */\n\n/* Structure for decoding tables. Each entry provides either the\n information needed to do the operation requested by the code that\n indexed that table entry, or it provides a pointer to another\n table that indexes more bits of the code. op indicates whether\n the entry is a pointer to another table, a literal, a length or\n distance, an end-of-block, or an invalid code. For a table\n pointer, the low four bits of op is the number of index bits of\n that table. For a length or distance, the low four bits of op\n is the number of extra bits to get after the code. bits is\n the number of bits in this code or part of the code to drop off\n of the bit buffer. val is the actual byte to output in the case\n of a literal, the base length or distance, or the offset from\n the current table to the next table. Each entry is four bytes. */\ntypedef struct {\n unsigned char op; /* operation, extra bits, table bits */\n unsigned char bits; /* bits in this part of the code */\n unsigned short val; /* offset in table or code value */\n} code;\n\n/* op values as set by inflate_table():\n 00000000 - literal\n 0000tttt - table link, tttt != 0 is the number of table index bits\n 0001eeee - length or distance, eeee is the number of extra bits\n 01100000 - end of block\n 01000000 - invalid code\n */\n\n/* Maximum size of the dynamic table. The maximum number of code structures is\n 1444, which is the sum of 852 for literal/length codes and 592 for distance\n codes. These values were found by exhaustive searches using the program\n examples/enough.c found in the zlib distribution. The arguments to that\n program are the number of symbols, the initial root table size, and the\n maximum bit length of a code. \"enough 286 9 15\" for literal/length codes\n returns 852, and \"enough 30 6 15\" for distance codes returns 592. The\n initial root table size (9 or 6) is found in the fifth argument of the\n inflate_table() calls in inflate.c and infback.c. If the root table size is\n changed, then these maximum sizes would be need to be recalculated and\n updated. */\n#define ENOUGH_LENS 852\n#define ENOUGH_DISTS 592\n#define ENOUGH (ENOUGH_LENS+ENOUGH_DISTS)\n\n/* Type of code to build for inflate_table() */\ntypedef enum {\n CODES,\n LENS,\n DISTS\n} codetype;\n\nint ZLIB_INTERNAL inflate_table(codetype type, unsigned short FAR *lens,\n unsigned codes, code FAR * FAR *table,\n unsigned FAR *bits, unsigned short FAR *work);\n" }, { "path": "pypcode/zlib/trees.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* trees.c -- output deflated data using Huffman coding\n * Copyright (C) 1995-2024 Jean-loup Gailly\n * detect_data_type() function provided freely by Cosmin Truta, 2006\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/*\n * ALGORITHM\n *\n * The \"deflation\" process uses several Huffman trees. The more\n * common source values are represented by shorter bit sequences.\n *\n * Each code tree is stored in a compressed form which is itself\n * a Huffman encoding of the lengths of all the code strings (in\n * ascending order by source values). The actual code strings are\n * reconstructed from the lengths in the inflate process, as described\n * in the deflate specification.\n *\n * REFERENCES\n *\n * Deutsch, L.P.,\"'Deflate' Compressed Data Format Specification\".\n * Available in ftp.uu.net:/pub/archiving/zip/doc/deflate-1.1.doc\n *\n * Storer, James A.\n * Data Compression: Methods and Theory, pp. 49-50.\n * Computer Science Press, 1988. ISBN 0-7167-8156-5.\n *\n * Sedgewick, R.\n * Algorithms, p290.\n * Addison-Wesley, 1983. ISBN 0-201-06672-6.\n */\n\n/* @(#) $Id$ */\n\n/* #define GEN_TREES_H */\n\n#include \"deflate.h\"\n\n#ifdef ZLIB_DEBUG\n# include \n#endif\n\n/* ===========================================================================\n * Constants\n */\n\n#define MAX_BL_BITS 7\n/* Bit length codes must not exceed MAX_BL_BITS bits */\n\n#define END_BLOCK 256\n/* end of block literal code */\n\n#define REP_3_6 16\n/* repeat previous bit length 3-6 times (2 bits of repeat count) */\n\n#define REPZ_3_10 17\n/* repeat a zero length 3-10 times (3 bits of repeat count) */\n\n#define REPZ_11_138 18\n/* repeat a zero length 11-138 times (7 bits of repeat count) */\n\nlocal const int extra_lbits[LENGTH_CODES] /* extra bits for each length code */\n = {0,0,0,0,0,0,0,0,1,1,1,1,2,2,2,2,3,3,3,3,4,4,4,4,5,5,5,5,0};\n\nlocal const int extra_dbits[D_CODES] /* extra bits for each distance code */\n = {0,0,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13};\n\nlocal const int extra_blbits[BL_CODES]/* extra bits for each bit length code */\n = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,3,7};\n\nlocal const uch bl_order[BL_CODES]\n = {16,17,18,0,8,7,9,6,10,5,11,4,12,3,13,2,14,1,15};\n/* The lengths of the bit length codes are sent in order of decreasing\n * probability, to avoid transmitting the lengths for unused bit length codes.\n */\n\n/* ===========================================================================\n * Local data. These are initialized only once.\n */\n\n#define DIST_CODE_LEN 512 /* see definition of array dist_code below */\n\n#if defined(GEN_TREES_H) || !defined(STDC)\n/* non ANSI compilers may not accept trees.h */\n\nlocal ct_data static_ltree[L_CODES+2];\n/* The static literal tree. Since the bit lengths are imposed, there is no\n * need for the L_CODES extra codes used during heap construction. However\n * The codes 286 and 287 are needed to build a canonical tree (see _tr_init\n * below).\n */\n\nlocal ct_data static_dtree[D_CODES];\n/* The static distance tree. (Actually a trivial tree since all codes use\n * 5 bits.)\n */\n\nuch _dist_code[DIST_CODE_LEN];\n/* Distance codes. The first 256 values correspond to the distances\n * 3 .. 258, the last 256 values correspond to the top 8 bits of\n * the 15 bit distances.\n */\n\nuch _length_code[MAX_MATCH-MIN_MATCH+1];\n/* length code for each normalized match length (0 == MIN_MATCH) */\n\nlocal int base_length[LENGTH_CODES];\n/* First normalized length for each code (0 = MIN_MATCH) */\n\nlocal int base_dist[D_CODES];\n/* First normalized distance for each code (0 = distance of 1) */\n\n#else\n# include \"trees.h\"\n#endif /* GEN_TREES_H */\n\nstruct static_tree_desc_s {\n const ct_data *static_tree; /* static tree or NULL */\n const intf *extra_bits; /* extra bits for each code or NULL */\n int extra_base; /* base index for extra_bits */\n int elems; /* max number of elements in the tree */\n int max_length; /* max bit length for the codes */\n};\n\n#ifdef NO_INIT_GLOBAL_POINTERS\n# define TCONST\n#else\n# define TCONST const\n#endif\n\nlocal TCONST static_tree_desc static_l_desc =\n{static_ltree, extra_lbits, LITERALS+1, L_CODES, MAX_BITS};\n\nlocal TCONST static_tree_desc static_d_desc =\n{static_dtree, extra_dbits, 0, D_CODES, MAX_BITS};\n\nlocal TCONST static_tree_desc static_bl_desc =\n{(const ct_data *)0, extra_blbits, 0, BL_CODES, MAX_BL_BITS};\n\n/* ===========================================================================\n * Output a short LSB first on the stream.\n * IN assertion: there is enough room in pendingBuf.\n */\n#define put_short(s, w) { \\\n put_byte(s, (uch)((w) & 0xff)); \\\n put_byte(s, (uch)((ush)(w) >> 8)); \\\n}\n\n/* ===========================================================================\n * Reverse the first len bits of a code, using straightforward code (a faster\n * method would use a table)\n * IN assertion: 1 <= len <= 15\n */\nlocal unsigned bi_reverse(unsigned code, int len) {\n register unsigned res = 0;\n do {\n res |= code & 1;\n code >>= 1, res <<= 1;\n } while (--len > 0);\n return res >> 1;\n}\n\n/* ===========================================================================\n * Flush the bit buffer, keeping at most 7 bits in it.\n */\nlocal void bi_flush(deflate_state *s) {\n if (s->bi_valid == 16) {\n put_short(s, s->bi_buf);\n s->bi_buf = 0;\n s->bi_valid = 0;\n } else if (s->bi_valid >= 8) {\n put_byte(s, (Byte)s->bi_buf);\n s->bi_buf >>= 8;\n s->bi_valid -= 8;\n }\n}\n\n/* ===========================================================================\n * Flush the bit buffer and align the output on a byte boundary\n */\nlocal void bi_windup(deflate_state *s) {\n if (s->bi_valid > 8) {\n put_short(s, s->bi_buf);\n } else if (s->bi_valid > 0) {\n put_byte(s, (Byte)s->bi_buf);\n }\n s->bi_buf = 0;\n s->bi_valid = 0;\n#ifdef ZLIB_DEBUG\n s->bits_sent = (s->bits_sent + 7) & ~7;\n#endif\n}\n\n/* ===========================================================================\n * Generate the codes for a given tree and bit counts (which need not be\n * optimal).\n * IN assertion: the array bl_count contains the bit length statistics for\n * the given tree and the field len is set for all tree elements.\n * OUT assertion: the field code is set for all tree elements of non\n * zero code length.\n */\nlocal void gen_codes(ct_data *tree, int max_code, ushf *bl_count) {\n ush next_code[MAX_BITS+1]; /* next code value for each bit length */\n unsigned code = 0; /* running code value */\n int bits; /* bit index */\n int n; /* code index */\n\n /* The distribution counts are first used to generate the code values\n * without bit reversal.\n */\n for (bits = 1; bits <= MAX_BITS; bits++) {\n code = (code + bl_count[bits - 1]) << 1;\n next_code[bits] = (ush)code;\n }\n /* Check that the bit counts in bl_count are consistent. The last code\n * must be all ones.\n */\n Assert (code + bl_count[MAX_BITS] - 1 == (1 << MAX_BITS) - 1,\n \"inconsistent bit counts\");\n Tracev((stderr,\"\\ngen_codes: max_code %d \", max_code));\n\n for (n = 0; n <= max_code; n++) {\n int len = tree[n].Len;\n if (len == 0) continue;\n /* Now reverse the bits */\n tree[n].Code = (ush)bi_reverse(next_code[len]++, len);\n\n Tracecv(tree != static_ltree, (stderr,\"\\nn %3d %c l %2d c %4x (%x) \",\n n, (isgraph(n) ? n : ' '), len, tree[n].Code, next_code[len] - 1));\n }\n}\n\n#ifdef GEN_TREES_H\nlocal void gen_trees_header(void);\n#endif\n\n#ifndef ZLIB_DEBUG\n# define send_code(s, c, tree) send_bits(s, tree[c].Code, tree[c].Len)\n /* Send a code of the given tree. c and tree must not have side effects */\n\n#else /* !ZLIB_DEBUG */\n# define send_code(s, c, tree) \\\n { if (z_verbose>2) fprintf(stderr,\"\\ncd %3d \",(c)); \\\n send_bits(s, tree[c].Code, tree[c].Len); }\n#endif\n\n/* ===========================================================================\n * Send a value on a given number of bits.\n * IN assertion: length <= 16 and value fits in length bits.\n */\n#ifdef ZLIB_DEBUG\nlocal void send_bits(deflate_state *s, int value, int length) {\n Tracevv((stderr,\" l %2d v %4x \", length, value));\n Assert(length > 0 && length <= 15, \"invalid length\");\n s->bits_sent += (ulg)length;\n\n /* If not enough room in bi_buf, use (valid) bits from bi_buf and\n * (16 - bi_valid) bits from value, leaving (width - (16 - bi_valid))\n * unused bits in value.\n */\n if (s->bi_valid > (int)Buf_size - length) {\n s->bi_buf |= (ush)value << s->bi_valid;\n put_short(s, s->bi_buf);\n s->bi_buf = (ush)value >> (Buf_size - s->bi_valid);\n s->bi_valid += length - Buf_size;\n } else {\n s->bi_buf |= (ush)value << s->bi_valid;\n s->bi_valid += length;\n }\n}\n#else /* !ZLIB_DEBUG */\n\n#define send_bits(s, value, length) \\\n{ int len = length;\\\n if (s->bi_valid > (int)Buf_size - len) {\\\n int val = (int)value;\\\n s->bi_buf |= (ush)val << s->bi_valid;\\\n put_short(s, s->bi_buf);\\\n s->bi_buf = (ush)val >> (Buf_size - s->bi_valid);\\\n s->bi_valid += len - Buf_size;\\\n } else {\\\n s->bi_buf |= (ush)(value) << s->bi_valid;\\\n s->bi_valid += len;\\\n }\\\n}\n#endif /* ZLIB_DEBUG */\n\n\n/* the arguments must not have side effects */\n\n/* ===========================================================================\n * Initialize the various 'constant' tables.\n */\nlocal void tr_static_init(void) {\n#if defined(GEN_TREES_H) || !defined(STDC)\n static int static_init_done = 0;\n int n; /* iterates over tree elements */\n int bits; /* bit counter */\n int length; /* length value */\n int code; /* code value */\n int dist; /* distance index */\n ush bl_count[MAX_BITS+1];\n /* number of codes at each bit length for an optimal tree */\n\n if (static_init_done) return;\n\n /* For some embedded targets, global variables are not initialized: */\n#ifdef NO_INIT_GLOBAL_POINTERS\n static_l_desc.static_tree = static_ltree;\n static_l_desc.extra_bits = extra_lbits;\n static_d_desc.static_tree = static_dtree;\n static_d_desc.extra_bits = extra_dbits;\n static_bl_desc.extra_bits = extra_blbits;\n#endif\n\n /* Initialize the mapping length (0..255) -> length code (0..28) */\n length = 0;\n for (code = 0; code < LENGTH_CODES-1; code++) {\n base_length[code] = length;\n for (n = 0; n < (1 << extra_lbits[code]); n++) {\n _length_code[length++] = (uch)code;\n }\n }\n Assert (length == 256, \"tr_static_init: length != 256\");\n /* Note that the length 255 (match length 258) can be represented\n * in two different ways: code 284 + 5 bits or code 285, so we\n * overwrite length_code[255] to use the best encoding:\n */\n _length_code[length - 1] = (uch)code;\n\n /* Initialize the mapping dist (0..32K) -> dist code (0..29) */\n dist = 0;\n for (code = 0 ; code < 16; code++) {\n base_dist[code] = dist;\n for (n = 0; n < (1 << extra_dbits[code]); n++) {\n _dist_code[dist++] = (uch)code;\n }\n }\n Assert (dist == 256, \"tr_static_init: dist != 256\");\n dist >>= 7; /* from now on, all distances are divided by 128 */\n for ( ; code < D_CODES; code++) {\n base_dist[code] = dist << 7;\n for (n = 0; n < (1 << (extra_dbits[code] - 7)); n++) {\n _dist_code[256 + dist++] = (uch)code;\n }\n }\n Assert (dist == 256, \"tr_static_init: 256 + dist != 512\");\n\n /* Construct the codes of the static literal tree */\n for (bits = 0; bits <= MAX_BITS; bits++) bl_count[bits] = 0;\n n = 0;\n while (n <= 143) static_ltree[n++].Len = 8, bl_count[8]++;\n while (n <= 255) static_ltree[n++].Len = 9, bl_count[9]++;\n while (n <= 279) static_ltree[n++].Len = 7, bl_count[7]++;\n while (n <= 287) static_ltree[n++].Len = 8, bl_count[8]++;\n /* Codes 286 and 287 do not exist, but we must include them in the\n * tree construction to get a canonical Huffman tree (longest code\n * all ones)\n */\n gen_codes((ct_data *)static_ltree, L_CODES+1, bl_count);\n\n /* The static distance tree is trivial: */\n for (n = 0; n < D_CODES; n++) {\n static_dtree[n].Len = 5;\n static_dtree[n].Code = bi_reverse((unsigned)n, 5);\n }\n static_init_done = 1;\n\n# ifdef GEN_TREES_H\n gen_trees_header();\n# endif\n#endif /* defined(GEN_TREES_H) || !defined(STDC) */\n}\n\n/* ===========================================================================\n * Generate the file trees.h describing the static trees.\n */\n#ifdef GEN_TREES_H\n# ifndef ZLIB_DEBUG\n# include \n# endif\n\n# define SEPARATOR(i, last, width) \\\n ((i) == (last)? \"\\n};\\n\\n\" : \\\n ((i) % (width) == (width) - 1 ? \",\\n\" : \", \"))\n\nvoid gen_trees_header(void) {\n FILE *header = fopen(\"trees.h\", \"w\");\n int i;\n\n Assert (header != NULL, \"Can't open trees.h\");\n fprintf(header,\n \"/* header created automatically with -DGEN_TREES_H */\\n\\n\");\n\n fprintf(header, \"local const ct_data static_ltree[L_CODES+2] = {\\n\");\n for (i = 0; i < L_CODES+2; i++) {\n fprintf(header, \"{{%3u},{%3u}}%s\", static_ltree[i].Code,\n static_ltree[i].Len, SEPARATOR(i, L_CODES+1, 5));\n }\n\n fprintf(header, \"local const ct_data static_dtree[D_CODES] = {\\n\");\n for (i = 0; i < D_CODES; i++) {\n fprintf(header, \"{{%2u},{%2u}}%s\", static_dtree[i].Code,\n static_dtree[i].Len, SEPARATOR(i, D_CODES-1, 5));\n }\n\n fprintf(header, \"const uch ZLIB_INTERNAL _dist_code[DIST_CODE_LEN] = {\\n\");\n for (i = 0; i < DIST_CODE_LEN; i++) {\n fprintf(header, \"%2u%s\", _dist_code[i],\n SEPARATOR(i, DIST_CODE_LEN-1, 20));\n }\n\n fprintf(header,\n \"const uch ZLIB_INTERNAL _length_code[MAX_MATCH-MIN_MATCH+1]= {\\n\");\n for (i = 0; i < MAX_MATCH-MIN_MATCH+1; i++) {\n fprintf(header, \"%2u%s\", _length_code[i],\n SEPARATOR(i, MAX_MATCH-MIN_MATCH, 20));\n }\n\n fprintf(header, \"local const int base_length[LENGTH_CODES] = {\\n\");\n for (i = 0; i < LENGTH_CODES; i++) {\n fprintf(header, \"%1u%s\", base_length[i],\n SEPARATOR(i, LENGTH_CODES-1, 20));\n }\n\n fprintf(header, \"local const int base_dist[D_CODES] = {\\n\");\n for (i = 0; i < D_CODES; i++) {\n fprintf(header, \"%5u%s\", base_dist[i],\n SEPARATOR(i, D_CODES-1, 10));\n }\n\n fclose(header);\n}\n#endif /* GEN_TREES_H */\n\n/* ===========================================================================\n * Initialize a new block.\n */\nlocal void init_block(deflate_state *s) {\n int n; /* iterates over tree elements */\n\n /* Initialize the trees. */\n for (n = 0; n < L_CODES; n++) s->dyn_ltree[n].Freq = 0;\n for (n = 0; n < D_CODES; n++) s->dyn_dtree[n].Freq = 0;\n for (n = 0; n < BL_CODES; n++) s->bl_tree[n].Freq = 0;\n\n s->dyn_ltree[END_BLOCK].Freq = 1;\n s->opt_len = s->static_len = 0L;\n s->sym_next = s->matches = 0;\n}\n\n/* ===========================================================================\n * Initialize the tree data structures for a new zlib stream.\n */\nvoid ZLIB_INTERNAL _tr_init(deflate_state *s) {\n tr_static_init();\n\n s->l_desc.dyn_tree = s->dyn_ltree;\n s->l_desc.stat_desc = &static_l_desc;\n\n s->d_desc.dyn_tree = s->dyn_dtree;\n s->d_desc.stat_desc = &static_d_desc;\n\n s->bl_desc.dyn_tree = s->bl_tree;\n s->bl_desc.stat_desc = &static_bl_desc;\n\n s->bi_buf = 0;\n s->bi_valid = 0;\n#ifdef ZLIB_DEBUG\n s->compressed_len = 0L;\n s->bits_sent = 0L;\n#endif\n\n /* Initialize the first block of the first file: */\n init_block(s);\n}\n\n#define SMALLEST 1\n/* Index within the heap array of least frequent node in the Huffman tree */\n\n\n/* ===========================================================================\n * Remove the smallest element from the heap and recreate the heap with\n * one less element. Updates heap and heap_len.\n */\n#define pqremove(s, tree, top) \\\n{\\\n top = s->heap[SMALLEST]; \\\n s->heap[SMALLEST] = s->heap[s->heap_len--]; \\\n pqdownheap(s, tree, SMALLEST); \\\n}\n\n/* ===========================================================================\n * Compares to subtrees, using the tree depth as tie breaker when\n * the subtrees have equal frequency. This minimizes the worst case length.\n */\n#define smaller(tree, n, m, depth) \\\n (tree[n].Freq < tree[m].Freq || \\\n (tree[n].Freq == tree[m].Freq && depth[n] <= depth[m]))\n\n/* ===========================================================================\n * Restore the heap property by moving down the tree starting at node k,\n * exchanging a node with the smallest of its two sons if necessary, stopping\n * when the heap property is re-established (each father smaller than its\n * two sons).\n */\nlocal void pqdownheap(deflate_state *s, ct_data *tree, int k) {\n int v = s->heap[k];\n int j = k << 1; /* left son of k */\n while (j <= s->heap_len) {\n /* Set j to the smallest of the two sons: */\n if (j < s->heap_len &&\n smaller(tree, s->heap[j + 1], s->heap[j], s->depth)) {\n j++;\n }\n /* Exit if v is smaller than both sons */\n if (smaller(tree, v, s->heap[j], s->depth)) break;\n\n /* Exchange v with the smallest son */\n s->heap[k] = s->heap[j]; k = j;\n\n /* And continue down the tree, setting j to the left son of k */\n j <<= 1;\n }\n s->heap[k] = v;\n}\n\n/* ===========================================================================\n * Compute the optimal bit lengths for a tree and update the total bit length\n * for the current block.\n * IN assertion: the fields freq and dad are set, heap[heap_max] and\n * above are the tree nodes sorted by increasing frequency.\n * OUT assertions: the field len is set to the optimal bit length, the\n * array bl_count contains the frequencies for each bit length.\n * The length opt_len is updated; static_len is also updated if stree is\n * not null.\n */\nlocal void gen_bitlen(deflate_state *s, tree_desc *desc) {\n ct_data *tree = desc->dyn_tree;\n int max_code = desc->max_code;\n const ct_data *stree = desc->stat_desc->static_tree;\n const intf *extra = desc->stat_desc->extra_bits;\n int base = desc->stat_desc->extra_base;\n int max_length = desc->stat_desc->max_length;\n int h; /* heap index */\n int n, m; /* iterate over the tree elements */\n int bits; /* bit length */\n int xbits; /* extra bits */\n ush f; /* frequency */\n int overflow = 0; /* number of elements with bit length too large */\n\n for (bits = 0; bits <= MAX_BITS; bits++) s->bl_count[bits] = 0;\n\n /* In a first pass, compute the optimal bit lengths (which may\n * overflow in the case of the bit length tree).\n */\n tree[s->heap[s->heap_max]].Len = 0; /* root of the heap */\n\n for (h = s->heap_max + 1; h < HEAP_SIZE; h++) {\n n = s->heap[h];\n bits = tree[tree[n].Dad].Len + 1;\n if (bits > max_length) bits = max_length, overflow++;\n tree[n].Len = (ush)bits;\n /* We overwrite tree[n].Dad which is no longer needed */\n\n if (n > max_code) continue; /* not a leaf node */\n\n s->bl_count[bits]++;\n xbits = 0;\n if (n >= base) xbits = extra[n - base];\n f = tree[n].Freq;\n s->opt_len += (ulg)f * (unsigned)(bits + xbits);\n if (stree) s->static_len += (ulg)f * (unsigned)(stree[n].Len + xbits);\n }\n if (overflow == 0) return;\n\n Tracev((stderr,\"\\nbit length overflow\\n\"));\n /* This happens for example on obj2 and pic of the Calgary corpus */\n\n /* Find the first bit length which could increase: */\n do {\n bits = max_length - 1;\n while (s->bl_count[bits] == 0) bits--;\n s->bl_count[bits]--; /* move one leaf down the tree */\n s->bl_count[bits + 1] += 2; /* move one overflow item as its brother */\n s->bl_count[max_length]--;\n /* The brother of the overflow item also moves one step up,\n * but this does not affect bl_count[max_length]\n */\n overflow -= 2;\n } while (overflow > 0);\n\n /* Now recompute all bit lengths, scanning in increasing frequency.\n * h is still equal to HEAP_SIZE. (It is simpler to reconstruct all\n * lengths instead of fixing only the wrong ones. This idea is taken\n * from 'ar' written by Haruhiko Okumura.)\n */\n for (bits = max_length; bits != 0; bits--) {\n n = s->bl_count[bits];\n while (n != 0) {\n m = s->heap[--h];\n if (m > max_code) continue;\n if ((unsigned) tree[m].Len != (unsigned) bits) {\n Tracev((stderr,\"code %d bits %d->%d\\n\", m, tree[m].Len, bits));\n s->opt_len += ((ulg)bits - tree[m].Len) * tree[m].Freq;\n tree[m].Len = (ush)bits;\n }\n n--;\n }\n }\n}\n\n#ifdef DUMP_BL_TREE\n# include \n#endif\n\n/* ===========================================================================\n * Construct one Huffman tree and assigns the code bit strings and lengths.\n * Update the total bit length for the current block.\n * IN assertion: the field freq is set for all tree elements.\n * OUT assertions: the fields len and code are set to the optimal bit length\n * and corresponding code. The length opt_len is updated; static_len is\n * also updated if stree is not null. The field max_code is set.\n */\nlocal void build_tree(deflate_state *s, tree_desc *desc) {\n ct_data *tree = desc->dyn_tree;\n const ct_data *stree = desc->stat_desc->static_tree;\n int elems = desc->stat_desc->elems;\n int n, m; /* iterate over heap elements */\n int max_code = -1; /* largest code with non zero frequency */\n int node; /* new node being created */\n\n /* Construct the initial heap, with least frequent element in\n * heap[SMALLEST]. The sons of heap[n] are heap[2*n] and heap[2*n + 1].\n * heap[0] is not used.\n */\n s->heap_len = 0, s->heap_max = HEAP_SIZE;\n\n for (n = 0; n < elems; n++) {\n if (tree[n].Freq != 0) {\n s->heap[++(s->heap_len)] = max_code = n;\n s->depth[n] = 0;\n } else {\n tree[n].Len = 0;\n }\n }\n\n /* The pkzip format requires that at least one distance code exists,\n * and that at least one bit should be sent even if there is only one\n * possible code. So to avoid special checks later on we force at least\n * two codes of non zero frequency.\n */\n while (s->heap_len < 2) {\n node = s->heap[++(s->heap_len)] = (max_code < 2 ? ++max_code : 0);\n tree[node].Freq = 1;\n s->depth[node] = 0;\n s->opt_len--; if (stree) s->static_len -= stree[node].Len;\n /* node is 0 or 1 so it does not have extra bits */\n }\n desc->max_code = max_code;\n\n /* The elements heap[heap_len/2 + 1 .. heap_len] are leaves of the tree,\n * establish sub-heaps of increasing lengths:\n */\n for (n = s->heap_len/2; n >= 1; n--) pqdownheap(s, tree, n);\n\n /* Construct the Huffman tree by repeatedly combining the least two\n * frequent nodes.\n */\n node = elems; /* next internal node of the tree */\n do {\n pqremove(s, tree, n); /* n = node of least frequency */\n m = s->heap[SMALLEST]; /* m = node of next least frequency */\n\n s->heap[--(s->heap_max)] = n; /* keep the nodes sorted by frequency */\n s->heap[--(s->heap_max)] = m;\n\n /* Create a new node father of n and m */\n tree[node].Freq = tree[n].Freq + tree[m].Freq;\n s->depth[node] = (uch)((s->depth[n] >= s->depth[m] ?\n s->depth[n] : s->depth[m]) + 1);\n tree[n].Dad = tree[m].Dad = (ush)node;\n#ifdef DUMP_BL_TREE\n if (tree == s->bl_tree) {\n fprintf(stderr,\"\\nnode %d(%d), sons %d(%d) %d(%d)\",\n node, tree[node].Freq, n, tree[n].Freq, m, tree[m].Freq);\n }\n#endif\n /* and insert the new node in the heap */\n s->heap[SMALLEST] = node++;\n pqdownheap(s, tree, SMALLEST);\n\n } while (s->heap_len >= 2);\n\n s->heap[--(s->heap_max)] = s->heap[SMALLEST];\n\n /* At this point, the fields freq and dad are set. We can now\n * generate the bit lengths.\n */\n gen_bitlen(s, (tree_desc *)desc);\n\n /* The field len is now set, we can generate the bit codes */\n gen_codes ((ct_data *)tree, max_code, s->bl_count);\n}\n\n/* ===========================================================================\n * Scan a literal or distance tree to determine the frequencies of the codes\n * in the bit length tree.\n */\nlocal void scan_tree(deflate_state *s, ct_data *tree, int max_code) {\n int n; /* iterates over all tree elements */\n int prevlen = -1; /* last emitted length */\n int curlen; /* length of current code */\n int nextlen = tree[0].Len; /* length of next code */\n int count = 0; /* repeat count of the current code */\n int max_count = 7; /* max repeat count */\n int min_count = 4; /* min repeat count */\n\n if (nextlen == 0) max_count = 138, min_count = 3;\n tree[max_code + 1].Len = (ush)0xffff; /* guard */\n\n for (n = 0; n <= max_code; n++) {\n curlen = nextlen; nextlen = tree[n + 1].Len;\n if (++count < max_count && curlen == nextlen) {\n continue;\n } else if (count < min_count) {\n s->bl_tree[curlen].Freq += count;\n } else if (curlen != 0) {\n if (curlen != prevlen) s->bl_tree[curlen].Freq++;\n s->bl_tree[REP_3_6].Freq++;\n } else if (count <= 10) {\n s->bl_tree[REPZ_3_10].Freq++;\n } else {\n s->bl_tree[REPZ_11_138].Freq++;\n }\n count = 0; prevlen = curlen;\n if (nextlen == 0) {\n max_count = 138, min_count = 3;\n } else if (curlen == nextlen) {\n max_count = 6, min_count = 3;\n } else {\n max_count = 7, min_count = 4;\n }\n }\n}\n\n/* ===========================================================================\n * Send a literal or distance tree in compressed form, using the codes in\n * bl_tree.\n */\nlocal void send_tree(deflate_state *s, ct_data *tree, int max_code) {\n int n; /* iterates over all tree elements */\n int prevlen = -1; /* last emitted length */\n int curlen; /* length of current code */\n int nextlen = tree[0].Len; /* length of next code */\n int count = 0; /* repeat count of the current code */\n int max_count = 7; /* max repeat count */\n int min_count = 4; /* min repeat count */\n\n /* tree[max_code + 1].Len = -1; */ /* guard already set */\n if (nextlen == 0) max_count = 138, min_count = 3;\n\n for (n = 0; n <= max_code; n++) {\n curlen = nextlen; nextlen = tree[n + 1].Len;\n if (++count < max_count && curlen == nextlen) {\n continue;\n } else if (count < min_count) {\n do { send_code(s, curlen, s->bl_tree); } while (--count != 0);\n\n } else if (curlen != 0) {\n if (curlen != prevlen) {\n send_code(s, curlen, s->bl_tree); count--;\n }\n Assert(count >= 3 && count <= 6, \" 3_6?\");\n send_code(s, REP_3_6, s->bl_tree); send_bits(s, count - 3, 2);\n\n } else if (count <= 10) {\n send_code(s, REPZ_3_10, s->bl_tree); send_bits(s, count - 3, 3);\n\n } else {\n send_code(s, REPZ_11_138, s->bl_tree); send_bits(s, count - 11, 7);\n }\n count = 0; prevlen = curlen;\n if (nextlen == 0) {\n max_count = 138, min_count = 3;\n } else if (curlen == nextlen) {\n max_count = 6, min_count = 3;\n } else {\n max_count = 7, min_count = 4;\n }\n }\n}\n\n/* ===========================================================================\n * Construct the Huffman tree for the bit lengths and return the index in\n * bl_order of the last bit length code to send.\n */\nlocal int build_bl_tree(deflate_state *s) {\n int max_blindex; /* index of last bit length code of non zero freq */\n\n /* Determine the bit length frequencies for literal and distance trees */\n scan_tree(s, (ct_data *)s->dyn_ltree, s->l_desc.max_code);\n scan_tree(s, (ct_data *)s->dyn_dtree, s->d_desc.max_code);\n\n /* Build the bit length tree: */\n build_tree(s, (tree_desc *)(&(s->bl_desc)));\n /* opt_len now includes the length of the tree representations, except the\n * lengths of the bit lengths codes and the 5 + 5 + 4 bits for the counts.\n */\n\n /* Determine the number of bit length codes to send. The pkzip format\n * requires that at least 4 bit length codes be sent. (appnote.txt says\n * 3 but the actual value used is 4.)\n */\n for (max_blindex = BL_CODES-1; max_blindex >= 3; max_blindex--) {\n if (s->bl_tree[bl_order[max_blindex]].Len != 0) break;\n }\n /* Update opt_len to include the bit length tree and counts */\n s->opt_len += 3*((ulg)max_blindex + 1) + 5 + 5 + 4;\n Tracev((stderr, \"\\ndyn trees: dyn %ld, stat %ld\",\n s->opt_len, s->static_len));\n\n return max_blindex;\n}\n\n/* ===========================================================================\n * Send the header for a block using dynamic Huffman trees: the counts, the\n * lengths of the bit length codes, the literal tree and the distance tree.\n * IN assertion: lcodes >= 257, dcodes >= 1, blcodes >= 4.\n */\nlocal void send_all_trees(deflate_state *s, int lcodes, int dcodes,\n int blcodes) {\n int rank; /* index in bl_order */\n\n Assert (lcodes >= 257 && dcodes >= 1 && blcodes >= 4, \"not enough codes\");\n Assert (lcodes <= L_CODES && dcodes <= D_CODES && blcodes <= BL_CODES,\n \"too many codes\");\n Tracev((stderr, \"\\nbl counts: \"));\n send_bits(s, lcodes - 257, 5); /* not +255 as stated in appnote.txt */\n send_bits(s, dcodes - 1, 5);\n send_bits(s, blcodes - 4, 4); /* not -3 as stated in appnote.txt */\n for (rank = 0; rank < blcodes; rank++) {\n Tracev((stderr, \"\\nbl code %2d \", bl_order[rank]));\n send_bits(s, s->bl_tree[bl_order[rank]].Len, 3);\n }\n Tracev((stderr, \"\\nbl tree: sent %ld\", s->bits_sent));\n\n send_tree(s, (ct_data *)s->dyn_ltree, lcodes - 1); /* literal tree */\n Tracev((stderr, \"\\nlit tree: sent %ld\", s->bits_sent));\n\n send_tree(s, (ct_data *)s->dyn_dtree, dcodes - 1); /* distance tree */\n Tracev((stderr, \"\\ndist tree: sent %ld\", s->bits_sent));\n}\n\n/* ===========================================================================\n * Send a stored block\n */\nvoid ZLIB_INTERNAL _tr_stored_block(deflate_state *s, charf *buf,\n ulg stored_len, int last) {\n send_bits(s, (STORED_BLOCK<<1) + last, 3); /* send block type */\n bi_windup(s); /* align on byte boundary */\n put_short(s, (ush)stored_len);\n put_short(s, (ush)~stored_len);\n if (stored_len)\n zmemcpy(s->pending_buf + s->pending, (Bytef *)buf, stored_len);\n s->pending += stored_len;\n#ifdef ZLIB_DEBUG\n s->compressed_len = (s->compressed_len + 3 + 7) & (ulg)~7L;\n s->compressed_len += (stored_len + 4) << 3;\n s->bits_sent += 2*16;\n s->bits_sent += stored_len << 3;\n#endif\n}\n\n/* ===========================================================================\n * Flush the bits in the bit buffer to pending output (leaves at most 7 bits)\n */\nvoid ZLIB_INTERNAL _tr_flush_bits(deflate_state *s) {\n bi_flush(s);\n}\n\n/* ===========================================================================\n * Send one empty static block to give enough lookahead for inflate.\n * This takes 10 bits, of which 7 may remain in the bit buffer.\n */\nvoid ZLIB_INTERNAL _tr_align(deflate_state *s) {\n send_bits(s, STATIC_TREES<<1, 3);\n send_code(s, END_BLOCK, static_ltree);\n#ifdef ZLIB_DEBUG\n s->compressed_len += 10L; /* 3 for block type, 7 for EOB */\n#endif\n bi_flush(s);\n}\n\n/* ===========================================================================\n * Send the block data compressed using the given Huffman trees\n */\nlocal void compress_block(deflate_state *s, const ct_data *ltree,\n const ct_data *dtree) {\n unsigned dist; /* distance of matched string */\n int lc; /* match length or unmatched char (if dist == 0) */\n unsigned sx = 0; /* running index in symbol buffers */\n unsigned code; /* the code to send */\n int extra; /* number of extra bits to send */\n\n if (s->sym_next != 0) do {\n#ifdef LIT_MEM\n dist = s->d_buf[sx];\n lc = s->l_buf[sx++];\n#else\n dist = s->sym_buf[sx++] & 0xff;\n dist += (unsigned)(s->sym_buf[sx++] & 0xff) << 8;\n lc = s->sym_buf[sx++];\n#endif\n if (dist == 0) {\n send_code(s, lc, ltree); /* send a literal byte */\n Tracecv(isgraph(lc), (stderr,\" '%c' \", lc));\n } else {\n /* Here, lc is the match length - MIN_MATCH */\n code = _length_code[lc];\n send_code(s, code + LITERALS + 1, ltree); /* send length code */\n extra = extra_lbits[code];\n if (extra != 0) {\n lc -= base_length[code];\n send_bits(s, lc, extra); /* send the extra length bits */\n }\n dist--; /* dist is now the match distance - 1 */\n code = d_code(dist);\n Assert (code < D_CODES, \"bad d_code\");\n\n send_code(s, code, dtree); /* send the distance code */\n extra = extra_dbits[code];\n if (extra != 0) {\n dist -= (unsigned)base_dist[code];\n send_bits(s, dist, extra); /* send the extra distance bits */\n }\n } /* literal or match pair ? */\n\n /* Check for no overlay of pending_buf on needed symbols */\n#ifdef LIT_MEM\n Assert(s->pending < 2 * (s->lit_bufsize + sx), \"pendingBuf overflow\");\n#else\n Assert(s->pending < s->lit_bufsize + sx, \"pendingBuf overflow\");\n#endif\n\n } while (sx < s->sym_next);\n\n send_code(s, END_BLOCK, ltree);\n}\n\n/* ===========================================================================\n * Check if the data type is TEXT or BINARY, using the following algorithm:\n * - TEXT if the two conditions below are satisfied:\n * a) There are no non-portable control characters belonging to the\n * \"block list\" (0..6, 14..25, 28..31).\n * b) There is at least one printable character belonging to the\n * \"allow list\" (9 {TAB}, 10 {LF}, 13 {CR}, 32..255).\n * - BINARY otherwise.\n * - The following partially-portable control characters form a\n * \"gray list\" that is ignored in this detection algorithm:\n * (7 {BEL}, 8 {BS}, 11 {VT}, 12 {FF}, 26 {SUB}, 27 {ESC}).\n * IN assertion: the fields Freq of dyn_ltree are set.\n */\nlocal int detect_data_type(deflate_state *s) {\n /* block_mask is the bit mask of block-listed bytes\n * set bits 0..6, 14..25, and 28..31\n * 0xf3ffc07f = binary 11110011111111111100000001111111\n */\n unsigned long block_mask = 0xf3ffc07fUL;\n int n;\n\n /* Check for non-textual (\"block-listed\") bytes. */\n for (n = 0; n <= 31; n++, block_mask >>= 1)\n if ((block_mask & 1) && (s->dyn_ltree[n].Freq != 0))\n return Z_BINARY;\n\n /* Check for textual (\"allow-listed\") bytes. */\n if (s->dyn_ltree[9].Freq != 0 || s->dyn_ltree[10].Freq != 0\n || s->dyn_ltree[13].Freq != 0)\n return Z_TEXT;\n for (n = 32; n < LITERALS; n++)\n if (s->dyn_ltree[n].Freq != 0)\n return Z_TEXT;\n\n /* There are no \"block-listed\" or \"allow-listed\" bytes:\n * this stream either is empty or has tolerated (\"gray-listed\") bytes only.\n */\n return Z_BINARY;\n}\n\n/* ===========================================================================\n * Determine the best encoding for the current block: dynamic trees, static\n * trees or store, and write out the encoded block.\n */\nvoid ZLIB_INTERNAL _tr_flush_block(deflate_state *s, charf *buf,\n ulg stored_len, int last) {\n ulg opt_lenb, static_lenb; /* opt_len and static_len in bytes */\n int max_blindex = 0; /* index of last bit length code of non zero freq */\n\n /* Build the Huffman trees unless a stored block is forced */\n if (s->level > 0) {\n\n /* Check if the file is binary or text */\n if (s->strm->data_type == Z_UNKNOWN)\n s->strm->data_type = detect_data_type(s);\n\n /* Construct the literal and distance trees */\n build_tree(s, (tree_desc *)(&(s->l_desc)));\n Tracev((stderr, \"\\nlit data: dyn %ld, stat %ld\", s->opt_len,\n s->static_len));\n\n build_tree(s, (tree_desc *)(&(s->d_desc)));\n Tracev((stderr, \"\\ndist data: dyn %ld, stat %ld\", s->opt_len,\n s->static_len));\n /* At this point, opt_len and static_len are the total bit lengths of\n * the compressed block data, excluding the tree representations.\n */\n\n /* Build the bit length tree for the above two trees, and get the index\n * in bl_order of the last bit length code to send.\n */\n max_blindex = build_bl_tree(s);\n\n /* Determine the best encoding. Compute the block lengths in bytes. */\n opt_lenb = (s->opt_len + 3 + 7) >> 3;\n static_lenb = (s->static_len + 3 + 7) >> 3;\n\n Tracev((stderr, \"\\nopt %lu(%lu) stat %lu(%lu) stored %lu lit %u \",\n opt_lenb, s->opt_len, static_lenb, s->static_len, stored_len,\n s->sym_next / 3));\n\n#ifndef FORCE_STATIC\n if (static_lenb <= opt_lenb || s->strategy == Z_FIXED)\n#endif\n opt_lenb = static_lenb;\n\n } else {\n Assert(buf != (char*)0, \"lost buf\");\n opt_lenb = static_lenb = stored_len + 5; /* force a stored block */\n }\n\n#ifdef FORCE_STORED\n if (buf != (char*)0) { /* force stored block */\n#else\n if (stored_len + 4 <= opt_lenb && buf != (char*)0) {\n /* 4: two words for the lengths */\n#endif\n /* The test buf != NULL is only necessary if LIT_BUFSIZE > WSIZE.\n * Otherwise we can't have processed more than WSIZE input bytes since\n * the last block flush, because compression would have been\n * successful. If LIT_BUFSIZE <= WSIZE, it is never too late to\n * transform a block into a stored block.\n */\n _tr_stored_block(s, buf, stored_len, last);\n\n } else if (static_lenb == opt_lenb) {\n send_bits(s, (STATIC_TREES<<1) + last, 3);\n compress_block(s, (const ct_data *)static_ltree,\n (const ct_data *)static_dtree);\n#ifdef ZLIB_DEBUG\n s->compressed_len += 3 + s->static_len;\n#endif\n } else {\n send_bits(s, (DYN_TREES<<1) + last, 3);\n send_all_trees(s, s->l_desc.max_code + 1, s->d_desc.max_code + 1,\n max_blindex + 1);\n compress_block(s, (const ct_data *)s->dyn_ltree,\n (const ct_data *)s->dyn_dtree);\n#ifdef ZLIB_DEBUG\n s->compressed_len += 3 + s->opt_len;\n#endif\n }\n Assert (s->compressed_len == s->bits_sent, \"bad compressed size\");\n /* The above check is made mod 2^32, for files larger than 512 MB\n * and uLong implemented on 32 bits.\n */\n init_block(s);\n\n if (last) {\n bi_windup(s);\n#ifdef ZLIB_DEBUG\n s->compressed_len += 7; /* align on byte boundary */\n#endif\n }\n Tracev((stderr,\"\\ncomprlen %lu(%lu) \", s->compressed_len >> 3,\n s->compressed_len - 7*last));\n}\n\n/* ===========================================================================\n * Save the match info and tally the frequency counts. Return true if\n * the current block must be flushed.\n */\nint ZLIB_INTERNAL _tr_tally(deflate_state *s, unsigned dist, unsigned lc) {\n#ifdef LIT_MEM\n s->d_buf[s->sym_next] = (ush)dist;\n s->l_buf[s->sym_next++] = (uch)lc;\n#else\n s->sym_buf[s->sym_next++] = (uch)dist;\n s->sym_buf[s->sym_next++] = (uch)(dist >> 8);\n s->sym_buf[s->sym_next++] = (uch)lc;\n#endif\n if (dist == 0) {\n /* lc is the unmatched char */\n s->dyn_ltree[lc].Freq++;\n } else {\n s->matches++;\n /* Here, lc is the match length - MIN_MATCH */\n dist--; /* dist = match distance - 1 */\n Assert((ush)dist < (ush)MAX_DIST(s) &&\n (ush)lc <= (ush)(MAX_MATCH-MIN_MATCH) &&\n (ush)d_code(dist) < (ush)D_CODES, \"_tr_tally: bad match\");\n\n s->dyn_ltree[_length_code[lc] + LITERALS + 1].Freq++;\n s->dyn_dtree[d_code(dist)].Freq++;\n }\n return (s->sym_next == s->sym_end);\n}\n" }, { "path": "pypcode/zlib/trees.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* header created automatically with -DGEN_TREES_H */\n\nlocal const ct_data static_ltree[L_CODES+2] = {\n{{ 12},{ 8}}, {{140},{ 8}}, {{ 76},{ 8}}, {{204},{ 8}}, {{ 44},{ 8}},\n{{172},{ 8}}, {{108},{ 8}}, {{236},{ 8}}, {{ 28},{ 8}}, {{156},{ 8}},\n{{ 92},{ 8}}, {{220},{ 8}}, {{ 60},{ 8}}, {{188},{ 8}}, {{124},{ 8}},\n{{252},{ 8}}, {{ 2},{ 8}}, {{130},{ 8}}, {{ 66},{ 8}}, {{194},{ 8}},\n{{ 34},{ 8}}, {{162},{ 8}}, {{ 98},{ 8}}, {{226},{ 8}}, {{ 18},{ 8}},\n{{146},{ 8}}, {{ 82},{ 8}}, {{210},{ 8}}, {{ 50},{ 8}}, {{178},{ 8}},\n{{114},{ 8}}, {{242},{ 8}}, {{ 10},{ 8}}, {{138},{ 8}}, {{ 74},{ 8}},\n{{202},{ 8}}, {{ 42},{ 8}}, {{170},{ 8}}, {{106},{ 8}}, {{234},{ 8}},\n{{ 26},{ 8}}, {{154},{ 8}}, {{ 90},{ 8}}, {{218},{ 8}}, {{ 58},{ 8}},\n{{186},{ 8}}, {{122},{ 8}}, {{250},{ 8}}, {{ 6},{ 8}}, {{134},{ 8}},\n{{ 70},{ 8}}, {{198},{ 8}}, {{ 38},{ 8}}, {{166},{ 8}}, {{102},{ 8}},\n{{230},{ 8}}, {{ 22},{ 8}}, {{150},{ 8}}, {{ 86},{ 8}}, {{214},{ 8}},\n{{ 54},{ 8}}, {{182},{ 8}}, {{118},{ 8}}, {{246},{ 8}}, {{ 14},{ 8}},\n{{142},{ 8}}, {{ 78},{ 8}}, {{206},{ 8}}, {{ 46},{ 8}}, {{174},{ 8}},\n{{110},{ 8}}, {{238},{ 8}}, {{ 30},{ 8}}, {{158},{ 8}}, {{ 94},{ 8}},\n{{222},{ 8}}, {{ 62},{ 8}}, {{190},{ 8}}, {{126},{ 8}}, {{254},{ 8}},\n{{ 1},{ 8}}, {{129},{ 8}}, {{ 65},{ 8}}, {{193},{ 8}}, {{ 33},{ 8}},\n{{161},{ 8}}, {{ 97},{ 8}}, {{225},{ 8}}, {{ 17},{ 8}}, {{145},{ 8}},\n{{ 81},{ 8}}, {{209},{ 8}}, {{ 49},{ 8}}, {{177},{ 8}}, {{113},{ 8}},\n{{241},{ 8}}, {{ 9},{ 8}}, {{137},{ 8}}, {{ 73},{ 8}}, {{201},{ 8}},\n{{ 41},{ 8}}, {{169},{ 8}}, {{105},{ 8}}, {{233},{ 8}}, {{ 25},{ 8}},\n{{153},{ 8}}, {{ 89},{ 8}}, {{217},{ 8}}, {{ 57},{ 8}}, {{185},{ 8}},\n{{121},{ 8}}, {{249},{ 8}}, {{ 5},{ 8}}, {{133},{ 8}}, {{ 69},{ 8}},\n{{197},{ 8}}, {{ 37},{ 8}}, {{165},{ 8}}, {{101},{ 8}}, {{229},{ 8}},\n{{ 21},{ 8}}, {{149},{ 8}}, {{ 85},{ 8}}, {{213},{ 8}}, {{ 53},{ 8}},\n{{181},{ 8}}, {{117},{ 8}}, {{245},{ 8}}, {{ 13},{ 8}}, {{141},{ 8}},\n{{ 77},{ 8}}, {{205},{ 8}}, {{ 45},{ 8}}, {{173},{ 8}}, {{109},{ 8}},\n{{237},{ 8}}, {{ 29},{ 8}}, {{157},{ 8}}, {{ 93},{ 8}}, {{221},{ 8}},\n{{ 61},{ 8}}, {{189},{ 8}}, {{125},{ 8}}, {{253},{ 8}}, {{ 19},{ 9}},\n{{275},{ 9}}, {{147},{ 9}}, {{403},{ 9}}, {{ 83},{ 9}}, {{339},{ 9}},\n{{211},{ 9}}, {{467},{ 9}}, {{ 51},{ 9}}, {{307},{ 9}}, {{179},{ 9}},\n{{435},{ 9}}, {{115},{ 9}}, {{371},{ 9}}, {{243},{ 9}}, {{499},{ 9}},\n{{ 11},{ 9}}, {{267},{ 9}}, {{139},{ 9}}, {{395},{ 9}}, {{ 75},{ 9}},\n{{331},{ 9}}, {{203},{ 9}}, {{459},{ 9}}, {{ 43},{ 9}}, {{299},{ 9}},\n{{171},{ 9}}, {{427},{ 9}}, {{107},{ 9}}, {{363},{ 9}}, {{235},{ 9}},\n{{491},{ 9}}, {{ 27},{ 9}}, {{283},{ 9}}, {{155},{ 9}}, {{411},{ 9}},\n{{ 91},{ 9}}, {{347},{ 9}}, {{219},{ 9}}, {{475},{ 9}}, {{ 59},{ 9}},\n{{315},{ 9}}, {{187},{ 9}}, {{443},{ 9}}, {{123},{ 9}}, {{379},{ 9}},\n{{251},{ 9}}, {{507},{ 9}}, {{ 7},{ 9}}, {{263},{ 9}}, {{135},{ 9}},\n{{391},{ 9}}, {{ 71},{ 9}}, {{327},{ 9}}, {{199},{ 9}}, {{455},{ 9}},\n{{ 39},{ 9}}, {{295},{ 9}}, {{167},{ 9}}, {{423},{ 9}}, {{103},{ 9}},\n{{359},{ 9}}, {{231},{ 9}}, {{487},{ 9}}, {{ 23},{ 9}}, {{279},{ 9}},\n{{151},{ 9}}, {{407},{ 9}}, {{ 87},{ 9}}, {{343},{ 9}}, {{215},{ 9}},\n{{471},{ 9}}, {{ 55},{ 9}}, {{311},{ 9}}, {{183},{ 9}}, {{439},{ 9}},\n{{119},{ 9}}, {{375},{ 9}}, {{247},{ 9}}, {{503},{ 9}}, {{ 15},{ 9}},\n{{271},{ 9}}, {{143},{ 9}}, {{399},{ 9}}, {{ 79},{ 9}}, {{335},{ 9}},\n{{207},{ 9}}, {{463},{ 9}}, {{ 47},{ 9}}, {{303},{ 9}}, {{175},{ 9}},\n{{431},{ 9}}, {{111},{ 9}}, {{367},{ 9}}, {{239},{ 9}}, {{495},{ 9}},\n{{ 31},{ 9}}, {{287},{ 9}}, {{159},{ 9}}, {{415},{ 9}}, {{ 95},{ 9}},\n{{351},{ 9}}, {{223},{ 9}}, {{479},{ 9}}, {{ 63},{ 9}}, {{319},{ 9}},\n{{191},{ 9}}, {{447},{ 9}}, {{127},{ 9}}, {{383},{ 9}}, {{255},{ 9}},\n{{511},{ 9}}, {{ 0},{ 7}}, {{ 64},{ 7}}, {{ 32},{ 7}}, {{ 96},{ 7}},\n{{ 16},{ 7}}, {{ 80},{ 7}}, {{ 48},{ 7}}, {{112},{ 7}}, {{ 8},{ 7}},\n{{ 72},{ 7}}, {{ 40},{ 7}}, {{104},{ 7}}, {{ 24},{ 7}}, {{ 88},{ 7}},\n{{ 56},{ 7}}, {{120},{ 7}}, {{ 4},{ 7}}, {{ 68},{ 7}}, {{ 36},{ 7}},\n{{100},{ 7}}, {{ 20},{ 7}}, {{ 84},{ 7}}, {{ 52},{ 7}}, {{116},{ 7}},\n{{ 3},{ 8}}, {{131},{ 8}}, {{ 67},{ 8}}, {{195},{ 8}}, {{ 35},{ 8}},\n{{163},{ 8}}, {{ 99},{ 8}}, {{227},{ 8}}\n};\n\nlocal const ct_data static_dtree[D_CODES] = {\n{{ 0},{ 5}}, {{16},{ 5}}, {{ 8},{ 5}}, {{24},{ 5}}, {{ 4},{ 5}},\n{{20},{ 5}}, {{12},{ 5}}, {{28},{ 5}}, {{ 2},{ 5}}, {{18},{ 5}},\n{{10},{ 5}}, {{26},{ 5}}, {{ 6},{ 5}}, {{22},{ 5}}, {{14},{ 5}},\n{{30},{ 5}}, {{ 1},{ 5}}, {{17},{ 5}}, {{ 9},{ 5}}, {{25},{ 5}},\n{{ 5},{ 5}}, {{21},{ 5}}, {{13},{ 5}}, {{29},{ 5}}, {{ 3},{ 5}},\n{{19},{ 5}}, {{11},{ 5}}, {{27},{ 5}}, {{ 7},{ 5}}, {{23},{ 5}}\n};\n\nconst uch ZLIB_INTERNAL _dist_code[DIST_CODE_LEN] = {\n 0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8,\n 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10,\n10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\n11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,\n12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 13,\n13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,\n13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,\n14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,\n14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,\n14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15,\n15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,\n15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,\n15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 0, 0, 16, 17,\n18, 18, 19, 19, 20, 20, 20, 20, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22,\n23, 23, 23, 23, 23, 23, 23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,\n24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,\n26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,\n26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27,\n27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,\n27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,\n28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,\n28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,\n28, 28, 28, 28, 28, 28, 28, 28, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,\n29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,\n29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,\n29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29\n};\n\nconst uch ZLIB_INTERNAL _length_code[MAX_MATCH-MIN_MATCH+1]= {\n 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12,\n13, 13, 13, 13, 14, 14, 14, 14, 15, 15, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16,\n17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 19, 19, 19, 19,\n19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,\n21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 22, 22, 22, 22,\n22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23,\n23, 23, 23, 23, 23, 23, 23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,\n24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,\n25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,\n25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26, 26, 26,\n26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,\n26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,\n27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 28\n};\n\nlocal const int base_length[LENGTH_CODES] = {\n0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56,\n64, 80, 96, 112, 128, 160, 192, 224, 0\n};\n\nlocal const int base_dist[D_CODES] = {\n 0, 1, 2, 3, 4, 6, 8, 12, 16, 24,\n 32, 48, 64, 96, 128, 192, 256, 384, 512, 768,\n 1024, 1536, 2048, 3072, 4096, 6144, 8192, 12288, 16384, 24576\n};\n\n" }, { "path": "pypcode/zlib/zconf.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* zconf.h -- configuration of the zlib compression library\n * Copyright (C) 1995-2024 Jean-loup Gailly, Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* @(#) $Id$ */\n\n#ifndef ZCONF_H\n#define ZCONF_H\n\n/*\n * If you *really* need a unique prefix for all types and library functions,\n * compile with -DZ_PREFIX. The \"standard\" zlib should be compiled without it.\n * Even better than compiling with -DZ_PREFIX would be to use configure to set\n * this permanently in zconf.h using \"./configure --zprefix\".\n */\n#ifdef Z_PREFIX /* may be set to #if 1 by ./configure */\n# define Z_PREFIX_SET\n\n/* all linked symbols and init macros */\n# define _dist_code z__dist_code\n# define _length_code z__length_code\n# define _tr_align z__tr_align\n# define _tr_flush_bits z__tr_flush_bits\n# define _tr_flush_block z__tr_flush_block\n# define _tr_init z__tr_init\n# define _tr_stored_block z__tr_stored_block\n# define _tr_tally z__tr_tally\n# define adler32 z_adler32\n# define adler32_combine z_adler32_combine\n# define adler32_combine64 z_adler32_combine64\n# define adler32_z z_adler32_z\n# ifndef Z_SOLO\n# define compress z_compress\n# define compress2 z_compress2\n# define compressBound z_compressBound\n# endif\n# define crc32 z_crc32\n# define crc32_combine z_crc32_combine\n# define crc32_combine64 z_crc32_combine64\n# define crc32_combine_gen z_crc32_combine_gen\n# define crc32_combine_gen64 z_crc32_combine_gen64\n# define crc32_combine_op z_crc32_combine_op\n# define crc32_z z_crc32_z\n# define deflate z_deflate\n# define deflateBound z_deflateBound\n# define deflateCopy z_deflateCopy\n# define deflateEnd z_deflateEnd\n# define deflateGetDictionary z_deflateGetDictionary\n# define deflateInit z_deflateInit\n# define deflateInit2 z_deflateInit2\n# define deflateInit2_ z_deflateInit2_\n# define deflateInit_ z_deflateInit_\n# define deflateParams z_deflateParams\n# define deflatePending z_deflatePending\n# define deflatePrime z_deflatePrime\n# define deflateReset z_deflateReset\n# define deflateResetKeep z_deflateResetKeep\n# define deflateSetDictionary z_deflateSetDictionary\n# define deflateSetHeader z_deflateSetHeader\n# define deflateTune z_deflateTune\n# define deflate_copyright z_deflate_copyright\n# define get_crc_table z_get_crc_table\n# ifndef Z_SOLO\n# define gz_error z_gz_error\n# define gz_intmax z_gz_intmax\n# define gz_strwinerror z_gz_strwinerror\n# define gzbuffer z_gzbuffer\n# define gzclearerr z_gzclearerr\n# define gzclose z_gzclose\n# define gzclose_r z_gzclose_r\n# define gzclose_w z_gzclose_w\n# define gzdirect z_gzdirect\n# define gzdopen z_gzdopen\n# define gzeof z_gzeof\n# define gzerror z_gzerror\n# define gzflush z_gzflush\n# define gzfread z_gzfread\n# define gzfwrite z_gzfwrite\n# define gzgetc z_gzgetc\n# define gzgetc_ z_gzgetc_\n# define gzgets z_gzgets\n# define gzoffset z_gzoffset\n# define gzoffset64 z_gzoffset64\n# define gzopen z_gzopen\n# define gzopen64 z_gzopen64\n# ifdef _WIN32\n# define gzopen_w z_gzopen_w\n# endif\n# define gzprintf z_gzprintf\n# define gzputc z_gzputc\n# define gzputs z_gzputs\n# define gzread z_gzread\n# define gzrewind z_gzrewind\n# define gzseek z_gzseek\n# define gzseek64 z_gzseek64\n# define gzsetparams z_gzsetparams\n# define gztell z_gztell\n# define gztell64 z_gztell64\n# define gzungetc z_gzungetc\n# define gzvprintf z_gzvprintf\n# define gzwrite z_gzwrite\n# endif\n# define inflate z_inflate\n# define inflateBack z_inflateBack\n# define inflateBackEnd z_inflateBackEnd\n# define inflateBackInit z_inflateBackInit\n# define inflateBackInit_ z_inflateBackInit_\n# define inflateCodesUsed z_inflateCodesUsed\n# define inflateCopy z_inflateCopy\n# define inflateEnd z_inflateEnd\n# define inflateGetDictionary z_inflateGetDictionary\n# define inflateGetHeader z_inflateGetHeader\n# define inflateInit z_inflateInit\n# define inflateInit2 z_inflateInit2\n# define inflateInit2_ z_inflateInit2_\n# define inflateInit_ z_inflateInit_\n# define inflateMark z_inflateMark\n# define inflatePrime z_inflatePrime\n# define inflateReset z_inflateReset\n# define inflateReset2 z_inflateReset2\n# define inflateResetKeep z_inflateResetKeep\n# define inflateSetDictionary z_inflateSetDictionary\n# define inflateSync z_inflateSync\n# define inflateSyncPoint z_inflateSyncPoint\n# define inflateUndermine z_inflateUndermine\n# define inflateValidate z_inflateValidate\n# define inflate_copyright z_inflate_copyright\n# define inflate_fast z_inflate_fast\n# define inflate_table z_inflate_table\n# ifndef Z_SOLO\n# define uncompress z_uncompress\n# define uncompress2 z_uncompress2\n# endif\n# define zError z_zError\n# ifndef Z_SOLO\n# define zcalloc z_zcalloc\n# define zcfree z_zcfree\n# endif\n# define zlibCompileFlags z_zlibCompileFlags\n# define zlibVersion z_zlibVersion\n\n/* all zlib typedefs in zlib.h and zconf.h */\n# define Byte z_Byte\n# define Bytef z_Bytef\n# define alloc_func z_alloc_func\n# define charf z_charf\n# define free_func z_free_func\n# ifndef Z_SOLO\n# define gzFile z_gzFile\n# endif\n# define gz_header z_gz_header\n# define gz_headerp z_gz_headerp\n# define in_func z_in_func\n# define intf z_intf\n# define out_func z_out_func\n# define uInt z_uInt\n# define uIntf z_uIntf\n# define uLong z_uLong\n# define uLongf z_uLongf\n# define voidp z_voidp\n# define voidpc z_voidpc\n# define voidpf z_voidpf\n\n/* all zlib structs in zlib.h and zconf.h */\n# define gz_header_s z_gz_header_s\n# define internal_state z_internal_state\n\n#endif\n\n#if defined(__MSDOS__) && !defined(MSDOS)\n# define MSDOS\n#endif\n#if (defined(OS_2) || defined(__OS2__)) && !defined(OS2)\n# define OS2\n#endif\n#if defined(_WINDOWS) && !defined(WINDOWS)\n# define WINDOWS\n#endif\n#if defined(_WIN32) || defined(_WIN32_WCE) || defined(__WIN32__)\n# ifndef WIN32\n# define WIN32\n# endif\n#endif\n#if (defined(MSDOS) || defined(OS2) || defined(WINDOWS)) && !defined(WIN32)\n# if !defined(__GNUC__) && !defined(__FLAT__) && !defined(__386__)\n# ifndef SYS16BIT\n# define SYS16BIT\n# endif\n# endif\n#endif\n\n/*\n * Compile with -DMAXSEG_64K if the alloc function cannot allocate more\n * than 64k bytes at a time (needed on systems with 16-bit int).\n */\n#ifdef SYS16BIT\n# define MAXSEG_64K\n#endif\n#ifdef MSDOS\n# define UNALIGNED_OK\n#endif\n\n#ifdef __STDC_VERSION__\n# ifndef STDC\n# define STDC\n# endif\n# if __STDC_VERSION__ >= 199901L\n# ifndef STDC99\n# define STDC99\n# endif\n# endif\n#endif\n#if !defined(STDC) && (defined(__STDC__) || defined(__cplusplus))\n# define STDC\n#endif\n#if !defined(STDC) && (defined(__GNUC__) || defined(__BORLANDC__))\n# define STDC\n#endif\n#if !defined(STDC) && (defined(MSDOS) || defined(WINDOWS) || defined(WIN32))\n# define STDC\n#endif\n#if !defined(STDC) && (defined(OS2) || defined(__HOS_AIX__))\n# define STDC\n#endif\n\n#if defined(__OS400__) && !defined(STDC) /* iSeries (formerly AS/400). */\n# define STDC\n#endif\n\n#ifndef STDC\n# ifndef const /* cannot use !defined(STDC) && !defined(const) on Mac */\n# define const /* note: need a more gentle solution here */\n# endif\n#endif\n\n#if defined(ZLIB_CONST) && !defined(z_const)\n# define z_const const\n#else\n# define z_const\n#endif\n\n#ifdef Z_SOLO\n# ifdef _WIN64\n typedef unsigned long long z_size_t;\n# else\n typedef unsigned long z_size_t;\n# endif\n#else\n# define z_longlong long long\n# if defined(NO_SIZE_T)\n typedef unsigned NO_SIZE_T z_size_t;\n# elif defined(STDC)\n# include \n typedef size_t z_size_t;\n# else\n typedef unsigned long z_size_t;\n# endif\n# undef z_longlong\n#endif\n\n/* Maximum value for memLevel in deflateInit2 */\n#ifndef MAX_MEM_LEVEL\n# ifdef MAXSEG_64K\n# define MAX_MEM_LEVEL 8\n# else\n# define MAX_MEM_LEVEL 9\n# endif\n#endif\n\n/* Maximum value for windowBits in deflateInit2 and inflateInit2.\n * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files\n * created by gzip. (Files created by minigzip can still be extracted by\n * gzip.)\n */\n#ifndef MAX_WBITS\n# define MAX_WBITS 15 /* 32K LZ77 window */\n#endif\n\n/* The memory requirements for deflate are (in bytes):\n (1 << (windowBits+2)) + (1 << (memLevel+9))\n that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values)\n plus a few kilobytes for small objects. For example, if you want to reduce\n the default memory requirements from 256K to 128K, compile with\n make CFLAGS=\"-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7\"\n Of course this will generally degrade compression (there's no free lunch).\n\n The memory requirements for inflate are (in bytes) 1 << windowBits\n that is, 32K for windowBits=15 (default value) plus about 7 kilobytes\n for small objects.\n*/\n\n /* Type declarations */\n\n#ifndef OF /* function prototypes */\n# ifdef STDC\n# define OF(args) args\n# else\n# define OF(args) ()\n# endif\n#endif\n\n/* The following definitions for FAR are needed only for MSDOS mixed\n * model programming (small or medium model with some far allocations).\n * This was tested only with MSC; for other MSDOS compilers you may have\n * to define NO_MEMCPY in zutil.h. If you don't need the mixed model,\n * just define FAR to be empty.\n */\n#ifdef SYS16BIT\n# if defined(M_I86SM) || defined(M_I86MM)\n /* MSC small or medium model */\n# define SMALL_MEDIUM\n# ifdef _MSC_VER\n# define FAR _far\n# else\n# define FAR far\n# endif\n# endif\n# if (defined(__SMALL__) || defined(__MEDIUM__))\n /* Turbo C small or medium model */\n# define SMALL_MEDIUM\n# ifdef __BORLANDC__\n# define FAR _far\n# else\n# define FAR far\n# endif\n# endif\n#endif\n\n#if defined(WINDOWS) || defined(WIN32)\n /* If building or using zlib as a DLL, define ZLIB_DLL.\n * This is not mandatory, but it offers a little performance increase.\n */\n# ifdef ZLIB_DLL\n# if defined(WIN32) && (!defined(__BORLANDC__) || (__BORLANDC__ >= 0x500))\n# ifdef ZLIB_INTERNAL\n# define ZEXTERN extern __declspec(dllexport)\n# else\n# define ZEXTERN extern __declspec(dllimport)\n# endif\n# endif\n# endif /* ZLIB_DLL */\n /* If building or using zlib with the WINAPI/WINAPIV calling convention,\n * define ZLIB_WINAPI.\n * Caution: the standard ZLIB1.DLL is NOT compiled using ZLIB_WINAPI.\n */\n# ifdef ZLIB_WINAPI\n# ifdef FAR\n# undef FAR\n# endif\n# ifndef WIN32_LEAN_AND_MEAN\n# define WIN32_LEAN_AND_MEAN\n# endif\n# include \n /* No need for _export, use ZLIB.DEF instead. */\n /* For complete Windows compatibility, use WINAPI, not __stdcall. */\n# define ZEXPORT WINAPI\n# ifdef WIN32\n# define ZEXPORTVA WINAPIV\n# else\n# define ZEXPORTVA FAR CDECL\n# endif\n# endif\n#endif\n\n#if defined (__BEOS__)\n# ifdef ZLIB_DLL\n# ifdef ZLIB_INTERNAL\n# define ZEXPORT __declspec(dllexport)\n# define ZEXPORTVA __declspec(dllexport)\n# else\n# define ZEXPORT __declspec(dllimport)\n# define ZEXPORTVA __declspec(dllimport)\n# endif\n# endif\n#endif\n\n#ifndef ZEXTERN\n# define ZEXTERN extern\n#endif\n#ifndef ZEXPORT\n# define ZEXPORT\n#endif\n#ifndef ZEXPORTVA\n# define ZEXPORTVA\n#endif\n\n#ifndef FAR\n# define FAR\n#endif\n\n#if !defined(__MACTYPES__)\ntypedef unsigned char Byte; /* 8 bits */\n#endif\ntypedef unsigned int uInt; /* 16 bits or more */\ntypedef unsigned long uLong; /* 32 bits or more */\n\n#ifdef SMALL_MEDIUM\n /* Borland C/C++ and some old MSC versions ignore FAR inside typedef */\n# define Bytef Byte FAR\n#else\n typedef Byte FAR Bytef;\n#endif\ntypedef char FAR charf;\ntypedef int FAR intf;\ntypedef uInt FAR uIntf;\ntypedef uLong FAR uLongf;\n\n#ifdef STDC\n typedef void const *voidpc;\n typedef void FAR *voidpf;\n typedef void *voidp;\n#else\n typedef Byte const *voidpc;\n typedef Byte FAR *voidpf;\n typedef Byte *voidp;\n#endif\n\n#if !defined(Z_U4) && !defined(Z_SOLO) && defined(STDC)\n# include \n# if (UINT_MAX == 0xffffffffUL)\n# define Z_U4 unsigned\n# elif (ULONG_MAX == 0xffffffffUL)\n# define Z_U4 unsigned long\n# elif (USHRT_MAX == 0xffffffffUL)\n# define Z_U4 unsigned short\n# endif\n#endif\n\n#ifdef Z_U4\n typedef Z_U4 z_crc_t;\n#else\n typedef unsigned long z_crc_t;\n#endif\n\n#ifdef HAVE_UNISTD_H /* may be set to #if 1 by ./configure */\n# define Z_HAVE_UNISTD_H\n#endif\n\n#ifdef HAVE_STDARG_H /* may be set to #if 1 by ./configure */\n# define Z_HAVE_STDARG_H\n#endif\n\n#ifdef STDC\n# ifndef Z_SOLO\n# include /* for off_t */\n# endif\n#endif\n\n#if defined(STDC) || defined(Z_HAVE_STDARG_H)\n# ifndef Z_SOLO\n# include /* for va_list */\n# endif\n#endif\n\n#ifdef _WIN32\n# ifndef Z_SOLO\n# include /* for wchar_t */\n# endif\n#endif\n\n/* a little trick to accommodate both \"#define _LARGEFILE64_SOURCE\" and\n * \"#define _LARGEFILE64_SOURCE 1\" as requesting 64-bit operations, (even\n * though the former does not conform to the LFS document), but considering\n * both \"#undef _LARGEFILE64_SOURCE\" and \"#define _LARGEFILE64_SOURCE 0\" as\n * equivalently requesting no 64-bit operations\n */\n#if defined(_LARGEFILE64_SOURCE) && -_LARGEFILE64_SOURCE - -1 == 1\n# undef _LARGEFILE64_SOURCE\n#endif\n\n#ifndef Z_HAVE_UNISTD_H\n# ifdef __WATCOMC__\n# define Z_HAVE_UNISTD_H\n# endif\n#endif\n#ifndef Z_HAVE_UNISTD_H\n# if defined(_LARGEFILE64_SOURCE) && !defined(_WIN32)\n# define Z_HAVE_UNISTD_H\n# endif\n#endif\n#ifndef Z_SOLO\n# if defined(Z_HAVE_UNISTD_H)\n# include /* for SEEK_*, off_t, and _LFS64_LARGEFILE */\n# ifdef VMS\n# include /* for off_t */\n# endif\n# ifndef z_off_t\n# define z_off_t off_t\n# endif\n# endif\n#endif\n\n#if defined(_LFS64_LARGEFILE) && _LFS64_LARGEFILE-0\n# define Z_LFS64\n#endif\n\n#if defined(_LARGEFILE64_SOURCE) && defined(Z_LFS64)\n# define Z_LARGE64\n#endif\n\n#if defined(_FILE_OFFSET_BITS) && _FILE_OFFSET_BITS-0 == 64 && defined(Z_LFS64)\n# define Z_WANT64\n#endif\n\n#if !defined(SEEK_SET) && !defined(Z_SOLO)\n# define SEEK_SET 0 /* Seek from beginning of file. */\n# define SEEK_CUR 1 /* Seek from current position. */\n# define SEEK_END 2 /* Set file pointer to EOF plus \"offset\" */\n#endif\n\n#ifndef z_off_t\n# define z_off_t long\n#endif\n\n#if !defined(_WIN32) && defined(Z_LARGE64)\n# define z_off64_t off64_t\n#else\n# if defined(_WIN32) && !defined(__GNUC__)\n# define z_off64_t __int64\n# else\n# define z_off64_t z_off_t\n# endif\n#endif\n\n/* MVS linker does not support external names larger than 8 bytes */\n#if defined(__MVS__)\n #pragma map(deflateInit_,\"DEIN\")\n #pragma map(deflateInit2_,\"DEIN2\")\n #pragma map(deflateEnd,\"DEEND\")\n #pragma map(deflateBound,\"DEBND\")\n #pragma map(inflateInit_,\"ININ\")\n #pragma map(inflateInit2_,\"ININ2\")\n #pragma map(inflateEnd,\"INEND\")\n #pragma map(inflateSync,\"INSY\")\n #pragma map(inflateSetDictionary,\"INSEDI\")\n #pragma map(compressBound,\"CMBND\")\n #pragma map(inflate_table,\"INTABL\")\n #pragma map(inflate_fast,\"INFA\")\n #pragma map(inflate_copyright,\"INCOPY\")\n#endif\n\n#endif /* ZCONF_H */\n" }, { "path": "pypcode/zlib/zlib.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* zlib.h -- interface of the 'zlib' general purpose compression library\n version 1.3.1, January 22nd, 2024\n\n Copyright (C) 1995-2024 Jean-loup Gailly and Mark Adler\n\n This software is provided 'as-is', without any express or implied\n warranty. In no event will the authors be held liable for any damages\n arising from the use of this software.\n\n Permission is granted to anyone to use this software for any purpose,\n including commercial applications, and to alter it and redistribute it\n freely, subject to the following restrictions:\n\n 1. The origin of this software must not be misrepresented; you must not\n claim that you wrote the original software. If you use this software\n in a product, an acknowledgment in the product documentation would be\n appreciated but is not required.\n 2. Altered source versions must be plainly marked as such, and must not be\n misrepresented as being the original software.\n 3. This notice may not be removed or altered from any source distribution.\n\n Jean-loup Gailly Mark Adler\n jloup@gzip.org madler@alumni.caltech.edu\n\n\n The data format used by the zlib library is described by RFCs (Request for\n Comments) 1950 to 1952 in the files http://tools.ietf.org/html/rfc1950\n (zlib format), rfc1951 (deflate format) and rfc1952 (gzip format).\n*/\n\n#ifndef ZLIB_H\n#define ZLIB_H\n\n#include \"zconf.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define ZLIB_VERSION \"1.3.1\"\n#define ZLIB_VERNUM 0x1310\n#define ZLIB_VER_MAJOR 1\n#define ZLIB_VER_MINOR 3\n#define ZLIB_VER_REVISION 1\n#define ZLIB_VER_SUBREVISION 0\n\n/*\n The 'zlib' compression library provides in-memory compression and\n decompression functions, including integrity checks of the uncompressed data.\n This version of the library supports only one compression method (deflation)\n but other algorithms will be added later and will have the same stream\n interface.\n\n Compression can be done in a single step if the buffers are large enough,\n or can be done by repeated calls of the compression function. In the latter\n case, the application must provide more input and/or consume the output\n (providing more output space) before each call.\n\n The compressed data format used by default by the in-memory functions is\n the zlib format, which is a zlib wrapper documented in RFC 1950, wrapped\n around a deflate stream, which is itself documented in RFC 1951.\n\n The library also supports reading and writing files in gzip (.gz) format\n with an interface similar to that of stdio using the functions that start\n with \"gz\". The gzip format is different from the zlib format. gzip is a\n gzip wrapper, documented in RFC 1952, wrapped around a deflate stream.\n\n This library can optionally read and write gzip and raw deflate streams in\n memory as well.\n\n The zlib format was designed to be compact and fast for use in memory\n and on communications channels. The gzip format was designed for single-\n file compression on file systems, has a larger header than zlib to maintain\n directory information, and uses a different, slower check method than zlib.\n\n The library does not install any signal handler. The decoder checks\n the consistency of the compressed data, so the library should never crash\n even in the case of corrupted input.\n*/\n\ntypedef voidpf (*alloc_func)(voidpf opaque, uInt items, uInt size);\ntypedef void (*free_func)(voidpf opaque, voidpf address);\n\nstruct internal_state;\n\ntypedef struct z_stream_s {\n z_const Bytef *next_in; /* next input byte */\n uInt avail_in; /* number of bytes available at next_in */\n uLong total_in; /* total number of input bytes read so far */\n\n Bytef *next_out; /* next output byte will go here */\n uInt avail_out; /* remaining free space at next_out */\n uLong total_out; /* total number of bytes output so far */\n\n z_const char *msg; /* last error message, NULL if no error */\n struct internal_state FAR *state; /* not visible by applications */\n\n alloc_func zalloc; /* used to allocate the internal state */\n free_func zfree; /* used to free the internal state */\n voidpf opaque; /* private data object passed to zalloc and zfree */\n\n int data_type; /* best guess about the data type: binary or text\n for deflate, or the decoding state for inflate */\n uLong adler; /* Adler-32 or CRC-32 value of the uncompressed data */\n uLong reserved; /* reserved for future use */\n} z_stream;\n\ntypedef z_stream FAR *z_streamp;\n\n/*\n gzip header information passed to and from zlib routines. See RFC 1952\n for more details on the meanings of these fields.\n*/\ntypedef struct gz_header_s {\n int text; /* true if compressed data believed to be text */\n uLong time; /* modification time */\n int xflags; /* extra flags (not used when writing a gzip file) */\n int os; /* operating system */\n Bytef *extra; /* pointer to extra field or Z_NULL if none */\n uInt extra_len; /* extra field length (valid if extra != Z_NULL) */\n uInt extra_max; /* space at extra (only when reading header) */\n Bytef *name; /* pointer to zero-terminated file name or Z_NULL */\n uInt name_max; /* space at name (only when reading header) */\n Bytef *comment; /* pointer to zero-terminated comment or Z_NULL */\n uInt comm_max; /* space at comment (only when reading header) */\n int hcrc; /* true if there was or will be a header crc */\n int done; /* true when done reading gzip header (not used\n when writing a gzip file) */\n} gz_header;\n\ntypedef gz_header FAR *gz_headerp;\n\n/*\n The application must update next_in and avail_in when avail_in has dropped\n to zero. It must update next_out and avail_out when avail_out has dropped\n to zero. The application must initialize zalloc, zfree and opaque before\n calling the init function. All other fields are set by the compression\n library and must not be updated by the application.\n\n The opaque value provided by the application will be passed as the first\n parameter for calls of zalloc and zfree. This can be useful for custom\n memory management. The compression library attaches no meaning to the\n opaque value.\n\n zalloc must return Z_NULL if there is not enough memory for the object.\n If zlib is used in a multi-threaded application, zalloc and zfree must be\n thread safe. In that case, zlib is thread-safe. When zalloc and zfree are\n Z_NULL on entry to the initialization function, they are set to internal\n routines that use the standard library functions malloc() and free().\n\n On 16-bit systems, the functions zalloc and zfree must be able to allocate\n exactly 65536 bytes, but will not be required to allocate more than this if\n the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS, pointers\n returned by zalloc for objects of exactly 65536 bytes *must* have their\n offset normalized to zero. The default allocation function provided by this\n library ensures this (see zutil.c). To reduce memory requirements and avoid\n any allocation of 64K objects, at the expense of compression ratio, compile\n the library with -DMAX_WBITS=14 (see zconf.h).\n\n The fields total_in and total_out can be used for statistics or progress\n reports. After compression, total_in holds the total size of the\n uncompressed data and may be saved for use by the decompressor (particularly\n if the decompressor wants to decompress everything in a single step).\n*/\n\n /* constants */\n\n#define Z_NO_FLUSH 0\n#define Z_PARTIAL_FLUSH 1\n#define Z_SYNC_FLUSH 2\n#define Z_FULL_FLUSH 3\n#define Z_FINISH 4\n#define Z_BLOCK 5\n#define Z_TREES 6\n/* Allowed flush values; see deflate() and inflate() below for details */\n\n#define Z_OK 0\n#define Z_STREAM_END 1\n#define Z_NEED_DICT 2\n#define Z_ERRNO (-1)\n#define Z_STREAM_ERROR (-2)\n#define Z_DATA_ERROR (-3)\n#define Z_MEM_ERROR (-4)\n#define Z_BUF_ERROR (-5)\n#define Z_VERSION_ERROR (-6)\n/* Return codes for the compression/decompression functions. Negative values\n * are errors, positive values are used for special but normal events.\n */\n\n#define Z_NO_COMPRESSION 0\n#define Z_BEST_SPEED 1\n#define Z_BEST_COMPRESSION 9\n#define Z_DEFAULT_COMPRESSION (-1)\n/* compression levels */\n\n#define Z_FILTERED 1\n#define Z_HUFFMAN_ONLY 2\n#define Z_RLE 3\n#define Z_FIXED 4\n#define Z_DEFAULT_STRATEGY 0\n/* compression strategy; see deflateInit2() below for details */\n\n#define Z_BINARY 0\n#define Z_TEXT 1\n#define Z_ASCII Z_TEXT /* for compatibility with 1.2.2 and earlier */\n#define Z_UNKNOWN 2\n/* Possible values of the data_type field for deflate() */\n\n#define Z_DEFLATED 8\n/* The deflate compression method (the only one supported in this version) */\n\n#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */\n\n#define zlib_version zlibVersion()\n/* for compatibility with versions < 1.0.2 */\n\n\n /* basic functions */\n\nZEXTERN const char * ZEXPORT zlibVersion(void);\n/* The application can compare zlibVersion and ZLIB_VERSION for consistency.\n If the first character differs, the library code actually used is not\n compatible with the zlib.h header file used by the application. This check\n is automatically made by deflateInit and inflateInit.\n */\n\n/*\nZEXTERN int ZEXPORT deflateInit(z_streamp strm, int level);\n\n Initializes the internal stream state for compression. The fields\n zalloc, zfree and opaque must be initialized before by the caller. If\n zalloc and zfree are set to Z_NULL, deflateInit updates them to use default\n allocation functions. total_in, total_out, adler, and msg are initialized.\n\n The compression level must be Z_DEFAULT_COMPRESSION, or between 0 and 9:\n 1 gives best speed, 9 gives best compression, 0 gives no compression at all\n (the input data is simply copied a block at a time). Z_DEFAULT_COMPRESSION\n requests a default compromise between speed and compression (currently\n equivalent to level 6).\n\n deflateInit returns Z_OK if success, Z_MEM_ERROR if there was not enough\n memory, Z_STREAM_ERROR if level is not a valid compression level, or\n Z_VERSION_ERROR if the zlib library version (zlib_version) is incompatible\n with the version assumed by the caller (ZLIB_VERSION). msg is set to null\n if there is no error message. deflateInit does not perform any compression:\n this will be done by deflate().\n*/\n\n\nZEXTERN int ZEXPORT deflate(z_streamp strm, int flush);\n/*\n deflate compresses as much data as possible, and stops when the input\n buffer becomes empty or the output buffer becomes full. It may introduce\n some output latency (reading input without producing any output) except when\n forced to flush.\n\n The detailed semantics are as follows. deflate performs one or both of the\n following actions:\n\n - Compress more input starting at next_in and update next_in and avail_in\n accordingly. If not all input can be processed (because there is not\n enough room in the output buffer), next_in and avail_in are updated and\n processing will resume at this point for the next call of deflate().\n\n - Generate more output starting at next_out and update next_out and avail_out\n accordingly. This action is forced if the parameter flush is non zero.\n Forcing flush frequently degrades the compression ratio, so this parameter\n should be set only when necessary. Some output may be provided even if\n flush is zero.\n\n Before the call of deflate(), the application should ensure that at least\n one of the actions is possible, by providing more input and/or consuming more\n output, and updating avail_in or avail_out accordingly; avail_out should\n never be zero before the call. The application can consume the compressed\n output when it wants, for example when the output buffer is full (avail_out\n == 0), or after each call of deflate(). If deflate returns Z_OK and with\n zero avail_out, it must be called again after making room in the output\n buffer because there might be more output pending. See deflatePending(),\n which can be used if desired to determine whether or not there is more output\n in that case.\n\n Normally the parameter flush is set to Z_NO_FLUSH, which allows deflate to\n decide how much data to accumulate before producing output, in order to\n maximize compression.\n\n If the parameter flush is set to Z_SYNC_FLUSH, all pending output is\n flushed to the output buffer and the output is aligned on a byte boundary, so\n that the decompressor can get all input data available so far. (In\n particular avail_in is zero after the call if enough output space has been\n provided before the call.) Flushing may degrade compression for some\n compression algorithms and so it should be used only when necessary. This\n completes the current deflate block and follows it with an empty stored block\n that is three bits plus filler bits to the next byte, followed by four bytes\n (00 00 ff ff).\n\n If flush is set to Z_PARTIAL_FLUSH, all pending output is flushed to the\n output buffer, but the output is not aligned to a byte boundary. All of the\n input data so far will be available to the decompressor, as for Z_SYNC_FLUSH.\n This completes the current deflate block and follows it with an empty fixed\n codes block that is 10 bits long. This assures that enough bytes are output\n in order for the decompressor to finish the block before the empty fixed\n codes block.\n\n If flush is set to Z_BLOCK, a deflate block is completed and emitted, as\n for Z_SYNC_FLUSH, but the output is not aligned on a byte boundary, and up to\n seven bits of the current block are held to be written as the next byte after\n the next deflate block is completed. In this case, the decompressor may not\n be provided enough bits at this point in order to complete decompression of\n the data provided so far to the compressor. It may need to wait for the next\n block to be emitted. This is for advanced applications that need to control\n the emission of deflate blocks.\n\n If flush is set to Z_FULL_FLUSH, all output is flushed as with\n Z_SYNC_FLUSH, and the compression state is reset so that decompression can\n restart from this point if previous compressed data has been damaged or if\n random access is desired. Using Z_FULL_FLUSH too often can seriously degrade\n compression.\n\n If deflate returns with avail_out == 0, this function must be called again\n with the same value of the flush parameter and more output space (updated\n avail_out), until the flush is complete (deflate returns with non-zero\n avail_out). In the case of a Z_FULL_FLUSH or Z_SYNC_FLUSH, make sure that\n avail_out is greater than six when the flush marker begins, in order to avoid\n repeated flush markers upon calling deflate() again when avail_out == 0.\n\n If the parameter flush is set to Z_FINISH, pending input is processed,\n pending output is flushed and deflate returns with Z_STREAM_END if there was\n enough output space. If deflate returns with Z_OK or Z_BUF_ERROR, this\n function must be called again with Z_FINISH and more output space (updated\n avail_out) but no more input data, until it returns with Z_STREAM_END or an\n error. After deflate has returned Z_STREAM_END, the only possible operations\n on the stream are deflateReset or deflateEnd.\n\n Z_FINISH can be used in the first deflate call after deflateInit if all the\n compression is to be done in a single step. In order to complete in one\n call, avail_out must be at least the value returned by deflateBound (see\n below). Then deflate is guaranteed to return Z_STREAM_END. If not enough\n output space is provided, deflate will not return Z_STREAM_END, and it must\n be called again as described above.\n\n deflate() sets strm->adler to the Adler-32 checksum of all input read\n so far (that is, total_in bytes). If a gzip stream is being generated, then\n strm->adler will be the CRC-32 checksum of the input read so far. (See\n deflateInit2 below.)\n\n deflate() may update strm->data_type if it can make a good guess about\n the input data type (Z_BINARY or Z_TEXT). If in doubt, the data is\n considered binary. This field is only for information purposes and does not\n affect the compression algorithm in any manner.\n\n deflate() returns Z_OK if some progress has been made (more input\n processed or more output produced), Z_STREAM_END if all input has been\n consumed and all output has been produced (only when flush is set to\n Z_FINISH), Z_STREAM_ERROR if the stream state was inconsistent (for example\n if next_in or next_out was Z_NULL or the state was inadvertently written over\n by the application), or Z_BUF_ERROR if no progress is possible (for example\n avail_in or avail_out was zero). Note that Z_BUF_ERROR is not fatal, and\n deflate() can be called again with more input and more output space to\n continue compressing.\n*/\n\n\nZEXTERN int ZEXPORT deflateEnd(z_streamp strm);\n/*\n All dynamically allocated data structures for this stream are freed.\n This function discards any unprocessed input and does not flush any pending\n output.\n\n deflateEnd returns Z_OK if success, Z_STREAM_ERROR if the\n stream state was inconsistent, Z_DATA_ERROR if the stream was freed\n prematurely (some input or output was discarded). In the error case, msg\n may be set but then points to a static string (which must not be\n deallocated).\n*/\n\n\n/*\nZEXTERN int ZEXPORT inflateInit(z_streamp strm);\n\n Initializes the internal stream state for decompression. The fields\n next_in, avail_in, zalloc, zfree and opaque must be initialized before by\n the caller. In the current version of inflate, the provided input is not\n read or consumed. The allocation of a sliding window will be deferred to\n the first call of inflate (if the decompression does not complete on the\n first call). If zalloc and zfree are set to Z_NULL, inflateInit updates\n them to use default allocation functions. total_in, total_out, adler, and\n msg are initialized.\n\n inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not enough\n memory, Z_VERSION_ERROR if the zlib library version is incompatible with the\n version assumed by the caller, or Z_STREAM_ERROR if the parameters are\n invalid, such as a null pointer to the structure. msg is set to null if\n there is no error message. inflateInit does not perform any decompression.\n Actual decompression will be done by inflate(). So next_in, and avail_in,\n next_out, and avail_out are unused and unchanged. The current\n implementation of inflateInit() does not process any header information --\n that is deferred until inflate() is called.\n*/\n\n\nZEXTERN int ZEXPORT inflate(z_streamp strm, int flush);\n/*\n inflate decompresses as much data as possible, and stops when the input\n buffer becomes empty or the output buffer becomes full. It may introduce\n some output latency (reading input without producing any output) except when\n forced to flush.\n\n The detailed semantics are as follows. inflate performs one or both of the\n following actions:\n\n - Decompress more input starting at next_in and update next_in and avail_in\n accordingly. If not all input can be processed (because there is not\n enough room in the output buffer), then next_in and avail_in are updated\n accordingly, and processing will resume at this point for the next call of\n inflate().\n\n - Generate more output starting at next_out and update next_out and avail_out\n accordingly. inflate() provides as much output as possible, until there is\n no more input data or no more space in the output buffer (see below about\n the flush parameter).\n\n Before the call of inflate(), the application should ensure that at least\n one of the actions is possible, by providing more input and/or consuming more\n output, and updating the next_* and avail_* values accordingly. If the\n caller of inflate() does not provide both available input and available\n output space, it is possible that there will be no progress made. The\n application can consume the uncompressed output when it wants, for example\n when the output buffer is full (avail_out == 0), or after each call of\n inflate(). If inflate returns Z_OK and with zero avail_out, it must be\n called again after making room in the output buffer because there might be\n more output pending.\n\n The flush parameter of inflate() can be Z_NO_FLUSH, Z_SYNC_FLUSH, Z_FINISH,\n Z_BLOCK, or Z_TREES. Z_SYNC_FLUSH requests that inflate() flush as much\n output as possible to the output buffer. Z_BLOCK requests that inflate()\n stop if and when it gets to the next deflate block boundary. When decoding\n the zlib or gzip format, this will cause inflate() to return immediately\n after the header and before the first block. When doing a raw inflate,\n inflate() will go ahead and process the first block, and will return when it\n gets to the end of that block, or when it runs out of data.\n\n The Z_BLOCK option assists in appending to or combining deflate streams.\n To assist in this, on return inflate() always sets strm->data_type to the\n number of unused bits in the last byte taken from strm->next_in, plus 64 if\n inflate() is currently decoding the last block in the deflate stream, plus\n 128 if inflate() returned immediately after decoding an end-of-block code or\n decoding the complete header up to just before the first byte of the deflate\n stream. The end-of-block will not be indicated until all of the uncompressed\n data from that block has been written to strm->next_out. The number of\n unused bits may in general be greater than seven, except when bit 7 of\n data_type is set, in which case the number of unused bits will be less than\n eight. data_type is set as noted here every time inflate() returns for all\n flush options, and so can be used to determine the amount of currently\n consumed input in bits.\n\n The Z_TREES option behaves as Z_BLOCK does, but it also returns when the\n end of each deflate block header is reached, before any actual data in that\n block is decoded. This allows the caller to determine the length of the\n deflate block header for later use in random access within a deflate block.\n 256 is added to the value of strm->data_type when inflate() returns\n immediately after reaching the end of the deflate block header.\n\n inflate() should normally be called until it returns Z_STREAM_END or an\n error. However if all decompression is to be performed in a single step (a\n single call of inflate), the parameter flush should be set to Z_FINISH. In\n this case all pending input is processed and all pending output is flushed;\n avail_out must be large enough to hold all of the uncompressed data for the\n operation to complete. (The size of the uncompressed data may have been\n saved by the compressor for this purpose.) The use of Z_FINISH is not\n required to perform an inflation in one step. However it may be used to\n inform inflate that a faster approach can be used for the single inflate()\n call. Z_FINISH also informs inflate to not maintain a sliding window if the\n stream completes, which reduces inflate's memory footprint. If the stream\n does not complete, either because not all of the stream is provided or not\n enough output space is provided, then a sliding window will be allocated and\n inflate() can be called again to continue the operation as if Z_NO_FLUSH had\n been used.\n\n In this implementation, inflate() always flushes as much output as\n possible to the output buffer, and always uses the faster approach on the\n first call. So the effects of the flush parameter in this implementation are\n on the return value of inflate() as noted below, when inflate() returns early\n when Z_BLOCK or Z_TREES is used, and when inflate() avoids the allocation of\n memory for a sliding window when Z_FINISH is used.\n\n If a preset dictionary is needed after this call (see inflateSetDictionary\n below), inflate sets strm->adler to the Adler-32 checksum of the dictionary\n chosen by the compressor and returns Z_NEED_DICT; otherwise it sets\n strm->adler to the Adler-32 checksum of all output produced so far (that is,\n total_out bytes) and returns Z_OK, Z_STREAM_END or an error code as described\n below. At the end of the stream, inflate() checks that its computed Adler-32\n checksum is equal to that saved by the compressor and returns Z_STREAM_END\n only if the checksum is correct.\n\n inflate() can decompress and check either zlib-wrapped or gzip-wrapped\n deflate data. The header type is detected automatically, if requested when\n initializing with inflateInit2(). Any information contained in the gzip\n header is not retained unless inflateGetHeader() is used. When processing\n gzip-wrapped deflate data, strm->adler32 is set to the CRC-32 of the output\n produced so far. The CRC-32 is checked against the gzip trailer, as is the\n uncompressed length, modulo 2^32.\n\n inflate() returns Z_OK if some progress has been made (more input processed\n or more output produced), Z_STREAM_END if the end of the compressed data has\n been reached and all uncompressed output has been produced, Z_NEED_DICT if a\n preset dictionary is needed at this point, Z_DATA_ERROR if the input data was\n corrupted (input stream not conforming to the zlib format or incorrect check\n value, in which case strm->msg points to a string with a more specific\n error), Z_STREAM_ERROR if the stream structure was inconsistent (for example\n next_in or next_out was Z_NULL, or the state was inadvertently written over\n by the application), Z_MEM_ERROR if there was not enough memory, Z_BUF_ERROR\n if no progress was possible or if there was not enough room in the output\n buffer when Z_FINISH is used. Note that Z_BUF_ERROR is not fatal, and\n inflate() can be called again with more input and more output space to\n continue decompressing. If Z_DATA_ERROR is returned, the application may\n then call inflateSync() to look for a good compression block if a partial\n recovery of the data is to be attempted.\n*/\n\n\nZEXTERN int ZEXPORT inflateEnd(z_streamp strm);\n/*\n All dynamically allocated data structures for this stream are freed.\n This function discards any unprocessed input and does not flush any pending\n output.\n\n inflateEnd returns Z_OK if success, or Z_STREAM_ERROR if the stream state\n was inconsistent.\n*/\n\n\n /* Advanced functions */\n\n/*\n The following functions are needed only in some special applications.\n*/\n\n/*\nZEXTERN int ZEXPORT deflateInit2(z_streamp strm,\n int level,\n int method,\n int windowBits,\n int memLevel,\n int strategy);\n\n This is another version of deflateInit with more compression options. The\n fields zalloc, zfree and opaque must be initialized before by the caller.\n\n The method parameter is the compression method. It must be Z_DEFLATED in\n this version of the library.\n\n The windowBits parameter is the base two logarithm of the window size\n (the size of the history buffer). It should be in the range 8..15 for this\n version of the library. Larger values of this parameter result in better\n compression at the expense of memory usage. The default value is 15 if\n deflateInit is used instead.\n\n For the current implementation of deflate(), a windowBits value of 8 (a\n window size of 256 bytes) is not supported. As a result, a request for 8\n will result in 9 (a 512-byte window). In that case, providing 8 to\n inflateInit2() will result in an error when the zlib header with 9 is\n checked against the initialization of inflate(). The remedy is to not use 8\n with deflateInit2() with this initialization, or at least in that case use 9\n with inflateInit2().\n\n windowBits can also be -8..-15 for raw deflate. In this case, -windowBits\n determines the window size. deflate() will then generate raw deflate data\n with no zlib header or trailer, and will not compute a check value.\n\n windowBits can also be greater than 15 for optional gzip encoding. Add\n 16 to windowBits to write a simple gzip header and trailer around the\n compressed data instead of a zlib wrapper. The gzip header will have no\n file name, no extra data, no comment, no modification time (set to zero), no\n header crc, and the operating system will be set to the appropriate value,\n if the operating system was determined at compile time. If a gzip stream is\n being written, strm->adler is a CRC-32 instead of an Adler-32.\n\n For raw deflate or gzip encoding, a request for a 256-byte window is\n rejected as invalid, since only the zlib header provides a means of\n transmitting the window size to the decompressor.\n\n The memLevel parameter specifies how much memory should be allocated\n for the internal compression state. memLevel=1 uses minimum memory but is\n slow and reduces compression ratio; memLevel=9 uses maximum memory for\n optimal speed. The default value is 8. See zconf.h for total memory usage\n as a function of windowBits and memLevel.\n\n The strategy parameter is used to tune the compression algorithm. Use the\n value Z_DEFAULT_STRATEGY for normal data, Z_FILTERED for data produced by a\n filter (or predictor), Z_HUFFMAN_ONLY to force Huffman encoding only (no\n string match), or Z_RLE to limit match distances to one (run-length\n encoding). Filtered data consists mostly of small values with a somewhat\n random distribution. In this case, the compression algorithm is tuned to\n compress them better. The effect of Z_FILTERED is to force more Huffman\n coding and less string matching; it is somewhat intermediate between\n Z_DEFAULT_STRATEGY and Z_HUFFMAN_ONLY. Z_RLE is designed to be almost as\n fast as Z_HUFFMAN_ONLY, but give better compression for PNG image data. The\n strategy parameter only affects the compression ratio but not the\n correctness of the compressed output even if it is not set appropriately.\n Z_FIXED prevents the use of dynamic Huffman codes, allowing for a simpler\n decoder for special applications.\n\n deflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough\n memory, Z_STREAM_ERROR if any parameter is invalid (such as an invalid\n method), or Z_VERSION_ERROR if the zlib library version (zlib_version) is\n incompatible with the version assumed by the caller (ZLIB_VERSION). msg is\n set to null if there is no error message. deflateInit2 does not perform any\n compression: this will be done by deflate().\n*/\n\nZEXTERN int ZEXPORT deflateSetDictionary(z_streamp strm,\n const Bytef *dictionary,\n uInt dictLength);\n/*\n Initializes the compression dictionary from the given byte sequence\n without producing any compressed output. When using the zlib format, this\n function must be called immediately after deflateInit, deflateInit2 or\n deflateReset, and before any call of deflate. When doing raw deflate, this\n function must be called either before any call of deflate, or immediately\n after the completion of a deflate block, i.e. after all input has been\n consumed and all output has been delivered when using any of the flush\n options Z_BLOCK, Z_PARTIAL_FLUSH, Z_SYNC_FLUSH, or Z_FULL_FLUSH. The\n compressor and decompressor must use exactly the same dictionary (see\n inflateSetDictionary).\n\n The dictionary should consist of strings (byte sequences) that are likely\n to be encountered later in the data to be compressed, with the most commonly\n used strings preferably put towards the end of the dictionary. Using a\n dictionary is most useful when the data to be compressed is short and can be\n predicted with good accuracy; the data can then be compressed better than\n with the default empty dictionary.\n\n Depending on the size of the compression data structures selected by\n deflateInit or deflateInit2, a part of the dictionary may in effect be\n discarded, for example if the dictionary is larger than the window size\n provided in deflateInit or deflateInit2. Thus the strings most likely to be\n useful should be put at the end of the dictionary, not at the front. In\n addition, the current implementation of deflate will use at most the window\n size minus 262 bytes of the provided dictionary.\n\n Upon return of this function, strm->adler is set to the Adler-32 value\n of the dictionary; the decompressor may later use this value to determine\n which dictionary has been used by the compressor. (The Adler-32 value\n applies to the whole dictionary even if only a subset of the dictionary is\n actually used by the compressor.) If a raw deflate was requested, then the\n Adler-32 value is not computed and strm->adler is not set.\n\n deflateSetDictionary returns Z_OK if success, or Z_STREAM_ERROR if a\n parameter is invalid (e.g. dictionary being Z_NULL) or the stream state is\n inconsistent (for example if deflate has already been called for this stream\n or if not at a block boundary for raw deflate). deflateSetDictionary does\n not perform any compression: this will be done by deflate().\n*/\n\nZEXTERN int ZEXPORT deflateGetDictionary(z_streamp strm,\n Bytef *dictionary,\n uInt *dictLength);\n/*\n Returns the sliding dictionary being maintained by deflate. dictLength is\n set to the number of bytes in the dictionary, and that many bytes are copied\n to dictionary. dictionary must have enough space, where 32768 bytes is\n always enough. If deflateGetDictionary() is called with dictionary equal to\n Z_NULL, then only the dictionary length is returned, and nothing is copied.\n Similarly, if dictLength is Z_NULL, then it is not set.\n\n deflateGetDictionary() may return a length less than the window size, even\n when more than the window size in input has been provided. It may return up\n to 258 bytes less in that case, due to how zlib's implementation of deflate\n manages the sliding window and lookahead for matches, where matches can be\n up to 258 bytes long. If the application needs the last window-size bytes of\n input, then that would need to be saved by the application outside of zlib.\n\n deflateGetDictionary returns Z_OK on success, or Z_STREAM_ERROR if the\n stream state is inconsistent.\n*/\n\nZEXTERN int ZEXPORT deflateCopy(z_streamp dest,\n z_streamp source);\n/*\n Sets the destination stream as a complete copy of the source stream.\n\n This function can be useful when several compression strategies will be\n tried, for example when there are several ways of pre-processing the input\n data with a filter. The streams that will be discarded should then be freed\n by calling deflateEnd. Note that deflateCopy duplicates the internal\n compression state which can be quite large, so this strategy is slow and can\n consume lots of memory.\n\n deflateCopy returns Z_OK if success, Z_MEM_ERROR if there was not\n enough memory, Z_STREAM_ERROR if the source stream state was inconsistent\n (such as zalloc being Z_NULL). msg is left unchanged in both source and\n destination.\n*/\n\nZEXTERN int ZEXPORT deflateReset(z_streamp strm);\n/*\n This function is equivalent to deflateEnd followed by deflateInit, but\n does not free and reallocate the internal compression state. The stream\n will leave the compression level and any other attributes that may have been\n set unchanged. total_in, total_out, adler, and msg are initialized.\n\n deflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent (such as zalloc or state being Z_NULL).\n*/\n\nZEXTERN int ZEXPORT deflateParams(z_streamp strm,\n int level,\n int strategy);\n/*\n Dynamically update the compression level and compression strategy. The\n interpretation of level and strategy is as in deflateInit2(). This can be\n used to switch between compression and straight copy of the input data, or\n to switch to a different kind of input data requiring a different strategy.\n If the compression approach (which is a function of the level) or the\n strategy is changed, and if there have been any deflate() calls since the\n state was initialized or reset, then the input available so far is\n compressed with the old level and strategy using deflate(strm, Z_BLOCK).\n There are three approaches for the compression levels 0, 1..3, and 4..9\n respectively. The new level and strategy will take effect at the next call\n of deflate().\n\n If a deflate(strm, Z_BLOCK) is performed by deflateParams(), and it does\n not have enough output space to complete, then the parameter change will not\n take effect. In this case, deflateParams() can be called again with the\n same parameters and more output space to try again.\n\n In order to assure a change in the parameters on the first try, the\n deflate stream should be flushed using deflate() with Z_BLOCK or other flush\n request until strm.avail_out is not zero, before calling deflateParams().\n Then no more input data should be provided before the deflateParams() call.\n If this is done, the old level and strategy will be applied to the data\n compressed before deflateParams(), and the new level and strategy will be\n applied to the data compressed after deflateParams().\n\n deflateParams returns Z_OK on success, Z_STREAM_ERROR if the source stream\n state was inconsistent or if a parameter was invalid, or Z_BUF_ERROR if\n there was not enough output space to complete the compression of the\n available input data before a change in the strategy or approach. Note that\n in the case of a Z_BUF_ERROR, the parameters are not changed. A return\n value of Z_BUF_ERROR is not fatal, in which case deflateParams() can be\n retried with more output space.\n*/\n\nZEXTERN int ZEXPORT deflateTune(z_streamp strm,\n int good_length,\n int max_lazy,\n int nice_length,\n int max_chain);\n/*\n Fine tune deflate's internal compression parameters. This should only be\n used by someone who understands the algorithm used by zlib's deflate for\n searching for the best matching string, and even then only by the most\n fanatic optimizer trying to squeeze out the last compressed bit for their\n specific input data. Read the deflate.c source code for the meaning of the\n max_lazy, good_length, nice_length, and max_chain parameters.\n\n deflateTune() can be called after deflateInit() or deflateInit2(), and\n returns Z_OK on success, or Z_STREAM_ERROR for an invalid deflate stream.\n */\n\nZEXTERN uLong ZEXPORT deflateBound(z_streamp strm,\n uLong sourceLen);\n/*\n deflateBound() returns an upper bound on the compressed size after\n deflation of sourceLen bytes. It must be called after deflateInit() or\n deflateInit2(), and after deflateSetHeader(), if used. This would be used\n to allocate an output buffer for deflation in a single pass, and so would be\n called before deflate(). If that first deflate() call is provided the\n sourceLen input bytes, an output buffer allocated to the size returned by\n deflateBound(), and the flush value Z_FINISH, then deflate() is guaranteed\n to return Z_STREAM_END. Note that it is possible for the compressed size to\n be larger than the value returned by deflateBound() if flush options other\n than Z_FINISH or Z_NO_FLUSH are used.\n*/\n\nZEXTERN int ZEXPORT deflatePending(z_streamp strm,\n unsigned *pending,\n int *bits);\n/*\n deflatePending() returns the number of bytes and bits of output that have\n been generated, but not yet provided in the available output. The bytes not\n provided would be due to the available output space having being consumed.\n The number of bits of output not provided are between 0 and 7, where they\n await more bits to join them in order to fill out a full byte. If pending\n or bits are Z_NULL, then those values are not set.\n\n deflatePending returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent.\n */\n\nZEXTERN int ZEXPORT deflatePrime(z_streamp strm,\n int bits,\n int value);\n/*\n deflatePrime() inserts bits in the deflate output stream. The intent\n is that this function is used to start off the deflate output with the bits\n leftover from a previous deflate stream when appending to it. As such, this\n function can only be used for raw deflate, and must be used before the first\n deflate() call after a deflateInit2() or deflateReset(). bits must be less\n than or equal to 16, and that many of the least significant bits of value\n will be inserted in the output.\n\n deflatePrime returns Z_OK if success, Z_BUF_ERROR if there was not enough\n room in the internal buffer to insert the bits, or Z_STREAM_ERROR if the\n source stream state was inconsistent.\n*/\n\nZEXTERN int ZEXPORT deflateSetHeader(z_streamp strm,\n gz_headerp head);\n/*\n deflateSetHeader() provides gzip header information for when a gzip\n stream is requested by deflateInit2(). deflateSetHeader() may be called\n after deflateInit2() or deflateReset() and before the first call of\n deflate(). The text, time, os, extra field, name, and comment information\n in the provided gz_header structure are written to the gzip header (xflag is\n ignored -- the extra flags are set according to the compression level). The\n caller must assure that, if not Z_NULL, name and comment are terminated with\n a zero byte, and that if extra is not Z_NULL, that extra_len bytes are\n available there. If hcrc is true, a gzip header crc is included. Note that\n the current versions of the command-line version of gzip (up through version\n 1.3.x) do not support header crc's, and will report that it is a \"multi-part\n gzip file\" and give up.\n\n If deflateSetHeader is not used, the default gzip header has text false,\n the time set to zero, and os set to the current operating system, with no\n extra, name, or comment fields. The gzip header is returned to the default\n state by deflateReset().\n\n deflateSetHeader returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent.\n*/\n\n/*\nZEXTERN int ZEXPORT inflateInit2(z_streamp strm,\n int windowBits);\n\n This is another version of inflateInit with an extra parameter. The\n fields next_in, avail_in, zalloc, zfree and opaque must be initialized\n before by the caller.\n\n The windowBits parameter is the base two logarithm of the maximum window\n size (the size of the history buffer). It should be in the range 8..15 for\n this version of the library. The default value is 15 if inflateInit is used\n instead. windowBits must be greater than or equal to the windowBits value\n provided to deflateInit2() while compressing, or it must be equal to 15 if\n deflateInit2() was not used. If a compressed stream with a larger window\n size is given as input, inflate() will return with the error code\n Z_DATA_ERROR instead of trying to allocate a larger window.\n\n windowBits can also be zero to request that inflate use the window size in\n the zlib header of the compressed stream.\n\n windowBits can also be -8..-15 for raw inflate. In this case, -windowBits\n determines the window size. inflate() will then process raw deflate data,\n not looking for a zlib or gzip header, not generating a check value, and not\n looking for any check values for comparison at the end of the stream. This\n is for use with other formats that use the deflate compressed data format\n such as zip. Those formats provide their own check values. If a custom\n format is developed using the raw deflate format for compressed data, it is\n recommended that a check value such as an Adler-32 or a CRC-32 be applied to\n the uncompressed data as is done in the zlib, gzip, and zip formats. For\n most applications, the zlib format should be used as is. Note that comments\n above on the use in deflateInit2() applies to the magnitude of windowBits.\n\n windowBits can also be greater than 15 for optional gzip decoding. Add\n 32 to windowBits to enable zlib and gzip decoding with automatic header\n detection, or add 16 to decode only the gzip format (the zlib format will\n return a Z_DATA_ERROR). If a gzip stream is being decoded, strm->adler is a\n CRC-32 instead of an Adler-32. Unlike the gunzip utility and gzread() (see\n below), inflate() will *not* automatically decode concatenated gzip members.\n inflate() will return Z_STREAM_END at the end of the gzip member. The state\n would need to be reset to continue decoding a subsequent gzip member. This\n *must* be done if there is more data after a gzip member, in order for the\n decompression to be compliant with the gzip standard (RFC 1952).\n\n inflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough\n memory, Z_VERSION_ERROR if the zlib library version is incompatible with the\n version assumed by the caller, or Z_STREAM_ERROR if the parameters are\n invalid, such as a null pointer to the structure. msg is set to null if\n there is no error message. inflateInit2 does not perform any decompression\n apart from possibly reading the zlib header if present: actual decompression\n will be done by inflate(). (So next_in and avail_in may be modified, but\n next_out and avail_out are unused and unchanged.) The current implementation\n of inflateInit2() does not process any header information -- that is\n deferred until inflate() is called.\n*/\n\nZEXTERN int ZEXPORT inflateSetDictionary(z_streamp strm,\n const Bytef *dictionary,\n uInt dictLength);\n/*\n Initializes the decompression dictionary from the given uncompressed byte\n sequence. This function must be called immediately after a call of inflate,\n if that call returned Z_NEED_DICT. The dictionary chosen by the compressor\n can be determined from the Adler-32 value returned by that call of inflate.\n The compressor and decompressor must use exactly the same dictionary (see\n deflateSetDictionary). For raw inflate, this function can be called at any\n time to set the dictionary. If the provided dictionary is smaller than the\n window and there is already data in the window, then the provided dictionary\n will amend what's there. The application must insure that the dictionary\n that was used for compression is provided.\n\n inflateSetDictionary returns Z_OK if success, Z_STREAM_ERROR if a\n parameter is invalid (e.g. dictionary being Z_NULL) or the stream state is\n inconsistent, Z_DATA_ERROR if the given dictionary doesn't match the\n expected one (incorrect Adler-32 value). inflateSetDictionary does not\n perform any decompression: this will be done by subsequent calls of\n inflate().\n*/\n\nZEXTERN int ZEXPORT inflateGetDictionary(z_streamp strm,\n Bytef *dictionary,\n uInt *dictLength);\n/*\n Returns the sliding dictionary being maintained by inflate. dictLength is\n set to the number of bytes in the dictionary, and that many bytes are copied\n to dictionary. dictionary must have enough space, where 32768 bytes is\n always enough. If inflateGetDictionary() is called with dictionary equal to\n Z_NULL, then only the dictionary length is returned, and nothing is copied.\n Similarly, if dictLength is Z_NULL, then it is not set.\n\n inflateGetDictionary returns Z_OK on success, or Z_STREAM_ERROR if the\n stream state is inconsistent.\n*/\n\nZEXTERN int ZEXPORT inflateSync(z_streamp strm);\n/*\n Skips invalid compressed data until a possible full flush point (see above\n for the description of deflate with Z_FULL_FLUSH) can be found, or until all\n available input is skipped. No output is provided.\n\n inflateSync searches for a 00 00 FF FF pattern in the compressed data.\n All full flush points have this pattern, but not all occurrences of this\n pattern are full flush points.\n\n inflateSync returns Z_OK if a possible full flush point has been found,\n Z_BUF_ERROR if no more input was provided, Z_DATA_ERROR if no flush point\n has been found, or Z_STREAM_ERROR if the stream structure was inconsistent.\n In the success case, the application may save the current value of total_in\n which indicates where valid compressed data was found. In the error case,\n the application may repeatedly call inflateSync, providing more input each\n time, until success or end of the input data.\n*/\n\nZEXTERN int ZEXPORT inflateCopy(z_streamp dest,\n z_streamp source);\n/*\n Sets the destination stream as a complete copy of the source stream.\n\n This function can be useful when randomly accessing a large stream. The\n first pass through the stream can periodically record the inflate state,\n allowing restarting inflate at those points when randomly accessing the\n stream.\n\n inflateCopy returns Z_OK if success, Z_MEM_ERROR if there was not\n enough memory, Z_STREAM_ERROR if the source stream state was inconsistent\n (such as zalloc being Z_NULL). msg is left unchanged in both source and\n destination.\n*/\n\nZEXTERN int ZEXPORT inflateReset(z_streamp strm);\n/*\n This function is equivalent to inflateEnd followed by inflateInit,\n but does not free and reallocate the internal decompression state. The\n stream will keep attributes that may have been set by inflateInit2.\n total_in, total_out, adler, and msg are initialized.\n\n inflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent (such as zalloc or state being Z_NULL).\n*/\n\nZEXTERN int ZEXPORT inflateReset2(z_streamp strm,\n int windowBits);\n/*\n This function is the same as inflateReset, but it also permits changing\n the wrap and window size requests. The windowBits parameter is interpreted\n the same as it is for inflateInit2. If the window size is changed, then the\n memory allocated for the window is freed, and the window will be reallocated\n by inflate() if needed.\n\n inflateReset2 returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent (such as zalloc or state being Z_NULL), or if\n the windowBits parameter is invalid.\n*/\n\nZEXTERN int ZEXPORT inflatePrime(z_streamp strm,\n int bits,\n int value);\n/*\n This function inserts bits in the inflate input stream. The intent is\n that this function is used to start inflating at a bit position in the\n middle of a byte. The provided bits will be used before any bytes are used\n from next_in. This function should only be used with raw inflate, and\n should be used before the first inflate() call after inflateInit2() or\n inflateReset(). bits must be less than or equal to 16, and that many of the\n least significant bits of value will be inserted in the input.\n\n If bits is negative, then the input stream bit buffer is emptied. Then\n inflatePrime() can be called again to put bits in the buffer. This is used\n to clear out bits leftover after feeding inflate a block description prior\n to feeding inflate codes.\n\n inflatePrime returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent.\n*/\n\nZEXTERN long ZEXPORT inflateMark(z_streamp strm);\n/*\n This function returns two values, one in the lower 16 bits of the return\n value, and the other in the remaining upper bits, obtained by shifting the\n return value down 16 bits. If the upper value is -1 and the lower value is\n zero, then inflate() is currently decoding information outside of a block.\n If the upper value is -1 and the lower value is non-zero, then inflate is in\n the middle of a stored block, with the lower value equaling the number of\n bytes from the input remaining to copy. If the upper value is not -1, then\n it is the number of bits back from the current bit position in the input of\n the code (literal or length/distance pair) currently being processed. In\n that case the lower value is the number of bytes already emitted for that\n code.\n\n A code is being processed if inflate is waiting for more input to complete\n decoding of the code, or if it has completed decoding but is waiting for\n more output space to write the literal or match data.\n\n inflateMark() is used to mark locations in the input data for random\n access, which may be at bit positions, and to note those cases where the\n output of a code may span boundaries of random access blocks. The current\n location in the input stream can be determined from avail_in and data_type\n as noted in the description for the Z_BLOCK flush parameter for inflate.\n\n inflateMark returns the value noted above, or -65536 if the provided\n source stream state was inconsistent.\n*/\n\nZEXTERN int ZEXPORT inflateGetHeader(z_streamp strm,\n gz_headerp head);\n/*\n inflateGetHeader() requests that gzip header information be stored in the\n provided gz_header structure. inflateGetHeader() may be called after\n inflateInit2() or inflateReset(), and before the first call of inflate().\n As inflate() processes the gzip stream, head->done is zero until the header\n is completed, at which time head->done is set to one. If a zlib stream is\n being decoded, then head->done is set to -1 to indicate that there will be\n no gzip header information forthcoming. Note that Z_BLOCK or Z_TREES can be\n used to force inflate() to return immediately after header processing is\n complete and before any actual data is decompressed.\n\n The text, time, xflags, and os fields are filled in with the gzip header\n contents. hcrc is set to true if there is a header CRC. (The header CRC\n was valid if done is set to one.) If extra is not Z_NULL, then extra_max\n contains the maximum number of bytes to write to extra. Once done is true,\n extra_len contains the actual extra field length, and extra contains the\n extra field, or that field truncated if extra_max is less than extra_len.\n If name is not Z_NULL, then up to name_max characters are written there,\n terminated with a zero unless the length is greater than name_max. If\n comment is not Z_NULL, then up to comm_max characters are written there,\n terminated with a zero unless the length is greater than comm_max. When any\n of extra, name, or comment are not Z_NULL and the respective field is not\n present in the header, then that field is set to Z_NULL to signal its\n absence. This allows the use of deflateSetHeader() with the returned\n structure to duplicate the header. However if those fields are set to\n allocated memory, then the application will need to save those pointers\n elsewhere so that they can be eventually freed.\n\n If inflateGetHeader is not used, then the header information is simply\n discarded. The header is always checked for validity, including the header\n CRC if present. inflateReset() will reset the process to discard the header\n information. The application would need to call inflateGetHeader() again to\n retrieve the header from the next gzip stream.\n\n inflateGetHeader returns Z_OK if success, or Z_STREAM_ERROR if the source\n stream state was inconsistent.\n*/\n\n/*\nZEXTERN int ZEXPORT inflateBackInit(z_streamp strm, int windowBits,\n unsigned char FAR *window);\n\n Initialize the internal stream state for decompression using inflateBack()\n calls. The fields zalloc, zfree and opaque in strm must be initialized\n before the call. If zalloc and zfree are Z_NULL, then the default library-\n derived memory allocation routines are used. windowBits is the base two\n logarithm of the window size, in the range 8..15. window is a caller\n supplied buffer of that size. Except for special applications where it is\n assured that deflate was used with small window sizes, windowBits must be 15\n and a 32K byte window must be supplied to be able to decompress general\n deflate streams.\n\n See inflateBack() for the usage of these routines.\n\n inflateBackInit will return Z_OK on success, Z_STREAM_ERROR if any of\n the parameters are invalid, Z_MEM_ERROR if the internal state could not be\n allocated, or Z_VERSION_ERROR if the version of the library does not match\n the version of the header file.\n*/\n\ntypedef unsigned (*in_func)(void FAR *,\n z_const unsigned char FAR * FAR *);\ntypedef int (*out_func)(void FAR *, unsigned char FAR *, unsigned);\n\nZEXTERN int ZEXPORT inflateBack(z_streamp strm,\n in_func in, void FAR *in_desc,\n out_func out, void FAR *out_desc);\n/*\n inflateBack() does a raw inflate with a single call using a call-back\n interface for input and output. This is potentially more efficient than\n inflate() for file i/o applications, in that it avoids copying between the\n output and the sliding window by simply making the window itself the output\n buffer. inflate() can be faster on modern CPUs when used with large\n buffers. inflateBack() trusts the application to not change the output\n buffer passed by the output function, at least until inflateBack() returns.\n\n inflateBackInit() must be called first to allocate the internal state\n and to initialize the state with the user-provided window buffer.\n inflateBack() may then be used multiple times to inflate a complete, raw\n deflate stream with each call. inflateBackEnd() is then called to free the\n allocated state.\n\n A raw deflate stream is one with no zlib or gzip header or trailer.\n This routine would normally be used in a utility that reads zip or gzip\n files and writes out uncompressed files. The utility would decode the\n header and process the trailer on its own, hence this routine expects only\n the raw deflate stream to decompress. This is different from the default\n behavior of inflate(), which expects a zlib header and trailer around the\n deflate stream.\n\n inflateBack() uses two subroutines supplied by the caller that are then\n called by inflateBack() for input and output. inflateBack() calls those\n routines until it reads a complete deflate stream and writes out all of the\n uncompressed data, or until it encounters an error. The function's\n parameters and return types are defined above in the in_func and out_func\n typedefs. inflateBack() will call in(in_desc, &buf) which should return the\n number of bytes of provided input, and a pointer to that input in buf. If\n there is no input available, in() must return zero -- buf is ignored in that\n case -- and inflateBack() will return a buffer error. inflateBack() will\n call out(out_desc, buf, len) to write the uncompressed data buf[0..len-1].\n out() should return zero on success, or non-zero on failure. If out()\n returns non-zero, inflateBack() will return with an error. Neither in() nor\n out() are permitted to change the contents of the window provided to\n inflateBackInit(), which is also the buffer that out() uses to write from.\n The length written by out() will be at most the window size. Any non-zero\n amount of input may be provided by in().\n\n For convenience, inflateBack() can be provided input on the first call by\n setting strm->next_in and strm->avail_in. If that input is exhausted, then\n in() will be called. Therefore strm->next_in must be initialized before\n calling inflateBack(). If strm->next_in is Z_NULL, then in() will be called\n immediately for input. If strm->next_in is not Z_NULL, then strm->avail_in\n must also be initialized, and then if strm->avail_in is not zero, input will\n initially be taken from strm->next_in[0 .. strm->avail_in - 1].\n\n The in_desc and out_desc parameters of inflateBack() is passed as the\n first parameter of in() and out() respectively when they are called. These\n descriptors can be optionally used to pass any information that the caller-\n supplied in() and out() functions need to do their job.\n\n On return, inflateBack() will set strm->next_in and strm->avail_in to\n pass back any unused input that was provided by the last in() call. The\n return values of inflateBack() can be Z_STREAM_END on success, Z_BUF_ERROR\n if in() or out() returned an error, Z_DATA_ERROR if there was a format error\n in the deflate stream (in which case strm->msg is set to indicate the nature\n of the error), or Z_STREAM_ERROR if the stream was not properly initialized.\n In the case of Z_BUF_ERROR, an input or output error can be distinguished\n using strm->next_in which will be Z_NULL only if in() returned an error. If\n strm->next_in is not Z_NULL, then the Z_BUF_ERROR was due to out() returning\n non-zero. (in() will always be called before out(), so strm->next_in is\n assured to be defined if out() returns non-zero.) Note that inflateBack()\n cannot return Z_OK.\n*/\n\nZEXTERN int ZEXPORT inflateBackEnd(z_streamp strm);\n/*\n All memory allocated by inflateBackInit() is freed.\n\n inflateBackEnd() returns Z_OK on success, or Z_STREAM_ERROR if the stream\n state was inconsistent.\n*/\n\nZEXTERN uLong ZEXPORT zlibCompileFlags(void);\n/* Return flags indicating compile-time options.\n\n Type sizes, two bits each, 00 = 16 bits, 01 = 32, 10 = 64, 11 = other:\n 1.0: size of uInt\n 3.2: size of uLong\n 5.4: size of voidpf (pointer)\n 7.6: size of z_off_t\n\n Compiler, assembler, and debug options:\n 8: ZLIB_DEBUG\n 9: ASMV or ASMINF -- use ASM code\n 10: ZLIB_WINAPI -- exported functions use the WINAPI calling convention\n 11: 0 (reserved)\n\n One-time table building (smaller code, but not thread-safe if true):\n 12: BUILDFIXED -- build static block decoding tables when needed\n 13: DYNAMIC_CRC_TABLE -- build CRC calculation tables when needed\n 14,15: 0 (reserved)\n\n Library content (indicates missing functionality):\n 16: NO_GZCOMPRESS -- gz* functions cannot compress (to avoid linking\n deflate code when not needed)\n 17: NO_GZIP -- deflate can't write gzip streams, and inflate can't detect\n and decode gzip streams (to avoid linking crc code)\n 18-19: 0 (reserved)\n\n Operation variations (changes in library functionality):\n 20: PKZIP_BUG_WORKAROUND -- slightly more permissive inflate\n 21: FASTEST -- deflate algorithm with only one, lowest compression level\n 22,23: 0 (reserved)\n\n The sprintf variant used by gzprintf (zero is best):\n 24: 0 = vs*, 1 = s* -- 1 means limited to 20 arguments after the format\n 25: 0 = *nprintf, 1 = *printf -- 1 means gzprintf() not secure!\n 26: 0 = returns value, 1 = void -- 1 means inferred string length returned\n\n Remainder:\n 27-31: 0 (reserved)\n */\n\n#ifndef Z_SOLO\n\n /* utility functions */\n\n/*\n The following utility functions are implemented on top of the basic\n stream-oriented functions. To simplify the interface, some default options\n are assumed (compression level and memory usage, standard memory allocation\n functions). The source code of these utility functions can be modified if\n you need special options.\n*/\n\nZEXTERN int ZEXPORT compress(Bytef *dest, uLongf *destLen,\n const Bytef *source, uLong sourceLen);\n/*\n Compresses the source buffer into the destination buffer. sourceLen is\n the byte length of the source buffer. Upon entry, destLen is the total size\n of the destination buffer, which must be at least the value returned by\n compressBound(sourceLen). Upon exit, destLen is the actual size of the\n compressed data. compress() is equivalent to compress2() with a level\n parameter of Z_DEFAULT_COMPRESSION.\n\n compress returns Z_OK if success, Z_MEM_ERROR if there was not\n enough memory, Z_BUF_ERROR if there was not enough room in the output\n buffer.\n*/\n\nZEXTERN int ZEXPORT compress2(Bytef *dest, uLongf *destLen,\n const Bytef *source, uLong sourceLen,\n int level);\n/*\n Compresses the source buffer into the destination buffer. The level\n parameter has the same meaning as in deflateInit. sourceLen is the byte\n length of the source buffer. Upon entry, destLen is the total size of the\n destination buffer, which must be at least the value returned by\n compressBound(sourceLen). Upon exit, destLen is the actual size of the\n compressed data.\n\n compress2 returns Z_OK if success, Z_MEM_ERROR if there was not enough\n memory, Z_BUF_ERROR if there was not enough room in the output buffer,\n Z_STREAM_ERROR if the level parameter is invalid.\n*/\n\nZEXTERN uLong ZEXPORT compressBound(uLong sourceLen);\n/*\n compressBound() returns an upper bound on the compressed size after\n compress() or compress2() on sourceLen bytes. It would be used before a\n compress() or compress2() call to allocate the destination buffer.\n*/\n\nZEXTERN int ZEXPORT uncompress(Bytef *dest, uLongf *destLen,\n const Bytef *source, uLong sourceLen);\n/*\n Decompresses the source buffer into the destination buffer. sourceLen is\n the byte length of the source buffer. Upon entry, destLen is the total size\n of the destination buffer, which must be large enough to hold the entire\n uncompressed data. (The size of the uncompressed data must have been saved\n previously by the compressor and transmitted to the decompressor by some\n mechanism outside the scope of this compression library.) Upon exit, destLen\n is the actual size of the uncompressed data.\n\n uncompress returns Z_OK if success, Z_MEM_ERROR if there was not\n enough memory, Z_BUF_ERROR if there was not enough room in the output\n buffer, or Z_DATA_ERROR if the input data was corrupted or incomplete. In\n the case where there is not enough room, uncompress() will fill the output\n buffer with the uncompressed data up to that point.\n*/\n\nZEXTERN int ZEXPORT uncompress2(Bytef *dest, uLongf *destLen,\n const Bytef *source, uLong *sourceLen);\n/*\n Same as uncompress, except that sourceLen is a pointer, where the\n length of the source is *sourceLen. On return, *sourceLen is the number of\n source bytes consumed.\n*/\n\n /* gzip file access functions */\n\n/*\n This library supports reading and writing files in gzip (.gz) format with\n an interface similar to that of stdio, using the functions that start with\n \"gz\". The gzip format is different from the zlib format. gzip is a gzip\n wrapper, documented in RFC 1952, wrapped around a deflate stream.\n*/\n\ntypedef struct gzFile_s *gzFile; /* semi-opaque gzip file descriptor */\n\n/*\nZEXTERN gzFile ZEXPORT gzopen(const char *path, const char *mode);\n\n Open the gzip (.gz) file at path for reading and decompressing, or\n compressing and writing. The mode parameter is as in fopen (\"rb\" or \"wb\")\n but can also include a compression level (\"wb9\") or a strategy: 'f' for\n filtered data as in \"wb6f\", 'h' for Huffman-only compression as in \"wb1h\",\n 'R' for run-length encoding as in \"wb1R\", or 'F' for fixed code compression\n as in \"wb9F\". (See the description of deflateInit2 for more information\n about the strategy parameter.) 'T' will request transparent writing or\n appending with no compression and not using the gzip format.\n\n \"a\" can be used instead of \"w\" to request that the gzip stream that will\n be written be appended to the file. \"+\" will result in an error, since\n reading and writing to the same gzip file is not supported. The addition of\n \"x\" when writing will create the file exclusively, which fails if the file\n already exists. On systems that support it, the addition of \"e\" when\n reading or writing will set the flag to close the file on an execve() call.\n\n These functions, as well as gzip, will read and decode a sequence of gzip\n streams in a file. The append function of gzopen() can be used to create\n such a file. (Also see gzflush() for another way to do this.) When\n appending, gzopen does not test whether the file begins with a gzip stream,\n nor does it look for the end of the gzip streams to begin appending. gzopen\n will simply append a gzip stream to the existing file.\n\n gzopen can be used to read a file which is not in gzip format; in this\n case gzread will directly read from the file without decompression. When\n reading, this will be detected automatically by looking for the magic two-\n byte gzip header.\n\n gzopen returns NULL if the file could not be opened, if there was\n insufficient memory to allocate the gzFile state, or if an invalid mode was\n specified (an 'r', 'w', or 'a' was not provided, or '+' was provided).\n errno can be checked to determine if the reason gzopen failed was that the\n file could not be opened.\n*/\n\nZEXTERN gzFile ZEXPORT gzdopen(int fd, const char *mode);\n/*\n Associate a gzFile with the file descriptor fd. File descriptors are\n obtained from calls like open, dup, creat, pipe or fileno (if the file has\n been previously opened with fopen). The mode parameter is as in gzopen.\n\n The next call of gzclose on the returned gzFile will also close the file\n descriptor fd, just like fclose(fdopen(fd, mode)) closes the file descriptor\n fd. If you want to keep fd open, use fd = dup(fd_keep); gz = gzdopen(fd,\n mode);. The duplicated descriptor should be saved to avoid a leak, since\n gzdopen does not close fd if it fails. If you are using fileno() to get the\n file descriptor from a FILE *, then you will have to use dup() to avoid\n double-close()ing the file descriptor. Both gzclose() and fclose() will\n close the associated file descriptor, so they need to have different file\n descriptors.\n\n gzdopen returns NULL if there was insufficient memory to allocate the\n gzFile state, if an invalid mode was specified (an 'r', 'w', or 'a' was not\n provided, or '+' was provided), or if fd is -1. The file descriptor is not\n used until the next gz* read, write, seek, or close operation, so gzdopen\n will not detect if fd is invalid (unless fd is -1).\n*/\n\nZEXTERN int ZEXPORT gzbuffer(gzFile file, unsigned size);\n/*\n Set the internal buffer size used by this library's functions for file to\n size. The default buffer size is 8192 bytes. This function must be called\n after gzopen() or gzdopen(), and before any other calls that read or write\n the file. The buffer memory allocation is always deferred to the first read\n or write. Three times that size in buffer space is allocated. A larger\n buffer size of, for example, 64K or 128K bytes will noticeably increase the\n speed of decompression (reading).\n\n The new buffer size also affects the maximum length for gzprintf().\n\n gzbuffer() returns 0 on success, or -1 on failure, such as being called\n too late.\n*/\n\nZEXTERN int ZEXPORT gzsetparams(gzFile file, int level, int strategy);\n/*\n Dynamically update the compression level and strategy for file. See the\n description of deflateInit2 for the meaning of these parameters. Previously\n provided data is flushed before applying the parameter changes.\n\n gzsetparams returns Z_OK if success, Z_STREAM_ERROR if the file was not\n opened for writing, Z_ERRNO if there is an error writing the flushed data,\n or Z_MEM_ERROR if there is a memory allocation error.\n*/\n\nZEXTERN int ZEXPORT gzread(gzFile file, voidp buf, unsigned len);\n/*\n Read and decompress up to len uncompressed bytes from file into buf. If\n the input file is not in gzip format, gzread copies the given number of\n bytes into the buffer directly from the file.\n\n After reaching the end of a gzip stream in the input, gzread will continue\n to read, looking for another gzip stream. Any number of gzip streams may be\n concatenated in the input file, and will all be decompressed by gzread().\n If something other than a gzip stream is encountered after a gzip stream,\n that remaining trailing garbage is ignored (and no error is returned).\n\n gzread can be used to read a gzip file that is being concurrently written.\n Upon reaching the end of the input, gzread will return with the available\n data. If the error code returned by gzerror is Z_OK or Z_BUF_ERROR, then\n gzclearerr can be used to clear the end of file indicator in order to permit\n gzread to be tried again. Z_OK indicates that a gzip stream was completed\n on the last gzread. Z_BUF_ERROR indicates that the input file ended in the\n middle of a gzip stream. Note that gzread does not return -1 in the event\n of an incomplete gzip stream. This error is deferred until gzclose(), which\n will return Z_BUF_ERROR if the last gzread ended in the middle of a gzip\n stream. Alternatively, gzerror can be used before gzclose to detect this\n case.\n\n gzread returns the number of uncompressed bytes actually read, less than\n len for end of file, or -1 for error. If len is too large to fit in an int,\n then nothing is read, -1 is returned, and the error state is set to\n Z_STREAM_ERROR.\n*/\n\nZEXTERN z_size_t ZEXPORT gzfread(voidp buf, z_size_t size, z_size_t nitems,\n gzFile file);\n/*\n Read and decompress up to nitems items of size size from file into buf,\n otherwise operating as gzread() does. This duplicates the interface of\n stdio's fread(), with size_t request and return types. If the library\n defines size_t, then z_size_t is identical to size_t. If not, then z_size_t\n is an unsigned integer type that can contain a pointer.\n\n gzfread() returns the number of full items read of size size, or zero if\n the end of the file was reached and a full item could not be read, or if\n there was an error. gzerror() must be consulted if zero is returned in\n order to determine if there was an error. If the multiplication of size and\n nitems overflows, i.e. the product does not fit in a z_size_t, then nothing\n is read, zero is returned, and the error state is set to Z_STREAM_ERROR.\n\n In the event that the end of file is reached and only a partial item is\n available at the end, i.e. the remaining uncompressed data length is not a\n multiple of size, then the final partial item is nevertheless read into buf\n and the end-of-file flag is set. The length of the partial item read is not\n provided, but could be inferred from the result of gztell(). This behavior\n is the same as the behavior of fread() implementations in common libraries,\n but it prevents the direct use of gzfread() to read a concurrently written\n file, resetting and retrying on end-of-file, when size is not 1.\n*/\n\nZEXTERN int ZEXPORT gzwrite(gzFile file, voidpc buf, unsigned len);\n/*\n Compress and write the len uncompressed bytes at buf to file. gzwrite\n returns the number of uncompressed bytes written or 0 in case of error.\n*/\n\nZEXTERN z_size_t ZEXPORT gzfwrite(voidpc buf, z_size_t size,\n z_size_t nitems, gzFile file);\n/*\n Compress and write nitems items of size size from buf to file, duplicating\n the interface of stdio's fwrite(), with size_t request and return types. If\n the library defines size_t, then z_size_t is identical to size_t. If not,\n then z_size_t is an unsigned integer type that can contain a pointer.\n\n gzfwrite() returns the number of full items written of size size, or zero\n if there was an error. If the multiplication of size and nitems overflows,\n i.e. the product does not fit in a z_size_t, then nothing is written, zero\n is returned, and the error state is set to Z_STREAM_ERROR.\n*/\n\nZEXTERN int ZEXPORTVA gzprintf(gzFile file, const char *format, ...);\n/*\n Convert, format, compress, and write the arguments (...) to file under\n control of the string format, as in fprintf. gzprintf returns the number of\n uncompressed bytes actually written, or a negative zlib error code in case\n of error. The number of uncompressed bytes written is limited to 8191, or\n one less than the buffer size given to gzbuffer(). The caller should assure\n that this limit is not exceeded. If it is exceeded, then gzprintf() will\n return an error (0) with nothing written. In this case, there may also be a\n buffer overflow with unpredictable consequences, which is possible only if\n zlib was compiled with the insecure functions sprintf() or vsprintf(),\n because the secure snprintf() or vsnprintf() functions were not available.\n This can be determined using zlibCompileFlags().\n*/\n\nZEXTERN int ZEXPORT gzputs(gzFile file, const char *s);\n/*\n Compress and write the given null-terminated string s to file, excluding\n the terminating null character.\n\n gzputs returns the number of characters written, or -1 in case of error.\n*/\n\nZEXTERN char * ZEXPORT gzgets(gzFile file, char *buf, int len);\n/*\n Read and decompress bytes from file into buf, until len-1 characters are\n read, or until a newline character is read and transferred to buf, or an\n end-of-file condition is encountered. If any characters are read or if len\n is one, the string is terminated with a null character. If no characters\n are read due to an end-of-file or len is less than one, then the buffer is\n left untouched.\n\n gzgets returns buf which is a null-terminated string, or it returns NULL\n for end-of-file or in case of error. If there was an error, the contents at\n buf are indeterminate.\n*/\n\nZEXTERN int ZEXPORT gzputc(gzFile file, int c);\n/*\n Compress and write c, converted to an unsigned char, into file. gzputc\n returns the value that was written, or -1 in case of error.\n*/\n\nZEXTERN int ZEXPORT gzgetc(gzFile file);\n/*\n Read and decompress one byte from file. gzgetc returns this byte or -1\n in case of end of file or error. This is implemented as a macro for speed.\n As such, it does not do all of the checking the other functions do. I.e.\n it does not check to see if file is NULL, nor whether the structure file\n points to has been clobbered or not.\n*/\n\nZEXTERN int ZEXPORT gzungetc(int c, gzFile file);\n/*\n Push c back onto the stream for file to be read as the first character on\n the next read. At least one character of push-back is always allowed.\n gzungetc() returns the character pushed, or -1 on failure. gzungetc() will\n fail if c is -1, and may fail if a character has been pushed but not read\n yet. If gzungetc is used immediately after gzopen or gzdopen, at least the\n output buffer size of pushed characters is allowed. (See gzbuffer above.)\n The pushed character will be discarded if the stream is repositioned with\n gzseek() or gzrewind().\n*/\n\nZEXTERN int ZEXPORT gzflush(gzFile file, int flush);\n/*\n Flush all pending output to file. The parameter flush is as in the\n deflate() function. The return value is the zlib error number (see function\n gzerror below). gzflush is only permitted when writing.\n\n If the flush parameter is Z_FINISH, the remaining data is written and the\n gzip stream is completed in the output. If gzwrite() is called again, a new\n gzip stream will be started in the output. gzread() is able to read such\n concatenated gzip streams.\n\n gzflush should be called only when strictly necessary because it will\n degrade compression if called too often.\n*/\n\n/*\nZEXTERN z_off_t ZEXPORT gzseek(gzFile file,\n z_off_t offset, int whence);\n\n Set the starting position to offset relative to whence for the next gzread\n or gzwrite on file. The offset represents a number of bytes in the\n uncompressed data stream. The whence parameter is defined as in lseek(2);\n the value SEEK_END is not supported.\n\n If the file is opened for reading, this function is emulated but can be\n extremely slow. If the file is opened for writing, only forward seeks are\n supported; gzseek then compresses a sequence of zeroes up to the new\n starting position.\n\n gzseek returns the resulting offset location as measured in bytes from\n the beginning of the uncompressed stream, or -1 in case of error, in\n particular if the file is opened for writing and the new starting position\n would be before the current position.\n*/\n\nZEXTERN int ZEXPORT gzrewind(gzFile file);\n/*\n Rewind file. This function is supported only for reading.\n\n gzrewind(file) is equivalent to (int)gzseek(file, 0L, SEEK_SET).\n*/\n\n/*\nZEXTERN z_off_t ZEXPORT gztell(gzFile file);\n\n Return the starting position for the next gzread or gzwrite on file.\n This position represents a number of bytes in the uncompressed data stream,\n and is zero when starting, even if appending or reading a gzip stream from\n the middle of a file using gzdopen().\n\n gztell(file) is equivalent to gzseek(file, 0L, SEEK_CUR)\n*/\n\n/*\nZEXTERN z_off_t ZEXPORT gzoffset(gzFile file);\n\n Return the current compressed (actual) read or write offset of file. This\n offset includes the count of bytes that precede the gzip stream, for example\n when appending or when using gzdopen() for reading. When reading, the\n offset does not include as yet unused buffered input. This information can\n be used for a progress indicator. On error, gzoffset() returns -1.\n*/\n\nZEXTERN int ZEXPORT gzeof(gzFile file);\n/*\n Return true (1) if the end-of-file indicator for file has been set while\n reading, false (0) otherwise. Note that the end-of-file indicator is set\n only if the read tried to go past the end of the input, but came up short.\n Therefore, just like feof(), gzeof() may return false even if there is no\n more data to read, in the event that the last read request was for the exact\n number of bytes remaining in the input file. This will happen if the input\n file size is an exact multiple of the buffer size.\n\n If gzeof() returns true, then the read functions will return no more data,\n unless the end-of-file indicator is reset by gzclearerr() and the input file\n has grown since the previous end of file was detected.\n*/\n\nZEXTERN int ZEXPORT gzdirect(gzFile file);\n/*\n Return true (1) if file is being copied directly while reading, or false\n (0) if file is a gzip stream being decompressed.\n\n If the input file is empty, gzdirect() will return true, since the input\n does not contain a gzip stream.\n\n If gzdirect() is used immediately after gzopen() or gzdopen() it will\n cause buffers to be allocated to allow reading the file to determine if it\n is a gzip file. Therefore if gzbuffer() is used, it should be called before\n gzdirect().\n\n When writing, gzdirect() returns true (1) if transparent writing was\n requested (\"wT\" for the gzopen() mode), or false (0) otherwise. (Note:\n gzdirect() is not needed when writing. Transparent writing must be\n explicitly requested, so the application already knows the answer. When\n linking statically, using gzdirect() will include all of the zlib code for\n gzip file reading and decompression, which may not be desired.)\n*/\n\nZEXTERN int ZEXPORT gzclose(gzFile file);\n/*\n Flush all pending output for file, if necessary, close file and\n deallocate the (de)compression state. Note that once file is closed, you\n cannot call gzerror with file, since its structures have been deallocated.\n gzclose must not be called more than once on the same file, just as free\n must not be called more than once on the same allocation.\n\n gzclose will return Z_STREAM_ERROR if file is not valid, Z_ERRNO on a\n file operation error, Z_MEM_ERROR if out of memory, Z_BUF_ERROR if the\n last read ended in the middle of a gzip stream, or Z_OK on success.\n*/\n\nZEXTERN int ZEXPORT gzclose_r(gzFile file);\nZEXTERN int ZEXPORT gzclose_w(gzFile file);\n/*\n Same as gzclose(), but gzclose_r() is only for use when reading, and\n gzclose_w() is only for use when writing or appending. The advantage to\n using these instead of gzclose() is that they avoid linking in zlib\n compression or decompression code that is not used when only reading or only\n writing respectively. If gzclose() is used, then both compression and\n decompression code will be included the application when linking to a static\n zlib library.\n*/\n\nZEXTERN const char * ZEXPORT gzerror(gzFile file, int *errnum);\n/*\n Return the error message for the last error which occurred on file.\n errnum is set to zlib error number. If an error occurred in the file system\n and not in the compression library, errnum is set to Z_ERRNO and the\n application may consult errno to get the exact error code.\n\n The application must not modify the returned string. Future calls to\n this function may invalidate the previously returned string. If file is\n closed, then the string previously returned by gzerror will no longer be\n available.\n\n gzerror() should be used to distinguish errors from end-of-file for those\n functions above that do not distinguish those cases in their return values.\n*/\n\nZEXTERN void ZEXPORT gzclearerr(gzFile file);\n/*\n Clear the error and end-of-file flags for file. This is analogous to the\n clearerr() function in stdio. This is useful for continuing to read a gzip\n file that is being written concurrently.\n*/\n\n#endif /* !Z_SOLO */\n\n /* checksum functions */\n\n/*\n These functions are not related to compression but are exported\n anyway because they might be useful in applications using the compression\n library.\n*/\n\nZEXTERN uLong ZEXPORT adler32(uLong adler, const Bytef *buf, uInt len);\n/*\n Update a running Adler-32 checksum with the bytes buf[0..len-1] and\n return the updated checksum. An Adler-32 value is in the range of a 32-bit\n unsigned integer. If buf is Z_NULL, this function returns the required\n initial value for the checksum.\n\n An Adler-32 checksum is almost as reliable as a CRC-32 but can be computed\n much faster.\n\n Usage example:\n\n uLong adler = adler32(0L, Z_NULL, 0);\n\n while (read_buffer(buffer, length) != EOF) {\n adler = adler32(adler, buffer, length);\n }\n if (adler != original_adler) error();\n*/\n\nZEXTERN uLong ZEXPORT adler32_z(uLong adler, const Bytef *buf,\n z_size_t len);\n/*\n Same as adler32(), but with a size_t length.\n*/\n\n/*\nZEXTERN uLong ZEXPORT adler32_combine(uLong adler1, uLong adler2,\n z_off_t len2);\n\n Combine two Adler-32 checksums into one. For two sequences of bytes, seq1\n and seq2 with lengths len1 and len2, Adler-32 checksums were calculated for\n each, adler1 and adler2. adler32_combine() returns the Adler-32 checksum of\n seq1 and seq2 concatenated, requiring only adler1, adler2, and len2. Note\n that the z_off_t type (like off_t) is a signed integer. If len2 is\n negative, the result has no meaning or utility.\n*/\n\nZEXTERN uLong ZEXPORT crc32(uLong crc, const Bytef *buf, uInt len);\n/*\n Update a running CRC-32 with the bytes buf[0..len-1] and return the\n updated CRC-32. A CRC-32 value is in the range of a 32-bit unsigned integer.\n If buf is Z_NULL, this function returns the required initial value for the\n crc. Pre- and post-conditioning (one's complement) is performed within this\n function so it shouldn't be done by the application.\n\n Usage example:\n\n uLong crc = crc32(0L, Z_NULL, 0);\n\n while (read_buffer(buffer, length) != EOF) {\n crc = crc32(crc, buffer, length);\n }\n if (crc != original_crc) error();\n*/\n\nZEXTERN uLong ZEXPORT crc32_z(uLong crc, const Bytef *buf,\n z_size_t len);\n/*\n Same as crc32(), but with a size_t length.\n*/\n\n/*\nZEXTERN uLong ZEXPORT crc32_combine(uLong crc1, uLong crc2, z_off_t len2);\n\n Combine two CRC-32 check values into one. For two sequences of bytes,\n seq1 and seq2 with lengths len1 and len2, CRC-32 check values were\n calculated for each, crc1 and crc2. crc32_combine() returns the CRC-32\n check value of seq1 and seq2 concatenated, requiring only crc1, crc2, and\n len2. len2 must be non-negative.\n*/\n\n/*\nZEXTERN uLong ZEXPORT crc32_combine_gen(z_off_t len2);\n\n Return the operator corresponding to length len2, to be used with\n crc32_combine_op(). len2 must be non-negative.\n*/\n\nZEXTERN uLong ZEXPORT crc32_combine_op(uLong crc1, uLong crc2, uLong op);\n/*\n Give the same result as crc32_combine(), using op in place of len2. op is\n is generated from len2 by crc32_combine_gen(). This will be faster than\n crc32_combine() if the generated op is used more than once.\n*/\n\n\n /* various hacks, don't look :) */\n\n/* deflateInit and inflateInit are macros to allow checking the zlib version\n * and the compiler's view of z_stream:\n */\nZEXTERN int ZEXPORT deflateInit_(z_streamp strm, int level,\n const char *version, int stream_size);\nZEXTERN int ZEXPORT inflateInit_(z_streamp strm,\n const char *version, int stream_size);\nZEXTERN int ZEXPORT deflateInit2_(z_streamp strm, int level, int method,\n int windowBits, int memLevel,\n int strategy, const char *version,\n int stream_size);\nZEXTERN int ZEXPORT inflateInit2_(z_streamp strm, int windowBits,\n const char *version, int stream_size);\nZEXTERN int ZEXPORT inflateBackInit_(z_streamp strm, int windowBits,\n unsigned char FAR *window,\n const char *version,\n int stream_size);\n#ifdef Z_PREFIX_SET\n# define z_deflateInit(strm, level) \\\n deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream))\n# define z_inflateInit(strm) \\\n inflateInit_((strm), ZLIB_VERSION, (int)sizeof(z_stream))\n# define z_deflateInit2(strm, level, method, windowBits, memLevel, strategy) \\\n deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\\\n (strategy), ZLIB_VERSION, (int)sizeof(z_stream))\n# define z_inflateInit2(strm, windowBits) \\\n inflateInit2_((strm), (windowBits), ZLIB_VERSION, \\\n (int)sizeof(z_stream))\n# define z_inflateBackInit(strm, windowBits, window) \\\n inflateBackInit_((strm), (windowBits), (window), \\\n ZLIB_VERSION, (int)sizeof(z_stream))\n#else\n# define deflateInit(strm, level) \\\n deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream))\n# define inflateInit(strm) \\\n inflateInit_((strm), ZLIB_VERSION, (int)sizeof(z_stream))\n# define deflateInit2(strm, level, method, windowBits, memLevel, strategy) \\\n deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\\\n (strategy), ZLIB_VERSION, (int)sizeof(z_stream))\n# define inflateInit2(strm, windowBits) \\\n inflateInit2_((strm), (windowBits), ZLIB_VERSION, \\\n (int)sizeof(z_stream))\n# define inflateBackInit(strm, windowBits, window) \\\n inflateBackInit_((strm), (windowBits), (window), \\\n ZLIB_VERSION, (int)sizeof(z_stream))\n#endif\n\n#ifndef Z_SOLO\n\n/* gzgetc() macro and its supporting function and exposed data structure. Note\n * that the real internal state is much larger than the exposed structure.\n * This abbreviated structure exposes just enough for the gzgetc() macro. The\n * user should not mess with these exposed elements, since their names or\n * behavior could change in the future, perhaps even capriciously. They can\n * only be used by the gzgetc() macro. You have been warned.\n */\nstruct gzFile_s {\n unsigned have;\n unsigned char *next;\n z_off64_t pos;\n};\nZEXTERN int ZEXPORT gzgetc_(gzFile file); /* backward compatibility */\n#ifdef Z_PREFIX_SET\n# undef z_gzgetc\n# define z_gzgetc(g) \\\n ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))\n#else\n# define gzgetc(g) \\\n ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))\n#endif\n\n/* provide 64-bit offset functions if _LARGEFILE64_SOURCE defined, and/or\n * change the regular functions to 64 bits if _FILE_OFFSET_BITS is 64 (if\n * both are true, the application gets the *64 functions, and the regular\n * functions are changed to 64 bits) -- in case these are set on systems\n * without large file support, _LFS64_LARGEFILE must also be true\n */\n#ifdef Z_LARGE64\n ZEXTERN gzFile ZEXPORT gzopen64(const char *, const char *);\n ZEXTERN z_off64_t ZEXPORT gzseek64(gzFile, z_off64_t, int);\n ZEXTERN z_off64_t ZEXPORT gztell64(gzFile);\n ZEXTERN z_off64_t ZEXPORT gzoffset64(gzFile);\n ZEXTERN uLong ZEXPORT adler32_combine64(uLong, uLong, z_off64_t);\n ZEXTERN uLong ZEXPORT crc32_combine64(uLong, uLong, z_off64_t);\n ZEXTERN uLong ZEXPORT crc32_combine_gen64(z_off64_t);\n#endif\n\n#if !defined(ZLIB_INTERNAL) && defined(Z_WANT64)\n# ifdef Z_PREFIX_SET\n# define z_gzopen z_gzopen64\n# define z_gzseek z_gzseek64\n# define z_gztell z_gztell64\n# define z_gzoffset z_gzoffset64\n# define z_adler32_combine z_adler32_combine64\n# define z_crc32_combine z_crc32_combine64\n# define z_crc32_combine_gen z_crc32_combine_gen64\n# else\n# define gzopen gzopen64\n# define gzseek gzseek64\n# define gztell gztell64\n# define gzoffset gzoffset64\n# define adler32_combine adler32_combine64\n# define crc32_combine crc32_combine64\n# define crc32_combine_gen crc32_combine_gen64\n# endif\n# ifndef Z_LARGE64\n ZEXTERN gzFile ZEXPORT gzopen64(const char *, const char *);\n ZEXTERN z_off_t ZEXPORT gzseek64(gzFile, z_off_t, int);\n ZEXTERN z_off_t ZEXPORT gztell64(gzFile);\n ZEXTERN z_off_t ZEXPORT gzoffset64(gzFile);\n ZEXTERN uLong ZEXPORT adler32_combine64(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine64(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine_gen64(z_off_t);\n# endif\n#else\n ZEXTERN gzFile ZEXPORT gzopen(const char *, const char *);\n ZEXTERN z_off_t ZEXPORT gzseek(gzFile, z_off_t, int);\n ZEXTERN z_off_t ZEXPORT gztell(gzFile);\n ZEXTERN z_off_t ZEXPORT gzoffset(gzFile);\n ZEXTERN uLong ZEXPORT adler32_combine(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine_gen(z_off_t);\n#endif\n\n#else /* Z_SOLO */\n\n ZEXTERN uLong ZEXPORT adler32_combine(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine_gen(z_off_t);\n\n#endif /* !Z_SOLO */\n\n/* undocumented functions */\nZEXTERN const char * ZEXPORT zError(int);\nZEXTERN int ZEXPORT inflateSyncPoint(z_streamp);\nZEXTERN const z_crc_t FAR * ZEXPORT get_crc_table(void);\nZEXTERN int ZEXPORT inflateUndermine(z_streamp, int);\nZEXTERN int ZEXPORT inflateValidate(z_streamp, int);\nZEXTERN unsigned long ZEXPORT inflateCodesUsed(z_streamp);\nZEXTERN int ZEXPORT inflateResetKeep(z_streamp);\nZEXTERN int ZEXPORT deflateResetKeep(z_streamp);\n#if defined(_WIN32) && !defined(Z_SOLO)\nZEXTERN gzFile ZEXPORT gzopen_w(const wchar_t *path,\n const char *mode);\n#endif\n#if defined(STDC) || defined(Z_HAVE_STDARG_H)\n# ifndef Z_SOLO\nZEXTERN int ZEXPORTVA gzvprintf(gzFile file,\n const char *format,\n va_list va);\n# endif\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ZLIB_H */\n" }, { "path": "pypcode/zlib/zutil.c", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* zutil.c -- target dependent utility functions for the compression library\n * Copyright (C) 1995-2017 Jean-loup Gailly\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* @(#) $Id$ */\n\n#include \"zutil.h\"\n#ifndef Z_SOLO\n# include \"gzguts.h\"\n#endif\n\nz_const char * const z_errmsg[10] = {\n (z_const char *)\"need dictionary\", /* Z_NEED_DICT 2 */\n (z_const char *)\"stream end\", /* Z_STREAM_END 1 */\n (z_const char *)\"\", /* Z_OK 0 */\n (z_const char *)\"file error\", /* Z_ERRNO (-1) */\n (z_const char *)\"stream error\", /* Z_STREAM_ERROR (-2) */\n (z_const char *)\"data error\", /* Z_DATA_ERROR (-3) */\n (z_const char *)\"insufficient memory\", /* Z_MEM_ERROR (-4) */\n (z_const char *)\"buffer error\", /* Z_BUF_ERROR (-5) */\n (z_const char *)\"incompatible version\",/* Z_VERSION_ERROR (-6) */\n (z_const char *)\"\"\n};\n\n\nconst char * ZEXPORT zlibVersion(void) {\n return ZLIB_VERSION;\n}\n\nuLong ZEXPORT zlibCompileFlags(void) {\n uLong flags;\n\n flags = 0;\n switch ((int)(sizeof(uInt))) {\n case 2: break;\n case 4: flags += 1; break;\n case 8: flags += 2; break;\n default: flags += 3;\n }\n switch ((int)(sizeof(uLong))) {\n case 2: break;\n case 4: flags += 1 << 2; break;\n case 8: flags += 2 << 2; break;\n default: flags += 3 << 2;\n }\n switch ((int)(sizeof(voidpf))) {\n case 2: break;\n case 4: flags += 1 << 4; break;\n case 8: flags += 2 << 4; break;\n default: flags += 3 << 4;\n }\n switch ((int)(sizeof(z_off_t))) {\n case 2: break;\n case 4: flags += 1 << 6; break;\n case 8: flags += 2 << 6; break;\n default: flags += 3 << 6;\n }\n#ifdef ZLIB_DEBUG\n flags += 1 << 8;\n#endif\n /*\n#if defined(ASMV) || defined(ASMINF)\n flags += 1 << 9;\n#endif\n */\n#ifdef ZLIB_WINAPI\n flags += 1 << 10;\n#endif\n#ifdef BUILDFIXED\n flags += 1 << 12;\n#endif\n#ifdef DYNAMIC_CRC_TABLE\n flags += 1 << 13;\n#endif\n#ifdef NO_GZCOMPRESS\n flags += 1L << 16;\n#endif\n#ifdef NO_GZIP\n flags += 1L << 17;\n#endif\n#ifdef PKZIP_BUG_WORKAROUND\n flags += 1L << 20;\n#endif\n#ifdef FASTEST\n flags += 1L << 21;\n#endif\n#if defined(STDC) || defined(Z_HAVE_STDARG_H)\n# ifdef NO_vsnprintf\n flags += 1L << 25;\n# ifdef HAS_vsprintf_void\n flags += 1L << 26;\n# endif\n# else\n# ifdef HAS_vsnprintf_void\n flags += 1L << 26;\n# endif\n# endif\n#else\n flags += 1L << 24;\n# ifdef NO_snprintf\n flags += 1L << 25;\n# ifdef HAS_sprintf_void\n flags += 1L << 26;\n# endif\n# else\n# ifdef HAS_snprintf_void\n flags += 1L << 26;\n# endif\n# endif\n#endif\n return flags;\n}\n\n#ifdef ZLIB_DEBUG\n#include \n# ifndef verbose\n# define verbose 0\n# endif\nint ZLIB_INTERNAL z_verbose = verbose;\n\nvoid ZLIB_INTERNAL z_error(char *m) {\n fprintf(stderr, \"%s\\n\", m);\n exit(1);\n}\n#endif\n\n/* exported to allow conversion of error code to string for compress() and\n * uncompress()\n */\nconst char * ZEXPORT zError(int err) {\n return ERR_MSG(err);\n}\n\n#if defined(_WIN32_WCE) && _WIN32_WCE < 0x800\n /* The older Microsoft C Run-Time Library for Windows CE doesn't have\n * errno. We define it as a global variable to simplify porting.\n * Its value is always 0 and should not be used.\n */\n int errno = 0;\n#endif\n\n#ifndef HAVE_MEMCPY\n\nvoid ZLIB_INTERNAL zmemcpy(Bytef* dest, const Bytef* source, uInt len) {\n if (len == 0) return;\n do {\n *dest++ = *source++; /* ??? to be unrolled */\n } while (--len != 0);\n}\n\nint ZLIB_INTERNAL zmemcmp(const Bytef* s1, const Bytef* s2, uInt len) {\n uInt j;\n\n for (j = 0; j < len; j++) {\n if (s1[j] != s2[j]) return 2*(s1[j] > s2[j])-1;\n }\n return 0;\n}\n\nvoid ZLIB_INTERNAL zmemzero(Bytef* dest, uInt len) {\n if (len == 0) return;\n do {\n *dest++ = 0; /* ??? to be unrolled */\n } while (--len != 0);\n}\n#endif\n\n#ifndef Z_SOLO\n\n#ifdef SYS16BIT\n\n#ifdef __TURBOC__\n/* Turbo C in 16-bit mode */\n\n# define MY_ZCALLOC\n\n/* Turbo C malloc() does not allow dynamic allocation of 64K bytes\n * and farmalloc(64K) returns a pointer with an offset of 8, so we\n * must fix the pointer. Warning: the pointer must be put back to its\n * original form in order to free it, use zcfree().\n */\n\n#define MAX_PTR 10\n/* 10*64K = 640K */\n\nlocal int next_ptr = 0;\n\ntypedef struct ptr_table_s {\n voidpf org_ptr;\n voidpf new_ptr;\n} ptr_table;\n\nlocal ptr_table table[MAX_PTR];\n/* This table is used to remember the original form of pointers\n * to large buffers (64K). Such pointers are normalized with a zero offset.\n * Since MSDOS is not a preemptive multitasking OS, this table is not\n * protected from concurrent access. This hack doesn't work anyway on\n * a protected system like OS/2. Use Microsoft C instead.\n */\n\nvoidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, unsigned size) {\n voidpf buf;\n ulg bsize = (ulg)items*size;\n\n (void)opaque;\n\n /* If we allocate less than 65520 bytes, we assume that farmalloc\n * will return a usable pointer which doesn't have to be normalized.\n */\n if (bsize < 65520L) {\n buf = farmalloc(bsize);\n if (*(ush*)&buf != 0) return buf;\n } else {\n buf = farmalloc(bsize + 16L);\n }\n if (buf == NULL || next_ptr >= MAX_PTR) return NULL;\n table[next_ptr].org_ptr = buf;\n\n /* Normalize the pointer to seg:0 */\n *((ush*)&buf+1) += ((ush)((uch*)buf-0) + 15) >> 4;\n *(ush*)&buf = 0;\n table[next_ptr++].new_ptr = buf;\n return buf;\n}\n\nvoid ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) {\n int n;\n\n (void)opaque;\n\n if (*(ush*)&ptr != 0) { /* object < 64K */\n farfree(ptr);\n return;\n }\n /* Find the original pointer */\n for (n = 0; n < next_ptr; n++) {\n if (ptr != table[n].new_ptr) continue;\n\n farfree(table[n].org_ptr);\n while (++n < next_ptr) {\n table[n-1] = table[n];\n }\n next_ptr--;\n return;\n }\n Assert(0, \"zcfree: ptr not found\");\n}\n\n#endif /* __TURBOC__ */\n\n\n#ifdef M_I86\n/* Microsoft C in 16-bit mode */\n\n# define MY_ZCALLOC\n\n#if (!defined(_MSC_VER) || (_MSC_VER <= 600))\n# define _halloc halloc\n# define _hfree hfree\n#endif\n\nvoidpf ZLIB_INTERNAL zcalloc(voidpf opaque, uInt items, uInt size) {\n (void)opaque;\n return _halloc((long)items, size);\n}\n\nvoid ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) {\n (void)opaque;\n _hfree(ptr);\n}\n\n#endif /* M_I86 */\n\n#endif /* SYS16BIT */\n\n\n#ifndef MY_ZCALLOC /* Any system without a special alloc function */\n\n#ifndef STDC\nextern voidp malloc(uInt size);\nextern voidp calloc(uInt items, uInt size);\nextern void free(voidpf ptr);\n#endif\n\nvoidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, unsigned size) {\n (void)opaque;\n return sizeof(uInt) > 2 ? (voidpf)malloc(items * size) :\n (voidpf)calloc(items, size);\n}\n\nvoid ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) {\n (void)opaque;\n free(ptr);\n}\n\n#endif /* MY_ZCALLOC */\n\n#endif /* !Z_SOLO */\n" }, { "path": "pypcode/zlib/zutil.h", "content": "/* ###\n * IP: zlib License\n * NOTE: from zlib 1.3.1\n */\n/* zutil.h -- internal interface and configuration of the compression library\n * Copyright (C) 1995-2024 Jean-loup Gailly, Mark Adler\n * For conditions of distribution and use, see copyright notice in zlib.h\n */\n\n/* WARNING: this file should *not* be used by applications. It is\n part of the implementation of the compression library and is\n subject to change. Applications should only use zlib.h.\n */\n\n/* @(#) $Id$ */\n\n#ifndef ZUTIL_H\n#define ZUTIL_H\n\n#ifdef HAVE_HIDDEN\n# define ZLIB_INTERNAL __attribute__((visibility (\"hidden\")))\n#else\n# define ZLIB_INTERNAL\n#endif\n\n#include \"zlib.h\"\n\n#if defined(STDC) && !defined(Z_SOLO)\n# if !(defined(_WIN32_WCE) && defined(_MSC_VER))\n# include \n# endif\n# include \n# include \n#endif\n\n#ifndef local\n# define local static\n#endif\n/* since \"static\" is used to mean two completely different things in C, we\n define \"local\" for the non-static meaning of \"static\", for readability\n (compile with -Dlocal if your debugger can't find static symbols) */\n\ntypedef unsigned char uch;\ntypedef uch FAR uchf;\ntypedef unsigned short ush;\ntypedef ush FAR ushf;\ntypedef unsigned long ulg;\n\n#if !defined(Z_U8) && !defined(Z_SOLO) && defined(STDC)\n# include \n# if (ULONG_MAX == 0xffffffffffffffff)\n# define Z_U8 unsigned long\n# elif (ULLONG_MAX == 0xffffffffffffffff)\n# define Z_U8 unsigned long long\n# elif (UINT_MAX == 0xffffffffffffffff)\n# define Z_U8 unsigned\n# endif\n#endif\n\nextern z_const char * const z_errmsg[10]; /* indexed by 2-zlib_error */\n/* (size given to avoid silly warnings with Visual C++) */\n\n#define ERR_MSG(err) z_errmsg[(err) < -6 || (err) > 2 ? 9 : 2 - (err)]\n\n#define ERR_RETURN(strm,err) \\\n return (strm->msg = ERR_MSG(err), (err))\n/* To be used only when the state is known to be valid */\n\n /* common constants */\n\n#ifndef DEF_WBITS\n# define DEF_WBITS MAX_WBITS\n#endif\n/* default windowBits for decompression. MAX_WBITS is for compression only */\n\n#if MAX_MEM_LEVEL >= 8\n# define DEF_MEM_LEVEL 8\n#else\n# define DEF_MEM_LEVEL MAX_MEM_LEVEL\n#endif\n/* default memLevel */\n\n#define STORED_BLOCK 0\n#define STATIC_TREES 1\n#define DYN_TREES 2\n/* The three kinds of block type */\n\n#define MIN_MATCH 3\n#define MAX_MATCH 258\n/* The minimum and maximum match lengths */\n\n#define PRESET_DICT 0x20 /* preset dictionary flag in zlib header */\n\n /* target dependencies */\n\n#if defined(MSDOS) || (defined(WINDOWS) && !defined(WIN32))\n# define OS_CODE 0x00\n# ifndef Z_SOLO\n# if defined(__TURBOC__) || defined(__BORLANDC__)\n# if (__STDC__ == 1) && (defined(__LARGE__) || defined(__COMPACT__))\n /* Allow compilation with ANSI keywords only enabled */\n void _Cdecl farfree( void *block );\n void *_Cdecl farmalloc( unsigned long nbytes );\n# else\n# include \n# endif\n# else /* MSC or DJGPP */\n# include \n# endif\n# endif\n#endif\n\n#ifdef AMIGA\n# define OS_CODE 1\n#endif\n\n#if defined(VAXC) || defined(VMS)\n# define OS_CODE 2\n# define F_OPEN(name, mode) \\\n fopen((name), (mode), \"mbc=60\", \"ctx=stm\", \"rfm=fix\", \"mrs=512\")\n#endif\n\n#ifdef __370__\n# if __TARGET_LIB__ < 0x20000000\n# define OS_CODE 4\n# elif __TARGET_LIB__ < 0x40000000\n# define OS_CODE 11\n# else\n# define OS_CODE 8\n# endif\n#endif\n\n#if defined(ATARI) || defined(atarist)\n# define OS_CODE 5\n#endif\n\n#ifdef OS2\n# define OS_CODE 6\n# if defined(M_I86) && !defined(Z_SOLO)\n# include \n# endif\n#endif\n\n#if defined(MACOS)\n# define OS_CODE 7\n#endif\n\n#ifdef __acorn\n# define OS_CODE 13\n#endif\n\n#if defined(WIN32) && !defined(__CYGWIN__)\n# define OS_CODE 10\n#endif\n\n#ifdef _BEOS_\n# define OS_CODE 16\n#endif\n\n#ifdef __TOS_OS400__\n# define OS_CODE 18\n#endif\n\n#ifdef __APPLE__\n# define OS_CODE 19\n#endif\n\n#if defined(__BORLANDC__) && !defined(MSDOS)\n #pragma warn -8004\n #pragma warn -8008\n #pragma warn -8066\n#endif\n\n/* provide prototypes for these when building zlib without LFS */\n#if !defined(_WIN32) && \\\n (!defined(_LARGEFILE64_SOURCE) || _LFS64_LARGEFILE-0 == 0)\n ZEXTERN uLong ZEXPORT adler32_combine64(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine64(uLong, uLong, z_off_t);\n ZEXTERN uLong ZEXPORT crc32_combine_gen64(z_off_t);\n#endif\n\n /* common defaults */\n\n#ifndef OS_CODE\n# define OS_CODE 3 /* assume Unix */\n#endif\n\n#ifndef F_OPEN\n# define F_OPEN(name, mode) fopen((name), (mode))\n#endif\n\n /* functions */\n\n#if defined(pyr) || defined(Z_SOLO)\n# define NO_MEMCPY\n#endif\n#if defined(SMALL_MEDIUM) && !defined(_MSC_VER) && !defined(__SC__)\n /* Use our own functions for small and medium model with MSC <= 5.0.\n * You may have to use the same strategy for Borland C (untested).\n * The __SC__ check is for Symantec.\n */\n# define NO_MEMCPY\n#endif\n#if defined(STDC) && !defined(HAVE_MEMCPY) && !defined(NO_MEMCPY)\n# define HAVE_MEMCPY\n#endif\n#ifdef HAVE_MEMCPY\n# ifdef SMALL_MEDIUM /* MSDOS small or medium model */\n# define zmemcpy _fmemcpy\n# define zmemcmp _fmemcmp\n# define zmemzero(dest, len) _fmemset(dest, 0, len)\n# else\n# define zmemcpy memcpy\n# define zmemcmp memcmp\n# define zmemzero(dest, len) memset(dest, 0, len)\n# endif\n#else\n void ZLIB_INTERNAL zmemcpy(Bytef* dest, const Bytef* source, uInt len);\n int ZLIB_INTERNAL zmemcmp(const Bytef* s1, const Bytef* s2, uInt len);\n void ZLIB_INTERNAL zmemzero(Bytef* dest, uInt len);\n#endif\n\n/* Diagnostic functions */\n#ifdef ZLIB_DEBUG\n# include \n extern int ZLIB_INTERNAL z_verbose;\n extern void ZLIB_INTERNAL z_error(char *m);\n# define Assert(cond,msg) {if(!(cond)) z_error(msg);}\n# define Trace(x) {if (z_verbose>=0) fprintf x ;}\n# define Tracev(x) {if (z_verbose>0) fprintf x ;}\n# define Tracevv(x) {if (z_verbose>1) fprintf x ;}\n# define Tracec(c,x) {if (z_verbose>0 && (c)) fprintf x ;}\n# define Tracecv(c,x) {if (z_verbose>1 && (c)) fprintf x ;}\n#else\n# define Assert(cond,msg)\n# define Trace(x)\n# define Tracev(x)\n# define Tracevv(x)\n# define Tracec(c,x)\n# define Tracecv(c,x)\n#endif\n\n#ifndef Z_SOLO\n voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items,\n unsigned size);\n void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr);\n#endif\n\n#define ZALLOC(strm, items, size) \\\n (*((strm)->zalloc))((strm)->opaque, (items), (size))\n#define ZFREE(strm, addr) (*((strm)->zfree))((strm)->opaque, (voidpf)(addr))\n#define TRY_FREE(s, p) {if (p) ZFREE(s, p);}\n\n/* Reverse the bytes in a 32-bit value */\n#define ZSWAP32(q) ((((q) >> 24) & 0xff) + (((q) >> 8) & 0xff00) + \\\n (((q) & 0xff00) << 8) + (((q) & 0xff) << 24))\n\n#endif /* ZUTIL_H */\n" }, { "path": "pyproject.toml", "content": "[project]\nname = \"pypcode\"\ndescription = \"Machine code disassembly and IR translation library\"\nlicense = \"BSD-2-Clause AND Apache-2.0 AND Zlib\"\nlicense-files = [ \"LICENSE.txt\" ]\nreadme = { file = \"README.md\", content-type = \"text/markdown\" }\nclassifiers = [\n \"Programming Language :: Python\",\n \"Programming Language :: Python :: 3\",\n \"Programming Language :: Python :: 3 :: Only\",\n \"Programming Language :: Python :: 3.12\",\n \"Programming Language :: Python :: 3.13\",\n \"Programming Language :: Python :: 3.14\",\n]\nrequires-python = \">=3.12\"\ndynamic = [ \"version\" ]\n\n[project.urls]\nHomepage = \"https://api.angr.io/projects/pypcode/en/latest/\"\nRepository = \"https://github.com/angr/pypcode\"\n\n[project.optional-dependencies]\ndocs = [\n \"furo\",\n \"ipython\",\n \"myst-parser\",\n \"sphinx\",\n \"sphinx-autodoc-typehints\",\n]\ntesting = [\n \"pytest\",\n \"pytest-cov\",\n \"coverage\",\n \"gcovr\",\n]\n\n[build-system]\nrequires = [ \"setuptools\", \"nanobind\", \"cmake\" ]\nbuild-backend = \"setuptools.build_meta\"\n\n[tool.setuptools]\ndynamic = { version = { attr = \"pypcode.__version__.__version__\" } }\npackages = [ \"pypcode\" ]\next-modules = [\n { name = \"pypcode.pypcode_native\", sources = [] }\n]\n\n[tool.black]\nline-length = 120\ntarget-version = ['py312']\n\n[tool.ruff]\nline-length = 120\nextend-ignore = [\n\t\"E402\", # Bottom imports\n]\n\n[tool.pytest.ini_options]\naddopts = [\n \"--cov=pypcode\",\n \"--cov-report=term-missing\",\n \"--cov-branch\",\n]\ntestpaths = [ \"tests\" ]\n\n[tool.coverage.run]\nbranch = true\nsource = [ \"pypcode\" ]\nparallel = true\nomit = [ \"tests/*\" ]\n\n[tool.coverage.report]\nshow_missing = true\nskip_covered = true\nexclude_lines = [\n \"if TYPE_CHECKING:\",\n \"if __name__ == .__main__.:\"\n]\n" }, { "path": "scripts/benchmark.py", "content": "#!/usr/bin/env python3\n# pylint:disable=import-outside-toplevel,wrong-import-position\n\"\"\"\nBenchmark disassembly and IR lifting performance for pypcode and other libraries.\n\"\"\"\n\nimport argparse\nimport csv\nimport functools\nimport gc\nimport hashlib\nimport logging\nimport os\nimport pickle\nimport random\nimport sys\nimport time\nfrom dataclasses import dataclass\n\nfrom typing import cast, Any\nfrom collections.abc import Callable, Iterable\n\nlogging.basicConfig(level=logging.INFO)\nlog = logging.getLogger(__name__)\nlog.setLevel(logging.INFO)\n\n\ntry:\n import_start_time = time.time()\n\n import capstone # type: ignore\n\n CAPSTONE_IMPORT_DURATION = time.time() - import_start_time\n del import_start_time\n HAVE_CAPSTONE = True\nexcept ImportError:\n HAVE_CAPSTONE = False\n\ntry:\n import_start_time = time.time()\n\n import pypcode\n\n PYPCODE_IMPORT_DURATION = time.time() - import_start_time\n del import_start_time\n HAVE_PYPCODE = True\nexcept ImportError:\n HAVE_PYPCODE = False\n\ntry:\n import_start_time = time.time()\n\n import archinfo\n import pyvex\n\n PYVEX_IMPORT_DURATION = time.time() - import_start_time\n del import_start_time\n HAVE_PYVEX = True\nexcept ImportError:\n HAVE_PYVEX = False\n\n\n@dataclass\nclass Block:\n \"\"\"Block to translate\"\"\"\n\n addr: int\n data: bytes\n\n\n@dataclass\nclass BenchmarkResult:\n \"\"\"Result of a benchmark run\"\"\"\n\n startup_duration: float\n translation_duration: float\n\n\ndef get_file_hash(binary_path: str) -> str:\n log.info(\"Calculating sha256 of file '%s'\", binary_path)\n m = hashlib.sha256()\n with open(binary_path, \"rb\") as f:\n m.update(f.read())\n d = m.hexdigest()\n log.info(\"sha256:%s\", d)\n return d\n\n\ndef get_blocks(binary_path: str) -> list[Block]:\n blocks_file_path = f\"blocks_{get_file_hash(binary_path)[0:8]}.cache\"\n blocks: list[Block] = []\n\n if not os.path.exists(blocks_file_path):\n log.info(\"Recovering blocks from CFG...\")\n\n try:\n import angr\n\n logging.getLogger(\"angr\").setLevel(logging.WARNING)\n logging.getLogger(\"cle\").setLevel(logging.WARNING)\n logging.getLogger(\"pyvex\").setLevel(logging.WARNING)\n logging.getLogger(\"claripy\").setLevel(logging.WARNING)\n except ImportError:\n log.error(\"Install angr to build list of blocks\")\n sys.exit(1)\n\n p = angr.Project(binary_path, auto_load_libs=False)\n cfg = p.analyses[angr.analyses.CFGFast].prep(show_progressbar=True)(\n resolve_indirect_jumps=False, force_smart_scan=False\n )\n for n in cast(Iterable[angr.knowledge_plugins.cfg.cfg_model.CFGNode], cfg.model.nodes()):\n if n.byte_string:\n blocks.append(Block(n.addr, n.byte_string))\n log.info(\"Saving blocks to file '%s' for subsequent benchmarks...\", blocks_file_path)\n with open(blocks_file_path, \"wb\") as f:\n pickle.dump(blocks, f)\n else:\n log.info(\"Loading blocks from cache file '%s'...\", blocks_file_path)\n with open(blocks_file_path, \"rb\") as f:\n blocks = pickle.load(f)\n\n return blocks\n\n\ndef benchmark_pypcode(blocks: list[Block], iter_ops: bool = False, iter_varnodes: bool = False) -> BenchmarkResult:\n assert pypcode is not None\n\n start_time = time.time()\n ctx = pypcode.Context(\"x86:LE:64:default\")\n startup_duration = time.time() - start_time\n\n start_time = time.time()\n count = 0\n for block in blocks:\n t = ctx.translate(block.data, block.addr)\n if iter_ops and not iter_varnodes:\n for _ in t.ops:\n count += 1\n if iter_varnodes:\n for op in t.ops:\n for _ in op.inputs:\n count += 1\n translation_duration = time.time() - start_time\n\n return BenchmarkResult(startup_duration, translation_duration)\n\n\ndef benchmark_pypcode_disassembly(blocks: list[Block]) -> BenchmarkResult:\n assert pypcode is not None\n\n start_time = time.time()\n ctx = pypcode.Context(\"x86:LE:64:default\")\n startup_duration = time.time() - start_time\n\n start_time = time.time()\n size = 0\n for block in blocks:\n for ins in ctx.disassemble(block.data, block.addr).instructions:\n size += ins.length\n translation_duration = time.time() - start_time\n\n return BenchmarkResult(startup_duration, translation_duration)\n\n\ndef benchmark_pyvex(blocks: list[Block], **vex_args) -> BenchmarkResult:\n assert pyvex is not None\n\n start_time = time.time()\n arch = archinfo.ArchAMD64()\n startup_duration = time.time() - start_time\n\n start_time = time.time()\n for block in blocks:\n pyvex.lift(block.data, block.addr, arch, **vex_args)\n translation_duration = time.time() - start_time\n\n return BenchmarkResult(startup_duration, translation_duration)\n\n\ndef benchmark_capstone(blocks: list[Block], lite: bool = False) -> BenchmarkResult:\n assert capstone is not None\n\n start_time = time.time()\n md = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_64)\n startup_duration = time.time() - start_time\n\n start_time = time.time()\n size = 0\n if lite:\n for block in blocks:\n for ins in md.disasm_lite(block.data, block.addr):\n size += ins[1]\n else:\n for block in blocks:\n for ins in md.disasm(block.data, block.addr):\n size += ins.size\n translation_duration = time.time() - start_time\n\n return BenchmarkResult(startup_duration, translation_duration)\n\n\ndef gen_benchmarks_from_configurations(\n name: str, benchmark_func: Callable, configurations: list[dict[str, Any]]\n) -> list[tuple[str, Callable]]:\n benchmarks: list[tuple[str, Callable]] = []\n for config in configurations:\n name_append = \"\"\n if config:\n name_append += f\" ({', '.join(f'{k}={v}' for k, v in config.items())})\"\n benchmarks.append((name + name_append, functools.partial(benchmark_func, **config)))\n return benchmarks\n\n\ndef main() -> None:\n ap = argparse.ArgumentParser(description=__doc__)\n ap.add_argument(\n \"-b\", \"--binary\", default=sys.executable, help=\"Binary to benchmark with (Python interpreter by default)\"\n )\n ap.add_argument(\n \"-c\",\n \"--coverage\",\n default=1,\n type=float,\n help=\"Percentage of blocks to include in benchmark in (0,1] (default=1)\",\n )\n ap.add_argument(\n \"--skip\", nargs=\"*\", default=[], help=\"Skip benchmarks for a particular package (pypcode, pyvex, capstone)\"\n )\n ap.add_argument(\"--csv\", help=\"Save results to CSV file\")\n args = ap.parse_args()\n\n # Display import times (use python -Ximporttime for more accurate import profiling)\n imports = []\n if HAVE_CAPSTONE:\n imports.append((\"capstone\", capstone.__version__, CAPSTONE_IMPORT_DURATION))\n if HAVE_PYPCODE:\n imports.append((\"pypcode\", pypcode.__version__, PYPCODE_IMPORT_DURATION))\n if HAVE_PYVEX:\n imports.append((\"pyvex\", pyvex.__version__, PYVEX_IMPORT_DURATION))\n for name, version, import_duration in imports:\n log.info(\"%s v%s took %.2f ms to import\", name, version, import_duration * 1000)\n\n benchmarks: list[tuple[str, Callable]] = []\n if HAVE_CAPSTONE and \"capstone\" not in args.skip:\n benchmarks.extend(\n gen_benchmarks_from_configurations(\n \"capstone Disassemble\",\n benchmark_capstone,\n [\n {},\n {\"lite\": True},\n ],\n )\n )\n if HAVE_PYPCODE and \"pypcode\" not in args.skip:\n benchmarks.append((\"pypcode Disassemble\", benchmark_pypcode_disassembly))\n benchmarks.extend(\n gen_benchmarks_from_configurations(\n \"pypcode Lift\",\n benchmark_pypcode,\n [\n {},\n {\"iter_ops\": True}, # Iterate over all ops\n {\"iter_varnodes\": True}, # Iterate over all ops and varnodes\n ],\n )\n )\n if HAVE_PYVEX and \"pyvex\" not in args.skip:\n benchmarks.extend(\n gen_benchmarks_from_configurations(\n \"pyvex Lift\",\n benchmark_pyvex,\n [\n {},\n {\"opt_level\": -1},\n {\"opt_level\": 0},\n {\"skip_stmts\": True},\n {\"collect_data_refs\": True},\n ],\n )\n )\n if not benchmarks:\n log.error(\"No benchmarks to run. Install pypcode to run a benchmark.\")\n sys.exit(1)\n\n log.info(\"Using blocks from binary '%s' for benchmarking\", args.binary)\n blocks = get_blocks(args.binary)\n num_blocks = len(blocks)\n\n # Handle reduced block sampling\n assert 0 < args.coverage <= 1, \"Specified coverage percentage not in range (0, 1]\"\n if args.coverage < 1:\n blocks = random.choices(blocks, k=int(num_blocks * args.coverage))\n num_blocks = len(blocks)\n\n if num_blocks == 0:\n log.error(\"No blocks included in benchmark!\")\n sys.exit(1)\n\n blocks_total_size = sum(len(block.data) for block in blocks)\n log.info(\"Benchmark includes %d blocks totaling %.1f KiB\", num_blocks, blocks_total_size / 1024)\n\n gc.collect()\n results: list[tuple[str, BenchmarkResult]] = []\n gc.disable()\n for name, benchmark in benchmarks:\n log.info(\"Benchmarking %s performance...\", name)\n results.append((name, benchmark(blocks)))\n gc.enable()\n\n rows = [[\"Benchmark\", \"Startup ms\", \"Process s\", \"KiB/s\", \"kBlock/s\", \"us/Block\"]]\n num_cols = len(rows[0])\n\n for name, result in results:\n rows.append(\n [\n name,\n f\"{result.startup_duration * 1000:.3f}\",\n f\"{result.translation_duration:.3f}\",\n f\"{(blocks_total_size / result.translation_duration) / 1024:.2f}\",\n f\"{num_blocks / result.translation_duration / 1000:.2f}\",\n f\"{result.translation_duration / num_blocks * 1000000:.3f}\",\n ]\n )\n\n col_widths = [max(len(row[c]) for row in rows) for c in range(num_cols)]\n row = rows[0]\n header = \" | \".join(row[c].ljust(col_widths[c]) for c in range(num_cols))\n log.info(\"-\" * len(header))\n log.info(\"%s\", header)\n log.info(\"-\" * len(header))\n for row in rows[1:]:\n log.info(\"%s\", \" | \".join(row[c].ljust(col_widths[c]) for c in range(num_cols)))\n\n if args.csv:\n with open(args.csv, \"w\", encoding=\"utf-8\") as f:\n writer = csv.writer(f)\n for row in rows:\n writer.writerow(row)\n\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": "scripts/sleigh_download.sh", "content": "#!/bin/bash\nset -e\nset -x\n\nTAG=12.0.2\nGHIDRA_SRC_DIR=ghidra_src_${TAG}\ngit clone --depth=1 -b Ghidra_${TAG}_build https://github.com/NationalSecurityAgency/ghidra.git ${GHIDRA_SRC_DIR}\n\n# We just need Makefile and $(LIBSLA_SOURCE) defined inside Makefile. Do it this\n# way to make sure we stay up to date with the list of required files.\nSLEIGH_SRC_DIR=sleigh\npushd ${GHIDRA_SRC_DIR}/Ghidra/Features/Decompiler/src/decompile/cpp/\n\n# Touch fake dependency files recently removed upstream. Not having these triggers build steps.\nmkdir -p com_opt com_dbg\ntouch com_opt/depend com_dbg/depend\n\necho -e \"$SLEIGH_SRC_DIR:\\n\\tmkdir -p $SLEIGH_SRC_DIR\\n\\tcp \\$(LIBSLA_SOURCE) Makefile $SLEIGH_SRC_DIR\" >> Makefile\nmake $SLEIGH_SRC_DIR\nSLEIGH_SRC_DIR=${PWD}/${SLEIGH_SRC_DIR}\npopd\n\nmkdir ${TAG}\nmv $SLEIGH_SRC_DIR ${TAG}\nmv ${GHIDRA_SRC_DIR}/Ghidra/Processors ${TAG}/processors\n" }, { "path": "setup.py", "content": "#!/usr/bin/env python3\nimport os\nfrom pathlib import Path\nimport platform\nimport shutil\nimport struct\nimport subprocess\nimport sys\nfrom setuptools import setup\nfrom setuptools.command.build_ext import build_ext\n\n\nclass BuildExtension(build_ext):\n \"\"\"\n Runs cmake to build the pypcode_native extension, sleigh binary, and runs sleigh to build .sla files.\n \"\"\"\n\n def run(self):\n try:\n subprocess.check_output([\"cmake\", \"--version\"])\n except OSError as exc:\n raise RuntimeError(\"Please install CMake to build\") from exc\n\n cross_compiling_for_macos_arm64 = (\n platform.system() == \"Darwin\" and platform.machine() == \"x86_64\" and \"arm64\" in os.getenv(\"ARCHFLAGS\", \"\")\n )\n cross_compiling_for_macos_amd64 = (\n platform.system() == \"Darwin\" and platform.machine() != \"x86_64\" and \"x86_64\" in os.getenv(\"ARCHFLAGS\", \"\")\n )\n cross_compiling = cross_compiling_for_macos_arm64 or cross_compiling_for_macos_amd64\n\n root_dir = Path(__file__).parent.absolute()\n target_build_dir = root_dir / \"build\" / \"native\"\n host_build_dir = target_build_dir / \"host\"\n install_pkg_root_dir = (root_dir if self.inplace else Path(self.build_lib).absolute()) / \"pypcode\"\n install_pkg_bin_dir = install_pkg_root_dir / \"bin\"\n host_bin_root_dir = host_build_dir if cross_compiling else install_pkg_bin_dir\n sleigh_filename = \"sleigh\" + (\".exe\" if platform.system() == \"Windows\" else \"\")\n sleigh_bin = host_bin_root_dir / sleigh_filename\n specfiles_dir = install_pkg_root_dir / \"processors\"\n\n # Build sleigh and pypcode_native extension\n cmake_config_args = [\n f\"-DCMAKE_INSTALL_PREFIX={install_pkg_root_dir}\",\n f\"-DPython_EXECUTABLE={sys.executable}\",\n ]\n cmake_build_args = []\n if platform.system() == \"Windows\":\n is_64b = struct.calcsize(\"P\") * 8 == 64\n cmake_config_args += [\"-A\", \"x64\" if is_64b else \"Win32\"]\n cmake_build_args += [\"--config\", \"Release\"]\n\n target_cmake_config_args = cmake_config_args[::]\n if cross_compiling:\n target_cmake_config_args += [\n \"-DCMAKE_OSX_DEPLOYMENT_TARGET=10.14\",\n \"-DCMAKE_OSX_ARCHITECTURES=\" + os.getenv(\"ARCHFLAGS\"),\n ]\n subprocess.check_call([\"cmake\", \"-S\", \".\", \"-B\", target_build_dir] + target_cmake_config_args, cwd=root_dir)\n subprocess.check_call(\n [\"cmake\", \"--build\", target_build_dir, \"--parallel\", \"--verbose\"] + cmake_build_args,\n cwd=root_dir,\n )\n\n if cross_compiling:\n # Also build a host version of sleigh to process .sla files\n host_cmake_config_args = cmake_config_args\n subprocess.check_call([\"cmake\", \"-S\", \".\", \"-B\", host_build_dir] + host_cmake_config_args, cwd=root_dir)\n subprocess.check_call(\n [\"cmake\", \"--build\", host_build_dir, \"--parallel\", \"--verbose\", \"--target\", \"sleigh\"]\n + cmake_build_args,\n cwd=root_dir,\n )\n\n # Install extension and sleigh binary into target package\n if cross_compiling:\n # Note: Manually install because cmake install step may refuse to install binaries for foreign architectures\n install_pkg_bin_dir.mkdir(exist_ok=True)\n ext_path = next(target_build_dir.glob(\"pypcode_native.*\"))\n shutil.copy(target_build_dir / sleigh_filename, install_pkg_bin_dir / sleigh_filename)\n shutil.copy(ext_path, install_pkg_root_dir / ext_path.name)\n else:\n subprocess.check_call([\"cmake\", \"--install\", target_build_dir], cwd=root_dir)\n\n # Build sla files\n subprocess.check_call([sleigh_bin, \"-a\", specfiles_dir])\n\n\ndef add_pkg_data_dirs(pkg, dirs):\n pkg_data = []\n for d in dirs:\n for root, _, files in os.walk(os.path.join(pkg, d)):\n r = os.path.relpath(root, pkg)\n pkg_data.extend([os.path.join(r, f) for f in files])\n return pkg_data\n\n\nsetup(\n package_data={\n \"pypcode\": add_pkg_data_dirs(\"pypcode\", [\"bin\", \"docs\", \"processors\"]) + [\"py.typed\", \"pypcode_native.pyi\"]\n },\n cmdclass={\"build_ext\": BuildExtension},\n)\n" }, { "path": "tests/test_cli.py", "content": "#!/usr/bin/env python3\n# pylint:disable=no-self-use\n\nimport unittest\nimport base64\nimport tempfile\nimport sys\nimport os\nimport io\nfrom unittest import mock\n\nfrom pypcode.__main__ import main\n\n\ndef run_cli(*args):\n with mock.patch(\"sys.argv\", [sys.executable, *args]), mock.patch(\"sys.stdout\", new=io.StringIO()) as fake_out:\n try:\n main()\n except SystemExit:\n pass\n return fake_out.getvalue()\n\n\nclass TestCli(unittest.TestCase):\n \"\"\"\n Test the pypcode module command line interface\n \"\"\"\n\n def test_language_list(self):\n output = run_cli(\"-l\")\n assert \"x86:LE:64:default\" in output\n\n def test_language_suggestions(self):\n output = run_cli(\"x86\", \"_\")\n assert 'Language \"x86\" not found.' in output\n assert \"Suggestions:\" in output\n assert \"x86:LE:32:default\" in output\n assert \"x86:LE:64:default\" in output\n\n def test_language_no_suggestions(self):\n output = run_cli(\"xyz\", \"_\")\n assert \"Suggestions:\" not in output\n\n def test_translate(self):\n with tempfile.NamedTemporaryFile(delete=False) as tf:\n tf.write(base64.b64decode(\"McA5xnYRSInBg+EfigwKMAwHSP/A6+vD\"))\n tf.close()\n path = tf.name\n\n try:\n output = run_cli(\"x86:LE:64:default\", path)\n assert \"0x17/1: RET\" in output\n finally:\n os.unlink(path)\n\n def test_failed_translation(self):\n with tempfile.NamedTemporaryFile(delete=False) as tf:\n tf.write(b\"\\x40\\x40\")\n tf.close()\n path = tf.name\n\n try:\n output = run_cli(\"x86:LE:64:default\", path)\n assert \"An error occurred\" in output\n finally:\n os.unlink(path)\n\n\nif __name__ == \"__main__\":\n unittest.main()\n" }, { "path": "tests/test_pypcode.py", "content": "#!/usr/bin/env python3\n# pylint:disable=no-self-use\n\nimport gc\nimport logging\nfrom unittest import main, TestCase\nfrom unittest.mock import create_autospec\nfrom typing import cast\n\nfrom pypcode import (\n AddrSpace,\n Arch,\n ArchLanguage,\n BadDataError,\n Context,\n LowlevelError,\n OpCode,\n PcodeOp,\n TranslateFlags,\n Translation,\n UnimplError,\n Varnode,\n)\nfrom pypcode.printing import OpFormat, PcodePrettyPrinter\n\n# logging.basicConfig(level=logging.DEBUG)\nlog = logging.getLogger(__name__)\n\n\ndef get_imarks(translation: Translation) -> list[PcodeOp]:\n return [op for op in translation.ops if op.opcode == OpCode.IMARK]\n\n\nclass ContextTests(TestCase):\n \"\"\"\n Basic Context tests\n \"\"\"\n\n def tearDown(self):\n gc.collect()\n\n def test_bad_context_language_type(self):\n with self.assertRaises(TypeError):\n Context(1234)\n\n def test_can_create_all_language_contexts(self):\n for arch in Arch.enumerate():\n for lang in arch.languages:\n with self.subTest(lang=lang.id):\n log.debug(\"Creating context for %s\", lang.id)\n Context(lang)\n\n def test_context_creation_failure(self):\n lang = ArchLanguage.from_id(\"x86:LE:64:default\")\n bad_lang = ArchLanguage(\"/bad/arch/path\", lang.ldef)\n with self.assertRaises(LowlevelError):\n Context(bad_lang)\n\n def test_context_premature_release(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xc3\")\n del ctx\n log.debug(\"Should not crash: %d\", len(tx.ops[0].inputs[0].space.name))\n del tx\n log.debug(\"--\")\n\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xc3\")\n op = tx.ops[0]\n del tx # Should not be released\n del ctx # Should not be released while op is alive\n log.debug(\"Should not crash: %d\", len(op.inputs[0].space.name))\n del op # Now ctx, tx can be released\n log.debug(\"--\")\n\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xc3\")\n vn = tx.ops[0].inputs[0]\n del tx\n del ctx\n log.debug(\"Should not crash: %d\", len(vn.space.name))\n del vn # Now ctx, tx can be released\n log.debug(\"--\")\n\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xc3\")\n space = tx.ops[0].inputs[0].space\n del tx\n del ctx\n log.debug(\"Should not crash: %d\", len(space.name))\n del space # Now ctx, tx can be released. Space is managed by context, so C++ obj should not be released.\n log.debug(\"--\")\n\n\nclass RegistersTests(TestCase):\n \"\"\"\n Context register lookup tests\n \"\"\"\n\n def test_registers(self):\n ctx = Context(\"x86:LE:64:default\")\n assert \"RAX\" in ctx.registers\n\n def test_getRegisterName(self):\n ctx = Context(\"x86:LE:64:default\")\n ri = ctx.registers[\"RAX\"]\n assert ctx.getRegisterName(ri.space, ri.offset, ri.size) == \"RAX\"\n\n\nclass AddrSpaceTests(TestCase):\n \"\"\"\n AddrSpace tests\n \"\"\"\n\n def test_name(self):\n ctx = Context(\"x86:LE:64:default\")\n assert ctx.translate(b\"\\xeb\\xfe\").ops[1].inputs[0].space.name == \"ram\"\n\n\nclass VarnodeTests(TestCase):\n \"\"\"\n Varnode tests\n \"\"\"\n\n def test_getSpaceFromConst(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x48\\x8b\\x41\\x01\") # mov rax, [rcx + 1]\n assert tx.ops[2].inputs[0].getSpaceFromConst().name == \"ram\"\n\n def test_getRegisterName(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x48\\x8b\\x41\\x01\") # mov rax, [rcx + 1]\n assert tx.ops[1].inputs[0].getRegisterName() == \"RCX\"\n assert tx.ops[1].inputs[1].getRegisterName() == \"\"\n\n def test_getUserDefinedOpName(self):\n ctx = Context(\"AARCH64:LE:64:AppleSilicon\")\n ctx.setVariableDefault(\"ShowPAC\", 1)\n ctx.setVariableDefault(\"PAC_clobber\", 1)\n\n tx = ctx.translate(b\"\\x7f\\x23\\x03\\xd5\") # pacibsp\n\n # x30 = pacib(x30, sp)\n assert tx.ops[1].opcode == OpCode.CALLOTHER\n assert tx.ops[1].output.getRegisterName() == \"x30\"\n assert tx.ops[1].inputs[0].getUserDefinedOpName() == \"pacib\"\n assert tx.ops[1].inputs[1].getRegisterName() == \"x30\"\n assert tx.ops[1].inputs[2].getRegisterName() == \"sp\"\n\n\nclass DisassembleTests(TestCase):\n \"\"\"\n Context::disassemble tests\n \"\"\"\n\n def test_disassemble(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\x90\\xeb\\xfe\")\n assert len(dx.instructions) == 2\n ins = dx.instructions[1]\n assert ins.addr.offset == 1\n assert ins.length == 2\n assert ins.mnem == \"JMP\"\n assert ins.body == \"0x1\"\n\n def test_decode_failure(self):\n ctx = Context(\"x86:LE:64:default\")\n with self.assertRaises(BadDataError):\n ctx.disassemble(b\"\\x40\\x40\")\n\n def test_partial_decode_failure(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\xff\\xc0\\x90\\x40\\x40\") # inc eax; nop; bad\n assert len(dx.instructions) == 2\n\n def test_not_cached(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\xeb\\xfe\", 5)\n dx = ctx.disassemble(b\"\\xc3\", 5)\n ins = dx.instructions[0]\n assert ins.addr.offset == 5\n assert ins.length == 1\n assert ins.mnem == \"RET\"\n assert ins.body == \"\"\n\n def test_arg_base_address(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\xeb\\xfe\", 10)\n assert len(dx.instructions) == 1\n assert dx.instructions[0].mnem == \"JMP\"\n assert dx.instructions[0].body == \"0xa\"\n\n def test_arg_offset(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\x90\\xeb\\xfe\", offset=1)\n assert len(dx.instructions) == 1\n\n def test_arg_offset_out_of_range(self):\n ctx = Context(\"x86:LE:64:default\")\n with self.assertRaises(IndexError):\n ctx.disassemble(b\"\\x90\\xeb\\xfe\", offset=3)\n\n def test_arg_max_bytes(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\x90\\xeb\\xfe\", max_bytes=1)\n assert len(dx.instructions) == 1\n\n def test_arg_max_instructions(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\x90\\xeb\\xfe\", max_instructions=1)\n assert len(dx.instructions) == 1\n\n def test_pretty_printing(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\x48\\x31\\xc0\\xc3\")\n assert \"0x0/3: XOR RAX,RAX\" in str(dx)\n assert \"0x3/1: RET\" in str(dx)\n\n\nclass TranslateTests(TestCase):\n \"\"\"\n Context::translate tests\n \"\"\"\n\n def test_translate(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x48\\x35\\x78\\x56\\x34\\x12\\xc3\")\n assert len(get_imarks(tx)) == 2\n\n def test_decode_failure(self):\n ctx = Context(\"x86:LE:64:default\")\n with self.assertRaises(BadDataError):\n ctx.translate(b\"\\x40\\x40\")\n\n def test_partial_decode_failure(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xff\\xc0\\x40\\x40\") # inc eax; bad\n assert len(get_imarks(tx)) == 1\n\n def test_unimpl_failure(self):\n ctx = Context(\"Toy:BE:32:default\")\n with self.assertRaises(UnimplError):\n ctx.translate(b\"\\xa8\\x00\")\n\n def test_partial_unimpl_failure(self):\n ctx = Context(\"Toy:BE:32:default\")\n tx = ctx.translate(b\"\\xd0\\x00\\xa8\\x00\") # and r0, r0; unimpl\n assert len(get_imarks(tx)) == 1\n\n def test_not_cached(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xeb\\xfe\", 5)\n tx = ctx.translate(b\"\\xc3\", 5)\n assert tx.ops[-1].opcode == OpCode.RETURN\n\n def test_translate_and_disassemble_not_cached(self):\n ctx = Context(\"x86:LE:64:default\")\n dx = ctx.disassemble(b\"\\xeb\\xfe\", 5)\n tx = ctx.translate(b\"\\xc3\", 5)\n assert tx.ops[-1].opcode == OpCode.RETURN\n\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xc3\", 5)\n dx = ctx.disassemble(b\"\\xeb\\xfe\", 5)\n assert len(dx.instructions) == 1\n ins = dx.instructions[0]\n assert ins.addr.offset == 5\n assert ins.length == 2\n assert ins.mnem == \"JMP\"\n assert ins.body == \"0x5\"\n\n def test_arg_base_address(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\xeb\\xfe\", 10) # jmp $\n assert len(tx.ops) == 2\n assert len(tx.ops[0].inputs) == 1 # Check just one instruction decoded\n assert tx.ops[0].inputs[0].offset == 10 # Check IMARK\n assert tx.ops[1].inputs[0].offset == 10 # Check jump target\n\n def test_arg_offset(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x90\\x90\\xeb\\xfe\", offset=2) # nop; nop; jmp $\n assert len(get_imarks(tx)) == 1\n\n def test_arg_offset_out_of_range(self):\n ctx = Context(\"x86:LE:64:default\")\n with self.assertRaises(IndexError):\n ctx.translate(b\"\\x90\\x90\\xeb\\xfe\", offset=10) # nop; nop; jmp $\n\n def test_arg_max_bytes(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x90\\x90\\x90\", max_bytes=1)\n assert len(get_imarks(tx)) == 1\n\n def test_arg_max_instructions(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x90\\x90\\x90\", max_instructions=2)\n assert len(get_imarks(tx)) == 2\n\n def test_arg_flag_bb_terminating(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x90\\xeb\\xfe\\x90\\x90\", flags=TranslateFlags.BB_TERMINATING)\n assert len(get_imarks(tx)) == 2\n\n def test_delay_slot(self):\n ctx = Context(\"MIPS:BE:32:default\")\n tx = ctx.translate(b\"\\x10@\\x00\\x06\\x00 \\x08%\", 0x4009F4)\n imarks = get_imarks(tx)\n assert len(imarks) == 1\n assert len(imarks[0].inputs) == 2\n assert imarks[0].inputs[0].offset == 0x4009F4\n assert imarks[0].inputs[0].size == 4\n assert imarks[0].inputs[1].offset == 0x4009F8\n assert imarks[0].inputs[1].size == 4\n\n def test_pretty_printing(self):\n ctx = Context(\"x86:LE:64:default\")\n tx = ctx.translate(b\"\\x48\\x31\\xc0\")\n assert \"RAX = RAX ^ RAX\" in str(tx)\n\n\nclass PrintingTests(TestCase):\n \"\"\"\n Pretty printing tests.\n \"\"\"\n\n def test_branches(self):\n for opc, output in [\n (OpCode.BRANCH, \"goto ram[123:4]\"),\n (OpCode.BRANCHIND, \"goto [ram[123:4]]\"),\n (OpCode.CALL, \"call ram[123:4]\"),\n (OpCode.CALLIND, \"call [ram[123:4]]\"),\n (OpCode.RETURN, \"return ram[123:4]\"),\n ]:\n vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n vn.space.name = \"ram\"\n vn.offset = 0x123\n vn.size = 4\n\n op = cast(PcodeOp, create_autospec(PcodeOp, instance=True, spec_set=True))\n op.opcode = opc\n op.output = None\n op.inputs = [vn]\n\n assert PcodePrettyPrinter.fmt_op(op) == output\n\n def test_cbranch(self):\n target_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n target_vn.space.name = \"ram\"\n target_vn.offset = 0x456\n target_vn.size = 4\n\n cond_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n cond_vn.space.name = \"ram\"\n cond_vn.offset = 0x123\n cond_vn.size = 1\n\n op = cast(PcodeOp, create_autospec(PcodeOp, instance=True, spec_set=True))\n op.opcode = OpCode.CBRANCH\n op.output = None\n op.inputs = [target_vn, cond_vn]\n\n assert PcodePrettyPrinter.fmt_op(op) == \"if (ram[123:1]) goto ram[456:4]\"\n\n def test_load(self):\n dest_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n dest_vn.space.name = \"ram\"\n dest_vn.offset = 0x123\n dest_vn.size = 1\n\n space = cast(AddrSpace, create_autospec(AddrSpace, instance=True, spec_set=True))\n space.name = \"ram\"\n\n space_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n space_vn.space.name = \"const\"\n space_vn.getSpaceFromConst.return_value = space\n\n offset_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n offset_vn.space.name = \"const\"\n offset_vn.offset = 0x456\n offset_vn.size = 1\n\n op = cast(PcodeOp, create_autospec(PcodeOp, instance=True, spec_set=True))\n op.opcode = OpCode.LOAD\n op.output = dest_vn\n op.inputs = [space_vn, offset_vn]\n\n assert PcodePrettyPrinter.fmt_op(op) == \"ram[123:1] = *[ram]0x456\"\n\n def test_store(self):\n space = cast(AddrSpace, create_autospec(AddrSpace, instance=True, spec_set=True))\n space.name = \"ram\"\n\n space_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n space_vn.space.name = \"const\"\n space_vn.getSpaceFromConst.return_value = space\n\n offset_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n offset_vn.space.name = \"const\"\n offset_vn.offset = 0x123\n offset_vn.size = 1\n\n value_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n value_vn.space.name = \"const\"\n value_vn.offset = 0x456\n value_vn.size = 1\n\n op = cast(PcodeOp, create_autospec(PcodeOp, instance=True, spec_set=True))\n op.opcode = OpCode.STORE\n op.output = None\n op.inputs = [space_vn, offset_vn, value_vn]\n\n assert PcodePrettyPrinter.fmt_op(op) == \"*[ram]0x123 = 0x456\"\n\n def test_callother(self):\n target_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n target_vn.getUserDefinedOpName.return_value = \"udop\"\n\n arg_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n arg_vn.space.name = \"const\"\n arg_vn.offset = 0x456\n arg_vn.size = 1\n\n op = cast(PcodeOp, create_autospec(PcodeOp, instance=True, spec_set=True))\n op.opcode = OpCode.CALLOTHER\n op.output = None\n op.inputs = [target_vn, arg_vn]\n\n assert PcodePrettyPrinter.fmt_op(op) == \"udop(0x456)\"\n\n def test_no_regname(self):\n arg_vn = cast(Varnode, create_autospec(Varnode, instance=True, spec_set=True))\n arg_vn.space.name = \"register\"\n arg_vn.offset = 0x123\n arg_vn.size = 4\n arg_vn.getRegisterName.return_value = None\n assert OpFormat.fmt_vn(arg_vn) == \"register[123:4]\"\n\n\nif __name__ == \"__main__\":\n main()\n" } ]